2006.202.08:02:35.80;Log Opened: Mark IV Field System Version 9.7.7 2006.202.08:02:35.80;location,TSUKUB32,-140.09,36.10,61.0 2006.202.08:02:35.80;horizon1,0.,5.,360. 2006.202.08:02:35.80;antenna,32.0,180.0,180.0,10.0,710.0,5.0,88.0,azel 2006.202.08:02:35.80;equip,k42c/mk4,vlbab,vlbab,mk4,500.10,3,a/d,101,60,20,none,41,1,in,8bit,cdp,3 2006.202.08:02:35.80;drivev11,330,270,no 2006.202.08:02:35.80;drivev12,mvme117,0,11.400,2548.000,152.780,-6.655,0.014,152,10.000,54500 2006.202.08:02:35.80;drivev13,15.000,268,10.000,10.000,10.000 2006.202.08:02:35.80;drivev21,330,270,no 2006.202.08:02:35.80;drivev22,mvme117,0,11.500,2821.000,127.500,-8.640,0.015,152,14.000,54500 2006.202.08:02:35.80;drivev23,15.000,268,10.000,10.000,10.000 2006.202.08:02:35.80;head10,all,all,all,odd,adaptive,no,5.0000,1 2006.202.08:02:35.80;head11,131.5,16.4,-291.0,131.5,16.4,0.8,168.30,168.30 2006.202.08:02:35.80;head12,122.8,13.9,-150.8,122.8,14.7,2.5,167.61,167.61 2006.202.08:02:35.80;head20,all,all,all,odd,adaptive,no,5.0000,1 2006.202.08:02:35.80;head21,145.3,16.1,-209.3,137.2,16.1,58.9,165.28,165.28 2006.202.08:02:35.80;head22,157.5,17.4,-203.7,149.2,16.6,56.5,169.73,169.73 2006.202.08:02:35.80;time,-0.364,101.533,rate 2006.202.08:02:35.80;flagr,200 2006.202.08:02:35.80:" K06203 2006 TSUKUB32 T Ts 2006.202.08:02:35.80:" T TSUKUB32 AZEL .0000 180.0 14 10.0 710.0 180.0 14 5.0 88.0 32.0 Ts 108 2006.202.08:02:35.80:" Ts TSUKUB32 -3957408.75120 3310229.34660 3737494.83600 73452301 2006.202.08:02:35.80:" 108 TSUKUB32 14 17400 2006.202.08:02:35.80:" drudg version 050216 compiled under FS 9.7.07 2006.202.08:02:35.80:" Rack=K4-2/M4 Recorder 1=K5 Recorder 2=none 2006.202.08:02:35.80:exper_initi 2006.202.08:02:35.80&exper_initi/proc_library 2006.202.08:02:35.80&exper_initi/sched_initi 2006.202.08:02:35.80:!2006.203.06:29:50 2006.202.08:02:35.80&proc_library/" k06203 tsukub32 ts 2006.202.08:02:35.80&proc_library/" drudg version 050216 compiled under fs 9.7.7 2006.202.08:02:35.80&proc_library/"< k4-2/m4 rack >< k5 recorder 1> 2006.202.08:02:35.80&sched_initi/startcheck 2006.202.08:02:35.80&startcheck/sy=check_fsrun.pl & 2006.202.08:02:35.80&startcheck/" sy=/usr2/oper/temp/chmem.sh >& /dev/null & 2006.202.08:02:52.96;cable 2006.202.08:02:53.07/cable/+6.4462E-03 2006.202.08:03:53.19;cablelong 2006.202.08:03:53.35/cablelong/+6.9967E-03 2006.202.08:03:57.71;cablediff 2006.202.08:03:57.71/cablediff/550.5e-6,+ 2006.202.08:04:51.39;cable 2006.202.08:04:51.54/cable/+6.4468E-03 2006.202.08:04:57.20;wx 2006.202.08:04:57.20/wx/21.11,998.5,100 2006.202.08:05:07.83;"Sky is cloudy. 2006.202.08:05:20.09;xfe 2006.202.08:05:20.18/xfe/off,on,14.5 2006.202.08:05:25.35;clockoff 2006.202.08:05:25.35&clockoff/"gps-fmout=1p 2006.202.08:05:25.35&clockoff/fmout-gps=1p 2006.202.08:05:26.08/fmout-gps/S +4.20E-07 2006.203.06:29:50.00:sy=/usr2/oper/k5/bin/freeze_chk.pl & 2006.203.06:29:50.02:!2006.203.07:19:50 2006.203.07:19:50.00:unstow 2006.203.07:19:50.00&unstow/antenna=e 2006.203.07:19:50.00&unstow/!+10s 2006.203.07:19:50.00&unstow/antenna=m2 2006.203.07:20:02.01:scan_name=203-0730,k06203,60 2006.203.07:20:02.01:source=3c418,203837.03,511912.7,2000.0,ccw 2006.203.07:20:03.14#antcn#PM 1 00019 2005 228 00 22 31 00 2006.203.07:20:03.14#antcn#PM 2 90.0000 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 2006.203.07:20:03.14#antcn#PM 2 -0.0279715 0.0000000 -0.0282214 -0.0241630 -0.0014011 2006.203.07:20:03.14#antcn#PM 3 -0.0059899 0.0042895 -0.0643783 0.0000000 0.0000000 2006.203.07:20:03.14#antcn#PM 4 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.203.07:20:03.14#antcn#PM 5 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.203.07:20:04.14:ready_k5 2006.203.07:20:04.14&ready_k5/obsinfo=st 2006.203.07:20:04.14&ready_k5/autoobs=1 2006.203.07:20:04.14&ready_k5/autoobs=2 2006.203.07:20:04.14&ready_k5/autoobs=3 2006.203.07:20:04.14&ready_k5/autoobs=4 2006.203.07:20:04.14&ready_k5/obsinfo 2006.203.07:20:04.14#flagr#flagr/antenna,new-source 2006.203.07:20:04.14/obsinfo=st/error_log.tmp was not found (or not removed). 2006.203.07:20:08.11/autoobs//k5ts1/ autoobs started! 2006.203.07:20:11.85/autoobs//k5ts2/ autoobs started! 2006.203.07:20:15.74/autoobs//k5ts3/ autoobs started! 2006.203.07:20:19.14/autoobs//k5ts4/ autoobs started! 2006.203.07:20:19.17/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.203.07:20:19.17:4f8m12a=1 2006.203.07:20:19.17&4f8m12a/xlog=on 2006.203.07:20:19.17&4f8m12a/echo=on 2006.203.07:20:19.17&4f8m12a/pcalon 2006.203.07:20:19.17&4f8m12a/"tpicd=stop 2006.203.07:20:19.17&4f8m12a/vc4f8 2006.203.07:20:19.17&4f8m12a/ifd4f 2006.203.07:20:19.17&4f8m12a/"form=m,16.000,1:2 2006.203.07:20:19.17&4f8m12a/"tpicd 2006.203.07:20:19.17&4f8m12a/echo=off 2006.203.07:20:19.17&4f8m12a/xlog=off 2006.203.07:20:19.17$4f8m12a/echo=on 2006.203.07:20:19.17$4f8m12a/pcalon 2006.203.07:20:19.17&pcalon/"no phase cal control is implemented here 2006.203.07:20:19.17$pcalon/"no phase cal control is implemented here 2006.203.07:20:19.17$4f8m12a/"tpicd=stop 2006.203.07:20:19.17$4f8m12a/vc4f8 2006.203.07:20:19.17&vc4f8/valo=1,532.99 2006.203.07:20:19.17&vc4f8/va=1,8 2006.203.07:20:19.17&vc4f8/valo=2,572.99 2006.203.07:20:19.17&vc4f8/va=2,7 2006.203.07:20:19.17&vc4f8/valo=3,672.99 2006.203.07:20:19.17&vc4f8/va=3,8 2006.203.07:20:19.17&vc4f8/valo=4,832.99 2006.203.07:20:19.17&vc4f8/va=4,7 2006.203.07:20:19.17&vc4f8/valo=5,652.99 2006.203.07:20:19.17&vc4f8/va=5,7 2006.203.07:20:19.17&vc4f8/valo=6,772.99 2006.203.07:20:19.17&vc4f8/va=6,6 2006.203.07:20:19.17&vc4f8/valo=7,832.99 2006.203.07:20:19.17&vc4f8/va=7,7 2006.203.07:20:19.17&vc4f8/valo=8,852.99 2006.203.07:20:19.17&vc4f8/va=8,6 2006.203.07:20:19.17&vc4f8/vblo=1,632.99 2006.203.07:20:19.17&vc4f8/vb=1,4 2006.203.07:20:19.17&vc4f8/vblo=2,640.99 2006.203.07:20:19.17&vc4f8/vb=2,4 2006.203.07:20:19.17&vc4f8/vblo=3,656.99 2006.203.07:20:19.17&vc4f8/vb=3,4 2006.203.07:20:19.17&vc4f8/vblo=4,712.99 2006.203.07:20:19.17&vc4f8/vb=4,4 2006.203.07:20:19.17&vc4f8/vblo=5,744.99 2006.203.07:20:19.17&vc4f8/vb=5,3 2006.203.07:20:19.17&vc4f8/vblo=6,752.99 2006.203.07:20:19.17&vc4f8/vb=6,4 2006.203.07:20:19.17&vc4f8/vabw=wide 2006.203.07:20:19.17&vc4f8/vbbw=wide 2006.203.07:20:19.17$vc4f8/valo=1,532.99 2006.203.07:20:19.21#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.203.07:20:19.21#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.203.07:20:19.21#ibcon#ireg 17 cls_cnt 0 2006.203.07:20:19.21#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.203.07:20:19.21#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.203.07:20:19.21#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.203.07:20:19.21#ibcon#enter wrdev, iclass 39, count 0 2006.203.07:20:19.21#ibcon#first serial, iclass 39, count 0 2006.203.07:20:19.21#ibcon#enter sib2, iclass 39, count 0 2006.203.07:20:19.21#ibcon#flushed, iclass 39, count 0 2006.203.07:20:19.21#ibcon#about to write, iclass 39, count 0 2006.203.07:20:19.21#ibcon#wrote, iclass 39, count 0 2006.203.07:20:19.21#ibcon#about to read 3, iclass 39, count 0 2006.203.07:20:19.23#ibcon#read 3, iclass 39, count 0 2006.203.07:20:19.23#ibcon#about to read 4, iclass 39, count 0 2006.203.07:20:19.23#ibcon#read 4, iclass 39, count 0 2006.203.07:20:19.23#ibcon#about to read 5, iclass 39, count 0 2006.203.07:20:19.23#ibcon#read 5, iclass 39, count 0 2006.203.07:20:19.23#ibcon#about to read 6, iclass 39, count 0 2006.203.07:20:19.23#ibcon#read 6, iclass 39, count 0 2006.203.07:20:19.23#ibcon#end of sib2, iclass 39, count 0 2006.203.07:20:19.23#ibcon#*mode == 0, iclass 39, count 0 2006.203.07:20:19.23#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.203.07:20:19.23#ibcon#[26=FRQ=01,532.99\r\n] 2006.203.07:20:19.23#ibcon#*before write, iclass 39, count 0 2006.203.07:20:19.23#ibcon#enter sib2, iclass 39, count 0 2006.203.07:20:19.23#ibcon#flushed, iclass 39, count 0 2006.203.07:20:19.23#ibcon#about to write, iclass 39, count 0 2006.203.07:20:19.23#ibcon#wrote, iclass 39, count 0 2006.203.07:20:19.23#ibcon#about to read 3, iclass 39, count 0 2006.203.07:20:19.29#ibcon#read 3, iclass 39, count 0 2006.203.07:20:19.29#ibcon#about to read 4, iclass 39, count 0 2006.203.07:20:19.29#ibcon#read 4, iclass 39, count 0 2006.203.07:20:19.29#ibcon#about to read 5, iclass 39, count 0 2006.203.07:20:19.29#ibcon#read 5, iclass 39, count 0 2006.203.07:20:19.29#ibcon#about to read 6, iclass 39, count 0 2006.203.07:20:19.29#ibcon#read 6, iclass 39, count 0 2006.203.07:20:19.29#ibcon#end of sib2, iclass 39, count 0 2006.203.07:20:19.29#ibcon#*after write, iclass 39, count 0 2006.203.07:20:19.29#ibcon#*before return 0, iclass 39, count 0 2006.203.07:20:19.29#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.203.07:20:19.29#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.203.07:20:19.29#ibcon#about to clear, iclass 39 cls_cnt 0 2006.203.07:20:19.29#ibcon#cleared, iclass 39 cls_cnt 0 2006.203.07:20:19.29$vc4f8/va=1,8 2006.203.07:20:19.29#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.203.07:20:19.29#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.203.07:20:19.29#ibcon#ireg 11 cls_cnt 2 2006.203.07:20:19.29#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.203.07:20:19.29#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.203.07:20:19.29#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.203.07:20:19.29#ibcon#enter wrdev, iclass 3, count 2 2006.203.07:20:19.29#ibcon#first serial, iclass 3, count 2 2006.203.07:20:19.29#ibcon#enter sib2, iclass 3, count 2 2006.203.07:20:19.29#ibcon#flushed, iclass 3, count 2 2006.203.07:20:19.29#ibcon#about to write, iclass 3, count 2 2006.203.07:20:19.29#ibcon#wrote, iclass 3, count 2 2006.203.07:20:19.29#ibcon#about to read 3, iclass 3, count 2 2006.203.07:20:19.31#ibcon#read 3, iclass 3, count 2 2006.203.07:20:19.31#ibcon#about to read 4, iclass 3, count 2 2006.203.07:20:19.31#ibcon#read 4, iclass 3, count 2 2006.203.07:20:19.31#ibcon#about to read 5, iclass 3, count 2 2006.203.07:20:19.31#ibcon#read 5, iclass 3, count 2 2006.203.07:20:19.31#ibcon#about to read 6, iclass 3, count 2 2006.203.07:20:19.31#ibcon#read 6, iclass 3, count 2 2006.203.07:20:19.31#ibcon#end of sib2, iclass 3, count 2 2006.203.07:20:19.31#ibcon#*mode == 0, iclass 3, count 2 2006.203.07:20:19.31#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.203.07:20:19.31#ibcon#[25=AT01-08\r\n] 2006.203.07:20:19.31#ibcon#*before write, iclass 3, count 2 2006.203.07:20:19.31#ibcon#enter sib2, iclass 3, count 2 2006.203.07:20:19.31#ibcon#flushed, iclass 3, count 2 2006.203.07:20:19.31#ibcon#about to write, iclass 3, count 2 2006.203.07:20:19.31#ibcon#wrote, iclass 3, count 2 2006.203.07:20:19.31#ibcon#about to read 3, iclass 3, count 2 2006.203.07:20:19.35#ibcon#read 3, iclass 3, count 2 2006.203.07:20:19.35#ibcon#about to read 4, iclass 3, count 2 2006.203.07:20:19.35#ibcon#read 4, iclass 3, count 2 2006.203.07:20:19.35#ibcon#about to read 5, iclass 3, count 2 2006.203.07:20:19.35#ibcon#read 5, iclass 3, count 2 2006.203.07:20:19.35#ibcon#about to read 6, iclass 3, count 2 2006.203.07:20:19.35#ibcon#read 6, iclass 3, count 2 2006.203.07:20:19.35#ibcon#end of sib2, iclass 3, count 2 2006.203.07:20:19.35#ibcon#*after write, iclass 3, count 2 2006.203.07:20:19.35#ibcon#*before return 0, iclass 3, count 2 2006.203.07:20:19.35#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.203.07:20:19.35#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.203.07:20:19.35#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.203.07:20:19.35#ibcon#ireg 7 cls_cnt 0 2006.203.07:20:19.35#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.203.07:20:19.47#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.203.07:20:19.47#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.203.07:20:19.47#ibcon#enter wrdev, iclass 3, count 0 2006.203.07:20:19.47#ibcon#first serial, iclass 3, count 0 2006.203.07:20:19.47#ibcon#enter sib2, iclass 3, count 0 2006.203.07:20:19.47#ibcon#flushed, iclass 3, count 0 2006.203.07:20:19.47#ibcon#about to write, iclass 3, count 0 2006.203.07:20:19.47#ibcon#wrote, iclass 3, count 0 2006.203.07:20:19.47#ibcon#about to read 3, iclass 3, count 0 2006.203.07:20:19.49#ibcon#read 3, iclass 3, count 0 2006.203.07:20:19.49#ibcon#about to read 4, iclass 3, count 0 2006.203.07:20:19.49#ibcon#read 4, iclass 3, count 0 2006.203.07:20:19.49#ibcon#about to read 5, iclass 3, count 0 2006.203.07:20:19.49#ibcon#read 5, iclass 3, count 0 2006.203.07:20:19.49#ibcon#about to read 6, iclass 3, count 0 2006.203.07:20:19.49#ibcon#read 6, iclass 3, count 0 2006.203.07:20:19.49#ibcon#end of sib2, iclass 3, count 0 2006.203.07:20:19.49#ibcon#*mode == 0, iclass 3, count 0 2006.203.07:20:19.49#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.203.07:20:19.49#ibcon#[25=USB\r\n] 2006.203.07:20:19.49#ibcon#*before write, iclass 3, count 0 2006.203.07:20:19.49#ibcon#enter sib2, iclass 3, count 0 2006.203.07:20:19.49#ibcon#flushed, iclass 3, count 0 2006.203.07:20:19.49#ibcon#about to write, iclass 3, count 0 2006.203.07:20:19.49#ibcon#wrote, iclass 3, count 0 2006.203.07:20:19.49#ibcon#about to read 3, iclass 3, count 0 2006.203.07:20:19.52#ibcon#read 3, iclass 3, count 0 2006.203.07:20:19.52#ibcon#about to read 4, iclass 3, count 0 2006.203.07:20:19.52#ibcon#read 4, iclass 3, count 0 2006.203.07:20:19.52#ibcon#about to read 5, iclass 3, count 0 2006.203.07:20:19.52#ibcon#read 5, iclass 3, count 0 2006.203.07:20:19.52#ibcon#about to read 6, iclass 3, count 0 2006.203.07:20:19.52#ibcon#read 6, iclass 3, count 0 2006.203.07:20:19.52#ibcon#end of sib2, iclass 3, count 0 2006.203.07:20:19.52#ibcon#*after write, iclass 3, count 0 2006.203.07:20:19.52#ibcon#*before return 0, iclass 3, count 0 2006.203.07:20:19.52#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.203.07:20:19.52#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.203.07:20:19.52#ibcon#about to clear, iclass 3 cls_cnt 0 2006.203.07:20:19.52#ibcon#cleared, iclass 3 cls_cnt 0 2006.203.07:20:19.52$vc4f8/valo=2,572.99 2006.203.07:20:19.52#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.203.07:20:19.52#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.203.07:20:19.52#ibcon#ireg 17 cls_cnt 0 2006.203.07:20:19.52#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.203.07:20:19.52#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.203.07:20:19.52#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.203.07:20:19.52#ibcon#enter wrdev, iclass 5, count 0 2006.203.07:20:19.52#ibcon#first serial, iclass 5, count 0 2006.203.07:20:19.52#ibcon#enter sib2, iclass 5, count 0 2006.203.07:20:19.52#ibcon#flushed, iclass 5, count 0 2006.203.07:20:19.52#ibcon#about to write, iclass 5, count 0 2006.203.07:20:19.52#ibcon#wrote, iclass 5, count 0 2006.203.07:20:19.52#ibcon#about to read 3, iclass 5, count 0 2006.203.07:20:19.54#ibcon#read 3, iclass 5, count 0 2006.203.07:20:19.54#ibcon#about to read 4, iclass 5, count 0 2006.203.07:20:19.54#ibcon#read 4, iclass 5, count 0 2006.203.07:20:19.54#ibcon#about to read 5, iclass 5, count 0 2006.203.07:20:19.54#ibcon#read 5, iclass 5, count 0 2006.203.07:20:19.54#ibcon#about to read 6, iclass 5, count 0 2006.203.07:20:19.54#ibcon#read 6, iclass 5, count 0 2006.203.07:20:19.54#ibcon#end of sib2, iclass 5, count 0 2006.203.07:20:19.54#ibcon#*mode == 0, iclass 5, count 0 2006.203.07:20:19.54#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.203.07:20:19.54#ibcon#[26=FRQ=02,572.99\r\n] 2006.203.07:20:19.54#ibcon#*before write, iclass 5, count 0 2006.203.07:20:19.54#ibcon#enter sib2, iclass 5, count 0 2006.203.07:20:19.54#ibcon#flushed, iclass 5, count 0 2006.203.07:20:19.54#ibcon#about to write, iclass 5, count 0 2006.203.07:20:19.54#ibcon#wrote, iclass 5, count 0 2006.203.07:20:19.54#ibcon#about to read 3, iclass 5, count 0 2006.203.07:20:19.59#ibcon#read 3, iclass 5, count 0 2006.203.07:20:19.59#ibcon#about to read 4, iclass 5, count 0 2006.203.07:20:19.59#ibcon#read 4, iclass 5, count 0 2006.203.07:20:19.59#ibcon#about to read 5, iclass 5, count 0 2006.203.07:20:19.59#ibcon#read 5, iclass 5, count 0 2006.203.07:20:19.59#ibcon#about to read 6, iclass 5, count 0 2006.203.07:20:19.59#ibcon#read 6, iclass 5, count 0 2006.203.07:20:19.59#ibcon#end of sib2, iclass 5, count 0 2006.203.07:20:19.59#ibcon#*after write, iclass 5, count 0 2006.203.07:20:19.59#ibcon#*before return 0, iclass 5, count 0 2006.203.07:20:19.59#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.203.07:20:19.59#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.203.07:20:19.59#ibcon#about to clear, iclass 5 cls_cnt 0 2006.203.07:20:19.59#ibcon#cleared, iclass 5 cls_cnt 0 2006.203.07:20:19.59$vc4f8/va=2,7 2006.203.07:20:19.59#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.203.07:20:19.59#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.203.07:20:19.59#ibcon#ireg 11 cls_cnt 2 2006.203.07:20:19.59#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.203.07:20:19.64#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.203.07:20:19.64#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.203.07:20:19.64#ibcon#enter wrdev, iclass 7, count 2 2006.203.07:20:19.64#ibcon#first serial, iclass 7, count 2 2006.203.07:20:19.64#ibcon#enter sib2, iclass 7, count 2 2006.203.07:20:19.64#ibcon#flushed, iclass 7, count 2 2006.203.07:20:19.64#ibcon#about to write, iclass 7, count 2 2006.203.07:20:19.64#ibcon#wrote, iclass 7, count 2 2006.203.07:20:19.64#ibcon#about to read 3, iclass 7, count 2 2006.203.07:20:19.66#ibcon#read 3, iclass 7, count 2 2006.203.07:20:19.66#ibcon#about to read 4, iclass 7, count 2 2006.203.07:20:19.66#ibcon#read 4, iclass 7, count 2 2006.203.07:20:19.66#ibcon#about to read 5, iclass 7, count 2 2006.203.07:20:19.66#ibcon#read 5, iclass 7, count 2 2006.203.07:20:19.66#ibcon#about to read 6, iclass 7, count 2 2006.203.07:20:19.66#ibcon#read 6, iclass 7, count 2 2006.203.07:20:19.66#ibcon#end of sib2, iclass 7, count 2 2006.203.07:20:19.66#ibcon#*mode == 0, iclass 7, count 2 2006.203.07:20:19.66#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.203.07:20:19.66#ibcon#[25=AT02-07\r\n] 2006.203.07:20:19.66#ibcon#*before write, iclass 7, count 2 2006.203.07:20:19.66#ibcon#enter sib2, iclass 7, count 2 2006.203.07:20:19.66#ibcon#flushed, iclass 7, count 2 2006.203.07:20:19.66#ibcon#about to write, iclass 7, count 2 2006.203.07:20:19.66#ibcon#wrote, iclass 7, count 2 2006.203.07:20:19.66#ibcon#about to read 3, iclass 7, count 2 2006.203.07:20:19.69#ibcon#read 3, iclass 7, count 2 2006.203.07:20:19.69#ibcon#about to read 4, iclass 7, count 2 2006.203.07:20:19.69#ibcon#read 4, iclass 7, count 2 2006.203.07:20:19.69#ibcon#about to read 5, iclass 7, count 2 2006.203.07:20:19.69#ibcon#read 5, iclass 7, count 2 2006.203.07:20:19.69#ibcon#about to read 6, iclass 7, count 2 2006.203.07:20:19.69#ibcon#read 6, iclass 7, count 2 2006.203.07:20:19.69#ibcon#end of sib2, iclass 7, count 2 2006.203.07:20:19.69#ibcon#*after write, iclass 7, count 2 2006.203.07:20:19.69#ibcon#*before return 0, iclass 7, count 2 2006.203.07:20:19.69#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.203.07:20:19.69#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.203.07:20:19.69#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.203.07:20:19.69#ibcon#ireg 7 cls_cnt 0 2006.203.07:20:19.69#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.203.07:20:19.81#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.203.07:20:19.81#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.203.07:20:19.81#ibcon#enter wrdev, iclass 7, count 0 2006.203.07:20:19.81#ibcon#first serial, iclass 7, count 0 2006.203.07:20:19.81#ibcon#enter sib2, iclass 7, count 0 2006.203.07:20:19.81#ibcon#flushed, iclass 7, count 0 2006.203.07:20:19.81#ibcon#about to write, iclass 7, count 0 2006.203.07:20:19.81#ibcon#wrote, iclass 7, count 0 2006.203.07:20:19.81#ibcon#about to read 3, iclass 7, count 0 2006.203.07:20:19.83#ibcon#read 3, iclass 7, count 0 2006.203.07:20:19.83#ibcon#about to read 4, iclass 7, count 0 2006.203.07:20:19.83#ibcon#read 4, iclass 7, count 0 2006.203.07:20:19.83#ibcon#about to read 5, iclass 7, count 0 2006.203.07:20:19.83#ibcon#read 5, iclass 7, count 0 2006.203.07:20:19.83#ibcon#about to read 6, iclass 7, count 0 2006.203.07:20:19.83#ibcon#read 6, iclass 7, count 0 2006.203.07:20:19.83#ibcon#end of sib2, iclass 7, count 0 2006.203.07:20:19.83#ibcon#*mode == 0, iclass 7, count 0 2006.203.07:20:19.83#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.203.07:20:19.83#ibcon#[25=USB\r\n] 2006.203.07:20:19.83#ibcon#*before write, iclass 7, count 0 2006.203.07:20:19.83#ibcon#enter sib2, iclass 7, count 0 2006.203.07:20:19.83#ibcon#flushed, iclass 7, count 0 2006.203.07:20:19.83#ibcon#about to write, iclass 7, count 0 2006.203.07:20:19.83#ibcon#wrote, iclass 7, count 0 2006.203.07:20:19.83#ibcon#about to read 3, iclass 7, count 0 2006.203.07:20:19.86#ibcon#read 3, iclass 7, count 0 2006.203.07:20:19.86#ibcon#about to read 4, iclass 7, count 0 2006.203.07:20:19.86#ibcon#read 4, iclass 7, count 0 2006.203.07:20:19.86#ibcon#about to read 5, iclass 7, count 0 2006.203.07:20:19.86#ibcon#read 5, iclass 7, count 0 2006.203.07:20:19.86#ibcon#about to read 6, iclass 7, count 0 2006.203.07:20:19.86#ibcon#read 6, iclass 7, count 0 2006.203.07:20:19.86#ibcon#end of sib2, iclass 7, count 0 2006.203.07:20:19.86#ibcon#*after write, iclass 7, count 0 2006.203.07:20:19.86#ibcon#*before return 0, iclass 7, count 0 2006.203.07:20:19.86#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.203.07:20:19.86#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.203.07:20:19.86#ibcon#about to clear, iclass 7 cls_cnt 0 2006.203.07:20:19.86#ibcon#cleared, iclass 7 cls_cnt 0 2006.203.07:20:19.86$vc4f8/valo=3,672.99 2006.203.07:20:19.86#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.203.07:20:19.86#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.203.07:20:19.86#ibcon#ireg 17 cls_cnt 0 2006.203.07:20:19.86#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.203.07:20:19.86#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.203.07:20:19.86#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.203.07:20:19.86#ibcon#enter wrdev, iclass 11, count 0 2006.203.07:20:19.86#ibcon#first serial, iclass 11, count 0 2006.203.07:20:19.86#ibcon#enter sib2, iclass 11, count 0 2006.203.07:20:19.86#ibcon#flushed, iclass 11, count 0 2006.203.07:20:19.86#ibcon#about to write, iclass 11, count 0 2006.203.07:20:19.86#ibcon#wrote, iclass 11, count 0 2006.203.07:20:19.86#ibcon#about to read 3, iclass 11, count 0 2006.203.07:20:19.88#ibcon#read 3, iclass 11, count 0 2006.203.07:20:19.88#ibcon#about to read 4, iclass 11, count 0 2006.203.07:20:19.88#ibcon#read 4, iclass 11, count 0 2006.203.07:20:19.88#ibcon#about to read 5, iclass 11, count 0 2006.203.07:20:19.88#ibcon#read 5, iclass 11, count 0 2006.203.07:20:19.88#ibcon#about to read 6, iclass 11, count 0 2006.203.07:20:19.88#ibcon#read 6, iclass 11, count 0 2006.203.07:20:19.88#ibcon#end of sib2, iclass 11, count 0 2006.203.07:20:19.88#ibcon#*mode == 0, iclass 11, count 0 2006.203.07:20:19.88#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.203.07:20:19.88#ibcon#[26=FRQ=03,672.99\r\n] 2006.203.07:20:19.88#ibcon#*before write, iclass 11, count 0 2006.203.07:20:19.88#ibcon#enter sib2, iclass 11, count 0 2006.203.07:20:19.88#ibcon#flushed, iclass 11, count 0 2006.203.07:20:19.88#ibcon#about to write, iclass 11, count 0 2006.203.07:20:19.88#ibcon#wrote, iclass 11, count 0 2006.203.07:20:19.88#ibcon#about to read 3, iclass 11, count 0 2006.203.07:20:19.93#ibcon#read 3, iclass 11, count 0 2006.203.07:20:19.93#ibcon#about to read 4, iclass 11, count 0 2006.203.07:20:19.93#ibcon#read 4, iclass 11, count 0 2006.203.07:20:19.93#ibcon#about to read 5, iclass 11, count 0 2006.203.07:20:19.93#ibcon#read 5, iclass 11, count 0 2006.203.07:20:19.93#ibcon#about to read 6, iclass 11, count 0 2006.203.07:20:19.93#ibcon#read 6, iclass 11, count 0 2006.203.07:20:19.93#ibcon#end of sib2, iclass 11, count 0 2006.203.07:20:19.93#ibcon#*after write, iclass 11, count 0 2006.203.07:20:19.93#ibcon#*before return 0, iclass 11, count 0 2006.203.07:20:19.93#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.203.07:20:19.93#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.203.07:20:19.93#ibcon#about to clear, iclass 11 cls_cnt 0 2006.203.07:20:19.93#ibcon#cleared, iclass 11 cls_cnt 0 2006.203.07:20:19.93$vc4f8/va=3,8 2006.203.07:20:19.93#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.203.07:20:19.93#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.203.07:20:19.93#ibcon#ireg 11 cls_cnt 2 2006.203.07:20:19.93#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.203.07:20:19.98#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.203.07:20:19.98#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.203.07:20:19.98#ibcon#enter wrdev, iclass 13, count 2 2006.203.07:20:19.98#ibcon#first serial, iclass 13, count 2 2006.203.07:20:19.98#ibcon#enter sib2, iclass 13, count 2 2006.203.07:20:19.98#ibcon#flushed, iclass 13, count 2 2006.203.07:20:19.98#ibcon#about to write, iclass 13, count 2 2006.203.07:20:19.98#ibcon#wrote, iclass 13, count 2 2006.203.07:20:19.98#ibcon#about to read 3, iclass 13, count 2 2006.203.07:20:20.00#ibcon#read 3, iclass 13, count 2 2006.203.07:20:20.00#ibcon#about to read 4, iclass 13, count 2 2006.203.07:20:20.00#ibcon#read 4, iclass 13, count 2 2006.203.07:20:20.00#ibcon#about to read 5, iclass 13, count 2 2006.203.07:20:20.00#ibcon#read 5, iclass 13, count 2 2006.203.07:20:20.00#ibcon#about to read 6, iclass 13, count 2 2006.203.07:20:20.00#ibcon#read 6, iclass 13, count 2 2006.203.07:20:20.00#ibcon#end of sib2, iclass 13, count 2 2006.203.07:20:20.00#ibcon#*mode == 0, iclass 13, count 2 2006.203.07:20:20.00#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.203.07:20:20.00#ibcon#[25=AT03-08\r\n] 2006.203.07:20:20.00#ibcon#*before write, iclass 13, count 2 2006.203.07:20:20.00#ibcon#enter sib2, iclass 13, count 2 2006.203.07:20:20.00#ibcon#flushed, iclass 13, count 2 2006.203.07:20:20.00#ibcon#about to write, iclass 13, count 2 2006.203.07:20:20.00#ibcon#wrote, iclass 13, count 2 2006.203.07:20:20.00#ibcon#about to read 3, iclass 13, count 2 2006.203.07:20:20.03#ibcon#read 3, iclass 13, count 2 2006.203.07:20:20.03#ibcon#about to read 4, iclass 13, count 2 2006.203.07:20:20.03#ibcon#read 4, iclass 13, count 2 2006.203.07:20:20.03#ibcon#about to read 5, iclass 13, count 2 2006.203.07:20:20.03#ibcon#read 5, iclass 13, count 2 2006.203.07:20:20.03#ibcon#about to read 6, iclass 13, count 2 2006.203.07:20:20.03#ibcon#read 6, iclass 13, count 2 2006.203.07:20:20.03#ibcon#end of sib2, iclass 13, count 2 2006.203.07:20:20.03#ibcon#*after write, iclass 13, count 2 2006.203.07:20:20.03#ibcon#*before return 0, iclass 13, count 2 2006.203.07:20:20.03#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.203.07:20:20.03#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.203.07:20:20.03#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.203.07:20:20.03#ibcon#ireg 7 cls_cnt 0 2006.203.07:20:20.03#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.203.07:20:20.15#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.203.07:20:20.15#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.203.07:20:20.15#ibcon#enter wrdev, iclass 13, count 0 2006.203.07:20:20.15#ibcon#first serial, iclass 13, count 0 2006.203.07:20:20.15#ibcon#enter sib2, iclass 13, count 0 2006.203.07:20:20.15#ibcon#flushed, iclass 13, count 0 2006.203.07:20:20.15#ibcon#about to write, iclass 13, count 0 2006.203.07:20:20.15#ibcon#wrote, iclass 13, count 0 2006.203.07:20:20.15#ibcon#about to read 3, iclass 13, count 0 2006.203.07:20:20.17#ibcon#read 3, iclass 13, count 0 2006.203.07:20:20.17#ibcon#about to read 4, iclass 13, count 0 2006.203.07:20:20.17#ibcon#read 4, iclass 13, count 0 2006.203.07:20:20.17#ibcon#about to read 5, iclass 13, count 0 2006.203.07:20:20.17#ibcon#read 5, iclass 13, count 0 2006.203.07:20:20.17#ibcon#about to read 6, iclass 13, count 0 2006.203.07:20:20.17#ibcon#read 6, iclass 13, count 0 2006.203.07:20:20.17#ibcon#end of sib2, iclass 13, count 0 2006.203.07:20:20.17#ibcon#*mode == 0, iclass 13, count 0 2006.203.07:20:20.17#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.203.07:20:20.17#ibcon#[25=USB\r\n] 2006.203.07:20:20.17#ibcon#*before write, iclass 13, count 0 2006.203.07:20:20.17#ibcon#enter sib2, iclass 13, count 0 2006.203.07:20:20.17#ibcon#flushed, iclass 13, count 0 2006.203.07:20:20.17#ibcon#about to write, iclass 13, count 0 2006.203.07:20:20.17#ibcon#wrote, iclass 13, count 0 2006.203.07:20:20.17#ibcon#about to read 3, iclass 13, count 0 2006.203.07:20:20.20#ibcon#read 3, iclass 13, count 0 2006.203.07:20:20.20#ibcon#about to read 4, iclass 13, count 0 2006.203.07:20:20.20#ibcon#read 4, iclass 13, count 0 2006.203.07:20:20.20#ibcon#about to read 5, iclass 13, count 0 2006.203.07:20:20.20#ibcon#read 5, iclass 13, count 0 2006.203.07:20:20.20#ibcon#about to read 6, iclass 13, count 0 2006.203.07:20:20.20#ibcon#read 6, iclass 13, count 0 2006.203.07:20:20.20#ibcon#end of sib2, iclass 13, count 0 2006.203.07:20:20.20#ibcon#*after write, iclass 13, count 0 2006.203.07:20:20.20#ibcon#*before return 0, iclass 13, count 0 2006.203.07:20:20.20#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.203.07:20:20.20#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.203.07:20:20.20#ibcon#about to clear, iclass 13 cls_cnt 0 2006.203.07:20:20.20#ibcon#cleared, iclass 13 cls_cnt 0 2006.203.07:20:20.20$vc4f8/valo=4,832.99 2006.203.07:20:20.20#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.203.07:20:20.20#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.203.07:20:20.20#ibcon#ireg 17 cls_cnt 0 2006.203.07:20:20.20#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.203.07:20:20.20#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.203.07:20:20.20#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.203.07:20:20.20#ibcon#enter wrdev, iclass 15, count 0 2006.203.07:20:20.20#ibcon#first serial, iclass 15, count 0 2006.203.07:20:20.20#ibcon#enter sib2, iclass 15, count 0 2006.203.07:20:20.20#ibcon#flushed, iclass 15, count 0 2006.203.07:20:20.20#ibcon#about to write, iclass 15, count 0 2006.203.07:20:20.20#ibcon#wrote, iclass 15, count 0 2006.203.07:20:20.20#ibcon#about to read 3, iclass 15, count 0 2006.203.07:20:20.22#ibcon#read 3, iclass 15, count 0 2006.203.07:20:20.22#ibcon#about to read 4, iclass 15, count 0 2006.203.07:20:20.22#ibcon#read 4, iclass 15, count 0 2006.203.07:20:20.22#ibcon#about to read 5, iclass 15, count 0 2006.203.07:20:20.22#ibcon#read 5, iclass 15, count 0 2006.203.07:20:20.22#ibcon#about to read 6, iclass 15, count 0 2006.203.07:20:20.22#ibcon#read 6, iclass 15, count 0 2006.203.07:20:20.22#ibcon#end of sib2, iclass 15, count 0 2006.203.07:20:20.22#ibcon#*mode == 0, iclass 15, count 0 2006.203.07:20:20.22#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.203.07:20:20.22#ibcon#[26=FRQ=04,832.99\r\n] 2006.203.07:20:20.22#ibcon#*before write, iclass 15, count 0 2006.203.07:20:20.22#ibcon#enter sib2, iclass 15, count 0 2006.203.07:20:20.22#ibcon#flushed, iclass 15, count 0 2006.203.07:20:20.22#ibcon#about to write, iclass 15, count 0 2006.203.07:20:20.22#ibcon#wrote, iclass 15, count 0 2006.203.07:20:20.22#ibcon#about to read 3, iclass 15, count 0 2006.203.07:20:20.27#ibcon#read 3, iclass 15, count 0 2006.203.07:20:20.27#ibcon#about to read 4, iclass 15, count 0 2006.203.07:20:20.27#ibcon#read 4, iclass 15, count 0 2006.203.07:20:20.27#ibcon#about to read 5, iclass 15, count 0 2006.203.07:20:20.27#ibcon#read 5, iclass 15, count 0 2006.203.07:20:20.27#ibcon#about to read 6, iclass 15, count 0 2006.203.07:20:20.27#ibcon#read 6, iclass 15, count 0 2006.203.07:20:20.27#ibcon#end of sib2, iclass 15, count 0 2006.203.07:20:20.27#ibcon#*after write, iclass 15, count 0 2006.203.07:20:20.27#ibcon#*before return 0, iclass 15, count 0 2006.203.07:20:20.27#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.203.07:20:20.27#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.203.07:20:20.27#ibcon#about to clear, iclass 15 cls_cnt 0 2006.203.07:20:20.27#ibcon#cleared, iclass 15 cls_cnt 0 2006.203.07:20:20.27$vc4f8/va=4,7 2006.203.07:20:20.27#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.203.07:20:20.27#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.203.07:20:20.27#ibcon#ireg 11 cls_cnt 2 2006.203.07:20:20.27#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.203.07:20:20.32#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.203.07:20:20.32#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.203.07:20:20.32#ibcon#enter wrdev, iclass 17, count 2 2006.203.07:20:20.32#ibcon#first serial, iclass 17, count 2 2006.203.07:20:20.32#ibcon#enter sib2, iclass 17, count 2 2006.203.07:20:20.32#ibcon#flushed, iclass 17, count 2 2006.203.07:20:20.32#ibcon#about to write, iclass 17, count 2 2006.203.07:20:20.32#ibcon#wrote, iclass 17, count 2 2006.203.07:20:20.32#ibcon#about to read 3, iclass 17, count 2 2006.203.07:20:20.34#ibcon#read 3, iclass 17, count 2 2006.203.07:20:20.34#ibcon#about to read 4, iclass 17, count 2 2006.203.07:20:20.34#ibcon#read 4, iclass 17, count 2 2006.203.07:20:20.34#ibcon#about to read 5, iclass 17, count 2 2006.203.07:20:20.34#ibcon#read 5, iclass 17, count 2 2006.203.07:20:20.34#ibcon#about to read 6, iclass 17, count 2 2006.203.07:20:20.34#ibcon#read 6, iclass 17, count 2 2006.203.07:20:20.34#ibcon#end of sib2, iclass 17, count 2 2006.203.07:20:20.34#ibcon#*mode == 0, iclass 17, count 2 2006.203.07:20:20.34#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.203.07:20:20.34#ibcon#[25=AT04-07\r\n] 2006.203.07:20:20.34#ibcon#*before write, iclass 17, count 2 2006.203.07:20:20.34#ibcon#enter sib2, iclass 17, count 2 2006.203.07:20:20.34#ibcon#flushed, iclass 17, count 2 2006.203.07:20:20.34#ibcon#about to write, iclass 17, count 2 2006.203.07:20:20.34#ibcon#wrote, iclass 17, count 2 2006.203.07:20:20.34#ibcon#about to read 3, iclass 17, count 2 2006.203.07:20:20.37#ibcon#read 3, iclass 17, count 2 2006.203.07:20:20.37#ibcon#about to read 4, iclass 17, count 2 2006.203.07:20:20.37#ibcon#read 4, iclass 17, count 2 2006.203.07:20:20.37#ibcon#about to read 5, iclass 17, count 2 2006.203.07:20:20.37#ibcon#read 5, iclass 17, count 2 2006.203.07:20:20.37#ibcon#about to read 6, iclass 17, count 2 2006.203.07:20:20.37#ibcon#read 6, iclass 17, count 2 2006.203.07:20:20.37#ibcon#end of sib2, iclass 17, count 2 2006.203.07:20:20.37#ibcon#*after write, iclass 17, count 2 2006.203.07:20:20.37#ibcon#*before return 0, iclass 17, count 2 2006.203.07:20:20.37#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.203.07:20:20.37#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.203.07:20:20.37#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.203.07:20:20.37#ibcon#ireg 7 cls_cnt 0 2006.203.07:20:20.37#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.203.07:20:20.49#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.203.07:20:20.49#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.203.07:20:20.49#ibcon#enter wrdev, iclass 17, count 0 2006.203.07:20:20.49#ibcon#first serial, iclass 17, count 0 2006.203.07:20:20.49#ibcon#enter sib2, iclass 17, count 0 2006.203.07:20:20.49#ibcon#flushed, iclass 17, count 0 2006.203.07:20:20.49#ibcon#about to write, iclass 17, count 0 2006.203.07:20:20.49#ibcon#wrote, iclass 17, count 0 2006.203.07:20:20.49#ibcon#about to read 3, iclass 17, count 0 2006.203.07:20:20.51#ibcon#read 3, iclass 17, count 0 2006.203.07:20:20.51#ibcon#about to read 4, iclass 17, count 0 2006.203.07:20:20.51#ibcon#read 4, iclass 17, count 0 2006.203.07:20:20.51#ibcon#about to read 5, iclass 17, count 0 2006.203.07:20:20.51#ibcon#read 5, iclass 17, count 0 2006.203.07:20:20.51#ibcon#about to read 6, iclass 17, count 0 2006.203.07:20:20.51#ibcon#read 6, iclass 17, count 0 2006.203.07:20:20.51#ibcon#end of sib2, iclass 17, count 0 2006.203.07:20:20.51#ibcon#*mode == 0, iclass 17, count 0 2006.203.07:20:20.51#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.203.07:20:20.51#ibcon#[25=USB\r\n] 2006.203.07:20:20.51#ibcon#*before write, iclass 17, count 0 2006.203.07:20:20.51#ibcon#enter sib2, iclass 17, count 0 2006.203.07:20:20.51#ibcon#flushed, iclass 17, count 0 2006.203.07:20:20.51#ibcon#about to write, iclass 17, count 0 2006.203.07:20:20.51#ibcon#wrote, iclass 17, count 0 2006.203.07:20:20.51#ibcon#about to read 3, iclass 17, count 0 2006.203.07:20:20.54#ibcon#read 3, iclass 17, count 0 2006.203.07:20:20.54#ibcon#about to read 4, iclass 17, count 0 2006.203.07:20:20.54#ibcon#read 4, iclass 17, count 0 2006.203.07:20:20.54#ibcon#about to read 5, iclass 17, count 0 2006.203.07:20:20.54#ibcon#read 5, iclass 17, count 0 2006.203.07:20:20.54#ibcon#about to read 6, iclass 17, count 0 2006.203.07:20:20.54#ibcon#read 6, iclass 17, count 0 2006.203.07:20:20.54#ibcon#end of sib2, iclass 17, count 0 2006.203.07:20:20.54#ibcon#*after write, iclass 17, count 0 2006.203.07:20:20.54#ibcon#*before return 0, iclass 17, count 0 2006.203.07:20:20.54#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.203.07:20:20.54#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.203.07:20:20.54#ibcon#about to clear, iclass 17 cls_cnt 0 2006.203.07:20:20.54#ibcon#cleared, iclass 17 cls_cnt 0 2006.203.07:20:20.54$vc4f8/valo=5,652.99 2006.203.07:20:20.54#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.203.07:20:20.54#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.203.07:20:20.54#ibcon#ireg 17 cls_cnt 0 2006.203.07:20:20.54#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.203.07:20:20.54#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.203.07:20:20.54#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.203.07:20:20.54#ibcon#enter wrdev, iclass 19, count 0 2006.203.07:20:20.54#ibcon#first serial, iclass 19, count 0 2006.203.07:20:20.54#ibcon#enter sib2, iclass 19, count 0 2006.203.07:20:20.54#ibcon#flushed, iclass 19, count 0 2006.203.07:20:20.54#ibcon#about to write, iclass 19, count 0 2006.203.07:20:20.54#ibcon#wrote, iclass 19, count 0 2006.203.07:20:20.54#ibcon#about to read 3, iclass 19, count 0 2006.203.07:20:20.56#ibcon#read 3, iclass 19, count 0 2006.203.07:20:20.56#ibcon#about to read 4, iclass 19, count 0 2006.203.07:20:20.56#ibcon#read 4, iclass 19, count 0 2006.203.07:20:20.56#ibcon#about to read 5, iclass 19, count 0 2006.203.07:20:20.56#ibcon#read 5, iclass 19, count 0 2006.203.07:20:20.56#ibcon#about to read 6, iclass 19, count 0 2006.203.07:20:20.56#ibcon#read 6, iclass 19, count 0 2006.203.07:20:20.56#ibcon#end of sib2, iclass 19, count 0 2006.203.07:20:20.56#ibcon#*mode == 0, iclass 19, count 0 2006.203.07:20:20.56#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.203.07:20:20.56#ibcon#[26=FRQ=05,652.99\r\n] 2006.203.07:20:20.56#ibcon#*before write, iclass 19, count 0 2006.203.07:20:20.56#ibcon#enter sib2, iclass 19, count 0 2006.203.07:20:20.56#ibcon#flushed, iclass 19, count 0 2006.203.07:20:20.56#ibcon#about to write, iclass 19, count 0 2006.203.07:20:20.56#ibcon#wrote, iclass 19, count 0 2006.203.07:20:20.56#ibcon#about to read 3, iclass 19, count 0 2006.203.07:20:20.60#ibcon#read 3, iclass 19, count 0 2006.203.07:20:20.60#ibcon#about to read 4, iclass 19, count 0 2006.203.07:20:20.60#ibcon#read 4, iclass 19, count 0 2006.203.07:20:20.60#ibcon#about to read 5, iclass 19, count 0 2006.203.07:20:20.60#ibcon#read 5, iclass 19, count 0 2006.203.07:20:20.60#ibcon#about to read 6, iclass 19, count 0 2006.203.07:20:20.60#ibcon#read 6, iclass 19, count 0 2006.203.07:20:20.60#ibcon#end of sib2, iclass 19, count 0 2006.203.07:20:20.60#ibcon#*after write, iclass 19, count 0 2006.203.07:20:20.60#ibcon#*before return 0, iclass 19, count 0 2006.203.07:20:20.60#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.203.07:20:20.60#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.203.07:20:20.60#ibcon#about to clear, iclass 19 cls_cnt 0 2006.203.07:20:20.60#ibcon#cleared, iclass 19 cls_cnt 0 2006.203.07:20:20.60$vc4f8/va=5,7 2006.203.07:20:20.60#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.203.07:20:20.60#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.203.07:20:20.60#ibcon#ireg 11 cls_cnt 2 2006.203.07:20:20.60#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.203.07:20:20.66#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.203.07:20:20.66#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.203.07:20:20.66#ibcon#enter wrdev, iclass 21, count 2 2006.203.07:20:20.66#ibcon#first serial, iclass 21, count 2 2006.203.07:20:20.66#ibcon#enter sib2, iclass 21, count 2 2006.203.07:20:20.66#ibcon#flushed, iclass 21, count 2 2006.203.07:20:20.66#ibcon#about to write, iclass 21, count 2 2006.203.07:20:20.66#ibcon#wrote, iclass 21, count 2 2006.203.07:20:20.66#ibcon#about to read 3, iclass 21, count 2 2006.203.07:20:20.68#ibcon#read 3, iclass 21, count 2 2006.203.07:20:20.68#ibcon#about to read 4, iclass 21, count 2 2006.203.07:20:20.68#ibcon#read 4, iclass 21, count 2 2006.203.07:20:20.68#ibcon#about to read 5, iclass 21, count 2 2006.203.07:20:20.68#ibcon#read 5, iclass 21, count 2 2006.203.07:20:20.68#ibcon#about to read 6, iclass 21, count 2 2006.203.07:20:20.68#ibcon#read 6, iclass 21, count 2 2006.203.07:20:20.68#ibcon#end of sib2, iclass 21, count 2 2006.203.07:20:20.68#ibcon#*mode == 0, iclass 21, count 2 2006.203.07:20:20.68#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.203.07:20:20.68#ibcon#[25=AT05-07\r\n] 2006.203.07:20:20.68#ibcon#*before write, iclass 21, count 2 2006.203.07:20:20.68#ibcon#enter sib2, iclass 21, count 2 2006.203.07:20:20.68#ibcon#flushed, iclass 21, count 2 2006.203.07:20:20.68#ibcon#about to write, iclass 21, count 2 2006.203.07:20:20.68#ibcon#wrote, iclass 21, count 2 2006.203.07:20:20.68#ibcon#about to read 3, iclass 21, count 2 2006.203.07:20:20.71#ibcon#read 3, iclass 21, count 2 2006.203.07:20:20.71#ibcon#about to read 4, iclass 21, count 2 2006.203.07:20:20.71#ibcon#read 4, iclass 21, count 2 2006.203.07:20:20.71#ibcon#about to read 5, iclass 21, count 2 2006.203.07:20:20.71#ibcon#read 5, iclass 21, count 2 2006.203.07:20:20.71#ibcon#about to read 6, iclass 21, count 2 2006.203.07:20:20.71#ibcon#read 6, iclass 21, count 2 2006.203.07:20:20.71#ibcon#end of sib2, iclass 21, count 2 2006.203.07:20:20.71#ibcon#*after write, iclass 21, count 2 2006.203.07:20:20.71#ibcon#*before return 0, iclass 21, count 2 2006.203.07:20:20.71#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.203.07:20:20.71#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.203.07:20:20.71#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.203.07:20:20.71#ibcon#ireg 7 cls_cnt 0 2006.203.07:20:20.71#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.203.07:20:20.83#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.203.07:20:20.83#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.203.07:20:20.83#ibcon#enter wrdev, iclass 21, count 0 2006.203.07:20:20.83#ibcon#first serial, iclass 21, count 0 2006.203.07:20:20.83#ibcon#enter sib2, iclass 21, count 0 2006.203.07:20:20.83#ibcon#flushed, iclass 21, count 0 2006.203.07:20:20.83#ibcon#about to write, iclass 21, count 0 2006.203.07:20:20.83#ibcon#wrote, iclass 21, count 0 2006.203.07:20:20.83#ibcon#about to read 3, iclass 21, count 0 2006.203.07:20:20.85#ibcon#read 3, iclass 21, count 0 2006.203.07:20:20.85#ibcon#about to read 4, iclass 21, count 0 2006.203.07:20:20.85#ibcon#read 4, iclass 21, count 0 2006.203.07:20:20.85#ibcon#about to read 5, iclass 21, count 0 2006.203.07:20:20.85#ibcon#read 5, iclass 21, count 0 2006.203.07:20:20.85#ibcon#about to read 6, iclass 21, count 0 2006.203.07:20:20.85#ibcon#read 6, iclass 21, count 0 2006.203.07:20:20.85#ibcon#end of sib2, iclass 21, count 0 2006.203.07:20:20.85#ibcon#*mode == 0, iclass 21, count 0 2006.203.07:20:20.85#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.203.07:20:20.85#ibcon#[25=USB\r\n] 2006.203.07:20:20.85#ibcon#*before write, iclass 21, count 0 2006.203.07:20:20.85#ibcon#enter sib2, iclass 21, count 0 2006.203.07:20:20.85#ibcon#flushed, iclass 21, count 0 2006.203.07:20:20.85#ibcon#about to write, iclass 21, count 0 2006.203.07:20:20.85#ibcon#wrote, iclass 21, count 0 2006.203.07:20:20.85#ibcon#about to read 3, iclass 21, count 0 2006.203.07:20:20.88#ibcon#read 3, iclass 21, count 0 2006.203.07:20:20.88#ibcon#about to read 4, iclass 21, count 0 2006.203.07:20:20.88#ibcon#read 4, iclass 21, count 0 2006.203.07:20:20.88#ibcon#about to read 5, iclass 21, count 0 2006.203.07:20:20.88#ibcon#read 5, iclass 21, count 0 2006.203.07:20:20.88#ibcon#about to read 6, iclass 21, count 0 2006.203.07:20:20.88#ibcon#read 6, iclass 21, count 0 2006.203.07:20:20.88#ibcon#end of sib2, iclass 21, count 0 2006.203.07:20:20.88#ibcon#*after write, iclass 21, count 0 2006.203.07:20:20.88#ibcon#*before return 0, iclass 21, count 0 2006.203.07:20:20.88#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.203.07:20:20.88#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.203.07:20:20.88#ibcon#about to clear, iclass 21 cls_cnt 0 2006.203.07:20:20.88#ibcon#cleared, iclass 21 cls_cnt 0 2006.203.07:20:20.88$vc4f8/valo=6,772.99 2006.203.07:20:20.88#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.203.07:20:20.88#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.203.07:20:20.88#ibcon#ireg 17 cls_cnt 0 2006.203.07:20:20.88#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.203.07:20:20.88#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.203.07:20:20.88#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.203.07:20:20.88#ibcon#enter wrdev, iclass 23, count 0 2006.203.07:20:20.88#ibcon#first serial, iclass 23, count 0 2006.203.07:20:20.88#ibcon#enter sib2, iclass 23, count 0 2006.203.07:20:20.88#ibcon#flushed, iclass 23, count 0 2006.203.07:20:20.88#ibcon#about to write, iclass 23, count 0 2006.203.07:20:20.88#ibcon#wrote, iclass 23, count 0 2006.203.07:20:20.88#ibcon#about to read 3, iclass 23, count 0 2006.203.07:20:20.90#ibcon#read 3, iclass 23, count 0 2006.203.07:20:20.90#ibcon#about to read 4, iclass 23, count 0 2006.203.07:20:20.90#ibcon#read 4, iclass 23, count 0 2006.203.07:20:20.90#ibcon#about to read 5, iclass 23, count 0 2006.203.07:20:20.90#ibcon#read 5, iclass 23, count 0 2006.203.07:20:20.90#ibcon#about to read 6, iclass 23, count 0 2006.203.07:20:20.90#ibcon#read 6, iclass 23, count 0 2006.203.07:20:20.90#ibcon#end of sib2, iclass 23, count 0 2006.203.07:20:20.90#ibcon#*mode == 0, iclass 23, count 0 2006.203.07:20:20.90#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.203.07:20:20.90#ibcon#[26=FRQ=06,772.99\r\n] 2006.203.07:20:20.90#ibcon#*before write, iclass 23, count 0 2006.203.07:20:20.90#ibcon#enter sib2, iclass 23, count 0 2006.203.07:20:20.90#ibcon#flushed, iclass 23, count 0 2006.203.07:20:20.90#ibcon#about to write, iclass 23, count 0 2006.203.07:20:20.90#ibcon#wrote, iclass 23, count 0 2006.203.07:20:20.90#ibcon#about to read 3, iclass 23, count 0 2006.203.07:20:20.95#ibcon#read 3, iclass 23, count 0 2006.203.07:20:20.95#ibcon#about to read 4, iclass 23, count 0 2006.203.07:20:20.95#ibcon#read 4, iclass 23, count 0 2006.203.07:20:20.95#ibcon#about to read 5, iclass 23, count 0 2006.203.07:20:20.95#ibcon#read 5, iclass 23, count 0 2006.203.07:20:20.95#ibcon#about to read 6, iclass 23, count 0 2006.203.07:20:20.95#ibcon#read 6, iclass 23, count 0 2006.203.07:20:20.95#ibcon#end of sib2, iclass 23, count 0 2006.203.07:20:20.95#ibcon#*after write, iclass 23, count 0 2006.203.07:20:20.95#ibcon#*before return 0, iclass 23, count 0 2006.203.07:20:20.95#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.203.07:20:20.95#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.203.07:20:20.95#ibcon#about to clear, iclass 23 cls_cnt 0 2006.203.07:20:20.95#ibcon#cleared, iclass 23 cls_cnt 0 2006.203.07:20:20.95$vc4f8/va=6,6 2006.203.07:20:20.95#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.203.07:20:20.95#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.203.07:20:20.95#ibcon#ireg 11 cls_cnt 2 2006.203.07:20:20.95#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.203.07:20:21.00#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.203.07:20:21.00#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.203.07:20:21.00#ibcon#enter wrdev, iclass 25, count 2 2006.203.07:20:21.00#ibcon#first serial, iclass 25, count 2 2006.203.07:20:21.00#ibcon#enter sib2, iclass 25, count 2 2006.203.07:20:21.00#ibcon#flushed, iclass 25, count 2 2006.203.07:20:21.00#ibcon#about to write, iclass 25, count 2 2006.203.07:20:21.00#ibcon#wrote, iclass 25, count 2 2006.203.07:20:21.00#ibcon#about to read 3, iclass 25, count 2 2006.203.07:20:21.02#ibcon#read 3, iclass 25, count 2 2006.203.07:20:21.02#ibcon#about to read 4, iclass 25, count 2 2006.203.07:20:21.02#ibcon#read 4, iclass 25, count 2 2006.203.07:20:21.02#ibcon#about to read 5, iclass 25, count 2 2006.203.07:20:21.02#ibcon#read 5, iclass 25, count 2 2006.203.07:20:21.02#ibcon#about to read 6, iclass 25, count 2 2006.203.07:20:21.02#ibcon#read 6, iclass 25, count 2 2006.203.07:20:21.02#ibcon#end of sib2, iclass 25, count 2 2006.203.07:20:21.02#ibcon#*mode == 0, iclass 25, count 2 2006.203.07:20:21.02#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.203.07:20:21.02#ibcon#[25=AT06-06\r\n] 2006.203.07:20:21.02#ibcon#*before write, iclass 25, count 2 2006.203.07:20:21.02#ibcon#enter sib2, iclass 25, count 2 2006.203.07:20:21.02#ibcon#flushed, iclass 25, count 2 2006.203.07:20:21.02#ibcon#about to write, iclass 25, count 2 2006.203.07:20:21.02#ibcon#wrote, iclass 25, count 2 2006.203.07:20:21.02#ibcon#about to read 3, iclass 25, count 2 2006.203.07:20:21.05#ibcon#read 3, iclass 25, count 2 2006.203.07:20:21.05#ibcon#about to read 4, iclass 25, count 2 2006.203.07:20:21.05#ibcon#read 4, iclass 25, count 2 2006.203.07:20:21.05#ibcon#about to read 5, iclass 25, count 2 2006.203.07:20:21.05#ibcon#read 5, iclass 25, count 2 2006.203.07:20:21.05#ibcon#about to read 6, iclass 25, count 2 2006.203.07:20:21.05#ibcon#read 6, iclass 25, count 2 2006.203.07:20:21.05#ibcon#end of sib2, iclass 25, count 2 2006.203.07:20:21.05#ibcon#*after write, iclass 25, count 2 2006.203.07:20:21.05#ibcon#*before return 0, iclass 25, count 2 2006.203.07:20:21.05#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.203.07:20:21.05#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.203.07:20:21.05#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.203.07:20:21.05#ibcon#ireg 7 cls_cnt 0 2006.203.07:20:21.05#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.203.07:20:21.17#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.203.07:20:21.17#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.203.07:20:21.17#ibcon#enter wrdev, iclass 25, count 0 2006.203.07:20:21.17#ibcon#first serial, iclass 25, count 0 2006.203.07:20:21.17#ibcon#enter sib2, iclass 25, count 0 2006.203.07:20:21.17#ibcon#flushed, iclass 25, count 0 2006.203.07:20:21.17#ibcon#about to write, iclass 25, count 0 2006.203.07:20:21.17#ibcon#wrote, iclass 25, count 0 2006.203.07:20:21.17#ibcon#about to read 3, iclass 25, count 0 2006.203.07:20:21.19#ibcon#read 3, iclass 25, count 0 2006.203.07:20:21.19#ibcon#about to read 4, iclass 25, count 0 2006.203.07:20:21.19#ibcon#read 4, iclass 25, count 0 2006.203.07:20:21.19#ibcon#about to read 5, iclass 25, count 0 2006.203.07:20:21.19#ibcon#read 5, iclass 25, count 0 2006.203.07:20:21.19#ibcon#about to read 6, iclass 25, count 0 2006.203.07:20:21.19#ibcon#read 6, iclass 25, count 0 2006.203.07:20:21.19#ibcon#end of sib2, iclass 25, count 0 2006.203.07:20:21.19#ibcon#*mode == 0, iclass 25, count 0 2006.203.07:20:21.19#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.203.07:20:21.19#ibcon#[25=USB\r\n] 2006.203.07:20:21.19#ibcon#*before write, iclass 25, count 0 2006.203.07:20:21.19#ibcon#enter sib2, iclass 25, count 0 2006.203.07:20:21.19#ibcon#flushed, iclass 25, count 0 2006.203.07:20:21.19#ibcon#about to write, iclass 25, count 0 2006.203.07:20:21.19#ibcon#wrote, iclass 25, count 0 2006.203.07:20:21.19#ibcon#about to read 3, iclass 25, count 0 2006.203.07:20:21.22#ibcon#read 3, iclass 25, count 0 2006.203.07:20:21.22#ibcon#about to read 4, iclass 25, count 0 2006.203.07:20:21.22#ibcon#read 4, iclass 25, count 0 2006.203.07:20:21.22#ibcon#about to read 5, iclass 25, count 0 2006.203.07:20:21.22#ibcon#read 5, iclass 25, count 0 2006.203.07:20:21.22#ibcon#about to read 6, iclass 25, count 0 2006.203.07:20:21.22#ibcon#read 6, iclass 25, count 0 2006.203.07:20:21.22#ibcon#end of sib2, iclass 25, count 0 2006.203.07:20:21.22#ibcon#*after write, iclass 25, count 0 2006.203.07:20:21.22#ibcon#*before return 0, iclass 25, count 0 2006.203.07:20:21.22#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.203.07:20:21.22#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.203.07:20:21.22#ibcon#about to clear, iclass 25 cls_cnt 0 2006.203.07:20:21.22#ibcon#cleared, iclass 25 cls_cnt 0 2006.203.07:20:21.22$vc4f8/valo=7,832.99 2006.203.07:20:21.22#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.203.07:20:21.22#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.203.07:20:21.22#ibcon#ireg 17 cls_cnt 0 2006.203.07:20:21.22#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:20:21.22#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:20:21.22#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:20:21.22#ibcon#enter wrdev, iclass 27, count 0 2006.203.07:20:21.22#ibcon#first serial, iclass 27, count 0 2006.203.07:20:21.22#ibcon#enter sib2, iclass 27, count 0 2006.203.07:20:21.22#ibcon#flushed, iclass 27, count 0 2006.203.07:20:21.22#ibcon#about to write, iclass 27, count 0 2006.203.07:20:21.22#ibcon#wrote, iclass 27, count 0 2006.203.07:20:21.22#ibcon#about to read 3, iclass 27, count 0 2006.203.07:20:21.24#ibcon#read 3, iclass 27, count 0 2006.203.07:20:21.24#ibcon#about to read 4, iclass 27, count 0 2006.203.07:20:21.24#ibcon#read 4, iclass 27, count 0 2006.203.07:20:21.24#ibcon#about to read 5, iclass 27, count 0 2006.203.07:20:21.24#ibcon#read 5, iclass 27, count 0 2006.203.07:20:21.24#ibcon#about to read 6, iclass 27, count 0 2006.203.07:20:21.24#ibcon#read 6, iclass 27, count 0 2006.203.07:20:21.24#ibcon#end of sib2, iclass 27, count 0 2006.203.07:20:21.24#ibcon#*mode == 0, iclass 27, count 0 2006.203.07:20:21.24#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.203.07:20:21.24#ibcon#[26=FRQ=07,832.99\r\n] 2006.203.07:20:21.24#ibcon#*before write, iclass 27, count 0 2006.203.07:20:21.24#ibcon#enter sib2, iclass 27, count 0 2006.203.07:20:21.24#ibcon#flushed, iclass 27, count 0 2006.203.07:20:21.24#ibcon#about to write, iclass 27, count 0 2006.203.07:20:21.24#ibcon#wrote, iclass 27, count 0 2006.203.07:20:21.24#ibcon#about to read 3, iclass 27, count 0 2006.203.07:20:21.28#ibcon#read 3, iclass 27, count 0 2006.203.07:20:21.28#ibcon#about to read 4, iclass 27, count 0 2006.203.07:20:21.28#ibcon#read 4, iclass 27, count 0 2006.203.07:20:21.28#ibcon#about to read 5, iclass 27, count 0 2006.203.07:20:21.28#ibcon#read 5, iclass 27, count 0 2006.203.07:20:21.28#ibcon#about to read 6, iclass 27, count 0 2006.203.07:20:21.28#ibcon#read 6, iclass 27, count 0 2006.203.07:20:21.28#ibcon#end of sib2, iclass 27, count 0 2006.203.07:20:21.28#ibcon#*after write, iclass 27, count 0 2006.203.07:20:21.28#ibcon#*before return 0, iclass 27, count 0 2006.203.07:20:21.28#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:20:21.28#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:20:21.28#ibcon#about to clear, iclass 27 cls_cnt 0 2006.203.07:20:21.28#ibcon#cleared, iclass 27 cls_cnt 0 2006.203.07:20:21.28$vc4f8/va=7,7 2006.203.07:20:21.28#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.203.07:20:21.28#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.203.07:20:21.28#ibcon#ireg 11 cls_cnt 2 2006.203.07:20:21.28#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.203.07:20:21.34#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.203.07:20:21.34#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.203.07:20:21.34#ibcon#enter wrdev, iclass 29, count 2 2006.203.07:20:21.34#ibcon#first serial, iclass 29, count 2 2006.203.07:20:21.34#ibcon#enter sib2, iclass 29, count 2 2006.203.07:20:21.34#ibcon#flushed, iclass 29, count 2 2006.203.07:20:21.34#ibcon#about to write, iclass 29, count 2 2006.203.07:20:21.34#ibcon#wrote, iclass 29, count 2 2006.203.07:20:21.34#ibcon#about to read 3, iclass 29, count 2 2006.203.07:20:21.36#ibcon#read 3, iclass 29, count 2 2006.203.07:20:21.36#ibcon#about to read 4, iclass 29, count 2 2006.203.07:20:21.36#ibcon#read 4, iclass 29, count 2 2006.203.07:20:21.36#ibcon#about to read 5, iclass 29, count 2 2006.203.07:20:21.36#ibcon#read 5, iclass 29, count 2 2006.203.07:20:21.36#ibcon#about to read 6, iclass 29, count 2 2006.203.07:20:21.36#ibcon#read 6, iclass 29, count 2 2006.203.07:20:21.36#ibcon#end of sib2, iclass 29, count 2 2006.203.07:20:21.36#ibcon#*mode == 0, iclass 29, count 2 2006.203.07:20:21.36#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.203.07:20:21.36#ibcon#[25=AT07-07\r\n] 2006.203.07:20:21.36#ibcon#*before write, iclass 29, count 2 2006.203.07:20:21.36#ibcon#enter sib2, iclass 29, count 2 2006.203.07:20:21.36#ibcon#flushed, iclass 29, count 2 2006.203.07:20:21.36#ibcon#about to write, iclass 29, count 2 2006.203.07:20:21.36#ibcon#wrote, iclass 29, count 2 2006.203.07:20:21.36#ibcon#about to read 3, iclass 29, count 2 2006.203.07:20:21.39#ibcon#read 3, iclass 29, count 2 2006.203.07:20:21.39#ibcon#about to read 4, iclass 29, count 2 2006.203.07:20:21.39#ibcon#read 4, iclass 29, count 2 2006.203.07:20:21.39#ibcon#about to read 5, iclass 29, count 2 2006.203.07:20:21.39#ibcon#read 5, iclass 29, count 2 2006.203.07:20:21.39#ibcon#about to read 6, iclass 29, count 2 2006.203.07:20:21.39#ibcon#read 6, iclass 29, count 2 2006.203.07:20:21.39#ibcon#end of sib2, iclass 29, count 2 2006.203.07:20:21.39#ibcon#*after write, iclass 29, count 2 2006.203.07:20:21.39#ibcon#*before return 0, iclass 29, count 2 2006.203.07:20:21.39#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.203.07:20:21.39#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.203.07:20:21.39#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.203.07:20:21.39#ibcon#ireg 7 cls_cnt 0 2006.203.07:20:21.39#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.203.07:20:21.51#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.203.07:20:21.51#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.203.07:20:21.51#ibcon#enter wrdev, iclass 29, count 0 2006.203.07:20:21.51#ibcon#first serial, iclass 29, count 0 2006.203.07:20:21.51#ibcon#enter sib2, iclass 29, count 0 2006.203.07:20:21.51#ibcon#flushed, iclass 29, count 0 2006.203.07:20:21.51#ibcon#about to write, iclass 29, count 0 2006.203.07:20:21.51#ibcon#wrote, iclass 29, count 0 2006.203.07:20:21.51#ibcon#about to read 3, iclass 29, count 0 2006.203.07:20:21.53#ibcon#read 3, iclass 29, count 0 2006.203.07:20:21.53#ibcon#about to read 4, iclass 29, count 0 2006.203.07:20:21.53#ibcon#read 4, iclass 29, count 0 2006.203.07:20:21.53#ibcon#about to read 5, iclass 29, count 0 2006.203.07:20:21.53#ibcon#read 5, iclass 29, count 0 2006.203.07:20:21.53#ibcon#about to read 6, iclass 29, count 0 2006.203.07:20:21.53#ibcon#read 6, iclass 29, count 0 2006.203.07:20:21.53#ibcon#end of sib2, iclass 29, count 0 2006.203.07:20:21.53#ibcon#*mode == 0, iclass 29, count 0 2006.203.07:20:21.53#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.203.07:20:21.53#ibcon#[25=USB\r\n] 2006.203.07:20:21.53#ibcon#*before write, iclass 29, count 0 2006.203.07:20:21.53#ibcon#enter sib2, iclass 29, count 0 2006.203.07:20:21.53#ibcon#flushed, iclass 29, count 0 2006.203.07:20:21.53#ibcon#about to write, iclass 29, count 0 2006.203.07:20:21.53#ibcon#wrote, iclass 29, count 0 2006.203.07:20:21.53#ibcon#about to read 3, iclass 29, count 0 2006.203.07:20:21.56#ibcon#read 3, iclass 29, count 0 2006.203.07:20:21.56#ibcon#about to read 4, iclass 29, count 0 2006.203.07:20:21.56#ibcon#read 4, iclass 29, count 0 2006.203.07:20:21.56#ibcon#about to read 5, iclass 29, count 0 2006.203.07:20:21.56#ibcon#read 5, iclass 29, count 0 2006.203.07:20:21.56#ibcon#about to read 6, iclass 29, count 0 2006.203.07:20:21.56#ibcon#read 6, iclass 29, count 0 2006.203.07:20:21.56#ibcon#end of sib2, iclass 29, count 0 2006.203.07:20:21.56#ibcon#*after write, iclass 29, count 0 2006.203.07:20:21.56#ibcon#*before return 0, iclass 29, count 0 2006.203.07:20:21.56#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.203.07:20:21.56#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.203.07:20:21.56#ibcon#about to clear, iclass 29 cls_cnt 0 2006.203.07:20:21.56#ibcon#cleared, iclass 29 cls_cnt 0 2006.203.07:20:21.56$vc4f8/valo=8,852.99 2006.203.07:20:21.56#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.203.07:20:21.56#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.203.07:20:21.56#ibcon#ireg 17 cls_cnt 0 2006.203.07:20:21.56#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.203.07:20:21.56#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.203.07:20:21.56#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.203.07:20:21.56#ibcon#enter wrdev, iclass 31, count 0 2006.203.07:20:21.56#ibcon#first serial, iclass 31, count 0 2006.203.07:20:21.56#ibcon#enter sib2, iclass 31, count 0 2006.203.07:20:21.56#ibcon#flushed, iclass 31, count 0 2006.203.07:20:21.56#ibcon#about to write, iclass 31, count 0 2006.203.07:20:21.56#ibcon#wrote, iclass 31, count 0 2006.203.07:20:21.56#ibcon#about to read 3, iclass 31, count 0 2006.203.07:20:21.58#ibcon#read 3, iclass 31, count 0 2006.203.07:20:21.58#ibcon#about to read 4, iclass 31, count 0 2006.203.07:20:21.58#ibcon#read 4, iclass 31, count 0 2006.203.07:20:21.58#ibcon#about to read 5, iclass 31, count 0 2006.203.07:20:21.58#ibcon#read 5, iclass 31, count 0 2006.203.07:20:21.58#ibcon#about to read 6, iclass 31, count 0 2006.203.07:20:21.58#ibcon#read 6, iclass 31, count 0 2006.203.07:20:21.58#ibcon#end of sib2, iclass 31, count 0 2006.203.07:20:21.58#ibcon#*mode == 0, iclass 31, count 0 2006.203.07:20:21.58#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.203.07:20:21.58#ibcon#[26=FRQ=08,852.99\r\n] 2006.203.07:20:21.58#ibcon#*before write, iclass 31, count 0 2006.203.07:20:21.58#ibcon#enter sib2, iclass 31, count 0 2006.203.07:20:21.58#ibcon#flushed, iclass 31, count 0 2006.203.07:20:21.58#ibcon#about to write, iclass 31, count 0 2006.203.07:20:21.58#ibcon#wrote, iclass 31, count 0 2006.203.07:20:21.58#ibcon#about to read 3, iclass 31, count 0 2006.203.07:20:21.63#ibcon#read 3, iclass 31, count 0 2006.203.07:20:21.63#ibcon#about to read 4, iclass 31, count 0 2006.203.07:20:21.63#ibcon#read 4, iclass 31, count 0 2006.203.07:20:21.63#ibcon#about to read 5, iclass 31, count 0 2006.203.07:20:21.63#ibcon#read 5, iclass 31, count 0 2006.203.07:20:21.63#ibcon#about to read 6, iclass 31, count 0 2006.203.07:20:21.63#ibcon#read 6, iclass 31, count 0 2006.203.07:20:21.63#ibcon#end of sib2, iclass 31, count 0 2006.203.07:20:21.63#ibcon#*after write, iclass 31, count 0 2006.203.07:20:21.63#ibcon#*before return 0, iclass 31, count 0 2006.203.07:20:21.63#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.203.07:20:21.63#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.203.07:20:21.63#ibcon#about to clear, iclass 31 cls_cnt 0 2006.203.07:20:21.63#ibcon#cleared, iclass 31 cls_cnt 0 2006.203.07:20:21.63$vc4f8/va=8,6 2006.203.07:20:21.63#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.203.07:20:21.63#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.203.07:20:21.63#ibcon#ireg 11 cls_cnt 2 2006.203.07:20:21.63#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.203.07:20:21.68#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.203.07:20:21.68#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.203.07:20:21.68#ibcon#enter wrdev, iclass 33, count 2 2006.203.07:20:21.68#ibcon#first serial, iclass 33, count 2 2006.203.07:20:21.68#ibcon#enter sib2, iclass 33, count 2 2006.203.07:20:21.68#ibcon#flushed, iclass 33, count 2 2006.203.07:20:21.68#ibcon#about to write, iclass 33, count 2 2006.203.07:20:21.68#ibcon#wrote, iclass 33, count 2 2006.203.07:20:21.68#ibcon#about to read 3, iclass 33, count 2 2006.203.07:20:21.70#ibcon#read 3, iclass 33, count 2 2006.203.07:20:21.70#ibcon#about to read 4, iclass 33, count 2 2006.203.07:20:21.70#ibcon#read 4, iclass 33, count 2 2006.203.07:20:21.70#ibcon#about to read 5, iclass 33, count 2 2006.203.07:20:21.70#ibcon#read 5, iclass 33, count 2 2006.203.07:20:21.70#ibcon#about to read 6, iclass 33, count 2 2006.203.07:20:21.70#ibcon#read 6, iclass 33, count 2 2006.203.07:20:21.70#ibcon#end of sib2, iclass 33, count 2 2006.203.07:20:21.70#ibcon#*mode == 0, iclass 33, count 2 2006.203.07:20:21.70#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.203.07:20:21.70#ibcon#[25=AT08-06\r\n] 2006.203.07:20:21.70#ibcon#*before write, iclass 33, count 2 2006.203.07:20:21.70#ibcon#enter sib2, iclass 33, count 2 2006.203.07:20:21.70#ibcon#flushed, iclass 33, count 2 2006.203.07:20:21.70#ibcon#about to write, iclass 33, count 2 2006.203.07:20:21.70#ibcon#wrote, iclass 33, count 2 2006.203.07:20:21.70#ibcon#about to read 3, iclass 33, count 2 2006.203.07:20:21.73#ibcon#read 3, iclass 33, count 2 2006.203.07:20:21.73#ibcon#about to read 4, iclass 33, count 2 2006.203.07:20:21.73#ibcon#read 4, iclass 33, count 2 2006.203.07:20:21.73#ibcon#about to read 5, iclass 33, count 2 2006.203.07:20:21.73#ibcon#read 5, iclass 33, count 2 2006.203.07:20:21.73#ibcon#about to read 6, iclass 33, count 2 2006.203.07:20:21.73#ibcon#read 6, iclass 33, count 2 2006.203.07:20:21.73#ibcon#end of sib2, iclass 33, count 2 2006.203.07:20:21.73#ibcon#*after write, iclass 33, count 2 2006.203.07:20:21.73#ibcon#*before return 0, iclass 33, count 2 2006.203.07:20:21.73#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.203.07:20:21.73#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.203.07:20:21.73#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.203.07:20:21.73#ibcon#ireg 7 cls_cnt 0 2006.203.07:20:21.73#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.203.07:20:21.85#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.203.07:20:21.85#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.203.07:20:21.85#ibcon#enter wrdev, iclass 33, count 0 2006.203.07:20:21.85#ibcon#first serial, iclass 33, count 0 2006.203.07:20:21.85#ibcon#enter sib2, iclass 33, count 0 2006.203.07:20:21.85#ibcon#flushed, iclass 33, count 0 2006.203.07:20:21.85#ibcon#about to write, iclass 33, count 0 2006.203.07:20:21.85#ibcon#wrote, iclass 33, count 0 2006.203.07:20:21.85#ibcon#about to read 3, iclass 33, count 0 2006.203.07:20:21.87#ibcon#read 3, iclass 33, count 0 2006.203.07:20:21.87#ibcon#about to read 4, iclass 33, count 0 2006.203.07:20:21.87#ibcon#read 4, iclass 33, count 0 2006.203.07:20:21.87#ibcon#about to read 5, iclass 33, count 0 2006.203.07:20:21.87#ibcon#read 5, iclass 33, count 0 2006.203.07:20:21.87#ibcon#about to read 6, iclass 33, count 0 2006.203.07:20:21.87#ibcon#read 6, iclass 33, count 0 2006.203.07:20:21.87#ibcon#end of sib2, iclass 33, count 0 2006.203.07:20:21.87#ibcon#*mode == 0, iclass 33, count 0 2006.203.07:20:21.87#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.203.07:20:21.87#ibcon#[25=USB\r\n] 2006.203.07:20:21.87#ibcon#*before write, iclass 33, count 0 2006.203.07:20:21.87#ibcon#enter sib2, iclass 33, count 0 2006.203.07:20:21.87#ibcon#flushed, iclass 33, count 0 2006.203.07:20:21.87#ibcon#about to write, iclass 33, count 0 2006.203.07:20:21.87#ibcon#wrote, iclass 33, count 0 2006.203.07:20:21.87#ibcon#about to read 3, iclass 33, count 0 2006.203.07:20:21.90#ibcon#read 3, iclass 33, count 0 2006.203.07:20:21.90#ibcon#about to read 4, iclass 33, count 0 2006.203.07:20:21.90#ibcon#read 4, iclass 33, count 0 2006.203.07:20:21.90#ibcon#about to read 5, iclass 33, count 0 2006.203.07:20:21.90#ibcon#read 5, iclass 33, count 0 2006.203.07:20:21.90#ibcon#about to read 6, iclass 33, count 0 2006.203.07:20:21.90#ibcon#read 6, iclass 33, count 0 2006.203.07:20:21.90#ibcon#end of sib2, iclass 33, count 0 2006.203.07:20:21.90#ibcon#*after write, iclass 33, count 0 2006.203.07:20:21.90#ibcon#*before return 0, iclass 33, count 0 2006.203.07:20:21.90#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.203.07:20:21.90#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.203.07:20:21.90#ibcon#about to clear, iclass 33 cls_cnt 0 2006.203.07:20:21.90#ibcon#cleared, iclass 33 cls_cnt 0 2006.203.07:20:21.90$vc4f8/vblo=1,632.99 2006.203.07:20:21.90#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.203.07:20:21.90#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.203.07:20:21.90#ibcon#ireg 17 cls_cnt 0 2006.203.07:20:21.90#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.203.07:20:21.90#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.203.07:20:21.90#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.203.07:20:21.90#ibcon#enter wrdev, iclass 35, count 0 2006.203.07:20:21.90#ibcon#first serial, iclass 35, count 0 2006.203.07:20:21.90#ibcon#enter sib2, iclass 35, count 0 2006.203.07:20:21.90#ibcon#flushed, iclass 35, count 0 2006.203.07:20:21.90#ibcon#about to write, iclass 35, count 0 2006.203.07:20:21.90#ibcon#wrote, iclass 35, count 0 2006.203.07:20:21.90#ibcon#about to read 3, iclass 35, count 0 2006.203.07:20:21.92#ibcon#read 3, iclass 35, count 0 2006.203.07:20:21.92#ibcon#about to read 4, iclass 35, count 0 2006.203.07:20:21.92#ibcon#read 4, iclass 35, count 0 2006.203.07:20:21.92#ibcon#about to read 5, iclass 35, count 0 2006.203.07:20:21.92#ibcon#read 5, iclass 35, count 0 2006.203.07:20:21.92#ibcon#about to read 6, iclass 35, count 0 2006.203.07:20:21.92#ibcon#read 6, iclass 35, count 0 2006.203.07:20:21.92#ibcon#end of sib2, iclass 35, count 0 2006.203.07:20:21.92#ibcon#*mode == 0, iclass 35, count 0 2006.203.07:20:21.92#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.203.07:20:21.92#ibcon#[28=FRQ=01,632.99\r\n] 2006.203.07:20:21.92#ibcon#*before write, iclass 35, count 0 2006.203.07:20:21.92#ibcon#enter sib2, iclass 35, count 0 2006.203.07:20:21.92#ibcon#flushed, iclass 35, count 0 2006.203.07:20:21.92#ibcon#about to write, iclass 35, count 0 2006.203.07:20:21.92#ibcon#wrote, iclass 35, count 0 2006.203.07:20:21.92#ibcon#about to read 3, iclass 35, count 0 2006.203.07:20:21.98#ibcon#read 3, iclass 35, count 0 2006.203.07:20:21.98#ibcon#about to read 4, iclass 35, count 0 2006.203.07:20:21.98#ibcon#read 4, iclass 35, count 0 2006.203.07:20:21.98#ibcon#about to read 5, iclass 35, count 0 2006.203.07:20:21.98#ibcon#read 5, iclass 35, count 0 2006.203.07:20:21.98#ibcon#about to read 6, iclass 35, count 0 2006.203.07:20:21.98#ibcon#read 6, iclass 35, count 0 2006.203.07:20:21.98#ibcon#end of sib2, iclass 35, count 0 2006.203.07:20:21.98#ibcon#*after write, iclass 35, count 0 2006.203.07:20:21.98#ibcon#*before return 0, iclass 35, count 0 2006.203.07:20:21.98#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.203.07:20:21.98#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.203.07:20:21.98#ibcon#about to clear, iclass 35 cls_cnt 0 2006.203.07:20:21.98#ibcon#cleared, iclass 35 cls_cnt 0 2006.203.07:20:21.98$vc4f8/vb=1,4 2006.203.07:20:21.98#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.203.07:20:21.98#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.203.07:20:21.98#ibcon#ireg 11 cls_cnt 2 2006.203.07:20:21.98#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.203.07:20:21.98#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.203.07:20:21.98#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.203.07:20:21.98#ibcon#enter wrdev, iclass 37, count 2 2006.203.07:20:21.98#ibcon#first serial, iclass 37, count 2 2006.203.07:20:21.98#ibcon#enter sib2, iclass 37, count 2 2006.203.07:20:21.98#ibcon#flushed, iclass 37, count 2 2006.203.07:20:21.98#ibcon#about to write, iclass 37, count 2 2006.203.07:20:21.98#ibcon#wrote, iclass 37, count 2 2006.203.07:20:21.98#ibcon#about to read 3, iclass 37, count 2 2006.203.07:20:22.00#ibcon#read 3, iclass 37, count 2 2006.203.07:20:22.00#ibcon#about to read 4, iclass 37, count 2 2006.203.07:20:22.00#ibcon#read 4, iclass 37, count 2 2006.203.07:20:22.00#ibcon#about to read 5, iclass 37, count 2 2006.203.07:20:22.00#ibcon#read 5, iclass 37, count 2 2006.203.07:20:22.00#ibcon#about to read 6, iclass 37, count 2 2006.203.07:20:22.00#ibcon#read 6, iclass 37, count 2 2006.203.07:20:22.00#ibcon#end of sib2, iclass 37, count 2 2006.203.07:20:22.00#ibcon#*mode == 0, iclass 37, count 2 2006.203.07:20:22.00#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.203.07:20:22.00#ibcon#[27=AT01-04\r\n] 2006.203.07:20:22.00#ibcon#*before write, iclass 37, count 2 2006.203.07:20:22.00#ibcon#enter sib2, iclass 37, count 2 2006.203.07:20:22.00#ibcon#flushed, iclass 37, count 2 2006.203.07:20:22.00#ibcon#about to write, iclass 37, count 2 2006.203.07:20:22.00#ibcon#wrote, iclass 37, count 2 2006.203.07:20:22.00#ibcon#about to read 3, iclass 37, count 2 2006.203.07:20:22.04#ibcon#read 3, iclass 37, count 2 2006.203.07:20:22.04#ibcon#about to read 4, iclass 37, count 2 2006.203.07:20:22.04#ibcon#read 4, iclass 37, count 2 2006.203.07:20:22.04#ibcon#about to read 5, iclass 37, count 2 2006.203.07:20:22.04#ibcon#read 5, iclass 37, count 2 2006.203.07:20:22.04#ibcon#about to read 6, iclass 37, count 2 2006.203.07:20:22.04#ibcon#read 6, iclass 37, count 2 2006.203.07:20:22.04#ibcon#end of sib2, iclass 37, count 2 2006.203.07:20:22.04#ibcon#*after write, iclass 37, count 2 2006.203.07:20:22.04#ibcon#*before return 0, iclass 37, count 2 2006.203.07:20:22.04#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.203.07:20:22.04#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.203.07:20:22.04#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.203.07:20:22.04#ibcon#ireg 7 cls_cnt 0 2006.203.07:20:22.04#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.203.07:20:22.16#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.203.07:20:22.16#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.203.07:20:22.16#ibcon#enter wrdev, iclass 37, count 0 2006.203.07:20:22.16#ibcon#first serial, iclass 37, count 0 2006.203.07:20:22.16#ibcon#enter sib2, iclass 37, count 0 2006.203.07:20:22.16#ibcon#flushed, iclass 37, count 0 2006.203.07:20:22.16#ibcon#about to write, iclass 37, count 0 2006.203.07:20:22.16#ibcon#wrote, iclass 37, count 0 2006.203.07:20:22.16#ibcon#about to read 3, iclass 37, count 0 2006.203.07:20:22.18#ibcon#read 3, iclass 37, count 0 2006.203.07:20:22.18#ibcon#about to read 4, iclass 37, count 0 2006.203.07:20:22.18#ibcon#read 4, iclass 37, count 0 2006.203.07:20:22.18#ibcon#about to read 5, iclass 37, count 0 2006.203.07:20:22.18#ibcon#read 5, iclass 37, count 0 2006.203.07:20:22.18#ibcon#about to read 6, iclass 37, count 0 2006.203.07:20:22.18#ibcon#read 6, iclass 37, count 0 2006.203.07:20:22.18#ibcon#end of sib2, iclass 37, count 0 2006.203.07:20:22.18#ibcon#*mode == 0, iclass 37, count 0 2006.203.07:20:22.18#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.203.07:20:22.18#ibcon#[27=USB\r\n] 2006.203.07:20:22.18#ibcon#*before write, iclass 37, count 0 2006.203.07:20:22.18#ibcon#enter sib2, iclass 37, count 0 2006.203.07:20:22.18#ibcon#flushed, iclass 37, count 0 2006.203.07:20:22.18#ibcon#about to write, iclass 37, count 0 2006.203.07:20:22.18#ibcon#wrote, iclass 37, count 0 2006.203.07:20:22.18#ibcon#about to read 3, iclass 37, count 0 2006.203.07:20:22.21#ibcon#read 3, iclass 37, count 0 2006.203.07:20:22.21#ibcon#about to read 4, iclass 37, count 0 2006.203.07:20:22.21#ibcon#read 4, iclass 37, count 0 2006.203.07:20:22.21#ibcon#about to read 5, iclass 37, count 0 2006.203.07:20:22.21#ibcon#read 5, iclass 37, count 0 2006.203.07:20:22.21#ibcon#about to read 6, iclass 37, count 0 2006.203.07:20:22.21#ibcon#read 6, iclass 37, count 0 2006.203.07:20:22.21#ibcon#end of sib2, iclass 37, count 0 2006.203.07:20:22.21#ibcon#*after write, iclass 37, count 0 2006.203.07:20:22.21#ibcon#*before return 0, iclass 37, count 0 2006.203.07:20:22.21#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.203.07:20:22.21#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.203.07:20:22.21#ibcon#about to clear, iclass 37 cls_cnt 0 2006.203.07:20:22.21#ibcon#cleared, iclass 37 cls_cnt 0 2006.203.07:20:22.21$vc4f8/vblo=2,640.99 2006.203.07:20:22.21#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.203.07:20:22.21#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.203.07:20:22.21#ibcon#ireg 17 cls_cnt 0 2006.203.07:20:22.21#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.203.07:20:22.21#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.203.07:20:22.21#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.203.07:20:22.21#ibcon#enter wrdev, iclass 39, count 0 2006.203.07:20:22.21#ibcon#first serial, iclass 39, count 0 2006.203.07:20:22.21#ibcon#enter sib2, iclass 39, count 0 2006.203.07:20:22.21#ibcon#flushed, iclass 39, count 0 2006.203.07:20:22.21#ibcon#about to write, iclass 39, count 0 2006.203.07:20:22.21#ibcon#wrote, iclass 39, count 0 2006.203.07:20:22.21#ibcon#about to read 3, iclass 39, count 0 2006.203.07:20:22.23#ibcon#read 3, iclass 39, count 0 2006.203.07:20:22.23#ibcon#about to read 4, iclass 39, count 0 2006.203.07:20:22.23#ibcon#read 4, iclass 39, count 0 2006.203.07:20:22.23#ibcon#about to read 5, iclass 39, count 0 2006.203.07:20:22.23#ibcon#read 5, iclass 39, count 0 2006.203.07:20:22.23#ibcon#about to read 6, iclass 39, count 0 2006.203.07:20:22.23#ibcon#read 6, iclass 39, count 0 2006.203.07:20:22.23#ibcon#end of sib2, iclass 39, count 0 2006.203.07:20:22.23#ibcon#*mode == 0, iclass 39, count 0 2006.203.07:20:22.23#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.203.07:20:22.23#ibcon#[28=FRQ=02,640.99\r\n] 2006.203.07:20:22.23#ibcon#*before write, iclass 39, count 0 2006.203.07:20:22.23#ibcon#enter sib2, iclass 39, count 0 2006.203.07:20:22.23#ibcon#flushed, iclass 39, count 0 2006.203.07:20:22.23#ibcon#about to write, iclass 39, count 0 2006.203.07:20:22.23#ibcon#wrote, iclass 39, count 0 2006.203.07:20:22.23#ibcon#about to read 3, iclass 39, count 0 2006.203.07:20:22.27#ibcon#read 3, iclass 39, count 0 2006.203.07:20:22.27#ibcon#about to read 4, iclass 39, count 0 2006.203.07:20:22.27#ibcon#read 4, iclass 39, count 0 2006.203.07:20:22.27#ibcon#about to read 5, iclass 39, count 0 2006.203.07:20:22.27#ibcon#read 5, iclass 39, count 0 2006.203.07:20:22.27#ibcon#about to read 6, iclass 39, count 0 2006.203.07:20:22.27#ibcon#read 6, iclass 39, count 0 2006.203.07:20:22.27#ibcon#end of sib2, iclass 39, count 0 2006.203.07:20:22.27#ibcon#*after write, iclass 39, count 0 2006.203.07:20:22.27#ibcon#*before return 0, iclass 39, count 0 2006.203.07:20:22.27#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.203.07:20:22.27#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.203.07:20:22.27#ibcon#about to clear, iclass 39 cls_cnt 0 2006.203.07:20:22.27#ibcon#cleared, iclass 39 cls_cnt 0 2006.203.07:20:22.27$vc4f8/vb=2,4 2006.203.07:20:22.27#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.203.07:20:22.27#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.203.07:20:22.27#ibcon#ireg 11 cls_cnt 2 2006.203.07:20:22.27#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.203.07:20:22.33#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.203.07:20:22.33#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.203.07:20:22.33#ibcon#enter wrdev, iclass 3, count 2 2006.203.07:20:22.33#ibcon#first serial, iclass 3, count 2 2006.203.07:20:22.33#ibcon#enter sib2, iclass 3, count 2 2006.203.07:20:22.33#ibcon#flushed, iclass 3, count 2 2006.203.07:20:22.33#ibcon#about to write, iclass 3, count 2 2006.203.07:20:22.33#ibcon#wrote, iclass 3, count 2 2006.203.07:20:22.33#ibcon#about to read 3, iclass 3, count 2 2006.203.07:20:22.35#ibcon#read 3, iclass 3, count 2 2006.203.07:20:22.35#ibcon#about to read 4, iclass 3, count 2 2006.203.07:20:22.35#ibcon#read 4, iclass 3, count 2 2006.203.07:20:22.35#ibcon#about to read 5, iclass 3, count 2 2006.203.07:20:22.35#ibcon#read 5, iclass 3, count 2 2006.203.07:20:22.35#ibcon#about to read 6, iclass 3, count 2 2006.203.07:20:22.35#ibcon#read 6, iclass 3, count 2 2006.203.07:20:22.35#ibcon#end of sib2, iclass 3, count 2 2006.203.07:20:22.35#ibcon#*mode == 0, iclass 3, count 2 2006.203.07:20:22.35#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.203.07:20:22.35#ibcon#[27=AT02-04\r\n] 2006.203.07:20:22.35#ibcon#*before write, iclass 3, count 2 2006.203.07:20:22.35#ibcon#enter sib2, iclass 3, count 2 2006.203.07:20:22.35#ibcon#flushed, iclass 3, count 2 2006.203.07:20:22.35#ibcon#about to write, iclass 3, count 2 2006.203.07:20:22.35#ibcon#wrote, iclass 3, count 2 2006.203.07:20:22.35#ibcon#about to read 3, iclass 3, count 2 2006.203.07:20:22.38#ibcon#read 3, iclass 3, count 2 2006.203.07:20:22.38#ibcon#about to read 4, iclass 3, count 2 2006.203.07:20:22.38#ibcon#read 4, iclass 3, count 2 2006.203.07:20:22.38#ibcon#about to read 5, iclass 3, count 2 2006.203.07:20:22.38#ibcon#read 5, iclass 3, count 2 2006.203.07:20:22.38#ibcon#about to read 6, iclass 3, count 2 2006.203.07:20:22.38#ibcon#read 6, iclass 3, count 2 2006.203.07:20:22.38#ibcon#end of sib2, iclass 3, count 2 2006.203.07:20:22.38#ibcon#*after write, iclass 3, count 2 2006.203.07:20:22.38#ibcon#*before return 0, iclass 3, count 2 2006.203.07:20:22.38#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.203.07:20:22.38#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.203.07:20:22.38#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.203.07:20:22.38#ibcon#ireg 7 cls_cnt 0 2006.203.07:20:22.38#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.203.07:20:22.50#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.203.07:20:22.50#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.203.07:20:22.50#ibcon#enter wrdev, iclass 3, count 0 2006.203.07:20:22.50#ibcon#first serial, iclass 3, count 0 2006.203.07:20:22.50#ibcon#enter sib2, iclass 3, count 0 2006.203.07:20:22.50#ibcon#flushed, iclass 3, count 0 2006.203.07:20:22.50#ibcon#about to write, iclass 3, count 0 2006.203.07:20:22.50#ibcon#wrote, iclass 3, count 0 2006.203.07:20:22.50#ibcon#about to read 3, iclass 3, count 0 2006.203.07:20:22.52#ibcon#read 3, iclass 3, count 0 2006.203.07:20:22.52#ibcon#about to read 4, iclass 3, count 0 2006.203.07:20:22.52#ibcon#read 4, iclass 3, count 0 2006.203.07:20:22.52#ibcon#about to read 5, iclass 3, count 0 2006.203.07:20:22.52#ibcon#read 5, iclass 3, count 0 2006.203.07:20:22.52#ibcon#about to read 6, iclass 3, count 0 2006.203.07:20:22.52#ibcon#read 6, iclass 3, count 0 2006.203.07:20:22.52#ibcon#end of sib2, iclass 3, count 0 2006.203.07:20:22.52#ibcon#*mode == 0, iclass 3, count 0 2006.203.07:20:22.52#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.203.07:20:22.52#ibcon#[27=USB\r\n] 2006.203.07:20:22.52#ibcon#*before write, iclass 3, count 0 2006.203.07:20:22.52#ibcon#enter sib2, iclass 3, count 0 2006.203.07:20:22.52#ibcon#flushed, iclass 3, count 0 2006.203.07:20:22.52#ibcon#about to write, iclass 3, count 0 2006.203.07:20:22.52#ibcon#wrote, iclass 3, count 0 2006.203.07:20:22.52#ibcon#about to read 3, iclass 3, count 0 2006.203.07:20:22.55#ibcon#read 3, iclass 3, count 0 2006.203.07:20:22.55#ibcon#about to read 4, iclass 3, count 0 2006.203.07:20:22.55#ibcon#read 4, iclass 3, count 0 2006.203.07:20:22.55#ibcon#about to read 5, iclass 3, count 0 2006.203.07:20:22.55#ibcon#read 5, iclass 3, count 0 2006.203.07:20:22.55#ibcon#about to read 6, iclass 3, count 0 2006.203.07:20:22.55#ibcon#read 6, iclass 3, count 0 2006.203.07:20:22.55#ibcon#end of sib2, iclass 3, count 0 2006.203.07:20:22.55#ibcon#*after write, iclass 3, count 0 2006.203.07:20:22.55#ibcon#*before return 0, iclass 3, count 0 2006.203.07:20:22.55#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.203.07:20:22.55#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.203.07:20:22.55#ibcon#about to clear, iclass 3 cls_cnt 0 2006.203.07:20:22.55#ibcon#cleared, iclass 3 cls_cnt 0 2006.203.07:20:22.55$vc4f8/vblo=3,656.99 2006.203.07:20:22.55#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.203.07:20:22.55#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.203.07:20:22.55#ibcon#ireg 17 cls_cnt 0 2006.203.07:20:22.55#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.203.07:20:22.55#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.203.07:20:22.55#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.203.07:20:22.55#ibcon#enter wrdev, iclass 5, count 0 2006.203.07:20:22.55#ibcon#first serial, iclass 5, count 0 2006.203.07:20:22.55#ibcon#enter sib2, iclass 5, count 0 2006.203.07:20:22.55#ibcon#flushed, iclass 5, count 0 2006.203.07:20:22.55#ibcon#about to write, iclass 5, count 0 2006.203.07:20:22.55#ibcon#wrote, iclass 5, count 0 2006.203.07:20:22.55#ibcon#about to read 3, iclass 5, count 0 2006.203.07:20:22.57#ibcon#read 3, iclass 5, count 0 2006.203.07:20:22.57#ibcon#about to read 4, iclass 5, count 0 2006.203.07:20:22.57#ibcon#read 4, iclass 5, count 0 2006.203.07:20:22.57#ibcon#about to read 5, iclass 5, count 0 2006.203.07:20:22.57#ibcon#read 5, iclass 5, count 0 2006.203.07:20:22.57#ibcon#about to read 6, iclass 5, count 0 2006.203.07:20:22.57#ibcon#read 6, iclass 5, count 0 2006.203.07:20:22.57#ibcon#end of sib2, iclass 5, count 0 2006.203.07:20:22.57#ibcon#*mode == 0, iclass 5, count 0 2006.203.07:20:22.57#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.203.07:20:22.57#ibcon#[28=FRQ=03,656.99\r\n] 2006.203.07:20:22.57#ibcon#*before write, iclass 5, count 0 2006.203.07:20:22.57#ibcon#enter sib2, iclass 5, count 0 2006.203.07:20:22.57#ibcon#flushed, iclass 5, count 0 2006.203.07:20:22.57#ibcon#about to write, iclass 5, count 0 2006.203.07:20:22.57#ibcon#wrote, iclass 5, count 0 2006.203.07:20:22.57#ibcon#about to read 3, iclass 5, count 0 2006.203.07:20:22.61#ibcon#read 3, iclass 5, count 0 2006.203.07:20:22.61#ibcon#about to read 4, iclass 5, count 0 2006.203.07:20:22.61#ibcon#read 4, iclass 5, count 0 2006.203.07:20:22.61#ibcon#about to read 5, iclass 5, count 0 2006.203.07:20:22.61#ibcon#read 5, iclass 5, count 0 2006.203.07:20:22.61#ibcon#about to read 6, iclass 5, count 0 2006.203.07:20:22.61#ibcon#read 6, iclass 5, count 0 2006.203.07:20:22.61#ibcon#end of sib2, iclass 5, count 0 2006.203.07:20:22.61#ibcon#*after write, iclass 5, count 0 2006.203.07:20:22.61#ibcon#*before return 0, iclass 5, count 0 2006.203.07:20:22.61#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.203.07:20:22.61#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.203.07:20:22.61#ibcon#about to clear, iclass 5 cls_cnt 0 2006.203.07:20:22.61#ibcon#cleared, iclass 5 cls_cnt 0 2006.203.07:20:22.61$vc4f8/vb=3,4 2006.203.07:20:22.61#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.203.07:20:22.61#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.203.07:20:22.61#ibcon#ireg 11 cls_cnt 2 2006.203.07:20:22.61#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.203.07:20:22.67#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.203.07:20:22.67#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.203.07:20:22.67#ibcon#enter wrdev, iclass 7, count 2 2006.203.07:20:22.67#ibcon#first serial, iclass 7, count 2 2006.203.07:20:22.67#ibcon#enter sib2, iclass 7, count 2 2006.203.07:20:22.67#ibcon#flushed, iclass 7, count 2 2006.203.07:20:22.67#ibcon#about to write, iclass 7, count 2 2006.203.07:20:22.67#ibcon#wrote, iclass 7, count 2 2006.203.07:20:22.67#ibcon#about to read 3, iclass 7, count 2 2006.203.07:20:22.69#ibcon#read 3, iclass 7, count 2 2006.203.07:20:22.69#ibcon#about to read 4, iclass 7, count 2 2006.203.07:20:22.69#ibcon#read 4, iclass 7, count 2 2006.203.07:20:22.69#ibcon#about to read 5, iclass 7, count 2 2006.203.07:20:22.69#ibcon#read 5, iclass 7, count 2 2006.203.07:20:22.69#ibcon#about to read 6, iclass 7, count 2 2006.203.07:20:22.69#ibcon#read 6, iclass 7, count 2 2006.203.07:20:22.69#ibcon#end of sib2, iclass 7, count 2 2006.203.07:20:22.69#ibcon#*mode == 0, iclass 7, count 2 2006.203.07:20:22.69#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.203.07:20:22.69#ibcon#[27=AT03-04\r\n] 2006.203.07:20:22.69#ibcon#*before write, iclass 7, count 2 2006.203.07:20:22.69#ibcon#enter sib2, iclass 7, count 2 2006.203.07:20:22.69#ibcon#flushed, iclass 7, count 2 2006.203.07:20:22.69#ibcon#about to write, iclass 7, count 2 2006.203.07:20:22.69#ibcon#wrote, iclass 7, count 2 2006.203.07:20:22.69#ibcon#about to read 3, iclass 7, count 2 2006.203.07:20:22.72#ibcon#read 3, iclass 7, count 2 2006.203.07:20:22.72#ibcon#about to read 4, iclass 7, count 2 2006.203.07:20:22.72#ibcon#read 4, iclass 7, count 2 2006.203.07:20:22.72#ibcon#about to read 5, iclass 7, count 2 2006.203.07:20:22.72#ibcon#read 5, iclass 7, count 2 2006.203.07:20:22.72#ibcon#about to read 6, iclass 7, count 2 2006.203.07:20:22.72#ibcon#read 6, iclass 7, count 2 2006.203.07:20:22.72#ibcon#end of sib2, iclass 7, count 2 2006.203.07:20:22.72#ibcon#*after write, iclass 7, count 2 2006.203.07:20:22.72#ibcon#*before return 0, iclass 7, count 2 2006.203.07:20:22.72#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.203.07:20:22.72#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.203.07:20:22.72#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.203.07:20:22.72#ibcon#ireg 7 cls_cnt 0 2006.203.07:20:22.72#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.203.07:20:22.84#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.203.07:20:22.84#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.203.07:20:22.84#ibcon#enter wrdev, iclass 7, count 0 2006.203.07:20:22.84#ibcon#first serial, iclass 7, count 0 2006.203.07:20:22.84#ibcon#enter sib2, iclass 7, count 0 2006.203.07:20:22.84#ibcon#flushed, iclass 7, count 0 2006.203.07:20:22.84#ibcon#about to write, iclass 7, count 0 2006.203.07:20:22.84#ibcon#wrote, iclass 7, count 0 2006.203.07:20:22.84#ibcon#about to read 3, iclass 7, count 0 2006.203.07:20:22.86#ibcon#read 3, iclass 7, count 0 2006.203.07:20:22.86#ibcon#about to read 4, iclass 7, count 0 2006.203.07:20:22.86#ibcon#read 4, iclass 7, count 0 2006.203.07:20:22.86#ibcon#about to read 5, iclass 7, count 0 2006.203.07:20:22.86#ibcon#read 5, iclass 7, count 0 2006.203.07:20:22.86#ibcon#about to read 6, iclass 7, count 0 2006.203.07:20:22.86#ibcon#read 6, iclass 7, count 0 2006.203.07:20:22.86#ibcon#end of sib2, iclass 7, count 0 2006.203.07:20:22.86#ibcon#*mode == 0, iclass 7, count 0 2006.203.07:20:22.86#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.203.07:20:22.86#ibcon#[27=USB\r\n] 2006.203.07:20:22.86#ibcon#*before write, iclass 7, count 0 2006.203.07:20:22.86#ibcon#enter sib2, iclass 7, count 0 2006.203.07:20:22.86#ibcon#flushed, iclass 7, count 0 2006.203.07:20:22.86#ibcon#about to write, iclass 7, count 0 2006.203.07:20:22.86#ibcon#wrote, iclass 7, count 0 2006.203.07:20:22.86#ibcon#about to read 3, iclass 7, count 0 2006.203.07:20:22.89#ibcon#read 3, iclass 7, count 0 2006.203.07:20:22.89#ibcon#about to read 4, iclass 7, count 0 2006.203.07:20:22.89#ibcon#read 4, iclass 7, count 0 2006.203.07:20:22.89#ibcon#about to read 5, iclass 7, count 0 2006.203.07:20:22.89#ibcon#read 5, iclass 7, count 0 2006.203.07:20:22.89#ibcon#about to read 6, iclass 7, count 0 2006.203.07:20:22.89#ibcon#read 6, iclass 7, count 0 2006.203.07:20:22.89#ibcon#end of sib2, iclass 7, count 0 2006.203.07:20:22.89#ibcon#*after write, iclass 7, count 0 2006.203.07:20:22.89#ibcon#*before return 0, iclass 7, count 0 2006.203.07:20:22.89#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.203.07:20:22.89#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.203.07:20:22.89#ibcon#about to clear, iclass 7 cls_cnt 0 2006.203.07:20:22.89#ibcon#cleared, iclass 7 cls_cnt 0 2006.203.07:20:22.89$vc4f8/vblo=4,712.99 2006.203.07:20:22.89#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.203.07:20:22.89#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.203.07:20:22.89#ibcon#ireg 17 cls_cnt 0 2006.203.07:20:22.89#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.203.07:20:22.89#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.203.07:20:22.89#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.203.07:20:22.89#ibcon#enter wrdev, iclass 11, count 0 2006.203.07:20:22.89#ibcon#first serial, iclass 11, count 0 2006.203.07:20:22.89#ibcon#enter sib2, iclass 11, count 0 2006.203.07:20:22.89#ibcon#flushed, iclass 11, count 0 2006.203.07:20:22.89#ibcon#about to write, iclass 11, count 0 2006.203.07:20:22.89#ibcon#wrote, iclass 11, count 0 2006.203.07:20:22.89#ibcon#about to read 3, iclass 11, count 0 2006.203.07:20:22.91#ibcon#read 3, iclass 11, count 0 2006.203.07:20:22.91#ibcon#about to read 4, iclass 11, count 0 2006.203.07:20:22.91#ibcon#read 4, iclass 11, count 0 2006.203.07:20:22.91#ibcon#about to read 5, iclass 11, count 0 2006.203.07:20:22.91#ibcon#read 5, iclass 11, count 0 2006.203.07:20:22.91#ibcon#about to read 6, iclass 11, count 0 2006.203.07:20:22.91#ibcon#read 6, iclass 11, count 0 2006.203.07:20:22.91#ibcon#end of sib2, iclass 11, count 0 2006.203.07:20:22.91#ibcon#*mode == 0, iclass 11, count 0 2006.203.07:20:22.91#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.203.07:20:22.91#ibcon#[28=FRQ=04,712.99\r\n] 2006.203.07:20:22.91#ibcon#*before write, iclass 11, count 0 2006.203.07:20:22.91#ibcon#enter sib2, iclass 11, count 0 2006.203.07:20:22.91#ibcon#flushed, iclass 11, count 0 2006.203.07:20:22.91#ibcon#about to write, iclass 11, count 0 2006.203.07:20:22.91#ibcon#wrote, iclass 11, count 0 2006.203.07:20:22.91#ibcon#about to read 3, iclass 11, count 0 2006.203.07:20:22.95#ibcon#read 3, iclass 11, count 0 2006.203.07:20:22.95#ibcon#about to read 4, iclass 11, count 0 2006.203.07:20:22.95#ibcon#read 4, iclass 11, count 0 2006.203.07:20:22.95#ibcon#about to read 5, iclass 11, count 0 2006.203.07:20:22.95#ibcon#read 5, iclass 11, count 0 2006.203.07:20:22.95#ibcon#about to read 6, iclass 11, count 0 2006.203.07:20:22.95#ibcon#read 6, iclass 11, count 0 2006.203.07:20:22.95#ibcon#end of sib2, iclass 11, count 0 2006.203.07:20:22.95#ibcon#*after write, iclass 11, count 0 2006.203.07:20:22.95#ibcon#*before return 0, iclass 11, count 0 2006.203.07:20:22.95#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.203.07:20:22.95#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.203.07:20:22.95#ibcon#about to clear, iclass 11 cls_cnt 0 2006.203.07:20:22.95#ibcon#cleared, iclass 11 cls_cnt 0 2006.203.07:20:22.95$vc4f8/vb=4,4 2006.203.07:20:22.95#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.203.07:20:22.95#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.203.07:20:22.95#ibcon#ireg 11 cls_cnt 2 2006.203.07:20:22.95#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.203.07:20:23.01#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.203.07:20:23.01#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.203.07:20:23.01#ibcon#enter wrdev, iclass 13, count 2 2006.203.07:20:23.01#ibcon#first serial, iclass 13, count 2 2006.203.07:20:23.01#ibcon#enter sib2, iclass 13, count 2 2006.203.07:20:23.01#ibcon#flushed, iclass 13, count 2 2006.203.07:20:23.01#ibcon#about to write, iclass 13, count 2 2006.203.07:20:23.01#ibcon#wrote, iclass 13, count 2 2006.203.07:20:23.01#ibcon#about to read 3, iclass 13, count 2 2006.203.07:20:23.03#ibcon#read 3, iclass 13, count 2 2006.203.07:20:23.03#ibcon#about to read 4, iclass 13, count 2 2006.203.07:20:23.03#ibcon#read 4, iclass 13, count 2 2006.203.07:20:23.03#ibcon#about to read 5, iclass 13, count 2 2006.203.07:20:23.03#ibcon#read 5, iclass 13, count 2 2006.203.07:20:23.03#ibcon#about to read 6, iclass 13, count 2 2006.203.07:20:23.03#ibcon#read 6, iclass 13, count 2 2006.203.07:20:23.03#ibcon#end of sib2, iclass 13, count 2 2006.203.07:20:23.03#ibcon#*mode == 0, iclass 13, count 2 2006.203.07:20:23.03#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.203.07:20:23.03#ibcon#[27=AT04-04\r\n] 2006.203.07:20:23.03#ibcon#*before write, iclass 13, count 2 2006.203.07:20:23.03#ibcon#enter sib2, iclass 13, count 2 2006.203.07:20:23.03#ibcon#flushed, iclass 13, count 2 2006.203.07:20:23.03#ibcon#about to write, iclass 13, count 2 2006.203.07:20:23.03#ibcon#wrote, iclass 13, count 2 2006.203.07:20:23.03#ibcon#about to read 3, iclass 13, count 2 2006.203.07:20:23.06#ibcon#read 3, iclass 13, count 2 2006.203.07:20:23.06#ibcon#about to read 4, iclass 13, count 2 2006.203.07:20:23.06#ibcon#read 4, iclass 13, count 2 2006.203.07:20:23.06#ibcon#about to read 5, iclass 13, count 2 2006.203.07:20:23.06#ibcon#read 5, iclass 13, count 2 2006.203.07:20:23.06#ibcon#about to read 6, iclass 13, count 2 2006.203.07:20:23.06#ibcon#read 6, iclass 13, count 2 2006.203.07:20:23.06#ibcon#end of sib2, iclass 13, count 2 2006.203.07:20:23.06#ibcon#*after write, iclass 13, count 2 2006.203.07:20:23.06#ibcon#*before return 0, iclass 13, count 2 2006.203.07:20:23.06#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.203.07:20:23.06#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.203.07:20:23.06#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.203.07:20:23.06#ibcon#ireg 7 cls_cnt 0 2006.203.07:20:23.06#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.203.07:20:23.18#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.203.07:20:23.18#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.203.07:20:23.18#ibcon#enter wrdev, iclass 13, count 0 2006.203.07:20:23.18#ibcon#first serial, iclass 13, count 0 2006.203.07:20:23.18#ibcon#enter sib2, iclass 13, count 0 2006.203.07:20:23.18#ibcon#flushed, iclass 13, count 0 2006.203.07:20:23.18#ibcon#about to write, iclass 13, count 0 2006.203.07:20:23.18#ibcon#wrote, iclass 13, count 0 2006.203.07:20:23.18#ibcon#about to read 3, iclass 13, count 0 2006.203.07:20:23.20#ibcon#read 3, iclass 13, count 0 2006.203.07:20:23.20#ibcon#about to read 4, iclass 13, count 0 2006.203.07:20:23.20#ibcon#read 4, iclass 13, count 0 2006.203.07:20:23.20#ibcon#about to read 5, iclass 13, count 0 2006.203.07:20:23.20#ibcon#read 5, iclass 13, count 0 2006.203.07:20:23.20#ibcon#about to read 6, iclass 13, count 0 2006.203.07:20:23.20#ibcon#read 6, iclass 13, count 0 2006.203.07:20:23.20#ibcon#end of sib2, iclass 13, count 0 2006.203.07:20:23.20#ibcon#*mode == 0, iclass 13, count 0 2006.203.07:20:23.20#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.203.07:20:23.20#ibcon#[27=USB\r\n] 2006.203.07:20:23.20#ibcon#*before write, iclass 13, count 0 2006.203.07:20:23.20#ibcon#enter sib2, iclass 13, count 0 2006.203.07:20:23.20#ibcon#flushed, iclass 13, count 0 2006.203.07:20:23.20#ibcon#about to write, iclass 13, count 0 2006.203.07:20:23.20#ibcon#wrote, iclass 13, count 0 2006.203.07:20:23.20#ibcon#about to read 3, iclass 13, count 0 2006.203.07:20:23.23#ibcon#read 3, iclass 13, count 0 2006.203.07:20:23.23#ibcon#about to read 4, iclass 13, count 0 2006.203.07:20:23.23#ibcon#read 4, iclass 13, count 0 2006.203.07:20:23.23#ibcon#about to read 5, iclass 13, count 0 2006.203.07:20:23.23#ibcon#read 5, iclass 13, count 0 2006.203.07:20:23.23#ibcon#about to read 6, iclass 13, count 0 2006.203.07:20:23.23#ibcon#read 6, iclass 13, count 0 2006.203.07:20:23.23#ibcon#end of sib2, iclass 13, count 0 2006.203.07:20:23.23#ibcon#*after write, iclass 13, count 0 2006.203.07:20:23.23#ibcon#*before return 0, iclass 13, count 0 2006.203.07:20:23.23#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.203.07:20:23.23#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.203.07:20:23.23#ibcon#about to clear, iclass 13 cls_cnt 0 2006.203.07:20:23.23#ibcon#cleared, iclass 13 cls_cnt 0 2006.203.07:20:23.23$vc4f8/vblo=5,744.99 2006.203.07:20:23.23#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.203.07:20:23.23#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.203.07:20:23.23#ibcon#ireg 17 cls_cnt 0 2006.203.07:20:23.23#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.203.07:20:23.23#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.203.07:20:23.23#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.203.07:20:23.23#ibcon#enter wrdev, iclass 15, count 0 2006.203.07:20:23.23#ibcon#first serial, iclass 15, count 0 2006.203.07:20:23.23#ibcon#enter sib2, iclass 15, count 0 2006.203.07:20:23.23#ibcon#flushed, iclass 15, count 0 2006.203.07:20:23.23#ibcon#about to write, iclass 15, count 0 2006.203.07:20:23.23#ibcon#wrote, iclass 15, count 0 2006.203.07:20:23.23#ibcon#about to read 3, iclass 15, count 0 2006.203.07:20:23.25#ibcon#read 3, iclass 15, count 0 2006.203.07:20:23.25#ibcon#about to read 4, iclass 15, count 0 2006.203.07:20:23.25#ibcon#read 4, iclass 15, count 0 2006.203.07:20:23.25#ibcon#about to read 5, iclass 15, count 0 2006.203.07:20:23.25#ibcon#read 5, iclass 15, count 0 2006.203.07:20:23.25#ibcon#about to read 6, iclass 15, count 0 2006.203.07:20:23.25#ibcon#read 6, iclass 15, count 0 2006.203.07:20:23.25#ibcon#end of sib2, iclass 15, count 0 2006.203.07:20:23.25#ibcon#*mode == 0, iclass 15, count 0 2006.203.07:20:23.25#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.203.07:20:23.25#ibcon#[28=FRQ=05,744.99\r\n] 2006.203.07:20:23.25#ibcon#*before write, iclass 15, count 0 2006.203.07:20:23.25#ibcon#enter sib2, iclass 15, count 0 2006.203.07:20:23.25#ibcon#flushed, iclass 15, count 0 2006.203.07:20:23.25#ibcon#about to write, iclass 15, count 0 2006.203.07:20:23.25#ibcon#wrote, iclass 15, count 0 2006.203.07:20:23.25#ibcon#about to read 3, iclass 15, count 0 2006.203.07:20:23.29#ibcon#read 3, iclass 15, count 0 2006.203.07:20:23.29#ibcon#about to read 4, iclass 15, count 0 2006.203.07:20:23.29#ibcon#read 4, iclass 15, count 0 2006.203.07:20:23.29#ibcon#about to read 5, iclass 15, count 0 2006.203.07:20:23.29#ibcon#read 5, iclass 15, count 0 2006.203.07:20:23.29#ibcon#about to read 6, iclass 15, count 0 2006.203.07:20:23.29#ibcon#read 6, iclass 15, count 0 2006.203.07:20:23.29#ibcon#end of sib2, iclass 15, count 0 2006.203.07:20:23.29#ibcon#*after write, iclass 15, count 0 2006.203.07:20:23.29#ibcon#*before return 0, iclass 15, count 0 2006.203.07:20:23.29#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.203.07:20:23.29#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.203.07:20:23.29#ibcon#about to clear, iclass 15 cls_cnt 0 2006.203.07:20:23.29#ibcon#cleared, iclass 15 cls_cnt 0 2006.203.07:20:23.29$vc4f8/vb=5,3 2006.203.07:20:23.29#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.203.07:20:23.29#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.203.07:20:23.29#ibcon#ireg 11 cls_cnt 2 2006.203.07:20:23.29#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.203.07:20:23.35#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.203.07:20:23.35#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.203.07:20:23.35#ibcon#enter wrdev, iclass 17, count 2 2006.203.07:20:23.35#ibcon#first serial, iclass 17, count 2 2006.203.07:20:23.35#ibcon#enter sib2, iclass 17, count 2 2006.203.07:20:23.35#ibcon#flushed, iclass 17, count 2 2006.203.07:20:23.35#ibcon#about to write, iclass 17, count 2 2006.203.07:20:23.35#ibcon#wrote, iclass 17, count 2 2006.203.07:20:23.35#ibcon#about to read 3, iclass 17, count 2 2006.203.07:20:23.37#ibcon#read 3, iclass 17, count 2 2006.203.07:20:23.37#ibcon#about to read 4, iclass 17, count 2 2006.203.07:20:23.37#ibcon#read 4, iclass 17, count 2 2006.203.07:20:23.37#ibcon#about to read 5, iclass 17, count 2 2006.203.07:20:23.37#ibcon#read 5, iclass 17, count 2 2006.203.07:20:23.37#ibcon#about to read 6, iclass 17, count 2 2006.203.07:20:23.37#ibcon#read 6, iclass 17, count 2 2006.203.07:20:23.37#ibcon#end of sib2, iclass 17, count 2 2006.203.07:20:23.37#ibcon#*mode == 0, iclass 17, count 2 2006.203.07:20:23.37#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.203.07:20:23.37#ibcon#[27=AT05-03\r\n] 2006.203.07:20:23.37#ibcon#*before write, iclass 17, count 2 2006.203.07:20:23.37#ibcon#enter sib2, iclass 17, count 2 2006.203.07:20:23.37#ibcon#flushed, iclass 17, count 2 2006.203.07:20:23.37#ibcon#about to write, iclass 17, count 2 2006.203.07:20:23.37#ibcon#wrote, iclass 17, count 2 2006.203.07:20:23.37#ibcon#about to read 3, iclass 17, count 2 2006.203.07:20:23.40#ibcon#read 3, iclass 17, count 2 2006.203.07:20:23.40#ibcon#about to read 4, iclass 17, count 2 2006.203.07:20:23.40#ibcon#read 4, iclass 17, count 2 2006.203.07:20:23.40#ibcon#about to read 5, iclass 17, count 2 2006.203.07:20:23.40#ibcon#read 5, iclass 17, count 2 2006.203.07:20:23.40#ibcon#about to read 6, iclass 17, count 2 2006.203.07:20:23.40#ibcon#read 6, iclass 17, count 2 2006.203.07:20:23.40#ibcon#end of sib2, iclass 17, count 2 2006.203.07:20:23.40#ibcon#*after write, iclass 17, count 2 2006.203.07:20:23.40#ibcon#*before return 0, iclass 17, count 2 2006.203.07:20:23.40#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.203.07:20:23.40#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.203.07:20:23.40#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.203.07:20:23.40#ibcon#ireg 7 cls_cnt 0 2006.203.07:20:23.40#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.203.07:20:23.52#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.203.07:20:23.52#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.203.07:20:23.52#ibcon#enter wrdev, iclass 17, count 0 2006.203.07:20:23.52#ibcon#first serial, iclass 17, count 0 2006.203.07:20:23.52#ibcon#enter sib2, iclass 17, count 0 2006.203.07:20:23.52#ibcon#flushed, iclass 17, count 0 2006.203.07:20:23.52#ibcon#about to write, iclass 17, count 0 2006.203.07:20:23.52#ibcon#wrote, iclass 17, count 0 2006.203.07:20:23.52#ibcon#about to read 3, iclass 17, count 0 2006.203.07:20:23.54#ibcon#read 3, iclass 17, count 0 2006.203.07:20:23.54#ibcon#about to read 4, iclass 17, count 0 2006.203.07:20:23.54#ibcon#read 4, iclass 17, count 0 2006.203.07:20:23.54#ibcon#about to read 5, iclass 17, count 0 2006.203.07:20:23.54#ibcon#read 5, iclass 17, count 0 2006.203.07:20:23.54#ibcon#about to read 6, iclass 17, count 0 2006.203.07:20:23.54#ibcon#read 6, iclass 17, count 0 2006.203.07:20:23.54#ibcon#end of sib2, iclass 17, count 0 2006.203.07:20:23.54#ibcon#*mode == 0, iclass 17, count 0 2006.203.07:20:23.54#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.203.07:20:23.54#ibcon#[27=USB\r\n] 2006.203.07:20:23.54#ibcon#*before write, iclass 17, count 0 2006.203.07:20:23.54#ibcon#enter sib2, iclass 17, count 0 2006.203.07:20:23.54#ibcon#flushed, iclass 17, count 0 2006.203.07:20:23.54#ibcon#about to write, iclass 17, count 0 2006.203.07:20:23.54#ibcon#wrote, iclass 17, count 0 2006.203.07:20:23.54#ibcon#about to read 3, iclass 17, count 0 2006.203.07:20:23.57#ibcon#read 3, iclass 17, count 0 2006.203.07:20:23.57#ibcon#about to read 4, iclass 17, count 0 2006.203.07:20:23.57#ibcon#read 4, iclass 17, count 0 2006.203.07:20:23.57#ibcon#about to read 5, iclass 17, count 0 2006.203.07:20:23.57#ibcon#read 5, iclass 17, count 0 2006.203.07:20:23.57#ibcon#about to read 6, iclass 17, count 0 2006.203.07:20:23.57#ibcon#read 6, iclass 17, count 0 2006.203.07:20:23.57#ibcon#end of sib2, iclass 17, count 0 2006.203.07:20:23.57#ibcon#*after write, iclass 17, count 0 2006.203.07:20:23.57#ibcon#*before return 0, iclass 17, count 0 2006.203.07:20:23.57#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.203.07:20:23.57#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.203.07:20:23.57#ibcon#about to clear, iclass 17 cls_cnt 0 2006.203.07:20:23.57#ibcon#cleared, iclass 17 cls_cnt 0 2006.203.07:20:23.57$vc4f8/vblo=6,752.99 2006.203.07:20:23.57#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.203.07:20:23.57#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.203.07:20:23.57#ibcon#ireg 17 cls_cnt 0 2006.203.07:20:23.57#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.203.07:20:23.57#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.203.07:20:23.57#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.203.07:20:23.57#ibcon#enter wrdev, iclass 19, count 0 2006.203.07:20:23.57#ibcon#first serial, iclass 19, count 0 2006.203.07:20:23.57#ibcon#enter sib2, iclass 19, count 0 2006.203.07:20:23.57#ibcon#flushed, iclass 19, count 0 2006.203.07:20:23.57#ibcon#about to write, iclass 19, count 0 2006.203.07:20:23.57#ibcon#wrote, iclass 19, count 0 2006.203.07:20:23.57#ibcon#about to read 3, iclass 19, count 0 2006.203.07:20:23.59#ibcon#read 3, iclass 19, count 0 2006.203.07:20:23.59#ibcon#about to read 4, iclass 19, count 0 2006.203.07:20:23.59#ibcon#read 4, iclass 19, count 0 2006.203.07:20:23.59#ibcon#about to read 5, iclass 19, count 0 2006.203.07:20:23.59#ibcon#read 5, iclass 19, count 0 2006.203.07:20:23.59#ibcon#about to read 6, iclass 19, count 0 2006.203.07:20:23.59#ibcon#read 6, iclass 19, count 0 2006.203.07:20:23.59#ibcon#end of sib2, iclass 19, count 0 2006.203.07:20:23.59#ibcon#*mode == 0, iclass 19, count 0 2006.203.07:20:23.59#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.203.07:20:23.59#ibcon#[28=FRQ=06,752.99\r\n] 2006.203.07:20:23.59#ibcon#*before write, iclass 19, count 0 2006.203.07:20:23.59#ibcon#enter sib2, iclass 19, count 0 2006.203.07:20:23.59#ibcon#flushed, iclass 19, count 0 2006.203.07:20:23.59#ibcon#about to write, iclass 19, count 0 2006.203.07:20:23.59#ibcon#wrote, iclass 19, count 0 2006.203.07:20:23.59#ibcon#about to read 3, iclass 19, count 0 2006.203.07:20:23.63#ibcon#read 3, iclass 19, count 0 2006.203.07:20:23.63#ibcon#about to read 4, iclass 19, count 0 2006.203.07:20:23.63#ibcon#read 4, iclass 19, count 0 2006.203.07:20:23.63#ibcon#about to read 5, iclass 19, count 0 2006.203.07:20:23.63#ibcon#read 5, iclass 19, count 0 2006.203.07:20:23.63#ibcon#about to read 6, iclass 19, count 0 2006.203.07:20:23.63#ibcon#read 6, iclass 19, count 0 2006.203.07:20:23.63#ibcon#end of sib2, iclass 19, count 0 2006.203.07:20:23.63#ibcon#*after write, iclass 19, count 0 2006.203.07:20:23.63#ibcon#*before return 0, iclass 19, count 0 2006.203.07:20:23.63#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.203.07:20:23.63#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.203.07:20:23.63#ibcon#about to clear, iclass 19 cls_cnt 0 2006.203.07:20:23.63#ibcon#cleared, iclass 19 cls_cnt 0 2006.203.07:20:23.63$vc4f8/vb=6,4 2006.203.07:20:23.63#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.203.07:20:23.63#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.203.07:20:23.63#ibcon#ireg 11 cls_cnt 2 2006.203.07:20:23.63#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.203.07:20:23.69#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.203.07:20:23.69#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.203.07:20:23.69#ibcon#enter wrdev, iclass 21, count 2 2006.203.07:20:23.69#ibcon#first serial, iclass 21, count 2 2006.203.07:20:23.69#ibcon#enter sib2, iclass 21, count 2 2006.203.07:20:23.69#ibcon#flushed, iclass 21, count 2 2006.203.07:20:23.69#ibcon#about to write, iclass 21, count 2 2006.203.07:20:23.69#ibcon#wrote, iclass 21, count 2 2006.203.07:20:23.69#ibcon#about to read 3, iclass 21, count 2 2006.203.07:20:23.71#ibcon#read 3, iclass 21, count 2 2006.203.07:20:23.71#ibcon#about to read 4, iclass 21, count 2 2006.203.07:20:23.71#ibcon#read 4, iclass 21, count 2 2006.203.07:20:23.71#ibcon#about to read 5, iclass 21, count 2 2006.203.07:20:23.71#ibcon#read 5, iclass 21, count 2 2006.203.07:20:23.71#ibcon#about to read 6, iclass 21, count 2 2006.203.07:20:23.71#ibcon#read 6, iclass 21, count 2 2006.203.07:20:23.71#ibcon#end of sib2, iclass 21, count 2 2006.203.07:20:23.71#ibcon#*mode == 0, iclass 21, count 2 2006.203.07:20:23.71#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.203.07:20:23.71#ibcon#[27=AT06-04\r\n] 2006.203.07:20:23.71#ibcon#*before write, iclass 21, count 2 2006.203.07:20:23.71#ibcon#enter sib2, iclass 21, count 2 2006.203.07:20:23.71#ibcon#flushed, iclass 21, count 2 2006.203.07:20:23.71#ibcon#about to write, iclass 21, count 2 2006.203.07:20:23.71#ibcon#wrote, iclass 21, count 2 2006.203.07:20:23.71#ibcon#about to read 3, iclass 21, count 2 2006.203.07:20:23.74#ibcon#read 3, iclass 21, count 2 2006.203.07:20:23.74#ibcon#about to read 4, iclass 21, count 2 2006.203.07:20:23.74#ibcon#read 4, iclass 21, count 2 2006.203.07:20:23.74#ibcon#about to read 5, iclass 21, count 2 2006.203.07:20:23.74#ibcon#read 5, iclass 21, count 2 2006.203.07:20:23.74#ibcon#about to read 6, iclass 21, count 2 2006.203.07:20:23.74#ibcon#read 6, iclass 21, count 2 2006.203.07:20:23.74#ibcon#end of sib2, iclass 21, count 2 2006.203.07:20:23.74#ibcon#*after write, iclass 21, count 2 2006.203.07:20:23.74#ibcon#*before return 0, iclass 21, count 2 2006.203.07:20:23.74#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.203.07:20:23.74#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.203.07:20:23.74#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.203.07:20:23.74#ibcon#ireg 7 cls_cnt 0 2006.203.07:20:23.74#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.203.07:20:23.80#abcon#<5=/04 1.7 3.5 24.19 971000.9\r\n> 2006.203.07:20:23.82#abcon#{5=INTERFACE CLEAR} 2006.203.07:20:23.86#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.203.07:20:23.86#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.203.07:20:23.86#ibcon#enter wrdev, iclass 21, count 0 2006.203.07:20:23.86#ibcon#first serial, iclass 21, count 0 2006.203.07:20:23.86#ibcon#enter sib2, iclass 21, count 0 2006.203.07:20:23.86#ibcon#flushed, iclass 21, count 0 2006.203.07:20:23.86#ibcon#about to write, iclass 21, count 0 2006.203.07:20:23.86#ibcon#wrote, iclass 21, count 0 2006.203.07:20:23.86#ibcon#about to read 3, iclass 21, count 0 2006.203.07:20:23.88#ibcon#read 3, iclass 21, count 0 2006.203.07:20:23.88#ibcon#about to read 4, iclass 21, count 0 2006.203.07:20:23.88#ibcon#read 4, iclass 21, count 0 2006.203.07:20:23.88#ibcon#about to read 5, iclass 21, count 0 2006.203.07:20:23.88#ibcon#read 5, iclass 21, count 0 2006.203.07:20:23.88#ibcon#about to read 6, iclass 21, count 0 2006.203.07:20:23.88#ibcon#read 6, iclass 21, count 0 2006.203.07:20:23.88#ibcon#end of sib2, iclass 21, count 0 2006.203.07:20:23.88#ibcon#*mode == 0, iclass 21, count 0 2006.203.07:20:23.88#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.203.07:20:23.88#ibcon#[27=USB\r\n] 2006.203.07:20:23.88#ibcon#*before write, iclass 21, count 0 2006.203.07:20:23.88#ibcon#enter sib2, iclass 21, count 0 2006.203.07:20:23.88#ibcon#flushed, iclass 21, count 0 2006.203.07:20:23.88#ibcon#about to write, iclass 21, count 0 2006.203.07:20:23.88#ibcon#wrote, iclass 21, count 0 2006.203.07:20:23.88#ibcon#about to read 3, iclass 21, count 0 2006.203.07:20:23.88#abcon#[5=S1D000X0/0*\r\n] 2006.203.07:20:23.91#ibcon#read 3, iclass 21, count 0 2006.203.07:20:23.91#ibcon#about to read 4, iclass 21, count 0 2006.203.07:20:23.91#ibcon#read 4, iclass 21, count 0 2006.203.07:20:23.91#ibcon#about to read 5, iclass 21, count 0 2006.203.07:20:23.91#ibcon#read 5, iclass 21, count 0 2006.203.07:20:23.91#ibcon#about to read 6, iclass 21, count 0 2006.203.07:20:23.91#ibcon#read 6, iclass 21, count 0 2006.203.07:20:23.91#ibcon#end of sib2, iclass 21, count 0 2006.203.07:20:23.91#ibcon#*after write, iclass 21, count 0 2006.203.07:20:23.91#ibcon#*before return 0, iclass 21, count 0 2006.203.07:20:23.91#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.203.07:20:23.91#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.203.07:20:23.91#ibcon#about to clear, iclass 21 cls_cnt 0 2006.203.07:20:23.91#ibcon#cleared, iclass 21 cls_cnt 0 2006.203.07:20:23.91$vc4f8/vabw=wide 2006.203.07:20:23.91#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.203.07:20:23.91#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.203.07:20:23.91#ibcon#ireg 8 cls_cnt 0 2006.203.07:20:23.91#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:20:23.91#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:20:23.91#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:20:23.91#ibcon#enter wrdev, iclass 27, count 0 2006.203.07:20:23.91#ibcon#first serial, iclass 27, count 0 2006.203.07:20:23.91#ibcon#enter sib2, iclass 27, count 0 2006.203.07:20:23.91#ibcon#flushed, iclass 27, count 0 2006.203.07:20:23.91#ibcon#about to write, iclass 27, count 0 2006.203.07:20:23.91#ibcon#wrote, iclass 27, count 0 2006.203.07:20:23.91#ibcon#about to read 3, iclass 27, count 0 2006.203.07:20:23.93#ibcon#read 3, iclass 27, count 0 2006.203.07:20:23.93#ibcon#about to read 4, iclass 27, count 0 2006.203.07:20:23.93#ibcon#read 4, iclass 27, count 0 2006.203.07:20:23.93#ibcon#about to read 5, iclass 27, count 0 2006.203.07:20:23.93#ibcon#read 5, iclass 27, count 0 2006.203.07:20:23.93#ibcon#about to read 6, iclass 27, count 0 2006.203.07:20:23.93#ibcon#read 6, iclass 27, count 0 2006.203.07:20:23.93#ibcon#end of sib2, iclass 27, count 0 2006.203.07:20:23.93#ibcon#*mode == 0, iclass 27, count 0 2006.203.07:20:23.93#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.203.07:20:23.93#ibcon#[25=BW32\r\n] 2006.203.07:20:23.93#ibcon#*before write, iclass 27, count 0 2006.203.07:20:23.93#ibcon#enter sib2, iclass 27, count 0 2006.203.07:20:23.93#ibcon#flushed, iclass 27, count 0 2006.203.07:20:23.93#ibcon#about to write, iclass 27, count 0 2006.203.07:20:23.93#ibcon#wrote, iclass 27, count 0 2006.203.07:20:23.93#ibcon#about to read 3, iclass 27, count 0 2006.203.07:20:23.96#ibcon#read 3, iclass 27, count 0 2006.203.07:20:23.96#ibcon#about to read 4, iclass 27, count 0 2006.203.07:20:23.96#ibcon#read 4, iclass 27, count 0 2006.203.07:20:23.96#ibcon#about to read 5, iclass 27, count 0 2006.203.07:20:23.96#ibcon#read 5, iclass 27, count 0 2006.203.07:20:23.96#ibcon#about to read 6, iclass 27, count 0 2006.203.07:20:23.96#ibcon#read 6, iclass 27, count 0 2006.203.07:20:23.96#ibcon#end of sib2, iclass 27, count 0 2006.203.07:20:23.96#ibcon#*after write, iclass 27, count 0 2006.203.07:20:23.96#ibcon#*before return 0, iclass 27, count 0 2006.203.07:20:23.96#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:20:23.96#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:20:23.96#ibcon#about to clear, iclass 27 cls_cnt 0 2006.203.07:20:23.96#ibcon#cleared, iclass 27 cls_cnt 0 2006.203.07:20:23.96$vc4f8/vbbw=wide 2006.203.07:20:23.96#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.203.07:20:23.96#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.203.07:20:23.96#ibcon#ireg 8 cls_cnt 0 2006.203.07:20:23.96#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.203.07:20:24.03#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.203.07:20:24.03#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.203.07:20:24.03#ibcon#enter wrdev, iclass 29, count 0 2006.203.07:20:24.03#ibcon#first serial, iclass 29, count 0 2006.203.07:20:24.03#ibcon#enter sib2, iclass 29, count 0 2006.203.07:20:24.03#ibcon#flushed, iclass 29, count 0 2006.203.07:20:24.03#ibcon#about to write, iclass 29, count 0 2006.203.07:20:24.03#ibcon#wrote, iclass 29, count 0 2006.203.07:20:24.03#ibcon#about to read 3, iclass 29, count 0 2006.203.07:20:24.05#ibcon#read 3, iclass 29, count 0 2006.203.07:20:24.05#ibcon#about to read 4, iclass 29, count 0 2006.203.07:20:24.05#ibcon#read 4, iclass 29, count 0 2006.203.07:20:24.05#ibcon#about to read 5, iclass 29, count 0 2006.203.07:20:24.05#ibcon#read 5, iclass 29, count 0 2006.203.07:20:24.05#ibcon#about to read 6, iclass 29, count 0 2006.203.07:20:24.05#ibcon#read 6, iclass 29, count 0 2006.203.07:20:24.05#ibcon#end of sib2, iclass 29, count 0 2006.203.07:20:24.05#ibcon#*mode == 0, iclass 29, count 0 2006.203.07:20:24.05#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.203.07:20:24.05#ibcon#[27=BW32\r\n] 2006.203.07:20:24.05#ibcon#*before write, iclass 29, count 0 2006.203.07:20:24.05#ibcon#enter sib2, iclass 29, count 0 2006.203.07:20:24.05#ibcon#flushed, iclass 29, count 0 2006.203.07:20:24.05#ibcon#about to write, iclass 29, count 0 2006.203.07:20:24.05#ibcon#wrote, iclass 29, count 0 2006.203.07:20:24.05#ibcon#about to read 3, iclass 29, count 0 2006.203.07:20:24.08#ibcon#read 3, iclass 29, count 0 2006.203.07:20:24.08#ibcon#about to read 4, iclass 29, count 0 2006.203.07:20:24.08#ibcon#read 4, iclass 29, count 0 2006.203.07:20:24.08#ibcon#about to read 5, iclass 29, count 0 2006.203.07:20:24.08#ibcon#read 5, iclass 29, count 0 2006.203.07:20:24.08#ibcon#about to read 6, iclass 29, count 0 2006.203.07:20:24.08#ibcon#read 6, iclass 29, count 0 2006.203.07:20:24.08#ibcon#end of sib2, iclass 29, count 0 2006.203.07:20:24.08#ibcon#*after write, iclass 29, count 0 2006.203.07:20:24.08#ibcon#*before return 0, iclass 29, count 0 2006.203.07:20:24.08#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.203.07:20:24.08#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.203.07:20:24.08#ibcon#about to clear, iclass 29 cls_cnt 0 2006.203.07:20:24.08#ibcon#cleared, iclass 29 cls_cnt 0 2006.203.07:20:24.08$4f8m12a/ifd4f 2006.203.07:20:24.08&ifd4f/lo= 2006.203.07:20:24.08&ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.203.07:20:24.08&ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.203.07:20:24.08&ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.203.07:20:24.08&ifd4f/patch= 2006.203.07:20:24.08&ifd4f/patch=lo1,a1,a2,a3,a4 2006.203.07:20:24.08&ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.203.07:20:24.08&ifd4f/patch=lo3,a5,a6,a7,a8 2006.203.07:20:24.08$ifd4f/lo= 2006.203.07:20:24.08$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.203.07:20:24.08$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.203.07:20:24.08$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.203.07:20:24.08$ifd4f/patch= 2006.203.07:20:24.08$ifd4f/patch=lo1,a1,a2,a3,a4 2006.203.07:20:24.08$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.203.07:20:24.08$ifd4f/patch=lo3,a5,a6,a7,a8 2006.203.07:20:24.08$4f8m12a/"form=m,16.000,1:2 2006.203.07:20:24.08$4f8m12a/"tpicd 2006.203.07:20:24.08$4f8m12a/echo=off 2006.203.07:20:24.08$4f8m12a/xlog=off 2006.203.07:20:24.08:!2006.203.07:29:50 2006.203.07:20:44.14#trakl#Source acquired 2006.203.07:20:44.14#flagr#flagr/antenna,acquired 2006.203.07:29:50.02:preob 2006.203.07:29:50.02&preob/onsource 2006.203.07:29:51.14/onsource/TRACKING 2006.203.07:29:51.14:!2006.203.07:30:00 2006.203.07:30:00.02:data_valid=on 2006.203.07:30:00.02:midob 2006.203.07:30:00.02&midob/onsource 2006.203.07:30:00.02&midob/wx 2006.203.07:30:00.02&midob/cable 2006.203.07:30:00.02&midob/va 2006.203.07:30:00.02&midob/valo 2006.203.07:30:00.02&midob/vb 2006.203.07:30:00.02&midob/vblo 2006.203.07:30:00.02&midob/vabw 2006.203.07:30:00.02&midob/vbbw 2006.203.07:30:00.02&midob/"form 2006.203.07:30:00.02&midob/xfe 2006.203.07:30:00.02&midob/ifatt 2006.203.07:30:00.02&midob/clockoff 2006.203.07:30:00.02&midob/sy=logmail 2006.203.07:30:00.02&midob/"sy=run setcl adapt & 2006.203.07:30:01.14/onsource/TRACKING 2006.203.07:30:01.14/wx/24.15,1000.9,97 2006.203.07:30:01.22/cable/+6.4584E-03 2006.203.07:30:02.31/va/01,08,usb,yes,33,35 2006.203.07:30:02.31/va/02,07,usb,yes,33,34 2006.203.07:30:02.31/va/03,08,usb,yes,25,25 2006.203.07:30:02.31/va/04,07,usb,yes,34,36 2006.203.07:30:02.31/va/05,07,usb,yes,37,39 2006.203.07:30:02.32/va/06,06,usb,yes,36,35 2006.203.07:30:02.32/va/07,07,usb,yes,32,31 2006.203.07:30:02.32/va/08,06,usb,yes,39,38 2006.203.07:30:02.54/valo/01,532.99,yes,locked 2006.203.07:30:02.55/valo/02,572.99,yes,locked 2006.203.07:30:02.55/valo/03,672.99,yes,locked 2006.203.07:30:02.55/valo/04,832.99,yes,locked 2006.203.07:30:02.55/valo/05,652.99,yes,locked 2006.203.07:30:02.55/valo/06,772.99,yes,locked 2006.203.07:30:02.55/valo/07,832.99,yes,locked 2006.203.07:30:02.55/valo/08,852.99,yes,locked 2006.203.07:30:03.63/vb/01,04,usb,yes,31,29 2006.203.07:30:03.63/vb/02,04,usb,yes,33,34 2006.203.07:30:03.63/vb/03,04,usb,yes,29,33 2006.203.07:30:03.63/vb/04,04,usb,yes,30,30 2006.203.07:30:03.63/vb/05,03,usb,yes,36,40 2006.203.07:30:03.63/vb/06,04,usb,yes,30,32 2006.203.07:30:03.63/vb/07,04,usb,yes,32,32 2006.203.07:30:03.63/vb/08,04,usb,yes,29,33 2006.203.07:30:03.87/vblo/01,632.99,yes,locked 2006.203.07:30:03.87/vblo/02,640.99,yes,locked 2006.203.07:30:03.88/vblo/03,656.99,yes,locked 2006.203.07:30:03.88/vblo/04,712.99,yes,locked 2006.203.07:30:03.88/vblo/05,744.99,yes,locked 2006.203.07:30:03.88/vblo/06,752.99,yes,locked 2006.203.07:30:03.88/vblo/07,734.99,yes,locked 2006.203.07:30:03.88/vblo/08,744.99,yes,locked 2006.203.07:30:04.02/vabw/8 2006.203.07:30:04.17/vbbw/8 2006.203.07:30:04.30/xfe/off,on,16.5 2006.203.07:30:04.68/ifatt/23,28,28,28 2006.203.07:30:05.07/fmout-gps/S +4.56E-07 2006.203.07:30:05.16:!2006.203.07:31:00 2006.203.07:31:00.02:data_valid=off 2006.203.07:31:00.02:postob 2006.203.07:31:00.02&postob/cable 2006.203.07:31:00.03&postob/wx 2006.203.07:31:00.03&postob/clockoff 2006.203.07:31:00.25/cable/+6.4582E-03 2006.203.07:31:00.26/wx/24.13,1000.9,97 2006.203.07:31:00.34/fmout-gps/S +4.57E-07 2006.203.07:31:00.34:scan_name=203-0733,k06203,60 2006.203.07:31:00.35:source=0808+019,081126.71,014652.2,2000.0,ccw 2006.203.07:31:01.14#flagr#flagr/antenna,new-source 2006.203.07:31:01.14:checkk5 2006.203.07:31:01.14&checkk5/chk_autoobs=1 2006.203.07:31:01.15&checkk5/chk_autoobs=2 2006.203.07:31:01.15&checkk5/chk_autoobs=3 2006.203.07:31:01.15&checkk5/chk_autoobs=4 2006.203.07:31:01.16&checkk5/chk_obsdata=1 2006.203.07:31:01.16&checkk5/chk_obsdata=2 2006.203.07:31:01.16&checkk5/chk_obsdata=3 2006.203.07:31:01.17&checkk5/chk_obsdata=4 2006.203.07:31:01.17&checkk5/k5log=1 2006.203.07:31:01.17&checkk5/k5log=2 2006.203.07:31:01.22&checkk5/k5log=3 2006.203.07:31:01.23&checkk5/k5log=4 2006.203.07:31:01.23&checkk5/obsinfo 2006.203.07:31:01.72/chk_autoobs//k5ts1/ autoobs is running! 2006.203.07:31:02.17/chk_autoobs//k5ts2/ autoobs is running! 2006.203.07:31:02.66/chk_autoobs//k5ts3/ autoobs is running! 2006.203.07:31:03.07/chk_autoobs//k5ts4/ autoobs is running! 2006.203.07:31:03.49/chk_obsdata//k5ts1/T2030730??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.07:31:03.91/chk_obsdata//k5ts2/T2030730??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.07:31:04.35/chk_obsdata//k5ts3/T2030730??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.07:31:04.75/chk_obsdata//k5ts4/T2030730??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.07:31:05.55/k5log//k5ts1_log_newline 2006.203.07:31:06.38/k5log//k5ts2_log_newline 2006.203.07:31:07.52/k5log//k5ts3_log_newline 2006.203.07:31:08.38/k5log//k5ts4_log_newline 2006.203.07:31:08.40/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.203.07:31:08.40:4f8m12a=1 2006.203.07:31:08.40$4f8m12a/echo=on 2006.203.07:31:08.40$4f8m12a/pcalon 2006.203.07:31:08.40$pcalon/"no phase cal control is implemented here 2006.203.07:31:08.40$4f8m12a/"tpicd=stop 2006.203.07:31:08.40$4f8m12a/vc4f8 2006.203.07:31:08.40$vc4f8/valo=1,532.99 2006.203.07:31:08.41#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.203.07:31:08.41#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.203.07:31:08.41#ibcon#ireg 17 cls_cnt 0 2006.203.07:31:08.41#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.203.07:31:08.41#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.203.07:31:08.41#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.203.07:31:08.41#ibcon#enter wrdev, iclass 32, count 0 2006.203.07:31:08.41#ibcon#first serial, iclass 32, count 0 2006.203.07:31:08.41#ibcon#enter sib2, iclass 32, count 0 2006.203.07:31:08.41#ibcon#flushed, iclass 32, count 0 2006.203.07:31:08.41#ibcon#about to write, iclass 32, count 0 2006.203.07:31:08.41#ibcon#wrote, iclass 32, count 0 2006.203.07:31:08.41#ibcon#about to read 3, iclass 32, count 0 2006.203.07:31:08.45#ibcon#read 3, iclass 32, count 0 2006.203.07:31:08.45#ibcon#about to read 4, iclass 32, count 0 2006.203.07:31:08.45#ibcon#read 4, iclass 32, count 0 2006.203.07:31:08.45#ibcon#about to read 5, iclass 32, count 0 2006.203.07:31:08.45#ibcon#read 5, iclass 32, count 0 2006.203.07:31:08.45#ibcon#about to read 6, iclass 32, count 0 2006.203.07:31:08.45#ibcon#read 6, iclass 32, count 0 2006.203.07:31:08.45#ibcon#end of sib2, iclass 32, count 0 2006.203.07:31:08.45#ibcon#*mode == 0, iclass 32, count 0 2006.203.07:31:08.45#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.203.07:31:08.45#ibcon#[26=FRQ=01,532.99\r\n] 2006.203.07:31:08.45#ibcon#*before write, iclass 32, count 0 2006.203.07:31:08.45#ibcon#enter sib2, iclass 32, count 0 2006.203.07:31:08.45#ibcon#flushed, iclass 32, count 0 2006.203.07:31:08.45#ibcon#about to write, iclass 32, count 0 2006.203.07:31:08.45#ibcon#wrote, iclass 32, count 0 2006.203.07:31:08.45#ibcon#about to read 3, iclass 32, count 0 2006.203.07:31:08.49#ibcon#read 3, iclass 32, count 0 2006.203.07:31:08.49#ibcon#about to read 4, iclass 32, count 0 2006.203.07:31:08.49#ibcon#read 4, iclass 32, count 0 2006.203.07:31:08.49#ibcon#about to read 5, iclass 32, count 0 2006.203.07:31:08.49#ibcon#read 5, iclass 32, count 0 2006.203.07:31:08.49#ibcon#about to read 6, iclass 32, count 0 2006.203.07:31:08.49#ibcon#read 6, iclass 32, count 0 2006.203.07:31:08.49#ibcon#end of sib2, iclass 32, count 0 2006.203.07:31:08.49#ibcon#*after write, iclass 32, count 0 2006.203.07:31:08.49#ibcon#*before return 0, iclass 32, count 0 2006.203.07:31:08.49#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.203.07:31:08.49#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.203.07:31:08.49#ibcon#about to clear, iclass 32 cls_cnt 0 2006.203.07:31:08.49#ibcon#cleared, iclass 32 cls_cnt 0 2006.203.07:31:08.50$vc4f8/va=1,8 2006.203.07:31:08.50#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.203.07:31:08.50#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.203.07:31:08.50#ibcon#ireg 11 cls_cnt 2 2006.203.07:31:08.50#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.203.07:31:08.50#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.203.07:31:08.50#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.203.07:31:08.50#ibcon#enter wrdev, iclass 34, count 2 2006.203.07:31:08.50#ibcon#first serial, iclass 34, count 2 2006.203.07:31:08.50#ibcon#enter sib2, iclass 34, count 2 2006.203.07:31:08.50#ibcon#flushed, iclass 34, count 2 2006.203.07:31:08.50#ibcon#about to write, iclass 34, count 2 2006.203.07:31:08.50#ibcon#wrote, iclass 34, count 2 2006.203.07:31:08.50#ibcon#about to read 3, iclass 34, count 2 2006.203.07:31:08.51#ibcon#read 3, iclass 34, count 2 2006.203.07:31:08.51#ibcon#about to read 4, iclass 34, count 2 2006.203.07:31:08.51#ibcon#read 4, iclass 34, count 2 2006.203.07:31:08.51#ibcon#about to read 5, iclass 34, count 2 2006.203.07:31:08.51#ibcon#read 5, iclass 34, count 2 2006.203.07:31:08.51#ibcon#about to read 6, iclass 34, count 2 2006.203.07:31:08.51#ibcon#read 6, iclass 34, count 2 2006.203.07:31:08.51#ibcon#end of sib2, iclass 34, count 2 2006.203.07:31:08.51#ibcon#*mode == 0, iclass 34, count 2 2006.203.07:31:08.51#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.203.07:31:08.51#ibcon#[25=AT01-08\r\n] 2006.203.07:31:08.51#ibcon#*before write, iclass 34, count 2 2006.203.07:31:08.51#ibcon#enter sib2, iclass 34, count 2 2006.203.07:31:08.51#ibcon#flushed, iclass 34, count 2 2006.203.07:31:08.51#ibcon#about to write, iclass 34, count 2 2006.203.07:31:08.51#ibcon#wrote, iclass 34, count 2 2006.203.07:31:08.51#ibcon#about to read 3, iclass 34, count 2 2006.203.07:31:08.54#ibcon#read 3, iclass 34, count 2 2006.203.07:31:08.54#ibcon#about to read 4, iclass 34, count 2 2006.203.07:31:08.54#ibcon#read 4, iclass 34, count 2 2006.203.07:31:08.54#ibcon#about to read 5, iclass 34, count 2 2006.203.07:31:08.54#ibcon#read 5, iclass 34, count 2 2006.203.07:31:08.54#ibcon#about to read 6, iclass 34, count 2 2006.203.07:31:08.54#ibcon#read 6, iclass 34, count 2 2006.203.07:31:08.54#ibcon#end of sib2, iclass 34, count 2 2006.203.07:31:08.54#ibcon#*after write, iclass 34, count 2 2006.203.07:31:08.54#ibcon#*before return 0, iclass 34, count 2 2006.203.07:31:08.54#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.203.07:31:08.54#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.203.07:31:08.54#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.203.07:31:08.54#ibcon#ireg 7 cls_cnt 0 2006.203.07:31:08.54#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.203.07:31:08.67#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.203.07:31:08.67#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.203.07:31:08.67#ibcon#enter wrdev, iclass 34, count 0 2006.203.07:31:08.67#ibcon#first serial, iclass 34, count 0 2006.203.07:31:08.67#ibcon#enter sib2, iclass 34, count 0 2006.203.07:31:08.67#ibcon#flushed, iclass 34, count 0 2006.203.07:31:08.67#ibcon#about to write, iclass 34, count 0 2006.203.07:31:08.67#ibcon#wrote, iclass 34, count 0 2006.203.07:31:08.67#ibcon#about to read 3, iclass 34, count 0 2006.203.07:31:08.68#ibcon#read 3, iclass 34, count 0 2006.203.07:31:08.68#ibcon#about to read 4, iclass 34, count 0 2006.203.07:31:08.68#ibcon#read 4, iclass 34, count 0 2006.203.07:31:08.68#ibcon#about to read 5, iclass 34, count 0 2006.203.07:31:08.68#ibcon#read 5, iclass 34, count 0 2006.203.07:31:08.68#ibcon#about to read 6, iclass 34, count 0 2006.203.07:31:08.68#ibcon#read 6, iclass 34, count 0 2006.203.07:31:08.68#ibcon#end of sib2, iclass 34, count 0 2006.203.07:31:08.68#ibcon#*mode == 0, iclass 34, count 0 2006.203.07:31:08.68#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.203.07:31:08.68#ibcon#[25=USB\r\n] 2006.203.07:31:08.68#ibcon#*before write, iclass 34, count 0 2006.203.07:31:08.68#ibcon#enter sib2, iclass 34, count 0 2006.203.07:31:08.68#ibcon#flushed, iclass 34, count 0 2006.203.07:31:08.68#ibcon#about to write, iclass 34, count 0 2006.203.07:31:08.68#ibcon#wrote, iclass 34, count 0 2006.203.07:31:08.68#ibcon#about to read 3, iclass 34, count 0 2006.203.07:31:08.71#ibcon#read 3, iclass 34, count 0 2006.203.07:31:08.71#ibcon#about to read 4, iclass 34, count 0 2006.203.07:31:08.71#ibcon#read 4, iclass 34, count 0 2006.203.07:31:08.71#ibcon#about to read 5, iclass 34, count 0 2006.203.07:31:08.71#ibcon#read 5, iclass 34, count 0 2006.203.07:31:08.71#ibcon#about to read 6, iclass 34, count 0 2006.203.07:31:08.71#ibcon#read 6, iclass 34, count 0 2006.203.07:31:08.71#ibcon#end of sib2, iclass 34, count 0 2006.203.07:31:08.71#ibcon#*after write, iclass 34, count 0 2006.203.07:31:08.71#ibcon#*before return 0, iclass 34, count 0 2006.203.07:31:08.71#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.203.07:31:08.71#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.203.07:31:08.71#ibcon#about to clear, iclass 34 cls_cnt 0 2006.203.07:31:08.71#ibcon#cleared, iclass 34 cls_cnt 0 2006.203.07:31:08.72$vc4f8/valo=2,572.99 2006.203.07:31:08.72#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.203.07:31:08.72#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.203.07:31:08.72#ibcon#ireg 17 cls_cnt 0 2006.203.07:31:08.72#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.203.07:31:08.72#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.203.07:31:08.72#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.203.07:31:08.72#ibcon#enter wrdev, iclass 36, count 0 2006.203.07:31:08.72#ibcon#first serial, iclass 36, count 0 2006.203.07:31:08.72#ibcon#enter sib2, iclass 36, count 0 2006.203.07:31:08.72#ibcon#flushed, iclass 36, count 0 2006.203.07:31:08.72#ibcon#about to write, iclass 36, count 0 2006.203.07:31:08.72#ibcon#wrote, iclass 36, count 0 2006.203.07:31:08.72#ibcon#about to read 3, iclass 36, count 0 2006.203.07:31:08.74#ibcon#read 3, iclass 36, count 0 2006.203.07:31:08.74#ibcon#about to read 4, iclass 36, count 0 2006.203.07:31:08.74#ibcon#read 4, iclass 36, count 0 2006.203.07:31:08.74#ibcon#about to read 5, iclass 36, count 0 2006.203.07:31:08.74#ibcon#read 5, iclass 36, count 0 2006.203.07:31:08.74#ibcon#about to read 6, iclass 36, count 0 2006.203.07:31:08.74#ibcon#read 6, iclass 36, count 0 2006.203.07:31:08.74#ibcon#end of sib2, iclass 36, count 0 2006.203.07:31:08.74#ibcon#*mode == 0, iclass 36, count 0 2006.203.07:31:08.74#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.203.07:31:08.74#ibcon#[26=FRQ=02,572.99\r\n] 2006.203.07:31:08.74#ibcon#*before write, iclass 36, count 0 2006.203.07:31:08.74#ibcon#enter sib2, iclass 36, count 0 2006.203.07:31:08.74#ibcon#flushed, iclass 36, count 0 2006.203.07:31:08.74#ibcon#about to write, iclass 36, count 0 2006.203.07:31:08.74#ibcon#wrote, iclass 36, count 0 2006.203.07:31:08.74#ibcon#about to read 3, iclass 36, count 0 2006.203.07:31:08.78#ibcon#read 3, iclass 36, count 0 2006.203.07:31:08.78#ibcon#about to read 4, iclass 36, count 0 2006.203.07:31:08.78#ibcon#read 4, iclass 36, count 0 2006.203.07:31:08.78#ibcon#about to read 5, iclass 36, count 0 2006.203.07:31:08.78#ibcon#read 5, iclass 36, count 0 2006.203.07:31:08.78#ibcon#about to read 6, iclass 36, count 0 2006.203.07:31:08.78#ibcon#read 6, iclass 36, count 0 2006.203.07:31:08.78#ibcon#end of sib2, iclass 36, count 0 2006.203.07:31:08.78#ibcon#*after write, iclass 36, count 0 2006.203.07:31:08.78#ibcon#*before return 0, iclass 36, count 0 2006.203.07:31:08.78#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.203.07:31:08.78#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.203.07:31:08.78#ibcon#about to clear, iclass 36 cls_cnt 0 2006.203.07:31:08.78#ibcon#cleared, iclass 36 cls_cnt 0 2006.203.07:31:08.79$vc4f8/va=2,7 2006.203.07:31:08.79#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.203.07:31:08.79#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.203.07:31:08.79#ibcon#ireg 11 cls_cnt 2 2006.203.07:31:08.79#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.203.07:31:08.82#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.203.07:31:08.82#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.203.07:31:08.82#ibcon#enter wrdev, iclass 38, count 2 2006.203.07:31:08.82#ibcon#first serial, iclass 38, count 2 2006.203.07:31:08.82#ibcon#enter sib2, iclass 38, count 2 2006.203.07:31:08.82#ibcon#flushed, iclass 38, count 2 2006.203.07:31:08.82#ibcon#about to write, iclass 38, count 2 2006.203.07:31:08.82#ibcon#wrote, iclass 38, count 2 2006.203.07:31:08.82#ibcon#about to read 3, iclass 38, count 2 2006.203.07:31:08.84#ibcon#read 3, iclass 38, count 2 2006.203.07:31:08.84#ibcon#about to read 4, iclass 38, count 2 2006.203.07:31:08.84#ibcon#read 4, iclass 38, count 2 2006.203.07:31:08.84#ibcon#about to read 5, iclass 38, count 2 2006.203.07:31:08.84#ibcon#read 5, iclass 38, count 2 2006.203.07:31:08.84#ibcon#about to read 6, iclass 38, count 2 2006.203.07:31:08.84#ibcon#read 6, iclass 38, count 2 2006.203.07:31:08.84#ibcon#end of sib2, iclass 38, count 2 2006.203.07:31:08.84#ibcon#*mode == 0, iclass 38, count 2 2006.203.07:31:08.84#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.203.07:31:08.84#ibcon#[25=AT02-07\r\n] 2006.203.07:31:08.84#ibcon#*before write, iclass 38, count 2 2006.203.07:31:08.84#ibcon#enter sib2, iclass 38, count 2 2006.203.07:31:08.84#ibcon#flushed, iclass 38, count 2 2006.203.07:31:08.84#ibcon#about to write, iclass 38, count 2 2006.203.07:31:08.84#ibcon#wrote, iclass 38, count 2 2006.203.07:31:08.84#ibcon#about to read 3, iclass 38, count 2 2006.203.07:31:08.87#ibcon#read 3, iclass 38, count 2 2006.203.07:31:08.87#ibcon#about to read 4, iclass 38, count 2 2006.203.07:31:08.87#ibcon#read 4, iclass 38, count 2 2006.203.07:31:08.87#ibcon#about to read 5, iclass 38, count 2 2006.203.07:31:08.87#ibcon#read 5, iclass 38, count 2 2006.203.07:31:08.87#ibcon#about to read 6, iclass 38, count 2 2006.203.07:31:08.87#ibcon#read 6, iclass 38, count 2 2006.203.07:31:08.87#ibcon#end of sib2, iclass 38, count 2 2006.203.07:31:08.87#ibcon#*after write, iclass 38, count 2 2006.203.07:31:08.87#ibcon#*before return 0, iclass 38, count 2 2006.203.07:31:08.87#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.203.07:31:08.87#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.203.07:31:08.87#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.203.07:31:08.87#ibcon#ireg 7 cls_cnt 0 2006.203.07:31:08.87#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.203.07:31:08.99#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.203.07:31:08.99#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.203.07:31:08.99#ibcon#enter wrdev, iclass 38, count 0 2006.203.07:31:08.99#ibcon#first serial, iclass 38, count 0 2006.203.07:31:08.99#ibcon#enter sib2, iclass 38, count 0 2006.203.07:31:08.99#ibcon#flushed, iclass 38, count 0 2006.203.07:31:08.99#ibcon#about to write, iclass 38, count 0 2006.203.07:31:08.99#ibcon#wrote, iclass 38, count 0 2006.203.07:31:08.99#ibcon#about to read 3, iclass 38, count 0 2006.203.07:31:09.01#ibcon#read 3, iclass 38, count 0 2006.203.07:31:09.01#ibcon#about to read 4, iclass 38, count 0 2006.203.07:31:09.01#ibcon#read 4, iclass 38, count 0 2006.203.07:31:09.01#ibcon#about to read 5, iclass 38, count 0 2006.203.07:31:09.01#ibcon#read 5, iclass 38, count 0 2006.203.07:31:09.01#ibcon#about to read 6, iclass 38, count 0 2006.203.07:31:09.01#ibcon#read 6, iclass 38, count 0 2006.203.07:31:09.01#ibcon#end of sib2, iclass 38, count 0 2006.203.07:31:09.01#ibcon#*mode == 0, iclass 38, count 0 2006.203.07:31:09.01#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.203.07:31:09.01#ibcon#[25=USB\r\n] 2006.203.07:31:09.01#ibcon#*before write, iclass 38, count 0 2006.203.07:31:09.01#ibcon#enter sib2, iclass 38, count 0 2006.203.07:31:09.01#ibcon#flushed, iclass 38, count 0 2006.203.07:31:09.01#ibcon#about to write, iclass 38, count 0 2006.203.07:31:09.01#ibcon#wrote, iclass 38, count 0 2006.203.07:31:09.01#ibcon#about to read 3, iclass 38, count 0 2006.203.07:31:09.04#ibcon#read 3, iclass 38, count 0 2006.203.07:31:09.04#ibcon#about to read 4, iclass 38, count 0 2006.203.07:31:09.04#ibcon#read 4, iclass 38, count 0 2006.203.07:31:09.04#ibcon#about to read 5, iclass 38, count 0 2006.203.07:31:09.04#ibcon#read 5, iclass 38, count 0 2006.203.07:31:09.04#ibcon#about to read 6, iclass 38, count 0 2006.203.07:31:09.04#ibcon#read 6, iclass 38, count 0 2006.203.07:31:09.04#ibcon#end of sib2, iclass 38, count 0 2006.203.07:31:09.04#ibcon#*after write, iclass 38, count 0 2006.203.07:31:09.04#ibcon#*before return 0, iclass 38, count 0 2006.203.07:31:09.04#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.203.07:31:09.04#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.203.07:31:09.04#ibcon#about to clear, iclass 38 cls_cnt 0 2006.203.07:31:09.04#ibcon#cleared, iclass 38 cls_cnt 0 2006.203.07:31:09.05$vc4f8/valo=3,672.99 2006.203.07:31:09.05#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.203.07:31:09.05#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.203.07:31:09.05#ibcon#ireg 17 cls_cnt 0 2006.203.07:31:09.05#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.203.07:31:09.05#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.203.07:31:09.05#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.203.07:31:09.05#ibcon#enter wrdev, iclass 40, count 0 2006.203.07:31:09.05#ibcon#first serial, iclass 40, count 0 2006.203.07:31:09.05#ibcon#enter sib2, iclass 40, count 0 2006.203.07:31:09.05#ibcon#flushed, iclass 40, count 0 2006.203.07:31:09.05#ibcon#about to write, iclass 40, count 0 2006.203.07:31:09.05#ibcon#wrote, iclass 40, count 0 2006.203.07:31:09.05#ibcon#about to read 3, iclass 40, count 0 2006.203.07:31:09.07#ibcon#read 3, iclass 40, count 0 2006.203.07:31:09.07#ibcon#about to read 4, iclass 40, count 0 2006.203.07:31:09.07#ibcon#read 4, iclass 40, count 0 2006.203.07:31:09.07#ibcon#about to read 5, iclass 40, count 0 2006.203.07:31:09.07#ibcon#read 5, iclass 40, count 0 2006.203.07:31:09.07#ibcon#about to read 6, iclass 40, count 0 2006.203.07:31:09.07#ibcon#read 6, iclass 40, count 0 2006.203.07:31:09.07#ibcon#end of sib2, iclass 40, count 0 2006.203.07:31:09.07#ibcon#*mode == 0, iclass 40, count 0 2006.203.07:31:09.07#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.203.07:31:09.07#ibcon#[26=FRQ=03,672.99\r\n] 2006.203.07:31:09.07#ibcon#*before write, iclass 40, count 0 2006.203.07:31:09.07#ibcon#enter sib2, iclass 40, count 0 2006.203.07:31:09.07#ibcon#flushed, iclass 40, count 0 2006.203.07:31:09.07#ibcon#about to write, iclass 40, count 0 2006.203.07:31:09.07#ibcon#wrote, iclass 40, count 0 2006.203.07:31:09.07#ibcon#about to read 3, iclass 40, count 0 2006.203.07:31:09.11#ibcon#read 3, iclass 40, count 0 2006.203.07:31:09.11#ibcon#about to read 4, iclass 40, count 0 2006.203.07:31:09.11#ibcon#read 4, iclass 40, count 0 2006.203.07:31:09.11#ibcon#about to read 5, iclass 40, count 0 2006.203.07:31:09.11#ibcon#read 5, iclass 40, count 0 2006.203.07:31:09.11#ibcon#about to read 6, iclass 40, count 0 2006.203.07:31:09.11#ibcon#read 6, iclass 40, count 0 2006.203.07:31:09.11#ibcon#end of sib2, iclass 40, count 0 2006.203.07:31:09.11#ibcon#*after write, iclass 40, count 0 2006.203.07:31:09.11#ibcon#*before return 0, iclass 40, count 0 2006.203.07:31:09.11#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.203.07:31:09.11#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.203.07:31:09.11#ibcon#about to clear, iclass 40 cls_cnt 0 2006.203.07:31:09.11#ibcon#cleared, iclass 40 cls_cnt 0 2006.203.07:31:09.12$vc4f8/va=3,8 2006.203.07:31:09.12#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.203.07:31:09.12#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.203.07:31:09.12#ibcon#ireg 11 cls_cnt 2 2006.203.07:31:09.12#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.203.07:31:09.15#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.203.07:31:09.15#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.203.07:31:09.15#ibcon#enter wrdev, iclass 4, count 2 2006.203.07:31:09.15#ibcon#first serial, iclass 4, count 2 2006.203.07:31:09.15#ibcon#enter sib2, iclass 4, count 2 2006.203.07:31:09.15#ibcon#flushed, iclass 4, count 2 2006.203.07:31:09.15#ibcon#about to write, iclass 4, count 2 2006.203.07:31:09.15#ibcon#wrote, iclass 4, count 2 2006.203.07:31:09.15#ibcon#about to read 3, iclass 4, count 2 2006.203.07:31:09.17#ibcon#read 3, iclass 4, count 2 2006.203.07:31:09.17#ibcon#about to read 4, iclass 4, count 2 2006.203.07:31:09.17#ibcon#read 4, iclass 4, count 2 2006.203.07:31:09.17#ibcon#about to read 5, iclass 4, count 2 2006.203.07:31:09.17#ibcon#read 5, iclass 4, count 2 2006.203.07:31:09.17#ibcon#about to read 6, iclass 4, count 2 2006.203.07:31:09.17#ibcon#read 6, iclass 4, count 2 2006.203.07:31:09.17#ibcon#end of sib2, iclass 4, count 2 2006.203.07:31:09.17#ibcon#*mode == 0, iclass 4, count 2 2006.203.07:31:09.17#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.203.07:31:09.17#ibcon#[25=AT03-08\r\n] 2006.203.07:31:09.17#ibcon#*before write, iclass 4, count 2 2006.203.07:31:09.17#ibcon#enter sib2, iclass 4, count 2 2006.203.07:31:09.17#ibcon#flushed, iclass 4, count 2 2006.203.07:31:09.17#ibcon#about to write, iclass 4, count 2 2006.203.07:31:09.17#ibcon#wrote, iclass 4, count 2 2006.203.07:31:09.17#ibcon#about to read 3, iclass 4, count 2 2006.203.07:31:09.20#ibcon#read 3, iclass 4, count 2 2006.203.07:31:09.20#ibcon#about to read 4, iclass 4, count 2 2006.203.07:31:09.20#ibcon#read 4, iclass 4, count 2 2006.203.07:31:09.20#ibcon#about to read 5, iclass 4, count 2 2006.203.07:31:09.20#ibcon#read 5, iclass 4, count 2 2006.203.07:31:09.20#ibcon#about to read 6, iclass 4, count 2 2006.203.07:31:09.20#ibcon#read 6, iclass 4, count 2 2006.203.07:31:09.20#ibcon#end of sib2, iclass 4, count 2 2006.203.07:31:09.20#ibcon#*after write, iclass 4, count 2 2006.203.07:31:09.20#ibcon#*before return 0, iclass 4, count 2 2006.203.07:31:09.20#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.203.07:31:09.20#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.203.07:31:09.20#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.203.07:31:09.20#ibcon#ireg 7 cls_cnt 0 2006.203.07:31:09.20#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.203.07:31:09.32#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.203.07:31:09.32#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.203.07:31:09.32#ibcon#enter wrdev, iclass 4, count 0 2006.203.07:31:09.32#ibcon#first serial, iclass 4, count 0 2006.203.07:31:09.32#ibcon#enter sib2, iclass 4, count 0 2006.203.07:31:09.32#ibcon#flushed, iclass 4, count 0 2006.203.07:31:09.32#ibcon#about to write, iclass 4, count 0 2006.203.07:31:09.32#ibcon#wrote, iclass 4, count 0 2006.203.07:31:09.32#ibcon#about to read 3, iclass 4, count 0 2006.203.07:31:09.34#ibcon#read 3, iclass 4, count 0 2006.203.07:31:09.34#ibcon#about to read 4, iclass 4, count 0 2006.203.07:31:09.34#ibcon#read 4, iclass 4, count 0 2006.203.07:31:09.34#ibcon#about to read 5, iclass 4, count 0 2006.203.07:31:09.34#ibcon#read 5, iclass 4, count 0 2006.203.07:31:09.34#ibcon#about to read 6, iclass 4, count 0 2006.203.07:31:09.34#ibcon#read 6, iclass 4, count 0 2006.203.07:31:09.34#ibcon#end of sib2, iclass 4, count 0 2006.203.07:31:09.34#ibcon#*mode == 0, iclass 4, count 0 2006.203.07:31:09.34#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.203.07:31:09.34#ibcon#[25=USB\r\n] 2006.203.07:31:09.34#ibcon#*before write, iclass 4, count 0 2006.203.07:31:09.34#ibcon#enter sib2, iclass 4, count 0 2006.203.07:31:09.34#ibcon#flushed, iclass 4, count 0 2006.203.07:31:09.34#ibcon#about to write, iclass 4, count 0 2006.203.07:31:09.34#ibcon#wrote, iclass 4, count 0 2006.203.07:31:09.34#ibcon#about to read 3, iclass 4, count 0 2006.203.07:31:09.37#ibcon#read 3, iclass 4, count 0 2006.203.07:31:09.37#ibcon#about to read 4, iclass 4, count 0 2006.203.07:31:09.37#ibcon#read 4, iclass 4, count 0 2006.203.07:31:09.37#ibcon#about to read 5, iclass 4, count 0 2006.203.07:31:09.37#ibcon#read 5, iclass 4, count 0 2006.203.07:31:09.37#ibcon#about to read 6, iclass 4, count 0 2006.203.07:31:09.37#ibcon#read 6, iclass 4, count 0 2006.203.07:31:09.37#ibcon#end of sib2, iclass 4, count 0 2006.203.07:31:09.37#ibcon#*after write, iclass 4, count 0 2006.203.07:31:09.37#ibcon#*before return 0, iclass 4, count 0 2006.203.07:31:09.37#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.203.07:31:09.37#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.203.07:31:09.37#ibcon#about to clear, iclass 4 cls_cnt 0 2006.203.07:31:09.37#ibcon#cleared, iclass 4 cls_cnt 0 2006.203.07:31:09.38$vc4f8/valo=4,832.99 2006.203.07:31:09.38#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.203.07:31:09.38#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.203.07:31:09.38#ibcon#ireg 17 cls_cnt 0 2006.203.07:31:09.38#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.203.07:31:09.38#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.203.07:31:09.38#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.203.07:31:09.38#ibcon#enter wrdev, iclass 6, count 0 2006.203.07:31:09.38#ibcon#first serial, iclass 6, count 0 2006.203.07:31:09.38#ibcon#enter sib2, iclass 6, count 0 2006.203.07:31:09.38#ibcon#flushed, iclass 6, count 0 2006.203.07:31:09.38#ibcon#about to write, iclass 6, count 0 2006.203.07:31:09.38#ibcon#wrote, iclass 6, count 0 2006.203.07:31:09.38#ibcon#about to read 3, iclass 6, count 0 2006.203.07:31:09.40#ibcon#read 3, iclass 6, count 0 2006.203.07:31:09.40#ibcon#about to read 4, iclass 6, count 0 2006.203.07:31:09.40#ibcon#read 4, iclass 6, count 0 2006.203.07:31:09.40#ibcon#about to read 5, iclass 6, count 0 2006.203.07:31:09.40#ibcon#read 5, iclass 6, count 0 2006.203.07:31:09.40#ibcon#about to read 6, iclass 6, count 0 2006.203.07:31:09.40#ibcon#read 6, iclass 6, count 0 2006.203.07:31:09.40#ibcon#end of sib2, iclass 6, count 0 2006.203.07:31:09.40#ibcon#*mode == 0, iclass 6, count 0 2006.203.07:31:09.40#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.203.07:31:09.40#ibcon#[26=FRQ=04,832.99\r\n] 2006.203.07:31:09.40#ibcon#*before write, iclass 6, count 0 2006.203.07:31:09.40#ibcon#enter sib2, iclass 6, count 0 2006.203.07:31:09.40#ibcon#flushed, iclass 6, count 0 2006.203.07:31:09.40#ibcon#about to write, iclass 6, count 0 2006.203.07:31:09.40#ibcon#wrote, iclass 6, count 0 2006.203.07:31:09.40#ibcon#about to read 3, iclass 6, count 0 2006.203.07:31:09.44#ibcon#read 3, iclass 6, count 0 2006.203.07:31:09.44#ibcon#about to read 4, iclass 6, count 0 2006.203.07:31:09.44#ibcon#read 4, iclass 6, count 0 2006.203.07:31:09.44#ibcon#about to read 5, iclass 6, count 0 2006.203.07:31:09.44#ibcon#read 5, iclass 6, count 0 2006.203.07:31:09.44#ibcon#about to read 6, iclass 6, count 0 2006.203.07:31:09.44#ibcon#read 6, iclass 6, count 0 2006.203.07:31:09.44#ibcon#end of sib2, iclass 6, count 0 2006.203.07:31:09.44#ibcon#*after write, iclass 6, count 0 2006.203.07:31:09.44#ibcon#*before return 0, iclass 6, count 0 2006.203.07:31:09.44#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.203.07:31:09.44#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.203.07:31:09.44#ibcon#about to clear, iclass 6 cls_cnt 0 2006.203.07:31:09.44#ibcon#cleared, iclass 6 cls_cnt 0 2006.203.07:31:09.45$vc4f8/va=4,7 2006.203.07:31:09.45#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.203.07:31:09.45#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.203.07:31:09.45#ibcon#ireg 11 cls_cnt 2 2006.203.07:31:09.45#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.203.07:31:09.48#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.203.07:31:09.48#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.203.07:31:09.48#ibcon#enter wrdev, iclass 10, count 2 2006.203.07:31:09.48#ibcon#first serial, iclass 10, count 2 2006.203.07:31:09.48#ibcon#enter sib2, iclass 10, count 2 2006.203.07:31:09.48#ibcon#flushed, iclass 10, count 2 2006.203.07:31:09.48#ibcon#about to write, iclass 10, count 2 2006.203.07:31:09.48#ibcon#wrote, iclass 10, count 2 2006.203.07:31:09.48#ibcon#about to read 3, iclass 10, count 2 2006.203.07:31:09.50#ibcon#read 3, iclass 10, count 2 2006.203.07:31:09.50#ibcon#about to read 4, iclass 10, count 2 2006.203.07:31:09.50#ibcon#read 4, iclass 10, count 2 2006.203.07:31:09.50#ibcon#about to read 5, iclass 10, count 2 2006.203.07:31:09.50#ibcon#read 5, iclass 10, count 2 2006.203.07:31:09.50#ibcon#about to read 6, iclass 10, count 2 2006.203.07:31:09.50#ibcon#read 6, iclass 10, count 2 2006.203.07:31:09.50#ibcon#end of sib2, iclass 10, count 2 2006.203.07:31:09.50#ibcon#*mode == 0, iclass 10, count 2 2006.203.07:31:09.50#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.203.07:31:09.50#ibcon#[25=AT04-07\r\n] 2006.203.07:31:09.50#ibcon#*before write, iclass 10, count 2 2006.203.07:31:09.50#ibcon#enter sib2, iclass 10, count 2 2006.203.07:31:09.50#ibcon#flushed, iclass 10, count 2 2006.203.07:31:09.50#ibcon#about to write, iclass 10, count 2 2006.203.07:31:09.50#ibcon#wrote, iclass 10, count 2 2006.203.07:31:09.50#ibcon#about to read 3, iclass 10, count 2 2006.203.07:31:09.53#ibcon#read 3, iclass 10, count 2 2006.203.07:31:09.53#ibcon#about to read 4, iclass 10, count 2 2006.203.07:31:09.53#ibcon#read 4, iclass 10, count 2 2006.203.07:31:09.53#ibcon#about to read 5, iclass 10, count 2 2006.203.07:31:09.53#ibcon#read 5, iclass 10, count 2 2006.203.07:31:09.53#ibcon#about to read 6, iclass 10, count 2 2006.203.07:31:09.53#ibcon#read 6, iclass 10, count 2 2006.203.07:31:09.53#ibcon#end of sib2, iclass 10, count 2 2006.203.07:31:09.53#ibcon#*after write, iclass 10, count 2 2006.203.07:31:09.53#ibcon#*before return 0, iclass 10, count 2 2006.203.07:31:09.53#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.203.07:31:09.53#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.203.07:31:09.53#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.203.07:31:09.53#ibcon#ireg 7 cls_cnt 0 2006.203.07:31:09.53#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.203.07:31:09.65#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.203.07:31:09.65#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.203.07:31:09.65#ibcon#enter wrdev, iclass 10, count 0 2006.203.07:31:09.65#ibcon#first serial, iclass 10, count 0 2006.203.07:31:09.65#ibcon#enter sib2, iclass 10, count 0 2006.203.07:31:09.65#ibcon#flushed, iclass 10, count 0 2006.203.07:31:09.65#ibcon#about to write, iclass 10, count 0 2006.203.07:31:09.65#ibcon#wrote, iclass 10, count 0 2006.203.07:31:09.65#ibcon#about to read 3, iclass 10, count 0 2006.203.07:31:09.67#ibcon#read 3, iclass 10, count 0 2006.203.07:31:09.67#ibcon#about to read 4, iclass 10, count 0 2006.203.07:31:09.67#ibcon#read 4, iclass 10, count 0 2006.203.07:31:09.67#ibcon#about to read 5, iclass 10, count 0 2006.203.07:31:09.67#ibcon#read 5, iclass 10, count 0 2006.203.07:31:09.67#ibcon#about to read 6, iclass 10, count 0 2006.203.07:31:09.67#ibcon#read 6, iclass 10, count 0 2006.203.07:31:09.67#ibcon#end of sib2, iclass 10, count 0 2006.203.07:31:09.67#ibcon#*mode == 0, iclass 10, count 0 2006.203.07:31:09.67#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.203.07:31:09.67#ibcon#[25=USB\r\n] 2006.203.07:31:09.67#ibcon#*before write, iclass 10, count 0 2006.203.07:31:09.67#ibcon#enter sib2, iclass 10, count 0 2006.203.07:31:09.67#ibcon#flushed, iclass 10, count 0 2006.203.07:31:09.67#ibcon#about to write, iclass 10, count 0 2006.203.07:31:09.67#ibcon#wrote, iclass 10, count 0 2006.203.07:31:09.67#ibcon#about to read 3, iclass 10, count 0 2006.203.07:31:09.70#ibcon#read 3, iclass 10, count 0 2006.203.07:31:09.70#ibcon#about to read 4, iclass 10, count 0 2006.203.07:31:09.70#ibcon#read 4, iclass 10, count 0 2006.203.07:31:09.70#ibcon#about to read 5, iclass 10, count 0 2006.203.07:31:09.70#ibcon#read 5, iclass 10, count 0 2006.203.07:31:09.70#ibcon#about to read 6, iclass 10, count 0 2006.203.07:31:09.70#ibcon#read 6, iclass 10, count 0 2006.203.07:31:09.70#ibcon#end of sib2, iclass 10, count 0 2006.203.07:31:09.70#ibcon#*after write, iclass 10, count 0 2006.203.07:31:09.70#ibcon#*before return 0, iclass 10, count 0 2006.203.07:31:09.70#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.203.07:31:09.70#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.203.07:31:09.70#ibcon#about to clear, iclass 10 cls_cnt 0 2006.203.07:31:09.70#ibcon#cleared, iclass 10 cls_cnt 0 2006.203.07:31:09.71$vc4f8/valo=5,652.99 2006.203.07:31:09.71#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.203.07:31:09.71#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.203.07:31:09.71#ibcon#ireg 17 cls_cnt 0 2006.203.07:31:09.71#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.203.07:31:09.71#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.203.07:31:09.71#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.203.07:31:09.71#ibcon#enter wrdev, iclass 12, count 0 2006.203.07:31:09.71#ibcon#first serial, iclass 12, count 0 2006.203.07:31:09.71#ibcon#enter sib2, iclass 12, count 0 2006.203.07:31:09.71#ibcon#flushed, iclass 12, count 0 2006.203.07:31:09.71#ibcon#about to write, iclass 12, count 0 2006.203.07:31:09.71#ibcon#wrote, iclass 12, count 0 2006.203.07:31:09.71#ibcon#about to read 3, iclass 12, count 0 2006.203.07:31:09.72#ibcon#read 3, iclass 12, count 0 2006.203.07:31:09.72#ibcon#about to read 4, iclass 12, count 0 2006.203.07:31:09.72#ibcon#read 4, iclass 12, count 0 2006.203.07:31:09.72#ibcon#about to read 5, iclass 12, count 0 2006.203.07:31:09.72#ibcon#read 5, iclass 12, count 0 2006.203.07:31:09.72#ibcon#about to read 6, iclass 12, count 0 2006.203.07:31:09.72#ibcon#read 6, iclass 12, count 0 2006.203.07:31:09.72#ibcon#end of sib2, iclass 12, count 0 2006.203.07:31:09.72#ibcon#*mode == 0, iclass 12, count 0 2006.203.07:31:09.72#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.203.07:31:09.72#ibcon#[26=FRQ=05,652.99\r\n] 2006.203.07:31:09.72#ibcon#*before write, iclass 12, count 0 2006.203.07:31:09.72#ibcon#enter sib2, iclass 12, count 0 2006.203.07:31:09.72#ibcon#flushed, iclass 12, count 0 2006.203.07:31:09.72#ibcon#about to write, iclass 12, count 0 2006.203.07:31:09.72#ibcon#wrote, iclass 12, count 0 2006.203.07:31:09.72#ibcon#about to read 3, iclass 12, count 0 2006.203.07:31:09.76#ibcon#read 3, iclass 12, count 0 2006.203.07:31:09.76#ibcon#about to read 4, iclass 12, count 0 2006.203.07:31:09.76#ibcon#read 4, iclass 12, count 0 2006.203.07:31:09.76#ibcon#about to read 5, iclass 12, count 0 2006.203.07:31:09.76#ibcon#read 5, iclass 12, count 0 2006.203.07:31:09.76#ibcon#about to read 6, iclass 12, count 0 2006.203.07:31:09.76#ibcon#read 6, iclass 12, count 0 2006.203.07:31:09.76#ibcon#end of sib2, iclass 12, count 0 2006.203.07:31:09.76#ibcon#*after write, iclass 12, count 0 2006.203.07:31:09.76#ibcon#*before return 0, iclass 12, count 0 2006.203.07:31:09.76#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.203.07:31:09.76#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.203.07:31:09.76#ibcon#about to clear, iclass 12 cls_cnt 0 2006.203.07:31:09.76#ibcon#cleared, iclass 12 cls_cnt 0 2006.203.07:31:09.77$vc4f8/va=5,7 2006.203.07:31:09.77#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.203.07:31:09.77#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.203.07:31:09.77#ibcon#ireg 11 cls_cnt 2 2006.203.07:31:09.77#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.203.07:31:09.81#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.203.07:31:09.81#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.203.07:31:09.81#ibcon#enter wrdev, iclass 14, count 2 2006.203.07:31:09.81#ibcon#first serial, iclass 14, count 2 2006.203.07:31:09.81#ibcon#enter sib2, iclass 14, count 2 2006.203.07:31:09.81#ibcon#flushed, iclass 14, count 2 2006.203.07:31:09.81#ibcon#about to write, iclass 14, count 2 2006.203.07:31:09.81#ibcon#wrote, iclass 14, count 2 2006.203.07:31:09.81#ibcon#about to read 3, iclass 14, count 2 2006.203.07:31:09.84#ibcon#read 3, iclass 14, count 2 2006.203.07:31:09.84#ibcon#about to read 4, iclass 14, count 2 2006.203.07:31:09.84#ibcon#read 4, iclass 14, count 2 2006.203.07:31:09.84#ibcon#about to read 5, iclass 14, count 2 2006.203.07:31:09.84#ibcon#read 5, iclass 14, count 2 2006.203.07:31:09.84#ibcon#about to read 6, iclass 14, count 2 2006.203.07:31:09.84#ibcon#read 6, iclass 14, count 2 2006.203.07:31:09.84#ibcon#end of sib2, iclass 14, count 2 2006.203.07:31:09.84#ibcon#*mode == 0, iclass 14, count 2 2006.203.07:31:09.84#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.203.07:31:09.84#ibcon#[25=AT05-07\r\n] 2006.203.07:31:09.84#ibcon#*before write, iclass 14, count 2 2006.203.07:31:09.84#ibcon#enter sib2, iclass 14, count 2 2006.203.07:31:09.84#ibcon#flushed, iclass 14, count 2 2006.203.07:31:09.84#ibcon#about to write, iclass 14, count 2 2006.203.07:31:09.84#ibcon#wrote, iclass 14, count 2 2006.203.07:31:09.84#ibcon#about to read 3, iclass 14, count 2 2006.203.07:31:09.87#ibcon#read 3, iclass 14, count 2 2006.203.07:31:09.87#ibcon#about to read 4, iclass 14, count 2 2006.203.07:31:09.87#ibcon#read 4, iclass 14, count 2 2006.203.07:31:09.87#ibcon#about to read 5, iclass 14, count 2 2006.203.07:31:09.87#ibcon#read 5, iclass 14, count 2 2006.203.07:31:09.87#ibcon#about to read 6, iclass 14, count 2 2006.203.07:31:09.87#ibcon#read 6, iclass 14, count 2 2006.203.07:31:09.87#ibcon#end of sib2, iclass 14, count 2 2006.203.07:31:09.87#ibcon#*after write, iclass 14, count 2 2006.203.07:31:09.87#ibcon#*before return 0, iclass 14, count 2 2006.203.07:31:09.87#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.203.07:31:09.87#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.203.07:31:09.87#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.203.07:31:09.87#ibcon#ireg 7 cls_cnt 0 2006.203.07:31:09.87#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.203.07:31:09.99#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.203.07:31:09.99#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.203.07:31:09.99#ibcon#enter wrdev, iclass 14, count 0 2006.203.07:31:09.99#ibcon#first serial, iclass 14, count 0 2006.203.07:31:09.99#ibcon#enter sib2, iclass 14, count 0 2006.203.07:31:09.99#ibcon#flushed, iclass 14, count 0 2006.203.07:31:09.99#ibcon#about to write, iclass 14, count 0 2006.203.07:31:09.99#ibcon#wrote, iclass 14, count 0 2006.203.07:31:09.99#ibcon#about to read 3, iclass 14, count 0 2006.203.07:31:10.01#ibcon#read 3, iclass 14, count 0 2006.203.07:31:10.01#ibcon#about to read 4, iclass 14, count 0 2006.203.07:31:10.01#ibcon#read 4, iclass 14, count 0 2006.203.07:31:10.01#ibcon#about to read 5, iclass 14, count 0 2006.203.07:31:10.01#ibcon#read 5, iclass 14, count 0 2006.203.07:31:10.01#ibcon#about to read 6, iclass 14, count 0 2006.203.07:31:10.01#ibcon#read 6, iclass 14, count 0 2006.203.07:31:10.01#ibcon#end of sib2, iclass 14, count 0 2006.203.07:31:10.01#ibcon#*mode == 0, iclass 14, count 0 2006.203.07:31:10.01#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.203.07:31:10.01#ibcon#[25=USB\r\n] 2006.203.07:31:10.01#ibcon#*before write, iclass 14, count 0 2006.203.07:31:10.01#ibcon#enter sib2, iclass 14, count 0 2006.203.07:31:10.01#ibcon#flushed, iclass 14, count 0 2006.203.07:31:10.01#ibcon#about to write, iclass 14, count 0 2006.203.07:31:10.01#ibcon#wrote, iclass 14, count 0 2006.203.07:31:10.01#ibcon#about to read 3, iclass 14, count 0 2006.203.07:31:10.04#ibcon#read 3, iclass 14, count 0 2006.203.07:31:10.04#ibcon#about to read 4, iclass 14, count 0 2006.203.07:31:10.04#ibcon#read 4, iclass 14, count 0 2006.203.07:31:10.04#ibcon#about to read 5, iclass 14, count 0 2006.203.07:31:10.04#ibcon#read 5, iclass 14, count 0 2006.203.07:31:10.04#ibcon#about to read 6, iclass 14, count 0 2006.203.07:31:10.04#ibcon#read 6, iclass 14, count 0 2006.203.07:31:10.04#ibcon#end of sib2, iclass 14, count 0 2006.203.07:31:10.04#ibcon#*after write, iclass 14, count 0 2006.203.07:31:10.04#ibcon#*before return 0, iclass 14, count 0 2006.203.07:31:10.04#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.203.07:31:10.04#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.203.07:31:10.04#ibcon#about to clear, iclass 14 cls_cnt 0 2006.203.07:31:10.04#ibcon#cleared, iclass 14 cls_cnt 0 2006.203.07:31:10.05$vc4f8/valo=6,772.99 2006.203.07:31:10.05#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.203.07:31:10.05#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.203.07:31:10.05#ibcon#ireg 17 cls_cnt 0 2006.203.07:31:10.05#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.203.07:31:10.05#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.203.07:31:10.05#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.203.07:31:10.05#ibcon#enter wrdev, iclass 16, count 0 2006.203.07:31:10.05#ibcon#first serial, iclass 16, count 0 2006.203.07:31:10.05#ibcon#enter sib2, iclass 16, count 0 2006.203.07:31:10.05#ibcon#flushed, iclass 16, count 0 2006.203.07:31:10.05#ibcon#about to write, iclass 16, count 0 2006.203.07:31:10.05#ibcon#wrote, iclass 16, count 0 2006.203.07:31:10.05#ibcon#about to read 3, iclass 16, count 0 2006.203.07:31:10.07#ibcon#read 3, iclass 16, count 0 2006.203.07:31:10.07#ibcon#about to read 4, iclass 16, count 0 2006.203.07:31:10.07#ibcon#read 4, iclass 16, count 0 2006.203.07:31:10.07#ibcon#about to read 5, iclass 16, count 0 2006.203.07:31:10.07#ibcon#read 5, iclass 16, count 0 2006.203.07:31:10.07#ibcon#about to read 6, iclass 16, count 0 2006.203.07:31:10.07#ibcon#read 6, iclass 16, count 0 2006.203.07:31:10.07#ibcon#end of sib2, iclass 16, count 0 2006.203.07:31:10.07#ibcon#*mode == 0, iclass 16, count 0 2006.203.07:31:10.07#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.203.07:31:10.07#ibcon#[26=FRQ=06,772.99\r\n] 2006.203.07:31:10.07#ibcon#*before write, iclass 16, count 0 2006.203.07:31:10.07#ibcon#enter sib2, iclass 16, count 0 2006.203.07:31:10.07#ibcon#flushed, iclass 16, count 0 2006.203.07:31:10.07#ibcon#about to write, iclass 16, count 0 2006.203.07:31:10.07#ibcon#wrote, iclass 16, count 0 2006.203.07:31:10.07#ibcon#about to read 3, iclass 16, count 0 2006.203.07:31:10.11#ibcon#read 3, iclass 16, count 0 2006.203.07:31:10.11#ibcon#about to read 4, iclass 16, count 0 2006.203.07:31:10.11#ibcon#read 4, iclass 16, count 0 2006.203.07:31:10.11#ibcon#about to read 5, iclass 16, count 0 2006.203.07:31:10.11#ibcon#read 5, iclass 16, count 0 2006.203.07:31:10.11#ibcon#about to read 6, iclass 16, count 0 2006.203.07:31:10.11#ibcon#read 6, iclass 16, count 0 2006.203.07:31:10.11#ibcon#end of sib2, iclass 16, count 0 2006.203.07:31:10.11#ibcon#*after write, iclass 16, count 0 2006.203.07:31:10.11#ibcon#*before return 0, iclass 16, count 0 2006.203.07:31:10.11#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.203.07:31:10.11#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.203.07:31:10.11#ibcon#about to clear, iclass 16 cls_cnt 0 2006.203.07:31:10.11#ibcon#cleared, iclass 16 cls_cnt 0 2006.203.07:31:10.12$vc4f8/va=6,6 2006.203.07:31:10.12#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.203.07:31:10.12#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.203.07:31:10.12#ibcon#ireg 11 cls_cnt 2 2006.203.07:31:10.12#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.203.07:31:10.15#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.203.07:31:10.15#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.203.07:31:10.15#ibcon#enter wrdev, iclass 18, count 2 2006.203.07:31:10.15#ibcon#first serial, iclass 18, count 2 2006.203.07:31:10.15#ibcon#enter sib2, iclass 18, count 2 2006.203.07:31:10.15#ibcon#flushed, iclass 18, count 2 2006.203.07:31:10.15#ibcon#about to write, iclass 18, count 2 2006.203.07:31:10.15#ibcon#wrote, iclass 18, count 2 2006.203.07:31:10.15#ibcon#about to read 3, iclass 18, count 2 2006.203.07:31:10.17#ibcon#read 3, iclass 18, count 2 2006.203.07:31:10.17#ibcon#about to read 4, iclass 18, count 2 2006.203.07:31:10.17#ibcon#read 4, iclass 18, count 2 2006.203.07:31:10.17#ibcon#about to read 5, iclass 18, count 2 2006.203.07:31:10.17#ibcon#read 5, iclass 18, count 2 2006.203.07:31:10.17#ibcon#about to read 6, iclass 18, count 2 2006.203.07:31:10.17#ibcon#read 6, iclass 18, count 2 2006.203.07:31:10.17#ibcon#end of sib2, iclass 18, count 2 2006.203.07:31:10.17#ibcon#*mode == 0, iclass 18, count 2 2006.203.07:31:10.17#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.203.07:31:10.17#ibcon#[25=AT06-06\r\n] 2006.203.07:31:10.17#ibcon#*before write, iclass 18, count 2 2006.203.07:31:10.17#ibcon#enter sib2, iclass 18, count 2 2006.203.07:31:10.17#ibcon#flushed, iclass 18, count 2 2006.203.07:31:10.17#ibcon#about to write, iclass 18, count 2 2006.203.07:31:10.17#ibcon#wrote, iclass 18, count 2 2006.203.07:31:10.17#ibcon#about to read 3, iclass 18, count 2 2006.203.07:31:10.20#ibcon#read 3, iclass 18, count 2 2006.203.07:31:10.20#ibcon#about to read 4, iclass 18, count 2 2006.203.07:31:10.20#ibcon#read 4, iclass 18, count 2 2006.203.07:31:10.20#ibcon#about to read 5, iclass 18, count 2 2006.203.07:31:10.20#ibcon#read 5, iclass 18, count 2 2006.203.07:31:10.20#ibcon#about to read 6, iclass 18, count 2 2006.203.07:31:10.20#ibcon#read 6, iclass 18, count 2 2006.203.07:31:10.20#ibcon#end of sib2, iclass 18, count 2 2006.203.07:31:10.20#ibcon#*after write, iclass 18, count 2 2006.203.07:31:10.20#ibcon#*before return 0, iclass 18, count 2 2006.203.07:31:10.20#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.203.07:31:10.20#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.203.07:31:10.20#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.203.07:31:10.20#ibcon#ireg 7 cls_cnt 0 2006.203.07:31:10.20#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.203.07:31:10.32#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.203.07:31:10.32#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.203.07:31:10.32#ibcon#enter wrdev, iclass 18, count 0 2006.203.07:31:10.32#ibcon#first serial, iclass 18, count 0 2006.203.07:31:10.32#ibcon#enter sib2, iclass 18, count 0 2006.203.07:31:10.32#ibcon#flushed, iclass 18, count 0 2006.203.07:31:10.32#ibcon#about to write, iclass 18, count 0 2006.203.07:31:10.32#ibcon#wrote, iclass 18, count 0 2006.203.07:31:10.32#ibcon#about to read 3, iclass 18, count 0 2006.203.07:31:10.34#ibcon#read 3, iclass 18, count 0 2006.203.07:31:10.34#ibcon#about to read 4, iclass 18, count 0 2006.203.07:31:10.34#ibcon#read 4, iclass 18, count 0 2006.203.07:31:10.34#ibcon#about to read 5, iclass 18, count 0 2006.203.07:31:10.34#ibcon#read 5, iclass 18, count 0 2006.203.07:31:10.34#ibcon#about to read 6, iclass 18, count 0 2006.203.07:31:10.34#ibcon#read 6, iclass 18, count 0 2006.203.07:31:10.34#ibcon#end of sib2, iclass 18, count 0 2006.203.07:31:10.34#ibcon#*mode == 0, iclass 18, count 0 2006.203.07:31:10.34#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.203.07:31:10.34#ibcon#[25=USB\r\n] 2006.203.07:31:10.34#ibcon#*before write, iclass 18, count 0 2006.203.07:31:10.34#ibcon#enter sib2, iclass 18, count 0 2006.203.07:31:10.34#ibcon#flushed, iclass 18, count 0 2006.203.07:31:10.34#ibcon#about to write, iclass 18, count 0 2006.203.07:31:10.34#ibcon#wrote, iclass 18, count 0 2006.203.07:31:10.34#ibcon#about to read 3, iclass 18, count 0 2006.203.07:31:10.37#ibcon#read 3, iclass 18, count 0 2006.203.07:31:10.37#ibcon#about to read 4, iclass 18, count 0 2006.203.07:31:10.37#ibcon#read 4, iclass 18, count 0 2006.203.07:31:10.37#ibcon#about to read 5, iclass 18, count 0 2006.203.07:31:10.37#ibcon#read 5, iclass 18, count 0 2006.203.07:31:10.37#ibcon#about to read 6, iclass 18, count 0 2006.203.07:31:10.37#ibcon#read 6, iclass 18, count 0 2006.203.07:31:10.37#ibcon#end of sib2, iclass 18, count 0 2006.203.07:31:10.37#ibcon#*after write, iclass 18, count 0 2006.203.07:31:10.37#ibcon#*before return 0, iclass 18, count 0 2006.203.07:31:10.37#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.203.07:31:10.37#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.203.07:31:10.37#ibcon#about to clear, iclass 18 cls_cnt 0 2006.203.07:31:10.37#ibcon#cleared, iclass 18 cls_cnt 0 2006.203.07:31:10.38$vc4f8/valo=7,832.99 2006.203.07:31:10.38#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.203.07:31:10.38#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.203.07:31:10.38#ibcon#ireg 17 cls_cnt 0 2006.203.07:31:10.38#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.203.07:31:10.38#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.203.07:31:10.38#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.203.07:31:10.38#ibcon#enter wrdev, iclass 20, count 0 2006.203.07:31:10.38#ibcon#first serial, iclass 20, count 0 2006.203.07:31:10.38#ibcon#enter sib2, iclass 20, count 0 2006.203.07:31:10.38#ibcon#flushed, iclass 20, count 0 2006.203.07:31:10.38#ibcon#about to write, iclass 20, count 0 2006.203.07:31:10.38#ibcon#wrote, iclass 20, count 0 2006.203.07:31:10.38#ibcon#about to read 3, iclass 20, count 0 2006.203.07:31:10.39#ibcon#read 3, iclass 20, count 0 2006.203.07:31:10.39#ibcon#about to read 4, iclass 20, count 0 2006.203.07:31:10.39#ibcon#read 4, iclass 20, count 0 2006.203.07:31:10.39#ibcon#about to read 5, iclass 20, count 0 2006.203.07:31:10.39#ibcon#read 5, iclass 20, count 0 2006.203.07:31:10.39#ibcon#about to read 6, iclass 20, count 0 2006.203.07:31:10.39#ibcon#read 6, iclass 20, count 0 2006.203.07:31:10.39#ibcon#end of sib2, iclass 20, count 0 2006.203.07:31:10.39#ibcon#*mode == 0, iclass 20, count 0 2006.203.07:31:10.39#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.203.07:31:10.39#ibcon#[26=FRQ=07,832.99\r\n] 2006.203.07:31:10.39#ibcon#*before write, iclass 20, count 0 2006.203.07:31:10.39#ibcon#enter sib2, iclass 20, count 0 2006.203.07:31:10.39#ibcon#flushed, iclass 20, count 0 2006.203.07:31:10.39#ibcon#about to write, iclass 20, count 0 2006.203.07:31:10.39#ibcon#wrote, iclass 20, count 0 2006.203.07:31:10.39#ibcon#about to read 3, iclass 20, count 0 2006.203.07:31:10.43#ibcon#read 3, iclass 20, count 0 2006.203.07:31:10.43#ibcon#about to read 4, iclass 20, count 0 2006.203.07:31:10.43#ibcon#read 4, iclass 20, count 0 2006.203.07:31:10.43#ibcon#about to read 5, iclass 20, count 0 2006.203.07:31:10.43#ibcon#read 5, iclass 20, count 0 2006.203.07:31:10.43#ibcon#about to read 6, iclass 20, count 0 2006.203.07:31:10.43#ibcon#read 6, iclass 20, count 0 2006.203.07:31:10.43#ibcon#end of sib2, iclass 20, count 0 2006.203.07:31:10.43#ibcon#*after write, iclass 20, count 0 2006.203.07:31:10.43#ibcon#*before return 0, iclass 20, count 0 2006.203.07:31:10.43#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.203.07:31:10.43#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.203.07:31:10.43#ibcon#about to clear, iclass 20 cls_cnt 0 2006.203.07:31:10.43#ibcon#cleared, iclass 20 cls_cnt 0 2006.203.07:31:10.44$vc4f8/va=7,7 2006.203.07:31:10.44#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.203.07:31:10.44#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.203.07:31:10.44#ibcon#ireg 11 cls_cnt 2 2006.203.07:31:10.44#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.203.07:31:10.48#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.203.07:31:10.48#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.203.07:31:10.48#ibcon#enter wrdev, iclass 22, count 2 2006.203.07:31:10.48#ibcon#first serial, iclass 22, count 2 2006.203.07:31:10.48#ibcon#enter sib2, iclass 22, count 2 2006.203.07:31:10.48#ibcon#flushed, iclass 22, count 2 2006.203.07:31:10.48#ibcon#about to write, iclass 22, count 2 2006.203.07:31:10.48#ibcon#wrote, iclass 22, count 2 2006.203.07:31:10.48#ibcon#about to read 3, iclass 22, count 2 2006.203.07:31:10.51#ibcon#read 3, iclass 22, count 2 2006.203.07:31:10.51#ibcon#about to read 4, iclass 22, count 2 2006.203.07:31:10.51#ibcon#read 4, iclass 22, count 2 2006.203.07:31:10.51#ibcon#about to read 5, iclass 22, count 2 2006.203.07:31:10.51#ibcon#read 5, iclass 22, count 2 2006.203.07:31:10.51#ibcon#about to read 6, iclass 22, count 2 2006.203.07:31:10.51#ibcon#read 6, iclass 22, count 2 2006.203.07:31:10.51#ibcon#end of sib2, iclass 22, count 2 2006.203.07:31:10.51#ibcon#*mode == 0, iclass 22, count 2 2006.203.07:31:10.51#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.203.07:31:10.51#ibcon#[25=AT07-07\r\n] 2006.203.07:31:10.51#ibcon#*before write, iclass 22, count 2 2006.203.07:31:10.51#ibcon#enter sib2, iclass 22, count 2 2006.203.07:31:10.51#ibcon#flushed, iclass 22, count 2 2006.203.07:31:10.51#ibcon#about to write, iclass 22, count 2 2006.203.07:31:10.51#ibcon#wrote, iclass 22, count 2 2006.203.07:31:10.51#ibcon#about to read 3, iclass 22, count 2 2006.203.07:31:10.54#ibcon#read 3, iclass 22, count 2 2006.203.07:31:10.54#ibcon#about to read 4, iclass 22, count 2 2006.203.07:31:10.54#ibcon#read 4, iclass 22, count 2 2006.203.07:31:10.54#ibcon#about to read 5, iclass 22, count 2 2006.203.07:31:10.54#ibcon#read 5, iclass 22, count 2 2006.203.07:31:10.54#ibcon#about to read 6, iclass 22, count 2 2006.203.07:31:10.54#ibcon#read 6, iclass 22, count 2 2006.203.07:31:10.54#ibcon#end of sib2, iclass 22, count 2 2006.203.07:31:10.54#ibcon#*after write, iclass 22, count 2 2006.203.07:31:10.54#ibcon#*before return 0, iclass 22, count 2 2006.203.07:31:10.54#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.203.07:31:10.54#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.203.07:31:10.54#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.203.07:31:10.54#ibcon#ireg 7 cls_cnt 0 2006.203.07:31:10.54#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.203.07:31:10.66#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.203.07:31:10.66#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.203.07:31:10.66#ibcon#enter wrdev, iclass 22, count 0 2006.203.07:31:10.66#ibcon#first serial, iclass 22, count 0 2006.203.07:31:10.66#ibcon#enter sib2, iclass 22, count 0 2006.203.07:31:10.66#ibcon#flushed, iclass 22, count 0 2006.203.07:31:10.66#ibcon#about to write, iclass 22, count 0 2006.203.07:31:10.66#ibcon#wrote, iclass 22, count 0 2006.203.07:31:10.66#ibcon#about to read 3, iclass 22, count 0 2006.203.07:31:10.68#ibcon#read 3, iclass 22, count 0 2006.203.07:31:10.68#ibcon#about to read 4, iclass 22, count 0 2006.203.07:31:10.68#ibcon#read 4, iclass 22, count 0 2006.203.07:31:10.68#ibcon#about to read 5, iclass 22, count 0 2006.203.07:31:10.68#ibcon#read 5, iclass 22, count 0 2006.203.07:31:10.68#ibcon#about to read 6, iclass 22, count 0 2006.203.07:31:10.68#ibcon#read 6, iclass 22, count 0 2006.203.07:31:10.68#ibcon#end of sib2, iclass 22, count 0 2006.203.07:31:10.68#ibcon#*mode == 0, iclass 22, count 0 2006.203.07:31:10.68#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.203.07:31:10.68#ibcon#[25=USB\r\n] 2006.203.07:31:10.68#ibcon#*before write, iclass 22, count 0 2006.203.07:31:10.68#ibcon#enter sib2, iclass 22, count 0 2006.203.07:31:10.68#ibcon#flushed, iclass 22, count 0 2006.203.07:31:10.68#ibcon#about to write, iclass 22, count 0 2006.203.07:31:10.68#ibcon#wrote, iclass 22, count 0 2006.203.07:31:10.68#ibcon#about to read 3, iclass 22, count 0 2006.203.07:31:10.71#ibcon#read 3, iclass 22, count 0 2006.203.07:31:10.71#ibcon#about to read 4, iclass 22, count 0 2006.203.07:31:10.71#ibcon#read 4, iclass 22, count 0 2006.203.07:31:10.71#ibcon#about to read 5, iclass 22, count 0 2006.203.07:31:10.71#ibcon#read 5, iclass 22, count 0 2006.203.07:31:10.71#ibcon#about to read 6, iclass 22, count 0 2006.203.07:31:10.71#ibcon#read 6, iclass 22, count 0 2006.203.07:31:10.71#ibcon#end of sib2, iclass 22, count 0 2006.203.07:31:10.71#ibcon#*after write, iclass 22, count 0 2006.203.07:31:10.71#ibcon#*before return 0, iclass 22, count 0 2006.203.07:31:10.71#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.203.07:31:10.71#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.203.07:31:10.71#ibcon#about to clear, iclass 22 cls_cnt 0 2006.203.07:31:10.71#ibcon#cleared, iclass 22 cls_cnt 0 2006.203.07:31:10.72$vc4f8/valo=8,852.99 2006.203.07:31:10.72#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.203.07:31:10.72#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.203.07:31:10.72#ibcon#ireg 17 cls_cnt 0 2006.203.07:31:10.72#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.203.07:31:10.72#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.203.07:31:10.72#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.203.07:31:10.72#ibcon#enter wrdev, iclass 24, count 0 2006.203.07:31:10.72#ibcon#first serial, iclass 24, count 0 2006.203.07:31:10.72#ibcon#enter sib2, iclass 24, count 0 2006.203.07:31:10.72#ibcon#flushed, iclass 24, count 0 2006.203.07:31:10.72#ibcon#about to write, iclass 24, count 0 2006.203.07:31:10.72#ibcon#wrote, iclass 24, count 0 2006.203.07:31:10.72#ibcon#about to read 3, iclass 24, count 0 2006.203.07:31:10.74#ibcon#read 3, iclass 24, count 0 2006.203.07:31:10.74#ibcon#about to read 4, iclass 24, count 0 2006.203.07:31:10.74#ibcon#read 4, iclass 24, count 0 2006.203.07:31:10.74#ibcon#about to read 5, iclass 24, count 0 2006.203.07:31:10.74#ibcon#read 5, iclass 24, count 0 2006.203.07:31:10.74#ibcon#about to read 6, iclass 24, count 0 2006.203.07:31:10.74#ibcon#read 6, iclass 24, count 0 2006.203.07:31:10.74#ibcon#end of sib2, iclass 24, count 0 2006.203.07:31:10.74#ibcon#*mode == 0, iclass 24, count 0 2006.203.07:31:10.74#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.203.07:31:10.74#ibcon#[26=FRQ=08,852.99\r\n] 2006.203.07:31:10.74#ibcon#*before write, iclass 24, count 0 2006.203.07:31:10.74#ibcon#enter sib2, iclass 24, count 0 2006.203.07:31:10.74#ibcon#flushed, iclass 24, count 0 2006.203.07:31:10.74#ibcon#about to write, iclass 24, count 0 2006.203.07:31:10.74#ibcon#wrote, iclass 24, count 0 2006.203.07:31:10.74#ibcon#about to read 3, iclass 24, count 0 2006.203.07:31:10.78#ibcon#read 3, iclass 24, count 0 2006.203.07:31:10.78#ibcon#about to read 4, iclass 24, count 0 2006.203.07:31:10.78#ibcon#read 4, iclass 24, count 0 2006.203.07:31:10.78#ibcon#about to read 5, iclass 24, count 0 2006.203.07:31:10.78#ibcon#read 5, iclass 24, count 0 2006.203.07:31:10.78#ibcon#about to read 6, iclass 24, count 0 2006.203.07:31:10.78#ibcon#read 6, iclass 24, count 0 2006.203.07:31:10.78#ibcon#end of sib2, iclass 24, count 0 2006.203.07:31:10.78#ibcon#*after write, iclass 24, count 0 2006.203.07:31:10.78#ibcon#*before return 0, iclass 24, count 0 2006.203.07:31:10.78#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.203.07:31:10.78#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.203.07:31:10.78#ibcon#about to clear, iclass 24 cls_cnt 0 2006.203.07:31:10.78#ibcon#cleared, iclass 24 cls_cnt 0 2006.203.07:31:10.79$vc4f8/va=8,6 2006.203.07:31:10.79#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.203.07:31:10.79#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.203.07:31:10.79#ibcon#ireg 11 cls_cnt 2 2006.203.07:31:10.79#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.203.07:31:10.82#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.203.07:31:10.82#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.203.07:31:10.82#ibcon#enter wrdev, iclass 26, count 2 2006.203.07:31:10.82#ibcon#first serial, iclass 26, count 2 2006.203.07:31:10.82#ibcon#enter sib2, iclass 26, count 2 2006.203.07:31:10.82#ibcon#flushed, iclass 26, count 2 2006.203.07:31:10.82#ibcon#about to write, iclass 26, count 2 2006.203.07:31:10.82#ibcon#wrote, iclass 26, count 2 2006.203.07:31:10.82#ibcon#about to read 3, iclass 26, count 2 2006.203.07:31:10.84#ibcon#read 3, iclass 26, count 2 2006.203.07:31:10.84#ibcon#about to read 4, iclass 26, count 2 2006.203.07:31:10.84#ibcon#read 4, iclass 26, count 2 2006.203.07:31:10.84#ibcon#about to read 5, iclass 26, count 2 2006.203.07:31:10.84#ibcon#read 5, iclass 26, count 2 2006.203.07:31:10.84#ibcon#about to read 6, iclass 26, count 2 2006.203.07:31:10.84#ibcon#read 6, iclass 26, count 2 2006.203.07:31:10.84#ibcon#end of sib2, iclass 26, count 2 2006.203.07:31:10.84#ibcon#*mode == 0, iclass 26, count 2 2006.203.07:31:10.84#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.203.07:31:10.84#ibcon#[25=AT08-06\r\n] 2006.203.07:31:10.84#ibcon#*before write, iclass 26, count 2 2006.203.07:31:10.84#ibcon#enter sib2, iclass 26, count 2 2006.203.07:31:10.84#ibcon#flushed, iclass 26, count 2 2006.203.07:31:10.84#ibcon#about to write, iclass 26, count 2 2006.203.07:31:10.84#ibcon#wrote, iclass 26, count 2 2006.203.07:31:10.84#ibcon#about to read 3, iclass 26, count 2 2006.203.07:31:10.87#ibcon#read 3, iclass 26, count 2 2006.203.07:31:10.87#ibcon#about to read 4, iclass 26, count 2 2006.203.07:31:10.87#ibcon#read 4, iclass 26, count 2 2006.203.07:31:10.87#ibcon#about to read 5, iclass 26, count 2 2006.203.07:31:10.87#ibcon#read 5, iclass 26, count 2 2006.203.07:31:10.87#ibcon#about to read 6, iclass 26, count 2 2006.203.07:31:10.87#ibcon#read 6, iclass 26, count 2 2006.203.07:31:10.87#ibcon#end of sib2, iclass 26, count 2 2006.203.07:31:10.87#ibcon#*after write, iclass 26, count 2 2006.203.07:31:10.87#ibcon#*before return 0, iclass 26, count 2 2006.203.07:31:10.87#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.203.07:31:10.87#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.203.07:31:10.87#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.203.07:31:10.87#ibcon#ireg 7 cls_cnt 0 2006.203.07:31:10.87#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.203.07:31:10.99#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.203.07:31:10.99#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.203.07:31:10.99#ibcon#enter wrdev, iclass 26, count 0 2006.203.07:31:10.99#ibcon#first serial, iclass 26, count 0 2006.203.07:31:10.99#ibcon#enter sib2, iclass 26, count 0 2006.203.07:31:10.99#ibcon#flushed, iclass 26, count 0 2006.203.07:31:10.99#ibcon#about to write, iclass 26, count 0 2006.203.07:31:10.99#ibcon#wrote, iclass 26, count 0 2006.203.07:31:10.99#ibcon#about to read 3, iclass 26, count 0 2006.203.07:31:11.01#ibcon#read 3, iclass 26, count 0 2006.203.07:31:11.01#ibcon#about to read 4, iclass 26, count 0 2006.203.07:31:11.01#ibcon#read 4, iclass 26, count 0 2006.203.07:31:11.01#ibcon#about to read 5, iclass 26, count 0 2006.203.07:31:11.01#ibcon#read 5, iclass 26, count 0 2006.203.07:31:11.01#ibcon#about to read 6, iclass 26, count 0 2006.203.07:31:11.01#ibcon#read 6, iclass 26, count 0 2006.203.07:31:11.01#ibcon#end of sib2, iclass 26, count 0 2006.203.07:31:11.01#ibcon#*mode == 0, iclass 26, count 0 2006.203.07:31:11.01#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.203.07:31:11.01#ibcon#[25=USB\r\n] 2006.203.07:31:11.01#ibcon#*before write, iclass 26, count 0 2006.203.07:31:11.01#ibcon#enter sib2, iclass 26, count 0 2006.203.07:31:11.01#ibcon#flushed, iclass 26, count 0 2006.203.07:31:11.01#ibcon#about to write, iclass 26, count 0 2006.203.07:31:11.01#ibcon#wrote, iclass 26, count 0 2006.203.07:31:11.01#ibcon#about to read 3, iclass 26, count 0 2006.203.07:31:11.04#ibcon#read 3, iclass 26, count 0 2006.203.07:31:11.04#ibcon#about to read 4, iclass 26, count 0 2006.203.07:31:11.04#ibcon#read 4, iclass 26, count 0 2006.203.07:31:11.04#ibcon#about to read 5, iclass 26, count 0 2006.203.07:31:11.04#ibcon#read 5, iclass 26, count 0 2006.203.07:31:11.04#ibcon#about to read 6, iclass 26, count 0 2006.203.07:31:11.04#ibcon#read 6, iclass 26, count 0 2006.203.07:31:11.04#ibcon#end of sib2, iclass 26, count 0 2006.203.07:31:11.04#ibcon#*after write, iclass 26, count 0 2006.203.07:31:11.04#ibcon#*before return 0, iclass 26, count 0 2006.203.07:31:11.04#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.203.07:31:11.04#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.203.07:31:11.04#ibcon#about to clear, iclass 26 cls_cnt 0 2006.203.07:31:11.04#ibcon#cleared, iclass 26 cls_cnt 0 2006.203.07:31:11.05$vc4f8/vblo=1,632.99 2006.203.07:31:11.05#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.203.07:31:11.05#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.203.07:31:11.05#ibcon#ireg 17 cls_cnt 0 2006.203.07:31:11.05#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.203.07:31:11.05#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.203.07:31:11.05#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.203.07:31:11.05#ibcon#enter wrdev, iclass 28, count 0 2006.203.07:31:11.05#ibcon#first serial, iclass 28, count 0 2006.203.07:31:11.05#ibcon#enter sib2, iclass 28, count 0 2006.203.07:31:11.05#ibcon#flushed, iclass 28, count 0 2006.203.07:31:11.05#ibcon#about to write, iclass 28, count 0 2006.203.07:31:11.05#ibcon#wrote, iclass 28, count 0 2006.203.07:31:11.05#ibcon#about to read 3, iclass 28, count 0 2006.203.07:31:11.06#ibcon#read 3, iclass 28, count 0 2006.203.07:31:11.06#ibcon#about to read 4, iclass 28, count 0 2006.203.07:31:11.06#ibcon#read 4, iclass 28, count 0 2006.203.07:31:11.06#ibcon#about to read 5, iclass 28, count 0 2006.203.07:31:11.06#ibcon#read 5, iclass 28, count 0 2006.203.07:31:11.06#ibcon#about to read 6, iclass 28, count 0 2006.203.07:31:11.06#ibcon#read 6, iclass 28, count 0 2006.203.07:31:11.06#ibcon#end of sib2, iclass 28, count 0 2006.203.07:31:11.06#ibcon#*mode == 0, iclass 28, count 0 2006.203.07:31:11.06#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.203.07:31:11.06#ibcon#[28=FRQ=01,632.99\r\n] 2006.203.07:31:11.06#ibcon#*before write, iclass 28, count 0 2006.203.07:31:11.06#ibcon#enter sib2, iclass 28, count 0 2006.203.07:31:11.06#ibcon#flushed, iclass 28, count 0 2006.203.07:31:11.06#ibcon#about to write, iclass 28, count 0 2006.203.07:31:11.06#ibcon#wrote, iclass 28, count 0 2006.203.07:31:11.06#ibcon#about to read 3, iclass 28, count 0 2006.203.07:31:11.10#ibcon#read 3, iclass 28, count 0 2006.203.07:31:11.10#ibcon#about to read 4, iclass 28, count 0 2006.203.07:31:11.10#ibcon#read 4, iclass 28, count 0 2006.203.07:31:11.10#ibcon#about to read 5, iclass 28, count 0 2006.203.07:31:11.10#ibcon#read 5, iclass 28, count 0 2006.203.07:31:11.10#ibcon#about to read 6, iclass 28, count 0 2006.203.07:31:11.10#ibcon#read 6, iclass 28, count 0 2006.203.07:31:11.10#ibcon#end of sib2, iclass 28, count 0 2006.203.07:31:11.10#ibcon#*after write, iclass 28, count 0 2006.203.07:31:11.10#ibcon#*before return 0, iclass 28, count 0 2006.203.07:31:11.10#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.203.07:31:11.10#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.203.07:31:11.10#ibcon#about to clear, iclass 28 cls_cnt 0 2006.203.07:31:11.10#ibcon#cleared, iclass 28 cls_cnt 0 2006.203.07:31:11.11$vc4f8/vb=1,4 2006.203.07:31:11.11#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.203.07:31:11.11#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.203.07:31:11.11#ibcon#ireg 11 cls_cnt 2 2006.203.07:31:11.11#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.203.07:31:11.11#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.203.07:31:11.11#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.203.07:31:11.11#ibcon#enter wrdev, iclass 30, count 2 2006.203.07:31:11.11#ibcon#first serial, iclass 30, count 2 2006.203.07:31:11.11#ibcon#enter sib2, iclass 30, count 2 2006.203.07:31:11.11#ibcon#flushed, iclass 30, count 2 2006.203.07:31:11.11#ibcon#about to write, iclass 30, count 2 2006.203.07:31:11.11#ibcon#wrote, iclass 30, count 2 2006.203.07:31:11.11#ibcon#about to read 3, iclass 30, count 2 2006.203.07:31:11.12#ibcon#read 3, iclass 30, count 2 2006.203.07:31:11.12#ibcon#about to read 4, iclass 30, count 2 2006.203.07:31:11.12#ibcon#read 4, iclass 30, count 2 2006.203.07:31:11.12#ibcon#about to read 5, iclass 30, count 2 2006.203.07:31:11.12#ibcon#read 5, iclass 30, count 2 2006.203.07:31:11.12#ibcon#about to read 6, iclass 30, count 2 2006.203.07:31:11.12#ibcon#read 6, iclass 30, count 2 2006.203.07:31:11.12#ibcon#end of sib2, iclass 30, count 2 2006.203.07:31:11.12#ibcon#*mode == 0, iclass 30, count 2 2006.203.07:31:11.12#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.203.07:31:11.12#ibcon#[27=AT01-04\r\n] 2006.203.07:31:11.12#ibcon#*before write, iclass 30, count 2 2006.203.07:31:11.12#ibcon#enter sib2, iclass 30, count 2 2006.203.07:31:11.12#ibcon#flushed, iclass 30, count 2 2006.203.07:31:11.12#ibcon#about to write, iclass 30, count 2 2006.203.07:31:11.12#ibcon#wrote, iclass 30, count 2 2006.203.07:31:11.12#ibcon#about to read 3, iclass 30, count 2 2006.203.07:31:11.15#ibcon#read 3, iclass 30, count 2 2006.203.07:31:11.15#ibcon#about to read 4, iclass 30, count 2 2006.203.07:31:11.15#ibcon#read 4, iclass 30, count 2 2006.203.07:31:11.15#ibcon#about to read 5, iclass 30, count 2 2006.203.07:31:11.15#ibcon#read 5, iclass 30, count 2 2006.203.07:31:11.15#ibcon#about to read 6, iclass 30, count 2 2006.203.07:31:11.15#ibcon#read 6, iclass 30, count 2 2006.203.07:31:11.15#ibcon#end of sib2, iclass 30, count 2 2006.203.07:31:11.15#ibcon#*after write, iclass 30, count 2 2006.203.07:31:11.15#ibcon#*before return 0, iclass 30, count 2 2006.203.07:31:11.15#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.203.07:31:11.15#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.203.07:31:11.15#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.203.07:31:11.15#ibcon#ireg 7 cls_cnt 0 2006.203.07:31:11.15#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.203.07:31:11.28#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.203.07:31:11.28#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.203.07:31:11.28#ibcon#enter wrdev, iclass 30, count 0 2006.203.07:31:11.28#ibcon#first serial, iclass 30, count 0 2006.203.07:31:11.28#ibcon#enter sib2, iclass 30, count 0 2006.203.07:31:11.28#ibcon#flushed, iclass 30, count 0 2006.203.07:31:11.28#ibcon#about to write, iclass 30, count 0 2006.203.07:31:11.28#ibcon#wrote, iclass 30, count 0 2006.203.07:31:11.28#ibcon#about to read 3, iclass 30, count 0 2006.203.07:31:11.29#ibcon#read 3, iclass 30, count 0 2006.203.07:31:11.29#ibcon#about to read 4, iclass 30, count 0 2006.203.07:31:11.29#ibcon#read 4, iclass 30, count 0 2006.203.07:31:11.29#ibcon#about to read 5, iclass 30, count 0 2006.203.07:31:11.29#ibcon#read 5, iclass 30, count 0 2006.203.07:31:11.29#ibcon#about to read 6, iclass 30, count 0 2006.203.07:31:11.29#ibcon#read 6, iclass 30, count 0 2006.203.07:31:11.29#ibcon#end of sib2, iclass 30, count 0 2006.203.07:31:11.29#ibcon#*mode == 0, iclass 30, count 0 2006.203.07:31:11.29#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.203.07:31:11.29#ibcon#[27=USB\r\n] 2006.203.07:31:11.29#ibcon#*before write, iclass 30, count 0 2006.203.07:31:11.29#ibcon#enter sib2, iclass 30, count 0 2006.203.07:31:11.29#ibcon#flushed, iclass 30, count 0 2006.203.07:31:11.29#ibcon#about to write, iclass 30, count 0 2006.203.07:31:11.29#ibcon#wrote, iclass 30, count 0 2006.203.07:31:11.29#ibcon#about to read 3, iclass 30, count 0 2006.203.07:31:11.32#ibcon#read 3, iclass 30, count 0 2006.203.07:31:11.32#ibcon#about to read 4, iclass 30, count 0 2006.203.07:31:11.32#ibcon#read 4, iclass 30, count 0 2006.203.07:31:11.32#ibcon#about to read 5, iclass 30, count 0 2006.203.07:31:11.32#ibcon#read 5, iclass 30, count 0 2006.203.07:31:11.32#ibcon#about to read 6, iclass 30, count 0 2006.203.07:31:11.32#ibcon#read 6, iclass 30, count 0 2006.203.07:31:11.32#ibcon#end of sib2, iclass 30, count 0 2006.203.07:31:11.32#ibcon#*after write, iclass 30, count 0 2006.203.07:31:11.32#ibcon#*before return 0, iclass 30, count 0 2006.203.07:31:11.32#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.203.07:31:11.32#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.203.07:31:11.32#ibcon#about to clear, iclass 30 cls_cnt 0 2006.203.07:31:11.32#ibcon#cleared, iclass 30 cls_cnt 0 2006.203.07:31:11.33$vc4f8/vblo=2,640.99 2006.203.07:31:11.33#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.203.07:31:11.33#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.203.07:31:11.33#ibcon#ireg 17 cls_cnt 0 2006.203.07:31:11.33#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.203.07:31:11.33#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.203.07:31:11.33#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.203.07:31:11.33#ibcon#enter wrdev, iclass 32, count 0 2006.203.07:31:11.33#ibcon#first serial, iclass 32, count 0 2006.203.07:31:11.33#ibcon#enter sib2, iclass 32, count 0 2006.203.07:31:11.33#ibcon#flushed, iclass 32, count 0 2006.203.07:31:11.33#ibcon#about to write, iclass 32, count 0 2006.203.07:31:11.33#ibcon#wrote, iclass 32, count 0 2006.203.07:31:11.33#ibcon#about to read 3, iclass 32, count 0 2006.203.07:31:11.34#ibcon#read 3, iclass 32, count 0 2006.203.07:31:11.34#ibcon#about to read 4, iclass 32, count 0 2006.203.07:31:11.34#ibcon#read 4, iclass 32, count 0 2006.203.07:31:11.34#ibcon#about to read 5, iclass 32, count 0 2006.203.07:31:11.34#ibcon#read 5, iclass 32, count 0 2006.203.07:31:11.34#ibcon#about to read 6, iclass 32, count 0 2006.203.07:31:11.34#ibcon#read 6, iclass 32, count 0 2006.203.07:31:11.34#ibcon#end of sib2, iclass 32, count 0 2006.203.07:31:11.34#ibcon#*mode == 0, iclass 32, count 0 2006.203.07:31:11.34#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.203.07:31:11.34#ibcon#[28=FRQ=02,640.99\r\n] 2006.203.07:31:11.34#ibcon#*before write, iclass 32, count 0 2006.203.07:31:11.34#ibcon#enter sib2, iclass 32, count 0 2006.203.07:31:11.34#ibcon#flushed, iclass 32, count 0 2006.203.07:31:11.34#ibcon#about to write, iclass 32, count 0 2006.203.07:31:11.34#ibcon#wrote, iclass 32, count 0 2006.203.07:31:11.34#ibcon#about to read 3, iclass 32, count 0 2006.203.07:31:11.38#ibcon#read 3, iclass 32, count 0 2006.203.07:31:11.38#ibcon#about to read 4, iclass 32, count 0 2006.203.07:31:11.38#ibcon#read 4, iclass 32, count 0 2006.203.07:31:11.38#ibcon#about to read 5, iclass 32, count 0 2006.203.07:31:11.38#ibcon#read 5, iclass 32, count 0 2006.203.07:31:11.38#ibcon#about to read 6, iclass 32, count 0 2006.203.07:31:11.38#ibcon#read 6, iclass 32, count 0 2006.203.07:31:11.38#ibcon#end of sib2, iclass 32, count 0 2006.203.07:31:11.38#ibcon#*after write, iclass 32, count 0 2006.203.07:31:11.38#ibcon#*before return 0, iclass 32, count 0 2006.203.07:31:11.38#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.203.07:31:11.38#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.203.07:31:11.38#ibcon#about to clear, iclass 32 cls_cnt 0 2006.203.07:31:11.38#ibcon#cleared, iclass 32 cls_cnt 0 2006.203.07:31:11.39$vc4f8/vb=2,4 2006.203.07:31:11.39#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.203.07:31:11.39#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.203.07:31:11.39#ibcon#ireg 11 cls_cnt 2 2006.203.07:31:11.39#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.203.07:31:11.43#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.203.07:31:11.43#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.203.07:31:11.43#ibcon#enter wrdev, iclass 34, count 2 2006.203.07:31:11.43#ibcon#first serial, iclass 34, count 2 2006.203.07:31:11.43#ibcon#enter sib2, iclass 34, count 2 2006.203.07:31:11.43#ibcon#flushed, iclass 34, count 2 2006.203.07:31:11.43#ibcon#about to write, iclass 34, count 2 2006.203.07:31:11.43#ibcon#wrote, iclass 34, count 2 2006.203.07:31:11.43#ibcon#about to read 3, iclass 34, count 2 2006.203.07:31:11.45#ibcon#read 3, iclass 34, count 2 2006.203.07:31:11.45#ibcon#about to read 4, iclass 34, count 2 2006.203.07:31:11.45#ibcon#read 4, iclass 34, count 2 2006.203.07:31:11.45#ibcon#about to read 5, iclass 34, count 2 2006.203.07:31:11.45#ibcon#read 5, iclass 34, count 2 2006.203.07:31:11.45#ibcon#about to read 6, iclass 34, count 2 2006.203.07:31:11.45#ibcon#read 6, iclass 34, count 2 2006.203.07:31:11.45#ibcon#end of sib2, iclass 34, count 2 2006.203.07:31:11.45#ibcon#*mode == 0, iclass 34, count 2 2006.203.07:31:11.45#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.203.07:31:11.45#ibcon#[27=AT02-04\r\n] 2006.203.07:31:11.45#ibcon#*before write, iclass 34, count 2 2006.203.07:31:11.45#ibcon#enter sib2, iclass 34, count 2 2006.203.07:31:11.45#ibcon#flushed, iclass 34, count 2 2006.203.07:31:11.45#ibcon#about to write, iclass 34, count 2 2006.203.07:31:11.45#ibcon#wrote, iclass 34, count 2 2006.203.07:31:11.45#ibcon#about to read 3, iclass 34, count 2 2006.203.07:31:11.48#ibcon#read 3, iclass 34, count 2 2006.203.07:31:11.48#ibcon#about to read 4, iclass 34, count 2 2006.203.07:31:11.48#ibcon#read 4, iclass 34, count 2 2006.203.07:31:11.48#ibcon#about to read 5, iclass 34, count 2 2006.203.07:31:11.48#ibcon#read 5, iclass 34, count 2 2006.203.07:31:11.48#ibcon#about to read 6, iclass 34, count 2 2006.203.07:31:11.48#ibcon#read 6, iclass 34, count 2 2006.203.07:31:11.48#ibcon#end of sib2, iclass 34, count 2 2006.203.07:31:11.48#ibcon#*after write, iclass 34, count 2 2006.203.07:31:11.48#ibcon#*before return 0, iclass 34, count 2 2006.203.07:31:11.48#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.203.07:31:11.48#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.203.07:31:11.48#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.203.07:31:11.48#ibcon#ireg 7 cls_cnt 0 2006.203.07:31:11.48#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.203.07:31:11.60#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.203.07:31:11.60#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.203.07:31:11.60#ibcon#enter wrdev, iclass 34, count 0 2006.203.07:31:11.60#ibcon#first serial, iclass 34, count 0 2006.203.07:31:11.60#ibcon#enter sib2, iclass 34, count 0 2006.203.07:31:11.60#ibcon#flushed, iclass 34, count 0 2006.203.07:31:11.60#ibcon#about to write, iclass 34, count 0 2006.203.07:31:11.60#ibcon#wrote, iclass 34, count 0 2006.203.07:31:11.60#ibcon#about to read 3, iclass 34, count 0 2006.203.07:31:11.62#ibcon#read 3, iclass 34, count 0 2006.203.07:31:11.62#ibcon#about to read 4, iclass 34, count 0 2006.203.07:31:11.62#ibcon#read 4, iclass 34, count 0 2006.203.07:31:11.62#ibcon#about to read 5, iclass 34, count 0 2006.203.07:31:11.62#ibcon#read 5, iclass 34, count 0 2006.203.07:31:11.62#ibcon#about to read 6, iclass 34, count 0 2006.203.07:31:11.62#ibcon#read 6, iclass 34, count 0 2006.203.07:31:11.62#ibcon#end of sib2, iclass 34, count 0 2006.203.07:31:11.62#ibcon#*mode == 0, iclass 34, count 0 2006.203.07:31:11.62#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.203.07:31:11.62#ibcon#[27=USB\r\n] 2006.203.07:31:11.62#ibcon#*before write, iclass 34, count 0 2006.203.07:31:11.62#ibcon#enter sib2, iclass 34, count 0 2006.203.07:31:11.62#ibcon#flushed, iclass 34, count 0 2006.203.07:31:11.62#ibcon#about to write, iclass 34, count 0 2006.203.07:31:11.62#ibcon#wrote, iclass 34, count 0 2006.203.07:31:11.62#ibcon#about to read 3, iclass 34, count 0 2006.203.07:31:11.65#ibcon#read 3, iclass 34, count 0 2006.203.07:31:11.65#ibcon#about to read 4, iclass 34, count 0 2006.203.07:31:11.65#ibcon#read 4, iclass 34, count 0 2006.203.07:31:11.65#ibcon#about to read 5, iclass 34, count 0 2006.203.07:31:11.65#ibcon#read 5, iclass 34, count 0 2006.203.07:31:11.65#ibcon#about to read 6, iclass 34, count 0 2006.203.07:31:11.65#ibcon#read 6, iclass 34, count 0 2006.203.07:31:11.65#ibcon#end of sib2, iclass 34, count 0 2006.203.07:31:11.65#ibcon#*after write, iclass 34, count 0 2006.203.07:31:11.65#ibcon#*before return 0, iclass 34, count 0 2006.203.07:31:11.65#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.203.07:31:11.65#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.203.07:31:11.65#ibcon#about to clear, iclass 34 cls_cnt 0 2006.203.07:31:11.65#ibcon#cleared, iclass 34 cls_cnt 0 2006.203.07:31:11.66$vc4f8/vblo=3,656.99 2006.203.07:31:11.66#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.203.07:31:11.66#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.203.07:31:11.66#ibcon#ireg 17 cls_cnt 0 2006.203.07:31:11.66#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.203.07:31:11.66#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.203.07:31:11.66#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.203.07:31:11.66#ibcon#enter wrdev, iclass 36, count 0 2006.203.07:31:11.66#ibcon#first serial, iclass 36, count 0 2006.203.07:31:11.66#ibcon#enter sib2, iclass 36, count 0 2006.203.07:31:11.66#ibcon#flushed, iclass 36, count 0 2006.203.07:31:11.66#ibcon#about to write, iclass 36, count 0 2006.203.07:31:11.66#ibcon#wrote, iclass 36, count 0 2006.203.07:31:11.66#ibcon#about to read 3, iclass 36, count 0 2006.203.07:31:11.67#ibcon#read 3, iclass 36, count 0 2006.203.07:31:11.67#ibcon#about to read 4, iclass 36, count 0 2006.203.07:31:11.67#ibcon#read 4, iclass 36, count 0 2006.203.07:31:11.67#ibcon#about to read 5, iclass 36, count 0 2006.203.07:31:11.67#ibcon#read 5, iclass 36, count 0 2006.203.07:31:11.67#ibcon#about to read 6, iclass 36, count 0 2006.203.07:31:11.67#ibcon#read 6, iclass 36, count 0 2006.203.07:31:11.67#ibcon#end of sib2, iclass 36, count 0 2006.203.07:31:11.67#ibcon#*mode == 0, iclass 36, count 0 2006.203.07:31:11.67#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.203.07:31:11.67#ibcon#[28=FRQ=03,656.99\r\n] 2006.203.07:31:11.67#ibcon#*before write, iclass 36, count 0 2006.203.07:31:11.67#ibcon#enter sib2, iclass 36, count 0 2006.203.07:31:11.67#ibcon#flushed, iclass 36, count 0 2006.203.07:31:11.67#ibcon#about to write, iclass 36, count 0 2006.203.07:31:11.67#ibcon#wrote, iclass 36, count 0 2006.203.07:31:11.67#ibcon#about to read 3, iclass 36, count 0 2006.203.07:31:11.71#ibcon#read 3, iclass 36, count 0 2006.203.07:31:11.71#ibcon#about to read 4, iclass 36, count 0 2006.203.07:31:11.71#ibcon#read 4, iclass 36, count 0 2006.203.07:31:11.71#ibcon#about to read 5, iclass 36, count 0 2006.203.07:31:11.71#ibcon#read 5, iclass 36, count 0 2006.203.07:31:11.71#ibcon#about to read 6, iclass 36, count 0 2006.203.07:31:11.71#ibcon#read 6, iclass 36, count 0 2006.203.07:31:11.71#ibcon#end of sib2, iclass 36, count 0 2006.203.07:31:11.71#ibcon#*after write, iclass 36, count 0 2006.203.07:31:11.71#ibcon#*before return 0, iclass 36, count 0 2006.203.07:31:11.71#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.203.07:31:11.71#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.203.07:31:11.71#ibcon#about to clear, iclass 36 cls_cnt 0 2006.203.07:31:11.71#ibcon#cleared, iclass 36 cls_cnt 0 2006.203.07:31:11.72$vc4f8/vb=3,4 2006.203.07:31:11.72#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.203.07:31:11.72#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.203.07:31:11.72#ibcon#ireg 11 cls_cnt 2 2006.203.07:31:11.72#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.203.07:31:11.76#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.203.07:31:11.76#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.203.07:31:11.76#ibcon#enter wrdev, iclass 38, count 2 2006.203.07:31:11.76#ibcon#first serial, iclass 38, count 2 2006.203.07:31:11.76#ibcon#enter sib2, iclass 38, count 2 2006.203.07:31:11.76#ibcon#flushed, iclass 38, count 2 2006.203.07:31:11.76#ibcon#about to write, iclass 38, count 2 2006.203.07:31:11.76#ibcon#wrote, iclass 38, count 2 2006.203.07:31:11.76#ibcon#about to read 3, iclass 38, count 2 2006.203.07:31:11.78#ibcon#read 3, iclass 38, count 2 2006.203.07:31:11.78#ibcon#about to read 4, iclass 38, count 2 2006.203.07:31:11.78#ibcon#read 4, iclass 38, count 2 2006.203.07:31:11.78#ibcon#about to read 5, iclass 38, count 2 2006.203.07:31:11.78#ibcon#read 5, iclass 38, count 2 2006.203.07:31:11.78#ibcon#about to read 6, iclass 38, count 2 2006.203.07:31:11.78#ibcon#read 6, iclass 38, count 2 2006.203.07:31:11.78#ibcon#end of sib2, iclass 38, count 2 2006.203.07:31:11.78#ibcon#*mode == 0, iclass 38, count 2 2006.203.07:31:11.78#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.203.07:31:11.78#ibcon#[27=AT03-04\r\n] 2006.203.07:31:11.78#ibcon#*before write, iclass 38, count 2 2006.203.07:31:11.78#ibcon#enter sib2, iclass 38, count 2 2006.203.07:31:11.78#ibcon#flushed, iclass 38, count 2 2006.203.07:31:11.78#ibcon#about to write, iclass 38, count 2 2006.203.07:31:11.78#ibcon#wrote, iclass 38, count 2 2006.203.07:31:11.78#ibcon#about to read 3, iclass 38, count 2 2006.203.07:31:11.81#ibcon#read 3, iclass 38, count 2 2006.203.07:31:11.81#ibcon#about to read 4, iclass 38, count 2 2006.203.07:31:11.81#ibcon#read 4, iclass 38, count 2 2006.203.07:31:11.81#ibcon#about to read 5, iclass 38, count 2 2006.203.07:31:11.81#ibcon#read 5, iclass 38, count 2 2006.203.07:31:11.81#ibcon#about to read 6, iclass 38, count 2 2006.203.07:31:11.81#ibcon#read 6, iclass 38, count 2 2006.203.07:31:11.81#ibcon#end of sib2, iclass 38, count 2 2006.203.07:31:11.81#ibcon#*after write, iclass 38, count 2 2006.203.07:31:11.81#ibcon#*before return 0, iclass 38, count 2 2006.203.07:31:11.81#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.203.07:31:11.81#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.203.07:31:11.81#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.203.07:31:11.81#ibcon#ireg 7 cls_cnt 0 2006.203.07:31:11.81#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.203.07:31:11.93#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.203.07:31:11.93#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.203.07:31:11.93#ibcon#enter wrdev, iclass 38, count 0 2006.203.07:31:11.93#ibcon#first serial, iclass 38, count 0 2006.203.07:31:11.93#ibcon#enter sib2, iclass 38, count 0 2006.203.07:31:11.93#ibcon#flushed, iclass 38, count 0 2006.203.07:31:11.93#ibcon#about to write, iclass 38, count 0 2006.203.07:31:11.93#ibcon#wrote, iclass 38, count 0 2006.203.07:31:11.93#ibcon#about to read 3, iclass 38, count 0 2006.203.07:31:11.95#ibcon#read 3, iclass 38, count 0 2006.203.07:31:11.95#ibcon#about to read 4, iclass 38, count 0 2006.203.07:31:11.95#ibcon#read 4, iclass 38, count 0 2006.203.07:31:11.95#ibcon#about to read 5, iclass 38, count 0 2006.203.07:31:11.95#ibcon#read 5, iclass 38, count 0 2006.203.07:31:11.95#ibcon#about to read 6, iclass 38, count 0 2006.203.07:31:11.95#ibcon#read 6, iclass 38, count 0 2006.203.07:31:11.95#ibcon#end of sib2, iclass 38, count 0 2006.203.07:31:11.95#ibcon#*mode == 0, iclass 38, count 0 2006.203.07:31:11.95#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.203.07:31:11.95#ibcon#[27=USB\r\n] 2006.203.07:31:11.95#ibcon#*before write, iclass 38, count 0 2006.203.07:31:11.95#ibcon#enter sib2, iclass 38, count 0 2006.203.07:31:11.95#ibcon#flushed, iclass 38, count 0 2006.203.07:31:11.95#ibcon#about to write, iclass 38, count 0 2006.203.07:31:11.95#ibcon#wrote, iclass 38, count 0 2006.203.07:31:11.95#ibcon#about to read 3, iclass 38, count 0 2006.203.07:31:11.98#ibcon#read 3, iclass 38, count 0 2006.203.07:31:11.98#ibcon#about to read 4, iclass 38, count 0 2006.203.07:31:11.98#ibcon#read 4, iclass 38, count 0 2006.203.07:31:11.98#ibcon#about to read 5, iclass 38, count 0 2006.203.07:31:11.98#ibcon#read 5, iclass 38, count 0 2006.203.07:31:11.98#ibcon#about to read 6, iclass 38, count 0 2006.203.07:31:11.98#ibcon#read 6, iclass 38, count 0 2006.203.07:31:11.98#ibcon#end of sib2, iclass 38, count 0 2006.203.07:31:11.98#ibcon#*after write, iclass 38, count 0 2006.203.07:31:11.98#ibcon#*before return 0, iclass 38, count 0 2006.203.07:31:11.98#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.203.07:31:11.98#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.203.07:31:11.98#ibcon#about to clear, iclass 38 cls_cnt 0 2006.203.07:31:11.98#ibcon#cleared, iclass 38 cls_cnt 0 2006.203.07:31:11.99$vc4f8/vblo=4,712.99 2006.203.07:31:11.99#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.203.07:31:11.99#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.203.07:31:11.99#ibcon#ireg 17 cls_cnt 0 2006.203.07:31:11.99#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.203.07:31:11.99#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.203.07:31:11.99#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.203.07:31:11.99#ibcon#enter wrdev, iclass 40, count 0 2006.203.07:31:11.99#ibcon#first serial, iclass 40, count 0 2006.203.07:31:11.99#ibcon#enter sib2, iclass 40, count 0 2006.203.07:31:11.99#ibcon#flushed, iclass 40, count 0 2006.203.07:31:11.99#ibcon#about to write, iclass 40, count 0 2006.203.07:31:11.99#ibcon#wrote, iclass 40, count 0 2006.203.07:31:11.99#ibcon#about to read 3, iclass 40, count 0 2006.203.07:31:12.00#ibcon#read 3, iclass 40, count 0 2006.203.07:31:12.00#ibcon#about to read 4, iclass 40, count 0 2006.203.07:31:12.00#ibcon#read 4, iclass 40, count 0 2006.203.07:31:12.00#ibcon#about to read 5, iclass 40, count 0 2006.203.07:31:12.00#ibcon#read 5, iclass 40, count 0 2006.203.07:31:12.00#ibcon#about to read 6, iclass 40, count 0 2006.203.07:31:12.00#ibcon#read 6, iclass 40, count 0 2006.203.07:31:12.00#ibcon#end of sib2, iclass 40, count 0 2006.203.07:31:12.00#ibcon#*mode == 0, iclass 40, count 0 2006.203.07:31:12.00#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.203.07:31:12.00#ibcon#[28=FRQ=04,712.99\r\n] 2006.203.07:31:12.00#ibcon#*before write, iclass 40, count 0 2006.203.07:31:12.00#ibcon#enter sib2, iclass 40, count 0 2006.203.07:31:12.00#ibcon#flushed, iclass 40, count 0 2006.203.07:31:12.00#ibcon#about to write, iclass 40, count 0 2006.203.07:31:12.00#ibcon#wrote, iclass 40, count 0 2006.203.07:31:12.00#ibcon#about to read 3, iclass 40, count 0 2006.203.07:31:12.04#ibcon#read 3, iclass 40, count 0 2006.203.07:31:12.04#ibcon#about to read 4, iclass 40, count 0 2006.203.07:31:12.04#ibcon#read 4, iclass 40, count 0 2006.203.07:31:12.04#ibcon#about to read 5, iclass 40, count 0 2006.203.07:31:12.04#ibcon#read 5, iclass 40, count 0 2006.203.07:31:12.04#ibcon#about to read 6, iclass 40, count 0 2006.203.07:31:12.04#ibcon#read 6, iclass 40, count 0 2006.203.07:31:12.04#ibcon#end of sib2, iclass 40, count 0 2006.203.07:31:12.04#ibcon#*after write, iclass 40, count 0 2006.203.07:31:12.04#ibcon#*before return 0, iclass 40, count 0 2006.203.07:31:12.04#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.203.07:31:12.04#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.203.07:31:12.04#ibcon#about to clear, iclass 40 cls_cnt 0 2006.203.07:31:12.04#ibcon#cleared, iclass 40 cls_cnt 0 2006.203.07:31:12.05$vc4f8/vb=4,4 2006.203.07:31:12.05#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.203.07:31:12.05#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.203.07:31:12.05#ibcon#ireg 11 cls_cnt 2 2006.203.07:31:12.05#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.203.07:31:12.09#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.203.07:31:12.09#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.203.07:31:12.09#ibcon#enter wrdev, iclass 4, count 2 2006.203.07:31:12.09#ibcon#first serial, iclass 4, count 2 2006.203.07:31:12.09#ibcon#enter sib2, iclass 4, count 2 2006.203.07:31:12.09#ibcon#flushed, iclass 4, count 2 2006.203.07:31:12.09#ibcon#about to write, iclass 4, count 2 2006.203.07:31:12.09#ibcon#wrote, iclass 4, count 2 2006.203.07:31:12.09#ibcon#about to read 3, iclass 4, count 2 2006.203.07:31:12.11#ibcon#read 3, iclass 4, count 2 2006.203.07:31:12.11#ibcon#about to read 4, iclass 4, count 2 2006.203.07:31:12.11#ibcon#read 4, iclass 4, count 2 2006.203.07:31:12.11#ibcon#about to read 5, iclass 4, count 2 2006.203.07:31:12.11#ibcon#read 5, iclass 4, count 2 2006.203.07:31:12.11#ibcon#about to read 6, iclass 4, count 2 2006.203.07:31:12.11#ibcon#read 6, iclass 4, count 2 2006.203.07:31:12.11#ibcon#end of sib2, iclass 4, count 2 2006.203.07:31:12.11#ibcon#*mode == 0, iclass 4, count 2 2006.203.07:31:12.11#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.203.07:31:12.11#ibcon#[27=AT04-04\r\n] 2006.203.07:31:12.11#ibcon#*before write, iclass 4, count 2 2006.203.07:31:12.11#ibcon#enter sib2, iclass 4, count 2 2006.203.07:31:12.11#ibcon#flushed, iclass 4, count 2 2006.203.07:31:12.11#ibcon#about to write, iclass 4, count 2 2006.203.07:31:12.11#ibcon#wrote, iclass 4, count 2 2006.203.07:31:12.11#ibcon#about to read 3, iclass 4, count 2 2006.203.07:31:12.14#ibcon#read 3, iclass 4, count 2 2006.203.07:31:12.14#ibcon#about to read 4, iclass 4, count 2 2006.203.07:31:12.14#ibcon#read 4, iclass 4, count 2 2006.203.07:31:12.14#ibcon#about to read 5, iclass 4, count 2 2006.203.07:31:12.14#ibcon#read 5, iclass 4, count 2 2006.203.07:31:12.14#ibcon#about to read 6, iclass 4, count 2 2006.203.07:31:12.14#ibcon#read 6, iclass 4, count 2 2006.203.07:31:12.14#ibcon#end of sib2, iclass 4, count 2 2006.203.07:31:12.14#ibcon#*after write, iclass 4, count 2 2006.203.07:31:12.14#ibcon#*before return 0, iclass 4, count 2 2006.203.07:31:12.14#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.203.07:31:12.14#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.203.07:31:12.14#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.203.07:31:12.14#ibcon#ireg 7 cls_cnt 0 2006.203.07:31:12.14#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.203.07:31:12.26#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.203.07:31:12.26#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.203.07:31:12.26#ibcon#enter wrdev, iclass 4, count 0 2006.203.07:31:12.26#ibcon#first serial, iclass 4, count 0 2006.203.07:31:12.26#ibcon#enter sib2, iclass 4, count 0 2006.203.07:31:12.26#ibcon#flushed, iclass 4, count 0 2006.203.07:31:12.26#ibcon#about to write, iclass 4, count 0 2006.203.07:31:12.26#ibcon#wrote, iclass 4, count 0 2006.203.07:31:12.26#ibcon#about to read 3, iclass 4, count 0 2006.203.07:31:12.28#ibcon#read 3, iclass 4, count 0 2006.203.07:31:12.28#ibcon#about to read 4, iclass 4, count 0 2006.203.07:31:12.28#ibcon#read 4, iclass 4, count 0 2006.203.07:31:12.28#ibcon#about to read 5, iclass 4, count 0 2006.203.07:31:12.28#ibcon#read 5, iclass 4, count 0 2006.203.07:31:12.28#ibcon#about to read 6, iclass 4, count 0 2006.203.07:31:12.28#ibcon#read 6, iclass 4, count 0 2006.203.07:31:12.28#ibcon#end of sib2, iclass 4, count 0 2006.203.07:31:12.28#ibcon#*mode == 0, iclass 4, count 0 2006.203.07:31:12.28#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.203.07:31:12.28#ibcon#[27=USB\r\n] 2006.203.07:31:12.28#ibcon#*before write, iclass 4, count 0 2006.203.07:31:12.28#ibcon#enter sib2, iclass 4, count 0 2006.203.07:31:12.28#ibcon#flushed, iclass 4, count 0 2006.203.07:31:12.28#ibcon#about to write, iclass 4, count 0 2006.203.07:31:12.28#ibcon#wrote, iclass 4, count 0 2006.203.07:31:12.28#ibcon#about to read 3, iclass 4, count 0 2006.203.07:31:12.31#ibcon#read 3, iclass 4, count 0 2006.203.07:31:12.31#ibcon#about to read 4, iclass 4, count 0 2006.203.07:31:12.31#ibcon#read 4, iclass 4, count 0 2006.203.07:31:12.31#ibcon#about to read 5, iclass 4, count 0 2006.203.07:31:12.31#ibcon#read 5, iclass 4, count 0 2006.203.07:31:12.31#ibcon#about to read 6, iclass 4, count 0 2006.203.07:31:12.31#ibcon#read 6, iclass 4, count 0 2006.203.07:31:12.31#ibcon#end of sib2, iclass 4, count 0 2006.203.07:31:12.31#ibcon#*after write, iclass 4, count 0 2006.203.07:31:12.31#ibcon#*before return 0, iclass 4, count 0 2006.203.07:31:12.31#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.203.07:31:12.31#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.203.07:31:12.31#ibcon#about to clear, iclass 4 cls_cnt 0 2006.203.07:31:12.31#ibcon#cleared, iclass 4 cls_cnt 0 2006.203.07:31:12.32$vc4f8/vblo=5,744.99 2006.203.07:31:12.32#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.203.07:31:12.32#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.203.07:31:12.32#ibcon#ireg 17 cls_cnt 0 2006.203.07:31:12.32#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.203.07:31:12.32#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.203.07:31:12.32#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.203.07:31:12.32#ibcon#enter wrdev, iclass 6, count 0 2006.203.07:31:12.32#ibcon#first serial, iclass 6, count 0 2006.203.07:31:12.32#ibcon#enter sib2, iclass 6, count 0 2006.203.07:31:12.32#ibcon#flushed, iclass 6, count 0 2006.203.07:31:12.32#ibcon#about to write, iclass 6, count 0 2006.203.07:31:12.32#ibcon#wrote, iclass 6, count 0 2006.203.07:31:12.32#ibcon#about to read 3, iclass 6, count 0 2006.203.07:31:12.33#ibcon#read 3, iclass 6, count 0 2006.203.07:31:12.33#ibcon#about to read 4, iclass 6, count 0 2006.203.07:31:12.33#ibcon#read 4, iclass 6, count 0 2006.203.07:31:12.33#ibcon#about to read 5, iclass 6, count 0 2006.203.07:31:12.33#ibcon#read 5, iclass 6, count 0 2006.203.07:31:12.33#ibcon#about to read 6, iclass 6, count 0 2006.203.07:31:12.33#ibcon#read 6, iclass 6, count 0 2006.203.07:31:12.33#ibcon#end of sib2, iclass 6, count 0 2006.203.07:31:12.33#ibcon#*mode == 0, iclass 6, count 0 2006.203.07:31:12.33#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.203.07:31:12.33#ibcon#[28=FRQ=05,744.99\r\n] 2006.203.07:31:12.33#ibcon#*before write, iclass 6, count 0 2006.203.07:31:12.33#ibcon#enter sib2, iclass 6, count 0 2006.203.07:31:12.33#ibcon#flushed, iclass 6, count 0 2006.203.07:31:12.33#ibcon#about to write, iclass 6, count 0 2006.203.07:31:12.33#ibcon#wrote, iclass 6, count 0 2006.203.07:31:12.33#ibcon#about to read 3, iclass 6, count 0 2006.203.07:31:12.37#ibcon#read 3, iclass 6, count 0 2006.203.07:31:12.37#ibcon#about to read 4, iclass 6, count 0 2006.203.07:31:12.37#ibcon#read 4, iclass 6, count 0 2006.203.07:31:12.37#ibcon#about to read 5, iclass 6, count 0 2006.203.07:31:12.37#ibcon#read 5, iclass 6, count 0 2006.203.07:31:12.37#ibcon#about to read 6, iclass 6, count 0 2006.203.07:31:12.37#ibcon#read 6, iclass 6, count 0 2006.203.07:31:12.37#ibcon#end of sib2, iclass 6, count 0 2006.203.07:31:12.37#ibcon#*after write, iclass 6, count 0 2006.203.07:31:12.37#ibcon#*before return 0, iclass 6, count 0 2006.203.07:31:12.37#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.203.07:31:12.37#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.203.07:31:12.37#ibcon#about to clear, iclass 6 cls_cnt 0 2006.203.07:31:12.37#ibcon#cleared, iclass 6 cls_cnt 0 2006.203.07:31:12.38$vc4f8/vb=5,3 2006.203.07:31:12.38#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.203.07:31:12.38#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.203.07:31:12.38#ibcon#ireg 11 cls_cnt 2 2006.203.07:31:12.38#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.203.07:31:12.42#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.203.07:31:12.42#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.203.07:31:12.42#ibcon#enter wrdev, iclass 10, count 2 2006.203.07:31:12.42#ibcon#first serial, iclass 10, count 2 2006.203.07:31:12.42#ibcon#enter sib2, iclass 10, count 2 2006.203.07:31:12.42#ibcon#flushed, iclass 10, count 2 2006.203.07:31:12.42#ibcon#about to write, iclass 10, count 2 2006.203.07:31:12.42#ibcon#wrote, iclass 10, count 2 2006.203.07:31:12.42#ibcon#about to read 3, iclass 10, count 2 2006.203.07:31:12.44#ibcon#read 3, iclass 10, count 2 2006.203.07:31:12.44#ibcon#about to read 4, iclass 10, count 2 2006.203.07:31:12.44#ibcon#read 4, iclass 10, count 2 2006.203.07:31:12.44#ibcon#about to read 5, iclass 10, count 2 2006.203.07:31:12.44#ibcon#read 5, iclass 10, count 2 2006.203.07:31:12.44#ibcon#about to read 6, iclass 10, count 2 2006.203.07:31:12.44#ibcon#read 6, iclass 10, count 2 2006.203.07:31:12.44#ibcon#end of sib2, iclass 10, count 2 2006.203.07:31:12.44#ibcon#*mode == 0, iclass 10, count 2 2006.203.07:31:12.44#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.203.07:31:12.44#ibcon#[27=AT05-03\r\n] 2006.203.07:31:12.44#ibcon#*before write, iclass 10, count 2 2006.203.07:31:12.44#ibcon#enter sib2, iclass 10, count 2 2006.203.07:31:12.44#ibcon#flushed, iclass 10, count 2 2006.203.07:31:12.44#ibcon#about to write, iclass 10, count 2 2006.203.07:31:12.44#ibcon#wrote, iclass 10, count 2 2006.203.07:31:12.44#ibcon#about to read 3, iclass 10, count 2 2006.203.07:31:12.47#ibcon#read 3, iclass 10, count 2 2006.203.07:31:12.47#ibcon#about to read 4, iclass 10, count 2 2006.203.07:31:12.47#ibcon#read 4, iclass 10, count 2 2006.203.07:31:12.47#ibcon#about to read 5, iclass 10, count 2 2006.203.07:31:12.47#ibcon#read 5, iclass 10, count 2 2006.203.07:31:12.47#ibcon#about to read 6, iclass 10, count 2 2006.203.07:31:12.47#ibcon#read 6, iclass 10, count 2 2006.203.07:31:12.47#ibcon#end of sib2, iclass 10, count 2 2006.203.07:31:12.47#ibcon#*after write, iclass 10, count 2 2006.203.07:31:12.47#ibcon#*before return 0, iclass 10, count 2 2006.203.07:31:12.47#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.203.07:31:12.47#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.203.07:31:12.47#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.203.07:31:12.47#ibcon#ireg 7 cls_cnt 0 2006.203.07:31:12.47#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.203.07:31:12.59#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.203.07:31:12.59#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.203.07:31:12.59#ibcon#enter wrdev, iclass 10, count 0 2006.203.07:31:12.59#ibcon#first serial, iclass 10, count 0 2006.203.07:31:12.59#ibcon#enter sib2, iclass 10, count 0 2006.203.07:31:12.59#ibcon#flushed, iclass 10, count 0 2006.203.07:31:12.59#ibcon#about to write, iclass 10, count 0 2006.203.07:31:12.59#ibcon#wrote, iclass 10, count 0 2006.203.07:31:12.59#ibcon#about to read 3, iclass 10, count 0 2006.203.07:31:12.61#ibcon#read 3, iclass 10, count 0 2006.203.07:31:12.61#ibcon#about to read 4, iclass 10, count 0 2006.203.07:31:12.61#ibcon#read 4, iclass 10, count 0 2006.203.07:31:12.61#ibcon#about to read 5, iclass 10, count 0 2006.203.07:31:12.61#ibcon#read 5, iclass 10, count 0 2006.203.07:31:12.61#ibcon#about to read 6, iclass 10, count 0 2006.203.07:31:12.61#ibcon#read 6, iclass 10, count 0 2006.203.07:31:12.61#ibcon#end of sib2, iclass 10, count 0 2006.203.07:31:12.61#ibcon#*mode == 0, iclass 10, count 0 2006.203.07:31:12.61#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.203.07:31:12.61#ibcon#[27=USB\r\n] 2006.203.07:31:12.61#ibcon#*before write, iclass 10, count 0 2006.203.07:31:12.61#ibcon#enter sib2, iclass 10, count 0 2006.203.07:31:12.61#ibcon#flushed, iclass 10, count 0 2006.203.07:31:12.61#ibcon#about to write, iclass 10, count 0 2006.203.07:31:12.61#ibcon#wrote, iclass 10, count 0 2006.203.07:31:12.61#ibcon#about to read 3, iclass 10, count 0 2006.203.07:31:12.64#ibcon#read 3, iclass 10, count 0 2006.203.07:31:12.64#ibcon#about to read 4, iclass 10, count 0 2006.203.07:31:12.64#ibcon#read 4, iclass 10, count 0 2006.203.07:31:12.64#ibcon#about to read 5, iclass 10, count 0 2006.203.07:31:12.64#ibcon#read 5, iclass 10, count 0 2006.203.07:31:12.64#ibcon#about to read 6, iclass 10, count 0 2006.203.07:31:12.64#ibcon#read 6, iclass 10, count 0 2006.203.07:31:12.64#ibcon#end of sib2, iclass 10, count 0 2006.203.07:31:12.64#ibcon#*after write, iclass 10, count 0 2006.203.07:31:12.64#ibcon#*before return 0, iclass 10, count 0 2006.203.07:31:12.64#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.203.07:31:12.64#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.203.07:31:12.64#ibcon#about to clear, iclass 10 cls_cnt 0 2006.203.07:31:12.64#ibcon#cleared, iclass 10 cls_cnt 0 2006.203.07:31:12.65$vc4f8/vblo=6,752.99 2006.203.07:31:12.65#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.203.07:31:12.65#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.203.07:31:12.65#ibcon#ireg 17 cls_cnt 0 2006.203.07:31:12.65#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.203.07:31:12.65#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.203.07:31:12.65#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.203.07:31:12.65#ibcon#enter wrdev, iclass 12, count 0 2006.203.07:31:12.65#ibcon#first serial, iclass 12, count 0 2006.203.07:31:12.65#ibcon#enter sib2, iclass 12, count 0 2006.203.07:31:12.65#ibcon#flushed, iclass 12, count 0 2006.203.07:31:12.65#ibcon#about to write, iclass 12, count 0 2006.203.07:31:12.65#ibcon#wrote, iclass 12, count 0 2006.203.07:31:12.65#ibcon#about to read 3, iclass 12, count 0 2006.203.07:31:12.66#ibcon#read 3, iclass 12, count 0 2006.203.07:31:12.66#ibcon#about to read 4, iclass 12, count 0 2006.203.07:31:12.66#ibcon#read 4, iclass 12, count 0 2006.203.07:31:12.66#ibcon#about to read 5, iclass 12, count 0 2006.203.07:31:12.66#ibcon#read 5, iclass 12, count 0 2006.203.07:31:12.66#ibcon#about to read 6, iclass 12, count 0 2006.203.07:31:12.66#ibcon#read 6, iclass 12, count 0 2006.203.07:31:12.66#ibcon#end of sib2, iclass 12, count 0 2006.203.07:31:12.66#ibcon#*mode == 0, iclass 12, count 0 2006.203.07:31:12.66#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.203.07:31:12.66#ibcon#[28=FRQ=06,752.99\r\n] 2006.203.07:31:12.66#ibcon#*before write, iclass 12, count 0 2006.203.07:31:12.66#ibcon#enter sib2, iclass 12, count 0 2006.203.07:31:12.66#ibcon#flushed, iclass 12, count 0 2006.203.07:31:12.66#ibcon#about to write, iclass 12, count 0 2006.203.07:31:12.66#ibcon#wrote, iclass 12, count 0 2006.203.07:31:12.66#ibcon#about to read 3, iclass 12, count 0 2006.203.07:31:12.70#ibcon#read 3, iclass 12, count 0 2006.203.07:31:12.70#ibcon#about to read 4, iclass 12, count 0 2006.203.07:31:12.70#ibcon#read 4, iclass 12, count 0 2006.203.07:31:12.70#ibcon#about to read 5, iclass 12, count 0 2006.203.07:31:12.70#ibcon#read 5, iclass 12, count 0 2006.203.07:31:12.70#ibcon#about to read 6, iclass 12, count 0 2006.203.07:31:12.70#ibcon#read 6, iclass 12, count 0 2006.203.07:31:12.70#ibcon#end of sib2, iclass 12, count 0 2006.203.07:31:12.70#ibcon#*after write, iclass 12, count 0 2006.203.07:31:12.70#ibcon#*before return 0, iclass 12, count 0 2006.203.07:31:12.70#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.203.07:31:12.70#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.203.07:31:12.70#ibcon#about to clear, iclass 12 cls_cnt 0 2006.203.07:31:12.70#ibcon#cleared, iclass 12 cls_cnt 0 2006.203.07:31:12.71$vc4f8/vb=6,4 2006.203.07:31:12.71#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.203.07:31:12.71#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.203.07:31:12.71#ibcon#ireg 11 cls_cnt 2 2006.203.07:31:12.71#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.203.07:31:12.75#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.203.07:31:12.75#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.203.07:31:12.75#ibcon#enter wrdev, iclass 14, count 2 2006.203.07:31:12.75#ibcon#first serial, iclass 14, count 2 2006.203.07:31:12.75#ibcon#enter sib2, iclass 14, count 2 2006.203.07:31:12.75#ibcon#flushed, iclass 14, count 2 2006.203.07:31:12.75#ibcon#about to write, iclass 14, count 2 2006.203.07:31:12.75#ibcon#wrote, iclass 14, count 2 2006.203.07:31:12.75#ibcon#about to read 3, iclass 14, count 2 2006.203.07:31:12.77#ibcon#read 3, iclass 14, count 2 2006.203.07:31:12.77#ibcon#about to read 4, iclass 14, count 2 2006.203.07:31:12.77#ibcon#read 4, iclass 14, count 2 2006.203.07:31:12.77#ibcon#about to read 5, iclass 14, count 2 2006.203.07:31:12.77#ibcon#read 5, iclass 14, count 2 2006.203.07:31:12.77#ibcon#about to read 6, iclass 14, count 2 2006.203.07:31:12.77#ibcon#read 6, iclass 14, count 2 2006.203.07:31:12.77#ibcon#end of sib2, iclass 14, count 2 2006.203.07:31:12.77#ibcon#*mode == 0, iclass 14, count 2 2006.203.07:31:12.77#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.203.07:31:12.77#ibcon#[27=AT06-04\r\n] 2006.203.07:31:12.77#ibcon#*before write, iclass 14, count 2 2006.203.07:31:12.77#ibcon#enter sib2, iclass 14, count 2 2006.203.07:31:12.77#ibcon#flushed, iclass 14, count 2 2006.203.07:31:12.77#ibcon#about to write, iclass 14, count 2 2006.203.07:31:12.77#ibcon#wrote, iclass 14, count 2 2006.203.07:31:12.77#ibcon#about to read 3, iclass 14, count 2 2006.203.07:31:12.80#ibcon#read 3, iclass 14, count 2 2006.203.07:31:12.80#ibcon#about to read 4, iclass 14, count 2 2006.203.07:31:12.80#ibcon#read 4, iclass 14, count 2 2006.203.07:31:12.80#ibcon#about to read 5, iclass 14, count 2 2006.203.07:31:12.80#ibcon#read 5, iclass 14, count 2 2006.203.07:31:12.80#ibcon#about to read 6, iclass 14, count 2 2006.203.07:31:12.80#ibcon#read 6, iclass 14, count 2 2006.203.07:31:12.80#ibcon#end of sib2, iclass 14, count 2 2006.203.07:31:12.80#ibcon#*after write, iclass 14, count 2 2006.203.07:31:12.80#ibcon#*before return 0, iclass 14, count 2 2006.203.07:31:12.80#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.203.07:31:12.80#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.203.07:31:12.80#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.203.07:31:12.80#ibcon#ireg 7 cls_cnt 0 2006.203.07:31:12.80#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.203.07:31:12.92#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.203.07:31:12.92#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.203.07:31:12.92#ibcon#enter wrdev, iclass 14, count 0 2006.203.07:31:12.92#ibcon#first serial, iclass 14, count 0 2006.203.07:31:12.92#ibcon#enter sib2, iclass 14, count 0 2006.203.07:31:12.92#ibcon#flushed, iclass 14, count 0 2006.203.07:31:12.92#ibcon#about to write, iclass 14, count 0 2006.203.07:31:12.92#ibcon#wrote, iclass 14, count 0 2006.203.07:31:12.92#ibcon#about to read 3, iclass 14, count 0 2006.203.07:31:12.94#ibcon#read 3, iclass 14, count 0 2006.203.07:31:12.94#ibcon#about to read 4, iclass 14, count 0 2006.203.07:31:12.94#ibcon#read 4, iclass 14, count 0 2006.203.07:31:12.94#ibcon#about to read 5, iclass 14, count 0 2006.203.07:31:12.94#ibcon#read 5, iclass 14, count 0 2006.203.07:31:12.94#ibcon#about to read 6, iclass 14, count 0 2006.203.07:31:12.94#ibcon#read 6, iclass 14, count 0 2006.203.07:31:12.94#ibcon#end of sib2, iclass 14, count 0 2006.203.07:31:12.94#ibcon#*mode == 0, iclass 14, count 0 2006.203.07:31:12.94#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.203.07:31:12.94#ibcon#[27=USB\r\n] 2006.203.07:31:12.94#ibcon#*before write, iclass 14, count 0 2006.203.07:31:12.94#ibcon#enter sib2, iclass 14, count 0 2006.203.07:31:12.94#ibcon#flushed, iclass 14, count 0 2006.203.07:31:12.94#ibcon#about to write, iclass 14, count 0 2006.203.07:31:12.94#ibcon#wrote, iclass 14, count 0 2006.203.07:31:12.94#ibcon#about to read 3, iclass 14, count 0 2006.203.07:31:12.97#ibcon#read 3, iclass 14, count 0 2006.203.07:31:12.97#ibcon#about to read 4, iclass 14, count 0 2006.203.07:31:12.97#ibcon#read 4, iclass 14, count 0 2006.203.07:31:12.97#ibcon#about to read 5, iclass 14, count 0 2006.203.07:31:12.97#ibcon#read 5, iclass 14, count 0 2006.203.07:31:12.97#ibcon#about to read 6, iclass 14, count 0 2006.203.07:31:12.97#ibcon#read 6, iclass 14, count 0 2006.203.07:31:12.97#ibcon#end of sib2, iclass 14, count 0 2006.203.07:31:12.97#ibcon#*after write, iclass 14, count 0 2006.203.07:31:12.97#ibcon#*before return 0, iclass 14, count 0 2006.203.07:31:12.97#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.203.07:31:12.97#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.203.07:31:12.97#ibcon#about to clear, iclass 14 cls_cnt 0 2006.203.07:31:12.97#ibcon#cleared, iclass 14 cls_cnt 0 2006.203.07:31:12.98$vc4f8/vabw=wide 2006.203.07:31:12.98#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.203.07:31:12.98#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.203.07:31:12.98#ibcon#ireg 8 cls_cnt 0 2006.203.07:31:12.98#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.203.07:31:12.98#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.203.07:31:12.98#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.203.07:31:12.98#ibcon#enter wrdev, iclass 16, count 0 2006.203.07:31:12.98#ibcon#first serial, iclass 16, count 0 2006.203.07:31:12.98#ibcon#enter sib2, iclass 16, count 0 2006.203.07:31:12.98#ibcon#flushed, iclass 16, count 0 2006.203.07:31:12.98#ibcon#about to write, iclass 16, count 0 2006.203.07:31:12.98#ibcon#wrote, iclass 16, count 0 2006.203.07:31:12.98#ibcon#about to read 3, iclass 16, count 0 2006.203.07:31:12.99#ibcon#read 3, iclass 16, count 0 2006.203.07:31:12.99#ibcon#about to read 4, iclass 16, count 0 2006.203.07:31:12.99#ibcon#read 4, iclass 16, count 0 2006.203.07:31:12.99#ibcon#about to read 5, iclass 16, count 0 2006.203.07:31:12.99#ibcon#read 5, iclass 16, count 0 2006.203.07:31:12.99#ibcon#about to read 6, iclass 16, count 0 2006.203.07:31:12.99#ibcon#read 6, iclass 16, count 0 2006.203.07:31:12.99#ibcon#end of sib2, iclass 16, count 0 2006.203.07:31:12.99#ibcon#*mode == 0, iclass 16, count 0 2006.203.07:31:12.99#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.203.07:31:12.99#ibcon#[25=BW32\r\n] 2006.203.07:31:12.99#ibcon#*before write, iclass 16, count 0 2006.203.07:31:12.99#ibcon#enter sib2, iclass 16, count 0 2006.203.07:31:12.99#ibcon#flushed, iclass 16, count 0 2006.203.07:31:12.99#ibcon#about to write, iclass 16, count 0 2006.203.07:31:12.99#ibcon#wrote, iclass 16, count 0 2006.203.07:31:12.99#ibcon#about to read 3, iclass 16, count 0 2006.203.07:31:13.02#ibcon#read 3, iclass 16, count 0 2006.203.07:31:13.02#ibcon#about to read 4, iclass 16, count 0 2006.203.07:31:13.02#ibcon#read 4, iclass 16, count 0 2006.203.07:31:13.02#ibcon#about to read 5, iclass 16, count 0 2006.203.07:31:13.02#ibcon#read 5, iclass 16, count 0 2006.203.07:31:13.02#ibcon#about to read 6, iclass 16, count 0 2006.203.07:31:13.02#ibcon#read 6, iclass 16, count 0 2006.203.07:31:13.02#ibcon#end of sib2, iclass 16, count 0 2006.203.07:31:13.02#ibcon#*after write, iclass 16, count 0 2006.203.07:31:13.02#ibcon#*before return 0, iclass 16, count 0 2006.203.07:31:13.02#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.203.07:31:13.02#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.203.07:31:13.02#ibcon#about to clear, iclass 16 cls_cnt 0 2006.203.07:31:13.02#ibcon#cleared, iclass 16 cls_cnt 0 2006.203.07:31:13.02$vc4f8/vbbw=wide 2006.203.07:31:13.03#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.203.07:31:13.03#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.203.07:31:13.03#ibcon#ireg 8 cls_cnt 0 2006.203.07:31:13.03#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.203.07:31:13.08#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.203.07:31:13.08#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.203.07:31:13.08#ibcon#enter wrdev, iclass 18, count 0 2006.203.07:31:13.08#ibcon#first serial, iclass 18, count 0 2006.203.07:31:13.08#ibcon#enter sib2, iclass 18, count 0 2006.203.07:31:13.08#ibcon#flushed, iclass 18, count 0 2006.203.07:31:13.08#ibcon#about to write, iclass 18, count 0 2006.203.07:31:13.08#ibcon#wrote, iclass 18, count 0 2006.203.07:31:13.08#ibcon#about to read 3, iclass 18, count 0 2006.203.07:31:13.10#ibcon#read 3, iclass 18, count 0 2006.203.07:31:13.10#ibcon#about to read 4, iclass 18, count 0 2006.203.07:31:13.10#ibcon#read 4, iclass 18, count 0 2006.203.07:31:13.10#ibcon#about to read 5, iclass 18, count 0 2006.203.07:31:13.10#ibcon#read 5, iclass 18, count 0 2006.203.07:31:13.10#ibcon#about to read 6, iclass 18, count 0 2006.203.07:31:13.10#ibcon#read 6, iclass 18, count 0 2006.203.07:31:13.10#ibcon#end of sib2, iclass 18, count 0 2006.203.07:31:13.10#ibcon#*mode == 0, iclass 18, count 0 2006.203.07:31:13.10#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.203.07:31:13.10#ibcon#[27=BW32\r\n] 2006.203.07:31:13.10#ibcon#*before write, iclass 18, count 0 2006.203.07:31:13.10#ibcon#enter sib2, iclass 18, count 0 2006.203.07:31:13.10#ibcon#flushed, iclass 18, count 0 2006.203.07:31:13.10#ibcon#about to write, iclass 18, count 0 2006.203.07:31:13.10#ibcon#wrote, iclass 18, count 0 2006.203.07:31:13.10#ibcon#about to read 3, iclass 18, count 0 2006.203.07:31:13.13#ibcon#read 3, iclass 18, count 0 2006.203.07:31:13.13#ibcon#about to read 4, iclass 18, count 0 2006.203.07:31:13.13#ibcon#read 4, iclass 18, count 0 2006.203.07:31:13.13#ibcon#about to read 5, iclass 18, count 0 2006.203.07:31:13.13#ibcon#read 5, iclass 18, count 0 2006.203.07:31:13.13#ibcon#about to read 6, iclass 18, count 0 2006.203.07:31:13.13#ibcon#read 6, iclass 18, count 0 2006.203.07:31:13.13#ibcon#end of sib2, iclass 18, count 0 2006.203.07:31:13.13#ibcon#*after write, iclass 18, count 0 2006.203.07:31:13.13#ibcon#*before return 0, iclass 18, count 0 2006.203.07:31:13.13#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.203.07:31:13.13#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.203.07:31:13.13#ibcon#about to clear, iclass 18 cls_cnt 0 2006.203.07:31:13.13#ibcon#cleared, iclass 18 cls_cnt 0 2006.203.07:31:13.14$4f8m12a/ifd4f 2006.203.07:31:13.14$ifd4f/lo= 2006.203.07:31:13.14$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.203.07:31:13.14$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.203.07:31:13.14$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.203.07:31:13.14$ifd4f/patch= 2006.203.07:31:13.14$ifd4f/patch=lo1,a1,a2,a3,a4 2006.203.07:31:13.14$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.203.07:31:13.14$ifd4f/patch=lo3,a5,a6,a7,a8 2006.203.07:31:13.14$4f8m12a/"form=m,16.000,1:2 2006.203.07:31:13.14$4f8m12a/"tpicd 2006.203.07:31:13.14$4f8m12a/echo=off 2006.203.07:31:13.14$4f8m12a/xlog=off 2006.203.07:31:13.14:!2006.203.07:33:20 2006.203.07:31:53.14#trakl#Source acquired 2006.203.07:31:53.15#flagr#flagr/antenna,acquired 2006.203.07:33:20.01:preob 2006.203.07:33:21.14/onsource/TRACKING 2006.203.07:33:21.14:!2006.203.07:33:30 2006.203.07:33:30.00:data_valid=on 2006.203.07:33:30.00:midob 2006.203.07:33:30.14/onsource/TRACKING 2006.203.07:33:30.14/wx/24.07,1000.9,98 2006.203.07:33:30.25/cable/+6.4605E-03 2006.203.07:33:31.34/va/01,08,usb,yes,31,33 2006.203.07:33:31.34/va/02,07,usb,yes,32,33 2006.203.07:33:31.34/va/03,08,usb,yes,24,24 2006.203.07:33:31.34/va/04,07,usb,yes,32,35 2006.203.07:33:31.34/va/05,07,usb,yes,34,36 2006.203.07:33:31.34/va/06,06,usb,yes,34,33 2006.203.07:33:31.34/va/07,07,usb,yes,30,29 2006.203.07:33:31.34/va/08,06,usb,yes,36,36 2006.203.07:33:31.57/valo/01,532.99,yes,locked 2006.203.07:33:31.57/valo/02,572.99,yes,locked 2006.203.07:33:31.57/valo/03,672.99,yes,locked 2006.203.07:33:31.57/valo/04,832.99,yes,locked 2006.203.07:33:31.57/valo/05,652.99,yes,locked 2006.203.07:33:31.57/valo/06,772.99,yes,locked 2006.203.07:33:31.57/valo/07,832.99,yes,locked 2006.203.07:33:31.57/valo/08,852.99,yes,locked 2006.203.07:33:32.66/vb/01,04,usb,yes,27,26 2006.203.07:33:32.66/vb/02,04,usb,yes,29,30 2006.203.07:33:32.66/vb/03,04,usb,yes,25,29 2006.203.07:33:32.66/vb/04,04,usb,yes,26,26 2006.203.07:33:32.66/vb/05,03,usb,yes,31,35 2006.203.07:33:32.66/vb/06,04,usb,yes,25,28 2006.203.07:33:32.66/vb/07,04,usb,yes,27,27 2006.203.07:33:32.66/vb/08,04,usb,yes,25,28 2006.203.07:33:32.89/vblo/01,632.99,yes,locked 2006.203.07:33:32.89/vblo/02,640.99,yes,locked 2006.203.07:33:32.89/vblo/03,656.99,yes,locked 2006.203.07:33:32.89/vblo/04,712.99,yes,locked 2006.203.07:33:32.89/vblo/05,744.99,yes,locked 2006.203.07:33:32.89/vblo/06,752.99,yes,locked 2006.203.07:33:32.89/vblo/07,734.99,yes,locked 2006.203.07:33:32.89/vblo/08,744.99,yes,locked 2006.203.07:33:33.04/vabw/8 2006.203.07:33:33.19/vbbw/8 2006.203.07:33:33.28/xfe/off,on,16.5 2006.203.07:33:33.67/ifatt/23,28,28,28 2006.203.07:33:34.07/fmout-gps/S +4.56E-07 2006.203.07:33:34.12:!2006.203.07:34:30 2006.203.07:34:30.01:data_valid=off 2006.203.07:34:30.01:postob 2006.203.07:34:30.21/cable/+6.4605E-03 2006.203.07:34:30.21/wx/24.05,1001.0,98 2006.203.07:34:31.07/fmout-gps/S +4.55E-07 2006.203.07:34:31.07:scan_name=203-0735,k06203,60 2006.203.07:34:31.07:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.203.07:34:31.14#flagr#flagr/antenna,new-source 2006.203.07:34:32.14:checkk5 2006.203.07:34:32.57/chk_autoobs//k5ts1/ autoobs is running! 2006.203.07:34:32.99/chk_autoobs//k5ts2/ autoobs is running! 2006.203.07:34:33.42/chk_autoobs//k5ts3/ autoobs is running! 2006.203.07:34:33.86/chk_autoobs//k5ts4/ autoobs is running! 2006.203.07:34:34.28/chk_obsdata//k5ts1/T2030733??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.07:34:34.71/chk_obsdata//k5ts2/T2030733??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.07:34:35.13/chk_obsdata//k5ts3/T2030733??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.07:34:35.61/chk_obsdata//k5ts4/T2030733??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.07:34:36.57/k5log//k5ts1_log_newline 2006.203.07:34:37.42/k5log//k5ts2_log_newline 2006.203.07:34:38.15/k5log//k5ts3_log_newline 2006.203.07:34:38.91/k5log//k5ts4_log_newline 2006.203.07:34:38.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.203.07:34:38.93:4f8m12a=1 2006.203.07:34:38.93$4f8m12a/echo=on 2006.203.07:34:38.93$4f8m12a/pcalon 2006.203.07:34:38.93$pcalon/"no phase cal control is implemented here 2006.203.07:34:38.93$4f8m12a/"tpicd=stop 2006.203.07:34:38.93$4f8m12a/vc4f8 2006.203.07:34:38.93$vc4f8/valo=1,532.99 2006.203.07:34:38.94#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.203.07:34:38.94#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.203.07:34:38.94#ibcon#ireg 17 cls_cnt 0 2006.203.07:34:38.94#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.203.07:34:38.94#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.203.07:34:38.94#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.203.07:34:38.94#ibcon#enter wrdev, iclass 33, count 0 2006.203.07:34:38.94#ibcon#first serial, iclass 33, count 0 2006.203.07:34:38.94#ibcon#enter sib2, iclass 33, count 0 2006.203.07:34:38.94#ibcon#flushed, iclass 33, count 0 2006.203.07:34:38.94#ibcon#about to write, iclass 33, count 0 2006.203.07:34:38.94#ibcon#wrote, iclass 33, count 0 2006.203.07:34:38.94#ibcon#about to read 3, iclass 33, count 0 2006.203.07:34:38.98#ibcon#read 3, iclass 33, count 0 2006.203.07:34:38.98#ibcon#about to read 4, iclass 33, count 0 2006.203.07:34:38.98#ibcon#read 4, iclass 33, count 0 2006.203.07:34:38.98#ibcon#about to read 5, iclass 33, count 0 2006.203.07:34:38.98#ibcon#read 5, iclass 33, count 0 2006.203.07:34:38.98#ibcon#about to read 6, iclass 33, count 0 2006.203.07:34:38.98#ibcon#read 6, iclass 33, count 0 2006.203.07:34:38.98#ibcon#end of sib2, iclass 33, count 0 2006.203.07:34:38.98#ibcon#*mode == 0, iclass 33, count 0 2006.203.07:34:38.98#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.203.07:34:38.98#ibcon#[26=FRQ=01,532.99\r\n] 2006.203.07:34:38.98#ibcon#*before write, iclass 33, count 0 2006.203.07:34:38.98#ibcon#enter sib2, iclass 33, count 0 2006.203.07:34:38.98#ibcon#flushed, iclass 33, count 0 2006.203.07:34:38.98#ibcon#about to write, iclass 33, count 0 2006.203.07:34:38.98#ibcon#wrote, iclass 33, count 0 2006.203.07:34:38.98#ibcon#about to read 3, iclass 33, count 0 2006.203.07:34:39.02#ibcon#read 3, iclass 33, count 0 2006.203.07:34:39.02#ibcon#about to read 4, iclass 33, count 0 2006.203.07:34:39.02#ibcon#read 4, iclass 33, count 0 2006.203.07:34:39.02#ibcon#about to read 5, iclass 33, count 0 2006.203.07:34:39.02#ibcon#read 5, iclass 33, count 0 2006.203.07:34:39.02#ibcon#about to read 6, iclass 33, count 0 2006.203.07:34:39.02#ibcon#read 6, iclass 33, count 0 2006.203.07:34:39.02#ibcon#end of sib2, iclass 33, count 0 2006.203.07:34:39.02#ibcon#*after write, iclass 33, count 0 2006.203.07:34:39.02#ibcon#*before return 0, iclass 33, count 0 2006.203.07:34:39.02#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.203.07:34:39.02#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.203.07:34:39.02#ibcon#about to clear, iclass 33 cls_cnt 0 2006.203.07:34:39.02#ibcon#cleared, iclass 33 cls_cnt 0 2006.203.07:34:39.02$vc4f8/va=1,8 2006.203.07:34:39.02#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.203.07:34:39.02#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.203.07:34:39.02#ibcon#ireg 11 cls_cnt 2 2006.203.07:34:39.02#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.203.07:34:39.02#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.203.07:34:39.02#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.203.07:34:39.02#ibcon#enter wrdev, iclass 35, count 2 2006.203.07:34:39.02#ibcon#first serial, iclass 35, count 2 2006.203.07:34:39.02#ibcon#enter sib2, iclass 35, count 2 2006.203.07:34:39.02#ibcon#flushed, iclass 35, count 2 2006.203.07:34:39.02#ibcon#about to write, iclass 35, count 2 2006.203.07:34:39.02#ibcon#wrote, iclass 35, count 2 2006.203.07:34:39.02#ibcon#about to read 3, iclass 35, count 2 2006.203.07:34:39.04#ibcon#read 3, iclass 35, count 2 2006.203.07:34:39.04#ibcon#about to read 4, iclass 35, count 2 2006.203.07:34:39.04#ibcon#read 4, iclass 35, count 2 2006.203.07:34:39.04#ibcon#about to read 5, iclass 35, count 2 2006.203.07:34:39.04#ibcon#read 5, iclass 35, count 2 2006.203.07:34:39.04#ibcon#about to read 6, iclass 35, count 2 2006.203.07:34:39.04#ibcon#read 6, iclass 35, count 2 2006.203.07:34:39.04#ibcon#end of sib2, iclass 35, count 2 2006.203.07:34:39.04#ibcon#*mode == 0, iclass 35, count 2 2006.203.07:34:39.04#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.203.07:34:39.04#ibcon#[25=AT01-08\r\n] 2006.203.07:34:39.04#ibcon#*before write, iclass 35, count 2 2006.203.07:34:39.04#ibcon#enter sib2, iclass 35, count 2 2006.203.07:34:39.04#ibcon#flushed, iclass 35, count 2 2006.203.07:34:39.04#ibcon#about to write, iclass 35, count 2 2006.203.07:34:39.04#ibcon#wrote, iclass 35, count 2 2006.203.07:34:39.04#ibcon#about to read 3, iclass 35, count 2 2006.203.07:34:39.08#ibcon#read 3, iclass 35, count 2 2006.203.07:34:39.08#ibcon#about to read 4, iclass 35, count 2 2006.203.07:34:39.08#ibcon#read 4, iclass 35, count 2 2006.203.07:34:39.08#ibcon#about to read 5, iclass 35, count 2 2006.203.07:34:39.08#ibcon#read 5, iclass 35, count 2 2006.203.07:34:39.08#ibcon#about to read 6, iclass 35, count 2 2006.203.07:34:39.08#ibcon#read 6, iclass 35, count 2 2006.203.07:34:39.08#ibcon#end of sib2, iclass 35, count 2 2006.203.07:34:39.08#ibcon#*after write, iclass 35, count 2 2006.203.07:34:39.08#ibcon#*before return 0, iclass 35, count 2 2006.203.07:34:39.08#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.203.07:34:39.08#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.203.07:34:39.08#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.203.07:34:39.08#ibcon#ireg 7 cls_cnt 0 2006.203.07:34:39.08#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.203.07:34:39.20#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.203.07:34:39.20#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.203.07:34:39.20#ibcon#enter wrdev, iclass 35, count 0 2006.203.07:34:39.20#ibcon#first serial, iclass 35, count 0 2006.203.07:34:39.20#ibcon#enter sib2, iclass 35, count 0 2006.203.07:34:39.20#ibcon#flushed, iclass 35, count 0 2006.203.07:34:39.20#ibcon#about to write, iclass 35, count 0 2006.203.07:34:39.20#ibcon#wrote, iclass 35, count 0 2006.203.07:34:39.20#ibcon#about to read 3, iclass 35, count 0 2006.203.07:34:39.21#ibcon#read 3, iclass 35, count 0 2006.203.07:34:39.21#ibcon#about to read 4, iclass 35, count 0 2006.203.07:34:39.21#ibcon#read 4, iclass 35, count 0 2006.203.07:34:39.21#ibcon#about to read 5, iclass 35, count 0 2006.203.07:34:39.21#ibcon#read 5, iclass 35, count 0 2006.203.07:34:39.21#ibcon#about to read 6, iclass 35, count 0 2006.203.07:34:39.21#ibcon#read 6, iclass 35, count 0 2006.203.07:34:39.21#ibcon#end of sib2, iclass 35, count 0 2006.203.07:34:39.21#ibcon#*mode == 0, iclass 35, count 0 2006.203.07:34:39.21#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.203.07:34:39.21#ibcon#[25=USB\r\n] 2006.203.07:34:39.21#ibcon#*before write, iclass 35, count 0 2006.203.07:34:39.21#ibcon#enter sib2, iclass 35, count 0 2006.203.07:34:39.21#ibcon#flushed, iclass 35, count 0 2006.203.07:34:39.21#ibcon#about to write, iclass 35, count 0 2006.203.07:34:39.21#ibcon#wrote, iclass 35, count 0 2006.203.07:34:39.21#ibcon#about to read 3, iclass 35, count 0 2006.203.07:34:39.24#ibcon#read 3, iclass 35, count 0 2006.203.07:34:39.24#ibcon#about to read 4, iclass 35, count 0 2006.203.07:34:39.24#ibcon#read 4, iclass 35, count 0 2006.203.07:34:39.24#ibcon#about to read 5, iclass 35, count 0 2006.203.07:34:39.24#ibcon#read 5, iclass 35, count 0 2006.203.07:34:39.24#ibcon#about to read 6, iclass 35, count 0 2006.203.07:34:39.24#ibcon#read 6, iclass 35, count 0 2006.203.07:34:39.24#ibcon#end of sib2, iclass 35, count 0 2006.203.07:34:39.24#ibcon#*after write, iclass 35, count 0 2006.203.07:34:39.24#ibcon#*before return 0, iclass 35, count 0 2006.203.07:34:39.24#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.203.07:34:39.24#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.203.07:34:39.24#ibcon#about to clear, iclass 35 cls_cnt 0 2006.203.07:34:39.24#ibcon#cleared, iclass 35 cls_cnt 0 2006.203.07:34:39.24$vc4f8/valo=2,572.99 2006.203.07:34:39.24#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.203.07:34:39.24#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.203.07:34:39.24#ibcon#ireg 17 cls_cnt 0 2006.203.07:34:39.24#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.203.07:34:39.24#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.203.07:34:39.24#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.203.07:34:39.24#ibcon#enter wrdev, iclass 37, count 0 2006.203.07:34:39.24#ibcon#first serial, iclass 37, count 0 2006.203.07:34:39.24#ibcon#enter sib2, iclass 37, count 0 2006.203.07:34:39.24#ibcon#flushed, iclass 37, count 0 2006.203.07:34:39.24#ibcon#about to write, iclass 37, count 0 2006.203.07:34:39.24#ibcon#wrote, iclass 37, count 0 2006.203.07:34:39.24#ibcon#about to read 3, iclass 37, count 0 2006.203.07:34:39.27#ibcon#read 3, iclass 37, count 0 2006.203.07:34:39.27#ibcon#about to read 4, iclass 37, count 0 2006.203.07:34:39.27#ibcon#read 4, iclass 37, count 0 2006.203.07:34:39.27#ibcon#about to read 5, iclass 37, count 0 2006.203.07:34:39.27#ibcon#read 5, iclass 37, count 0 2006.203.07:34:39.27#ibcon#about to read 6, iclass 37, count 0 2006.203.07:34:39.27#ibcon#read 6, iclass 37, count 0 2006.203.07:34:39.27#ibcon#end of sib2, iclass 37, count 0 2006.203.07:34:39.27#ibcon#*mode == 0, iclass 37, count 0 2006.203.07:34:39.27#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.203.07:34:39.27#ibcon#[26=FRQ=02,572.99\r\n] 2006.203.07:34:39.27#ibcon#*before write, iclass 37, count 0 2006.203.07:34:39.27#ibcon#enter sib2, iclass 37, count 0 2006.203.07:34:39.27#ibcon#flushed, iclass 37, count 0 2006.203.07:34:39.27#ibcon#about to write, iclass 37, count 0 2006.203.07:34:39.27#ibcon#wrote, iclass 37, count 0 2006.203.07:34:39.27#ibcon#about to read 3, iclass 37, count 0 2006.203.07:34:39.31#ibcon#read 3, iclass 37, count 0 2006.203.07:34:39.31#ibcon#about to read 4, iclass 37, count 0 2006.203.07:34:39.31#ibcon#read 4, iclass 37, count 0 2006.203.07:34:39.31#ibcon#about to read 5, iclass 37, count 0 2006.203.07:34:39.31#ibcon#read 5, iclass 37, count 0 2006.203.07:34:39.31#ibcon#about to read 6, iclass 37, count 0 2006.203.07:34:39.31#ibcon#read 6, iclass 37, count 0 2006.203.07:34:39.31#ibcon#end of sib2, iclass 37, count 0 2006.203.07:34:39.31#ibcon#*after write, iclass 37, count 0 2006.203.07:34:39.31#ibcon#*before return 0, iclass 37, count 0 2006.203.07:34:39.31#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.203.07:34:39.31#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.203.07:34:39.31#ibcon#about to clear, iclass 37 cls_cnt 0 2006.203.07:34:39.31#ibcon#cleared, iclass 37 cls_cnt 0 2006.203.07:34:39.31$vc4f8/va=2,7 2006.203.07:34:39.31#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.203.07:34:39.31#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.203.07:34:39.31#ibcon#ireg 11 cls_cnt 2 2006.203.07:34:39.31#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.203.07:34:39.37#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.203.07:34:39.37#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.203.07:34:39.37#ibcon#enter wrdev, iclass 39, count 2 2006.203.07:34:39.37#ibcon#first serial, iclass 39, count 2 2006.203.07:34:39.37#ibcon#enter sib2, iclass 39, count 2 2006.203.07:34:39.37#ibcon#flushed, iclass 39, count 2 2006.203.07:34:39.37#ibcon#about to write, iclass 39, count 2 2006.203.07:34:39.37#ibcon#wrote, iclass 39, count 2 2006.203.07:34:39.37#ibcon#about to read 3, iclass 39, count 2 2006.203.07:34:39.38#ibcon#read 3, iclass 39, count 2 2006.203.07:34:39.38#ibcon#about to read 4, iclass 39, count 2 2006.203.07:34:39.38#ibcon#read 4, iclass 39, count 2 2006.203.07:34:39.38#ibcon#about to read 5, iclass 39, count 2 2006.203.07:34:39.38#ibcon#read 5, iclass 39, count 2 2006.203.07:34:39.38#ibcon#about to read 6, iclass 39, count 2 2006.203.07:34:39.38#ibcon#read 6, iclass 39, count 2 2006.203.07:34:39.38#ibcon#end of sib2, iclass 39, count 2 2006.203.07:34:39.38#ibcon#*mode == 0, iclass 39, count 2 2006.203.07:34:39.38#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.203.07:34:39.38#ibcon#[25=AT02-07\r\n] 2006.203.07:34:39.38#ibcon#*before write, iclass 39, count 2 2006.203.07:34:39.38#ibcon#enter sib2, iclass 39, count 2 2006.203.07:34:39.38#ibcon#flushed, iclass 39, count 2 2006.203.07:34:39.38#ibcon#about to write, iclass 39, count 2 2006.203.07:34:39.38#ibcon#wrote, iclass 39, count 2 2006.203.07:34:39.38#ibcon#about to read 3, iclass 39, count 2 2006.203.07:34:39.41#ibcon#read 3, iclass 39, count 2 2006.203.07:34:39.41#ibcon#about to read 4, iclass 39, count 2 2006.203.07:34:39.41#ibcon#read 4, iclass 39, count 2 2006.203.07:34:39.41#ibcon#about to read 5, iclass 39, count 2 2006.203.07:34:39.41#ibcon#read 5, iclass 39, count 2 2006.203.07:34:39.41#ibcon#about to read 6, iclass 39, count 2 2006.203.07:34:39.41#ibcon#read 6, iclass 39, count 2 2006.203.07:34:39.41#ibcon#end of sib2, iclass 39, count 2 2006.203.07:34:39.41#ibcon#*after write, iclass 39, count 2 2006.203.07:34:39.41#ibcon#*before return 0, iclass 39, count 2 2006.203.07:34:39.41#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.203.07:34:39.41#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.203.07:34:39.41#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.203.07:34:39.41#ibcon#ireg 7 cls_cnt 0 2006.203.07:34:39.41#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.203.07:34:39.53#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.203.07:34:39.53#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.203.07:34:39.53#ibcon#enter wrdev, iclass 39, count 0 2006.203.07:34:39.53#ibcon#first serial, iclass 39, count 0 2006.203.07:34:39.53#ibcon#enter sib2, iclass 39, count 0 2006.203.07:34:39.53#ibcon#flushed, iclass 39, count 0 2006.203.07:34:39.53#ibcon#about to write, iclass 39, count 0 2006.203.07:34:39.53#ibcon#wrote, iclass 39, count 0 2006.203.07:34:39.53#ibcon#about to read 3, iclass 39, count 0 2006.203.07:34:39.55#ibcon#read 3, iclass 39, count 0 2006.203.07:34:39.55#ibcon#about to read 4, iclass 39, count 0 2006.203.07:34:39.55#ibcon#read 4, iclass 39, count 0 2006.203.07:34:39.55#ibcon#about to read 5, iclass 39, count 0 2006.203.07:34:39.55#ibcon#read 5, iclass 39, count 0 2006.203.07:34:39.55#ibcon#about to read 6, iclass 39, count 0 2006.203.07:34:39.55#ibcon#read 6, iclass 39, count 0 2006.203.07:34:39.55#ibcon#end of sib2, iclass 39, count 0 2006.203.07:34:39.55#ibcon#*mode == 0, iclass 39, count 0 2006.203.07:34:39.55#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.203.07:34:39.55#ibcon#[25=USB\r\n] 2006.203.07:34:39.55#ibcon#*before write, iclass 39, count 0 2006.203.07:34:39.55#ibcon#enter sib2, iclass 39, count 0 2006.203.07:34:39.55#ibcon#flushed, iclass 39, count 0 2006.203.07:34:39.55#ibcon#about to write, iclass 39, count 0 2006.203.07:34:39.55#ibcon#wrote, iclass 39, count 0 2006.203.07:34:39.55#ibcon#about to read 3, iclass 39, count 0 2006.203.07:34:39.58#ibcon#read 3, iclass 39, count 0 2006.203.07:34:39.58#ibcon#about to read 4, iclass 39, count 0 2006.203.07:34:39.58#ibcon#read 4, iclass 39, count 0 2006.203.07:34:39.58#ibcon#about to read 5, iclass 39, count 0 2006.203.07:34:39.58#ibcon#read 5, iclass 39, count 0 2006.203.07:34:39.58#ibcon#about to read 6, iclass 39, count 0 2006.203.07:34:39.58#ibcon#read 6, iclass 39, count 0 2006.203.07:34:39.58#ibcon#end of sib2, iclass 39, count 0 2006.203.07:34:39.58#ibcon#*after write, iclass 39, count 0 2006.203.07:34:39.58#ibcon#*before return 0, iclass 39, count 0 2006.203.07:34:39.58#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.203.07:34:39.58#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.203.07:34:39.58#ibcon#about to clear, iclass 39 cls_cnt 0 2006.203.07:34:39.58#ibcon#cleared, iclass 39 cls_cnt 0 2006.203.07:34:39.58$vc4f8/valo=3,672.99 2006.203.07:34:39.58#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.203.07:34:39.58#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.203.07:34:39.58#ibcon#ireg 17 cls_cnt 0 2006.203.07:34:39.58#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.203.07:34:39.58#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.203.07:34:39.58#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.203.07:34:39.58#ibcon#enter wrdev, iclass 3, count 0 2006.203.07:34:39.58#ibcon#first serial, iclass 3, count 0 2006.203.07:34:39.58#ibcon#enter sib2, iclass 3, count 0 2006.203.07:34:39.58#ibcon#flushed, iclass 3, count 0 2006.203.07:34:39.58#ibcon#about to write, iclass 3, count 0 2006.203.07:34:39.58#ibcon#wrote, iclass 3, count 0 2006.203.07:34:39.58#ibcon#about to read 3, iclass 3, count 0 2006.203.07:34:39.61#ibcon#read 3, iclass 3, count 0 2006.203.07:34:39.61#ibcon#about to read 4, iclass 3, count 0 2006.203.07:34:39.61#ibcon#read 4, iclass 3, count 0 2006.203.07:34:39.61#ibcon#about to read 5, iclass 3, count 0 2006.203.07:34:39.61#ibcon#read 5, iclass 3, count 0 2006.203.07:34:39.61#ibcon#about to read 6, iclass 3, count 0 2006.203.07:34:39.61#ibcon#read 6, iclass 3, count 0 2006.203.07:34:39.61#ibcon#end of sib2, iclass 3, count 0 2006.203.07:34:39.61#ibcon#*mode == 0, iclass 3, count 0 2006.203.07:34:39.61#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.203.07:34:39.61#ibcon#[26=FRQ=03,672.99\r\n] 2006.203.07:34:39.61#ibcon#*before write, iclass 3, count 0 2006.203.07:34:39.61#ibcon#enter sib2, iclass 3, count 0 2006.203.07:34:39.61#ibcon#flushed, iclass 3, count 0 2006.203.07:34:39.61#ibcon#about to write, iclass 3, count 0 2006.203.07:34:39.61#ibcon#wrote, iclass 3, count 0 2006.203.07:34:39.61#ibcon#about to read 3, iclass 3, count 0 2006.203.07:34:39.65#ibcon#read 3, iclass 3, count 0 2006.203.07:34:39.65#ibcon#about to read 4, iclass 3, count 0 2006.203.07:34:39.65#ibcon#read 4, iclass 3, count 0 2006.203.07:34:39.65#ibcon#about to read 5, iclass 3, count 0 2006.203.07:34:39.65#ibcon#read 5, iclass 3, count 0 2006.203.07:34:39.65#ibcon#about to read 6, iclass 3, count 0 2006.203.07:34:39.65#ibcon#read 6, iclass 3, count 0 2006.203.07:34:39.65#ibcon#end of sib2, iclass 3, count 0 2006.203.07:34:39.65#ibcon#*after write, iclass 3, count 0 2006.203.07:34:39.65#ibcon#*before return 0, iclass 3, count 0 2006.203.07:34:39.65#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.203.07:34:39.65#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.203.07:34:39.65#ibcon#about to clear, iclass 3 cls_cnt 0 2006.203.07:34:39.65#ibcon#cleared, iclass 3 cls_cnt 0 2006.203.07:34:39.65$vc4f8/va=3,8 2006.203.07:34:39.65#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.203.07:34:39.65#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.203.07:34:39.65#ibcon#ireg 11 cls_cnt 2 2006.203.07:34:39.65#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.203.07:34:39.71#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.203.07:34:39.71#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.203.07:34:39.71#ibcon#enter wrdev, iclass 5, count 2 2006.203.07:34:39.71#ibcon#first serial, iclass 5, count 2 2006.203.07:34:39.71#ibcon#enter sib2, iclass 5, count 2 2006.203.07:34:39.71#ibcon#flushed, iclass 5, count 2 2006.203.07:34:39.71#ibcon#about to write, iclass 5, count 2 2006.203.07:34:39.71#ibcon#wrote, iclass 5, count 2 2006.203.07:34:39.71#ibcon#about to read 3, iclass 5, count 2 2006.203.07:34:39.72#ibcon#read 3, iclass 5, count 2 2006.203.07:34:39.72#ibcon#about to read 4, iclass 5, count 2 2006.203.07:34:39.72#ibcon#read 4, iclass 5, count 2 2006.203.07:34:39.72#ibcon#about to read 5, iclass 5, count 2 2006.203.07:34:39.72#ibcon#read 5, iclass 5, count 2 2006.203.07:34:39.72#ibcon#about to read 6, iclass 5, count 2 2006.203.07:34:39.72#ibcon#read 6, iclass 5, count 2 2006.203.07:34:39.72#ibcon#end of sib2, iclass 5, count 2 2006.203.07:34:39.72#ibcon#*mode == 0, iclass 5, count 2 2006.203.07:34:39.72#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.203.07:34:39.72#ibcon#[25=AT03-08\r\n] 2006.203.07:34:39.72#ibcon#*before write, iclass 5, count 2 2006.203.07:34:39.72#ibcon#enter sib2, iclass 5, count 2 2006.203.07:34:39.72#ibcon#flushed, iclass 5, count 2 2006.203.07:34:39.72#ibcon#about to write, iclass 5, count 2 2006.203.07:34:39.72#ibcon#wrote, iclass 5, count 2 2006.203.07:34:39.72#ibcon#about to read 3, iclass 5, count 2 2006.203.07:34:39.75#ibcon#read 3, iclass 5, count 2 2006.203.07:34:39.75#ibcon#about to read 4, iclass 5, count 2 2006.203.07:34:39.75#ibcon#read 4, iclass 5, count 2 2006.203.07:34:39.75#ibcon#about to read 5, iclass 5, count 2 2006.203.07:34:39.75#ibcon#read 5, iclass 5, count 2 2006.203.07:34:39.75#ibcon#about to read 6, iclass 5, count 2 2006.203.07:34:39.75#ibcon#read 6, iclass 5, count 2 2006.203.07:34:39.75#ibcon#end of sib2, iclass 5, count 2 2006.203.07:34:39.75#ibcon#*after write, iclass 5, count 2 2006.203.07:34:39.75#ibcon#*before return 0, iclass 5, count 2 2006.203.07:34:39.75#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.203.07:34:39.75#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.203.07:34:39.75#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.203.07:34:39.75#ibcon#ireg 7 cls_cnt 0 2006.203.07:34:39.75#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.203.07:34:39.87#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.203.07:34:39.87#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.203.07:34:39.87#ibcon#enter wrdev, iclass 5, count 0 2006.203.07:34:39.87#ibcon#first serial, iclass 5, count 0 2006.203.07:34:39.87#ibcon#enter sib2, iclass 5, count 0 2006.203.07:34:39.87#ibcon#flushed, iclass 5, count 0 2006.203.07:34:39.87#ibcon#about to write, iclass 5, count 0 2006.203.07:34:39.87#ibcon#wrote, iclass 5, count 0 2006.203.07:34:39.87#ibcon#about to read 3, iclass 5, count 0 2006.203.07:34:39.89#ibcon#read 3, iclass 5, count 0 2006.203.07:34:39.89#ibcon#about to read 4, iclass 5, count 0 2006.203.07:34:39.89#ibcon#read 4, iclass 5, count 0 2006.203.07:34:39.89#ibcon#about to read 5, iclass 5, count 0 2006.203.07:34:39.89#ibcon#read 5, iclass 5, count 0 2006.203.07:34:39.89#ibcon#about to read 6, iclass 5, count 0 2006.203.07:34:39.89#ibcon#read 6, iclass 5, count 0 2006.203.07:34:39.89#ibcon#end of sib2, iclass 5, count 0 2006.203.07:34:39.89#ibcon#*mode == 0, iclass 5, count 0 2006.203.07:34:39.89#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.203.07:34:39.89#ibcon#[25=USB\r\n] 2006.203.07:34:39.89#ibcon#*before write, iclass 5, count 0 2006.203.07:34:39.89#ibcon#enter sib2, iclass 5, count 0 2006.203.07:34:39.89#ibcon#flushed, iclass 5, count 0 2006.203.07:34:39.89#ibcon#about to write, iclass 5, count 0 2006.203.07:34:39.89#ibcon#wrote, iclass 5, count 0 2006.203.07:34:39.89#ibcon#about to read 3, iclass 5, count 0 2006.203.07:34:39.92#ibcon#read 3, iclass 5, count 0 2006.203.07:34:39.92#ibcon#about to read 4, iclass 5, count 0 2006.203.07:34:39.92#ibcon#read 4, iclass 5, count 0 2006.203.07:34:39.92#ibcon#about to read 5, iclass 5, count 0 2006.203.07:34:39.92#ibcon#read 5, iclass 5, count 0 2006.203.07:34:39.92#ibcon#about to read 6, iclass 5, count 0 2006.203.07:34:39.92#ibcon#read 6, iclass 5, count 0 2006.203.07:34:39.92#ibcon#end of sib2, iclass 5, count 0 2006.203.07:34:39.92#ibcon#*after write, iclass 5, count 0 2006.203.07:34:39.92#ibcon#*before return 0, iclass 5, count 0 2006.203.07:34:39.92#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.203.07:34:39.92#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.203.07:34:39.92#ibcon#about to clear, iclass 5 cls_cnt 0 2006.203.07:34:39.92#ibcon#cleared, iclass 5 cls_cnt 0 2006.203.07:34:39.92$vc4f8/valo=4,832.99 2006.203.07:34:39.92#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.203.07:34:39.92#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.203.07:34:39.92#ibcon#ireg 17 cls_cnt 0 2006.203.07:34:39.92#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.203.07:34:39.92#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.203.07:34:39.92#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.203.07:34:39.92#ibcon#enter wrdev, iclass 7, count 0 2006.203.07:34:39.92#ibcon#first serial, iclass 7, count 0 2006.203.07:34:39.92#ibcon#enter sib2, iclass 7, count 0 2006.203.07:34:39.92#ibcon#flushed, iclass 7, count 0 2006.203.07:34:39.92#ibcon#about to write, iclass 7, count 0 2006.203.07:34:39.92#ibcon#wrote, iclass 7, count 0 2006.203.07:34:39.92#ibcon#about to read 3, iclass 7, count 0 2006.203.07:34:39.95#ibcon#read 3, iclass 7, count 0 2006.203.07:34:39.95#ibcon#about to read 4, iclass 7, count 0 2006.203.07:34:39.95#ibcon#read 4, iclass 7, count 0 2006.203.07:34:39.95#ibcon#about to read 5, iclass 7, count 0 2006.203.07:34:39.95#ibcon#read 5, iclass 7, count 0 2006.203.07:34:39.95#ibcon#about to read 6, iclass 7, count 0 2006.203.07:34:39.95#ibcon#read 6, iclass 7, count 0 2006.203.07:34:39.95#ibcon#end of sib2, iclass 7, count 0 2006.203.07:34:39.95#ibcon#*mode == 0, iclass 7, count 0 2006.203.07:34:39.95#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.203.07:34:39.95#ibcon#[26=FRQ=04,832.99\r\n] 2006.203.07:34:39.95#ibcon#*before write, iclass 7, count 0 2006.203.07:34:39.95#ibcon#enter sib2, iclass 7, count 0 2006.203.07:34:39.95#ibcon#flushed, iclass 7, count 0 2006.203.07:34:39.95#ibcon#about to write, iclass 7, count 0 2006.203.07:34:39.95#ibcon#wrote, iclass 7, count 0 2006.203.07:34:39.95#ibcon#about to read 3, iclass 7, count 0 2006.203.07:34:39.99#ibcon#read 3, iclass 7, count 0 2006.203.07:34:39.99#ibcon#about to read 4, iclass 7, count 0 2006.203.07:34:39.99#ibcon#read 4, iclass 7, count 0 2006.203.07:34:39.99#ibcon#about to read 5, iclass 7, count 0 2006.203.07:34:39.99#ibcon#read 5, iclass 7, count 0 2006.203.07:34:39.99#ibcon#about to read 6, iclass 7, count 0 2006.203.07:34:39.99#ibcon#read 6, iclass 7, count 0 2006.203.07:34:39.99#ibcon#end of sib2, iclass 7, count 0 2006.203.07:34:39.99#ibcon#*after write, iclass 7, count 0 2006.203.07:34:39.99#ibcon#*before return 0, iclass 7, count 0 2006.203.07:34:39.99#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.203.07:34:39.99#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.203.07:34:39.99#ibcon#about to clear, iclass 7 cls_cnt 0 2006.203.07:34:39.99#ibcon#cleared, iclass 7 cls_cnt 0 2006.203.07:34:39.99$vc4f8/va=4,7 2006.203.07:34:39.99#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.203.07:34:39.99#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.203.07:34:39.99#ibcon#ireg 11 cls_cnt 2 2006.203.07:34:39.99#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.203.07:34:40.04#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.203.07:34:40.04#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.203.07:34:40.04#ibcon#enter wrdev, iclass 11, count 2 2006.203.07:34:40.04#ibcon#first serial, iclass 11, count 2 2006.203.07:34:40.04#ibcon#enter sib2, iclass 11, count 2 2006.203.07:34:40.04#ibcon#flushed, iclass 11, count 2 2006.203.07:34:40.04#ibcon#about to write, iclass 11, count 2 2006.203.07:34:40.04#ibcon#wrote, iclass 11, count 2 2006.203.07:34:40.04#ibcon#about to read 3, iclass 11, count 2 2006.203.07:34:40.06#ibcon#read 3, iclass 11, count 2 2006.203.07:34:40.06#ibcon#about to read 4, iclass 11, count 2 2006.203.07:34:40.06#ibcon#read 4, iclass 11, count 2 2006.203.07:34:40.06#ibcon#about to read 5, iclass 11, count 2 2006.203.07:34:40.06#ibcon#read 5, iclass 11, count 2 2006.203.07:34:40.06#ibcon#about to read 6, iclass 11, count 2 2006.203.07:34:40.06#ibcon#read 6, iclass 11, count 2 2006.203.07:34:40.06#ibcon#end of sib2, iclass 11, count 2 2006.203.07:34:40.06#ibcon#*mode == 0, iclass 11, count 2 2006.203.07:34:40.06#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.203.07:34:40.06#ibcon#[25=AT04-07\r\n] 2006.203.07:34:40.06#ibcon#*before write, iclass 11, count 2 2006.203.07:34:40.06#ibcon#enter sib2, iclass 11, count 2 2006.203.07:34:40.06#ibcon#flushed, iclass 11, count 2 2006.203.07:34:40.06#ibcon#about to write, iclass 11, count 2 2006.203.07:34:40.06#ibcon#wrote, iclass 11, count 2 2006.203.07:34:40.06#ibcon#about to read 3, iclass 11, count 2 2006.203.07:34:40.09#ibcon#read 3, iclass 11, count 2 2006.203.07:34:40.09#ibcon#about to read 4, iclass 11, count 2 2006.203.07:34:40.09#ibcon#read 4, iclass 11, count 2 2006.203.07:34:40.09#ibcon#about to read 5, iclass 11, count 2 2006.203.07:34:40.09#ibcon#read 5, iclass 11, count 2 2006.203.07:34:40.09#ibcon#about to read 6, iclass 11, count 2 2006.203.07:34:40.09#ibcon#read 6, iclass 11, count 2 2006.203.07:34:40.09#ibcon#end of sib2, iclass 11, count 2 2006.203.07:34:40.09#ibcon#*after write, iclass 11, count 2 2006.203.07:34:40.09#ibcon#*before return 0, iclass 11, count 2 2006.203.07:34:40.09#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.203.07:34:40.09#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.203.07:34:40.09#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.203.07:34:40.09#ibcon#ireg 7 cls_cnt 0 2006.203.07:34:40.09#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.203.07:34:40.21#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.203.07:34:40.21#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.203.07:34:40.21#ibcon#enter wrdev, iclass 11, count 0 2006.203.07:34:40.21#ibcon#first serial, iclass 11, count 0 2006.203.07:34:40.21#ibcon#enter sib2, iclass 11, count 0 2006.203.07:34:40.21#ibcon#flushed, iclass 11, count 0 2006.203.07:34:40.21#ibcon#about to write, iclass 11, count 0 2006.203.07:34:40.21#ibcon#wrote, iclass 11, count 0 2006.203.07:34:40.21#ibcon#about to read 3, iclass 11, count 0 2006.203.07:34:40.23#ibcon#read 3, iclass 11, count 0 2006.203.07:34:40.23#ibcon#about to read 4, iclass 11, count 0 2006.203.07:34:40.23#ibcon#read 4, iclass 11, count 0 2006.203.07:34:40.23#ibcon#about to read 5, iclass 11, count 0 2006.203.07:34:40.23#ibcon#read 5, iclass 11, count 0 2006.203.07:34:40.23#ibcon#about to read 6, iclass 11, count 0 2006.203.07:34:40.23#ibcon#read 6, iclass 11, count 0 2006.203.07:34:40.23#ibcon#end of sib2, iclass 11, count 0 2006.203.07:34:40.23#ibcon#*mode == 0, iclass 11, count 0 2006.203.07:34:40.23#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.203.07:34:40.23#ibcon#[25=USB\r\n] 2006.203.07:34:40.23#ibcon#*before write, iclass 11, count 0 2006.203.07:34:40.23#ibcon#enter sib2, iclass 11, count 0 2006.203.07:34:40.23#ibcon#flushed, iclass 11, count 0 2006.203.07:34:40.23#ibcon#about to write, iclass 11, count 0 2006.203.07:34:40.23#ibcon#wrote, iclass 11, count 0 2006.203.07:34:40.23#ibcon#about to read 3, iclass 11, count 0 2006.203.07:34:40.26#ibcon#read 3, iclass 11, count 0 2006.203.07:34:40.26#ibcon#about to read 4, iclass 11, count 0 2006.203.07:34:40.26#ibcon#read 4, iclass 11, count 0 2006.203.07:34:40.26#ibcon#about to read 5, iclass 11, count 0 2006.203.07:34:40.26#ibcon#read 5, iclass 11, count 0 2006.203.07:34:40.26#ibcon#about to read 6, iclass 11, count 0 2006.203.07:34:40.26#ibcon#read 6, iclass 11, count 0 2006.203.07:34:40.26#ibcon#end of sib2, iclass 11, count 0 2006.203.07:34:40.26#ibcon#*after write, iclass 11, count 0 2006.203.07:34:40.26#ibcon#*before return 0, iclass 11, count 0 2006.203.07:34:40.26#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.203.07:34:40.26#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.203.07:34:40.26#ibcon#about to clear, iclass 11 cls_cnt 0 2006.203.07:34:40.26#ibcon#cleared, iclass 11 cls_cnt 0 2006.203.07:34:40.26$vc4f8/valo=5,652.99 2006.203.07:34:40.26#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.203.07:34:40.26#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.203.07:34:40.26#ibcon#ireg 17 cls_cnt 0 2006.203.07:34:40.26#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.203.07:34:40.26#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.203.07:34:40.26#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.203.07:34:40.26#ibcon#enter wrdev, iclass 13, count 0 2006.203.07:34:40.26#ibcon#first serial, iclass 13, count 0 2006.203.07:34:40.26#ibcon#enter sib2, iclass 13, count 0 2006.203.07:34:40.26#ibcon#flushed, iclass 13, count 0 2006.203.07:34:40.26#ibcon#about to write, iclass 13, count 0 2006.203.07:34:40.26#ibcon#wrote, iclass 13, count 0 2006.203.07:34:40.26#ibcon#about to read 3, iclass 13, count 0 2006.203.07:34:40.28#ibcon#read 3, iclass 13, count 0 2006.203.07:34:40.28#ibcon#about to read 4, iclass 13, count 0 2006.203.07:34:40.28#ibcon#read 4, iclass 13, count 0 2006.203.07:34:40.28#ibcon#about to read 5, iclass 13, count 0 2006.203.07:34:40.28#ibcon#read 5, iclass 13, count 0 2006.203.07:34:40.28#ibcon#about to read 6, iclass 13, count 0 2006.203.07:34:40.28#ibcon#read 6, iclass 13, count 0 2006.203.07:34:40.28#ibcon#end of sib2, iclass 13, count 0 2006.203.07:34:40.28#ibcon#*mode == 0, iclass 13, count 0 2006.203.07:34:40.28#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.203.07:34:40.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.203.07:34:40.28#ibcon#*before write, iclass 13, count 0 2006.203.07:34:40.28#ibcon#enter sib2, iclass 13, count 0 2006.203.07:34:40.28#ibcon#flushed, iclass 13, count 0 2006.203.07:34:40.28#ibcon#about to write, iclass 13, count 0 2006.203.07:34:40.28#ibcon#wrote, iclass 13, count 0 2006.203.07:34:40.28#ibcon#about to read 3, iclass 13, count 0 2006.203.07:34:40.33#ibcon#read 3, iclass 13, count 0 2006.203.07:34:40.33#ibcon#about to read 4, iclass 13, count 0 2006.203.07:34:40.33#ibcon#read 4, iclass 13, count 0 2006.203.07:34:40.33#ibcon#about to read 5, iclass 13, count 0 2006.203.07:34:40.33#ibcon#read 5, iclass 13, count 0 2006.203.07:34:40.33#ibcon#about to read 6, iclass 13, count 0 2006.203.07:34:40.33#ibcon#read 6, iclass 13, count 0 2006.203.07:34:40.33#ibcon#end of sib2, iclass 13, count 0 2006.203.07:34:40.33#ibcon#*after write, iclass 13, count 0 2006.203.07:34:40.33#ibcon#*before return 0, iclass 13, count 0 2006.203.07:34:40.33#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.203.07:34:40.33#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.203.07:34:40.33#ibcon#about to clear, iclass 13 cls_cnt 0 2006.203.07:34:40.33#ibcon#cleared, iclass 13 cls_cnt 0 2006.203.07:34:40.33$vc4f8/va=5,7 2006.203.07:34:40.33#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.203.07:34:40.33#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.203.07:34:40.33#ibcon#ireg 11 cls_cnt 2 2006.203.07:34:40.33#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.203.07:34:40.37#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.203.07:34:40.37#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.203.07:34:40.37#ibcon#enter wrdev, iclass 15, count 2 2006.203.07:34:40.37#ibcon#first serial, iclass 15, count 2 2006.203.07:34:40.37#ibcon#enter sib2, iclass 15, count 2 2006.203.07:34:40.37#ibcon#flushed, iclass 15, count 2 2006.203.07:34:40.37#ibcon#about to write, iclass 15, count 2 2006.203.07:34:40.37#ibcon#wrote, iclass 15, count 2 2006.203.07:34:40.37#ibcon#about to read 3, iclass 15, count 2 2006.203.07:34:40.39#ibcon#read 3, iclass 15, count 2 2006.203.07:34:40.39#ibcon#about to read 4, iclass 15, count 2 2006.203.07:34:40.39#ibcon#read 4, iclass 15, count 2 2006.203.07:34:40.39#ibcon#about to read 5, iclass 15, count 2 2006.203.07:34:40.39#ibcon#read 5, iclass 15, count 2 2006.203.07:34:40.39#ibcon#about to read 6, iclass 15, count 2 2006.203.07:34:40.39#ibcon#read 6, iclass 15, count 2 2006.203.07:34:40.39#ibcon#end of sib2, iclass 15, count 2 2006.203.07:34:40.39#ibcon#*mode == 0, iclass 15, count 2 2006.203.07:34:40.39#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.203.07:34:40.39#ibcon#[25=AT05-07\r\n] 2006.203.07:34:40.39#ibcon#*before write, iclass 15, count 2 2006.203.07:34:40.39#ibcon#enter sib2, iclass 15, count 2 2006.203.07:34:40.39#ibcon#flushed, iclass 15, count 2 2006.203.07:34:40.39#ibcon#about to write, iclass 15, count 2 2006.203.07:34:40.39#ibcon#wrote, iclass 15, count 2 2006.203.07:34:40.39#ibcon#about to read 3, iclass 15, count 2 2006.203.07:34:40.42#ibcon#read 3, iclass 15, count 2 2006.203.07:34:40.42#ibcon#about to read 4, iclass 15, count 2 2006.203.07:34:40.42#ibcon#read 4, iclass 15, count 2 2006.203.07:34:40.42#ibcon#about to read 5, iclass 15, count 2 2006.203.07:34:40.42#ibcon#read 5, iclass 15, count 2 2006.203.07:34:40.42#ibcon#about to read 6, iclass 15, count 2 2006.203.07:34:40.42#ibcon#read 6, iclass 15, count 2 2006.203.07:34:40.42#ibcon#end of sib2, iclass 15, count 2 2006.203.07:34:40.42#ibcon#*after write, iclass 15, count 2 2006.203.07:34:40.42#ibcon#*before return 0, iclass 15, count 2 2006.203.07:34:40.42#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.203.07:34:40.42#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.203.07:34:40.42#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.203.07:34:40.42#ibcon#ireg 7 cls_cnt 0 2006.203.07:34:40.42#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.203.07:34:40.54#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.203.07:34:40.54#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.203.07:34:40.54#ibcon#enter wrdev, iclass 15, count 0 2006.203.07:34:40.54#ibcon#first serial, iclass 15, count 0 2006.203.07:34:40.54#ibcon#enter sib2, iclass 15, count 0 2006.203.07:34:40.54#ibcon#flushed, iclass 15, count 0 2006.203.07:34:40.54#ibcon#about to write, iclass 15, count 0 2006.203.07:34:40.54#ibcon#wrote, iclass 15, count 0 2006.203.07:34:40.54#ibcon#about to read 3, iclass 15, count 0 2006.203.07:34:40.56#ibcon#read 3, iclass 15, count 0 2006.203.07:34:40.56#ibcon#about to read 4, iclass 15, count 0 2006.203.07:34:40.56#ibcon#read 4, iclass 15, count 0 2006.203.07:34:40.56#ibcon#about to read 5, iclass 15, count 0 2006.203.07:34:40.56#ibcon#read 5, iclass 15, count 0 2006.203.07:34:40.56#ibcon#about to read 6, iclass 15, count 0 2006.203.07:34:40.56#ibcon#read 6, iclass 15, count 0 2006.203.07:34:40.56#ibcon#end of sib2, iclass 15, count 0 2006.203.07:34:40.56#ibcon#*mode == 0, iclass 15, count 0 2006.203.07:34:40.56#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.203.07:34:40.56#ibcon#[25=USB\r\n] 2006.203.07:34:40.56#ibcon#*before write, iclass 15, count 0 2006.203.07:34:40.56#ibcon#enter sib2, iclass 15, count 0 2006.203.07:34:40.56#ibcon#flushed, iclass 15, count 0 2006.203.07:34:40.56#ibcon#about to write, iclass 15, count 0 2006.203.07:34:40.56#ibcon#wrote, iclass 15, count 0 2006.203.07:34:40.56#ibcon#about to read 3, iclass 15, count 0 2006.203.07:34:40.59#ibcon#read 3, iclass 15, count 0 2006.203.07:34:40.59#ibcon#about to read 4, iclass 15, count 0 2006.203.07:34:40.59#ibcon#read 4, iclass 15, count 0 2006.203.07:34:40.59#ibcon#about to read 5, iclass 15, count 0 2006.203.07:34:40.59#ibcon#read 5, iclass 15, count 0 2006.203.07:34:40.59#ibcon#about to read 6, iclass 15, count 0 2006.203.07:34:40.59#ibcon#read 6, iclass 15, count 0 2006.203.07:34:40.59#ibcon#end of sib2, iclass 15, count 0 2006.203.07:34:40.59#ibcon#*after write, iclass 15, count 0 2006.203.07:34:40.59#ibcon#*before return 0, iclass 15, count 0 2006.203.07:34:40.59#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.203.07:34:40.59#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.203.07:34:40.59#ibcon#about to clear, iclass 15 cls_cnt 0 2006.203.07:34:40.59#ibcon#cleared, iclass 15 cls_cnt 0 2006.203.07:34:40.59$vc4f8/valo=6,772.99 2006.203.07:34:40.59#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.203.07:34:40.59#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.203.07:34:40.59#ibcon#ireg 17 cls_cnt 0 2006.203.07:34:40.59#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.203.07:34:40.59#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.203.07:34:40.59#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.203.07:34:40.59#ibcon#enter wrdev, iclass 17, count 0 2006.203.07:34:40.59#ibcon#first serial, iclass 17, count 0 2006.203.07:34:40.59#ibcon#enter sib2, iclass 17, count 0 2006.203.07:34:40.59#ibcon#flushed, iclass 17, count 0 2006.203.07:34:40.59#ibcon#about to write, iclass 17, count 0 2006.203.07:34:40.59#ibcon#wrote, iclass 17, count 0 2006.203.07:34:40.59#ibcon#about to read 3, iclass 17, count 0 2006.203.07:34:40.62#ibcon#read 3, iclass 17, count 0 2006.203.07:34:40.62#ibcon#about to read 4, iclass 17, count 0 2006.203.07:34:40.62#ibcon#read 4, iclass 17, count 0 2006.203.07:34:40.62#ibcon#about to read 5, iclass 17, count 0 2006.203.07:34:40.62#ibcon#read 5, iclass 17, count 0 2006.203.07:34:40.62#ibcon#about to read 6, iclass 17, count 0 2006.203.07:34:40.62#ibcon#read 6, iclass 17, count 0 2006.203.07:34:40.62#ibcon#end of sib2, iclass 17, count 0 2006.203.07:34:40.62#ibcon#*mode == 0, iclass 17, count 0 2006.203.07:34:40.62#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.203.07:34:40.62#ibcon#[26=FRQ=06,772.99\r\n] 2006.203.07:34:40.62#ibcon#*before write, iclass 17, count 0 2006.203.07:34:40.62#ibcon#enter sib2, iclass 17, count 0 2006.203.07:34:40.62#ibcon#flushed, iclass 17, count 0 2006.203.07:34:40.62#ibcon#about to write, iclass 17, count 0 2006.203.07:34:40.62#ibcon#wrote, iclass 17, count 0 2006.203.07:34:40.62#ibcon#about to read 3, iclass 17, count 0 2006.203.07:34:40.66#ibcon#read 3, iclass 17, count 0 2006.203.07:34:40.66#ibcon#about to read 4, iclass 17, count 0 2006.203.07:34:40.66#ibcon#read 4, iclass 17, count 0 2006.203.07:34:40.66#ibcon#about to read 5, iclass 17, count 0 2006.203.07:34:40.66#ibcon#read 5, iclass 17, count 0 2006.203.07:34:40.66#ibcon#about to read 6, iclass 17, count 0 2006.203.07:34:40.66#ibcon#read 6, iclass 17, count 0 2006.203.07:34:40.66#ibcon#end of sib2, iclass 17, count 0 2006.203.07:34:40.66#ibcon#*after write, iclass 17, count 0 2006.203.07:34:40.66#ibcon#*before return 0, iclass 17, count 0 2006.203.07:34:40.66#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.203.07:34:40.66#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.203.07:34:40.66#ibcon#about to clear, iclass 17 cls_cnt 0 2006.203.07:34:40.66#ibcon#cleared, iclass 17 cls_cnt 0 2006.203.07:34:40.66$vc4f8/va=6,6 2006.203.07:34:40.66#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.203.07:34:40.66#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.203.07:34:40.66#ibcon#ireg 11 cls_cnt 2 2006.203.07:34:40.66#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.203.07:34:40.71#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.203.07:34:40.71#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.203.07:34:40.71#ibcon#enter wrdev, iclass 19, count 2 2006.203.07:34:40.71#ibcon#first serial, iclass 19, count 2 2006.203.07:34:40.71#ibcon#enter sib2, iclass 19, count 2 2006.203.07:34:40.71#ibcon#flushed, iclass 19, count 2 2006.203.07:34:40.71#ibcon#about to write, iclass 19, count 2 2006.203.07:34:40.71#ibcon#wrote, iclass 19, count 2 2006.203.07:34:40.71#ibcon#about to read 3, iclass 19, count 2 2006.203.07:34:40.73#ibcon#read 3, iclass 19, count 2 2006.203.07:34:40.73#ibcon#about to read 4, iclass 19, count 2 2006.203.07:34:40.73#ibcon#read 4, iclass 19, count 2 2006.203.07:34:40.73#ibcon#about to read 5, iclass 19, count 2 2006.203.07:34:40.73#ibcon#read 5, iclass 19, count 2 2006.203.07:34:40.73#ibcon#about to read 6, iclass 19, count 2 2006.203.07:34:40.73#ibcon#read 6, iclass 19, count 2 2006.203.07:34:40.73#ibcon#end of sib2, iclass 19, count 2 2006.203.07:34:40.73#ibcon#*mode == 0, iclass 19, count 2 2006.203.07:34:40.73#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.203.07:34:40.73#ibcon#[25=AT06-06\r\n] 2006.203.07:34:40.73#ibcon#*before write, iclass 19, count 2 2006.203.07:34:40.73#ibcon#enter sib2, iclass 19, count 2 2006.203.07:34:40.73#ibcon#flushed, iclass 19, count 2 2006.203.07:34:40.73#ibcon#about to write, iclass 19, count 2 2006.203.07:34:40.73#ibcon#wrote, iclass 19, count 2 2006.203.07:34:40.73#ibcon#about to read 3, iclass 19, count 2 2006.203.07:34:40.76#ibcon#read 3, iclass 19, count 2 2006.203.07:34:40.76#ibcon#about to read 4, iclass 19, count 2 2006.203.07:34:40.76#ibcon#read 4, iclass 19, count 2 2006.203.07:34:40.76#ibcon#about to read 5, iclass 19, count 2 2006.203.07:34:40.76#ibcon#read 5, iclass 19, count 2 2006.203.07:34:40.76#ibcon#about to read 6, iclass 19, count 2 2006.203.07:34:40.76#ibcon#read 6, iclass 19, count 2 2006.203.07:34:40.76#ibcon#end of sib2, iclass 19, count 2 2006.203.07:34:40.76#ibcon#*after write, iclass 19, count 2 2006.203.07:34:40.76#ibcon#*before return 0, iclass 19, count 2 2006.203.07:34:40.76#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.203.07:34:40.76#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.203.07:34:40.76#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.203.07:34:40.76#ibcon#ireg 7 cls_cnt 0 2006.203.07:34:40.76#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.203.07:34:40.88#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.203.07:34:40.88#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.203.07:34:40.88#ibcon#enter wrdev, iclass 19, count 0 2006.203.07:34:40.88#ibcon#first serial, iclass 19, count 0 2006.203.07:34:40.88#ibcon#enter sib2, iclass 19, count 0 2006.203.07:34:40.88#ibcon#flushed, iclass 19, count 0 2006.203.07:34:40.88#ibcon#about to write, iclass 19, count 0 2006.203.07:34:40.88#ibcon#wrote, iclass 19, count 0 2006.203.07:34:40.88#ibcon#about to read 3, iclass 19, count 0 2006.203.07:34:40.90#ibcon#read 3, iclass 19, count 0 2006.203.07:34:40.90#ibcon#about to read 4, iclass 19, count 0 2006.203.07:34:40.90#ibcon#read 4, iclass 19, count 0 2006.203.07:34:40.90#ibcon#about to read 5, iclass 19, count 0 2006.203.07:34:40.90#ibcon#read 5, iclass 19, count 0 2006.203.07:34:40.90#ibcon#about to read 6, iclass 19, count 0 2006.203.07:34:40.90#ibcon#read 6, iclass 19, count 0 2006.203.07:34:40.90#ibcon#end of sib2, iclass 19, count 0 2006.203.07:34:40.90#ibcon#*mode == 0, iclass 19, count 0 2006.203.07:34:40.90#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.203.07:34:40.90#ibcon#[25=USB\r\n] 2006.203.07:34:40.90#ibcon#*before write, iclass 19, count 0 2006.203.07:34:40.90#ibcon#enter sib2, iclass 19, count 0 2006.203.07:34:40.90#ibcon#flushed, iclass 19, count 0 2006.203.07:34:40.90#ibcon#about to write, iclass 19, count 0 2006.203.07:34:40.90#ibcon#wrote, iclass 19, count 0 2006.203.07:34:40.90#ibcon#about to read 3, iclass 19, count 0 2006.203.07:34:40.93#ibcon#read 3, iclass 19, count 0 2006.203.07:34:40.93#ibcon#about to read 4, iclass 19, count 0 2006.203.07:34:40.93#ibcon#read 4, iclass 19, count 0 2006.203.07:34:40.93#ibcon#about to read 5, iclass 19, count 0 2006.203.07:34:40.93#ibcon#read 5, iclass 19, count 0 2006.203.07:34:40.93#ibcon#about to read 6, iclass 19, count 0 2006.203.07:34:40.93#ibcon#read 6, iclass 19, count 0 2006.203.07:34:40.93#ibcon#end of sib2, iclass 19, count 0 2006.203.07:34:40.93#ibcon#*after write, iclass 19, count 0 2006.203.07:34:40.93#ibcon#*before return 0, iclass 19, count 0 2006.203.07:34:40.93#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.203.07:34:40.93#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.203.07:34:40.93#ibcon#about to clear, iclass 19 cls_cnt 0 2006.203.07:34:40.93#ibcon#cleared, iclass 19 cls_cnt 0 2006.203.07:34:40.93$vc4f8/valo=7,832.99 2006.203.07:34:40.93#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.203.07:34:40.93#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.203.07:34:40.93#ibcon#ireg 17 cls_cnt 0 2006.203.07:34:40.93#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.203.07:34:40.93#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.203.07:34:40.93#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.203.07:34:40.93#ibcon#enter wrdev, iclass 21, count 0 2006.203.07:34:40.93#ibcon#first serial, iclass 21, count 0 2006.203.07:34:40.93#ibcon#enter sib2, iclass 21, count 0 2006.203.07:34:40.93#ibcon#flushed, iclass 21, count 0 2006.203.07:34:40.93#ibcon#about to write, iclass 21, count 0 2006.203.07:34:40.93#ibcon#wrote, iclass 21, count 0 2006.203.07:34:40.93#ibcon#about to read 3, iclass 21, count 0 2006.203.07:34:40.95#ibcon#read 3, iclass 21, count 0 2006.203.07:34:40.95#ibcon#about to read 4, iclass 21, count 0 2006.203.07:34:40.95#ibcon#read 4, iclass 21, count 0 2006.203.07:34:40.95#ibcon#about to read 5, iclass 21, count 0 2006.203.07:34:40.95#ibcon#read 5, iclass 21, count 0 2006.203.07:34:40.95#ibcon#about to read 6, iclass 21, count 0 2006.203.07:34:40.95#ibcon#read 6, iclass 21, count 0 2006.203.07:34:40.95#ibcon#end of sib2, iclass 21, count 0 2006.203.07:34:40.95#ibcon#*mode == 0, iclass 21, count 0 2006.203.07:34:40.95#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.203.07:34:40.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.203.07:34:40.95#ibcon#*before write, iclass 21, count 0 2006.203.07:34:40.95#ibcon#enter sib2, iclass 21, count 0 2006.203.07:34:40.95#ibcon#flushed, iclass 21, count 0 2006.203.07:34:40.95#ibcon#about to write, iclass 21, count 0 2006.203.07:34:40.95#ibcon#wrote, iclass 21, count 0 2006.203.07:34:40.95#ibcon#about to read 3, iclass 21, count 0 2006.203.07:34:40.99#ibcon#read 3, iclass 21, count 0 2006.203.07:34:40.99#ibcon#about to read 4, iclass 21, count 0 2006.203.07:34:40.99#ibcon#read 4, iclass 21, count 0 2006.203.07:34:40.99#ibcon#about to read 5, iclass 21, count 0 2006.203.07:34:40.99#ibcon#read 5, iclass 21, count 0 2006.203.07:34:40.99#ibcon#about to read 6, iclass 21, count 0 2006.203.07:34:40.99#ibcon#read 6, iclass 21, count 0 2006.203.07:34:40.99#ibcon#end of sib2, iclass 21, count 0 2006.203.07:34:40.99#ibcon#*after write, iclass 21, count 0 2006.203.07:34:40.99#ibcon#*before return 0, iclass 21, count 0 2006.203.07:34:40.99#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.203.07:34:40.99#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.203.07:34:40.99#ibcon#about to clear, iclass 21 cls_cnt 0 2006.203.07:34:40.99#ibcon#cleared, iclass 21 cls_cnt 0 2006.203.07:34:40.99$vc4f8/va=7,7 2006.203.07:34:40.99#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.203.07:34:40.99#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.203.07:34:40.99#ibcon#ireg 11 cls_cnt 2 2006.203.07:34:40.99#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.203.07:34:41.06#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.203.07:34:41.06#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.203.07:34:41.06#ibcon#enter wrdev, iclass 23, count 2 2006.203.07:34:41.06#ibcon#first serial, iclass 23, count 2 2006.203.07:34:41.06#ibcon#enter sib2, iclass 23, count 2 2006.203.07:34:41.06#ibcon#flushed, iclass 23, count 2 2006.203.07:34:41.06#ibcon#about to write, iclass 23, count 2 2006.203.07:34:41.06#ibcon#wrote, iclass 23, count 2 2006.203.07:34:41.06#ibcon#about to read 3, iclass 23, count 2 2006.203.07:34:41.07#ibcon#read 3, iclass 23, count 2 2006.203.07:34:41.07#ibcon#about to read 4, iclass 23, count 2 2006.203.07:34:41.07#ibcon#read 4, iclass 23, count 2 2006.203.07:34:41.07#ibcon#about to read 5, iclass 23, count 2 2006.203.07:34:41.07#ibcon#read 5, iclass 23, count 2 2006.203.07:34:41.07#ibcon#about to read 6, iclass 23, count 2 2006.203.07:34:41.07#ibcon#read 6, iclass 23, count 2 2006.203.07:34:41.07#ibcon#end of sib2, iclass 23, count 2 2006.203.07:34:41.07#ibcon#*mode == 0, iclass 23, count 2 2006.203.07:34:41.07#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.203.07:34:41.07#ibcon#[25=AT07-07\r\n] 2006.203.07:34:41.07#ibcon#*before write, iclass 23, count 2 2006.203.07:34:41.07#ibcon#enter sib2, iclass 23, count 2 2006.203.07:34:41.07#ibcon#flushed, iclass 23, count 2 2006.203.07:34:41.07#ibcon#about to write, iclass 23, count 2 2006.203.07:34:41.07#ibcon#wrote, iclass 23, count 2 2006.203.07:34:41.07#ibcon#about to read 3, iclass 23, count 2 2006.203.07:34:41.10#ibcon#read 3, iclass 23, count 2 2006.203.07:34:41.10#ibcon#about to read 4, iclass 23, count 2 2006.203.07:34:41.10#ibcon#read 4, iclass 23, count 2 2006.203.07:34:41.10#ibcon#about to read 5, iclass 23, count 2 2006.203.07:34:41.10#ibcon#read 5, iclass 23, count 2 2006.203.07:34:41.10#ibcon#about to read 6, iclass 23, count 2 2006.203.07:34:41.10#ibcon#read 6, iclass 23, count 2 2006.203.07:34:41.10#ibcon#end of sib2, iclass 23, count 2 2006.203.07:34:41.10#ibcon#*after write, iclass 23, count 2 2006.203.07:34:41.10#ibcon#*before return 0, iclass 23, count 2 2006.203.07:34:41.10#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.203.07:34:41.10#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.203.07:34:41.10#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.203.07:34:41.10#ibcon#ireg 7 cls_cnt 0 2006.203.07:34:41.10#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.203.07:34:41.22#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.203.07:34:41.22#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.203.07:34:41.22#ibcon#enter wrdev, iclass 23, count 0 2006.203.07:34:41.22#ibcon#first serial, iclass 23, count 0 2006.203.07:34:41.22#ibcon#enter sib2, iclass 23, count 0 2006.203.07:34:41.22#ibcon#flushed, iclass 23, count 0 2006.203.07:34:41.22#ibcon#about to write, iclass 23, count 0 2006.203.07:34:41.22#ibcon#wrote, iclass 23, count 0 2006.203.07:34:41.22#ibcon#about to read 3, iclass 23, count 0 2006.203.07:34:41.26#ibcon#read 3, iclass 23, count 0 2006.203.07:34:41.26#ibcon#about to read 4, iclass 23, count 0 2006.203.07:34:41.26#ibcon#read 4, iclass 23, count 0 2006.203.07:34:41.26#ibcon#about to read 5, iclass 23, count 0 2006.203.07:34:41.26#ibcon#read 5, iclass 23, count 0 2006.203.07:34:41.26#ibcon#about to read 6, iclass 23, count 0 2006.203.07:34:41.26#ibcon#read 6, iclass 23, count 0 2006.203.07:34:41.26#ibcon#end of sib2, iclass 23, count 0 2006.203.07:34:41.26#ibcon#*mode == 0, iclass 23, count 0 2006.203.07:34:41.26#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.203.07:34:41.26#ibcon#[25=USB\r\n] 2006.203.07:34:41.26#ibcon#*before write, iclass 23, count 0 2006.203.07:34:41.26#ibcon#enter sib2, iclass 23, count 0 2006.203.07:34:41.26#ibcon#flushed, iclass 23, count 0 2006.203.07:34:41.26#ibcon#about to write, iclass 23, count 0 2006.203.07:34:41.26#ibcon#wrote, iclass 23, count 0 2006.203.07:34:41.26#ibcon#about to read 3, iclass 23, count 0 2006.203.07:34:41.29#ibcon#read 3, iclass 23, count 0 2006.203.07:34:41.29#ibcon#about to read 4, iclass 23, count 0 2006.203.07:34:41.29#ibcon#read 4, iclass 23, count 0 2006.203.07:34:41.29#ibcon#about to read 5, iclass 23, count 0 2006.203.07:34:41.29#ibcon#read 5, iclass 23, count 0 2006.203.07:34:41.29#ibcon#about to read 6, iclass 23, count 0 2006.203.07:34:41.29#ibcon#read 6, iclass 23, count 0 2006.203.07:34:41.29#ibcon#end of sib2, iclass 23, count 0 2006.203.07:34:41.29#ibcon#*after write, iclass 23, count 0 2006.203.07:34:41.29#ibcon#*before return 0, iclass 23, count 0 2006.203.07:34:41.29#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.203.07:34:41.29#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.203.07:34:41.29#ibcon#about to clear, iclass 23 cls_cnt 0 2006.203.07:34:41.29#ibcon#cleared, iclass 23 cls_cnt 0 2006.203.07:34:41.29$vc4f8/valo=8,852.99 2006.203.07:34:41.29#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.203.07:34:41.29#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.203.07:34:41.29#ibcon#ireg 17 cls_cnt 0 2006.203.07:34:41.29#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.203.07:34:41.29#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.203.07:34:41.29#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.203.07:34:41.29#ibcon#enter wrdev, iclass 25, count 0 2006.203.07:34:41.29#ibcon#first serial, iclass 25, count 0 2006.203.07:34:41.29#ibcon#enter sib2, iclass 25, count 0 2006.203.07:34:41.29#ibcon#flushed, iclass 25, count 0 2006.203.07:34:41.29#ibcon#about to write, iclass 25, count 0 2006.203.07:34:41.29#ibcon#wrote, iclass 25, count 0 2006.203.07:34:41.29#ibcon#about to read 3, iclass 25, count 0 2006.203.07:34:41.31#ibcon#read 3, iclass 25, count 0 2006.203.07:34:41.31#ibcon#about to read 4, iclass 25, count 0 2006.203.07:34:41.31#ibcon#read 4, iclass 25, count 0 2006.203.07:34:41.31#ibcon#about to read 5, iclass 25, count 0 2006.203.07:34:41.31#ibcon#read 5, iclass 25, count 0 2006.203.07:34:41.31#ibcon#about to read 6, iclass 25, count 0 2006.203.07:34:41.31#ibcon#read 6, iclass 25, count 0 2006.203.07:34:41.31#ibcon#end of sib2, iclass 25, count 0 2006.203.07:34:41.31#ibcon#*mode == 0, iclass 25, count 0 2006.203.07:34:41.31#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.203.07:34:41.31#ibcon#[26=FRQ=08,852.99\r\n] 2006.203.07:34:41.31#ibcon#*before write, iclass 25, count 0 2006.203.07:34:41.31#ibcon#enter sib2, iclass 25, count 0 2006.203.07:34:41.31#ibcon#flushed, iclass 25, count 0 2006.203.07:34:41.31#ibcon#about to write, iclass 25, count 0 2006.203.07:34:41.31#ibcon#wrote, iclass 25, count 0 2006.203.07:34:41.31#ibcon#about to read 3, iclass 25, count 0 2006.203.07:34:41.35#ibcon#read 3, iclass 25, count 0 2006.203.07:34:41.35#ibcon#about to read 4, iclass 25, count 0 2006.203.07:34:41.35#ibcon#read 4, iclass 25, count 0 2006.203.07:34:41.35#ibcon#about to read 5, iclass 25, count 0 2006.203.07:34:41.35#ibcon#read 5, iclass 25, count 0 2006.203.07:34:41.35#ibcon#about to read 6, iclass 25, count 0 2006.203.07:34:41.35#ibcon#read 6, iclass 25, count 0 2006.203.07:34:41.35#ibcon#end of sib2, iclass 25, count 0 2006.203.07:34:41.35#ibcon#*after write, iclass 25, count 0 2006.203.07:34:41.35#ibcon#*before return 0, iclass 25, count 0 2006.203.07:34:41.35#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.203.07:34:41.35#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.203.07:34:41.35#ibcon#about to clear, iclass 25 cls_cnt 0 2006.203.07:34:41.35#ibcon#cleared, iclass 25 cls_cnt 0 2006.203.07:34:41.35$vc4f8/va=8,6 2006.203.07:34:41.35#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.203.07:34:41.35#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.203.07:34:41.35#ibcon#ireg 11 cls_cnt 2 2006.203.07:34:41.35#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.203.07:34:41.41#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.203.07:34:41.41#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.203.07:34:41.41#ibcon#enter wrdev, iclass 27, count 2 2006.203.07:34:41.41#ibcon#first serial, iclass 27, count 2 2006.203.07:34:41.41#ibcon#enter sib2, iclass 27, count 2 2006.203.07:34:41.41#ibcon#flushed, iclass 27, count 2 2006.203.07:34:41.41#ibcon#about to write, iclass 27, count 2 2006.203.07:34:41.41#ibcon#wrote, iclass 27, count 2 2006.203.07:34:41.41#ibcon#about to read 3, iclass 27, count 2 2006.203.07:34:41.43#ibcon#read 3, iclass 27, count 2 2006.203.07:34:41.43#ibcon#about to read 4, iclass 27, count 2 2006.203.07:34:41.43#ibcon#read 4, iclass 27, count 2 2006.203.07:34:41.43#ibcon#about to read 5, iclass 27, count 2 2006.203.07:34:41.43#ibcon#read 5, iclass 27, count 2 2006.203.07:34:41.43#ibcon#about to read 6, iclass 27, count 2 2006.203.07:34:41.43#ibcon#read 6, iclass 27, count 2 2006.203.07:34:41.43#ibcon#end of sib2, iclass 27, count 2 2006.203.07:34:41.43#ibcon#*mode == 0, iclass 27, count 2 2006.203.07:34:41.43#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.203.07:34:41.43#ibcon#[25=AT08-06\r\n] 2006.203.07:34:41.43#ibcon#*before write, iclass 27, count 2 2006.203.07:34:41.43#ibcon#enter sib2, iclass 27, count 2 2006.203.07:34:41.43#ibcon#flushed, iclass 27, count 2 2006.203.07:34:41.43#ibcon#about to write, iclass 27, count 2 2006.203.07:34:41.43#ibcon#wrote, iclass 27, count 2 2006.203.07:34:41.43#ibcon#about to read 3, iclass 27, count 2 2006.203.07:34:41.46#ibcon#read 3, iclass 27, count 2 2006.203.07:34:41.46#ibcon#about to read 4, iclass 27, count 2 2006.203.07:34:41.46#ibcon#read 4, iclass 27, count 2 2006.203.07:34:41.46#ibcon#about to read 5, iclass 27, count 2 2006.203.07:34:41.46#ibcon#read 5, iclass 27, count 2 2006.203.07:34:41.46#ibcon#about to read 6, iclass 27, count 2 2006.203.07:34:41.46#ibcon#read 6, iclass 27, count 2 2006.203.07:34:41.46#ibcon#end of sib2, iclass 27, count 2 2006.203.07:34:41.46#ibcon#*after write, iclass 27, count 2 2006.203.07:34:41.46#ibcon#*before return 0, iclass 27, count 2 2006.203.07:34:41.46#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.203.07:34:41.46#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.203.07:34:41.46#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.203.07:34:41.46#ibcon#ireg 7 cls_cnt 0 2006.203.07:34:41.46#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.203.07:34:41.58#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.203.07:34:41.58#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.203.07:34:41.58#ibcon#enter wrdev, iclass 27, count 0 2006.203.07:34:41.58#ibcon#first serial, iclass 27, count 0 2006.203.07:34:41.58#ibcon#enter sib2, iclass 27, count 0 2006.203.07:34:41.58#ibcon#flushed, iclass 27, count 0 2006.203.07:34:41.58#ibcon#about to write, iclass 27, count 0 2006.203.07:34:41.58#ibcon#wrote, iclass 27, count 0 2006.203.07:34:41.58#ibcon#about to read 3, iclass 27, count 0 2006.203.07:34:41.60#ibcon#read 3, iclass 27, count 0 2006.203.07:34:41.60#ibcon#about to read 4, iclass 27, count 0 2006.203.07:34:41.60#ibcon#read 4, iclass 27, count 0 2006.203.07:34:41.60#ibcon#about to read 5, iclass 27, count 0 2006.203.07:34:41.60#ibcon#read 5, iclass 27, count 0 2006.203.07:34:41.60#ibcon#about to read 6, iclass 27, count 0 2006.203.07:34:41.60#ibcon#read 6, iclass 27, count 0 2006.203.07:34:41.60#ibcon#end of sib2, iclass 27, count 0 2006.203.07:34:41.60#ibcon#*mode == 0, iclass 27, count 0 2006.203.07:34:41.60#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.203.07:34:41.60#ibcon#[25=USB\r\n] 2006.203.07:34:41.60#ibcon#*before write, iclass 27, count 0 2006.203.07:34:41.60#ibcon#enter sib2, iclass 27, count 0 2006.203.07:34:41.60#ibcon#flushed, iclass 27, count 0 2006.203.07:34:41.60#ibcon#about to write, iclass 27, count 0 2006.203.07:34:41.60#ibcon#wrote, iclass 27, count 0 2006.203.07:34:41.60#ibcon#about to read 3, iclass 27, count 0 2006.203.07:34:41.63#ibcon#read 3, iclass 27, count 0 2006.203.07:34:41.63#ibcon#about to read 4, iclass 27, count 0 2006.203.07:34:41.63#ibcon#read 4, iclass 27, count 0 2006.203.07:34:41.63#ibcon#about to read 5, iclass 27, count 0 2006.203.07:34:41.63#ibcon#read 5, iclass 27, count 0 2006.203.07:34:41.63#ibcon#about to read 6, iclass 27, count 0 2006.203.07:34:41.63#ibcon#read 6, iclass 27, count 0 2006.203.07:34:41.63#ibcon#end of sib2, iclass 27, count 0 2006.203.07:34:41.63#ibcon#*after write, iclass 27, count 0 2006.203.07:34:41.63#ibcon#*before return 0, iclass 27, count 0 2006.203.07:34:41.63#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.203.07:34:41.63#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.203.07:34:41.63#ibcon#about to clear, iclass 27 cls_cnt 0 2006.203.07:34:41.63#ibcon#cleared, iclass 27 cls_cnt 0 2006.203.07:34:41.63$vc4f8/vblo=1,632.99 2006.203.07:34:41.63#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.203.07:34:41.63#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.203.07:34:41.63#ibcon#ireg 17 cls_cnt 0 2006.203.07:34:41.63#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.203.07:34:41.63#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.203.07:34:41.63#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.203.07:34:41.63#ibcon#enter wrdev, iclass 29, count 0 2006.203.07:34:41.63#ibcon#first serial, iclass 29, count 0 2006.203.07:34:41.63#ibcon#enter sib2, iclass 29, count 0 2006.203.07:34:41.63#ibcon#flushed, iclass 29, count 0 2006.203.07:34:41.63#ibcon#about to write, iclass 29, count 0 2006.203.07:34:41.63#ibcon#wrote, iclass 29, count 0 2006.203.07:34:41.63#ibcon#about to read 3, iclass 29, count 0 2006.203.07:34:41.65#ibcon#read 3, iclass 29, count 0 2006.203.07:34:41.65#ibcon#about to read 4, iclass 29, count 0 2006.203.07:34:41.65#ibcon#read 4, iclass 29, count 0 2006.203.07:34:41.65#ibcon#about to read 5, iclass 29, count 0 2006.203.07:34:41.65#ibcon#read 5, iclass 29, count 0 2006.203.07:34:41.65#ibcon#about to read 6, iclass 29, count 0 2006.203.07:34:41.65#ibcon#read 6, iclass 29, count 0 2006.203.07:34:41.65#ibcon#end of sib2, iclass 29, count 0 2006.203.07:34:41.65#ibcon#*mode == 0, iclass 29, count 0 2006.203.07:34:41.65#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.203.07:34:41.65#ibcon#[28=FRQ=01,632.99\r\n] 2006.203.07:34:41.65#ibcon#*before write, iclass 29, count 0 2006.203.07:34:41.65#ibcon#enter sib2, iclass 29, count 0 2006.203.07:34:41.65#ibcon#flushed, iclass 29, count 0 2006.203.07:34:41.65#ibcon#about to write, iclass 29, count 0 2006.203.07:34:41.65#ibcon#wrote, iclass 29, count 0 2006.203.07:34:41.65#ibcon#about to read 3, iclass 29, count 0 2006.203.07:34:41.69#ibcon#read 3, iclass 29, count 0 2006.203.07:34:41.69#ibcon#about to read 4, iclass 29, count 0 2006.203.07:34:41.69#ibcon#read 4, iclass 29, count 0 2006.203.07:34:41.69#ibcon#about to read 5, iclass 29, count 0 2006.203.07:34:41.69#ibcon#read 5, iclass 29, count 0 2006.203.07:34:41.69#ibcon#about to read 6, iclass 29, count 0 2006.203.07:34:41.69#ibcon#read 6, iclass 29, count 0 2006.203.07:34:41.69#ibcon#end of sib2, iclass 29, count 0 2006.203.07:34:41.69#ibcon#*after write, iclass 29, count 0 2006.203.07:34:41.69#ibcon#*before return 0, iclass 29, count 0 2006.203.07:34:41.69#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.203.07:34:41.69#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.203.07:34:41.69#ibcon#about to clear, iclass 29 cls_cnt 0 2006.203.07:34:41.69#ibcon#cleared, iclass 29 cls_cnt 0 2006.203.07:34:41.69$vc4f8/vb=1,4 2006.203.07:34:41.69#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.203.07:34:41.69#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.203.07:34:41.69#ibcon#ireg 11 cls_cnt 2 2006.203.07:34:41.69#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.203.07:34:41.69#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.203.07:34:41.69#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.203.07:34:41.69#ibcon#enter wrdev, iclass 31, count 2 2006.203.07:34:41.69#ibcon#first serial, iclass 31, count 2 2006.203.07:34:41.69#ibcon#enter sib2, iclass 31, count 2 2006.203.07:34:41.69#ibcon#flushed, iclass 31, count 2 2006.203.07:34:41.69#ibcon#about to write, iclass 31, count 2 2006.203.07:34:41.69#ibcon#wrote, iclass 31, count 2 2006.203.07:34:41.69#ibcon#about to read 3, iclass 31, count 2 2006.203.07:34:41.71#ibcon#read 3, iclass 31, count 2 2006.203.07:34:41.71#ibcon#about to read 4, iclass 31, count 2 2006.203.07:34:41.71#ibcon#read 4, iclass 31, count 2 2006.203.07:34:41.71#ibcon#about to read 5, iclass 31, count 2 2006.203.07:34:41.71#ibcon#read 5, iclass 31, count 2 2006.203.07:34:41.71#ibcon#about to read 6, iclass 31, count 2 2006.203.07:34:41.71#ibcon#read 6, iclass 31, count 2 2006.203.07:34:41.71#ibcon#end of sib2, iclass 31, count 2 2006.203.07:34:41.71#ibcon#*mode == 0, iclass 31, count 2 2006.203.07:34:41.71#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.203.07:34:41.71#ibcon#[27=AT01-04\r\n] 2006.203.07:34:41.71#ibcon#*before write, iclass 31, count 2 2006.203.07:34:41.71#ibcon#enter sib2, iclass 31, count 2 2006.203.07:34:41.71#ibcon#flushed, iclass 31, count 2 2006.203.07:34:41.71#ibcon#about to write, iclass 31, count 2 2006.203.07:34:41.71#ibcon#wrote, iclass 31, count 2 2006.203.07:34:41.71#ibcon#about to read 3, iclass 31, count 2 2006.203.07:34:41.74#ibcon#read 3, iclass 31, count 2 2006.203.07:34:41.74#ibcon#about to read 4, iclass 31, count 2 2006.203.07:34:41.74#ibcon#read 4, iclass 31, count 2 2006.203.07:34:41.74#ibcon#about to read 5, iclass 31, count 2 2006.203.07:34:41.74#ibcon#read 5, iclass 31, count 2 2006.203.07:34:41.74#ibcon#about to read 6, iclass 31, count 2 2006.203.07:34:41.74#ibcon#read 6, iclass 31, count 2 2006.203.07:34:41.74#ibcon#end of sib2, iclass 31, count 2 2006.203.07:34:41.74#ibcon#*after write, iclass 31, count 2 2006.203.07:34:41.74#ibcon#*before return 0, iclass 31, count 2 2006.203.07:34:41.74#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.203.07:34:41.74#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.203.07:34:41.74#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.203.07:34:41.74#ibcon#ireg 7 cls_cnt 0 2006.203.07:34:41.74#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.203.07:34:41.87#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.203.07:34:41.87#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.203.07:34:41.87#ibcon#enter wrdev, iclass 31, count 0 2006.203.07:34:41.87#ibcon#first serial, iclass 31, count 0 2006.203.07:34:41.87#ibcon#enter sib2, iclass 31, count 0 2006.203.07:34:41.87#ibcon#flushed, iclass 31, count 0 2006.203.07:34:41.87#ibcon#about to write, iclass 31, count 0 2006.203.07:34:41.87#ibcon#wrote, iclass 31, count 0 2006.203.07:34:41.87#ibcon#about to read 3, iclass 31, count 0 2006.203.07:34:41.88#ibcon#read 3, iclass 31, count 0 2006.203.07:34:41.88#ibcon#about to read 4, iclass 31, count 0 2006.203.07:34:41.88#ibcon#read 4, iclass 31, count 0 2006.203.07:34:41.88#ibcon#about to read 5, iclass 31, count 0 2006.203.07:34:41.88#ibcon#read 5, iclass 31, count 0 2006.203.07:34:41.88#ibcon#about to read 6, iclass 31, count 0 2006.203.07:34:41.88#ibcon#read 6, iclass 31, count 0 2006.203.07:34:41.88#ibcon#end of sib2, iclass 31, count 0 2006.203.07:34:41.88#ibcon#*mode == 0, iclass 31, count 0 2006.203.07:34:41.88#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.203.07:34:41.88#ibcon#[27=USB\r\n] 2006.203.07:34:41.88#ibcon#*before write, iclass 31, count 0 2006.203.07:34:41.88#ibcon#enter sib2, iclass 31, count 0 2006.203.07:34:41.88#ibcon#flushed, iclass 31, count 0 2006.203.07:34:41.88#ibcon#about to write, iclass 31, count 0 2006.203.07:34:41.88#ibcon#wrote, iclass 31, count 0 2006.203.07:34:41.88#ibcon#about to read 3, iclass 31, count 0 2006.203.07:34:41.91#ibcon#read 3, iclass 31, count 0 2006.203.07:34:41.91#ibcon#about to read 4, iclass 31, count 0 2006.203.07:34:41.91#ibcon#read 4, iclass 31, count 0 2006.203.07:34:41.91#ibcon#about to read 5, iclass 31, count 0 2006.203.07:34:41.91#ibcon#read 5, iclass 31, count 0 2006.203.07:34:41.91#ibcon#about to read 6, iclass 31, count 0 2006.203.07:34:41.91#ibcon#read 6, iclass 31, count 0 2006.203.07:34:41.91#ibcon#end of sib2, iclass 31, count 0 2006.203.07:34:41.91#ibcon#*after write, iclass 31, count 0 2006.203.07:34:41.91#ibcon#*before return 0, iclass 31, count 0 2006.203.07:34:41.91#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.203.07:34:41.91#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.203.07:34:41.91#ibcon#about to clear, iclass 31 cls_cnt 0 2006.203.07:34:41.91#ibcon#cleared, iclass 31 cls_cnt 0 2006.203.07:34:41.91$vc4f8/vblo=2,640.99 2006.203.07:34:41.91#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.203.07:34:41.91#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.203.07:34:41.91#ibcon#ireg 17 cls_cnt 0 2006.203.07:34:41.91#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.203.07:34:41.91#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.203.07:34:41.91#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.203.07:34:41.91#ibcon#enter wrdev, iclass 33, count 0 2006.203.07:34:41.91#ibcon#first serial, iclass 33, count 0 2006.203.07:34:41.91#ibcon#enter sib2, iclass 33, count 0 2006.203.07:34:41.91#ibcon#flushed, iclass 33, count 0 2006.203.07:34:41.91#ibcon#about to write, iclass 33, count 0 2006.203.07:34:41.91#ibcon#wrote, iclass 33, count 0 2006.203.07:34:41.91#ibcon#about to read 3, iclass 33, count 0 2006.203.07:34:41.93#ibcon#read 3, iclass 33, count 0 2006.203.07:34:41.93#ibcon#about to read 4, iclass 33, count 0 2006.203.07:34:41.93#ibcon#read 4, iclass 33, count 0 2006.203.07:34:41.93#ibcon#about to read 5, iclass 33, count 0 2006.203.07:34:41.93#ibcon#read 5, iclass 33, count 0 2006.203.07:34:41.93#ibcon#about to read 6, iclass 33, count 0 2006.203.07:34:41.93#ibcon#read 6, iclass 33, count 0 2006.203.07:34:41.93#ibcon#end of sib2, iclass 33, count 0 2006.203.07:34:41.93#ibcon#*mode == 0, iclass 33, count 0 2006.203.07:34:41.93#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.203.07:34:41.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.203.07:34:41.93#ibcon#*before write, iclass 33, count 0 2006.203.07:34:41.93#ibcon#enter sib2, iclass 33, count 0 2006.203.07:34:41.93#ibcon#flushed, iclass 33, count 0 2006.203.07:34:41.93#ibcon#about to write, iclass 33, count 0 2006.203.07:34:41.93#ibcon#wrote, iclass 33, count 0 2006.203.07:34:41.93#ibcon#about to read 3, iclass 33, count 0 2006.203.07:34:41.97#ibcon#read 3, iclass 33, count 0 2006.203.07:34:41.97#ibcon#about to read 4, iclass 33, count 0 2006.203.07:34:41.97#ibcon#read 4, iclass 33, count 0 2006.203.07:34:41.97#ibcon#about to read 5, iclass 33, count 0 2006.203.07:34:41.97#ibcon#read 5, iclass 33, count 0 2006.203.07:34:41.97#ibcon#about to read 6, iclass 33, count 0 2006.203.07:34:41.97#ibcon#read 6, iclass 33, count 0 2006.203.07:34:41.97#ibcon#end of sib2, iclass 33, count 0 2006.203.07:34:41.97#ibcon#*after write, iclass 33, count 0 2006.203.07:34:41.97#ibcon#*before return 0, iclass 33, count 0 2006.203.07:34:41.97#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.203.07:34:41.97#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.203.07:34:41.97#ibcon#about to clear, iclass 33 cls_cnt 0 2006.203.07:34:41.97#ibcon#cleared, iclass 33 cls_cnt 0 2006.203.07:34:41.97$vc4f8/vb=2,4 2006.203.07:34:41.97#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.203.07:34:41.97#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.203.07:34:41.97#ibcon#ireg 11 cls_cnt 2 2006.203.07:34:41.97#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.203.07:34:42.03#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.203.07:34:42.03#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.203.07:34:42.03#ibcon#enter wrdev, iclass 35, count 2 2006.203.07:34:42.03#ibcon#first serial, iclass 35, count 2 2006.203.07:34:42.03#ibcon#enter sib2, iclass 35, count 2 2006.203.07:34:42.03#ibcon#flushed, iclass 35, count 2 2006.203.07:34:42.03#ibcon#about to write, iclass 35, count 2 2006.203.07:34:42.03#ibcon#wrote, iclass 35, count 2 2006.203.07:34:42.03#ibcon#about to read 3, iclass 35, count 2 2006.203.07:34:42.05#ibcon#read 3, iclass 35, count 2 2006.203.07:34:42.05#ibcon#about to read 4, iclass 35, count 2 2006.203.07:34:42.05#ibcon#read 4, iclass 35, count 2 2006.203.07:34:42.05#ibcon#about to read 5, iclass 35, count 2 2006.203.07:34:42.05#ibcon#read 5, iclass 35, count 2 2006.203.07:34:42.05#ibcon#about to read 6, iclass 35, count 2 2006.203.07:34:42.05#ibcon#read 6, iclass 35, count 2 2006.203.07:34:42.05#ibcon#end of sib2, iclass 35, count 2 2006.203.07:34:42.05#ibcon#*mode == 0, iclass 35, count 2 2006.203.07:34:42.05#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.203.07:34:42.05#ibcon#[27=AT02-04\r\n] 2006.203.07:34:42.05#ibcon#*before write, iclass 35, count 2 2006.203.07:34:42.05#ibcon#enter sib2, iclass 35, count 2 2006.203.07:34:42.05#ibcon#flushed, iclass 35, count 2 2006.203.07:34:42.05#ibcon#about to write, iclass 35, count 2 2006.203.07:34:42.05#ibcon#wrote, iclass 35, count 2 2006.203.07:34:42.05#ibcon#about to read 3, iclass 35, count 2 2006.203.07:34:42.08#ibcon#read 3, iclass 35, count 2 2006.203.07:34:42.08#ibcon#about to read 4, iclass 35, count 2 2006.203.07:34:42.08#ibcon#read 4, iclass 35, count 2 2006.203.07:34:42.08#ibcon#about to read 5, iclass 35, count 2 2006.203.07:34:42.08#ibcon#read 5, iclass 35, count 2 2006.203.07:34:42.08#ibcon#about to read 6, iclass 35, count 2 2006.203.07:34:42.08#ibcon#read 6, iclass 35, count 2 2006.203.07:34:42.08#ibcon#end of sib2, iclass 35, count 2 2006.203.07:34:42.08#ibcon#*after write, iclass 35, count 2 2006.203.07:34:42.08#ibcon#*before return 0, iclass 35, count 2 2006.203.07:34:42.08#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.203.07:34:42.08#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.203.07:34:42.08#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.203.07:34:42.08#ibcon#ireg 7 cls_cnt 0 2006.203.07:34:42.08#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.203.07:34:42.20#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.203.07:34:42.20#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.203.07:34:42.20#ibcon#enter wrdev, iclass 35, count 0 2006.203.07:34:42.20#ibcon#first serial, iclass 35, count 0 2006.203.07:34:42.20#ibcon#enter sib2, iclass 35, count 0 2006.203.07:34:42.20#ibcon#flushed, iclass 35, count 0 2006.203.07:34:42.20#ibcon#about to write, iclass 35, count 0 2006.203.07:34:42.20#ibcon#wrote, iclass 35, count 0 2006.203.07:34:42.20#ibcon#about to read 3, iclass 35, count 0 2006.203.07:34:42.22#ibcon#read 3, iclass 35, count 0 2006.203.07:34:42.22#ibcon#about to read 4, iclass 35, count 0 2006.203.07:34:42.22#ibcon#read 4, iclass 35, count 0 2006.203.07:34:42.22#ibcon#about to read 5, iclass 35, count 0 2006.203.07:34:42.22#ibcon#read 5, iclass 35, count 0 2006.203.07:34:42.22#ibcon#about to read 6, iclass 35, count 0 2006.203.07:34:42.22#ibcon#read 6, iclass 35, count 0 2006.203.07:34:42.22#ibcon#end of sib2, iclass 35, count 0 2006.203.07:34:42.22#ibcon#*mode == 0, iclass 35, count 0 2006.203.07:34:42.22#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.203.07:34:42.22#ibcon#[27=USB\r\n] 2006.203.07:34:42.22#ibcon#*before write, iclass 35, count 0 2006.203.07:34:42.22#ibcon#enter sib2, iclass 35, count 0 2006.203.07:34:42.22#ibcon#flushed, iclass 35, count 0 2006.203.07:34:42.22#ibcon#about to write, iclass 35, count 0 2006.203.07:34:42.22#ibcon#wrote, iclass 35, count 0 2006.203.07:34:42.22#ibcon#about to read 3, iclass 35, count 0 2006.203.07:34:42.25#ibcon#read 3, iclass 35, count 0 2006.203.07:34:42.25#ibcon#about to read 4, iclass 35, count 0 2006.203.07:34:42.25#ibcon#read 4, iclass 35, count 0 2006.203.07:34:42.25#ibcon#about to read 5, iclass 35, count 0 2006.203.07:34:42.25#ibcon#read 5, iclass 35, count 0 2006.203.07:34:42.25#ibcon#about to read 6, iclass 35, count 0 2006.203.07:34:42.25#ibcon#read 6, iclass 35, count 0 2006.203.07:34:42.25#ibcon#end of sib2, iclass 35, count 0 2006.203.07:34:42.25#ibcon#*after write, iclass 35, count 0 2006.203.07:34:42.25#ibcon#*before return 0, iclass 35, count 0 2006.203.07:34:42.25#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.203.07:34:42.25#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.203.07:34:42.25#ibcon#about to clear, iclass 35 cls_cnt 0 2006.203.07:34:42.25#ibcon#cleared, iclass 35 cls_cnt 0 2006.203.07:34:42.25$vc4f8/vblo=3,656.99 2006.203.07:34:42.25#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.203.07:34:42.25#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.203.07:34:42.25#ibcon#ireg 17 cls_cnt 0 2006.203.07:34:42.25#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.203.07:34:42.25#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.203.07:34:42.25#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.203.07:34:42.25#ibcon#enter wrdev, iclass 37, count 0 2006.203.07:34:42.25#ibcon#first serial, iclass 37, count 0 2006.203.07:34:42.25#ibcon#enter sib2, iclass 37, count 0 2006.203.07:34:42.25#ibcon#flushed, iclass 37, count 0 2006.203.07:34:42.25#ibcon#about to write, iclass 37, count 0 2006.203.07:34:42.25#ibcon#wrote, iclass 37, count 0 2006.203.07:34:42.25#ibcon#about to read 3, iclass 37, count 0 2006.203.07:34:42.27#ibcon#read 3, iclass 37, count 0 2006.203.07:34:42.27#ibcon#about to read 4, iclass 37, count 0 2006.203.07:34:42.27#ibcon#read 4, iclass 37, count 0 2006.203.07:34:42.27#ibcon#about to read 5, iclass 37, count 0 2006.203.07:34:42.27#ibcon#read 5, iclass 37, count 0 2006.203.07:34:42.27#ibcon#about to read 6, iclass 37, count 0 2006.203.07:34:42.27#ibcon#read 6, iclass 37, count 0 2006.203.07:34:42.27#ibcon#end of sib2, iclass 37, count 0 2006.203.07:34:42.27#ibcon#*mode == 0, iclass 37, count 0 2006.203.07:34:42.27#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.203.07:34:42.27#ibcon#[28=FRQ=03,656.99\r\n] 2006.203.07:34:42.27#ibcon#*before write, iclass 37, count 0 2006.203.07:34:42.27#ibcon#enter sib2, iclass 37, count 0 2006.203.07:34:42.27#ibcon#flushed, iclass 37, count 0 2006.203.07:34:42.27#ibcon#about to write, iclass 37, count 0 2006.203.07:34:42.27#ibcon#wrote, iclass 37, count 0 2006.203.07:34:42.27#ibcon#about to read 3, iclass 37, count 0 2006.203.07:34:42.31#ibcon#read 3, iclass 37, count 0 2006.203.07:34:42.31#ibcon#about to read 4, iclass 37, count 0 2006.203.07:34:42.31#ibcon#read 4, iclass 37, count 0 2006.203.07:34:42.31#ibcon#about to read 5, iclass 37, count 0 2006.203.07:34:42.31#ibcon#read 5, iclass 37, count 0 2006.203.07:34:42.31#ibcon#about to read 6, iclass 37, count 0 2006.203.07:34:42.31#ibcon#read 6, iclass 37, count 0 2006.203.07:34:42.31#ibcon#end of sib2, iclass 37, count 0 2006.203.07:34:42.31#ibcon#*after write, iclass 37, count 0 2006.203.07:34:42.31#ibcon#*before return 0, iclass 37, count 0 2006.203.07:34:42.31#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.203.07:34:42.31#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.203.07:34:42.31#ibcon#about to clear, iclass 37 cls_cnt 0 2006.203.07:34:42.31#ibcon#cleared, iclass 37 cls_cnt 0 2006.203.07:34:42.31$vc4f8/vb=3,4 2006.203.07:34:42.31#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.203.07:34:42.31#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.203.07:34:42.31#ibcon#ireg 11 cls_cnt 2 2006.203.07:34:42.31#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.203.07:34:42.37#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.203.07:34:42.37#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.203.07:34:42.37#ibcon#enter wrdev, iclass 39, count 2 2006.203.07:34:42.37#ibcon#first serial, iclass 39, count 2 2006.203.07:34:42.37#ibcon#enter sib2, iclass 39, count 2 2006.203.07:34:42.37#ibcon#flushed, iclass 39, count 2 2006.203.07:34:42.37#ibcon#about to write, iclass 39, count 2 2006.203.07:34:42.37#ibcon#wrote, iclass 39, count 2 2006.203.07:34:42.37#ibcon#about to read 3, iclass 39, count 2 2006.203.07:34:42.39#ibcon#read 3, iclass 39, count 2 2006.203.07:34:42.39#ibcon#about to read 4, iclass 39, count 2 2006.203.07:34:42.39#ibcon#read 4, iclass 39, count 2 2006.203.07:34:42.39#ibcon#about to read 5, iclass 39, count 2 2006.203.07:34:42.39#ibcon#read 5, iclass 39, count 2 2006.203.07:34:42.39#ibcon#about to read 6, iclass 39, count 2 2006.203.07:34:42.39#ibcon#read 6, iclass 39, count 2 2006.203.07:34:42.39#ibcon#end of sib2, iclass 39, count 2 2006.203.07:34:42.39#ibcon#*mode == 0, iclass 39, count 2 2006.203.07:34:42.39#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.203.07:34:42.39#ibcon#[27=AT03-04\r\n] 2006.203.07:34:42.39#ibcon#*before write, iclass 39, count 2 2006.203.07:34:42.39#ibcon#enter sib2, iclass 39, count 2 2006.203.07:34:42.39#ibcon#flushed, iclass 39, count 2 2006.203.07:34:42.39#ibcon#about to write, iclass 39, count 2 2006.203.07:34:42.39#ibcon#wrote, iclass 39, count 2 2006.203.07:34:42.39#ibcon#about to read 3, iclass 39, count 2 2006.203.07:34:42.42#ibcon#read 3, iclass 39, count 2 2006.203.07:34:42.42#ibcon#about to read 4, iclass 39, count 2 2006.203.07:34:42.42#ibcon#read 4, iclass 39, count 2 2006.203.07:34:42.42#ibcon#about to read 5, iclass 39, count 2 2006.203.07:34:42.42#ibcon#read 5, iclass 39, count 2 2006.203.07:34:42.42#ibcon#about to read 6, iclass 39, count 2 2006.203.07:34:42.42#ibcon#read 6, iclass 39, count 2 2006.203.07:34:42.42#ibcon#end of sib2, iclass 39, count 2 2006.203.07:34:42.42#ibcon#*after write, iclass 39, count 2 2006.203.07:34:42.42#ibcon#*before return 0, iclass 39, count 2 2006.203.07:34:42.42#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.203.07:34:42.42#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.203.07:34:42.42#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.203.07:34:42.42#ibcon#ireg 7 cls_cnt 0 2006.203.07:34:42.42#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.203.07:34:42.54#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.203.07:34:42.54#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.203.07:34:42.54#ibcon#enter wrdev, iclass 39, count 0 2006.203.07:34:42.54#ibcon#first serial, iclass 39, count 0 2006.203.07:34:42.54#ibcon#enter sib2, iclass 39, count 0 2006.203.07:34:42.54#ibcon#flushed, iclass 39, count 0 2006.203.07:34:42.54#ibcon#about to write, iclass 39, count 0 2006.203.07:34:42.54#ibcon#wrote, iclass 39, count 0 2006.203.07:34:42.54#ibcon#about to read 3, iclass 39, count 0 2006.203.07:34:42.56#ibcon#read 3, iclass 39, count 0 2006.203.07:34:42.56#ibcon#about to read 4, iclass 39, count 0 2006.203.07:34:42.56#ibcon#read 4, iclass 39, count 0 2006.203.07:34:42.56#ibcon#about to read 5, iclass 39, count 0 2006.203.07:34:42.56#ibcon#read 5, iclass 39, count 0 2006.203.07:34:42.56#ibcon#about to read 6, iclass 39, count 0 2006.203.07:34:42.56#ibcon#read 6, iclass 39, count 0 2006.203.07:34:42.56#ibcon#end of sib2, iclass 39, count 0 2006.203.07:34:42.56#ibcon#*mode == 0, iclass 39, count 0 2006.203.07:34:42.56#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.203.07:34:42.56#ibcon#[27=USB\r\n] 2006.203.07:34:42.56#ibcon#*before write, iclass 39, count 0 2006.203.07:34:42.56#ibcon#enter sib2, iclass 39, count 0 2006.203.07:34:42.56#ibcon#flushed, iclass 39, count 0 2006.203.07:34:42.56#ibcon#about to write, iclass 39, count 0 2006.203.07:34:42.56#ibcon#wrote, iclass 39, count 0 2006.203.07:34:42.56#ibcon#about to read 3, iclass 39, count 0 2006.203.07:34:42.59#ibcon#read 3, iclass 39, count 0 2006.203.07:34:42.59#ibcon#about to read 4, iclass 39, count 0 2006.203.07:34:42.59#ibcon#read 4, iclass 39, count 0 2006.203.07:34:42.59#ibcon#about to read 5, iclass 39, count 0 2006.203.07:34:42.59#ibcon#read 5, iclass 39, count 0 2006.203.07:34:42.59#ibcon#about to read 6, iclass 39, count 0 2006.203.07:34:42.59#ibcon#read 6, iclass 39, count 0 2006.203.07:34:42.59#ibcon#end of sib2, iclass 39, count 0 2006.203.07:34:42.59#ibcon#*after write, iclass 39, count 0 2006.203.07:34:42.59#ibcon#*before return 0, iclass 39, count 0 2006.203.07:34:42.59#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.203.07:34:42.59#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.203.07:34:42.59#ibcon#about to clear, iclass 39 cls_cnt 0 2006.203.07:34:42.59#ibcon#cleared, iclass 39 cls_cnt 0 2006.203.07:34:42.59$vc4f8/vblo=4,712.99 2006.203.07:34:42.59#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.203.07:34:42.59#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.203.07:34:42.59#ibcon#ireg 17 cls_cnt 0 2006.203.07:34:42.59#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.203.07:34:42.59#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.203.07:34:42.59#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.203.07:34:42.59#ibcon#enter wrdev, iclass 3, count 0 2006.203.07:34:42.59#ibcon#first serial, iclass 3, count 0 2006.203.07:34:42.59#ibcon#enter sib2, iclass 3, count 0 2006.203.07:34:42.59#ibcon#flushed, iclass 3, count 0 2006.203.07:34:42.59#ibcon#about to write, iclass 3, count 0 2006.203.07:34:42.59#ibcon#wrote, iclass 3, count 0 2006.203.07:34:42.59#ibcon#about to read 3, iclass 3, count 0 2006.203.07:34:42.61#ibcon#read 3, iclass 3, count 0 2006.203.07:34:42.61#ibcon#about to read 4, iclass 3, count 0 2006.203.07:34:42.61#ibcon#read 4, iclass 3, count 0 2006.203.07:34:42.61#ibcon#about to read 5, iclass 3, count 0 2006.203.07:34:42.61#ibcon#read 5, iclass 3, count 0 2006.203.07:34:42.61#ibcon#about to read 6, iclass 3, count 0 2006.203.07:34:42.61#ibcon#read 6, iclass 3, count 0 2006.203.07:34:42.61#ibcon#end of sib2, iclass 3, count 0 2006.203.07:34:42.61#ibcon#*mode == 0, iclass 3, count 0 2006.203.07:34:42.61#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.203.07:34:42.61#ibcon#[28=FRQ=04,712.99\r\n] 2006.203.07:34:42.61#ibcon#*before write, iclass 3, count 0 2006.203.07:34:42.61#ibcon#enter sib2, iclass 3, count 0 2006.203.07:34:42.61#ibcon#flushed, iclass 3, count 0 2006.203.07:34:42.61#ibcon#about to write, iclass 3, count 0 2006.203.07:34:42.61#ibcon#wrote, iclass 3, count 0 2006.203.07:34:42.61#ibcon#about to read 3, iclass 3, count 0 2006.203.07:34:42.65#ibcon#read 3, iclass 3, count 0 2006.203.07:34:42.65#ibcon#about to read 4, iclass 3, count 0 2006.203.07:34:42.65#ibcon#read 4, iclass 3, count 0 2006.203.07:34:42.65#ibcon#about to read 5, iclass 3, count 0 2006.203.07:34:42.65#ibcon#read 5, iclass 3, count 0 2006.203.07:34:42.65#ibcon#about to read 6, iclass 3, count 0 2006.203.07:34:42.65#ibcon#read 6, iclass 3, count 0 2006.203.07:34:42.65#ibcon#end of sib2, iclass 3, count 0 2006.203.07:34:42.65#ibcon#*after write, iclass 3, count 0 2006.203.07:34:42.65#ibcon#*before return 0, iclass 3, count 0 2006.203.07:34:42.65#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.203.07:34:42.65#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.203.07:34:42.65#ibcon#about to clear, iclass 3 cls_cnt 0 2006.203.07:34:42.65#ibcon#cleared, iclass 3 cls_cnt 0 2006.203.07:34:42.65$vc4f8/vb=4,4 2006.203.07:34:42.65#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.203.07:34:42.65#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.203.07:34:42.65#ibcon#ireg 11 cls_cnt 2 2006.203.07:34:42.65#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.203.07:34:42.71#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.203.07:34:42.71#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.203.07:34:42.71#ibcon#enter wrdev, iclass 5, count 2 2006.203.07:34:42.71#ibcon#first serial, iclass 5, count 2 2006.203.07:34:42.71#ibcon#enter sib2, iclass 5, count 2 2006.203.07:34:42.71#ibcon#flushed, iclass 5, count 2 2006.203.07:34:42.71#ibcon#about to write, iclass 5, count 2 2006.203.07:34:42.71#ibcon#wrote, iclass 5, count 2 2006.203.07:34:42.71#ibcon#about to read 3, iclass 5, count 2 2006.203.07:34:42.74#ibcon#read 3, iclass 5, count 2 2006.203.07:34:42.74#ibcon#about to read 4, iclass 5, count 2 2006.203.07:34:42.74#ibcon#read 4, iclass 5, count 2 2006.203.07:34:42.74#ibcon#about to read 5, iclass 5, count 2 2006.203.07:34:42.74#ibcon#read 5, iclass 5, count 2 2006.203.07:34:42.74#ibcon#about to read 6, iclass 5, count 2 2006.203.07:34:42.74#ibcon#read 6, iclass 5, count 2 2006.203.07:34:42.74#ibcon#end of sib2, iclass 5, count 2 2006.203.07:34:42.74#ibcon#*mode == 0, iclass 5, count 2 2006.203.07:34:42.74#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.203.07:34:42.74#ibcon#[27=AT04-04\r\n] 2006.203.07:34:42.74#ibcon#*before write, iclass 5, count 2 2006.203.07:34:42.74#ibcon#enter sib2, iclass 5, count 2 2006.203.07:34:42.74#ibcon#flushed, iclass 5, count 2 2006.203.07:34:42.74#ibcon#about to write, iclass 5, count 2 2006.203.07:34:42.74#ibcon#wrote, iclass 5, count 2 2006.203.07:34:42.74#ibcon#about to read 3, iclass 5, count 2 2006.203.07:34:42.77#ibcon#read 3, iclass 5, count 2 2006.203.07:34:42.77#ibcon#about to read 4, iclass 5, count 2 2006.203.07:34:42.77#ibcon#read 4, iclass 5, count 2 2006.203.07:34:42.77#ibcon#about to read 5, iclass 5, count 2 2006.203.07:34:42.77#ibcon#read 5, iclass 5, count 2 2006.203.07:34:42.77#ibcon#about to read 6, iclass 5, count 2 2006.203.07:34:42.77#ibcon#read 6, iclass 5, count 2 2006.203.07:34:42.77#ibcon#end of sib2, iclass 5, count 2 2006.203.07:34:42.77#ibcon#*after write, iclass 5, count 2 2006.203.07:34:42.77#ibcon#*before return 0, iclass 5, count 2 2006.203.07:34:42.77#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.203.07:34:42.77#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.203.07:34:42.77#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.203.07:34:42.77#ibcon#ireg 7 cls_cnt 0 2006.203.07:34:42.77#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.203.07:34:42.89#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.203.07:34:42.89#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.203.07:34:42.89#ibcon#enter wrdev, iclass 5, count 0 2006.203.07:34:42.89#ibcon#first serial, iclass 5, count 0 2006.203.07:34:42.89#ibcon#enter sib2, iclass 5, count 0 2006.203.07:34:42.89#ibcon#flushed, iclass 5, count 0 2006.203.07:34:42.89#ibcon#about to write, iclass 5, count 0 2006.203.07:34:42.89#ibcon#wrote, iclass 5, count 0 2006.203.07:34:42.89#ibcon#about to read 3, iclass 5, count 0 2006.203.07:34:42.91#ibcon#read 3, iclass 5, count 0 2006.203.07:34:42.91#ibcon#about to read 4, iclass 5, count 0 2006.203.07:34:42.91#ibcon#read 4, iclass 5, count 0 2006.203.07:34:42.91#ibcon#about to read 5, iclass 5, count 0 2006.203.07:34:42.91#ibcon#read 5, iclass 5, count 0 2006.203.07:34:42.91#ibcon#about to read 6, iclass 5, count 0 2006.203.07:34:42.91#ibcon#read 6, iclass 5, count 0 2006.203.07:34:42.91#ibcon#end of sib2, iclass 5, count 0 2006.203.07:34:42.91#ibcon#*mode == 0, iclass 5, count 0 2006.203.07:34:42.91#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.203.07:34:42.91#ibcon#[27=USB\r\n] 2006.203.07:34:42.91#ibcon#*before write, iclass 5, count 0 2006.203.07:34:42.91#ibcon#enter sib2, iclass 5, count 0 2006.203.07:34:42.91#ibcon#flushed, iclass 5, count 0 2006.203.07:34:42.91#ibcon#about to write, iclass 5, count 0 2006.203.07:34:42.91#ibcon#wrote, iclass 5, count 0 2006.203.07:34:42.91#ibcon#about to read 3, iclass 5, count 0 2006.203.07:34:42.94#ibcon#read 3, iclass 5, count 0 2006.203.07:34:42.94#ibcon#about to read 4, iclass 5, count 0 2006.203.07:34:42.94#ibcon#read 4, iclass 5, count 0 2006.203.07:34:42.94#ibcon#about to read 5, iclass 5, count 0 2006.203.07:34:42.94#ibcon#read 5, iclass 5, count 0 2006.203.07:34:42.94#ibcon#about to read 6, iclass 5, count 0 2006.203.07:34:42.94#ibcon#read 6, iclass 5, count 0 2006.203.07:34:42.94#ibcon#end of sib2, iclass 5, count 0 2006.203.07:34:42.94#ibcon#*after write, iclass 5, count 0 2006.203.07:34:42.94#ibcon#*before return 0, iclass 5, count 0 2006.203.07:34:42.94#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.203.07:34:42.94#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.203.07:34:42.94#ibcon#about to clear, iclass 5 cls_cnt 0 2006.203.07:34:42.94#ibcon#cleared, iclass 5 cls_cnt 0 2006.203.07:34:42.94$vc4f8/vblo=5,744.99 2006.203.07:34:42.94#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.203.07:34:42.94#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.203.07:34:42.94#ibcon#ireg 17 cls_cnt 0 2006.203.07:34:42.94#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.203.07:34:42.94#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.203.07:34:42.94#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.203.07:34:42.94#ibcon#enter wrdev, iclass 7, count 0 2006.203.07:34:42.94#ibcon#first serial, iclass 7, count 0 2006.203.07:34:42.94#ibcon#enter sib2, iclass 7, count 0 2006.203.07:34:42.94#ibcon#flushed, iclass 7, count 0 2006.203.07:34:42.94#ibcon#about to write, iclass 7, count 0 2006.203.07:34:42.94#ibcon#wrote, iclass 7, count 0 2006.203.07:34:42.94#ibcon#about to read 3, iclass 7, count 0 2006.203.07:34:42.96#ibcon#read 3, iclass 7, count 0 2006.203.07:34:42.96#ibcon#about to read 4, iclass 7, count 0 2006.203.07:34:42.96#ibcon#read 4, iclass 7, count 0 2006.203.07:34:42.96#ibcon#about to read 5, iclass 7, count 0 2006.203.07:34:42.96#ibcon#read 5, iclass 7, count 0 2006.203.07:34:42.96#ibcon#about to read 6, iclass 7, count 0 2006.203.07:34:42.96#ibcon#read 6, iclass 7, count 0 2006.203.07:34:42.96#ibcon#end of sib2, iclass 7, count 0 2006.203.07:34:42.96#ibcon#*mode == 0, iclass 7, count 0 2006.203.07:34:42.96#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.203.07:34:42.96#ibcon#[28=FRQ=05,744.99\r\n] 2006.203.07:34:42.96#ibcon#*before write, iclass 7, count 0 2006.203.07:34:42.96#ibcon#enter sib2, iclass 7, count 0 2006.203.07:34:42.96#ibcon#flushed, iclass 7, count 0 2006.203.07:34:42.96#ibcon#about to write, iclass 7, count 0 2006.203.07:34:42.96#ibcon#wrote, iclass 7, count 0 2006.203.07:34:42.96#ibcon#about to read 3, iclass 7, count 0 2006.203.07:34:43.00#ibcon#read 3, iclass 7, count 0 2006.203.07:34:43.00#ibcon#about to read 4, iclass 7, count 0 2006.203.07:34:43.00#ibcon#read 4, iclass 7, count 0 2006.203.07:34:43.00#ibcon#about to read 5, iclass 7, count 0 2006.203.07:34:43.00#ibcon#read 5, iclass 7, count 0 2006.203.07:34:43.00#ibcon#about to read 6, iclass 7, count 0 2006.203.07:34:43.00#ibcon#read 6, iclass 7, count 0 2006.203.07:34:43.00#ibcon#end of sib2, iclass 7, count 0 2006.203.07:34:43.00#ibcon#*after write, iclass 7, count 0 2006.203.07:34:43.00#ibcon#*before return 0, iclass 7, count 0 2006.203.07:34:43.00#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.203.07:34:43.00#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.203.07:34:43.00#ibcon#about to clear, iclass 7 cls_cnt 0 2006.203.07:34:43.00#ibcon#cleared, iclass 7 cls_cnt 0 2006.203.07:34:43.00$vc4f8/vb=5,3 2006.203.07:34:43.00#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.203.07:34:43.00#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.203.07:34:43.00#ibcon#ireg 11 cls_cnt 2 2006.203.07:34:43.00#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.203.07:34:43.06#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.203.07:34:43.06#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.203.07:34:43.06#ibcon#enter wrdev, iclass 11, count 2 2006.203.07:34:43.06#ibcon#first serial, iclass 11, count 2 2006.203.07:34:43.06#ibcon#enter sib2, iclass 11, count 2 2006.203.07:34:43.06#ibcon#flushed, iclass 11, count 2 2006.203.07:34:43.06#ibcon#about to write, iclass 11, count 2 2006.203.07:34:43.06#ibcon#wrote, iclass 11, count 2 2006.203.07:34:43.06#ibcon#about to read 3, iclass 11, count 2 2006.203.07:34:43.08#ibcon#read 3, iclass 11, count 2 2006.203.07:34:43.08#ibcon#about to read 4, iclass 11, count 2 2006.203.07:34:43.08#ibcon#read 4, iclass 11, count 2 2006.203.07:34:43.08#ibcon#about to read 5, iclass 11, count 2 2006.203.07:34:43.08#ibcon#read 5, iclass 11, count 2 2006.203.07:34:43.08#ibcon#about to read 6, iclass 11, count 2 2006.203.07:34:43.08#ibcon#read 6, iclass 11, count 2 2006.203.07:34:43.08#ibcon#end of sib2, iclass 11, count 2 2006.203.07:34:43.08#ibcon#*mode == 0, iclass 11, count 2 2006.203.07:34:43.08#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.203.07:34:43.08#ibcon#[27=AT05-03\r\n] 2006.203.07:34:43.08#ibcon#*before write, iclass 11, count 2 2006.203.07:34:43.08#ibcon#enter sib2, iclass 11, count 2 2006.203.07:34:43.08#ibcon#flushed, iclass 11, count 2 2006.203.07:34:43.08#ibcon#about to write, iclass 11, count 2 2006.203.07:34:43.08#ibcon#wrote, iclass 11, count 2 2006.203.07:34:43.08#ibcon#about to read 3, iclass 11, count 2 2006.203.07:34:43.11#ibcon#read 3, iclass 11, count 2 2006.203.07:34:43.11#ibcon#about to read 4, iclass 11, count 2 2006.203.07:34:43.11#ibcon#read 4, iclass 11, count 2 2006.203.07:34:43.11#ibcon#about to read 5, iclass 11, count 2 2006.203.07:34:43.11#ibcon#read 5, iclass 11, count 2 2006.203.07:34:43.11#ibcon#about to read 6, iclass 11, count 2 2006.203.07:34:43.11#ibcon#read 6, iclass 11, count 2 2006.203.07:34:43.11#ibcon#end of sib2, iclass 11, count 2 2006.203.07:34:43.11#ibcon#*after write, iclass 11, count 2 2006.203.07:34:43.11#ibcon#*before return 0, iclass 11, count 2 2006.203.07:34:43.11#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.203.07:34:43.11#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.203.07:34:43.11#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.203.07:34:43.11#ibcon#ireg 7 cls_cnt 0 2006.203.07:34:43.11#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.203.07:34:43.23#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.203.07:34:43.23#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.203.07:34:43.23#ibcon#enter wrdev, iclass 11, count 0 2006.203.07:34:43.23#ibcon#first serial, iclass 11, count 0 2006.203.07:34:43.23#ibcon#enter sib2, iclass 11, count 0 2006.203.07:34:43.23#ibcon#flushed, iclass 11, count 0 2006.203.07:34:43.23#ibcon#about to write, iclass 11, count 0 2006.203.07:34:43.23#ibcon#wrote, iclass 11, count 0 2006.203.07:34:43.23#ibcon#about to read 3, iclass 11, count 0 2006.203.07:34:43.25#ibcon#read 3, iclass 11, count 0 2006.203.07:34:43.25#ibcon#about to read 4, iclass 11, count 0 2006.203.07:34:43.25#ibcon#read 4, iclass 11, count 0 2006.203.07:34:43.25#ibcon#about to read 5, iclass 11, count 0 2006.203.07:34:43.25#ibcon#read 5, iclass 11, count 0 2006.203.07:34:43.25#ibcon#about to read 6, iclass 11, count 0 2006.203.07:34:43.25#ibcon#read 6, iclass 11, count 0 2006.203.07:34:43.25#ibcon#end of sib2, iclass 11, count 0 2006.203.07:34:43.25#ibcon#*mode == 0, iclass 11, count 0 2006.203.07:34:43.25#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.203.07:34:43.25#ibcon#[27=USB\r\n] 2006.203.07:34:43.25#ibcon#*before write, iclass 11, count 0 2006.203.07:34:43.25#ibcon#enter sib2, iclass 11, count 0 2006.203.07:34:43.25#ibcon#flushed, iclass 11, count 0 2006.203.07:34:43.25#ibcon#about to write, iclass 11, count 0 2006.203.07:34:43.25#ibcon#wrote, iclass 11, count 0 2006.203.07:34:43.25#ibcon#about to read 3, iclass 11, count 0 2006.203.07:34:43.28#ibcon#read 3, iclass 11, count 0 2006.203.07:34:43.28#ibcon#about to read 4, iclass 11, count 0 2006.203.07:34:43.28#ibcon#read 4, iclass 11, count 0 2006.203.07:34:43.28#ibcon#about to read 5, iclass 11, count 0 2006.203.07:34:43.28#ibcon#read 5, iclass 11, count 0 2006.203.07:34:43.28#ibcon#about to read 6, iclass 11, count 0 2006.203.07:34:43.28#ibcon#read 6, iclass 11, count 0 2006.203.07:34:43.28#ibcon#end of sib2, iclass 11, count 0 2006.203.07:34:43.28#ibcon#*after write, iclass 11, count 0 2006.203.07:34:43.28#ibcon#*before return 0, iclass 11, count 0 2006.203.07:34:43.28#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.203.07:34:43.28#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.203.07:34:43.28#ibcon#about to clear, iclass 11 cls_cnt 0 2006.203.07:34:43.28#ibcon#cleared, iclass 11 cls_cnt 0 2006.203.07:34:43.28$vc4f8/vblo=6,752.99 2006.203.07:34:43.28#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.203.07:34:43.28#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.203.07:34:43.28#ibcon#ireg 17 cls_cnt 0 2006.203.07:34:43.28#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.203.07:34:43.28#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.203.07:34:43.28#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.203.07:34:43.28#ibcon#enter wrdev, iclass 13, count 0 2006.203.07:34:43.28#ibcon#first serial, iclass 13, count 0 2006.203.07:34:43.28#ibcon#enter sib2, iclass 13, count 0 2006.203.07:34:43.28#ibcon#flushed, iclass 13, count 0 2006.203.07:34:43.28#ibcon#about to write, iclass 13, count 0 2006.203.07:34:43.28#ibcon#wrote, iclass 13, count 0 2006.203.07:34:43.28#ibcon#about to read 3, iclass 13, count 0 2006.203.07:34:43.30#ibcon#read 3, iclass 13, count 0 2006.203.07:34:43.30#ibcon#about to read 4, iclass 13, count 0 2006.203.07:34:43.30#ibcon#read 4, iclass 13, count 0 2006.203.07:34:43.30#ibcon#about to read 5, iclass 13, count 0 2006.203.07:34:43.30#ibcon#read 5, iclass 13, count 0 2006.203.07:34:43.30#ibcon#about to read 6, iclass 13, count 0 2006.203.07:34:43.30#ibcon#read 6, iclass 13, count 0 2006.203.07:34:43.30#ibcon#end of sib2, iclass 13, count 0 2006.203.07:34:43.30#ibcon#*mode == 0, iclass 13, count 0 2006.203.07:34:43.30#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.203.07:34:43.30#ibcon#[28=FRQ=06,752.99\r\n] 2006.203.07:34:43.30#ibcon#*before write, iclass 13, count 0 2006.203.07:34:43.30#ibcon#enter sib2, iclass 13, count 0 2006.203.07:34:43.30#ibcon#flushed, iclass 13, count 0 2006.203.07:34:43.30#ibcon#about to write, iclass 13, count 0 2006.203.07:34:43.30#ibcon#wrote, iclass 13, count 0 2006.203.07:34:43.30#ibcon#about to read 3, iclass 13, count 0 2006.203.07:34:43.34#ibcon#read 3, iclass 13, count 0 2006.203.07:34:43.34#ibcon#about to read 4, iclass 13, count 0 2006.203.07:34:43.34#ibcon#read 4, iclass 13, count 0 2006.203.07:34:43.34#ibcon#about to read 5, iclass 13, count 0 2006.203.07:34:43.34#ibcon#read 5, iclass 13, count 0 2006.203.07:34:43.34#ibcon#about to read 6, iclass 13, count 0 2006.203.07:34:43.34#ibcon#read 6, iclass 13, count 0 2006.203.07:34:43.34#ibcon#end of sib2, iclass 13, count 0 2006.203.07:34:43.34#ibcon#*after write, iclass 13, count 0 2006.203.07:34:43.34#ibcon#*before return 0, iclass 13, count 0 2006.203.07:34:43.34#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.203.07:34:43.34#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.203.07:34:43.34#ibcon#about to clear, iclass 13 cls_cnt 0 2006.203.07:34:43.34#ibcon#cleared, iclass 13 cls_cnt 0 2006.203.07:34:43.34$vc4f8/vb=6,4 2006.203.07:34:43.34#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.203.07:34:43.34#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.203.07:34:43.34#ibcon#ireg 11 cls_cnt 2 2006.203.07:34:43.34#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.203.07:34:43.41#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.203.07:34:43.41#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.203.07:34:43.41#ibcon#enter wrdev, iclass 15, count 2 2006.203.07:34:43.41#ibcon#first serial, iclass 15, count 2 2006.203.07:34:43.41#ibcon#enter sib2, iclass 15, count 2 2006.203.07:34:43.41#ibcon#flushed, iclass 15, count 2 2006.203.07:34:43.41#ibcon#about to write, iclass 15, count 2 2006.203.07:34:43.41#ibcon#wrote, iclass 15, count 2 2006.203.07:34:43.41#ibcon#about to read 3, iclass 15, count 2 2006.203.07:34:43.42#ibcon#read 3, iclass 15, count 2 2006.203.07:34:43.42#ibcon#about to read 4, iclass 15, count 2 2006.203.07:34:43.42#ibcon#read 4, iclass 15, count 2 2006.203.07:34:43.42#ibcon#about to read 5, iclass 15, count 2 2006.203.07:34:43.42#ibcon#read 5, iclass 15, count 2 2006.203.07:34:43.42#ibcon#about to read 6, iclass 15, count 2 2006.203.07:34:43.42#ibcon#read 6, iclass 15, count 2 2006.203.07:34:43.42#ibcon#end of sib2, iclass 15, count 2 2006.203.07:34:43.42#ibcon#*mode == 0, iclass 15, count 2 2006.203.07:34:43.42#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.203.07:34:43.42#ibcon#[27=AT06-04\r\n] 2006.203.07:34:43.42#ibcon#*before write, iclass 15, count 2 2006.203.07:34:43.42#ibcon#enter sib2, iclass 15, count 2 2006.203.07:34:43.42#ibcon#flushed, iclass 15, count 2 2006.203.07:34:43.42#ibcon#about to write, iclass 15, count 2 2006.203.07:34:43.42#ibcon#wrote, iclass 15, count 2 2006.203.07:34:43.42#ibcon#about to read 3, iclass 15, count 2 2006.203.07:34:43.45#ibcon#read 3, iclass 15, count 2 2006.203.07:34:43.45#ibcon#about to read 4, iclass 15, count 2 2006.203.07:34:43.45#ibcon#read 4, iclass 15, count 2 2006.203.07:34:43.45#ibcon#about to read 5, iclass 15, count 2 2006.203.07:34:43.45#ibcon#read 5, iclass 15, count 2 2006.203.07:34:43.45#ibcon#about to read 6, iclass 15, count 2 2006.203.07:34:43.45#ibcon#read 6, iclass 15, count 2 2006.203.07:34:43.45#ibcon#end of sib2, iclass 15, count 2 2006.203.07:34:43.45#ibcon#*after write, iclass 15, count 2 2006.203.07:34:43.45#ibcon#*before return 0, iclass 15, count 2 2006.203.07:34:43.45#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.203.07:34:43.45#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.203.07:34:43.45#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.203.07:34:43.45#ibcon#ireg 7 cls_cnt 0 2006.203.07:34:43.45#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.203.07:34:43.57#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.203.07:34:43.57#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.203.07:34:43.57#ibcon#enter wrdev, iclass 15, count 0 2006.203.07:34:43.57#ibcon#first serial, iclass 15, count 0 2006.203.07:34:43.57#ibcon#enter sib2, iclass 15, count 0 2006.203.07:34:43.57#ibcon#flushed, iclass 15, count 0 2006.203.07:34:43.57#ibcon#about to write, iclass 15, count 0 2006.203.07:34:43.57#ibcon#wrote, iclass 15, count 0 2006.203.07:34:43.57#ibcon#about to read 3, iclass 15, count 0 2006.203.07:34:43.59#ibcon#read 3, iclass 15, count 0 2006.203.07:34:43.59#ibcon#about to read 4, iclass 15, count 0 2006.203.07:34:43.59#ibcon#read 4, iclass 15, count 0 2006.203.07:34:43.59#ibcon#about to read 5, iclass 15, count 0 2006.203.07:34:43.59#ibcon#read 5, iclass 15, count 0 2006.203.07:34:43.59#ibcon#about to read 6, iclass 15, count 0 2006.203.07:34:43.59#ibcon#read 6, iclass 15, count 0 2006.203.07:34:43.59#ibcon#end of sib2, iclass 15, count 0 2006.203.07:34:43.59#ibcon#*mode == 0, iclass 15, count 0 2006.203.07:34:43.59#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.203.07:34:43.59#ibcon#[27=USB\r\n] 2006.203.07:34:43.59#ibcon#*before write, iclass 15, count 0 2006.203.07:34:43.59#ibcon#enter sib2, iclass 15, count 0 2006.203.07:34:43.59#ibcon#flushed, iclass 15, count 0 2006.203.07:34:43.59#ibcon#about to write, iclass 15, count 0 2006.203.07:34:43.59#ibcon#wrote, iclass 15, count 0 2006.203.07:34:43.59#ibcon#about to read 3, iclass 15, count 0 2006.203.07:34:43.62#ibcon#read 3, iclass 15, count 0 2006.203.07:34:43.62#ibcon#about to read 4, iclass 15, count 0 2006.203.07:34:43.62#ibcon#read 4, iclass 15, count 0 2006.203.07:34:43.62#ibcon#about to read 5, iclass 15, count 0 2006.203.07:34:43.62#ibcon#read 5, iclass 15, count 0 2006.203.07:34:43.62#ibcon#about to read 6, iclass 15, count 0 2006.203.07:34:43.62#ibcon#read 6, iclass 15, count 0 2006.203.07:34:43.62#ibcon#end of sib2, iclass 15, count 0 2006.203.07:34:43.62#ibcon#*after write, iclass 15, count 0 2006.203.07:34:43.62#ibcon#*before return 0, iclass 15, count 0 2006.203.07:34:43.62#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.203.07:34:43.62#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.203.07:34:43.62#ibcon#about to clear, iclass 15 cls_cnt 0 2006.203.07:34:43.62#ibcon#cleared, iclass 15 cls_cnt 0 2006.203.07:34:43.62$vc4f8/vabw=wide 2006.203.07:34:43.62#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.203.07:34:43.62#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.203.07:34:43.62#ibcon#ireg 8 cls_cnt 0 2006.203.07:34:43.62#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.203.07:34:43.62#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.203.07:34:43.62#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.203.07:34:43.62#ibcon#enter wrdev, iclass 17, count 0 2006.203.07:34:43.62#ibcon#first serial, iclass 17, count 0 2006.203.07:34:43.62#ibcon#enter sib2, iclass 17, count 0 2006.203.07:34:43.62#ibcon#flushed, iclass 17, count 0 2006.203.07:34:43.62#ibcon#about to write, iclass 17, count 0 2006.203.07:34:43.62#ibcon#wrote, iclass 17, count 0 2006.203.07:34:43.62#ibcon#about to read 3, iclass 17, count 0 2006.203.07:34:43.64#ibcon#read 3, iclass 17, count 0 2006.203.07:34:43.64#ibcon#about to read 4, iclass 17, count 0 2006.203.07:34:43.64#ibcon#read 4, iclass 17, count 0 2006.203.07:34:43.64#ibcon#about to read 5, iclass 17, count 0 2006.203.07:34:43.64#ibcon#read 5, iclass 17, count 0 2006.203.07:34:43.64#ibcon#about to read 6, iclass 17, count 0 2006.203.07:34:43.64#ibcon#read 6, iclass 17, count 0 2006.203.07:34:43.64#ibcon#end of sib2, iclass 17, count 0 2006.203.07:34:43.64#ibcon#*mode == 0, iclass 17, count 0 2006.203.07:34:43.64#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.203.07:34:43.64#ibcon#[25=BW32\r\n] 2006.203.07:34:43.64#ibcon#*before write, iclass 17, count 0 2006.203.07:34:43.64#ibcon#enter sib2, iclass 17, count 0 2006.203.07:34:43.64#ibcon#flushed, iclass 17, count 0 2006.203.07:34:43.64#ibcon#about to write, iclass 17, count 0 2006.203.07:34:43.64#ibcon#wrote, iclass 17, count 0 2006.203.07:34:43.64#ibcon#about to read 3, iclass 17, count 0 2006.203.07:34:43.67#ibcon#read 3, iclass 17, count 0 2006.203.07:34:43.67#ibcon#about to read 4, iclass 17, count 0 2006.203.07:34:43.67#ibcon#read 4, iclass 17, count 0 2006.203.07:34:43.67#ibcon#about to read 5, iclass 17, count 0 2006.203.07:34:43.67#ibcon#read 5, iclass 17, count 0 2006.203.07:34:43.67#ibcon#about to read 6, iclass 17, count 0 2006.203.07:34:43.67#ibcon#read 6, iclass 17, count 0 2006.203.07:34:43.67#ibcon#end of sib2, iclass 17, count 0 2006.203.07:34:43.67#ibcon#*after write, iclass 17, count 0 2006.203.07:34:43.67#ibcon#*before return 0, iclass 17, count 0 2006.203.07:34:43.67#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.203.07:34:43.67#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.203.07:34:43.67#ibcon#about to clear, iclass 17 cls_cnt 0 2006.203.07:34:43.67#ibcon#cleared, iclass 17 cls_cnt 0 2006.203.07:34:43.67$vc4f8/vbbw=wide 2006.203.07:34:43.67#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.203.07:34:43.67#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.203.07:34:43.67#ibcon#ireg 8 cls_cnt 0 2006.203.07:34:43.67#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.203.07:34:43.74#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.203.07:34:43.74#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.203.07:34:43.74#ibcon#enter wrdev, iclass 19, count 0 2006.203.07:34:43.74#ibcon#first serial, iclass 19, count 0 2006.203.07:34:43.74#ibcon#enter sib2, iclass 19, count 0 2006.203.07:34:43.74#ibcon#flushed, iclass 19, count 0 2006.203.07:34:43.74#ibcon#about to write, iclass 19, count 0 2006.203.07:34:43.74#ibcon#wrote, iclass 19, count 0 2006.203.07:34:43.74#ibcon#about to read 3, iclass 19, count 0 2006.203.07:34:43.76#ibcon#read 3, iclass 19, count 0 2006.203.07:34:43.76#ibcon#about to read 4, iclass 19, count 0 2006.203.07:34:43.76#ibcon#read 4, iclass 19, count 0 2006.203.07:34:43.76#ibcon#about to read 5, iclass 19, count 0 2006.203.07:34:43.76#ibcon#read 5, iclass 19, count 0 2006.203.07:34:43.76#ibcon#about to read 6, iclass 19, count 0 2006.203.07:34:43.76#ibcon#read 6, iclass 19, count 0 2006.203.07:34:43.76#ibcon#end of sib2, iclass 19, count 0 2006.203.07:34:43.76#ibcon#*mode == 0, iclass 19, count 0 2006.203.07:34:43.76#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.203.07:34:43.76#ibcon#[27=BW32\r\n] 2006.203.07:34:43.76#ibcon#*before write, iclass 19, count 0 2006.203.07:34:43.76#ibcon#enter sib2, iclass 19, count 0 2006.203.07:34:43.76#ibcon#flushed, iclass 19, count 0 2006.203.07:34:43.76#ibcon#about to write, iclass 19, count 0 2006.203.07:34:43.76#ibcon#wrote, iclass 19, count 0 2006.203.07:34:43.76#ibcon#about to read 3, iclass 19, count 0 2006.203.07:34:43.79#ibcon#read 3, iclass 19, count 0 2006.203.07:34:43.79#ibcon#about to read 4, iclass 19, count 0 2006.203.07:34:43.79#ibcon#read 4, iclass 19, count 0 2006.203.07:34:43.79#ibcon#about to read 5, iclass 19, count 0 2006.203.07:34:43.79#ibcon#read 5, iclass 19, count 0 2006.203.07:34:43.79#ibcon#about to read 6, iclass 19, count 0 2006.203.07:34:43.79#ibcon#read 6, iclass 19, count 0 2006.203.07:34:43.79#ibcon#end of sib2, iclass 19, count 0 2006.203.07:34:43.79#ibcon#*after write, iclass 19, count 0 2006.203.07:34:43.79#ibcon#*before return 0, iclass 19, count 0 2006.203.07:34:43.79#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.203.07:34:43.79#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.203.07:34:43.79#ibcon#about to clear, iclass 19 cls_cnt 0 2006.203.07:34:43.79#ibcon#cleared, iclass 19 cls_cnt 0 2006.203.07:34:43.79$4f8m12a/ifd4f 2006.203.07:34:43.79$ifd4f/lo= 2006.203.07:34:43.79$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.203.07:34:43.79$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.203.07:34:43.79$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.203.07:34:43.79$ifd4f/patch= 2006.203.07:34:43.80$ifd4f/patch=lo1,a1,a2,a3,a4 2006.203.07:34:43.80$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.203.07:34:43.80$ifd4f/patch=lo3,a5,a6,a7,a8 2006.203.07:34:43.80$4f8m12a/"form=m,16.000,1:2 2006.203.07:34:43.80$4f8m12a/"tpicd 2006.203.07:34:43.80$4f8m12a/echo=off 2006.203.07:34:43.80$4f8m12a/xlog=off 2006.203.07:34:43.80:!2006.203.07:35:10 2006.203.07:34:53.14#trakl#Source acquired 2006.203.07:34:55.14#flagr#flagr/antenna,acquired 2006.203.07:35:10.01:preob 2006.203.07:35:11.14/onsource/TRACKING 2006.203.07:35:11.14:!2006.203.07:35:20 2006.203.07:35:20.00:data_valid=on 2006.203.07:35:20.00:midob 2006.203.07:35:20.14/onsource/TRACKING 2006.203.07:35:20.14/wx/24.04,1001.0,98 2006.203.07:35:20.31/cable/+6.4596E-03 2006.203.07:35:21.40/va/01,08,usb,yes,29,31 2006.203.07:35:21.40/va/02,07,usb,yes,29,31 2006.203.07:35:21.40/va/03,08,usb,yes,22,22 2006.203.07:35:21.40/va/04,07,usb,yes,30,32 2006.203.07:35:21.40/va/05,07,usb,yes,32,34 2006.203.07:35:21.40/va/06,06,usb,yes,31,31 2006.203.07:35:21.40/va/07,07,usb,yes,28,27 2006.203.07:35:21.40/va/08,06,usb,yes,34,33 2006.203.07:35:21.63/valo/01,532.99,yes,locked 2006.203.07:35:21.63/valo/02,572.99,yes,locked 2006.203.07:35:21.63/valo/03,672.99,yes,locked 2006.203.07:35:21.63/valo/04,832.99,yes,locked 2006.203.07:35:21.63/valo/05,652.99,yes,locked 2006.203.07:35:21.63/valo/06,772.99,yes,locked 2006.203.07:35:21.63/valo/07,832.99,yes,locked 2006.203.07:35:21.63/valo/08,852.99,yes,locked 2006.203.07:35:22.72/vb/01,04,usb,yes,28,27 2006.203.07:35:22.72/vb/02,04,usb,yes,30,32 2006.203.07:35:22.72/vb/03,04,usb,yes,27,30 2006.203.07:35:22.72/vb/04,04,usb,yes,28,28 2006.203.07:35:22.72/vb/05,03,usb,yes,33,37 2006.203.07:35:22.72/vb/06,04,usb,yes,27,30 2006.203.07:35:22.72/vb/07,04,usb,yes,29,29 2006.203.07:35:22.72/vb/08,04,usb,yes,27,30 2006.203.07:35:22.96/vblo/01,632.99,yes,locked 2006.203.07:35:22.96/vblo/02,640.99,yes,locked 2006.203.07:35:22.96/vblo/03,656.99,yes,locked 2006.203.07:35:22.96/vblo/04,712.99,yes,locked 2006.203.07:35:22.96/vblo/05,744.99,yes,locked 2006.203.07:35:22.96/vblo/06,752.99,yes,locked 2006.203.07:35:22.96/vblo/07,734.99,yes,locked 2006.203.07:35:22.96/vblo/08,744.99,yes,locked 2006.203.07:35:23.11/vabw/8 2006.203.07:35:23.26/vbbw/8 2006.203.07:35:23.35/xfe/off,on,16.5 2006.203.07:35:23.74/ifatt/23,28,28,28 2006.203.07:35:24.07/fmout-gps/S +4.56E-07 2006.203.07:35:24.12:!2006.203.07:36:20 2006.203.07:36:20.01:data_valid=off 2006.203.07:36:20.02:postob 2006.203.07:36:20.21/cable/+6.4616E-03 2006.203.07:36:20.22/wx/24.02,1001.0,98 2006.203.07:36:21.07/fmout-gps/S +4.55E-07 2006.203.07:36:21.08:scan_name=203-0737,k06203,60 2006.203.07:36:21.08:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.203.07:36:21.14#flagr#flagr/antenna,new-source 2006.203.07:36:22.14:checkk5 2006.203.07:36:22.56/chk_autoobs//k5ts1/ autoobs is running! 2006.203.07:36:22.96/chk_autoobs//k5ts2/ autoobs is running! 2006.203.07:36:23.43/chk_autoobs//k5ts3/ autoobs is running! 2006.203.07:36:24.06/chk_autoobs//k5ts4/ autoobs is running! 2006.203.07:36:24.71/chk_obsdata//k5ts1/T2030735??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.07:36:25.37/chk_obsdata//k5ts2/T2030735??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.07:36:25.79/chk_obsdata//k5ts3/T2030735??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.07:36:26.23/chk_obsdata//k5ts4/T2030735??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.07:36:27.30/k5log//k5ts1_log_newline 2006.203.07:36:28.24/k5log//k5ts2_log_newline 2006.203.07:36:29.02/k5log//k5ts3_log_newline 2006.203.07:36:29.98/k5log//k5ts4_log_newline 2006.203.07:36:30.01/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.203.07:36:30.01:4f8m12a=1 2006.203.07:36:30.01$4f8m12a/echo=on 2006.203.07:36:30.01$4f8m12a/pcalon 2006.203.07:36:30.01$pcalon/"no phase cal control is implemented here 2006.203.07:36:30.01$4f8m12a/"tpicd=stop 2006.203.07:36:30.01$4f8m12a/vc4f8 2006.203.07:36:30.01$vc4f8/valo=1,532.99 2006.203.07:36:30.01#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.203.07:36:30.01#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.203.07:36:30.01#ibcon#ireg 17 cls_cnt 0 2006.203.07:36:30.01#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.203.07:36:30.01#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.203.07:36:30.01#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.203.07:36:30.01#ibcon#enter wrdev, iclass 26, count 0 2006.203.07:36:30.01#ibcon#first serial, iclass 26, count 0 2006.203.07:36:30.01#ibcon#enter sib2, iclass 26, count 0 2006.203.07:36:30.01#ibcon#flushed, iclass 26, count 0 2006.203.07:36:30.01#ibcon#about to write, iclass 26, count 0 2006.203.07:36:30.01#ibcon#wrote, iclass 26, count 0 2006.203.07:36:30.01#ibcon#about to read 3, iclass 26, count 0 2006.203.07:36:30.02#ibcon#read 3, iclass 26, count 0 2006.203.07:36:30.02#ibcon#about to read 4, iclass 26, count 0 2006.203.07:36:30.02#ibcon#read 4, iclass 26, count 0 2006.203.07:36:30.02#ibcon#about to read 5, iclass 26, count 0 2006.203.07:36:30.02#ibcon#read 5, iclass 26, count 0 2006.203.07:36:30.02#ibcon#about to read 6, iclass 26, count 0 2006.203.07:36:30.02#ibcon#read 6, iclass 26, count 0 2006.203.07:36:30.02#ibcon#end of sib2, iclass 26, count 0 2006.203.07:36:30.02#ibcon#*mode == 0, iclass 26, count 0 2006.203.07:36:30.02#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.203.07:36:30.02#ibcon#[26=FRQ=01,532.99\r\n] 2006.203.07:36:30.02#ibcon#*before write, iclass 26, count 0 2006.203.07:36:30.02#ibcon#enter sib2, iclass 26, count 0 2006.203.07:36:30.02#ibcon#flushed, iclass 26, count 0 2006.203.07:36:30.02#ibcon#about to write, iclass 26, count 0 2006.203.07:36:30.02#ibcon#wrote, iclass 26, count 0 2006.203.07:36:30.02#ibcon#about to read 3, iclass 26, count 0 2006.203.07:36:30.07#ibcon#read 3, iclass 26, count 0 2006.203.07:36:30.07#ibcon#about to read 4, iclass 26, count 0 2006.203.07:36:30.07#ibcon#read 4, iclass 26, count 0 2006.203.07:36:30.07#ibcon#about to read 5, iclass 26, count 0 2006.203.07:36:30.07#ibcon#read 5, iclass 26, count 0 2006.203.07:36:30.07#ibcon#about to read 6, iclass 26, count 0 2006.203.07:36:30.07#ibcon#read 6, iclass 26, count 0 2006.203.07:36:30.07#ibcon#end of sib2, iclass 26, count 0 2006.203.07:36:30.07#ibcon#*after write, iclass 26, count 0 2006.203.07:36:30.07#ibcon#*before return 0, iclass 26, count 0 2006.203.07:36:30.07#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.203.07:36:30.07#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.203.07:36:30.07#ibcon#about to clear, iclass 26 cls_cnt 0 2006.203.07:36:30.07#ibcon#cleared, iclass 26 cls_cnt 0 2006.203.07:36:30.07$vc4f8/va=1,8 2006.203.07:36:30.07#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.203.07:36:30.07#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.203.07:36:30.07#ibcon#ireg 11 cls_cnt 2 2006.203.07:36:30.07#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.203.07:36:30.07#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.203.07:36:30.07#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.203.07:36:30.07#ibcon#enter wrdev, iclass 28, count 2 2006.203.07:36:30.07#ibcon#first serial, iclass 28, count 2 2006.203.07:36:30.07#ibcon#enter sib2, iclass 28, count 2 2006.203.07:36:30.07#ibcon#flushed, iclass 28, count 2 2006.203.07:36:30.07#ibcon#about to write, iclass 28, count 2 2006.203.07:36:30.07#ibcon#wrote, iclass 28, count 2 2006.203.07:36:30.07#ibcon#about to read 3, iclass 28, count 2 2006.203.07:36:30.09#ibcon#read 3, iclass 28, count 2 2006.203.07:36:30.09#ibcon#about to read 4, iclass 28, count 2 2006.203.07:36:30.09#ibcon#read 4, iclass 28, count 2 2006.203.07:36:30.09#ibcon#about to read 5, iclass 28, count 2 2006.203.07:36:30.09#ibcon#read 5, iclass 28, count 2 2006.203.07:36:30.09#ibcon#about to read 6, iclass 28, count 2 2006.203.07:36:30.09#ibcon#read 6, iclass 28, count 2 2006.203.07:36:30.09#ibcon#end of sib2, iclass 28, count 2 2006.203.07:36:30.09#ibcon#*mode == 0, iclass 28, count 2 2006.203.07:36:30.09#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.203.07:36:30.09#ibcon#[25=AT01-08\r\n] 2006.203.07:36:30.09#ibcon#*before write, iclass 28, count 2 2006.203.07:36:30.09#ibcon#enter sib2, iclass 28, count 2 2006.203.07:36:30.09#ibcon#flushed, iclass 28, count 2 2006.203.07:36:30.09#ibcon#about to write, iclass 28, count 2 2006.203.07:36:30.09#ibcon#wrote, iclass 28, count 2 2006.203.07:36:30.09#ibcon#about to read 3, iclass 28, count 2 2006.203.07:36:30.12#ibcon#read 3, iclass 28, count 2 2006.203.07:36:30.12#ibcon#about to read 4, iclass 28, count 2 2006.203.07:36:30.12#ibcon#read 4, iclass 28, count 2 2006.203.07:36:30.12#ibcon#about to read 5, iclass 28, count 2 2006.203.07:36:30.12#ibcon#read 5, iclass 28, count 2 2006.203.07:36:30.12#ibcon#about to read 6, iclass 28, count 2 2006.203.07:36:30.12#ibcon#read 6, iclass 28, count 2 2006.203.07:36:30.12#ibcon#end of sib2, iclass 28, count 2 2006.203.07:36:30.12#ibcon#*after write, iclass 28, count 2 2006.203.07:36:30.12#ibcon#*before return 0, iclass 28, count 2 2006.203.07:36:30.12#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.203.07:36:30.12#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.203.07:36:30.12#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.203.07:36:30.12#ibcon#ireg 7 cls_cnt 0 2006.203.07:36:30.12#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.203.07:36:30.21#abcon#<5=/06 2.4 4.4 24.02 981001.0\r\n> 2006.203.07:36:30.23#abcon#{5=INTERFACE CLEAR} 2006.203.07:36:30.24#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.203.07:36:30.24#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.203.07:36:30.24#ibcon#enter wrdev, iclass 28, count 0 2006.203.07:36:30.24#ibcon#first serial, iclass 28, count 0 2006.203.07:36:30.24#ibcon#enter sib2, iclass 28, count 0 2006.203.07:36:30.24#ibcon#flushed, iclass 28, count 0 2006.203.07:36:30.24#ibcon#about to write, iclass 28, count 0 2006.203.07:36:30.24#ibcon#wrote, iclass 28, count 0 2006.203.07:36:30.24#ibcon#about to read 3, iclass 28, count 0 2006.203.07:36:30.26#ibcon#read 3, iclass 28, count 0 2006.203.07:36:30.26#ibcon#about to read 4, iclass 28, count 0 2006.203.07:36:30.26#ibcon#read 4, iclass 28, count 0 2006.203.07:36:30.26#ibcon#about to read 5, iclass 28, count 0 2006.203.07:36:30.26#ibcon#read 5, iclass 28, count 0 2006.203.07:36:30.26#ibcon#about to read 6, iclass 28, count 0 2006.203.07:36:30.26#ibcon#read 6, iclass 28, count 0 2006.203.07:36:30.26#ibcon#end of sib2, iclass 28, count 0 2006.203.07:36:30.26#ibcon#*mode == 0, iclass 28, count 0 2006.203.07:36:30.26#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.203.07:36:30.26#ibcon#[25=USB\r\n] 2006.203.07:36:30.26#ibcon#*before write, iclass 28, count 0 2006.203.07:36:30.26#ibcon#enter sib2, iclass 28, count 0 2006.203.07:36:30.26#ibcon#flushed, iclass 28, count 0 2006.203.07:36:30.26#ibcon#about to write, iclass 28, count 0 2006.203.07:36:30.26#ibcon#wrote, iclass 28, count 0 2006.203.07:36:30.26#ibcon#about to read 3, iclass 28, count 0 2006.203.07:36:30.29#abcon#[5=S1D000X0/0*\r\n] 2006.203.07:36:30.29#ibcon#read 3, iclass 28, count 0 2006.203.07:36:30.29#ibcon#about to read 4, iclass 28, count 0 2006.203.07:36:30.29#ibcon#read 4, iclass 28, count 0 2006.203.07:36:30.29#ibcon#about to read 5, iclass 28, count 0 2006.203.07:36:30.29#ibcon#read 5, iclass 28, count 0 2006.203.07:36:30.29#ibcon#about to read 6, iclass 28, count 0 2006.203.07:36:30.29#ibcon#read 6, iclass 28, count 0 2006.203.07:36:30.29#ibcon#end of sib2, iclass 28, count 0 2006.203.07:36:30.29#ibcon#*after write, iclass 28, count 0 2006.203.07:36:30.29#ibcon#*before return 0, iclass 28, count 0 2006.203.07:36:30.29#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.203.07:36:30.29#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.203.07:36:30.29#ibcon#about to clear, iclass 28 cls_cnt 0 2006.203.07:36:30.29#ibcon#cleared, iclass 28 cls_cnt 0 2006.203.07:36:30.29$vc4f8/valo=2,572.99 2006.203.07:36:30.29#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.203.07:36:30.29#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.203.07:36:30.29#ibcon#ireg 17 cls_cnt 0 2006.203.07:36:30.29#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.203.07:36:30.29#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.203.07:36:30.29#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.203.07:36:30.29#ibcon#enter wrdev, iclass 34, count 0 2006.203.07:36:30.29#ibcon#first serial, iclass 34, count 0 2006.203.07:36:30.29#ibcon#enter sib2, iclass 34, count 0 2006.203.07:36:30.29#ibcon#flushed, iclass 34, count 0 2006.203.07:36:30.29#ibcon#about to write, iclass 34, count 0 2006.203.07:36:30.29#ibcon#wrote, iclass 34, count 0 2006.203.07:36:30.29#ibcon#about to read 3, iclass 34, count 0 2006.203.07:36:30.32#ibcon#read 3, iclass 34, count 0 2006.203.07:36:30.32#ibcon#about to read 4, iclass 34, count 0 2006.203.07:36:30.32#ibcon#read 4, iclass 34, count 0 2006.203.07:36:30.32#ibcon#about to read 5, iclass 34, count 0 2006.203.07:36:30.32#ibcon#read 5, iclass 34, count 0 2006.203.07:36:30.32#ibcon#about to read 6, iclass 34, count 0 2006.203.07:36:30.32#ibcon#read 6, iclass 34, count 0 2006.203.07:36:30.32#ibcon#end of sib2, iclass 34, count 0 2006.203.07:36:30.32#ibcon#*mode == 0, iclass 34, count 0 2006.203.07:36:30.32#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.203.07:36:30.32#ibcon#[26=FRQ=02,572.99\r\n] 2006.203.07:36:30.32#ibcon#*before write, iclass 34, count 0 2006.203.07:36:30.32#ibcon#enter sib2, iclass 34, count 0 2006.203.07:36:30.32#ibcon#flushed, iclass 34, count 0 2006.203.07:36:30.32#ibcon#about to write, iclass 34, count 0 2006.203.07:36:30.32#ibcon#wrote, iclass 34, count 0 2006.203.07:36:30.32#ibcon#about to read 3, iclass 34, count 0 2006.203.07:36:30.36#ibcon#read 3, iclass 34, count 0 2006.203.07:36:30.36#ibcon#about to read 4, iclass 34, count 0 2006.203.07:36:30.36#ibcon#read 4, iclass 34, count 0 2006.203.07:36:30.36#ibcon#about to read 5, iclass 34, count 0 2006.203.07:36:30.36#ibcon#read 5, iclass 34, count 0 2006.203.07:36:30.36#ibcon#about to read 6, iclass 34, count 0 2006.203.07:36:30.36#ibcon#read 6, iclass 34, count 0 2006.203.07:36:30.36#ibcon#end of sib2, iclass 34, count 0 2006.203.07:36:30.36#ibcon#*after write, iclass 34, count 0 2006.203.07:36:30.36#ibcon#*before return 0, iclass 34, count 0 2006.203.07:36:30.36#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.203.07:36:30.36#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.203.07:36:30.36#ibcon#about to clear, iclass 34 cls_cnt 0 2006.203.07:36:30.36#ibcon#cleared, iclass 34 cls_cnt 0 2006.203.07:36:30.36$vc4f8/va=2,7 2006.203.07:36:30.36#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.203.07:36:30.36#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.203.07:36:30.36#ibcon#ireg 11 cls_cnt 2 2006.203.07:36:30.36#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.203.07:36:30.40#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.203.07:36:30.40#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.203.07:36:30.40#ibcon#enter wrdev, iclass 36, count 2 2006.203.07:36:30.40#ibcon#first serial, iclass 36, count 2 2006.203.07:36:30.40#ibcon#enter sib2, iclass 36, count 2 2006.203.07:36:30.40#ibcon#flushed, iclass 36, count 2 2006.203.07:36:30.40#ibcon#about to write, iclass 36, count 2 2006.203.07:36:30.40#ibcon#wrote, iclass 36, count 2 2006.203.07:36:30.40#ibcon#about to read 3, iclass 36, count 2 2006.203.07:36:30.43#ibcon#read 3, iclass 36, count 2 2006.203.07:36:30.43#ibcon#about to read 4, iclass 36, count 2 2006.203.07:36:30.43#ibcon#read 4, iclass 36, count 2 2006.203.07:36:30.43#ibcon#about to read 5, iclass 36, count 2 2006.203.07:36:30.43#ibcon#read 5, iclass 36, count 2 2006.203.07:36:30.43#ibcon#about to read 6, iclass 36, count 2 2006.203.07:36:30.43#ibcon#read 6, iclass 36, count 2 2006.203.07:36:30.43#ibcon#end of sib2, iclass 36, count 2 2006.203.07:36:30.43#ibcon#*mode == 0, iclass 36, count 2 2006.203.07:36:30.43#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.203.07:36:30.43#ibcon#[25=AT02-07\r\n] 2006.203.07:36:30.43#ibcon#*before write, iclass 36, count 2 2006.203.07:36:30.43#ibcon#enter sib2, iclass 36, count 2 2006.203.07:36:30.43#ibcon#flushed, iclass 36, count 2 2006.203.07:36:30.43#ibcon#about to write, iclass 36, count 2 2006.203.07:36:30.43#ibcon#wrote, iclass 36, count 2 2006.203.07:36:30.43#ibcon#about to read 3, iclass 36, count 2 2006.203.07:36:30.46#ibcon#read 3, iclass 36, count 2 2006.203.07:36:30.46#ibcon#about to read 4, iclass 36, count 2 2006.203.07:36:30.46#ibcon#read 4, iclass 36, count 2 2006.203.07:36:30.46#ibcon#about to read 5, iclass 36, count 2 2006.203.07:36:30.46#ibcon#read 5, iclass 36, count 2 2006.203.07:36:30.46#ibcon#about to read 6, iclass 36, count 2 2006.203.07:36:30.46#ibcon#read 6, iclass 36, count 2 2006.203.07:36:30.46#ibcon#end of sib2, iclass 36, count 2 2006.203.07:36:30.46#ibcon#*after write, iclass 36, count 2 2006.203.07:36:30.46#ibcon#*before return 0, iclass 36, count 2 2006.203.07:36:30.46#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.203.07:36:30.46#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.203.07:36:30.46#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.203.07:36:30.46#ibcon#ireg 7 cls_cnt 0 2006.203.07:36:30.46#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.203.07:36:30.58#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.203.07:36:30.58#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.203.07:36:30.58#ibcon#enter wrdev, iclass 36, count 0 2006.203.07:36:30.58#ibcon#first serial, iclass 36, count 0 2006.203.07:36:30.58#ibcon#enter sib2, iclass 36, count 0 2006.203.07:36:30.58#ibcon#flushed, iclass 36, count 0 2006.203.07:36:30.58#ibcon#about to write, iclass 36, count 0 2006.203.07:36:30.58#ibcon#wrote, iclass 36, count 0 2006.203.07:36:30.58#ibcon#about to read 3, iclass 36, count 0 2006.203.07:36:30.60#ibcon#read 3, iclass 36, count 0 2006.203.07:36:30.60#ibcon#about to read 4, iclass 36, count 0 2006.203.07:36:30.60#ibcon#read 4, iclass 36, count 0 2006.203.07:36:30.60#ibcon#about to read 5, iclass 36, count 0 2006.203.07:36:30.60#ibcon#read 5, iclass 36, count 0 2006.203.07:36:30.60#ibcon#about to read 6, iclass 36, count 0 2006.203.07:36:30.60#ibcon#read 6, iclass 36, count 0 2006.203.07:36:30.60#ibcon#end of sib2, iclass 36, count 0 2006.203.07:36:30.60#ibcon#*mode == 0, iclass 36, count 0 2006.203.07:36:30.60#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.203.07:36:30.60#ibcon#[25=USB\r\n] 2006.203.07:36:30.60#ibcon#*before write, iclass 36, count 0 2006.203.07:36:30.60#ibcon#enter sib2, iclass 36, count 0 2006.203.07:36:30.60#ibcon#flushed, iclass 36, count 0 2006.203.07:36:30.60#ibcon#about to write, iclass 36, count 0 2006.203.07:36:30.60#ibcon#wrote, iclass 36, count 0 2006.203.07:36:30.60#ibcon#about to read 3, iclass 36, count 0 2006.203.07:36:30.63#ibcon#read 3, iclass 36, count 0 2006.203.07:36:30.63#ibcon#about to read 4, iclass 36, count 0 2006.203.07:36:30.63#ibcon#read 4, iclass 36, count 0 2006.203.07:36:30.63#ibcon#about to read 5, iclass 36, count 0 2006.203.07:36:30.63#ibcon#read 5, iclass 36, count 0 2006.203.07:36:30.63#ibcon#about to read 6, iclass 36, count 0 2006.203.07:36:30.63#ibcon#read 6, iclass 36, count 0 2006.203.07:36:30.63#ibcon#end of sib2, iclass 36, count 0 2006.203.07:36:30.63#ibcon#*after write, iclass 36, count 0 2006.203.07:36:30.63#ibcon#*before return 0, iclass 36, count 0 2006.203.07:36:30.63#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.203.07:36:30.63#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.203.07:36:30.63#ibcon#about to clear, iclass 36 cls_cnt 0 2006.203.07:36:30.63#ibcon#cleared, iclass 36 cls_cnt 0 2006.203.07:36:30.63$vc4f8/valo=3,672.99 2006.203.07:36:30.63#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.203.07:36:30.63#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.203.07:36:30.63#ibcon#ireg 17 cls_cnt 0 2006.203.07:36:30.63#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.203.07:36:30.63#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.203.07:36:30.63#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.203.07:36:30.63#ibcon#enter wrdev, iclass 38, count 0 2006.203.07:36:30.63#ibcon#first serial, iclass 38, count 0 2006.203.07:36:30.63#ibcon#enter sib2, iclass 38, count 0 2006.203.07:36:30.63#ibcon#flushed, iclass 38, count 0 2006.203.07:36:30.63#ibcon#about to write, iclass 38, count 0 2006.203.07:36:30.63#ibcon#wrote, iclass 38, count 0 2006.203.07:36:30.63#ibcon#about to read 3, iclass 38, count 0 2006.203.07:36:30.66#ibcon#read 3, iclass 38, count 0 2006.203.07:36:30.66#ibcon#about to read 4, iclass 38, count 0 2006.203.07:36:30.66#ibcon#read 4, iclass 38, count 0 2006.203.07:36:30.66#ibcon#about to read 5, iclass 38, count 0 2006.203.07:36:30.66#ibcon#read 5, iclass 38, count 0 2006.203.07:36:30.66#ibcon#about to read 6, iclass 38, count 0 2006.203.07:36:30.66#ibcon#read 6, iclass 38, count 0 2006.203.07:36:30.66#ibcon#end of sib2, iclass 38, count 0 2006.203.07:36:30.66#ibcon#*mode == 0, iclass 38, count 0 2006.203.07:36:30.66#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.203.07:36:30.66#ibcon#[26=FRQ=03,672.99\r\n] 2006.203.07:36:30.66#ibcon#*before write, iclass 38, count 0 2006.203.07:36:30.66#ibcon#enter sib2, iclass 38, count 0 2006.203.07:36:30.66#ibcon#flushed, iclass 38, count 0 2006.203.07:36:30.66#ibcon#about to write, iclass 38, count 0 2006.203.07:36:30.66#ibcon#wrote, iclass 38, count 0 2006.203.07:36:30.66#ibcon#about to read 3, iclass 38, count 0 2006.203.07:36:30.70#ibcon#read 3, iclass 38, count 0 2006.203.07:36:30.70#ibcon#about to read 4, iclass 38, count 0 2006.203.07:36:30.70#ibcon#read 4, iclass 38, count 0 2006.203.07:36:30.70#ibcon#about to read 5, iclass 38, count 0 2006.203.07:36:30.70#ibcon#read 5, iclass 38, count 0 2006.203.07:36:30.70#ibcon#about to read 6, iclass 38, count 0 2006.203.07:36:30.70#ibcon#read 6, iclass 38, count 0 2006.203.07:36:30.70#ibcon#end of sib2, iclass 38, count 0 2006.203.07:36:30.70#ibcon#*after write, iclass 38, count 0 2006.203.07:36:30.70#ibcon#*before return 0, iclass 38, count 0 2006.203.07:36:30.70#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.203.07:36:30.70#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.203.07:36:30.70#ibcon#about to clear, iclass 38 cls_cnt 0 2006.203.07:36:30.70#ibcon#cleared, iclass 38 cls_cnt 0 2006.203.07:36:30.70$vc4f8/va=3,8 2006.203.07:36:30.70#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.203.07:36:30.70#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.203.07:36:30.70#ibcon#ireg 11 cls_cnt 2 2006.203.07:36:30.70#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.203.07:36:30.76#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.203.07:36:30.76#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.203.07:36:30.76#ibcon#enter wrdev, iclass 40, count 2 2006.203.07:36:30.76#ibcon#first serial, iclass 40, count 2 2006.203.07:36:30.76#ibcon#enter sib2, iclass 40, count 2 2006.203.07:36:30.76#ibcon#flushed, iclass 40, count 2 2006.203.07:36:30.76#ibcon#about to write, iclass 40, count 2 2006.203.07:36:30.76#ibcon#wrote, iclass 40, count 2 2006.203.07:36:30.76#ibcon#about to read 3, iclass 40, count 2 2006.203.07:36:30.77#ibcon#read 3, iclass 40, count 2 2006.203.07:36:30.77#ibcon#about to read 4, iclass 40, count 2 2006.203.07:36:30.77#ibcon#read 4, iclass 40, count 2 2006.203.07:36:30.77#ibcon#about to read 5, iclass 40, count 2 2006.203.07:36:30.77#ibcon#read 5, iclass 40, count 2 2006.203.07:36:30.77#ibcon#about to read 6, iclass 40, count 2 2006.203.07:36:30.77#ibcon#read 6, iclass 40, count 2 2006.203.07:36:30.77#ibcon#end of sib2, iclass 40, count 2 2006.203.07:36:30.77#ibcon#*mode == 0, iclass 40, count 2 2006.203.07:36:30.77#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.203.07:36:30.77#ibcon#[25=AT03-08\r\n] 2006.203.07:36:30.77#ibcon#*before write, iclass 40, count 2 2006.203.07:36:30.77#ibcon#enter sib2, iclass 40, count 2 2006.203.07:36:30.77#ibcon#flushed, iclass 40, count 2 2006.203.07:36:30.77#ibcon#about to write, iclass 40, count 2 2006.203.07:36:30.77#ibcon#wrote, iclass 40, count 2 2006.203.07:36:30.77#ibcon#about to read 3, iclass 40, count 2 2006.203.07:36:30.80#ibcon#read 3, iclass 40, count 2 2006.203.07:36:30.80#ibcon#about to read 4, iclass 40, count 2 2006.203.07:36:30.80#ibcon#read 4, iclass 40, count 2 2006.203.07:36:30.80#ibcon#about to read 5, iclass 40, count 2 2006.203.07:36:30.80#ibcon#read 5, iclass 40, count 2 2006.203.07:36:30.80#ibcon#about to read 6, iclass 40, count 2 2006.203.07:36:30.80#ibcon#read 6, iclass 40, count 2 2006.203.07:36:30.80#ibcon#end of sib2, iclass 40, count 2 2006.203.07:36:30.80#ibcon#*after write, iclass 40, count 2 2006.203.07:36:30.80#ibcon#*before return 0, iclass 40, count 2 2006.203.07:36:30.80#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.203.07:36:30.80#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.203.07:36:30.80#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.203.07:36:30.80#ibcon#ireg 7 cls_cnt 0 2006.203.07:36:30.80#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.203.07:36:30.92#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.203.07:36:30.92#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.203.07:36:30.92#ibcon#enter wrdev, iclass 40, count 0 2006.203.07:36:30.92#ibcon#first serial, iclass 40, count 0 2006.203.07:36:30.92#ibcon#enter sib2, iclass 40, count 0 2006.203.07:36:30.92#ibcon#flushed, iclass 40, count 0 2006.203.07:36:30.92#ibcon#about to write, iclass 40, count 0 2006.203.07:36:30.92#ibcon#wrote, iclass 40, count 0 2006.203.07:36:30.92#ibcon#about to read 3, iclass 40, count 0 2006.203.07:36:30.94#ibcon#read 3, iclass 40, count 0 2006.203.07:36:30.94#ibcon#about to read 4, iclass 40, count 0 2006.203.07:36:30.94#ibcon#read 4, iclass 40, count 0 2006.203.07:36:30.94#ibcon#about to read 5, iclass 40, count 0 2006.203.07:36:30.94#ibcon#read 5, iclass 40, count 0 2006.203.07:36:30.94#ibcon#about to read 6, iclass 40, count 0 2006.203.07:36:30.94#ibcon#read 6, iclass 40, count 0 2006.203.07:36:30.94#ibcon#end of sib2, iclass 40, count 0 2006.203.07:36:30.94#ibcon#*mode == 0, iclass 40, count 0 2006.203.07:36:30.94#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.203.07:36:30.94#ibcon#[25=USB\r\n] 2006.203.07:36:30.94#ibcon#*before write, iclass 40, count 0 2006.203.07:36:30.94#ibcon#enter sib2, iclass 40, count 0 2006.203.07:36:30.94#ibcon#flushed, iclass 40, count 0 2006.203.07:36:30.94#ibcon#about to write, iclass 40, count 0 2006.203.07:36:30.94#ibcon#wrote, iclass 40, count 0 2006.203.07:36:30.94#ibcon#about to read 3, iclass 40, count 0 2006.203.07:36:30.97#ibcon#read 3, iclass 40, count 0 2006.203.07:36:30.97#ibcon#about to read 4, iclass 40, count 0 2006.203.07:36:30.97#ibcon#read 4, iclass 40, count 0 2006.203.07:36:30.97#ibcon#about to read 5, iclass 40, count 0 2006.203.07:36:30.97#ibcon#read 5, iclass 40, count 0 2006.203.07:36:30.97#ibcon#about to read 6, iclass 40, count 0 2006.203.07:36:30.97#ibcon#read 6, iclass 40, count 0 2006.203.07:36:30.97#ibcon#end of sib2, iclass 40, count 0 2006.203.07:36:30.97#ibcon#*after write, iclass 40, count 0 2006.203.07:36:30.97#ibcon#*before return 0, iclass 40, count 0 2006.203.07:36:30.97#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.203.07:36:30.97#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.203.07:36:30.97#ibcon#about to clear, iclass 40 cls_cnt 0 2006.203.07:36:30.97#ibcon#cleared, iclass 40 cls_cnt 0 2006.203.07:36:30.97$vc4f8/valo=4,832.99 2006.203.07:36:30.97#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.203.07:36:30.97#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.203.07:36:30.97#ibcon#ireg 17 cls_cnt 0 2006.203.07:36:30.97#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.203.07:36:30.97#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.203.07:36:30.97#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.203.07:36:30.97#ibcon#enter wrdev, iclass 4, count 0 2006.203.07:36:30.97#ibcon#first serial, iclass 4, count 0 2006.203.07:36:30.97#ibcon#enter sib2, iclass 4, count 0 2006.203.07:36:30.97#ibcon#flushed, iclass 4, count 0 2006.203.07:36:30.97#ibcon#about to write, iclass 4, count 0 2006.203.07:36:30.97#ibcon#wrote, iclass 4, count 0 2006.203.07:36:30.97#ibcon#about to read 3, iclass 4, count 0 2006.203.07:36:30.99#ibcon#read 3, iclass 4, count 0 2006.203.07:36:30.99#ibcon#about to read 4, iclass 4, count 0 2006.203.07:36:30.99#ibcon#read 4, iclass 4, count 0 2006.203.07:36:30.99#ibcon#about to read 5, iclass 4, count 0 2006.203.07:36:30.99#ibcon#read 5, iclass 4, count 0 2006.203.07:36:30.99#ibcon#about to read 6, iclass 4, count 0 2006.203.07:36:30.99#ibcon#read 6, iclass 4, count 0 2006.203.07:36:30.99#ibcon#end of sib2, iclass 4, count 0 2006.203.07:36:30.99#ibcon#*mode == 0, iclass 4, count 0 2006.203.07:36:30.99#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.203.07:36:30.99#ibcon#[26=FRQ=04,832.99\r\n] 2006.203.07:36:30.99#ibcon#*before write, iclass 4, count 0 2006.203.07:36:30.99#ibcon#enter sib2, iclass 4, count 0 2006.203.07:36:30.99#ibcon#flushed, iclass 4, count 0 2006.203.07:36:30.99#ibcon#about to write, iclass 4, count 0 2006.203.07:36:30.99#ibcon#wrote, iclass 4, count 0 2006.203.07:36:30.99#ibcon#about to read 3, iclass 4, count 0 2006.203.07:36:31.03#ibcon#read 3, iclass 4, count 0 2006.203.07:36:31.03#ibcon#about to read 4, iclass 4, count 0 2006.203.07:36:31.03#ibcon#read 4, iclass 4, count 0 2006.203.07:36:31.03#ibcon#about to read 5, iclass 4, count 0 2006.203.07:36:31.03#ibcon#read 5, iclass 4, count 0 2006.203.07:36:31.03#ibcon#about to read 6, iclass 4, count 0 2006.203.07:36:31.03#ibcon#read 6, iclass 4, count 0 2006.203.07:36:31.03#ibcon#end of sib2, iclass 4, count 0 2006.203.07:36:31.03#ibcon#*after write, iclass 4, count 0 2006.203.07:36:31.03#ibcon#*before return 0, iclass 4, count 0 2006.203.07:36:31.03#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.203.07:36:31.03#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.203.07:36:31.03#ibcon#about to clear, iclass 4 cls_cnt 0 2006.203.07:36:31.03#ibcon#cleared, iclass 4 cls_cnt 0 2006.203.07:36:31.03$vc4f8/va=4,7 2006.203.07:36:31.03#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.203.07:36:31.03#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.203.07:36:31.03#ibcon#ireg 11 cls_cnt 2 2006.203.07:36:31.03#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.203.07:36:31.09#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.203.07:36:31.09#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.203.07:36:31.09#ibcon#enter wrdev, iclass 6, count 2 2006.203.07:36:31.09#ibcon#first serial, iclass 6, count 2 2006.203.07:36:31.09#ibcon#enter sib2, iclass 6, count 2 2006.203.07:36:31.09#ibcon#flushed, iclass 6, count 2 2006.203.07:36:31.09#ibcon#about to write, iclass 6, count 2 2006.203.07:36:31.09#ibcon#wrote, iclass 6, count 2 2006.203.07:36:31.09#ibcon#about to read 3, iclass 6, count 2 2006.203.07:36:31.11#ibcon#read 3, iclass 6, count 2 2006.203.07:36:31.11#ibcon#about to read 4, iclass 6, count 2 2006.203.07:36:31.11#ibcon#read 4, iclass 6, count 2 2006.203.07:36:31.11#ibcon#about to read 5, iclass 6, count 2 2006.203.07:36:31.11#ibcon#read 5, iclass 6, count 2 2006.203.07:36:31.11#ibcon#about to read 6, iclass 6, count 2 2006.203.07:36:31.11#ibcon#read 6, iclass 6, count 2 2006.203.07:36:31.11#ibcon#end of sib2, iclass 6, count 2 2006.203.07:36:31.11#ibcon#*mode == 0, iclass 6, count 2 2006.203.07:36:31.11#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.203.07:36:31.11#ibcon#[25=AT04-07\r\n] 2006.203.07:36:31.11#ibcon#*before write, iclass 6, count 2 2006.203.07:36:31.11#ibcon#enter sib2, iclass 6, count 2 2006.203.07:36:31.11#ibcon#flushed, iclass 6, count 2 2006.203.07:36:31.11#ibcon#about to write, iclass 6, count 2 2006.203.07:36:31.11#ibcon#wrote, iclass 6, count 2 2006.203.07:36:31.11#ibcon#about to read 3, iclass 6, count 2 2006.203.07:36:31.14#ibcon#read 3, iclass 6, count 2 2006.203.07:36:31.14#ibcon#about to read 4, iclass 6, count 2 2006.203.07:36:31.14#ibcon#read 4, iclass 6, count 2 2006.203.07:36:31.14#ibcon#about to read 5, iclass 6, count 2 2006.203.07:36:31.14#ibcon#read 5, iclass 6, count 2 2006.203.07:36:31.14#ibcon#about to read 6, iclass 6, count 2 2006.203.07:36:31.14#ibcon#read 6, iclass 6, count 2 2006.203.07:36:31.14#ibcon#end of sib2, iclass 6, count 2 2006.203.07:36:31.14#ibcon#*after write, iclass 6, count 2 2006.203.07:36:31.14#ibcon#*before return 0, iclass 6, count 2 2006.203.07:36:31.14#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.203.07:36:31.14#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.203.07:36:31.14#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.203.07:36:31.14#ibcon#ireg 7 cls_cnt 0 2006.203.07:36:31.14#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.203.07:36:31.26#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.203.07:36:31.26#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.203.07:36:31.26#ibcon#enter wrdev, iclass 6, count 0 2006.203.07:36:31.26#ibcon#first serial, iclass 6, count 0 2006.203.07:36:31.26#ibcon#enter sib2, iclass 6, count 0 2006.203.07:36:31.26#ibcon#flushed, iclass 6, count 0 2006.203.07:36:31.26#ibcon#about to write, iclass 6, count 0 2006.203.07:36:31.26#ibcon#wrote, iclass 6, count 0 2006.203.07:36:31.26#ibcon#about to read 3, iclass 6, count 0 2006.203.07:36:31.28#ibcon#read 3, iclass 6, count 0 2006.203.07:36:31.28#ibcon#about to read 4, iclass 6, count 0 2006.203.07:36:31.28#ibcon#read 4, iclass 6, count 0 2006.203.07:36:31.28#ibcon#about to read 5, iclass 6, count 0 2006.203.07:36:31.28#ibcon#read 5, iclass 6, count 0 2006.203.07:36:31.28#ibcon#about to read 6, iclass 6, count 0 2006.203.07:36:31.28#ibcon#read 6, iclass 6, count 0 2006.203.07:36:31.28#ibcon#end of sib2, iclass 6, count 0 2006.203.07:36:31.28#ibcon#*mode == 0, iclass 6, count 0 2006.203.07:36:31.28#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.203.07:36:31.28#ibcon#[25=USB\r\n] 2006.203.07:36:31.28#ibcon#*before write, iclass 6, count 0 2006.203.07:36:31.28#ibcon#enter sib2, iclass 6, count 0 2006.203.07:36:31.28#ibcon#flushed, iclass 6, count 0 2006.203.07:36:31.28#ibcon#about to write, iclass 6, count 0 2006.203.07:36:31.28#ibcon#wrote, iclass 6, count 0 2006.203.07:36:31.28#ibcon#about to read 3, iclass 6, count 0 2006.203.07:36:31.31#ibcon#read 3, iclass 6, count 0 2006.203.07:36:31.31#ibcon#about to read 4, iclass 6, count 0 2006.203.07:36:31.31#ibcon#read 4, iclass 6, count 0 2006.203.07:36:31.31#ibcon#about to read 5, iclass 6, count 0 2006.203.07:36:31.31#ibcon#read 5, iclass 6, count 0 2006.203.07:36:31.31#ibcon#about to read 6, iclass 6, count 0 2006.203.07:36:31.31#ibcon#read 6, iclass 6, count 0 2006.203.07:36:31.31#ibcon#end of sib2, iclass 6, count 0 2006.203.07:36:31.31#ibcon#*after write, iclass 6, count 0 2006.203.07:36:31.31#ibcon#*before return 0, iclass 6, count 0 2006.203.07:36:31.31#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.203.07:36:31.31#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.203.07:36:31.31#ibcon#about to clear, iclass 6 cls_cnt 0 2006.203.07:36:31.31#ibcon#cleared, iclass 6 cls_cnt 0 2006.203.07:36:31.31$vc4f8/valo=5,652.99 2006.203.07:36:31.31#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.203.07:36:31.31#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.203.07:36:31.31#ibcon#ireg 17 cls_cnt 0 2006.203.07:36:31.31#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.203.07:36:31.31#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.203.07:36:31.31#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.203.07:36:31.31#ibcon#enter wrdev, iclass 10, count 0 2006.203.07:36:31.31#ibcon#first serial, iclass 10, count 0 2006.203.07:36:31.31#ibcon#enter sib2, iclass 10, count 0 2006.203.07:36:31.31#ibcon#flushed, iclass 10, count 0 2006.203.07:36:31.31#ibcon#about to write, iclass 10, count 0 2006.203.07:36:31.31#ibcon#wrote, iclass 10, count 0 2006.203.07:36:31.31#ibcon#about to read 3, iclass 10, count 0 2006.203.07:36:31.33#ibcon#read 3, iclass 10, count 0 2006.203.07:36:31.33#ibcon#about to read 4, iclass 10, count 0 2006.203.07:36:31.33#ibcon#read 4, iclass 10, count 0 2006.203.07:36:31.33#ibcon#about to read 5, iclass 10, count 0 2006.203.07:36:31.33#ibcon#read 5, iclass 10, count 0 2006.203.07:36:31.33#ibcon#about to read 6, iclass 10, count 0 2006.203.07:36:31.33#ibcon#read 6, iclass 10, count 0 2006.203.07:36:31.33#ibcon#end of sib2, iclass 10, count 0 2006.203.07:36:31.33#ibcon#*mode == 0, iclass 10, count 0 2006.203.07:36:31.33#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.203.07:36:31.33#ibcon#[26=FRQ=05,652.99\r\n] 2006.203.07:36:31.33#ibcon#*before write, iclass 10, count 0 2006.203.07:36:31.33#ibcon#enter sib2, iclass 10, count 0 2006.203.07:36:31.33#ibcon#flushed, iclass 10, count 0 2006.203.07:36:31.33#ibcon#about to write, iclass 10, count 0 2006.203.07:36:31.33#ibcon#wrote, iclass 10, count 0 2006.203.07:36:31.33#ibcon#about to read 3, iclass 10, count 0 2006.203.07:36:31.37#ibcon#read 3, iclass 10, count 0 2006.203.07:36:31.37#ibcon#about to read 4, iclass 10, count 0 2006.203.07:36:31.37#ibcon#read 4, iclass 10, count 0 2006.203.07:36:31.37#ibcon#about to read 5, iclass 10, count 0 2006.203.07:36:31.37#ibcon#read 5, iclass 10, count 0 2006.203.07:36:31.37#ibcon#about to read 6, iclass 10, count 0 2006.203.07:36:31.37#ibcon#read 6, iclass 10, count 0 2006.203.07:36:31.37#ibcon#end of sib2, iclass 10, count 0 2006.203.07:36:31.37#ibcon#*after write, iclass 10, count 0 2006.203.07:36:31.37#ibcon#*before return 0, iclass 10, count 0 2006.203.07:36:31.37#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.203.07:36:31.37#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.203.07:36:31.37#ibcon#about to clear, iclass 10 cls_cnt 0 2006.203.07:36:31.37#ibcon#cleared, iclass 10 cls_cnt 0 2006.203.07:36:31.37$vc4f8/va=5,7 2006.203.07:36:31.37#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.203.07:36:31.37#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.203.07:36:31.37#ibcon#ireg 11 cls_cnt 2 2006.203.07:36:31.37#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.203.07:36:31.44#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.203.07:36:31.44#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.203.07:36:31.44#ibcon#enter wrdev, iclass 12, count 2 2006.203.07:36:31.44#ibcon#first serial, iclass 12, count 2 2006.203.07:36:31.44#ibcon#enter sib2, iclass 12, count 2 2006.203.07:36:31.44#ibcon#flushed, iclass 12, count 2 2006.203.07:36:31.44#ibcon#about to write, iclass 12, count 2 2006.203.07:36:31.44#ibcon#wrote, iclass 12, count 2 2006.203.07:36:31.44#ibcon#about to read 3, iclass 12, count 2 2006.203.07:36:31.45#ibcon#read 3, iclass 12, count 2 2006.203.07:36:31.45#ibcon#about to read 4, iclass 12, count 2 2006.203.07:36:31.45#ibcon#read 4, iclass 12, count 2 2006.203.07:36:31.45#ibcon#about to read 5, iclass 12, count 2 2006.203.07:36:31.45#ibcon#read 5, iclass 12, count 2 2006.203.07:36:31.45#ibcon#about to read 6, iclass 12, count 2 2006.203.07:36:31.45#ibcon#read 6, iclass 12, count 2 2006.203.07:36:31.45#ibcon#end of sib2, iclass 12, count 2 2006.203.07:36:31.45#ibcon#*mode == 0, iclass 12, count 2 2006.203.07:36:31.45#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.203.07:36:31.45#ibcon#[25=AT05-07\r\n] 2006.203.07:36:31.45#ibcon#*before write, iclass 12, count 2 2006.203.07:36:31.45#ibcon#enter sib2, iclass 12, count 2 2006.203.07:36:31.45#ibcon#flushed, iclass 12, count 2 2006.203.07:36:31.45#ibcon#about to write, iclass 12, count 2 2006.203.07:36:31.45#ibcon#wrote, iclass 12, count 2 2006.203.07:36:31.45#ibcon#about to read 3, iclass 12, count 2 2006.203.07:36:31.48#ibcon#read 3, iclass 12, count 2 2006.203.07:36:31.48#ibcon#about to read 4, iclass 12, count 2 2006.203.07:36:31.48#ibcon#read 4, iclass 12, count 2 2006.203.07:36:31.48#ibcon#about to read 5, iclass 12, count 2 2006.203.07:36:31.48#ibcon#read 5, iclass 12, count 2 2006.203.07:36:31.48#ibcon#about to read 6, iclass 12, count 2 2006.203.07:36:31.48#ibcon#read 6, iclass 12, count 2 2006.203.07:36:31.48#ibcon#end of sib2, iclass 12, count 2 2006.203.07:36:31.48#ibcon#*after write, iclass 12, count 2 2006.203.07:36:31.48#ibcon#*before return 0, iclass 12, count 2 2006.203.07:36:31.48#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.203.07:36:31.48#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.203.07:36:31.48#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.203.07:36:31.48#ibcon#ireg 7 cls_cnt 0 2006.203.07:36:31.48#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.203.07:36:31.60#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.203.07:36:31.60#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.203.07:36:31.60#ibcon#enter wrdev, iclass 12, count 0 2006.203.07:36:31.60#ibcon#first serial, iclass 12, count 0 2006.203.07:36:31.60#ibcon#enter sib2, iclass 12, count 0 2006.203.07:36:31.60#ibcon#flushed, iclass 12, count 0 2006.203.07:36:31.60#ibcon#about to write, iclass 12, count 0 2006.203.07:36:31.60#ibcon#wrote, iclass 12, count 0 2006.203.07:36:31.60#ibcon#about to read 3, iclass 12, count 0 2006.203.07:36:31.62#ibcon#read 3, iclass 12, count 0 2006.203.07:36:31.62#ibcon#about to read 4, iclass 12, count 0 2006.203.07:36:31.62#ibcon#read 4, iclass 12, count 0 2006.203.07:36:31.62#ibcon#about to read 5, iclass 12, count 0 2006.203.07:36:31.62#ibcon#read 5, iclass 12, count 0 2006.203.07:36:31.62#ibcon#about to read 6, iclass 12, count 0 2006.203.07:36:31.62#ibcon#read 6, iclass 12, count 0 2006.203.07:36:31.62#ibcon#end of sib2, iclass 12, count 0 2006.203.07:36:31.62#ibcon#*mode == 0, iclass 12, count 0 2006.203.07:36:31.62#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.203.07:36:31.62#ibcon#[25=USB\r\n] 2006.203.07:36:31.62#ibcon#*before write, iclass 12, count 0 2006.203.07:36:31.62#ibcon#enter sib2, iclass 12, count 0 2006.203.07:36:31.62#ibcon#flushed, iclass 12, count 0 2006.203.07:36:31.62#ibcon#about to write, iclass 12, count 0 2006.203.07:36:31.62#ibcon#wrote, iclass 12, count 0 2006.203.07:36:31.62#ibcon#about to read 3, iclass 12, count 0 2006.203.07:36:31.65#ibcon#read 3, iclass 12, count 0 2006.203.07:36:31.65#ibcon#about to read 4, iclass 12, count 0 2006.203.07:36:31.65#ibcon#read 4, iclass 12, count 0 2006.203.07:36:31.65#ibcon#about to read 5, iclass 12, count 0 2006.203.07:36:31.65#ibcon#read 5, iclass 12, count 0 2006.203.07:36:31.65#ibcon#about to read 6, iclass 12, count 0 2006.203.07:36:31.65#ibcon#read 6, iclass 12, count 0 2006.203.07:36:31.65#ibcon#end of sib2, iclass 12, count 0 2006.203.07:36:31.65#ibcon#*after write, iclass 12, count 0 2006.203.07:36:31.65#ibcon#*before return 0, iclass 12, count 0 2006.203.07:36:31.65#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.203.07:36:31.65#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.203.07:36:31.65#ibcon#about to clear, iclass 12 cls_cnt 0 2006.203.07:36:31.65#ibcon#cleared, iclass 12 cls_cnt 0 2006.203.07:36:31.65$vc4f8/valo=6,772.99 2006.203.07:36:31.65#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.203.07:36:31.65#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.203.07:36:31.65#ibcon#ireg 17 cls_cnt 0 2006.203.07:36:31.65#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.203.07:36:31.65#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.203.07:36:31.65#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.203.07:36:31.65#ibcon#enter wrdev, iclass 14, count 0 2006.203.07:36:31.65#ibcon#first serial, iclass 14, count 0 2006.203.07:36:31.65#ibcon#enter sib2, iclass 14, count 0 2006.203.07:36:31.65#ibcon#flushed, iclass 14, count 0 2006.203.07:36:31.65#ibcon#about to write, iclass 14, count 0 2006.203.07:36:31.65#ibcon#wrote, iclass 14, count 0 2006.203.07:36:31.65#ibcon#about to read 3, iclass 14, count 0 2006.203.07:36:31.68#ibcon#read 3, iclass 14, count 0 2006.203.07:36:31.68#ibcon#about to read 4, iclass 14, count 0 2006.203.07:36:31.68#ibcon#read 4, iclass 14, count 0 2006.203.07:36:31.68#ibcon#about to read 5, iclass 14, count 0 2006.203.07:36:31.68#ibcon#read 5, iclass 14, count 0 2006.203.07:36:31.68#ibcon#about to read 6, iclass 14, count 0 2006.203.07:36:31.68#ibcon#read 6, iclass 14, count 0 2006.203.07:36:31.68#ibcon#end of sib2, iclass 14, count 0 2006.203.07:36:31.68#ibcon#*mode == 0, iclass 14, count 0 2006.203.07:36:31.68#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.203.07:36:31.68#ibcon#[26=FRQ=06,772.99\r\n] 2006.203.07:36:31.68#ibcon#*before write, iclass 14, count 0 2006.203.07:36:31.68#ibcon#enter sib2, iclass 14, count 0 2006.203.07:36:31.68#ibcon#flushed, iclass 14, count 0 2006.203.07:36:31.68#ibcon#about to write, iclass 14, count 0 2006.203.07:36:31.68#ibcon#wrote, iclass 14, count 0 2006.203.07:36:31.68#ibcon#about to read 3, iclass 14, count 0 2006.203.07:36:31.72#ibcon#read 3, iclass 14, count 0 2006.203.07:36:31.72#ibcon#about to read 4, iclass 14, count 0 2006.203.07:36:31.72#ibcon#read 4, iclass 14, count 0 2006.203.07:36:31.72#ibcon#about to read 5, iclass 14, count 0 2006.203.07:36:31.72#ibcon#read 5, iclass 14, count 0 2006.203.07:36:31.72#ibcon#about to read 6, iclass 14, count 0 2006.203.07:36:31.72#ibcon#read 6, iclass 14, count 0 2006.203.07:36:31.72#ibcon#end of sib2, iclass 14, count 0 2006.203.07:36:31.72#ibcon#*after write, iclass 14, count 0 2006.203.07:36:31.72#ibcon#*before return 0, iclass 14, count 0 2006.203.07:36:31.72#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.203.07:36:31.72#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.203.07:36:31.72#ibcon#about to clear, iclass 14 cls_cnt 0 2006.203.07:36:31.72#ibcon#cleared, iclass 14 cls_cnt 0 2006.203.07:36:31.72$vc4f8/va=6,6 2006.203.07:36:31.72#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.203.07:36:31.72#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.203.07:36:31.72#ibcon#ireg 11 cls_cnt 2 2006.203.07:36:31.72#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.203.07:36:31.77#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.203.07:36:31.77#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.203.07:36:31.77#ibcon#enter wrdev, iclass 16, count 2 2006.203.07:36:31.77#ibcon#first serial, iclass 16, count 2 2006.203.07:36:31.77#ibcon#enter sib2, iclass 16, count 2 2006.203.07:36:31.77#ibcon#flushed, iclass 16, count 2 2006.203.07:36:31.77#ibcon#about to write, iclass 16, count 2 2006.203.07:36:31.77#ibcon#wrote, iclass 16, count 2 2006.203.07:36:31.77#ibcon#about to read 3, iclass 16, count 2 2006.203.07:36:31.79#ibcon#read 3, iclass 16, count 2 2006.203.07:36:31.79#ibcon#about to read 4, iclass 16, count 2 2006.203.07:36:31.79#ibcon#read 4, iclass 16, count 2 2006.203.07:36:31.79#ibcon#about to read 5, iclass 16, count 2 2006.203.07:36:31.79#ibcon#read 5, iclass 16, count 2 2006.203.07:36:31.79#ibcon#about to read 6, iclass 16, count 2 2006.203.07:36:31.79#ibcon#read 6, iclass 16, count 2 2006.203.07:36:31.79#ibcon#end of sib2, iclass 16, count 2 2006.203.07:36:31.79#ibcon#*mode == 0, iclass 16, count 2 2006.203.07:36:31.79#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.203.07:36:31.79#ibcon#[25=AT06-06\r\n] 2006.203.07:36:31.79#ibcon#*before write, iclass 16, count 2 2006.203.07:36:31.79#ibcon#enter sib2, iclass 16, count 2 2006.203.07:36:31.79#ibcon#flushed, iclass 16, count 2 2006.203.07:36:31.79#ibcon#about to write, iclass 16, count 2 2006.203.07:36:31.79#ibcon#wrote, iclass 16, count 2 2006.203.07:36:31.79#ibcon#about to read 3, iclass 16, count 2 2006.203.07:36:31.82#ibcon#read 3, iclass 16, count 2 2006.203.07:36:31.82#ibcon#about to read 4, iclass 16, count 2 2006.203.07:36:31.82#ibcon#read 4, iclass 16, count 2 2006.203.07:36:31.82#ibcon#about to read 5, iclass 16, count 2 2006.203.07:36:31.82#ibcon#read 5, iclass 16, count 2 2006.203.07:36:31.82#ibcon#about to read 6, iclass 16, count 2 2006.203.07:36:31.82#ibcon#read 6, iclass 16, count 2 2006.203.07:36:31.82#ibcon#end of sib2, iclass 16, count 2 2006.203.07:36:31.82#ibcon#*after write, iclass 16, count 2 2006.203.07:36:31.82#ibcon#*before return 0, iclass 16, count 2 2006.203.07:36:31.82#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.203.07:36:31.82#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.203.07:36:31.82#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.203.07:36:31.82#ibcon#ireg 7 cls_cnt 0 2006.203.07:36:31.82#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.203.07:36:31.94#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.203.07:36:31.94#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.203.07:36:31.94#ibcon#enter wrdev, iclass 16, count 0 2006.203.07:36:31.94#ibcon#first serial, iclass 16, count 0 2006.203.07:36:31.94#ibcon#enter sib2, iclass 16, count 0 2006.203.07:36:31.94#ibcon#flushed, iclass 16, count 0 2006.203.07:36:31.94#ibcon#about to write, iclass 16, count 0 2006.203.07:36:31.94#ibcon#wrote, iclass 16, count 0 2006.203.07:36:31.94#ibcon#about to read 3, iclass 16, count 0 2006.203.07:36:31.96#ibcon#read 3, iclass 16, count 0 2006.203.07:36:31.96#ibcon#about to read 4, iclass 16, count 0 2006.203.07:36:31.96#ibcon#read 4, iclass 16, count 0 2006.203.07:36:31.96#ibcon#about to read 5, iclass 16, count 0 2006.203.07:36:31.96#ibcon#read 5, iclass 16, count 0 2006.203.07:36:31.96#ibcon#about to read 6, iclass 16, count 0 2006.203.07:36:31.96#ibcon#read 6, iclass 16, count 0 2006.203.07:36:31.96#ibcon#end of sib2, iclass 16, count 0 2006.203.07:36:31.96#ibcon#*mode == 0, iclass 16, count 0 2006.203.07:36:31.96#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.203.07:36:31.96#ibcon#[25=USB\r\n] 2006.203.07:36:31.96#ibcon#*before write, iclass 16, count 0 2006.203.07:36:31.96#ibcon#enter sib2, iclass 16, count 0 2006.203.07:36:31.96#ibcon#flushed, iclass 16, count 0 2006.203.07:36:31.96#ibcon#about to write, iclass 16, count 0 2006.203.07:36:31.96#ibcon#wrote, iclass 16, count 0 2006.203.07:36:31.96#ibcon#about to read 3, iclass 16, count 0 2006.203.07:36:31.99#ibcon#read 3, iclass 16, count 0 2006.203.07:36:31.99#ibcon#about to read 4, iclass 16, count 0 2006.203.07:36:31.99#ibcon#read 4, iclass 16, count 0 2006.203.07:36:31.99#ibcon#about to read 5, iclass 16, count 0 2006.203.07:36:31.99#ibcon#read 5, iclass 16, count 0 2006.203.07:36:31.99#ibcon#about to read 6, iclass 16, count 0 2006.203.07:36:31.99#ibcon#read 6, iclass 16, count 0 2006.203.07:36:31.99#ibcon#end of sib2, iclass 16, count 0 2006.203.07:36:31.99#ibcon#*after write, iclass 16, count 0 2006.203.07:36:31.99#ibcon#*before return 0, iclass 16, count 0 2006.203.07:36:31.99#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.203.07:36:31.99#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.203.07:36:31.99#ibcon#about to clear, iclass 16 cls_cnt 0 2006.203.07:36:31.99#ibcon#cleared, iclass 16 cls_cnt 0 2006.203.07:36:31.99$vc4f8/valo=7,832.99 2006.203.07:36:31.99#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.203.07:36:31.99#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.203.07:36:31.99#ibcon#ireg 17 cls_cnt 0 2006.203.07:36:31.99#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.203.07:36:31.99#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.203.07:36:31.99#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.203.07:36:31.99#ibcon#enter wrdev, iclass 18, count 0 2006.203.07:36:31.99#ibcon#first serial, iclass 18, count 0 2006.203.07:36:31.99#ibcon#enter sib2, iclass 18, count 0 2006.203.07:36:31.99#ibcon#flushed, iclass 18, count 0 2006.203.07:36:31.99#ibcon#about to write, iclass 18, count 0 2006.203.07:36:31.99#ibcon#wrote, iclass 18, count 0 2006.203.07:36:31.99#ibcon#about to read 3, iclass 18, count 0 2006.203.07:36:32.01#ibcon#read 3, iclass 18, count 0 2006.203.07:36:32.01#ibcon#about to read 4, iclass 18, count 0 2006.203.07:36:32.01#ibcon#read 4, iclass 18, count 0 2006.203.07:36:32.01#ibcon#about to read 5, iclass 18, count 0 2006.203.07:36:32.01#ibcon#read 5, iclass 18, count 0 2006.203.07:36:32.01#ibcon#about to read 6, iclass 18, count 0 2006.203.07:36:32.01#ibcon#read 6, iclass 18, count 0 2006.203.07:36:32.01#ibcon#end of sib2, iclass 18, count 0 2006.203.07:36:32.01#ibcon#*mode == 0, iclass 18, count 0 2006.203.07:36:32.01#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.203.07:36:32.01#ibcon#[26=FRQ=07,832.99\r\n] 2006.203.07:36:32.01#ibcon#*before write, iclass 18, count 0 2006.203.07:36:32.01#ibcon#enter sib2, iclass 18, count 0 2006.203.07:36:32.01#ibcon#flushed, iclass 18, count 0 2006.203.07:36:32.01#ibcon#about to write, iclass 18, count 0 2006.203.07:36:32.01#ibcon#wrote, iclass 18, count 0 2006.203.07:36:32.01#ibcon#about to read 3, iclass 18, count 0 2006.203.07:36:32.05#ibcon#read 3, iclass 18, count 0 2006.203.07:36:32.05#ibcon#about to read 4, iclass 18, count 0 2006.203.07:36:32.05#ibcon#read 4, iclass 18, count 0 2006.203.07:36:32.05#ibcon#about to read 5, iclass 18, count 0 2006.203.07:36:32.05#ibcon#read 5, iclass 18, count 0 2006.203.07:36:32.05#ibcon#about to read 6, iclass 18, count 0 2006.203.07:36:32.05#ibcon#read 6, iclass 18, count 0 2006.203.07:36:32.05#ibcon#end of sib2, iclass 18, count 0 2006.203.07:36:32.05#ibcon#*after write, iclass 18, count 0 2006.203.07:36:32.05#ibcon#*before return 0, iclass 18, count 0 2006.203.07:36:32.05#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.203.07:36:32.05#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.203.07:36:32.05#ibcon#about to clear, iclass 18 cls_cnt 0 2006.203.07:36:32.05#ibcon#cleared, iclass 18 cls_cnt 0 2006.203.07:36:32.05$vc4f8/va=7,7 2006.203.07:36:32.05#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.203.07:36:32.05#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.203.07:36:32.05#ibcon#ireg 11 cls_cnt 2 2006.203.07:36:32.05#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.203.07:36:32.11#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.203.07:36:32.11#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.203.07:36:32.11#ibcon#enter wrdev, iclass 20, count 2 2006.203.07:36:32.11#ibcon#first serial, iclass 20, count 2 2006.203.07:36:32.11#ibcon#enter sib2, iclass 20, count 2 2006.203.07:36:32.11#ibcon#flushed, iclass 20, count 2 2006.203.07:36:32.11#ibcon#about to write, iclass 20, count 2 2006.203.07:36:32.11#ibcon#wrote, iclass 20, count 2 2006.203.07:36:32.11#ibcon#about to read 3, iclass 20, count 2 2006.203.07:36:32.13#ibcon#read 3, iclass 20, count 2 2006.203.07:36:32.13#ibcon#about to read 4, iclass 20, count 2 2006.203.07:36:32.13#ibcon#read 4, iclass 20, count 2 2006.203.07:36:32.13#ibcon#about to read 5, iclass 20, count 2 2006.203.07:36:32.13#ibcon#read 5, iclass 20, count 2 2006.203.07:36:32.13#ibcon#about to read 6, iclass 20, count 2 2006.203.07:36:32.13#ibcon#read 6, iclass 20, count 2 2006.203.07:36:32.13#ibcon#end of sib2, iclass 20, count 2 2006.203.07:36:32.13#ibcon#*mode == 0, iclass 20, count 2 2006.203.07:36:32.13#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.203.07:36:32.13#ibcon#[25=AT07-07\r\n] 2006.203.07:36:32.13#ibcon#*before write, iclass 20, count 2 2006.203.07:36:32.13#ibcon#enter sib2, iclass 20, count 2 2006.203.07:36:32.13#ibcon#flushed, iclass 20, count 2 2006.203.07:36:32.13#ibcon#about to write, iclass 20, count 2 2006.203.07:36:32.13#ibcon#wrote, iclass 20, count 2 2006.203.07:36:32.13#ibcon#about to read 3, iclass 20, count 2 2006.203.07:36:32.16#ibcon#read 3, iclass 20, count 2 2006.203.07:36:32.16#ibcon#about to read 4, iclass 20, count 2 2006.203.07:36:32.16#ibcon#read 4, iclass 20, count 2 2006.203.07:36:32.16#ibcon#about to read 5, iclass 20, count 2 2006.203.07:36:32.16#ibcon#read 5, iclass 20, count 2 2006.203.07:36:32.16#ibcon#about to read 6, iclass 20, count 2 2006.203.07:36:32.16#ibcon#read 6, iclass 20, count 2 2006.203.07:36:32.16#ibcon#end of sib2, iclass 20, count 2 2006.203.07:36:32.16#ibcon#*after write, iclass 20, count 2 2006.203.07:36:32.16#ibcon#*before return 0, iclass 20, count 2 2006.203.07:36:32.16#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.203.07:36:32.16#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.203.07:36:32.16#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.203.07:36:32.16#ibcon#ireg 7 cls_cnt 0 2006.203.07:36:32.16#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.203.07:36:32.28#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.203.07:36:32.28#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.203.07:36:32.28#ibcon#enter wrdev, iclass 20, count 0 2006.203.07:36:32.28#ibcon#first serial, iclass 20, count 0 2006.203.07:36:32.28#ibcon#enter sib2, iclass 20, count 0 2006.203.07:36:32.28#ibcon#flushed, iclass 20, count 0 2006.203.07:36:32.28#ibcon#about to write, iclass 20, count 0 2006.203.07:36:32.28#ibcon#wrote, iclass 20, count 0 2006.203.07:36:32.28#ibcon#about to read 3, iclass 20, count 0 2006.203.07:36:32.30#ibcon#read 3, iclass 20, count 0 2006.203.07:36:32.30#ibcon#about to read 4, iclass 20, count 0 2006.203.07:36:32.30#ibcon#read 4, iclass 20, count 0 2006.203.07:36:32.30#ibcon#about to read 5, iclass 20, count 0 2006.203.07:36:32.30#ibcon#read 5, iclass 20, count 0 2006.203.07:36:32.30#ibcon#about to read 6, iclass 20, count 0 2006.203.07:36:32.30#ibcon#read 6, iclass 20, count 0 2006.203.07:36:32.30#ibcon#end of sib2, iclass 20, count 0 2006.203.07:36:32.30#ibcon#*mode == 0, iclass 20, count 0 2006.203.07:36:32.30#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.203.07:36:32.30#ibcon#[25=USB\r\n] 2006.203.07:36:32.30#ibcon#*before write, iclass 20, count 0 2006.203.07:36:32.30#ibcon#enter sib2, iclass 20, count 0 2006.203.07:36:32.30#ibcon#flushed, iclass 20, count 0 2006.203.07:36:32.30#ibcon#about to write, iclass 20, count 0 2006.203.07:36:32.30#ibcon#wrote, iclass 20, count 0 2006.203.07:36:32.30#ibcon#about to read 3, iclass 20, count 0 2006.203.07:36:32.33#ibcon#read 3, iclass 20, count 0 2006.203.07:36:32.33#ibcon#about to read 4, iclass 20, count 0 2006.203.07:36:32.33#ibcon#read 4, iclass 20, count 0 2006.203.07:36:32.33#ibcon#about to read 5, iclass 20, count 0 2006.203.07:36:32.33#ibcon#read 5, iclass 20, count 0 2006.203.07:36:32.33#ibcon#about to read 6, iclass 20, count 0 2006.203.07:36:32.33#ibcon#read 6, iclass 20, count 0 2006.203.07:36:32.33#ibcon#end of sib2, iclass 20, count 0 2006.203.07:36:32.33#ibcon#*after write, iclass 20, count 0 2006.203.07:36:32.33#ibcon#*before return 0, iclass 20, count 0 2006.203.07:36:32.33#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.203.07:36:32.33#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.203.07:36:32.33#ibcon#about to clear, iclass 20 cls_cnt 0 2006.203.07:36:32.33#ibcon#cleared, iclass 20 cls_cnt 0 2006.203.07:36:32.33$vc4f8/valo=8,852.99 2006.203.07:36:32.33#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.203.07:36:32.33#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.203.07:36:32.33#ibcon#ireg 17 cls_cnt 0 2006.203.07:36:32.33#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.203.07:36:32.33#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.203.07:36:32.33#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.203.07:36:32.33#ibcon#enter wrdev, iclass 22, count 0 2006.203.07:36:32.33#ibcon#first serial, iclass 22, count 0 2006.203.07:36:32.33#ibcon#enter sib2, iclass 22, count 0 2006.203.07:36:32.33#ibcon#flushed, iclass 22, count 0 2006.203.07:36:32.33#ibcon#about to write, iclass 22, count 0 2006.203.07:36:32.33#ibcon#wrote, iclass 22, count 0 2006.203.07:36:32.33#ibcon#about to read 3, iclass 22, count 0 2006.203.07:36:32.36#ibcon#read 3, iclass 22, count 0 2006.203.07:36:32.36#ibcon#about to read 4, iclass 22, count 0 2006.203.07:36:32.36#ibcon#read 4, iclass 22, count 0 2006.203.07:36:32.36#ibcon#about to read 5, iclass 22, count 0 2006.203.07:36:32.36#ibcon#read 5, iclass 22, count 0 2006.203.07:36:32.36#ibcon#about to read 6, iclass 22, count 0 2006.203.07:36:32.36#ibcon#read 6, iclass 22, count 0 2006.203.07:36:32.36#ibcon#end of sib2, iclass 22, count 0 2006.203.07:36:32.36#ibcon#*mode == 0, iclass 22, count 0 2006.203.07:36:32.36#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.203.07:36:32.36#ibcon#[26=FRQ=08,852.99\r\n] 2006.203.07:36:32.36#ibcon#*before write, iclass 22, count 0 2006.203.07:36:32.36#ibcon#enter sib2, iclass 22, count 0 2006.203.07:36:32.36#ibcon#flushed, iclass 22, count 0 2006.203.07:36:32.36#ibcon#about to write, iclass 22, count 0 2006.203.07:36:32.36#ibcon#wrote, iclass 22, count 0 2006.203.07:36:32.36#ibcon#about to read 3, iclass 22, count 0 2006.203.07:36:32.40#ibcon#read 3, iclass 22, count 0 2006.203.07:36:32.40#ibcon#about to read 4, iclass 22, count 0 2006.203.07:36:32.40#ibcon#read 4, iclass 22, count 0 2006.203.07:36:32.40#ibcon#about to read 5, iclass 22, count 0 2006.203.07:36:32.40#ibcon#read 5, iclass 22, count 0 2006.203.07:36:32.40#ibcon#about to read 6, iclass 22, count 0 2006.203.07:36:32.40#ibcon#read 6, iclass 22, count 0 2006.203.07:36:32.40#ibcon#end of sib2, iclass 22, count 0 2006.203.07:36:32.40#ibcon#*after write, iclass 22, count 0 2006.203.07:36:32.40#ibcon#*before return 0, iclass 22, count 0 2006.203.07:36:32.40#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.203.07:36:32.40#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.203.07:36:32.40#ibcon#about to clear, iclass 22 cls_cnt 0 2006.203.07:36:32.40#ibcon#cleared, iclass 22 cls_cnt 0 2006.203.07:36:32.40$vc4f8/va=8,6 2006.203.07:36:32.40#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.203.07:36:32.40#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.203.07:36:32.40#ibcon#ireg 11 cls_cnt 2 2006.203.07:36:32.40#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.203.07:36:32.45#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.203.07:36:32.45#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.203.07:36:32.45#ibcon#enter wrdev, iclass 24, count 2 2006.203.07:36:32.45#ibcon#first serial, iclass 24, count 2 2006.203.07:36:32.45#ibcon#enter sib2, iclass 24, count 2 2006.203.07:36:32.45#ibcon#flushed, iclass 24, count 2 2006.203.07:36:32.45#ibcon#about to write, iclass 24, count 2 2006.203.07:36:32.45#ibcon#wrote, iclass 24, count 2 2006.203.07:36:32.45#ibcon#about to read 3, iclass 24, count 2 2006.203.07:36:32.47#ibcon#read 3, iclass 24, count 2 2006.203.07:36:32.47#ibcon#about to read 4, iclass 24, count 2 2006.203.07:36:32.47#ibcon#read 4, iclass 24, count 2 2006.203.07:36:32.47#ibcon#about to read 5, iclass 24, count 2 2006.203.07:36:32.47#ibcon#read 5, iclass 24, count 2 2006.203.07:36:32.47#ibcon#about to read 6, iclass 24, count 2 2006.203.07:36:32.47#ibcon#read 6, iclass 24, count 2 2006.203.07:36:32.47#ibcon#end of sib2, iclass 24, count 2 2006.203.07:36:32.47#ibcon#*mode == 0, iclass 24, count 2 2006.203.07:36:32.47#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.203.07:36:32.47#ibcon#[25=AT08-06\r\n] 2006.203.07:36:32.47#ibcon#*before write, iclass 24, count 2 2006.203.07:36:32.47#ibcon#enter sib2, iclass 24, count 2 2006.203.07:36:32.47#ibcon#flushed, iclass 24, count 2 2006.203.07:36:32.47#ibcon#about to write, iclass 24, count 2 2006.203.07:36:32.47#ibcon#wrote, iclass 24, count 2 2006.203.07:36:32.47#ibcon#about to read 3, iclass 24, count 2 2006.203.07:36:32.50#ibcon#read 3, iclass 24, count 2 2006.203.07:36:32.50#ibcon#about to read 4, iclass 24, count 2 2006.203.07:36:32.50#ibcon#read 4, iclass 24, count 2 2006.203.07:36:32.50#ibcon#about to read 5, iclass 24, count 2 2006.203.07:36:32.50#ibcon#read 5, iclass 24, count 2 2006.203.07:36:32.50#ibcon#about to read 6, iclass 24, count 2 2006.203.07:36:32.50#ibcon#read 6, iclass 24, count 2 2006.203.07:36:32.50#ibcon#end of sib2, iclass 24, count 2 2006.203.07:36:32.50#ibcon#*after write, iclass 24, count 2 2006.203.07:36:32.50#ibcon#*before return 0, iclass 24, count 2 2006.203.07:36:32.50#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.203.07:36:32.50#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.203.07:36:32.50#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.203.07:36:32.50#ibcon#ireg 7 cls_cnt 0 2006.203.07:36:32.50#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.203.07:36:32.62#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.203.07:36:32.62#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.203.07:36:32.62#ibcon#enter wrdev, iclass 24, count 0 2006.203.07:36:32.62#ibcon#first serial, iclass 24, count 0 2006.203.07:36:32.62#ibcon#enter sib2, iclass 24, count 0 2006.203.07:36:32.62#ibcon#flushed, iclass 24, count 0 2006.203.07:36:32.62#ibcon#about to write, iclass 24, count 0 2006.203.07:36:32.62#ibcon#wrote, iclass 24, count 0 2006.203.07:36:32.62#ibcon#about to read 3, iclass 24, count 0 2006.203.07:36:32.64#ibcon#read 3, iclass 24, count 0 2006.203.07:36:32.64#ibcon#about to read 4, iclass 24, count 0 2006.203.07:36:32.64#ibcon#read 4, iclass 24, count 0 2006.203.07:36:32.64#ibcon#about to read 5, iclass 24, count 0 2006.203.07:36:32.64#ibcon#read 5, iclass 24, count 0 2006.203.07:36:32.64#ibcon#about to read 6, iclass 24, count 0 2006.203.07:36:32.64#ibcon#read 6, iclass 24, count 0 2006.203.07:36:32.64#ibcon#end of sib2, iclass 24, count 0 2006.203.07:36:32.64#ibcon#*mode == 0, iclass 24, count 0 2006.203.07:36:32.64#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.203.07:36:32.64#ibcon#[25=USB\r\n] 2006.203.07:36:32.64#ibcon#*before write, iclass 24, count 0 2006.203.07:36:32.64#ibcon#enter sib2, iclass 24, count 0 2006.203.07:36:32.64#ibcon#flushed, iclass 24, count 0 2006.203.07:36:32.64#ibcon#about to write, iclass 24, count 0 2006.203.07:36:32.64#ibcon#wrote, iclass 24, count 0 2006.203.07:36:32.64#ibcon#about to read 3, iclass 24, count 0 2006.203.07:36:32.67#ibcon#read 3, iclass 24, count 0 2006.203.07:36:32.67#ibcon#about to read 4, iclass 24, count 0 2006.203.07:36:32.67#ibcon#read 4, iclass 24, count 0 2006.203.07:36:32.67#ibcon#about to read 5, iclass 24, count 0 2006.203.07:36:32.67#ibcon#read 5, iclass 24, count 0 2006.203.07:36:32.67#ibcon#about to read 6, iclass 24, count 0 2006.203.07:36:32.67#ibcon#read 6, iclass 24, count 0 2006.203.07:36:32.67#ibcon#end of sib2, iclass 24, count 0 2006.203.07:36:32.67#ibcon#*after write, iclass 24, count 0 2006.203.07:36:32.67#ibcon#*before return 0, iclass 24, count 0 2006.203.07:36:32.67#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.203.07:36:32.67#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.203.07:36:32.67#ibcon#about to clear, iclass 24 cls_cnt 0 2006.203.07:36:32.67#ibcon#cleared, iclass 24 cls_cnt 0 2006.203.07:36:32.67$vc4f8/vblo=1,632.99 2006.203.07:36:32.67#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.203.07:36:32.67#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.203.07:36:32.67#ibcon#ireg 17 cls_cnt 0 2006.203.07:36:32.67#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.203.07:36:32.67#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.203.07:36:32.67#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.203.07:36:32.67#ibcon#enter wrdev, iclass 26, count 0 2006.203.07:36:32.67#ibcon#first serial, iclass 26, count 0 2006.203.07:36:32.67#ibcon#enter sib2, iclass 26, count 0 2006.203.07:36:32.67#ibcon#flushed, iclass 26, count 0 2006.203.07:36:32.67#ibcon#about to write, iclass 26, count 0 2006.203.07:36:32.67#ibcon#wrote, iclass 26, count 0 2006.203.07:36:32.67#ibcon#about to read 3, iclass 26, count 0 2006.203.07:36:32.69#ibcon#read 3, iclass 26, count 0 2006.203.07:36:32.69#ibcon#about to read 4, iclass 26, count 0 2006.203.07:36:32.69#ibcon#read 4, iclass 26, count 0 2006.203.07:36:32.69#ibcon#about to read 5, iclass 26, count 0 2006.203.07:36:32.69#ibcon#read 5, iclass 26, count 0 2006.203.07:36:32.69#ibcon#about to read 6, iclass 26, count 0 2006.203.07:36:32.69#ibcon#read 6, iclass 26, count 0 2006.203.07:36:32.69#ibcon#end of sib2, iclass 26, count 0 2006.203.07:36:32.69#ibcon#*mode == 0, iclass 26, count 0 2006.203.07:36:32.69#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.203.07:36:32.69#ibcon#[28=FRQ=01,632.99\r\n] 2006.203.07:36:32.69#ibcon#*before write, iclass 26, count 0 2006.203.07:36:32.69#ibcon#enter sib2, iclass 26, count 0 2006.203.07:36:32.69#ibcon#flushed, iclass 26, count 0 2006.203.07:36:32.69#ibcon#about to write, iclass 26, count 0 2006.203.07:36:32.69#ibcon#wrote, iclass 26, count 0 2006.203.07:36:32.69#ibcon#about to read 3, iclass 26, count 0 2006.203.07:36:32.73#ibcon#read 3, iclass 26, count 0 2006.203.07:36:32.73#ibcon#about to read 4, iclass 26, count 0 2006.203.07:36:32.73#ibcon#read 4, iclass 26, count 0 2006.203.07:36:32.73#ibcon#about to read 5, iclass 26, count 0 2006.203.07:36:32.73#ibcon#read 5, iclass 26, count 0 2006.203.07:36:32.73#ibcon#about to read 6, iclass 26, count 0 2006.203.07:36:32.73#ibcon#read 6, iclass 26, count 0 2006.203.07:36:32.73#ibcon#end of sib2, iclass 26, count 0 2006.203.07:36:32.73#ibcon#*after write, iclass 26, count 0 2006.203.07:36:32.73#ibcon#*before return 0, iclass 26, count 0 2006.203.07:36:32.73#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.203.07:36:32.73#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.203.07:36:32.73#ibcon#about to clear, iclass 26 cls_cnt 0 2006.203.07:36:32.73#ibcon#cleared, iclass 26 cls_cnt 0 2006.203.07:36:32.73$vc4f8/vb=1,4 2006.203.07:36:32.73#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.203.07:36:32.73#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.203.07:36:32.73#ibcon#ireg 11 cls_cnt 2 2006.203.07:36:32.73#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.203.07:36:32.73#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.203.07:36:32.73#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.203.07:36:32.73#ibcon#enter wrdev, iclass 28, count 2 2006.203.07:36:32.73#ibcon#first serial, iclass 28, count 2 2006.203.07:36:32.73#ibcon#enter sib2, iclass 28, count 2 2006.203.07:36:32.73#ibcon#flushed, iclass 28, count 2 2006.203.07:36:32.73#ibcon#about to write, iclass 28, count 2 2006.203.07:36:32.73#ibcon#wrote, iclass 28, count 2 2006.203.07:36:32.73#ibcon#about to read 3, iclass 28, count 2 2006.203.07:36:32.75#ibcon#read 3, iclass 28, count 2 2006.203.07:36:32.75#ibcon#about to read 4, iclass 28, count 2 2006.203.07:36:32.75#ibcon#read 4, iclass 28, count 2 2006.203.07:36:32.75#ibcon#about to read 5, iclass 28, count 2 2006.203.07:36:32.75#ibcon#read 5, iclass 28, count 2 2006.203.07:36:32.75#ibcon#about to read 6, iclass 28, count 2 2006.203.07:36:32.75#ibcon#read 6, iclass 28, count 2 2006.203.07:36:32.75#ibcon#end of sib2, iclass 28, count 2 2006.203.07:36:32.75#ibcon#*mode == 0, iclass 28, count 2 2006.203.07:36:32.75#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.203.07:36:32.75#ibcon#[27=AT01-04\r\n] 2006.203.07:36:32.75#ibcon#*before write, iclass 28, count 2 2006.203.07:36:32.75#ibcon#enter sib2, iclass 28, count 2 2006.203.07:36:32.75#ibcon#flushed, iclass 28, count 2 2006.203.07:36:32.75#ibcon#about to write, iclass 28, count 2 2006.203.07:36:32.75#ibcon#wrote, iclass 28, count 2 2006.203.07:36:32.75#ibcon#about to read 3, iclass 28, count 2 2006.203.07:36:32.78#ibcon#read 3, iclass 28, count 2 2006.203.07:36:32.78#ibcon#about to read 4, iclass 28, count 2 2006.203.07:36:32.78#ibcon#read 4, iclass 28, count 2 2006.203.07:36:32.78#ibcon#about to read 5, iclass 28, count 2 2006.203.07:36:32.78#ibcon#read 5, iclass 28, count 2 2006.203.07:36:32.78#ibcon#about to read 6, iclass 28, count 2 2006.203.07:36:32.78#ibcon#read 6, iclass 28, count 2 2006.203.07:36:32.78#ibcon#end of sib2, iclass 28, count 2 2006.203.07:36:32.78#ibcon#*after write, iclass 28, count 2 2006.203.07:36:32.78#ibcon#*before return 0, iclass 28, count 2 2006.203.07:36:32.78#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.203.07:36:32.78#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.203.07:36:32.78#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.203.07:36:32.78#ibcon#ireg 7 cls_cnt 0 2006.203.07:36:32.78#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.203.07:36:32.91#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.203.07:36:32.91#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.203.07:36:32.91#ibcon#enter wrdev, iclass 28, count 0 2006.203.07:36:32.91#ibcon#first serial, iclass 28, count 0 2006.203.07:36:32.91#ibcon#enter sib2, iclass 28, count 0 2006.203.07:36:32.91#ibcon#flushed, iclass 28, count 0 2006.203.07:36:32.91#ibcon#about to write, iclass 28, count 0 2006.203.07:36:32.91#ibcon#wrote, iclass 28, count 0 2006.203.07:36:32.91#ibcon#about to read 3, iclass 28, count 0 2006.203.07:36:32.92#ibcon#read 3, iclass 28, count 0 2006.203.07:36:32.92#ibcon#about to read 4, iclass 28, count 0 2006.203.07:36:32.92#ibcon#read 4, iclass 28, count 0 2006.203.07:36:32.92#ibcon#about to read 5, iclass 28, count 0 2006.203.07:36:32.92#ibcon#read 5, iclass 28, count 0 2006.203.07:36:32.92#ibcon#about to read 6, iclass 28, count 0 2006.203.07:36:32.92#ibcon#read 6, iclass 28, count 0 2006.203.07:36:32.92#ibcon#end of sib2, iclass 28, count 0 2006.203.07:36:32.92#ibcon#*mode == 0, iclass 28, count 0 2006.203.07:36:32.92#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.203.07:36:32.92#ibcon#[27=USB\r\n] 2006.203.07:36:32.92#ibcon#*before write, iclass 28, count 0 2006.203.07:36:32.92#ibcon#enter sib2, iclass 28, count 0 2006.203.07:36:32.92#ibcon#flushed, iclass 28, count 0 2006.203.07:36:32.92#ibcon#about to write, iclass 28, count 0 2006.203.07:36:32.92#ibcon#wrote, iclass 28, count 0 2006.203.07:36:32.92#ibcon#about to read 3, iclass 28, count 0 2006.203.07:36:32.95#ibcon#read 3, iclass 28, count 0 2006.203.07:36:32.95#ibcon#about to read 4, iclass 28, count 0 2006.203.07:36:32.95#ibcon#read 4, iclass 28, count 0 2006.203.07:36:32.95#ibcon#about to read 5, iclass 28, count 0 2006.203.07:36:32.95#ibcon#read 5, iclass 28, count 0 2006.203.07:36:32.95#ibcon#about to read 6, iclass 28, count 0 2006.203.07:36:32.95#ibcon#read 6, iclass 28, count 0 2006.203.07:36:32.95#ibcon#end of sib2, iclass 28, count 0 2006.203.07:36:32.95#ibcon#*after write, iclass 28, count 0 2006.203.07:36:32.95#ibcon#*before return 0, iclass 28, count 0 2006.203.07:36:32.95#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.203.07:36:32.95#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.203.07:36:32.95#ibcon#about to clear, iclass 28 cls_cnt 0 2006.203.07:36:32.95#ibcon#cleared, iclass 28 cls_cnt 0 2006.203.07:36:32.95$vc4f8/vblo=2,640.99 2006.203.07:36:32.95#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.203.07:36:32.95#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.203.07:36:32.95#ibcon#ireg 17 cls_cnt 0 2006.203.07:36:32.95#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.203.07:36:32.95#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.203.07:36:32.95#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.203.07:36:32.95#ibcon#enter wrdev, iclass 30, count 0 2006.203.07:36:32.95#ibcon#first serial, iclass 30, count 0 2006.203.07:36:32.95#ibcon#enter sib2, iclass 30, count 0 2006.203.07:36:32.95#ibcon#flushed, iclass 30, count 0 2006.203.07:36:32.95#ibcon#about to write, iclass 30, count 0 2006.203.07:36:32.95#ibcon#wrote, iclass 30, count 0 2006.203.07:36:32.95#ibcon#about to read 3, iclass 30, count 0 2006.203.07:36:32.98#ibcon#read 3, iclass 30, count 0 2006.203.07:36:32.98#ibcon#about to read 4, iclass 30, count 0 2006.203.07:36:32.98#ibcon#read 4, iclass 30, count 0 2006.203.07:36:32.98#ibcon#about to read 5, iclass 30, count 0 2006.203.07:36:32.98#ibcon#read 5, iclass 30, count 0 2006.203.07:36:32.98#ibcon#about to read 6, iclass 30, count 0 2006.203.07:36:32.98#ibcon#read 6, iclass 30, count 0 2006.203.07:36:32.98#ibcon#end of sib2, iclass 30, count 0 2006.203.07:36:32.98#ibcon#*mode == 0, iclass 30, count 0 2006.203.07:36:32.98#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.203.07:36:32.98#ibcon#[28=FRQ=02,640.99\r\n] 2006.203.07:36:32.98#ibcon#*before write, iclass 30, count 0 2006.203.07:36:32.98#ibcon#enter sib2, iclass 30, count 0 2006.203.07:36:32.98#ibcon#flushed, iclass 30, count 0 2006.203.07:36:32.98#ibcon#about to write, iclass 30, count 0 2006.203.07:36:32.98#ibcon#wrote, iclass 30, count 0 2006.203.07:36:32.98#ibcon#about to read 3, iclass 30, count 0 2006.203.07:36:33.02#ibcon#read 3, iclass 30, count 0 2006.203.07:36:33.02#ibcon#about to read 4, iclass 30, count 0 2006.203.07:36:33.02#ibcon#read 4, iclass 30, count 0 2006.203.07:36:33.02#ibcon#about to read 5, iclass 30, count 0 2006.203.07:36:33.02#ibcon#read 5, iclass 30, count 0 2006.203.07:36:33.02#ibcon#about to read 6, iclass 30, count 0 2006.203.07:36:33.02#ibcon#read 6, iclass 30, count 0 2006.203.07:36:33.02#ibcon#end of sib2, iclass 30, count 0 2006.203.07:36:33.02#ibcon#*after write, iclass 30, count 0 2006.203.07:36:33.02#ibcon#*before return 0, iclass 30, count 0 2006.203.07:36:33.02#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.203.07:36:33.02#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.203.07:36:33.02#ibcon#about to clear, iclass 30 cls_cnt 0 2006.203.07:36:33.02#ibcon#cleared, iclass 30 cls_cnt 0 2006.203.07:36:33.02$vc4f8/vb=2,4 2006.203.07:36:33.02#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.203.07:36:33.02#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.203.07:36:33.02#ibcon#ireg 11 cls_cnt 2 2006.203.07:36:33.02#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.203.07:36:33.07#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.203.07:36:33.07#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.203.07:36:33.07#ibcon#enter wrdev, iclass 32, count 2 2006.203.07:36:33.07#ibcon#first serial, iclass 32, count 2 2006.203.07:36:33.07#ibcon#enter sib2, iclass 32, count 2 2006.203.07:36:33.07#ibcon#flushed, iclass 32, count 2 2006.203.07:36:33.07#ibcon#about to write, iclass 32, count 2 2006.203.07:36:33.07#ibcon#wrote, iclass 32, count 2 2006.203.07:36:33.07#ibcon#about to read 3, iclass 32, count 2 2006.203.07:36:33.09#ibcon#read 3, iclass 32, count 2 2006.203.07:36:33.09#ibcon#about to read 4, iclass 32, count 2 2006.203.07:36:33.09#ibcon#read 4, iclass 32, count 2 2006.203.07:36:33.09#ibcon#about to read 5, iclass 32, count 2 2006.203.07:36:33.09#ibcon#read 5, iclass 32, count 2 2006.203.07:36:33.09#ibcon#about to read 6, iclass 32, count 2 2006.203.07:36:33.09#ibcon#read 6, iclass 32, count 2 2006.203.07:36:33.09#ibcon#end of sib2, iclass 32, count 2 2006.203.07:36:33.09#ibcon#*mode == 0, iclass 32, count 2 2006.203.07:36:33.09#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.203.07:36:33.09#ibcon#[27=AT02-04\r\n] 2006.203.07:36:33.09#ibcon#*before write, iclass 32, count 2 2006.203.07:36:33.09#ibcon#enter sib2, iclass 32, count 2 2006.203.07:36:33.09#ibcon#flushed, iclass 32, count 2 2006.203.07:36:33.09#ibcon#about to write, iclass 32, count 2 2006.203.07:36:33.09#ibcon#wrote, iclass 32, count 2 2006.203.07:36:33.09#ibcon#about to read 3, iclass 32, count 2 2006.203.07:36:33.12#ibcon#read 3, iclass 32, count 2 2006.203.07:36:33.12#ibcon#about to read 4, iclass 32, count 2 2006.203.07:36:33.12#ibcon#read 4, iclass 32, count 2 2006.203.07:36:33.12#ibcon#about to read 5, iclass 32, count 2 2006.203.07:36:33.12#ibcon#read 5, iclass 32, count 2 2006.203.07:36:33.12#ibcon#about to read 6, iclass 32, count 2 2006.203.07:36:33.12#ibcon#read 6, iclass 32, count 2 2006.203.07:36:33.12#ibcon#end of sib2, iclass 32, count 2 2006.203.07:36:33.12#ibcon#*after write, iclass 32, count 2 2006.203.07:36:33.12#ibcon#*before return 0, iclass 32, count 2 2006.203.07:36:33.12#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.203.07:36:33.12#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.203.07:36:33.12#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.203.07:36:33.12#ibcon#ireg 7 cls_cnt 0 2006.203.07:36:33.12#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.203.07:36:33.24#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.203.07:36:33.24#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.203.07:36:33.24#ibcon#enter wrdev, iclass 32, count 0 2006.203.07:36:33.24#ibcon#first serial, iclass 32, count 0 2006.203.07:36:33.24#ibcon#enter sib2, iclass 32, count 0 2006.203.07:36:33.24#ibcon#flushed, iclass 32, count 0 2006.203.07:36:33.24#ibcon#about to write, iclass 32, count 0 2006.203.07:36:33.24#ibcon#wrote, iclass 32, count 0 2006.203.07:36:33.24#ibcon#about to read 3, iclass 32, count 0 2006.203.07:36:33.26#ibcon#read 3, iclass 32, count 0 2006.203.07:36:33.26#ibcon#about to read 4, iclass 32, count 0 2006.203.07:36:33.26#ibcon#read 4, iclass 32, count 0 2006.203.07:36:33.26#ibcon#about to read 5, iclass 32, count 0 2006.203.07:36:33.26#ibcon#read 5, iclass 32, count 0 2006.203.07:36:33.26#ibcon#about to read 6, iclass 32, count 0 2006.203.07:36:33.26#ibcon#read 6, iclass 32, count 0 2006.203.07:36:33.26#ibcon#end of sib2, iclass 32, count 0 2006.203.07:36:33.26#ibcon#*mode == 0, iclass 32, count 0 2006.203.07:36:33.26#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.203.07:36:33.26#ibcon#[27=USB\r\n] 2006.203.07:36:33.26#ibcon#*before write, iclass 32, count 0 2006.203.07:36:33.26#ibcon#enter sib2, iclass 32, count 0 2006.203.07:36:33.26#ibcon#flushed, iclass 32, count 0 2006.203.07:36:33.26#ibcon#about to write, iclass 32, count 0 2006.203.07:36:33.26#ibcon#wrote, iclass 32, count 0 2006.203.07:36:33.26#ibcon#about to read 3, iclass 32, count 0 2006.203.07:36:33.29#ibcon#read 3, iclass 32, count 0 2006.203.07:36:33.29#ibcon#about to read 4, iclass 32, count 0 2006.203.07:36:33.29#ibcon#read 4, iclass 32, count 0 2006.203.07:36:33.29#ibcon#about to read 5, iclass 32, count 0 2006.203.07:36:33.29#ibcon#read 5, iclass 32, count 0 2006.203.07:36:33.29#ibcon#about to read 6, iclass 32, count 0 2006.203.07:36:33.29#ibcon#read 6, iclass 32, count 0 2006.203.07:36:33.29#ibcon#end of sib2, iclass 32, count 0 2006.203.07:36:33.29#ibcon#*after write, iclass 32, count 0 2006.203.07:36:33.29#ibcon#*before return 0, iclass 32, count 0 2006.203.07:36:33.29#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.203.07:36:33.29#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.203.07:36:33.29#ibcon#about to clear, iclass 32 cls_cnt 0 2006.203.07:36:33.29#ibcon#cleared, iclass 32 cls_cnt 0 2006.203.07:36:33.29$vc4f8/vblo=3,656.99 2006.203.07:36:33.29#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.203.07:36:33.29#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.203.07:36:33.29#ibcon#ireg 17 cls_cnt 0 2006.203.07:36:33.29#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.203.07:36:33.29#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.203.07:36:33.29#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.203.07:36:33.29#ibcon#enter wrdev, iclass 34, count 0 2006.203.07:36:33.29#ibcon#first serial, iclass 34, count 0 2006.203.07:36:33.29#ibcon#enter sib2, iclass 34, count 0 2006.203.07:36:33.29#ibcon#flushed, iclass 34, count 0 2006.203.07:36:33.29#ibcon#about to write, iclass 34, count 0 2006.203.07:36:33.29#ibcon#wrote, iclass 34, count 0 2006.203.07:36:33.29#ibcon#about to read 3, iclass 34, count 0 2006.203.07:36:33.31#ibcon#read 3, iclass 34, count 0 2006.203.07:36:33.31#ibcon#about to read 4, iclass 34, count 0 2006.203.07:36:33.31#ibcon#read 4, iclass 34, count 0 2006.203.07:36:33.31#ibcon#about to read 5, iclass 34, count 0 2006.203.07:36:33.31#ibcon#read 5, iclass 34, count 0 2006.203.07:36:33.31#ibcon#about to read 6, iclass 34, count 0 2006.203.07:36:33.31#ibcon#read 6, iclass 34, count 0 2006.203.07:36:33.31#ibcon#end of sib2, iclass 34, count 0 2006.203.07:36:33.31#ibcon#*mode == 0, iclass 34, count 0 2006.203.07:36:33.31#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.203.07:36:33.31#ibcon#[28=FRQ=03,656.99\r\n] 2006.203.07:36:33.31#ibcon#*before write, iclass 34, count 0 2006.203.07:36:33.31#ibcon#enter sib2, iclass 34, count 0 2006.203.07:36:33.31#ibcon#flushed, iclass 34, count 0 2006.203.07:36:33.31#ibcon#about to write, iclass 34, count 0 2006.203.07:36:33.31#ibcon#wrote, iclass 34, count 0 2006.203.07:36:33.31#ibcon#about to read 3, iclass 34, count 0 2006.203.07:36:33.35#ibcon#read 3, iclass 34, count 0 2006.203.07:36:33.35#ibcon#about to read 4, iclass 34, count 0 2006.203.07:36:33.35#ibcon#read 4, iclass 34, count 0 2006.203.07:36:33.35#ibcon#about to read 5, iclass 34, count 0 2006.203.07:36:33.35#ibcon#read 5, iclass 34, count 0 2006.203.07:36:33.35#ibcon#about to read 6, iclass 34, count 0 2006.203.07:36:33.35#ibcon#read 6, iclass 34, count 0 2006.203.07:36:33.35#ibcon#end of sib2, iclass 34, count 0 2006.203.07:36:33.35#ibcon#*after write, iclass 34, count 0 2006.203.07:36:33.35#ibcon#*before return 0, iclass 34, count 0 2006.203.07:36:33.35#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.203.07:36:33.35#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.203.07:36:33.35#ibcon#about to clear, iclass 34 cls_cnt 0 2006.203.07:36:33.35#ibcon#cleared, iclass 34 cls_cnt 0 2006.203.07:36:33.35$vc4f8/vb=3,4 2006.203.07:36:33.35#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.203.07:36:33.35#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.203.07:36:33.35#ibcon#ireg 11 cls_cnt 2 2006.203.07:36:33.35#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.203.07:36:33.41#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.203.07:36:33.41#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.203.07:36:33.41#ibcon#enter wrdev, iclass 36, count 2 2006.203.07:36:33.41#ibcon#first serial, iclass 36, count 2 2006.203.07:36:33.41#ibcon#enter sib2, iclass 36, count 2 2006.203.07:36:33.41#ibcon#flushed, iclass 36, count 2 2006.203.07:36:33.41#ibcon#about to write, iclass 36, count 2 2006.203.07:36:33.41#ibcon#wrote, iclass 36, count 2 2006.203.07:36:33.41#ibcon#about to read 3, iclass 36, count 2 2006.203.07:36:33.43#ibcon#read 3, iclass 36, count 2 2006.203.07:36:33.43#ibcon#about to read 4, iclass 36, count 2 2006.203.07:36:33.43#ibcon#read 4, iclass 36, count 2 2006.203.07:36:33.43#ibcon#about to read 5, iclass 36, count 2 2006.203.07:36:33.43#ibcon#read 5, iclass 36, count 2 2006.203.07:36:33.43#ibcon#about to read 6, iclass 36, count 2 2006.203.07:36:33.43#ibcon#read 6, iclass 36, count 2 2006.203.07:36:33.43#ibcon#end of sib2, iclass 36, count 2 2006.203.07:36:33.43#ibcon#*mode == 0, iclass 36, count 2 2006.203.07:36:33.43#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.203.07:36:33.43#ibcon#[27=AT03-04\r\n] 2006.203.07:36:33.43#ibcon#*before write, iclass 36, count 2 2006.203.07:36:33.43#ibcon#enter sib2, iclass 36, count 2 2006.203.07:36:33.43#ibcon#flushed, iclass 36, count 2 2006.203.07:36:33.43#ibcon#about to write, iclass 36, count 2 2006.203.07:36:33.43#ibcon#wrote, iclass 36, count 2 2006.203.07:36:33.43#ibcon#about to read 3, iclass 36, count 2 2006.203.07:36:33.46#ibcon#read 3, iclass 36, count 2 2006.203.07:36:33.46#ibcon#about to read 4, iclass 36, count 2 2006.203.07:36:33.46#ibcon#read 4, iclass 36, count 2 2006.203.07:36:33.46#ibcon#about to read 5, iclass 36, count 2 2006.203.07:36:33.46#ibcon#read 5, iclass 36, count 2 2006.203.07:36:33.46#ibcon#about to read 6, iclass 36, count 2 2006.203.07:36:33.46#ibcon#read 6, iclass 36, count 2 2006.203.07:36:33.46#ibcon#end of sib2, iclass 36, count 2 2006.203.07:36:33.46#ibcon#*after write, iclass 36, count 2 2006.203.07:36:33.46#ibcon#*before return 0, iclass 36, count 2 2006.203.07:36:33.46#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.203.07:36:33.46#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.203.07:36:33.46#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.203.07:36:33.46#ibcon#ireg 7 cls_cnt 0 2006.203.07:36:33.46#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.203.07:36:33.58#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.203.07:36:33.58#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.203.07:36:33.58#ibcon#enter wrdev, iclass 36, count 0 2006.203.07:36:33.58#ibcon#first serial, iclass 36, count 0 2006.203.07:36:33.58#ibcon#enter sib2, iclass 36, count 0 2006.203.07:36:33.58#ibcon#flushed, iclass 36, count 0 2006.203.07:36:33.58#ibcon#about to write, iclass 36, count 0 2006.203.07:36:33.58#ibcon#wrote, iclass 36, count 0 2006.203.07:36:33.58#ibcon#about to read 3, iclass 36, count 0 2006.203.07:36:33.60#ibcon#read 3, iclass 36, count 0 2006.203.07:36:33.60#ibcon#about to read 4, iclass 36, count 0 2006.203.07:36:33.60#ibcon#read 4, iclass 36, count 0 2006.203.07:36:33.60#ibcon#about to read 5, iclass 36, count 0 2006.203.07:36:33.60#ibcon#read 5, iclass 36, count 0 2006.203.07:36:33.60#ibcon#about to read 6, iclass 36, count 0 2006.203.07:36:33.60#ibcon#read 6, iclass 36, count 0 2006.203.07:36:33.60#ibcon#end of sib2, iclass 36, count 0 2006.203.07:36:33.60#ibcon#*mode == 0, iclass 36, count 0 2006.203.07:36:33.60#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.203.07:36:33.60#ibcon#[27=USB\r\n] 2006.203.07:36:33.60#ibcon#*before write, iclass 36, count 0 2006.203.07:36:33.60#ibcon#enter sib2, iclass 36, count 0 2006.203.07:36:33.60#ibcon#flushed, iclass 36, count 0 2006.203.07:36:33.60#ibcon#about to write, iclass 36, count 0 2006.203.07:36:33.60#ibcon#wrote, iclass 36, count 0 2006.203.07:36:33.60#ibcon#about to read 3, iclass 36, count 0 2006.203.07:36:33.63#ibcon#read 3, iclass 36, count 0 2006.203.07:36:33.63#ibcon#about to read 4, iclass 36, count 0 2006.203.07:36:33.63#ibcon#read 4, iclass 36, count 0 2006.203.07:36:33.63#ibcon#about to read 5, iclass 36, count 0 2006.203.07:36:33.63#ibcon#read 5, iclass 36, count 0 2006.203.07:36:33.63#ibcon#about to read 6, iclass 36, count 0 2006.203.07:36:33.63#ibcon#read 6, iclass 36, count 0 2006.203.07:36:33.63#ibcon#end of sib2, iclass 36, count 0 2006.203.07:36:33.63#ibcon#*after write, iclass 36, count 0 2006.203.07:36:33.63#ibcon#*before return 0, iclass 36, count 0 2006.203.07:36:33.63#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.203.07:36:33.63#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.203.07:36:33.63#ibcon#about to clear, iclass 36 cls_cnt 0 2006.203.07:36:33.63#ibcon#cleared, iclass 36 cls_cnt 0 2006.203.07:36:33.63$vc4f8/vblo=4,712.99 2006.203.07:36:33.63#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.203.07:36:33.63#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.203.07:36:33.63#ibcon#ireg 17 cls_cnt 0 2006.203.07:36:33.63#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.203.07:36:33.63#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.203.07:36:33.63#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.203.07:36:33.63#ibcon#enter wrdev, iclass 38, count 0 2006.203.07:36:33.63#ibcon#first serial, iclass 38, count 0 2006.203.07:36:33.63#ibcon#enter sib2, iclass 38, count 0 2006.203.07:36:33.63#ibcon#flushed, iclass 38, count 0 2006.203.07:36:33.63#ibcon#about to write, iclass 38, count 0 2006.203.07:36:33.63#ibcon#wrote, iclass 38, count 0 2006.203.07:36:33.63#ibcon#about to read 3, iclass 38, count 0 2006.203.07:36:33.66#ibcon#read 3, iclass 38, count 0 2006.203.07:36:33.66#ibcon#about to read 4, iclass 38, count 0 2006.203.07:36:33.66#ibcon#read 4, iclass 38, count 0 2006.203.07:36:33.66#ibcon#about to read 5, iclass 38, count 0 2006.203.07:36:33.66#ibcon#read 5, iclass 38, count 0 2006.203.07:36:33.66#ibcon#about to read 6, iclass 38, count 0 2006.203.07:36:33.66#ibcon#read 6, iclass 38, count 0 2006.203.07:36:33.66#ibcon#end of sib2, iclass 38, count 0 2006.203.07:36:33.66#ibcon#*mode == 0, iclass 38, count 0 2006.203.07:36:33.66#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.203.07:36:33.66#ibcon#[28=FRQ=04,712.99\r\n] 2006.203.07:36:33.66#ibcon#*before write, iclass 38, count 0 2006.203.07:36:33.66#ibcon#enter sib2, iclass 38, count 0 2006.203.07:36:33.66#ibcon#flushed, iclass 38, count 0 2006.203.07:36:33.66#ibcon#about to write, iclass 38, count 0 2006.203.07:36:33.66#ibcon#wrote, iclass 38, count 0 2006.203.07:36:33.66#ibcon#about to read 3, iclass 38, count 0 2006.203.07:36:33.70#ibcon#read 3, iclass 38, count 0 2006.203.07:36:33.70#ibcon#about to read 4, iclass 38, count 0 2006.203.07:36:33.70#ibcon#read 4, iclass 38, count 0 2006.203.07:36:33.70#ibcon#about to read 5, iclass 38, count 0 2006.203.07:36:33.70#ibcon#read 5, iclass 38, count 0 2006.203.07:36:33.70#ibcon#about to read 6, iclass 38, count 0 2006.203.07:36:33.70#ibcon#read 6, iclass 38, count 0 2006.203.07:36:33.70#ibcon#end of sib2, iclass 38, count 0 2006.203.07:36:33.70#ibcon#*after write, iclass 38, count 0 2006.203.07:36:33.70#ibcon#*before return 0, iclass 38, count 0 2006.203.07:36:33.70#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.203.07:36:33.70#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.203.07:36:33.70#ibcon#about to clear, iclass 38 cls_cnt 0 2006.203.07:36:33.70#ibcon#cleared, iclass 38 cls_cnt 0 2006.203.07:36:33.70$vc4f8/vb=4,4 2006.203.07:36:33.70#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.203.07:36:33.70#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.203.07:36:33.70#ibcon#ireg 11 cls_cnt 2 2006.203.07:36:33.70#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.203.07:36:33.76#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.203.07:36:33.76#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.203.07:36:33.76#ibcon#enter wrdev, iclass 40, count 2 2006.203.07:36:33.76#ibcon#first serial, iclass 40, count 2 2006.203.07:36:33.76#ibcon#enter sib2, iclass 40, count 2 2006.203.07:36:33.76#ibcon#flushed, iclass 40, count 2 2006.203.07:36:33.76#ibcon#about to write, iclass 40, count 2 2006.203.07:36:33.76#ibcon#wrote, iclass 40, count 2 2006.203.07:36:33.76#ibcon#about to read 3, iclass 40, count 2 2006.203.07:36:33.77#ibcon#read 3, iclass 40, count 2 2006.203.07:36:33.77#ibcon#about to read 4, iclass 40, count 2 2006.203.07:36:33.77#ibcon#read 4, iclass 40, count 2 2006.203.07:36:33.77#ibcon#about to read 5, iclass 40, count 2 2006.203.07:36:33.77#ibcon#read 5, iclass 40, count 2 2006.203.07:36:33.77#ibcon#about to read 6, iclass 40, count 2 2006.203.07:36:33.77#ibcon#read 6, iclass 40, count 2 2006.203.07:36:33.77#ibcon#end of sib2, iclass 40, count 2 2006.203.07:36:33.77#ibcon#*mode == 0, iclass 40, count 2 2006.203.07:36:33.77#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.203.07:36:33.77#ibcon#[27=AT04-04\r\n] 2006.203.07:36:33.77#ibcon#*before write, iclass 40, count 2 2006.203.07:36:33.77#ibcon#enter sib2, iclass 40, count 2 2006.203.07:36:33.77#ibcon#flushed, iclass 40, count 2 2006.203.07:36:33.77#ibcon#about to write, iclass 40, count 2 2006.203.07:36:33.77#ibcon#wrote, iclass 40, count 2 2006.203.07:36:33.77#ibcon#about to read 3, iclass 40, count 2 2006.203.07:36:33.80#ibcon#read 3, iclass 40, count 2 2006.203.07:36:33.80#ibcon#about to read 4, iclass 40, count 2 2006.203.07:36:33.80#ibcon#read 4, iclass 40, count 2 2006.203.07:36:33.80#ibcon#about to read 5, iclass 40, count 2 2006.203.07:36:33.80#ibcon#read 5, iclass 40, count 2 2006.203.07:36:33.80#ibcon#about to read 6, iclass 40, count 2 2006.203.07:36:33.80#ibcon#read 6, iclass 40, count 2 2006.203.07:36:33.80#ibcon#end of sib2, iclass 40, count 2 2006.203.07:36:33.80#ibcon#*after write, iclass 40, count 2 2006.203.07:36:33.80#ibcon#*before return 0, iclass 40, count 2 2006.203.07:36:33.80#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.203.07:36:33.80#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.203.07:36:33.80#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.203.07:36:33.80#ibcon#ireg 7 cls_cnt 0 2006.203.07:36:33.80#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.203.07:36:33.92#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.203.07:36:33.92#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.203.07:36:33.92#ibcon#enter wrdev, iclass 40, count 0 2006.203.07:36:33.92#ibcon#first serial, iclass 40, count 0 2006.203.07:36:33.92#ibcon#enter sib2, iclass 40, count 0 2006.203.07:36:33.92#ibcon#flushed, iclass 40, count 0 2006.203.07:36:33.92#ibcon#about to write, iclass 40, count 0 2006.203.07:36:33.92#ibcon#wrote, iclass 40, count 0 2006.203.07:36:33.92#ibcon#about to read 3, iclass 40, count 0 2006.203.07:36:33.94#ibcon#read 3, iclass 40, count 0 2006.203.07:36:33.94#ibcon#about to read 4, iclass 40, count 0 2006.203.07:36:33.94#ibcon#read 4, iclass 40, count 0 2006.203.07:36:33.94#ibcon#about to read 5, iclass 40, count 0 2006.203.07:36:33.94#ibcon#read 5, iclass 40, count 0 2006.203.07:36:33.94#ibcon#about to read 6, iclass 40, count 0 2006.203.07:36:33.94#ibcon#read 6, iclass 40, count 0 2006.203.07:36:33.94#ibcon#end of sib2, iclass 40, count 0 2006.203.07:36:33.94#ibcon#*mode == 0, iclass 40, count 0 2006.203.07:36:33.94#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.203.07:36:33.94#ibcon#[27=USB\r\n] 2006.203.07:36:33.94#ibcon#*before write, iclass 40, count 0 2006.203.07:36:33.94#ibcon#enter sib2, iclass 40, count 0 2006.203.07:36:33.94#ibcon#flushed, iclass 40, count 0 2006.203.07:36:33.94#ibcon#about to write, iclass 40, count 0 2006.203.07:36:33.94#ibcon#wrote, iclass 40, count 0 2006.203.07:36:33.94#ibcon#about to read 3, iclass 40, count 0 2006.203.07:36:33.97#ibcon#read 3, iclass 40, count 0 2006.203.07:36:33.97#ibcon#about to read 4, iclass 40, count 0 2006.203.07:36:33.97#ibcon#read 4, iclass 40, count 0 2006.203.07:36:33.97#ibcon#about to read 5, iclass 40, count 0 2006.203.07:36:33.97#ibcon#read 5, iclass 40, count 0 2006.203.07:36:33.97#ibcon#about to read 6, iclass 40, count 0 2006.203.07:36:33.97#ibcon#read 6, iclass 40, count 0 2006.203.07:36:33.97#ibcon#end of sib2, iclass 40, count 0 2006.203.07:36:33.97#ibcon#*after write, iclass 40, count 0 2006.203.07:36:33.97#ibcon#*before return 0, iclass 40, count 0 2006.203.07:36:33.97#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.203.07:36:33.97#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.203.07:36:33.97#ibcon#about to clear, iclass 40 cls_cnt 0 2006.203.07:36:33.97#ibcon#cleared, iclass 40 cls_cnt 0 2006.203.07:36:33.97$vc4f8/vblo=5,744.99 2006.203.07:36:33.97#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.203.07:36:33.97#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.203.07:36:33.97#ibcon#ireg 17 cls_cnt 0 2006.203.07:36:33.97#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.203.07:36:33.97#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.203.07:36:33.97#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.203.07:36:33.97#ibcon#enter wrdev, iclass 4, count 0 2006.203.07:36:33.97#ibcon#first serial, iclass 4, count 0 2006.203.07:36:33.97#ibcon#enter sib2, iclass 4, count 0 2006.203.07:36:33.97#ibcon#flushed, iclass 4, count 0 2006.203.07:36:33.97#ibcon#about to write, iclass 4, count 0 2006.203.07:36:33.97#ibcon#wrote, iclass 4, count 0 2006.203.07:36:33.97#ibcon#about to read 3, iclass 4, count 0 2006.203.07:36:33.99#ibcon#read 3, iclass 4, count 0 2006.203.07:36:33.99#ibcon#about to read 4, iclass 4, count 0 2006.203.07:36:33.99#ibcon#read 4, iclass 4, count 0 2006.203.07:36:33.99#ibcon#about to read 5, iclass 4, count 0 2006.203.07:36:33.99#ibcon#read 5, iclass 4, count 0 2006.203.07:36:33.99#ibcon#about to read 6, iclass 4, count 0 2006.203.07:36:33.99#ibcon#read 6, iclass 4, count 0 2006.203.07:36:33.99#ibcon#end of sib2, iclass 4, count 0 2006.203.07:36:33.99#ibcon#*mode == 0, iclass 4, count 0 2006.203.07:36:33.99#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.203.07:36:33.99#ibcon#[28=FRQ=05,744.99\r\n] 2006.203.07:36:33.99#ibcon#*before write, iclass 4, count 0 2006.203.07:36:33.99#ibcon#enter sib2, iclass 4, count 0 2006.203.07:36:33.99#ibcon#flushed, iclass 4, count 0 2006.203.07:36:33.99#ibcon#about to write, iclass 4, count 0 2006.203.07:36:33.99#ibcon#wrote, iclass 4, count 0 2006.203.07:36:33.99#ibcon#about to read 3, iclass 4, count 0 2006.203.07:36:34.03#ibcon#read 3, iclass 4, count 0 2006.203.07:36:34.03#ibcon#about to read 4, iclass 4, count 0 2006.203.07:36:34.03#ibcon#read 4, iclass 4, count 0 2006.203.07:36:34.03#ibcon#about to read 5, iclass 4, count 0 2006.203.07:36:34.03#ibcon#read 5, iclass 4, count 0 2006.203.07:36:34.03#ibcon#about to read 6, iclass 4, count 0 2006.203.07:36:34.03#ibcon#read 6, iclass 4, count 0 2006.203.07:36:34.03#ibcon#end of sib2, iclass 4, count 0 2006.203.07:36:34.03#ibcon#*after write, iclass 4, count 0 2006.203.07:36:34.03#ibcon#*before return 0, iclass 4, count 0 2006.203.07:36:34.03#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.203.07:36:34.03#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.203.07:36:34.03#ibcon#about to clear, iclass 4 cls_cnt 0 2006.203.07:36:34.03#ibcon#cleared, iclass 4 cls_cnt 0 2006.203.07:36:34.03$vc4f8/vb=5,3 2006.203.07:36:34.03#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.203.07:36:34.03#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.203.07:36:34.03#ibcon#ireg 11 cls_cnt 2 2006.203.07:36:34.03#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.203.07:36:34.09#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.203.07:36:34.09#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.203.07:36:34.09#ibcon#enter wrdev, iclass 6, count 2 2006.203.07:36:34.09#ibcon#first serial, iclass 6, count 2 2006.203.07:36:34.09#ibcon#enter sib2, iclass 6, count 2 2006.203.07:36:34.09#ibcon#flushed, iclass 6, count 2 2006.203.07:36:34.09#ibcon#about to write, iclass 6, count 2 2006.203.07:36:34.09#ibcon#wrote, iclass 6, count 2 2006.203.07:36:34.09#ibcon#about to read 3, iclass 6, count 2 2006.203.07:36:34.11#ibcon#read 3, iclass 6, count 2 2006.203.07:36:34.11#ibcon#about to read 4, iclass 6, count 2 2006.203.07:36:34.11#ibcon#read 4, iclass 6, count 2 2006.203.07:36:34.11#ibcon#about to read 5, iclass 6, count 2 2006.203.07:36:34.11#ibcon#read 5, iclass 6, count 2 2006.203.07:36:34.11#ibcon#about to read 6, iclass 6, count 2 2006.203.07:36:34.11#ibcon#read 6, iclass 6, count 2 2006.203.07:36:34.11#ibcon#end of sib2, iclass 6, count 2 2006.203.07:36:34.11#ibcon#*mode == 0, iclass 6, count 2 2006.203.07:36:34.11#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.203.07:36:34.11#ibcon#[27=AT05-03\r\n] 2006.203.07:36:34.11#ibcon#*before write, iclass 6, count 2 2006.203.07:36:34.11#ibcon#enter sib2, iclass 6, count 2 2006.203.07:36:34.11#ibcon#flushed, iclass 6, count 2 2006.203.07:36:34.11#ibcon#about to write, iclass 6, count 2 2006.203.07:36:34.11#ibcon#wrote, iclass 6, count 2 2006.203.07:36:34.11#ibcon#about to read 3, iclass 6, count 2 2006.203.07:36:34.14#ibcon#read 3, iclass 6, count 2 2006.203.07:36:34.14#ibcon#about to read 4, iclass 6, count 2 2006.203.07:36:34.14#ibcon#read 4, iclass 6, count 2 2006.203.07:36:34.14#ibcon#about to read 5, iclass 6, count 2 2006.203.07:36:34.14#ibcon#read 5, iclass 6, count 2 2006.203.07:36:34.14#ibcon#about to read 6, iclass 6, count 2 2006.203.07:36:34.14#ibcon#read 6, iclass 6, count 2 2006.203.07:36:34.14#ibcon#end of sib2, iclass 6, count 2 2006.203.07:36:34.14#ibcon#*after write, iclass 6, count 2 2006.203.07:36:34.14#ibcon#*before return 0, iclass 6, count 2 2006.203.07:36:34.14#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.203.07:36:34.14#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.203.07:36:34.14#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.203.07:36:34.14#ibcon#ireg 7 cls_cnt 0 2006.203.07:36:34.14#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.203.07:36:34.26#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.203.07:36:34.26#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.203.07:36:34.26#ibcon#enter wrdev, iclass 6, count 0 2006.203.07:36:34.26#ibcon#first serial, iclass 6, count 0 2006.203.07:36:34.26#ibcon#enter sib2, iclass 6, count 0 2006.203.07:36:34.26#ibcon#flushed, iclass 6, count 0 2006.203.07:36:34.26#ibcon#about to write, iclass 6, count 0 2006.203.07:36:34.26#ibcon#wrote, iclass 6, count 0 2006.203.07:36:34.26#ibcon#about to read 3, iclass 6, count 0 2006.203.07:36:34.28#ibcon#read 3, iclass 6, count 0 2006.203.07:36:34.28#ibcon#about to read 4, iclass 6, count 0 2006.203.07:36:34.28#ibcon#read 4, iclass 6, count 0 2006.203.07:36:34.28#ibcon#about to read 5, iclass 6, count 0 2006.203.07:36:34.28#ibcon#read 5, iclass 6, count 0 2006.203.07:36:34.28#ibcon#about to read 6, iclass 6, count 0 2006.203.07:36:34.28#ibcon#read 6, iclass 6, count 0 2006.203.07:36:34.28#ibcon#end of sib2, iclass 6, count 0 2006.203.07:36:34.28#ibcon#*mode == 0, iclass 6, count 0 2006.203.07:36:34.28#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.203.07:36:34.28#ibcon#[27=USB\r\n] 2006.203.07:36:34.28#ibcon#*before write, iclass 6, count 0 2006.203.07:36:34.28#ibcon#enter sib2, iclass 6, count 0 2006.203.07:36:34.28#ibcon#flushed, iclass 6, count 0 2006.203.07:36:34.28#ibcon#about to write, iclass 6, count 0 2006.203.07:36:34.28#ibcon#wrote, iclass 6, count 0 2006.203.07:36:34.28#ibcon#about to read 3, iclass 6, count 0 2006.203.07:36:34.31#ibcon#read 3, iclass 6, count 0 2006.203.07:36:34.31#ibcon#about to read 4, iclass 6, count 0 2006.203.07:36:34.31#ibcon#read 4, iclass 6, count 0 2006.203.07:36:34.31#ibcon#about to read 5, iclass 6, count 0 2006.203.07:36:34.31#ibcon#read 5, iclass 6, count 0 2006.203.07:36:34.31#ibcon#about to read 6, iclass 6, count 0 2006.203.07:36:34.31#ibcon#read 6, iclass 6, count 0 2006.203.07:36:34.31#ibcon#end of sib2, iclass 6, count 0 2006.203.07:36:34.31#ibcon#*after write, iclass 6, count 0 2006.203.07:36:34.31#ibcon#*before return 0, iclass 6, count 0 2006.203.07:36:34.31#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.203.07:36:34.31#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.203.07:36:34.31#ibcon#about to clear, iclass 6 cls_cnt 0 2006.203.07:36:34.31#ibcon#cleared, iclass 6 cls_cnt 0 2006.203.07:36:34.31$vc4f8/vblo=6,752.99 2006.203.07:36:34.31#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.203.07:36:34.31#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.203.07:36:34.31#ibcon#ireg 17 cls_cnt 0 2006.203.07:36:34.31#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.203.07:36:34.31#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.203.07:36:34.31#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.203.07:36:34.31#ibcon#enter wrdev, iclass 10, count 0 2006.203.07:36:34.31#ibcon#first serial, iclass 10, count 0 2006.203.07:36:34.31#ibcon#enter sib2, iclass 10, count 0 2006.203.07:36:34.31#ibcon#flushed, iclass 10, count 0 2006.203.07:36:34.31#ibcon#about to write, iclass 10, count 0 2006.203.07:36:34.31#ibcon#wrote, iclass 10, count 0 2006.203.07:36:34.31#ibcon#about to read 3, iclass 10, count 0 2006.203.07:36:34.34#ibcon#read 3, iclass 10, count 0 2006.203.07:36:34.34#ibcon#about to read 4, iclass 10, count 0 2006.203.07:36:34.34#ibcon#read 4, iclass 10, count 0 2006.203.07:36:34.34#ibcon#about to read 5, iclass 10, count 0 2006.203.07:36:34.34#ibcon#read 5, iclass 10, count 0 2006.203.07:36:34.34#ibcon#about to read 6, iclass 10, count 0 2006.203.07:36:34.34#ibcon#read 6, iclass 10, count 0 2006.203.07:36:34.34#ibcon#end of sib2, iclass 10, count 0 2006.203.07:36:34.34#ibcon#*mode == 0, iclass 10, count 0 2006.203.07:36:34.34#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.203.07:36:34.34#ibcon#[28=FRQ=06,752.99\r\n] 2006.203.07:36:34.34#ibcon#*before write, iclass 10, count 0 2006.203.07:36:34.34#ibcon#enter sib2, iclass 10, count 0 2006.203.07:36:34.34#ibcon#flushed, iclass 10, count 0 2006.203.07:36:34.34#ibcon#about to write, iclass 10, count 0 2006.203.07:36:34.34#ibcon#wrote, iclass 10, count 0 2006.203.07:36:34.34#ibcon#about to read 3, iclass 10, count 0 2006.203.07:36:34.38#ibcon#read 3, iclass 10, count 0 2006.203.07:36:34.38#ibcon#about to read 4, iclass 10, count 0 2006.203.07:36:34.38#ibcon#read 4, iclass 10, count 0 2006.203.07:36:34.38#ibcon#about to read 5, iclass 10, count 0 2006.203.07:36:34.38#ibcon#read 5, iclass 10, count 0 2006.203.07:36:34.38#ibcon#about to read 6, iclass 10, count 0 2006.203.07:36:34.38#ibcon#read 6, iclass 10, count 0 2006.203.07:36:34.38#ibcon#end of sib2, iclass 10, count 0 2006.203.07:36:34.38#ibcon#*after write, iclass 10, count 0 2006.203.07:36:34.38#ibcon#*before return 0, iclass 10, count 0 2006.203.07:36:34.38#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.203.07:36:34.38#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.203.07:36:34.38#ibcon#about to clear, iclass 10 cls_cnt 0 2006.203.07:36:34.38#ibcon#cleared, iclass 10 cls_cnt 0 2006.203.07:36:34.38$vc4f8/vb=6,4 2006.203.07:36:34.38#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.203.07:36:34.38#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.203.07:36:34.38#ibcon#ireg 11 cls_cnt 2 2006.203.07:36:34.38#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.203.07:36:34.44#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.203.07:36:34.44#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.203.07:36:34.44#ibcon#enter wrdev, iclass 12, count 2 2006.203.07:36:34.44#ibcon#first serial, iclass 12, count 2 2006.203.07:36:34.44#ibcon#enter sib2, iclass 12, count 2 2006.203.07:36:34.44#ibcon#flushed, iclass 12, count 2 2006.203.07:36:34.44#ibcon#about to write, iclass 12, count 2 2006.203.07:36:34.44#ibcon#wrote, iclass 12, count 2 2006.203.07:36:34.44#ibcon#about to read 3, iclass 12, count 2 2006.203.07:36:34.45#ibcon#read 3, iclass 12, count 2 2006.203.07:36:34.45#ibcon#about to read 4, iclass 12, count 2 2006.203.07:36:34.45#ibcon#read 4, iclass 12, count 2 2006.203.07:36:34.45#ibcon#about to read 5, iclass 12, count 2 2006.203.07:36:34.45#ibcon#read 5, iclass 12, count 2 2006.203.07:36:34.45#ibcon#about to read 6, iclass 12, count 2 2006.203.07:36:34.45#ibcon#read 6, iclass 12, count 2 2006.203.07:36:34.45#ibcon#end of sib2, iclass 12, count 2 2006.203.07:36:34.45#ibcon#*mode == 0, iclass 12, count 2 2006.203.07:36:34.45#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.203.07:36:34.45#ibcon#[27=AT06-04\r\n] 2006.203.07:36:34.45#ibcon#*before write, iclass 12, count 2 2006.203.07:36:34.45#ibcon#enter sib2, iclass 12, count 2 2006.203.07:36:34.45#ibcon#flushed, iclass 12, count 2 2006.203.07:36:34.45#ibcon#about to write, iclass 12, count 2 2006.203.07:36:34.45#ibcon#wrote, iclass 12, count 2 2006.203.07:36:34.45#ibcon#about to read 3, iclass 12, count 2 2006.203.07:36:34.48#ibcon#read 3, iclass 12, count 2 2006.203.07:36:34.48#ibcon#about to read 4, iclass 12, count 2 2006.203.07:36:34.48#ibcon#read 4, iclass 12, count 2 2006.203.07:36:34.48#ibcon#about to read 5, iclass 12, count 2 2006.203.07:36:34.48#ibcon#read 5, iclass 12, count 2 2006.203.07:36:34.48#ibcon#about to read 6, iclass 12, count 2 2006.203.07:36:34.48#ibcon#read 6, iclass 12, count 2 2006.203.07:36:34.48#ibcon#end of sib2, iclass 12, count 2 2006.203.07:36:34.48#ibcon#*after write, iclass 12, count 2 2006.203.07:36:34.48#ibcon#*before return 0, iclass 12, count 2 2006.203.07:36:34.48#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.203.07:36:34.48#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.203.07:36:34.48#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.203.07:36:34.48#ibcon#ireg 7 cls_cnt 0 2006.203.07:36:34.48#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.203.07:36:34.60#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.203.07:36:34.60#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.203.07:36:34.60#ibcon#enter wrdev, iclass 12, count 0 2006.203.07:36:34.60#ibcon#first serial, iclass 12, count 0 2006.203.07:36:34.60#ibcon#enter sib2, iclass 12, count 0 2006.203.07:36:34.60#ibcon#flushed, iclass 12, count 0 2006.203.07:36:34.60#ibcon#about to write, iclass 12, count 0 2006.203.07:36:34.60#ibcon#wrote, iclass 12, count 0 2006.203.07:36:34.60#ibcon#about to read 3, iclass 12, count 0 2006.203.07:36:34.62#ibcon#read 3, iclass 12, count 0 2006.203.07:36:34.62#ibcon#about to read 4, iclass 12, count 0 2006.203.07:36:34.62#ibcon#read 4, iclass 12, count 0 2006.203.07:36:34.62#ibcon#about to read 5, iclass 12, count 0 2006.203.07:36:34.62#ibcon#read 5, iclass 12, count 0 2006.203.07:36:34.62#ibcon#about to read 6, iclass 12, count 0 2006.203.07:36:34.62#ibcon#read 6, iclass 12, count 0 2006.203.07:36:34.62#ibcon#end of sib2, iclass 12, count 0 2006.203.07:36:34.62#ibcon#*mode == 0, iclass 12, count 0 2006.203.07:36:34.62#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.203.07:36:34.62#ibcon#[27=USB\r\n] 2006.203.07:36:34.62#ibcon#*before write, iclass 12, count 0 2006.203.07:36:34.62#ibcon#enter sib2, iclass 12, count 0 2006.203.07:36:34.62#ibcon#flushed, iclass 12, count 0 2006.203.07:36:34.62#ibcon#about to write, iclass 12, count 0 2006.203.07:36:34.62#ibcon#wrote, iclass 12, count 0 2006.203.07:36:34.62#ibcon#about to read 3, iclass 12, count 0 2006.203.07:36:34.65#ibcon#read 3, iclass 12, count 0 2006.203.07:36:34.65#ibcon#about to read 4, iclass 12, count 0 2006.203.07:36:34.65#ibcon#read 4, iclass 12, count 0 2006.203.07:36:34.65#ibcon#about to read 5, iclass 12, count 0 2006.203.07:36:34.65#ibcon#read 5, iclass 12, count 0 2006.203.07:36:34.65#ibcon#about to read 6, iclass 12, count 0 2006.203.07:36:34.65#ibcon#read 6, iclass 12, count 0 2006.203.07:36:34.65#ibcon#end of sib2, iclass 12, count 0 2006.203.07:36:34.65#ibcon#*after write, iclass 12, count 0 2006.203.07:36:34.65#ibcon#*before return 0, iclass 12, count 0 2006.203.07:36:34.65#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.203.07:36:34.65#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.203.07:36:34.65#ibcon#about to clear, iclass 12 cls_cnt 0 2006.203.07:36:34.65#ibcon#cleared, iclass 12 cls_cnt 0 2006.203.07:36:34.65$vc4f8/vabw=wide 2006.203.07:36:34.65#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.203.07:36:34.65#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.203.07:36:34.65#ibcon#ireg 8 cls_cnt 0 2006.203.07:36:34.65#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.203.07:36:34.65#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.203.07:36:34.65#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.203.07:36:34.65#ibcon#enter wrdev, iclass 14, count 0 2006.203.07:36:34.65#ibcon#first serial, iclass 14, count 0 2006.203.07:36:34.65#ibcon#enter sib2, iclass 14, count 0 2006.203.07:36:34.65#ibcon#flushed, iclass 14, count 0 2006.203.07:36:34.65#ibcon#about to write, iclass 14, count 0 2006.203.07:36:34.65#ibcon#wrote, iclass 14, count 0 2006.203.07:36:34.65#ibcon#about to read 3, iclass 14, count 0 2006.203.07:36:34.67#ibcon#read 3, iclass 14, count 0 2006.203.07:36:34.67#ibcon#about to read 4, iclass 14, count 0 2006.203.07:36:34.67#ibcon#read 4, iclass 14, count 0 2006.203.07:36:34.67#ibcon#about to read 5, iclass 14, count 0 2006.203.07:36:34.67#ibcon#read 5, iclass 14, count 0 2006.203.07:36:34.67#ibcon#about to read 6, iclass 14, count 0 2006.203.07:36:34.67#ibcon#read 6, iclass 14, count 0 2006.203.07:36:34.67#ibcon#end of sib2, iclass 14, count 0 2006.203.07:36:34.67#ibcon#*mode == 0, iclass 14, count 0 2006.203.07:36:34.67#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.203.07:36:34.67#ibcon#[25=BW32\r\n] 2006.203.07:36:34.67#ibcon#*before write, iclass 14, count 0 2006.203.07:36:34.67#ibcon#enter sib2, iclass 14, count 0 2006.203.07:36:34.67#ibcon#flushed, iclass 14, count 0 2006.203.07:36:34.67#ibcon#about to write, iclass 14, count 0 2006.203.07:36:34.67#ibcon#wrote, iclass 14, count 0 2006.203.07:36:34.67#ibcon#about to read 3, iclass 14, count 0 2006.203.07:36:34.70#ibcon#read 3, iclass 14, count 0 2006.203.07:36:34.70#ibcon#about to read 4, iclass 14, count 0 2006.203.07:36:34.70#ibcon#read 4, iclass 14, count 0 2006.203.07:36:34.70#ibcon#about to read 5, iclass 14, count 0 2006.203.07:36:34.70#ibcon#read 5, iclass 14, count 0 2006.203.07:36:34.70#ibcon#about to read 6, iclass 14, count 0 2006.203.07:36:34.70#ibcon#read 6, iclass 14, count 0 2006.203.07:36:34.70#ibcon#end of sib2, iclass 14, count 0 2006.203.07:36:34.70#ibcon#*after write, iclass 14, count 0 2006.203.07:36:34.70#ibcon#*before return 0, iclass 14, count 0 2006.203.07:36:34.70#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.203.07:36:34.70#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.203.07:36:34.70#ibcon#about to clear, iclass 14 cls_cnt 0 2006.203.07:36:34.70#ibcon#cleared, iclass 14 cls_cnt 0 2006.203.07:36:34.70$vc4f8/vbbw=wide 2006.203.07:36:34.70#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.203.07:36:34.70#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.203.07:36:34.70#ibcon#ireg 8 cls_cnt 0 2006.203.07:36:34.70#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.203.07:36:34.77#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.203.07:36:34.77#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.203.07:36:34.77#ibcon#enter wrdev, iclass 16, count 0 2006.203.07:36:34.77#ibcon#first serial, iclass 16, count 0 2006.203.07:36:34.77#ibcon#enter sib2, iclass 16, count 0 2006.203.07:36:34.77#ibcon#flushed, iclass 16, count 0 2006.203.07:36:34.77#ibcon#about to write, iclass 16, count 0 2006.203.07:36:34.77#ibcon#wrote, iclass 16, count 0 2006.203.07:36:34.77#ibcon#about to read 3, iclass 16, count 0 2006.203.07:36:34.79#ibcon#read 3, iclass 16, count 0 2006.203.07:36:34.79#ibcon#about to read 4, iclass 16, count 0 2006.203.07:36:34.79#ibcon#read 4, iclass 16, count 0 2006.203.07:36:34.79#ibcon#about to read 5, iclass 16, count 0 2006.203.07:36:34.79#ibcon#read 5, iclass 16, count 0 2006.203.07:36:34.79#ibcon#about to read 6, iclass 16, count 0 2006.203.07:36:34.79#ibcon#read 6, iclass 16, count 0 2006.203.07:36:34.79#ibcon#end of sib2, iclass 16, count 0 2006.203.07:36:34.79#ibcon#*mode == 0, iclass 16, count 0 2006.203.07:36:34.79#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.203.07:36:34.79#ibcon#[27=BW32\r\n] 2006.203.07:36:34.79#ibcon#*before write, iclass 16, count 0 2006.203.07:36:34.79#ibcon#enter sib2, iclass 16, count 0 2006.203.07:36:34.79#ibcon#flushed, iclass 16, count 0 2006.203.07:36:34.79#ibcon#about to write, iclass 16, count 0 2006.203.07:36:34.79#ibcon#wrote, iclass 16, count 0 2006.203.07:36:34.79#ibcon#about to read 3, iclass 16, count 0 2006.203.07:36:34.82#ibcon#read 3, iclass 16, count 0 2006.203.07:36:34.82#ibcon#about to read 4, iclass 16, count 0 2006.203.07:36:34.82#ibcon#read 4, iclass 16, count 0 2006.203.07:36:34.82#ibcon#about to read 5, iclass 16, count 0 2006.203.07:36:34.82#ibcon#read 5, iclass 16, count 0 2006.203.07:36:34.82#ibcon#about to read 6, iclass 16, count 0 2006.203.07:36:34.82#ibcon#read 6, iclass 16, count 0 2006.203.07:36:34.82#ibcon#end of sib2, iclass 16, count 0 2006.203.07:36:34.82#ibcon#*after write, iclass 16, count 0 2006.203.07:36:34.82#ibcon#*before return 0, iclass 16, count 0 2006.203.07:36:34.82#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.203.07:36:34.82#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.203.07:36:34.82#ibcon#about to clear, iclass 16 cls_cnt 0 2006.203.07:36:34.82#ibcon#cleared, iclass 16 cls_cnt 0 2006.203.07:36:34.82$4f8m12a/ifd4f 2006.203.07:36:34.82$ifd4f/lo= 2006.203.07:36:34.82$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.203.07:36:34.82$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.203.07:36:34.82$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.203.07:36:34.82$ifd4f/patch= 2006.203.07:36:34.82$ifd4f/patch=lo1,a1,a2,a3,a4 2006.203.07:36:34.82$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.203.07:36:34.83$ifd4f/patch=lo3,a5,a6,a7,a8 2006.203.07:36:34.83$4f8m12a/"form=m,16.000,1:2 2006.203.07:36:34.83$4f8m12a/"tpicd 2006.203.07:36:34.83$4f8m12a/echo=off 2006.203.07:36:34.83$4f8m12a/xlog=off 2006.203.07:36:34.83:!2006.203.07:37:00 2006.203.07:36:46.14#trakl#Source acquired 2006.203.07:36:48.14#flagr#flagr/antenna,acquired 2006.203.07:37:00.01:preob 2006.203.07:37:01.14/onsource/TRACKING 2006.203.07:37:01.14:!2006.203.07:37:10 2006.203.07:37:10.00:data_valid=on 2006.203.07:37:10.00:midob 2006.203.07:37:10.14/onsource/TRACKING 2006.203.07:37:10.14/wx/24.01,1001.0,97 2006.203.07:37:10.25/cable/+6.4609E-03 2006.203.07:37:11.34/va/01,08,usb,yes,43,45 2006.203.07:37:11.34/va/02,07,usb,yes,43,45 2006.203.07:37:11.34/va/03,08,usb,yes,33,33 2006.203.07:37:11.34/va/04,07,usb,yes,43,47 2006.203.07:37:11.34/va/05,07,usb,yes,47,50 2006.203.07:37:11.34/va/06,06,usb,yes,46,45 2006.203.07:37:11.34/va/07,07,usb,yes,41,41 2006.203.07:37:11.34/va/08,06,usb,yes,49,48 2006.203.07:37:11.57/valo/01,532.99,yes,locked 2006.203.07:37:11.57/valo/02,572.99,yes,locked 2006.203.07:37:11.57/valo/03,672.99,yes,locked 2006.203.07:37:11.57/valo/04,832.99,yes,locked 2006.203.07:37:11.57/valo/05,652.99,yes,locked 2006.203.07:37:11.57/valo/06,772.99,yes,locked 2006.203.07:37:11.57/valo/07,832.99,yes,locked 2006.203.07:37:11.57/valo/08,852.99,yes,locked 2006.203.07:37:12.66/vb/01,04,usb,yes,38,35 2006.203.07:37:12.66/vb/02,04,usb,yes,40,41 2006.203.07:37:12.66/vb/03,04,usb,yes,35,40 2006.203.07:37:12.66/vb/04,04,usb,yes,36,37 2006.203.07:37:12.66/vb/05,03,usb,yes,43,48 2006.203.07:37:12.66/vb/06,04,usb,yes,35,39 2006.203.07:37:12.66/vb/07,04,usb,yes,38,38 2006.203.07:37:12.66/vb/08,04,usb,yes,35,39 2006.203.07:37:12.90/vblo/01,632.99,yes,locked 2006.203.07:37:12.90/vblo/02,640.99,yes,locked 2006.203.07:37:12.90/vblo/03,656.99,yes,locked 2006.203.07:37:12.90/vblo/04,712.99,yes,locked 2006.203.07:37:12.90/vblo/05,744.99,yes,locked 2006.203.07:37:12.90/vblo/06,752.99,yes,locked 2006.203.07:37:12.90/vblo/07,734.99,yes,locked 2006.203.07:37:12.90/vblo/08,744.99,yes,locked 2006.203.07:37:13.05/vabw/8 2006.203.07:37:13.20/vbbw/8 2006.203.07:37:13.32/xfe/off,on,16.5 2006.203.07:37:13.70/ifatt/23,28,28,28 2006.203.07:37:14.07/fmout-gps/S +4.55E-07 2006.203.07:37:14.15:!2006.203.07:38:10 2006.203.07:38:10.01:data_valid=off 2006.203.07:38:10.02:postob 2006.203.07:38:10.13/cable/+6.4591E-03 2006.203.07:38:10.14/wx/23.99,1001.0,97 2006.203.07:38:11.07/fmout-gps/S +4.55E-07 2006.203.07:38:11.08:scan_name=203-0739,k06203,60 2006.203.07:38:11.08:source=0804+499,080839.67,495036.5,2000.0,ccw 2006.203.07:38:11.15#flagr#flagr/antenna,new-source 2006.203.07:38:12.13:checkk5 2006.203.07:38:12.54/chk_autoobs//k5ts1/ autoobs is running! 2006.203.07:38:12.93/chk_autoobs//k5ts2/ autoobs is running! 2006.203.07:38:13.41/chk_autoobs//k5ts3/ autoobs is running! 2006.203.07:38:13.82/chk_autoobs//k5ts4/ autoobs is running! 2006.203.07:38:14.27/chk_obsdata//k5ts1/T2030737??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.07:38:14.65/chk_obsdata//k5ts2/T2030737??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.07:38:15.05/chk_obsdata//k5ts3/T2030737??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.07:38:15.44/chk_obsdata//k5ts4/T2030737??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.07:38:16.22/k5log//k5ts1_log_newline 2006.203.07:38:17.24/k5log//k5ts2_log_newline 2006.203.07:38:18.16/k5log//k5ts3_log_newline 2006.203.07:38:19.15/k5log//k5ts4_log_newline 2006.203.07:38:19.21/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.203.07:38:19.21:4f8m12a=1 2006.203.07:38:19.21$4f8m12a/echo=on 2006.203.07:38:19.21$4f8m12a/pcalon 2006.203.07:38:19.21$pcalon/"no phase cal control is implemented here 2006.203.07:38:19.21$4f8m12a/"tpicd=stop 2006.203.07:38:19.21$4f8m12a/vc4f8 2006.203.07:38:19.21$vc4f8/valo=1,532.99 2006.203.07:38:19.21#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.203.07:38:19.21#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.203.07:38:19.21#ibcon#ireg 17 cls_cnt 0 2006.203.07:38:19.21#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.203.07:38:19.21#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.203.07:38:19.21#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.203.07:38:19.21#ibcon#enter wrdev, iclass 23, count 0 2006.203.07:38:19.21#ibcon#first serial, iclass 23, count 0 2006.203.07:38:19.21#ibcon#enter sib2, iclass 23, count 0 2006.203.07:38:19.21#ibcon#flushed, iclass 23, count 0 2006.203.07:38:19.21#ibcon#about to write, iclass 23, count 0 2006.203.07:38:19.21#ibcon#wrote, iclass 23, count 0 2006.203.07:38:19.21#ibcon#about to read 3, iclass 23, count 0 2006.203.07:38:19.23#ibcon#read 3, iclass 23, count 0 2006.203.07:38:19.23#ibcon#about to read 4, iclass 23, count 0 2006.203.07:38:19.23#ibcon#read 4, iclass 23, count 0 2006.203.07:38:19.23#ibcon#about to read 5, iclass 23, count 0 2006.203.07:38:19.23#ibcon#read 5, iclass 23, count 0 2006.203.07:38:19.23#ibcon#about to read 6, iclass 23, count 0 2006.203.07:38:19.23#ibcon#read 6, iclass 23, count 0 2006.203.07:38:19.23#ibcon#end of sib2, iclass 23, count 0 2006.203.07:38:19.23#ibcon#*mode == 0, iclass 23, count 0 2006.203.07:38:19.23#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.203.07:38:19.23#ibcon#[26=FRQ=01,532.99\r\n] 2006.203.07:38:19.23#ibcon#*before write, iclass 23, count 0 2006.203.07:38:19.23#ibcon#enter sib2, iclass 23, count 0 2006.203.07:38:19.23#ibcon#flushed, iclass 23, count 0 2006.203.07:38:19.23#ibcon#about to write, iclass 23, count 0 2006.203.07:38:19.23#ibcon#wrote, iclass 23, count 0 2006.203.07:38:19.23#ibcon#about to read 3, iclass 23, count 0 2006.203.07:38:19.28#ibcon#read 3, iclass 23, count 0 2006.203.07:38:19.28#ibcon#about to read 4, iclass 23, count 0 2006.203.07:38:19.28#ibcon#read 4, iclass 23, count 0 2006.203.07:38:19.28#ibcon#about to read 5, iclass 23, count 0 2006.203.07:38:19.28#ibcon#read 5, iclass 23, count 0 2006.203.07:38:19.28#ibcon#about to read 6, iclass 23, count 0 2006.203.07:38:19.28#ibcon#read 6, iclass 23, count 0 2006.203.07:38:19.28#ibcon#end of sib2, iclass 23, count 0 2006.203.07:38:19.28#ibcon#*after write, iclass 23, count 0 2006.203.07:38:19.28#ibcon#*before return 0, iclass 23, count 0 2006.203.07:38:19.28#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.203.07:38:19.28#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.203.07:38:19.28#ibcon#about to clear, iclass 23 cls_cnt 0 2006.203.07:38:19.28#ibcon#cleared, iclass 23 cls_cnt 0 2006.203.07:38:19.28$vc4f8/va=1,8 2006.203.07:38:19.28#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.203.07:38:19.28#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.203.07:38:19.28#ibcon#ireg 11 cls_cnt 2 2006.203.07:38:19.28#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.203.07:38:19.28#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.203.07:38:19.28#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.203.07:38:19.28#ibcon#enter wrdev, iclass 25, count 2 2006.203.07:38:19.28#ibcon#first serial, iclass 25, count 2 2006.203.07:38:19.28#ibcon#enter sib2, iclass 25, count 2 2006.203.07:38:19.28#ibcon#flushed, iclass 25, count 2 2006.203.07:38:19.28#ibcon#about to write, iclass 25, count 2 2006.203.07:38:19.28#ibcon#wrote, iclass 25, count 2 2006.203.07:38:19.28#ibcon#about to read 3, iclass 25, count 2 2006.203.07:38:19.30#ibcon#read 3, iclass 25, count 2 2006.203.07:38:19.30#ibcon#about to read 4, iclass 25, count 2 2006.203.07:38:19.30#ibcon#read 4, iclass 25, count 2 2006.203.07:38:19.30#ibcon#about to read 5, iclass 25, count 2 2006.203.07:38:19.30#ibcon#read 5, iclass 25, count 2 2006.203.07:38:19.30#ibcon#about to read 6, iclass 25, count 2 2006.203.07:38:19.30#ibcon#read 6, iclass 25, count 2 2006.203.07:38:19.30#ibcon#end of sib2, iclass 25, count 2 2006.203.07:38:19.30#ibcon#*mode == 0, iclass 25, count 2 2006.203.07:38:19.30#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.203.07:38:19.30#ibcon#[25=AT01-08\r\n] 2006.203.07:38:19.30#ibcon#*before write, iclass 25, count 2 2006.203.07:38:19.30#ibcon#enter sib2, iclass 25, count 2 2006.203.07:38:19.30#ibcon#flushed, iclass 25, count 2 2006.203.07:38:19.30#ibcon#about to write, iclass 25, count 2 2006.203.07:38:19.30#ibcon#wrote, iclass 25, count 2 2006.203.07:38:19.30#ibcon#about to read 3, iclass 25, count 2 2006.203.07:38:19.33#ibcon#read 3, iclass 25, count 2 2006.203.07:38:19.33#ibcon#about to read 4, iclass 25, count 2 2006.203.07:38:19.33#ibcon#read 4, iclass 25, count 2 2006.203.07:38:19.33#ibcon#about to read 5, iclass 25, count 2 2006.203.07:38:19.33#ibcon#read 5, iclass 25, count 2 2006.203.07:38:19.33#ibcon#about to read 6, iclass 25, count 2 2006.203.07:38:19.33#ibcon#read 6, iclass 25, count 2 2006.203.07:38:19.33#ibcon#end of sib2, iclass 25, count 2 2006.203.07:38:19.33#ibcon#*after write, iclass 25, count 2 2006.203.07:38:19.33#ibcon#*before return 0, iclass 25, count 2 2006.203.07:38:19.33#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.203.07:38:19.33#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.203.07:38:19.33#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.203.07:38:19.33#ibcon#ireg 7 cls_cnt 0 2006.203.07:38:19.33#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.203.07:38:19.45#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.203.07:38:19.45#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.203.07:38:19.45#ibcon#enter wrdev, iclass 25, count 0 2006.203.07:38:19.45#ibcon#first serial, iclass 25, count 0 2006.203.07:38:19.45#ibcon#enter sib2, iclass 25, count 0 2006.203.07:38:19.45#ibcon#flushed, iclass 25, count 0 2006.203.07:38:19.45#ibcon#about to write, iclass 25, count 0 2006.203.07:38:19.45#ibcon#wrote, iclass 25, count 0 2006.203.07:38:19.45#ibcon#about to read 3, iclass 25, count 0 2006.203.07:38:19.47#ibcon#read 3, iclass 25, count 0 2006.203.07:38:19.47#ibcon#about to read 4, iclass 25, count 0 2006.203.07:38:19.47#ibcon#read 4, iclass 25, count 0 2006.203.07:38:19.47#ibcon#about to read 5, iclass 25, count 0 2006.203.07:38:19.47#ibcon#read 5, iclass 25, count 0 2006.203.07:38:19.47#ibcon#about to read 6, iclass 25, count 0 2006.203.07:38:19.47#ibcon#read 6, iclass 25, count 0 2006.203.07:38:19.47#ibcon#end of sib2, iclass 25, count 0 2006.203.07:38:19.47#ibcon#*mode == 0, iclass 25, count 0 2006.203.07:38:19.47#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.203.07:38:19.47#ibcon#[25=USB\r\n] 2006.203.07:38:19.47#ibcon#*before write, iclass 25, count 0 2006.203.07:38:19.47#ibcon#enter sib2, iclass 25, count 0 2006.203.07:38:19.47#ibcon#flushed, iclass 25, count 0 2006.203.07:38:19.47#ibcon#about to write, iclass 25, count 0 2006.203.07:38:19.47#ibcon#wrote, iclass 25, count 0 2006.203.07:38:19.47#ibcon#about to read 3, iclass 25, count 0 2006.203.07:38:19.50#ibcon#read 3, iclass 25, count 0 2006.203.07:38:19.50#ibcon#about to read 4, iclass 25, count 0 2006.203.07:38:19.50#ibcon#read 4, iclass 25, count 0 2006.203.07:38:19.50#ibcon#about to read 5, iclass 25, count 0 2006.203.07:38:19.50#ibcon#read 5, iclass 25, count 0 2006.203.07:38:19.50#ibcon#about to read 6, iclass 25, count 0 2006.203.07:38:19.50#ibcon#read 6, iclass 25, count 0 2006.203.07:38:19.50#ibcon#end of sib2, iclass 25, count 0 2006.203.07:38:19.50#ibcon#*after write, iclass 25, count 0 2006.203.07:38:19.50#ibcon#*before return 0, iclass 25, count 0 2006.203.07:38:19.50#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.203.07:38:19.50#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.203.07:38:19.50#ibcon#about to clear, iclass 25 cls_cnt 0 2006.203.07:38:19.50#ibcon#cleared, iclass 25 cls_cnt 0 2006.203.07:38:19.50$vc4f8/valo=2,572.99 2006.203.07:38:19.50#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.203.07:38:19.50#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.203.07:38:19.50#ibcon#ireg 17 cls_cnt 0 2006.203.07:38:19.50#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:38:19.50#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:38:19.50#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:38:19.50#ibcon#enter wrdev, iclass 27, count 0 2006.203.07:38:19.50#ibcon#first serial, iclass 27, count 0 2006.203.07:38:19.50#ibcon#enter sib2, iclass 27, count 0 2006.203.07:38:19.50#ibcon#flushed, iclass 27, count 0 2006.203.07:38:19.50#ibcon#about to write, iclass 27, count 0 2006.203.07:38:19.50#ibcon#wrote, iclass 27, count 0 2006.203.07:38:19.50#ibcon#about to read 3, iclass 27, count 0 2006.203.07:38:19.53#ibcon#read 3, iclass 27, count 0 2006.203.07:38:19.53#ibcon#about to read 4, iclass 27, count 0 2006.203.07:38:19.53#ibcon#read 4, iclass 27, count 0 2006.203.07:38:19.53#ibcon#about to read 5, iclass 27, count 0 2006.203.07:38:19.53#ibcon#read 5, iclass 27, count 0 2006.203.07:38:19.53#ibcon#about to read 6, iclass 27, count 0 2006.203.07:38:19.53#ibcon#read 6, iclass 27, count 0 2006.203.07:38:19.53#ibcon#end of sib2, iclass 27, count 0 2006.203.07:38:19.53#ibcon#*mode == 0, iclass 27, count 0 2006.203.07:38:19.53#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.203.07:38:19.53#ibcon#[26=FRQ=02,572.99\r\n] 2006.203.07:38:19.53#ibcon#*before write, iclass 27, count 0 2006.203.07:38:19.53#ibcon#enter sib2, iclass 27, count 0 2006.203.07:38:19.53#ibcon#flushed, iclass 27, count 0 2006.203.07:38:19.53#ibcon#about to write, iclass 27, count 0 2006.203.07:38:19.53#ibcon#wrote, iclass 27, count 0 2006.203.07:38:19.53#ibcon#about to read 3, iclass 27, count 0 2006.203.07:38:19.57#ibcon#read 3, iclass 27, count 0 2006.203.07:38:19.57#ibcon#about to read 4, iclass 27, count 0 2006.203.07:38:19.57#ibcon#read 4, iclass 27, count 0 2006.203.07:38:19.57#ibcon#about to read 5, iclass 27, count 0 2006.203.07:38:19.57#ibcon#read 5, iclass 27, count 0 2006.203.07:38:19.57#ibcon#about to read 6, iclass 27, count 0 2006.203.07:38:19.57#ibcon#read 6, iclass 27, count 0 2006.203.07:38:19.57#ibcon#end of sib2, iclass 27, count 0 2006.203.07:38:19.57#ibcon#*after write, iclass 27, count 0 2006.203.07:38:19.57#ibcon#*before return 0, iclass 27, count 0 2006.203.07:38:19.57#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:38:19.57#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:38:19.57#ibcon#about to clear, iclass 27 cls_cnt 0 2006.203.07:38:19.57#ibcon#cleared, iclass 27 cls_cnt 0 2006.203.07:38:19.57$vc4f8/va=2,7 2006.203.07:38:19.57#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.203.07:38:19.57#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.203.07:38:19.57#ibcon#ireg 11 cls_cnt 2 2006.203.07:38:19.57#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.203.07:38:19.62#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.203.07:38:19.62#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.203.07:38:19.62#ibcon#enter wrdev, iclass 29, count 2 2006.203.07:38:19.62#ibcon#first serial, iclass 29, count 2 2006.203.07:38:19.62#ibcon#enter sib2, iclass 29, count 2 2006.203.07:38:19.62#ibcon#flushed, iclass 29, count 2 2006.203.07:38:19.62#ibcon#about to write, iclass 29, count 2 2006.203.07:38:19.62#ibcon#wrote, iclass 29, count 2 2006.203.07:38:19.62#ibcon#about to read 3, iclass 29, count 2 2006.203.07:38:19.64#ibcon#read 3, iclass 29, count 2 2006.203.07:38:19.64#ibcon#about to read 4, iclass 29, count 2 2006.203.07:38:19.64#ibcon#read 4, iclass 29, count 2 2006.203.07:38:19.64#ibcon#about to read 5, iclass 29, count 2 2006.203.07:38:19.64#ibcon#read 5, iclass 29, count 2 2006.203.07:38:19.64#ibcon#about to read 6, iclass 29, count 2 2006.203.07:38:19.64#ibcon#read 6, iclass 29, count 2 2006.203.07:38:19.64#ibcon#end of sib2, iclass 29, count 2 2006.203.07:38:19.64#ibcon#*mode == 0, iclass 29, count 2 2006.203.07:38:19.64#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.203.07:38:19.64#ibcon#[25=AT02-07\r\n] 2006.203.07:38:19.64#ibcon#*before write, iclass 29, count 2 2006.203.07:38:19.64#ibcon#enter sib2, iclass 29, count 2 2006.203.07:38:19.64#ibcon#flushed, iclass 29, count 2 2006.203.07:38:19.64#ibcon#about to write, iclass 29, count 2 2006.203.07:38:19.64#ibcon#wrote, iclass 29, count 2 2006.203.07:38:19.64#ibcon#about to read 3, iclass 29, count 2 2006.203.07:38:19.67#ibcon#read 3, iclass 29, count 2 2006.203.07:38:19.67#ibcon#about to read 4, iclass 29, count 2 2006.203.07:38:19.67#ibcon#read 4, iclass 29, count 2 2006.203.07:38:19.67#ibcon#about to read 5, iclass 29, count 2 2006.203.07:38:19.67#ibcon#read 5, iclass 29, count 2 2006.203.07:38:19.67#ibcon#about to read 6, iclass 29, count 2 2006.203.07:38:19.67#ibcon#read 6, iclass 29, count 2 2006.203.07:38:19.67#ibcon#end of sib2, iclass 29, count 2 2006.203.07:38:19.67#ibcon#*after write, iclass 29, count 2 2006.203.07:38:19.67#ibcon#*before return 0, iclass 29, count 2 2006.203.07:38:19.67#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.203.07:38:19.67#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.203.07:38:19.67#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.203.07:38:19.67#ibcon#ireg 7 cls_cnt 0 2006.203.07:38:19.67#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.203.07:38:19.79#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.203.07:38:19.79#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.203.07:38:19.79#ibcon#enter wrdev, iclass 29, count 0 2006.203.07:38:19.79#ibcon#first serial, iclass 29, count 0 2006.203.07:38:19.79#ibcon#enter sib2, iclass 29, count 0 2006.203.07:38:19.79#ibcon#flushed, iclass 29, count 0 2006.203.07:38:19.79#ibcon#about to write, iclass 29, count 0 2006.203.07:38:19.79#ibcon#wrote, iclass 29, count 0 2006.203.07:38:19.79#ibcon#about to read 3, iclass 29, count 0 2006.203.07:38:19.81#ibcon#read 3, iclass 29, count 0 2006.203.07:38:19.81#ibcon#about to read 4, iclass 29, count 0 2006.203.07:38:19.81#ibcon#read 4, iclass 29, count 0 2006.203.07:38:19.81#ibcon#about to read 5, iclass 29, count 0 2006.203.07:38:19.81#ibcon#read 5, iclass 29, count 0 2006.203.07:38:19.81#ibcon#about to read 6, iclass 29, count 0 2006.203.07:38:19.81#ibcon#read 6, iclass 29, count 0 2006.203.07:38:19.81#ibcon#end of sib2, iclass 29, count 0 2006.203.07:38:19.81#ibcon#*mode == 0, iclass 29, count 0 2006.203.07:38:19.81#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.203.07:38:19.81#ibcon#[25=USB\r\n] 2006.203.07:38:19.81#ibcon#*before write, iclass 29, count 0 2006.203.07:38:19.81#ibcon#enter sib2, iclass 29, count 0 2006.203.07:38:19.81#ibcon#flushed, iclass 29, count 0 2006.203.07:38:19.81#ibcon#about to write, iclass 29, count 0 2006.203.07:38:19.81#ibcon#wrote, iclass 29, count 0 2006.203.07:38:19.81#ibcon#about to read 3, iclass 29, count 0 2006.203.07:38:19.84#ibcon#read 3, iclass 29, count 0 2006.203.07:38:19.84#ibcon#about to read 4, iclass 29, count 0 2006.203.07:38:19.84#ibcon#read 4, iclass 29, count 0 2006.203.07:38:19.84#ibcon#about to read 5, iclass 29, count 0 2006.203.07:38:19.84#ibcon#read 5, iclass 29, count 0 2006.203.07:38:19.84#ibcon#about to read 6, iclass 29, count 0 2006.203.07:38:19.84#ibcon#read 6, iclass 29, count 0 2006.203.07:38:19.84#ibcon#end of sib2, iclass 29, count 0 2006.203.07:38:19.84#ibcon#*after write, iclass 29, count 0 2006.203.07:38:19.84#ibcon#*before return 0, iclass 29, count 0 2006.203.07:38:19.84#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.203.07:38:19.84#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.203.07:38:19.84#ibcon#about to clear, iclass 29 cls_cnt 0 2006.203.07:38:19.84#ibcon#cleared, iclass 29 cls_cnt 0 2006.203.07:38:19.84$vc4f8/valo=3,672.99 2006.203.07:38:19.84#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.203.07:38:19.84#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.203.07:38:19.84#ibcon#ireg 17 cls_cnt 0 2006.203.07:38:19.84#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.203.07:38:19.84#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.203.07:38:19.84#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.203.07:38:19.84#ibcon#enter wrdev, iclass 31, count 0 2006.203.07:38:19.84#ibcon#first serial, iclass 31, count 0 2006.203.07:38:19.84#ibcon#enter sib2, iclass 31, count 0 2006.203.07:38:19.84#ibcon#flushed, iclass 31, count 0 2006.203.07:38:19.84#ibcon#about to write, iclass 31, count 0 2006.203.07:38:19.84#ibcon#wrote, iclass 31, count 0 2006.203.07:38:19.84#ibcon#about to read 3, iclass 31, count 0 2006.203.07:38:19.87#ibcon#read 3, iclass 31, count 0 2006.203.07:38:19.87#ibcon#about to read 4, iclass 31, count 0 2006.203.07:38:19.87#ibcon#read 4, iclass 31, count 0 2006.203.07:38:19.87#ibcon#about to read 5, iclass 31, count 0 2006.203.07:38:19.87#ibcon#read 5, iclass 31, count 0 2006.203.07:38:19.87#ibcon#about to read 6, iclass 31, count 0 2006.203.07:38:19.87#ibcon#read 6, iclass 31, count 0 2006.203.07:38:19.87#ibcon#end of sib2, iclass 31, count 0 2006.203.07:38:19.87#ibcon#*mode == 0, iclass 31, count 0 2006.203.07:38:19.87#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.203.07:38:19.87#ibcon#[26=FRQ=03,672.99\r\n] 2006.203.07:38:19.87#ibcon#*before write, iclass 31, count 0 2006.203.07:38:19.87#ibcon#enter sib2, iclass 31, count 0 2006.203.07:38:19.87#ibcon#flushed, iclass 31, count 0 2006.203.07:38:19.87#ibcon#about to write, iclass 31, count 0 2006.203.07:38:19.87#ibcon#wrote, iclass 31, count 0 2006.203.07:38:19.87#ibcon#about to read 3, iclass 31, count 0 2006.203.07:38:19.91#ibcon#read 3, iclass 31, count 0 2006.203.07:38:19.91#ibcon#about to read 4, iclass 31, count 0 2006.203.07:38:19.91#ibcon#read 4, iclass 31, count 0 2006.203.07:38:19.91#ibcon#about to read 5, iclass 31, count 0 2006.203.07:38:19.91#ibcon#read 5, iclass 31, count 0 2006.203.07:38:19.91#ibcon#about to read 6, iclass 31, count 0 2006.203.07:38:19.91#ibcon#read 6, iclass 31, count 0 2006.203.07:38:19.91#ibcon#end of sib2, iclass 31, count 0 2006.203.07:38:19.91#ibcon#*after write, iclass 31, count 0 2006.203.07:38:19.91#ibcon#*before return 0, iclass 31, count 0 2006.203.07:38:19.91#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.203.07:38:19.91#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.203.07:38:19.91#ibcon#about to clear, iclass 31 cls_cnt 0 2006.203.07:38:19.91#ibcon#cleared, iclass 31 cls_cnt 0 2006.203.07:38:19.91$vc4f8/va=3,8 2006.203.07:38:19.91#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.203.07:38:19.91#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.203.07:38:19.91#ibcon#ireg 11 cls_cnt 2 2006.203.07:38:19.91#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.203.07:38:19.96#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.203.07:38:19.96#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.203.07:38:19.96#ibcon#enter wrdev, iclass 33, count 2 2006.203.07:38:19.96#ibcon#first serial, iclass 33, count 2 2006.203.07:38:19.96#ibcon#enter sib2, iclass 33, count 2 2006.203.07:38:19.96#ibcon#flushed, iclass 33, count 2 2006.203.07:38:19.96#ibcon#about to write, iclass 33, count 2 2006.203.07:38:19.96#ibcon#wrote, iclass 33, count 2 2006.203.07:38:19.96#ibcon#about to read 3, iclass 33, count 2 2006.203.07:38:19.98#ibcon#read 3, iclass 33, count 2 2006.203.07:38:19.98#ibcon#about to read 4, iclass 33, count 2 2006.203.07:38:19.98#ibcon#read 4, iclass 33, count 2 2006.203.07:38:19.98#ibcon#about to read 5, iclass 33, count 2 2006.203.07:38:19.98#ibcon#read 5, iclass 33, count 2 2006.203.07:38:19.98#ibcon#about to read 6, iclass 33, count 2 2006.203.07:38:19.98#ibcon#read 6, iclass 33, count 2 2006.203.07:38:19.98#ibcon#end of sib2, iclass 33, count 2 2006.203.07:38:19.98#ibcon#*mode == 0, iclass 33, count 2 2006.203.07:38:19.98#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.203.07:38:19.98#ibcon#[25=AT03-08\r\n] 2006.203.07:38:19.98#ibcon#*before write, iclass 33, count 2 2006.203.07:38:19.98#ibcon#enter sib2, iclass 33, count 2 2006.203.07:38:19.98#ibcon#flushed, iclass 33, count 2 2006.203.07:38:19.98#ibcon#about to write, iclass 33, count 2 2006.203.07:38:19.98#ibcon#wrote, iclass 33, count 2 2006.203.07:38:19.98#ibcon#about to read 3, iclass 33, count 2 2006.203.07:38:20.01#ibcon#read 3, iclass 33, count 2 2006.203.07:38:20.01#ibcon#about to read 4, iclass 33, count 2 2006.203.07:38:20.01#ibcon#read 4, iclass 33, count 2 2006.203.07:38:20.01#ibcon#about to read 5, iclass 33, count 2 2006.203.07:38:20.01#ibcon#read 5, iclass 33, count 2 2006.203.07:38:20.01#ibcon#about to read 6, iclass 33, count 2 2006.203.07:38:20.01#ibcon#read 6, iclass 33, count 2 2006.203.07:38:20.01#ibcon#end of sib2, iclass 33, count 2 2006.203.07:38:20.01#ibcon#*after write, iclass 33, count 2 2006.203.07:38:20.01#ibcon#*before return 0, iclass 33, count 2 2006.203.07:38:20.01#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.203.07:38:20.01#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.203.07:38:20.01#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.203.07:38:20.01#ibcon#ireg 7 cls_cnt 0 2006.203.07:38:20.01#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.203.07:38:20.13#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.203.07:38:20.13#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.203.07:38:20.13#ibcon#enter wrdev, iclass 33, count 0 2006.203.07:38:20.13#ibcon#first serial, iclass 33, count 0 2006.203.07:38:20.13#ibcon#enter sib2, iclass 33, count 0 2006.203.07:38:20.13#ibcon#flushed, iclass 33, count 0 2006.203.07:38:20.13#ibcon#about to write, iclass 33, count 0 2006.203.07:38:20.13#ibcon#wrote, iclass 33, count 0 2006.203.07:38:20.13#ibcon#about to read 3, iclass 33, count 0 2006.203.07:38:20.15#ibcon#read 3, iclass 33, count 0 2006.203.07:38:20.15#ibcon#about to read 4, iclass 33, count 0 2006.203.07:38:20.15#ibcon#read 4, iclass 33, count 0 2006.203.07:38:20.15#ibcon#about to read 5, iclass 33, count 0 2006.203.07:38:20.15#ibcon#read 5, iclass 33, count 0 2006.203.07:38:20.15#ibcon#about to read 6, iclass 33, count 0 2006.203.07:38:20.15#ibcon#read 6, iclass 33, count 0 2006.203.07:38:20.15#ibcon#end of sib2, iclass 33, count 0 2006.203.07:38:20.15#ibcon#*mode == 0, iclass 33, count 0 2006.203.07:38:20.15#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.203.07:38:20.15#ibcon#[25=USB\r\n] 2006.203.07:38:20.15#ibcon#*before write, iclass 33, count 0 2006.203.07:38:20.15#ibcon#enter sib2, iclass 33, count 0 2006.203.07:38:20.15#ibcon#flushed, iclass 33, count 0 2006.203.07:38:20.15#ibcon#about to write, iclass 33, count 0 2006.203.07:38:20.15#ibcon#wrote, iclass 33, count 0 2006.203.07:38:20.15#ibcon#about to read 3, iclass 33, count 0 2006.203.07:38:20.18#ibcon#read 3, iclass 33, count 0 2006.203.07:38:20.18#ibcon#about to read 4, iclass 33, count 0 2006.203.07:38:20.18#ibcon#read 4, iclass 33, count 0 2006.203.07:38:20.18#ibcon#about to read 5, iclass 33, count 0 2006.203.07:38:20.18#ibcon#read 5, iclass 33, count 0 2006.203.07:38:20.18#ibcon#about to read 6, iclass 33, count 0 2006.203.07:38:20.18#ibcon#read 6, iclass 33, count 0 2006.203.07:38:20.18#ibcon#end of sib2, iclass 33, count 0 2006.203.07:38:20.18#ibcon#*after write, iclass 33, count 0 2006.203.07:38:20.18#ibcon#*before return 0, iclass 33, count 0 2006.203.07:38:20.18#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.203.07:38:20.18#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.203.07:38:20.18#ibcon#about to clear, iclass 33 cls_cnt 0 2006.203.07:38:20.18#ibcon#cleared, iclass 33 cls_cnt 0 2006.203.07:38:20.18$vc4f8/valo=4,832.99 2006.203.07:38:20.18#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.203.07:38:20.18#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.203.07:38:20.18#ibcon#ireg 17 cls_cnt 0 2006.203.07:38:20.18#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.203.07:38:20.18#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.203.07:38:20.18#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.203.07:38:20.18#ibcon#enter wrdev, iclass 35, count 0 2006.203.07:38:20.18#ibcon#first serial, iclass 35, count 0 2006.203.07:38:20.18#ibcon#enter sib2, iclass 35, count 0 2006.203.07:38:20.18#ibcon#flushed, iclass 35, count 0 2006.203.07:38:20.18#ibcon#about to write, iclass 35, count 0 2006.203.07:38:20.18#ibcon#wrote, iclass 35, count 0 2006.203.07:38:20.18#ibcon#about to read 3, iclass 35, count 0 2006.203.07:38:20.21#ibcon#read 3, iclass 35, count 0 2006.203.07:38:20.21#ibcon#about to read 4, iclass 35, count 0 2006.203.07:38:20.21#ibcon#read 4, iclass 35, count 0 2006.203.07:38:20.21#ibcon#about to read 5, iclass 35, count 0 2006.203.07:38:20.21#ibcon#read 5, iclass 35, count 0 2006.203.07:38:20.21#ibcon#about to read 6, iclass 35, count 0 2006.203.07:38:20.21#ibcon#read 6, iclass 35, count 0 2006.203.07:38:20.21#ibcon#end of sib2, iclass 35, count 0 2006.203.07:38:20.21#ibcon#*mode == 0, iclass 35, count 0 2006.203.07:38:20.21#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.203.07:38:20.21#ibcon#[26=FRQ=04,832.99\r\n] 2006.203.07:38:20.21#ibcon#*before write, iclass 35, count 0 2006.203.07:38:20.21#ibcon#enter sib2, iclass 35, count 0 2006.203.07:38:20.21#ibcon#flushed, iclass 35, count 0 2006.203.07:38:20.21#ibcon#about to write, iclass 35, count 0 2006.203.07:38:20.21#ibcon#wrote, iclass 35, count 0 2006.203.07:38:20.21#ibcon#about to read 3, iclass 35, count 0 2006.203.07:38:20.25#ibcon#read 3, iclass 35, count 0 2006.203.07:38:20.25#ibcon#about to read 4, iclass 35, count 0 2006.203.07:38:20.25#ibcon#read 4, iclass 35, count 0 2006.203.07:38:20.25#ibcon#about to read 5, iclass 35, count 0 2006.203.07:38:20.25#ibcon#read 5, iclass 35, count 0 2006.203.07:38:20.25#ibcon#about to read 6, iclass 35, count 0 2006.203.07:38:20.25#ibcon#read 6, iclass 35, count 0 2006.203.07:38:20.25#ibcon#end of sib2, iclass 35, count 0 2006.203.07:38:20.25#ibcon#*after write, iclass 35, count 0 2006.203.07:38:20.25#ibcon#*before return 0, iclass 35, count 0 2006.203.07:38:20.25#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.203.07:38:20.25#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.203.07:38:20.25#ibcon#about to clear, iclass 35 cls_cnt 0 2006.203.07:38:20.25#ibcon#cleared, iclass 35 cls_cnt 0 2006.203.07:38:20.25$vc4f8/va=4,7 2006.203.07:38:20.25#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.203.07:38:20.25#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.203.07:38:20.25#ibcon#ireg 11 cls_cnt 2 2006.203.07:38:20.25#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.203.07:38:20.30#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.203.07:38:20.30#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.203.07:38:20.30#ibcon#enter wrdev, iclass 37, count 2 2006.203.07:38:20.30#ibcon#first serial, iclass 37, count 2 2006.203.07:38:20.30#ibcon#enter sib2, iclass 37, count 2 2006.203.07:38:20.30#ibcon#flushed, iclass 37, count 2 2006.203.07:38:20.30#ibcon#about to write, iclass 37, count 2 2006.203.07:38:20.30#ibcon#wrote, iclass 37, count 2 2006.203.07:38:20.30#ibcon#about to read 3, iclass 37, count 2 2006.203.07:38:20.32#ibcon#read 3, iclass 37, count 2 2006.203.07:38:20.32#ibcon#about to read 4, iclass 37, count 2 2006.203.07:38:20.32#ibcon#read 4, iclass 37, count 2 2006.203.07:38:20.32#ibcon#about to read 5, iclass 37, count 2 2006.203.07:38:20.32#ibcon#read 5, iclass 37, count 2 2006.203.07:38:20.32#ibcon#about to read 6, iclass 37, count 2 2006.203.07:38:20.32#ibcon#read 6, iclass 37, count 2 2006.203.07:38:20.32#ibcon#end of sib2, iclass 37, count 2 2006.203.07:38:20.32#ibcon#*mode == 0, iclass 37, count 2 2006.203.07:38:20.32#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.203.07:38:20.32#ibcon#[25=AT04-07\r\n] 2006.203.07:38:20.32#ibcon#*before write, iclass 37, count 2 2006.203.07:38:20.32#ibcon#enter sib2, iclass 37, count 2 2006.203.07:38:20.32#ibcon#flushed, iclass 37, count 2 2006.203.07:38:20.32#ibcon#about to write, iclass 37, count 2 2006.203.07:38:20.32#ibcon#wrote, iclass 37, count 2 2006.203.07:38:20.32#ibcon#about to read 3, iclass 37, count 2 2006.203.07:38:20.35#ibcon#read 3, iclass 37, count 2 2006.203.07:38:20.35#ibcon#about to read 4, iclass 37, count 2 2006.203.07:38:20.35#ibcon#read 4, iclass 37, count 2 2006.203.07:38:20.35#ibcon#about to read 5, iclass 37, count 2 2006.203.07:38:20.35#ibcon#read 5, iclass 37, count 2 2006.203.07:38:20.35#ibcon#about to read 6, iclass 37, count 2 2006.203.07:38:20.35#ibcon#read 6, iclass 37, count 2 2006.203.07:38:20.35#ibcon#end of sib2, iclass 37, count 2 2006.203.07:38:20.35#ibcon#*after write, iclass 37, count 2 2006.203.07:38:20.35#ibcon#*before return 0, iclass 37, count 2 2006.203.07:38:20.35#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.203.07:38:20.35#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.203.07:38:20.35#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.203.07:38:20.35#ibcon#ireg 7 cls_cnt 0 2006.203.07:38:20.35#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.203.07:38:20.47#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.203.07:38:20.47#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.203.07:38:20.47#ibcon#enter wrdev, iclass 37, count 0 2006.203.07:38:20.47#ibcon#first serial, iclass 37, count 0 2006.203.07:38:20.47#ibcon#enter sib2, iclass 37, count 0 2006.203.07:38:20.47#ibcon#flushed, iclass 37, count 0 2006.203.07:38:20.47#ibcon#about to write, iclass 37, count 0 2006.203.07:38:20.47#ibcon#wrote, iclass 37, count 0 2006.203.07:38:20.47#ibcon#about to read 3, iclass 37, count 0 2006.203.07:38:20.49#ibcon#read 3, iclass 37, count 0 2006.203.07:38:20.49#ibcon#about to read 4, iclass 37, count 0 2006.203.07:38:20.49#ibcon#read 4, iclass 37, count 0 2006.203.07:38:20.49#ibcon#about to read 5, iclass 37, count 0 2006.203.07:38:20.49#ibcon#read 5, iclass 37, count 0 2006.203.07:38:20.49#ibcon#about to read 6, iclass 37, count 0 2006.203.07:38:20.49#ibcon#read 6, iclass 37, count 0 2006.203.07:38:20.49#ibcon#end of sib2, iclass 37, count 0 2006.203.07:38:20.49#ibcon#*mode == 0, iclass 37, count 0 2006.203.07:38:20.49#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.203.07:38:20.49#ibcon#[25=USB\r\n] 2006.203.07:38:20.49#ibcon#*before write, iclass 37, count 0 2006.203.07:38:20.49#ibcon#enter sib2, iclass 37, count 0 2006.203.07:38:20.49#ibcon#flushed, iclass 37, count 0 2006.203.07:38:20.49#ibcon#about to write, iclass 37, count 0 2006.203.07:38:20.49#ibcon#wrote, iclass 37, count 0 2006.203.07:38:20.49#ibcon#about to read 3, iclass 37, count 0 2006.203.07:38:20.52#ibcon#read 3, iclass 37, count 0 2006.203.07:38:20.52#ibcon#about to read 4, iclass 37, count 0 2006.203.07:38:20.52#ibcon#read 4, iclass 37, count 0 2006.203.07:38:20.52#ibcon#about to read 5, iclass 37, count 0 2006.203.07:38:20.52#ibcon#read 5, iclass 37, count 0 2006.203.07:38:20.52#ibcon#about to read 6, iclass 37, count 0 2006.203.07:38:20.52#ibcon#read 6, iclass 37, count 0 2006.203.07:38:20.52#ibcon#end of sib2, iclass 37, count 0 2006.203.07:38:20.52#ibcon#*after write, iclass 37, count 0 2006.203.07:38:20.52#ibcon#*before return 0, iclass 37, count 0 2006.203.07:38:20.52#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.203.07:38:20.52#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.203.07:38:20.52#ibcon#about to clear, iclass 37 cls_cnt 0 2006.203.07:38:20.52#ibcon#cleared, iclass 37 cls_cnt 0 2006.203.07:38:20.52$vc4f8/valo=5,652.99 2006.203.07:38:20.52#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.203.07:38:20.52#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.203.07:38:20.52#ibcon#ireg 17 cls_cnt 0 2006.203.07:38:20.52#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.203.07:38:20.52#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.203.07:38:20.52#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.203.07:38:20.52#ibcon#enter wrdev, iclass 39, count 0 2006.203.07:38:20.52#ibcon#first serial, iclass 39, count 0 2006.203.07:38:20.52#ibcon#enter sib2, iclass 39, count 0 2006.203.07:38:20.52#ibcon#flushed, iclass 39, count 0 2006.203.07:38:20.52#ibcon#about to write, iclass 39, count 0 2006.203.07:38:20.52#ibcon#wrote, iclass 39, count 0 2006.203.07:38:20.52#ibcon#about to read 3, iclass 39, count 0 2006.203.07:38:20.55#ibcon#read 3, iclass 39, count 0 2006.203.07:38:20.55#ibcon#about to read 4, iclass 39, count 0 2006.203.07:38:20.55#ibcon#read 4, iclass 39, count 0 2006.203.07:38:20.55#ibcon#about to read 5, iclass 39, count 0 2006.203.07:38:20.55#ibcon#read 5, iclass 39, count 0 2006.203.07:38:20.55#ibcon#about to read 6, iclass 39, count 0 2006.203.07:38:20.55#ibcon#read 6, iclass 39, count 0 2006.203.07:38:20.55#ibcon#end of sib2, iclass 39, count 0 2006.203.07:38:20.55#ibcon#*mode == 0, iclass 39, count 0 2006.203.07:38:20.55#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.203.07:38:20.55#ibcon#[26=FRQ=05,652.99\r\n] 2006.203.07:38:20.55#ibcon#*before write, iclass 39, count 0 2006.203.07:38:20.55#ibcon#enter sib2, iclass 39, count 0 2006.203.07:38:20.55#ibcon#flushed, iclass 39, count 0 2006.203.07:38:20.55#ibcon#about to write, iclass 39, count 0 2006.203.07:38:20.55#ibcon#wrote, iclass 39, count 0 2006.203.07:38:20.55#ibcon#about to read 3, iclass 39, count 0 2006.203.07:38:20.59#ibcon#read 3, iclass 39, count 0 2006.203.07:38:20.59#ibcon#about to read 4, iclass 39, count 0 2006.203.07:38:20.59#ibcon#read 4, iclass 39, count 0 2006.203.07:38:20.59#ibcon#about to read 5, iclass 39, count 0 2006.203.07:38:20.59#ibcon#read 5, iclass 39, count 0 2006.203.07:38:20.59#ibcon#about to read 6, iclass 39, count 0 2006.203.07:38:20.59#ibcon#read 6, iclass 39, count 0 2006.203.07:38:20.59#ibcon#end of sib2, iclass 39, count 0 2006.203.07:38:20.59#ibcon#*after write, iclass 39, count 0 2006.203.07:38:20.59#ibcon#*before return 0, iclass 39, count 0 2006.203.07:38:20.59#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.203.07:38:20.59#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.203.07:38:20.59#ibcon#about to clear, iclass 39 cls_cnt 0 2006.203.07:38:20.59#ibcon#cleared, iclass 39 cls_cnt 0 2006.203.07:38:20.59$vc4f8/va=5,7 2006.203.07:38:20.59#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.203.07:38:20.59#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.203.07:38:20.59#ibcon#ireg 11 cls_cnt 2 2006.203.07:38:20.59#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.203.07:38:20.64#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.203.07:38:20.64#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.203.07:38:20.64#ibcon#enter wrdev, iclass 3, count 2 2006.203.07:38:20.64#ibcon#first serial, iclass 3, count 2 2006.203.07:38:20.64#ibcon#enter sib2, iclass 3, count 2 2006.203.07:38:20.64#ibcon#flushed, iclass 3, count 2 2006.203.07:38:20.64#ibcon#about to write, iclass 3, count 2 2006.203.07:38:20.64#ibcon#wrote, iclass 3, count 2 2006.203.07:38:20.64#ibcon#about to read 3, iclass 3, count 2 2006.203.07:38:20.66#ibcon#read 3, iclass 3, count 2 2006.203.07:38:20.66#ibcon#about to read 4, iclass 3, count 2 2006.203.07:38:20.66#ibcon#read 4, iclass 3, count 2 2006.203.07:38:20.66#ibcon#about to read 5, iclass 3, count 2 2006.203.07:38:20.66#ibcon#read 5, iclass 3, count 2 2006.203.07:38:20.66#ibcon#about to read 6, iclass 3, count 2 2006.203.07:38:20.66#ibcon#read 6, iclass 3, count 2 2006.203.07:38:20.66#ibcon#end of sib2, iclass 3, count 2 2006.203.07:38:20.66#ibcon#*mode == 0, iclass 3, count 2 2006.203.07:38:20.66#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.203.07:38:20.66#ibcon#[25=AT05-07\r\n] 2006.203.07:38:20.66#ibcon#*before write, iclass 3, count 2 2006.203.07:38:20.66#ibcon#enter sib2, iclass 3, count 2 2006.203.07:38:20.66#ibcon#flushed, iclass 3, count 2 2006.203.07:38:20.66#ibcon#about to write, iclass 3, count 2 2006.203.07:38:20.66#ibcon#wrote, iclass 3, count 2 2006.203.07:38:20.66#ibcon#about to read 3, iclass 3, count 2 2006.203.07:38:20.69#ibcon#read 3, iclass 3, count 2 2006.203.07:38:20.69#ibcon#about to read 4, iclass 3, count 2 2006.203.07:38:20.69#ibcon#read 4, iclass 3, count 2 2006.203.07:38:20.69#ibcon#about to read 5, iclass 3, count 2 2006.203.07:38:20.69#ibcon#read 5, iclass 3, count 2 2006.203.07:38:20.69#ibcon#about to read 6, iclass 3, count 2 2006.203.07:38:20.69#ibcon#read 6, iclass 3, count 2 2006.203.07:38:20.69#ibcon#end of sib2, iclass 3, count 2 2006.203.07:38:20.69#ibcon#*after write, iclass 3, count 2 2006.203.07:38:20.69#ibcon#*before return 0, iclass 3, count 2 2006.203.07:38:20.69#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.203.07:38:20.69#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.203.07:38:20.69#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.203.07:38:20.69#ibcon#ireg 7 cls_cnt 0 2006.203.07:38:20.69#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.203.07:38:20.81#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.203.07:38:20.81#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.203.07:38:20.81#ibcon#enter wrdev, iclass 3, count 0 2006.203.07:38:20.81#ibcon#first serial, iclass 3, count 0 2006.203.07:38:20.81#ibcon#enter sib2, iclass 3, count 0 2006.203.07:38:20.81#ibcon#flushed, iclass 3, count 0 2006.203.07:38:20.81#ibcon#about to write, iclass 3, count 0 2006.203.07:38:20.81#ibcon#wrote, iclass 3, count 0 2006.203.07:38:20.81#ibcon#about to read 3, iclass 3, count 0 2006.203.07:38:20.83#ibcon#read 3, iclass 3, count 0 2006.203.07:38:20.83#ibcon#about to read 4, iclass 3, count 0 2006.203.07:38:20.83#ibcon#read 4, iclass 3, count 0 2006.203.07:38:20.83#ibcon#about to read 5, iclass 3, count 0 2006.203.07:38:20.83#ibcon#read 5, iclass 3, count 0 2006.203.07:38:20.83#ibcon#about to read 6, iclass 3, count 0 2006.203.07:38:20.83#ibcon#read 6, iclass 3, count 0 2006.203.07:38:20.83#ibcon#end of sib2, iclass 3, count 0 2006.203.07:38:20.83#ibcon#*mode == 0, iclass 3, count 0 2006.203.07:38:20.83#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.203.07:38:20.83#ibcon#[25=USB\r\n] 2006.203.07:38:20.83#ibcon#*before write, iclass 3, count 0 2006.203.07:38:20.83#ibcon#enter sib2, iclass 3, count 0 2006.203.07:38:20.83#ibcon#flushed, iclass 3, count 0 2006.203.07:38:20.83#ibcon#about to write, iclass 3, count 0 2006.203.07:38:20.83#ibcon#wrote, iclass 3, count 0 2006.203.07:38:20.83#ibcon#about to read 3, iclass 3, count 0 2006.203.07:38:20.86#ibcon#read 3, iclass 3, count 0 2006.203.07:38:20.86#ibcon#about to read 4, iclass 3, count 0 2006.203.07:38:20.86#ibcon#read 4, iclass 3, count 0 2006.203.07:38:20.86#ibcon#about to read 5, iclass 3, count 0 2006.203.07:38:20.86#ibcon#read 5, iclass 3, count 0 2006.203.07:38:20.86#ibcon#about to read 6, iclass 3, count 0 2006.203.07:38:20.86#ibcon#read 6, iclass 3, count 0 2006.203.07:38:20.86#ibcon#end of sib2, iclass 3, count 0 2006.203.07:38:20.86#ibcon#*after write, iclass 3, count 0 2006.203.07:38:20.86#ibcon#*before return 0, iclass 3, count 0 2006.203.07:38:20.86#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.203.07:38:20.86#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.203.07:38:20.86#ibcon#about to clear, iclass 3 cls_cnt 0 2006.203.07:38:20.86#ibcon#cleared, iclass 3 cls_cnt 0 2006.203.07:38:20.86$vc4f8/valo=6,772.99 2006.203.07:38:20.86#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.203.07:38:20.86#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.203.07:38:20.86#ibcon#ireg 17 cls_cnt 0 2006.203.07:38:20.86#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.203.07:38:20.86#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.203.07:38:20.86#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.203.07:38:20.86#ibcon#enter wrdev, iclass 5, count 0 2006.203.07:38:20.86#ibcon#first serial, iclass 5, count 0 2006.203.07:38:20.86#ibcon#enter sib2, iclass 5, count 0 2006.203.07:38:20.86#ibcon#flushed, iclass 5, count 0 2006.203.07:38:20.86#ibcon#about to write, iclass 5, count 0 2006.203.07:38:20.86#ibcon#wrote, iclass 5, count 0 2006.203.07:38:20.86#ibcon#about to read 3, iclass 5, count 0 2006.203.07:38:20.88#ibcon#read 3, iclass 5, count 0 2006.203.07:38:20.88#ibcon#about to read 4, iclass 5, count 0 2006.203.07:38:20.88#ibcon#read 4, iclass 5, count 0 2006.203.07:38:20.88#ibcon#about to read 5, iclass 5, count 0 2006.203.07:38:20.88#ibcon#read 5, iclass 5, count 0 2006.203.07:38:20.88#ibcon#about to read 6, iclass 5, count 0 2006.203.07:38:20.88#ibcon#read 6, iclass 5, count 0 2006.203.07:38:20.88#ibcon#end of sib2, iclass 5, count 0 2006.203.07:38:20.88#ibcon#*mode == 0, iclass 5, count 0 2006.203.07:38:20.88#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.203.07:38:20.88#ibcon#[26=FRQ=06,772.99\r\n] 2006.203.07:38:20.88#ibcon#*before write, iclass 5, count 0 2006.203.07:38:20.88#ibcon#enter sib2, iclass 5, count 0 2006.203.07:38:20.88#ibcon#flushed, iclass 5, count 0 2006.203.07:38:20.88#ibcon#about to write, iclass 5, count 0 2006.203.07:38:20.88#ibcon#wrote, iclass 5, count 0 2006.203.07:38:20.88#ibcon#about to read 3, iclass 5, count 0 2006.203.07:38:20.92#ibcon#read 3, iclass 5, count 0 2006.203.07:38:20.92#ibcon#about to read 4, iclass 5, count 0 2006.203.07:38:20.92#ibcon#read 4, iclass 5, count 0 2006.203.07:38:20.92#ibcon#about to read 5, iclass 5, count 0 2006.203.07:38:20.92#ibcon#read 5, iclass 5, count 0 2006.203.07:38:20.92#ibcon#about to read 6, iclass 5, count 0 2006.203.07:38:20.92#ibcon#read 6, iclass 5, count 0 2006.203.07:38:20.92#ibcon#end of sib2, iclass 5, count 0 2006.203.07:38:20.92#ibcon#*after write, iclass 5, count 0 2006.203.07:38:20.92#ibcon#*before return 0, iclass 5, count 0 2006.203.07:38:20.92#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.203.07:38:20.92#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.203.07:38:20.92#ibcon#about to clear, iclass 5 cls_cnt 0 2006.203.07:38:20.92#ibcon#cleared, iclass 5 cls_cnt 0 2006.203.07:38:20.92$vc4f8/va=6,6 2006.203.07:38:20.92#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.203.07:38:20.92#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.203.07:38:20.92#ibcon#ireg 11 cls_cnt 2 2006.203.07:38:20.92#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.203.07:38:20.98#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.203.07:38:20.98#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.203.07:38:20.98#ibcon#enter wrdev, iclass 7, count 2 2006.203.07:38:20.98#ibcon#first serial, iclass 7, count 2 2006.203.07:38:20.98#ibcon#enter sib2, iclass 7, count 2 2006.203.07:38:20.98#ibcon#flushed, iclass 7, count 2 2006.203.07:38:20.98#ibcon#about to write, iclass 7, count 2 2006.203.07:38:20.98#ibcon#wrote, iclass 7, count 2 2006.203.07:38:20.98#ibcon#about to read 3, iclass 7, count 2 2006.203.07:38:21.00#ibcon#read 3, iclass 7, count 2 2006.203.07:38:21.00#ibcon#about to read 4, iclass 7, count 2 2006.203.07:38:21.00#ibcon#read 4, iclass 7, count 2 2006.203.07:38:21.00#ibcon#about to read 5, iclass 7, count 2 2006.203.07:38:21.00#ibcon#read 5, iclass 7, count 2 2006.203.07:38:21.00#ibcon#about to read 6, iclass 7, count 2 2006.203.07:38:21.00#ibcon#read 6, iclass 7, count 2 2006.203.07:38:21.00#ibcon#end of sib2, iclass 7, count 2 2006.203.07:38:21.00#ibcon#*mode == 0, iclass 7, count 2 2006.203.07:38:21.00#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.203.07:38:21.00#ibcon#[25=AT06-06\r\n] 2006.203.07:38:21.00#ibcon#*before write, iclass 7, count 2 2006.203.07:38:21.00#ibcon#enter sib2, iclass 7, count 2 2006.203.07:38:21.00#ibcon#flushed, iclass 7, count 2 2006.203.07:38:21.00#ibcon#about to write, iclass 7, count 2 2006.203.07:38:21.00#ibcon#wrote, iclass 7, count 2 2006.203.07:38:21.00#ibcon#about to read 3, iclass 7, count 2 2006.203.07:38:21.03#ibcon#read 3, iclass 7, count 2 2006.203.07:38:21.03#ibcon#about to read 4, iclass 7, count 2 2006.203.07:38:21.03#ibcon#read 4, iclass 7, count 2 2006.203.07:38:21.03#ibcon#about to read 5, iclass 7, count 2 2006.203.07:38:21.03#ibcon#read 5, iclass 7, count 2 2006.203.07:38:21.03#ibcon#about to read 6, iclass 7, count 2 2006.203.07:38:21.03#ibcon#read 6, iclass 7, count 2 2006.203.07:38:21.03#ibcon#end of sib2, iclass 7, count 2 2006.203.07:38:21.03#ibcon#*after write, iclass 7, count 2 2006.203.07:38:21.03#ibcon#*before return 0, iclass 7, count 2 2006.203.07:38:21.03#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.203.07:38:21.03#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.203.07:38:21.03#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.203.07:38:21.03#ibcon#ireg 7 cls_cnt 0 2006.203.07:38:21.03#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.203.07:38:21.15#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.203.07:38:21.15#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.203.07:38:21.15#ibcon#enter wrdev, iclass 7, count 0 2006.203.07:38:21.15#ibcon#first serial, iclass 7, count 0 2006.203.07:38:21.15#ibcon#enter sib2, iclass 7, count 0 2006.203.07:38:21.15#ibcon#flushed, iclass 7, count 0 2006.203.07:38:21.15#ibcon#about to write, iclass 7, count 0 2006.203.07:38:21.15#ibcon#wrote, iclass 7, count 0 2006.203.07:38:21.15#ibcon#about to read 3, iclass 7, count 0 2006.203.07:38:21.17#ibcon#read 3, iclass 7, count 0 2006.203.07:38:21.17#ibcon#about to read 4, iclass 7, count 0 2006.203.07:38:21.17#ibcon#read 4, iclass 7, count 0 2006.203.07:38:21.17#ibcon#about to read 5, iclass 7, count 0 2006.203.07:38:21.17#ibcon#read 5, iclass 7, count 0 2006.203.07:38:21.17#ibcon#about to read 6, iclass 7, count 0 2006.203.07:38:21.17#ibcon#read 6, iclass 7, count 0 2006.203.07:38:21.17#ibcon#end of sib2, iclass 7, count 0 2006.203.07:38:21.17#ibcon#*mode == 0, iclass 7, count 0 2006.203.07:38:21.17#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.203.07:38:21.17#ibcon#[25=USB\r\n] 2006.203.07:38:21.17#ibcon#*before write, iclass 7, count 0 2006.203.07:38:21.17#ibcon#enter sib2, iclass 7, count 0 2006.203.07:38:21.17#ibcon#flushed, iclass 7, count 0 2006.203.07:38:21.17#ibcon#about to write, iclass 7, count 0 2006.203.07:38:21.17#ibcon#wrote, iclass 7, count 0 2006.203.07:38:21.17#ibcon#about to read 3, iclass 7, count 0 2006.203.07:38:21.20#ibcon#read 3, iclass 7, count 0 2006.203.07:38:21.20#ibcon#about to read 4, iclass 7, count 0 2006.203.07:38:21.20#ibcon#read 4, iclass 7, count 0 2006.203.07:38:21.20#ibcon#about to read 5, iclass 7, count 0 2006.203.07:38:21.20#ibcon#read 5, iclass 7, count 0 2006.203.07:38:21.20#ibcon#about to read 6, iclass 7, count 0 2006.203.07:38:21.20#ibcon#read 6, iclass 7, count 0 2006.203.07:38:21.20#ibcon#end of sib2, iclass 7, count 0 2006.203.07:38:21.20#ibcon#*after write, iclass 7, count 0 2006.203.07:38:21.20#ibcon#*before return 0, iclass 7, count 0 2006.203.07:38:21.20#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.203.07:38:21.20#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.203.07:38:21.20#ibcon#about to clear, iclass 7 cls_cnt 0 2006.203.07:38:21.20#ibcon#cleared, iclass 7 cls_cnt 0 2006.203.07:38:21.20$vc4f8/valo=7,832.99 2006.203.07:38:21.20#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.203.07:38:21.20#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.203.07:38:21.20#ibcon#ireg 17 cls_cnt 0 2006.203.07:38:21.20#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.203.07:38:21.20#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.203.07:38:21.20#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.203.07:38:21.20#ibcon#enter wrdev, iclass 11, count 0 2006.203.07:38:21.20#ibcon#first serial, iclass 11, count 0 2006.203.07:38:21.20#ibcon#enter sib2, iclass 11, count 0 2006.203.07:38:21.20#ibcon#flushed, iclass 11, count 0 2006.203.07:38:21.20#ibcon#about to write, iclass 11, count 0 2006.203.07:38:21.20#ibcon#wrote, iclass 11, count 0 2006.203.07:38:21.20#ibcon#about to read 3, iclass 11, count 0 2006.203.07:38:21.22#ibcon#read 3, iclass 11, count 0 2006.203.07:38:21.22#ibcon#about to read 4, iclass 11, count 0 2006.203.07:38:21.22#ibcon#read 4, iclass 11, count 0 2006.203.07:38:21.22#ibcon#about to read 5, iclass 11, count 0 2006.203.07:38:21.22#ibcon#read 5, iclass 11, count 0 2006.203.07:38:21.22#ibcon#about to read 6, iclass 11, count 0 2006.203.07:38:21.22#ibcon#read 6, iclass 11, count 0 2006.203.07:38:21.22#ibcon#end of sib2, iclass 11, count 0 2006.203.07:38:21.22#ibcon#*mode == 0, iclass 11, count 0 2006.203.07:38:21.22#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.203.07:38:21.22#ibcon#[26=FRQ=07,832.99\r\n] 2006.203.07:38:21.22#ibcon#*before write, iclass 11, count 0 2006.203.07:38:21.22#ibcon#enter sib2, iclass 11, count 0 2006.203.07:38:21.22#ibcon#flushed, iclass 11, count 0 2006.203.07:38:21.22#ibcon#about to write, iclass 11, count 0 2006.203.07:38:21.22#ibcon#wrote, iclass 11, count 0 2006.203.07:38:21.22#ibcon#about to read 3, iclass 11, count 0 2006.203.07:38:21.26#ibcon#read 3, iclass 11, count 0 2006.203.07:38:21.26#ibcon#about to read 4, iclass 11, count 0 2006.203.07:38:21.26#ibcon#read 4, iclass 11, count 0 2006.203.07:38:21.26#ibcon#about to read 5, iclass 11, count 0 2006.203.07:38:21.26#ibcon#read 5, iclass 11, count 0 2006.203.07:38:21.26#ibcon#about to read 6, iclass 11, count 0 2006.203.07:38:21.26#ibcon#read 6, iclass 11, count 0 2006.203.07:38:21.26#ibcon#end of sib2, iclass 11, count 0 2006.203.07:38:21.26#ibcon#*after write, iclass 11, count 0 2006.203.07:38:21.26#ibcon#*before return 0, iclass 11, count 0 2006.203.07:38:21.26#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.203.07:38:21.26#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.203.07:38:21.26#ibcon#about to clear, iclass 11 cls_cnt 0 2006.203.07:38:21.26#ibcon#cleared, iclass 11 cls_cnt 0 2006.203.07:38:21.26$vc4f8/va=7,7 2006.203.07:38:21.26#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.203.07:38:21.26#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.203.07:38:21.26#ibcon#ireg 11 cls_cnt 2 2006.203.07:38:21.26#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.203.07:38:21.32#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.203.07:38:21.32#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.203.07:38:21.32#ibcon#enter wrdev, iclass 13, count 2 2006.203.07:38:21.32#ibcon#first serial, iclass 13, count 2 2006.203.07:38:21.32#ibcon#enter sib2, iclass 13, count 2 2006.203.07:38:21.32#ibcon#flushed, iclass 13, count 2 2006.203.07:38:21.32#ibcon#about to write, iclass 13, count 2 2006.203.07:38:21.32#ibcon#wrote, iclass 13, count 2 2006.203.07:38:21.32#ibcon#about to read 3, iclass 13, count 2 2006.203.07:38:21.34#ibcon#read 3, iclass 13, count 2 2006.203.07:38:21.34#ibcon#about to read 4, iclass 13, count 2 2006.203.07:38:21.34#ibcon#read 4, iclass 13, count 2 2006.203.07:38:21.34#ibcon#about to read 5, iclass 13, count 2 2006.203.07:38:21.34#ibcon#read 5, iclass 13, count 2 2006.203.07:38:21.34#ibcon#about to read 6, iclass 13, count 2 2006.203.07:38:21.34#ibcon#read 6, iclass 13, count 2 2006.203.07:38:21.34#ibcon#end of sib2, iclass 13, count 2 2006.203.07:38:21.34#ibcon#*mode == 0, iclass 13, count 2 2006.203.07:38:21.34#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.203.07:38:21.34#ibcon#[25=AT07-07\r\n] 2006.203.07:38:21.34#ibcon#*before write, iclass 13, count 2 2006.203.07:38:21.34#ibcon#enter sib2, iclass 13, count 2 2006.203.07:38:21.34#ibcon#flushed, iclass 13, count 2 2006.203.07:38:21.34#ibcon#about to write, iclass 13, count 2 2006.203.07:38:21.34#ibcon#wrote, iclass 13, count 2 2006.203.07:38:21.34#ibcon#about to read 3, iclass 13, count 2 2006.203.07:38:21.37#ibcon#read 3, iclass 13, count 2 2006.203.07:38:21.37#ibcon#about to read 4, iclass 13, count 2 2006.203.07:38:21.37#ibcon#read 4, iclass 13, count 2 2006.203.07:38:21.37#ibcon#about to read 5, iclass 13, count 2 2006.203.07:38:21.37#ibcon#read 5, iclass 13, count 2 2006.203.07:38:21.37#ibcon#about to read 6, iclass 13, count 2 2006.203.07:38:21.37#ibcon#read 6, iclass 13, count 2 2006.203.07:38:21.37#ibcon#end of sib2, iclass 13, count 2 2006.203.07:38:21.37#ibcon#*after write, iclass 13, count 2 2006.203.07:38:21.37#ibcon#*before return 0, iclass 13, count 2 2006.203.07:38:21.37#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.203.07:38:21.37#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.203.07:38:21.37#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.203.07:38:21.37#ibcon#ireg 7 cls_cnt 0 2006.203.07:38:21.37#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.203.07:38:21.49#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.203.07:38:21.49#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.203.07:38:21.49#ibcon#enter wrdev, iclass 13, count 0 2006.203.07:38:21.49#ibcon#first serial, iclass 13, count 0 2006.203.07:38:21.49#ibcon#enter sib2, iclass 13, count 0 2006.203.07:38:21.49#ibcon#flushed, iclass 13, count 0 2006.203.07:38:21.49#ibcon#about to write, iclass 13, count 0 2006.203.07:38:21.49#ibcon#wrote, iclass 13, count 0 2006.203.07:38:21.49#ibcon#about to read 3, iclass 13, count 0 2006.203.07:38:21.51#ibcon#read 3, iclass 13, count 0 2006.203.07:38:21.51#ibcon#about to read 4, iclass 13, count 0 2006.203.07:38:21.51#ibcon#read 4, iclass 13, count 0 2006.203.07:38:21.51#ibcon#about to read 5, iclass 13, count 0 2006.203.07:38:21.51#ibcon#read 5, iclass 13, count 0 2006.203.07:38:21.51#ibcon#about to read 6, iclass 13, count 0 2006.203.07:38:21.51#ibcon#read 6, iclass 13, count 0 2006.203.07:38:21.51#ibcon#end of sib2, iclass 13, count 0 2006.203.07:38:21.51#ibcon#*mode == 0, iclass 13, count 0 2006.203.07:38:21.51#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.203.07:38:21.51#ibcon#[25=USB\r\n] 2006.203.07:38:21.51#ibcon#*before write, iclass 13, count 0 2006.203.07:38:21.51#ibcon#enter sib2, iclass 13, count 0 2006.203.07:38:21.51#ibcon#flushed, iclass 13, count 0 2006.203.07:38:21.51#ibcon#about to write, iclass 13, count 0 2006.203.07:38:21.51#ibcon#wrote, iclass 13, count 0 2006.203.07:38:21.51#ibcon#about to read 3, iclass 13, count 0 2006.203.07:38:21.54#ibcon#read 3, iclass 13, count 0 2006.203.07:38:21.54#ibcon#about to read 4, iclass 13, count 0 2006.203.07:38:21.54#ibcon#read 4, iclass 13, count 0 2006.203.07:38:21.54#ibcon#about to read 5, iclass 13, count 0 2006.203.07:38:21.54#ibcon#read 5, iclass 13, count 0 2006.203.07:38:21.54#ibcon#about to read 6, iclass 13, count 0 2006.203.07:38:21.54#ibcon#read 6, iclass 13, count 0 2006.203.07:38:21.54#ibcon#end of sib2, iclass 13, count 0 2006.203.07:38:21.54#ibcon#*after write, iclass 13, count 0 2006.203.07:38:21.54#ibcon#*before return 0, iclass 13, count 0 2006.203.07:38:21.54#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.203.07:38:21.54#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.203.07:38:21.54#ibcon#about to clear, iclass 13 cls_cnt 0 2006.203.07:38:21.54#ibcon#cleared, iclass 13 cls_cnt 0 2006.203.07:38:21.54$vc4f8/valo=8,852.99 2006.203.07:38:21.54#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.203.07:38:21.54#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.203.07:38:21.54#ibcon#ireg 17 cls_cnt 0 2006.203.07:38:21.54#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.203.07:38:21.54#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.203.07:38:21.54#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.203.07:38:21.54#ibcon#enter wrdev, iclass 15, count 0 2006.203.07:38:21.54#ibcon#first serial, iclass 15, count 0 2006.203.07:38:21.54#ibcon#enter sib2, iclass 15, count 0 2006.203.07:38:21.54#ibcon#flushed, iclass 15, count 0 2006.203.07:38:21.54#ibcon#about to write, iclass 15, count 0 2006.203.07:38:21.54#ibcon#wrote, iclass 15, count 0 2006.203.07:38:21.54#ibcon#about to read 3, iclass 15, count 0 2006.203.07:38:21.56#ibcon#read 3, iclass 15, count 0 2006.203.07:38:21.56#ibcon#about to read 4, iclass 15, count 0 2006.203.07:38:21.56#ibcon#read 4, iclass 15, count 0 2006.203.07:38:21.56#ibcon#about to read 5, iclass 15, count 0 2006.203.07:38:21.56#ibcon#read 5, iclass 15, count 0 2006.203.07:38:21.56#ibcon#about to read 6, iclass 15, count 0 2006.203.07:38:21.56#ibcon#read 6, iclass 15, count 0 2006.203.07:38:21.56#ibcon#end of sib2, iclass 15, count 0 2006.203.07:38:21.56#ibcon#*mode == 0, iclass 15, count 0 2006.203.07:38:21.56#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.203.07:38:21.56#ibcon#[26=FRQ=08,852.99\r\n] 2006.203.07:38:21.56#ibcon#*before write, iclass 15, count 0 2006.203.07:38:21.56#ibcon#enter sib2, iclass 15, count 0 2006.203.07:38:21.56#ibcon#flushed, iclass 15, count 0 2006.203.07:38:21.56#ibcon#about to write, iclass 15, count 0 2006.203.07:38:21.56#ibcon#wrote, iclass 15, count 0 2006.203.07:38:21.56#ibcon#about to read 3, iclass 15, count 0 2006.203.07:38:21.60#ibcon#read 3, iclass 15, count 0 2006.203.07:38:21.60#ibcon#about to read 4, iclass 15, count 0 2006.203.07:38:21.60#ibcon#read 4, iclass 15, count 0 2006.203.07:38:21.60#ibcon#about to read 5, iclass 15, count 0 2006.203.07:38:21.60#ibcon#read 5, iclass 15, count 0 2006.203.07:38:21.60#ibcon#about to read 6, iclass 15, count 0 2006.203.07:38:21.60#ibcon#read 6, iclass 15, count 0 2006.203.07:38:21.60#ibcon#end of sib2, iclass 15, count 0 2006.203.07:38:21.60#ibcon#*after write, iclass 15, count 0 2006.203.07:38:21.60#ibcon#*before return 0, iclass 15, count 0 2006.203.07:38:21.60#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.203.07:38:21.60#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.203.07:38:21.60#ibcon#about to clear, iclass 15 cls_cnt 0 2006.203.07:38:21.60#ibcon#cleared, iclass 15 cls_cnt 0 2006.203.07:38:21.60$vc4f8/va=8,6 2006.203.07:38:21.60#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.203.07:38:21.60#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.203.07:38:21.60#ibcon#ireg 11 cls_cnt 2 2006.203.07:38:21.60#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.203.07:38:21.66#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.203.07:38:21.66#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.203.07:38:21.66#ibcon#enter wrdev, iclass 17, count 2 2006.203.07:38:21.66#ibcon#first serial, iclass 17, count 2 2006.203.07:38:21.66#ibcon#enter sib2, iclass 17, count 2 2006.203.07:38:21.66#ibcon#flushed, iclass 17, count 2 2006.203.07:38:21.66#ibcon#about to write, iclass 17, count 2 2006.203.07:38:21.66#ibcon#wrote, iclass 17, count 2 2006.203.07:38:21.66#ibcon#about to read 3, iclass 17, count 2 2006.203.07:38:21.68#ibcon#read 3, iclass 17, count 2 2006.203.07:38:21.68#ibcon#about to read 4, iclass 17, count 2 2006.203.07:38:21.68#ibcon#read 4, iclass 17, count 2 2006.203.07:38:21.68#ibcon#about to read 5, iclass 17, count 2 2006.203.07:38:21.68#ibcon#read 5, iclass 17, count 2 2006.203.07:38:21.68#ibcon#about to read 6, iclass 17, count 2 2006.203.07:38:21.68#ibcon#read 6, iclass 17, count 2 2006.203.07:38:21.68#ibcon#end of sib2, iclass 17, count 2 2006.203.07:38:21.68#ibcon#*mode == 0, iclass 17, count 2 2006.203.07:38:21.68#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.203.07:38:21.68#ibcon#[25=AT08-06\r\n] 2006.203.07:38:21.68#ibcon#*before write, iclass 17, count 2 2006.203.07:38:21.68#ibcon#enter sib2, iclass 17, count 2 2006.203.07:38:21.68#ibcon#flushed, iclass 17, count 2 2006.203.07:38:21.68#ibcon#about to write, iclass 17, count 2 2006.203.07:38:21.68#ibcon#wrote, iclass 17, count 2 2006.203.07:38:21.68#ibcon#about to read 3, iclass 17, count 2 2006.203.07:38:21.71#ibcon#read 3, iclass 17, count 2 2006.203.07:38:21.71#ibcon#about to read 4, iclass 17, count 2 2006.203.07:38:21.71#ibcon#read 4, iclass 17, count 2 2006.203.07:38:21.71#ibcon#about to read 5, iclass 17, count 2 2006.203.07:38:21.71#ibcon#read 5, iclass 17, count 2 2006.203.07:38:21.71#ibcon#about to read 6, iclass 17, count 2 2006.203.07:38:21.71#ibcon#read 6, iclass 17, count 2 2006.203.07:38:21.71#ibcon#end of sib2, iclass 17, count 2 2006.203.07:38:21.71#ibcon#*after write, iclass 17, count 2 2006.203.07:38:21.71#ibcon#*before return 0, iclass 17, count 2 2006.203.07:38:21.71#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.203.07:38:21.71#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.203.07:38:21.71#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.203.07:38:21.71#ibcon#ireg 7 cls_cnt 0 2006.203.07:38:21.71#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.203.07:38:21.83#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.203.07:38:21.83#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.203.07:38:21.83#ibcon#enter wrdev, iclass 17, count 0 2006.203.07:38:21.83#ibcon#first serial, iclass 17, count 0 2006.203.07:38:21.83#ibcon#enter sib2, iclass 17, count 0 2006.203.07:38:21.83#ibcon#flushed, iclass 17, count 0 2006.203.07:38:21.83#ibcon#about to write, iclass 17, count 0 2006.203.07:38:21.83#ibcon#wrote, iclass 17, count 0 2006.203.07:38:21.83#ibcon#about to read 3, iclass 17, count 0 2006.203.07:38:21.85#ibcon#read 3, iclass 17, count 0 2006.203.07:38:21.85#ibcon#about to read 4, iclass 17, count 0 2006.203.07:38:21.85#ibcon#read 4, iclass 17, count 0 2006.203.07:38:21.85#ibcon#about to read 5, iclass 17, count 0 2006.203.07:38:21.85#ibcon#read 5, iclass 17, count 0 2006.203.07:38:21.85#ibcon#about to read 6, iclass 17, count 0 2006.203.07:38:21.85#ibcon#read 6, iclass 17, count 0 2006.203.07:38:21.85#ibcon#end of sib2, iclass 17, count 0 2006.203.07:38:21.85#ibcon#*mode == 0, iclass 17, count 0 2006.203.07:38:21.85#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.203.07:38:21.85#ibcon#[25=USB\r\n] 2006.203.07:38:21.85#ibcon#*before write, iclass 17, count 0 2006.203.07:38:21.85#ibcon#enter sib2, iclass 17, count 0 2006.203.07:38:21.85#ibcon#flushed, iclass 17, count 0 2006.203.07:38:21.85#ibcon#about to write, iclass 17, count 0 2006.203.07:38:21.85#ibcon#wrote, iclass 17, count 0 2006.203.07:38:21.85#ibcon#about to read 3, iclass 17, count 0 2006.203.07:38:21.88#ibcon#read 3, iclass 17, count 0 2006.203.07:38:21.88#ibcon#about to read 4, iclass 17, count 0 2006.203.07:38:21.88#ibcon#read 4, iclass 17, count 0 2006.203.07:38:21.88#ibcon#about to read 5, iclass 17, count 0 2006.203.07:38:21.88#ibcon#read 5, iclass 17, count 0 2006.203.07:38:21.88#ibcon#about to read 6, iclass 17, count 0 2006.203.07:38:21.88#ibcon#read 6, iclass 17, count 0 2006.203.07:38:21.88#ibcon#end of sib2, iclass 17, count 0 2006.203.07:38:21.88#ibcon#*after write, iclass 17, count 0 2006.203.07:38:21.88#ibcon#*before return 0, iclass 17, count 0 2006.203.07:38:21.88#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.203.07:38:21.88#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.203.07:38:21.88#ibcon#about to clear, iclass 17 cls_cnt 0 2006.203.07:38:21.88#ibcon#cleared, iclass 17 cls_cnt 0 2006.203.07:38:21.88$vc4f8/vblo=1,632.99 2006.203.07:38:21.88#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.203.07:38:21.88#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.203.07:38:21.88#ibcon#ireg 17 cls_cnt 0 2006.203.07:38:21.88#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.203.07:38:21.88#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.203.07:38:21.88#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.203.07:38:21.88#ibcon#enter wrdev, iclass 19, count 0 2006.203.07:38:21.88#ibcon#first serial, iclass 19, count 0 2006.203.07:38:21.88#ibcon#enter sib2, iclass 19, count 0 2006.203.07:38:21.88#ibcon#flushed, iclass 19, count 0 2006.203.07:38:21.88#ibcon#about to write, iclass 19, count 0 2006.203.07:38:21.88#ibcon#wrote, iclass 19, count 0 2006.203.07:38:21.88#ibcon#about to read 3, iclass 19, count 0 2006.203.07:38:21.90#ibcon#read 3, iclass 19, count 0 2006.203.07:38:21.90#ibcon#about to read 4, iclass 19, count 0 2006.203.07:38:21.90#ibcon#read 4, iclass 19, count 0 2006.203.07:38:21.90#ibcon#about to read 5, iclass 19, count 0 2006.203.07:38:21.90#ibcon#read 5, iclass 19, count 0 2006.203.07:38:21.90#ibcon#about to read 6, iclass 19, count 0 2006.203.07:38:21.90#ibcon#read 6, iclass 19, count 0 2006.203.07:38:21.90#ibcon#end of sib2, iclass 19, count 0 2006.203.07:38:21.90#ibcon#*mode == 0, iclass 19, count 0 2006.203.07:38:21.90#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.203.07:38:21.90#ibcon#[28=FRQ=01,632.99\r\n] 2006.203.07:38:21.90#ibcon#*before write, iclass 19, count 0 2006.203.07:38:21.90#ibcon#enter sib2, iclass 19, count 0 2006.203.07:38:21.90#ibcon#flushed, iclass 19, count 0 2006.203.07:38:21.90#ibcon#about to write, iclass 19, count 0 2006.203.07:38:21.90#ibcon#wrote, iclass 19, count 0 2006.203.07:38:21.90#ibcon#about to read 3, iclass 19, count 0 2006.203.07:38:21.94#ibcon#read 3, iclass 19, count 0 2006.203.07:38:21.94#ibcon#about to read 4, iclass 19, count 0 2006.203.07:38:21.94#ibcon#read 4, iclass 19, count 0 2006.203.07:38:21.94#ibcon#about to read 5, iclass 19, count 0 2006.203.07:38:21.94#ibcon#read 5, iclass 19, count 0 2006.203.07:38:21.94#ibcon#about to read 6, iclass 19, count 0 2006.203.07:38:21.94#ibcon#read 6, iclass 19, count 0 2006.203.07:38:21.94#ibcon#end of sib2, iclass 19, count 0 2006.203.07:38:21.94#ibcon#*after write, iclass 19, count 0 2006.203.07:38:21.94#ibcon#*before return 0, iclass 19, count 0 2006.203.07:38:21.94#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.203.07:38:21.94#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.203.07:38:21.94#ibcon#about to clear, iclass 19 cls_cnt 0 2006.203.07:38:21.94#ibcon#cleared, iclass 19 cls_cnt 0 2006.203.07:38:21.94$vc4f8/vb=1,4 2006.203.07:38:21.94#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.203.07:38:21.94#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.203.07:38:21.94#ibcon#ireg 11 cls_cnt 2 2006.203.07:38:21.94#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.203.07:38:21.94#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.203.07:38:21.94#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.203.07:38:21.94#ibcon#enter wrdev, iclass 21, count 2 2006.203.07:38:21.94#ibcon#first serial, iclass 21, count 2 2006.203.07:38:21.94#ibcon#enter sib2, iclass 21, count 2 2006.203.07:38:21.94#ibcon#flushed, iclass 21, count 2 2006.203.07:38:21.94#ibcon#about to write, iclass 21, count 2 2006.203.07:38:21.94#ibcon#wrote, iclass 21, count 2 2006.203.07:38:21.94#ibcon#about to read 3, iclass 21, count 2 2006.203.07:38:21.96#ibcon#read 3, iclass 21, count 2 2006.203.07:38:21.96#ibcon#about to read 4, iclass 21, count 2 2006.203.07:38:21.96#ibcon#read 4, iclass 21, count 2 2006.203.07:38:21.96#ibcon#about to read 5, iclass 21, count 2 2006.203.07:38:21.96#ibcon#read 5, iclass 21, count 2 2006.203.07:38:21.96#ibcon#about to read 6, iclass 21, count 2 2006.203.07:38:21.96#ibcon#read 6, iclass 21, count 2 2006.203.07:38:21.96#ibcon#end of sib2, iclass 21, count 2 2006.203.07:38:21.96#ibcon#*mode == 0, iclass 21, count 2 2006.203.07:38:21.96#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.203.07:38:21.96#ibcon#[27=AT01-04\r\n] 2006.203.07:38:21.96#ibcon#*before write, iclass 21, count 2 2006.203.07:38:21.96#ibcon#enter sib2, iclass 21, count 2 2006.203.07:38:21.96#ibcon#flushed, iclass 21, count 2 2006.203.07:38:21.96#ibcon#about to write, iclass 21, count 2 2006.203.07:38:21.96#ibcon#wrote, iclass 21, count 2 2006.203.07:38:21.96#ibcon#about to read 3, iclass 21, count 2 2006.203.07:38:21.99#ibcon#read 3, iclass 21, count 2 2006.203.07:38:21.99#ibcon#about to read 4, iclass 21, count 2 2006.203.07:38:21.99#ibcon#read 4, iclass 21, count 2 2006.203.07:38:21.99#ibcon#about to read 5, iclass 21, count 2 2006.203.07:38:21.99#ibcon#read 5, iclass 21, count 2 2006.203.07:38:21.99#ibcon#about to read 6, iclass 21, count 2 2006.203.07:38:21.99#ibcon#read 6, iclass 21, count 2 2006.203.07:38:21.99#ibcon#end of sib2, iclass 21, count 2 2006.203.07:38:21.99#ibcon#*after write, iclass 21, count 2 2006.203.07:38:21.99#ibcon#*before return 0, iclass 21, count 2 2006.203.07:38:21.99#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.203.07:38:21.99#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.203.07:38:21.99#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.203.07:38:21.99#ibcon#ireg 7 cls_cnt 0 2006.203.07:38:21.99#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.203.07:38:22.08#abcon#<5=/06 2.3 4.4 23.98 971001.0\r\n> 2006.203.07:38:22.10#abcon#{5=INTERFACE CLEAR} 2006.203.07:38:22.11#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.203.07:38:22.11#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.203.07:38:22.11#ibcon#enter wrdev, iclass 21, count 0 2006.203.07:38:22.11#ibcon#first serial, iclass 21, count 0 2006.203.07:38:22.11#ibcon#enter sib2, iclass 21, count 0 2006.203.07:38:22.11#ibcon#flushed, iclass 21, count 0 2006.203.07:38:22.11#ibcon#about to write, iclass 21, count 0 2006.203.07:38:22.11#ibcon#wrote, iclass 21, count 0 2006.203.07:38:22.11#ibcon#about to read 3, iclass 21, count 0 2006.203.07:38:22.13#ibcon#read 3, iclass 21, count 0 2006.203.07:38:22.13#ibcon#about to read 4, iclass 21, count 0 2006.203.07:38:22.13#ibcon#read 4, iclass 21, count 0 2006.203.07:38:22.13#ibcon#about to read 5, iclass 21, count 0 2006.203.07:38:22.13#ibcon#read 5, iclass 21, count 0 2006.203.07:38:22.13#ibcon#about to read 6, iclass 21, count 0 2006.203.07:38:22.13#ibcon#read 6, iclass 21, count 0 2006.203.07:38:22.13#ibcon#end of sib2, iclass 21, count 0 2006.203.07:38:22.13#ibcon#*mode == 0, iclass 21, count 0 2006.203.07:38:22.13#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.203.07:38:22.13#ibcon#[27=USB\r\n] 2006.203.07:38:22.13#ibcon#*before write, iclass 21, count 0 2006.203.07:38:22.13#ibcon#enter sib2, iclass 21, count 0 2006.203.07:38:22.13#ibcon#flushed, iclass 21, count 0 2006.203.07:38:22.13#ibcon#about to write, iclass 21, count 0 2006.203.07:38:22.13#ibcon#wrote, iclass 21, count 0 2006.203.07:38:22.13#ibcon#about to read 3, iclass 21, count 0 2006.203.07:38:22.16#abcon#[5=S1D000X0/0*\r\n] 2006.203.07:38:22.16#ibcon#read 3, iclass 21, count 0 2006.203.07:38:22.16#ibcon#about to read 4, iclass 21, count 0 2006.203.07:38:22.16#ibcon#read 4, iclass 21, count 0 2006.203.07:38:22.16#ibcon#about to read 5, iclass 21, count 0 2006.203.07:38:22.16#ibcon#read 5, iclass 21, count 0 2006.203.07:38:22.16#ibcon#about to read 6, iclass 21, count 0 2006.203.07:38:22.16#ibcon#read 6, iclass 21, count 0 2006.203.07:38:22.16#ibcon#end of sib2, iclass 21, count 0 2006.203.07:38:22.16#ibcon#*after write, iclass 21, count 0 2006.203.07:38:22.16#ibcon#*before return 0, iclass 21, count 0 2006.203.07:38:22.16#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.203.07:38:22.16#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.203.07:38:22.16#ibcon#about to clear, iclass 21 cls_cnt 0 2006.203.07:38:22.16#ibcon#cleared, iclass 21 cls_cnt 0 2006.203.07:38:22.16$vc4f8/vblo=2,640.99 2006.203.07:38:22.16#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.203.07:38:22.16#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.203.07:38:22.16#ibcon#ireg 17 cls_cnt 0 2006.203.07:38:22.16#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:38:22.16#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:38:22.16#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:38:22.16#ibcon#enter wrdev, iclass 27, count 0 2006.203.07:38:22.16#ibcon#first serial, iclass 27, count 0 2006.203.07:38:22.16#ibcon#enter sib2, iclass 27, count 0 2006.203.07:38:22.16#ibcon#flushed, iclass 27, count 0 2006.203.07:38:22.16#ibcon#about to write, iclass 27, count 0 2006.203.07:38:22.16#ibcon#wrote, iclass 27, count 0 2006.203.07:38:22.16#ibcon#about to read 3, iclass 27, count 0 2006.203.07:38:22.19#ibcon#read 3, iclass 27, count 0 2006.203.07:38:22.19#ibcon#about to read 4, iclass 27, count 0 2006.203.07:38:22.19#ibcon#read 4, iclass 27, count 0 2006.203.07:38:22.19#ibcon#about to read 5, iclass 27, count 0 2006.203.07:38:22.19#ibcon#read 5, iclass 27, count 0 2006.203.07:38:22.19#ibcon#about to read 6, iclass 27, count 0 2006.203.07:38:22.19#ibcon#read 6, iclass 27, count 0 2006.203.07:38:22.19#ibcon#end of sib2, iclass 27, count 0 2006.203.07:38:22.19#ibcon#*mode == 0, iclass 27, count 0 2006.203.07:38:22.19#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.203.07:38:22.19#ibcon#[28=FRQ=02,640.99\r\n] 2006.203.07:38:22.19#ibcon#*before write, iclass 27, count 0 2006.203.07:38:22.19#ibcon#enter sib2, iclass 27, count 0 2006.203.07:38:22.19#ibcon#flushed, iclass 27, count 0 2006.203.07:38:22.19#ibcon#about to write, iclass 27, count 0 2006.203.07:38:22.19#ibcon#wrote, iclass 27, count 0 2006.203.07:38:22.19#ibcon#about to read 3, iclass 27, count 0 2006.203.07:38:22.22#ibcon#read 3, iclass 27, count 0 2006.203.07:38:22.22#ibcon#about to read 4, iclass 27, count 0 2006.203.07:38:22.22#ibcon#read 4, iclass 27, count 0 2006.203.07:38:22.22#ibcon#about to read 5, iclass 27, count 0 2006.203.07:38:22.22#ibcon#read 5, iclass 27, count 0 2006.203.07:38:22.22#ibcon#about to read 6, iclass 27, count 0 2006.203.07:38:22.22#ibcon#read 6, iclass 27, count 0 2006.203.07:38:22.22#ibcon#end of sib2, iclass 27, count 0 2006.203.07:38:22.22#ibcon#*after write, iclass 27, count 0 2006.203.07:38:22.22#ibcon#*before return 0, iclass 27, count 0 2006.203.07:38:22.22#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:38:22.22#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:38:22.22#ibcon#about to clear, iclass 27 cls_cnt 0 2006.203.07:38:22.22#ibcon#cleared, iclass 27 cls_cnt 0 2006.203.07:38:22.22$vc4f8/vb=2,4 2006.203.07:38:22.22#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.203.07:38:22.22#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.203.07:38:22.22#ibcon#ireg 11 cls_cnt 2 2006.203.07:38:22.22#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.203.07:38:22.28#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.203.07:38:22.28#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.203.07:38:22.28#ibcon#enter wrdev, iclass 29, count 2 2006.203.07:38:22.28#ibcon#first serial, iclass 29, count 2 2006.203.07:38:22.28#ibcon#enter sib2, iclass 29, count 2 2006.203.07:38:22.28#ibcon#flushed, iclass 29, count 2 2006.203.07:38:22.28#ibcon#about to write, iclass 29, count 2 2006.203.07:38:22.28#ibcon#wrote, iclass 29, count 2 2006.203.07:38:22.28#ibcon#about to read 3, iclass 29, count 2 2006.203.07:38:22.30#ibcon#read 3, iclass 29, count 2 2006.203.07:38:22.30#ibcon#about to read 4, iclass 29, count 2 2006.203.07:38:22.30#ibcon#read 4, iclass 29, count 2 2006.203.07:38:22.30#ibcon#about to read 5, iclass 29, count 2 2006.203.07:38:22.30#ibcon#read 5, iclass 29, count 2 2006.203.07:38:22.30#ibcon#about to read 6, iclass 29, count 2 2006.203.07:38:22.30#ibcon#read 6, iclass 29, count 2 2006.203.07:38:22.30#ibcon#end of sib2, iclass 29, count 2 2006.203.07:38:22.30#ibcon#*mode == 0, iclass 29, count 2 2006.203.07:38:22.30#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.203.07:38:22.30#ibcon#[27=AT02-04\r\n] 2006.203.07:38:22.30#ibcon#*before write, iclass 29, count 2 2006.203.07:38:22.30#ibcon#enter sib2, iclass 29, count 2 2006.203.07:38:22.30#ibcon#flushed, iclass 29, count 2 2006.203.07:38:22.30#ibcon#about to write, iclass 29, count 2 2006.203.07:38:22.30#ibcon#wrote, iclass 29, count 2 2006.203.07:38:22.30#ibcon#about to read 3, iclass 29, count 2 2006.203.07:38:22.33#ibcon#read 3, iclass 29, count 2 2006.203.07:38:22.33#ibcon#about to read 4, iclass 29, count 2 2006.203.07:38:22.33#ibcon#read 4, iclass 29, count 2 2006.203.07:38:22.33#ibcon#about to read 5, iclass 29, count 2 2006.203.07:38:22.33#ibcon#read 5, iclass 29, count 2 2006.203.07:38:22.33#ibcon#about to read 6, iclass 29, count 2 2006.203.07:38:22.33#ibcon#read 6, iclass 29, count 2 2006.203.07:38:22.33#ibcon#end of sib2, iclass 29, count 2 2006.203.07:38:22.33#ibcon#*after write, iclass 29, count 2 2006.203.07:38:22.33#ibcon#*before return 0, iclass 29, count 2 2006.203.07:38:22.33#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.203.07:38:22.33#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.203.07:38:22.33#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.203.07:38:22.33#ibcon#ireg 7 cls_cnt 0 2006.203.07:38:22.33#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.203.07:38:22.45#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.203.07:38:22.45#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.203.07:38:22.45#ibcon#enter wrdev, iclass 29, count 0 2006.203.07:38:22.45#ibcon#first serial, iclass 29, count 0 2006.203.07:38:22.45#ibcon#enter sib2, iclass 29, count 0 2006.203.07:38:22.45#ibcon#flushed, iclass 29, count 0 2006.203.07:38:22.45#ibcon#about to write, iclass 29, count 0 2006.203.07:38:22.45#ibcon#wrote, iclass 29, count 0 2006.203.07:38:22.45#ibcon#about to read 3, iclass 29, count 0 2006.203.07:38:22.47#ibcon#read 3, iclass 29, count 0 2006.203.07:38:22.47#ibcon#about to read 4, iclass 29, count 0 2006.203.07:38:22.47#ibcon#read 4, iclass 29, count 0 2006.203.07:38:22.47#ibcon#about to read 5, iclass 29, count 0 2006.203.07:38:22.47#ibcon#read 5, iclass 29, count 0 2006.203.07:38:22.47#ibcon#about to read 6, iclass 29, count 0 2006.203.07:38:22.47#ibcon#read 6, iclass 29, count 0 2006.203.07:38:22.47#ibcon#end of sib2, iclass 29, count 0 2006.203.07:38:22.47#ibcon#*mode == 0, iclass 29, count 0 2006.203.07:38:22.47#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.203.07:38:22.47#ibcon#[27=USB\r\n] 2006.203.07:38:22.47#ibcon#*before write, iclass 29, count 0 2006.203.07:38:22.47#ibcon#enter sib2, iclass 29, count 0 2006.203.07:38:22.47#ibcon#flushed, iclass 29, count 0 2006.203.07:38:22.47#ibcon#about to write, iclass 29, count 0 2006.203.07:38:22.47#ibcon#wrote, iclass 29, count 0 2006.203.07:38:22.47#ibcon#about to read 3, iclass 29, count 0 2006.203.07:38:22.50#ibcon#read 3, iclass 29, count 0 2006.203.07:38:22.50#ibcon#about to read 4, iclass 29, count 0 2006.203.07:38:22.50#ibcon#read 4, iclass 29, count 0 2006.203.07:38:22.50#ibcon#about to read 5, iclass 29, count 0 2006.203.07:38:22.50#ibcon#read 5, iclass 29, count 0 2006.203.07:38:22.50#ibcon#about to read 6, iclass 29, count 0 2006.203.07:38:22.50#ibcon#read 6, iclass 29, count 0 2006.203.07:38:22.50#ibcon#end of sib2, iclass 29, count 0 2006.203.07:38:22.50#ibcon#*after write, iclass 29, count 0 2006.203.07:38:22.50#ibcon#*before return 0, iclass 29, count 0 2006.203.07:38:22.50#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.203.07:38:22.50#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.203.07:38:22.50#ibcon#about to clear, iclass 29 cls_cnt 0 2006.203.07:38:22.50#ibcon#cleared, iclass 29 cls_cnt 0 2006.203.07:38:22.50$vc4f8/vblo=3,656.99 2006.203.07:38:22.50#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.203.07:38:22.50#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.203.07:38:22.50#ibcon#ireg 17 cls_cnt 0 2006.203.07:38:22.50#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.203.07:38:22.50#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.203.07:38:22.50#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.203.07:38:22.50#ibcon#enter wrdev, iclass 31, count 0 2006.203.07:38:22.50#ibcon#first serial, iclass 31, count 0 2006.203.07:38:22.50#ibcon#enter sib2, iclass 31, count 0 2006.203.07:38:22.50#ibcon#flushed, iclass 31, count 0 2006.203.07:38:22.50#ibcon#about to write, iclass 31, count 0 2006.203.07:38:22.50#ibcon#wrote, iclass 31, count 0 2006.203.07:38:22.50#ibcon#about to read 3, iclass 31, count 0 2006.203.07:38:22.52#ibcon#read 3, iclass 31, count 0 2006.203.07:38:22.52#ibcon#about to read 4, iclass 31, count 0 2006.203.07:38:22.52#ibcon#read 4, iclass 31, count 0 2006.203.07:38:22.52#ibcon#about to read 5, iclass 31, count 0 2006.203.07:38:22.52#ibcon#read 5, iclass 31, count 0 2006.203.07:38:22.52#ibcon#about to read 6, iclass 31, count 0 2006.203.07:38:22.52#ibcon#read 6, iclass 31, count 0 2006.203.07:38:22.52#ibcon#end of sib2, iclass 31, count 0 2006.203.07:38:22.52#ibcon#*mode == 0, iclass 31, count 0 2006.203.07:38:22.52#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.203.07:38:22.52#ibcon#[28=FRQ=03,656.99\r\n] 2006.203.07:38:22.52#ibcon#*before write, iclass 31, count 0 2006.203.07:38:22.52#ibcon#enter sib2, iclass 31, count 0 2006.203.07:38:22.52#ibcon#flushed, iclass 31, count 0 2006.203.07:38:22.52#ibcon#about to write, iclass 31, count 0 2006.203.07:38:22.52#ibcon#wrote, iclass 31, count 0 2006.203.07:38:22.52#ibcon#about to read 3, iclass 31, count 0 2006.203.07:38:22.56#ibcon#read 3, iclass 31, count 0 2006.203.07:38:22.56#ibcon#about to read 4, iclass 31, count 0 2006.203.07:38:22.56#ibcon#read 4, iclass 31, count 0 2006.203.07:38:22.56#ibcon#about to read 5, iclass 31, count 0 2006.203.07:38:22.56#ibcon#read 5, iclass 31, count 0 2006.203.07:38:22.56#ibcon#about to read 6, iclass 31, count 0 2006.203.07:38:22.56#ibcon#read 6, iclass 31, count 0 2006.203.07:38:22.56#ibcon#end of sib2, iclass 31, count 0 2006.203.07:38:22.56#ibcon#*after write, iclass 31, count 0 2006.203.07:38:22.56#ibcon#*before return 0, iclass 31, count 0 2006.203.07:38:22.56#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.203.07:38:22.56#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.203.07:38:22.56#ibcon#about to clear, iclass 31 cls_cnt 0 2006.203.07:38:22.56#ibcon#cleared, iclass 31 cls_cnt 0 2006.203.07:38:22.56$vc4f8/vb=3,4 2006.203.07:38:22.56#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.203.07:38:22.56#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.203.07:38:22.56#ibcon#ireg 11 cls_cnt 2 2006.203.07:38:22.56#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.203.07:38:22.62#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.203.07:38:22.62#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.203.07:38:22.62#ibcon#enter wrdev, iclass 33, count 2 2006.203.07:38:22.62#ibcon#first serial, iclass 33, count 2 2006.203.07:38:22.62#ibcon#enter sib2, iclass 33, count 2 2006.203.07:38:22.62#ibcon#flushed, iclass 33, count 2 2006.203.07:38:22.62#ibcon#about to write, iclass 33, count 2 2006.203.07:38:22.62#ibcon#wrote, iclass 33, count 2 2006.203.07:38:22.62#ibcon#about to read 3, iclass 33, count 2 2006.203.07:38:22.64#ibcon#read 3, iclass 33, count 2 2006.203.07:38:22.64#ibcon#about to read 4, iclass 33, count 2 2006.203.07:38:22.64#ibcon#read 4, iclass 33, count 2 2006.203.07:38:22.64#ibcon#about to read 5, iclass 33, count 2 2006.203.07:38:22.64#ibcon#read 5, iclass 33, count 2 2006.203.07:38:22.64#ibcon#about to read 6, iclass 33, count 2 2006.203.07:38:22.64#ibcon#read 6, iclass 33, count 2 2006.203.07:38:22.64#ibcon#end of sib2, iclass 33, count 2 2006.203.07:38:22.64#ibcon#*mode == 0, iclass 33, count 2 2006.203.07:38:22.64#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.203.07:38:22.64#ibcon#[27=AT03-04\r\n] 2006.203.07:38:22.64#ibcon#*before write, iclass 33, count 2 2006.203.07:38:22.64#ibcon#enter sib2, iclass 33, count 2 2006.203.07:38:22.64#ibcon#flushed, iclass 33, count 2 2006.203.07:38:22.64#ibcon#about to write, iclass 33, count 2 2006.203.07:38:22.64#ibcon#wrote, iclass 33, count 2 2006.203.07:38:22.64#ibcon#about to read 3, iclass 33, count 2 2006.203.07:38:22.67#ibcon#read 3, iclass 33, count 2 2006.203.07:38:22.67#ibcon#about to read 4, iclass 33, count 2 2006.203.07:38:22.67#ibcon#read 4, iclass 33, count 2 2006.203.07:38:22.67#ibcon#about to read 5, iclass 33, count 2 2006.203.07:38:22.67#ibcon#read 5, iclass 33, count 2 2006.203.07:38:22.67#ibcon#about to read 6, iclass 33, count 2 2006.203.07:38:22.67#ibcon#read 6, iclass 33, count 2 2006.203.07:38:22.67#ibcon#end of sib2, iclass 33, count 2 2006.203.07:38:22.67#ibcon#*after write, iclass 33, count 2 2006.203.07:38:22.67#ibcon#*before return 0, iclass 33, count 2 2006.203.07:38:22.67#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.203.07:38:22.67#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.203.07:38:22.67#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.203.07:38:22.67#ibcon#ireg 7 cls_cnt 0 2006.203.07:38:22.67#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.203.07:38:22.79#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.203.07:38:22.79#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.203.07:38:22.79#ibcon#enter wrdev, iclass 33, count 0 2006.203.07:38:22.79#ibcon#first serial, iclass 33, count 0 2006.203.07:38:22.79#ibcon#enter sib2, iclass 33, count 0 2006.203.07:38:22.79#ibcon#flushed, iclass 33, count 0 2006.203.07:38:22.79#ibcon#about to write, iclass 33, count 0 2006.203.07:38:22.79#ibcon#wrote, iclass 33, count 0 2006.203.07:38:22.79#ibcon#about to read 3, iclass 33, count 0 2006.203.07:38:22.81#ibcon#read 3, iclass 33, count 0 2006.203.07:38:22.81#ibcon#about to read 4, iclass 33, count 0 2006.203.07:38:22.81#ibcon#read 4, iclass 33, count 0 2006.203.07:38:22.81#ibcon#about to read 5, iclass 33, count 0 2006.203.07:38:22.81#ibcon#read 5, iclass 33, count 0 2006.203.07:38:22.81#ibcon#about to read 6, iclass 33, count 0 2006.203.07:38:22.81#ibcon#read 6, iclass 33, count 0 2006.203.07:38:22.81#ibcon#end of sib2, iclass 33, count 0 2006.203.07:38:22.81#ibcon#*mode == 0, iclass 33, count 0 2006.203.07:38:22.81#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.203.07:38:22.81#ibcon#[27=USB\r\n] 2006.203.07:38:22.81#ibcon#*before write, iclass 33, count 0 2006.203.07:38:22.81#ibcon#enter sib2, iclass 33, count 0 2006.203.07:38:22.81#ibcon#flushed, iclass 33, count 0 2006.203.07:38:22.81#ibcon#about to write, iclass 33, count 0 2006.203.07:38:22.81#ibcon#wrote, iclass 33, count 0 2006.203.07:38:22.81#ibcon#about to read 3, iclass 33, count 0 2006.203.07:38:22.84#ibcon#read 3, iclass 33, count 0 2006.203.07:38:22.84#ibcon#about to read 4, iclass 33, count 0 2006.203.07:38:22.84#ibcon#read 4, iclass 33, count 0 2006.203.07:38:22.84#ibcon#about to read 5, iclass 33, count 0 2006.203.07:38:22.84#ibcon#read 5, iclass 33, count 0 2006.203.07:38:22.84#ibcon#about to read 6, iclass 33, count 0 2006.203.07:38:22.84#ibcon#read 6, iclass 33, count 0 2006.203.07:38:22.84#ibcon#end of sib2, iclass 33, count 0 2006.203.07:38:22.84#ibcon#*after write, iclass 33, count 0 2006.203.07:38:22.84#ibcon#*before return 0, iclass 33, count 0 2006.203.07:38:22.84#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.203.07:38:22.84#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.203.07:38:22.84#ibcon#about to clear, iclass 33 cls_cnt 0 2006.203.07:38:22.84#ibcon#cleared, iclass 33 cls_cnt 0 2006.203.07:38:22.84$vc4f8/vblo=4,712.99 2006.203.07:38:22.84#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.203.07:38:22.84#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.203.07:38:22.84#ibcon#ireg 17 cls_cnt 0 2006.203.07:38:22.84#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.203.07:38:22.84#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.203.07:38:22.84#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.203.07:38:22.84#ibcon#enter wrdev, iclass 35, count 0 2006.203.07:38:22.84#ibcon#first serial, iclass 35, count 0 2006.203.07:38:22.84#ibcon#enter sib2, iclass 35, count 0 2006.203.07:38:22.84#ibcon#flushed, iclass 35, count 0 2006.203.07:38:22.84#ibcon#about to write, iclass 35, count 0 2006.203.07:38:22.84#ibcon#wrote, iclass 35, count 0 2006.203.07:38:22.84#ibcon#about to read 3, iclass 35, count 0 2006.203.07:38:22.86#ibcon#read 3, iclass 35, count 0 2006.203.07:38:22.86#ibcon#about to read 4, iclass 35, count 0 2006.203.07:38:22.86#ibcon#read 4, iclass 35, count 0 2006.203.07:38:22.86#ibcon#about to read 5, iclass 35, count 0 2006.203.07:38:22.86#ibcon#read 5, iclass 35, count 0 2006.203.07:38:22.86#ibcon#about to read 6, iclass 35, count 0 2006.203.07:38:22.86#ibcon#read 6, iclass 35, count 0 2006.203.07:38:22.86#ibcon#end of sib2, iclass 35, count 0 2006.203.07:38:22.86#ibcon#*mode == 0, iclass 35, count 0 2006.203.07:38:22.86#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.203.07:38:22.86#ibcon#[28=FRQ=04,712.99\r\n] 2006.203.07:38:22.86#ibcon#*before write, iclass 35, count 0 2006.203.07:38:22.86#ibcon#enter sib2, iclass 35, count 0 2006.203.07:38:22.86#ibcon#flushed, iclass 35, count 0 2006.203.07:38:22.86#ibcon#about to write, iclass 35, count 0 2006.203.07:38:22.86#ibcon#wrote, iclass 35, count 0 2006.203.07:38:22.86#ibcon#about to read 3, iclass 35, count 0 2006.203.07:38:22.90#ibcon#read 3, iclass 35, count 0 2006.203.07:38:22.90#ibcon#about to read 4, iclass 35, count 0 2006.203.07:38:22.90#ibcon#read 4, iclass 35, count 0 2006.203.07:38:22.90#ibcon#about to read 5, iclass 35, count 0 2006.203.07:38:22.90#ibcon#read 5, iclass 35, count 0 2006.203.07:38:22.90#ibcon#about to read 6, iclass 35, count 0 2006.203.07:38:22.90#ibcon#read 6, iclass 35, count 0 2006.203.07:38:22.90#ibcon#end of sib2, iclass 35, count 0 2006.203.07:38:22.90#ibcon#*after write, iclass 35, count 0 2006.203.07:38:22.90#ibcon#*before return 0, iclass 35, count 0 2006.203.07:38:22.90#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.203.07:38:22.90#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.203.07:38:22.90#ibcon#about to clear, iclass 35 cls_cnt 0 2006.203.07:38:22.90#ibcon#cleared, iclass 35 cls_cnt 0 2006.203.07:38:22.90$vc4f8/vb=4,4 2006.203.07:38:22.90#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.203.07:38:22.90#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.203.07:38:22.90#ibcon#ireg 11 cls_cnt 2 2006.203.07:38:22.90#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.203.07:38:22.96#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.203.07:38:22.96#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.203.07:38:22.96#ibcon#enter wrdev, iclass 37, count 2 2006.203.07:38:22.96#ibcon#first serial, iclass 37, count 2 2006.203.07:38:22.96#ibcon#enter sib2, iclass 37, count 2 2006.203.07:38:22.96#ibcon#flushed, iclass 37, count 2 2006.203.07:38:22.96#ibcon#about to write, iclass 37, count 2 2006.203.07:38:22.96#ibcon#wrote, iclass 37, count 2 2006.203.07:38:22.96#ibcon#about to read 3, iclass 37, count 2 2006.203.07:38:22.98#ibcon#read 3, iclass 37, count 2 2006.203.07:38:22.98#ibcon#about to read 4, iclass 37, count 2 2006.203.07:38:22.98#ibcon#read 4, iclass 37, count 2 2006.203.07:38:22.98#ibcon#about to read 5, iclass 37, count 2 2006.203.07:38:22.98#ibcon#read 5, iclass 37, count 2 2006.203.07:38:22.98#ibcon#about to read 6, iclass 37, count 2 2006.203.07:38:22.98#ibcon#read 6, iclass 37, count 2 2006.203.07:38:22.98#ibcon#end of sib2, iclass 37, count 2 2006.203.07:38:22.98#ibcon#*mode == 0, iclass 37, count 2 2006.203.07:38:22.98#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.203.07:38:22.98#ibcon#[27=AT04-04\r\n] 2006.203.07:38:22.98#ibcon#*before write, iclass 37, count 2 2006.203.07:38:22.98#ibcon#enter sib2, iclass 37, count 2 2006.203.07:38:22.98#ibcon#flushed, iclass 37, count 2 2006.203.07:38:22.98#ibcon#about to write, iclass 37, count 2 2006.203.07:38:22.98#ibcon#wrote, iclass 37, count 2 2006.203.07:38:22.98#ibcon#about to read 3, iclass 37, count 2 2006.203.07:38:23.01#ibcon#read 3, iclass 37, count 2 2006.203.07:38:23.01#ibcon#about to read 4, iclass 37, count 2 2006.203.07:38:23.01#ibcon#read 4, iclass 37, count 2 2006.203.07:38:23.01#ibcon#about to read 5, iclass 37, count 2 2006.203.07:38:23.01#ibcon#read 5, iclass 37, count 2 2006.203.07:38:23.01#ibcon#about to read 6, iclass 37, count 2 2006.203.07:38:23.01#ibcon#read 6, iclass 37, count 2 2006.203.07:38:23.01#ibcon#end of sib2, iclass 37, count 2 2006.203.07:38:23.01#ibcon#*after write, iclass 37, count 2 2006.203.07:38:23.01#ibcon#*before return 0, iclass 37, count 2 2006.203.07:38:23.01#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.203.07:38:23.01#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.203.07:38:23.01#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.203.07:38:23.01#ibcon#ireg 7 cls_cnt 0 2006.203.07:38:23.01#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.203.07:38:23.13#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.203.07:38:23.13#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.203.07:38:23.13#ibcon#enter wrdev, iclass 37, count 0 2006.203.07:38:23.13#ibcon#first serial, iclass 37, count 0 2006.203.07:38:23.13#ibcon#enter sib2, iclass 37, count 0 2006.203.07:38:23.13#ibcon#flushed, iclass 37, count 0 2006.203.07:38:23.13#ibcon#about to write, iclass 37, count 0 2006.203.07:38:23.13#ibcon#wrote, iclass 37, count 0 2006.203.07:38:23.13#ibcon#about to read 3, iclass 37, count 0 2006.203.07:38:23.15#ibcon#read 3, iclass 37, count 0 2006.203.07:38:23.15#ibcon#about to read 4, iclass 37, count 0 2006.203.07:38:23.15#ibcon#read 4, iclass 37, count 0 2006.203.07:38:23.15#ibcon#about to read 5, iclass 37, count 0 2006.203.07:38:23.15#ibcon#read 5, iclass 37, count 0 2006.203.07:38:23.15#ibcon#about to read 6, iclass 37, count 0 2006.203.07:38:23.15#ibcon#read 6, iclass 37, count 0 2006.203.07:38:23.15#ibcon#end of sib2, iclass 37, count 0 2006.203.07:38:23.15#ibcon#*mode == 0, iclass 37, count 0 2006.203.07:38:23.15#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.203.07:38:23.15#ibcon#[27=USB\r\n] 2006.203.07:38:23.15#ibcon#*before write, iclass 37, count 0 2006.203.07:38:23.15#ibcon#enter sib2, iclass 37, count 0 2006.203.07:38:23.15#ibcon#flushed, iclass 37, count 0 2006.203.07:38:23.15#ibcon#about to write, iclass 37, count 0 2006.203.07:38:23.15#ibcon#wrote, iclass 37, count 0 2006.203.07:38:23.15#ibcon#about to read 3, iclass 37, count 0 2006.203.07:38:23.18#ibcon#read 3, iclass 37, count 0 2006.203.07:38:23.18#ibcon#about to read 4, iclass 37, count 0 2006.203.07:38:23.18#ibcon#read 4, iclass 37, count 0 2006.203.07:38:23.18#ibcon#about to read 5, iclass 37, count 0 2006.203.07:38:23.18#ibcon#read 5, iclass 37, count 0 2006.203.07:38:23.18#ibcon#about to read 6, iclass 37, count 0 2006.203.07:38:23.18#ibcon#read 6, iclass 37, count 0 2006.203.07:38:23.18#ibcon#end of sib2, iclass 37, count 0 2006.203.07:38:23.18#ibcon#*after write, iclass 37, count 0 2006.203.07:38:23.18#ibcon#*before return 0, iclass 37, count 0 2006.203.07:38:23.18#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.203.07:38:23.18#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.203.07:38:23.18#ibcon#about to clear, iclass 37 cls_cnt 0 2006.203.07:38:23.18#ibcon#cleared, iclass 37 cls_cnt 0 2006.203.07:38:23.18$vc4f8/vblo=5,744.99 2006.203.07:38:23.18#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.203.07:38:23.18#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.203.07:38:23.18#ibcon#ireg 17 cls_cnt 0 2006.203.07:38:23.18#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.203.07:38:23.18#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.203.07:38:23.18#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.203.07:38:23.18#ibcon#enter wrdev, iclass 39, count 0 2006.203.07:38:23.18#ibcon#first serial, iclass 39, count 0 2006.203.07:38:23.18#ibcon#enter sib2, iclass 39, count 0 2006.203.07:38:23.18#ibcon#flushed, iclass 39, count 0 2006.203.07:38:23.18#ibcon#about to write, iclass 39, count 0 2006.203.07:38:23.18#ibcon#wrote, iclass 39, count 0 2006.203.07:38:23.18#ibcon#about to read 3, iclass 39, count 0 2006.203.07:38:23.20#ibcon#read 3, iclass 39, count 0 2006.203.07:38:23.20#ibcon#about to read 4, iclass 39, count 0 2006.203.07:38:23.20#ibcon#read 4, iclass 39, count 0 2006.203.07:38:23.20#ibcon#about to read 5, iclass 39, count 0 2006.203.07:38:23.20#ibcon#read 5, iclass 39, count 0 2006.203.07:38:23.20#ibcon#about to read 6, iclass 39, count 0 2006.203.07:38:23.20#ibcon#read 6, iclass 39, count 0 2006.203.07:38:23.20#ibcon#end of sib2, iclass 39, count 0 2006.203.07:38:23.20#ibcon#*mode == 0, iclass 39, count 0 2006.203.07:38:23.20#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.203.07:38:23.20#ibcon#[28=FRQ=05,744.99\r\n] 2006.203.07:38:23.20#ibcon#*before write, iclass 39, count 0 2006.203.07:38:23.20#ibcon#enter sib2, iclass 39, count 0 2006.203.07:38:23.20#ibcon#flushed, iclass 39, count 0 2006.203.07:38:23.20#ibcon#about to write, iclass 39, count 0 2006.203.07:38:23.20#ibcon#wrote, iclass 39, count 0 2006.203.07:38:23.20#ibcon#about to read 3, iclass 39, count 0 2006.203.07:38:23.24#ibcon#read 3, iclass 39, count 0 2006.203.07:38:23.24#ibcon#about to read 4, iclass 39, count 0 2006.203.07:38:23.24#ibcon#read 4, iclass 39, count 0 2006.203.07:38:23.24#ibcon#about to read 5, iclass 39, count 0 2006.203.07:38:23.24#ibcon#read 5, iclass 39, count 0 2006.203.07:38:23.24#ibcon#about to read 6, iclass 39, count 0 2006.203.07:38:23.24#ibcon#read 6, iclass 39, count 0 2006.203.07:38:23.24#ibcon#end of sib2, iclass 39, count 0 2006.203.07:38:23.24#ibcon#*after write, iclass 39, count 0 2006.203.07:38:23.24#ibcon#*before return 0, iclass 39, count 0 2006.203.07:38:23.24#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.203.07:38:23.24#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.203.07:38:23.24#ibcon#about to clear, iclass 39 cls_cnt 0 2006.203.07:38:23.24#ibcon#cleared, iclass 39 cls_cnt 0 2006.203.07:38:23.24$vc4f8/vb=5,3 2006.203.07:38:23.24#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.203.07:38:23.24#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.203.07:38:23.24#ibcon#ireg 11 cls_cnt 2 2006.203.07:38:23.24#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.203.07:38:23.30#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.203.07:38:23.30#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.203.07:38:23.30#ibcon#enter wrdev, iclass 3, count 2 2006.203.07:38:23.30#ibcon#first serial, iclass 3, count 2 2006.203.07:38:23.30#ibcon#enter sib2, iclass 3, count 2 2006.203.07:38:23.30#ibcon#flushed, iclass 3, count 2 2006.203.07:38:23.30#ibcon#about to write, iclass 3, count 2 2006.203.07:38:23.30#ibcon#wrote, iclass 3, count 2 2006.203.07:38:23.30#ibcon#about to read 3, iclass 3, count 2 2006.203.07:38:23.32#ibcon#read 3, iclass 3, count 2 2006.203.07:38:23.32#ibcon#about to read 4, iclass 3, count 2 2006.203.07:38:23.32#ibcon#read 4, iclass 3, count 2 2006.203.07:38:23.32#ibcon#about to read 5, iclass 3, count 2 2006.203.07:38:23.32#ibcon#read 5, iclass 3, count 2 2006.203.07:38:23.32#ibcon#about to read 6, iclass 3, count 2 2006.203.07:38:23.32#ibcon#read 6, iclass 3, count 2 2006.203.07:38:23.32#ibcon#end of sib2, iclass 3, count 2 2006.203.07:38:23.32#ibcon#*mode == 0, iclass 3, count 2 2006.203.07:38:23.32#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.203.07:38:23.32#ibcon#[27=AT05-03\r\n] 2006.203.07:38:23.32#ibcon#*before write, iclass 3, count 2 2006.203.07:38:23.32#ibcon#enter sib2, iclass 3, count 2 2006.203.07:38:23.32#ibcon#flushed, iclass 3, count 2 2006.203.07:38:23.32#ibcon#about to write, iclass 3, count 2 2006.203.07:38:23.32#ibcon#wrote, iclass 3, count 2 2006.203.07:38:23.32#ibcon#about to read 3, iclass 3, count 2 2006.203.07:38:23.35#ibcon#read 3, iclass 3, count 2 2006.203.07:38:23.35#ibcon#about to read 4, iclass 3, count 2 2006.203.07:38:23.35#ibcon#read 4, iclass 3, count 2 2006.203.07:38:23.35#ibcon#about to read 5, iclass 3, count 2 2006.203.07:38:23.35#ibcon#read 5, iclass 3, count 2 2006.203.07:38:23.35#ibcon#about to read 6, iclass 3, count 2 2006.203.07:38:23.35#ibcon#read 6, iclass 3, count 2 2006.203.07:38:23.35#ibcon#end of sib2, iclass 3, count 2 2006.203.07:38:23.35#ibcon#*after write, iclass 3, count 2 2006.203.07:38:23.35#ibcon#*before return 0, iclass 3, count 2 2006.203.07:38:23.35#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.203.07:38:23.35#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.203.07:38:23.35#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.203.07:38:23.35#ibcon#ireg 7 cls_cnt 0 2006.203.07:38:23.35#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.203.07:38:23.47#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.203.07:38:23.47#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.203.07:38:23.47#ibcon#enter wrdev, iclass 3, count 0 2006.203.07:38:23.47#ibcon#first serial, iclass 3, count 0 2006.203.07:38:23.47#ibcon#enter sib2, iclass 3, count 0 2006.203.07:38:23.47#ibcon#flushed, iclass 3, count 0 2006.203.07:38:23.47#ibcon#about to write, iclass 3, count 0 2006.203.07:38:23.47#ibcon#wrote, iclass 3, count 0 2006.203.07:38:23.47#ibcon#about to read 3, iclass 3, count 0 2006.203.07:38:23.49#ibcon#read 3, iclass 3, count 0 2006.203.07:38:23.49#ibcon#about to read 4, iclass 3, count 0 2006.203.07:38:23.49#ibcon#read 4, iclass 3, count 0 2006.203.07:38:23.49#ibcon#about to read 5, iclass 3, count 0 2006.203.07:38:23.49#ibcon#read 5, iclass 3, count 0 2006.203.07:38:23.49#ibcon#about to read 6, iclass 3, count 0 2006.203.07:38:23.49#ibcon#read 6, iclass 3, count 0 2006.203.07:38:23.49#ibcon#end of sib2, iclass 3, count 0 2006.203.07:38:23.49#ibcon#*mode == 0, iclass 3, count 0 2006.203.07:38:23.49#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.203.07:38:23.49#ibcon#[27=USB\r\n] 2006.203.07:38:23.49#ibcon#*before write, iclass 3, count 0 2006.203.07:38:23.49#ibcon#enter sib2, iclass 3, count 0 2006.203.07:38:23.49#ibcon#flushed, iclass 3, count 0 2006.203.07:38:23.49#ibcon#about to write, iclass 3, count 0 2006.203.07:38:23.49#ibcon#wrote, iclass 3, count 0 2006.203.07:38:23.49#ibcon#about to read 3, iclass 3, count 0 2006.203.07:38:23.52#ibcon#read 3, iclass 3, count 0 2006.203.07:38:23.52#ibcon#about to read 4, iclass 3, count 0 2006.203.07:38:23.52#ibcon#read 4, iclass 3, count 0 2006.203.07:38:23.52#ibcon#about to read 5, iclass 3, count 0 2006.203.07:38:23.52#ibcon#read 5, iclass 3, count 0 2006.203.07:38:23.52#ibcon#about to read 6, iclass 3, count 0 2006.203.07:38:23.52#ibcon#read 6, iclass 3, count 0 2006.203.07:38:23.52#ibcon#end of sib2, iclass 3, count 0 2006.203.07:38:23.52#ibcon#*after write, iclass 3, count 0 2006.203.07:38:23.52#ibcon#*before return 0, iclass 3, count 0 2006.203.07:38:23.52#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.203.07:38:23.52#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.203.07:38:23.52#ibcon#about to clear, iclass 3 cls_cnt 0 2006.203.07:38:23.52#ibcon#cleared, iclass 3 cls_cnt 0 2006.203.07:38:23.52$vc4f8/vblo=6,752.99 2006.203.07:38:23.52#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.203.07:38:23.52#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.203.07:38:23.52#ibcon#ireg 17 cls_cnt 0 2006.203.07:38:23.52#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.203.07:38:23.52#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.203.07:38:23.52#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.203.07:38:23.52#ibcon#enter wrdev, iclass 5, count 0 2006.203.07:38:23.52#ibcon#first serial, iclass 5, count 0 2006.203.07:38:23.52#ibcon#enter sib2, iclass 5, count 0 2006.203.07:38:23.52#ibcon#flushed, iclass 5, count 0 2006.203.07:38:23.52#ibcon#about to write, iclass 5, count 0 2006.203.07:38:23.52#ibcon#wrote, iclass 5, count 0 2006.203.07:38:23.52#ibcon#about to read 3, iclass 5, count 0 2006.203.07:38:23.54#ibcon#read 3, iclass 5, count 0 2006.203.07:38:23.54#ibcon#about to read 4, iclass 5, count 0 2006.203.07:38:23.54#ibcon#read 4, iclass 5, count 0 2006.203.07:38:23.54#ibcon#about to read 5, iclass 5, count 0 2006.203.07:38:23.54#ibcon#read 5, iclass 5, count 0 2006.203.07:38:23.54#ibcon#about to read 6, iclass 5, count 0 2006.203.07:38:23.54#ibcon#read 6, iclass 5, count 0 2006.203.07:38:23.54#ibcon#end of sib2, iclass 5, count 0 2006.203.07:38:23.54#ibcon#*mode == 0, iclass 5, count 0 2006.203.07:38:23.54#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.203.07:38:23.54#ibcon#[28=FRQ=06,752.99\r\n] 2006.203.07:38:23.54#ibcon#*before write, iclass 5, count 0 2006.203.07:38:23.54#ibcon#enter sib2, iclass 5, count 0 2006.203.07:38:23.54#ibcon#flushed, iclass 5, count 0 2006.203.07:38:23.54#ibcon#about to write, iclass 5, count 0 2006.203.07:38:23.54#ibcon#wrote, iclass 5, count 0 2006.203.07:38:23.54#ibcon#about to read 3, iclass 5, count 0 2006.203.07:38:23.58#ibcon#read 3, iclass 5, count 0 2006.203.07:38:23.58#ibcon#about to read 4, iclass 5, count 0 2006.203.07:38:23.58#ibcon#read 4, iclass 5, count 0 2006.203.07:38:23.58#ibcon#about to read 5, iclass 5, count 0 2006.203.07:38:23.58#ibcon#read 5, iclass 5, count 0 2006.203.07:38:23.58#ibcon#about to read 6, iclass 5, count 0 2006.203.07:38:23.58#ibcon#read 6, iclass 5, count 0 2006.203.07:38:23.58#ibcon#end of sib2, iclass 5, count 0 2006.203.07:38:23.58#ibcon#*after write, iclass 5, count 0 2006.203.07:38:23.58#ibcon#*before return 0, iclass 5, count 0 2006.203.07:38:23.58#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.203.07:38:23.58#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.203.07:38:23.58#ibcon#about to clear, iclass 5 cls_cnt 0 2006.203.07:38:23.58#ibcon#cleared, iclass 5 cls_cnt 0 2006.203.07:38:23.58$vc4f8/vb=6,4 2006.203.07:38:23.58#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.203.07:38:23.58#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.203.07:38:23.58#ibcon#ireg 11 cls_cnt 2 2006.203.07:38:23.58#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.203.07:38:23.64#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.203.07:38:23.64#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.203.07:38:23.64#ibcon#enter wrdev, iclass 7, count 2 2006.203.07:38:23.64#ibcon#first serial, iclass 7, count 2 2006.203.07:38:23.64#ibcon#enter sib2, iclass 7, count 2 2006.203.07:38:23.64#ibcon#flushed, iclass 7, count 2 2006.203.07:38:23.64#ibcon#about to write, iclass 7, count 2 2006.203.07:38:23.64#ibcon#wrote, iclass 7, count 2 2006.203.07:38:23.64#ibcon#about to read 3, iclass 7, count 2 2006.203.07:38:23.66#ibcon#read 3, iclass 7, count 2 2006.203.07:38:23.66#ibcon#about to read 4, iclass 7, count 2 2006.203.07:38:23.66#ibcon#read 4, iclass 7, count 2 2006.203.07:38:23.66#ibcon#about to read 5, iclass 7, count 2 2006.203.07:38:23.66#ibcon#read 5, iclass 7, count 2 2006.203.07:38:23.66#ibcon#about to read 6, iclass 7, count 2 2006.203.07:38:23.66#ibcon#read 6, iclass 7, count 2 2006.203.07:38:23.66#ibcon#end of sib2, iclass 7, count 2 2006.203.07:38:23.66#ibcon#*mode == 0, iclass 7, count 2 2006.203.07:38:23.66#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.203.07:38:23.66#ibcon#[27=AT06-04\r\n] 2006.203.07:38:23.66#ibcon#*before write, iclass 7, count 2 2006.203.07:38:23.66#ibcon#enter sib2, iclass 7, count 2 2006.203.07:38:23.66#ibcon#flushed, iclass 7, count 2 2006.203.07:38:23.66#ibcon#about to write, iclass 7, count 2 2006.203.07:38:23.66#ibcon#wrote, iclass 7, count 2 2006.203.07:38:23.66#ibcon#about to read 3, iclass 7, count 2 2006.203.07:38:23.69#ibcon#read 3, iclass 7, count 2 2006.203.07:38:23.69#ibcon#about to read 4, iclass 7, count 2 2006.203.07:38:23.69#ibcon#read 4, iclass 7, count 2 2006.203.07:38:23.69#ibcon#about to read 5, iclass 7, count 2 2006.203.07:38:23.69#ibcon#read 5, iclass 7, count 2 2006.203.07:38:23.69#ibcon#about to read 6, iclass 7, count 2 2006.203.07:38:23.69#ibcon#read 6, iclass 7, count 2 2006.203.07:38:23.69#ibcon#end of sib2, iclass 7, count 2 2006.203.07:38:23.69#ibcon#*after write, iclass 7, count 2 2006.203.07:38:23.69#ibcon#*before return 0, iclass 7, count 2 2006.203.07:38:23.69#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.203.07:38:23.69#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.203.07:38:23.69#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.203.07:38:23.69#ibcon#ireg 7 cls_cnt 0 2006.203.07:38:23.69#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.203.07:38:23.81#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.203.07:38:23.81#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.203.07:38:23.81#ibcon#enter wrdev, iclass 7, count 0 2006.203.07:38:23.81#ibcon#first serial, iclass 7, count 0 2006.203.07:38:23.81#ibcon#enter sib2, iclass 7, count 0 2006.203.07:38:23.81#ibcon#flushed, iclass 7, count 0 2006.203.07:38:23.81#ibcon#about to write, iclass 7, count 0 2006.203.07:38:23.81#ibcon#wrote, iclass 7, count 0 2006.203.07:38:23.81#ibcon#about to read 3, iclass 7, count 0 2006.203.07:38:23.83#ibcon#read 3, iclass 7, count 0 2006.203.07:38:23.83#ibcon#about to read 4, iclass 7, count 0 2006.203.07:38:23.83#ibcon#read 4, iclass 7, count 0 2006.203.07:38:23.83#ibcon#about to read 5, iclass 7, count 0 2006.203.07:38:23.83#ibcon#read 5, iclass 7, count 0 2006.203.07:38:23.83#ibcon#about to read 6, iclass 7, count 0 2006.203.07:38:23.83#ibcon#read 6, iclass 7, count 0 2006.203.07:38:23.83#ibcon#end of sib2, iclass 7, count 0 2006.203.07:38:23.83#ibcon#*mode == 0, iclass 7, count 0 2006.203.07:38:23.83#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.203.07:38:23.83#ibcon#[27=USB\r\n] 2006.203.07:38:23.83#ibcon#*before write, iclass 7, count 0 2006.203.07:38:23.83#ibcon#enter sib2, iclass 7, count 0 2006.203.07:38:23.83#ibcon#flushed, iclass 7, count 0 2006.203.07:38:23.83#ibcon#about to write, iclass 7, count 0 2006.203.07:38:23.83#ibcon#wrote, iclass 7, count 0 2006.203.07:38:23.83#ibcon#about to read 3, iclass 7, count 0 2006.203.07:38:23.86#ibcon#read 3, iclass 7, count 0 2006.203.07:38:23.86#ibcon#about to read 4, iclass 7, count 0 2006.203.07:38:23.86#ibcon#read 4, iclass 7, count 0 2006.203.07:38:23.86#ibcon#about to read 5, iclass 7, count 0 2006.203.07:38:23.86#ibcon#read 5, iclass 7, count 0 2006.203.07:38:23.86#ibcon#about to read 6, iclass 7, count 0 2006.203.07:38:23.86#ibcon#read 6, iclass 7, count 0 2006.203.07:38:23.86#ibcon#end of sib2, iclass 7, count 0 2006.203.07:38:23.86#ibcon#*after write, iclass 7, count 0 2006.203.07:38:23.86#ibcon#*before return 0, iclass 7, count 0 2006.203.07:38:23.86#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.203.07:38:23.86#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.203.07:38:23.86#ibcon#about to clear, iclass 7 cls_cnt 0 2006.203.07:38:23.86#ibcon#cleared, iclass 7 cls_cnt 0 2006.203.07:38:23.86$vc4f8/vabw=wide 2006.203.07:38:23.86#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.203.07:38:23.86#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.203.07:38:23.86#ibcon#ireg 8 cls_cnt 0 2006.203.07:38:23.86#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.203.07:38:23.86#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.203.07:38:23.86#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.203.07:38:23.86#ibcon#enter wrdev, iclass 11, count 0 2006.203.07:38:23.86#ibcon#first serial, iclass 11, count 0 2006.203.07:38:23.86#ibcon#enter sib2, iclass 11, count 0 2006.203.07:38:23.86#ibcon#flushed, iclass 11, count 0 2006.203.07:38:23.86#ibcon#about to write, iclass 11, count 0 2006.203.07:38:23.86#ibcon#wrote, iclass 11, count 0 2006.203.07:38:23.86#ibcon#about to read 3, iclass 11, count 0 2006.203.07:38:23.89#ibcon#read 3, iclass 11, count 0 2006.203.07:38:23.89#ibcon#about to read 4, iclass 11, count 0 2006.203.07:38:23.89#ibcon#read 4, iclass 11, count 0 2006.203.07:38:23.89#ibcon#about to read 5, iclass 11, count 0 2006.203.07:38:23.89#ibcon#read 5, iclass 11, count 0 2006.203.07:38:23.89#ibcon#about to read 6, iclass 11, count 0 2006.203.07:38:23.89#ibcon#read 6, iclass 11, count 0 2006.203.07:38:23.89#ibcon#end of sib2, iclass 11, count 0 2006.203.07:38:23.89#ibcon#*mode == 0, iclass 11, count 0 2006.203.07:38:23.89#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.203.07:38:23.89#ibcon#[25=BW32\r\n] 2006.203.07:38:23.89#ibcon#*before write, iclass 11, count 0 2006.203.07:38:23.89#ibcon#enter sib2, iclass 11, count 0 2006.203.07:38:23.89#ibcon#flushed, iclass 11, count 0 2006.203.07:38:23.89#ibcon#about to write, iclass 11, count 0 2006.203.07:38:23.89#ibcon#wrote, iclass 11, count 0 2006.203.07:38:23.89#ibcon#about to read 3, iclass 11, count 0 2006.203.07:38:23.92#ibcon#read 3, iclass 11, count 0 2006.203.07:38:23.92#ibcon#about to read 4, iclass 11, count 0 2006.203.07:38:23.92#ibcon#read 4, iclass 11, count 0 2006.203.07:38:23.92#ibcon#about to read 5, iclass 11, count 0 2006.203.07:38:23.92#ibcon#read 5, iclass 11, count 0 2006.203.07:38:23.92#ibcon#about to read 6, iclass 11, count 0 2006.203.07:38:23.92#ibcon#read 6, iclass 11, count 0 2006.203.07:38:23.92#ibcon#end of sib2, iclass 11, count 0 2006.203.07:38:23.92#ibcon#*after write, iclass 11, count 0 2006.203.07:38:23.92#ibcon#*before return 0, iclass 11, count 0 2006.203.07:38:23.92#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.203.07:38:23.92#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.203.07:38:23.92#ibcon#about to clear, iclass 11 cls_cnt 0 2006.203.07:38:23.92#ibcon#cleared, iclass 11 cls_cnt 0 2006.203.07:38:23.92$vc4f8/vbbw=wide 2006.203.07:38:23.92#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.203.07:38:23.92#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.203.07:38:23.92#ibcon#ireg 8 cls_cnt 0 2006.203.07:38:23.92#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.203.07:38:23.98#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.203.07:38:23.98#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.203.07:38:23.98#ibcon#enter wrdev, iclass 13, count 0 2006.203.07:38:23.98#ibcon#first serial, iclass 13, count 0 2006.203.07:38:23.98#ibcon#enter sib2, iclass 13, count 0 2006.203.07:38:23.98#ibcon#flushed, iclass 13, count 0 2006.203.07:38:23.98#ibcon#about to write, iclass 13, count 0 2006.203.07:38:23.98#ibcon#wrote, iclass 13, count 0 2006.203.07:38:23.98#ibcon#about to read 3, iclass 13, count 0 2006.203.07:38:24.00#ibcon#read 3, iclass 13, count 0 2006.203.07:38:24.00#ibcon#about to read 4, iclass 13, count 0 2006.203.07:38:24.00#ibcon#read 4, iclass 13, count 0 2006.203.07:38:24.00#ibcon#about to read 5, iclass 13, count 0 2006.203.07:38:24.00#ibcon#read 5, iclass 13, count 0 2006.203.07:38:24.00#ibcon#about to read 6, iclass 13, count 0 2006.203.07:38:24.00#ibcon#read 6, iclass 13, count 0 2006.203.07:38:24.00#ibcon#end of sib2, iclass 13, count 0 2006.203.07:38:24.00#ibcon#*mode == 0, iclass 13, count 0 2006.203.07:38:24.00#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.203.07:38:24.00#ibcon#[27=BW32\r\n] 2006.203.07:38:24.00#ibcon#*before write, iclass 13, count 0 2006.203.07:38:24.00#ibcon#enter sib2, iclass 13, count 0 2006.203.07:38:24.00#ibcon#flushed, iclass 13, count 0 2006.203.07:38:24.00#ibcon#about to write, iclass 13, count 0 2006.203.07:38:24.00#ibcon#wrote, iclass 13, count 0 2006.203.07:38:24.00#ibcon#about to read 3, iclass 13, count 0 2006.203.07:38:24.03#ibcon#read 3, iclass 13, count 0 2006.203.07:38:24.03#ibcon#about to read 4, iclass 13, count 0 2006.203.07:38:24.03#ibcon#read 4, iclass 13, count 0 2006.203.07:38:24.03#ibcon#about to read 5, iclass 13, count 0 2006.203.07:38:24.03#ibcon#read 5, iclass 13, count 0 2006.203.07:38:24.03#ibcon#about to read 6, iclass 13, count 0 2006.203.07:38:24.03#ibcon#read 6, iclass 13, count 0 2006.203.07:38:24.03#ibcon#end of sib2, iclass 13, count 0 2006.203.07:38:24.03#ibcon#*after write, iclass 13, count 0 2006.203.07:38:24.03#ibcon#*before return 0, iclass 13, count 0 2006.203.07:38:24.03#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.203.07:38:24.03#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.203.07:38:24.03#ibcon#about to clear, iclass 13 cls_cnt 0 2006.203.07:38:24.03#ibcon#cleared, iclass 13 cls_cnt 0 2006.203.07:38:24.03$4f8m12a/ifd4f 2006.203.07:38:24.03$ifd4f/lo= 2006.203.07:38:24.03$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.203.07:38:24.03$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.203.07:38:24.03$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.203.07:38:24.03$ifd4f/patch= 2006.203.07:38:24.03$ifd4f/patch=lo1,a1,a2,a3,a4 2006.203.07:38:24.03$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.203.07:38:24.03$ifd4f/patch=lo3,a5,a6,a7,a8 2006.203.07:38:24.03$4f8m12a/"form=m,16.000,1:2 2006.203.07:38:24.03$4f8m12a/"tpicd 2006.203.07:38:24.03$4f8m12a/echo=off 2006.203.07:38:24.03$4f8m12a/xlog=off 2006.203.07:38:24.04:!2006.203.07:38:50 2006.203.07:38:33.13#trakl#Source acquired 2006.203.07:38:35.13#flagr#flagr/antenna,acquired 2006.203.07:38:50.01:preob 2006.203.07:38:51.13/onsource/TRACKING 2006.203.07:38:51.13:!2006.203.07:39:00 2006.203.07:39:00.00:data_valid=on 2006.203.07:39:00.00:midob 2006.203.07:39:00.13/onsource/TRACKING 2006.203.07:39:00.13/wx/23.98,1001.0,97 2006.203.07:39:00.23/cable/+6.4616E-03 2006.203.07:39:01.32/va/01,08,usb,yes,29,31 2006.203.07:39:01.32/va/02,07,usb,yes,29,31 2006.203.07:39:01.32/va/03,08,usb,yes,22,22 2006.203.07:39:01.32/va/04,07,usb,yes,30,32 2006.203.07:39:01.32/va/05,07,usb,yes,32,34 2006.203.07:39:01.32/va/06,06,usb,yes,31,31 2006.203.07:39:01.32/va/07,07,usb,yes,28,27 2006.203.07:39:01.32/va/08,06,usb,yes,34,33 2006.203.07:39:01.55/valo/01,532.99,yes,locked 2006.203.07:39:01.55/valo/02,572.99,yes,locked 2006.203.07:39:01.55/valo/03,672.99,yes,locked 2006.203.07:39:01.55/valo/04,832.99,yes,locked 2006.203.07:39:01.55/valo/05,652.99,yes,locked 2006.203.07:39:01.55/valo/06,772.99,yes,locked 2006.203.07:39:01.55/valo/07,832.99,yes,locked 2006.203.07:39:01.55/valo/08,852.99,yes,locked 2006.203.07:39:02.64/vb/01,04,usb,yes,29,27 2006.203.07:39:02.64/vb/02,04,usb,yes,30,32 2006.203.07:39:02.64/vb/03,04,usb,yes,27,30 2006.203.07:39:02.64/vb/04,04,usb,yes,28,28 2006.203.07:39:02.64/vb/05,03,usb,yes,33,37 2006.203.07:39:02.64/vb/06,04,usb,yes,27,30 2006.203.07:39:02.64/vb/07,04,usb,yes,29,29 2006.203.07:39:02.64/vb/08,04,usb,yes,27,30 2006.203.07:39:02.88/vblo/01,632.99,yes,locked 2006.203.07:39:02.88/vblo/02,640.99,yes,locked 2006.203.07:39:02.88/vblo/03,656.99,yes,locked 2006.203.07:39:02.88/vblo/04,712.99,yes,locked 2006.203.07:39:02.88/vblo/05,744.99,yes,locked 2006.203.07:39:02.88/vblo/06,752.99,yes,locked 2006.203.07:39:02.88/vblo/07,734.99,yes,locked 2006.203.07:39:02.88/vblo/08,744.99,yes,locked 2006.203.07:39:03.03/vabw/8 2006.203.07:39:03.18/vbbw/8 2006.203.07:39:03.27/xfe/off,on,16.5 2006.203.07:39:03.64/ifatt/23,28,28,28 2006.203.07:39:04.07/fmout-gps/S +4.54E-07 2006.203.07:39:04.11:!2006.203.07:40:00 2006.203.07:40:00.01:data_valid=off 2006.203.07:40:00.01:postob 2006.203.07:40:00.14/cable/+6.4580E-03 2006.203.07:40:00.15/wx/23.96,1001.1,97 2006.203.07:40:01.07/fmout-gps/S +4.54E-07 2006.203.07:40:01.08:scan_name=203-0740,k06203,60 2006.203.07:40:01.08:source=0602+673,060752.67,672055.4,2000.0,ccw 2006.203.07:40:01.13#flagr#flagr/antenna,new-source 2006.203.07:40:02.13:checkk5 2006.203.07:40:02.55/chk_autoobs//k5ts1/ autoobs is running! 2006.203.07:40:02.99/chk_autoobs//k5ts2/ autoobs is running! 2006.203.07:40:03.42/chk_autoobs//k5ts3/ autoobs is running! 2006.203.07:40:03.81/chk_autoobs//k5ts4/ autoobs is running! 2006.203.07:40:04.45/chk_obsdata//k5ts1/T2030739??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.07:40:04.91/chk_obsdata//k5ts2/T2030739??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.07:40:05.32/chk_obsdata//k5ts3/T2030739??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.07:40:05.73/chk_obsdata//k5ts4/T2030739??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.07:40:06.49/k5log//k5ts1_log_newline 2006.203.07:40:07.16/k5log//k5ts2_log_newline 2006.203.07:40:07.95/k5log//k5ts3_log_newline 2006.203.07:40:08.92/k5log//k5ts4_log_newline 2006.203.07:40:08.94/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.203.07:40:08.94:4f8m12a=1 2006.203.07:40:08.94$4f8m12a/echo=on 2006.203.07:40:08.94$4f8m12a/pcalon 2006.203.07:40:08.94$pcalon/"no phase cal control is implemented here 2006.203.07:40:08.94$4f8m12a/"tpicd=stop 2006.203.07:40:08.94$4f8m12a/vc4f8 2006.203.07:40:08.94$vc4f8/valo=1,532.99 2006.203.07:40:08.95#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.203.07:40:08.95#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.203.07:40:08.95#ibcon#ireg 17 cls_cnt 0 2006.203.07:40:08.95#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.203.07:40:08.95#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.203.07:40:08.95#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.203.07:40:08.95#ibcon#enter wrdev, iclass 20, count 0 2006.203.07:40:08.95#ibcon#first serial, iclass 20, count 0 2006.203.07:40:08.95#ibcon#enter sib2, iclass 20, count 0 2006.203.07:40:08.95#ibcon#flushed, iclass 20, count 0 2006.203.07:40:08.95#ibcon#about to write, iclass 20, count 0 2006.203.07:40:08.95#ibcon#wrote, iclass 20, count 0 2006.203.07:40:08.95#ibcon#about to read 3, iclass 20, count 0 2006.203.07:40:08.99#ibcon#read 3, iclass 20, count 0 2006.203.07:40:08.99#ibcon#about to read 4, iclass 20, count 0 2006.203.07:40:08.99#ibcon#read 4, iclass 20, count 0 2006.203.07:40:08.99#ibcon#about to read 5, iclass 20, count 0 2006.203.07:40:08.99#ibcon#read 5, iclass 20, count 0 2006.203.07:40:08.99#ibcon#about to read 6, iclass 20, count 0 2006.203.07:40:08.99#ibcon#read 6, iclass 20, count 0 2006.203.07:40:08.99#ibcon#end of sib2, iclass 20, count 0 2006.203.07:40:08.99#ibcon#*mode == 0, iclass 20, count 0 2006.203.07:40:08.99#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.203.07:40:08.99#ibcon#[26=FRQ=01,532.99\r\n] 2006.203.07:40:08.99#ibcon#*before write, iclass 20, count 0 2006.203.07:40:08.99#ibcon#enter sib2, iclass 20, count 0 2006.203.07:40:08.99#ibcon#flushed, iclass 20, count 0 2006.203.07:40:08.99#ibcon#about to write, iclass 20, count 0 2006.203.07:40:08.99#ibcon#wrote, iclass 20, count 0 2006.203.07:40:08.99#ibcon#about to read 3, iclass 20, count 0 2006.203.07:40:09.03#ibcon#read 3, iclass 20, count 0 2006.203.07:40:09.03#ibcon#about to read 4, iclass 20, count 0 2006.203.07:40:09.03#ibcon#read 4, iclass 20, count 0 2006.203.07:40:09.03#ibcon#about to read 5, iclass 20, count 0 2006.203.07:40:09.03#ibcon#read 5, iclass 20, count 0 2006.203.07:40:09.03#ibcon#about to read 6, iclass 20, count 0 2006.203.07:40:09.03#ibcon#read 6, iclass 20, count 0 2006.203.07:40:09.03#ibcon#end of sib2, iclass 20, count 0 2006.203.07:40:09.03#ibcon#*after write, iclass 20, count 0 2006.203.07:40:09.03#ibcon#*before return 0, iclass 20, count 0 2006.203.07:40:09.03#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.203.07:40:09.03#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.203.07:40:09.03#ibcon#about to clear, iclass 20 cls_cnt 0 2006.203.07:40:09.03#ibcon#cleared, iclass 20 cls_cnt 0 2006.203.07:40:09.03$vc4f8/va=1,8 2006.203.07:40:09.03#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.203.07:40:09.03#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.203.07:40:09.03#ibcon#ireg 11 cls_cnt 2 2006.203.07:40:09.03#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.203.07:40:09.03#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.203.07:40:09.03#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.203.07:40:09.03#ibcon#enter wrdev, iclass 22, count 2 2006.203.07:40:09.03#ibcon#first serial, iclass 22, count 2 2006.203.07:40:09.03#ibcon#enter sib2, iclass 22, count 2 2006.203.07:40:09.03#ibcon#flushed, iclass 22, count 2 2006.203.07:40:09.03#ibcon#about to write, iclass 22, count 2 2006.203.07:40:09.03#ibcon#wrote, iclass 22, count 2 2006.203.07:40:09.03#ibcon#about to read 3, iclass 22, count 2 2006.203.07:40:09.05#ibcon#read 3, iclass 22, count 2 2006.203.07:40:09.05#ibcon#about to read 4, iclass 22, count 2 2006.203.07:40:09.05#ibcon#read 4, iclass 22, count 2 2006.203.07:40:09.05#ibcon#about to read 5, iclass 22, count 2 2006.203.07:40:09.05#ibcon#read 5, iclass 22, count 2 2006.203.07:40:09.05#ibcon#about to read 6, iclass 22, count 2 2006.203.07:40:09.05#ibcon#read 6, iclass 22, count 2 2006.203.07:40:09.05#ibcon#end of sib2, iclass 22, count 2 2006.203.07:40:09.05#ibcon#*mode == 0, iclass 22, count 2 2006.203.07:40:09.05#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.203.07:40:09.05#ibcon#[25=AT01-08\r\n] 2006.203.07:40:09.05#ibcon#*before write, iclass 22, count 2 2006.203.07:40:09.05#ibcon#enter sib2, iclass 22, count 2 2006.203.07:40:09.05#ibcon#flushed, iclass 22, count 2 2006.203.07:40:09.05#ibcon#about to write, iclass 22, count 2 2006.203.07:40:09.05#ibcon#wrote, iclass 22, count 2 2006.203.07:40:09.05#ibcon#about to read 3, iclass 22, count 2 2006.203.07:40:09.09#ibcon#read 3, iclass 22, count 2 2006.203.07:40:09.09#ibcon#about to read 4, iclass 22, count 2 2006.203.07:40:09.09#ibcon#read 4, iclass 22, count 2 2006.203.07:40:09.09#ibcon#about to read 5, iclass 22, count 2 2006.203.07:40:09.09#ibcon#read 5, iclass 22, count 2 2006.203.07:40:09.09#ibcon#about to read 6, iclass 22, count 2 2006.203.07:40:09.09#ibcon#read 6, iclass 22, count 2 2006.203.07:40:09.09#ibcon#end of sib2, iclass 22, count 2 2006.203.07:40:09.09#ibcon#*after write, iclass 22, count 2 2006.203.07:40:09.09#ibcon#*before return 0, iclass 22, count 2 2006.203.07:40:09.09#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.203.07:40:09.09#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.203.07:40:09.09#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.203.07:40:09.09#ibcon#ireg 7 cls_cnt 0 2006.203.07:40:09.09#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.203.07:40:09.20#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.203.07:40:09.20#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.203.07:40:09.20#ibcon#enter wrdev, iclass 22, count 0 2006.203.07:40:09.20#ibcon#first serial, iclass 22, count 0 2006.203.07:40:09.20#ibcon#enter sib2, iclass 22, count 0 2006.203.07:40:09.20#ibcon#flushed, iclass 22, count 0 2006.203.07:40:09.20#ibcon#about to write, iclass 22, count 0 2006.203.07:40:09.20#ibcon#wrote, iclass 22, count 0 2006.203.07:40:09.20#ibcon#about to read 3, iclass 22, count 0 2006.203.07:40:09.22#ibcon#read 3, iclass 22, count 0 2006.203.07:40:09.22#ibcon#about to read 4, iclass 22, count 0 2006.203.07:40:09.22#ibcon#read 4, iclass 22, count 0 2006.203.07:40:09.22#ibcon#about to read 5, iclass 22, count 0 2006.203.07:40:09.22#ibcon#read 5, iclass 22, count 0 2006.203.07:40:09.22#ibcon#about to read 6, iclass 22, count 0 2006.203.07:40:09.22#ibcon#read 6, iclass 22, count 0 2006.203.07:40:09.22#ibcon#end of sib2, iclass 22, count 0 2006.203.07:40:09.22#ibcon#*mode == 0, iclass 22, count 0 2006.203.07:40:09.22#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.203.07:40:09.22#ibcon#[25=USB\r\n] 2006.203.07:40:09.22#ibcon#*before write, iclass 22, count 0 2006.203.07:40:09.22#ibcon#enter sib2, iclass 22, count 0 2006.203.07:40:09.22#ibcon#flushed, iclass 22, count 0 2006.203.07:40:09.22#ibcon#about to write, iclass 22, count 0 2006.203.07:40:09.22#ibcon#wrote, iclass 22, count 0 2006.203.07:40:09.22#ibcon#about to read 3, iclass 22, count 0 2006.203.07:40:09.25#ibcon#read 3, iclass 22, count 0 2006.203.07:40:09.25#ibcon#about to read 4, iclass 22, count 0 2006.203.07:40:09.25#ibcon#read 4, iclass 22, count 0 2006.203.07:40:09.25#ibcon#about to read 5, iclass 22, count 0 2006.203.07:40:09.25#ibcon#read 5, iclass 22, count 0 2006.203.07:40:09.25#ibcon#about to read 6, iclass 22, count 0 2006.203.07:40:09.25#ibcon#read 6, iclass 22, count 0 2006.203.07:40:09.25#ibcon#end of sib2, iclass 22, count 0 2006.203.07:40:09.25#ibcon#*after write, iclass 22, count 0 2006.203.07:40:09.25#ibcon#*before return 0, iclass 22, count 0 2006.203.07:40:09.25#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.203.07:40:09.25#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.203.07:40:09.25#ibcon#about to clear, iclass 22 cls_cnt 0 2006.203.07:40:09.25#ibcon#cleared, iclass 22 cls_cnt 0 2006.203.07:40:09.25$vc4f8/valo=2,572.99 2006.203.07:40:09.25#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.203.07:40:09.25#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.203.07:40:09.25#ibcon#ireg 17 cls_cnt 0 2006.203.07:40:09.25#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.203.07:40:09.25#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.203.07:40:09.25#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.203.07:40:09.25#ibcon#enter wrdev, iclass 24, count 0 2006.203.07:40:09.25#ibcon#first serial, iclass 24, count 0 2006.203.07:40:09.25#ibcon#enter sib2, iclass 24, count 0 2006.203.07:40:09.25#ibcon#flushed, iclass 24, count 0 2006.203.07:40:09.25#ibcon#about to write, iclass 24, count 0 2006.203.07:40:09.25#ibcon#wrote, iclass 24, count 0 2006.203.07:40:09.25#ibcon#about to read 3, iclass 24, count 0 2006.203.07:40:09.28#ibcon#read 3, iclass 24, count 0 2006.203.07:40:09.28#ibcon#about to read 4, iclass 24, count 0 2006.203.07:40:09.28#ibcon#read 4, iclass 24, count 0 2006.203.07:40:09.28#ibcon#about to read 5, iclass 24, count 0 2006.203.07:40:09.28#ibcon#read 5, iclass 24, count 0 2006.203.07:40:09.28#ibcon#about to read 6, iclass 24, count 0 2006.203.07:40:09.28#ibcon#read 6, iclass 24, count 0 2006.203.07:40:09.28#ibcon#end of sib2, iclass 24, count 0 2006.203.07:40:09.28#ibcon#*mode == 0, iclass 24, count 0 2006.203.07:40:09.28#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.203.07:40:09.28#ibcon#[26=FRQ=02,572.99\r\n] 2006.203.07:40:09.28#ibcon#*before write, iclass 24, count 0 2006.203.07:40:09.28#ibcon#enter sib2, iclass 24, count 0 2006.203.07:40:09.28#ibcon#flushed, iclass 24, count 0 2006.203.07:40:09.28#ibcon#about to write, iclass 24, count 0 2006.203.07:40:09.28#ibcon#wrote, iclass 24, count 0 2006.203.07:40:09.28#ibcon#about to read 3, iclass 24, count 0 2006.203.07:40:09.32#ibcon#read 3, iclass 24, count 0 2006.203.07:40:09.32#ibcon#about to read 4, iclass 24, count 0 2006.203.07:40:09.32#ibcon#read 4, iclass 24, count 0 2006.203.07:40:09.32#ibcon#about to read 5, iclass 24, count 0 2006.203.07:40:09.32#ibcon#read 5, iclass 24, count 0 2006.203.07:40:09.32#ibcon#about to read 6, iclass 24, count 0 2006.203.07:40:09.32#ibcon#read 6, iclass 24, count 0 2006.203.07:40:09.32#ibcon#end of sib2, iclass 24, count 0 2006.203.07:40:09.32#ibcon#*after write, iclass 24, count 0 2006.203.07:40:09.32#ibcon#*before return 0, iclass 24, count 0 2006.203.07:40:09.32#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.203.07:40:09.32#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.203.07:40:09.32#ibcon#about to clear, iclass 24 cls_cnt 0 2006.203.07:40:09.32#ibcon#cleared, iclass 24 cls_cnt 0 2006.203.07:40:09.32$vc4f8/va=2,7 2006.203.07:40:09.32#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.203.07:40:09.32#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.203.07:40:09.32#ibcon#ireg 11 cls_cnt 2 2006.203.07:40:09.32#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.203.07:40:09.37#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.203.07:40:09.37#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.203.07:40:09.37#ibcon#enter wrdev, iclass 26, count 2 2006.203.07:40:09.37#ibcon#first serial, iclass 26, count 2 2006.203.07:40:09.37#ibcon#enter sib2, iclass 26, count 2 2006.203.07:40:09.37#ibcon#flushed, iclass 26, count 2 2006.203.07:40:09.37#ibcon#about to write, iclass 26, count 2 2006.203.07:40:09.37#ibcon#wrote, iclass 26, count 2 2006.203.07:40:09.37#ibcon#about to read 3, iclass 26, count 2 2006.203.07:40:09.39#ibcon#read 3, iclass 26, count 2 2006.203.07:40:09.39#ibcon#about to read 4, iclass 26, count 2 2006.203.07:40:09.39#ibcon#read 4, iclass 26, count 2 2006.203.07:40:09.39#ibcon#about to read 5, iclass 26, count 2 2006.203.07:40:09.39#ibcon#read 5, iclass 26, count 2 2006.203.07:40:09.39#ibcon#about to read 6, iclass 26, count 2 2006.203.07:40:09.39#ibcon#read 6, iclass 26, count 2 2006.203.07:40:09.39#ibcon#end of sib2, iclass 26, count 2 2006.203.07:40:09.39#ibcon#*mode == 0, iclass 26, count 2 2006.203.07:40:09.39#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.203.07:40:09.39#ibcon#[25=AT02-07\r\n] 2006.203.07:40:09.39#ibcon#*before write, iclass 26, count 2 2006.203.07:40:09.39#ibcon#enter sib2, iclass 26, count 2 2006.203.07:40:09.39#ibcon#flushed, iclass 26, count 2 2006.203.07:40:09.39#ibcon#about to write, iclass 26, count 2 2006.203.07:40:09.39#ibcon#wrote, iclass 26, count 2 2006.203.07:40:09.39#ibcon#about to read 3, iclass 26, count 2 2006.203.07:40:09.42#ibcon#read 3, iclass 26, count 2 2006.203.07:40:09.42#ibcon#about to read 4, iclass 26, count 2 2006.203.07:40:09.42#ibcon#read 4, iclass 26, count 2 2006.203.07:40:09.42#ibcon#about to read 5, iclass 26, count 2 2006.203.07:40:09.42#ibcon#read 5, iclass 26, count 2 2006.203.07:40:09.42#ibcon#about to read 6, iclass 26, count 2 2006.203.07:40:09.42#ibcon#read 6, iclass 26, count 2 2006.203.07:40:09.42#ibcon#end of sib2, iclass 26, count 2 2006.203.07:40:09.42#ibcon#*after write, iclass 26, count 2 2006.203.07:40:09.42#ibcon#*before return 0, iclass 26, count 2 2006.203.07:40:09.42#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.203.07:40:09.42#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.203.07:40:09.42#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.203.07:40:09.42#ibcon#ireg 7 cls_cnt 0 2006.203.07:40:09.42#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.203.07:40:09.54#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.203.07:40:09.54#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.203.07:40:09.54#ibcon#enter wrdev, iclass 26, count 0 2006.203.07:40:09.54#ibcon#first serial, iclass 26, count 0 2006.203.07:40:09.54#ibcon#enter sib2, iclass 26, count 0 2006.203.07:40:09.54#ibcon#flushed, iclass 26, count 0 2006.203.07:40:09.54#ibcon#about to write, iclass 26, count 0 2006.203.07:40:09.54#ibcon#wrote, iclass 26, count 0 2006.203.07:40:09.54#ibcon#about to read 3, iclass 26, count 0 2006.203.07:40:09.56#ibcon#read 3, iclass 26, count 0 2006.203.07:40:09.56#ibcon#about to read 4, iclass 26, count 0 2006.203.07:40:09.56#ibcon#read 4, iclass 26, count 0 2006.203.07:40:09.56#ibcon#about to read 5, iclass 26, count 0 2006.203.07:40:09.56#ibcon#read 5, iclass 26, count 0 2006.203.07:40:09.56#ibcon#about to read 6, iclass 26, count 0 2006.203.07:40:09.56#ibcon#read 6, iclass 26, count 0 2006.203.07:40:09.56#ibcon#end of sib2, iclass 26, count 0 2006.203.07:40:09.56#ibcon#*mode == 0, iclass 26, count 0 2006.203.07:40:09.56#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.203.07:40:09.56#ibcon#[25=USB\r\n] 2006.203.07:40:09.56#ibcon#*before write, iclass 26, count 0 2006.203.07:40:09.56#ibcon#enter sib2, iclass 26, count 0 2006.203.07:40:09.56#ibcon#flushed, iclass 26, count 0 2006.203.07:40:09.56#ibcon#about to write, iclass 26, count 0 2006.203.07:40:09.56#ibcon#wrote, iclass 26, count 0 2006.203.07:40:09.56#ibcon#about to read 3, iclass 26, count 0 2006.203.07:40:09.59#ibcon#read 3, iclass 26, count 0 2006.203.07:40:09.59#ibcon#about to read 4, iclass 26, count 0 2006.203.07:40:09.59#ibcon#read 4, iclass 26, count 0 2006.203.07:40:09.59#ibcon#about to read 5, iclass 26, count 0 2006.203.07:40:09.59#ibcon#read 5, iclass 26, count 0 2006.203.07:40:09.59#ibcon#about to read 6, iclass 26, count 0 2006.203.07:40:09.59#ibcon#read 6, iclass 26, count 0 2006.203.07:40:09.59#ibcon#end of sib2, iclass 26, count 0 2006.203.07:40:09.59#ibcon#*after write, iclass 26, count 0 2006.203.07:40:09.59#ibcon#*before return 0, iclass 26, count 0 2006.203.07:40:09.59#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.203.07:40:09.59#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.203.07:40:09.59#ibcon#about to clear, iclass 26 cls_cnt 0 2006.203.07:40:09.59#ibcon#cleared, iclass 26 cls_cnt 0 2006.203.07:40:09.59$vc4f8/valo=3,672.99 2006.203.07:40:09.59#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.203.07:40:09.59#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.203.07:40:09.59#ibcon#ireg 17 cls_cnt 0 2006.203.07:40:09.59#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.203.07:40:09.59#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.203.07:40:09.59#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.203.07:40:09.59#ibcon#enter wrdev, iclass 28, count 0 2006.203.07:40:09.59#ibcon#first serial, iclass 28, count 0 2006.203.07:40:09.59#ibcon#enter sib2, iclass 28, count 0 2006.203.07:40:09.59#ibcon#flushed, iclass 28, count 0 2006.203.07:40:09.59#ibcon#about to write, iclass 28, count 0 2006.203.07:40:09.59#ibcon#wrote, iclass 28, count 0 2006.203.07:40:09.59#ibcon#about to read 3, iclass 28, count 0 2006.203.07:40:09.62#ibcon#read 3, iclass 28, count 0 2006.203.07:40:09.62#ibcon#about to read 4, iclass 28, count 0 2006.203.07:40:09.62#ibcon#read 4, iclass 28, count 0 2006.203.07:40:09.62#ibcon#about to read 5, iclass 28, count 0 2006.203.07:40:09.62#ibcon#read 5, iclass 28, count 0 2006.203.07:40:09.62#ibcon#about to read 6, iclass 28, count 0 2006.203.07:40:09.62#ibcon#read 6, iclass 28, count 0 2006.203.07:40:09.62#ibcon#end of sib2, iclass 28, count 0 2006.203.07:40:09.62#ibcon#*mode == 0, iclass 28, count 0 2006.203.07:40:09.62#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.203.07:40:09.62#ibcon#[26=FRQ=03,672.99\r\n] 2006.203.07:40:09.62#ibcon#*before write, iclass 28, count 0 2006.203.07:40:09.62#ibcon#enter sib2, iclass 28, count 0 2006.203.07:40:09.62#ibcon#flushed, iclass 28, count 0 2006.203.07:40:09.62#ibcon#about to write, iclass 28, count 0 2006.203.07:40:09.62#ibcon#wrote, iclass 28, count 0 2006.203.07:40:09.62#ibcon#about to read 3, iclass 28, count 0 2006.203.07:40:09.66#ibcon#read 3, iclass 28, count 0 2006.203.07:40:09.66#ibcon#about to read 4, iclass 28, count 0 2006.203.07:40:09.66#ibcon#read 4, iclass 28, count 0 2006.203.07:40:09.66#ibcon#about to read 5, iclass 28, count 0 2006.203.07:40:09.66#ibcon#read 5, iclass 28, count 0 2006.203.07:40:09.66#ibcon#about to read 6, iclass 28, count 0 2006.203.07:40:09.66#ibcon#read 6, iclass 28, count 0 2006.203.07:40:09.66#ibcon#end of sib2, iclass 28, count 0 2006.203.07:40:09.66#ibcon#*after write, iclass 28, count 0 2006.203.07:40:09.66#ibcon#*before return 0, iclass 28, count 0 2006.203.07:40:09.66#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.203.07:40:09.66#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.203.07:40:09.66#ibcon#about to clear, iclass 28 cls_cnt 0 2006.203.07:40:09.66#ibcon#cleared, iclass 28 cls_cnt 0 2006.203.07:40:09.66$vc4f8/va=3,8 2006.203.07:40:09.66#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.203.07:40:09.66#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.203.07:40:09.66#ibcon#ireg 11 cls_cnt 2 2006.203.07:40:09.66#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.203.07:40:09.71#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.203.07:40:09.71#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.203.07:40:09.71#ibcon#enter wrdev, iclass 30, count 2 2006.203.07:40:09.71#ibcon#first serial, iclass 30, count 2 2006.203.07:40:09.71#ibcon#enter sib2, iclass 30, count 2 2006.203.07:40:09.71#ibcon#flushed, iclass 30, count 2 2006.203.07:40:09.71#ibcon#about to write, iclass 30, count 2 2006.203.07:40:09.71#ibcon#wrote, iclass 30, count 2 2006.203.07:40:09.71#ibcon#about to read 3, iclass 30, count 2 2006.203.07:40:09.73#ibcon#read 3, iclass 30, count 2 2006.203.07:40:09.73#ibcon#about to read 4, iclass 30, count 2 2006.203.07:40:09.73#ibcon#read 4, iclass 30, count 2 2006.203.07:40:09.73#ibcon#about to read 5, iclass 30, count 2 2006.203.07:40:09.73#ibcon#read 5, iclass 30, count 2 2006.203.07:40:09.73#ibcon#about to read 6, iclass 30, count 2 2006.203.07:40:09.73#ibcon#read 6, iclass 30, count 2 2006.203.07:40:09.73#ibcon#end of sib2, iclass 30, count 2 2006.203.07:40:09.73#ibcon#*mode == 0, iclass 30, count 2 2006.203.07:40:09.73#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.203.07:40:09.73#ibcon#[25=AT03-08\r\n] 2006.203.07:40:09.73#ibcon#*before write, iclass 30, count 2 2006.203.07:40:09.73#ibcon#enter sib2, iclass 30, count 2 2006.203.07:40:09.73#ibcon#flushed, iclass 30, count 2 2006.203.07:40:09.73#ibcon#about to write, iclass 30, count 2 2006.203.07:40:09.73#ibcon#wrote, iclass 30, count 2 2006.203.07:40:09.73#ibcon#about to read 3, iclass 30, count 2 2006.203.07:40:09.76#ibcon#read 3, iclass 30, count 2 2006.203.07:40:09.76#ibcon#about to read 4, iclass 30, count 2 2006.203.07:40:09.76#ibcon#read 4, iclass 30, count 2 2006.203.07:40:09.76#ibcon#about to read 5, iclass 30, count 2 2006.203.07:40:09.76#ibcon#read 5, iclass 30, count 2 2006.203.07:40:09.76#ibcon#about to read 6, iclass 30, count 2 2006.203.07:40:09.76#ibcon#read 6, iclass 30, count 2 2006.203.07:40:09.76#ibcon#end of sib2, iclass 30, count 2 2006.203.07:40:09.76#ibcon#*after write, iclass 30, count 2 2006.203.07:40:09.76#ibcon#*before return 0, iclass 30, count 2 2006.203.07:40:09.76#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.203.07:40:09.76#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.203.07:40:09.76#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.203.07:40:09.76#ibcon#ireg 7 cls_cnt 0 2006.203.07:40:09.76#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.203.07:40:09.88#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.203.07:40:09.88#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.203.07:40:09.88#ibcon#enter wrdev, iclass 30, count 0 2006.203.07:40:09.88#ibcon#first serial, iclass 30, count 0 2006.203.07:40:09.88#ibcon#enter sib2, iclass 30, count 0 2006.203.07:40:09.88#ibcon#flushed, iclass 30, count 0 2006.203.07:40:09.88#ibcon#about to write, iclass 30, count 0 2006.203.07:40:09.88#ibcon#wrote, iclass 30, count 0 2006.203.07:40:09.88#ibcon#about to read 3, iclass 30, count 0 2006.203.07:40:09.90#ibcon#read 3, iclass 30, count 0 2006.203.07:40:09.90#ibcon#about to read 4, iclass 30, count 0 2006.203.07:40:09.90#ibcon#read 4, iclass 30, count 0 2006.203.07:40:09.90#ibcon#about to read 5, iclass 30, count 0 2006.203.07:40:09.90#ibcon#read 5, iclass 30, count 0 2006.203.07:40:09.90#ibcon#about to read 6, iclass 30, count 0 2006.203.07:40:09.90#ibcon#read 6, iclass 30, count 0 2006.203.07:40:09.90#ibcon#end of sib2, iclass 30, count 0 2006.203.07:40:09.90#ibcon#*mode == 0, iclass 30, count 0 2006.203.07:40:09.90#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.203.07:40:09.90#ibcon#[25=USB\r\n] 2006.203.07:40:09.90#ibcon#*before write, iclass 30, count 0 2006.203.07:40:09.90#ibcon#enter sib2, iclass 30, count 0 2006.203.07:40:09.90#ibcon#flushed, iclass 30, count 0 2006.203.07:40:09.90#ibcon#about to write, iclass 30, count 0 2006.203.07:40:09.90#ibcon#wrote, iclass 30, count 0 2006.203.07:40:09.90#ibcon#about to read 3, iclass 30, count 0 2006.203.07:40:09.93#ibcon#read 3, iclass 30, count 0 2006.203.07:40:09.93#ibcon#about to read 4, iclass 30, count 0 2006.203.07:40:09.93#ibcon#read 4, iclass 30, count 0 2006.203.07:40:09.93#ibcon#about to read 5, iclass 30, count 0 2006.203.07:40:09.93#ibcon#read 5, iclass 30, count 0 2006.203.07:40:09.93#ibcon#about to read 6, iclass 30, count 0 2006.203.07:40:09.93#ibcon#read 6, iclass 30, count 0 2006.203.07:40:09.93#ibcon#end of sib2, iclass 30, count 0 2006.203.07:40:09.93#ibcon#*after write, iclass 30, count 0 2006.203.07:40:09.93#ibcon#*before return 0, iclass 30, count 0 2006.203.07:40:09.93#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.203.07:40:09.93#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.203.07:40:09.93#ibcon#about to clear, iclass 30 cls_cnt 0 2006.203.07:40:09.93#ibcon#cleared, iclass 30 cls_cnt 0 2006.203.07:40:09.93$vc4f8/valo=4,832.99 2006.203.07:40:09.93#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.203.07:40:09.93#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.203.07:40:09.93#ibcon#ireg 17 cls_cnt 0 2006.203.07:40:09.93#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.203.07:40:09.93#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.203.07:40:09.93#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.203.07:40:09.93#ibcon#enter wrdev, iclass 32, count 0 2006.203.07:40:09.93#ibcon#first serial, iclass 32, count 0 2006.203.07:40:09.93#ibcon#enter sib2, iclass 32, count 0 2006.203.07:40:09.93#ibcon#flushed, iclass 32, count 0 2006.203.07:40:09.93#ibcon#about to write, iclass 32, count 0 2006.203.07:40:09.93#ibcon#wrote, iclass 32, count 0 2006.203.07:40:09.93#ibcon#about to read 3, iclass 32, count 0 2006.203.07:40:09.96#ibcon#read 3, iclass 32, count 0 2006.203.07:40:09.96#ibcon#about to read 4, iclass 32, count 0 2006.203.07:40:09.96#ibcon#read 4, iclass 32, count 0 2006.203.07:40:09.96#ibcon#about to read 5, iclass 32, count 0 2006.203.07:40:09.96#ibcon#read 5, iclass 32, count 0 2006.203.07:40:09.96#ibcon#about to read 6, iclass 32, count 0 2006.203.07:40:09.96#ibcon#read 6, iclass 32, count 0 2006.203.07:40:09.96#ibcon#end of sib2, iclass 32, count 0 2006.203.07:40:09.96#ibcon#*mode == 0, iclass 32, count 0 2006.203.07:40:09.96#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.203.07:40:09.96#ibcon#[26=FRQ=04,832.99\r\n] 2006.203.07:40:09.96#ibcon#*before write, iclass 32, count 0 2006.203.07:40:09.96#ibcon#enter sib2, iclass 32, count 0 2006.203.07:40:09.96#ibcon#flushed, iclass 32, count 0 2006.203.07:40:09.96#ibcon#about to write, iclass 32, count 0 2006.203.07:40:09.96#ibcon#wrote, iclass 32, count 0 2006.203.07:40:09.96#ibcon#about to read 3, iclass 32, count 0 2006.203.07:40:10.00#ibcon#read 3, iclass 32, count 0 2006.203.07:40:10.00#ibcon#about to read 4, iclass 32, count 0 2006.203.07:40:10.00#ibcon#read 4, iclass 32, count 0 2006.203.07:40:10.00#ibcon#about to read 5, iclass 32, count 0 2006.203.07:40:10.00#ibcon#read 5, iclass 32, count 0 2006.203.07:40:10.00#ibcon#about to read 6, iclass 32, count 0 2006.203.07:40:10.00#ibcon#read 6, iclass 32, count 0 2006.203.07:40:10.00#ibcon#end of sib2, iclass 32, count 0 2006.203.07:40:10.00#ibcon#*after write, iclass 32, count 0 2006.203.07:40:10.00#ibcon#*before return 0, iclass 32, count 0 2006.203.07:40:10.00#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.203.07:40:10.00#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.203.07:40:10.00#ibcon#about to clear, iclass 32 cls_cnt 0 2006.203.07:40:10.00#ibcon#cleared, iclass 32 cls_cnt 0 2006.203.07:40:10.00$vc4f8/va=4,7 2006.203.07:40:10.00#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.203.07:40:10.00#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.203.07:40:10.00#ibcon#ireg 11 cls_cnt 2 2006.203.07:40:10.00#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.203.07:40:10.05#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.203.07:40:10.05#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.203.07:40:10.05#ibcon#enter wrdev, iclass 34, count 2 2006.203.07:40:10.05#ibcon#first serial, iclass 34, count 2 2006.203.07:40:10.05#ibcon#enter sib2, iclass 34, count 2 2006.203.07:40:10.05#ibcon#flushed, iclass 34, count 2 2006.203.07:40:10.05#ibcon#about to write, iclass 34, count 2 2006.203.07:40:10.05#ibcon#wrote, iclass 34, count 2 2006.203.07:40:10.05#ibcon#about to read 3, iclass 34, count 2 2006.203.07:40:10.07#ibcon#read 3, iclass 34, count 2 2006.203.07:40:10.07#ibcon#about to read 4, iclass 34, count 2 2006.203.07:40:10.07#ibcon#read 4, iclass 34, count 2 2006.203.07:40:10.07#ibcon#about to read 5, iclass 34, count 2 2006.203.07:40:10.07#ibcon#read 5, iclass 34, count 2 2006.203.07:40:10.07#ibcon#about to read 6, iclass 34, count 2 2006.203.07:40:10.07#ibcon#read 6, iclass 34, count 2 2006.203.07:40:10.07#ibcon#end of sib2, iclass 34, count 2 2006.203.07:40:10.07#ibcon#*mode == 0, iclass 34, count 2 2006.203.07:40:10.07#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.203.07:40:10.07#ibcon#[25=AT04-07\r\n] 2006.203.07:40:10.07#ibcon#*before write, iclass 34, count 2 2006.203.07:40:10.07#ibcon#enter sib2, iclass 34, count 2 2006.203.07:40:10.07#ibcon#flushed, iclass 34, count 2 2006.203.07:40:10.07#ibcon#about to write, iclass 34, count 2 2006.203.07:40:10.07#ibcon#wrote, iclass 34, count 2 2006.203.07:40:10.07#ibcon#about to read 3, iclass 34, count 2 2006.203.07:40:10.10#ibcon#read 3, iclass 34, count 2 2006.203.07:40:10.10#ibcon#about to read 4, iclass 34, count 2 2006.203.07:40:10.10#ibcon#read 4, iclass 34, count 2 2006.203.07:40:10.10#ibcon#about to read 5, iclass 34, count 2 2006.203.07:40:10.10#ibcon#read 5, iclass 34, count 2 2006.203.07:40:10.10#ibcon#about to read 6, iclass 34, count 2 2006.203.07:40:10.10#ibcon#read 6, iclass 34, count 2 2006.203.07:40:10.10#ibcon#end of sib2, iclass 34, count 2 2006.203.07:40:10.10#ibcon#*after write, iclass 34, count 2 2006.203.07:40:10.10#ibcon#*before return 0, iclass 34, count 2 2006.203.07:40:10.10#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.203.07:40:10.10#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.203.07:40:10.10#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.203.07:40:10.10#ibcon#ireg 7 cls_cnt 0 2006.203.07:40:10.10#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.203.07:40:10.22#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.203.07:40:10.22#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.203.07:40:10.22#ibcon#enter wrdev, iclass 34, count 0 2006.203.07:40:10.22#ibcon#first serial, iclass 34, count 0 2006.203.07:40:10.22#ibcon#enter sib2, iclass 34, count 0 2006.203.07:40:10.22#ibcon#flushed, iclass 34, count 0 2006.203.07:40:10.22#ibcon#about to write, iclass 34, count 0 2006.203.07:40:10.22#ibcon#wrote, iclass 34, count 0 2006.203.07:40:10.22#ibcon#about to read 3, iclass 34, count 0 2006.203.07:40:10.24#ibcon#read 3, iclass 34, count 0 2006.203.07:40:10.24#ibcon#about to read 4, iclass 34, count 0 2006.203.07:40:10.24#ibcon#read 4, iclass 34, count 0 2006.203.07:40:10.24#ibcon#about to read 5, iclass 34, count 0 2006.203.07:40:10.24#ibcon#read 5, iclass 34, count 0 2006.203.07:40:10.24#ibcon#about to read 6, iclass 34, count 0 2006.203.07:40:10.24#ibcon#read 6, iclass 34, count 0 2006.203.07:40:10.24#ibcon#end of sib2, iclass 34, count 0 2006.203.07:40:10.24#ibcon#*mode == 0, iclass 34, count 0 2006.203.07:40:10.24#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.203.07:40:10.24#ibcon#[25=USB\r\n] 2006.203.07:40:10.24#ibcon#*before write, iclass 34, count 0 2006.203.07:40:10.24#ibcon#enter sib2, iclass 34, count 0 2006.203.07:40:10.24#ibcon#flushed, iclass 34, count 0 2006.203.07:40:10.24#ibcon#about to write, iclass 34, count 0 2006.203.07:40:10.24#ibcon#wrote, iclass 34, count 0 2006.203.07:40:10.24#ibcon#about to read 3, iclass 34, count 0 2006.203.07:40:10.27#ibcon#read 3, iclass 34, count 0 2006.203.07:40:10.27#ibcon#about to read 4, iclass 34, count 0 2006.203.07:40:10.27#ibcon#read 4, iclass 34, count 0 2006.203.07:40:10.27#ibcon#about to read 5, iclass 34, count 0 2006.203.07:40:10.27#ibcon#read 5, iclass 34, count 0 2006.203.07:40:10.27#ibcon#about to read 6, iclass 34, count 0 2006.203.07:40:10.27#ibcon#read 6, iclass 34, count 0 2006.203.07:40:10.27#ibcon#end of sib2, iclass 34, count 0 2006.203.07:40:10.27#ibcon#*after write, iclass 34, count 0 2006.203.07:40:10.27#ibcon#*before return 0, iclass 34, count 0 2006.203.07:40:10.27#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.203.07:40:10.27#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.203.07:40:10.27#ibcon#about to clear, iclass 34 cls_cnt 0 2006.203.07:40:10.27#ibcon#cleared, iclass 34 cls_cnt 0 2006.203.07:40:10.27$vc4f8/valo=5,652.99 2006.203.07:40:10.27#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.203.07:40:10.27#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.203.07:40:10.27#ibcon#ireg 17 cls_cnt 0 2006.203.07:40:10.27#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.203.07:40:10.27#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.203.07:40:10.27#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.203.07:40:10.27#ibcon#enter wrdev, iclass 36, count 0 2006.203.07:40:10.27#ibcon#first serial, iclass 36, count 0 2006.203.07:40:10.27#ibcon#enter sib2, iclass 36, count 0 2006.203.07:40:10.27#ibcon#flushed, iclass 36, count 0 2006.203.07:40:10.27#ibcon#about to write, iclass 36, count 0 2006.203.07:40:10.27#ibcon#wrote, iclass 36, count 0 2006.203.07:40:10.27#ibcon#about to read 3, iclass 36, count 0 2006.203.07:40:10.30#ibcon#read 3, iclass 36, count 0 2006.203.07:40:10.30#ibcon#about to read 4, iclass 36, count 0 2006.203.07:40:10.30#ibcon#read 4, iclass 36, count 0 2006.203.07:40:10.30#ibcon#about to read 5, iclass 36, count 0 2006.203.07:40:10.30#ibcon#read 5, iclass 36, count 0 2006.203.07:40:10.30#ibcon#about to read 6, iclass 36, count 0 2006.203.07:40:10.30#ibcon#read 6, iclass 36, count 0 2006.203.07:40:10.30#ibcon#end of sib2, iclass 36, count 0 2006.203.07:40:10.30#ibcon#*mode == 0, iclass 36, count 0 2006.203.07:40:10.30#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.203.07:40:10.30#ibcon#[26=FRQ=05,652.99\r\n] 2006.203.07:40:10.30#ibcon#*before write, iclass 36, count 0 2006.203.07:40:10.30#ibcon#enter sib2, iclass 36, count 0 2006.203.07:40:10.30#ibcon#flushed, iclass 36, count 0 2006.203.07:40:10.30#ibcon#about to write, iclass 36, count 0 2006.203.07:40:10.30#ibcon#wrote, iclass 36, count 0 2006.203.07:40:10.30#ibcon#about to read 3, iclass 36, count 0 2006.203.07:40:10.34#ibcon#read 3, iclass 36, count 0 2006.203.07:40:10.34#ibcon#about to read 4, iclass 36, count 0 2006.203.07:40:10.34#ibcon#read 4, iclass 36, count 0 2006.203.07:40:10.34#ibcon#about to read 5, iclass 36, count 0 2006.203.07:40:10.34#ibcon#read 5, iclass 36, count 0 2006.203.07:40:10.34#ibcon#about to read 6, iclass 36, count 0 2006.203.07:40:10.34#ibcon#read 6, iclass 36, count 0 2006.203.07:40:10.34#ibcon#end of sib2, iclass 36, count 0 2006.203.07:40:10.34#ibcon#*after write, iclass 36, count 0 2006.203.07:40:10.34#ibcon#*before return 0, iclass 36, count 0 2006.203.07:40:10.34#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.203.07:40:10.34#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.203.07:40:10.34#ibcon#about to clear, iclass 36 cls_cnt 0 2006.203.07:40:10.34#ibcon#cleared, iclass 36 cls_cnt 0 2006.203.07:40:10.34$vc4f8/va=5,7 2006.203.07:40:10.34#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.203.07:40:10.34#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.203.07:40:10.34#ibcon#ireg 11 cls_cnt 2 2006.203.07:40:10.34#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.203.07:40:10.39#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.203.07:40:10.39#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.203.07:40:10.39#ibcon#enter wrdev, iclass 38, count 2 2006.203.07:40:10.39#ibcon#first serial, iclass 38, count 2 2006.203.07:40:10.39#ibcon#enter sib2, iclass 38, count 2 2006.203.07:40:10.39#ibcon#flushed, iclass 38, count 2 2006.203.07:40:10.39#ibcon#about to write, iclass 38, count 2 2006.203.07:40:10.39#ibcon#wrote, iclass 38, count 2 2006.203.07:40:10.39#ibcon#about to read 3, iclass 38, count 2 2006.203.07:40:10.41#ibcon#read 3, iclass 38, count 2 2006.203.07:40:10.41#ibcon#about to read 4, iclass 38, count 2 2006.203.07:40:10.41#ibcon#read 4, iclass 38, count 2 2006.203.07:40:10.41#ibcon#about to read 5, iclass 38, count 2 2006.203.07:40:10.41#ibcon#read 5, iclass 38, count 2 2006.203.07:40:10.41#ibcon#about to read 6, iclass 38, count 2 2006.203.07:40:10.41#ibcon#read 6, iclass 38, count 2 2006.203.07:40:10.41#ibcon#end of sib2, iclass 38, count 2 2006.203.07:40:10.41#ibcon#*mode == 0, iclass 38, count 2 2006.203.07:40:10.41#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.203.07:40:10.41#ibcon#[25=AT05-07\r\n] 2006.203.07:40:10.41#ibcon#*before write, iclass 38, count 2 2006.203.07:40:10.41#ibcon#enter sib2, iclass 38, count 2 2006.203.07:40:10.41#ibcon#flushed, iclass 38, count 2 2006.203.07:40:10.41#ibcon#about to write, iclass 38, count 2 2006.203.07:40:10.41#ibcon#wrote, iclass 38, count 2 2006.203.07:40:10.41#ibcon#about to read 3, iclass 38, count 2 2006.203.07:40:10.44#ibcon#read 3, iclass 38, count 2 2006.203.07:40:10.44#ibcon#about to read 4, iclass 38, count 2 2006.203.07:40:10.44#ibcon#read 4, iclass 38, count 2 2006.203.07:40:10.44#ibcon#about to read 5, iclass 38, count 2 2006.203.07:40:10.44#ibcon#read 5, iclass 38, count 2 2006.203.07:40:10.44#ibcon#about to read 6, iclass 38, count 2 2006.203.07:40:10.44#ibcon#read 6, iclass 38, count 2 2006.203.07:40:10.44#ibcon#end of sib2, iclass 38, count 2 2006.203.07:40:10.44#ibcon#*after write, iclass 38, count 2 2006.203.07:40:10.44#ibcon#*before return 0, iclass 38, count 2 2006.203.07:40:10.44#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.203.07:40:10.44#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.203.07:40:10.44#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.203.07:40:10.44#ibcon#ireg 7 cls_cnt 0 2006.203.07:40:10.44#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.203.07:40:10.56#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.203.07:40:10.56#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.203.07:40:10.56#ibcon#enter wrdev, iclass 38, count 0 2006.203.07:40:10.56#ibcon#first serial, iclass 38, count 0 2006.203.07:40:10.56#ibcon#enter sib2, iclass 38, count 0 2006.203.07:40:10.56#ibcon#flushed, iclass 38, count 0 2006.203.07:40:10.56#ibcon#about to write, iclass 38, count 0 2006.203.07:40:10.56#ibcon#wrote, iclass 38, count 0 2006.203.07:40:10.56#ibcon#about to read 3, iclass 38, count 0 2006.203.07:40:10.58#ibcon#read 3, iclass 38, count 0 2006.203.07:40:10.58#ibcon#about to read 4, iclass 38, count 0 2006.203.07:40:10.58#ibcon#read 4, iclass 38, count 0 2006.203.07:40:10.58#ibcon#about to read 5, iclass 38, count 0 2006.203.07:40:10.58#ibcon#read 5, iclass 38, count 0 2006.203.07:40:10.58#ibcon#about to read 6, iclass 38, count 0 2006.203.07:40:10.58#ibcon#read 6, iclass 38, count 0 2006.203.07:40:10.58#ibcon#end of sib2, iclass 38, count 0 2006.203.07:40:10.58#ibcon#*mode == 0, iclass 38, count 0 2006.203.07:40:10.58#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.203.07:40:10.58#ibcon#[25=USB\r\n] 2006.203.07:40:10.58#ibcon#*before write, iclass 38, count 0 2006.203.07:40:10.58#ibcon#enter sib2, iclass 38, count 0 2006.203.07:40:10.58#ibcon#flushed, iclass 38, count 0 2006.203.07:40:10.58#ibcon#about to write, iclass 38, count 0 2006.203.07:40:10.58#ibcon#wrote, iclass 38, count 0 2006.203.07:40:10.58#ibcon#about to read 3, iclass 38, count 0 2006.203.07:40:10.61#ibcon#read 3, iclass 38, count 0 2006.203.07:40:10.61#ibcon#about to read 4, iclass 38, count 0 2006.203.07:40:10.61#ibcon#read 4, iclass 38, count 0 2006.203.07:40:10.61#ibcon#about to read 5, iclass 38, count 0 2006.203.07:40:10.61#ibcon#read 5, iclass 38, count 0 2006.203.07:40:10.61#ibcon#about to read 6, iclass 38, count 0 2006.203.07:40:10.61#ibcon#read 6, iclass 38, count 0 2006.203.07:40:10.61#ibcon#end of sib2, iclass 38, count 0 2006.203.07:40:10.61#ibcon#*after write, iclass 38, count 0 2006.203.07:40:10.61#ibcon#*before return 0, iclass 38, count 0 2006.203.07:40:10.61#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.203.07:40:10.61#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.203.07:40:10.61#ibcon#about to clear, iclass 38 cls_cnt 0 2006.203.07:40:10.61#ibcon#cleared, iclass 38 cls_cnt 0 2006.203.07:40:10.61$vc4f8/valo=6,772.99 2006.203.07:40:10.61#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.203.07:40:10.61#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.203.07:40:10.61#ibcon#ireg 17 cls_cnt 0 2006.203.07:40:10.61#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.203.07:40:10.61#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.203.07:40:10.61#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.203.07:40:10.61#ibcon#enter wrdev, iclass 40, count 0 2006.203.07:40:10.61#ibcon#first serial, iclass 40, count 0 2006.203.07:40:10.61#ibcon#enter sib2, iclass 40, count 0 2006.203.07:40:10.61#ibcon#flushed, iclass 40, count 0 2006.203.07:40:10.61#ibcon#about to write, iclass 40, count 0 2006.203.07:40:10.61#ibcon#wrote, iclass 40, count 0 2006.203.07:40:10.61#ibcon#about to read 3, iclass 40, count 0 2006.203.07:40:10.63#ibcon#read 3, iclass 40, count 0 2006.203.07:40:10.63#ibcon#about to read 4, iclass 40, count 0 2006.203.07:40:10.63#ibcon#read 4, iclass 40, count 0 2006.203.07:40:10.63#ibcon#about to read 5, iclass 40, count 0 2006.203.07:40:10.63#ibcon#read 5, iclass 40, count 0 2006.203.07:40:10.63#ibcon#about to read 6, iclass 40, count 0 2006.203.07:40:10.63#ibcon#read 6, iclass 40, count 0 2006.203.07:40:10.63#ibcon#end of sib2, iclass 40, count 0 2006.203.07:40:10.63#ibcon#*mode == 0, iclass 40, count 0 2006.203.07:40:10.63#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.203.07:40:10.63#ibcon#[26=FRQ=06,772.99\r\n] 2006.203.07:40:10.63#ibcon#*before write, iclass 40, count 0 2006.203.07:40:10.63#ibcon#enter sib2, iclass 40, count 0 2006.203.07:40:10.63#ibcon#flushed, iclass 40, count 0 2006.203.07:40:10.63#ibcon#about to write, iclass 40, count 0 2006.203.07:40:10.63#ibcon#wrote, iclass 40, count 0 2006.203.07:40:10.63#ibcon#about to read 3, iclass 40, count 0 2006.203.07:40:10.67#ibcon#read 3, iclass 40, count 0 2006.203.07:40:10.67#ibcon#about to read 4, iclass 40, count 0 2006.203.07:40:10.67#ibcon#read 4, iclass 40, count 0 2006.203.07:40:10.67#ibcon#about to read 5, iclass 40, count 0 2006.203.07:40:10.67#ibcon#read 5, iclass 40, count 0 2006.203.07:40:10.67#ibcon#about to read 6, iclass 40, count 0 2006.203.07:40:10.67#ibcon#read 6, iclass 40, count 0 2006.203.07:40:10.67#ibcon#end of sib2, iclass 40, count 0 2006.203.07:40:10.67#ibcon#*after write, iclass 40, count 0 2006.203.07:40:10.67#ibcon#*before return 0, iclass 40, count 0 2006.203.07:40:10.67#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.203.07:40:10.67#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.203.07:40:10.67#ibcon#about to clear, iclass 40 cls_cnt 0 2006.203.07:40:10.67#ibcon#cleared, iclass 40 cls_cnt 0 2006.203.07:40:10.67$vc4f8/va=6,6 2006.203.07:40:10.67#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.203.07:40:10.67#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.203.07:40:10.67#ibcon#ireg 11 cls_cnt 2 2006.203.07:40:10.67#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.203.07:40:10.73#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.203.07:40:10.73#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.203.07:40:10.73#ibcon#enter wrdev, iclass 4, count 2 2006.203.07:40:10.73#ibcon#first serial, iclass 4, count 2 2006.203.07:40:10.73#ibcon#enter sib2, iclass 4, count 2 2006.203.07:40:10.73#ibcon#flushed, iclass 4, count 2 2006.203.07:40:10.73#ibcon#about to write, iclass 4, count 2 2006.203.07:40:10.73#ibcon#wrote, iclass 4, count 2 2006.203.07:40:10.73#ibcon#about to read 3, iclass 4, count 2 2006.203.07:40:10.75#ibcon#read 3, iclass 4, count 2 2006.203.07:40:10.75#ibcon#about to read 4, iclass 4, count 2 2006.203.07:40:10.75#ibcon#read 4, iclass 4, count 2 2006.203.07:40:10.75#ibcon#about to read 5, iclass 4, count 2 2006.203.07:40:10.75#ibcon#read 5, iclass 4, count 2 2006.203.07:40:10.75#ibcon#about to read 6, iclass 4, count 2 2006.203.07:40:10.75#ibcon#read 6, iclass 4, count 2 2006.203.07:40:10.75#ibcon#end of sib2, iclass 4, count 2 2006.203.07:40:10.75#ibcon#*mode == 0, iclass 4, count 2 2006.203.07:40:10.75#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.203.07:40:10.75#ibcon#[25=AT06-06\r\n] 2006.203.07:40:10.75#ibcon#*before write, iclass 4, count 2 2006.203.07:40:10.75#ibcon#enter sib2, iclass 4, count 2 2006.203.07:40:10.75#ibcon#flushed, iclass 4, count 2 2006.203.07:40:10.75#ibcon#about to write, iclass 4, count 2 2006.203.07:40:10.75#ibcon#wrote, iclass 4, count 2 2006.203.07:40:10.75#ibcon#about to read 3, iclass 4, count 2 2006.203.07:40:10.78#ibcon#read 3, iclass 4, count 2 2006.203.07:40:10.78#ibcon#about to read 4, iclass 4, count 2 2006.203.07:40:10.78#ibcon#read 4, iclass 4, count 2 2006.203.07:40:10.78#ibcon#about to read 5, iclass 4, count 2 2006.203.07:40:10.78#ibcon#read 5, iclass 4, count 2 2006.203.07:40:10.78#ibcon#about to read 6, iclass 4, count 2 2006.203.07:40:10.78#ibcon#read 6, iclass 4, count 2 2006.203.07:40:10.78#ibcon#end of sib2, iclass 4, count 2 2006.203.07:40:10.78#ibcon#*after write, iclass 4, count 2 2006.203.07:40:10.78#ibcon#*before return 0, iclass 4, count 2 2006.203.07:40:10.78#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.203.07:40:10.78#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.203.07:40:10.78#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.203.07:40:10.78#ibcon#ireg 7 cls_cnt 0 2006.203.07:40:10.78#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.203.07:40:10.90#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.203.07:40:10.90#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.203.07:40:10.90#ibcon#enter wrdev, iclass 4, count 0 2006.203.07:40:10.90#ibcon#first serial, iclass 4, count 0 2006.203.07:40:10.90#ibcon#enter sib2, iclass 4, count 0 2006.203.07:40:10.90#ibcon#flushed, iclass 4, count 0 2006.203.07:40:10.90#ibcon#about to write, iclass 4, count 0 2006.203.07:40:10.90#ibcon#wrote, iclass 4, count 0 2006.203.07:40:10.90#ibcon#about to read 3, iclass 4, count 0 2006.203.07:40:10.92#ibcon#read 3, iclass 4, count 0 2006.203.07:40:10.92#ibcon#about to read 4, iclass 4, count 0 2006.203.07:40:10.92#ibcon#read 4, iclass 4, count 0 2006.203.07:40:10.92#ibcon#about to read 5, iclass 4, count 0 2006.203.07:40:10.92#ibcon#read 5, iclass 4, count 0 2006.203.07:40:10.92#ibcon#about to read 6, iclass 4, count 0 2006.203.07:40:10.92#ibcon#read 6, iclass 4, count 0 2006.203.07:40:10.92#ibcon#end of sib2, iclass 4, count 0 2006.203.07:40:10.92#ibcon#*mode == 0, iclass 4, count 0 2006.203.07:40:10.92#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.203.07:40:10.92#ibcon#[25=USB\r\n] 2006.203.07:40:10.92#ibcon#*before write, iclass 4, count 0 2006.203.07:40:10.92#ibcon#enter sib2, iclass 4, count 0 2006.203.07:40:10.92#ibcon#flushed, iclass 4, count 0 2006.203.07:40:10.92#ibcon#about to write, iclass 4, count 0 2006.203.07:40:10.92#ibcon#wrote, iclass 4, count 0 2006.203.07:40:10.92#ibcon#about to read 3, iclass 4, count 0 2006.203.07:40:10.95#ibcon#read 3, iclass 4, count 0 2006.203.07:40:10.95#ibcon#about to read 4, iclass 4, count 0 2006.203.07:40:10.95#ibcon#read 4, iclass 4, count 0 2006.203.07:40:10.95#ibcon#about to read 5, iclass 4, count 0 2006.203.07:40:10.95#ibcon#read 5, iclass 4, count 0 2006.203.07:40:10.95#ibcon#about to read 6, iclass 4, count 0 2006.203.07:40:10.95#ibcon#read 6, iclass 4, count 0 2006.203.07:40:10.95#ibcon#end of sib2, iclass 4, count 0 2006.203.07:40:10.95#ibcon#*after write, iclass 4, count 0 2006.203.07:40:10.95#ibcon#*before return 0, iclass 4, count 0 2006.203.07:40:10.95#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.203.07:40:10.95#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.203.07:40:10.95#ibcon#about to clear, iclass 4 cls_cnt 0 2006.203.07:40:10.95#ibcon#cleared, iclass 4 cls_cnt 0 2006.203.07:40:10.95$vc4f8/valo=7,832.99 2006.203.07:40:10.95#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.203.07:40:10.95#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.203.07:40:10.95#ibcon#ireg 17 cls_cnt 0 2006.203.07:40:10.95#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.203.07:40:10.95#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.203.07:40:10.95#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.203.07:40:10.95#ibcon#enter wrdev, iclass 6, count 0 2006.203.07:40:10.95#ibcon#first serial, iclass 6, count 0 2006.203.07:40:10.95#ibcon#enter sib2, iclass 6, count 0 2006.203.07:40:10.95#ibcon#flushed, iclass 6, count 0 2006.203.07:40:10.95#ibcon#about to write, iclass 6, count 0 2006.203.07:40:10.95#ibcon#wrote, iclass 6, count 0 2006.203.07:40:10.95#ibcon#about to read 3, iclass 6, count 0 2006.203.07:40:10.98#ibcon#read 3, iclass 6, count 0 2006.203.07:40:10.98#ibcon#about to read 4, iclass 6, count 0 2006.203.07:40:10.98#ibcon#read 4, iclass 6, count 0 2006.203.07:40:10.98#ibcon#about to read 5, iclass 6, count 0 2006.203.07:40:10.98#ibcon#read 5, iclass 6, count 0 2006.203.07:40:10.98#ibcon#about to read 6, iclass 6, count 0 2006.203.07:40:10.98#ibcon#read 6, iclass 6, count 0 2006.203.07:40:10.98#ibcon#end of sib2, iclass 6, count 0 2006.203.07:40:10.98#ibcon#*mode == 0, iclass 6, count 0 2006.203.07:40:10.98#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.203.07:40:10.98#ibcon#[26=FRQ=07,832.99\r\n] 2006.203.07:40:10.98#ibcon#*before write, iclass 6, count 0 2006.203.07:40:10.98#ibcon#enter sib2, iclass 6, count 0 2006.203.07:40:10.98#ibcon#flushed, iclass 6, count 0 2006.203.07:40:10.98#ibcon#about to write, iclass 6, count 0 2006.203.07:40:10.98#ibcon#wrote, iclass 6, count 0 2006.203.07:40:10.98#ibcon#about to read 3, iclass 6, count 0 2006.203.07:40:11.02#ibcon#read 3, iclass 6, count 0 2006.203.07:40:11.02#ibcon#about to read 4, iclass 6, count 0 2006.203.07:40:11.02#ibcon#read 4, iclass 6, count 0 2006.203.07:40:11.02#ibcon#about to read 5, iclass 6, count 0 2006.203.07:40:11.02#ibcon#read 5, iclass 6, count 0 2006.203.07:40:11.02#ibcon#about to read 6, iclass 6, count 0 2006.203.07:40:11.02#ibcon#read 6, iclass 6, count 0 2006.203.07:40:11.02#ibcon#end of sib2, iclass 6, count 0 2006.203.07:40:11.02#ibcon#*after write, iclass 6, count 0 2006.203.07:40:11.02#ibcon#*before return 0, iclass 6, count 0 2006.203.07:40:11.02#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.203.07:40:11.02#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.203.07:40:11.02#ibcon#about to clear, iclass 6 cls_cnt 0 2006.203.07:40:11.02#ibcon#cleared, iclass 6 cls_cnt 0 2006.203.07:40:11.02$vc4f8/va=7,7 2006.203.07:40:11.02#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.203.07:40:11.02#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.203.07:40:11.02#ibcon#ireg 11 cls_cnt 2 2006.203.07:40:11.02#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.203.07:40:11.07#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.203.07:40:11.07#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.203.07:40:11.07#ibcon#enter wrdev, iclass 10, count 2 2006.203.07:40:11.07#ibcon#first serial, iclass 10, count 2 2006.203.07:40:11.07#ibcon#enter sib2, iclass 10, count 2 2006.203.07:40:11.07#ibcon#flushed, iclass 10, count 2 2006.203.07:40:11.07#ibcon#about to write, iclass 10, count 2 2006.203.07:40:11.07#ibcon#wrote, iclass 10, count 2 2006.203.07:40:11.07#ibcon#about to read 3, iclass 10, count 2 2006.203.07:40:11.09#ibcon#read 3, iclass 10, count 2 2006.203.07:40:11.09#ibcon#about to read 4, iclass 10, count 2 2006.203.07:40:11.09#ibcon#read 4, iclass 10, count 2 2006.203.07:40:11.09#ibcon#about to read 5, iclass 10, count 2 2006.203.07:40:11.09#ibcon#read 5, iclass 10, count 2 2006.203.07:40:11.09#ibcon#about to read 6, iclass 10, count 2 2006.203.07:40:11.09#ibcon#read 6, iclass 10, count 2 2006.203.07:40:11.09#ibcon#end of sib2, iclass 10, count 2 2006.203.07:40:11.09#ibcon#*mode == 0, iclass 10, count 2 2006.203.07:40:11.09#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.203.07:40:11.09#ibcon#[25=AT07-07\r\n] 2006.203.07:40:11.09#ibcon#*before write, iclass 10, count 2 2006.203.07:40:11.09#ibcon#enter sib2, iclass 10, count 2 2006.203.07:40:11.09#ibcon#flushed, iclass 10, count 2 2006.203.07:40:11.09#ibcon#about to write, iclass 10, count 2 2006.203.07:40:11.09#ibcon#wrote, iclass 10, count 2 2006.203.07:40:11.09#ibcon#about to read 3, iclass 10, count 2 2006.203.07:40:11.12#ibcon#read 3, iclass 10, count 2 2006.203.07:40:11.12#ibcon#about to read 4, iclass 10, count 2 2006.203.07:40:11.12#ibcon#read 4, iclass 10, count 2 2006.203.07:40:11.12#ibcon#about to read 5, iclass 10, count 2 2006.203.07:40:11.12#ibcon#read 5, iclass 10, count 2 2006.203.07:40:11.12#ibcon#about to read 6, iclass 10, count 2 2006.203.07:40:11.12#ibcon#read 6, iclass 10, count 2 2006.203.07:40:11.12#ibcon#end of sib2, iclass 10, count 2 2006.203.07:40:11.12#ibcon#*after write, iclass 10, count 2 2006.203.07:40:11.12#ibcon#*before return 0, iclass 10, count 2 2006.203.07:40:11.12#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.203.07:40:11.12#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.203.07:40:11.12#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.203.07:40:11.12#ibcon#ireg 7 cls_cnt 0 2006.203.07:40:11.12#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.203.07:40:11.24#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.203.07:40:11.24#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.203.07:40:11.24#ibcon#enter wrdev, iclass 10, count 0 2006.203.07:40:11.24#ibcon#first serial, iclass 10, count 0 2006.203.07:40:11.24#ibcon#enter sib2, iclass 10, count 0 2006.203.07:40:11.24#ibcon#flushed, iclass 10, count 0 2006.203.07:40:11.24#ibcon#about to write, iclass 10, count 0 2006.203.07:40:11.24#ibcon#wrote, iclass 10, count 0 2006.203.07:40:11.24#ibcon#about to read 3, iclass 10, count 0 2006.203.07:40:11.26#ibcon#read 3, iclass 10, count 0 2006.203.07:40:11.26#ibcon#about to read 4, iclass 10, count 0 2006.203.07:40:11.26#ibcon#read 4, iclass 10, count 0 2006.203.07:40:11.26#ibcon#about to read 5, iclass 10, count 0 2006.203.07:40:11.26#ibcon#read 5, iclass 10, count 0 2006.203.07:40:11.26#ibcon#about to read 6, iclass 10, count 0 2006.203.07:40:11.26#ibcon#read 6, iclass 10, count 0 2006.203.07:40:11.26#ibcon#end of sib2, iclass 10, count 0 2006.203.07:40:11.26#ibcon#*mode == 0, iclass 10, count 0 2006.203.07:40:11.26#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.203.07:40:11.26#ibcon#[25=USB\r\n] 2006.203.07:40:11.26#ibcon#*before write, iclass 10, count 0 2006.203.07:40:11.26#ibcon#enter sib2, iclass 10, count 0 2006.203.07:40:11.26#ibcon#flushed, iclass 10, count 0 2006.203.07:40:11.26#ibcon#about to write, iclass 10, count 0 2006.203.07:40:11.26#ibcon#wrote, iclass 10, count 0 2006.203.07:40:11.26#ibcon#about to read 3, iclass 10, count 0 2006.203.07:40:11.29#ibcon#read 3, iclass 10, count 0 2006.203.07:40:11.29#ibcon#about to read 4, iclass 10, count 0 2006.203.07:40:11.29#ibcon#read 4, iclass 10, count 0 2006.203.07:40:11.29#ibcon#about to read 5, iclass 10, count 0 2006.203.07:40:11.29#ibcon#read 5, iclass 10, count 0 2006.203.07:40:11.29#ibcon#about to read 6, iclass 10, count 0 2006.203.07:40:11.29#ibcon#read 6, iclass 10, count 0 2006.203.07:40:11.29#ibcon#end of sib2, iclass 10, count 0 2006.203.07:40:11.29#ibcon#*after write, iclass 10, count 0 2006.203.07:40:11.29#ibcon#*before return 0, iclass 10, count 0 2006.203.07:40:11.29#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.203.07:40:11.29#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.203.07:40:11.29#ibcon#about to clear, iclass 10 cls_cnt 0 2006.203.07:40:11.29#ibcon#cleared, iclass 10 cls_cnt 0 2006.203.07:40:11.29$vc4f8/valo=8,852.99 2006.203.07:40:11.29#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.203.07:40:11.29#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.203.07:40:11.29#ibcon#ireg 17 cls_cnt 0 2006.203.07:40:11.29#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.203.07:40:11.29#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.203.07:40:11.29#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.203.07:40:11.29#ibcon#enter wrdev, iclass 12, count 0 2006.203.07:40:11.29#ibcon#first serial, iclass 12, count 0 2006.203.07:40:11.29#ibcon#enter sib2, iclass 12, count 0 2006.203.07:40:11.29#ibcon#flushed, iclass 12, count 0 2006.203.07:40:11.29#ibcon#about to write, iclass 12, count 0 2006.203.07:40:11.29#ibcon#wrote, iclass 12, count 0 2006.203.07:40:11.29#ibcon#about to read 3, iclass 12, count 0 2006.203.07:40:11.31#ibcon#read 3, iclass 12, count 0 2006.203.07:40:11.31#ibcon#about to read 4, iclass 12, count 0 2006.203.07:40:11.31#ibcon#read 4, iclass 12, count 0 2006.203.07:40:11.31#ibcon#about to read 5, iclass 12, count 0 2006.203.07:40:11.31#ibcon#read 5, iclass 12, count 0 2006.203.07:40:11.31#ibcon#about to read 6, iclass 12, count 0 2006.203.07:40:11.31#ibcon#read 6, iclass 12, count 0 2006.203.07:40:11.31#ibcon#end of sib2, iclass 12, count 0 2006.203.07:40:11.31#ibcon#*mode == 0, iclass 12, count 0 2006.203.07:40:11.31#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.203.07:40:11.31#ibcon#[26=FRQ=08,852.99\r\n] 2006.203.07:40:11.31#ibcon#*before write, iclass 12, count 0 2006.203.07:40:11.31#ibcon#enter sib2, iclass 12, count 0 2006.203.07:40:11.31#ibcon#flushed, iclass 12, count 0 2006.203.07:40:11.31#ibcon#about to write, iclass 12, count 0 2006.203.07:40:11.31#ibcon#wrote, iclass 12, count 0 2006.203.07:40:11.31#ibcon#about to read 3, iclass 12, count 0 2006.203.07:40:11.35#ibcon#read 3, iclass 12, count 0 2006.203.07:40:11.35#ibcon#about to read 4, iclass 12, count 0 2006.203.07:40:11.35#ibcon#read 4, iclass 12, count 0 2006.203.07:40:11.35#ibcon#about to read 5, iclass 12, count 0 2006.203.07:40:11.35#ibcon#read 5, iclass 12, count 0 2006.203.07:40:11.35#ibcon#about to read 6, iclass 12, count 0 2006.203.07:40:11.35#ibcon#read 6, iclass 12, count 0 2006.203.07:40:11.35#ibcon#end of sib2, iclass 12, count 0 2006.203.07:40:11.35#ibcon#*after write, iclass 12, count 0 2006.203.07:40:11.35#ibcon#*before return 0, iclass 12, count 0 2006.203.07:40:11.35#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.203.07:40:11.35#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.203.07:40:11.35#ibcon#about to clear, iclass 12 cls_cnt 0 2006.203.07:40:11.35#ibcon#cleared, iclass 12 cls_cnt 0 2006.203.07:40:11.35$vc4f8/va=8,6 2006.203.07:40:11.35#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.203.07:40:11.35#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.203.07:40:11.35#ibcon#ireg 11 cls_cnt 2 2006.203.07:40:11.35#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.203.07:40:11.41#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.203.07:40:11.41#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.203.07:40:11.41#ibcon#enter wrdev, iclass 14, count 2 2006.203.07:40:11.41#ibcon#first serial, iclass 14, count 2 2006.203.07:40:11.41#ibcon#enter sib2, iclass 14, count 2 2006.203.07:40:11.41#ibcon#flushed, iclass 14, count 2 2006.203.07:40:11.41#ibcon#about to write, iclass 14, count 2 2006.203.07:40:11.41#ibcon#wrote, iclass 14, count 2 2006.203.07:40:11.41#ibcon#about to read 3, iclass 14, count 2 2006.203.07:40:11.43#ibcon#read 3, iclass 14, count 2 2006.203.07:40:11.43#ibcon#about to read 4, iclass 14, count 2 2006.203.07:40:11.43#ibcon#read 4, iclass 14, count 2 2006.203.07:40:11.43#ibcon#about to read 5, iclass 14, count 2 2006.203.07:40:11.43#ibcon#read 5, iclass 14, count 2 2006.203.07:40:11.43#ibcon#about to read 6, iclass 14, count 2 2006.203.07:40:11.43#ibcon#read 6, iclass 14, count 2 2006.203.07:40:11.43#ibcon#end of sib2, iclass 14, count 2 2006.203.07:40:11.43#ibcon#*mode == 0, iclass 14, count 2 2006.203.07:40:11.43#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.203.07:40:11.43#ibcon#[25=AT08-06\r\n] 2006.203.07:40:11.43#ibcon#*before write, iclass 14, count 2 2006.203.07:40:11.43#ibcon#enter sib2, iclass 14, count 2 2006.203.07:40:11.43#ibcon#flushed, iclass 14, count 2 2006.203.07:40:11.43#ibcon#about to write, iclass 14, count 2 2006.203.07:40:11.43#ibcon#wrote, iclass 14, count 2 2006.203.07:40:11.43#ibcon#about to read 3, iclass 14, count 2 2006.203.07:40:11.46#ibcon#read 3, iclass 14, count 2 2006.203.07:40:11.46#ibcon#about to read 4, iclass 14, count 2 2006.203.07:40:11.46#ibcon#read 4, iclass 14, count 2 2006.203.07:40:11.46#ibcon#about to read 5, iclass 14, count 2 2006.203.07:40:11.46#ibcon#read 5, iclass 14, count 2 2006.203.07:40:11.46#ibcon#about to read 6, iclass 14, count 2 2006.203.07:40:11.46#ibcon#read 6, iclass 14, count 2 2006.203.07:40:11.46#ibcon#end of sib2, iclass 14, count 2 2006.203.07:40:11.46#ibcon#*after write, iclass 14, count 2 2006.203.07:40:11.46#ibcon#*before return 0, iclass 14, count 2 2006.203.07:40:11.46#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.203.07:40:11.46#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.203.07:40:11.46#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.203.07:40:11.46#ibcon#ireg 7 cls_cnt 0 2006.203.07:40:11.46#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.203.07:40:11.58#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.203.07:40:11.58#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.203.07:40:11.58#ibcon#enter wrdev, iclass 14, count 0 2006.203.07:40:11.58#ibcon#first serial, iclass 14, count 0 2006.203.07:40:11.58#ibcon#enter sib2, iclass 14, count 0 2006.203.07:40:11.58#ibcon#flushed, iclass 14, count 0 2006.203.07:40:11.58#ibcon#about to write, iclass 14, count 0 2006.203.07:40:11.58#ibcon#wrote, iclass 14, count 0 2006.203.07:40:11.58#ibcon#about to read 3, iclass 14, count 0 2006.203.07:40:11.60#ibcon#read 3, iclass 14, count 0 2006.203.07:40:11.60#ibcon#about to read 4, iclass 14, count 0 2006.203.07:40:11.60#ibcon#read 4, iclass 14, count 0 2006.203.07:40:11.60#ibcon#about to read 5, iclass 14, count 0 2006.203.07:40:11.60#ibcon#read 5, iclass 14, count 0 2006.203.07:40:11.60#ibcon#about to read 6, iclass 14, count 0 2006.203.07:40:11.60#ibcon#read 6, iclass 14, count 0 2006.203.07:40:11.60#ibcon#end of sib2, iclass 14, count 0 2006.203.07:40:11.60#ibcon#*mode == 0, iclass 14, count 0 2006.203.07:40:11.60#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.203.07:40:11.60#ibcon#[25=USB\r\n] 2006.203.07:40:11.60#ibcon#*before write, iclass 14, count 0 2006.203.07:40:11.60#ibcon#enter sib2, iclass 14, count 0 2006.203.07:40:11.60#ibcon#flushed, iclass 14, count 0 2006.203.07:40:11.60#ibcon#about to write, iclass 14, count 0 2006.203.07:40:11.60#ibcon#wrote, iclass 14, count 0 2006.203.07:40:11.60#ibcon#about to read 3, iclass 14, count 0 2006.203.07:40:11.63#ibcon#read 3, iclass 14, count 0 2006.203.07:40:11.63#ibcon#about to read 4, iclass 14, count 0 2006.203.07:40:11.63#ibcon#read 4, iclass 14, count 0 2006.203.07:40:11.63#ibcon#about to read 5, iclass 14, count 0 2006.203.07:40:11.63#ibcon#read 5, iclass 14, count 0 2006.203.07:40:11.63#ibcon#about to read 6, iclass 14, count 0 2006.203.07:40:11.63#ibcon#read 6, iclass 14, count 0 2006.203.07:40:11.63#ibcon#end of sib2, iclass 14, count 0 2006.203.07:40:11.63#ibcon#*after write, iclass 14, count 0 2006.203.07:40:11.63#ibcon#*before return 0, iclass 14, count 0 2006.203.07:40:11.63#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.203.07:40:11.63#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.203.07:40:11.63#ibcon#about to clear, iclass 14 cls_cnt 0 2006.203.07:40:11.63#ibcon#cleared, iclass 14 cls_cnt 0 2006.203.07:40:11.63$vc4f8/vblo=1,632.99 2006.203.07:40:11.63#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.203.07:40:11.63#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.203.07:40:11.63#ibcon#ireg 17 cls_cnt 0 2006.203.07:40:11.63#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.203.07:40:11.63#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.203.07:40:11.63#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.203.07:40:11.63#ibcon#enter wrdev, iclass 16, count 0 2006.203.07:40:11.63#ibcon#first serial, iclass 16, count 0 2006.203.07:40:11.63#ibcon#enter sib2, iclass 16, count 0 2006.203.07:40:11.63#ibcon#flushed, iclass 16, count 0 2006.203.07:40:11.63#ibcon#about to write, iclass 16, count 0 2006.203.07:40:11.63#ibcon#wrote, iclass 16, count 0 2006.203.07:40:11.63#ibcon#about to read 3, iclass 16, count 0 2006.203.07:40:11.66#ibcon#read 3, iclass 16, count 0 2006.203.07:40:11.66#ibcon#about to read 4, iclass 16, count 0 2006.203.07:40:11.66#ibcon#read 4, iclass 16, count 0 2006.203.07:40:11.66#ibcon#about to read 5, iclass 16, count 0 2006.203.07:40:11.66#ibcon#read 5, iclass 16, count 0 2006.203.07:40:11.66#ibcon#about to read 6, iclass 16, count 0 2006.203.07:40:11.66#ibcon#read 6, iclass 16, count 0 2006.203.07:40:11.66#ibcon#end of sib2, iclass 16, count 0 2006.203.07:40:11.66#ibcon#*mode == 0, iclass 16, count 0 2006.203.07:40:11.66#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.203.07:40:11.66#ibcon#[28=FRQ=01,632.99\r\n] 2006.203.07:40:11.66#ibcon#*before write, iclass 16, count 0 2006.203.07:40:11.66#ibcon#enter sib2, iclass 16, count 0 2006.203.07:40:11.66#ibcon#flushed, iclass 16, count 0 2006.203.07:40:11.66#ibcon#about to write, iclass 16, count 0 2006.203.07:40:11.66#ibcon#wrote, iclass 16, count 0 2006.203.07:40:11.66#ibcon#about to read 3, iclass 16, count 0 2006.203.07:40:11.70#ibcon#read 3, iclass 16, count 0 2006.203.07:40:11.70#ibcon#about to read 4, iclass 16, count 0 2006.203.07:40:11.70#ibcon#read 4, iclass 16, count 0 2006.203.07:40:11.70#ibcon#about to read 5, iclass 16, count 0 2006.203.07:40:11.70#ibcon#read 5, iclass 16, count 0 2006.203.07:40:11.70#ibcon#about to read 6, iclass 16, count 0 2006.203.07:40:11.70#ibcon#read 6, iclass 16, count 0 2006.203.07:40:11.70#ibcon#end of sib2, iclass 16, count 0 2006.203.07:40:11.70#ibcon#*after write, iclass 16, count 0 2006.203.07:40:11.70#ibcon#*before return 0, iclass 16, count 0 2006.203.07:40:11.70#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.203.07:40:11.70#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.203.07:40:11.70#ibcon#about to clear, iclass 16 cls_cnt 0 2006.203.07:40:11.70#ibcon#cleared, iclass 16 cls_cnt 0 2006.203.07:40:11.70$vc4f8/vb=1,4 2006.203.07:40:11.70#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.203.07:40:11.70#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.203.07:40:11.70#ibcon#ireg 11 cls_cnt 2 2006.203.07:40:11.70#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.203.07:40:11.70#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.203.07:40:11.70#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.203.07:40:11.70#ibcon#enter wrdev, iclass 18, count 2 2006.203.07:40:11.70#ibcon#first serial, iclass 18, count 2 2006.203.07:40:11.70#ibcon#enter sib2, iclass 18, count 2 2006.203.07:40:11.70#ibcon#flushed, iclass 18, count 2 2006.203.07:40:11.70#ibcon#about to write, iclass 18, count 2 2006.203.07:40:11.70#ibcon#wrote, iclass 18, count 2 2006.203.07:40:11.70#ibcon#about to read 3, iclass 18, count 2 2006.203.07:40:11.72#ibcon#read 3, iclass 18, count 2 2006.203.07:40:11.72#ibcon#about to read 4, iclass 18, count 2 2006.203.07:40:11.72#ibcon#read 4, iclass 18, count 2 2006.203.07:40:11.72#ibcon#about to read 5, iclass 18, count 2 2006.203.07:40:11.72#ibcon#read 5, iclass 18, count 2 2006.203.07:40:11.72#ibcon#about to read 6, iclass 18, count 2 2006.203.07:40:11.72#ibcon#read 6, iclass 18, count 2 2006.203.07:40:11.72#ibcon#end of sib2, iclass 18, count 2 2006.203.07:40:11.72#ibcon#*mode == 0, iclass 18, count 2 2006.203.07:40:11.72#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.203.07:40:11.72#ibcon#[27=AT01-04\r\n] 2006.203.07:40:11.72#ibcon#*before write, iclass 18, count 2 2006.203.07:40:11.72#ibcon#enter sib2, iclass 18, count 2 2006.203.07:40:11.72#ibcon#flushed, iclass 18, count 2 2006.203.07:40:11.72#ibcon#about to write, iclass 18, count 2 2006.203.07:40:11.72#ibcon#wrote, iclass 18, count 2 2006.203.07:40:11.72#ibcon#about to read 3, iclass 18, count 2 2006.203.07:40:11.76#ibcon#read 3, iclass 18, count 2 2006.203.07:40:11.76#ibcon#about to read 4, iclass 18, count 2 2006.203.07:40:11.76#ibcon#read 4, iclass 18, count 2 2006.203.07:40:11.76#ibcon#about to read 5, iclass 18, count 2 2006.203.07:40:11.76#ibcon#read 5, iclass 18, count 2 2006.203.07:40:11.76#ibcon#about to read 6, iclass 18, count 2 2006.203.07:40:11.76#ibcon#read 6, iclass 18, count 2 2006.203.07:40:11.76#ibcon#end of sib2, iclass 18, count 2 2006.203.07:40:11.76#ibcon#*after write, iclass 18, count 2 2006.203.07:40:11.76#ibcon#*before return 0, iclass 18, count 2 2006.203.07:40:11.76#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.203.07:40:11.76#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.203.07:40:11.76#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.203.07:40:11.76#ibcon#ireg 7 cls_cnt 0 2006.203.07:40:11.76#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.203.07:40:11.87#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.203.07:40:11.87#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.203.07:40:11.87#ibcon#enter wrdev, iclass 18, count 0 2006.203.07:40:11.87#ibcon#first serial, iclass 18, count 0 2006.203.07:40:11.87#ibcon#enter sib2, iclass 18, count 0 2006.203.07:40:11.87#ibcon#flushed, iclass 18, count 0 2006.203.07:40:11.87#ibcon#about to write, iclass 18, count 0 2006.203.07:40:11.87#ibcon#wrote, iclass 18, count 0 2006.203.07:40:11.87#ibcon#about to read 3, iclass 18, count 0 2006.203.07:40:11.89#ibcon#read 3, iclass 18, count 0 2006.203.07:40:11.89#ibcon#about to read 4, iclass 18, count 0 2006.203.07:40:11.89#ibcon#read 4, iclass 18, count 0 2006.203.07:40:11.89#ibcon#about to read 5, iclass 18, count 0 2006.203.07:40:11.89#ibcon#read 5, iclass 18, count 0 2006.203.07:40:11.89#ibcon#about to read 6, iclass 18, count 0 2006.203.07:40:11.89#ibcon#read 6, iclass 18, count 0 2006.203.07:40:11.89#ibcon#end of sib2, iclass 18, count 0 2006.203.07:40:11.89#ibcon#*mode == 0, iclass 18, count 0 2006.203.07:40:11.89#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.203.07:40:11.89#ibcon#[27=USB\r\n] 2006.203.07:40:11.89#ibcon#*before write, iclass 18, count 0 2006.203.07:40:11.89#ibcon#enter sib2, iclass 18, count 0 2006.203.07:40:11.89#ibcon#flushed, iclass 18, count 0 2006.203.07:40:11.89#ibcon#about to write, iclass 18, count 0 2006.203.07:40:11.89#ibcon#wrote, iclass 18, count 0 2006.203.07:40:11.89#ibcon#about to read 3, iclass 18, count 0 2006.203.07:40:11.92#ibcon#read 3, iclass 18, count 0 2006.203.07:40:11.92#ibcon#about to read 4, iclass 18, count 0 2006.203.07:40:11.92#ibcon#read 4, iclass 18, count 0 2006.203.07:40:11.92#ibcon#about to read 5, iclass 18, count 0 2006.203.07:40:11.92#ibcon#read 5, iclass 18, count 0 2006.203.07:40:11.92#ibcon#about to read 6, iclass 18, count 0 2006.203.07:40:11.92#ibcon#read 6, iclass 18, count 0 2006.203.07:40:11.92#ibcon#end of sib2, iclass 18, count 0 2006.203.07:40:11.92#ibcon#*after write, iclass 18, count 0 2006.203.07:40:11.92#ibcon#*before return 0, iclass 18, count 0 2006.203.07:40:11.92#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.203.07:40:11.92#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.203.07:40:11.92#ibcon#about to clear, iclass 18 cls_cnt 0 2006.203.07:40:11.92#ibcon#cleared, iclass 18 cls_cnt 0 2006.203.07:40:11.92$vc4f8/vblo=2,640.99 2006.203.07:40:11.92#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.203.07:40:11.92#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.203.07:40:11.92#ibcon#ireg 17 cls_cnt 0 2006.203.07:40:11.92#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.203.07:40:11.92#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.203.07:40:11.92#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.203.07:40:11.92#ibcon#enter wrdev, iclass 20, count 0 2006.203.07:40:11.92#ibcon#first serial, iclass 20, count 0 2006.203.07:40:11.92#ibcon#enter sib2, iclass 20, count 0 2006.203.07:40:11.92#ibcon#flushed, iclass 20, count 0 2006.203.07:40:11.92#ibcon#about to write, iclass 20, count 0 2006.203.07:40:11.92#ibcon#wrote, iclass 20, count 0 2006.203.07:40:11.92#ibcon#about to read 3, iclass 20, count 0 2006.203.07:40:11.94#ibcon#read 3, iclass 20, count 0 2006.203.07:40:11.94#ibcon#about to read 4, iclass 20, count 0 2006.203.07:40:11.94#ibcon#read 4, iclass 20, count 0 2006.203.07:40:11.94#ibcon#about to read 5, iclass 20, count 0 2006.203.07:40:11.94#ibcon#read 5, iclass 20, count 0 2006.203.07:40:11.94#ibcon#about to read 6, iclass 20, count 0 2006.203.07:40:11.94#ibcon#read 6, iclass 20, count 0 2006.203.07:40:11.94#ibcon#end of sib2, iclass 20, count 0 2006.203.07:40:11.94#ibcon#*mode == 0, iclass 20, count 0 2006.203.07:40:11.94#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.203.07:40:11.94#ibcon#[28=FRQ=02,640.99\r\n] 2006.203.07:40:11.94#ibcon#*before write, iclass 20, count 0 2006.203.07:40:11.94#ibcon#enter sib2, iclass 20, count 0 2006.203.07:40:11.94#ibcon#flushed, iclass 20, count 0 2006.203.07:40:11.94#ibcon#about to write, iclass 20, count 0 2006.203.07:40:11.94#ibcon#wrote, iclass 20, count 0 2006.203.07:40:11.94#ibcon#about to read 3, iclass 20, count 0 2006.203.07:40:11.98#ibcon#read 3, iclass 20, count 0 2006.203.07:40:11.98#ibcon#about to read 4, iclass 20, count 0 2006.203.07:40:11.98#ibcon#read 4, iclass 20, count 0 2006.203.07:40:11.98#ibcon#about to read 5, iclass 20, count 0 2006.203.07:40:11.98#ibcon#read 5, iclass 20, count 0 2006.203.07:40:11.98#ibcon#about to read 6, iclass 20, count 0 2006.203.07:40:11.98#ibcon#read 6, iclass 20, count 0 2006.203.07:40:11.98#ibcon#end of sib2, iclass 20, count 0 2006.203.07:40:11.98#ibcon#*after write, iclass 20, count 0 2006.203.07:40:11.98#ibcon#*before return 0, iclass 20, count 0 2006.203.07:40:11.98#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.203.07:40:11.98#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.203.07:40:11.98#ibcon#about to clear, iclass 20 cls_cnt 0 2006.203.07:40:11.98#ibcon#cleared, iclass 20 cls_cnt 0 2006.203.07:40:11.98$vc4f8/vb=2,4 2006.203.07:40:11.98#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.203.07:40:11.98#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.203.07:40:11.98#ibcon#ireg 11 cls_cnt 2 2006.203.07:40:11.98#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.203.07:40:12.04#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.203.07:40:12.04#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.203.07:40:12.04#ibcon#enter wrdev, iclass 22, count 2 2006.203.07:40:12.04#ibcon#first serial, iclass 22, count 2 2006.203.07:40:12.04#ibcon#enter sib2, iclass 22, count 2 2006.203.07:40:12.04#ibcon#flushed, iclass 22, count 2 2006.203.07:40:12.04#ibcon#about to write, iclass 22, count 2 2006.203.07:40:12.04#ibcon#wrote, iclass 22, count 2 2006.203.07:40:12.04#ibcon#about to read 3, iclass 22, count 2 2006.203.07:40:12.06#ibcon#read 3, iclass 22, count 2 2006.203.07:40:12.06#ibcon#about to read 4, iclass 22, count 2 2006.203.07:40:12.06#ibcon#read 4, iclass 22, count 2 2006.203.07:40:12.06#ibcon#about to read 5, iclass 22, count 2 2006.203.07:40:12.06#ibcon#read 5, iclass 22, count 2 2006.203.07:40:12.06#ibcon#about to read 6, iclass 22, count 2 2006.203.07:40:12.06#ibcon#read 6, iclass 22, count 2 2006.203.07:40:12.06#ibcon#end of sib2, iclass 22, count 2 2006.203.07:40:12.06#ibcon#*mode == 0, iclass 22, count 2 2006.203.07:40:12.06#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.203.07:40:12.06#ibcon#[27=AT02-04\r\n] 2006.203.07:40:12.06#ibcon#*before write, iclass 22, count 2 2006.203.07:40:12.06#ibcon#enter sib2, iclass 22, count 2 2006.203.07:40:12.06#ibcon#flushed, iclass 22, count 2 2006.203.07:40:12.06#ibcon#about to write, iclass 22, count 2 2006.203.07:40:12.06#ibcon#wrote, iclass 22, count 2 2006.203.07:40:12.06#ibcon#about to read 3, iclass 22, count 2 2006.203.07:40:12.09#ibcon#read 3, iclass 22, count 2 2006.203.07:40:12.09#ibcon#about to read 4, iclass 22, count 2 2006.203.07:40:12.09#ibcon#read 4, iclass 22, count 2 2006.203.07:40:12.09#ibcon#about to read 5, iclass 22, count 2 2006.203.07:40:12.09#ibcon#read 5, iclass 22, count 2 2006.203.07:40:12.09#ibcon#about to read 6, iclass 22, count 2 2006.203.07:40:12.09#ibcon#read 6, iclass 22, count 2 2006.203.07:40:12.09#ibcon#end of sib2, iclass 22, count 2 2006.203.07:40:12.09#ibcon#*after write, iclass 22, count 2 2006.203.07:40:12.09#ibcon#*before return 0, iclass 22, count 2 2006.203.07:40:12.09#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.203.07:40:12.09#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.203.07:40:12.09#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.203.07:40:12.09#ibcon#ireg 7 cls_cnt 0 2006.203.07:40:12.09#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.203.07:40:12.21#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.203.07:40:12.21#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.203.07:40:12.21#ibcon#enter wrdev, iclass 22, count 0 2006.203.07:40:12.21#ibcon#first serial, iclass 22, count 0 2006.203.07:40:12.21#ibcon#enter sib2, iclass 22, count 0 2006.203.07:40:12.21#ibcon#flushed, iclass 22, count 0 2006.203.07:40:12.21#ibcon#about to write, iclass 22, count 0 2006.203.07:40:12.21#ibcon#wrote, iclass 22, count 0 2006.203.07:40:12.21#ibcon#about to read 3, iclass 22, count 0 2006.203.07:40:12.25#ibcon#read 3, iclass 22, count 0 2006.203.07:40:12.25#ibcon#about to read 4, iclass 22, count 0 2006.203.07:40:12.25#ibcon#read 4, iclass 22, count 0 2006.203.07:40:12.25#ibcon#about to read 5, iclass 22, count 0 2006.203.07:40:12.25#ibcon#read 5, iclass 22, count 0 2006.203.07:40:12.25#ibcon#about to read 6, iclass 22, count 0 2006.203.07:40:12.25#ibcon#read 6, iclass 22, count 0 2006.203.07:40:12.25#ibcon#end of sib2, iclass 22, count 0 2006.203.07:40:12.25#ibcon#*mode == 0, iclass 22, count 0 2006.203.07:40:12.25#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.203.07:40:12.25#ibcon#[27=USB\r\n] 2006.203.07:40:12.25#ibcon#*before write, iclass 22, count 0 2006.203.07:40:12.25#ibcon#enter sib2, iclass 22, count 0 2006.203.07:40:12.25#ibcon#flushed, iclass 22, count 0 2006.203.07:40:12.25#ibcon#about to write, iclass 22, count 0 2006.203.07:40:12.25#ibcon#wrote, iclass 22, count 0 2006.203.07:40:12.25#ibcon#about to read 3, iclass 22, count 0 2006.203.07:40:12.28#ibcon#read 3, iclass 22, count 0 2006.203.07:40:12.28#ibcon#about to read 4, iclass 22, count 0 2006.203.07:40:12.28#ibcon#read 4, iclass 22, count 0 2006.203.07:40:12.28#ibcon#about to read 5, iclass 22, count 0 2006.203.07:40:12.28#ibcon#read 5, iclass 22, count 0 2006.203.07:40:12.28#ibcon#about to read 6, iclass 22, count 0 2006.203.07:40:12.28#ibcon#read 6, iclass 22, count 0 2006.203.07:40:12.28#ibcon#end of sib2, iclass 22, count 0 2006.203.07:40:12.28#ibcon#*after write, iclass 22, count 0 2006.203.07:40:12.28#ibcon#*before return 0, iclass 22, count 0 2006.203.07:40:12.28#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.203.07:40:12.28#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.203.07:40:12.28#ibcon#about to clear, iclass 22 cls_cnt 0 2006.203.07:40:12.28#ibcon#cleared, iclass 22 cls_cnt 0 2006.203.07:40:12.28$vc4f8/vblo=3,656.99 2006.203.07:40:12.28#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.203.07:40:12.28#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.203.07:40:12.28#ibcon#ireg 17 cls_cnt 0 2006.203.07:40:12.28#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.203.07:40:12.28#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.203.07:40:12.28#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.203.07:40:12.28#ibcon#enter wrdev, iclass 24, count 0 2006.203.07:40:12.28#ibcon#first serial, iclass 24, count 0 2006.203.07:40:12.28#ibcon#enter sib2, iclass 24, count 0 2006.203.07:40:12.28#ibcon#flushed, iclass 24, count 0 2006.203.07:40:12.28#ibcon#about to write, iclass 24, count 0 2006.203.07:40:12.28#ibcon#wrote, iclass 24, count 0 2006.203.07:40:12.28#ibcon#about to read 3, iclass 24, count 0 2006.203.07:40:12.30#ibcon#read 3, iclass 24, count 0 2006.203.07:40:12.30#ibcon#about to read 4, iclass 24, count 0 2006.203.07:40:12.30#ibcon#read 4, iclass 24, count 0 2006.203.07:40:12.30#ibcon#about to read 5, iclass 24, count 0 2006.203.07:40:12.30#ibcon#read 5, iclass 24, count 0 2006.203.07:40:12.30#ibcon#about to read 6, iclass 24, count 0 2006.203.07:40:12.30#ibcon#read 6, iclass 24, count 0 2006.203.07:40:12.30#ibcon#end of sib2, iclass 24, count 0 2006.203.07:40:12.30#ibcon#*mode == 0, iclass 24, count 0 2006.203.07:40:12.30#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.203.07:40:12.30#ibcon#[28=FRQ=03,656.99\r\n] 2006.203.07:40:12.30#ibcon#*before write, iclass 24, count 0 2006.203.07:40:12.30#ibcon#enter sib2, iclass 24, count 0 2006.203.07:40:12.30#ibcon#flushed, iclass 24, count 0 2006.203.07:40:12.30#ibcon#about to write, iclass 24, count 0 2006.203.07:40:12.30#ibcon#wrote, iclass 24, count 0 2006.203.07:40:12.30#ibcon#about to read 3, iclass 24, count 0 2006.203.07:40:12.34#ibcon#read 3, iclass 24, count 0 2006.203.07:40:12.34#ibcon#about to read 4, iclass 24, count 0 2006.203.07:40:12.34#ibcon#read 4, iclass 24, count 0 2006.203.07:40:12.34#ibcon#about to read 5, iclass 24, count 0 2006.203.07:40:12.34#ibcon#read 5, iclass 24, count 0 2006.203.07:40:12.34#ibcon#about to read 6, iclass 24, count 0 2006.203.07:40:12.34#ibcon#read 6, iclass 24, count 0 2006.203.07:40:12.34#ibcon#end of sib2, iclass 24, count 0 2006.203.07:40:12.34#ibcon#*after write, iclass 24, count 0 2006.203.07:40:12.34#ibcon#*before return 0, iclass 24, count 0 2006.203.07:40:12.34#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.203.07:40:12.34#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.203.07:40:12.34#ibcon#about to clear, iclass 24 cls_cnt 0 2006.203.07:40:12.34#ibcon#cleared, iclass 24 cls_cnt 0 2006.203.07:40:12.34$vc4f8/vb=3,4 2006.203.07:40:12.34#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.203.07:40:12.34#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.203.07:40:12.34#ibcon#ireg 11 cls_cnt 2 2006.203.07:40:12.34#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.203.07:40:12.40#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.203.07:40:12.40#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.203.07:40:12.40#ibcon#enter wrdev, iclass 26, count 2 2006.203.07:40:12.40#ibcon#first serial, iclass 26, count 2 2006.203.07:40:12.40#ibcon#enter sib2, iclass 26, count 2 2006.203.07:40:12.40#ibcon#flushed, iclass 26, count 2 2006.203.07:40:12.40#ibcon#about to write, iclass 26, count 2 2006.203.07:40:12.40#ibcon#wrote, iclass 26, count 2 2006.203.07:40:12.40#ibcon#about to read 3, iclass 26, count 2 2006.203.07:40:12.43#ibcon#read 3, iclass 26, count 2 2006.203.07:40:12.43#ibcon#about to read 4, iclass 26, count 2 2006.203.07:40:12.43#ibcon#read 4, iclass 26, count 2 2006.203.07:40:12.43#ibcon#about to read 5, iclass 26, count 2 2006.203.07:40:12.43#ibcon#read 5, iclass 26, count 2 2006.203.07:40:12.43#ibcon#about to read 6, iclass 26, count 2 2006.203.07:40:12.43#ibcon#read 6, iclass 26, count 2 2006.203.07:40:12.43#ibcon#end of sib2, iclass 26, count 2 2006.203.07:40:12.43#ibcon#*mode == 0, iclass 26, count 2 2006.203.07:40:12.43#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.203.07:40:12.43#ibcon#[27=AT03-04\r\n] 2006.203.07:40:12.43#ibcon#*before write, iclass 26, count 2 2006.203.07:40:12.43#ibcon#enter sib2, iclass 26, count 2 2006.203.07:40:12.43#ibcon#flushed, iclass 26, count 2 2006.203.07:40:12.43#ibcon#about to write, iclass 26, count 2 2006.203.07:40:12.43#ibcon#wrote, iclass 26, count 2 2006.203.07:40:12.43#ibcon#about to read 3, iclass 26, count 2 2006.203.07:40:12.46#ibcon#read 3, iclass 26, count 2 2006.203.07:40:12.46#ibcon#about to read 4, iclass 26, count 2 2006.203.07:40:12.46#ibcon#read 4, iclass 26, count 2 2006.203.07:40:12.46#ibcon#about to read 5, iclass 26, count 2 2006.203.07:40:12.46#ibcon#read 5, iclass 26, count 2 2006.203.07:40:12.46#ibcon#about to read 6, iclass 26, count 2 2006.203.07:40:12.46#ibcon#read 6, iclass 26, count 2 2006.203.07:40:12.46#ibcon#end of sib2, iclass 26, count 2 2006.203.07:40:12.46#ibcon#*after write, iclass 26, count 2 2006.203.07:40:12.46#ibcon#*before return 0, iclass 26, count 2 2006.203.07:40:12.46#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.203.07:40:12.46#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.203.07:40:12.46#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.203.07:40:12.46#ibcon#ireg 7 cls_cnt 0 2006.203.07:40:12.46#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.203.07:40:12.58#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.203.07:40:12.58#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.203.07:40:12.58#ibcon#enter wrdev, iclass 26, count 0 2006.203.07:40:12.58#ibcon#first serial, iclass 26, count 0 2006.203.07:40:12.58#ibcon#enter sib2, iclass 26, count 0 2006.203.07:40:12.58#ibcon#flushed, iclass 26, count 0 2006.203.07:40:12.58#ibcon#about to write, iclass 26, count 0 2006.203.07:40:12.58#ibcon#wrote, iclass 26, count 0 2006.203.07:40:12.58#ibcon#about to read 3, iclass 26, count 0 2006.203.07:40:12.60#ibcon#read 3, iclass 26, count 0 2006.203.07:40:12.60#ibcon#about to read 4, iclass 26, count 0 2006.203.07:40:12.60#ibcon#read 4, iclass 26, count 0 2006.203.07:40:12.60#ibcon#about to read 5, iclass 26, count 0 2006.203.07:40:12.60#ibcon#read 5, iclass 26, count 0 2006.203.07:40:12.60#ibcon#about to read 6, iclass 26, count 0 2006.203.07:40:12.60#ibcon#read 6, iclass 26, count 0 2006.203.07:40:12.60#ibcon#end of sib2, iclass 26, count 0 2006.203.07:40:12.60#ibcon#*mode == 0, iclass 26, count 0 2006.203.07:40:12.60#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.203.07:40:12.60#ibcon#[27=USB\r\n] 2006.203.07:40:12.60#ibcon#*before write, iclass 26, count 0 2006.203.07:40:12.60#ibcon#enter sib2, iclass 26, count 0 2006.203.07:40:12.60#ibcon#flushed, iclass 26, count 0 2006.203.07:40:12.60#ibcon#about to write, iclass 26, count 0 2006.203.07:40:12.60#ibcon#wrote, iclass 26, count 0 2006.203.07:40:12.60#ibcon#about to read 3, iclass 26, count 0 2006.203.07:40:12.63#ibcon#read 3, iclass 26, count 0 2006.203.07:40:12.63#ibcon#about to read 4, iclass 26, count 0 2006.203.07:40:12.63#ibcon#read 4, iclass 26, count 0 2006.203.07:40:12.63#ibcon#about to read 5, iclass 26, count 0 2006.203.07:40:12.63#ibcon#read 5, iclass 26, count 0 2006.203.07:40:12.63#ibcon#about to read 6, iclass 26, count 0 2006.203.07:40:12.63#ibcon#read 6, iclass 26, count 0 2006.203.07:40:12.63#ibcon#end of sib2, iclass 26, count 0 2006.203.07:40:12.63#ibcon#*after write, iclass 26, count 0 2006.203.07:40:12.63#ibcon#*before return 0, iclass 26, count 0 2006.203.07:40:12.63#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.203.07:40:12.63#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.203.07:40:12.63#ibcon#about to clear, iclass 26 cls_cnt 0 2006.203.07:40:12.63#ibcon#cleared, iclass 26 cls_cnt 0 2006.203.07:40:12.63$vc4f8/vblo=4,712.99 2006.203.07:40:12.63#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.203.07:40:12.63#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.203.07:40:12.63#ibcon#ireg 17 cls_cnt 0 2006.203.07:40:12.63#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.203.07:40:12.63#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.203.07:40:12.63#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.203.07:40:12.63#ibcon#enter wrdev, iclass 28, count 0 2006.203.07:40:12.63#ibcon#first serial, iclass 28, count 0 2006.203.07:40:12.63#ibcon#enter sib2, iclass 28, count 0 2006.203.07:40:12.63#ibcon#flushed, iclass 28, count 0 2006.203.07:40:12.63#ibcon#about to write, iclass 28, count 0 2006.203.07:40:12.63#ibcon#wrote, iclass 28, count 0 2006.203.07:40:12.63#ibcon#about to read 3, iclass 28, count 0 2006.203.07:40:12.65#ibcon#read 3, iclass 28, count 0 2006.203.07:40:12.65#ibcon#about to read 4, iclass 28, count 0 2006.203.07:40:12.65#ibcon#read 4, iclass 28, count 0 2006.203.07:40:12.65#ibcon#about to read 5, iclass 28, count 0 2006.203.07:40:12.65#ibcon#read 5, iclass 28, count 0 2006.203.07:40:12.65#ibcon#about to read 6, iclass 28, count 0 2006.203.07:40:12.65#ibcon#read 6, iclass 28, count 0 2006.203.07:40:12.65#ibcon#end of sib2, iclass 28, count 0 2006.203.07:40:12.65#ibcon#*mode == 0, iclass 28, count 0 2006.203.07:40:12.65#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.203.07:40:12.65#ibcon#[28=FRQ=04,712.99\r\n] 2006.203.07:40:12.65#ibcon#*before write, iclass 28, count 0 2006.203.07:40:12.65#ibcon#enter sib2, iclass 28, count 0 2006.203.07:40:12.65#ibcon#flushed, iclass 28, count 0 2006.203.07:40:12.65#ibcon#about to write, iclass 28, count 0 2006.203.07:40:12.65#ibcon#wrote, iclass 28, count 0 2006.203.07:40:12.65#ibcon#about to read 3, iclass 28, count 0 2006.203.07:40:12.69#ibcon#read 3, iclass 28, count 0 2006.203.07:40:12.69#ibcon#about to read 4, iclass 28, count 0 2006.203.07:40:12.69#ibcon#read 4, iclass 28, count 0 2006.203.07:40:12.69#ibcon#about to read 5, iclass 28, count 0 2006.203.07:40:12.69#ibcon#read 5, iclass 28, count 0 2006.203.07:40:12.69#ibcon#about to read 6, iclass 28, count 0 2006.203.07:40:12.69#ibcon#read 6, iclass 28, count 0 2006.203.07:40:12.69#ibcon#end of sib2, iclass 28, count 0 2006.203.07:40:12.69#ibcon#*after write, iclass 28, count 0 2006.203.07:40:12.69#ibcon#*before return 0, iclass 28, count 0 2006.203.07:40:12.69#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.203.07:40:12.69#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.203.07:40:12.69#ibcon#about to clear, iclass 28 cls_cnt 0 2006.203.07:40:12.69#ibcon#cleared, iclass 28 cls_cnt 0 2006.203.07:40:12.69$vc4f8/vb=4,4 2006.203.07:40:12.69#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.203.07:40:12.69#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.203.07:40:12.69#ibcon#ireg 11 cls_cnt 2 2006.203.07:40:12.69#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.203.07:40:12.75#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.203.07:40:12.75#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.203.07:40:12.75#ibcon#enter wrdev, iclass 30, count 2 2006.203.07:40:12.75#ibcon#first serial, iclass 30, count 2 2006.203.07:40:12.75#ibcon#enter sib2, iclass 30, count 2 2006.203.07:40:12.75#ibcon#flushed, iclass 30, count 2 2006.203.07:40:12.75#ibcon#about to write, iclass 30, count 2 2006.203.07:40:12.75#ibcon#wrote, iclass 30, count 2 2006.203.07:40:12.75#ibcon#about to read 3, iclass 30, count 2 2006.203.07:40:12.77#ibcon#read 3, iclass 30, count 2 2006.203.07:40:12.77#ibcon#about to read 4, iclass 30, count 2 2006.203.07:40:12.77#ibcon#read 4, iclass 30, count 2 2006.203.07:40:12.77#ibcon#about to read 5, iclass 30, count 2 2006.203.07:40:12.77#ibcon#read 5, iclass 30, count 2 2006.203.07:40:12.77#ibcon#about to read 6, iclass 30, count 2 2006.203.07:40:12.77#ibcon#read 6, iclass 30, count 2 2006.203.07:40:12.77#ibcon#end of sib2, iclass 30, count 2 2006.203.07:40:12.77#ibcon#*mode == 0, iclass 30, count 2 2006.203.07:40:12.77#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.203.07:40:12.77#ibcon#[27=AT04-04\r\n] 2006.203.07:40:12.77#ibcon#*before write, iclass 30, count 2 2006.203.07:40:12.77#ibcon#enter sib2, iclass 30, count 2 2006.203.07:40:12.77#ibcon#flushed, iclass 30, count 2 2006.203.07:40:12.77#ibcon#about to write, iclass 30, count 2 2006.203.07:40:12.77#ibcon#wrote, iclass 30, count 2 2006.203.07:40:12.77#ibcon#about to read 3, iclass 30, count 2 2006.203.07:40:12.80#ibcon#read 3, iclass 30, count 2 2006.203.07:40:12.80#ibcon#about to read 4, iclass 30, count 2 2006.203.07:40:12.80#ibcon#read 4, iclass 30, count 2 2006.203.07:40:12.80#ibcon#about to read 5, iclass 30, count 2 2006.203.07:40:12.80#ibcon#read 5, iclass 30, count 2 2006.203.07:40:12.80#ibcon#about to read 6, iclass 30, count 2 2006.203.07:40:12.80#ibcon#read 6, iclass 30, count 2 2006.203.07:40:12.80#ibcon#end of sib2, iclass 30, count 2 2006.203.07:40:12.80#ibcon#*after write, iclass 30, count 2 2006.203.07:40:12.80#ibcon#*before return 0, iclass 30, count 2 2006.203.07:40:12.80#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.203.07:40:12.80#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.203.07:40:12.80#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.203.07:40:12.80#ibcon#ireg 7 cls_cnt 0 2006.203.07:40:12.80#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.203.07:40:12.92#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.203.07:40:12.92#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.203.07:40:12.92#ibcon#enter wrdev, iclass 30, count 0 2006.203.07:40:12.92#ibcon#first serial, iclass 30, count 0 2006.203.07:40:12.92#ibcon#enter sib2, iclass 30, count 0 2006.203.07:40:12.92#ibcon#flushed, iclass 30, count 0 2006.203.07:40:12.92#ibcon#about to write, iclass 30, count 0 2006.203.07:40:12.92#ibcon#wrote, iclass 30, count 0 2006.203.07:40:12.92#ibcon#about to read 3, iclass 30, count 0 2006.203.07:40:12.94#ibcon#read 3, iclass 30, count 0 2006.203.07:40:12.94#ibcon#about to read 4, iclass 30, count 0 2006.203.07:40:12.94#ibcon#read 4, iclass 30, count 0 2006.203.07:40:12.94#ibcon#about to read 5, iclass 30, count 0 2006.203.07:40:12.94#ibcon#read 5, iclass 30, count 0 2006.203.07:40:12.94#ibcon#about to read 6, iclass 30, count 0 2006.203.07:40:12.94#ibcon#read 6, iclass 30, count 0 2006.203.07:40:12.94#ibcon#end of sib2, iclass 30, count 0 2006.203.07:40:12.94#ibcon#*mode == 0, iclass 30, count 0 2006.203.07:40:12.94#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.203.07:40:12.94#ibcon#[27=USB\r\n] 2006.203.07:40:12.94#ibcon#*before write, iclass 30, count 0 2006.203.07:40:12.94#ibcon#enter sib2, iclass 30, count 0 2006.203.07:40:12.94#ibcon#flushed, iclass 30, count 0 2006.203.07:40:12.94#ibcon#about to write, iclass 30, count 0 2006.203.07:40:12.94#ibcon#wrote, iclass 30, count 0 2006.203.07:40:12.94#ibcon#about to read 3, iclass 30, count 0 2006.203.07:40:12.97#ibcon#read 3, iclass 30, count 0 2006.203.07:40:12.97#ibcon#about to read 4, iclass 30, count 0 2006.203.07:40:12.97#ibcon#read 4, iclass 30, count 0 2006.203.07:40:12.97#ibcon#about to read 5, iclass 30, count 0 2006.203.07:40:12.97#ibcon#read 5, iclass 30, count 0 2006.203.07:40:12.97#ibcon#about to read 6, iclass 30, count 0 2006.203.07:40:12.97#ibcon#read 6, iclass 30, count 0 2006.203.07:40:12.97#ibcon#end of sib2, iclass 30, count 0 2006.203.07:40:12.97#ibcon#*after write, iclass 30, count 0 2006.203.07:40:12.97#ibcon#*before return 0, iclass 30, count 0 2006.203.07:40:12.97#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.203.07:40:12.97#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.203.07:40:12.97#ibcon#about to clear, iclass 30 cls_cnt 0 2006.203.07:40:12.97#ibcon#cleared, iclass 30 cls_cnt 0 2006.203.07:40:12.97$vc4f8/vblo=5,744.99 2006.203.07:40:12.97#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.203.07:40:12.97#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.203.07:40:12.97#ibcon#ireg 17 cls_cnt 0 2006.203.07:40:12.97#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.203.07:40:12.97#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.203.07:40:12.97#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.203.07:40:12.97#ibcon#enter wrdev, iclass 32, count 0 2006.203.07:40:12.97#ibcon#first serial, iclass 32, count 0 2006.203.07:40:12.97#ibcon#enter sib2, iclass 32, count 0 2006.203.07:40:12.97#ibcon#flushed, iclass 32, count 0 2006.203.07:40:12.97#ibcon#about to write, iclass 32, count 0 2006.203.07:40:12.97#ibcon#wrote, iclass 32, count 0 2006.203.07:40:12.97#ibcon#about to read 3, iclass 32, count 0 2006.203.07:40:13.00#ibcon#read 3, iclass 32, count 0 2006.203.07:40:13.00#ibcon#about to read 4, iclass 32, count 0 2006.203.07:40:13.00#ibcon#read 4, iclass 32, count 0 2006.203.07:40:13.00#ibcon#about to read 5, iclass 32, count 0 2006.203.07:40:13.00#ibcon#read 5, iclass 32, count 0 2006.203.07:40:13.00#ibcon#about to read 6, iclass 32, count 0 2006.203.07:40:13.00#ibcon#read 6, iclass 32, count 0 2006.203.07:40:13.00#ibcon#end of sib2, iclass 32, count 0 2006.203.07:40:13.00#ibcon#*mode == 0, iclass 32, count 0 2006.203.07:40:13.00#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.203.07:40:13.00#ibcon#[28=FRQ=05,744.99\r\n] 2006.203.07:40:13.00#ibcon#*before write, iclass 32, count 0 2006.203.07:40:13.00#ibcon#enter sib2, iclass 32, count 0 2006.203.07:40:13.00#ibcon#flushed, iclass 32, count 0 2006.203.07:40:13.00#ibcon#about to write, iclass 32, count 0 2006.203.07:40:13.00#ibcon#wrote, iclass 32, count 0 2006.203.07:40:13.00#ibcon#about to read 3, iclass 32, count 0 2006.203.07:40:13.04#ibcon#read 3, iclass 32, count 0 2006.203.07:40:13.04#ibcon#about to read 4, iclass 32, count 0 2006.203.07:40:13.04#ibcon#read 4, iclass 32, count 0 2006.203.07:40:13.04#ibcon#about to read 5, iclass 32, count 0 2006.203.07:40:13.04#ibcon#read 5, iclass 32, count 0 2006.203.07:40:13.04#ibcon#about to read 6, iclass 32, count 0 2006.203.07:40:13.04#ibcon#read 6, iclass 32, count 0 2006.203.07:40:13.04#ibcon#end of sib2, iclass 32, count 0 2006.203.07:40:13.04#ibcon#*after write, iclass 32, count 0 2006.203.07:40:13.04#ibcon#*before return 0, iclass 32, count 0 2006.203.07:40:13.04#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.203.07:40:13.04#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.203.07:40:13.04#ibcon#about to clear, iclass 32 cls_cnt 0 2006.203.07:40:13.04#ibcon#cleared, iclass 32 cls_cnt 0 2006.203.07:40:13.04$vc4f8/vb=5,3 2006.203.07:40:13.04#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.203.07:40:13.04#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.203.07:40:13.04#ibcon#ireg 11 cls_cnt 2 2006.203.07:40:13.04#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.203.07:40:13.09#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.203.07:40:13.09#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.203.07:40:13.09#ibcon#enter wrdev, iclass 34, count 2 2006.203.07:40:13.09#ibcon#first serial, iclass 34, count 2 2006.203.07:40:13.09#ibcon#enter sib2, iclass 34, count 2 2006.203.07:40:13.09#ibcon#flushed, iclass 34, count 2 2006.203.07:40:13.09#ibcon#about to write, iclass 34, count 2 2006.203.07:40:13.09#ibcon#wrote, iclass 34, count 2 2006.203.07:40:13.09#ibcon#about to read 3, iclass 34, count 2 2006.203.07:40:13.11#ibcon#read 3, iclass 34, count 2 2006.203.07:40:13.11#ibcon#about to read 4, iclass 34, count 2 2006.203.07:40:13.11#ibcon#read 4, iclass 34, count 2 2006.203.07:40:13.11#ibcon#about to read 5, iclass 34, count 2 2006.203.07:40:13.11#ibcon#read 5, iclass 34, count 2 2006.203.07:40:13.11#ibcon#about to read 6, iclass 34, count 2 2006.203.07:40:13.11#ibcon#read 6, iclass 34, count 2 2006.203.07:40:13.11#ibcon#end of sib2, iclass 34, count 2 2006.203.07:40:13.11#ibcon#*mode == 0, iclass 34, count 2 2006.203.07:40:13.11#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.203.07:40:13.11#ibcon#[27=AT05-03\r\n] 2006.203.07:40:13.11#ibcon#*before write, iclass 34, count 2 2006.203.07:40:13.11#ibcon#enter sib2, iclass 34, count 2 2006.203.07:40:13.11#ibcon#flushed, iclass 34, count 2 2006.203.07:40:13.11#ibcon#about to write, iclass 34, count 2 2006.203.07:40:13.11#ibcon#wrote, iclass 34, count 2 2006.203.07:40:13.11#ibcon#about to read 3, iclass 34, count 2 2006.203.07:40:13.14#ibcon#read 3, iclass 34, count 2 2006.203.07:40:13.14#ibcon#about to read 4, iclass 34, count 2 2006.203.07:40:13.14#ibcon#read 4, iclass 34, count 2 2006.203.07:40:13.14#ibcon#about to read 5, iclass 34, count 2 2006.203.07:40:13.14#ibcon#read 5, iclass 34, count 2 2006.203.07:40:13.14#ibcon#about to read 6, iclass 34, count 2 2006.203.07:40:13.14#ibcon#read 6, iclass 34, count 2 2006.203.07:40:13.14#ibcon#end of sib2, iclass 34, count 2 2006.203.07:40:13.14#ibcon#*after write, iclass 34, count 2 2006.203.07:40:13.14#ibcon#*before return 0, iclass 34, count 2 2006.203.07:40:13.14#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.203.07:40:13.14#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.203.07:40:13.14#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.203.07:40:13.14#ibcon#ireg 7 cls_cnt 0 2006.203.07:40:13.14#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.203.07:40:13.26#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.203.07:40:13.26#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.203.07:40:13.26#ibcon#enter wrdev, iclass 34, count 0 2006.203.07:40:13.26#ibcon#first serial, iclass 34, count 0 2006.203.07:40:13.26#ibcon#enter sib2, iclass 34, count 0 2006.203.07:40:13.26#ibcon#flushed, iclass 34, count 0 2006.203.07:40:13.26#ibcon#about to write, iclass 34, count 0 2006.203.07:40:13.26#ibcon#wrote, iclass 34, count 0 2006.203.07:40:13.26#ibcon#about to read 3, iclass 34, count 0 2006.203.07:40:13.28#ibcon#read 3, iclass 34, count 0 2006.203.07:40:13.28#ibcon#about to read 4, iclass 34, count 0 2006.203.07:40:13.28#ibcon#read 4, iclass 34, count 0 2006.203.07:40:13.28#ibcon#about to read 5, iclass 34, count 0 2006.203.07:40:13.28#ibcon#read 5, iclass 34, count 0 2006.203.07:40:13.28#ibcon#about to read 6, iclass 34, count 0 2006.203.07:40:13.28#ibcon#read 6, iclass 34, count 0 2006.203.07:40:13.28#ibcon#end of sib2, iclass 34, count 0 2006.203.07:40:13.28#ibcon#*mode == 0, iclass 34, count 0 2006.203.07:40:13.28#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.203.07:40:13.28#ibcon#[27=USB\r\n] 2006.203.07:40:13.28#ibcon#*before write, iclass 34, count 0 2006.203.07:40:13.28#ibcon#enter sib2, iclass 34, count 0 2006.203.07:40:13.28#ibcon#flushed, iclass 34, count 0 2006.203.07:40:13.28#ibcon#about to write, iclass 34, count 0 2006.203.07:40:13.28#ibcon#wrote, iclass 34, count 0 2006.203.07:40:13.28#ibcon#about to read 3, iclass 34, count 0 2006.203.07:40:13.31#ibcon#read 3, iclass 34, count 0 2006.203.07:40:13.31#ibcon#about to read 4, iclass 34, count 0 2006.203.07:40:13.31#ibcon#read 4, iclass 34, count 0 2006.203.07:40:13.31#ibcon#about to read 5, iclass 34, count 0 2006.203.07:40:13.31#ibcon#read 5, iclass 34, count 0 2006.203.07:40:13.31#ibcon#about to read 6, iclass 34, count 0 2006.203.07:40:13.31#ibcon#read 6, iclass 34, count 0 2006.203.07:40:13.31#ibcon#end of sib2, iclass 34, count 0 2006.203.07:40:13.31#ibcon#*after write, iclass 34, count 0 2006.203.07:40:13.31#ibcon#*before return 0, iclass 34, count 0 2006.203.07:40:13.31#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.203.07:40:13.31#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.203.07:40:13.31#ibcon#about to clear, iclass 34 cls_cnt 0 2006.203.07:40:13.31#ibcon#cleared, iclass 34 cls_cnt 0 2006.203.07:40:13.31$vc4f8/vblo=6,752.99 2006.203.07:40:13.31#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.203.07:40:13.31#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.203.07:40:13.31#ibcon#ireg 17 cls_cnt 0 2006.203.07:40:13.31#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.203.07:40:13.31#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.203.07:40:13.31#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.203.07:40:13.31#ibcon#enter wrdev, iclass 36, count 0 2006.203.07:40:13.31#ibcon#first serial, iclass 36, count 0 2006.203.07:40:13.31#ibcon#enter sib2, iclass 36, count 0 2006.203.07:40:13.31#ibcon#flushed, iclass 36, count 0 2006.203.07:40:13.31#ibcon#about to write, iclass 36, count 0 2006.203.07:40:13.31#ibcon#wrote, iclass 36, count 0 2006.203.07:40:13.31#ibcon#about to read 3, iclass 36, count 0 2006.203.07:40:13.33#ibcon#read 3, iclass 36, count 0 2006.203.07:40:13.33#ibcon#about to read 4, iclass 36, count 0 2006.203.07:40:13.33#ibcon#read 4, iclass 36, count 0 2006.203.07:40:13.33#ibcon#about to read 5, iclass 36, count 0 2006.203.07:40:13.33#ibcon#read 5, iclass 36, count 0 2006.203.07:40:13.33#ibcon#about to read 6, iclass 36, count 0 2006.203.07:40:13.33#ibcon#read 6, iclass 36, count 0 2006.203.07:40:13.33#ibcon#end of sib2, iclass 36, count 0 2006.203.07:40:13.33#ibcon#*mode == 0, iclass 36, count 0 2006.203.07:40:13.33#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.203.07:40:13.33#ibcon#[28=FRQ=06,752.99\r\n] 2006.203.07:40:13.33#ibcon#*before write, iclass 36, count 0 2006.203.07:40:13.33#ibcon#enter sib2, iclass 36, count 0 2006.203.07:40:13.33#ibcon#flushed, iclass 36, count 0 2006.203.07:40:13.33#ibcon#about to write, iclass 36, count 0 2006.203.07:40:13.33#ibcon#wrote, iclass 36, count 0 2006.203.07:40:13.33#ibcon#about to read 3, iclass 36, count 0 2006.203.07:40:13.37#ibcon#read 3, iclass 36, count 0 2006.203.07:40:13.37#ibcon#about to read 4, iclass 36, count 0 2006.203.07:40:13.37#ibcon#read 4, iclass 36, count 0 2006.203.07:40:13.37#ibcon#about to read 5, iclass 36, count 0 2006.203.07:40:13.37#ibcon#read 5, iclass 36, count 0 2006.203.07:40:13.37#ibcon#about to read 6, iclass 36, count 0 2006.203.07:40:13.37#ibcon#read 6, iclass 36, count 0 2006.203.07:40:13.37#ibcon#end of sib2, iclass 36, count 0 2006.203.07:40:13.37#ibcon#*after write, iclass 36, count 0 2006.203.07:40:13.37#ibcon#*before return 0, iclass 36, count 0 2006.203.07:40:13.37#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.203.07:40:13.37#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.203.07:40:13.37#ibcon#about to clear, iclass 36 cls_cnt 0 2006.203.07:40:13.37#ibcon#cleared, iclass 36 cls_cnt 0 2006.203.07:40:13.37$vc4f8/vb=6,4 2006.203.07:40:13.37#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.203.07:40:13.37#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.203.07:40:13.37#ibcon#ireg 11 cls_cnt 2 2006.203.07:40:13.37#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.203.07:40:13.43#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.203.07:40:13.43#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.203.07:40:13.43#ibcon#enter wrdev, iclass 38, count 2 2006.203.07:40:13.43#ibcon#first serial, iclass 38, count 2 2006.203.07:40:13.43#ibcon#enter sib2, iclass 38, count 2 2006.203.07:40:13.43#ibcon#flushed, iclass 38, count 2 2006.203.07:40:13.43#ibcon#about to write, iclass 38, count 2 2006.203.07:40:13.43#ibcon#wrote, iclass 38, count 2 2006.203.07:40:13.43#ibcon#about to read 3, iclass 38, count 2 2006.203.07:40:13.45#ibcon#read 3, iclass 38, count 2 2006.203.07:40:13.45#ibcon#about to read 4, iclass 38, count 2 2006.203.07:40:13.45#ibcon#read 4, iclass 38, count 2 2006.203.07:40:13.45#ibcon#about to read 5, iclass 38, count 2 2006.203.07:40:13.45#ibcon#read 5, iclass 38, count 2 2006.203.07:40:13.45#ibcon#about to read 6, iclass 38, count 2 2006.203.07:40:13.45#ibcon#read 6, iclass 38, count 2 2006.203.07:40:13.45#ibcon#end of sib2, iclass 38, count 2 2006.203.07:40:13.45#ibcon#*mode == 0, iclass 38, count 2 2006.203.07:40:13.45#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.203.07:40:13.45#ibcon#[27=AT06-04\r\n] 2006.203.07:40:13.45#ibcon#*before write, iclass 38, count 2 2006.203.07:40:13.45#ibcon#enter sib2, iclass 38, count 2 2006.203.07:40:13.45#ibcon#flushed, iclass 38, count 2 2006.203.07:40:13.45#ibcon#about to write, iclass 38, count 2 2006.203.07:40:13.45#ibcon#wrote, iclass 38, count 2 2006.203.07:40:13.45#ibcon#about to read 3, iclass 38, count 2 2006.203.07:40:13.48#ibcon#read 3, iclass 38, count 2 2006.203.07:40:13.48#ibcon#about to read 4, iclass 38, count 2 2006.203.07:40:13.48#ibcon#read 4, iclass 38, count 2 2006.203.07:40:13.48#ibcon#about to read 5, iclass 38, count 2 2006.203.07:40:13.48#ibcon#read 5, iclass 38, count 2 2006.203.07:40:13.48#ibcon#about to read 6, iclass 38, count 2 2006.203.07:40:13.48#ibcon#read 6, iclass 38, count 2 2006.203.07:40:13.48#ibcon#end of sib2, iclass 38, count 2 2006.203.07:40:13.48#ibcon#*after write, iclass 38, count 2 2006.203.07:40:13.48#ibcon#*before return 0, iclass 38, count 2 2006.203.07:40:13.48#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.203.07:40:13.48#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.203.07:40:13.48#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.203.07:40:13.48#ibcon#ireg 7 cls_cnt 0 2006.203.07:40:13.48#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.203.07:40:13.60#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.203.07:40:13.60#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.203.07:40:13.60#ibcon#enter wrdev, iclass 38, count 0 2006.203.07:40:13.60#ibcon#first serial, iclass 38, count 0 2006.203.07:40:13.60#ibcon#enter sib2, iclass 38, count 0 2006.203.07:40:13.60#ibcon#flushed, iclass 38, count 0 2006.203.07:40:13.60#ibcon#about to write, iclass 38, count 0 2006.203.07:40:13.60#ibcon#wrote, iclass 38, count 0 2006.203.07:40:13.60#ibcon#about to read 3, iclass 38, count 0 2006.203.07:40:13.62#ibcon#read 3, iclass 38, count 0 2006.203.07:40:13.62#ibcon#about to read 4, iclass 38, count 0 2006.203.07:40:13.62#ibcon#read 4, iclass 38, count 0 2006.203.07:40:13.62#ibcon#about to read 5, iclass 38, count 0 2006.203.07:40:13.62#ibcon#read 5, iclass 38, count 0 2006.203.07:40:13.62#ibcon#about to read 6, iclass 38, count 0 2006.203.07:40:13.62#ibcon#read 6, iclass 38, count 0 2006.203.07:40:13.62#ibcon#end of sib2, iclass 38, count 0 2006.203.07:40:13.62#ibcon#*mode == 0, iclass 38, count 0 2006.203.07:40:13.62#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.203.07:40:13.62#ibcon#[27=USB\r\n] 2006.203.07:40:13.62#ibcon#*before write, iclass 38, count 0 2006.203.07:40:13.62#ibcon#enter sib2, iclass 38, count 0 2006.203.07:40:13.62#ibcon#flushed, iclass 38, count 0 2006.203.07:40:13.62#ibcon#about to write, iclass 38, count 0 2006.203.07:40:13.62#ibcon#wrote, iclass 38, count 0 2006.203.07:40:13.62#ibcon#about to read 3, iclass 38, count 0 2006.203.07:40:13.65#ibcon#read 3, iclass 38, count 0 2006.203.07:40:13.65#ibcon#about to read 4, iclass 38, count 0 2006.203.07:40:13.65#ibcon#read 4, iclass 38, count 0 2006.203.07:40:13.65#ibcon#about to read 5, iclass 38, count 0 2006.203.07:40:13.65#ibcon#read 5, iclass 38, count 0 2006.203.07:40:13.65#ibcon#about to read 6, iclass 38, count 0 2006.203.07:40:13.65#ibcon#read 6, iclass 38, count 0 2006.203.07:40:13.65#ibcon#end of sib2, iclass 38, count 0 2006.203.07:40:13.65#ibcon#*after write, iclass 38, count 0 2006.203.07:40:13.65#ibcon#*before return 0, iclass 38, count 0 2006.203.07:40:13.65#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.203.07:40:13.65#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.203.07:40:13.65#ibcon#about to clear, iclass 38 cls_cnt 0 2006.203.07:40:13.65#ibcon#cleared, iclass 38 cls_cnt 0 2006.203.07:40:13.65$vc4f8/vabw=wide 2006.203.07:40:13.65#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.203.07:40:13.65#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.203.07:40:13.65#ibcon#ireg 8 cls_cnt 0 2006.203.07:40:13.65#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.203.07:40:13.65#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.203.07:40:13.65#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.203.07:40:13.65#ibcon#enter wrdev, iclass 40, count 0 2006.203.07:40:13.65#ibcon#first serial, iclass 40, count 0 2006.203.07:40:13.65#ibcon#enter sib2, iclass 40, count 0 2006.203.07:40:13.65#ibcon#flushed, iclass 40, count 0 2006.203.07:40:13.65#ibcon#about to write, iclass 40, count 0 2006.203.07:40:13.65#ibcon#wrote, iclass 40, count 0 2006.203.07:40:13.65#ibcon#about to read 3, iclass 40, count 0 2006.203.07:40:13.67#ibcon#read 3, iclass 40, count 0 2006.203.07:40:13.67#ibcon#about to read 4, iclass 40, count 0 2006.203.07:40:13.67#ibcon#read 4, iclass 40, count 0 2006.203.07:40:13.67#ibcon#about to read 5, iclass 40, count 0 2006.203.07:40:13.67#ibcon#read 5, iclass 40, count 0 2006.203.07:40:13.67#ibcon#about to read 6, iclass 40, count 0 2006.203.07:40:13.67#ibcon#read 6, iclass 40, count 0 2006.203.07:40:13.67#ibcon#end of sib2, iclass 40, count 0 2006.203.07:40:13.67#ibcon#*mode == 0, iclass 40, count 0 2006.203.07:40:13.67#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.203.07:40:13.67#ibcon#[25=BW32\r\n] 2006.203.07:40:13.67#ibcon#*before write, iclass 40, count 0 2006.203.07:40:13.67#ibcon#enter sib2, iclass 40, count 0 2006.203.07:40:13.67#ibcon#flushed, iclass 40, count 0 2006.203.07:40:13.67#ibcon#about to write, iclass 40, count 0 2006.203.07:40:13.67#ibcon#wrote, iclass 40, count 0 2006.203.07:40:13.67#ibcon#about to read 3, iclass 40, count 0 2006.203.07:40:13.70#ibcon#read 3, iclass 40, count 0 2006.203.07:40:13.70#ibcon#about to read 4, iclass 40, count 0 2006.203.07:40:13.70#ibcon#read 4, iclass 40, count 0 2006.203.07:40:13.70#ibcon#about to read 5, iclass 40, count 0 2006.203.07:40:13.70#ibcon#read 5, iclass 40, count 0 2006.203.07:40:13.70#ibcon#about to read 6, iclass 40, count 0 2006.203.07:40:13.70#ibcon#read 6, iclass 40, count 0 2006.203.07:40:13.70#ibcon#end of sib2, iclass 40, count 0 2006.203.07:40:13.70#ibcon#*after write, iclass 40, count 0 2006.203.07:40:13.70#ibcon#*before return 0, iclass 40, count 0 2006.203.07:40:13.70#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.203.07:40:13.70#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.203.07:40:13.70#ibcon#about to clear, iclass 40 cls_cnt 0 2006.203.07:40:13.70#ibcon#cleared, iclass 40 cls_cnt 0 2006.203.07:40:13.70$vc4f8/vbbw=wide 2006.203.07:40:13.70#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.203.07:40:13.70#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.203.07:40:13.70#ibcon#ireg 8 cls_cnt 0 2006.203.07:40:13.70#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.203.07:40:13.77#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.203.07:40:13.77#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.203.07:40:13.77#ibcon#enter wrdev, iclass 4, count 0 2006.203.07:40:13.77#ibcon#first serial, iclass 4, count 0 2006.203.07:40:13.77#ibcon#enter sib2, iclass 4, count 0 2006.203.07:40:13.77#ibcon#flushed, iclass 4, count 0 2006.203.07:40:13.77#ibcon#about to write, iclass 4, count 0 2006.203.07:40:13.77#ibcon#wrote, iclass 4, count 0 2006.203.07:40:13.77#ibcon#about to read 3, iclass 4, count 0 2006.203.07:40:13.79#ibcon#read 3, iclass 4, count 0 2006.203.07:40:13.79#ibcon#about to read 4, iclass 4, count 0 2006.203.07:40:13.79#ibcon#read 4, iclass 4, count 0 2006.203.07:40:13.79#ibcon#about to read 5, iclass 4, count 0 2006.203.07:40:13.79#ibcon#read 5, iclass 4, count 0 2006.203.07:40:13.79#ibcon#about to read 6, iclass 4, count 0 2006.203.07:40:13.79#ibcon#read 6, iclass 4, count 0 2006.203.07:40:13.79#ibcon#end of sib2, iclass 4, count 0 2006.203.07:40:13.79#ibcon#*mode == 0, iclass 4, count 0 2006.203.07:40:13.79#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.203.07:40:13.79#ibcon#[27=BW32\r\n] 2006.203.07:40:13.79#ibcon#*before write, iclass 4, count 0 2006.203.07:40:13.79#ibcon#enter sib2, iclass 4, count 0 2006.203.07:40:13.79#ibcon#flushed, iclass 4, count 0 2006.203.07:40:13.79#ibcon#about to write, iclass 4, count 0 2006.203.07:40:13.79#ibcon#wrote, iclass 4, count 0 2006.203.07:40:13.79#ibcon#about to read 3, iclass 4, count 0 2006.203.07:40:13.82#ibcon#read 3, iclass 4, count 0 2006.203.07:40:13.82#ibcon#about to read 4, iclass 4, count 0 2006.203.07:40:13.82#ibcon#read 4, iclass 4, count 0 2006.203.07:40:13.82#ibcon#about to read 5, iclass 4, count 0 2006.203.07:40:13.82#ibcon#read 5, iclass 4, count 0 2006.203.07:40:13.82#ibcon#about to read 6, iclass 4, count 0 2006.203.07:40:13.82#ibcon#read 6, iclass 4, count 0 2006.203.07:40:13.82#ibcon#end of sib2, iclass 4, count 0 2006.203.07:40:13.82#ibcon#*after write, iclass 4, count 0 2006.203.07:40:13.82#ibcon#*before return 0, iclass 4, count 0 2006.203.07:40:13.82#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.203.07:40:13.82#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.203.07:40:13.82#ibcon#about to clear, iclass 4 cls_cnt 0 2006.203.07:40:13.82#ibcon#cleared, iclass 4 cls_cnt 0 2006.203.07:40:13.82$4f8m12a/ifd4f 2006.203.07:40:13.82$ifd4f/lo= 2006.203.07:40:13.82$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.203.07:40:13.82$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.203.07:40:13.82$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.203.07:40:13.82$ifd4f/patch= 2006.203.07:40:13.82$ifd4f/patch=lo1,a1,a2,a3,a4 2006.203.07:40:13.82$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.203.07:40:13.82$ifd4f/patch=lo3,a5,a6,a7,a8 2006.203.07:40:13.82$4f8m12a/"form=m,16.000,1:2 2006.203.07:40:13.82$4f8m12a/"tpicd 2006.203.07:40:13.82$4f8m12a/echo=off 2006.203.07:40:13.82$4f8m12a/xlog=off 2006.203.07:40:13.82:!2006.203.07:40:40 2006.203.07:40:20.14#trakl#Source acquired 2006.203.07:40:22.14#flagr#flagr/antenna,acquired 2006.203.07:40:40.00:preob 2006.203.07:40:41.14/onsource/TRACKING 2006.203.07:40:41.14:!2006.203.07:40:50 2006.203.07:40:50.00:data_valid=on 2006.203.07:40:50.00:midob 2006.203.07:40:50.14/onsource/TRACKING 2006.203.07:40:50.14/wx/23.95,1001.0,97 2006.203.07:40:50.35/cable/+6.4588E-03 2006.203.07:40:51.44/va/01,08,usb,yes,30,31 2006.203.07:40:51.44/va/02,07,usb,yes,30,31 2006.203.07:40:51.44/va/03,08,usb,yes,22,23 2006.203.07:40:51.44/va/04,07,usb,yes,31,33 2006.203.07:40:51.44/va/05,07,usb,yes,33,35 2006.203.07:40:51.44/va/06,06,usb,yes,32,32 2006.203.07:40:51.44/va/07,07,usb,yes,28,28 2006.203.07:40:51.44/va/08,06,usb,yes,35,34 2006.203.07:40:51.67/valo/01,532.99,yes,locked 2006.203.07:40:51.67/valo/02,572.99,yes,locked 2006.203.07:40:51.67/valo/03,672.99,yes,locked 2006.203.07:40:51.67/valo/04,832.99,yes,locked 2006.203.07:40:51.67/valo/05,652.99,yes,locked 2006.203.07:40:51.67/valo/06,772.99,yes,locked 2006.203.07:40:51.67/valo/07,832.99,yes,locked 2006.203.07:40:51.67/valo/08,852.99,yes,locked 2006.203.07:40:52.76/vb/01,04,usb,yes,29,28 2006.203.07:40:52.76/vb/02,04,usb,yes,31,32 2006.203.07:40:52.76/vb/03,04,usb,yes,27,31 2006.203.07:40:52.76/vb/04,04,usb,yes,28,28 2006.203.07:40:52.76/vb/05,03,usb,yes,33,38 2006.203.07:40:52.76/vb/06,04,usb,yes,28,30 2006.203.07:40:52.76/vb/07,04,usb,yes,30,29 2006.203.07:40:52.76/vb/08,04,usb,yes,27,31 2006.203.07:40:52.99/vblo/01,632.99,yes,locked 2006.203.07:40:52.99/vblo/02,640.99,yes,locked 2006.203.07:40:52.99/vblo/03,656.99,yes,locked 2006.203.07:40:52.99/vblo/04,712.99,yes,locked 2006.203.07:40:52.99/vblo/05,744.99,yes,locked 2006.203.07:40:52.99/vblo/06,752.99,yes,locked 2006.203.07:40:52.99/vblo/07,734.99,yes,locked 2006.203.07:40:52.99/vblo/08,744.99,yes,locked 2006.203.07:40:53.14/vabw/8 2006.203.07:40:53.29/vbbw/8 2006.203.07:40:53.38/xfe/off,on,16.5 2006.203.07:40:53.76/ifatt/23,28,28,28 2006.203.07:40:54.07/fmout-gps/S +4.55E-07 2006.203.07:40:54.15:!2006.203.07:41:50 2006.203.07:41:50.00:data_valid=off 2006.203.07:41:50.01:postob 2006.203.07:41:50.06/cable/+6.4596E-03 2006.203.07:41:50.07/wx/23.93,1001.0,97 2006.203.07:41:51.07/fmout-gps/S +4.54E-07 2006.203.07:41:51.08:scan_name=203-0742,k06203,60 2006.203.07:41:51.08:source=1803+784,180045.68,782804.0,2000.0,cw 2006.203.07:41:51.14#flagr#flagr/antenna,new-source 2006.203.07:41:52.14:checkk5 2006.203.07:41:52.69/chk_autoobs//k5ts1/ autoobs is running! 2006.203.07:41:53.11/chk_autoobs//k5ts2/ autoobs is running! 2006.203.07:41:53.53/chk_autoobs//k5ts3/ autoobs is running! 2006.203.07:41:53.92/chk_autoobs//k5ts4/ autoobs is running! 2006.203.07:41:54.46/chk_obsdata//k5ts1/T2030740??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.07:41:54.87/chk_obsdata//k5ts2/T2030740??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.07:41:55.77/chk_obsdata//k5ts3/T2030740??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.07:41:56.22/chk_obsdata//k5ts4/T2030740??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.07:41:57.02/k5log//k5ts1_log_newline 2006.203.07:41:57.82/k5log//k5ts2_log_newline 2006.203.07:41:58.63/k5log//k5ts3_log_newline 2006.203.07:41:59.38/k5log//k5ts4_log_newline 2006.203.07:41:59.40/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.203.07:41:59.40:4f8m12a=1 2006.203.07:41:59.40$4f8m12a/echo=on 2006.203.07:41:59.40$4f8m12a/pcalon 2006.203.07:41:59.40$pcalon/"no phase cal control is implemented here 2006.203.07:41:59.40$4f8m12a/"tpicd=stop 2006.203.07:41:59.40$4f8m12a/vc4f8 2006.203.07:41:59.41$vc4f8/valo=1,532.99 2006.203.07:41:59.41#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.203.07:41:59.41#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.203.07:41:59.41#ibcon#ireg 17 cls_cnt 0 2006.203.07:41:59.41#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.203.07:41:59.41#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.203.07:41:59.41#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.203.07:41:59.41#ibcon#enter wrdev, iclass 17, count 0 2006.203.07:41:59.41#ibcon#first serial, iclass 17, count 0 2006.203.07:41:59.41#ibcon#enter sib2, iclass 17, count 0 2006.203.07:41:59.41#ibcon#flushed, iclass 17, count 0 2006.203.07:41:59.41#ibcon#about to write, iclass 17, count 0 2006.203.07:41:59.41#ibcon#wrote, iclass 17, count 0 2006.203.07:41:59.41#ibcon#about to read 3, iclass 17, count 0 2006.203.07:41:59.45#ibcon#read 3, iclass 17, count 0 2006.203.07:41:59.45#ibcon#about to read 4, iclass 17, count 0 2006.203.07:41:59.45#ibcon#read 4, iclass 17, count 0 2006.203.07:41:59.45#ibcon#about to read 5, iclass 17, count 0 2006.203.07:41:59.45#ibcon#read 5, iclass 17, count 0 2006.203.07:41:59.45#ibcon#about to read 6, iclass 17, count 0 2006.203.07:41:59.45#ibcon#read 6, iclass 17, count 0 2006.203.07:41:59.45#ibcon#end of sib2, iclass 17, count 0 2006.203.07:41:59.45#ibcon#*mode == 0, iclass 17, count 0 2006.203.07:41:59.45#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.203.07:41:59.45#ibcon#[26=FRQ=01,532.99\r\n] 2006.203.07:41:59.45#ibcon#*before write, iclass 17, count 0 2006.203.07:41:59.45#ibcon#enter sib2, iclass 17, count 0 2006.203.07:41:59.45#ibcon#flushed, iclass 17, count 0 2006.203.07:41:59.45#ibcon#about to write, iclass 17, count 0 2006.203.07:41:59.45#ibcon#wrote, iclass 17, count 0 2006.203.07:41:59.45#ibcon#about to read 3, iclass 17, count 0 2006.203.07:41:59.50#ibcon#read 3, iclass 17, count 0 2006.203.07:41:59.50#ibcon#about to read 4, iclass 17, count 0 2006.203.07:41:59.50#ibcon#read 4, iclass 17, count 0 2006.203.07:41:59.50#ibcon#about to read 5, iclass 17, count 0 2006.203.07:41:59.50#ibcon#read 5, iclass 17, count 0 2006.203.07:41:59.50#ibcon#about to read 6, iclass 17, count 0 2006.203.07:41:59.50#ibcon#read 6, iclass 17, count 0 2006.203.07:41:59.50#ibcon#end of sib2, iclass 17, count 0 2006.203.07:41:59.50#ibcon#*after write, iclass 17, count 0 2006.203.07:41:59.50#ibcon#*before return 0, iclass 17, count 0 2006.203.07:41:59.50#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.203.07:41:59.50#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.203.07:41:59.50#ibcon#about to clear, iclass 17 cls_cnt 0 2006.203.07:41:59.50#ibcon#cleared, iclass 17 cls_cnt 0 2006.203.07:41:59.50$vc4f8/va=1,8 2006.203.07:41:59.50#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.203.07:41:59.50#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.203.07:41:59.50#ibcon#ireg 11 cls_cnt 2 2006.203.07:41:59.50#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.203.07:41:59.50#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.203.07:41:59.50#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.203.07:41:59.50#ibcon#enter wrdev, iclass 19, count 2 2006.203.07:41:59.50#ibcon#first serial, iclass 19, count 2 2006.203.07:41:59.50#ibcon#enter sib2, iclass 19, count 2 2006.203.07:41:59.50#ibcon#flushed, iclass 19, count 2 2006.203.07:41:59.50#ibcon#about to write, iclass 19, count 2 2006.203.07:41:59.50#ibcon#wrote, iclass 19, count 2 2006.203.07:41:59.50#ibcon#about to read 3, iclass 19, count 2 2006.203.07:41:59.53#ibcon#read 3, iclass 19, count 2 2006.203.07:41:59.53#ibcon#about to read 4, iclass 19, count 2 2006.203.07:41:59.53#ibcon#read 4, iclass 19, count 2 2006.203.07:41:59.53#ibcon#about to read 5, iclass 19, count 2 2006.203.07:41:59.53#ibcon#read 5, iclass 19, count 2 2006.203.07:41:59.53#ibcon#about to read 6, iclass 19, count 2 2006.203.07:41:59.53#ibcon#read 6, iclass 19, count 2 2006.203.07:41:59.53#ibcon#end of sib2, iclass 19, count 2 2006.203.07:41:59.53#ibcon#*mode == 0, iclass 19, count 2 2006.203.07:41:59.53#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.203.07:41:59.53#ibcon#[25=AT01-08\r\n] 2006.203.07:41:59.53#ibcon#*before write, iclass 19, count 2 2006.203.07:41:59.53#ibcon#enter sib2, iclass 19, count 2 2006.203.07:41:59.53#ibcon#flushed, iclass 19, count 2 2006.203.07:41:59.53#ibcon#about to write, iclass 19, count 2 2006.203.07:41:59.53#ibcon#wrote, iclass 19, count 2 2006.203.07:41:59.53#ibcon#about to read 3, iclass 19, count 2 2006.203.07:41:59.56#ibcon#read 3, iclass 19, count 2 2006.203.07:41:59.56#ibcon#about to read 4, iclass 19, count 2 2006.203.07:41:59.56#ibcon#read 4, iclass 19, count 2 2006.203.07:41:59.56#ibcon#about to read 5, iclass 19, count 2 2006.203.07:41:59.56#ibcon#read 5, iclass 19, count 2 2006.203.07:41:59.56#ibcon#about to read 6, iclass 19, count 2 2006.203.07:41:59.56#ibcon#read 6, iclass 19, count 2 2006.203.07:41:59.56#ibcon#end of sib2, iclass 19, count 2 2006.203.07:41:59.56#ibcon#*after write, iclass 19, count 2 2006.203.07:41:59.56#ibcon#*before return 0, iclass 19, count 2 2006.203.07:41:59.56#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.203.07:41:59.56#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.203.07:41:59.56#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.203.07:41:59.56#ibcon#ireg 7 cls_cnt 0 2006.203.07:41:59.56#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.203.07:41:59.68#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.203.07:41:59.68#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.203.07:41:59.68#ibcon#enter wrdev, iclass 19, count 0 2006.203.07:41:59.68#ibcon#first serial, iclass 19, count 0 2006.203.07:41:59.68#ibcon#enter sib2, iclass 19, count 0 2006.203.07:41:59.68#ibcon#flushed, iclass 19, count 0 2006.203.07:41:59.68#ibcon#about to write, iclass 19, count 0 2006.203.07:41:59.68#ibcon#wrote, iclass 19, count 0 2006.203.07:41:59.68#ibcon#about to read 3, iclass 19, count 0 2006.203.07:41:59.70#ibcon#read 3, iclass 19, count 0 2006.203.07:41:59.70#ibcon#about to read 4, iclass 19, count 0 2006.203.07:41:59.70#ibcon#read 4, iclass 19, count 0 2006.203.07:41:59.70#ibcon#about to read 5, iclass 19, count 0 2006.203.07:41:59.70#ibcon#read 5, iclass 19, count 0 2006.203.07:41:59.70#ibcon#about to read 6, iclass 19, count 0 2006.203.07:41:59.70#ibcon#read 6, iclass 19, count 0 2006.203.07:41:59.70#ibcon#end of sib2, iclass 19, count 0 2006.203.07:41:59.70#ibcon#*mode == 0, iclass 19, count 0 2006.203.07:41:59.70#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.203.07:41:59.70#ibcon#[25=USB\r\n] 2006.203.07:41:59.70#ibcon#*before write, iclass 19, count 0 2006.203.07:41:59.70#ibcon#enter sib2, iclass 19, count 0 2006.203.07:41:59.70#ibcon#flushed, iclass 19, count 0 2006.203.07:41:59.70#ibcon#about to write, iclass 19, count 0 2006.203.07:41:59.70#ibcon#wrote, iclass 19, count 0 2006.203.07:41:59.70#ibcon#about to read 3, iclass 19, count 0 2006.203.07:41:59.73#ibcon#read 3, iclass 19, count 0 2006.203.07:41:59.73#ibcon#about to read 4, iclass 19, count 0 2006.203.07:41:59.73#ibcon#read 4, iclass 19, count 0 2006.203.07:41:59.73#ibcon#about to read 5, iclass 19, count 0 2006.203.07:41:59.73#ibcon#read 5, iclass 19, count 0 2006.203.07:41:59.73#ibcon#about to read 6, iclass 19, count 0 2006.203.07:41:59.73#ibcon#read 6, iclass 19, count 0 2006.203.07:41:59.73#ibcon#end of sib2, iclass 19, count 0 2006.203.07:41:59.73#ibcon#*after write, iclass 19, count 0 2006.203.07:41:59.73#ibcon#*before return 0, iclass 19, count 0 2006.203.07:41:59.73#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.203.07:41:59.73#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.203.07:41:59.73#ibcon#about to clear, iclass 19 cls_cnt 0 2006.203.07:41:59.73#ibcon#cleared, iclass 19 cls_cnt 0 2006.203.07:41:59.73$vc4f8/valo=2,572.99 2006.203.07:41:59.73#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.203.07:41:59.73#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.203.07:41:59.73#ibcon#ireg 17 cls_cnt 0 2006.203.07:41:59.73#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.203.07:41:59.73#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.203.07:41:59.73#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.203.07:41:59.73#ibcon#enter wrdev, iclass 21, count 0 2006.203.07:41:59.73#ibcon#first serial, iclass 21, count 0 2006.203.07:41:59.73#ibcon#enter sib2, iclass 21, count 0 2006.203.07:41:59.73#ibcon#flushed, iclass 21, count 0 2006.203.07:41:59.73#ibcon#about to write, iclass 21, count 0 2006.203.07:41:59.73#ibcon#wrote, iclass 21, count 0 2006.203.07:41:59.73#ibcon#about to read 3, iclass 21, count 0 2006.203.07:41:59.76#ibcon#read 3, iclass 21, count 0 2006.203.07:41:59.76#ibcon#about to read 4, iclass 21, count 0 2006.203.07:41:59.76#ibcon#read 4, iclass 21, count 0 2006.203.07:41:59.76#ibcon#about to read 5, iclass 21, count 0 2006.203.07:41:59.76#ibcon#read 5, iclass 21, count 0 2006.203.07:41:59.76#ibcon#about to read 6, iclass 21, count 0 2006.203.07:41:59.76#ibcon#read 6, iclass 21, count 0 2006.203.07:41:59.76#ibcon#end of sib2, iclass 21, count 0 2006.203.07:41:59.76#ibcon#*mode == 0, iclass 21, count 0 2006.203.07:41:59.76#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.203.07:41:59.76#ibcon#[26=FRQ=02,572.99\r\n] 2006.203.07:41:59.76#ibcon#*before write, iclass 21, count 0 2006.203.07:41:59.76#ibcon#enter sib2, iclass 21, count 0 2006.203.07:41:59.76#ibcon#flushed, iclass 21, count 0 2006.203.07:41:59.76#ibcon#about to write, iclass 21, count 0 2006.203.07:41:59.76#ibcon#wrote, iclass 21, count 0 2006.203.07:41:59.76#ibcon#about to read 3, iclass 21, count 0 2006.203.07:41:59.80#ibcon#read 3, iclass 21, count 0 2006.203.07:41:59.80#ibcon#about to read 4, iclass 21, count 0 2006.203.07:41:59.80#ibcon#read 4, iclass 21, count 0 2006.203.07:41:59.80#ibcon#about to read 5, iclass 21, count 0 2006.203.07:41:59.80#ibcon#read 5, iclass 21, count 0 2006.203.07:41:59.80#ibcon#about to read 6, iclass 21, count 0 2006.203.07:41:59.80#ibcon#read 6, iclass 21, count 0 2006.203.07:41:59.80#ibcon#end of sib2, iclass 21, count 0 2006.203.07:41:59.80#ibcon#*after write, iclass 21, count 0 2006.203.07:41:59.80#ibcon#*before return 0, iclass 21, count 0 2006.203.07:41:59.80#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.203.07:41:59.80#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.203.07:41:59.80#ibcon#about to clear, iclass 21 cls_cnt 0 2006.203.07:41:59.80#ibcon#cleared, iclass 21 cls_cnt 0 2006.203.07:41:59.80$vc4f8/va=2,7 2006.203.07:41:59.80#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.203.07:41:59.80#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.203.07:41:59.80#ibcon#ireg 11 cls_cnt 2 2006.203.07:41:59.80#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.203.07:41:59.85#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.203.07:41:59.85#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.203.07:41:59.85#ibcon#enter wrdev, iclass 23, count 2 2006.203.07:41:59.85#ibcon#first serial, iclass 23, count 2 2006.203.07:41:59.85#ibcon#enter sib2, iclass 23, count 2 2006.203.07:41:59.85#ibcon#flushed, iclass 23, count 2 2006.203.07:41:59.85#ibcon#about to write, iclass 23, count 2 2006.203.07:41:59.85#ibcon#wrote, iclass 23, count 2 2006.203.07:41:59.85#ibcon#about to read 3, iclass 23, count 2 2006.203.07:41:59.87#ibcon#read 3, iclass 23, count 2 2006.203.07:41:59.87#ibcon#about to read 4, iclass 23, count 2 2006.203.07:41:59.87#ibcon#read 4, iclass 23, count 2 2006.203.07:41:59.87#ibcon#about to read 5, iclass 23, count 2 2006.203.07:41:59.87#ibcon#read 5, iclass 23, count 2 2006.203.07:41:59.87#ibcon#about to read 6, iclass 23, count 2 2006.203.07:41:59.87#ibcon#read 6, iclass 23, count 2 2006.203.07:41:59.87#ibcon#end of sib2, iclass 23, count 2 2006.203.07:41:59.87#ibcon#*mode == 0, iclass 23, count 2 2006.203.07:41:59.87#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.203.07:41:59.87#ibcon#[25=AT02-07\r\n] 2006.203.07:41:59.87#ibcon#*before write, iclass 23, count 2 2006.203.07:41:59.87#ibcon#enter sib2, iclass 23, count 2 2006.203.07:41:59.87#ibcon#flushed, iclass 23, count 2 2006.203.07:41:59.87#ibcon#about to write, iclass 23, count 2 2006.203.07:41:59.87#ibcon#wrote, iclass 23, count 2 2006.203.07:41:59.87#ibcon#about to read 3, iclass 23, count 2 2006.203.07:41:59.90#ibcon#read 3, iclass 23, count 2 2006.203.07:41:59.90#ibcon#about to read 4, iclass 23, count 2 2006.203.07:41:59.90#ibcon#read 4, iclass 23, count 2 2006.203.07:41:59.90#ibcon#about to read 5, iclass 23, count 2 2006.203.07:41:59.90#ibcon#read 5, iclass 23, count 2 2006.203.07:41:59.90#ibcon#about to read 6, iclass 23, count 2 2006.203.07:41:59.90#ibcon#read 6, iclass 23, count 2 2006.203.07:41:59.90#ibcon#end of sib2, iclass 23, count 2 2006.203.07:41:59.90#ibcon#*after write, iclass 23, count 2 2006.203.07:41:59.90#ibcon#*before return 0, iclass 23, count 2 2006.203.07:41:59.90#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.203.07:41:59.90#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.203.07:41:59.90#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.203.07:41:59.90#ibcon#ireg 7 cls_cnt 0 2006.203.07:41:59.90#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.203.07:42:00.02#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.203.07:42:00.02#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.203.07:42:00.02#ibcon#enter wrdev, iclass 23, count 0 2006.203.07:42:00.02#ibcon#first serial, iclass 23, count 0 2006.203.07:42:00.02#ibcon#enter sib2, iclass 23, count 0 2006.203.07:42:00.02#ibcon#flushed, iclass 23, count 0 2006.203.07:42:00.02#ibcon#about to write, iclass 23, count 0 2006.203.07:42:00.02#ibcon#wrote, iclass 23, count 0 2006.203.07:42:00.02#ibcon#about to read 3, iclass 23, count 0 2006.203.07:42:00.04#ibcon#read 3, iclass 23, count 0 2006.203.07:42:00.04#ibcon#about to read 4, iclass 23, count 0 2006.203.07:42:00.04#ibcon#read 4, iclass 23, count 0 2006.203.07:42:00.04#ibcon#about to read 5, iclass 23, count 0 2006.203.07:42:00.04#ibcon#read 5, iclass 23, count 0 2006.203.07:42:00.04#ibcon#about to read 6, iclass 23, count 0 2006.203.07:42:00.04#ibcon#read 6, iclass 23, count 0 2006.203.07:42:00.04#ibcon#end of sib2, iclass 23, count 0 2006.203.07:42:00.04#ibcon#*mode == 0, iclass 23, count 0 2006.203.07:42:00.04#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.203.07:42:00.04#ibcon#[25=USB\r\n] 2006.203.07:42:00.04#ibcon#*before write, iclass 23, count 0 2006.203.07:42:00.04#ibcon#enter sib2, iclass 23, count 0 2006.203.07:42:00.04#ibcon#flushed, iclass 23, count 0 2006.203.07:42:00.04#ibcon#about to write, iclass 23, count 0 2006.203.07:42:00.04#ibcon#wrote, iclass 23, count 0 2006.203.07:42:00.04#ibcon#about to read 3, iclass 23, count 0 2006.203.07:42:00.08#ibcon#read 3, iclass 23, count 0 2006.203.07:42:00.08#ibcon#about to read 4, iclass 23, count 0 2006.203.07:42:00.08#ibcon#read 4, iclass 23, count 0 2006.203.07:42:00.08#ibcon#about to read 5, iclass 23, count 0 2006.203.07:42:00.08#ibcon#read 5, iclass 23, count 0 2006.203.07:42:00.08#ibcon#about to read 6, iclass 23, count 0 2006.203.07:42:00.08#ibcon#read 6, iclass 23, count 0 2006.203.07:42:00.08#ibcon#end of sib2, iclass 23, count 0 2006.203.07:42:00.08#ibcon#*after write, iclass 23, count 0 2006.203.07:42:00.08#ibcon#*before return 0, iclass 23, count 0 2006.203.07:42:00.08#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.203.07:42:00.08#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.203.07:42:00.08#ibcon#about to clear, iclass 23 cls_cnt 0 2006.203.07:42:00.08#ibcon#cleared, iclass 23 cls_cnt 0 2006.203.07:42:00.08$vc4f8/valo=3,672.99 2006.203.07:42:00.08#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.203.07:42:00.08#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.203.07:42:00.08#ibcon#ireg 17 cls_cnt 0 2006.203.07:42:00.08#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.203.07:42:00.08#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.203.07:42:00.08#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.203.07:42:00.08#ibcon#enter wrdev, iclass 25, count 0 2006.203.07:42:00.08#ibcon#first serial, iclass 25, count 0 2006.203.07:42:00.08#ibcon#enter sib2, iclass 25, count 0 2006.203.07:42:00.08#ibcon#flushed, iclass 25, count 0 2006.203.07:42:00.08#ibcon#about to write, iclass 25, count 0 2006.203.07:42:00.08#ibcon#wrote, iclass 25, count 0 2006.203.07:42:00.08#ibcon#about to read 3, iclass 25, count 0 2006.203.07:42:00.09#ibcon#read 3, iclass 25, count 0 2006.203.07:42:00.10#ibcon#about to read 4, iclass 25, count 0 2006.203.07:42:00.10#ibcon#read 4, iclass 25, count 0 2006.203.07:42:00.10#ibcon#about to read 5, iclass 25, count 0 2006.203.07:42:00.10#ibcon#read 5, iclass 25, count 0 2006.203.07:42:00.10#ibcon#about to read 6, iclass 25, count 0 2006.203.07:42:00.10#ibcon#read 6, iclass 25, count 0 2006.203.07:42:00.10#ibcon#end of sib2, iclass 25, count 0 2006.203.07:42:00.10#ibcon#*mode == 0, iclass 25, count 0 2006.203.07:42:00.10#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.203.07:42:00.10#ibcon#[26=FRQ=03,672.99\r\n] 2006.203.07:42:00.10#ibcon#*before write, iclass 25, count 0 2006.203.07:42:00.10#ibcon#enter sib2, iclass 25, count 0 2006.203.07:42:00.10#ibcon#flushed, iclass 25, count 0 2006.203.07:42:00.10#ibcon#about to write, iclass 25, count 0 2006.203.07:42:00.10#ibcon#wrote, iclass 25, count 0 2006.203.07:42:00.10#ibcon#about to read 3, iclass 25, count 0 2006.203.07:42:00.13#ibcon#read 3, iclass 25, count 0 2006.203.07:42:00.13#ibcon#about to read 4, iclass 25, count 0 2006.203.07:42:00.13#ibcon#read 4, iclass 25, count 0 2006.203.07:42:00.13#ibcon#about to read 5, iclass 25, count 0 2006.203.07:42:00.13#ibcon#read 5, iclass 25, count 0 2006.203.07:42:00.13#ibcon#about to read 6, iclass 25, count 0 2006.203.07:42:00.13#ibcon#read 6, iclass 25, count 0 2006.203.07:42:00.13#ibcon#end of sib2, iclass 25, count 0 2006.203.07:42:00.13#ibcon#*after write, iclass 25, count 0 2006.203.07:42:00.13#ibcon#*before return 0, iclass 25, count 0 2006.203.07:42:00.13#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.203.07:42:00.13#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.203.07:42:00.13#ibcon#about to clear, iclass 25 cls_cnt 0 2006.203.07:42:00.13#ibcon#cleared, iclass 25 cls_cnt 0 2006.203.07:42:00.13$vc4f8/va=3,8 2006.203.07:42:00.13#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.203.07:42:00.13#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.203.07:42:00.13#ibcon#ireg 11 cls_cnt 2 2006.203.07:42:00.13#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.203.07:42:00.20#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.203.07:42:00.20#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.203.07:42:00.20#ibcon#enter wrdev, iclass 27, count 2 2006.203.07:42:00.20#ibcon#first serial, iclass 27, count 2 2006.203.07:42:00.20#ibcon#enter sib2, iclass 27, count 2 2006.203.07:42:00.20#ibcon#flushed, iclass 27, count 2 2006.203.07:42:00.20#ibcon#about to write, iclass 27, count 2 2006.203.07:42:00.20#ibcon#wrote, iclass 27, count 2 2006.203.07:42:00.20#ibcon#about to read 3, iclass 27, count 2 2006.203.07:42:00.22#ibcon#read 3, iclass 27, count 2 2006.203.07:42:00.22#ibcon#about to read 4, iclass 27, count 2 2006.203.07:42:00.22#ibcon#read 4, iclass 27, count 2 2006.203.07:42:00.22#ibcon#about to read 5, iclass 27, count 2 2006.203.07:42:00.22#ibcon#read 5, iclass 27, count 2 2006.203.07:42:00.22#ibcon#about to read 6, iclass 27, count 2 2006.203.07:42:00.22#ibcon#read 6, iclass 27, count 2 2006.203.07:42:00.22#ibcon#end of sib2, iclass 27, count 2 2006.203.07:42:00.22#ibcon#*mode == 0, iclass 27, count 2 2006.203.07:42:00.22#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.203.07:42:00.22#ibcon#[25=AT03-08\r\n] 2006.203.07:42:00.22#ibcon#*before write, iclass 27, count 2 2006.203.07:42:00.22#ibcon#enter sib2, iclass 27, count 2 2006.203.07:42:00.22#ibcon#flushed, iclass 27, count 2 2006.203.07:42:00.22#ibcon#about to write, iclass 27, count 2 2006.203.07:42:00.22#ibcon#wrote, iclass 27, count 2 2006.203.07:42:00.22#ibcon#about to read 3, iclass 27, count 2 2006.203.07:42:00.25#ibcon#read 3, iclass 27, count 2 2006.203.07:42:00.25#ibcon#about to read 4, iclass 27, count 2 2006.203.07:42:00.25#ibcon#read 4, iclass 27, count 2 2006.203.07:42:00.25#ibcon#about to read 5, iclass 27, count 2 2006.203.07:42:00.25#ibcon#read 5, iclass 27, count 2 2006.203.07:42:00.25#ibcon#about to read 6, iclass 27, count 2 2006.203.07:42:00.25#ibcon#read 6, iclass 27, count 2 2006.203.07:42:00.25#ibcon#end of sib2, iclass 27, count 2 2006.203.07:42:00.25#ibcon#*after write, iclass 27, count 2 2006.203.07:42:00.25#ibcon#*before return 0, iclass 27, count 2 2006.203.07:42:00.25#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.203.07:42:00.25#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.203.07:42:00.25#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.203.07:42:00.25#ibcon#ireg 7 cls_cnt 0 2006.203.07:42:00.25#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.203.07:42:00.37#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.203.07:42:00.37#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.203.07:42:00.37#ibcon#enter wrdev, iclass 27, count 0 2006.203.07:42:00.37#ibcon#first serial, iclass 27, count 0 2006.203.07:42:00.37#ibcon#enter sib2, iclass 27, count 0 2006.203.07:42:00.37#ibcon#flushed, iclass 27, count 0 2006.203.07:42:00.37#ibcon#about to write, iclass 27, count 0 2006.203.07:42:00.37#ibcon#wrote, iclass 27, count 0 2006.203.07:42:00.37#ibcon#about to read 3, iclass 27, count 0 2006.203.07:42:00.39#ibcon#read 3, iclass 27, count 0 2006.203.07:42:00.39#ibcon#about to read 4, iclass 27, count 0 2006.203.07:42:00.39#ibcon#read 4, iclass 27, count 0 2006.203.07:42:00.39#ibcon#about to read 5, iclass 27, count 0 2006.203.07:42:00.39#ibcon#read 5, iclass 27, count 0 2006.203.07:42:00.39#ibcon#about to read 6, iclass 27, count 0 2006.203.07:42:00.39#ibcon#read 6, iclass 27, count 0 2006.203.07:42:00.39#ibcon#end of sib2, iclass 27, count 0 2006.203.07:42:00.39#ibcon#*mode == 0, iclass 27, count 0 2006.203.07:42:00.39#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.203.07:42:00.39#ibcon#[25=USB\r\n] 2006.203.07:42:00.39#ibcon#*before write, iclass 27, count 0 2006.203.07:42:00.39#ibcon#enter sib2, iclass 27, count 0 2006.203.07:42:00.39#ibcon#flushed, iclass 27, count 0 2006.203.07:42:00.39#ibcon#about to write, iclass 27, count 0 2006.203.07:42:00.39#ibcon#wrote, iclass 27, count 0 2006.203.07:42:00.39#ibcon#about to read 3, iclass 27, count 0 2006.203.07:42:00.42#ibcon#read 3, iclass 27, count 0 2006.203.07:42:00.42#ibcon#about to read 4, iclass 27, count 0 2006.203.07:42:00.42#ibcon#read 4, iclass 27, count 0 2006.203.07:42:00.42#ibcon#about to read 5, iclass 27, count 0 2006.203.07:42:00.42#ibcon#read 5, iclass 27, count 0 2006.203.07:42:00.42#ibcon#about to read 6, iclass 27, count 0 2006.203.07:42:00.42#ibcon#read 6, iclass 27, count 0 2006.203.07:42:00.42#ibcon#end of sib2, iclass 27, count 0 2006.203.07:42:00.42#ibcon#*after write, iclass 27, count 0 2006.203.07:42:00.42#ibcon#*before return 0, iclass 27, count 0 2006.203.07:42:00.42#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.203.07:42:00.42#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.203.07:42:00.42#ibcon#about to clear, iclass 27 cls_cnt 0 2006.203.07:42:00.42#ibcon#cleared, iclass 27 cls_cnt 0 2006.203.07:42:00.42$vc4f8/valo=4,832.99 2006.203.07:42:00.42#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.203.07:42:00.42#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.203.07:42:00.42#ibcon#ireg 17 cls_cnt 0 2006.203.07:42:00.42#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.203.07:42:00.42#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.203.07:42:00.42#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.203.07:42:00.42#ibcon#enter wrdev, iclass 29, count 0 2006.203.07:42:00.42#ibcon#first serial, iclass 29, count 0 2006.203.07:42:00.42#ibcon#enter sib2, iclass 29, count 0 2006.203.07:42:00.42#ibcon#flushed, iclass 29, count 0 2006.203.07:42:00.42#ibcon#about to write, iclass 29, count 0 2006.203.07:42:00.42#ibcon#wrote, iclass 29, count 0 2006.203.07:42:00.42#ibcon#about to read 3, iclass 29, count 0 2006.203.07:42:00.44#ibcon#read 3, iclass 29, count 0 2006.203.07:42:00.44#ibcon#about to read 4, iclass 29, count 0 2006.203.07:42:00.44#ibcon#read 4, iclass 29, count 0 2006.203.07:42:00.44#ibcon#about to read 5, iclass 29, count 0 2006.203.07:42:00.44#ibcon#read 5, iclass 29, count 0 2006.203.07:42:00.44#ibcon#about to read 6, iclass 29, count 0 2006.203.07:42:00.44#ibcon#read 6, iclass 29, count 0 2006.203.07:42:00.44#ibcon#end of sib2, iclass 29, count 0 2006.203.07:42:00.44#ibcon#*mode == 0, iclass 29, count 0 2006.203.07:42:00.44#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.203.07:42:00.44#ibcon#[26=FRQ=04,832.99\r\n] 2006.203.07:42:00.44#ibcon#*before write, iclass 29, count 0 2006.203.07:42:00.44#ibcon#enter sib2, iclass 29, count 0 2006.203.07:42:00.44#ibcon#flushed, iclass 29, count 0 2006.203.07:42:00.44#ibcon#about to write, iclass 29, count 0 2006.203.07:42:00.44#ibcon#wrote, iclass 29, count 0 2006.203.07:42:00.44#ibcon#about to read 3, iclass 29, count 0 2006.203.07:42:00.48#ibcon#read 3, iclass 29, count 0 2006.203.07:42:00.48#ibcon#about to read 4, iclass 29, count 0 2006.203.07:42:00.48#ibcon#read 4, iclass 29, count 0 2006.203.07:42:00.48#ibcon#about to read 5, iclass 29, count 0 2006.203.07:42:00.48#ibcon#read 5, iclass 29, count 0 2006.203.07:42:00.48#ibcon#about to read 6, iclass 29, count 0 2006.203.07:42:00.48#ibcon#read 6, iclass 29, count 0 2006.203.07:42:00.48#ibcon#end of sib2, iclass 29, count 0 2006.203.07:42:00.48#ibcon#*after write, iclass 29, count 0 2006.203.07:42:00.48#ibcon#*before return 0, iclass 29, count 0 2006.203.07:42:00.48#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.203.07:42:00.48#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.203.07:42:00.48#ibcon#about to clear, iclass 29 cls_cnt 0 2006.203.07:42:00.48#ibcon#cleared, iclass 29 cls_cnt 0 2006.203.07:42:00.48$vc4f8/va=4,7 2006.203.07:42:00.48#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.203.07:42:00.48#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.203.07:42:00.48#ibcon#ireg 11 cls_cnt 2 2006.203.07:42:00.48#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.203.07:42:00.54#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.203.07:42:00.54#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.203.07:42:00.54#ibcon#enter wrdev, iclass 31, count 2 2006.203.07:42:00.54#ibcon#first serial, iclass 31, count 2 2006.203.07:42:00.54#ibcon#enter sib2, iclass 31, count 2 2006.203.07:42:00.54#ibcon#flushed, iclass 31, count 2 2006.203.07:42:00.54#ibcon#about to write, iclass 31, count 2 2006.203.07:42:00.54#ibcon#wrote, iclass 31, count 2 2006.203.07:42:00.54#ibcon#about to read 3, iclass 31, count 2 2006.203.07:42:00.56#ibcon#read 3, iclass 31, count 2 2006.203.07:42:00.56#ibcon#about to read 4, iclass 31, count 2 2006.203.07:42:00.56#ibcon#read 4, iclass 31, count 2 2006.203.07:42:00.56#ibcon#about to read 5, iclass 31, count 2 2006.203.07:42:00.56#ibcon#read 5, iclass 31, count 2 2006.203.07:42:00.56#ibcon#about to read 6, iclass 31, count 2 2006.203.07:42:00.56#ibcon#read 6, iclass 31, count 2 2006.203.07:42:00.56#ibcon#end of sib2, iclass 31, count 2 2006.203.07:42:00.56#ibcon#*mode == 0, iclass 31, count 2 2006.203.07:42:00.56#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.203.07:42:00.56#ibcon#[25=AT04-07\r\n] 2006.203.07:42:00.56#ibcon#*before write, iclass 31, count 2 2006.203.07:42:00.56#ibcon#enter sib2, iclass 31, count 2 2006.203.07:42:00.56#ibcon#flushed, iclass 31, count 2 2006.203.07:42:00.56#ibcon#about to write, iclass 31, count 2 2006.203.07:42:00.56#ibcon#wrote, iclass 31, count 2 2006.203.07:42:00.56#ibcon#about to read 3, iclass 31, count 2 2006.203.07:42:00.59#ibcon#read 3, iclass 31, count 2 2006.203.07:42:00.59#ibcon#about to read 4, iclass 31, count 2 2006.203.07:42:00.59#ibcon#read 4, iclass 31, count 2 2006.203.07:42:00.59#ibcon#about to read 5, iclass 31, count 2 2006.203.07:42:00.59#ibcon#read 5, iclass 31, count 2 2006.203.07:42:00.59#ibcon#about to read 6, iclass 31, count 2 2006.203.07:42:00.59#ibcon#read 6, iclass 31, count 2 2006.203.07:42:00.59#ibcon#end of sib2, iclass 31, count 2 2006.203.07:42:00.59#ibcon#*after write, iclass 31, count 2 2006.203.07:42:00.59#ibcon#*before return 0, iclass 31, count 2 2006.203.07:42:00.59#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.203.07:42:00.59#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.203.07:42:00.59#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.203.07:42:00.59#ibcon#ireg 7 cls_cnt 0 2006.203.07:42:00.59#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.203.07:42:00.71#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.203.07:42:00.71#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.203.07:42:00.71#ibcon#enter wrdev, iclass 31, count 0 2006.203.07:42:00.71#ibcon#first serial, iclass 31, count 0 2006.203.07:42:00.71#ibcon#enter sib2, iclass 31, count 0 2006.203.07:42:00.71#ibcon#flushed, iclass 31, count 0 2006.203.07:42:00.71#ibcon#about to write, iclass 31, count 0 2006.203.07:42:00.71#ibcon#wrote, iclass 31, count 0 2006.203.07:42:00.71#ibcon#about to read 3, iclass 31, count 0 2006.203.07:42:00.73#ibcon#read 3, iclass 31, count 0 2006.203.07:42:00.73#ibcon#about to read 4, iclass 31, count 0 2006.203.07:42:00.73#ibcon#read 4, iclass 31, count 0 2006.203.07:42:00.73#ibcon#about to read 5, iclass 31, count 0 2006.203.07:42:00.73#ibcon#read 5, iclass 31, count 0 2006.203.07:42:00.73#ibcon#about to read 6, iclass 31, count 0 2006.203.07:42:00.73#ibcon#read 6, iclass 31, count 0 2006.203.07:42:00.73#ibcon#end of sib2, iclass 31, count 0 2006.203.07:42:00.73#ibcon#*mode == 0, iclass 31, count 0 2006.203.07:42:00.73#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.203.07:42:00.73#ibcon#[25=USB\r\n] 2006.203.07:42:00.73#ibcon#*before write, iclass 31, count 0 2006.203.07:42:00.73#ibcon#enter sib2, iclass 31, count 0 2006.203.07:42:00.73#ibcon#flushed, iclass 31, count 0 2006.203.07:42:00.73#ibcon#about to write, iclass 31, count 0 2006.203.07:42:00.73#ibcon#wrote, iclass 31, count 0 2006.203.07:42:00.73#ibcon#about to read 3, iclass 31, count 0 2006.203.07:42:00.76#ibcon#read 3, iclass 31, count 0 2006.203.07:42:00.76#ibcon#about to read 4, iclass 31, count 0 2006.203.07:42:00.76#ibcon#read 4, iclass 31, count 0 2006.203.07:42:00.76#ibcon#about to read 5, iclass 31, count 0 2006.203.07:42:00.76#ibcon#read 5, iclass 31, count 0 2006.203.07:42:00.76#ibcon#about to read 6, iclass 31, count 0 2006.203.07:42:00.76#ibcon#read 6, iclass 31, count 0 2006.203.07:42:00.76#ibcon#end of sib2, iclass 31, count 0 2006.203.07:42:00.76#ibcon#*after write, iclass 31, count 0 2006.203.07:42:00.76#ibcon#*before return 0, iclass 31, count 0 2006.203.07:42:00.76#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.203.07:42:00.76#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.203.07:42:00.76#ibcon#about to clear, iclass 31 cls_cnt 0 2006.203.07:42:00.76#ibcon#cleared, iclass 31 cls_cnt 0 2006.203.07:42:00.76$vc4f8/valo=5,652.99 2006.203.07:42:00.76#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.203.07:42:00.76#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.203.07:42:00.76#ibcon#ireg 17 cls_cnt 0 2006.203.07:42:00.76#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.203.07:42:00.76#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.203.07:42:00.76#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.203.07:42:00.76#ibcon#enter wrdev, iclass 33, count 0 2006.203.07:42:00.76#ibcon#first serial, iclass 33, count 0 2006.203.07:42:00.76#ibcon#enter sib2, iclass 33, count 0 2006.203.07:42:00.76#ibcon#flushed, iclass 33, count 0 2006.203.07:42:00.76#ibcon#about to write, iclass 33, count 0 2006.203.07:42:00.76#ibcon#wrote, iclass 33, count 0 2006.203.07:42:00.76#ibcon#about to read 3, iclass 33, count 0 2006.203.07:42:00.78#ibcon#read 3, iclass 33, count 0 2006.203.07:42:00.78#ibcon#about to read 4, iclass 33, count 0 2006.203.07:42:00.78#ibcon#read 4, iclass 33, count 0 2006.203.07:42:00.78#ibcon#about to read 5, iclass 33, count 0 2006.203.07:42:00.78#ibcon#read 5, iclass 33, count 0 2006.203.07:42:00.78#ibcon#about to read 6, iclass 33, count 0 2006.203.07:42:00.78#ibcon#read 6, iclass 33, count 0 2006.203.07:42:00.78#ibcon#end of sib2, iclass 33, count 0 2006.203.07:42:00.78#ibcon#*mode == 0, iclass 33, count 0 2006.203.07:42:00.78#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.203.07:42:00.78#ibcon#[26=FRQ=05,652.99\r\n] 2006.203.07:42:00.78#ibcon#*before write, iclass 33, count 0 2006.203.07:42:00.78#ibcon#enter sib2, iclass 33, count 0 2006.203.07:42:00.78#ibcon#flushed, iclass 33, count 0 2006.203.07:42:00.78#ibcon#about to write, iclass 33, count 0 2006.203.07:42:00.78#ibcon#wrote, iclass 33, count 0 2006.203.07:42:00.78#ibcon#about to read 3, iclass 33, count 0 2006.203.07:42:00.82#ibcon#read 3, iclass 33, count 0 2006.203.07:42:00.82#ibcon#about to read 4, iclass 33, count 0 2006.203.07:42:00.82#ibcon#read 4, iclass 33, count 0 2006.203.07:42:00.82#ibcon#about to read 5, iclass 33, count 0 2006.203.07:42:00.82#ibcon#read 5, iclass 33, count 0 2006.203.07:42:00.82#ibcon#about to read 6, iclass 33, count 0 2006.203.07:42:00.82#ibcon#read 6, iclass 33, count 0 2006.203.07:42:00.82#ibcon#end of sib2, iclass 33, count 0 2006.203.07:42:00.82#ibcon#*after write, iclass 33, count 0 2006.203.07:42:00.82#ibcon#*before return 0, iclass 33, count 0 2006.203.07:42:00.82#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.203.07:42:00.82#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.203.07:42:00.82#ibcon#about to clear, iclass 33 cls_cnt 0 2006.203.07:42:00.82#ibcon#cleared, iclass 33 cls_cnt 0 2006.203.07:42:00.82$vc4f8/va=5,7 2006.203.07:42:00.82#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.203.07:42:00.82#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.203.07:42:00.82#ibcon#ireg 11 cls_cnt 2 2006.203.07:42:00.82#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.203.07:42:00.88#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.203.07:42:00.88#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.203.07:42:00.88#ibcon#enter wrdev, iclass 35, count 2 2006.203.07:42:00.88#ibcon#first serial, iclass 35, count 2 2006.203.07:42:00.88#ibcon#enter sib2, iclass 35, count 2 2006.203.07:42:00.88#ibcon#flushed, iclass 35, count 2 2006.203.07:42:00.88#ibcon#about to write, iclass 35, count 2 2006.203.07:42:00.88#ibcon#wrote, iclass 35, count 2 2006.203.07:42:00.88#ibcon#about to read 3, iclass 35, count 2 2006.203.07:42:00.90#ibcon#read 3, iclass 35, count 2 2006.203.07:42:00.90#ibcon#about to read 4, iclass 35, count 2 2006.203.07:42:00.90#ibcon#read 4, iclass 35, count 2 2006.203.07:42:00.90#ibcon#about to read 5, iclass 35, count 2 2006.203.07:42:00.90#ibcon#read 5, iclass 35, count 2 2006.203.07:42:00.90#ibcon#about to read 6, iclass 35, count 2 2006.203.07:42:00.90#ibcon#read 6, iclass 35, count 2 2006.203.07:42:00.90#ibcon#end of sib2, iclass 35, count 2 2006.203.07:42:00.90#ibcon#*mode == 0, iclass 35, count 2 2006.203.07:42:00.90#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.203.07:42:00.90#ibcon#[25=AT05-07\r\n] 2006.203.07:42:00.90#ibcon#*before write, iclass 35, count 2 2006.203.07:42:00.90#ibcon#enter sib2, iclass 35, count 2 2006.203.07:42:00.90#ibcon#flushed, iclass 35, count 2 2006.203.07:42:00.90#ibcon#about to write, iclass 35, count 2 2006.203.07:42:00.90#ibcon#wrote, iclass 35, count 2 2006.203.07:42:00.90#ibcon#about to read 3, iclass 35, count 2 2006.203.07:42:00.93#ibcon#read 3, iclass 35, count 2 2006.203.07:42:00.93#ibcon#about to read 4, iclass 35, count 2 2006.203.07:42:00.93#ibcon#read 4, iclass 35, count 2 2006.203.07:42:00.93#ibcon#about to read 5, iclass 35, count 2 2006.203.07:42:00.93#ibcon#read 5, iclass 35, count 2 2006.203.07:42:00.93#ibcon#about to read 6, iclass 35, count 2 2006.203.07:42:00.93#ibcon#read 6, iclass 35, count 2 2006.203.07:42:00.93#ibcon#end of sib2, iclass 35, count 2 2006.203.07:42:00.93#ibcon#*after write, iclass 35, count 2 2006.203.07:42:00.93#ibcon#*before return 0, iclass 35, count 2 2006.203.07:42:00.93#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.203.07:42:00.93#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.203.07:42:00.93#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.203.07:42:00.93#ibcon#ireg 7 cls_cnt 0 2006.203.07:42:00.93#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.203.07:42:01.05#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.203.07:42:01.05#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.203.07:42:01.05#ibcon#enter wrdev, iclass 35, count 0 2006.203.07:42:01.05#ibcon#first serial, iclass 35, count 0 2006.203.07:42:01.05#ibcon#enter sib2, iclass 35, count 0 2006.203.07:42:01.05#ibcon#flushed, iclass 35, count 0 2006.203.07:42:01.05#ibcon#about to write, iclass 35, count 0 2006.203.07:42:01.05#ibcon#wrote, iclass 35, count 0 2006.203.07:42:01.05#ibcon#about to read 3, iclass 35, count 0 2006.203.07:42:01.07#ibcon#read 3, iclass 35, count 0 2006.203.07:42:01.07#ibcon#about to read 4, iclass 35, count 0 2006.203.07:42:01.07#ibcon#read 4, iclass 35, count 0 2006.203.07:42:01.07#ibcon#about to read 5, iclass 35, count 0 2006.203.07:42:01.07#ibcon#read 5, iclass 35, count 0 2006.203.07:42:01.07#ibcon#about to read 6, iclass 35, count 0 2006.203.07:42:01.07#ibcon#read 6, iclass 35, count 0 2006.203.07:42:01.07#ibcon#end of sib2, iclass 35, count 0 2006.203.07:42:01.07#ibcon#*mode == 0, iclass 35, count 0 2006.203.07:42:01.07#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.203.07:42:01.07#ibcon#[25=USB\r\n] 2006.203.07:42:01.07#ibcon#*before write, iclass 35, count 0 2006.203.07:42:01.07#ibcon#enter sib2, iclass 35, count 0 2006.203.07:42:01.07#ibcon#flushed, iclass 35, count 0 2006.203.07:42:01.07#ibcon#about to write, iclass 35, count 0 2006.203.07:42:01.07#ibcon#wrote, iclass 35, count 0 2006.203.07:42:01.07#ibcon#about to read 3, iclass 35, count 0 2006.203.07:42:01.10#ibcon#read 3, iclass 35, count 0 2006.203.07:42:01.10#ibcon#about to read 4, iclass 35, count 0 2006.203.07:42:01.10#ibcon#read 4, iclass 35, count 0 2006.203.07:42:01.10#ibcon#about to read 5, iclass 35, count 0 2006.203.07:42:01.10#ibcon#read 5, iclass 35, count 0 2006.203.07:42:01.10#ibcon#about to read 6, iclass 35, count 0 2006.203.07:42:01.10#ibcon#read 6, iclass 35, count 0 2006.203.07:42:01.10#ibcon#end of sib2, iclass 35, count 0 2006.203.07:42:01.10#ibcon#*after write, iclass 35, count 0 2006.203.07:42:01.10#ibcon#*before return 0, iclass 35, count 0 2006.203.07:42:01.10#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.203.07:42:01.10#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.203.07:42:01.10#ibcon#about to clear, iclass 35 cls_cnt 0 2006.203.07:42:01.10#ibcon#cleared, iclass 35 cls_cnt 0 2006.203.07:42:01.10$vc4f8/valo=6,772.99 2006.203.07:42:01.10#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.203.07:42:01.10#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.203.07:42:01.10#ibcon#ireg 17 cls_cnt 0 2006.203.07:42:01.10#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.203.07:42:01.10#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.203.07:42:01.10#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.203.07:42:01.10#ibcon#enter wrdev, iclass 37, count 0 2006.203.07:42:01.10#ibcon#first serial, iclass 37, count 0 2006.203.07:42:01.10#ibcon#enter sib2, iclass 37, count 0 2006.203.07:42:01.10#ibcon#flushed, iclass 37, count 0 2006.203.07:42:01.10#ibcon#about to write, iclass 37, count 0 2006.203.07:42:01.10#ibcon#wrote, iclass 37, count 0 2006.203.07:42:01.10#ibcon#about to read 3, iclass 37, count 0 2006.203.07:42:01.12#ibcon#read 3, iclass 37, count 0 2006.203.07:42:01.12#ibcon#about to read 4, iclass 37, count 0 2006.203.07:42:01.12#ibcon#read 4, iclass 37, count 0 2006.203.07:42:01.12#ibcon#about to read 5, iclass 37, count 0 2006.203.07:42:01.12#ibcon#read 5, iclass 37, count 0 2006.203.07:42:01.12#ibcon#about to read 6, iclass 37, count 0 2006.203.07:42:01.12#ibcon#read 6, iclass 37, count 0 2006.203.07:42:01.12#ibcon#end of sib2, iclass 37, count 0 2006.203.07:42:01.12#ibcon#*mode == 0, iclass 37, count 0 2006.203.07:42:01.12#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.203.07:42:01.12#ibcon#[26=FRQ=06,772.99\r\n] 2006.203.07:42:01.12#ibcon#*before write, iclass 37, count 0 2006.203.07:42:01.12#ibcon#enter sib2, iclass 37, count 0 2006.203.07:42:01.12#ibcon#flushed, iclass 37, count 0 2006.203.07:42:01.12#ibcon#about to write, iclass 37, count 0 2006.203.07:42:01.12#ibcon#wrote, iclass 37, count 0 2006.203.07:42:01.12#ibcon#about to read 3, iclass 37, count 0 2006.203.07:42:01.16#ibcon#read 3, iclass 37, count 0 2006.203.07:42:01.16#ibcon#about to read 4, iclass 37, count 0 2006.203.07:42:01.16#ibcon#read 4, iclass 37, count 0 2006.203.07:42:01.16#ibcon#about to read 5, iclass 37, count 0 2006.203.07:42:01.16#ibcon#read 5, iclass 37, count 0 2006.203.07:42:01.16#ibcon#about to read 6, iclass 37, count 0 2006.203.07:42:01.16#ibcon#read 6, iclass 37, count 0 2006.203.07:42:01.16#ibcon#end of sib2, iclass 37, count 0 2006.203.07:42:01.16#ibcon#*after write, iclass 37, count 0 2006.203.07:42:01.16#ibcon#*before return 0, iclass 37, count 0 2006.203.07:42:01.16#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.203.07:42:01.16#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.203.07:42:01.16#ibcon#about to clear, iclass 37 cls_cnt 0 2006.203.07:42:01.16#ibcon#cleared, iclass 37 cls_cnt 0 2006.203.07:42:01.16$vc4f8/va=6,6 2006.203.07:42:01.16#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.203.07:42:01.16#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.203.07:42:01.16#ibcon#ireg 11 cls_cnt 2 2006.203.07:42:01.16#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.203.07:42:01.22#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.203.07:42:01.22#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.203.07:42:01.22#ibcon#enter wrdev, iclass 39, count 2 2006.203.07:42:01.22#ibcon#first serial, iclass 39, count 2 2006.203.07:42:01.22#ibcon#enter sib2, iclass 39, count 2 2006.203.07:42:01.22#ibcon#flushed, iclass 39, count 2 2006.203.07:42:01.22#ibcon#about to write, iclass 39, count 2 2006.203.07:42:01.22#ibcon#wrote, iclass 39, count 2 2006.203.07:42:01.22#ibcon#about to read 3, iclass 39, count 2 2006.203.07:42:01.24#ibcon#read 3, iclass 39, count 2 2006.203.07:42:01.24#ibcon#about to read 4, iclass 39, count 2 2006.203.07:42:01.24#ibcon#read 4, iclass 39, count 2 2006.203.07:42:01.24#ibcon#about to read 5, iclass 39, count 2 2006.203.07:42:01.24#ibcon#read 5, iclass 39, count 2 2006.203.07:42:01.24#ibcon#about to read 6, iclass 39, count 2 2006.203.07:42:01.24#ibcon#read 6, iclass 39, count 2 2006.203.07:42:01.24#ibcon#end of sib2, iclass 39, count 2 2006.203.07:42:01.24#ibcon#*mode == 0, iclass 39, count 2 2006.203.07:42:01.24#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.203.07:42:01.24#ibcon#[25=AT06-06\r\n] 2006.203.07:42:01.24#ibcon#*before write, iclass 39, count 2 2006.203.07:42:01.24#ibcon#enter sib2, iclass 39, count 2 2006.203.07:42:01.24#ibcon#flushed, iclass 39, count 2 2006.203.07:42:01.24#ibcon#about to write, iclass 39, count 2 2006.203.07:42:01.24#ibcon#wrote, iclass 39, count 2 2006.203.07:42:01.24#ibcon#about to read 3, iclass 39, count 2 2006.203.07:42:01.27#ibcon#read 3, iclass 39, count 2 2006.203.07:42:01.27#ibcon#about to read 4, iclass 39, count 2 2006.203.07:42:01.27#ibcon#read 4, iclass 39, count 2 2006.203.07:42:01.27#ibcon#about to read 5, iclass 39, count 2 2006.203.07:42:01.27#ibcon#read 5, iclass 39, count 2 2006.203.07:42:01.27#ibcon#about to read 6, iclass 39, count 2 2006.203.07:42:01.27#ibcon#read 6, iclass 39, count 2 2006.203.07:42:01.27#ibcon#end of sib2, iclass 39, count 2 2006.203.07:42:01.27#ibcon#*after write, iclass 39, count 2 2006.203.07:42:01.27#ibcon#*before return 0, iclass 39, count 2 2006.203.07:42:01.27#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.203.07:42:01.27#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.203.07:42:01.27#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.203.07:42:01.27#ibcon#ireg 7 cls_cnt 0 2006.203.07:42:01.27#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.203.07:42:01.39#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.203.07:42:01.39#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.203.07:42:01.39#ibcon#enter wrdev, iclass 39, count 0 2006.203.07:42:01.39#ibcon#first serial, iclass 39, count 0 2006.203.07:42:01.39#ibcon#enter sib2, iclass 39, count 0 2006.203.07:42:01.39#ibcon#flushed, iclass 39, count 0 2006.203.07:42:01.39#ibcon#about to write, iclass 39, count 0 2006.203.07:42:01.39#ibcon#wrote, iclass 39, count 0 2006.203.07:42:01.39#ibcon#about to read 3, iclass 39, count 0 2006.203.07:42:01.41#ibcon#read 3, iclass 39, count 0 2006.203.07:42:01.41#ibcon#about to read 4, iclass 39, count 0 2006.203.07:42:01.41#ibcon#read 4, iclass 39, count 0 2006.203.07:42:01.41#ibcon#about to read 5, iclass 39, count 0 2006.203.07:42:01.41#ibcon#read 5, iclass 39, count 0 2006.203.07:42:01.41#ibcon#about to read 6, iclass 39, count 0 2006.203.07:42:01.41#ibcon#read 6, iclass 39, count 0 2006.203.07:42:01.41#ibcon#end of sib2, iclass 39, count 0 2006.203.07:42:01.41#ibcon#*mode == 0, iclass 39, count 0 2006.203.07:42:01.41#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.203.07:42:01.41#ibcon#[25=USB\r\n] 2006.203.07:42:01.41#ibcon#*before write, iclass 39, count 0 2006.203.07:42:01.41#ibcon#enter sib2, iclass 39, count 0 2006.203.07:42:01.41#ibcon#flushed, iclass 39, count 0 2006.203.07:42:01.41#ibcon#about to write, iclass 39, count 0 2006.203.07:42:01.41#ibcon#wrote, iclass 39, count 0 2006.203.07:42:01.41#ibcon#about to read 3, iclass 39, count 0 2006.203.07:42:01.44#ibcon#read 3, iclass 39, count 0 2006.203.07:42:01.44#ibcon#about to read 4, iclass 39, count 0 2006.203.07:42:01.44#ibcon#read 4, iclass 39, count 0 2006.203.07:42:01.44#ibcon#about to read 5, iclass 39, count 0 2006.203.07:42:01.44#ibcon#read 5, iclass 39, count 0 2006.203.07:42:01.44#ibcon#about to read 6, iclass 39, count 0 2006.203.07:42:01.44#ibcon#read 6, iclass 39, count 0 2006.203.07:42:01.44#ibcon#end of sib2, iclass 39, count 0 2006.203.07:42:01.44#ibcon#*after write, iclass 39, count 0 2006.203.07:42:01.44#ibcon#*before return 0, iclass 39, count 0 2006.203.07:42:01.44#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.203.07:42:01.44#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.203.07:42:01.44#ibcon#about to clear, iclass 39 cls_cnt 0 2006.203.07:42:01.44#ibcon#cleared, iclass 39 cls_cnt 0 2006.203.07:42:01.44$vc4f8/valo=7,832.99 2006.203.07:42:01.44#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.203.07:42:01.44#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.203.07:42:01.44#ibcon#ireg 17 cls_cnt 0 2006.203.07:42:01.44#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.203.07:42:01.44#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.203.07:42:01.44#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.203.07:42:01.44#ibcon#enter wrdev, iclass 3, count 0 2006.203.07:42:01.44#ibcon#first serial, iclass 3, count 0 2006.203.07:42:01.44#ibcon#enter sib2, iclass 3, count 0 2006.203.07:42:01.44#ibcon#flushed, iclass 3, count 0 2006.203.07:42:01.44#ibcon#about to write, iclass 3, count 0 2006.203.07:42:01.44#ibcon#wrote, iclass 3, count 0 2006.203.07:42:01.44#ibcon#about to read 3, iclass 3, count 0 2006.203.07:42:01.46#ibcon#read 3, iclass 3, count 0 2006.203.07:42:01.46#ibcon#about to read 4, iclass 3, count 0 2006.203.07:42:01.46#ibcon#read 4, iclass 3, count 0 2006.203.07:42:01.46#ibcon#about to read 5, iclass 3, count 0 2006.203.07:42:01.46#ibcon#read 5, iclass 3, count 0 2006.203.07:42:01.46#ibcon#about to read 6, iclass 3, count 0 2006.203.07:42:01.46#ibcon#read 6, iclass 3, count 0 2006.203.07:42:01.46#ibcon#end of sib2, iclass 3, count 0 2006.203.07:42:01.46#ibcon#*mode == 0, iclass 3, count 0 2006.203.07:42:01.46#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.203.07:42:01.46#ibcon#[26=FRQ=07,832.99\r\n] 2006.203.07:42:01.46#ibcon#*before write, iclass 3, count 0 2006.203.07:42:01.46#ibcon#enter sib2, iclass 3, count 0 2006.203.07:42:01.46#ibcon#flushed, iclass 3, count 0 2006.203.07:42:01.46#ibcon#about to write, iclass 3, count 0 2006.203.07:42:01.46#ibcon#wrote, iclass 3, count 0 2006.203.07:42:01.46#ibcon#about to read 3, iclass 3, count 0 2006.203.07:42:01.50#ibcon#read 3, iclass 3, count 0 2006.203.07:42:01.50#ibcon#about to read 4, iclass 3, count 0 2006.203.07:42:01.50#ibcon#read 4, iclass 3, count 0 2006.203.07:42:01.50#ibcon#about to read 5, iclass 3, count 0 2006.203.07:42:01.50#ibcon#read 5, iclass 3, count 0 2006.203.07:42:01.50#ibcon#about to read 6, iclass 3, count 0 2006.203.07:42:01.50#ibcon#read 6, iclass 3, count 0 2006.203.07:42:01.50#ibcon#end of sib2, iclass 3, count 0 2006.203.07:42:01.50#ibcon#*after write, iclass 3, count 0 2006.203.07:42:01.50#ibcon#*before return 0, iclass 3, count 0 2006.203.07:42:01.50#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.203.07:42:01.50#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.203.07:42:01.50#ibcon#about to clear, iclass 3 cls_cnt 0 2006.203.07:42:01.50#ibcon#cleared, iclass 3 cls_cnt 0 2006.203.07:42:01.50$vc4f8/va=7,7 2006.203.07:42:01.50#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.203.07:42:01.50#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.203.07:42:01.50#ibcon#ireg 11 cls_cnt 2 2006.203.07:42:01.50#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.203.07:42:01.56#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.203.07:42:01.56#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.203.07:42:01.56#ibcon#enter wrdev, iclass 5, count 2 2006.203.07:42:01.56#ibcon#first serial, iclass 5, count 2 2006.203.07:42:01.56#ibcon#enter sib2, iclass 5, count 2 2006.203.07:42:01.56#ibcon#flushed, iclass 5, count 2 2006.203.07:42:01.56#ibcon#about to write, iclass 5, count 2 2006.203.07:42:01.56#ibcon#wrote, iclass 5, count 2 2006.203.07:42:01.56#ibcon#about to read 3, iclass 5, count 2 2006.203.07:42:01.58#ibcon#read 3, iclass 5, count 2 2006.203.07:42:01.58#ibcon#about to read 4, iclass 5, count 2 2006.203.07:42:01.58#ibcon#read 4, iclass 5, count 2 2006.203.07:42:01.58#ibcon#about to read 5, iclass 5, count 2 2006.203.07:42:01.58#ibcon#read 5, iclass 5, count 2 2006.203.07:42:01.58#ibcon#about to read 6, iclass 5, count 2 2006.203.07:42:01.58#ibcon#read 6, iclass 5, count 2 2006.203.07:42:01.58#ibcon#end of sib2, iclass 5, count 2 2006.203.07:42:01.58#ibcon#*mode == 0, iclass 5, count 2 2006.203.07:42:01.58#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.203.07:42:01.58#ibcon#[25=AT07-07\r\n] 2006.203.07:42:01.58#ibcon#*before write, iclass 5, count 2 2006.203.07:42:01.58#ibcon#enter sib2, iclass 5, count 2 2006.203.07:42:01.58#ibcon#flushed, iclass 5, count 2 2006.203.07:42:01.58#ibcon#about to write, iclass 5, count 2 2006.203.07:42:01.58#ibcon#wrote, iclass 5, count 2 2006.203.07:42:01.58#ibcon#about to read 3, iclass 5, count 2 2006.203.07:42:01.61#ibcon#read 3, iclass 5, count 2 2006.203.07:42:01.61#ibcon#about to read 4, iclass 5, count 2 2006.203.07:42:01.61#ibcon#read 4, iclass 5, count 2 2006.203.07:42:01.61#ibcon#about to read 5, iclass 5, count 2 2006.203.07:42:01.61#ibcon#read 5, iclass 5, count 2 2006.203.07:42:01.61#ibcon#about to read 6, iclass 5, count 2 2006.203.07:42:01.61#ibcon#read 6, iclass 5, count 2 2006.203.07:42:01.61#ibcon#end of sib2, iclass 5, count 2 2006.203.07:42:01.61#ibcon#*after write, iclass 5, count 2 2006.203.07:42:01.61#ibcon#*before return 0, iclass 5, count 2 2006.203.07:42:01.61#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.203.07:42:01.61#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.203.07:42:01.61#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.203.07:42:01.61#ibcon#ireg 7 cls_cnt 0 2006.203.07:42:01.61#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.203.07:42:01.73#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.203.07:42:01.73#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.203.07:42:01.73#ibcon#enter wrdev, iclass 5, count 0 2006.203.07:42:01.73#ibcon#first serial, iclass 5, count 0 2006.203.07:42:01.73#ibcon#enter sib2, iclass 5, count 0 2006.203.07:42:01.73#ibcon#flushed, iclass 5, count 0 2006.203.07:42:01.73#ibcon#about to write, iclass 5, count 0 2006.203.07:42:01.73#ibcon#wrote, iclass 5, count 0 2006.203.07:42:01.73#ibcon#about to read 3, iclass 5, count 0 2006.203.07:42:01.75#ibcon#read 3, iclass 5, count 0 2006.203.07:42:01.75#ibcon#about to read 4, iclass 5, count 0 2006.203.07:42:01.75#ibcon#read 4, iclass 5, count 0 2006.203.07:42:01.75#ibcon#about to read 5, iclass 5, count 0 2006.203.07:42:01.75#ibcon#read 5, iclass 5, count 0 2006.203.07:42:01.75#ibcon#about to read 6, iclass 5, count 0 2006.203.07:42:01.75#ibcon#read 6, iclass 5, count 0 2006.203.07:42:01.75#ibcon#end of sib2, iclass 5, count 0 2006.203.07:42:01.75#ibcon#*mode == 0, iclass 5, count 0 2006.203.07:42:01.75#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.203.07:42:01.75#ibcon#[25=USB\r\n] 2006.203.07:42:01.75#ibcon#*before write, iclass 5, count 0 2006.203.07:42:01.75#ibcon#enter sib2, iclass 5, count 0 2006.203.07:42:01.75#ibcon#flushed, iclass 5, count 0 2006.203.07:42:01.75#ibcon#about to write, iclass 5, count 0 2006.203.07:42:01.75#ibcon#wrote, iclass 5, count 0 2006.203.07:42:01.75#ibcon#about to read 3, iclass 5, count 0 2006.203.07:42:01.78#ibcon#read 3, iclass 5, count 0 2006.203.07:42:01.78#ibcon#about to read 4, iclass 5, count 0 2006.203.07:42:01.78#ibcon#read 4, iclass 5, count 0 2006.203.07:42:01.78#ibcon#about to read 5, iclass 5, count 0 2006.203.07:42:01.78#ibcon#read 5, iclass 5, count 0 2006.203.07:42:01.78#ibcon#about to read 6, iclass 5, count 0 2006.203.07:42:01.78#ibcon#read 6, iclass 5, count 0 2006.203.07:42:01.78#ibcon#end of sib2, iclass 5, count 0 2006.203.07:42:01.78#ibcon#*after write, iclass 5, count 0 2006.203.07:42:01.78#ibcon#*before return 0, iclass 5, count 0 2006.203.07:42:01.78#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.203.07:42:01.78#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.203.07:42:01.78#ibcon#about to clear, iclass 5 cls_cnt 0 2006.203.07:42:01.78#ibcon#cleared, iclass 5 cls_cnt 0 2006.203.07:42:01.78$vc4f8/valo=8,852.99 2006.203.07:42:01.78#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.203.07:42:01.78#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.203.07:42:01.78#ibcon#ireg 17 cls_cnt 0 2006.203.07:42:01.78#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.203.07:42:01.78#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.203.07:42:01.78#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.203.07:42:01.78#ibcon#enter wrdev, iclass 7, count 0 2006.203.07:42:01.78#ibcon#first serial, iclass 7, count 0 2006.203.07:42:01.78#ibcon#enter sib2, iclass 7, count 0 2006.203.07:42:01.78#ibcon#flushed, iclass 7, count 0 2006.203.07:42:01.78#ibcon#about to write, iclass 7, count 0 2006.203.07:42:01.78#ibcon#wrote, iclass 7, count 0 2006.203.07:42:01.78#ibcon#about to read 3, iclass 7, count 0 2006.203.07:42:01.81#ibcon#read 3, iclass 7, count 0 2006.203.07:42:01.81#ibcon#about to read 4, iclass 7, count 0 2006.203.07:42:01.81#ibcon#read 4, iclass 7, count 0 2006.203.07:42:01.81#ibcon#about to read 5, iclass 7, count 0 2006.203.07:42:01.81#ibcon#read 5, iclass 7, count 0 2006.203.07:42:01.81#ibcon#about to read 6, iclass 7, count 0 2006.203.07:42:01.81#ibcon#read 6, iclass 7, count 0 2006.203.07:42:01.81#ibcon#end of sib2, iclass 7, count 0 2006.203.07:42:01.81#ibcon#*mode == 0, iclass 7, count 0 2006.203.07:42:01.81#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.203.07:42:01.81#ibcon#[26=FRQ=08,852.99\r\n] 2006.203.07:42:01.81#ibcon#*before write, iclass 7, count 0 2006.203.07:42:01.81#ibcon#enter sib2, iclass 7, count 0 2006.203.07:42:01.81#ibcon#flushed, iclass 7, count 0 2006.203.07:42:01.81#ibcon#about to write, iclass 7, count 0 2006.203.07:42:01.81#ibcon#wrote, iclass 7, count 0 2006.203.07:42:01.81#ibcon#about to read 3, iclass 7, count 0 2006.203.07:42:01.85#ibcon#read 3, iclass 7, count 0 2006.203.07:42:01.85#ibcon#about to read 4, iclass 7, count 0 2006.203.07:42:01.85#ibcon#read 4, iclass 7, count 0 2006.203.07:42:01.85#ibcon#about to read 5, iclass 7, count 0 2006.203.07:42:01.85#ibcon#read 5, iclass 7, count 0 2006.203.07:42:01.85#ibcon#about to read 6, iclass 7, count 0 2006.203.07:42:01.85#ibcon#read 6, iclass 7, count 0 2006.203.07:42:01.85#ibcon#end of sib2, iclass 7, count 0 2006.203.07:42:01.85#ibcon#*after write, iclass 7, count 0 2006.203.07:42:01.85#ibcon#*before return 0, iclass 7, count 0 2006.203.07:42:01.85#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.203.07:42:01.85#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.203.07:42:01.85#ibcon#about to clear, iclass 7 cls_cnt 0 2006.203.07:42:01.85#ibcon#cleared, iclass 7 cls_cnt 0 2006.203.07:42:01.85$vc4f8/va=8,6 2006.203.07:42:01.85#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.203.07:42:01.85#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.203.07:42:01.85#ibcon#ireg 11 cls_cnt 2 2006.203.07:42:01.85#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.203.07:42:01.90#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.203.07:42:01.90#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.203.07:42:01.90#ibcon#enter wrdev, iclass 11, count 2 2006.203.07:42:01.90#ibcon#first serial, iclass 11, count 2 2006.203.07:42:01.90#ibcon#enter sib2, iclass 11, count 2 2006.203.07:42:01.90#ibcon#flushed, iclass 11, count 2 2006.203.07:42:01.90#ibcon#about to write, iclass 11, count 2 2006.203.07:42:01.90#ibcon#wrote, iclass 11, count 2 2006.203.07:42:01.90#ibcon#about to read 3, iclass 11, count 2 2006.203.07:42:01.92#ibcon#read 3, iclass 11, count 2 2006.203.07:42:01.92#ibcon#about to read 4, iclass 11, count 2 2006.203.07:42:01.92#ibcon#read 4, iclass 11, count 2 2006.203.07:42:01.92#ibcon#about to read 5, iclass 11, count 2 2006.203.07:42:01.92#ibcon#read 5, iclass 11, count 2 2006.203.07:42:01.92#ibcon#about to read 6, iclass 11, count 2 2006.203.07:42:01.92#ibcon#read 6, iclass 11, count 2 2006.203.07:42:01.92#ibcon#end of sib2, iclass 11, count 2 2006.203.07:42:01.92#ibcon#*mode == 0, iclass 11, count 2 2006.203.07:42:01.92#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.203.07:42:01.92#ibcon#[25=AT08-06\r\n] 2006.203.07:42:01.92#ibcon#*before write, iclass 11, count 2 2006.203.07:42:01.92#ibcon#enter sib2, iclass 11, count 2 2006.203.07:42:01.92#ibcon#flushed, iclass 11, count 2 2006.203.07:42:01.92#ibcon#about to write, iclass 11, count 2 2006.203.07:42:01.92#ibcon#wrote, iclass 11, count 2 2006.203.07:42:01.92#ibcon#about to read 3, iclass 11, count 2 2006.203.07:42:01.95#ibcon#read 3, iclass 11, count 2 2006.203.07:42:01.95#ibcon#about to read 4, iclass 11, count 2 2006.203.07:42:01.95#ibcon#read 4, iclass 11, count 2 2006.203.07:42:01.95#ibcon#about to read 5, iclass 11, count 2 2006.203.07:42:01.95#ibcon#read 5, iclass 11, count 2 2006.203.07:42:01.95#ibcon#about to read 6, iclass 11, count 2 2006.203.07:42:01.95#ibcon#read 6, iclass 11, count 2 2006.203.07:42:01.95#ibcon#end of sib2, iclass 11, count 2 2006.203.07:42:01.95#ibcon#*after write, iclass 11, count 2 2006.203.07:42:01.95#ibcon#*before return 0, iclass 11, count 2 2006.203.07:42:01.95#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.203.07:42:01.95#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.203.07:42:01.95#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.203.07:42:01.95#ibcon#ireg 7 cls_cnt 0 2006.203.07:42:01.95#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.203.07:42:02.07#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.203.07:42:02.07#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.203.07:42:02.07#ibcon#enter wrdev, iclass 11, count 0 2006.203.07:42:02.07#ibcon#first serial, iclass 11, count 0 2006.203.07:42:02.07#ibcon#enter sib2, iclass 11, count 0 2006.203.07:42:02.07#ibcon#flushed, iclass 11, count 0 2006.203.07:42:02.07#ibcon#about to write, iclass 11, count 0 2006.203.07:42:02.07#ibcon#wrote, iclass 11, count 0 2006.203.07:42:02.07#ibcon#about to read 3, iclass 11, count 0 2006.203.07:42:02.09#ibcon#read 3, iclass 11, count 0 2006.203.07:42:02.09#ibcon#about to read 4, iclass 11, count 0 2006.203.07:42:02.09#ibcon#read 4, iclass 11, count 0 2006.203.07:42:02.09#ibcon#about to read 5, iclass 11, count 0 2006.203.07:42:02.09#ibcon#read 5, iclass 11, count 0 2006.203.07:42:02.09#ibcon#about to read 6, iclass 11, count 0 2006.203.07:42:02.09#ibcon#read 6, iclass 11, count 0 2006.203.07:42:02.09#ibcon#end of sib2, iclass 11, count 0 2006.203.07:42:02.09#ibcon#*mode == 0, iclass 11, count 0 2006.203.07:42:02.09#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.203.07:42:02.09#ibcon#[25=USB\r\n] 2006.203.07:42:02.09#ibcon#*before write, iclass 11, count 0 2006.203.07:42:02.09#ibcon#enter sib2, iclass 11, count 0 2006.203.07:42:02.09#ibcon#flushed, iclass 11, count 0 2006.203.07:42:02.09#ibcon#about to write, iclass 11, count 0 2006.203.07:42:02.09#ibcon#wrote, iclass 11, count 0 2006.203.07:42:02.09#ibcon#about to read 3, iclass 11, count 0 2006.203.07:42:02.12#ibcon#read 3, iclass 11, count 0 2006.203.07:42:02.12#ibcon#about to read 4, iclass 11, count 0 2006.203.07:42:02.12#ibcon#read 4, iclass 11, count 0 2006.203.07:42:02.12#ibcon#about to read 5, iclass 11, count 0 2006.203.07:42:02.12#ibcon#read 5, iclass 11, count 0 2006.203.07:42:02.12#ibcon#about to read 6, iclass 11, count 0 2006.203.07:42:02.12#ibcon#read 6, iclass 11, count 0 2006.203.07:42:02.12#ibcon#end of sib2, iclass 11, count 0 2006.203.07:42:02.12#ibcon#*after write, iclass 11, count 0 2006.203.07:42:02.12#ibcon#*before return 0, iclass 11, count 0 2006.203.07:42:02.12#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.203.07:42:02.12#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.203.07:42:02.12#ibcon#about to clear, iclass 11 cls_cnt 0 2006.203.07:42:02.12#ibcon#cleared, iclass 11 cls_cnt 0 2006.203.07:42:02.12$vc4f8/vblo=1,632.99 2006.203.07:42:02.12#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.203.07:42:02.12#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.203.07:42:02.12#ibcon#ireg 17 cls_cnt 0 2006.203.07:42:02.12#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.203.07:42:02.12#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.203.07:42:02.12#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.203.07:42:02.12#ibcon#enter wrdev, iclass 13, count 0 2006.203.07:42:02.12#ibcon#first serial, iclass 13, count 0 2006.203.07:42:02.12#ibcon#enter sib2, iclass 13, count 0 2006.203.07:42:02.12#ibcon#flushed, iclass 13, count 0 2006.203.07:42:02.12#ibcon#about to write, iclass 13, count 0 2006.203.07:42:02.12#ibcon#wrote, iclass 13, count 0 2006.203.07:42:02.12#ibcon#about to read 3, iclass 13, count 0 2006.203.07:42:02.14#ibcon#read 3, iclass 13, count 0 2006.203.07:42:02.14#ibcon#about to read 4, iclass 13, count 0 2006.203.07:42:02.14#ibcon#read 4, iclass 13, count 0 2006.203.07:42:02.14#ibcon#about to read 5, iclass 13, count 0 2006.203.07:42:02.14#ibcon#read 5, iclass 13, count 0 2006.203.07:42:02.14#ibcon#about to read 6, iclass 13, count 0 2006.203.07:42:02.14#ibcon#read 6, iclass 13, count 0 2006.203.07:42:02.14#ibcon#end of sib2, iclass 13, count 0 2006.203.07:42:02.14#ibcon#*mode == 0, iclass 13, count 0 2006.203.07:42:02.14#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.203.07:42:02.14#ibcon#[28=FRQ=01,632.99\r\n] 2006.203.07:42:02.14#ibcon#*before write, iclass 13, count 0 2006.203.07:42:02.14#ibcon#enter sib2, iclass 13, count 0 2006.203.07:42:02.14#ibcon#flushed, iclass 13, count 0 2006.203.07:42:02.14#ibcon#about to write, iclass 13, count 0 2006.203.07:42:02.14#ibcon#wrote, iclass 13, count 0 2006.203.07:42:02.14#ibcon#about to read 3, iclass 13, count 0 2006.203.07:42:02.18#ibcon#read 3, iclass 13, count 0 2006.203.07:42:02.18#ibcon#about to read 4, iclass 13, count 0 2006.203.07:42:02.18#ibcon#read 4, iclass 13, count 0 2006.203.07:42:02.18#ibcon#about to read 5, iclass 13, count 0 2006.203.07:42:02.18#ibcon#read 5, iclass 13, count 0 2006.203.07:42:02.18#ibcon#about to read 6, iclass 13, count 0 2006.203.07:42:02.18#ibcon#read 6, iclass 13, count 0 2006.203.07:42:02.18#ibcon#end of sib2, iclass 13, count 0 2006.203.07:42:02.18#ibcon#*after write, iclass 13, count 0 2006.203.07:42:02.18#ibcon#*before return 0, iclass 13, count 0 2006.203.07:42:02.18#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.203.07:42:02.18#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.203.07:42:02.18#ibcon#about to clear, iclass 13 cls_cnt 0 2006.203.07:42:02.18#ibcon#cleared, iclass 13 cls_cnt 0 2006.203.07:42:02.18$vc4f8/vb=1,4 2006.203.07:42:02.18#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.203.07:42:02.18#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.203.07:42:02.18#ibcon#ireg 11 cls_cnt 2 2006.203.07:42:02.18#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.203.07:42:02.18#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.203.07:42:02.18#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.203.07:42:02.18#ibcon#enter wrdev, iclass 15, count 2 2006.203.07:42:02.18#ibcon#first serial, iclass 15, count 2 2006.203.07:42:02.18#ibcon#enter sib2, iclass 15, count 2 2006.203.07:42:02.18#ibcon#flushed, iclass 15, count 2 2006.203.07:42:02.18#ibcon#about to write, iclass 15, count 2 2006.203.07:42:02.18#ibcon#wrote, iclass 15, count 2 2006.203.07:42:02.18#ibcon#about to read 3, iclass 15, count 2 2006.203.07:42:02.20#ibcon#read 3, iclass 15, count 2 2006.203.07:42:02.20#ibcon#about to read 4, iclass 15, count 2 2006.203.07:42:02.20#ibcon#read 4, iclass 15, count 2 2006.203.07:42:02.20#ibcon#about to read 5, iclass 15, count 2 2006.203.07:42:02.20#ibcon#read 5, iclass 15, count 2 2006.203.07:42:02.20#ibcon#about to read 6, iclass 15, count 2 2006.203.07:42:02.20#ibcon#read 6, iclass 15, count 2 2006.203.07:42:02.20#ibcon#end of sib2, iclass 15, count 2 2006.203.07:42:02.20#ibcon#*mode == 0, iclass 15, count 2 2006.203.07:42:02.20#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.203.07:42:02.20#ibcon#[27=AT01-04\r\n] 2006.203.07:42:02.20#ibcon#*before write, iclass 15, count 2 2006.203.07:42:02.20#ibcon#enter sib2, iclass 15, count 2 2006.203.07:42:02.20#ibcon#flushed, iclass 15, count 2 2006.203.07:42:02.20#ibcon#about to write, iclass 15, count 2 2006.203.07:42:02.20#ibcon#wrote, iclass 15, count 2 2006.203.07:42:02.20#ibcon#about to read 3, iclass 15, count 2 2006.203.07:42:02.23#ibcon#read 3, iclass 15, count 2 2006.203.07:42:02.23#ibcon#about to read 4, iclass 15, count 2 2006.203.07:42:02.23#ibcon#read 4, iclass 15, count 2 2006.203.07:42:02.23#ibcon#about to read 5, iclass 15, count 2 2006.203.07:42:02.23#ibcon#read 5, iclass 15, count 2 2006.203.07:42:02.23#ibcon#about to read 6, iclass 15, count 2 2006.203.07:42:02.23#ibcon#read 6, iclass 15, count 2 2006.203.07:42:02.23#ibcon#end of sib2, iclass 15, count 2 2006.203.07:42:02.23#ibcon#*after write, iclass 15, count 2 2006.203.07:42:02.23#ibcon#*before return 0, iclass 15, count 2 2006.203.07:42:02.23#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.203.07:42:02.23#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.203.07:42:02.23#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.203.07:42:02.23#ibcon#ireg 7 cls_cnt 0 2006.203.07:42:02.23#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.203.07:42:02.35#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.203.07:42:02.35#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.203.07:42:02.35#ibcon#enter wrdev, iclass 15, count 0 2006.203.07:42:02.35#ibcon#first serial, iclass 15, count 0 2006.203.07:42:02.35#ibcon#enter sib2, iclass 15, count 0 2006.203.07:42:02.35#ibcon#flushed, iclass 15, count 0 2006.203.07:42:02.35#ibcon#about to write, iclass 15, count 0 2006.203.07:42:02.35#ibcon#wrote, iclass 15, count 0 2006.203.07:42:02.35#ibcon#about to read 3, iclass 15, count 0 2006.203.07:42:02.37#ibcon#read 3, iclass 15, count 0 2006.203.07:42:02.37#ibcon#about to read 4, iclass 15, count 0 2006.203.07:42:02.37#ibcon#read 4, iclass 15, count 0 2006.203.07:42:02.37#ibcon#about to read 5, iclass 15, count 0 2006.203.07:42:02.37#ibcon#read 5, iclass 15, count 0 2006.203.07:42:02.37#ibcon#about to read 6, iclass 15, count 0 2006.203.07:42:02.37#ibcon#read 6, iclass 15, count 0 2006.203.07:42:02.37#ibcon#end of sib2, iclass 15, count 0 2006.203.07:42:02.37#ibcon#*mode == 0, iclass 15, count 0 2006.203.07:42:02.37#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.203.07:42:02.37#ibcon#[27=USB\r\n] 2006.203.07:42:02.37#ibcon#*before write, iclass 15, count 0 2006.203.07:42:02.37#ibcon#enter sib2, iclass 15, count 0 2006.203.07:42:02.37#ibcon#flushed, iclass 15, count 0 2006.203.07:42:02.37#ibcon#about to write, iclass 15, count 0 2006.203.07:42:02.37#ibcon#wrote, iclass 15, count 0 2006.203.07:42:02.37#ibcon#about to read 3, iclass 15, count 0 2006.203.07:42:02.40#ibcon#read 3, iclass 15, count 0 2006.203.07:42:02.40#ibcon#about to read 4, iclass 15, count 0 2006.203.07:42:02.40#ibcon#read 4, iclass 15, count 0 2006.203.07:42:02.40#ibcon#about to read 5, iclass 15, count 0 2006.203.07:42:02.40#ibcon#read 5, iclass 15, count 0 2006.203.07:42:02.40#ibcon#about to read 6, iclass 15, count 0 2006.203.07:42:02.40#ibcon#read 6, iclass 15, count 0 2006.203.07:42:02.40#ibcon#end of sib2, iclass 15, count 0 2006.203.07:42:02.40#ibcon#*after write, iclass 15, count 0 2006.203.07:42:02.40#ibcon#*before return 0, iclass 15, count 0 2006.203.07:42:02.40#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.203.07:42:02.40#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.203.07:42:02.40#ibcon#about to clear, iclass 15 cls_cnt 0 2006.203.07:42:02.40#ibcon#cleared, iclass 15 cls_cnt 0 2006.203.07:42:02.40$vc4f8/vblo=2,640.99 2006.203.07:42:02.40#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.203.07:42:02.40#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.203.07:42:02.40#ibcon#ireg 17 cls_cnt 0 2006.203.07:42:02.40#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.203.07:42:02.40#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.203.07:42:02.40#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.203.07:42:02.40#ibcon#enter wrdev, iclass 17, count 0 2006.203.07:42:02.40#ibcon#first serial, iclass 17, count 0 2006.203.07:42:02.40#ibcon#enter sib2, iclass 17, count 0 2006.203.07:42:02.40#ibcon#flushed, iclass 17, count 0 2006.203.07:42:02.40#ibcon#about to write, iclass 17, count 0 2006.203.07:42:02.40#ibcon#wrote, iclass 17, count 0 2006.203.07:42:02.40#ibcon#about to read 3, iclass 17, count 0 2006.203.07:42:02.43#ibcon#read 3, iclass 17, count 0 2006.203.07:42:02.43#ibcon#about to read 4, iclass 17, count 0 2006.203.07:42:02.43#ibcon#read 4, iclass 17, count 0 2006.203.07:42:02.43#ibcon#about to read 5, iclass 17, count 0 2006.203.07:42:02.43#ibcon#read 5, iclass 17, count 0 2006.203.07:42:02.43#ibcon#about to read 6, iclass 17, count 0 2006.203.07:42:02.43#ibcon#read 6, iclass 17, count 0 2006.203.07:42:02.43#ibcon#end of sib2, iclass 17, count 0 2006.203.07:42:02.43#ibcon#*mode == 0, iclass 17, count 0 2006.203.07:42:02.43#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.203.07:42:02.43#ibcon#[28=FRQ=02,640.99\r\n] 2006.203.07:42:02.43#ibcon#*before write, iclass 17, count 0 2006.203.07:42:02.43#ibcon#enter sib2, iclass 17, count 0 2006.203.07:42:02.43#ibcon#flushed, iclass 17, count 0 2006.203.07:42:02.43#ibcon#about to write, iclass 17, count 0 2006.203.07:42:02.43#ibcon#wrote, iclass 17, count 0 2006.203.07:42:02.43#ibcon#about to read 3, iclass 17, count 0 2006.203.07:42:02.47#ibcon#read 3, iclass 17, count 0 2006.203.07:42:02.47#ibcon#about to read 4, iclass 17, count 0 2006.203.07:42:02.47#ibcon#read 4, iclass 17, count 0 2006.203.07:42:02.47#ibcon#about to read 5, iclass 17, count 0 2006.203.07:42:02.47#ibcon#read 5, iclass 17, count 0 2006.203.07:42:02.47#ibcon#about to read 6, iclass 17, count 0 2006.203.07:42:02.47#ibcon#read 6, iclass 17, count 0 2006.203.07:42:02.47#ibcon#end of sib2, iclass 17, count 0 2006.203.07:42:02.47#ibcon#*after write, iclass 17, count 0 2006.203.07:42:02.47#ibcon#*before return 0, iclass 17, count 0 2006.203.07:42:02.47#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.203.07:42:02.47#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.203.07:42:02.47#ibcon#about to clear, iclass 17 cls_cnt 0 2006.203.07:42:02.47#ibcon#cleared, iclass 17 cls_cnt 0 2006.203.07:42:02.47$vc4f8/vb=2,4 2006.203.07:42:02.47#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.203.07:42:02.47#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.203.07:42:02.47#ibcon#ireg 11 cls_cnt 2 2006.203.07:42:02.47#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.203.07:42:02.52#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.203.07:42:02.52#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.203.07:42:02.52#ibcon#enter wrdev, iclass 19, count 2 2006.203.07:42:02.52#ibcon#first serial, iclass 19, count 2 2006.203.07:42:02.52#ibcon#enter sib2, iclass 19, count 2 2006.203.07:42:02.52#ibcon#flushed, iclass 19, count 2 2006.203.07:42:02.52#ibcon#about to write, iclass 19, count 2 2006.203.07:42:02.52#ibcon#wrote, iclass 19, count 2 2006.203.07:42:02.52#ibcon#about to read 3, iclass 19, count 2 2006.203.07:42:02.54#ibcon#read 3, iclass 19, count 2 2006.203.07:42:02.54#ibcon#about to read 4, iclass 19, count 2 2006.203.07:42:02.54#ibcon#read 4, iclass 19, count 2 2006.203.07:42:02.54#ibcon#about to read 5, iclass 19, count 2 2006.203.07:42:02.54#ibcon#read 5, iclass 19, count 2 2006.203.07:42:02.54#ibcon#about to read 6, iclass 19, count 2 2006.203.07:42:02.54#ibcon#read 6, iclass 19, count 2 2006.203.07:42:02.54#ibcon#end of sib2, iclass 19, count 2 2006.203.07:42:02.54#ibcon#*mode == 0, iclass 19, count 2 2006.203.07:42:02.54#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.203.07:42:02.54#ibcon#[27=AT02-04\r\n] 2006.203.07:42:02.54#ibcon#*before write, iclass 19, count 2 2006.203.07:42:02.54#ibcon#enter sib2, iclass 19, count 2 2006.203.07:42:02.54#ibcon#flushed, iclass 19, count 2 2006.203.07:42:02.54#ibcon#about to write, iclass 19, count 2 2006.203.07:42:02.54#ibcon#wrote, iclass 19, count 2 2006.203.07:42:02.54#ibcon#about to read 3, iclass 19, count 2 2006.203.07:42:02.57#ibcon#read 3, iclass 19, count 2 2006.203.07:42:02.57#ibcon#about to read 4, iclass 19, count 2 2006.203.07:42:02.57#ibcon#read 4, iclass 19, count 2 2006.203.07:42:02.57#ibcon#about to read 5, iclass 19, count 2 2006.203.07:42:02.57#ibcon#read 5, iclass 19, count 2 2006.203.07:42:02.57#ibcon#about to read 6, iclass 19, count 2 2006.203.07:42:02.57#ibcon#read 6, iclass 19, count 2 2006.203.07:42:02.57#ibcon#end of sib2, iclass 19, count 2 2006.203.07:42:02.57#ibcon#*after write, iclass 19, count 2 2006.203.07:42:02.57#ibcon#*before return 0, iclass 19, count 2 2006.203.07:42:02.57#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.203.07:42:02.57#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.203.07:42:02.57#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.203.07:42:02.57#ibcon#ireg 7 cls_cnt 0 2006.203.07:42:02.57#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.203.07:42:02.69#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.203.07:42:02.69#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.203.07:42:02.69#ibcon#enter wrdev, iclass 19, count 0 2006.203.07:42:02.69#ibcon#first serial, iclass 19, count 0 2006.203.07:42:02.69#ibcon#enter sib2, iclass 19, count 0 2006.203.07:42:02.69#ibcon#flushed, iclass 19, count 0 2006.203.07:42:02.69#ibcon#about to write, iclass 19, count 0 2006.203.07:42:02.69#ibcon#wrote, iclass 19, count 0 2006.203.07:42:02.69#ibcon#about to read 3, iclass 19, count 0 2006.203.07:42:02.71#ibcon#read 3, iclass 19, count 0 2006.203.07:42:02.71#ibcon#about to read 4, iclass 19, count 0 2006.203.07:42:02.71#ibcon#read 4, iclass 19, count 0 2006.203.07:42:02.71#ibcon#about to read 5, iclass 19, count 0 2006.203.07:42:02.71#ibcon#read 5, iclass 19, count 0 2006.203.07:42:02.71#ibcon#about to read 6, iclass 19, count 0 2006.203.07:42:02.71#ibcon#read 6, iclass 19, count 0 2006.203.07:42:02.71#ibcon#end of sib2, iclass 19, count 0 2006.203.07:42:02.71#ibcon#*mode == 0, iclass 19, count 0 2006.203.07:42:02.71#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.203.07:42:02.71#ibcon#[27=USB\r\n] 2006.203.07:42:02.71#ibcon#*before write, iclass 19, count 0 2006.203.07:42:02.71#ibcon#enter sib2, iclass 19, count 0 2006.203.07:42:02.71#ibcon#flushed, iclass 19, count 0 2006.203.07:42:02.71#ibcon#about to write, iclass 19, count 0 2006.203.07:42:02.71#ibcon#wrote, iclass 19, count 0 2006.203.07:42:02.71#ibcon#about to read 3, iclass 19, count 0 2006.203.07:42:02.74#ibcon#read 3, iclass 19, count 0 2006.203.07:42:02.74#ibcon#about to read 4, iclass 19, count 0 2006.203.07:42:02.74#ibcon#read 4, iclass 19, count 0 2006.203.07:42:02.74#ibcon#about to read 5, iclass 19, count 0 2006.203.07:42:02.74#ibcon#read 5, iclass 19, count 0 2006.203.07:42:02.74#ibcon#about to read 6, iclass 19, count 0 2006.203.07:42:02.74#ibcon#read 6, iclass 19, count 0 2006.203.07:42:02.74#ibcon#end of sib2, iclass 19, count 0 2006.203.07:42:02.74#ibcon#*after write, iclass 19, count 0 2006.203.07:42:02.74#ibcon#*before return 0, iclass 19, count 0 2006.203.07:42:02.74#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.203.07:42:02.74#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.203.07:42:02.74#ibcon#about to clear, iclass 19 cls_cnt 0 2006.203.07:42:02.74#ibcon#cleared, iclass 19 cls_cnt 0 2006.203.07:42:02.74$vc4f8/vblo=3,656.99 2006.203.07:42:02.74#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.203.07:42:02.74#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.203.07:42:02.74#ibcon#ireg 17 cls_cnt 0 2006.203.07:42:02.74#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.203.07:42:02.74#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.203.07:42:02.74#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.203.07:42:02.74#ibcon#enter wrdev, iclass 21, count 0 2006.203.07:42:02.74#ibcon#first serial, iclass 21, count 0 2006.203.07:42:02.74#ibcon#enter sib2, iclass 21, count 0 2006.203.07:42:02.74#ibcon#flushed, iclass 21, count 0 2006.203.07:42:02.74#ibcon#about to write, iclass 21, count 0 2006.203.07:42:02.74#ibcon#wrote, iclass 21, count 0 2006.203.07:42:02.74#ibcon#about to read 3, iclass 21, count 0 2006.203.07:42:02.76#ibcon#read 3, iclass 21, count 0 2006.203.07:42:02.76#ibcon#about to read 4, iclass 21, count 0 2006.203.07:42:02.76#ibcon#read 4, iclass 21, count 0 2006.203.07:42:02.76#ibcon#about to read 5, iclass 21, count 0 2006.203.07:42:02.76#ibcon#read 5, iclass 21, count 0 2006.203.07:42:02.76#ibcon#about to read 6, iclass 21, count 0 2006.203.07:42:02.76#ibcon#read 6, iclass 21, count 0 2006.203.07:42:02.76#ibcon#end of sib2, iclass 21, count 0 2006.203.07:42:02.76#ibcon#*mode == 0, iclass 21, count 0 2006.203.07:42:02.76#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.203.07:42:02.76#ibcon#[28=FRQ=03,656.99\r\n] 2006.203.07:42:02.76#ibcon#*before write, iclass 21, count 0 2006.203.07:42:02.76#ibcon#enter sib2, iclass 21, count 0 2006.203.07:42:02.76#ibcon#flushed, iclass 21, count 0 2006.203.07:42:02.76#ibcon#about to write, iclass 21, count 0 2006.203.07:42:02.76#ibcon#wrote, iclass 21, count 0 2006.203.07:42:02.76#ibcon#about to read 3, iclass 21, count 0 2006.203.07:42:02.80#ibcon#read 3, iclass 21, count 0 2006.203.07:42:02.80#ibcon#about to read 4, iclass 21, count 0 2006.203.07:42:02.80#ibcon#read 4, iclass 21, count 0 2006.203.07:42:02.80#ibcon#about to read 5, iclass 21, count 0 2006.203.07:42:02.80#ibcon#read 5, iclass 21, count 0 2006.203.07:42:02.80#ibcon#about to read 6, iclass 21, count 0 2006.203.07:42:02.80#ibcon#read 6, iclass 21, count 0 2006.203.07:42:02.80#ibcon#end of sib2, iclass 21, count 0 2006.203.07:42:02.80#ibcon#*after write, iclass 21, count 0 2006.203.07:42:02.80#ibcon#*before return 0, iclass 21, count 0 2006.203.07:42:02.80#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.203.07:42:02.80#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.203.07:42:02.80#ibcon#about to clear, iclass 21 cls_cnt 0 2006.203.07:42:02.80#ibcon#cleared, iclass 21 cls_cnt 0 2006.203.07:42:02.80$vc4f8/vb=3,4 2006.203.07:42:02.80#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.203.07:42:02.80#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.203.07:42:02.80#ibcon#ireg 11 cls_cnt 2 2006.203.07:42:02.80#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.203.07:42:02.86#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.203.07:42:02.86#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.203.07:42:02.86#ibcon#enter wrdev, iclass 23, count 2 2006.203.07:42:02.86#ibcon#first serial, iclass 23, count 2 2006.203.07:42:02.86#ibcon#enter sib2, iclass 23, count 2 2006.203.07:42:02.86#ibcon#flushed, iclass 23, count 2 2006.203.07:42:02.86#ibcon#about to write, iclass 23, count 2 2006.203.07:42:02.86#ibcon#wrote, iclass 23, count 2 2006.203.07:42:02.86#ibcon#about to read 3, iclass 23, count 2 2006.203.07:42:02.88#ibcon#read 3, iclass 23, count 2 2006.203.07:42:02.88#ibcon#about to read 4, iclass 23, count 2 2006.203.07:42:02.88#ibcon#read 4, iclass 23, count 2 2006.203.07:42:02.88#ibcon#about to read 5, iclass 23, count 2 2006.203.07:42:02.88#ibcon#read 5, iclass 23, count 2 2006.203.07:42:02.88#ibcon#about to read 6, iclass 23, count 2 2006.203.07:42:02.88#ibcon#read 6, iclass 23, count 2 2006.203.07:42:02.88#ibcon#end of sib2, iclass 23, count 2 2006.203.07:42:02.88#ibcon#*mode == 0, iclass 23, count 2 2006.203.07:42:02.88#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.203.07:42:02.88#ibcon#[27=AT03-04\r\n] 2006.203.07:42:02.88#ibcon#*before write, iclass 23, count 2 2006.203.07:42:02.88#ibcon#enter sib2, iclass 23, count 2 2006.203.07:42:02.88#ibcon#flushed, iclass 23, count 2 2006.203.07:42:02.88#ibcon#about to write, iclass 23, count 2 2006.203.07:42:02.88#ibcon#wrote, iclass 23, count 2 2006.203.07:42:02.88#ibcon#about to read 3, iclass 23, count 2 2006.203.07:42:02.91#ibcon#read 3, iclass 23, count 2 2006.203.07:42:02.91#ibcon#about to read 4, iclass 23, count 2 2006.203.07:42:02.91#ibcon#read 4, iclass 23, count 2 2006.203.07:42:02.91#ibcon#about to read 5, iclass 23, count 2 2006.203.07:42:02.91#ibcon#read 5, iclass 23, count 2 2006.203.07:42:02.91#ibcon#about to read 6, iclass 23, count 2 2006.203.07:42:02.91#ibcon#read 6, iclass 23, count 2 2006.203.07:42:02.91#ibcon#end of sib2, iclass 23, count 2 2006.203.07:42:02.91#ibcon#*after write, iclass 23, count 2 2006.203.07:42:02.91#ibcon#*before return 0, iclass 23, count 2 2006.203.07:42:02.91#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.203.07:42:02.91#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.203.07:42:02.91#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.203.07:42:02.91#ibcon#ireg 7 cls_cnt 0 2006.203.07:42:02.91#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.203.07:42:03.03#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.203.07:42:03.03#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.203.07:42:03.03#ibcon#enter wrdev, iclass 23, count 0 2006.203.07:42:03.03#ibcon#first serial, iclass 23, count 0 2006.203.07:42:03.03#ibcon#enter sib2, iclass 23, count 0 2006.203.07:42:03.03#ibcon#flushed, iclass 23, count 0 2006.203.07:42:03.03#ibcon#about to write, iclass 23, count 0 2006.203.07:42:03.03#ibcon#wrote, iclass 23, count 0 2006.203.07:42:03.03#ibcon#about to read 3, iclass 23, count 0 2006.203.07:42:03.05#ibcon#read 3, iclass 23, count 0 2006.203.07:42:03.05#ibcon#about to read 4, iclass 23, count 0 2006.203.07:42:03.05#ibcon#read 4, iclass 23, count 0 2006.203.07:42:03.05#ibcon#about to read 5, iclass 23, count 0 2006.203.07:42:03.05#ibcon#read 5, iclass 23, count 0 2006.203.07:42:03.05#ibcon#about to read 6, iclass 23, count 0 2006.203.07:42:03.05#ibcon#read 6, iclass 23, count 0 2006.203.07:42:03.05#ibcon#end of sib2, iclass 23, count 0 2006.203.07:42:03.05#ibcon#*mode == 0, iclass 23, count 0 2006.203.07:42:03.05#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.203.07:42:03.05#ibcon#[27=USB\r\n] 2006.203.07:42:03.05#ibcon#*before write, iclass 23, count 0 2006.203.07:42:03.05#ibcon#enter sib2, iclass 23, count 0 2006.203.07:42:03.05#ibcon#flushed, iclass 23, count 0 2006.203.07:42:03.05#ibcon#about to write, iclass 23, count 0 2006.203.07:42:03.05#ibcon#wrote, iclass 23, count 0 2006.203.07:42:03.05#ibcon#about to read 3, iclass 23, count 0 2006.203.07:42:03.08#ibcon#read 3, iclass 23, count 0 2006.203.07:42:03.08#ibcon#about to read 4, iclass 23, count 0 2006.203.07:42:03.08#ibcon#read 4, iclass 23, count 0 2006.203.07:42:03.08#ibcon#about to read 5, iclass 23, count 0 2006.203.07:42:03.08#ibcon#read 5, iclass 23, count 0 2006.203.07:42:03.08#ibcon#about to read 6, iclass 23, count 0 2006.203.07:42:03.08#ibcon#read 6, iclass 23, count 0 2006.203.07:42:03.08#ibcon#end of sib2, iclass 23, count 0 2006.203.07:42:03.08#ibcon#*after write, iclass 23, count 0 2006.203.07:42:03.08#ibcon#*before return 0, iclass 23, count 0 2006.203.07:42:03.08#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.203.07:42:03.08#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.203.07:42:03.08#ibcon#about to clear, iclass 23 cls_cnt 0 2006.203.07:42:03.08#ibcon#cleared, iclass 23 cls_cnt 0 2006.203.07:42:03.08$vc4f8/vblo=4,712.99 2006.203.07:42:03.08#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.203.07:42:03.08#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.203.07:42:03.08#ibcon#ireg 17 cls_cnt 0 2006.203.07:42:03.08#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.203.07:42:03.08#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.203.07:42:03.08#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.203.07:42:03.08#ibcon#enter wrdev, iclass 25, count 0 2006.203.07:42:03.08#ibcon#first serial, iclass 25, count 0 2006.203.07:42:03.08#ibcon#enter sib2, iclass 25, count 0 2006.203.07:42:03.08#ibcon#flushed, iclass 25, count 0 2006.203.07:42:03.08#ibcon#about to write, iclass 25, count 0 2006.203.07:42:03.08#ibcon#wrote, iclass 25, count 0 2006.203.07:42:03.08#ibcon#about to read 3, iclass 25, count 0 2006.203.07:42:03.10#ibcon#read 3, iclass 25, count 0 2006.203.07:42:03.10#ibcon#about to read 4, iclass 25, count 0 2006.203.07:42:03.10#ibcon#read 4, iclass 25, count 0 2006.203.07:42:03.10#ibcon#about to read 5, iclass 25, count 0 2006.203.07:42:03.10#ibcon#read 5, iclass 25, count 0 2006.203.07:42:03.10#ibcon#about to read 6, iclass 25, count 0 2006.203.07:42:03.10#ibcon#read 6, iclass 25, count 0 2006.203.07:42:03.10#ibcon#end of sib2, iclass 25, count 0 2006.203.07:42:03.10#ibcon#*mode == 0, iclass 25, count 0 2006.203.07:42:03.10#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.203.07:42:03.10#ibcon#[28=FRQ=04,712.99\r\n] 2006.203.07:42:03.10#ibcon#*before write, iclass 25, count 0 2006.203.07:42:03.10#ibcon#enter sib2, iclass 25, count 0 2006.203.07:42:03.10#ibcon#flushed, iclass 25, count 0 2006.203.07:42:03.10#ibcon#about to write, iclass 25, count 0 2006.203.07:42:03.10#ibcon#wrote, iclass 25, count 0 2006.203.07:42:03.10#ibcon#about to read 3, iclass 25, count 0 2006.203.07:42:03.14#ibcon#read 3, iclass 25, count 0 2006.203.07:42:03.14#ibcon#about to read 4, iclass 25, count 0 2006.203.07:42:03.14#ibcon#read 4, iclass 25, count 0 2006.203.07:42:03.14#ibcon#about to read 5, iclass 25, count 0 2006.203.07:42:03.14#ibcon#read 5, iclass 25, count 0 2006.203.07:42:03.14#ibcon#about to read 6, iclass 25, count 0 2006.203.07:42:03.14#ibcon#read 6, iclass 25, count 0 2006.203.07:42:03.14#ibcon#end of sib2, iclass 25, count 0 2006.203.07:42:03.14#ibcon#*after write, iclass 25, count 0 2006.203.07:42:03.14#ibcon#*before return 0, iclass 25, count 0 2006.203.07:42:03.14#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.203.07:42:03.14#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.203.07:42:03.14#ibcon#about to clear, iclass 25 cls_cnt 0 2006.203.07:42:03.14#ibcon#cleared, iclass 25 cls_cnt 0 2006.203.07:42:03.14$vc4f8/vb=4,4 2006.203.07:42:03.14#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.203.07:42:03.14#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.203.07:42:03.14#ibcon#ireg 11 cls_cnt 2 2006.203.07:42:03.14#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.203.07:42:03.20#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.203.07:42:03.20#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.203.07:42:03.20#ibcon#enter wrdev, iclass 27, count 2 2006.203.07:42:03.20#ibcon#first serial, iclass 27, count 2 2006.203.07:42:03.20#ibcon#enter sib2, iclass 27, count 2 2006.203.07:42:03.20#ibcon#flushed, iclass 27, count 2 2006.203.07:42:03.20#ibcon#about to write, iclass 27, count 2 2006.203.07:42:03.20#ibcon#wrote, iclass 27, count 2 2006.203.07:42:03.20#ibcon#about to read 3, iclass 27, count 2 2006.203.07:42:03.22#ibcon#read 3, iclass 27, count 2 2006.203.07:42:03.22#ibcon#about to read 4, iclass 27, count 2 2006.203.07:42:03.22#ibcon#read 4, iclass 27, count 2 2006.203.07:42:03.22#ibcon#about to read 5, iclass 27, count 2 2006.203.07:42:03.22#ibcon#read 5, iclass 27, count 2 2006.203.07:42:03.22#ibcon#about to read 6, iclass 27, count 2 2006.203.07:42:03.22#ibcon#read 6, iclass 27, count 2 2006.203.07:42:03.22#ibcon#end of sib2, iclass 27, count 2 2006.203.07:42:03.22#ibcon#*mode == 0, iclass 27, count 2 2006.203.07:42:03.22#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.203.07:42:03.22#ibcon#[27=AT04-04\r\n] 2006.203.07:42:03.22#ibcon#*before write, iclass 27, count 2 2006.203.07:42:03.22#ibcon#enter sib2, iclass 27, count 2 2006.203.07:42:03.22#ibcon#flushed, iclass 27, count 2 2006.203.07:42:03.22#ibcon#about to write, iclass 27, count 2 2006.203.07:42:03.22#ibcon#wrote, iclass 27, count 2 2006.203.07:42:03.22#ibcon#about to read 3, iclass 27, count 2 2006.203.07:42:03.25#ibcon#read 3, iclass 27, count 2 2006.203.07:42:03.25#ibcon#about to read 4, iclass 27, count 2 2006.203.07:42:03.25#ibcon#read 4, iclass 27, count 2 2006.203.07:42:03.25#ibcon#about to read 5, iclass 27, count 2 2006.203.07:42:03.25#ibcon#read 5, iclass 27, count 2 2006.203.07:42:03.25#ibcon#about to read 6, iclass 27, count 2 2006.203.07:42:03.25#ibcon#read 6, iclass 27, count 2 2006.203.07:42:03.25#ibcon#end of sib2, iclass 27, count 2 2006.203.07:42:03.25#ibcon#*after write, iclass 27, count 2 2006.203.07:42:03.25#ibcon#*before return 0, iclass 27, count 2 2006.203.07:42:03.25#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.203.07:42:03.25#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.203.07:42:03.25#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.203.07:42:03.25#ibcon#ireg 7 cls_cnt 0 2006.203.07:42:03.25#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.203.07:42:03.37#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.203.07:42:03.37#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.203.07:42:03.37#ibcon#enter wrdev, iclass 27, count 0 2006.203.07:42:03.37#ibcon#first serial, iclass 27, count 0 2006.203.07:42:03.37#ibcon#enter sib2, iclass 27, count 0 2006.203.07:42:03.37#ibcon#flushed, iclass 27, count 0 2006.203.07:42:03.37#ibcon#about to write, iclass 27, count 0 2006.203.07:42:03.37#ibcon#wrote, iclass 27, count 0 2006.203.07:42:03.37#ibcon#about to read 3, iclass 27, count 0 2006.203.07:42:03.39#ibcon#read 3, iclass 27, count 0 2006.203.07:42:03.39#ibcon#about to read 4, iclass 27, count 0 2006.203.07:42:03.39#ibcon#read 4, iclass 27, count 0 2006.203.07:42:03.39#ibcon#about to read 5, iclass 27, count 0 2006.203.07:42:03.39#ibcon#read 5, iclass 27, count 0 2006.203.07:42:03.39#ibcon#about to read 6, iclass 27, count 0 2006.203.07:42:03.39#ibcon#read 6, iclass 27, count 0 2006.203.07:42:03.39#ibcon#end of sib2, iclass 27, count 0 2006.203.07:42:03.39#ibcon#*mode == 0, iclass 27, count 0 2006.203.07:42:03.39#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.203.07:42:03.39#ibcon#[27=USB\r\n] 2006.203.07:42:03.39#ibcon#*before write, iclass 27, count 0 2006.203.07:42:03.39#ibcon#enter sib2, iclass 27, count 0 2006.203.07:42:03.39#ibcon#flushed, iclass 27, count 0 2006.203.07:42:03.39#ibcon#about to write, iclass 27, count 0 2006.203.07:42:03.39#ibcon#wrote, iclass 27, count 0 2006.203.07:42:03.39#ibcon#about to read 3, iclass 27, count 0 2006.203.07:42:03.42#ibcon#read 3, iclass 27, count 0 2006.203.07:42:03.42#ibcon#about to read 4, iclass 27, count 0 2006.203.07:42:03.42#ibcon#read 4, iclass 27, count 0 2006.203.07:42:03.42#ibcon#about to read 5, iclass 27, count 0 2006.203.07:42:03.42#ibcon#read 5, iclass 27, count 0 2006.203.07:42:03.42#ibcon#about to read 6, iclass 27, count 0 2006.203.07:42:03.42#ibcon#read 6, iclass 27, count 0 2006.203.07:42:03.42#ibcon#end of sib2, iclass 27, count 0 2006.203.07:42:03.42#ibcon#*after write, iclass 27, count 0 2006.203.07:42:03.42#ibcon#*before return 0, iclass 27, count 0 2006.203.07:42:03.42#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.203.07:42:03.42#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.203.07:42:03.42#ibcon#about to clear, iclass 27 cls_cnt 0 2006.203.07:42:03.42#ibcon#cleared, iclass 27 cls_cnt 0 2006.203.07:42:03.42$vc4f8/vblo=5,744.99 2006.203.07:42:03.42#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.203.07:42:03.42#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.203.07:42:03.42#ibcon#ireg 17 cls_cnt 0 2006.203.07:42:03.42#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.203.07:42:03.42#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.203.07:42:03.42#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.203.07:42:03.42#ibcon#enter wrdev, iclass 29, count 0 2006.203.07:42:03.42#ibcon#first serial, iclass 29, count 0 2006.203.07:42:03.42#ibcon#enter sib2, iclass 29, count 0 2006.203.07:42:03.42#ibcon#flushed, iclass 29, count 0 2006.203.07:42:03.42#ibcon#about to write, iclass 29, count 0 2006.203.07:42:03.42#ibcon#wrote, iclass 29, count 0 2006.203.07:42:03.42#ibcon#about to read 3, iclass 29, count 0 2006.203.07:42:03.44#ibcon#read 3, iclass 29, count 0 2006.203.07:42:03.44#ibcon#about to read 4, iclass 29, count 0 2006.203.07:42:03.44#ibcon#read 4, iclass 29, count 0 2006.203.07:42:03.44#ibcon#about to read 5, iclass 29, count 0 2006.203.07:42:03.44#ibcon#read 5, iclass 29, count 0 2006.203.07:42:03.44#ibcon#about to read 6, iclass 29, count 0 2006.203.07:42:03.44#ibcon#read 6, iclass 29, count 0 2006.203.07:42:03.44#ibcon#end of sib2, iclass 29, count 0 2006.203.07:42:03.44#ibcon#*mode == 0, iclass 29, count 0 2006.203.07:42:03.44#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.203.07:42:03.44#ibcon#[28=FRQ=05,744.99\r\n] 2006.203.07:42:03.44#ibcon#*before write, iclass 29, count 0 2006.203.07:42:03.44#ibcon#enter sib2, iclass 29, count 0 2006.203.07:42:03.44#ibcon#flushed, iclass 29, count 0 2006.203.07:42:03.44#ibcon#about to write, iclass 29, count 0 2006.203.07:42:03.44#ibcon#wrote, iclass 29, count 0 2006.203.07:42:03.44#ibcon#about to read 3, iclass 29, count 0 2006.203.07:42:03.48#ibcon#read 3, iclass 29, count 0 2006.203.07:42:03.48#ibcon#about to read 4, iclass 29, count 0 2006.203.07:42:03.48#ibcon#read 4, iclass 29, count 0 2006.203.07:42:03.48#ibcon#about to read 5, iclass 29, count 0 2006.203.07:42:03.48#ibcon#read 5, iclass 29, count 0 2006.203.07:42:03.48#ibcon#about to read 6, iclass 29, count 0 2006.203.07:42:03.48#ibcon#read 6, iclass 29, count 0 2006.203.07:42:03.48#ibcon#end of sib2, iclass 29, count 0 2006.203.07:42:03.48#ibcon#*after write, iclass 29, count 0 2006.203.07:42:03.48#ibcon#*before return 0, iclass 29, count 0 2006.203.07:42:03.48#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.203.07:42:03.48#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.203.07:42:03.48#ibcon#about to clear, iclass 29 cls_cnt 0 2006.203.07:42:03.48#ibcon#cleared, iclass 29 cls_cnt 0 2006.203.07:42:03.48$vc4f8/vb=5,3 2006.203.07:42:03.48#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.203.07:42:03.48#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.203.07:42:03.48#ibcon#ireg 11 cls_cnt 2 2006.203.07:42:03.48#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.203.07:42:03.54#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.203.07:42:03.54#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.203.07:42:03.54#ibcon#enter wrdev, iclass 31, count 2 2006.203.07:42:03.54#ibcon#first serial, iclass 31, count 2 2006.203.07:42:03.54#ibcon#enter sib2, iclass 31, count 2 2006.203.07:42:03.54#ibcon#flushed, iclass 31, count 2 2006.203.07:42:03.54#ibcon#about to write, iclass 31, count 2 2006.203.07:42:03.54#ibcon#wrote, iclass 31, count 2 2006.203.07:42:03.54#ibcon#about to read 3, iclass 31, count 2 2006.203.07:42:03.56#ibcon#read 3, iclass 31, count 2 2006.203.07:42:03.56#ibcon#about to read 4, iclass 31, count 2 2006.203.07:42:03.56#ibcon#read 4, iclass 31, count 2 2006.203.07:42:03.56#ibcon#about to read 5, iclass 31, count 2 2006.203.07:42:03.56#ibcon#read 5, iclass 31, count 2 2006.203.07:42:03.56#ibcon#about to read 6, iclass 31, count 2 2006.203.07:42:03.56#ibcon#read 6, iclass 31, count 2 2006.203.07:42:03.56#ibcon#end of sib2, iclass 31, count 2 2006.203.07:42:03.56#ibcon#*mode == 0, iclass 31, count 2 2006.203.07:42:03.56#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.203.07:42:03.56#ibcon#[27=AT05-03\r\n] 2006.203.07:42:03.56#ibcon#*before write, iclass 31, count 2 2006.203.07:42:03.56#ibcon#enter sib2, iclass 31, count 2 2006.203.07:42:03.56#ibcon#flushed, iclass 31, count 2 2006.203.07:42:03.56#ibcon#about to write, iclass 31, count 2 2006.203.07:42:03.56#ibcon#wrote, iclass 31, count 2 2006.203.07:42:03.56#ibcon#about to read 3, iclass 31, count 2 2006.203.07:42:03.59#ibcon#read 3, iclass 31, count 2 2006.203.07:42:03.59#ibcon#about to read 4, iclass 31, count 2 2006.203.07:42:03.59#ibcon#read 4, iclass 31, count 2 2006.203.07:42:03.59#ibcon#about to read 5, iclass 31, count 2 2006.203.07:42:03.59#ibcon#read 5, iclass 31, count 2 2006.203.07:42:03.59#ibcon#about to read 6, iclass 31, count 2 2006.203.07:42:03.59#ibcon#read 6, iclass 31, count 2 2006.203.07:42:03.59#ibcon#end of sib2, iclass 31, count 2 2006.203.07:42:03.59#ibcon#*after write, iclass 31, count 2 2006.203.07:42:03.59#ibcon#*before return 0, iclass 31, count 2 2006.203.07:42:03.59#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.203.07:42:03.59#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.203.07:42:03.59#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.203.07:42:03.59#ibcon#ireg 7 cls_cnt 0 2006.203.07:42:03.59#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.203.07:42:03.71#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.203.07:42:03.71#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.203.07:42:03.71#ibcon#enter wrdev, iclass 31, count 0 2006.203.07:42:03.71#ibcon#first serial, iclass 31, count 0 2006.203.07:42:03.71#ibcon#enter sib2, iclass 31, count 0 2006.203.07:42:03.71#ibcon#flushed, iclass 31, count 0 2006.203.07:42:03.71#ibcon#about to write, iclass 31, count 0 2006.203.07:42:03.71#ibcon#wrote, iclass 31, count 0 2006.203.07:42:03.71#ibcon#about to read 3, iclass 31, count 0 2006.203.07:42:03.73#ibcon#read 3, iclass 31, count 0 2006.203.07:42:03.73#ibcon#about to read 4, iclass 31, count 0 2006.203.07:42:03.73#ibcon#read 4, iclass 31, count 0 2006.203.07:42:03.73#ibcon#about to read 5, iclass 31, count 0 2006.203.07:42:03.73#ibcon#read 5, iclass 31, count 0 2006.203.07:42:03.73#ibcon#about to read 6, iclass 31, count 0 2006.203.07:42:03.73#ibcon#read 6, iclass 31, count 0 2006.203.07:42:03.73#ibcon#end of sib2, iclass 31, count 0 2006.203.07:42:03.73#ibcon#*mode == 0, iclass 31, count 0 2006.203.07:42:03.73#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.203.07:42:03.73#ibcon#[27=USB\r\n] 2006.203.07:42:03.73#ibcon#*before write, iclass 31, count 0 2006.203.07:42:03.73#ibcon#enter sib2, iclass 31, count 0 2006.203.07:42:03.73#ibcon#flushed, iclass 31, count 0 2006.203.07:42:03.73#ibcon#about to write, iclass 31, count 0 2006.203.07:42:03.73#ibcon#wrote, iclass 31, count 0 2006.203.07:42:03.73#ibcon#about to read 3, iclass 31, count 0 2006.203.07:42:03.76#ibcon#read 3, iclass 31, count 0 2006.203.07:42:03.76#ibcon#about to read 4, iclass 31, count 0 2006.203.07:42:03.76#ibcon#read 4, iclass 31, count 0 2006.203.07:42:03.76#ibcon#about to read 5, iclass 31, count 0 2006.203.07:42:03.76#ibcon#read 5, iclass 31, count 0 2006.203.07:42:03.76#ibcon#about to read 6, iclass 31, count 0 2006.203.07:42:03.76#ibcon#read 6, iclass 31, count 0 2006.203.07:42:03.76#ibcon#end of sib2, iclass 31, count 0 2006.203.07:42:03.76#ibcon#*after write, iclass 31, count 0 2006.203.07:42:03.76#ibcon#*before return 0, iclass 31, count 0 2006.203.07:42:03.76#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.203.07:42:03.76#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.203.07:42:03.76#ibcon#about to clear, iclass 31 cls_cnt 0 2006.203.07:42:03.76#ibcon#cleared, iclass 31 cls_cnt 0 2006.203.07:42:03.76$vc4f8/vblo=6,752.99 2006.203.07:42:03.76#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.203.07:42:03.76#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.203.07:42:03.76#ibcon#ireg 17 cls_cnt 0 2006.203.07:42:03.76#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.203.07:42:03.76#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.203.07:42:03.76#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.203.07:42:03.76#ibcon#enter wrdev, iclass 33, count 0 2006.203.07:42:03.76#ibcon#first serial, iclass 33, count 0 2006.203.07:42:03.76#ibcon#enter sib2, iclass 33, count 0 2006.203.07:42:03.76#ibcon#flushed, iclass 33, count 0 2006.203.07:42:03.76#ibcon#about to write, iclass 33, count 0 2006.203.07:42:03.76#ibcon#wrote, iclass 33, count 0 2006.203.07:42:03.76#ibcon#about to read 3, iclass 33, count 0 2006.203.07:42:03.78#ibcon#read 3, iclass 33, count 0 2006.203.07:42:03.78#ibcon#about to read 4, iclass 33, count 0 2006.203.07:42:03.78#ibcon#read 4, iclass 33, count 0 2006.203.07:42:03.78#ibcon#about to read 5, iclass 33, count 0 2006.203.07:42:03.78#ibcon#read 5, iclass 33, count 0 2006.203.07:42:03.78#ibcon#about to read 6, iclass 33, count 0 2006.203.07:42:03.78#ibcon#read 6, iclass 33, count 0 2006.203.07:42:03.78#ibcon#end of sib2, iclass 33, count 0 2006.203.07:42:03.78#ibcon#*mode == 0, iclass 33, count 0 2006.203.07:42:03.78#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.203.07:42:03.78#ibcon#[28=FRQ=06,752.99\r\n] 2006.203.07:42:03.78#ibcon#*before write, iclass 33, count 0 2006.203.07:42:03.78#ibcon#enter sib2, iclass 33, count 0 2006.203.07:42:03.78#ibcon#flushed, iclass 33, count 0 2006.203.07:42:03.78#ibcon#about to write, iclass 33, count 0 2006.203.07:42:03.78#ibcon#wrote, iclass 33, count 0 2006.203.07:42:03.78#ibcon#about to read 3, iclass 33, count 0 2006.203.07:42:03.82#ibcon#read 3, iclass 33, count 0 2006.203.07:42:03.82#ibcon#about to read 4, iclass 33, count 0 2006.203.07:42:03.82#ibcon#read 4, iclass 33, count 0 2006.203.07:42:03.82#ibcon#about to read 5, iclass 33, count 0 2006.203.07:42:03.82#ibcon#read 5, iclass 33, count 0 2006.203.07:42:03.82#ibcon#about to read 6, iclass 33, count 0 2006.203.07:42:03.82#ibcon#read 6, iclass 33, count 0 2006.203.07:42:03.82#ibcon#end of sib2, iclass 33, count 0 2006.203.07:42:03.82#ibcon#*after write, iclass 33, count 0 2006.203.07:42:03.82#ibcon#*before return 0, iclass 33, count 0 2006.203.07:42:03.82#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.203.07:42:03.82#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.203.07:42:03.82#ibcon#about to clear, iclass 33 cls_cnt 0 2006.203.07:42:03.82#ibcon#cleared, iclass 33 cls_cnt 0 2006.203.07:42:03.82$vc4f8/vb=6,4 2006.203.07:42:03.82#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.203.07:42:03.82#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.203.07:42:03.82#ibcon#ireg 11 cls_cnt 2 2006.203.07:42:03.82#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.203.07:42:03.88#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.203.07:42:03.88#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.203.07:42:03.88#ibcon#enter wrdev, iclass 35, count 2 2006.203.07:42:03.88#ibcon#first serial, iclass 35, count 2 2006.203.07:42:03.88#ibcon#enter sib2, iclass 35, count 2 2006.203.07:42:03.88#ibcon#flushed, iclass 35, count 2 2006.203.07:42:03.88#ibcon#about to write, iclass 35, count 2 2006.203.07:42:03.88#ibcon#wrote, iclass 35, count 2 2006.203.07:42:03.88#ibcon#about to read 3, iclass 35, count 2 2006.203.07:42:03.90#ibcon#read 3, iclass 35, count 2 2006.203.07:42:03.90#ibcon#about to read 4, iclass 35, count 2 2006.203.07:42:03.90#ibcon#read 4, iclass 35, count 2 2006.203.07:42:03.90#ibcon#about to read 5, iclass 35, count 2 2006.203.07:42:03.90#ibcon#read 5, iclass 35, count 2 2006.203.07:42:03.90#ibcon#about to read 6, iclass 35, count 2 2006.203.07:42:03.90#ibcon#read 6, iclass 35, count 2 2006.203.07:42:03.90#ibcon#end of sib2, iclass 35, count 2 2006.203.07:42:03.90#ibcon#*mode == 0, iclass 35, count 2 2006.203.07:42:03.90#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.203.07:42:03.90#ibcon#[27=AT06-04\r\n] 2006.203.07:42:03.90#ibcon#*before write, iclass 35, count 2 2006.203.07:42:03.90#ibcon#enter sib2, iclass 35, count 2 2006.203.07:42:03.90#ibcon#flushed, iclass 35, count 2 2006.203.07:42:03.90#ibcon#about to write, iclass 35, count 2 2006.203.07:42:03.90#ibcon#wrote, iclass 35, count 2 2006.203.07:42:03.90#ibcon#about to read 3, iclass 35, count 2 2006.203.07:42:03.93#ibcon#read 3, iclass 35, count 2 2006.203.07:42:03.93#ibcon#about to read 4, iclass 35, count 2 2006.203.07:42:03.93#ibcon#read 4, iclass 35, count 2 2006.203.07:42:03.93#ibcon#about to read 5, iclass 35, count 2 2006.203.07:42:03.93#ibcon#read 5, iclass 35, count 2 2006.203.07:42:03.93#ibcon#about to read 6, iclass 35, count 2 2006.203.07:42:03.93#ibcon#read 6, iclass 35, count 2 2006.203.07:42:03.93#ibcon#end of sib2, iclass 35, count 2 2006.203.07:42:03.93#ibcon#*after write, iclass 35, count 2 2006.203.07:42:03.93#ibcon#*before return 0, iclass 35, count 2 2006.203.07:42:03.93#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.203.07:42:03.93#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.203.07:42:03.93#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.203.07:42:03.93#ibcon#ireg 7 cls_cnt 0 2006.203.07:42:03.93#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.203.07:42:04.05#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.203.07:42:04.05#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.203.07:42:04.05#ibcon#enter wrdev, iclass 35, count 0 2006.203.07:42:04.05#ibcon#first serial, iclass 35, count 0 2006.203.07:42:04.05#ibcon#enter sib2, iclass 35, count 0 2006.203.07:42:04.05#ibcon#flushed, iclass 35, count 0 2006.203.07:42:04.05#ibcon#about to write, iclass 35, count 0 2006.203.07:42:04.05#ibcon#wrote, iclass 35, count 0 2006.203.07:42:04.05#ibcon#about to read 3, iclass 35, count 0 2006.203.07:42:04.09#ibcon#read 3, iclass 35, count 0 2006.203.07:42:04.09#ibcon#about to read 4, iclass 35, count 0 2006.203.07:42:04.09#ibcon#read 4, iclass 35, count 0 2006.203.07:42:04.09#ibcon#about to read 5, iclass 35, count 0 2006.203.07:42:04.09#ibcon#read 5, iclass 35, count 0 2006.203.07:42:04.09#ibcon#about to read 6, iclass 35, count 0 2006.203.07:42:04.09#ibcon#read 6, iclass 35, count 0 2006.203.07:42:04.09#ibcon#end of sib2, iclass 35, count 0 2006.203.07:42:04.09#ibcon#*mode == 0, iclass 35, count 0 2006.203.07:42:04.09#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.203.07:42:04.09#ibcon#[27=USB\r\n] 2006.203.07:42:04.09#ibcon#*before write, iclass 35, count 0 2006.203.07:42:04.09#ibcon#enter sib2, iclass 35, count 0 2006.203.07:42:04.09#ibcon#flushed, iclass 35, count 0 2006.203.07:42:04.09#ibcon#about to write, iclass 35, count 0 2006.203.07:42:04.09#ibcon#wrote, iclass 35, count 0 2006.203.07:42:04.09#ibcon#about to read 3, iclass 35, count 0 2006.203.07:42:04.12#ibcon#read 3, iclass 35, count 0 2006.203.07:42:04.12#ibcon#about to read 4, iclass 35, count 0 2006.203.07:42:04.12#ibcon#read 4, iclass 35, count 0 2006.203.07:42:04.12#ibcon#about to read 5, iclass 35, count 0 2006.203.07:42:04.12#ibcon#read 5, iclass 35, count 0 2006.203.07:42:04.12#ibcon#about to read 6, iclass 35, count 0 2006.203.07:42:04.12#ibcon#read 6, iclass 35, count 0 2006.203.07:42:04.12#ibcon#end of sib2, iclass 35, count 0 2006.203.07:42:04.12#ibcon#*after write, iclass 35, count 0 2006.203.07:42:04.12#ibcon#*before return 0, iclass 35, count 0 2006.203.07:42:04.12#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.203.07:42:04.12#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.203.07:42:04.12#ibcon#about to clear, iclass 35 cls_cnt 0 2006.203.07:42:04.12#ibcon#cleared, iclass 35 cls_cnt 0 2006.203.07:42:04.12$vc4f8/vabw=wide 2006.203.07:42:04.12#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.203.07:42:04.12#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.203.07:42:04.12#ibcon#ireg 8 cls_cnt 0 2006.203.07:42:04.12#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.203.07:42:04.12#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.203.07:42:04.12#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.203.07:42:04.12#ibcon#enter wrdev, iclass 37, count 0 2006.203.07:42:04.12#ibcon#first serial, iclass 37, count 0 2006.203.07:42:04.12#ibcon#enter sib2, iclass 37, count 0 2006.203.07:42:04.12#ibcon#flushed, iclass 37, count 0 2006.203.07:42:04.12#ibcon#about to write, iclass 37, count 0 2006.203.07:42:04.12#ibcon#wrote, iclass 37, count 0 2006.203.07:42:04.12#ibcon#about to read 3, iclass 37, count 0 2006.203.07:42:04.14#ibcon#read 3, iclass 37, count 0 2006.203.07:42:04.14#ibcon#about to read 4, iclass 37, count 0 2006.203.07:42:04.14#ibcon#read 4, iclass 37, count 0 2006.203.07:42:04.14#ibcon#about to read 5, iclass 37, count 0 2006.203.07:42:04.14#ibcon#read 5, iclass 37, count 0 2006.203.07:42:04.14#ibcon#about to read 6, iclass 37, count 0 2006.203.07:42:04.14#ibcon#read 6, iclass 37, count 0 2006.203.07:42:04.14#ibcon#end of sib2, iclass 37, count 0 2006.203.07:42:04.14#ibcon#*mode == 0, iclass 37, count 0 2006.203.07:42:04.14#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.203.07:42:04.14#ibcon#[25=BW32\r\n] 2006.203.07:42:04.14#ibcon#*before write, iclass 37, count 0 2006.203.07:42:04.14#ibcon#enter sib2, iclass 37, count 0 2006.203.07:42:04.14#ibcon#flushed, iclass 37, count 0 2006.203.07:42:04.14#ibcon#about to write, iclass 37, count 0 2006.203.07:42:04.14#ibcon#wrote, iclass 37, count 0 2006.203.07:42:04.14#ibcon#about to read 3, iclass 37, count 0 2006.203.07:42:04.17#ibcon#read 3, iclass 37, count 0 2006.203.07:42:04.17#ibcon#about to read 4, iclass 37, count 0 2006.203.07:42:04.17#ibcon#read 4, iclass 37, count 0 2006.203.07:42:04.17#ibcon#about to read 5, iclass 37, count 0 2006.203.07:42:04.17#ibcon#read 5, iclass 37, count 0 2006.203.07:42:04.17#ibcon#about to read 6, iclass 37, count 0 2006.203.07:42:04.17#ibcon#read 6, iclass 37, count 0 2006.203.07:42:04.17#ibcon#end of sib2, iclass 37, count 0 2006.203.07:42:04.17#ibcon#*after write, iclass 37, count 0 2006.203.07:42:04.17#ibcon#*before return 0, iclass 37, count 0 2006.203.07:42:04.17#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.203.07:42:04.17#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.203.07:42:04.17#ibcon#about to clear, iclass 37 cls_cnt 0 2006.203.07:42:04.17#ibcon#cleared, iclass 37 cls_cnt 0 2006.203.07:42:04.17$vc4f8/vbbw=wide 2006.203.07:42:04.17#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.203.07:42:04.17#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.203.07:42:04.17#ibcon#ireg 8 cls_cnt 0 2006.203.07:42:04.17#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.203.07:42:04.24#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.203.07:42:04.24#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.203.07:42:04.24#ibcon#enter wrdev, iclass 39, count 0 2006.203.07:42:04.24#ibcon#first serial, iclass 39, count 0 2006.203.07:42:04.24#ibcon#enter sib2, iclass 39, count 0 2006.203.07:42:04.24#ibcon#flushed, iclass 39, count 0 2006.203.07:42:04.24#ibcon#about to write, iclass 39, count 0 2006.203.07:42:04.24#ibcon#wrote, iclass 39, count 0 2006.203.07:42:04.24#ibcon#about to read 3, iclass 39, count 0 2006.203.07:42:04.26#ibcon#read 3, iclass 39, count 0 2006.203.07:42:04.26#ibcon#about to read 4, iclass 39, count 0 2006.203.07:42:04.26#ibcon#read 4, iclass 39, count 0 2006.203.07:42:04.26#ibcon#about to read 5, iclass 39, count 0 2006.203.07:42:04.26#ibcon#read 5, iclass 39, count 0 2006.203.07:42:04.26#ibcon#about to read 6, iclass 39, count 0 2006.203.07:42:04.26#ibcon#read 6, iclass 39, count 0 2006.203.07:42:04.26#ibcon#end of sib2, iclass 39, count 0 2006.203.07:42:04.26#ibcon#*mode == 0, iclass 39, count 0 2006.203.07:42:04.26#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.203.07:42:04.26#ibcon#[27=BW32\r\n] 2006.203.07:42:04.26#ibcon#*before write, iclass 39, count 0 2006.203.07:42:04.26#ibcon#enter sib2, iclass 39, count 0 2006.203.07:42:04.26#ibcon#flushed, iclass 39, count 0 2006.203.07:42:04.26#ibcon#about to write, iclass 39, count 0 2006.203.07:42:04.26#ibcon#wrote, iclass 39, count 0 2006.203.07:42:04.26#ibcon#about to read 3, iclass 39, count 0 2006.203.07:42:04.29#ibcon#read 3, iclass 39, count 0 2006.203.07:42:04.29#ibcon#about to read 4, iclass 39, count 0 2006.203.07:42:04.29#ibcon#read 4, iclass 39, count 0 2006.203.07:42:04.29#ibcon#about to read 5, iclass 39, count 0 2006.203.07:42:04.29#ibcon#read 5, iclass 39, count 0 2006.203.07:42:04.29#ibcon#about to read 6, iclass 39, count 0 2006.203.07:42:04.29#ibcon#read 6, iclass 39, count 0 2006.203.07:42:04.29#ibcon#end of sib2, iclass 39, count 0 2006.203.07:42:04.29#ibcon#*after write, iclass 39, count 0 2006.203.07:42:04.29#ibcon#*before return 0, iclass 39, count 0 2006.203.07:42:04.29#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.203.07:42:04.29#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.203.07:42:04.29#ibcon#about to clear, iclass 39 cls_cnt 0 2006.203.07:42:04.29#ibcon#cleared, iclass 39 cls_cnt 0 2006.203.07:42:04.29$4f8m12a/ifd4f 2006.203.07:42:04.29$ifd4f/lo= 2006.203.07:42:04.29$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.203.07:42:04.29$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.203.07:42:04.29$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.203.07:42:04.29$ifd4f/patch= 2006.203.07:42:04.29$ifd4f/patch=lo1,a1,a2,a3,a4 2006.203.07:42:04.29$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.203.07:42:04.29$ifd4f/patch=lo3,a5,a6,a7,a8 2006.203.07:42:04.29$4f8m12a/"form=m,16.000,1:2 2006.203.07:42:04.29$4f8m12a/"tpicd 2006.203.07:42:04.29$4f8m12a/echo=off 2006.203.07:42:04.29$4f8m12a/xlog=off 2006.203.07:42:04.29:!2006.203.07:42:30 2006.203.07:42:14.14#trakl#Source acquired 2006.203.07:42:15.14#flagr#flagr/antenna,acquired 2006.203.07:42:30.00:preob 2006.203.07:42:31.14/onsource/TRACKING 2006.203.07:42:31.14:!2006.203.07:42:40 2006.203.07:42:40.00:data_valid=on 2006.203.07:42:40.00:midob 2006.203.07:42:40.14/onsource/TRACKING 2006.203.07:42:40.14/wx/23.92,1001.0,97 2006.203.07:42:40.25/cable/+6.4605E-03 2006.203.07:42:41.34/va/01,08,usb,yes,29,31 2006.203.07:42:41.34/va/02,07,usb,yes,29,31 2006.203.07:42:41.34/va/03,08,usb,yes,22,22 2006.203.07:42:41.34/va/04,07,usb,yes,30,32 2006.203.07:42:41.34/va/05,07,usb,yes,32,34 2006.203.07:42:41.34/va/06,06,usb,yes,31,31 2006.203.07:42:41.34/va/07,07,usb,yes,28,28 2006.203.07:42:41.34/va/08,06,usb,yes,34,34 2006.203.07:42:41.57/valo/01,532.99,yes,locked 2006.203.07:42:41.57/valo/02,572.99,yes,locked 2006.203.07:42:41.57/valo/03,672.99,yes,locked 2006.203.07:42:41.57/valo/04,832.99,yes,locked 2006.203.07:42:41.57/valo/05,652.99,yes,locked 2006.203.07:42:41.57/valo/06,772.99,yes,locked 2006.203.07:42:41.57/valo/07,832.99,yes,locked 2006.203.07:42:41.57/valo/08,852.99,yes,locked 2006.203.07:42:42.66/vb/01,04,usb,yes,28,27 2006.203.07:42:42.66/vb/02,04,usb,yes,30,31 2006.203.07:42:42.66/vb/03,04,usb,yes,27,30 2006.203.07:42:42.66/vb/04,04,usb,yes,27,28 2006.203.07:42:42.66/vb/05,03,usb,yes,33,37 2006.203.07:42:42.66/vb/06,04,usb,yes,27,30 2006.203.07:42:42.66/vb/07,04,usb,yes,29,29 2006.203.07:42:42.66/vb/08,04,usb,yes,27,30 2006.203.07:42:42.89/vblo/01,632.99,yes,locked 2006.203.07:42:42.89/vblo/02,640.99,yes,locked 2006.203.07:42:42.89/vblo/03,656.99,yes,locked 2006.203.07:42:42.89/vblo/04,712.99,yes,locked 2006.203.07:42:42.89/vblo/05,744.99,yes,locked 2006.203.07:42:42.89/vblo/06,752.99,yes,locked 2006.203.07:42:42.89/vblo/07,734.99,yes,locked 2006.203.07:42:42.89/vblo/08,744.99,yes,locked 2006.203.07:42:43.04/vabw/8 2006.203.07:42:43.19/vbbw/8 2006.203.07:42:43.29/xfe/off,on,16.2 2006.203.07:42:43.67/ifatt/23,28,28,28 2006.203.07:42:44.07/fmout-gps/S +4.54E-07 2006.203.07:42:44.11:!2006.203.07:43:40 2006.203.07:43:40.00:data_valid=off 2006.203.07:43:40.01:postob 2006.203.07:43:40.21/cable/+6.4591E-03 2006.203.07:43:40.22/wx/23.91,1001.1,98 2006.203.07:43:41.07/fmout-gps/S +4.53E-07 2006.203.07:43:41.08:scan_name=203-0745,k06203,60 2006.203.07:43:41.08:source=0823+033,082550.34,030924.5,2000.0,ccw 2006.203.07:43:41.14#flagr#flagr/antenna,new-source 2006.203.07:43:42.14:checkk5 2006.203.07:43:42.56/chk_autoobs//k5ts1/ autoobs is running! 2006.203.07:43:42.96/chk_autoobs//k5ts2/ autoobs is running! 2006.203.07:43:43.40/chk_autoobs//k5ts3/ autoobs is running! 2006.203.07:43:43.80/chk_autoobs//k5ts4/ autoobs is running! 2006.203.07:43:44.23/chk_obsdata//k5ts1/T2030742??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.07:43:44.85/chk_obsdata//k5ts2/T2030742??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.07:43:45.26/chk_obsdata//k5ts3/T2030742??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.07:43:45.66/chk_obsdata//k5ts4/T2030742??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.07:43:46.47/k5log//k5ts1_log_newline 2006.203.07:43:47.23/k5log//k5ts2_log_newline 2006.203.07:43:48.16/k5log//k5ts3_log_newline 2006.203.07:43:48.89/k5log//k5ts4_log_newline 2006.203.07:43:48.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.203.07:43:48.91:4f8m12a=1 2006.203.07:43:48.91$4f8m12a/echo=on 2006.203.07:43:48.91$4f8m12a/pcalon 2006.203.07:43:48.91$pcalon/"no phase cal control is implemented here 2006.203.07:43:48.91$4f8m12a/"tpicd=stop 2006.203.07:43:48.91$4f8m12a/vc4f8 2006.203.07:43:48.91$vc4f8/valo=1,532.99 2006.203.07:43:48.92#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.203.07:43:48.92#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.203.07:43:48.92#ibcon#ireg 17 cls_cnt 0 2006.203.07:43:48.92#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.203.07:43:48.92#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.203.07:43:48.92#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.203.07:43:48.92#ibcon#enter wrdev, iclass 3, count 0 2006.203.07:43:48.92#ibcon#first serial, iclass 3, count 0 2006.203.07:43:48.92#ibcon#enter sib2, iclass 3, count 0 2006.203.07:43:48.92#ibcon#flushed, iclass 3, count 0 2006.203.07:43:48.92#ibcon#about to write, iclass 3, count 0 2006.203.07:43:48.92#ibcon#wrote, iclass 3, count 0 2006.203.07:43:48.92#ibcon#about to read 3, iclass 3, count 0 2006.203.07:43:48.96#ibcon#read 3, iclass 3, count 0 2006.203.07:43:48.96#ibcon#about to read 4, iclass 3, count 0 2006.203.07:43:48.96#ibcon#read 4, iclass 3, count 0 2006.203.07:43:48.96#ibcon#about to read 5, iclass 3, count 0 2006.203.07:43:48.96#ibcon#read 5, iclass 3, count 0 2006.203.07:43:48.96#ibcon#about to read 6, iclass 3, count 0 2006.203.07:43:48.96#ibcon#read 6, iclass 3, count 0 2006.203.07:43:48.96#ibcon#end of sib2, iclass 3, count 0 2006.203.07:43:48.96#ibcon#*mode == 0, iclass 3, count 0 2006.203.07:43:48.96#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.203.07:43:48.96#ibcon#[26=FRQ=01,532.99\r\n] 2006.203.07:43:48.96#ibcon#*before write, iclass 3, count 0 2006.203.07:43:48.96#ibcon#enter sib2, iclass 3, count 0 2006.203.07:43:48.96#ibcon#flushed, iclass 3, count 0 2006.203.07:43:48.96#ibcon#about to write, iclass 3, count 0 2006.203.07:43:48.96#ibcon#wrote, iclass 3, count 0 2006.203.07:43:48.96#ibcon#about to read 3, iclass 3, count 0 2006.203.07:43:49.00#ibcon#read 3, iclass 3, count 0 2006.203.07:43:49.00#ibcon#about to read 4, iclass 3, count 0 2006.203.07:43:49.00#ibcon#read 4, iclass 3, count 0 2006.203.07:43:49.00#ibcon#about to read 5, iclass 3, count 0 2006.203.07:43:49.00#ibcon#read 5, iclass 3, count 0 2006.203.07:43:49.00#ibcon#about to read 6, iclass 3, count 0 2006.203.07:43:49.00#ibcon#read 6, iclass 3, count 0 2006.203.07:43:49.00#ibcon#end of sib2, iclass 3, count 0 2006.203.07:43:49.00#ibcon#*after write, iclass 3, count 0 2006.203.07:43:49.00#ibcon#*before return 0, iclass 3, count 0 2006.203.07:43:49.00#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.203.07:43:49.00#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.203.07:43:49.00#ibcon#about to clear, iclass 3 cls_cnt 0 2006.203.07:43:49.00#ibcon#cleared, iclass 3 cls_cnt 0 2006.203.07:43:49.00$vc4f8/va=1,8 2006.203.07:43:49.00#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.203.07:43:49.00#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.203.07:43:49.00#ibcon#ireg 11 cls_cnt 2 2006.203.07:43:49.00#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.203.07:43:49.00#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.203.07:43:49.00#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.203.07:43:49.00#ibcon#enter wrdev, iclass 5, count 2 2006.203.07:43:49.00#ibcon#first serial, iclass 5, count 2 2006.203.07:43:49.00#ibcon#enter sib2, iclass 5, count 2 2006.203.07:43:49.00#ibcon#flushed, iclass 5, count 2 2006.203.07:43:49.00#ibcon#about to write, iclass 5, count 2 2006.203.07:43:49.00#ibcon#wrote, iclass 5, count 2 2006.203.07:43:49.00#ibcon#about to read 3, iclass 5, count 2 2006.203.07:43:49.02#ibcon#read 3, iclass 5, count 2 2006.203.07:43:49.02#ibcon#about to read 4, iclass 5, count 2 2006.203.07:43:49.02#ibcon#read 4, iclass 5, count 2 2006.203.07:43:49.02#ibcon#about to read 5, iclass 5, count 2 2006.203.07:43:49.02#ibcon#read 5, iclass 5, count 2 2006.203.07:43:49.02#ibcon#about to read 6, iclass 5, count 2 2006.203.07:43:49.02#ibcon#read 6, iclass 5, count 2 2006.203.07:43:49.02#ibcon#end of sib2, iclass 5, count 2 2006.203.07:43:49.02#ibcon#*mode == 0, iclass 5, count 2 2006.203.07:43:49.02#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.203.07:43:49.02#ibcon#[25=AT01-08\r\n] 2006.203.07:43:49.02#ibcon#*before write, iclass 5, count 2 2006.203.07:43:49.02#ibcon#enter sib2, iclass 5, count 2 2006.203.07:43:49.02#ibcon#flushed, iclass 5, count 2 2006.203.07:43:49.02#ibcon#about to write, iclass 5, count 2 2006.203.07:43:49.02#ibcon#wrote, iclass 5, count 2 2006.203.07:43:49.02#ibcon#about to read 3, iclass 5, count 2 2006.203.07:43:49.05#ibcon#read 3, iclass 5, count 2 2006.203.07:43:49.05#ibcon#about to read 4, iclass 5, count 2 2006.203.07:43:49.05#ibcon#read 4, iclass 5, count 2 2006.203.07:43:49.05#ibcon#about to read 5, iclass 5, count 2 2006.203.07:43:49.05#ibcon#read 5, iclass 5, count 2 2006.203.07:43:49.05#ibcon#about to read 6, iclass 5, count 2 2006.203.07:43:49.05#ibcon#read 6, iclass 5, count 2 2006.203.07:43:49.05#ibcon#end of sib2, iclass 5, count 2 2006.203.07:43:49.05#ibcon#*after write, iclass 5, count 2 2006.203.07:43:49.05#ibcon#*before return 0, iclass 5, count 2 2006.203.07:43:49.05#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.203.07:43:49.05#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.203.07:43:49.05#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.203.07:43:49.05#ibcon#ireg 7 cls_cnt 0 2006.203.07:43:49.05#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.203.07:43:49.17#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.203.07:43:49.17#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.203.07:43:49.17#ibcon#enter wrdev, iclass 5, count 0 2006.203.07:43:49.17#ibcon#first serial, iclass 5, count 0 2006.203.07:43:49.17#ibcon#enter sib2, iclass 5, count 0 2006.203.07:43:49.17#ibcon#flushed, iclass 5, count 0 2006.203.07:43:49.17#ibcon#about to write, iclass 5, count 0 2006.203.07:43:49.17#ibcon#wrote, iclass 5, count 0 2006.203.07:43:49.17#ibcon#about to read 3, iclass 5, count 0 2006.203.07:43:49.19#ibcon#read 3, iclass 5, count 0 2006.203.07:43:49.19#ibcon#about to read 4, iclass 5, count 0 2006.203.07:43:49.19#ibcon#read 4, iclass 5, count 0 2006.203.07:43:49.19#ibcon#about to read 5, iclass 5, count 0 2006.203.07:43:49.19#ibcon#read 5, iclass 5, count 0 2006.203.07:43:49.19#ibcon#about to read 6, iclass 5, count 0 2006.203.07:43:49.19#ibcon#read 6, iclass 5, count 0 2006.203.07:43:49.19#ibcon#end of sib2, iclass 5, count 0 2006.203.07:43:49.19#ibcon#*mode == 0, iclass 5, count 0 2006.203.07:43:49.19#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.203.07:43:49.19#ibcon#[25=USB\r\n] 2006.203.07:43:49.19#ibcon#*before write, iclass 5, count 0 2006.203.07:43:49.19#ibcon#enter sib2, iclass 5, count 0 2006.203.07:43:49.19#ibcon#flushed, iclass 5, count 0 2006.203.07:43:49.19#ibcon#about to write, iclass 5, count 0 2006.203.07:43:49.19#ibcon#wrote, iclass 5, count 0 2006.203.07:43:49.19#ibcon#about to read 3, iclass 5, count 0 2006.203.07:43:49.22#ibcon#read 3, iclass 5, count 0 2006.203.07:43:49.22#ibcon#about to read 4, iclass 5, count 0 2006.203.07:43:49.22#ibcon#read 4, iclass 5, count 0 2006.203.07:43:49.22#ibcon#about to read 5, iclass 5, count 0 2006.203.07:43:49.22#ibcon#read 5, iclass 5, count 0 2006.203.07:43:49.22#ibcon#about to read 6, iclass 5, count 0 2006.203.07:43:49.22#ibcon#read 6, iclass 5, count 0 2006.203.07:43:49.22#ibcon#end of sib2, iclass 5, count 0 2006.203.07:43:49.22#ibcon#*after write, iclass 5, count 0 2006.203.07:43:49.22#ibcon#*before return 0, iclass 5, count 0 2006.203.07:43:49.22#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.203.07:43:49.22#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.203.07:43:49.22#ibcon#about to clear, iclass 5 cls_cnt 0 2006.203.07:43:49.22#ibcon#cleared, iclass 5 cls_cnt 0 2006.203.07:43:49.22$vc4f8/valo=2,572.99 2006.203.07:43:49.22#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.203.07:43:49.22#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.203.07:43:49.22#ibcon#ireg 17 cls_cnt 0 2006.203.07:43:49.22#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.203.07:43:49.22#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.203.07:43:49.22#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.203.07:43:49.22#ibcon#enter wrdev, iclass 7, count 0 2006.203.07:43:49.22#ibcon#first serial, iclass 7, count 0 2006.203.07:43:49.22#ibcon#enter sib2, iclass 7, count 0 2006.203.07:43:49.22#ibcon#flushed, iclass 7, count 0 2006.203.07:43:49.22#ibcon#about to write, iclass 7, count 0 2006.203.07:43:49.22#ibcon#wrote, iclass 7, count 0 2006.203.07:43:49.22#ibcon#about to read 3, iclass 7, count 0 2006.203.07:43:49.25#ibcon#read 3, iclass 7, count 0 2006.203.07:43:49.25#ibcon#about to read 4, iclass 7, count 0 2006.203.07:43:49.25#ibcon#read 4, iclass 7, count 0 2006.203.07:43:49.25#ibcon#about to read 5, iclass 7, count 0 2006.203.07:43:49.25#ibcon#read 5, iclass 7, count 0 2006.203.07:43:49.25#ibcon#about to read 6, iclass 7, count 0 2006.203.07:43:49.25#ibcon#read 6, iclass 7, count 0 2006.203.07:43:49.25#ibcon#end of sib2, iclass 7, count 0 2006.203.07:43:49.25#ibcon#*mode == 0, iclass 7, count 0 2006.203.07:43:49.25#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.203.07:43:49.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.203.07:43:49.25#ibcon#*before write, iclass 7, count 0 2006.203.07:43:49.25#ibcon#enter sib2, iclass 7, count 0 2006.203.07:43:49.25#ibcon#flushed, iclass 7, count 0 2006.203.07:43:49.25#ibcon#about to write, iclass 7, count 0 2006.203.07:43:49.25#ibcon#wrote, iclass 7, count 0 2006.203.07:43:49.25#ibcon#about to read 3, iclass 7, count 0 2006.203.07:43:49.29#ibcon#read 3, iclass 7, count 0 2006.203.07:43:49.29#ibcon#about to read 4, iclass 7, count 0 2006.203.07:43:49.29#ibcon#read 4, iclass 7, count 0 2006.203.07:43:49.29#ibcon#about to read 5, iclass 7, count 0 2006.203.07:43:49.29#ibcon#read 5, iclass 7, count 0 2006.203.07:43:49.29#ibcon#about to read 6, iclass 7, count 0 2006.203.07:43:49.29#ibcon#read 6, iclass 7, count 0 2006.203.07:43:49.29#ibcon#end of sib2, iclass 7, count 0 2006.203.07:43:49.29#ibcon#*after write, iclass 7, count 0 2006.203.07:43:49.29#ibcon#*before return 0, iclass 7, count 0 2006.203.07:43:49.29#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.203.07:43:49.29#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.203.07:43:49.29#ibcon#about to clear, iclass 7 cls_cnt 0 2006.203.07:43:49.29#ibcon#cleared, iclass 7 cls_cnt 0 2006.203.07:43:49.29$vc4f8/va=2,7 2006.203.07:43:49.29#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.203.07:43:49.29#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.203.07:43:49.29#ibcon#ireg 11 cls_cnt 2 2006.203.07:43:49.29#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.203.07:43:49.34#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.203.07:43:49.34#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.203.07:43:49.34#ibcon#enter wrdev, iclass 11, count 2 2006.203.07:43:49.34#ibcon#first serial, iclass 11, count 2 2006.203.07:43:49.34#ibcon#enter sib2, iclass 11, count 2 2006.203.07:43:49.34#ibcon#flushed, iclass 11, count 2 2006.203.07:43:49.34#ibcon#about to write, iclass 11, count 2 2006.203.07:43:49.34#ibcon#wrote, iclass 11, count 2 2006.203.07:43:49.34#ibcon#about to read 3, iclass 11, count 2 2006.203.07:43:49.36#ibcon#read 3, iclass 11, count 2 2006.203.07:43:49.36#ibcon#about to read 4, iclass 11, count 2 2006.203.07:43:49.36#ibcon#read 4, iclass 11, count 2 2006.203.07:43:49.36#ibcon#about to read 5, iclass 11, count 2 2006.203.07:43:49.36#ibcon#read 5, iclass 11, count 2 2006.203.07:43:49.36#ibcon#about to read 6, iclass 11, count 2 2006.203.07:43:49.36#ibcon#read 6, iclass 11, count 2 2006.203.07:43:49.36#ibcon#end of sib2, iclass 11, count 2 2006.203.07:43:49.36#ibcon#*mode == 0, iclass 11, count 2 2006.203.07:43:49.36#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.203.07:43:49.36#ibcon#[25=AT02-07\r\n] 2006.203.07:43:49.36#ibcon#*before write, iclass 11, count 2 2006.203.07:43:49.36#ibcon#enter sib2, iclass 11, count 2 2006.203.07:43:49.36#ibcon#flushed, iclass 11, count 2 2006.203.07:43:49.36#ibcon#about to write, iclass 11, count 2 2006.203.07:43:49.36#ibcon#wrote, iclass 11, count 2 2006.203.07:43:49.36#ibcon#about to read 3, iclass 11, count 2 2006.203.07:43:49.39#ibcon#read 3, iclass 11, count 2 2006.203.07:43:49.39#ibcon#about to read 4, iclass 11, count 2 2006.203.07:43:49.39#ibcon#read 4, iclass 11, count 2 2006.203.07:43:49.39#ibcon#about to read 5, iclass 11, count 2 2006.203.07:43:49.39#ibcon#read 5, iclass 11, count 2 2006.203.07:43:49.39#ibcon#about to read 6, iclass 11, count 2 2006.203.07:43:49.39#ibcon#read 6, iclass 11, count 2 2006.203.07:43:49.39#ibcon#end of sib2, iclass 11, count 2 2006.203.07:43:49.39#ibcon#*after write, iclass 11, count 2 2006.203.07:43:49.39#ibcon#*before return 0, iclass 11, count 2 2006.203.07:43:49.39#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.203.07:43:49.39#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.203.07:43:49.39#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.203.07:43:49.39#ibcon#ireg 7 cls_cnt 0 2006.203.07:43:49.39#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.203.07:43:49.51#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.203.07:43:49.51#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.203.07:43:49.51#ibcon#enter wrdev, iclass 11, count 0 2006.203.07:43:49.51#ibcon#first serial, iclass 11, count 0 2006.203.07:43:49.51#ibcon#enter sib2, iclass 11, count 0 2006.203.07:43:49.51#ibcon#flushed, iclass 11, count 0 2006.203.07:43:49.51#ibcon#about to write, iclass 11, count 0 2006.203.07:43:49.51#ibcon#wrote, iclass 11, count 0 2006.203.07:43:49.51#ibcon#about to read 3, iclass 11, count 0 2006.203.07:43:49.53#ibcon#read 3, iclass 11, count 0 2006.203.07:43:49.53#ibcon#about to read 4, iclass 11, count 0 2006.203.07:43:49.53#ibcon#read 4, iclass 11, count 0 2006.203.07:43:49.53#ibcon#about to read 5, iclass 11, count 0 2006.203.07:43:49.53#ibcon#read 5, iclass 11, count 0 2006.203.07:43:49.53#ibcon#about to read 6, iclass 11, count 0 2006.203.07:43:49.53#ibcon#read 6, iclass 11, count 0 2006.203.07:43:49.53#ibcon#end of sib2, iclass 11, count 0 2006.203.07:43:49.53#ibcon#*mode == 0, iclass 11, count 0 2006.203.07:43:49.53#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.203.07:43:49.53#ibcon#[25=USB\r\n] 2006.203.07:43:49.53#ibcon#*before write, iclass 11, count 0 2006.203.07:43:49.53#ibcon#enter sib2, iclass 11, count 0 2006.203.07:43:49.53#ibcon#flushed, iclass 11, count 0 2006.203.07:43:49.53#ibcon#about to write, iclass 11, count 0 2006.203.07:43:49.53#ibcon#wrote, iclass 11, count 0 2006.203.07:43:49.53#ibcon#about to read 3, iclass 11, count 0 2006.203.07:43:49.56#ibcon#read 3, iclass 11, count 0 2006.203.07:43:49.56#ibcon#about to read 4, iclass 11, count 0 2006.203.07:43:49.56#ibcon#read 4, iclass 11, count 0 2006.203.07:43:49.56#ibcon#about to read 5, iclass 11, count 0 2006.203.07:43:49.56#ibcon#read 5, iclass 11, count 0 2006.203.07:43:49.56#ibcon#about to read 6, iclass 11, count 0 2006.203.07:43:49.56#ibcon#read 6, iclass 11, count 0 2006.203.07:43:49.56#ibcon#end of sib2, iclass 11, count 0 2006.203.07:43:49.56#ibcon#*after write, iclass 11, count 0 2006.203.07:43:49.56#ibcon#*before return 0, iclass 11, count 0 2006.203.07:43:49.56#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.203.07:43:49.56#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.203.07:43:49.56#ibcon#about to clear, iclass 11 cls_cnt 0 2006.203.07:43:49.56#ibcon#cleared, iclass 11 cls_cnt 0 2006.203.07:43:49.56$vc4f8/valo=3,672.99 2006.203.07:43:49.56#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.203.07:43:49.56#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.203.07:43:49.56#ibcon#ireg 17 cls_cnt 0 2006.203.07:43:49.56#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.203.07:43:49.56#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.203.07:43:49.56#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.203.07:43:49.56#ibcon#enter wrdev, iclass 13, count 0 2006.203.07:43:49.56#ibcon#first serial, iclass 13, count 0 2006.203.07:43:49.56#ibcon#enter sib2, iclass 13, count 0 2006.203.07:43:49.56#ibcon#flushed, iclass 13, count 0 2006.203.07:43:49.56#ibcon#about to write, iclass 13, count 0 2006.203.07:43:49.56#ibcon#wrote, iclass 13, count 0 2006.203.07:43:49.56#ibcon#about to read 3, iclass 13, count 0 2006.203.07:43:49.59#ibcon#read 3, iclass 13, count 0 2006.203.07:43:49.59#ibcon#about to read 4, iclass 13, count 0 2006.203.07:43:49.59#ibcon#read 4, iclass 13, count 0 2006.203.07:43:49.59#ibcon#about to read 5, iclass 13, count 0 2006.203.07:43:49.59#ibcon#read 5, iclass 13, count 0 2006.203.07:43:49.59#ibcon#about to read 6, iclass 13, count 0 2006.203.07:43:49.59#ibcon#read 6, iclass 13, count 0 2006.203.07:43:49.59#ibcon#end of sib2, iclass 13, count 0 2006.203.07:43:49.59#ibcon#*mode == 0, iclass 13, count 0 2006.203.07:43:49.59#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.203.07:43:49.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.203.07:43:49.59#ibcon#*before write, iclass 13, count 0 2006.203.07:43:49.59#ibcon#enter sib2, iclass 13, count 0 2006.203.07:43:49.59#ibcon#flushed, iclass 13, count 0 2006.203.07:43:49.59#ibcon#about to write, iclass 13, count 0 2006.203.07:43:49.59#ibcon#wrote, iclass 13, count 0 2006.203.07:43:49.59#ibcon#about to read 3, iclass 13, count 0 2006.203.07:43:49.63#ibcon#read 3, iclass 13, count 0 2006.203.07:43:49.63#ibcon#about to read 4, iclass 13, count 0 2006.203.07:43:49.63#ibcon#read 4, iclass 13, count 0 2006.203.07:43:49.63#ibcon#about to read 5, iclass 13, count 0 2006.203.07:43:49.63#ibcon#read 5, iclass 13, count 0 2006.203.07:43:49.63#ibcon#about to read 6, iclass 13, count 0 2006.203.07:43:49.63#ibcon#read 6, iclass 13, count 0 2006.203.07:43:49.63#ibcon#end of sib2, iclass 13, count 0 2006.203.07:43:49.63#ibcon#*after write, iclass 13, count 0 2006.203.07:43:49.63#ibcon#*before return 0, iclass 13, count 0 2006.203.07:43:49.63#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.203.07:43:49.63#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.203.07:43:49.63#ibcon#about to clear, iclass 13 cls_cnt 0 2006.203.07:43:49.63#ibcon#cleared, iclass 13 cls_cnt 0 2006.203.07:43:49.63$vc4f8/va=3,8 2006.203.07:43:49.63#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.203.07:43:49.63#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.203.07:43:49.63#ibcon#ireg 11 cls_cnt 2 2006.203.07:43:49.63#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.203.07:43:49.68#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.203.07:43:49.68#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.203.07:43:49.68#ibcon#enter wrdev, iclass 15, count 2 2006.203.07:43:49.68#ibcon#first serial, iclass 15, count 2 2006.203.07:43:49.68#ibcon#enter sib2, iclass 15, count 2 2006.203.07:43:49.68#ibcon#flushed, iclass 15, count 2 2006.203.07:43:49.68#ibcon#about to write, iclass 15, count 2 2006.203.07:43:49.68#ibcon#wrote, iclass 15, count 2 2006.203.07:43:49.68#ibcon#about to read 3, iclass 15, count 2 2006.203.07:43:49.70#ibcon#read 3, iclass 15, count 2 2006.203.07:43:49.70#ibcon#about to read 4, iclass 15, count 2 2006.203.07:43:49.70#ibcon#read 4, iclass 15, count 2 2006.203.07:43:49.70#ibcon#about to read 5, iclass 15, count 2 2006.203.07:43:49.70#ibcon#read 5, iclass 15, count 2 2006.203.07:43:49.70#ibcon#about to read 6, iclass 15, count 2 2006.203.07:43:49.70#ibcon#read 6, iclass 15, count 2 2006.203.07:43:49.70#ibcon#end of sib2, iclass 15, count 2 2006.203.07:43:49.70#ibcon#*mode == 0, iclass 15, count 2 2006.203.07:43:49.70#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.203.07:43:49.70#ibcon#[25=AT03-08\r\n] 2006.203.07:43:49.70#ibcon#*before write, iclass 15, count 2 2006.203.07:43:49.70#ibcon#enter sib2, iclass 15, count 2 2006.203.07:43:49.70#ibcon#flushed, iclass 15, count 2 2006.203.07:43:49.70#ibcon#about to write, iclass 15, count 2 2006.203.07:43:49.70#ibcon#wrote, iclass 15, count 2 2006.203.07:43:49.70#ibcon#about to read 3, iclass 15, count 2 2006.203.07:43:49.73#ibcon#read 3, iclass 15, count 2 2006.203.07:43:49.73#ibcon#about to read 4, iclass 15, count 2 2006.203.07:43:49.73#ibcon#read 4, iclass 15, count 2 2006.203.07:43:49.73#ibcon#about to read 5, iclass 15, count 2 2006.203.07:43:49.73#ibcon#read 5, iclass 15, count 2 2006.203.07:43:49.73#ibcon#about to read 6, iclass 15, count 2 2006.203.07:43:49.73#ibcon#read 6, iclass 15, count 2 2006.203.07:43:49.73#ibcon#end of sib2, iclass 15, count 2 2006.203.07:43:49.73#ibcon#*after write, iclass 15, count 2 2006.203.07:43:49.73#ibcon#*before return 0, iclass 15, count 2 2006.203.07:43:49.73#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.203.07:43:49.73#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.203.07:43:49.73#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.203.07:43:49.73#ibcon#ireg 7 cls_cnt 0 2006.203.07:43:49.73#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.203.07:43:49.85#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.203.07:43:49.85#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.203.07:43:49.85#ibcon#enter wrdev, iclass 15, count 0 2006.203.07:43:49.85#ibcon#first serial, iclass 15, count 0 2006.203.07:43:49.85#ibcon#enter sib2, iclass 15, count 0 2006.203.07:43:49.85#ibcon#flushed, iclass 15, count 0 2006.203.07:43:49.85#ibcon#about to write, iclass 15, count 0 2006.203.07:43:49.85#ibcon#wrote, iclass 15, count 0 2006.203.07:43:49.85#ibcon#about to read 3, iclass 15, count 0 2006.203.07:43:49.87#ibcon#read 3, iclass 15, count 0 2006.203.07:43:49.87#ibcon#about to read 4, iclass 15, count 0 2006.203.07:43:49.87#ibcon#read 4, iclass 15, count 0 2006.203.07:43:49.87#ibcon#about to read 5, iclass 15, count 0 2006.203.07:43:49.87#ibcon#read 5, iclass 15, count 0 2006.203.07:43:49.87#ibcon#about to read 6, iclass 15, count 0 2006.203.07:43:49.87#ibcon#read 6, iclass 15, count 0 2006.203.07:43:49.87#ibcon#end of sib2, iclass 15, count 0 2006.203.07:43:49.87#ibcon#*mode == 0, iclass 15, count 0 2006.203.07:43:49.87#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.203.07:43:49.87#ibcon#[25=USB\r\n] 2006.203.07:43:49.87#ibcon#*before write, iclass 15, count 0 2006.203.07:43:49.87#ibcon#enter sib2, iclass 15, count 0 2006.203.07:43:49.87#ibcon#flushed, iclass 15, count 0 2006.203.07:43:49.87#ibcon#about to write, iclass 15, count 0 2006.203.07:43:49.87#ibcon#wrote, iclass 15, count 0 2006.203.07:43:49.87#ibcon#about to read 3, iclass 15, count 0 2006.203.07:43:49.90#ibcon#read 3, iclass 15, count 0 2006.203.07:43:49.90#ibcon#about to read 4, iclass 15, count 0 2006.203.07:43:49.90#ibcon#read 4, iclass 15, count 0 2006.203.07:43:49.90#ibcon#about to read 5, iclass 15, count 0 2006.203.07:43:49.90#ibcon#read 5, iclass 15, count 0 2006.203.07:43:49.90#ibcon#about to read 6, iclass 15, count 0 2006.203.07:43:49.90#ibcon#read 6, iclass 15, count 0 2006.203.07:43:49.90#ibcon#end of sib2, iclass 15, count 0 2006.203.07:43:49.90#ibcon#*after write, iclass 15, count 0 2006.203.07:43:49.90#ibcon#*before return 0, iclass 15, count 0 2006.203.07:43:49.90#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.203.07:43:49.90#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.203.07:43:49.90#ibcon#about to clear, iclass 15 cls_cnt 0 2006.203.07:43:49.90#ibcon#cleared, iclass 15 cls_cnt 0 2006.203.07:43:49.90$vc4f8/valo=4,832.99 2006.203.07:43:49.90#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.203.07:43:49.90#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.203.07:43:49.90#ibcon#ireg 17 cls_cnt 0 2006.203.07:43:49.90#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.203.07:43:49.90#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.203.07:43:49.90#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.203.07:43:49.90#ibcon#enter wrdev, iclass 17, count 0 2006.203.07:43:49.90#ibcon#first serial, iclass 17, count 0 2006.203.07:43:49.90#ibcon#enter sib2, iclass 17, count 0 2006.203.07:43:49.90#ibcon#flushed, iclass 17, count 0 2006.203.07:43:49.90#ibcon#about to write, iclass 17, count 0 2006.203.07:43:49.90#ibcon#wrote, iclass 17, count 0 2006.203.07:43:49.90#ibcon#about to read 3, iclass 17, count 0 2006.203.07:43:49.92#ibcon#read 3, iclass 17, count 0 2006.203.07:43:49.92#ibcon#about to read 4, iclass 17, count 0 2006.203.07:43:49.92#ibcon#read 4, iclass 17, count 0 2006.203.07:43:49.92#ibcon#about to read 5, iclass 17, count 0 2006.203.07:43:49.92#ibcon#read 5, iclass 17, count 0 2006.203.07:43:49.92#ibcon#about to read 6, iclass 17, count 0 2006.203.07:43:49.92#ibcon#read 6, iclass 17, count 0 2006.203.07:43:49.92#ibcon#end of sib2, iclass 17, count 0 2006.203.07:43:49.92#ibcon#*mode == 0, iclass 17, count 0 2006.203.07:43:49.92#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.203.07:43:49.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.203.07:43:49.92#ibcon#*before write, iclass 17, count 0 2006.203.07:43:49.92#ibcon#enter sib2, iclass 17, count 0 2006.203.07:43:49.92#ibcon#flushed, iclass 17, count 0 2006.203.07:43:49.92#ibcon#about to write, iclass 17, count 0 2006.203.07:43:49.92#ibcon#wrote, iclass 17, count 0 2006.203.07:43:49.92#ibcon#about to read 3, iclass 17, count 0 2006.203.07:43:49.96#ibcon#read 3, iclass 17, count 0 2006.203.07:43:49.96#ibcon#about to read 4, iclass 17, count 0 2006.203.07:43:49.96#ibcon#read 4, iclass 17, count 0 2006.203.07:43:49.96#ibcon#about to read 5, iclass 17, count 0 2006.203.07:43:49.96#ibcon#read 5, iclass 17, count 0 2006.203.07:43:49.96#ibcon#about to read 6, iclass 17, count 0 2006.203.07:43:49.96#ibcon#read 6, iclass 17, count 0 2006.203.07:43:49.96#ibcon#end of sib2, iclass 17, count 0 2006.203.07:43:49.96#ibcon#*after write, iclass 17, count 0 2006.203.07:43:49.96#ibcon#*before return 0, iclass 17, count 0 2006.203.07:43:49.96#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.203.07:43:49.96#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.203.07:43:49.96#ibcon#about to clear, iclass 17 cls_cnt 0 2006.203.07:43:49.96#ibcon#cleared, iclass 17 cls_cnt 0 2006.203.07:43:49.96$vc4f8/va=4,7 2006.203.07:43:49.96#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.203.07:43:49.96#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.203.07:43:49.96#ibcon#ireg 11 cls_cnt 2 2006.203.07:43:49.96#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.203.07:43:50.02#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.203.07:43:50.02#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.203.07:43:50.02#ibcon#enter wrdev, iclass 19, count 2 2006.203.07:43:50.02#ibcon#first serial, iclass 19, count 2 2006.203.07:43:50.02#ibcon#enter sib2, iclass 19, count 2 2006.203.07:43:50.02#ibcon#flushed, iclass 19, count 2 2006.203.07:43:50.02#ibcon#about to write, iclass 19, count 2 2006.203.07:43:50.02#ibcon#wrote, iclass 19, count 2 2006.203.07:43:50.02#ibcon#about to read 3, iclass 19, count 2 2006.203.07:43:50.04#ibcon#read 3, iclass 19, count 2 2006.203.07:43:50.04#ibcon#about to read 4, iclass 19, count 2 2006.203.07:43:50.04#ibcon#read 4, iclass 19, count 2 2006.203.07:43:50.04#ibcon#about to read 5, iclass 19, count 2 2006.203.07:43:50.04#ibcon#read 5, iclass 19, count 2 2006.203.07:43:50.04#ibcon#about to read 6, iclass 19, count 2 2006.203.07:43:50.04#ibcon#read 6, iclass 19, count 2 2006.203.07:43:50.04#ibcon#end of sib2, iclass 19, count 2 2006.203.07:43:50.04#ibcon#*mode == 0, iclass 19, count 2 2006.203.07:43:50.04#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.203.07:43:50.04#ibcon#[25=AT04-07\r\n] 2006.203.07:43:50.04#ibcon#*before write, iclass 19, count 2 2006.203.07:43:50.04#ibcon#enter sib2, iclass 19, count 2 2006.203.07:43:50.04#ibcon#flushed, iclass 19, count 2 2006.203.07:43:50.04#ibcon#about to write, iclass 19, count 2 2006.203.07:43:50.04#ibcon#wrote, iclass 19, count 2 2006.203.07:43:50.04#ibcon#about to read 3, iclass 19, count 2 2006.203.07:43:50.07#ibcon#read 3, iclass 19, count 2 2006.203.07:43:50.07#ibcon#about to read 4, iclass 19, count 2 2006.203.07:43:50.07#ibcon#read 4, iclass 19, count 2 2006.203.07:43:50.07#ibcon#about to read 5, iclass 19, count 2 2006.203.07:43:50.07#ibcon#read 5, iclass 19, count 2 2006.203.07:43:50.07#ibcon#about to read 6, iclass 19, count 2 2006.203.07:43:50.07#ibcon#read 6, iclass 19, count 2 2006.203.07:43:50.07#ibcon#end of sib2, iclass 19, count 2 2006.203.07:43:50.07#ibcon#*after write, iclass 19, count 2 2006.203.07:43:50.07#ibcon#*before return 0, iclass 19, count 2 2006.203.07:43:50.07#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.203.07:43:50.07#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.203.07:43:50.07#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.203.07:43:50.07#ibcon#ireg 7 cls_cnt 0 2006.203.07:43:50.07#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.203.07:43:50.19#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.203.07:43:50.19#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.203.07:43:50.19#ibcon#enter wrdev, iclass 19, count 0 2006.203.07:43:50.19#ibcon#first serial, iclass 19, count 0 2006.203.07:43:50.19#ibcon#enter sib2, iclass 19, count 0 2006.203.07:43:50.19#ibcon#flushed, iclass 19, count 0 2006.203.07:43:50.19#ibcon#about to write, iclass 19, count 0 2006.203.07:43:50.19#ibcon#wrote, iclass 19, count 0 2006.203.07:43:50.19#ibcon#about to read 3, iclass 19, count 0 2006.203.07:43:50.21#ibcon#read 3, iclass 19, count 0 2006.203.07:43:50.21#ibcon#about to read 4, iclass 19, count 0 2006.203.07:43:50.21#ibcon#read 4, iclass 19, count 0 2006.203.07:43:50.21#ibcon#about to read 5, iclass 19, count 0 2006.203.07:43:50.21#ibcon#read 5, iclass 19, count 0 2006.203.07:43:50.21#ibcon#about to read 6, iclass 19, count 0 2006.203.07:43:50.21#ibcon#read 6, iclass 19, count 0 2006.203.07:43:50.21#ibcon#end of sib2, iclass 19, count 0 2006.203.07:43:50.21#ibcon#*mode == 0, iclass 19, count 0 2006.203.07:43:50.21#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.203.07:43:50.21#ibcon#[25=USB\r\n] 2006.203.07:43:50.21#ibcon#*before write, iclass 19, count 0 2006.203.07:43:50.21#ibcon#enter sib2, iclass 19, count 0 2006.203.07:43:50.21#ibcon#flushed, iclass 19, count 0 2006.203.07:43:50.21#ibcon#about to write, iclass 19, count 0 2006.203.07:43:50.21#ibcon#wrote, iclass 19, count 0 2006.203.07:43:50.21#ibcon#about to read 3, iclass 19, count 0 2006.203.07:43:50.24#ibcon#read 3, iclass 19, count 0 2006.203.07:43:50.24#ibcon#about to read 4, iclass 19, count 0 2006.203.07:43:50.24#ibcon#read 4, iclass 19, count 0 2006.203.07:43:50.24#ibcon#about to read 5, iclass 19, count 0 2006.203.07:43:50.24#ibcon#read 5, iclass 19, count 0 2006.203.07:43:50.24#ibcon#about to read 6, iclass 19, count 0 2006.203.07:43:50.24#ibcon#read 6, iclass 19, count 0 2006.203.07:43:50.24#ibcon#end of sib2, iclass 19, count 0 2006.203.07:43:50.24#ibcon#*after write, iclass 19, count 0 2006.203.07:43:50.24#ibcon#*before return 0, iclass 19, count 0 2006.203.07:43:50.24#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.203.07:43:50.24#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.203.07:43:50.24#ibcon#about to clear, iclass 19 cls_cnt 0 2006.203.07:43:50.24#ibcon#cleared, iclass 19 cls_cnt 0 2006.203.07:43:50.24$vc4f8/valo=5,652.99 2006.203.07:43:50.24#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.203.07:43:50.24#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.203.07:43:50.24#ibcon#ireg 17 cls_cnt 0 2006.203.07:43:50.24#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.203.07:43:50.24#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.203.07:43:50.24#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.203.07:43:50.24#ibcon#enter wrdev, iclass 21, count 0 2006.203.07:43:50.24#ibcon#first serial, iclass 21, count 0 2006.203.07:43:50.24#ibcon#enter sib2, iclass 21, count 0 2006.203.07:43:50.24#ibcon#flushed, iclass 21, count 0 2006.203.07:43:50.24#ibcon#about to write, iclass 21, count 0 2006.203.07:43:50.24#ibcon#wrote, iclass 21, count 0 2006.203.07:43:50.24#ibcon#about to read 3, iclass 21, count 0 2006.203.07:43:50.26#ibcon#read 3, iclass 21, count 0 2006.203.07:43:50.26#ibcon#about to read 4, iclass 21, count 0 2006.203.07:43:50.26#ibcon#read 4, iclass 21, count 0 2006.203.07:43:50.26#ibcon#about to read 5, iclass 21, count 0 2006.203.07:43:50.26#ibcon#read 5, iclass 21, count 0 2006.203.07:43:50.26#ibcon#about to read 6, iclass 21, count 0 2006.203.07:43:50.26#ibcon#read 6, iclass 21, count 0 2006.203.07:43:50.26#ibcon#end of sib2, iclass 21, count 0 2006.203.07:43:50.26#ibcon#*mode == 0, iclass 21, count 0 2006.203.07:43:50.26#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.203.07:43:50.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.203.07:43:50.26#ibcon#*before write, iclass 21, count 0 2006.203.07:43:50.26#ibcon#enter sib2, iclass 21, count 0 2006.203.07:43:50.26#ibcon#flushed, iclass 21, count 0 2006.203.07:43:50.26#ibcon#about to write, iclass 21, count 0 2006.203.07:43:50.26#ibcon#wrote, iclass 21, count 0 2006.203.07:43:50.26#ibcon#about to read 3, iclass 21, count 0 2006.203.07:43:50.30#ibcon#read 3, iclass 21, count 0 2006.203.07:43:50.30#ibcon#about to read 4, iclass 21, count 0 2006.203.07:43:50.30#ibcon#read 4, iclass 21, count 0 2006.203.07:43:50.30#ibcon#about to read 5, iclass 21, count 0 2006.203.07:43:50.30#ibcon#read 5, iclass 21, count 0 2006.203.07:43:50.30#ibcon#about to read 6, iclass 21, count 0 2006.203.07:43:50.30#ibcon#read 6, iclass 21, count 0 2006.203.07:43:50.30#ibcon#end of sib2, iclass 21, count 0 2006.203.07:43:50.30#ibcon#*after write, iclass 21, count 0 2006.203.07:43:50.30#ibcon#*before return 0, iclass 21, count 0 2006.203.07:43:50.30#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.203.07:43:50.30#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.203.07:43:50.30#ibcon#about to clear, iclass 21 cls_cnt 0 2006.203.07:43:50.30#ibcon#cleared, iclass 21 cls_cnt 0 2006.203.07:43:50.30$vc4f8/va=5,7 2006.203.07:43:50.30#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.203.07:43:50.30#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.203.07:43:50.30#ibcon#ireg 11 cls_cnt 2 2006.203.07:43:50.30#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.203.07:43:50.36#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.203.07:43:50.36#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.203.07:43:50.36#ibcon#enter wrdev, iclass 23, count 2 2006.203.07:43:50.36#ibcon#first serial, iclass 23, count 2 2006.203.07:43:50.36#ibcon#enter sib2, iclass 23, count 2 2006.203.07:43:50.36#ibcon#flushed, iclass 23, count 2 2006.203.07:43:50.36#ibcon#about to write, iclass 23, count 2 2006.203.07:43:50.36#ibcon#wrote, iclass 23, count 2 2006.203.07:43:50.36#ibcon#about to read 3, iclass 23, count 2 2006.203.07:43:50.38#ibcon#read 3, iclass 23, count 2 2006.203.07:43:50.38#ibcon#about to read 4, iclass 23, count 2 2006.203.07:43:50.38#ibcon#read 4, iclass 23, count 2 2006.203.07:43:50.38#ibcon#about to read 5, iclass 23, count 2 2006.203.07:43:50.38#ibcon#read 5, iclass 23, count 2 2006.203.07:43:50.38#ibcon#about to read 6, iclass 23, count 2 2006.203.07:43:50.38#ibcon#read 6, iclass 23, count 2 2006.203.07:43:50.38#ibcon#end of sib2, iclass 23, count 2 2006.203.07:43:50.38#ibcon#*mode == 0, iclass 23, count 2 2006.203.07:43:50.38#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.203.07:43:50.38#ibcon#[25=AT05-07\r\n] 2006.203.07:43:50.38#ibcon#*before write, iclass 23, count 2 2006.203.07:43:50.38#ibcon#enter sib2, iclass 23, count 2 2006.203.07:43:50.38#ibcon#flushed, iclass 23, count 2 2006.203.07:43:50.38#ibcon#about to write, iclass 23, count 2 2006.203.07:43:50.38#ibcon#wrote, iclass 23, count 2 2006.203.07:43:50.38#ibcon#about to read 3, iclass 23, count 2 2006.203.07:43:50.41#ibcon#read 3, iclass 23, count 2 2006.203.07:43:50.41#ibcon#about to read 4, iclass 23, count 2 2006.203.07:43:50.41#ibcon#read 4, iclass 23, count 2 2006.203.07:43:50.41#ibcon#about to read 5, iclass 23, count 2 2006.203.07:43:50.41#ibcon#read 5, iclass 23, count 2 2006.203.07:43:50.41#ibcon#about to read 6, iclass 23, count 2 2006.203.07:43:50.41#ibcon#read 6, iclass 23, count 2 2006.203.07:43:50.41#ibcon#end of sib2, iclass 23, count 2 2006.203.07:43:50.41#ibcon#*after write, iclass 23, count 2 2006.203.07:43:50.41#ibcon#*before return 0, iclass 23, count 2 2006.203.07:43:50.41#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.203.07:43:50.41#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.203.07:43:50.41#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.203.07:43:50.41#ibcon#ireg 7 cls_cnt 0 2006.203.07:43:50.41#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.203.07:43:50.46#abcon#<5=/05 1.8 2.9 23.91 981001.1\r\n> 2006.203.07:43:50.48#abcon#{5=INTERFACE CLEAR} 2006.203.07:43:50.53#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.203.07:43:50.53#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.203.07:43:50.53#ibcon#enter wrdev, iclass 23, count 0 2006.203.07:43:50.53#ibcon#first serial, iclass 23, count 0 2006.203.07:43:50.53#ibcon#enter sib2, iclass 23, count 0 2006.203.07:43:50.53#ibcon#flushed, iclass 23, count 0 2006.203.07:43:50.53#ibcon#about to write, iclass 23, count 0 2006.203.07:43:50.53#ibcon#wrote, iclass 23, count 0 2006.203.07:43:50.53#ibcon#about to read 3, iclass 23, count 0 2006.203.07:43:50.54#abcon#[5=S1D000X0/0*\r\n] 2006.203.07:43:50.55#ibcon#read 3, iclass 23, count 0 2006.203.07:43:50.55#ibcon#about to read 4, iclass 23, count 0 2006.203.07:43:50.55#ibcon#read 4, iclass 23, count 0 2006.203.07:43:50.55#ibcon#about to read 5, iclass 23, count 0 2006.203.07:43:50.55#ibcon#read 5, iclass 23, count 0 2006.203.07:43:50.55#ibcon#about to read 6, iclass 23, count 0 2006.203.07:43:50.55#ibcon#read 6, iclass 23, count 0 2006.203.07:43:50.55#ibcon#end of sib2, iclass 23, count 0 2006.203.07:43:50.55#ibcon#*mode == 0, iclass 23, count 0 2006.203.07:43:50.55#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.203.07:43:50.55#ibcon#[25=USB\r\n] 2006.203.07:43:50.55#ibcon#*before write, iclass 23, count 0 2006.203.07:43:50.55#ibcon#enter sib2, iclass 23, count 0 2006.203.07:43:50.55#ibcon#flushed, iclass 23, count 0 2006.203.07:43:50.55#ibcon#about to write, iclass 23, count 0 2006.203.07:43:50.55#ibcon#wrote, iclass 23, count 0 2006.203.07:43:50.55#ibcon#about to read 3, iclass 23, count 0 2006.203.07:43:50.58#ibcon#read 3, iclass 23, count 0 2006.203.07:43:50.58#ibcon#about to read 4, iclass 23, count 0 2006.203.07:43:50.58#ibcon#read 4, iclass 23, count 0 2006.203.07:43:50.58#ibcon#about to read 5, iclass 23, count 0 2006.203.07:43:50.58#ibcon#read 5, iclass 23, count 0 2006.203.07:43:50.58#ibcon#about to read 6, iclass 23, count 0 2006.203.07:43:50.58#ibcon#read 6, iclass 23, count 0 2006.203.07:43:50.58#ibcon#end of sib2, iclass 23, count 0 2006.203.07:43:50.58#ibcon#*after write, iclass 23, count 0 2006.203.07:43:50.58#ibcon#*before return 0, iclass 23, count 0 2006.203.07:43:50.58#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.203.07:43:50.58#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.203.07:43:50.58#ibcon#about to clear, iclass 23 cls_cnt 0 2006.203.07:43:50.58#ibcon#cleared, iclass 23 cls_cnt 0 2006.203.07:43:50.58$vc4f8/valo=6,772.99 2006.203.07:43:50.58#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.203.07:43:50.58#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.203.07:43:50.58#ibcon#ireg 17 cls_cnt 0 2006.203.07:43:50.58#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.203.07:43:50.58#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.203.07:43:50.58#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.203.07:43:50.58#ibcon#enter wrdev, iclass 29, count 0 2006.203.07:43:50.58#ibcon#first serial, iclass 29, count 0 2006.203.07:43:50.58#ibcon#enter sib2, iclass 29, count 0 2006.203.07:43:50.58#ibcon#flushed, iclass 29, count 0 2006.203.07:43:50.58#ibcon#about to write, iclass 29, count 0 2006.203.07:43:50.58#ibcon#wrote, iclass 29, count 0 2006.203.07:43:50.58#ibcon#about to read 3, iclass 29, count 0 2006.203.07:43:50.60#ibcon#read 3, iclass 29, count 0 2006.203.07:43:50.60#ibcon#about to read 4, iclass 29, count 0 2006.203.07:43:50.60#ibcon#read 4, iclass 29, count 0 2006.203.07:43:50.60#ibcon#about to read 5, iclass 29, count 0 2006.203.07:43:50.60#ibcon#read 5, iclass 29, count 0 2006.203.07:43:50.60#ibcon#about to read 6, iclass 29, count 0 2006.203.07:43:50.60#ibcon#read 6, iclass 29, count 0 2006.203.07:43:50.60#ibcon#end of sib2, iclass 29, count 0 2006.203.07:43:50.60#ibcon#*mode == 0, iclass 29, count 0 2006.203.07:43:50.60#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.203.07:43:50.60#ibcon#[26=FRQ=06,772.99\r\n] 2006.203.07:43:50.60#ibcon#*before write, iclass 29, count 0 2006.203.07:43:50.60#ibcon#enter sib2, iclass 29, count 0 2006.203.07:43:50.60#ibcon#flushed, iclass 29, count 0 2006.203.07:43:50.60#ibcon#about to write, iclass 29, count 0 2006.203.07:43:50.60#ibcon#wrote, iclass 29, count 0 2006.203.07:43:50.60#ibcon#about to read 3, iclass 29, count 0 2006.203.07:43:50.64#ibcon#read 3, iclass 29, count 0 2006.203.07:43:50.64#ibcon#about to read 4, iclass 29, count 0 2006.203.07:43:50.64#ibcon#read 4, iclass 29, count 0 2006.203.07:43:50.64#ibcon#about to read 5, iclass 29, count 0 2006.203.07:43:50.64#ibcon#read 5, iclass 29, count 0 2006.203.07:43:50.64#ibcon#about to read 6, iclass 29, count 0 2006.203.07:43:50.64#ibcon#read 6, iclass 29, count 0 2006.203.07:43:50.64#ibcon#end of sib2, iclass 29, count 0 2006.203.07:43:50.64#ibcon#*after write, iclass 29, count 0 2006.203.07:43:50.64#ibcon#*before return 0, iclass 29, count 0 2006.203.07:43:50.64#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.203.07:43:50.64#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.203.07:43:50.64#ibcon#about to clear, iclass 29 cls_cnt 0 2006.203.07:43:50.64#ibcon#cleared, iclass 29 cls_cnt 0 2006.203.07:43:50.64$vc4f8/va=6,6 2006.203.07:43:50.64#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.203.07:43:50.64#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.203.07:43:50.64#ibcon#ireg 11 cls_cnt 2 2006.203.07:43:50.64#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.203.07:43:50.70#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.203.07:43:50.70#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.203.07:43:50.70#ibcon#enter wrdev, iclass 31, count 2 2006.203.07:43:50.70#ibcon#first serial, iclass 31, count 2 2006.203.07:43:50.70#ibcon#enter sib2, iclass 31, count 2 2006.203.07:43:50.70#ibcon#flushed, iclass 31, count 2 2006.203.07:43:50.70#ibcon#about to write, iclass 31, count 2 2006.203.07:43:50.70#ibcon#wrote, iclass 31, count 2 2006.203.07:43:50.70#ibcon#about to read 3, iclass 31, count 2 2006.203.07:43:50.72#ibcon#read 3, iclass 31, count 2 2006.203.07:43:50.72#ibcon#about to read 4, iclass 31, count 2 2006.203.07:43:50.72#ibcon#read 4, iclass 31, count 2 2006.203.07:43:50.72#ibcon#about to read 5, iclass 31, count 2 2006.203.07:43:50.72#ibcon#read 5, iclass 31, count 2 2006.203.07:43:50.72#ibcon#about to read 6, iclass 31, count 2 2006.203.07:43:50.72#ibcon#read 6, iclass 31, count 2 2006.203.07:43:50.72#ibcon#end of sib2, iclass 31, count 2 2006.203.07:43:50.72#ibcon#*mode == 0, iclass 31, count 2 2006.203.07:43:50.72#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.203.07:43:50.72#ibcon#[25=AT06-06\r\n] 2006.203.07:43:50.72#ibcon#*before write, iclass 31, count 2 2006.203.07:43:50.72#ibcon#enter sib2, iclass 31, count 2 2006.203.07:43:50.72#ibcon#flushed, iclass 31, count 2 2006.203.07:43:50.72#ibcon#about to write, iclass 31, count 2 2006.203.07:43:50.72#ibcon#wrote, iclass 31, count 2 2006.203.07:43:50.72#ibcon#about to read 3, iclass 31, count 2 2006.203.07:43:50.75#ibcon#read 3, iclass 31, count 2 2006.203.07:43:50.75#ibcon#about to read 4, iclass 31, count 2 2006.203.07:43:50.75#ibcon#read 4, iclass 31, count 2 2006.203.07:43:50.75#ibcon#about to read 5, iclass 31, count 2 2006.203.07:43:50.75#ibcon#read 5, iclass 31, count 2 2006.203.07:43:50.75#ibcon#about to read 6, iclass 31, count 2 2006.203.07:43:50.75#ibcon#read 6, iclass 31, count 2 2006.203.07:43:50.75#ibcon#end of sib2, iclass 31, count 2 2006.203.07:43:50.75#ibcon#*after write, iclass 31, count 2 2006.203.07:43:50.75#ibcon#*before return 0, iclass 31, count 2 2006.203.07:43:50.75#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.203.07:43:50.75#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.203.07:43:50.75#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.203.07:43:50.75#ibcon#ireg 7 cls_cnt 0 2006.203.07:43:50.75#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.203.07:43:50.87#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.203.07:43:50.87#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.203.07:43:50.87#ibcon#enter wrdev, iclass 31, count 0 2006.203.07:43:50.87#ibcon#first serial, iclass 31, count 0 2006.203.07:43:50.87#ibcon#enter sib2, iclass 31, count 0 2006.203.07:43:50.87#ibcon#flushed, iclass 31, count 0 2006.203.07:43:50.87#ibcon#about to write, iclass 31, count 0 2006.203.07:43:50.87#ibcon#wrote, iclass 31, count 0 2006.203.07:43:50.87#ibcon#about to read 3, iclass 31, count 0 2006.203.07:43:50.89#ibcon#read 3, iclass 31, count 0 2006.203.07:43:50.89#ibcon#about to read 4, iclass 31, count 0 2006.203.07:43:50.89#ibcon#read 4, iclass 31, count 0 2006.203.07:43:50.89#ibcon#about to read 5, iclass 31, count 0 2006.203.07:43:50.89#ibcon#read 5, iclass 31, count 0 2006.203.07:43:50.89#ibcon#about to read 6, iclass 31, count 0 2006.203.07:43:50.89#ibcon#read 6, iclass 31, count 0 2006.203.07:43:50.89#ibcon#end of sib2, iclass 31, count 0 2006.203.07:43:50.89#ibcon#*mode == 0, iclass 31, count 0 2006.203.07:43:50.89#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.203.07:43:50.89#ibcon#[25=USB\r\n] 2006.203.07:43:50.89#ibcon#*before write, iclass 31, count 0 2006.203.07:43:50.89#ibcon#enter sib2, iclass 31, count 0 2006.203.07:43:50.89#ibcon#flushed, iclass 31, count 0 2006.203.07:43:50.89#ibcon#about to write, iclass 31, count 0 2006.203.07:43:50.89#ibcon#wrote, iclass 31, count 0 2006.203.07:43:50.89#ibcon#about to read 3, iclass 31, count 0 2006.203.07:43:50.92#ibcon#read 3, iclass 31, count 0 2006.203.07:43:50.92#ibcon#about to read 4, iclass 31, count 0 2006.203.07:43:50.92#ibcon#read 4, iclass 31, count 0 2006.203.07:43:50.92#ibcon#about to read 5, iclass 31, count 0 2006.203.07:43:50.92#ibcon#read 5, iclass 31, count 0 2006.203.07:43:50.92#ibcon#about to read 6, iclass 31, count 0 2006.203.07:43:50.92#ibcon#read 6, iclass 31, count 0 2006.203.07:43:50.92#ibcon#end of sib2, iclass 31, count 0 2006.203.07:43:50.92#ibcon#*after write, iclass 31, count 0 2006.203.07:43:50.92#ibcon#*before return 0, iclass 31, count 0 2006.203.07:43:50.92#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.203.07:43:50.92#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.203.07:43:50.92#ibcon#about to clear, iclass 31 cls_cnt 0 2006.203.07:43:50.92#ibcon#cleared, iclass 31 cls_cnt 0 2006.203.07:43:50.92$vc4f8/valo=7,832.99 2006.203.07:43:50.92#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.203.07:43:50.92#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.203.07:43:50.92#ibcon#ireg 17 cls_cnt 0 2006.203.07:43:50.92#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.203.07:43:50.92#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.203.07:43:50.92#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.203.07:43:50.92#ibcon#enter wrdev, iclass 33, count 0 2006.203.07:43:50.92#ibcon#first serial, iclass 33, count 0 2006.203.07:43:50.92#ibcon#enter sib2, iclass 33, count 0 2006.203.07:43:50.92#ibcon#flushed, iclass 33, count 0 2006.203.07:43:50.92#ibcon#about to write, iclass 33, count 0 2006.203.07:43:50.92#ibcon#wrote, iclass 33, count 0 2006.203.07:43:50.92#ibcon#about to read 3, iclass 33, count 0 2006.203.07:43:50.94#ibcon#read 3, iclass 33, count 0 2006.203.07:43:50.94#ibcon#about to read 4, iclass 33, count 0 2006.203.07:43:50.94#ibcon#read 4, iclass 33, count 0 2006.203.07:43:50.94#ibcon#about to read 5, iclass 33, count 0 2006.203.07:43:50.94#ibcon#read 5, iclass 33, count 0 2006.203.07:43:50.94#ibcon#about to read 6, iclass 33, count 0 2006.203.07:43:50.94#ibcon#read 6, iclass 33, count 0 2006.203.07:43:50.94#ibcon#end of sib2, iclass 33, count 0 2006.203.07:43:50.94#ibcon#*mode == 0, iclass 33, count 0 2006.203.07:43:50.94#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.203.07:43:50.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.203.07:43:50.94#ibcon#*before write, iclass 33, count 0 2006.203.07:43:50.94#ibcon#enter sib2, iclass 33, count 0 2006.203.07:43:50.94#ibcon#flushed, iclass 33, count 0 2006.203.07:43:50.94#ibcon#about to write, iclass 33, count 0 2006.203.07:43:50.94#ibcon#wrote, iclass 33, count 0 2006.203.07:43:50.94#ibcon#about to read 3, iclass 33, count 0 2006.203.07:43:50.98#ibcon#read 3, iclass 33, count 0 2006.203.07:43:50.98#ibcon#about to read 4, iclass 33, count 0 2006.203.07:43:50.98#ibcon#read 4, iclass 33, count 0 2006.203.07:43:50.98#ibcon#about to read 5, iclass 33, count 0 2006.203.07:43:50.98#ibcon#read 5, iclass 33, count 0 2006.203.07:43:50.98#ibcon#about to read 6, iclass 33, count 0 2006.203.07:43:50.98#ibcon#read 6, iclass 33, count 0 2006.203.07:43:50.98#ibcon#end of sib2, iclass 33, count 0 2006.203.07:43:50.98#ibcon#*after write, iclass 33, count 0 2006.203.07:43:50.98#ibcon#*before return 0, iclass 33, count 0 2006.203.07:43:50.98#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.203.07:43:50.98#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.203.07:43:50.98#ibcon#about to clear, iclass 33 cls_cnt 0 2006.203.07:43:50.98#ibcon#cleared, iclass 33 cls_cnt 0 2006.203.07:43:50.98$vc4f8/va=7,7 2006.203.07:43:50.98#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.203.07:43:50.98#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.203.07:43:50.98#ibcon#ireg 11 cls_cnt 2 2006.203.07:43:50.98#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.203.07:43:51.04#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.203.07:43:51.04#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.203.07:43:51.04#ibcon#enter wrdev, iclass 35, count 2 2006.203.07:43:51.04#ibcon#first serial, iclass 35, count 2 2006.203.07:43:51.04#ibcon#enter sib2, iclass 35, count 2 2006.203.07:43:51.04#ibcon#flushed, iclass 35, count 2 2006.203.07:43:51.04#ibcon#about to write, iclass 35, count 2 2006.203.07:43:51.04#ibcon#wrote, iclass 35, count 2 2006.203.07:43:51.04#ibcon#about to read 3, iclass 35, count 2 2006.203.07:43:51.06#ibcon#read 3, iclass 35, count 2 2006.203.07:43:51.06#ibcon#about to read 4, iclass 35, count 2 2006.203.07:43:51.06#ibcon#read 4, iclass 35, count 2 2006.203.07:43:51.06#ibcon#about to read 5, iclass 35, count 2 2006.203.07:43:51.06#ibcon#read 5, iclass 35, count 2 2006.203.07:43:51.06#ibcon#about to read 6, iclass 35, count 2 2006.203.07:43:51.06#ibcon#read 6, iclass 35, count 2 2006.203.07:43:51.06#ibcon#end of sib2, iclass 35, count 2 2006.203.07:43:51.06#ibcon#*mode == 0, iclass 35, count 2 2006.203.07:43:51.06#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.203.07:43:51.06#ibcon#[25=AT07-07\r\n] 2006.203.07:43:51.06#ibcon#*before write, iclass 35, count 2 2006.203.07:43:51.06#ibcon#enter sib2, iclass 35, count 2 2006.203.07:43:51.06#ibcon#flushed, iclass 35, count 2 2006.203.07:43:51.06#ibcon#about to write, iclass 35, count 2 2006.203.07:43:51.06#ibcon#wrote, iclass 35, count 2 2006.203.07:43:51.06#ibcon#about to read 3, iclass 35, count 2 2006.203.07:43:51.09#ibcon#read 3, iclass 35, count 2 2006.203.07:43:51.09#ibcon#about to read 4, iclass 35, count 2 2006.203.07:43:51.09#ibcon#read 4, iclass 35, count 2 2006.203.07:43:51.09#ibcon#about to read 5, iclass 35, count 2 2006.203.07:43:51.09#ibcon#read 5, iclass 35, count 2 2006.203.07:43:51.09#ibcon#about to read 6, iclass 35, count 2 2006.203.07:43:51.09#ibcon#read 6, iclass 35, count 2 2006.203.07:43:51.09#ibcon#end of sib2, iclass 35, count 2 2006.203.07:43:51.09#ibcon#*after write, iclass 35, count 2 2006.203.07:43:51.09#ibcon#*before return 0, iclass 35, count 2 2006.203.07:43:51.09#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.203.07:43:51.09#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.203.07:43:51.09#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.203.07:43:51.09#ibcon#ireg 7 cls_cnt 0 2006.203.07:43:51.09#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.203.07:43:51.21#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.203.07:43:51.21#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.203.07:43:51.21#ibcon#enter wrdev, iclass 35, count 0 2006.203.07:43:51.21#ibcon#first serial, iclass 35, count 0 2006.203.07:43:51.21#ibcon#enter sib2, iclass 35, count 0 2006.203.07:43:51.21#ibcon#flushed, iclass 35, count 0 2006.203.07:43:51.21#ibcon#about to write, iclass 35, count 0 2006.203.07:43:51.21#ibcon#wrote, iclass 35, count 0 2006.203.07:43:51.21#ibcon#about to read 3, iclass 35, count 0 2006.203.07:43:51.23#ibcon#read 3, iclass 35, count 0 2006.203.07:43:51.23#ibcon#about to read 4, iclass 35, count 0 2006.203.07:43:51.23#ibcon#read 4, iclass 35, count 0 2006.203.07:43:51.23#ibcon#about to read 5, iclass 35, count 0 2006.203.07:43:51.23#ibcon#read 5, iclass 35, count 0 2006.203.07:43:51.23#ibcon#about to read 6, iclass 35, count 0 2006.203.07:43:51.23#ibcon#read 6, iclass 35, count 0 2006.203.07:43:51.23#ibcon#end of sib2, iclass 35, count 0 2006.203.07:43:51.23#ibcon#*mode == 0, iclass 35, count 0 2006.203.07:43:51.23#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.203.07:43:51.23#ibcon#[25=USB\r\n] 2006.203.07:43:51.23#ibcon#*before write, iclass 35, count 0 2006.203.07:43:51.23#ibcon#enter sib2, iclass 35, count 0 2006.203.07:43:51.23#ibcon#flushed, iclass 35, count 0 2006.203.07:43:51.23#ibcon#about to write, iclass 35, count 0 2006.203.07:43:51.23#ibcon#wrote, iclass 35, count 0 2006.203.07:43:51.23#ibcon#about to read 3, iclass 35, count 0 2006.203.07:43:51.26#ibcon#read 3, iclass 35, count 0 2006.203.07:43:51.26#ibcon#about to read 4, iclass 35, count 0 2006.203.07:43:51.26#ibcon#read 4, iclass 35, count 0 2006.203.07:43:51.26#ibcon#about to read 5, iclass 35, count 0 2006.203.07:43:51.26#ibcon#read 5, iclass 35, count 0 2006.203.07:43:51.26#ibcon#about to read 6, iclass 35, count 0 2006.203.07:43:51.26#ibcon#read 6, iclass 35, count 0 2006.203.07:43:51.26#ibcon#end of sib2, iclass 35, count 0 2006.203.07:43:51.26#ibcon#*after write, iclass 35, count 0 2006.203.07:43:51.26#ibcon#*before return 0, iclass 35, count 0 2006.203.07:43:51.26#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.203.07:43:51.26#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.203.07:43:51.26#ibcon#about to clear, iclass 35 cls_cnt 0 2006.203.07:43:51.26#ibcon#cleared, iclass 35 cls_cnt 0 2006.203.07:43:51.26$vc4f8/valo=8,852.99 2006.203.07:43:51.26#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.203.07:43:51.26#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.203.07:43:51.26#ibcon#ireg 17 cls_cnt 0 2006.203.07:43:51.26#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.203.07:43:51.26#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.203.07:43:51.26#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.203.07:43:51.26#ibcon#enter wrdev, iclass 37, count 0 2006.203.07:43:51.26#ibcon#first serial, iclass 37, count 0 2006.203.07:43:51.26#ibcon#enter sib2, iclass 37, count 0 2006.203.07:43:51.26#ibcon#flushed, iclass 37, count 0 2006.203.07:43:51.26#ibcon#about to write, iclass 37, count 0 2006.203.07:43:51.26#ibcon#wrote, iclass 37, count 0 2006.203.07:43:51.26#ibcon#about to read 3, iclass 37, count 0 2006.203.07:43:51.28#ibcon#read 3, iclass 37, count 0 2006.203.07:43:51.28#ibcon#about to read 4, iclass 37, count 0 2006.203.07:43:51.28#ibcon#read 4, iclass 37, count 0 2006.203.07:43:51.28#ibcon#about to read 5, iclass 37, count 0 2006.203.07:43:51.28#ibcon#read 5, iclass 37, count 0 2006.203.07:43:51.28#ibcon#about to read 6, iclass 37, count 0 2006.203.07:43:51.28#ibcon#read 6, iclass 37, count 0 2006.203.07:43:51.28#ibcon#end of sib2, iclass 37, count 0 2006.203.07:43:51.28#ibcon#*mode == 0, iclass 37, count 0 2006.203.07:43:51.28#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.203.07:43:51.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.203.07:43:51.28#ibcon#*before write, iclass 37, count 0 2006.203.07:43:51.28#ibcon#enter sib2, iclass 37, count 0 2006.203.07:43:51.28#ibcon#flushed, iclass 37, count 0 2006.203.07:43:51.28#ibcon#about to write, iclass 37, count 0 2006.203.07:43:51.28#ibcon#wrote, iclass 37, count 0 2006.203.07:43:51.28#ibcon#about to read 3, iclass 37, count 0 2006.203.07:43:51.32#ibcon#read 3, iclass 37, count 0 2006.203.07:43:51.32#ibcon#about to read 4, iclass 37, count 0 2006.203.07:43:51.32#ibcon#read 4, iclass 37, count 0 2006.203.07:43:51.32#ibcon#about to read 5, iclass 37, count 0 2006.203.07:43:51.32#ibcon#read 5, iclass 37, count 0 2006.203.07:43:51.32#ibcon#about to read 6, iclass 37, count 0 2006.203.07:43:51.32#ibcon#read 6, iclass 37, count 0 2006.203.07:43:51.32#ibcon#end of sib2, iclass 37, count 0 2006.203.07:43:51.32#ibcon#*after write, iclass 37, count 0 2006.203.07:43:51.32#ibcon#*before return 0, iclass 37, count 0 2006.203.07:43:51.32#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.203.07:43:51.32#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.203.07:43:51.32#ibcon#about to clear, iclass 37 cls_cnt 0 2006.203.07:43:51.32#ibcon#cleared, iclass 37 cls_cnt 0 2006.203.07:43:51.32$vc4f8/va=8,6 2006.203.07:43:51.32#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.203.07:43:51.32#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.203.07:43:51.32#ibcon#ireg 11 cls_cnt 2 2006.203.07:43:51.32#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.203.07:43:51.38#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.203.07:43:51.38#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.203.07:43:51.38#ibcon#enter wrdev, iclass 39, count 2 2006.203.07:43:51.38#ibcon#first serial, iclass 39, count 2 2006.203.07:43:51.38#ibcon#enter sib2, iclass 39, count 2 2006.203.07:43:51.38#ibcon#flushed, iclass 39, count 2 2006.203.07:43:51.38#ibcon#about to write, iclass 39, count 2 2006.203.07:43:51.38#ibcon#wrote, iclass 39, count 2 2006.203.07:43:51.38#ibcon#about to read 3, iclass 39, count 2 2006.203.07:43:51.40#ibcon#read 3, iclass 39, count 2 2006.203.07:43:51.40#ibcon#about to read 4, iclass 39, count 2 2006.203.07:43:51.40#ibcon#read 4, iclass 39, count 2 2006.203.07:43:51.40#ibcon#about to read 5, iclass 39, count 2 2006.203.07:43:51.40#ibcon#read 5, iclass 39, count 2 2006.203.07:43:51.40#ibcon#about to read 6, iclass 39, count 2 2006.203.07:43:51.40#ibcon#read 6, iclass 39, count 2 2006.203.07:43:51.40#ibcon#end of sib2, iclass 39, count 2 2006.203.07:43:51.40#ibcon#*mode == 0, iclass 39, count 2 2006.203.07:43:51.40#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.203.07:43:51.40#ibcon#[25=AT08-06\r\n] 2006.203.07:43:51.40#ibcon#*before write, iclass 39, count 2 2006.203.07:43:51.40#ibcon#enter sib2, iclass 39, count 2 2006.203.07:43:51.40#ibcon#flushed, iclass 39, count 2 2006.203.07:43:51.40#ibcon#about to write, iclass 39, count 2 2006.203.07:43:51.40#ibcon#wrote, iclass 39, count 2 2006.203.07:43:51.40#ibcon#about to read 3, iclass 39, count 2 2006.203.07:43:51.43#ibcon#read 3, iclass 39, count 2 2006.203.07:43:51.43#ibcon#about to read 4, iclass 39, count 2 2006.203.07:43:51.43#ibcon#read 4, iclass 39, count 2 2006.203.07:43:51.43#ibcon#about to read 5, iclass 39, count 2 2006.203.07:43:51.43#ibcon#read 5, iclass 39, count 2 2006.203.07:43:51.43#ibcon#about to read 6, iclass 39, count 2 2006.203.07:43:51.43#ibcon#read 6, iclass 39, count 2 2006.203.07:43:51.43#ibcon#end of sib2, iclass 39, count 2 2006.203.07:43:51.43#ibcon#*after write, iclass 39, count 2 2006.203.07:43:51.43#ibcon#*before return 0, iclass 39, count 2 2006.203.07:43:51.43#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.203.07:43:51.43#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.203.07:43:51.43#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.203.07:43:51.43#ibcon#ireg 7 cls_cnt 0 2006.203.07:43:51.43#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.203.07:43:51.55#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.203.07:43:51.55#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.203.07:43:51.55#ibcon#enter wrdev, iclass 39, count 0 2006.203.07:43:51.55#ibcon#first serial, iclass 39, count 0 2006.203.07:43:51.55#ibcon#enter sib2, iclass 39, count 0 2006.203.07:43:51.55#ibcon#flushed, iclass 39, count 0 2006.203.07:43:51.55#ibcon#about to write, iclass 39, count 0 2006.203.07:43:51.55#ibcon#wrote, iclass 39, count 0 2006.203.07:43:51.55#ibcon#about to read 3, iclass 39, count 0 2006.203.07:43:51.57#ibcon#read 3, iclass 39, count 0 2006.203.07:43:51.57#ibcon#about to read 4, iclass 39, count 0 2006.203.07:43:51.57#ibcon#read 4, iclass 39, count 0 2006.203.07:43:51.57#ibcon#about to read 5, iclass 39, count 0 2006.203.07:43:51.57#ibcon#read 5, iclass 39, count 0 2006.203.07:43:51.57#ibcon#about to read 6, iclass 39, count 0 2006.203.07:43:51.57#ibcon#read 6, iclass 39, count 0 2006.203.07:43:51.57#ibcon#end of sib2, iclass 39, count 0 2006.203.07:43:51.57#ibcon#*mode == 0, iclass 39, count 0 2006.203.07:43:51.57#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.203.07:43:51.57#ibcon#[25=USB\r\n] 2006.203.07:43:51.57#ibcon#*before write, iclass 39, count 0 2006.203.07:43:51.57#ibcon#enter sib2, iclass 39, count 0 2006.203.07:43:51.57#ibcon#flushed, iclass 39, count 0 2006.203.07:43:51.57#ibcon#about to write, iclass 39, count 0 2006.203.07:43:51.57#ibcon#wrote, iclass 39, count 0 2006.203.07:43:51.57#ibcon#about to read 3, iclass 39, count 0 2006.203.07:43:51.60#ibcon#read 3, iclass 39, count 0 2006.203.07:43:51.60#ibcon#about to read 4, iclass 39, count 0 2006.203.07:43:51.60#ibcon#read 4, iclass 39, count 0 2006.203.07:43:51.60#ibcon#about to read 5, iclass 39, count 0 2006.203.07:43:51.60#ibcon#read 5, iclass 39, count 0 2006.203.07:43:51.60#ibcon#about to read 6, iclass 39, count 0 2006.203.07:43:51.60#ibcon#read 6, iclass 39, count 0 2006.203.07:43:51.60#ibcon#end of sib2, iclass 39, count 0 2006.203.07:43:51.60#ibcon#*after write, iclass 39, count 0 2006.203.07:43:51.60#ibcon#*before return 0, iclass 39, count 0 2006.203.07:43:51.60#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.203.07:43:51.60#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.203.07:43:51.60#ibcon#about to clear, iclass 39 cls_cnt 0 2006.203.07:43:51.60#ibcon#cleared, iclass 39 cls_cnt 0 2006.203.07:43:51.60$vc4f8/vblo=1,632.99 2006.203.07:43:51.60#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.203.07:43:51.60#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.203.07:43:51.60#ibcon#ireg 17 cls_cnt 0 2006.203.07:43:51.60#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.203.07:43:51.60#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.203.07:43:51.60#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.203.07:43:51.60#ibcon#enter wrdev, iclass 3, count 0 2006.203.07:43:51.60#ibcon#first serial, iclass 3, count 0 2006.203.07:43:51.60#ibcon#enter sib2, iclass 3, count 0 2006.203.07:43:51.60#ibcon#flushed, iclass 3, count 0 2006.203.07:43:51.60#ibcon#about to write, iclass 3, count 0 2006.203.07:43:51.60#ibcon#wrote, iclass 3, count 0 2006.203.07:43:51.60#ibcon#about to read 3, iclass 3, count 0 2006.203.07:43:51.62#ibcon#read 3, iclass 3, count 0 2006.203.07:43:51.62#ibcon#about to read 4, iclass 3, count 0 2006.203.07:43:51.62#ibcon#read 4, iclass 3, count 0 2006.203.07:43:51.62#ibcon#about to read 5, iclass 3, count 0 2006.203.07:43:51.62#ibcon#read 5, iclass 3, count 0 2006.203.07:43:51.62#ibcon#about to read 6, iclass 3, count 0 2006.203.07:43:51.62#ibcon#read 6, iclass 3, count 0 2006.203.07:43:51.62#ibcon#end of sib2, iclass 3, count 0 2006.203.07:43:51.62#ibcon#*mode == 0, iclass 3, count 0 2006.203.07:43:51.62#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.203.07:43:51.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.203.07:43:51.62#ibcon#*before write, iclass 3, count 0 2006.203.07:43:51.62#ibcon#enter sib2, iclass 3, count 0 2006.203.07:43:51.62#ibcon#flushed, iclass 3, count 0 2006.203.07:43:51.62#ibcon#about to write, iclass 3, count 0 2006.203.07:43:51.62#ibcon#wrote, iclass 3, count 0 2006.203.07:43:51.62#ibcon#about to read 3, iclass 3, count 0 2006.203.07:43:51.66#ibcon#read 3, iclass 3, count 0 2006.203.07:43:51.66#ibcon#about to read 4, iclass 3, count 0 2006.203.07:43:51.66#ibcon#read 4, iclass 3, count 0 2006.203.07:43:51.66#ibcon#about to read 5, iclass 3, count 0 2006.203.07:43:51.66#ibcon#read 5, iclass 3, count 0 2006.203.07:43:51.66#ibcon#about to read 6, iclass 3, count 0 2006.203.07:43:51.66#ibcon#read 6, iclass 3, count 0 2006.203.07:43:51.66#ibcon#end of sib2, iclass 3, count 0 2006.203.07:43:51.66#ibcon#*after write, iclass 3, count 0 2006.203.07:43:51.66#ibcon#*before return 0, iclass 3, count 0 2006.203.07:43:51.66#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.203.07:43:51.66#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.203.07:43:51.66#ibcon#about to clear, iclass 3 cls_cnt 0 2006.203.07:43:51.66#ibcon#cleared, iclass 3 cls_cnt 0 2006.203.07:43:51.66$vc4f8/vb=1,4 2006.203.07:43:51.66#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.203.07:43:51.66#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.203.07:43:51.66#ibcon#ireg 11 cls_cnt 2 2006.203.07:43:51.66#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.203.07:43:51.66#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.203.07:43:51.66#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.203.07:43:51.66#ibcon#enter wrdev, iclass 5, count 2 2006.203.07:43:51.66#ibcon#first serial, iclass 5, count 2 2006.203.07:43:51.66#ibcon#enter sib2, iclass 5, count 2 2006.203.07:43:51.66#ibcon#flushed, iclass 5, count 2 2006.203.07:43:51.66#ibcon#about to write, iclass 5, count 2 2006.203.07:43:51.66#ibcon#wrote, iclass 5, count 2 2006.203.07:43:51.66#ibcon#about to read 3, iclass 5, count 2 2006.203.07:43:51.68#ibcon#read 3, iclass 5, count 2 2006.203.07:43:51.68#ibcon#about to read 4, iclass 5, count 2 2006.203.07:43:51.68#ibcon#read 4, iclass 5, count 2 2006.203.07:43:51.68#ibcon#about to read 5, iclass 5, count 2 2006.203.07:43:51.68#ibcon#read 5, iclass 5, count 2 2006.203.07:43:51.68#ibcon#about to read 6, iclass 5, count 2 2006.203.07:43:51.68#ibcon#read 6, iclass 5, count 2 2006.203.07:43:51.68#ibcon#end of sib2, iclass 5, count 2 2006.203.07:43:51.68#ibcon#*mode == 0, iclass 5, count 2 2006.203.07:43:51.68#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.203.07:43:51.68#ibcon#[27=AT01-04\r\n] 2006.203.07:43:51.68#ibcon#*before write, iclass 5, count 2 2006.203.07:43:51.68#ibcon#enter sib2, iclass 5, count 2 2006.203.07:43:51.68#ibcon#flushed, iclass 5, count 2 2006.203.07:43:51.68#ibcon#about to write, iclass 5, count 2 2006.203.07:43:51.68#ibcon#wrote, iclass 5, count 2 2006.203.07:43:51.68#ibcon#about to read 3, iclass 5, count 2 2006.203.07:43:51.71#ibcon#read 3, iclass 5, count 2 2006.203.07:43:51.71#ibcon#about to read 4, iclass 5, count 2 2006.203.07:43:51.71#ibcon#read 4, iclass 5, count 2 2006.203.07:43:51.71#ibcon#about to read 5, iclass 5, count 2 2006.203.07:43:51.71#ibcon#read 5, iclass 5, count 2 2006.203.07:43:51.71#ibcon#about to read 6, iclass 5, count 2 2006.203.07:43:51.71#ibcon#read 6, iclass 5, count 2 2006.203.07:43:51.71#ibcon#end of sib2, iclass 5, count 2 2006.203.07:43:51.71#ibcon#*after write, iclass 5, count 2 2006.203.07:43:51.71#ibcon#*before return 0, iclass 5, count 2 2006.203.07:43:51.71#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.203.07:43:51.71#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.203.07:43:51.71#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.203.07:43:51.71#ibcon#ireg 7 cls_cnt 0 2006.203.07:43:51.71#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.203.07:43:51.83#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.203.07:43:51.83#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.203.07:43:51.83#ibcon#enter wrdev, iclass 5, count 0 2006.203.07:43:51.83#ibcon#first serial, iclass 5, count 0 2006.203.07:43:51.83#ibcon#enter sib2, iclass 5, count 0 2006.203.07:43:51.83#ibcon#flushed, iclass 5, count 0 2006.203.07:43:51.83#ibcon#about to write, iclass 5, count 0 2006.203.07:43:51.83#ibcon#wrote, iclass 5, count 0 2006.203.07:43:51.83#ibcon#about to read 3, iclass 5, count 0 2006.203.07:43:51.85#ibcon#read 3, iclass 5, count 0 2006.203.07:43:51.85#ibcon#about to read 4, iclass 5, count 0 2006.203.07:43:51.85#ibcon#read 4, iclass 5, count 0 2006.203.07:43:51.85#ibcon#about to read 5, iclass 5, count 0 2006.203.07:43:51.85#ibcon#read 5, iclass 5, count 0 2006.203.07:43:51.85#ibcon#about to read 6, iclass 5, count 0 2006.203.07:43:51.85#ibcon#read 6, iclass 5, count 0 2006.203.07:43:51.85#ibcon#end of sib2, iclass 5, count 0 2006.203.07:43:51.85#ibcon#*mode == 0, iclass 5, count 0 2006.203.07:43:51.85#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.203.07:43:51.85#ibcon#[27=USB\r\n] 2006.203.07:43:51.85#ibcon#*before write, iclass 5, count 0 2006.203.07:43:51.85#ibcon#enter sib2, iclass 5, count 0 2006.203.07:43:51.85#ibcon#flushed, iclass 5, count 0 2006.203.07:43:51.85#ibcon#about to write, iclass 5, count 0 2006.203.07:43:51.85#ibcon#wrote, iclass 5, count 0 2006.203.07:43:51.85#ibcon#about to read 3, iclass 5, count 0 2006.203.07:43:51.88#ibcon#read 3, iclass 5, count 0 2006.203.07:43:51.88#ibcon#about to read 4, iclass 5, count 0 2006.203.07:43:51.88#ibcon#read 4, iclass 5, count 0 2006.203.07:43:51.88#ibcon#about to read 5, iclass 5, count 0 2006.203.07:43:51.88#ibcon#read 5, iclass 5, count 0 2006.203.07:43:51.88#ibcon#about to read 6, iclass 5, count 0 2006.203.07:43:51.88#ibcon#read 6, iclass 5, count 0 2006.203.07:43:51.88#ibcon#end of sib2, iclass 5, count 0 2006.203.07:43:51.88#ibcon#*after write, iclass 5, count 0 2006.203.07:43:51.88#ibcon#*before return 0, iclass 5, count 0 2006.203.07:43:51.88#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.203.07:43:51.88#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.203.07:43:51.88#ibcon#about to clear, iclass 5 cls_cnt 0 2006.203.07:43:51.88#ibcon#cleared, iclass 5 cls_cnt 0 2006.203.07:43:51.88$vc4f8/vblo=2,640.99 2006.203.07:43:51.88#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.203.07:43:51.88#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.203.07:43:51.88#ibcon#ireg 17 cls_cnt 0 2006.203.07:43:51.88#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.203.07:43:51.88#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.203.07:43:51.88#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.203.07:43:51.88#ibcon#enter wrdev, iclass 7, count 0 2006.203.07:43:51.88#ibcon#first serial, iclass 7, count 0 2006.203.07:43:51.88#ibcon#enter sib2, iclass 7, count 0 2006.203.07:43:51.88#ibcon#flushed, iclass 7, count 0 2006.203.07:43:51.88#ibcon#about to write, iclass 7, count 0 2006.203.07:43:51.88#ibcon#wrote, iclass 7, count 0 2006.203.07:43:51.88#ibcon#about to read 3, iclass 7, count 0 2006.203.07:43:51.90#ibcon#read 3, iclass 7, count 0 2006.203.07:43:51.90#ibcon#about to read 4, iclass 7, count 0 2006.203.07:43:51.90#ibcon#read 4, iclass 7, count 0 2006.203.07:43:51.90#ibcon#about to read 5, iclass 7, count 0 2006.203.07:43:51.90#ibcon#read 5, iclass 7, count 0 2006.203.07:43:51.90#ibcon#about to read 6, iclass 7, count 0 2006.203.07:43:51.90#ibcon#read 6, iclass 7, count 0 2006.203.07:43:51.90#ibcon#end of sib2, iclass 7, count 0 2006.203.07:43:51.90#ibcon#*mode == 0, iclass 7, count 0 2006.203.07:43:51.90#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.203.07:43:51.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.203.07:43:51.90#ibcon#*before write, iclass 7, count 0 2006.203.07:43:51.90#ibcon#enter sib2, iclass 7, count 0 2006.203.07:43:51.90#ibcon#flushed, iclass 7, count 0 2006.203.07:43:51.90#ibcon#about to write, iclass 7, count 0 2006.203.07:43:51.90#ibcon#wrote, iclass 7, count 0 2006.203.07:43:51.90#ibcon#about to read 3, iclass 7, count 0 2006.203.07:43:51.94#ibcon#read 3, iclass 7, count 0 2006.203.07:43:51.94#ibcon#about to read 4, iclass 7, count 0 2006.203.07:43:51.94#ibcon#read 4, iclass 7, count 0 2006.203.07:43:51.94#ibcon#about to read 5, iclass 7, count 0 2006.203.07:43:51.94#ibcon#read 5, iclass 7, count 0 2006.203.07:43:51.94#ibcon#about to read 6, iclass 7, count 0 2006.203.07:43:51.94#ibcon#read 6, iclass 7, count 0 2006.203.07:43:51.94#ibcon#end of sib2, iclass 7, count 0 2006.203.07:43:51.94#ibcon#*after write, iclass 7, count 0 2006.203.07:43:51.94#ibcon#*before return 0, iclass 7, count 0 2006.203.07:43:51.94#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.203.07:43:51.94#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.203.07:43:51.94#ibcon#about to clear, iclass 7 cls_cnt 0 2006.203.07:43:51.94#ibcon#cleared, iclass 7 cls_cnt 0 2006.203.07:43:51.94$vc4f8/vb=2,4 2006.203.07:43:51.94#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.203.07:43:51.94#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.203.07:43:51.94#ibcon#ireg 11 cls_cnt 2 2006.203.07:43:51.94#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.203.07:43:52.00#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.203.07:43:52.00#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.203.07:43:52.00#ibcon#enter wrdev, iclass 11, count 2 2006.203.07:43:52.00#ibcon#first serial, iclass 11, count 2 2006.203.07:43:52.00#ibcon#enter sib2, iclass 11, count 2 2006.203.07:43:52.00#ibcon#flushed, iclass 11, count 2 2006.203.07:43:52.00#ibcon#about to write, iclass 11, count 2 2006.203.07:43:52.00#ibcon#wrote, iclass 11, count 2 2006.203.07:43:52.00#ibcon#about to read 3, iclass 11, count 2 2006.203.07:43:52.02#ibcon#read 3, iclass 11, count 2 2006.203.07:43:52.02#ibcon#about to read 4, iclass 11, count 2 2006.203.07:43:52.02#ibcon#read 4, iclass 11, count 2 2006.203.07:43:52.02#ibcon#about to read 5, iclass 11, count 2 2006.203.07:43:52.02#ibcon#read 5, iclass 11, count 2 2006.203.07:43:52.02#ibcon#about to read 6, iclass 11, count 2 2006.203.07:43:52.02#ibcon#read 6, iclass 11, count 2 2006.203.07:43:52.02#ibcon#end of sib2, iclass 11, count 2 2006.203.07:43:52.02#ibcon#*mode == 0, iclass 11, count 2 2006.203.07:43:52.02#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.203.07:43:52.02#ibcon#[27=AT02-04\r\n] 2006.203.07:43:52.02#ibcon#*before write, iclass 11, count 2 2006.203.07:43:52.02#ibcon#enter sib2, iclass 11, count 2 2006.203.07:43:52.02#ibcon#flushed, iclass 11, count 2 2006.203.07:43:52.02#ibcon#about to write, iclass 11, count 2 2006.203.07:43:52.02#ibcon#wrote, iclass 11, count 2 2006.203.07:43:52.02#ibcon#about to read 3, iclass 11, count 2 2006.203.07:43:52.05#ibcon#read 3, iclass 11, count 2 2006.203.07:43:52.05#ibcon#about to read 4, iclass 11, count 2 2006.203.07:43:52.05#ibcon#read 4, iclass 11, count 2 2006.203.07:43:52.05#ibcon#about to read 5, iclass 11, count 2 2006.203.07:43:52.05#ibcon#read 5, iclass 11, count 2 2006.203.07:43:52.05#ibcon#about to read 6, iclass 11, count 2 2006.203.07:43:52.05#ibcon#read 6, iclass 11, count 2 2006.203.07:43:52.05#ibcon#end of sib2, iclass 11, count 2 2006.203.07:43:52.05#ibcon#*after write, iclass 11, count 2 2006.203.07:43:52.05#ibcon#*before return 0, iclass 11, count 2 2006.203.07:43:52.05#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.203.07:43:52.05#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.203.07:43:52.05#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.203.07:43:52.05#ibcon#ireg 7 cls_cnt 0 2006.203.07:43:52.05#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.203.07:43:52.17#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.203.07:43:52.17#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.203.07:43:52.17#ibcon#enter wrdev, iclass 11, count 0 2006.203.07:43:52.17#ibcon#first serial, iclass 11, count 0 2006.203.07:43:52.17#ibcon#enter sib2, iclass 11, count 0 2006.203.07:43:52.17#ibcon#flushed, iclass 11, count 0 2006.203.07:43:52.17#ibcon#about to write, iclass 11, count 0 2006.203.07:43:52.17#ibcon#wrote, iclass 11, count 0 2006.203.07:43:52.17#ibcon#about to read 3, iclass 11, count 0 2006.203.07:43:52.19#ibcon#read 3, iclass 11, count 0 2006.203.07:43:52.19#ibcon#about to read 4, iclass 11, count 0 2006.203.07:43:52.19#ibcon#read 4, iclass 11, count 0 2006.203.07:43:52.19#ibcon#about to read 5, iclass 11, count 0 2006.203.07:43:52.19#ibcon#read 5, iclass 11, count 0 2006.203.07:43:52.19#ibcon#about to read 6, iclass 11, count 0 2006.203.07:43:52.19#ibcon#read 6, iclass 11, count 0 2006.203.07:43:52.19#ibcon#end of sib2, iclass 11, count 0 2006.203.07:43:52.19#ibcon#*mode == 0, iclass 11, count 0 2006.203.07:43:52.19#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.203.07:43:52.19#ibcon#[27=USB\r\n] 2006.203.07:43:52.19#ibcon#*before write, iclass 11, count 0 2006.203.07:43:52.19#ibcon#enter sib2, iclass 11, count 0 2006.203.07:43:52.19#ibcon#flushed, iclass 11, count 0 2006.203.07:43:52.19#ibcon#about to write, iclass 11, count 0 2006.203.07:43:52.19#ibcon#wrote, iclass 11, count 0 2006.203.07:43:52.19#ibcon#about to read 3, iclass 11, count 0 2006.203.07:43:52.22#ibcon#read 3, iclass 11, count 0 2006.203.07:43:52.22#ibcon#about to read 4, iclass 11, count 0 2006.203.07:43:52.22#ibcon#read 4, iclass 11, count 0 2006.203.07:43:52.22#ibcon#about to read 5, iclass 11, count 0 2006.203.07:43:52.22#ibcon#read 5, iclass 11, count 0 2006.203.07:43:52.22#ibcon#about to read 6, iclass 11, count 0 2006.203.07:43:52.22#ibcon#read 6, iclass 11, count 0 2006.203.07:43:52.22#ibcon#end of sib2, iclass 11, count 0 2006.203.07:43:52.22#ibcon#*after write, iclass 11, count 0 2006.203.07:43:52.22#ibcon#*before return 0, iclass 11, count 0 2006.203.07:43:52.22#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.203.07:43:52.22#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.203.07:43:52.22#ibcon#about to clear, iclass 11 cls_cnt 0 2006.203.07:43:52.22#ibcon#cleared, iclass 11 cls_cnt 0 2006.203.07:43:52.22$vc4f8/vblo=3,656.99 2006.203.07:43:52.22#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.203.07:43:52.22#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.203.07:43:52.22#ibcon#ireg 17 cls_cnt 0 2006.203.07:43:52.22#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.203.07:43:52.22#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.203.07:43:52.22#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.203.07:43:52.22#ibcon#enter wrdev, iclass 13, count 0 2006.203.07:43:52.22#ibcon#first serial, iclass 13, count 0 2006.203.07:43:52.22#ibcon#enter sib2, iclass 13, count 0 2006.203.07:43:52.22#ibcon#flushed, iclass 13, count 0 2006.203.07:43:52.22#ibcon#about to write, iclass 13, count 0 2006.203.07:43:52.22#ibcon#wrote, iclass 13, count 0 2006.203.07:43:52.22#ibcon#about to read 3, iclass 13, count 0 2006.203.07:43:52.24#ibcon#read 3, iclass 13, count 0 2006.203.07:43:52.24#ibcon#about to read 4, iclass 13, count 0 2006.203.07:43:52.24#ibcon#read 4, iclass 13, count 0 2006.203.07:43:52.24#ibcon#about to read 5, iclass 13, count 0 2006.203.07:43:52.24#ibcon#read 5, iclass 13, count 0 2006.203.07:43:52.24#ibcon#about to read 6, iclass 13, count 0 2006.203.07:43:52.24#ibcon#read 6, iclass 13, count 0 2006.203.07:43:52.24#ibcon#end of sib2, iclass 13, count 0 2006.203.07:43:52.24#ibcon#*mode == 0, iclass 13, count 0 2006.203.07:43:52.24#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.203.07:43:52.24#ibcon#[28=FRQ=03,656.99\r\n] 2006.203.07:43:52.24#ibcon#*before write, iclass 13, count 0 2006.203.07:43:52.24#ibcon#enter sib2, iclass 13, count 0 2006.203.07:43:52.24#ibcon#flushed, iclass 13, count 0 2006.203.07:43:52.24#ibcon#about to write, iclass 13, count 0 2006.203.07:43:52.24#ibcon#wrote, iclass 13, count 0 2006.203.07:43:52.24#ibcon#about to read 3, iclass 13, count 0 2006.203.07:43:52.28#ibcon#read 3, iclass 13, count 0 2006.203.07:43:52.28#ibcon#about to read 4, iclass 13, count 0 2006.203.07:43:52.28#ibcon#read 4, iclass 13, count 0 2006.203.07:43:52.28#ibcon#about to read 5, iclass 13, count 0 2006.203.07:43:52.28#ibcon#read 5, iclass 13, count 0 2006.203.07:43:52.28#ibcon#about to read 6, iclass 13, count 0 2006.203.07:43:52.28#ibcon#read 6, iclass 13, count 0 2006.203.07:43:52.28#ibcon#end of sib2, iclass 13, count 0 2006.203.07:43:52.28#ibcon#*after write, iclass 13, count 0 2006.203.07:43:52.28#ibcon#*before return 0, iclass 13, count 0 2006.203.07:43:52.28#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.203.07:43:52.28#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.203.07:43:52.28#ibcon#about to clear, iclass 13 cls_cnt 0 2006.203.07:43:52.28#ibcon#cleared, iclass 13 cls_cnt 0 2006.203.07:43:52.28$vc4f8/vb=3,4 2006.203.07:43:52.28#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.203.07:43:52.28#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.203.07:43:52.28#ibcon#ireg 11 cls_cnt 2 2006.203.07:43:52.28#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.203.07:43:52.34#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.203.07:43:52.34#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.203.07:43:52.34#ibcon#enter wrdev, iclass 15, count 2 2006.203.07:43:52.34#ibcon#first serial, iclass 15, count 2 2006.203.07:43:52.34#ibcon#enter sib2, iclass 15, count 2 2006.203.07:43:52.34#ibcon#flushed, iclass 15, count 2 2006.203.07:43:52.34#ibcon#about to write, iclass 15, count 2 2006.203.07:43:52.34#ibcon#wrote, iclass 15, count 2 2006.203.07:43:52.34#ibcon#about to read 3, iclass 15, count 2 2006.203.07:43:52.36#ibcon#read 3, iclass 15, count 2 2006.203.07:43:52.36#ibcon#about to read 4, iclass 15, count 2 2006.203.07:43:52.36#ibcon#read 4, iclass 15, count 2 2006.203.07:43:52.36#ibcon#about to read 5, iclass 15, count 2 2006.203.07:43:52.36#ibcon#read 5, iclass 15, count 2 2006.203.07:43:52.36#ibcon#about to read 6, iclass 15, count 2 2006.203.07:43:52.36#ibcon#read 6, iclass 15, count 2 2006.203.07:43:52.36#ibcon#end of sib2, iclass 15, count 2 2006.203.07:43:52.36#ibcon#*mode == 0, iclass 15, count 2 2006.203.07:43:52.36#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.203.07:43:52.36#ibcon#[27=AT03-04\r\n] 2006.203.07:43:52.36#ibcon#*before write, iclass 15, count 2 2006.203.07:43:52.36#ibcon#enter sib2, iclass 15, count 2 2006.203.07:43:52.36#ibcon#flushed, iclass 15, count 2 2006.203.07:43:52.36#ibcon#about to write, iclass 15, count 2 2006.203.07:43:52.36#ibcon#wrote, iclass 15, count 2 2006.203.07:43:52.36#ibcon#about to read 3, iclass 15, count 2 2006.203.07:43:52.39#ibcon#read 3, iclass 15, count 2 2006.203.07:43:52.39#ibcon#about to read 4, iclass 15, count 2 2006.203.07:43:52.39#ibcon#read 4, iclass 15, count 2 2006.203.07:43:52.39#ibcon#about to read 5, iclass 15, count 2 2006.203.07:43:52.39#ibcon#read 5, iclass 15, count 2 2006.203.07:43:52.39#ibcon#about to read 6, iclass 15, count 2 2006.203.07:43:52.39#ibcon#read 6, iclass 15, count 2 2006.203.07:43:52.39#ibcon#end of sib2, iclass 15, count 2 2006.203.07:43:52.39#ibcon#*after write, iclass 15, count 2 2006.203.07:43:52.39#ibcon#*before return 0, iclass 15, count 2 2006.203.07:43:52.39#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.203.07:43:52.39#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.203.07:43:52.39#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.203.07:43:52.39#ibcon#ireg 7 cls_cnt 0 2006.203.07:43:52.39#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.203.07:43:52.51#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.203.07:43:52.51#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.203.07:43:52.51#ibcon#enter wrdev, iclass 15, count 0 2006.203.07:43:52.51#ibcon#first serial, iclass 15, count 0 2006.203.07:43:52.51#ibcon#enter sib2, iclass 15, count 0 2006.203.07:43:52.51#ibcon#flushed, iclass 15, count 0 2006.203.07:43:52.51#ibcon#about to write, iclass 15, count 0 2006.203.07:43:52.51#ibcon#wrote, iclass 15, count 0 2006.203.07:43:52.51#ibcon#about to read 3, iclass 15, count 0 2006.203.07:43:52.53#ibcon#read 3, iclass 15, count 0 2006.203.07:43:52.53#ibcon#about to read 4, iclass 15, count 0 2006.203.07:43:52.53#ibcon#read 4, iclass 15, count 0 2006.203.07:43:52.53#ibcon#about to read 5, iclass 15, count 0 2006.203.07:43:52.53#ibcon#read 5, iclass 15, count 0 2006.203.07:43:52.53#ibcon#about to read 6, iclass 15, count 0 2006.203.07:43:52.53#ibcon#read 6, iclass 15, count 0 2006.203.07:43:52.53#ibcon#end of sib2, iclass 15, count 0 2006.203.07:43:52.53#ibcon#*mode == 0, iclass 15, count 0 2006.203.07:43:52.53#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.203.07:43:52.53#ibcon#[27=USB\r\n] 2006.203.07:43:52.53#ibcon#*before write, iclass 15, count 0 2006.203.07:43:52.53#ibcon#enter sib2, iclass 15, count 0 2006.203.07:43:52.53#ibcon#flushed, iclass 15, count 0 2006.203.07:43:52.53#ibcon#about to write, iclass 15, count 0 2006.203.07:43:52.53#ibcon#wrote, iclass 15, count 0 2006.203.07:43:52.53#ibcon#about to read 3, iclass 15, count 0 2006.203.07:43:52.56#ibcon#read 3, iclass 15, count 0 2006.203.07:43:52.56#ibcon#about to read 4, iclass 15, count 0 2006.203.07:43:52.56#ibcon#read 4, iclass 15, count 0 2006.203.07:43:52.56#ibcon#about to read 5, iclass 15, count 0 2006.203.07:43:52.56#ibcon#read 5, iclass 15, count 0 2006.203.07:43:52.56#ibcon#about to read 6, iclass 15, count 0 2006.203.07:43:52.56#ibcon#read 6, iclass 15, count 0 2006.203.07:43:52.56#ibcon#end of sib2, iclass 15, count 0 2006.203.07:43:52.56#ibcon#*after write, iclass 15, count 0 2006.203.07:43:52.56#ibcon#*before return 0, iclass 15, count 0 2006.203.07:43:52.56#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.203.07:43:52.56#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.203.07:43:52.56#ibcon#about to clear, iclass 15 cls_cnt 0 2006.203.07:43:52.56#ibcon#cleared, iclass 15 cls_cnt 0 2006.203.07:43:52.56$vc4f8/vblo=4,712.99 2006.203.07:43:52.56#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.203.07:43:52.56#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.203.07:43:52.56#ibcon#ireg 17 cls_cnt 0 2006.203.07:43:52.56#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.203.07:43:52.56#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.203.07:43:52.56#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.203.07:43:52.56#ibcon#enter wrdev, iclass 17, count 0 2006.203.07:43:52.56#ibcon#first serial, iclass 17, count 0 2006.203.07:43:52.56#ibcon#enter sib2, iclass 17, count 0 2006.203.07:43:52.56#ibcon#flushed, iclass 17, count 0 2006.203.07:43:52.56#ibcon#about to write, iclass 17, count 0 2006.203.07:43:52.56#ibcon#wrote, iclass 17, count 0 2006.203.07:43:52.56#ibcon#about to read 3, iclass 17, count 0 2006.203.07:43:52.58#ibcon#read 3, iclass 17, count 0 2006.203.07:43:52.58#ibcon#about to read 4, iclass 17, count 0 2006.203.07:43:52.58#ibcon#read 4, iclass 17, count 0 2006.203.07:43:52.58#ibcon#about to read 5, iclass 17, count 0 2006.203.07:43:52.58#ibcon#read 5, iclass 17, count 0 2006.203.07:43:52.58#ibcon#about to read 6, iclass 17, count 0 2006.203.07:43:52.58#ibcon#read 6, iclass 17, count 0 2006.203.07:43:52.58#ibcon#end of sib2, iclass 17, count 0 2006.203.07:43:52.58#ibcon#*mode == 0, iclass 17, count 0 2006.203.07:43:52.58#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.203.07:43:52.58#ibcon#[28=FRQ=04,712.99\r\n] 2006.203.07:43:52.58#ibcon#*before write, iclass 17, count 0 2006.203.07:43:52.58#ibcon#enter sib2, iclass 17, count 0 2006.203.07:43:52.58#ibcon#flushed, iclass 17, count 0 2006.203.07:43:52.58#ibcon#about to write, iclass 17, count 0 2006.203.07:43:52.58#ibcon#wrote, iclass 17, count 0 2006.203.07:43:52.58#ibcon#about to read 3, iclass 17, count 0 2006.203.07:43:52.62#ibcon#read 3, iclass 17, count 0 2006.203.07:43:52.62#ibcon#about to read 4, iclass 17, count 0 2006.203.07:43:52.62#ibcon#read 4, iclass 17, count 0 2006.203.07:43:52.62#ibcon#about to read 5, iclass 17, count 0 2006.203.07:43:52.62#ibcon#read 5, iclass 17, count 0 2006.203.07:43:52.62#ibcon#about to read 6, iclass 17, count 0 2006.203.07:43:52.62#ibcon#read 6, iclass 17, count 0 2006.203.07:43:52.62#ibcon#end of sib2, iclass 17, count 0 2006.203.07:43:52.62#ibcon#*after write, iclass 17, count 0 2006.203.07:43:52.62#ibcon#*before return 0, iclass 17, count 0 2006.203.07:43:52.62#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.203.07:43:52.62#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.203.07:43:52.62#ibcon#about to clear, iclass 17 cls_cnt 0 2006.203.07:43:52.62#ibcon#cleared, iclass 17 cls_cnt 0 2006.203.07:43:52.62$vc4f8/vb=4,4 2006.203.07:43:52.62#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.203.07:43:52.62#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.203.07:43:52.62#ibcon#ireg 11 cls_cnt 2 2006.203.07:43:52.62#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.203.07:43:52.68#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.203.07:43:52.68#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.203.07:43:52.68#ibcon#enter wrdev, iclass 19, count 2 2006.203.07:43:52.68#ibcon#first serial, iclass 19, count 2 2006.203.07:43:52.68#ibcon#enter sib2, iclass 19, count 2 2006.203.07:43:52.68#ibcon#flushed, iclass 19, count 2 2006.203.07:43:52.68#ibcon#about to write, iclass 19, count 2 2006.203.07:43:52.68#ibcon#wrote, iclass 19, count 2 2006.203.07:43:52.68#ibcon#about to read 3, iclass 19, count 2 2006.203.07:43:52.70#ibcon#read 3, iclass 19, count 2 2006.203.07:43:52.70#ibcon#about to read 4, iclass 19, count 2 2006.203.07:43:52.70#ibcon#read 4, iclass 19, count 2 2006.203.07:43:52.70#ibcon#about to read 5, iclass 19, count 2 2006.203.07:43:52.70#ibcon#read 5, iclass 19, count 2 2006.203.07:43:52.70#ibcon#about to read 6, iclass 19, count 2 2006.203.07:43:52.70#ibcon#read 6, iclass 19, count 2 2006.203.07:43:52.70#ibcon#end of sib2, iclass 19, count 2 2006.203.07:43:52.70#ibcon#*mode == 0, iclass 19, count 2 2006.203.07:43:52.70#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.203.07:43:52.70#ibcon#[27=AT04-04\r\n] 2006.203.07:43:52.70#ibcon#*before write, iclass 19, count 2 2006.203.07:43:52.70#ibcon#enter sib2, iclass 19, count 2 2006.203.07:43:52.70#ibcon#flushed, iclass 19, count 2 2006.203.07:43:52.70#ibcon#about to write, iclass 19, count 2 2006.203.07:43:52.70#ibcon#wrote, iclass 19, count 2 2006.203.07:43:52.70#ibcon#about to read 3, iclass 19, count 2 2006.203.07:43:52.73#ibcon#read 3, iclass 19, count 2 2006.203.07:43:52.73#ibcon#about to read 4, iclass 19, count 2 2006.203.07:43:52.73#ibcon#read 4, iclass 19, count 2 2006.203.07:43:52.73#ibcon#about to read 5, iclass 19, count 2 2006.203.07:43:52.73#ibcon#read 5, iclass 19, count 2 2006.203.07:43:52.73#ibcon#about to read 6, iclass 19, count 2 2006.203.07:43:52.73#ibcon#read 6, iclass 19, count 2 2006.203.07:43:52.73#ibcon#end of sib2, iclass 19, count 2 2006.203.07:43:52.73#ibcon#*after write, iclass 19, count 2 2006.203.07:43:52.73#ibcon#*before return 0, iclass 19, count 2 2006.203.07:43:52.73#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.203.07:43:52.73#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.203.07:43:52.73#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.203.07:43:52.73#ibcon#ireg 7 cls_cnt 0 2006.203.07:43:52.73#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.203.07:43:52.85#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.203.07:43:52.85#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.203.07:43:52.85#ibcon#enter wrdev, iclass 19, count 0 2006.203.07:43:52.85#ibcon#first serial, iclass 19, count 0 2006.203.07:43:52.85#ibcon#enter sib2, iclass 19, count 0 2006.203.07:43:52.85#ibcon#flushed, iclass 19, count 0 2006.203.07:43:52.85#ibcon#about to write, iclass 19, count 0 2006.203.07:43:52.85#ibcon#wrote, iclass 19, count 0 2006.203.07:43:52.85#ibcon#about to read 3, iclass 19, count 0 2006.203.07:43:52.87#ibcon#read 3, iclass 19, count 0 2006.203.07:43:52.87#ibcon#about to read 4, iclass 19, count 0 2006.203.07:43:52.87#ibcon#read 4, iclass 19, count 0 2006.203.07:43:52.87#ibcon#about to read 5, iclass 19, count 0 2006.203.07:43:52.87#ibcon#read 5, iclass 19, count 0 2006.203.07:43:52.87#ibcon#about to read 6, iclass 19, count 0 2006.203.07:43:52.87#ibcon#read 6, iclass 19, count 0 2006.203.07:43:52.87#ibcon#end of sib2, iclass 19, count 0 2006.203.07:43:52.87#ibcon#*mode == 0, iclass 19, count 0 2006.203.07:43:52.87#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.203.07:43:52.87#ibcon#[27=USB\r\n] 2006.203.07:43:52.87#ibcon#*before write, iclass 19, count 0 2006.203.07:43:52.87#ibcon#enter sib2, iclass 19, count 0 2006.203.07:43:52.87#ibcon#flushed, iclass 19, count 0 2006.203.07:43:52.87#ibcon#about to write, iclass 19, count 0 2006.203.07:43:52.87#ibcon#wrote, iclass 19, count 0 2006.203.07:43:52.87#ibcon#about to read 3, iclass 19, count 0 2006.203.07:43:52.90#ibcon#read 3, iclass 19, count 0 2006.203.07:43:52.90#ibcon#about to read 4, iclass 19, count 0 2006.203.07:43:52.90#ibcon#read 4, iclass 19, count 0 2006.203.07:43:52.90#ibcon#about to read 5, iclass 19, count 0 2006.203.07:43:52.90#ibcon#read 5, iclass 19, count 0 2006.203.07:43:52.90#ibcon#about to read 6, iclass 19, count 0 2006.203.07:43:52.90#ibcon#read 6, iclass 19, count 0 2006.203.07:43:52.90#ibcon#end of sib2, iclass 19, count 0 2006.203.07:43:52.90#ibcon#*after write, iclass 19, count 0 2006.203.07:43:52.90#ibcon#*before return 0, iclass 19, count 0 2006.203.07:43:52.90#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.203.07:43:52.90#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.203.07:43:52.90#ibcon#about to clear, iclass 19 cls_cnt 0 2006.203.07:43:52.90#ibcon#cleared, iclass 19 cls_cnt 0 2006.203.07:43:52.90$vc4f8/vblo=5,744.99 2006.203.07:43:52.90#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.203.07:43:52.90#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.203.07:43:52.90#ibcon#ireg 17 cls_cnt 0 2006.203.07:43:52.90#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.203.07:43:52.90#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.203.07:43:52.90#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.203.07:43:52.90#ibcon#enter wrdev, iclass 21, count 0 2006.203.07:43:52.90#ibcon#first serial, iclass 21, count 0 2006.203.07:43:52.90#ibcon#enter sib2, iclass 21, count 0 2006.203.07:43:52.90#ibcon#flushed, iclass 21, count 0 2006.203.07:43:52.90#ibcon#about to write, iclass 21, count 0 2006.203.07:43:52.90#ibcon#wrote, iclass 21, count 0 2006.203.07:43:52.90#ibcon#about to read 3, iclass 21, count 0 2006.203.07:43:52.92#ibcon#read 3, iclass 21, count 0 2006.203.07:43:52.92#ibcon#about to read 4, iclass 21, count 0 2006.203.07:43:52.92#ibcon#read 4, iclass 21, count 0 2006.203.07:43:52.92#ibcon#about to read 5, iclass 21, count 0 2006.203.07:43:52.92#ibcon#read 5, iclass 21, count 0 2006.203.07:43:52.92#ibcon#about to read 6, iclass 21, count 0 2006.203.07:43:52.92#ibcon#read 6, iclass 21, count 0 2006.203.07:43:52.92#ibcon#end of sib2, iclass 21, count 0 2006.203.07:43:52.92#ibcon#*mode == 0, iclass 21, count 0 2006.203.07:43:52.92#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.203.07:43:52.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.203.07:43:52.92#ibcon#*before write, iclass 21, count 0 2006.203.07:43:52.92#ibcon#enter sib2, iclass 21, count 0 2006.203.07:43:52.92#ibcon#flushed, iclass 21, count 0 2006.203.07:43:52.92#ibcon#about to write, iclass 21, count 0 2006.203.07:43:52.92#ibcon#wrote, iclass 21, count 0 2006.203.07:43:52.92#ibcon#about to read 3, iclass 21, count 0 2006.203.07:43:52.96#ibcon#read 3, iclass 21, count 0 2006.203.07:43:52.96#ibcon#about to read 4, iclass 21, count 0 2006.203.07:43:52.96#ibcon#read 4, iclass 21, count 0 2006.203.07:43:52.96#ibcon#about to read 5, iclass 21, count 0 2006.203.07:43:52.96#ibcon#read 5, iclass 21, count 0 2006.203.07:43:52.96#ibcon#about to read 6, iclass 21, count 0 2006.203.07:43:52.96#ibcon#read 6, iclass 21, count 0 2006.203.07:43:52.96#ibcon#end of sib2, iclass 21, count 0 2006.203.07:43:52.96#ibcon#*after write, iclass 21, count 0 2006.203.07:43:52.96#ibcon#*before return 0, iclass 21, count 0 2006.203.07:43:52.96#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.203.07:43:52.96#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.203.07:43:52.96#ibcon#about to clear, iclass 21 cls_cnt 0 2006.203.07:43:52.96#ibcon#cleared, iclass 21 cls_cnt 0 2006.203.07:43:52.96$vc4f8/vb=5,3 2006.203.07:43:52.96#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.203.07:43:52.96#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.203.07:43:52.96#ibcon#ireg 11 cls_cnt 2 2006.203.07:43:52.96#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.203.07:43:53.02#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.203.07:43:53.02#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.203.07:43:53.02#ibcon#enter wrdev, iclass 23, count 2 2006.203.07:43:53.02#ibcon#first serial, iclass 23, count 2 2006.203.07:43:53.02#ibcon#enter sib2, iclass 23, count 2 2006.203.07:43:53.02#ibcon#flushed, iclass 23, count 2 2006.203.07:43:53.02#ibcon#about to write, iclass 23, count 2 2006.203.07:43:53.02#ibcon#wrote, iclass 23, count 2 2006.203.07:43:53.02#ibcon#about to read 3, iclass 23, count 2 2006.203.07:43:53.04#ibcon#read 3, iclass 23, count 2 2006.203.07:43:53.04#ibcon#about to read 4, iclass 23, count 2 2006.203.07:43:53.04#ibcon#read 4, iclass 23, count 2 2006.203.07:43:53.04#ibcon#about to read 5, iclass 23, count 2 2006.203.07:43:53.04#ibcon#read 5, iclass 23, count 2 2006.203.07:43:53.04#ibcon#about to read 6, iclass 23, count 2 2006.203.07:43:53.04#ibcon#read 6, iclass 23, count 2 2006.203.07:43:53.04#ibcon#end of sib2, iclass 23, count 2 2006.203.07:43:53.04#ibcon#*mode == 0, iclass 23, count 2 2006.203.07:43:53.04#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.203.07:43:53.04#ibcon#[27=AT05-03\r\n] 2006.203.07:43:53.04#ibcon#*before write, iclass 23, count 2 2006.203.07:43:53.04#ibcon#enter sib2, iclass 23, count 2 2006.203.07:43:53.04#ibcon#flushed, iclass 23, count 2 2006.203.07:43:53.04#ibcon#about to write, iclass 23, count 2 2006.203.07:43:53.04#ibcon#wrote, iclass 23, count 2 2006.203.07:43:53.04#ibcon#about to read 3, iclass 23, count 2 2006.203.07:43:53.07#ibcon#read 3, iclass 23, count 2 2006.203.07:43:53.07#ibcon#about to read 4, iclass 23, count 2 2006.203.07:43:53.07#ibcon#read 4, iclass 23, count 2 2006.203.07:43:53.07#ibcon#about to read 5, iclass 23, count 2 2006.203.07:43:53.07#ibcon#read 5, iclass 23, count 2 2006.203.07:43:53.07#ibcon#about to read 6, iclass 23, count 2 2006.203.07:43:53.07#ibcon#read 6, iclass 23, count 2 2006.203.07:43:53.07#ibcon#end of sib2, iclass 23, count 2 2006.203.07:43:53.07#ibcon#*after write, iclass 23, count 2 2006.203.07:43:53.07#ibcon#*before return 0, iclass 23, count 2 2006.203.07:43:53.07#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.203.07:43:53.07#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.203.07:43:53.07#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.203.07:43:53.07#ibcon#ireg 7 cls_cnt 0 2006.203.07:43:53.07#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.203.07:43:53.19#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.203.07:43:53.19#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.203.07:43:53.19#ibcon#enter wrdev, iclass 23, count 0 2006.203.07:43:53.19#ibcon#first serial, iclass 23, count 0 2006.203.07:43:53.19#ibcon#enter sib2, iclass 23, count 0 2006.203.07:43:53.19#ibcon#flushed, iclass 23, count 0 2006.203.07:43:53.19#ibcon#about to write, iclass 23, count 0 2006.203.07:43:53.19#ibcon#wrote, iclass 23, count 0 2006.203.07:43:53.19#ibcon#about to read 3, iclass 23, count 0 2006.203.07:43:53.21#ibcon#read 3, iclass 23, count 0 2006.203.07:43:53.21#ibcon#about to read 4, iclass 23, count 0 2006.203.07:43:53.21#ibcon#read 4, iclass 23, count 0 2006.203.07:43:53.21#ibcon#about to read 5, iclass 23, count 0 2006.203.07:43:53.21#ibcon#read 5, iclass 23, count 0 2006.203.07:43:53.21#ibcon#about to read 6, iclass 23, count 0 2006.203.07:43:53.21#ibcon#read 6, iclass 23, count 0 2006.203.07:43:53.21#ibcon#end of sib2, iclass 23, count 0 2006.203.07:43:53.21#ibcon#*mode == 0, iclass 23, count 0 2006.203.07:43:53.21#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.203.07:43:53.21#ibcon#[27=USB\r\n] 2006.203.07:43:53.21#ibcon#*before write, iclass 23, count 0 2006.203.07:43:53.21#ibcon#enter sib2, iclass 23, count 0 2006.203.07:43:53.21#ibcon#flushed, iclass 23, count 0 2006.203.07:43:53.21#ibcon#about to write, iclass 23, count 0 2006.203.07:43:53.21#ibcon#wrote, iclass 23, count 0 2006.203.07:43:53.21#ibcon#about to read 3, iclass 23, count 0 2006.203.07:43:53.24#ibcon#read 3, iclass 23, count 0 2006.203.07:43:53.24#ibcon#about to read 4, iclass 23, count 0 2006.203.07:43:53.24#ibcon#read 4, iclass 23, count 0 2006.203.07:43:53.24#ibcon#about to read 5, iclass 23, count 0 2006.203.07:43:53.24#ibcon#read 5, iclass 23, count 0 2006.203.07:43:53.24#ibcon#about to read 6, iclass 23, count 0 2006.203.07:43:53.24#ibcon#read 6, iclass 23, count 0 2006.203.07:43:53.24#ibcon#end of sib2, iclass 23, count 0 2006.203.07:43:53.24#ibcon#*after write, iclass 23, count 0 2006.203.07:43:53.24#ibcon#*before return 0, iclass 23, count 0 2006.203.07:43:53.24#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.203.07:43:53.24#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.203.07:43:53.24#ibcon#about to clear, iclass 23 cls_cnt 0 2006.203.07:43:53.24#ibcon#cleared, iclass 23 cls_cnt 0 2006.203.07:43:53.24$vc4f8/vblo=6,752.99 2006.203.07:43:53.24#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.203.07:43:53.24#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.203.07:43:53.24#ibcon#ireg 17 cls_cnt 0 2006.203.07:43:53.24#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.203.07:43:53.24#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.203.07:43:53.24#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.203.07:43:53.24#ibcon#enter wrdev, iclass 25, count 0 2006.203.07:43:53.24#ibcon#first serial, iclass 25, count 0 2006.203.07:43:53.24#ibcon#enter sib2, iclass 25, count 0 2006.203.07:43:53.24#ibcon#flushed, iclass 25, count 0 2006.203.07:43:53.24#ibcon#about to write, iclass 25, count 0 2006.203.07:43:53.24#ibcon#wrote, iclass 25, count 0 2006.203.07:43:53.24#ibcon#about to read 3, iclass 25, count 0 2006.203.07:43:53.26#ibcon#read 3, iclass 25, count 0 2006.203.07:43:53.26#ibcon#about to read 4, iclass 25, count 0 2006.203.07:43:53.26#ibcon#read 4, iclass 25, count 0 2006.203.07:43:53.26#ibcon#about to read 5, iclass 25, count 0 2006.203.07:43:53.26#ibcon#read 5, iclass 25, count 0 2006.203.07:43:53.26#ibcon#about to read 6, iclass 25, count 0 2006.203.07:43:53.26#ibcon#read 6, iclass 25, count 0 2006.203.07:43:53.26#ibcon#end of sib2, iclass 25, count 0 2006.203.07:43:53.26#ibcon#*mode == 0, iclass 25, count 0 2006.203.07:43:53.26#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.203.07:43:53.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.203.07:43:53.26#ibcon#*before write, iclass 25, count 0 2006.203.07:43:53.26#ibcon#enter sib2, iclass 25, count 0 2006.203.07:43:53.26#ibcon#flushed, iclass 25, count 0 2006.203.07:43:53.26#ibcon#about to write, iclass 25, count 0 2006.203.07:43:53.26#ibcon#wrote, iclass 25, count 0 2006.203.07:43:53.26#ibcon#about to read 3, iclass 25, count 0 2006.203.07:43:53.30#ibcon#read 3, iclass 25, count 0 2006.203.07:43:53.30#ibcon#about to read 4, iclass 25, count 0 2006.203.07:43:53.30#ibcon#read 4, iclass 25, count 0 2006.203.07:43:53.30#ibcon#about to read 5, iclass 25, count 0 2006.203.07:43:53.30#ibcon#read 5, iclass 25, count 0 2006.203.07:43:53.30#ibcon#about to read 6, iclass 25, count 0 2006.203.07:43:53.30#ibcon#read 6, iclass 25, count 0 2006.203.07:43:53.30#ibcon#end of sib2, iclass 25, count 0 2006.203.07:43:53.30#ibcon#*after write, iclass 25, count 0 2006.203.07:43:53.30#ibcon#*before return 0, iclass 25, count 0 2006.203.07:43:53.30#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.203.07:43:53.30#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.203.07:43:53.30#ibcon#about to clear, iclass 25 cls_cnt 0 2006.203.07:43:53.30#ibcon#cleared, iclass 25 cls_cnt 0 2006.203.07:43:53.30$vc4f8/vb=6,4 2006.203.07:43:53.30#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.203.07:43:53.30#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.203.07:43:53.30#ibcon#ireg 11 cls_cnt 2 2006.203.07:43:53.30#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.203.07:43:53.36#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.203.07:43:53.36#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.203.07:43:53.36#ibcon#enter wrdev, iclass 27, count 2 2006.203.07:43:53.36#ibcon#first serial, iclass 27, count 2 2006.203.07:43:53.36#ibcon#enter sib2, iclass 27, count 2 2006.203.07:43:53.36#ibcon#flushed, iclass 27, count 2 2006.203.07:43:53.36#ibcon#about to write, iclass 27, count 2 2006.203.07:43:53.36#ibcon#wrote, iclass 27, count 2 2006.203.07:43:53.36#ibcon#about to read 3, iclass 27, count 2 2006.203.07:43:53.38#ibcon#read 3, iclass 27, count 2 2006.203.07:43:53.38#ibcon#about to read 4, iclass 27, count 2 2006.203.07:43:53.38#ibcon#read 4, iclass 27, count 2 2006.203.07:43:53.38#ibcon#about to read 5, iclass 27, count 2 2006.203.07:43:53.38#ibcon#read 5, iclass 27, count 2 2006.203.07:43:53.38#ibcon#about to read 6, iclass 27, count 2 2006.203.07:43:53.38#ibcon#read 6, iclass 27, count 2 2006.203.07:43:53.38#ibcon#end of sib2, iclass 27, count 2 2006.203.07:43:53.38#ibcon#*mode == 0, iclass 27, count 2 2006.203.07:43:53.38#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.203.07:43:53.38#ibcon#[27=AT06-04\r\n] 2006.203.07:43:53.38#ibcon#*before write, iclass 27, count 2 2006.203.07:43:53.38#ibcon#enter sib2, iclass 27, count 2 2006.203.07:43:53.38#ibcon#flushed, iclass 27, count 2 2006.203.07:43:53.38#ibcon#about to write, iclass 27, count 2 2006.203.07:43:53.38#ibcon#wrote, iclass 27, count 2 2006.203.07:43:53.38#ibcon#about to read 3, iclass 27, count 2 2006.203.07:43:53.41#ibcon#read 3, iclass 27, count 2 2006.203.07:43:53.41#ibcon#about to read 4, iclass 27, count 2 2006.203.07:43:53.41#ibcon#read 4, iclass 27, count 2 2006.203.07:43:53.41#ibcon#about to read 5, iclass 27, count 2 2006.203.07:43:53.41#ibcon#read 5, iclass 27, count 2 2006.203.07:43:53.41#ibcon#about to read 6, iclass 27, count 2 2006.203.07:43:53.41#ibcon#read 6, iclass 27, count 2 2006.203.07:43:53.41#ibcon#end of sib2, iclass 27, count 2 2006.203.07:43:53.41#ibcon#*after write, iclass 27, count 2 2006.203.07:43:53.41#ibcon#*before return 0, iclass 27, count 2 2006.203.07:43:53.41#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.203.07:43:53.41#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.203.07:43:53.41#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.203.07:43:53.41#ibcon#ireg 7 cls_cnt 0 2006.203.07:43:53.41#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.203.07:43:53.53#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.203.07:43:53.53#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.203.07:43:53.53#ibcon#enter wrdev, iclass 27, count 0 2006.203.07:43:53.53#ibcon#first serial, iclass 27, count 0 2006.203.07:43:53.53#ibcon#enter sib2, iclass 27, count 0 2006.203.07:43:53.53#ibcon#flushed, iclass 27, count 0 2006.203.07:43:53.53#ibcon#about to write, iclass 27, count 0 2006.203.07:43:53.53#ibcon#wrote, iclass 27, count 0 2006.203.07:43:53.53#ibcon#about to read 3, iclass 27, count 0 2006.203.07:43:53.55#ibcon#read 3, iclass 27, count 0 2006.203.07:43:53.55#ibcon#about to read 4, iclass 27, count 0 2006.203.07:43:53.55#ibcon#read 4, iclass 27, count 0 2006.203.07:43:53.55#ibcon#about to read 5, iclass 27, count 0 2006.203.07:43:53.55#ibcon#read 5, iclass 27, count 0 2006.203.07:43:53.55#ibcon#about to read 6, iclass 27, count 0 2006.203.07:43:53.55#ibcon#read 6, iclass 27, count 0 2006.203.07:43:53.55#ibcon#end of sib2, iclass 27, count 0 2006.203.07:43:53.55#ibcon#*mode == 0, iclass 27, count 0 2006.203.07:43:53.55#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.203.07:43:53.55#ibcon#[27=USB\r\n] 2006.203.07:43:53.55#ibcon#*before write, iclass 27, count 0 2006.203.07:43:53.55#ibcon#enter sib2, iclass 27, count 0 2006.203.07:43:53.55#ibcon#flushed, iclass 27, count 0 2006.203.07:43:53.55#ibcon#about to write, iclass 27, count 0 2006.203.07:43:53.55#ibcon#wrote, iclass 27, count 0 2006.203.07:43:53.55#ibcon#about to read 3, iclass 27, count 0 2006.203.07:43:53.58#ibcon#read 3, iclass 27, count 0 2006.203.07:43:53.58#ibcon#about to read 4, iclass 27, count 0 2006.203.07:43:53.58#ibcon#read 4, iclass 27, count 0 2006.203.07:43:53.58#ibcon#about to read 5, iclass 27, count 0 2006.203.07:43:53.58#ibcon#read 5, iclass 27, count 0 2006.203.07:43:53.58#ibcon#about to read 6, iclass 27, count 0 2006.203.07:43:53.58#ibcon#read 6, iclass 27, count 0 2006.203.07:43:53.58#ibcon#end of sib2, iclass 27, count 0 2006.203.07:43:53.58#ibcon#*after write, iclass 27, count 0 2006.203.07:43:53.58#ibcon#*before return 0, iclass 27, count 0 2006.203.07:43:53.58#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.203.07:43:53.58#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.203.07:43:53.58#ibcon#about to clear, iclass 27 cls_cnt 0 2006.203.07:43:53.58#ibcon#cleared, iclass 27 cls_cnt 0 2006.203.07:43:53.58$vc4f8/vabw=wide 2006.203.07:43:53.58#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.203.07:43:53.58#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.203.07:43:53.58#ibcon#ireg 8 cls_cnt 0 2006.203.07:43:53.58#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.203.07:43:53.58#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.203.07:43:53.58#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.203.07:43:53.58#ibcon#enter wrdev, iclass 29, count 0 2006.203.07:43:53.58#ibcon#first serial, iclass 29, count 0 2006.203.07:43:53.58#ibcon#enter sib2, iclass 29, count 0 2006.203.07:43:53.58#ibcon#flushed, iclass 29, count 0 2006.203.07:43:53.58#ibcon#about to write, iclass 29, count 0 2006.203.07:43:53.58#ibcon#wrote, iclass 29, count 0 2006.203.07:43:53.58#ibcon#about to read 3, iclass 29, count 0 2006.203.07:43:53.60#ibcon#read 3, iclass 29, count 0 2006.203.07:43:53.60#ibcon#about to read 4, iclass 29, count 0 2006.203.07:43:53.60#ibcon#read 4, iclass 29, count 0 2006.203.07:43:53.60#ibcon#about to read 5, iclass 29, count 0 2006.203.07:43:53.60#ibcon#read 5, iclass 29, count 0 2006.203.07:43:53.60#ibcon#about to read 6, iclass 29, count 0 2006.203.07:43:53.60#ibcon#read 6, iclass 29, count 0 2006.203.07:43:53.60#ibcon#end of sib2, iclass 29, count 0 2006.203.07:43:53.60#ibcon#*mode == 0, iclass 29, count 0 2006.203.07:43:53.60#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.203.07:43:53.60#ibcon#[25=BW32\r\n] 2006.203.07:43:53.60#ibcon#*before write, iclass 29, count 0 2006.203.07:43:53.60#ibcon#enter sib2, iclass 29, count 0 2006.203.07:43:53.60#ibcon#flushed, iclass 29, count 0 2006.203.07:43:53.60#ibcon#about to write, iclass 29, count 0 2006.203.07:43:53.60#ibcon#wrote, iclass 29, count 0 2006.203.07:43:53.60#ibcon#about to read 3, iclass 29, count 0 2006.203.07:43:53.63#ibcon#read 3, iclass 29, count 0 2006.203.07:43:53.63#ibcon#about to read 4, iclass 29, count 0 2006.203.07:43:53.63#ibcon#read 4, iclass 29, count 0 2006.203.07:43:53.63#ibcon#about to read 5, iclass 29, count 0 2006.203.07:43:53.63#ibcon#read 5, iclass 29, count 0 2006.203.07:43:53.63#ibcon#about to read 6, iclass 29, count 0 2006.203.07:43:53.63#ibcon#read 6, iclass 29, count 0 2006.203.07:43:53.63#ibcon#end of sib2, iclass 29, count 0 2006.203.07:43:53.63#ibcon#*after write, iclass 29, count 0 2006.203.07:43:53.63#ibcon#*before return 0, iclass 29, count 0 2006.203.07:43:53.63#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.203.07:43:53.63#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.203.07:43:53.63#ibcon#about to clear, iclass 29 cls_cnt 0 2006.203.07:43:53.63#ibcon#cleared, iclass 29 cls_cnt 0 2006.203.07:43:53.63$vc4f8/vbbw=wide 2006.203.07:43:53.63#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.203.07:43:53.63#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.203.07:43:53.63#ibcon#ireg 8 cls_cnt 0 2006.203.07:43:53.63#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.203.07:43:53.70#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.203.07:43:53.70#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.203.07:43:53.70#ibcon#enter wrdev, iclass 31, count 0 2006.203.07:43:53.70#ibcon#first serial, iclass 31, count 0 2006.203.07:43:53.70#ibcon#enter sib2, iclass 31, count 0 2006.203.07:43:53.70#ibcon#flushed, iclass 31, count 0 2006.203.07:43:53.70#ibcon#about to write, iclass 31, count 0 2006.203.07:43:53.70#ibcon#wrote, iclass 31, count 0 2006.203.07:43:53.70#ibcon#about to read 3, iclass 31, count 0 2006.203.07:43:53.73#ibcon#read 3, iclass 31, count 0 2006.203.07:43:53.73#ibcon#about to read 4, iclass 31, count 0 2006.203.07:43:53.73#ibcon#read 4, iclass 31, count 0 2006.203.07:43:53.73#ibcon#about to read 5, iclass 31, count 0 2006.203.07:43:53.73#ibcon#read 5, iclass 31, count 0 2006.203.07:43:53.73#ibcon#about to read 6, iclass 31, count 0 2006.203.07:43:53.73#ibcon#read 6, iclass 31, count 0 2006.203.07:43:53.73#ibcon#end of sib2, iclass 31, count 0 2006.203.07:43:53.73#ibcon#*mode == 0, iclass 31, count 0 2006.203.07:43:53.73#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.203.07:43:53.73#ibcon#[27=BW32\r\n] 2006.203.07:43:53.73#ibcon#*before write, iclass 31, count 0 2006.203.07:43:53.73#ibcon#enter sib2, iclass 31, count 0 2006.203.07:43:53.73#ibcon#flushed, iclass 31, count 0 2006.203.07:43:53.73#ibcon#about to write, iclass 31, count 0 2006.203.07:43:53.73#ibcon#wrote, iclass 31, count 0 2006.203.07:43:53.73#ibcon#about to read 3, iclass 31, count 0 2006.203.07:43:53.76#ibcon#read 3, iclass 31, count 0 2006.203.07:43:53.76#ibcon#about to read 4, iclass 31, count 0 2006.203.07:43:53.76#ibcon#read 4, iclass 31, count 0 2006.203.07:43:53.76#ibcon#about to read 5, iclass 31, count 0 2006.203.07:43:53.76#ibcon#read 5, iclass 31, count 0 2006.203.07:43:53.76#ibcon#about to read 6, iclass 31, count 0 2006.203.07:43:53.76#ibcon#read 6, iclass 31, count 0 2006.203.07:43:53.76#ibcon#end of sib2, iclass 31, count 0 2006.203.07:43:53.76#ibcon#*after write, iclass 31, count 0 2006.203.07:43:53.76#ibcon#*before return 0, iclass 31, count 0 2006.203.07:43:53.76#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.203.07:43:53.76#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.203.07:43:53.76#ibcon#about to clear, iclass 31 cls_cnt 0 2006.203.07:43:53.76#ibcon#cleared, iclass 31 cls_cnt 0 2006.203.07:43:53.76$4f8m12a/ifd4f 2006.203.07:43:53.76$ifd4f/lo= 2006.203.07:43:53.76$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.203.07:43:53.76$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.203.07:43:53.76$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.203.07:43:53.76$ifd4f/patch= 2006.203.07:43:53.76$ifd4f/patch=lo1,a1,a2,a3,a4 2006.203.07:43:53.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.203.07:43:53.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.203.07:43:53.76$4f8m12a/"form=m,16.000,1:2 2006.203.07:43:53.76$4f8m12a/"tpicd 2006.203.07:43:53.76$4f8m12a/echo=off 2006.203.07:43:53.76$4f8m12a/xlog=off 2006.203.07:43:53.76:!2006.203.07:44:50 2006.203.07:44:27.14#trakl#Source acquired 2006.203.07:44:29.14#flagr#flagr/antenna,acquired 2006.203.07:44:50.00:preob 2006.203.07:44:51.14/onsource/TRACKING 2006.203.07:44:51.14:!2006.203.07:45:00 2006.203.07:45:00.00:data_valid=on 2006.203.07:45:00.00:midob 2006.203.07:45:00.14/onsource/TRACKING 2006.203.07:45:00.14/wx/23.90,1001.1,97 2006.203.07:45:00.22/cable/+6.4584E-03 2006.203.07:45:01.31/va/01,08,usb,yes,31,33 2006.203.07:45:01.31/va/02,07,usb,yes,31,33 2006.203.07:45:01.31/va/03,08,usb,yes,23,24 2006.203.07:45:01.31/va/04,07,usb,yes,32,35 2006.203.07:45:01.31/va/05,07,usb,yes,34,36 2006.203.07:45:01.31/va/06,06,usb,yes,34,33 2006.203.07:45:01.31/va/07,07,usb,yes,30,29 2006.203.07:45:01.31/va/08,06,usb,yes,36,36 2006.203.07:45:01.54/valo/01,532.99,yes,locked 2006.203.07:45:01.54/valo/02,572.99,yes,locked 2006.203.07:45:01.54/valo/03,672.99,yes,locked 2006.203.07:45:01.54/valo/04,832.99,yes,locked 2006.203.07:45:01.54/valo/05,652.99,yes,locked 2006.203.07:45:01.54/valo/06,772.99,yes,locked 2006.203.07:45:01.54/valo/07,832.99,yes,locked 2006.203.07:45:01.54/valo/08,852.99,yes,locked 2006.203.07:45:02.63/vb/01,04,usb,yes,28,27 2006.203.07:45:02.63/vb/02,04,usb,yes,30,31 2006.203.07:45:02.63/vb/03,04,usb,yes,27,30 2006.203.07:45:02.63/vb/04,04,usb,yes,27,27 2006.203.07:45:02.63/vb/05,03,usb,yes,33,37 2006.203.07:45:02.63/vb/06,04,usb,yes,27,30 2006.203.07:45:02.63/vb/07,04,usb,yes,29,29 2006.203.07:45:02.63/vb/08,04,usb,yes,27,30 2006.203.07:45:02.87/vblo/01,632.99,yes,locked 2006.203.07:45:02.87/vblo/02,640.99,yes,locked 2006.203.07:45:02.87/vblo/03,656.99,yes,locked 2006.203.07:45:02.87/vblo/04,712.99,yes,locked 2006.203.07:45:02.87/vblo/05,744.99,yes,locked 2006.203.07:45:02.87/vblo/06,752.99,yes,locked 2006.203.07:45:02.87/vblo/07,734.99,yes,locked 2006.203.07:45:02.87/vblo/08,744.99,yes,locked 2006.203.07:45:03.02/vabw/8 2006.203.07:45:03.17/vbbw/8 2006.203.07:45:03.26/xfe/off,on,16.0 2006.203.07:45:03.63/ifatt/23,28,28,28 2006.203.07:45:04.07/fmout-gps/S +4.53E-07 2006.203.07:45:04.15:!2006.203.07:46:00 2006.203.07:46:00.00:data_valid=off 2006.203.07:46:00.00:postob 2006.203.07:46:00.08/cable/+6.4604E-03 2006.203.07:46:00.08/wx/23.88,1001.1,98 2006.203.07:46:01.07/fmout-gps/S +4.53E-07 2006.203.07:46:01.07:scan_name=203-0747,k06203,60 2006.203.07:46:01.08:source=1357+769,135755.37,764321.1,2000.0,neutral 2006.203.07:46:01.14#flagr#flagr/antenna,new-source 2006.203.07:46:02.14:checkk5 2006.203.07:46:02.57/chk_autoobs//k5ts1/ autoobs is running! 2006.203.07:46:02.98/chk_autoobs//k5ts2/ autoobs is running! 2006.203.07:46:03.39/chk_autoobs//k5ts3/ autoobs is running! 2006.203.07:46:03.81/chk_autoobs//k5ts4/ autoobs is running! 2006.203.07:46:04.25/chk_obsdata//k5ts1/T2030745??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.203.07:46:04.68/chk_obsdata//k5ts2/T2030745??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.203.07:46:05.10/chk_obsdata//k5ts3/T2030745??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.203.07:46:05.48/chk_obsdata//k5ts4/T2030745??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.203.07:46:06.26/k5log//k5ts1_log_newline 2006.203.07:46:07.04/k5log//k5ts2_log_newline 2006.203.07:46:07.79/k5log//k5ts3_log_newline 2006.203.07:46:08.81/k5log//k5ts4_log_newline 2006.203.07:46:08.84/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.203.07:46:08.84:4f8m12a=1 2006.203.07:46:08.84$4f8m12a/echo=on 2006.203.07:46:08.84$4f8m12a/pcalon 2006.203.07:46:08.84$pcalon/"no phase cal control is implemented here 2006.203.07:46:08.84$4f8m12a/"tpicd=stop 2006.203.07:46:08.84$4f8m12a/vc4f8 2006.203.07:46:08.84$vc4f8/valo=1,532.99 2006.203.07:46:08.84#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.203.07:46:08.84#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.203.07:46:08.84#ibcon#ireg 17 cls_cnt 0 2006.203.07:46:08.84#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.203.07:46:08.84#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.203.07:46:08.84#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.203.07:46:08.84#ibcon#enter wrdev, iclass 14, count 0 2006.203.07:46:08.84#ibcon#first serial, iclass 14, count 0 2006.203.07:46:08.84#ibcon#enter sib2, iclass 14, count 0 2006.203.07:46:08.84#ibcon#flushed, iclass 14, count 0 2006.203.07:46:08.84#ibcon#about to write, iclass 14, count 0 2006.203.07:46:08.84#ibcon#wrote, iclass 14, count 0 2006.203.07:46:08.84#ibcon#about to read 3, iclass 14, count 0 2006.203.07:46:08.88#ibcon#read 3, iclass 14, count 0 2006.203.07:46:08.88#ibcon#about to read 4, iclass 14, count 0 2006.203.07:46:08.88#ibcon#read 4, iclass 14, count 0 2006.203.07:46:08.88#ibcon#about to read 5, iclass 14, count 0 2006.203.07:46:08.88#ibcon#read 5, iclass 14, count 0 2006.203.07:46:08.88#ibcon#about to read 6, iclass 14, count 0 2006.203.07:46:08.88#ibcon#read 6, iclass 14, count 0 2006.203.07:46:08.88#ibcon#end of sib2, iclass 14, count 0 2006.203.07:46:08.88#ibcon#*mode == 0, iclass 14, count 0 2006.203.07:46:08.88#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.203.07:46:08.88#ibcon#[26=FRQ=01,532.99\r\n] 2006.203.07:46:08.88#ibcon#*before write, iclass 14, count 0 2006.203.07:46:08.88#ibcon#enter sib2, iclass 14, count 0 2006.203.07:46:08.88#ibcon#flushed, iclass 14, count 0 2006.203.07:46:08.88#ibcon#about to write, iclass 14, count 0 2006.203.07:46:08.88#ibcon#wrote, iclass 14, count 0 2006.203.07:46:08.88#ibcon#about to read 3, iclass 14, count 0 2006.203.07:46:08.93#ibcon#read 3, iclass 14, count 0 2006.203.07:46:08.93#ibcon#about to read 4, iclass 14, count 0 2006.203.07:46:08.93#ibcon#read 4, iclass 14, count 0 2006.203.07:46:08.93#ibcon#about to read 5, iclass 14, count 0 2006.203.07:46:08.93#ibcon#read 5, iclass 14, count 0 2006.203.07:46:08.93#ibcon#about to read 6, iclass 14, count 0 2006.203.07:46:08.93#ibcon#read 6, iclass 14, count 0 2006.203.07:46:08.93#ibcon#end of sib2, iclass 14, count 0 2006.203.07:46:08.93#ibcon#*after write, iclass 14, count 0 2006.203.07:46:08.93#ibcon#*before return 0, iclass 14, count 0 2006.203.07:46:08.93#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.203.07:46:08.93#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.203.07:46:08.93#ibcon#about to clear, iclass 14 cls_cnt 0 2006.203.07:46:08.93#ibcon#cleared, iclass 14 cls_cnt 0 2006.203.07:46:08.93$vc4f8/va=1,8 2006.203.07:46:08.93#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.203.07:46:08.93#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.203.07:46:08.93#ibcon#ireg 11 cls_cnt 2 2006.203.07:46:08.93#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.203.07:46:08.93#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.203.07:46:08.93#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.203.07:46:08.93#ibcon#enter wrdev, iclass 16, count 2 2006.203.07:46:08.93#ibcon#first serial, iclass 16, count 2 2006.203.07:46:08.93#ibcon#enter sib2, iclass 16, count 2 2006.203.07:46:08.93#ibcon#flushed, iclass 16, count 2 2006.203.07:46:08.93#ibcon#about to write, iclass 16, count 2 2006.203.07:46:08.93#ibcon#wrote, iclass 16, count 2 2006.203.07:46:08.93#ibcon#about to read 3, iclass 16, count 2 2006.203.07:46:08.96#ibcon#read 3, iclass 16, count 2 2006.203.07:46:08.96#ibcon#about to read 4, iclass 16, count 2 2006.203.07:46:08.96#ibcon#read 4, iclass 16, count 2 2006.203.07:46:08.96#ibcon#about to read 5, iclass 16, count 2 2006.203.07:46:08.96#ibcon#read 5, iclass 16, count 2 2006.203.07:46:08.96#ibcon#about to read 6, iclass 16, count 2 2006.203.07:46:08.96#ibcon#read 6, iclass 16, count 2 2006.203.07:46:08.96#ibcon#end of sib2, iclass 16, count 2 2006.203.07:46:08.96#ibcon#*mode == 0, iclass 16, count 2 2006.203.07:46:08.96#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.203.07:46:08.96#ibcon#[25=AT01-08\r\n] 2006.203.07:46:08.96#ibcon#*before write, iclass 16, count 2 2006.203.07:46:08.96#ibcon#enter sib2, iclass 16, count 2 2006.203.07:46:08.96#ibcon#flushed, iclass 16, count 2 2006.203.07:46:08.96#ibcon#about to write, iclass 16, count 2 2006.203.07:46:08.96#ibcon#wrote, iclass 16, count 2 2006.203.07:46:08.96#ibcon#about to read 3, iclass 16, count 2 2006.203.07:46:08.99#ibcon#read 3, iclass 16, count 2 2006.203.07:46:08.99#ibcon#about to read 4, iclass 16, count 2 2006.203.07:46:08.99#ibcon#read 4, iclass 16, count 2 2006.203.07:46:08.99#ibcon#about to read 5, iclass 16, count 2 2006.203.07:46:08.99#ibcon#read 5, iclass 16, count 2 2006.203.07:46:08.99#ibcon#about to read 6, iclass 16, count 2 2006.203.07:46:08.99#ibcon#read 6, iclass 16, count 2 2006.203.07:46:08.99#ibcon#end of sib2, iclass 16, count 2 2006.203.07:46:08.99#ibcon#*after write, iclass 16, count 2 2006.203.07:46:08.99#ibcon#*before return 0, iclass 16, count 2 2006.203.07:46:08.99#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.203.07:46:08.99#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.203.07:46:08.99#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.203.07:46:08.99#ibcon#ireg 7 cls_cnt 0 2006.203.07:46:08.99#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.203.07:46:09.11#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.203.07:46:09.11#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.203.07:46:09.11#ibcon#enter wrdev, iclass 16, count 0 2006.203.07:46:09.11#ibcon#first serial, iclass 16, count 0 2006.203.07:46:09.11#ibcon#enter sib2, iclass 16, count 0 2006.203.07:46:09.11#ibcon#flushed, iclass 16, count 0 2006.203.07:46:09.11#ibcon#about to write, iclass 16, count 0 2006.203.07:46:09.11#ibcon#wrote, iclass 16, count 0 2006.203.07:46:09.11#ibcon#about to read 3, iclass 16, count 0 2006.203.07:46:09.13#ibcon#read 3, iclass 16, count 0 2006.203.07:46:09.13#ibcon#about to read 4, iclass 16, count 0 2006.203.07:46:09.13#ibcon#read 4, iclass 16, count 0 2006.203.07:46:09.13#ibcon#about to read 5, iclass 16, count 0 2006.203.07:46:09.13#ibcon#read 5, iclass 16, count 0 2006.203.07:46:09.13#ibcon#about to read 6, iclass 16, count 0 2006.203.07:46:09.13#ibcon#read 6, iclass 16, count 0 2006.203.07:46:09.13#ibcon#end of sib2, iclass 16, count 0 2006.203.07:46:09.13#ibcon#*mode == 0, iclass 16, count 0 2006.203.07:46:09.13#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.203.07:46:09.13#ibcon#[25=USB\r\n] 2006.203.07:46:09.13#ibcon#*before write, iclass 16, count 0 2006.203.07:46:09.13#ibcon#enter sib2, iclass 16, count 0 2006.203.07:46:09.13#ibcon#flushed, iclass 16, count 0 2006.203.07:46:09.13#ibcon#about to write, iclass 16, count 0 2006.203.07:46:09.13#ibcon#wrote, iclass 16, count 0 2006.203.07:46:09.13#ibcon#about to read 3, iclass 16, count 0 2006.203.07:46:09.16#ibcon#read 3, iclass 16, count 0 2006.203.07:46:09.16#ibcon#about to read 4, iclass 16, count 0 2006.203.07:46:09.16#ibcon#read 4, iclass 16, count 0 2006.203.07:46:09.16#ibcon#about to read 5, iclass 16, count 0 2006.203.07:46:09.16#ibcon#read 5, iclass 16, count 0 2006.203.07:46:09.16#ibcon#about to read 6, iclass 16, count 0 2006.203.07:46:09.16#ibcon#read 6, iclass 16, count 0 2006.203.07:46:09.16#ibcon#end of sib2, iclass 16, count 0 2006.203.07:46:09.16#ibcon#*after write, iclass 16, count 0 2006.203.07:46:09.16#ibcon#*before return 0, iclass 16, count 0 2006.203.07:46:09.16#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.203.07:46:09.16#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.203.07:46:09.16#ibcon#about to clear, iclass 16 cls_cnt 0 2006.203.07:46:09.16#ibcon#cleared, iclass 16 cls_cnt 0 2006.203.07:46:09.16$vc4f8/valo=2,572.99 2006.203.07:46:09.16#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.203.07:46:09.16#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.203.07:46:09.16#ibcon#ireg 17 cls_cnt 0 2006.203.07:46:09.16#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.203.07:46:09.16#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.203.07:46:09.16#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.203.07:46:09.16#ibcon#enter wrdev, iclass 18, count 0 2006.203.07:46:09.16#ibcon#first serial, iclass 18, count 0 2006.203.07:46:09.16#ibcon#enter sib2, iclass 18, count 0 2006.203.07:46:09.16#ibcon#flushed, iclass 18, count 0 2006.203.07:46:09.16#ibcon#about to write, iclass 18, count 0 2006.203.07:46:09.16#ibcon#wrote, iclass 18, count 0 2006.203.07:46:09.16#ibcon#about to read 3, iclass 18, count 0 2006.203.07:46:09.18#ibcon#read 3, iclass 18, count 0 2006.203.07:46:09.18#ibcon#about to read 4, iclass 18, count 0 2006.203.07:46:09.18#ibcon#read 4, iclass 18, count 0 2006.203.07:46:09.18#ibcon#about to read 5, iclass 18, count 0 2006.203.07:46:09.18#ibcon#read 5, iclass 18, count 0 2006.203.07:46:09.18#ibcon#about to read 6, iclass 18, count 0 2006.203.07:46:09.18#ibcon#read 6, iclass 18, count 0 2006.203.07:46:09.18#ibcon#end of sib2, iclass 18, count 0 2006.203.07:46:09.18#ibcon#*mode == 0, iclass 18, count 0 2006.203.07:46:09.18#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.203.07:46:09.18#ibcon#[26=FRQ=02,572.99\r\n] 2006.203.07:46:09.18#ibcon#*before write, iclass 18, count 0 2006.203.07:46:09.18#ibcon#enter sib2, iclass 18, count 0 2006.203.07:46:09.18#ibcon#flushed, iclass 18, count 0 2006.203.07:46:09.18#ibcon#about to write, iclass 18, count 0 2006.203.07:46:09.18#ibcon#wrote, iclass 18, count 0 2006.203.07:46:09.18#ibcon#about to read 3, iclass 18, count 0 2006.203.07:46:09.22#ibcon#read 3, iclass 18, count 0 2006.203.07:46:09.22#ibcon#about to read 4, iclass 18, count 0 2006.203.07:46:09.22#ibcon#read 4, iclass 18, count 0 2006.203.07:46:09.22#ibcon#about to read 5, iclass 18, count 0 2006.203.07:46:09.22#ibcon#read 5, iclass 18, count 0 2006.203.07:46:09.22#ibcon#about to read 6, iclass 18, count 0 2006.203.07:46:09.22#ibcon#read 6, iclass 18, count 0 2006.203.07:46:09.22#ibcon#end of sib2, iclass 18, count 0 2006.203.07:46:09.22#ibcon#*after write, iclass 18, count 0 2006.203.07:46:09.22#ibcon#*before return 0, iclass 18, count 0 2006.203.07:46:09.22#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.203.07:46:09.22#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.203.07:46:09.22#ibcon#about to clear, iclass 18 cls_cnt 0 2006.203.07:46:09.22#ibcon#cleared, iclass 18 cls_cnt 0 2006.203.07:46:09.22$vc4f8/va=2,7 2006.203.07:46:09.22#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.203.07:46:09.22#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.203.07:46:09.22#ibcon#ireg 11 cls_cnt 2 2006.203.07:46:09.22#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.203.07:46:09.29#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.203.07:46:09.29#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.203.07:46:09.29#ibcon#enter wrdev, iclass 20, count 2 2006.203.07:46:09.29#ibcon#first serial, iclass 20, count 2 2006.203.07:46:09.29#ibcon#enter sib2, iclass 20, count 2 2006.203.07:46:09.29#ibcon#flushed, iclass 20, count 2 2006.203.07:46:09.29#ibcon#about to write, iclass 20, count 2 2006.203.07:46:09.29#ibcon#wrote, iclass 20, count 2 2006.203.07:46:09.29#ibcon#about to read 3, iclass 20, count 2 2006.203.07:46:09.30#ibcon#read 3, iclass 20, count 2 2006.203.07:46:09.30#ibcon#about to read 4, iclass 20, count 2 2006.203.07:46:09.30#ibcon#read 4, iclass 20, count 2 2006.203.07:46:09.30#ibcon#about to read 5, iclass 20, count 2 2006.203.07:46:09.30#ibcon#read 5, iclass 20, count 2 2006.203.07:46:09.30#ibcon#about to read 6, iclass 20, count 2 2006.203.07:46:09.30#ibcon#read 6, iclass 20, count 2 2006.203.07:46:09.30#ibcon#end of sib2, iclass 20, count 2 2006.203.07:46:09.30#ibcon#*mode == 0, iclass 20, count 2 2006.203.07:46:09.30#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.203.07:46:09.30#ibcon#[25=AT02-07\r\n] 2006.203.07:46:09.30#ibcon#*before write, iclass 20, count 2 2006.203.07:46:09.30#ibcon#enter sib2, iclass 20, count 2 2006.203.07:46:09.30#ibcon#flushed, iclass 20, count 2 2006.203.07:46:09.30#ibcon#about to write, iclass 20, count 2 2006.203.07:46:09.30#ibcon#wrote, iclass 20, count 2 2006.203.07:46:09.30#ibcon#about to read 3, iclass 20, count 2 2006.203.07:46:09.33#ibcon#read 3, iclass 20, count 2 2006.203.07:46:09.33#ibcon#about to read 4, iclass 20, count 2 2006.203.07:46:09.33#ibcon#read 4, iclass 20, count 2 2006.203.07:46:09.33#ibcon#about to read 5, iclass 20, count 2 2006.203.07:46:09.33#ibcon#read 5, iclass 20, count 2 2006.203.07:46:09.33#ibcon#about to read 6, iclass 20, count 2 2006.203.07:46:09.33#ibcon#read 6, iclass 20, count 2 2006.203.07:46:09.33#ibcon#end of sib2, iclass 20, count 2 2006.203.07:46:09.33#ibcon#*after write, iclass 20, count 2 2006.203.07:46:09.33#ibcon#*before return 0, iclass 20, count 2 2006.203.07:46:09.33#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.203.07:46:09.33#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.203.07:46:09.33#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.203.07:46:09.33#ibcon#ireg 7 cls_cnt 0 2006.203.07:46:09.33#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.203.07:46:09.45#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.203.07:46:09.45#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.203.07:46:09.45#ibcon#enter wrdev, iclass 20, count 0 2006.203.07:46:09.45#ibcon#first serial, iclass 20, count 0 2006.203.07:46:09.45#ibcon#enter sib2, iclass 20, count 0 2006.203.07:46:09.45#ibcon#flushed, iclass 20, count 0 2006.203.07:46:09.45#ibcon#about to write, iclass 20, count 0 2006.203.07:46:09.45#ibcon#wrote, iclass 20, count 0 2006.203.07:46:09.45#ibcon#about to read 3, iclass 20, count 0 2006.203.07:46:09.47#ibcon#read 3, iclass 20, count 0 2006.203.07:46:09.47#ibcon#about to read 4, iclass 20, count 0 2006.203.07:46:09.47#ibcon#read 4, iclass 20, count 0 2006.203.07:46:09.47#ibcon#about to read 5, iclass 20, count 0 2006.203.07:46:09.47#ibcon#read 5, iclass 20, count 0 2006.203.07:46:09.47#ibcon#about to read 6, iclass 20, count 0 2006.203.07:46:09.47#ibcon#read 6, iclass 20, count 0 2006.203.07:46:09.47#ibcon#end of sib2, iclass 20, count 0 2006.203.07:46:09.47#ibcon#*mode == 0, iclass 20, count 0 2006.203.07:46:09.47#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.203.07:46:09.47#ibcon#[25=USB\r\n] 2006.203.07:46:09.47#ibcon#*before write, iclass 20, count 0 2006.203.07:46:09.47#ibcon#enter sib2, iclass 20, count 0 2006.203.07:46:09.47#ibcon#flushed, iclass 20, count 0 2006.203.07:46:09.47#ibcon#about to write, iclass 20, count 0 2006.203.07:46:09.47#ibcon#wrote, iclass 20, count 0 2006.203.07:46:09.47#ibcon#about to read 3, iclass 20, count 0 2006.203.07:46:09.50#ibcon#read 3, iclass 20, count 0 2006.203.07:46:09.50#ibcon#about to read 4, iclass 20, count 0 2006.203.07:46:09.50#ibcon#read 4, iclass 20, count 0 2006.203.07:46:09.50#ibcon#about to read 5, iclass 20, count 0 2006.203.07:46:09.50#ibcon#read 5, iclass 20, count 0 2006.203.07:46:09.50#ibcon#about to read 6, iclass 20, count 0 2006.203.07:46:09.50#ibcon#read 6, iclass 20, count 0 2006.203.07:46:09.50#ibcon#end of sib2, iclass 20, count 0 2006.203.07:46:09.50#ibcon#*after write, iclass 20, count 0 2006.203.07:46:09.50#ibcon#*before return 0, iclass 20, count 0 2006.203.07:46:09.50#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.203.07:46:09.50#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.203.07:46:09.50#ibcon#about to clear, iclass 20 cls_cnt 0 2006.203.07:46:09.50#ibcon#cleared, iclass 20 cls_cnt 0 2006.203.07:46:09.50$vc4f8/valo=3,672.99 2006.203.07:46:09.50#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.203.07:46:09.50#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.203.07:46:09.50#ibcon#ireg 17 cls_cnt 0 2006.203.07:46:09.50#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.203.07:46:09.50#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.203.07:46:09.50#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.203.07:46:09.50#ibcon#enter wrdev, iclass 22, count 0 2006.203.07:46:09.50#ibcon#first serial, iclass 22, count 0 2006.203.07:46:09.50#ibcon#enter sib2, iclass 22, count 0 2006.203.07:46:09.50#ibcon#flushed, iclass 22, count 0 2006.203.07:46:09.50#ibcon#about to write, iclass 22, count 0 2006.203.07:46:09.50#ibcon#wrote, iclass 22, count 0 2006.203.07:46:09.50#ibcon#about to read 3, iclass 22, count 0 2006.203.07:46:09.52#ibcon#read 3, iclass 22, count 0 2006.203.07:46:09.52#ibcon#about to read 4, iclass 22, count 0 2006.203.07:46:09.52#ibcon#read 4, iclass 22, count 0 2006.203.07:46:09.52#ibcon#about to read 5, iclass 22, count 0 2006.203.07:46:09.52#ibcon#read 5, iclass 22, count 0 2006.203.07:46:09.52#ibcon#about to read 6, iclass 22, count 0 2006.203.07:46:09.52#ibcon#read 6, iclass 22, count 0 2006.203.07:46:09.52#ibcon#end of sib2, iclass 22, count 0 2006.203.07:46:09.52#ibcon#*mode == 0, iclass 22, count 0 2006.203.07:46:09.52#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.203.07:46:09.52#ibcon#[26=FRQ=03,672.99\r\n] 2006.203.07:46:09.52#ibcon#*before write, iclass 22, count 0 2006.203.07:46:09.52#ibcon#enter sib2, iclass 22, count 0 2006.203.07:46:09.52#ibcon#flushed, iclass 22, count 0 2006.203.07:46:09.52#ibcon#about to write, iclass 22, count 0 2006.203.07:46:09.52#ibcon#wrote, iclass 22, count 0 2006.203.07:46:09.52#ibcon#about to read 3, iclass 22, count 0 2006.203.07:46:09.56#ibcon#read 3, iclass 22, count 0 2006.203.07:46:09.56#ibcon#about to read 4, iclass 22, count 0 2006.203.07:46:09.56#ibcon#read 4, iclass 22, count 0 2006.203.07:46:09.56#ibcon#about to read 5, iclass 22, count 0 2006.203.07:46:09.56#ibcon#read 5, iclass 22, count 0 2006.203.07:46:09.56#ibcon#about to read 6, iclass 22, count 0 2006.203.07:46:09.56#ibcon#read 6, iclass 22, count 0 2006.203.07:46:09.56#ibcon#end of sib2, iclass 22, count 0 2006.203.07:46:09.56#ibcon#*after write, iclass 22, count 0 2006.203.07:46:09.56#ibcon#*before return 0, iclass 22, count 0 2006.203.07:46:09.56#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.203.07:46:09.56#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.203.07:46:09.56#ibcon#about to clear, iclass 22 cls_cnt 0 2006.203.07:46:09.56#ibcon#cleared, iclass 22 cls_cnt 0 2006.203.07:46:09.56$vc4f8/va=3,8 2006.203.07:46:09.56#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.203.07:46:09.56#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.203.07:46:09.56#ibcon#ireg 11 cls_cnt 2 2006.203.07:46:09.56#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.203.07:46:09.63#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.203.07:46:09.63#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.203.07:46:09.63#ibcon#enter wrdev, iclass 24, count 2 2006.203.07:46:09.63#ibcon#first serial, iclass 24, count 2 2006.203.07:46:09.63#ibcon#enter sib2, iclass 24, count 2 2006.203.07:46:09.63#ibcon#flushed, iclass 24, count 2 2006.203.07:46:09.63#ibcon#about to write, iclass 24, count 2 2006.203.07:46:09.63#ibcon#wrote, iclass 24, count 2 2006.203.07:46:09.63#ibcon#about to read 3, iclass 24, count 2 2006.203.07:46:09.64#ibcon#read 3, iclass 24, count 2 2006.203.07:46:09.64#ibcon#about to read 4, iclass 24, count 2 2006.203.07:46:09.64#ibcon#read 4, iclass 24, count 2 2006.203.07:46:09.64#ibcon#about to read 5, iclass 24, count 2 2006.203.07:46:09.64#ibcon#read 5, iclass 24, count 2 2006.203.07:46:09.64#ibcon#about to read 6, iclass 24, count 2 2006.203.07:46:09.64#ibcon#read 6, iclass 24, count 2 2006.203.07:46:09.64#ibcon#end of sib2, iclass 24, count 2 2006.203.07:46:09.64#ibcon#*mode == 0, iclass 24, count 2 2006.203.07:46:09.64#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.203.07:46:09.64#ibcon#[25=AT03-08\r\n] 2006.203.07:46:09.64#ibcon#*before write, iclass 24, count 2 2006.203.07:46:09.64#ibcon#enter sib2, iclass 24, count 2 2006.203.07:46:09.64#ibcon#flushed, iclass 24, count 2 2006.203.07:46:09.64#ibcon#about to write, iclass 24, count 2 2006.203.07:46:09.64#ibcon#wrote, iclass 24, count 2 2006.203.07:46:09.64#ibcon#about to read 3, iclass 24, count 2 2006.203.07:46:09.67#ibcon#read 3, iclass 24, count 2 2006.203.07:46:09.67#ibcon#about to read 4, iclass 24, count 2 2006.203.07:46:09.67#ibcon#read 4, iclass 24, count 2 2006.203.07:46:09.67#ibcon#about to read 5, iclass 24, count 2 2006.203.07:46:09.67#ibcon#read 5, iclass 24, count 2 2006.203.07:46:09.67#ibcon#about to read 6, iclass 24, count 2 2006.203.07:46:09.67#ibcon#read 6, iclass 24, count 2 2006.203.07:46:09.67#ibcon#end of sib2, iclass 24, count 2 2006.203.07:46:09.67#ibcon#*after write, iclass 24, count 2 2006.203.07:46:09.67#ibcon#*before return 0, iclass 24, count 2 2006.203.07:46:09.67#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.203.07:46:09.67#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.203.07:46:09.67#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.203.07:46:09.67#ibcon#ireg 7 cls_cnt 0 2006.203.07:46:09.67#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.203.07:46:09.79#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.203.07:46:09.79#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.203.07:46:09.79#ibcon#enter wrdev, iclass 24, count 0 2006.203.07:46:09.79#ibcon#first serial, iclass 24, count 0 2006.203.07:46:09.79#ibcon#enter sib2, iclass 24, count 0 2006.203.07:46:09.79#ibcon#flushed, iclass 24, count 0 2006.203.07:46:09.79#ibcon#about to write, iclass 24, count 0 2006.203.07:46:09.79#ibcon#wrote, iclass 24, count 0 2006.203.07:46:09.79#ibcon#about to read 3, iclass 24, count 0 2006.203.07:46:09.81#ibcon#read 3, iclass 24, count 0 2006.203.07:46:09.81#ibcon#about to read 4, iclass 24, count 0 2006.203.07:46:09.81#ibcon#read 4, iclass 24, count 0 2006.203.07:46:09.81#ibcon#about to read 5, iclass 24, count 0 2006.203.07:46:09.81#ibcon#read 5, iclass 24, count 0 2006.203.07:46:09.81#ibcon#about to read 6, iclass 24, count 0 2006.203.07:46:09.81#ibcon#read 6, iclass 24, count 0 2006.203.07:46:09.81#ibcon#end of sib2, iclass 24, count 0 2006.203.07:46:09.81#ibcon#*mode == 0, iclass 24, count 0 2006.203.07:46:09.81#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.203.07:46:09.81#ibcon#[25=USB\r\n] 2006.203.07:46:09.81#ibcon#*before write, iclass 24, count 0 2006.203.07:46:09.81#ibcon#enter sib2, iclass 24, count 0 2006.203.07:46:09.81#ibcon#flushed, iclass 24, count 0 2006.203.07:46:09.81#ibcon#about to write, iclass 24, count 0 2006.203.07:46:09.81#ibcon#wrote, iclass 24, count 0 2006.203.07:46:09.81#ibcon#about to read 3, iclass 24, count 0 2006.203.07:46:09.84#ibcon#read 3, iclass 24, count 0 2006.203.07:46:09.84#ibcon#about to read 4, iclass 24, count 0 2006.203.07:46:09.84#ibcon#read 4, iclass 24, count 0 2006.203.07:46:09.84#ibcon#about to read 5, iclass 24, count 0 2006.203.07:46:09.84#ibcon#read 5, iclass 24, count 0 2006.203.07:46:09.84#ibcon#about to read 6, iclass 24, count 0 2006.203.07:46:09.84#ibcon#read 6, iclass 24, count 0 2006.203.07:46:09.84#ibcon#end of sib2, iclass 24, count 0 2006.203.07:46:09.84#ibcon#*after write, iclass 24, count 0 2006.203.07:46:09.84#ibcon#*before return 0, iclass 24, count 0 2006.203.07:46:09.84#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.203.07:46:09.84#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.203.07:46:09.84#ibcon#about to clear, iclass 24 cls_cnt 0 2006.203.07:46:09.84#ibcon#cleared, iclass 24 cls_cnt 0 2006.203.07:46:09.84$vc4f8/valo=4,832.99 2006.203.07:46:09.84#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.203.07:46:09.84#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.203.07:46:09.84#ibcon#ireg 17 cls_cnt 0 2006.203.07:46:09.84#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.203.07:46:09.84#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.203.07:46:09.84#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.203.07:46:09.84#ibcon#enter wrdev, iclass 26, count 0 2006.203.07:46:09.84#ibcon#first serial, iclass 26, count 0 2006.203.07:46:09.84#ibcon#enter sib2, iclass 26, count 0 2006.203.07:46:09.84#ibcon#flushed, iclass 26, count 0 2006.203.07:46:09.84#ibcon#about to write, iclass 26, count 0 2006.203.07:46:09.84#ibcon#wrote, iclass 26, count 0 2006.203.07:46:09.84#ibcon#about to read 3, iclass 26, count 0 2006.203.07:46:09.86#ibcon#read 3, iclass 26, count 0 2006.203.07:46:09.86#ibcon#about to read 4, iclass 26, count 0 2006.203.07:46:09.86#ibcon#read 4, iclass 26, count 0 2006.203.07:46:09.86#ibcon#about to read 5, iclass 26, count 0 2006.203.07:46:09.86#ibcon#read 5, iclass 26, count 0 2006.203.07:46:09.86#ibcon#about to read 6, iclass 26, count 0 2006.203.07:46:09.86#ibcon#read 6, iclass 26, count 0 2006.203.07:46:09.86#ibcon#end of sib2, iclass 26, count 0 2006.203.07:46:09.86#ibcon#*mode == 0, iclass 26, count 0 2006.203.07:46:09.86#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.203.07:46:09.86#ibcon#[26=FRQ=04,832.99\r\n] 2006.203.07:46:09.86#ibcon#*before write, iclass 26, count 0 2006.203.07:46:09.86#ibcon#enter sib2, iclass 26, count 0 2006.203.07:46:09.86#ibcon#flushed, iclass 26, count 0 2006.203.07:46:09.86#ibcon#about to write, iclass 26, count 0 2006.203.07:46:09.86#ibcon#wrote, iclass 26, count 0 2006.203.07:46:09.86#ibcon#about to read 3, iclass 26, count 0 2006.203.07:46:09.90#ibcon#read 3, iclass 26, count 0 2006.203.07:46:09.90#ibcon#about to read 4, iclass 26, count 0 2006.203.07:46:09.90#ibcon#read 4, iclass 26, count 0 2006.203.07:46:09.90#ibcon#about to read 5, iclass 26, count 0 2006.203.07:46:09.90#ibcon#read 5, iclass 26, count 0 2006.203.07:46:09.90#ibcon#about to read 6, iclass 26, count 0 2006.203.07:46:09.90#ibcon#read 6, iclass 26, count 0 2006.203.07:46:09.90#ibcon#end of sib2, iclass 26, count 0 2006.203.07:46:09.90#ibcon#*after write, iclass 26, count 0 2006.203.07:46:09.90#ibcon#*before return 0, iclass 26, count 0 2006.203.07:46:09.90#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.203.07:46:09.90#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.203.07:46:09.90#ibcon#about to clear, iclass 26 cls_cnt 0 2006.203.07:46:09.90#ibcon#cleared, iclass 26 cls_cnt 0 2006.203.07:46:09.90$vc4f8/va=4,7 2006.203.07:46:09.90#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.203.07:46:09.90#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.203.07:46:09.90#ibcon#ireg 11 cls_cnt 2 2006.203.07:46:09.90#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.203.07:46:09.96#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.203.07:46:09.96#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.203.07:46:09.96#ibcon#enter wrdev, iclass 28, count 2 2006.203.07:46:09.96#ibcon#first serial, iclass 28, count 2 2006.203.07:46:09.96#ibcon#enter sib2, iclass 28, count 2 2006.203.07:46:09.96#ibcon#flushed, iclass 28, count 2 2006.203.07:46:09.96#ibcon#about to write, iclass 28, count 2 2006.203.07:46:09.96#ibcon#wrote, iclass 28, count 2 2006.203.07:46:09.96#ibcon#about to read 3, iclass 28, count 2 2006.203.07:46:09.98#ibcon#read 3, iclass 28, count 2 2006.203.07:46:09.98#ibcon#about to read 4, iclass 28, count 2 2006.203.07:46:09.98#ibcon#read 4, iclass 28, count 2 2006.203.07:46:09.98#ibcon#about to read 5, iclass 28, count 2 2006.203.07:46:09.98#ibcon#read 5, iclass 28, count 2 2006.203.07:46:09.98#ibcon#about to read 6, iclass 28, count 2 2006.203.07:46:09.98#ibcon#read 6, iclass 28, count 2 2006.203.07:46:09.98#ibcon#end of sib2, iclass 28, count 2 2006.203.07:46:09.98#ibcon#*mode == 0, iclass 28, count 2 2006.203.07:46:09.98#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.203.07:46:09.98#ibcon#[25=AT04-07\r\n] 2006.203.07:46:09.98#ibcon#*before write, iclass 28, count 2 2006.203.07:46:09.98#ibcon#enter sib2, iclass 28, count 2 2006.203.07:46:09.98#ibcon#flushed, iclass 28, count 2 2006.203.07:46:09.98#ibcon#about to write, iclass 28, count 2 2006.203.07:46:09.98#ibcon#wrote, iclass 28, count 2 2006.203.07:46:09.98#ibcon#about to read 3, iclass 28, count 2 2006.203.07:46:10.01#ibcon#read 3, iclass 28, count 2 2006.203.07:46:10.01#ibcon#about to read 4, iclass 28, count 2 2006.203.07:46:10.01#ibcon#read 4, iclass 28, count 2 2006.203.07:46:10.01#ibcon#about to read 5, iclass 28, count 2 2006.203.07:46:10.01#ibcon#read 5, iclass 28, count 2 2006.203.07:46:10.01#ibcon#about to read 6, iclass 28, count 2 2006.203.07:46:10.01#ibcon#read 6, iclass 28, count 2 2006.203.07:46:10.01#ibcon#end of sib2, iclass 28, count 2 2006.203.07:46:10.01#ibcon#*after write, iclass 28, count 2 2006.203.07:46:10.01#ibcon#*before return 0, iclass 28, count 2 2006.203.07:46:10.01#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.203.07:46:10.01#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.203.07:46:10.01#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.203.07:46:10.01#ibcon#ireg 7 cls_cnt 0 2006.203.07:46:10.01#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.203.07:46:10.13#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.203.07:46:10.13#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.203.07:46:10.13#ibcon#enter wrdev, iclass 28, count 0 2006.203.07:46:10.13#ibcon#first serial, iclass 28, count 0 2006.203.07:46:10.13#ibcon#enter sib2, iclass 28, count 0 2006.203.07:46:10.13#ibcon#flushed, iclass 28, count 0 2006.203.07:46:10.13#ibcon#about to write, iclass 28, count 0 2006.203.07:46:10.13#ibcon#wrote, iclass 28, count 0 2006.203.07:46:10.13#ibcon#about to read 3, iclass 28, count 0 2006.203.07:46:10.15#ibcon#read 3, iclass 28, count 0 2006.203.07:46:10.15#ibcon#about to read 4, iclass 28, count 0 2006.203.07:46:10.15#ibcon#read 4, iclass 28, count 0 2006.203.07:46:10.15#ibcon#about to read 5, iclass 28, count 0 2006.203.07:46:10.15#ibcon#read 5, iclass 28, count 0 2006.203.07:46:10.15#ibcon#about to read 6, iclass 28, count 0 2006.203.07:46:10.15#ibcon#read 6, iclass 28, count 0 2006.203.07:46:10.15#ibcon#end of sib2, iclass 28, count 0 2006.203.07:46:10.15#ibcon#*mode == 0, iclass 28, count 0 2006.203.07:46:10.15#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.203.07:46:10.15#ibcon#[25=USB\r\n] 2006.203.07:46:10.15#ibcon#*before write, iclass 28, count 0 2006.203.07:46:10.15#ibcon#enter sib2, iclass 28, count 0 2006.203.07:46:10.15#ibcon#flushed, iclass 28, count 0 2006.203.07:46:10.15#ibcon#about to write, iclass 28, count 0 2006.203.07:46:10.15#ibcon#wrote, iclass 28, count 0 2006.203.07:46:10.15#ibcon#about to read 3, iclass 28, count 0 2006.203.07:46:10.18#ibcon#read 3, iclass 28, count 0 2006.203.07:46:10.18#ibcon#about to read 4, iclass 28, count 0 2006.203.07:46:10.18#ibcon#read 4, iclass 28, count 0 2006.203.07:46:10.18#ibcon#about to read 5, iclass 28, count 0 2006.203.07:46:10.18#ibcon#read 5, iclass 28, count 0 2006.203.07:46:10.18#ibcon#about to read 6, iclass 28, count 0 2006.203.07:46:10.18#ibcon#read 6, iclass 28, count 0 2006.203.07:46:10.18#ibcon#end of sib2, iclass 28, count 0 2006.203.07:46:10.18#ibcon#*after write, iclass 28, count 0 2006.203.07:46:10.18#ibcon#*before return 0, iclass 28, count 0 2006.203.07:46:10.18#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.203.07:46:10.18#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.203.07:46:10.18#ibcon#about to clear, iclass 28 cls_cnt 0 2006.203.07:46:10.18#ibcon#cleared, iclass 28 cls_cnt 0 2006.203.07:46:10.18$vc4f8/valo=5,652.99 2006.203.07:46:10.18#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.203.07:46:10.18#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.203.07:46:10.18#ibcon#ireg 17 cls_cnt 0 2006.203.07:46:10.18#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.203.07:46:10.18#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.203.07:46:10.18#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.203.07:46:10.18#ibcon#enter wrdev, iclass 30, count 0 2006.203.07:46:10.18#ibcon#first serial, iclass 30, count 0 2006.203.07:46:10.18#ibcon#enter sib2, iclass 30, count 0 2006.203.07:46:10.18#ibcon#flushed, iclass 30, count 0 2006.203.07:46:10.18#ibcon#about to write, iclass 30, count 0 2006.203.07:46:10.18#ibcon#wrote, iclass 30, count 0 2006.203.07:46:10.18#ibcon#about to read 3, iclass 30, count 0 2006.203.07:46:10.20#ibcon#read 3, iclass 30, count 0 2006.203.07:46:10.20#ibcon#about to read 4, iclass 30, count 0 2006.203.07:46:10.20#ibcon#read 4, iclass 30, count 0 2006.203.07:46:10.20#ibcon#about to read 5, iclass 30, count 0 2006.203.07:46:10.20#ibcon#read 5, iclass 30, count 0 2006.203.07:46:10.20#ibcon#about to read 6, iclass 30, count 0 2006.203.07:46:10.20#ibcon#read 6, iclass 30, count 0 2006.203.07:46:10.20#ibcon#end of sib2, iclass 30, count 0 2006.203.07:46:10.20#ibcon#*mode == 0, iclass 30, count 0 2006.203.07:46:10.20#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.203.07:46:10.20#ibcon#[26=FRQ=05,652.99\r\n] 2006.203.07:46:10.20#ibcon#*before write, iclass 30, count 0 2006.203.07:46:10.20#ibcon#enter sib2, iclass 30, count 0 2006.203.07:46:10.20#ibcon#flushed, iclass 30, count 0 2006.203.07:46:10.20#ibcon#about to write, iclass 30, count 0 2006.203.07:46:10.20#ibcon#wrote, iclass 30, count 0 2006.203.07:46:10.20#ibcon#about to read 3, iclass 30, count 0 2006.203.07:46:10.24#ibcon#read 3, iclass 30, count 0 2006.203.07:46:10.24#ibcon#about to read 4, iclass 30, count 0 2006.203.07:46:10.24#ibcon#read 4, iclass 30, count 0 2006.203.07:46:10.24#ibcon#about to read 5, iclass 30, count 0 2006.203.07:46:10.24#ibcon#read 5, iclass 30, count 0 2006.203.07:46:10.24#ibcon#about to read 6, iclass 30, count 0 2006.203.07:46:10.24#ibcon#read 6, iclass 30, count 0 2006.203.07:46:10.24#ibcon#end of sib2, iclass 30, count 0 2006.203.07:46:10.24#ibcon#*after write, iclass 30, count 0 2006.203.07:46:10.24#ibcon#*before return 0, iclass 30, count 0 2006.203.07:46:10.24#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.203.07:46:10.24#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.203.07:46:10.24#ibcon#about to clear, iclass 30 cls_cnt 0 2006.203.07:46:10.24#ibcon#cleared, iclass 30 cls_cnt 0 2006.203.07:46:10.24$vc4f8/va=5,7 2006.203.07:46:10.24#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.203.07:46:10.24#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.203.07:46:10.24#ibcon#ireg 11 cls_cnt 2 2006.203.07:46:10.24#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.203.07:46:10.31#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.203.07:46:10.31#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.203.07:46:10.31#ibcon#enter wrdev, iclass 32, count 2 2006.203.07:46:10.31#ibcon#first serial, iclass 32, count 2 2006.203.07:46:10.31#ibcon#enter sib2, iclass 32, count 2 2006.203.07:46:10.31#ibcon#flushed, iclass 32, count 2 2006.203.07:46:10.31#ibcon#about to write, iclass 32, count 2 2006.203.07:46:10.31#ibcon#wrote, iclass 32, count 2 2006.203.07:46:10.31#ibcon#about to read 3, iclass 32, count 2 2006.203.07:46:10.32#ibcon#read 3, iclass 32, count 2 2006.203.07:46:10.32#ibcon#about to read 4, iclass 32, count 2 2006.203.07:46:10.32#ibcon#read 4, iclass 32, count 2 2006.203.07:46:10.32#ibcon#about to read 5, iclass 32, count 2 2006.203.07:46:10.32#ibcon#read 5, iclass 32, count 2 2006.203.07:46:10.32#ibcon#about to read 6, iclass 32, count 2 2006.203.07:46:10.32#ibcon#read 6, iclass 32, count 2 2006.203.07:46:10.32#ibcon#end of sib2, iclass 32, count 2 2006.203.07:46:10.32#ibcon#*mode == 0, iclass 32, count 2 2006.203.07:46:10.32#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.203.07:46:10.32#ibcon#[25=AT05-07\r\n] 2006.203.07:46:10.32#ibcon#*before write, iclass 32, count 2 2006.203.07:46:10.32#ibcon#enter sib2, iclass 32, count 2 2006.203.07:46:10.32#ibcon#flushed, iclass 32, count 2 2006.203.07:46:10.32#ibcon#about to write, iclass 32, count 2 2006.203.07:46:10.32#ibcon#wrote, iclass 32, count 2 2006.203.07:46:10.32#ibcon#about to read 3, iclass 32, count 2 2006.203.07:46:10.35#ibcon#read 3, iclass 32, count 2 2006.203.07:46:10.35#ibcon#about to read 4, iclass 32, count 2 2006.203.07:46:10.35#ibcon#read 4, iclass 32, count 2 2006.203.07:46:10.35#ibcon#about to read 5, iclass 32, count 2 2006.203.07:46:10.35#ibcon#read 5, iclass 32, count 2 2006.203.07:46:10.35#ibcon#about to read 6, iclass 32, count 2 2006.203.07:46:10.35#ibcon#read 6, iclass 32, count 2 2006.203.07:46:10.35#ibcon#end of sib2, iclass 32, count 2 2006.203.07:46:10.35#ibcon#*after write, iclass 32, count 2 2006.203.07:46:10.35#ibcon#*before return 0, iclass 32, count 2 2006.203.07:46:10.35#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.203.07:46:10.35#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.203.07:46:10.35#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.203.07:46:10.35#ibcon#ireg 7 cls_cnt 0 2006.203.07:46:10.35#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.203.07:46:10.47#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.203.07:46:10.47#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.203.07:46:10.47#ibcon#enter wrdev, iclass 32, count 0 2006.203.07:46:10.47#ibcon#first serial, iclass 32, count 0 2006.203.07:46:10.47#ibcon#enter sib2, iclass 32, count 0 2006.203.07:46:10.47#ibcon#flushed, iclass 32, count 0 2006.203.07:46:10.47#ibcon#about to write, iclass 32, count 0 2006.203.07:46:10.47#ibcon#wrote, iclass 32, count 0 2006.203.07:46:10.47#ibcon#about to read 3, iclass 32, count 0 2006.203.07:46:10.49#ibcon#read 3, iclass 32, count 0 2006.203.07:46:10.49#ibcon#about to read 4, iclass 32, count 0 2006.203.07:46:10.49#ibcon#read 4, iclass 32, count 0 2006.203.07:46:10.49#ibcon#about to read 5, iclass 32, count 0 2006.203.07:46:10.49#ibcon#read 5, iclass 32, count 0 2006.203.07:46:10.49#ibcon#about to read 6, iclass 32, count 0 2006.203.07:46:10.49#ibcon#read 6, iclass 32, count 0 2006.203.07:46:10.49#ibcon#end of sib2, iclass 32, count 0 2006.203.07:46:10.49#ibcon#*mode == 0, iclass 32, count 0 2006.203.07:46:10.49#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.203.07:46:10.49#ibcon#[25=USB\r\n] 2006.203.07:46:10.49#ibcon#*before write, iclass 32, count 0 2006.203.07:46:10.49#ibcon#enter sib2, iclass 32, count 0 2006.203.07:46:10.49#ibcon#flushed, iclass 32, count 0 2006.203.07:46:10.49#ibcon#about to write, iclass 32, count 0 2006.203.07:46:10.49#ibcon#wrote, iclass 32, count 0 2006.203.07:46:10.49#ibcon#about to read 3, iclass 32, count 0 2006.203.07:46:10.52#ibcon#read 3, iclass 32, count 0 2006.203.07:46:10.52#ibcon#about to read 4, iclass 32, count 0 2006.203.07:46:10.52#ibcon#read 4, iclass 32, count 0 2006.203.07:46:10.52#ibcon#about to read 5, iclass 32, count 0 2006.203.07:46:10.52#ibcon#read 5, iclass 32, count 0 2006.203.07:46:10.52#ibcon#about to read 6, iclass 32, count 0 2006.203.07:46:10.52#ibcon#read 6, iclass 32, count 0 2006.203.07:46:10.52#ibcon#end of sib2, iclass 32, count 0 2006.203.07:46:10.52#ibcon#*after write, iclass 32, count 0 2006.203.07:46:10.52#ibcon#*before return 0, iclass 32, count 0 2006.203.07:46:10.52#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.203.07:46:10.52#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.203.07:46:10.52#ibcon#about to clear, iclass 32 cls_cnt 0 2006.203.07:46:10.52#ibcon#cleared, iclass 32 cls_cnt 0 2006.203.07:46:10.52$vc4f8/valo=6,772.99 2006.203.07:46:10.52#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.203.07:46:10.52#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.203.07:46:10.52#ibcon#ireg 17 cls_cnt 0 2006.203.07:46:10.52#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.203.07:46:10.52#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.203.07:46:10.52#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.203.07:46:10.52#ibcon#enter wrdev, iclass 34, count 0 2006.203.07:46:10.52#ibcon#first serial, iclass 34, count 0 2006.203.07:46:10.52#ibcon#enter sib2, iclass 34, count 0 2006.203.07:46:10.52#ibcon#flushed, iclass 34, count 0 2006.203.07:46:10.52#ibcon#about to write, iclass 34, count 0 2006.203.07:46:10.52#ibcon#wrote, iclass 34, count 0 2006.203.07:46:10.52#ibcon#about to read 3, iclass 34, count 0 2006.203.07:46:10.54#ibcon#read 3, iclass 34, count 0 2006.203.07:46:10.54#ibcon#about to read 4, iclass 34, count 0 2006.203.07:46:10.54#ibcon#read 4, iclass 34, count 0 2006.203.07:46:10.54#ibcon#about to read 5, iclass 34, count 0 2006.203.07:46:10.54#ibcon#read 5, iclass 34, count 0 2006.203.07:46:10.54#ibcon#about to read 6, iclass 34, count 0 2006.203.07:46:10.54#ibcon#read 6, iclass 34, count 0 2006.203.07:46:10.54#ibcon#end of sib2, iclass 34, count 0 2006.203.07:46:10.54#ibcon#*mode == 0, iclass 34, count 0 2006.203.07:46:10.54#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.203.07:46:10.54#ibcon#[26=FRQ=06,772.99\r\n] 2006.203.07:46:10.54#ibcon#*before write, iclass 34, count 0 2006.203.07:46:10.54#ibcon#enter sib2, iclass 34, count 0 2006.203.07:46:10.54#ibcon#flushed, iclass 34, count 0 2006.203.07:46:10.54#ibcon#about to write, iclass 34, count 0 2006.203.07:46:10.54#ibcon#wrote, iclass 34, count 0 2006.203.07:46:10.54#ibcon#about to read 3, iclass 34, count 0 2006.203.07:46:10.58#ibcon#read 3, iclass 34, count 0 2006.203.07:46:10.58#ibcon#about to read 4, iclass 34, count 0 2006.203.07:46:10.58#ibcon#read 4, iclass 34, count 0 2006.203.07:46:10.58#ibcon#about to read 5, iclass 34, count 0 2006.203.07:46:10.58#ibcon#read 5, iclass 34, count 0 2006.203.07:46:10.58#ibcon#about to read 6, iclass 34, count 0 2006.203.07:46:10.58#ibcon#read 6, iclass 34, count 0 2006.203.07:46:10.58#ibcon#end of sib2, iclass 34, count 0 2006.203.07:46:10.58#ibcon#*after write, iclass 34, count 0 2006.203.07:46:10.58#ibcon#*before return 0, iclass 34, count 0 2006.203.07:46:10.58#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.203.07:46:10.58#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.203.07:46:10.58#ibcon#about to clear, iclass 34 cls_cnt 0 2006.203.07:46:10.58#ibcon#cleared, iclass 34 cls_cnt 0 2006.203.07:46:10.58$vc4f8/va=6,6 2006.203.07:46:10.58#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.203.07:46:10.58#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.203.07:46:10.58#ibcon#ireg 11 cls_cnt 2 2006.203.07:46:10.58#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.203.07:46:10.65#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.203.07:46:10.65#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.203.07:46:10.65#ibcon#enter wrdev, iclass 36, count 2 2006.203.07:46:10.65#ibcon#first serial, iclass 36, count 2 2006.203.07:46:10.65#ibcon#enter sib2, iclass 36, count 2 2006.203.07:46:10.65#ibcon#flushed, iclass 36, count 2 2006.203.07:46:10.65#ibcon#about to write, iclass 36, count 2 2006.203.07:46:10.65#ibcon#wrote, iclass 36, count 2 2006.203.07:46:10.65#ibcon#about to read 3, iclass 36, count 2 2006.203.07:46:10.66#ibcon#read 3, iclass 36, count 2 2006.203.07:46:10.66#ibcon#about to read 4, iclass 36, count 2 2006.203.07:46:10.66#ibcon#read 4, iclass 36, count 2 2006.203.07:46:10.66#ibcon#about to read 5, iclass 36, count 2 2006.203.07:46:10.66#ibcon#read 5, iclass 36, count 2 2006.203.07:46:10.66#ibcon#about to read 6, iclass 36, count 2 2006.203.07:46:10.66#ibcon#read 6, iclass 36, count 2 2006.203.07:46:10.66#ibcon#end of sib2, iclass 36, count 2 2006.203.07:46:10.66#ibcon#*mode == 0, iclass 36, count 2 2006.203.07:46:10.66#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.203.07:46:10.66#ibcon#[25=AT06-06\r\n] 2006.203.07:46:10.66#ibcon#*before write, iclass 36, count 2 2006.203.07:46:10.66#ibcon#enter sib2, iclass 36, count 2 2006.203.07:46:10.66#ibcon#flushed, iclass 36, count 2 2006.203.07:46:10.66#ibcon#about to write, iclass 36, count 2 2006.203.07:46:10.66#ibcon#wrote, iclass 36, count 2 2006.203.07:46:10.66#ibcon#about to read 3, iclass 36, count 2 2006.203.07:46:10.69#ibcon#read 3, iclass 36, count 2 2006.203.07:46:10.69#ibcon#about to read 4, iclass 36, count 2 2006.203.07:46:10.69#ibcon#read 4, iclass 36, count 2 2006.203.07:46:10.69#ibcon#about to read 5, iclass 36, count 2 2006.203.07:46:10.69#ibcon#read 5, iclass 36, count 2 2006.203.07:46:10.69#ibcon#about to read 6, iclass 36, count 2 2006.203.07:46:10.69#ibcon#read 6, iclass 36, count 2 2006.203.07:46:10.69#ibcon#end of sib2, iclass 36, count 2 2006.203.07:46:10.69#ibcon#*after write, iclass 36, count 2 2006.203.07:46:10.69#ibcon#*before return 0, iclass 36, count 2 2006.203.07:46:10.69#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.203.07:46:10.69#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.203.07:46:10.69#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.203.07:46:10.69#ibcon#ireg 7 cls_cnt 0 2006.203.07:46:10.69#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.203.07:46:10.81#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.203.07:46:10.81#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.203.07:46:10.81#ibcon#enter wrdev, iclass 36, count 0 2006.203.07:46:10.81#ibcon#first serial, iclass 36, count 0 2006.203.07:46:10.81#ibcon#enter sib2, iclass 36, count 0 2006.203.07:46:10.81#ibcon#flushed, iclass 36, count 0 2006.203.07:46:10.81#ibcon#about to write, iclass 36, count 0 2006.203.07:46:10.81#ibcon#wrote, iclass 36, count 0 2006.203.07:46:10.81#ibcon#about to read 3, iclass 36, count 0 2006.203.07:46:10.83#ibcon#read 3, iclass 36, count 0 2006.203.07:46:10.83#ibcon#about to read 4, iclass 36, count 0 2006.203.07:46:10.83#ibcon#read 4, iclass 36, count 0 2006.203.07:46:10.83#ibcon#about to read 5, iclass 36, count 0 2006.203.07:46:10.83#ibcon#read 5, iclass 36, count 0 2006.203.07:46:10.83#ibcon#about to read 6, iclass 36, count 0 2006.203.07:46:10.83#ibcon#read 6, iclass 36, count 0 2006.203.07:46:10.83#ibcon#end of sib2, iclass 36, count 0 2006.203.07:46:10.83#ibcon#*mode == 0, iclass 36, count 0 2006.203.07:46:10.83#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.203.07:46:10.83#ibcon#[25=USB\r\n] 2006.203.07:46:10.83#ibcon#*before write, iclass 36, count 0 2006.203.07:46:10.83#ibcon#enter sib2, iclass 36, count 0 2006.203.07:46:10.83#ibcon#flushed, iclass 36, count 0 2006.203.07:46:10.83#ibcon#about to write, iclass 36, count 0 2006.203.07:46:10.83#ibcon#wrote, iclass 36, count 0 2006.203.07:46:10.83#ibcon#about to read 3, iclass 36, count 0 2006.203.07:46:10.86#ibcon#read 3, iclass 36, count 0 2006.203.07:46:10.86#ibcon#about to read 4, iclass 36, count 0 2006.203.07:46:10.86#ibcon#read 4, iclass 36, count 0 2006.203.07:46:10.86#ibcon#about to read 5, iclass 36, count 0 2006.203.07:46:10.86#ibcon#read 5, iclass 36, count 0 2006.203.07:46:10.86#ibcon#about to read 6, iclass 36, count 0 2006.203.07:46:10.86#ibcon#read 6, iclass 36, count 0 2006.203.07:46:10.86#ibcon#end of sib2, iclass 36, count 0 2006.203.07:46:10.86#ibcon#*after write, iclass 36, count 0 2006.203.07:46:10.86#ibcon#*before return 0, iclass 36, count 0 2006.203.07:46:10.86#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.203.07:46:10.86#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.203.07:46:10.86#ibcon#about to clear, iclass 36 cls_cnt 0 2006.203.07:46:10.86#ibcon#cleared, iclass 36 cls_cnt 0 2006.203.07:46:10.86$vc4f8/valo=7,832.99 2006.203.07:46:10.86#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.203.07:46:10.86#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.203.07:46:10.86#ibcon#ireg 17 cls_cnt 0 2006.203.07:46:10.86#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.203.07:46:10.86#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.203.07:46:10.86#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.203.07:46:10.86#ibcon#enter wrdev, iclass 38, count 0 2006.203.07:46:10.86#ibcon#first serial, iclass 38, count 0 2006.203.07:46:10.86#ibcon#enter sib2, iclass 38, count 0 2006.203.07:46:10.86#ibcon#flushed, iclass 38, count 0 2006.203.07:46:10.86#ibcon#about to write, iclass 38, count 0 2006.203.07:46:10.86#ibcon#wrote, iclass 38, count 0 2006.203.07:46:10.86#ibcon#about to read 3, iclass 38, count 0 2006.203.07:46:10.88#ibcon#read 3, iclass 38, count 0 2006.203.07:46:10.88#ibcon#about to read 4, iclass 38, count 0 2006.203.07:46:10.88#ibcon#read 4, iclass 38, count 0 2006.203.07:46:10.88#ibcon#about to read 5, iclass 38, count 0 2006.203.07:46:10.88#ibcon#read 5, iclass 38, count 0 2006.203.07:46:10.88#ibcon#about to read 6, iclass 38, count 0 2006.203.07:46:10.88#ibcon#read 6, iclass 38, count 0 2006.203.07:46:10.88#ibcon#end of sib2, iclass 38, count 0 2006.203.07:46:10.88#ibcon#*mode == 0, iclass 38, count 0 2006.203.07:46:10.88#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.203.07:46:10.88#ibcon#[26=FRQ=07,832.99\r\n] 2006.203.07:46:10.88#ibcon#*before write, iclass 38, count 0 2006.203.07:46:10.88#ibcon#enter sib2, iclass 38, count 0 2006.203.07:46:10.88#ibcon#flushed, iclass 38, count 0 2006.203.07:46:10.88#ibcon#about to write, iclass 38, count 0 2006.203.07:46:10.88#ibcon#wrote, iclass 38, count 0 2006.203.07:46:10.88#ibcon#about to read 3, iclass 38, count 0 2006.203.07:46:10.92#ibcon#read 3, iclass 38, count 0 2006.203.07:46:10.92#ibcon#about to read 4, iclass 38, count 0 2006.203.07:46:10.92#ibcon#read 4, iclass 38, count 0 2006.203.07:46:10.92#ibcon#about to read 5, iclass 38, count 0 2006.203.07:46:10.92#ibcon#read 5, iclass 38, count 0 2006.203.07:46:10.92#ibcon#about to read 6, iclass 38, count 0 2006.203.07:46:10.92#ibcon#read 6, iclass 38, count 0 2006.203.07:46:10.92#ibcon#end of sib2, iclass 38, count 0 2006.203.07:46:10.92#ibcon#*after write, iclass 38, count 0 2006.203.07:46:10.92#ibcon#*before return 0, iclass 38, count 0 2006.203.07:46:10.92#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.203.07:46:10.92#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.203.07:46:10.92#ibcon#about to clear, iclass 38 cls_cnt 0 2006.203.07:46:10.92#ibcon#cleared, iclass 38 cls_cnt 0 2006.203.07:46:10.92$vc4f8/va=7,7 2006.203.07:46:10.92#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.203.07:46:10.92#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.203.07:46:10.92#ibcon#ireg 11 cls_cnt 2 2006.203.07:46:10.92#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.203.07:46:10.99#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.203.07:46:10.99#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.203.07:46:10.99#ibcon#enter wrdev, iclass 40, count 2 2006.203.07:46:10.99#ibcon#first serial, iclass 40, count 2 2006.203.07:46:10.99#ibcon#enter sib2, iclass 40, count 2 2006.203.07:46:10.99#ibcon#flushed, iclass 40, count 2 2006.203.07:46:10.99#ibcon#about to write, iclass 40, count 2 2006.203.07:46:10.99#ibcon#wrote, iclass 40, count 2 2006.203.07:46:10.99#ibcon#about to read 3, iclass 40, count 2 2006.203.07:46:11.00#ibcon#read 3, iclass 40, count 2 2006.203.07:46:11.00#ibcon#about to read 4, iclass 40, count 2 2006.203.07:46:11.00#ibcon#read 4, iclass 40, count 2 2006.203.07:46:11.00#ibcon#about to read 5, iclass 40, count 2 2006.203.07:46:11.00#ibcon#read 5, iclass 40, count 2 2006.203.07:46:11.00#ibcon#about to read 6, iclass 40, count 2 2006.203.07:46:11.00#ibcon#read 6, iclass 40, count 2 2006.203.07:46:11.00#ibcon#end of sib2, iclass 40, count 2 2006.203.07:46:11.00#ibcon#*mode == 0, iclass 40, count 2 2006.203.07:46:11.00#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.203.07:46:11.00#ibcon#[25=AT07-07\r\n] 2006.203.07:46:11.00#ibcon#*before write, iclass 40, count 2 2006.203.07:46:11.00#ibcon#enter sib2, iclass 40, count 2 2006.203.07:46:11.00#ibcon#flushed, iclass 40, count 2 2006.203.07:46:11.00#ibcon#about to write, iclass 40, count 2 2006.203.07:46:11.00#ibcon#wrote, iclass 40, count 2 2006.203.07:46:11.00#ibcon#about to read 3, iclass 40, count 2 2006.203.07:46:11.03#ibcon#read 3, iclass 40, count 2 2006.203.07:46:11.03#ibcon#about to read 4, iclass 40, count 2 2006.203.07:46:11.03#ibcon#read 4, iclass 40, count 2 2006.203.07:46:11.03#ibcon#about to read 5, iclass 40, count 2 2006.203.07:46:11.03#ibcon#read 5, iclass 40, count 2 2006.203.07:46:11.03#ibcon#about to read 6, iclass 40, count 2 2006.203.07:46:11.03#ibcon#read 6, iclass 40, count 2 2006.203.07:46:11.03#ibcon#end of sib2, iclass 40, count 2 2006.203.07:46:11.03#ibcon#*after write, iclass 40, count 2 2006.203.07:46:11.03#ibcon#*before return 0, iclass 40, count 2 2006.203.07:46:11.03#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.203.07:46:11.03#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.203.07:46:11.03#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.203.07:46:11.03#ibcon#ireg 7 cls_cnt 0 2006.203.07:46:11.03#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.203.07:46:11.15#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.203.07:46:11.15#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.203.07:46:11.15#ibcon#enter wrdev, iclass 40, count 0 2006.203.07:46:11.15#ibcon#first serial, iclass 40, count 0 2006.203.07:46:11.15#ibcon#enter sib2, iclass 40, count 0 2006.203.07:46:11.15#ibcon#flushed, iclass 40, count 0 2006.203.07:46:11.15#ibcon#about to write, iclass 40, count 0 2006.203.07:46:11.15#ibcon#wrote, iclass 40, count 0 2006.203.07:46:11.15#ibcon#about to read 3, iclass 40, count 0 2006.203.07:46:11.17#ibcon#read 3, iclass 40, count 0 2006.203.07:46:11.17#ibcon#about to read 4, iclass 40, count 0 2006.203.07:46:11.17#ibcon#read 4, iclass 40, count 0 2006.203.07:46:11.17#ibcon#about to read 5, iclass 40, count 0 2006.203.07:46:11.17#ibcon#read 5, iclass 40, count 0 2006.203.07:46:11.17#ibcon#about to read 6, iclass 40, count 0 2006.203.07:46:11.17#ibcon#read 6, iclass 40, count 0 2006.203.07:46:11.17#ibcon#end of sib2, iclass 40, count 0 2006.203.07:46:11.17#ibcon#*mode == 0, iclass 40, count 0 2006.203.07:46:11.17#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.203.07:46:11.17#ibcon#[25=USB\r\n] 2006.203.07:46:11.17#ibcon#*before write, iclass 40, count 0 2006.203.07:46:11.17#ibcon#enter sib2, iclass 40, count 0 2006.203.07:46:11.17#ibcon#flushed, iclass 40, count 0 2006.203.07:46:11.17#ibcon#about to write, iclass 40, count 0 2006.203.07:46:11.17#ibcon#wrote, iclass 40, count 0 2006.203.07:46:11.17#ibcon#about to read 3, iclass 40, count 0 2006.203.07:46:11.20#ibcon#read 3, iclass 40, count 0 2006.203.07:46:11.20#ibcon#about to read 4, iclass 40, count 0 2006.203.07:46:11.20#ibcon#read 4, iclass 40, count 0 2006.203.07:46:11.20#ibcon#about to read 5, iclass 40, count 0 2006.203.07:46:11.20#ibcon#read 5, iclass 40, count 0 2006.203.07:46:11.20#ibcon#about to read 6, iclass 40, count 0 2006.203.07:46:11.20#ibcon#read 6, iclass 40, count 0 2006.203.07:46:11.20#ibcon#end of sib2, iclass 40, count 0 2006.203.07:46:11.20#ibcon#*after write, iclass 40, count 0 2006.203.07:46:11.20#ibcon#*before return 0, iclass 40, count 0 2006.203.07:46:11.20#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.203.07:46:11.20#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.203.07:46:11.20#ibcon#about to clear, iclass 40 cls_cnt 0 2006.203.07:46:11.20#ibcon#cleared, iclass 40 cls_cnt 0 2006.203.07:46:11.21$vc4f8/valo=8,852.99 2006.203.07:46:11.21#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.203.07:46:11.21#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.203.07:46:11.21#ibcon#ireg 17 cls_cnt 0 2006.203.07:46:11.21#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.203.07:46:11.21#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.203.07:46:11.21#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.203.07:46:11.21#ibcon#enter wrdev, iclass 4, count 0 2006.203.07:46:11.21#ibcon#first serial, iclass 4, count 0 2006.203.07:46:11.21#ibcon#enter sib2, iclass 4, count 0 2006.203.07:46:11.21#ibcon#flushed, iclass 4, count 0 2006.203.07:46:11.21#ibcon#about to write, iclass 4, count 0 2006.203.07:46:11.21#ibcon#wrote, iclass 4, count 0 2006.203.07:46:11.21#ibcon#about to read 3, iclass 4, count 0 2006.203.07:46:11.22#ibcon#read 3, iclass 4, count 0 2006.203.07:46:11.22#ibcon#about to read 4, iclass 4, count 0 2006.203.07:46:11.22#ibcon#read 4, iclass 4, count 0 2006.203.07:46:11.22#ibcon#about to read 5, iclass 4, count 0 2006.203.07:46:11.22#ibcon#read 5, iclass 4, count 0 2006.203.07:46:11.22#ibcon#about to read 6, iclass 4, count 0 2006.203.07:46:11.22#ibcon#read 6, iclass 4, count 0 2006.203.07:46:11.22#ibcon#end of sib2, iclass 4, count 0 2006.203.07:46:11.22#ibcon#*mode == 0, iclass 4, count 0 2006.203.07:46:11.22#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.203.07:46:11.22#ibcon#[26=FRQ=08,852.99\r\n] 2006.203.07:46:11.22#ibcon#*before write, iclass 4, count 0 2006.203.07:46:11.22#ibcon#enter sib2, iclass 4, count 0 2006.203.07:46:11.22#ibcon#flushed, iclass 4, count 0 2006.203.07:46:11.22#ibcon#about to write, iclass 4, count 0 2006.203.07:46:11.22#ibcon#wrote, iclass 4, count 0 2006.203.07:46:11.22#ibcon#about to read 3, iclass 4, count 0 2006.203.07:46:11.26#ibcon#read 3, iclass 4, count 0 2006.203.07:46:11.26#ibcon#about to read 4, iclass 4, count 0 2006.203.07:46:11.26#ibcon#read 4, iclass 4, count 0 2006.203.07:46:11.26#ibcon#about to read 5, iclass 4, count 0 2006.203.07:46:11.26#ibcon#read 5, iclass 4, count 0 2006.203.07:46:11.26#ibcon#about to read 6, iclass 4, count 0 2006.203.07:46:11.26#ibcon#read 6, iclass 4, count 0 2006.203.07:46:11.26#ibcon#end of sib2, iclass 4, count 0 2006.203.07:46:11.26#ibcon#*after write, iclass 4, count 0 2006.203.07:46:11.26#ibcon#*before return 0, iclass 4, count 0 2006.203.07:46:11.26#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.203.07:46:11.26#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.203.07:46:11.26#ibcon#about to clear, iclass 4 cls_cnt 0 2006.203.07:46:11.26#ibcon#cleared, iclass 4 cls_cnt 0 2006.203.07:46:11.26$vc4f8/va=8,6 2006.203.07:46:11.26#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.203.07:46:11.26#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.203.07:46:11.26#ibcon#ireg 11 cls_cnt 2 2006.203.07:46:11.26#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.203.07:46:11.32#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.203.07:46:11.32#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.203.07:46:11.32#ibcon#enter wrdev, iclass 6, count 2 2006.203.07:46:11.32#ibcon#first serial, iclass 6, count 2 2006.203.07:46:11.32#ibcon#enter sib2, iclass 6, count 2 2006.203.07:46:11.32#ibcon#flushed, iclass 6, count 2 2006.203.07:46:11.32#ibcon#about to write, iclass 6, count 2 2006.203.07:46:11.32#ibcon#wrote, iclass 6, count 2 2006.203.07:46:11.32#ibcon#about to read 3, iclass 6, count 2 2006.203.07:46:11.34#ibcon#read 3, iclass 6, count 2 2006.203.07:46:11.34#ibcon#about to read 4, iclass 6, count 2 2006.203.07:46:11.34#ibcon#read 4, iclass 6, count 2 2006.203.07:46:11.34#ibcon#about to read 5, iclass 6, count 2 2006.203.07:46:11.34#ibcon#read 5, iclass 6, count 2 2006.203.07:46:11.34#ibcon#about to read 6, iclass 6, count 2 2006.203.07:46:11.34#ibcon#read 6, iclass 6, count 2 2006.203.07:46:11.34#ibcon#end of sib2, iclass 6, count 2 2006.203.07:46:11.34#ibcon#*mode == 0, iclass 6, count 2 2006.203.07:46:11.34#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.203.07:46:11.34#ibcon#[25=AT08-06\r\n] 2006.203.07:46:11.34#ibcon#*before write, iclass 6, count 2 2006.203.07:46:11.34#ibcon#enter sib2, iclass 6, count 2 2006.203.07:46:11.34#ibcon#flushed, iclass 6, count 2 2006.203.07:46:11.34#ibcon#about to write, iclass 6, count 2 2006.203.07:46:11.34#ibcon#wrote, iclass 6, count 2 2006.203.07:46:11.34#ibcon#about to read 3, iclass 6, count 2 2006.203.07:46:11.37#ibcon#read 3, iclass 6, count 2 2006.203.07:46:11.37#ibcon#about to read 4, iclass 6, count 2 2006.203.07:46:11.37#ibcon#read 4, iclass 6, count 2 2006.203.07:46:11.37#ibcon#about to read 5, iclass 6, count 2 2006.203.07:46:11.37#ibcon#read 5, iclass 6, count 2 2006.203.07:46:11.37#ibcon#about to read 6, iclass 6, count 2 2006.203.07:46:11.37#ibcon#read 6, iclass 6, count 2 2006.203.07:46:11.37#ibcon#end of sib2, iclass 6, count 2 2006.203.07:46:11.37#ibcon#*after write, iclass 6, count 2 2006.203.07:46:11.37#ibcon#*before return 0, iclass 6, count 2 2006.203.07:46:11.37#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.203.07:46:11.37#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.203.07:46:11.37#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.203.07:46:11.37#ibcon#ireg 7 cls_cnt 0 2006.203.07:46:11.37#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.203.07:46:11.49#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.203.07:46:11.49#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.203.07:46:11.49#ibcon#enter wrdev, iclass 6, count 0 2006.203.07:46:11.49#ibcon#first serial, iclass 6, count 0 2006.203.07:46:11.49#ibcon#enter sib2, iclass 6, count 0 2006.203.07:46:11.49#ibcon#flushed, iclass 6, count 0 2006.203.07:46:11.49#ibcon#about to write, iclass 6, count 0 2006.203.07:46:11.49#ibcon#wrote, iclass 6, count 0 2006.203.07:46:11.49#ibcon#about to read 3, iclass 6, count 0 2006.203.07:46:11.51#ibcon#read 3, iclass 6, count 0 2006.203.07:46:11.51#ibcon#about to read 4, iclass 6, count 0 2006.203.07:46:11.51#ibcon#read 4, iclass 6, count 0 2006.203.07:46:11.51#ibcon#about to read 5, iclass 6, count 0 2006.203.07:46:11.51#ibcon#read 5, iclass 6, count 0 2006.203.07:46:11.51#ibcon#about to read 6, iclass 6, count 0 2006.203.07:46:11.51#ibcon#read 6, iclass 6, count 0 2006.203.07:46:11.51#ibcon#end of sib2, iclass 6, count 0 2006.203.07:46:11.51#ibcon#*mode == 0, iclass 6, count 0 2006.203.07:46:11.51#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.203.07:46:11.51#ibcon#[25=USB\r\n] 2006.203.07:46:11.51#ibcon#*before write, iclass 6, count 0 2006.203.07:46:11.51#ibcon#enter sib2, iclass 6, count 0 2006.203.07:46:11.51#ibcon#flushed, iclass 6, count 0 2006.203.07:46:11.51#ibcon#about to write, iclass 6, count 0 2006.203.07:46:11.51#ibcon#wrote, iclass 6, count 0 2006.203.07:46:11.51#ibcon#about to read 3, iclass 6, count 0 2006.203.07:46:11.54#ibcon#read 3, iclass 6, count 0 2006.203.07:46:11.54#ibcon#about to read 4, iclass 6, count 0 2006.203.07:46:11.54#ibcon#read 4, iclass 6, count 0 2006.203.07:46:11.54#ibcon#about to read 5, iclass 6, count 0 2006.203.07:46:11.54#ibcon#read 5, iclass 6, count 0 2006.203.07:46:11.54#ibcon#about to read 6, iclass 6, count 0 2006.203.07:46:11.54#ibcon#read 6, iclass 6, count 0 2006.203.07:46:11.54#ibcon#end of sib2, iclass 6, count 0 2006.203.07:46:11.54#ibcon#*after write, iclass 6, count 0 2006.203.07:46:11.54#ibcon#*before return 0, iclass 6, count 0 2006.203.07:46:11.54#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.203.07:46:11.54#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.203.07:46:11.54#ibcon#about to clear, iclass 6 cls_cnt 0 2006.203.07:46:11.54#ibcon#cleared, iclass 6 cls_cnt 0 2006.203.07:46:11.54$vc4f8/vblo=1,632.99 2006.203.07:46:11.54#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.203.07:46:11.54#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.203.07:46:11.54#ibcon#ireg 17 cls_cnt 0 2006.203.07:46:11.54#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.203.07:46:11.54#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.203.07:46:11.54#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.203.07:46:11.54#ibcon#enter wrdev, iclass 10, count 0 2006.203.07:46:11.54#ibcon#first serial, iclass 10, count 0 2006.203.07:46:11.54#ibcon#enter sib2, iclass 10, count 0 2006.203.07:46:11.54#ibcon#flushed, iclass 10, count 0 2006.203.07:46:11.54#ibcon#about to write, iclass 10, count 0 2006.203.07:46:11.54#ibcon#wrote, iclass 10, count 0 2006.203.07:46:11.54#ibcon#about to read 3, iclass 10, count 0 2006.203.07:46:11.56#ibcon#read 3, iclass 10, count 0 2006.203.07:46:11.56#ibcon#about to read 4, iclass 10, count 0 2006.203.07:46:11.56#ibcon#read 4, iclass 10, count 0 2006.203.07:46:11.56#ibcon#about to read 5, iclass 10, count 0 2006.203.07:46:11.56#ibcon#read 5, iclass 10, count 0 2006.203.07:46:11.56#ibcon#about to read 6, iclass 10, count 0 2006.203.07:46:11.56#ibcon#read 6, iclass 10, count 0 2006.203.07:46:11.56#ibcon#end of sib2, iclass 10, count 0 2006.203.07:46:11.56#ibcon#*mode == 0, iclass 10, count 0 2006.203.07:46:11.56#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.203.07:46:11.56#ibcon#[28=FRQ=01,632.99\r\n] 2006.203.07:46:11.56#ibcon#*before write, iclass 10, count 0 2006.203.07:46:11.56#ibcon#enter sib2, iclass 10, count 0 2006.203.07:46:11.56#ibcon#flushed, iclass 10, count 0 2006.203.07:46:11.56#ibcon#about to write, iclass 10, count 0 2006.203.07:46:11.56#ibcon#wrote, iclass 10, count 0 2006.203.07:46:11.56#ibcon#about to read 3, iclass 10, count 0 2006.203.07:46:11.60#ibcon#read 3, iclass 10, count 0 2006.203.07:46:11.60#ibcon#about to read 4, iclass 10, count 0 2006.203.07:46:11.60#ibcon#read 4, iclass 10, count 0 2006.203.07:46:11.60#ibcon#about to read 5, iclass 10, count 0 2006.203.07:46:11.60#ibcon#read 5, iclass 10, count 0 2006.203.07:46:11.60#ibcon#about to read 6, iclass 10, count 0 2006.203.07:46:11.60#ibcon#read 6, iclass 10, count 0 2006.203.07:46:11.60#ibcon#end of sib2, iclass 10, count 0 2006.203.07:46:11.60#ibcon#*after write, iclass 10, count 0 2006.203.07:46:11.60#ibcon#*before return 0, iclass 10, count 0 2006.203.07:46:11.60#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.203.07:46:11.60#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.203.07:46:11.60#ibcon#about to clear, iclass 10 cls_cnt 0 2006.203.07:46:11.60#ibcon#cleared, iclass 10 cls_cnt 0 2006.203.07:46:11.60$vc4f8/vb=1,4 2006.203.07:46:11.60#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.203.07:46:11.60#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.203.07:46:11.60#ibcon#ireg 11 cls_cnt 2 2006.203.07:46:11.60#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.203.07:46:11.60#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.203.07:46:11.60#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.203.07:46:11.60#ibcon#enter wrdev, iclass 12, count 2 2006.203.07:46:11.60#ibcon#first serial, iclass 12, count 2 2006.203.07:46:11.60#ibcon#enter sib2, iclass 12, count 2 2006.203.07:46:11.60#ibcon#flushed, iclass 12, count 2 2006.203.07:46:11.60#ibcon#about to write, iclass 12, count 2 2006.203.07:46:11.60#ibcon#wrote, iclass 12, count 2 2006.203.07:46:11.60#ibcon#about to read 3, iclass 12, count 2 2006.203.07:46:11.62#ibcon#read 3, iclass 12, count 2 2006.203.07:46:11.62#ibcon#about to read 4, iclass 12, count 2 2006.203.07:46:11.62#ibcon#read 4, iclass 12, count 2 2006.203.07:46:11.62#ibcon#about to read 5, iclass 12, count 2 2006.203.07:46:11.62#ibcon#read 5, iclass 12, count 2 2006.203.07:46:11.62#ibcon#about to read 6, iclass 12, count 2 2006.203.07:46:11.62#ibcon#read 6, iclass 12, count 2 2006.203.07:46:11.62#ibcon#end of sib2, iclass 12, count 2 2006.203.07:46:11.62#ibcon#*mode == 0, iclass 12, count 2 2006.203.07:46:11.62#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.203.07:46:11.62#ibcon#[27=AT01-04\r\n] 2006.203.07:46:11.62#ibcon#*before write, iclass 12, count 2 2006.203.07:46:11.62#ibcon#enter sib2, iclass 12, count 2 2006.203.07:46:11.62#ibcon#flushed, iclass 12, count 2 2006.203.07:46:11.62#ibcon#about to write, iclass 12, count 2 2006.203.07:46:11.62#ibcon#wrote, iclass 12, count 2 2006.203.07:46:11.62#ibcon#about to read 3, iclass 12, count 2 2006.203.07:46:11.65#ibcon#read 3, iclass 12, count 2 2006.203.07:46:11.65#ibcon#about to read 4, iclass 12, count 2 2006.203.07:46:11.65#ibcon#read 4, iclass 12, count 2 2006.203.07:46:11.65#ibcon#about to read 5, iclass 12, count 2 2006.203.07:46:11.65#ibcon#read 5, iclass 12, count 2 2006.203.07:46:11.65#ibcon#about to read 6, iclass 12, count 2 2006.203.07:46:11.65#ibcon#read 6, iclass 12, count 2 2006.203.07:46:11.65#ibcon#end of sib2, iclass 12, count 2 2006.203.07:46:11.65#ibcon#*after write, iclass 12, count 2 2006.203.07:46:11.65#ibcon#*before return 0, iclass 12, count 2 2006.203.07:46:11.65#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.203.07:46:11.65#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.203.07:46:11.65#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.203.07:46:11.65#ibcon#ireg 7 cls_cnt 0 2006.203.07:46:11.65#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.203.07:46:11.78#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.203.07:46:11.78#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.203.07:46:11.78#ibcon#enter wrdev, iclass 12, count 0 2006.203.07:46:11.78#ibcon#first serial, iclass 12, count 0 2006.203.07:46:11.78#ibcon#enter sib2, iclass 12, count 0 2006.203.07:46:11.78#ibcon#flushed, iclass 12, count 0 2006.203.07:46:11.78#ibcon#about to write, iclass 12, count 0 2006.203.07:46:11.78#ibcon#wrote, iclass 12, count 0 2006.203.07:46:11.78#ibcon#about to read 3, iclass 12, count 0 2006.203.07:46:11.80#ibcon#read 3, iclass 12, count 0 2006.203.07:46:11.80#ibcon#about to read 4, iclass 12, count 0 2006.203.07:46:11.80#ibcon#read 4, iclass 12, count 0 2006.203.07:46:11.80#ibcon#about to read 5, iclass 12, count 0 2006.203.07:46:11.80#ibcon#read 5, iclass 12, count 0 2006.203.07:46:11.80#ibcon#about to read 6, iclass 12, count 0 2006.203.07:46:11.80#ibcon#read 6, iclass 12, count 0 2006.203.07:46:11.80#ibcon#end of sib2, iclass 12, count 0 2006.203.07:46:11.80#ibcon#*mode == 0, iclass 12, count 0 2006.203.07:46:11.80#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.203.07:46:11.80#ibcon#[27=USB\r\n] 2006.203.07:46:11.80#ibcon#*before write, iclass 12, count 0 2006.203.07:46:11.80#ibcon#enter sib2, iclass 12, count 0 2006.203.07:46:11.80#ibcon#flushed, iclass 12, count 0 2006.203.07:46:11.80#ibcon#about to write, iclass 12, count 0 2006.203.07:46:11.80#ibcon#wrote, iclass 12, count 0 2006.203.07:46:11.80#ibcon#about to read 3, iclass 12, count 0 2006.203.07:46:11.83#ibcon#read 3, iclass 12, count 0 2006.203.07:46:11.83#ibcon#about to read 4, iclass 12, count 0 2006.203.07:46:11.83#ibcon#read 4, iclass 12, count 0 2006.203.07:46:11.83#ibcon#about to read 5, iclass 12, count 0 2006.203.07:46:11.83#ibcon#read 5, iclass 12, count 0 2006.203.07:46:11.83#ibcon#about to read 6, iclass 12, count 0 2006.203.07:46:11.83#ibcon#read 6, iclass 12, count 0 2006.203.07:46:11.83#ibcon#end of sib2, iclass 12, count 0 2006.203.07:46:11.83#ibcon#*after write, iclass 12, count 0 2006.203.07:46:11.83#ibcon#*before return 0, iclass 12, count 0 2006.203.07:46:11.83#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.203.07:46:11.83#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.203.07:46:11.83#ibcon#about to clear, iclass 12 cls_cnt 0 2006.203.07:46:11.83#ibcon#cleared, iclass 12 cls_cnt 0 2006.203.07:46:11.83$vc4f8/vblo=2,640.99 2006.203.07:46:11.83#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.203.07:46:11.83#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.203.07:46:11.83#ibcon#ireg 17 cls_cnt 0 2006.203.07:46:11.83#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.203.07:46:11.83#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.203.07:46:11.83#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.203.07:46:11.83#ibcon#enter wrdev, iclass 14, count 0 2006.203.07:46:11.83#ibcon#first serial, iclass 14, count 0 2006.203.07:46:11.83#ibcon#enter sib2, iclass 14, count 0 2006.203.07:46:11.83#ibcon#flushed, iclass 14, count 0 2006.203.07:46:11.83#ibcon#about to write, iclass 14, count 0 2006.203.07:46:11.83#ibcon#wrote, iclass 14, count 0 2006.203.07:46:11.83#ibcon#about to read 3, iclass 14, count 0 2006.203.07:46:11.85#ibcon#read 3, iclass 14, count 0 2006.203.07:46:11.85#ibcon#about to read 4, iclass 14, count 0 2006.203.07:46:11.85#ibcon#read 4, iclass 14, count 0 2006.203.07:46:11.85#ibcon#about to read 5, iclass 14, count 0 2006.203.07:46:11.85#ibcon#read 5, iclass 14, count 0 2006.203.07:46:11.85#ibcon#about to read 6, iclass 14, count 0 2006.203.07:46:11.85#ibcon#read 6, iclass 14, count 0 2006.203.07:46:11.85#ibcon#end of sib2, iclass 14, count 0 2006.203.07:46:11.85#ibcon#*mode == 0, iclass 14, count 0 2006.203.07:46:11.85#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.203.07:46:11.85#ibcon#[28=FRQ=02,640.99\r\n] 2006.203.07:46:11.85#ibcon#*before write, iclass 14, count 0 2006.203.07:46:11.85#ibcon#enter sib2, iclass 14, count 0 2006.203.07:46:11.85#ibcon#flushed, iclass 14, count 0 2006.203.07:46:11.85#ibcon#about to write, iclass 14, count 0 2006.203.07:46:11.85#ibcon#wrote, iclass 14, count 0 2006.203.07:46:11.85#ibcon#about to read 3, iclass 14, count 0 2006.203.07:46:11.89#ibcon#read 3, iclass 14, count 0 2006.203.07:46:11.89#ibcon#about to read 4, iclass 14, count 0 2006.203.07:46:11.89#ibcon#read 4, iclass 14, count 0 2006.203.07:46:11.89#ibcon#about to read 5, iclass 14, count 0 2006.203.07:46:11.89#ibcon#read 5, iclass 14, count 0 2006.203.07:46:11.89#ibcon#about to read 6, iclass 14, count 0 2006.203.07:46:11.89#ibcon#read 6, iclass 14, count 0 2006.203.07:46:11.89#ibcon#end of sib2, iclass 14, count 0 2006.203.07:46:11.89#ibcon#*after write, iclass 14, count 0 2006.203.07:46:11.89#ibcon#*before return 0, iclass 14, count 0 2006.203.07:46:11.89#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.203.07:46:11.89#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.203.07:46:11.89#ibcon#about to clear, iclass 14 cls_cnt 0 2006.203.07:46:11.89#ibcon#cleared, iclass 14 cls_cnt 0 2006.203.07:46:11.89$vc4f8/vb=2,4 2006.203.07:46:11.89#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.203.07:46:11.89#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.203.07:46:11.89#ibcon#ireg 11 cls_cnt 2 2006.203.07:46:11.89#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.203.07:46:11.95#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.203.07:46:11.95#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.203.07:46:11.95#ibcon#enter wrdev, iclass 16, count 2 2006.203.07:46:11.95#ibcon#first serial, iclass 16, count 2 2006.203.07:46:11.95#ibcon#enter sib2, iclass 16, count 2 2006.203.07:46:11.95#ibcon#flushed, iclass 16, count 2 2006.203.07:46:11.95#ibcon#about to write, iclass 16, count 2 2006.203.07:46:11.95#ibcon#wrote, iclass 16, count 2 2006.203.07:46:11.95#ibcon#about to read 3, iclass 16, count 2 2006.203.07:46:11.97#ibcon#read 3, iclass 16, count 2 2006.203.07:46:11.97#ibcon#about to read 4, iclass 16, count 2 2006.203.07:46:11.97#ibcon#read 4, iclass 16, count 2 2006.203.07:46:11.97#ibcon#about to read 5, iclass 16, count 2 2006.203.07:46:11.97#ibcon#read 5, iclass 16, count 2 2006.203.07:46:11.97#ibcon#about to read 6, iclass 16, count 2 2006.203.07:46:11.97#ibcon#read 6, iclass 16, count 2 2006.203.07:46:11.97#ibcon#end of sib2, iclass 16, count 2 2006.203.07:46:11.97#ibcon#*mode == 0, iclass 16, count 2 2006.203.07:46:11.97#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.203.07:46:11.97#ibcon#[27=AT02-04\r\n] 2006.203.07:46:11.97#ibcon#*before write, iclass 16, count 2 2006.203.07:46:11.97#ibcon#enter sib2, iclass 16, count 2 2006.203.07:46:11.97#ibcon#flushed, iclass 16, count 2 2006.203.07:46:11.97#ibcon#about to write, iclass 16, count 2 2006.203.07:46:11.97#ibcon#wrote, iclass 16, count 2 2006.203.07:46:11.97#ibcon#about to read 3, iclass 16, count 2 2006.203.07:46:12.00#ibcon#read 3, iclass 16, count 2 2006.203.07:46:12.00#ibcon#about to read 4, iclass 16, count 2 2006.203.07:46:12.00#ibcon#read 4, iclass 16, count 2 2006.203.07:46:12.00#ibcon#about to read 5, iclass 16, count 2 2006.203.07:46:12.00#ibcon#read 5, iclass 16, count 2 2006.203.07:46:12.00#ibcon#about to read 6, iclass 16, count 2 2006.203.07:46:12.00#ibcon#read 6, iclass 16, count 2 2006.203.07:46:12.00#ibcon#end of sib2, iclass 16, count 2 2006.203.07:46:12.00#ibcon#*after write, iclass 16, count 2 2006.203.07:46:12.00#ibcon#*before return 0, iclass 16, count 2 2006.203.07:46:12.00#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.203.07:46:12.00#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.203.07:46:12.00#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.203.07:46:12.00#ibcon#ireg 7 cls_cnt 0 2006.203.07:46:12.00#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.203.07:46:12.12#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.203.07:46:12.12#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.203.07:46:12.12#ibcon#enter wrdev, iclass 16, count 0 2006.203.07:46:12.12#ibcon#first serial, iclass 16, count 0 2006.203.07:46:12.12#ibcon#enter sib2, iclass 16, count 0 2006.203.07:46:12.12#ibcon#flushed, iclass 16, count 0 2006.203.07:46:12.12#ibcon#about to write, iclass 16, count 0 2006.203.07:46:12.12#ibcon#wrote, iclass 16, count 0 2006.203.07:46:12.12#ibcon#about to read 3, iclass 16, count 0 2006.203.07:46:12.14#ibcon#read 3, iclass 16, count 0 2006.203.07:46:12.14#ibcon#about to read 4, iclass 16, count 0 2006.203.07:46:12.14#ibcon#read 4, iclass 16, count 0 2006.203.07:46:12.14#ibcon#about to read 5, iclass 16, count 0 2006.203.07:46:12.14#ibcon#read 5, iclass 16, count 0 2006.203.07:46:12.14#ibcon#about to read 6, iclass 16, count 0 2006.203.07:46:12.14#ibcon#read 6, iclass 16, count 0 2006.203.07:46:12.14#ibcon#end of sib2, iclass 16, count 0 2006.203.07:46:12.14#ibcon#*mode == 0, iclass 16, count 0 2006.203.07:46:12.14#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.203.07:46:12.14#ibcon#[27=USB\r\n] 2006.203.07:46:12.14#ibcon#*before write, iclass 16, count 0 2006.203.07:46:12.14#ibcon#enter sib2, iclass 16, count 0 2006.203.07:46:12.14#ibcon#flushed, iclass 16, count 0 2006.203.07:46:12.14#ibcon#about to write, iclass 16, count 0 2006.203.07:46:12.14#ibcon#wrote, iclass 16, count 0 2006.203.07:46:12.14#ibcon#about to read 3, iclass 16, count 0 2006.203.07:46:12.17#ibcon#read 3, iclass 16, count 0 2006.203.07:46:12.17#ibcon#about to read 4, iclass 16, count 0 2006.203.07:46:12.17#ibcon#read 4, iclass 16, count 0 2006.203.07:46:12.17#ibcon#about to read 5, iclass 16, count 0 2006.203.07:46:12.17#ibcon#read 5, iclass 16, count 0 2006.203.07:46:12.17#ibcon#about to read 6, iclass 16, count 0 2006.203.07:46:12.17#ibcon#read 6, iclass 16, count 0 2006.203.07:46:12.17#ibcon#end of sib2, iclass 16, count 0 2006.203.07:46:12.17#ibcon#*after write, iclass 16, count 0 2006.203.07:46:12.17#ibcon#*before return 0, iclass 16, count 0 2006.203.07:46:12.17#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.203.07:46:12.17#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.203.07:46:12.17#ibcon#about to clear, iclass 16 cls_cnt 0 2006.203.07:46:12.17#ibcon#cleared, iclass 16 cls_cnt 0 2006.203.07:46:12.17$vc4f8/vblo=3,656.99 2006.203.07:46:12.17#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.203.07:46:12.17#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.203.07:46:12.17#ibcon#ireg 17 cls_cnt 0 2006.203.07:46:12.17#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.203.07:46:12.17#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.203.07:46:12.17#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.203.07:46:12.17#ibcon#enter wrdev, iclass 18, count 0 2006.203.07:46:12.17#ibcon#first serial, iclass 18, count 0 2006.203.07:46:12.17#ibcon#enter sib2, iclass 18, count 0 2006.203.07:46:12.17#ibcon#flushed, iclass 18, count 0 2006.203.07:46:12.17#ibcon#about to write, iclass 18, count 0 2006.203.07:46:12.17#ibcon#wrote, iclass 18, count 0 2006.203.07:46:12.17#ibcon#about to read 3, iclass 18, count 0 2006.203.07:46:12.19#ibcon#read 3, iclass 18, count 0 2006.203.07:46:12.19#ibcon#about to read 4, iclass 18, count 0 2006.203.07:46:12.19#ibcon#read 4, iclass 18, count 0 2006.203.07:46:12.19#ibcon#about to read 5, iclass 18, count 0 2006.203.07:46:12.19#ibcon#read 5, iclass 18, count 0 2006.203.07:46:12.19#ibcon#about to read 6, iclass 18, count 0 2006.203.07:46:12.19#ibcon#read 6, iclass 18, count 0 2006.203.07:46:12.19#ibcon#end of sib2, iclass 18, count 0 2006.203.07:46:12.19#ibcon#*mode == 0, iclass 18, count 0 2006.203.07:46:12.19#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.203.07:46:12.19#ibcon#[28=FRQ=03,656.99\r\n] 2006.203.07:46:12.19#ibcon#*before write, iclass 18, count 0 2006.203.07:46:12.19#ibcon#enter sib2, iclass 18, count 0 2006.203.07:46:12.19#ibcon#flushed, iclass 18, count 0 2006.203.07:46:12.19#ibcon#about to write, iclass 18, count 0 2006.203.07:46:12.19#ibcon#wrote, iclass 18, count 0 2006.203.07:46:12.19#ibcon#about to read 3, iclass 18, count 0 2006.203.07:46:12.23#ibcon#read 3, iclass 18, count 0 2006.203.07:46:12.23#ibcon#about to read 4, iclass 18, count 0 2006.203.07:46:12.23#ibcon#read 4, iclass 18, count 0 2006.203.07:46:12.23#ibcon#about to read 5, iclass 18, count 0 2006.203.07:46:12.23#ibcon#read 5, iclass 18, count 0 2006.203.07:46:12.23#ibcon#about to read 6, iclass 18, count 0 2006.203.07:46:12.23#ibcon#read 6, iclass 18, count 0 2006.203.07:46:12.23#ibcon#end of sib2, iclass 18, count 0 2006.203.07:46:12.23#ibcon#*after write, iclass 18, count 0 2006.203.07:46:12.23#ibcon#*before return 0, iclass 18, count 0 2006.203.07:46:12.23#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.203.07:46:12.23#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.203.07:46:12.23#ibcon#about to clear, iclass 18 cls_cnt 0 2006.203.07:46:12.23#ibcon#cleared, iclass 18 cls_cnt 0 2006.203.07:46:12.23$vc4f8/vb=3,4 2006.203.07:46:12.23#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.203.07:46:12.23#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.203.07:46:12.23#ibcon#ireg 11 cls_cnt 2 2006.203.07:46:12.23#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.203.07:46:12.29#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.203.07:46:12.29#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.203.07:46:12.29#ibcon#enter wrdev, iclass 20, count 2 2006.203.07:46:12.29#ibcon#first serial, iclass 20, count 2 2006.203.07:46:12.29#ibcon#enter sib2, iclass 20, count 2 2006.203.07:46:12.29#ibcon#flushed, iclass 20, count 2 2006.203.07:46:12.29#ibcon#about to write, iclass 20, count 2 2006.203.07:46:12.29#ibcon#wrote, iclass 20, count 2 2006.203.07:46:12.29#ibcon#about to read 3, iclass 20, count 2 2006.203.07:46:12.31#ibcon#read 3, iclass 20, count 2 2006.203.07:46:12.31#ibcon#about to read 4, iclass 20, count 2 2006.203.07:46:12.31#ibcon#read 4, iclass 20, count 2 2006.203.07:46:12.31#ibcon#about to read 5, iclass 20, count 2 2006.203.07:46:12.31#ibcon#read 5, iclass 20, count 2 2006.203.07:46:12.31#ibcon#about to read 6, iclass 20, count 2 2006.203.07:46:12.31#ibcon#read 6, iclass 20, count 2 2006.203.07:46:12.31#ibcon#end of sib2, iclass 20, count 2 2006.203.07:46:12.31#ibcon#*mode == 0, iclass 20, count 2 2006.203.07:46:12.31#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.203.07:46:12.31#ibcon#[27=AT03-04\r\n] 2006.203.07:46:12.31#ibcon#*before write, iclass 20, count 2 2006.203.07:46:12.31#ibcon#enter sib2, iclass 20, count 2 2006.203.07:46:12.31#ibcon#flushed, iclass 20, count 2 2006.203.07:46:12.31#ibcon#about to write, iclass 20, count 2 2006.203.07:46:12.31#ibcon#wrote, iclass 20, count 2 2006.203.07:46:12.31#ibcon#about to read 3, iclass 20, count 2 2006.203.07:46:12.34#ibcon#read 3, iclass 20, count 2 2006.203.07:46:12.34#ibcon#about to read 4, iclass 20, count 2 2006.203.07:46:12.34#ibcon#read 4, iclass 20, count 2 2006.203.07:46:12.34#ibcon#about to read 5, iclass 20, count 2 2006.203.07:46:12.34#ibcon#read 5, iclass 20, count 2 2006.203.07:46:12.34#ibcon#about to read 6, iclass 20, count 2 2006.203.07:46:12.34#ibcon#read 6, iclass 20, count 2 2006.203.07:46:12.34#ibcon#end of sib2, iclass 20, count 2 2006.203.07:46:12.34#ibcon#*after write, iclass 20, count 2 2006.203.07:46:12.34#ibcon#*before return 0, iclass 20, count 2 2006.203.07:46:12.34#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.203.07:46:12.34#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.203.07:46:12.34#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.203.07:46:12.34#ibcon#ireg 7 cls_cnt 0 2006.203.07:46:12.34#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.203.07:46:12.46#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.203.07:46:12.46#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.203.07:46:12.46#ibcon#enter wrdev, iclass 20, count 0 2006.203.07:46:12.46#ibcon#first serial, iclass 20, count 0 2006.203.07:46:12.46#ibcon#enter sib2, iclass 20, count 0 2006.203.07:46:12.46#ibcon#flushed, iclass 20, count 0 2006.203.07:46:12.46#ibcon#about to write, iclass 20, count 0 2006.203.07:46:12.46#ibcon#wrote, iclass 20, count 0 2006.203.07:46:12.46#ibcon#about to read 3, iclass 20, count 0 2006.203.07:46:12.48#ibcon#read 3, iclass 20, count 0 2006.203.07:46:12.48#ibcon#about to read 4, iclass 20, count 0 2006.203.07:46:12.48#ibcon#read 4, iclass 20, count 0 2006.203.07:46:12.48#ibcon#about to read 5, iclass 20, count 0 2006.203.07:46:12.48#ibcon#read 5, iclass 20, count 0 2006.203.07:46:12.48#ibcon#about to read 6, iclass 20, count 0 2006.203.07:46:12.48#ibcon#read 6, iclass 20, count 0 2006.203.07:46:12.48#ibcon#end of sib2, iclass 20, count 0 2006.203.07:46:12.48#ibcon#*mode == 0, iclass 20, count 0 2006.203.07:46:12.48#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.203.07:46:12.48#ibcon#[27=USB\r\n] 2006.203.07:46:12.48#ibcon#*before write, iclass 20, count 0 2006.203.07:46:12.48#ibcon#enter sib2, iclass 20, count 0 2006.203.07:46:12.48#ibcon#flushed, iclass 20, count 0 2006.203.07:46:12.48#ibcon#about to write, iclass 20, count 0 2006.203.07:46:12.48#ibcon#wrote, iclass 20, count 0 2006.203.07:46:12.48#ibcon#about to read 3, iclass 20, count 0 2006.203.07:46:12.51#ibcon#read 3, iclass 20, count 0 2006.203.07:46:12.51#ibcon#about to read 4, iclass 20, count 0 2006.203.07:46:12.51#ibcon#read 4, iclass 20, count 0 2006.203.07:46:12.51#ibcon#about to read 5, iclass 20, count 0 2006.203.07:46:12.51#ibcon#read 5, iclass 20, count 0 2006.203.07:46:12.51#ibcon#about to read 6, iclass 20, count 0 2006.203.07:46:12.51#ibcon#read 6, iclass 20, count 0 2006.203.07:46:12.51#ibcon#end of sib2, iclass 20, count 0 2006.203.07:46:12.51#ibcon#*after write, iclass 20, count 0 2006.203.07:46:12.51#ibcon#*before return 0, iclass 20, count 0 2006.203.07:46:12.51#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.203.07:46:12.51#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.203.07:46:12.51#ibcon#about to clear, iclass 20 cls_cnt 0 2006.203.07:46:12.51#ibcon#cleared, iclass 20 cls_cnt 0 2006.203.07:46:12.51$vc4f8/vblo=4,712.99 2006.203.07:46:12.51#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.203.07:46:12.51#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.203.07:46:12.51#ibcon#ireg 17 cls_cnt 0 2006.203.07:46:12.51#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.203.07:46:12.51#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.203.07:46:12.51#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.203.07:46:12.51#ibcon#enter wrdev, iclass 22, count 0 2006.203.07:46:12.51#ibcon#first serial, iclass 22, count 0 2006.203.07:46:12.51#ibcon#enter sib2, iclass 22, count 0 2006.203.07:46:12.51#ibcon#flushed, iclass 22, count 0 2006.203.07:46:12.51#ibcon#about to write, iclass 22, count 0 2006.203.07:46:12.51#ibcon#wrote, iclass 22, count 0 2006.203.07:46:12.51#ibcon#about to read 3, iclass 22, count 0 2006.203.07:46:12.53#ibcon#read 3, iclass 22, count 0 2006.203.07:46:12.53#ibcon#about to read 4, iclass 22, count 0 2006.203.07:46:12.53#ibcon#read 4, iclass 22, count 0 2006.203.07:46:12.53#ibcon#about to read 5, iclass 22, count 0 2006.203.07:46:12.53#ibcon#read 5, iclass 22, count 0 2006.203.07:46:12.53#ibcon#about to read 6, iclass 22, count 0 2006.203.07:46:12.53#ibcon#read 6, iclass 22, count 0 2006.203.07:46:12.53#ibcon#end of sib2, iclass 22, count 0 2006.203.07:46:12.53#ibcon#*mode == 0, iclass 22, count 0 2006.203.07:46:12.53#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.203.07:46:12.53#ibcon#[28=FRQ=04,712.99\r\n] 2006.203.07:46:12.53#ibcon#*before write, iclass 22, count 0 2006.203.07:46:12.53#ibcon#enter sib2, iclass 22, count 0 2006.203.07:46:12.53#ibcon#flushed, iclass 22, count 0 2006.203.07:46:12.53#ibcon#about to write, iclass 22, count 0 2006.203.07:46:12.53#ibcon#wrote, iclass 22, count 0 2006.203.07:46:12.53#ibcon#about to read 3, iclass 22, count 0 2006.203.07:46:12.57#ibcon#read 3, iclass 22, count 0 2006.203.07:46:12.57#ibcon#about to read 4, iclass 22, count 0 2006.203.07:46:12.57#ibcon#read 4, iclass 22, count 0 2006.203.07:46:12.57#ibcon#about to read 5, iclass 22, count 0 2006.203.07:46:12.57#ibcon#read 5, iclass 22, count 0 2006.203.07:46:12.57#ibcon#about to read 6, iclass 22, count 0 2006.203.07:46:12.57#ibcon#read 6, iclass 22, count 0 2006.203.07:46:12.57#ibcon#end of sib2, iclass 22, count 0 2006.203.07:46:12.57#ibcon#*after write, iclass 22, count 0 2006.203.07:46:12.57#ibcon#*before return 0, iclass 22, count 0 2006.203.07:46:12.57#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.203.07:46:12.57#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.203.07:46:12.57#ibcon#about to clear, iclass 22 cls_cnt 0 2006.203.07:46:12.57#ibcon#cleared, iclass 22 cls_cnt 0 2006.203.07:46:12.57$vc4f8/vb=4,4 2006.203.07:46:12.57#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.203.07:46:12.57#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.203.07:46:12.57#ibcon#ireg 11 cls_cnt 2 2006.203.07:46:12.57#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.203.07:46:12.64#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.203.07:46:12.64#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.203.07:46:12.64#ibcon#enter wrdev, iclass 24, count 2 2006.203.07:46:12.64#ibcon#first serial, iclass 24, count 2 2006.203.07:46:12.64#ibcon#enter sib2, iclass 24, count 2 2006.203.07:46:12.64#ibcon#flushed, iclass 24, count 2 2006.203.07:46:12.64#ibcon#about to write, iclass 24, count 2 2006.203.07:46:12.64#ibcon#wrote, iclass 24, count 2 2006.203.07:46:12.64#ibcon#about to read 3, iclass 24, count 2 2006.203.07:46:12.65#ibcon#read 3, iclass 24, count 2 2006.203.07:46:12.65#ibcon#about to read 4, iclass 24, count 2 2006.203.07:46:12.65#ibcon#read 4, iclass 24, count 2 2006.203.07:46:12.65#ibcon#about to read 5, iclass 24, count 2 2006.203.07:46:12.65#ibcon#read 5, iclass 24, count 2 2006.203.07:46:12.65#ibcon#about to read 6, iclass 24, count 2 2006.203.07:46:12.65#ibcon#read 6, iclass 24, count 2 2006.203.07:46:12.65#ibcon#end of sib2, iclass 24, count 2 2006.203.07:46:12.65#ibcon#*mode == 0, iclass 24, count 2 2006.203.07:46:12.65#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.203.07:46:12.65#ibcon#[27=AT04-04\r\n] 2006.203.07:46:12.65#ibcon#*before write, iclass 24, count 2 2006.203.07:46:12.65#ibcon#enter sib2, iclass 24, count 2 2006.203.07:46:12.65#ibcon#flushed, iclass 24, count 2 2006.203.07:46:12.65#ibcon#about to write, iclass 24, count 2 2006.203.07:46:12.65#ibcon#wrote, iclass 24, count 2 2006.203.07:46:12.65#ibcon#about to read 3, iclass 24, count 2 2006.203.07:46:12.68#ibcon#read 3, iclass 24, count 2 2006.203.07:46:12.68#ibcon#about to read 4, iclass 24, count 2 2006.203.07:46:12.68#ibcon#read 4, iclass 24, count 2 2006.203.07:46:12.68#ibcon#about to read 5, iclass 24, count 2 2006.203.07:46:12.68#ibcon#read 5, iclass 24, count 2 2006.203.07:46:12.68#ibcon#about to read 6, iclass 24, count 2 2006.203.07:46:12.68#ibcon#read 6, iclass 24, count 2 2006.203.07:46:12.68#ibcon#end of sib2, iclass 24, count 2 2006.203.07:46:12.68#ibcon#*after write, iclass 24, count 2 2006.203.07:46:12.68#ibcon#*before return 0, iclass 24, count 2 2006.203.07:46:12.68#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.203.07:46:12.68#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.203.07:46:12.68#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.203.07:46:12.68#ibcon#ireg 7 cls_cnt 0 2006.203.07:46:12.68#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.203.07:46:12.80#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.203.07:46:12.80#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.203.07:46:12.80#ibcon#enter wrdev, iclass 24, count 0 2006.203.07:46:12.80#ibcon#first serial, iclass 24, count 0 2006.203.07:46:12.80#ibcon#enter sib2, iclass 24, count 0 2006.203.07:46:12.80#ibcon#flushed, iclass 24, count 0 2006.203.07:46:12.80#ibcon#about to write, iclass 24, count 0 2006.203.07:46:12.80#ibcon#wrote, iclass 24, count 0 2006.203.07:46:12.80#ibcon#about to read 3, iclass 24, count 0 2006.203.07:46:12.82#ibcon#read 3, iclass 24, count 0 2006.203.07:46:12.82#ibcon#about to read 4, iclass 24, count 0 2006.203.07:46:12.82#ibcon#read 4, iclass 24, count 0 2006.203.07:46:12.82#ibcon#about to read 5, iclass 24, count 0 2006.203.07:46:12.82#ibcon#read 5, iclass 24, count 0 2006.203.07:46:12.82#ibcon#about to read 6, iclass 24, count 0 2006.203.07:46:12.82#ibcon#read 6, iclass 24, count 0 2006.203.07:46:12.82#ibcon#end of sib2, iclass 24, count 0 2006.203.07:46:12.82#ibcon#*mode == 0, iclass 24, count 0 2006.203.07:46:12.82#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.203.07:46:12.82#ibcon#[27=USB\r\n] 2006.203.07:46:12.82#ibcon#*before write, iclass 24, count 0 2006.203.07:46:12.82#ibcon#enter sib2, iclass 24, count 0 2006.203.07:46:12.82#ibcon#flushed, iclass 24, count 0 2006.203.07:46:12.82#ibcon#about to write, iclass 24, count 0 2006.203.07:46:12.82#ibcon#wrote, iclass 24, count 0 2006.203.07:46:12.82#ibcon#about to read 3, iclass 24, count 0 2006.203.07:46:12.85#ibcon#read 3, iclass 24, count 0 2006.203.07:46:12.85#ibcon#about to read 4, iclass 24, count 0 2006.203.07:46:12.85#ibcon#read 4, iclass 24, count 0 2006.203.07:46:12.85#ibcon#about to read 5, iclass 24, count 0 2006.203.07:46:12.85#ibcon#read 5, iclass 24, count 0 2006.203.07:46:12.85#ibcon#about to read 6, iclass 24, count 0 2006.203.07:46:12.85#ibcon#read 6, iclass 24, count 0 2006.203.07:46:12.85#ibcon#end of sib2, iclass 24, count 0 2006.203.07:46:12.85#ibcon#*after write, iclass 24, count 0 2006.203.07:46:12.85#ibcon#*before return 0, iclass 24, count 0 2006.203.07:46:12.85#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.203.07:46:12.85#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.203.07:46:12.85#ibcon#about to clear, iclass 24 cls_cnt 0 2006.203.07:46:12.85#ibcon#cleared, iclass 24 cls_cnt 0 2006.203.07:46:12.85$vc4f8/vblo=5,744.99 2006.203.07:46:12.85#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.203.07:46:12.85#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.203.07:46:12.85#ibcon#ireg 17 cls_cnt 0 2006.203.07:46:12.85#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:46:12.85#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:46:12.85#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:46:12.85#ibcon#enter wrdev, iclass 27, count 0 2006.203.07:46:12.85#ibcon#first serial, iclass 27, count 0 2006.203.07:46:12.85#ibcon#enter sib2, iclass 27, count 0 2006.203.07:46:12.85#ibcon#flushed, iclass 27, count 0 2006.203.07:46:12.85#ibcon#about to write, iclass 27, count 0 2006.203.07:46:12.85#ibcon#wrote, iclass 27, count 0 2006.203.07:46:12.85#ibcon#about to read 3, iclass 27, count 0 2006.203.07:46:12.86#abcon#<5=/05 1.7 2.9 23.88 981001.2\r\n> 2006.203.07:46:12.87#ibcon#read 3, iclass 27, count 0 2006.203.07:46:12.87#ibcon#about to read 4, iclass 27, count 0 2006.203.07:46:12.87#ibcon#read 4, iclass 27, count 0 2006.203.07:46:12.87#ibcon#about to read 5, iclass 27, count 0 2006.203.07:46:12.87#ibcon#read 5, iclass 27, count 0 2006.203.07:46:12.87#ibcon#about to read 6, iclass 27, count 0 2006.203.07:46:12.87#ibcon#read 6, iclass 27, count 0 2006.203.07:46:12.87#ibcon#end of sib2, iclass 27, count 0 2006.203.07:46:12.87#ibcon#*mode == 0, iclass 27, count 0 2006.203.07:46:12.87#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.203.07:46:12.87#ibcon#[28=FRQ=05,744.99\r\n] 2006.203.07:46:12.87#ibcon#*before write, iclass 27, count 0 2006.203.07:46:12.87#ibcon#enter sib2, iclass 27, count 0 2006.203.07:46:12.87#ibcon#flushed, iclass 27, count 0 2006.203.07:46:12.87#ibcon#about to write, iclass 27, count 0 2006.203.07:46:12.87#ibcon#wrote, iclass 27, count 0 2006.203.07:46:12.87#ibcon#about to read 3, iclass 27, count 0 2006.203.07:46:12.88#abcon#{5=INTERFACE CLEAR} 2006.203.07:46:12.91#ibcon#read 3, iclass 27, count 0 2006.203.07:46:12.91#ibcon#about to read 4, iclass 27, count 0 2006.203.07:46:12.91#ibcon#read 4, iclass 27, count 0 2006.203.07:46:12.91#ibcon#about to read 5, iclass 27, count 0 2006.203.07:46:12.91#ibcon#read 5, iclass 27, count 0 2006.203.07:46:12.91#ibcon#about to read 6, iclass 27, count 0 2006.203.07:46:12.91#ibcon#read 6, iclass 27, count 0 2006.203.07:46:12.91#ibcon#end of sib2, iclass 27, count 0 2006.203.07:46:12.91#ibcon#*after write, iclass 27, count 0 2006.203.07:46:12.91#ibcon#*before return 0, iclass 27, count 0 2006.203.07:46:12.91#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:46:12.91#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:46:12.91#ibcon#about to clear, iclass 27 cls_cnt 0 2006.203.07:46:12.91#ibcon#cleared, iclass 27 cls_cnt 0 2006.203.07:46:12.91$vc4f8/vb=5,3 2006.203.07:46:12.91#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.203.07:46:12.91#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.203.07:46:12.91#ibcon#ireg 11 cls_cnt 2 2006.203.07:46:12.91#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.203.07:46:12.94#abcon#[5=S1D000X0/0*\r\n] 2006.203.07:46:12.97#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.203.07:46:12.97#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.203.07:46:12.97#ibcon#enter wrdev, iclass 31, count 2 2006.203.07:46:12.97#ibcon#first serial, iclass 31, count 2 2006.203.07:46:12.97#ibcon#enter sib2, iclass 31, count 2 2006.203.07:46:12.97#ibcon#flushed, iclass 31, count 2 2006.203.07:46:12.97#ibcon#about to write, iclass 31, count 2 2006.203.07:46:12.97#ibcon#wrote, iclass 31, count 2 2006.203.07:46:12.97#ibcon#about to read 3, iclass 31, count 2 2006.203.07:46:12.99#ibcon#read 3, iclass 31, count 2 2006.203.07:46:12.99#ibcon#about to read 4, iclass 31, count 2 2006.203.07:46:12.99#ibcon#read 4, iclass 31, count 2 2006.203.07:46:12.99#ibcon#about to read 5, iclass 31, count 2 2006.203.07:46:12.99#ibcon#read 5, iclass 31, count 2 2006.203.07:46:12.99#ibcon#about to read 6, iclass 31, count 2 2006.203.07:46:12.99#ibcon#read 6, iclass 31, count 2 2006.203.07:46:12.99#ibcon#end of sib2, iclass 31, count 2 2006.203.07:46:12.99#ibcon#*mode == 0, iclass 31, count 2 2006.203.07:46:12.99#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.203.07:46:12.99#ibcon#[27=AT05-03\r\n] 2006.203.07:46:12.99#ibcon#*before write, iclass 31, count 2 2006.203.07:46:12.99#ibcon#enter sib2, iclass 31, count 2 2006.203.07:46:12.99#ibcon#flushed, iclass 31, count 2 2006.203.07:46:12.99#ibcon#about to write, iclass 31, count 2 2006.203.07:46:12.99#ibcon#wrote, iclass 31, count 2 2006.203.07:46:12.99#ibcon#about to read 3, iclass 31, count 2 2006.203.07:46:13.02#ibcon#read 3, iclass 31, count 2 2006.203.07:46:13.02#ibcon#about to read 4, iclass 31, count 2 2006.203.07:46:13.02#ibcon#read 4, iclass 31, count 2 2006.203.07:46:13.02#ibcon#about to read 5, iclass 31, count 2 2006.203.07:46:13.02#ibcon#read 5, iclass 31, count 2 2006.203.07:46:13.02#ibcon#about to read 6, iclass 31, count 2 2006.203.07:46:13.02#ibcon#read 6, iclass 31, count 2 2006.203.07:46:13.02#ibcon#end of sib2, iclass 31, count 2 2006.203.07:46:13.02#ibcon#*after write, iclass 31, count 2 2006.203.07:46:13.02#ibcon#*before return 0, iclass 31, count 2 2006.203.07:46:13.02#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.203.07:46:13.02#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.203.07:46:13.02#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.203.07:46:13.02#ibcon#ireg 7 cls_cnt 0 2006.203.07:46:13.02#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.203.07:46:13.14#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.203.07:46:13.14#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.203.07:46:13.14#ibcon#enter wrdev, iclass 31, count 0 2006.203.07:46:13.14#ibcon#first serial, iclass 31, count 0 2006.203.07:46:13.14#ibcon#enter sib2, iclass 31, count 0 2006.203.07:46:13.14#ibcon#flushed, iclass 31, count 0 2006.203.07:46:13.14#ibcon#about to write, iclass 31, count 0 2006.203.07:46:13.14#ibcon#wrote, iclass 31, count 0 2006.203.07:46:13.14#ibcon#about to read 3, iclass 31, count 0 2006.203.07:46:13.16#ibcon#read 3, iclass 31, count 0 2006.203.07:46:13.16#ibcon#about to read 4, iclass 31, count 0 2006.203.07:46:13.16#ibcon#read 4, iclass 31, count 0 2006.203.07:46:13.16#ibcon#about to read 5, iclass 31, count 0 2006.203.07:46:13.16#ibcon#read 5, iclass 31, count 0 2006.203.07:46:13.16#ibcon#about to read 6, iclass 31, count 0 2006.203.07:46:13.16#ibcon#read 6, iclass 31, count 0 2006.203.07:46:13.16#ibcon#end of sib2, iclass 31, count 0 2006.203.07:46:13.16#ibcon#*mode == 0, iclass 31, count 0 2006.203.07:46:13.16#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.203.07:46:13.16#ibcon#[27=USB\r\n] 2006.203.07:46:13.16#ibcon#*before write, iclass 31, count 0 2006.203.07:46:13.16#ibcon#enter sib2, iclass 31, count 0 2006.203.07:46:13.16#ibcon#flushed, iclass 31, count 0 2006.203.07:46:13.16#ibcon#about to write, iclass 31, count 0 2006.203.07:46:13.16#ibcon#wrote, iclass 31, count 0 2006.203.07:46:13.16#ibcon#about to read 3, iclass 31, count 0 2006.203.07:46:13.19#ibcon#read 3, iclass 31, count 0 2006.203.07:46:13.19#ibcon#about to read 4, iclass 31, count 0 2006.203.07:46:13.19#ibcon#read 4, iclass 31, count 0 2006.203.07:46:13.19#ibcon#about to read 5, iclass 31, count 0 2006.203.07:46:13.19#ibcon#read 5, iclass 31, count 0 2006.203.07:46:13.19#ibcon#about to read 6, iclass 31, count 0 2006.203.07:46:13.19#ibcon#read 6, iclass 31, count 0 2006.203.07:46:13.19#ibcon#end of sib2, iclass 31, count 0 2006.203.07:46:13.19#ibcon#*after write, iclass 31, count 0 2006.203.07:46:13.19#ibcon#*before return 0, iclass 31, count 0 2006.203.07:46:13.19#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.203.07:46:13.19#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.203.07:46:13.19#ibcon#about to clear, iclass 31 cls_cnt 0 2006.203.07:46:13.19#ibcon#cleared, iclass 31 cls_cnt 0 2006.203.07:46:13.19$vc4f8/vblo=6,752.99 2006.203.07:46:13.19#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.203.07:46:13.19#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.203.07:46:13.19#ibcon#ireg 17 cls_cnt 0 2006.203.07:46:13.19#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.203.07:46:13.19#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.203.07:46:13.19#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.203.07:46:13.19#ibcon#enter wrdev, iclass 34, count 0 2006.203.07:46:13.19#ibcon#first serial, iclass 34, count 0 2006.203.07:46:13.19#ibcon#enter sib2, iclass 34, count 0 2006.203.07:46:13.19#ibcon#flushed, iclass 34, count 0 2006.203.07:46:13.19#ibcon#about to write, iclass 34, count 0 2006.203.07:46:13.19#ibcon#wrote, iclass 34, count 0 2006.203.07:46:13.19#ibcon#about to read 3, iclass 34, count 0 2006.203.07:46:13.22#ibcon#read 3, iclass 34, count 0 2006.203.07:46:13.22#ibcon#about to read 4, iclass 34, count 0 2006.203.07:46:13.22#ibcon#read 4, iclass 34, count 0 2006.203.07:46:13.22#ibcon#about to read 5, iclass 34, count 0 2006.203.07:46:13.22#ibcon#read 5, iclass 34, count 0 2006.203.07:46:13.22#ibcon#about to read 6, iclass 34, count 0 2006.203.07:46:13.22#ibcon#read 6, iclass 34, count 0 2006.203.07:46:13.22#ibcon#end of sib2, iclass 34, count 0 2006.203.07:46:13.22#ibcon#*mode == 0, iclass 34, count 0 2006.203.07:46:13.22#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.203.07:46:13.22#ibcon#[28=FRQ=06,752.99\r\n] 2006.203.07:46:13.22#ibcon#*before write, iclass 34, count 0 2006.203.07:46:13.22#ibcon#enter sib2, iclass 34, count 0 2006.203.07:46:13.22#ibcon#flushed, iclass 34, count 0 2006.203.07:46:13.22#ibcon#about to write, iclass 34, count 0 2006.203.07:46:13.22#ibcon#wrote, iclass 34, count 0 2006.203.07:46:13.22#ibcon#about to read 3, iclass 34, count 0 2006.203.07:46:13.26#ibcon#read 3, iclass 34, count 0 2006.203.07:46:13.26#ibcon#about to read 4, iclass 34, count 0 2006.203.07:46:13.26#ibcon#read 4, iclass 34, count 0 2006.203.07:46:13.26#ibcon#about to read 5, iclass 34, count 0 2006.203.07:46:13.26#ibcon#read 5, iclass 34, count 0 2006.203.07:46:13.26#ibcon#about to read 6, iclass 34, count 0 2006.203.07:46:13.26#ibcon#read 6, iclass 34, count 0 2006.203.07:46:13.26#ibcon#end of sib2, iclass 34, count 0 2006.203.07:46:13.26#ibcon#*after write, iclass 34, count 0 2006.203.07:46:13.26#ibcon#*before return 0, iclass 34, count 0 2006.203.07:46:13.26#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.203.07:46:13.26#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.203.07:46:13.26#ibcon#about to clear, iclass 34 cls_cnt 0 2006.203.07:46:13.26#ibcon#cleared, iclass 34 cls_cnt 0 2006.203.07:46:13.26$vc4f8/vb=6,4 2006.203.07:46:13.26#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.203.07:46:13.26#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.203.07:46:13.26#ibcon#ireg 11 cls_cnt 2 2006.203.07:46:13.26#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.203.07:46:13.31#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.203.07:46:13.31#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.203.07:46:13.31#ibcon#enter wrdev, iclass 36, count 2 2006.203.07:46:13.31#ibcon#first serial, iclass 36, count 2 2006.203.07:46:13.31#ibcon#enter sib2, iclass 36, count 2 2006.203.07:46:13.31#ibcon#flushed, iclass 36, count 2 2006.203.07:46:13.31#ibcon#about to write, iclass 36, count 2 2006.203.07:46:13.31#ibcon#wrote, iclass 36, count 2 2006.203.07:46:13.31#ibcon#about to read 3, iclass 36, count 2 2006.203.07:46:13.33#ibcon#read 3, iclass 36, count 2 2006.203.07:46:13.33#ibcon#about to read 4, iclass 36, count 2 2006.203.07:46:13.33#ibcon#read 4, iclass 36, count 2 2006.203.07:46:13.33#ibcon#about to read 5, iclass 36, count 2 2006.203.07:46:13.33#ibcon#read 5, iclass 36, count 2 2006.203.07:46:13.33#ibcon#about to read 6, iclass 36, count 2 2006.203.07:46:13.33#ibcon#read 6, iclass 36, count 2 2006.203.07:46:13.33#ibcon#end of sib2, iclass 36, count 2 2006.203.07:46:13.33#ibcon#*mode == 0, iclass 36, count 2 2006.203.07:46:13.33#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.203.07:46:13.33#ibcon#[27=AT06-04\r\n] 2006.203.07:46:13.33#ibcon#*before write, iclass 36, count 2 2006.203.07:46:13.33#ibcon#enter sib2, iclass 36, count 2 2006.203.07:46:13.33#ibcon#flushed, iclass 36, count 2 2006.203.07:46:13.33#ibcon#about to write, iclass 36, count 2 2006.203.07:46:13.33#ibcon#wrote, iclass 36, count 2 2006.203.07:46:13.33#ibcon#about to read 3, iclass 36, count 2 2006.203.07:46:13.36#ibcon#read 3, iclass 36, count 2 2006.203.07:46:13.36#ibcon#about to read 4, iclass 36, count 2 2006.203.07:46:13.36#ibcon#read 4, iclass 36, count 2 2006.203.07:46:13.36#ibcon#about to read 5, iclass 36, count 2 2006.203.07:46:13.36#ibcon#read 5, iclass 36, count 2 2006.203.07:46:13.36#ibcon#about to read 6, iclass 36, count 2 2006.203.07:46:13.36#ibcon#read 6, iclass 36, count 2 2006.203.07:46:13.36#ibcon#end of sib2, iclass 36, count 2 2006.203.07:46:13.36#ibcon#*after write, iclass 36, count 2 2006.203.07:46:13.36#ibcon#*before return 0, iclass 36, count 2 2006.203.07:46:13.36#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.203.07:46:13.36#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.203.07:46:13.36#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.203.07:46:13.36#ibcon#ireg 7 cls_cnt 0 2006.203.07:46:13.36#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.203.07:46:13.48#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.203.07:46:13.48#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.203.07:46:13.48#ibcon#enter wrdev, iclass 36, count 0 2006.203.07:46:13.48#ibcon#first serial, iclass 36, count 0 2006.203.07:46:13.48#ibcon#enter sib2, iclass 36, count 0 2006.203.07:46:13.48#ibcon#flushed, iclass 36, count 0 2006.203.07:46:13.48#ibcon#about to write, iclass 36, count 0 2006.203.07:46:13.48#ibcon#wrote, iclass 36, count 0 2006.203.07:46:13.48#ibcon#about to read 3, iclass 36, count 0 2006.203.07:46:13.50#ibcon#read 3, iclass 36, count 0 2006.203.07:46:13.50#ibcon#about to read 4, iclass 36, count 0 2006.203.07:46:13.50#ibcon#read 4, iclass 36, count 0 2006.203.07:46:13.50#ibcon#about to read 5, iclass 36, count 0 2006.203.07:46:13.50#ibcon#read 5, iclass 36, count 0 2006.203.07:46:13.50#ibcon#about to read 6, iclass 36, count 0 2006.203.07:46:13.50#ibcon#read 6, iclass 36, count 0 2006.203.07:46:13.50#ibcon#end of sib2, iclass 36, count 0 2006.203.07:46:13.50#ibcon#*mode == 0, iclass 36, count 0 2006.203.07:46:13.50#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.203.07:46:13.50#ibcon#[27=USB\r\n] 2006.203.07:46:13.50#ibcon#*before write, iclass 36, count 0 2006.203.07:46:13.50#ibcon#enter sib2, iclass 36, count 0 2006.203.07:46:13.50#ibcon#flushed, iclass 36, count 0 2006.203.07:46:13.50#ibcon#about to write, iclass 36, count 0 2006.203.07:46:13.50#ibcon#wrote, iclass 36, count 0 2006.203.07:46:13.50#ibcon#about to read 3, iclass 36, count 0 2006.203.07:46:13.53#ibcon#read 3, iclass 36, count 0 2006.203.07:46:13.53#ibcon#about to read 4, iclass 36, count 0 2006.203.07:46:13.53#ibcon#read 4, iclass 36, count 0 2006.203.07:46:13.53#ibcon#about to read 5, iclass 36, count 0 2006.203.07:46:13.53#ibcon#read 5, iclass 36, count 0 2006.203.07:46:13.53#ibcon#about to read 6, iclass 36, count 0 2006.203.07:46:13.53#ibcon#read 6, iclass 36, count 0 2006.203.07:46:13.53#ibcon#end of sib2, iclass 36, count 0 2006.203.07:46:13.53#ibcon#*after write, iclass 36, count 0 2006.203.07:46:13.53#ibcon#*before return 0, iclass 36, count 0 2006.203.07:46:13.53#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.203.07:46:13.53#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.203.07:46:13.53#ibcon#about to clear, iclass 36 cls_cnt 0 2006.203.07:46:13.53#ibcon#cleared, iclass 36 cls_cnt 0 2006.203.07:46:13.53$vc4f8/vabw=wide 2006.203.07:46:13.53#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.203.07:46:13.53#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.203.07:46:13.53#ibcon#ireg 8 cls_cnt 0 2006.203.07:46:13.53#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.203.07:46:13.53#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.203.07:46:13.53#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.203.07:46:13.53#ibcon#enter wrdev, iclass 38, count 0 2006.203.07:46:13.53#ibcon#first serial, iclass 38, count 0 2006.203.07:46:13.53#ibcon#enter sib2, iclass 38, count 0 2006.203.07:46:13.53#ibcon#flushed, iclass 38, count 0 2006.203.07:46:13.53#ibcon#about to write, iclass 38, count 0 2006.203.07:46:13.53#ibcon#wrote, iclass 38, count 0 2006.203.07:46:13.53#ibcon#about to read 3, iclass 38, count 0 2006.203.07:46:13.55#ibcon#read 3, iclass 38, count 0 2006.203.07:46:13.55#ibcon#about to read 4, iclass 38, count 0 2006.203.07:46:13.55#ibcon#read 4, iclass 38, count 0 2006.203.07:46:13.55#ibcon#about to read 5, iclass 38, count 0 2006.203.07:46:13.55#ibcon#read 5, iclass 38, count 0 2006.203.07:46:13.55#ibcon#about to read 6, iclass 38, count 0 2006.203.07:46:13.55#ibcon#read 6, iclass 38, count 0 2006.203.07:46:13.55#ibcon#end of sib2, iclass 38, count 0 2006.203.07:46:13.55#ibcon#*mode == 0, iclass 38, count 0 2006.203.07:46:13.55#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.203.07:46:13.55#ibcon#[25=BW32\r\n] 2006.203.07:46:13.55#ibcon#*before write, iclass 38, count 0 2006.203.07:46:13.55#ibcon#enter sib2, iclass 38, count 0 2006.203.07:46:13.55#ibcon#flushed, iclass 38, count 0 2006.203.07:46:13.55#ibcon#about to write, iclass 38, count 0 2006.203.07:46:13.55#ibcon#wrote, iclass 38, count 0 2006.203.07:46:13.55#ibcon#about to read 3, iclass 38, count 0 2006.203.07:46:13.58#ibcon#read 3, iclass 38, count 0 2006.203.07:46:13.58#ibcon#about to read 4, iclass 38, count 0 2006.203.07:46:13.58#ibcon#read 4, iclass 38, count 0 2006.203.07:46:13.58#ibcon#about to read 5, iclass 38, count 0 2006.203.07:46:13.58#ibcon#read 5, iclass 38, count 0 2006.203.07:46:13.58#ibcon#about to read 6, iclass 38, count 0 2006.203.07:46:13.58#ibcon#read 6, iclass 38, count 0 2006.203.07:46:13.58#ibcon#end of sib2, iclass 38, count 0 2006.203.07:46:13.58#ibcon#*after write, iclass 38, count 0 2006.203.07:46:13.58#ibcon#*before return 0, iclass 38, count 0 2006.203.07:46:13.58#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.203.07:46:13.58#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.203.07:46:13.58#ibcon#about to clear, iclass 38 cls_cnt 0 2006.203.07:46:13.58#ibcon#cleared, iclass 38 cls_cnt 0 2006.203.07:46:13.58$vc4f8/vbbw=wide 2006.203.07:46:13.58#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.203.07:46:13.58#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.203.07:46:13.58#ibcon#ireg 8 cls_cnt 0 2006.203.07:46:13.58#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.203.07:46:13.65#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.203.07:46:13.65#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.203.07:46:13.65#ibcon#enter wrdev, iclass 40, count 0 2006.203.07:46:13.65#ibcon#first serial, iclass 40, count 0 2006.203.07:46:13.65#ibcon#enter sib2, iclass 40, count 0 2006.203.07:46:13.65#ibcon#flushed, iclass 40, count 0 2006.203.07:46:13.65#ibcon#about to write, iclass 40, count 0 2006.203.07:46:13.65#ibcon#wrote, iclass 40, count 0 2006.203.07:46:13.65#ibcon#about to read 3, iclass 40, count 0 2006.203.07:46:13.67#ibcon#read 3, iclass 40, count 0 2006.203.07:46:13.67#ibcon#about to read 4, iclass 40, count 0 2006.203.07:46:13.67#ibcon#read 4, iclass 40, count 0 2006.203.07:46:13.67#ibcon#about to read 5, iclass 40, count 0 2006.203.07:46:13.67#ibcon#read 5, iclass 40, count 0 2006.203.07:46:13.67#ibcon#about to read 6, iclass 40, count 0 2006.203.07:46:13.67#ibcon#read 6, iclass 40, count 0 2006.203.07:46:13.67#ibcon#end of sib2, iclass 40, count 0 2006.203.07:46:13.67#ibcon#*mode == 0, iclass 40, count 0 2006.203.07:46:13.67#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.203.07:46:13.67#ibcon#[27=BW32\r\n] 2006.203.07:46:13.67#ibcon#*before write, iclass 40, count 0 2006.203.07:46:13.67#ibcon#enter sib2, iclass 40, count 0 2006.203.07:46:13.67#ibcon#flushed, iclass 40, count 0 2006.203.07:46:13.67#ibcon#about to write, iclass 40, count 0 2006.203.07:46:13.67#ibcon#wrote, iclass 40, count 0 2006.203.07:46:13.67#ibcon#about to read 3, iclass 40, count 0 2006.203.07:46:13.70#ibcon#read 3, iclass 40, count 0 2006.203.07:46:13.70#ibcon#about to read 4, iclass 40, count 0 2006.203.07:46:13.70#ibcon#read 4, iclass 40, count 0 2006.203.07:46:13.70#ibcon#about to read 5, iclass 40, count 0 2006.203.07:46:13.70#ibcon#read 5, iclass 40, count 0 2006.203.07:46:13.70#ibcon#about to read 6, iclass 40, count 0 2006.203.07:46:13.70#ibcon#read 6, iclass 40, count 0 2006.203.07:46:13.70#ibcon#end of sib2, iclass 40, count 0 2006.203.07:46:13.70#ibcon#*after write, iclass 40, count 0 2006.203.07:46:13.70#ibcon#*before return 0, iclass 40, count 0 2006.203.07:46:13.70#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.203.07:46:13.70#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.203.07:46:13.70#ibcon#about to clear, iclass 40 cls_cnt 0 2006.203.07:46:13.70#ibcon#cleared, iclass 40 cls_cnt 0 2006.203.07:46:13.70$4f8m12a/ifd4f 2006.203.07:46:13.70$ifd4f/lo= 2006.203.07:46:13.70$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.203.07:46:13.70$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.203.07:46:13.70$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.203.07:46:13.70$ifd4f/patch= 2006.203.07:46:13.70$ifd4f/patch=lo1,a1,a2,a3,a4 2006.203.07:46:13.70$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.203.07:46:13.70$ifd4f/patch=lo3,a5,a6,a7,a8 2006.203.07:46:13.70$4f8m12a/"form=m,16.000,1:2 2006.203.07:46:13.70$4f8m12a/"tpicd 2006.203.07:46:13.70$4f8m12a/echo=off 2006.203.07:46:13.70$4f8m12a/xlog=off 2006.203.07:46:13.70:!2006.203.07:47:10 2006.203.07:46:44.13#trakl#Source acquired 2006.203.07:46:46.13#flagr#flagr/antenna,acquired 2006.203.07:47:10.00:preob 2006.203.07:47:11.13/onsource/TRACKING 2006.203.07:47:11.13:!2006.203.07:47:20 2006.203.07:47:20.00:data_valid=on 2006.203.07:47:20.00:midob 2006.203.07:47:20.13/onsource/TRACKING 2006.203.07:47:20.13/wx/23.87,1001.2,98 2006.203.07:47:20.23/cable/+6.4607E-03 2006.203.07:47:21.32/va/01,08,usb,yes,28,30 2006.203.07:47:21.32/va/02,07,usb,yes,29,30 2006.203.07:47:21.32/va/03,08,usb,yes,21,22 2006.203.07:47:21.32/va/04,07,usb,yes,29,32 2006.203.07:47:21.32/va/05,07,usb,yes,31,33 2006.203.07:47:21.32/va/06,06,usb,yes,31,30 2006.203.07:47:21.32/va/07,07,usb,yes,27,27 2006.203.07:47:21.32/va/08,06,usb,yes,33,33 2006.203.07:47:21.55/valo/01,532.99,yes,locked 2006.203.07:47:21.55/valo/02,572.99,yes,locked 2006.203.07:47:21.55/valo/03,672.99,yes,locked 2006.203.07:47:21.55/valo/04,832.99,yes,locked 2006.203.07:47:21.55/valo/05,652.99,yes,locked 2006.203.07:47:21.55/valo/06,772.99,yes,locked 2006.203.07:47:21.55/valo/07,832.99,yes,locked 2006.203.07:47:21.55/valo/08,852.99,yes,locked 2006.203.07:47:22.64/vb/01,04,usb,yes,28,27 2006.203.07:47:22.64/vb/02,04,usb,yes,30,31 2006.203.07:47:22.64/vb/03,04,usb,yes,27,30 2006.203.07:47:22.64/vb/04,04,usb,yes,27,27 2006.203.07:47:22.64/vb/05,03,usb,yes,32,37 2006.203.07:47:22.64/vb/06,04,usb,yes,27,29 2006.203.07:47:22.64/vb/07,04,usb,yes,29,29 2006.203.07:47:22.64/vb/08,04,usb,yes,26,30 2006.203.07:47:22.88/vblo/01,632.99,yes,locked 2006.203.07:47:22.88/vblo/02,640.99,yes,locked 2006.203.07:47:22.88/vblo/03,656.99,yes,locked 2006.203.07:47:22.88/vblo/04,712.99,yes,locked 2006.203.07:47:22.88/vblo/05,744.99,yes,locked 2006.203.07:47:22.88/vblo/06,752.99,yes,locked 2006.203.07:47:22.88/vblo/07,734.99,yes,locked 2006.203.07:47:22.88/vblo/08,744.99,yes,locked 2006.203.07:47:23.03/vabw/8 2006.203.07:47:23.18/vbbw/8 2006.203.07:47:23.27/xfe/off,on,15.2 2006.203.07:47:23.65/ifatt/23,28,28,28 2006.203.07:47:24.08/fmout-gps/S +4.54E-07 2006.203.07:47:24.16:!2006.203.07:48:20 2006.203.07:48:20.00:data_valid=off 2006.203.07:48:20.00:postob 2006.203.07:48:20.09/cable/+6.4604E-03 2006.203.07:48:20.09/wx/23.87,1001.2,98 2006.203.07:48:21.07/fmout-gps/S +4.52E-07 2006.203.07:48:21.07:scan_name=203-0749,k06203,60 2006.203.07:48:21.08:source=3c371,180650.68,694928.1,2000.0,cw 2006.203.07:48:21.13#flagr#flagr/antenna,new-source 2006.203.07:48:22.13:checkk5 2006.203.07:48:22.53/chk_autoobs//k5ts1/ autoobs is running! 2006.203.07:48:22.96/chk_autoobs//k5ts2/ autoobs is running! 2006.203.07:48:23.38/chk_autoobs//k5ts3/ autoobs is running! 2006.203.07:48:23.83/chk_autoobs//k5ts4/ autoobs is running! 2006.203.07:48:24.25/chk_obsdata//k5ts1/T2030747??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.07:48:24.63/chk_obsdata//k5ts2/T2030747??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.07:48:25.05/chk_obsdata//k5ts3/T2030747??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.07:48:25.46/chk_obsdata//k5ts4/T2030747??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.07:48:26.27/k5log//k5ts1_log_newline 2006.203.07:48:27.03/k5log//k5ts2_log_newline 2006.203.07:48:27.79/k5log//k5ts3_log_newline 2006.203.07:48:28.62/k5log//k5ts4_log_newline 2006.203.07:48:28.65/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.203.07:48:28.65:4f8m12a=1 2006.203.07:48:28.65$4f8m12a/echo=on 2006.203.07:48:28.65$4f8m12a/pcalon 2006.203.07:48:28.65$pcalon/"no phase cal control is implemented here 2006.203.07:48:28.65$4f8m12a/"tpicd=stop 2006.203.07:48:28.65$4f8m12a/vc4f8 2006.203.07:48:28.65$vc4f8/valo=1,532.99 2006.203.07:48:28.65#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.203.07:48:28.65#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.203.07:48:28.65#ibcon#ireg 17 cls_cnt 0 2006.203.07:48:28.65#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.203.07:48:28.65#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.203.07:48:28.65#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.203.07:48:28.65#ibcon#enter wrdev, iclass 23, count 0 2006.203.07:48:28.65#ibcon#first serial, iclass 23, count 0 2006.203.07:48:28.65#ibcon#enter sib2, iclass 23, count 0 2006.203.07:48:28.65#ibcon#flushed, iclass 23, count 0 2006.203.07:48:28.65#ibcon#about to write, iclass 23, count 0 2006.203.07:48:28.65#ibcon#wrote, iclass 23, count 0 2006.203.07:48:28.65#ibcon#about to read 3, iclass 23, count 0 2006.203.07:48:28.69#ibcon#read 3, iclass 23, count 0 2006.203.07:48:28.69#ibcon#about to read 4, iclass 23, count 0 2006.203.07:48:28.69#ibcon#read 4, iclass 23, count 0 2006.203.07:48:28.69#ibcon#about to read 5, iclass 23, count 0 2006.203.07:48:28.69#ibcon#read 5, iclass 23, count 0 2006.203.07:48:28.69#ibcon#about to read 6, iclass 23, count 0 2006.203.07:48:28.69#ibcon#read 6, iclass 23, count 0 2006.203.07:48:28.69#ibcon#end of sib2, iclass 23, count 0 2006.203.07:48:28.69#ibcon#*mode == 0, iclass 23, count 0 2006.203.07:48:28.69#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.203.07:48:28.69#ibcon#[26=FRQ=01,532.99\r\n] 2006.203.07:48:28.69#ibcon#*before write, iclass 23, count 0 2006.203.07:48:28.69#ibcon#enter sib2, iclass 23, count 0 2006.203.07:48:28.69#ibcon#flushed, iclass 23, count 0 2006.203.07:48:28.69#ibcon#about to write, iclass 23, count 0 2006.203.07:48:28.69#ibcon#wrote, iclass 23, count 0 2006.203.07:48:28.69#ibcon#about to read 3, iclass 23, count 0 2006.203.07:48:28.74#ibcon#read 3, iclass 23, count 0 2006.203.07:48:28.74#ibcon#about to read 4, iclass 23, count 0 2006.203.07:48:28.74#ibcon#read 4, iclass 23, count 0 2006.203.07:48:28.74#ibcon#about to read 5, iclass 23, count 0 2006.203.07:48:28.74#ibcon#read 5, iclass 23, count 0 2006.203.07:48:28.74#ibcon#about to read 6, iclass 23, count 0 2006.203.07:48:28.74#ibcon#read 6, iclass 23, count 0 2006.203.07:48:28.74#ibcon#end of sib2, iclass 23, count 0 2006.203.07:48:28.74#ibcon#*after write, iclass 23, count 0 2006.203.07:48:28.74#ibcon#*before return 0, iclass 23, count 0 2006.203.07:48:28.74#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.203.07:48:28.74#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.203.07:48:28.74#ibcon#about to clear, iclass 23 cls_cnt 0 2006.203.07:48:28.74#ibcon#cleared, iclass 23 cls_cnt 0 2006.203.07:48:28.74$vc4f8/va=1,8 2006.203.07:48:28.74#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.203.07:48:28.74#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.203.07:48:28.74#ibcon#ireg 11 cls_cnt 2 2006.203.07:48:28.74#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.203.07:48:28.74#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.203.07:48:28.74#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.203.07:48:28.74#ibcon#enter wrdev, iclass 25, count 2 2006.203.07:48:28.74#ibcon#first serial, iclass 25, count 2 2006.203.07:48:28.74#ibcon#enter sib2, iclass 25, count 2 2006.203.07:48:28.74#ibcon#flushed, iclass 25, count 2 2006.203.07:48:28.74#ibcon#about to write, iclass 25, count 2 2006.203.07:48:28.74#ibcon#wrote, iclass 25, count 2 2006.203.07:48:28.74#ibcon#about to read 3, iclass 25, count 2 2006.203.07:48:28.77#ibcon#read 3, iclass 25, count 2 2006.203.07:48:28.77#ibcon#about to read 4, iclass 25, count 2 2006.203.07:48:28.77#ibcon#read 4, iclass 25, count 2 2006.203.07:48:28.77#ibcon#about to read 5, iclass 25, count 2 2006.203.07:48:28.77#ibcon#read 5, iclass 25, count 2 2006.203.07:48:28.77#ibcon#about to read 6, iclass 25, count 2 2006.203.07:48:28.77#ibcon#read 6, iclass 25, count 2 2006.203.07:48:28.77#ibcon#end of sib2, iclass 25, count 2 2006.203.07:48:28.77#ibcon#*mode == 0, iclass 25, count 2 2006.203.07:48:28.77#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.203.07:48:28.77#ibcon#[25=AT01-08\r\n] 2006.203.07:48:28.77#ibcon#*before write, iclass 25, count 2 2006.203.07:48:28.77#ibcon#enter sib2, iclass 25, count 2 2006.203.07:48:28.77#ibcon#flushed, iclass 25, count 2 2006.203.07:48:28.77#ibcon#about to write, iclass 25, count 2 2006.203.07:48:28.77#ibcon#wrote, iclass 25, count 2 2006.203.07:48:28.77#ibcon#about to read 3, iclass 25, count 2 2006.203.07:48:28.80#ibcon#read 3, iclass 25, count 2 2006.203.07:48:28.80#ibcon#about to read 4, iclass 25, count 2 2006.203.07:48:28.80#ibcon#read 4, iclass 25, count 2 2006.203.07:48:28.80#ibcon#about to read 5, iclass 25, count 2 2006.203.07:48:28.80#ibcon#read 5, iclass 25, count 2 2006.203.07:48:28.80#ibcon#about to read 6, iclass 25, count 2 2006.203.07:48:28.80#ibcon#read 6, iclass 25, count 2 2006.203.07:48:28.80#ibcon#end of sib2, iclass 25, count 2 2006.203.07:48:28.80#ibcon#*after write, iclass 25, count 2 2006.203.07:48:28.80#ibcon#*before return 0, iclass 25, count 2 2006.203.07:48:28.80#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.203.07:48:28.80#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.203.07:48:28.80#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.203.07:48:28.80#ibcon#ireg 7 cls_cnt 0 2006.203.07:48:28.80#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.203.07:48:28.92#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.203.07:48:28.92#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.203.07:48:28.92#ibcon#enter wrdev, iclass 25, count 0 2006.203.07:48:28.92#ibcon#first serial, iclass 25, count 0 2006.203.07:48:28.92#ibcon#enter sib2, iclass 25, count 0 2006.203.07:48:28.92#ibcon#flushed, iclass 25, count 0 2006.203.07:48:28.92#ibcon#about to write, iclass 25, count 0 2006.203.07:48:28.92#ibcon#wrote, iclass 25, count 0 2006.203.07:48:28.92#ibcon#about to read 3, iclass 25, count 0 2006.203.07:48:28.94#ibcon#read 3, iclass 25, count 0 2006.203.07:48:28.94#ibcon#about to read 4, iclass 25, count 0 2006.203.07:48:28.94#ibcon#read 4, iclass 25, count 0 2006.203.07:48:28.94#ibcon#about to read 5, iclass 25, count 0 2006.203.07:48:28.94#ibcon#read 5, iclass 25, count 0 2006.203.07:48:28.94#ibcon#about to read 6, iclass 25, count 0 2006.203.07:48:28.94#ibcon#read 6, iclass 25, count 0 2006.203.07:48:28.94#ibcon#end of sib2, iclass 25, count 0 2006.203.07:48:28.94#ibcon#*mode == 0, iclass 25, count 0 2006.203.07:48:28.94#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.203.07:48:28.94#ibcon#[25=USB\r\n] 2006.203.07:48:28.94#ibcon#*before write, iclass 25, count 0 2006.203.07:48:28.94#ibcon#enter sib2, iclass 25, count 0 2006.203.07:48:28.94#ibcon#flushed, iclass 25, count 0 2006.203.07:48:28.94#ibcon#about to write, iclass 25, count 0 2006.203.07:48:28.94#ibcon#wrote, iclass 25, count 0 2006.203.07:48:28.94#ibcon#about to read 3, iclass 25, count 0 2006.203.07:48:28.97#ibcon#read 3, iclass 25, count 0 2006.203.07:48:28.97#ibcon#about to read 4, iclass 25, count 0 2006.203.07:48:28.97#ibcon#read 4, iclass 25, count 0 2006.203.07:48:28.97#ibcon#about to read 5, iclass 25, count 0 2006.203.07:48:28.97#ibcon#read 5, iclass 25, count 0 2006.203.07:48:28.97#ibcon#about to read 6, iclass 25, count 0 2006.203.07:48:28.97#ibcon#read 6, iclass 25, count 0 2006.203.07:48:28.97#ibcon#end of sib2, iclass 25, count 0 2006.203.07:48:28.97#ibcon#*after write, iclass 25, count 0 2006.203.07:48:28.97#ibcon#*before return 0, iclass 25, count 0 2006.203.07:48:28.97#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.203.07:48:28.97#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.203.07:48:28.97#ibcon#about to clear, iclass 25 cls_cnt 0 2006.203.07:48:28.97#ibcon#cleared, iclass 25 cls_cnt 0 2006.203.07:48:28.97$vc4f8/valo=2,572.99 2006.203.07:48:28.97#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.203.07:48:28.97#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.203.07:48:28.97#ibcon#ireg 17 cls_cnt 0 2006.203.07:48:28.97#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:48:28.97#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:48:28.97#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:48:28.97#ibcon#enter wrdev, iclass 27, count 0 2006.203.07:48:28.97#ibcon#first serial, iclass 27, count 0 2006.203.07:48:28.97#ibcon#enter sib2, iclass 27, count 0 2006.203.07:48:28.97#ibcon#flushed, iclass 27, count 0 2006.203.07:48:28.97#ibcon#about to write, iclass 27, count 0 2006.203.07:48:28.97#ibcon#wrote, iclass 27, count 0 2006.203.07:48:28.97#ibcon#about to read 3, iclass 27, count 0 2006.203.07:48:29.00#ibcon#read 3, iclass 27, count 0 2006.203.07:48:29.00#ibcon#about to read 4, iclass 27, count 0 2006.203.07:48:29.00#ibcon#read 4, iclass 27, count 0 2006.203.07:48:29.00#ibcon#about to read 5, iclass 27, count 0 2006.203.07:48:29.00#ibcon#read 5, iclass 27, count 0 2006.203.07:48:29.00#ibcon#about to read 6, iclass 27, count 0 2006.203.07:48:29.00#ibcon#read 6, iclass 27, count 0 2006.203.07:48:29.00#ibcon#end of sib2, iclass 27, count 0 2006.203.07:48:29.00#ibcon#*mode == 0, iclass 27, count 0 2006.203.07:48:29.00#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.203.07:48:29.00#ibcon#[26=FRQ=02,572.99\r\n] 2006.203.07:48:29.00#ibcon#*before write, iclass 27, count 0 2006.203.07:48:29.00#ibcon#enter sib2, iclass 27, count 0 2006.203.07:48:29.00#ibcon#flushed, iclass 27, count 0 2006.203.07:48:29.00#ibcon#about to write, iclass 27, count 0 2006.203.07:48:29.00#ibcon#wrote, iclass 27, count 0 2006.203.07:48:29.00#ibcon#about to read 3, iclass 27, count 0 2006.203.07:48:29.04#ibcon#read 3, iclass 27, count 0 2006.203.07:48:29.04#ibcon#about to read 4, iclass 27, count 0 2006.203.07:48:29.04#ibcon#read 4, iclass 27, count 0 2006.203.07:48:29.04#ibcon#about to read 5, iclass 27, count 0 2006.203.07:48:29.04#ibcon#read 5, iclass 27, count 0 2006.203.07:48:29.04#ibcon#about to read 6, iclass 27, count 0 2006.203.07:48:29.04#ibcon#read 6, iclass 27, count 0 2006.203.07:48:29.04#ibcon#end of sib2, iclass 27, count 0 2006.203.07:48:29.04#ibcon#*after write, iclass 27, count 0 2006.203.07:48:29.04#ibcon#*before return 0, iclass 27, count 0 2006.203.07:48:29.04#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:48:29.04#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:48:29.04#ibcon#about to clear, iclass 27 cls_cnt 0 2006.203.07:48:29.04#ibcon#cleared, iclass 27 cls_cnt 0 2006.203.07:48:29.04$vc4f8/va=2,7 2006.203.07:48:29.04#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.203.07:48:29.04#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.203.07:48:29.04#ibcon#ireg 11 cls_cnt 2 2006.203.07:48:29.04#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.203.07:48:29.09#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.203.07:48:29.09#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.203.07:48:29.09#ibcon#enter wrdev, iclass 29, count 2 2006.203.07:48:29.09#ibcon#first serial, iclass 29, count 2 2006.203.07:48:29.09#ibcon#enter sib2, iclass 29, count 2 2006.203.07:48:29.09#ibcon#flushed, iclass 29, count 2 2006.203.07:48:29.09#ibcon#about to write, iclass 29, count 2 2006.203.07:48:29.09#ibcon#wrote, iclass 29, count 2 2006.203.07:48:29.09#ibcon#about to read 3, iclass 29, count 2 2006.203.07:48:29.11#ibcon#read 3, iclass 29, count 2 2006.203.07:48:29.11#ibcon#about to read 4, iclass 29, count 2 2006.203.07:48:29.11#ibcon#read 4, iclass 29, count 2 2006.203.07:48:29.11#ibcon#about to read 5, iclass 29, count 2 2006.203.07:48:29.11#ibcon#read 5, iclass 29, count 2 2006.203.07:48:29.11#ibcon#about to read 6, iclass 29, count 2 2006.203.07:48:29.11#ibcon#read 6, iclass 29, count 2 2006.203.07:48:29.11#ibcon#end of sib2, iclass 29, count 2 2006.203.07:48:29.11#ibcon#*mode == 0, iclass 29, count 2 2006.203.07:48:29.11#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.203.07:48:29.11#ibcon#[25=AT02-07\r\n] 2006.203.07:48:29.11#ibcon#*before write, iclass 29, count 2 2006.203.07:48:29.11#ibcon#enter sib2, iclass 29, count 2 2006.203.07:48:29.11#ibcon#flushed, iclass 29, count 2 2006.203.07:48:29.11#ibcon#about to write, iclass 29, count 2 2006.203.07:48:29.11#ibcon#wrote, iclass 29, count 2 2006.203.07:48:29.11#ibcon#about to read 3, iclass 29, count 2 2006.203.07:48:29.14#ibcon#read 3, iclass 29, count 2 2006.203.07:48:29.14#ibcon#about to read 4, iclass 29, count 2 2006.203.07:48:29.14#ibcon#read 4, iclass 29, count 2 2006.203.07:48:29.14#ibcon#about to read 5, iclass 29, count 2 2006.203.07:48:29.14#ibcon#read 5, iclass 29, count 2 2006.203.07:48:29.14#ibcon#about to read 6, iclass 29, count 2 2006.203.07:48:29.14#ibcon#read 6, iclass 29, count 2 2006.203.07:48:29.14#ibcon#end of sib2, iclass 29, count 2 2006.203.07:48:29.14#ibcon#*after write, iclass 29, count 2 2006.203.07:48:29.14#ibcon#*before return 0, iclass 29, count 2 2006.203.07:48:29.14#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.203.07:48:29.14#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.203.07:48:29.14#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.203.07:48:29.14#ibcon#ireg 7 cls_cnt 0 2006.203.07:48:29.14#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.203.07:48:29.26#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.203.07:48:29.26#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.203.07:48:29.26#ibcon#enter wrdev, iclass 29, count 0 2006.203.07:48:29.26#ibcon#first serial, iclass 29, count 0 2006.203.07:48:29.26#ibcon#enter sib2, iclass 29, count 0 2006.203.07:48:29.26#ibcon#flushed, iclass 29, count 0 2006.203.07:48:29.26#ibcon#about to write, iclass 29, count 0 2006.203.07:48:29.26#ibcon#wrote, iclass 29, count 0 2006.203.07:48:29.26#ibcon#about to read 3, iclass 29, count 0 2006.203.07:48:29.28#ibcon#read 3, iclass 29, count 0 2006.203.07:48:29.28#ibcon#about to read 4, iclass 29, count 0 2006.203.07:48:29.28#ibcon#read 4, iclass 29, count 0 2006.203.07:48:29.28#ibcon#about to read 5, iclass 29, count 0 2006.203.07:48:29.28#ibcon#read 5, iclass 29, count 0 2006.203.07:48:29.28#ibcon#about to read 6, iclass 29, count 0 2006.203.07:48:29.28#ibcon#read 6, iclass 29, count 0 2006.203.07:48:29.28#ibcon#end of sib2, iclass 29, count 0 2006.203.07:48:29.28#ibcon#*mode == 0, iclass 29, count 0 2006.203.07:48:29.28#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.203.07:48:29.28#ibcon#[25=USB\r\n] 2006.203.07:48:29.28#ibcon#*before write, iclass 29, count 0 2006.203.07:48:29.28#ibcon#enter sib2, iclass 29, count 0 2006.203.07:48:29.28#ibcon#flushed, iclass 29, count 0 2006.203.07:48:29.28#ibcon#about to write, iclass 29, count 0 2006.203.07:48:29.28#ibcon#wrote, iclass 29, count 0 2006.203.07:48:29.28#ibcon#about to read 3, iclass 29, count 0 2006.203.07:48:29.31#ibcon#read 3, iclass 29, count 0 2006.203.07:48:29.31#ibcon#about to read 4, iclass 29, count 0 2006.203.07:48:29.31#ibcon#read 4, iclass 29, count 0 2006.203.07:48:29.31#ibcon#about to read 5, iclass 29, count 0 2006.203.07:48:29.31#ibcon#read 5, iclass 29, count 0 2006.203.07:48:29.31#ibcon#about to read 6, iclass 29, count 0 2006.203.07:48:29.31#ibcon#read 6, iclass 29, count 0 2006.203.07:48:29.31#ibcon#end of sib2, iclass 29, count 0 2006.203.07:48:29.31#ibcon#*after write, iclass 29, count 0 2006.203.07:48:29.31#ibcon#*before return 0, iclass 29, count 0 2006.203.07:48:29.31#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.203.07:48:29.31#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.203.07:48:29.31#ibcon#about to clear, iclass 29 cls_cnt 0 2006.203.07:48:29.31#ibcon#cleared, iclass 29 cls_cnt 0 2006.203.07:48:29.31$vc4f8/valo=3,672.99 2006.203.07:48:29.31#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.203.07:48:29.31#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.203.07:48:29.31#ibcon#ireg 17 cls_cnt 0 2006.203.07:48:29.31#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.203.07:48:29.31#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.203.07:48:29.31#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.203.07:48:29.31#ibcon#enter wrdev, iclass 31, count 0 2006.203.07:48:29.31#ibcon#first serial, iclass 31, count 0 2006.203.07:48:29.31#ibcon#enter sib2, iclass 31, count 0 2006.203.07:48:29.31#ibcon#flushed, iclass 31, count 0 2006.203.07:48:29.31#ibcon#about to write, iclass 31, count 0 2006.203.07:48:29.31#ibcon#wrote, iclass 31, count 0 2006.203.07:48:29.31#ibcon#about to read 3, iclass 31, count 0 2006.203.07:48:29.34#ibcon#read 3, iclass 31, count 0 2006.203.07:48:29.34#ibcon#about to read 4, iclass 31, count 0 2006.203.07:48:29.34#ibcon#read 4, iclass 31, count 0 2006.203.07:48:29.34#ibcon#about to read 5, iclass 31, count 0 2006.203.07:48:29.34#ibcon#read 5, iclass 31, count 0 2006.203.07:48:29.34#ibcon#about to read 6, iclass 31, count 0 2006.203.07:48:29.34#ibcon#read 6, iclass 31, count 0 2006.203.07:48:29.34#ibcon#end of sib2, iclass 31, count 0 2006.203.07:48:29.34#ibcon#*mode == 0, iclass 31, count 0 2006.203.07:48:29.34#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.203.07:48:29.34#ibcon#[26=FRQ=03,672.99\r\n] 2006.203.07:48:29.34#ibcon#*before write, iclass 31, count 0 2006.203.07:48:29.34#ibcon#enter sib2, iclass 31, count 0 2006.203.07:48:29.34#ibcon#flushed, iclass 31, count 0 2006.203.07:48:29.34#ibcon#about to write, iclass 31, count 0 2006.203.07:48:29.34#ibcon#wrote, iclass 31, count 0 2006.203.07:48:29.34#ibcon#about to read 3, iclass 31, count 0 2006.203.07:48:29.38#ibcon#read 3, iclass 31, count 0 2006.203.07:48:29.38#ibcon#about to read 4, iclass 31, count 0 2006.203.07:48:29.38#ibcon#read 4, iclass 31, count 0 2006.203.07:48:29.38#ibcon#about to read 5, iclass 31, count 0 2006.203.07:48:29.38#ibcon#read 5, iclass 31, count 0 2006.203.07:48:29.38#ibcon#about to read 6, iclass 31, count 0 2006.203.07:48:29.38#ibcon#read 6, iclass 31, count 0 2006.203.07:48:29.38#ibcon#end of sib2, iclass 31, count 0 2006.203.07:48:29.38#ibcon#*after write, iclass 31, count 0 2006.203.07:48:29.38#ibcon#*before return 0, iclass 31, count 0 2006.203.07:48:29.38#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.203.07:48:29.38#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.203.07:48:29.38#ibcon#about to clear, iclass 31 cls_cnt 0 2006.203.07:48:29.38#ibcon#cleared, iclass 31 cls_cnt 0 2006.203.07:48:29.38$vc4f8/va=3,8 2006.203.07:48:29.38#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.203.07:48:29.38#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.203.07:48:29.38#ibcon#ireg 11 cls_cnt 2 2006.203.07:48:29.38#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.203.07:48:29.43#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.203.07:48:29.43#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.203.07:48:29.43#ibcon#enter wrdev, iclass 33, count 2 2006.203.07:48:29.43#ibcon#first serial, iclass 33, count 2 2006.203.07:48:29.43#ibcon#enter sib2, iclass 33, count 2 2006.203.07:48:29.43#ibcon#flushed, iclass 33, count 2 2006.203.07:48:29.43#ibcon#about to write, iclass 33, count 2 2006.203.07:48:29.43#ibcon#wrote, iclass 33, count 2 2006.203.07:48:29.43#ibcon#about to read 3, iclass 33, count 2 2006.203.07:48:29.45#ibcon#read 3, iclass 33, count 2 2006.203.07:48:29.45#ibcon#about to read 4, iclass 33, count 2 2006.203.07:48:29.45#ibcon#read 4, iclass 33, count 2 2006.203.07:48:29.45#ibcon#about to read 5, iclass 33, count 2 2006.203.07:48:29.45#ibcon#read 5, iclass 33, count 2 2006.203.07:48:29.45#ibcon#about to read 6, iclass 33, count 2 2006.203.07:48:29.45#ibcon#read 6, iclass 33, count 2 2006.203.07:48:29.45#ibcon#end of sib2, iclass 33, count 2 2006.203.07:48:29.45#ibcon#*mode == 0, iclass 33, count 2 2006.203.07:48:29.45#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.203.07:48:29.45#ibcon#[25=AT03-08\r\n] 2006.203.07:48:29.45#ibcon#*before write, iclass 33, count 2 2006.203.07:48:29.45#ibcon#enter sib2, iclass 33, count 2 2006.203.07:48:29.45#ibcon#flushed, iclass 33, count 2 2006.203.07:48:29.45#ibcon#about to write, iclass 33, count 2 2006.203.07:48:29.45#ibcon#wrote, iclass 33, count 2 2006.203.07:48:29.45#ibcon#about to read 3, iclass 33, count 2 2006.203.07:48:29.48#ibcon#read 3, iclass 33, count 2 2006.203.07:48:29.48#ibcon#about to read 4, iclass 33, count 2 2006.203.07:48:29.48#ibcon#read 4, iclass 33, count 2 2006.203.07:48:29.48#ibcon#about to read 5, iclass 33, count 2 2006.203.07:48:29.48#ibcon#read 5, iclass 33, count 2 2006.203.07:48:29.48#ibcon#about to read 6, iclass 33, count 2 2006.203.07:48:29.48#ibcon#read 6, iclass 33, count 2 2006.203.07:48:29.48#ibcon#end of sib2, iclass 33, count 2 2006.203.07:48:29.48#ibcon#*after write, iclass 33, count 2 2006.203.07:48:29.48#ibcon#*before return 0, iclass 33, count 2 2006.203.07:48:29.48#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.203.07:48:29.48#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.203.07:48:29.48#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.203.07:48:29.48#ibcon#ireg 7 cls_cnt 0 2006.203.07:48:29.48#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.203.07:48:29.60#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.203.07:48:29.60#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.203.07:48:29.60#ibcon#enter wrdev, iclass 33, count 0 2006.203.07:48:29.60#ibcon#first serial, iclass 33, count 0 2006.203.07:48:29.60#ibcon#enter sib2, iclass 33, count 0 2006.203.07:48:29.60#ibcon#flushed, iclass 33, count 0 2006.203.07:48:29.60#ibcon#about to write, iclass 33, count 0 2006.203.07:48:29.60#ibcon#wrote, iclass 33, count 0 2006.203.07:48:29.60#ibcon#about to read 3, iclass 33, count 0 2006.203.07:48:29.62#ibcon#read 3, iclass 33, count 0 2006.203.07:48:29.62#ibcon#about to read 4, iclass 33, count 0 2006.203.07:48:29.62#ibcon#read 4, iclass 33, count 0 2006.203.07:48:29.62#ibcon#about to read 5, iclass 33, count 0 2006.203.07:48:29.62#ibcon#read 5, iclass 33, count 0 2006.203.07:48:29.62#ibcon#about to read 6, iclass 33, count 0 2006.203.07:48:29.62#ibcon#read 6, iclass 33, count 0 2006.203.07:48:29.62#ibcon#end of sib2, iclass 33, count 0 2006.203.07:48:29.62#ibcon#*mode == 0, iclass 33, count 0 2006.203.07:48:29.62#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.203.07:48:29.62#ibcon#[25=USB\r\n] 2006.203.07:48:29.62#ibcon#*before write, iclass 33, count 0 2006.203.07:48:29.62#ibcon#enter sib2, iclass 33, count 0 2006.203.07:48:29.62#ibcon#flushed, iclass 33, count 0 2006.203.07:48:29.62#ibcon#about to write, iclass 33, count 0 2006.203.07:48:29.62#ibcon#wrote, iclass 33, count 0 2006.203.07:48:29.62#ibcon#about to read 3, iclass 33, count 0 2006.203.07:48:29.65#ibcon#read 3, iclass 33, count 0 2006.203.07:48:29.65#ibcon#about to read 4, iclass 33, count 0 2006.203.07:48:29.65#ibcon#read 4, iclass 33, count 0 2006.203.07:48:29.65#ibcon#about to read 5, iclass 33, count 0 2006.203.07:48:29.65#ibcon#read 5, iclass 33, count 0 2006.203.07:48:29.65#ibcon#about to read 6, iclass 33, count 0 2006.203.07:48:29.65#ibcon#read 6, iclass 33, count 0 2006.203.07:48:29.65#ibcon#end of sib2, iclass 33, count 0 2006.203.07:48:29.65#ibcon#*after write, iclass 33, count 0 2006.203.07:48:29.65#ibcon#*before return 0, iclass 33, count 0 2006.203.07:48:29.65#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.203.07:48:29.65#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.203.07:48:29.65#ibcon#about to clear, iclass 33 cls_cnt 0 2006.203.07:48:29.65#ibcon#cleared, iclass 33 cls_cnt 0 2006.203.07:48:29.65$vc4f8/valo=4,832.99 2006.203.07:48:29.65#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.203.07:48:29.65#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.203.07:48:29.65#ibcon#ireg 17 cls_cnt 0 2006.203.07:48:29.65#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.203.07:48:29.65#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.203.07:48:29.65#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.203.07:48:29.65#ibcon#enter wrdev, iclass 35, count 0 2006.203.07:48:29.65#ibcon#first serial, iclass 35, count 0 2006.203.07:48:29.65#ibcon#enter sib2, iclass 35, count 0 2006.203.07:48:29.65#ibcon#flushed, iclass 35, count 0 2006.203.07:48:29.65#ibcon#about to write, iclass 35, count 0 2006.203.07:48:29.65#ibcon#wrote, iclass 35, count 0 2006.203.07:48:29.65#ibcon#about to read 3, iclass 35, count 0 2006.203.07:48:29.67#ibcon#read 3, iclass 35, count 0 2006.203.07:48:29.67#ibcon#about to read 4, iclass 35, count 0 2006.203.07:48:29.67#ibcon#read 4, iclass 35, count 0 2006.203.07:48:29.67#ibcon#about to read 5, iclass 35, count 0 2006.203.07:48:29.67#ibcon#read 5, iclass 35, count 0 2006.203.07:48:29.67#ibcon#about to read 6, iclass 35, count 0 2006.203.07:48:29.67#ibcon#read 6, iclass 35, count 0 2006.203.07:48:29.67#ibcon#end of sib2, iclass 35, count 0 2006.203.07:48:29.67#ibcon#*mode == 0, iclass 35, count 0 2006.203.07:48:29.67#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.203.07:48:29.67#ibcon#[26=FRQ=04,832.99\r\n] 2006.203.07:48:29.67#ibcon#*before write, iclass 35, count 0 2006.203.07:48:29.67#ibcon#enter sib2, iclass 35, count 0 2006.203.07:48:29.67#ibcon#flushed, iclass 35, count 0 2006.203.07:48:29.67#ibcon#about to write, iclass 35, count 0 2006.203.07:48:29.67#ibcon#wrote, iclass 35, count 0 2006.203.07:48:29.67#ibcon#about to read 3, iclass 35, count 0 2006.203.07:48:29.71#ibcon#read 3, iclass 35, count 0 2006.203.07:48:29.71#ibcon#about to read 4, iclass 35, count 0 2006.203.07:48:29.71#ibcon#read 4, iclass 35, count 0 2006.203.07:48:29.71#ibcon#about to read 5, iclass 35, count 0 2006.203.07:48:29.71#ibcon#read 5, iclass 35, count 0 2006.203.07:48:29.71#ibcon#about to read 6, iclass 35, count 0 2006.203.07:48:29.71#ibcon#read 6, iclass 35, count 0 2006.203.07:48:29.71#ibcon#end of sib2, iclass 35, count 0 2006.203.07:48:29.71#ibcon#*after write, iclass 35, count 0 2006.203.07:48:29.71#ibcon#*before return 0, iclass 35, count 0 2006.203.07:48:29.71#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.203.07:48:29.71#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.203.07:48:29.71#ibcon#about to clear, iclass 35 cls_cnt 0 2006.203.07:48:29.71#ibcon#cleared, iclass 35 cls_cnt 0 2006.203.07:48:29.71$vc4f8/va=4,7 2006.203.07:48:29.71#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.203.07:48:29.71#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.203.07:48:29.71#ibcon#ireg 11 cls_cnt 2 2006.203.07:48:29.71#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.203.07:48:29.77#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.203.07:48:29.77#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.203.07:48:29.77#ibcon#enter wrdev, iclass 37, count 2 2006.203.07:48:29.77#ibcon#first serial, iclass 37, count 2 2006.203.07:48:29.77#ibcon#enter sib2, iclass 37, count 2 2006.203.07:48:29.77#ibcon#flushed, iclass 37, count 2 2006.203.07:48:29.77#ibcon#about to write, iclass 37, count 2 2006.203.07:48:29.77#ibcon#wrote, iclass 37, count 2 2006.203.07:48:29.77#ibcon#about to read 3, iclass 37, count 2 2006.203.07:48:29.79#ibcon#read 3, iclass 37, count 2 2006.203.07:48:29.79#ibcon#about to read 4, iclass 37, count 2 2006.203.07:48:29.79#ibcon#read 4, iclass 37, count 2 2006.203.07:48:29.79#ibcon#about to read 5, iclass 37, count 2 2006.203.07:48:29.79#ibcon#read 5, iclass 37, count 2 2006.203.07:48:29.79#ibcon#about to read 6, iclass 37, count 2 2006.203.07:48:29.79#ibcon#read 6, iclass 37, count 2 2006.203.07:48:29.79#ibcon#end of sib2, iclass 37, count 2 2006.203.07:48:29.79#ibcon#*mode == 0, iclass 37, count 2 2006.203.07:48:29.79#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.203.07:48:29.79#ibcon#[25=AT04-07\r\n] 2006.203.07:48:29.79#ibcon#*before write, iclass 37, count 2 2006.203.07:48:29.79#ibcon#enter sib2, iclass 37, count 2 2006.203.07:48:29.79#ibcon#flushed, iclass 37, count 2 2006.203.07:48:29.79#ibcon#about to write, iclass 37, count 2 2006.203.07:48:29.79#ibcon#wrote, iclass 37, count 2 2006.203.07:48:29.79#ibcon#about to read 3, iclass 37, count 2 2006.203.07:48:29.82#ibcon#read 3, iclass 37, count 2 2006.203.07:48:29.82#ibcon#about to read 4, iclass 37, count 2 2006.203.07:48:29.82#ibcon#read 4, iclass 37, count 2 2006.203.07:48:29.82#ibcon#about to read 5, iclass 37, count 2 2006.203.07:48:29.82#ibcon#read 5, iclass 37, count 2 2006.203.07:48:29.82#ibcon#about to read 6, iclass 37, count 2 2006.203.07:48:29.82#ibcon#read 6, iclass 37, count 2 2006.203.07:48:29.82#ibcon#end of sib2, iclass 37, count 2 2006.203.07:48:29.82#ibcon#*after write, iclass 37, count 2 2006.203.07:48:29.82#ibcon#*before return 0, iclass 37, count 2 2006.203.07:48:29.82#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.203.07:48:29.82#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.203.07:48:29.82#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.203.07:48:29.82#ibcon#ireg 7 cls_cnt 0 2006.203.07:48:29.82#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.203.07:48:29.94#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.203.07:48:29.94#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.203.07:48:29.94#ibcon#enter wrdev, iclass 37, count 0 2006.203.07:48:29.94#ibcon#first serial, iclass 37, count 0 2006.203.07:48:29.94#ibcon#enter sib2, iclass 37, count 0 2006.203.07:48:29.94#ibcon#flushed, iclass 37, count 0 2006.203.07:48:29.94#ibcon#about to write, iclass 37, count 0 2006.203.07:48:29.94#ibcon#wrote, iclass 37, count 0 2006.203.07:48:29.94#ibcon#about to read 3, iclass 37, count 0 2006.203.07:48:29.96#ibcon#read 3, iclass 37, count 0 2006.203.07:48:29.96#ibcon#about to read 4, iclass 37, count 0 2006.203.07:48:29.96#ibcon#read 4, iclass 37, count 0 2006.203.07:48:29.96#ibcon#about to read 5, iclass 37, count 0 2006.203.07:48:29.96#ibcon#read 5, iclass 37, count 0 2006.203.07:48:29.96#ibcon#about to read 6, iclass 37, count 0 2006.203.07:48:29.96#ibcon#read 6, iclass 37, count 0 2006.203.07:48:29.96#ibcon#end of sib2, iclass 37, count 0 2006.203.07:48:29.96#ibcon#*mode == 0, iclass 37, count 0 2006.203.07:48:29.96#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.203.07:48:29.96#ibcon#[25=USB\r\n] 2006.203.07:48:29.96#ibcon#*before write, iclass 37, count 0 2006.203.07:48:29.96#ibcon#enter sib2, iclass 37, count 0 2006.203.07:48:29.96#ibcon#flushed, iclass 37, count 0 2006.203.07:48:29.96#ibcon#about to write, iclass 37, count 0 2006.203.07:48:29.96#ibcon#wrote, iclass 37, count 0 2006.203.07:48:29.96#ibcon#about to read 3, iclass 37, count 0 2006.203.07:48:29.99#ibcon#read 3, iclass 37, count 0 2006.203.07:48:29.99#ibcon#about to read 4, iclass 37, count 0 2006.203.07:48:29.99#ibcon#read 4, iclass 37, count 0 2006.203.07:48:29.99#ibcon#about to read 5, iclass 37, count 0 2006.203.07:48:29.99#ibcon#read 5, iclass 37, count 0 2006.203.07:48:29.99#ibcon#about to read 6, iclass 37, count 0 2006.203.07:48:29.99#ibcon#read 6, iclass 37, count 0 2006.203.07:48:29.99#ibcon#end of sib2, iclass 37, count 0 2006.203.07:48:29.99#ibcon#*after write, iclass 37, count 0 2006.203.07:48:29.99#ibcon#*before return 0, iclass 37, count 0 2006.203.07:48:29.99#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.203.07:48:29.99#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.203.07:48:29.99#ibcon#about to clear, iclass 37 cls_cnt 0 2006.203.07:48:29.99#ibcon#cleared, iclass 37 cls_cnt 0 2006.203.07:48:29.99$vc4f8/valo=5,652.99 2006.203.07:48:29.99#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.203.07:48:29.99#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.203.07:48:29.99#ibcon#ireg 17 cls_cnt 0 2006.203.07:48:29.99#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.203.07:48:29.99#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.203.07:48:29.99#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.203.07:48:29.99#ibcon#enter wrdev, iclass 39, count 0 2006.203.07:48:29.99#ibcon#first serial, iclass 39, count 0 2006.203.07:48:29.99#ibcon#enter sib2, iclass 39, count 0 2006.203.07:48:29.99#ibcon#flushed, iclass 39, count 0 2006.203.07:48:29.99#ibcon#about to write, iclass 39, count 0 2006.203.07:48:29.99#ibcon#wrote, iclass 39, count 0 2006.203.07:48:29.99#ibcon#about to read 3, iclass 39, count 0 2006.203.07:48:30.01#ibcon#read 3, iclass 39, count 0 2006.203.07:48:30.01#ibcon#about to read 4, iclass 39, count 0 2006.203.07:48:30.01#ibcon#read 4, iclass 39, count 0 2006.203.07:48:30.01#ibcon#about to read 5, iclass 39, count 0 2006.203.07:48:30.01#ibcon#read 5, iclass 39, count 0 2006.203.07:48:30.01#ibcon#about to read 6, iclass 39, count 0 2006.203.07:48:30.01#ibcon#read 6, iclass 39, count 0 2006.203.07:48:30.01#ibcon#end of sib2, iclass 39, count 0 2006.203.07:48:30.01#ibcon#*mode == 0, iclass 39, count 0 2006.203.07:48:30.01#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.203.07:48:30.01#ibcon#[26=FRQ=05,652.99\r\n] 2006.203.07:48:30.01#ibcon#*before write, iclass 39, count 0 2006.203.07:48:30.01#ibcon#enter sib2, iclass 39, count 0 2006.203.07:48:30.01#ibcon#flushed, iclass 39, count 0 2006.203.07:48:30.01#ibcon#about to write, iclass 39, count 0 2006.203.07:48:30.01#ibcon#wrote, iclass 39, count 0 2006.203.07:48:30.01#ibcon#about to read 3, iclass 39, count 0 2006.203.07:48:30.05#ibcon#read 3, iclass 39, count 0 2006.203.07:48:30.05#ibcon#about to read 4, iclass 39, count 0 2006.203.07:48:30.05#ibcon#read 4, iclass 39, count 0 2006.203.07:48:30.05#ibcon#about to read 5, iclass 39, count 0 2006.203.07:48:30.05#ibcon#read 5, iclass 39, count 0 2006.203.07:48:30.05#ibcon#about to read 6, iclass 39, count 0 2006.203.07:48:30.05#ibcon#read 6, iclass 39, count 0 2006.203.07:48:30.05#ibcon#end of sib2, iclass 39, count 0 2006.203.07:48:30.05#ibcon#*after write, iclass 39, count 0 2006.203.07:48:30.05#ibcon#*before return 0, iclass 39, count 0 2006.203.07:48:30.05#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.203.07:48:30.05#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.203.07:48:30.05#ibcon#about to clear, iclass 39 cls_cnt 0 2006.203.07:48:30.05#ibcon#cleared, iclass 39 cls_cnt 0 2006.203.07:48:30.05$vc4f8/va=5,7 2006.203.07:48:30.05#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.203.07:48:30.05#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.203.07:48:30.05#ibcon#ireg 11 cls_cnt 2 2006.203.07:48:30.05#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.203.07:48:30.11#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.203.07:48:30.11#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.203.07:48:30.11#ibcon#enter wrdev, iclass 3, count 2 2006.203.07:48:30.11#ibcon#first serial, iclass 3, count 2 2006.203.07:48:30.11#ibcon#enter sib2, iclass 3, count 2 2006.203.07:48:30.11#ibcon#flushed, iclass 3, count 2 2006.203.07:48:30.11#ibcon#about to write, iclass 3, count 2 2006.203.07:48:30.11#ibcon#wrote, iclass 3, count 2 2006.203.07:48:30.11#ibcon#about to read 3, iclass 3, count 2 2006.203.07:48:30.13#ibcon#read 3, iclass 3, count 2 2006.203.07:48:30.13#ibcon#about to read 4, iclass 3, count 2 2006.203.07:48:30.13#ibcon#read 4, iclass 3, count 2 2006.203.07:48:30.13#ibcon#about to read 5, iclass 3, count 2 2006.203.07:48:30.13#ibcon#read 5, iclass 3, count 2 2006.203.07:48:30.13#ibcon#about to read 6, iclass 3, count 2 2006.203.07:48:30.13#ibcon#read 6, iclass 3, count 2 2006.203.07:48:30.13#ibcon#end of sib2, iclass 3, count 2 2006.203.07:48:30.13#ibcon#*mode == 0, iclass 3, count 2 2006.203.07:48:30.13#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.203.07:48:30.13#ibcon#[25=AT05-07\r\n] 2006.203.07:48:30.13#ibcon#*before write, iclass 3, count 2 2006.203.07:48:30.13#ibcon#enter sib2, iclass 3, count 2 2006.203.07:48:30.13#ibcon#flushed, iclass 3, count 2 2006.203.07:48:30.13#ibcon#about to write, iclass 3, count 2 2006.203.07:48:30.13#ibcon#wrote, iclass 3, count 2 2006.203.07:48:30.13#ibcon#about to read 3, iclass 3, count 2 2006.203.07:48:30.16#ibcon#read 3, iclass 3, count 2 2006.203.07:48:30.16#ibcon#about to read 4, iclass 3, count 2 2006.203.07:48:30.16#ibcon#read 4, iclass 3, count 2 2006.203.07:48:30.16#ibcon#about to read 5, iclass 3, count 2 2006.203.07:48:30.16#ibcon#read 5, iclass 3, count 2 2006.203.07:48:30.16#ibcon#about to read 6, iclass 3, count 2 2006.203.07:48:30.16#ibcon#read 6, iclass 3, count 2 2006.203.07:48:30.16#ibcon#end of sib2, iclass 3, count 2 2006.203.07:48:30.16#ibcon#*after write, iclass 3, count 2 2006.203.07:48:30.16#ibcon#*before return 0, iclass 3, count 2 2006.203.07:48:30.16#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.203.07:48:30.16#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.203.07:48:30.16#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.203.07:48:30.16#ibcon#ireg 7 cls_cnt 0 2006.203.07:48:30.16#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.203.07:48:30.28#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.203.07:48:30.28#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.203.07:48:30.28#ibcon#enter wrdev, iclass 3, count 0 2006.203.07:48:30.28#ibcon#first serial, iclass 3, count 0 2006.203.07:48:30.28#ibcon#enter sib2, iclass 3, count 0 2006.203.07:48:30.28#ibcon#flushed, iclass 3, count 0 2006.203.07:48:30.28#ibcon#about to write, iclass 3, count 0 2006.203.07:48:30.28#ibcon#wrote, iclass 3, count 0 2006.203.07:48:30.28#ibcon#about to read 3, iclass 3, count 0 2006.203.07:48:30.30#ibcon#read 3, iclass 3, count 0 2006.203.07:48:30.30#ibcon#about to read 4, iclass 3, count 0 2006.203.07:48:30.30#ibcon#read 4, iclass 3, count 0 2006.203.07:48:30.30#ibcon#about to read 5, iclass 3, count 0 2006.203.07:48:30.30#ibcon#read 5, iclass 3, count 0 2006.203.07:48:30.30#ibcon#about to read 6, iclass 3, count 0 2006.203.07:48:30.30#ibcon#read 6, iclass 3, count 0 2006.203.07:48:30.30#ibcon#end of sib2, iclass 3, count 0 2006.203.07:48:30.30#ibcon#*mode == 0, iclass 3, count 0 2006.203.07:48:30.30#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.203.07:48:30.30#ibcon#[25=USB\r\n] 2006.203.07:48:30.30#ibcon#*before write, iclass 3, count 0 2006.203.07:48:30.30#ibcon#enter sib2, iclass 3, count 0 2006.203.07:48:30.30#ibcon#flushed, iclass 3, count 0 2006.203.07:48:30.30#ibcon#about to write, iclass 3, count 0 2006.203.07:48:30.30#ibcon#wrote, iclass 3, count 0 2006.203.07:48:30.30#ibcon#about to read 3, iclass 3, count 0 2006.203.07:48:30.33#ibcon#read 3, iclass 3, count 0 2006.203.07:48:30.33#ibcon#about to read 4, iclass 3, count 0 2006.203.07:48:30.33#ibcon#read 4, iclass 3, count 0 2006.203.07:48:30.33#ibcon#about to read 5, iclass 3, count 0 2006.203.07:48:30.33#ibcon#read 5, iclass 3, count 0 2006.203.07:48:30.33#ibcon#about to read 6, iclass 3, count 0 2006.203.07:48:30.33#ibcon#read 6, iclass 3, count 0 2006.203.07:48:30.33#ibcon#end of sib2, iclass 3, count 0 2006.203.07:48:30.33#ibcon#*after write, iclass 3, count 0 2006.203.07:48:30.33#ibcon#*before return 0, iclass 3, count 0 2006.203.07:48:30.33#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.203.07:48:30.33#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.203.07:48:30.33#ibcon#about to clear, iclass 3 cls_cnt 0 2006.203.07:48:30.33#ibcon#cleared, iclass 3 cls_cnt 0 2006.203.07:48:30.33$vc4f8/valo=6,772.99 2006.203.07:48:30.33#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.203.07:48:30.33#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.203.07:48:30.33#ibcon#ireg 17 cls_cnt 0 2006.203.07:48:30.33#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.203.07:48:30.33#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.203.07:48:30.33#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.203.07:48:30.33#ibcon#enter wrdev, iclass 5, count 0 2006.203.07:48:30.33#ibcon#first serial, iclass 5, count 0 2006.203.07:48:30.33#ibcon#enter sib2, iclass 5, count 0 2006.203.07:48:30.33#ibcon#flushed, iclass 5, count 0 2006.203.07:48:30.33#ibcon#about to write, iclass 5, count 0 2006.203.07:48:30.33#ibcon#wrote, iclass 5, count 0 2006.203.07:48:30.33#ibcon#about to read 3, iclass 5, count 0 2006.203.07:48:30.36#ibcon#read 3, iclass 5, count 0 2006.203.07:48:30.36#ibcon#about to read 4, iclass 5, count 0 2006.203.07:48:30.36#ibcon#read 4, iclass 5, count 0 2006.203.07:48:30.36#ibcon#about to read 5, iclass 5, count 0 2006.203.07:48:30.36#ibcon#read 5, iclass 5, count 0 2006.203.07:48:30.36#ibcon#about to read 6, iclass 5, count 0 2006.203.07:48:30.36#ibcon#read 6, iclass 5, count 0 2006.203.07:48:30.36#ibcon#end of sib2, iclass 5, count 0 2006.203.07:48:30.36#ibcon#*mode == 0, iclass 5, count 0 2006.203.07:48:30.36#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.203.07:48:30.36#ibcon#[26=FRQ=06,772.99\r\n] 2006.203.07:48:30.36#ibcon#*before write, iclass 5, count 0 2006.203.07:48:30.36#ibcon#enter sib2, iclass 5, count 0 2006.203.07:48:30.36#ibcon#flushed, iclass 5, count 0 2006.203.07:48:30.36#ibcon#about to write, iclass 5, count 0 2006.203.07:48:30.36#ibcon#wrote, iclass 5, count 0 2006.203.07:48:30.36#ibcon#about to read 3, iclass 5, count 0 2006.203.07:48:30.40#ibcon#read 3, iclass 5, count 0 2006.203.07:48:30.40#ibcon#about to read 4, iclass 5, count 0 2006.203.07:48:30.40#ibcon#read 4, iclass 5, count 0 2006.203.07:48:30.40#ibcon#about to read 5, iclass 5, count 0 2006.203.07:48:30.40#ibcon#read 5, iclass 5, count 0 2006.203.07:48:30.40#ibcon#about to read 6, iclass 5, count 0 2006.203.07:48:30.40#ibcon#read 6, iclass 5, count 0 2006.203.07:48:30.40#ibcon#end of sib2, iclass 5, count 0 2006.203.07:48:30.40#ibcon#*after write, iclass 5, count 0 2006.203.07:48:30.40#ibcon#*before return 0, iclass 5, count 0 2006.203.07:48:30.40#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.203.07:48:30.40#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.203.07:48:30.40#ibcon#about to clear, iclass 5 cls_cnt 0 2006.203.07:48:30.40#ibcon#cleared, iclass 5 cls_cnt 0 2006.203.07:48:30.40$vc4f8/va=6,6 2006.203.07:48:30.40#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.203.07:48:30.40#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.203.07:48:30.40#ibcon#ireg 11 cls_cnt 2 2006.203.07:48:30.40#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.203.07:48:30.45#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.203.07:48:30.45#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.203.07:48:30.45#ibcon#enter wrdev, iclass 7, count 2 2006.203.07:48:30.45#ibcon#first serial, iclass 7, count 2 2006.203.07:48:30.45#ibcon#enter sib2, iclass 7, count 2 2006.203.07:48:30.45#ibcon#flushed, iclass 7, count 2 2006.203.07:48:30.45#ibcon#about to write, iclass 7, count 2 2006.203.07:48:30.45#ibcon#wrote, iclass 7, count 2 2006.203.07:48:30.45#ibcon#about to read 3, iclass 7, count 2 2006.203.07:48:30.47#ibcon#read 3, iclass 7, count 2 2006.203.07:48:30.47#ibcon#about to read 4, iclass 7, count 2 2006.203.07:48:30.47#ibcon#read 4, iclass 7, count 2 2006.203.07:48:30.47#ibcon#about to read 5, iclass 7, count 2 2006.203.07:48:30.47#ibcon#read 5, iclass 7, count 2 2006.203.07:48:30.47#ibcon#about to read 6, iclass 7, count 2 2006.203.07:48:30.47#ibcon#read 6, iclass 7, count 2 2006.203.07:48:30.47#ibcon#end of sib2, iclass 7, count 2 2006.203.07:48:30.47#ibcon#*mode == 0, iclass 7, count 2 2006.203.07:48:30.47#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.203.07:48:30.47#ibcon#[25=AT06-06\r\n] 2006.203.07:48:30.47#ibcon#*before write, iclass 7, count 2 2006.203.07:48:30.47#ibcon#enter sib2, iclass 7, count 2 2006.203.07:48:30.47#ibcon#flushed, iclass 7, count 2 2006.203.07:48:30.47#ibcon#about to write, iclass 7, count 2 2006.203.07:48:30.47#ibcon#wrote, iclass 7, count 2 2006.203.07:48:30.47#ibcon#about to read 3, iclass 7, count 2 2006.203.07:48:30.50#ibcon#read 3, iclass 7, count 2 2006.203.07:48:30.50#ibcon#about to read 4, iclass 7, count 2 2006.203.07:48:30.50#ibcon#read 4, iclass 7, count 2 2006.203.07:48:30.50#ibcon#about to read 5, iclass 7, count 2 2006.203.07:48:30.50#ibcon#read 5, iclass 7, count 2 2006.203.07:48:30.50#ibcon#about to read 6, iclass 7, count 2 2006.203.07:48:30.50#ibcon#read 6, iclass 7, count 2 2006.203.07:48:30.50#ibcon#end of sib2, iclass 7, count 2 2006.203.07:48:30.50#ibcon#*after write, iclass 7, count 2 2006.203.07:48:30.50#ibcon#*before return 0, iclass 7, count 2 2006.203.07:48:30.50#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.203.07:48:30.50#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.203.07:48:30.50#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.203.07:48:30.50#ibcon#ireg 7 cls_cnt 0 2006.203.07:48:30.50#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.203.07:48:30.62#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.203.07:48:30.62#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.203.07:48:30.62#ibcon#enter wrdev, iclass 7, count 0 2006.203.07:48:30.62#ibcon#first serial, iclass 7, count 0 2006.203.07:48:30.62#ibcon#enter sib2, iclass 7, count 0 2006.203.07:48:30.62#ibcon#flushed, iclass 7, count 0 2006.203.07:48:30.62#ibcon#about to write, iclass 7, count 0 2006.203.07:48:30.62#ibcon#wrote, iclass 7, count 0 2006.203.07:48:30.62#ibcon#about to read 3, iclass 7, count 0 2006.203.07:48:30.64#ibcon#read 3, iclass 7, count 0 2006.203.07:48:30.64#ibcon#about to read 4, iclass 7, count 0 2006.203.07:48:30.64#ibcon#read 4, iclass 7, count 0 2006.203.07:48:30.64#ibcon#about to read 5, iclass 7, count 0 2006.203.07:48:30.64#ibcon#read 5, iclass 7, count 0 2006.203.07:48:30.64#ibcon#about to read 6, iclass 7, count 0 2006.203.07:48:30.64#ibcon#read 6, iclass 7, count 0 2006.203.07:48:30.64#ibcon#end of sib2, iclass 7, count 0 2006.203.07:48:30.64#ibcon#*mode == 0, iclass 7, count 0 2006.203.07:48:30.64#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.203.07:48:30.64#ibcon#[25=USB\r\n] 2006.203.07:48:30.64#ibcon#*before write, iclass 7, count 0 2006.203.07:48:30.64#ibcon#enter sib2, iclass 7, count 0 2006.203.07:48:30.64#ibcon#flushed, iclass 7, count 0 2006.203.07:48:30.64#ibcon#about to write, iclass 7, count 0 2006.203.07:48:30.64#ibcon#wrote, iclass 7, count 0 2006.203.07:48:30.64#ibcon#about to read 3, iclass 7, count 0 2006.203.07:48:30.67#ibcon#read 3, iclass 7, count 0 2006.203.07:48:30.67#ibcon#about to read 4, iclass 7, count 0 2006.203.07:48:30.67#ibcon#read 4, iclass 7, count 0 2006.203.07:48:30.67#ibcon#about to read 5, iclass 7, count 0 2006.203.07:48:30.67#ibcon#read 5, iclass 7, count 0 2006.203.07:48:30.67#ibcon#about to read 6, iclass 7, count 0 2006.203.07:48:30.67#ibcon#read 6, iclass 7, count 0 2006.203.07:48:30.67#ibcon#end of sib2, iclass 7, count 0 2006.203.07:48:30.67#ibcon#*after write, iclass 7, count 0 2006.203.07:48:30.67#ibcon#*before return 0, iclass 7, count 0 2006.203.07:48:30.67#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.203.07:48:30.67#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.203.07:48:30.67#ibcon#about to clear, iclass 7 cls_cnt 0 2006.203.07:48:30.67#ibcon#cleared, iclass 7 cls_cnt 0 2006.203.07:48:30.67$vc4f8/valo=7,832.99 2006.203.07:48:30.67#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.203.07:48:30.67#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.203.07:48:30.67#ibcon#ireg 17 cls_cnt 0 2006.203.07:48:30.67#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.203.07:48:30.67#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.203.07:48:30.67#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.203.07:48:30.67#ibcon#enter wrdev, iclass 11, count 0 2006.203.07:48:30.67#ibcon#first serial, iclass 11, count 0 2006.203.07:48:30.67#ibcon#enter sib2, iclass 11, count 0 2006.203.07:48:30.67#ibcon#flushed, iclass 11, count 0 2006.203.07:48:30.67#ibcon#about to write, iclass 11, count 0 2006.203.07:48:30.67#ibcon#wrote, iclass 11, count 0 2006.203.07:48:30.67#ibcon#about to read 3, iclass 11, count 0 2006.203.07:48:30.69#ibcon#read 3, iclass 11, count 0 2006.203.07:48:30.69#ibcon#about to read 4, iclass 11, count 0 2006.203.07:48:30.69#ibcon#read 4, iclass 11, count 0 2006.203.07:48:30.69#ibcon#about to read 5, iclass 11, count 0 2006.203.07:48:30.69#ibcon#read 5, iclass 11, count 0 2006.203.07:48:30.69#ibcon#about to read 6, iclass 11, count 0 2006.203.07:48:30.69#ibcon#read 6, iclass 11, count 0 2006.203.07:48:30.69#ibcon#end of sib2, iclass 11, count 0 2006.203.07:48:30.69#ibcon#*mode == 0, iclass 11, count 0 2006.203.07:48:30.69#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.203.07:48:30.69#ibcon#[26=FRQ=07,832.99\r\n] 2006.203.07:48:30.69#ibcon#*before write, iclass 11, count 0 2006.203.07:48:30.69#ibcon#enter sib2, iclass 11, count 0 2006.203.07:48:30.69#ibcon#flushed, iclass 11, count 0 2006.203.07:48:30.69#ibcon#about to write, iclass 11, count 0 2006.203.07:48:30.69#ibcon#wrote, iclass 11, count 0 2006.203.07:48:30.69#ibcon#about to read 3, iclass 11, count 0 2006.203.07:48:30.73#ibcon#read 3, iclass 11, count 0 2006.203.07:48:30.73#ibcon#about to read 4, iclass 11, count 0 2006.203.07:48:30.73#ibcon#read 4, iclass 11, count 0 2006.203.07:48:30.73#ibcon#about to read 5, iclass 11, count 0 2006.203.07:48:30.73#ibcon#read 5, iclass 11, count 0 2006.203.07:48:30.73#ibcon#about to read 6, iclass 11, count 0 2006.203.07:48:30.73#ibcon#read 6, iclass 11, count 0 2006.203.07:48:30.73#ibcon#end of sib2, iclass 11, count 0 2006.203.07:48:30.73#ibcon#*after write, iclass 11, count 0 2006.203.07:48:30.73#ibcon#*before return 0, iclass 11, count 0 2006.203.07:48:30.73#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.203.07:48:30.73#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.203.07:48:30.73#ibcon#about to clear, iclass 11 cls_cnt 0 2006.203.07:48:30.73#ibcon#cleared, iclass 11 cls_cnt 0 2006.203.07:48:30.73$vc4f8/va=7,7 2006.203.07:48:30.73#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.203.07:48:30.73#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.203.07:48:30.73#ibcon#ireg 11 cls_cnt 2 2006.203.07:48:30.73#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.203.07:48:30.79#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.203.07:48:30.79#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.203.07:48:30.79#ibcon#enter wrdev, iclass 13, count 2 2006.203.07:48:30.79#ibcon#first serial, iclass 13, count 2 2006.203.07:48:30.79#ibcon#enter sib2, iclass 13, count 2 2006.203.07:48:30.79#ibcon#flushed, iclass 13, count 2 2006.203.07:48:30.79#ibcon#about to write, iclass 13, count 2 2006.203.07:48:30.79#ibcon#wrote, iclass 13, count 2 2006.203.07:48:30.79#ibcon#about to read 3, iclass 13, count 2 2006.203.07:48:30.81#ibcon#read 3, iclass 13, count 2 2006.203.07:48:30.81#ibcon#about to read 4, iclass 13, count 2 2006.203.07:48:30.81#ibcon#read 4, iclass 13, count 2 2006.203.07:48:30.81#ibcon#about to read 5, iclass 13, count 2 2006.203.07:48:30.81#ibcon#read 5, iclass 13, count 2 2006.203.07:48:30.81#ibcon#about to read 6, iclass 13, count 2 2006.203.07:48:30.81#ibcon#read 6, iclass 13, count 2 2006.203.07:48:30.81#ibcon#end of sib2, iclass 13, count 2 2006.203.07:48:30.81#ibcon#*mode == 0, iclass 13, count 2 2006.203.07:48:30.81#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.203.07:48:30.81#ibcon#[25=AT07-07\r\n] 2006.203.07:48:30.81#ibcon#*before write, iclass 13, count 2 2006.203.07:48:30.81#ibcon#enter sib2, iclass 13, count 2 2006.203.07:48:30.81#ibcon#flushed, iclass 13, count 2 2006.203.07:48:30.81#ibcon#about to write, iclass 13, count 2 2006.203.07:48:30.81#ibcon#wrote, iclass 13, count 2 2006.203.07:48:30.81#ibcon#about to read 3, iclass 13, count 2 2006.203.07:48:30.84#ibcon#read 3, iclass 13, count 2 2006.203.07:48:30.84#ibcon#about to read 4, iclass 13, count 2 2006.203.07:48:30.84#ibcon#read 4, iclass 13, count 2 2006.203.07:48:30.84#ibcon#about to read 5, iclass 13, count 2 2006.203.07:48:30.84#ibcon#read 5, iclass 13, count 2 2006.203.07:48:30.84#ibcon#about to read 6, iclass 13, count 2 2006.203.07:48:30.84#ibcon#read 6, iclass 13, count 2 2006.203.07:48:30.84#ibcon#end of sib2, iclass 13, count 2 2006.203.07:48:30.84#ibcon#*after write, iclass 13, count 2 2006.203.07:48:30.84#ibcon#*before return 0, iclass 13, count 2 2006.203.07:48:30.84#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.203.07:48:30.84#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.203.07:48:30.84#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.203.07:48:30.84#ibcon#ireg 7 cls_cnt 0 2006.203.07:48:30.84#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.203.07:48:30.96#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.203.07:48:30.96#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.203.07:48:30.96#ibcon#enter wrdev, iclass 13, count 0 2006.203.07:48:30.96#ibcon#first serial, iclass 13, count 0 2006.203.07:48:30.96#ibcon#enter sib2, iclass 13, count 0 2006.203.07:48:30.96#ibcon#flushed, iclass 13, count 0 2006.203.07:48:30.96#ibcon#about to write, iclass 13, count 0 2006.203.07:48:30.96#ibcon#wrote, iclass 13, count 0 2006.203.07:48:30.96#ibcon#about to read 3, iclass 13, count 0 2006.203.07:48:30.98#ibcon#read 3, iclass 13, count 0 2006.203.07:48:30.98#ibcon#about to read 4, iclass 13, count 0 2006.203.07:48:30.98#ibcon#read 4, iclass 13, count 0 2006.203.07:48:30.98#ibcon#about to read 5, iclass 13, count 0 2006.203.07:48:30.98#ibcon#read 5, iclass 13, count 0 2006.203.07:48:30.98#ibcon#about to read 6, iclass 13, count 0 2006.203.07:48:30.98#ibcon#read 6, iclass 13, count 0 2006.203.07:48:30.98#ibcon#end of sib2, iclass 13, count 0 2006.203.07:48:30.98#ibcon#*mode == 0, iclass 13, count 0 2006.203.07:48:30.98#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.203.07:48:30.98#ibcon#[25=USB\r\n] 2006.203.07:48:30.98#ibcon#*before write, iclass 13, count 0 2006.203.07:48:30.98#ibcon#enter sib2, iclass 13, count 0 2006.203.07:48:30.98#ibcon#flushed, iclass 13, count 0 2006.203.07:48:30.98#ibcon#about to write, iclass 13, count 0 2006.203.07:48:30.98#ibcon#wrote, iclass 13, count 0 2006.203.07:48:30.98#ibcon#about to read 3, iclass 13, count 0 2006.203.07:48:31.01#ibcon#read 3, iclass 13, count 0 2006.203.07:48:31.01#ibcon#about to read 4, iclass 13, count 0 2006.203.07:48:31.01#ibcon#read 4, iclass 13, count 0 2006.203.07:48:31.01#ibcon#about to read 5, iclass 13, count 0 2006.203.07:48:31.01#ibcon#read 5, iclass 13, count 0 2006.203.07:48:31.01#ibcon#about to read 6, iclass 13, count 0 2006.203.07:48:31.01#ibcon#read 6, iclass 13, count 0 2006.203.07:48:31.01#ibcon#end of sib2, iclass 13, count 0 2006.203.07:48:31.01#ibcon#*after write, iclass 13, count 0 2006.203.07:48:31.01#ibcon#*before return 0, iclass 13, count 0 2006.203.07:48:31.01#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.203.07:48:31.01#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.203.07:48:31.01#ibcon#about to clear, iclass 13 cls_cnt 0 2006.203.07:48:31.01#ibcon#cleared, iclass 13 cls_cnt 0 2006.203.07:48:31.01$vc4f8/valo=8,852.99 2006.203.07:48:31.01#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.203.07:48:31.01#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.203.07:48:31.01#ibcon#ireg 17 cls_cnt 0 2006.203.07:48:31.01#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.203.07:48:31.01#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.203.07:48:31.01#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.203.07:48:31.01#ibcon#enter wrdev, iclass 15, count 0 2006.203.07:48:31.01#ibcon#first serial, iclass 15, count 0 2006.203.07:48:31.01#ibcon#enter sib2, iclass 15, count 0 2006.203.07:48:31.01#ibcon#flushed, iclass 15, count 0 2006.203.07:48:31.01#ibcon#about to write, iclass 15, count 0 2006.203.07:48:31.01#ibcon#wrote, iclass 15, count 0 2006.203.07:48:31.01#ibcon#about to read 3, iclass 15, count 0 2006.203.07:48:31.04#ibcon#read 3, iclass 15, count 0 2006.203.07:48:31.04#ibcon#about to read 4, iclass 15, count 0 2006.203.07:48:31.04#ibcon#read 4, iclass 15, count 0 2006.203.07:48:31.04#ibcon#about to read 5, iclass 15, count 0 2006.203.07:48:31.04#ibcon#read 5, iclass 15, count 0 2006.203.07:48:31.04#ibcon#about to read 6, iclass 15, count 0 2006.203.07:48:31.04#ibcon#read 6, iclass 15, count 0 2006.203.07:48:31.04#ibcon#end of sib2, iclass 15, count 0 2006.203.07:48:31.04#ibcon#*mode == 0, iclass 15, count 0 2006.203.07:48:31.04#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.203.07:48:31.04#ibcon#[26=FRQ=08,852.99\r\n] 2006.203.07:48:31.04#ibcon#*before write, iclass 15, count 0 2006.203.07:48:31.04#ibcon#enter sib2, iclass 15, count 0 2006.203.07:48:31.04#ibcon#flushed, iclass 15, count 0 2006.203.07:48:31.04#ibcon#about to write, iclass 15, count 0 2006.203.07:48:31.04#ibcon#wrote, iclass 15, count 0 2006.203.07:48:31.04#ibcon#about to read 3, iclass 15, count 0 2006.203.07:48:31.08#ibcon#read 3, iclass 15, count 0 2006.203.07:48:31.08#ibcon#about to read 4, iclass 15, count 0 2006.203.07:48:31.08#ibcon#read 4, iclass 15, count 0 2006.203.07:48:31.08#ibcon#about to read 5, iclass 15, count 0 2006.203.07:48:31.08#ibcon#read 5, iclass 15, count 0 2006.203.07:48:31.08#ibcon#about to read 6, iclass 15, count 0 2006.203.07:48:31.08#ibcon#read 6, iclass 15, count 0 2006.203.07:48:31.08#ibcon#end of sib2, iclass 15, count 0 2006.203.07:48:31.08#ibcon#*after write, iclass 15, count 0 2006.203.07:48:31.08#ibcon#*before return 0, iclass 15, count 0 2006.203.07:48:31.08#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.203.07:48:31.08#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.203.07:48:31.08#ibcon#about to clear, iclass 15 cls_cnt 0 2006.203.07:48:31.08#ibcon#cleared, iclass 15 cls_cnt 0 2006.203.07:48:31.08$vc4f8/va=8,6 2006.203.07:48:31.08#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.203.07:48:31.08#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.203.07:48:31.08#ibcon#ireg 11 cls_cnt 2 2006.203.07:48:31.08#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.203.07:48:31.13#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.203.07:48:31.13#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.203.07:48:31.13#ibcon#enter wrdev, iclass 17, count 2 2006.203.07:48:31.13#ibcon#first serial, iclass 17, count 2 2006.203.07:48:31.13#ibcon#enter sib2, iclass 17, count 2 2006.203.07:48:31.13#ibcon#flushed, iclass 17, count 2 2006.203.07:48:31.13#ibcon#about to write, iclass 17, count 2 2006.203.07:48:31.13#ibcon#wrote, iclass 17, count 2 2006.203.07:48:31.13#ibcon#about to read 3, iclass 17, count 2 2006.203.07:48:31.15#ibcon#read 3, iclass 17, count 2 2006.203.07:48:31.15#ibcon#about to read 4, iclass 17, count 2 2006.203.07:48:31.15#ibcon#read 4, iclass 17, count 2 2006.203.07:48:31.15#ibcon#about to read 5, iclass 17, count 2 2006.203.07:48:31.15#ibcon#read 5, iclass 17, count 2 2006.203.07:48:31.15#ibcon#about to read 6, iclass 17, count 2 2006.203.07:48:31.15#ibcon#read 6, iclass 17, count 2 2006.203.07:48:31.15#ibcon#end of sib2, iclass 17, count 2 2006.203.07:48:31.15#ibcon#*mode == 0, iclass 17, count 2 2006.203.07:48:31.15#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.203.07:48:31.15#ibcon#[25=AT08-06\r\n] 2006.203.07:48:31.15#ibcon#*before write, iclass 17, count 2 2006.203.07:48:31.15#ibcon#enter sib2, iclass 17, count 2 2006.203.07:48:31.15#ibcon#flushed, iclass 17, count 2 2006.203.07:48:31.15#ibcon#about to write, iclass 17, count 2 2006.203.07:48:31.15#ibcon#wrote, iclass 17, count 2 2006.203.07:48:31.15#ibcon#about to read 3, iclass 17, count 2 2006.203.07:48:31.18#ibcon#read 3, iclass 17, count 2 2006.203.07:48:31.18#ibcon#about to read 4, iclass 17, count 2 2006.203.07:48:31.18#ibcon#read 4, iclass 17, count 2 2006.203.07:48:31.18#ibcon#about to read 5, iclass 17, count 2 2006.203.07:48:31.18#ibcon#read 5, iclass 17, count 2 2006.203.07:48:31.18#ibcon#about to read 6, iclass 17, count 2 2006.203.07:48:31.18#ibcon#read 6, iclass 17, count 2 2006.203.07:48:31.18#ibcon#end of sib2, iclass 17, count 2 2006.203.07:48:31.18#ibcon#*after write, iclass 17, count 2 2006.203.07:48:31.18#ibcon#*before return 0, iclass 17, count 2 2006.203.07:48:31.18#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.203.07:48:31.18#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.203.07:48:31.18#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.203.07:48:31.18#ibcon#ireg 7 cls_cnt 0 2006.203.07:48:31.18#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.203.07:48:31.30#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.203.07:48:31.30#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.203.07:48:31.30#ibcon#enter wrdev, iclass 17, count 0 2006.203.07:48:31.30#ibcon#first serial, iclass 17, count 0 2006.203.07:48:31.30#ibcon#enter sib2, iclass 17, count 0 2006.203.07:48:31.30#ibcon#flushed, iclass 17, count 0 2006.203.07:48:31.30#ibcon#about to write, iclass 17, count 0 2006.203.07:48:31.30#ibcon#wrote, iclass 17, count 0 2006.203.07:48:31.30#ibcon#about to read 3, iclass 17, count 0 2006.203.07:48:31.32#ibcon#read 3, iclass 17, count 0 2006.203.07:48:31.32#ibcon#about to read 4, iclass 17, count 0 2006.203.07:48:31.32#ibcon#read 4, iclass 17, count 0 2006.203.07:48:31.32#ibcon#about to read 5, iclass 17, count 0 2006.203.07:48:31.32#ibcon#read 5, iclass 17, count 0 2006.203.07:48:31.32#ibcon#about to read 6, iclass 17, count 0 2006.203.07:48:31.32#ibcon#read 6, iclass 17, count 0 2006.203.07:48:31.32#ibcon#end of sib2, iclass 17, count 0 2006.203.07:48:31.32#ibcon#*mode == 0, iclass 17, count 0 2006.203.07:48:31.32#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.203.07:48:31.32#ibcon#[25=USB\r\n] 2006.203.07:48:31.32#ibcon#*before write, iclass 17, count 0 2006.203.07:48:31.32#ibcon#enter sib2, iclass 17, count 0 2006.203.07:48:31.32#ibcon#flushed, iclass 17, count 0 2006.203.07:48:31.32#ibcon#about to write, iclass 17, count 0 2006.203.07:48:31.32#ibcon#wrote, iclass 17, count 0 2006.203.07:48:31.32#ibcon#about to read 3, iclass 17, count 0 2006.203.07:48:31.35#ibcon#read 3, iclass 17, count 0 2006.203.07:48:31.35#ibcon#about to read 4, iclass 17, count 0 2006.203.07:48:31.35#ibcon#read 4, iclass 17, count 0 2006.203.07:48:31.35#ibcon#about to read 5, iclass 17, count 0 2006.203.07:48:31.35#ibcon#read 5, iclass 17, count 0 2006.203.07:48:31.35#ibcon#about to read 6, iclass 17, count 0 2006.203.07:48:31.35#ibcon#read 6, iclass 17, count 0 2006.203.07:48:31.35#ibcon#end of sib2, iclass 17, count 0 2006.203.07:48:31.35#ibcon#*after write, iclass 17, count 0 2006.203.07:48:31.35#ibcon#*before return 0, iclass 17, count 0 2006.203.07:48:31.35#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.203.07:48:31.35#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.203.07:48:31.35#ibcon#about to clear, iclass 17 cls_cnt 0 2006.203.07:48:31.35#ibcon#cleared, iclass 17 cls_cnt 0 2006.203.07:48:31.35$vc4f8/vblo=1,632.99 2006.203.07:48:31.35#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.203.07:48:31.35#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.203.07:48:31.35#ibcon#ireg 17 cls_cnt 0 2006.203.07:48:31.35#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.203.07:48:31.35#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.203.07:48:31.35#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.203.07:48:31.35#ibcon#enter wrdev, iclass 19, count 0 2006.203.07:48:31.35#ibcon#first serial, iclass 19, count 0 2006.203.07:48:31.35#ibcon#enter sib2, iclass 19, count 0 2006.203.07:48:31.35#ibcon#flushed, iclass 19, count 0 2006.203.07:48:31.35#ibcon#about to write, iclass 19, count 0 2006.203.07:48:31.35#ibcon#wrote, iclass 19, count 0 2006.203.07:48:31.35#ibcon#about to read 3, iclass 19, count 0 2006.203.07:48:31.37#ibcon#read 3, iclass 19, count 0 2006.203.07:48:31.37#ibcon#about to read 4, iclass 19, count 0 2006.203.07:48:31.37#ibcon#read 4, iclass 19, count 0 2006.203.07:48:31.37#ibcon#about to read 5, iclass 19, count 0 2006.203.07:48:31.37#ibcon#read 5, iclass 19, count 0 2006.203.07:48:31.37#ibcon#about to read 6, iclass 19, count 0 2006.203.07:48:31.37#ibcon#read 6, iclass 19, count 0 2006.203.07:48:31.37#ibcon#end of sib2, iclass 19, count 0 2006.203.07:48:31.37#ibcon#*mode == 0, iclass 19, count 0 2006.203.07:48:31.37#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.203.07:48:31.37#ibcon#[28=FRQ=01,632.99\r\n] 2006.203.07:48:31.37#ibcon#*before write, iclass 19, count 0 2006.203.07:48:31.37#ibcon#enter sib2, iclass 19, count 0 2006.203.07:48:31.37#ibcon#flushed, iclass 19, count 0 2006.203.07:48:31.37#ibcon#about to write, iclass 19, count 0 2006.203.07:48:31.37#ibcon#wrote, iclass 19, count 0 2006.203.07:48:31.37#ibcon#about to read 3, iclass 19, count 0 2006.203.07:48:31.41#ibcon#read 3, iclass 19, count 0 2006.203.07:48:31.41#ibcon#about to read 4, iclass 19, count 0 2006.203.07:48:31.41#ibcon#read 4, iclass 19, count 0 2006.203.07:48:31.41#ibcon#about to read 5, iclass 19, count 0 2006.203.07:48:31.41#ibcon#read 5, iclass 19, count 0 2006.203.07:48:31.41#ibcon#about to read 6, iclass 19, count 0 2006.203.07:48:31.41#ibcon#read 6, iclass 19, count 0 2006.203.07:48:31.41#ibcon#end of sib2, iclass 19, count 0 2006.203.07:48:31.41#ibcon#*after write, iclass 19, count 0 2006.203.07:48:31.41#ibcon#*before return 0, iclass 19, count 0 2006.203.07:48:31.41#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.203.07:48:31.41#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.203.07:48:31.41#ibcon#about to clear, iclass 19 cls_cnt 0 2006.203.07:48:31.41#ibcon#cleared, iclass 19 cls_cnt 0 2006.203.07:48:31.41$vc4f8/vb=1,4 2006.203.07:48:31.41#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.203.07:48:31.41#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.203.07:48:31.41#ibcon#ireg 11 cls_cnt 2 2006.203.07:48:31.41#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.203.07:48:31.41#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.203.07:48:31.41#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.203.07:48:31.41#ibcon#enter wrdev, iclass 21, count 2 2006.203.07:48:31.41#ibcon#first serial, iclass 21, count 2 2006.203.07:48:31.41#ibcon#enter sib2, iclass 21, count 2 2006.203.07:48:31.41#ibcon#flushed, iclass 21, count 2 2006.203.07:48:31.41#ibcon#about to write, iclass 21, count 2 2006.203.07:48:31.41#ibcon#wrote, iclass 21, count 2 2006.203.07:48:31.41#ibcon#about to read 3, iclass 21, count 2 2006.203.07:48:31.43#ibcon#read 3, iclass 21, count 2 2006.203.07:48:31.43#ibcon#about to read 4, iclass 21, count 2 2006.203.07:48:31.43#ibcon#read 4, iclass 21, count 2 2006.203.07:48:31.43#ibcon#about to read 5, iclass 21, count 2 2006.203.07:48:31.43#ibcon#read 5, iclass 21, count 2 2006.203.07:48:31.43#ibcon#about to read 6, iclass 21, count 2 2006.203.07:48:31.43#ibcon#read 6, iclass 21, count 2 2006.203.07:48:31.43#ibcon#end of sib2, iclass 21, count 2 2006.203.07:48:31.43#ibcon#*mode == 0, iclass 21, count 2 2006.203.07:48:31.43#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.203.07:48:31.43#ibcon#[27=AT01-04\r\n] 2006.203.07:48:31.43#ibcon#*before write, iclass 21, count 2 2006.203.07:48:31.43#ibcon#enter sib2, iclass 21, count 2 2006.203.07:48:31.43#ibcon#flushed, iclass 21, count 2 2006.203.07:48:31.43#ibcon#about to write, iclass 21, count 2 2006.203.07:48:31.43#ibcon#wrote, iclass 21, count 2 2006.203.07:48:31.43#ibcon#about to read 3, iclass 21, count 2 2006.203.07:48:31.46#ibcon#read 3, iclass 21, count 2 2006.203.07:48:31.46#ibcon#about to read 4, iclass 21, count 2 2006.203.07:48:31.46#ibcon#read 4, iclass 21, count 2 2006.203.07:48:31.46#ibcon#about to read 5, iclass 21, count 2 2006.203.07:48:31.46#ibcon#read 5, iclass 21, count 2 2006.203.07:48:31.46#ibcon#about to read 6, iclass 21, count 2 2006.203.07:48:31.46#ibcon#read 6, iclass 21, count 2 2006.203.07:48:31.46#ibcon#end of sib2, iclass 21, count 2 2006.203.07:48:31.46#ibcon#*after write, iclass 21, count 2 2006.203.07:48:31.46#ibcon#*before return 0, iclass 21, count 2 2006.203.07:48:31.46#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.203.07:48:31.46#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.203.07:48:31.46#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.203.07:48:31.46#ibcon#ireg 7 cls_cnt 0 2006.203.07:48:31.46#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.203.07:48:31.58#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.203.07:48:31.58#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.203.07:48:31.58#ibcon#enter wrdev, iclass 21, count 0 2006.203.07:48:31.58#ibcon#first serial, iclass 21, count 0 2006.203.07:48:31.58#ibcon#enter sib2, iclass 21, count 0 2006.203.07:48:31.58#ibcon#flushed, iclass 21, count 0 2006.203.07:48:31.58#ibcon#about to write, iclass 21, count 0 2006.203.07:48:31.58#ibcon#wrote, iclass 21, count 0 2006.203.07:48:31.58#ibcon#about to read 3, iclass 21, count 0 2006.203.07:48:31.60#ibcon#read 3, iclass 21, count 0 2006.203.07:48:31.60#ibcon#about to read 4, iclass 21, count 0 2006.203.07:48:31.60#ibcon#read 4, iclass 21, count 0 2006.203.07:48:31.60#ibcon#about to read 5, iclass 21, count 0 2006.203.07:48:31.60#ibcon#read 5, iclass 21, count 0 2006.203.07:48:31.60#ibcon#about to read 6, iclass 21, count 0 2006.203.07:48:31.60#ibcon#read 6, iclass 21, count 0 2006.203.07:48:31.60#ibcon#end of sib2, iclass 21, count 0 2006.203.07:48:31.60#ibcon#*mode == 0, iclass 21, count 0 2006.203.07:48:31.60#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.203.07:48:31.60#ibcon#[27=USB\r\n] 2006.203.07:48:31.60#ibcon#*before write, iclass 21, count 0 2006.203.07:48:31.60#ibcon#enter sib2, iclass 21, count 0 2006.203.07:48:31.60#ibcon#flushed, iclass 21, count 0 2006.203.07:48:31.60#ibcon#about to write, iclass 21, count 0 2006.203.07:48:31.60#ibcon#wrote, iclass 21, count 0 2006.203.07:48:31.60#ibcon#about to read 3, iclass 21, count 0 2006.203.07:48:31.63#ibcon#read 3, iclass 21, count 0 2006.203.07:48:31.63#ibcon#about to read 4, iclass 21, count 0 2006.203.07:48:31.63#ibcon#read 4, iclass 21, count 0 2006.203.07:48:31.63#ibcon#about to read 5, iclass 21, count 0 2006.203.07:48:31.63#ibcon#read 5, iclass 21, count 0 2006.203.07:48:31.63#ibcon#about to read 6, iclass 21, count 0 2006.203.07:48:31.63#ibcon#read 6, iclass 21, count 0 2006.203.07:48:31.63#ibcon#end of sib2, iclass 21, count 0 2006.203.07:48:31.63#ibcon#*after write, iclass 21, count 0 2006.203.07:48:31.63#ibcon#*before return 0, iclass 21, count 0 2006.203.07:48:31.63#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.203.07:48:31.63#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.203.07:48:31.63#ibcon#about to clear, iclass 21 cls_cnt 0 2006.203.07:48:31.63#ibcon#cleared, iclass 21 cls_cnt 0 2006.203.07:48:31.63$vc4f8/vblo=2,640.99 2006.203.07:48:31.63#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.203.07:48:31.63#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.203.07:48:31.63#ibcon#ireg 17 cls_cnt 0 2006.203.07:48:31.63#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.203.07:48:31.63#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.203.07:48:31.63#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.203.07:48:31.63#ibcon#enter wrdev, iclass 23, count 0 2006.203.07:48:31.63#ibcon#first serial, iclass 23, count 0 2006.203.07:48:31.63#ibcon#enter sib2, iclass 23, count 0 2006.203.07:48:31.63#ibcon#flushed, iclass 23, count 0 2006.203.07:48:31.63#ibcon#about to write, iclass 23, count 0 2006.203.07:48:31.63#ibcon#wrote, iclass 23, count 0 2006.203.07:48:31.63#ibcon#about to read 3, iclass 23, count 0 2006.203.07:48:31.66#ibcon#read 3, iclass 23, count 0 2006.203.07:48:31.66#ibcon#about to read 4, iclass 23, count 0 2006.203.07:48:31.66#ibcon#read 4, iclass 23, count 0 2006.203.07:48:31.66#ibcon#about to read 5, iclass 23, count 0 2006.203.07:48:31.66#ibcon#read 5, iclass 23, count 0 2006.203.07:48:31.66#ibcon#about to read 6, iclass 23, count 0 2006.203.07:48:31.66#ibcon#read 6, iclass 23, count 0 2006.203.07:48:31.66#ibcon#end of sib2, iclass 23, count 0 2006.203.07:48:31.66#ibcon#*mode == 0, iclass 23, count 0 2006.203.07:48:31.66#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.203.07:48:31.66#ibcon#[28=FRQ=02,640.99\r\n] 2006.203.07:48:31.66#ibcon#*before write, iclass 23, count 0 2006.203.07:48:31.66#ibcon#enter sib2, iclass 23, count 0 2006.203.07:48:31.66#ibcon#flushed, iclass 23, count 0 2006.203.07:48:31.66#ibcon#about to write, iclass 23, count 0 2006.203.07:48:31.66#ibcon#wrote, iclass 23, count 0 2006.203.07:48:31.66#ibcon#about to read 3, iclass 23, count 0 2006.203.07:48:31.70#ibcon#read 3, iclass 23, count 0 2006.203.07:48:31.70#ibcon#about to read 4, iclass 23, count 0 2006.203.07:48:31.70#ibcon#read 4, iclass 23, count 0 2006.203.07:48:31.70#ibcon#about to read 5, iclass 23, count 0 2006.203.07:48:31.70#ibcon#read 5, iclass 23, count 0 2006.203.07:48:31.70#ibcon#about to read 6, iclass 23, count 0 2006.203.07:48:31.70#ibcon#read 6, iclass 23, count 0 2006.203.07:48:31.70#ibcon#end of sib2, iclass 23, count 0 2006.203.07:48:31.70#ibcon#*after write, iclass 23, count 0 2006.203.07:48:31.70#ibcon#*before return 0, iclass 23, count 0 2006.203.07:48:31.70#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.203.07:48:31.70#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.203.07:48:31.70#ibcon#about to clear, iclass 23 cls_cnt 0 2006.203.07:48:31.70#ibcon#cleared, iclass 23 cls_cnt 0 2006.203.07:48:31.70$vc4f8/vb=2,4 2006.203.07:48:31.70#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.203.07:48:31.70#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.203.07:48:31.70#ibcon#ireg 11 cls_cnt 2 2006.203.07:48:31.70#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.203.07:48:31.75#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.203.07:48:31.75#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.203.07:48:31.75#ibcon#enter wrdev, iclass 25, count 2 2006.203.07:48:31.75#ibcon#first serial, iclass 25, count 2 2006.203.07:48:31.75#ibcon#enter sib2, iclass 25, count 2 2006.203.07:48:31.75#ibcon#flushed, iclass 25, count 2 2006.203.07:48:31.75#ibcon#about to write, iclass 25, count 2 2006.203.07:48:31.75#ibcon#wrote, iclass 25, count 2 2006.203.07:48:31.75#ibcon#about to read 3, iclass 25, count 2 2006.203.07:48:31.77#ibcon#read 3, iclass 25, count 2 2006.203.07:48:31.77#ibcon#about to read 4, iclass 25, count 2 2006.203.07:48:31.77#ibcon#read 4, iclass 25, count 2 2006.203.07:48:31.77#ibcon#about to read 5, iclass 25, count 2 2006.203.07:48:31.77#ibcon#read 5, iclass 25, count 2 2006.203.07:48:31.77#ibcon#about to read 6, iclass 25, count 2 2006.203.07:48:31.77#ibcon#read 6, iclass 25, count 2 2006.203.07:48:31.77#ibcon#end of sib2, iclass 25, count 2 2006.203.07:48:31.77#ibcon#*mode == 0, iclass 25, count 2 2006.203.07:48:31.77#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.203.07:48:31.77#ibcon#[27=AT02-04\r\n] 2006.203.07:48:31.77#ibcon#*before write, iclass 25, count 2 2006.203.07:48:31.77#ibcon#enter sib2, iclass 25, count 2 2006.203.07:48:31.77#ibcon#flushed, iclass 25, count 2 2006.203.07:48:31.77#ibcon#about to write, iclass 25, count 2 2006.203.07:48:31.77#ibcon#wrote, iclass 25, count 2 2006.203.07:48:31.77#ibcon#about to read 3, iclass 25, count 2 2006.203.07:48:31.80#ibcon#read 3, iclass 25, count 2 2006.203.07:48:31.80#ibcon#about to read 4, iclass 25, count 2 2006.203.07:48:31.80#ibcon#read 4, iclass 25, count 2 2006.203.07:48:31.80#ibcon#about to read 5, iclass 25, count 2 2006.203.07:48:31.80#ibcon#read 5, iclass 25, count 2 2006.203.07:48:31.80#ibcon#about to read 6, iclass 25, count 2 2006.203.07:48:31.80#ibcon#read 6, iclass 25, count 2 2006.203.07:48:31.80#ibcon#end of sib2, iclass 25, count 2 2006.203.07:48:31.80#ibcon#*after write, iclass 25, count 2 2006.203.07:48:31.80#ibcon#*before return 0, iclass 25, count 2 2006.203.07:48:31.80#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.203.07:48:31.80#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.203.07:48:31.80#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.203.07:48:31.80#ibcon#ireg 7 cls_cnt 0 2006.203.07:48:31.80#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.203.07:48:31.92#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.203.07:48:31.92#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.203.07:48:31.92#ibcon#enter wrdev, iclass 25, count 0 2006.203.07:48:31.92#ibcon#first serial, iclass 25, count 0 2006.203.07:48:31.92#ibcon#enter sib2, iclass 25, count 0 2006.203.07:48:31.92#ibcon#flushed, iclass 25, count 0 2006.203.07:48:31.92#ibcon#about to write, iclass 25, count 0 2006.203.07:48:31.92#ibcon#wrote, iclass 25, count 0 2006.203.07:48:31.92#ibcon#about to read 3, iclass 25, count 0 2006.203.07:48:31.94#ibcon#read 3, iclass 25, count 0 2006.203.07:48:31.94#ibcon#about to read 4, iclass 25, count 0 2006.203.07:48:31.94#ibcon#read 4, iclass 25, count 0 2006.203.07:48:31.94#ibcon#about to read 5, iclass 25, count 0 2006.203.07:48:31.94#ibcon#read 5, iclass 25, count 0 2006.203.07:48:31.94#ibcon#about to read 6, iclass 25, count 0 2006.203.07:48:31.94#ibcon#read 6, iclass 25, count 0 2006.203.07:48:31.94#ibcon#end of sib2, iclass 25, count 0 2006.203.07:48:31.94#ibcon#*mode == 0, iclass 25, count 0 2006.203.07:48:31.94#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.203.07:48:31.94#ibcon#[27=USB\r\n] 2006.203.07:48:31.94#ibcon#*before write, iclass 25, count 0 2006.203.07:48:31.94#ibcon#enter sib2, iclass 25, count 0 2006.203.07:48:31.94#ibcon#flushed, iclass 25, count 0 2006.203.07:48:31.94#ibcon#about to write, iclass 25, count 0 2006.203.07:48:31.94#ibcon#wrote, iclass 25, count 0 2006.203.07:48:31.94#ibcon#about to read 3, iclass 25, count 0 2006.203.07:48:31.97#ibcon#read 3, iclass 25, count 0 2006.203.07:48:31.97#ibcon#about to read 4, iclass 25, count 0 2006.203.07:48:31.97#ibcon#read 4, iclass 25, count 0 2006.203.07:48:31.97#ibcon#about to read 5, iclass 25, count 0 2006.203.07:48:31.97#ibcon#read 5, iclass 25, count 0 2006.203.07:48:31.97#ibcon#about to read 6, iclass 25, count 0 2006.203.07:48:31.97#ibcon#read 6, iclass 25, count 0 2006.203.07:48:31.97#ibcon#end of sib2, iclass 25, count 0 2006.203.07:48:31.97#ibcon#*after write, iclass 25, count 0 2006.203.07:48:31.97#ibcon#*before return 0, iclass 25, count 0 2006.203.07:48:31.97#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.203.07:48:31.97#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.203.07:48:31.97#ibcon#about to clear, iclass 25 cls_cnt 0 2006.203.07:48:31.97#ibcon#cleared, iclass 25 cls_cnt 0 2006.203.07:48:31.97$vc4f8/vblo=3,656.99 2006.203.07:48:31.97#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.203.07:48:31.97#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.203.07:48:31.97#ibcon#ireg 17 cls_cnt 0 2006.203.07:48:31.97#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:48:31.97#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:48:31.97#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:48:31.97#ibcon#enter wrdev, iclass 27, count 0 2006.203.07:48:31.97#ibcon#first serial, iclass 27, count 0 2006.203.07:48:31.97#ibcon#enter sib2, iclass 27, count 0 2006.203.07:48:31.97#ibcon#flushed, iclass 27, count 0 2006.203.07:48:31.97#ibcon#about to write, iclass 27, count 0 2006.203.07:48:31.97#ibcon#wrote, iclass 27, count 0 2006.203.07:48:31.97#ibcon#about to read 3, iclass 27, count 0 2006.203.07:48:31.99#ibcon#read 3, iclass 27, count 0 2006.203.07:48:31.99#ibcon#about to read 4, iclass 27, count 0 2006.203.07:48:31.99#ibcon#read 4, iclass 27, count 0 2006.203.07:48:31.99#ibcon#about to read 5, iclass 27, count 0 2006.203.07:48:31.99#ibcon#read 5, iclass 27, count 0 2006.203.07:48:31.99#ibcon#about to read 6, iclass 27, count 0 2006.203.07:48:31.99#ibcon#read 6, iclass 27, count 0 2006.203.07:48:31.99#ibcon#end of sib2, iclass 27, count 0 2006.203.07:48:31.99#ibcon#*mode == 0, iclass 27, count 0 2006.203.07:48:31.99#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.203.07:48:31.99#ibcon#[28=FRQ=03,656.99\r\n] 2006.203.07:48:31.99#ibcon#*before write, iclass 27, count 0 2006.203.07:48:31.99#ibcon#enter sib2, iclass 27, count 0 2006.203.07:48:31.99#ibcon#flushed, iclass 27, count 0 2006.203.07:48:31.99#ibcon#about to write, iclass 27, count 0 2006.203.07:48:31.99#ibcon#wrote, iclass 27, count 0 2006.203.07:48:31.99#ibcon#about to read 3, iclass 27, count 0 2006.203.07:48:32.03#ibcon#read 3, iclass 27, count 0 2006.203.07:48:32.03#ibcon#about to read 4, iclass 27, count 0 2006.203.07:48:32.03#ibcon#read 4, iclass 27, count 0 2006.203.07:48:32.03#ibcon#about to read 5, iclass 27, count 0 2006.203.07:48:32.03#ibcon#read 5, iclass 27, count 0 2006.203.07:48:32.03#ibcon#about to read 6, iclass 27, count 0 2006.203.07:48:32.03#ibcon#read 6, iclass 27, count 0 2006.203.07:48:32.03#ibcon#end of sib2, iclass 27, count 0 2006.203.07:48:32.03#ibcon#*after write, iclass 27, count 0 2006.203.07:48:32.03#ibcon#*before return 0, iclass 27, count 0 2006.203.07:48:32.03#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:48:32.03#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:48:32.03#ibcon#about to clear, iclass 27 cls_cnt 0 2006.203.07:48:32.03#ibcon#cleared, iclass 27 cls_cnt 0 2006.203.07:48:32.03$vc4f8/vb=3,4 2006.203.07:48:32.03#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.203.07:48:32.03#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.203.07:48:32.03#ibcon#ireg 11 cls_cnt 2 2006.203.07:48:32.03#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.203.07:48:32.09#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.203.07:48:32.09#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.203.07:48:32.09#ibcon#enter wrdev, iclass 29, count 2 2006.203.07:48:32.09#ibcon#first serial, iclass 29, count 2 2006.203.07:48:32.09#ibcon#enter sib2, iclass 29, count 2 2006.203.07:48:32.09#ibcon#flushed, iclass 29, count 2 2006.203.07:48:32.09#ibcon#about to write, iclass 29, count 2 2006.203.07:48:32.09#ibcon#wrote, iclass 29, count 2 2006.203.07:48:32.09#ibcon#about to read 3, iclass 29, count 2 2006.203.07:48:32.11#ibcon#read 3, iclass 29, count 2 2006.203.07:48:32.11#ibcon#about to read 4, iclass 29, count 2 2006.203.07:48:32.11#ibcon#read 4, iclass 29, count 2 2006.203.07:48:32.11#ibcon#about to read 5, iclass 29, count 2 2006.203.07:48:32.11#ibcon#read 5, iclass 29, count 2 2006.203.07:48:32.11#ibcon#about to read 6, iclass 29, count 2 2006.203.07:48:32.11#ibcon#read 6, iclass 29, count 2 2006.203.07:48:32.11#ibcon#end of sib2, iclass 29, count 2 2006.203.07:48:32.11#ibcon#*mode == 0, iclass 29, count 2 2006.203.07:48:32.11#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.203.07:48:32.11#ibcon#[27=AT03-04\r\n] 2006.203.07:48:32.11#ibcon#*before write, iclass 29, count 2 2006.203.07:48:32.11#ibcon#enter sib2, iclass 29, count 2 2006.203.07:48:32.11#ibcon#flushed, iclass 29, count 2 2006.203.07:48:32.11#ibcon#about to write, iclass 29, count 2 2006.203.07:48:32.11#ibcon#wrote, iclass 29, count 2 2006.203.07:48:32.11#ibcon#about to read 3, iclass 29, count 2 2006.203.07:48:32.14#ibcon#read 3, iclass 29, count 2 2006.203.07:48:32.14#ibcon#about to read 4, iclass 29, count 2 2006.203.07:48:32.14#ibcon#read 4, iclass 29, count 2 2006.203.07:48:32.14#ibcon#about to read 5, iclass 29, count 2 2006.203.07:48:32.14#ibcon#read 5, iclass 29, count 2 2006.203.07:48:32.14#ibcon#about to read 6, iclass 29, count 2 2006.203.07:48:32.14#ibcon#read 6, iclass 29, count 2 2006.203.07:48:32.14#ibcon#end of sib2, iclass 29, count 2 2006.203.07:48:32.14#ibcon#*after write, iclass 29, count 2 2006.203.07:48:32.14#ibcon#*before return 0, iclass 29, count 2 2006.203.07:48:32.14#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.203.07:48:32.14#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.203.07:48:32.14#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.203.07:48:32.14#ibcon#ireg 7 cls_cnt 0 2006.203.07:48:32.14#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.203.07:48:32.26#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.203.07:48:32.26#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.203.07:48:32.26#ibcon#enter wrdev, iclass 29, count 0 2006.203.07:48:32.26#ibcon#first serial, iclass 29, count 0 2006.203.07:48:32.26#ibcon#enter sib2, iclass 29, count 0 2006.203.07:48:32.26#ibcon#flushed, iclass 29, count 0 2006.203.07:48:32.26#ibcon#about to write, iclass 29, count 0 2006.203.07:48:32.26#ibcon#wrote, iclass 29, count 0 2006.203.07:48:32.26#ibcon#about to read 3, iclass 29, count 0 2006.203.07:48:32.28#ibcon#read 3, iclass 29, count 0 2006.203.07:48:32.28#ibcon#about to read 4, iclass 29, count 0 2006.203.07:48:32.28#ibcon#read 4, iclass 29, count 0 2006.203.07:48:32.28#ibcon#about to read 5, iclass 29, count 0 2006.203.07:48:32.28#ibcon#read 5, iclass 29, count 0 2006.203.07:48:32.28#ibcon#about to read 6, iclass 29, count 0 2006.203.07:48:32.28#ibcon#read 6, iclass 29, count 0 2006.203.07:48:32.28#ibcon#end of sib2, iclass 29, count 0 2006.203.07:48:32.28#ibcon#*mode == 0, iclass 29, count 0 2006.203.07:48:32.28#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.203.07:48:32.28#ibcon#[27=USB\r\n] 2006.203.07:48:32.28#ibcon#*before write, iclass 29, count 0 2006.203.07:48:32.28#ibcon#enter sib2, iclass 29, count 0 2006.203.07:48:32.28#ibcon#flushed, iclass 29, count 0 2006.203.07:48:32.28#ibcon#about to write, iclass 29, count 0 2006.203.07:48:32.28#ibcon#wrote, iclass 29, count 0 2006.203.07:48:32.28#ibcon#about to read 3, iclass 29, count 0 2006.203.07:48:32.31#ibcon#read 3, iclass 29, count 0 2006.203.07:48:32.31#ibcon#about to read 4, iclass 29, count 0 2006.203.07:48:32.31#ibcon#read 4, iclass 29, count 0 2006.203.07:48:32.31#ibcon#about to read 5, iclass 29, count 0 2006.203.07:48:32.31#ibcon#read 5, iclass 29, count 0 2006.203.07:48:32.31#ibcon#about to read 6, iclass 29, count 0 2006.203.07:48:32.31#ibcon#read 6, iclass 29, count 0 2006.203.07:48:32.31#ibcon#end of sib2, iclass 29, count 0 2006.203.07:48:32.31#ibcon#*after write, iclass 29, count 0 2006.203.07:48:32.31#ibcon#*before return 0, iclass 29, count 0 2006.203.07:48:32.31#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.203.07:48:32.31#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.203.07:48:32.31#ibcon#about to clear, iclass 29 cls_cnt 0 2006.203.07:48:32.31#ibcon#cleared, iclass 29 cls_cnt 0 2006.203.07:48:32.31$vc4f8/vblo=4,712.99 2006.203.07:48:32.31#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.203.07:48:32.31#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.203.07:48:32.31#ibcon#ireg 17 cls_cnt 0 2006.203.07:48:32.31#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.203.07:48:32.31#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.203.07:48:32.31#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.203.07:48:32.31#ibcon#enter wrdev, iclass 31, count 0 2006.203.07:48:32.31#ibcon#first serial, iclass 31, count 0 2006.203.07:48:32.31#ibcon#enter sib2, iclass 31, count 0 2006.203.07:48:32.31#ibcon#flushed, iclass 31, count 0 2006.203.07:48:32.31#ibcon#about to write, iclass 31, count 0 2006.203.07:48:32.31#ibcon#wrote, iclass 31, count 0 2006.203.07:48:32.31#ibcon#about to read 3, iclass 31, count 0 2006.203.07:48:32.34#ibcon#read 3, iclass 31, count 0 2006.203.07:48:32.34#ibcon#about to read 4, iclass 31, count 0 2006.203.07:48:32.34#ibcon#read 4, iclass 31, count 0 2006.203.07:48:32.34#ibcon#about to read 5, iclass 31, count 0 2006.203.07:48:32.34#ibcon#read 5, iclass 31, count 0 2006.203.07:48:32.34#ibcon#about to read 6, iclass 31, count 0 2006.203.07:48:32.34#ibcon#read 6, iclass 31, count 0 2006.203.07:48:32.34#ibcon#end of sib2, iclass 31, count 0 2006.203.07:48:32.34#ibcon#*mode == 0, iclass 31, count 0 2006.203.07:48:32.34#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.203.07:48:32.34#ibcon#[28=FRQ=04,712.99\r\n] 2006.203.07:48:32.34#ibcon#*before write, iclass 31, count 0 2006.203.07:48:32.34#ibcon#enter sib2, iclass 31, count 0 2006.203.07:48:32.34#ibcon#flushed, iclass 31, count 0 2006.203.07:48:32.34#ibcon#about to write, iclass 31, count 0 2006.203.07:48:32.34#ibcon#wrote, iclass 31, count 0 2006.203.07:48:32.34#ibcon#about to read 3, iclass 31, count 0 2006.203.07:48:32.38#ibcon#read 3, iclass 31, count 0 2006.203.07:48:32.38#ibcon#about to read 4, iclass 31, count 0 2006.203.07:48:32.38#ibcon#read 4, iclass 31, count 0 2006.203.07:48:32.38#ibcon#about to read 5, iclass 31, count 0 2006.203.07:48:32.38#ibcon#read 5, iclass 31, count 0 2006.203.07:48:32.38#ibcon#about to read 6, iclass 31, count 0 2006.203.07:48:32.38#ibcon#read 6, iclass 31, count 0 2006.203.07:48:32.38#ibcon#end of sib2, iclass 31, count 0 2006.203.07:48:32.38#ibcon#*after write, iclass 31, count 0 2006.203.07:48:32.38#ibcon#*before return 0, iclass 31, count 0 2006.203.07:48:32.38#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.203.07:48:32.38#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.203.07:48:32.38#ibcon#about to clear, iclass 31 cls_cnt 0 2006.203.07:48:32.38#ibcon#cleared, iclass 31 cls_cnt 0 2006.203.07:48:32.38$vc4f8/vb=4,4 2006.203.07:48:32.38#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.203.07:48:32.38#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.203.07:48:32.38#ibcon#ireg 11 cls_cnt 2 2006.203.07:48:32.38#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.203.07:48:32.43#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.203.07:48:32.43#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.203.07:48:32.43#ibcon#enter wrdev, iclass 33, count 2 2006.203.07:48:32.43#ibcon#first serial, iclass 33, count 2 2006.203.07:48:32.43#ibcon#enter sib2, iclass 33, count 2 2006.203.07:48:32.43#ibcon#flushed, iclass 33, count 2 2006.203.07:48:32.43#ibcon#about to write, iclass 33, count 2 2006.203.07:48:32.43#ibcon#wrote, iclass 33, count 2 2006.203.07:48:32.43#ibcon#about to read 3, iclass 33, count 2 2006.203.07:48:32.45#ibcon#read 3, iclass 33, count 2 2006.203.07:48:32.45#ibcon#about to read 4, iclass 33, count 2 2006.203.07:48:32.45#ibcon#read 4, iclass 33, count 2 2006.203.07:48:32.45#ibcon#about to read 5, iclass 33, count 2 2006.203.07:48:32.45#ibcon#read 5, iclass 33, count 2 2006.203.07:48:32.45#ibcon#about to read 6, iclass 33, count 2 2006.203.07:48:32.45#ibcon#read 6, iclass 33, count 2 2006.203.07:48:32.45#ibcon#end of sib2, iclass 33, count 2 2006.203.07:48:32.45#ibcon#*mode == 0, iclass 33, count 2 2006.203.07:48:32.45#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.203.07:48:32.45#ibcon#[27=AT04-04\r\n] 2006.203.07:48:32.45#ibcon#*before write, iclass 33, count 2 2006.203.07:48:32.45#ibcon#enter sib2, iclass 33, count 2 2006.203.07:48:32.45#ibcon#flushed, iclass 33, count 2 2006.203.07:48:32.45#ibcon#about to write, iclass 33, count 2 2006.203.07:48:32.45#ibcon#wrote, iclass 33, count 2 2006.203.07:48:32.45#ibcon#about to read 3, iclass 33, count 2 2006.203.07:48:32.48#ibcon#read 3, iclass 33, count 2 2006.203.07:48:32.48#ibcon#about to read 4, iclass 33, count 2 2006.203.07:48:32.48#ibcon#read 4, iclass 33, count 2 2006.203.07:48:32.48#ibcon#about to read 5, iclass 33, count 2 2006.203.07:48:32.48#ibcon#read 5, iclass 33, count 2 2006.203.07:48:32.48#ibcon#about to read 6, iclass 33, count 2 2006.203.07:48:32.48#ibcon#read 6, iclass 33, count 2 2006.203.07:48:32.48#ibcon#end of sib2, iclass 33, count 2 2006.203.07:48:32.48#ibcon#*after write, iclass 33, count 2 2006.203.07:48:32.48#ibcon#*before return 0, iclass 33, count 2 2006.203.07:48:32.48#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.203.07:48:32.48#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.203.07:48:32.48#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.203.07:48:32.48#ibcon#ireg 7 cls_cnt 0 2006.203.07:48:32.48#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.203.07:48:32.60#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.203.07:48:32.60#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.203.07:48:32.60#ibcon#enter wrdev, iclass 33, count 0 2006.203.07:48:32.60#ibcon#first serial, iclass 33, count 0 2006.203.07:48:32.60#ibcon#enter sib2, iclass 33, count 0 2006.203.07:48:32.60#ibcon#flushed, iclass 33, count 0 2006.203.07:48:32.60#ibcon#about to write, iclass 33, count 0 2006.203.07:48:32.60#ibcon#wrote, iclass 33, count 0 2006.203.07:48:32.60#ibcon#about to read 3, iclass 33, count 0 2006.203.07:48:32.62#ibcon#read 3, iclass 33, count 0 2006.203.07:48:32.62#ibcon#about to read 4, iclass 33, count 0 2006.203.07:48:32.62#ibcon#read 4, iclass 33, count 0 2006.203.07:48:32.62#ibcon#about to read 5, iclass 33, count 0 2006.203.07:48:32.62#ibcon#read 5, iclass 33, count 0 2006.203.07:48:32.62#ibcon#about to read 6, iclass 33, count 0 2006.203.07:48:32.62#ibcon#read 6, iclass 33, count 0 2006.203.07:48:32.62#ibcon#end of sib2, iclass 33, count 0 2006.203.07:48:32.62#ibcon#*mode == 0, iclass 33, count 0 2006.203.07:48:32.62#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.203.07:48:32.62#ibcon#[27=USB\r\n] 2006.203.07:48:32.62#ibcon#*before write, iclass 33, count 0 2006.203.07:48:32.62#ibcon#enter sib2, iclass 33, count 0 2006.203.07:48:32.62#ibcon#flushed, iclass 33, count 0 2006.203.07:48:32.62#ibcon#about to write, iclass 33, count 0 2006.203.07:48:32.62#ibcon#wrote, iclass 33, count 0 2006.203.07:48:32.62#ibcon#about to read 3, iclass 33, count 0 2006.203.07:48:32.65#ibcon#read 3, iclass 33, count 0 2006.203.07:48:32.65#ibcon#about to read 4, iclass 33, count 0 2006.203.07:48:32.65#ibcon#read 4, iclass 33, count 0 2006.203.07:48:32.65#ibcon#about to read 5, iclass 33, count 0 2006.203.07:48:32.65#ibcon#read 5, iclass 33, count 0 2006.203.07:48:32.65#ibcon#about to read 6, iclass 33, count 0 2006.203.07:48:32.65#ibcon#read 6, iclass 33, count 0 2006.203.07:48:32.65#ibcon#end of sib2, iclass 33, count 0 2006.203.07:48:32.65#ibcon#*after write, iclass 33, count 0 2006.203.07:48:32.65#ibcon#*before return 0, iclass 33, count 0 2006.203.07:48:32.65#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.203.07:48:32.65#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.203.07:48:32.65#ibcon#about to clear, iclass 33 cls_cnt 0 2006.203.07:48:32.65#ibcon#cleared, iclass 33 cls_cnt 0 2006.203.07:48:32.65$vc4f8/vblo=5,744.99 2006.203.07:48:32.65#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.203.07:48:32.65#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.203.07:48:32.65#ibcon#ireg 17 cls_cnt 0 2006.203.07:48:32.65#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.203.07:48:32.65#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.203.07:48:32.65#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.203.07:48:32.65#ibcon#enter wrdev, iclass 35, count 0 2006.203.07:48:32.65#ibcon#first serial, iclass 35, count 0 2006.203.07:48:32.65#ibcon#enter sib2, iclass 35, count 0 2006.203.07:48:32.65#ibcon#flushed, iclass 35, count 0 2006.203.07:48:32.65#ibcon#about to write, iclass 35, count 0 2006.203.07:48:32.65#ibcon#wrote, iclass 35, count 0 2006.203.07:48:32.65#ibcon#about to read 3, iclass 35, count 0 2006.203.07:48:32.67#ibcon#read 3, iclass 35, count 0 2006.203.07:48:32.67#ibcon#about to read 4, iclass 35, count 0 2006.203.07:48:32.67#ibcon#read 4, iclass 35, count 0 2006.203.07:48:32.67#ibcon#about to read 5, iclass 35, count 0 2006.203.07:48:32.67#ibcon#read 5, iclass 35, count 0 2006.203.07:48:32.67#ibcon#about to read 6, iclass 35, count 0 2006.203.07:48:32.67#ibcon#read 6, iclass 35, count 0 2006.203.07:48:32.67#ibcon#end of sib2, iclass 35, count 0 2006.203.07:48:32.67#ibcon#*mode == 0, iclass 35, count 0 2006.203.07:48:32.67#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.203.07:48:32.67#ibcon#[28=FRQ=05,744.99\r\n] 2006.203.07:48:32.67#ibcon#*before write, iclass 35, count 0 2006.203.07:48:32.67#ibcon#enter sib2, iclass 35, count 0 2006.203.07:48:32.67#ibcon#flushed, iclass 35, count 0 2006.203.07:48:32.67#ibcon#about to write, iclass 35, count 0 2006.203.07:48:32.67#ibcon#wrote, iclass 35, count 0 2006.203.07:48:32.67#ibcon#about to read 3, iclass 35, count 0 2006.203.07:48:32.71#ibcon#read 3, iclass 35, count 0 2006.203.07:48:32.71#ibcon#about to read 4, iclass 35, count 0 2006.203.07:48:32.71#ibcon#read 4, iclass 35, count 0 2006.203.07:48:32.71#ibcon#about to read 5, iclass 35, count 0 2006.203.07:48:32.71#ibcon#read 5, iclass 35, count 0 2006.203.07:48:32.71#ibcon#about to read 6, iclass 35, count 0 2006.203.07:48:32.71#ibcon#read 6, iclass 35, count 0 2006.203.07:48:32.71#ibcon#end of sib2, iclass 35, count 0 2006.203.07:48:32.71#ibcon#*after write, iclass 35, count 0 2006.203.07:48:32.71#ibcon#*before return 0, iclass 35, count 0 2006.203.07:48:32.71#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.203.07:48:32.71#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.203.07:48:32.71#ibcon#about to clear, iclass 35 cls_cnt 0 2006.203.07:48:32.71#ibcon#cleared, iclass 35 cls_cnt 0 2006.203.07:48:32.71$vc4f8/vb=5,3 2006.203.07:48:32.71#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.203.07:48:32.71#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.203.07:48:32.71#ibcon#ireg 11 cls_cnt 2 2006.203.07:48:32.71#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.203.07:48:32.77#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.203.07:48:32.77#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.203.07:48:32.77#ibcon#enter wrdev, iclass 37, count 2 2006.203.07:48:32.77#ibcon#first serial, iclass 37, count 2 2006.203.07:48:32.77#ibcon#enter sib2, iclass 37, count 2 2006.203.07:48:32.77#ibcon#flushed, iclass 37, count 2 2006.203.07:48:32.77#ibcon#about to write, iclass 37, count 2 2006.203.07:48:32.77#ibcon#wrote, iclass 37, count 2 2006.203.07:48:32.77#ibcon#about to read 3, iclass 37, count 2 2006.203.07:48:32.79#ibcon#read 3, iclass 37, count 2 2006.203.07:48:32.79#ibcon#about to read 4, iclass 37, count 2 2006.203.07:48:32.79#ibcon#read 4, iclass 37, count 2 2006.203.07:48:32.79#ibcon#about to read 5, iclass 37, count 2 2006.203.07:48:32.79#ibcon#read 5, iclass 37, count 2 2006.203.07:48:32.79#ibcon#about to read 6, iclass 37, count 2 2006.203.07:48:32.79#ibcon#read 6, iclass 37, count 2 2006.203.07:48:32.79#ibcon#end of sib2, iclass 37, count 2 2006.203.07:48:32.79#ibcon#*mode == 0, iclass 37, count 2 2006.203.07:48:32.79#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.203.07:48:32.79#ibcon#[27=AT05-03\r\n] 2006.203.07:48:32.79#ibcon#*before write, iclass 37, count 2 2006.203.07:48:32.79#ibcon#enter sib2, iclass 37, count 2 2006.203.07:48:32.79#ibcon#flushed, iclass 37, count 2 2006.203.07:48:32.79#ibcon#about to write, iclass 37, count 2 2006.203.07:48:32.79#ibcon#wrote, iclass 37, count 2 2006.203.07:48:32.79#ibcon#about to read 3, iclass 37, count 2 2006.203.07:48:32.82#ibcon#read 3, iclass 37, count 2 2006.203.07:48:32.82#ibcon#about to read 4, iclass 37, count 2 2006.203.07:48:32.82#ibcon#read 4, iclass 37, count 2 2006.203.07:48:32.82#ibcon#about to read 5, iclass 37, count 2 2006.203.07:48:32.82#ibcon#read 5, iclass 37, count 2 2006.203.07:48:32.82#ibcon#about to read 6, iclass 37, count 2 2006.203.07:48:32.82#ibcon#read 6, iclass 37, count 2 2006.203.07:48:32.82#ibcon#end of sib2, iclass 37, count 2 2006.203.07:48:32.82#ibcon#*after write, iclass 37, count 2 2006.203.07:48:32.82#ibcon#*before return 0, iclass 37, count 2 2006.203.07:48:32.82#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.203.07:48:32.82#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.203.07:48:32.82#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.203.07:48:32.82#ibcon#ireg 7 cls_cnt 0 2006.203.07:48:32.82#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.203.07:48:32.94#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.203.07:48:32.94#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.203.07:48:32.94#ibcon#enter wrdev, iclass 37, count 0 2006.203.07:48:32.94#ibcon#first serial, iclass 37, count 0 2006.203.07:48:32.94#ibcon#enter sib2, iclass 37, count 0 2006.203.07:48:32.94#ibcon#flushed, iclass 37, count 0 2006.203.07:48:32.94#ibcon#about to write, iclass 37, count 0 2006.203.07:48:32.94#ibcon#wrote, iclass 37, count 0 2006.203.07:48:32.94#ibcon#about to read 3, iclass 37, count 0 2006.203.07:48:32.96#ibcon#read 3, iclass 37, count 0 2006.203.07:48:32.96#ibcon#about to read 4, iclass 37, count 0 2006.203.07:48:32.96#ibcon#read 4, iclass 37, count 0 2006.203.07:48:32.96#ibcon#about to read 5, iclass 37, count 0 2006.203.07:48:32.96#ibcon#read 5, iclass 37, count 0 2006.203.07:48:32.96#ibcon#about to read 6, iclass 37, count 0 2006.203.07:48:32.96#ibcon#read 6, iclass 37, count 0 2006.203.07:48:32.96#ibcon#end of sib2, iclass 37, count 0 2006.203.07:48:32.96#ibcon#*mode == 0, iclass 37, count 0 2006.203.07:48:32.96#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.203.07:48:32.96#ibcon#[27=USB\r\n] 2006.203.07:48:32.96#ibcon#*before write, iclass 37, count 0 2006.203.07:48:32.96#ibcon#enter sib2, iclass 37, count 0 2006.203.07:48:32.96#ibcon#flushed, iclass 37, count 0 2006.203.07:48:32.96#ibcon#about to write, iclass 37, count 0 2006.203.07:48:32.96#ibcon#wrote, iclass 37, count 0 2006.203.07:48:32.96#ibcon#about to read 3, iclass 37, count 0 2006.203.07:48:32.99#ibcon#read 3, iclass 37, count 0 2006.203.07:48:32.99#ibcon#about to read 4, iclass 37, count 0 2006.203.07:48:32.99#ibcon#read 4, iclass 37, count 0 2006.203.07:48:32.99#ibcon#about to read 5, iclass 37, count 0 2006.203.07:48:32.99#ibcon#read 5, iclass 37, count 0 2006.203.07:48:32.99#ibcon#about to read 6, iclass 37, count 0 2006.203.07:48:32.99#ibcon#read 6, iclass 37, count 0 2006.203.07:48:32.99#ibcon#end of sib2, iclass 37, count 0 2006.203.07:48:32.99#ibcon#*after write, iclass 37, count 0 2006.203.07:48:32.99#ibcon#*before return 0, iclass 37, count 0 2006.203.07:48:32.99#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.203.07:48:32.99#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.203.07:48:32.99#ibcon#about to clear, iclass 37 cls_cnt 0 2006.203.07:48:32.99#ibcon#cleared, iclass 37 cls_cnt 0 2006.203.07:48:32.99$vc4f8/vblo=6,752.99 2006.203.07:48:32.99#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.203.07:48:32.99#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.203.07:48:32.99#ibcon#ireg 17 cls_cnt 0 2006.203.07:48:32.99#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.203.07:48:32.99#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.203.07:48:32.99#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.203.07:48:32.99#ibcon#enter wrdev, iclass 39, count 0 2006.203.07:48:32.99#ibcon#first serial, iclass 39, count 0 2006.203.07:48:32.99#ibcon#enter sib2, iclass 39, count 0 2006.203.07:48:32.99#ibcon#flushed, iclass 39, count 0 2006.203.07:48:32.99#ibcon#about to write, iclass 39, count 0 2006.203.07:48:32.99#ibcon#wrote, iclass 39, count 0 2006.203.07:48:32.99#ibcon#about to read 3, iclass 39, count 0 2006.203.07:48:33.02#ibcon#read 3, iclass 39, count 0 2006.203.07:48:33.02#ibcon#about to read 4, iclass 39, count 0 2006.203.07:48:33.02#ibcon#read 4, iclass 39, count 0 2006.203.07:48:33.02#ibcon#about to read 5, iclass 39, count 0 2006.203.07:48:33.02#ibcon#read 5, iclass 39, count 0 2006.203.07:48:33.02#ibcon#about to read 6, iclass 39, count 0 2006.203.07:48:33.02#ibcon#read 6, iclass 39, count 0 2006.203.07:48:33.02#ibcon#end of sib2, iclass 39, count 0 2006.203.07:48:33.02#ibcon#*mode == 0, iclass 39, count 0 2006.203.07:48:33.02#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.203.07:48:33.02#ibcon#[28=FRQ=06,752.99\r\n] 2006.203.07:48:33.02#ibcon#*before write, iclass 39, count 0 2006.203.07:48:33.02#ibcon#enter sib2, iclass 39, count 0 2006.203.07:48:33.02#ibcon#flushed, iclass 39, count 0 2006.203.07:48:33.02#ibcon#about to write, iclass 39, count 0 2006.203.07:48:33.02#ibcon#wrote, iclass 39, count 0 2006.203.07:48:33.02#ibcon#about to read 3, iclass 39, count 0 2006.203.07:48:33.06#ibcon#read 3, iclass 39, count 0 2006.203.07:48:33.06#ibcon#about to read 4, iclass 39, count 0 2006.203.07:48:33.06#ibcon#read 4, iclass 39, count 0 2006.203.07:48:33.06#ibcon#about to read 5, iclass 39, count 0 2006.203.07:48:33.06#ibcon#read 5, iclass 39, count 0 2006.203.07:48:33.06#ibcon#about to read 6, iclass 39, count 0 2006.203.07:48:33.06#ibcon#read 6, iclass 39, count 0 2006.203.07:48:33.06#ibcon#end of sib2, iclass 39, count 0 2006.203.07:48:33.06#ibcon#*after write, iclass 39, count 0 2006.203.07:48:33.06#ibcon#*before return 0, iclass 39, count 0 2006.203.07:48:33.06#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.203.07:48:33.06#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.203.07:48:33.06#ibcon#about to clear, iclass 39 cls_cnt 0 2006.203.07:48:33.06#ibcon#cleared, iclass 39 cls_cnt 0 2006.203.07:48:33.06$vc4f8/vb=6,4 2006.203.07:48:33.06#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.203.07:48:33.06#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.203.07:48:33.06#ibcon#ireg 11 cls_cnt 2 2006.203.07:48:33.06#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.203.07:48:33.11#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.203.07:48:33.11#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.203.07:48:33.11#ibcon#enter wrdev, iclass 3, count 2 2006.203.07:48:33.11#ibcon#first serial, iclass 3, count 2 2006.203.07:48:33.11#ibcon#enter sib2, iclass 3, count 2 2006.203.07:48:33.11#ibcon#flushed, iclass 3, count 2 2006.203.07:48:33.11#ibcon#about to write, iclass 3, count 2 2006.203.07:48:33.11#ibcon#wrote, iclass 3, count 2 2006.203.07:48:33.11#ibcon#about to read 3, iclass 3, count 2 2006.203.07:48:33.13#ibcon#read 3, iclass 3, count 2 2006.203.07:48:33.13#ibcon#about to read 4, iclass 3, count 2 2006.203.07:48:33.13#ibcon#read 4, iclass 3, count 2 2006.203.07:48:33.13#ibcon#about to read 5, iclass 3, count 2 2006.203.07:48:33.13#ibcon#read 5, iclass 3, count 2 2006.203.07:48:33.13#ibcon#about to read 6, iclass 3, count 2 2006.203.07:48:33.13#ibcon#read 6, iclass 3, count 2 2006.203.07:48:33.13#ibcon#end of sib2, iclass 3, count 2 2006.203.07:48:33.13#ibcon#*mode == 0, iclass 3, count 2 2006.203.07:48:33.13#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.203.07:48:33.13#ibcon#[27=AT06-04\r\n] 2006.203.07:48:33.13#ibcon#*before write, iclass 3, count 2 2006.203.07:48:33.13#ibcon#enter sib2, iclass 3, count 2 2006.203.07:48:33.13#ibcon#flushed, iclass 3, count 2 2006.203.07:48:33.13#ibcon#about to write, iclass 3, count 2 2006.203.07:48:33.13#ibcon#wrote, iclass 3, count 2 2006.203.07:48:33.13#ibcon#about to read 3, iclass 3, count 2 2006.203.07:48:33.16#ibcon#read 3, iclass 3, count 2 2006.203.07:48:33.16#ibcon#about to read 4, iclass 3, count 2 2006.203.07:48:33.16#ibcon#read 4, iclass 3, count 2 2006.203.07:48:33.16#ibcon#about to read 5, iclass 3, count 2 2006.203.07:48:33.16#ibcon#read 5, iclass 3, count 2 2006.203.07:48:33.16#ibcon#about to read 6, iclass 3, count 2 2006.203.07:48:33.16#ibcon#read 6, iclass 3, count 2 2006.203.07:48:33.16#ibcon#end of sib2, iclass 3, count 2 2006.203.07:48:33.16#ibcon#*after write, iclass 3, count 2 2006.203.07:48:33.16#ibcon#*before return 0, iclass 3, count 2 2006.203.07:48:33.16#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.203.07:48:33.16#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.203.07:48:33.16#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.203.07:48:33.16#ibcon#ireg 7 cls_cnt 0 2006.203.07:48:33.16#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.203.07:48:33.28#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.203.07:48:33.28#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.203.07:48:33.28#ibcon#enter wrdev, iclass 3, count 0 2006.203.07:48:33.28#ibcon#first serial, iclass 3, count 0 2006.203.07:48:33.28#ibcon#enter sib2, iclass 3, count 0 2006.203.07:48:33.28#ibcon#flushed, iclass 3, count 0 2006.203.07:48:33.28#ibcon#about to write, iclass 3, count 0 2006.203.07:48:33.28#ibcon#wrote, iclass 3, count 0 2006.203.07:48:33.28#ibcon#about to read 3, iclass 3, count 0 2006.203.07:48:33.30#ibcon#read 3, iclass 3, count 0 2006.203.07:48:33.30#ibcon#about to read 4, iclass 3, count 0 2006.203.07:48:33.30#ibcon#read 4, iclass 3, count 0 2006.203.07:48:33.30#ibcon#about to read 5, iclass 3, count 0 2006.203.07:48:33.30#ibcon#read 5, iclass 3, count 0 2006.203.07:48:33.30#ibcon#about to read 6, iclass 3, count 0 2006.203.07:48:33.30#ibcon#read 6, iclass 3, count 0 2006.203.07:48:33.30#ibcon#end of sib2, iclass 3, count 0 2006.203.07:48:33.30#ibcon#*mode == 0, iclass 3, count 0 2006.203.07:48:33.30#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.203.07:48:33.30#ibcon#[27=USB\r\n] 2006.203.07:48:33.30#ibcon#*before write, iclass 3, count 0 2006.203.07:48:33.30#ibcon#enter sib2, iclass 3, count 0 2006.203.07:48:33.30#ibcon#flushed, iclass 3, count 0 2006.203.07:48:33.30#ibcon#about to write, iclass 3, count 0 2006.203.07:48:33.30#ibcon#wrote, iclass 3, count 0 2006.203.07:48:33.30#ibcon#about to read 3, iclass 3, count 0 2006.203.07:48:33.33#ibcon#read 3, iclass 3, count 0 2006.203.07:48:33.33#ibcon#about to read 4, iclass 3, count 0 2006.203.07:48:33.33#ibcon#read 4, iclass 3, count 0 2006.203.07:48:33.33#ibcon#about to read 5, iclass 3, count 0 2006.203.07:48:33.33#ibcon#read 5, iclass 3, count 0 2006.203.07:48:33.33#ibcon#about to read 6, iclass 3, count 0 2006.203.07:48:33.33#ibcon#read 6, iclass 3, count 0 2006.203.07:48:33.33#ibcon#end of sib2, iclass 3, count 0 2006.203.07:48:33.33#ibcon#*after write, iclass 3, count 0 2006.203.07:48:33.33#ibcon#*before return 0, iclass 3, count 0 2006.203.07:48:33.33#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.203.07:48:33.33#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.203.07:48:33.33#ibcon#about to clear, iclass 3 cls_cnt 0 2006.203.07:48:33.33#ibcon#cleared, iclass 3 cls_cnt 0 2006.203.07:48:33.33$vc4f8/vabw=wide 2006.203.07:48:33.33#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.203.07:48:33.33#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.203.07:48:33.33#ibcon#ireg 8 cls_cnt 0 2006.203.07:48:33.33#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.203.07:48:33.33#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.203.07:48:33.33#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.203.07:48:33.33#ibcon#enter wrdev, iclass 5, count 0 2006.203.07:48:33.33#ibcon#first serial, iclass 5, count 0 2006.203.07:48:33.33#ibcon#enter sib2, iclass 5, count 0 2006.203.07:48:33.33#ibcon#flushed, iclass 5, count 0 2006.203.07:48:33.33#ibcon#about to write, iclass 5, count 0 2006.203.07:48:33.33#ibcon#wrote, iclass 5, count 0 2006.203.07:48:33.33#ibcon#about to read 3, iclass 5, count 0 2006.203.07:48:33.35#ibcon#read 3, iclass 5, count 0 2006.203.07:48:33.35#ibcon#about to read 4, iclass 5, count 0 2006.203.07:48:33.35#ibcon#read 4, iclass 5, count 0 2006.203.07:48:33.35#ibcon#about to read 5, iclass 5, count 0 2006.203.07:48:33.35#ibcon#read 5, iclass 5, count 0 2006.203.07:48:33.35#ibcon#about to read 6, iclass 5, count 0 2006.203.07:48:33.35#ibcon#read 6, iclass 5, count 0 2006.203.07:48:33.35#ibcon#end of sib2, iclass 5, count 0 2006.203.07:48:33.35#ibcon#*mode == 0, iclass 5, count 0 2006.203.07:48:33.35#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.203.07:48:33.35#ibcon#[25=BW32\r\n] 2006.203.07:48:33.35#ibcon#*before write, iclass 5, count 0 2006.203.07:48:33.35#ibcon#enter sib2, iclass 5, count 0 2006.203.07:48:33.35#ibcon#flushed, iclass 5, count 0 2006.203.07:48:33.35#ibcon#about to write, iclass 5, count 0 2006.203.07:48:33.35#ibcon#wrote, iclass 5, count 0 2006.203.07:48:33.35#ibcon#about to read 3, iclass 5, count 0 2006.203.07:48:33.38#ibcon#read 3, iclass 5, count 0 2006.203.07:48:33.38#ibcon#about to read 4, iclass 5, count 0 2006.203.07:48:33.38#ibcon#read 4, iclass 5, count 0 2006.203.07:48:33.38#ibcon#about to read 5, iclass 5, count 0 2006.203.07:48:33.38#ibcon#read 5, iclass 5, count 0 2006.203.07:48:33.38#ibcon#about to read 6, iclass 5, count 0 2006.203.07:48:33.38#ibcon#read 6, iclass 5, count 0 2006.203.07:48:33.38#ibcon#end of sib2, iclass 5, count 0 2006.203.07:48:33.38#ibcon#*after write, iclass 5, count 0 2006.203.07:48:33.38#ibcon#*before return 0, iclass 5, count 0 2006.203.07:48:33.38#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.203.07:48:33.38#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.203.07:48:33.38#ibcon#about to clear, iclass 5 cls_cnt 0 2006.203.07:48:33.38#ibcon#cleared, iclass 5 cls_cnt 0 2006.203.07:48:33.38$vc4f8/vbbw=wide 2006.203.07:48:33.38#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.203.07:48:33.38#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.203.07:48:33.38#ibcon#ireg 8 cls_cnt 0 2006.203.07:48:33.38#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.203.07:48:33.45#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.203.07:48:33.45#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.203.07:48:33.45#ibcon#enter wrdev, iclass 7, count 0 2006.203.07:48:33.45#ibcon#first serial, iclass 7, count 0 2006.203.07:48:33.45#ibcon#enter sib2, iclass 7, count 0 2006.203.07:48:33.45#ibcon#flushed, iclass 7, count 0 2006.203.07:48:33.45#ibcon#about to write, iclass 7, count 0 2006.203.07:48:33.45#ibcon#wrote, iclass 7, count 0 2006.203.07:48:33.45#ibcon#about to read 3, iclass 7, count 0 2006.203.07:48:33.47#ibcon#read 3, iclass 7, count 0 2006.203.07:48:33.47#ibcon#about to read 4, iclass 7, count 0 2006.203.07:48:33.47#ibcon#read 4, iclass 7, count 0 2006.203.07:48:33.47#ibcon#about to read 5, iclass 7, count 0 2006.203.07:48:33.47#ibcon#read 5, iclass 7, count 0 2006.203.07:48:33.47#ibcon#about to read 6, iclass 7, count 0 2006.203.07:48:33.47#ibcon#read 6, iclass 7, count 0 2006.203.07:48:33.47#ibcon#end of sib2, iclass 7, count 0 2006.203.07:48:33.47#ibcon#*mode == 0, iclass 7, count 0 2006.203.07:48:33.47#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.203.07:48:33.47#ibcon#[27=BW32\r\n] 2006.203.07:48:33.47#ibcon#*before write, iclass 7, count 0 2006.203.07:48:33.47#ibcon#enter sib2, iclass 7, count 0 2006.203.07:48:33.47#ibcon#flushed, iclass 7, count 0 2006.203.07:48:33.47#ibcon#about to write, iclass 7, count 0 2006.203.07:48:33.47#ibcon#wrote, iclass 7, count 0 2006.203.07:48:33.47#ibcon#about to read 3, iclass 7, count 0 2006.203.07:48:33.50#ibcon#read 3, iclass 7, count 0 2006.203.07:48:33.50#ibcon#about to read 4, iclass 7, count 0 2006.203.07:48:33.50#ibcon#read 4, iclass 7, count 0 2006.203.07:48:33.50#ibcon#about to read 5, iclass 7, count 0 2006.203.07:48:33.50#ibcon#read 5, iclass 7, count 0 2006.203.07:48:33.50#ibcon#about to read 6, iclass 7, count 0 2006.203.07:48:33.50#ibcon#read 6, iclass 7, count 0 2006.203.07:48:33.50#ibcon#end of sib2, iclass 7, count 0 2006.203.07:48:33.50#ibcon#*after write, iclass 7, count 0 2006.203.07:48:33.50#ibcon#*before return 0, iclass 7, count 0 2006.203.07:48:33.50#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.203.07:48:33.50#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.203.07:48:33.50#ibcon#about to clear, iclass 7 cls_cnt 0 2006.203.07:48:33.50#ibcon#cleared, iclass 7 cls_cnt 0 2006.203.07:48:33.50$4f8m12a/ifd4f 2006.203.07:48:33.50$ifd4f/lo= 2006.203.07:48:33.50$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.203.07:48:33.50$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.203.07:48:33.50$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.203.07:48:33.50$ifd4f/patch= 2006.203.07:48:33.50$ifd4f/patch=lo1,a1,a2,a3,a4 2006.203.07:48:33.50$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.203.07:48:33.50$ifd4f/patch=lo3,a5,a6,a7,a8 2006.203.07:48:33.50$4f8m12a/"form=m,16.000,1:2 2006.203.07:48:33.50$4f8m12a/"tpicd 2006.203.07:48:33.50$4f8m12a/echo=off 2006.203.07:48:33.50$4f8m12a/xlog=off 2006.203.07:48:33.50:!2006.203.07:49:00 2006.203.07:48:38.13#trakl#Source acquired 2006.203.07:48:39.13#flagr#flagr/antenna,acquired 2006.203.07:49:00.00:preob 2006.203.07:49:01.14/onsource/TRACKING 2006.203.07:49:01.14:!2006.203.07:49:10 2006.203.07:49:10.00:data_valid=on 2006.203.07:49:10.00:midob 2006.203.07:49:10.14/onsource/TRACKING 2006.203.07:49:10.14/wx/23.86,1001.2,98 2006.203.07:49:10.26/cable/+6.4604E-03 2006.203.07:49:11.35/va/01,08,usb,yes,29,31 2006.203.07:49:11.35/va/02,07,usb,yes,29,31 2006.203.07:49:11.35/va/03,08,usb,yes,22,22 2006.203.07:49:11.35/va/04,07,usb,yes,30,32 2006.203.07:49:11.35/va/05,07,usb,yes,32,34 2006.203.07:49:11.35/va/06,06,usb,yes,32,31 2006.203.07:49:11.35/va/07,07,usb,yes,28,28 2006.203.07:49:11.35/va/08,06,usb,yes,34,34 2006.203.07:49:11.58/valo/01,532.99,yes,locked 2006.203.07:49:11.58/valo/02,572.99,yes,locked 2006.203.07:49:11.58/valo/03,672.99,yes,locked 2006.203.07:49:11.58/valo/04,832.99,yes,locked 2006.203.07:49:11.58/valo/05,652.99,yes,locked 2006.203.07:49:11.58/valo/06,772.99,yes,locked 2006.203.07:49:11.58/valo/07,832.99,yes,locked 2006.203.07:49:11.58/valo/08,852.99,yes,locked 2006.203.07:49:12.67/vb/01,04,usb,yes,29,27 2006.203.07:49:12.67/vb/02,04,usb,yes,30,32 2006.203.07:49:12.67/vb/03,04,usb,yes,27,30 2006.203.07:49:12.67/vb/04,04,usb,yes,28,28 2006.203.07:49:12.67/vb/05,03,usb,yes,33,37 2006.203.07:49:12.67/vb/06,04,usb,yes,27,30 2006.203.07:49:12.67/vb/07,04,usb,yes,29,29 2006.203.07:49:12.67/vb/08,04,usb,yes,27,30 2006.203.07:49:12.90/vblo/01,632.99,yes,locked 2006.203.07:49:12.90/vblo/02,640.99,yes,locked 2006.203.07:49:12.90/vblo/03,656.99,yes,locked 2006.203.07:49:12.90/vblo/04,712.99,yes,locked 2006.203.07:49:12.90/vblo/05,744.99,yes,locked 2006.203.07:49:12.90/vblo/06,752.99,yes,locked 2006.203.07:49:12.90/vblo/07,734.99,yes,locked 2006.203.07:49:12.90/vblo/08,744.99,yes,locked 2006.203.07:49:13.05/vabw/8 2006.203.07:49:13.20/vbbw/8 2006.203.07:49:13.29/xfe/off,on,14.2 2006.203.07:49:13.68/ifatt/23,28,28,28 2006.203.07:49:14.07/fmout-gps/S +4.52E-07 2006.203.07:49:14.11:!2006.203.07:50:10 2006.203.07:50:10.00:data_valid=off 2006.203.07:50:10.00:postob 2006.203.07:50:10.22/cable/+6.4587E-03 2006.203.07:50:10.22/wx/23.85,1001.2,97 2006.203.07:50:11.07/fmout-gps/S +4.53E-07 2006.203.07:50:11.07:scan_name=203-0751,k06203,60 2006.203.07:50:11.07:source=1739+522,174036.98,521143.4,2000.0,cw 2006.203.07:50:11.14#flagr#flagr/antenna,new-source 2006.203.07:50:12.14:checkk5 2006.203.07:50:12.56/chk_autoobs//k5ts1/ autoobs is running! 2006.203.07:50:13.21/chk_autoobs//k5ts2/ autoobs is running! 2006.203.07:50:13.64/chk_autoobs//k5ts3/ autoobs is running! 2006.203.07:50:14.07/chk_autoobs//k5ts4/ autoobs is running! 2006.203.07:50:14.49/chk_obsdata//k5ts1/T2030749??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.07:50:15.09/chk_obsdata//k5ts2/T2030749??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.07:50:15.50/chk_obsdata//k5ts3/T2030749??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.07:50:15.93/chk_obsdata//k5ts4/T2030749??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.07:50:16.74/k5log//k5ts1_log_newline 2006.203.07:50:17.48/k5log//k5ts2_log_newline 2006.203.07:50:18.45/k5log//k5ts3_log_newline 2006.203.07:50:19.20/k5log//k5ts4_log_newline 2006.203.07:50:19.22/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.203.07:50:19.22:4f8m12a=1 2006.203.07:50:19.22$4f8m12a/echo=on 2006.203.07:50:19.22$4f8m12a/pcalon 2006.203.07:50:19.22$pcalon/"no phase cal control is implemented here 2006.203.07:50:19.22$4f8m12a/"tpicd=stop 2006.203.07:50:19.22$4f8m12a/vc4f8 2006.203.07:50:19.23$vc4f8/valo=1,532.99 2006.203.07:50:19.23#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.203.07:50:19.23#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.203.07:50:19.23#ibcon#ireg 17 cls_cnt 0 2006.203.07:50:19.23#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.203.07:50:19.23#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.203.07:50:19.23#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.203.07:50:19.23#ibcon#enter wrdev, iclass 11, count 0 2006.203.07:50:19.23#ibcon#first serial, iclass 11, count 0 2006.203.07:50:19.23#ibcon#enter sib2, iclass 11, count 0 2006.203.07:50:19.23#ibcon#flushed, iclass 11, count 0 2006.203.07:50:19.23#ibcon#about to write, iclass 11, count 0 2006.203.07:50:19.23#ibcon#wrote, iclass 11, count 0 2006.203.07:50:19.23#ibcon#about to read 3, iclass 11, count 0 2006.203.07:50:19.27#ibcon#read 3, iclass 11, count 0 2006.203.07:50:19.27#ibcon#about to read 4, iclass 11, count 0 2006.203.07:50:19.27#ibcon#read 4, iclass 11, count 0 2006.203.07:50:19.27#ibcon#about to read 5, iclass 11, count 0 2006.203.07:50:19.27#ibcon#read 5, iclass 11, count 0 2006.203.07:50:19.27#ibcon#about to read 6, iclass 11, count 0 2006.203.07:50:19.27#ibcon#read 6, iclass 11, count 0 2006.203.07:50:19.27#ibcon#end of sib2, iclass 11, count 0 2006.203.07:50:19.27#ibcon#*mode == 0, iclass 11, count 0 2006.203.07:50:19.27#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.203.07:50:19.27#ibcon#[26=FRQ=01,532.99\r\n] 2006.203.07:50:19.27#ibcon#*before write, iclass 11, count 0 2006.203.07:50:19.27#ibcon#enter sib2, iclass 11, count 0 2006.203.07:50:19.27#ibcon#flushed, iclass 11, count 0 2006.203.07:50:19.27#ibcon#about to write, iclass 11, count 0 2006.203.07:50:19.27#ibcon#wrote, iclass 11, count 0 2006.203.07:50:19.27#ibcon#about to read 3, iclass 11, count 0 2006.203.07:50:19.32#ibcon#read 3, iclass 11, count 0 2006.203.07:50:19.32#ibcon#about to read 4, iclass 11, count 0 2006.203.07:50:19.32#ibcon#read 4, iclass 11, count 0 2006.203.07:50:19.32#ibcon#about to read 5, iclass 11, count 0 2006.203.07:50:19.32#ibcon#read 5, iclass 11, count 0 2006.203.07:50:19.32#ibcon#about to read 6, iclass 11, count 0 2006.203.07:50:19.32#ibcon#read 6, iclass 11, count 0 2006.203.07:50:19.32#ibcon#end of sib2, iclass 11, count 0 2006.203.07:50:19.32#ibcon#*after write, iclass 11, count 0 2006.203.07:50:19.32#ibcon#*before return 0, iclass 11, count 0 2006.203.07:50:19.32#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.203.07:50:19.32#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.203.07:50:19.32#ibcon#about to clear, iclass 11 cls_cnt 0 2006.203.07:50:19.32#ibcon#cleared, iclass 11 cls_cnt 0 2006.203.07:50:19.32$vc4f8/va=1,8 2006.203.07:50:19.32#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.203.07:50:19.32#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.203.07:50:19.32#ibcon#ireg 11 cls_cnt 2 2006.203.07:50:19.32#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.203.07:50:19.32#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.203.07:50:19.32#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.203.07:50:19.32#ibcon#enter wrdev, iclass 13, count 2 2006.203.07:50:19.32#ibcon#first serial, iclass 13, count 2 2006.203.07:50:19.32#ibcon#enter sib2, iclass 13, count 2 2006.203.07:50:19.32#ibcon#flushed, iclass 13, count 2 2006.203.07:50:19.32#ibcon#about to write, iclass 13, count 2 2006.203.07:50:19.32#ibcon#wrote, iclass 13, count 2 2006.203.07:50:19.32#ibcon#about to read 3, iclass 13, count 2 2006.203.07:50:19.35#ibcon#read 3, iclass 13, count 2 2006.203.07:50:19.35#ibcon#about to read 4, iclass 13, count 2 2006.203.07:50:19.35#ibcon#read 4, iclass 13, count 2 2006.203.07:50:19.35#ibcon#about to read 5, iclass 13, count 2 2006.203.07:50:19.35#ibcon#read 5, iclass 13, count 2 2006.203.07:50:19.35#ibcon#about to read 6, iclass 13, count 2 2006.203.07:50:19.35#ibcon#read 6, iclass 13, count 2 2006.203.07:50:19.35#ibcon#end of sib2, iclass 13, count 2 2006.203.07:50:19.35#ibcon#*mode == 0, iclass 13, count 2 2006.203.07:50:19.35#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.203.07:50:19.35#ibcon#[25=AT01-08\r\n] 2006.203.07:50:19.35#ibcon#*before write, iclass 13, count 2 2006.203.07:50:19.35#ibcon#enter sib2, iclass 13, count 2 2006.203.07:50:19.35#ibcon#flushed, iclass 13, count 2 2006.203.07:50:19.35#ibcon#about to write, iclass 13, count 2 2006.203.07:50:19.35#ibcon#wrote, iclass 13, count 2 2006.203.07:50:19.35#ibcon#about to read 3, iclass 13, count 2 2006.203.07:50:19.38#ibcon#read 3, iclass 13, count 2 2006.203.07:50:19.38#ibcon#about to read 4, iclass 13, count 2 2006.203.07:50:19.38#ibcon#read 4, iclass 13, count 2 2006.203.07:50:19.38#ibcon#about to read 5, iclass 13, count 2 2006.203.07:50:19.38#ibcon#read 5, iclass 13, count 2 2006.203.07:50:19.38#ibcon#about to read 6, iclass 13, count 2 2006.203.07:50:19.38#ibcon#read 6, iclass 13, count 2 2006.203.07:50:19.38#ibcon#end of sib2, iclass 13, count 2 2006.203.07:50:19.38#ibcon#*after write, iclass 13, count 2 2006.203.07:50:19.38#ibcon#*before return 0, iclass 13, count 2 2006.203.07:50:19.38#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.203.07:50:19.38#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.203.07:50:19.38#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.203.07:50:19.38#ibcon#ireg 7 cls_cnt 0 2006.203.07:50:19.38#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.203.07:50:19.50#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.203.07:50:19.50#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.203.07:50:19.50#ibcon#enter wrdev, iclass 13, count 0 2006.203.07:50:19.50#ibcon#first serial, iclass 13, count 0 2006.203.07:50:19.50#ibcon#enter sib2, iclass 13, count 0 2006.203.07:50:19.50#ibcon#flushed, iclass 13, count 0 2006.203.07:50:19.50#ibcon#about to write, iclass 13, count 0 2006.203.07:50:19.50#ibcon#wrote, iclass 13, count 0 2006.203.07:50:19.50#ibcon#about to read 3, iclass 13, count 0 2006.203.07:50:19.52#ibcon#read 3, iclass 13, count 0 2006.203.07:50:19.52#ibcon#about to read 4, iclass 13, count 0 2006.203.07:50:19.52#ibcon#read 4, iclass 13, count 0 2006.203.07:50:19.52#ibcon#about to read 5, iclass 13, count 0 2006.203.07:50:19.52#ibcon#read 5, iclass 13, count 0 2006.203.07:50:19.52#ibcon#about to read 6, iclass 13, count 0 2006.203.07:50:19.52#ibcon#read 6, iclass 13, count 0 2006.203.07:50:19.52#ibcon#end of sib2, iclass 13, count 0 2006.203.07:50:19.52#ibcon#*mode == 0, iclass 13, count 0 2006.203.07:50:19.52#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.203.07:50:19.52#ibcon#[25=USB\r\n] 2006.203.07:50:19.52#ibcon#*before write, iclass 13, count 0 2006.203.07:50:19.52#ibcon#enter sib2, iclass 13, count 0 2006.203.07:50:19.52#ibcon#flushed, iclass 13, count 0 2006.203.07:50:19.52#ibcon#about to write, iclass 13, count 0 2006.203.07:50:19.52#ibcon#wrote, iclass 13, count 0 2006.203.07:50:19.52#ibcon#about to read 3, iclass 13, count 0 2006.203.07:50:19.55#ibcon#read 3, iclass 13, count 0 2006.203.07:50:19.55#ibcon#about to read 4, iclass 13, count 0 2006.203.07:50:19.55#ibcon#read 4, iclass 13, count 0 2006.203.07:50:19.55#ibcon#about to read 5, iclass 13, count 0 2006.203.07:50:19.55#ibcon#read 5, iclass 13, count 0 2006.203.07:50:19.55#ibcon#about to read 6, iclass 13, count 0 2006.203.07:50:19.55#ibcon#read 6, iclass 13, count 0 2006.203.07:50:19.55#ibcon#end of sib2, iclass 13, count 0 2006.203.07:50:19.55#ibcon#*after write, iclass 13, count 0 2006.203.07:50:19.55#ibcon#*before return 0, iclass 13, count 0 2006.203.07:50:19.55#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.203.07:50:19.55#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.203.07:50:19.55#ibcon#about to clear, iclass 13 cls_cnt 0 2006.203.07:50:19.55#ibcon#cleared, iclass 13 cls_cnt 0 2006.203.07:50:19.55$vc4f8/valo=2,572.99 2006.203.07:50:19.55#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.203.07:50:19.55#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.203.07:50:19.55#ibcon#ireg 17 cls_cnt 0 2006.203.07:50:19.55#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.203.07:50:19.55#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.203.07:50:19.55#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.203.07:50:19.55#ibcon#enter wrdev, iclass 15, count 0 2006.203.07:50:19.55#ibcon#first serial, iclass 15, count 0 2006.203.07:50:19.55#ibcon#enter sib2, iclass 15, count 0 2006.203.07:50:19.55#ibcon#flushed, iclass 15, count 0 2006.203.07:50:19.55#ibcon#about to write, iclass 15, count 0 2006.203.07:50:19.55#ibcon#wrote, iclass 15, count 0 2006.203.07:50:19.55#ibcon#about to read 3, iclass 15, count 0 2006.203.07:50:19.57#ibcon#read 3, iclass 15, count 0 2006.203.07:50:19.57#ibcon#about to read 4, iclass 15, count 0 2006.203.07:50:19.57#ibcon#read 4, iclass 15, count 0 2006.203.07:50:19.57#ibcon#about to read 5, iclass 15, count 0 2006.203.07:50:19.57#ibcon#read 5, iclass 15, count 0 2006.203.07:50:19.57#ibcon#about to read 6, iclass 15, count 0 2006.203.07:50:19.57#ibcon#read 6, iclass 15, count 0 2006.203.07:50:19.57#ibcon#end of sib2, iclass 15, count 0 2006.203.07:50:19.57#ibcon#*mode == 0, iclass 15, count 0 2006.203.07:50:19.57#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.203.07:50:19.57#ibcon#[26=FRQ=02,572.99\r\n] 2006.203.07:50:19.57#ibcon#*before write, iclass 15, count 0 2006.203.07:50:19.57#ibcon#enter sib2, iclass 15, count 0 2006.203.07:50:19.57#ibcon#flushed, iclass 15, count 0 2006.203.07:50:19.57#ibcon#about to write, iclass 15, count 0 2006.203.07:50:19.57#ibcon#wrote, iclass 15, count 0 2006.203.07:50:19.57#ibcon#about to read 3, iclass 15, count 0 2006.203.07:50:19.61#ibcon#read 3, iclass 15, count 0 2006.203.07:50:19.61#ibcon#about to read 4, iclass 15, count 0 2006.203.07:50:19.61#ibcon#read 4, iclass 15, count 0 2006.203.07:50:19.61#ibcon#about to read 5, iclass 15, count 0 2006.203.07:50:19.61#ibcon#read 5, iclass 15, count 0 2006.203.07:50:19.61#ibcon#about to read 6, iclass 15, count 0 2006.203.07:50:19.61#ibcon#read 6, iclass 15, count 0 2006.203.07:50:19.61#ibcon#end of sib2, iclass 15, count 0 2006.203.07:50:19.61#ibcon#*after write, iclass 15, count 0 2006.203.07:50:19.61#ibcon#*before return 0, iclass 15, count 0 2006.203.07:50:19.61#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.203.07:50:19.61#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.203.07:50:19.61#ibcon#about to clear, iclass 15 cls_cnt 0 2006.203.07:50:19.61#ibcon#cleared, iclass 15 cls_cnt 0 2006.203.07:50:19.61$vc4f8/va=2,7 2006.203.07:50:19.61#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.203.07:50:19.61#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.203.07:50:19.61#ibcon#ireg 11 cls_cnt 2 2006.203.07:50:19.61#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.203.07:50:19.68#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.203.07:50:19.68#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.203.07:50:19.68#ibcon#enter wrdev, iclass 17, count 2 2006.203.07:50:19.68#ibcon#first serial, iclass 17, count 2 2006.203.07:50:19.68#ibcon#enter sib2, iclass 17, count 2 2006.203.07:50:19.68#ibcon#flushed, iclass 17, count 2 2006.203.07:50:19.68#ibcon#about to write, iclass 17, count 2 2006.203.07:50:19.68#ibcon#wrote, iclass 17, count 2 2006.203.07:50:19.68#ibcon#about to read 3, iclass 17, count 2 2006.203.07:50:19.69#ibcon#read 3, iclass 17, count 2 2006.203.07:50:19.69#ibcon#about to read 4, iclass 17, count 2 2006.203.07:50:19.69#ibcon#read 4, iclass 17, count 2 2006.203.07:50:19.69#ibcon#about to read 5, iclass 17, count 2 2006.203.07:50:19.69#ibcon#read 5, iclass 17, count 2 2006.203.07:50:19.69#ibcon#about to read 6, iclass 17, count 2 2006.203.07:50:19.69#ibcon#read 6, iclass 17, count 2 2006.203.07:50:19.69#ibcon#end of sib2, iclass 17, count 2 2006.203.07:50:19.69#ibcon#*mode == 0, iclass 17, count 2 2006.203.07:50:19.69#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.203.07:50:19.69#ibcon#[25=AT02-07\r\n] 2006.203.07:50:19.69#ibcon#*before write, iclass 17, count 2 2006.203.07:50:19.69#ibcon#enter sib2, iclass 17, count 2 2006.203.07:50:19.69#ibcon#flushed, iclass 17, count 2 2006.203.07:50:19.69#ibcon#about to write, iclass 17, count 2 2006.203.07:50:19.69#ibcon#wrote, iclass 17, count 2 2006.203.07:50:19.69#ibcon#about to read 3, iclass 17, count 2 2006.203.07:50:19.72#ibcon#read 3, iclass 17, count 2 2006.203.07:50:19.72#ibcon#about to read 4, iclass 17, count 2 2006.203.07:50:19.72#ibcon#read 4, iclass 17, count 2 2006.203.07:50:19.72#ibcon#about to read 5, iclass 17, count 2 2006.203.07:50:19.72#ibcon#read 5, iclass 17, count 2 2006.203.07:50:19.72#ibcon#about to read 6, iclass 17, count 2 2006.203.07:50:19.72#ibcon#read 6, iclass 17, count 2 2006.203.07:50:19.72#ibcon#end of sib2, iclass 17, count 2 2006.203.07:50:19.72#ibcon#*after write, iclass 17, count 2 2006.203.07:50:19.72#ibcon#*before return 0, iclass 17, count 2 2006.203.07:50:19.72#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.203.07:50:19.72#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.203.07:50:19.72#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.203.07:50:19.72#ibcon#ireg 7 cls_cnt 0 2006.203.07:50:19.72#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.203.07:50:19.84#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.203.07:50:19.84#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.203.07:50:19.84#ibcon#enter wrdev, iclass 17, count 0 2006.203.07:50:19.84#ibcon#first serial, iclass 17, count 0 2006.203.07:50:19.84#ibcon#enter sib2, iclass 17, count 0 2006.203.07:50:19.84#ibcon#flushed, iclass 17, count 0 2006.203.07:50:19.84#ibcon#about to write, iclass 17, count 0 2006.203.07:50:19.84#ibcon#wrote, iclass 17, count 0 2006.203.07:50:19.84#ibcon#about to read 3, iclass 17, count 0 2006.203.07:50:19.86#ibcon#read 3, iclass 17, count 0 2006.203.07:50:19.86#ibcon#about to read 4, iclass 17, count 0 2006.203.07:50:19.86#ibcon#read 4, iclass 17, count 0 2006.203.07:50:19.86#ibcon#about to read 5, iclass 17, count 0 2006.203.07:50:19.86#ibcon#read 5, iclass 17, count 0 2006.203.07:50:19.86#ibcon#about to read 6, iclass 17, count 0 2006.203.07:50:19.86#ibcon#read 6, iclass 17, count 0 2006.203.07:50:19.86#ibcon#end of sib2, iclass 17, count 0 2006.203.07:50:19.86#ibcon#*mode == 0, iclass 17, count 0 2006.203.07:50:19.86#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.203.07:50:19.86#ibcon#[25=USB\r\n] 2006.203.07:50:19.86#ibcon#*before write, iclass 17, count 0 2006.203.07:50:19.86#ibcon#enter sib2, iclass 17, count 0 2006.203.07:50:19.86#ibcon#flushed, iclass 17, count 0 2006.203.07:50:19.86#ibcon#about to write, iclass 17, count 0 2006.203.07:50:19.86#ibcon#wrote, iclass 17, count 0 2006.203.07:50:19.86#ibcon#about to read 3, iclass 17, count 0 2006.203.07:50:19.89#ibcon#read 3, iclass 17, count 0 2006.203.07:50:19.89#ibcon#about to read 4, iclass 17, count 0 2006.203.07:50:19.89#ibcon#read 4, iclass 17, count 0 2006.203.07:50:19.89#ibcon#about to read 5, iclass 17, count 0 2006.203.07:50:19.89#ibcon#read 5, iclass 17, count 0 2006.203.07:50:19.89#ibcon#about to read 6, iclass 17, count 0 2006.203.07:50:19.89#ibcon#read 6, iclass 17, count 0 2006.203.07:50:19.89#ibcon#end of sib2, iclass 17, count 0 2006.203.07:50:19.89#ibcon#*after write, iclass 17, count 0 2006.203.07:50:19.89#ibcon#*before return 0, iclass 17, count 0 2006.203.07:50:19.89#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.203.07:50:19.89#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.203.07:50:19.89#ibcon#about to clear, iclass 17 cls_cnt 0 2006.203.07:50:19.89#ibcon#cleared, iclass 17 cls_cnt 0 2006.203.07:50:19.89$vc4f8/valo=3,672.99 2006.203.07:50:19.89#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.203.07:50:19.89#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.203.07:50:19.89#ibcon#ireg 17 cls_cnt 0 2006.203.07:50:19.89#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.203.07:50:19.89#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.203.07:50:19.89#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.203.07:50:19.89#ibcon#enter wrdev, iclass 20, count 0 2006.203.07:50:19.89#ibcon#first serial, iclass 20, count 0 2006.203.07:50:19.89#ibcon#enter sib2, iclass 20, count 0 2006.203.07:50:19.89#ibcon#flushed, iclass 20, count 0 2006.203.07:50:19.89#ibcon#about to write, iclass 20, count 0 2006.203.07:50:19.89#ibcon#wrote, iclass 20, count 0 2006.203.07:50:19.89#ibcon#about to read 3, iclass 20, count 0 2006.203.07:50:19.90#abcon#<5=/05 1.5 3.0 23.84 971001.1\r\n> 2006.203.07:50:19.91#ibcon#read 3, iclass 20, count 0 2006.203.07:50:19.91#ibcon#about to read 4, iclass 20, count 0 2006.203.07:50:19.91#ibcon#read 4, iclass 20, count 0 2006.203.07:50:19.91#ibcon#about to read 5, iclass 20, count 0 2006.203.07:50:19.91#ibcon#read 5, iclass 20, count 0 2006.203.07:50:19.91#ibcon#about to read 6, iclass 20, count 0 2006.203.07:50:19.91#ibcon#read 6, iclass 20, count 0 2006.203.07:50:19.91#ibcon#end of sib2, iclass 20, count 0 2006.203.07:50:19.91#ibcon#*mode == 0, iclass 20, count 0 2006.203.07:50:19.91#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.203.07:50:19.91#ibcon#[26=FRQ=03,672.99\r\n] 2006.203.07:50:19.91#ibcon#*before write, iclass 20, count 0 2006.203.07:50:19.91#ibcon#enter sib2, iclass 20, count 0 2006.203.07:50:19.91#ibcon#flushed, iclass 20, count 0 2006.203.07:50:19.91#ibcon#about to write, iclass 20, count 0 2006.203.07:50:19.91#ibcon#wrote, iclass 20, count 0 2006.203.07:50:19.91#ibcon#about to read 3, iclass 20, count 0 2006.203.07:50:19.92#abcon#{5=INTERFACE CLEAR} 2006.203.07:50:19.95#ibcon#read 3, iclass 20, count 0 2006.203.07:50:19.95#ibcon#about to read 4, iclass 20, count 0 2006.203.07:50:19.95#ibcon#read 4, iclass 20, count 0 2006.203.07:50:19.95#ibcon#about to read 5, iclass 20, count 0 2006.203.07:50:19.95#ibcon#read 5, iclass 20, count 0 2006.203.07:50:19.95#ibcon#about to read 6, iclass 20, count 0 2006.203.07:50:19.95#ibcon#read 6, iclass 20, count 0 2006.203.07:50:19.95#ibcon#end of sib2, iclass 20, count 0 2006.203.07:50:19.95#ibcon#*after write, iclass 20, count 0 2006.203.07:50:19.95#ibcon#*before return 0, iclass 20, count 0 2006.203.07:50:19.95#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.203.07:50:19.95#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.203.07:50:19.95#ibcon#about to clear, iclass 20 cls_cnt 0 2006.203.07:50:19.95#ibcon#cleared, iclass 20 cls_cnt 0 2006.203.07:50:19.95$vc4f8/va=3,8 2006.203.07:50:19.95#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.203.07:50:19.95#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.203.07:50:19.95#ibcon#ireg 11 cls_cnt 2 2006.203.07:50:19.95#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.203.07:50:19.98#abcon#[5=S1D000X0/0*\r\n] 2006.203.07:50:20.01#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.203.07:50:20.01#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.203.07:50:20.01#ibcon#enter wrdev, iclass 24, count 2 2006.203.07:50:20.01#ibcon#first serial, iclass 24, count 2 2006.203.07:50:20.01#ibcon#enter sib2, iclass 24, count 2 2006.203.07:50:20.01#ibcon#flushed, iclass 24, count 2 2006.203.07:50:20.01#ibcon#about to write, iclass 24, count 2 2006.203.07:50:20.01#ibcon#wrote, iclass 24, count 2 2006.203.07:50:20.01#ibcon#about to read 3, iclass 24, count 2 2006.203.07:50:20.04#ibcon#read 3, iclass 24, count 2 2006.203.07:50:20.04#ibcon#about to read 4, iclass 24, count 2 2006.203.07:50:20.04#ibcon#read 4, iclass 24, count 2 2006.203.07:50:20.04#ibcon#about to read 5, iclass 24, count 2 2006.203.07:50:20.04#ibcon#read 5, iclass 24, count 2 2006.203.07:50:20.04#ibcon#about to read 6, iclass 24, count 2 2006.203.07:50:20.04#ibcon#read 6, iclass 24, count 2 2006.203.07:50:20.04#ibcon#end of sib2, iclass 24, count 2 2006.203.07:50:20.04#ibcon#*mode == 0, iclass 24, count 2 2006.203.07:50:20.04#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.203.07:50:20.04#ibcon#[25=AT03-08\r\n] 2006.203.07:50:20.04#ibcon#*before write, iclass 24, count 2 2006.203.07:50:20.04#ibcon#enter sib2, iclass 24, count 2 2006.203.07:50:20.04#ibcon#flushed, iclass 24, count 2 2006.203.07:50:20.04#ibcon#about to write, iclass 24, count 2 2006.203.07:50:20.04#ibcon#wrote, iclass 24, count 2 2006.203.07:50:20.04#ibcon#about to read 3, iclass 24, count 2 2006.203.07:50:20.07#ibcon#read 3, iclass 24, count 2 2006.203.07:50:20.07#ibcon#about to read 4, iclass 24, count 2 2006.203.07:50:20.07#ibcon#read 4, iclass 24, count 2 2006.203.07:50:20.07#ibcon#about to read 5, iclass 24, count 2 2006.203.07:50:20.07#ibcon#read 5, iclass 24, count 2 2006.203.07:50:20.07#ibcon#about to read 6, iclass 24, count 2 2006.203.07:50:20.07#ibcon#read 6, iclass 24, count 2 2006.203.07:50:20.07#ibcon#end of sib2, iclass 24, count 2 2006.203.07:50:20.07#ibcon#*after write, iclass 24, count 2 2006.203.07:50:20.07#ibcon#*before return 0, iclass 24, count 2 2006.203.07:50:20.07#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.203.07:50:20.07#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.203.07:50:20.07#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.203.07:50:20.07#ibcon#ireg 7 cls_cnt 0 2006.203.07:50:20.07#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.203.07:50:20.19#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.203.07:50:20.19#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.203.07:50:20.19#ibcon#enter wrdev, iclass 24, count 0 2006.203.07:50:20.19#ibcon#first serial, iclass 24, count 0 2006.203.07:50:20.19#ibcon#enter sib2, iclass 24, count 0 2006.203.07:50:20.19#ibcon#flushed, iclass 24, count 0 2006.203.07:50:20.19#ibcon#about to write, iclass 24, count 0 2006.203.07:50:20.19#ibcon#wrote, iclass 24, count 0 2006.203.07:50:20.19#ibcon#about to read 3, iclass 24, count 0 2006.203.07:50:20.21#ibcon#read 3, iclass 24, count 0 2006.203.07:50:20.21#ibcon#about to read 4, iclass 24, count 0 2006.203.07:50:20.21#ibcon#read 4, iclass 24, count 0 2006.203.07:50:20.21#ibcon#about to read 5, iclass 24, count 0 2006.203.07:50:20.21#ibcon#read 5, iclass 24, count 0 2006.203.07:50:20.21#ibcon#about to read 6, iclass 24, count 0 2006.203.07:50:20.21#ibcon#read 6, iclass 24, count 0 2006.203.07:50:20.21#ibcon#end of sib2, iclass 24, count 0 2006.203.07:50:20.21#ibcon#*mode == 0, iclass 24, count 0 2006.203.07:50:20.21#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.203.07:50:20.21#ibcon#[25=USB\r\n] 2006.203.07:50:20.21#ibcon#*before write, iclass 24, count 0 2006.203.07:50:20.21#ibcon#enter sib2, iclass 24, count 0 2006.203.07:50:20.21#ibcon#flushed, iclass 24, count 0 2006.203.07:50:20.21#ibcon#about to write, iclass 24, count 0 2006.203.07:50:20.21#ibcon#wrote, iclass 24, count 0 2006.203.07:50:20.21#ibcon#about to read 3, iclass 24, count 0 2006.203.07:50:20.24#ibcon#read 3, iclass 24, count 0 2006.203.07:50:20.24#ibcon#about to read 4, iclass 24, count 0 2006.203.07:50:20.24#ibcon#read 4, iclass 24, count 0 2006.203.07:50:20.24#ibcon#about to read 5, iclass 24, count 0 2006.203.07:50:20.24#ibcon#read 5, iclass 24, count 0 2006.203.07:50:20.24#ibcon#about to read 6, iclass 24, count 0 2006.203.07:50:20.24#ibcon#read 6, iclass 24, count 0 2006.203.07:50:20.24#ibcon#end of sib2, iclass 24, count 0 2006.203.07:50:20.24#ibcon#*after write, iclass 24, count 0 2006.203.07:50:20.24#ibcon#*before return 0, iclass 24, count 0 2006.203.07:50:20.24#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.203.07:50:20.24#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.203.07:50:20.24#ibcon#about to clear, iclass 24 cls_cnt 0 2006.203.07:50:20.24#ibcon#cleared, iclass 24 cls_cnt 0 2006.203.07:50:20.24$vc4f8/valo=4,832.99 2006.203.07:50:20.24#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.203.07:50:20.24#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.203.07:50:20.24#ibcon#ireg 17 cls_cnt 0 2006.203.07:50:20.24#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:50:20.24#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:50:20.24#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:50:20.24#ibcon#enter wrdev, iclass 27, count 0 2006.203.07:50:20.24#ibcon#first serial, iclass 27, count 0 2006.203.07:50:20.24#ibcon#enter sib2, iclass 27, count 0 2006.203.07:50:20.24#ibcon#flushed, iclass 27, count 0 2006.203.07:50:20.24#ibcon#about to write, iclass 27, count 0 2006.203.07:50:20.24#ibcon#wrote, iclass 27, count 0 2006.203.07:50:20.24#ibcon#about to read 3, iclass 27, count 0 2006.203.07:50:20.26#ibcon#read 3, iclass 27, count 0 2006.203.07:50:20.26#ibcon#about to read 4, iclass 27, count 0 2006.203.07:50:20.26#ibcon#read 4, iclass 27, count 0 2006.203.07:50:20.26#ibcon#about to read 5, iclass 27, count 0 2006.203.07:50:20.26#ibcon#read 5, iclass 27, count 0 2006.203.07:50:20.26#ibcon#about to read 6, iclass 27, count 0 2006.203.07:50:20.26#ibcon#read 6, iclass 27, count 0 2006.203.07:50:20.26#ibcon#end of sib2, iclass 27, count 0 2006.203.07:50:20.26#ibcon#*mode == 0, iclass 27, count 0 2006.203.07:50:20.26#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.203.07:50:20.26#ibcon#[26=FRQ=04,832.99\r\n] 2006.203.07:50:20.26#ibcon#*before write, iclass 27, count 0 2006.203.07:50:20.26#ibcon#enter sib2, iclass 27, count 0 2006.203.07:50:20.26#ibcon#flushed, iclass 27, count 0 2006.203.07:50:20.26#ibcon#about to write, iclass 27, count 0 2006.203.07:50:20.26#ibcon#wrote, iclass 27, count 0 2006.203.07:50:20.26#ibcon#about to read 3, iclass 27, count 0 2006.203.07:50:20.30#ibcon#read 3, iclass 27, count 0 2006.203.07:50:20.30#ibcon#about to read 4, iclass 27, count 0 2006.203.07:50:20.30#ibcon#read 4, iclass 27, count 0 2006.203.07:50:20.30#ibcon#about to read 5, iclass 27, count 0 2006.203.07:50:20.30#ibcon#read 5, iclass 27, count 0 2006.203.07:50:20.30#ibcon#about to read 6, iclass 27, count 0 2006.203.07:50:20.30#ibcon#read 6, iclass 27, count 0 2006.203.07:50:20.30#ibcon#end of sib2, iclass 27, count 0 2006.203.07:50:20.30#ibcon#*after write, iclass 27, count 0 2006.203.07:50:20.30#ibcon#*before return 0, iclass 27, count 0 2006.203.07:50:20.30#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:50:20.30#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:50:20.30#ibcon#about to clear, iclass 27 cls_cnt 0 2006.203.07:50:20.30#ibcon#cleared, iclass 27 cls_cnt 0 2006.203.07:50:20.30$vc4f8/va=4,7 2006.203.07:50:20.30#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.203.07:50:20.30#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.203.07:50:20.30#ibcon#ireg 11 cls_cnt 2 2006.203.07:50:20.30#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.203.07:50:20.36#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.203.07:50:20.36#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.203.07:50:20.36#ibcon#enter wrdev, iclass 29, count 2 2006.203.07:50:20.36#ibcon#first serial, iclass 29, count 2 2006.203.07:50:20.36#ibcon#enter sib2, iclass 29, count 2 2006.203.07:50:20.36#ibcon#flushed, iclass 29, count 2 2006.203.07:50:20.36#ibcon#about to write, iclass 29, count 2 2006.203.07:50:20.36#ibcon#wrote, iclass 29, count 2 2006.203.07:50:20.36#ibcon#about to read 3, iclass 29, count 2 2006.203.07:50:20.38#ibcon#read 3, iclass 29, count 2 2006.203.07:50:20.38#ibcon#about to read 4, iclass 29, count 2 2006.203.07:50:20.38#ibcon#read 4, iclass 29, count 2 2006.203.07:50:20.38#ibcon#about to read 5, iclass 29, count 2 2006.203.07:50:20.38#ibcon#read 5, iclass 29, count 2 2006.203.07:50:20.38#ibcon#about to read 6, iclass 29, count 2 2006.203.07:50:20.38#ibcon#read 6, iclass 29, count 2 2006.203.07:50:20.38#ibcon#end of sib2, iclass 29, count 2 2006.203.07:50:20.38#ibcon#*mode == 0, iclass 29, count 2 2006.203.07:50:20.38#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.203.07:50:20.38#ibcon#[25=AT04-07\r\n] 2006.203.07:50:20.38#ibcon#*before write, iclass 29, count 2 2006.203.07:50:20.38#ibcon#enter sib2, iclass 29, count 2 2006.203.07:50:20.38#ibcon#flushed, iclass 29, count 2 2006.203.07:50:20.38#ibcon#about to write, iclass 29, count 2 2006.203.07:50:20.38#ibcon#wrote, iclass 29, count 2 2006.203.07:50:20.38#ibcon#about to read 3, iclass 29, count 2 2006.203.07:50:20.41#ibcon#read 3, iclass 29, count 2 2006.203.07:50:20.41#ibcon#about to read 4, iclass 29, count 2 2006.203.07:50:20.41#ibcon#read 4, iclass 29, count 2 2006.203.07:50:20.41#ibcon#about to read 5, iclass 29, count 2 2006.203.07:50:20.41#ibcon#read 5, iclass 29, count 2 2006.203.07:50:20.41#ibcon#about to read 6, iclass 29, count 2 2006.203.07:50:20.41#ibcon#read 6, iclass 29, count 2 2006.203.07:50:20.41#ibcon#end of sib2, iclass 29, count 2 2006.203.07:50:20.41#ibcon#*after write, iclass 29, count 2 2006.203.07:50:20.41#ibcon#*before return 0, iclass 29, count 2 2006.203.07:50:20.41#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.203.07:50:20.41#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.203.07:50:20.41#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.203.07:50:20.41#ibcon#ireg 7 cls_cnt 0 2006.203.07:50:20.41#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.203.07:50:20.53#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.203.07:50:20.53#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.203.07:50:20.53#ibcon#enter wrdev, iclass 29, count 0 2006.203.07:50:20.53#ibcon#first serial, iclass 29, count 0 2006.203.07:50:20.53#ibcon#enter sib2, iclass 29, count 0 2006.203.07:50:20.53#ibcon#flushed, iclass 29, count 0 2006.203.07:50:20.53#ibcon#about to write, iclass 29, count 0 2006.203.07:50:20.53#ibcon#wrote, iclass 29, count 0 2006.203.07:50:20.53#ibcon#about to read 3, iclass 29, count 0 2006.203.07:50:20.55#ibcon#read 3, iclass 29, count 0 2006.203.07:50:20.55#ibcon#about to read 4, iclass 29, count 0 2006.203.07:50:20.55#ibcon#read 4, iclass 29, count 0 2006.203.07:50:20.55#ibcon#about to read 5, iclass 29, count 0 2006.203.07:50:20.55#ibcon#read 5, iclass 29, count 0 2006.203.07:50:20.55#ibcon#about to read 6, iclass 29, count 0 2006.203.07:50:20.55#ibcon#read 6, iclass 29, count 0 2006.203.07:50:20.55#ibcon#end of sib2, iclass 29, count 0 2006.203.07:50:20.55#ibcon#*mode == 0, iclass 29, count 0 2006.203.07:50:20.55#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.203.07:50:20.55#ibcon#[25=USB\r\n] 2006.203.07:50:20.55#ibcon#*before write, iclass 29, count 0 2006.203.07:50:20.55#ibcon#enter sib2, iclass 29, count 0 2006.203.07:50:20.55#ibcon#flushed, iclass 29, count 0 2006.203.07:50:20.55#ibcon#about to write, iclass 29, count 0 2006.203.07:50:20.55#ibcon#wrote, iclass 29, count 0 2006.203.07:50:20.55#ibcon#about to read 3, iclass 29, count 0 2006.203.07:50:20.58#ibcon#read 3, iclass 29, count 0 2006.203.07:50:20.58#ibcon#about to read 4, iclass 29, count 0 2006.203.07:50:20.58#ibcon#read 4, iclass 29, count 0 2006.203.07:50:20.58#ibcon#about to read 5, iclass 29, count 0 2006.203.07:50:20.58#ibcon#read 5, iclass 29, count 0 2006.203.07:50:20.58#ibcon#about to read 6, iclass 29, count 0 2006.203.07:50:20.58#ibcon#read 6, iclass 29, count 0 2006.203.07:50:20.58#ibcon#end of sib2, iclass 29, count 0 2006.203.07:50:20.58#ibcon#*after write, iclass 29, count 0 2006.203.07:50:20.58#ibcon#*before return 0, iclass 29, count 0 2006.203.07:50:20.58#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.203.07:50:20.58#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.203.07:50:20.58#ibcon#about to clear, iclass 29 cls_cnt 0 2006.203.07:50:20.58#ibcon#cleared, iclass 29 cls_cnt 0 2006.203.07:50:20.58$vc4f8/valo=5,652.99 2006.203.07:50:20.58#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.203.07:50:20.58#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.203.07:50:20.58#ibcon#ireg 17 cls_cnt 0 2006.203.07:50:20.58#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.203.07:50:20.58#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.203.07:50:20.58#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.203.07:50:20.58#ibcon#enter wrdev, iclass 31, count 0 2006.203.07:50:20.58#ibcon#first serial, iclass 31, count 0 2006.203.07:50:20.58#ibcon#enter sib2, iclass 31, count 0 2006.203.07:50:20.58#ibcon#flushed, iclass 31, count 0 2006.203.07:50:20.58#ibcon#about to write, iclass 31, count 0 2006.203.07:50:20.58#ibcon#wrote, iclass 31, count 0 2006.203.07:50:20.58#ibcon#about to read 3, iclass 31, count 0 2006.203.07:50:20.60#ibcon#read 3, iclass 31, count 0 2006.203.07:50:20.60#ibcon#about to read 4, iclass 31, count 0 2006.203.07:50:20.60#ibcon#read 4, iclass 31, count 0 2006.203.07:50:20.60#ibcon#about to read 5, iclass 31, count 0 2006.203.07:50:20.60#ibcon#read 5, iclass 31, count 0 2006.203.07:50:20.60#ibcon#about to read 6, iclass 31, count 0 2006.203.07:50:20.60#ibcon#read 6, iclass 31, count 0 2006.203.07:50:20.60#ibcon#end of sib2, iclass 31, count 0 2006.203.07:50:20.60#ibcon#*mode == 0, iclass 31, count 0 2006.203.07:50:20.60#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.203.07:50:20.60#ibcon#[26=FRQ=05,652.99\r\n] 2006.203.07:50:20.60#ibcon#*before write, iclass 31, count 0 2006.203.07:50:20.60#ibcon#enter sib2, iclass 31, count 0 2006.203.07:50:20.60#ibcon#flushed, iclass 31, count 0 2006.203.07:50:20.60#ibcon#about to write, iclass 31, count 0 2006.203.07:50:20.60#ibcon#wrote, iclass 31, count 0 2006.203.07:50:20.60#ibcon#about to read 3, iclass 31, count 0 2006.203.07:50:20.64#ibcon#read 3, iclass 31, count 0 2006.203.07:50:20.64#ibcon#about to read 4, iclass 31, count 0 2006.203.07:50:20.64#ibcon#read 4, iclass 31, count 0 2006.203.07:50:20.64#ibcon#about to read 5, iclass 31, count 0 2006.203.07:50:20.64#ibcon#read 5, iclass 31, count 0 2006.203.07:50:20.64#ibcon#about to read 6, iclass 31, count 0 2006.203.07:50:20.64#ibcon#read 6, iclass 31, count 0 2006.203.07:50:20.64#ibcon#end of sib2, iclass 31, count 0 2006.203.07:50:20.64#ibcon#*after write, iclass 31, count 0 2006.203.07:50:20.64#ibcon#*before return 0, iclass 31, count 0 2006.203.07:50:20.64#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.203.07:50:20.64#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.203.07:50:20.64#ibcon#about to clear, iclass 31 cls_cnt 0 2006.203.07:50:20.64#ibcon#cleared, iclass 31 cls_cnt 0 2006.203.07:50:20.64$vc4f8/va=5,7 2006.203.07:50:20.64#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.203.07:50:20.64#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.203.07:50:20.64#ibcon#ireg 11 cls_cnt 2 2006.203.07:50:20.64#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.203.07:50:20.70#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.203.07:50:20.70#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.203.07:50:20.70#ibcon#enter wrdev, iclass 33, count 2 2006.203.07:50:20.70#ibcon#first serial, iclass 33, count 2 2006.203.07:50:20.70#ibcon#enter sib2, iclass 33, count 2 2006.203.07:50:20.70#ibcon#flushed, iclass 33, count 2 2006.203.07:50:20.70#ibcon#about to write, iclass 33, count 2 2006.203.07:50:20.70#ibcon#wrote, iclass 33, count 2 2006.203.07:50:20.70#ibcon#about to read 3, iclass 33, count 2 2006.203.07:50:20.72#ibcon#read 3, iclass 33, count 2 2006.203.07:50:20.72#ibcon#about to read 4, iclass 33, count 2 2006.203.07:50:20.72#ibcon#read 4, iclass 33, count 2 2006.203.07:50:20.72#ibcon#about to read 5, iclass 33, count 2 2006.203.07:50:20.72#ibcon#read 5, iclass 33, count 2 2006.203.07:50:20.72#ibcon#about to read 6, iclass 33, count 2 2006.203.07:50:20.72#ibcon#read 6, iclass 33, count 2 2006.203.07:50:20.72#ibcon#end of sib2, iclass 33, count 2 2006.203.07:50:20.72#ibcon#*mode == 0, iclass 33, count 2 2006.203.07:50:20.72#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.203.07:50:20.72#ibcon#[25=AT05-07\r\n] 2006.203.07:50:20.72#ibcon#*before write, iclass 33, count 2 2006.203.07:50:20.72#ibcon#enter sib2, iclass 33, count 2 2006.203.07:50:20.72#ibcon#flushed, iclass 33, count 2 2006.203.07:50:20.72#ibcon#about to write, iclass 33, count 2 2006.203.07:50:20.72#ibcon#wrote, iclass 33, count 2 2006.203.07:50:20.72#ibcon#about to read 3, iclass 33, count 2 2006.203.07:50:20.75#ibcon#read 3, iclass 33, count 2 2006.203.07:50:20.75#ibcon#about to read 4, iclass 33, count 2 2006.203.07:50:20.75#ibcon#read 4, iclass 33, count 2 2006.203.07:50:20.75#ibcon#about to read 5, iclass 33, count 2 2006.203.07:50:20.75#ibcon#read 5, iclass 33, count 2 2006.203.07:50:20.75#ibcon#about to read 6, iclass 33, count 2 2006.203.07:50:20.75#ibcon#read 6, iclass 33, count 2 2006.203.07:50:20.75#ibcon#end of sib2, iclass 33, count 2 2006.203.07:50:20.75#ibcon#*after write, iclass 33, count 2 2006.203.07:50:20.75#ibcon#*before return 0, iclass 33, count 2 2006.203.07:50:20.75#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.203.07:50:20.75#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.203.07:50:20.75#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.203.07:50:20.75#ibcon#ireg 7 cls_cnt 0 2006.203.07:50:20.75#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.203.07:50:20.87#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.203.07:50:20.87#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.203.07:50:20.87#ibcon#enter wrdev, iclass 33, count 0 2006.203.07:50:20.87#ibcon#first serial, iclass 33, count 0 2006.203.07:50:20.87#ibcon#enter sib2, iclass 33, count 0 2006.203.07:50:20.87#ibcon#flushed, iclass 33, count 0 2006.203.07:50:20.87#ibcon#about to write, iclass 33, count 0 2006.203.07:50:20.87#ibcon#wrote, iclass 33, count 0 2006.203.07:50:20.87#ibcon#about to read 3, iclass 33, count 0 2006.203.07:50:20.89#ibcon#read 3, iclass 33, count 0 2006.203.07:50:20.89#ibcon#about to read 4, iclass 33, count 0 2006.203.07:50:20.89#ibcon#read 4, iclass 33, count 0 2006.203.07:50:20.89#ibcon#about to read 5, iclass 33, count 0 2006.203.07:50:20.89#ibcon#read 5, iclass 33, count 0 2006.203.07:50:20.89#ibcon#about to read 6, iclass 33, count 0 2006.203.07:50:20.89#ibcon#read 6, iclass 33, count 0 2006.203.07:50:20.89#ibcon#end of sib2, iclass 33, count 0 2006.203.07:50:20.89#ibcon#*mode == 0, iclass 33, count 0 2006.203.07:50:20.89#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.203.07:50:20.89#ibcon#[25=USB\r\n] 2006.203.07:50:20.89#ibcon#*before write, iclass 33, count 0 2006.203.07:50:20.89#ibcon#enter sib2, iclass 33, count 0 2006.203.07:50:20.89#ibcon#flushed, iclass 33, count 0 2006.203.07:50:20.89#ibcon#about to write, iclass 33, count 0 2006.203.07:50:20.89#ibcon#wrote, iclass 33, count 0 2006.203.07:50:20.89#ibcon#about to read 3, iclass 33, count 0 2006.203.07:50:20.92#ibcon#read 3, iclass 33, count 0 2006.203.07:50:20.92#ibcon#about to read 4, iclass 33, count 0 2006.203.07:50:20.92#ibcon#read 4, iclass 33, count 0 2006.203.07:50:20.92#ibcon#about to read 5, iclass 33, count 0 2006.203.07:50:20.92#ibcon#read 5, iclass 33, count 0 2006.203.07:50:20.92#ibcon#about to read 6, iclass 33, count 0 2006.203.07:50:20.92#ibcon#read 6, iclass 33, count 0 2006.203.07:50:20.92#ibcon#end of sib2, iclass 33, count 0 2006.203.07:50:20.92#ibcon#*after write, iclass 33, count 0 2006.203.07:50:20.92#ibcon#*before return 0, iclass 33, count 0 2006.203.07:50:20.92#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.203.07:50:20.92#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.203.07:50:20.92#ibcon#about to clear, iclass 33 cls_cnt 0 2006.203.07:50:20.92#ibcon#cleared, iclass 33 cls_cnt 0 2006.203.07:50:20.92$vc4f8/valo=6,772.99 2006.203.07:50:20.92#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.203.07:50:20.92#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.203.07:50:20.92#ibcon#ireg 17 cls_cnt 0 2006.203.07:50:20.92#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.203.07:50:20.92#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.203.07:50:20.92#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.203.07:50:20.92#ibcon#enter wrdev, iclass 35, count 0 2006.203.07:50:20.92#ibcon#first serial, iclass 35, count 0 2006.203.07:50:20.92#ibcon#enter sib2, iclass 35, count 0 2006.203.07:50:20.92#ibcon#flushed, iclass 35, count 0 2006.203.07:50:20.92#ibcon#about to write, iclass 35, count 0 2006.203.07:50:20.92#ibcon#wrote, iclass 35, count 0 2006.203.07:50:20.92#ibcon#about to read 3, iclass 35, count 0 2006.203.07:50:20.94#ibcon#read 3, iclass 35, count 0 2006.203.07:50:20.94#ibcon#about to read 4, iclass 35, count 0 2006.203.07:50:20.94#ibcon#read 4, iclass 35, count 0 2006.203.07:50:20.94#ibcon#about to read 5, iclass 35, count 0 2006.203.07:50:20.94#ibcon#read 5, iclass 35, count 0 2006.203.07:50:20.94#ibcon#about to read 6, iclass 35, count 0 2006.203.07:50:20.94#ibcon#read 6, iclass 35, count 0 2006.203.07:50:20.94#ibcon#end of sib2, iclass 35, count 0 2006.203.07:50:20.94#ibcon#*mode == 0, iclass 35, count 0 2006.203.07:50:20.94#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.203.07:50:20.94#ibcon#[26=FRQ=06,772.99\r\n] 2006.203.07:50:20.94#ibcon#*before write, iclass 35, count 0 2006.203.07:50:20.94#ibcon#enter sib2, iclass 35, count 0 2006.203.07:50:20.94#ibcon#flushed, iclass 35, count 0 2006.203.07:50:20.94#ibcon#about to write, iclass 35, count 0 2006.203.07:50:20.94#ibcon#wrote, iclass 35, count 0 2006.203.07:50:20.94#ibcon#about to read 3, iclass 35, count 0 2006.203.07:50:20.98#ibcon#read 3, iclass 35, count 0 2006.203.07:50:20.98#ibcon#about to read 4, iclass 35, count 0 2006.203.07:50:20.98#ibcon#read 4, iclass 35, count 0 2006.203.07:50:20.98#ibcon#about to read 5, iclass 35, count 0 2006.203.07:50:20.98#ibcon#read 5, iclass 35, count 0 2006.203.07:50:20.98#ibcon#about to read 6, iclass 35, count 0 2006.203.07:50:20.98#ibcon#read 6, iclass 35, count 0 2006.203.07:50:20.98#ibcon#end of sib2, iclass 35, count 0 2006.203.07:50:20.98#ibcon#*after write, iclass 35, count 0 2006.203.07:50:20.98#ibcon#*before return 0, iclass 35, count 0 2006.203.07:50:20.98#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.203.07:50:20.98#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.203.07:50:20.98#ibcon#about to clear, iclass 35 cls_cnt 0 2006.203.07:50:20.98#ibcon#cleared, iclass 35 cls_cnt 0 2006.203.07:50:20.98$vc4f8/va=6,6 2006.203.07:50:20.98#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.203.07:50:20.98#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.203.07:50:20.98#ibcon#ireg 11 cls_cnt 2 2006.203.07:50:20.98#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.203.07:50:21.05#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.203.07:50:21.05#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.203.07:50:21.05#ibcon#enter wrdev, iclass 37, count 2 2006.203.07:50:21.05#ibcon#first serial, iclass 37, count 2 2006.203.07:50:21.05#ibcon#enter sib2, iclass 37, count 2 2006.203.07:50:21.05#ibcon#flushed, iclass 37, count 2 2006.203.07:50:21.05#ibcon#about to write, iclass 37, count 2 2006.203.07:50:21.05#ibcon#wrote, iclass 37, count 2 2006.203.07:50:21.05#ibcon#about to read 3, iclass 37, count 2 2006.203.07:50:21.06#ibcon#read 3, iclass 37, count 2 2006.203.07:50:21.06#ibcon#about to read 4, iclass 37, count 2 2006.203.07:50:21.06#ibcon#read 4, iclass 37, count 2 2006.203.07:50:21.06#ibcon#about to read 5, iclass 37, count 2 2006.203.07:50:21.06#ibcon#read 5, iclass 37, count 2 2006.203.07:50:21.06#ibcon#about to read 6, iclass 37, count 2 2006.203.07:50:21.06#ibcon#read 6, iclass 37, count 2 2006.203.07:50:21.06#ibcon#end of sib2, iclass 37, count 2 2006.203.07:50:21.06#ibcon#*mode == 0, iclass 37, count 2 2006.203.07:50:21.06#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.203.07:50:21.06#ibcon#[25=AT06-06\r\n] 2006.203.07:50:21.06#ibcon#*before write, iclass 37, count 2 2006.203.07:50:21.06#ibcon#enter sib2, iclass 37, count 2 2006.203.07:50:21.06#ibcon#flushed, iclass 37, count 2 2006.203.07:50:21.06#ibcon#about to write, iclass 37, count 2 2006.203.07:50:21.06#ibcon#wrote, iclass 37, count 2 2006.203.07:50:21.06#ibcon#about to read 3, iclass 37, count 2 2006.203.07:50:21.09#ibcon#read 3, iclass 37, count 2 2006.203.07:50:21.09#ibcon#about to read 4, iclass 37, count 2 2006.203.07:50:21.09#ibcon#read 4, iclass 37, count 2 2006.203.07:50:21.09#ibcon#about to read 5, iclass 37, count 2 2006.203.07:50:21.09#ibcon#read 5, iclass 37, count 2 2006.203.07:50:21.09#ibcon#about to read 6, iclass 37, count 2 2006.203.07:50:21.09#ibcon#read 6, iclass 37, count 2 2006.203.07:50:21.09#ibcon#end of sib2, iclass 37, count 2 2006.203.07:50:21.09#ibcon#*after write, iclass 37, count 2 2006.203.07:50:21.09#ibcon#*before return 0, iclass 37, count 2 2006.203.07:50:21.09#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.203.07:50:21.09#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.203.07:50:21.09#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.203.07:50:21.09#ibcon#ireg 7 cls_cnt 0 2006.203.07:50:21.09#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.203.07:50:21.21#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.203.07:50:21.21#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.203.07:50:21.21#ibcon#enter wrdev, iclass 37, count 0 2006.203.07:50:21.21#ibcon#first serial, iclass 37, count 0 2006.203.07:50:21.21#ibcon#enter sib2, iclass 37, count 0 2006.203.07:50:21.21#ibcon#flushed, iclass 37, count 0 2006.203.07:50:21.21#ibcon#about to write, iclass 37, count 0 2006.203.07:50:21.21#ibcon#wrote, iclass 37, count 0 2006.203.07:50:21.21#ibcon#about to read 3, iclass 37, count 0 2006.203.07:50:21.23#ibcon#read 3, iclass 37, count 0 2006.203.07:50:21.23#ibcon#about to read 4, iclass 37, count 0 2006.203.07:50:21.23#ibcon#read 4, iclass 37, count 0 2006.203.07:50:21.23#ibcon#about to read 5, iclass 37, count 0 2006.203.07:50:21.23#ibcon#read 5, iclass 37, count 0 2006.203.07:50:21.23#ibcon#about to read 6, iclass 37, count 0 2006.203.07:50:21.23#ibcon#read 6, iclass 37, count 0 2006.203.07:50:21.23#ibcon#end of sib2, iclass 37, count 0 2006.203.07:50:21.23#ibcon#*mode == 0, iclass 37, count 0 2006.203.07:50:21.23#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.203.07:50:21.23#ibcon#[25=USB\r\n] 2006.203.07:50:21.23#ibcon#*before write, iclass 37, count 0 2006.203.07:50:21.23#ibcon#enter sib2, iclass 37, count 0 2006.203.07:50:21.23#ibcon#flushed, iclass 37, count 0 2006.203.07:50:21.23#ibcon#about to write, iclass 37, count 0 2006.203.07:50:21.23#ibcon#wrote, iclass 37, count 0 2006.203.07:50:21.23#ibcon#about to read 3, iclass 37, count 0 2006.203.07:50:21.26#ibcon#read 3, iclass 37, count 0 2006.203.07:50:21.26#ibcon#about to read 4, iclass 37, count 0 2006.203.07:50:21.26#ibcon#read 4, iclass 37, count 0 2006.203.07:50:21.26#ibcon#about to read 5, iclass 37, count 0 2006.203.07:50:21.26#ibcon#read 5, iclass 37, count 0 2006.203.07:50:21.26#ibcon#about to read 6, iclass 37, count 0 2006.203.07:50:21.26#ibcon#read 6, iclass 37, count 0 2006.203.07:50:21.26#ibcon#end of sib2, iclass 37, count 0 2006.203.07:50:21.26#ibcon#*after write, iclass 37, count 0 2006.203.07:50:21.26#ibcon#*before return 0, iclass 37, count 0 2006.203.07:50:21.26#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.203.07:50:21.26#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.203.07:50:21.26#ibcon#about to clear, iclass 37 cls_cnt 0 2006.203.07:50:21.26#ibcon#cleared, iclass 37 cls_cnt 0 2006.203.07:50:21.26$vc4f8/valo=7,832.99 2006.203.07:50:21.26#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.203.07:50:21.26#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.203.07:50:21.26#ibcon#ireg 17 cls_cnt 0 2006.203.07:50:21.26#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.203.07:50:21.26#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.203.07:50:21.26#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.203.07:50:21.26#ibcon#enter wrdev, iclass 39, count 0 2006.203.07:50:21.26#ibcon#first serial, iclass 39, count 0 2006.203.07:50:21.26#ibcon#enter sib2, iclass 39, count 0 2006.203.07:50:21.26#ibcon#flushed, iclass 39, count 0 2006.203.07:50:21.26#ibcon#about to write, iclass 39, count 0 2006.203.07:50:21.26#ibcon#wrote, iclass 39, count 0 2006.203.07:50:21.26#ibcon#about to read 3, iclass 39, count 0 2006.203.07:50:21.28#ibcon#read 3, iclass 39, count 0 2006.203.07:50:21.28#ibcon#about to read 4, iclass 39, count 0 2006.203.07:50:21.28#ibcon#read 4, iclass 39, count 0 2006.203.07:50:21.28#ibcon#about to read 5, iclass 39, count 0 2006.203.07:50:21.28#ibcon#read 5, iclass 39, count 0 2006.203.07:50:21.28#ibcon#about to read 6, iclass 39, count 0 2006.203.07:50:21.28#ibcon#read 6, iclass 39, count 0 2006.203.07:50:21.28#ibcon#end of sib2, iclass 39, count 0 2006.203.07:50:21.28#ibcon#*mode == 0, iclass 39, count 0 2006.203.07:50:21.28#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.203.07:50:21.28#ibcon#[26=FRQ=07,832.99\r\n] 2006.203.07:50:21.28#ibcon#*before write, iclass 39, count 0 2006.203.07:50:21.28#ibcon#enter sib2, iclass 39, count 0 2006.203.07:50:21.28#ibcon#flushed, iclass 39, count 0 2006.203.07:50:21.28#ibcon#about to write, iclass 39, count 0 2006.203.07:50:21.28#ibcon#wrote, iclass 39, count 0 2006.203.07:50:21.28#ibcon#about to read 3, iclass 39, count 0 2006.203.07:50:21.32#ibcon#read 3, iclass 39, count 0 2006.203.07:50:21.32#ibcon#about to read 4, iclass 39, count 0 2006.203.07:50:21.32#ibcon#read 4, iclass 39, count 0 2006.203.07:50:21.32#ibcon#about to read 5, iclass 39, count 0 2006.203.07:50:21.32#ibcon#read 5, iclass 39, count 0 2006.203.07:50:21.32#ibcon#about to read 6, iclass 39, count 0 2006.203.07:50:21.32#ibcon#read 6, iclass 39, count 0 2006.203.07:50:21.32#ibcon#end of sib2, iclass 39, count 0 2006.203.07:50:21.32#ibcon#*after write, iclass 39, count 0 2006.203.07:50:21.32#ibcon#*before return 0, iclass 39, count 0 2006.203.07:50:21.32#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.203.07:50:21.32#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.203.07:50:21.32#ibcon#about to clear, iclass 39 cls_cnt 0 2006.203.07:50:21.32#ibcon#cleared, iclass 39 cls_cnt 0 2006.203.07:50:21.32$vc4f8/va=7,7 2006.203.07:50:21.32#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.203.07:50:21.32#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.203.07:50:21.32#ibcon#ireg 11 cls_cnt 2 2006.203.07:50:21.32#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.203.07:50:21.38#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.203.07:50:21.38#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.203.07:50:21.38#ibcon#enter wrdev, iclass 3, count 2 2006.203.07:50:21.38#ibcon#first serial, iclass 3, count 2 2006.203.07:50:21.38#ibcon#enter sib2, iclass 3, count 2 2006.203.07:50:21.38#ibcon#flushed, iclass 3, count 2 2006.203.07:50:21.38#ibcon#about to write, iclass 3, count 2 2006.203.07:50:21.38#ibcon#wrote, iclass 3, count 2 2006.203.07:50:21.38#ibcon#about to read 3, iclass 3, count 2 2006.203.07:50:21.40#ibcon#read 3, iclass 3, count 2 2006.203.07:50:21.40#ibcon#about to read 4, iclass 3, count 2 2006.203.07:50:21.40#ibcon#read 4, iclass 3, count 2 2006.203.07:50:21.40#ibcon#about to read 5, iclass 3, count 2 2006.203.07:50:21.40#ibcon#read 5, iclass 3, count 2 2006.203.07:50:21.40#ibcon#about to read 6, iclass 3, count 2 2006.203.07:50:21.40#ibcon#read 6, iclass 3, count 2 2006.203.07:50:21.40#ibcon#end of sib2, iclass 3, count 2 2006.203.07:50:21.40#ibcon#*mode == 0, iclass 3, count 2 2006.203.07:50:21.40#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.203.07:50:21.40#ibcon#[25=AT07-07\r\n] 2006.203.07:50:21.40#ibcon#*before write, iclass 3, count 2 2006.203.07:50:21.40#ibcon#enter sib2, iclass 3, count 2 2006.203.07:50:21.40#ibcon#flushed, iclass 3, count 2 2006.203.07:50:21.40#ibcon#about to write, iclass 3, count 2 2006.203.07:50:21.40#ibcon#wrote, iclass 3, count 2 2006.203.07:50:21.40#ibcon#about to read 3, iclass 3, count 2 2006.203.07:50:21.43#ibcon#read 3, iclass 3, count 2 2006.203.07:50:21.43#ibcon#about to read 4, iclass 3, count 2 2006.203.07:50:21.43#ibcon#read 4, iclass 3, count 2 2006.203.07:50:21.43#ibcon#about to read 5, iclass 3, count 2 2006.203.07:50:21.43#ibcon#read 5, iclass 3, count 2 2006.203.07:50:21.43#ibcon#about to read 6, iclass 3, count 2 2006.203.07:50:21.43#ibcon#read 6, iclass 3, count 2 2006.203.07:50:21.43#ibcon#end of sib2, iclass 3, count 2 2006.203.07:50:21.43#ibcon#*after write, iclass 3, count 2 2006.203.07:50:21.43#ibcon#*before return 0, iclass 3, count 2 2006.203.07:50:21.43#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.203.07:50:21.43#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.203.07:50:21.43#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.203.07:50:21.43#ibcon#ireg 7 cls_cnt 0 2006.203.07:50:21.43#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.203.07:50:21.55#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.203.07:50:21.55#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.203.07:50:21.55#ibcon#enter wrdev, iclass 3, count 0 2006.203.07:50:21.55#ibcon#first serial, iclass 3, count 0 2006.203.07:50:21.55#ibcon#enter sib2, iclass 3, count 0 2006.203.07:50:21.55#ibcon#flushed, iclass 3, count 0 2006.203.07:50:21.55#ibcon#about to write, iclass 3, count 0 2006.203.07:50:21.55#ibcon#wrote, iclass 3, count 0 2006.203.07:50:21.55#ibcon#about to read 3, iclass 3, count 0 2006.203.07:50:21.57#ibcon#read 3, iclass 3, count 0 2006.203.07:50:21.57#ibcon#about to read 4, iclass 3, count 0 2006.203.07:50:21.57#ibcon#read 4, iclass 3, count 0 2006.203.07:50:21.57#ibcon#about to read 5, iclass 3, count 0 2006.203.07:50:21.57#ibcon#read 5, iclass 3, count 0 2006.203.07:50:21.57#ibcon#about to read 6, iclass 3, count 0 2006.203.07:50:21.57#ibcon#read 6, iclass 3, count 0 2006.203.07:50:21.57#ibcon#end of sib2, iclass 3, count 0 2006.203.07:50:21.57#ibcon#*mode == 0, iclass 3, count 0 2006.203.07:50:21.57#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.203.07:50:21.57#ibcon#[25=USB\r\n] 2006.203.07:50:21.57#ibcon#*before write, iclass 3, count 0 2006.203.07:50:21.57#ibcon#enter sib2, iclass 3, count 0 2006.203.07:50:21.57#ibcon#flushed, iclass 3, count 0 2006.203.07:50:21.57#ibcon#about to write, iclass 3, count 0 2006.203.07:50:21.57#ibcon#wrote, iclass 3, count 0 2006.203.07:50:21.57#ibcon#about to read 3, iclass 3, count 0 2006.203.07:50:21.60#ibcon#read 3, iclass 3, count 0 2006.203.07:50:21.60#ibcon#about to read 4, iclass 3, count 0 2006.203.07:50:21.60#ibcon#read 4, iclass 3, count 0 2006.203.07:50:21.60#ibcon#about to read 5, iclass 3, count 0 2006.203.07:50:21.60#ibcon#read 5, iclass 3, count 0 2006.203.07:50:21.60#ibcon#about to read 6, iclass 3, count 0 2006.203.07:50:21.60#ibcon#read 6, iclass 3, count 0 2006.203.07:50:21.60#ibcon#end of sib2, iclass 3, count 0 2006.203.07:50:21.60#ibcon#*after write, iclass 3, count 0 2006.203.07:50:21.60#ibcon#*before return 0, iclass 3, count 0 2006.203.07:50:21.60#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.203.07:50:21.60#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.203.07:50:21.60#ibcon#about to clear, iclass 3 cls_cnt 0 2006.203.07:50:21.60#ibcon#cleared, iclass 3 cls_cnt 0 2006.203.07:50:21.60$vc4f8/valo=8,852.99 2006.203.07:50:21.60#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.203.07:50:21.60#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.203.07:50:21.60#ibcon#ireg 17 cls_cnt 0 2006.203.07:50:21.60#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.203.07:50:21.60#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.203.07:50:21.60#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.203.07:50:21.60#ibcon#enter wrdev, iclass 5, count 0 2006.203.07:50:21.60#ibcon#first serial, iclass 5, count 0 2006.203.07:50:21.60#ibcon#enter sib2, iclass 5, count 0 2006.203.07:50:21.60#ibcon#flushed, iclass 5, count 0 2006.203.07:50:21.60#ibcon#about to write, iclass 5, count 0 2006.203.07:50:21.60#ibcon#wrote, iclass 5, count 0 2006.203.07:50:21.60#ibcon#about to read 3, iclass 5, count 0 2006.203.07:50:21.62#ibcon#read 3, iclass 5, count 0 2006.203.07:50:21.62#ibcon#about to read 4, iclass 5, count 0 2006.203.07:50:21.62#ibcon#read 4, iclass 5, count 0 2006.203.07:50:21.62#ibcon#about to read 5, iclass 5, count 0 2006.203.07:50:21.62#ibcon#read 5, iclass 5, count 0 2006.203.07:50:21.62#ibcon#about to read 6, iclass 5, count 0 2006.203.07:50:21.62#ibcon#read 6, iclass 5, count 0 2006.203.07:50:21.62#ibcon#end of sib2, iclass 5, count 0 2006.203.07:50:21.62#ibcon#*mode == 0, iclass 5, count 0 2006.203.07:50:21.62#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.203.07:50:21.62#ibcon#[26=FRQ=08,852.99\r\n] 2006.203.07:50:21.62#ibcon#*before write, iclass 5, count 0 2006.203.07:50:21.62#ibcon#enter sib2, iclass 5, count 0 2006.203.07:50:21.62#ibcon#flushed, iclass 5, count 0 2006.203.07:50:21.62#ibcon#about to write, iclass 5, count 0 2006.203.07:50:21.62#ibcon#wrote, iclass 5, count 0 2006.203.07:50:21.62#ibcon#about to read 3, iclass 5, count 0 2006.203.07:50:21.66#ibcon#read 3, iclass 5, count 0 2006.203.07:50:21.66#ibcon#about to read 4, iclass 5, count 0 2006.203.07:50:21.66#ibcon#read 4, iclass 5, count 0 2006.203.07:50:21.66#ibcon#about to read 5, iclass 5, count 0 2006.203.07:50:21.66#ibcon#read 5, iclass 5, count 0 2006.203.07:50:21.66#ibcon#about to read 6, iclass 5, count 0 2006.203.07:50:21.66#ibcon#read 6, iclass 5, count 0 2006.203.07:50:21.66#ibcon#end of sib2, iclass 5, count 0 2006.203.07:50:21.66#ibcon#*after write, iclass 5, count 0 2006.203.07:50:21.66#ibcon#*before return 0, iclass 5, count 0 2006.203.07:50:21.66#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.203.07:50:21.66#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.203.07:50:21.66#ibcon#about to clear, iclass 5 cls_cnt 0 2006.203.07:50:21.66#ibcon#cleared, iclass 5 cls_cnt 0 2006.203.07:50:21.66$vc4f8/va=8,6 2006.203.07:50:21.66#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.203.07:50:21.66#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.203.07:50:21.66#ibcon#ireg 11 cls_cnt 2 2006.203.07:50:21.66#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.203.07:50:21.73#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.203.07:50:21.73#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.203.07:50:21.73#ibcon#enter wrdev, iclass 7, count 2 2006.203.07:50:21.73#ibcon#first serial, iclass 7, count 2 2006.203.07:50:21.73#ibcon#enter sib2, iclass 7, count 2 2006.203.07:50:21.73#ibcon#flushed, iclass 7, count 2 2006.203.07:50:21.73#ibcon#about to write, iclass 7, count 2 2006.203.07:50:21.73#ibcon#wrote, iclass 7, count 2 2006.203.07:50:21.73#ibcon#about to read 3, iclass 7, count 2 2006.203.07:50:21.74#ibcon#read 3, iclass 7, count 2 2006.203.07:50:21.74#ibcon#about to read 4, iclass 7, count 2 2006.203.07:50:21.74#ibcon#read 4, iclass 7, count 2 2006.203.07:50:21.74#ibcon#about to read 5, iclass 7, count 2 2006.203.07:50:21.74#ibcon#read 5, iclass 7, count 2 2006.203.07:50:21.74#ibcon#about to read 6, iclass 7, count 2 2006.203.07:50:21.74#ibcon#read 6, iclass 7, count 2 2006.203.07:50:21.74#ibcon#end of sib2, iclass 7, count 2 2006.203.07:50:21.74#ibcon#*mode == 0, iclass 7, count 2 2006.203.07:50:21.74#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.203.07:50:21.74#ibcon#[25=AT08-06\r\n] 2006.203.07:50:21.74#ibcon#*before write, iclass 7, count 2 2006.203.07:50:21.74#ibcon#enter sib2, iclass 7, count 2 2006.203.07:50:21.74#ibcon#flushed, iclass 7, count 2 2006.203.07:50:21.74#ibcon#about to write, iclass 7, count 2 2006.203.07:50:21.74#ibcon#wrote, iclass 7, count 2 2006.203.07:50:21.74#ibcon#about to read 3, iclass 7, count 2 2006.203.07:50:21.77#ibcon#read 3, iclass 7, count 2 2006.203.07:50:21.77#ibcon#about to read 4, iclass 7, count 2 2006.203.07:50:21.77#ibcon#read 4, iclass 7, count 2 2006.203.07:50:21.77#ibcon#about to read 5, iclass 7, count 2 2006.203.07:50:21.77#ibcon#read 5, iclass 7, count 2 2006.203.07:50:21.77#ibcon#about to read 6, iclass 7, count 2 2006.203.07:50:21.77#ibcon#read 6, iclass 7, count 2 2006.203.07:50:21.77#ibcon#end of sib2, iclass 7, count 2 2006.203.07:50:21.77#ibcon#*after write, iclass 7, count 2 2006.203.07:50:21.77#ibcon#*before return 0, iclass 7, count 2 2006.203.07:50:21.77#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.203.07:50:21.77#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.203.07:50:21.77#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.203.07:50:21.77#ibcon#ireg 7 cls_cnt 0 2006.203.07:50:21.77#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.203.07:50:21.89#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.203.07:50:21.89#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.203.07:50:21.89#ibcon#enter wrdev, iclass 7, count 0 2006.203.07:50:21.89#ibcon#first serial, iclass 7, count 0 2006.203.07:50:21.89#ibcon#enter sib2, iclass 7, count 0 2006.203.07:50:21.89#ibcon#flushed, iclass 7, count 0 2006.203.07:50:21.89#ibcon#about to write, iclass 7, count 0 2006.203.07:50:21.89#ibcon#wrote, iclass 7, count 0 2006.203.07:50:21.89#ibcon#about to read 3, iclass 7, count 0 2006.203.07:50:21.91#ibcon#read 3, iclass 7, count 0 2006.203.07:50:21.91#ibcon#about to read 4, iclass 7, count 0 2006.203.07:50:21.91#ibcon#read 4, iclass 7, count 0 2006.203.07:50:21.91#ibcon#about to read 5, iclass 7, count 0 2006.203.07:50:21.91#ibcon#read 5, iclass 7, count 0 2006.203.07:50:21.91#ibcon#about to read 6, iclass 7, count 0 2006.203.07:50:21.91#ibcon#read 6, iclass 7, count 0 2006.203.07:50:21.91#ibcon#end of sib2, iclass 7, count 0 2006.203.07:50:21.91#ibcon#*mode == 0, iclass 7, count 0 2006.203.07:50:21.91#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.203.07:50:21.91#ibcon#[25=USB\r\n] 2006.203.07:50:21.91#ibcon#*before write, iclass 7, count 0 2006.203.07:50:21.91#ibcon#enter sib2, iclass 7, count 0 2006.203.07:50:21.91#ibcon#flushed, iclass 7, count 0 2006.203.07:50:21.91#ibcon#about to write, iclass 7, count 0 2006.203.07:50:21.91#ibcon#wrote, iclass 7, count 0 2006.203.07:50:21.91#ibcon#about to read 3, iclass 7, count 0 2006.203.07:50:21.94#ibcon#read 3, iclass 7, count 0 2006.203.07:50:21.94#ibcon#about to read 4, iclass 7, count 0 2006.203.07:50:21.94#ibcon#read 4, iclass 7, count 0 2006.203.07:50:21.94#ibcon#about to read 5, iclass 7, count 0 2006.203.07:50:21.94#ibcon#read 5, iclass 7, count 0 2006.203.07:50:21.94#ibcon#about to read 6, iclass 7, count 0 2006.203.07:50:21.94#ibcon#read 6, iclass 7, count 0 2006.203.07:50:21.94#ibcon#end of sib2, iclass 7, count 0 2006.203.07:50:21.94#ibcon#*after write, iclass 7, count 0 2006.203.07:50:21.94#ibcon#*before return 0, iclass 7, count 0 2006.203.07:50:21.94#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.203.07:50:21.94#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.203.07:50:21.94#ibcon#about to clear, iclass 7 cls_cnt 0 2006.203.07:50:21.94#ibcon#cleared, iclass 7 cls_cnt 0 2006.203.07:50:21.94$vc4f8/vblo=1,632.99 2006.203.07:50:21.94#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.203.07:50:21.94#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.203.07:50:21.94#ibcon#ireg 17 cls_cnt 0 2006.203.07:50:21.94#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.203.07:50:21.94#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.203.07:50:21.94#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.203.07:50:21.94#ibcon#enter wrdev, iclass 11, count 0 2006.203.07:50:21.94#ibcon#first serial, iclass 11, count 0 2006.203.07:50:21.94#ibcon#enter sib2, iclass 11, count 0 2006.203.07:50:21.94#ibcon#flushed, iclass 11, count 0 2006.203.07:50:21.94#ibcon#about to write, iclass 11, count 0 2006.203.07:50:21.94#ibcon#wrote, iclass 11, count 0 2006.203.07:50:21.94#ibcon#about to read 3, iclass 11, count 0 2006.203.07:50:21.96#ibcon#read 3, iclass 11, count 0 2006.203.07:50:21.96#ibcon#about to read 4, iclass 11, count 0 2006.203.07:50:21.96#ibcon#read 4, iclass 11, count 0 2006.203.07:50:21.96#ibcon#about to read 5, iclass 11, count 0 2006.203.07:50:21.96#ibcon#read 5, iclass 11, count 0 2006.203.07:50:21.96#ibcon#about to read 6, iclass 11, count 0 2006.203.07:50:21.96#ibcon#read 6, iclass 11, count 0 2006.203.07:50:21.96#ibcon#end of sib2, iclass 11, count 0 2006.203.07:50:21.96#ibcon#*mode == 0, iclass 11, count 0 2006.203.07:50:21.96#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.203.07:50:21.96#ibcon#[28=FRQ=01,632.99\r\n] 2006.203.07:50:21.96#ibcon#*before write, iclass 11, count 0 2006.203.07:50:21.96#ibcon#enter sib2, iclass 11, count 0 2006.203.07:50:21.96#ibcon#flushed, iclass 11, count 0 2006.203.07:50:21.96#ibcon#about to write, iclass 11, count 0 2006.203.07:50:21.96#ibcon#wrote, iclass 11, count 0 2006.203.07:50:21.96#ibcon#about to read 3, iclass 11, count 0 2006.203.07:50:22.00#ibcon#read 3, iclass 11, count 0 2006.203.07:50:22.00#ibcon#about to read 4, iclass 11, count 0 2006.203.07:50:22.00#ibcon#read 4, iclass 11, count 0 2006.203.07:50:22.00#ibcon#about to read 5, iclass 11, count 0 2006.203.07:50:22.00#ibcon#read 5, iclass 11, count 0 2006.203.07:50:22.00#ibcon#about to read 6, iclass 11, count 0 2006.203.07:50:22.00#ibcon#read 6, iclass 11, count 0 2006.203.07:50:22.00#ibcon#end of sib2, iclass 11, count 0 2006.203.07:50:22.00#ibcon#*after write, iclass 11, count 0 2006.203.07:50:22.00#ibcon#*before return 0, iclass 11, count 0 2006.203.07:50:22.00#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.203.07:50:22.00#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.203.07:50:22.00#ibcon#about to clear, iclass 11 cls_cnt 0 2006.203.07:50:22.00#ibcon#cleared, iclass 11 cls_cnt 0 2006.203.07:50:22.00$vc4f8/vb=1,4 2006.203.07:50:22.00#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.203.07:50:22.00#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.203.07:50:22.00#ibcon#ireg 11 cls_cnt 2 2006.203.07:50:22.00#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.203.07:50:22.00#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.203.07:50:22.00#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.203.07:50:22.00#ibcon#enter wrdev, iclass 13, count 2 2006.203.07:50:22.00#ibcon#first serial, iclass 13, count 2 2006.203.07:50:22.00#ibcon#enter sib2, iclass 13, count 2 2006.203.07:50:22.00#ibcon#flushed, iclass 13, count 2 2006.203.07:50:22.00#ibcon#about to write, iclass 13, count 2 2006.203.07:50:22.00#ibcon#wrote, iclass 13, count 2 2006.203.07:50:22.00#ibcon#about to read 3, iclass 13, count 2 2006.203.07:50:22.02#ibcon#read 3, iclass 13, count 2 2006.203.07:50:22.02#ibcon#about to read 4, iclass 13, count 2 2006.203.07:50:22.02#ibcon#read 4, iclass 13, count 2 2006.203.07:50:22.02#ibcon#about to read 5, iclass 13, count 2 2006.203.07:50:22.02#ibcon#read 5, iclass 13, count 2 2006.203.07:50:22.02#ibcon#about to read 6, iclass 13, count 2 2006.203.07:50:22.02#ibcon#read 6, iclass 13, count 2 2006.203.07:50:22.02#ibcon#end of sib2, iclass 13, count 2 2006.203.07:50:22.02#ibcon#*mode == 0, iclass 13, count 2 2006.203.07:50:22.02#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.203.07:50:22.02#ibcon#[27=AT01-04\r\n] 2006.203.07:50:22.02#ibcon#*before write, iclass 13, count 2 2006.203.07:50:22.02#ibcon#enter sib2, iclass 13, count 2 2006.203.07:50:22.02#ibcon#flushed, iclass 13, count 2 2006.203.07:50:22.02#ibcon#about to write, iclass 13, count 2 2006.203.07:50:22.02#ibcon#wrote, iclass 13, count 2 2006.203.07:50:22.02#ibcon#about to read 3, iclass 13, count 2 2006.203.07:50:22.05#ibcon#read 3, iclass 13, count 2 2006.203.07:50:22.05#ibcon#about to read 4, iclass 13, count 2 2006.203.07:50:22.05#ibcon#read 4, iclass 13, count 2 2006.203.07:50:22.05#ibcon#about to read 5, iclass 13, count 2 2006.203.07:50:22.05#ibcon#read 5, iclass 13, count 2 2006.203.07:50:22.05#ibcon#about to read 6, iclass 13, count 2 2006.203.07:50:22.05#ibcon#read 6, iclass 13, count 2 2006.203.07:50:22.05#ibcon#end of sib2, iclass 13, count 2 2006.203.07:50:22.05#ibcon#*after write, iclass 13, count 2 2006.203.07:50:22.05#ibcon#*before return 0, iclass 13, count 2 2006.203.07:50:22.05#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.203.07:50:22.05#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.203.07:50:22.05#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.203.07:50:22.05#ibcon#ireg 7 cls_cnt 0 2006.203.07:50:22.05#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.203.07:50:22.17#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.203.07:50:22.17#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.203.07:50:22.17#ibcon#enter wrdev, iclass 13, count 0 2006.203.07:50:22.17#ibcon#first serial, iclass 13, count 0 2006.203.07:50:22.17#ibcon#enter sib2, iclass 13, count 0 2006.203.07:50:22.17#ibcon#flushed, iclass 13, count 0 2006.203.07:50:22.17#ibcon#about to write, iclass 13, count 0 2006.203.07:50:22.17#ibcon#wrote, iclass 13, count 0 2006.203.07:50:22.17#ibcon#about to read 3, iclass 13, count 0 2006.203.07:50:22.19#ibcon#read 3, iclass 13, count 0 2006.203.07:50:22.19#ibcon#about to read 4, iclass 13, count 0 2006.203.07:50:22.19#ibcon#read 4, iclass 13, count 0 2006.203.07:50:22.19#ibcon#about to read 5, iclass 13, count 0 2006.203.07:50:22.19#ibcon#read 5, iclass 13, count 0 2006.203.07:50:22.19#ibcon#about to read 6, iclass 13, count 0 2006.203.07:50:22.19#ibcon#read 6, iclass 13, count 0 2006.203.07:50:22.19#ibcon#end of sib2, iclass 13, count 0 2006.203.07:50:22.19#ibcon#*mode == 0, iclass 13, count 0 2006.203.07:50:22.19#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.203.07:50:22.19#ibcon#[27=USB\r\n] 2006.203.07:50:22.19#ibcon#*before write, iclass 13, count 0 2006.203.07:50:22.19#ibcon#enter sib2, iclass 13, count 0 2006.203.07:50:22.19#ibcon#flushed, iclass 13, count 0 2006.203.07:50:22.19#ibcon#about to write, iclass 13, count 0 2006.203.07:50:22.19#ibcon#wrote, iclass 13, count 0 2006.203.07:50:22.19#ibcon#about to read 3, iclass 13, count 0 2006.203.07:50:22.22#ibcon#read 3, iclass 13, count 0 2006.203.07:50:22.22#ibcon#about to read 4, iclass 13, count 0 2006.203.07:50:22.22#ibcon#read 4, iclass 13, count 0 2006.203.07:50:22.22#ibcon#about to read 5, iclass 13, count 0 2006.203.07:50:22.22#ibcon#read 5, iclass 13, count 0 2006.203.07:50:22.22#ibcon#about to read 6, iclass 13, count 0 2006.203.07:50:22.22#ibcon#read 6, iclass 13, count 0 2006.203.07:50:22.22#ibcon#end of sib2, iclass 13, count 0 2006.203.07:50:22.22#ibcon#*after write, iclass 13, count 0 2006.203.07:50:22.22#ibcon#*before return 0, iclass 13, count 0 2006.203.07:50:22.22#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.203.07:50:22.22#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.203.07:50:22.22#ibcon#about to clear, iclass 13 cls_cnt 0 2006.203.07:50:22.22#ibcon#cleared, iclass 13 cls_cnt 0 2006.203.07:50:22.22$vc4f8/vblo=2,640.99 2006.203.07:50:22.22#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.203.07:50:22.22#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.203.07:50:22.22#ibcon#ireg 17 cls_cnt 0 2006.203.07:50:22.22#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.203.07:50:22.22#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.203.07:50:22.22#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.203.07:50:22.22#ibcon#enter wrdev, iclass 15, count 0 2006.203.07:50:22.22#ibcon#first serial, iclass 15, count 0 2006.203.07:50:22.22#ibcon#enter sib2, iclass 15, count 0 2006.203.07:50:22.22#ibcon#flushed, iclass 15, count 0 2006.203.07:50:22.22#ibcon#about to write, iclass 15, count 0 2006.203.07:50:22.22#ibcon#wrote, iclass 15, count 0 2006.203.07:50:22.22#ibcon#about to read 3, iclass 15, count 0 2006.203.07:50:22.24#ibcon#read 3, iclass 15, count 0 2006.203.07:50:22.24#ibcon#about to read 4, iclass 15, count 0 2006.203.07:50:22.24#ibcon#read 4, iclass 15, count 0 2006.203.07:50:22.24#ibcon#about to read 5, iclass 15, count 0 2006.203.07:50:22.24#ibcon#read 5, iclass 15, count 0 2006.203.07:50:22.24#ibcon#about to read 6, iclass 15, count 0 2006.203.07:50:22.24#ibcon#read 6, iclass 15, count 0 2006.203.07:50:22.24#ibcon#end of sib2, iclass 15, count 0 2006.203.07:50:22.24#ibcon#*mode == 0, iclass 15, count 0 2006.203.07:50:22.24#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.203.07:50:22.24#ibcon#[28=FRQ=02,640.99\r\n] 2006.203.07:50:22.24#ibcon#*before write, iclass 15, count 0 2006.203.07:50:22.24#ibcon#enter sib2, iclass 15, count 0 2006.203.07:50:22.24#ibcon#flushed, iclass 15, count 0 2006.203.07:50:22.24#ibcon#about to write, iclass 15, count 0 2006.203.07:50:22.24#ibcon#wrote, iclass 15, count 0 2006.203.07:50:22.24#ibcon#about to read 3, iclass 15, count 0 2006.203.07:50:22.28#ibcon#read 3, iclass 15, count 0 2006.203.07:50:22.28#ibcon#about to read 4, iclass 15, count 0 2006.203.07:50:22.28#ibcon#read 4, iclass 15, count 0 2006.203.07:50:22.28#ibcon#about to read 5, iclass 15, count 0 2006.203.07:50:22.28#ibcon#read 5, iclass 15, count 0 2006.203.07:50:22.28#ibcon#about to read 6, iclass 15, count 0 2006.203.07:50:22.28#ibcon#read 6, iclass 15, count 0 2006.203.07:50:22.28#ibcon#end of sib2, iclass 15, count 0 2006.203.07:50:22.28#ibcon#*after write, iclass 15, count 0 2006.203.07:50:22.28#ibcon#*before return 0, iclass 15, count 0 2006.203.07:50:22.28#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.203.07:50:22.28#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.203.07:50:22.28#ibcon#about to clear, iclass 15 cls_cnt 0 2006.203.07:50:22.28#ibcon#cleared, iclass 15 cls_cnt 0 2006.203.07:50:22.28$vc4f8/vb=2,4 2006.203.07:50:22.28#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.203.07:50:22.28#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.203.07:50:22.28#ibcon#ireg 11 cls_cnt 2 2006.203.07:50:22.28#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.203.07:50:22.34#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.203.07:50:22.34#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.203.07:50:22.34#ibcon#enter wrdev, iclass 17, count 2 2006.203.07:50:22.34#ibcon#first serial, iclass 17, count 2 2006.203.07:50:22.34#ibcon#enter sib2, iclass 17, count 2 2006.203.07:50:22.34#ibcon#flushed, iclass 17, count 2 2006.203.07:50:22.34#ibcon#about to write, iclass 17, count 2 2006.203.07:50:22.34#ibcon#wrote, iclass 17, count 2 2006.203.07:50:22.34#ibcon#about to read 3, iclass 17, count 2 2006.203.07:50:22.36#ibcon#read 3, iclass 17, count 2 2006.203.07:50:22.36#ibcon#about to read 4, iclass 17, count 2 2006.203.07:50:22.36#ibcon#read 4, iclass 17, count 2 2006.203.07:50:22.36#ibcon#about to read 5, iclass 17, count 2 2006.203.07:50:22.36#ibcon#read 5, iclass 17, count 2 2006.203.07:50:22.36#ibcon#about to read 6, iclass 17, count 2 2006.203.07:50:22.36#ibcon#read 6, iclass 17, count 2 2006.203.07:50:22.36#ibcon#end of sib2, iclass 17, count 2 2006.203.07:50:22.36#ibcon#*mode == 0, iclass 17, count 2 2006.203.07:50:22.36#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.203.07:50:22.36#ibcon#[27=AT02-04\r\n] 2006.203.07:50:22.36#ibcon#*before write, iclass 17, count 2 2006.203.07:50:22.36#ibcon#enter sib2, iclass 17, count 2 2006.203.07:50:22.36#ibcon#flushed, iclass 17, count 2 2006.203.07:50:22.36#ibcon#about to write, iclass 17, count 2 2006.203.07:50:22.36#ibcon#wrote, iclass 17, count 2 2006.203.07:50:22.36#ibcon#about to read 3, iclass 17, count 2 2006.203.07:50:22.39#ibcon#read 3, iclass 17, count 2 2006.203.07:50:22.39#ibcon#about to read 4, iclass 17, count 2 2006.203.07:50:22.39#ibcon#read 4, iclass 17, count 2 2006.203.07:50:22.39#ibcon#about to read 5, iclass 17, count 2 2006.203.07:50:22.39#ibcon#read 5, iclass 17, count 2 2006.203.07:50:22.39#ibcon#about to read 6, iclass 17, count 2 2006.203.07:50:22.39#ibcon#read 6, iclass 17, count 2 2006.203.07:50:22.39#ibcon#end of sib2, iclass 17, count 2 2006.203.07:50:22.39#ibcon#*after write, iclass 17, count 2 2006.203.07:50:22.39#ibcon#*before return 0, iclass 17, count 2 2006.203.07:50:22.39#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.203.07:50:22.39#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.203.07:50:22.39#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.203.07:50:22.39#ibcon#ireg 7 cls_cnt 0 2006.203.07:50:22.39#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.203.07:50:22.51#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.203.07:50:22.51#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.203.07:50:22.51#ibcon#enter wrdev, iclass 17, count 0 2006.203.07:50:22.51#ibcon#first serial, iclass 17, count 0 2006.203.07:50:22.51#ibcon#enter sib2, iclass 17, count 0 2006.203.07:50:22.51#ibcon#flushed, iclass 17, count 0 2006.203.07:50:22.51#ibcon#about to write, iclass 17, count 0 2006.203.07:50:22.51#ibcon#wrote, iclass 17, count 0 2006.203.07:50:22.51#ibcon#about to read 3, iclass 17, count 0 2006.203.07:50:22.53#ibcon#read 3, iclass 17, count 0 2006.203.07:50:22.53#ibcon#about to read 4, iclass 17, count 0 2006.203.07:50:22.53#ibcon#read 4, iclass 17, count 0 2006.203.07:50:22.53#ibcon#about to read 5, iclass 17, count 0 2006.203.07:50:22.53#ibcon#read 5, iclass 17, count 0 2006.203.07:50:22.53#ibcon#about to read 6, iclass 17, count 0 2006.203.07:50:22.53#ibcon#read 6, iclass 17, count 0 2006.203.07:50:22.53#ibcon#end of sib2, iclass 17, count 0 2006.203.07:50:22.53#ibcon#*mode == 0, iclass 17, count 0 2006.203.07:50:22.53#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.203.07:50:22.53#ibcon#[27=USB\r\n] 2006.203.07:50:22.53#ibcon#*before write, iclass 17, count 0 2006.203.07:50:22.53#ibcon#enter sib2, iclass 17, count 0 2006.203.07:50:22.53#ibcon#flushed, iclass 17, count 0 2006.203.07:50:22.53#ibcon#about to write, iclass 17, count 0 2006.203.07:50:22.53#ibcon#wrote, iclass 17, count 0 2006.203.07:50:22.53#ibcon#about to read 3, iclass 17, count 0 2006.203.07:50:22.56#ibcon#read 3, iclass 17, count 0 2006.203.07:50:22.56#ibcon#about to read 4, iclass 17, count 0 2006.203.07:50:22.56#ibcon#read 4, iclass 17, count 0 2006.203.07:50:22.56#ibcon#about to read 5, iclass 17, count 0 2006.203.07:50:22.56#ibcon#read 5, iclass 17, count 0 2006.203.07:50:22.56#ibcon#about to read 6, iclass 17, count 0 2006.203.07:50:22.56#ibcon#read 6, iclass 17, count 0 2006.203.07:50:22.56#ibcon#end of sib2, iclass 17, count 0 2006.203.07:50:22.56#ibcon#*after write, iclass 17, count 0 2006.203.07:50:22.56#ibcon#*before return 0, iclass 17, count 0 2006.203.07:50:22.56#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.203.07:50:22.56#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.203.07:50:22.56#ibcon#about to clear, iclass 17 cls_cnt 0 2006.203.07:50:22.56#ibcon#cleared, iclass 17 cls_cnt 0 2006.203.07:50:22.56$vc4f8/vblo=3,656.99 2006.203.07:50:22.56#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.203.07:50:22.56#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.203.07:50:22.56#ibcon#ireg 17 cls_cnt 0 2006.203.07:50:22.56#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.203.07:50:22.56#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.203.07:50:22.56#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.203.07:50:22.56#ibcon#enter wrdev, iclass 19, count 0 2006.203.07:50:22.56#ibcon#first serial, iclass 19, count 0 2006.203.07:50:22.56#ibcon#enter sib2, iclass 19, count 0 2006.203.07:50:22.56#ibcon#flushed, iclass 19, count 0 2006.203.07:50:22.56#ibcon#about to write, iclass 19, count 0 2006.203.07:50:22.56#ibcon#wrote, iclass 19, count 0 2006.203.07:50:22.56#ibcon#about to read 3, iclass 19, count 0 2006.203.07:50:22.58#ibcon#read 3, iclass 19, count 0 2006.203.07:50:22.58#ibcon#about to read 4, iclass 19, count 0 2006.203.07:50:22.58#ibcon#read 4, iclass 19, count 0 2006.203.07:50:22.58#ibcon#about to read 5, iclass 19, count 0 2006.203.07:50:22.58#ibcon#read 5, iclass 19, count 0 2006.203.07:50:22.58#ibcon#about to read 6, iclass 19, count 0 2006.203.07:50:22.58#ibcon#read 6, iclass 19, count 0 2006.203.07:50:22.58#ibcon#end of sib2, iclass 19, count 0 2006.203.07:50:22.58#ibcon#*mode == 0, iclass 19, count 0 2006.203.07:50:22.58#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.203.07:50:22.58#ibcon#[28=FRQ=03,656.99\r\n] 2006.203.07:50:22.58#ibcon#*before write, iclass 19, count 0 2006.203.07:50:22.58#ibcon#enter sib2, iclass 19, count 0 2006.203.07:50:22.58#ibcon#flushed, iclass 19, count 0 2006.203.07:50:22.58#ibcon#about to write, iclass 19, count 0 2006.203.07:50:22.58#ibcon#wrote, iclass 19, count 0 2006.203.07:50:22.58#ibcon#about to read 3, iclass 19, count 0 2006.203.07:50:22.62#ibcon#read 3, iclass 19, count 0 2006.203.07:50:22.62#ibcon#about to read 4, iclass 19, count 0 2006.203.07:50:22.62#ibcon#read 4, iclass 19, count 0 2006.203.07:50:22.62#ibcon#about to read 5, iclass 19, count 0 2006.203.07:50:22.62#ibcon#read 5, iclass 19, count 0 2006.203.07:50:22.62#ibcon#about to read 6, iclass 19, count 0 2006.203.07:50:22.62#ibcon#read 6, iclass 19, count 0 2006.203.07:50:22.62#ibcon#end of sib2, iclass 19, count 0 2006.203.07:50:22.62#ibcon#*after write, iclass 19, count 0 2006.203.07:50:22.62#ibcon#*before return 0, iclass 19, count 0 2006.203.07:50:22.62#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.203.07:50:22.62#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.203.07:50:22.62#ibcon#about to clear, iclass 19 cls_cnt 0 2006.203.07:50:22.62#ibcon#cleared, iclass 19 cls_cnt 0 2006.203.07:50:22.62$vc4f8/vb=3,4 2006.203.07:50:22.62#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.203.07:50:22.62#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.203.07:50:22.62#ibcon#ireg 11 cls_cnt 2 2006.203.07:50:22.62#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.203.07:50:22.68#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.203.07:50:22.68#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.203.07:50:22.68#ibcon#enter wrdev, iclass 21, count 2 2006.203.07:50:22.68#ibcon#first serial, iclass 21, count 2 2006.203.07:50:22.68#ibcon#enter sib2, iclass 21, count 2 2006.203.07:50:22.68#ibcon#flushed, iclass 21, count 2 2006.203.07:50:22.68#ibcon#about to write, iclass 21, count 2 2006.203.07:50:22.68#ibcon#wrote, iclass 21, count 2 2006.203.07:50:22.68#ibcon#about to read 3, iclass 21, count 2 2006.203.07:50:22.70#ibcon#read 3, iclass 21, count 2 2006.203.07:50:22.70#ibcon#about to read 4, iclass 21, count 2 2006.203.07:50:22.70#ibcon#read 4, iclass 21, count 2 2006.203.07:50:22.70#ibcon#about to read 5, iclass 21, count 2 2006.203.07:50:22.70#ibcon#read 5, iclass 21, count 2 2006.203.07:50:22.70#ibcon#about to read 6, iclass 21, count 2 2006.203.07:50:22.70#ibcon#read 6, iclass 21, count 2 2006.203.07:50:22.70#ibcon#end of sib2, iclass 21, count 2 2006.203.07:50:22.70#ibcon#*mode == 0, iclass 21, count 2 2006.203.07:50:22.70#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.203.07:50:22.70#ibcon#[27=AT03-04\r\n] 2006.203.07:50:22.70#ibcon#*before write, iclass 21, count 2 2006.203.07:50:22.70#ibcon#enter sib2, iclass 21, count 2 2006.203.07:50:22.70#ibcon#flushed, iclass 21, count 2 2006.203.07:50:22.70#ibcon#about to write, iclass 21, count 2 2006.203.07:50:22.70#ibcon#wrote, iclass 21, count 2 2006.203.07:50:22.70#ibcon#about to read 3, iclass 21, count 2 2006.203.07:50:22.73#ibcon#read 3, iclass 21, count 2 2006.203.07:50:22.73#ibcon#about to read 4, iclass 21, count 2 2006.203.07:50:22.73#ibcon#read 4, iclass 21, count 2 2006.203.07:50:22.73#ibcon#about to read 5, iclass 21, count 2 2006.203.07:50:22.73#ibcon#read 5, iclass 21, count 2 2006.203.07:50:22.73#ibcon#about to read 6, iclass 21, count 2 2006.203.07:50:22.73#ibcon#read 6, iclass 21, count 2 2006.203.07:50:22.73#ibcon#end of sib2, iclass 21, count 2 2006.203.07:50:22.73#ibcon#*after write, iclass 21, count 2 2006.203.07:50:22.73#ibcon#*before return 0, iclass 21, count 2 2006.203.07:50:22.73#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.203.07:50:22.73#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.203.07:50:22.73#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.203.07:50:22.73#ibcon#ireg 7 cls_cnt 0 2006.203.07:50:22.73#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.203.07:50:22.85#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.203.07:50:22.85#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.203.07:50:22.85#ibcon#enter wrdev, iclass 21, count 0 2006.203.07:50:22.85#ibcon#first serial, iclass 21, count 0 2006.203.07:50:22.85#ibcon#enter sib2, iclass 21, count 0 2006.203.07:50:22.85#ibcon#flushed, iclass 21, count 0 2006.203.07:50:22.85#ibcon#about to write, iclass 21, count 0 2006.203.07:50:22.85#ibcon#wrote, iclass 21, count 0 2006.203.07:50:22.85#ibcon#about to read 3, iclass 21, count 0 2006.203.07:50:22.87#ibcon#read 3, iclass 21, count 0 2006.203.07:50:22.87#ibcon#about to read 4, iclass 21, count 0 2006.203.07:50:22.87#ibcon#read 4, iclass 21, count 0 2006.203.07:50:22.87#ibcon#about to read 5, iclass 21, count 0 2006.203.07:50:22.87#ibcon#read 5, iclass 21, count 0 2006.203.07:50:22.87#ibcon#about to read 6, iclass 21, count 0 2006.203.07:50:22.87#ibcon#read 6, iclass 21, count 0 2006.203.07:50:22.87#ibcon#end of sib2, iclass 21, count 0 2006.203.07:50:22.87#ibcon#*mode == 0, iclass 21, count 0 2006.203.07:50:22.87#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.203.07:50:22.87#ibcon#[27=USB\r\n] 2006.203.07:50:22.87#ibcon#*before write, iclass 21, count 0 2006.203.07:50:22.87#ibcon#enter sib2, iclass 21, count 0 2006.203.07:50:22.87#ibcon#flushed, iclass 21, count 0 2006.203.07:50:22.87#ibcon#about to write, iclass 21, count 0 2006.203.07:50:22.87#ibcon#wrote, iclass 21, count 0 2006.203.07:50:22.87#ibcon#about to read 3, iclass 21, count 0 2006.203.07:50:22.90#ibcon#read 3, iclass 21, count 0 2006.203.07:50:22.90#ibcon#about to read 4, iclass 21, count 0 2006.203.07:50:22.90#ibcon#read 4, iclass 21, count 0 2006.203.07:50:22.90#ibcon#about to read 5, iclass 21, count 0 2006.203.07:50:22.90#ibcon#read 5, iclass 21, count 0 2006.203.07:50:22.90#ibcon#about to read 6, iclass 21, count 0 2006.203.07:50:22.90#ibcon#read 6, iclass 21, count 0 2006.203.07:50:22.90#ibcon#end of sib2, iclass 21, count 0 2006.203.07:50:22.90#ibcon#*after write, iclass 21, count 0 2006.203.07:50:22.90#ibcon#*before return 0, iclass 21, count 0 2006.203.07:50:22.90#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.203.07:50:22.90#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.203.07:50:22.90#ibcon#about to clear, iclass 21 cls_cnt 0 2006.203.07:50:22.90#ibcon#cleared, iclass 21 cls_cnt 0 2006.203.07:50:22.90$vc4f8/vblo=4,712.99 2006.203.07:50:22.90#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.203.07:50:22.90#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.203.07:50:22.90#ibcon#ireg 17 cls_cnt 0 2006.203.07:50:22.90#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.203.07:50:22.90#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.203.07:50:22.90#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.203.07:50:22.90#ibcon#enter wrdev, iclass 23, count 0 2006.203.07:50:22.90#ibcon#first serial, iclass 23, count 0 2006.203.07:50:22.90#ibcon#enter sib2, iclass 23, count 0 2006.203.07:50:22.90#ibcon#flushed, iclass 23, count 0 2006.203.07:50:22.90#ibcon#about to write, iclass 23, count 0 2006.203.07:50:22.90#ibcon#wrote, iclass 23, count 0 2006.203.07:50:22.90#ibcon#about to read 3, iclass 23, count 0 2006.203.07:50:22.92#ibcon#read 3, iclass 23, count 0 2006.203.07:50:22.92#ibcon#about to read 4, iclass 23, count 0 2006.203.07:50:22.92#ibcon#read 4, iclass 23, count 0 2006.203.07:50:22.92#ibcon#about to read 5, iclass 23, count 0 2006.203.07:50:22.92#ibcon#read 5, iclass 23, count 0 2006.203.07:50:22.92#ibcon#about to read 6, iclass 23, count 0 2006.203.07:50:22.92#ibcon#read 6, iclass 23, count 0 2006.203.07:50:22.92#ibcon#end of sib2, iclass 23, count 0 2006.203.07:50:22.92#ibcon#*mode == 0, iclass 23, count 0 2006.203.07:50:22.92#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.203.07:50:22.92#ibcon#[28=FRQ=04,712.99\r\n] 2006.203.07:50:22.92#ibcon#*before write, iclass 23, count 0 2006.203.07:50:22.92#ibcon#enter sib2, iclass 23, count 0 2006.203.07:50:22.92#ibcon#flushed, iclass 23, count 0 2006.203.07:50:22.92#ibcon#about to write, iclass 23, count 0 2006.203.07:50:22.92#ibcon#wrote, iclass 23, count 0 2006.203.07:50:22.92#ibcon#about to read 3, iclass 23, count 0 2006.203.07:50:22.96#ibcon#read 3, iclass 23, count 0 2006.203.07:50:22.96#ibcon#about to read 4, iclass 23, count 0 2006.203.07:50:22.96#ibcon#read 4, iclass 23, count 0 2006.203.07:50:22.96#ibcon#about to read 5, iclass 23, count 0 2006.203.07:50:22.96#ibcon#read 5, iclass 23, count 0 2006.203.07:50:22.96#ibcon#about to read 6, iclass 23, count 0 2006.203.07:50:22.96#ibcon#read 6, iclass 23, count 0 2006.203.07:50:22.96#ibcon#end of sib2, iclass 23, count 0 2006.203.07:50:22.96#ibcon#*after write, iclass 23, count 0 2006.203.07:50:22.96#ibcon#*before return 0, iclass 23, count 0 2006.203.07:50:22.96#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.203.07:50:22.96#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.203.07:50:22.96#ibcon#about to clear, iclass 23 cls_cnt 0 2006.203.07:50:22.96#ibcon#cleared, iclass 23 cls_cnt 0 2006.203.07:50:22.96$vc4f8/vb=4,4 2006.203.07:50:22.96#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.203.07:50:22.96#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.203.07:50:22.96#ibcon#ireg 11 cls_cnt 2 2006.203.07:50:22.96#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.203.07:50:23.02#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.203.07:50:23.02#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.203.07:50:23.02#ibcon#enter wrdev, iclass 25, count 2 2006.203.07:50:23.02#ibcon#first serial, iclass 25, count 2 2006.203.07:50:23.02#ibcon#enter sib2, iclass 25, count 2 2006.203.07:50:23.02#ibcon#flushed, iclass 25, count 2 2006.203.07:50:23.02#ibcon#about to write, iclass 25, count 2 2006.203.07:50:23.02#ibcon#wrote, iclass 25, count 2 2006.203.07:50:23.02#ibcon#about to read 3, iclass 25, count 2 2006.203.07:50:23.04#ibcon#read 3, iclass 25, count 2 2006.203.07:50:23.04#ibcon#about to read 4, iclass 25, count 2 2006.203.07:50:23.04#ibcon#read 4, iclass 25, count 2 2006.203.07:50:23.04#ibcon#about to read 5, iclass 25, count 2 2006.203.07:50:23.04#ibcon#read 5, iclass 25, count 2 2006.203.07:50:23.04#ibcon#about to read 6, iclass 25, count 2 2006.203.07:50:23.04#ibcon#read 6, iclass 25, count 2 2006.203.07:50:23.04#ibcon#end of sib2, iclass 25, count 2 2006.203.07:50:23.04#ibcon#*mode == 0, iclass 25, count 2 2006.203.07:50:23.04#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.203.07:50:23.04#ibcon#[27=AT04-04\r\n] 2006.203.07:50:23.04#ibcon#*before write, iclass 25, count 2 2006.203.07:50:23.04#ibcon#enter sib2, iclass 25, count 2 2006.203.07:50:23.04#ibcon#flushed, iclass 25, count 2 2006.203.07:50:23.04#ibcon#about to write, iclass 25, count 2 2006.203.07:50:23.04#ibcon#wrote, iclass 25, count 2 2006.203.07:50:23.04#ibcon#about to read 3, iclass 25, count 2 2006.203.07:50:23.07#ibcon#read 3, iclass 25, count 2 2006.203.07:50:23.07#ibcon#about to read 4, iclass 25, count 2 2006.203.07:50:23.07#ibcon#read 4, iclass 25, count 2 2006.203.07:50:23.07#ibcon#about to read 5, iclass 25, count 2 2006.203.07:50:23.07#ibcon#read 5, iclass 25, count 2 2006.203.07:50:23.07#ibcon#about to read 6, iclass 25, count 2 2006.203.07:50:23.07#ibcon#read 6, iclass 25, count 2 2006.203.07:50:23.07#ibcon#end of sib2, iclass 25, count 2 2006.203.07:50:23.07#ibcon#*after write, iclass 25, count 2 2006.203.07:50:23.07#ibcon#*before return 0, iclass 25, count 2 2006.203.07:50:23.07#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.203.07:50:23.07#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.203.07:50:23.07#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.203.07:50:23.07#ibcon#ireg 7 cls_cnt 0 2006.203.07:50:23.07#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.203.07:50:23.19#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.203.07:50:23.19#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.203.07:50:23.19#ibcon#enter wrdev, iclass 25, count 0 2006.203.07:50:23.19#ibcon#first serial, iclass 25, count 0 2006.203.07:50:23.19#ibcon#enter sib2, iclass 25, count 0 2006.203.07:50:23.19#ibcon#flushed, iclass 25, count 0 2006.203.07:50:23.19#ibcon#about to write, iclass 25, count 0 2006.203.07:50:23.19#ibcon#wrote, iclass 25, count 0 2006.203.07:50:23.19#ibcon#about to read 3, iclass 25, count 0 2006.203.07:50:23.23#ibcon#read 3, iclass 25, count 0 2006.203.07:50:23.23#ibcon#about to read 4, iclass 25, count 0 2006.203.07:50:23.23#ibcon#read 4, iclass 25, count 0 2006.203.07:50:23.23#ibcon#about to read 5, iclass 25, count 0 2006.203.07:50:23.23#ibcon#read 5, iclass 25, count 0 2006.203.07:50:23.23#ibcon#about to read 6, iclass 25, count 0 2006.203.07:50:23.23#ibcon#read 6, iclass 25, count 0 2006.203.07:50:23.23#ibcon#end of sib2, iclass 25, count 0 2006.203.07:50:23.23#ibcon#*mode == 0, iclass 25, count 0 2006.203.07:50:23.23#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.203.07:50:23.23#ibcon#[27=USB\r\n] 2006.203.07:50:23.23#ibcon#*before write, iclass 25, count 0 2006.203.07:50:23.23#ibcon#enter sib2, iclass 25, count 0 2006.203.07:50:23.23#ibcon#flushed, iclass 25, count 0 2006.203.07:50:23.23#ibcon#about to write, iclass 25, count 0 2006.203.07:50:23.23#ibcon#wrote, iclass 25, count 0 2006.203.07:50:23.23#ibcon#about to read 3, iclass 25, count 0 2006.203.07:50:23.26#ibcon#read 3, iclass 25, count 0 2006.203.07:50:23.26#ibcon#about to read 4, iclass 25, count 0 2006.203.07:50:23.26#ibcon#read 4, iclass 25, count 0 2006.203.07:50:23.26#ibcon#about to read 5, iclass 25, count 0 2006.203.07:50:23.26#ibcon#read 5, iclass 25, count 0 2006.203.07:50:23.26#ibcon#about to read 6, iclass 25, count 0 2006.203.07:50:23.26#ibcon#read 6, iclass 25, count 0 2006.203.07:50:23.26#ibcon#end of sib2, iclass 25, count 0 2006.203.07:50:23.26#ibcon#*after write, iclass 25, count 0 2006.203.07:50:23.26#ibcon#*before return 0, iclass 25, count 0 2006.203.07:50:23.26#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.203.07:50:23.26#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.203.07:50:23.26#ibcon#about to clear, iclass 25 cls_cnt 0 2006.203.07:50:23.26#ibcon#cleared, iclass 25 cls_cnt 0 2006.203.07:50:23.26$vc4f8/vblo=5,744.99 2006.203.07:50:23.26#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.203.07:50:23.26#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.203.07:50:23.26#ibcon#ireg 17 cls_cnt 0 2006.203.07:50:23.26#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:50:23.26#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:50:23.26#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:50:23.26#ibcon#enter wrdev, iclass 27, count 0 2006.203.07:50:23.26#ibcon#first serial, iclass 27, count 0 2006.203.07:50:23.26#ibcon#enter sib2, iclass 27, count 0 2006.203.07:50:23.26#ibcon#flushed, iclass 27, count 0 2006.203.07:50:23.26#ibcon#about to write, iclass 27, count 0 2006.203.07:50:23.26#ibcon#wrote, iclass 27, count 0 2006.203.07:50:23.26#ibcon#about to read 3, iclass 27, count 0 2006.203.07:50:23.28#ibcon#read 3, iclass 27, count 0 2006.203.07:50:23.28#ibcon#about to read 4, iclass 27, count 0 2006.203.07:50:23.28#ibcon#read 4, iclass 27, count 0 2006.203.07:50:23.28#ibcon#about to read 5, iclass 27, count 0 2006.203.07:50:23.28#ibcon#read 5, iclass 27, count 0 2006.203.07:50:23.28#ibcon#about to read 6, iclass 27, count 0 2006.203.07:50:23.28#ibcon#read 6, iclass 27, count 0 2006.203.07:50:23.28#ibcon#end of sib2, iclass 27, count 0 2006.203.07:50:23.28#ibcon#*mode == 0, iclass 27, count 0 2006.203.07:50:23.28#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.203.07:50:23.28#ibcon#[28=FRQ=05,744.99\r\n] 2006.203.07:50:23.28#ibcon#*before write, iclass 27, count 0 2006.203.07:50:23.28#ibcon#enter sib2, iclass 27, count 0 2006.203.07:50:23.28#ibcon#flushed, iclass 27, count 0 2006.203.07:50:23.28#ibcon#about to write, iclass 27, count 0 2006.203.07:50:23.28#ibcon#wrote, iclass 27, count 0 2006.203.07:50:23.28#ibcon#about to read 3, iclass 27, count 0 2006.203.07:50:23.32#ibcon#read 3, iclass 27, count 0 2006.203.07:50:23.32#ibcon#about to read 4, iclass 27, count 0 2006.203.07:50:23.32#ibcon#read 4, iclass 27, count 0 2006.203.07:50:23.32#ibcon#about to read 5, iclass 27, count 0 2006.203.07:50:23.32#ibcon#read 5, iclass 27, count 0 2006.203.07:50:23.32#ibcon#about to read 6, iclass 27, count 0 2006.203.07:50:23.32#ibcon#read 6, iclass 27, count 0 2006.203.07:50:23.32#ibcon#end of sib2, iclass 27, count 0 2006.203.07:50:23.32#ibcon#*after write, iclass 27, count 0 2006.203.07:50:23.32#ibcon#*before return 0, iclass 27, count 0 2006.203.07:50:23.32#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:50:23.32#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:50:23.32#ibcon#about to clear, iclass 27 cls_cnt 0 2006.203.07:50:23.32#ibcon#cleared, iclass 27 cls_cnt 0 2006.203.07:50:23.32$vc4f8/vb=5,3 2006.203.07:50:23.32#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.203.07:50:23.32#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.203.07:50:23.32#ibcon#ireg 11 cls_cnt 2 2006.203.07:50:23.32#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.203.07:50:23.38#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.203.07:50:23.38#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.203.07:50:23.38#ibcon#enter wrdev, iclass 29, count 2 2006.203.07:50:23.38#ibcon#first serial, iclass 29, count 2 2006.203.07:50:23.38#ibcon#enter sib2, iclass 29, count 2 2006.203.07:50:23.38#ibcon#flushed, iclass 29, count 2 2006.203.07:50:23.38#ibcon#about to write, iclass 29, count 2 2006.203.07:50:23.38#ibcon#wrote, iclass 29, count 2 2006.203.07:50:23.38#ibcon#about to read 3, iclass 29, count 2 2006.203.07:50:23.40#ibcon#read 3, iclass 29, count 2 2006.203.07:50:23.40#ibcon#about to read 4, iclass 29, count 2 2006.203.07:50:23.40#ibcon#read 4, iclass 29, count 2 2006.203.07:50:23.40#ibcon#about to read 5, iclass 29, count 2 2006.203.07:50:23.40#ibcon#read 5, iclass 29, count 2 2006.203.07:50:23.40#ibcon#about to read 6, iclass 29, count 2 2006.203.07:50:23.40#ibcon#read 6, iclass 29, count 2 2006.203.07:50:23.40#ibcon#end of sib2, iclass 29, count 2 2006.203.07:50:23.40#ibcon#*mode == 0, iclass 29, count 2 2006.203.07:50:23.40#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.203.07:50:23.40#ibcon#[27=AT05-03\r\n] 2006.203.07:50:23.40#ibcon#*before write, iclass 29, count 2 2006.203.07:50:23.40#ibcon#enter sib2, iclass 29, count 2 2006.203.07:50:23.40#ibcon#flushed, iclass 29, count 2 2006.203.07:50:23.40#ibcon#about to write, iclass 29, count 2 2006.203.07:50:23.40#ibcon#wrote, iclass 29, count 2 2006.203.07:50:23.40#ibcon#about to read 3, iclass 29, count 2 2006.203.07:50:23.43#ibcon#read 3, iclass 29, count 2 2006.203.07:50:23.43#ibcon#about to read 4, iclass 29, count 2 2006.203.07:50:23.43#ibcon#read 4, iclass 29, count 2 2006.203.07:50:23.43#ibcon#about to read 5, iclass 29, count 2 2006.203.07:50:23.43#ibcon#read 5, iclass 29, count 2 2006.203.07:50:23.43#ibcon#about to read 6, iclass 29, count 2 2006.203.07:50:23.43#ibcon#read 6, iclass 29, count 2 2006.203.07:50:23.43#ibcon#end of sib2, iclass 29, count 2 2006.203.07:50:23.43#ibcon#*after write, iclass 29, count 2 2006.203.07:50:23.43#ibcon#*before return 0, iclass 29, count 2 2006.203.07:50:23.43#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.203.07:50:23.43#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.203.07:50:23.43#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.203.07:50:23.43#ibcon#ireg 7 cls_cnt 0 2006.203.07:50:23.43#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.203.07:50:23.55#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.203.07:50:23.55#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.203.07:50:23.55#ibcon#enter wrdev, iclass 29, count 0 2006.203.07:50:23.55#ibcon#first serial, iclass 29, count 0 2006.203.07:50:23.55#ibcon#enter sib2, iclass 29, count 0 2006.203.07:50:23.55#ibcon#flushed, iclass 29, count 0 2006.203.07:50:23.55#ibcon#about to write, iclass 29, count 0 2006.203.07:50:23.55#ibcon#wrote, iclass 29, count 0 2006.203.07:50:23.55#ibcon#about to read 3, iclass 29, count 0 2006.203.07:50:23.57#ibcon#read 3, iclass 29, count 0 2006.203.07:50:23.57#ibcon#about to read 4, iclass 29, count 0 2006.203.07:50:23.57#ibcon#read 4, iclass 29, count 0 2006.203.07:50:23.57#ibcon#about to read 5, iclass 29, count 0 2006.203.07:50:23.57#ibcon#read 5, iclass 29, count 0 2006.203.07:50:23.57#ibcon#about to read 6, iclass 29, count 0 2006.203.07:50:23.57#ibcon#read 6, iclass 29, count 0 2006.203.07:50:23.57#ibcon#end of sib2, iclass 29, count 0 2006.203.07:50:23.57#ibcon#*mode == 0, iclass 29, count 0 2006.203.07:50:23.57#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.203.07:50:23.57#ibcon#[27=USB\r\n] 2006.203.07:50:23.57#ibcon#*before write, iclass 29, count 0 2006.203.07:50:23.57#ibcon#enter sib2, iclass 29, count 0 2006.203.07:50:23.57#ibcon#flushed, iclass 29, count 0 2006.203.07:50:23.57#ibcon#about to write, iclass 29, count 0 2006.203.07:50:23.57#ibcon#wrote, iclass 29, count 0 2006.203.07:50:23.57#ibcon#about to read 3, iclass 29, count 0 2006.203.07:50:23.60#ibcon#read 3, iclass 29, count 0 2006.203.07:50:23.60#ibcon#about to read 4, iclass 29, count 0 2006.203.07:50:23.60#ibcon#read 4, iclass 29, count 0 2006.203.07:50:23.60#ibcon#about to read 5, iclass 29, count 0 2006.203.07:50:23.60#ibcon#read 5, iclass 29, count 0 2006.203.07:50:23.60#ibcon#about to read 6, iclass 29, count 0 2006.203.07:50:23.60#ibcon#read 6, iclass 29, count 0 2006.203.07:50:23.60#ibcon#end of sib2, iclass 29, count 0 2006.203.07:50:23.60#ibcon#*after write, iclass 29, count 0 2006.203.07:50:23.60#ibcon#*before return 0, iclass 29, count 0 2006.203.07:50:23.60#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.203.07:50:23.60#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.203.07:50:23.60#ibcon#about to clear, iclass 29 cls_cnt 0 2006.203.07:50:23.60#ibcon#cleared, iclass 29 cls_cnt 0 2006.203.07:50:23.60$vc4f8/vblo=6,752.99 2006.203.07:50:23.60#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.203.07:50:23.60#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.203.07:50:23.60#ibcon#ireg 17 cls_cnt 0 2006.203.07:50:23.60#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.203.07:50:23.60#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.203.07:50:23.60#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.203.07:50:23.60#ibcon#enter wrdev, iclass 31, count 0 2006.203.07:50:23.60#ibcon#first serial, iclass 31, count 0 2006.203.07:50:23.60#ibcon#enter sib2, iclass 31, count 0 2006.203.07:50:23.60#ibcon#flushed, iclass 31, count 0 2006.203.07:50:23.60#ibcon#about to write, iclass 31, count 0 2006.203.07:50:23.60#ibcon#wrote, iclass 31, count 0 2006.203.07:50:23.60#ibcon#about to read 3, iclass 31, count 0 2006.203.07:50:23.62#ibcon#read 3, iclass 31, count 0 2006.203.07:50:23.62#ibcon#about to read 4, iclass 31, count 0 2006.203.07:50:23.62#ibcon#read 4, iclass 31, count 0 2006.203.07:50:23.62#ibcon#about to read 5, iclass 31, count 0 2006.203.07:50:23.62#ibcon#read 5, iclass 31, count 0 2006.203.07:50:23.62#ibcon#about to read 6, iclass 31, count 0 2006.203.07:50:23.62#ibcon#read 6, iclass 31, count 0 2006.203.07:50:23.62#ibcon#end of sib2, iclass 31, count 0 2006.203.07:50:23.62#ibcon#*mode == 0, iclass 31, count 0 2006.203.07:50:23.62#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.203.07:50:23.62#ibcon#[28=FRQ=06,752.99\r\n] 2006.203.07:50:23.62#ibcon#*before write, iclass 31, count 0 2006.203.07:50:23.62#ibcon#enter sib2, iclass 31, count 0 2006.203.07:50:23.62#ibcon#flushed, iclass 31, count 0 2006.203.07:50:23.62#ibcon#about to write, iclass 31, count 0 2006.203.07:50:23.62#ibcon#wrote, iclass 31, count 0 2006.203.07:50:23.62#ibcon#about to read 3, iclass 31, count 0 2006.203.07:50:23.66#ibcon#read 3, iclass 31, count 0 2006.203.07:50:23.66#ibcon#about to read 4, iclass 31, count 0 2006.203.07:50:23.66#ibcon#read 4, iclass 31, count 0 2006.203.07:50:23.66#ibcon#about to read 5, iclass 31, count 0 2006.203.07:50:23.66#ibcon#read 5, iclass 31, count 0 2006.203.07:50:23.66#ibcon#about to read 6, iclass 31, count 0 2006.203.07:50:23.66#ibcon#read 6, iclass 31, count 0 2006.203.07:50:23.66#ibcon#end of sib2, iclass 31, count 0 2006.203.07:50:23.66#ibcon#*after write, iclass 31, count 0 2006.203.07:50:23.66#ibcon#*before return 0, iclass 31, count 0 2006.203.07:50:23.66#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.203.07:50:23.66#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.203.07:50:23.66#ibcon#about to clear, iclass 31 cls_cnt 0 2006.203.07:50:23.66#ibcon#cleared, iclass 31 cls_cnt 0 2006.203.07:50:23.66$vc4f8/vb=6,4 2006.203.07:50:23.66#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.203.07:50:23.66#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.203.07:50:23.66#ibcon#ireg 11 cls_cnt 2 2006.203.07:50:23.66#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.203.07:50:23.72#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.203.07:50:23.72#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.203.07:50:23.72#ibcon#enter wrdev, iclass 33, count 2 2006.203.07:50:23.72#ibcon#first serial, iclass 33, count 2 2006.203.07:50:23.72#ibcon#enter sib2, iclass 33, count 2 2006.203.07:50:23.72#ibcon#flushed, iclass 33, count 2 2006.203.07:50:23.72#ibcon#about to write, iclass 33, count 2 2006.203.07:50:23.72#ibcon#wrote, iclass 33, count 2 2006.203.07:50:23.72#ibcon#about to read 3, iclass 33, count 2 2006.203.07:50:23.74#ibcon#read 3, iclass 33, count 2 2006.203.07:50:23.74#ibcon#about to read 4, iclass 33, count 2 2006.203.07:50:23.74#ibcon#read 4, iclass 33, count 2 2006.203.07:50:23.74#ibcon#about to read 5, iclass 33, count 2 2006.203.07:50:23.74#ibcon#read 5, iclass 33, count 2 2006.203.07:50:23.74#ibcon#about to read 6, iclass 33, count 2 2006.203.07:50:23.74#ibcon#read 6, iclass 33, count 2 2006.203.07:50:23.74#ibcon#end of sib2, iclass 33, count 2 2006.203.07:50:23.74#ibcon#*mode == 0, iclass 33, count 2 2006.203.07:50:23.74#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.203.07:50:23.74#ibcon#[27=AT06-04\r\n] 2006.203.07:50:23.74#ibcon#*before write, iclass 33, count 2 2006.203.07:50:23.74#ibcon#enter sib2, iclass 33, count 2 2006.203.07:50:23.74#ibcon#flushed, iclass 33, count 2 2006.203.07:50:23.74#ibcon#about to write, iclass 33, count 2 2006.203.07:50:23.74#ibcon#wrote, iclass 33, count 2 2006.203.07:50:23.74#ibcon#about to read 3, iclass 33, count 2 2006.203.07:50:23.77#ibcon#read 3, iclass 33, count 2 2006.203.07:50:23.77#ibcon#about to read 4, iclass 33, count 2 2006.203.07:50:23.77#ibcon#read 4, iclass 33, count 2 2006.203.07:50:23.77#ibcon#about to read 5, iclass 33, count 2 2006.203.07:50:23.77#ibcon#read 5, iclass 33, count 2 2006.203.07:50:23.77#ibcon#about to read 6, iclass 33, count 2 2006.203.07:50:23.77#ibcon#read 6, iclass 33, count 2 2006.203.07:50:23.77#ibcon#end of sib2, iclass 33, count 2 2006.203.07:50:23.77#ibcon#*after write, iclass 33, count 2 2006.203.07:50:23.77#ibcon#*before return 0, iclass 33, count 2 2006.203.07:50:23.77#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.203.07:50:23.77#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.203.07:50:23.77#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.203.07:50:23.77#ibcon#ireg 7 cls_cnt 0 2006.203.07:50:23.77#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.203.07:50:23.89#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.203.07:50:23.89#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.203.07:50:23.89#ibcon#enter wrdev, iclass 33, count 0 2006.203.07:50:23.89#ibcon#first serial, iclass 33, count 0 2006.203.07:50:23.89#ibcon#enter sib2, iclass 33, count 0 2006.203.07:50:23.89#ibcon#flushed, iclass 33, count 0 2006.203.07:50:23.89#ibcon#about to write, iclass 33, count 0 2006.203.07:50:23.89#ibcon#wrote, iclass 33, count 0 2006.203.07:50:23.89#ibcon#about to read 3, iclass 33, count 0 2006.203.07:50:23.91#ibcon#read 3, iclass 33, count 0 2006.203.07:50:23.91#ibcon#about to read 4, iclass 33, count 0 2006.203.07:50:23.91#ibcon#read 4, iclass 33, count 0 2006.203.07:50:23.91#ibcon#about to read 5, iclass 33, count 0 2006.203.07:50:23.91#ibcon#read 5, iclass 33, count 0 2006.203.07:50:23.91#ibcon#about to read 6, iclass 33, count 0 2006.203.07:50:23.91#ibcon#read 6, iclass 33, count 0 2006.203.07:50:23.91#ibcon#end of sib2, iclass 33, count 0 2006.203.07:50:23.91#ibcon#*mode == 0, iclass 33, count 0 2006.203.07:50:23.91#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.203.07:50:23.91#ibcon#[27=USB\r\n] 2006.203.07:50:23.91#ibcon#*before write, iclass 33, count 0 2006.203.07:50:23.91#ibcon#enter sib2, iclass 33, count 0 2006.203.07:50:23.91#ibcon#flushed, iclass 33, count 0 2006.203.07:50:23.91#ibcon#about to write, iclass 33, count 0 2006.203.07:50:23.91#ibcon#wrote, iclass 33, count 0 2006.203.07:50:23.91#ibcon#about to read 3, iclass 33, count 0 2006.203.07:50:23.94#ibcon#read 3, iclass 33, count 0 2006.203.07:50:23.94#ibcon#about to read 4, iclass 33, count 0 2006.203.07:50:23.94#ibcon#read 4, iclass 33, count 0 2006.203.07:50:23.94#ibcon#about to read 5, iclass 33, count 0 2006.203.07:50:23.94#ibcon#read 5, iclass 33, count 0 2006.203.07:50:23.94#ibcon#about to read 6, iclass 33, count 0 2006.203.07:50:23.94#ibcon#read 6, iclass 33, count 0 2006.203.07:50:23.94#ibcon#end of sib2, iclass 33, count 0 2006.203.07:50:23.94#ibcon#*after write, iclass 33, count 0 2006.203.07:50:23.94#ibcon#*before return 0, iclass 33, count 0 2006.203.07:50:23.94#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.203.07:50:23.94#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.203.07:50:23.94#ibcon#about to clear, iclass 33 cls_cnt 0 2006.203.07:50:23.94#ibcon#cleared, iclass 33 cls_cnt 0 2006.203.07:50:23.94$vc4f8/vabw=wide 2006.203.07:50:23.94#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.203.07:50:23.94#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.203.07:50:23.94#ibcon#ireg 8 cls_cnt 0 2006.203.07:50:23.94#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.203.07:50:23.94#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.203.07:50:23.94#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.203.07:50:23.94#ibcon#enter wrdev, iclass 35, count 0 2006.203.07:50:23.94#ibcon#first serial, iclass 35, count 0 2006.203.07:50:23.94#ibcon#enter sib2, iclass 35, count 0 2006.203.07:50:23.94#ibcon#flushed, iclass 35, count 0 2006.203.07:50:23.94#ibcon#about to write, iclass 35, count 0 2006.203.07:50:23.94#ibcon#wrote, iclass 35, count 0 2006.203.07:50:23.94#ibcon#about to read 3, iclass 35, count 0 2006.203.07:50:23.96#ibcon#read 3, iclass 35, count 0 2006.203.07:50:23.96#ibcon#about to read 4, iclass 35, count 0 2006.203.07:50:23.96#ibcon#read 4, iclass 35, count 0 2006.203.07:50:23.96#ibcon#about to read 5, iclass 35, count 0 2006.203.07:50:23.96#ibcon#read 5, iclass 35, count 0 2006.203.07:50:23.96#ibcon#about to read 6, iclass 35, count 0 2006.203.07:50:23.96#ibcon#read 6, iclass 35, count 0 2006.203.07:50:23.96#ibcon#end of sib2, iclass 35, count 0 2006.203.07:50:23.96#ibcon#*mode == 0, iclass 35, count 0 2006.203.07:50:23.96#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.203.07:50:23.96#ibcon#[25=BW32\r\n] 2006.203.07:50:23.96#ibcon#*before write, iclass 35, count 0 2006.203.07:50:23.96#ibcon#enter sib2, iclass 35, count 0 2006.203.07:50:23.96#ibcon#flushed, iclass 35, count 0 2006.203.07:50:23.96#ibcon#about to write, iclass 35, count 0 2006.203.07:50:23.96#ibcon#wrote, iclass 35, count 0 2006.203.07:50:23.96#ibcon#about to read 3, iclass 35, count 0 2006.203.07:50:23.99#ibcon#read 3, iclass 35, count 0 2006.203.07:50:23.99#ibcon#about to read 4, iclass 35, count 0 2006.203.07:50:23.99#ibcon#read 4, iclass 35, count 0 2006.203.07:50:23.99#ibcon#about to read 5, iclass 35, count 0 2006.203.07:50:23.99#ibcon#read 5, iclass 35, count 0 2006.203.07:50:23.99#ibcon#about to read 6, iclass 35, count 0 2006.203.07:50:23.99#ibcon#read 6, iclass 35, count 0 2006.203.07:50:23.99#ibcon#end of sib2, iclass 35, count 0 2006.203.07:50:23.99#ibcon#*after write, iclass 35, count 0 2006.203.07:50:23.99#ibcon#*before return 0, iclass 35, count 0 2006.203.07:50:23.99#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.203.07:50:23.99#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.203.07:50:23.99#ibcon#about to clear, iclass 35 cls_cnt 0 2006.203.07:50:23.99#ibcon#cleared, iclass 35 cls_cnt 0 2006.203.07:50:23.99$vc4f8/vbbw=wide 2006.203.07:50:23.99#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.203.07:50:23.99#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.203.07:50:23.99#ibcon#ireg 8 cls_cnt 0 2006.203.07:50:23.99#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.203.07:50:24.07#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.203.07:50:24.07#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.203.07:50:24.07#ibcon#enter wrdev, iclass 37, count 0 2006.203.07:50:24.07#ibcon#first serial, iclass 37, count 0 2006.203.07:50:24.07#ibcon#enter sib2, iclass 37, count 0 2006.203.07:50:24.07#ibcon#flushed, iclass 37, count 0 2006.203.07:50:24.07#ibcon#about to write, iclass 37, count 0 2006.203.07:50:24.07#ibcon#wrote, iclass 37, count 0 2006.203.07:50:24.07#ibcon#about to read 3, iclass 37, count 0 2006.203.07:50:24.08#ibcon#read 3, iclass 37, count 0 2006.203.07:50:24.08#ibcon#about to read 4, iclass 37, count 0 2006.203.07:50:24.08#ibcon#read 4, iclass 37, count 0 2006.203.07:50:24.08#ibcon#about to read 5, iclass 37, count 0 2006.203.07:50:24.08#ibcon#read 5, iclass 37, count 0 2006.203.07:50:24.08#ibcon#about to read 6, iclass 37, count 0 2006.203.07:50:24.08#ibcon#read 6, iclass 37, count 0 2006.203.07:50:24.08#ibcon#end of sib2, iclass 37, count 0 2006.203.07:50:24.08#ibcon#*mode == 0, iclass 37, count 0 2006.203.07:50:24.08#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.203.07:50:24.08#ibcon#[27=BW32\r\n] 2006.203.07:50:24.08#ibcon#*before write, iclass 37, count 0 2006.203.07:50:24.08#ibcon#enter sib2, iclass 37, count 0 2006.203.07:50:24.08#ibcon#flushed, iclass 37, count 0 2006.203.07:50:24.08#ibcon#about to write, iclass 37, count 0 2006.203.07:50:24.08#ibcon#wrote, iclass 37, count 0 2006.203.07:50:24.08#ibcon#about to read 3, iclass 37, count 0 2006.203.07:50:24.11#ibcon#read 3, iclass 37, count 0 2006.203.07:50:24.11#ibcon#about to read 4, iclass 37, count 0 2006.203.07:50:24.11#ibcon#read 4, iclass 37, count 0 2006.203.07:50:24.11#ibcon#about to read 5, iclass 37, count 0 2006.203.07:50:24.11#ibcon#read 5, iclass 37, count 0 2006.203.07:50:24.11#ibcon#about to read 6, iclass 37, count 0 2006.203.07:50:24.11#ibcon#read 6, iclass 37, count 0 2006.203.07:50:24.11#ibcon#end of sib2, iclass 37, count 0 2006.203.07:50:24.11#ibcon#*after write, iclass 37, count 0 2006.203.07:50:24.11#ibcon#*before return 0, iclass 37, count 0 2006.203.07:50:24.11#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.203.07:50:24.11#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.203.07:50:24.11#ibcon#about to clear, iclass 37 cls_cnt 0 2006.203.07:50:24.11#ibcon#cleared, iclass 37 cls_cnt 0 2006.203.07:50:24.11$4f8m12a/ifd4f 2006.203.07:50:24.11$ifd4f/lo= 2006.203.07:50:24.11$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.203.07:50:24.11$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.203.07:50:24.11$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.203.07:50:24.11$ifd4f/patch= 2006.203.07:50:24.11$ifd4f/patch=lo1,a1,a2,a3,a4 2006.203.07:50:24.11$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.203.07:50:24.11$ifd4f/patch=lo3,a5,a6,a7,a8 2006.203.07:50:24.11$4f8m12a/"form=m,16.000,1:2 2006.203.07:50:24.11$4f8m12a/"tpicd 2006.203.07:50:24.11$4f8m12a/echo=off 2006.203.07:50:24.11$4f8m12a/xlog=off 2006.203.07:50:24.11:!2006.203.07:50:50 2006.203.07:50:29.14#trakl#Source acquired 2006.203.07:50:29.14#flagr#flagr/antenna,acquired 2006.203.07:50:50.00:preob 2006.203.07:50:51.14/onsource/TRACKING 2006.203.07:50:51.14:!2006.203.07:51:00 2006.203.07:51:00.00:data_valid=on 2006.203.07:51:00.00:midob 2006.203.07:51:00.14/onsource/TRACKING 2006.203.07:51:00.14/wx/23.83,1001.1,97 2006.203.07:51:00.26/cable/+6.4601E-03 2006.203.07:51:01.35/va/01,08,usb,yes,29,31 2006.203.07:51:01.35/va/02,07,usb,yes,29,30 2006.203.07:51:01.35/va/03,08,usb,yes,22,22 2006.203.07:51:01.35/va/04,07,usb,yes,30,32 2006.203.07:51:01.35/va/05,07,usb,yes,32,34 2006.203.07:51:01.35/va/06,06,usb,yes,32,31 2006.203.07:51:01.35/va/07,07,usb,yes,28,28 2006.203.07:51:01.35/va/08,06,usb,yes,34,34 2006.203.07:51:01.58/valo/01,532.99,yes,locked 2006.203.07:51:01.58/valo/02,572.99,yes,locked 2006.203.07:51:01.58/valo/03,672.99,yes,locked 2006.203.07:51:01.58/valo/04,832.99,yes,locked 2006.203.07:51:01.58/valo/05,652.99,yes,locked 2006.203.07:51:01.58/valo/06,772.99,yes,locked 2006.203.07:51:01.58/valo/07,832.99,yes,locked 2006.203.07:51:01.58/valo/08,852.99,yes,locked 2006.203.07:51:02.67/vb/01,04,usb,yes,29,27 2006.203.07:51:02.67/vb/02,04,usb,yes,30,32 2006.203.07:51:02.67/vb/03,04,usb,yes,27,30 2006.203.07:51:02.67/vb/04,04,usb,yes,28,28 2006.203.07:51:02.67/vb/05,03,usb,yes,33,37 2006.203.07:51:02.67/vb/06,04,usb,yes,27,30 2006.203.07:51:02.67/vb/07,04,usb,yes,29,29 2006.203.07:51:02.67/vb/08,04,usb,yes,27,30 2006.203.07:51:02.91/vblo/01,632.99,yes,locked 2006.203.07:51:02.91/vblo/02,640.99,yes,locked 2006.203.07:51:02.91/vblo/03,656.99,yes,locked 2006.203.07:51:02.91/vblo/04,712.99,yes,locked 2006.203.07:51:02.91/vblo/05,744.99,yes,locked 2006.203.07:51:02.91/vblo/06,752.99,yes,locked 2006.203.07:51:02.91/vblo/07,734.99,yes,locked 2006.203.07:51:02.91/vblo/08,744.99,yes,locked 2006.203.07:51:03.06/vabw/8 2006.203.07:51:03.21/vbbw/8 2006.203.07:51:03.30/xfe/off,on,14.0 2006.203.07:51:03.67/ifatt/23,28,28,28 2006.203.07:51:04.08/fmout-gps/S +4.55E-07 2006.203.07:51:04.16:!2006.203.07:52:00 2006.203.07:52:00.00:data_valid=off 2006.203.07:52:00.00:postob 2006.203.07:52:00.10/cable/+6.4587E-03 2006.203.07:52:00.10/wx/23.81,1001.2,98 2006.203.07:52:01.07/fmout-gps/S +4.54E-07 2006.203.07:52:01.07:scan_name=203-0752,k06203,60 2006.203.07:52:01.08:source=3c418,203837.03,511912.7,2000.0,cw 2006.203.07:52:01.14#flagr#flagr/antenna,new-source 2006.203.07:52:02.14:checkk5 2006.203.07:52:02.53/chk_autoobs//k5ts1/ autoobs is running! 2006.203.07:52:02.95/chk_autoobs//k5ts2/ autoobs is running! 2006.203.07:52:03.34/chk_autoobs//k5ts3/ autoobs is running! 2006.203.07:52:03.75/chk_autoobs//k5ts4/ autoobs is running! 2006.203.07:52:04.14/chk_obsdata//k5ts1/T2030751??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.203.07:52:04.78/chk_obsdata//k5ts2/T2030751??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.203.07:52:05.44/chk_obsdata//k5ts3/T2030751??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.203.07:52:06.05/chk_obsdata//k5ts4/T2030751??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.203.07:52:06.85/k5log//k5ts1_log_newline 2006.203.07:52:07.60/k5log//k5ts2_log_newline 2006.203.07:52:08.64/k5log//k5ts3_log_newline 2006.203.07:52:12.41/k5log//k5ts4_log_newline 2006.203.07:52:12.44/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.203.07:52:12.44:4f8m12a=1 2006.203.07:52:12.44$4f8m12a/echo=on 2006.203.07:52:12.44$4f8m12a/pcalon 2006.203.07:52:12.44$pcalon/"no phase cal control is implemented here 2006.203.07:52:12.44$4f8m12a/"tpicd=stop 2006.203.07:52:12.44$4f8m12a/vc4f8 2006.203.07:52:12.44$vc4f8/valo=1,532.99 2006.203.07:52:12.44#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.203.07:52:12.44#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.203.07:52:12.44#ibcon#ireg 17 cls_cnt 0 2006.203.07:52:12.44#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.203.07:52:12.44#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.203.07:52:12.44#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.203.07:52:12.44#ibcon#enter wrdev, iclass 12, count 0 2006.203.07:52:12.44#ibcon#first serial, iclass 12, count 0 2006.203.07:52:12.44#ibcon#enter sib2, iclass 12, count 0 2006.203.07:52:12.44#ibcon#flushed, iclass 12, count 0 2006.203.07:52:12.44#ibcon#about to write, iclass 12, count 0 2006.203.07:52:12.44#ibcon#wrote, iclass 12, count 0 2006.203.07:52:12.44#ibcon#about to read 3, iclass 12, count 0 2006.203.07:52:12.48#ibcon#read 3, iclass 12, count 0 2006.203.07:52:12.48#ibcon#about to read 4, iclass 12, count 0 2006.203.07:52:12.48#ibcon#read 4, iclass 12, count 0 2006.203.07:52:12.48#ibcon#about to read 5, iclass 12, count 0 2006.203.07:52:12.48#ibcon#read 5, iclass 12, count 0 2006.203.07:52:12.48#ibcon#about to read 6, iclass 12, count 0 2006.203.07:52:12.48#ibcon#read 6, iclass 12, count 0 2006.203.07:52:12.48#ibcon#end of sib2, iclass 12, count 0 2006.203.07:52:12.48#ibcon#*mode == 0, iclass 12, count 0 2006.203.07:52:12.48#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.203.07:52:12.48#ibcon#[26=FRQ=01,532.99\r\n] 2006.203.07:52:12.48#ibcon#*before write, iclass 12, count 0 2006.203.07:52:12.48#ibcon#enter sib2, iclass 12, count 0 2006.203.07:52:12.48#ibcon#flushed, iclass 12, count 0 2006.203.07:52:12.48#ibcon#about to write, iclass 12, count 0 2006.203.07:52:12.48#ibcon#wrote, iclass 12, count 0 2006.203.07:52:12.48#ibcon#about to read 3, iclass 12, count 0 2006.203.07:52:12.53#ibcon#read 3, iclass 12, count 0 2006.203.07:52:12.53#ibcon#about to read 4, iclass 12, count 0 2006.203.07:52:12.53#ibcon#read 4, iclass 12, count 0 2006.203.07:52:12.53#ibcon#about to read 5, iclass 12, count 0 2006.203.07:52:12.53#ibcon#read 5, iclass 12, count 0 2006.203.07:52:12.53#ibcon#about to read 6, iclass 12, count 0 2006.203.07:52:12.53#ibcon#read 6, iclass 12, count 0 2006.203.07:52:12.53#ibcon#end of sib2, iclass 12, count 0 2006.203.07:52:12.53#ibcon#*after write, iclass 12, count 0 2006.203.07:52:12.53#ibcon#*before return 0, iclass 12, count 0 2006.203.07:52:12.53#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.203.07:52:12.53#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.203.07:52:12.53#ibcon#about to clear, iclass 12 cls_cnt 0 2006.203.07:52:12.53#ibcon#cleared, iclass 12 cls_cnt 0 2006.203.07:52:12.53$vc4f8/va=1,8 2006.203.07:52:12.53#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.203.07:52:12.53#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.203.07:52:12.53#ibcon#ireg 11 cls_cnt 2 2006.203.07:52:12.53#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.203.07:52:12.53#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.203.07:52:12.53#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.203.07:52:12.53#ibcon#enter wrdev, iclass 14, count 2 2006.203.07:52:12.53#ibcon#first serial, iclass 14, count 2 2006.203.07:52:12.53#ibcon#enter sib2, iclass 14, count 2 2006.203.07:52:12.53#ibcon#flushed, iclass 14, count 2 2006.203.07:52:12.53#ibcon#about to write, iclass 14, count 2 2006.203.07:52:12.53#ibcon#wrote, iclass 14, count 2 2006.203.07:52:12.53#ibcon#about to read 3, iclass 14, count 2 2006.203.07:52:12.55#ibcon#read 3, iclass 14, count 2 2006.203.07:52:12.55#ibcon#about to read 4, iclass 14, count 2 2006.203.07:52:12.56#ibcon#read 4, iclass 14, count 2 2006.203.07:52:12.56#ibcon#about to read 5, iclass 14, count 2 2006.203.07:52:12.56#ibcon#read 5, iclass 14, count 2 2006.203.07:52:12.56#ibcon#about to read 6, iclass 14, count 2 2006.203.07:52:12.56#ibcon#read 6, iclass 14, count 2 2006.203.07:52:12.56#ibcon#end of sib2, iclass 14, count 2 2006.203.07:52:12.56#ibcon#*mode == 0, iclass 14, count 2 2006.203.07:52:12.56#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.203.07:52:12.56#ibcon#[25=AT01-08\r\n] 2006.203.07:52:12.56#ibcon#*before write, iclass 14, count 2 2006.203.07:52:12.56#ibcon#enter sib2, iclass 14, count 2 2006.203.07:52:12.56#ibcon#flushed, iclass 14, count 2 2006.203.07:52:12.56#ibcon#about to write, iclass 14, count 2 2006.203.07:52:12.56#ibcon#wrote, iclass 14, count 2 2006.203.07:52:12.56#ibcon#about to read 3, iclass 14, count 2 2006.203.07:52:12.59#ibcon#read 3, iclass 14, count 2 2006.203.07:52:12.59#ibcon#about to read 4, iclass 14, count 2 2006.203.07:52:12.59#ibcon#read 4, iclass 14, count 2 2006.203.07:52:12.59#ibcon#about to read 5, iclass 14, count 2 2006.203.07:52:12.59#ibcon#read 5, iclass 14, count 2 2006.203.07:52:12.59#ibcon#about to read 6, iclass 14, count 2 2006.203.07:52:12.59#ibcon#read 6, iclass 14, count 2 2006.203.07:52:12.59#ibcon#end of sib2, iclass 14, count 2 2006.203.07:52:12.59#ibcon#*after write, iclass 14, count 2 2006.203.07:52:12.59#ibcon#*before return 0, iclass 14, count 2 2006.203.07:52:12.59#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.203.07:52:12.59#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.203.07:52:12.59#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.203.07:52:12.59#ibcon#ireg 7 cls_cnt 0 2006.203.07:52:12.59#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.203.07:52:12.71#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.203.07:52:12.71#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.203.07:52:12.71#ibcon#enter wrdev, iclass 14, count 0 2006.203.07:52:12.71#ibcon#first serial, iclass 14, count 0 2006.203.07:52:12.71#ibcon#enter sib2, iclass 14, count 0 2006.203.07:52:12.71#ibcon#flushed, iclass 14, count 0 2006.203.07:52:12.71#ibcon#about to write, iclass 14, count 0 2006.203.07:52:12.71#ibcon#wrote, iclass 14, count 0 2006.203.07:52:12.71#ibcon#about to read 3, iclass 14, count 0 2006.203.07:52:12.73#ibcon#read 3, iclass 14, count 0 2006.203.07:52:12.73#ibcon#about to read 4, iclass 14, count 0 2006.203.07:52:12.73#ibcon#read 4, iclass 14, count 0 2006.203.07:52:12.73#ibcon#about to read 5, iclass 14, count 0 2006.203.07:52:12.73#ibcon#read 5, iclass 14, count 0 2006.203.07:52:12.73#ibcon#about to read 6, iclass 14, count 0 2006.203.07:52:12.73#ibcon#read 6, iclass 14, count 0 2006.203.07:52:12.73#ibcon#end of sib2, iclass 14, count 0 2006.203.07:52:12.73#ibcon#*mode == 0, iclass 14, count 0 2006.203.07:52:12.73#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.203.07:52:12.73#ibcon#[25=USB\r\n] 2006.203.07:52:12.73#ibcon#*before write, iclass 14, count 0 2006.203.07:52:12.73#ibcon#enter sib2, iclass 14, count 0 2006.203.07:52:12.73#ibcon#flushed, iclass 14, count 0 2006.203.07:52:12.73#ibcon#about to write, iclass 14, count 0 2006.203.07:52:12.73#ibcon#wrote, iclass 14, count 0 2006.203.07:52:12.73#ibcon#about to read 3, iclass 14, count 0 2006.203.07:52:12.76#ibcon#read 3, iclass 14, count 0 2006.203.07:52:12.76#ibcon#about to read 4, iclass 14, count 0 2006.203.07:52:12.76#ibcon#read 4, iclass 14, count 0 2006.203.07:52:12.76#ibcon#about to read 5, iclass 14, count 0 2006.203.07:52:12.76#ibcon#read 5, iclass 14, count 0 2006.203.07:52:12.76#ibcon#about to read 6, iclass 14, count 0 2006.203.07:52:12.76#ibcon#read 6, iclass 14, count 0 2006.203.07:52:12.76#ibcon#end of sib2, iclass 14, count 0 2006.203.07:52:12.76#ibcon#*after write, iclass 14, count 0 2006.203.07:52:12.76#ibcon#*before return 0, iclass 14, count 0 2006.203.07:52:12.76#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.203.07:52:12.76#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.203.07:52:12.76#ibcon#about to clear, iclass 14 cls_cnt 0 2006.203.07:52:12.76#ibcon#cleared, iclass 14 cls_cnt 0 2006.203.07:52:12.76$vc4f8/valo=2,572.99 2006.203.07:52:12.76#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.203.07:52:12.76#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.203.07:52:12.76#ibcon#ireg 17 cls_cnt 0 2006.203.07:52:12.76#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.203.07:52:12.76#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.203.07:52:12.76#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.203.07:52:12.76#ibcon#enter wrdev, iclass 16, count 0 2006.203.07:52:12.76#ibcon#first serial, iclass 16, count 0 2006.203.07:52:12.76#ibcon#enter sib2, iclass 16, count 0 2006.203.07:52:12.76#ibcon#flushed, iclass 16, count 0 2006.203.07:52:12.76#ibcon#about to write, iclass 16, count 0 2006.203.07:52:12.76#ibcon#wrote, iclass 16, count 0 2006.203.07:52:12.76#ibcon#about to read 3, iclass 16, count 0 2006.203.07:52:12.79#ibcon#read 3, iclass 16, count 0 2006.203.07:52:12.79#ibcon#about to read 4, iclass 16, count 0 2006.203.07:52:12.79#ibcon#read 4, iclass 16, count 0 2006.203.07:52:12.79#ibcon#about to read 5, iclass 16, count 0 2006.203.07:52:12.79#ibcon#read 5, iclass 16, count 0 2006.203.07:52:12.79#ibcon#about to read 6, iclass 16, count 0 2006.203.07:52:12.79#ibcon#read 6, iclass 16, count 0 2006.203.07:52:12.79#ibcon#end of sib2, iclass 16, count 0 2006.203.07:52:12.79#ibcon#*mode == 0, iclass 16, count 0 2006.203.07:52:12.79#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.203.07:52:12.79#ibcon#[26=FRQ=02,572.99\r\n] 2006.203.07:52:12.79#ibcon#*before write, iclass 16, count 0 2006.203.07:52:12.79#ibcon#enter sib2, iclass 16, count 0 2006.203.07:52:12.79#ibcon#flushed, iclass 16, count 0 2006.203.07:52:12.79#ibcon#about to write, iclass 16, count 0 2006.203.07:52:12.79#ibcon#wrote, iclass 16, count 0 2006.203.07:52:12.79#ibcon#about to read 3, iclass 16, count 0 2006.203.07:52:12.83#ibcon#read 3, iclass 16, count 0 2006.203.07:52:12.83#ibcon#about to read 4, iclass 16, count 0 2006.203.07:52:12.83#ibcon#read 4, iclass 16, count 0 2006.203.07:52:12.83#ibcon#about to read 5, iclass 16, count 0 2006.203.07:52:12.83#ibcon#read 5, iclass 16, count 0 2006.203.07:52:12.83#ibcon#about to read 6, iclass 16, count 0 2006.203.07:52:12.83#ibcon#read 6, iclass 16, count 0 2006.203.07:52:12.83#ibcon#end of sib2, iclass 16, count 0 2006.203.07:52:12.83#ibcon#*after write, iclass 16, count 0 2006.203.07:52:12.83#ibcon#*before return 0, iclass 16, count 0 2006.203.07:52:12.83#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.203.07:52:12.83#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.203.07:52:12.83#ibcon#about to clear, iclass 16 cls_cnt 0 2006.203.07:52:12.83#ibcon#cleared, iclass 16 cls_cnt 0 2006.203.07:52:12.83$vc4f8/va=2,7 2006.203.07:52:12.83#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.203.07:52:12.83#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.203.07:52:12.83#ibcon#ireg 11 cls_cnt 2 2006.203.07:52:12.83#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.203.07:52:12.88#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.203.07:52:12.88#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.203.07:52:12.88#ibcon#enter wrdev, iclass 18, count 2 2006.203.07:52:12.88#ibcon#first serial, iclass 18, count 2 2006.203.07:52:12.88#ibcon#enter sib2, iclass 18, count 2 2006.203.07:52:12.88#ibcon#flushed, iclass 18, count 2 2006.203.07:52:12.88#ibcon#about to write, iclass 18, count 2 2006.203.07:52:12.88#ibcon#wrote, iclass 18, count 2 2006.203.07:52:12.88#ibcon#about to read 3, iclass 18, count 2 2006.203.07:52:12.90#ibcon#read 3, iclass 18, count 2 2006.203.07:52:12.90#ibcon#about to read 4, iclass 18, count 2 2006.203.07:52:12.90#ibcon#read 4, iclass 18, count 2 2006.203.07:52:12.90#ibcon#about to read 5, iclass 18, count 2 2006.203.07:52:12.90#ibcon#read 5, iclass 18, count 2 2006.203.07:52:12.90#ibcon#about to read 6, iclass 18, count 2 2006.203.07:52:12.90#ibcon#read 6, iclass 18, count 2 2006.203.07:52:12.90#ibcon#end of sib2, iclass 18, count 2 2006.203.07:52:12.90#ibcon#*mode == 0, iclass 18, count 2 2006.203.07:52:12.90#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.203.07:52:12.90#ibcon#[25=AT02-07\r\n] 2006.203.07:52:12.90#ibcon#*before write, iclass 18, count 2 2006.203.07:52:12.90#ibcon#enter sib2, iclass 18, count 2 2006.203.07:52:12.90#ibcon#flushed, iclass 18, count 2 2006.203.07:52:12.90#ibcon#about to write, iclass 18, count 2 2006.203.07:52:12.90#ibcon#wrote, iclass 18, count 2 2006.203.07:52:12.90#ibcon#about to read 3, iclass 18, count 2 2006.203.07:52:12.93#ibcon#read 3, iclass 18, count 2 2006.203.07:52:12.93#ibcon#about to read 4, iclass 18, count 2 2006.203.07:52:12.93#ibcon#read 4, iclass 18, count 2 2006.203.07:52:12.93#ibcon#about to read 5, iclass 18, count 2 2006.203.07:52:12.93#ibcon#read 5, iclass 18, count 2 2006.203.07:52:12.93#ibcon#about to read 6, iclass 18, count 2 2006.203.07:52:12.93#ibcon#read 6, iclass 18, count 2 2006.203.07:52:12.93#ibcon#end of sib2, iclass 18, count 2 2006.203.07:52:12.93#ibcon#*after write, iclass 18, count 2 2006.203.07:52:12.93#ibcon#*before return 0, iclass 18, count 2 2006.203.07:52:12.93#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.203.07:52:12.93#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.203.07:52:12.93#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.203.07:52:12.93#ibcon#ireg 7 cls_cnt 0 2006.203.07:52:12.93#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.203.07:52:13.05#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.203.07:52:13.05#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.203.07:52:13.05#ibcon#enter wrdev, iclass 18, count 0 2006.203.07:52:13.05#ibcon#first serial, iclass 18, count 0 2006.203.07:52:13.05#ibcon#enter sib2, iclass 18, count 0 2006.203.07:52:13.05#ibcon#flushed, iclass 18, count 0 2006.203.07:52:13.05#ibcon#about to write, iclass 18, count 0 2006.203.07:52:13.05#ibcon#wrote, iclass 18, count 0 2006.203.07:52:13.05#ibcon#about to read 3, iclass 18, count 0 2006.203.07:52:13.09#ibcon#read 3, iclass 18, count 0 2006.203.07:52:13.09#ibcon#about to read 4, iclass 18, count 0 2006.203.07:52:13.09#ibcon#read 4, iclass 18, count 0 2006.203.07:52:13.09#ibcon#about to read 5, iclass 18, count 0 2006.203.07:52:13.09#ibcon#read 5, iclass 18, count 0 2006.203.07:52:13.09#ibcon#about to read 6, iclass 18, count 0 2006.203.07:52:13.09#ibcon#read 6, iclass 18, count 0 2006.203.07:52:13.09#ibcon#end of sib2, iclass 18, count 0 2006.203.07:52:13.09#ibcon#*mode == 0, iclass 18, count 0 2006.203.07:52:13.09#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.203.07:52:13.09#ibcon#[25=USB\r\n] 2006.203.07:52:13.09#ibcon#*before write, iclass 18, count 0 2006.203.07:52:13.09#ibcon#enter sib2, iclass 18, count 0 2006.203.07:52:13.09#ibcon#flushed, iclass 18, count 0 2006.203.07:52:13.09#ibcon#about to write, iclass 18, count 0 2006.203.07:52:13.09#ibcon#wrote, iclass 18, count 0 2006.203.07:52:13.09#ibcon#about to read 3, iclass 18, count 0 2006.203.07:52:13.12#ibcon#read 3, iclass 18, count 0 2006.203.07:52:13.12#ibcon#about to read 4, iclass 18, count 0 2006.203.07:52:13.12#ibcon#read 4, iclass 18, count 0 2006.203.07:52:13.12#ibcon#about to read 5, iclass 18, count 0 2006.203.07:52:13.12#ibcon#read 5, iclass 18, count 0 2006.203.07:52:13.12#ibcon#about to read 6, iclass 18, count 0 2006.203.07:52:13.12#ibcon#read 6, iclass 18, count 0 2006.203.07:52:13.12#ibcon#end of sib2, iclass 18, count 0 2006.203.07:52:13.12#ibcon#*after write, iclass 18, count 0 2006.203.07:52:13.12#ibcon#*before return 0, iclass 18, count 0 2006.203.07:52:13.12#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.203.07:52:13.12#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.203.07:52:13.12#ibcon#about to clear, iclass 18 cls_cnt 0 2006.203.07:52:13.12#ibcon#cleared, iclass 18 cls_cnt 0 2006.203.07:52:13.12$vc4f8/valo=3,672.99 2006.203.07:52:13.12#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.203.07:52:13.12#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.203.07:52:13.12#ibcon#ireg 17 cls_cnt 0 2006.203.07:52:13.12#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.203.07:52:13.12#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.203.07:52:13.12#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.203.07:52:13.12#ibcon#enter wrdev, iclass 20, count 0 2006.203.07:52:13.12#ibcon#first serial, iclass 20, count 0 2006.203.07:52:13.12#ibcon#enter sib2, iclass 20, count 0 2006.203.07:52:13.12#ibcon#flushed, iclass 20, count 0 2006.203.07:52:13.12#ibcon#about to write, iclass 20, count 0 2006.203.07:52:13.12#ibcon#wrote, iclass 20, count 0 2006.203.07:52:13.12#ibcon#about to read 3, iclass 20, count 0 2006.203.07:52:13.14#ibcon#read 3, iclass 20, count 0 2006.203.07:52:13.14#ibcon#about to read 4, iclass 20, count 0 2006.203.07:52:13.14#ibcon#read 4, iclass 20, count 0 2006.203.07:52:13.14#ibcon#about to read 5, iclass 20, count 0 2006.203.07:52:13.14#ibcon#read 5, iclass 20, count 0 2006.203.07:52:13.14#ibcon#about to read 6, iclass 20, count 0 2006.203.07:52:13.14#ibcon#read 6, iclass 20, count 0 2006.203.07:52:13.14#ibcon#end of sib2, iclass 20, count 0 2006.203.07:52:13.14#ibcon#*mode == 0, iclass 20, count 0 2006.203.07:52:13.14#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.203.07:52:13.14#ibcon#[26=FRQ=03,672.99\r\n] 2006.203.07:52:13.14#ibcon#*before write, iclass 20, count 0 2006.203.07:52:13.14#ibcon#enter sib2, iclass 20, count 0 2006.203.07:52:13.14#ibcon#flushed, iclass 20, count 0 2006.203.07:52:13.14#ibcon#about to write, iclass 20, count 0 2006.203.07:52:13.14#ibcon#wrote, iclass 20, count 0 2006.203.07:52:13.14#ibcon#about to read 3, iclass 20, count 0 2006.203.07:52:13.18#ibcon#read 3, iclass 20, count 0 2006.203.07:52:13.18#ibcon#about to read 4, iclass 20, count 0 2006.203.07:52:13.18#ibcon#read 4, iclass 20, count 0 2006.203.07:52:13.18#ibcon#about to read 5, iclass 20, count 0 2006.203.07:52:13.18#ibcon#read 5, iclass 20, count 0 2006.203.07:52:13.18#ibcon#about to read 6, iclass 20, count 0 2006.203.07:52:13.18#ibcon#read 6, iclass 20, count 0 2006.203.07:52:13.18#ibcon#end of sib2, iclass 20, count 0 2006.203.07:52:13.18#ibcon#*after write, iclass 20, count 0 2006.203.07:52:13.18#ibcon#*before return 0, iclass 20, count 0 2006.203.07:52:13.18#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.203.07:52:13.18#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.203.07:52:13.18#ibcon#about to clear, iclass 20 cls_cnt 0 2006.203.07:52:13.18#ibcon#cleared, iclass 20 cls_cnt 0 2006.203.07:52:13.18$vc4f8/va=3,8 2006.203.07:52:13.18#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.203.07:52:13.18#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.203.07:52:13.18#ibcon#ireg 11 cls_cnt 2 2006.203.07:52:13.18#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.203.07:52:13.24#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.203.07:52:13.24#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.203.07:52:13.24#ibcon#enter wrdev, iclass 22, count 2 2006.203.07:52:13.24#ibcon#first serial, iclass 22, count 2 2006.203.07:52:13.24#ibcon#enter sib2, iclass 22, count 2 2006.203.07:52:13.24#ibcon#flushed, iclass 22, count 2 2006.203.07:52:13.24#ibcon#about to write, iclass 22, count 2 2006.203.07:52:13.24#ibcon#wrote, iclass 22, count 2 2006.203.07:52:13.24#ibcon#about to read 3, iclass 22, count 2 2006.203.07:52:13.26#ibcon#read 3, iclass 22, count 2 2006.203.07:52:13.26#ibcon#about to read 4, iclass 22, count 2 2006.203.07:52:13.26#ibcon#read 4, iclass 22, count 2 2006.203.07:52:13.26#ibcon#about to read 5, iclass 22, count 2 2006.203.07:52:13.26#ibcon#read 5, iclass 22, count 2 2006.203.07:52:13.26#ibcon#about to read 6, iclass 22, count 2 2006.203.07:52:13.26#ibcon#read 6, iclass 22, count 2 2006.203.07:52:13.26#ibcon#end of sib2, iclass 22, count 2 2006.203.07:52:13.26#ibcon#*mode == 0, iclass 22, count 2 2006.203.07:52:13.26#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.203.07:52:13.26#ibcon#[25=AT03-08\r\n] 2006.203.07:52:13.26#ibcon#*before write, iclass 22, count 2 2006.203.07:52:13.26#ibcon#enter sib2, iclass 22, count 2 2006.203.07:52:13.26#ibcon#flushed, iclass 22, count 2 2006.203.07:52:13.26#ibcon#about to write, iclass 22, count 2 2006.203.07:52:13.26#ibcon#wrote, iclass 22, count 2 2006.203.07:52:13.26#ibcon#about to read 3, iclass 22, count 2 2006.203.07:52:13.29#ibcon#read 3, iclass 22, count 2 2006.203.07:52:13.29#ibcon#about to read 4, iclass 22, count 2 2006.203.07:52:13.29#ibcon#read 4, iclass 22, count 2 2006.203.07:52:13.29#ibcon#about to read 5, iclass 22, count 2 2006.203.07:52:13.29#ibcon#read 5, iclass 22, count 2 2006.203.07:52:13.29#ibcon#about to read 6, iclass 22, count 2 2006.203.07:52:13.29#ibcon#read 6, iclass 22, count 2 2006.203.07:52:13.29#ibcon#end of sib2, iclass 22, count 2 2006.203.07:52:13.29#ibcon#*after write, iclass 22, count 2 2006.203.07:52:13.29#ibcon#*before return 0, iclass 22, count 2 2006.203.07:52:13.29#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.203.07:52:13.29#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.203.07:52:13.29#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.203.07:52:13.29#ibcon#ireg 7 cls_cnt 0 2006.203.07:52:13.29#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.203.07:52:13.41#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.203.07:52:13.41#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.203.07:52:13.41#ibcon#enter wrdev, iclass 22, count 0 2006.203.07:52:13.41#ibcon#first serial, iclass 22, count 0 2006.203.07:52:13.41#ibcon#enter sib2, iclass 22, count 0 2006.203.07:52:13.41#ibcon#flushed, iclass 22, count 0 2006.203.07:52:13.41#ibcon#about to write, iclass 22, count 0 2006.203.07:52:13.41#ibcon#wrote, iclass 22, count 0 2006.203.07:52:13.41#ibcon#about to read 3, iclass 22, count 0 2006.203.07:52:13.43#ibcon#read 3, iclass 22, count 0 2006.203.07:52:13.43#ibcon#about to read 4, iclass 22, count 0 2006.203.07:52:13.43#ibcon#read 4, iclass 22, count 0 2006.203.07:52:13.43#ibcon#about to read 5, iclass 22, count 0 2006.203.07:52:13.43#ibcon#read 5, iclass 22, count 0 2006.203.07:52:13.43#ibcon#about to read 6, iclass 22, count 0 2006.203.07:52:13.43#ibcon#read 6, iclass 22, count 0 2006.203.07:52:13.43#ibcon#end of sib2, iclass 22, count 0 2006.203.07:52:13.43#ibcon#*mode == 0, iclass 22, count 0 2006.203.07:52:13.43#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.203.07:52:13.43#ibcon#[25=USB\r\n] 2006.203.07:52:13.43#ibcon#*before write, iclass 22, count 0 2006.203.07:52:13.43#ibcon#enter sib2, iclass 22, count 0 2006.203.07:52:13.43#ibcon#flushed, iclass 22, count 0 2006.203.07:52:13.43#ibcon#about to write, iclass 22, count 0 2006.203.07:52:13.43#ibcon#wrote, iclass 22, count 0 2006.203.07:52:13.43#ibcon#about to read 3, iclass 22, count 0 2006.203.07:52:13.46#ibcon#read 3, iclass 22, count 0 2006.203.07:52:13.46#ibcon#about to read 4, iclass 22, count 0 2006.203.07:52:13.46#ibcon#read 4, iclass 22, count 0 2006.203.07:52:13.46#ibcon#about to read 5, iclass 22, count 0 2006.203.07:52:13.46#ibcon#read 5, iclass 22, count 0 2006.203.07:52:13.46#ibcon#about to read 6, iclass 22, count 0 2006.203.07:52:13.46#ibcon#read 6, iclass 22, count 0 2006.203.07:52:13.46#ibcon#end of sib2, iclass 22, count 0 2006.203.07:52:13.46#ibcon#*after write, iclass 22, count 0 2006.203.07:52:13.46#ibcon#*before return 0, iclass 22, count 0 2006.203.07:52:13.46#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.203.07:52:13.46#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.203.07:52:13.46#ibcon#about to clear, iclass 22 cls_cnt 0 2006.203.07:52:13.46#ibcon#cleared, iclass 22 cls_cnt 0 2006.203.07:52:13.46$vc4f8/valo=4,832.99 2006.203.07:52:13.46#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.203.07:52:13.46#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.203.07:52:13.46#ibcon#ireg 17 cls_cnt 0 2006.203.07:52:13.46#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.203.07:52:13.46#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.203.07:52:13.46#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.203.07:52:13.46#ibcon#enter wrdev, iclass 24, count 0 2006.203.07:52:13.46#ibcon#first serial, iclass 24, count 0 2006.203.07:52:13.46#ibcon#enter sib2, iclass 24, count 0 2006.203.07:52:13.46#ibcon#flushed, iclass 24, count 0 2006.203.07:52:13.46#ibcon#about to write, iclass 24, count 0 2006.203.07:52:13.46#ibcon#wrote, iclass 24, count 0 2006.203.07:52:13.46#ibcon#about to read 3, iclass 24, count 0 2006.203.07:52:13.48#ibcon#read 3, iclass 24, count 0 2006.203.07:52:13.48#ibcon#about to read 4, iclass 24, count 0 2006.203.07:52:13.48#ibcon#read 4, iclass 24, count 0 2006.203.07:52:13.48#ibcon#about to read 5, iclass 24, count 0 2006.203.07:52:13.48#ibcon#read 5, iclass 24, count 0 2006.203.07:52:13.48#ibcon#about to read 6, iclass 24, count 0 2006.203.07:52:13.48#ibcon#read 6, iclass 24, count 0 2006.203.07:52:13.48#ibcon#end of sib2, iclass 24, count 0 2006.203.07:52:13.48#ibcon#*mode == 0, iclass 24, count 0 2006.203.07:52:13.48#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.203.07:52:13.48#ibcon#[26=FRQ=04,832.99\r\n] 2006.203.07:52:13.48#ibcon#*before write, iclass 24, count 0 2006.203.07:52:13.48#ibcon#enter sib2, iclass 24, count 0 2006.203.07:52:13.48#ibcon#flushed, iclass 24, count 0 2006.203.07:52:13.48#ibcon#about to write, iclass 24, count 0 2006.203.07:52:13.48#ibcon#wrote, iclass 24, count 0 2006.203.07:52:13.48#ibcon#about to read 3, iclass 24, count 0 2006.203.07:52:13.52#ibcon#read 3, iclass 24, count 0 2006.203.07:52:13.52#ibcon#about to read 4, iclass 24, count 0 2006.203.07:52:13.52#ibcon#read 4, iclass 24, count 0 2006.203.07:52:13.52#ibcon#about to read 5, iclass 24, count 0 2006.203.07:52:13.52#ibcon#read 5, iclass 24, count 0 2006.203.07:52:13.52#ibcon#about to read 6, iclass 24, count 0 2006.203.07:52:13.52#ibcon#read 6, iclass 24, count 0 2006.203.07:52:13.52#ibcon#end of sib2, iclass 24, count 0 2006.203.07:52:13.52#ibcon#*after write, iclass 24, count 0 2006.203.07:52:13.52#ibcon#*before return 0, iclass 24, count 0 2006.203.07:52:13.52#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.203.07:52:13.52#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.203.07:52:13.52#ibcon#about to clear, iclass 24 cls_cnt 0 2006.203.07:52:13.52#ibcon#cleared, iclass 24 cls_cnt 0 2006.203.07:52:13.52$vc4f8/va=4,7 2006.203.07:52:13.52#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.203.07:52:13.52#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.203.07:52:13.52#ibcon#ireg 11 cls_cnt 2 2006.203.07:52:13.52#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.203.07:52:13.58#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.203.07:52:13.58#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.203.07:52:13.58#ibcon#enter wrdev, iclass 26, count 2 2006.203.07:52:13.58#ibcon#first serial, iclass 26, count 2 2006.203.07:52:13.58#ibcon#enter sib2, iclass 26, count 2 2006.203.07:52:13.58#ibcon#flushed, iclass 26, count 2 2006.203.07:52:13.58#ibcon#about to write, iclass 26, count 2 2006.203.07:52:13.58#ibcon#wrote, iclass 26, count 2 2006.203.07:52:13.58#ibcon#about to read 3, iclass 26, count 2 2006.203.07:52:13.60#ibcon#read 3, iclass 26, count 2 2006.203.07:52:13.60#ibcon#about to read 4, iclass 26, count 2 2006.203.07:52:13.60#ibcon#read 4, iclass 26, count 2 2006.203.07:52:13.60#ibcon#about to read 5, iclass 26, count 2 2006.203.07:52:13.60#ibcon#read 5, iclass 26, count 2 2006.203.07:52:13.60#ibcon#about to read 6, iclass 26, count 2 2006.203.07:52:13.60#ibcon#read 6, iclass 26, count 2 2006.203.07:52:13.60#ibcon#end of sib2, iclass 26, count 2 2006.203.07:52:13.60#ibcon#*mode == 0, iclass 26, count 2 2006.203.07:52:13.60#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.203.07:52:13.60#ibcon#[25=AT04-07\r\n] 2006.203.07:52:13.60#ibcon#*before write, iclass 26, count 2 2006.203.07:52:13.60#ibcon#enter sib2, iclass 26, count 2 2006.203.07:52:13.60#ibcon#flushed, iclass 26, count 2 2006.203.07:52:13.60#ibcon#about to write, iclass 26, count 2 2006.203.07:52:13.60#ibcon#wrote, iclass 26, count 2 2006.203.07:52:13.60#ibcon#about to read 3, iclass 26, count 2 2006.203.07:52:13.63#ibcon#read 3, iclass 26, count 2 2006.203.07:52:13.63#ibcon#about to read 4, iclass 26, count 2 2006.203.07:52:13.63#ibcon#read 4, iclass 26, count 2 2006.203.07:52:13.63#ibcon#about to read 5, iclass 26, count 2 2006.203.07:52:13.63#ibcon#read 5, iclass 26, count 2 2006.203.07:52:13.63#ibcon#about to read 6, iclass 26, count 2 2006.203.07:52:13.63#ibcon#read 6, iclass 26, count 2 2006.203.07:52:13.63#ibcon#end of sib2, iclass 26, count 2 2006.203.07:52:13.63#ibcon#*after write, iclass 26, count 2 2006.203.07:52:13.63#ibcon#*before return 0, iclass 26, count 2 2006.203.07:52:13.63#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.203.07:52:13.63#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.203.07:52:13.63#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.203.07:52:13.63#ibcon#ireg 7 cls_cnt 0 2006.203.07:52:13.63#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.203.07:52:13.75#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.203.07:52:13.75#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.203.07:52:13.75#ibcon#enter wrdev, iclass 26, count 0 2006.203.07:52:13.75#ibcon#first serial, iclass 26, count 0 2006.203.07:52:13.75#ibcon#enter sib2, iclass 26, count 0 2006.203.07:52:13.75#ibcon#flushed, iclass 26, count 0 2006.203.07:52:13.75#ibcon#about to write, iclass 26, count 0 2006.203.07:52:13.75#ibcon#wrote, iclass 26, count 0 2006.203.07:52:13.75#ibcon#about to read 3, iclass 26, count 0 2006.203.07:52:13.77#ibcon#read 3, iclass 26, count 0 2006.203.07:52:13.77#ibcon#about to read 4, iclass 26, count 0 2006.203.07:52:13.77#ibcon#read 4, iclass 26, count 0 2006.203.07:52:13.77#ibcon#about to read 5, iclass 26, count 0 2006.203.07:52:13.77#ibcon#read 5, iclass 26, count 0 2006.203.07:52:13.77#ibcon#about to read 6, iclass 26, count 0 2006.203.07:52:13.77#ibcon#read 6, iclass 26, count 0 2006.203.07:52:13.77#ibcon#end of sib2, iclass 26, count 0 2006.203.07:52:13.77#ibcon#*mode == 0, iclass 26, count 0 2006.203.07:52:13.77#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.203.07:52:13.77#ibcon#[25=USB\r\n] 2006.203.07:52:13.77#ibcon#*before write, iclass 26, count 0 2006.203.07:52:13.77#ibcon#enter sib2, iclass 26, count 0 2006.203.07:52:13.77#ibcon#flushed, iclass 26, count 0 2006.203.07:52:13.77#ibcon#about to write, iclass 26, count 0 2006.203.07:52:13.77#ibcon#wrote, iclass 26, count 0 2006.203.07:52:13.77#ibcon#about to read 3, iclass 26, count 0 2006.203.07:52:13.80#ibcon#read 3, iclass 26, count 0 2006.203.07:52:13.80#ibcon#about to read 4, iclass 26, count 0 2006.203.07:52:13.80#ibcon#read 4, iclass 26, count 0 2006.203.07:52:13.80#ibcon#about to read 5, iclass 26, count 0 2006.203.07:52:13.80#ibcon#read 5, iclass 26, count 0 2006.203.07:52:13.80#ibcon#about to read 6, iclass 26, count 0 2006.203.07:52:13.80#ibcon#read 6, iclass 26, count 0 2006.203.07:52:13.80#ibcon#end of sib2, iclass 26, count 0 2006.203.07:52:13.80#ibcon#*after write, iclass 26, count 0 2006.203.07:52:13.80#ibcon#*before return 0, iclass 26, count 0 2006.203.07:52:13.80#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.203.07:52:13.80#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.203.07:52:13.80#ibcon#about to clear, iclass 26 cls_cnt 0 2006.203.07:52:13.80#ibcon#cleared, iclass 26 cls_cnt 0 2006.203.07:52:13.80$vc4f8/valo=5,652.99 2006.203.07:52:13.80#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.203.07:52:13.80#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.203.07:52:13.80#ibcon#ireg 17 cls_cnt 0 2006.203.07:52:13.80#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.203.07:52:13.80#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.203.07:52:13.80#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.203.07:52:13.80#ibcon#enter wrdev, iclass 28, count 0 2006.203.07:52:13.80#ibcon#first serial, iclass 28, count 0 2006.203.07:52:13.80#ibcon#enter sib2, iclass 28, count 0 2006.203.07:52:13.80#ibcon#flushed, iclass 28, count 0 2006.203.07:52:13.80#ibcon#about to write, iclass 28, count 0 2006.203.07:52:13.80#ibcon#wrote, iclass 28, count 0 2006.203.07:52:13.80#ibcon#about to read 3, iclass 28, count 0 2006.203.07:52:13.82#ibcon#read 3, iclass 28, count 0 2006.203.07:52:13.82#ibcon#about to read 4, iclass 28, count 0 2006.203.07:52:13.82#ibcon#read 4, iclass 28, count 0 2006.203.07:52:13.82#ibcon#about to read 5, iclass 28, count 0 2006.203.07:52:13.82#ibcon#read 5, iclass 28, count 0 2006.203.07:52:13.82#ibcon#about to read 6, iclass 28, count 0 2006.203.07:52:13.82#ibcon#read 6, iclass 28, count 0 2006.203.07:52:13.82#ibcon#end of sib2, iclass 28, count 0 2006.203.07:52:13.82#ibcon#*mode == 0, iclass 28, count 0 2006.203.07:52:13.82#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.203.07:52:13.82#ibcon#[26=FRQ=05,652.99\r\n] 2006.203.07:52:13.82#ibcon#*before write, iclass 28, count 0 2006.203.07:52:13.82#ibcon#enter sib2, iclass 28, count 0 2006.203.07:52:13.82#ibcon#flushed, iclass 28, count 0 2006.203.07:52:13.82#ibcon#about to write, iclass 28, count 0 2006.203.07:52:13.82#ibcon#wrote, iclass 28, count 0 2006.203.07:52:13.82#ibcon#about to read 3, iclass 28, count 0 2006.203.07:52:13.86#ibcon#read 3, iclass 28, count 0 2006.203.07:52:13.86#ibcon#about to read 4, iclass 28, count 0 2006.203.07:52:13.86#ibcon#read 4, iclass 28, count 0 2006.203.07:52:13.86#ibcon#about to read 5, iclass 28, count 0 2006.203.07:52:13.86#ibcon#read 5, iclass 28, count 0 2006.203.07:52:13.86#ibcon#about to read 6, iclass 28, count 0 2006.203.07:52:13.86#ibcon#read 6, iclass 28, count 0 2006.203.07:52:13.86#ibcon#end of sib2, iclass 28, count 0 2006.203.07:52:13.86#ibcon#*after write, iclass 28, count 0 2006.203.07:52:13.86#ibcon#*before return 0, iclass 28, count 0 2006.203.07:52:13.86#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.203.07:52:13.86#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.203.07:52:13.86#ibcon#about to clear, iclass 28 cls_cnt 0 2006.203.07:52:13.86#ibcon#cleared, iclass 28 cls_cnt 0 2006.203.07:52:13.86$vc4f8/va=5,7 2006.203.07:52:13.86#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.203.07:52:13.86#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.203.07:52:13.86#ibcon#ireg 11 cls_cnt 2 2006.203.07:52:13.86#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.203.07:52:13.92#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.203.07:52:13.92#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.203.07:52:13.92#ibcon#enter wrdev, iclass 30, count 2 2006.203.07:52:13.92#ibcon#first serial, iclass 30, count 2 2006.203.07:52:13.92#ibcon#enter sib2, iclass 30, count 2 2006.203.07:52:13.92#ibcon#flushed, iclass 30, count 2 2006.203.07:52:13.92#ibcon#about to write, iclass 30, count 2 2006.203.07:52:13.92#ibcon#wrote, iclass 30, count 2 2006.203.07:52:13.92#ibcon#about to read 3, iclass 30, count 2 2006.203.07:52:13.94#ibcon#read 3, iclass 30, count 2 2006.203.07:52:13.94#ibcon#about to read 4, iclass 30, count 2 2006.203.07:52:13.94#ibcon#read 4, iclass 30, count 2 2006.203.07:52:13.94#ibcon#about to read 5, iclass 30, count 2 2006.203.07:52:13.94#ibcon#read 5, iclass 30, count 2 2006.203.07:52:13.94#ibcon#about to read 6, iclass 30, count 2 2006.203.07:52:13.94#ibcon#read 6, iclass 30, count 2 2006.203.07:52:13.94#ibcon#end of sib2, iclass 30, count 2 2006.203.07:52:13.94#ibcon#*mode == 0, iclass 30, count 2 2006.203.07:52:13.94#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.203.07:52:13.94#ibcon#[25=AT05-07\r\n] 2006.203.07:52:13.94#ibcon#*before write, iclass 30, count 2 2006.203.07:52:13.94#ibcon#enter sib2, iclass 30, count 2 2006.203.07:52:13.94#ibcon#flushed, iclass 30, count 2 2006.203.07:52:13.94#ibcon#about to write, iclass 30, count 2 2006.203.07:52:13.94#ibcon#wrote, iclass 30, count 2 2006.203.07:52:13.94#ibcon#about to read 3, iclass 30, count 2 2006.203.07:52:13.97#ibcon#read 3, iclass 30, count 2 2006.203.07:52:13.97#ibcon#about to read 4, iclass 30, count 2 2006.203.07:52:13.97#ibcon#read 4, iclass 30, count 2 2006.203.07:52:13.97#ibcon#about to read 5, iclass 30, count 2 2006.203.07:52:13.97#ibcon#read 5, iclass 30, count 2 2006.203.07:52:13.97#ibcon#about to read 6, iclass 30, count 2 2006.203.07:52:13.97#ibcon#read 6, iclass 30, count 2 2006.203.07:52:13.97#ibcon#end of sib2, iclass 30, count 2 2006.203.07:52:13.97#ibcon#*after write, iclass 30, count 2 2006.203.07:52:13.97#ibcon#*before return 0, iclass 30, count 2 2006.203.07:52:13.97#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.203.07:52:13.97#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.203.07:52:13.97#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.203.07:52:13.97#ibcon#ireg 7 cls_cnt 0 2006.203.07:52:13.97#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.203.07:52:14.09#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.203.07:52:14.09#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.203.07:52:14.09#ibcon#enter wrdev, iclass 30, count 0 2006.203.07:52:14.09#ibcon#first serial, iclass 30, count 0 2006.203.07:52:14.09#ibcon#enter sib2, iclass 30, count 0 2006.203.07:52:14.09#ibcon#flushed, iclass 30, count 0 2006.203.07:52:14.09#ibcon#about to write, iclass 30, count 0 2006.203.07:52:14.09#ibcon#wrote, iclass 30, count 0 2006.203.07:52:14.09#ibcon#about to read 3, iclass 30, count 0 2006.203.07:52:14.11#ibcon#read 3, iclass 30, count 0 2006.203.07:52:14.11#ibcon#about to read 4, iclass 30, count 0 2006.203.07:52:14.11#ibcon#read 4, iclass 30, count 0 2006.203.07:52:14.11#ibcon#about to read 5, iclass 30, count 0 2006.203.07:52:14.11#ibcon#read 5, iclass 30, count 0 2006.203.07:52:14.11#ibcon#about to read 6, iclass 30, count 0 2006.203.07:52:14.11#ibcon#read 6, iclass 30, count 0 2006.203.07:52:14.11#ibcon#end of sib2, iclass 30, count 0 2006.203.07:52:14.11#ibcon#*mode == 0, iclass 30, count 0 2006.203.07:52:14.11#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.203.07:52:14.11#ibcon#[25=USB\r\n] 2006.203.07:52:14.11#ibcon#*before write, iclass 30, count 0 2006.203.07:52:14.11#ibcon#enter sib2, iclass 30, count 0 2006.203.07:52:14.11#ibcon#flushed, iclass 30, count 0 2006.203.07:52:14.11#ibcon#about to write, iclass 30, count 0 2006.203.07:52:14.11#ibcon#wrote, iclass 30, count 0 2006.203.07:52:14.11#ibcon#about to read 3, iclass 30, count 0 2006.203.07:52:14.14#ibcon#read 3, iclass 30, count 0 2006.203.07:52:14.14#ibcon#about to read 4, iclass 30, count 0 2006.203.07:52:14.14#ibcon#read 4, iclass 30, count 0 2006.203.07:52:14.14#ibcon#about to read 5, iclass 30, count 0 2006.203.07:52:14.14#ibcon#read 5, iclass 30, count 0 2006.203.07:52:14.14#ibcon#about to read 6, iclass 30, count 0 2006.203.07:52:14.14#ibcon#read 6, iclass 30, count 0 2006.203.07:52:14.14#ibcon#end of sib2, iclass 30, count 0 2006.203.07:52:14.14#ibcon#*after write, iclass 30, count 0 2006.203.07:52:14.14#ibcon#*before return 0, iclass 30, count 0 2006.203.07:52:14.14#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.203.07:52:14.14#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.203.07:52:14.14#ibcon#about to clear, iclass 30 cls_cnt 0 2006.203.07:52:14.14#ibcon#cleared, iclass 30 cls_cnt 0 2006.203.07:52:14.14$vc4f8/valo=6,772.99 2006.203.07:52:14.14#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.203.07:52:14.14#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.203.07:52:14.14#ibcon#ireg 17 cls_cnt 0 2006.203.07:52:14.14#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.203.07:52:14.14#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.203.07:52:14.14#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.203.07:52:14.14#ibcon#enter wrdev, iclass 32, count 0 2006.203.07:52:14.14#ibcon#first serial, iclass 32, count 0 2006.203.07:52:14.14#ibcon#enter sib2, iclass 32, count 0 2006.203.07:52:14.14#ibcon#flushed, iclass 32, count 0 2006.203.07:52:14.14#ibcon#about to write, iclass 32, count 0 2006.203.07:52:14.14#ibcon#wrote, iclass 32, count 0 2006.203.07:52:14.14#ibcon#about to read 3, iclass 32, count 0 2006.203.07:52:14.16#ibcon#read 3, iclass 32, count 0 2006.203.07:52:14.16#ibcon#about to read 4, iclass 32, count 0 2006.203.07:52:14.16#ibcon#read 4, iclass 32, count 0 2006.203.07:52:14.16#ibcon#about to read 5, iclass 32, count 0 2006.203.07:52:14.16#ibcon#read 5, iclass 32, count 0 2006.203.07:52:14.16#ibcon#about to read 6, iclass 32, count 0 2006.203.07:52:14.16#ibcon#read 6, iclass 32, count 0 2006.203.07:52:14.16#ibcon#end of sib2, iclass 32, count 0 2006.203.07:52:14.16#ibcon#*mode == 0, iclass 32, count 0 2006.203.07:52:14.16#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.203.07:52:14.16#ibcon#[26=FRQ=06,772.99\r\n] 2006.203.07:52:14.16#ibcon#*before write, iclass 32, count 0 2006.203.07:52:14.16#ibcon#enter sib2, iclass 32, count 0 2006.203.07:52:14.16#ibcon#flushed, iclass 32, count 0 2006.203.07:52:14.16#ibcon#about to write, iclass 32, count 0 2006.203.07:52:14.16#ibcon#wrote, iclass 32, count 0 2006.203.07:52:14.16#ibcon#about to read 3, iclass 32, count 0 2006.203.07:52:14.20#ibcon#read 3, iclass 32, count 0 2006.203.07:52:14.20#ibcon#about to read 4, iclass 32, count 0 2006.203.07:52:14.20#ibcon#read 4, iclass 32, count 0 2006.203.07:52:14.20#ibcon#about to read 5, iclass 32, count 0 2006.203.07:52:14.20#ibcon#read 5, iclass 32, count 0 2006.203.07:52:14.20#ibcon#about to read 6, iclass 32, count 0 2006.203.07:52:14.20#ibcon#read 6, iclass 32, count 0 2006.203.07:52:14.20#ibcon#end of sib2, iclass 32, count 0 2006.203.07:52:14.20#ibcon#*after write, iclass 32, count 0 2006.203.07:52:14.20#ibcon#*before return 0, iclass 32, count 0 2006.203.07:52:14.20#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.203.07:52:14.20#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.203.07:52:14.20#ibcon#about to clear, iclass 32 cls_cnt 0 2006.203.07:52:14.20#ibcon#cleared, iclass 32 cls_cnt 0 2006.203.07:52:14.20$vc4f8/va=6,6 2006.203.07:52:14.20#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.203.07:52:14.20#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.203.07:52:14.20#ibcon#ireg 11 cls_cnt 2 2006.203.07:52:14.20#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.203.07:52:14.26#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.203.07:52:14.26#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.203.07:52:14.26#ibcon#enter wrdev, iclass 34, count 2 2006.203.07:52:14.26#ibcon#first serial, iclass 34, count 2 2006.203.07:52:14.26#ibcon#enter sib2, iclass 34, count 2 2006.203.07:52:14.26#ibcon#flushed, iclass 34, count 2 2006.203.07:52:14.26#ibcon#about to write, iclass 34, count 2 2006.203.07:52:14.26#ibcon#wrote, iclass 34, count 2 2006.203.07:52:14.26#ibcon#about to read 3, iclass 34, count 2 2006.203.07:52:14.28#ibcon#read 3, iclass 34, count 2 2006.203.07:52:14.28#ibcon#about to read 4, iclass 34, count 2 2006.203.07:52:14.28#ibcon#read 4, iclass 34, count 2 2006.203.07:52:14.28#ibcon#about to read 5, iclass 34, count 2 2006.203.07:52:14.28#ibcon#read 5, iclass 34, count 2 2006.203.07:52:14.28#ibcon#about to read 6, iclass 34, count 2 2006.203.07:52:14.28#ibcon#read 6, iclass 34, count 2 2006.203.07:52:14.28#ibcon#end of sib2, iclass 34, count 2 2006.203.07:52:14.28#ibcon#*mode == 0, iclass 34, count 2 2006.203.07:52:14.28#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.203.07:52:14.28#ibcon#[25=AT06-06\r\n] 2006.203.07:52:14.28#ibcon#*before write, iclass 34, count 2 2006.203.07:52:14.28#ibcon#enter sib2, iclass 34, count 2 2006.203.07:52:14.28#ibcon#flushed, iclass 34, count 2 2006.203.07:52:14.28#ibcon#about to write, iclass 34, count 2 2006.203.07:52:14.28#ibcon#wrote, iclass 34, count 2 2006.203.07:52:14.28#ibcon#about to read 3, iclass 34, count 2 2006.203.07:52:14.31#ibcon#read 3, iclass 34, count 2 2006.203.07:52:14.31#ibcon#about to read 4, iclass 34, count 2 2006.203.07:52:14.31#ibcon#read 4, iclass 34, count 2 2006.203.07:52:14.31#ibcon#about to read 5, iclass 34, count 2 2006.203.07:52:14.31#ibcon#read 5, iclass 34, count 2 2006.203.07:52:14.31#ibcon#about to read 6, iclass 34, count 2 2006.203.07:52:14.31#ibcon#read 6, iclass 34, count 2 2006.203.07:52:14.31#ibcon#end of sib2, iclass 34, count 2 2006.203.07:52:14.31#ibcon#*after write, iclass 34, count 2 2006.203.07:52:14.31#ibcon#*before return 0, iclass 34, count 2 2006.203.07:52:14.31#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.203.07:52:14.31#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.203.07:52:14.31#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.203.07:52:14.31#ibcon#ireg 7 cls_cnt 0 2006.203.07:52:14.31#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.203.07:52:14.43#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.203.07:52:14.43#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.203.07:52:14.43#ibcon#enter wrdev, iclass 34, count 0 2006.203.07:52:14.43#ibcon#first serial, iclass 34, count 0 2006.203.07:52:14.43#ibcon#enter sib2, iclass 34, count 0 2006.203.07:52:14.43#ibcon#flushed, iclass 34, count 0 2006.203.07:52:14.43#ibcon#about to write, iclass 34, count 0 2006.203.07:52:14.43#ibcon#wrote, iclass 34, count 0 2006.203.07:52:14.43#ibcon#about to read 3, iclass 34, count 0 2006.203.07:52:14.45#ibcon#read 3, iclass 34, count 0 2006.203.07:52:14.45#ibcon#about to read 4, iclass 34, count 0 2006.203.07:52:14.45#ibcon#read 4, iclass 34, count 0 2006.203.07:52:14.45#ibcon#about to read 5, iclass 34, count 0 2006.203.07:52:14.45#ibcon#read 5, iclass 34, count 0 2006.203.07:52:14.45#ibcon#about to read 6, iclass 34, count 0 2006.203.07:52:14.45#ibcon#read 6, iclass 34, count 0 2006.203.07:52:14.45#ibcon#end of sib2, iclass 34, count 0 2006.203.07:52:14.45#ibcon#*mode == 0, iclass 34, count 0 2006.203.07:52:14.45#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.203.07:52:14.45#ibcon#[25=USB\r\n] 2006.203.07:52:14.45#ibcon#*before write, iclass 34, count 0 2006.203.07:52:14.45#ibcon#enter sib2, iclass 34, count 0 2006.203.07:52:14.45#ibcon#flushed, iclass 34, count 0 2006.203.07:52:14.45#ibcon#about to write, iclass 34, count 0 2006.203.07:52:14.45#ibcon#wrote, iclass 34, count 0 2006.203.07:52:14.45#ibcon#about to read 3, iclass 34, count 0 2006.203.07:52:14.48#ibcon#read 3, iclass 34, count 0 2006.203.07:52:14.48#ibcon#about to read 4, iclass 34, count 0 2006.203.07:52:14.48#ibcon#read 4, iclass 34, count 0 2006.203.07:52:14.48#ibcon#about to read 5, iclass 34, count 0 2006.203.07:52:14.48#ibcon#read 5, iclass 34, count 0 2006.203.07:52:14.48#ibcon#about to read 6, iclass 34, count 0 2006.203.07:52:14.48#ibcon#read 6, iclass 34, count 0 2006.203.07:52:14.48#ibcon#end of sib2, iclass 34, count 0 2006.203.07:52:14.48#ibcon#*after write, iclass 34, count 0 2006.203.07:52:14.48#ibcon#*before return 0, iclass 34, count 0 2006.203.07:52:14.48#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.203.07:52:14.48#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.203.07:52:14.48#ibcon#about to clear, iclass 34 cls_cnt 0 2006.203.07:52:14.48#ibcon#cleared, iclass 34 cls_cnt 0 2006.203.07:52:14.48$vc4f8/valo=7,832.99 2006.203.07:52:14.48#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.203.07:52:14.48#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.203.07:52:14.48#ibcon#ireg 17 cls_cnt 0 2006.203.07:52:14.48#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.203.07:52:14.48#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.203.07:52:14.48#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.203.07:52:14.48#ibcon#enter wrdev, iclass 36, count 0 2006.203.07:52:14.48#ibcon#first serial, iclass 36, count 0 2006.203.07:52:14.48#ibcon#enter sib2, iclass 36, count 0 2006.203.07:52:14.48#ibcon#flushed, iclass 36, count 0 2006.203.07:52:14.48#ibcon#about to write, iclass 36, count 0 2006.203.07:52:14.48#ibcon#wrote, iclass 36, count 0 2006.203.07:52:14.48#ibcon#about to read 3, iclass 36, count 0 2006.203.07:52:14.50#ibcon#read 3, iclass 36, count 0 2006.203.07:52:14.50#ibcon#about to read 4, iclass 36, count 0 2006.203.07:52:14.50#ibcon#read 4, iclass 36, count 0 2006.203.07:52:14.50#ibcon#about to read 5, iclass 36, count 0 2006.203.07:52:14.50#ibcon#read 5, iclass 36, count 0 2006.203.07:52:14.50#ibcon#about to read 6, iclass 36, count 0 2006.203.07:52:14.50#ibcon#read 6, iclass 36, count 0 2006.203.07:52:14.50#ibcon#end of sib2, iclass 36, count 0 2006.203.07:52:14.50#ibcon#*mode == 0, iclass 36, count 0 2006.203.07:52:14.50#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.203.07:52:14.50#ibcon#[26=FRQ=07,832.99\r\n] 2006.203.07:52:14.50#ibcon#*before write, iclass 36, count 0 2006.203.07:52:14.50#ibcon#enter sib2, iclass 36, count 0 2006.203.07:52:14.50#ibcon#flushed, iclass 36, count 0 2006.203.07:52:14.50#ibcon#about to write, iclass 36, count 0 2006.203.07:52:14.50#ibcon#wrote, iclass 36, count 0 2006.203.07:52:14.50#ibcon#about to read 3, iclass 36, count 0 2006.203.07:52:14.54#ibcon#read 3, iclass 36, count 0 2006.203.07:52:14.54#ibcon#about to read 4, iclass 36, count 0 2006.203.07:52:14.54#ibcon#read 4, iclass 36, count 0 2006.203.07:52:14.54#ibcon#about to read 5, iclass 36, count 0 2006.203.07:52:14.54#ibcon#read 5, iclass 36, count 0 2006.203.07:52:14.54#ibcon#about to read 6, iclass 36, count 0 2006.203.07:52:14.54#ibcon#read 6, iclass 36, count 0 2006.203.07:52:14.54#ibcon#end of sib2, iclass 36, count 0 2006.203.07:52:14.54#ibcon#*after write, iclass 36, count 0 2006.203.07:52:14.54#ibcon#*before return 0, iclass 36, count 0 2006.203.07:52:14.54#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.203.07:52:14.54#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.203.07:52:14.54#ibcon#about to clear, iclass 36 cls_cnt 0 2006.203.07:52:14.54#ibcon#cleared, iclass 36 cls_cnt 0 2006.203.07:52:14.54$vc4f8/va=7,7 2006.203.07:52:14.54#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.203.07:52:14.54#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.203.07:52:14.54#ibcon#ireg 11 cls_cnt 2 2006.203.07:52:14.54#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.203.07:52:14.60#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.203.07:52:14.60#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.203.07:52:14.60#ibcon#enter wrdev, iclass 38, count 2 2006.203.07:52:14.60#ibcon#first serial, iclass 38, count 2 2006.203.07:52:14.60#ibcon#enter sib2, iclass 38, count 2 2006.203.07:52:14.60#ibcon#flushed, iclass 38, count 2 2006.203.07:52:14.60#ibcon#about to write, iclass 38, count 2 2006.203.07:52:14.60#ibcon#wrote, iclass 38, count 2 2006.203.07:52:14.60#ibcon#about to read 3, iclass 38, count 2 2006.203.07:52:14.62#ibcon#read 3, iclass 38, count 2 2006.203.07:52:14.62#ibcon#about to read 4, iclass 38, count 2 2006.203.07:52:14.62#ibcon#read 4, iclass 38, count 2 2006.203.07:52:14.62#ibcon#about to read 5, iclass 38, count 2 2006.203.07:52:14.62#ibcon#read 5, iclass 38, count 2 2006.203.07:52:14.62#ibcon#about to read 6, iclass 38, count 2 2006.203.07:52:14.62#ibcon#read 6, iclass 38, count 2 2006.203.07:52:14.62#ibcon#end of sib2, iclass 38, count 2 2006.203.07:52:14.62#ibcon#*mode == 0, iclass 38, count 2 2006.203.07:52:14.62#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.203.07:52:14.62#ibcon#[25=AT07-07\r\n] 2006.203.07:52:14.62#ibcon#*before write, iclass 38, count 2 2006.203.07:52:14.62#ibcon#enter sib2, iclass 38, count 2 2006.203.07:52:14.62#ibcon#flushed, iclass 38, count 2 2006.203.07:52:14.62#ibcon#about to write, iclass 38, count 2 2006.203.07:52:14.62#ibcon#wrote, iclass 38, count 2 2006.203.07:52:14.62#ibcon#about to read 3, iclass 38, count 2 2006.203.07:52:14.65#ibcon#read 3, iclass 38, count 2 2006.203.07:52:14.65#ibcon#about to read 4, iclass 38, count 2 2006.203.07:52:14.65#ibcon#read 4, iclass 38, count 2 2006.203.07:52:14.65#ibcon#about to read 5, iclass 38, count 2 2006.203.07:52:14.65#ibcon#read 5, iclass 38, count 2 2006.203.07:52:14.65#ibcon#about to read 6, iclass 38, count 2 2006.203.07:52:14.65#ibcon#read 6, iclass 38, count 2 2006.203.07:52:14.65#ibcon#end of sib2, iclass 38, count 2 2006.203.07:52:14.65#ibcon#*after write, iclass 38, count 2 2006.203.07:52:14.65#ibcon#*before return 0, iclass 38, count 2 2006.203.07:52:14.65#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.203.07:52:14.65#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.203.07:52:14.65#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.203.07:52:14.65#ibcon#ireg 7 cls_cnt 0 2006.203.07:52:14.65#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.203.07:52:14.77#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.203.07:52:14.77#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.203.07:52:14.77#ibcon#enter wrdev, iclass 38, count 0 2006.203.07:52:14.77#ibcon#first serial, iclass 38, count 0 2006.203.07:52:14.77#ibcon#enter sib2, iclass 38, count 0 2006.203.07:52:14.77#ibcon#flushed, iclass 38, count 0 2006.203.07:52:14.77#ibcon#about to write, iclass 38, count 0 2006.203.07:52:14.77#ibcon#wrote, iclass 38, count 0 2006.203.07:52:14.77#ibcon#about to read 3, iclass 38, count 0 2006.203.07:52:14.79#ibcon#read 3, iclass 38, count 0 2006.203.07:52:14.79#ibcon#about to read 4, iclass 38, count 0 2006.203.07:52:14.79#ibcon#read 4, iclass 38, count 0 2006.203.07:52:14.79#ibcon#about to read 5, iclass 38, count 0 2006.203.07:52:14.79#ibcon#read 5, iclass 38, count 0 2006.203.07:52:14.79#ibcon#about to read 6, iclass 38, count 0 2006.203.07:52:14.79#ibcon#read 6, iclass 38, count 0 2006.203.07:52:14.79#ibcon#end of sib2, iclass 38, count 0 2006.203.07:52:14.79#ibcon#*mode == 0, iclass 38, count 0 2006.203.07:52:14.79#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.203.07:52:14.79#ibcon#[25=USB\r\n] 2006.203.07:52:14.79#ibcon#*before write, iclass 38, count 0 2006.203.07:52:14.79#ibcon#enter sib2, iclass 38, count 0 2006.203.07:52:14.79#ibcon#flushed, iclass 38, count 0 2006.203.07:52:14.79#ibcon#about to write, iclass 38, count 0 2006.203.07:52:14.79#ibcon#wrote, iclass 38, count 0 2006.203.07:52:14.79#ibcon#about to read 3, iclass 38, count 0 2006.203.07:52:14.82#ibcon#read 3, iclass 38, count 0 2006.203.07:52:14.82#ibcon#about to read 4, iclass 38, count 0 2006.203.07:52:14.82#ibcon#read 4, iclass 38, count 0 2006.203.07:52:14.82#ibcon#about to read 5, iclass 38, count 0 2006.203.07:52:14.82#ibcon#read 5, iclass 38, count 0 2006.203.07:52:14.82#ibcon#about to read 6, iclass 38, count 0 2006.203.07:52:14.82#ibcon#read 6, iclass 38, count 0 2006.203.07:52:14.82#ibcon#end of sib2, iclass 38, count 0 2006.203.07:52:14.82#ibcon#*after write, iclass 38, count 0 2006.203.07:52:14.82#ibcon#*before return 0, iclass 38, count 0 2006.203.07:52:14.82#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.203.07:52:14.82#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.203.07:52:14.82#ibcon#about to clear, iclass 38 cls_cnt 0 2006.203.07:52:14.82#ibcon#cleared, iclass 38 cls_cnt 0 2006.203.07:52:14.82$vc4f8/valo=8,852.99 2006.203.07:52:14.82#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.203.07:52:14.82#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.203.07:52:14.82#ibcon#ireg 17 cls_cnt 0 2006.203.07:52:14.82#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.203.07:52:14.82#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.203.07:52:14.82#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.203.07:52:14.82#ibcon#enter wrdev, iclass 40, count 0 2006.203.07:52:14.82#ibcon#first serial, iclass 40, count 0 2006.203.07:52:14.82#ibcon#enter sib2, iclass 40, count 0 2006.203.07:52:14.82#ibcon#flushed, iclass 40, count 0 2006.203.07:52:14.82#ibcon#about to write, iclass 40, count 0 2006.203.07:52:14.82#ibcon#wrote, iclass 40, count 0 2006.203.07:52:14.82#ibcon#about to read 3, iclass 40, count 0 2006.203.07:52:14.85#ibcon#read 3, iclass 40, count 0 2006.203.07:52:14.85#ibcon#about to read 4, iclass 40, count 0 2006.203.07:52:14.85#ibcon#read 4, iclass 40, count 0 2006.203.07:52:14.85#ibcon#about to read 5, iclass 40, count 0 2006.203.07:52:14.85#ibcon#read 5, iclass 40, count 0 2006.203.07:52:14.85#ibcon#about to read 6, iclass 40, count 0 2006.203.07:52:14.85#ibcon#read 6, iclass 40, count 0 2006.203.07:52:14.85#ibcon#end of sib2, iclass 40, count 0 2006.203.07:52:14.85#ibcon#*mode == 0, iclass 40, count 0 2006.203.07:52:14.85#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.203.07:52:14.85#ibcon#[26=FRQ=08,852.99\r\n] 2006.203.07:52:14.85#ibcon#*before write, iclass 40, count 0 2006.203.07:52:14.85#ibcon#enter sib2, iclass 40, count 0 2006.203.07:52:14.85#ibcon#flushed, iclass 40, count 0 2006.203.07:52:14.85#ibcon#about to write, iclass 40, count 0 2006.203.07:52:14.85#ibcon#wrote, iclass 40, count 0 2006.203.07:52:14.85#ibcon#about to read 3, iclass 40, count 0 2006.203.07:52:14.89#ibcon#read 3, iclass 40, count 0 2006.203.07:52:14.89#ibcon#about to read 4, iclass 40, count 0 2006.203.07:52:14.89#ibcon#read 4, iclass 40, count 0 2006.203.07:52:14.89#ibcon#about to read 5, iclass 40, count 0 2006.203.07:52:14.89#ibcon#read 5, iclass 40, count 0 2006.203.07:52:14.89#ibcon#about to read 6, iclass 40, count 0 2006.203.07:52:14.89#ibcon#read 6, iclass 40, count 0 2006.203.07:52:14.89#ibcon#end of sib2, iclass 40, count 0 2006.203.07:52:14.89#ibcon#*after write, iclass 40, count 0 2006.203.07:52:14.89#ibcon#*before return 0, iclass 40, count 0 2006.203.07:52:14.89#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.203.07:52:14.89#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.203.07:52:14.89#ibcon#about to clear, iclass 40 cls_cnt 0 2006.203.07:52:14.89#ibcon#cleared, iclass 40 cls_cnt 0 2006.203.07:52:14.89$vc4f8/va=8,6 2006.203.07:52:14.89#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.203.07:52:14.89#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.203.07:52:14.89#ibcon#ireg 11 cls_cnt 2 2006.203.07:52:14.89#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.203.07:52:14.94#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.203.07:52:14.94#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.203.07:52:14.94#ibcon#enter wrdev, iclass 4, count 2 2006.203.07:52:14.94#ibcon#first serial, iclass 4, count 2 2006.203.07:52:14.94#ibcon#enter sib2, iclass 4, count 2 2006.203.07:52:14.94#ibcon#flushed, iclass 4, count 2 2006.203.07:52:14.94#ibcon#about to write, iclass 4, count 2 2006.203.07:52:14.94#ibcon#wrote, iclass 4, count 2 2006.203.07:52:14.94#ibcon#about to read 3, iclass 4, count 2 2006.203.07:52:14.96#ibcon#read 3, iclass 4, count 2 2006.203.07:52:14.96#ibcon#about to read 4, iclass 4, count 2 2006.203.07:52:14.96#ibcon#read 4, iclass 4, count 2 2006.203.07:52:14.96#ibcon#about to read 5, iclass 4, count 2 2006.203.07:52:14.96#ibcon#read 5, iclass 4, count 2 2006.203.07:52:14.96#ibcon#about to read 6, iclass 4, count 2 2006.203.07:52:14.96#ibcon#read 6, iclass 4, count 2 2006.203.07:52:14.96#ibcon#end of sib2, iclass 4, count 2 2006.203.07:52:14.96#ibcon#*mode == 0, iclass 4, count 2 2006.203.07:52:14.96#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.203.07:52:14.96#ibcon#[25=AT08-06\r\n] 2006.203.07:52:14.96#ibcon#*before write, iclass 4, count 2 2006.203.07:52:14.96#ibcon#enter sib2, iclass 4, count 2 2006.203.07:52:14.96#ibcon#flushed, iclass 4, count 2 2006.203.07:52:14.96#ibcon#about to write, iclass 4, count 2 2006.203.07:52:14.96#ibcon#wrote, iclass 4, count 2 2006.203.07:52:14.96#ibcon#about to read 3, iclass 4, count 2 2006.203.07:52:14.99#ibcon#read 3, iclass 4, count 2 2006.203.07:52:14.99#ibcon#about to read 4, iclass 4, count 2 2006.203.07:52:14.99#ibcon#read 4, iclass 4, count 2 2006.203.07:52:14.99#ibcon#about to read 5, iclass 4, count 2 2006.203.07:52:14.99#ibcon#read 5, iclass 4, count 2 2006.203.07:52:14.99#ibcon#about to read 6, iclass 4, count 2 2006.203.07:52:14.99#ibcon#read 6, iclass 4, count 2 2006.203.07:52:14.99#ibcon#end of sib2, iclass 4, count 2 2006.203.07:52:14.99#ibcon#*after write, iclass 4, count 2 2006.203.07:52:14.99#ibcon#*before return 0, iclass 4, count 2 2006.203.07:52:14.99#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.203.07:52:14.99#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.203.07:52:14.99#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.203.07:52:14.99#ibcon#ireg 7 cls_cnt 0 2006.203.07:52:14.99#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.203.07:52:15.11#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.203.07:52:15.11#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.203.07:52:15.11#ibcon#enter wrdev, iclass 4, count 0 2006.203.07:52:15.11#ibcon#first serial, iclass 4, count 0 2006.203.07:52:15.11#ibcon#enter sib2, iclass 4, count 0 2006.203.07:52:15.11#ibcon#flushed, iclass 4, count 0 2006.203.07:52:15.11#ibcon#about to write, iclass 4, count 0 2006.203.07:52:15.11#ibcon#wrote, iclass 4, count 0 2006.203.07:52:15.11#ibcon#about to read 3, iclass 4, count 0 2006.203.07:52:15.13#ibcon#read 3, iclass 4, count 0 2006.203.07:52:15.13#ibcon#about to read 4, iclass 4, count 0 2006.203.07:52:15.13#ibcon#read 4, iclass 4, count 0 2006.203.07:52:15.13#ibcon#about to read 5, iclass 4, count 0 2006.203.07:52:15.13#ibcon#read 5, iclass 4, count 0 2006.203.07:52:15.13#ibcon#about to read 6, iclass 4, count 0 2006.203.07:52:15.13#ibcon#read 6, iclass 4, count 0 2006.203.07:52:15.13#ibcon#end of sib2, iclass 4, count 0 2006.203.07:52:15.13#ibcon#*mode == 0, iclass 4, count 0 2006.203.07:52:15.13#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.203.07:52:15.13#ibcon#[25=USB\r\n] 2006.203.07:52:15.13#ibcon#*before write, iclass 4, count 0 2006.203.07:52:15.13#ibcon#enter sib2, iclass 4, count 0 2006.203.07:52:15.13#ibcon#flushed, iclass 4, count 0 2006.203.07:52:15.13#ibcon#about to write, iclass 4, count 0 2006.203.07:52:15.13#ibcon#wrote, iclass 4, count 0 2006.203.07:52:15.13#ibcon#about to read 3, iclass 4, count 0 2006.203.07:52:15.16#ibcon#read 3, iclass 4, count 0 2006.203.07:52:15.16#ibcon#about to read 4, iclass 4, count 0 2006.203.07:52:15.16#ibcon#read 4, iclass 4, count 0 2006.203.07:52:15.16#ibcon#about to read 5, iclass 4, count 0 2006.203.07:52:15.16#ibcon#read 5, iclass 4, count 0 2006.203.07:52:15.16#ibcon#about to read 6, iclass 4, count 0 2006.203.07:52:15.16#ibcon#read 6, iclass 4, count 0 2006.203.07:52:15.16#ibcon#end of sib2, iclass 4, count 0 2006.203.07:52:15.16#ibcon#*after write, iclass 4, count 0 2006.203.07:52:15.16#ibcon#*before return 0, iclass 4, count 0 2006.203.07:52:15.16#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.203.07:52:15.16#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.203.07:52:15.16#ibcon#about to clear, iclass 4 cls_cnt 0 2006.203.07:52:15.16#ibcon#cleared, iclass 4 cls_cnt 0 2006.203.07:52:15.16$vc4f8/vblo=1,632.99 2006.203.07:52:15.16#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.203.07:52:15.16#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.203.07:52:15.16#ibcon#ireg 17 cls_cnt 0 2006.203.07:52:15.16#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.203.07:52:15.16#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.203.07:52:15.16#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.203.07:52:15.16#ibcon#enter wrdev, iclass 6, count 0 2006.203.07:52:15.16#ibcon#first serial, iclass 6, count 0 2006.203.07:52:15.16#ibcon#enter sib2, iclass 6, count 0 2006.203.07:52:15.16#ibcon#flushed, iclass 6, count 0 2006.203.07:52:15.16#ibcon#about to write, iclass 6, count 0 2006.203.07:52:15.16#ibcon#wrote, iclass 6, count 0 2006.203.07:52:15.16#ibcon#about to read 3, iclass 6, count 0 2006.203.07:52:15.18#ibcon#read 3, iclass 6, count 0 2006.203.07:52:15.18#ibcon#about to read 4, iclass 6, count 0 2006.203.07:52:15.18#ibcon#read 4, iclass 6, count 0 2006.203.07:52:15.18#ibcon#about to read 5, iclass 6, count 0 2006.203.07:52:15.18#ibcon#read 5, iclass 6, count 0 2006.203.07:52:15.18#ibcon#about to read 6, iclass 6, count 0 2006.203.07:52:15.18#ibcon#read 6, iclass 6, count 0 2006.203.07:52:15.18#ibcon#end of sib2, iclass 6, count 0 2006.203.07:52:15.18#ibcon#*mode == 0, iclass 6, count 0 2006.203.07:52:15.18#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.203.07:52:15.18#ibcon#[28=FRQ=01,632.99\r\n] 2006.203.07:52:15.18#ibcon#*before write, iclass 6, count 0 2006.203.07:52:15.18#ibcon#enter sib2, iclass 6, count 0 2006.203.07:52:15.18#ibcon#flushed, iclass 6, count 0 2006.203.07:52:15.18#ibcon#about to write, iclass 6, count 0 2006.203.07:52:15.18#ibcon#wrote, iclass 6, count 0 2006.203.07:52:15.18#ibcon#about to read 3, iclass 6, count 0 2006.203.07:52:15.22#ibcon#read 3, iclass 6, count 0 2006.203.07:52:15.22#ibcon#about to read 4, iclass 6, count 0 2006.203.07:52:15.22#ibcon#read 4, iclass 6, count 0 2006.203.07:52:15.22#ibcon#about to read 5, iclass 6, count 0 2006.203.07:52:15.22#ibcon#read 5, iclass 6, count 0 2006.203.07:52:15.22#ibcon#about to read 6, iclass 6, count 0 2006.203.07:52:15.22#ibcon#read 6, iclass 6, count 0 2006.203.07:52:15.22#ibcon#end of sib2, iclass 6, count 0 2006.203.07:52:15.22#ibcon#*after write, iclass 6, count 0 2006.203.07:52:15.22#ibcon#*before return 0, iclass 6, count 0 2006.203.07:52:15.22#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.203.07:52:15.22#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.203.07:52:15.22#ibcon#about to clear, iclass 6 cls_cnt 0 2006.203.07:52:15.22#ibcon#cleared, iclass 6 cls_cnt 0 2006.203.07:52:15.22$vc4f8/vb=1,4 2006.203.07:52:15.22#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.203.07:52:15.22#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.203.07:52:15.22#ibcon#ireg 11 cls_cnt 2 2006.203.07:52:15.22#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.203.07:52:15.22#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.203.07:52:15.22#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.203.07:52:15.22#ibcon#enter wrdev, iclass 10, count 2 2006.203.07:52:15.22#ibcon#first serial, iclass 10, count 2 2006.203.07:52:15.22#ibcon#enter sib2, iclass 10, count 2 2006.203.07:52:15.22#ibcon#flushed, iclass 10, count 2 2006.203.07:52:15.22#ibcon#about to write, iclass 10, count 2 2006.203.07:52:15.22#ibcon#wrote, iclass 10, count 2 2006.203.07:52:15.22#ibcon#about to read 3, iclass 10, count 2 2006.203.07:52:15.24#ibcon#read 3, iclass 10, count 2 2006.203.07:52:15.24#ibcon#about to read 4, iclass 10, count 2 2006.203.07:52:15.24#ibcon#read 4, iclass 10, count 2 2006.203.07:52:15.24#ibcon#about to read 5, iclass 10, count 2 2006.203.07:52:15.24#ibcon#read 5, iclass 10, count 2 2006.203.07:52:15.24#ibcon#about to read 6, iclass 10, count 2 2006.203.07:52:15.24#ibcon#read 6, iclass 10, count 2 2006.203.07:52:15.24#ibcon#end of sib2, iclass 10, count 2 2006.203.07:52:15.24#ibcon#*mode == 0, iclass 10, count 2 2006.203.07:52:15.24#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.203.07:52:15.24#ibcon#[27=AT01-04\r\n] 2006.203.07:52:15.24#ibcon#*before write, iclass 10, count 2 2006.203.07:52:15.24#ibcon#enter sib2, iclass 10, count 2 2006.203.07:52:15.24#ibcon#flushed, iclass 10, count 2 2006.203.07:52:15.24#ibcon#about to write, iclass 10, count 2 2006.203.07:52:15.24#ibcon#wrote, iclass 10, count 2 2006.203.07:52:15.24#ibcon#about to read 3, iclass 10, count 2 2006.203.07:52:15.27#ibcon#read 3, iclass 10, count 2 2006.203.07:52:15.27#ibcon#about to read 4, iclass 10, count 2 2006.203.07:52:15.27#ibcon#read 4, iclass 10, count 2 2006.203.07:52:15.27#ibcon#about to read 5, iclass 10, count 2 2006.203.07:52:15.27#ibcon#read 5, iclass 10, count 2 2006.203.07:52:15.27#ibcon#about to read 6, iclass 10, count 2 2006.203.07:52:15.27#ibcon#read 6, iclass 10, count 2 2006.203.07:52:15.27#ibcon#end of sib2, iclass 10, count 2 2006.203.07:52:15.27#ibcon#*after write, iclass 10, count 2 2006.203.07:52:15.27#ibcon#*before return 0, iclass 10, count 2 2006.203.07:52:15.27#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.203.07:52:15.27#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.203.07:52:15.27#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.203.07:52:15.27#ibcon#ireg 7 cls_cnt 0 2006.203.07:52:15.27#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.203.07:52:15.39#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.203.07:52:15.39#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.203.07:52:15.39#ibcon#enter wrdev, iclass 10, count 0 2006.203.07:52:15.39#ibcon#first serial, iclass 10, count 0 2006.203.07:52:15.39#ibcon#enter sib2, iclass 10, count 0 2006.203.07:52:15.39#ibcon#flushed, iclass 10, count 0 2006.203.07:52:15.39#ibcon#about to write, iclass 10, count 0 2006.203.07:52:15.39#ibcon#wrote, iclass 10, count 0 2006.203.07:52:15.39#ibcon#about to read 3, iclass 10, count 0 2006.203.07:52:15.41#ibcon#read 3, iclass 10, count 0 2006.203.07:52:15.41#ibcon#about to read 4, iclass 10, count 0 2006.203.07:52:15.41#ibcon#read 4, iclass 10, count 0 2006.203.07:52:15.41#ibcon#about to read 5, iclass 10, count 0 2006.203.07:52:15.41#ibcon#read 5, iclass 10, count 0 2006.203.07:52:15.41#ibcon#about to read 6, iclass 10, count 0 2006.203.07:52:15.41#ibcon#read 6, iclass 10, count 0 2006.203.07:52:15.41#ibcon#end of sib2, iclass 10, count 0 2006.203.07:52:15.41#ibcon#*mode == 0, iclass 10, count 0 2006.203.07:52:15.41#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.203.07:52:15.41#ibcon#[27=USB\r\n] 2006.203.07:52:15.41#ibcon#*before write, iclass 10, count 0 2006.203.07:52:15.41#ibcon#enter sib2, iclass 10, count 0 2006.203.07:52:15.41#ibcon#flushed, iclass 10, count 0 2006.203.07:52:15.41#ibcon#about to write, iclass 10, count 0 2006.203.07:52:15.41#ibcon#wrote, iclass 10, count 0 2006.203.07:52:15.41#ibcon#about to read 3, iclass 10, count 0 2006.203.07:52:15.44#ibcon#read 3, iclass 10, count 0 2006.203.07:52:15.44#ibcon#about to read 4, iclass 10, count 0 2006.203.07:52:15.44#ibcon#read 4, iclass 10, count 0 2006.203.07:52:15.44#ibcon#about to read 5, iclass 10, count 0 2006.203.07:52:15.44#ibcon#read 5, iclass 10, count 0 2006.203.07:52:15.44#ibcon#about to read 6, iclass 10, count 0 2006.203.07:52:15.44#ibcon#read 6, iclass 10, count 0 2006.203.07:52:15.44#ibcon#end of sib2, iclass 10, count 0 2006.203.07:52:15.44#ibcon#*after write, iclass 10, count 0 2006.203.07:52:15.44#ibcon#*before return 0, iclass 10, count 0 2006.203.07:52:15.44#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.203.07:52:15.44#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.203.07:52:15.44#ibcon#about to clear, iclass 10 cls_cnt 0 2006.203.07:52:15.44#ibcon#cleared, iclass 10 cls_cnt 0 2006.203.07:52:15.44$vc4f8/vblo=2,640.99 2006.203.07:52:15.44#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.203.07:52:15.44#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.203.07:52:15.44#ibcon#ireg 17 cls_cnt 0 2006.203.07:52:15.44#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.203.07:52:15.44#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.203.07:52:15.44#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.203.07:52:15.44#ibcon#enter wrdev, iclass 12, count 0 2006.203.07:52:15.44#ibcon#first serial, iclass 12, count 0 2006.203.07:52:15.44#ibcon#enter sib2, iclass 12, count 0 2006.203.07:52:15.44#ibcon#flushed, iclass 12, count 0 2006.203.07:52:15.44#ibcon#about to write, iclass 12, count 0 2006.203.07:52:15.44#ibcon#wrote, iclass 12, count 0 2006.203.07:52:15.44#ibcon#about to read 3, iclass 12, count 0 2006.203.07:52:15.46#ibcon#read 3, iclass 12, count 0 2006.203.07:52:15.46#ibcon#about to read 4, iclass 12, count 0 2006.203.07:52:15.46#ibcon#read 4, iclass 12, count 0 2006.203.07:52:15.46#ibcon#about to read 5, iclass 12, count 0 2006.203.07:52:15.46#ibcon#read 5, iclass 12, count 0 2006.203.07:52:15.46#ibcon#about to read 6, iclass 12, count 0 2006.203.07:52:15.46#ibcon#read 6, iclass 12, count 0 2006.203.07:52:15.46#ibcon#end of sib2, iclass 12, count 0 2006.203.07:52:15.46#ibcon#*mode == 0, iclass 12, count 0 2006.203.07:52:15.46#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.203.07:52:15.46#ibcon#[28=FRQ=02,640.99\r\n] 2006.203.07:52:15.46#ibcon#*before write, iclass 12, count 0 2006.203.07:52:15.46#ibcon#enter sib2, iclass 12, count 0 2006.203.07:52:15.46#ibcon#flushed, iclass 12, count 0 2006.203.07:52:15.46#ibcon#about to write, iclass 12, count 0 2006.203.07:52:15.46#ibcon#wrote, iclass 12, count 0 2006.203.07:52:15.46#ibcon#about to read 3, iclass 12, count 0 2006.203.07:52:15.50#ibcon#read 3, iclass 12, count 0 2006.203.07:52:15.50#ibcon#about to read 4, iclass 12, count 0 2006.203.07:52:15.50#ibcon#read 4, iclass 12, count 0 2006.203.07:52:15.50#ibcon#about to read 5, iclass 12, count 0 2006.203.07:52:15.50#ibcon#read 5, iclass 12, count 0 2006.203.07:52:15.50#ibcon#about to read 6, iclass 12, count 0 2006.203.07:52:15.50#ibcon#read 6, iclass 12, count 0 2006.203.07:52:15.50#ibcon#end of sib2, iclass 12, count 0 2006.203.07:52:15.50#ibcon#*after write, iclass 12, count 0 2006.203.07:52:15.50#ibcon#*before return 0, iclass 12, count 0 2006.203.07:52:15.50#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.203.07:52:15.50#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.203.07:52:15.50#ibcon#about to clear, iclass 12 cls_cnt 0 2006.203.07:52:15.50#ibcon#cleared, iclass 12 cls_cnt 0 2006.203.07:52:15.50$vc4f8/vb=2,4 2006.203.07:52:15.50#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.203.07:52:15.50#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.203.07:52:15.50#ibcon#ireg 11 cls_cnt 2 2006.203.07:52:15.50#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.203.07:52:15.56#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.203.07:52:15.56#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.203.07:52:15.56#ibcon#enter wrdev, iclass 14, count 2 2006.203.07:52:15.56#ibcon#first serial, iclass 14, count 2 2006.203.07:52:15.56#ibcon#enter sib2, iclass 14, count 2 2006.203.07:52:15.56#ibcon#flushed, iclass 14, count 2 2006.203.07:52:15.56#ibcon#about to write, iclass 14, count 2 2006.203.07:52:15.56#ibcon#wrote, iclass 14, count 2 2006.203.07:52:15.56#ibcon#about to read 3, iclass 14, count 2 2006.203.07:52:15.58#ibcon#read 3, iclass 14, count 2 2006.203.07:52:15.58#ibcon#about to read 4, iclass 14, count 2 2006.203.07:52:15.58#ibcon#read 4, iclass 14, count 2 2006.203.07:52:15.58#ibcon#about to read 5, iclass 14, count 2 2006.203.07:52:15.58#ibcon#read 5, iclass 14, count 2 2006.203.07:52:15.58#ibcon#about to read 6, iclass 14, count 2 2006.203.07:52:15.58#ibcon#read 6, iclass 14, count 2 2006.203.07:52:15.58#ibcon#end of sib2, iclass 14, count 2 2006.203.07:52:15.58#ibcon#*mode == 0, iclass 14, count 2 2006.203.07:52:15.58#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.203.07:52:15.58#ibcon#[27=AT02-04\r\n] 2006.203.07:52:15.58#ibcon#*before write, iclass 14, count 2 2006.203.07:52:15.58#ibcon#enter sib2, iclass 14, count 2 2006.203.07:52:15.58#ibcon#flushed, iclass 14, count 2 2006.203.07:52:15.58#ibcon#about to write, iclass 14, count 2 2006.203.07:52:15.58#ibcon#wrote, iclass 14, count 2 2006.203.07:52:15.58#ibcon#about to read 3, iclass 14, count 2 2006.203.07:52:15.61#ibcon#read 3, iclass 14, count 2 2006.203.07:52:15.61#ibcon#about to read 4, iclass 14, count 2 2006.203.07:52:15.61#ibcon#read 4, iclass 14, count 2 2006.203.07:52:15.61#ibcon#about to read 5, iclass 14, count 2 2006.203.07:52:15.61#ibcon#read 5, iclass 14, count 2 2006.203.07:52:15.61#ibcon#about to read 6, iclass 14, count 2 2006.203.07:52:15.61#ibcon#read 6, iclass 14, count 2 2006.203.07:52:15.61#ibcon#end of sib2, iclass 14, count 2 2006.203.07:52:15.61#ibcon#*after write, iclass 14, count 2 2006.203.07:52:15.61#ibcon#*before return 0, iclass 14, count 2 2006.203.07:52:15.61#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.203.07:52:15.61#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.203.07:52:15.61#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.203.07:52:15.61#ibcon#ireg 7 cls_cnt 0 2006.203.07:52:15.61#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.203.07:52:15.73#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.203.07:52:15.73#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.203.07:52:15.73#ibcon#enter wrdev, iclass 14, count 0 2006.203.07:52:15.73#ibcon#first serial, iclass 14, count 0 2006.203.07:52:15.73#ibcon#enter sib2, iclass 14, count 0 2006.203.07:52:15.73#ibcon#flushed, iclass 14, count 0 2006.203.07:52:15.73#ibcon#about to write, iclass 14, count 0 2006.203.07:52:15.73#ibcon#wrote, iclass 14, count 0 2006.203.07:52:15.73#ibcon#about to read 3, iclass 14, count 0 2006.203.07:52:15.75#ibcon#read 3, iclass 14, count 0 2006.203.07:52:15.75#ibcon#about to read 4, iclass 14, count 0 2006.203.07:52:15.75#ibcon#read 4, iclass 14, count 0 2006.203.07:52:15.75#ibcon#about to read 5, iclass 14, count 0 2006.203.07:52:15.75#ibcon#read 5, iclass 14, count 0 2006.203.07:52:15.75#ibcon#about to read 6, iclass 14, count 0 2006.203.07:52:15.75#ibcon#read 6, iclass 14, count 0 2006.203.07:52:15.75#ibcon#end of sib2, iclass 14, count 0 2006.203.07:52:15.75#ibcon#*mode == 0, iclass 14, count 0 2006.203.07:52:15.75#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.203.07:52:15.75#ibcon#[27=USB\r\n] 2006.203.07:52:15.75#ibcon#*before write, iclass 14, count 0 2006.203.07:52:15.75#ibcon#enter sib2, iclass 14, count 0 2006.203.07:52:15.75#ibcon#flushed, iclass 14, count 0 2006.203.07:52:15.75#ibcon#about to write, iclass 14, count 0 2006.203.07:52:15.75#ibcon#wrote, iclass 14, count 0 2006.203.07:52:15.75#ibcon#about to read 3, iclass 14, count 0 2006.203.07:52:15.78#ibcon#read 3, iclass 14, count 0 2006.203.07:52:15.78#ibcon#about to read 4, iclass 14, count 0 2006.203.07:52:15.78#ibcon#read 4, iclass 14, count 0 2006.203.07:52:15.78#ibcon#about to read 5, iclass 14, count 0 2006.203.07:52:15.78#ibcon#read 5, iclass 14, count 0 2006.203.07:52:15.78#ibcon#about to read 6, iclass 14, count 0 2006.203.07:52:15.78#ibcon#read 6, iclass 14, count 0 2006.203.07:52:15.78#ibcon#end of sib2, iclass 14, count 0 2006.203.07:52:15.78#ibcon#*after write, iclass 14, count 0 2006.203.07:52:15.78#ibcon#*before return 0, iclass 14, count 0 2006.203.07:52:15.78#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.203.07:52:15.78#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.203.07:52:15.78#ibcon#about to clear, iclass 14 cls_cnt 0 2006.203.07:52:15.78#ibcon#cleared, iclass 14 cls_cnt 0 2006.203.07:52:15.78$vc4f8/vblo=3,656.99 2006.203.07:52:15.78#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.203.07:52:15.78#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.203.07:52:15.78#ibcon#ireg 17 cls_cnt 0 2006.203.07:52:15.78#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.203.07:52:15.78#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.203.07:52:15.78#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.203.07:52:15.78#ibcon#enter wrdev, iclass 16, count 0 2006.203.07:52:15.78#ibcon#first serial, iclass 16, count 0 2006.203.07:52:15.78#ibcon#enter sib2, iclass 16, count 0 2006.203.07:52:15.78#ibcon#flushed, iclass 16, count 0 2006.203.07:52:15.78#ibcon#about to write, iclass 16, count 0 2006.203.07:52:15.78#ibcon#wrote, iclass 16, count 0 2006.203.07:52:15.78#ibcon#about to read 3, iclass 16, count 0 2006.203.07:52:15.80#ibcon#read 3, iclass 16, count 0 2006.203.07:52:15.80#ibcon#about to read 4, iclass 16, count 0 2006.203.07:52:15.80#ibcon#read 4, iclass 16, count 0 2006.203.07:52:15.80#ibcon#about to read 5, iclass 16, count 0 2006.203.07:52:15.80#ibcon#read 5, iclass 16, count 0 2006.203.07:52:15.80#ibcon#about to read 6, iclass 16, count 0 2006.203.07:52:15.80#ibcon#read 6, iclass 16, count 0 2006.203.07:52:15.80#ibcon#end of sib2, iclass 16, count 0 2006.203.07:52:15.80#ibcon#*mode == 0, iclass 16, count 0 2006.203.07:52:15.80#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.203.07:52:15.80#ibcon#[28=FRQ=03,656.99\r\n] 2006.203.07:52:15.80#ibcon#*before write, iclass 16, count 0 2006.203.07:52:15.80#ibcon#enter sib2, iclass 16, count 0 2006.203.07:52:15.80#ibcon#flushed, iclass 16, count 0 2006.203.07:52:15.80#ibcon#about to write, iclass 16, count 0 2006.203.07:52:15.80#ibcon#wrote, iclass 16, count 0 2006.203.07:52:15.80#ibcon#about to read 3, iclass 16, count 0 2006.203.07:52:15.84#ibcon#read 3, iclass 16, count 0 2006.203.07:52:15.84#ibcon#about to read 4, iclass 16, count 0 2006.203.07:52:15.84#ibcon#read 4, iclass 16, count 0 2006.203.07:52:15.84#ibcon#about to read 5, iclass 16, count 0 2006.203.07:52:15.84#ibcon#read 5, iclass 16, count 0 2006.203.07:52:15.84#ibcon#about to read 6, iclass 16, count 0 2006.203.07:52:15.84#ibcon#read 6, iclass 16, count 0 2006.203.07:52:15.84#ibcon#end of sib2, iclass 16, count 0 2006.203.07:52:15.84#ibcon#*after write, iclass 16, count 0 2006.203.07:52:15.84#ibcon#*before return 0, iclass 16, count 0 2006.203.07:52:15.84#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.203.07:52:15.84#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.203.07:52:15.84#ibcon#about to clear, iclass 16 cls_cnt 0 2006.203.07:52:15.84#ibcon#cleared, iclass 16 cls_cnt 0 2006.203.07:52:15.84$vc4f8/vb=3,4 2006.203.07:52:15.84#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.203.07:52:15.84#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.203.07:52:15.84#ibcon#ireg 11 cls_cnt 2 2006.203.07:52:15.84#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.203.07:52:15.90#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.203.07:52:15.90#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.203.07:52:15.90#ibcon#enter wrdev, iclass 18, count 2 2006.203.07:52:15.90#ibcon#first serial, iclass 18, count 2 2006.203.07:52:15.90#ibcon#enter sib2, iclass 18, count 2 2006.203.07:52:15.90#ibcon#flushed, iclass 18, count 2 2006.203.07:52:15.90#ibcon#about to write, iclass 18, count 2 2006.203.07:52:15.90#ibcon#wrote, iclass 18, count 2 2006.203.07:52:15.90#ibcon#about to read 3, iclass 18, count 2 2006.203.07:52:15.92#ibcon#read 3, iclass 18, count 2 2006.203.07:52:15.92#ibcon#about to read 4, iclass 18, count 2 2006.203.07:52:15.92#ibcon#read 4, iclass 18, count 2 2006.203.07:52:15.92#ibcon#about to read 5, iclass 18, count 2 2006.203.07:52:15.92#ibcon#read 5, iclass 18, count 2 2006.203.07:52:15.92#ibcon#about to read 6, iclass 18, count 2 2006.203.07:52:15.92#ibcon#read 6, iclass 18, count 2 2006.203.07:52:15.92#ibcon#end of sib2, iclass 18, count 2 2006.203.07:52:15.92#ibcon#*mode == 0, iclass 18, count 2 2006.203.07:52:15.92#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.203.07:52:15.92#ibcon#[27=AT03-04\r\n] 2006.203.07:52:15.92#ibcon#*before write, iclass 18, count 2 2006.203.07:52:15.92#ibcon#enter sib2, iclass 18, count 2 2006.203.07:52:15.92#ibcon#flushed, iclass 18, count 2 2006.203.07:52:15.92#ibcon#about to write, iclass 18, count 2 2006.203.07:52:15.92#ibcon#wrote, iclass 18, count 2 2006.203.07:52:15.92#ibcon#about to read 3, iclass 18, count 2 2006.203.07:52:15.95#ibcon#read 3, iclass 18, count 2 2006.203.07:52:15.95#ibcon#about to read 4, iclass 18, count 2 2006.203.07:52:15.95#ibcon#read 4, iclass 18, count 2 2006.203.07:52:15.95#ibcon#about to read 5, iclass 18, count 2 2006.203.07:52:15.95#ibcon#read 5, iclass 18, count 2 2006.203.07:52:15.95#ibcon#about to read 6, iclass 18, count 2 2006.203.07:52:15.95#ibcon#read 6, iclass 18, count 2 2006.203.07:52:15.95#ibcon#end of sib2, iclass 18, count 2 2006.203.07:52:15.95#ibcon#*after write, iclass 18, count 2 2006.203.07:52:15.95#ibcon#*before return 0, iclass 18, count 2 2006.203.07:52:15.95#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.203.07:52:15.95#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.203.07:52:15.95#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.203.07:52:15.95#ibcon#ireg 7 cls_cnt 0 2006.203.07:52:15.95#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.203.07:52:16.07#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.203.07:52:16.07#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.203.07:52:16.07#ibcon#enter wrdev, iclass 18, count 0 2006.203.07:52:16.07#ibcon#first serial, iclass 18, count 0 2006.203.07:52:16.07#ibcon#enter sib2, iclass 18, count 0 2006.203.07:52:16.07#ibcon#flushed, iclass 18, count 0 2006.203.07:52:16.07#ibcon#about to write, iclass 18, count 0 2006.203.07:52:16.07#ibcon#wrote, iclass 18, count 0 2006.203.07:52:16.07#ibcon#about to read 3, iclass 18, count 0 2006.203.07:52:16.09#ibcon#read 3, iclass 18, count 0 2006.203.07:52:16.09#ibcon#about to read 4, iclass 18, count 0 2006.203.07:52:16.09#ibcon#read 4, iclass 18, count 0 2006.203.07:52:16.09#ibcon#about to read 5, iclass 18, count 0 2006.203.07:52:16.09#ibcon#read 5, iclass 18, count 0 2006.203.07:52:16.09#ibcon#about to read 6, iclass 18, count 0 2006.203.07:52:16.09#ibcon#read 6, iclass 18, count 0 2006.203.07:52:16.09#ibcon#end of sib2, iclass 18, count 0 2006.203.07:52:16.09#ibcon#*mode == 0, iclass 18, count 0 2006.203.07:52:16.09#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.203.07:52:16.09#ibcon#[27=USB\r\n] 2006.203.07:52:16.09#ibcon#*before write, iclass 18, count 0 2006.203.07:52:16.09#ibcon#enter sib2, iclass 18, count 0 2006.203.07:52:16.09#ibcon#flushed, iclass 18, count 0 2006.203.07:52:16.09#ibcon#about to write, iclass 18, count 0 2006.203.07:52:16.09#ibcon#wrote, iclass 18, count 0 2006.203.07:52:16.09#ibcon#about to read 3, iclass 18, count 0 2006.203.07:52:16.12#ibcon#read 3, iclass 18, count 0 2006.203.07:52:16.12#ibcon#about to read 4, iclass 18, count 0 2006.203.07:52:16.12#ibcon#read 4, iclass 18, count 0 2006.203.07:52:16.12#ibcon#about to read 5, iclass 18, count 0 2006.203.07:52:16.12#ibcon#read 5, iclass 18, count 0 2006.203.07:52:16.12#ibcon#about to read 6, iclass 18, count 0 2006.203.07:52:16.12#ibcon#read 6, iclass 18, count 0 2006.203.07:52:16.12#ibcon#end of sib2, iclass 18, count 0 2006.203.07:52:16.12#ibcon#*after write, iclass 18, count 0 2006.203.07:52:16.12#ibcon#*before return 0, iclass 18, count 0 2006.203.07:52:16.12#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.203.07:52:16.12#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.203.07:52:16.12#ibcon#about to clear, iclass 18 cls_cnt 0 2006.203.07:52:16.12#ibcon#cleared, iclass 18 cls_cnt 0 2006.203.07:52:16.12$vc4f8/vblo=4,712.99 2006.203.07:52:16.12#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.203.07:52:16.12#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.203.07:52:16.12#ibcon#ireg 17 cls_cnt 0 2006.203.07:52:16.12#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.203.07:52:16.12#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.203.07:52:16.12#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.203.07:52:16.12#ibcon#enter wrdev, iclass 20, count 0 2006.203.07:52:16.12#ibcon#first serial, iclass 20, count 0 2006.203.07:52:16.12#ibcon#enter sib2, iclass 20, count 0 2006.203.07:52:16.12#ibcon#flushed, iclass 20, count 0 2006.203.07:52:16.12#ibcon#about to write, iclass 20, count 0 2006.203.07:52:16.12#ibcon#wrote, iclass 20, count 0 2006.203.07:52:16.12#ibcon#about to read 3, iclass 20, count 0 2006.203.07:52:16.14#ibcon#read 3, iclass 20, count 0 2006.203.07:52:16.14#ibcon#about to read 4, iclass 20, count 0 2006.203.07:52:16.14#ibcon#read 4, iclass 20, count 0 2006.203.07:52:16.14#ibcon#about to read 5, iclass 20, count 0 2006.203.07:52:16.14#ibcon#read 5, iclass 20, count 0 2006.203.07:52:16.14#ibcon#about to read 6, iclass 20, count 0 2006.203.07:52:16.14#ibcon#read 6, iclass 20, count 0 2006.203.07:52:16.14#ibcon#end of sib2, iclass 20, count 0 2006.203.07:52:16.14#ibcon#*mode == 0, iclass 20, count 0 2006.203.07:52:16.14#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.203.07:52:16.14#ibcon#[28=FRQ=04,712.99\r\n] 2006.203.07:52:16.14#ibcon#*before write, iclass 20, count 0 2006.203.07:52:16.14#ibcon#enter sib2, iclass 20, count 0 2006.203.07:52:16.14#ibcon#flushed, iclass 20, count 0 2006.203.07:52:16.14#ibcon#about to write, iclass 20, count 0 2006.203.07:52:16.14#ibcon#wrote, iclass 20, count 0 2006.203.07:52:16.14#ibcon#about to read 3, iclass 20, count 0 2006.203.07:52:16.18#ibcon#read 3, iclass 20, count 0 2006.203.07:52:16.18#ibcon#about to read 4, iclass 20, count 0 2006.203.07:52:16.18#ibcon#read 4, iclass 20, count 0 2006.203.07:52:16.18#ibcon#about to read 5, iclass 20, count 0 2006.203.07:52:16.18#ibcon#read 5, iclass 20, count 0 2006.203.07:52:16.18#ibcon#about to read 6, iclass 20, count 0 2006.203.07:52:16.18#ibcon#read 6, iclass 20, count 0 2006.203.07:52:16.18#ibcon#end of sib2, iclass 20, count 0 2006.203.07:52:16.18#ibcon#*after write, iclass 20, count 0 2006.203.07:52:16.18#ibcon#*before return 0, iclass 20, count 0 2006.203.07:52:16.18#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.203.07:52:16.18#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.203.07:52:16.18#ibcon#about to clear, iclass 20 cls_cnt 0 2006.203.07:52:16.18#ibcon#cleared, iclass 20 cls_cnt 0 2006.203.07:52:16.18$vc4f8/vb=4,4 2006.203.07:52:16.18#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.203.07:52:16.18#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.203.07:52:16.18#ibcon#ireg 11 cls_cnt 2 2006.203.07:52:16.18#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.203.07:52:16.24#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.203.07:52:16.24#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.203.07:52:16.24#ibcon#enter wrdev, iclass 22, count 2 2006.203.07:52:16.24#ibcon#first serial, iclass 22, count 2 2006.203.07:52:16.24#ibcon#enter sib2, iclass 22, count 2 2006.203.07:52:16.24#ibcon#flushed, iclass 22, count 2 2006.203.07:52:16.24#ibcon#about to write, iclass 22, count 2 2006.203.07:52:16.24#ibcon#wrote, iclass 22, count 2 2006.203.07:52:16.24#ibcon#about to read 3, iclass 22, count 2 2006.203.07:52:16.26#ibcon#read 3, iclass 22, count 2 2006.203.07:52:16.26#ibcon#about to read 4, iclass 22, count 2 2006.203.07:52:16.26#ibcon#read 4, iclass 22, count 2 2006.203.07:52:16.26#ibcon#about to read 5, iclass 22, count 2 2006.203.07:52:16.26#ibcon#read 5, iclass 22, count 2 2006.203.07:52:16.26#ibcon#about to read 6, iclass 22, count 2 2006.203.07:52:16.26#ibcon#read 6, iclass 22, count 2 2006.203.07:52:16.26#ibcon#end of sib2, iclass 22, count 2 2006.203.07:52:16.26#ibcon#*mode == 0, iclass 22, count 2 2006.203.07:52:16.26#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.203.07:52:16.26#ibcon#[27=AT04-04\r\n] 2006.203.07:52:16.26#ibcon#*before write, iclass 22, count 2 2006.203.07:52:16.26#ibcon#enter sib2, iclass 22, count 2 2006.203.07:52:16.26#ibcon#flushed, iclass 22, count 2 2006.203.07:52:16.26#ibcon#about to write, iclass 22, count 2 2006.203.07:52:16.26#ibcon#wrote, iclass 22, count 2 2006.203.07:52:16.26#ibcon#about to read 3, iclass 22, count 2 2006.203.07:52:16.29#ibcon#read 3, iclass 22, count 2 2006.203.07:52:16.29#ibcon#about to read 4, iclass 22, count 2 2006.203.07:52:16.29#ibcon#read 4, iclass 22, count 2 2006.203.07:52:16.29#ibcon#about to read 5, iclass 22, count 2 2006.203.07:52:16.29#ibcon#read 5, iclass 22, count 2 2006.203.07:52:16.29#ibcon#about to read 6, iclass 22, count 2 2006.203.07:52:16.29#ibcon#read 6, iclass 22, count 2 2006.203.07:52:16.29#ibcon#end of sib2, iclass 22, count 2 2006.203.07:52:16.29#ibcon#*after write, iclass 22, count 2 2006.203.07:52:16.29#ibcon#*before return 0, iclass 22, count 2 2006.203.07:52:16.29#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.203.07:52:16.29#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.203.07:52:16.29#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.203.07:52:16.29#ibcon#ireg 7 cls_cnt 0 2006.203.07:52:16.29#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.203.07:52:16.41#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.203.07:52:16.41#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.203.07:52:16.41#ibcon#enter wrdev, iclass 22, count 0 2006.203.07:52:16.41#ibcon#first serial, iclass 22, count 0 2006.203.07:52:16.41#ibcon#enter sib2, iclass 22, count 0 2006.203.07:52:16.41#ibcon#flushed, iclass 22, count 0 2006.203.07:52:16.41#ibcon#about to write, iclass 22, count 0 2006.203.07:52:16.41#ibcon#wrote, iclass 22, count 0 2006.203.07:52:16.41#ibcon#about to read 3, iclass 22, count 0 2006.203.07:52:16.43#ibcon#read 3, iclass 22, count 0 2006.203.07:52:16.43#ibcon#about to read 4, iclass 22, count 0 2006.203.07:52:16.43#ibcon#read 4, iclass 22, count 0 2006.203.07:52:16.43#ibcon#about to read 5, iclass 22, count 0 2006.203.07:52:16.43#ibcon#read 5, iclass 22, count 0 2006.203.07:52:16.43#ibcon#about to read 6, iclass 22, count 0 2006.203.07:52:16.43#ibcon#read 6, iclass 22, count 0 2006.203.07:52:16.43#ibcon#end of sib2, iclass 22, count 0 2006.203.07:52:16.43#ibcon#*mode == 0, iclass 22, count 0 2006.203.07:52:16.43#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.203.07:52:16.43#ibcon#[27=USB\r\n] 2006.203.07:52:16.43#ibcon#*before write, iclass 22, count 0 2006.203.07:52:16.43#ibcon#enter sib2, iclass 22, count 0 2006.203.07:52:16.43#ibcon#flushed, iclass 22, count 0 2006.203.07:52:16.43#ibcon#about to write, iclass 22, count 0 2006.203.07:52:16.43#ibcon#wrote, iclass 22, count 0 2006.203.07:52:16.43#ibcon#about to read 3, iclass 22, count 0 2006.203.07:52:16.46#ibcon#read 3, iclass 22, count 0 2006.203.07:52:16.46#ibcon#about to read 4, iclass 22, count 0 2006.203.07:52:16.46#ibcon#read 4, iclass 22, count 0 2006.203.07:52:16.46#ibcon#about to read 5, iclass 22, count 0 2006.203.07:52:16.46#ibcon#read 5, iclass 22, count 0 2006.203.07:52:16.46#ibcon#about to read 6, iclass 22, count 0 2006.203.07:52:16.46#ibcon#read 6, iclass 22, count 0 2006.203.07:52:16.46#ibcon#end of sib2, iclass 22, count 0 2006.203.07:52:16.46#ibcon#*after write, iclass 22, count 0 2006.203.07:52:16.46#ibcon#*before return 0, iclass 22, count 0 2006.203.07:52:16.46#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.203.07:52:16.46#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.203.07:52:16.46#ibcon#about to clear, iclass 22 cls_cnt 0 2006.203.07:52:16.46#ibcon#cleared, iclass 22 cls_cnt 0 2006.203.07:52:16.46$vc4f8/vblo=5,744.99 2006.203.07:52:16.46#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.203.07:52:16.46#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.203.07:52:16.46#ibcon#ireg 17 cls_cnt 0 2006.203.07:52:16.46#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.203.07:52:16.46#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.203.07:52:16.46#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.203.07:52:16.46#ibcon#enter wrdev, iclass 24, count 0 2006.203.07:52:16.46#ibcon#first serial, iclass 24, count 0 2006.203.07:52:16.46#ibcon#enter sib2, iclass 24, count 0 2006.203.07:52:16.46#ibcon#flushed, iclass 24, count 0 2006.203.07:52:16.46#ibcon#about to write, iclass 24, count 0 2006.203.07:52:16.46#ibcon#wrote, iclass 24, count 0 2006.203.07:52:16.46#ibcon#about to read 3, iclass 24, count 0 2006.203.07:52:16.48#ibcon#read 3, iclass 24, count 0 2006.203.07:52:16.48#ibcon#about to read 4, iclass 24, count 0 2006.203.07:52:16.48#ibcon#read 4, iclass 24, count 0 2006.203.07:52:16.48#ibcon#about to read 5, iclass 24, count 0 2006.203.07:52:16.48#ibcon#read 5, iclass 24, count 0 2006.203.07:52:16.48#ibcon#about to read 6, iclass 24, count 0 2006.203.07:52:16.48#ibcon#read 6, iclass 24, count 0 2006.203.07:52:16.48#ibcon#end of sib2, iclass 24, count 0 2006.203.07:52:16.48#ibcon#*mode == 0, iclass 24, count 0 2006.203.07:52:16.48#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.203.07:52:16.48#ibcon#[28=FRQ=05,744.99\r\n] 2006.203.07:52:16.48#ibcon#*before write, iclass 24, count 0 2006.203.07:52:16.48#ibcon#enter sib2, iclass 24, count 0 2006.203.07:52:16.48#ibcon#flushed, iclass 24, count 0 2006.203.07:52:16.48#ibcon#about to write, iclass 24, count 0 2006.203.07:52:16.48#ibcon#wrote, iclass 24, count 0 2006.203.07:52:16.48#ibcon#about to read 3, iclass 24, count 0 2006.203.07:52:16.52#ibcon#read 3, iclass 24, count 0 2006.203.07:52:16.52#ibcon#about to read 4, iclass 24, count 0 2006.203.07:52:16.52#ibcon#read 4, iclass 24, count 0 2006.203.07:52:16.52#ibcon#about to read 5, iclass 24, count 0 2006.203.07:52:16.52#ibcon#read 5, iclass 24, count 0 2006.203.07:52:16.52#ibcon#about to read 6, iclass 24, count 0 2006.203.07:52:16.52#ibcon#read 6, iclass 24, count 0 2006.203.07:52:16.52#ibcon#end of sib2, iclass 24, count 0 2006.203.07:52:16.52#ibcon#*after write, iclass 24, count 0 2006.203.07:52:16.52#ibcon#*before return 0, iclass 24, count 0 2006.203.07:52:16.52#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.203.07:52:16.52#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.203.07:52:16.52#ibcon#about to clear, iclass 24 cls_cnt 0 2006.203.07:52:16.52#ibcon#cleared, iclass 24 cls_cnt 0 2006.203.07:52:16.52$vc4f8/vb=5,3 2006.203.07:52:16.52#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.203.07:52:16.52#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.203.07:52:16.52#ibcon#ireg 11 cls_cnt 2 2006.203.07:52:16.52#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.203.07:52:16.58#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.203.07:52:16.58#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.203.07:52:16.58#ibcon#enter wrdev, iclass 26, count 2 2006.203.07:52:16.58#ibcon#first serial, iclass 26, count 2 2006.203.07:52:16.58#ibcon#enter sib2, iclass 26, count 2 2006.203.07:52:16.58#ibcon#flushed, iclass 26, count 2 2006.203.07:52:16.58#ibcon#about to write, iclass 26, count 2 2006.203.07:52:16.58#ibcon#wrote, iclass 26, count 2 2006.203.07:52:16.58#ibcon#about to read 3, iclass 26, count 2 2006.203.07:52:16.60#ibcon#read 3, iclass 26, count 2 2006.203.07:52:16.60#ibcon#about to read 4, iclass 26, count 2 2006.203.07:52:16.60#ibcon#read 4, iclass 26, count 2 2006.203.07:52:16.60#ibcon#about to read 5, iclass 26, count 2 2006.203.07:52:16.60#ibcon#read 5, iclass 26, count 2 2006.203.07:52:16.60#ibcon#about to read 6, iclass 26, count 2 2006.203.07:52:16.60#ibcon#read 6, iclass 26, count 2 2006.203.07:52:16.60#ibcon#end of sib2, iclass 26, count 2 2006.203.07:52:16.60#ibcon#*mode == 0, iclass 26, count 2 2006.203.07:52:16.60#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.203.07:52:16.60#ibcon#[27=AT05-03\r\n] 2006.203.07:52:16.60#ibcon#*before write, iclass 26, count 2 2006.203.07:52:16.60#ibcon#enter sib2, iclass 26, count 2 2006.203.07:52:16.60#ibcon#flushed, iclass 26, count 2 2006.203.07:52:16.60#ibcon#about to write, iclass 26, count 2 2006.203.07:52:16.60#ibcon#wrote, iclass 26, count 2 2006.203.07:52:16.60#ibcon#about to read 3, iclass 26, count 2 2006.203.07:52:16.63#ibcon#read 3, iclass 26, count 2 2006.203.07:52:16.63#ibcon#about to read 4, iclass 26, count 2 2006.203.07:52:16.63#ibcon#read 4, iclass 26, count 2 2006.203.07:52:16.63#ibcon#about to read 5, iclass 26, count 2 2006.203.07:52:16.63#ibcon#read 5, iclass 26, count 2 2006.203.07:52:16.63#ibcon#about to read 6, iclass 26, count 2 2006.203.07:52:16.63#ibcon#read 6, iclass 26, count 2 2006.203.07:52:16.63#ibcon#end of sib2, iclass 26, count 2 2006.203.07:52:16.63#ibcon#*after write, iclass 26, count 2 2006.203.07:52:16.63#ibcon#*before return 0, iclass 26, count 2 2006.203.07:52:16.63#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.203.07:52:16.63#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.203.07:52:16.63#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.203.07:52:16.63#ibcon#ireg 7 cls_cnt 0 2006.203.07:52:16.63#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.203.07:52:16.75#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.203.07:52:16.75#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.203.07:52:16.75#ibcon#enter wrdev, iclass 26, count 0 2006.203.07:52:16.75#ibcon#first serial, iclass 26, count 0 2006.203.07:52:16.75#ibcon#enter sib2, iclass 26, count 0 2006.203.07:52:16.75#ibcon#flushed, iclass 26, count 0 2006.203.07:52:16.75#ibcon#about to write, iclass 26, count 0 2006.203.07:52:16.75#ibcon#wrote, iclass 26, count 0 2006.203.07:52:16.75#ibcon#about to read 3, iclass 26, count 0 2006.203.07:52:16.77#ibcon#read 3, iclass 26, count 0 2006.203.07:52:16.77#ibcon#about to read 4, iclass 26, count 0 2006.203.07:52:16.77#ibcon#read 4, iclass 26, count 0 2006.203.07:52:16.77#ibcon#about to read 5, iclass 26, count 0 2006.203.07:52:16.77#ibcon#read 5, iclass 26, count 0 2006.203.07:52:16.77#ibcon#about to read 6, iclass 26, count 0 2006.203.07:52:16.77#ibcon#read 6, iclass 26, count 0 2006.203.07:52:16.77#ibcon#end of sib2, iclass 26, count 0 2006.203.07:52:16.77#ibcon#*mode == 0, iclass 26, count 0 2006.203.07:52:16.77#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.203.07:52:16.77#ibcon#[27=USB\r\n] 2006.203.07:52:16.77#ibcon#*before write, iclass 26, count 0 2006.203.07:52:16.77#ibcon#enter sib2, iclass 26, count 0 2006.203.07:52:16.77#ibcon#flushed, iclass 26, count 0 2006.203.07:52:16.77#ibcon#about to write, iclass 26, count 0 2006.203.07:52:16.77#ibcon#wrote, iclass 26, count 0 2006.203.07:52:16.77#ibcon#about to read 3, iclass 26, count 0 2006.203.07:52:16.80#ibcon#read 3, iclass 26, count 0 2006.203.07:52:16.80#ibcon#about to read 4, iclass 26, count 0 2006.203.07:52:16.80#ibcon#read 4, iclass 26, count 0 2006.203.07:52:16.80#ibcon#about to read 5, iclass 26, count 0 2006.203.07:52:16.80#ibcon#read 5, iclass 26, count 0 2006.203.07:52:16.80#ibcon#about to read 6, iclass 26, count 0 2006.203.07:52:16.80#ibcon#read 6, iclass 26, count 0 2006.203.07:52:16.80#ibcon#end of sib2, iclass 26, count 0 2006.203.07:52:16.80#ibcon#*after write, iclass 26, count 0 2006.203.07:52:16.80#ibcon#*before return 0, iclass 26, count 0 2006.203.07:52:16.80#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.203.07:52:16.80#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.203.07:52:16.80#ibcon#about to clear, iclass 26 cls_cnt 0 2006.203.07:52:16.80#ibcon#cleared, iclass 26 cls_cnt 0 2006.203.07:52:16.80$vc4f8/vblo=6,752.99 2006.203.07:52:16.80#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.203.07:52:16.80#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.203.07:52:16.80#ibcon#ireg 17 cls_cnt 0 2006.203.07:52:16.80#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.203.07:52:16.80#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.203.07:52:16.80#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.203.07:52:16.80#ibcon#enter wrdev, iclass 28, count 0 2006.203.07:52:16.80#ibcon#first serial, iclass 28, count 0 2006.203.07:52:16.80#ibcon#enter sib2, iclass 28, count 0 2006.203.07:52:16.80#ibcon#flushed, iclass 28, count 0 2006.203.07:52:16.80#ibcon#about to write, iclass 28, count 0 2006.203.07:52:16.80#ibcon#wrote, iclass 28, count 0 2006.203.07:52:16.80#ibcon#about to read 3, iclass 28, count 0 2006.203.07:52:16.83#ibcon#read 3, iclass 28, count 0 2006.203.07:52:16.83#ibcon#about to read 4, iclass 28, count 0 2006.203.07:52:16.83#ibcon#read 4, iclass 28, count 0 2006.203.07:52:16.83#ibcon#about to read 5, iclass 28, count 0 2006.203.07:52:16.83#ibcon#read 5, iclass 28, count 0 2006.203.07:52:16.83#ibcon#about to read 6, iclass 28, count 0 2006.203.07:52:16.83#ibcon#read 6, iclass 28, count 0 2006.203.07:52:16.83#ibcon#end of sib2, iclass 28, count 0 2006.203.07:52:16.83#ibcon#*mode == 0, iclass 28, count 0 2006.203.07:52:16.83#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.203.07:52:16.83#ibcon#[28=FRQ=06,752.99\r\n] 2006.203.07:52:16.83#ibcon#*before write, iclass 28, count 0 2006.203.07:52:16.83#ibcon#enter sib2, iclass 28, count 0 2006.203.07:52:16.83#ibcon#flushed, iclass 28, count 0 2006.203.07:52:16.83#ibcon#about to write, iclass 28, count 0 2006.203.07:52:16.83#ibcon#wrote, iclass 28, count 0 2006.203.07:52:16.83#ibcon#about to read 3, iclass 28, count 0 2006.203.07:52:16.87#ibcon#read 3, iclass 28, count 0 2006.203.07:52:16.87#ibcon#about to read 4, iclass 28, count 0 2006.203.07:52:16.87#ibcon#read 4, iclass 28, count 0 2006.203.07:52:16.87#ibcon#about to read 5, iclass 28, count 0 2006.203.07:52:16.87#ibcon#read 5, iclass 28, count 0 2006.203.07:52:16.87#ibcon#about to read 6, iclass 28, count 0 2006.203.07:52:16.87#ibcon#read 6, iclass 28, count 0 2006.203.07:52:16.87#ibcon#end of sib2, iclass 28, count 0 2006.203.07:52:16.87#ibcon#*after write, iclass 28, count 0 2006.203.07:52:16.87#ibcon#*before return 0, iclass 28, count 0 2006.203.07:52:16.87#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.203.07:52:16.87#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.203.07:52:16.87#ibcon#about to clear, iclass 28 cls_cnt 0 2006.203.07:52:16.87#ibcon#cleared, iclass 28 cls_cnt 0 2006.203.07:52:16.87$vc4f8/vb=6,4 2006.203.07:52:16.87#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.203.07:52:16.87#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.203.07:52:16.87#ibcon#ireg 11 cls_cnt 2 2006.203.07:52:16.87#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.203.07:52:16.92#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.203.07:52:16.92#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.203.07:52:16.92#ibcon#enter wrdev, iclass 30, count 2 2006.203.07:52:16.92#ibcon#first serial, iclass 30, count 2 2006.203.07:52:16.92#ibcon#enter sib2, iclass 30, count 2 2006.203.07:52:16.92#ibcon#flushed, iclass 30, count 2 2006.203.07:52:16.92#ibcon#about to write, iclass 30, count 2 2006.203.07:52:16.92#ibcon#wrote, iclass 30, count 2 2006.203.07:52:16.92#ibcon#about to read 3, iclass 30, count 2 2006.203.07:52:16.94#ibcon#read 3, iclass 30, count 2 2006.203.07:52:16.94#ibcon#about to read 4, iclass 30, count 2 2006.203.07:52:16.94#ibcon#read 4, iclass 30, count 2 2006.203.07:52:16.94#ibcon#about to read 5, iclass 30, count 2 2006.203.07:52:16.94#ibcon#read 5, iclass 30, count 2 2006.203.07:52:16.94#ibcon#about to read 6, iclass 30, count 2 2006.203.07:52:16.94#ibcon#read 6, iclass 30, count 2 2006.203.07:52:16.94#ibcon#end of sib2, iclass 30, count 2 2006.203.07:52:16.94#ibcon#*mode == 0, iclass 30, count 2 2006.203.07:52:16.94#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.203.07:52:16.94#ibcon#[27=AT06-04\r\n] 2006.203.07:52:16.94#ibcon#*before write, iclass 30, count 2 2006.203.07:52:16.94#ibcon#enter sib2, iclass 30, count 2 2006.203.07:52:16.94#ibcon#flushed, iclass 30, count 2 2006.203.07:52:16.94#ibcon#about to write, iclass 30, count 2 2006.203.07:52:16.94#ibcon#wrote, iclass 30, count 2 2006.203.07:52:16.94#ibcon#about to read 3, iclass 30, count 2 2006.203.07:52:16.97#ibcon#read 3, iclass 30, count 2 2006.203.07:52:16.97#ibcon#about to read 4, iclass 30, count 2 2006.203.07:52:16.97#ibcon#read 4, iclass 30, count 2 2006.203.07:52:16.97#ibcon#about to read 5, iclass 30, count 2 2006.203.07:52:16.97#ibcon#read 5, iclass 30, count 2 2006.203.07:52:16.97#ibcon#about to read 6, iclass 30, count 2 2006.203.07:52:16.97#ibcon#read 6, iclass 30, count 2 2006.203.07:52:16.97#ibcon#end of sib2, iclass 30, count 2 2006.203.07:52:16.97#ibcon#*after write, iclass 30, count 2 2006.203.07:52:16.97#ibcon#*before return 0, iclass 30, count 2 2006.203.07:52:16.97#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.203.07:52:16.97#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.203.07:52:16.97#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.203.07:52:16.97#ibcon#ireg 7 cls_cnt 0 2006.203.07:52:16.97#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.203.07:52:17.09#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.203.07:52:17.09#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.203.07:52:17.09#ibcon#enter wrdev, iclass 30, count 0 2006.203.07:52:17.09#ibcon#first serial, iclass 30, count 0 2006.203.07:52:17.09#ibcon#enter sib2, iclass 30, count 0 2006.203.07:52:17.09#ibcon#flushed, iclass 30, count 0 2006.203.07:52:17.09#ibcon#about to write, iclass 30, count 0 2006.203.07:52:17.09#ibcon#wrote, iclass 30, count 0 2006.203.07:52:17.09#ibcon#about to read 3, iclass 30, count 0 2006.203.07:52:17.11#ibcon#read 3, iclass 30, count 0 2006.203.07:52:17.11#ibcon#about to read 4, iclass 30, count 0 2006.203.07:52:17.11#ibcon#read 4, iclass 30, count 0 2006.203.07:52:17.11#ibcon#about to read 5, iclass 30, count 0 2006.203.07:52:17.11#ibcon#read 5, iclass 30, count 0 2006.203.07:52:17.11#ibcon#about to read 6, iclass 30, count 0 2006.203.07:52:17.11#ibcon#read 6, iclass 30, count 0 2006.203.07:52:17.11#ibcon#end of sib2, iclass 30, count 0 2006.203.07:52:17.11#ibcon#*mode == 0, iclass 30, count 0 2006.203.07:52:17.11#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.203.07:52:17.11#ibcon#[27=USB\r\n] 2006.203.07:52:17.11#ibcon#*before write, iclass 30, count 0 2006.203.07:52:17.11#ibcon#enter sib2, iclass 30, count 0 2006.203.07:52:17.11#ibcon#flushed, iclass 30, count 0 2006.203.07:52:17.11#ibcon#about to write, iclass 30, count 0 2006.203.07:52:17.11#ibcon#wrote, iclass 30, count 0 2006.203.07:52:17.11#ibcon#about to read 3, iclass 30, count 0 2006.203.07:52:17.14#ibcon#read 3, iclass 30, count 0 2006.203.07:52:17.14#ibcon#about to read 4, iclass 30, count 0 2006.203.07:52:17.14#ibcon#read 4, iclass 30, count 0 2006.203.07:52:17.14#ibcon#about to read 5, iclass 30, count 0 2006.203.07:52:17.14#ibcon#read 5, iclass 30, count 0 2006.203.07:52:17.14#ibcon#about to read 6, iclass 30, count 0 2006.203.07:52:17.14#ibcon#read 6, iclass 30, count 0 2006.203.07:52:17.14#ibcon#end of sib2, iclass 30, count 0 2006.203.07:52:17.14#ibcon#*after write, iclass 30, count 0 2006.203.07:52:17.14#ibcon#*before return 0, iclass 30, count 0 2006.203.07:52:17.14#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.203.07:52:17.14#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.203.07:52:17.14#ibcon#about to clear, iclass 30 cls_cnt 0 2006.203.07:52:17.14#ibcon#cleared, iclass 30 cls_cnt 0 2006.203.07:52:17.14$vc4f8/vabw=wide 2006.203.07:52:17.14#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.203.07:52:17.14#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.203.07:52:17.14#ibcon#ireg 8 cls_cnt 0 2006.203.07:52:17.14#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.203.07:52:17.14#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.203.07:52:17.14#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.203.07:52:17.14#ibcon#enter wrdev, iclass 32, count 0 2006.203.07:52:17.14#ibcon#first serial, iclass 32, count 0 2006.203.07:52:17.14#ibcon#enter sib2, iclass 32, count 0 2006.203.07:52:17.14#ibcon#flushed, iclass 32, count 0 2006.203.07:52:17.14#ibcon#about to write, iclass 32, count 0 2006.203.07:52:17.14#ibcon#wrote, iclass 32, count 0 2006.203.07:52:17.14#ibcon#about to read 3, iclass 32, count 0 2006.203.07:52:17.16#ibcon#read 3, iclass 32, count 0 2006.203.07:52:17.16#ibcon#about to read 4, iclass 32, count 0 2006.203.07:52:17.16#ibcon#read 4, iclass 32, count 0 2006.203.07:52:17.16#ibcon#about to read 5, iclass 32, count 0 2006.203.07:52:17.16#ibcon#read 5, iclass 32, count 0 2006.203.07:52:17.16#ibcon#about to read 6, iclass 32, count 0 2006.203.07:52:17.16#ibcon#read 6, iclass 32, count 0 2006.203.07:52:17.16#ibcon#end of sib2, iclass 32, count 0 2006.203.07:52:17.16#ibcon#*mode == 0, iclass 32, count 0 2006.203.07:52:17.16#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.203.07:52:17.16#ibcon#[25=BW32\r\n] 2006.203.07:52:17.16#ibcon#*before write, iclass 32, count 0 2006.203.07:52:17.16#ibcon#enter sib2, iclass 32, count 0 2006.203.07:52:17.16#ibcon#flushed, iclass 32, count 0 2006.203.07:52:17.16#ibcon#about to write, iclass 32, count 0 2006.203.07:52:17.16#ibcon#wrote, iclass 32, count 0 2006.203.07:52:17.16#ibcon#about to read 3, iclass 32, count 0 2006.203.07:52:17.19#ibcon#read 3, iclass 32, count 0 2006.203.07:52:17.19#ibcon#about to read 4, iclass 32, count 0 2006.203.07:52:17.19#ibcon#read 4, iclass 32, count 0 2006.203.07:52:17.19#ibcon#about to read 5, iclass 32, count 0 2006.203.07:52:17.19#ibcon#read 5, iclass 32, count 0 2006.203.07:52:17.19#ibcon#about to read 6, iclass 32, count 0 2006.203.07:52:17.19#ibcon#read 6, iclass 32, count 0 2006.203.07:52:17.19#ibcon#end of sib2, iclass 32, count 0 2006.203.07:52:17.19#ibcon#*after write, iclass 32, count 0 2006.203.07:52:17.19#ibcon#*before return 0, iclass 32, count 0 2006.203.07:52:17.19#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.203.07:52:17.19#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.203.07:52:17.19#ibcon#about to clear, iclass 32 cls_cnt 0 2006.203.07:52:17.19#ibcon#cleared, iclass 32 cls_cnt 0 2006.203.07:52:17.19$vc4f8/vbbw=wide 2006.203.07:52:17.19#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.203.07:52:17.19#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.203.07:52:17.19#ibcon#ireg 8 cls_cnt 0 2006.203.07:52:17.19#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.203.07:52:17.26#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.203.07:52:17.26#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.203.07:52:17.26#ibcon#enter wrdev, iclass 34, count 0 2006.203.07:52:17.26#ibcon#first serial, iclass 34, count 0 2006.203.07:52:17.26#ibcon#enter sib2, iclass 34, count 0 2006.203.07:52:17.26#ibcon#flushed, iclass 34, count 0 2006.203.07:52:17.26#ibcon#about to write, iclass 34, count 0 2006.203.07:52:17.26#ibcon#wrote, iclass 34, count 0 2006.203.07:52:17.26#ibcon#about to read 3, iclass 34, count 0 2006.203.07:52:17.28#ibcon#read 3, iclass 34, count 0 2006.203.07:52:17.28#ibcon#about to read 4, iclass 34, count 0 2006.203.07:52:17.28#ibcon#read 4, iclass 34, count 0 2006.203.07:52:17.28#ibcon#about to read 5, iclass 34, count 0 2006.203.07:52:17.28#ibcon#read 5, iclass 34, count 0 2006.203.07:52:17.28#ibcon#about to read 6, iclass 34, count 0 2006.203.07:52:17.28#ibcon#read 6, iclass 34, count 0 2006.203.07:52:17.28#ibcon#end of sib2, iclass 34, count 0 2006.203.07:52:17.28#ibcon#*mode == 0, iclass 34, count 0 2006.203.07:52:17.28#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.203.07:52:17.28#ibcon#[27=BW32\r\n] 2006.203.07:52:17.28#ibcon#*before write, iclass 34, count 0 2006.203.07:52:17.28#ibcon#enter sib2, iclass 34, count 0 2006.203.07:52:17.28#ibcon#flushed, iclass 34, count 0 2006.203.07:52:17.28#ibcon#about to write, iclass 34, count 0 2006.203.07:52:17.28#ibcon#wrote, iclass 34, count 0 2006.203.07:52:17.28#ibcon#about to read 3, iclass 34, count 0 2006.203.07:52:17.31#ibcon#read 3, iclass 34, count 0 2006.203.07:52:17.31#ibcon#about to read 4, iclass 34, count 0 2006.203.07:52:17.31#ibcon#read 4, iclass 34, count 0 2006.203.07:52:17.31#ibcon#about to read 5, iclass 34, count 0 2006.203.07:52:17.31#ibcon#read 5, iclass 34, count 0 2006.203.07:52:17.31#ibcon#about to read 6, iclass 34, count 0 2006.203.07:52:17.31#ibcon#read 6, iclass 34, count 0 2006.203.07:52:17.31#ibcon#end of sib2, iclass 34, count 0 2006.203.07:52:17.31#ibcon#*after write, iclass 34, count 0 2006.203.07:52:17.31#ibcon#*before return 0, iclass 34, count 0 2006.203.07:52:17.31#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.203.07:52:17.31#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.203.07:52:17.31#ibcon#about to clear, iclass 34 cls_cnt 0 2006.203.07:52:17.31#ibcon#cleared, iclass 34 cls_cnt 0 2006.203.07:52:17.31$4f8m12a/ifd4f 2006.203.07:52:17.31$ifd4f/lo= 2006.203.07:52:17.31$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.203.07:52:17.31$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.203.07:52:17.31$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.203.07:52:17.31$ifd4f/patch= 2006.203.07:52:17.31$ifd4f/patch=lo1,a1,a2,a3,a4 2006.203.07:52:17.31$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.203.07:52:17.31$ifd4f/patch=lo3,a5,a6,a7,a8 2006.203.07:52:17.31$4f8m12a/"form=m,16.000,1:2 2006.203.07:52:17.31$4f8m12a/"tpicd 2006.203.07:52:17.31$4f8m12a/echo=off 2006.203.07:52:17.31$4f8m12a/xlog=off 2006.203.07:52:17.31:!2006.203.07:52:40 2006.203.07:52:23.14#trakl#Source acquired 2006.203.07:52:25.14#flagr#flagr/antenna,acquired 2006.203.07:52:40.00:preob 2006.203.07:52:41.14/onsource/TRACKING 2006.203.07:52:41.14:!2006.203.07:52:50 2006.203.07:52:50.00:data_valid=on 2006.203.07:52:50.00:midob 2006.203.07:52:50.14/onsource/TRACKING 2006.203.07:52:50.14/wx/23.80,1001.1,98 2006.203.07:52:50.29/cable/+6.4604E-03 2006.203.07:52:51.38/va/01,08,usb,yes,32,34 2006.203.07:52:51.38/va/02,07,usb,yes,32,34 2006.203.07:52:51.38/va/03,08,usb,yes,24,25 2006.203.07:52:51.38/va/04,07,usb,yes,33,36 2006.203.07:52:51.38/va/05,07,usb,yes,36,38 2006.203.07:52:51.38/va/06,06,usb,yes,35,35 2006.203.07:52:51.38/va/07,07,usb,yes,32,31 2006.203.07:52:51.38/va/08,06,usb,yes,39,38 2006.203.07:52:51.61/valo/01,532.99,yes,locked 2006.203.07:52:51.61/valo/02,572.99,yes,locked 2006.203.07:52:51.61/valo/03,672.99,yes,locked 2006.203.07:52:51.61/valo/04,832.99,yes,locked 2006.203.07:52:51.61/valo/05,652.99,yes,locked 2006.203.07:52:51.61/valo/06,772.99,yes,locked 2006.203.07:52:51.61/valo/07,832.99,yes,locked 2006.203.07:52:51.61/valo/08,852.99,yes,locked 2006.203.07:52:52.70/vb/01,04,usb,yes,30,29 2006.203.07:52:52.70/vb/02,04,usb,yes,32,34 2006.203.07:52:52.70/vb/03,04,usb,yes,29,32 2006.203.07:52:52.70/vb/04,04,usb,yes,30,30 2006.203.07:52:52.70/vb/05,03,usb,yes,35,39 2006.203.07:52:52.70/vb/06,04,usb,yes,29,32 2006.203.07:52:52.70/vb/07,04,usb,yes,31,31 2006.203.07:52:52.70/vb/08,04,usb,yes,29,32 2006.203.07:52:52.93/vblo/01,632.99,yes,locked 2006.203.07:52:52.93/vblo/02,640.99,yes,locked 2006.203.07:52:52.93/vblo/03,656.99,yes,locked 2006.203.07:52:52.93/vblo/04,712.99,yes,locked 2006.203.07:52:52.93/vblo/05,744.99,yes,locked 2006.203.07:52:52.93/vblo/06,752.99,yes,locked 2006.203.07:52:52.93/vblo/07,734.99,yes,locked 2006.203.07:52:52.93/vblo/08,744.99,yes,locked 2006.203.07:52:53.08/vabw/8 2006.203.07:52:53.23/vbbw/8 2006.203.07:52:53.32/xfe/off,on,14.0 2006.203.07:52:53.71/ifatt/23,28,28,28 2006.203.07:52:54.08/fmout-gps/S +4.56E-07 2006.203.07:52:54.16:!2006.203.07:53:50 2006.203.07:53:50.00:data_valid=off 2006.203.07:53:50.00:postob 2006.203.07:53:50.19/cable/+6.4586E-03 2006.203.07:53:50.19/wx/23.79,1001.2,98 2006.203.07:53:51.07/fmout-gps/S +4.55E-07 2006.203.07:53:51.07:scan_name=203-0755,k06203,60 2006.203.07:53:51.08:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.203.07:53:51.14#flagr#flagr/antenna,new-source 2006.203.07:53:52.14:checkk5 2006.203.07:53:52.58/chk_autoobs//k5ts1/ autoobs is running! 2006.203.07:53:53.01/chk_autoobs//k5ts2/ autoobs is running! 2006.203.07:53:53.43/chk_autoobs//k5ts3/ autoobs is running! 2006.203.07:53:53.93/chk_autoobs//k5ts4/ autoobs is running! 2006.203.07:53:54.33/chk_obsdata//k5ts1/T2030752??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.07:53:54.70/chk_obsdata//k5ts2/T2030752??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.07:53:55.10/chk_obsdata//k5ts3/T2030752??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.07:53:55.51/chk_obsdata//k5ts4/T2030752??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.07:53:56.33/k5log//k5ts1_log_newline 2006.203.07:53:57.12/k5log//k5ts2_log_newline 2006.203.07:53:57.89/k5log//k5ts3_log_newline 2006.203.07:53:58.66/k5log//k5ts4_log_newline 2006.203.07:53:58.69/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.203.07:53:58.69:4f8m12a=2 2006.203.07:53:58.69$4f8m12a/echo=on 2006.203.07:53:58.69$4f8m12a/pcalon 2006.203.07:53:58.69$pcalon/"no phase cal control is implemented here 2006.203.07:53:58.69$4f8m12a/"tpicd=stop 2006.203.07:53:58.69$4f8m12a/vc4f8 2006.203.07:53:58.69$vc4f8/valo=1,532.99 2006.203.07:53:58.69#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.203.07:53:58.69#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.203.07:53:58.69#ibcon#ireg 17 cls_cnt 0 2006.203.07:53:58.69#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.203.07:53:58.69#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.203.07:53:58.69#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.203.07:53:58.69#ibcon#enter wrdev, iclass 3, count 0 2006.203.07:53:58.69#ibcon#first serial, iclass 3, count 0 2006.203.07:53:58.69#ibcon#enter sib2, iclass 3, count 0 2006.203.07:53:58.69#ibcon#flushed, iclass 3, count 0 2006.203.07:53:58.69#ibcon#about to write, iclass 3, count 0 2006.203.07:53:58.69#ibcon#wrote, iclass 3, count 0 2006.203.07:53:58.69#ibcon#about to read 3, iclass 3, count 0 2006.203.07:53:58.73#ibcon#read 3, iclass 3, count 0 2006.203.07:53:58.73#ibcon#about to read 4, iclass 3, count 0 2006.203.07:53:58.73#ibcon#read 4, iclass 3, count 0 2006.203.07:53:58.73#ibcon#about to read 5, iclass 3, count 0 2006.203.07:53:58.73#ibcon#read 5, iclass 3, count 0 2006.203.07:53:58.73#ibcon#about to read 6, iclass 3, count 0 2006.203.07:53:58.73#ibcon#read 6, iclass 3, count 0 2006.203.07:53:58.73#ibcon#end of sib2, iclass 3, count 0 2006.203.07:53:58.73#ibcon#*mode == 0, iclass 3, count 0 2006.203.07:53:58.73#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.203.07:53:58.73#ibcon#[26=FRQ=01,532.99\r\n] 2006.203.07:53:58.73#ibcon#*before write, iclass 3, count 0 2006.203.07:53:58.73#ibcon#enter sib2, iclass 3, count 0 2006.203.07:53:58.73#ibcon#flushed, iclass 3, count 0 2006.203.07:53:58.73#ibcon#about to write, iclass 3, count 0 2006.203.07:53:58.73#ibcon#wrote, iclass 3, count 0 2006.203.07:53:58.73#ibcon#about to read 3, iclass 3, count 0 2006.203.07:53:58.78#ibcon#read 3, iclass 3, count 0 2006.203.07:53:58.78#ibcon#about to read 4, iclass 3, count 0 2006.203.07:53:58.78#ibcon#read 4, iclass 3, count 0 2006.203.07:53:58.78#ibcon#about to read 5, iclass 3, count 0 2006.203.07:53:58.78#ibcon#read 5, iclass 3, count 0 2006.203.07:53:58.78#ibcon#about to read 6, iclass 3, count 0 2006.203.07:53:58.78#ibcon#read 6, iclass 3, count 0 2006.203.07:53:58.78#ibcon#end of sib2, iclass 3, count 0 2006.203.07:53:58.78#ibcon#*after write, iclass 3, count 0 2006.203.07:53:58.78#ibcon#*before return 0, iclass 3, count 0 2006.203.07:53:58.78#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.203.07:53:58.78#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.203.07:53:58.78#ibcon#about to clear, iclass 3 cls_cnt 0 2006.203.07:53:58.78#ibcon#cleared, iclass 3 cls_cnt 0 2006.203.07:53:58.78$vc4f8/va=1,8 2006.203.07:53:58.78#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.203.07:53:58.78#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.203.07:53:58.78#ibcon#ireg 11 cls_cnt 2 2006.203.07:53:58.78#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.203.07:53:58.78#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.203.07:53:58.78#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.203.07:53:58.78#ibcon#enter wrdev, iclass 5, count 2 2006.203.07:53:58.78#ibcon#first serial, iclass 5, count 2 2006.203.07:53:58.78#ibcon#enter sib2, iclass 5, count 2 2006.203.07:53:58.78#ibcon#flushed, iclass 5, count 2 2006.203.07:53:58.78#ibcon#about to write, iclass 5, count 2 2006.203.07:53:58.78#ibcon#wrote, iclass 5, count 2 2006.203.07:53:58.78#ibcon#about to read 3, iclass 5, count 2 2006.203.07:53:58.80#ibcon#read 3, iclass 5, count 2 2006.203.07:53:58.80#ibcon#about to read 4, iclass 5, count 2 2006.203.07:53:58.80#ibcon#read 4, iclass 5, count 2 2006.203.07:53:58.80#ibcon#about to read 5, iclass 5, count 2 2006.203.07:53:58.80#ibcon#read 5, iclass 5, count 2 2006.203.07:53:58.80#ibcon#about to read 6, iclass 5, count 2 2006.203.07:53:58.80#ibcon#read 6, iclass 5, count 2 2006.203.07:53:58.80#ibcon#end of sib2, iclass 5, count 2 2006.203.07:53:58.80#ibcon#*mode == 0, iclass 5, count 2 2006.203.07:53:58.80#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.203.07:53:58.80#ibcon#[25=AT01-08\r\n] 2006.203.07:53:58.80#ibcon#*before write, iclass 5, count 2 2006.203.07:53:58.80#ibcon#enter sib2, iclass 5, count 2 2006.203.07:53:58.80#ibcon#flushed, iclass 5, count 2 2006.203.07:53:58.80#ibcon#about to write, iclass 5, count 2 2006.203.07:53:58.80#ibcon#wrote, iclass 5, count 2 2006.203.07:53:58.80#ibcon#about to read 3, iclass 5, count 2 2006.203.07:53:58.84#ibcon#read 3, iclass 5, count 2 2006.203.07:53:58.84#ibcon#about to read 4, iclass 5, count 2 2006.203.07:53:58.84#ibcon#read 4, iclass 5, count 2 2006.203.07:53:58.84#ibcon#about to read 5, iclass 5, count 2 2006.203.07:53:58.84#ibcon#read 5, iclass 5, count 2 2006.203.07:53:58.84#ibcon#about to read 6, iclass 5, count 2 2006.203.07:53:58.84#ibcon#read 6, iclass 5, count 2 2006.203.07:53:58.84#ibcon#end of sib2, iclass 5, count 2 2006.203.07:53:58.84#ibcon#*after write, iclass 5, count 2 2006.203.07:53:58.84#ibcon#*before return 0, iclass 5, count 2 2006.203.07:53:58.84#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.203.07:53:58.84#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.203.07:53:58.84#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.203.07:53:58.84#ibcon#ireg 7 cls_cnt 0 2006.203.07:53:58.84#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.203.07:53:58.96#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.203.07:53:58.96#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.203.07:53:58.96#ibcon#enter wrdev, iclass 5, count 0 2006.203.07:53:58.96#ibcon#first serial, iclass 5, count 0 2006.203.07:53:58.96#ibcon#enter sib2, iclass 5, count 0 2006.203.07:53:58.96#ibcon#flushed, iclass 5, count 0 2006.203.07:53:58.96#ibcon#about to write, iclass 5, count 0 2006.203.07:53:58.96#ibcon#wrote, iclass 5, count 0 2006.203.07:53:58.96#ibcon#about to read 3, iclass 5, count 0 2006.203.07:53:58.98#ibcon#read 3, iclass 5, count 0 2006.203.07:53:58.98#ibcon#about to read 4, iclass 5, count 0 2006.203.07:53:58.98#ibcon#read 4, iclass 5, count 0 2006.203.07:53:58.98#ibcon#about to read 5, iclass 5, count 0 2006.203.07:53:58.98#ibcon#read 5, iclass 5, count 0 2006.203.07:53:58.98#ibcon#about to read 6, iclass 5, count 0 2006.203.07:53:58.98#ibcon#read 6, iclass 5, count 0 2006.203.07:53:58.98#ibcon#end of sib2, iclass 5, count 0 2006.203.07:53:58.98#ibcon#*mode == 0, iclass 5, count 0 2006.203.07:53:58.98#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.203.07:53:58.98#ibcon#[25=USB\r\n] 2006.203.07:53:58.98#ibcon#*before write, iclass 5, count 0 2006.203.07:53:58.98#ibcon#enter sib2, iclass 5, count 0 2006.203.07:53:58.98#ibcon#flushed, iclass 5, count 0 2006.203.07:53:58.98#ibcon#about to write, iclass 5, count 0 2006.203.07:53:58.98#ibcon#wrote, iclass 5, count 0 2006.203.07:53:58.98#ibcon#about to read 3, iclass 5, count 0 2006.203.07:53:59.01#ibcon#read 3, iclass 5, count 0 2006.203.07:53:59.01#ibcon#about to read 4, iclass 5, count 0 2006.203.07:53:59.01#ibcon#read 4, iclass 5, count 0 2006.203.07:53:59.01#ibcon#about to read 5, iclass 5, count 0 2006.203.07:53:59.01#ibcon#read 5, iclass 5, count 0 2006.203.07:53:59.01#ibcon#about to read 6, iclass 5, count 0 2006.203.07:53:59.01#ibcon#read 6, iclass 5, count 0 2006.203.07:53:59.01#ibcon#end of sib2, iclass 5, count 0 2006.203.07:53:59.01#ibcon#*after write, iclass 5, count 0 2006.203.07:53:59.01#ibcon#*before return 0, iclass 5, count 0 2006.203.07:53:59.01#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.203.07:53:59.01#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.203.07:53:59.01#ibcon#about to clear, iclass 5 cls_cnt 0 2006.203.07:53:59.01#ibcon#cleared, iclass 5 cls_cnt 0 2006.203.07:53:59.01$vc4f8/valo=2,572.99 2006.203.07:53:59.01#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.203.07:53:59.01#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.203.07:53:59.01#ibcon#ireg 17 cls_cnt 0 2006.203.07:53:59.01#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.203.07:53:59.01#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.203.07:53:59.01#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.203.07:53:59.01#ibcon#enter wrdev, iclass 7, count 0 2006.203.07:53:59.01#ibcon#first serial, iclass 7, count 0 2006.203.07:53:59.01#ibcon#enter sib2, iclass 7, count 0 2006.203.07:53:59.01#ibcon#flushed, iclass 7, count 0 2006.203.07:53:59.01#ibcon#about to write, iclass 7, count 0 2006.203.07:53:59.01#ibcon#wrote, iclass 7, count 0 2006.203.07:53:59.01#ibcon#about to read 3, iclass 7, count 0 2006.203.07:53:59.03#ibcon#read 3, iclass 7, count 0 2006.203.07:53:59.03#ibcon#about to read 4, iclass 7, count 0 2006.203.07:53:59.03#ibcon#read 4, iclass 7, count 0 2006.203.07:53:59.03#ibcon#about to read 5, iclass 7, count 0 2006.203.07:53:59.03#ibcon#read 5, iclass 7, count 0 2006.203.07:53:59.03#ibcon#about to read 6, iclass 7, count 0 2006.203.07:53:59.03#ibcon#read 6, iclass 7, count 0 2006.203.07:53:59.03#ibcon#end of sib2, iclass 7, count 0 2006.203.07:53:59.03#ibcon#*mode == 0, iclass 7, count 0 2006.203.07:53:59.03#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.203.07:53:59.03#ibcon#[26=FRQ=02,572.99\r\n] 2006.203.07:53:59.03#ibcon#*before write, iclass 7, count 0 2006.203.07:53:59.03#ibcon#enter sib2, iclass 7, count 0 2006.203.07:53:59.03#ibcon#flushed, iclass 7, count 0 2006.203.07:53:59.03#ibcon#about to write, iclass 7, count 0 2006.203.07:53:59.03#ibcon#wrote, iclass 7, count 0 2006.203.07:53:59.03#ibcon#about to read 3, iclass 7, count 0 2006.203.07:53:59.07#ibcon#read 3, iclass 7, count 0 2006.203.07:53:59.07#ibcon#about to read 4, iclass 7, count 0 2006.203.07:53:59.07#ibcon#read 4, iclass 7, count 0 2006.203.07:53:59.07#ibcon#about to read 5, iclass 7, count 0 2006.203.07:53:59.07#ibcon#read 5, iclass 7, count 0 2006.203.07:53:59.07#ibcon#about to read 6, iclass 7, count 0 2006.203.07:53:59.07#ibcon#read 6, iclass 7, count 0 2006.203.07:53:59.07#ibcon#end of sib2, iclass 7, count 0 2006.203.07:53:59.07#ibcon#*after write, iclass 7, count 0 2006.203.07:53:59.07#ibcon#*before return 0, iclass 7, count 0 2006.203.07:53:59.07#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.203.07:53:59.07#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.203.07:53:59.07#ibcon#about to clear, iclass 7 cls_cnt 0 2006.203.07:53:59.07#ibcon#cleared, iclass 7 cls_cnt 0 2006.203.07:53:59.07$vc4f8/va=2,7 2006.203.07:53:59.07#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.203.07:53:59.07#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.203.07:53:59.07#ibcon#ireg 11 cls_cnt 2 2006.203.07:53:59.07#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.203.07:53:59.14#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.203.07:53:59.14#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.203.07:53:59.14#ibcon#enter wrdev, iclass 11, count 2 2006.203.07:53:59.14#ibcon#first serial, iclass 11, count 2 2006.203.07:53:59.14#ibcon#enter sib2, iclass 11, count 2 2006.203.07:53:59.14#ibcon#flushed, iclass 11, count 2 2006.203.07:53:59.14#ibcon#about to write, iclass 11, count 2 2006.203.07:53:59.14#ibcon#wrote, iclass 11, count 2 2006.203.07:53:59.14#ibcon#about to read 3, iclass 11, count 2 2006.203.07:53:59.15#ibcon#read 3, iclass 11, count 2 2006.203.07:53:59.15#ibcon#about to read 4, iclass 11, count 2 2006.203.07:53:59.15#ibcon#read 4, iclass 11, count 2 2006.203.07:53:59.15#ibcon#about to read 5, iclass 11, count 2 2006.203.07:53:59.15#ibcon#read 5, iclass 11, count 2 2006.203.07:53:59.15#ibcon#about to read 6, iclass 11, count 2 2006.203.07:53:59.15#ibcon#read 6, iclass 11, count 2 2006.203.07:53:59.15#ibcon#end of sib2, iclass 11, count 2 2006.203.07:53:59.15#ibcon#*mode == 0, iclass 11, count 2 2006.203.07:53:59.15#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.203.07:53:59.15#ibcon#[25=AT02-07\r\n] 2006.203.07:53:59.15#ibcon#*before write, iclass 11, count 2 2006.203.07:53:59.15#ibcon#enter sib2, iclass 11, count 2 2006.203.07:53:59.15#ibcon#flushed, iclass 11, count 2 2006.203.07:53:59.15#ibcon#about to write, iclass 11, count 2 2006.203.07:53:59.15#ibcon#wrote, iclass 11, count 2 2006.203.07:53:59.15#ibcon#about to read 3, iclass 11, count 2 2006.203.07:53:59.18#ibcon#read 3, iclass 11, count 2 2006.203.07:53:59.18#ibcon#about to read 4, iclass 11, count 2 2006.203.07:53:59.18#ibcon#read 4, iclass 11, count 2 2006.203.07:53:59.18#ibcon#about to read 5, iclass 11, count 2 2006.203.07:53:59.18#ibcon#read 5, iclass 11, count 2 2006.203.07:53:59.18#ibcon#about to read 6, iclass 11, count 2 2006.203.07:53:59.18#ibcon#read 6, iclass 11, count 2 2006.203.07:53:59.18#ibcon#end of sib2, iclass 11, count 2 2006.203.07:53:59.18#ibcon#*after write, iclass 11, count 2 2006.203.07:53:59.18#ibcon#*before return 0, iclass 11, count 2 2006.203.07:53:59.18#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.203.07:53:59.18#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.203.07:53:59.18#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.203.07:53:59.18#ibcon#ireg 7 cls_cnt 0 2006.203.07:53:59.18#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.203.07:53:59.30#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.203.07:53:59.30#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.203.07:53:59.30#ibcon#enter wrdev, iclass 11, count 0 2006.203.07:53:59.30#ibcon#first serial, iclass 11, count 0 2006.203.07:53:59.30#ibcon#enter sib2, iclass 11, count 0 2006.203.07:53:59.30#ibcon#flushed, iclass 11, count 0 2006.203.07:53:59.30#ibcon#about to write, iclass 11, count 0 2006.203.07:53:59.30#ibcon#wrote, iclass 11, count 0 2006.203.07:53:59.30#ibcon#about to read 3, iclass 11, count 0 2006.203.07:53:59.32#ibcon#read 3, iclass 11, count 0 2006.203.07:53:59.32#ibcon#about to read 4, iclass 11, count 0 2006.203.07:53:59.32#ibcon#read 4, iclass 11, count 0 2006.203.07:53:59.32#ibcon#about to read 5, iclass 11, count 0 2006.203.07:53:59.32#ibcon#read 5, iclass 11, count 0 2006.203.07:53:59.32#ibcon#about to read 6, iclass 11, count 0 2006.203.07:53:59.32#ibcon#read 6, iclass 11, count 0 2006.203.07:53:59.32#ibcon#end of sib2, iclass 11, count 0 2006.203.07:53:59.32#ibcon#*mode == 0, iclass 11, count 0 2006.203.07:53:59.32#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.203.07:53:59.32#ibcon#[25=USB\r\n] 2006.203.07:53:59.32#ibcon#*before write, iclass 11, count 0 2006.203.07:53:59.32#ibcon#enter sib2, iclass 11, count 0 2006.203.07:53:59.32#ibcon#flushed, iclass 11, count 0 2006.203.07:53:59.32#ibcon#about to write, iclass 11, count 0 2006.203.07:53:59.32#ibcon#wrote, iclass 11, count 0 2006.203.07:53:59.32#ibcon#about to read 3, iclass 11, count 0 2006.203.07:53:59.35#ibcon#read 3, iclass 11, count 0 2006.203.07:53:59.35#ibcon#about to read 4, iclass 11, count 0 2006.203.07:53:59.35#ibcon#read 4, iclass 11, count 0 2006.203.07:53:59.35#ibcon#about to read 5, iclass 11, count 0 2006.203.07:53:59.35#ibcon#read 5, iclass 11, count 0 2006.203.07:53:59.35#ibcon#about to read 6, iclass 11, count 0 2006.203.07:53:59.35#ibcon#read 6, iclass 11, count 0 2006.203.07:53:59.35#ibcon#end of sib2, iclass 11, count 0 2006.203.07:53:59.35#ibcon#*after write, iclass 11, count 0 2006.203.07:53:59.35#ibcon#*before return 0, iclass 11, count 0 2006.203.07:53:59.35#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.203.07:53:59.35#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.203.07:53:59.35#ibcon#about to clear, iclass 11 cls_cnt 0 2006.203.07:53:59.35#ibcon#cleared, iclass 11 cls_cnt 0 2006.203.07:53:59.35$vc4f8/valo=3,672.99 2006.203.07:53:59.35#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.203.07:53:59.35#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.203.07:53:59.35#ibcon#ireg 17 cls_cnt 0 2006.203.07:53:59.35#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.203.07:53:59.35#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.203.07:53:59.35#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.203.07:53:59.35#ibcon#enter wrdev, iclass 13, count 0 2006.203.07:53:59.35#ibcon#first serial, iclass 13, count 0 2006.203.07:53:59.35#ibcon#enter sib2, iclass 13, count 0 2006.203.07:53:59.35#ibcon#flushed, iclass 13, count 0 2006.203.07:53:59.35#ibcon#about to write, iclass 13, count 0 2006.203.07:53:59.35#ibcon#wrote, iclass 13, count 0 2006.203.07:53:59.35#ibcon#about to read 3, iclass 13, count 0 2006.203.07:53:59.37#ibcon#read 3, iclass 13, count 0 2006.203.07:53:59.37#ibcon#about to read 4, iclass 13, count 0 2006.203.07:53:59.37#ibcon#read 4, iclass 13, count 0 2006.203.07:53:59.37#ibcon#about to read 5, iclass 13, count 0 2006.203.07:53:59.37#ibcon#read 5, iclass 13, count 0 2006.203.07:53:59.37#ibcon#about to read 6, iclass 13, count 0 2006.203.07:53:59.37#ibcon#read 6, iclass 13, count 0 2006.203.07:53:59.37#ibcon#end of sib2, iclass 13, count 0 2006.203.07:53:59.37#ibcon#*mode == 0, iclass 13, count 0 2006.203.07:53:59.37#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.203.07:53:59.37#ibcon#[26=FRQ=03,672.99\r\n] 2006.203.07:53:59.37#ibcon#*before write, iclass 13, count 0 2006.203.07:53:59.37#ibcon#enter sib2, iclass 13, count 0 2006.203.07:53:59.37#ibcon#flushed, iclass 13, count 0 2006.203.07:53:59.37#ibcon#about to write, iclass 13, count 0 2006.203.07:53:59.37#ibcon#wrote, iclass 13, count 0 2006.203.07:53:59.37#ibcon#about to read 3, iclass 13, count 0 2006.203.07:53:59.41#ibcon#read 3, iclass 13, count 0 2006.203.07:53:59.41#ibcon#about to read 4, iclass 13, count 0 2006.203.07:53:59.41#ibcon#read 4, iclass 13, count 0 2006.203.07:53:59.41#ibcon#about to read 5, iclass 13, count 0 2006.203.07:53:59.41#ibcon#read 5, iclass 13, count 0 2006.203.07:53:59.41#ibcon#about to read 6, iclass 13, count 0 2006.203.07:53:59.41#ibcon#read 6, iclass 13, count 0 2006.203.07:53:59.41#ibcon#end of sib2, iclass 13, count 0 2006.203.07:53:59.41#ibcon#*after write, iclass 13, count 0 2006.203.07:53:59.41#ibcon#*before return 0, iclass 13, count 0 2006.203.07:53:59.41#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.203.07:53:59.41#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.203.07:53:59.41#ibcon#about to clear, iclass 13 cls_cnt 0 2006.203.07:53:59.41#ibcon#cleared, iclass 13 cls_cnt 0 2006.203.07:53:59.41$vc4f8/va=3,8 2006.203.07:53:59.41#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.203.07:53:59.41#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.203.07:53:59.41#ibcon#ireg 11 cls_cnt 2 2006.203.07:53:59.41#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.203.07:53:59.48#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.203.07:53:59.48#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.203.07:53:59.48#ibcon#enter wrdev, iclass 15, count 2 2006.203.07:53:59.48#ibcon#first serial, iclass 15, count 2 2006.203.07:53:59.48#ibcon#enter sib2, iclass 15, count 2 2006.203.07:53:59.48#ibcon#flushed, iclass 15, count 2 2006.203.07:53:59.48#ibcon#about to write, iclass 15, count 2 2006.203.07:53:59.48#ibcon#wrote, iclass 15, count 2 2006.203.07:53:59.48#ibcon#about to read 3, iclass 15, count 2 2006.203.07:53:59.49#ibcon#read 3, iclass 15, count 2 2006.203.07:53:59.49#ibcon#about to read 4, iclass 15, count 2 2006.203.07:53:59.49#ibcon#read 4, iclass 15, count 2 2006.203.07:53:59.49#ibcon#about to read 5, iclass 15, count 2 2006.203.07:53:59.49#ibcon#read 5, iclass 15, count 2 2006.203.07:53:59.49#ibcon#about to read 6, iclass 15, count 2 2006.203.07:53:59.49#ibcon#read 6, iclass 15, count 2 2006.203.07:53:59.49#ibcon#end of sib2, iclass 15, count 2 2006.203.07:53:59.49#ibcon#*mode == 0, iclass 15, count 2 2006.203.07:53:59.49#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.203.07:53:59.49#ibcon#[25=AT03-08\r\n] 2006.203.07:53:59.49#ibcon#*before write, iclass 15, count 2 2006.203.07:53:59.49#ibcon#enter sib2, iclass 15, count 2 2006.203.07:53:59.49#ibcon#flushed, iclass 15, count 2 2006.203.07:53:59.49#ibcon#about to write, iclass 15, count 2 2006.203.07:53:59.49#ibcon#wrote, iclass 15, count 2 2006.203.07:53:59.49#ibcon#about to read 3, iclass 15, count 2 2006.203.07:53:59.52#ibcon#read 3, iclass 15, count 2 2006.203.07:53:59.52#ibcon#about to read 4, iclass 15, count 2 2006.203.07:53:59.52#ibcon#read 4, iclass 15, count 2 2006.203.07:53:59.52#ibcon#about to read 5, iclass 15, count 2 2006.203.07:53:59.52#ibcon#read 5, iclass 15, count 2 2006.203.07:53:59.52#ibcon#about to read 6, iclass 15, count 2 2006.203.07:53:59.52#ibcon#read 6, iclass 15, count 2 2006.203.07:53:59.52#ibcon#end of sib2, iclass 15, count 2 2006.203.07:53:59.52#ibcon#*after write, iclass 15, count 2 2006.203.07:53:59.52#ibcon#*before return 0, iclass 15, count 2 2006.203.07:53:59.52#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.203.07:53:59.52#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.203.07:53:59.52#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.203.07:53:59.52#ibcon#ireg 7 cls_cnt 0 2006.203.07:53:59.52#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.203.07:53:59.64#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.203.07:53:59.64#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.203.07:53:59.64#ibcon#enter wrdev, iclass 15, count 0 2006.203.07:53:59.64#ibcon#first serial, iclass 15, count 0 2006.203.07:53:59.64#ibcon#enter sib2, iclass 15, count 0 2006.203.07:53:59.64#ibcon#flushed, iclass 15, count 0 2006.203.07:53:59.64#ibcon#about to write, iclass 15, count 0 2006.203.07:53:59.64#ibcon#wrote, iclass 15, count 0 2006.203.07:53:59.64#ibcon#about to read 3, iclass 15, count 0 2006.203.07:53:59.66#ibcon#read 3, iclass 15, count 0 2006.203.07:53:59.66#ibcon#about to read 4, iclass 15, count 0 2006.203.07:53:59.66#ibcon#read 4, iclass 15, count 0 2006.203.07:53:59.66#ibcon#about to read 5, iclass 15, count 0 2006.203.07:53:59.66#ibcon#read 5, iclass 15, count 0 2006.203.07:53:59.66#ibcon#about to read 6, iclass 15, count 0 2006.203.07:53:59.66#ibcon#read 6, iclass 15, count 0 2006.203.07:53:59.66#ibcon#end of sib2, iclass 15, count 0 2006.203.07:53:59.66#ibcon#*mode == 0, iclass 15, count 0 2006.203.07:53:59.66#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.203.07:53:59.66#ibcon#[25=USB\r\n] 2006.203.07:53:59.66#ibcon#*before write, iclass 15, count 0 2006.203.07:53:59.66#ibcon#enter sib2, iclass 15, count 0 2006.203.07:53:59.66#ibcon#flushed, iclass 15, count 0 2006.203.07:53:59.66#ibcon#about to write, iclass 15, count 0 2006.203.07:53:59.66#ibcon#wrote, iclass 15, count 0 2006.203.07:53:59.66#ibcon#about to read 3, iclass 15, count 0 2006.203.07:53:59.69#ibcon#read 3, iclass 15, count 0 2006.203.07:53:59.69#ibcon#about to read 4, iclass 15, count 0 2006.203.07:53:59.69#ibcon#read 4, iclass 15, count 0 2006.203.07:53:59.69#ibcon#about to read 5, iclass 15, count 0 2006.203.07:53:59.69#ibcon#read 5, iclass 15, count 0 2006.203.07:53:59.69#ibcon#about to read 6, iclass 15, count 0 2006.203.07:53:59.69#ibcon#read 6, iclass 15, count 0 2006.203.07:53:59.69#ibcon#end of sib2, iclass 15, count 0 2006.203.07:53:59.69#ibcon#*after write, iclass 15, count 0 2006.203.07:53:59.69#ibcon#*before return 0, iclass 15, count 0 2006.203.07:53:59.69#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.203.07:53:59.69#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.203.07:53:59.69#ibcon#about to clear, iclass 15 cls_cnt 0 2006.203.07:53:59.69#ibcon#cleared, iclass 15 cls_cnt 0 2006.203.07:53:59.69$vc4f8/valo=4,832.99 2006.203.07:53:59.69#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.203.07:53:59.69#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.203.07:53:59.69#ibcon#ireg 17 cls_cnt 0 2006.203.07:53:59.69#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.203.07:53:59.69#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.203.07:53:59.69#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.203.07:53:59.69#ibcon#enter wrdev, iclass 17, count 0 2006.203.07:53:59.69#ibcon#first serial, iclass 17, count 0 2006.203.07:53:59.69#ibcon#enter sib2, iclass 17, count 0 2006.203.07:53:59.69#ibcon#flushed, iclass 17, count 0 2006.203.07:53:59.69#ibcon#about to write, iclass 17, count 0 2006.203.07:53:59.69#ibcon#wrote, iclass 17, count 0 2006.203.07:53:59.69#ibcon#about to read 3, iclass 17, count 0 2006.203.07:53:59.71#ibcon#read 3, iclass 17, count 0 2006.203.07:53:59.71#ibcon#about to read 4, iclass 17, count 0 2006.203.07:53:59.71#ibcon#read 4, iclass 17, count 0 2006.203.07:53:59.71#ibcon#about to read 5, iclass 17, count 0 2006.203.07:53:59.71#ibcon#read 5, iclass 17, count 0 2006.203.07:53:59.71#ibcon#about to read 6, iclass 17, count 0 2006.203.07:53:59.71#ibcon#read 6, iclass 17, count 0 2006.203.07:53:59.71#ibcon#end of sib2, iclass 17, count 0 2006.203.07:53:59.71#ibcon#*mode == 0, iclass 17, count 0 2006.203.07:53:59.71#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.203.07:53:59.71#ibcon#[26=FRQ=04,832.99\r\n] 2006.203.07:53:59.71#ibcon#*before write, iclass 17, count 0 2006.203.07:53:59.71#ibcon#enter sib2, iclass 17, count 0 2006.203.07:53:59.71#ibcon#flushed, iclass 17, count 0 2006.203.07:53:59.71#ibcon#about to write, iclass 17, count 0 2006.203.07:53:59.71#ibcon#wrote, iclass 17, count 0 2006.203.07:53:59.71#ibcon#about to read 3, iclass 17, count 0 2006.203.07:53:59.75#ibcon#read 3, iclass 17, count 0 2006.203.07:53:59.75#ibcon#about to read 4, iclass 17, count 0 2006.203.07:53:59.75#ibcon#read 4, iclass 17, count 0 2006.203.07:53:59.75#ibcon#about to read 5, iclass 17, count 0 2006.203.07:53:59.75#ibcon#read 5, iclass 17, count 0 2006.203.07:53:59.75#ibcon#about to read 6, iclass 17, count 0 2006.203.07:53:59.75#ibcon#read 6, iclass 17, count 0 2006.203.07:53:59.75#ibcon#end of sib2, iclass 17, count 0 2006.203.07:53:59.75#ibcon#*after write, iclass 17, count 0 2006.203.07:53:59.75#ibcon#*before return 0, iclass 17, count 0 2006.203.07:53:59.75#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.203.07:53:59.75#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.203.07:53:59.75#ibcon#about to clear, iclass 17 cls_cnt 0 2006.203.07:53:59.75#ibcon#cleared, iclass 17 cls_cnt 0 2006.203.07:53:59.75$vc4f8/va=4,7 2006.203.07:53:59.75#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.203.07:53:59.75#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.203.07:53:59.75#ibcon#ireg 11 cls_cnt 2 2006.203.07:53:59.75#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.203.07:53:59.81#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.203.07:53:59.81#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.203.07:53:59.81#ibcon#enter wrdev, iclass 19, count 2 2006.203.07:53:59.81#ibcon#first serial, iclass 19, count 2 2006.203.07:53:59.81#ibcon#enter sib2, iclass 19, count 2 2006.203.07:53:59.81#ibcon#flushed, iclass 19, count 2 2006.203.07:53:59.81#ibcon#about to write, iclass 19, count 2 2006.203.07:53:59.81#ibcon#wrote, iclass 19, count 2 2006.203.07:53:59.81#ibcon#about to read 3, iclass 19, count 2 2006.203.07:53:59.83#ibcon#read 3, iclass 19, count 2 2006.203.07:53:59.83#ibcon#about to read 4, iclass 19, count 2 2006.203.07:53:59.83#ibcon#read 4, iclass 19, count 2 2006.203.07:53:59.83#ibcon#about to read 5, iclass 19, count 2 2006.203.07:53:59.83#ibcon#read 5, iclass 19, count 2 2006.203.07:53:59.83#ibcon#about to read 6, iclass 19, count 2 2006.203.07:53:59.83#ibcon#read 6, iclass 19, count 2 2006.203.07:53:59.83#ibcon#end of sib2, iclass 19, count 2 2006.203.07:53:59.83#ibcon#*mode == 0, iclass 19, count 2 2006.203.07:53:59.83#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.203.07:53:59.83#ibcon#[25=AT04-07\r\n] 2006.203.07:53:59.83#ibcon#*before write, iclass 19, count 2 2006.203.07:53:59.83#ibcon#enter sib2, iclass 19, count 2 2006.203.07:53:59.83#ibcon#flushed, iclass 19, count 2 2006.203.07:53:59.83#ibcon#about to write, iclass 19, count 2 2006.203.07:53:59.83#ibcon#wrote, iclass 19, count 2 2006.203.07:53:59.83#ibcon#about to read 3, iclass 19, count 2 2006.203.07:53:59.86#ibcon#read 3, iclass 19, count 2 2006.203.07:53:59.86#ibcon#about to read 4, iclass 19, count 2 2006.203.07:53:59.86#ibcon#read 4, iclass 19, count 2 2006.203.07:53:59.86#ibcon#about to read 5, iclass 19, count 2 2006.203.07:53:59.86#ibcon#read 5, iclass 19, count 2 2006.203.07:53:59.86#ibcon#about to read 6, iclass 19, count 2 2006.203.07:53:59.86#ibcon#read 6, iclass 19, count 2 2006.203.07:53:59.86#ibcon#end of sib2, iclass 19, count 2 2006.203.07:53:59.86#ibcon#*after write, iclass 19, count 2 2006.203.07:53:59.86#ibcon#*before return 0, iclass 19, count 2 2006.203.07:53:59.86#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.203.07:53:59.86#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.203.07:53:59.86#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.203.07:53:59.86#ibcon#ireg 7 cls_cnt 0 2006.203.07:53:59.86#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.203.07:53:59.98#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.203.07:53:59.98#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.203.07:53:59.98#ibcon#enter wrdev, iclass 19, count 0 2006.203.07:53:59.98#ibcon#first serial, iclass 19, count 0 2006.203.07:53:59.98#ibcon#enter sib2, iclass 19, count 0 2006.203.07:53:59.98#ibcon#flushed, iclass 19, count 0 2006.203.07:53:59.98#ibcon#about to write, iclass 19, count 0 2006.203.07:53:59.98#ibcon#wrote, iclass 19, count 0 2006.203.07:53:59.98#ibcon#about to read 3, iclass 19, count 0 2006.203.07:54:00.00#ibcon#read 3, iclass 19, count 0 2006.203.07:54:00.00#ibcon#about to read 4, iclass 19, count 0 2006.203.07:54:00.00#ibcon#read 4, iclass 19, count 0 2006.203.07:54:00.00#ibcon#about to read 5, iclass 19, count 0 2006.203.07:54:00.00#ibcon#read 5, iclass 19, count 0 2006.203.07:54:00.00#ibcon#about to read 6, iclass 19, count 0 2006.203.07:54:00.00#ibcon#read 6, iclass 19, count 0 2006.203.07:54:00.00#ibcon#end of sib2, iclass 19, count 0 2006.203.07:54:00.00#ibcon#*mode == 0, iclass 19, count 0 2006.203.07:54:00.00#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.203.07:54:00.00#ibcon#[25=USB\r\n] 2006.203.07:54:00.00#ibcon#*before write, iclass 19, count 0 2006.203.07:54:00.00#ibcon#enter sib2, iclass 19, count 0 2006.203.07:54:00.00#ibcon#flushed, iclass 19, count 0 2006.203.07:54:00.00#ibcon#about to write, iclass 19, count 0 2006.203.07:54:00.00#ibcon#wrote, iclass 19, count 0 2006.203.07:54:00.00#ibcon#about to read 3, iclass 19, count 0 2006.203.07:54:00.03#ibcon#read 3, iclass 19, count 0 2006.203.07:54:00.03#ibcon#about to read 4, iclass 19, count 0 2006.203.07:54:00.03#ibcon#read 4, iclass 19, count 0 2006.203.07:54:00.03#ibcon#about to read 5, iclass 19, count 0 2006.203.07:54:00.03#ibcon#read 5, iclass 19, count 0 2006.203.07:54:00.03#ibcon#about to read 6, iclass 19, count 0 2006.203.07:54:00.03#ibcon#read 6, iclass 19, count 0 2006.203.07:54:00.03#ibcon#end of sib2, iclass 19, count 0 2006.203.07:54:00.03#ibcon#*after write, iclass 19, count 0 2006.203.07:54:00.03#ibcon#*before return 0, iclass 19, count 0 2006.203.07:54:00.03#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.203.07:54:00.03#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.203.07:54:00.03#ibcon#about to clear, iclass 19 cls_cnt 0 2006.203.07:54:00.03#ibcon#cleared, iclass 19 cls_cnt 0 2006.203.07:54:00.03$vc4f8/valo=5,652.99 2006.203.07:54:00.03#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.203.07:54:00.03#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.203.07:54:00.03#ibcon#ireg 17 cls_cnt 0 2006.203.07:54:00.03#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.203.07:54:00.03#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.203.07:54:00.03#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.203.07:54:00.03#ibcon#enter wrdev, iclass 21, count 0 2006.203.07:54:00.03#ibcon#first serial, iclass 21, count 0 2006.203.07:54:00.03#ibcon#enter sib2, iclass 21, count 0 2006.203.07:54:00.03#ibcon#flushed, iclass 21, count 0 2006.203.07:54:00.03#ibcon#about to write, iclass 21, count 0 2006.203.07:54:00.03#ibcon#wrote, iclass 21, count 0 2006.203.07:54:00.03#ibcon#about to read 3, iclass 21, count 0 2006.203.07:54:00.05#ibcon#read 3, iclass 21, count 0 2006.203.07:54:00.05#ibcon#about to read 4, iclass 21, count 0 2006.203.07:54:00.05#ibcon#read 4, iclass 21, count 0 2006.203.07:54:00.05#ibcon#about to read 5, iclass 21, count 0 2006.203.07:54:00.05#ibcon#read 5, iclass 21, count 0 2006.203.07:54:00.05#ibcon#about to read 6, iclass 21, count 0 2006.203.07:54:00.05#ibcon#read 6, iclass 21, count 0 2006.203.07:54:00.05#ibcon#end of sib2, iclass 21, count 0 2006.203.07:54:00.05#ibcon#*mode == 0, iclass 21, count 0 2006.203.07:54:00.05#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.203.07:54:00.05#ibcon#[26=FRQ=05,652.99\r\n] 2006.203.07:54:00.05#ibcon#*before write, iclass 21, count 0 2006.203.07:54:00.05#ibcon#enter sib2, iclass 21, count 0 2006.203.07:54:00.05#ibcon#flushed, iclass 21, count 0 2006.203.07:54:00.05#ibcon#about to write, iclass 21, count 0 2006.203.07:54:00.05#ibcon#wrote, iclass 21, count 0 2006.203.07:54:00.05#ibcon#about to read 3, iclass 21, count 0 2006.203.07:54:00.09#ibcon#read 3, iclass 21, count 0 2006.203.07:54:00.09#ibcon#about to read 4, iclass 21, count 0 2006.203.07:54:00.09#ibcon#read 4, iclass 21, count 0 2006.203.07:54:00.09#ibcon#about to read 5, iclass 21, count 0 2006.203.07:54:00.09#ibcon#read 5, iclass 21, count 0 2006.203.07:54:00.09#ibcon#about to read 6, iclass 21, count 0 2006.203.07:54:00.09#ibcon#read 6, iclass 21, count 0 2006.203.07:54:00.09#ibcon#end of sib2, iclass 21, count 0 2006.203.07:54:00.09#ibcon#*after write, iclass 21, count 0 2006.203.07:54:00.09#ibcon#*before return 0, iclass 21, count 0 2006.203.07:54:00.09#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.203.07:54:00.09#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.203.07:54:00.09#ibcon#about to clear, iclass 21 cls_cnt 0 2006.203.07:54:00.09#ibcon#cleared, iclass 21 cls_cnt 0 2006.203.07:54:00.09$vc4f8/va=5,7 2006.203.07:54:00.09#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.203.07:54:00.09#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.203.07:54:00.09#ibcon#ireg 11 cls_cnt 2 2006.203.07:54:00.09#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.203.07:54:00.16#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.203.07:54:00.16#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.203.07:54:00.16#ibcon#enter wrdev, iclass 23, count 2 2006.203.07:54:00.16#ibcon#first serial, iclass 23, count 2 2006.203.07:54:00.16#ibcon#enter sib2, iclass 23, count 2 2006.203.07:54:00.16#ibcon#flushed, iclass 23, count 2 2006.203.07:54:00.16#ibcon#about to write, iclass 23, count 2 2006.203.07:54:00.16#ibcon#wrote, iclass 23, count 2 2006.203.07:54:00.16#ibcon#about to read 3, iclass 23, count 2 2006.203.07:54:00.17#ibcon#read 3, iclass 23, count 2 2006.203.07:54:00.17#ibcon#about to read 4, iclass 23, count 2 2006.203.07:54:00.17#ibcon#read 4, iclass 23, count 2 2006.203.07:54:00.17#ibcon#about to read 5, iclass 23, count 2 2006.203.07:54:00.17#ibcon#read 5, iclass 23, count 2 2006.203.07:54:00.17#ibcon#about to read 6, iclass 23, count 2 2006.203.07:54:00.17#ibcon#read 6, iclass 23, count 2 2006.203.07:54:00.17#ibcon#end of sib2, iclass 23, count 2 2006.203.07:54:00.17#ibcon#*mode == 0, iclass 23, count 2 2006.203.07:54:00.17#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.203.07:54:00.17#ibcon#[25=AT05-07\r\n] 2006.203.07:54:00.17#ibcon#*before write, iclass 23, count 2 2006.203.07:54:00.17#ibcon#enter sib2, iclass 23, count 2 2006.203.07:54:00.17#ibcon#flushed, iclass 23, count 2 2006.203.07:54:00.17#ibcon#about to write, iclass 23, count 2 2006.203.07:54:00.17#ibcon#wrote, iclass 23, count 2 2006.203.07:54:00.17#ibcon#about to read 3, iclass 23, count 2 2006.203.07:54:00.20#ibcon#read 3, iclass 23, count 2 2006.203.07:54:00.20#ibcon#about to read 4, iclass 23, count 2 2006.203.07:54:00.20#ibcon#read 4, iclass 23, count 2 2006.203.07:54:00.20#ibcon#about to read 5, iclass 23, count 2 2006.203.07:54:00.20#ibcon#read 5, iclass 23, count 2 2006.203.07:54:00.20#ibcon#about to read 6, iclass 23, count 2 2006.203.07:54:00.20#ibcon#read 6, iclass 23, count 2 2006.203.07:54:00.20#ibcon#end of sib2, iclass 23, count 2 2006.203.07:54:00.20#ibcon#*after write, iclass 23, count 2 2006.203.07:54:00.20#ibcon#*before return 0, iclass 23, count 2 2006.203.07:54:00.20#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.203.07:54:00.20#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.203.07:54:00.20#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.203.07:54:00.20#ibcon#ireg 7 cls_cnt 0 2006.203.07:54:00.20#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.203.07:54:00.32#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.203.07:54:00.32#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.203.07:54:00.32#ibcon#enter wrdev, iclass 23, count 0 2006.203.07:54:00.32#ibcon#first serial, iclass 23, count 0 2006.203.07:54:00.32#ibcon#enter sib2, iclass 23, count 0 2006.203.07:54:00.32#ibcon#flushed, iclass 23, count 0 2006.203.07:54:00.32#ibcon#about to write, iclass 23, count 0 2006.203.07:54:00.32#ibcon#wrote, iclass 23, count 0 2006.203.07:54:00.32#ibcon#about to read 3, iclass 23, count 0 2006.203.07:54:00.34#ibcon#read 3, iclass 23, count 0 2006.203.07:54:00.34#ibcon#about to read 4, iclass 23, count 0 2006.203.07:54:00.34#ibcon#read 4, iclass 23, count 0 2006.203.07:54:00.34#ibcon#about to read 5, iclass 23, count 0 2006.203.07:54:00.34#ibcon#read 5, iclass 23, count 0 2006.203.07:54:00.34#ibcon#about to read 6, iclass 23, count 0 2006.203.07:54:00.34#ibcon#read 6, iclass 23, count 0 2006.203.07:54:00.34#ibcon#end of sib2, iclass 23, count 0 2006.203.07:54:00.34#ibcon#*mode == 0, iclass 23, count 0 2006.203.07:54:00.34#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.203.07:54:00.34#ibcon#[25=USB\r\n] 2006.203.07:54:00.34#ibcon#*before write, iclass 23, count 0 2006.203.07:54:00.34#ibcon#enter sib2, iclass 23, count 0 2006.203.07:54:00.34#ibcon#flushed, iclass 23, count 0 2006.203.07:54:00.34#ibcon#about to write, iclass 23, count 0 2006.203.07:54:00.34#ibcon#wrote, iclass 23, count 0 2006.203.07:54:00.34#ibcon#about to read 3, iclass 23, count 0 2006.203.07:54:00.37#ibcon#read 3, iclass 23, count 0 2006.203.07:54:00.37#ibcon#about to read 4, iclass 23, count 0 2006.203.07:54:00.37#ibcon#read 4, iclass 23, count 0 2006.203.07:54:00.37#ibcon#about to read 5, iclass 23, count 0 2006.203.07:54:00.37#ibcon#read 5, iclass 23, count 0 2006.203.07:54:00.37#ibcon#about to read 6, iclass 23, count 0 2006.203.07:54:00.37#ibcon#read 6, iclass 23, count 0 2006.203.07:54:00.37#ibcon#end of sib2, iclass 23, count 0 2006.203.07:54:00.37#ibcon#*after write, iclass 23, count 0 2006.203.07:54:00.37#ibcon#*before return 0, iclass 23, count 0 2006.203.07:54:00.37#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.203.07:54:00.37#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.203.07:54:00.37#ibcon#about to clear, iclass 23 cls_cnt 0 2006.203.07:54:00.37#ibcon#cleared, iclass 23 cls_cnt 0 2006.203.07:54:00.37$vc4f8/valo=6,772.99 2006.203.07:54:00.37#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.203.07:54:00.37#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.203.07:54:00.37#ibcon#ireg 17 cls_cnt 0 2006.203.07:54:00.37#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.203.07:54:00.37#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.203.07:54:00.37#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.203.07:54:00.37#ibcon#enter wrdev, iclass 25, count 0 2006.203.07:54:00.37#ibcon#first serial, iclass 25, count 0 2006.203.07:54:00.37#ibcon#enter sib2, iclass 25, count 0 2006.203.07:54:00.37#ibcon#flushed, iclass 25, count 0 2006.203.07:54:00.37#ibcon#about to write, iclass 25, count 0 2006.203.07:54:00.37#ibcon#wrote, iclass 25, count 0 2006.203.07:54:00.37#ibcon#about to read 3, iclass 25, count 0 2006.203.07:54:00.39#ibcon#read 3, iclass 25, count 0 2006.203.07:54:00.39#ibcon#about to read 4, iclass 25, count 0 2006.203.07:54:00.39#ibcon#read 4, iclass 25, count 0 2006.203.07:54:00.39#ibcon#about to read 5, iclass 25, count 0 2006.203.07:54:00.39#ibcon#read 5, iclass 25, count 0 2006.203.07:54:00.39#ibcon#about to read 6, iclass 25, count 0 2006.203.07:54:00.39#ibcon#read 6, iclass 25, count 0 2006.203.07:54:00.39#ibcon#end of sib2, iclass 25, count 0 2006.203.07:54:00.39#ibcon#*mode == 0, iclass 25, count 0 2006.203.07:54:00.39#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.203.07:54:00.39#ibcon#[26=FRQ=06,772.99\r\n] 2006.203.07:54:00.39#ibcon#*before write, iclass 25, count 0 2006.203.07:54:00.39#ibcon#enter sib2, iclass 25, count 0 2006.203.07:54:00.39#ibcon#flushed, iclass 25, count 0 2006.203.07:54:00.39#ibcon#about to write, iclass 25, count 0 2006.203.07:54:00.39#ibcon#wrote, iclass 25, count 0 2006.203.07:54:00.39#ibcon#about to read 3, iclass 25, count 0 2006.203.07:54:00.43#ibcon#read 3, iclass 25, count 0 2006.203.07:54:00.43#ibcon#about to read 4, iclass 25, count 0 2006.203.07:54:00.43#ibcon#read 4, iclass 25, count 0 2006.203.07:54:00.43#ibcon#about to read 5, iclass 25, count 0 2006.203.07:54:00.43#ibcon#read 5, iclass 25, count 0 2006.203.07:54:00.43#ibcon#about to read 6, iclass 25, count 0 2006.203.07:54:00.43#ibcon#read 6, iclass 25, count 0 2006.203.07:54:00.43#ibcon#end of sib2, iclass 25, count 0 2006.203.07:54:00.43#ibcon#*after write, iclass 25, count 0 2006.203.07:54:00.43#ibcon#*before return 0, iclass 25, count 0 2006.203.07:54:00.43#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.203.07:54:00.43#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.203.07:54:00.43#ibcon#about to clear, iclass 25 cls_cnt 0 2006.203.07:54:00.43#ibcon#cleared, iclass 25 cls_cnt 0 2006.203.07:54:00.43$vc4f8/va=6,6 2006.203.07:54:00.43#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.203.07:54:00.43#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.203.07:54:00.43#ibcon#ireg 11 cls_cnt 2 2006.203.07:54:00.43#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.203.07:54:00.50#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.203.07:54:00.50#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.203.07:54:00.50#ibcon#enter wrdev, iclass 27, count 2 2006.203.07:54:00.50#ibcon#first serial, iclass 27, count 2 2006.203.07:54:00.50#ibcon#enter sib2, iclass 27, count 2 2006.203.07:54:00.50#ibcon#flushed, iclass 27, count 2 2006.203.07:54:00.50#ibcon#about to write, iclass 27, count 2 2006.203.07:54:00.50#ibcon#wrote, iclass 27, count 2 2006.203.07:54:00.50#ibcon#about to read 3, iclass 27, count 2 2006.203.07:54:00.51#ibcon#read 3, iclass 27, count 2 2006.203.07:54:00.51#ibcon#about to read 4, iclass 27, count 2 2006.203.07:54:00.51#ibcon#read 4, iclass 27, count 2 2006.203.07:54:00.51#ibcon#about to read 5, iclass 27, count 2 2006.203.07:54:00.51#ibcon#read 5, iclass 27, count 2 2006.203.07:54:00.51#ibcon#about to read 6, iclass 27, count 2 2006.203.07:54:00.51#ibcon#read 6, iclass 27, count 2 2006.203.07:54:00.51#ibcon#end of sib2, iclass 27, count 2 2006.203.07:54:00.51#ibcon#*mode == 0, iclass 27, count 2 2006.203.07:54:00.51#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.203.07:54:00.51#ibcon#[25=AT06-06\r\n] 2006.203.07:54:00.51#ibcon#*before write, iclass 27, count 2 2006.203.07:54:00.51#ibcon#enter sib2, iclass 27, count 2 2006.203.07:54:00.51#ibcon#flushed, iclass 27, count 2 2006.203.07:54:00.51#ibcon#about to write, iclass 27, count 2 2006.203.07:54:00.51#ibcon#wrote, iclass 27, count 2 2006.203.07:54:00.51#ibcon#about to read 3, iclass 27, count 2 2006.203.07:54:00.54#ibcon#read 3, iclass 27, count 2 2006.203.07:54:00.54#ibcon#about to read 4, iclass 27, count 2 2006.203.07:54:00.54#ibcon#read 4, iclass 27, count 2 2006.203.07:54:00.54#ibcon#about to read 5, iclass 27, count 2 2006.203.07:54:00.54#ibcon#read 5, iclass 27, count 2 2006.203.07:54:00.54#ibcon#about to read 6, iclass 27, count 2 2006.203.07:54:00.54#ibcon#read 6, iclass 27, count 2 2006.203.07:54:00.54#ibcon#end of sib2, iclass 27, count 2 2006.203.07:54:00.54#ibcon#*after write, iclass 27, count 2 2006.203.07:54:00.54#ibcon#*before return 0, iclass 27, count 2 2006.203.07:54:00.54#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.203.07:54:00.54#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.203.07:54:00.54#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.203.07:54:00.54#ibcon#ireg 7 cls_cnt 0 2006.203.07:54:00.54#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.203.07:54:00.66#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.203.07:54:00.66#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.203.07:54:00.66#ibcon#enter wrdev, iclass 27, count 0 2006.203.07:54:00.66#ibcon#first serial, iclass 27, count 0 2006.203.07:54:00.66#ibcon#enter sib2, iclass 27, count 0 2006.203.07:54:00.66#ibcon#flushed, iclass 27, count 0 2006.203.07:54:00.66#ibcon#about to write, iclass 27, count 0 2006.203.07:54:00.66#ibcon#wrote, iclass 27, count 0 2006.203.07:54:00.66#ibcon#about to read 3, iclass 27, count 0 2006.203.07:54:00.68#ibcon#read 3, iclass 27, count 0 2006.203.07:54:00.68#ibcon#about to read 4, iclass 27, count 0 2006.203.07:54:00.68#ibcon#read 4, iclass 27, count 0 2006.203.07:54:00.68#ibcon#about to read 5, iclass 27, count 0 2006.203.07:54:00.68#ibcon#read 5, iclass 27, count 0 2006.203.07:54:00.68#ibcon#about to read 6, iclass 27, count 0 2006.203.07:54:00.68#ibcon#read 6, iclass 27, count 0 2006.203.07:54:00.68#ibcon#end of sib2, iclass 27, count 0 2006.203.07:54:00.68#ibcon#*mode == 0, iclass 27, count 0 2006.203.07:54:00.68#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.203.07:54:00.68#ibcon#[25=USB\r\n] 2006.203.07:54:00.68#ibcon#*before write, iclass 27, count 0 2006.203.07:54:00.68#ibcon#enter sib2, iclass 27, count 0 2006.203.07:54:00.68#ibcon#flushed, iclass 27, count 0 2006.203.07:54:00.68#ibcon#about to write, iclass 27, count 0 2006.203.07:54:00.68#ibcon#wrote, iclass 27, count 0 2006.203.07:54:00.68#ibcon#about to read 3, iclass 27, count 0 2006.203.07:54:00.71#ibcon#read 3, iclass 27, count 0 2006.203.07:54:00.71#ibcon#about to read 4, iclass 27, count 0 2006.203.07:54:00.71#ibcon#read 4, iclass 27, count 0 2006.203.07:54:00.71#ibcon#about to read 5, iclass 27, count 0 2006.203.07:54:00.71#ibcon#read 5, iclass 27, count 0 2006.203.07:54:00.71#ibcon#about to read 6, iclass 27, count 0 2006.203.07:54:00.71#ibcon#read 6, iclass 27, count 0 2006.203.07:54:00.71#ibcon#end of sib2, iclass 27, count 0 2006.203.07:54:00.71#ibcon#*after write, iclass 27, count 0 2006.203.07:54:00.71#ibcon#*before return 0, iclass 27, count 0 2006.203.07:54:00.71#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.203.07:54:00.71#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.203.07:54:00.71#ibcon#about to clear, iclass 27 cls_cnt 0 2006.203.07:54:00.71#ibcon#cleared, iclass 27 cls_cnt 0 2006.203.07:54:00.71$vc4f8/valo=7,832.99 2006.203.07:54:00.71#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.203.07:54:00.71#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.203.07:54:00.71#ibcon#ireg 17 cls_cnt 0 2006.203.07:54:00.71#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.203.07:54:00.71#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.203.07:54:00.71#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.203.07:54:00.71#ibcon#enter wrdev, iclass 29, count 0 2006.203.07:54:00.71#ibcon#first serial, iclass 29, count 0 2006.203.07:54:00.71#ibcon#enter sib2, iclass 29, count 0 2006.203.07:54:00.71#ibcon#flushed, iclass 29, count 0 2006.203.07:54:00.71#ibcon#about to write, iclass 29, count 0 2006.203.07:54:00.71#ibcon#wrote, iclass 29, count 0 2006.203.07:54:00.71#ibcon#about to read 3, iclass 29, count 0 2006.203.07:54:00.73#ibcon#read 3, iclass 29, count 0 2006.203.07:54:00.73#ibcon#about to read 4, iclass 29, count 0 2006.203.07:54:00.73#ibcon#read 4, iclass 29, count 0 2006.203.07:54:00.73#ibcon#about to read 5, iclass 29, count 0 2006.203.07:54:00.73#ibcon#read 5, iclass 29, count 0 2006.203.07:54:00.73#ibcon#about to read 6, iclass 29, count 0 2006.203.07:54:00.73#ibcon#read 6, iclass 29, count 0 2006.203.07:54:00.73#ibcon#end of sib2, iclass 29, count 0 2006.203.07:54:00.73#ibcon#*mode == 0, iclass 29, count 0 2006.203.07:54:00.73#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.203.07:54:00.73#ibcon#[26=FRQ=07,832.99\r\n] 2006.203.07:54:00.73#ibcon#*before write, iclass 29, count 0 2006.203.07:54:00.73#ibcon#enter sib2, iclass 29, count 0 2006.203.07:54:00.73#ibcon#flushed, iclass 29, count 0 2006.203.07:54:00.73#ibcon#about to write, iclass 29, count 0 2006.203.07:54:00.73#ibcon#wrote, iclass 29, count 0 2006.203.07:54:00.73#ibcon#about to read 3, iclass 29, count 0 2006.203.07:54:00.77#ibcon#read 3, iclass 29, count 0 2006.203.07:54:00.77#ibcon#about to read 4, iclass 29, count 0 2006.203.07:54:00.77#ibcon#read 4, iclass 29, count 0 2006.203.07:54:00.77#ibcon#about to read 5, iclass 29, count 0 2006.203.07:54:00.77#ibcon#read 5, iclass 29, count 0 2006.203.07:54:00.77#ibcon#about to read 6, iclass 29, count 0 2006.203.07:54:00.77#ibcon#read 6, iclass 29, count 0 2006.203.07:54:00.77#ibcon#end of sib2, iclass 29, count 0 2006.203.07:54:00.77#ibcon#*after write, iclass 29, count 0 2006.203.07:54:00.77#ibcon#*before return 0, iclass 29, count 0 2006.203.07:54:00.77#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.203.07:54:00.77#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.203.07:54:00.77#ibcon#about to clear, iclass 29 cls_cnt 0 2006.203.07:54:00.77#ibcon#cleared, iclass 29 cls_cnt 0 2006.203.07:54:00.77$vc4f8/va=7,7 2006.203.07:54:00.77#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.203.07:54:00.77#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.203.07:54:00.77#ibcon#ireg 11 cls_cnt 2 2006.203.07:54:00.77#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.203.07:54:00.84#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.203.07:54:00.84#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.203.07:54:00.84#ibcon#enter wrdev, iclass 31, count 2 2006.203.07:54:00.84#ibcon#first serial, iclass 31, count 2 2006.203.07:54:00.84#ibcon#enter sib2, iclass 31, count 2 2006.203.07:54:00.84#ibcon#flushed, iclass 31, count 2 2006.203.07:54:00.84#ibcon#about to write, iclass 31, count 2 2006.203.07:54:00.84#ibcon#wrote, iclass 31, count 2 2006.203.07:54:00.84#ibcon#about to read 3, iclass 31, count 2 2006.203.07:54:00.85#ibcon#read 3, iclass 31, count 2 2006.203.07:54:00.85#ibcon#about to read 4, iclass 31, count 2 2006.203.07:54:00.85#ibcon#read 4, iclass 31, count 2 2006.203.07:54:00.85#ibcon#about to read 5, iclass 31, count 2 2006.203.07:54:00.85#ibcon#read 5, iclass 31, count 2 2006.203.07:54:00.85#ibcon#about to read 6, iclass 31, count 2 2006.203.07:54:00.85#ibcon#read 6, iclass 31, count 2 2006.203.07:54:00.85#ibcon#end of sib2, iclass 31, count 2 2006.203.07:54:00.85#ibcon#*mode == 0, iclass 31, count 2 2006.203.07:54:00.85#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.203.07:54:00.85#ibcon#[25=AT07-07\r\n] 2006.203.07:54:00.85#ibcon#*before write, iclass 31, count 2 2006.203.07:54:00.85#ibcon#enter sib2, iclass 31, count 2 2006.203.07:54:00.85#ibcon#flushed, iclass 31, count 2 2006.203.07:54:00.85#ibcon#about to write, iclass 31, count 2 2006.203.07:54:00.85#ibcon#wrote, iclass 31, count 2 2006.203.07:54:00.85#ibcon#about to read 3, iclass 31, count 2 2006.203.07:54:00.88#ibcon#read 3, iclass 31, count 2 2006.203.07:54:00.88#ibcon#about to read 4, iclass 31, count 2 2006.203.07:54:00.88#ibcon#read 4, iclass 31, count 2 2006.203.07:54:00.88#ibcon#about to read 5, iclass 31, count 2 2006.203.07:54:00.88#ibcon#read 5, iclass 31, count 2 2006.203.07:54:00.88#ibcon#about to read 6, iclass 31, count 2 2006.203.07:54:00.88#ibcon#read 6, iclass 31, count 2 2006.203.07:54:00.88#ibcon#end of sib2, iclass 31, count 2 2006.203.07:54:00.88#ibcon#*after write, iclass 31, count 2 2006.203.07:54:00.88#ibcon#*before return 0, iclass 31, count 2 2006.203.07:54:00.88#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.203.07:54:00.88#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.203.07:54:00.88#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.203.07:54:00.88#ibcon#ireg 7 cls_cnt 0 2006.203.07:54:00.88#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.203.07:54:01.00#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.203.07:54:01.00#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.203.07:54:01.00#ibcon#enter wrdev, iclass 31, count 0 2006.203.07:54:01.00#ibcon#first serial, iclass 31, count 0 2006.203.07:54:01.00#ibcon#enter sib2, iclass 31, count 0 2006.203.07:54:01.00#ibcon#flushed, iclass 31, count 0 2006.203.07:54:01.00#ibcon#about to write, iclass 31, count 0 2006.203.07:54:01.00#ibcon#wrote, iclass 31, count 0 2006.203.07:54:01.00#ibcon#about to read 3, iclass 31, count 0 2006.203.07:54:01.02#ibcon#read 3, iclass 31, count 0 2006.203.07:54:01.02#ibcon#about to read 4, iclass 31, count 0 2006.203.07:54:01.02#ibcon#read 4, iclass 31, count 0 2006.203.07:54:01.02#ibcon#about to read 5, iclass 31, count 0 2006.203.07:54:01.02#ibcon#read 5, iclass 31, count 0 2006.203.07:54:01.02#ibcon#about to read 6, iclass 31, count 0 2006.203.07:54:01.02#ibcon#read 6, iclass 31, count 0 2006.203.07:54:01.02#ibcon#end of sib2, iclass 31, count 0 2006.203.07:54:01.02#ibcon#*mode == 0, iclass 31, count 0 2006.203.07:54:01.02#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.203.07:54:01.02#ibcon#[25=USB\r\n] 2006.203.07:54:01.02#ibcon#*before write, iclass 31, count 0 2006.203.07:54:01.02#ibcon#enter sib2, iclass 31, count 0 2006.203.07:54:01.02#ibcon#flushed, iclass 31, count 0 2006.203.07:54:01.02#ibcon#about to write, iclass 31, count 0 2006.203.07:54:01.02#ibcon#wrote, iclass 31, count 0 2006.203.07:54:01.02#ibcon#about to read 3, iclass 31, count 0 2006.203.07:54:01.05#ibcon#read 3, iclass 31, count 0 2006.203.07:54:01.05#ibcon#about to read 4, iclass 31, count 0 2006.203.07:54:01.05#ibcon#read 4, iclass 31, count 0 2006.203.07:54:01.05#ibcon#about to read 5, iclass 31, count 0 2006.203.07:54:01.05#ibcon#read 5, iclass 31, count 0 2006.203.07:54:01.05#ibcon#about to read 6, iclass 31, count 0 2006.203.07:54:01.05#ibcon#read 6, iclass 31, count 0 2006.203.07:54:01.05#ibcon#end of sib2, iclass 31, count 0 2006.203.07:54:01.05#ibcon#*after write, iclass 31, count 0 2006.203.07:54:01.05#ibcon#*before return 0, iclass 31, count 0 2006.203.07:54:01.05#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.203.07:54:01.05#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.203.07:54:01.05#ibcon#about to clear, iclass 31 cls_cnt 0 2006.203.07:54:01.05#ibcon#cleared, iclass 31 cls_cnt 0 2006.203.07:54:01.05$vc4f8/valo=8,852.99 2006.203.07:54:01.05#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.203.07:54:01.05#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.203.07:54:01.05#ibcon#ireg 17 cls_cnt 0 2006.203.07:54:01.05#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.203.07:54:01.05#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.203.07:54:01.05#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.203.07:54:01.05#ibcon#enter wrdev, iclass 33, count 0 2006.203.07:54:01.05#ibcon#first serial, iclass 33, count 0 2006.203.07:54:01.05#ibcon#enter sib2, iclass 33, count 0 2006.203.07:54:01.05#ibcon#flushed, iclass 33, count 0 2006.203.07:54:01.05#ibcon#about to write, iclass 33, count 0 2006.203.07:54:01.05#ibcon#wrote, iclass 33, count 0 2006.203.07:54:01.05#ibcon#about to read 3, iclass 33, count 0 2006.203.07:54:01.07#ibcon#read 3, iclass 33, count 0 2006.203.07:54:01.07#ibcon#about to read 4, iclass 33, count 0 2006.203.07:54:01.07#ibcon#read 4, iclass 33, count 0 2006.203.07:54:01.07#ibcon#about to read 5, iclass 33, count 0 2006.203.07:54:01.07#ibcon#read 5, iclass 33, count 0 2006.203.07:54:01.07#ibcon#about to read 6, iclass 33, count 0 2006.203.07:54:01.07#ibcon#read 6, iclass 33, count 0 2006.203.07:54:01.07#ibcon#end of sib2, iclass 33, count 0 2006.203.07:54:01.07#ibcon#*mode == 0, iclass 33, count 0 2006.203.07:54:01.07#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.203.07:54:01.07#ibcon#[26=FRQ=08,852.99\r\n] 2006.203.07:54:01.07#ibcon#*before write, iclass 33, count 0 2006.203.07:54:01.07#ibcon#enter sib2, iclass 33, count 0 2006.203.07:54:01.07#ibcon#flushed, iclass 33, count 0 2006.203.07:54:01.07#ibcon#about to write, iclass 33, count 0 2006.203.07:54:01.07#ibcon#wrote, iclass 33, count 0 2006.203.07:54:01.07#ibcon#about to read 3, iclass 33, count 0 2006.203.07:54:01.11#ibcon#read 3, iclass 33, count 0 2006.203.07:54:01.11#ibcon#about to read 4, iclass 33, count 0 2006.203.07:54:01.11#ibcon#read 4, iclass 33, count 0 2006.203.07:54:01.11#ibcon#about to read 5, iclass 33, count 0 2006.203.07:54:01.11#ibcon#read 5, iclass 33, count 0 2006.203.07:54:01.11#ibcon#about to read 6, iclass 33, count 0 2006.203.07:54:01.11#ibcon#read 6, iclass 33, count 0 2006.203.07:54:01.11#ibcon#end of sib2, iclass 33, count 0 2006.203.07:54:01.11#ibcon#*after write, iclass 33, count 0 2006.203.07:54:01.11#ibcon#*before return 0, iclass 33, count 0 2006.203.07:54:01.11#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.203.07:54:01.11#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.203.07:54:01.11#ibcon#about to clear, iclass 33 cls_cnt 0 2006.203.07:54:01.11#ibcon#cleared, iclass 33 cls_cnt 0 2006.203.07:54:01.11$vc4f8/va=8,6 2006.203.07:54:01.11#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.203.07:54:01.11#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.203.07:54:01.11#ibcon#ireg 11 cls_cnt 2 2006.203.07:54:01.11#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.203.07:54:01.17#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.203.07:54:01.17#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.203.07:54:01.17#ibcon#enter wrdev, iclass 35, count 2 2006.203.07:54:01.17#ibcon#first serial, iclass 35, count 2 2006.203.07:54:01.17#ibcon#enter sib2, iclass 35, count 2 2006.203.07:54:01.17#ibcon#flushed, iclass 35, count 2 2006.203.07:54:01.17#ibcon#about to write, iclass 35, count 2 2006.203.07:54:01.17#ibcon#wrote, iclass 35, count 2 2006.203.07:54:01.17#ibcon#about to read 3, iclass 35, count 2 2006.203.07:54:01.19#ibcon#read 3, iclass 35, count 2 2006.203.07:54:01.19#ibcon#about to read 4, iclass 35, count 2 2006.203.07:54:01.19#ibcon#read 4, iclass 35, count 2 2006.203.07:54:01.19#ibcon#about to read 5, iclass 35, count 2 2006.203.07:54:01.19#ibcon#read 5, iclass 35, count 2 2006.203.07:54:01.19#ibcon#about to read 6, iclass 35, count 2 2006.203.07:54:01.19#ibcon#read 6, iclass 35, count 2 2006.203.07:54:01.19#ibcon#end of sib2, iclass 35, count 2 2006.203.07:54:01.19#ibcon#*mode == 0, iclass 35, count 2 2006.203.07:54:01.19#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.203.07:54:01.19#ibcon#[25=AT08-06\r\n] 2006.203.07:54:01.19#ibcon#*before write, iclass 35, count 2 2006.203.07:54:01.19#ibcon#enter sib2, iclass 35, count 2 2006.203.07:54:01.19#ibcon#flushed, iclass 35, count 2 2006.203.07:54:01.19#ibcon#about to write, iclass 35, count 2 2006.203.07:54:01.19#ibcon#wrote, iclass 35, count 2 2006.203.07:54:01.19#ibcon#about to read 3, iclass 35, count 2 2006.203.07:54:01.22#ibcon#read 3, iclass 35, count 2 2006.203.07:54:01.22#ibcon#about to read 4, iclass 35, count 2 2006.203.07:54:01.22#ibcon#read 4, iclass 35, count 2 2006.203.07:54:01.22#ibcon#about to read 5, iclass 35, count 2 2006.203.07:54:01.22#ibcon#read 5, iclass 35, count 2 2006.203.07:54:01.22#ibcon#about to read 6, iclass 35, count 2 2006.203.07:54:01.22#ibcon#read 6, iclass 35, count 2 2006.203.07:54:01.22#ibcon#end of sib2, iclass 35, count 2 2006.203.07:54:01.22#ibcon#*after write, iclass 35, count 2 2006.203.07:54:01.22#ibcon#*before return 0, iclass 35, count 2 2006.203.07:54:01.22#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.203.07:54:01.22#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.203.07:54:01.22#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.203.07:54:01.22#ibcon#ireg 7 cls_cnt 0 2006.203.07:54:01.22#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.203.07:54:01.34#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.203.07:54:01.34#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.203.07:54:01.34#ibcon#enter wrdev, iclass 35, count 0 2006.203.07:54:01.34#ibcon#first serial, iclass 35, count 0 2006.203.07:54:01.34#ibcon#enter sib2, iclass 35, count 0 2006.203.07:54:01.34#ibcon#flushed, iclass 35, count 0 2006.203.07:54:01.34#ibcon#about to write, iclass 35, count 0 2006.203.07:54:01.34#ibcon#wrote, iclass 35, count 0 2006.203.07:54:01.34#ibcon#about to read 3, iclass 35, count 0 2006.203.07:54:01.36#ibcon#read 3, iclass 35, count 0 2006.203.07:54:01.36#ibcon#about to read 4, iclass 35, count 0 2006.203.07:54:01.36#ibcon#read 4, iclass 35, count 0 2006.203.07:54:01.36#ibcon#about to read 5, iclass 35, count 0 2006.203.07:54:01.36#ibcon#read 5, iclass 35, count 0 2006.203.07:54:01.36#ibcon#about to read 6, iclass 35, count 0 2006.203.07:54:01.36#ibcon#read 6, iclass 35, count 0 2006.203.07:54:01.36#ibcon#end of sib2, iclass 35, count 0 2006.203.07:54:01.36#ibcon#*mode == 0, iclass 35, count 0 2006.203.07:54:01.36#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.203.07:54:01.36#ibcon#[25=USB\r\n] 2006.203.07:54:01.36#ibcon#*before write, iclass 35, count 0 2006.203.07:54:01.36#ibcon#enter sib2, iclass 35, count 0 2006.203.07:54:01.36#ibcon#flushed, iclass 35, count 0 2006.203.07:54:01.36#ibcon#about to write, iclass 35, count 0 2006.203.07:54:01.36#ibcon#wrote, iclass 35, count 0 2006.203.07:54:01.36#ibcon#about to read 3, iclass 35, count 0 2006.203.07:54:01.39#ibcon#read 3, iclass 35, count 0 2006.203.07:54:01.39#ibcon#about to read 4, iclass 35, count 0 2006.203.07:54:01.39#ibcon#read 4, iclass 35, count 0 2006.203.07:54:01.39#ibcon#about to read 5, iclass 35, count 0 2006.203.07:54:01.39#ibcon#read 5, iclass 35, count 0 2006.203.07:54:01.39#ibcon#about to read 6, iclass 35, count 0 2006.203.07:54:01.39#ibcon#read 6, iclass 35, count 0 2006.203.07:54:01.39#ibcon#end of sib2, iclass 35, count 0 2006.203.07:54:01.39#ibcon#*after write, iclass 35, count 0 2006.203.07:54:01.39#ibcon#*before return 0, iclass 35, count 0 2006.203.07:54:01.39#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.203.07:54:01.39#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.203.07:54:01.39#ibcon#about to clear, iclass 35 cls_cnt 0 2006.203.07:54:01.39#ibcon#cleared, iclass 35 cls_cnt 0 2006.203.07:54:01.39$vc4f8/vblo=1,632.99 2006.203.07:54:01.39#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.203.07:54:01.39#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.203.07:54:01.39#ibcon#ireg 17 cls_cnt 0 2006.203.07:54:01.39#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.203.07:54:01.39#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.203.07:54:01.39#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.203.07:54:01.39#ibcon#enter wrdev, iclass 37, count 0 2006.203.07:54:01.39#ibcon#first serial, iclass 37, count 0 2006.203.07:54:01.39#ibcon#enter sib2, iclass 37, count 0 2006.203.07:54:01.39#ibcon#flushed, iclass 37, count 0 2006.203.07:54:01.39#ibcon#about to write, iclass 37, count 0 2006.203.07:54:01.39#ibcon#wrote, iclass 37, count 0 2006.203.07:54:01.39#ibcon#about to read 3, iclass 37, count 0 2006.203.07:54:01.41#ibcon#read 3, iclass 37, count 0 2006.203.07:54:01.41#ibcon#about to read 4, iclass 37, count 0 2006.203.07:54:01.41#ibcon#read 4, iclass 37, count 0 2006.203.07:54:01.41#ibcon#about to read 5, iclass 37, count 0 2006.203.07:54:01.41#ibcon#read 5, iclass 37, count 0 2006.203.07:54:01.41#ibcon#about to read 6, iclass 37, count 0 2006.203.07:54:01.41#ibcon#read 6, iclass 37, count 0 2006.203.07:54:01.41#ibcon#end of sib2, iclass 37, count 0 2006.203.07:54:01.41#ibcon#*mode == 0, iclass 37, count 0 2006.203.07:54:01.41#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.203.07:54:01.41#ibcon#[28=FRQ=01,632.99\r\n] 2006.203.07:54:01.41#ibcon#*before write, iclass 37, count 0 2006.203.07:54:01.41#ibcon#enter sib2, iclass 37, count 0 2006.203.07:54:01.41#ibcon#flushed, iclass 37, count 0 2006.203.07:54:01.41#ibcon#about to write, iclass 37, count 0 2006.203.07:54:01.41#ibcon#wrote, iclass 37, count 0 2006.203.07:54:01.41#ibcon#about to read 3, iclass 37, count 0 2006.203.07:54:01.45#ibcon#read 3, iclass 37, count 0 2006.203.07:54:01.45#ibcon#about to read 4, iclass 37, count 0 2006.203.07:54:01.45#ibcon#read 4, iclass 37, count 0 2006.203.07:54:01.45#ibcon#about to read 5, iclass 37, count 0 2006.203.07:54:01.45#ibcon#read 5, iclass 37, count 0 2006.203.07:54:01.45#ibcon#about to read 6, iclass 37, count 0 2006.203.07:54:01.45#ibcon#read 6, iclass 37, count 0 2006.203.07:54:01.45#ibcon#end of sib2, iclass 37, count 0 2006.203.07:54:01.45#ibcon#*after write, iclass 37, count 0 2006.203.07:54:01.45#ibcon#*before return 0, iclass 37, count 0 2006.203.07:54:01.45#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.203.07:54:01.45#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.203.07:54:01.45#ibcon#about to clear, iclass 37 cls_cnt 0 2006.203.07:54:01.45#ibcon#cleared, iclass 37 cls_cnt 0 2006.203.07:54:01.45$vc4f8/vb=1,4 2006.203.07:54:01.45#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.203.07:54:01.45#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.203.07:54:01.45#ibcon#ireg 11 cls_cnt 2 2006.203.07:54:01.45#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.203.07:54:01.45#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.203.07:54:01.45#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.203.07:54:01.45#ibcon#enter wrdev, iclass 39, count 2 2006.203.07:54:01.45#ibcon#first serial, iclass 39, count 2 2006.203.07:54:01.45#ibcon#enter sib2, iclass 39, count 2 2006.203.07:54:01.45#ibcon#flushed, iclass 39, count 2 2006.203.07:54:01.45#ibcon#about to write, iclass 39, count 2 2006.203.07:54:01.45#ibcon#wrote, iclass 39, count 2 2006.203.07:54:01.45#ibcon#about to read 3, iclass 39, count 2 2006.203.07:54:01.47#ibcon#read 3, iclass 39, count 2 2006.203.07:54:01.47#ibcon#about to read 4, iclass 39, count 2 2006.203.07:54:01.47#ibcon#read 4, iclass 39, count 2 2006.203.07:54:01.47#ibcon#about to read 5, iclass 39, count 2 2006.203.07:54:01.47#ibcon#read 5, iclass 39, count 2 2006.203.07:54:01.47#ibcon#about to read 6, iclass 39, count 2 2006.203.07:54:01.47#ibcon#read 6, iclass 39, count 2 2006.203.07:54:01.47#ibcon#end of sib2, iclass 39, count 2 2006.203.07:54:01.47#ibcon#*mode == 0, iclass 39, count 2 2006.203.07:54:01.47#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.203.07:54:01.47#ibcon#[27=AT01-04\r\n] 2006.203.07:54:01.47#ibcon#*before write, iclass 39, count 2 2006.203.07:54:01.47#ibcon#enter sib2, iclass 39, count 2 2006.203.07:54:01.47#ibcon#flushed, iclass 39, count 2 2006.203.07:54:01.47#ibcon#about to write, iclass 39, count 2 2006.203.07:54:01.47#ibcon#wrote, iclass 39, count 2 2006.203.07:54:01.47#ibcon#about to read 3, iclass 39, count 2 2006.203.07:54:01.50#ibcon#read 3, iclass 39, count 2 2006.203.07:54:01.50#ibcon#about to read 4, iclass 39, count 2 2006.203.07:54:01.50#ibcon#read 4, iclass 39, count 2 2006.203.07:54:01.50#ibcon#about to read 5, iclass 39, count 2 2006.203.07:54:01.50#ibcon#read 5, iclass 39, count 2 2006.203.07:54:01.50#ibcon#about to read 6, iclass 39, count 2 2006.203.07:54:01.50#ibcon#read 6, iclass 39, count 2 2006.203.07:54:01.50#ibcon#end of sib2, iclass 39, count 2 2006.203.07:54:01.50#ibcon#*after write, iclass 39, count 2 2006.203.07:54:01.50#ibcon#*before return 0, iclass 39, count 2 2006.203.07:54:01.50#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.203.07:54:01.50#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.203.07:54:01.50#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.203.07:54:01.50#ibcon#ireg 7 cls_cnt 0 2006.203.07:54:01.50#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.203.07:54:01.62#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.203.07:54:01.62#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.203.07:54:01.62#ibcon#enter wrdev, iclass 39, count 0 2006.203.07:54:01.62#ibcon#first serial, iclass 39, count 0 2006.203.07:54:01.62#ibcon#enter sib2, iclass 39, count 0 2006.203.07:54:01.62#ibcon#flushed, iclass 39, count 0 2006.203.07:54:01.62#ibcon#about to write, iclass 39, count 0 2006.203.07:54:01.62#ibcon#wrote, iclass 39, count 0 2006.203.07:54:01.62#ibcon#about to read 3, iclass 39, count 0 2006.203.07:54:01.64#ibcon#read 3, iclass 39, count 0 2006.203.07:54:01.64#ibcon#about to read 4, iclass 39, count 0 2006.203.07:54:01.64#ibcon#read 4, iclass 39, count 0 2006.203.07:54:01.64#ibcon#about to read 5, iclass 39, count 0 2006.203.07:54:01.64#ibcon#read 5, iclass 39, count 0 2006.203.07:54:01.64#ibcon#about to read 6, iclass 39, count 0 2006.203.07:54:01.64#ibcon#read 6, iclass 39, count 0 2006.203.07:54:01.64#ibcon#end of sib2, iclass 39, count 0 2006.203.07:54:01.64#ibcon#*mode == 0, iclass 39, count 0 2006.203.07:54:01.64#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.203.07:54:01.64#ibcon#[27=USB\r\n] 2006.203.07:54:01.64#ibcon#*before write, iclass 39, count 0 2006.203.07:54:01.64#ibcon#enter sib2, iclass 39, count 0 2006.203.07:54:01.64#ibcon#flushed, iclass 39, count 0 2006.203.07:54:01.64#ibcon#about to write, iclass 39, count 0 2006.203.07:54:01.64#ibcon#wrote, iclass 39, count 0 2006.203.07:54:01.64#ibcon#about to read 3, iclass 39, count 0 2006.203.07:54:01.67#ibcon#read 3, iclass 39, count 0 2006.203.07:54:01.67#ibcon#about to read 4, iclass 39, count 0 2006.203.07:54:01.67#ibcon#read 4, iclass 39, count 0 2006.203.07:54:01.67#ibcon#about to read 5, iclass 39, count 0 2006.203.07:54:01.67#ibcon#read 5, iclass 39, count 0 2006.203.07:54:01.67#ibcon#about to read 6, iclass 39, count 0 2006.203.07:54:01.67#ibcon#read 6, iclass 39, count 0 2006.203.07:54:01.67#ibcon#end of sib2, iclass 39, count 0 2006.203.07:54:01.67#ibcon#*after write, iclass 39, count 0 2006.203.07:54:01.67#ibcon#*before return 0, iclass 39, count 0 2006.203.07:54:01.67#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.203.07:54:01.67#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.203.07:54:01.67#ibcon#about to clear, iclass 39 cls_cnt 0 2006.203.07:54:01.67#ibcon#cleared, iclass 39 cls_cnt 0 2006.203.07:54:01.67$vc4f8/vblo=2,640.99 2006.203.07:54:01.67#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.203.07:54:01.67#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.203.07:54:01.67#ibcon#ireg 17 cls_cnt 0 2006.203.07:54:01.67#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.203.07:54:01.67#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.203.07:54:01.67#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.203.07:54:01.67#ibcon#enter wrdev, iclass 3, count 0 2006.203.07:54:01.67#ibcon#first serial, iclass 3, count 0 2006.203.07:54:01.67#ibcon#enter sib2, iclass 3, count 0 2006.203.07:54:01.67#ibcon#flushed, iclass 3, count 0 2006.203.07:54:01.67#ibcon#about to write, iclass 3, count 0 2006.203.07:54:01.67#ibcon#wrote, iclass 3, count 0 2006.203.07:54:01.67#ibcon#about to read 3, iclass 3, count 0 2006.203.07:54:01.69#ibcon#read 3, iclass 3, count 0 2006.203.07:54:01.69#ibcon#about to read 4, iclass 3, count 0 2006.203.07:54:01.69#ibcon#read 4, iclass 3, count 0 2006.203.07:54:01.69#ibcon#about to read 5, iclass 3, count 0 2006.203.07:54:01.69#ibcon#read 5, iclass 3, count 0 2006.203.07:54:01.69#ibcon#about to read 6, iclass 3, count 0 2006.203.07:54:01.69#ibcon#read 6, iclass 3, count 0 2006.203.07:54:01.69#ibcon#end of sib2, iclass 3, count 0 2006.203.07:54:01.69#ibcon#*mode == 0, iclass 3, count 0 2006.203.07:54:01.69#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.203.07:54:01.69#ibcon#[28=FRQ=02,640.99\r\n] 2006.203.07:54:01.69#ibcon#*before write, iclass 3, count 0 2006.203.07:54:01.69#ibcon#enter sib2, iclass 3, count 0 2006.203.07:54:01.69#ibcon#flushed, iclass 3, count 0 2006.203.07:54:01.69#ibcon#about to write, iclass 3, count 0 2006.203.07:54:01.69#ibcon#wrote, iclass 3, count 0 2006.203.07:54:01.69#ibcon#about to read 3, iclass 3, count 0 2006.203.07:54:01.73#ibcon#read 3, iclass 3, count 0 2006.203.07:54:01.73#ibcon#about to read 4, iclass 3, count 0 2006.203.07:54:01.73#ibcon#read 4, iclass 3, count 0 2006.203.07:54:01.73#ibcon#about to read 5, iclass 3, count 0 2006.203.07:54:01.73#ibcon#read 5, iclass 3, count 0 2006.203.07:54:01.73#ibcon#about to read 6, iclass 3, count 0 2006.203.07:54:01.73#ibcon#read 6, iclass 3, count 0 2006.203.07:54:01.73#ibcon#end of sib2, iclass 3, count 0 2006.203.07:54:01.73#ibcon#*after write, iclass 3, count 0 2006.203.07:54:01.73#ibcon#*before return 0, iclass 3, count 0 2006.203.07:54:01.73#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.203.07:54:01.73#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.203.07:54:01.73#ibcon#about to clear, iclass 3 cls_cnt 0 2006.203.07:54:01.73#ibcon#cleared, iclass 3 cls_cnt 0 2006.203.07:54:01.73$vc4f8/vb=2,4 2006.203.07:54:01.73#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.203.07:54:01.73#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.203.07:54:01.73#ibcon#ireg 11 cls_cnt 2 2006.203.07:54:01.73#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.203.07:54:01.80#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.203.07:54:01.80#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.203.07:54:01.80#ibcon#enter wrdev, iclass 5, count 2 2006.203.07:54:01.80#ibcon#first serial, iclass 5, count 2 2006.203.07:54:01.80#ibcon#enter sib2, iclass 5, count 2 2006.203.07:54:01.80#ibcon#flushed, iclass 5, count 2 2006.203.07:54:01.80#ibcon#about to write, iclass 5, count 2 2006.203.07:54:01.80#ibcon#wrote, iclass 5, count 2 2006.203.07:54:01.80#ibcon#about to read 3, iclass 5, count 2 2006.203.07:54:01.81#ibcon#read 3, iclass 5, count 2 2006.203.07:54:01.81#ibcon#about to read 4, iclass 5, count 2 2006.203.07:54:01.81#ibcon#read 4, iclass 5, count 2 2006.203.07:54:01.81#ibcon#about to read 5, iclass 5, count 2 2006.203.07:54:01.81#ibcon#read 5, iclass 5, count 2 2006.203.07:54:01.81#ibcon#about to read 6, iclass 5, count 2 2006.203.07:54:01.81#ibcon#read 6, iclass 5, count 2 2006.203.07:54:01.81#ibcon#end of sib2, iclass 5, count 2 2006.203.07:54:01.81#ibcon#*mode == 0, iclass 5, count 2 2006.203.07:54:01.81#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.203.07:54:01.81#ibcon#[27=AT02-04\r\n] 2006.203.07:54:01.81#ibcon#*before write, iclass 5, count 2 2006.203.07:54:01.81#ibcon#enter sib2, iclass 5, count 2 2006.203.07:54:01.81#ibcon#flushed, iclass 5, count 2 2006.203.07:54:01.81#ibcon#about to write, iclass 5, count 2 2006.203.07:54:01.81#ibcon#wrote, iclass 5, count 2 2006.203.07:54:01.81#ibcon#about to read 3, iclass 5, count 2 2006.203.07:54:01.84#ibcon#read 3, iclass 5, count 2 2006.203.07:54:01.84#ibcon#about to read 4, iclass 5, count 2 2006.203.07:54:01.84#ibcon#read 4, iclass 5, count 2 2006.203.07:54:01.84#ibcon#about to read 5, iclass 5, count 2 2006.203.07:54:01.84#ibcon#read 5, iclass 5, count 2 2006.203.07:54:01.84#ibcon#about to read 6, iclass 5, count 2 2006.203.07:54:01.84#ibcon#read 6, iclass 5, count 2 2006.203.07:54:01.84#ibcon#end of sib2, iclass 5, count 2 2006.203.07:54:01.84#ibcon#*after write, iclass 5, count 2 2006.203.07:54:01.84#ibcon#*before return 0, iclass 5, count 2 2006.203.07:54:01.84#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.203.07:54:01.84#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.203.07:54:01.84#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.203.07:54:01.84#ibcon#ireg 7 cls_cnt 0 2006.203.07:54:01.84#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.203.07:54:01.96#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.203.07:54:01.96#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.203.07:54:01.96#ibcon#enter wrdev, iclass 5, count 0 2006.203.07:54:01.96#ibcon#first serial, iclass 5, count 0 2006.203.07:54:01.96#ibcon#enter sib2, iclass 5, count 0 2006.203.07:54:01.96#ibcon#flushed, iclass 5, count 0 2006.203.07:54:01.96#ibcon#about to write, iclass 5, count 0 2006.203.07:54:01.96#ibcon#wrote, iclass 5, count 0 2006.203.07:54:01.96#ibcon#about to read 3, iclass 5, count 0 2006.203.07:54:01.98#ibcon#read 3, iclass 5, count 0 2006.203.07:54:01.98#ibcon#about to read 4, iclass 5, count 0 2006.203.07:54:01.98#ibcon#read 4, iclass 5, count 0 2006.203.07:54:01.98#ibcon#about to read 5, iclass 5, count 0 2006.203.07:54:01.98#ibcon#read 5, iclass 5, count 0 2006.203.07:54:01.98#ibcon#about to read 6, iclass 5, count 0 2006.203.07:54:01.98#ibcon#read 6, iclass 5, count 0 2006.203.07:54:01.98#ibcon#end of sib2, iclass 5, count 0 2006.203.07:54:01.98#ibcon#*mode == 0, iclass 5, count 0 2006.203.07:54:01.98#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.203.07:54:01.98#ibcon#[27=USB\r\n] 2006.203.07:54:01.98#ibcon#*before write, iclass 5, count 0 2006.203.07:54:01.98#ibcon#enter sib2, iclass 5, count 0 2006.203.07:54:01.98#ibcon#flushed, iclass 5, count 0 2006.203.07:54:01.98#ibcon#about to write, iclass 5, count 0 2006.203.07:54:01.98#ibcon#wrote, iclass 5, count 0 2006.203.07:54:01.98#ibcon#about to read 3, iclass 5, count 0 2006.203.07:54:02.01#ibcon#read 3, iclass 5, count 0 2006.203.07:54:02.01#ibcon#about to read 4, iclass 5, count 0 2006.203.07:54:02.01#ibcon#read 4, iclass 5, count 0 2006.203.07:54:02.01#ibcon#about to read 5, iclass 5, count 0 2006.203.07:54:02.01#ibcon#read 5, iclass 5, count 0 2006.203.07:54:02.01#ibcon#about to read 6, iclass 5, count 0 2006.203.07:54:02.01#ibcon#read 6, iclass 5, count 0 2006.203.07:54:02.01#ibcon#end of sib2, iclass 5, count 0 2006.203.07:54:02.01#ibcon#*after write, iclass 5, count 0 2006.203.07:54:02.01#ibcon#*before return 0, iclass 5, count 0 2006.203.07:54:02.01#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.203.07:54:02.01#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.203.07:54:02.01#ibcon#about to clear, iclass 5 cls_cnt 0 2006.203.07:54:02.01#ibcon#cleared, iclass 5 cls_cnt 0 2006.203.07:54:02.01$vc4f8/vblo=3,656.99 2006.203.07:54:02.01#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.203.07:54:02.01#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.203.07:54:02.01#ibcon#ireg 17 cls_cnt 0 2006.203.07:54:02.01#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.203.07:54:02.01#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.203.07:54:02.01#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.203.07:54:02.01#ibcon#enter wrdev, iclass 7, count 0 2006.203.07:54:02.01#ibcon#first serial, iclass 7, count 0 2006.203.07:54:02.01#ibcon#enter sib2, iclass 7, count 0 2006.203.07:54:02.01#ibcon#flushed, iclass 7, count 0 2006.203.07:54:02.01#ibcon#about to write, iclass 7, count 0 2006.203.07:54:02.01#ibcon#wrote, iclass 7, count 0 2006.203.07:54:02.01#ibcon#about to read 3, iclass 7, count 0 2006.203.07:54:02.03#ibcon#read 3, iclass 7, count 0 2006.203.07:54:02.03#ibcon#about to read 4, iclass 7, count 0 2006.203.07:54:02.03#ibcon#read 4, iclass 7, count 0 2006.203.07:54:02.03#ibcon#about to read 5, iclass 7, count 0 2006.203.07:54:02.03#ibcon#read 5, iclass 7, count 0 2006.203.07:54:02.03#ibcon#about to read 6, iclass 7, count 0 2006.203.07:54:02.03#ibcon#read 6, iclass 7, count 0 2006.203.07:54:02.03#ibcon#end of sib2, iclass 7, count 0 2006.203.07:54:02.03#ibcon#*mode == 0, iclass 7, count 0 2006.203.07:54:02.03#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.203.07:54:02.03#ibcon#[28=FRQ=03,656.99\r\n] 2006.203.07:54:02.03#ibcon#*before write, iclass 7, count 0 2006.203.07:54:02.03#ibcon#enter sib2, iclass 7, count 0 2006.203.07:54:02.03#ibcon#flushed, iclass 7, count 0 2006.203.07:54:02.03#ibcon#about to write, iclass 7, count 0 2006.203.07:54:02.03#ibcon#wrote, iclass 7, count 0 2006.203.07:54:02.03#ibcon#about to read 3, iclass 7, count 0 2006.203.07:54:02.07#ibcon#read 3, iclass 7, count 0 2006.203.07:54:02.07#ibcon#about to read 4, iclass 7, count 0 2006.203.07:54:02.07#ibcon#read 4, iclass 7, count 0 2006.203.07:54:02.07#ibcon#about to read 5, iclass 7, count 0 2006.203.07:54:02.07#ibcon#read 5, iclass 7, count 0 2006.203.07:54:02.07#ibcon#about to read 6, iclass 7, count 0 2006.203.07:54:02.07#ibcon#read 6, iclass 7, count 0 2006.203.07:54:02.07#ibcon#end of sib2, iclass 7, count 0 2006.203.07:54:02.07#ibcon#*after write, iclass 7, count 0 2006.203.07:54:02.07#ibcon#*before return 0, iclass 7, count 0 2006.203.07:54:02.07#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.203.07:54:02.07#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.203.07:54:02.07#ibcon#about to clear, iclass 7 cls_cnt 0 2006.203.07:54:02.07#ibcon#cleared, iclass 7 cls_cnt 0 2006.203.07:54:02.07$vc4f8/vb=3,4 2006.203.07:54:02.07#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.203.07:54:02.07#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.203.07:54:02.07#ibcon#ireg 11 cls_cnt 2 2006.203.07:54:02.07#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.203.07:54:02.13#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.203.07:54:02.13#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.203.07:54:02.13#ibcon#enter wrdev, iclass 11, count 2 2006.203.07:54:02.13#ibcon#first serial, iclass 11, count 2 2006.203.07:54:02.13#ibcon#enter sib2, iclass 11, count 2 2006.203.07:54:02.13#ibcon#flushed, iclass 11, count 2 2006.203.07:54:02.13#ibcon#about to write, iclass 11, count 2 2006.203.07:54:02.13#ibcon#wrote, iclass 11, count 2 2006.203.07:54:02.13#ibcon#about to read 3, iclass 11, count 2 2006.203.07:54:02.15#ibcon#read 3, iclass 11, count 2 2006.203.07:54:02.15#ibcon#about to read 4, iclass 11, count 2 2006.203.07:54:02.15#ibcon#read 4, iclass 11, count 2 2006.203.07:54:02.15#ibcon#about to read 5, iclass 11, count 2 2006.203.07:54:02.15#ibcon#read 5, iclass 11, count 2 2006.203.07:54:02.15#ibcon#about to read 6, iclass 11, count 2 2006.203.07:54:02.15#ibcon#read 6, iclass 11, count 2 2006.203.07:54:02.15#ibcon#end of sib2, iclass 11, count 2 2006.203.07:54:02.15#ibcon#*mode == 0, iclass 11, count 2 2006.203.07:54:02.15#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.203.07:54:02.15#ibcon#[27=AT03-04\r\n] 2006.203.07:54:02.15#ibcon#*before write, iclass 11, count 2 2006.203.07:54:02.15#ibcon#enter sib2, iclass 11, count 2 2006.203.07:54:02.15#ibcon#flushed, iclass 11, count 2 2006.203.07:54:02.15#ibcon#about to write, iclass 11, count 2 2006.203.07:54:02.15#ibcon#wrote, iclass 11, count 2 2006.203.07:54:02.15#ibcon#about to read 3, iclass 11, count 2 2006.203.07:54:02.18#ibcon#read 3, iclass 11, count 2 2006.203.07:54:02.18#ibcon#about to read 4, iclass 11, count 2 2006.203.07:54:02.18#ibcon#read 4, iclass 11, count 2 2006.203.07:54:02.18#ibcon#about to read 5, iclass 11, count 2 2006.203.07:54:02.18#ibcon#read 5, iclass 11, count 2 2006.203.07:54:02.18#ibcon#about to read 6, iclass 11, count 2 2006.203.07:54:02.18#ibcon#read 6, iclass 11, count 2 2006.203.07:54:02.18#ibcon#end of sib2, iclass 11, count 2 2006.203.07:54:02.18#ibcon#*after write, iclass 11, count 2 2006.203.07:54:02.18#ibcon#*before return 0, iclass 11, count 2 2006.203.07:54:02.18#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.203.07:54:02.18#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.203.07:54:02.18#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.203.07:54:02.18#ibcon#ireg 7 cls_cnt 0 2006.203.07:54:02.18#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.203.07:54:02.30#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.203.07:54:02.30#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.203.07:54:02.30#ibcon#enter wrdev, iclass 11, count 0 2006.203.07:54:02.30#ibcon#first serial, iclass 11, count 0 2006.203.07:54:02.30#ibcon#enter sib2, iclass 11, count 0 2006.203.07:54:02.30#ibcon#flushed, iclass 11, count 0 2006.203.07:54:02.30#ibcon#about to write, iclass 11, count 0 2006.203.07:54:02.30#ibcon#wrote, iclass 11, count 0 2006.203.07:54:02.30#ibcon#about to read 3, iclass 11, count 0 2006.203.07:54:02.32#ibcon#read 3, iclass 11, count 0 2006.203.07:54:02.32#ibcon#about to read 4, iclass 11, count 0 2006.203.07:54:02.32#ibcon#read 4, iclass 11, count 0 2006.203.07:54:02.32#ibcon#about to read 5, iclass 11, count 0 2006.203.07:54:02.32#ibcon#read 5, iclass 11, count 0 2006.203.07:54:02.32#ibcon#about to read 6, iclass 11, count 0 2006.203.07:54:02.32#ibcon#read 6, iclass 11, count 0 2006.203.07:54:02.32#ibcon#end of sib2, iclass 11, count 0 2006.203.07:54:02.32#ibcon#*mode == 0, iclass 11, count 0 2006.203.07:54:02.32#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.203.07:54:02.32#ibcon#[27=USB\r\n] 2006.203.07:54:02.32#ibcon#*before write, iclass 11, count 0 2006.203.07:54:02.32#ibcon#enter sib2, iclass 11, count 0 2006.203.07:54:02.32#ibcon#flushed, iclass 11, count 0 2006.203.07:54:02.32#ibcon#about to write, iclass 11, count 0 2006.203.07:54:02.32#ibcon#wrote, iclass 11, count 0 2006.203.07:54:02.32#ibcon#about to read 3, iclass 11, count 0 2006.203.07:54:02.35#ibcon#read 3, iclass 11, count 0 2006.203.07:54:02.35#ibcon#about to read 4, iclass 11, count 0 2006.203.07:54:02.35#ibcon#read 4, iclass 11, count 0 2006.203.07:54:02.35#ibcon#about to read 5, iclass 11, count 0 2006.203.07:54:02.35#ibcon#read 5, iclass 11, count 0 2006.203.07:54:02.35#ibcon#about to read 6, iclass 11, count 0 2006.203.07:54:02.35#ibcon#read 6, iclass 11, count 0 2006.203.07:54:02.35#ibcon#end of sib2, iclass 11, count 0 2006.203.07:54:02.35#ibcon#*after write, iclass 11, count 0 2006.203.07:54:02.35#ibcon#*before return 0, iclass 11, count 0 2006.203.07:54:02.35#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.203.07:54:02.35#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.203.07:54:02.35#ibcon#about to clear, iclass 11 cls_cnt 0 2006.203.07:54:02.35#ibcon#cleared, iclass 11 cls_cnt 0 2006.203.07:54:02.35$vc4f8/vblo=4,712.99 2006.203.07:54:02.35#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.203.07:54:02.35#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.203.07:54:02.35#ibcon#ireg 17 cls_cnt 0 2006.203.07:54:02.35#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.203.07:54:02.35#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.203.07:54:02.35#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.203.07:54:02.35#ibcon#enter wrdev, iclass 13, count 0 2006.203.07:54:02.35#ibcon#first serial, iclass 13, count 0 2006.203.07:54:02.35#ibcon#enter sib2, iclass 13, count 0 2006.203.07:54:02.35#ibcon#flushed, iclass 13, count 0 2006.203.07:54:02.35#ibcon#about to write, iclass 13, count 0 2006.203.07:54:02.35#ibcon#wrote, iclass 13, count 0 2006.203.07:54:02.35#ibcon#about to read 3, iclass 13, count 0 2006.203.07:54:02.37#ibcon#read 3, iclass 13, count 0 2006.203.07:54:02.37#ibcon#about to read 4, iclass 13, count 0 2006.203.07:54:02.37#ibcon#read 4, iclass 13, count 0 2006.203.07:54:02.37#ibcon#about to read 5, iclass 13, count 0 2006.203.07:54:02.37#ibcon#read 5, iclass 13, count 0 2006.203.07:54:02.37#ibcon#about to read 6, iclass 13, count 0 2006.203.07:54:02.37#ibcon#read 6, iclass 13, count 0 2006.203.07:54:02.37#ibcon#end of sib2, iclass 13, count 0 2006.203.07:54:02.37#ibcon#*mode == 0, iclass 13, count 0 2006.203.07:54:02.37#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.203.07:54:02.37#ibcon#[28=FRQ=04,712.99\r\n] 2006.203.07:54:02.37#ibcon#*before write, iclass 13, count 0 2006.203.07:54:02.37#ibcon#enter sib2, iclass 13, count 0 2006.203.07:54:02.37#ibcon#flushed, iclass 13, count 0 2006.203.07:54:02.37#ibcon#about to write, iclass 13, count 0 2006.203.07:54:02.37#ibcon#wrote, iclass 13, count 0 2006.203.07:54:02.37#ibcon#about to read 3, iclass 13, count 0 2006.203.07:54:02.41#ibcon#read 3, iclass 13, count 0 2006.203.07:54:02.41#ibcon#about to read 4, iclass 13, count 0 2006.203.07:54:02.41#ibcon#read 4, iclass 13, count 0 2006.203.07:54:02.41#ibcon#about to read 5, iclass 13, count 0 2006.203.07:54:02.41#ibcon#read 5, iclass 13, count 0 2006.203.07:54:02.41#ibcon#about to read 6, iclass 13, count 0 2006.203.07:54:02.41#ibcon#read 6, iclass 13, count 0 2006.203.07:54:02.41#ibcon#end of sib2, iclass 13, count 0 2006.203.07:54:02.41#ibcon#*after write, iclass 13, count 0 2006.203.07:54:02.41#ibcon#*before return 0, iclass 13, count 0 2006.203.07:54:02.41#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.203.07:54:02.41#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.203.07:54:02.41#ibcon#about to clear, iclass 13 cls_cnt 0 2006.203.07:54:02.41#ibcon#cleared, iclass 13 cls_cnt 0 2006.203.07:54:02.41$vc4f8/vb=4,4 2006.203.07:54:02.41#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.203.07:54:02.41#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.203.07:54:02.41#ibcon#ireg 11 cls_cnt 2 2006.203.07:54:02.41#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.203.07:54:02.48#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.203.07:54:02.48#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.203.07:54:02.48#ibcon#enter wrdev, iclass 15, count 2 2006.203.07:54:02.48#ibcon#first serial, iclass 15, count 2 2006.203.07:54:02.48#ibcon#enter sib2, iclass 15, count 2 2006.203.07:54:02.48#ibcon#flushed, iclass 15, count 2 2006.203.07:54:02.48#ibcon#about to write, iclass 15, count 2 2006.203.07:54:02.48#ibcon#wrote, iclass 15, count 2 2006.203.07:54:02.48#ibcon#about to read 3, iclass 15, count 2 2006.203.07:54:02.49#ibcon#read 3, iclass 15, count 2 2006.203.07:54:02.49#ibcon#about to read 4, iclass 15, count 2 2006.203.07:54:02.49#ibcon#read 4, iclass 15, count 2 2006.203.07:54:02.49#ibcon#about to read 5, iclass 15, count 2 2006.203.07:54:02.49#ibcon#read 5, iclass 15, count 2 2006.203.07:54:02.49#ibcon#about to read 6, iclass 15, count 2 2006.203.07:54:02.49#ibcon#read 6, iclass 15, count 2 2006.203.07:54:02.49#ibcon#end of sib2, iclass 15, count 2 2006.203.07:54:02.49#ibcon#*mode == 0, iclass 15, count 2 2006.203.07:54:02.49#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.203.07:54:02.49#ibcon#[27=AT04-04\r\n] 2006.203.07:54:02.49#ibcon#*before write, iclass 15, count 2 2006.203.07:54:02.49#ibcon#enter sib2, iclass 15, count 2 2006.203.07:54:02.49#ibcon#flushed, iclass 15, count 2 2006.203.07:54:02.49#ibcon#about to write, iclass 15, count 2 2006.203.07:54:02.49#ibcon#wrote, iclass 15, count 2 2006.203.07:54:02.49#ibcon#about to read 3, iclass 15, count 2 2006.203.07:54:02.52#ibcon#read 3, iclass 15, count 2 2006.203.07:54:02.52#ibcon#about to read 4, iclass 15, count 2 2006.203.07:54:02.52#ibcon#read 4, iclass 15, count 2 2006.203.07:54:02.52#ibcon#about to read 5, iclass 15, count 2 2006.203.07:54:02.52#ibcon#read 5, iclass 15, count 2 2006.203.07:54:02.52#ibcon#about to read 6, iclass 15, count 2 2006.203.07:54:02.52#ibcon#read 6, iclass 15, count 2 2006.203.07:54:02.52#ibcon#end of sib2, iclass 15, count 2 2006.203.07:54:02.52#ibcon#*after write, iclass 15, count 2 2006.203.07:54:02.52#ibcon#*before return 0, iclass 15, count 2 2006.203.07:54:02.52#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.203.07:54:02.52#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.203.07:54:02.52#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.203.07:54:02.52#ibcon#ireg 7 cls_cnt 0 2006.203.07:54:02.52#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.203.07:54:02.64#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.203.07:54:02.64#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.203.07:54:02.64#ibcon#enter wrdev, iclass 15, count 0 2006.203.07:54:02.64#ibcon#first serial, iclass 15, count 0 2006.203.07:54:02.64#ibcon#enter sib2, iclass 15, count 0 2006.203.07:54:02.64#ibcon#flushed, iclass 15, count 0 2006.203.07:54:02.64#ibcon#about to write, iclass 15, count 0 2006.203.07:54:02.64#ibcon#wrote, iclass 15, count 0 2006.203.07:54:02.64#ibcon#about to read 3, iclass 15, count 0 2006.203.07:54:02.66#ibcon#read 3, iclass 15, count 0 2006.203.07:54:02.66#ibcon#about to read 4, iclass 15, count 0 2006.203.07:54:02.66#ibcon#read 4, iclass 15, count 0 2006.203.07:54:02.66#ibcon#about to read 5, iclass 15, count 0 2006.203.07:54:02.66#ibcon#read 5, iclass 15, count 0 2006.203.07:54:02.66#ibcon#about to read 6, iclass 15, count 0 2006.203.07:54:02.66#ibcon#read 6, iclass 15, count 0 2006.203.07:54:02.66#ibcon#end of sib2, iclass 15, count 0 2006.203.07:54:02.66#ibcon#*mode == 0, iclass 15, count 0 2006.203.07:54:02.66#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.203.07:54:02.66#ibcon#[27=USB\r\n] 2006.203.07:54:02.66#ibcon#*before write, iclass 15, count 0 2006.203.07:54:02.66#ibcon#enter sib2, iclass 15, count 0 2006.203.07:54:02.66#ibcon#flushed, iclass 15, count 0 2006.203.07:54:02.66#ibcon#about to write, iclass 15, count 0 2006.203.07:54:02.66#ibcon#wrote, iclass 15, count 0 2006.203.07:54:02.66#ibcon#about to read 3, iclass 15, count 0 2006.203.07:54:02.69#ibcon#read 3, iclass 15, count 0 2006.203.07:54:02.69#ibcon#about to read 4, iclass 15, count 0 2006.203.07:54:02.69#ibcon#read 4, iclass 15, count 0 2006.203.07:54:02.69#ibcon#about to read 5, iclass 15, count 0 2006.203.07:54:02.69#ibcon#read 5, iclass 15, count 0 2006.203.07:54:02.69#ibcon#about to read 6, iclass 15, count 0 2006.203.07:54:02.69#ibcon#read 6, iclass 15, count 0 2006.203.07:54:02.69#ibcon#end of sib2, iclass 15, count 0 2006.203.07:54:02.69#ibcon#*after write, iclass 15, count 0 2006.203.07:54:02.69#ibcon#*before return 0, iclass 15, count 0 2006.203.07:54:02.69#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.203.07:54:02.69#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.203.07:54:02.69#ibcon#about to clear, iclass 15 cls_cnt 0 2006.203.07:54:02.69#ibcon#cleared, iclass 15 cls_cnt 0 2006.203.07:54:02.69$vc4f8/vblo=5,744.99 2006.203.07:54:02.69#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.203.07:54:02.69#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.203.07:54:02.69#ibcon#ireg 17 cls_cnt 0 2006.203.07:54:02.69#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.203.07:54:02.69#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.203.07:54:02.69#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.203.07:54:02.69#ibcon#enter wrdev, iclass 17, count 0 2006.203.07:54:02.69#ibcon#first serial, iclass 17, count 0 2006.203.07:54:02.69#ibcon#enter sib2, iclass 17, count 0 2006.203.07:54:02.69#ibcon#flushed, iclass 17, count 0 2006.203.07:54:02.69#ibcon#about to write, iclass 17, count 0 2006.203.07:54:02.69#ibcon#wrote, iclass 17, count 0 2006.203.07:54:02.69#ibcon#about to read 3, iclass 17, count 0 2006.203.07:54:02.71#ibcon#read 3, iclass 17, count 0 2006.203.07:54:02.71#ibcon#about to read 4, iclass 17, count 0 2006.203.07:54:02.71#ibcon#read 4, iclass 17, count 0 2006.203.07:54:02.71#ibcon#about to read 5, iclass 17, count 0 2006.203.07:54:02.71#ibcon#read 5, iclass 17, count 0 2006.203.07:54:02.71#ibcon#about to read 6, iclass 17, count 0 2006.203.07:54:02.71#ibcon#read 6, iclass 17, count 0 2006.203.07:54:02.71#ibcon#end of sib2, iclass 17, count 0 2006.203.07:54:02.71#ibcon#*mode == 0, iclass 17, count 0 2006.203.07:54:02.71#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.203.07:54:02.71#ibcon#[28=FRQ=05,744.99\r\n] 2006.203.07:54:02.71#ibcon#*before write, iclass 17, count 0 2006.203.07:54:02.71#ibcon#enter sib2, iclass 17, count 0 2006.203.07:54:02.71#ibcon#flushed, iclass 17, count 0 2006.203.07:54:02.71#ibcon#about to write, iclass 17, count 0 2006.203.07:54:02.71#ibcon#wrote, iclass 17, count 0 2006.203.07:54:02.71#ibcon#about to read 3, iclass 17, count 0 2006.203.07:54:02.75#ibcon#read 3, iclass 17, count 0 2006.203.07:54:02.75#ibcon#about to read 4, iclass 17, count 0 2006.203.07:54:02.75#ibcon#read 4, iclass 17, count 0 2006.203.07:54:02.75#ibcon#about to read 5, iclass 17, count 0 2006.203.07:54:02.75#ibcon#read 5, iclass 17, count 0 2006.203.07:54:02.75#ibcon#about to read 6, iclass 17, count 0 2006.203.07:54:02.75#ibcon#read 6, iclass 17, count 0 2006.203.07:54:02.75#ibcon#end of sib2, iclass 17, count 0 2006.203.07:54:02.75#ibcon#*after write, iclass 17, count 0 2006.203.07:54:02.75#ibcon#*before return 0, iclass 17, count 0 2006.203.07:54:02.75#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.203.07:54:02.75#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.203.07:54:02.75#ibcon#about to clear, iclass 17 cls_cnt 0 2006.203.07:54:02.75#ibcon#cleared, iclass 17 cls_cnt 0 2006.203.07:54:02.75$vc4f8/vb=5,3 2006.203.07:54:02.75#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.203.07:54:02.75#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.203.07:54:02.75#ibcon#ireg 11 cls_cnt 2 2006.203.07:54:02.75#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.203.07:54:02.81#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.203.07:54:02.81#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.203.07:54:02.81#ibcon#enter wrdev, iclass 19, count 2 2006.203.07:54:02.81#ibcon#first serial, iclass 19, count 2 2006.203.07:54:02.81#ibcon#enter sib2, iclass 19, count 2 2006.203.07:54:02.81#ibcon#flushed, iclass 19, count 2 2006.203.07:54:02.81#ibcon#about to write, iclass 19, count 2 2006.203.07:54:02.81#ibcon#wrote, iclass 19, count 2 2006.203.07:54:02.81#ibcon#about to read 3, iclass 19, count 2 2006.203.07:54:02.83#ibcon#read 3, iclass 19, count 2 2006.203.07:54:02.83#ibcon#about to read 4, iclass 19, count 2 2006.203.07:54:02.83#ibcon#read 4, iclass 19, count 2 2006.203.07:54:02.83#ibcon#about to read 5, iclass 19, count 2 2006.203.07:54:02.83#ibcon#read 5, iclass 19, count 2 2006.203.07:54:02.83#ibcon#about to read 6, iclass 19, count 2 2006.203.07:54:02.83#ibcon#read 6, iclass 19, count 2 2006.203.07:54:02.83#ibcon#end of sib2, iclass 19, count 2 2006.203.07:54:02.83#ibcon#*mode == 0, iclass 19, count 2 2006.203.07:54:02.83#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.203.07:54:02.83#ibcon#[27=AT05-03\r\n] 2006.203.07:54:02.83#ibcon#*before write, iclass 19, count 2 2006.203.07:54:02.83#ibcon#enter sib2, iclass 19, count 2 2006.203.07:54:02.83#ibcon#flushed, iclass 19, count 2 2006.203.07:54:02.83#ibcon#about to write, iclass 19, count 2 2006.203.07:54:02.83#ibcon#wrote, iclass 19, count 2 2006.203.07:54:02.83#ibcon#about to read 3, iclass 19, count 2 2006.203.07:54:02.86#ibcon#read 3, iclass 19, count 2 2006.203.07:54:02.86#ibcon#about to read 4, iclass 19, count 2 2006.203.07:54:02.86#ibcon#read 4, iclass 19, count 2 2006.203.07:54:02.86#ibcon#about to read 5, iclass 19, count 2 2006.203.07:54:02.86#ibcon#read 5, iclass 19, count 2 2006.203.07:54:02.86#ibcon#about to read 6, iclass 19, count 2 2006.203.07:54:02.86#ibcon#read 6, iclass 19, count 2 2006.203.07:54:02.86#ibcon#end of sib2, iclass 19, count 2 2006.203.07:54:02.86#ibcon#*after write, iclass 19, count 2 2006.203.07:54:02.86#ibcon#*before return 0, iclass 19, count 2 2006.203.07:54:02.86#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.203.07:54:02.86#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.203.07:54:02.86#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.203.07:54:02.86#ibcon#ireg 7 cls_cnt 0 2006.203.07:54:02.86#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.203.07:54:02.98#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.203.07:54:02.98#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.203.07:54:02.98#ibcon#enter wrdev, iclass 19, count 0 2006.203.07:54:02.98#ibcon#first serial, iclass 19, count 0 2006.203.07:54:02.98#ibcon#enter sib2, iclass 19, count 0 2006.203.07:54:02.98#ibcon#flushed, iclass 19, count 0 2006.203.07:54:02.98#ibcon#about to write, iclass 19, count 0 2006.203.07:54:02.98#ibcon#wrote, iclass 19, count 0 2006.203.07:54:02.98#ibcon#about to read 3, iclass 19, count 0 2006.203.07:54:03.00#ibcon#read 3, iclass 19, count 0 2006.203.07:54:03.00#ibcon#about to read 4, iclass 19, count 0 2006.203.07:54:03.00#ibcon#read 4, iclass 19, count 0 2006.203.07:54:03.00#ibcon#about to read 5, iclass 19, count 0 2006.203.07:54:03.00#ibcon#read 5, iclass 19, count 0 2006.203.07:54:03.00#ibcon#about to read 6, iclass 19, count 0 2006.203.07:54:03.00#ibcon#read 6, iclass 19, count 0 2006.203.07:54:03.00#ibcon#end of sib2, iclass 19, count 0 2006.203.07:54:03.00#ibcon#*mode == 0, iclass 19, count 0 2006.203.07:54:03.00#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.203.07:54:03.00#ibcon#[27=USB\r\n] 2006.203.07:54:03.00#ibcon#*before write, iclass 19, count 0 2006.203.07:54:03.00#ibcon#enter sib2, iclass 19, count 0 2006.203.07:54:03.00#ibcon#flushed, iclass 19, count 0 2006.203.07:54:03.00#ibcon#about to write, iclass 19, count 0 2006.203.07:54:03.00#ibcon#wrote, iclass 19, count 0 2006.203.07:54:03.00#ibcon#about to read 3, iclass 19, count 0 2006.203.07:54:03.03#ibcon#read 3, iclass 19, count 0 2006.203.07:54:03.03#ibcon#about to read 4, iclass 19, count 0 2006.203.07:54:03.03#ibcon#read 4, iclass 19, count 0 2006.203.07:54:03.03#ibcon#about to read 5, iclass 19, count 0 2006.203.07:54:03.03#ibcon#read 5, iclass 19, count 0 2006.203.07:54:03.03#ibcon#about to read 6, iclass 19, count 0 2006.203.07:54:03.03#ibcon#read 6, iclass 19, count 0 2006.203.07:54:03.03#ibcon#end of sib2, iclass 19, count 0 2006.203.07:54:03.03#ibcon#*after write, iclass 19, count 0 2006.203.07:54:03.03#ibcon#*before return 0, iclass 19, count 0 2006.203.07:54:03.03#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.203.07:54:03.03#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.203.07:54:03.03#ibcon#about to clear, iclass 19 cls_cnt 0 2006.203.07:54:03.03#ibcon#cleared, iclass 19 cls_cnt 0 2006.203.07:54:03.03$vc4f8/vblo=6,752.99 2006.203.07:54:03.03#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.203.07:54:03.03#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.203.07:54:03.03#ibcon#ireg 17 cls_cnt 0 2006.203.07:54:03.03#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.203.07:54:03.03#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.203.07:54:03.03#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.203.07:54:03.03#ibcon#enter wrdev, iclass 21, count 0 2006.203.07:54:03.03#ibcon#first serial, iclass 21, count 0 2006.203.07:54:03.03#ibcon#enter sib2, iclass 21, count 0 2006.203.07:54:03.03#ibcon#flushed, iclass 21, count 0 2006.203.07:54:03.03#ibcon#about to write, iclass 21, count 0 2006.203.07:54:03.03#ibcon#wrote, iclass 21, count 0 2006.203.07:54:03.03#ibcon#about to read 3, iclass 21, count 0 2006.203.07:54:03.05#ibcon#read 3, iclass 21, count 0 2006.203.07:54:03.05#ibcon#about to read 4, iclass 21, count 0 2006.203.07:54:03.05#ibcon#read 4, iclass 21, count 0 2006.203.07:54:03.05#ibcon#about to read 5, iclass 21, count 0 2006.203.07:54:03.05#ibcon#read 5, iclass 21, count 0 2006.203.07:54:03.05#ibcon#about to read 6, iclass 21, count 0 2006.203.07:54:03.05#ibcon#read 6, iclass 21, count 0 2006.203.07:54:03.05#ibcon#end of sib2, iclass 21, count 0 2006.203.07:54:03.05#ibcon#*mode == 0, iclass 21, count 0 2006.203.07:54:03.05#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.203.07:54:03.05#ibcon#[28=FRQ=06,752.99\r\n] 2006.203.07:54:03.05#ibcon#*before write, iclass 21, count 0 2006.203.07:54:03.05#ibcon#enter sib2, iclass 21, count 0 2006.203.07:54:03.05#ibcon#flushed, iclass 21, count 0 2006.203.07:54:03.05#ibcon#about to write, iclass 21, count 0 2006.203.07:54:03.05#ibcon#wrote, iclass 21, count 0 2006.203.07:54:03.05#ibcon#about to read 3, iclass 21, count 0 2006.203.07:54:03.09#ibcon#read 3, iclass 21, count 0 2006.203.07:54:03.09#ibcon#about to read 4, iclass 21, count 0 2006.203.07:54:03.09#ibcon#read 4, iclass 21, count 0 2006.203.07:54:03.09#ibcon#about to read 5, iclass 21, count 0 2006.203.07:54:03.09#ibcon#read 5, iclass 21, count 0 2006.203.07:54:03.09#ibcon#about to read 6, iclass 21, count 0 2006.203.07:54:03.09#ibcon#read 6, iclass 21, count 0 2006.203.07:54:03.09#ibcon#end of sib2, iclass 21, count 0 2006.203.07:54:03.09#ibcon#*after write, iclass 21, count 0 2006.203.07:54:03.09#ibcon#*before return 0, iclass 21, count 0 2006.203.07:54:03.09#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.203.07:54:03.09#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.203.07:54:03.09#ibcon#about to clear, iclass 21 cls_cnt 0 2006.203.07:54:03.09#ibcon#cleared, iclass 21 cls_cnt 0 2006.203.07:54:03.09$vc4f8/vb=6,4 2006.203.07:54:03.09#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.203.07:54:03.09#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.203.07:54:03.09#ibcon#ireg 11 cls_cnt 2 2006.203.07:54:03.09#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.203.07:54:03.16#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.203.07:54:03.16#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.203.07:54:03.16#ibcon#enter wrdev, iclass 23, count 2 2006.203.07:54:03.16#ibcon#first serial, iclass 23, count 2 2006.203.07:54:03.16#ibcon#enter sib2, iclass 23, count 2 2006.203.07:54:03.16#ibcon#flushed, iclass 23, count 2 2006.203.07:54:03.16#ibcon#about to write, iclass 23, count 2 2006.203.07:54:03.16#ibcon#wrote, iclass 23, count 2 2006.203.07:54:03.16#ibcon#about to read 3, iclass 23, count 2 2006.203.07:54:03.17#ibcon#read 3, iclass 23, count 2 2006.203.07:54:03.17#ibcon#about to read 4, iclass 23, count 2 2006.203.07:54:03.17#ibcon#read 4, iclass 23, count 2 2006.203.07:54:03.17#ibcon#about to read 5, iclass 23, count 2 2006.203.07:54:03.17#ibcon#read 5, iclass 23, count 2 2006.203.07:54:03.17#ibcon#about to read 6, iclass 23, count 2 2006.203.07:54:03.17#ibcon#read 6, iclass 23, count 2 2006.203.07:54:03.17#ibcon#end of sib2, iclass 23, count 2 2006.203.07:54:03.17#ibcon#*mode == 0, iclass 23, count 2 2006.203.07:54:03.17#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.203.07:54:03.17#ibcon#[27=AT06-04\r\n] 2006.203.07:54:03.17#ibcon#*before write, iclass 23, count 2 2006.203.07:54:03.17#ibcon#enter sib2, iclass 23, count 2 2006.203.07:54:03.17#ibcon#flushed, iclass 23, count 2 2006.203.07:54:03.17#ibcon#about to write, iclass 23, count 2 2006.203.07:54:03.17#ibcon#wrote, iclass 23, count 2 2006.203.07:54:03.17#ibcon#about to read 3, iclass 23, count 2 2006.203.07:54:03.20#ibcon#read 3, iclass 23, count 2 2006.203.07:54:03.20#ibcon#about to read 4, iclass 23, count 2 2006.203.07:54:03.20#ibcon#read 4, iclass 23, count 2 2006.203.07:54:03.20#ibcon#about to read 5, iclass 23, count 2 2006.203.07:54:03.20#ibcon#read 5, iclass 23, count 2 2006.203.07:54:03.20#ibcon#about to read 6, iclass 23, count 2 2006.203.07:54:03.20#ibcon#read 6, iclass 23, count 2 2006.203.07:54:03.20#ibcon#end of sib2, iclass 23, count 2 2006.203.07:54:03.20#ibcon#*after write, iclass 23, count 2 2006.203.07:54:03.20#ibcon#*before return 0, iclass 23, count 2 2006.203.07:54:03.20#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.203.07:54:03.20#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.203.07:54:03.20#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.203.07:54:03.20#ibcon#ireg 7 cls_cnt 0 2006.203.07:54:03.20#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.203.07:54:03.32#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.203.07:54:03.32#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.203.07:54:03.32#ibcon#enter wrdev, iclass 23, count 0 2006.203.07:54:03.32#ibcon#first serial, iclass 23, count 0 2006.203.07:54:03.32#ibcon#enter sib2, iclass 23, count 0 2006.203.07:54:03.32#ibcon#flushed, iclass 23, count 0 2006.203.07:54:03.32#ibcon#about to write, iclass 23, count 0 2006.203.07:54:03.32#ibcon#wrote, iclass 23, count 0 2006.203.07:54:03.32#ibcon#about to read 3, iclass 23, count 0 2006.203.07:54:03.34#ibcon#read 3, iclass 23, count 0 2006.203.07:54:03.34#ibcon#about to read 4, iclass 23, count 0 2006.203.07:54:03.34#ibcon#read 4, iclass 23, count 0 2006.203.07:54:03.34#ibcon#about to read 5, iclass 23, count 0 2006.203.07:54:03.34#ibcon#read 5, iclass 23, count 0 2006.203.07:54:03.34#ibcon#about to read 6, iclass 23, count 0 2006.203.07:54:03.34#ibcon#read 6, iclass 23, count 0 2006.203.07:54:03.34#ibcon#end of sib2, iclass 23, count 0 2006.203.07:54:03.34#ibcon#*mode == 0, iclass 23, count 0 2006.203.07:54:03.34#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.203.07:54:03.34#ibcon#[27=USB\r\n] 2006.203.07:54:03.34#ibcon#*before write, iclass 23, count 0 2006.203.07:54:03.34#ibcon#enter sib2, iclass 23, count 0 2006.203.07:54:03.34#ibcon#flushed, iclass 23, count 0 2006.203.07:54:03.34#ibcon#about to write, iclass 23, count 0 2006.203.07:54:03.34#ibcon#wrote, iclass 23, count 0 2006.203.07:54:03.34#ibcon#about to read 3, iclass 23, count 0 2006.203.07:54:03.37#ibcon#read 3, iclass 23, count 0 2006.203.07:54:03.37#ibcon#about to read 4, iclass 23, count 0 2006.203.07:54:03.37#ibcon#read 4, iclass 23, count 0 2006.203.07:54:03.37#ibcon#about to read 5, iclass 23, count 0 2006.203.07:54:03.37#ibcon#read 5, iclass 23, count 0 2006.203.07:54:03.37#ibcon#about to read 6, iclass 23, count 0 2006.203.07:54:03.37#ibcon#read 6, iclass 23, count 0 2006.203.07:54:03.37#ibcon#end of sib2, iclass 23, count 0 2006.203.07:54:03.37#ibcon#*after write, iclass 23, count 0 2006.203.07:54:03.37#ibcon#*before return 0, iclass 23, count 0 2006.203.07:54:03.37#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.203.07:54:03.37#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.203.07:54:03.37#ibcon#about to clear, iclass 23 cls_cnt 0 2006.203.07:54:03.37#ibcon#cleared, iclass 23 cls_cnt 0 2006.203.07:54:03.37$vc4f8/vabw=wide 2006.203.07:54:03.37#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.203.07:54:03.37#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.203.07:54:03.37#ibcon#ireg 8 cls_cnt 0 2006.203.07:54:03.37#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.203.07:54:03.37#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.203.07:54:03.37#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.203.07:54:03.37#ibcon#enter wrdev, iclass 25, count 0 2006.203.07:54:03.37#ibcon#first serial, iclass 25, count 0 2006.203.07:54:03.37#ibcon#enter sib2, iclass 25, count 0 2006.203.07:54:03.37#ibcon#flushed, iclass 25, count 0 2006.203.07:54:03.37#ibcon#about to write, iclass 25, count 0 2006.203.07:54:03.37#ibcon#wrote, iclass 25, count 0 2006.203.07:54:03.37#ibcon#about to read 3, iclass 25, count 0 2006.203.07:54:03.39#ibcon#read 3, iclass 25, count 0 2006.203.07:54:03.39#ibcon#about to read 4, iclass 25, count 0 2006.203.07:54:03.39#ibcon#read 4, iclass 25, count 0 2006.203.07:54:03.39#ibcon#about to read 5, iclass 25, count 0 2006.203.07:54:03.39#ibcon#read 5, iclass 25, count 0 2006.203.07:54:03.39#ibcon#about to read 6, iclass 25, count 0 2006.203.07:54:03.39#ibcon#read 6, iclass 25, count 0 2006.203.07:54:03.39#ibcon#end of sib2, iclass 25, count 0 2006.203.07:54:03.39#ibcon#*mode == 0, iclass 25, count 0 2006.203.07:54:03.39#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.203.07:54:03.39#ibcon#[25=BW32\r\n] 2006.203.07:54:03.39#ibcon#*before write, iclass 25, count 0 2006.203.07:54:03.39#ibcon#enter sib2, iclass 25, count 0 2006.203.07:54:03.39#ibcon#flushed, iclass 25, count 0 2006.203.07:54:03.39#ibcon#about to write, iclass 25, count 0 2006.203.07:54:03.39#ibcon#wrote, iclass 25, count 0 2006.203.07:54:03.39#ibcon#about to read 3, iclass 25, count 0 2006.203.07:54:03.42#ibcon#read 3, iclass 25, count 0 2006.203.07:54:03.42#ibcon#about to read 4, iclass 25, count 0 2006.203.07:54:03.42#ibcon#read 4, iclass 25, count 0 2006.203.07:54:03.42#ibcon#about to read 5, iclass 25, count 0 2006.203.07:54:03.42#ibcon#read 5, iclass 25, count 0 2006.203.07:54:03.42#ibcon#about to read 6, iclass 25, count 0 2006.203.07:54:03.42#ibcon#read 6, iclass 25, count 0 2006.203.07:54:03.42#ibcon#end of sib2, iclass 25, count 0 2006.203.07:54:03.42#ibcon#*after write, iclass 25, count 0 2006.203.07:54:03.42#ibcon#*before return 0, iclass 25, count 0 2006.203.07:54:03.42#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.203.07:54:03.42#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.203.07:54:03.42#ibcon#about to clear, iclass 25 cls_cnt 0 2006.203.07:54:03.42#ibcon#cleared, iclass 25 cls_cnt 0 2006.203.07:54:03.42$vc4f8/vbbw=wide 2006.203.07:54:03.42#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.203.07:54:03.42#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.203.07:54:03.42#ibcon#ireg 8 cls_cnt 0 2006.203.07:54:03.42#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:54:03.49#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:54:03.49#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:54:03.49#ibcon#enter wrdev, iclass 27, count 0 2006.203.07:54:03.49#ibcon#first serial, iclass 27, count 0 2006.203.07:54:03.49#ibcon#enter sib2, iclass 27, count 0 2006.203.07:54:03.49#ibcon#flushed, iclass 27, count 0 2006.203.07:54:03.49#ibcon#about to write, iclass 27, count 0 2006.203.07:54:03.49#ibcon#wrote, iclass 27, count 0 2006.203.07:54:03.49#ibcon#about to read 3, iclass 27, count 0 2006.203.07:54:03.51#ibcon#read 3, iclass 27, count 0 2006.203.07:54:03.51#ibcon#about to read 4, iclass 27, count 0 2006.203.07:54:03.51#ibcon#read 4, iclass 27, count 0 2006.203.07:54:03.51#ibcon#about to read 5, iclass 27, count 0 2006.203.07:54:03.51#ibcon#read 5, iclass 27, count 0 2006.203.07:54:03.51#ibcon#about to read 6, iclass 27, count 0 2006.203.07:54:03.51#ibcon#read 6, iclass 27, count 0 2006.203.07:54:03.51#ibcon#end of sib2, iclass 27, count 0 2006.203.07:54:03.51#ibcon#*mode == 0, iclass 27, count 0 2006.203.07:54:03.51#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.203.07:54:03.51#ibcon#[27=BW32\r\n] 2006.203.07:54:03.51#ibcon#*before write, iclass 27, count 0 2006.203.07:54:03.51#ibcon#enter sib2, iclass 27, count 0 2006.203.07:54:03.51#ibcon#flushed, iclass 27, count 0 2006.203.07:54:03.51#ibcon#about to write, iclass 27, count 0 2006.203.07:54:03.51#ibcon#wrote, iclass 27, count 0 2006.203.07:54:03.51#ibcon#about to read 3, iclass 27, count 0 2006.203.07:54:03.54#ibcon#read 3, iclass 27, count 0 2006.203.07:54:03.54#ibcon#about to read 4, iclass 27, count 0 2006.203.07:54:03.54#ibcon#read 4, iclass 27, count 0 2006.203.07:54:03.54#ibcon#about to read 5, iclass 27, count 0 2006.203.07:54:03.54#ibcon#read 5, iclass 27, count 0 2006.203.07:54:03.54#ibcon#about to read 6, iclass 27, count 0 2006.203.07:54:03.54#ibcon#read 6, iclass 27, count 0 2006.203.07:54:03.54#ibcon#end of sib2, iclass 27, count 0 2006.203.07:54:03.54#ibcon#*after write, iclass 27, count 0 2006.203.07:54:03.54#ibcon#*before return 0, iclass 27, count 0 2006.203.07:54:03.54#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:54:03.54#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.203.07:54:03.54#ibcon#about to clear, iclass 27 cls_cnt 0 2006.203.07:54:03.54#ibcon#cleared, iclass 27 cls_cnt 0 2006.203.07:54:03.54$4f8m12a/ifd4f 2006.203.07:54:03.54$ifd4f/lo= 2006.203.07:54:03.54$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.203.07:54:03.54$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.203.07:54:03.54$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.203.07:54:03.54$ifd4f/patch= 2006.203.07:54:03.54$ifd4f/patch=lo1,a1,a2,a3,a4 2006.203.07:54:03.54$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.203.07:54:03.54$ifd4f/patch=lo3,a5,a6,a7,a8 2006.203.07:54:03.54$4f8m12a/"form=m,16.000,1:2 2006.203.07:54:03.54$4f8m12a/"tpicd 2006.203.07:54:03.54$4f8m12a/echo=off 2006.203.07:54:03.54$4f8m12a/xlog=off 2006.203.07:54:03.54:!2006.203.07:55:40 2006.203.07:54:37.14#trakl#Source acquired 2006.203.07:54:39.14#flagr#flagr/antenna,acquired 2006.203.07:55:40.00:preob 2006.203.07:55:40.13/onsource/TRACKING 2006.203.07:55:40.13:!2006.203.07:55:50 2006.203.07:55:50.00:data_valid=on 2006.203.07:55:50.00:midob 2006.203.07:55:51.13/onsource/TRACKING 2006.203.07:55:51.13/wx/23.77,1001.2,98 2006.203.07:55:51.34/cable/+6.4608E-03 2006.203.07:55:52.43/va/01,08,usb,yes,29,30 2006.203.07:55:52.43/va/02,07,usb,yes,29,30 2006.203.07:55:52.43/va/03,08,usb,yes,21,22 2006.203.07:55:52.43/va/04,07,usb,yes,30,32 2006.203.07:55:52.43/va/05,07,usb,yes,32,34 2006.203.07:55:52.43/va/06,06,usb,yes,31,31 2006.203.07:55:52.43/va/07,07,usb,yes,27,27 2006.203.07:55:52.43/va/08,06,usb,yes,34,33 2006.203.07:55:52.66/valo/01,532.99,yes,locked 2006.203.07:55:52.66/valo/02,572.99,yes,locked 2006.203.07:55:52.66/valo/03,672.99,yes,locked 2006.203.07:55:52.66/valo/04,832.99,yes,locked 2006.203.07:55:52.66/valo/05,652.99,yes,locked 2006.203.07:55:52.66/valo/06,772.99,yes,locked 2006.203.07:55:52.66/valo/07,832.99,yes,locked 2006.203.07:55:52.66/valo/08,852.99,yes,locked 2006.203.07:55:53.75/vb/01,04,usb,yes,28,27 2006.203.07:55:53.75/vb/02,04,usb,yes,30,31 2006.203.07:55:53.75/vb/03,04,usb,yes,26,30 2006.203.07:55:53.75/vb/04,04,usb,yes,27,27 2006.203.07:55:53.75/vb/05,03,usb,yes,32,36 2006.203.07:55:53.75/vb/06,04,usb,yes,27,29 2006.203.07:55:53.75/vb/07,04,usb,yes,29,28 2006.203.07:55:53.75/vb/08,04,usb,yes,26,30 2006.203.07:55:53.99/vblo/01,632.99,yes,locked 2006.203.07:55:53.99/vblo/02,640.99,yes,locked 2006.203.07:55:53.99/vblo/03,656.99,yes,locked 2006.203.07:55:53.99/vblo/04,712.99,yes,locked 2006.203.07:55:53.99/vblo/05,744.99,yes,locked 2006.203.07:55:53.99/vblo/06,752.99,yes,locked 2006.203.07:55:53.99/vblo/07,734.99,yes,locked 2006.203.07:55:53.99/vblo/08,744.99,yes,locked 2006.203.07:55:54.14/vabw/8 2006.203.07:55:54.29/vbbw/8 2006.203.07:55:54.41/xfe/off,on,14.0 2006.203.07:55:54.78/ifatt/23,28,28,28 2006.203.07:55:55.07/fmout-gps/S +4.56E-07 2006.203.07:55:55.11:!2006.203.07:56:50 2006.203.07:56:50.00:data_valid=off 2006.203.07:56:50.00:postob 2006.203.07:56:50.22/cable/+6.4602E-03 2006.203.07:56:50.22/wx/23.76,1001.2,98 2006.203.07:56:51.07/fmout-gps/S +4.58E-07 2006.203.07:56:51.07:scan_name=203-0759,k06203,60 2006.203.07:56:51.07:source=0808+019,081126.71,014652.2,2000.0,ccw 2006.203.07:56:51.13#flagr#flagr/antenna,new-source 2006.203.07:56:52.13:checkk5 2006.203.07:56:52.57/chk_autoobs//k5ts1/ autoobs is running! 2006.203.07:56:53.01/chk_autoobs//k5ts2/ autoobs is running! 2006.203.07:56:53.41/chk_autoobs//k5ts3/ autoobs is running! 2006.203.07:56:53.84/chk_autoobs//k5ts4/ autoobs is running! 2006.203.07:56:54.23/chk_obsdata//k5ts1/T2030755??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.07:56:54.65/chk_obsdata//k5ts2/T2030755??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.07:56:55.04/chk_obsdata//k5ts3/T2030755??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.07:56:55.41/chk_obsdata//k5ts4/T2030755??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.07:56:56.18/k5log//k5ts1_log_newline 2006.203.07:56:57.09/k5log//k5ts2_log_newline 2006.203.07:56:58.02/k5log//k5ts3_log_newline 2006.203.07:56:59.16/k5log//k5ts4_log_newline 2006.203.07:56:59.22/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.203.07:56:59.22:4f8m12a=2 2006.203.07:56:59.22$4f8m12a/echo=on 2006.203.07:56:59.22$4f8m12a/pcalon 2006.203.07:56:59.22$pcalon/"no phase cal control is implemented here 2006.203.07:56:59.22$4f8m12a/"tpicd=stop 2006.203.07:56:59.22$4f8m12a/vc4f8 2006.203.07:56:59.22$vc4f8/valo=1,532.99 2006.203.07:56:59.23#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.203.07:56:59.23#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.203.07:56:59.23#ibcon#ireg 17 cls_cnt 0 2006.203.07:56:59.23#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.203.07:56:59.23#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.203.07:56:59.23#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.203.07:56:59.23#ibcon#enter wrdev, iclass 30, count 0 2006.203.07:56:59.23#ibcon#first serial, iclass 30, count 0 2006.203.07:56:59.23#ibcon#enter sib2, iclass 30, count 0 2006.203.07:56:59.23#ibcon#flushed, iclass 30, count 0 2006.203.07:56:59.23#ibcon#about to write, iclass 30, count 0 2006.203.07:56:59.23#ibcon#wrote, iclass 30, count 0 2006.203.07:56:59.23#ibcon#about to read 3, iclass 30, count 0 2006.203.07:56:59.25#ibcon#read 3, iclass 30, count 0 2006.203.07:56:59.25#ibcon#about to read 4, iclass 30, count 0 2006.203.07:56:59.25#ibcon#read 4, iclass 30, count 0 2006.203.07:56:59.25#ibcon#about to read 5, iclass 30, count 0 2006.203.07:56:59.25#ibcon#read 5, iclass 30, count 0 2006.203.07:56:59.25#ibcon#about to read 6, iclass 30, count 0 2006.203.07:56:59.25#ibcon#read 6, iclass 30, count 0 2006.203.07:56:59.25#ibcon#end of sib2, iclass 30, count 0 2006.203.07:56:59.25#ibcon#*mode == 0, iclass 30, count 0 2006.203.07:56:59.25#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.203.07:56:59.25#ibcon#[26=FRQ=01,532.99\r\n] 2006.203.07:56:59.25#ibcon#*before write, iclass 30, count 0 2006.203.07:56:59.25#ibcon#enter sib2, iclass 30, count 0 2006.203.07:56:59.25#ibcon#flushed, iclass 30, count 0 2006.203.07:56:59.25#ibcon#about to write, iclass 30, count 0 2006.203.07:56:59.25#ibcon#wrote, iclass 30, count 0 2006.203.07:56:59.25#ibcon#about to read 3, iclass 30, count 0 2006.203.07:56:59.30#ibcon#read 3, iclass 30, count 0 2006.203.07:56:59.30#ibcon#about to read 4, iclass 30, count 0 2006.203.07:56:59.30#ibcon#read 4, iclass 30, count 0 2006.203.07:56:59.30#ibcon#about to read 5, iclass 30, count 0 2006.203.07:56:59.30#ibcon#read 5, iclass 30, count 0 2006.203.07:56:59.30#ibcon#about to read 6, iclass 30, count 0 2006.203.07:56:59.30#ibcon#read 6, iclass 30, count 0 2006.203.07:56:59.30#ibcon#end of sib2, iclass 30, count 0 2006.203.07:56:59.30#ibcon#*after write, iclass 30, count 0 2006.203.07:56:59.30#ibcon#*before return 0, iclass 30, count 0 2006.203.07:56:59.30#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.203.07:56:59.30#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.203.07:56:59.30#ibcon#about to clear, iclass 30 cls_cnt 0 2006.203.07:56:59.30#ibcon#cleared, iclass 30 cls_cnt 0 2006.203.07:56:59.30$vc4f8/va=1,8 2006.203.07:56:59.30#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.203.07:56:59.30#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.203.07:56:59.30#ibcon#ireg 11 cls_cnt 2 2006.203.07:56:59.30#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.203.07:56:59.30#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.203.07:56:59.30#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.203.07:56:59.30#ibcon#enter wrdev, iclass 32, count 2 2006.203.07:56:59.30#ibcon#first serial, iclass 32, count 2 2006.203.07:56:59.30#ibcon#enter sib2, iclass 32, count 2 2006.203.07:56:59.30#ibcon#flushed, iclass 32, count 2 2006.203.07:56:59.30#ibcon#about to write, iclass 32, count 2 2006.203.07:56:59.30#ibcon#wrote, iclass 32, count 2 2006.203.07:56:59.30#ibcon#about to read 3, iclass 32, count 2 2006.203.07:56:59.32#ibcon#read 3, iclass 32, count 2 2006.203.07:56:59.32#ibcon#about to read 4, iclass 32, count 2 2006.203.07:56:59.32#ibcon#read 4, iclass 32, count 2 2006.203.07:56:59.32#ibcon#about to read 5, iclass 32, count 2 2006.203.07:56:59.32#ibcon#read 5, iclass 32, count 2 2006.203.07:56:59.32#ibcon#about to read 6, iclass 32, count 2 2006.203.07:56:59.32#ibcon#read 6, iclass 32, count 2 2006.203.07:56:59.32#ibcon#end of sib2, iclass 32, count 2 2006.203.07:56:59.32#ibcon#*mode == 0, iclass 32, count 2 2006.203.07:56:59.32#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.203.07:56:59.32#ibcon#[25=AT01-08\r\n] 2006.203.07:56:59.32#ibcon#*before write, iclass 32, count 2 2006.203.07:56:59.32#ibcon#enter sib2, iclass 32, count 2 2006.203.07:56:59.32#ibcon#flushed, iclass 32, count 2 2006.203.07:56:59.32#ibcon#about to write, iclass 32, count 2 2006.203.07:56:59.32#ibcon#wrote, iclass 32, count 2 2006.203.07:56:59.32#ibcon#about to read 3, iclass 32, count 2 2006.203.07:56:59.35#ibcon#read 3, iclass 32, count 2 2006.203.07:56:59.35#ibcon#about to read 4, iclass 32, count 2 2006.203.07:56:59.35#ibcon#read 4, iclass 32, count 2 2006.203.07:56:59.35#ibcon#about to read 5, iclass 32, count 2 2006.203.07:56:59.35#ibcon#read 5, iclass 32, count 2 2006.203.07:56:59.35#ibcon#about to read 6, iclass 32, count 2 2006.203.07:56:59.35#ibcon#read 6, iclass 32, count 2 2006.203.07:56:59.35#ibcon#end of sib2, iclass 32, count 2 2006.203.07:56:59.35#ibcon#*after write, iclass 32, count 2 2006.203.07:56:59.35#ibcon#*before return 0, iclass 32, count 2 2006.203.07:56:59.35#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.203.07:56:59.35#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.203.07:56:59.35#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.203.07:56:59.35#ibcon#ireg 7 cls_cnt 0 2006.203.07:56:59.35#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.203.07:56:59.47#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.203.07:56:59.47#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.203.07:56:59.47#ibcon#enter wrdev, iclass 32, count 0 2006.203.07:56:59.47#ibcon#first serial, iclass 32, count 0 2006.203.07:56:59.47#ibcon#enter sib2, iclass 32, count 0 2006.203.07:56:59.47#ibcon#flushed, iclass 32, count 0 2006.203.07:56:59.47#ibcon#about to write, iclass 32, count 0 2006.203.07:56:59.47#ibcon#wrote, iclass 32, count 0 2006.203.07:56:59.47#ibcon#about to read 3, iclass 32, count 0 2006.203.07:56:59.49#ibcon#read 3, iclass 32, count 0 2006.203.07:56:59.49#ibcon#about to read 4, iclass 32, count 0 2006.203.07:56:59.49#ibcon#read 4, iclass 32, count 0 2006.203.07:56:59.49#ibcon#about to read 5, iclass 32, count 0 2006.203.07:56:59.49#ibcon#read 5, iclass 32, count 0 2006.203.07:56:59.49#ibcon#about to read 6, iclass 32, count 0 2006.203.07:56:59.49#ibcon#read 6, iclass 32, count 0 2006.203.07:56:59.49#ibcon#end of sib2, iclass 32, count 0 2006.203.07:56:59.49#ibcon#*mode == 0, iclass 32, count 0 2006.203.07:56:59.49#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.203.07:56:59.49#ibcon#[25=USB\r\n] 2006.203.07:56:59.49#ibcon#*before write, iclass 32, count 0 2006.203.07:56:59.49#ibcon#enter sib2, iclass 32, count 0 2006.203.07:56:59.49#ibcon#flushed, iclass 32, count 0 2006.203.07:56:59.49#ibcon#about to write, iclass 32, count 0 2006.203.07:56:59.49#ibcon#wrote, iclass 32, count 0 2006.203.07:56:59.49#ibcon#about to read 3, iclass 32, count 0 2006.203.07:56:59.52#ibcon#read 3, iclass 32, count 0 2006.203.07:56:59.52#ibcon#about to read 4, iclass 32, count 0 2006.203.07:56:59.52#ibcon#read 4, iclass 32, count 0 2006.203.07:56:59.52#ibcon#about to read 5, iclass 32, count 0 2006.203.07:56:59.52#ibcon#read 5, iclass 32, count 0 2006.203.07:56:59.52#ibcon#about to read 6, iclass 32, count 0 2006.203.07:56:59.52#ibcon#read 6, iclass 32, count 0 2006.203.07:56:59.52#ibcon#end of sib2, iclass 32, count 0 2006.203.07:56:59.52#ibcon#*after write, iclass 32, count 0 2006.203.07:56:59.52#ibcon#*before return 0, iclass 32, count 0 2006.203.07:56:59.52#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.203.07:56:59.52#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.203.07:56:59.52#ibcon#about to clear, iclass 32 cls_cnt 0 2006.203.07:56:59.52#ibcon#cleared, iclass 32 cls_cnt 0 2006.203.07:56:59.52$vc4f8/valo=2,572.99 2006.203.07:56:59.52#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.203.07:56:59.52#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.203.07:56:59.52#ibcon#ireg 17 cls_cnt 0 2006.203.07:56:59.52#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.203.07:56:59.52#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.203.07:56:59.52#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.203.07:56:59.52#ibcon#enter wrdev, iclass 34, count 0 2006.203.07:56:59.52#ibcon#first serial, iclass 34, count 0 2006.203.07:56:59.52#ibcon#enter sib2, iclass 34, count 0 2006.203.07:56:59.52#ibcon#flushed, iclass 34, count 0 2006.203.07:56:59.52#ibcon#about to write, iclass 34, count 0 2006.203.07:56:59.52#ibcon#wrote, iclass 34, count 0 2006.203.07:56:59.52#ibcon#about to read 3, iclass 34, count 0 2006.203.07:56:59.54#ibcon#read 3, iclass 34, count 0 2006.203.07:56:59.54#ibcon#about to read 4, iclass 34, count 0 2006.203.07:56:59.54#ibcon#read 4, iclass 34, count 0 2006.203.07:56:59.54#ibcon#about to read 5, iclass 34, count 0 2006.203.07:56:59.54#ibcon#read 5, iclass 34, count 0 2006.203.07:56:59.54#ibcon#about to read 6, iclass 34, count 0 2006.203.07:56:59.54#ibcon#read 6, iclass 34, count 0 2006.203.07:56:59.54#ibcon#end of sib2, iclass 34, count 0 2006.203.07:56:59.54#ibcon#*mode == 0, iclass 34, count 0 2006.203.07:56:59.54#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.203.07:56:59.54#ibcon#[26=FRQ=02,572.99\r\n] 2006.203.07:56:59.54#ibcon#*before write, iclass 34, count 0 2006.203.07:56:59.54#ibcon#enter sib2, iclass 34, count 0 2006.203.07:56:59.54#ibcon#flushed, iclass 34, count 0 2006.203.07:56:59.54#ibcon#about to write, iclass 34, count 0 2006.203.07:56:59.54#ibcon#wrote, iclass 34, count 0 2006.203.07:56:59.54#ibcon#about to read 3, iclass 34, count 0 2006.203.07:56:59.59#ibcon#read 3, iclass 34, count 0 2006.203.07:56:59.59#ibcon#about to read 4, iclass 34, count 0 2006.203.07:56:59.59#ibcon#read 4, iclass 34, count 0 2006.203.07:56:59.59#ibcon#about to read 5, iclass 34, count 0 2006.203.07:56:59.59#ibcon#read 5, iclass 34, count 0 2006.203.07:56:59.59#ibcon#about to read 6, iclass 34, count 0 2006.203.07:56:59.59#ibcon#read 6, iclass 34, count 0 2006.203.07:56:59.59#ibcon#end of sib2, iclass 34, count 0 2006.203.07:56:59.59#ibcon#*after write, iclass 34, count 0 2006.203.07:56:59.59#ibcon#*before return 0, iclass 34, count 0 2006.203.07:56:59.59#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.203.07:56:59.59#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.203.07:56:59.59#ibcon#about to clear, iclass 34 cls_cnt 0 2006.203.07:56:59.59#ibcon#cleared, iclass 34 cls_cnt 0 2006.203.07:56:59.59$vc4f8/va=2,7 2006.203.07:56:59.59#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.203.07:56:59.59#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.203.07:56:59.59#ibcon#ireg 11 cls_cnt 2 2006.203.07:56:59.59#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.203.07:56:59.64#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.203.07:56:59.64#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.203.07:56:59.64#ibcon#enter wrdev, iclass 36, count 2 2006.203.07:56:59.64#ibcon#first serial, iclass 36, count 2 2006.203.07:56:59.64#ibcon#enter sib2, iclass 36, count 2 2006.203.07:56:59.64#ibcon#flushed, iclass 36, count 2 2006.203.07:56:59.64#ibcon#about to write, iclass 36, count 2 2006.203.07:56:59.64#ibcon#wrote, iclass 36, count 2 2006.203.07:56:59.64#ibcon#about to read 3, iclass 36, count 2 2006.203.07:56:59.66#ibcon#read 3, iclass 36, count 2 2006.203.07:56:59.66#ibcon#about to read 4, iclass 36, count 2 2006.203.07:56:59.66#ibcon#read 4, iclass 36, count 2 2006.203.07:56:59.66#ibcon#about to read 5, iclass 36, count 2 2006.203.07:56:59.66#ibcon#read 5, iclass 36, count 2 2006.203.07:56:59.66#ibcon#about to read 6, iclass 36, count 2 2006.203.07:56:59.66#ibcon#read 6, iclass 36, count 2 2006.203.07:56:59.66#ibcon#end of sib2, iclass 36, count 2 2006.203.07:56:59.66#ibcon#*mode == 0, iclass 36, count 2 2006.203.07:56:59.66#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.203.07:56:59.66#ibcon#[25=AT02-07\r\n] 2006.203.07:56:59.66#ibcon#*before write, iclass 36, count 2 2006.203.07:56:59.66#ibcon#enter sib2, iclass 36, count 2 2006.203.07:56:59.66#ibcon#flushed, iclass 36, count 2 2006.203.07:56:59.66#ibcon#about to write, iclass 36, count 2 2006.203.07:56:59.66#ibcon#wrote, iclass 36, count 2 2006.203.07:56:59.66#ibcon#about to read 3, iclass 36, count 2 2006.203.07:56:59.69#ibcon#read 3, iclass 36, count 2 2006.203.07:56:59.69#ibcon#about to read 4, iclass 36, count 2 2006.203.07:56:59.69#ibcon#read 4, iclass 36, count 2 2006.203.07:56:59.69#ibcon#about to read 5, iclass 36, count 2 2006.203.07:56:59.69#ibcon#read 5, iclass 36, count 2 2006.203.07:56:59.69#ibcon#about to read 6, iclass 36, count 2 2006.203.07:56:59.69#ibcon#read 6, iclass 36, count 2 2006.203.07:56:59.69#ibcon#end of sib2, iclass 36, count 2 2006.203.07:56:59.69#ibcon#*after write, iclass 36, count 2 2006.203.07:56:59.69#ibcon#*before return 0, iclass 36, count 2 2006.203.07:56:59.69#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.203.07:56:59.69#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.203.07:56:59.69#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.203.07:56:59.69#ibcon#ireg 7 cls_cnt 0 2006.203.07:56:59.69#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.203.07:56:59.81#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.203.07:56:59.81#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.203.07:56:59.81#ibcon#enter wrdev, iclass 36, count 0 2006.203.07:56:59.81#ibcon#first serial, iclass 36, count 0 2006.203.07:56:59.81#ibcon#enter sib2, iclass 36, count 0 2006.203.07:56:59.81#ibcon#flushed, iclass 36, count 0 2006.203.07:56:59.81#ibcon#about to write, iclass 36, count 0 2006.203.07:56:59.81#ibcon#wrote, iclass 36, count 0 2006.203.07:56:59.81#ibcon#about to read 3, iclass 36, count 0 2006.203.07:56:59.83#ibcon#read 3, iclass 36, count 0 2006.203.07:56:59.83#ibcon#about to read 4, iclass 36, count 0 2006.203.07:56:59.83#ibcon#read 4, iclass 36, count 0 2006.203.07:56:59.83#ibcon#about to read 5, iclass 36, count 0 2006.203.07:56:59.83#ibcon#read 5, iclass 36, count 0 2006.203.07:56:59.83#ibcon#about to read 6, iclass 36, count 0 2006.203.07:56:59.83#ibcon#read 6, iclass 36, count 0 2006.203.07:56:59.83#ibcon#end of sib2, iclass 36, count 0 2006.203.07:56:59.83#ibcon#*mode == 0, iclass 36, count 0 2006.203.07:56:59.83#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.203.07:56:59.83#ibcon#[25=USB\r\n] 2006.203.07:56:59.83#ibcon#*before write, iclass 36, count 0 2006.203.07:56:59.83#ibcon#enter sib2, iclass 36, count 0 2006.203.07:56:59.83#ibcon#flushed, iclass 36, count 0 2006.203.07:56:59.83#ibcon#about to write, iclass 36, count 0 2006.203.07:56:59.83#ibcon#wrote, iclass 36, count 0 2006.203.07:56:59.83#ibcon#about to read 3, iclass 36, count 0 2006.203.07:56:59.86#ibcon#read 3, iclass 36, count 0 2006.203.07:56:59.86#ibcon#about to read 4, iclass 36, count 0 2006.203.07:56:59.86#ibcon#read 4, iclass 36, count 0 2006.203.07:56:59.86#ibcon#about to read 5, iclass 36, count 0 2006.203.07:56:59.86#ibcon#read 5, iclass 36, count 0 2006.203.07:56:59.86#ibcon#about to read 6, iclass 36, count 0 2006.203.07:56:59.86#ibcon#read 6, iclass 36, count 0 2006.203.07:56:59.86#ibcon#end of sib2, iclass 36, count 0 2006.203.07:56:59.86#ibcon#*after write, iclass 36, count 0 2006.203.07:56:59.86#ibcon#*before return 0, iclass 36, count 0 2006.203.07:56:59.86#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.203.07:56:59.86#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.203.07:56:59.86#ibcon#about to clear, iclass 36 cls_cnt 0 2006.203.07:56:59.86#ibcon#cleared, iclass 36 cls_cnt 0 2006.203.07:56:59.86$vc4f8/valo=3,672.99 2006.203.07:56:59.86#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.203.07:56:59.86#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.203.07:56:59.86#ibcon#ireg 17 cls_cnt 0 2006.203.07:56:59.86#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.203.07:56:59.86#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.203.07:56:59.86#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.203.07:56:59.86#ibcon#enter wrdev, iclass 38, count 0 2006.203.07:56:59.86#ibcon#first serial, iclass 38, count 0 2006.203.07:56:59.86#ibcon#enter sib2, iclass 38, count 0 2006.203.07:56:59.86#ibcon#flushed, iclass 38, count 0 2006.203.07:56:59.86#ibcon#about to write, iclass 38, count 0 2006.203.07:56:59.86#ibcon#wrote, iclass 38, count 0 2006.203.07:56:59.86#ibcon#about to read 3, iclass 38, count 0 2006.203.07:56:59.88#ibcon#read 3, iclass 38, count 0 2006.203.07:56:59.88#ibcon#about to read 4, iclass 38, count 0 2006.203.07:56:59.88#ibcon#read 4, iclass 38, count 0 2006.203.07:56:59.88#ibcon#about to read 5, iclass 38, count 0 2006.203.07:56:59.88#ibcon#read 5, iclass 38, count 0 2006.203.07:56:59.88#ibcon#about to read 6, iclass 38, count 0 2006.203.07:56:59.88#ibcon#read 6, iclass 38, count 0 2006.203.07:56:59.88#ibcon#end of sib2, iclass 38, count 0 2006.203.07:56:59.88#ibcon#*mode == 0, iclass 38, count 0 2006.203.07:56:59.88#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.203.07:56:59.88#ibcon#[26=FRQ=03,672.99\r\n] 2006.203.07:56:59.88#ibcon#*before write, iclass 38, count 0 2006.203.07:56:59.88#ibcon#enter sib2, iclass 38, count 0 2006.203.07:56:59.88#ibcon#flushed, iclass 38, count 0 2006.203.07:56:59.88#ibcon#about to write, iclass 38, count 0 2006.203.07:56:59.88#ibcon#wrote, iclass 38, count 0 2006.203.07:56:59.88#ibcon#about to read 3, iclass 38, count 0 2006.203.07:56:59.93#ibcon#read 3, iclass 38, count 0 2006.203.07:56:59.93#ibcon#about to read 4, iclass 38, count 0 2006.203.07:56:59.93#ibcon#read 4, iclass 38, count 0 2006.203.07:56:59.93#ibcon#about to read 5, iclass 38, count 0 2006.203.07:56:59.93#ibcon#read 5, iclass 38, count 0 2006.203.07:56:59.93#ibcon#about to read 6, iclass 38, count 0 2006.203.07:56:59.93#ibcon#read 6, iclass 38, count 0 2006.203.07:56:59.93#ibcon#end of sib2, iclass 38, count 0 2006.203.07:56:59.93#ibcon#*after write, iclass 38, count 0 2006.203.07:56:59.93#ibcon#*before return 0, iclass 38, count 0 2006.203.07:56:59.93#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.203.07:56:59.93#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.203.07:56:59.93#ibcon#about to clear, iclass 38 cls_cnt 0 2006.203.07:56:59.93#ibcon#cleared, iclass 38 cls_cnt 0 2006.203.07:56:59.93$vc4f8/va=3,8 2006.203.07:56:59.93#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.203.07:56:59.93#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.203.07:56:59.93#ibcon#ireg 11 cls_cnt 2 2006.203.07:56:59.93#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.203.07:56:59.98#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.203.07:56:59.98#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.203.07:56:59.98#ibcon#enter wrdev, iclass 40, count 2 2006.203.07:56:59.98#ibcon#first serial, iclass 40, count 2 2006.203.07:56:59.98#ibcon#enter sib2, iclass 40, count 2 2006.203.07:56:59.98#ibcon#flushed, iclass 40, count 2 2006.203.07:56:59.98#ibcon#about to write, iclass 40, count 2 2006.203.07:56:59.98#ibcon#wrote, iclass 40, count 2 2006.203.07:56:59.98#ibcon#about to read 3, iclass 40, count 2 2006.203.07:57:00.00#ibcon#read 3, iclass 40, count 2 2006.203.07:57:00.00#ibcon#about to read 4, iclass 40, count 2 2006.203.07:57:00.00#ibcon#read 4, iclass 40, count 2 2006.203.07:57:00.00#ibcon#about to read 5, iclass 40, count 2 2006.203.07:57:00.00#ibcon#read 5, iclass 40, count 2 2006.203.07:57:00.00#ibcon#about to read 6, iclass 40, count 2 2006.203.07:57:00.00#ibcon#read 6, iclass 40, count 2 2006.203.07:57:00.00#ibcon#end of sib2, iclass 40, count 2 2006.203.07:57:00.00#ibcon#*mode == 0, iclass 40, count 2 2006.203.07:57:00.00#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.203.07:57:00.00#ibcon#[25=AT03-08\r\n] 2006.203.07:57:00.00#ibcon#*before write, iclass 40, count 2 2006.203.07:57:00.00#ibcon#enter sib2, iclass 40, count 2 2006.203.07:57:00.00#ibcon#flushed, iclass 40, count 2 2006.203.07:57:00.00#ibcon#about to write, iclass 40, count 2 2006.203.07:57:00.00#ibcon#wrote, iclass 40, count 2 2006.203.07:57:00.00#ibcon#about to read 3, iclass 40, count 2 2006.203.07:57:00.03#ibcon#read 3, iclass 40, count 2 2006.203.07:57:00.03#ibcon#about to read 4, iclass 40, count 2 2006.203.07:57:00.03#ibcon#read 4, iclass 40, count 2 2006.203.07:57:00.03#ibcon#about to read 5, iclass 40, count 2 2006.203.07:57:00.03#ibcon#read 5, iclass 40, count 2 2006.203.07:57:00.03#ibcon#about to read 6, iclass 40, count 2 2006.203.07:57:00.03#ibcon#read 6, iclass 40, count 2 2006.203.07:57:00.03#ibcon#end of sib2, iclass 40, count 2 2006.203.07:57:00.03#ibcon#*after write, iclass 40, count 2 2006.203.07:57:00.03#ibcon#*before return 0, iclass 40, count 2 2006.203.07:57:00.03#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.203.07:57:00.03#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.203.07:57:00.03#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.203.07:57:00.03#ibcon#ireg 7 cls_cnt 0 2006.203.07:57:00.03#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.203.07:57:00.15#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.203.07:57:00.15#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.203.07:57:00.15#ibcon#enter wrdev, iclass 40, count 0 2006.203.07:57:00.15#ibcon#first serial, iclass 40, count 0 2006.203.07:57:00.15#ibcon#enter sib2, iclass 40, count 0 2006.203.07:57:00.15#ibcon#flushed, iclass 40, count 0 2006.203.07:57:00.15#ibcon#about to write, iclass 40, count 0 2006.203.07:57:00.15#ibcon#wrote, iclass 40, count 0 2006.203.07:57:00.15#ibcon#about to read 3, iclass 40, count 0 2006.203.07:57:00.17#ibcon#read 3, iclass 40, count 0 2006.203.07:57:00.17#ibcon#about to read 4, iclass 40, count 0 2006.203.07:57:00.17#ibcon#read 4, iclass 40, count 0 2006.203.07:57:00.17#ibcon#about to read 5, iclass 40, count 0 2006.203.07:57:00.17#ibcon#read 5, iclass 40, count 0 2006.203.07:57:00.17#ibcon#about to read 6, iclass 40, count 0 2006.203.07:57:00.17#ibcon#read 6, iclass 40, count 0 2006.203.07:57:00.17#ibcon#end of sib2, iclass 40, count 0 2006.203.07:57:00.17#ibcon#*mode == 0, iclass 40, count 0 2006.203.07:57:00.17#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.203.07:57:00.17#ibcon#[25=USB\r\n] 2006.203.07:57:00.17#ibcon#*before write, iclass 40, count 0 2006.203.07:57:00.17#ibcon#enter sib2, iclass 40, count 0 2006.203.07:57:00.17#ibcon#flushed, iclass 40, count 0 2006.203.07:57:00.17#ibcon#about to write, iclass 40, count 0 2006.203.07:57:00.17#ibcon#wrote, iclass 40, count 0 2006.203.07:57:00.17#ibcon#about to read 3, iclass 40, count 0 2006.203.07:57:00.20#ibcon#read 3, iclass 40, count 0 2006.203.07:57:00.20#ibcon#about to read 4, iclass 40, count 0 2006.203.07:57:00.20#ibcon#read 4, iclass 40, count 0 2006.203.07:57:00.20#ibcon#about to read 5, iclass 40, count 0 2006.203.07:57:00.20#ibcon#read 5, iclass 40, count 0 2006.203.07:57:00.20#ibcon#about to read 6, iclass 40, count 0 2006.203.07:57:00.20#ibcon#read 6, iclass 40, count 0 2006.203.07:57:00.20#ibcon#end of sib2, iclass 40, count 0 2006.203.07:57:00.20#ibcon#*after write, iclass 40, count 0 2006.203.07:57:00.20#ibcon#*before return 0, iclass 40, count 0 2006.203.07:57:00.20#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.203.07:57:00.20#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.203.07:57:00.20#ibcon#about to clear, iclass 40 cls_cnt 0 2006.203.07:57:00.20#ibcon#cleared, iclass 40 cls_cnt 0 2006.203.07:57:00.20$vc4f8/valo=4,832.99 2006.203.07:57:00.20#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.203.07:57:00.20#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.203.07:57:00.20#ibcon#ireg 17 cls_cnt 0 2006.203.07:57:00.20#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.203.07:57:00.20#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.203.07:57:00.20#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.203.07:57:00.20#ibcon#enter wrdev, iclass 4, count 0 2006.203.07:57:00.20#ibcon#first serial, iclass 4, count 0 2006.203.07:57:00.20#ibcon#enter sib2, iclass 4, count 0 2006.203.07:57:00.20#ibcon#flushed, iclass 4, count 0 2006.203.07:57:00.20#ibcon#about to write, iclass 4, count 0 2006.203.07:57:00.20#ibcon#wrote, iclass 4, count 0 2006.203.07:57:00.20#ibcon#about to read 3, iclass 4, count 0 2006.203.07:57:00.22#ibcon#read 3, iclass 4, count 0 2006.203.07:57:00.22#ibcon#about to read 4, iclass 4, count 0 2006.203.07:57:00.22#ibcon#read 4, iclass 4, count 0 2006.203.07:57:00.22#ibcon#about to read 5, iclass 4, count 0 2006.203.07:57:00.22#ibcon#read 5, iclass 4, count 0 2006.203.07:57:00.22#ibcon#about to read 6, iclass 4, count 0 2006.203.07:57:00.22#ibcon#read 6, iclass 4, count 0 2006.203.07:57:00.22#ibcon#end of sib2, iclass 4, count 0 2006.203.07:57:00.22#ibcon#*mode == 0, iclass 4, count 0 2006.203.07:57:00.22#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.203.07:57:00.22#ibcon#[26=FRQ=04,832.99\r\n] 2006.203.07:57:00.22#ibcon#*before write, iclass 4, count 0 2006.203.07:57:00.22#ibcon#enter sib2, iclass 4, count 0 2006.203.07:57:00.22#ibcon#flushed, iclass 4, count 0 2006.203.07:57:00.22#ibcon#about to write, iclass 4, count 0 2006.203.07:57:00.22#ibcon#wrote, iclass 4, count 0 2006.203.07:57:00.22#ibcon#about to read 3, iclass 4, count 0 2006.203.07:57:00.26#ibcon#read 3, iclass 4, count 0 2006.203.07:57:00.26#ibcon#about to read 4, iclass 4, count 0 2006.203.07:57:00.26#ibcon#read 4, iclass 4, count 0 2006.203.07:57:00.26#ibcon#about to read 5, iclass 4, count 0 2006.203.07:57:00.26#ibcon#read 5, iclass 4, count 0 2006.203.07:57:00.26#ibcon#about to read 6, iclass 4, count 0 2006.203.07:57:00.26#ibcon#read 6, iclass 4, count 0 2006.203.07:57:00.26#ibcon#end of sib2, iclass 4, count 0 2006.203.07:57:00.26#ibcon#*after write, iclass 4, count 0 2006.203.07:57:00.26#ibcon#*before return 0, iclass 4, count 0 2006.203.07:57:00.26#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.203.07:57:00.26#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.203.07:57:00.26#ibcon#about to clear, iclass 4 cls_cnt 0 2006.203.07:57:00.26#ibcon#cleared, iclass 4 cls_cnt 0 2006.203.07:57:00.26$vc4f8/va=4,7 2006.203.07:57:00.26#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.203.07:57:00.26#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.203.07:57:00.26#ibcon#ireg 11 cls_cnt 2 2006.203.07:57:00.26#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.203.07:57:00.32#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.203.07:57:00.32#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.203.07:57:00.32#ibcon#enter wrdev, iclass 6, count 2 2006.203.07:57:00.32#ibcon#first serial, iclass 6, count 2 2006.203.07:57:00.32#ibcon#enter sib2, iclass 6, count 2 2006.203.07:57:00.32#ibcon#flushed, iclass 6, count 2 2006.203.07:57:00.32#ibcon#about to write, iclass 6, count 2 2006.203.07:57:00.32#ibcon#wrote, iclass 6, count 2 2006.203.07:57:00.32#ibcon#about to read 3, iclass 6, count 2 2006.203.07:57:00.34#ibcon#read 3, iclass 6, count 2 2006.203.07:57:00.34#ibcon#about to read 4, iclass 6, count 2 2006.203.07:57:00.34#ibcon#read 4, iclass 6, count 2 2006.203.07:57:00.34#ibcon#about to read 5, iclass 6, count 2 2006.203.07:57:00.34#ibcon#read 5, iclass 6, count 2 2006.203.07:57:00.34#ibcon#about to read 6, iclass 6, count 2 2006.203.07:57:00.34#ibcon#read 6, iclass 6, count 2 2006.203.07:57:00.34#ibcon#end of sib2, iclass 6, count 2 2006.203.07:57:00.34#ibcon#*mode == 0, iclass 6, count 2 2006.203.07:57:00.34#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.203.07:57:00.34#ibcon#[25=AT04-07\r\n] 2006.203.07:57:00.34#ibcon#*before write, iclass 6, count 2 2006.203.07:57:00.34#ibcon#enter sib2, iclass 6, count 2 2006.203.07:57:00.34#ibcon#flushed, iclass 6, count 2 2006.203.07:57:00.34#ibcon#about to write, iclass 6, count 2 2006.203.07:57:00.34#ibcon#wrote, iclass 6, count 2 2006.203.07:57:00.34#ibcon#about to read 3, iclass 6, count 2 2006.203.07:57:00.37#ibcon#read 3, iclass 6, count 2 2006.203.07:57:00.37#ibcon#about to read 4, iclass 6, count 2 2006.203.07:57:00.37#ibcon#read 4, iclass 6, count 2 2006.203.07:57:00.37#ibcon#about to read 5, iclass 6, count 2 2006.203.07:57:00.37#ibcon#read 5, iclass 6, count 2 2006.203.07:57:00.37#ibcon#about to read 6, iclass 6, count 2 2006.203.07:57:00.37#ibcon#read 6, iclass 6, count 2 2006.203.07:57:00.37#ibcon#end of sib2, iclass 6, count 2 2006.203.07:57:00.37#ibcon#*after write, iclass 6, count 2 2006.203.07:57:00.37#ibcon#*before return 0, iclass 6, count 2 2006.203.07:57:00.37#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.203.07:57:00.37#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.203.07:57:00.37#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.203.07:57:00.37#ibcon#ireg 7 cls_cnt 0 2006.203.07:57:00.37#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.203.07:57:00.49#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.203.07:57:00.49#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.203.07:57:00.49#ibcon#enter wrdev, iclass 6, count 0 2006.203.07:57:00.49#ibcon#first serial, iclass 6, count 0 2006.203.07:57:00.49#ibcon#enter sib2, iclass 6, count 0 2006.203.07:57:00.49#ibcon#flushed, iclass 6, count 0 2006.203.07:57:00.49#ibcon#about to write, iclass 6, count 0 2006.203.07:57:00.49#ibcon#wrote, iclass 6, count 0 2006.203.07:57:00.49#ibcon#about to read 3, iclass 6, count 0 2006.203.07:57:00.51#ibcon#read 3, iclass 6, count 0 2006.203.07:57:00.51#ibcon#about to read 4, iclass 6, count 0 2006.203.07:57:00.51#ibcon#read 4, iclass 6, count 0 2006.203.07:57:00.51#ibcon#about to read 5, iclass 6, count 0 2006.203.07:57:00.51#ibcon#read 5, iclass 6, count 0 2006.203.07:57:00.51#ibcon#about to read 6, iclass 6, count 0 2006.203.07:57:00.51#ibcon#read 6, iclass 6, count 0 2006.203.07:57:00.51#ibcon#end of sib2, iclass 6, count 0 2006.203.07:57:00.51#ibcon#*mode == 0, iclass 6, count 0 2006.203.07:57:00.51#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.203.07:57:00.51#ibcon#[25=USB\r\n] 2006.203.07:57:00.51#ibcon#*before write, iclass 6, count 0 2006.203.07:57:00.51#ibcon#enter sib2, iclass 6, count 0 2006.203.07:57:00.51#ibcon#flushed, iclass 6, count 0 2006.203.07:57:00.51#ibcon#about to write, iclass 6, count 0 2006.203.07:57:00.51#ibcon#wrote, iclass 6, count 0 2006.203.07:57:00.51#ibcon#about to read 3, iclass 6, count 0 2006.203.07:57:00.54#ibcon#read 3, iclass 6, count 0 2006.203.07:57:00.54#ibcon#about to read 4, iclass 6, count 0 2006.203.07:57:00.54#ibcon#read 4, iclass 6, count 0 2006.203.07:57:00.54#ibcon#about to read 5, iclass 6, count 0 2006.203.07:57:00.54#ibcon#read 5, iclass 6, count 0 2006.203.07:57:00.54#ibcon#about to read 6, iclass 6, count 0 2006.203.07:57:00.54#ibcon#read 6, iclass 6, count 0 2006.203.07:57:00.54#ibcon#end of sib2, iclass 6, count 0 2006.203.07:57:00.54#ibcon#*after write, iclass 6, count 0 2006.203.07:57:00.54#ibcon#*before return 0, iclass 6, count 0 2006.203.07:57:00.54#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.203.07:57:00.54#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.203.07:57:00.54#ibcon#about to clear, iclass 6 cls_cnt 0 2006.203.07:57:00.54#ibcon#cleared, iclass 6 cls_cnt 0 2006.203.07:57:00.54$vc4f8/valo=5,652.99 2006.203.07:57:00.54#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.203.07:57:00.54#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.203.07:57:00.54#ibcon#ireg 17 cls_cnt 0 2006.203.07:57:00.54#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.203.07:57:00.54#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.203.07:57:00.54#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.203.07:57:00.54#ibcon#enter wrdev, iclass 10, count 0 2006.203.07:57:00.54#ibcon#first serial, iclass 10, count 0 2006.203.07:57:00.54#ibcon#enter sib2, iclass 10, count 0 2006.203.07:57:00.54#ibcon#flushed, iclass 10, count 0 2006.203.07:57:00.54#ibcon#about to write, iclass 10, count 0 2006.203.07:57:00.54#ibcon#wrote, iclass 10, count 0 2006.203.07:57:00.54#ibcon#about to read 3, iclass 10, count 0 2006.203.07:57:00.56#ibcon#read 3, iclass 10, count 0 2006.203.07:57:00.56#ibcon#about to read 4, iclass 10, count 0 2006.203.07:57:00.56#ibcon#read 4, iclass 10, count 0 2006.203.07:57:00.56#ibcon#about to read 5, iclass 10, count 0 2006.203.07:57:00.56#ibcon#read 5, iclass 10, count 0 2006.203.07:57:00.56#ibcon#about to read 6, iclass 10, count 0 2006.203.07:57:00.56#ibcon#read 6, iclass 10, count 0 2006.203.07:57:00.56#ibcon#end of sib2, iclass 10, count 0 2006.203.07:57:00.56#ibcon#*mode == 0, iclass 10, count 0 2006.203.07:57:00.56#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.203.07:57:00.56#ibcon#[26=FRQ=05,652.99\r\n] 2006.203.07:57:00.56#ibcon#*before write, iclass 10, count 0 2006.203.07:57:00.56#ibcon#enter sib2, iclass 10, count 0 2006.203.07:57:00.56#ibcon#flushed, iclass 10, count 0 2006.203.07:57:00.56#ibcon#about to write, iclass 10, count 0 2006.203.07:57:00.56#ibcon#wrote, iclass 10, count 0 2006.203.07:57:00.56#ibcon#about to read 3, iclass 10, count 0 2006.203.07:57:00.60#ibcon#read 3, iclass 10, count 0 2006.203.07:57:00.60#ibcon#about to read 4, iclass 10, count 0 2006.203.07:57:00.60#ibcon#read 4, iclass 10, count 0 2006.203.07:57:00.60#ibcon#about to read 5, iclass 10, count 0 2006.203.07:57:00.60#ibcon#read 5, iclass 10, count 0 2006.203.07:57:00.60#ibcon#about to read 6, iclass 10, count 0 2006.203.07:57:00.60#ibcon#read 6, iclass 10, count 0 2006.203.07:57:00.60#ibcon#end of sib2, iclass 10, count 0 2006.203.07:57:00.60#ibcon#*after write, iclass 10, count 0 2006.203.07:57:00.60#ibcon#*before return 0, iclass 10, count 0 2006.203.07:57:00.60#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.203.07:57:00.60#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.203.07:57:00.60#ibcon#about to clear, iclass 10 cls_cnt 0 2006.203.07:57:00.60#ibcon#cleared, iclass 10 cls_cnt 0 2006.203.07:57:00.60$vc4f8/va=5,7 2006.203.07:57:00.60#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.203.07:57:00.60#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.203.07:57:00.60#ibcon#ireg 11 cls_cnt 2 2006.203.07:57:00.60#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.203.07:57:00.66#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.203.07:57:00.66#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.203.07:57:00.66#ibcon#enter wrdev, iclass 12, count 2 2006.203.07:57:00.66#ibcon#first serial, iclass 12, count 2 2006.203.07:57:00.66#ibcon#enter sib2, iclass 12, count 2 2006.203.07:57:00.66#ibcon#flushed, iclass 12, count 2 2006.203.07:57:00.66#ibcon#about to write, iclass 12, count 2 2006.203.07:57:00.66#ibcon#wrote, iclass 12, count 2 2006.203.07:57:00.66#ibcon#about to read 3, iclass 12, count 2 2006.203.07:57:00.68#ibcon#read 3, iclass 12, count 2 2006.203.07:57:00.68#ibcon#about to read 4, iclass 12, count 2 2006.203.07:57:00.68#ibcon#read 4, iclass 12, count 2 2006.203.07:57:00.68#ibcon#about to read 5, iclass 12, count 2 2006.203.07:57:00.68#ibcon#read 5, iclass 12, count 2 2006.203.07:57:00.68#ibcon#about to read 6, iclass 12, count 2 2006.203.07:57:00.68#ibcon#read 6, iclass 12, count 2 2006.203.07:57:00.68#ibcon#end of sib2, iclass 12, count 2 2006.203.07:57:00.68#ibcon#*mode == 0, iclass 12, count 2 2006.203.07:57:00.68#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.203.07:57:00.68#ibcon#[25=AT05-07\r\n] 2006.203.07:57:00.68#ibcon#*before write, iclass 12, count 2 2006.203.07:57:00.68#ibcon#enter sib2, iclass 12, count 2 2006.203.07:57:00.68#ibcon#flushed, iclass 12, count 2 2006.203.07:57:00.68#ibcon#about to write, iclass 12, count 2 2006.203.07:57:00.68#ibcon#wrote, iclass 12, count 2 2006.203.07:57:00.68#ibcon#about to read 3, iclass 12, count 2 2006.203.07:57:00.72#ibcon#read 3, iclass 12, count 2 2006.203.07:57:00.72#ibcon#about to read 4, iclass 12, count 2 2006.203.07:57:00.72#ibcon#read 4, iclass 12, count 2 2006.203.07:57:00.72#ibcon#about to read 5, iclass 12, count 2 2006.203.07:57:00.72#ibcon#read 5, iclass 12, count 2 2006.203.07:57:00.72#ibcon#about to read 6, iclass 12, count 2 2006.203.07:57:00.72#ibcon#read 6, iclass 12, count 2 2006.203.07:57:00.72#ibcon#end of sib2, iclass 12, count 2 2006.203.07:57:00.72#ibcon#*after write, iclass 12, count 2 2006.203.07:57:00.72#ibcon#*before return 0, iclass 12, count 2 2006.203.07:57:00.72#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.203.07:57:00.72#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.203.07:57:00.72#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.203.07:57:00.72#ibcon#ireg 7 cls_cnt 0 2006.203.07:57:00.72#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.203.07:57:00.84#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.203.07:57:00.84#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.203.07:57:00.84#ibcon#enter wrdev, iclass 12, count 0 2006.203.07:57:00.84#ibcon#first serial, iclass 12, count 0 2006.203.07:57:00.84#ibcon#enter sib2, iclass 12, count 0 2006.203.07:57:00.84#ibcon#flushed, iclass 12, count 0 2006.203.07:57:00.84#ibcon#about to write, iclass 12, count 0 2006.203.07:57:00.84#ibcon#wrote, iclass 12, count 0 2006.203.07:57:00.84#ibcon#about to read 3, iclass 12, count 0 2006.203.07:57:00.86#ibcon#read 3, iclass 12, count 0 2006.203.07:57:00.86#ibcon#about to read 4, iclass 12, count 0 2006.203.07:57:00.86#ibcon#read 4, iclass 12, count 0 2006.203.07:57:00.86#ibcon#about to read 5, iclass 12, count 0 2006.203.07:57:00.86#ibcon#read 5, iclass 12, count 0 2006.203.07:57:00.86#ibcon#about to read 6, iclass 12, count 0 2006.203.07:57:00.86#ibcon#read 6, iclass 12, count 0 2006.203.07:57:00.86#ibcon#end of sib2, iclass 12, count 0 2006.203.07:57:00.86#ibcon#*mode == 0, iclass 12, count 0 2006.203.07:57:00.86#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.203.07:57:00.86#ibcon#[25=USB\r\n] 2006.203.07:57:00.86#ibcon#*before write, iclass 12, count 0 2006.203.07:57:00.86#ibcon#enter sib2, iclass 12, count 0 2006.203.07:57:00.86#ibcon#flushed, iclass 12, count 0 2006.203.07:57:00.86#ibcon#about to write, iclass 12, count 0 2006.203.07:57:00.86#ibcon#wrote, iclass 12, count 0 2006.203.07:57:00.86#ibcon#about to read 3, iclass 12, count 0 2006.203.07:57:00.89#ibcon#read 3, iclass 12, count 0 2006.203.07:57:00.89#ibcon#about to read 4, iclass 12, count 0 2006.203.07:57:00.89#ibcon#read 4, iclass 12, count 0 2006.203.07:57:00.89#ibcon#about to read 5, iclass 12, count 0 2006.203.07:57:00.89#ibcon#read 5, iclass 12, count 0 2006.203.07:57:00.89#ibcon#about to read 6, iclass 12, count 0 2006.203.07:57:00.89#ibcon#read 6, iclass 12, count 0 2006.203.07:57:00.89#ibcon#end of sib2, iclass 12, count 0 2006.203.07:57:00.89#ibcon#*after write, iclass 12, count 0 2006.203.07:57:00.89#ibcon#*before return 0, iclass 12, count 0 2006.203.07:57:00.89#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.203.07:57:00.89#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.203.07:57:00.89#ibcon#about to clear, iclass 12 cls_cnt 0 2006.203.07:57:00.89#ibcon#cleared, iclass 12 cls_cnt 0 2006.203.07:57:00.89$vc4f8/valo=6,772.99 2006.203.07:57:00.89#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.203.07:57:00.89#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.203.07:57:00.89#ibcon#ireg 17 cls_cnt 0 2006.203.07:57:00.89#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.203.07:57:00.89#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.203.07:57:00.89#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.203.07:57:00.89#ibcon#enter wrdev, iclass 14, count 0 2006.203.07:57:00.89#ibcon#first serial, iclass 14, count 0 2006.203.07:57:00.89#ibcon#enter sib2, iclass 14, count 0 2006.203.07:57:00.89#ibcon#flushed, iclass 14, count 0 2006.203.07:57:00.89#ibcon#about to write, iclass 14, count 0 2006.203.07:57:00.89#ibcon#wrote, iclass 14, count 0 2006.203.07:57:00.89#ibcon#about to read 3, iclass 14, count 0 2006.203.07:57:00.91#ibcon#read 3, iclass 14, count 0 2006.203.07:57:00.91#ibcon#about to read 4, iclass 14, count 0 2006.203.07:57:00.91#ibcon#read 4, iclass 14, count 0 2006.203.07:57:00.91#ibcon#about to read 5, iclass 14, count 0 2006.203.07:57:00.91#ibcon#read 5, iclass 14, count 0 2006.203.07:57:00.91#ibcon#about to read 6, iclass 14, count 0 2006.203.07:57:00.91#ibcon#read 6, iclass 14, count 0 2006.203.07:57:00.91#ibcon#end of sib2, iclass 14, count 0 2006.203.07:57:00.91#ibcon#*mode == 0, iclass 14, count 0 2006.203.07:57:00.91#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.203.07:57:00.91#ibcon#[26=FRQ=06,772.99\r\n] 2006.203.07:57:00.91#ibcon#*before write, iclass 14, count 0 2006.203.07:57:00.91#ibcon#enter sib2, iclass 14, count 0 2006.203.07:57:00.91#ibcon#flushed, iclass 14, count 0 2006.203.07:57:00.91#ibcon#about to write, iclass 14, count 0 2006.203.07:57:00.91#ibcon#wrote, iclass 14, count 0 2006.203.07:57:00.91#ibcon#about to read 3, iclass 14, count 0 2006.203.07:57:00.95#ibcon#read 3, iclass 14, count 0 2006.203.07:57:00.95#ibcon#about to read 4, iclass 14, count 0 2006.203.07:57:00.95#ibcon#read 4, iclass 14, count 0 2006.203.07:57:00.95#ibcon#about to read 5, iclass 14, count 0 2006.203.07:57:00.95#ibcon#read 5, iclass 14, count 0 2006.203.07:57:00.95#ibcon#about to read 6, iclass 14, count 0 2006.203.07:57:00.95#ibcon#read 6, iclass 14, count 0 2006.203.07:57:00.95#ibcon#end of sib2, iclass 14, count 0 2006.203.07:57:00.95#ibcon#*after write, iclass 14, count 0 2006.203.07:57:00.95#ibcon#*before return 0, iclass 14, count 0 2006.203.07:57:00.95#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.203.07:57:00.95#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.203.07:57:00.95#ibcon#about to clear, iclass 14 cls_cnt 0 2006.203.07:57:00.95#ibcon#cleared, iclass 14 cls_cnt 0 2006.203.07:57:00.95$vc4f8/va=6,6 2006.203.07:57:00.95#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.203.07:57:00.95#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.203.07:57:00.95#ibcon#ireg 11 cls_cnt 2 2006.203.07:57:00.95#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.203.07:57:01.01#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.203.07:57:01.01#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.203.07:57:01.01#ibcon#enter wrdev, iclass 16, count 2 2006.203.07:57:01.01#ibcon#first serial, iclass 16, count 2 2006.203.07:57:01.01#ibcon#enter sib2, iclass 16, count 2 2006.203.07:57:01.01#ibcon#flushed, iclass 16, count 2 2006.203.07:57:01.01#ibcon#about to write, iclass 16, count 2 2006.203.07:57:01.01#ibcon#wrote, iclass 16, count 2 2006.203.07:57:01.01#ibcon#about to read 3, iclass 16, count 2 2006.203.07:57:01.03#ibcon#read 3, iclass 16, count 2 2006.203.07:57:01.03#ibcon#about to read 4, iclass 16, count 2 2006.203.07:57:01.03#ibcon#read 4, iclass 16, count 2 2006.203.07:57:01.03#ibcon#about to read 5, iclass 16, count 2 2006.203.07:57:01.03#ibcon#read 5, iclass 16, count 2 2006.203.07:57:01.03#ibcon#about to read 6, iclass 16, count 2 2006.203.07:57:01.03#ibcon#read 6, iclass 16, count 2 2006.203.07:57:01.03#ibcon#end of sib2, iclass 16, count 2 2006.203.07:57:01.03#ibcon#*mode == 0, iclass 16, count 2 2006.203.07:57:01.03#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.203.07:57:01.03#ibcon#[25=AT06-06\r\n] 2006.203.07:57:01.03#ibcon#*before write, iclass 16, count 2 2006.203.07:57:01.03#ibcon#enter sib2, iclass 16, count 2 2006.203.07:57:01.03#ibcon#flushed, iclass 16, count 2 2006.203.07:57:01.03#ibcon#about to write, iclass 16, count 2 2006.203.07:57:01.03#ibcon#wrote, iclass 16, count 2 2006.203.07:57:01.03#ibcon#about to read 3, iclass 16, count 2 2006.203.07:57:01.06#ibcon#read 3, iclass 16, count 2 2006.203.07:57:01.06#ibcon#about to read 4, iclass 16, count 2 2006.203.07:57:01.06#ibcon#read 4, iclass 16, count 2 2006.203.07:57:01.06#ibcon#about to read 5, iclass 16, count 2 2006.203.07:57:01.06#ibcon#read 5, iclass 16, count 2 2006.203.07:57:01.06#ibcon#about to read 6, iclass 16, count 2 2006.203.07:57:01.06#ibcon#read 6, iclass 16, count 2 2006.203.07:57:01.06#ibcon#end of sib2, iclass 16, count 2 2006.203.07:57:01.06#ibcon#*after write, iclass 16, count 2 2006.203.07:57:01.06#ibcon#*before return 0, iclass 16, count 2 2006.203.07:57:01.06#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.203.07:57:01.06#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.203.07:57:01.06#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.203.07:57:01.06#ibcon#ireg 7 cls_cnt 0 2006.203.07:57:01.06#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.203.07:57:01.18#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.203.07:57:01.18#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.203.07:57:01.18#ibcon#enter wrdev, iclass 16, count 0 2006.203.07:57:01.18#ibcon#first serial, iclass 16, count 0 2006.203.07:57:01.18#ibcon#enter sib2, iclass 16, count 0 2006.203.07:57:01.18#ibcon#flushed, iclass 16, count 0 2006.203.07:57:01.18#ibcon#about to write, iclass 16, count 0 2006.203.07:57:01.18#ibcon#wrote, iclass 16, count 0 2006.203.07:57:01.18#ibcon#about to read 3, iclass 16, count 0 2006.203.07:57:01.20#ibcon#read 3, iclass 16, count 0 2006.203.07:57:01.20#ibcon#about to read 4, iclass 16, count 0 2006.203.07:57:01.20#ibcon#read 4, iclass 16, count 0 2006.203.07:57:01.20#ibcon#about to read 5, iclass 16, count 0 2006.203.07:57:01.20#ibcon#read 5, iclass 16, count 0 2006.203.07:57:01.20#ibcon#about to read 6, iclass 16, count 0 2006.203.07:57:01.20#ibcon#read 6, iclass 16, count 0 2006.203.07:57:01.20#ibcon#end of sib2, iclass 16, count 0 2006.203.07:57:01.20#ibcon#*mode == 0, iclass 16, count 0 2006.203.07:57:01.20#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.203.07:57:01.20#ibcon#[25=USB\r\n] 2006.203.07:57:01.20#ibcon#*before write, iclass 16, count 0 2006.203.07:57:01.20#ibcon#enter sib2, iclass 16, count 0 2006.203.07:57:01.20#ibcon#flushed, iclass 16, count 0 2006.203.07:57:01.20#ibcon#about to write, iclass 16, count 0 2006.203.07:57:01.20#ibcon#wrote, iclass 16, count 0 2006.203.07:57:01.20#ibcon#about to read 3, iclass 16, count 0 2006.203.07:57:01.23#ibcon#read 3, iclass 16, count 0 2006.203.07:57:01.23#ibcon#about to read 4, iclass 16, count 0 2006.203.07:57:01.23#ibcon#read 4, iclass 16, count 0 2006.203.07:57:01.23#ibcon#about to read 5, iclass 16, count 0 2006.203.07:57:01.23#ibcon#read 5, iclass 16, count 0 2006.203.07:57:01.23#ibcon#about to read 6, iclass 16, count 0 2006.203.07:57:01.23#ibcon#read 6, iclass 16, count 0 2006.203.07:57:01.23#ibcon#end of sib2, iclass 16, count 0 2006.203.07:57:01.23#ibcon#*after write, iclass 16, count 0 2006.203.07:57:01.23#ibcon#*before return 0, iclass 16, count 0 2006.203.07:57:01.23#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.203.07:57:01.23#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.203.07:57:01.23#ibcon#about to clear, iclass 16 cls_cnt 0 2006.203.07:57:01.23#ibcon#cleared, iclass 16 cls_cnt 0 2006.203.07:57:01.23$vc4f8/valo=7,832.99 2006.203.07:57:01.23#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.203.07:57:01.23#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.203.07:57:01.23#ibcon#ireg 17 cls_cnt 0 2006.203.07:57:01.23#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.203.07:57:01.23#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.203.07:57:01.23#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.203.07:57:01.23#ibcon#enter wrdev, iclass 18, count 0 2006.203.07:57:01.23#ibcon#first serial, iclass 18, count 0 2006.203.07:57:01.23#ibcon#enter sib2, iclass 18, count 0 2006.203.07:57:01.23#ibcon#flushed, iclass 18, count 0 2006.203.07:57:01.23#ibcon#about to write, iclass 18, count 0 2006.203.07:57:01.23#ibcon#wrote, iclass 18, count 0 2006.203.07:57:01.23#ibcon#about to read 3, iclass 18, count 0 2006.203.07:57:01.25#ibcon#read 3, iclass 18, count 0 2006.203.07:57:01.25#ibcon#about to read 4, iclass 18, count 0 2006.203.07:57:01.25#ibcon#read 4, iclass 18, count 0 2006.203.07:57:01.25#ibcon#about to read 5, iclass 18, count 0 2006.203.07:57:01.25#ibcon#read 5, iclass 18, count 0 2006.203.07:57:01.25#ibcon#about to read 6, iclass 18, count 0 2006.203.07:57:01.25#ibcon#read 6, iclass 18, count 0 2006.203.07:57:01.25#ibcon#end of sib2, iclass 18, count 0 2006.203.07:57:01.25#ibcon#*mode == 0, iclass 18, count 0 2006.203.07:57:01.25#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.203.07:57:01.25#ibcon#[26=FRQ=07,832.99\r\n] 2006.203.07:57:01.25#ibcon#*before write, iclass 18, count 0 2006.203.07:57:01.25#ibcon#enter sib2, iclass 18, count 0 2006.203.07:57:01.25#ibcon#flushed, iclass 18, count 0 2006.203.07:57:01.25#ibcon#about to write, iclass 18, count 0 2006.203.07:57:01.25#ibcon#wrote, iclass 18, count 0 2006.203.07:57:01.25#ibcon#about to read 3, iclass 18, count 0 2006.203.07:57:01.29#ibcon#read 3, iclass 18, count 0 2006.203.07:57:01.29#ibcon#about to read 4, iclass 18, count 0 2006.203.07:57:01.29#ibcon#read 4, iclass 18, count 0 2006.203.07:57:01.29#ibcon#about to read 5, iclass 18, count 0 2006.203.07:57:01.29#ibcon#read 5, iclass 18, count 0 2006.203.07:57:01.29#ibcon#about to read 6, iclass 18, count 0 2006.203.07:57:01.29#ibcon#read 6, iclass 18, count 0 2006.203.07:57:01.29#ibcon#end of sib2, iclass 18, count 0 2006.203.07:57:01.29#ibcon#*after write, iclass 18, count 0 2006.203.07:57:01.29#ibcon#*before return 0, iclass 18, count 0 2006.203.07:57:01.29#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.203.07:57:01.29#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.203.07:57:01.29#ibcon#about to clear, iclass 18 cls_cnt 0 2006.203.07:57:01.29#ibcon#cleared, iclass 18 cls_cnt 0 2006.203.07:57:01.29$vc4f8/va=7,7 2006.203.07:57:01.29#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.203.07:57:01.29#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.203.07:57:01.29#ibcon#ireg 11 cls_cnt 2 2006.203.07:57:01.29#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.203.07:57:01.35#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.203.07:57:01.35#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.203.07:57:01.35#ibcon#enter wrdev, iclass 20, count 2 2006.203.07:57:01.35#ibcon#first serial, iclass 20, count 2 2006.203.07:57:01.35#ibcon#enter sib2, iclass 20, count 2 2006.203.07:57:01.35#ibcon#flushed, iclass 20, count 2 2006.203.07:57:01.35#ibcon#about to write, iclass 20, count 2 2006.203.07:57:01.35#ibcon#wrote, iclass 20, count 2 2006.203.07:57:01.35#ibcon#about to read 3, iclass 20, count 2 2006.203.07:57:01.37#ibcon#read 3, iclass 20, count 2 2006.203.07:57:01.37#ibcon#about to read 4, iclass 20, count 2 2006.203.07:57:01.37#ibcon#read 4, iclass 20, count 2 2006.203.07:57:01.37#ibcon#about to read 5, iclass 20, count 2 2006.203.07:57:01.37#ibcon#read 5, iclass 20, count 2 2006.203.07:57:01.37#ibcon#about to read 6, iclass 20, count 2 2006.203.07:57:01.37#ibcon#read 6, iclass 20, count 2 2006.203.07:57:01.37#ibcon#end of sib2, iclass 20, count 2 2006.203.07:57:01.37#ibcon#*mode == 0, iclass 20, count 2 2006.203.07:57:01.37#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.203.07:57:01.37#ibcon#[25=AT07-07\r\n] 2006.203.07:57:01.37#ibcon#*before write, iclass 20, count 2 2006.203.07:57:01.37#ibcon#enter sib2, iclass 20, count 2 2006.203.07:57:01.37#ibcon#flushed, iclass 20, count 2 2006.203.07:57:01.37#ibcon#about to write, iclass 20, count 2 2006.203.07:57:01.37#ibcon#wrote, iclass 20, count 2 2006.203.07:57:01.37#ibcon#about to read 3, iclass 20, count 2 2006.203.07:57:01.40#ibcon#read 3, iclass 20, count 2 2006.203.07:57:01.40#ibcon#about to read 4, iclass 20, count 2 2006.203.07:57:01.40#ibcon#read 4, iclass 20, count 2 2006.203.07:57:01.40#ibcon#about to read 5, iclass 20, count 2 2006.203.07:57:01.40#ibcon#read 5, iclass 20, count 2 2006.203.07:57:01.40#ibcon#about to read 6, iclass 20, count 2 2006.203.07:57:01.40#ibcon#read 6, iclass 20, count 2 2006.203.07:57:01.40#ibcon#end of sib2, iclass 20, count 2 2006.203.07:57:01.40#ibcon#*after write, iclass 20, count 2 2006.203.07:57:01.40#ibcon#*before return 0, iclass 20, count 2 2006.203.07:57:01.40#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.203.07:57:01.40#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.203.07:57:01.40#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.203.07:57:01.40#ibcon#ireg 7 cls_cnt 0 2006.203.07:57:01.40#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.203.07:57:01.52#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.203.07:57:01.52#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.203.07:57:01.52#ibcon#enter wrdev, iclass 20, count 0 2006.203.07:57:01.52#ibcon#first serial, iclass 20, count 0 2006.203.07:57:01.52#ibcon#enter sib2, iclass 20, count 0 2006.203.07:57:01.52#ibcon#flushed, iclass 20, count 0 2006.203.07:57:01.52#ibcon#about to write, iclass 20, count 0 2006.203.07:57:01.52#ibcon#wrote, iclass 20, count 0 2006.203.07:57:01.52#ibcon#about to read 3, iclass 20, count 0 2006.203.07:57:01.54#ibcon#read 3, iclass 20, count 0 2006.203.07:57:01.54#ibcon#about to read 4, iclass 20, count 0 2006.203.07:57:01.54#ibcon#read 4, iclass 20, count 0 2006.203.07:57:01.54#ibcon#about to read 5, iclass 20, count 0 2006.203.07:57:01.54#ibcon#read 5, iclass 20, count 0 2006.203.07:57:01.54#ibcon#about to read 6, iclass 20, count 0 2006.203.07:57:01.54#ibcon#read 6, iclass 20, count 0 2006.203.07:57:01.54#ibcon#end of sib2, iclass 20, count 0 2006.203.07:57:01.54#ibcon#*mode == 0, iclass 20, count 0 2006.203.07:57:01.54#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.203.07:57:01.54#ibcon#[25=USB\r\n] 2006.203.07:57:01.54#ibcon#*before write, iclass 20, count 0 2006.203.07:57:01.54#ibcon#enter sib2, iclass 20, count 0 2006.203.07:57:01.54#ibcon#flushed, iclass 20, count 0 2006.203.07:57:01.54#ibcon#about to write, iclass 20, count 0 2006.203.07:57:01.54#ibcon#wrote, iclass 20, count 0 2006.203.07:57:01.54#ibcon#about to read 3, iclass 20, count 0 2006.203.07:57:01.57#ibcon#read 3, iclass 20, count 0 2006.203.07:57:01.57#ibcon#about to read 4, iclass 20, count 0 2006.203.07:57:01.57#ibcon#read 4, iclass 20, count 0 2006.203.07:57:01.57#ibcon#about to read 5, iclass 20, count 0 2006.203.07:57:01.57#ibcon#read 5, iclass 20, count 0 2006.203.07:57:01.57#ibcon#about to read 6, iclass 20, count 0 2006.203.07:57:01.57#ibcon#read 6, iclass 20, count 0 2006.203.07:57:01.57#ibcon#end of sib2, iclass 20, count 0 2006.203.07:57:01.57#ibcon#*after write, iclass 20, count 0 2006.203.07:57:01.57#ibcon#*before return 0, iclass 20, count 0 2006.203.07:57:01.57#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.203.07:57:01.57#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.203.07:57:01.57#ibcon#about to clear, iclass 20 cls_cnt 0 2006.203.07:57:01.57#ibcon#cleared, iclass 20 cls_cnt 0 2006.203.07:57:01.57$vc4f8/valo=8,852.99 2006.203.07:57:01.57#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.203.07:57:01.57#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.203.07:57:01.57#ibcon#ireg 17 cls_cnt 0 2006.203.07:57:01.57#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.203.07:57:01.57#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.203.07:57:01.57#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.203.07:57:01.57#ibcon#enter wrdev, iclass 22, count 0 2006.203.07:57:01.57#ibcon#first serial, iclass 22, count 0 2006.203.07:57:01.57#ibcon#enter sib2, iclass 22, count 0 2006.203.07:57:01.57#ibcon#flushed, iclass 22, count 0 2006.203.07:57:01.57#ibcon#about to write, iclass 22, count 0 2006.203.07:57:01.57#ibcon#wrote, iclass 22, count 0 2006.203.07:57:01.57#ibcon#about to read 3, iclass 22, count 0 2006.203.07:57:01.59#ibcon#read 3, iclass 22, count 0 2006.203.07:57:01.59#ibcon#about to read 4, iclass 22, count 0 2006.203.07:57:01.59#ibcon#read 4, iclass 22, count 0 2006.203.07:57:01.59#ibcon#about to read 5, iclass 22, count 0 2006.203.07:57:01.59#ibcon#read 5, iclass 22, count 0 2006.203.07:57:01.59#ibcon#about to read 6, iclass 22, count 0 2006.203.07:57:01.59#ibcon#read 6, iclass 22, count 0 2006.203.07:57:01.59#ibcon#end of sib2, iclass 22, count 0 2006.203.07:57:01.59#ibcon#*mode == 0, iclass 22, count 0 2006.203.07:57:01.59#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.203.07:57:01.59#ibcon#[26=FRQ=08,852.99\r\n] 2006.203.07:57:01.59#ibcon#*before write, iclass 22, count 0 2006.203.07:57:01.59#ibcon#enter sib2, iclass 22, count 0 2006.203.07:57:01.59#ibcon#flushed, iclass 22, count 0 2006.203.07:57:01.59#ibcon#about to write, iclass 22, count 0 2006.203.07:57:01.59#ibcon#wrote, iclass 22, count 0 2006.203.07:57:01.59#ibcon#about to read 3, iclass 22, count 0 2006.203.07:57:01.63#ibcon#read 3, iclass 22, count 0 2006.203.07:57:01.63#ibcon#about to read 4, iclass 22, count 0 2006.203.07:57:01.63#ibcon#read 4, iclass 22, count 0 2006.203.07:57:01.63#ibcon#about to read 5, iclass 22, count 0 2006.203.07:57:01.63#ibcon#read 5, iclass 22, count 0 2006.203.07:57:01.63#ibcon#about to read 6, iclass 22, count 0 2006.203.07:57:01.63#ibcon#read 6, iclass 22, count 0 2006.203.07:57:01.63#ibcon#end of sib2, iclass 22, count 0 2006.203.07:57:01.63#ibcon#*after write, iclass 22, count 0 2006.203.07:57:01.63#ibcon#*before return 0, iclass 22, count 0 2006.203.07:57:01.63#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.203.07:57:01.63#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.203.07:57:01.63#ibcon#about to clear, iclass 22 cls_cnt 0 2006.203.07:57:01.63#ibcon#cleared, iclass 22 cls_cnt 0 2006.203.07:57:01.63$vc4f8/va=8,6 2006.203.07:57:01.63#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.203.07:57:01.63#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.203.07:57:01.63#ibcon#ireg 11 cls_cnt 2 2006.203.07:57:01.63#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.203.07:57:01.69#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.203.07:57:01.69#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.203.07:57:01.69#ibcon#enter wrdev, iclass 24, count 2 2006.203.07:57:01.69#ibcon#first serial, iclass 24, count 2 2006.203.07:57:01.69#ibcon#enter sib2, iclass 24, count 2 2006.203.07:57:01.69#ibcon#flushed, iclass 24, count 2 2006.203.07:57:01.69#ibcon#about to write, iclass 24, count 2 2006.203.07:57:01.69#ibcon#wrote, iclass 24, count 2 2006.203.07:57:01.69#ibcon#about to read 3, iclass 24, count 2 2006.203.07:57:01.71#ibcon#read 3, iclass 24, count 2 2006.203.07:57:01.71#ibcon#about to read 4, iclass 24, count 2 2006.203.07:57:01.71#ibcon#read 4, iclass 24, count 2 2006.203.07:57:01.71#ibcon#about to read 5, iclass 24, count 2 2006.203.07:57:01.71#ibcon#read 5, iclass 24, count 2 2006.203.07:57:01.71#ibcon#about to read 6, iclass 24, count 2 2006.203.07:57:01.71#ibcon#read 6, iclass 24, count 2 2006.203.07:57:01.71#ibcon#end of sib2, iclass 24, count 2 2006.203.07:57:01.71#ibcon#*mode == 0, iclass 24, count 2 2006.203.07:57:01.71#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.203.07:57:01.71#ibcon#[25=AT08-06\r\n] 2006.203.07:57:01.71#ibcon#*before write, iclass 24, count 2 2006.203.07:57:01.71#ibcon#enter sib2, iclass 24, count 2 2006.203.07:57:01.71#ibcon#flushed, iclass 24, count 2 2006.203.07:57:01.71#ibcon#about to write, iclass 24, count 2 2006.203.07:57:01.71#ibcon#wrote, iclass 24, count 2 2006.203.07:57:01.71#ibcon#about to read 3, iclass 24, count 2 2006.203.07:57:01.74#ibcon#read 3, iclass 24, count 2 2006.203.07:57:01.74#ibcon#about to read 4, iclass 24, count 2 2006.203.07:57:01.74#ibcon#read 4, iclass 24, count 2 2006.203.07:57:01.74#ibcon#about to read 5, iclass 24, count 2 2006.203.07:57:01.74#ibcon#read 5, iclass 24, count 2 2006.203.07:57:01.74#ibcon#about to read 6, iclass 24, count 2 2006.203.07:57:01.74#ibcon#read 6, iclass 24, count 2 2006.203.07:57:01.74#ibcon#end of sib2, iclass 24, count 2 2006.203.07:57:01.74#ibcon#*after write, iclass 24, count 2 2006.203.07:57:01.74#ibcon#*before return 0, iclass 24, count 2 2006.203.07:57:01.74#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.203.07:57:01.74#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.203.07:57:01.74#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.203.07:57:01.74#ibcon#ireg 7 cls_cnt 0 2006.203.07:57:01.74#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.203.07:57:01.86#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.203.07:57:01.86#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.203.07:57:01.86#ibcon#enter wrdev, iclass 24, count 0 2006.203.07:57:01.86#ibcon#first serial, iclass 24, count 0 2006.203.07:57:01.86#ibcon#enter sib2, iclass 24, count 0 2006.203.07:57:01.86#ibcon#flushed, iclass 24, count 0 2006.203.07:57:01.86#ibcon#about to write, iclass 24, count 0 2006.203.07:57:01.86#ibcon#wrote, iclass 24, count 0 2006.203.07:57:01.86#ibcon#about to read 3, iclass 24, count 0 2006.203.07:57:01.88#ibcon#read 3, iclass 24, count 0 2006.203.07:57:01.88#ibcon#about to read 4, iclass 24, count 0 2006.203.07:57:01.88#ibcon#read 4, iclass 24, count 0 2006.203.07:57:01.88#ibcon#about to read 5, iclass 24, count 0 2006.203.07:57:01.88#ibcon#read 5, iclass 24, count 0 2006.203.07:57:01.88#ibcon#about to read 6, iclass 24, count 0 2006.203.07:57:01.88#ibcon#read 6, iclass 24, count 0 2006.203.07:57:01.88#ibcon#end of sib2, iclass 24, count 0 2006.203.07:57:01.88#ibcon#*mode == 0, iclass 24, count 0 2006.203.07:57:01.88#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.203.07:57:01.88#ibcon#[25=USB\r\n] 2006.203.07:57:01.88#ibcon#*before write, iclass 24, count 0 2006.203.07:57:01.88#ibcon#enter sib2, iclass 24, count 0 2006.203.07:57:01.88#ibcon#flushed, iclass 24, count 0 2006.203.07:57:01.88#ibcon#about to write, iclass 24, count 0 2006.203.07:57:01.88#ibcon#wrote, iclass 24, count 0 2006.203.07:57:01.88#ibcon#about to read 3, iclass 24, count 0 2006.203.07:57:01.91#ibcon#read 3, iclass 24, count 0 2006.203.07:57:01.91#ibcon#about to read 4, iclass 24, count 0 2006.203.07:57:01.91#ibcon#read 4, iclass 24, count 0 2006.203.07:57:01.91#ibcon#about to read 5, iclass 24, count 0 2006.203.07:57:01.91#ibcon#read 5, iclass 24, count 0 2006.203.07:57:01.91#ibcon#about to read 6, iclass 24, count 0 2006.203.07:57:01.91#ibcon#read 6, iclass 24, count 0 2006.203.07:57:01.91#ibcon#end of sib2, iclass 24, count 0 2006.203.07:57:01.91#ibcon#*after write, iclass 24, count 0 2006.203.07:57:01.91#ibcon#*before return 0, iclass 24, count 0 2006.203.07:57:01.91#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.203.07:57:01.91#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.203.07:57:01.91#ibcon#about to clear, iclass 24 cls_cnt 0 2006.203.07:57:01.91#ibcon#cleared, iclass 24 cls_cnt 0 2006.203.07:57:01.91$vc4f8/vblo=1,632.99 2006.203.07:57:01.91#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.203.07:57:01.91#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.203.07:57:01.91#ibcon#ireg 17 cls_cnt 0 2006.203.07:57:01.91#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.203.07:57:01.91#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.203.07:57:01.91#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.203.07:57:01.91#ibcon#enter wrdev, iclass 26, count 0 2006.203.07:57:01.91#ibcon#first serial, iclass 26, count 0 2006.203.07:57:01.91#ibcon#enter sib2, iclass 26, count 0 2006.203.07:57:01.91#ibcon#flushed, iclass 26, count 0 2006.203.07:57:01.91#ibcon#about to write, iclass 26, count 0 2006.203.07:57:01.91#ibcon#wrote, iclass 26, count 0 2006.203.07:57:01.91#ibcon#about to read 3, iclass 26, count 0 2006.203.07:57:01.93#ibcon#read 3, iclass 26, count 0 2006.203.07:57:01.93#ibcon#about to read 4, iclass 26, count 0 2006.203.07:57:01.93#ibcon#read 4, iclass 26, count 0 2006.203.07:57:01.93#ibcon#about to read 5, iclass 26, count 0 2006.203.07:57:01.93#ibcon#read 5, iclass 26, count 0 2006.203.07:57:01.93#ibcon#about to read 6, iclass 26, count 0 2006.203.07:57:01.93#ibcon#read 6, iclass 26, count 0 2006.203.07:57:01.93#ibcon#end of sib2, iclass 26, count 0 2006.203.07:57:01.93#ibcon#*mode == 0, iclass 26, count 0 2006.203.07:57:01.93#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.203.07:57:01.93#ibcon#[28=FRQ=01,632.99\r\n] 2006.203.07:57:01.93#ibcon#*before write, iclass 26, count 0 2006.203.07:57:01.93#ibcon#enter sib2, iclass 26, count 0 2006.203.07:57:01.93#ibcon#flushed, iclass 26, count 0 2006.203.07:57:01.93#ibcon#about to write, iclass 26, count 0 2006.203.07:57:01.93#ibcon#wrote, iclass 26, count 0 2006.203.07:57:01.93#ibcon#about to read 3, iclass 26, count 0 2006.203.07:57:01.97#ibcon#read 3, iclass 26, count 0 2006.203.07:57:01.97#ibcon#about to read 4, iclass 26, count 0 2006.203.07:57:01.97#ibcon#read 4, iclass 26, count 0 2006.203.07:57:01.97#ibcon#about to read 5, iclass 26, count 0 2006.203.07:57:01.97#ibcon#read 5, iclass 26, count 0 2006.203.07:57:01.97#ibcon#about to read 6, iclass 26, count 0 2006.203.07:57:01.97#ibcon#read 6, iclass 26, count 0 2006.203.07:57:01.97#ibcon#end of sib2, iclass 26, count 0 2006.203.07:57:01.97#ibcon#*after write, iclass 26, count 0 2006.203.07:57:01.97#ibcon#*before return 0, iclass 26, count 0 2006.203.07:57:01.97#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.203.07:57:01.97#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.203.07:57:01.97#ibcon#about to clear, iclass 26 cls_cnt 0 2006.203.07:57:01.97#ibcon#cleared, iclass 26 cls_cnt 0 2006.203.07:57:01.97$vc4f8/vb=1,4 2006.203.07:57:01.97#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.203.07:57:01.97#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.203.07:57:01.97#ibcon#ireg 11 cls_cnt 2 2006.203.07:57:01.97#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.203.07:57:01.97#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.203.07:57:01.97#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.203.07:57:01.97#ibcon#enter wrdev, iclass 28, count 2 2006.203.07:57:01.97#ibcon#first serial, iclass 28, count 2 2006.203.07:57:01.97#ibcon#enter sib2, iclass 28, count 2 2006.203.07:57:01.97#ibcon#flushed, iclass 28, count 2 2006.203.07:57:01.97#ibcon#about to write, iclass 28, count 2 2006.203.07:57:01.97#ibcon#wrote, iclass 28, count 2 2006.203.07:57:01.97#ibcon#about to read 3, iclass 28, count 2 2006.203.07:57:01.99#ibcon#read 3, iclass 28, count 2 2006.203.07:57:01.99#ibcon#about to read 4, iclass 28, count 2 2006.203.07:57:01.99#ibcon#read 4, iclass 28, count 2 2006.203.07:57:01.99#ibcon#about to read 5, iclass 28, count 2 2006.203.07:57:01.99#ibcon#read 5, iclass 28, count 2 2006.203.07:57:01.99#ibcon#about to read 6, iclass 28, count 2 2006.203.07:57:01.99#ibcon#read 6, iclass 28, count 2 2006.203.07:57:01.99#ibcon#end of sib2, iclass 28, count 2 2006.203.07:57:01.99#ibcon#*mode == 0, iclass 28, count 2 2006.203.07:57:01.99#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.203.07:57:01.99#ibcon#[27=AT01-04\r\n] 2006.203.07:57:01.99#ibcon#*before write, iclass 28, count 2 2006.203.07:57:01.99#ibcon#enter sib2, iclass 28, count 2 2006.203.07:57:01.99#ibcon#flushed, iclass 28, count 2 2006.203.07:57:01.99#ibcon#about to write, iclass 28, count 2 2006.203.07:57:01.99#ibcon#wrote, iclass 28, count 2 2006.203.07:57:01.99#ibcon#about to read 3, iclass 28, count 2 2006.203.07:57:02.02#ibcon#read 3, iclass 28, count 2 2006.203.07:57:02.02#ibcon#about to read 4, iclass 28, count 2 2006.203.07:57:02.02#ibcon#read 4, iclass 28, count 2 2006.203.07:57:02.02#ibcon#about to read 5, iclass 28, count 2 2006.203.07:57:02.02#ibcon#read 5, iclass 28, count 2 2006.203.07:57:02.02#ibcon#about to read 6, iclass 28, count 2 2006.203.07:57:02.02#ibcon#read 6, iclass 28, count 2 2006.203.07:57:02.02#ibcon#end of sib2, iclass 28, count 2 2006.203.07:57:02.02#ibcon#*after write, iclass 28, count 2 2006.203.07:57:02.02#ibcon#*before return 0, iclass 28, count 2 2006.203.07:57:02.02#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.203.07:57:02.02#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.203.07:57:02.02#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.203.07:57:02.02#ibcon#ireg 7 cls_cnt 0 2006.203.07:57:02.02#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.203.07:57:02.14#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.203.07:57:02.14#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.203.07:57:02.14#ibcon#enter wrdev, iclass 28, count 0 2006.203.07:57:02.14#ibcon#first serial, iclass 28, count 0 2006.203.07:57:02.14#ibcon#enter sib2, iclass 28, count 0 2006.203.07:57:02.14#ibcon#flushed, iclass 28, count 0 2006.203.07:57:02.14#ibcon#about to write, iclass 28, count 0 2006.203.07:57:02.14#ibcon#wrote, iclass 28, count 0 2006.203.07:57:02.14#ibcon#about to read 3, iclass 28, count 0 2006.203.07:57:02.16#ibcon#read 3, iclass 28, count 0 2006.203.07:57:02.16#ibcon#about to read 4, iclass 28, count 0 2006.203.07:57:02.16#ibcon#read 4, iclass 28, count 0 2006.203.07:57:02.16#ibcon#about to read 5, iclass 28, count 0 2006.203.07:57:02.16#ibcon#read 5, iclass 28, count 0 2006.203.07:57:02.16#ibcon#about to read 6, iclass 28, count 0 2006.203.07:57:02.16#ibcon#read 6, iclass 28, count 0 2006.203.07:57:02.16#ibcon#end of sib2, iclass 28, count 0 2006.203.07:57:02.16#ibcon#*mode == 0, iclass 28, count 0 2006.203.07:57:02.16#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.203.07:57:02.16#ibcon#[27=USB\r\n] 2006.203.07:57:02.16#ibcon#*before write, iclass 28, count 0 2006.203.07:57:02.16#ibcon#enter sib2, iclass 28, count 0 2006.203.07:57:02.16#ibcon#flushed, iclass 28, count 0 2006.203.07:57:02.16#ibcon#about to write, iclass 28, count 0 2006.203.07:57:02.16#ibcon#wrote, iclass 28, count 0 2006.203.07:57:02.16#ibcon#about to read 3, iclass 28, count 0 2006.203.07:57:02.19#ibcon#read 3, iclass 28, count 0 2006.203.07:57:02.19#ibcon#about to read 4, iclass 28, count 0 2006.203.07:57:02.19#ibcon#read 4, iclass 28, count 0 2006.203.07:57:02.19#ibcon#about to read 5, iclass 28, count 0 2006.203.07:57:02.19#ibcon#read 5, iclass 28, count 0 2006.203.07:57:02.19#ibcon#about to read 6, iclass 28, count 0 2006.203.07:57:02.19#ibcon#read 6, iclass 28, count 0 2006.203.07:57:02.19#ibcon#end of sib2, iclass 28, count 0 2006.203.07:57:02.19#ibcon#*after write, iclass 28, count 0 2006.203.07:57:02.19#ibcon#*before return 0, iclass 28, count 0 2006.203.07:57:02.19#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.203.07:57:02.19#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.203.07:57:02.19#ibcon#about to clear, iclass 28 cls_cnt 0 2006.203.07:57:02.19#ibcon#cleared, iclass 28 cls_cnt 0 2006.203.07:57:02.19$vc4f8/vblo=2,640.99 2006.203.07:57:02.19#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.203.07:57:02.19#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.203.07:57:02.19#ibcon#ireg 17 cls_cnt 0 2006.203.07:57:02.19#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.203.07:57:02.19#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.203.07:57:02.19#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.203.07:57:02.19#ibcon#enter wrdev, iclass 30, count 0 2006.203.07:57:02.19#ibcon#first serial, iclass 30, count 0 2006.203.07:57:02.19#ibcon#enter sib2, iclass 30, count 0 2006.203.07:57:02.19#ibcon#flushed, iclass 30, count 0 2006.203.07:57:02.19#ibcon#about to write, iclass 30, count 0 2006.203.07:57:02.19#ibcon#wrote, iclass 30, count 0 2006.203.07:57:02.19#ibcon#about to read 3, iclass 30, count 0 2006.203.07:57:02.21#ibcon#read 3, iclass 30, count 0 2006.203.07:57:02.21#ibcon#about to read 4, iclass 30, count 0 2006.203.07:57:02.21#ibcon#read 4, iclass 30, count 0 2006.203.07:57:02.21#ibcon#about to read 5, iclass 30, count 0 2006.203.07:57:02.21#ibcon#read 5, iclass 30, count 0 2006.203.07:57:02.21#ibcon#about to read 6, iclass 30, count 0 2006.203.07:57:02.21#ibcon#read 6, iclass 30, count 0 2006.203.07:57:02.21#ibcon#end of sib2, iclass 30, count 0 2006.203.07:57:02.21#ibcon#*mode == 0, iclass 30, count 0 2006.203.07:57:02.21#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.203.07:57:02.21#ibcon#[28=FRQ=02,640.99\r\n] 2006.203.07:57:02.21#ibcon#*before write, iclass 30, count 0 2006.203.07:57:02.21#ibcon#enter sib2, iclass 30, count 0 2006.203.07:57:02.21#ibcon#flushed, iclass 30, count 0 2006.203.07:57:02.21#ibcon#about to write, iclass 30, count 0 2006.203.07:57:02.21#ibcon#wrote, iclass 30, count 0 2006.203.07:57:02.21#ibcon#about to read 3, iclass 30, count 0 2006.203.07:57:02.25#ibcon#read 3, iclass 30, count 0 2006.203.07:57:02.25#ibcon#about to read 4, iclass 30, count 0 2006.203.07:57:02.25#ibcon#read 4, iclass 30, count 0 2006.203.07:57:02.25#ibcon#about to read 5, iclass 30, count 0 2006.203.07:57:02.25#ibcon#read 5, iclass 30, count 0 2006.203.07:57:02.25#ibcon#about to read 6, iclass 30, count 0 2006.203.07:57:02.25#ibcon#read 6, iclass 30, count 0 2006.203.07:57:02.25#ibcon#end of sib2, iclass 30, count 0 2006.203.07:57:02.25#ibcon#*after write, iclass 30, count 0 2006.203.07:57:02.25#ibcon#*before return 0, iclass 30, count 0 2006.203.07:57:02.25#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.203.07:57:02.25#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.203.07:57:02.25#ibcon#about to clear, iclass 30 cls_cnt 0 2006.203.07:57:02.25#ibcon#cleared, iclass 30 cls_cnt 0 2006.203.07:57:02.25$vc4f8/vb=2,4 2006.203.07:57:02.25#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.203.07:57:02.25#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.203.07:57:02.25#ibcon#ireg 11 cls_cnt 2 2006.203.07:57:02.25#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.203.07:57:02.31#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.203.07:57:02.31#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.203.07:57:02.31#ibcon#enter wrdev, iclass 32, count 2 2006.203.07:57:02.31#ibcon#first serial, iclass 32, count 2 2006.203.07:57:02.31#ibcon#enter sib2, iclass 32, count 2 2006.203.07:57:02.31#ibcon#flushed, iclass 32, count 2 2006.203.07:57:02.31#ibcon#about to write, iclass 32, count 2 2006.203.07:57:02.31#ibcon#wrote, iclass 32, count 2 2006.203.07:57:02.31#ibcon#about to read 3, iclass 32, count 2 2006.203.07:57:02.34#ibcon#read 3, iclass 32, count 2 2006.203.07:57:02.34#ibcon#about to read 4, iclass 32, count 2 2006.203.07:57:02.34#ibcon#read 4, iclass 32, count 2 2006.203.07:57:02.34#ibcon#about to read 5, iclass 32, count 2 2006.203.07:57:02.34#ibcon#read 5, iclass 32, count 2 2006.203.07:57:02.34#ibcon#about to read 6, iclass 32, count 2 2006.203.07:57:02.34#ibcon#read 6, iclass 32, count 2 2006.203.07:57:02.34#ibcon#end of sib2, iclass 32, count 2 2006.203.07:57:02.34#ibcon#*mode == 0, iclass 32, count 2 2006.203.07:57:02.34#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.203.07:57:02.34#ibcon#[27=AT02-04\r\n] 2006.203.07:57:02.34#ibcon#*before write, iclass 32, count 2 2006.203.07:57:02.34#ibcon#enter sib2, iclass 32, count 2 2006.203.07:57:02.34#ibcon#flushed, iclass 32, count 2 2006.203.07:57:02.34#ibcon#about to write, iclass 32, count 2 2006.203.07:57:02.34#ibcon#wrote, iclass 32, count 2 2006.203.07:57:02.34#ibcon#about to read 3, iclass 32, count 2 2006.203.07:57:02.37#ibcon#read 3, iclass 32, count 2 2006.203.07:57:02.37#ibcon#about to read 4, iclass 32, count 2 2006.203.07:57:02.37#ibcon#read 4, iclass 32, count 2 2006.203.07:57:02.37#ibcon#about to read 5, iclass 32, count 2 2006.203.07:57:02.37#ibcon#read 5, iclass 32, count 2 2006.203.07:57:02.37#ibcon#about to read 6, iclass 32, count 2 2006.203.07:57:02.37#ibcon#read 6, iclass 32, count 2 2006.203.07:57:02.37#ibcon#end of sib2, iclass 32, count 2 2006.203.07:57:02.37#ibcon#*after write, iclass 32, count 2 2006.203.07:57:02.37#ibcon#*before return 0, iclass 32, count 2 2006.203.07:57:02.37#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.203.07:57:02.37#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.203.07:57:02.37#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.203.07:57:02.37#ibcon#ireg 7 cls_cnt 0 2006.203.07:57:02.37#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.203.07:57:02.49#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.203.07:57:02.49#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.203.07:57:02.49#ibcon#enter wrdev, iclass 32, count 0 2006.203.07:57:02.49#ibcon#first serial, iclass 32, count 0 2006.203.07:57:02.49#ibcon#enter sib2, iclass 32, count 0 2006.203.07:57:02.49#ibcon#flushed, iclass 32, count 0 2006.203.07:57:02.49#ibcon#about to write, iclass 32, count 0 2006.203.07:57:02.49#ibcon#wrote, iclass 32, count 0 2006.203.07:57:02.49#ibcon#about to read 3, iclass 32, count 0 2006.203.07:57:02.51#ibcon#read 3, iclass 32, count 0 2006.203.07:57:02.51#ibcon#about to read 4, iclass 32, count 0 2006.203.07:57:02.51#ibcon#read 4, iclass 32, count 0 2006.203.07:57:02.51#ibcon#about to read 5, iclass 32, count 0 2006.203.07:57:02.51#ibcon#read 5, iclass 32, count 0 2006.203.07:57:02.51#ibcon#about to read 6, iclass 32, count 0 2006.203.07:57:02.51#ibcon#read 6, iclass 32, count 0 2006.203.07:57:02.51#ibcon#end of sib2, iclass 32, count 0 2006.203.07:57:02.51#ibcon#*mode == 0, iclass 32, count 0 2006.203.07:57:02.51#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.203.07:57:02.51#ibcon#[27=USB\r\n] 2006.203.07:57:02.51#ibcon#*before write, iclass 32, count 0 2006.203.07:57:02.51#ibcon#enter sib2, iclass 32, count 0 2006.203.07:57:02.51#ibcon#flushed, iclass 32, count 0 2006.203.07:57:02.51#ibcon#about to write, iclass 32, count 0 2006.203.07:57:02.51#ibcon#wrote, iclass 32, count 0 2006.203.07:57:02.51#ibcon#about to read 3, iclass 32, count 0 2006.203.07:57:02.54#ibcon#read 3, iclass 32, count 0 2006.203.07:57:02.54#ibcon#about to read 4, iclass 32, count 0 2006.203.07:57:02.54#ibcon#read 4, iclass 32, count 0 2006.203.07:57:02.54#ibcon#about to read 5, iclass 32, count 0 2006.203.07:57:02.54#ibcon#read 5, iclass 32, count 0 2006.203.07:57:02.54#ibcon#about to read 6, iclass 32, count 0 2006.203.07:57:02.54#ibcon#read 6, iclass 32, count 0 2006.203.07:57:02.54#ibcon#end of sib2, iclass 32, count 0 2006.203.07:57:02.54#ibcon#*after write, iclass 32, count 0 2006.203.07:57:02.54#ibcon#*before return 0, iclass 32, count 0 2006.203.07:57:02.54#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.203.07:57:02.54#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.203.07:57:02.54#ibcon#about to clear, iclass 32 cls_cnt 0 2006.203.07:57:02.54#ibcon#cleared, iclass 32 cls_cnt 0 2006.203.07:57:02.54$vc4f8/vblo=3,656.99 2006.203.07:57:02.54#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.203.07:57:02.54#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.203.07:57:02.54#ibcon#ireg 17 cls_cnt 0 2006.203.07:57:02.54#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.203.07:57:02.54#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.203.07:57:02.54#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.203.07:57:02.54#ibcon#enter wrdev, iclass 34, count 0 2006.203.07:57:02.54#ibcon#first serial, iclass 34, count 0 2006.203.07:57:02.54#ibcon#enter sib2, iclass 34, count 0 2006.203.07:57:02.54#ibcon#flushed, iclass 34, count 0 2006.203.07:57:02.54#ibcon#about to write, iclass 34, count 0 2006.203.07:57:02.54#ibcon#wrote, iclass 34, count 0 2006.203.07:57:02.54#ibcon#about to read 3, iclass 34, count 0 2006.203.07:57:02.56#ibcon#read 3, iclass 34, count 0 2006.203.07:57:02.56#ibcon#about to read 4, iclass 34, count 0 2006.203.07:57:02.56#ibcon#read 4, iclass 34, count 0 2006.203.07:57:02.56#ibcon#about to read 5, iclass 34, count 0 2006.203.07:57:02.56#ibcon#read 5, iclass 34, count 0 2006.203.07:57:02.56#ibcon#about to read 6, iclass 34, count 0 2006.203.07:57:02.56#ibcon#read 6, iclass 34, count 0 2006.203.07:57:02.56#ibcon#end of sib2, iclass 34, count 0 2006.203.07:57:02.56#ibcon#*mode == 0, iclass 34, count 0 2006.203.07:57:02.56#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.203.07:57:02.56#ibcon#[28=FRQ=03,656.99\r\n] 2006.203.07:57:02.56#ibcon#*before write, iclass 34, count 0 2006.203.07:57:02.56#ibcon#enter sib2, iclass 34, count 0 2006.203.07:57:02.56#ibcon#flushed, iclass 34, count 0 2006.203.07:57:02.56#ibcon#about to write, iclass 34, count 0 2006.203.07:57:02.56#ibcon#wrote, iclass 34, count 0 2006.203.07:57:02.56#ibcon#about to read 3, iclass 34, count 0 2006.203.07:57:02.60#ibcon#read 3, iclass 34, count 0 2006.203.07:57:02.60#ibcon#about to read 4, iclass 34, count 0 2006.203.07:57:02.60#ibcon#read 4, iclass 34, count 0 2006.203.07:57:02.60#ibcon#about to read 5, iclass 34, count 0 2006.203.07:57:02.60#ibcon#read 5, iclass 34, count 0 2006.203.07:57:02.60#ibcon#about to read 6, iclass 34, count 0 2006.203.07:57:02.60#ibcon#read 6, iclass 34, count 0 2006.203.07:57:02.60#ibcon#end of sib2, iclass 34, count 0 2006.203.07:57:02.60#ibcon#*after write, iclass 34, count 0 2006.203.07:57:02.60#ibcon#*before return 0, iclass 34, count 0 2006.203.07:57:02.60#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.203.07:57:02.60#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.203.07:57:02.60#ibcon#about to clear, iclass 34 cls_cnt 0 2006.203.07:57:02.60#ibcon#cleared, iclass 34 cls_cnt 0 2006.203.07:57:02.60$vc4f8/vb=3,4 2006.203.07:57:02.60#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.203.07:57:02.60#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.203.07:57:02.60#ibcon#ireg 11 cls_cnt 2 2006.203.07:57:02.60#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.203.07:57:02.66#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.203.07:57:02.66#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.203.07:57:02.66#ibcon#enter wrdev, iclass 36, count 2 2006.203.07:57:02.66#ibcon#first serial, iclass 36, count 2 2006.203.07:57:02.66#ibcon#enter sib2, iclass 36, count 2 2006.203.07:57:02.66#ibcon#flushed, iclass 36, count 2 2006.203.07:57:02.66#ibcon#about to write, iclass 36, count 2 2006.203.07:57:02.66#ibcon#wrote, iclass 36, count 2 2006.203.07:57:02.66#ibcon#about to read 3, iclass 36, count 2 2006.203.07:57:02.68#ibcon#read 3, iclass 36, count 2 2006.203.07:57:02.68#ibcon#about to read 4, iclass 36, count 2 2006.203.07:57:02.68#ibcon#read 4, iclass 36, count 2 2006.203.07:57:02.68#ibcon#about to read 5, iclass 36, count 2 2006.203.07:57:02.68#ibcon#read 5, iclass 36, count 2 2006.203.07:57:02.68#ibcon#about to read 6, iclass 36, count 2 2006.203.07:57:02.68#ibcon#read 6, iclass 36, count 2 2006.203.07:57:02.68#ibcon#end of sib2, iclass 36, count 2 2006.203.07:57:02.68#ibcon#*mode == 0, iclass 36, count 2 2006.203.07:57:02.68#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.203.07:57:02.68#ibcon#[27=AT03-04\r\n] 2006.203.07:57:02.68#ibcon#*before write, iclass 36, count 2 2006.203.07:57:02.68#ibcon#enter sib2, iclass 36, count 2 2006.203.07:57:02.68#ibcon#flushed, iclass 36, count 2 2006.203.07:57:02.68#ibcon#about to write, iclass 36, count 2 2006.203.07:57:02.68#ibcon#wrote, iclass 36, count 2 2006.203.07:57:02.68#ibcon#about to read 3, iclass 36, count 2 2006.203.07:57:02.71#ibcon#read 3, iclass 36, count 2 2006.203.07:57:02.71#ibcon#about to read 4, iclass 36, count 2 2006.203.07:57:02.71#ibcon#read 4, iclass 36, count 2 2006.203.07:57:02.71#ibcon#about to read 5, iclass 36, count 2 2006.203.07:57:02.71#ibcon#read 5, iclass 36, count 2 2006.203.07:57:02.71#ibcon#about to read 6, iclass 36, count 2 2006.203.07:57:02.71#ibcon#read 6, iclass 36, count 2 2006.203.07:57:02.71#ibcon#end of sib2, iclass 36, count 2 2006.203.07:57:02.71#ibcon#*after write, iclass 36, count 2 2006.203.07:57:02.71#ibcon#*before return 0, iclass 36, count 2 2006.203.07:57:02.71#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.203.07:57:02.71#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.203.07:57:02.71#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.203.07:57:02.71#ibcon#ireg 7 cls_cnt 0 2006.203.07:57:02.71#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.203.07:57:02.83#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.203.07:57:02.83#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.203.07:57:02.83#ibcon#enter wrdev, iclass 36, count 0 2006.203.07:57:02.83#ibcon#first serial, iclass 36, count 0 2006.203.07:57:02.83#ibcon#enter sib2, iclass 36, count 0 2006.203.07:57:02.83#ibcon#flushed, iclass 36, count 0 2006.203.07:57:02.83#ibcon#about to write, iclass 36, count 0 2006.203.07:57:02.83#ibcon#wrote, iclass 36, count 0 2006.203.07:57:02.83#ibcon#about to read 3, iclass 36, count 0 2006.203.07:57:02.85#ibcon#read 3, iclass 36, count 0 2006.203.07:57:02.85#ibcon#about to read 4, iclass 36, count 0 2006.203.07:57:02.85#ibcon#read 4, iclass 36, count 0 2006.203.07:57:02.85#ibcon#about to read 5, iclass 36, count 0 2006.203.07:57:02.85#ibcon#read 5, iclass 36, count 0 2006.203.07:57:02.85#ibcon#about to read 6, iclass 36, count 0 2006.203.07:57:02.85#ibcon#read 6, iclass 36, count 0 2006.203.07:57:02.85#ibcon#end of sib2, iclass 36, count 0 2006.203.07:57:02.85#ibcon#*mode == 0, iclass 36, count 0 2006.203.07:57:02.85#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.203.07:57:02.85#ibcon#[27=USB\r\n] 2006.203.07:57:02.85#ibcon#*before write, iclass 36, count 0 2006.203.07:57:02.85#ibcon#enter sib2, iclass 36, count 0 2006.203.07:57:02.85#ibcon#flushed, iclass 36, count 0 2006.203.07:57:02.85#ibcon#about to write, iclass 36, count 0 2006.203.07:57:02.85#ibcon#wrote, iclass 36, count 0 2006.203.07:57:02.85#ibcon#about to read 3, iclass 36, count 0 2006.203.07:57:02.88#ibcon#read 3, iclass 36, count 0 2006.203.07:57:02.88#ibcon#about to read 4, iclass 36, count 0 2006.203.07:57:02.88#ibcon#read 4, iclass 36, count 0 2006.203.07:57:02.88#ibcon#about to read 5, iclass 36, count 0 2006.203.07:57:02.88#ibcon#read 5, iclass 36, count 0 2006.203.07:57:02.88#ibcon#about to read 6, iclass 36, count 0 2006.203.07:57:02.88#ibcon#read 6, iclass 36, count 0 2006.203.07:57:02.88#ibcon#end of sib2, iclass 36, count 0 2006.203.07:57:02.88#ibcon#*after write, iclass 36, count 0 2006.203.07:57:02.88#ibcon#*before return 0, iclass 36, count 0 2006.203.07:57:02.88#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.203.07:57:02.88#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.203.07:57:02.88#ibcon#about to clear, iclass 36 cls_cnt 0 2006.203.07:57:02.88#ibcon#cleared, iclass 36 cls_cnt 0 2006.203.07:57:02.88$vc4f8/vblo=4,712.99 2006.203.07:57:02.88#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.203.07:57:02.88#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.203.07:57:02.88#ibcon#ireg 17 cls_cnt 0 2006.203.07:57:02.88#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.203.07:57:02.88#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.203.07:57:02.88#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.203.07:57:02.88#ibcon#enter wrdev, iclass 38, count 0 2006.203.07:57:02.88#ibcon#first serial, iclass 38, count 0 2006.203.07:57:02.88#ibcon#enter sib2, iclass 38, count 0 2006.203.07:57:02.88#ibcon#flushed, iclass 38, count 0 2006.203.07:57:02.88#ibcon#about to write, iclass 38, count 0 2006.203.07:57:02.88#ibcon#wrote, iclass 38, count 0 2006.203.07:57:02.88#ibcon#about to read 3, iclass 38, count 0 2006.203.07:57:02.90#ibcon#read 3, iclass 38, count 0 2006.203.07:57:02.90#ibcon#about to read 4, iclass 38, count 0 2006.203.07:57:02.90#ibcon#read 4, iclass 38, count 0 2006.203.07:57:02.90#ibcon#about to read 5, iclass 38, count 0 2006.203.07:57:02.90#ibcon#read 5, iclass 38, count 0 2006.203.07:57:02.90#ibcon#about to read 6, iclass 38, count 0 2006.203.07:57:02.90#ibcon#read 6, iclass 38, count 0 2006.203.07:57:02.90#ibcon#end of sib2, iclass 38, count 0 2006.203.07:57:02.90#ibcon#*mode == 0, iclass 38, count 0 2006.203.07:57:02.90#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.203.07:57:02.90#ibcon#[28=FRQ=04,712.99\r\n] 2006.203.07:57:02.90#ibcon#*before write, iclass 38, count 0 2006.203.07:57:02.90#ibcon#enter sib2, iclass 38, count 0 2006.203.07:57:02.90#ibcon#flushed, iclass 38, count 0 2006.203.07:57:02.90#ibcon#about to write, iclass 38, count 0 2006.203.07:57:02.90#ibcon#wrote, iclass 38, count 0 2006.203.07:57:02.90#ibcon#about to read 3, iclass 38, count 0 2006.203.07:57:02.94#ibcon#read 3, iclass 38, count 0 2006.203.07:57:02.94#ibcon#about to read 4, iclass 38, count 0 2006.203.07:57:02.94#ibcon#read 4, iclass 38, count 0 2006.203.07:57:02.94#ibcon#about to read 5, iclass 38, count 0 2006.203.07:57:02.94#ibcon#read 5, iclass 38, count 0 2006.203.07:57:02.94#ibcon#about to read 6, iclass 38, count 0 2006.203.07:57:02.94#ibcon#read 6, iclass 38, count 0 2006.203.07:57:02.94#ibcon#end of sib2, iclass 38, count 0 2006.203.07:57:02.94#ibcon#*after write, iclass 38, count 0 2006.203.07:57:02.94#ibcon#*before return 0, iclass 38, count 0 2006.203.07:57:02.94#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.203.07:57:02.94#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.203.07:57:02.94#ibcon#about to clear, iclass 38 cls_cnt 0 2006.203.07:57:02.94#ibcon#cleared, iclass 38 cls_cnt 0 2006.203.07:57:02.94$vc4f8/vb=4,4 2006.203.07:57:02.94#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.203.07:57:02.94#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.203.07:57:02.94#ibcon#ireg 11 cls_cnt 2 2006.203.07:57:02.94#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.203.07:57:03.00#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.203.07:57:03.00#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.203.07:57:03.00#ibcon#enter wrdev, iclass 40, count 2 2006.203.07:57:03.00#ibcon#first serial, iclass 40, count 2 2006.203.07:57:03.00#ibcon#enter sib2, iclass 40, count 2 2006.203.07:57:03.00#ibcon#flushed, iclass 40, count 2 2006.203.07:57:03.00#ibcon#about to write, iclass 40, count 2 2006.203.07:57:03.00#ibcon#wrote, iclass 40, count 2 2006.203.07:57:03.00#ibcon#about to read 3, iclass 40, count 2 2006.203.07:57:03.02#ibcon#read 3, iclass 40, count 2 2006.203.07:57:03.02#ibcon#about to read 4, iclass 40, count 2 2006.203.07:57:03.02#ibcon#read 4, iclass 40, count 2 2006.203.07:57:03.02#ibcon#about to read 5, iclass 40, count 2 2006.203.07:57:03.02#ibcon#read 5, iclass 40, count 2 2006.203.07:57:03.02#ibcon#about to read 6, iclass 40, count 2 2006.203.07:57:03.02#ibcon#read 6, iclass 40, count 2 2006.203.07:57:03.02#ibcon#end of sib2, iclass 40, count 2 2006.203.07:57:03.02#ibcon#*mode == 0, iclass 40, count 2 2006.203.07:57:03.02#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.203.07:57:03.02#ibcon#[27=AT04-04\r\n] 2006.203.07:57:03.02#ibcon#*before write, iclass 40, count 2 2006.203.07:57:03.02#ibcon#enter sib2, iclass 40, count 2 2006.203.07:57:03.02#ibcon#flushed, iclass 40, count 2 2006.203.07:57:03.02#ibcon#about to write, iclass 40, count 2 2006.203.07:57:03.02#ibcon#wrote, iclass 40, count 2 2006.203.07:57:03.02#ibcon#about to read 3, iclass 40, count 2 2006.203.07:57:03.05#ibcon#read 3, iclass 40, count 2 2006.203.07:57:03.05#ibcon#about to read 4, iclass 40, count 2 2006.203.07:57:03.05#ibcon#read 4, iclass 40, count 2 2006.203.07:57:03.05#ibcon#about to read 5, iclass 40, count 2 2006.203.07:57:03.05#ibcon#read 5, iclass 40, count 2 2006.203.07:57:03.05#ibcon#about to read 6, iclass 40, count 2 2006.203.07:57:03.05#ibcon#read 6, iclass 40, count 2 2006.203.07:57:03.05#ibcon#end of sib2, iclass 40, count 2 2006.203.07:57:03.05#ibcon#*after write, iclass 40, count 2 2006.203.07:57:03.05#ibcon#*before return 0, iclass 40, count 2 2006.203.07:57:03.05#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.203.07:57:03.05#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.203.07:57:03.05#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.203.07:57:03.05#ibcon#ireg 7 cls_cnt 0 2006.203.07:57:03.05#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.203.07:57:03.17#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.203.07:57:03.17#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.203.07:57:03.17#ibcon#enter wrdev, iclass 40, count 0 2006.203.07:57:03.17#ibcon#first serial, iclass 40, count 0 2006.203.07:57:03.17#ibcon#enter sib2, iclass 40, count 0 2006.203.07:57:03.17#ibcon#flushed, iclass 40, count 0 2006.203.07:57:03.17#ibcon#about to write, iclass 40, count 0 2006.203.07:57:03.17#ibcon#wrote, iclass 40, count 0 2006.203.07:57:03.17#ibcon#about to read 3, iclass 40, count 0 2006.203.07:57:03.19#ibcon#read 3, iclass 40, count 0 2006.203.07:57:03.19#ibcon#about to read 4, iclass 40, count 0 2006.203.07:57:03.19#ibcon#read 4, iclass 40, count 0 2006.203.07:57:03.19#ibcon#about to read 5, iclass 40, count 0 2006.203.07:57:03.19#ibcon#read 5, iclass 40, count 0 2006.203.07:57:03.19#ibcon#about to read 6, iclass 40, count 0 2006.203.07:57:03.19#ibcon#read 6, iclass 40, count 0 2006.203.07:57:03.19#ibcon#end of sib2, iclass 40, count 0 2006.203.07:57:03.19#ibcon#*mode == 0, iclass 40, count 0 2006.203.07:57:03.19#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.203.07:57:03.19#ibcon#[27=USB\r\n] 2006.203.07:57:03.19#ibcon#*before write, iclass 40, count 0 2006.203.07:57:03.19#ibcon#enter sib2, iclass 40, count 0 2006.203.07:57:03.19#ibcon#flushed, iclass 40, count 0 2006.203.07:57:03.19#ibcon#about to write, iclass 40, count 0 2006.203.07:57:03.19#ibcon#wrote, iclass 40, count 0 2006.203.07:57:03.19#ibcon#about to read 3, iclass 40, count 0 2006.203.07:57:03.22#ibcon#read 3, iclass 40, count 0 2006.203.07:57:03.22#ibcon#about to read 4, iclass 40, count 0 2006.203.07:57:03.22#ibcon#read 4, iclass 40, count 0 2006.203.07:57:03.22#ibcon#about to read 5, iclass 40, count 0 2006.203.07:57:03.22#ibcon#read 5, iclass 40, count 0 2006.203.07:57:03.22#ibcon#about to read 6, iclass 40, count 0 2006.203.07:57:03.22#ibcon#read 6, iclass 40, count 0 2006.203.07:57:03.22#ibcon#end of sib2, iclass 40, count 0 2006.203.07:57:03.22#ibcon#*after write, iclass 40, count 0 2006.203.07:57:03.22#ibcon#*before return 0, iclass 40, count 0 2006.203.07:57:03.22#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.203.07:57:03.22#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.203.07:57:03.22#ibcon#about to clear, iclass 40 cls_cnt 0 2006.203.07:57:03.22#ibcon#cleared, iclass 40 cls_cnt 0 2006.203.07:57:03.22$vc4f8/vblo=5,744.99 2006.203.07:57:03.22#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.203.07:57:03.22#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.203.07:57:03.22#ibcon#ireg 17 cls_cnt 0 2006.203.07:57:03.22#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.203.07:57:03.22#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.203.07:57:03.22#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.203.07:57:03.22#ibcon#enter wrdev, iclass 4, count 0 2006.203.07:57:03.22#ibcon#first serial, iclass 4, count 0 2006.203.07:57:03.22#ibcon#enter sib2, iclass 4, count 0 2006.203.07:57:03.22#ibcon#flushed, iclass 4, count 0 2006.203.07:57:03.22#ibcon#about to write, iclass 4, count 0 2006.203.07:57:03.22#ibcon#wrote, iclass 4, count 0 2006.203.07:57:03.22#ibcon#about to read 3, iclass 4, count 0 2006.203.07:57:03.24#ibcon#read 3, iclass 4, count 0 2006.203.07:57:03.24#ibcon#about to read 4, iclass 4, count 0 2006.203.07:57:03.24#ibcon#read 4, iclass 4, count 0 2006.203.07:57:03.24#ibcon#about to read 5, iclass 4, count 0 2006.203.07:57:03.24#ibcon#read 5, iclass 4, count 0 2006.203.07:57:03.24#ibcon#about to read 6, iclass 4, count 0 2006.203.07:57:03.24#ibcon#read 6, iclass 4, count 0 2006.203.07:57:03.24#ibcon#end of sib2, iclass 4, count 0 2006.203.07:57:03.24#ibcon#*mode == 0, iclass 4, count 0 2006.203.07:57:03.24#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.203.07:57:03.24#ibcon#[28=FRQ=05,744.99\r\n] 2006.203.07:57:03.24#ibcon#*before write, iclass 4, count 0 2006.203.07:57:03.24#ibcon#enter sib2, iclass 4, count 0 2006.203.07:57:03.24#ibcon#flushed, iclass 4, count 0 2006.203.07:57:03.24#ibcon#about to write, iclass 4, count 0 2006.203.07:57:03.24#ibcon#wrote, iclass 4, count 0 2006.203.07:57:03.24#ibcon#about to read 3, iclass 4, count 0 2006.203.07:57:03.28#ibcon#read 3, iclass 4, count 0 2006.203.07:57:03.28#ibcon#about to read 4, iclass 4, count 0 2006.203.07:57:03.28#ibcon#read 4, iclass 4, count 0 2006.203.07:57:03.28#ibcon#about to read 5, iclass 4, count 0 2006.203.07:57:03.28#ibcon#read 5, iclass 4, count 0 2006.203.07:57:03.28#ibcon#about to read 6, iclass 4, count 0 2006.203.07:57:03.28#ibcon#read 6, iclass 4, count 0 2006.203.07:57:03.28#ibcon#end of sib2, iclass 4, count 0 2006.203.07:57:03.28#ibcon#*after write, iclass 4, count 0 2006.203.07:57:03.28#ibcon#*before return 0, iclass 4, count 0 2006.203.07:57:03.28#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.203.07:57:03.28#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.203.07:57:03.28#ibcon#about to clear, iclass 4 cls_cnt 0 2006.203.07:57:03.28#ibcon#cleared, iclass 4 cls_cnt 0 2006.203.07:57:03.28$vc4f8/vb=5,3 2006.203.07:57:03.28#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.203.07:57:03.28#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.203.07:57:03.28#ibcon#ireg 11 cls_cnt 2 2006.203.07:57:03.28#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.203.07:57:03.34#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.203.07:57:03.34#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.203.07:57:03.34#ibcon#enter wrdev, iclass 6, count 2 2006.203.07:57:03.34#ibcon#first serial, iclass 6, count 2 2006.203.07:57:03.34#ibcon#enter sib2, iclass 6, count 2 2006.203.07:57:03.34#ibcon#flushed, iclass 6, count 2 2006.203.07:57:03.34#ibcon#about to write, iclass 6, count 2 2006.203.07:57:03.34#ibcon#wrote, iclass 6, count 2 2006.203.07:57:03.34#ibcon#about to read 3, iclass 6, count 2 2006.203.07:57:03.36#ibcon#read 3, iclass 6, count 2 2006.203.07:57:03.36#ibcon#about to read 4, iclass 6, count 2 2006.203.07:57:03.36#ibcon#read 4, iclass 6, count 2 2006.203.07:57:03.36#ibcon#about to read 5, iclass 6, count 2 2006.203.07:57:03.36#ibcon#read 5, iclass 6, count 2 2006.203.07:57:03.36#ibcon#about to read 6, iclass 6, count 2 2006.203.07:57:03.36#ibcon#read 6, iclass 6, count 2 2006.203.07:57:03.36#ibcon#end of sib2, iclass 6, count 2 2006.203.07:57:03.36#ibcon#*mode == 0, iclass 6, count 2 2006.203.07:57:03.36#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.203.07:57:03.36#ibcon#[27=AT05-03\r\n] 2006.203.07:57:03.36#ibcon#*before write, iclass 6, count 2 2006.203.07:57:03.36#ibcon#enter sib2, iclass 6, count 2 2006.203.07:57:03.36#ibcon#flushed, iclass 6, count 2 2006.203.07:57:03.36#ibcon#about to write, iclass 6, count 2 2006.203.07:57:03.36#ibcon#wrote, iclass 6, count 2 2006.203.07:57:03.36#ibcon#about to read 3, iclass 6, count 2 2006.203.07:57:03.39#ibcon#read 3, iclass 6, count 2 2006.203.07:57:03.39#ibcon#about to read 4, iclass 6, count 2 2006.203.07:57:03.39#ibcon#read 4, iclass 6, count 2 2006.203.07:57:03.39#ibcon#about to read 5, iclass 6, count 2 2006.203.07:57:03.39#ibcon#read 5, iclass 6, count 2 2006.203.07:57:03.39#ibcon#about to read 6, iclass 6, count 2 2006.203.07:57:03.39#ibcon#read 6, iclass 6, count 2 2006.203.07:57:03.39#ibcon#end of sib2, iclass 6, count 2 2006.203.07:57:03.39#ibcon#*after write, iclass 6, count 2 2006.203.07:57:03.39#ibcon#*before return 0, iclass 6, count 2 2006.203.07:57:03.39#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.203.07:57:03.39#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.203.07:57:03.39#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.203.07:57:03.39#ibcon#ireg 7 cls_cnt 0 2006.203.07:57:03.39#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.203.07:57:03.51#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.203.07:57:03.51#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.203.07:57:03.51#ibcon#enter wrdev, iclass 6, count 0 2006.203.07:57:03.51#ibcon#first serial, iclass 6, count 0 2006.203.07:57:03.51#ibcon#enter sib2, iclass 6, count 0 2006.203.07:57:03.51#ibcon#flushed, iclass 6, count 0 2006.203.07:57:03.51#ibcon#about to write, iclass 6, count 0 2006.203.07:57:03.51#ibcon#wrote, iclass 6, count 0 2006.203.07:57:03.51#ibcon#about to read 3, iclass 6, count 0 2006.203.07:57:03.53#ibcon#read 3, iclass 6, count 0 2006.203.07:57:03.53#ibcon#about to read 4, iclass 6, count 0 2006.203.07:57:03.53#ibcon#read 4, iclass 6, count 0 2006.203.07:57:03.53#ibcon#about to read 5, iclass 6, count 0 2006.203.07:57:03.53#ibcon#read 5, iclass 6, count 0 2006.203.07:57:03.53#ibcon#about to read 6, iclass 6, count 0 2006.203.07:57:03.53#ibcon#read 6, iclass 6, count 0 2006.203.07:57:03.53#ibcon#end of sib2, iclass 6, count 0 2006.203.07:57:03.53#ibcon#*mode == 0, iclass 6, count 0 2006.203.07:57:03.53#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.203.07:57:03.53#ibcon#[27=USB\r\n] 2006.203.07:57:03.53#ibcon#*before write, iclass 6, count 0 2006.203.07:57:03.53#ibcon#enter sib2, iclass 6, count 0 2006.203.07:57:03.53#ibcon#flushed, iclass 6, count 0 2006.203.07:57:03.53#ibcon#about to write, iclass 6, count 0 2006.203.07:57:03.53#ibcon#wrote, iclass 6, count 0 2006.203.07:57:03.53#ibcon#about to read 3, iclass 6, count 0 2006.203.07:57:03.56#ibcon#read 3, iclass 6, count 0 2006.203.07:57:03.56#ibcon#about to read 4, iclass 6, count 0 2006.203.07:57:03.56#ibcon#read 4, iclass 6, count 0 2006.203.07:57:03.56#ibcon#about to read 5, iclass 6, count 0 2006.203.07:57:03.56#ibcon#read 5, iclass 6, count 0 2006.203.07:57:03.56#ibcon#about to read 6, iclass 6, count 0 2006.203.07:57:03.56#ibcon#read 6, iclass 6, count 0 2006.203.07:57:03.56#ibcon#end of sib2, iclass 6, count 0 2006.203.07:57:03.56#ibcon#*after write, iclass 6, count 0 2006.203.07:57:03.56#ibcon#*before return 0, iclass 6, count 0 2006.203.07:57:03.56#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.203.07:57:03.56#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.203.07:57:03.56#ibcon#about to clear, iclass 6 cls_cnt 0 2006.203.07:57:03.56#ibcon#cleared, iclass 6 cls_cnt 0 2006.203.07:57:03.56$vc4f8/vblo=6,752.99 2006.203.07:57:03.56#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.203.07:57:03.56#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.203.07:57:03.56#ibcon#ireg 17 cls_cnt 0 2006.203.07:57:03.56#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.203.07:57:03.56#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.203.07:57:03.56#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.203.07:57:03.56#ibcon#enter wrdev, iclass 10, count 0 2006.203.07:57:03.56#ibcon#first serial, iclass 10, count 0 2006.203.07:57:03.56#ibcon#enter sib2, iclass 10, count 0 2006.203.07:57:03.56#ibcon#flushed, iclass 10, count 0 2006.203.07:57:03.56#ibcon#about to write, iclass 10, count 0 2006.203.07:57:03.56#ibcon#wrote, iclass 10, count 0 2006.203.07:57:03.56#ibcon#about to read 3, iclass 10, count 0 2006.203.07:57:03.58#ibcon#read 3, iclass 10, count 0 2006.203.07:57:03.58#ibcon#about to read 4, iclass 10, count 0 2006.203.07:57:03.58#ibcon#read 4, iclass 10, count 0 2006.203.07:57:03.58#ibcon#about to read 5, iclass 10, count 0 2006.203.07:57:03.58#ibcon#read 5, iclass 10, count 0 2006.203.07:57:03.58#ibcon#about to read 6, iclass 10, count 0 2006.203.07:57:03.58#ibcon#read 6, iclass 10, count 0 2006.203.07:57:03.58#ibcon#end of sib2, iclass 10, count 0 2006.203.07:57:03.58#ibcon#*mode == 0, iclass 10, count 0 2006.203.07:57:03.58#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.203.07:57:03.58#ibcon#[28=FRQ=06,752.99\r\n] 2006.203.07:57:03.58#ibcon#*before write, iclass 10, count 0 2006.203.07:57:03.58#ibcon#enter sib2, iclass 10, count 0 2006.203.07:57:03.58#ibcon#flushed, iclass 10, count 0 2006.203.07:57:03.58#ibcon#about to write, iclass 10, count 0 2006.203.07:57:03.58#ibcon#wrote, iclass 10, count 0 2006.203.07:57:03.58#ibcon#about to read 3, iclass 10, count 0 2006.203.07:57:03.62#ibcon#read 3, iclass 10, count 0 2006.203.07:57:03.62#ibcon#about to read 4, iclass 10, count 0 2006.203.07:57:03.62#ibcon#read 4, iclass 10, count 0 2006.203.07:57:03.62#ibcon#about to read 5, iclass 10, count 0 2006.203.07:57:03.62#ibcon#read 5, iclass 10, count 0 2006.203.07:57:03.62#ibcon#about to read 6, iclass 10, count 0 2006.203.07:57:03.62#ibcon#read 6, iclass 10, count 0 2006.203.07:57:03.62#ibcon#end of sib2, iclass 10, count 0 2006.203.07:57:03.62#ibcon#*after write, iclass 10, count 0 2006.203.07:57:03.62#ibcon#*before return 0, iclass 10, count 0 2006.203.07:57:03.62#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.203.07:57:03.62#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.203.07:57:03.62#ibcon#about to clear, iclass 10 cls_cnt 0 2006.203.07:57:03.62#ibcon#cleared, iclass 10 cls_cnt 0 2006.203.07:57:03.62$vc4f8/vb=6,4 2006.203.07:57:03.62#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.203.07:57:03.62#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.203.07:57:03.62#ibcon#ireg 11 cls_cnt 2 2006.203.07:57:03.62#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.203.07:57:03.68#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.203.07:57:03.68#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.203.07:57:03.68#ibcon#enter wrdev, iclass 12, count 2 2006.203.07:57:03.68#ibcon#first serial, iclass 12, count 2 2006.203.07:57:03.68#ibcon#enter sib2, iclass 12, count 2 2006.203.07:57:03.68#ibcon#flushed, iclass 12, count 2 2006.203.07:57:03.68#ibcon#about to write, iclass 12, count 2 2006.203.07:57:03.68#ibcon#wrote, iclass 12, count 2 2006.203.07:57:03.68#ibcon#about to read 3, iclass 12, count 2 2006.203.07:57:03.70#ibcon#read 3, iclass 12, count 2 2006.203.07:57:03.70#ibcon#about to read 4, iclass 12, count 2 2006.203.07:57:03.70#ibcon#read 4, iclass 12, count 2 2006.203.07:57:03.70#ibcon#about to read 5, iclass 12, count 2 2006.203.07:57:03.70#ibcon#read 5, iclass 12, count 2 2006.203.07:57:03.70#ibcon#about to read 6, iclass 12, count 2 2006.203.07:57:03.70#ibcon#read 6, iclass 12, count 2 2006.203.07:57:03.70#ibcon#end of sib2, iclass 12, count 2 2006.203.07:57:03.70#ibcon#*mode == 0, iclass 12, count 2 2006.203.07:57:03.70#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.203.07:57:03.70#ibcon#[27=AT06-04\r\n] 2006.203.07:57:03.70#ibcon#*before write, iclass 12, count 2 2006.203.07:57:03.70#ibcon#enter sib2, iclass 12, count 2 2006.203.07:57:03.70#ibcon#flushed, iclass 12, count 2 2006.203.07:57:03.70#ibcon#about to write, iclass 12, count 2 2006.203.07:57:03.70#ibcon#wrote, iclass 12, count 2 2006.203.07:57:03.70#ibcon#about to read 3, iclass 12, count 2 2006.203.07:57:03.73#ibcon#read 3, iclass 12, count 2 2006.203.07:57:03.73#ibcon#about to read 4, iclass 12, count 2 2006.203.07:57:03.73#ibcon#read 4, iclass 12, count 2 2006.203.07:57:03.73#ibcon#about to read 5, iclass 12, count 2 2006.203.07:57:03.73#ibcon#read 5, iclass 12, count 2 2006.203.07:57:03.73#ibcon#about to read 6, iclass 12, count 2 2006.203.07:57:03.73#ibcon#read 6, iclass 12, count 2 2006.203.07:57:03.73#ibcon#end of sib2, iclass 12, count 2 2006.203.07:57:03.73#ibcon#*after write, iclass 12, count 2 2006.203.07:57:03.73#ibcon#*before return 0, iclass 12, count 2 2006.203.07:57:03.73#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.203.07:57:03.73#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.203.07:57:03.73#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.203.07:57:03.73#ibcon#ireg 7 cls_cnt 0 2006.203.07:57:03.73#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.203.07:57:03.85#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.203.07:57:03.85#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.203.07:57:03.85#ibcon#enter wrdev, iclass 12, count 0 2006.203.07:57:03.85#ibcon#first serial, iclass 12, count 0 2006.203.07:57:03.85#ibcon#enter sib2, iclass 12, count 0 2006.203.07:57:03.85#ibcon#flushed, iclass 12, count 0 2006.203.07:57:03.85#ibcon#about to write, iclass 12, count 0 2006.203.07:57:03.85#ibcon#wrote, iclass 12, count 0 2006.203.07:57:03.85#ibcon#about to read 3, iclass 12, count 0 2006.203.07:57:03.87#ibcon#read 3, iclass 12, count 0 2006.203.07:57:03.87#ibcon#about to read 4, iclass 12, count 0 2006.203.07:57:03.87#ibcon#read 4, iclass 12, count 0 2006.203.07:57:03.87#ibcon#about to read 5, iclass 12, count 0 2006.203.07:57:03.87#ibcon#read 5, iclass 12, count 0 2006.203.07:57:03.87#ibcon#about to read 6, iclass 12, count 0 2006.203.07:57:03.87#ibcon#read 6, iclass 12, count 0 2006.203.07:57:03.87#ibcon#end of sib2, iclass 12, count 0 2006.203.07:57:03.87#ibcon#*mode == 0, iclass 12, count 0 2006.203.07:57:03.87#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.203.07:57:03.87#ibcon#[27=USB\r\n] 2006.203.07:57:03.87#ibcon#*before write, iclass 12, count 0 2006.203.07:57:03.87#ibcon#enter sib2, iclass 12, count 0 2006.203.07:57:03.87#ibcon#flushed, iclass 12, count 0 2006.203.07:57:03.87#ibcon#about to write, iclass 12, count 0 2006.203.07:57:03.87#ibcon#wrote, iclass 12, count 0 2006.203.07:57:03.87#ibcon#about to read 3, iclass 12, count 0 2006.203.07:57:03.90#ibcon#read 3, iclass 12, count 0 2006.203.07:57:03.90#ibcon#about to read 4, iclass 12, count 0 2006.203.07:57:03.90#ibcon#read 4, iclass 12, count 0 2006.203.07:57:03.90#ibcon#about to read 5, iclass 12, count 0 2006.203.07:57:03.90#ibcon#read 5, iclass 12, count 0 2006.203.07:57:03.90#ibcon#about to read 6, iclass 12, count 0 2006.203.07:57:03.90#ibcon#read 6, iclass 12, count 0 2006.203.07:57:03.90#ibcon#end of sib2, iclass 12, count 0 2006.203.07:57:03.90#ibcon#*after write, iclass 12, count 0 2006.203.07:57:03.90#ibcon#*before return 0, iclass 12, count 0 2006.203.07:57:03.90#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.203.07:57:03.90#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.203.07:57:03.90#ibcon#about to clear, iclass 12 cls_cnt 0 2006.203.07:57:03.90#ibcon#cleared, iclass 12 cls_cnt 0 2006.203.07:57:03.90$vc4f8/vabw=wide 2006.203.07:57:03.90#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.203.07:57:03.90#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.203.07:57:03.90#ibcon#ireg 8 cls_cnt 0 2006.203.07:57:03.90#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.203.07:57:03.90#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.203.07:57:03.90#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.203.07:57:03.90#ibcon#enter wrdev, iclass 14, count 0 2006.203.07:57:03.90#ibcon#first serial, iclass 14, count 0 2006.203.07:57:03.90#ibcon#enter sib2, iclass 14, count 0 2006.203.07:57:03.90#ibcon#flushed, iclass 14, count 0 2006.203.07:57:03.90#ibcon#about to write, iclass 14, count 0 2006.203.07:57:03.90#ibcon#wrote, iclass 14, count 0 2006.203.07:57:03.90#ibcon#about to read 3, iclass 14, count 0 2006.203.07:57:03.92#ibcon#read 3, iclass 14, count 0 2006.203.07:57:03.92#ibcon#about to read 4, iclass 14, count 0 2006.203.07:57:03.92#ibcon#read 4, iclass 14, count 0 2006.203.07:57:03.92#ibcon#about to read 5, iclass 14, count 0 2006.203.07:57:03.92#ibcon#read 5, iclass 14, count 0 2006.203.07:57:03.92#ibcon#about to read 6, iclass 14, count 0 2006.203.07:57:03.92#ibcon#read 6, iclass 14, count 0 2006.203.07:57:03.92#ibcon#end of sib2, iclass 14, count 0 2006.203.07:57:03.92#ibcon#*mode == 0, iclass 14, count 0 2006.203.07:57:03.92#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.203.07:57:03.92#ibcon#[25=BW32\r\n] 2006.203.07:57:03.92#ibcon#*before write, iclass 14, count 0 2006.203.07:57:03.92#ibcon#enter sib2, iclass 14, count 0 2006.203.07:57:03.92#ibcon#flushed, iclass 14, count 0 2006.203.07:57:03.92#ibcon#about to write, iclass 14, count 0 2006.203.07:57:03.92#ibcon#wrote, iclass 14, count 0 2006.203.07:57:03.92#ibcon#about to read 3, iclass 14, count 0 2006.203.07:57:03.96#ibcon#read 3, iclass 14, count 0 2006.203.07:57:03.96#ibcon#about to read 4, iclass 14, count 0 2006.203.07:57:03.96#ibcon#read 4, iclass 14, count 0 2006.203.07:57:03.96#ibcon#about to read 5, iclass 14, count 0 2006.203.07:57:03.96#ibcon#read 5, iclass 14, count 0 2006.203.07:57:03.96#ibcon#about to read 6, iclass 14, count 0 2006.203.07:57:03.96#ibcon#read 6, iclass 14, count 0 2006.203.07:57:03.96#ibcon#end of sib2, iclass 14, count 0 2006.203.07:57:03.96#ibcon#*after write, iclass 14, count 0 2006.203.07:57:03.96#ibcon#*before return 0, iclass 14, count 0 2006.203.07:57:03.96#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.203.07:57:03.96#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.203.07:57:03.96#ibcon#about to clear, iclass 14 cls_cnt 0 2006.203.07:57:03.96#ibcon#cleared, iclass 14 cls_cnt 0 2006.203.07:57:03.96$vc4f8/vbbw=wide 2006.203.07:57:03.96#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.203.07:57:03.96#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.203.07:57:03.96#ibcon#ireg 8 cls_cnt 0 2006.203.07:57:03.96#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.203.07:57:04.02#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.203.07:57:04.02#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.203.07:57:04.02#ibcon#enter wrdev, iclass 16, count 0 2006.203.07:57:04.02#ibcon#first serial, iclass 16, count 0 2006.203.07:57:04.02#ibcon#enter sib2, iclass 16, count 0 2006.203.07:57:04.02#ibcon#flushed, iclass 16, count 0 2006.203.07:57:04.02#ibcon#about to write, iclass 16, count 0 2006.203.07:57:04.02#ibcon#wrote, iclass 16, count 0 2006.203.07:57:04.02#ibcon#about to read 3, iclass 16, count 0 2006.203.07:57:04.04#ibcon#read 3, iclass 16, count 0 2006.203.07:57:04.04#ibcon#about to read 4, iclass 16, count 0 2006.203.07:57:04.04#ibcon#read 4, iclass 16, count 0 2006.203.07:57:04.04#ibcon#about to read 5, iclass 16, count 0 2006.203.07:57:04.04#ibcon#read 5, iclass 16, count 0 2006.203.07:57:04.04#ibcon#about to read 6, iclass 16, count 0 2006.203.07:57:04.04#ibcon#read 6, iclass 16, count 0 2006.203.07:57:04.04#ibcon#end of sib2, iclass 16, count 0 2006.203.07:57:04.04#ibcon#*mode == 0, iclass 16, count 0 2006.203.07:57:04.04#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.203.07:57:04.04#ibcon#[27=BW32\r\n] 2006.203.07:57:04.04#ibcon#*before write, iclass 16, count 0 2006.203.07:57:04.04#ibcon#enter sib2, iclass 16, count 0 2006.203.07:57:04.04#ibcon#flushed, iclass 16, count 0 2006.203.07:57:04.04#ibcon#about to write, iclass 16, count 0 2006.203.07:57:04.04#ibcon#wrote, iclass 16, count 0 2006.203.07:57:04.04#ibcon#about to read 3, iclass 16, count 0 2006.203.07:57:04.07#ibcon#read 3, iclass 16, count 0 2006.203.07:57:04.07#ibcon#about to read 4, iclass 16, count 0 2006.203.07:57:04.07#ibcon#read 4, iclass 16, count 0 2006.203.07:57:04.07#ibcon#about to read 5, iclass 16, count 0 2006.203.07:57:04.07#ibcon#read 5, iclass 16, count 0 2006.203.07:57:04.07#ibcon#about to read 6, iclass 16, count 0 2006.203.07:57:04.07#ibcon#read 6, iclass 16, count 0 2006.203.07:57:04.07#ibcon#end of sib2, iclass 16, count 0 2006.203.07:57:04.07#ibcon#*after write, iclass 16, count 0 2006.203.07:57:04.07#ibcon#*before return 0, iclass 16, count 0 2006.203.07:57:04.07#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.203.07:57:04.07#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.203.07:57:04.07#ibcon#about to clear, iclass 16 cls_cnt 0 2006.203.07:57:04.07#ibcon#cleared, iclass 16 cls_cnt 0 2006.203.07:57:04.07$4f8m12a/ifd4f 2006.203.07:57:04.07$ifd4f/lo= 2006.203.07:57:04.07$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.203.07:57:04.07$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.203.07:57:04.07$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.203.07:57:04.07$ifd4f/patch= 2006.203.07:57:04.07$ifd4f/patch=lo1,a1,a2,a3,a4 2006.203.07:57:04.07$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.203.07:57:04.07$ifd4f/patch=lo3,a5,a6,a7,a8 2006.203.07:57:04.07$4f8m12a/"form=m,16.000,1:2 2006.203.07:57:04.07$4f8m12a/"tpicd 2006.203.07:57:04.07$4f8m12a/echo=off 2006.203.07:57:04.07$4f8m12a/xlog=off 2006.203.07:57:04.07:!2006.203.07:59:10 2006.203.07:57:23.14#trakl#Source acquired 2006.203.07:57:24.14#flagr#flagr/antenna,acquired 2006.203.07:59:10.00:preob 2006.203.07:59:10.14/onsource/TRACKING 2006.203.07:59:10.14:!2006.203.07:59:20 2006.203.07:59:20.00:data_valid=on 2006.203.07:59:20.00:midob 2006.203.07:59:21.14/onsource/TRACKING 2006.203.07:59:21.14/wx/23.73,1001.1,98 2006.203.07:59:21.31/cable/+6.4609E-03 2006.203.07:59:22.40/va/01,08,usb,yes,34,36 2006.203.07:59:22.40/va/02,07,usb,yes,34,36 2006.203.07:59:22.40/va/03,08,usb,yes,26,26 2006.203.07:59:22.40/va/04,07,usb,yes,35,38 2006.203.07:59:22.40/va/05,07,usb,yes,38,40 2006.203.07:59:22.40/va/06,06,usb,yes,37,37 2006.203.07:59:22.40/va/07,07,usb,yes,33,33 2006.203.07:59:22.40/va/08,06,usb,yes,40,39 2006.203.07:59:22.63/valo/01,532.99,yes,locked 2006.203.07:59:22.63/valo/02,572.99,yes,locked 2006.203.07:59:22.63/valo/03,672.99,yes,locked 2006.203.07:59:22.63/valo/04,832.99,yes,locked 2006.203.07:59:22.63/valo/05,652.99,yes,locked 2006.203.07:59:22.63/valo/06,772.99,yes,locked 2006.203.07:59:22.63/valo/07,832.99,yes,locked 2006.203.07:59:22.63/valo/08,852.99,yes,locked 2006.203.07:59:23.72/vb/01,04,usb,yes,30,30 2006.203.07:59:23.72/vb/02,04,usb,yes,31,35 2006.203.07:59:23.72/vb/03,04,usb,yes,28,31 2006.203.07:59:23.72/vb/04,04,usb,yes,29,29 2006.203.07:59:23.72/vb/05,03,usb,yes,34,39 2006.203.07:59:23.72/vb/06,04,usb,yes,28,31 2006.203.07:59:23.72/vb/07,04,usb,yes,30,30 2006.203.07:59:23.72/vb/08,04,usb,yes,28,31 2006.203.07:59:23.96/vblo/01,632.99,yes,locked 2006.203.07:59:23.96/vblo/02,640.99,yes,locked 2006.203.07:59:23.96/vblo/03,656.99,yes,locked 2006.203.07:59:23.96/vblo/04,712.99,yes,locked 2006.203.07:59:23.96/vblo/05,744.99,yes,locked 2006.203.07:59:23.96/vblo/06,752.99,yes,locked 2006.203.07:59:23.96/vblo/07,734.99,yes,locked 2006.203.07:59:23.96/vblo/08,744.99,yes,locked 2006.203.07:59:24.11/vabw/8 2006.203.07:59:24.26/vbbw/8 2006.203.07:59:24.35/xfe/off,on,13.5 2006.203.07:59:24.72/ifatt/23,28,28,28 2006.203.07:59:25.07/fmout-gps/S +4.58E-07 2006.203.07:59:25.11:!2006.203.08:00:20 2006.203.08:00:20.00:data_valid=off 2006.203.08:00:20.00:postob 2006.203.08:00:20.14/cable/+6.4596E-03 2006.203.08:00:20.14/wx/23.72,1001.1,99 2006.203.08:00:21.07/fmout-gps/S +4.58E-07 2006.203.08:00:21.07:scan_name=203-0801,k06203,60 2006.203.08:00:21.07:source=0955+476,095819.67,472507.8,2000.0,ccw 2006.203.08:00:21.14#flagr#flagr/antenna,new-source 2006.203.08:00:22.14:checkk5 2006.203.08:00:22.58/chk_autoobs//k5ts1/ autoobs is running! 2006.203.08:00:23.21/chk_autoobs//k5ts2/ autoobs is running! 2006.203.08:00:23.68/chk_autoobs//k5ts3/ autoobs is running! 2006.203.08:00:24.11/chk_autoobs//k5ts4/ autoobs is running! 2006.203.08:00:24.55/chk_obsdata//k5ts1/T2030759??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.203.08:00:24.99/chk_obsdata//k5ts2/T2030759??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.203.08:00:25.42/chk_obsdata//k5ts3/T2030759??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.203.08:00:25.85/chk_obsdata//k5ts4/T2030759??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.203.08:00:26.61/k5log//k5ts1_log_newline 2006.203.08:00:27.38/k5log//k5ts2_log_newline 2006.203.08:00:28.42/k5log//k5ts3_log_newline 2006.203.08:00:29.42/k5log//k5ts4_log_newline 2006.203.08:00:29.44/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.203.08:00:29.44:4f8m12a=2 2006.203.08:00:29.44$4f8m12a/echo=on 2006.203.08:00:29.44$4f8m12a/pcalon 2006.203.08:00:29.44$pcalon/"no phase cal control is implemented here 2006.203.08:00:29.44$4f8m12a/"tpicd=stop 2006.203.08:00:29.44$4f8m12a/vc4f8 2006.203.08:00:29.44$vc4f8/valo=1,532.99 2006.203.08:00:29.45#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.203.08:00:29.45#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.203.08:00:29.45#ibcon#ireg 17 cls_cnt 0 2006.203.08:00:29.45#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.203.08:00:29.45#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.203.08:00:29.45#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.203.08:00:29.45#ibcon#enter wrdev, iclass 22, count 0 2006.203.08:00:29.45#ibcon#first serial, iclass 22, count 0 2006.203.08:00:29.45#ibcon#enter sib2, iclass 22, count 0 2006.203.08:00:29.45#ibcon#flushed, iclass 22, count 0 2006.203.08:00:29.45#ibcon#about to write, iclass 22, count 0 2006.203.08:00:29.45#ibcon#wrote, iclass 22, count 0 2006.203.08:00:29.45#ibcon#about to read 3, iclass 22, count 0 2006.203.08:00:29.49#ibcon#read 3, iclass 22, count 0 2006.203.08:00:29.49#ibcon#about to read 4, iclass 22, count 0 2006.203.08:00:29.49#ibcon#read 4, iclass 22, count 0 2006.203.08:00:29.49#ibcon#about to read 5, iclass 22, count 0 2006.203.08:00:29.49#ibcon#read 5, iclass 22, count 0 2006.203.08:00:29.49#ibcon#about to read 6, iclass 22, count 0 2006.203.08:00:29.49#ibcon#read 6, iclass 22, count 0 2006.203.08:00:29.49#ibcon#end of sib2, iclass 22, count 0 2006.203.08:00:29.49#ibcon#*mode == 0, iclass 22, count 0 2006.203.08:00:29.49#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.203.08:00:29.49#ibcon#[26=FRQ=01,532.99\r\n] 2006.203.08:00:29.49#ibcon#*before write, iclass 22, count 0 2006.203.08:00:29.49#ibcon#enter sib2, iclass 22, count 0 2006.203.08:00:29.49#ibcon#flushed, iclass 22, count 0 2006.203.08:00:29.49#ibcon#about to write, iclass 22, count 0 2006.203.08:00:29.49#ibcon#wrote, iclass 22, count 0 2006.203.08:00:29.49#ibcon#about to read 3, iclass 22, count 0 2006.203.08:00:29.54#ibcon#read 3, iclass 22, count 0 2006.203.08:00:29.54#ibcon#about to read 4, iclass 22, count 0 2006.203.08:00:29.54#ibcon#read 4, iclass 22, count 0 2006.203.08:00:29.54#ibcon#about to read 5, iclass 22, count 0 2006.203.08:00:29.54#ibcon#read 5, iclass 22, count 0 2006.203.08:00:29.54#ibcon#about to read 6, iclass 22, count 0 2006.203.08:00:29.54#ibcon#read 6, iclass 22, count 0 2006.203.08:00:29.54#ibcon#end of sib2, iclass 22, count 0 2006.203.08:00:29.54#ibcon#*after write, iclass 22, count 0 2006.203.08:00:29.54#ibcon#*before return 0, iclass 22, count 0 2006.203.08:00:29.54#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.203.08:00:29.54#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.203.08:00:29.54#ibcon#about to clear, iclass 22 cls_cnt 0 2006.203.08:00:29.54#ibcon#cleared, iclass 22 cls_cnt 0 2006.203.08:00:29.54$vc4f8/va=1,8 2006.203.08:00:29.54#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.203.08:00:29.54#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.203.08:00:29.54#ibcon#ireg 11 cls_cnt 2 2006.203.08:00:29.54#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.203.08:00:29.54#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.203.08:00:29.54#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.203.08:00:29.54#ibcon#enter wrdev, iclass 24, count 2 2006.203.08:00:29.54#ibcon#first serial, iclass 24, count 2 2006.203.08:00:29.54#ibcon#enter sib2, iclass 24, count 2 2006.203.08:00:29.54#ibcon#flushed, iclass 24, count 2 2006.203.08:00:29.54#ibcon#about to write, iclass 24, count 2 2006.203.08:00:29.54#ibcon#wrote, iclass 24, count 2 2006.203.08:00:29.54#ibcon#about to read 3, iclass 24, count 2 2006.203.08:00:29.56#ibcon#read 3, iclass 24, count 2 2006.203.08:00:29.56#ibcon#about to read 4, iclass 24, count 2 2006.203.08:00:29.56#ibcon#read 4, iclass 24, count 2 2006.203.08:00:29.56#ibcon#about to read 5, iclass 24, count 2 2006.203.08:00:29.56#ibcon#read 5, iclass 24, count 2 2006.203.08:00:29.56#ibcon#about to read 6, iclass 24, count 2 2006.203.08:00:29.56#ibcon#read 6, iclass 24, count 2 2006.203.08:00:29.56#ibcon#end of sib2, iclass 24, count 2 2006.203.08:00:29.56#ibcon#*mode == 0, iclass 24, count 2 2006.203.08:00:29.56#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.203.08:00:29.56#ibcon#[25=AT01-08\r\n] 2006.203.08:00:29.56#ibcon#*before write, iclass 24, count 2 2006.203.08:00:29.56#ibcon#enter sib2, iclass 24, count 2 2006.203.08:00:29.56#ibcon#flushed, iclass 24, count 2 2006.203.08:00:29.56#ibcon#about to write, iclass 24, count 2 2006.203.08:00:29.56#ibcon#wrote, iclass 24, count 2 2006.203.08:00:29.56#ibcon#about to read 3, iclass 24, count 2 2006.203.08:00:29.60#ibcon#read 3, iclass 24, count 2 2006.203.08:00:29.60#ibcon#about to read 4, iclass 24, count 2 2006.203.08:00:29.60#ibcon#read 4, iclass 24, count 2 2006.203.08:00:29.60#ibcon#about to read 5, iclass 24, count 2 2006.203.08:00:29.60#ibcon#read 5, iclass 24, count 2 2006.203.08:00:29.60#ibcon#about to read 6, iclass 24, count 2 2006.203.08:00:29.60#ibcon#read 6, iclass 24, count 2 2006.203.08:00:29.60#ibcon#end of sib2, iclass 24, count 2 2006.203.08:00:29.60#ibcon#*after write, iclass 24, count 2 2006.203.08:00:29.60#ibcon#*before return 0, iclass 24, count 2 2006.203.08:00:29.60#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.203.08:00:29.60#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.203.08:00:29.60#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.203.08:00:29.60#ibcon#ireg 7 cls_cnt 0 2006.203.08:00:29.60#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.203.08:00:29.72#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.203.08:00:29.72#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.203.08:00:29.72#ibcon#enter wrdev, iclass 24, count 0 2006.203.08:00:29.72#ibcon#first serial, iclass 24, count 0 2006.203.08:00:29.72#ibcon#enter sib2, iclass 24, count 0 2006.203.08:00:29.72#ibcon#flushed, iclass 24, count 0 2006.203.08:00:29.72#ibcon#about to write, iclass 24, count 0 2006.203.08:00:29.72#ibcon#wrote, iclass 24, count 0 2006.203.08:00:29.72#ibcon#about to read 3, iclass 24, count 0 2006.203.08:00:29.74#ibcon#read 3, iclass 24, count 0 2006.203.08:00:29.74#ibcon#about to read 4, iclass 24, count 0 2006.203.08:00:29.74#ibcon#read 4, iclass 24, count 0 2006.203.08:00:29.74#ibcon#about to read 5, iclass 24, count 0 2006.203.08:00:29.74#ibcon#read 5, iclass 24, count 0 2006.203.08:00:29.74#ibcon#about to read 6, iclass 24, count 0 2006.203.08:00:29.74#ibcon#read 6, iclass 24, count 0 2006.203.08:00:29.74#ibcon#end of sib2, iclass 24, count 0 2006.203.08:00:29.74#ibcon#*mode == 0, iclass 24, count 0 2006.203.08:00:29.74#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.203.08:00:29.74#ibcon#[25=USB\r\n] 2006.203.08:00:29.74#ibcon#*before write, iclass 24, count 0 2006.203.08:00:29.74#ibcon#enter sib2, iclass 24, count 0 2006.203.08:00:29.74#ibcon#flushed, iclass 24, count 0 2006.203.08:00:29.74#ibcon#about to write, iclass 24, count 0 2006.203.08:00:29.74#ibcon#wrote, iclass 24, count 0 2006.203.08:00:29.74#ibcon#about to read 3, iclass 24, count 0 2006.203.08:00:29.77#ibcon#read 3, iclass 24, count 0 2006.203.08:00:29.77#ibcon#about to read 4, iclass 24, count 0 2006.203.08:00:29.77#ibcon#read 4, iclass 24, count 0 2006.203.08:00:29.77#ibcon#about to read 5, iclass 24, count 0 2006.203.08:00:29.77#ibcon#read 5, iclass 24, count 0 2006.203.08:00:29.77#ibcon#about to read 6, iclass 24, count 0 2006.203.08:00:29.77#ibcon#read 6, iclass 24, count 0 2006.203.08:00:29.77#ibcon#end of sib2, iclass 24, count 0 2006.203.08:00:29.77#ibcon#*after write, iclass 24, count 0 2006.203.08:00:29.77#ibcon#*before return 0, iclass 24, count 0 2006.203.08:00:29.77#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.203.08:00:29.77#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.203.08:00:29.77#ibcon#about to clear, iclass 24 cls_cnt 0 2006.203.08:00:29.77#ibcon#cleared, iclass 24 cls_cnt 0 2006.203.08:00:29.77$vc4f8/valo=2,572.99 2006.203.08:00:29.77#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.203.08:00:29.77#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.203.08:00:29.77#ibcon#ireg 17 cls_cnt 0 2006.203.08:00:29.77#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.203.08:00:29.77#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.203.08:00:29.77#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.203.08:00:29.77#ibcon#enter wrdev, iclass 26, count 0 2006.203.08:00:29.77#ibcon#first serial, iclass 26, count 0 2006.203.08:00:29.77#ibcon#enter sib2, iclass 26, count 0 2006.203.08:00:29.77#ibcon#flushed, iclass 26, count 0 2006.203.08:00:29.77#ibcon#about to write, iclass 26, count 0 2006.203.08:00:29.77#ibcon#wrote, iclass 26, count 0 2006.203.08:00:29.77#ibcon#about to read 3, iclass 26, count 0 2006.203.08:00:29.79#ibcon#read 3, iclass 26, count 0 2006.203.08:00:29.79#ibcon#about to read 4, iclass 26, count 0 2006.203.08:00:29.79#ibcon#read 4, iclass 26, count 0 2006.203.08:00:29.79#ibcon#about to read 5, iclass 26, count 0 2006.203.08:00:29.79#ibcon#read 5, iclass 26, count 0 2006.203.08:00:29.79#ibcon#about to read 6, iclass 26, count 0 2006.203.08:00:29.79#ibcon#read 6, iclass 26, count 0 2006.203.08:00:29.79#ibcon#end of sib2, iclass 26, count 0 2006.203.08:00:29.79#ibcon#*mode == 0, iclass 26, count 0 2006.203.08:00:29.79#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.203.08:00:29.79#ibcon#[26=FRQ=02,572.99\r\n] 2006.203.08:00:29.79#ibcon#*before write, iclass 26, count 0 2006.203.08:00:29.79#ibcon#enter sib2, iclass 26, count 0 2006.203.08:00:29.79#ibcon#flushed, iclass 26, count 0 2006.203.08:00:29.79#ibcon#about to write, iclass 26, count 0 2006.203.08:00:29.79#ibcon#wrote, iclass 26, count 0 2006.203.08:00:29.79#ibcon#about to read 3, iclass 26, count 0 2006.203.08:00:29.84#ibcon#read 3, iclass 26, count 0 2006.203.08:00:29.84#ibcon#about to read 4, iclass 26, count 0 2006.203.08:00:29.84#ibcon#read 4, iclass 26, count 0 2006.203.08:00:29.84#ibcon#about to read 5, iclass 26, count 0 2006.203.08:00:29.84#ibcon#read 5, iclass 26, count 0 2006.203.08:00:29.84#ibcon#about to read 6, iclass 26, count 0 2006.203.08:00:29.84#ibcon#read 6, iclass 26, count 0 2006.203.08:00:29.84#ibcon#end of sib2, iclass 26, count 0 2006.203.08:00:29.84#ibcon#*after write, iclass 26, count 0 2006.203.08:00:29.84#ibcon#*before return 0, iclass 26, count 0 2006.203.08:00:29.84#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.203.08:00:29.84#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.203.08:00:29.84#ibcon#about to clear, iclass 26 cls_cnt 0 2006.203.08:00:29.84#ibcon#cleared, iclass 26 cls_cnt 0 2006.203.08:00:29.84$vc4f8/va=2,7 2006.203.08:00:29.84#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.203.08:00:29.84#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.203.08:00:29.84#ibcon#ireg 11 cls_cnt 2 2006.203.08:00:29.84#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.203.08:00:29.89#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.203.08:00:29.89#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.203.08:00:29.89#ibcon#enter wrdev, iclass 28, count 2 2006.203.08:00:29.89#ibcon#first serial, iclass 28, count 2 2006.203.08:00:29.89#ibcon#enter sib2, iclass 28, count 2 2006.203.08:00:29.89#ibcon#flushed, iclass 28, count 2 2006.203.08:00:29.89#ibcon#about to write, iclass 28, count 2 2006.203.08:00:29.89#ibcon#wrote, iclass 28, count 2 2006.203.08:00:29.89#ibcon#about to read 3, iclass 28, count 2 2006.203.08:00:29.91#ibcon#read 3, iclass 28, count 2 2006.203.08:00:29.91#ibcon#about to read 4, iclass 28, count 2 2006.203.08:00:29.91#ibcon#read 4, iclass 28, count 2 2006.203.08:00:29.91#ibcon#about to read 5, iclass 28, count 2 2006.203.08:00:29.91#ibcon#read 5, iclass 28, count 2 2006.203.08:00:29.91#ibcon#about to read 6, iclass 28, count 2 2006.203.08:00:29.91#ibcon#read 6, iclass 28, count 2 2006.203.08:00:29.91#ibcon#end of sib2, iclass 28, count 2 2006.203.08:00:29.91#ibcon#*mode == 0, iclass 28, count 2 2006.203.08:00:29.91#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.203.08:00:29.91#ibcon#[25=AT02-07\r\n] 2006.203.08:00:29.91#ibcon#*before write, iclass 28, count 2 2006.203.08:00:29.91#ibcon#enter sib2, iclass 28, count 2 2006.203.08:00:29.91#ibcon#flushed, iclass 28, count 2 2006.203.08:00:29.91#ibcon#about to write, iclass 28, count 2 2006.203.08:00:29.91#ibcon#wrote, iclass 28, count 2 2006.203.08:00:29.91#ibcon#about to read 3, iclass 28, count 2 2006.203.08:00:29.94#ibcon#read 3, iclass 28, count 2 2006.203.08:00:29.94#ibcon#about to read 4, iclass 28, count 2 2006.203.08:00:29.94#ibcon#read 4, iclass 28, count 2 2006.203.08:00:29.94#ibcon#about to read 5, iclass 28, count 2 2006.203.08:00:29.94#ibcon#read 5, iclass 28, count 2 2006.203.08:00:29.94#ibcon#about to read 6, iclass 28, count 2 2006.203.08:00:29.94#ibcon#read 6, iclass 28, count 2 2006.203.08:00:29.94#ibcon#end of sib2, iclass 28, count 2 2006.203.08:00:29.94#ibcon#*after write, iclass 28, count 2 2006.203.08:00:29.94#ibcon#*before return 0, iclass 28, count 2 2006.203.08:00:29.94#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.203.08:00:29.94#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.203.08:00:29.94#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.203.08:00:29.94#ibcon#ireg 7 cls_cnt 0 2006.203.08:00:29.94#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.203.08:00:30.06#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.203.08:00:30.06#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.203.08:00:30.06#ibcon#enter wrdev, iclass 28, count 0 2006.203.08:00:30.06#ibcon#first serial, iclass 28, count 0 2006.203.08:00:30.06#ibcon#enter sib2, iclass 28, count 0 2006.203.08:00:30.06#ibcon#flushed, iclass 28, count 0 2006.203.08:00:30.06#ibcon#about to write, iclass 28, count 0 2006.203.08:00:30.06#ibcon#wrote, iclass 28, count 0 2006.203.08:00:30.06#ibcon#about to read 3, iclass 28, count 0 2006.203.08:00:30.10#ibcon#read 3, iclass 28, count 0 2006.203.08:00:30.10#ibcon#about to read 4, iclass 28, count 0 2006.203.08:00:30.10#ibcon#read 4, iclass 28, count 0 2006.203.08:00:30.10#ibcon#about to read 5, iclass 28, count 0 2006.203.08:00:30.10#ibcon#read 5, iclass 28, count 0 2006.203.08:00:30.10#ibcon#about to read 6, iclass 28, count 0 2006.203.08:00:30.10#ibcon#read 6, iclass 28, count 0 2006.203.08:00:30.10#ibcon#end of sib2, iclass 28, count 0 2006.203.08:00:30.10#ibcon#*mode == 0, iclass 28, count 0 2006.203.08:00:30.10#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.203.08:00:30.10#ibcon#[25=USB\r\n] 2006.203.08:00:30.10#ibcon#*before write, iclass 28, count 0 2006.203.08:00:30.10#ibcon#enter sib2, iclass 28, count 0 2006.203.08:00:30.10#ibcon#flushed, iclass 28, count 0 2006.203.08:00:30.10#ibcon#about to write, iclass 28, count 0 2006.203.08:00:30.10#ibcon#wrote, iclass 28, count 0 2006.203.08:00:30.10#ibcon#about to read 3, iclass 28, count 0 2006.203.08:00:30.13#ibcon#read 3, iclass 28, count 0 2006.203.08:00:30.13#ibcon#about to read 4, iclass 28, count 0 2006.203.08:00:30.13#ibcon#read 4, iclass 28, count 0 2006.203.08:00:30.13#ibcon#about to read 5, iclass 28, count 0 2006.203.08:00:30.13#ibcon#read 5, iclass 28, count 0 2006.203.08:00:30.13#ibcon#about to read 6, iclass 28, count 0 2006.203.08:00:30.13#ibcon#read 6, iclass 28, count 0 2006.203.08:00:30.13#ibcon#end of sib2, iclass 28, count 0 2006.203.08:00:30.13#ibcon#*after write, iclass 28, count 0 2006.203.08:00:30.13#ibcon#*before return 0, iclass 28, count 0 2006.203.08:00:30.13#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.203.08:00:30.13#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.203.08:00:30.13#ibcon#about to clear, iclass 28 cls_cnt 0 2006.203.08:00:30.13#ibcon#cleared, iclass 28 cls_cnt 0 2006.203.08:00:30.13$vc4f8/valo=3,672.99 2006.203.08:00:30.13#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.203.08:00:30.13#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.203.08:00:30.13#ibcon#ireg 17 cls_cnt 0 2006.203.08:00:30.13#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.203.08:00:30.13#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.203.08:00:30.13#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.203.08:00:30.13#ibcon#enter wrdev, iclass 30, count 0 2006.203.08:00:30.13#ibcon#first serial, iclass 30, count 0 2006.203.08:00:30.13#ibcon#enter sib2, iclass 30, count 0 2006.203.08:00:30.13#ibcon#flushed, iclass 30, count 0 2006.203.08:00:30.13#ibcon#about to write, iclass 30, count 0 2006.203.08:00:30.13#ibcon#wrote, iclass 30, count 0 2006.203.08:00:30.13#ibcon#about to read 3, iclass 30, count 0 2006.203.08:00:30.15#ibcon#read 3, iclass 30, count 0 2006.203.08:00:30.15#ibcon#about to read 4, iclass 30, count 0 2006.203.08:00:30.15#ibcon#read 4, iclass 30, count 0 2006.203.08:00:30.15#ibcon#about to read 5, iclass 30, count 0 2006.203.08:00:30.15#ibcon#read 5, iclass 30, count 0 2006.203.08:00:30.15#ibcon#about to read 6, iclass 30, count 0 2006.203.08:00:30.15#ibcon#read 6, iclass 30, count 0 2006.203.08:00:30.15#ibcon#end of sib2, iclass 30, count 0 2006.203.08:00:30.15#ibcon#*mode == 0, iclass 30, count 0 2006.203.08:00:30.15#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.203.08:00:30.15#ibcon#[26=FRQ=03,672.99\r\n] 2006.203.08:00:30.15#ibcon#*before write, iclass 30, count 0 2006.203.08:00:30.15#ibcon#enter sib2, iclass 30, count 0 2006.203.08:00:30.15#ibcon#flushed, iclass 30, count 0 2006.203.08:00:30.15#ibcon#about to write, iclass 30, count 0 2006.203.08:00:30.15#ibcon#wrote, iclass 30, count 0 2006.203.08:00:30.15#ibcon#about to read 3, iclass 30, count 0 2006.203.08:00:30.19#ibcon#read 3, iclass 30, count 0 2006.203.08:00:30.19#ibcon#about to read 4, iclass 30, count 0 2006.203.08:00:30.19#ibcon#read 4, iclass 30, count 0 2006.203.08:00:30.19#ibcon#about to read 5, iclass 30, count 0 2006.203.08:00:30.19#ibcon#read 5, iclass 30, count 0 2006.203.08:00:30.19#ibcon#about to read 6, iclass 30, count 0 2006.203.08:00:30.19#ibcon#read 6, iclass 30, count 0 2006.203.08:00:30.19#ibcon#end of sib2, iclass 30, count 0 2006.203.08:00:30.19#ibcon#*after write, iclass 30, count 0 2006.203.08:00:30.19#ibcon#*before return 0, iclass 30, count 0 2006.203.08:00:30.19#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.203.08:00:30.19#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.203.08:00:30.19#ibcon#about to clear, iclass 30 cls_cnt 0 2006.203.08:00:30.19#ibcon#cleared, iclass 30 cls_cnt 0 2006.203.08:00:30.19$vc4f8/va=3,8 2006.203.08:00:30.19#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.203.08:00:30.19#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.203.08:00:30.19#ibcon#ireg 11 cls_cnt 2 2006.203.08:00:30.19#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.203.08:00:30.25#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.203.08:00:30.25#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.203.08:00:30.25#ibcon#enter wrdev, iclass 32, count 2 2006.203.08:00:30.25#ibcon#first serial, iclass 32, count 2 2006.203.08:00:30.25#ibcon#enter sib2, iclass 32, count 2 2006.203.08:00:30.25#ibcon#flushed, iclass 32, count 2 2006.203.08:00:30.25#ibcon#about to write, iclass 32, count 2 2006.203.08:00:30.25#ibcon#wrote, iclass 32, count 2 2006.203.08:00:30.25#ibcon#about to read 3, iclass 32, count 2 2006.203.08:00:30.27#ibcon#read 3, iclass 32, count 2 2006.203.08:00:30.27#ibcon#about to read 4, iclass 32, count 2 2006.203.08:00:30.27#ibcon#read 4, iclass 32, count 2 2006.203.08:00:30.27#ibcon#about to read 5, iclass 32, count 2 2006.203.08:00:30.27#ibcon#read 5, iclass 32, count 2 2006.203.08:00:30.27#ibcon#about to read 6, iclass 32, count 2 2006.203.08:00:30.27#ibcon#read 6, iclass 32, count 2 2006.203.08:00:30.27#ibcon#end of sib2, iclass 32, count 2 2006.203.08:00:30.27#ibcon#*mode == 0, iclass 32, count 2 2006.203.08:00:30.27#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.203.08:00:30.27#ibcon#[25=AT03-08\r\n] 2006.203.08:00:30.27#ibcon#*before write, iclass 32, count 2 2006.203.08:00:30.27#ibcon#enter sib2, iclass 32, count 2 2006.203.08:00:30.27#ibcon#flushed, iclass 32, count 2 2006.203.08:00:30.27#ibcon#about to write, iclass 32, count 2 2006.203.08:00:30.27#ibcon#wrote, iclass 32, count 2 2006.203.08:00:30.27#ibcon#about to read 3, iclass 32, count 2 2006.203.08:00:30.31#ibcon#read 3, iclass 32, count 2 2006.203.08:00:30.31#ibcon#about to read 4, iclass 32, count 2 2006.203.08:00:30.31#ibcon#read 4, iclass 32, count 2 2006.203.08:00:30.31#ibcon#about to read 5, iclass 32, count 2 2006.203.08:00:30.31#ibcon#read 5, iclass 32, count 2 2006.203.08:00:30.31#ibcon#about to read 6, iclass 32, count 2 2006.203.08:00:30.31#ibcon#read 6, iclass 32, count 2 2006.203.08:00:30.31#ibcon#end of sib2, iclass 32, count 2 2006.203.08:00:30.31#ibcon#*after write, iclass 32, count 2 2006.203.08:00:30.31#ibcon#*before return 0, iclass 32, count 2 2006.203.08:00:30.31#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.203.08:00:30.31#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.203.08:00:30.31#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.203.08:00:30.31#ibcon#ireg 7 cls_cnt 0 2006.203.08:00:30.31#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.203.08:00:30.43#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.203.08:00:30.43#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.203.08:00:30.43#ibcon#enter wrdev, iclass 32, count 0 2006.203.08:00:30.43#ibcon#first serial, iclass 32, count 0 2006.203.08:00:30.43#ibcon#enter sib2, iclass 32, count 0 2006.203.08:00:30.43#ibcon#flushed, iclass 32, count 0 2006.203.08:00:30.43#ibcon#about to write, iclass 32, count 0 2006.203.08:00:30.43#ibcon#wrote, iclass 32, count 0 2006.203.08:00:30.43#ibcon#about to read 3, iclass 32, count 0 2006.203.08:00:30.45#ibcon#read 3, iclass 32, count 0 2006.203.08:00:30.45#ibcon#about to read 4, iclass 32, count 0 2006.203.08:00:30.45#ibcon#read 4, iclass 32, count 0 2006.203.08:00:30.45#ibcon#about to read 5, iclass 32, count 0 2006.203.08:00:30.45#ibcon#read 5, iclass 32, count 0 2006.203.08:00:30.45#ibcon#about to read 6, iclass 32, count 0 2006.203.08:00:30.45#ibcon#read 6, iclass 32, count 0 2006.203.08:00:30.45#ibcon#end of sib2, iclass 32, count 0 2006.203.08:00:30.45#ibcon#*mode == 0, iclass 32, count 0 2006.203.08:00:30.45#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.203.08:00:30.45#ibcon#[25=USB\r\n] 2006.203.08:00:30.45#ibcon#*before write, iclass 32, count 0 2006.203.08:00:30.45#ibcon#enter sib2, iclass 32, count 0 2006.203.08:00:30.45#ibcon#flushed, iclass 32, count 0 2006.203.08:00:30.45#ibcon#about to write, iclass 32, count 0 2006.203.08:00:30.45#ibcon#wrote, iclass 32, count 0 2006.203.08:00:30.45#ibcon#about to read 3, iclass 32, count 0 2006.203.08:00:30.48#ibcon#read 3, iclass 32, count 0 2006.203.08:00:30.48#ibcon#about to read 4, iclass 32, count 0 2006.203.08:00:30.48#ibcon#read 4, iclass 32, count 0 2006.203.08:00:30.48#ibcon#about to read 5, iclass 32, count 0 2006.203.08:00:30.48#ibcon#read 5, iclass 32, count 0 2006.203.08:00:30.48#ibcon#about to read 6, iclass 32, count 0 2006.203.08:00:30.48#ibcon#read 6, iclass 32, count 0 2006.203.08:00:30.48#ibcon#end of sib2, iclass 32, count 0 2006.203.08:00:30.48#ibcon#*after write, iclass 32, count 0 2006.203.08:00:30.48#ibcon#*before return 0, iclass 32, count 0 2006.203.08:00:30.48#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.203.08:00:30.48#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.203.08:00:30.48#ibcon#about to clear, iclass 32 cls_cnt 0 2006.203.08:00:30.48#ibcon#cleared, iclass 32 cls_cnt 0 2006.203.08:00:30.48$vc4f8/valo=4,832.99 2006.203.08:00:30.48#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.203.08:00:30.48#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.203.08:00:30.48#ibcon#ireg 17 cls_cnt 0 2006.203.08:00:30.48#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.203.08:00:30.48#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.203.08:00:30.48#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.203.08:00:30.48#ibcon#enter wrdev, iclass 34, count 0 2006.203.08:00:30.48#ibcon#first serial, iclass 34, count 0 2006.203.08:00:30.48#ibcon#enter sib2, iclass 34, count 0 2006.203.08:00:30.48#ibcon#flushed, iclass 34, count 0 2006.203.08:00:30.48#ibcon#about to write, iclass 34, count 0 2006.203.08:00:30.48#ibcon#wrote, iclass 34, count 0 2006.203.08:00:30.48#ibcon#about to read 3, iclass 34, count 0 2006.203.08:00:30.50#ibcon#read 3, iclass 34, count 0 2006.203.08:00:30.50#ibcon#about to read 4, iclass 34, count 0 2006.203.08:00:30.50#ibcon#read 4, iclass 34, count 0 2006.203.08:00:30.50#ibcon#about to read 5, iclass 34, count 0 2006.203.08:00:30.50#ibcon#read 5, iclass 34, count 0 2006.203.08:00:30.50#ibcon#about to read 6, iclass 34, count 0 2006.203.08:00:30.50#ibcon#read 6, iclass 34, count 0 2006.203.08:00:30.50#ibcon#end of sib2, iclass 34, count 0 2006.203.08:00:30.50#ibcon#*mode == 0, iclass 34, count 0 2006.203.08:00:30.50#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.203.08:00:30.50#ibcon#[26=FRQ=04,832.99\r\n] 2006.203.08:00:30.50#ibcon#*before write, iclass 34, count 0 2006.203.08:00:30.50#ibcon#enter sib2, iclass 34, count 0 2006.203.08:00:30.50#ibcon#flushed, iclass 34, count 0 2006.203.08:00:30.50#ibcon#about to write, iclass 34, count 0 2006.203.08:00:30.50#ibcon#wrote, iclass 34, count 0 2006.203.08:00:30.50#ibcon#about to read 3, iclass 34, count 0 2006.203.08:00:30.54#ibcon#read 3, iclass 34, count 0 2006.203.08:00:30.54#ibcon#about to read 4, iclass 34, count 0 2006.203.08:00:30.54#ibcon#read 4, iclass 34, count 0 2006.203.08:00:30.54#ibcon#about to read 5, iclass 34, count 0 2006.203.08:00:30.54#ibcon#read 5, iclass 34, count 0 2006.203.08:00:30.54#ibcon#about to read 6, iclass 34, count 0 2006.203.08:00:30.54#ibcon#read 6, iclass 34, count 0 2006.203.08:00:30.54#ibcon#end of sib2, iclass 34, count 0 2006.203.08:00:30.54#ibcon#*after write, iclass 34, count 0 2006.203.08:00:30.54#ibcon#*before return 0, iclass 34, count 0 2006.203.08:00:30.54#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.203.08:00:30.54#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.203.08:00:30.54#ibcon#about to clear, iclass 34 cls_cnt 0 2006.203.08:00:30.54#ibcon#cleared, iclass 34 cls_cnt 0 2006.203.08:00:30.54$vc4f8/va=4,7 2006.203.08:00:30.54#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.203.08:00:30.54#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.203.08:00:30.54#ibcon#ireg 11 cls_cnt 2 2006.203.08:00:30.54#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.203.08:00:30.60#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.203.08:00:30.60#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.203.08:00:30.60#ibcon#enter wrdev, iclass 36, count 2 2006.203.08:00:30.60#ibcon#first serial, iclass 36, count 2 2006.203.08:00:30.60#ibcon#enter sib2, iclass 36, count 2 2006.203.08:00:30.60#ibcon#flushed, iclass 36, count 2 2006.203.08:00:30.60#ibcon#about to write, iclass 36, count 2 2006.203.08:00:30.60#ibcon#wrote, iclass 36, count 2 2006.203.08:00:30.60#ibcon#about to read 3, iclass 36, count 2 2006.203.08:00:30.62#ibcon#read 3, iclass 36, count 2 2006.203.08:00:30.62#ibcon#about to read 4, iclass 36, count 2 2006.203.08:00:30.62#ibcon#read 4, iclass 36, count 2 2006.203.08:00:30.62#ibcon#about to read 5, iclass 36, count 2 2006.203.08:00:30.62#ibcon#read 5, iclass 36, count 2 2006.203.08:00:30.62#ibcon#about to read 6, iclass 36, count 2 2006.203.08:00:30.62#ibcon#read 6, iclass 36, count 2 2006.203.08:00:30.62#ibcon#end of sib2, iclass 36, count 2 2006.203.08:00:30.62#ibcon#*mode == 0, iclass 36, count 2 2006.203.08:00:30.62#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.203.08:00:30.62#ibcon#[25=AT04-07\r\n] 2006.203.08:00:30.62#ibcon#*before write, iclass 36, count 2 2006.203.08:00:30.62#ibcon#enter sib2, iclass 36, count 2 2006.203.08:00:30.62#ibcon#flushed, iclass 36, count 2 2006.203.08:00:30.62#ibcon#about to write, iclass 36, count 2 2006.203.08:00:30.62#ibcon#wrote, iclass 36, count 2 2006.203.08:00:30.62#ibcon#about to read 3, iclass 36, count 2 2006.203.08:00:30.65#ibcon#read 3, iclass 36, count 2 2006.203.08:00:30.65#ibcon#about to read 4, iclass 36, count 2 2006.203.08:00:30.65#ibcon#read 4, iclass 36, count 2 2006.203.08:00:30.65#ibcon#about to read 5, iclass 36, count 2 2006.203.08:00:30.65#ibcon#read 5, iclass 36, count 2 2006.203.08:00:30.65#ibcon#about to read 6, iclass 36, count 2 2006.203.08:00:30.65#ibcon#read 6, iclass 36, count 2 2006.203.08:00:30.65#ibcon#end of sib2, iclass 36, count 2 2006.203.08:00:30.65#ibcon#*after write, iclass 36, count 2 2006.203.08:00:30.65#ibcon#*before return 0, iclass 36, count 2 2006.203.08:00:30.65#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.203.08:00:30.65#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.203.08:00:30.65#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.203.08:00:30.65#ibcon#ireg 7 cls_cnt 0 2006.203.08:00:30.65#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.203.08:00:30.77#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.203.08:00:30.77#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.203.08:00:30.77#ibcon#enter wrdev, iclass 36, count 0 2006.203.08:00:30.77#ibcon#first serial, iclass 36, count 0 2006.203.08:00:30.77#ibcon#enter sib2, iclass 36, count 0 2006.203.08:00:30.77#ibcon#flushed, iclass 36, count 0 2006.203.08:00:30.77#ibcon#about to write, iclass 36, count 0 2006.203.08:00:30.77#ibcon#wrote, iclass 36, count 0 2006.203.08:00:30.77#ibcon#about to read 3, iclass 36, count 0 2006.203.08:00:30.79#ibcon#read 3, iclass 36, count 0 2006.203.08:00:30.79#ibcon#about to read 4, iclass 36, count 0 2006.203.08:00:30.79#ibcon#read 4, iclass 36, count 0 2006.203.08:00:30.79#ibcon#about to read 5, iclass 36, count 0 2006.203.08:00:30.79#ibcon#read 5, iclass 36, count 0 2006.203.08:00:30.79#ibcon#about to read 6, iclass 36, count 0 2006.203.08:00:30.79#ibcon#read 6, iclass 36, count 0 2006.203.08:00:30.79#ibcon#end of sib2, iclass 36, count 0 2006.203.08:00:30.79#ibcon#*mode == 0, iclass 36, count 0 2006.203.08:00:30.79#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.203.08:00:30.79#ibcon#[25=USB\r\n] 2006.203.08:00:30.79#ibcon#*before write, iclass 36, count 0 2006.203.08:00:30.79#ibcon#enter sib2, iclass 36, count 0 2006.203.08:00:30.79#ibcon#flushed, iclass 36, count 0 2006.203.08:00:30.79#ibcon#about to write, iclass 36, count 0 2006.203.08:00:30.79#ibcon#wrote, iclass 36, count 0 2006.203.08:00:30.79#ibcon#about to read 3, iclass 36, count 0 2006.203.08:00:30.82#ibcon#read 3, iclass 36, count 0 2006.203.08:00:30.82#ibcon#about to read 4, iclass 36, count 0 2006.203.08:00:30.82#ibcon#read 4, iclass 36, count 0 2006.203.08:00:30.82#ibcon#about to read 5, iclass 36, count 0 2006.203.08:00:30.82#ibcon#read 5, iclass 36, count 0 2006.203.08:00:30.82#ibcon#about to read 6, iclass 36, count 0 2006.203.08:00:30.82#ibcon#read 6, iclass 36, count 0 2006.203.08:00:30.82#ibcon#end of sib2, iclass 36, count 0 2006.203.08:00:30.82#ibcon#*after write, iclass 36, count 0 2006.203.08:00:30.82#ibcon#*before return 0, iclass 36, count 0 2006.203.08:00:30.82#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.203.08:00:30.82#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.203.08:00:30.82#ibcon#about to clear, iclass 36 cls_cnt 0 2006.203.08:00:30.82#ibcon#cleared, iclass 36 cls_cnt 0 2006.203.08:00:30.82$vc4f8/valo=5,652.99 2006.203.08:00:30.82#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.203.08:00:30.82#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.203.08:00:30.82#ibcon#ireg 17 cls_cnt 0 2006.203.08:00:30.82#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.203.08:00:30.82#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.203.08:00:30.82#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.203.08:00:30.82#ibcon#enter wrdev, iclass 38, count 0 2006.203.08:00:30.82#ibcon#first serial, iclass 38, count 0 2006.203.08:00:30.82#ibcon#enter sib2, iclass 38, count 0 2006.203.08:00:30.82#ibcon#flushed, iclass 38, count 0 2006.203.08:00:30.82#ibcon#about to write, iclass 38, count 0 2006.203.08:00:30.82#ibcon#wrote, iclass 38, count 0 2006.203.08:00:30.82#ibcon#about to read 3, iclass 38, count 0 2006.203.08:00:30.84#ibcon#read 3, iclass 38, count 0 2006.203.08:00:30.84#ibcon#about to read 4, iclass 38, count 0 2006.203.08:00:30.84#ibcon#read 4, iclass 38, count 0 2006.203.08:00:30.84#ibcon#about to read 5, iclass 38, count 0 2006.203.08:00:30.84#ibcon#read 5, iclass 38, count 0 2006.203.08:00:30.84#ibcon#about to read 6, iclass 38, count 0 2006.203.08:00:30.84#ibcon#read 6, iclass 38, count 0 2006.203.08:00:30.84#ibcon#end of sib2, iclass 38, count 0 2006.203.08:00:30.84#ibcon#*mode == 0, iclass 38, count 0 2006.203.08:00:30.84#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.203.08:00:30.84#ibcon#[26=FRQ=05,652.99\r\n] 2006.203.08:00:30.84#ibcon#*before write, iclass 38, count 0 2006.203.08:00:30.84#ibcon#enter sib2, iclass 38, count 0 2006.203.08:00:30.84#ibcon#flushed, iclass 38, count 0 2006.203.08:00:30.84#ibcon#about to write, iclass 38, count 0 2006.203.08:00:30.84#ibcon#wrote, iclass 38, count 0 2006.203.08:00:30.84#ibcon#about to read 3, iclass 38, count 0 2006.203.08:00:30.88#ibcon#read 3, iclass 38, count 0 2006.203.08:00:30.88#ibcon#about to read 4, iclass 38, count 0 2006.203.08:00:30.88#ibcon#read 4, iclass 38, count 0 2006.203.08:00:30.88#ibcon#about to read 5, iclass 38, count 0 2006.203.08:00:30.88#ibcon#read 5, iclass 38, count 0 2006.203.08:00:30.88#ibcon#about to read 6, iclass 38, count 0 2006.203.08:00:30.88#ibcon#read 6, iclass 38, count 0 2006.203.08:00:30.88#ibcon#end of sib2, iclass 38, count 0 2006.203.08:00:30.88#ibcon#*after write, iclass 38, count 0 2006.203.08:00:30.88#ibcon#*before return 0, iclass 38, count 0 2006.203.08:00:30.88#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.203.08:00:30.88#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.203.08:00:30.88#ibcon#about to clear, iclass 38 cls_cnt 0 2006.203.08:00:30.88#ibcon#cleared, iclass 38 cls_cnt 0 2006.203.08:00:30.88$vc4f8/va=5,7 2006.203.08:00:30.88#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.203.08:00:30.88#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.203.08:00:30.88#ibcon#ireg 11 cls_cnt 2 2006.203.08:00:30.88#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.203.08:00:30.94#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.203.08:00:30.94#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.203.08:00:30.94#ibcon#enter wrdev, iclass 40, count 2 2006.203.08:00:30.94#ibcon#first serial, iclass 40, count 2 2006.203.08:00:30.94#ibcon#enter sib2, iclass 40, count 2 2006.203.08:00:30.94#ibcon#flushed, iclass 40, count 2 2006.203.08:00:30.94#ibcon#about to write, iclass 40, count 2 2006.203.08:00:30.94#ibcon#wrote, iclass 40, count 2 2006.203.08:00:30.94#ibcon#about to read 3, iclass 40, count 2 2006.203.08:00:30.96#ibcon#read 3, iclass 40, count 2 2006.203.08:00:30.96#ibcon#about to read 4, iclass 40, count 2 2006.203.08:00:30.96#ibcon#read 4, iclass 40, count 2 2006.203.08:00:30.96#ibcon#about to read 5, iclass 40, count 2 2006.203.08:00:30.96#ibcon#read 5, iclass 40, count 2 2006.203.08:00:30.96#ibcon#about to read 6, iclass 40, count 2 2006.203.08:00:30.96#ibcon#read 6, iclass 40, count 2 2006.203.08:00:30.96#ibcon#end of sib2, iclass 40, count 2 2006.203.08:00:30.96#ibcon#*mode == 0, iclass 40, count 2 2006.203.08:00:30.96#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.203.08:00:30.96#ibcon#[25=AT05-07\r\n] 2006.203.08:00:30.96#ibcon#*before write, iclass 40, count 2 2006.203.08:00:30.96#ibcon#enter sib2, iclass 40, count 2 2006.203.08:00:30.96#ibcon#flushed, iclass 40, count 2 2006.203.08:00:30.96#ibcon#about to write, iclass 40, count 2 2006.203.08:00:30.96#ibcon#wrote, iclass 40, count 2 2006.203.08:00:30.96#ibcon#about to read 3, iclass 40, count 2 2006.203.08:00:30.99#ibcon#read 3, iclass 40, count 2 2006.203.08:00:30.99#ibcon#about to read 4, iclass 40, count 2 2006.203.08:00:30.99#ibcon#read 4, iclass 40, count 2 2006.203.08:00:30.99#ibcon#about to read 5, iclass 40, count 2 2006.203.08:00:30.99#ibcon#read 5, iclass 40, count 2 2006.203.08:00:30.99#ibcon#about to read 6, iclass 40, count 2 2006.203.08:00:30.99#ibcon#read 6, iclass 40, count 2 2006.203.08:00:30.99#ibcon#end of sib2, iclass 40, count 2 2006.203.08:00:30.99#ibcon#*after write, iclass 40, count 2 2006.203.08:00:30.99#ibcon#*before return 0, iclass 40, count 2 2006.203.08:00:30.99#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.203.08:00:30.99#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.203.08:00:30.99#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.203.08:00:30.99#ibcon#ireg 7 cls_cnt 0 2006.203.08:00:30.99#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.203.08:00:31.11#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.203.08:00:31.11#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.203.08:00:31.11#ibcon#enter wrdev, iclass 40, count 0 2006.203.08:00:31.11#ibcon#first serial, iclass 40, count 0 2006.203.08:00:31.11#ibcon#enter sib2, iclass 40, count 0 2006.203.08:00:31.11#ibcon#flushed, iclass 40, count 0 2006.203.08:00:31.11#ibcon#about to write, iclass 40, count 0 2006.203.08:00:31.11#ibcon#wrote, iclass 40, count 0 2006.203.08:00:31.11#ibcon#about to read 3, iclass 40, count 0 2006.203.08:00:31.13#ibcon#read 3, iclass 40, count 0 2006.203.08:00:31.13#ibcon#about to read 4, iclass 40, count 0 2006.203.08:00:31.13#ibcon#read 4, iclass 40, count 0 2006.203.08:00:31.13#ibcon#about to read 5, iclass 40, count 0 2006.203.08:00:31.13#ibcon#read 5, iclass 40, count 0 2006.203.08:00:31.13#ibcon#about to read 6, iclass 40, count 0 2006.203.08:00:31.13#ibcon#read 6, iclass 40, count 0 2006.203.08:00:31.13#ibcon#end of sib2, iclass 40, count 0 2006.203.08:00:31.13#ibcon#*mode == 0, iclass 40, count 0 2006.203.08:00:31.13#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.203.08:00:31.13#ibcon#[25=USB\r\n] 2006.203.08:00:31.13#ibcon#*before write, iclass 40, count 0 2006.203.08:00:31.13#ibcon#enter sib2, iclass 40, count 0 2006.203.08:00:31.13#ibcon#flushed, iclass 40, count 0 2006.203.08:00:31.13#ibcon#about to write, iclass 40, count 0 2006.203.08:00:31.13#ibcon#wrote, iclass 40, count 0 2006.203.08:00:31.13#ibcon#about to read 3, iclass 40, count 0 2006.203.08:00:31.16#ibcon#read 3, iclass 40, count 0 2006.203.08:00:31.16#ibcon#about to read 4, iclass 40, count 0 2006.203.08:00:31.16#ibcon#read 4, iclass 40, count 0 2006.203.08:00:31.16#ibcon#about to read 5, iclass 40, count 0 2006.203.08:00:31.16#ibcon#read 5, iclass 40, count 0 2006.203.08:00:31.16#ibcon#about to read 6, iclass 40, count 0 2006.203.08:00:31.16#ibcon#read 6, iclass 40, count 0 2006.203.08:00:31.16#ibcon#end of sib2, iclass 40, count 0 2006.203.08:00:31.16#ibcon#*after write, iclass 40, count 0 2006.203.08:00:31.16#ibcon#*before return 0, iclass 40, count 0 2006.203.08:00:31.16#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.203.08:00:31.16#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.203.08:00:31.16#ibcon#about to clear, iclass 40 cls_cnt 0 2006.203.08:00:31.16#ibcon#cleared, iclass 40 cls_cnt 0 2006.203.08:00:31.16$vc4f8/valo=6,772.99 2006.203.08:00:31.16#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.203.08:00:31.16#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.203.08:00:31.16#ibcon#ireg 17 cls_cnt 0 2006.203.08:00:31.16#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.203.08:00:31.16#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.203.08:00:31.16#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.203.08:00:31.16#ibcon#enter wrdev, iclass 4, count 0 2006.203.08:00:31.16#ibcon#first serial, iclass 4, count 0 2006.203.08:00:31.16#ibcon#enter sib2, iclass 4, count 0 2006.203.08:00:31.16#ibcon#flushed, iclass 4, count 0 2006.203.08:00:31.16#ibcon#about to write, iclass 4, count 0 2006.203.08:00:31.16#ibcon#wrote, iclass 4, count 0 2006.203.08:00:31.16#ibcon#about to read 3, iclass 4, count 0 2006.203.08:00:31.18#ibcon#read 3, iclass 4, count 0 2006.203.08:00:31.18#ibcon#about to read 4, iclass 4, count 0 2006.203.08:00:31.18#ibcon#read 4, iclass 4, count 0 2006.203.08:00:31.18#ibcon#about to read 5, iclass 4, count 0 2006.203.08:00:31.18#ibcon#read 5, iclass 4, count 0 2006.203.08:00:31.18#ibcon#about to read 6, iclass 4, count 0 2006.203.08:00:31.18#ibcon#read 6, iclass 4, count 0 2006.203.08:00:31.18#ibcon#end of sib2, iclass 4, count 0 2006.203.08:00:31.18#ibcon#*mode == 0, iclass 4, count 0 2006.203.08:00:31.18#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.203.08:00:31.18#ibcon#[26=FRQ=06,772.99\r\n] 2006.203.08:00:31.18#ibcon#*before write, iclass 4, count 0 2006.203.08:00:31.18#ibcon#enter sib2, iclass 4, count 0 2006.203.08:00:31.18#ibcon#flushed, iclass 4, count 0 2006.203.08:00:31.18#ibcon#about to write, iclass 4, count 0 2006.203.08:00:31.18#ibcon#wrote, iclass 4, count 0 2006.203.08:00:31.18#ibcon#about to read 3, iclass 4, count 0 2006.203.08:00:31.22#ibcon#read 3, iclass 4, count 0 2006.203.08:00:31.22#ibcon#about to read 4, iclass 4, count 0 2006.203.08:00:31.22#ibcon#read 4, iclass 4, count 0 2006.203.08:00:31.22#ibcon#about to read 5, iclass 4, count 0 2006.203.08:00:31.22#ibcon#read 5, iclass 4, count 0 2006.203.08:00:31.22#ibcon#about to read 6, iclass 4, count 0 2006.203.08:00:31.22#ibcon#read 6, iclass 4, count 0 2006.203.08:00:31.22#ibcon#end of sib2, iclass 4, count 0 2006.203.08:00:31.22#ibcon#*after write, iclass 4, count 0 2006.203.08:00:31.22#ibcon#*before return 0, iclass 4, count 0 2006.203.08:00:31.22#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.203.08:00:31.22#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.203.08:00:31.22#ibcon#about to clear, iclass 4 cls_cnt 0 2006.203.08:00:31.22#ibcon#cleared, iclass 4 cls_cnt 0 2006.203.08:00:31.22$vc4f8/va=6,6 2006.203.08:00:31.22#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.203.08:00:31.22#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.203.08:00:31.22#ibcon#ireg 11 cls_cnt 2 2006.203.08:00:31.22#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.203.08:00:31.28#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.203.08:00:31.28#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.203.08:00:31.28#ibcon#enter wrdev, iclass 6, count 2 2006.203.08:00:31.28#ibcon#first serial, iclass 6, count 2 2006.203.08:00:31.28#ibcon#enter sib2, iclass 6, count 2 2006.203.08:00:31.28#ibcon#flushed, iclass 6, count 2 2006.203.08:00:31.28#ibcon#about to write, iclass 6, count 2 2006.203.08:00:31.28#ibcon#wrote, iclass 6, count 2 2006.203.08:00:31.28#ibcon#about to read 3, iclass 6, count 2 2006.203.08:00:31.30#ibcon#read 3, iclass 6, count 2 2006.203.08:00:31.30#ibcon#about to read 4, iclass 6, count 2 2006.203.08:00:31.30#ibcon#read 4, iclass 6, count 2 2006.203.08:00:31.30#ibcon#about to read 5, iclass 6, count 2 2006.203.08:00:31.30#ibcon#read 5, iclass 6, count 2 2006.203.08:00:31.30#ibcon#about to read 6, iclass 6, count 2 2006.203.08:00:31.30#ibcon#read 6, iclass 6, count 2 2006.203.08:00:31.30#ibcon#end of sib2, iclass 6, count 2 2006.203.08:00:31.30#ibcon#*mode == 0, iclass 6, count 2 2006.203.08:00:31.30#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.203.08:00:31.30#ibcon#[25=AT06-06\r\n] 2006.203.08:00:31.30#ibcon#*before write, iclass 6, count 2 2006.203.08:00:31.30#ibcon#enter sib2, iclass 6, count 2 2006.203.08:00:31.30#ibcon#flushed, iclass 6, count 2 2006.203.08:00:31.30#ibcon#about to write, iclass 6, count 2 2006.203.08:00:31.30#ibcon#wrote, iclass 6, count 2 2006.203.08:00:31.30#ibcon#about to read 3, iclass 6, count 2 2006.203.08:00:31.33#ibcon#read 3, iclass 6, count 2 2006.203.08:00:31.33#ibcon#about to read 4, iclass 6, count 2 2006.203.08:00:31.33#ibcon#read 4, iclass 6, count 2 2006.203.08:00:31.33#ibcon#about to read 5, iclass 6, count 2 2006.203.08:00:31.33#ibcon#read 5, iclass 6, count 2 2006.203.08:00:31.33#ibcon#about to read 6, iclass 6, count 2 2006.203.08:00:31.33#ibcon#read 6, iclass 6, count 2 2006.203.08:00:31.33#ibcon#end of sib2, iclass 6, count 2 2006.203.08:00:31.33#ibcon#*after write, iclass 6, count 2 2006.203.08:00:31.33#ibcon#*before return 0, iclass 6, count 2 2006.203.08:00:31.33#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.203.08:00:31.33#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.203.08:00:31.33#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.203.08:00:31.33#ibcon#ireg 7 cls_cnt 0 2006.203.08:00:31.33#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.203.08:00:31.45#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.203.08:00:31.45#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.203.08:00:31.45#ibcon#enter wrdev, iclass 6, count 0 2006.203.08:00:31.45#ibcon#first serial, iclass 6, count 0 2006.203.08:00:31.45#ibcon#enter sib2, iclass 6, count 0 2006.203.08:00:31.45#ibcon#flushed, iclass 6, count 0 2006.203.08:00:31.45#ibcon#about to write, iclass 6, count 0 2006.203.08:00:31.45#ibcon#wrote, iclass 6, count 0 2006.203.08:00:31.45#ibcon#about to read 3, iclass 6, count 0 2006.203.08:00:31.47#ibcon#read 3, iclass 6, count 0 2006.203.08:00:31.47#ibcon#about to read 4, iclass 6, count 0 2006.203.08:00:31.47#ibcon#read 4, iclass 6, count 0 2006.203.08:00:31.47#ibcon#about to read 5, iclass 6, count 0 2006.203.08:00:31.47#ibcon#read 5, iclass 6, count 0 2006.203.08:00:31.47#ibcon#about to read 6, iclass 6, count 0 2006.203.08:00:31.47#ibcon#read 6, iclass 6, count 0 2006.203.08:00:31.47#ibcon#end of sib2, iclass 6, count 0 2006.203.08:00:31.47#ibcon#*mode == 0, iclass 6, count 0 2006.203.08:00:31.47#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.203.08:00:31.47#ibcon#[25=USB\r\n] 2006.203.08:00:31.47#ibcon#*before write, iclass 6, count 0 2006.203.08:00:31.47#ibcon#enter sib2, iclass 6, count 0 2006.203.08:00:31.47#ibcon#flushed, iclass 6, count 0 2006.203.08:00:31.47#ibcon#about to write, iclass 6, count 0 2006.203.08:00:31.47#ibcon#wrote, iclass 6, count 0 2006.203.08:00:31.47#ibcon#about to read 3, iclass 6, count 0 2006.203.08:00:31.50#ibcon#read 3, iclass 6, count 0 2006.203.08:00:31.50#ibcon#about to read 4, iclass 6, count 0 2006.203.08:00:31.50#ibcon#read 4, iclass 6, count 0 2006.203.08:00:31.50#ibcon#about to read 5, iclass 6, count 0 2006.203.08:00:31.50#ibcon#read 5, iclass 6, count 0 2006.203.08:00:31.50#ibcon#about to read 6, iclass 6, count 0 2006.203.08:00:31.50#ibcon#read 6, iclass 6, count 0 2006.203.08:00:31.50#ibcon#end of sib2, iclass 6, count 0 2006.203.08:00:31.50#ibcon#*after write, iclass 6, count 0 2006.203.08:00:31.50#ibcon#*before return 0, iclass 6, count 0 2006.203.08:00:31.50#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.203.08:00:31.50#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.203.08:00:31.50#ibcon#about to clear, iclass 6 cls_cnt 0 2006.203.08:00:31.50#ibcon#cleared, iclass 6 cls_cnt 0 2006.203.08:00:31.50$vc4f8/valo=7,832.99 2006.203.08:00:31.50#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.203.08:00:31.50#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.203.08:00:31.50#ibcon#ireg 17 cls_cnt 0 2006.203.08:00:31.50#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.203.08:00:31.50#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.203.08:00:31.50#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.203.08:00:31.50#ibcon#enter wrdev, iclass 10, count 0 2006.203.08:00:31.50#ibcon#first serial, iclass 10, count 0 2006.203.08:00:31.50#ibcon#enter sib2, iclass 10, count 0 2006.203.08:00:31.50#ibcon#flushed, iclass 10, count 0 2006.203.08:00:31.50#ibcon#about to write, iclass 10, count 0 2006.203.08:00:31.50#ibcon#wrote, iclass 10, count 0 2006.203.08:00:31.50#ibcon#about to read 3, iclass 10, count 0 2006.203.08:00:31.52#ibcon#read 3, iclass 10, count 0 2006.203.08:00:31.52#ibcon#about to read 4, iclass 10, count 0 2006.203.08:00:31.52#ibcon#read 4, iclass 10, count 0 2006.203.08:00:31.52#ibcon#about to read 5, iclass 10, count 0 2006.203.08:00:31.52#ibcon#read 5, iclass 10, count 0 2006.203.08:00:31.52#ibcon#about to read 6, iclass 10, count 0 2006.203.08:00:31.52#ibcon#read 6, iclass 10, count 0 2006.203.08:00:31.52#ibcon#end of sib2, iclass 10, count 0 2006.203.08:00:31.52#ibcon#*mode == 0, iclass 10, count 0 2006.203.08:00:31.52#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.203.08:00:31.52#ibcon#[26=FRQ=07,832.99\r\n] 2006.203.08:00:31.52#ibcon#*before write, iclass 10, count 0 2006.203.08:00:31.52#ibcon#enter sib2, iclass 10, count 0 2006.203.08:00:31.52#ibcon#flushed, iclass 10, count 0 2006.203.08:00:31.52#ibcon#about to write, iclass 10, count 0 2006.203.08:00:31.52#ibcon#wrote, iclass 10, count 0 2006.203.08:00:31.52#ibcon#about to read 3, iclass 10, count 0 2006.203.08:00:31.56#ibcon#read 3, iclass 10, count 0 2006.203.08:00:31.56#ibcon#about to read 4, iclass 10, count 0 2006.203.08:00:31.56#ibcon#read 4, iclass 10, count 0 2006.203.08:00:31.56#ibcon#about to read 5, iclass 10, count 0 2006.203.08:00:31.56#ibcon#read 5, iclass 10, count 0 2006.203.08:00:31.56#ibcon#about to read 6, iclass 10, count 0 2006.203.08:00:31.56#ibcon#read 6, iclass 10, count 0 2006.203.08:00:31.56#ibcon#end of sib2, iclass 10, count 0 2006.203.08:00:31.56#ibcon#*after write, iclass 10, count 0 2006.203.08:00:31.56#ibcon#*before return 0, iclass 10, count 0 2006.203.08:00:31.56#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.203.08:00:31.56#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.203.08:00:31.56#ibcon#about to clear, iclass 10 cls_cnt 0 2006.203.08:00:31.56#ibcon#cleared, iclass 10 cls_cnt 0 2006.203.08:00:31.56$vc4f8/va=7,7 2006.203.08:00:31.56#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.203.08:00:31.56#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.203.08:00:31.56#ibcon#ireg 11 cls_cnt 2 2006.203.08:00:31.56#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.203.08:00:31.62#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.203.08:00:31.62#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.203.08:00:31.62#ibcon#enter wrdev, iclass 12, count 2 2006.203.08:00:31.62#ibcon#first serial, iclass 12, count 2 2006.203.08:00:31.62#ibcon#enter sib2, iclass 12, count 2 2006.203.08:00:31.62#ibcon#flushed, iclass 12, count 2 2006.203.08:00:31.62#ibcon#about to write, iclass 12, count 2 2006.203.08:00:31.62#ibcon#wrote, iclass 12, count 2 2006.203.08:00:31.62#ibcon#about to read 3, iclass 12, count 2 2006.203.08:00:31.64#ibcon#read 3, iclass 12, count 2 2006.203.08:00:31.64#ibcon#about to read 4, iclass 12, count 2 2006.203.08:00:31.64#ibcon#read 4, iclass 12, count 2 2006.203.08:00:31.64#ibcon#about to read 5, iclass 12, count 2 2006.203.08:00:31.64#ibcon#read 5, iclass 12, count 2 2006.203.08:00:31.64#ibcon#about to read 6, iclass 12, count 2 2006.203.08:00:31.64#ibcon#read 6, iclass 12, count 2 2006.203.08:00:31.64#ibcon#end of sib2, iclass 12, count 2 2006.203.08:00:31.64#ibcon#*mode == 0, iclass 12, count 2 2006.203.08:00:31.64#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.203.08:00:31.64#ibcon#[25=AT07-07\r\n] 2006.203.08:00:31.64#ibcon#*before write, iclass 12, count 2 2006.203.08:00:31.64#ibcon#enter sib2, iclass 12, count 2 2006.203.08:00:31.64#ibcon#flushed, iclass 12, count 2 2006.203.08:00:31.64#ibcon#about to write, iclass 12, count 2 2006.203.08:00:31.64#ibcon#wrote, iclass 12, count 2 2006.203.08:00:31.64#ibcon#about to read 3, iclass 12, count 2 2006.203.08:00:31.67#ibcon#read 3, iclass 12, count 2 2006.203.08:00:31.67#ibcon#about to read 4, iclass 12, count 2 2006.203.08:00:31.67#ibcon#read 4, iclass 12, count 2 2006.203.08:00:31.67#ibcon#about to read 5, iclass 12, count 2 2006.203.08:00:31.67#ibcon#read 5, iclass 12, count 2 2006.203.08:00:31.67#ibcon#about to read 6, iclass 12, count 2 2006.203.08:00:31.67#ibcon#read 6, iclass 12, count 2 2006.203.08:00:31.67#ibcon#end of sib2, iclass 12, count 2 2006.203.08:00:31.67#ibcon#*after write, iclass 12, count 2 2006.203.08:00:31.67#ibcon#*before return 0, iclass 12, count 2 2006.203.08:00:31.67#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.203.08:00:31.67#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.203.08:00:31.67#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.203.08:00:31.67#ibcon#ireg 7 cls_cnt 0 2006.203.08:00:31.67#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.203.08:00:31.79#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.203.08:00:31.79#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.203.08:00:31.79#ibcon#enter wrdev, iclass 12, count 0 2006.203.08:00:31.79#ibcon#first serial, iclass 12, count 0 2006.203.08:00:31.79#ibcon#enter sib2, iclass 12, count 0 2006.203.08:00:31.79#ibcon#flushed, iclass 12, count 0 2006.203.08:00:31.79#ibcon#about to write, iclass 12, count 0 2006.203.08:00:31.79#ibcon#wrote, iclass 12, count 0 2006.203.08:00:31.79#ibcon#about to read 3, iclass 12, count 0 2006.203.08:00:31.81#ibcon#read 3, iclass 12, count 0 2006.203.08:00:31.81#ibcon#about to read 4, iclass 12, count 0 2006.203.08:00:31.81#ibcon#read 4, iclass 12, count 0 2006.203.08:00:31.81#ibcon#about to read 5, iclass 12, count 0 2006.203.08:00:31.81#ibcon#read 5, iclass 12, count 0 2006.203.08:00:31.81#ibcon#about to read 6, iclass 12, count 0 2006.203.08:00:31.81#ibcon#read 6, iclass 12, count 0 2006.203.08:00:31.81#ibcon#end of sib2, iclass 12, count 0 2006.203.08:00:31.81#ibcon#*mode == 0, iclass 12, count 0 2006.203.08:00:31.81#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.203.08:00:31.81#ibcon#[25=USB\r\n] 2006.203.08:00:31.81#ibcon#*before write, iclass 12, count 0 2006.203.08:00:31.81#ibcon#enter sib2, iclass 12, count 0 2006.203.08:00:31.81#ibcon#flushed, iclass 12, count 0 2006.203.08:00:31.81#ibcon#about to write, iclass 12, count 0 2006.203.08:00:31.81#ibcon#wrote, iclass 12, count 0 2006.203.08:00:31.81#ibcon#about to read 3, iclass 12, count 0 2006.203.08:00:31.84#ibcon#read 3, iclass 12, count 0 2006.203.08:00:31.84#ibcon#about to read 4, iclass 12, count 0 2006.203.08:00:31.84#ibcon#read 4, iclass 12, count 0 2006.203.08:00:31.84#ibcon#about to read 5, iclass 12, count 0 2006.203.08:00:31.84#ibcon#read 5, iclass 12, count 0 2006.203.08:00:31.84#ibcon#about to read 6, iclass 12, count 0 2006.203.08:00:31.84#ibcon#read 6, iclass 12, count 0 2006.203.08:00:31.84#ibcon#end of sib2, iclass 12, count 0 2006.203.08:00:31.84#ibcon#*after write, iclass 12, count 0 2006.203.08:00:31.84#ibcon#*before return 0, iclass 12, count 0 2006.203.08:00:31.84#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.203.08:00:31.84#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.203.08:00:31.84#ibcon#about to clear, iclass 12 cls_cnt 0 2006.203.08:00:31.84#ibcon#cleared, iclass 12 cls_cnt 0 2006.203.08:00:31.84$vc4f8/valo=8,852.99 2006.203.08:00:31.84#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.203.08:00:31.84#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.203.08:00:31.84#ibcon#ireg 17 cls_cnt 0 2006.203.08:00:31.84#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.203.08:00:31.84#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.203.08:00:31.84#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.203.08:00:31.84#ibcon#enter wrdev, iclass 14, count 0 2006.203.08:00:31.84#ibcon#first serial, iclass 14, count 0 2006.203.08:00:31.84#ibcon#enter sib2, iclass 14, count 0 2006.203.08:00:31.84#ibcon#flushed, iclass 14, count 0 2006.203.08:00:31.84#ibcon#about to write, iclass 14, count 0 2006.203.08:00:31.84#ibcon#wrote, iclass 14, count 0 2006.203.08:00:31.84#ibcon#about to read 3, iclass 14, count 0 2006.203.08:00:31.86#ibcon#read 3, iclass 14, count 0 2006.203.08:00:31.86#ibcon#about to read 4, iclass 14, count 0 2006.203.08:00:31.86#ibcon#read 4, iclass 14, count 0 2006.203.08:00:31.86#ibcon#about to read 5, iclass 14, count 0 2006.203.08:00:31.86#ibcon#read 5, iclass 14, count 0 2006.203.08:00:31.86#ibcon#about to read 6, iclass 14, count 0 2006.203.08:00:31.86#ibcon#read 6, iclass 14, count 0 2006.203.08:00:31.86#ibcon#end of sib2, iclass 14, count 0 2006.203.08:00:31.86#ibcon#*mode == 0, iclass 14, count 0 2006.203.08:00:31.86#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.203.08:00:31.86#ibcon#[26=FRQ=08,852.99\r\n] 2006.203.08:00:31.86#ibcon#*before write, iclass 14, count 0 2006.203.08:00:31.86#ibcon#enter sib2, iclass 14, count 0 2006.203.08:00:31.86#ibcon#flushed, iclass 14, count 0 2006.203.08:00:31.86#ibcon#about to write, iclass 14, count 0 2006.203.08:00:31.86#ibcon#wrote, iclass 14, count 0 2006.203.08:00:31.86#ibcon#about to read 3, iclass 14, count 0 2006.203.08:00:31.91#ibcon#read 3, iclass 14, count 0 2006.203.08:00:31.91#ibcon#about to read 4, iclass 14, count 0 2006.203.08:00:31.91#ibcon#read 4, iclass 14, count 0 2006.203.08:00:31.91#ibcon#about to read 5, iclass 14, count 0 2006.203.08:00:31.91#ibcon#read 5, iclass 14, count 0 2006.203.08:00:31.91#ibcon#about to read 6, iclass 14, count 0 2006.203.08:00:31.91#ibcon#read 6, iclass 14, count 0 2006.203.08:00:31.91#ibcon#end of sib2, iclass 14, count 0 2006.203.08:00:31.91#ibcon#*after write, iclass 14, count 0 2006.203.08:00:31.91#ibcon#*before return 0, iclass 14, count 0 2006.203.08:00:31.91#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.203.08:00:31.91#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.203.08:00:31.91#ibcon#about to clear, iclass 14 cls_cnt 0 2006.203.08:00:31.91#ibcon#cleared, iclass 14 cls_cnt 0 2006.203.08:00:31.91$vc4f8/va=8,6 2006.203.08:00:31.91#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.203.08:00:31.91#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.203.08:00:31.91#ibcon#ireg 11 cls_cnt 2 2006.203.08:00:31.91#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.203.08:00:31.96#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.203.08:00:31.96#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.203.08:00:31.96#ibcon#enter wrdev, iclass 16, count 2 2006.203.08:00:31.96#ibcon#first serial, iclass 16, count 2 2006.203.08:00:31.96#ibcon#enter sib2, iclass 16, count 2 2006.203.08:00:31.96#ibcon#flushed, iclass 16, count 2 2006.203.08:00:31.96#ibcon#about to write, iclass 16, count 2 2006.203.08:00:31.96#ibcon#wrote, iclass 16, count 2 2006.203.08:00:31.96#ibcon#about to read 3, iclass 16, count 2 2006.203.08:00:31.98#ibcon#read 3, iclass 16, count 2 2006.203.08:00:31.98#ibcon#about to read 4, iclass 16, count 2 2006.203.08:00:31.98#ibcon#read 4, iclass 16, count 2 2006.203.08:00:31.98#ibcon#about to read 5, iclass 16, count 2 2006.203.08:00:31.98#ibcon#read 5, iclass 16, count 2 2006.203.08:00:31.98#ibcon#about to read 6, iclass 16, count 2 2006.203.08:00:31.98#ibcon#read 6, iclass 16, count 2 2006.203.08:00:31.98#ibcon#end of sib2, iclass 16, count 2 2006.203.08:00:31.98#ibcon#*mode == 0, iclass 16, count 2 2006.203.08:00:31.98#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.203.08:00:31.98#ibcon#[25=AT08-06\r\n] 2006.203.08:00:31.98#ibcon#*before write, iclass 16, count 2 2006.203.08:00:31.98#ibcon#enter sib2, iclass 16, count 2 2006.203.08:00:31.98#ibcon#flushed, iclass 16, count 2 2006.203.08:00:31.98#ibcon#about to write, iclass 16, count 2 2006.203.08:00:31.98#ibcon#wrote, iclass 16, count 2 2006.203.08:00:31.98#ibcon#about to read 3, iclass 16, count 2 2006.203.08:00:32.01#ibcon#read 3, iclass 16, count 2 2006.203.08:00:32.01#ibcon#about to read 4, iclass 16, count 2 2006.203.08:00:32.01#ibcon#read 4, iclass 16, count 2 2006.203.08:00:32.01#ibcon#about to read 5, iclass 16, count 2 2006.203.08:00:32.01#ibcon#read 5, iclass 16, count 2 2006.203.08:00:32.01#ibcon#about to read 6, iclass 16, count 2 2006.203.08:00:32.01#ibcon#read 6, iclass 16, count 2 2006.203.08:00:32.01#ibcon#end of sib2, iclass 16, count 2 2006.203.08:00:32.01#ibcon#*after write, iclass 16, count 2 2006.203.08:00:32.01#ibcon#*before return 0, iclass 16, count 2 2006.203.08:00:32.01#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.203.08:00:32.01#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.203.08:00:32.01#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.203.08:00:32.01#ibcon#ireg 7 cls_cnt 0 2006.203.08:00:32.01#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.203.08:00:32.13#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.203.08:00:32.13#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.203.08:00:32.13#ibcon#enter wrdev, iclass 16, count 0 2006.203.08:00:32.13#ibcon#first serial, iclass 16, count 0 2006.203.08:00:32.13#ibcon#enter sib2, iclass 16, count 0 2006.203.08:00:32.13#ibcon#flushed, iclass 16, count 0 2006.203.08:00:32.13#ibcon#about to write, iclass 16, count 0 2006.203.08:00:32.13#ibcon#wrote, iclass 16, count 0 2006.203.08:00:32.13#ibcon#about to read 3, iclass 16, count 0 2006.203.08:00:32.15#ibcon#read 3, iclass 16, count 0 2006.203.08:00:32.15#ibcon#about to read 4, iclass 16, count 0 2006.203.08:00:32.15#ibcon#read 4, iclass 16, count 0 2006.203.08:00:32.15#ibcon#about to read 5, iclass 16, count 0 2006.203.08:00:32.15#ibcon#read 5, iclass 16, count 0 2006.203.08:00:32.15#ibcon#about to read 6, iclass 16, count 0 2006.203.08:00:32.15#ibcon#read 6, iclass 16, count 0 2006.203.08:00:32.15#ibcon#end of sib2, iclass 16, count 0 2006.203.08:00:32.15#ibcon#*mode == 0, iclass 16, count 0 2006.203.08:00:32.15#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.203.08:00:32.15#ibcon#[25=USB\r\n] 2006.203.08:00:32.15#ibcon#*before write, iclass 16, count 0 2006.203.08:00:32.15#ibcon#enter sib2, iclass 16, count 0 2006.203.08:00:32.15#ibcon#flushed, iclass 16, count 0 2006.203.08:00:32.15#ibcon#about to write, iclass 16, count 0 2006.203.08:00:32.15#ibcon#wrote, iclass 16, count 0 2006.203.08:00:32.15#ibcon#about to read 3, iclass 16, count 0 2006.203.08:00:32.18#ibcon#read 3, iclass 16, count 0 2006.203.08:00:32.18#ibcon#about to read 4, iclass 16, count 0 2006.203.08:00:32.18#ibcon#read 4, iclass 16, count 0 2006.203.08:00:32.18#ibcon#about to read 5, iclass 16, count 0 2006.203.08:00:32.18#ibcon#read 5, iclass 16, count 0 2006.203.08:00:32.18#ibcon#about to read 6, iclass 16, count 0 2006.203.08:00:32.18#ibcon#read 6, iclass 16, count 0 2006.203.08:00:32.18#ibcon#end of sib2, iclass 16, count 0 2006.203.08:00:32.18#ibcon#*after write, iclass 16, count 0 2006.203.08:00:32.18#ibcon#*before return 0, iclass 16, count 0 2006.203.08:00:32.18#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.203.08:00:32.18#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.203.08:00:32.18#ibcon#about to clear, iclass 16 cls_cnt 0 2006.203.08:00:32.18#ibcon#cleared, iclass 16 cls_cnt 0 2006.203.08:00:32.18$vc4f8/vblo=1,632.99 2006.203.08:00:32.18#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.203.08:00:32.18#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.203.08:00:32.18#ibcon#ireg 17 cls_cnt 0 2006.203.08:00:32.18#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.203.08:00:32.18#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.203.08:00:32.18#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.203.08:00:32.18#ibcon#enter wrdev, iclass 18, count 0 2006.203.08:00:32.18#ibcon#first serial, iclass 18, count 0 2006.203.08:00:32.18#ibcon#enter sib2, iclass 18, count 0 2006.203.08:00:32.18#ibcon#flushed, iclass 18, count 0 2006.203.08:00:32.18#ibcon#about to write, iclass 18, count 0 2006.203.08:00:32.18#ibcon#wrote, iclass 18, count 0 2006.203.08:00:32.18#ibcon#about to read 3, iclass 18, count 0 2006.203.08:00:32.20#ibcon#read 3, iclass 18, count 0 2006.203.08:00:32.20#ibcon#about to read 4, iclass 18, count 0 2006.203.08:00:32.20#ibcon#read 4, iclass 18, count 0 2006.203.08:00:32.20#ibcon#about to read 5, iclass 18, count 0 2006.203.08:00:32.20#ibcon#read 5, iclass 18, count 0 2006.203.08:00:32.20#ibcon#about to read 6, iclass 18, count 0 2006.203.08:00:32.20#ibcon#read 6, iclass 18, count 0 2006.203.08:00:32.20#ibcon#end of sib2, iclass 18, count 0 2006.203.08:00:32.20#ibcon#*mode == 0, iclass 18, count 0 2006.203.08:00:32.20#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.203.08:00:32.20#ibcon#[28=FRQ=01,632.99\r\n] 2006.203.08:00:32.20#ibcon#*before write, iclass 18, count 0 2006.203.08:00:32.20#ibcon#enter sib2, iclass 18, count 0 2006.203.08:00:32.20#ibcon#flushed, iclass 18, count 0 2006.203.08:00:32.20#ibcon#about to write, iclass 18, count 0 2006.203.08:00:32.20#ibcon#wrote, iclass 18, count 0 2006.203.08:00:32.20#ibcon#about to read 3, iclass 18, count 0 2006.203.08:00:32.24#ibcon#read 3, iclass 18, count 0 2006.203.08:00:32.24#ibcon#about to read 4, iclass 18, count 0 2006.203.08:00:32.24#ibcon#read 4, iclass 18, count 0 2006.203.08:00:32.24#ibcon#about to read 5, iclass 18, count 0 2006.203.08:00:32.24#ibcon#read 5, iclass 18, count 0 2006.203.08:00:32.24#ibcon#about to read 6, iclass 18, count 0 2006.203.08:00:32.24#ibcon#read 6, iclass 18, count 0 2006.203.08:00:32.24#ibcon#end of sib2, iclass 18, count 0 2006.203.08:00:32.24#ibcon#*after write, iclass 18, count 0 2006.203.08:00:32.24#ibcon#*before return 0, iclass 18, count 0 2006.203.08:00:32.24#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.203.08:00:32.24#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.203.08:00:32.24#ibcon#about to clear, iclass 18 cls_cnt 0 2006.203.08:00:32.24#ibcon#cleared, iclass 18 cls_cnt 0 2006.203.08:00:32.24$vc4f8/vb=1,4 2006.203.08:00:32.24#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.203.08:00:32.24#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.203.08:00:32.24#ibcon#ireg 11 cls_cnt 2 2006.203.08:00:32.24#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.203.08:00:32.24#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.203.08:00:32.24#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.203.08:00:32.24#ibcon#enter wrdev, iclass 20, count 2 2006.203.08:00:32.24#ibcon#first serial, iclass 20, count 2 2006.203.08:00:32.24#ibcon#enter sib2, iclass 20, count 2 2006.203.08:00:32.24#ibcon#flushed, iclass 20, count 2 2006.203.08:00:32.24#ibcon#about to write, iclass 20, count 2 2006.203.08:00:32.24#ibcon#wrote, iclass 20, count 2 2006.203.08:00:32.24#ibcon#about to read 3, iclass 20, count 2 2006.203.08:00:32.26#ibcon#read 3, iclass 20, count 2 2006.203.08:00:32.26#ibcon#about to read 4, iclass 20, count 2 2006.203.08:00:32.26#ibcon#read 4, iclass 20, count 2 2006.203.08:00:32.26#ibcon#about to read 5, iclass 20, count 2 2006.203.08:00:32.26#ibcon#read 5, iclass 20, count 2 2006.203.08:00:32.26#ibcon#about to read 6, iclass 20, count 2 2006.203.08:00:32.26#ibcon#read 6, iclass 20, count 2 2006.203.08:00:32.26#ibcon#end of sib2, iclass 20, count 2 2006.203.08:00:32.26#ibcon#*mode == 0, iclass 20, count 2 2006.203.08:00:32.26#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.203.08:00:32.26#ibcon#[27=AT01-04\r\n] 2006.203.08:00:32.26#ibcon#*before write, iclass 20, count 2 2006.203.08:00:32.26#ibcon#enter sib2, iclass 20, count 2 2006.203.08:00:32.26#ibcon#flushed, iclass 20, count 2 2006.203.08:00:32.26#ibcon#about to write, iclass 20, count 2 2006.203.08:00:32.26#ibcon#wrote, iclass 20, count 2 2006.203.08:00:32.26#ibcon#about to read 3, iclass 20, count 2 2006.203.08:00:32.29#ibcon#read 3, iclass 20, count 2 2006.203.08:00:32.29#ibcon#about to read 4, iclass 20, count 2 2006.203.08:00:32.29#ibcon#read 4, iclass 20, count 2 2006.203.08:00:32.29#ibcon#about to read 5, iclass 20, count 2 2006.203.08:00:32.29#ibcon#read 5, iclass 20, count 2 2006.203.08:00:32.29#ibcon#about to read 6, iclass 20, count 2 2006.203.08:00:32.29#ibcon#read 6, iclass 20, count 2 2006.203.08:00:32.29#ibcon#end of sib2, iclass 20, count 2 2006.203.08:00:32.29#ibcon#*after write, iclass 20, count 2 2006.203.08:00:32.29#ibcon#*before return 0, iclass 20, count 2 2006.203.08:00:32.29#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.203.08:00:32.29#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.203.08:00:32.29#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.203.08:00:32.29#ibcon#ireg 7 cls_cnt 0 2006.203.08:00:32.29#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.203.08:00:32.41#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.203.08:00:32.41#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.203.08:00:32.41#ibcon#enter wrdev, iclass 20, count 0 2006.203.08:00:32.41#ibcon#first serial, iclass 20, count 0 2006.203.08:00:32.41#ibcon#enter sib2, iclass 20, count 0 2006.203.08:00:32.41#ibcon#flushed, iclass 20, count 0 2006.203.08:00:32.41#ibcon#about to write, iclass 20, count 0 2006.203.08:00:32.41#ibcon#wrote, iclass 20, count 0 2006.203.08:00:32.41#ibcon#about to read 3, iclass 20, count 0 2006.203.08:00:32.43#ibcon#read 3, iclass 20, count 0 2006.203.08:00:32.43#ibcon#about to read 4, iclass 20, count 0 2006.203.08:00:32.43#ibcon#read 4, iclass 20, count 0 2006.203.08:00:32.43#ibcon#about to read 5, iclass 20, count 0 2006.203.08:00:32.43#ibcon#read 5, iclass 20, count 0 2006.203.08:00:32.43#ibcon#about to read 6, iclass 20, count 0 2006.203.08:00:32.43#ibcon#read 6, iclass 20, count 0 2006.203.08:00:32.43#ibcon#end of sib2, iclass 20, count 0 2006.203.08:00:32.43#ibcon#*mode == 0, iclass 20, count 0 2006.203.08:00:32.43#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.203.08:00:32.43#ibcon#[27=USB\r\n] 2006.203.08:00:32.43#ibcon#*before write, iclass 20, count 0 2006.203.08:00:32.43#ibcon#enter sib2, iclass 20, count 0 2006.203.08:00:32.43#ibcon#flushed, iclass 20, count 0 2006.203.08:00:32.43#ibcon#about to write, iclass 20, count 0 2006.203.08:00:32.43#ibcon#wrote, iclass 20, count 0 2006.203.08:00:32.43#ibcon#about to read 3, iclass 20, count 0 2006.203.08:00:32.46#ibcon#read 3, iclass 20, count 0 2006.203.08:00:32.46#ibcon#about to read 4, iclass 20, count 0 2006.203.08:00:32.46#ibcon#read 4, iclass 20, count 0 2006.203.08:00:32.46#ibcon#about to read 5, iclass 20, count 0 2006.203.08:00:32.46#ibcon#read 5, iclass 20, count 0 2006.203.08:00:32.46#ibcon#about to read 6, iclass 20, count 0 2006.203.08:00:32.46#ibcon#read 6, iclass 20, count 0 2006.203.08:00:32.46#ibcon#end of sib2, iclass 20, count 0 2006.203.08:00:32.46#ibcon#*after write, iclass 20, count 0 2006.203.08:00:32.46#ibcon#*before return 0, iclass 20, count 0 2006.203.08:00:32.46#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.203.08:00:32.46#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.203.08:00:32.46#ibcon#about to clear, iclass 20 cls_cnt 0 2006.203.08:00:32.46#ibcon#cleared, iclass 20 cls_cnt 0 2006.203.08:00:32.46$vc4f8/vblo=2,640.99 2006.203.08:00:32.46#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.203.08:00:32.46#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.203.08:00:32.46#ibcon#ireg 17 cls_cnt 0 2006.203.08:00:32.46#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.203.08:00:32.46#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.203.08:00:32.46#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.203.08:00:32.46#ibcon#enter wrdev, iclass 22, count 0 2006.203.08:00:32.46#ibcon#first serial, iclass 22, count 0 2006.203.08:00:32.46#ibcon#enter sib2, iclass 22, count 0 2006.203.08:00:32.46#ibcon#flushed, iclass 22, count 0 2006.203.08:00:32.46#ibcon#about to write, iclass 22, count 0 2006.203.08:00:32.46#ibcon#wrote, iclass 22, count 0 2006.203.08:00:32.46#ibcon#about to read 3, iclass 22, count 0 2006.203.08:00:32.48#ibcon#read 3, iclass 22, count 0 2006.203.08:00:32.48#ibcon#about to read 4, iclass 22, count 0 2006.203.08:00:32.48#ibcon#read 4, iclass 22, count 0 2006.203.08:00:32.48#ibcon#about to read 5, iclass 22, count 0 2006.203.08:00:32.48#ibcon#read 5, iclass 22, count 0 2006.203.08:00:32.48#ibcon#about to read 6, iclass 22, count 0 2006.203.08:00:32.48#ibcon#read 6, iclass 22, count 0 2006.203.08:00:32.48#ibcon#end of sib2, iclass 22, count 0 2006.203.08:00:32.48#ibcon#*mode == 0, iclass 22, count 0 2006.203.08:00:32.48#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.203.08:00:32.48#ibcon#[28=FRQ=02,640.99\r\n] 2006.203.08:00:32.48#ibcon#*before write, iclass 22, count 0 2006.203.08:00:32.48#ibcon#enter sib2, iclass 22, count 0 2006.203.08:00:32.48#ibcon#flushed, iclass 22, count 0 2006.203.08:00:32.48#ibcon#about to write, iclass 22, count 0 2006.203.08:00:32.48#ibcon#wrote, iclass 22, count 0 2006.203.08:00:32.48#ibcon#about to read 3, iclass 22, count 0 2006.203.08:00:32.52#ibcon#read 3, iclass 22, count 0 2006.203.08:00:32.52#ibcon#about to read 4, iclass 22, count 0 2006.203.08:00:32.52#ibcon#read 4, iclass 22, count 0 2006.203.08:00:32.52#ibcon#about to read 5, iclass 22, count 0 2006.203.08:00:32.52#ibcon#read 5, iclass 22, count 0 2006.203.08:00:32.52#ibcon#about to read 6, iclass 22, count 0 2006.203.08:00:32.52#ibcon#read 6, iclass 22, count 0 2006.203.08:00:32.52#ibcon#end of sib2, iclass 22, count 0 2006.203.08:00:32.52#ibcon#*after write, iclass 22, count 0 2006.203.08:00:32.52#ibcon#*before return 0, iclass 22, count 0 2006.203.08:00:32.52#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.203.08:00:32.52#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.203.08:00:32.52#ibcon#about to clear, iclass 22 cls_cnt 0 2006.203.08:00:32.52#ibcon#cleared, iclass 22 cls_cnt 0 2006.203.08:00:32.52$vc4f8/vb=2,4 2006.203.08:00:32.52#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.203.08:00:32.52#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.203.08:00:32.52#ibcon#ireg 11 cls_cnt 2 2006.203.08:00:32.52#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.203.08:00:32.58#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.203.08:00:32.58#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.203.08:00:32.58#ibcon#enter wrdev, iclass 24, count 2 2006.203.08:00:32.58#ibcon#first serial, iclass 24, count 2 2006.203.08:00:32.58#ibcon#enter sib2, iclass 24, count 2 2006.203.08:00:32.58#ibcon#flushed, iclass 24, count 2 2006.203.08:00:32.58#ibcon#about to write, iclass 24, count 2 2006.203.08:00:32.58#ibcon#wrote, iclass 24, count 2 2006.203.08:00:32.58#ibcon#about to read 3, iclass 24, count 2 2006.203.08:00:32.60#ibcon#read 3, iclass 24, count 2 2006.203.08:00:32.60#ibcon#about to read 4, iclass 24, count 2 2006.203.08:00:32.60#ibcon#read 4, iclass 24, count 2 2006.203.08:00:32.60#ibcon#about to read 5, iclass 24, count 2 2006.203.08:00:32.60#ibcon#read 5, iclass 24, count 2 2006.203.08:00:32.60#ibcon#about to read 6, iclass 24, count 2 2006.203.08:00:32.60#ibcon#read 6, iclass 24, count 2 2006.203.08:00:32.60#ibcon#end of sib2, iclass 24, count 2 2006.203.08:00:32.60#ibcon#*mode == 0, iclass 24, count 2 2006.203.08:00:32.60#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.203.08:00:32.60#ibcon#[27=AT02-04\r\n] 2006.203.08:00:32.60#ibcon#*before write, iclass 24, count 2 2006.203.08:00:32.60#ibcon#enter sib2, iclass 24, count 2 2006.203.08:00:32.60#ibcon#flushed, iclass 24, count 2 2006.203.08:00:32.60#ibcon#about to write, iclass 24, count 2 2006.203.08:00:32.60#ibcon#wrote, iclass 24, count 2 2006.203.08:00:32.60#ibcon#about to read 3, iclass 24, count 2 2006.203.08:00:32.64#ibcon#read 3, iclass 24, count 2 2006.203.08:00:32.64#ibcon#about to read 4, iclass 24, count 2 2006.203.08:00:32.64#ibcon#read 4, iclass 24, count 2 2006.203.08:00:32.64#ibcon#about to read 5, iclass 24, count 2 2006.203.08:00:32.64#ibcon#read 5, iclass 24, count 2 2006.203.08:00:32.64#ibcon#about to read 6, iclass 24, count 2 2006.203.08:00:32.64#ibcon#read 6, iclass 24, count 2 2006.203.08:00:32.64#ibcon#end of sib2, iclass 24, count 2 2006.203.08:00:32.64#ibcon#*after write, iclass 24, count 2 2006.203.08:00:32.64#ibcon#*before return 0, iclass 24, count 2 2006.203.08:00:32.64#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.203.08:00:32.64#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.203.08:00:32.64#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.203.08:00:32.64#ibcon#ireg 7 cls_cnt 0 2006.203.08:00:32.64#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.203.08:00:32.76#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.203.08:00:32.76#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.203.08:00:32.76#ibcon#enter wrdev, iclass 24, count 0 2006.203.08:00:32.76#ibcon#first serial, iclass 24, count 0 2006.203.08:00:32.76#ibcon#enter sib2, iclass 24, count 0 2006.203.08:00:32.76#ibcon#flushed, iclass 24, count 0 2006.203.08:00:32.76#ibcon#about to write, iclass 24, count 0 2006.203.08:00:32.76#ibcon#wrote, iclass 24, count 0 2006.203.08:00:32.76#ibcon#about to read 3, iclass 24, count 0 2006.203.08:00:32.78#ibcon#read 3, iclass 24, count 0 2006.203.08:00:32.78#ibcon#about to read 4, iclass 24, count 0 2006.203.08:00:32.78#ibcon#read 4, iclass 24, count 0 2006.203.08:00:32.78#ibcon#about to read 5, iclass 24, count 0 2006.203.08:00:32.78#ibcon#read 5, iclass 24, count 0 2006.203.08:00:32.78#ibcon#about to read 6, iclass 24, count 0 2006.203.08:00:32.78#ibcon#read 6, iclass 24, count 0 2006.203.08:00:32.78#ibcon#end of sib2, iclass 24, count 0 2006.203.08:00:32.78#ibcon#*mode == 0, iclass 24, count 0 2006.203.08:00:32.78#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.203.08:00:32.78#ibcon#[27=USB\r\n] 2006.203.08:00:32.78#ibcon#*before write, iclass 24, count 0 2006.203.08:00:32.78#ibcon#enter sib2, iclass 24, count 0 2006.203.08:00:32.78#ibcon#flushed, iclass 24, count 0 2006.203.08:00:32.78#ibcon#about to write, iclass 24, count 0 2006.203.08:00:32.78#ibcon#wrote, iclass 24, count 0 2006.203.08:00:32.78#ibcon#about to read 3, iclass 24, count 0 2006.203.08:00:32.81#ibcon#read 3, iclass 24, count 0 2006.203.08:00:32.81#ibcon#about to read 4, iclass 24, count 0 2006.203.08:00:32.81#ibcon#read 4, iclass 24, count 0 2006.203.08:00:32.81#ibcon#about to read 5, iclass 24, count 0 2006.203.08:00:32.81#ibcon#read 5, iclass 24, count 0 2006.203.08:00:32.81#ibcon#about to read 6, iclass 24, count 0 2006.203.08:00:32.81#ibcon#read 6, iclass 24, count 0 2006.203.08:00:32.81#ibcon#end of sib2, iclass 24, count 0 2006.203.08:00:32.81#ibcon#*after write, iclass 24, count 0 2006.203.08:00:32.81#ibcon#*before return 0, iclass 24, count 0 2006.203.08:00:32.81#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.203.08:00:32.81#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.203.08:00:32.81#ibcon#about to clear, iclass 24 cls_cnt 0 2006.203.08:00:32.81#ibcon#cleared, iclass 24 cls_cnt 0 2006.203.08:00:32.81$vc4f8/vblo=3,656.99 2006.203.08:00:32.81#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.203.08:00:32.81#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.203.08:00:32.81#ibcon#ireg 17 cls_cnt 0 2006.203.08:00:32.81#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.203.08:00:32.81#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.203.08:00:32.81#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.203.08:00:32.81#ibcon#enter wrdev, iclass 26, count 0 2006.203.08:00:32.81#ibcon#first serial, iclass 26, count 0 2006.203.08:00:32.81#ibcon#enter sib2, iclass 26, count 0 2006.203.08:00:32.81#ibcon#flushed, iclass 26, count 0 2006.203.08:00:32.81#ibcon#about to write, iclass 26, count 0 2006.203.08:00:32.81#ibcon#wrote, iclass 26, count 0 2006.203.08:00:32.81#ibcon#about to read 3, iclass 26, count 0 2006.203.08:00:32.83#ibcon#read 3, iclass 26, count 0 2006.203.08:00:32.83#ibcon#about to read 4, iclass 26, count 0 2006.203.08:00:32.83#ibcon#read 4, iclass 26, count 0 2006.203.08:00:32.83#ibcon#about to read 5, iclass 26, count 0 2006.203.08:00:32.83#ibcon#read 5, iclass 26, count 0 2006.203.08:00:32.83#ibcon#about to read 6, iclass 26, count 0 2006.203.08:00:32.83#ibcon#read 6, iclass 26, count 0 2006.203.08:00:32.83#ibcon#end of sib2, iclass 26, count 0 2006.203.08:00:32.83#ibcon#*mode == 0, iclass 26, count 0 2006.203.08:00:32.83#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.203.08:00:32.83#ibcon#[28=FRQ=03,656.99\r\n] 2006.203.08:00:32.83#ibcon#*before write, iclass 26, count 0 2006.203.08:00:32.83#ibcon#enter sib2, iclass 26, count 0 2006.203.08:00:32.83#ibcon#flushed, iclass 26, count 0 2006.203.08:00:32.83#ibcon#about to write, iclass 26, count 0 2006.203.08:00:32.83#ibcon#wrote, iclass 26, count 0 2006.203.08:00:32.83#ibcon#about to read 3, iclass 26, count 0 2006.203.08:00:32.87#ibcon#read 3, iclass 26, count 0 2006.203.08:00:32.87#ibcon#about to read 4, iclass 26, count 0 2006.203.08:00:32.87#ibcon#read 4, iclass 26, count 0 2006.203.08:00:32.87#ibcon#about to read 5, iclass 26, count 0 2006.203.08:00:32.87#ibcon#read 5, iclass 26, count 0 2006.203.08:00:32.87#ibcon#about to read 6, iclass 26, count 0 2006.203.08:00:32.87#ibcon#read 6, iclass 26, count 0 2006.203.08:00:32.87#ibcon#end of sib2, iclass 26, count 0 2006.203.08:00:32.87#ibcon#*after write, iclass 26, count 0 2006.203.08:00:32.87#ibcon#*before return 0, iclass 26, count 0 2006.203.08:00:32.87#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.203.08:00:32.87#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.203.08:00:32.87#ibcon#about to clear, iclass 26 cls_cnt 0 2006.203.08:00:32.87#ibcon#cleared, iclass 26 cls_cnt 0 2006.203.08:00:32.87$vc4f8/vb=3,4 2006.203.08:00:32.87#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.203.08:00:32.87#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.203.08:00:32.87#ibcon#ireg 11 cls_cnt 2 2006.203.08:00:32.87#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.203.08:00:32.93#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.203.08:00:32.93#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.203.08:00:32.93#ibcon#enter wrdev, iclass 28, count 2 2006.203.08:00:32.93#ibcon#first serial, iclass 28, count 2 2006.203.08:00:32.93#ibcon#enter sib2, iclass 28, count 2 2006.203.08:00:32.93#ibcon#flushed, iclass 28, count 2 2006.203.08:00:32.93#ibcon#about to write, iclass 28, count 2 2006.203.08:00:32.93#ibcon#wrote, iclass 28, count 2 2006.203.08:00:32.93#ibcon#about to read 3, iclass 28, count 2 2006.203.08:00:32.95#ibcon#read 3, iclass 28, count 2 2006.203.08:00:32.95#ibcon#about to read 4, iclass 28, count 2 2006.203.08:00:32.95#ibcon#read 4, iclass 28, count 2 2006.203.08:00:32.95#ibcon#about to read 5, iclass 28, count 2 2006.203.08:00:32.95#ibcon#read 5, iclass 28, count 2 2006.203.08:00:32.95#ibcon#about to read 6, iclass 28, count 2 2006.203.08:00:32.95#ibcon#read 6, iclass 28, count 2 2006.203.08:00:32.95#ibcon#end of sib2, iclass 28, count 2 2006.203.08:00:32.95#ibcon#*mode == 0, iclass 28, count 2 2006.203.08:00:32.95#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.203.08:00:32.95#ibcon#[27=AT03-04\r\n] 2006.203.08:00:32.95#ibcon#*before write, iclass 28, count 2 2006.203.08:00:32.95#ibcon#enter sib2, iclass 28, count 2 2006.203.08:00:32.95#ibcon#flushed, iclass 28, count 2 2006.203.08:00:32.95#ibcon#about to write, iclass 28, count 2 2006.203.08:00:32.95#ibcon#wrote, iclass 28, count 2 2006.203.08:00:32.95#ibcon#about to read 3, iclass 28, count 2 2006.203.08:00:32.96#abcon#<5=/05 1.9 3.2 23.72 991001.1\r\n> 2006.203.08:00:32.98#abcon#{5=INTERFACE CLEAR} 2006.203.08:00:32.98#ibcon#read 3, iclass 28, count 2 2006.203.08:00:32.98#ibcon#about to read 4, iclass 28, count 2 2006.203.08:00:32.98#ibcon#read 4, iclass 28, count 2 2006.203.08:00:32.98#ibcon#about to read 5, iclass 28, count 2 2006.203.08:00:32.98#ibcon#read 5, iclass 28, count 2 2006.203.08:00:32.98#ibcon#about to read 6, iclass 28, count 2 2006.203.08:00:32.98#ibcon#read 6, iclass 28, count 2 2006.203.08:00:32.98#ibcon#end of sib2, iclass 28, count 2 2006.203.08:00:32.98#ibcon#*after write, iclass 28, count 2 2006.203.08:00:32.98#ibcon#*before return 0, iclass 28, count 2 2006.203.08:00:32.98#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.203.08:00:32.98#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.203.08:00:32.98#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.203.08:00:32.98#ibcon#ireg 7 cls_cnt 0 2006.203.08:00:32.98#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.203.08:00:33.04#abcon#[5=S1D000X0/0*\r\n] 2006.203.08:00:33.10#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.203.08:00:33.10#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.203.08:00:33.10#ibcon#enter wrdev, iclass 28, count 0 2006.203.08:00:33.10#ibcon#first serial, iclass 28, count 0 2006.203.08:00:33.10#ibcon#enter sib2, iclass 28, count 0 2006.203.08:00:33.10#ibcon#flushed, iclass 28, count 0 2006.203.08:00:33.10#ibcon#about to write, iclass 28, count 0 2006.203.08:00:33.10#ibcon#wrote, iclass 28, count 0 2006.203.08:00:33.10#ibcon#about to read 3, iclass 28, count 0 2006.203.08:00:33.12#ibcon#read 3, iclass 28, count 0 2006.203.08:00:33.12#ibcon#about to read 4, iclass 28, count 0 2006.203.08:00:33.12#ibcon#read 4, iclass 28, count 0 2006.203.08:00:33.12#ibcon#about to read 5, iclass 28, count 0 2006.203.08:00:33.12#ibcon#read 5, iclass 28, count 0 2006.203.08:00:33.12#ibcon#about to read 6, iclass 28, count 0 2006.203.08:00:33.12#ibcon#read 6, iclass 28, count 0 2006.203.08:00:33.12#ibcon#end of sib2, iclass 28, count 0 2006.203.08:00:33.12#ibcon#*mode == 0, iclass 28, count 0 2006.203.08:00:33.12#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.203.08:00:33.12#ibcon#[27=USB\r\n] 2006.203.08:00:33.12#ibcon#*before write, iclass 28, count 0 2006.203.08:00:33.12#ibcon#enter sib2, iclass 28, count 0 2006.203.08:00:33.12#ibcon#flushed, iclass 28, count 0 2006.203.08:00:33.12#ibcon#about to write, iclass 28, count 0 2006.203.08:00:33.12#ibcon#wrote, iclass 28, count 0 2006.203.08:00:33.12#ibcon#about to read 3, iclass 28, count 0 2006.203.08:00:33.15#ibcon#read 3, iclass 28, count 0 2006.203.08:00:33.15#ibcon#about to read 4, iclass 28, count 0 2006.203.08:00:33.15#ibcon#read 4, iclass 28, count 0 2006.203.08:00:33.15#ibcon#about to read 5, iclass 28, count 0 2006.203.08:00:33.15#ibcon#read 5, iclass 28, count 0 2006.203.08:00:33.15#ibcon#about to read 6, iclass 28, count 0 2006.203.08:00:33.15#ibcon#read 6, iclass 28, count 0 2006.203.08:00:33.15#ibcon#end of sib2, iclass 28, count 0 2006.203.08:00:33.15#ibcon#*after write, iclass 28, count 0 2006.203.08:00:33.15#ibcon#*before return 0, iclass 28, count 0 2006.203.08:00:33.15#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.203.08:00:33.15#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.203.08:00:33.15#ibcon#about to clear, iclass 28 cls_cnt 0 2006.203.08:00:33.15#ibcon#cleared, iclass 28 cls_cnt 0 2006.203.08:00:33.15$vc4f8/vblo=4,712.99 2006.203.08:00:33.15#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.203.08:00:33.15#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.203.08:00:33.15#ibcon#ireg 17 cls_cnt 0 2006.203.08:00:33.15#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.203.08:00:33.15#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.203.08:00:33.15#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.203.08:00:33.15#ibcon#enter wrdev, iclass 34, count 0 2006.203.08:00:33.15#ibcon#first serial, iclass 34, count 0 2006.203.08:00:33.15#ibcon#enter sib2, iclass 34, count 0 2006.203.08:00:33.15#ibcon#flushed, iclass 34, count 0 2006.203.08:00:33.15#ibcon#about to write, iclass 34, count 0 2006.203.08:00:33.15#ibcon#wrote, iclass 34, count 0 2006.203.08:00:33.15#ibcon#about to read 3, iclass 34, count 0 2006.203.08:00:33.17#ibcon#read 3, iclass 34, count 0 2006.203.08:00:33.17#ibcon#about to read 4, iclass 34, count 0 2006.203.08:00:33.17#ibcon#read 4, iclass 34, count 0 2006.203.08:00:33.17#ibcon#about to read 5, iclass 34, count 0 2006.203.08:00:33.17#ibcon#read 5, iclass 34, count 0 2006.203.08:00:33.17#ibcon#about to read 6, iclass 34, count 0 2006.203.08:00:33.17#ibcon#read 6, iclass 34, count 0 2006.203.08:00:33.17#ibcon#end of sib2, iclass 34, count 0 2006.203.08:00:33.17#ibcon#*mode == 0, iclass 34, count 0 2006.203.08:00:33.17#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.203.08:00:33.17#ibcon#[28=FRQ=04,712.99\r\n] 2006.203.08:00:33.17#ibcon#*before write, iclass 34, count 0 2006.203.08:00:33.17#ibcon#enter sib2, iclass 34, count 0 2006.203.08:00:33.17#ibcon#flushed, iclass 34, count 0 2006.203.08:00:33.17#ibcon#about to write, iclass 34, count 0 2006.203.08:00:33.17#ibcon#wrote, iclass 34, count 0 2006.203.08:00:33.17#ibcon#about to read 3, iclass 34, count 0 2006.203.08:00:33.21#ibcon#read 3, iclass 34, count 0 2006.203.08:00:33.21#ibcon#about to read 4, iclass 34, count 0 2006.203.08:00:33.21#ibcon#read 4, iclass 34, count 0 2006.203.08:00:33.21#ibcon#about to read 5, iclass 34, count 0 2006.203.08:00:33.21#ibcon#read 5, iclass 34, count 0 2006.203.08:00:33.21#ibcon#about to read 6, iclass 34, count 0 2006.203.08:00:33.21#ibcon#read 6, iclass 34, count 0 2006.203.08:00:33.21#ibcon#end of sib2, iclass 34, count 0 2006.203.08:00:33.21#ibcon#*after write, iclass 34, count 0 2006.203.08:00:33.21#ibcon#*before return 0, iclass 34, count 0 2006.203.08:00:33.21#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.203.08:00:33.21#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.203.08:00:33.21#ibcon#about to clear, iclass 34 cls_cnt 0 2006.203.08:00:33.21#ibcon#cleared, iclass 34 cls_cnt 0 2006.203.08:00:33.21$vc4f8/vb=4,4 2006.203.08:00:33.21#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.203.08:00:33.21#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.203.08:00:33.21#ibcon#ireg 11 cls_cnt 2 2006.203.08:00:33.21#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.203.08:00:33.27#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.203.08:00:33.27#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.203.08:00:33.27#ibcon#enter wrdev, iclass 36, count 2 2006.203.08:00:33.27#ibcon#first serial, iclass 36, count 2 2006.203.08:00:33.27#ibcon#enter sib2, iclass 36, count 2 2006.203.08:00:33.27#ibcon#flushed, iclass 36, count 2 2006.203.08:00:33.27#ibcon#about to write, iclass 36, count 2 2006.203.08:00:33.27#ibcon#wrote, iclass 36, count 2 2006.203.08:00:33.27#ibcon#about to read 3, iclass 36, count 2 2006.203.08:00:33.29#ibcon#read 3, iclass 36, count 2 2006.203.08:00:33.29#ibcon#about to read 4, iclass 36, count 2 2006.203.08:00:33.29#ibcon#read 4, iclass 36, count 2 2006.203.08:00:33.29#ibcon#about to read 5, iclass 36, count 2 2006.203.08:00:33.29#ibcon#read 5, iclass 36, count 2 2006.203.08:00:33.29#ibcon#about to read 6, iclass 36, count 2 2006.203.08:00:33.29#ibcon#read 6, iclass 36, count 2 2006.203.08:00:33.29#ibcon#end of sib2, iclass 36, count 2 2006.203.08:00:33.29#ibcon#*mode == 0, iclass 36, count 2 2006.203.08:00:33.29#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.203.08:00:33.29#ibcon#[27=AT04-04\r\n] 2006.203.08:00:33.29#ibcon#*before write, iclass 36, count 2 2006.203.08:00:33.29#ibcon#enter sib2, iclass 36, count 2 2006.203.08:00:33.29#ibcon#flushed, iclass 36, count 2 2006.203.08:00:33.29#ibcon#about to write, iclass 36, count 2 2006.203.08:00:33.29#ibcon#wrote, iclass 36, count 2 2006.203.08:00:33.29#ibcon#about to read 3, iclass 36, count 2 2006.203.08:00:33.32#ibcon#read 3, iclass 36, count 2 2006.203.08:00:33.32#ibcon#about to read 4, iclass 36, count 2 2006.203.08:00:33.32#ibcon#read 4, iclass 36, count 2 2006.203.08:00:33.32#ibcon#about to read 5, iclass 36, count 2 2006.203.08:00:33.32#ibcon#read 5, iclass 36, count 2 2006.203.08:00:33.32#ibcon#about to read 6, iclass 36, count 2 2006.203.08:00:33.32#ibcon#read 6, iclass 36, count 2 2006.203.08:00:33.32#ibcon#end of sib2, iclass 36, count 2 2006.203.08:00:33.32#ibcon#*after write, iclass 36, count 2 2006.203.08:00:33.32#ibcon#*before return 0, iclass 36, count 2 2006.203.08:00:33.32#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.203.08:00:33.32#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.203.08:00:33.32#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.203.08:00:33.32#ibcon#ireg 7 cls_cnt 0 2006.203.08:00:33.32#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.203.08:00:33.44#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.203.08:00:33.44#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.203.08:00:33.44#ibcon#enter wrdev, iclass 36, count 0 2006.203.08:00:33.44#ibcon#first serial, iclass 36, count 0 2006.203.08:00:33.44#ibcon#enter sib2, iclass 36, count 0 2006.203.08:00:33.44#ibcon#flushed, iclass 36, count 0 2006.203.08:00:33.44#ibcon#about to write, iclass 36, count 0 2006.203.08:00:33.44#ibcon#wrote, iclass 36, count 0 2006.203.08:00:33.44#ibcon#about to read 3, iclass 36, count 0 2006.203.08:00:33.46#ibcon#read 3, iclass 36, count 0 2006.203.08:00:33.46#ibcon#about to read 4, iclass 36, count 0 2006.203.08:00:33.46#ibcon#read 4, iclass 36, count 0 2006.203.08:00:33.46#ibcon#about to read 5, iclass 36, count 0 2006.203.08:00:33.46#ibcon#read 5, iclass 36, count 0 2006.203.08:00:33.46#ibcon#about to read 6, iclass 36, count 0 2006.203.08:00:33.46#ibcon#read 6, iclass 36, count 0 2006.203.08:00:33.46#ibcon#end of sib2, iclass 36, count 0 2006.203.08:00:33.46#ibcon#*mode == 0, iclass 36, count 0 2006.203.08:00:33.46#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.203.08:00:33.46#ibcon#[27=USB\r\n] 2006.203.08:00:33.46#ibcon#*before write, iclass 36, count 0 2006.203.08:00:33.46#ibcon#enter sib2, iclass 36, count 0 2006.203.08:00:33.46#ibcon#flushed, iclass 36, count 0 2006.203.08:00:33.46#ibcon#about to write, iclass 36, count 0 2006.203.08:00:33.46#ibcon#wrote, iclass 36, count 0 2006.203.08:00:33.46#ibcon#about to read 3, iclass 36, count 0 2006.203.08:00:33.49#ibcon#read 3, iclass 36, count 0 2006.203.08:00:33.49#ibcon#about to read 4, iclass 36, count 0 2006.203.08:00:33.49#ibcon#read 4, iclass 36, count 0 2006.203.08:00:33.49#ibcon#about to read 5, iclass 36, count 0 2006.203.08:00:33.49#ibcon#read 5, iclass 36, count 0 2006.203.08:00:33.49#ibcon#about to read 6, iclass 36, count 0 2006.203.08:00:33.49#ibcon#read 6, iclass 36, count 0 2006.203.08:00:33.49#ibcon#end of sib2, iclass 36, count 0 2006.203.08:00:33.49#ibcon#*after write, iclass 36, count 0 2006.203.08:00:33.49#ibcon#*before return 0, iclass 36, count 0 2006.203.08:00:33.49#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.203.08:00:33.49#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.203.08:00:33.49#ibcon#about to clear, iclass 36 cls_cnt 0 2006.203.08:00:33.49#ibcon#cleared, iclass 36 cls_cnt 0 2006.203.08:00:33.49$vc4f8/vblo=5,744.99 2006.203.08:00:33.49#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.203.08:00:33.49#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.203.08:00:33.49#ibcon#ireg 17 cls_cnt 0 2006.203.08:00:33.49#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.203.08:00:33.49#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.203.08:00:33.49#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.203.08:00:33.49#ibcon#enter wrdev, iclass 38, count 0 2006.203.08:00:33.49#ibcon#first serial, iclass 38, count 0 2006.203.08:00:33.49#ibcon#enter sib2, iclass 38, count 0 2006.203.08:00:33.49#ibcon#flushed, iclass 38, count 0 2006.203.08:00:33.49#ibcon#about to write, iclass 38, count 0 2006.203.08:00:33.49#ibcon#wrote, iclass 38, count 0 2006.203.08:00:33.49#ibcon#about to read 3, iclass 38, count 0 2006.203.08:00:33.51#ibcon#read 3, iclass 38, count 0 2006.203.08:00:33.51#ibcon#about to read 4, iclass 38, count 0 2006.203.08:00:33.51#ibcon#read 4, iclass 38, count 0 2006.203.08:00:33.51#ibcon#about to read 5, iclass 38, count 0 2006.203.08:00:33.51#ibcon#read 5, iclass 38, count 0 2006.203.08:00:33.51#ibcon#about to read 6, iclass 38, count 0 2006.203.08:00:33.51#ibcon#read 6, iclass 38, count 0 2006.203.08:00:33.51#ibcon#end of sib2, iclass 38, count 0 2006.203.08:00:33.51#ibcon#*mode == 0, iclass 38, count 0 2006.203.08:00:33.51#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.203.08:00:33.51#ibcon#[28=FRQ=05,744.99\r\n] 2006.203.08:00:33.51#ibcon#*before write, iclass 38, count 0 2006.203.08:00:33.51#ibcon#enter sib2, iclass 38, count 0 2006.203.08:00:33.51#ibcon#flushed, iclass 38, count 0 2006.203.08:00:33.51#ibcon#about to write, iclass 38, count 0 2006.203.08:00:33.51#ibcon#wrote, iclass 38, count 0 2006.203.08:00:33.51#ibcon#about to read 3, iclass 38, count 0 2006.203.08:00:33.55#ibcon#read 3, iclass 38, count 0 2006.203.08:00:33.55#ibcon#about to read 4, iclass 38, count 0 2006.203.08:00:33.55#ibcon#read 4, iclass 38, count 0 2006.203.08:00:33.55#ibcon#about to read 5, iclass 38, count 0 2006.203.08:00:33.55#ibcon#read 5, iclass 38, count 0 2006.203.08:00:33.55#ibcon#about to read 6, iclass 38, count 0 2006.203.08:00:33.55#ibcon#read 6, iclass 38, count 0 2006.203.08:00:33.55#ibcon#end of sib2, iclass 38, count 0 2006.203.08:00:33.55#ibcon#*after write, iclass 38, count 0 2006.203.08:00:33.55#ibcon#*before return 0, iclass 38, count 0 2006.203.08:00:33.55#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.203.08:00:33.55#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.203.08:00:33.55#ibcon#about to clear, iclass 38 cls_cnt 0 2006.203.08:00:33.55#ibcon#cleared, iclass 38 cls_cnt 0 2006.203.08:00:33.55$vc4f8/vb=5,3 2006.203.08:00:33.55#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.203.08:00:33.55#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.203.08:00:33.55#ibcon#ireg 11 cls_cnt 2 2006.203.08:00:33.55#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.203.08:00:33.61#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.203.08:00:33.61#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.203.08:00:33.61#ibcon#enter wrdev, iclass 40, count 2 2006.203.08:00:33.61#ibcon#first serial, iclass 40, count 2 2006.203.08:00:33.61#ibcon#enter sib2, iclass 40, count 2 2006.203.08:00:33.61#ibcon#flushed, iclass 40, count 2 2006.203.08:00:33.61#ibcon#about to write, iclass 40, count 2 2006.203.08:00:33.61#ibcon#wrote, iclass 40, count 2 2006.203.08:00:33.61#ibcon#about to read 3, iclass 40, count 2 2006.203.08:00:33.63#ibcon#read 3, iclass 40, count 2 2006.203.08:00:33.63#ibcon#about to read 4, iclass 40, count 2 2006.203.08:00:33.63#ibcon#read 4, iclass 40, count 2 2006.203.08:00:33.63#ibcon#about to read 5, iclass 40, count 2 2006.203.08:00:33.63#ibcon#read 5, iclass 40, count 2 2006.203.08:00:33.63#ibcon#about to read 6, iclass 40, count 2 2006.203.08:00:33.63#ibcon#read 6, iclass 40, count 2 2006.203.08:00:33.63#ibcon#end of sib2, iclass 40, count 2 2006.203.08:00:33.63#ibcon#*mode == 0, iclass 40, count 2 2006.203.08:00:33.63#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.203.08:00:33.63#ibcon#[27=AT05-03\r\n] 2006.203.08:00:33.63#ibcon#*before write, iclass 40, count 2 2006.203.08:00:33.63#ibcon#enter sib2, iclass 40, count 2 2006.203.08:00:33.63#ibcon#flushed, iclass 40, count 2 2006.203.08:00:33.63#ibcon#about to write, iclass 40, count 2 2006.203.08:00:33.63#ibcon#wrote, iclass 40, count 2 2006.203.08:00:33.63#ibcon#about to read 3, iclass 40, count 2 2006.203.08:00:33.66#ibcon#read 3, iclass 40, count 2 2006.203.08:00:33.66#ibcon#about to read 4, iclass 40, count 2 2006.203.08:00:33.66#ibcon#read 4, iclass 40, count 2 2006.203.08:00:33.66#ibcon#about to read 5, iclass 40, count 2 2006.203.08:00:33.66#ibcon#read 5, iclass 40, count 2 2006.203.08:00:33.66#ibcon#about to read 6, iclass 40, count 2 2006.203.08:00:33.66#ibcon#read 6, iclass 40, count 2 2006.203.08:00:33.66#ibcon#end of sib2, iclass 40, count 2 2006.203.08:00:33.66#ibcon#*after write, iclass 40, count 2 2006.203.08:00:33.66#ibcon#*before return 0, iclass 40, count 2 2006.203.08:00:33.66#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.203.08:00:33.66#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.203.08:00:33.66#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.203.08:00:33.66#ibcon#ireg 7 cls_cnt 0 2006.203.08:00:33.66#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.203.08:00:33.78#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.203.08:00:33.78#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.203.08:00:33.78#ibcon#enter wrdev, iclass 40, count 0 2006.203.08:00:33.78#ibcon#first serial, iclass 40, count 0 2006.203.08:00:33.78#ibcon#enter sib2, iclass 40, count 0 2006.203.08:00:33.78#ibcon#flushed, iclass 40, count 0 2006.203.08:00:33.78#ibcon#about to write, iclass 40, count 0 2006.203.08:00:33.78#ibcon#wrote, iclass 40, count 0 2006.203.08:00:33.78#ibcon#about to read 3, iclass 40, count 0 2006.203.08:00:33.80#ibcon#read 3, iclass 40, count 0 2006.203.08:00:33.80#ibcon#about to read 4, iclass 40, count 0 2006.203.08:00:33.80#ibcon#read 4, iclass 40, count 0 2006.203.08:00:33.80#ibcon#about to read 5, iclass 40, count 0 2006.203.08:00:33.80#ibcon#read 5, iclass 40, count 0 2006.203.08:00:33.80#ibcon#about to read 6, iclass 40, count 0 2006.203.08:00:33.80#ibcon#read 6, iclass 40, count 0 2006.203.08:00:33.80#ibcon#end of sib2, iclass 40, count 0 2006.203.08:00:33.80#ibcon#*mode == 0, iclass 40, count 0 2006.203.08:00:33.80#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.203.08:00:33.80#ibcon#[27=USB\r\n] 2006.203.08:00:33.80#ibcon#*before write, iclass 40, count 0 2006.203.08:00:33.80#ibcon#enter sib2, iclass 40, count 0 2006.203.08:00:33.80#ibcon#flushed, iclass 40, count 0 2006.203.08:00:33.80#ibcon#about to write, iclass 40, count 0 2006.203.08:00:33.80#ibcon#wrote, iclass 40, count 0 2006.203.08:00:33.80#ibcon#about to read 3, iclass 40, count 0 2006.203.08:00:33.83#ibcon#read 3, iclass 40, count 0 2006.203.08:00:33.83#ibcon#about to read 4, iclass 40, count 0 2006.203.08:00:33.83#ibcon#read 4, iclass 40, count 0 2006.203.08:00:33.83#ibcon#about to read 5, iclass 40, count 0 2006.203.08:00:33.83#ibcon#read 5, iclass 40, count 0 2006.203.08:00:33.83#ibcon#about to read 6, iclass 40, count 0 2006.203.08:00:33.83#ibcon#read 6, iclass 40, count 0 2006.203.08:00:33.83#ibcon#end of sib2, iclass 40, count 0 2006.203.08:00:33.83#ibcon#*after write, iclass 40, count 0 2006.203.08:00:33.83#ibcon#*before return 0, iclass 40, count 0 2006.203.08:00:33.83#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.203.08:00:33.83#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.203.08:00:33.83#ibcon#about to clear, iclass 40 cls_cnt 0 2006.203.08:00:33.83#ibcon#cleared, iclass 40 cls_cnt 0 2006.203.08:00:33.83$vc4f8/vblo=6,752.99 2006.203.08:00:33.83#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.203.08:00:33.83#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.203.08:00:33.83#ibcon#ireg 17 cls_cnt 0 2006.203.08:00:33.83#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.203.08:00:33.83#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.203.08:00:33.83#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.203.08:00:33.83#ibcon#enter wrdev, iclass 4, count 0 2006.203.08:00:33.83#ibcon#first serial, iclass 4, count 0 2006.203.08:00:33.83#ibcon#enter sib2, iclass 4, count 0 2006.203.08:00:33.83#ibcon#flushed, iclass 4, count 0 2006.203.08:00:33.83#ibcon#about to write, iclass 4, count 0 2006.203.08:00:33.83#ibcon#wrote, iclass 4, count 0 2006.203.08:00:33.83#ibcon#about to read 3, iclass 4, count 0 2006.203.08:00:33.85#ibcon#read 3, iclass 4, count 0 2006.203.08:00:33.85#ibcon#about to read 4, iclass 4, count 0 2006.203.08:00:33.85#ibcon#read 4, iclass 4, count 0 2006.203.08:00:33.85#ibcon#about to read 5, iclass 4, count 0 2006.203.08:00:33.85#ibcon#read 5, iclass 4, count 0 2006.203.08:00:33.85#ibcon#about to read 6, iclass 4, count 0 2006.203.08:00:33.85#ibcon#read 6, iclass 4, count 0 2006.203.08:00:33.85#ibcon#end of sib2, iclass 4, count 0 2006.203.08:00:33.85#ibcon#*mode == 0, iclass 4, count 0 2006.203.08:00:33.85#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.203.08:00:33.85#ibcon#[28=FRQ=06,752.99\r\n] 2006.203.08:00:33.85#ibcon#*before write, iclass 4, count 0 2006.203.08:00:33.85#ibcon#enter sib2, iclass 4, count 0 2006.203.08:00:33.85#ibcon#flushed, iclass 4, count 0 2006.203.08:00:33.85#ibcon#about to write, iclass 4, count 0 2006.203.08:00:33.85#ibcon#wrote, iclass 4, count 0 2006.203.08:00:33.85#ibcon#about to read 3, iclass 4, count 0 2006.203.08:00:33.89#ibcon#read 3, iclass 4, count 0 2006.203.08:00:33.89#ibcon#about to read 4, iclass 4, count 0 2006.203.08:00:33.89#ibcon#read 4, iclass 4, count 0 2006.203.08:00:33.89#ibcon#about to read 5, iclass 4, count 0 2006.203.08:00:33.89#ibcon#read 5, iclass 4, count 0 2006.203.08:00:33.89#ibcon#about to read 6, iclass 4, count 0 2006.203.08:00:33.89#ibcon#read 6, iclass 4, count 0 2006.203.08:00:33.89#ibcon#end of sib2, iclass 4, count 0 2006.203.08:00:33.89#ibcon#*after write, iclass 4, count 0 2006.203.08:00:33.89#ibcon#*before return 0, iclass 4, count 0 2006.203.08:00:33.89#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.203.08:00:33.89#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.203.08:00:33.89#ibcon#about to clear, iclass 4 cls_cnt 0 2006.203.08:00:33.89#ibcon#cleared, iclass 4 cls_cnt 0 2006.203.08:00:33.89$vc4f8/vb=6,4 2006.203.08:00:33.89#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.203.08:00:33.89#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.203.08:00:33.89#ibcon#ireg 11 cls_cnt 2 2006.203.08:00:33.89#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.203.08:00:33.95#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.203.08:00:33.95#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.203.08:00:33.95#ibcon#enter wrdev, iclass 6, count 2 2006.203.08:00:33.95#ibcon#first serial, iclass 6, count 2 2006.203.08:00:33.95#ibcon#enter sib2, iclass 6, count 2 2006.203.08:00:33.95#ibcon#flushed, iclass 6, count 2 2006.203.08:00:33.95#ibcon#about to write, iclass 6, count 2 2006.203.08:00:33.95#ibcon#wrote, iclass 6, count 2 2006.203.08:00:33.95#ibcon#about to read 3, iclass 6, count 2 2006.203.08:00:33.97#ibcon#read 3, iclass 6, count 2 2006.203.08:00:33.97#ibcon#about to read 4, iclass 6, count 2 2006.203.08:00:33.97#ibcon#read 4, iclass 6, count 2 2006.203.08:00:33.97#ibcon#about to read 5, iclass 6, count 2 2006.203.08:00:33.97#ibcon#read 5, iclass 6, count 2 2006.203.08:00:33.97#ibcon#about to read 6, iclass 6, count 2 2006.203.08:00:33.97#ibcon#read 6, iclass 6, count 2 2006.203.08:00:33.97#ibcon#end of sib2, iclass 6, count 2 2006.203.08:00:33.97#ibcon#*mode == 0, iclass 6, count 2 2006.203.08:00:33.97#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.203.08:00:33.97#ibcon#[27=AT06-04\r\n] 2006.203.08:00:33.97#ibcon#*before write, iclass 6, count 2 2006.203.08:00:33.97#ibcon#enter sib2, iclass 6, count 2 2006.203.08:00:33.97#ibcon#flushed, iclass 6, count 2 2006.203.08:00:33.97#ibcon#about to write, iclass 6, count 2 2006.203.08:00:33.97#ibcon#wrote, iclass 6, count 2 2006.203.08:00:33.97#ibcon#about to read 3, iclass 6, count 2 2006.203.08:00:34.00#ibcon#read 3, iclass 6, count 2 2006.203.08:00:34.00#ibcon#about to read 4, iclass 6, count 2 2006.203.08:00:34.00#ibcon#read 4, iclass 6, count 2 2006.203.08:00:34.00#ibcon#about to read 5, iclass 6, count 2 2006.203.08:00:34.00#ibcon#read 5, iclass 6, count 2 2006.203.08:00:34.00#ibcon#about to read 6, iclass 6, count 2 2006.203.08:00:34.00#ibcon#read 6, iclass 6, count 2 2006.203.08:00:34.00#ibcon#end of sib2, iclass 6, count 2 2006.203.08:00:34.00#ibcon#*after write, iclass 6, count 2 2006.203.08:00:34.00#ibcon#*before return 0, iclass 6, count 2 2006.203.08:00:34.00#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.203.08:00:34.00#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.203.08:00:34.00#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.203.08:00:34.00#ibcon#ireg 7 cls_cnt 0 2006.203.08:00:34.00#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.203.08:00:34.12#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.203.08:00:34.12#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.203.08:00:34.12#ibcon#enter wrdev, iclass 6, count 0 2006.203.08:00:34.12#ibcon#first serial, iclass 6, count 0 2006.203.08:00:34.12#ibcon#enter sib2, iclass 6, count 0 2006.203.08:00:34.12#ibcon#flushed, iclass 6, count 0 2006.203.08:00:34.12#ibcon#about to write, iclass 6, count 0 2006.203.08:00:34.12#ibcon#wrote, iclass 6, count 0 2006.203.08:00:34.12#ibcon#about to read 3, iclass 6, count 0 2006.203.08:00:34.14#ibcon#read 3, iclass 6, count 0 2006.203.08:00:34.14#ibcon#about to read 4, iclass 6, count 0 2006.203.08:00:34.14#ibcon#read 4, iclass 6, count 0 2006.203.08:00:34.14#ibcon#about to read 5, iclass 6, count 0 2006.203.08:00:34.14#ibcon#read 5, iclass 6, count 0 2006.203.08:00:34.14#ibcon#about to read 6, iclass 6, count 0 2006.203.08:00:34.14#ibcon#read 6, iclass 6, count 0 2006.203.08:00:34.14#ibcon#end of sib2, iclass 6, count 0 2006.203.08:00:34.14#ibcon#*mode == 0, iclass 6, count 0 2006.203.08:00:34.14#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.203.08:00:34.14#ibcon#[27=USB\r\n] 2006.203.08:00:34.14#ibcon#*before write, iclass 6, count 0 2006.203.08:00:34.14#ibcon#enter sib2, iclass 6, count 0 2006.203.08:00:34.14#ibcon#flushed, iclass 6, count 0 2006.203.08:00:34.14#ibcon#about to write, iclass 6, count 0 2006.203.08:00:34.14#ibcon#wrote, iclass 6, count 0 2006.203.08:00:34.14#ibcon#about to read 3, iclass 6, count 0 2006.203.08:00:34.17#ibcon#read 3, iclass 6, count 0 2006.203.08:00:34.17#ibcon#about to read 4, iclass 6, count 0 2006.203.08:00:34.17#ibcon#read 4, iclass 6, count 0 2006.203.08:00:34.17#ibcon#about to read 5, iclass 6, count 0 2006.203.08:00:34.17#ibcon#read 5, iclass 6, count 0 2006.203.08:00:34.17#ibcon#about to read 6, iclass 6, count 0 2006.203.08:00:34.17#ibcon#read 6, iclass 6, count 0 2006.203.08:00:34.17#ibcon#end of sib2, iclass 6, count 0 2006.203.08:00:34.17#ibcon#*after write, iclass 6, count 0 2006.203.08:00:34.17#ibcon#*before return 0, iclass 6, count 0 2006.203.08:00:34.17#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.203.08:00:34.17#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.203.08:00:34.17#ibcon#about to clear, iclass 6 cls_cnt 0 2006.203.08:00:34.17#ibcon#cleared, iclass 6 cls_cnt 0 2006.203.08:00:34.17$vc4f8/vabw=wide 2006.203.08:00:34.17#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.203.08:00:34.17#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.203.08:00:34.17#ibcon#ireg 8 cls_cnt 0 2006.203.08:00:34.17#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.203.08:00:34.17#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.203.08:00:34.17#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.203.08:00:34.17#ibcon#enter wrdev, iclass 10, count 0 2006.203.08:00:34.17#ibcon#first serial, iclass 10, count 0 2006.203.08:00:34.17#ibcon#enter sib2, iclass 10, count 0 2006.203.08:00:34.17#ibcon#flushed, iclass 10, count 0 2006.203.08:00:34.17#ibcon#about to write, iclass 10, count 0 2006.203.08:00:34.17#ibcon#wrote, iclass 10, count 0 2006.203.08:00:34.17#ibcon#about to read 3, iclass 10, count 0 2006.203.08:00:34.19#ibcon#read 3, iclass 10, count 0 2006.203.08:00:34.19#ibcon#about to read 4, iclass 10, count 0 2006.203.08:00:34.19#ibcon#read 4, iclass 10, count 0 2006.203.08:00:34.19#ibcon#about to read 5, iclass 10, count 0 2006.203.08:00:34.19#ibcon#read 5, iclass 10, count 0 2006.203.08:00:34.19#ibcon#about to read 6, iclass 10, count 0 2006.203.08:00:34.19#ibcon#read 6, iclass 10, count 0 2006.203.08:00:34.19#ibcon#end of sib2, iclass 10, count 0 2006.203.08:00:34.19#ibcon#*mode == 0, iclass 10, count 0 2006.203.08:00:34.19#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.203.08:00:34.19#ibcon#[25=BW32\r\n] 2006.203.08:00:34.19#ibcon#*before write, iclass 10, count 0 2006.203.08:00:34.19#ibcon#enter sib2, iclass 10, count 0 2006.203.08:00:34.19#ibcon#flushed, iclass 10, count 0 2006.203.08:00:34.19#ibcon#about to write, iclass 10, count 0 2006.203.08:00:34.19#ibcon#wrote, iclass 10, count 0 2006.203.08:00:34.19#ibcon#about to read 3, iclass 10, count 0 2006.203.08:00:34.22#ibcon#read 3, iclass 10, count 0 2006.203.08:00:34.22#ibcon#about to read 4, iclass 10, count 0 2006.203.08:00:34.22#ibcon#read 4, iclass 10, count 0 2006.203.08:00:34.22#ibcon#about to read 5, iclass 10, count 0 2006.203.08:00:34.22#ibcon#read 5, iclass 10, count 0 2006.203.08:00:34.22#ibcon#about to read 6, iclass 10, count 0 2006.203.08:00:34.22#ibcon#read 6, iclass 10, count 0 2006.203.08:00:34.22#ibcon#end of sib2, iclass 10, count 0 2006.203.08:00:34.22#ibcon#*after write, iclass 10, count 0 2006.203.08:00:34.22#ibcon#*before return 0, iclass 10, count 0 2006.203.08:00:34.22#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.203.08:00:34.22#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.203.08:00:34.22#ibcon#about to clear, iclass 10 cls_cnt 0 2006.203.08:00:34.22#ibcon#cleared, iclass 10 cls_cnt 0 2006.203.08:00:34.22$vc4f8/vbbw=wide 2006.203.08:00:34.22#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.203.08:00:34.22#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.203.08:00:34.22#ibcon#ireg 8 cls_cnt 0 2006.203.08:00:34.22#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.203.08:00:34.29#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.203.08:00:34.29#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.203.08:00:34.29#ibcon#enter wrdev, iclass 12, count 0 2006.203.08:00:34.29#ibcon#first serial, iclass 12, count 0 2006.203.08:00:34.29#ibcon#enter sib2, iclass 12, count 0 2006.203.08:00:34.29#ibcon#flushed, iclass 12, count 0 2006.203.08:00:34.29#ibcon#about to write, iclass 12, count 0 2006.203.08:00:34.29#ibcon#wrote, iclass 12, count 0 2006.203.08:00:34.29#ibcon#about to read 3, iclass 12, count 0 2006.203.08:00:34.31#ibcon#read 3, iclass 12, count 0 2006.203.08:00:34.31#ibcon#about to read 4, iclass 12, count 0 2006.203.08:00:34.31#ibcon#read 4, iclass 12, count 0 2006.203.08:00:34.31#ibcon#about to read 5, iclass 12, count 0 2006.203.08:00:34.31#ibcon#read 5, iclass 12, count 0 2006.203.08:00:34.31#ibcon#about to read 6, iclass 12, count 0 2006.203.08:00:34.31#ibcon#read 6, iclass 12, count 0 2006.203.08:00:34.31#ibcon#end of sib2, iclass 12, count 0 2006.203.08:00:34.31#ibcon#*mode == 0, iclass 12, count 0 2006.203.08:00:34.31#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.203.08:00:34.31#ibcon#[27=BW32\r\n] 2006.203.08:00:34.31#ibcon#*before write, iclass 12, count 0 2006.203.08:00:34.31#ibcon#enter sib2, iclass 12, count 0 2006.203.08:00:34.31#ibcon#flushed, iclass 12, count 0 2006.203.08:00:34.31#ibcon#about to write, iclass 12, count 0 2006.203.08:00:34.31#ibcon#wrote, iclass 12, count 0 2006.203.08:00:34.31#ibcon#about to read 3, iclass 12, count 0 2006.203.08:00:34.34#ibcon#read 3, iclass 12, count 0 2006.203.08:00:34.34#ibcon#about to read 4, iclass 12, count 0 2006.203.08:00:34.34#ibcon#read 4, iclass 12, count 0 2006.203.08:00:34.34#ibcon#about to read 5, iclass 12, count 0 2006.203.08:00:34.34#ibcon#read 5, iclass 12, count 0 2006.203.08:00:34.34#ibcon#about to read 6, iclass 12, count 0 2006.203.08:00:34.34#ibcon#read 6, iclass 12, count 0 2006.203.08:00:34.34#ibcon#end of sib2, iclass 12, count 0 2006.203.08:00:34.34#ibcon#*after write, iclass 12, count 0 2006.203.08:00:34.34#ibcon#*before return 0, iclass 12, count 0 2006.203.08:00:34.34#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.203.08:00:34.34#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.203.08:00:34.34#ibcon#about to clear, iclass 12 cls_cnt 0 2006.203.08:00:34.34#ibcon#cleared, iclass 12 cls_cnt 0 2006.203.08:00:34.34$4f8m12a/ifd4f 2006.203.08:00:34.34$ifd4f/lo= 2006.203.08:00:34.34$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.203.08:00:34.34$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.203.08:00:34.34$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.203.08:00:34.34$ifd4f/patch= 2006.203.08:00:34.34$ifd4f/patch=lo1,a1,a2,a3,a4 2006.203.08:00:34.34$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.203.08:00:34.34$ifd4f/patch=lo3,a5,a6,a7,a8 2006.203.08:00:34.34$4f8m12a/"form=m,16.000,1:2 2006.203.08:00:34.34$4f8m12a/"tpicd 2006.203.08:00:34.34$4f8m12a/echo=off 2006.203.08:00:34.34$4f8m12a/xlog=off 2006.203.08:00:34.34:!2006.203.08:01:00 2006.203.08:00:45.14#trakl#Source acquired 2006.203.08:00:45.14#flagr#flagr/antenna,acquired 2006.203.08:01:00.00:preob 2006.203.08:01:01.14/onsource/TRACKING 2006.203.08:01:01.14:!2006.203.08:01:10 2006.203.08:01:10.00:data_valid=on 2006.203.08:01:10.00:midob 2006.203.08:01:10.14/onsource/TRACKING 2006.203.08:01:10.14/wx/23.71,1001.1,99 2006.203.08:01:10.27/cable/+6.4607E-03 2006.203.08:01:11.36/va/01,08,usb,yes,29,31 2006.203.08:01:11.36/va/02,07,usb,yes,29,30 2006.203.08:01:11.36/va/03,08,usb,yes,22,22 2006.203.08:01:11.36/va/04,07,usb,yes,30,32 2006.203.08:01:11.36/va/05,07,usb,yes,32,34 2006.203.08:01:11.36/va/06,06,usb,yes,31,31 2006.203.08:01:11.36/va/07,07,usb,yes,28,28 2006.203.08:01:11.36/va/08,06,usb,yes,34,34 2006.203.08:01:11.59/valo/01,532.99,yes,locked 2006.203.08:01:11.59/valo/02,572.99,yes,locked 2006.203.08:01:11.59/valo/03,672.99,yes,locked 2006.203.08:01:11.59/valo/04,832.99,yes,locked 2006.203.08:01:11.59/valo/05,652.99,yes,locked 2006.203.08:01:11.59/valo/06,772.99,yes,locked 2006.203.08:01:11.59/valo/07,832.99,yes,locked 2006.203.08:01:11.59/valo/08,852.99,yes,locked 2006.203.08:01:12.68/vb/01,04,usb,yes,28,27 2006.203.08:01:12.68/vb/02,04,usb,yes,30,31 2006.203.08:01:12.68/vb/03,04,usb,yes,27,30 2006.203.08:01:12.68/vb/04,04,usb,yes,27,27 2006.203.08:01:12.68/vb/05,03,usb,yes,32,37 2006.203.08:01:12.68/vb/06,04,usb,yes,27,29 2006.203.08:01:12.68/vb/07,04,usb,yes,29,29 2006.203.08:01:12.68/vb/08,04,usb,yes,26,30 2006.203.08:01:12.92/vblo/01,632.99,yes,locked 2006.203.08:01:12.92/vblo/02,640.99,yes,locked 2006.203.08:01:12.92/vblo/03,656.99,yes,locked 2006.203.08:01:12.92/vblo/04,712.99,yes,locked 2006.203.08:01:12.92/vblo/05,744.99,yes,locked 2006.203.08:01:12.92/vblo/06,752.99,yes,locked 2006.203.08:01:12.92/vblo/07,734.99,yes,locked 2006.203.08:01:12.92/vblo/08,744.99,yes,locked 2006.203.08:01:13.07/vabw/8 2006.203.08:01:13.22/vbbw/8 2006.203.08:01:13.31/xfe/off,on,13.2 2006.203.08:01:13.69/ifatt/23,28,28,28 2006.203.08:01:14.08/fmout-gps/S +4.59E-07 2006.203.08:01:14.12:!2006.203.08:02:10 2006.203.08:02:10.00:data_valid=off 2006.203.08:02:10.00:postob 2006.203.08:02:10.19/cable/+6.4617E-03 2006.203.08:02:10.19/wx/23.71,1001.1,99 2006.203.08:02:11.07/fmout-gps/S +4.60E-07 2006.203.08:02:11.07:scan_name=203-0803,k06203,60 2006.203.08:02:11.07:source=0602+673,060752.67,672055.4,2000.0,ccw 2006.203.08:02:11.14#flagr#flagr/antenna,new-source 2006.203.08:02:12.14:checkk5 2006.203.08:02:12.57/chk_autoobs//k5ts1/ autoobs is running! 2006.203.08:02:12.97/chk_autoobs//k5ts2/ autoobs is running! 2006.203.08:02:13.40/chk_autoobs//k5ts3/ autoobs is running! 2006.203.08:02:13.82/chk_autoobs//k5ts4/ autoobs is running! 2006.203.08:02:14.37/chk_obsdata//k5ts1/T2030801??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.08:02:14.78/chk_obsdata//k5ts2/T2030801??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.08:02:15.20/chk_obsdata//k5ts3/T2030801??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.08:02:15.57/chk_obsdata//k5ts4/T2030801??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.08:02:16.45/k5log//k5ts1_log_newline 2006.203.08:02:17.20/k5log//k5ts2_log_newline 2006.203.08:02:17.97/k5log//k5ts3_log_newline 2006.203.08:02:18.73/k5log//k5ts4_log_newline 2006.203.08:02:18.75/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.203.08:02:18.75:4f8m12a=2 2006.203.08:02:18.75$4f8m12a/echo=on 2006.203.08:02:18.75$4f8m12a/pcalon 2006.203.08:02:18.75$pcalon/"no phase cal control is implemented here 2006.203.08:02:18.75$4f8m12a/"tpicd=stop 2006.203.08:02:18.75$4f8m12a/vc4f8 2006.203.08:02:18.75$vc4f8/valo=1,532.99 2006.203.08:02:18.76#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.203.08:02:18.76#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.203.08:02:18.76#ibcon#ireg 17 cls_cnt 0 2006.203.08:02:18.76#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.203.08:02:18.76#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.203.08:02:18.76#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.203.08:02:18.76#ibcon#enter wrdev, iclass 19, count 0 2006.203.08:02:18.76#ibcon#first serial, iclass 19, count 0 2006.203.08:02:18.76#ibcon#enter sib2, iclass 19, count 0 2006.203.08:02:18.76#ibcon#flushed, iclass 19, count 0 2006.203.08:02:18.76#ibcon#about to write, iclass 19, count 0 2006.203.08:02:18.76#ibcon#wrote, iclass 19, count 0 2006.203.08:02:18.76#ibcon#about to read 3, iclass 19, count 0 2006.203.08:02:18.80#ibcon#read 3, iclass 19, count 0 2006.203.08:02:18.80#ibcon#about to read 4, iclass 19, count 0 2006.203.08:02:18.80#ibcon#read 4, iclass 19, count 0 2006.203.08:02:18.80#ibcon#about to read 5, iclass 19, count 0 2006.203.08:02:18.80#ibcon#read 5, iclass 19, count 0 2006.203.08:02:18.80#ibcon#about to read 6, iclass 19, count 0 2006.203.08:02:18.80#ibcon#read 6, iclass 19, count 0 2006.203.08:02:18.80#ibcon#end of sib2, iclass 19, count 0 2006.203.08:02:18.80#ibcon#*mode == 0, iclass 19, count 0 2006.203.08:02:18.80#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.203.08:02:18.80#ibcon#[26=FRQ=01,532.99\r\n] 2006.203.08:02:18.80#ibcon#*before write, iclass 19, count 0 2006.203.08:02:18.80#ibcon#enter sib2, iclass 19, count 0 2006.203.08:02:18.80#ibcon#flushed, iclass 19, count 0 2006.203.08:02:18.80#ibcon#about to write, iclass 19, count 0 2006.203.08:02:18.80#ibcon#wrote, iclass 19, count 0 2006.203.08:02:18.80#ibcon#about to read 3, iclass 19, count 0 2006.203.08:02:18.85#ibcon#read 3, iclass 19, count 0 2006.203.08:02:18.85#ibcon#about to read 4, iclass 19, count 0 2006.203.08:02:18.85#ibcon#read 4, iclass 19, count 0 2006.203.08:02:18.85#ibcon#about to read 5, iclass 19, count 0 2006.203.08:02:18.85#ibcon#read 5, iclass 19, count 0 2006.203.08:02:18.85#ibcon#about to read 6, iclass 19, count 0 2006.203.08:02:18.85#ibcon#read 6, iclass 19, count 0 2006.203.08:02:18.85#ibcon#end of sib2, iclass 19, count 0 2006.203.08:02:18.85#ibcon#*after write, iclass 19, count 0 2006.203.08:02:18.85#ibcon#*before return 0, iclass 19, count 0 2006.203.08:02:18.85#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.203.08:02:18.85#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.203.08:02:18.85#ibcon#about to clear, iclass 19 cls_cnt 0 2006.203.08:02:18.85#ibcon#cleared, iclass 19 cls_cnt 0 2006.203.08:02:18.85$vc4f8/va=1,8 2006.203.08:02:18.85#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.203.08:02:18.85#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.203.08:02:18.85#ibcon#ireg 11 cls_cnt 2 2006.203.08:02:18.85#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.203.08:02:18.85#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.203.08:02:18.85#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.203.08:02:18.85#ibcon#enter wrdev, iclass 21, count 2 2006.203.08:02:18.85#ibcon#first serial, iclass 21, count 2 2006.203.08:02:18.85#ibcon#enter sib2, iclass 21, count 2 2006.203.08:02:18.85#ibcon#flushed, iclass 21, count 2 2006.203.08:02:18.85#ibcon#about to write, iclass 21, count 2 2006.203.08:02:18.85#ibcon#wrote, iclass 21, count 2 2006.203.08:02:18.85#ibcon#about to read 3, iclass 21, count 2 2006.203.08:02:18.87#ibcon#read 3, iclass 21, count 2 2006.203.08:02:18.87#ibcon#about to read 4, iclass 21, count 2 2006.203.08:02:18.87#ibcon#read 4, iclass 21, count 2 2006.203.08:02:18.87#ibcon#about to read 5, iclass 21, count 2 2006.203.08:02:18.87#ibcon#read 5, iclass 21, count 2 2006.203.08:02:18.87#ibcon#about to read 6, iclass 21, count 2 2006.203.08:02:18.87#ibcon#read 6, iclass 21, count 2 2006.203.08:02:18.87#ibcon#end of sib2, iclass 21, count 2 2006.203.08:02:18.87#ibcon#*mode == 0, iclass 21, count 2 2006.203.08:02:18.87#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.203.08:02:18.87#ibcon#[25=AT01-08\r\n] 2006.203.08:02:18.87#ibcon#*before write, iclass 21, count 2 2006.203.08:02:18.87#ibcon#enter sib2, iclass 21, count 2 2006.203.08:02:18.87#ibcon#flushed, iclass 21, count 2 2006.203.08:02:18.87#ibcon#about to write, iclass 21, count 2 2006.203.08:02:18.87#ibcon#wrote, iclass 21, count 2 2006.203.08:02:18.87#ibcon#about to read 3, iclass 21, count 2 2006.203.08:02:18.91#ibcon#read 3, iclass 21, count 2 2006.203.08:02:18.91#ibcon#about to read 4, iclass 21, count 2 2006.203.08:02:18.91#ibcon#read 4, iclass 21, count 2 2006.203.08:02:18.91#ibcon#about to read 5, iclass 21, count 2 2006.203.08:02:18.91#ibcon#read 5, iclass 21, count 2 2006.203.08:02:18.91#ibcon#about to read 6, iclass 21, count 2 2006.203.08:02:18.91#ibcon#read 6, iclass 21, count 2 2006.203.08:02:18.91#ibcon#end of sib2, iclass 21, count 2 2006.203.08:02:18.91#ibcon#*after write, iclass 21, count 2 2006.203.08:02:18.91#ibcon#*before return 0, iclass 21, count 2 2006.203.08:02:18.91#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.203.08:02:18.91#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.203.08:02:18.91#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.203.08:02:18.91#ibcon#ireg 7 cls_cnt 0 2006.203.08:02:18.91#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.203.08:02:19.03#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.203.08:02:19.03#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.203.08:02:19.03#ibcon#enter wrdev, iclass 21, count 0 2006.203.08:02:19.03#ibcon#first serial, iclass 21, count 0 2006.203.08:02:19.03#ibcon#enter sib2, iclass 21, count 0 2006.203.08:02:19.03#ibcon#flushed, iclass 21, count 0 2006.203.08:02:19.03#ibcon#about to write, iclass 21, count 0 2006.203.08:02:19.03#ibcon#wrote, iclass 21, count 0 2006.203.08:02:19.03#ibcon#about to read 3, iclass 21, count 0 2006.203.08:02:19.05#ibcon#read 3, iclass 21, count 0 2006.203.08:02:19.05#ibcon#about to read 4, iclass 21, count 0 2006.203.08:02:19.05#ibcon#read 4, iclass 21, count 0 2006.203.08:02:19.05#ibcon#about to read 5, iclass 21, count 0 2006.203.08:02:19.05#ibcon#read 5, iclass 21, count 0 2006.203.08:02:19.05#ibcon#about to read 6, iclass 21, count 0 2006.203.08:02:19.05#ibcon#read 6, iclass 21, count 0 2006.203.08:02:19.05#ibcon#end of sib2, iclass 21, count 0 2006.203.08:02:19.05#ibcon#*mode == 0, iclass 21, count 0 2006.203.08:02:19.05#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.203.08:02:19.05#ibcon#[25=USB\r\n] 2006.203.08:02:19.05#ibcon#*before write, iclass 21, count 0 2006.203.08:02:19.05#ibcon#enter sib2, iclass 21, count 0 2006.203.08:02:19.05#ibcon#flushed, iclass 21, count 0 2006.203.08:02:19.05#ibcon#about to write, iclass 21, count 0 2006.203.08:02:19.05#ibcon#wrote, iclass 21, count 0 2006.203.08:02:19.05#ibcon#about to read 3, iclass 21, count 0 2006.203.08:02:19.08#ibcon#read 3, iclass 21, count 0 2006.203.08:02:19.08#ibcon#about to read 4, iclass 21, count 0 2006.203.08:02:19.08#ibcon#read 4, iclass 21, count 0 2006.203.08:02:19.08#ibcon#about to read 5, iclass 21, count 0 2006.203.08:02:19.08#ibcon#read 5, iclass 21, count 0 2006.203.08:02:19.08#ibcon#about to read 6, iclass 21, count 0 2006.203.08:02:19.08#ibcon#read 6, iclass 21, count 0 2006.203.08:02:19.08#ibcon#end of sib2, iclass 21, count 0 2006.203.08:02:19.08#ibcon#*after write, iclass 21, count 0 2006.203.08:02:19.08#ibcon#*before return 0, iclass 21, count 0 2006.203.08:02:19.08#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.203.08:02:19.08#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.203.08:02:19.08#ibcon#about to clear, iclass 21 cls_cnt 0 2006.203.08:02:19.08#ibcon#cleared, iclass 21 cls_cnt 0 2006.203.08:02:19.08$vc4f8/valo=2,572.99 2006.203.08:02:19.08#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.203.08:02:19.08#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.203.08:02:19.08#ibcon#ireg 17 cls_cnt 0 2006.203.08:02:19.08#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.203.08:02:19.08#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.203.08:02:19.08#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.203.08:02:19.08#ibcon#enter wrdev, iclass 23, count 0 2006.203.08:02:19.08#ibcon#first serial, iclass 23, count 0 2006.203.08:02:19.08#ibcon#enter sib2, iclass 23, count 0 2006.203.08:02:19.08#ibcon#flushed, iclass 23, count 0 2006.203.08:02:19.08#ibcon#about to write, iclass 23, count 0 2006.203.08:02:19.08#ibcon#wrote, iclass 23, count 0 2006.203.08:02:19.08#ibcon#about to read 3, iclass 23, count 0 2006.203.08:02:19.10#ibcon#read 3, iclass 23, count 0 2006.203.08:02:19.10#ibcon#about to read 4, iclass 23, count 0 2006.203.08:02:19.10#ibcon#read 4, iclass 23, count 0 2006.203.08:02:19.10#ibcon#about to read 5, iclass 23, count 0 2006.203.08:02:19.10#ibcon#read 5, iclass 23, count 0 2006.203.08:02:19.10#ibcon#about to read 6, iclass 23, count 0 2006.203.08:02:19.10#ibcon#read 6, iclass 23, count 0 2006.203.08:02:19.10#ibcon#end of sib2, iclass 23, count 0 2006.203.08:02:19.10#ibcon#*mode == 0, iclass 23, count 0 2006.203.08:02:19.10#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.203.08:02:19.10#ibcon#[26=FRQ=02,572.99\r\n] 2006.203.08:02:19.10#ibcon#*before write, iclass 23, count 0 2006.203.08:02:19.10#ibcon#enter sib2, iclass 23, count 0 2006.203.08:02:19.10#ibcon#flushed, iclass 23, count 0 2006.203.08:02:19.10#ibcon#about to write, iclass 23, count 0 2006.203.08:02:19.10#ibcon#wrote, iclass 23, count 0 2006.203.08:02:19.10#ibcon#about to read 3, iclass 23, count 0 2006.203.08:02:19.14#ibcon#read 3, iclass 23, count 0 2006.203.08:02:19.14#ibcon#about to read 4, iclass 23, count 0 2006.203.08:02:19.14#ibcon#read 4, iclass 23, count 0 2006.203.08:02:19.14#ibcon#about to read 5, iclass 23, count 0 2006.203.08:02:19.14#ibcon#read 5, iclass 23, count 0 2006.203.08:02:19.14#ibcon#about to read 6, iclass 23, count 0 2006.203.08:02:19.14#ibcon#read 6, iclass 23, count 0 2006.203.08:02:19.14#ibcon#end of sib2, iclass 23, count 0 2006.203.08:02:19.14#ibcon#*after write, iclass 23, count 0 2006.203.08:02:19.14#ibcon#*before return 0, iclass 23, count 0 2006.203.08:02:19.14#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.203.08:02:19.14#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.203.08:02:19.14#ibcon#about to clear, iclass 23 cls_cnt 0 2006.203.08:02:19.14#ibcon#cleared, iclass 23 cls_cnt 0 2006.203.08:02:19.14$vc4f8/va=2,7 2006.203.08:02:19.14#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.203.08:02:19.14#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.203.08:02:19.14#ibcon#ireg 11 cls_cnt 2 2006.203.08:02:19.14#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.203.08:02:19.20#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.203.08:02:19.20#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.203.08:02:19.20#ibcon#enter wrdev, iclass 25, count 2 2006.203.08:02:19.20#ibcon#first serial, iclass 25, count 2 2006.203.08:02:19.20#ibcon#enter sib2, iclass 25, count 2 2006.203.08:02:19.20#ibcon#flushed, iclass 25, count 2 2006.203.08:02:19.20#ibcon#about to write, iclass 25, count 2 2006.203.08:02:19.20#ibcon#wrote, iclass 25, count 2 2006.203.08:02:19.20#ibcon#about to read 3, iclass 25, count 2 2006.203.08:02:19.22#ibcon#read 3, iclass 25, count 2 2006.203.08:02:19.22#ibcon#about to read 4, iclass 25, count 2 2006.203.08:02:19.22#ibcon#read 4, iclass 25, count 2 2006.203.08:02:19.22#ibcon#about to read 5, iclass 25, count 2 2006.203.08:02:19.22#ibcon#read 5, iclass 25, count 2 2006.203.08:02:19.22#ibcon#about to read 6, iclass 25, count 2 2006.203.08:02:19.22#ibcon#read 6, iclass 25, count 2 2006.203.08:02:19.22#ibcon#end of sib2, iclass 25, count 2 2006.203.08:02:19.22#ibcon#*mode == 0, iclass 25, count 2 2006.203.08:02:19.22#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.203.08:02:19.22#ibcon#[25=AT02-07\r\n] 2006.203.08:02:19.22#ibcon#*before write, iclass 25, count 2 2006.203.08:02:19.22#ibcon#enter sib2, iclass 25, count 2 2006.203.08:02:19.22#ibcon#flushed, iclass 25, count 2 2006.203.08:02:19.22#ibcon#about to write, iclass 25, count 2 2006.203.08:02:19.22#ibcon#wrote, iclass 25, count 2 2006.203.08:02:19.22#ibcon#about to read 3, iclass 25, count 2 2006.203.08:02:19.25#ibcon#read 3, iclass 25, count 2 2006.203.08:02:19.25#ibcon#about to read 4, iclass 25, count 2 2006.203.08:02:19.25#ibcon#read 4, iclass 25, count 2 2006.203.08:02:19.25#ibcon#about to read 5, iclass 25, count 2 2006.203.08:02:19.25#ibcon#read 5, iclass 25, count 2 2006.203.08:02:19.25#ibcon#about to read 6, iclass 25, count 2 2006.203.08:02:19.25#ibcon#read 6, iclass 25, count 2 2006.203.08:02:19.25#ibcon#end of sib2, iclass 25, count 2 2006.203.08:02:19.25#ibcon#*after write, iclass 25, count 2 2006.203.08:02:19.25#ibcon#*before return 0, iclass 25, count 2 2006.203.08:02:19.25#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.203.08:02:19.25#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.203.08:02:19.25#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.203.08:02:19.25#ibcon#ireg 7 cls_cnt 0 2006.203.08:02:19.25#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.203.08:02:19.37#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.203.08:02:19.37#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.203.08:02:19.37#ibcon#enter wrdev, iclass 25, count 0 2006.203.08:02:19.37#ibcon#first serial, iclass 25, count 0 2006.203.08:02:19.37#ibcon#enter sib2, iclass 25, count 0 2006.203.08:02:19.37#ibcon#flushed, iclass 25, count 0 2006.203.08:02:19.37#ibcon#about to write, iclass 25, count 0 2006.203.08:02:19.37#ibcon#wrote, iclass 25, count 0 2006.203.08:02:19.37#ibcon#about to read 3, iclass 25, count 0 2006.203.08:02:19.39#ibcon#read 3, iclass 25, count 0 2006.203.08:02:19.39#ibcon#about to read 4, iclass 25, count 0 2006.203.08:02:19.39#ibcon#read 4, iclass 25, count 0 2006.203.08:02:19.39#ibcon#about to read 5, iclass 25, count 0 2006.203.08:02:19.39#ibcon#read 5, iclass 25, count 0 2006.203.08:02:19.39#ibcon#about to read 6, iclass 25, count 0 2006.203.08:02:19.39#ibcon#read 6, iclass 25, count 0 2006.203.08:02:19.39#ibcon#end of sib2, iclass 25, count 0 2006.203.08:02:19.39#ibcon#*mode == 0, iclass 25, count 0 2006.203.08:02:19.39#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.203.08:02:19.39#ibcon#[25=USB\r\n] 2006.203.08:02:19.39#ibcon#*before write, iclass 25, count 0 2006.203.08:02:19.39#ibcon#enter sib2, iclass 25, count 0 2006.203.08:02:19.39#ibcon#flushed, iclass 25, count 0 2006.203.08:02:19.39#ibcon#about to write, iclass 25, count 0 2006.203.08:02:19.39#ibcon#wrote, iclass 25, count 0 2006.203.08:02:19.39#ibcon#about to read 3, iclass 25, count 0 2006.203.08:02:19.42#ibcon#read 3, iclass 25, count 0 2006.203.08:02:19.42#ibcon#about to read 4, iclass 25, count 0 2006.203.08:02:19.42#ibcon#read 4, iclass 25, count 0 2006.203.08:02:19.42#ibcon#about to read 5, iclass 25, count 0 2006.203.08:02:19.42#ibcon#read 5, iclass 25, count 0 2006.203.08:02:19.42#ibcon#about to read 6, iclass 25, count 0 2006.203.08:02:19.42#ibcon#read 6, iclass 25, count 0 2006.203.08:02:19.42#ibcon#end of sib2, iclass 25, count 0 2006.203.08:02:19.42#ibcon#*after write, iclass 25, count 0 2006.203.08:02:19.42#ibcon#*before return 0, iclass 25, count 0 2006.203.08:02:19.42#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.203.08:02:19.42#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.203.08:02:19.42#ibcon#about to clear, iclass 25 cls_cnt 0 2006.203.08:02:19.42#ibcon#cleared, iclass 25 cls_cnt 0 2006.203.08:02:19.42$vc4f8/valo=3,672.99 2006.203.08:02:19.42#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.203.08:02:19.42#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.203.08:02:19.42#ibcon#ireg 17 cls_cnt 0 2006.203.08:02:19.42#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.203.08:02:19.42#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.203.08:02:19.42#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.203.08:02:19.42#ibcon#enter wrdev, iclass 27, count 0 2006.203.08:02:19.42#ibcon#first serial, iclass 27, count 0 2006.203.08:02:19.42#ibcon#enter sib2, iclass 27, count 0 2006.203.08:02:19.42#ibcon#flushed, iclass 27, count 0 2006.203.08:02:19.42#ibcon#about to write, iclass 27, count 0 2006.203.08:02:19.42#ibcon#wrote, iclass 27, count 0 2006.203.08:02:19.42#ibcon#about to read 3, iclass 27, count 0 2006.203.08:02:19.44#ibcon#read 3, iclass 27, count 0 2006.203.08:02:19.44#ibcon#about to read 4, iclass 27, count 0 2006.203.08:02:19.44#ibcon#read 4, iclass 27, count 0 2006.203.08:02:19.44#ibcon#about to read 5, iclass 27, count 0 2006.203.08:02:19.44#ibcon#read 5, iclass 27, count 0 2006.203.08:02:19.44#ibcon#about to read 6, iclass 27, count 0 2006.203.08:02:19.44#ibcon#read 6, iclass 27, count 0 2006.203.08:02:19.44#ibcon#end of sib2, iclass 27, count 0 2006.203.08:02:19.44#ibcon#*mode == 0, iclass 27, count 0 2006.203.08:02:19.44#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.203.08:02:19.44#ibcon#[26=FRQ=03,672.99\r\n] 2006.203.08:02:19.44#ibcon#*before write, iclass 27, count 0 2006.203.08:02:19.44#ibcon#enter sib2, iclass 27, count 0 2006.203.08:02:19.44#ibcon#flushed, iclass 27, count 0 2006.203.08:02:19.44#ibcon#about to write, iclass 27, count 0 2006.203.08:02:19.44#ibcon#wrote, iclass 27, count 0 2006.203.08:02:19.44#ibcon#about to read 3, iclass 27, count 0 2006.203.08:02:19.48#ibcon#read 3, iclass 27, count 0 2006.203.08:02:19.48#ibcon#about to read 4, iclass 27, count 0 2006.203.08:02:19.48#ibcon#read 4, iclass 27, count 0 2006.203.08:02:19.48#ibcon#about to read 5, iclass 27, count 0 2006.203.08:02:19.48#ibcon#read 5, iclass 27, count 0 2006.203.08:02:19.48#ibcon#about to read 6, iclass 27, count 0 2006.203.08:02:19.48#ibcon#read 6, iclass 27, count 0 2006.203.08:02:19.48#ibcon#end of sib2, iclass 27, count 0 2006.203.08:02:19.48#ibcon#*after write, iclass 27, count 0 2006.203.08:02:19.48#ibcon#*before return 0, iclass 27, count 0 2006.203.08:02:19.48#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.203.08:02:19.48#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.203.08:02:19.48#ibcon#about to clear, iclass 27 cls_cnt 0 2006.203.08:02:19.48#ibcon#cleared, iclass 27 cls_cnt 0 2006.203.08:02:19.48$vc4f8/va=3,8 2006.203.08:02:19.48#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.203.08:02:19.48#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.203.08:02:19.48#ibcon#ireg 11 cls_cnt 2 2006.203.08:02:19.48#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.203.08:02:19.54#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.203.08:02:19.54#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.203.08:02:19.54#ibcon#enter wrdev, iclass 29, count 2 2006.203.08:02:19.54#ibcon#first serial, iclass 29, count 2 2006.203.08:02:19.54#ibcon#enter sib2, iclass 29, count 2 2006.203.08:02:19.54#ibcon#flushed, iclass 29, count 2 2006.203.08:02:19.54#ibcon#about to write, iclass 29, count 2 2006.203.08:02:19.54#ibcon#wrote, iclass 29, count 2 2006.203.08:02:19.54#ibcon#about to read 3, iclass 29, count 2 2006.203.08:02:19.56#ibcon#read 3, iclass 29, count 2 2006.203.08:02:19.56#ibcon#about to read 4, iclass 29, count 2 2006.203.08:02:19.56#ibcon#read 4, iclass 29, count 2 2006.203.08:02:19.56#ibcon#about to read 5, iclass 29, count 2 2006.203.08:02:19.56#ibcon#read 5, iclass 29, count 2 2006.203.08:02:19.56#ibcon#about to read 6, iclass 29, count 2 2006.203.08:02:19.56#ibcon#read 6, iclass 29, count 2 2006.203.08:02:19.56#ibcon#end of sib2, iclass 29, count 2 2006.203.08:02:19.56#ibcon#*mode == 0, iclass 29, count 2 2006.203.08:02:19.56#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.203.08:02:19.56#ibcon#[25=AT03-08\r\n] 2006.203.08:02:19.56#ibcon#*before write, iclass 29, count 2 2006.203.08:02:19.56#ibcon#enter sib2, iclass 29, count 2 2006.203.08:02:19.56#ibcon#flushed, iclass 29, count 2 2006.203.08:02:19.56#ibcon#about to write, iclass 29, count 2 2006.203.08:02:19.56#ibcon#wrote, iclass 29, count 2 2006.203.08:02:19.56#ibcon#about to read 3, iclass 29, count 2 2006.203.08:02:19.59#ibcon#read 3, iclass 29, count 2 2006.203.08:02:19.59#ibcon#about to read 4, iclass 29, count 2 2006.203.08:02:19.59#ibcon#read 4, iclass 29, count 2 2006.203.08:02:19.59#ibcon#about to read 5, iclass 29, count 2 2006.203.08:02:19.59#ibcon#read 5, iclass 29, count 2 2006.203.08:02:19.59#ibcon#about to read 6, iclass 29, count 2 2006.203.08:02:19.59#ibcon#read 6, iclass 29, count 2 2006.203.08:02:19.59#ibcon#end of sib2, iclass 29, count 2 2006.203.08:02:19.59#ibcon#*after write, iclass 29, count 2 2006.203.08:02:19.59#ibcon#*before return 0, iclass 29, count 2 2006.203.08:02:19.59#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.203.08:02:19.59#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.203.08:02:19.59#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.203.08:02:19.59#ibcon#ireg 7 cls_cnt 0 2006.203.08:02:19.59#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.203.08:02:19.71#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.203.08:02:19.71#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.203.08:02:19.71#ibcon#enter wrdev, iclass 29, count 0 2006.203.08:02:19.71#ibcon#first serial, iclass 29, count 0 2006.203.08:02:19.71#ibcon#enter sib2, iclass 29, count 0 2006.203.08:02:19.71#ibcon#flushed, iclass 29, count 0 2006.203.08:02:19.71#ibcon#about to write, iclass 29, count 0 2006.203.08:02:19.71#ibcon#wrote, iclass 29, count 0 2006.203.08:02:19.71#ibcon#about to read 3, iclass 29, count 0 2006.203.08:02:19.73#ibcon#read 3, iclass 29, count 0 2006.203.08:02:19.73#ibcon#about to read 4, iclass 29, count 0 2006.203.08:02:19.73#ibcon#read 4, iclass 29, count 0 2006.203.08:02:19.73#ibcon#about to read 5, iclass 29, count 0 2006.203.08:02:19.73#ibcon#read 5, iclass 29, count 0 2006.203.08:02:19.73#ibcon#about to read 6, iclass 29, count 0 2006.203.08:02:19.73#ibcon#read 6, iclass 29, count 0 2006.203.08:02:19.73#ibcon#end of sib2, iclass 29, count 0 2006.203.08:02:19.73#ibcon#*mode == 0, iclass 29, count 0 2006.203.08:02:19.73#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.203.08:02:19.73#ibcon#[25=USB\r\n] 2006.203.08:02:19.73#ibcon#*before write, iclass 29, count 0 2006.203.08:02:19.73#ibcon#enter sib2, iclass 29, count 0 2006.203.08:02:19.73#ibcon#flushed, iclass 29, count 0 2006.203.08:02:19.73#ibcon#about to write, iclass 29, count 0 2006.203.08:02:19.73#ibcon#wrote, iclass 29, count 0 2006.203.08:02:19.73#ibcon#about to read 3, iclass 29, count 0 2006.203.08:02:19.76#ibcon#read 3, iclass 29, count 0 2006.203.08:02:19.76#ibcon#about to read 4, iclass 29, count 0 2006.203.08:02:19.76#ibcon#read 4, iclass 29, count 0 2006.203.08:02:19.76#ibcon#about to read 5, iclass 29, count 0 2006.203.08:02:19.76#ibcon#read 5, iclass 29, count 0 2006.203.08:02:19.76#ibcon#about to read 6, iclass 29, count 0 2006.203.08:02:19.76#ibcon#read 6, iclass 29, count 0 2006.203.08:02:19.76#ibcon#end of sib2, iclass 29, count 0 2006.203.08:02:19.76#ibcon#*after write, iclass 29, count 0 2006.203.08:02:19.76#ibcon#*before return 0, iclass 29, count 0 2006.203.08:02:19.76#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.203.08:02:19.76#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.203.08:02:19.76#ibcon#about to clear, iclass 29 cls_cnt 0 2006.203.08:02:19.76#ibcon#cleared, iclass 29 cls_cnt 0 2006.203.08:02:19.76$vc4f8/valo=4,832.99 2006.203.08:02:19.76#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.203.08:02:19.76#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.203.08:02:19.76#ibcon#ireg 17 cls_cnt 0 2006.203.08:02:19.76#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.203.08:02:19.76#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.203.08:02:19.76#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.203.08:02:19.76#ibcon#enter wrdev, iclass 31, count 0 2006.203.08:02:19.76#ibcon#first serial, iclass 31, count 0 2006.203.08:02:19.76#ibcon#enter sib2, iclass 31, count 0 2006.203.08:02:19.76#ibcon#flushed, iclass 31, count 0 2006.203.08:02:19.76#ibcon#about to write, iclass 31, count 0 2006.203.08:02:19.76#ibcon#wrote, iclass 31, count 0 2006.203.08:02:19.76#ibcon#about to read 3, iclass 31, count 0 2006.203.08:02:19.78#ibcon#read 3, iclass 31, count 0 2006.203.08:02:19.78#ibcon#about to read 4, iclass 31, count 0 2006.203.08:02:19.78#ibcon#read 4, iclass 31, count 0 2006.203.08:02:19.78#ibcon#about to read 5, iclass 31, count 0 2006.203.08:02:19.78#ibcon#read 5, iclass 31, count 0 2006.203.08:02:19.78#ibcon#about to read 6, iclass 31, count 0 2006.203.08:02:19.78#ibcon#read 6, iclass 31, count 0 2006.203.08:02:19.78#ibcon#end of sib2, iclass 31, count 0 2006.203.08:02:19.78#ibcon#*mode == 0, iclass 31, count 0 2006.203.08:02:19.78#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.203.08:02:19.78#ibcon#[26=FRQ=04,832.99\r\n] 2006.203.08:02:19.78#ibcon#*before write, iclass 31, count 0 2006.203.08:02:19.78#ibcon#enter sib2, iclass 31, count 0 2006.203.08:02:19.78#ibcon#flushed, iclass 31, count 0 2006.203.08:02:19.78#ibcon#about to write, iclass 31, count 0 2006.203.08:02:19.78#ibcon#wrote, iclass 31, count 0 2006.203.08:02:19.78#ibcon#about to read 3, iclass 31, count 0 2006.203.08:02:19.82#ibcon#read 3, iclass 31, count 0 2006.203.08:02:19.82#ibcon#about to read 4, iclass 31, count 0 2006.203.08:02:19.82#ibcon#read 4, iclass 31, count 0 2006.203.08:02:19.82#ibcon#about to read 5, iclass 31, count 0 2006.203.08:02:19.82#ibcon#read 5, iclass 31, count 0 2006.203.08:02:19.82#ibcon#about to read 6, iclass 31, count 0 2006.203.08:02:19.82#ibcon#read 6, iclass 31, count 0 2006.203.08:02:19.82#ibcon#end of sib2, iclass 31, count 0 2006.203.08:02:19.82#ibcon#*after write, iclass 31, count 0 2006.203.08:02:19.82#ibcon#*before return 0, iclass 31, count 0 2006.203.08:02:19.82#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.203.08:02:19.82#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.203.08:02:19.82#ibcon#about to clear, iclass 31 cls_cnt 0 2006.203.08:02:19.82#ibcon#cleared, iclass 31 cls_cnt 0 2006.203.08:02:19.82$vc4f8/va=4,7 2006.203.08:02:19.82#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.203.08:02:19.82#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.203.08:02:19.82#ibcon#ireg 11 cls_cnt 2 2006.203.08:02:19.82#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.203.08:02:19.88#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.203.08:02:19.88#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.203.08:02:19.88#ibcon#enter wrdev, iclass 33, count 2 2006.203.08:02:19.88#ibcon#first serial, iclass 33, count 2 2006.203.08:02:19.88#ibcon#enter sib2, iclass 33, count 2 2006.203.08:02:19.88#ibcon#flushed, iclass 33, count 2 2006.203.08:02:19.88#ibcon#about to write, iclass 33, count 2 2006.203.08:02:19.88#ibcon#wrote, iclass 33, count 2 2006.203.08:02:19.88#ibcon#about to read 3, iclass 33, count 2 2006.203.08:02:19.90#ibcon#read 3, iclass 33, count 2 2006.203.08:02:19.90#ibcon#about to read 4, iclass 33, count 2 2006.203.08:02:19.90#ibcon#read 4, iclass 33, count 2 2006.203.08:02:19.90#ibcon#about to read 5, iclass 33, count 2 2006.203.08:02:19.90#ibcon#read 5, iclass 33, count 2 2006.203.08:02:19.90#ibcon#about to read 6, iclass 33, count 2 2006.203.08:02:19.90#ibcon#read 6, iclass 33, count 2 2006.203.08:02:19.90#ibcon#end of sib2, iclass 33, count 2 2006.203.08:02:19.90#ibcon#*mode == 0, iclass 33, count 2 2006.203.08:02:19.90#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.203.08:02:19.90#ibcon#[25=AT04-07\r\n] 2006.203.08:02:19.90#ibcon#*before write, iclass 33, count 2 2006.203.08:02:19.90#ibcon#enter sib2, iclass 33, count 2 2006.203.08:02:19.90#ibcon#flushed, iclass 33, count 2 2006.203.08:02:19.90#ibcon#about to write, iclass 33, count 2 2006.203.08:02:19.90#ibcon#wrote, iclass 33, count 2 2006.203.08:02:19.90#ibcon#about to read 3, iclass 33, count 2 2006.203.08:02:19.93#ibcon#read 3, iclass 33, count 2 2006.203.08:02:19.93#ibcon#about to read 4, iclass 33, count 2 2006.203.08:02:19.93#ibcon#read 4, iclass 33, count 2 2006.203.08:02:19.93#ibcon#about to read 5, iclass 33, count 2 2006.203.08:02:19.93#ibcon#read 5, iclass 33, count 2 2006.203.08:02:19.93#ibcon#about to read 6, iclass 33, count 2 2006.203.08:02:19.93#ibcon#read 6, iclass 33, count 2 2006.203.08:02:19.93#ibcon#end of sib2, iclass 33, count 2 2006.203.08:02:19.93#ibcon#*after write, iclass 33, count 2 2006.203.08:02:19.93#ibcon#*before return 0, iclass 33, count 2 2006.203.08:02:19.93#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.203.08:02:19.93#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.203.08:02:19.93#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.203.08:02:19.93#ibcon#ireg 7 cls_cnt 0 2006.203.08:02:19.93#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.203.08:02:20.05#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.203.08:02:20.05#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.203.08:02:20.05#ibcon#enter wrdev, iclass 33, count 0 2006.203.08:02:20.05#ibcon#first serial, iclass 33, count 0 2006.203.08:02:20.05#ibcon#enter sib2, iclass 33, count 0 2006.203.08:02:20.05#ibcon#flushed, iclass 33, count 0 2006.203.08:02:20.05#ibcon#about to write, iclass 33, count 0 2006.203.08:02:20.05#ibcon#wrote, iclass 33, count 0 2006.203.08:02:20.05#ibcon#about to read 3, iclass 33, count 0 2006.203.08:02:20.07#ibcon#read 3, iclass 33, count 0 2006.203.08:02:20.07#ibcon#about to read 4, iclass 33, count 0 2006.203.08:02:20.07#ibcon#read 4, iclass 33, count 0 2006.203.08:02:20.07#ibcon#about to read 5, iclass 33, count 0 2006.203.08:02:20.07#ibcon#read 5, iclass 33, count 0 2006.203.08:02:20.07#ibcon#about to read 6, iclass 33, count 0 2006.203.08:02:20.07#ibcon#read 6, iclass 33, count 0 2006.203.08:02:20.07#ibcon#end of sib2, iclass 33, count 0 2006.203.08:02:20.07#ibcon#*mode == 0, iclass 33, count 0 2006.203.08:02:20.07#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.203.08:02:20.07#ibcon#[25=USB\r\n] 2006.203.08:02:20.07#ibcon#*before write, iclass 33, count 0 2006.203.08:02:20.07#ibcon#enter sib2, iclass 33, count 0 2006.203.08:02:20.07#ibcon#flushed, iclass 33, count 0 2006.203.08:02:20.07#ibcon#about to write, iclass 33, count 0 2006.203.08:02:20.07#ibcon#wrote, iclass 33, count 0 2006.203.08:02:20.07#ibcon#about to read 3, iclass 33, count 0 2006.203.08:02:20.10#ibcon#read 3, iclass 33, count 0 2006.203.08:02:20.10#ibcon#about to read 4, iclass 33, count 0 2006.203.08:02:20.10#ibcon#read 4, iclass 33, count 0 2006.203.08:02:20.10#ibcon#about to read 5, iclass 33, count 0 2006.203.08:02:20.10#ibcon#read 5, iclass 33, count 0 2006.203.08:02:20.10#ibcon#about to read 6, iclass 33, count 0 2006.203.08:02:20.10#ibcon#read 6, iclass 33, count 0 2006.203.08:02:20.10#ibcon#end of sib2, iclass 33, count 0 2006.203.08:02:20.10#ibcon#*after write, iclass 33, count 0 2006.203.08:02:20.10#ibcon#*before return 0, iclass 33, count 0 2006.203.08:02:20.10#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.203.08:02:20.10#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.203.08:02:20.10#ibcon#about to clear, iclass 33 cls_cnt 0 2006.203.08:02:20.10#ibcon#cleared, iclass 33 cls_cnt 0 2006.203.08:02:20.10$vc4f8/valo=5,652.99 2006.203.08:02:20.10#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.203.08:02:20.10#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.203.08:02:20.10#ibcon#ireg 17 cls_cnt 0 2006.203.08:02:20.10#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.203.08:02:20.10#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.203.08:02:20.10#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.203.08:02:20.10#ibcon#enter wrdev, iclass 35, count 0 2006.203.08:02:20.10#ibcon#first serial, iclass 35, count 0 2006.203.08:02:20.10#ibcon#enter sib2, iclass 35, count 0 2006.203.08:02:20.10#ibcon#flushed, iclass 35, count 0 2006.203.08:02:20.10#ibcon#about to write, iclass 35, count 0 2006.203.08:02:20.10#ibcon#wrote, iclass 35, count 0 2006.203.08:02:20.10#ibcon#about to read 3, iclass 35, count 0 2006.203.08:02:20.12#ibcon#read 3, iclass 35, count 0 2006.203.08:02:20.12#ibcon#about to read 4, iclass 35, count 0 2006.203.08:02:20.12#ibcon#read 4, iclass 35, count 0 2006.203.08:02:20.12#ibcon#about to read 5, iclass 35, count 0 2006.203.08:02:20.12#ibcon#read 5, iclass 35, count 0 2006.203.08:02:20.12#ibcon#about to read 6, iclass 35, count 0 2006.203.08:02:20.12#ibcon#read 6, iclass 35, count 0 2006.203.08:02:20.12#ibcon#end of sib2, iclass 35, count 0 2006.203.08:02:20.12#ibcon#*mode == 0, iclass 35, count 0 2006.203.08:02:20.12#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.203.08:02:20.12#ibcon#[26=FRQ=05,652.99\r\n] 2006.203.08:02:20.12#ibcon#*before write, iclass 35, count 0 2006.203.08:02:20.12#ibcon#enter sib2, iclass 35, count 0 2006.203.08:02:20.12#ibcon#flushed, iclass 35, count 0 2006.203.08:02:20.12#ibcon#about to write, iclass 35, count 0 2006.203.08:02:20.12#ibcon#wrote, iclass 35, count 0 2006.203.08:02:20.12#ibcon#about to read 3, iclass 35, count 0 2006.203.08:02:20.16#ibcon#read 3, iclass 35, count 0 2006.203.08:02:20.16#ibcon#about to read 4, iclass 35, count 0 2006.203.08:02:20.16#ibcon#read 4, iclass 35, count 0 2006.203.08:02:20.16#ibcon#about to read 5, iclass 35, count 0 2006.203.08:02:20.16#ibcon#read 5, iclass 35, count 0 2006.203.08:02:20.16#ibcon#about to read 6, iclass 35, count 0 2006.203.08:02:20.16#ibcon#read 6, iclass 35, count 0 2006.203.08:02:20.16#ibcon#end of sib2, iclass 35, count 0 2006.203.08:02:20.16#ibcon#*after write, iclass 35, count 0 2006.203.08:02:20.16#ibcon#*before return 0, iclass 35, count 0 2006.203.08:02:20.16#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.203.08:02:20.16#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.203.08:02:20.16#ibcon#about to clear, iclass 35 cls_cnt 0 2006.203.08:02:20.16#ibcon#cleared, iclass 35 cls_cnt 0 2006.203.08:02:20.16$vc4f8/va=5,7 2006.203.08:02:20.16#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.203.08:02:20.16#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.203.08:02:20.16#ibcon#ireg 11 cls_cnt 2 2006.203.08:02:20.16#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.203.08:02:20.22#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.203.08:02:20.22#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.203.08:02:20.22#ibcon#enter wrdev, iclass 37, count 2 2006.203.08:02:20.22#ibcon#first serial, iclass 37, count 2 2006.203.08:02:20.22#ibcon#enter sib2, iclass 37, count 2 2006.203.08:02:20.22#ibcon#flushed, iclass 37, count 2 2006.203.08:02:20.22#ibcon#about to write, iclass 37, count 2 2006.203.08:02:20.22#ibcon#wrote, iclass 37, count 2 2006.203.08:02:20.22#ibcon#about to read 3, iclass 37, count 2 2006.203.08:02:20.24#ibcon#read 3, iclass 37, count 2 2006.203.08:02:20.24#ibcon#about to read 4, iclass 37, count 2 2006.203.08:02:20.24#ibcon#read 4, iclass 37, count 2 2006.203.08:02:20.24#ibcon#about to read 5, iclass 37, count 2 2006.203.08:02:20.24#ibcon#read 5, iclass 37, count 2 2006.203.08:02:20.24#ibcon#about to read 6, iclass 37, count 2 2006.203.08:02:20.24#ibcon#read 6, iclass 37, count 2 2006.203.08:02:20.24#ibcon#end of sib2, iclass 37, count 2 2006.203.08:02:20.24#ibcon#*mode == 0, iclass 37, count 2 2006.203.08:02:20.24#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.203.08:02:20.24#ibcon#[25=AT05-07\r\n] 2006.203.08:02:20.24#ibcon#*before write, iclass 37, count 2 2006.203.08:02:20.24#ibcon#enter sib2, iclass 37, count 2 2006.203.08:02:20.24#ibcon#flushed, iclass 37, count 2 2006.203.08:02:20.24#ibcon#about to write, iclass 37, count 2 2006.203.08:02:20.24#ibcon#wrote, iclass 37, count 2 2006.203.08:02:20.24#ibcon#about to read 3, iclass 37, count 2 2006.203.08:02:20.27#ibcon#read 3, iclass 37, count 2 2006.203.08:02:20.27#ibcon#about to read 4, iclass 37, count 2 2006.203.08:02:20.27#ibcon#read 4, iclass 37, count 2 2006.203.08:02:20.27#ibcon#about to read 5, iclass 37, count 2 2006.203.08:02:20.27#ibcon#read 5, iclass 37, count 2 2006.203.08:02:20.27#ibcon#about to read 6, iclass 37, count 2 2006.203.08:02:20.27#ibcon#read 6, iclass 37, count 2 2006.203.08:02:20.27#ibcon#end of sib2, iclass 37, count 2 2006.203.08:02:20.27#ibcon#*after write, iclass 37, count 2 2006.203.08:02:20.27#ibcon#*before return 0, iclass 37, count 2 2006.203.08:02:20.27#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.203.08:02:20.27#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.203.08:02:20.27#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.203.08:02:20.27#ibcon#ireg 7 cls_cnt 0 2006.203.08:02:20.27#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.203.08:02:20.39#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.203.08:02:20.39#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.203.08:02:20.39#ibcon#enter wrdev, iclass 37, count 0 2006.203.08:02:20.39#ibcon#first serial, iclass 37, count 0 2006.203.08:02:20.39#ibcon#enter sib2, iclass 37, count 0 2006.203.08:02:20.39#ibcon#flushed, iclass 37, count 0 2006.203.08:02:20.39#ibcon#about to write, iclass 37, count 0 2006.203.08:02:20.39#ibcon#wrote, iclass 37, count 0 2006.203.08:02:20.39#ibcon#about to read 3, iclass 37, count 0 2006.203.08:02:20.41#ibcon#read 3, iclass 37, count 0 2006.203.08:02:20.41#ibcon#about to read 4, iclass 37, count 0 2006.203.08:02:20.41#ibcon#read 4, iclass 37, count 0 2006.203.08:02:20.41#ibcon#about to read 5, iclass 37, count 0 2006.203.08:02:20.41#ibcon#read 5, iclass 37, count 0 2006.203.08:02:20.41#ibcon#about to read 6, iclass 37, count 0 2006.203.08:02:20.41#ibcon#read 6, iclass 37, count 0 2006.203.08:02:20.41#ibcon#end of sib2, iclass 37, count 0 2006.203.08:02:20.41#ibcon#*mode == 0, iclass 37, count 0 2006.203.08:02:20.41#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.203.08:02:20.41#ibcon#[25=USB\r\n] 2006.203.08:02:20.41#ibcon#*before write, iclass 37, count 0 2006.203.08:02:20.41#ibcon#enter sib2, iclass 37, count 0 2006.203.08:02:20.41#ibcon#flushed, iclass 37, count 0 2006.203.08:02:20.41#ibcon#about to write, iclass 37, count 0 2006.203.08:02:20.41#ibcon#wrote, iclass 37, count 0 2006.203.08:02:20.41#ibcon#about to read 3, iclass 37, count 0 2006.203.08:02:20.44#ibcon#read 3, iclass 37, count 0 2006.203.08:02:20.44#ibcon#about to read 4, iclass 37, count 0 2006.203.08:02:20.44#ibcon#read 4, iclass 37, count 0 2006.203.08:02:20.44#ibcon#about to read 5, iclass 37, count 0 2006.203.08:02:20.44#ibcon#read 5, iclass 37, count 0 2006.203.08:02:20.44#ibcon#about to read 6, iclass 37, count 0 2006.203.08:02:20.44#ibcon#read 6, iclass 37, count 0 2006.203.08:02:20.44#ibcon#end of sib2, iclass 37, count 0 2006.203.08:02:20.44#ibcon#*after write, iclass 37, count 0 2006.203.08:02:20.44#ibcon#*before return 0, iclass 37, count 0 2006.203.08:02:20.44#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.203.08:02:20.44#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.203.08:02:20.44#ibcon#about to clear, iclass 37 cls_cnt 0 2006.203.08:02:20.44#ibcon#cleared, iclass 37 cls_cnt 0 2006.203.08:02:20.44$vc4f8/valo=6,772.99 2006.203.08:02:20.44#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.203.08:02:20.44#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.203.08:02:20.44#ibcon#ireg 17 cls_cnt 0 2006.203.08:02:20.44#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.203.08:02:20.44#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.203.08:02:20.44#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.203.08:02:20.44#ibcon#enter wrdev, iclass 39, count 0 2006.203.08:02:20.44#ibcon#first serial, iclass 39, count 0 2006.203.08:02:20.44#ibcon#enter sib2, iclass 39, count 0 2006.203.08:02:20.44#ibcon#flushed, iclass 39, count 0 2006.203.08:02:20.44#ibcon#about to write, iclass 39, count 0 2006.203.08:02:20.44#ibcon#wrote, iclass 39, count 0 2006.203.08:02:20.44#ibcon#about to read 3, iclass 39, count 0 2006.203.08:02:20.46#ibcon#read 3, iclass 39, count 0 2006.203.08:02:20.46#ibcon#about to read 4, iclass 39, count 0 2006.203.08:02:20.46#ibcon#read 4, iclass 39, count 0 2006.203.08:02:20.46#ibcon#about to read 5, iclass 39, count 0 2006.203.08:02:20.46#ibcon#read 5, iclass 39, count 0 2006.203.08:02:20.46#ibcon#about to read 6, iclass 39, count 0 2006.203.08:02:20.46#ibcon#read 6, iclass 39, count 0 2006.203.08:02:20.46#ibcon#end of sib2, iclass 39, count 0 2006.203.08:02:20.46#ibcon#*mode == 0, iclass 39, count 0 2006.203.08:02:20.46#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.203.08:02:20.46#ibcon#[26=FRQ=06,772.99\r\n] 2006.203.08:02:20.46#ibcon#*before write, iclass 39, count 0 2006.203.08:02:20.46#ibcon#enter sib2, iclass 39, count 0 2006.203.08:02:20.46#ibcon#flushed, iclass 39, count 0 2006.203.08:02:20.46#ibcon#about to write, iclass 39, count 0 2006.203.08:02:20.46#ibcon#wrote, iclass 39, count 0 2006.203.08:02:20.46#ibcon#about to read 3, iclass 39, count 0 2006.203.08:02:20.50#ibcon#read 3, iclass 39, count 0 2006.203.08:02:20.50#ibcon#about to read 4, iclass 39, count 0 2006.203.08:02:20.50#ibcon#read 4, iclass 39, count 0 2006.203.08:02:20.50#ibcon#about to read 5, iclass 39, count 0 2006.203.08:02:20.50#ibcon#read 5, iclass 39, count 0 2006.203.08:02:20.50#ibcon#about to read 6, iclass 39, count 0 2006.203.08:02:20.50#ibcon#read 6, iclass 39, count 0 2006.203.08:02:20.50#ibcon#end of sib2, iclass 39, count 0 2006.203.08:02:20.50#ibcon#*after write, iclass 39, count 0 2006.203.08:02:20.50#ibcon#*before return 0, iclass 39, count 0 2006.203.08:02:20.50#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.203.08:02:20.50#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.203.08:02:20.50#ibcon#about to clear, iclass 39 cls_cnt 0 2006.203.08:02:20.50#ibcon#cleared, iclass 39 cls_cnt 0 2006.203.08:02:20.50$vc4f8/va=6,6 2006.203.08:02:20.50#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.203.08:02:20.50#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.203.08:02:20.50#ibcon#ireg 11 cls_cnt 2 2006.203.08:02:20.50#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.203.08:02:20.56#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.203.08:02:20.56#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.203.08:02:20.56#ibcon#enter wrdev, iclass 3, count 2 2006.203.08:02:20.56#ibcon#first serial, iclass 3, count 2 2006.203.08:02:20.56#ibcon#enter sib2, iclass 3, count 2 2006.203.08:02:20.56#ibcon#flushed, iclass 3, count 2 2006.203.08:02:20.56#ibcon#about to write, iclass 3, count 2 2006.203.08:02:20.56#ibcon#wrote, iclass 3, count 2 2006.203.08:02:20.56#ibcon#about to read 3, iclass 3, count 2 2006.203.08:02:20.58#ibcon#read 3, iclass 3, count 2 2006.203.08:02:20.58#ibcon#about to read 4, iclass 3, count 2 2006.203.08:02:20.58#ibcon#read 4, iclass 3, count 2 2006.203.08:02:20.58#ibcon#about to read 5, iclass 3, count 2 2006.203.08:02:20.58#ibcon#read 5, iclass 3, count 2 2006.203.08:02:20.58#ibcon#about to read 6, iclass 3, count 2 2006.203.08:02:20.58#ibcon#read 6, iclass 3, count 2 2006.203.08:02:20.58#ibcon#end of sib2, iclass 3, count 2 2006.203.08:02:20.58#ibcon#*mode == 0, iclass 3, count 2 2006.203.08:02:20.58#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.203.08:02:20.58#ibcon#[25=AT06-06\r\n] 2006.203.08:02:20.58#ibcon#*before write, iclass 3, count 2 2006.203.08:02:20.58#ibcon#enter sib2, iclass 3, count 2 2006.203.08:02:20.58#ibcon#flushed, iclass 3, count 2 2006.203.08:02:20.58#ibcon#about to write, iclass 3, count 2 2006.203.08:02:20.58#ibcon#wrote, iclass 3, count 2 2006.203.08:02:20.58#ibcon#about to read 3, iclass 3, count 2 2006.203.08:02:20.61#ibcon#read 3, iclass 3, count 2 2006.203.08:02:20.61#ibcon#about to read 4, iclass 3, count 2 2006.203.08:02:20.61#ibcon#read 4, iclass 3, count 2 2006.203.08:02:20.61#ibcon#about to read 5, iclass 3, count 2 2006.203.08:02:20.61#ibcon#read 5, iclass 3, count 2 2006.203.08:02:20.61#ibcon#about to read 6, iclass 3, count 2 2006.203.08:02:20.61#ibcon#read 6, iclass 3, count 2 2006.203.08:02:20.61#ibcon#end of sib2, iclass 3, count 2 2006.203.08:02:20.61#ibcon#*after write, iclass 3, count 2 2006.203.08:02:20.61#ibcon#*before return 0, iclass 3, count 2 2006.203.08:02:20.61#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.203.08:02:20.61#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.203.08:02:20.61#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.203.08:02:20.61#ibcon#ireg 7 cls_cnt 0 2006.203.08:02:20.61#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.203.08:02:20.73#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.203.08:02:20.73#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.203.08:02:20.73#ibcon#enter wrdev, iclass 3, count 0 2006.203.08:02:20.73#ibcon#first serial, iclass 3, count 0 2006.203.08:02:20.73#ibcon#enter sib2, iclass 3, count 0 2006.203.08:02:20.73#ibcon#flushed, iclass 3, count 0 2006.203.08:02:20.73#ibcon#about to write, iclass 3, count 0 2006.203.08:02:20.73#ibcon#wrote, iclass 3, count 0 2006.203.08:02:20.73#ibcon#about to read 3, iclass 3, count 0 2006.203.08:02:20.75#ibcon#read 3, iclass 3, count 0 2006.203.08:02:20.75#ibcon#about to read 4, iclass 3, count 0 2006.203.08:02:20.75#ibcon#read 4, iclass 3, count 0 2006.203.08:02:20.75#ibcon#about to read 5, iclass 3, count 0 2006.203.08:02:20.75#ibcon#read 5, iclass 3, count 0 2006.203.08:02:20.75#ibcon#about to read 6, iclass 3, count 0 2006.203.08:02:20.75#ibcon#read 6, iclass 3, count 0 2006.203.08:02:20.75#ibcon#end of sib2, iclass 3, count 0 2006.203.08:02:20.75#ibcon#*mode == 0, iclass 3, count 0 2006.203.08:02:20.75#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.203.08:02:20.75#ibcon#[25=USB\r\n] 2006.203.08:02:20.75#ibcon#*before write, iclass 3, count 0 2006.203.08:02:20.75#ibcon#enter sib2, iclass 3, count 0 2006.203.08:02:20.75#ibcon#flushed, iclass 3, count 0 2006.203.08:02:20.75#ibcon#about to write, iclass 3, count 0 2006.203.08:02:20.75#ibcon#wrote, iclass 3, count 0 2006.203.08:02:20.75#ibcon#about to read 3, iclass 3, count 0 2006.203.08:02:20.78#ibcon#read 3, iclass 3, count 0 2006.203.08:02:20.78#ibcon#about to read 4, iclass 3, count 0 2006.203.08:02:20.78#ibcon#read 4, iclass 3, count 0 2006.203.08:02:20.78#ibcon#about to read 5, iclass 3, count 0 2006.203.08:02:20.78#ibcon#read 5, iclass 3, count 0 2006.203.08:02:20.78#ibcon#about to read 6, iclass 3, count 0 2006.203.08:02:20.78#ibcon#read 6, iclass 3, count 0 2006.203.08:02:20.78#ibcon#end of sib2, iclass 3, count 0 2006.203.08:02:20.78#ibcon#*after write, iclass 3, count 0 2006.203.08:02:20.78#ibcon#*before return 0, iclass 3, count 0 2006.203.08:02:20.78#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.203.08:02:20.78#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.203.08:02:20.78#ibcon#about to clear, iclass 3 cls_cnt 0 2006.203.08:02:20.78#ibcon#cleared, iclass 3 cls_cnt 0 2006.203.08:02:20.78$vc4f8/valo=7,832.99 2006.203.08:02:20.78#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.203.08:02:20.78#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.203.08:02:20.78#ibcon#ireg 17 cls_cnt 0 2006.203.08:02:20.78#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.203.08:02:20.78#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.203.08:02:20.78#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.203.08:02:20.78#ibcon#enter wrdev, iclass 5, count 0 2006.203.08:02:20.78#ibcon#first serial, iclass 5, count 0 2006.203.08:02:20.78#ibcon#enter sib2, iclass 5, count 0 2006.203.08:02:20.78#ibcon#flushed, iclass 5, count 0 2006.203.08:02:20.78#ibcon#about to write, iclass 5, count 0 2006.203.08:02:20.78#ibcon#wrote, iclass 5, count 0 2006.203.08:02:20.78#ibcon#about to read 3, iclass 5, count 0 2006.203.08:02:20.80#ibcon#read 3, iclass 5, count 0 2006.203.08:02:20.80#ibcon#about to read 4, iclass 5, count 0 2006.203.08:02:20.80#ibcon#read 4, iclass 5, count 0 2006.203.08:02:20.80#ibcon#about to read 5, iclass 5, count 0 2006.203.08:02:20.80#ibcon#read 5, iclass 5, count 0 2006.203.08:02:20.80#ibcon#about to read 6, iclass 5, count 0 2006.203.08:02:20.80#ibcon#read 6, iclass 5, count 0 2006.203.08:02:20.80#ibcon#end of sib2, iclass 5, count 0 2006.203.08:02:20.80#ibcon#*mode == 0, iclass 5, count 0 2006.203.08:02:20.80#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.203.08:02:20.80#ibcon#[26=FRQ=07,832.99\r\n] 2006.203.08:02:20.80#ibcon#*before write, iclass 5, count 0 2006.203.08:02:20.80#ibcon#enter sib2, iclass 5, count 0 2006.203.08:02:20.80#ibcon#flushed, iclass 5, count 0 2006.203.08:02:20.80#ibcon#about to write, iclass 5, count 0 2006.203.08:02:20.80#ibcon#wrote, iclass 5, count 0 2006.203.08:02:20.80#ibcon#about to read 3, iclass 5, count 0 2006.203.08:02:20.84#ibcon#read 3, iclass 5, count 0 2006.203.08:02:20.84#ibcon#about to read 4, iclass 5, count 0 2006.203.08:02:20.84#ibcon#read 4, iclass 5, count 0 2006.203.08:02:20.84#ibcon#about to read 5, iclass 5, count 0 2006.203.08:02:20.84#ibcon#read 5, iclass 5, count 0 2006.203.08:02:20.84#ibcon#about to read 6, iclass 5, count 0 2006.203.08:02:20.84#ibcon#read 6, iclass 5, count 0 2006.203.08:02:20.84#ibcon#end of sib2, iclass 5, count 0 2006.203.08:02:20.84#ibcon#*after write, iclass 5, count 0 2006.203.08:02:20.84#ibcon#*before return 0, iclass 5, count 0 2006.203.08:02:20.84#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.203.08:02:20.84#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.203.08:02:20.84#ibcon#about to clear, iclass 5 cls_cnt 0 2006.203.08:02:20.84#ibcon#cleared, iclass 5 cls_cnt 0 2006.203.08:02:20.84$vc4f8/va=7,7 2006.203.08:02:20.84#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.203.08:02:20.84#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.203.08:02:20.84#ibcon#ireg 11 cls_cnt 2 2006.203.08:02:20.84#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.203.08:02:20.90#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.203.08:02:20.90#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.203.08:02:20.90#ibcon#enter wrdev, iclass 7, count 2 2006.203.08:02:20.90#ibcon#first serial, iclass 7, count 2 2006.203.08:02:20.90#ibcon#enter sib2, iclass 7, count 2 2006.203.08:02:20.90#ibcon#flushed, iclass 7, count 2 2006.203.08:02:20.90#ibcon#about to write, iclass 7, count 2 2006.203.08:02:20.90#ibcon#wrote, iclass 7, count 2 2006.203.08:02:20.90#ibcon#about to read 3, iclass 7, count 2 2006.203.08:02:20.92#ibcon#read 3, iclass 7, count 2 2006.203.08:02:20.92#ibcon#about to read 4, iclass 7, count 2 2006.203.08:02:20.92#ibcon#read 4, iclass 7, count 2 2006.203.08:02:20.92#ibcon#about to read 5, iclass 7, count 2 2006.203.08:02:20.92#ibcon#read 5, iclass 7, count 2 2006.203.08:02:20.92#ibcon#about to read 6, iclass 7, count 2 2006.203.08:02:20.92#ibcon#read 6, iclass 7, count 2 2006.203.08:02:20.92#ibcon#end of sib2, iclass 7, count 2 2006.203.08:02:20.92#ibcon#*mode == 0, iclass 7, count 2 2006.203.08:02:20.92#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.203.08:02:20.92#ibcon#[25=AT07-07\r\n] 2006.203.08:02:20.92#ibcon#*before write, iclass 7, count 2 2006.203.08:02:20.92#ibcon#enter sib2, iclass 7, count 2 2006.203.08:02:20.92#ibcon#flushed, iclass 7, count 2 2006.203.08:02:20.92#ibcon#about to write, iclass 7, count 2 2006.203.08:02:20.92#ibcon#wrote, iclass 7, count 2 2006.203.08:02:20.92#ibcon#about to read 3, iclass 7, count 2 2006.203.08:02:20.95#ibcon#read 3, iclass 7, count 2 2006.203.08:02:20.95#ibcon#about to read 4, iclass 7, count 2 2006.203.08:02:20.95#ibcon#read 4, iclass 7, count 2 2006.203.08:02:20.95#ibcon#about to read 5, iclass 7, count 2 2006.203.08:02:20.95#ibcon#read 5, iclass 7, count 2 2006.203.08:02:20.95#ibcon#about to read 6, iclass 7, count 2 2006.203.08:02:20.95#ibcon#read 6, iclass 7, count 2 2006.203.08:02:20.95#ibcon#end of sib2, iclass 7, count 2 2006.203.08:02:20.95#ibcon#*after write, iclass 7, count 2 2006.203.08:02:20.95#ibcon#*before return 0, iclass 7, count 2 2006.203.08:02:20.95#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.203.08:02:20.95#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.203.08:02:20.95#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.203.08:02:20.95#ibcon#ireg 7 cls_cnt 0 2006.203.08:02:20.95#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.203.08:02:21.07#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.203.08:02:21.07#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.203.08:02:21.07#ibcon#enter wrdev, iclass 7, count 0 2006.203.08:02:21.07#ibcon#first serial, iclass 7, count 0 2006.203.08:02:21.07#ibcon#enter sib2, iclass 7, count 0 2006.203.08:02:21.07#ibcon#flushed, iclass 7, count 0 2006.203.08:02:21.07#ibcon#about to write, iclass 7, count 0 2006.203.08:02:21.07#ibcon#wrote, iclass 7, count 0 2006.203.08:02:21.07#ibcon#about to read 3, iclass 7, count 0 2006.203.08:02:21.09#ibcon#read 3, iclass 7, count 0 2006.203.08:02:21.09#ibcon#about to read 4, iclass 7, count 0 2006.203.08:02:21.09#ibcon#read 4, iclass 7, count 0 2006.203.08:02:21.09#ibcon#about to read 5, iclass 7, count 0 2006.203.08:02:21.09#ibcon#read 5, iclass 7, count 0 2006.203.08:02:21.09#ibcon#about to read 6, iclass 7, count 0 2006.203.08:02:21.09#ibcon#read 6, iclass 7, count 0 2006.203.08:02:21.09#ibcon#end of sib2, iclass 7, count 0 2006.203.08:02:21.09#ibcon#*mode == 0, iclass 7, count 0 2006.203.08:02:21.09#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.203.08:02:21.09#ibcon#[25=USB\r\n] 2006.203.08:02:21.09#ibcon#*before write, iclass 7, count 0 2006.203.08:02:21.09#ibcon#enter sib2, iclass 7, count 0 2006.203.08:02:21.09#ibcon#flushed, iclass 7, count 0 2006.203.08:02:21.09#ibcon#about to write, iclass 7, count 0 2006.203.08:02:21.09#ibcon#wrote, iclass 7, count 0 2006.203.08:02:21.09#ibcon#about to read 3, iclass 7, count 0 2006.203.08:02:21.12#ibcon#read 3, iclass 7, count 0 2006.203.08:02:21.12#ibcon#about to read 4, iclass 7, count 0 2006.203.08:02:21.12#ibcon#read 4, iclass 7, count 0 2006.203.08:02:21.12#ibcon#about to read 5, iclass 7, count 0 2006.203.08:02:21.12#ibcon#read 5, iclass 7, count 0 2006.203.08:02:21.12#ibcon#about to read 6, iclass 7, count 0 2006.203.08:02:21.12#ibcon#read 6, iclass 7, count 0 2006.203.08:02:21.12#ibcon#end of sib2, iclass 7, count 0 2006.203.08:02:21.12#ibcon#*after write, iclass 7, count 0 2006.203.08:02:21.12#ibcon#*before return 0, iclass 7, count 0 2006.203.08:02:21.12#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.203.08:02:21.12#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.203.08:02:21.12#ibcon#about to clear, iclass 7 cls_cnt 0 2006.203.08:02:21.12#ibcon#cleared, iclass 7 cls_cnt 0 2006.203.08:02:21.12$vc4f8/valo=8,852.99 2006.203.08:02:21.12#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.203.08:02:21.12#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.203.08:02:21.12#ibcon#ireg 17 cls_cnt 0 2006.203.08:02:21.12#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.203.08:02:21.12#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.203.08:02:21.12#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.203.08:02:21.12#ibcon#enter wrdev, iclass 11, count 0 2006.203.08:02:21.12#ibcon#first serial, iclass 11, count 0 2006.203.08:02:21.12#ibcon#enter sib2, iclass 11, count 0 2006.203.08:02:21.12#ibcon#flushed, iclass 11, count 0 2006.203.08:02:21.12#ibcon#about to write, iclass 11, count 0 2006.203.08:02:21.12#ibcon#wrote, iclass 11, count 0 2006.203.08:02:21.12#ibcon#about to read 3, iclass 11, count 0 2006.203.08:02:21.14#ibcon#read 3, iclass 11, count 0 2006.203.08:02:21.14#ibcon#about to read 4, iclass 11, count 0 2006.203.08:02:21.14#ibcon#read 4, iclass 11, count 0 2006.203.08:02:21.14#ibcon#about to read 5, iclass 11, count 0 2006.203.08:02:21.14#ibcon#read 5, iclass 11, count 0 2006.203.08:02:21.14#ibcon#about to read 6, iclass 11, count 0 2006.203.08:02:21.14#ibcon#read 6, iclass 11, count 0 2006.203.08:02:21.14#ibcon#end of sib2, iclass 11, count 0 2006.203.08:02:21.14#ibcon#*mode == 0, iclass 11, count 0 2006.203.08:02:21.14#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.203.08:02:21.14#ibcon#[26=FRQ=08,852.99\r\n] 2006.203.08:02:21.14#ibcon#*before write, iclass 11, count 0 2006.203.08:02:21.14#ibcon#enter sib2, iclass 11, count 0 2006.203.08:02:21.14#ibcon#flushed, iclass 11, count 0 2006.203.08:02:21.14#ibcon#about to write, iclass 11, count 0 2006.203.08:02:21.14#ibcon#wrote, iclass 11, count 0 2006.203.08:02:21.14#ibcon#about to read 3, iclass 11, count 0 2006.203.08:02:21.18#ibcon#read 3, iclass 11, count 0 2006.203.08:02:21.18#ibcon#about to read 4, iclass 11, count 0 2006.203.08:02:21.18#ibcon#read 4, iclass 11, count 0 2006.203.08:02:21.18#ibcon#about to read 5, iclass 11, count 0 2006.203.08:02:21.18#ibcon#read 5, iclass 11, count 0 2006.203.08:02:21.18#ibcon#about to read 6, iclass 11, count 0 2006.203.08:02:21.18#ibcon#read 6, iclass 11, count 0 2006.203.08:02:21.18#ibcon#end of sib2, iclass 11, count 0 2006.203.08:02:21.18#ibcon#*after write, iclass 11, count 0 2006.203.08:02:21.18#ibcon#*before return 0, iclass 11, count 0 2006.203.08:02:21.18#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.203.08:02:21.18#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.203.08:02:21.18#ibcon#about to clear, iclass 11 cls_cnt 0 2006.203.08:02:21.18#ibcon#cleared, iclass 11 cls_cnt 0 2006.203.08:02:21.18$vc4f8/va=8,6 2006.203.08:02:21.18#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.203.08:02:21.18#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.203.08:02:21.18#ibcon#ireg 11 cls_cnt 2 2006.203.08:02:21.18#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.203.08:02:21.24#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.203.08:02:21.24#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.203.08:02:21.24#ibcon#enter wrdev, iclass 13, count 2 2006.203.08:02:21.24#ibcon#first serial, iclass 13, count 2 2006.203.08:02:21.24#ibcon#enter sib2, iclass 13, count 2 2006.203.08:02:21.24#ibcon#flushed, iclass 13, count 2 2006.203.08:02:21.24#ibcon#about to write, iclass 13, count 2 2006.203.08:02:21.24#ibcon#wrote, iclass 13, count 2 2006.203.08:02:21.24#ibcon#about to read 3, iclass 13, count 2 2006.203.08:02:21.26#ibcon#read 3, iclass 13, count 2 2006.203.08:02:21.26#ibcon#about to read 4, iclass 13, count 2 2006.203.08:02:21.26#ibcon#read 4, iclass 13, count 2 2006.203.08:02:21.26#ibcon#about to read 5, iclass 13, count 2 2006.203.08:02:21.26#ibcon#read 5, iclass 13, count 2 2006.203.08:02:21.26#ibcon#about to read 6, iclass 13, count 2 2006.203.08:02:21.26#ibcon#read 6, iclass 13, count 2 2006.203.08:02:21.26#ibcon#end of sib2, iclass 13, count 2 2006.203.08:02:21.26#ibcon#*mode == 0, iclass 13, count 2 2006.203.08:02:21.26#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.203.08:02:21.26#ibcon#[25=AT08-06\r\n] 2006.203.08:02:21.26#ibcon#*before write, iclass 13, count 2 2006.203.08:02:21.26#ibcon#enter sib2, iclass 13, count 2 2006.203.08:02:21.26#ibcon#flushed, iclass 13, count 2 2006.203.08:02:21.26#ibcon#about to write, iclass 13, count 2 2006.203.08:02:21.26#ibcon#wrote, iclass 13, count 2 2006.203.08:02:21.26#ibcon#about to read 3, iclass 13, count 2 2006.203.08:02:21.29#ibcon#read 3, iclass 13, count 2 2006.203.08:02:21.29#ibcon#about to read 4, iclass 13, count 2 2006.203.08:02:21.29#ibcon#read 4, iclass 13, count 2 2006.203.08:02:21.29#ibcon#about to read 5, iclass 13, count 2 2006.203.08:02:21.29#ibcon#read 5, iclass 13, count 2 2006.203.08:02:21.29#ibcon#about to read 6, iclass 13, count 2 2006.203.08:02:21.29#ibcon#read 6, iclass 13, count 2 2006.203.08:02:21.29#ibcon#end of sib2, iclass 13, count 2 2006.203.08:02:21.29#ibcon#*after write, iclass 13, count 2 2006.203.08:02:21.29#ibcon#*before return 0, iclass 13, count 2 2006.203.08:02:21.29#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.203.08:02:21.29#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.203.08:02:21.29#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.203.08:02:21.29#ibcon#ireg 7 cls_cnt 0 2006.203.08:02:21.29#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.203.08:02:21.41#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.203.08:02:21.41#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.203.08:02:21.41#ibcon#enter wrdev, iclass 13, count 0 2006.203.08:02:21.41#ibcon#first serial, iclass 13, count 0 2006.203.08:02:21.41#ibcon#enter sib2, iclass 13, count 0 2006.203.08:02:21.41#ibcon#flushed, iclass 13, count 0 2006.203.08:02:21.41#ibcon#about to write, iclass 13, count 0 2006.203.08:02:21.41#ibcon#wrote, iclass 13, count 0 2006.203.08:02:21.41#ibcon#about to read 3, iclass 13, count 0 2006.203.08:02:21.43#ibcon#read 3, iclass 13, count 0 2006.203.08:02:21.43#ibcon#about to read 4, iclass 13, count 0 2006.203.08:02:21.43#ibcon#read 4, iclass 13, count 0 2006.203.08:02:21.43#ibcon#about to read 5, iclass 13, count 0 2006.203.08:02:21.43#ibcon#read 5, iclass 13, count 0 2006.203.08:02:21.43#ibcon#about to read 6, iclass 13, count 0 2006.203.08:02:21.43#ibcon#read 6, iclass 13, count 0 2006.203.08:02:21.43#ibcon#end of sib2, iclass 13, count 0 2006.203.08:02:21.43#ibcon#*mode == 0, iclass 13, count 0 2006.203.08:02:21.43#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.203.08:02:21.43#ibcon#[25=USB\r\n] 2006.203.08:02:21.43#ibcon#*before write, iclass 13, count 0 2006.203.08:02:21.43#ibcon#enter sib2, iclass 13, count 0 2006.203.08:02:21.43#ibcon#flushed, iclass 13, count 0 2006.203.08:02:21.43#ibcon#about to write, iclass 13, count 0 2006.203.08:02:21.43#ibcon#wrote, iclass 13, count 0 2006.203.08:02:21.43#ibcon#about to read 3, iclass 13, count 0 2006.203.08:02:21.46#ibcon#read 3, iclass 13, count 0 2006.203.08:02:21.46#ibcon#about to read 4, iclass 13, count 0 2006.203.08:02:21.46#ibcon#read 4, iclass 13, count 0 2006.203.08:02:21.46#ibcon#about to read 5, iclass 13, count 0 2006.203.08:02:21.46#ibcon#read 5, iclass 13, count 0 2006.203.08:02:21.46#ibcon#about to read 6, iclass 13, count 0 2006.203.08:02:21.46#ibcon#read 6, iclass 13, count 0 2006.203.08:02:21.46#ibcon#end of sib2, iclass 13, count 0 2006.203.08:02:21.46#ibcon#*after write, iclass 13, count 0 2006.203.08:02:21.46#ibcon#*before return 0, iclass 13, count 0 2006.203.08:02:21.46#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.203.08:02:21.46#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.203.08:02:21.46#ibcon#about to clear, iclass 13 cls_cnt 0 2006.203.08:02:21.46#ibcon#cleared, iclass 13 cls_cnt 0 2006.203.08:02:21.46$vc4f8/vblo=1,632.99 2006.203.08:02:21.46#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.203.08:02:21.46#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.203.08:02:21.46#ibcon#ireg 17 cls_cnt 0 2006.203.08:02:21.46#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.203.08:02:21.46#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.203.08:02:21.46#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.203.08:02:21.46#ibcon#enter wrdev, iclass 15, count 0 2006.203.08:02:21.46#ibcon#first serial, iclass 15, count 0 2006.203.08:02:21.46#ibcon#enter sib2, iclass 15, count 0 2006.203.08:02:21.46#ibcon#flushed, iclass 15, count 0 2006.203.08:02:21.46#ibcon#about to write, iclass 15, count 0 2006.203.08:02:21.46#ibcon#wrote, iclass 15, count 0 2006.203.08:02:21.46#ibcon#about to read 3, iclass 15, count 0 2006.203.08:02:21.48#ibcon#read 3, iclass 15, count 0 2006.203.08:02:21.48#ibcon#about to read 4, iclass 15, count 0 2006.203.08:02:21.48#ibcon#read 4, iclass 15, count 0 2006.203.08:02:21.48#ibcon#about to read 5, iclass 15, count 0 2006.203.08:02:21.48#ibcon#read 5, iclass 15, count 0 2006.203.08:02:21.48#ibcon#about to read 6, iclass 15, count 0 2006.203.08:02:21.48#ibcon#read 6, iclass 15, count 0 2006.203.08:02:21.48#ibcon#end of sib2, iclass 15, count 0 2006.203.08:02:21.48#ibcon#*mode == 0, iclass 15, count 0 2006.203.08:02:21.48#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.203.08:02:21.48#ibcon#[28=FRQ=01,632.99\r\n] 2006.203.08:02:21.48#ibcon#*before write, iclass 15, count 0 2006.203.08:02:21.48#ibcon#enter sib2, iclass 15, count 0 2006.203.08:02:21.48#ibcon#flushed, iclass 15, count 0 2006.203.08:02:21.48#ibcon#about to write, iclass 15, count 0 2006.203.08:02:21.48#ibcon#wrote, iclass 15, count 0 2006.203.08:02:21.48#ibcon#about to read 3, iclass 15, count 0 2006.203.08:02:21.52#ibcon#read 3, iclass 15, count 0 2006.203.08:02:21.52#ibcon#about to read 4, iclass 15, count 0 2006.203.08:02:21.52#ibcon#read 4, iclass 15, count 0 2006.203.08:02:21.52#ibcon#about to read 5, iclass 15, count 0 2006.203.08:02:21.52#ibcon#read 5, iclass 15, count 0 2006.203.08:02:21.52#ibcon#about to read 6, iclass 15, count 0 2006.203.08:02:21.52#ibcon#read 6, iclass 15, count 0 2006.203.08:02:21.52#ibcon#end of sib2, iclass 15, count 0 2006.203.08:02:21.52#ibcon#*after write, iclass 15, count 0 2006.203.08:02:21.52#ibcon#*before return 0, iclass 15, count 0 2006.203.08:02:21.52#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.203.08:02:21.52#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.203.08:02:21.52#ibcon#about to clear, iclass 15 cls_cnt 0 2006.203.08:02:21.52#ibcon#cleared, iclass 15 cls_cnt 0 2006.203.08:02:21.52$vc4f8/vb=1,4 2006.203.08:02:21.52#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.203.08:02:21.52#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.203.08:02:21.52#ibcon#ireg 11 cls_cnt 2 2006.203.08:02:21.52#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.203.08:02:21.52#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.203.08:02:21.52#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.203.08:02:21.52#ibcon#enter wrdev, iclass 17, count 2 2006.203.08:02:21.52#ibcon#first serial, iclass 17, count 2 2006.203.08:02:21.52#ibcon#enter sib2, iclass 17, count 2 2006.203.08:02:21.52#ibcon#flushed, iclass 17, count 2 2006.203.08:02:21.52#ibcon#about to write, iclass 17, count 2 2006.203.08:02:21.52#ibcon#wrote, iclass 17, count 2 2006.203.08:02:21.52#ibcon#about to read 3, iclass 17, count 2 2006.203.08:02:21.54#ibcon#read 3, iclass 17, count 2 2006.203.08:02:21.54#ibcon#about to read 4, iclass 17, count 2 2006.203.08:02:21.54#ibcon#read 4, iclass 17, count 2 2006.203.08:02:21.54#ibcon#about to read 5, iclass 17, count 2 2006.203.08:02:21.54#ibcon#read 5, iclass 17, count 2 2006.203.08:02:21.54#ibcon#about to read 6, iclass 17, count 2 2006.203.08:02:21.54#ibcon#read 6, iclass 17, count 2 2006.203.08:02:21.54#ibcon#end of sib2, iclass 17, count 2 2006.203.08:02:21.54#ibcon#*mode == 0, iclass 17, count 2 2006.203.08:02:21.54#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.203.08:02:21.54#ibcon#[27=AT01-04\r\n] 2006.203.08:02:21.54#ibcon#*before write, iclass 17, count 2 2006.203.08:02:21.54#ibcon#enter sib2, iclass 17, count 2 2006.203.08:02:21.54#ibcon#flushed, iclass 17, count 2 2006.203.08:02:21.54#ibcon#about to write, iclass 17, count 2 2006.203.08:02:21.54#ibcon#wrote, iclass 17, count 2 2006.203.08:02:21.54#ibcon#about to read 3, iclass 17, count 2 2006.203.08:02:21.57#ibcon#read 3, iclass 17, count 2 2006.203.08:02:21.57#ibcon#about to read 4, iclass 17, count 2 2006.203.08:02:21.57#ibcon#read 4, iclass 17, count 2 2006.203.08:02:21.57#ibcon#about to read 5, iclass 17, count 2 2006.203.08:02:21.57#ibcon#read 5, iclass 17, count 2 2006.203.08:02:21.57#ibcon#about to read 6, iclass 17, count 2 2006.203.08:02:21.57#ibcon#read 6, iclass 17, count 2 2006.203.08:02:21.57#ibcon#end of sib2, iclass 17, count 2 2006.203.08:02:21.57#ibcon#*after write, iclass 17, count 2 2006.203.08:02:21.57#ibcon#*before return 0, iclass 17, count 2 2006.203.08:02:21.57#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.203.08:02:21.57#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.203.08:02:21.57#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.203.08:02:21.57#ibcon#ireg 7 cls_cnt 0 2006.203.08:02:21.57#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.203.08:02:21.69#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.203.08:02:21.69#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.203.08:02:21.69#ibcon#enter wrdev, iclass 17, count 0 2006.203.08:02:21.69#ibcon#first serial, iclass 17, count 0 2006.203.08:02:21.69#ibcon#enter sib2, iclass 17, count 0 2006.203.08:02:21.69#ibcon#flushed, iclass 17, count 0 2006.203.08:02:21.69#ibcon#about to write, iclass 17, count 0 2006.203.08:02:21.69#ibcon#wrote, iclass 17, count 0 2006.203.08:02:21.69#ibcon#about to read 3, iclass 17, count 0 2006.203.08:02:21.71#ibcon#read 3, iclass 17, count 0 2006.203.08:02:21.71#ibcon#about to read 4, iclass 17, count 0 2006.203.08:02:21.71#ibcon#read 4, iclass 17, count 0 2006.203.08:02:21.71#ibcon#about to read 5, iclass 17, count 0 2006.203.08:02:21.71#ibcon#read 5, iclass 17, count 0 2006.203.08:02:21.71#ibcon#about to read 6, iclass 17, count 0 2006.203.08:02:21.71#ibcon#read 6, iclass 17, count 0 2006.203.08:02:21.71#ibcon#end of sib2, iclass 17, count 0 2006.203.08:02:21.71#ibcon#*mode == 0, iclass 17, count 0 2006.203.08:02:21.71#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.203.08:02:21.71#ibcon#[27=USB\r\n] 2006.203.08:02:21.71#ibcon#*before write, iclass 17, count 0 2006.203.08:02:21.71#ibcon#enter sib2, iclass 17, count 0 2006.203.08:02:21.71#ibcon#flushed, iclass 17, count 0 2006.203.08:02:21.71#ibcon#about to write, iclass 17, count 0 2006.203.08:02:21.71#ibcon#wrote, iclass 17, count 0 2006.203.08:02:21.71#ibcon#about to read 3, iclass 17, count 0 2006.203.08:02:21.74#ibcon#read 3, iclass 17, count 0 2006.203.08:02:21.74#ibcon#about to read 4, iclass 17, count 0 2006.203.08:02:21.74#ibcon#read 4, iclass 17, count 0 2006.203.08:02:21.74#ibcon#about to read 5, iclass 17, count 0 2006.203.08:02:21.74#ibcon#read 5, iclass 17, count 0 2006.203.08:02:21.74#ibcon#about to read 6, iclass 17, count 0 2006.203.08:02:21.74#ibcon#read 6, iclass 17, count 0 2006.203.08:02:21.74#ibcon#end of sib2, iclass 17, count 0 2006.203.08:02:21.74#ibcon#*after write, iclass 17, count 0 2006.203.08:02:21.74#ibcon#*before return 0, iclass 17, count 0 2006.203.08:02:21.74#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.203.08:02:21.74#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.203.08:02:21.74#ibcon#about to clear, iclass 17 cls_cnt 0 2006.203.08:02:21.74#ibcon#cleared, iclass 17 cls_cnt 0 2006.203.08:02:21.74$vc4f8/vblo=2,640.99 2006.203.08:02:21.74#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.203.08:02:21.74#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.203.08:02:21.74#ibcon#ireg 17 cls_cnt 0 2006.203.08:02:21.74#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.203.08:02:21.74#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.203.08:02:21.74#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.203.08:02:21.74#ibcon#enter wrdev, iclass 19, count 0 2006.203.08:02:21.74#ibcon#first serial, iclass 19, count 0 2006.203.08:02:21.74#ibcon#enter sib2, iclass 19, count 0 2006.203.08:02:21.74#ibcon#flushed, iclass 19, count 0 2006.203.08:02:21.74#ibcon#about to write, iclass 19, count 0 2006.203.08:02:21.74#ibcon#wrote, iclass 19, count 0 2006.203.08:02:21.74#ibcon#about to read 3, iclass 19, count 0 2006.203.08:02:21.76#ibcon#read 3, iclass 19, count 0 2006.203.08:02:21.76#ibcon#about to read 4, iclass 19, count 0 2006.203.08:02:21.76#ibcon#read 4, iclass 19, count 0 2006.203.08:02:21.76#ibcon#about to read 5, iclass 19, count 0 2006.203.08:02:21.76#ibcon#read 5, iclass 19, count 0 2006.203.08:02:21.76#ibcon#about to read 6, iclass 19, count 0 2006.203.08:02:21.76#ibcon#read 6, iclass 19, count 0 2006.203.08:02:21.76#ibcon#end of sib2, iclass 19, count 0 2006.203.08:02:21.76#ibcon#*mode == 0, iclass 19, count 0 2006.203.08:02:21.76#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.203.08:02:21.76#ibcon#[28=FRQ=02,640.99\r\n] 2006.203.08:02:21.76#ibcon#*before write, iclass 19, count 0 2006.203.08:02:21.76#ibcon#enter sib2, iclass 19, count 0 2006.203.08:02:21.76#ibcon#flushed, iclass 19, count 0 2006.203.08:02:21.76#ibcon#about to write, iclass 19, count 0 2006.203.08:02:21.76#ibcon#wrote, iclass 19, count 0 2006.203.08:02:21.76#ibcon#about to read 3, iclass 19, count 0 2006.203.08:02:21.80#ibcon#read 3, iclass 19, count 0 2006.203.08:02:21.80#ibcon#about to read 4, iclass 19, count 0 2006.203.08:02:21.80#ibcon#read 4, iclass 19, count 0 2006.203.08:02:21.80#ibcon#about to read 5, iclass 19, count 0 2006.203.08:02:21.80#ibcon#read 5, iclass 19, count 0 2006.203.08:02:21.80#ibcon#about to read 6, iclass 19, count 0 2006.203.08:02:21.80#ibcon#read 6, iclass 19, count 0 2006.203.08:02:21.80#ibcon#end of sib2, iclass 19, count 0 2006.203.08:02:21.80#ibcon#*after write, iclass 19, count 0 2006.203.08:02:21.80#ibcon#*before return 0, iclass 19, count 0 2006.203.08:02:21.80#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.203.08:02:21.80#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.203.08:02:21.80#ibcon#about to clear, iclass 19 cls_cnt 0 2006.203.08:02:21.80#ibcon#cleared, iclass 19 cls_cnt 0 2006.203.08:02:21.80$vc4f8/vb=2,4 2006.203.08:02:21.80#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.203.08:02:21.80#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.203.08:02:21.80#ibcon#ireg 11 cls_cnt 2 2006.203.08:02:21.80#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.203.08:02:21.86#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.203.08:02:21.86#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.203.08:02:21.86#ibcon#enter wrdev, iclass 21, count 2 2006.203.08:02:21.86#ibcon#first serial, iclass 21, count 2 2006.203.08:02:21.86#ibcon#enter sib2, iclass 21, count 2 2006.203.08:02:21.86#ibcon#flushed, iclass 21, count 2 2006.203.08:02:21.86#ibcon#about to write, iclass 21, count 2 2006.203.08:02:21.86#ibcon#wrote, iclass 21, count 2 2006.203.08:02:21.86#ibcon#about to read 3, iclass 21, count 2 2006.203.08:02:21.88#ibcon#read 3, iclass 21, count 2 2006.203.08:02:21.88#ibcon#about to read 4, iclass 21, count 2 2006.203.08:02:21.88#ibcon#read 4, iclass 21, count 2 2006.203.08:02:21.88#ibcon#about to read 5, iclass 21, count 2 2006.203.08:02:21.88#ibcon#read 5, iclass 21, count 2 2006.203.08:02:21.88#ibcon#about to read 6, iclass 21, count 2 2006.203.08:02:21.88#ibcon#read 6, iclass 21, count 2 2006.203.08:02:21.88#ibcon#end of sib2, iclass 21, count 2 2006.203.08:02:21.88#ibcon#*mode == 0, iclass 21, count 2 2006.203.08:02:21.88#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.203.08:02:21.88#ibcon#[27=AT02-04\r\n] 2006.203.08:02:21.88#ibcon#*before write, iclass 21, count 2 2006.203.08:02:21.88#ibcon#enter sib2, iclass 21, count 2 2006.203.08:02:21.88#ibcon#flushed, iclass 21, count 2 2006.203.08:02:21.88#ibcon#about to write, iclass 21, count 2 2006.203.08:02:21.88#ibcon#wrote, iclass 21, count 2 2006.203.08:02:21.88#ibcon#about to read 3, iclass 21, count 2 2006.203.08:02:21.91#ibcon#read 3, iclass 21, count 2 2006.203.08:02:21.91#ibcon#about to read 4, iclass 21, count 2 2006.203.08:02:21.91#ibcon#read 4, iclass 21, count 2 2006.203.08:02:21.91#ibcon#about to read 5, iclass 21, count 2 2006.203.08:02:21.91#ibcon#read 5, iclass 21, count 2 2006.203.08:02:21.91#ibcon#about to read 6, iclass 21, count 2 2006.203.08:02:21.91#ibcon#read 6, iclass 21, count 2 2006.203.08:02:21.91#ibcon#end of sib2, iclass 21, count 2 2006.203.08:02:21.91#ibcon#*after write, iclass 21, count 2 2006.203.08:02:21.91#ibcon#*before return 0, iclass 21, count 2 2006.203.08:02:21.91#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.203.08:02:21.91#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.203.08:02:21.91#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.203.08:02:21.91#ibcon#ireg 7 cls_cnt 0 2006.203.08:02:21.91#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.203.08:02:22.03#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.203.08:02:22.03#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.203.08:02:22.03#ibcon#enter wrdev, iclass 21, count 0 2006.203.08:02:22.03#ibcon#first serial, iclass 21, count 0 2006.203.08:02:22.03#ibcon#enter sib2, iclass 21, count 0 2006.203.08:02:22.03#ibcon#flushed, iclass 21, count 0 2006.203.08:02:22.03#ibcon#about to write, iclass 21, count 0 2006.203.08:02:22.03#ibcon#wrote, iclass 21, count 0 2006.203.08:02:22.03#ibcon#about to read 3, iclass 21, count 0 2006.203.08:02:22.05#ibcon#read 3, iclass 21, count 0 2006.203.08:02:22.05#ibcon#about to read 4, iclass 21, count 0 2006.203.08:02:22.05#ibcon#read 4, iclass 21, count 0 2006.203.08:02:22.05#ibcon#about to read 5, iclass 21, count 0 2006.203.08:02:22.05#ibcon#read 5, iclass 21, count 0 2006.203.08:02:22.05#ibcon#about to read 6, iclass 21, count 0 2006.203.08:02:22.05#ibcon#read 6, iclass 21, count 0 2006.203.08:02:22.05#ibcon#end of sib2, iclass 21, count 0 2006.203.08:02:22.05#ibcon#*mode == 0, iclass 21, count 0 2006.203.08:02:22.05#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.203.08:02:22.05#ibcon#[27=USB\r\n] 2006.203.08:02:22.05#ibcon#*before write, iclass 21, count 0 2006.203.08:02:22.05#ibcon#enter sib2, iclass 21, count 0 2006.203.08:02:22.05#ibcon#flushed, iclass 21, count 0 2006.203.08:02:22.05#ibcon#about to write, iclass 21, count 0 2006.203.08:02:22.05#ibcon#wrote, iclass 21, count 0 2006.203.08:02:22.05#ibcon#about to read 3, iclass 21, count 0 2006.203.08:02:22.08#ibcon#read 3, iclass 21, count 0 2006.203.08:02:22.08#ibcon#about to read 4, iclass 21, count 0 2006.203.08:02:22.08#ibcon#read 4, iclass 21, count 0 2006.203.08:02:22.08#ibcon#about to read 5, iclass 21, count 0 2006.203.08:02:22.08#ibcon#read 5, iclass 21, count 0 2006.203.08:02:22.08#ibcon#about to read 6, iclass 21, count 0 2006.203.08:02:22.08#ibcon#read 6, iclass 21, count 0 2006.203.08:02:22.08#ibcon#end of sib2, iclass 21, count 0 2006.203.08:02:22.08#ibcon#*after write, iclass 21, count 0 2006.203.08:02:22.08#ibcon#*before return 0, iclass 21, count 0 2006.203.08:02:22.08#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.203.08:02:22.08#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.203.08:02:22.08#ibcon#about to clear, iclass 21 cls_cnt 0 2006.203.08:02:22.08#ibcon#cleared, iclass 21 cls_cnt 0 2006.203.08:02:22.08$vc4f8/vblo=3,656.99 2006.203.08:02:22.08#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.203.08:02:22.08#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.203.08:02:22.08#ibcon#ireg 17 cls_cnt 0 2006.203.08:02:22.08#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.203.08:02:22.08#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.203.08:02:22.08#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.203.08:02:22.08#ibcon#enter wrdev, iclass 23, count 0 2006.203.08:02:22.08#ibcon#first serial, iclass 23, count 0 2006.203.08:02:22.08#ibcon#enter sib2, iclass 23, count 0 2006.203.08:02:22.08#ibcon#flushed, iclass 23, count 0 2006.203.08:02:22.08#ibcon#about to write, iclass 23, count 0 2006.203.08:02:22.08#ibcon#wrote, iclass 23, count 0 2006.203.08:02:22.08#ibcon#about to read 3, iclass 23, count 0 2006.203.08:02:22.10#ibcon#read 3, iclass 23, count 0 2006.203.08:02:22.10#ibcon#about to read 4, iclass 23, count 0 2006.203.08:02:22.10#ibcon#read 4, iclass 23, count 0 2006.203.08:02:22.10#ibcon#about to read 5, iclass 23, count 0 2006.203.08:02:22.10#ibcon#read 5, iclass 23, count 0 2006.203.08:02:22.10#ibcon#about to read 6, iclass 23, count 0 2006.203.08:02:22.10#ibcon#read 6, iclass 23, count 0 2006.203.08:02:22.10#ibcon#end of sib2, iclass 23, count 0 2006.203.08:02:22.10#ibcon#*mode == 0, iclass 23, count 0 2006.203.08:02:22.10#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.203.08:02:22.10#ibcon#[28=FRQ=03,656.99\r\n] 2006.203.08:02:22.10#ibcon#*before write, iclass 23, count 0 2006.203.08:02:22.10#ibcon#enter sib2, iclass 23, count 0 2006.203.08:02:22.10#ibcon#flushed, iclass 23, count 0 2006.203.08:02:22.10#ibcon#about to write, iclass 23, count 0 2006.203.08:02:22.10#ibcon#wrote, iclass 23, count 0 2006.203.08:02:22.10#ibcon#about to read 3, iclass 23, count 0 2006.203.08:02:22.14#ibcon#read 3, iclass 23, count 0 2006.203.08:02:22.14#ibcon#about to read 4, iclass 23, count 0 2006.203.08:02:22.14#ibcon#read 4, iclass 23, count 0 2006.203.08:02:22.14#ibcon#about to read 5, iclass 23, count 0 2006.203.08:02:22.14#ibcon#read 5, iclass 23, count 0 2006.203.08:02:22.14#ibcon#about to read 6, iclass 23, count 0 2006.203.08:02:22.14#ibcon#read 6, iclass 23, count 0 2006.203.08:02:22.14#ibcon#end of sib2, iclass 23, count 0 2006.203.08:02:22.14#ibcon#*after write, iclass 23, count 0 2006.203.08:02:22.14#ibcon#*before return 0, iclass 23, count 0 2006.203.08:02:22.14#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.203.08:02:22.14#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.203.08:02:22.14#ibcon#about to clear, iclass 23 cls_cnt 0 2006.203.08:02:22.14#ibcon#cleared, iclass 23 cls_cnt 0 2006.203.08:02:22.14$vc4f8/vb=3,4 2006.203.08:02:22.14#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.203.08:02:22.14#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.203.08:02:22.14#ibcon#ireg 11 cls_cnt 2 2006.203.08:02:22.14#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.203.08:02:22.20#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.203.08:02:22.20#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.203.08:02:22.20#ibcon#enter wrdev, iclass 25, count 2 2006.203.08:02:22.20#ibcon#first serial, iclass 25, count 2 2006.203.08:02:22.20#ibcon#enter sib2, iclass 25, count 2 2006.203.08:02:22.20#ibcon#flushed, iclass 25, count 2 2006.203.08:02:22.20#ibcon#about to write, iclass 25, count 2 2006.203.08:02:22.20#ibcon#wrote, iclass 25, count 2 2006.203.08:02:22.20#ibcon#about to read 3, iclass 25, count 2 2006.203.08:02:22.22#ibcon#read 3, iclass 25, count 2 2006.203.08:02:22.22#ibcon#about to read 4, iclass 25, count 2 2006.203.08:02:22.22#ibcon#read 4, iclass 25, count 2 2006.203.08:02:22.22#ibcon#about to read 5, iclass 25, count 2 2006.203.08:02:22.22#ibcon#read 5, iclass 25, count 2 2006.203.08:02:22.22#ibcon#about to read 6, iclass 25, count 2 2006.203.08:02:22.22#ibcon#read 6, iclass 25, count 2 2006.203.08:02:22.22#ibcon#end of sib2, iclass 25, count 2 2006.203.08:02:22.22#ibcon#*mode == 0, iclass 25, count 2 2006.203.08:02:22.22#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.203.08:02:22.22#ibcon#[27=AT03-04\r\n] 2006.203.08:02:22.22#ibcon#*before write, iclass 25, count 2 2006.203.08:02:22.22#ibcon#enter sib2, iclass 25, count 2 2006.203.08:02:22.22#ibcon#flushed, iclass 25, count 2 2006.203.08:02:22.22#ibcon#about to write, iclass 25, count 2 2006.203.08:02:22.22#ibcon#wrote, iclass 25, count 2 2006.203.08:02:22.22#ibcon#about to read 3, iclass 25, count 2 2006.203.08:02:22.25#ibcon#read 3, iclass 25, count 2 2006.203.08:02:22.25#ibcon#about to read 4, iclass 25, count 2 2006.203.08:02:22.25#ibcon#read 4, iclass 25, count 2 2006.203.08:02:22.25#ibcon#about to read 5, iclass 25, count 2 2006.203.08:02:22.25#ibcon#read 5, iclass 25, count 2 2006.203.08:02:22.25#ibcon#about to read 6, iclass 25, count 2 2006.203.08:02:22.25#ibcon#read 6, iclass 25, count 2 2006.203.08:02:22.25#ibcon#end of sib2, iclass 25, count 2 2006.203.08:02:22.25#ibcon#*after write, iclass 25, count 2 2006.203.08:02:22.25#ibcon#*before return 0, iclass 25, count 2 2006.203.08:02:22.25#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.203.08:02:22.25#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.203.08:02:22.25#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.203.08:02:22.25#ibcon#ireg 7 cls_cnt 0 2006.203.08:02:22.25#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.203.08:02:22.37#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.203.08:02:22.37#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.203.08:02:22.37#ibcon#enter wrdev, iclass 25, count 0 2006.203.08:02:22.37#ibcon#first serial, iclass 25, count 0 2006.203.08:02:22.37#ibcon#enter sib2, iclass 25, count 0 2006.203.08:02:22.37#ibcon#flushed, iclass 25, count 0 2006.203.08:02:22.37#ibcon#about to write, iclass 25, count 0 2006.203.08:02:22.37#ibcon#wrote, iclass 25, count 0 2006.203.08:02:22.37#ibcon#about to read 3, iclass 25, count 0 2006.203.08:02:22.39#ibcon#read 3, iclass 25, count 0 2006.203.08:02:22.39#ibcon#about to read 4, iclass 25, count 0 2006.203.08:02:22.39#ibcon#read 4, iclass 25, count 0 2006.203.08:02:22.39#ibcon#about to read 5, iclass 25, count 0 2006.203.08:02:22.39#ibcon#read 5, iclass 25, count 0 2006.203.08:02:22.39#ibcon#about to read 6, iclass 25, count 0 2006.203.08:02:22.39#ibcon#read 6, iclass 25, count 0 2006.203.08:02:22.39#ibcon#end of sib2, iclass 25, count 0 2006.203.08:02:22.39#ibcon#*mode == 0, iclass 25, count 0 2006.203.08:02:22.39#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.203.08:02:22.39#ibcon#[27=USB\r\n] 2006.203.08:02:22.39#ibcon#*before write, iclass 25, count 0 2006.203.08:02:22.39#ibcon#enter sib2, iclass 25, count 0 2006.203.08:02:22.39#ibcon#flushed, iclass 25, count 0 2006.203.08:02:22.39#ibcon#about to write, iclass 25, count 0 2006.203.08:02:22.39#ibcon#wrote, iclass 25, count 0 2006.203.08:02:22.39#ibcon#about to read 3, iclass 25, count 0 2006.203.08:02:22.42#ibcon#read 3, iclass 25, count 0 2006.203.08:02:22.42#ibcon#about to read 4, iclass 25, count 0 2006.203.08:02:22.42#ibcon#read 4, iclass 25, count 0 2006.203.08:02:22.42#ibcon#about to read 5, iclass 25, count 0 2006.203.08:02:22.42#ibcon#read 5, iclass 25, count 0 2006.203.08:02:22.42#ibcon#about to read 6, iclass 25, count 0 2006.203.08:02:22.42#ibcon#read 6, iclass 25, count 0 2006.203.08:02:22.42#ibcon#end of sib2, iclass 25, count 0 2006.203.08:02:22.42#ibcon#*after write, iclass 25, count 0 2006.203.08:02:22.42#ibcon#*before return 0, iclass 25, count 0 2006.203.08:02:22.42#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.203.08:02:22.42#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.203.08:02:22.42#ibcon#about to clear, iclass 25 cls_cnt 0 2006.203.08:02:22.42#ibcon#cleared, iclass 25 cls_cnt 0 2006.203.08:02:22.42$vc4f8/vblo=4,712.99 2006.203.08:02:22.42#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.203.08:02:22.42#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.203.08:02:22.42#ibcon#ireg 17 cls_cnt 0 2006.203.08:02:22.42#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.203.08:02:22.42#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.203.08:02:22.42#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.203.08:02:22.42#ibcon#enter wrdev, iclass 27, count 0 2006.203.08:02:22.42#ibcon#first serial, iclass 27, count 0 2006.203.08:02:22.42#ibcon#enter sib2, iclass 27, count 0 2006.203.08:02:22.42#ibcon#flushed, iclass 27, count 0 2006.203.08:02:22.42#ibcon#about to write, iclass 27, count 0 2006.203.08:02:22.42#ibcon#wrote, iclass 27, count 0 2006.203.08:02:22.42#ibcon#about to read 3, iclass 27, count 0 2006.203.08:02:22.44#ibcon#read 3, iclass 27, count 0 2006.203.08:02:22.44#ibcon#about to read 4, iclass 27, count 0 2006.203.08:02:22.44#ibcon#read 4, iclass 27, count 0 2006.203.08:02:22.44#ibcon#about to read 5, iclass 27, count 0 2006.203.08:02:22.44#ibcon#read 5, iclass 27, count 0 2006.203.08:02:22.44#ibcon#about to read 6, iclass 27, count 0 2006.203.08:02:22.44#ibcon#read 6, iclass 27, count 0 2006.203.08:02:22.44#ibcon#end of sib2, iclass 27, count 0 2006.203.08:02:22.44#ibcon#*mode == 0, iclass 27, count 0 2006.203.08:02:22.44#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.203.08:02:22.44#ibcon#[28=FRQ=04,712.99\r\n] 2006.203.08:02:22.44#ibcon#*before write, iclass 27, count 0 2006.203.08:02:22.44#ibcon#enter sib2, iclass 27, count 0 2006.203.08:02:22.44#ibcon#flushed, iclass 27, count 0 2006.203.08:02:22.44#ibcon#about to write, iclass 27, count 0 2006.203.08:02:22.44#ibcon#wrote, iclass 27, count 0 2006.203.08:02:22.44#ibcon#about to read 3, iclass 27, count 0 2006.203.08:02:22.48#ibcon#read 3, iclass 27, count 0 2006.203.08:02:22.48#ibcon#about to read 4, iclass 27, count 0 2006.203.08:02:22.48#ibcon#read 4, iclass 27, count 0 2006.203.08:02:22.48#ibcon#about to read 5, iclass 27, count 0 2006.203.08:02:22.48#ibcon#read 5, iclass 27, count 0 2006.203.08:02:22.48#ibcon#about to read 6, iclass 27, count 0 2006.203.08:02:22.48#ibcon#read 6, iclass 27, count 0 2006.203.08:02:22.48#ibcon#end of sib2, iclass 27, count 0 2006.203.08:02:22.48#ibcon#*after write, iclass 27, count 0 2006.203.08:02:22.48#ibcon#*before return 0, iclass 27, count 0 2006.203.08:02:22.48#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.203.08:02:22.48#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.203.08:02:22.48#ibcon#about to clear, iclass 27 cls_cnt 0 2006.203.08:02:22.48#ibcon#cleared, iclass 27 cls_cnt 0 2006.203.08:02:22.48$vc4f8/vb=4,4 2006.203.08:02:22.48#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.203.08:02:22.48#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.203.08:02:22.48#ibcon#ireg 11 cls_cnt 2 2006.203.08:02:22.48#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.203.08:02:22.54#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.203.08:02:22.54#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.203.08:02:22.54#ibcon#enter wrdev, iclass 29, count 2 2006.203.08:02:22.54#ibcon#first serial, iclass 29, count 2 2006.203.08:02:22.54#ibcon#enter sib2, iclass 29, count 2 2006.203.08:02:22.54#ibcon#flushed, iclass 29, count 2 2006.203.08:02:22.54#ibcon#about to write, iclass 29, count 2 2006.203.08:02:22.54#ibcon#wrote, iclass 29, count 2 2006.203.08:02:22.54#ibcon#about to read 3, iclass 29, count 2 2006.203.08:02:22.56#ibcon#read 3, iclass 29, count 2 2006.203.08:02:22.56#ibcon#about to read 4, iclass 29, count 2 2006.203.08:02:22.56#ibcon#read 4, iclass 29, count 2 2006.203.08:02:22.56#ibcon#about to read 5, iclass 29, count 2 2006.203.08:02:22.56#ibcon#read 5, iclass 29, count 2 2006.203.08:02:22.56#ibcon#about to read 6, iclass 29, count 2 2006.203.08:02:22.56#ibcon#read 6, iclass 29, count 2 2006.203.08:02:22.56#ibcon#end of sib2, iclass 29, count 2 2006.203.08:02:22.56#ibcon#*mode == 0, iclass 29, count 2 2006.203.08:02:22.56#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.203.08:02:22.56#ibcon#[27=AT04-04\r\n] 2006.203.08:02:22.56#ibcon#*before write, iclass 29, count 2 2006.203.08:02:22.56#ibcon#enter sib2, iclass 29, count 2 2006.203.08:02:22.56#ibcon#flushed, iclass 29, count 2 2006.203.08:02:22.56#ibcon#about to write, iclass 29, count 2 2006.203.08:02:22.56#ibcon#wrote, iclass 29, count 2 2006.203.08:02:22.56#ibcon#about to read 3, iclass 29, count 2 2006.203.08:02:22.59#ibcon#read 3, iclass 29, count 2 2006.203.08:02:22.59#ibcon#about to read 4, iclass 29, count 2 2006.203.08:02:22.59#ibcon#read 4, iclass 29, count 2 2006.203.08:02:22.59#ibcon#about to read 5, iclass 29, count 2 2006.203.08:02:22.59#ibcon#read 5, iclass 29, count 2 2006.203.08:02:22.59#ibcon#about to read 6, iclass 29, count 2 2006.203.08:02:22.59#ibcon#read 6, iclass 29, count 2 2006.203.08:02:22.59#ibcon#end of sib2, iclass 29, count 2 2006.203.08:02:22.59#ibcon#*after write, iclass 29, count 2 2006.203.08:02:22.59#ibcon#*before return 0, iclass 29, count 2 2006.203.08:02:22.59#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.203.08:02:22.59#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.203.08:02:22.59#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.203.08:02:22.59#ibcon#ireg 7 cls_cnt 0 2006.203.08:02:22.59#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.203.08:02:22.71#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.203.08:02:22.71#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.203.08:02:22.71#ibcon#enter wrdev, iclass 29, count 0 2006.203.08:02:22.71#ibcon#first serial, iclass 29, count 0 2006.203.08:02:22.71#ibcon#enter sib2, iclass 29, count 0 2006.203.08:02:22.71#ibcon#flushed, iclass 29, count 0 2006.203.08:02:22.71#ibcon#about to write, iclass 29, count 0 2006.203.08:02:22.71#ibcon#wrote, iclass 29, count 0 2006.203.08:02:22.71#ibcon#about to read 3, iclass 29, count 0 2006.203.08:02:22.73#ibcon#read 3, iclass 29, count 0 2006.203.08:02:22.73#ibcon#about to read 4, iclass 29, count 0 2006.203.08:02:22.73#ibcon#read 4, iclass 29, count 0 2006.203.08:02:22.73#ibcon#about to read 5, iclass 29, count 0 2006.203.08:02:22.73#ibcon#read 5, iclass 29, count 0 2006.203.08:02:22.73#ibcon#about to read 6, iclass 29, count 0 2006.203.08:02:22.73#ibcon#read 6, iclass 29, count 0 2006.203.08:02:22.73#ibcon#end of sib2, iclass 29, count 0 2006.203.08:02:22.73#ibcon#*mode == 0, iclass 29, count 0 2006.203.08:02:22.73#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.203.08:02:22.73#ibcon#[27=USB\r\n] 2006.203.08:02:22.73#ibcon#*before write, iclass 29, count 0 2006.203.08:02:22.73#ibcon#enter sib2, iclass 29, count 0 2006.203.08:02:22.73#ibcon#flushed, iclass 29, count 0 2006.203.08:02:22.73#ibcon#about to write, iclass 29, count 0 2006.203.08:02:22.73#ibcon#wrote, iclass 29, count 0 2006.203.08:02:22.73#ibcon#about to read 3, iclass 29, count 0 2006.203.08:02:22.76#ibcon#read 3, iclass 29, count 0 2006.203.08:02:22.76#ibcon#about to read 4, iclass 29, count 0 2006.203.08:02:22.76#ibcon#read 4, iclass 29, count 0 2006.203.08:02:22.76#ibcon#about to read 5, iclass 29, count 0 2006.203.08:02:22.76#ibcon#read 5, iclass 29, count 0 2006.203.08:02:22.76#ibcon#about to read 6, iclass 29, count 0 2006.203.08:02:22.76#ibcon#read 6, iclass 29, count 0 2006.203.08:02:22.76#ibcon#end of sib2, iclass 29, count 0 2006.203.08:02:22.76#ibcon#*after write, iclass 29, count 0 2006.203.08:02:22.76#ibcon#*before return 0, iclass 29, count 0 2006.203.08:02:22.76#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.203.08:02:22.76#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.203.08:02:22.76#ibcon#about to clear, iclass 29 cls_cnt 0 2006.203.08:02:22.76#ibcon#cleared, iclass 29 cls_cnt 0 2006.203.08:02:22.76$vc4f8/vblo=5,744.99 2006.203.08:02:22.76#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.203.08:02:22.76#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.203.08:02:22.76#ibcon#ireg 17 cls_cnt 0 2006.203.08:02:22.76#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.203.08:02:22.76#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.203.08:02:22.76#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.203.08:02:22.76#ibcon#enter wrdev, iclass 31, count 0 2006.203.08:02:22.76#ibcon#first serial, iclass 31, count 0 2006.203.08:02:22.76#ibcon#enter sib2, iclass 31, count 0 2006.203.08:02:22.76#ibcon#flushed, iclass 31, count 0 2006.203.08:02:22.76#ibcon#about to write, iclass 31, count 0 2006.203.08:02:22.76#ibcon#wrote, iclass 31, count 0 2006.203.08:02:22.76#ibcon#about to read 3, iclass 31, count 0 2006.203.08:02:22.78#ibcon#read 3, iclass 31, count 0 2006.203.08:02:22.78#ibcon#about to read 4, iclass 31, count 0 2006.203.08:02:22.78#ibcon#read 4, iclass 31, count 0 2006.203.08:02:22.78#ibcon#about to read 5, iclass 31, count 0 2006.203.08:02:22.78#ibcon#read 5, iclass 31, count 0 2006.203.08:02:22.78#ibcon#about to read 6, iclass 31, count 0 2006.203.08:02:22.78#ibcon#read 6, iclass 31, count 0 2006.203.08:02:22.78#ibcon#end of sib2, iclass 31, count 0 2006.203.08:02:22.78#ibcon#*mode == 0, iclass 31, count 0 2006.203.08:02:22.78#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.203.08:02:22.78#ibcon#[28=FRQ=05,744.99\r\n] 2006.203.08:02:22.78#ibcon#*before write, iclass 31, count 0 2006.203.08:02:22.78#ibcon#enter sib2, iclass 31, count 0 2006.203.08:02:22.78#ibcon#flushed, iclass 31, count 0 2006.203.08:02:22.78#ibcon#about to write, iclass 31, count 0 2006.203.08:02:22.78#ibcon#wrote, iclass 31, count 0 2006.203.08:02:22.78#ibcon#about to read 3, iclass 31, count 0 2006.203.08:02:22.82#ibcon#read 3, iclass 31, count 0 2006.203.08:02:22.82#ibcon#about to read 4, iclass 31, count 0 2006.203.08:02:22.82#ibcon#read 4, iclass 31, count 0 2006.203.08:02:22.82#ibcon#about to read 5, iclass 31, count 0 2006.203.08:02:22.82#ibcon#read 5, iclass 31, count 0 2006.203.08:02:22.82#ibcon#about to read 6, iclass 31, count 0 2006.203.08:02:22.82#ibcon#read 6, iclass 31, count 0 2006.203.08:02:22.82#ibcon#end of sib2, iclass 31, count 0 2006.203.08:02:22.82#ibcon#*after write, iclass 31, count 0 2006.203.08:02:22.82#ibcon#*before return 0, iclass 31, count 0 2006.203.08:02:22.82#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.203.08:02:22.82#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.203.08:02:22.82#ibcon#about to clear, iclass 31 cls_cnt 0 2006.203.08:02:22.82#ibcon#cleared, iclass 31 cls_cnt 0 2006.203.08:02:22.82$vc4f8/vb=5,3 2006.203.08:02:22.82#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.203.08:02:22.82#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.203.08:02:22.82#ibcon#ireg 11 cls_cnt 2 2006.203.08:02:22.82#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.203.08:02:22.88#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.203.08:02:22.88#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.203.08:02:22.88#ibcon#enter wrdev, iclass 33, count 2 2006.203.08:02:22.88#ibcon#first serial, iclass 33, count 2 2006.203.08:02:22.88#ibcon#enter sib2, iclass 33, count 2 2006.203.08:02:22.88#ibcon#flushed, iclass 33, count 2 2006.203.08:02:22.88#ibcon#about to write, iclass 33, count 2 2006.203.08:02:22.88#ibcon#wrote, iclass 33, count 2 2006.203.08:02:22.88#ibcon#about to read 3, iclass 33, count 2 2006.203.08:02:22.90#ibcon#read 3, iclass 33, count 2 2006.203.08:02:22.90#ibcon#about to read 4, iclass 33, count 2 2006.203.08:02:22.90#ibcon#read 4, iclass 33, count 2 2006.203.08:02:22.90#ibcon#about to read 5, iclass 33, count 2 2006.203.08:02:22.90#ibcon#read 5, iclass 33, count 2 2006.203.08:02:22.90#ibcon#about to read 6, iclass 33, count 2 2006.203.08:02:22.90#ibcon#read 6, iclass 33, count 2 2006.203.08:02:22.90#ibcon#end of sib2, iclass 33, count 2 2006.203.08:02:22.90#ibcon#*mode == 0, iclass 33, count 2 2006.203.08:02:22.90#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.203.08:02:22.90#ibcon#[27=AT05-03\r\n] 2006.203.08:02:22.90#ibcon#*before write, iclass 33, count 2 2006.203.08:02:22.90#ibcon#enter sib2, iclass 33, count 2 2006.203.08:02:22.90#ibcon#flushed, iclass 33, count 2 2006.203.08:02:22.90#ibcon#about to write, iclass 33, count 2 2006.203.08:02:22.90#ibcon#wrote, iclass 33, count 2 2006.203.08:02:22.90#ibcon#about to read 3, iclass 33, count 2 2006.203.08:02:22.93#ibcon#read 3, iclass 33, count 2 2006.203.08:02:22.93#ibcon#about to read 4, iclass 33, count 2 2006.203.08:02:22.93#ibcon#read 4, iclass 33, count 2 2006.203.08:02:22.93#ibcon#about to read 5, iclass 33, count 2 2006.203.08:02:22.93#ibcon#read 5, iclass 33, count 2 2006.203.08:02:22.93#ibcon#about to read 6, iclass 33, count 2 2006.203.08:02:22.93#ibcon#read 6, iclass 33, count 2 2006.203.08:02:22.93#ibcon#end of sib2, iclass 33, count 2 2006.203.08:02:22.93#ibcon#*after write, iclass 33, count 2 2006.203.08:02:22.93#ibcon#*before return 0, iclass 33, count 2 2006.203.08:02:22.93#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.203.08:02:22.93#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.203.08:02:22.93#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.203.08:02:22.93#ibcon#ireg 7 cls_cnt 0 2006.203.08:02:22.93#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.203.08:02:23.05#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.203.08:02:23.05#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.203.08:02:23.05#ibcon#enter wrdev, iclass 33, count 0 2006.203.08:02:23.05#ibcon#first serial, iclass 33, count 0 2006.203.08:02:23.05#ibcon#enter sib2, iclass 33, count 0 2006.203.08:02:23.05#ibcon#flushed, iclass 33, count 0 2006.203.08:02:23.05#ibcon#about to write, iclass 33, count 0 2006.203.08:02:23.05#ibcon#wrote, iclass 33, count 0 2006.203.08:02:23.05#ibcon#about to read 3, iclass 33, count 0 2006.203.08:02:23.07#ibcon#read 3, iclass 33, count 0 2006.203.08:02:23.07#ibcon#about to read 4, iclass 33, count 0 2006.203.08:02:23.07#ibcon#read 4, iclass 33, count 0 2006.203.08:02:23.07#ibcon#about to read 5, iclass 33, count 0 2006.203.08:02:23.07#ibcon#read 5, iclass 33, count 0 2006.203.08:02:23.07#ibcon#about to read 6, iclass 33, count 0 2006.203.08:02:23.07#ibcon#read 6, iclass 33, count 0 2006.203.08:02:23.07#ibcon#end of sib2, iclass 33, count 0 2006.203.08:02:23.07#ibcon#*mode == 0, iclass 33, count 0 2006.203.08:02:23.07#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.203.08:02:23.07#ibcon#[27=USB\r\n] 2006.203.08:02:23.07#ibcon#*before write, iclass 33, count 0 2006.203.08:02:23.07#ibcon#enter sib2, iclass 33, count 0 2006.203.08:02:23.07#ibcon#flushed, iclass 33, count 0 2006.203.08:02:23.07#ibcon#about to write, iclass 33, count 0 2006.203.08:02:23.07#ibcon#wrote, iclass 33, count 0 2006.203.08:02:23.07#ibcon#about to read 3, iclass 33, count 0 2006.203.08:02:23.10#ibcon#read 3, iclass 33, count 0 2006.203.08:02:23.10#ibcon#about to read 4, iclass 33, count 0 2006.203.08:02:23.10#ibcon#read 4, iclass 33, count 0 2006.203.08:02:23.10#ibcon#about to read 5, iclass 33, count 0 2006.203.08:02:23.10#ibcon#read 5, iclass 33, count 0 2006.203.08:02:23.10#ibcon#about to read 6, iclass 33, count 0 2006.203.08:02:23.10#ibcon#read 6, iclass 33, count 0 2006.203.08:02:23.10#ibcon#end of sib2, iclass 33, count 0 2006.203.08:02:23.10#ibcon#*after write, iclass 33, count 0 2006.203.08:02:23.10#ibcon#*before return 0, iclass 33, count 0 2006.203.08:02:23.10#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.203.08:02:23.10#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.203.08:02:23.10#ibcon#about to clear, iclass 33 cls_cnt 0 2006.203.08:02:23.10#ibcon#cleared, iclass 33 cls_cnt 0 2006.203.08:02:23.10$vc4f8/vblo=6,752.99 2006.203.08:02:23.10#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.203.08:02:23.10#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.203.08:02:23.10#ibcon#ireg 17 cls_cnt 0 2006.203.08:02:23.10#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.203.08:02:23.10#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.203.08:02:23.10#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.203.08:02:23.10#ibcon#enter wrdev, iclass 35, count 0 2006.203.08:02:23.10#ibcon#first serial, iclass 35, count 0 2006.203.08:02:23.10#ibcon#enter sib2, iclass 35, count 0 2006.203.08:02:23.10#ibcon#flushed, iclass 35, count 0 2006.203.08:02:23.10#ibcon#about to write, iclass 35, count 0 2006.203.08:02:23.10#ibcon#wrote, iclass 35, count 0 2006.203.08:02:23.10#ibcon#about to read 3, iclass 35, count 0 2006.203.08:02:23.12#ibcon#read 3, iclass 35, count 0 2006.203.08:02:23.12#ibcon#about to read 4, iclass 35, count 0 2006.203.08:02:23.12#ibcon#read 4, iclass 35, count 0 2006.203.08:02:23.12#ibcon#about to read 5, iclass 35, count 0 2006.203.08:02:23.12#ibcon#read 5, iclass 35, count 0 2006.203.08:02:23.12#ibcon#about to read 6, iclass 35, count 0 2006.203.08:02:23.12#ibcon#read 6, iclass 35, count 0 2006.203.08:02:23.12#ibcon#end of sib2, iclass 35, count 0 2006.203.08:02:23.12#ibcon#*mode == 0, iclass 35, count 0 2006.203.08:02:23.12#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.203.08:02:23.12#ibcon#[28=FRQ=06,752.99\r\n] 2006.203.08:02:23.12#ibcon#*before write, iclass 35, count 0 2006.203.08:02:23.12#ibcon#enter sib2, iclass 35, count 0 2006.203.08:02:23.12#ibcon#flushed, iclass 35, count 0 2006.203.08:02:23.12#ibcon#about to write, iclass 35, count 0 2006.203.08:02:23.12#ibcon#wrote, iclass 35, count 0 2006.203.08:02:23.12#ibcon#about to read 3, iclass 35, count 0 2006.203.08:02:23.16#ibcon#read 3, iclass 35, count 0 2006.203.08:02:23.16#ibcon#about to read 4, iclass 35, count 0 2006.203.08:02:23.16#ibcon#read 4, iclass 35, count 0 2006.203.08:02:23.16#ibcon#about to read 5, iclass 35, count 0 2006.203.08:02:23.16#ibcon#read 5, iclass 35, count 0 2006.203.08:02:23.16#ibcon#about to read 6, iclass 35, count 0 2006.203.08:02:23.16#ibcon#read 6, iclass 35, count 0 2006.203.08:02:23.16#ibcon#end of sib2, iclass 35, count 0 2006.203.08:02:23.16#ibcon#*after write, iclass 35, count 0 2006.203.08:02:23.16#ibcon#*before return 0, iclass 35, count 0 2006.203.08:02:23.16#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.203.08:02:23.16#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.203.08:02:23.16#ibcon#about to clear, iclass 35 cls_cnt 0 2006.203.08:02:23.16#ibcon#cleared, iclass 35 cls_cnt 0 2006.203.08:02:23.16$vc4f8/vb=6,4 2006.203.08:02:23.16#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.203.08:02:23.16#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.203.08:02:23.16#ibcon#ireg 11 cls_cnt 2 2006.203.08:02:23.16#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.203.08:02:23.22#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.203.08:02:23.22#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.203.08:02:23.22#ibcon#enter wrdev, iclass 37, count 2 2006.203.08:02:23.22#ibcon#first serial, iclass 37, count 2 2006.203.08:02:23.22#ibcon#enter sib2, iclass 37, count 2 2006.203.08:02:23.22#ibcon#flushed, iclass 37, count 2 2006.203.08:02:23.22#ibcon#about to write, iclass 37, count 2 2006.203.08:02:23.22#ibcon#wrote, iclass 37, count 2 2006.203.08:02:23.22#ibcon#about to read 3, iclass 37, count 2 2006.203.08:02:23.24#ibcon#read 3, iclass 37, count 2 2006.203.08:02:23.24#ibcon#about to read 4, iclass 37, count 2 2006.203.08:02:23.24#ibcon#read 4, iclass 37, count 2 2006.203.08:02:23.24#ibcon#about to read 5, iclass 37, count 2 2006.203.08:02:23.24#ibcon#read 5, iclass 37, count 2 2006.203.08:02:23.24#ibcon#about to read 6, iclass 37, count 2 2006.203.08:02:23.24#ibcon#read 6, iclass 37, count 2 2006.203.08:02:23.24#ibcon#end of sib2, iclass 37, count 2 2006.203.08:02:23.24#ibcon#*mode == 0, iclass 37, count 2 2006.203.08:02:23.24#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.203.08:02:23.24#ibcon#[27=AT06-04\r\n] 2006.203.08:02:23.24#ibcon#*before write, iclass 37, count 2 2006.203.08:02:23.24#ibcon#enter sib2, iclass 37, count 2 2006.203.08:02:23.24#ibcon#flushed, iclass 37, count 2 2006.203.08:02:23.24#ibcon#about to write, iclass 37, count 2 2006.203.08:02:23.24#ibcon#wrote, iclass 37, count 2 2006.203.08:02:23.24#ibcon#about to read 3, iclass 37, count 2 2006.203.08:02:23.27#ibcon#read 3, iclass 37, count 2 2006.203.08:02:23.27#ibcon#about to read 4, iclass 37, count 2 2006.203.08:02:23.27#ibcon#read 4, iclass 37, count 2 2006.203.08:02:23.27#ibcon#about to read 5, iclass 37, count 2 2006.203.08:02:23.27#ibcon#read 5, iclass 37, count 2 2006.203.08:02:23.27#ibcon#about to read 6, iclass 37, count 2 2006.203.08:02:23.27#ibcon#read 6, iclass 37, count 2 2006.203.08:02:23.27#ibcon#end of sib2, iclass 37, count 2 2006.203.08:02:23.27#ibcon#*after write, iclass 37, count 2 2006.203.08:02:23.27#ibcon#*before return 0, iclass 37, count 2 2006.203.08:02:23.27#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.203.08:02:23.27#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.203.08:02:23.27#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.203.08:02:23.27#ibcon#ireg 7 cls_cnt 0 2006.203.08:02:23.27#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.203.08:02:23.39#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.203.08:02:23.39#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.203.08:02:23.39#ibcon#enter wrdev, iclass 37, count 0 2006.203.08:02:23.39#ibcon#first serial, iclass 37, count 0 2006.203.08:02:23.39#ibcon#enter sib2, iclass 37, count 0 2006.203.08:02:23.39#ibcon#flushed, iclass 37, count 0 2006.203.08:02:23.39#ibcon#about to write, iclass 37, count 0 2006.203.08:02:23.39#ibcon#wrote, iclass 37, count 0 2006.203.08:02:23.39#ibcon#about to read 3, iclass 37, count 0 2006.203.08:02:23.41#ibcon#read 3, iclass 37, count 0 2006.203.08:02:23.41#ibcon#about to read 4, iclass 37, count 0 2006.203.08:02:23.41#ibcon#read 4, iclass 37, count 0 2006.203.08:02:23.41#ibcon#about to read 5, iclass 37, count 0 2006.203.08:02:23.41#ibcon#read 5, iclass 37, count 0 2006.203.08:02:23.41#ibcon#about to read 6, iclass 37, count 0 2006.203.08:02:23.41#ibcon#read 6, iclass 37, count 0 2006.203.08:02:23.41#ibcon#end of sib2, iclass 37, count 0 2006.203.08:02:23.41#ibcon#*mode == 0, iclass 37, count 0 2006.203.08:02:23.41#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.203.08:02:23.41#ibcon#[27=USB\r\n] 2006.203.08:02:23.41#ibcon#*before write, iclass 37, count 0 2006.203.08:02:23.41#ibcon#enter sib2, iclass 37, count 0 2006.203.08:02:23.41#ibcon#flushed, iclass 37, count 0 2006.203.08:02:23.41#ibcon#about to write, iclass 37, count 0 2006.203.08:02:23.41#ibcon#wrote, iclass 37, count 0 2006.203.08:02:23.41#ibcon#about to read 3, iclass 37, count 0 2006.203.08:02:23.44#ibcon#read 3, iclass 37, count 0 2006.203.08:02:23.44#ibcon#about to read 4, iclass 37, count 0 2006.203.08:02:23.44#ibcon#read 4, iclass 37, count 0 2006.203.08:02:23.44#ibcon#about to read 5, iclass 37, count 0 2006.203.08:02:23.44#ibcon#read 5, iclass 37, count 0 2006.203.08:02:23.44#ibcon#about to read 6, iclass 37, count 0 2006.203.08:02:23.44#ibcon#read 6, iclass 37, count 0 2006.203.08:02:23.44#ibcon#end of sib2, iclass 37, count 0 2006.203.08:02:23.44#ibcon#*after write, iclass 37, count 0 2006.203.08:02:23.44#ibcon#*before return 0, iclass 37, count 0 2006.203.08:02:23.44#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.203.08:02:23.44#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.203.08:02:23.44#ibcon#about to clear, iclass 37 cls_cnt 0 2006.203.08:02:23.44#ibcon#cleared, iclass 37 cls_cnt 0 2006.203.08:02:23.44$vc4f8/vabw=wide 2006.203.08:02:23.44#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.203.08:02:23.44#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.203.08:02:23.44#ibcon#ireg 8 cls_cnt 0 2006.203.08:02:23.44#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.203.08:02:23.44#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.203.08:02:23.44#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.203.08:02:23.44#ibcon#enter wrdev, iclass 39, count 0 2006.203.08:02:23.44#ibcon#first serial, iclass 39, count 0 2006.203.08:02:23.44#ibcon#enter sib2, iclass 39, count 0 2006.203.08:02:23.44#ibcon#flushed, iclass 39, count 0 2006.203.08:02:23.44#ibcon#about to write, iclass 39, count 0 2006.203.08:02:23.44#ibcon#wrote, iclass 39, count 0 2006.203.08:02:23.44#ibcon#about to read 3, iclass 39, count 0 2006.203.08:02:23.46#ibcon#read 3, iclass 39, count 0 2006.203.08:02:23.46#ibcon#about to read 4, iclass 39, count 0 2006.203.08:02:23.46#ibcon#read 4, iclass 39, count 0 2006.203.08:02:23.46#ibcon#about to read 5, iclass 39, count 0 2006.203.08:02:23.46#ibcon#read 5, iclass 39, count 0 2006.203.08:02:23.46#ibcon#about to read 6, iclass 39, count 0 2006.203.08:02:23.46#ibcon#read 6, iclass 39, count 0 2006.203.08:02:23.46#ibcon#end of sib2, iclass 39, count 0 2006.203.08:02:23.46#ibcon#*mode == 0, iclass 39, count 0 2006.203.08:02:23.46#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.203.08:02:23.46#ibcon#[25=BW32\r\n] 2006.203.08:02:23.46#ibcon#*before write, iclass 39, count 0 2006.203.08:02:23.46#ibcon#enter sib2, iclass 39, count 0 2006.203.08:02:23.46#ibcon#flushed, iclass 39, count 0 2006.203.08:02:23.46#ibcon#about to write, iclass 39, count 0 2006.203.08:02:23.46#ibcon#wrote, iclass 39, count 0 2006.203.08:02:23.46#ibcon#about to read 3, iclass 39, count 0 2006.203.08:02:23.49#ibcon#read 3, iclass 39, count 0 2006.203.08:02:23.49#ibcon#about to read 4, iclass 39, count 0 2006.203.08:02:23.49#ibcon#read 4, iclass 39, count 0 2006.203.08:02:23.49#ibcon#about to read 5, iclass 39, count 0 2006.203.08:02:23.49#ibcon#read 5, iclass 39, count 0 2006.203.08:02:23.49#ibcon#about to read 6, iclass 39, count 0 2006.203.08:02:23.49#ibcon#read 6, iclass 39, count 0 2006.203.08:02:23.49#ibcon#end of sib2, iclass 39, count 0 2006.203.08:02:23.49#ibcon#*after write, iclass 39, count 0 2006.203.08:02:23.49#ibcon#*before return 0, iclass 39, count 0 2006.203.08:02:23.49#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.203.08:02:23.49#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.203.08:02:23.49#ibcon#about to clear, iclass 39 cls_cnt 0 2006.203.08:02:23.49#ibcon#cleared, iclass 39 cls_cnt 0 2006.203.08:02:23.49$vc4f8/vbbw=wide 2006.203.08:02:23.49#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.203.08:02:23.49#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.203.08:02:23.49#ibcon#ireg 8 cls_cnt 0 2006.203.08:02:23.49#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.203.08:02:23.56#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.203.08:02:23.56#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.203.08:02:23.56#ibcon#enter wrdev, iclass 3, count 0 2006.203.08:02:23.56#ibcon#first serial, iclass 3, count 0 2006.203.08:02:23.56#ibcon#enter sib2, iclass 3, count 0 2006.203.08:02:23.56#ibcon#flushed, iclass 3, count 0 2006.203.08:02:23.56#ibcon#about to write, iclass 3, count 0 2006.203.08:02:23.56#ibcon#wrote, iclass 3, count 0 2006.203.08:02:23.56#ibcon#about to read 3, iclass 3, count 0 2006.203.08:02:23.58#ibcon#read 3, iclass 3, count 0 2006.203.08:02:23.58#ibcon#about to read 4, iclass 3, count 0 2006.203.08:02:23.58#ibcon#read 4, iclass 3, count 0 2006.203.08:02:23.58#ibcon#about to read 5, iclass 3, count 0 2006.203.08:02:23.58#ibcon#read 5, iclass 3, count 0 2006.203.08:02:23.58#ibcon#about to read 6, iclass 3, count 0 2006.203.08:02:23.58#ibcon#read 6, iclass 3, count 0 2006.203.08:02:23.58#ibcon#end of sib2, iclass 3, count 0 2006.203.08:02:23.58#ibcon#*mode == 0, iclass 3, count 0 2006.203.08:02:23.58#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.203.08:02:23.58#ibcon#[27=BW32\r\n] 2006.203.08:02:23.58#ibcon#*before write, iclass 3, count 0 2006.203.08:02:23.58#ibcon#enter sib2, iclass 3, count 0 2006.203.08:02:23.58#ibcon#flushed, iclass 3, count 0 2006.203.08:02:23.58#ibcon#about to write, iclass 3, count 0 2006.203.08:02:23.58#ibcon#wrote, iclass 3, count 0 2006.203.08:02:23.58#ibcon#about to read 3, iclass 3, count 0 2006.203.08:02:23.61#ibcon#read 3, iclass 3, count 0 2006.203.08:02:23.61#ibcon#about to read 4, iclass 3, count 0 2006.203.08:02:23.61#ibcon#read 4, iclass 3, count 0 2006.203.08:02:23.61#ibcon#about to read 5, iclass 3, count 0 2006.203.08:02:23.61#ibcon#read 5, iclass 3, count 0 2006.203.08:02:23.61#ibcon#about to read 6, iclass 3, count 0 2006.203.08:02:23.61#ibcon#read 6, iclass 3, count 0 2006.203.08:02:23.61#ibcon#end of sib2, iclass 3, count 0 2006.203.08:02:23.61#ibcon#*after write, iclass 3, count 0 2006.203.08:02:23.61#ibcon#*before return 0, iclass 3, count 0 2006.203.08:02:23.61#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.203.08:02:23.61#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.203.08:02:23.61#ibcon#about to clear, iclass 3 cls_cnt 0 2006.203.08:02:23.61#ibcon#cleared, iclass 3 cls_cnt 0 2006.203.08:02:23.61$4f8m12a/ifd4f 2006.203.08:02:23.61$ifd4f/lo= 2006.203.08:02:23.61$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.203.08:02:23.61$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.203.08:02:23.61$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.203.08:02:23.61$ifd4f/patch= 2006.203.08:02:23.61$ifd4f/patch=lo1,a1,a2,a3,a4 2006.203.08:02:23.61$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.203.08:02:23.61$ifd4f/patch=lo3,a5,a6,a7,a8 2006.203.08:02:23.61$4f8m12a/"form=m,16.000,1:2 2006.203.08:02:23.61$4f8m12a/"tpicd 2006.203.08:02:23.61$4f8m12a/echo=off 2006.203.08:02:23.61$4f8m12a/xlog=off 2006.203.08:02:23.61:!2006.203.08:02:50 2006.203.08:02:33.14#trakl#Source acquired 2006.203.08:02:35.14#flagr#flagr/antenna,acquired 2006.203.08:02:50.00:preob 2006.203.08:02:51.14/onsource/TRACKING 2006.203.08:02:51.14:!2006.203.08:03:00 2006.203.08:03:00.00:data_valid=on 2006.203.08:03:00.00:midob 2006.203.08:03:00.14/onsource/TRACKING 2006.203.08:03:00.14/wx/23.70,1001.1,99 2006.203.08:03:00.30/cable/+6.4592E-03 2006.203.08:03:01.39/va/01,08,usb,yes,31,32 2006.203.08:03:01.39/va/02,07,usb,yes,31,32 2006.203.08:03:01.39/va/03,08,usb,yes,23,23 2006.203.08:03:01.39/va/04,07,usb,yes,32,34 2006.203.08:03:01.39/va/05,07,usb,yes,34,36 2006.203.08:03:01.39/va/06,06,usb,yes,33,33 2006.203.08:03:01.39/va/07,07,usb,yes,30,29 2006.203.08:03:01.39/va/08,06,usb,yes,36,36 2006.203.08:03:01.62/valo/01,532.99,yes,locked 2006.203.08:03:01.62/valo/02,572.99,yes,locked 2006.203.08:03:01.62/valo/03,672.99,yes,locked 2006.203.08:03:01.62/valo/04,832.99,yes,locked 2006.203.08:03:01.62/valo/05,652.99,yes,locked 2006.203.08:03:01.62/valo/06,772.99,yes,locked 2006.203.08:03:01.62/valo/07,832.99,yes,locked 2006.203.08:03:01.62/valo/08,852.99,yes,locked 2006.203.08:03:02.71/vb/01,04,usb,yes,29,28 2006.203.08:03:02.71/vb/02,04,usb,yes,31,32 2006.203.08:03:02.71/vb/03,04,usb,yes,27,31 2006.203.08:03:02.71/vb/04,04,usb,yes,28,28 2006.203.08:03:02.71/vb/05,03,usb,yes,33,38 2006.203.08:03:02.71/vb/06,04,usb,yes,28,30 2006.203.08:03:02.71/vb/07,04,usb,yes,30,30 2006.203.08:03:02.71/vb/08,04,usb,yes,27,31 2006.203.08:03:02.95/vblo/01,632.99,yes,locked 2006.203.08:03:02.95/vblo/02,640.99,yes,locked 2006.203.08:03:02.95/vblo/03,656.99,yes,locked 2006.203.08:03:02.95/vblo/04,712.99,yes,locked 2006.203.08:03:02.95/vblo/05,744.99,yes,locked 2006.203.08:03:02.95/vblo/06,752.99,yes,locked 2006.203.08:03:02.95/vblo/07,734.99,yes,locked 2006.203.08:03:02.95/vblo/08,744.99,yes,locked 2006.203.08:03:03.10/vabw/8 2006.203.08:03:03.25/vbbw/8 2006.203.08:03:03.42/xfe/off,on,13.2 2006.203.08:03:03.79/ifatt/23,28,28,28 2006.203.08:03:04.08/fmout-gps/S +4.59E-07 2006.203.08:03:04.15:!2006.203.08:04:00 2006.203.08:04:00.00:data_valid=off 2006.203.08:04:00.00:postob 2006.203.08:04:00.10/cable/+6.4610E-03 2006.203.08:04:00.10/wx/23.69,1001.2,99 2006.203.08:04:01.07/fmout-gps/S +4.58E-07 2006.203.08:04:01.07:scan_name=203-0804,k06203,60 2006.203.08:04:01.07:source=1803+784,180045.68,782804.0,2000.0,cw 2006.203.08:04:01.15#flagr#flagr/antenna,new-source 2006.203.08:04:02.13:checkk5 2006.203.08:04:02.80/chk_autoobs//k5ts1/ autoobs is running! 2006.203.08:04:03.23/chk_autoobs//k5ts2/ autoobs is running! 2006.203.08:04:03.66/chk_autoobs//k5ts3/ autoobs is running! 2006.203.08:04:04.30/chk_autoobs//k5ts4/ autoobs is running! 2006.203.08:04:04.70/chk_obsdata//k5ts1/T2030803??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.08:04:05.16/chk_obsdata//k5ts2/T2030803??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.08:04:05.57/chk_obsdata//k5ts3/T2030803??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.08:04:05.96/chk_obsdata//k5ts4/T2030803??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.08:04:06.75/k5log//k5ts1_log_newline 2006.203.08:04:07.51/k5log//k5ts2_log_newline 2006.203.08:04:08.34/k5log//k5ts3_log_newline 2006.203.08:04:09.12/k5log//k5ts4_log_newline 2006.203.08:04:09.14/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.203.08:04:09.14:4f8m12a=2 2006.203.08:04:09.14$4f8m12a/echo=on 2006.203.08:04:09.14$4f8m12a/pcalon 2006.203.08:04:09.14$pcalon/"no phase cal control is implemented here 2006.203.08:04:09.14$4f8m12a/"tpicd=stop 2006.203.08:04:09.14$4f8m12a/vc4f8 2006.203.08:04:09.14$vc4f8/valo=1,532.99 2006.203.08:04:09.15#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.203.08:04:09.15#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.203.08:04:09.15#ibcon#ireg 17 cls_cnt 0 2006.203.08:04:09.15#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.203.08:04:09.15#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.203.08:04:09.15#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.203.08:04:09.15#ibcon#enter wrdev, iclass 16, count 0 2006.203.08:04:09.15#ibcon#first serial, iclass 16, count 0 2006.203.08:04:09.15#ibcon#enter sib2, iclass 16, count 0 2006.203.08:04:09.15#ibcon#flushed, iclass 16, count 0 2006.203.08:04:09.15#ibcon#about to write, iclass 16, count 0 2006.203.08:04:09.15#ibcon#wrote, iclass 16, count 0 2006.203.08:04:09.15#ibcon#about to read 3, iclass 16, count 0 2006.203.08:04:09.19#ibcon#read 3, iclass 16, count 0 2006.203.08:04:09.19#ibcon#about to read 4, iclass 16, count 0 2006.203.08:04:09.19#ibcon#read 4, iclass 16, count 0 2006.203.08:04:09.19#ibcon#about to read 5, iclass 16, count 0 2006.203.08:04:09.19#ibcon#read 5, iclass 16, count 0 2006.203.08:04:09.19#ibcon#about to read 6, iclass 16, count 0 2006.203.08:04:09.19#ibcon#read 6, iclass 16, count 0 2006.203.08:04:09.19#ibcon#end of sib2, iclass 16, count 0 2006.203.08:04:09.19#ibcon#*mode == 0, iclass 16, count 0 2006.203.08:04:09.19#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.203.08:04:09.19#ibcon#[26=FRQ=01,532.99\r\n] 2006.203.08:04:09.19#ibcon#*before write, iclass 16, count 0 2006.203.08:04:09.19#ibcon#enter sib2, iclass 16, count 0 2006.203.08:04:09.19#ibcon#flushed, iclass 16, count 0 2006.203.08:04:09.19#ibcon#about to write, iclass 16, count 0 2006.203.08:04:09.19#ibcon#wrote, iclass 16, count 0 2006.203.08:04:09.19#ibcon#about to read 3, iclass 16, count 0 2006.203.08:04:09.24#ibcon#read 3, iclass 16, count 0 2006.203.08:04:09.24#ibcon#about to read 4, iclass 16, count 0 2006.203.08:04:09.24#ibcon#read 4, iclass 16, count 0 2006.203.08:04:09.24#ibcon#about to read 5, iclass 16, count 0 2006.203.08:04:09.24#ibcon#read 5, iclass 16, count 0 2006.203.08:04:09.24#ibcon#about to read 6, iclass 16, count 0 2006.203.08:04:09.24#ibcon#read 6, iclass 16, count 0 2006.203.08:04:09.24#ibcon#end of sib2, iclass 16, count 0 2006.203.08:04:09.24#ibcon#*after write, iclass 16, count 0 2006.203.08:04:09.24#ibcon#*before return 0, iclass 16, count 0 2006.203.08:04:09.24#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.203.08:04:09.24#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.203.08:04:09.24#ibcon#about to clear, iclass 16 cls_cnt 0 2006.203.08:04:09.24#ibcon#cleared, iclass 16 cls_cnt 0 2006.203.08:04:09.24$vc4f8/va=1,8 2006.203.08:04:09.24#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.203.08:04:09.24#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.203.08:04:09.24#ibcon#ireg 11 cls_cnt 2 2006.203.08:04:09.24#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.203.08:04:09.24#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.203.08:04:09.24#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.203.08:04:09.24#ibcon#enter wrdev, iclass 18, count 2 2006.203.08:04:09.24#ibcon#first serial, iclass 18, count 2 2006.203.08:04:09.24#ibcon#enter sib2, iclass 18, count 2 2006.203.08:04:09.24#ibcon#flushed, iclass 18, count 2 2006.203.08:04:09.24#ibcon#about to write, iclass 18, count 2 2006.203.08:04:09.24#ibcon#wrote, iclass 18, count 2 2006.203.08:04:09.24#ibcon#about to read 3, iclass 18, count 2 2006.203.08:04:09.26#ibcon#read 3, iclass 18, count 2 2006.203.08:04:09.26#ibcon#about to read 4, iclass 18, count 2 2006.203.08:04:09.26#ibcon#read 4, iclass 18, count 2 2006.203.08:04:09.26#ibcon#about to read 5, iclass 18, count 2 2006.203.08:04:09.26#ibcon#read 5, iclass 18, count 2 2006.203.08:04:09.26#ibcon#about to read 6, iclass 18, count 2 2006.203.08:04:09.26#ibcon#read 6, iclass 18, count 2 2006.203.08:04:09.26#ibcon#end of sib2, iclass 18, count 2 2006.203.08:04:09.26#ibcon#*mode == 0, iclass 18, count 2 2006.203.08:04:09.26#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.203.08:04:09.26#ibcon#[25=AT01-08\r\n] 2006.203.08:04:09.26#ibcon#*before write, iclass 18, count 2 2006.203.08:04:09.26#ibcon#enter sib2, iclass 18, count 2 2006.203.08:04:09.26#ibcon#flushed, iclass 18, count 2 2006.203.08:04:09.26#ibcon#about to write, iclass 18, count 2 2006.203.08:04:09.26#ibcon#wrote, iclass 18, count 2 2006.203.08:04:09.26#ibcon#about to read 3, iclass 18, count 2 2006.203.08:04:09.29#ibcon#read 3, iclass 18, count 2 2006.203.08:04:09.29#ibcon#about to read 4, iclass 18, count 2 2006.203.08:04:09.29#ibcon#read 4, iclass 18, count 2 2006.203.08:04:09.29#ibcon#about to read 5, iclass 18, count 2 2006.203.08:04:09.29#ibcon#read 5, iclass 18, count 2 2006.203.08:04:09.29#ibcon#about to read 6, iclass 18, count 2 2006.203.08:04:09.29#ibcon#read 6, iclass 18, count 2 2006.203.08:04:09.29#ibcon#end of sib2, iclass 18, count 2 2006.203.08:04:09.29#ibcon#*after write, iclass 18, count 2 2006.203.08:04:09.29#ibcon#*before return 0, iclass 18, count 2 2006.203.08:04:09.29#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.203.08:04:09.29#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.203.08:04:09.29#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.203.08:04:09.29#ibcon#ireg 7 cls_cnt 0 2006.203.08:04:09.29#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.203.08:04:09.41#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.203.08:04:09.41#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.203.08:04:09.41#ibcon#enter wrdev, iclass 18, count 0 2006.203.08:04:09.41#ibcon#first serial, iclass 18, count 0 2006.203.08:04:09.41#ibcon#enter sib2, iclass 18, count 0 2006.203.08:04:09.41#ibcon#flushed, iclass 18, count 0 2006.203.08:04:09.41#ibcon#about to write, iclass 18, count 0 2006.203.08:04:09.41#ibcon#wrote, iclass 18, count 0 2006.203.08:04:09.41#ibcon#about to read 3, iclass 18, count 0 2006.203.08:04:09.43#ibcon#read 3, iclass 18, count 0 2006.203.08:04:09.43#ibcon#about to read 4, iclass 18, count 0 2006.203.08:04:09.43#ibcon#read 4, iclass 18, count 0 2006.203.08:04:09.43#ibcon#about to read 5, iclass 18, count 0 2006.203.08:04:09.43#ibcon#read 5, iclass 18, count 0 2006.203.08:04:09.43#ibcon#about to read 6, iclass 18, count 0 2006.203.08:04:09.43#ibcon#read 6, iclass 18, count 0 2006.203.08:04:09.43#ibcon#end of sib2, iclass 18, count 0 2006.203.08:04:09.43#ibcon#*mode == 0, iclass 18, count 0 2006.203.08:04:09.43#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.203.08:04:09.43#ibcon#[25=USB\r\n] 2006.203.08:04:09.43#ibcon#*before write, iclass 18, count 0 2006.203.08:04:09.43#ibcon#enter sib2, iclass 18, count 0 2006.203.08:04:09.43#ibcon#flushed, iclass 18, count 0 2006.203.08:04:09.43#ibcon#about to write, iclass 18, count 0 2006.203.08:04:09.43#ibcon#wrote, iclass 18, count 0 2006.203.08:04:09.43#ibcon#about to read 3, iclass 18, count 0 2006.203.08:04:09.46#ibcon#read 3, iclass 18, count 0 2006.203.08:04:09.46#ibcon#about to read 4, iclass 18, count 0 2006.203.08:04:09.46#ibcon#read 4, iclass 18, count 0 2006.203.08:04:09.46#ibcon#about to read 5, iclass 18, count 0 2006.203.08:04:09.46#ibcon#read 5, iclass 18, count 0 2006.203.08:04:09.46#ibcon#about to read 6, iclass 18, count 0 2006.203.08:04:09.46#ibcon#read 6, iclass 18, count 0 2006.203.08:04:09.46#ibcon#end of sib2, iclass 18, count 0 2006.203.08:04:09.46#ibcon#*after write, iclass 18, count 0 2006.203.08:04:09.46#ibcon#*before return 0, iclass 18, count 0 2006.203.08:04:09.46#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.203.08:04:09.46#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.203.08:04:09.46#ibcon#about to clear, iclass 18 cls_cnt 0 2006.203.08:04:09.46#ibcon#cleared, iclass 18 cls_cnt 0 2006.203.08:04:09.46$vc4f8/valo=2,572.99 2006.203.08:04:09.46#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.203.08:04:09.46#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.203.08:04:09.46#ibcon#ireg 17 cls_cnt 0 2006.203.08:04:09.46#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.203.08:04:09.46#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.203.08:04:09.46#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.203.08:04:09.46#ibcon#enter wrdev, iclass 20, count 0 2006.203.08:04:09.46#ibcon#first serial, iclass 20, count 0 2006.203.08:04:09.46#ibcon#enter sib2, iclass 20, count 0 2006.203.08:04:09.46#ibcon#flushed, iclass 20, count 0 2006.203.08:04:09.46#ibcon#about to write, iclass 20, count 0 2006.203.08:04:09.46#ibcon#wrote, iclass 20, count 0 2006.203.08:04:09.46#ibcon#about to read 3, iclass 20, count 0 2006.203.08:04:09.48#ibcon#read 3, iclass 20, count 0 2006.203.08:04:09.48#ibcon#about to read 4, iclass 20, count 0 2006.203.08:04:09.48#ibcon#read 4, iclass 20, count 0 2006.203.08:04:09.48#ibcon#about to read 5, iclass 20, count 0 2006.203.08:04:09.48#ibcon#read 5, iclass 20, count 0 2006.203.08:04:09.48#ibcon#about to read 6, iclass 20, count 0 2006.203.08:04:09.48#ibcon#read 6, iclass 20, count 0 2006.203.08:04:09.48#ibcon#end of sib2, iclass 20, count 0 2006.203.08:04:09.48#ibcon#*mode == 0, iclass 20, count 0 2006.203.08:04:09.48#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.203.08:04:09.48#ibcon#[26=FRQ=02,572.99\r\n] 2006.203.08:04:09.48#ibcon#*before write, iclass 20, count 0 2006.203.08:04:09.48#ibcon#enter sib2, iclass 20, count 0 2006.203.08:04:09.48#ibcon#flushed, iclass 20, count 0 2006.203.08:04:09.48#ibcon#about to write, iclass 20, count 0 2006.203.08:04:09.48#ibcon#wrote, iclass 20, count 0 2006.203.08:04:09.48#ibcon#about to read 3, iclass 20, count 0 2006.203.08:04:09.53#ibcon#read 3, iclass 20, count 0 2006.203.08:04:09.53#ibcon#about to read 4, iclass 20, count 0 2006.203.08:04:09.53#ibcon#read 4, iclass 20, count 0 2006.203.08:04:09.53#ibcon#about to read 5, iclass 20, count 0 2006.203.08:04:09.53#ibcon#read 5, iclass 20, count 0 2006.203.08:04:09.53#ibcon#about to read 6, iclass 20, count 0 2006.203.08:04:09.53#ibcon#read 6, iclass 20, count 0 2006.203.08:04:09.53#ibcon#end of sib2, iclass 20, count 0 2006.203.08:04:09.53#ibcon#*after write, iclass 20, count 0 2006.203.08:04:09.53#ibcon#*before return 0, iclass 20, count 0 2006.203.08:04:09.53#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.203.08:04:09.53#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.203.08:04:09.53#ibcon#about to clear, iclass 20 cls_cnt 0 2006.203.08:04:09.53#ibcon#cleared, iclass 20 cls_cnt 0 2006.203.08:04:09.53$vc4f8/va=2,7 2006.203.08:04:09.53#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.203.08:04:09.53#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.203.08:04:09.53#ibcon#ireg 11 cls_cnt 2 2006.203.08:04:09.53#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.203.08:04:09.58#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.203.08:04:09.58#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.203.08:04:09.58#ibcon#enter wrdev, iclass 22, count 2 2006.203.08:04:09.58#ibcon#first serial, iclass 22, count 2 2006.203.08:04:09.58#ibcon#enter sib2, iclass 22, count 2 2006.203.08:04:09.58#ibcon#flushed, iclass 22, count 2 2006.203.08:04:09.58#ibcon#about to write, iclass 22, count 2 2006.203.08:04:09.58#ibcon#wrote, iclass 22, count 2 2006.203.08:04:09.58#ibcon#about to read 3, iclass 22, count 2 2006.203.08:04:09.60#ibcon#read 3, iclass 22, count 2 2006.203.08:04:09.60#ibcon#about to read 4, iclass 22, count 2 2006.203.08:04:09.60#ibcon#read 4, iclass 22, count 2 2006.203.08:04:09.60#ibcon#about to read 5, iclass 22, count 2 2006.203.08:04:09.60#ibcon#read 5, iclass 22, count 2 2006.203.08:04:09.60#ibcon#about to read 6, iclass 22, count 2 2006.203.08:04:09.60#ibcon#read 6, iclass 22, count 2 2006.203.08:04:09.60#ibcon#end of sib2, iclass 22, count 2 2006.203.08:04:09.60#ibcon#*mode == 0, iclass 22, count 2 2006.203.08:04:09.60#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.203.08:04:09.60#ibcon#[25=AT02-07\r\n] 2006.203.08:04:09.60#ibcon#*before write, iclass 22, count 2 2006.203.08:04:09.60#ibcon#enter sib2, iclass 22, count 2 2006.203.08:04:09.60#ibcon#flushed, iclass 22, count 2 2006.203.08:04:09.60#ibcon#about to write, iclass 22, count 2 2006.203.08:04:09.60#ibcon#wrote, iclass 22, count 2 2006.203.08:04:09.60#ibcon#about to read 3, iclass 22, count 2 2006.203.08:04:09.63#ibcon#read 3, iclass 22, count 2 2006.203.08:04:09.63#ibcon#about to read 4, iclass 22, count 2 2006.203.08:04:09.63#ibcon#read 4, iclass 22, count 2 2006.203.08:04:09.63#ibcon#about to read 5, iclass 22, count 2 2006.203.08:04:09.63#ibcon#read 5, iclass 22, count 2 2006.203.08:04:09.63#ibcon#about to read 6, iclass 22, count 2 2006.203.08:04:09.63#ibcon#read 6, iclass 22, count 2 2006.203.08:04:09.63#ibcon#end of sib2, iclass 22, count 2 2006.203.08:04:09.63#ibcon#*after write, iclass 22, count 2 2006.203.08:04:09.63#ibcon#*before return 0, iclass 22, count 2 2006.203.08:04:09.63#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.203.08:04:09.63#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.203.08:04:09.63#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.203.08:04:09.63#ibcon#ireg 7 cls_cnt 0 2006.203.08:04:09.63#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.203.08:04:09.75#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.203.08:04:09.75#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.203.08:04:09.75#ibcon#enter wrdev, iclass 22, count 0 2006.203.08:04:09.75#ibcon#first serial, iclass 22, count 0 2006.203.08:04:09.75#ibcon#enter sib2, iclass 22, count 0 2006.203.08:04:09.75#ibcon#flushed, iclass 22, count 0 2006.203.08:04:09.75#ibcon#about to write, iclass 22, count 0 2006.203.08:04:09.75#ibcon#wrote, iclass 22, count 0 2006.203.08:04:09.75#ibcon#about to read 3, iclass 22, count 0 2006.203.08:04:09.77#ibcon#read 3, iclass 22, count 0 2006.203.08:04:09.77#ibcon#about to read 4, iclass 22, count 0 2006.203.08:04:09.77#ibcon#read 4, iclass 22, count 0 2006.203.08:04:09.77#ibcon#about to read 5, iclass 22, count 0 2006.203.08:04:09.77#ibcon#read 5, iclass 22, count 0 2006.203.08:04:09.77#ibcon#about to read 6, iclass 22, count 0 2006.203.08:04:09.77#ibcon#read 6, iclass 22, count 0 2006.203.08:04:09.77#ibcon#end of sib2, iclass 22, count 0 2006.203.08:04:09.77#ibcon#*mode == 0, iclass 22, count 0 2006.203.08:04:09.77#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.203.08:04:09.77#ibcon#[25=USB\r\n] 2006.203.08:04:09.77#ibcon#*before write, iclass 22, count 0 2006.203.08:04:09.77#ibcon#enter sib2, iclass 22, count 0 2006.203.08:04:09.77#ibcon#flushed, iclass 22, count 0 2006.203.08:04:09.77#ibcon#about to write, iclass 22, count 0 2006.203.08:04:09.77#ibcon#wrote, iclass 22, count 0 2006.203.08:04:09.77#ibcon#about to read 3, iclass 22, count 0 2006.203.08:04:09.80#ibcon#read 3, iclass 22, count 0 2006.203.08:04:09.80#ibcon#about to read 4, iclass 22, count 0 2006.203.08:04:09.80#ibcon#read 4, iclass 22, count 0 2006.203.08:04:09.80#ibcon#about to read 5, iclass 22, count 0 2006.203.08:04:09.80#ibcon#read 5, iclass 22, count 0 2006.203.08:04:09.80#ibcon#about to read 6, iclass 22, count 0 2006.203.08:04:09.80#ibcon#read 6, iclass 22, count 0 2006.203.08:04:09.80#ibcon#end of sib2, iclass 22, count 0 2006.203.08:04:09.80#ibcon#*after write, iclass 22, count 0 2006.203.08:04:09.80#ibcon#*before return 0, iclass 22, count 0 2006.203.08:04:09.80#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.203.08:04:09.80#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.203.08:04:09.80#ibcon#about to clear, iclass 22 cls_cnt 0 2006.203.08:04:09.80#ibcon#cleared, iclass 22 cls_cnt 0 2006.203.08:04:09.80$vc4f8/valo=3,672.99 2006.203.08:04:09.80#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.203.08:04:09.80#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.203.08:04:09.80#ibcon#ireg 17 cls_cnt 0 2006.203.08:04:09.80#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.203.08:04:09.80#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.203.08:04:09.80#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.203.08:04:09.80#ibcon#enter wrdev, iclass 24, count 0 2006.203.08:04:09.80#ibcon#first serial, iclass 24, count 0 2006.203.08:04:09.80#ibcon#enter sib2, iclass 24, count 0 2006.203.08:04:09.80#ibcon#flushed, iclass 24, count 0 2006.203.08:04:09.80#ibcon#about to write, iclass 24, count 0 2006.203.08:04:09.80#ibcon#wrote, iclass 24, count 0 2006.203.08:04:09.80#ibcon#about to read 3, iclass 24, count 0 2006.203.08:04:09.82#ibcon#read 3, iclass 24, count 0 2006.203.08:04:09.82#ibcon#about to read 4, iclass 24, count 0 2006.203.08:04:09.82#ibcon#read 4, iclass 24, count 0 2006.203.08:04:09.82#ibcon#about to read 5, iclass 24, count 0 2006.203.08:04:09.82#ibcon#read 5, iclass 24, count 0 2006.203.08:04:09.82#ibcon#about to read 6, iclass 24, count 0 2006.203.08:04:09.82#ibcon#read 6, iclass 24, count 0 2006.203.08:04:09.82#ibcon#end of sib2, iclass 24, count 0 2006.203.08:04:09.82#ibcon#*mode == 0, iclass 24, count 0 2006.203.08:04:09.82#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.203.08:04:09.82#ibcon#[26=FRQ=03,672.99\r\n] 2006.203.08:04:09.82#ibcon#*before write, iclass 24, count 0 2006.203.08:04:09.82#ibcon#enter sib2, iclass 24, count 0 2006.203.08:04:09.82#ibcon#flushed, iclass 24, count 0 2006.203.08:04:09.82#ibcon#about to write, iclass 24, count 0 2006.203.08:04:09.82#ibcon#wrote, iclass 24, count 0 2006.203.08:04:09.82#ibcon#about to read 3, iclass 24, count 0 2006.203.08:04:09.87#ibcon#read 3, iclass 24, count 0 2006.203.08:04:09.87#ibcon#about to read 4, iclass 24, count 0 2006.203.08:04:09.87#ibcon#read 4, iclass 24, count 0 2006.203.08:04:09.87#ibcon#about to read 5, iclass 24, count 0 2006.203.08:04:09.87#ibcon#read 5, iclass 24, count 0 2006.203.08:04:09.87#ibcon#about to read 6, iclass 24, count 0 2006.203.08:04:09.87#ibcon#read 6, iclass 24, count 0 2006.203.08:04:09.87#ibcon#end of sib2, iclass 24, count 0 2006.203.08:04:09.87#ibcon#*after write, iclass 24, count 0 2006.203.08:04:09.87#ibcon#*before return 0, iclass 24, count 0 2006.203.08:04:09.87#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.203.08:04:09.87#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.203.08:04:09.87#ibcon#about to clear, iclass 24 cls_cnt 0 2006.203.08:04:09.87#ibcon#cleared, iclass 24 cls_cnt 0 2006.203.08:04:09.87$vc4f8/va=3,8 2006.203.08:04:09.87#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.203.08:04:09.87#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.203.08:04:09.87#ibcon#ireg 11 cls_cnt 2 2006.203.08:04:09.87#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.203.08:04:09.92#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.203.08:04:09.92#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.203.08:04:09.92#ibcon#enter wrdev, iclass 26, count 2 2006.203.08:04:09.92#ibcon#first serial, iclass 26, count 2 2006.203.08:04:09.92#ibcon#enter sib2, iclass 26, count 2 2006.203.08:04:09.92#ibcon#flushed, iclass 26, count 2 2006.203.08:04:09.92#ibcon#about to write, iclass 26, count 2 2006.203.08:04:09.92#ibcon#wrote, iclass 26, count 2 2006.203.08:04:09.92#ibcon#about to read 3, iclass 26, count 2 2006.203.08:04:09.94#ibcon#read 3, iclass 26, count 2 2006.203.08:04:09.94#ibcon#about to read 4, iclass 26, count 2 2006.203.08:04:09.94#ibcon#read 4, iclass 26, count 2 2006.203.08:04:09.94#ibcon#about to read 5, iclass 26, count 2 2006.203.08:04:09.94#ibcon#read 5, iclass 26, count 2 2006.203.08:04:09.94#ibcon#about to read 6, iclass 26, count 2 2006.203.08:04:09.94#ibcon#read 6, iclass 26, count 2 2006.203.08:04:09.94#ibcon#end of sib2, iclass 26, count 2 2006.203.08:04:09.94#ibcon#*mode == 0, iclass 26, count 2 2006.203.08:04:09.94#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.203.08:04:09.94#ibcon#[25=AT03-08\r\n] 2006.203.08:04:09.94#ibcon#*before write, iclass 26, count 2 2006.203.08:04:09.94#ibcon#enter sib2, iclass 26, count 2 2006.203.08:04:09.94#ibcon#flushed, iclass 26, count 2 2006.203.08:04:09.94#ibcon#about to write, iclass 26, count 2 2006.203.08:04:09.94#ibcon#wrote, iclass 26, count 2 2006.203.08:04:09.94#ibcon#about to read 3, iclass 26, count 2 2006.203.08:04:09.97#ibcon#read 3, iclass 26, count 2 2006.203.08:04:09.97#ibcon#about to read 4, iclass 26, count 2 2006.203.08:04:09.97#ibcon#read 4, iclass 26, count 2 2006.203.08:04:09.97#ibcon#about to read 5, iclass 26, count 2 2006.203.08:04:09.97#ibcon#read 5, iclass 26, count 2 2006.203.08:04:09.97#ibcon#about to read 6, iclass 26, count 2 2006.203.08:04:09.97#ibcon#read 6, iclass 26, count 2 2006.203.08:04:09.97#ibcon#end of sib2, iclass 26, count 2 2006.203.08:04:09.97#ibcon#*after write, iclass 26, count 2 2006.203.08:04:09.97#ibcon#*before return 0, iclass 26, count 2 2006.203.08:04:09.97#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.203.08:04:09.97#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.203.08:04:09.97#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.203.08:04:09.97#ibcon#ireg 7 cls_cnt 0 2006.203.08:04:09.97#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.203.08:04:10.09#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.203.08:04:10.09#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.203.08:04:10.09#ibcon#enter wrdev, iclass 26, count 0 2006.203.08:04:10.09#ibcon#first serial, iclass 26, count 0 2006.203.08:04:10.09#ibcon#enter sib2, iclass 26, count 0 2006.203.08:04:10.09#ibcon#flushed, iclass 26, count 0 2006.203.08:04:10.09#ibcon#about to write, iclass 26, count 0 2006.203.08:04:10.09#ibcon#wrote, iclass 26, count 0 2006.203.08:04:10.09#ibcon#about to read 3, iclass 26, count 0 2006.203.08:04:10.11#ibcon#read 3, iclass 26, count 0 2006.203.08:04:10.11#ibcon#about to read 4, iclass 26, count 0 2006.203.08:04:10.11#ibcon#read 4, iclass 26, count 0 2006.203.08:04:10.11#ibcon#about to read 5, iclass 26, count 0 2006.203.08:04:10.11#ibcon#read 5, iclass 26, count 0 2006.203.08:04:10.11#ibcon#about to read 6, iclass 26, count 0 2006.203.08:04:10.11#ibcon#read 6, iclass 26, count 0 2006.203.08:04:10.11#ibcon#end of sib2, iclass 26, count 0 2006.203.08:04:10.11#ibcon#*mode == 0, iclass 26, count 0 2006.203.08:04:10.11#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.203.08:04:10.11#ibcon#[25=USB\r\n] 2006.203.08:04:10.11#ibcon#*before write, iclass 26, count 0 2006.203.08:04:10.11#ibcon#enter sib2, iclass 26, count 0 2006.203.08:04:10.11#ibcon#flushed, iclass 26, count 0 2006.203.08:04:10.11#ibcon#about to write, iclass 26, count 0 2006.203.08:04:10.11#ibcon#wrote, iclass 26, count 0 2006.203.08:04:10.11#ibcon#about to read 3, iclass 26, count 0 2006.203.08:04:10.14#ibcon#read 3, iclass 26, count 0 2006.203.08:04:10.14#ibcon#about to read 4, iclass 26, count 0 2006.203.08:04:10.14#ibcon#read 4, iclass 26, count 0 2006.203.08:04:10.14#ibcon#about to read 5, iclass 26, count 0 2006.203.08:04:10.14#ibcon#read 5, iclass 26, count 0 2006.203.08:04:10.14#ibcon#about to read 6, iclass 26, count 0 2006.203.08:04:10.14#ibcon#read 6, iclass 26, count 0 2006.203.08:04:10.14#ibcon#end of sib2, iclass 26, count 0 2006.203.08:04:10.14#ibcon#*after write, iclass 26, count 0 2006.203.08:04:10.14#ibcon#*before return 0, iclass 26, count 0 2006.203.08:04:10.14#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.203.08:04:10.14#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.203.08:04:10.14#ibcon#about to clear, iclass 26 cls_cnt 0 2006.203.08:04:10.14#ibcon#cleared, iclass 26 cls_cnt 0 2006.203.08:04:10.14$vc4f8/valo=4,832.99 2006.203.08:04:10.14#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.203.08:04:10.14#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.203.08:04:10.14#ibcon#ireg 17 cls_cnt 0 2006.203.08:04:10.14#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.203.08:04:10.14#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.203.08:04:10.14#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.203.08:04:10.14#ibcon#enter wrdev, iclass 28, count 0 2006.203.08:04:10.14#ibcon#first serial, iclass 28, count 0 2006.203.08:04:10.14#ibcon#enter sib2, iclass 28, count 0 2006.203.08:04:10.14#ibcon#flushed, iclass 28, count 0 2006.203.08:04:10.14#ibcon#about to write, iclass 28, count 0 2006.203.08:04:10.14#ibcon#wrote, iclass 28, count 0 2006.203.08:04:10.14#ibcon#about to read 3, iclass 28, count 0 2006.203.08:04:10.16#ibcon#read 3, iclass 28, count 0 2006.203.08:04:10.16#ibcon#about to read 4, iclass 28, count 0 2006.203.08:04:10.16#ibcon#read 4, iclass 28, count 0 2006.203.08:04:10.16#ibcon#about to read 5, iclass 28, count 0 2006.203.08:04:10.16#ibcon#read 5, iclass 28, count 0 2006.203.08:04:10.16#ibcon#about to read 6, iclass 28, count 0 2006.203.08:04:10.16#ibcon#read 6, iclass 28, count 0 2006.203.08:04:10.16#ibcon#end of sib2, iclass 28, count 0 2006.203.08:04:10.16#ibcon#*mode == 0, iclass 28, count 0 2006.203.08:04:10.16#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.203.08:04:10.16#ibcon#[26=FRQ=04,832.99\r\n] 2006.203.08:04:10.16#ibcon#*before write, iclass 28, count 0 2006.203.08:04:10.16#ibcon#enter sib2, iclass 28, count 0 2006.203.08:04:10.16#ibcon#flushed, iclass 28, count 0 2006.203.08:04:10.16#ibcon#about to write, iclass 28, count 0 2006.203.08:04:10.16#ibcon#wrote, iclass 28, count 0 2006.203.08:04:10.16#ibcon#about to read 3, iclass 28, count 0 2006.203.08:04:10.20#ibcon#read 3, iclass 28, count 0 2006.203.08:04:10.20#ibcon#about to read 4, iclass 28, count 0 2006.203.08:04:10.20#ibcon#read 4, iclass 28, count 0 2006.203.08:04:10.20#ibcon#about to read 5, iclass 28, count 0 2006.203.08:04:10.20#ibcon#read 5, iclass 28, count 0 2006.203.08:04:10.20#ibcon#about to read 6, iclass 28, count 0 2006.203.08:04:10.20#ibcon#read 6, iclass 28, count 0 2006.203.08:04:10.20#ibcon#end of sib2, iclass 28, count 0 2006.203.08:04:10.20#ibcon#*after write, iclass 28, count 0 2006.203.08:04:10.20#ibcon#*before return 0, iclass 28, count 0 2006.203.08:04:10.20#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.203.08:04:10.20#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.203.08:04:10.20#ibcon#about to clear, iclass 28 cls_cnt 0 2006.203.08:04:10.20#ibcon#cleared, iclass 28 cls_cnt 0 2006.203.08:04:10.20$vc4f8/va=4,7 2006.203.08:04:10.20#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.203.08:04:10.20#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.203.08:04:10.20#ibcon#ireg 11 cls_cnt 2 2006.203.08:04:10.20#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.203.08:04:10.26#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.203.08:04:10.26#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.203.08:04:10.26#ibcon#enter wrdev, iclass 30, count 2 2006.203.08:04:10.26#ibcon#first serial, iclass 30, count 2 2006.203.08:04:10.26#ibcon#enter sib2, iclass 30, count 2 2006.203.08:04:10.26#ibcon#flushed, iclass 30, count 2 2006.203.08:04:10.26#ibcon#about to write, iclass 30, count 2 2006.203.08:04:10.26#ibcon#wrote, iclass 30, count 2 2006.203.08:04:10.26#ibcon#about to read 3, iclass 30, count 2 2006.203.08:04:10.28#ibcon#read 3, iclass 30, count 2 2006.203.08:04:10.28#ibcon#about to read 4, iclass 30, count 2 2006.203.08:04:10.28#ibcon#read 4, iclass 30, count 2 2006.203.08:04:10.28#ibcon#about to read 5, iclass 30, count 2 2006.203.08:04:10.28#ibcon#read 5, iclass 30, count 2 2006.203.08:04:10.28#ibcon#about to read 6, iclass 30, count 2 2006.203.08:04:10.28#ibcon#read 6, iclass 30, count 2 2006.203.08:04:10.28#ibcon#end of sib2, iclass 30, count 2 2006.203.08:04:10.28#ibcon#*mode == 0, iclass 30, count 2 2006.203.08:04:10.28#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.203.08:04:10.28#ibcon#[25=AT04-07\r\n] 2006.203.08:04:10.28#ibcon#*before write, iclass 30, count 2 2006.203.08:04:10.28#ibcon#enter sib2, iclass 30, count 2 2006.203.08:04:10.28#ibcon#flushed, iclass 30, count 2 2006.203.08:04:10.28#ibcon#about to write, iclass 30, count 2 2006.203.08:04:10.28#ibcon#wrote, iclass 30, count 2 2006.203.08:04:10.28#ibcon#about to read 3, iclass 30, count 2 2006.203.08:04:10.31#ibcon#read 3, iclass 30, count 2 2006.203.08:04:10.31#ibcon#about to read 4, iclass 30, count 2 2006.203.08:04:10.31#ibcon#read 4, iclass 30, count 2 2006.203.08:04:10.31#ibcon#about to read 5, iclass 30, count 2 2006.203.08:04:10.31#ibcon#read 5, iclass 30, count 2 2006.203.08:04:10.31#ibcon#about to read 6, iclass 30, count 2 2006.203.08:04:10.31#ibcon#read 6, iclass 30, count 2 2006.203.08:04:10.31#ibcon#end of sib2, iclass 30, count 2 2006.203.08:04:10.31#ibcon#*after write, iclass 30, count 2 2006.203.08:04:10.31#ibcon#*before return 0, iclass 30, count 2 2006.203.08:04:10.31#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.203.08:04:10.31#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.203.08:04:10.31#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.203.08:04:10.31#ibcon#ireg 7 cls_cnt 0 2006.203.08:04:10.31#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.203.08:04:10.43#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.203.08:04:10.43#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.203.08:04:10.43#ibcon#enter wrdev, iclass 30, count 0 2006.203.08:04:10.43#ibcon#first serial, iclass 30, count 0 2006.203.08:04:10.43#ibcon#enter sib2, iclass 30, count 0 2006.203.08:04:10.43#ibcon#flushed, iclass 30, count 0 2006.203.08:04:10.43#ibcon#about to write, iclass 30, count 0 2006.203.08:04:10.43#ibcon#wrote, iclass 30, count 0 2006.203.08:04:10.43#ibcon#about to read 3, iclass 30, count 0 2006.203.08:04:10.45#ibcon#read 3, iclass 30, count 0 2006.203.08:04:10.45#ibcon#about to read 4, iclass 30, count 0 2006.203.08:04:10.45#ibcon#read 4, iclass 30, count 0 2006.203.08:04:10.45#ibcon#about to read 5, iclass 30, count 0 2006.203.08:04:10.45#ibcon#read 5, iclass 30, count 0 2006.203.08:04:10.45#ibcon#about to read 6, iclass 30, count 0 2006.203.08:04:10.45#ibcon#read 6, iclass 30, count 0 2006.203.08:04:10.45#ibcon#end of sib2, iclass 30, count 0 2006.203.08:04:10.45#ibcon#*mode == 0, iclass 30, count 0 2006.203.08:04:10.45#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.203.08:04:10.45#ibcon#[25=USB\r\n] 2006.203.08:04:10.45#ibcon#*before write, iclass 30, count 0 2006.203.08:04:10.45#ibcon#enter sib2, iclass 30, count 0 2006.203.08:04:10.45#ibcon#flushed, iclass 30, count 0 2006.203.08:04:10.45#ibcon#about to write, iclass 30, count 0 2006.203.08:04:10.45#ibcon#wrote, iclass 30, count 0 2006.203.08:04:10.45#ibcon#about to read 3, iclass 30, count 0 2006.203.08:04:10.48#ibcon#read 3, iclass 30, count 0 2006.203.08:04:10.48#ibcon#about to read 4, iclass 30, count 0 2006.203.08:04:10.48#ibcon#read 4, iclass 30, count 0 2006.203.08:04:10.48#ibcon#about to read 5, iclass 30, count 0 2006.203.08:04:10.48#ibcon#read 5, iclass 30, count 0 2006.203.08:04:10.48#ibcon#about to read 6, iclass 30, count 0 2006.203.08:04:10.48#ibcon#read 6, iclass 30, count 0 2006.203.08:04:10.48#ibcon#end of sib2, iclass 30, count 0 2006.203.08:04:10.48#ibcon#*after write, iclass 30, count 0 2006.203.08:04:10.48#ibcon#*before return 0, iclass 30, count 0 2006.203.08:04:10.48#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.203.08:04:10.48#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.203.08:04:10.48#ibcon#about to clear, iclass 30 cls_cnt 0 2006.203.08:04:10.48#ibcon#cleared, iclass 30 cls_cnt 0 2006.203.08:04:10.48$vc4f8/valo=5,652.99 2006.203.08:04:10.48#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.203.08:04:10.48#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.203.08:04:10.48#ibcon#ireg 17 cls_cnt 0 2006.203.08:04:10.48#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.203.08:04:10.48#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.203.08:04:10.48#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.203.08:04:10.48#ibcon#enter wrdev, iclass 32, count 0 2006.203.08:04:10.48#ibcon#first serial, iclass 32, count 0 2006.203.08:04:10.48#ibcon#enter sib2, iclass 32, count 0 2006.203.08:04:10.48#ibcon#flushed, iclass 32, count 0 2006.203.08:04:10.48#ibcon#about to write, iclass 32, count 0 2006.203.08:04:10.48#ibcon#wrote, iclass 32, count 0 2006.203.08:04:10.48#ibcon#about to read 3, iclass 32, count 0 2006.203.08:04:10.50#ibcon#read 3, iclass 32, count 0 2006.203.08:04:10.50#ibcon#about to read 4, iclass 32, count 0 2006.203.08:04:10.50#ibcon#read 4, iclass 32, count 0 2006.203.08:04:10.50#ibcon#about to read 5, iclass 32, count 0 2006.203.08:04:10.50#ibcon#read 5, iclass 32, count 0 2006.203.08:04:10.50#ibcon#about to read 6, iclass 32, count 0 2006.203.08:04:10.50#ibcon#read 6, iclass 32, count 0 2006.203.08:04:10.50#ibcon#end of sib2, iclass 32, count 0 2006.203.08:04:10.50#ibcon#*mode == 0, iclass 32, count 0 2006.203.08:04:10.50#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.203.08:04:10.50#ibcon#[26=FRQ=05,652.99\r\n] 2006.203.08:04:10.50#ibcon#*before write, iclass 32, count 0 2006.203.08:04:10.50#ibcon#enter sib2, iclass 32, count 0 2006.203.08:04:10.50#ibcon#flushed, iclass 32, count 0 2006.203.08:04:10.50#ibcon#about to write, iclass 32, count 0 2006.203.08:04:10.50#ibcon#wrote, iclass 32, count 0 2006.203.08:04:10.50#ibcon#about to read 3, iclass 32, count 0 2006.203.08:04:10.55#ibcon#read 3, iclass 32, count 0 2006.203.08:04:10.55#ibcon#about to read 4, iclass 32, count 0 2006.203.08:04:10.55#ibcon#read 4, iclass 32, count 0 2006.203.08:04:10.55#ibcon#about to read 5, iclass 32, count 0 2006.203.08:04:10.55#ibcon#read 5, iclass 32, count 0 2006.203.08:04:10.55#ibcon#about to read 6, iclass 32, count 0 2006.203.08:04:10.55#ibcon#read 6, iclass 32, count 0 2006.203.08:04:10.55#ibcon#end of sib2, iclass 32, count 0 2006.203.08:04:10.55#ibcon#*after write, iclass 32, count 0 2006.203.08:04:10.55#ibcon#*before return 0, iclass 32, count 0 2006.203.08:04:10.55#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.203.08:04:10.55#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.203.08:04:10.55#ibcon#about to clear, iclass 32 cls_cnt 0 2006.203.08:04:10.55#ibcon#cleared, iclass 32 cls_cnt 0 2006.203.08:04:10.55$vc4f8/va=5,7 2006.203.08:04:10.55#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.203.08:04:10.55#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.203.08:04:10.55#ibcon#ireg 11 cls_cnt 2 2006.203.08:04:10.55#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.203.08:04:10.60#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.203.08:04:10.60#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.203.08:04:10.60#ibcon#enter wrdev, iclass 34, count 2 2006.203.08:04:10.60#ibcon#first serial, iclass 34, count 2 2006.203.08:04:10.60#ibcon#enter sib2, iclass 34, count 2 2006.203.08:04:10.60#ibcon#flushed, iclass 34, count 2 2006.203.08:04:10.60#ibcon#about to write, iclass 34, count 2 2006.203.08:04:10.60#ibcon#wrote, iclass 34, count 2 2006.203.08:04:10.60#ibcon#about to read 3, iclass 34, count 2 2006.203.08:04:10.62#ibcon#read 3, iclass 34, count 2 2006.203.08:04:10.62#ibcon#about to read 4, iclass 34, count 2 2006.203.08:04:10.62#ibcon#read 4, iclass 34, count 2 2006.203.08:04:10.62#ibcon#about to read 5, iclass 34, count 2 2006.203.08:04:10.62#ibcon#read 5, iclass 34, count 2 2006.203.08:04:10.62#ibcon#about to read 6, iclass 34, count 2 2006.203.08:04:10.62#ibcon#read 6, iclass 34, count 2 2006.203.08:04:10.62#ibcon#end of sib2, iclass 34, count 2 2006.203.08:04:10.62#ibcon#*mode == 0, iclass 34, count 2 2006.203.08:04:10.62#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.203.08:04:10.62#ibcon#[25=AT05-07\r\n] 2006.203.08:04:10.62#ibcon#*before write, iclass 34, count 2 2006.203.08:04:10.62#ibcon#enter sib2, iclass 34, count 2 2006.203.08:04:10.62#ibcon#flushed, iclass 34, count 2 2006.203.08:04:10.62#ibcon#about to write, iclass 34, count 2 2006.203.08:04:10.62#ibcon#wrote, iclass 34, count 2 2006.203.08:04:10.62#ibcon#about to read 3, iclass 34, count 2 2006.203.08:04:10.65#ibcon#read 3, iclass 34, count 2 2006.203.08:04:10.65#ibcon#about to read 4, iclass 34, count 2 2006.203.08:04:10.65#ibcon#read 4, iclass 34, count 2 2006.203.08:04:10.65#ibcon#about to read 5, iclass 34, count 2 2006.203.08:04:10.65#ibcon#read 5, iclass 34, count 2 2006.203.08:04:10.65#ibcon#about to read 6, iclass 34, count 2 2006.203.08:04:10.65#ibcon#read 6, iclass 34, count 2 2006.203.08:04:10.65#ibcon#end of sib2, iclass 34, count 2 2006.203.08:04:10.65#ibcon#*after write, iclass 34, count 2 2006.203.08:04:10.65#ibcon#*before return 0, iclass 34, count 2 2006.203.08:04:10.65#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.203.08:04:10.65#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.203.08:04:10.65#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.203.08:04:10.65#ibcon#ireg 7 cls_cnt 0 2006.203.08:04:10.65#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.203.08:04:10.77#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.203.08:04:10.77#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.203.08:04:10.77#ibcon#enter wrdev, iclass 34, count 0 2006.203.08:04:10.77#ibcon#first serial, iclass 34, count 0 2006.203.08:04:10.77#ibcon#enter sib2, iclass 34, count 0 2006.203.08:04:10.77#ibcon#flushed, iclass 34, count 0 2006.203.08:04:10.77#ibcon#about to write, iclass 34, count 0 2006.203.08:04:10.77#ibcon#wrote, iclass 34, count 0 2006.203.08:04:10.77#ibcon#about to read 3, iclass 34, count 0 2006.203.08:04:10.79#ibcon#read 3, iclass 34, count 0 2006.203.08:04:10.79#ibcon#about to read 4, iclass 34, count 0 2006.203.08:04:10.79#ibcon#read 4, iclass 34, count 0 2006.203.08:04:10.79#ibcon#about to read 5, iclass 34, count 0 2006.203.08:04:10.79#ibcon#read 5, iclass 34, count 0 2006.203.08:04:10.79#ibcon#about to read 6, iclass 34, count 0 2006.203.08:04:10.79#ibcon#read 6, iclass 34, count 0 2006.203.08:04:10.79#ibcon#end of sib2, iclass 34, count 0 2006.203.08:04:10.79#ibcon#*mode == 0, iclass 34, count 0 2006.203.08:04:10.79#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.203.08:04:10.79#ibcon#[25=USB\r\n] 2006.203.08:04:10.79#ibcon#*before write, iclass 34, count 0 2006.203.08:04:10.79#ibcon#enter sib2, iclass 34, count 0 2006.203.08:04:10.79#ibcon#flushed, iclass 34, count 0 2006.203.08:04:10.79#ibcon#about to write, iclass 34, count 0 2006.203.08:04:10.79#ibcon#wrote, iclass 34, count 0 2006.203.08:04:10.79#ibcon#about to read 3, iclass 34, count 0 2006.203.08:04:10.82#ibcon#read 3, iclass 34, count 0 2006.203.08:04:10.82#ibcon#about to read 4, iclass 34, count 0 2006.203.08:04:10.82#ibcon#read 4, iclass 34, count 0 2006.203.08:04:10.82#ibcon#about to read 5, iclass 34, count 0 2006.203.08:04:10.82#ibcon#read 5, iclass 34, count 0 2006.203.08:04:10.82#ibcon#about to read 6, iclass 34, count 0 2006.203.08:04:10.82#ibcon#read 6, iclass 34, count 0 2006.203.08:04:10.82#ibcon#end of sib2, iclass 34, count 0 2006.203.08:04:10.82#ibcon#*after write, iclass 34, count 0 2006.203.08:04:10.82#ibcon#*before return 0, iclass 34, count 0 2006.203.08:04:10.82#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.203.08:04:10.82#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.203.08:04:10.82#ibcon#about to clear, iclass 34 cls_cnt 0 2006.203.08:04:10.82#ibcon#cleared, iclass 34 cls_cnt 0 2006.203.08:04:10.82$vc4f8/valo=6,772.99 2006.203.08:04:10.82#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.203.08:04:10.82#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.203.08:04:10.82#ibcon#ireg 17 cls_cnt 0 2006.203.08:04:10.82#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.203.08:04:10.82#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.203.08:04:10.82#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.203.08:04:10.82#ibcon#enter wrdev, iclass 36, count 0 2006.203.08:04:10.82#ibcon#first serial, iclass 36, count 0 2006.203.08:04:10.82#ibcon#enter sib2, iclass 36, count 0 2006.203.08:04:10.82#ibcon#flushed, iclass 36, count 0 2006.203.08:04:10.82#ibcon#about to write, iclass 36, count 0 2006.203.08:04:10.82#ibcon#wrote, iclass 36, count 0 2006.203.08:04:10.82#ibcon#about to read 3, iclass 36, count 0 2006.203.08:04:10.84#ibcon#read 3, iclass 36, count 0 2006.203.08:04:10.84#ibcon#about to read 4, iclass 36, count 0 2006.203.08:04:10.84#ibcon#read 4, iclass 36, count 0 2006.203.08:04:10.84#ibcon#about to read 5, iclass 36, count 0 2006.203.08:04:10.84#ibcon#read 5, iclass 36, count 0 2006.203.08:04:10.84#ibcon#about to read 6, iclass 36, count 0 2006.203.08:04:10.84#ibcon#read 6, iclass 36, count 0 2006.203.08:04:10.84#ibcon#end of sib2, iclass 36, count 0 2006.203.08:04:10.84#ibcon#*mode == 0, iclass 36, count 0 2006.203.08:04:10.84#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.203.08:04:10.84#ibcon#[26=FRQ=06,772.99\r\n] 2006.203.08:04:10.84#ibcon#*before write, iclass 36, count 0 2006.203.08:04:10.84#ibcon#enter sib2, iclass 36, count 0 2006.203.08:04:10.84#ibcon#flushed, iclass 36, count 0 2006.203.08:04:10.84#ibcon#about to write, iclass 36, count 0 2006.203.08:04:10.84#ibcon#wrote, iclass 36, count 0 2006.203.08:04:10.84#ibcon#about to read 3, iclass 36, count 0 2006.203.08:04:10.88#ibcon#read 3, iclass 36, count 0 2006.203.08:04:10.88#ibcon#about to read 4, iclass 36, count 0 2006.203.08:04:10.88#ibcon#read 4, iclass 36, count 0 2006.203.08:04:10.88#ibcon#about to read 5, iclass 36, count 0 2006.203.08:04:10.88#ibcon#read 5, iclass 36, count 0 2006.203.08:04:10.88#ibcon#about to read 6, iclass 36, count 0 2006.203.08:04:10.88#ibcon#read 6, iclass 36, count 0 2006.203.08:04:10.88#ibcon#end of sib2, iclass 36, count 0 2006.203.08:04:10.88#ibcon#*after write, iclass 36, count 0 2006.203.08:04:10.88#ibcon#*before return 0, iclass 36, count 0 2006.203.08:04:10.88#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.203.08:04:10.88#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.203.08:04:10.88#ibcon#about to clear, iclass 36 cls_cnt 0 2006.203.08:04:10.88#ibcon#cleared, iclass 36 cls_cnt 0 2006.203.08:04:10.88$vc4f8/va=6,6 2006.203.08:04:10.88#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.203.08:04:10.88#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.203.08:04:10.88#ibcon#ireg 11 cls_cnt 2 2006.203.08:04:10.88#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.203.08:04:10.94#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.203.08:04:10.94#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.203.08:04:10.94#ibcon#enter wrdev, iclass 38, count 2 2006.203.08:04:10.94#ibcon#first serial, iclass 38, count 2 2006.203.08:04:10.94#ibcon#enter sib2, iclass 38, count 2 2006.203.08:04:10.94#ibcon#flushed, iclass 38, count 2 2006.203.08:04:10.94#ibcon#about to write, iclass 38, count 2 2006.203.08:04:10.94#ibcon#wrote, iclass 38, count 2 2006.203.08:04:10.94#ibcon#about to read 3, iclass 38, count 2 2006.203.08:04:10.96#ibcon#read 3, iclass 38, count 2 2006.203.08:04:10.96#ibcon#about to read 4, iclass 38, count 2 2006.203.08:04:10.96#ibcon#read 4, iclass 38, count 2 2006.203.08:04:10.96#ibcon#about to read 5, iclass 38, count 2 2006.203.08:04:10.96#ibcon#read 5, iclass 38, count 2 2006.203.08:04:10.96#ibcon#about to read 6, iclass 38, count 2 2006.203.08:04:10.96#ibcon#read 6, iclass 38, count 2 2006.203.08:04:10.96#ibcon#end of sib2, iclass 38, count 2 2006.203.08:04:10.96#ibcon#*mode == 0, iclass 38, count 2 2006.203.08:04:10.96#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.203.08:04:10.96#ibcon#[25=AT06-06\r\n] 2006.203.08:04:10.96#ibcon#*before write, iclass 38, count 2 2006.203.08:04:10.96#ibcon#enter sib2, iclass 38, count 2 2006.203.08:04:10.96#ibcon#flushed, iclass 38, count 2 2006.203.08:04:10.96#ibcon#about to write, iclass 38, count 2 2006.203.08:04:10.96#ibcon#wrote, iclass 38, count 2 2006.203.08:04:10.96#ibcon#about to read 3, iclass 38, count 2 2006.203.08:04:10.99#ibcon#read 3, iclass 38, count 2 2006.203.08:04:10.99#ibcon#about to read 4, iclass 38, count 2 2006.203.08:04:10.99#ibcon#read 4, iclass 38, count 2 2006.203.08:04:10.99#ibcon#about to read 5, iclass 38, count 2 2006.203.08:04:10.99#ibcon#read 5, iclass 38, count 2 2006.203.08:04:10.99#ibcon#about to read 6, iclass 38, count 2 2006.203.08:04:10.99#ibcon#read 6, iclass 38, count 2 2006.203.08:04:10.99#ibcon#end of sib2, iclass 38, count 2 2006.203.08:04:10.99#ibcon#*after write, iclass 38, count 2 2006.203.08:04:10.99#ibcon#*before return 0, iclass 38, count 2 2006.203.08:04:10.99#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.203.08:04:10.99#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.203.08:04:10.99#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.203.08:04:10.99#ibcon#ireg 7 cls_cnt 0 2006.203.08:04:10.99#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.203.08:04:11.11#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.203.08:04:11.11#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.203.08:04:11.11#ibcon#enter wrdev, iclass 38, count 0 2006.203.08:04:11.11#ibcon#first serial, iclass 38, count 0 2006.203.08:04:11.11#ibcon#enter sib2, iclass 38, count 0 2006.203.08:04:11.11#ibcon#flushed, iclass 38, count 0 2006.203.08:04:11.11#ibcon#about to write, iclass 38, count 0 2006.203.08:04:11.11#ibcon#wrote, iclass 38, count 0 2006.203.08:04:11.11#ibcon#about to read 3, iclass 38, count 0 2006.203.08:04:11.13#ibcon#read 3, iclass 38, count 0 2006.203.08:04:11.13#ibcon#about to read 4, iclass 38, count 0 2006.203.08:04:11.13#ibcon#read 4, iclass 38, count 0 2006.203.08:04:11.13#ibcon#about to read 5, iclass 38, count 0 2006.203.08:04:11.13#ibcon#read 5, iclass 38, count 0 2006.203.08:04:11.13#ibcon#about to read 6, iclass 38, count 0 2006.203.08:04:11.13#ibcon#read 6, iclass 38, count 0 2006.203.08:04:11.13#ibcon#end of sib2, iclass 38, count 0 2006.203.08:04:11.13#ibcon#*mode == 0, iclass 38, count 0 2006.203.08:04:11.13#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.203.08:04:11.13#ibcon#[25=USB\r\n] 2006.203.08:04:11.13#ibcon#*before write, iclass 38, count 0 2006.203.08:04:11.13#ibcon#enter sib2, iclass 38, count 0 2006.203.08:04:11.13#ibcon#flushed, iclass 38, count 0 2006.203.08:04:11.13#ibcon#about to write, iclass 38, count 0 2006.203.08:04:11.13#ibcon#wrote, iclass 38, count 0 2006.203.08:04:11.13#ibcon#about to read 3, iclass 38, count 0 2006.203.08:04:11.16#ibcon#read 3, iclass 38, count 0 2006.203.08:04:11.16#ibcon#about to read 4, iclass 38, count 0 2006.203.08:04:11.16#ibcon#read 4, iclass 38, count 0 2006.203.08:04:11.16#ibcon#about to read 5, iclass 38, count 0 2006.203.08:04:11.16#ibcon#read 5, iclass 38, count 0 2006.203.08:04:11.16#ibcon#about to read 6, iclass 38, count 0 2006.203.08:04:11.16#ibcon#read 6, iclass 38, count 0 2006.203.08:04:11.16#ibcon#end of sib2, iclass 38, count 0 2006.203.08:04:11.16#ibcon#*after write, iclass 38, count 0 2006.203.08:04:11.16#ibcon#*before return 0, iclass 38, count 0 2006.203.08:04:11.16#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.203.08:04:11.16#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.203.08:04:11.16#ibcon#about to clear, iclass 38 cls_cnt 0 2006.203.08:04:11.16#ibcon#cleared, iclass 38 cls_cnt 0 2006.203.08:04:11.16$vc4f8/valo=7,832.99 2006.203.08:04:11.16#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.203.08:04:11.16#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.203.08:04:11.16#ibcon#ireg 17 cls_cnt 0 2006.203.08:04:11.16#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.203.08:04:11.16#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.203.08:04:11.16#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.203.08:04:11.16#ibcon#enter wrdev, iclass 40, count 0 2006.203.08:04:11.16#ibcon#first serial, iclass 40, count 0 2006.203.08:04:11.16#ibcon#enter sib2, iclass 40, count 0 2006.203.08:04:11.16#ibcon#flushed, iclass 40, count 0 2006.203.08:04:11.16#ibcon#about to write, iclass 40, count 0 2006.203.08:04:11.16#ibcon#wrote, iclass 40, count 0 2006.203.08:04:11.16#ibcon#about to read 3, iclass 40, count 0 2006.203.08:04:11.18#ibcon#read 3, iclass 40, count 0 2006.203.08:04:11.18#ibcon#about to read 4, iclass 40, count 0 2006.203.08:04:11.18#ibcon#read 4, iclass 40, count 0 2006.203.08:04:11.18#ibcon#about to read 5, iclass 40, count 0 2006.203.08:04:11.18#ibcon#read 5, iclass 40, count 0 2006.203.08:04:11.18#ibcon#about to read 6, iclass 40, count 0 2006.203.08:04:11.18#ibcon#read 6, iclass 40, count 0 2006.203.08:04:11.18#ibcon#end of sib2, iclass 40, count 0 2006.203.08:04:11.18#ibcon#*mode == 0, iclass 40, count 0 2006.203.08:04:11.18#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.203.08:04:11.18#ibcon#[26=FRQ=07,832.99\r\n] 2006.203.08:04:11.18#ibcon#*before write, iclass 40, count 0 2006.203.08:04:11.18#ibcon#enter sib2, iclass 40, count 0 2006.203.08:04:11.18#ibcon#flushed, iclass 40, count 0 2006.203.08:04:11.18#ibcon#about to write, iclass 40, count 0 2006.203.08:04:11.18#ibcon#wrote, iclass 40, count 0 2006.203.08:04:11.18#ibcon#about to read 3, iclass 40, count 0 2006.203.08:04:11.23#ibcon#read 3, iclass 40, count 0 2006.203.08:04:11.23#ibcon#about to read 4, iclass 40, count 0 2006.203.08:04:11.23#ibcon#read 4, iclass 40, count 0 2006.203.08:04:11.23#ibcon#about to read 5, iclass 40, count 0 2006.203.08:04:11.23#ibcon#read 5, iclass 40, count 0 2006.203.08:04:11.23#ibcon#about to read 6, iclass 40, count 0 2006.203.08:04:11.23#ibcon#read 6, iclass 40, count 0 2006.203.08:04:11.23#ibcon#end of sib2, iclass 40, count 0 2006.203.08:04:11.23#ibcon#*after write, iclass 40, count 0 2006.203.08:04:11.23#ibcon#*before return 0, iclass 40, count 0 2006.203.08:04:11.23#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.203.08:04:11.23#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.203.08:04:11.23#ibcon#about to clear, iclass 40 cls_cnt 0 2006.203.08:04:11.23#ibcon#cleared, iclass 40 cls_cnt 0 2006.203.08:04:11.23$vc4f8/va=7,7 2006.203.08:04:11.23#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.203.08:04:11.23#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.203.08:04:11.23#ibcon#ireg 11 cls_cnt 2 2006.203.08:04:11.23#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.203.08:04:11.28#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.203.08:04:11.28#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.203.08:04:11.28#ibcon#enter wrdev, iclass 4, count 2 2006.203.08:04:11.28#ibcon#first serial, iclass 4, count 2 2006.203.08:04:11.28#ibcon#enter sib2, iclass 4, count 2 2006.203.08:04:11.28#ibcon#flushed, iclass 4, count 2 2006.203.08:04:11.28#ibcon#about to write, iclass 4, count 2 2006.203.08:04:11.28#ibcon#wrote, iclass 4, count 2 2006.203.08:04:11.28#ibcon#about to read 3, iclass 4, count 2 2006.203.08:04:11.30#ibcon#read 3, iclass 4, count 2 2006.203.08:04:11.30#ibcon#about to read 4, iclass 4, count 2 2006.203.08:04:11.30#ibcon#read 4, iclass 4, count 2 2006.203.08:04:11.30#ibcon#about to read 5, iclass 4, count 2 2006.203.08:04:11.30#ibcon#read 5, iclass 4, count 2 2006.203.08:04:11.30#ibcon#about to read 6, iclass 4, count 2 2006.203.08:04:11.30#ibcon#read 6, iclass 4, count 2 2006.203.08:04:11.30#ibcon#end of sib2, iclass 4, count 2 2006.203.08:04:11.30#ibcon#*mode == 0, iclass 4, count 2 2006.203.08:04:11.30#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.203.08:04:11.30#ibcon#[25=AT07-07\r\n] 2006.203.08:04:11.30#ibcon#*before write, iclass 4, count 2 2006.203.08:04:11.30#ibcon#enter sib2, iclass 4, count 2 2006.203.08:04:11.30#ibcon#flushed, iclass 4, count 2 2006.203.08:04:11.30#ibcon#about to write, iclass 4, count 2 2006.203.08:04:11.30#ibcon#wrote, iclass 4, count 2 2006.203.08:04:11.30#ibcon#about to read 3, iclass 4, count 2 2006.203.08:04:11.33#ibcon#read 3, iclass 4, count 2 2006.203.08:04:11.33#ibcon#about to read 4, iclass 4, count 2 2006.203.08:04:11.33#ibcon#read 4, iclass 4, count 2 2006.203.08:04:11.33#ibcon#about to read 5, iclass 4, count 2 2006.203.08:04:11.33#ibcon#read 5, iclass 4, count 2 2006.203.08:04:11.33#ibcon#about to read 6, iclass 4, count 2 2006.203.08:04:11.33#ibcon#read 6, iclass 4, count 2 2006.203.08:04:11.33#ibcon#end of sib2, iclass 4, count 2 2006.203.08:04:11.33#ibcon#*after write, iclass 4, count 2 2006.203.08:04:11.33#ibcon#*before return 0, iclass 4, count 2 2006.203.08:04:11.33#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.203.08:04:11.33#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.203.08:04:11.33#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.203.08:04:11.33#ibcon#ireg 7 cls_cnt 0 2006.203.08:04:11.33#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.203.08:04:11.45#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.203.08:04:11.45#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.203.08:04:11.45#ibcon#enter wrdev, iclass 4, count 0 2006.203.08:04:11.45#ibcon#first serial, iclass 4, count 0 2006.203.08:04:11.45#ibcon#enter sib2, iclass 4, count 0 2006.203.08:04:11.45#ibcon#flushed, iclass 4, count 0 2006.203.08:04:11.45#ibcon#about to write, iclass 4, count 0 2006.203.08:04:11.45#ibcon#wrote, iclass 4, count 0 2006.203.08:04:11.45#ibcon#about to read 3, iclass 4, count 0 2006.203.08:04:11.47#ibcon#read 3, iclass 4, count 0 2006.203.08:04:11.47#ibcon#about to read 4, iclass 4, count 0 2006.203.08:04:11.47#ibcon#read 4, iclass 4, count 0 2006.203.08:04:11.47#ibcon#about to read 5, iclass 4, count 0 2006.203.08:04:11.47#ibcon#read 5, iclass 4, count 0 2006.203.08:04:11.47#ibcon#about to read 6, iclass 4, count 0 2006.203.08:04:11.47#ibcon#read 6, iclass 4, count 0 2006.203.08:04:11.47#ibcon#end of sib2, iclass 4, count 0 2006.203.08:04:11.47#ibcon#*mode == 0, iclass 4, count 0 2006.203.08:04:11.47#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.203.08:04:11.47#ibcon#[25=USB\r\n] 2006.203.08:04:11.47#ibcon#*before write, iclass 4, count 0 2006.203.08:04:11.47#ibcon#enter sib2, iclass 4, count 0 2006.203.08:04:11.47#ibcon#flushed, iclass 4, count 0 2006.203.08:04:11.47#ibcon#about to write, iclass 4, count 0 2006.203.08:04:11.47#ibcon#wrote, iclass 4, count 0 2006.203.08:04:11.47#ibcon#about to read 3, iclass 4, count 0 2006.203.08:04:11.50#ibcon#read 3, iclass 4, count 0 2006.203.08:04:11.50#ibcon#about to read 4, iclass 4, count 0 2006.203.08:04:11.50#ibcon#read 4, iclass 4, count 0 2006.203.08:04:11.50#ibcon#about to read 5, iclass 4, count 0 2006.203.08:04:11.50#ibcon#read 5, iclass 4, count 0 2006.203.08:04:11.50#ibcon#about to read 6, iclass 4, count 0 2006.203.08:04:11.50#ibcon#read 6, iclass 4, count 0 2006.203.08:04:11.50#ibcon#end of sib2, iclass 4, count 0 2006.203.08:04:11.50#ibcon#*after write, iclass 4, count 0 2006.203.08:04:11.50#ibcon#*before return 0, iclass 4, count 0 2006.203.08:04:11.50#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.203.08:04:11.50#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.203.08:04:11.50#ibcon#about to clear, iclass 4 cls_cnt 0 2006.203.08:04:11.50#ibcon#cleared, iclass 4 cls_cnt 0 2006.203.08:04:11.50$vc4f8/valo=8,852.99 2006.203.08:04:11.50#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.203.08:04:11.50#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.203.08:04:11.50#ibcon#ireg 17 cls_cnt 0 2006.203.08:04:11.50#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.203.08:04:11.50#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.203.08:04:11.50#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.203.08:04:11.50#ibcon#enter wrdev, iclass 6, count 0 2006.203.08:04:11.50#ibcon#first serial, iclass 6, count 0 2006.203.08:04:11.50#ibcon#enter sib2, iclass 6, count 0 2006.203.08:04:11.50#ibcon#flushed, iclass 6, count 0 2006.203.08:04:11.50#ibcon#about to write, iclass 6, count 0 2006.203.08:04:11.50#ibcon#wrote, iclass 6, count 0 2006.203.08:04:11.50#ibcon#about to read 3, iclass 6, count 0 2006.203.08:04:11.52#ibcon#read 3, iclass 6, count 0 2006.203.08:04:11.52#ibcon#about to read 4, iclass 6, count 0 2006.203.08:04:11.52#ibcon#read 4, iclass 6, count 0 2006.203.08:04:11.52#ibcon#about to read 5, iclass 6, count 0 2006.203.08:04:11.52#ibcon#read 5, iclass 6, count 0 2006.203.08:04:11.52#ibcon#about to read 6, iclass 6, count 0 2006.203.08:04:11.52#ibcon#read 6, iclass 6, count 0 2006.203.08:04:11.52#ibcon#end of sib2, iclass 6, count 0 2006.203.08:04:11.52#ibcon#*mode == 0, iclass 6, count 0 2006.203.08:04:11.52#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.203.08:04:11.52#ibcon#[26=FRQ=08,852.99\r\n] 2006.203.08:04:11.52#ibcon#*before write, iclass 6, count 0 2006.203.08:04:11.52#ibcon#enter sib2, iclass 6, count 0 2006.203.08:04:11.52#ibcon#flushed, iclass 6, count 0 2006.203.08:04:11.52#ibcon#about to write, iclass 6, count 0 2006.203.08:04:11.52#ibcon#wrote, iclass 6, count 0 2006.203.08:04:11.52#ibcon#about to read 3, iclass 6, count 0 2006.203.08:04:11.56#ibcon#read 3, iclass 6, count 0 2006.203.08:04:11.56#ibcon#about to read 4, iclass 6, count 0 2006.203.08:04:11.56#ibcon#read 4, iclass 6, count 0 2006.203.08:04:11.56#ibcon#about to read 5, iclass 6, count 0 2006.203.08:04:11.56#ibcon#read 5, iclass 6, count 0 2006.203.08:04:11.56#ibcon#about to read 6, iclass 6, count 0 2006.203.08:04:11.56#ibcon#read 6, iclass 6, count 0 2006.203.08:04:11.56#ibcon#end of sib2, iclass 6, count 0 2006.203.08:04:11.56#ibcon#*after write, iclass 6, count 0 2006.203.08:04:11.56#ibcon#*before return 0, iclass 6, count 0 2006.203.08:04:11.56#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.203.08:04:11.56#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.203.08:04:11.56#ibcon#about to clear, iclass 6 cls_cnt 0 2006.203.08:04:11.56#ibcon#cleared, iclass 6 cls_cnt 0 2006.203.08:04:11.56$vc4f8/va=8,6 2006.203.08:04:11.56#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.203.08:04:11.56#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.203.08:04:11.56#ibcon#ireg 11 cls_cnt 2 2006.203.08:04:11.56#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.203.08:04:11.62#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.203.08:04:11.62#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.203.08:04:11.62#ibcon#enter wrdev, iclass 10, count 2 2006.203.08:04:11.62#ibcon#first serial, iclass 10, count 2 2006.203.08:04:11.62#ibcon#enter sib2, iclass 10, count 2 2006.203.08:04:11.62#ibcon#flushed, iclass 10, count 2 2006.203.08:04:11.62#ibcon#about to write, iclass 10, count 2 2006.203.08:04:11.62#ibcon#wrote, iclass 10, count 2 2006.203.08:04:11.62#ibcon#about to read 3, iclass 10, count 2 2006.203.08:04:11.64#ibcon#read 3, iclass 10, count 2 2006.203.08:04:11.64#ibcon#about to read 4, iclass 10, count 2 2006.203.08:04:11.64#ibcon#read 4, iclass 10, count 2 2006.203.08:04:11.64#ibcon#about to read 5, iclass 10, count 2 2006.203.08:04:11.64#ibcon#read 5, iclass 10, count 2 2006.203.08:04:11.64#ibcon#about to read 6, iclass 10, count 2 2006.203.08:04:11.64#ibcon#read 6, iclass 10, count 2 2006.203.08:04:11.64#ibcon#end of sib2, iclass 10, count 2 2006.203.08:04:11.64#ibcon#*mode == 0, iclass 10, count 2 2006.203.08:04:11.64#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.203.08:04:11.64#ibcon#[25=AT08-06\r\n] 2006.203.08:04:11.64#ibcon#*before write, iclass 10, count 2 2006.203.08:04:11.64#ibcon#enter sib2, iclass 10, count 2 2006.203.08:04:11.64#ibcon#flushed, iclass 10, count 2 2006.203.08:04:11.64#ibcon#about to write, iclass 10, count 2 2006.203.08:04:11.64#ibcon#wrote, iclass 10, count 2 2006.203.08:04:11.64#ibcon#about to read 3, iclass 10, count 2 2006.203.08:04:11.67#ibcon#read 3, iclass 10, count 2 2006.203.08:04:11.67#ibcon#about to read 4, iclass 10, count 2 2006.203.08:04:11.67#ibcon#read 4, iclass 10, count 2 2006.203.08:04:11.67#ibcon#about to read 5, iclass 10, count 2 2006.203.08:04:11.67#ibcon#read 5, iclass 10, count 2 2006.203.08:04:11.67#ibcon#about to read 6, iclass 10, count 2 2006.203.08:04:11.67#ibcon#read 6, iclass 10, count 2 2006.203.08:04:11.67#ibcon#end of sib2, iclass 10, count 2 2006.203.08:04:11.67#ibcon#*after write, iclass 10, count 2 2006.203.08:04:11.67#ibcon#*before return 0, iclass 10, count 2 2006.203.08:04:11.67#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.203.08:04:11.67#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.203.08:04:11.67#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.203.08:04:11.67#ibcon#ireg 7 cls_cnt 0 2006.203.08:04:11.67#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.203.08:04:11.79#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.203.08:04:11.79#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.203.08:04:11.79#ibcon#enter wrdev, iclass 10, count 0 2006.203.08:04:11.79#ibcon#first serial, iclass 10, count 0 2006.203.08:04:11.79#ibcon#enter sib2, iclass 10, count 0 2006.203.08:04:11.79#ibcon#flushed, iclass 10, count 0 2006.203.08:04:11.79#ibcon#about to write, iclass 10, count 0 2006.203.08:04:11.79#ibcon#wrote, iclass 10, count 0 2006.203.08:04:11.79#ibcon#about to read 3, iclass 10, count 0 2006.203.08:04:11.81#ibcon#read 3, iclass 10, count 0 2006.203.08:04:11.81#ibcon#about to read 4, iclass 10, count 0 2006.203.08:04:11.81#ibcon#read 4, iclass 10, count 0 2006.203.08:04:11.81#ibcon#about to read 5, iclass 10, count 0 2006.203.08:04:11.81#ibcon#read 5, iclass 10, count 0 2006.203.08:04:11.81#ibcon#about to read 6, iclass 10, count 0 2006.203.08:04:11.81#ibcon#read 6, iclass 10, count 0 2006.203.08:04:11.81#ibcon#end of sib2, iclass 10, count 0 2006.203.08:04:11.81#ibcon#*mode == 0, iclass 10, count 0 2006.203.08:04:11.81#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.203.08:04:11.81#ibcon#[25=USB\r\n] 2006.203.08:04:11.81#ibcon#*before write, iclass 10, count 0 2006.203.08:04:11.81#ibcon#enter sib2, iclass 10, count 0 2006.203.08:04:11.81#ibcon#flushed, iclass 10, count 0 2006.203.08:04:11.81#ibcon#about to write, iclass 10, count 0 2006.203.08:04:11.81#ibcon#wrote, iclass 10, count 0 2006.203.08:04:11.81#ibcon#about to read 3, iclass 10, count 0 2006.203.08:04:11.84#ibcon#read 3, iclass 10, count 0 2006.203.08:04:11.84#ibcon#about to read 4, iclass 10, count 0 2006.203.08:04:11.84#ibcon#read 4, iclass 10, count 0 2006.203.08:04:11.84#ibcon#about to read 5, iclass 10, count 0 2006.203.08:04:11.84#ibcon#read 5, iclass 10, count 0 2006.203.08:04:11.84#ibcon#about to read 6, iclass 10, count 0 2006.203.08:04:11.84#ibcon#read 6, iclass 10, count 0 2006.203.08:04:11.84#ibcon#end of sib2, iclass 10, count 0 2006.203.08:04:11.84#ibcon#*after write, iclass 10, count 0 2006.203.08:04:11.84#ibcon#*before return 0, iclass 10, count 0 2006.203.08:04:11.84#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.203.08:04:11.84#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.203.08:04:11.84#ibcon#about to clear, iclass 10 cls_cnt 0 2006.203.08:04:11.84#ibcon#cleared, iclass 10 cls_cnt 0 2006.203.08:04:11.84$vc4f8/vblo=1,632.99 2006.203.08:04:11.84#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.203.08:04:11.84#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.203.08:04:11.84#ibcon#ireg 17 cls_cnt 0 2006.203.08:04:11.84#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.203.08:04:11.84#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.203.08:04:11.84#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.203.08:04:11.84#ibcon#enter wrdev, iclass 12, count 0 2006.203.08:04:11.84#ibcon#first serial, iclass 12, count 0 2006.203.08:04:11.84#ibcon#enter sib2, iclass 12, count 0 2006.203.08:04:11.84#ibcon#flushed, iclass 12, count 0 2006.203.08:04:11.84#ibcon#about to write, iclass 12, count 0 2006.203.08:04:11.84#ibcon#wrote, iclass 12, count 0 2006.203.08:04:11.84#ibcon#about to read 3, iclass 12, count 0 2006.203.08:04:11.86#ibcon#read 3, iclass 12, count 0 2006.203.08:04:11.86#ibcon#about to read 4, iclass 12, count 0 2006.203.08:04:11.86#ibcon#read 4, iclass 12, count 0 2006.203.08:04:11.86#ibcon#about to read 5, iclass 12, count 0 2006.203.08:04:11.86#ibcon#read 5, iclass 12, count 0 2006.203.08:04:11.86#ibcon#about to read 6, iclass 12, count 0 2006.203.08:04:11.86#ibcon#read 6, iclass 12, count 0 2006.203.08:04:11.86#ibcon#end of sib2, iclass 12, count 0 2006.203.08:04:11.86#ibcon#*mode == 0, iclass 12, count 0 2006.203.08:04:11.86#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.203.08:04:11.86#ibcon#[28=FRQ=01,632.99\r\n] 2006.203.08:04:11.86#ibcon#*before write, iclass 12, count 0 2006.203.08:04:11.86#ibcon#enter sib2, iclass 12, count 0 2006.203.08:04:11.86#ibcon#flushed, iclass 12, count 0 2006.203.08:04:11.86#ibcon#about to write, iclass 12, count 0 2006.203.08:04:11.86#ibcon#wrote, iclass 12, count 0 2006.203.08:04:11.86#ibcon#about to read 3, iclass 12, count 0 2006.203.08:04:11.90#ibcon#read 3, iclass 12, count 0 2006.203.08:04:11.90#ibcon#about to read 4, iclass 12, count 0 2006.203.08:04:11.90#ibcon#read 4, iclass 12, count 0 2006.203.08:04:11.90#ibcon#about to read 5, iclass 12, count 0 2006.203.08:04:11.90#ibcon#read 5, iclass 12, count 0 2006.203.08:04:11.90#ibcon#about to read 6, iclass 12, count 0 2006.203.08:04:11.90#ibcon#read 6, iclass 12, count 0 2006.203.08:04:11.90#ibcon#end of sib2, iclass 12, count 0 2006.203.08:04:11.90#ibcon#*after write, iclass 12, count 0 2006.203.08:04:11.90#ibcon#*before return 0, iclass 12, count 0 2006.203.08:04:11.90#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.203.08:04:11.90#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.203.08:04:11.90#ibcon#about to clear, iclass 12 cls_cnt 0 2006.203.08:04:11.90#ibcon#cleared, iclass 12 cls_cnt 0 2006.203.08:04:11.90$vc4f8/vb=1,4 2006.203.08:04:11.90#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.203.08:04:11.90#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.203.08:04:11.90#ibcon#ireg 11 cls_cnt 2 2006.203.08:04:11.90#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.203.08:04:11.90#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.203.08:04:11.90#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.203.08:04:11.90#ibcon#enter wrdev, iclass 14, count 2 2006.203.08:04:11.90#ibcon#first serial, iclass 14, count 2 2006.203.08:04:11.90#ibcon#enter sib2, iclass 14, count 2 2006.203.08:04:11.90#ibcon#flushed, iclass 14, count 2 2006.203.08:04:11.90#ibcon#about to write, iclass 14, count 2 2006.203.08:04:11.90#ibcon#wrote, iclass 14, count 2 2006.203.08:04:11.90#ibcon#about to read 3, iclass 14, count 2 2006.203.08:04:11.92#ibcon#read 3, iclass 14, count 2 2006.203.08:04:11.92#ibcon#about to read 4, iclass 14, count 2 2006.203.08:04:11.92#ibcon#read 4, iclass 14, count 2 2006.203.08:04:11.92#ibcon#about to read 5, iclass 14, count 2 2006.203.08:04:11.92#ibcon#read 5, iclass 14, count 2 2006.203.08:04:11.92#ibcon#about to read 6, iclass 14, count 2 2006.203.08:04:11.92#ibcon#read 6, iclass 14, count 2 2006.203.08:04:11.92#ibcon#end of sib2, iclass 14, count 2 2006.203.08:04:11.92#ibcon#*mode == 0, iclass 14, count 2 2006.203.08:04:11.92#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.203.08:04:11.92#ibcon#[27=AT01-04\r\n] 2006.203.08:04:11.92#ibcon#*before write, iclass 14, count 2 2006.203.08:04:11.92#ibcon#enter sib2, iclass 14, count 2 2006.203.08:04:11.92#ibcon#flushed, iclass 14, count 2 2006.203.08:04:11.92#ibcon#about to write, iclass 14, count 2 2006.203.08:04:11.92#ibcon#wrote, iclass 14, count 2 2006.203.08:04:11.92#ibcon#about to read 3, iclass 14, count 2 2006.203.08:04:11.95#ibcon#read 3, iclass 14, count 2 2006.203.08:04:11.95#ibcon#about to read 4, iclass 14, count 2 2006.203.08:04:11.95#ibcon#read 4, iclass 14, count 2 2006.203.08:04:11.95#ibcon#about to read 5, iclass 14, count 2 2006.203.08:04:11.95#ibcon#read 5, iclass 14, count 2 2006.203.08:04:11.95#ibcon#about to read 6, iclass 14, count 2 2006.203.08:04:11.95#ibcon#read 6, iclass 14, count 2 2006.203.08:04:11.95#ibcon#end of sib2, iclass 14, count 2 2006.203.08:04:11.95#ibcon#*after write, iclass 14, count 2 2006.203.08:04:11.95#ibcon#*before return 0, iclass 14, count 2 2006.203.08:04:11.95#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.203.08:04:11.95#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.203.08:04:11.95#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.203.08:04:11.95#ibcon#ireg 7 cls_cnt 0 2006.203.08:04:11.95#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.203.08:04:12.07#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.203.08:04:12.07#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.203.08:04:12.07#ibcon#enter wrdev, iclass 14, count 0 2006.203.08:04:12.07#ibcon#first serial, iclass 14, count 0 2006.203.08:04:12.07#ibcon#enter sib2, iclass 14, count 0 2006.203.08:04:12.07#ibcon#flushed, iclass 14, count 0 2006.203.08:04:12.07#ibcon#about to write, iclass 14, count 0 2006.203.08:04:12.07#ibcon#wrote, iclass 14, count 0 2006.203.08:04:12.07#ibcon#about to read 3, iclass 14, count 0 2006.203.08:04:12.09#ibcon#read 3, iclass 14, count 0 2006.203.08:04:12.09#ibcon#about to read 4, iclass 14, count 0 2006.203.08:04:12.09#ibcon#read 4, iclass 14, count 0 2006.203.08:04:12.09#ibcon#about to read 5, iclass 14, count 0 2006.203.08:04:12.09#ibcon#read 5, iclass 14, count 0 2006.203.08:04:12.09#ibcon#about to read 6, iclass 14, count 0 2006.203.08:04:12.09#ibcon#read 6, iclass 14, count 0 2006.203.08:04:12.09#ibcon#end of sib2, iclass 14, count 0 2006.203.08:04:12.09#ibcon#*mode == 0, iclass 14, count 0 2006.203.08:04:12.09#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.203.08:04:12.09#ibcon#[27=USB\r\n] 2006.203.08:04:12.09#ibcon#*before write, iclass 14, count 0 2006.203.08:04:12.09#ibcon#enter sib2, iclass 14, count 0 2006.203.08:04:12.09#ibcon#flushed, iclass 14, count 0 2006.203.08:04:12.09#ibcon#about to write, iclass 14, count 0 2006.203.08:04:12.09#ibcon#wrote, iclass 14, count 0 2006.203.08:04:12.09#ibcon#about to read 3, iclass 14, count 0 2006.203.08:04:12.12#ibcon#read 3, iclass 14, count 0 2006.203.08:04:12.12#ibcon#about to read 4, iclass 14, count 0 2006.203.08:04:12.12#ibcon#read 4, iclass 14, count 0 2006.203.08:04:12.12#ibcon#about to read 5, iclass 14, count 0 2006.203.08:04:12.12#ibcon#read 5, iclass 14, count 0 2006.203.08:04:12.12#ibcon#about to read 6, iclass 14, count 0 2006.203.08:04:12.12#ibcon#read 6, iclass 14, count 0 2006.203.08:04:12.12#ibcon#end of sib2, iclass 14, count 0 2006.203.08:04:12.12#ibcon#*after write, iclass 14, count 0 2006.203.08:04:12.12#ibcon#*before return 0, iclass 14, count 0 2006.203.08:04:12.12#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.203.08:04:12.12#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.203.08:04:12.12#ibcon#about to clear, iclass 14 cls_cnt 0 2006.203.08:04:12.12#ibcon#cleared, iclass 14 cls_cnt 0 2006.203.08:04:12.12$vc4f8/vblo=2,640.99 2006.203.08:04:12.12#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.203.08:04:12.12#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.203.08:04:12.12#ibcon#ireg 17 cls_cnt 0 2006.203.08:04:12.12#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.203.08:04:12.12#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.203.08:04:12.12#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.203.08:04:12.12#ibcon#enter wrdev, iclass 16, count 0 2006.203.08:04:12.12#ibcon#first serial, iclass 16, count 0 2006.203.08:04:12.12#ibcon#enter sib2, iclass 16, count 0 2006.203.08:04:12.12#ibcon#flushed, iclass 16, count 0 2006.203.08:04:12.12#ibcon#about to write, iclass 16, count 0 2006.203.08:04:12.12#ibcon#wrote, iclass 16, count 0 2006.203.08:04:12.12#ibcon#about to read 3, iclass 16, count 0 2006.203.08:04:12.14#ibcon#read 3, iclass 16, count 0 2006.203.08:04:12.14#ibcon#about to read 4, iclass 16, count 0 2006.203.08:04:12.14#ibcon#read 4, iclass 16, count 0 2006.203.08:04:12.14#ibcon#about to read 5, iclass 16, count 0 2006.203.08:04:12.14#ibcon#read 5, iclass 16, count 0 2006.203.08:04:12.14#ibcon#about to read 6, iclass 16, count 0 2006.203.08:04:12.14#ibcon#read 6, iclass 16, count 0 2006.203.08:04:12.14#ibcon#end of sib2, iclass 16, count 0 2006.203.08:04:12.14#ibcon#*mode == 0, iclass 16, count 0 2006.203.08:04:12.14#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.203.08:04:12.14#ibcon#[28=FRQ=02,640.99\r\n] 2006.203.08:04:12.14#ibcon#*before write, iclass 16, count 0 2006.203.08:04:12.14#ibcon#enter sib2, iclass 16, count 0 2006.203.08:04:12.14#ibcon#flushed, iclass 16, count 0 2006.203.08:04:12.14#ibcon#about to write, iclass 16, count 0 2006.203.08:04:12.14#ibcon#wrote, iclass 16, count 0 2006.203.08:04:12.14#ibcon#about to read 3, iclass 16, count 0 2006.203.08:04:12.18#ibcon#read 3, iclass 16, count 0 2006.203.08:04:12.18#ibcon#about to read 4, iclass 16, count 0 2006.203.08:04:12.18#ibcon#read 4, iclass 16, count 0 2006.203.08:04:12.18#ibcon#about to read 5, iclass 16, count 0 2006.203.08:04:12.18#ibcon#read 5, iclass 16, count 0 2006.203.08:04:12.18#ibcon#about to read 6, iclass 16, count 0 2006.203.08:04:12.18#ibcon#read 6, iclass 16, count 0 2006.203.08:04:12.18#ibcon#end of sib2, iclass 16, count 0 2006.203.08:04:12.18#ibcon#*after write, iclass 16, count 0 2006.203.08:04:12.18#ibcon#*before return 0, iclass 16, count 0 2006.203.08:04:12.18#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.203.08:04:12.18#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.203.08:04:12.18#ibcon#about to clear, iclass 16 cls_cnt 0 2006.203.08:04:12.18#ibcon#cleared, iclass 16 cls_cnt 0 2006.203.08:04:12.18$vc4f8/vb=2,4 2006.203.08:04:12.18#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.203.08:04:12.18#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.203.08:04:12.18#ibcon#ireg 11 cls_cnt 2 2006.203.08:04:12.18#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.203.08:04:12.24#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.203.08:04:12.24#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.203.08:04:12.24#ibcon#enter wrdev, iclass 18, count 2 2006.203.08:04:12.24#ibcon#first serial, iclass 18, count 2 2006.203.08:04:12.24#ibcon#enter sib2, iclass 18, count 2 2006.203.08:04:12.24#ibcon#flushed, iclass 18, count 2 2006.203.08:04:12.24#ibcon#about to write, iclass 18, count 2 2006.203.08:04:12.24#ibcon#wrote, iclass 18, count 2 2006.203.08:04:12.24#ibcon#about to read 3, iclass 18, count 2 2006.203.08:04:12.26#ibcon#read 3, iclass 18, count 2 2006.203.08:04:12.26#ibcon#about to read 4, iclass 18, count 2 2006.203.08:04:12.26#ibcon#read 4, iclass 18, count 2 2006.203.08:04:12.26#ibcon#about to read 5, iclass 18, count 2 2006.203.08:04:12.26#ibcon#read 5, iclass 18, count 2 2006.203.08:04:12.26#ibcon#about to read 6, iclass 18, count 2 2006.203.08:04:12.26#ibcon#read 6, iclass 18, count 2 2006.203.08:04:12.26#ibcon#end of sib2, iclass 18, count 2 2006.203.08:04:12.26#ibcon#*mode == 0, iclass 18, count 2 2006.203.08:04:12.26#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.203.08:04:12.26#ibcon#[27=AT02-04\r\n] 2006.203.08:04:12.26#ibcon#*before write, iclass 18, count 2 2006.203.08:04:12.26#ibcon#enter sib2, iclass 18, count 2 2006.203.08:04:12.26#ibcon#flushed, iclass 18, count 2 2006.203.08:04:12.26#ibcon#about to write, iclass 18, count 2 2006.203.08:04:12.26#ibcon#wrote, iclass 18, count 2 2006.203.08:04:12.26#ibcon#about to read 3, iclass 18, count 2 2006.203.08:04:12.29#ibcon#read 3, iclass 18, count 2 2006.203.08:04:12.29#ibcon#about to read 4, iclass 18, count 2 2006.203.08:04:12.29#ibcon#read 4, iclass 18, count 2 2006.203.08:04:12.29#ibcon#about to read 5, iclass 18, count 2 2006.203.08:04:12.29#ibcon#read 5, iclass 18, count 2 2006.203.08:04:12.29#ibcon#about to read 6, iclass 18, count 2 2006.203.08:04:12.29#ibcon#read 6, iclass 18, count 2 2006.203.08:04:12.29#ibcon#end of sib2, iclass 18, count 2 2006.203.08:04:12.29#ibcon#*after write, iclass 18, count 2 2006.203.08:04:12.29#ibcon#*before return 0, iclass 18, count 2 2006.203.08:04:12.29#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.203.08:04:12.29#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.203.08:04:12.29#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.203.08:04:12.29#ibcon#ireg 7 cls_cnt 0 2006.203.08:04:12.29#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.203.08:04:12.41#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.203.08:04:12.41#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.203.08:04:12.41#ibcon#enter wrdev, iclass 18, count 0 2006.203.08:04:12.41#ibcon#first serial, iclass 18, count 0 2006.203.08:04:12.41#ibcon#enter sib2, iclass 18, count 0 2006.203.08:04:12.41#ibcon#flushed, iclass 18, count 0 2006.203.08:04:12.41#ibcon#about to write, iclass 18, count 0 2006.203.08:04:12.41#ibcon#wrote, iclass 18, count 0 2006.203.08:04:12.41#ibcon#about to read 3, iclass 18, count 0 2006.203.08:04:12.43#ibcon#read 3, iclass 18, count 0 2006.203.08:04:12.43#ibcon#about to read 4, iclass 18, count 0 2006.203.08:04:12.43#ibcon#read 4, iclass 18, count 0 2006.203.08:04:12.43#ibcon#about to read 5, iclass 18, count 0 2006.203.08:04:12.43#ibcon#read 5, iclass 18, count 0 2006.203.08:04:12.43#ibcon#about to read 6, iclass 18, count 0 2006.203.08:04:12.43#ibcon#read 6, iclass 18, count 0 2006.203.08:04:12.43#ibcon#end of sib2, iclass 18, count 0 2006.203.08:04:12.43#ibcon#*mode == 0, iclass 18, count 0 2006.203.08:04:12.43#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.203.08:04:12.43#ibcon#[27=USB\r\n] 2006.203.08:04:12.43#ibcon#*before write, iclass 18, count 0 2006.203.08:04:12.43#ibcon#enter sib2, iclass 18, count 0 2006.203.08:04:12.43#ibcon#flushed, iclass 18, count 0 2006.203.08:04:12.43#ibcon#about to write, iclass 18, count 0 2006.203.08:04:12.43#ibcon#wrote, iclass 18, count 0 2006.203.08:04:12.43#ibcon#about to read 3, iclass 18, count 0 2006.203.08:04:12.46#ibcon#read 3, iclass 18, count 0 2006.203.08:04:12.46#ibcon#about to read 4, iclass 18, count 0 2006.203.08:04:12.46#ibcon#read 4, iclass 18, count 0 2006.203.08:04:12.46#ibcon#about to read 5, iclass 18, count 0 2006.203.08:04:12.46#ibcon#read 5, iclass 18, count 0 2006.203.08:04:12.46#ibcon#about to read 6, iclass 18, count 0 2006.203.08:04:12.46#ibcon#read 6, iclass 18, count 0 2006.203.08:04:12.46#ibcon#end of sib2, iclass 18, count 0 2006.203.08:04:12.46#ibcon#*after write, iclass 18, count 0 2006.203.08:04:12.46#ibcon#*before return 0, iclass 18, count 0 2006.203.08:04:12.46#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.203.08:04:12.46#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.203.08:04:12.46#ibcon#about to clear, iclass 18 cls_cnt 0 2006.203.08:04:12.46#ibcon#cleared, iclass 18 cls_cnt 0 2006.203.08:04:12.46$vc4f8/vblo=3,656.99 2006.203.08:04:12.46#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.203.08:04:12.46#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.203.08:04:12.46#ibcon#ireg 17 cls_cnt 0 2006.203.08:04:12.46#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.203.08:04:12.46#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.203.08:04:12.46#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.203.08:04:12.46#ibcon#enter wrdev, iclass 20, count 0 2006.203.08:04:12.46#ibcon#first serial, iclass 20, count 0 2006.203.08:04:12.46#ibcon#enter sib2, iclass 20, count 0 2006.203.08:04:12.46#ibcon#flushed, iclass 20, count 0 2006.203.08:04:12.46#ibcon#about to write, iclass 20, count 0 2006.203.08:04:12.46#ibcon#wrote, iclass 20, count 0 2006.203.08:04:12.46#ibcon#about to read 3, iclass 20, count 0 2006.203.08:04:12.48#ibcon#read 3, iclass 20, count 0 2006.203.08:04:12.48#ibcon#about to read 4, iclass 20, count 0 2006.203.08:04:12.48#ibcon#read 4, iclass 20, count 0 2006.203.08:04:12.48#ibcon#about to read 5, iclass 20, count 0 2006.203.08:04:12.48#ibcon#read 5, iclass 20, count 0 2006.203.08:04:12.48#ibcon#about to read 6, iclass 20, count 0 2006.203.08:04:12.48#ibcon#read 6, iclass 20, count 0 2006.203.08:04:12.48#ibcon#end of sib2, iclass 20, count 0 2006.203.08:04:12.48#ibcon#*mode == 0, iclass 20, count 0 2006.203.08:04:12.48#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.203.08:04:12.48#ibcon#[28=FRQ=03,656.99\r\n] 2006.203.08:04:12.48#ibcon#*before write, iclass 20, count 0 2006.203.08:04:12.48#ibcon#enter sib2, iclass 20, count 0 2006.203.08:04:12.48#ibcon#flushed, iclass 20, count 0 2006.203.08:04:12.48#ibcon#about to write, iclass 20, count 0 2006.203.08:04:12.48#ibcon#wrote, iclass 20, count 0 2006.203.08:04:12.48#ibcon#about to read 3, iclass 20, count 0 2006.203.08:04:12.52#ibcon#read 3, iclass 20, count 0 2006.203.08:04:12.52#ibcon#about to read 4, iclass 20, count 0 2006.203.08:04:12.52#ibcon#read 4, iclass 20, count 0 2006.203.08:04:12.52#ibcon#about to read 5, iclass 20, count 0 2006.203.08:04:12.52#ibcon#read 5, iclass 20, count 0 2006.203.08:04:12.52#ibcon#about to read 6, iclass 20, count 0 2006.203.08:04:12.52#ibcon#read 6, iclass 20, count 0 2006.203.08:04:12.52#ibcon#end of sib2, iclass 20, count 0 2006.203.08:04:12.52#ibcon#*after write, iclass 20, count 0 2006.203.08:04:12.52#ibcon#*before return 0, iclass 20, count 0 2006.203.08:04:12.52#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.203.08:04:12.52#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.203.08:04:12.52#ibcon#about to clear, iclass 20 cls_cnt 0 2006.203.08:04:12.52#ibcon#cleared, iclass 20 cls_cnt 0 2006.203.08:04:12.52$vc4f8/vb=3,4 2006.203.08:04:12.52#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.203.08:04:12.52#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.203.08:04:12.52#ibcon#ireg 11 cls_cnt 2 2006.203.08:04:12.52#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.203.08:04:12.58#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.203.08:04:12.58#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.203.08:04:12.58#ibcon#enter wrdev, iclass 22, count 2 2006.203.08:04:12.58#ibcon#first serial, iclass 22, count 2 2006.203.08:04:12.58#ibcon#enter sib2, iclass 22, count 2 2006.203.08:04:12.58#ibcon#flushed, iclass 22, count 2 2006.203.08:04:12.58#ibcon#about to write, iclass 22, count 2 2006.203.08:04:12.58#ibcon#wrote, iclass 22, count 2 2006.203.08:04:12.58#ibcon#about to read 3, iclass 22, count 2 2006.203.08:04:12.60#ibcon#read 3, iclass 22, count 2 2006.203.08:04:12.60#ibcon#about to read 4, iclass 22, count 2 2006.203.08:04:12.60#ibcon#read 4, iclass 22, count 2 2006.203.08:04:12.60#ibcon#about to read 5, iclass 22, count 2 2006.203.08:04:12.60#ibcon#read 5, iclass 22, count 2 2006.203.08:04:12.60#ibcon#about to read 6, iclass 22, count 2 2006.203.08:04:12.60#ibcon#read 6, iclass 22, count 2 2006.203.08:04:12.60#ibcon#end of sib2, iclass 22, count 2 2006.203.08:04:12.60#ibcon#*mode == 0, iclass 22, count 2 2006.203.08:04:12.60#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.203.08:04:12.60#ibcon#[27=AT03-04\r\n] 2006.203.08:04:12.60#ibcon#*before write, iclass 22, count 2 2006.203.08:04:12.60#ibcon#enter sib2, iclass 22, count 2 2006.203.08:04:12.60#ibcon#flushed, iclass 22, count 2 2006.203.08:04:12.60#ibcon#about to write, iclass 22, count 2 2006.203.08:04:12.60#ibcon#wrote, iclass 22, count 2 2006.203.08:04:12.60#ibcon#about to read 3, iclass 22, count 2 2006.203.08:04:12.63#ibcon#read 3, iclass 22, count 2 2006.203.08:04:12.63#ibcon#about to read 4, iclass 22, count 2 2006.203.08:04:12.63#ibcon#read 4, iclass 22, count 2 2006.203.08:04:12.63#ibcon#about to read 5, iclass 22, count 2 2006.203.08:04:12.63#ibcon#read 5, iclass 22, count 2 2006.203.08:04:12.63#ibcon#about to read 6, iclass 22, count 2 2006.203.08:04:12.63#ibcon#read 6, iclass 22, count 2 2006.203.08:04:12.63#ibcon#end of sib2, iclass 22, count 2 2006.203.08:04:12.63#ibcon#*after write, iclass 22, count 2 2006.203.08:04:12.63#ibcon#*before return 0, iclass 22, count 2 2006.203.08:04:12.63#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.203.08:04:12.63#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.203.08:04:12.63#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.203.08:04:12.63#ibcon#ireg 7 cls_cnt 0 2006.203.08:04:12.63#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.203.08:04:12.75#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.203.08:04:12.75#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.203.08:04:12.75#ibcon#enter wrdev, iclass 22, count 0 2006.203.08:04:12.75#ibcon#first serial, iclass 22, count 0 2006.203.08:04:12.75#ibcon#enter sib2, iclass 22, count 0 2006.203.08:04:12.75#ibcon#flushed, iclass 22, count 0 2006.203.08:04:12.75#ibcon#about to write, iclass 22, count 0 2006.203.08:04:12.75#ibcon#wrote, iclass 22, count 0 2006.203.08:04:12.75#ibcon#about to read 3, iclass 22, count 0 2006.203.08:04:12.77#ibcon#read 3, iclass 22, count 0 2006.203.08:04:12.77#ibcon#about to read 4, iclass 22, count 0 2006.203.08:04:12.77#ibcon#read 4, iclass 22, count 0 2006.203.08:04:12.77#ibcon#about to read 5, iclass 22, count 0 2006.203.08:04:12.77#ibcon#read 5, iclass 22, count 0 2006.203.08:04:12.77#ibcon#about to read 6, iclass 22, count 0 2006.203.08:04:12.77#ibcon#read 6, iclass 22, count 0 2006.203.08:04:12.77#ibcon#end of sib2, iclass 22, count 0 2006.203.08:04:12.77#ibcon#*mode == 0, iclass 22, count 0 2006.203.08:04:12.77#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.203.08:04:12.77#ibcon#[27=USB\r\n] 2006.203.08:04:12.77#ibcon#*before write, iclass 22, count 0 2006.203.08:04:12.77#ibcon#enter sib2, iclass 22, count 0 2006.203.08:04:12.77#ibcon#flushed, iclass 22, count 0 2006.203.08:04:12.77#ibcon#about to write, iclass 22, count 0 2006.203.08:04:12.77#ibcon#wrote, iclass 22, count 0 2006.203.08:04:12.77#ibcon#about to read 3, iclass 22, count 0 2006.203.08:04:12.80#ibcon#read 3, iclass 22, count 0 2006.203.08:04:12.80#ibcon#about to read 4, iclass 22, count 0 2006.203.08:04:12.80#ibcon#read 4, iclass 22, count 0 2006.203.08:04:12.80#ibcon#about to read 5, iclass 22, count 0 2006.203.08:04:12.80#ibcon#read 5, iclass 22, count 0 2006.203.08:04:12.80#ibcon#about to read 6, iclass 22, count 0 2006.203.08:04:12.80#ibcon#read 6, iclass 22, count 0 2006.203.08:04:12.80#ibcon#end of sib2, iclass 22, count 0 2006.203.08:04:12.80#ibcon#*after write, iclass 22, count 0 2006.203.08:04:12.80#ibcon#*before return 0, iclass 22, count 0 2006.203.08:04:12.80#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.203.08:04:12.80#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.203.08:04:12.80#ibcon#about to clear, iclass 22 cls_cnt 0 2006.203.08:04:12.80#ibcon#cleared, iclass 22 cls_cnt 0 2006.203.08:04:12.80$vc4f8/vblo=4,712.99 2006.203.08:04:12.80#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.203.08:04:12.80#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.203.08:04:12.80#ibcon#ireg 17 cls_cnt 0 2006.203.08:04:12.80#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.203.08:04:12.80#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.203.08:04:12.80#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.203.08:04:12.80#ibcon#enter wrdev, iclass 24, count 0 2006.203.08:04:12.80#ibcon#first serial, iclass 24, count 0 2006.203.08:04:12.80#ibcon#enter sib2, iclass 24, count 0 2006.203.08:04:12.80#ibcon#flushed, iclass 24, count 0 2006.203.08:04:12.80#ibcon#about to write, iclass 24, count 0 2006.203.08:04:12.80#ibcon#wrote, iclass 24, count 0 2006.203.08:04:12.80#ibcon#about to read 3, iclass 24, count 0 2006.203.08:04:12.82#ibcon#read 3, iclass 24, count 0 2006.203.08:04:12.82#ibcon#about to read 4, iclass 24, count 0 2006.203.08:04:12.82#ibcon#read 4, iclass 24, count 0 2006.203.08:04:12.82#ibcon#about to read 5, iclass 24, count 0 2006.203.08:04:12.82#ibcon#read 5, iclass 24, count 0 2006.203.08:04:12.82#ibcon#about to read 6, iclass 24, count 0 2006.203.08:04:12.82#ibcon#read 6, iclass 24, count 0 2006.203.08:04:12.82#ibcon#end of sib2, iclass 24, count 0 2006.203.08:04:12.82#ibcon#*mode == 0, iclass 24, count 0 2006.203.08:04:12.82#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.203.08:04:12.82#ibcon#[28=FRQ=04,712.99\r\n] 2006.203.08:04:12.82#ibcon#*before write, iclass 24, count 0 2006.203.08:04:12.82#ibcon#enter sib2, iclass 24, count 0 2006.203.08:04:12.82#ibcon#flushed, iclass 24, count 0 2006.203.08:04:12.82#ibcon#about to write, iclass 24, count 0 2006.203.08:04:12.82#ibcon#wrote, iclass 24, count 0 2006.203.08:04:12.82#ibcon#about to read 3, iclass 24, count 0 2006.203.08:04:12.87#ibcon#read 3, iclass 24, count 0 2006.203.08:04:12.87#ibcon#about to read 4, iclass 24, count 0 2006.203.08:04:12.87#ibcon#read 4, iclass 24, count 0 2006.203.08:04:12.87#ibcon#about to read 5, iclass 24, count 0 2006.203.08:04:12.87#ibcon#read 5, iclass 24, count 0 2006.203.08:04:12.87#ibcon#about to read 6, iclass 24, count 0 2006.203.08:04:12.87#ibcon#read 6, iclass 24, count 0 2006.203.08:04:12.87#ibcon#end of sib2, iclass 24, count 0 2006.203.08:04:12.87#ibcon#*after write, iclass 24, count 0 2006.203.08:04:12.87#ibcon#*before return 0, iclass 24, count 0 2006.203.08:04:12.87#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.203.08:04:12.87#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.203.08:04:12.87#ibcon#about to clear, iclass 24 cls_cnt 0 2006.203.08:04:12.87#ibcon#cleared, iclass 24 cls_cnt 0 2006.203.08:04:12.87$vc4f8/vb=4,4 2006.203.08:04:12.87#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.203.08:04:12.87#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.203.08:04:12.87#ibcon#ireg 11 cls_cnt 2 2006.203.08:04:12.87#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.203.08:04:12.92#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.203.08:04:12.92#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.203.08:04:12.92#ibcon#enter wrdev, iclass 26, count 2 2006.203.08:04:12.92#ibcon#first serial, iclass 26, count 2 2006.203.08:04:12.92#ibcon#enter sib2, iclass 26, count 2 2006.203.08:04:12.92#ibcon#flushed, iclass 26, count 2 2006.203.08:04:12.92#ibcon#about to write, iclass 26, count 2 2006.203.08:04:12.92#ibcon#wrote, iclass 26, count 2 2006.203.08:04:12.92#ibcon#about to read 3, iclass 26, count 2 2006.203.08:04:12.94#ibcon#read 3, iclass 26, count 2 2006.203.08:04:12.94#ibcon#about to read 4, iclass 26, count 2 2006.203.08:04:12.94#ibcon#read 4, iclass 26, count 2 2006.203.08:04:12.94#ibcon#about to read 5, iclass 26, count 2 2006.203.08:04:12.94#ibcon#read 5, iclass 26, count 2 2006.203.08:04:12.94#ibcon#about to read 6, iclass 26, count 2 2006.203.08:04:12.94#ibcon#read 6, iclass 26, count 2 2006.203.08:04:12.94#ibcon#end of sib2, iclass 26, count 2 2006.203.08:04:12.94#ibcon#*mode == 0, iclass 26, count 2 2006.203.08:04:12.94#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.203.08:04:12.94#ibcon#[27=AT04-04\r\n] 2006.203.08:04:12.94#ibcon#*before write, iclass 26, count 2 2006.203.08:04:12.94#ibcon#enter sib2, iclass 26, count 2 2006.203.08:04:12.94#ibcon#flushed, iclass 26, count 2 2006.203.08:04:12.94#ibcon#about to write, iclass 26, count 2 2006.203.08:04:12.94#ibcon#wrote, iclass 26, count 2 2006.203.08:04:12.94#ibcon#about to read 3, iclass 26, count 2 2006.203.08:04:12.97#ibcon#read 3, iclass 26, count 2 2006.203.08:04:12.97#ibcon#about to read 4, iclass 26, count 2 2006.203.08:04:12.97#ibcon#read 4, iclass 26, count 2 2006.203.08:04:12.97#ibcon#about to read 5, iclass 26, count 2 2006.203.08:04:12.97#ibcon#read 5, iclass 26, count 2 2006.203.08:04:12.97#ibcon#about to read 6, iclass 26, count 2 2006.203.08:04:12.97#ibcon#read 6, iclass 26, count 2 2006.203.08:04:12.97#ibcon#end of sib2, iclass 26, count 2 2006.203.08:04:12.97#ibcon#*after write, iclass 26, count 2 2006.203.08:04:12.97#ibcon#*before return 0, iclass 26, count 2 2006.203.08:04:12.97#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.203.08:04:12.97#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.203.08:04:12.97#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.203.08:04:12.97#ibcon#ireg 7 cls_cnt 0 2006.203.08:04:12.97#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.203.08:04:13.09#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.203.08:04:13.09#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.203.08:04:13.09#ibcon#enter wrdev, iclass 26, count 0 2006.203.08:04:13.09#ibcon#first serial, iclass 26, count 0 2006.203.08:04:13.09#ibcon#enter sib2, iclass 26, count 0 2006.203.08:04:13.09#ibcon#flushed, iclass 26, count 0 2006.203.08:04:13.09#ibcon#about to write, iclass 26, count 0 2006.203.08:04:13.09#ibcon#wrote, iclass 26, count 0 2006.203.08:04:13.09#ibcon#about to read 3, iclass 26, count 0 2006.203.08:04:13.11#ibcon#read 3, iclass 26, count 0 2006.203.08:04:13.11#ibcon#about to read 4, iclass 26, count 0 2006.203.08:04:13.11#ibcon#read 4, iclass 26, count 0 2006.203.08:04:13.11#ibcon#about to read 5, iclass 26, count 0 2006.203.08:04:13.11#ibcon#read 5, iclass 26, count 0 2006.203.08:04:13.11#ibcon#about to read 6, iclass 26, count 0 2006.203.08:04:13.11#ibcon#read 6, iclass 26, count 0 2006.203.08:04:13.11#ibcon#end of sib2, iclass 26, count 0 2006.203.08:04:13.11#ibcon#*mode == 0, iclass 26, count 0 2006.203.08:04:13.11#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.203.08:04:13.11#ibcon#[27=USB\r\n] 2006.203.08:04:13.11#ibcon#*before write, iclass 26, count 0 2006.203.08:04:13.11#ibcon#enter sib2, iclass 26, count 0 2006.203.08:04:13.11#ibcon#flushed, iclass 26, count 0 2006.203.08:04:13.11#ibcon#about to write, iclass 26, count 0 2006.203.08:04:13.11#ibcon#wrote, iclass 26, count 0 2006.203.08:04:13.11#ibcon#about to read 3, iclass 26, count 0 2006.203.08:04:13.14#ibcon#read 3, iclass 26, count 0 2006.203.08:04:13.14#ibcon#about to read 4, iclass 26, count 0 2006.203.08:04:13.14#ibcon#read 4, iclass 26, count 0 2006.203.08:04:13.14#ibcon#about to read 5, iclass 26, count 0 2006.203.08:04:13.14#ibcon#read 5, iclass 26, count 0 2006.203.08:04:13.14#ibcon#about to read 6, iclass 26, count 0 2006.203.08:04:13.14#ibcon#read 6, iclass 26, count 0 2006.203.08:04:13.14#ibcon#end of sib2, iclass 26, count 0 2006.203.08:04:13.14#ibcon#*after write, iclass 26, count 0 2006.203.08:04:13.14#ibcon#*before return 0, iclass 26, count 0 2006.203.08:04:13.14#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.203.08:04:13.14#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.203.08:04:13.14#ibcon#about to clear, iclass 26 cls_cnt 0 2006.203.08:04:13.14#ibcon#cleared, iclass 26 cls_cnt 0 2006.203.08:04:13.14$vc4f8/vblo=5,744.99 2006.203.08:04:13.14#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.203.08:04:13.14#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.203.08:04:13.14#ibcon#ireg 17 cls_cnt 0 2006.203.08:04:13.14#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.203.08:04:13.14#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.203.08:04:13.14#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.203.08:04:13.14#ibcon#enter wrdev, iclass 28, count 0 2006.203.08:04:13.14#ibcon#first serial, iclass 28, count 0 2006.203.08:04:13.14#ibcon#enter sib2, iclass 28, count 0 2006.203.08:04:13.14#ibcon#flushed, iclass 28, count 0 2006.203.08:04:13.14#ibcon#about to write, iclass 28, count 0 2006.203.08:04:13.14#ibcon#wrote, iclass 28, count 0 2006.203.08:04:13.14#ibcon#about to read 3, iclass 28, count 0 2006.203.08:04:13.16#ibcon#read 3, iclass 28, count 0 2006.203.08:04:13.16#ibcon#about to read 4, iclass 28, count 0 2006.203.08:04:13.16#ibcon#read 4, iclass 28, count 0 2006.203.08:04:13.16#ibcon#about to read 5, iclass 28, count 0 2006.203.08:04:13.16#ibcon#read 5, iclass 28, count 0 2006.203.08:04:13.16#ibcon#about to read 6, iclass 28, count 0 2006.203.08:04:13.16#ibcon#read 6, iclass 28, count 0 2006.203.08:04:13.16#ibcon#end of sib2, iclass 28, count 0 2006.203.08:04:13.16#ibcon#*mode == 0, iclass 28, count 0 2006.203.08:04:13.16#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.203.08:04:13.16#ibcon#[28=FRQ=05,744.99\r\n] 2006.203.08:04:13.16#ibcon#*before write, iclass 28, count 0 2006.203.08:04:13.16#ibcon#enter sib2, iclass 28, count 0 2006.203.08:04:13.16#ibcon#flushed, iclass 28, count 0 2006.203.08:04:13.16#ibcon#about to write, iclass 28, count 0 2006.203.08:04:13.16#ibcon#wrote, iclass 28, count 0 2006.203.08:04:13.16#ibcon#about to read 3, iclass 28, count 0 2006.203.08:04:13.20#ibcon#read 3, iclass 28, count 0 2006.203.08:04:13.20#ibcon#about to read 4, iclass 28, count 0 2006.203.08:04:13.20#ibcon#read 4, iclass 28, count 0 2006.203.08:04:13.20#ibcon#about to read 5, iclass 28, count 0 2006.203.08:04:13.20#ibcon#read 5, iclass 28, count 0 2006.203.08:04:13.20#ibcon#about to read 6, iclass 28, count 0 2006.203.08:04:13.20#ibcon#read 6, iclass 28, count 0 2006.203.08:04:13.20#ibcon#end of sib2, iclass 28, count 0 2006.203.08:04:13.20#ibcon#*after write, iclass 28, count 0 2006.203.08:04:13.20#ibcon#*before return 0, iclass 28, count 0 2006.203.08:04:13.20#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.203.08:04:13.20#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.203.08:04:13.20#ibcon#about to clear, iclass 28 cls_cnt 0 2006.203.08:04:13.20#ibcon#cleared, iclass 28 cls_cnt 0 2006.203.08:04:13.20$vc4f8/vb=5,3 2006.203.08:04:13.20#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.203.08:04:13.20#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.203.08:04:13.20#ibcon#ireg 11 cls_cnt 2 2006.203.08:04:13.20#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.203.08:04:13.26#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.203.08:04:13.26#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.203.08:04:13.26#ibcon#enter wrdev, iclass 30, count 2 2006.203.08:04:13.26#ibcon#first serial, iclass 30, count 2 2006.203.08:04:13.26#ibcon#enter sib2, iclass 30, count 2 2006.203.08:04:13.26#ibcon#flushed, iclass 30, count 2 2006.203.08:04:13.26#ibcon#about to write, iclass 30, count 2 2006.203.08:04:13.26#ibcon#wrote, iclass 30, count 2 2006.203.08:04:13.26#ibcon#about to read 3, iclass 30, count 2 2006.203.08:04:13.28#ibcon#read 3, iclass 30, count 2 2006.203.08:04:13.28#ibcon#about to read 4, iclass 30, count 2 2006.203.08:04:13.28#ibcon#read 4, iclass 30, count 2 2006.203.08:04:13.28#ibcon#about to read 5, iclass 30, count 2 2006.203.08:04:13.28#ibcon#read 5, iclass 30, count 2 2006.203.08:04:13.28#ibcon#about to read 6, iclass 30, count 2 2006.203.08:04:13.28#ibcon#read 6, iclass 30, count 2 2006.203.08:04:13.28#ibcon#end of sib2, iclass 30, count 2 2006.203.08:04:13.28#ibcon#*mode == 0, iclass 30, count 2 2006.203.08:04:13.28#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.203.08:04:13.28#ibcon#[27=AT05-03\r\n] 2006.203.08:04:13.28#ibcon#*before write, iclass 30, count 2 2006.203.08:04:13.28#ibcon#enter sib2, iclass 30, count 2 2006.203.08:04:13.28#ibcon#flushed, iclass 30, count 2 2006.203.08:04:13.28#ibcon#about to write, iclass 30, count 2 2006.203.08:04:13.28#ibcon#wrote, iclass 30, count 2 2006.203.08:04:13.28#ibcon#about to read 3, iclass 30, count 2 2006.203.08:04:13.31#ibcon#read 3, iclass 30, count 2 2006.203.08:04:13.31#ibcon#about to read 4, iclass 30, count 2 2006.203.08:04:13.31#ibcon#read 4, iclass 30, count 2 2006.203.08:04:13.31#ibcon#about to read 5, iclass 30, count 2 2006.203.08:04:13.31#ibcon#read 5, iclass 30, count 2 2006.203.08:04:13.31#ibcon#about to read 6, iclass 30, count 2 2006.203.08:04:13.31#ibcon#read 6, iclass 30, count 2 2006.203.08:04:13.31#ibcon#end of sib2, iclass 30, count 2 2006.203.08:04:13.31#ibcon#*after write, iclass 30, count 2 2006.203.08:04:13.31#ibcon#*before return 0, iclass 30, count 2 2006.203.08:04:13.31#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.203.08:04:13.31#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.203.08:04:13.31#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.203.08:04:13.31#ibcon#ireg 7 cls_cnt 0 2006.203.08:04:13.31#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.203.08:04:13.43#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.203.08:04:13.43#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.203.08:04:13.43#ibcon#enter wrdev, iclass 30, count 0 2006.203.08:04:13.43#ibcon#first serial, iclass 30, count 0 2006.203.08:04:13.43#ibcon#enter sib2, iclass 30, count 0 2006.203.08:04:13.43#ibcon#flushed, iclass 30, count 0 2006.203.08:04:13.43#ibcon#about to write, iclass 30, count 0 2006.203.08:04:13.43#ibcon#wrote, iclass 30, count 0 2006.203.08:04:13.43#ibcon#about to read 3, iclass 30, count 0 2006.203.08:04:13.45#ibcon#read 3, iclass 30, count 0 2006.203.08:04:13.45#ibcon#about to read 4, iclass 30, count 0 2006.203.08:04:13.45#ibcon#read 4, iclass 30, count 0 2006.203.08:04:13.45#ibcon#about to read 5, iclass 30, count 0 2006.203.08:04:13.45#ibcon#read 5, iclass 30, count 0 2006.203.08:04:13.45#ibcon#about to read 6, iclass 30, count 0 2006.203.08:04:13.45#ibcon#read 6, iclass 30, count 0 2006.203.08:04:13.45#ibcon#end of sib2, iclass 30, count 0 2006.203.08:04:13.45#ibcon#*mode == 0, iclass 30, count 0 2006.203.08:04:13.45#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.203.08:04:13.45#ibcon#[27=USB\r\n] 2006.203.08:04:13.45#ibcon#*before write, iclass 30, count 0 2006.203.08:04:13.45#ibcon#enter sib2, iclass 30, count 0 2006.203.08:04:13.45#ibcon#flushed, iclass 30, count 0 2006.203.08:04:13.45#ibcon#about to write, iclass 30, count 0 2006.203.08:04:13.45#ibcon#wrote, iclass 30, count 0 2006.203.08:04:13.45#ibcon#about to read 3, iclass 30, count 0 2006.203.08:04:13.48#ibcon#read 3, iclass 30, count 0 2006.203.08:04:13.48#ibcon#about to read 4, iclass 30, count 0 2006.203.08:04:13.48#ibcon#read 4, iclass 30, count 0 2006.203.08:04:13.48#ibcon#about to read 5, iclass 30, count 0 2006.203.08:04:13.48#ibcon#read 5, iclass 30, count 0 2006.203.08:04:13.48#ibcon#about to read 6, iclass 30, count 0 2006.203.08:04:13.48#ibcon#read 6, iclass 30, count 0 2006.203.08:04:13.48#ibcon#end of sib2, iclass 30, count 0 2006.203.08:04:13.48#ibcon#*after write, iclass 30, count 0 2006.203.08:04:13.48#ibcon#*before return 0, iclass 30, count 0 2006.203.08:04:13.48#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.203.08:04:13.48#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.203.08:04:13.48#ibcon#about to clear, iclass 30 cls_cnt 0 2006.203.08:04:13.48#ibcon#cleared, iclass 30 cls_cnt 0 2006.203.08:04:13.48$vc4f8/vblo=6,752.99 2006.203.08:04:13.48#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.203.08:04:13.48#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.203.08:04:13.48#ibcon#ireg 17 cls_cnt 0 2006.203.08:04:13.48#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.203.08:04:13.48#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.203.08:04:13.48#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.203.08:04:13.48#ibcon#enter wrdev, iclass 32, count 0 2006.203.08:04:13.48#ibcon#first serial, iclass 32, count 0 2006.203.08:04:13.48#ibcon#enter sib2, iclass 32, count 0 2006.203.08:04:13.48#ibcon#flushed, iclass 32, count 0 2006.203.08:04:13.48#ibcon#about to write, iclass 32, count 0 2006.203.08:04:13.48#ibcon#wrote, iclass 32, count 0 2006.203.08:04:13.48#ibcon#about to read 3, iclass 32, count 0 2006.203.08:04:13.50#ibcon#read 3, iclass 32, count 0 2006.203.08:04:13.50#ibcon#about to read 4, iclass 32, count 0 2006.203.08:04:13.50#ibcon#read 4, iclass 32, count 0 2006.203.08:04:13.50#ibcon#about to read 5, iclass 32, count 0 2006.203.08:04:13.50#ibcon#read 5, iclass 32, count 0 2006.203.08:04:13.50#ibcon#about to read 6, iclass 32, count 0 2006.203.08:04:13.50#ibcon#read 6, iclass 32, count 0 2006.203.08:04:13.50#ibcon#end of sib2, iclass 32, count 0 2006.203.08:04:13.50#ibcon#*mode == 0, iclass 32, count 0 2006.203.08:04:13.50#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.203.08:04:13.50#ibcon#[28=FRQ=06,752.99\r\n] 2006.203.08:04:13.50#ibcon#*before write, iclass 32, count 0 2006.203.08:04:13.50#ibcon#enter sib2, iclass 32, count 0 2006.203.08:04:13.50#ibcon#flushed, iclass 32, count 0 2006.203.08:04:13.50#ibcon#about to write, iclass 32, count 0 2006.203.08:04:13.50#ibcon#wrote, iclass 32, count 0 2006.203.08:04:13.50#ibcon#about to read 3, iclass 32, count 0 2006.203.08:04:13.55#ibcon#read 3, iclass 32, count 0 2006.203.08:04:13.55#ibcon#about to read 4, iclass 32, count 0 2006.203.08:04:13.55#ibcon#read 4, iclass 32, count 0 2006.203.08:04:13.55#ibcon#about to read 5, iclass 32, count 0 2006.203.08:04:13.55#ibcon#read 5, iclass 32, count 0 2006.203.08:04:13.55#ibcon#about to read 6, iclass 32, count 0 2006.203.08:04:13.55#ibcon#read 6, iclass 32, count 0 2006.203.08:04:13.55#ibcon#end of sib2, iclass 32, count 0 2006.203.08:04:13.55#ibcon#*after write, iclass 32, count 0 2006.203.08:04:13.55#ibcon#*before return 0, iclass 32, count 0 2006.203.08:04:13.55#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.203.08:04:13.55#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.203.08:04:13.55#ibcon#about to clear, iclass 32 cls_cnt 0 2006.203.08:04:13.55#ibcon#cleared, iclass 32 cls_cnt 0 2006.203.08:04:13.55$vc4f8/vb=6,4 2006.203.08:04:13.55#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.203.08:04:13.55#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.203.08:04:13.55#ibcon#ireg 11 cls_cnt 2 2006.203.08:04:13.55#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.203.08:04:13.60#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.203.08:04:13.60#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.203.08:04:13.60#ibcon#enter wrdev, iclass 34, count 2 2006.203.08:04:13.60#ibcon#first serial, iclass 34, count 2 2006.203.08:04:13.60#ibcon#enter sib2, iclass 34, count 2 2006.203.08:04:13.60#ibcon#flushed, iclass 34, count 2 2006.203.08:04:13.60#ibcon#about to write, iclass 34, count 2 2006.203.08:04:13.60#ibcon#wrote, iclass 34, count 2 2006.203.08:04:13.60#ibcon#about to read 3, iclass 34, count 2 2006.203.08:04:13.62#ibcon#read 3, iclass 34, count 2 2006.203.08:04:13.62#ibcon#about to read 4, iclass 34, count 2 2006.203.08:04:13.62#ibcon#read 4, iclass 34, count 2 2006.203.08:04:13.62#ibcon#about to read 5, iclass 34, count 2 2006.203.08:04:13.62#ibcon#read 5, iclass 34, count 2 2006.203.08:04:13.62#ibcon#about to read 6, iclass 34, count 2 2006.203.08:04:13.62#ibcon#read 6, iclass 34, count 2 2006.203.08:04:13.62#ibcon#end of sib2, iclass 34, count 2 2006.203.08:04:13.62#ibcon#*mode == 0, iclass 34, count 2 2006.203.08:04:13.62#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.203.08:04:13.62#ibcon#[27=AT06-04\r\n] 2006.203.08:04:13.62#ibcon#*before write, iclass 34, count 2 2006.203.08:04:13.62#ibcon#enter sib2, iclass 34, count 2 2006.203.08:04:13.62#ibcon#flushed, iclass 34, count 2 2006.203.08:04:13.62#ibcon#about to write, iclass 34, count 2 2006.203.08:04:13.62#ibcon#wrote, iclass 34, count 2 2006.203.08:04:13.62#ibcon#about to read 3, iclass 34, count 2 2006.203.08:04:13.65#ibcon#read 3, iclass 34, count 2 2006.203.08:04:13.65#ibcon#about to read 4, iclass 34, count 2 2006.203.08:04:13.65#ibcon#read 4, iclass 34, count 2 2006.203.08:04:13.65#ibcon#about to read 5, iclass 34, count 2 2006.203.08:04:13.65#ibcon#read 5, iclass 34, count 2 2006.203.08:04:13.65#ibcon#about to read 6, iclass 34, count 2 2006.203.08:04:13.65#ibcon#read 6, iclass 34, count 2 2006.203.08:04:13.65#ibcon#end of sib2, iclass 34, count 2 2006.203.08:04:13.65#ibcon#*after write, iclass 34, count 2 2006.203.08:04:13.65#ibcon#*before return 0, iclass 34, count 2 2006.203.08:04:13.65#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.203.08:04:13.65#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.203.08:04:13.65#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.203.08:04:13.65#ibcon#ireg 7 cls_cnt 0 2006.203.08:04:13.65#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.203.08:04:13.77#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.203.08:04:13.77#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.203.08:04:13.77#ibcon#enter wrdev, iclass 34, count 0 2006.203.08:04:13.77#ibcon#first serial, iclass 34, count 0 2006.203.08:04:13.77#ibcon#enter sib2, iclass 34, count 0 2006.203.08:04:13.77#ibcon#flushed, iclass 34, count 0 2006.203.08:04:13.77#ibcon#about to write, iclass 34, count 0 2006.203.08:04:13.77#ibcon#wrote, iclass 34, count 0 2006.203.08:04:13.77#ibcon#about to read 3, iclass 34, count 0 2006.203.08:04:13.79#ibcon#read 3, iclass 34, count 0 2006.203.08:04:13.79#ibcon#about to read 4, iclass 34, count 0 2006.203.08:04:13.79#ibcon#read 4, iclass 34, count 0 2006.203.08:04:13.79#ibcon#about to read 5, iclass 34, count 0 2006.203.08:04:13.79#ibcon#read 5, iclass 34, count 0 2006.203.08:04:13.79#ibcon#about to read 6, iclass 34, count 0 2006.203.08:04:13.79#ibcon#read 6, iclass 34, count 0 2006.203.08:04:13.79#ibcon#end of sib2, iclass 34, count 0 2006.203.08:04:13.79#ibcon#*mode == 0, iclass 34, count 0 2006.203.08:04:13.79#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.203.08:04:13.79#ibcon#[27=USB\r\n] 2006.203.08:04:13.79#ibcon#*before write, iclass 34, count 0 2006.203.08:04:13.79#ibcon#enter sib2, iclass 34, count 0 2006.203.08:04:13.79#ibcon#flushed, iclass 34, count 0 2006.203.08:04:13.79#ibcon#about to write, iclass 34, count 0 2006.203.08:04:13.79#ibcon#wrote, iclass 34, count 0 2006.203.08:04:13.79#ibcon#about to read 3, iclass 34, count 0 2006.203.08:04:13.82#ibcon#read 3, iclass 34, count 0 2006.203.08:04:13.82#ibcon#about to read 4, iclass 34, count 0 2006.203.08:04:13.82#ibcon#read 4, iclass 34, count 0 2006.203.08:04:13.82#ibcon#about to read 5, iclass 34, count 0 2006.203.08:04:13.82#ibcon#read 5, iclass 34, count 0 2006.203.08:04:13.82#ibcon#about to read 6, iclass 34, count 0 2006.203.08:04:13.82#ibcon#read 6, iclass 34, count 0 2006.203.08:04:13.82#ibcon#end of sib2, iclass 34, count 0 2006.203.08:04:13.82#ibcon#*after write, iclass 34, count 0 2006.203.08:04:13.82#ibcon#*before return 0, iclass 34, count 0 2006.203.08:04:13.82#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.203.08:04:13.82#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.203.08:04:13.82#ibcon#about to clear, iclass 34 cls_cnt 0 2006.203.08:04:13.82#ibcon#cleared, iclass 34 cls_cnt 0 2006.203.08:04:13.82$vc4f8/vabw=wide 2006.203.08:04:13.82#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.203.08:04:13.82#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.203.08:04:13.82#ibcon#ireg 8 cls_cnt 0 2006.203.08:04:13.82#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.203.08:04:13.82#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.203.08:04:13.82#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.203.08:04:13.82#ibcon#enter wrdev, iclass 36, count 0 2006.203.08:04:13.82#ibcon#first serial, iclass 36, count 0 2006.203.08:04:13.82#ibcon#enter sib2, iclass 36, count 0 2006.203.08:04:13.82#ibcon#flushed, iclass 36, count 0 2006.203.08:04:13.82#ibcon#about to write, iclass 36, count 0 2006.203.08:04:13.82#ibcon#wrote, iclass 36, count 0 2006.203.08:04:13.82#ibcon#about to read 3, iclass 36, count 0 2006.203.08:04:13.84#ibcon#read 3, iclass 36, count 0 2006.203.08:04:13.84#ibcon#about to read 4, iclass 36, count 0 2006.203.08:04:13.84#ibcon#read 4, iclass 36, count 0 2006.203.08:04:13.84#ibcon#about to read 5, iclass 36, count 0 2006.203.08:04:13.84#ibcon#read 5, iclass 36, count 0 2006.203.08:04:13.84#ibcon#about to read 6, iclass 36, count 0 2006.203.08:04:13.84#ibcon#read 6, iclass 36, count 0 2006.203.08:04:13.84#ibcon#end of sib2, iclass 36, count 0 2006.203.08:04:13.84#ibcon#*mode == 0, iclass 36, count 0 2006.203.08:04:13.84#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.203.08:04:13.84#ibcon#[25=BW32\r\n] 2006.203.08:04:13.84#ibcon#*before write, iclass 36, count 0 2006.203.08:04:13.84#ibcon#enter sib2, iclass 36, count 0 2006.203.08:04:13.84#ibcon#flushed, iclass 36, count 0 2006.203.08:04:13.84#ibcon#about to write, iclass 36, count 0 2006.203.08:04:13.84#ibcon#wrote, iclass 36, count 0 2006.203.08:04:13.84#ibcon#about to read 3, iclass 36, count 0 2006.203.08:04:13.87#ibcon#read 3, iclass 36, count 0 2006.203.08:04:13.87#ibcon#about to read 4, iclass 36, count 0 2006.203.08:04:13.87#ibcon#read 4, iclass 36, count 0 2006.203.08:04:13.87#ibcon#about to read 5, iclass 36, count 0 2006.203.08:04:13.87#ibcon#read 5, iclass 36, count 0 2006.203.08:04:13.87#ibcon#about to read 6, iclass 36, count 0 2006.203.08:04:13.87#ibcon#read 6, iclass 36, count 0 2006.203.08:04:13.87#ibcon#end of sib2, iclass 36, count 0 2006.203.08:04:13.87#ibcon#*after write, iclass 36, count 0 2006.203.08:04:13.87#ibcon#*before return 0, iclass 36, count 0 2006.203.08:04:13.87#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.203.08:04:13.87#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.203.08:04:13.87#ibcon#about to clear, iclass 36 cls_cnt 0 2006.203.08:04:13.87#ibcon#cleared, iclass 36 cls_cnt 0 2006.203.08:04:13.87$vc4f8/vbbw=wide 2006.203.08:04:13.87#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.203.08:04:13.87#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.203.08:04:13.87#ibcon#ireg 8 cls_cnt 0 2006.203.08:04:13.87#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.203.08:04:13.94#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.203.08:04:13.94#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.203.08:04:13.94#ibcon#enter wrdev, iclass 38, count 0 2006.203.08:04:13.94#ibcon#first serial, iclass 38, count 0 2006.203.08:04:13.94#ibcon#enter sib2, iclass 38, count 0 2006.203.08:04:13.94#ibcon#flushed, iclass 38, count 0 2006.203.08:04:13.94#ibcon#about to write, iclass 38, count 0 2006.203.08:04:13.94#ibcon#wrote, iclass 38, count 0 2006.203.08:04:13.94#ibcon#about to read 3, iclass 38, count 0 2006.203.08:04:13.96#ibcon#read 3, iclass 38, count 0 2006.203.08:04:13.96#ibcon#about to read 4, iclass 38, count 0 2006.203.08:04:13.96#ibcon#read 4, iclass 38, count 0 2006.203.08:04:13.96#ibcon#about to read 5, iclass 38, count 0 2006.203.08:04:13.96#ibcon#read 5, iclass 38, count 0 2006.203.08:04:13.96#ibcon#about to read 6, iclass 38, count 0 2006.203.08:04:13.96#ibcon#read 6, iclass 38, count 0 2006.203.08:04:13.96#ibcon#end of sib2, iclass 38, count 0 2006.203.08:04:13.96#ibcon#*mode == 0, iclass 38, count 0 2006.203.08:04:13.96#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.203.08:04:13.96#ibcon#[27=BW32\r\n] 2006.203.08:04:13.96#ibcon#*before write, iclass 38, count 0 2006.203.08:04:13.96#ibcon#enter sib2, iclass 38, count 0 2006.203.08:04:13.96#ibcon#flushed, iclass 38, count 0 2006.203.08:04:13.96#ibcon#about to write, iclass 38, count 0 2006.203.08:04:13.96#ibcon#wrote, iclass 38, count 0 2006.203.08:04:13.96#ibcon#about to read 3, iclass 38, count 0 2006.203.08:04:13.99#ibcon#read 3, iclass 38, count 0 2006.203.08:04:13.99#ibcon#about to read 4, iclass 38, count 0 2006.203.08:04:13.99#ibcon#read 4, iclass 38, count 0 2006.203.08:04:13.99#ibcon#about to read 5, iclass 38, count 0 2006.203.08:04:13.99#ibcon#read 5, iclass 38, count 0 2006.203.08:04:13.99#ibcon#about to read 6, iclass 38, count 0 2006.203.08:04:13.99#ibcon#read 6, iclass 38, count 0 2006.203.08:04:13.99#ibcon#end of sib2, iclass 38, count 0 2006.203.08:04:13.99#ibcon#*after write, iclass 38, count 0 2006.203.08:04:13.99#ibcon#*before return 0, iclass 38, count 0 2006.203.08:04:13.99#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.203.08:04:13.99#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.203.08:04:13.99#ibcon#about to clear, iclass 38 cls_cnt 0 2006.203.08:04:13.99#ibcon#cleared, iclass 38 cls_cnt 0 2006.203.08:04:13.99$4f8m12a/ifd4f 2006.203.08:04:13.99$ifd4f/lo= 2006.203.08:04:13.99$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.203.08:04:13.99$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.203.08:04:13.99$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.203.08:04:13.99$ifd4f/patch= 2006.203.08:04:13.99$ifd4f/patch=lo1,a1,a2,a3,a4 2006.203.08:04:13.99$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.203.08:04:13.99$ifd4f/patch=lo3,a5,a6,a7,a8 2006.203.08:04:13.99$4f8m12a/"form=m,16.000,1:2 2006.203.08:04:13.99$4f8m12a/"tpicd 2006.203.08:04:13.99$4f8m12a/echo=off 2006.203.08:04:13.99$4f8m12a/xlog=off 2006.203.08:04:13.99:!2006.203.08:04:40 2006.203.08:04:23.13#trakl#Source acquired 2006.203.08:04:25.13#flagr#flagr/antenna,acquired 2006.203.08:04:40.00:preob 2006.203.08:04:41.13/onsource/TRACKING 2006.203.08:04:41.13:!2006.203.08:04:50 2006.203.08:04:50.00:data_valid=on 2006.203.08:04:50.00:midob 2006.203.08:04:50.13/onsource/TRACKING 2006.203.08:04:50.13/wx/23.68,1001.2,99 2006.203.08:04:50.34/cable/+6.4616E-03 2006.203.08:04:51.43/va/01,08,usb,yes,29,31 2006.203.08:04:51.43/va/02,07,usb,yes,30,31 2006.203.08:04:51.43/va/03,08,usb,yes,22,22 2006.203.08:04:51.43/va/04,07,usb,yes,30,33 2006.203.08:04:51.43/va/05,07,usb,yes,33,35 2006.203.08:04:51.43/va/06,06,usb,yes,32,32 2006.203.08:04:51.43/va/07,07,usb,yes,28,28 2006.203.08:04:51.43/va/08,06,usb,yes,35,34 2006.203.08:04:51.66/valo/01,532.99,yes,locked 2006.203.08:04:51.66/valo/02,572.99,yes,locked 2006.203.08:04:51.66/valo/03,672.99,yes,locked 2006.203.08:04:51.66/valo/04,832.99,yes,locked 2006.203.08:04:51.66/valo/05,652.99,yes,locked 2006.203.08:04:51.66/valo/06,772.99,yes,locked 2006.203.08:04:51.66/valo/07,832.99,yes,locked 2006.203.08:04:51.66/valo/08,852.99,yes,locked 2006.203.08:04:52.75/vb/01,04,usb,yes,28,27 2006.203.08:04:52.75/vb/02,04,usb,yes,30,31 2006.203.08:04:52.75/vb/03,04,usb,yes,27,30 2006.203.08:04:52.75/vb/04,04,usb,yes,27,27 2006.203.08:04:52.75/vb/05,03,usb,yes,33,37 2006.203.08:04:52.75/vb/06,04,usb,yes,27,30 2006.203.08:04:52.75/vb/07,04,usb,yes,29,29 2006.203.08:04:52.75/vb/08,04,usb,yes,27,30 2006.203.08:04:52.98/vblo/01,632.99,yes,locked 2006.203.08:04:52.98/vblo/02,640.99,yes,locked 2006.203.08:04:52.98/vblo/03,656.99,yes,locked 2006.203.08:04:52.98/vblo/04,712.99,yes,locked 2006.203.08:04:52.98/vblo/05,744.99,yes,locked 2006.203.08:04:52.98/vblo/06,752.99,yes,locked 2006.203.08:04:52.98/vblo/07,734.99,yes,locked 2006.203.08:04:52.98/vblo/08,744.99,yes,locked 2006.203.08:04:53.13/vabw/8 2006.203.08:04:53.28/vbbw/8 2006.203.08:04:53.37/xfe/off,on,12.7 2006.203.08:04:53.75/ifatt/23,28,28,28 2006.203.08:04:54.08/fmout-gps/S +4.58E-07 2006.203.08:04:54.15:!2006.203.08:05:50 2006.203.08:05:50.00:data_valid=off 2006.203.08:05:50.00:postob 2006.203.08:05:50.07/cable/+6.4596E-03 2006.203.08:05:50.08/wx/23.69,1001.1,100 2006.203.08:05:51.08/fmout-gps/S +4.56E-07 2006.203.08:05:51.08:scan_name=203-0806,k06203,60 2006.203.08:05:51.08:source=3c418,203837.03,511912.7,2000.0,cw 2006.203.08:05:51.14#flagr#flagr/antenna,new-source 2006.203.08:05:52.14:checkk5 2006.203.08:05:52.58/chk_autoobs//k5ts1/ autoobs is running! 2006.203.08:05:52.99/chk_autoobs//k5ts2/ autoobs is running! 2006.203.08:05:53.41/chk_autoobs//k5ts3/ autoobs is running! 2006.203.08:05:53.88/chk_autoobs//k5ts4/ autoobs is running! 2006.203.08:05:54.28/chk_obsdata//k5ts1/T2030804??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.203.08:05:54.70/chk_obsdata//k5ts2/T2030804??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.203.08:05:55.32/chk_obsdata//k5ts3/T2030804??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.203.08:05:55.74/chk_obsdata//k5ts4/T2030804??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.203.08:05:56.48/k5log//k5ts1_log_newline 2006.203.08:05:57.27/k5log//k5ts2_log_newline 2006.203.08:05:58.04/k5log//k5ts3_log_newline 2006.203.08:05:58.80/k5log//k5ts4_log_newline 2006.203.08:05:58.82/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.203.08:05:58.82:4f8m12a=2 2006.203.08:05:58.82$4f8m12a/echo=on 2006.203.08:05:58.82$4f8m12a/pcalon 2006.203.08:05:58.83$pcalon/"no phase cal control is implemented here 2006.203.08:05:58.83$4f8m12a/"tpicd=stop 2006.203.08:05:58.83$4f8m12a/vc4f8 2006.203.08:05:58.83$vc4f8/valo=1,532.99 2006.203.08:05:58.83#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.203.08:05:58.83#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.203.08:05:58.83#ibcon#ireg 17 cls_cnt 0 2006.203.08:05:58.83#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.203.08:05:58.83#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.203.08:05:58.83#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.203.08:05:58.83#ibcon#enter wrdev, iclass 13, count 0 2006.203.08:05:58.83#ibcon#first serial, iclass 13, count 0 2006.203.08:05:58.83#ibcon#enter sib2, iclass 13, count 0 2006.203.08:05:58.83#ibcon#flushed, iclass 13, count 0 2006.203.08:05:58.83#ibcon#about to write, iclass 13, count 0 2006.203.08:05:58.83#ibcon#wrote, iclass 13, count 0 2006.203.08:05:58.83#ibcon#about to read 3, iclass 13, count 0 2006.203.08:05:58.87#ibcon#read 3, iclass 13, count 0 2006.203.08:05:58.87#ibcon#about to read 4, iclass 13, count 0 2006.203.08:05:58.87#ibcon#read 4, iclass 13, count 0 2006.203.08:05:58.87#ibcon#about to read 5, iclass 13, count 0 2006.203.08:05:58.87#ibcon#read 5, iclass 13, count 0 2006.203.08:05:58.87#ibcon#about to read 6, iclass 13, count 0 2006.203.08:05:58.87#ibcon#read 6, iclass 13, count 0 2006.203.08:05:58.87#ibcon#end of sib2, iclass 13, count 0 2006.203.08:05:58.87#ibcon#*mode == 0, iclass 13, count 0 2006.203.08:05:58.87#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.203.08:05:58.87#ibcon#[26=FRQ=01,532.99\r\n] 2006.203.08:05:58.87#ibcon#*before write, iclass 13, count 0 2006.203.08:05:58.87#ibcon#enter sib2, iclass 13, count 0 2006.203.08:05:58.87#ibcon#flushed, iclass 13, count 0 2006.203.08:05:58.87#ibcon#about to write, iclass 13, count 0 2006.203.08:05:58.87#ibcon#wrote, iclass 13, count 0 2006.203.08:05:58.87#ibcon#about to read 3, iclass 13, count 0 2006.203.08:05:58.92#ibcon#read 3, iclass 13, count 0 2006.203.08:05:58.92#ibcon#about to read 4, iclass 13, count 0 2006.203.08:05:58.92#ibcon#read 4, iclass 13, count 0 2006.203.08:05:58.92#ibcon#about to read 5, iclass 13, count 0 2006.203.08:05:58.92#ibcon#read 5, iclass 13, count 0 2006.203.08:05:58.92#ibcon#about to read 6, iclass 13, count 0 2006.203.08:05:58.92#ibcon#read 6, iclass 13, count 0 2006.203.08:05:58.92#ibcon#end of sib2, iclass 13, count 0 2006.203.08:05:58.92#ibcon#*after write, iclass 13, count 0 2006.203.08:05:58.92#ibcon#*before return 0, iclass 13, count 0 2006.203.08:05:58.92#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.203.08:05:58.92#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.203.08:05:58.92#ibcon#about to clear, iclass 13 cls_cnt 0 2006.203.08:05:58.92#ibcon#cleared, iclass 13 cls_cnt 0 2006.203.08:05:58.92$vc4f8/va=1,8 2006.203.08:05:58.92#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.203.08:05:58.92#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.203.08:05:58.92#ibcon#ireg 11 cls_cnt 2 2006.203.08:05:58.92#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.203.08:05:58.92#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.203.08:05:58.92#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.203.08:05:58.92#ibcon#enter wrdev, iclass 15, count 2 2006.203.08:05:58.92#ibcon#first serial, iclass 15, count 2 2006.203.08:05:58.92#ibcon#enter sib2, iclass 15, count 2 2006.203.08:05:58.92#ibcon#flushed, iclass 15, count 2 2006.203.08:05:58.92#ibcon#about to write, iclass 15, count 2 2006.203.08:05:58.92#ibcon#wrote, iclass 15, count 2 2006.203.08:05:58.92#ibcon#about to read 3, iclass 15, count 2 2006.203.08:05:58.94#ibcon#read 3, iclass 15, count 2 2006.203.08:05:58.94#ibcon#about to read 4, iclass 15, count 2 2006.203.08:05:58.94#ibcon#read 4, iclass 15, count 2 2006.203.08:05:58.94#ibcon#about to read 5, iclass 15, count 2 2006.203.08:05:58.94#ibcon#read 5, iclass 15, count 2 2006.203.08:05:58.94#ibcon#about to read 6, iclass 15, count 2 2006.203.08:05:58.94#ibcon#read 6, iclass 15, count 2 2006.203.08:05:58.94#ibcon#end of sib2, iclass 15, count 2 2006.203.08:05:58.94#ibcon#*mode == 0, iclass 15, count 2 2006.203.08:05:58.94#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.203.08:05:58.94#ibcon#[25=AT01-08\r\n] 2006.203.08:05:58.94#ibcon#*before write, iclass 15, count 2 2006.203.08:05:58.94#ibcon#enter sib2, iclass 15, count 2 2006.203.08:05:58.94#ibcon#flushed, iclass 15, count 2 2006.203.08:05:58.94#ibcon#about to write, iclass 15, count 2 2006.203.08:05:58.94#ibcon#wrote, iclass 15, count 2 2006.203.08:05:58.94#ibcon#about to read 3, iclass 15, count 2 2006.203.08:05:58.97#ibcon#read 3, iclass 15, count 2 2006.203.08:05:58.97#ibcon#about to read 4, iclass 15, count 2 2006.203.08:05:58.97#ibcon#read 4, iclass 15, count 2 2006.203.08:05:58.97#ibcon#about to read 5, iclass 15, count 2 2006.203.08:05:58.97#ibcon#read 5, iclass 15, count 2 2006.203.08:05:58.97#ibcon#about to read 6, iclass 15, count 2 2006.203.08:05:58.97#ibcon#read 6, iclass 15, count 2 2006.203.08:05:58.97#ibcon#end of sib2, iclass 15, count 2 2006.203.08:05:58.97#ibcon#*after write, iclass 15, count 2 2006.203.08:05:58.97#ibcon#*before return 0, iclass 15, count 2 2006.203.08:05:58.97#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.203.08:05:58.97#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.203.08:05:58.97#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.203.08:05:58.97#ibcon#ireg 7 cls_cnt 0 2006.203.08:05:58.97#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.203.08:05:59.09#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.203.08:05:59.09#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.203.08:05:59.09#ibcon#enter wrdev, iclass 15, count 0 2006.203.08:05:59.09#ibcon#first serial, iclass 15, count 0 2006.203.08:05:59.09#ibcon#enter sib2, iclass 15, count 0 2006.203.08:05:59.09#ibcon#flushed, iclass 15, count 0 2006.203.08:05:59.09#ibcon#about to write, iclass 15, count 0 2006.203.08:05:59.09#ibcon#wrote, iclass 15, count 0 2006.203.08:05:59.09#ibcon#about to read 3, iclass 15, count 0 2006.203.08:05:59.11#ibcon#read 3, iclass 15, count 0 2006.203.08:05:59.11#ibcon#about to read 4, iclass 15, count 0 2006.203.08:05:59.11#ibcon#read 4, iclass 15, count 0 2006.203.08:05:59.11#ibcon#about to read 5, iclass 15, count 0 2006.203.08:05:59.11#ibcon#read 5, iclass 15, count 0 2006.203.08:05:59.11#ibcon#about to read 6, iclass 15, count 0 2006.203.08:05:59.11#ibcon#read 6, iclass 15, count 0 2006.203.08:05:59.11#ibcon#end of sib2, iclass 15, count 0 2006.203.08:05:59.11#ibcon#*mode == 0, iclass 15, count 0 2006.203.08:05:59.11#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.203.08:05:59.11#ibcon#[25=USB\r\n] 2006.203.08:05:59.11#ibcon#*before write, iclass 15, count 0 2006.203.08:05:59.11#ibcon#enter sib2, iclass 15, count 0 2006.203.08:05:59.11#ibcon#flushed, iclass 15, count 0 2006.203.08:05:59.11#ibcon#about to write, iclass 15, count 0 2006.203.08:05:59.11#ibcon#wrote, iclass 15, count 0 2006.203.08:05:59.11#ibcon#about to read 3, iclass 15, count 0 2006.203.08:05:59.14#ibcon#read 3, iclass 15, count 0 2006.203.08:05:59.14#ibcon#about to read 4, iclass 15, count 0 2006.203.08:05:59.14#ibcon#read 4, iclass 15, count 0 2006.203.08:05:59.14#ibcon#about to read 5, iclass 15, count 0 2006.203.08:05:59.14#ibcon#read 5, iclass 15, count 0 2006.203.08:05:59.14#ibcon#about to read 6, iclass 15, count 0 2006.203.08:05:59.14#ibcon#read 6, iclass 15, count 0 2006.203.08:05:59.14#ibcon#end of sib2, iclass 15, count 0 2006.203.08:05:59.14#ibcon#*after write, iclass 15, count 0 2006.203.08:05:59.14#ibcon#*before return 0, iclass 15, count 0 2006.203.08:05:59.14#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.203.08:05:59.14#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.203.08:05:59.14#ibcon#about to clear, iclass 15 cls_cnt 0 2006.203.08:05:59.14#ibcon#cleared, iclass 15 cls_cnt 0 2006.203.08:05:59.14$vc4f8/valo=2,572.99 2006.203.08:05:59.14#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.203.08:05:59.14#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.203.08:05:59.14#ibcon#ireg 17 cls_cnt 0 2006.203.08:05:59.14#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.203.08:05:59.14#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.203.08:05:59.14#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.203.08:05:59.14#ibcon#enter wrdev, iclass 17, count 0 2006.203.08:05:59.14#ibcon#first serial, iclass 17, count 0 2006.203.08:05:59.14#ibcon#enter sib2, iclass 17, count 0 2006.203.08:05:59.14#ibcon#flushed, iclass 17, count 0 2006.203.08:05:59.14#ibcon#about to write, iclass 17, count 0 2006.203.08:05:59.14#ibcon#wrote, iclass 17, count 0 2006.203.08:05:59.14#ibcon#about to read 3, iclass 17, count 0 2006.203.08:05:59.16#ibcon#read 3, iclass 17, count 0 2006.203.08:05:59.16#ibcon#about to read 4, iclass 17, count 0 2006.203.08:05:59.16#ibcon#read 4, iclass 17, count 0 2006.203.08:05:59.16#ibcon#about to read 5, iclass 17, count 0 2006.203.08:05:59.16#ibcon#read 5, iclass 17, count 0 2006.203.08:05:59.16#ibcon#about to read 6, iclass 17, count 0 2006.203.08:05:59.16#ibcon#read 6, iclass 17, count 0 2006.203.08:05:59.16#ibcon#end of sib2, iclass 17, count 0 2006.203.08:05:59.16#ibcon#*mode == 0, iclass 17, count 0 2006.203.08:05:59.16#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.203.08:05:59.16#ibcon#[26=FRQ=02,572.99\r\n] 2006.203.08:05:59.16#ibcon#*before write, iclass 17, count 0 2006.203.08:05:59.16#ibcon#enter sib2, iclass 17, count 0 2006.203.08:05:59.16#ibcon#flushed, iclass 17, count 0 2006.203.08:05:59.16#ibcon#about to write, iclass 17, count 0 2006.203.08:05:59.16#ibcon#wrote, iclass 17, count 0 2006.203.08:05:59.16#ibcon#about to read 3, iclass 17, count 0 2006.203.08:05:59.20#ibcon#read 3, iclass 17, count 0 2006.203.08:05:59.20#ibcon#about to read 4, iclass 17, count 0 2006.203.08:05:59.20#ibcon#read 4, iclass 17, count 0 2006.203.08:05:59.20#ibcon#about to read 5, iclass 17, count 0 2006.203.08:05:59.20#ibcon#read 5, iclass 17, count 0 2006.203.08:05:59.20#ibcon#about to read 6, iclass 17, count 0 2006.203.08:05:59.20#ibcon#read 6, iclass 17, count 0 2006.203.08:05:59.20#ibcon#end of sib2, iclass 17, count 0 2006.203.08:05:59.20#ibcon#*after write, iclass 17, count 0 2006.203.08:05:59.20#ibcon#*before return 0, iclass 17, count 0 2006.203.08:05:59.20#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.203.08:05:59.20#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.203.08:05:59.20#ibcon#about to clear, iclass 17 cls_cnt 0 2006.203.08:05:59.20#ibcon#cleared, iclass 17 cls_cnt 0 2006.203.08:05:59.20$vc4f8/va=2,7 2006.203.08:05:59.20#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.203.08:05:59.20#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.203.08:05:59.20#ibcon#ireg 11 cls_cnt 2 2006.203.08:05:59.20#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.203.08:05:59.26#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.203.08:05:59.26#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.203.08:05:59.26#ibcon#enter wrdev, iclass 19, count 2 2006.203.08:05:59.26#ibcon#first serial, iclass 19, count 2 2006.203.08:05:59.26#ibcon#enter sib2, iclass 19, count 2 2006.203.08:05:59.26#ibcon#flushed, iclass 19, count 2 2006.203.08:05:59.26#ibcon#about to write, iclass 19, count 2 2006.203.08:05:59.26#ibcon#wrote, iclass 19, count 2 2006.203.08:05:59.26#ibcon#about to read 3, iclass 19, count 2 2006.203.08:05:59.28#ibcon#read 3, iclass 19, count 2 2006.203.08:05:59.28#ibcon#about to read 4, iclass 19, count 2 2006.203.08:05:59.28#ibcon#read 4, iclass 19, count 2 2006.203.08:05:59.28#ibcon#about to read 5, iclass 19, count 2 2006.203.08:05:59.28#ibcon#read 5, iclass 19, count 2 2006.203.08:05:59.28#ibcon#about to read 6, iclass 19, count 2 2006.203.08:05:59.28#ibcon#read 6, iclass 19, count 2 2006.203.08:05:59.28#ibcon#end of sib2, iclass 19, count 2 2006.203.08:05:59.28#ibcon#*mode == 0, iclass 19, count 2 2006.203.08:05:59.28#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.203.08:05:59.28#ibcon#[25=AT02-07\r\n] 2006.203.08:05:59.28#ibcon#*before write, iclass 19, count 2 2006.203.08:05:59.28#ibcon#enter sib2, iclass 19, count 2 2006.203.08:05:59.28#ibcon#flushed, iclass 19, count 2 2006.203.08:05:59.28#ibcon#about to write, iclass 19, count 2 2006.203.08:05:59.28#ibcon#wrote, iclass 19, count 2 2006.203.08:05:59.28#ibcon#about to read 3, iclass 19, count 2 2006.203.08:05:59.31#ibcon#read 3, iclass 19, count 2 2006.203.08:05:59.31#ibcon#about to read 4, iclass 19, count 2 2006.203.08:05:59.31#ibcon#read 4, iclass 19, count 2 2006.203.08:05:59.31#ibcon#about to read 5, iclass 19, count 2 2006.203.08:05:59.31#ibcon#read 5, iclass 19, count 2 2006.203.08:05:59.31#ibcon#about to read 6, iclass 19, count 2 2006.203.08:05:59.31#ibcon#read 6, iclass 19, count 2 2006.203.08:05:59.31#ibcon#end of sib2, iclass 19, count 2 2006.203.08:05:59.31#ibcon#*after write, iclass 19, count 2 2006.203.08:05:59.31#ibcon#*before return 0, iclass 19, count 2 2006.203.08:05:59.31#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.203.08:05:59.31#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.203.08:05:59.31#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.203.08:05:59.31#ibcon#ireg 7 cls_cnt 0 2006.203.08:05:59.31#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.203.08:05:59.43#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.203.08:05:59.43#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.203.08:05:59.43#ibcon#enter wrdev, iclass 19, count 0 2006.203.08:05:59.43#ibcon#first serial, iclass 19, count 0 2006.203.08:05:59.43#ibcon#enter sib2, iclass 19, count 0 2006.203.08:05:59.43#ibcon#flushed, iclass 19, count 0 2006.203.08:05:59.43#ibcon#about to write, iclass 19, count 0 2006.203.08:05:59.43#ibcon#wrote, iclass 19, count 0 2006.203.08:05:59.43#ibcon#about to read 3, iclass 19, count 0 2006.203.08:05:59.45#ibcon#read 3, iclass 19, count 0 2006.203.08:05:59.45#ibcon#about to read 4, iclass 19, count 0 2006.203.08:05:59.45#ibcon#read 4, iclass 19, count 0 2006.203.08:05:59.45#ibcon#about to read 5, iclass 19, count 0 2006.203.08:05:59.45#ibcon#read 5, iclass 19, count 0 2006.203.08:05:59.45#ibcon#about to read 6, iclass 19, count 0 2006.203.08:05:59.45#ibcon#read 6, iclass 19, count 0 2006.203.08:05:59.45#ibcon#end of sib2, iclass 19, count 0 2006.203.08:05:59.45#ibcon#*mode == 0, iclass 19, count 0 2006.203.08:05:59.45#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.203.08:05:59.45#ibcon#[25=USB\r\n] 2006.203.08:05:59.45#ibcon#*before write, iclass 19, count 0 2006.203.08:05:59.45#ibcon#enter sib2, iclass 19, count 0 2006.203.08:05:59.45#ibcon#flushed, iclass 19, count 0 2006.203.08:05:59.45#ibcon#about to write, iclass 19, count 0 2006.203.08:05:59.45#ibcon#wrote, iclass 19, count 0 2006.203.08:05:59.45#ibcon#about to read 3, iclass 19, count 0 2006.203.08:05:59.48#ibcon#read 3, iclass 19, count 0 2006.203.08:05:59.48#ibcon#about to read 4, iclass 19, count 0 2006.203.08:05:59.48#ibcon#read 4, iclass 19, count 0 2006.203.08:05:59.48#ibcon#about to read 5, iclass 19, count 0 2006.203.08:05:59.48#ibcon#read 5, iclass 19, count 0 2006.203.08:05:59.48#ibcon#about to read 6, iclass 19, count 0 2006.203.08:05:59.48#ibcon#read 6, iclass 19, count 0 2006.203.08:05:59.48#ibcon#end of sib2, iclass 19, count 0 2006.203.08:05:59.48#ibcon#*after write, iclass 19, count 0 2006.203.08:05:59.48#ibcon#*before return 0, iclass 19, count 0 2006.203.08:05:59.48#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.203.08:05:59.48#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.203.08:05:59.48#ibcon#about to clear, iclass 19 cls_cnt 0 2006.203.08:05:59.48#ibcon#cleared, iclass 19 cls_cnt 0 2006.203.08:05:59.48$vc4f8/valo=3,672.99 2006.203.08:05:59.48#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.203.08:05:59.48#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.203.08:05:59.48#ibcon#ireg 17 cls_cnt 0 2006.203.08:05:59.48#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.203.08:05:59.48#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.203.08:05:59.48#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.203.08:05:59.48#ibcon#enter wrdev, iclass 21, count 0 2006.203.08:05:59.48#ibcon#first serial, iclass 21, count 0 2006.203.08:05:59.48#ibcon#enter sib2, iclass 21, count 0 2006.203.08:05:59.48#ibcon#flushed, iclass 21, count 0 2006.203.08:05:59.48#ibcon#about to write, iclass 21, count 0 2006.203.08:05:59.48#ibcon#wrote, iclass 21, count 0 2006.203.08:05:59.48#ibcon#about to read 3, iclass 21, count 0 2006.203.08:05:59.50#ibcon#read 3, iclass 21, count 0 2006.203.08:05:59.50#ibcon#about to read 4, iclass 21, count 0 2006.203.08:05:59.50#ibcon#read 4, iclass 21, count 0 2006.203.08:05:59.50#ibcon#about to read 5, iclass 21, count 0 2006.203.08:05:59.50#ibcon#read 5, iclass 21, count 0 2006.203.08:05:59.50#ibcon#about to read 6, iclass 21, count 0 2006.203.08:05:59.50#ibcon#read 6, iclass 21, count 0 2006.203.08:05:59.50#ibcon#end of sib2, iclass 21, count 0 2006.203.08:05:59.50#ibcon#*mode == 0, iclass 21, count 0 2006.203.08:05:59.50#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.203.08:05:59.50#ibcon#[26=FRQ=03,672.99\r\n] 2006.203.08:05:59.50#ibcon#*before write, iclass 21, count 0 2006.203.08:05:59.50#ibcon#enter sib2, iclass 21, count 0 2006.203.08:05:59.50#ibcon#flushed, iclass 21, count 0 2006.203.08:05:59.50#ibcon#about to write, iclass 21, count 0 2006.203.08:05:59.50#ibcon#wrote, iclass 21, count 0 2006.203.08:05:59.50#ibcon#about to read 3, iclass 21, count 0 2006.203.08:05:59.54#ibcon#read 3, iclass 21, count 0 2006.203.08:05:59.54#ibcon#about to read 4, iclass 21, count 0 2006.203.08:05:59.54#ibcon#read 4, iclass 21, count 0 2006.203.08:05:59.54#ibcon#about to read 5, iclass 21, count 0 2006.203.08:05:59.54#ibcon#read 5, iclass 21, count 0 2006.203.08:05:59.54#ibcon#about to read 6, iclass 21, count 0 2006.203.08:05:59.54#ibcon#read 6, iclass 21, count 0 2006.203.08:05:59.54#ibcon#end of sib2, iclass 21, count 0 2006.203.08:05:59.54#ibcon#*after write, iclass 21, count 0 2006.203.08:05:59.54#ibcon#*before return 0, iclass 21, count 0 2006.203.08:05:59.54#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.203.08:05:59.54#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.203.08:05:59.54#ibcon#about to clear, iclass 21 cls_cnt 0 2006.203.08:05:59.54#ibcon#cleared, iclass 21 cls_cnt 0 2006.203.08:05:59.54$vc4f8/va=3,8 2006.203.08:05:59.54#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.203.08:05:59.54#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.203.08:05:59.54#ibcon#ireg 11 cls_cnt 2 2006.203.08:05:59.54#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.203.08:05:59.60#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.203.08:05:59.60#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.203.08:05:59.60#ibcon#enter wrdev, iclass 23, count 2 2006.203.08:05:59.60#ibcon#first serial, iclass 23, count 2 2006.203.08:05:59.60#ibcon#enter sib2, iclass 23, count 2 2006.203.08:05:59.60#ibcon#flushed, iclass 23, count 2 2006.203.08:05:59.60#ibcon#about to write, iclass 23, count 2 2006.203.08:05:59.60#ibcon#wrote, iclass 23, count 2 2006.203.08:05:59.60#ibcon#about to read 3, iclass 23, count 2 2006.203.08:05:59.62#ibcon#read 3, iclass 23, count 2 2006.203.08:05:59.62#ibcon#about to read 4, iclass 23, count 2 2006.203.08:05:59.62#ibcon#read 4, iclass 23, count 2 2006.203.08:05:59.62#ibcon#about to read 5, iclass 23, count 2 2006.203.08:05:59.62#ibcon#read 5, iclass 23, count 2 2006.203.08:05:59.62#ibcon#about to read 6, iclass 23, count 2 2006.203.08:05:59.62#ibcon#read 6, iclass 23, count 2 2006.203.08:05:59.62#ibcon#end of sib2, iclass 23, count 2 2006.203.08:05:59.62#ibcon#*mode == 0, iclass 23, count 2 2006.203.08:05:59.62#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.203.08:05:59.62#ibcon#[25=AT03-08\r\n] 2006.203.08:05:59.62#ibcon#*before write, iclass 23, count 2 2006.203.08:05:59.62#ibcon#enter sib2, iclass 23, count 2 2006.203.08:05:59.62#ibcon#flushed, iclass 23, count 2 2006.203.08:05:59.62#ibcon#about to write, iclass 23, count 2 2006.203.08:05:59.62#ibcon#wrote, iclass 23, count 2 2006.203.08:05:59.62#ibcon#about to read 3, iclass 23, count 2 2006.203.08:05:59.65#ibcon#read 3, iclass 23, count 2 2006.203.08:05:59.65#ibcon#about to read 4, iclass 23, count 2 2006.203.08:05:59.65#ibcon#read 4, iclass 23, count 2 2006.203.08:05:59.65#ibcon#about to read 5, iclass 23, count 2 2006.203.08:05:59.65#ibcon#read 5, iclass 23, count 2 2006.203.08:05:59.65#ibcon#about to read 6, iclass 23, count 2 2006.203.08:05:59.65#ibcon#read 6, iclass 23, count 2 2006.203.08:05:59.65#ibcon#end of sib2, iclass 23, count 2 2006.203.08:05:59.65#ibcon#*after write, iclass 23, count 2 2006.203.08:05:59.65#ibcon#*before return 0, iclass 23, count 2 2006.203.08:05:59.65#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.203.08:05:59.65#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.203.08:05:59.65#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.203.08:05:59.65#ibcon#ireg 7 cls_cnt 0 2006.203.08:05:59.65#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.203.08:05:59.77#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.203.08:05:59.77#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.203.08:05:59.77#ibcon#enter wrdev, iclass 23, count 0 2006.203.08:05:59.77#ibcon#first serial, iclass 23, count 0 2006.203.08:05:59.77#ibcon#enter sib2, iclass 23, count 0 2006.203.08:05:59.77#ibcon#flushed, iclass 23, count 0 2006.203.08:05:59.77#ibcon#about to write, iclass 23, count 0 2006.203.08:05:59.77#ibcon#wrote, iclass 23, count 0 2006.203.08:05:59.77#ibcon#about to read 3, iclass 23, count 0 2006.203.08:05:59.79#ibcon#read 3, iclass 23, count 0 2006.203.08:05:59.79#ibcon#about to read 4, iclass 23, count 0 2006.203.08:05:59.79#ibcon#read 4, iclass 23, count 0 2006.203.08:05:59.79#ibcon#about to read 5, iclass 23, count 0 2006.203.08:05:59.79#ibcon#read 5, iclass 23, count 0 2006.203.08:05:59.79#ibcon#about to read 6, iclass 23, count 0 2006.203.08:05:59.79#ibcon#read 6, iclass 23, count 0 2006.203.08:05:59.79#ibcon#end of sib2, iclass 23, count 0 2006.203.08:05:59.79#ibcon#*mode == 0, iclass 23, count 0 2006.203.08:05:59.79#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.203.08:05:59.79#ibcon#[25=USB\r\n] 2006.203.08:05:59.79#ibcon#*before write, iclass 23, count 0 2006.203.08:05:59.79#ibcon#enter sib2, iclass 23, count 0 2006.203.08:05:59.79#ibcon#flushed, iclass 23, count 0 2006.203.08:05:59.79#ibcon#about to write, iclass 23, count 0 2006.203.08:05:59.79#ibcon#wrote, iclass 23, count 0 2006.203.08:05:59.79#ibcon#about to read 3, iclass 23, count 0 2006.203.08:05:59.82#ibcon#read 3, iclass 23, count 0 2006.203.08:05:59.82#ibcon#about to read 4, iclass 23, count 0 2006.203.08:05:59.82#ibcon#read 4, iclass 23, count 0 2006.203.08:05:59.82#ibcon#about to read 5, iclass 23, count 0 2006.203.08:05:59.82#ibcon#read 5, iclass 23, count 0 2006.203.08:05:59.82#ibcon#about to read 6, iclass 23, count 0 2006.203.08:05:59.82#ibcon#read 6, iclass 23, count 0 2006.203.08:05:59.82#ibcon#end of sib2, iclass 23, count 0 2006.203.08:05:59.82#ibcon#*after write, iclass 23, count 0 2006.203.08:05:59.82#ibcon#*before return 0, iclass 23, count 0 2006.203.08:05:59.82#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.203.08:05:59.82#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.203.08:05:59.82#ibcon#about to clear, iclass 23 cls_cnt 0 2006.203.08:05:59.82#ibcon#cleared, iclass 23 cls_cnt 0 2006.203.08:05:59.82$vc4f8/valo=4,832.99 2006.203.08:05:59.82#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.203.08:05:59.82#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.203.08:05:59.82#ibcon#ireg 17 cls_cnt 0 2006.203.08:05:59.82#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.203.08:05:59.82#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.203.08:05:59.82#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.203.08:05:59.82#ibcon#enter wrdev, iclass 25, count 0 2006.203.08:05:59.82#ibcon#first serial, iclass 25, count 0 2006.203.08:05:59.82#ibcon#enter sib2, iclass 25, count 0 2006.203.08:05:59.82#ibcon#flushed, iclass 25, count 0 2006.203.08:05:59.82#ibcon#about to write, iclass 25, count 0 2006.203.08:05:59.82#ibcon#wrote, iclass 25, count 0 2006.203.08:05:59.82#ibcon#about to read 3, iclass 25, count 0 2006.203.08:05:59.84#ibcon#read 3, iclass 25, count 0 2006.203.08:05:59.84#ibcon#about to read 4, iclass 25, count 0 2006.203.08:05:59.84#ibcon#read 4, iclass 25, count 0 2006.203.08:05:59.84#ibcon#about to read 5, iclass 25, count 0 2006.203.08:05:59.84#ibcon#read 5, iclass 25, count 0 2006.203.08:05:59.84#ibcon#about to read 6, iclass 25, count 0 2006.203.08:05:59.84#ibcon#read 6, iclass 25, count 0 2006.203.08:05:59.84#ibcon#end of sib2, iclass 25, count 0 2006.203.08:05:59.84#ibcon#*mode == 0, iclass 25, count 0 2006.203.08:05:59.84#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.203.08:05:59.84#ibcon#[26=FRQ=04,832.99\r\n] 2006.203.08:05:59.84#ibcon#*before write, iclass 25, count 0 2006.203.08:05:59.84#ibcon#enter sib2, iclass 25, count 0 2006.203.08:05:59.84#ibcon#flushed, iclass 25, count 0 2006.203.08:05:59.84#ibcon#about to write, iclass 25, count 0 2006.203.08:05:59.84#ibcon#wrote, iclass 25, count 0 2006.203.08:05:59.84#ibcon#about to read 3, iclass 25, count 0 2006.203.08:05:59.88#ibcon#read 3, iclass 25, count 0 2006.203.08:05:59.88#ibcon#about to read 4, iclass 25, count 0 2006.203.08:05:59.88#ibcon#read 4, iclass 25, count 0 2006.203.08:05:59.88#ibcon#about to read 5, iclass 25, count 0 2006.203.08:05:59.88#ibcon#read 5, iclass 25, count 0 2006.203.08:05:59.88#ibcon#about to read 6, iclass 25, count 0 2006.203.08:05:59.88#ibcon#read 6, iclass 25, count 0 2006.203.08:05:59.88#ibcon#end of sib2, iclass 25, count 0 2006.203.08:05:59.88#ibcon#*after write, iclass 25, count 0 2006.203.08:05:59.88#ibcon#*before return 0, iclass 25, count 0 2006.203.08:05:59.88#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.203.08:05:59.88#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.203.08:05:59.88#ibcon#about to clear, iclass 25 cls_cnt 0 2006.203.08:05:59.88#ibcon#cleared, iclass 25 cls_cnt 0 2006.203.08:05:59.88$vc4f8/va=4,7 2006.203.08:05:59.88#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.203.08:05:59.88#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.203.08:05:59.88#ibcon#ireg 11 cls_cnt 2 2006.203.08:05:59.88#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.203.08:05:59.94#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.203.08:05:59.94#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.203.08:05:59.94#ibcon#enter wrdev, iclass 27, count 2 2006.203.08:05:59.94#ibcon#first serial, iclass 27, count 2 2006.203.08:05:59.94#ibcon#enter sib2, iclass 27, count 2 2006.203.08:05:59.94#ibcon#flushed, iclass 27, count 2 2006.203.08:05:59.94#ibcon#about to write, iclass 27, count 2 2006.203.08:05:59.94#ibcon#wrote, iclass 27, count 2 2006.203.08:05:59.94#ibcon#about to read 3, iclass 27, count 2 2006.203.08:05:59.96#ibcon#read 3, iclass 27, count 2 2006.203.08:05:59.96#ibcon#about to read 4, iclass 27, count 2 2006.203.08:05:59.96#ibcon#read 4, iclass 27, count 2 2006.203.08:05:59.96#ibcon#about to read 5, iclass 27, count 2 2006.203.08:05:59.96#ibcon#read 5, iclass 27, count 2 2006.203.08:05:59.96#ibcon#about to read 6, iclass 27, count 2 2006.203.08:05:59.96#ibcon#read 6, iclass 27, count 2 2006.203.08:05:59.96#ibcon#end of sib2, iclass 27, count 2 2006.203.08:05:59.96#ibcon#*mode == 0, iclass 27, count 2 2006.203.08:05:59.96#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.203.08:05:59.96#ibcon#[25=AT04-07\r\n] 2006.203.08:05:59.96#ibcon#*before write, iclass 27, count 2 2006.203.08:05:59.96#ibcon#enter sib2, iclass 27, count 2 2006.203.08:05:59.96#ibcon#flushed, iclass 27, count 2 2006.203.08:05:59.96#ibcon#about to write, iclass 27, count 2 2006.203.08:05:59.96#ibcon#wrote, iclass 27, count 2 2006.203.08:05:59.96#ibcon#about to read 3, iclass 27, count 2 2006.203.08:05:59.99#ibcon#read 3, iclass 27, count 2 2006.203.08:05:59.99#ibcon#about to read 4, iclass 27, count 2 2006.203.08:05:59.99#ibcon#read 4, iclass 27, count 2 2006.203.08:05:59.99#ibcon#about to read 5, iclass 27, count 2 2006.203.08:05:59.99#ibcon#read 5, iclass 27, count 2 2006.203.08:05:59.99#ibcon#about to read 6, iclass 27, count 2 2006.203.08:05:59.99#ibcon#read 6, iclass 27, count 2 2006.203.08:05:59.99#ibcon#end of sib2, iclass 27, count 2 2006.203.08:05:59.99#ibcon#*after write, iclass 27, count 2 2006.203.08:05:59.99#ibcon#*before return 0, iclass 27, count 2 2006.203.08:05:59.99#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.203.08:05:59.99#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.203.08:05:59.99#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.203.08:05:59.99#ibcon#ireg 7 cls_cnt 0 2006.203.08:05:59.99#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.203.08:06:00.11#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.203.08:06:00.11#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.203.08:06:00.11#ibcon#enter wrdev, iclass 27, count 0 2006.203.08:06:00.11#ibcon#first serial, iclass 27, count 0 2006.203.08:06:00.11#ibcon#enter sib2, iclass 27, count 0 2006.203.08:06:00.11#ibcon#flushed, iclass 27, count 0 2006.203.08:06:00.11#ibcon#about to write, iclass 27, count 0 2006.203.08:06:00.11#ibcon#wrote, iclass 27, count 0 2006.203.08:06:00.11#ibcon#about to read 3, iclass 27, count 0 2006.203.08:06:00.13#ibcon#read 3, iclass 27, count 0 2006.203.08:06:00.13#ibcon#about to read 4, iclass 27, count 0 2006.203.08:06:00.13#ibcon#read 4, iclass 27, count 0 2006.203.08:06:00.13#ibcon#about to read 5, iclass 27, count 0 2006.203.08:06:00.13#ibcon#read 5, iclass 27, count 0 2006.203.08:06:00.13#ibcon#about to read 6, iclass 27, count 0 2006.203.08:06:00.13#ibcon#read 6, iclass 27, count 0 2006.203.08:06:00.13#ibcon#end of sib2, iclass 27, count 0 2006.203.08:06:00.13#ibcon#*mode == 0, iclass 27, count 0 2006.203.08:06:00.13#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.203.08:06:00.13#ibcon#[25=USB\r\n] 2006.203.08:06:00.13#ibcon#*before write, iclass 27, count 0 2006.203.08:06:00.13#ibcon#enter sib2, iclass 27, count 0 2006.203.08:06:00.13#ibcon#flushed, iclass 27, count 0 2006.203.08:06:00.13#ibcon#about to write, iclass 27, count 0 2006.203.08:06:00.13#ibcon#wrote, iclass 27, count 0 2006.203.08:06:00.13#ibcon#about to read 3, iclass 27, count 0 2006.203.08:06:00.16#ibcon#read 3, iclass 27, count 0 2006.203.08:06:00.16#ibcon#about to read 4, iclass 27, count 0 2006.203.08:06:00.16#ibcon#read 4, iclass 27, count 0 2006.203.08:06:00.16#ibcon#about to read 5, iclass 27, count 0 2006.203.08:06:00.16#ibcon#read 5, iclass 27, count 0 2006.203.08:06:00.16#ibcon#about to read 6, iclass 27, count 0 2006.203.08:06:00.16#ibcon#read 6, iclass 27, count 0 2006.203.08:06:00.16#ibcon#end of sib2, iclass 27, count 0 2006.203.08:06:00.16#ibcon#*after write, iclass 27, count 0 2006.203.08:06:00.16#ibcon#*before return 0, iclass 27, count 0 2006.203.08:06:00.16#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.203.08:06:00.16#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.203.08:06:00.16#ibcon#about to clear, iclass 27 cls_cnt 0 2006.203.08:06:00.16#ibcon#cleared, iclass 27 cls_cnt 0 2006.203.08:06:00.16$vc4f8/valo=5,652.99 2006.203.08:06:00.16#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.203.08:06:00.16#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.203.08:06:00.16#ibcon#ireg 17 cls_cnt 0 2006.203.08:06:00.16#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.203.08:06:00.16#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.203.08:06:00.16#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.203.08:06:00.16#ibcon#enter wrdev, iclass 29, count 0 2006.203.08:06:00.16#ibcon#first serial, iclass 29, count 0 2006.203.08:06:00.16#ibcon#enter sib2, iclass 29, count 0 2006.203.08:06:00.16#ibcon#flushed, iclass 29, count 0 2006.203.08:06:00.16#ibcon#about to write, iclass 29, count 0 2006.203.08:06:00.16#ibcon#wrote, iclass 29, count 0 2006.203.08:06:00.16#ibcon#about to read 3, iclass 29, count 0 2006.203.08:06:00.18#ibcon#read 3, iclass 29, count 0 2006.203.08:06:00.18#ibcon#about to read 4, iclass 29, count 0 2006.203.08:06:00.18#ibcon#read 4, iclass 29, count 0 2006.203.08:06:00.18#ibcon#about to read 5, iclass 29, count 0 2006.203.08:06:00.18#ibcon#read 5, iclass 29, count 0 2006.203.08:06:00.18#ibcon#about to read 6, iclass 29, count 0 2006.203.08:06:00.18#ibcon#read 6, iclass 29, count 0 2006.203.08:06:00.18#ibcon#end of sib2, iclass 29, count 0 2006.203.08:06:00.18#ibcon#*mode == 0, iclass 29, count 0 2006.203.08:06:00.18#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.203.08:06:00.18#ibcon#[26=FRQ=05,652.99\r\n] 2006.203.08:06:00.18#ibcon#*before write, iclass 29, count 0 2006.203.08:06:00.18#ibcon#enter sib2, iclass 29, count 0 2006.203.08:06:00.18#ibcon#flushed, iclass 29, count 0 2006.203.08:06:00.18#ibcon#about to write, iclass 29, count 0 2006.203.08:06:00.18#ibcon#wrote, iclass 29, count 0 2006.203.08:06:00.18#ibcon#about to read 3, iclass 29, count 0 2006.203.08:06:00.22#ibcon#read 3, iclass 29, count 0 2006.203.08:06:00.22#ibcon#about to read 4, iclass 29, count 0 2006.203.08:06:00.22#ibcon#read 4, iclass 29, count 0 2006.203.08:06:00.22#ibcon#about to read 5, iclass 29, count 0 2006.203.08:06:00.22#ibcon#read 5, iclass 29, count 0 2006.203.08:06:00.22#ibcon#about to read 6, iclass 29, count 0 2006.203.08:06:00.22#ibcon#read 6, iclass 29, count 0 2006.203.08:06:00.22#ibcon#end of sib2, iclass 29, count 0 2006.203.08:06:00.22#ibcon#*after write, iclass 29, count 0 2006.203.08:06:00.22#ibcon#*before return 0, iclass 29, count 0 2006.203.08:06:00.22#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.203.08:06:00.22#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.203.08:06:00.22#ibcon#about to clear, iclass 29 cls_cnt 0 2006.203.08:06:00.22#ibcon#cleared, iclass 29 cls_cnt 0 2006.203.08:06:00.22$vc4f8/va=5,7 2006.203.08:06:00.22#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.203.08:06:00.22#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.203.08:06:00.22#ibcon#ireg 11 cls_cnt 2 2006.203.08:06:00.22#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.203.08:06:00.28#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.203.08:06:00.28#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.203.08:06:00.28#ibcon#enter wrdev, iclass 31, count 2 2006.203.08:06:00.28#ibcon#first serial, iclass 31, count 2 2006.203.08:06:00.28#ibcon#enter sib2, iclass 31, count 2 2006.203.08:06:00.28#ibcon#flushed, iclass 31, count 2 2006.203.08:06:00.28#ibcon#about to write, iclass 31, count 2 2006.203.08:06:00.28#ibcon#wrote, iclass 31, count 2 2006.203.08:06:00.28#ibcon#about to read 3, iclass 31, count 2 2006.203.08:06:00.30#ibcon#read 3, iclass 31, count 2 2006.203.08:06:00.30#ibcon#about to read 4, iclass 31, count 2 2006.203.08:06:00.30#ibcon#read 4, iclass 31, count 2 2006.203.08:06:00.30#ibcon#about to read 5, iclass 31, count 2 2006.203.08:06:00.30#ibcon#read 5, iclass 31, count 2 2006.203.08:06:00.30#ibcon#about to read 6, iclass 31, count 2 2006.203.08:06:00.30#ibcon#read 6, iclass 31, count 2 2006.203.08:06:00.30#ibcon#end of sib2, iclass 31, count 2 2006.203.08:06:00.30#ibcon#*mode == 0, iclass 31, count 2 2006.203.08:06:00.30#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.203.08:06:00.30#ibcon#[25=AT05-07\r\n] 2006.203.08:06:00.30#ibcon#*before write, iclass 31, count 2 2006.203.08:06:00.30#ibcon#enter sib2, iclass 31, count 2 2006.203.08:06:00.30#ibcon#flushed, iclass 31, count 2 2006.203.08:06:00.30#ibcon#about to write, iclass 31, count 2 2006.203.08:06:00.30#ibcon#wrote, iclass 31, count 2 2006.203.08:06:00.30#ibcon#about to read 3, iclass 31, count 2 2006.203.08:06:00.33#ibcon#read 3, iclass 31, count 2 2006.203.08:06:00.33#ibcon#about to read 4, iclass 31, count 2 2006.203.08:06:00.33#ibcon#read 4, iclass 31, count 2 2006.203.08:06:00.33#ibcon#about to read 5, iclass 31, count 2 2006.203.08:06:00.33#ibcon#read 5, iclass 31, count 2 2006.203.08:06:00.33#ibcon#about to read 6, iclass 31, count 2 2006.203.08:06:00.33#ibcon#read 6, iclass 31, count 2 2006.203.08:06:00.33#ibcon#end of sib2, iclass 31, count 2 2006.203.08:06:00.33#ibcon#*after write, iclass 31, count 2 2006.203.08:06:00.33#ibcon#*before return 0, iclass 31, count 2 2006.203.08:06:00.33#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.203.08:06:00.33#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.203.08:06:00.33#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.203.08:06:00.33#ibcon#ireg 7 cls_cnt 0 2006.203.08:06:00.33#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.203.08:06:00.45#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.203.08:06:00.45#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.203.08:06:00.45#ibcon#enter wrdev, iclass 31, count 0 2006.203.08:06:00.45#ibcon#first serial, iclass 31, count 0 2006.203.08:06:00.45#ibcon#enter sib2, iclass 31, count 0 2006.203.08:06:00.45#ibcon#flushed, iclass 31, count 0 2006.203.08:06:00.45#ibcon#about to write, iclass 31, count 0 2006.203.08:06:00.45#ibcon#wrote, iclass 31, count 0 2006.203.08:06:00.45#ibcon#about to read 3, iclass 31, count 0 2006.203.08:06:00.47#ibcon#read 3, iclass 31, count 0 2006.203.08:06:00.47#ibcon#about to read 4, iclass 31, count 0 2006.203.08:06:00.47#ibcon#read 4, iclass 31, count 0 2006.203.08:06:00.47#ibcon#about to read 5, iclass 31, count 0 2006.203.08:06:00.47#ibcon#read 5, iclass 31, count 0 2006.203.08:06:00.47#ibcon#about to read 6, iclass 31, count 0 2006.203.08:06:00.47#ibcon#read 6, iclass 31, count 0 2006.203.08:06:00.47#ibcon#end of sib2, iclass 31, count 0 2006.203.08:06:00.47#ibcon#*mode == 0, iclass 31, count 0 2006.203.08:06:00.47#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.203.08:06:00.47#ibcon#[25=USB\r\n] 2006.203.08:06:00.47#ibcon#*before write, iclass 31, count 0 2006.203.08:06:00.47#ibcon#enter sib2, iclass 31, count 0 2006.203.08:06:00.47#ibcon#flushed, iclass 31, count 0 2006.203.08:06:00.47#ibcon#about to write, iclass 31, count 0 2006.203.08:06:00.47#ibcon#wrote, iclass 31, count 0 2006.203.08:06:00.47#ibcon#about to read 3, iclass 31, count 0 2006.203.08:06:00.50#ibcon#read 3, iclass 31, count 0 2006.203.08:06:00.50#ibcon#about to read 4, iclass 31, count 0 2006.203.08:06:00.50#ibcon#read 4, iclass 31, count 0 2006.203.08:06:00.50#ibcon#about to read 5, iclass 31, count 0 2006.203.08:06:00.50#ibcon#read 5, iclass 31, count 0 2006.203.08:06:00.50#ibcon#about to read 6, iclass 31, count 0 2006.203.08:06:00.50#ibcon#read 6, iclass 31, count 0 2006.203.08:06:00.50#ibcon#end of sib2, iclass 31, count 0 2006.203.08:06:00.50#ibcon#*after write, iclass 31, count 0 2006.203.08:06:00.50#ibcon#*before return 0, iclass 31, count 0 2006.203.08:06:00.50#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.203.08:06:00.50#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.203.08:06:00.50#ibcon#about to clear, iclass 31 cls_cnt 0 2006.203.08:06:00.50#ibcon#cleared, iclass 31 cls_cnt 0 2006.203.08:06:00.50$vc4f8/valo=6,772.99 2006.203.08:06:00.50#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.203.08:06:00.50#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.203.08:06:00.50#ibcon#ireg 17 cls_cnt 0 2006.203.08:06:00.50#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.203.08:06:00.50#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.203.08:06:00.50#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.203.08:06:00.50#ibcon#enter wrdev, iclass 33, count 0 2006.203.08:06:00.50#ibcon#first serial, iclass 33, count 0 2006.203.08:06:00.50#ibcon#enter sib2, iclass 33, count 0 2006.203.08:06:00.50#ibcon#flushed, iclass 33, count 0 2006.203.08:06:00.50#ibcon#about to write, iclass 33, count 0 2006.203.08:06:00.50#ibcon#wrote, iclass 33, count 0 2006.203.08:06:00.50#ibcon#about to read 3, iclass 33, count 0 2006.203.08:06:00.52#ibcon#read 3, iclass 33, count 0 2006.203.08:06:00.52#ibcon#about to read 4, iclass 33, count 0 2006.203.08:06:00.52#ibcon#read 4, iclass 33, count 0 2006.203.08:06:00.52#ibcon#about to read 5, iclass 33, count 0 2006.203.08:06:00.52#ibcon#read 5, iclass 33, count 0 2006.203.08:06:00.52#ibcon#about to read 6, iclass 33, count 0 2006.203.08:06:00.52#ibcon#read 6, iclass 33, count 0 2006.203.08:06:00.52#ibcon#end of sib2, iclass 33, count 0 2006.203.08:06:00.52#ibcon#*mode == 0, iclass 33, count 0 2006.203.08:06:00.52#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.203.08:06:00.52#ibcon#[26=FRQ=06,772.99\r\n] 2006.203.08:06:00.52#ibcon#*before write, iclass 33, count 0 2006.203.08:06:00.52#ibcon#enter sib2, iclass 33, count 0 2006.203.08:06:00.52#ibcon#flushed, iclass 33, count 0 2006.203.08:06:00.52#ibcon#about to write, iclass 33, count 0 2006.203.08:06:00.52#ibcon#wrote, iclass 33, count 0 2006.203.08:06:00.52#ibcon#about to read 3, iclass 33, count 0 2006.203.08:06:00.56#ibcon#read 3, iclass 33, count 0 2006.203.08:06:00.56#ibcon#about to read 4, iclass 33, count 0 2006.203.08:06:00.56#ibcon#read 4, iclass 33, count 0 2006.203.08:06:00.56#ibcon#about to read 5, iclass 33, count 0 2006.203.08:06:00.56#ibcon#read 5, iclass 33, count 0 2006.203.08:06:00.56#ibcon#about to read 6, iclass 33, count 0 2006.203.08:06:00.56#ibcon#read 6, iclass 33, count 0 2006.203.08:06:00.56#ibcon#end of sib2, iclass 33, count 0 2006.203.08:06:00.56#ibcon#*after write, iclass 33, count 0 2006.203.08:06:00.56#ibcon#*before return 0, iclass 33, count 0 2006.203.08:06:00.56#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.203.08:06:00.56#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.203.08:06:00.56#ibcon#about to clear, iclass 33 cls_cnt 0 2006.203.08:06:00.56#ibcon#cleared, iclass 33 cls_cnt 0 2006.203.08:06:00.56$vc4f8/va=6,6 2006.203.08:06:00.56#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.203.08:06:00.56#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.203.08:06:00.56#ibcon#ireg 11 cls_cnt 2 2006.203.08:06:00.56#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.203.08:06:00.62#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.203.08:06:00.62#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.203.08:06:00.62#ibcon#enter wrdev, iclass 35, count 2 2006.203.08:06:00.62#ibcon#first serial, iclass 35, count 2 2006.203.08:06:00.62#ibcon#enter sib2, iclass 35, count 2 2006.203.08:06:00.62#ibcon#flushed, iclass 35, count 2 2006.203.08:06:00.62#ibcon#about to write, iclass 35, count 2 2006.203.08:06:00.62#ibcon#wrote, iclass 35, count 2 2006.203.08:06:00.62#ibcon#about to read 3, iclass 35, count 2 2006.203.08:06:00.64#ibcon#read 3, iclass 35, count 2 2006.203.08:06:00.64#ibcon#about to read 4, iclass 35, count 2 2006.203.08:06:00.64#ibcon#read 4, iclass 35, count 2 2006.203.08:06:00.64#ibcon#about to read 5, iclass 35, count 2 2006.203.08:06:00.64#ibcon#read 5, iclass 35, count 2 2006.203.08:06:00.64#ibcon#about to read 6, iclass 35, count 2 2006.203.08:06:00.64#ibcon#read 6, iclass 35, count 2 2006.203.08:06:00.64#ibcon#end of sib2, iclass 35, count 2 2006.203.08:06:00.64#ibcon#*mode == 0, iclass 35, count 2 2006.203.08:06:00.64#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.203.08:06:00.64#ibcon#[25=AT06-06\r\n] 2006.203.08:06:00.64#ibcon#*before write, iclass 35, count 2 2006.203.08:06:00.64#ibcon#enter sib2, iclass 35, count 2 2006.203.08:06:00.64#ibcon#flushed, iclass 35, count 2 2006.203.08:06:00.64#ibcon#about to write, iclass 35, count 2 2006.203.08:06:00.64#ibcon#wrote, iclass 35, count 2 2006.203.08:06:00.64#ibcon#about to read 3, iclass 35, count 2 2006.203.08:06:00.67#ibcon#read 3, iclass 35, count 2 2006.203.08:06:00.67#ibcon#about to read 4, iclass 35, count 2 2006.203.08:06:00.67#ibcon#read 4, iclass 35, count 2 2006.203.08:06:00.67#ibcon#about to read 5, iclass 35, count 2 2006.203.08:06:00.67#ibcon#read 5, iclass 35, count 2 2006.203.08:06:00.67#ibcon#about to read 6, iclass 35, count 2 2006.203.08:06:00.67#ibcon#read 6, iclass 35, count 2 2006.203.08:06:00.67#ibcon#end of sib2, iclass 35, count 2 2006.203.08:06:00.67#ibcon#*after write, iclass 35, count 2 2006.203.08:06:00.67#ibcon#*before return 0, iclass 35, count 2 2006.203.08:06:00.67#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.203.08:06:00.67#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.203.08:06:00.67#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.203.08:06:00.67#ibcon#ireg 7 cls_cnt 0 2006.203.08:06:00.67#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.203.08:06:00.79#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.203.08:06:00.79#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.203.08:06:00.79#ibcon#enter wrdev, iclass 35, count 0 2006.203.08:06:00.79#ibcon#first serial, iclass 35, count 0 2006.203.08:06:00.79#ibcon#enter sib2, iclass 35, count 0 2006.203.08:06:00.79#ibcon#flushed, iclass 35, count 0 2006.203.08:06:00.79#ibcon#about to write, iclass 35, count 0 2006.203.08:06:00.79#ibcon#wrote, iclass 35, count 0 2006.203.08:06:00.79#ibcon#about to read 3, iclass 35, count 0 2006.203.08:06:00.81#ibcon#read 3, iclass 35, count 0 2006.203.08:06:00.81#ibcon#about to read 4, iclass 35, count 0 2006.203.08:06:00.81#ibcon#read 4, iclass 35, count 0 2006.203.08:06:00.81#ibcon#about to read 5, iclass 35, count 0 2006.203.08:06:00.81#ibcon#read 5, iclass 35, count 0 2006.203.08:06:00.81#ibcon#about to read 6, iclass 35, count 0 2006.203.08:06:00.81#ibcon#read 6, iclass 35, count 0 2006.203.08:06:00.81#ibcon#end of sib2, iclass 35, count 0 2006.203.08:06:00.81#ibcon#*mode == 0, iclass 35, count 0 2006.203.08:06:00.81#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.203.08:06:00.81#ibcon#[25=USB\r\n] 2006.203.08:06:00.81#ibcon#*before write, iclass 35, count 0 2006.203.08:06:00.81#ibcon#enter sib2, iclass 35, count 0 2006.203.08:06:00.81#ibcon#flushed, iclass 35, count 0 2006.203.08:06:00.81#ibcon#about to write, iclass 35, count 0 2006.203.08:06:00.81#ibcon#wrote, iclass 35, count 0 2006.203.08:06:00.81#ibcon#about to read 3, iclass 35, count 0 2006.203.08:06:00.84#ibcon#read 3, iclass 35, count 0 2006.203.08:06:00.84#ibcon#about to read 4, iclass 35, count 0 2006.203.08:06:00.84#ibcon#read 4, iclass 35, count 0 2006.203.08:06:00.84#ibcon#about to read 5, iclass 35, count 0 2006.203.08:06:00.84#ibcon#read 5, iclass 35, count 0 2006.203.08:06:00.84#ibcon#about to read 6, iclass 35, count 0 2006.203.08:06:00.84#ibcon#read 6, iclass 35, count 0 2006.203.08:06:00.84#ibcon#end of sib2, iclass 35, count 0 2006.203.08:06:00.84#ibcon#*after write, iclass 35, count 0 2006.203.08:06:00.84#ibcon#*before return 0, iclass 35, count 0 2006.203.08:06:00.84#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.203.08:06:00.84#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.203.08:06:00.84#ibcon#about to clear, iclass 35 cls_cnt 0 2006.203.08:06:00.84#ibcon#cleared, iclass 35 cls_cnt 0 2006.203.08:06:00.84$vc4f8/valo=7,832.99 2006.203.08:06:00.84#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.203.08:06:00.84#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.203.08:06:00.84#ibcon#ireg 17 cls_cnt 0 2006.203.08:06:00.84#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.203.08:06:00.84#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.203.08:06:00.84#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.203.08:06:00.84#ibcon#enter wrdev, iclass 37, count 0 2006.203.08:06:00.84#ibcon#first serial, iclass 37, count 0 2006.203.08:06:00.84#ibcon#enter sib2, iclass 37, count 0 2006.203.08:06:00.84#ibcon#flushed, iclass 37, count 0 2006.203.08:06:00.84#ibcon#about to write, iclass 37, count 0 2006.203.08:06:00.84#ibcon#wrote, iclass 37, count 0 2006.203.08:06:00.84#ibcon#about to read 3, iclass 37, count 0 2006.203.08:06:00.86#ibcon#read 3, iclass 37, count 0 2006.203.08:06:00.86#ibcon#about to read 4, iclass 37, count 0 2006.203.08:06:00.86#ibcon#read 4, iclass 37, count 0 2006.203.08:06:00.86#ibcon#about to read 5, iclass 37, count 0 2006.203.08:06:00.86#ibcon#read 5, iclass 37, count 0 2006.203.08:06:00.86#ibcon#about to read 6, iclass 37, count 0 2006.203.08:06:00.86#ibcon#read 6, iclass 37, count 0 2006.203.08:06:00.86#ibcon#end of sib2, iclass 37, count 0 2006.203.08:06:00.86#ibcon#*mode == 0, iclass 37, count 0 2006.203.08:06:00.86#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.203.08:06:00.86#ibcon#[26=FRQ=07,832.99\r\n] 2006.203.08:06:00.86#ibcon#*before write, iclass 37, count 0 2006.203.08:06:00.86#ibcon#enter sib2, iclass 37, count 0 2006.203.08:06:00.86#ibcon#flushed, iclass 37, count 0 2006.203.08:06:00.86#ibcon#about to write, iclass 37, count 0 2006.203.08:06:00.86#ibcon#wrote, iclass 37, count 0 2006.203.08:06:00.86#ibcon#about to read 3, iclass 37, count 0 2006.203.08:06:00.90#ibcon#read 3, iclass 37, count 0 2006.203.08:06:00.90#ibcon#about to read 4, iclass 37, count 0 2006.203.08:06:00.90#ibcon#read 4, iclass 37, count 0 2006.203.08:06:00.90#ibcon#about to read 5, iclass 37, count 0 2006.203.08:06:00.90#ibcon#read 5, iclass 37, count 0 2006.203.08:06:00.90#ibcon#about to read 6, iclass 37, count 0 2006.203.08:06:00.90#ibcon#read 6, iclass 37, count 0 2006.203.08:06:00.90#ibcon#end of sib2, iclass 37, count 0 2006.203.08:06:00.90#ibcon#*after write, iclass 37, count 0 2006.203.08:06:00.90#ibcon#*before return 0, iclass 37, count 0 2006.203.08:06:00.90#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.203.08:06:00.90#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.203.08:06:00.90#ibcon#about to clear, iclass 37 cls_cnt 0 2006.203.08:06:00.90#ibcon#cleared, iclass 37 cls_cnt 0 2006.203.08:06:00.90$vc4f8/va=7,7 2006.203.08:06:00.90#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.203.08:06:00.90#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.203.08:06:00.90#ibcon#ireg 11 cls_cnt 2 2006.203.08:06:00.90#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.203.08:06:00.96#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.203.08:06:00.96#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.203.08:06:00.96#ibcon#enter wrdev, iclass 39, count 2 2006.203.08:06:00.96#ibcon#first serial, iclass 39, count 2 2006.203.08:06:00.96#ibcon#enter sib2, iclass 39, count 2 2006.203.08:06:00.96#ibcon#flushed, iclass 39, count 2 2006.203.08:06:00.96#ibcon#about to write, iclass 39, count 2 2006.203.08:06:00.96#ibcon#wrote, iclass 39, count 2 2006.203.08:06:00.96#ibcon#about to read 3, iclass 39, count 2 2006.203.08:06:00.98#ibcon#read 3, iclass 39, count 2 2006.203.08:06:00.98#ibcon#about to read 4, iclass 39, count 2 2006.203.08:06:00.98#ibcon#read 4, iclass 39, count 2 2006.203.08:06:00.98#ibcon#about to read 5, iclass 39, count 2 2006.203.08:06:00.98#ibcon#read 5, iclass 39, count 2 2006.203.08:06:00.98#ibcon#about to read 6, iclass 39, count 2 2006.203.08:06:00.98#ibcon#read 6, iclass 39, count 2 2006.203.08:06:00.98#ibcon#end of sib2, iclass 39, count 2 2006.203.08:06:00.98#ibcon#*mode == 0, iclass 39, count 2 2006.203.08:06:00.98#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.203.08:06:00.98#ibcon#[25=AT07-07\r\n] 2006.203.08:06:00.98#ibcon#*before write, iclass 39, count 2 2006.203.08:06:00.98#ibcon#enter sib2, iclass 39, count 2 2006.203.08:06:00.98#ibcon#flushed, iclass 39, count 2 2006.203.08:06:00.98#ibcon#about to write, iclass 39, count 2 2006.203.08:06:00.98#ibcon#wrote, iclass 39, count 2 2006.203.08:06:00.98#ibcon#about to read 3, iclass 39, count 2 2006.203.08:06:01.01#ibcon#read 3, iclass 39, count 2 2006.203.08:06:01.01#ibcon#about to read 4, iclass 39, count 2 2006.203.08:06:01.01#ibcon#read 4, iclass 39, count 2 2006.203.08:06:01.01#ibcon#about to read 5, iclass 39, count 2 2006.203.08:06:01.01#ibcon#read 5, iclass 39, count 2 2006.203.08:06:01.01#ibcon#about to read 6, iclass 39, count 2 2006.203.08:06:01.01#ibcon#read 6, iclass 39, count 2 2006.203.08:06:01.01#ibcon#end of sib2, iclass 39, count 2 2006.203.08:06:01.01#ibcon#*after write, iclass 39, count 2 2006.203.08:06:01.01#ibcon#*before return 0, iclass 39, count 2 2006.203.08:06:01.01#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.203.08:06:01.01#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.203.08:06:01.01#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.203.08:06:01.01#ibcon#ireg 7 cls_cnt 0 2006.203.08:06:01.01#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.203.08:06:01.13#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.203.08:06:01.13#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.203.08:06:01.13#ibcon#enter wrdev, iclass 39, count 0 2006.203.08:06:01.13#ibcon#first serial, iclass 39, count 0 2006.203.08:06:01.13#ibcon#enter sib2, iclass 39, count 0 2006.203.08:06:01.13#ibcon#flushed, iclass 39, count 0 2006.203.08:06:01.13#ibcon#about to write, iclass 39, count 0 2006.203.08:06:01.13#ibcon#wrote, iclass 39, count 0 2006.203.08:06:01.13#ibcon#about to read 3, iclass 39, count 0 2006.203.08:06:01.15#ibcon#read 3, iclass 39, count 0 2006.203.08:06:01.15#ibcon#about to read 4, iclass 39, count 0 2006.203.08:06:01.15#ibcon#read 4, iclass 39, count 0 2006.203.08:06:01.15#ibcon#about to read 5, iclass 39, count 0 2006.203.08:06:01.15#ibcon#read 5, iclass 39, count 0 2006.203.08:06:01.15#ibcon#about to read 6, iclass 39, count 0 2006.203.08:06:01.15#ibcon#read 6, iclass 39, count 0 2006.203.08:06:01.15#ibcon#end of sib2, iclass 39, count 0 2006.203.08:06:01.15#ibcon#*mode == 0, iclass 39, count 0 2006.203.08:06:01.15#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.203.08:06:01.15#ibcon#[25=USB\r\n] 2006.203.08:06:01.15#ibcon#*before write, iclass 39, count 0 2006.203.08:06:01.15#ibcon#enter sib2, iclass 39, count 0 2006.203.08:06:01.15#ibcon#flushed, iclass 39, count 0 2006.203.08:06:01.15#ibcon#about to write, iclass 39, count 0 2006.203.08:06:01.15#ibcon#wrote, iclass 39, count 0 2006.203.08:06:01.15#ibcon#about to read 3, iclass 39, count 0 2006.203.08:06:01.18#ibcon#read 3, iclass 39, count 0 2006.203.08:06:01.18#ibcon#about to read 4, iclass 39, count 0 2006.203.08:06:01.18#ibcon#read 4, iclass 39, count 0 2006.203.08:06:01.18#ibcon#about to read 5, iclass 39, count 0 2006.203.08:06:01.18#ibcon#read 5, iclass 39, count 0 2006.203.08:06:01.18#ibcon#about to read 6, iclass 39, count 0 2006.203.08:06:01.18#ibcon#read 6, iclass 39, count 0 2006.203.08:06:01.18#ibcon#end of sib2, iclass 39, count 0 2006.203.08:06:01.18#ibcon#*after write, iclass 39, count 0 2006.203.08:06:01.18#ibcon#*before return 0, iclass 39, count 0 2006.203.08:06:01.18#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.203.08:06:01.18#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.203.08:06:01.18#ibcon#about to clear, iclass 39 cls_cnt 0 2006.203.08:06:01.18#ibcon#cleared, iclass 39 cls_cnt 0 2006.203.08:06:01.18$vc4f8/valo=8,852.99 2006.203.08:06:01.18#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.203.08:06:01.18#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.203.08:06:01.18#ibcon#ireg 17 cls_cnt 0 2006.203.08:06:01.18#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.203.08:06:01.18#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.203.08:06:01.18#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.203.08:06:01.18#ibcon#enter wrdev, iclass 3, count 0 2006.203.08:06:01.18#ibcon#first serial, iclass 3, count 0 2006.203.08:06:01.18#ibcon#enter sib2, iclass 3, count 0 2006.203.08:06:01.18#ibcon#flushed, iclass 3, count 0 2006.203.08:06:01.18#ibcon#about to write, iclass 3, count 0 2006.203.08:06:01.18#ibcon#wrote, iclass 3, count 0 2006.203.08:06:01.18#ibcon#about to read 3, iclass 3, count 0 2006.203.08:06:01.20#ibcon#read 3, iclass 3, count 0 2006.203.08:06:01.20#ibcon#about to read 4, iclass 3, count 0 2006.203.08:06:01.20#ibcon#read 4, iclass 3, count 0 2006.203.08:06:01.20#ibcon#about to read 5, iclass 3, count 0 2006.203.08:06:01.20#ibcon#read 5, iclass 3, count 0 2006.203.08:06:01.20#ibcon#about to read 6, iclass 3, count 0 2006.203.08:06:01.20#ibcon#read 6, iclass 3, count 0 2006.203.08:06:01.20#ibcon#end of sib2, iclass 3, count 0 2006.203.08:06:01.20#ibcon#*mode == 0, iclass 3, count 0 2006.203.08:06:01.20#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.203.08:06:01.20#ibcon#[26=FRQ=08,852.99\r\n] 2006.203.08:06:01.20#ibcon#*before write, iclass 3, count 0 2006.203.08:06:01.20#ibcon#enter sib2, iclass 3, count 0 2006.203.08:06:01.20#ibcon#flushed, iclass 3, count 0 2006.203.08:06:01.20#ibcon#about to write, iclass 3, count 0 2006.203.08:06:01.20#ibcon#wrote, iclass 3, count 0 2006.203.08:06:01.20#ibcon#about to read 3, iclass 3, count 0 2006.203.08:06:01.24#ibcon#read 3, iclass 3, count 0 2006.203.08:06:01.24#ibcon#about to read 4, iclass 3, count 0 2006.203.08:06:01.24#ibcon#read 4, iclass 3, count 0 2006.203.08:06:01.24#ibcon#about to read 5, iclass 3, count 0 2006.203.08:06:01.24#ibcon#read 5, iclass 3, count 0 2006.203.08:06:01.24#ibcon#about to read 6, iclass 3, count 0 2006.203.08:06:01.24#ibcon#read 6, iclass 3, count 0 2006.203.08:06:01.24#ibcon#end of sib2, iclass 3, count 0 2006.203.08:06:01.24#ibcon#*after write, iclass 3, count 0 2006.203.08:06:01.24#ibcon#*before return 0, iclass 3, count 0 2006.203.08:06:01.24#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.203.08:06:01.24#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.203.08:06:01.24#ibcon#about to clear, iclass 3 cls_cnt 0 2006.203.08:06:01.24#ibcon#cleared, iclass 3 cls_cnt 0 2006.203.08:06:01.24$vc4f8/va=8,6 2006.203.08:06:01.24#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.203.08:06:01.24#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.203.08:06:01.24#ibcon#ireg 11 cls_cnt 2 2006.203.08:06:01.24#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.203.08:06:01.30#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.203.08:06:01.30#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.203.08:06:01.30#ibcon#enter wrdev, iclass 5, count 2 2006.203.08:06:01.30#ibcon#first serial, iclass 5, count 2 2006.203.08:06:01.30#ibcon#enter sib2, iclass 5, count 2 2006.203.08:06:01.30#ibcon#flushed, iclass 5, count 2 2006.203.08:06:01.30#ibcon#about to write, iclass 5, count 2 2006.203.08:06:01.30#ibcon#wrote, iclass 5, count 2 2006.203.08:06:01.30#ibcon#about to read 3, iclass 5, count 2 2006.203.08:06:01.32#ibcon#read 3, iclass 5, count 2 2006.203.08:06:01.32#ibcon#about to read 4, iclass 5, count 2 2006.203.08:06:01.32#ibcon#read 4, iclass 5, count 2 2006.203.08:06:01.32#ibcon#about to read 5, iclass 5, count 2 2006.203.08:06:01.32#ibcon#read 5, iclass 5, count 2 2006.203.08:06:01.32#ibcon#about to read 6, iclass 5, count 2 2006.203.08:06:01.32#ibcon#read 6, iclass 5, count 2 2006.203.08:06:01.32#ibcon#end of sib2, iclass 5, count 2 2006.203.08:06:01.32#ibcon#*mode == 0, iclass 5, count 2 2006.203.08:06:01.32#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.203.08:06:01.32#ibcon#[25=AT08-06\r\n] 2006.203.08:06:01.32#ibcon#*before write, iclass 5, count 2 2006.203.08:06:01.32#ibcon#enter sib2, iclass 5, count 2 2006.203.08:06:01.32#ibcon#flushed, iclass 5, count 2 2006.203.08:06:01.32#ibcon#about to write, iclass 5, count 2 2006.203.08:06:01.32#ibcon#wrote, iclass 5, count 2 2006.203.08:06:01.32#ibcon#about to read 3, iclass 5, count 2 2006.203.08:06:01.35#ibcon#read 3, iclass 5, count 2 2006.203.08:06:01.35#ibcon#about to read 4, iclass 5, count 2 2006.203.08:06:01.35#ibcon#read 4, iclass 5, count 2 2006.203.08:06:01.35#ibcon#about to read 5, iclass 5, count 2 2006.203.08:06:01.35#ibcon#read 5, iclass 5, count 2 2006.203.08:06:01.35#ibcon#about to read 6, iclass 5, count 2 2006.203.08:06:01.35#ibcon#read 6, iclass 5, count 2 2006.203.08:06:01.35#ibcon#end of sib2, iclass 5, count 2 2006.203.08:06:01.35#ibcon#*after write, iclass 5, count 2 2006.203.08:06:01.35#ibcon#*before return 0, iclass 5, count 2 2006.203.08:06:01.35#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.203.08:06:01.35#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.203.08:06:01.35#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.203.08:06:01.35#ibcon#ireg 7 cls_cnt 0 2006.203.08:06:01.35#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.203.08:06:01.47#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.203.08:06:01.47#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.203.08:06:01.47#ibcon#enter wrdev, iclass 5, count 0 2006.203.08:06:01.47#ibcon#first serial, iclass 5, count 0 2006.203.08:06:01.47#ibcon#enter sib2, iclass 5, count 0 2006.203.08:06:01.47#ibcon#flushed, iclass 5, count 0 2006.203.08:06:01.47#ibcon#about to write, iclass 5, count 0 2006.203.08:06:01.47#ibcon#wrote, iclass 5, count 0 2006.203.08:06:01.47#ibcon#about to read 3, iclass 5, count 0 2006.203.08:06:01.49#ibcon#read 3, iclass 5, count 0 2006.203.08:06:01.49#ibcon#about to read 4, iclass 5, count 0 2006.203.08:06:01.49#ibcon#read 4, iclass 5, count 0 2006.203.08:06:01.49#ibcon#about to read 5, iclass 5, count 0 2006.203.08:06:01.49#ibcon#read 5, iclass 5, count 0 2006.203.08:06:01.49#ibcon#about to read 6, iclass 5, count 0 2006.203.08:06:01.49#ibcon#read 6, iclass 5, count 0 2006.203.08:06:01.49#ibcon#end of sib2, iclass 5, count 0 2006.203.08:06:01.49#ibcon#*mode == 0, iclass 5, count 0 2006.203.08:06:01.49#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.203.08:06:01.49#ibcon#[25=USB\r\n] 2006.203.08:06:01.49#ibcon#*before write, iclass 5, count 0 2006.203.08:06:01.49#ibcon#enter sib2, iclass 5, count 0 2006.203.08:06:01.49#ibcon#flushed, iclass 5, count 0 2006.203.08:06:01.49#ibcon#about to write, iclass 5, count 0 2006.203.08:06:01.49#ibcon#wrote, iclass 5, count 0 2006.203.08:06:01.49#ibcon#about to read 3, iclass 5, count 0 2006.203.08:06:01.52#ibcon#read 3, iclass 5, count 0 2006.203.08:06:01.52#ibcon#about to read 4, iclass 5, count 0 2006.203.08:06:01.52#ibcon#read 4, iclass 5, count 0 2006.203.08:06:01.52#ibcon#about to read 5, iclass 5, count 0 2006.203.08:06:01.52#ibcon#read 5, iclass 5, count 0 2006.203.08:06:01.52#ibcon#about to read 6, iclass 5, count 0 2006.203.08:06:01.52#ibcon#read 6, iclass 5, count 0 2006.203.08:06:01.52#ibcon#end of sib2, iclass 5, count 0 2006.203.08:06:01.52#ibcon#*after write, iclass 5, count 0 2006.203.08:06:01.52#ibcon#*before return 0, iclass 5, count 0 2006.203.08:06:01.52#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.203.08:06:01.52#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.203.08:06:01.52#ibcon#about to clear, iclass 5 cls_cnt 0 2006.203.08:06:01.52#ibcon#cleared, iclass 5 cls_cnt 0 2006.203.08:06:01.52$vc4f8/vblo=1,632.99 2006.203.08:06:01.52#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.203.08:06:01.52#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.203.08:06:01.52#ibcon#ireg 17 cls_cnt 0 2006.203.08:06:01.52#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.203.08:06:01.52#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.203.08:06:01.52#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.203.08:06:01.52#ibcon#enter wrdev, iclass 7, count 0 2006.203.08:06:01.52#ibcon#first serial, iclass 7, count 0 2006.203.08:06:01.52#ibcon#enter sib2, iclass 7, count 0 2006.203.08:06:01.52#ibcon#flushed, iclass 7, count 0 2006.203.08:06:01.52#ibcon#about to write, iclass 7, count 0 2006.203.08:06:01.52#ibcon#wrote, iclass 7, count 0 2006.203.08:06:01.52#ibcon#about to read 3, iclass 7, count 0 2006.203.08:06:01.54#ibcon#read 3, iclass 7, count 0 2006.203.08:06:01.54#ibcon#about to read 4, iclass 7, count 0 2006.203.08:06:01.54#ibcon#read 4, iclass 7, count 0 2006.203.08:06:01.54#ibcon#about to read 5, iclass 7, count 0 2006.203.08:06:01.54#ibcon#read 5, iclass 7, count 0 2006.203.08:06:01.54#ibcon#about to read 6, iclass 7, count 0 2006.203.08:06:01.54#ibcon#read 6, iclass 7, count 0 2006.203.08:06:01.54#ibcon#end of sib2, iclass 7, count 0 2006.203.08:06:01.54#ibcon#*mode == 0, iclass 7, count 0 2006.203.08:06:01.54#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.203.08:06:01.54#ibcon#[28=FRQ=01,632.99\r\n] 2006.203.08:06:01.54#ibcon#*before write, iclass 7, count 0 2006.203.08:06:01.54#ibcon#enter sib2, iclass 7, count 0 2006.203.08:06:01.54#ibcon#flushed, iclass 7, count 0 2006.203.08:06:01.54#ibcon#about to write, iclass 7, count 0 2006.203.08:06:01.54#ibcon#wrote, iclass 7, count 0 2006.203.08:06:01.54#ibcon#about to read 3, iclass 7, count 0 2006.203.08:06:01.58#ibcon#read 3, iclass 7, count 0 2006.203.08:06:01.58#ibcon#about to read 4, iclass 7, count 0 2006.203.08:06:01.58#ibcon#read 4, iclass 7, count 0 2006.203.08:06:01.58#ibcon#about to read 5, iclass 7, count 0 2006.203.08:06:01.58#ibcon#read 5, iclass 7, count 0 2006.203.08:06:01.58#ibcon#about to read 6, iclass 7, count 0 2006.203.08:06:01.58#ibcon#read 6, iclass 7, count 0 2006.203.08:06:01.58#ibcon#end of sib2, iclass 7, count 0 2006.203.08:06:01.58#ibcon#*after write, iclass 7, count 0 2006.203.08:06:01.58#ibcon#*before return 0, iclass 7, count 0 2006.203.08:06:01.58#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.203.08:06:01.58#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.203.08:06:01.58#ibcon#about to clear, iclass 7 cls_cnt 0 2006.203.08:06:01.58#ibcon#cleared, iclass 7 cls_cnt 0 2006.203.08:06:01.58$vc4f8/vb=1,4 2006.203.08:06:01.58#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.203.08:06:01.58#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.203.08:06:01.58#ibcon#ireg 11 cls_cnt 2 2006.203.08:06:01.58#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.203.08:06:01.58#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.203.08:06:01.58#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.203.08:06:01.58#ibcon#enter wrdev, iclass 11, count 2 2006.203.08:06:01.58#ibcon#first serial, iclass 11, count 2 2006.203.08:06:01.58#ibcon#enter sib2, iclass 11, count 2 2006.203.08:06:01.58#ibcon#flushed, iclass 11, count 2 2006.203.08:06:01.58#ibcon#about to write, iclass 11, count 2 2006.203.08:06:01.58#ibcon#wrote, iclass 11, count 2 2006.203.08:06:01.58#ibcon#about to read 3, iclass 11, count 2 2006.203.08:06:01.60#ibcon#read 3, iclass 11, count 2 2006.203.08:06:01.60#ibcon#about to read 4, iclass 11, count 2 2006.203.08:06:01.60#ibcon#read 4, iclass 11, count 2 2006.203.08:06:01.60#ibcon#about to read 5, iclass 11, count 2 2006.203.08:06:01.60#ibcon#read 5, iclass 11, count 2 2006.203.08:06:01.60#ibcon#about to read 6, iclass 11, count 2 2006.203.08:06:01.60#ibcon#read 6, iclass 11, count 2 2006.203.08:06:01.60#ibcon#end of sib2, iclass 11, count 2 2006.203.08:06:01.60#ibcon#*mode == 0, iclass 11, count 2 2006.203.08:06:01.60#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.203.08:06:01.60#ibcon#[27=AT01-04\r\n] 2006.203.08:06:01.60#ibcon#*before write, iclass 11, count 2 2006.203.08:06:01.60#ibcon#enter sib2, iclass 11, count 2 2006.203.08:06:01.60#ibcon#flushed, iclass 11, count 2 2006.203.08:06:01.60#ibcon#about to write, iclass 11, count 2 2006.203.08:06:01.60#ibcon#wrote, iclass 11, count 2 2006.203.08:06:01.60#ibcon#about to read 3, iclass 11, count 2 2006.203.08:06:01.63#ibcon#read 3, iclass 11, count 2 2006.203.08:06:01.63#ibcon#about to read 4, iclass 11, count 2 2006.203.08:06:01.63#ibcon#read 4, iclass 11, count 2 2006.203.08:06:01.63#ibcon#about to read 5, iclass 11, count 2 2006.203.08:06:01.63#ibcon#read 5, iclass 11, count 2 2006.203.08:06:01.63#ibcon#about to read 6, iclass 11, count 2 2006.203.08:06:01.63#ibcon#read 6, iclass 11, count 2 2006.203.08:06:01.63#ibcon#end of sib2, iclass 11, count 2 2006.203.08:06:01.63#ibcon#*after write, iclass 11, count 2 2006.203.08:06:01.63#ibcon#*before return 0, iclass 11, count 2 2006.203.08:06:01.63#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.203.08:06:01.63#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.203.08:06:01.63#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.203.08:06:01.63#ibcon#ireg 7 cls_cnt 0 2006.203.08:06:01.63#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.203.08:06:01.75#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.203.08:06:01.75#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.203.08:06:01.75#ibcon#enter wrdev, iclass 11, count 0 2006.203.08:06:01.75#ibcon#first serial, iclass 11, count 0 2006.203.08:06:01.75#ibcon#enter sib2, iclass 11, count 0 2006.203.08:06:01.75#ibcon#flushed, iclass 11, count 0 2006.203.08:06:01.75#ibcon#about to write, iclass 11, count 0 2006.203.08:06:01.75#ibcon#wrote, iclass 11, count 0 2006.203.08:06:01.75#ibcon#about to read 3, iclass 11, count 0 2006.203.08:06:01.77#ibcon#read 3, iclass 11, count 0 2006.203.08:06:01.77#ibcon#about to read 4, iclass 11, count 0 2006.203.08:06:01.77#ibcon#read 4, iclass 11, count 0 2006.203.08:06:01.77#ibcon#about to read 5, iclass 11, count 0 2006.203.08:06:01.77#ibcon#read 5, iclass 11, count 0 2006.203.08:06:01.77#ibcon#about to read 6, iclass 11, count 0 2006.203.08:06:01.77#ibcon#read 6, iclass 11, count 0 2006.203.08:06:01.77#ibcon#end of sib2, iclass 11, count 0 2006.203.08:06:01.77#ibcon#*mode == 0, iclass 11, count 0 2006.203.08:06:01.77#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.203.08:06:01.77#ibcon#[27=USB\r\n] 2006.203.08:06:01.77#ibcon#*before write, iclass 11, count 0 2006.203.08:06:01.77#ibcon#enter sib2, iclass 11, count 0 2006.203.08:06:01.77#ibcon#flushed, iclass 11, count 0 2006.203.08:06:01.77#ibcon#about to write, iclass 11, count 0 2006.203.08:06:01.77#ibcon#wrote, iclass 11, count 0 2006.203.08:06:01.77#ibcon#about to read 3, iclass 11, count 0 2006.203.08:06:01.80#ibcon#read 3, iclass 11, count 0 2006.203.08:06:01.80#ibcon#about to read 4, iclass 11, count 0 2006.203.08:06:01.80#ibcon#read 4, iclass 11, count 0 2006.203.08:06:01.80#ibcon#about to read 5, iclass 11, count 0 2006.203.08:06:01.80#ibcon#read 5, iclass 11, count 0 2006.203.08:06:01.80#ibcon#about to read 6, iclass 11, count 0 2006.203.08:06:01.80#ibcon#read 6, iclass 11, count 0 2006.203.08:06:01.80#ibcon#end of sib2, iclass 11, count 0 2006.203.08:06:01.80#ibcon#*after write, iclass 11, count 0 2006.203.08:06:01.80#ibcon#*before return 0, iclass 11, count 0 2006.203.08:06:01.80#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.203.08:06:01.80#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.203.08:06:01.80#ibcon#about to clear, iclass 11 cls_cnt 0 2006.203.08:06:01.80#ibcon#cleared, iclass 11 cls_cnt 0 2006.203.08:06:01.80$vc4f8/vblo=2,640.99 2006.203.08:06:01.80#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.203.08:06:01.80#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.203.08:06:01.80#ibcon#ireg 17 cls_cnt 0 2006.203.08:06:01.80#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.203.08:06:01.80#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.203.08:06:01.80#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.203.08:06:01.80#ibcon#enter wrdev, iclass 13, count 0 2006.203.08:06:01.80#ibcon#first serial, iclass 13, count 0 2006.203.08:06:01.80#ibcon#enter sib2, iclass 13, count 0 2006.203.08:06:01.80#ibcon#flushed, iclass 13, count 0 2006.203.08:06:01.80#ibcon#about to write, iclass 13, count 0 2006.203.08:06:01.80#ibcon#wrote, iclass 13, count 0 2006.203.08:06:01.80#ibcon#about to read 3, iclass 13, count 0 2006.203.08:06:01.82#ibcon#read 3, iclass 13, count 0 2006.203.08:06:01.82#ibcon#about to read 4, iclass 13, count 0 2006.203.08:06:01.82#ibcon#read 4, iclass 13, count 0 2006.203.08:06:01.82#ibcon#about to read 5, iclass 13, count 0 2006.203.08:06:01.82#ibcon#read 5, iclass 13, count 0 2006.203.08:06:01.82#ibcon#about to read 6, iclass 13, count 0 2006.203.08:06:01.82#ibcon#read 6, iclass 13, count 0 2006.203.08:06:01.82#ibcon#end of sib2, iclass 13, count 0 2006.203.08:06:01.82#ibcon#*mode == 0, iclass 13, count 0 2006.203.08:06:01.82#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.203.08:06:01.82#ibcon#[28=FRQ=02,640.99\r\n] 2006.203.08:06:01.82#ibcon#*before write, iclass 13, count 0 2006.203.08:06:01.82#ibcon#enter sib2, iclass 13, count 0 2006.203.08:06:01.82#ibcon#flushed, iclass 13, count 0 2006.203.08:06:01.82#ibcon#about to write, iclass 13, count 0 2006.203.08:06:01.82#ibcon#wrote, iclass 13, count 0 2006.203.08:06:01.82#ibcon#about to read 3, iclass 13, count 0 2006.203.08:06:01.86#ibcon#read 3, iclass 13, count 0 2006.203.08:06:01.86#ibcon#about to read 4, iclass 13, count 0 2006.203.08:06:01.86#ibcon#read 4, iclass 13, count 0 2006.203.08:06:01.86#ibcon#about to read 5, iclass 13, count 0 2006.203.08:06:01.86#ibcon#read 5, iclass 13, count 0 2006.203.08:06:01.86#ibcon#about to read 6, iclass 13, count 0 2006.203.08:06:01.86#ibcon#read 6, iclass 13, count 0 2006.203.08:06:01.86#ibcon#end of sib2, iclass 13, count 0 2006.203.08:06:01.86#ibcon#*after write, iclass 13, count 0 2006.203.08:06:01.86#ibcon#*before return 0, iclass 13, count 0 2006.203.08:06:01.86#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.203.08:06:01.86#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.203.08:06:01.86#ibcon#about to clear, iclass 13 cls_cnt 0 2006.203.08:06:01.86#ibcon#cleared, iclass 13 cls_cnt 0 2006.203.08:06:01.86$vc4f8/vb=2,4 2006.203.08:06:01.86#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.203.08:06:01.86#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.203.08:06:01.86#ibcon#ireg 11 cls_cnt 2 2006.203.08:06:01.86#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.203.08:06:01.92#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.203.08:06:01.92#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.203.08:06:01.92#ibcon#enter wrdev, iclass 15, count 2 2006.203.08:06:01.92#ibcon#first serial, iclass 15, count 2 2006.203.08:06:01.92#ibcon#enter sib2, iclass 15, count 2 2006.203.08:06:01.92#ibcon#flushed, iclass 15, count 2 2006.203.08:06:01.92#ibcon#about to write, iclass 15, count 2 2006.203.08:06:01.92#ibcon#wrote, iclass 15, count 2 2006.203.08:06:01.92#ibcon#about to read 3, iclass 15, count 2 2006.203.08:06:01.94#ibcon#read 3, iclass 15, count 2 2006.203.08:06:01.94#ibcon#about to read 4, iclass 15, count 2 2006.203.08:06:01.94#ibcon#read 4, iclass 15, count 2 2006.203.08:06:01.94#ibcon#about to read 5, iclass 15, count 2 2006.203.08:06:01.94#ibcon#read 5, iclass 15, count 2 2006.203.08:06:01.94#ibcon#about to read 6, iclass 15, count 2 2006.203.08:06:01.94#ibcon#read 6, iclass 15, count 2 2006.203.08:06:01.94#ibcon#end of sib2, iclass 15, count 2 2006.203.08:06:01.94#ibcon#*mode == 0, iclass 15, count 2 2006.203.08:06:01.94#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.203.08:06:01.94#ibcon#[27=AT02-04\r\n] 2006.203.08:06:01.94#ibcon#*before write, iclass 15, count 2 2006.203.08:06:01.94#ibcon#enter sib2, iclass 15, count 2 2006.203.08:06:01.94#ibcon#flushed, iclass 15, count 2 2006.203.08:06:01.94#ibcon#about to write, iclass 15, count 2 2006.203.08:06:01.94#ibcon#wrote, iclass 15, count 2 2006.203.08:06:01.94#ibcon#about to read 3, iclass 15, count 2 2006.203.08:06:01.97#ibcon#read 3, iclass 15, count 2 2006.203.08:06:01.97#ibcon#about to read 4, iclass 15, count 2 2006.203.08:06:01.97#ibcon#read 4, iclass 15, count 2 2006.203.08:06:01.97#ibcon#about to read 5, iclass 15, count 2 2006.203.08:06:01.97#ibcon#read 5, iclass 15, count 2 2006.203.08:06:01.97#ibcon#about to read 6, iclass 15, count 2 2006.203.08:06:01.97#ibcon#read 6, iclass 15, count 2 2006.203.08:06:01.97#ibcon#end of sib2, iclass 15, count 2 2006.203.08:06:01.97#ibcon#*after write, iclass 15, count 2 2006.203.08:06:01.97#ibcon#*before return 0, iclass 15, count 2 2006.203.08:06:01.97#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.203.08:06:01.97#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.203.08:06:01.97#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.203.08:06:01.97#ibcon#ireg 7 cls_cnt 0 2006.203.08:06:01.97#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.203.08:06:02.09#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.203.08:06:02.09#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.203.08:06:02.09#ibcon#enter wrdev, iclass 15, count 0 2006.203.08:06:02.09#ibcon#first serial, iclass 15, count 0 2006.203.08:06:02.09#ibcon#enter sib2, iclass 15, count 0 2006.203.08:06:02.09#ibcon#flushed, iclass 15, count 0 2006.203.08:06:02.09#ibcon#about to write, iclass 15, count 0 2006.203.08:06:02.09#ibcon#wrote, iclass 15, count 0 2006.203.08:06:02.09#ibcon#about to read 3, iclass 15, count 0 2006.203.08:06:02.11#ibcon#read 3, iclass 15, count 0 2006.203.08:06:02.11#ibcon#about to read 4, iclass 15, count 0 2006.203.08:06:02.11#ibcon#read 4, iclass 15, count 0 2006.203.08:06:02.11#ibcon#about to read 5, iclass 15, count 0 2006.203.08:06:02.11#ibcon#read 5, iclass 15, count 0 2006.203.08:06:02.11#ibcon#about to read 6, iclass 15, count 0 2006.203.08:06:02.11#ibcon#read 6, iclass 15, count 0 2006.203.08:06:02.11#ibcon#end of sib2, iclass 15, count 0 2006.203.08:06:02.11#ibcon#*mode == 0, iclass 15, count 0 2006.203.08:06:02.11#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.203.08:06:02.11#ibcon#[27=USB\r\n] 2006.203.08:06:02.11#ibcon#*before write, iclass 15, count 0 2006.203.08:06:02.11#ibcon#enter sib2, iclass 15, count 0 2006.203.08:06:02.11#ibcon#flushed, iclass 15, count 0 2006.203.08:06:02.11#ibcon#about to write, iclass 15, count 0 2006.203.08:06:02.11#ibcon#wrote, iclass 15, count 0 2006.203.08:06:02.11#ibcon#about to read 3, iclass 15, count 0 2006.203.08:06:02.14#ibcon#read 3, iclass 15, count 0 2006.203.08:06:02.14#ibcon#about to read 4, iclass 15, count 0 2006.203.08:06:02.14#ibcon#read 4, iclass 15, count 0 2006.203.08:06:02.14#ibcon#about to read 5, iclass 15, count 0 2006.203.08:06:02.14#ibcon#read 5, iclass 15, count 0 2006.203.08:06:02.14#ibcon#about to read 6, iclass 15, count 0 2006.203.08:06:02.14#ibcon#read 6, iclass 15, count 0 2006.203.08:06:02.14#ibcon#end of sib2, iclass 15, count 0 2006.203.08:06:02.14#ibcon#*after write, iclass 15, count 0 2006.203.08:06:02.14#ibcon#*before return 0, iclass 15, count 0 2006.203.08:06:02.14#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.203.08:06:02.14#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.203.08:06:02.14#ibcon#about to clear, iclass 15 cls_cnt 0 2006.203.08:06:02.14#ibcon#cleared, iclass 15 cls_cnt 0 2006.203.08:06:02.14$vc4f8/vblo=3,656.99 2006.203.08:06:02.14#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.203.08:06:02.14#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.203.08:06:02.14#ibcon#ireg 17 cls_cnt 0 2006.203.08:06:02.14#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.203.08:06:02.14#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.203.08:06:02.14#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.203.08:06:02.14#ibcon#enter wrdev, iclass 17, count 0 2006.203.08:06:02.14#ibcon#first serial, iclass 17, count 0 2006.203.08:06:02.14#ibcon#enter sib2, iclass 17, count 0 2006.203.08:06:02.14#ibcon#flushed, iclass 17, count 0 2006.203.08:06:02.14#ibcon#about to write, iclass 17, count 0 2006.203.08:06:02.14#ibcon#wrote, iclass 17, count 0 2006.203.08:06:02.14#ibcon#about to read 3, iclass 17, count 0 2006.203.08:06:02.16#ibcon#read 3, iclass 17, count 0 2006.203.08:06:02.16#ibcon#about to read 4, iclass 17, count 0 2006.203.08:06:02.16#ibcon#read 4, iclass 17, count 0 2006.203.08:06:02.16#ibcon#about to read 5, iclass 17, count 0 2006.203.08:06:02.16#ibcon#read 5, iclass 17, count 0 2006.203.08:06:02.16#ibcon#about to read 6, iclass 17, count 0 2006.203.08:06:02.16#ibcon#read 6, iclass 17, count 0 2006.203.08:06:02.16#ibcon#end of sib2, iclass 17, count 0 2006.203.08:06:02.16#ibcon#*mode == 0, iclass 17, count 0 2006.203.08:06:02.16#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.203.08:06:02.16#ibcon#[28=FRQ=03,656.99\r\n] 2006.203.08:06:02.16#ibcon#*before write, iclass 17, count 0 2006.203.08:06:02.16#ibcon#enter sib2, iclass 17, count 0 2006.203.08:06:02.16#ibcon#flushed, iclass 17, count 0 2006.203.08:06:02.16#ibcon#about to write, iclass 17, count 0 2006.203.08:06:02.16#ibcon#wrote, iclass 17, count 0 2006.203.08:06:02.16#ibcon#about to read 3, iclass 17, count 0 2006.203.08:06:02.20#ibcon#read 3, iclass 17, count 0 2006.203.08:06:02.20#ibcon#about to read 4, iclass 17, count 0 2006.203.08:06:02.20#ibcon#read 4, iclass 17, count 0 2006.203.08:06:02.20#ibcon#about to read 5, iclass 17, count 0 2006.203.08:06:02.20#ibcon#read 5, iclass 17, count 0 2006.203.08:06:02.20#ibcon#about to read 6, iclass 17, count 0 2006.203.08:06:02.20#ibcon#read 6, iclass 17, count 0 2006.203.08:06:02.20#ibcon#end of sib2, iclass 17, count 0 2006.203.08:06:02.20#ibcon#*after write, iclass 17, count 0 2006.203.08:06:02.20#ibcon#*before return 0, iclass 17, count 0 2006.203.08:06:02.20#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.203.08:06:02.20#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.203.08:06:02.20#ibcon#about to clear, iclass 17 cls_cnt 0 2006.203.08:06:02.20#ibcon#cleared, iclass 17 cls_cnt 0 2006.203.08:06:02.20$vc4f8/vb=3,4 2006.203.08:06:02.20#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.203.08:06:02.20#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.203.08:06:02.20#ibcon#ireg 11 cls_cnt 2 2006.203.08:06:02.20#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.203.08:06:02.26#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.203.08:06:02.26#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.203.08:06:02.26#ibcon#enter wrdev, iclass 19, count 2 2006.203.08:06:02.26#ibcon#first serial, iclass 19, count 2 2006.203.08:06:02.26#ibcon#enter sib2, iclass 19, count 2 2006.203.08:06:02.26#ibcon#flushed, iclass 19, count 2 2006.203.08:06:02.26#ibcon#about to write, iclass 19, count 2 2006.203.08:06:02.26#ibcon#wrote, iclass 19, count 2 2006.203.08:06:02.26#ibcon#about to read 3, iclass 19, count 2 2006.203.08:06:02.28#ibcon#read 3, iclass 19, count 2 2006.203.08:06:02.28#ibcon#about to read 4, iclass 19, count 2 2006.203.08:06:02.28#ibcon#read 4, iclass 19, count 2 2006.203.08:06:02.28#ibcon#about to read 5, iclass 19, count 2 2006.203.08:06:02.28#ibcon#read 5, iclass 19, count 2 2006.203.08:06:02.28#ibcon#about to read 6, iclass 19, count 2 2006.203.08:06:02.28#ibcon#read 6, iclass 19, count 2 2006.203.08:06:02.28#ibcon#end of sib2, iclass 19, count 2 2006.203.08:06:02.28#ibcon#*mode == 0, iclass 19, count 2 2006.203.08:06:02.28#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.203.08:06:02.28#ibcon#[27=AT03-04\r\n] 2006.203.08:06:02.28#ibcon#*before write, iclass 19, count 2 2006.203.08:06:02.28#ibcon#enter sib2, iclass 19, count 2 2006.203.08:06:02.28#ibcon#flushed, iclass 19, count 2 2006.203.08:06:02.28#ibcon#about to write, iclass 19, count 2 2006.203.08:06:02.28#ibcon#wrote, iclass 19, count 2 2006.203.08:06:02.28#ibcon#about to read 3, iclass 19, count 2 2006.203.08:06:02.31#ibcon#read 3, iclass 19, count 2 2006.203.08:06:02.31#ibcon#about to read 4, iclass 19, count 2 2006.203.08:06:02.31#ibcon#read 4, iclass 19, count 2 2006.203.08:06:02.31#ibcon#about to read 5, iclass 19, count 2 2006.203.08:06:02.31#ibcon#read 5, iclass 19, count 2 2006.203.08:06:02.31#ibcon#about to read 6, iclass 19, count 2 2006.203.08:06:02.31#ibcon#read 6, iclass 19, count 2 2006.203.08:06:02.31#ibcon#end of sib2, iclass 19, count 2 2006.203.08:06:02.31#ibcon#*after write, iclass 19, count 2 2006.203.08:06:02.31#ibcon#*before return 0, iclass 19, count 2 2006.203.08:06:02.31#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.203.08:06:02.31#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.203.08:06:02.31#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.203.08:06:02.31#ibcon#ireg 7 cls_cnt 0 2006.203.08:06:02.31#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.203.08:06:02.43#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.203.08:06:02.43#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.203.08:06:02.43#ibcon#enter wrdev, iclass 19, count 0 2006.203.08:06:02.43#ibcon#first serial, iclass 19, count 0 2006.203.08:06:02.43#ibcon#enter sib2, iclass 19, count 0 2006.203.08:06:02.43#ibcon#flushed, iclass 19, count 0 2006.203.08:06:02.43#ibcon#about to write, iclass 19, count 0 2006.203.08:06:02.43#ibcon#wrote, iclass 19, count 0 2006.203.08:06:02.43#ibcon#about to read 3, iclass 19, count 0 2006.203.08:06:02.45#ibcon#read 3, iclass 19, count 0 2006.203.08:06:02.45#ibcon#about to read 4, iclass 19, count 0 2006.203.08:06:02.45#ibcon#read 4, iclass 19, count 0 2006.203.08:06:02.45#ibcon#about to read 5, iclass 19, count 0 2006.203.08:06:02.45#ibcon#read 5, iclass 19, count 0 2006.203.08:06:02.45#ibcon#about to read 6, iclass 19, count 0 2006.203.08:06:02.45#ibcon#read 6, iclass 19, count 0 2006.203.08:06:02.45#ibcon#end of sib2, iclass 19, count 0 2006.203.08:06:02.45#ibcon#*mode == 0, iclass 19, count 0 2006.203.08:06:02.45#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.203.08:06:02.45#ibcon#[27=USB\r\n] 2006.203.08:06:02.45#ibcon#*before write, iclass 19, count 0 2006.203.08:06:02.45#ibcon#enter sib2, iclass 19, count 0 2006.203.08:06:02.45#ibcon#flushed, iclass 19, count 0 2006.203.08:06:02.45#ibcon#about to write, iclass 19, count 0 2006.203.08:06:02.45#ibcon#wrote, iclass 19, count 0 2006.203.08:06:02.45#ibcon#about to read 3, iclass 19, count 0 2006.203.08:06:02.48#ibcon#read 3, iclass 19, count 0 2006.203.08:06:02.48#ibcon#about to read 4, iclass 19, count 0 2006.203.08:06:02.48#ibcon#read 4, iclass 19, count 0 2006.203.08:06:02.48#ibcon#about to read 5, iclass 19, count 0 2006.203.08:06:02.48#ibcon#read 5, iclass 19, count 0 2006.203.08:06:02.48#ibcon#about to read 6, iclass 19, count 0 2006.203.08:06:02.48#ibcon#read 6, iclass 19, count 0 2006.203.08:06:02.48#ibcon#end of sib2, iclass 19, count 0 2006.203.08:06:02.48#ibcon#*after write, iclass 19, count 0 2006.203.08:06:02.48#ibcon#*before return 0, iclass 19, count 0 2006.203.08:06:02.48#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.203.08:06:02.48#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.203.08:06:02.48#ibcon#about to clear, iclass 19 cls_cnt 0 2006.203.08:06:02.48#ibcon#cleared, iclass 19 cls_cnt 0 2006.203.08:06:02.48$vc4f8/vblo=4,712.99 2006.203.08:06:02.48#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.203.08:06:02.48#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.203.08:06:02.48#ibcon#ireg 17 cls_cnt 0 2006.203.08:06:02.48#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.203.08:06:02.48#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.203.08:06:02.48#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.203.08:06:02.48#ibcon#enter wrdev, iclass 21, count 0 2006.203.08:06:02.48#ibcon#first serial, iclass 21, count 0 2006.203.08:06:02.48#ibcon#enter sib2, iclass 21, count 0 2006.203.08:06:02.48#ibcon#flushed, iclass 21, count 0 2006.203.08:06:02.48#ibcon#about to write, iclass 21, count 0 2006.203.08:06:02.48#ibcon#wrote, iclass 21, count 0 2006.203.08:06:02.48#ibcon#about to read 3, iclass 21, count 0 2006.203.08:06:02.50#ibcon#read 3, iclass 21, count 0 2006.203.08:06:02.50#ibcon#about to read 4, iclass 21, count 0 2006.203.08:06:02.50#ibcon#read 4, iclass 21, count 0 2006.203.08:06:02.50#ibcon#about to read 5, iclass 21, count 0 2006.203.08:06:02.50#ibcon#read 5, iclass 21, count 0 2006.203.08:06:02.50#ibcon#about to read 6, iclass 21, count 0 2006.203.08:06:02.50#ibcon#read 6, iclass 21, count 0 2006.203.08:06:02.50#ibcon#end of sib2, iclass 21, count 0 2006.203.08:06:02.50#ibcon#*mode == 0, iclass 21, count 0 2006.203.08:06:02.50#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.203.08:06:02.50#ibcon#[28=FRQ=04,712.99\r\n] 2006.203.08:06:02.50#ibcon#*before write, iclass 21, count 0 2006.203.08:06:02.50#ibcon#enter sib2, iclass 21, count 0 2006.203.08:06:02.50#ibcon#flushed, iclass 21, count 0 2006.203.08:06:02.50#ibcon#about to write, iclass 21, count 0 2006.203.08:06:02.50#ibcon#wrote, iclass 21, count 0 2006.203.08:06:02.50#ibcon#about to read 3, iclass 21, count 0 2006.203.08:06:02.54#ibcon#read 3, iclass 21, count 0 2006.203.08:06:02.54#ibcon#about to read 4, iclass 21, count 0 2006.203.08:06:02.54#ibcon#read 4, iclass 21, count 0 2006.203.08:06:02.54#ibcon#about to read 5, iclass 21, count 0 2006.203.08:06:02.54#ibcon#read 5, iclass 21, count 0 2006.203.08:06:02.54#ibcon#about to read 6, iclass 21, count 0 2006.203.08:06:02.54#ibcon#read 6, iclass 21, count 0 2006.203.08:06:02.54#ibcon#end of sib2, iclass 21, count 0 2006.203.08:06:02.54#ibcon#*after write, iclass 21, count 0 2006.203.08:06:02.54#ibcon#*before return 0, iclass 21, count 0 2006.203.08:06:02.54#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.203.08:06:02.54#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.203.08:06:02.54#ibcon#about to clear, iclass 21 cls_cnt 0 2006.203.08:06:02.54#ibcon#cleared, iclass 21 cls_cnt 0 2006.203.08:06:02.54$vc4f8/vb=4,4 2006.203.08:06:02.54#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.203.08:06:02.54#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.203.08:06:02.54#ibcon#ireg 11 cls_cnt 2 2006.203.08:06:02.54#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.203.08:06:02.60#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.203.08:06:02.60#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.203.08:06:02.60#ibcon#enter wrdev, iclass 23, count 2 2006.203.08:06:02.60#ibcon#first serial, iclass 23, count 2 2006.203.08:06:02.60#ibcon#enter sib2, iclass 23, count 2 2006.203.08:06:02.60#ibcon#flushed, iclass 23, count 2 2006.203.08:06:02.60#ibcon#about to write, iclass 23, count 2 2006.203.08:06:02.60#ibcon#wrote, iclass 23, count 2 2006.203.08:06:02.60#ibcon#about to read 3, iclass 23, count 2 2006.203.08:06:02.62#ibcon#read 3, iclass 23, count 2 2006.203.08:06:02.62#ibcon#about to read 4, iclass 23, count 2 2006.203.08:06:02.62#ibcon#read 4, iclass 23, count 2 2006.203.08:06:02.62#ibcon#about to read 5, iclass 23, count 2 2006.203.08:06:02.62#ibcon#read 5, iclass 23, count 2 2006.203.08:06:02.62#ibcon#about to read 6, iclass 23, count 2 2006.203.08:06:02.62#ibcon#read 6, iclass 23, count 2 2006.203.08:06:02.62#ibcon#end of sib2, iclass 23, count 2 2006.203.08:06:02.62#ibcon#*mode == 0, iclass 23, count 2 2006.203.08:06:02.62#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.203.08:06:02.62#ibcon#[27=AT04-04\r\n] 2006.203.08:06:02.62#ibcon#*before write, iclass 23, count 2 2006.203.08:06:02.62#ibcon#enter sib2, iclass 23, count 2 2006.203.08:06:02.62#ibcon#flushed, iclass 23, count 2 2006.203.08:06:02.62#ibcon#about to write, iclass 23, count 2 2006.203.08:06:02.62#ibcon#wrote, iclass 23, count 2 2006.203.08:06:02.62#ibcon#about to read 3, iclass 23, count 2 2006.203.08:06:02.65#ibcon#read 3, iclass 23, count 2 2006.203.08:06:02.65#ibcon#about to read 4, iclass 23, count 2 2006.203.08:06:02.65#ibcon#read 4, iclass 23, count 2 2006.203.08:06:02.65#ibcon#about to read 5, iclass 23, count 2 2006.203.08:06:02.65#ibcon#read 5, iclass 23, count 2 2006.203.08:06:02.65#ibcon#about to read 6, iclass 23, count 2 2006.203.08:06:02.65#ibcon#read 6, iclass 23, count 2 2006.203.08:06:02.65#ibcon#end of sib2, iclass 23, count 2 2006.203.08:06:02.65#ibcon#*after write, iclass 23, count 2 2006.203.08:06:02.65#ibcon#*before return 0, iclass 23, count 2 2006.203.08:06:02.65#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.203.08:06:02.65#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.203.08:06:02.65#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.203.08:06:02.65#ibcon#ireg 7 cls_cnt 0 2006.203.08:06:02.65#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.203.08:06:02.77#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.203.08:06:02.77#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.203.08:06:02.77#ibcon#enter wrdev, iclass 23, count 0 2006.203.08:06:02.77#ibcon#first serial, iclass 23, count 0 2006.203.08:06:02.77#ibcon#enter sib2, iclass 23, count 0 2006.203.08:06:02.77#ibcon#flushed, iclass 23, count 0 2006.203.08:06:02.77#ibcon#about to write, iclass 23, count 0 2006.203.08:06:02.77#ibcon#wrote, iclass 23, count 0 2006.203.08:06:02.77#ibcon#about to read 3, iclass 23, count 0 2006.203.08:06:02.79#ibcon#read 3, iclass 23, count 0 2006.203.08:06:02.79#ibcon#about to read 4, iclass 23, count 0 2006.203.08:06:02.79#ibcon#read 4, iclass 23, count 0 2006.203.08:06:02.79#ibcon#about to read 5, iclass 23, count 0 2006.203.08:06:02.79#ibcon#read 5, iclass 23, count 0 2006.203.08:06:02.79#ibcon#about to read 6, iclass 23, count 0 2006.203.08:06:02.79#ibcon#read 6, iclass 23, count 0 2006.203.08:06:02.79#ibcon#end of sib2, iclass 23, count 0 2006.203.08:06:02.79#ibcon#*mode == 0, iclass 23, count 0 2006.203.08:06:02.79#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.203.08:06:02.79#ibcon#[27=USB\r\n] 2006.203.08:06:02.79#ibcon#*before write, iclass 23, count 0 2006.203.08:06:02.79#ibcon#enter sib2, iclass 23, count 0 2006.203.08:06:02.79#ibcon#flushed, iclass 23, count 0 2006.203.08:06:02.79#ibcon#about to write, iclass 23, count 0 2006.203.08:06:02.79#ibcon#wrote, iclass 23, count 0 2006.203.08:06:02.79#ibcon#about to read 3, iclass 23, count 0 2006.203.08:06:02.82#ibcon#read 3, iclass 23, count 0 2006.203.08:06:02.82#ibcon#about to read 4, iclass 23, count 0 2006.203.08:06:02.82#ibcon#read 4, iclass 23, count 0 2006.203.08:06:02.82#ibcon#about to read 5, iclass 23, count 0 2006.203.08:06:02.82#ibcon#read 5, iclass 23, count 0 2006.203.08:06:02.82#ibcon#about to read 6, iclass 23, count 0 2006.203.08:06:02.82#ibcon#read 6, iclass 23, count 0 2006.203.08:06:02.82#ibcon#end of sib2, iclass 23, count 0 2006.203.08:06:02.82#ibcon#*after write, iclass 23, count 0 2006.203.08:06:02.82#ibcon#*before return 0, iclass 23, count 0 2006.203.08:06:02.82#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.203.08:06:02.82#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.203.08:06:02.82#ibcon#about to clear, iclass 23 cls_cnt 0 2006.203.08:06:02.82#ibcon#cleared, iclass 23 cls_cnt 0 2006.203.08:06:02.82$vc4f8/vblo=5,744.99 2006.203.08:06:02.82#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.203.08:06:02.82#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.203.08:06:02.82#ibcon#ireg 17 cls_cnt 0 2006.203.08:06:02.82#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.203.08:06:02.82#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.203.08:06:02.82#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.203.08:06:02.82#ibcon#enter wrdev, iclass 25, count 0 2006.203.08:06:02.82#ibcon#first serial, iclass 25, count 0 2006.203.08:06:02.82#ibcon#enter sib2, iclass 25, count 0 2006.203.08:06:02.82#ibcon#flushed, iclass 25, count 0 2006.203.08:06:02.82#ibcon#about to write, iclass 25, count 0 2006.203.08:06:02.82#ibcon#wrote, iclass 25, count 0 2006.203.08:06:02.82#ibcon#about to read 3, iclass 25, count 0 2006.203.08:06:02.84#ibcon#read 3, iclass 25, count 0 2006.203.08:06:02.84#ibcon#about to read 4, iclass 25, count 0 2006.203.08:06:02.84#ibcon#read 4, iclass 25, count 0 2006.203.08:06:02.84#ibcon#about to read 5, iclass 25, count 0 2006.203.08:06:02.84#ibcon#read 5, iclass 25, count 0 2006.203.08:06:02.84#ibcon#about to read 6, iclass 25, count 0 2006.203.08:06:02.84#ibcon#read 6, iclass 25, count 0 2006.203.08:06:02.84#ibcon#end of sib2, iclass 25, count 0 2006.203.08:06:02.84#ibcon#*mode == 0, iclass 25, count 0 2006.203.08:06:02.84#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.203.08:06:02.84#ibcon#[28=FRQ=05,744.99\r\n] 2006.203.08:06:02.84#ibcon#*before write, iclass 25, count 0 2006.203.08:06:02.84#ibcon#enter sib2, iclass 25, count 0 2006.203.08:06:02.84#ibcon#flushed, iclass 25, count 0 2006.203.08:06:02.84#ibcon#about to write, iclass 25, count 0 2006.203.08:06:02.84#ibcon#wrote, iclass 25, count 0 2006.203.08:06:02.84#ibcon#about to read 3, iclass 25, count 0 2006.203.08:06:02.88#ibcon#read 3, iclass 25, count 0 2006.203.08:06:02.88#ibcon#about to read 4, iclass 25, count 0 2006.203.08:06:02.88#ibcon#read 4, iclass 25, count 0 2006.203.08:06:02.88#ibcon#about to read 5, iclass 25, count 0 2006.203.08:06:02.88#ibcon#read 5, iclass 25, count 0 2006.203.08:06:02.88#ibcon#about to read 6, iclass 25, count 0 2006.203.08:06:02.88#ibcon#read 6, iclass 25, count 0 2006.203.08:06:02.88#ibcon#end of sib2, iclass 25, count 0 2006.203.08:06:02.88#ibcon#*after write, iclass 25, count 0 2006.203.08:06:02.88#ibcon#*before return 0, iclass 25, count 0 2006.203.08:06:02.88#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.203.08:06:02.88#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.203.08:06:02.88#ibcon#about to clear, iclass 25 cls_cnt 0 2006.203.08:06:02.88#ibcon#cleared, iclass 25 cls_cnt 0 2006.203.08:06:02.88$vc4f8/vb=5,3 2006.203.08:06:02.88#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.203.08:06:02.88#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.203.08:06:02.88#ibcon#ireg 11 cls_cnt 2 2006.203.08:06:02.88#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.203.08:06:02.94#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.203.08:06:02.94#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.203.08:06:02.94#ibcon#enter wrdev, iclass 27, count 2 2006.203.08:06:02.94#ibcon#first serial, iclass 27, count 2 2006.203.08:06:02.94#ibcon#enter sib2, iclass 27, count 2 2006.203.08:06:02.94#ibcon#flushed, iclass 27, count 2 2006.203.08:06:02.94#ibcon#about to write, iclass 27, count 2 2006.203.08:06:02.94#ibcon#wrote, iclass 27, count 2 2006.203.08:06:02.94#ibcon#about to read 3, iclass 27, count 2 2006.203.08:06:02.96#ibcon#read 3, iclass 27, count 2 2006.203.08:06:02.96#ibcon#about to read 4, iclass 27, count 2 2006.203.08:06:02.96#ibcon#read 4, iclass 27, count 2 2006.203.08:06:02.96#ibcon#about to read 5, iclass 27, count 2 2006.203.08:06:02.96#ibcon#read 5, iclass 27, count 2 2006.203.08:06:02.96#ibcon#about to read 6, iclass 27, count 2 2006.203.08:06:02.96#ibcon#read 6, iclass 27, count 2 2006.203.08:06:02.96#ibcon#end of sib2, iclass 27, count 2 2006.203.08:06:02.96#ibcon#*mode == 0, iclass 27, count 2 2006.203.08:06:02.96#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.203.08:06:02.96#ibcon#[27=AT05-03\r\n] 2006.203.08:06:02.96#ibcon#*before write, iclass 27, count 2 2006.203.08:06:02.96#ibcon#enter sib2, iclass 27, count 2 2006.203.08:06:02.96#ibcon#flushed, iclass 27, count 2 2006.203.08:06:02.96#ibcon#about to write, iclass 27, count 2 2006.203.08:06:02.96#ibcon#wrote, iclass 27, count 2 2006.203.08:06:02.96#ibcon#about to read 3, iclass 27, count 2 2006.203.08:06:02.99#ibcon#read 3, iclass 27, count 2 2006.203.08:06:02.99#ibcon#about to read 4, iclass 27, count 2 2006.203.08:06:02.99#ibcon#read 4, iclass 27, count 2 2006.203.08:06:02.99#ibcon#about to read 5, iclass 27, count 2 2006.203.08:06:02.99#ibcon#read 5, iclass 27, count 2 2006.203.08:06:02.99#ibcon#about to read 6, iclass 27, count 2 2006.203.08:06:02.99#ibcon#read 6, iclass 27, count 2 2006.203.08:06:02.99#ibcon#end of sib2, iclass 27, count 2 2006.203.08:06:02.99#ibcon#*after write, iclass 27, count 2 2006.203.08:06:02.99#ibcon#*before return 0, iclass 27, count 2 2006.203.08:06:02.99#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.203.08:06:02.99#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.203.08:06:02.99#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.203.08:06:02.99#ibcon#ireg 7 cls_cnt 0 2006.203.08:06:02.99#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.203.08:06:03.11#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.203.08:06:03.11#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.203.08:06:03.11#ibcon#enter wrdev, iclass 27, count 0 2006.203.08:06:03.11#ibcon#first serial, iclass 27, count 0 2006.203.08:06:03.11#ibcon#enter sib2, iclass 27, count 0 2006.203.08:06:03.11#ibcon#flushed, iclass 27, count 0 2006.203.08:06:03.11#ibcon#about to write, iclass 27, count 0 2006.203.08:06:03.11#ibcon#wrote, iclass 27, count 0 2006.203.08:06:03.11#ibcon#about to read 3, iclass 27, count 0 2006.203.08:06:03.13#ibcon#read 3, iclass 27, count 0 2006.203.08:06:03.13#ibcon#about to read 4, iclass 27, count 0 2006.203.08:06:03.13#ibcon#read 4, iclass 27, count 0 2006.203.08:06:03.13#ibcon#about to read 5, iclass 27, count 0 2006.203.08:06:03.13#ibcon#read 5, iclass 27, count 0 2006.203.08:06:03.13#ibcon#about to read 6, iclass 27, count 0 2006.203.08:06:03.13#ibcon#read 6, iclass 27, count 0 2006.203.08:06:03.13#ibcon#end of sib2, iclass 27, count 0 2006.203.08:06:03.13#ibcon#*mode == 0, iclass 27, count 0 2006.203.08:06:03.13#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.203.08:06:03.13#ibcon#[27=USB\r\n] 2006.203.08:06:03.13#ibcon#*before write, iclass 27, count 0 2006.203.08:06:03.13#ibcon#enter sib2, iclass 27, count 0 2006.203.08:06:03.13#ibcon#flushed, iclass 27, count 0 2006.203.08:06:03.13#ibcon#about to write, iclass 27, count 0 2006.203.08:06:03.13#ibcon#wrote, iclass 27, count 0 2006.203.08:06:03.13#ibcon#about to read 3, iclass 27, count 0 2006.203.08:06:03.16#ibcon#read 3, iclass 27, count 0 2006.203.08:06:03.16#ibcon#about to read 4, iclass 27, count 0 2006.203.08:06:03.16#ibcon#read 4, iclass 27, count 0 2006.203.08:06:03.16#ibcon#about to read 5, iclass 27, count 0 2006.203.08:06:03.16#ibcon#read 5, iclass 27, count 0 2006.203.08:06:03.16#ibcon#about to read 6, iclass 27, count 0 2006.203.08:06:03.16#ibcon#read 6, iclass 27, count 0 2006.203.08:06:03.16#ibcon#end of sib2, iclass 27, count 0 2006.203.08:06:03.16#ibcon#*after write, iclass 27, count 0 2006.203.08:06:03.16#ibcon#*before return 0, iclass 27, count 0 2006.203.08:06:03.16#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.203.08:06:03.16#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.203.08:06:03.16#ibcon#about to clear, iclass 27 cls_cnt 0 2006.203.08:06:03.16#ibcon#cleared, iclass 27 cls_cnt 0 2006.203.08:06:03.16$vc4f8/vblo=6,752.99 2006.203.08:06:03.16#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.203.08:06:03.16#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.203.08:06:03.16#ibcon#ireg 17 cls_cnt 0 2006.203.08:06:03.16#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.203.08:06:03.16#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.203.08:06:03.16#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.203.08:06:03.16#ibcon#enter wrdev, iclass 29, count 0 2006.203.08:06:03.16#ibcon#first serial, iclass 29, count 0 2006.203.08:06:03.16#ibcon#enter sib2, iclass 29, count 0 2006.203.08:06:03.16#ibcon#flushed, iclass 29, count 0 2006.203.08:06:03.16#ibcon#about to write, iclass 29, count 0 2006.203.08:06:03.16#ibcon#wrote, iclass 29, count 0 2006.203.08:06:03.16#ibcon#about to read 3, iclass 29, count 0 2006.203.08:06:03.18#ibcon#read 3, iclass 29, count 0 2006.203.08:06:03.18#ibcon#about to read 4, iclass 29, count 0 2006.203.08:06:03.18#ibcon#read 4, iclass 29, count 0 2006.203.08:06:03.18#ibcon#about to read 5, iclass 29, count 0 2006.203.08:06:03.18#ibcon#read 5, iclass 29, count 0 2006.203.08:06:03.18#ibcon#about to read 6, iclass 29, count 0 2006.203.08:06:03.18#ibcon#read 6, iclass 29, count 0 2006.203.08:06:03.18#ibcon#end of sib2, iclass 29, count 0 2006.203.08:06:03.18#ibcon#*mode == 0, iclass 29, count 0 2006.203.08:06:03.18#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.203.08:06:03.18#ibcon#[28=FRQ=06,752.99\r\n] 2006.203.08:06:03.18#ibcon#*before write, iclass 29, count 0 2006.203.08:06:03.18#ibcon#enter sib2, iclass 29, count 0 2006.203.08:06:03.18#ibcon#flushed, iclass 29, count 0 2006.203.08:06:03.18#ibcon#about to write, iclass 29, count 0 2006.203.08:06:03.18#ibcon#wrote, iclass 29, count 0 2006.203.08:06:03.18#ibcon#about to read 3, iclass 29, count 0 2006.203.08:06:03.22#ibcon#read 3, iclass 29, count 0 2006.203.08:06:03.22#ibcon#about to read 4, iclass 29, count 0 2006.203.08:06:03.22#ibcon#read 4, iclass 29, count 0 2006.203.08:06:03.22#ibcon#about to read 5, iclass 29, count 0 2006.203.08:06:03.22#ibcon#read 5, iclass 29, count 0 2006.203.08:06:03.22#ibcon#about to read 6, iclass 29, count 0 2006.203.08:06:03.22#ibcon#read 6, iclass 29, count 0 2006.203.08:06:03.22#ibcon#end of sib2, iclass 29, count 0 2006.203.08:06:03.22#ibcon#*after write, iclass 29, count 0 2006.203.08:06:03.22#ibcon#*before return 0, iclass 29, count 0 2006.203.08:06:03.22#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.203.08:06:03.22#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.203.08:06:03.22#ibcon#about to clear, iclass 29 cls_cnt 0 2006.203.08:06:03.22#ibcon#cleared, iclass 29 cls_cnt 0 2006.203.08:06:03.22$vc4f8/vb=6,4 2006.203.08:06:03.22#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.203.08:06:03.22#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.203.08:06:03.22#ibcon#ireg 11 cls_cnt 2 2006.203.08:06:03.22#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.203.08:06:03.28#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.203.08:06:03.28#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.203.08:06:03.28#ibcon#enter wrdev, iclass 31, count 2 2006.203.08:06:03.28#ibcon#first serial, iclass 31, count 2 2006.203.08:06:03.28#ibcon#enter sib2, iclass 31, count 2 2006.203.08:06:03.28#ibcon#flushed, iclass 31, count 2 2006.203.08:06:03.28#ibcon#about to write, iclass 31, count 2 2006.203.08:06:03.28#ibcon#wrote, iclass 31, count 2 2006.203.08:06:03.28#ibcon#about to read 3, iclass 31, count 2 2006.203.08:06:03.30#ibcon#read 3, iclass 31, count 2 2006.203.08:06:03.30#ibcon#about to read 4, iclass 31, count 2 2006.203.08:06:03.30#ibcon#read 4, iclass 31, count 2 2006.203.08:06:03.30#ibcon#about to read 5, iclass 31, count 2 2006.203.08:06:03.30#ibcon#read 5, iclass 31, count 2 2006.203.08:06:03.30#ibcon#about to read 6, iclass 31, count 2 2006.203.08:06:03.30#ibcon#read 6, iclass 31, count 2 2006.203.08:06:03.30#ibcon#end of sib2, iclass 31, count 2 2006.203.08:06:03.30#ibcon#*mode == 0, iclass 31, count 2 2006.203.08:06:03.30#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.203.08:06:03.30#ibcon#[27=AT06-04\r\n] 2006.203.08:06:03.30#ibcon#*before write, iclass 31, count 2 2006.203.08:06:03.30#ibcon#enter sib2, iclass 31, count 2 2006.203.08:06:03.30#ibcon#flushed, iclass 31, count 2 2006.203.08:06:03.30#ibcon#about to write, iclass 31, count 2 2006.203.08:06:03.30#ibcon#wrote, iclass 31, count 2 2006.203.08:06:03.30#ibcon#about to read 3, iclass 31, count 2 2006.203.08:06:03.33#ibcon#read 3, iclass 31, count 2 2006.203.08:06:03.33#ibcon#about to read 4, iclass 31, count 2 2006.203.08:06:03.33#ibcon#read 4, iclass 31, count 2 2006.203.08:06:03.33#ibcon#about to read 5, iclass 31, count 2 2006.203.08:06:03.33#ibcon#read 5, iclass 31, count 2 2006.203.08:06:03.33#ibcon#about to read 6, iclass 31, count 2 2006.203.08:06:03.33#ibcon#read 6, iclass 31, count 2 2006.203.08:06:03.33#ibcon#end of sib2, iclass 31, count 2 2006.203.08:06:03.33#ibcon#*after write, iclass 31, count 2 2006.203.08:06:03.33#ibcon#*before return 0, iclass 31, count 2 2006.203.08:06:03.33#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.203.08:06:03.33#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.203.08:06:03.33#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.203.08:06:03.33#ibcon#ireg 7 cls_cnt 0 2006.203.08:06:03.33#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.203.08:06:03.45#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.203.08:06:03.45#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.203.08:06:03.45#ibcon#enter wrdev, iclass 31, count 0 2006.203.08:06:03.45#ibcon#first serial, iclass 31, count 0 2006.203.08:06:03.45#ibcon#enter sib2, iclass 31, count 0 2006.203.08:06:03.45#ibcon#flushed, iclass 31, count 0 2006.203.08:06:03.45#ibcon#about to write, iclass 31, count 0 2006.203.08:06:03.45#ibcon#wrote, iclass 31, count 0 2006.203.08:06:03.45#ibcon#about to read 3, iclass 31, count 0 2006.203.08:06:03.47#ibcon#read 3, iclass 31, count 0 2006.203.08:06:03.47#ibcon#about to read 4, iclass 31, count 0 2006.203.08:06:03.47#ibcon#read 4, iclass 31, count 0 2006.203.08:06:03.47#ibcon#about to read 5, iclass 31, count 0 2006.203.08:06:03.47#ibcon#read 5, iclass 31, count 0 2006.203.08:06:03.47#ibcon#about to read 6, iclass 31, count 0 2006.203.08:06:03.47#ibcon#read 6, iclass 31, count 0 2006.203.08:06:03.47#ibcon#end of sib2, iclass 31, count 0 2006.203.08:06:03.47#ibcon#*mode == 0, iclass 31, count 0 2006.203.08:06:03.47#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.203.08:06:03.47#ibcon#[27=USB\r\n] 2006.203.08:06:03.47#ibcon#*before write, iclass 31, count 0 2006.203.08:06:03.47#ibcon#enter sib2, iclass 31, count 0 2006.203.08:06:03.47#ibcon#flushed, iclass 31, count 0 2006.203.08:06:03.47#ibcon#about to write, iclass 31, count 0 2006.203.08:06:03.47#ibcon#wrote, iclass 31, count 0 2006.203.08:06:03.47#ibcon#about to read 3, iclass 31, count 0 2006.203.08:06:03.50#ibcon#read 3, iclass 31, count 0 2006.203.08:06:03.50#ibcon#about to read 4, iclass 31, count 0 2006.203.08:06:03.50#ibcon#read 4, iclass 31, count 0 2006.203.08:06:03.50#ibcon#about to read 5, iclass 31, count 0 2006.203.08:06:03.50#ibcon#read 5, iclass 31, count 0 2006.203.08:06:03.50#ibcon#about to read 6, iclass 31, count 0 2006.203.08:06:03.50#ibcon#read 6, iclass 31, count 0 2006.203.08:06:03.50#ibcon#end of sib2, iclass 31, count 0 2006.203.08:06:03.50#ibcon#*after write, iclass 31, count 0 2006.203.08:06:03.50#ibcon#*before return 0, iclass 31, count 0 2006.203.08:06:03.50#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.203.08:06:03.50#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.203.08:06:03.50#ibcon#about to clear, iclass 31 cls_cnt 0 2006.203.08:06:03.50#ibcon#cleared, iclass 31 cls_cnt 0 2006.203.08:06:03.50$vc4f8/vabw=wide 2006.203.08:06:03.50#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.203.08:06:03.50#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.203.08:06:03.50#ibcon#ireg 8 cls_cnt 0 2006.203.08:06:03.50#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.203.08:06:03.50#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.203.08:06:03.50#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.203.08:06:03.50#ibcon#enter wrdev, iclass 33, count 0 2006.203.08:06:03.50#ibcon#first serial, iclass 33, count 0 2006.203.08:06:03.50#ibcon#enter sib2, iclass 33, count 0 2006.203.08:06:03.50#ibcon#flushed, iclass 33, count 0 2006.203.08:06:03.50#ibcon#about to write, iclass 33, count 0 2006.203.08:06:03.50#ibcon#wrote, iclass 33, count 0 2006.203.08:06:03.50#ibcon#about to read 3, iclass 33, count 0 2006.203.08:06:03.52#ibcon#read 3, iclass 33, count 0 2006.203.08:06:03.52#ibcon#about to read 4, iclass 33, count 0 2006.203.08:06:03.52#ibcon#read 4, iclass 33, count 0 2006.203.08:06:03.52#ibcon#about to read 5, iclass 33, count 0 2006.203.08:06:03.52#ibcon#read 5, iclass 33, count 0 2006.203.08:06:03.52#ibcon#about to read 6, iclass 33, count 0 2006.203.08:06:03.52#ibcon#read 6, iclass 33, count 0 2006.203.08:06:03.52#ibcon#end of sib2, iclass 33, count 0 2006.203.08:06:03.52#ibcon#*mode == 0, iclass 33, count 0 2006.203.08:06:03.52#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.203.08:06:03.52#ibcon#[25=BW32\r\n] 2006.203.08:06:03.52#ibcon#*before write, iclass 33, count 0 2006.203.08:06:03.52#ibcon#enter sib2, iclass 33, count 0 2006.203.08:06:03.52#ibcon#flushed, iclass 33, count 0 2006.203.08:06:03.52#ibcon#about to write, iclass 33, count 0 2006.203.08:06:03.52#ibcon#wrote, iclass 33, count 0 2006.203.08:06:03.52#ibcon#about to read 3, iclass 33, count 0 2006.203.08:06:03.55#ibcon#read 3, iclass 33, count 0 2006.203.08:06:03.55#ibcon#about to read 4, iclass 33, count 0 2006.203.08:06:03.55#ibcon#read 4, iclass 33, count 0 2006.203.08:06:03.55#ibcon#about to read 5, iclass 33, count 0 2006.203.08:06:03.55#ibcon#read 5, iclass 33, count 0 2006.203.08:06:03.55#ibcon#about to read 6, iclass 33, count 0 2006.203.08:06:03.55#ibcon#read 6, iclass 33, count 0 2006.203.08:06:03.55#ibcon#end of sib2, iclass 33, count 0 2006.203.08:06:03.55#ibcon#*after write, iclass 33, count 0 2006.203.08:06:03.55#ibcon#*before return 0, iclass 33, count 0 2006.203.08:06:03.55#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.203.08:06:03.55#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.203.08:06:03.55#ibcon#about to clear, iclass 33 cls_cnt 0 2006.203.08:06:03.55#ibcon#cleared, iclass 33 cls_cnt 0 2006.203.08:06:03.55$vc4f8/vbbw=wide 2006.203.08:06:03.55#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.203.08:06:03.55#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.203.08:06:03.55#ibcon#ireg 8 cls_cnt 0 2006.203.08:06:03.55#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.203.08:06:03.62#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.203.08:06:03.62#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.203.08:06:03.62#ibcon#enter wrdev, iclass 35, count 0 2006.203.08:06:03.62#ibcon#first serial, iclass 35, count 0 2006.203.08:06:03.62#ibcon#enter sib2, iclass 35, count 0 2006.203.08:06:03.62#ibcon#flushed, iclass 35, count 0 2006.203.08:06:03.62#ibcon#about to write, iclass 35, count 0 2006.203.08:06:03.62#ibcon#wrote, iclass 35, count 0 2006.203.08:06:03.62#ibcon#about to read 3, iclass 35, count 0 2006.203.08:06:03.64#ibcon#read 3, iclass 35, count 0 2006.203.08:06:03.64#ibcon#about to read 4, iclass 35, count 0 2006.203.08:06:03.64#ibcon#read 4, iclass 35, count 0 2006.203.08:06:03.64#ibcon#about to read 5, iclass 35, count 0 2006.203.08:06:03.64#ibcon#read 5, iclass 35, count 0 2006.203.08:06:03.64#ibcon#about to read 6, iclass 35, count 0 2006.203.08:06:03.64#ibcon#read 6, iclass 35, count 0 2006.203.08:06:03.64#ibcon#end of sib2, iclass 35, count 0 2006.203.08:06:03.64#ibcon#*mode == 0, iclass 35, count 0 2006.203.08:06:03.64#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.203.08:06:03.64#ibcon#[27=BW32\r\n] 2006.203.08:06:03.64#ibcon#*before write, iclass 35, count 0 2006.203.08:06:03.64#ibcon#enter sib2, iclass 35, count 0 2006.203.08:06:03.64#ibcon#flushed, iclass 35, count 0 2006.203.08:06:03.64#ibcon#about to write, iclass 35, count 0 2006.203.08:06:03.64#ibcon#wrote, iclass 35, count 0 2006.203.08:06:03.64#ibcon#about to read 3, iclass 35, count 0 2006.203.08:06:03.67#ibcon#read 3, iclass 35, count 0 2006.203.08:06:03.67#ibcon#about to read 4, iclass 35, count 0 2006.203.08:06:03.67#ibcon#read 4, iclass 35, count 0 2006.203.08:06:03.67#ibcon#about to read 5, iclass 35, count 0 2006.203.08:06:03.67#ibcon#read 5, iclass 35, count 0 2006.203.08:06:03.67#ibcon#about to read 6, iclass 35, count 0 2006.203.08:06:03.67#ibcon#read 6, iclass 35, count 0 2006.203.08:06:03.67#ibcon#end of sib2, iclass 35, count 0 2006.203.08:06:03.67#ibcon#*after write, iclass 35, count 0 2006.203.08:06:03.67#ibcon#*before return 0, iclass 35, count 0 2006.203.08:06:03.67#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.203.08:06:03.67#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.203.08:06:03.67#ibcon#about to clear, iclass 35 cls_cnt 0 2006.203.08:06:03.67#ibcon#cleared, iclass 35 cls_cnt 0 2006.203.08:06:03.67$4f8m12a/ifd4f 2006.203.08:06:03.67$ifd4f/lo= 2006.203.08:06:03.67$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.203.08:06:03.67$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.203.08:06:03.67$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.203.08:06:03.67$ifd4f/patch= 2006.203.08:06:03.67$ifd4f/patch=lo1,a1,a2,a3,a4 2006.203.08:06:03.67$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.203.08:06:03.67$ifd4f/patch=lo3,a5,a6,a7,a8 2006.203.08:06:03.67$4f8m12a/"form=m,16.000,1:2 2006.203.08:06:03.67$4f8m12a/"tpicd 2006.203.08:06:03.67$4f8m12a/echo=off 2006.203.08:06:03.67$4f8m12a/xlog=off 2006.203.08:06:03.67:!2006.203.08:06:30 2006.203.08:06:11.14#trakl#Source acquired 2006.203.08:06:12.14#flagr#flagr/antenna,acquired 2006.203.08:06:30.02:preob 2006.203.08:06:31.14/onsource/TRACKING 2006.203.08:06:31.14:!2006.203.08:06:40 2006.203.08:06:40.02:data_valid=on 2006.203.08:06:40.02:midob 2006.203.08:06:41.14/onsource/TRACKING 2006.203.08:06:41.14/wx/23.68,1001.1,100 2006.203.08:06:41.30/cable/+6.4607E-03 2006.203.08:06:42.39/va/01,08,usb,yes,32,33 2006.203.08:06:42.39/va/02,07,usb,yes,32,33 2006.203.08:06:42.39/va/03,08,usb,yes,24,24 2006.203.08:06:42.39/va/04,07,usb,yes,33,35 2006.203.08:06:42.39/va/05,07,usb,yes,36,38 2006.203.08:06:42.39/va/06,06,usb,yes,35,35 2006.203.08:06:42.39/va/07,07,usb,yes,31,31 2006.203.08:06:42.39/va/08,06,usb,yes,38,37 2006.203.08:06:42.62/valo/01,532.99,yes,locked 2006.203.08:06:42.62/valo/02,572.99,yes,locked 2006.203.08:06:42.62/valo/03,672.99,yes,locked 2006.203.08:06:42.62/valo/04,832.99,yes,locked 2006.203.08:06:42.62/valo/05,652.99,yes,locked 2006.203.08:06:42.62/valo/06,772.99,yes,locked 2006.203.08:06:42.62/valo/07,832.99,yes,locked 2006.203.08:06:42.62/valo/08,852.99,yes,locked 2006.203.08:06:43.71/vb/01,04,usb,yes,30,28 2006.203.08:06:43.71/vb/02,04,usb,yes,32,33 2006.203.08:06:43.71/vb/03,04,usb,yes,28,32 2006.203.08:06:43.71/vb/04,04,usb,yes,29,29 2006.203.08:06:43.71/vb/05,03,usb,yes,34,39 2006.203.08:06:43.71/vb/06,04,usb,yes,28,31 2006.203.08:06:43.71/vb/07,04,usb,yes,30,31 2006.203.08:06:43.71/vb/08,04,usb,yes,28,31 2006.203.08:06:43.94/vblo/01,632.99,yes,locked 2006.203.08:06:43.94/vblo/02,640.99,yes,locked 2006.203.08:06:43.94/vblo/03,656.99,yes,locked 2006.203.08:06:43.94/vblo/04,712.99,yes,locked 2006.203.08:06:43.94/vblo/05,744.99,yes,locked 2006.203.08:06:43.94/vblo/06,752.99,yes,locked 2006.203.08:06:43.94/vblo/07,734.99,yes,locked 2006.203.08:06:43.94/vblo/08,744.99,yes,locked 2006.203.08:06:44.09/vabw/8 2006.203.08:06:44.24/vbbw/8 2006.203.08:06:44.33/xfe/off,on,12.5 2006.203.08:06:44.71/ifatt/23,28,28,28 2006.203.08:06:45.08/fmout-gps/S +4.56E-07 2006.203.08:06:45.15:!2006.203.08:07:40 2006.203.08:07:40.02:data_valid=off 2006.203.08:07:40.02:postob 2006.203.08:07:40.23/cable/+6.4597E-03 2006.203.08:07:40.23/wx/23.68,1001.1,100 2006.203.08:07:41.07/fmout-gps/S +4.56E-07 2006.203.08:07:41.08:scan_name=203-0808,k06203,60 2006.203.08:07:41.08:source=1739+522,174036.98,521143.4,2000.0,cw 2006.203.08:07:42.15#flagr#flagr/antenna,new-source 2006.203.08:07:42.15:checkk5 2006.203.08:07:42.81/chk_autoobs//k5ts1/ autoobs is running! 2006.203.08:07:43.21/chk_autoobs//k5ts2/ autoobs is running! 2006.203.08:07:43.58/chk_autoobs//k5ts3/ autoobs is running! 2006.203.08:07:44.00/chk_autoobs//k5ts4/ autoobs is running! 2006.203.08:07:44.64/chk_obsdata//k5ts1/T2030806??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.08:07:45.05/chk_obsdata//k5ts2/T2030806??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.08:07:45.45/chk_obsdata//k5ts3/T2030806??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.08:07:45.85/chk_obsdata//k5ts4/T2030806??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.08:07:46.63/k5log//k5ts1_log_newline 2006.203.08:07:47.46/k5log//k5ts2_log_newline 2006.203.08:07:48.24/k5log//k5ts3_log_newline 2006.203.08:07:49.03/k5log//k5ts4_log_newline 2006.203.08:07:49.05/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.203.08:07:49.05:4f8m12a=2 2006.203.08:07:49.06$4f8m12a/echo=on 2006.203.08:07:49.06$4f8m12a/pcalon 2006.203.08:07:49.06$pcalon/"no phase cal control is implemented here 2006.203.08:07:49.06$4f8m12a/"tpicd=stop 2006.203.08:07:49.06$4f8m12a/vc4f8 2006.203.08:07:49.06$vc4f8/valo=1,532.99 2006.203.08:07:49.10#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.203.08:07:49.10#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.203.08:07:49.10#ibcon#ireg 17 cls_cnt 0 2006.203.08:07:49.10#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.203.08:07:49.10#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.203.08:07:49.10#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.203.08:07:49.10#ibcon#enter wrdev, iclass 4, count 0 2006.203.08:07:49.10#ibcon#first serial, iclass 4, count 0 2006.203.08:07:49.10#ibcon#enter sib2, iclass 4, count 0 2006.203.08:07:49.10#ibcon#flushed, iclass 4, count 0 2006.203.08:07:49.10#ibcon#about to write, iclass 4, count 0 2006.203.08:07:49.10#ibcon#wrote, iclass 4, count 0 2006.203.08:07:49.10#ibcon#about to read 3, iclass 4, count 0 2006.203.08:07:49.11#ibcon#read 3, iclass 4, count 0 2006.203.08:07:49.11#ibcon#about to read 4, iclass 4, count 0 2006.203.08:07:49.11#ibcon#read 4, iclass 4, count 0 2006.203.08:07:49.11#ibcon#about to read 5, iclass 4, count 0 2006.203.08:07:49.11#ibcon#read 5, iclass 4, count 0 2006.203.08:07:49.11#ibcon#about to read 6, iclass 4, count 0 2006.203.08:07:49.11#ibcon#read 6, iclass 4, count 0 2006.203.08:07:49.11#ibcon#end of sib2, iclass 4, count 0 2006.203.08:07:49.11#ibcon#*mode == 0, iclass 4, count 0 2006.203.08:07:49.12#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.203.08:07:49.12#ibcon#[26=FRQ=01,532.99\r\n] 2006.203.08:07:49.12#ibcon#*before write, iclass 4, count 0 2006.203.08:07:49.12#ibcon#enter sib2, iclass 4, count 0 2006.203.08:07:49.12#ibcon#flushed, iclass 4, count 0 2006.203.08:07:49.12#ibcon#about to write, iclass 4, count 0 2006.203.08:07:49.12#ibcon#wrote, iclass 4, count 0 2006.203.08:07:49.12#ibcon#about to read 3, iclass 4, count 0 2006.203.08:07:49.17#ibcon#read 3, iclass 4, count 0 2006.203.08:07:49.17#ibcon#about to read 4, iclass 4, count 0 2006.203.08:07:49.17#ibcon#read 4, iclass 4, count 0 2006.203.08:07:49.17#ibcon#about to read 5, iclass 4, count 0 2006.203.08:07:49.17#ibcon#read 5, iclass 4, count 0 2006.203.08:07:49.17#ibcon#about to read 6, iclass 4, count 0 2006.203.08:07:49.17#ibcon#read 6, iclass 4, count 0 2006.203.08:07:49.17#ibcon#end of sib2, iclass 4, count 0 2006.203.08:07:49.17#ibcon#*after write, iclass 4, count 0 2006.203.08:07:49.17#ibcon#*before return 0, iclass 4, count 0 2006.203.08:07:49.17#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.203.08:07:49.17#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.203.08:07:49.17#ibcon#about to clear, iclass 4 cls_cnt 0 2006.203.08:07:49.17#ibcon#cleared, iclass 4 cls_cnt 0 2006.203.08:07:49.17$vc4f8/va=1,8 2006.203.08:07:49.17#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.203.08:07:49.17#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.203.08:07:49.17#ibcon#ireg 11 cls_cnt 2 2006.203.08:07:49.17#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.203.08:07:49.17#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.203.08:07:49.17#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.203.08:07:49.17#ibcon#enter wrdev, iclass 6, count 2 2006.203.08:07:49.17#ibcon#first serial, iclass 6, count 2 2006.203.08:07:49.17#ibcon#enter sib2, iclass 6, count 2 2006.203.08:07:49.17#ibcon#flushed, iclass 6, count 2 2006.203.08:07:49.17#ibcon#about to write, iclass 6, count 2 2006.203.08:07:49.17#ibcon#wrote, iclass 6, count 2 2006.203.08:07:49.17#ibcon#about to read 3, iclass 6, count 2 2006.203.08:07:49.19#ibcon#read 3, iclass 6, count 2 2006.203.08:07:49.19#ibcon#about to read 4, iclass 6, count 2 2006.203.08:07:49.19#ibcon#read 4, iclass 6, count 2 2006.203.08:07:49.19#ibcon#about to read 5, iclass 6, count 2 2006.203.08:07:49.19#ibcon#read 5, iclass 6, count 2 2006.203.08:07:49.19#ibcon#about to read 6, iclass 6, count 2 2006.203.08:07:49.19#ibcon#read 6, iclass 6, count 2 2006.203.08:07:49.19#ibcon#end of sib2, iclass 6, count 2 2006.203.08:07:49.19#ibcon#*mode == 0, iclass 6, count 2 2006.203.08:07:49.19#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.203.08:07:49.19#ibcon#[25=AT01-08\r\n] 2006.203.08:07:49.19#ibcon#*before write, iclass 6, count 2 2006.203.08:07:49.19#ibcon#enter sib2, iclass 6, count 2 2006.203.08:07:49.19#ibcon#flushed, iclass 6, count 2 2006.203.08:07:49.19#ibcon#about to write, iclass 6, count 2 2006.203.08:07:49.19#ibcon#wrote, iclass 6, count 2 2006.203.08:07:49.19#ibcon#about to read 3, iclass 6, count 2 2006.203.08:07:49.21#ibcon#read 3, iclass 6, count 2 2006.203.08:07:49.21#ibcon#about to read 4, iclass 6, count 2 2006.203.08:07:49.21#ibcon#read 4, iclass 6, count 2 2006.203.08:07:49.21#ibcon#about to read 5, iclass 6, count 2 2006.203.08:07:49.21#ibcon#read 5, iclass 6, count 2 2006.203.08:07:49.21#ibcon#about to read 6, iclass 6, count 2 2006.203.08:07:49.21#ibcon#read 6, iclass 6, count 2 2006.203.08:07:49.21#ibcon#end of sib2, iclass 6, count 2 2006.203.08:07:49.21#ibcon#*after write, iclass 6, count 2 2006.203.08:07:49.22#ibcon#*before return 0, iclass 6, count 2 2006.203.08:07:49.22#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.203.08:07:49.22#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.203.08:07:49.22#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.203.08:07:49.22#ibcon#ireg 7 cls_cnt 0 2006.203.08:07:49.22#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.203.08:07:49.33#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.203.08:07:49.33#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.203.08:07:49.33#ibcon#enter wrdev, iclass 6, count 0 2006.203.08:07:49.33#ibcon#first serial, iclass 6, count 0 2006.203.08:07:49.33#ibcon#enter sib2, iclass 6, count 0 2006.203.08:07:49.33#ibcon#flushed, iclass 6, count 0 2006.203.08:07:49.33#ibcon#about to write, iclass 6, count 0 2006.203.08:07:49.33#ibcon#wrote, iclass 6, count 0 2006.203.08:07:49.33#ibcon#about to read 3, iclass 6, count 0 2006.203.08:07:49.35#ibcon#read 3, iclass 6, count 0 2006.203.08:07:49.35#ibcon#about to read 4, iclass 6, count 0 2006.203.08:07:49.35#ibcon#read 4, iclass 6, count 0 2006.203.08:07:49.35#ibcon#about to read 5, iclass 6, count 0 2006.203.08:07:49.35#ibcon#read 5, iclass 6, count 0 2006.203.08:07:49.35#ibcon#about to read 6, iclass 6, count 0 2006.203.08:07:49.35#ibcon#read 6, iclass 6, count 0 2006.203.08:07:49.35#ibcon#end of sib2, iclass 6, count 0 2006.203.08:07:49.35#ibcon#*mode == 0, iclass 6, count 0 2006.203.08:07:49.35#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.203.08:07:49.35#ibcon#[25=USB\r\n] 2006.203.08:07:49.35#ibcon#*before write, iclass 6, count 0 2006.203.08:07:49.35#ibcon#enter sib2, iclass 6, count 0 2006.203.08:07:49.36#ibcon#flushed, iclass 6, count 0 2006.203.08:07:49.36#ibcon#about to write, iclass 6, count 0 2006.203.08:07:49.36#ibcon#wrote, iclass 6, count 0 2006.203.08:07:49.36#ibcon#about to read 3, iclass 6, count 0 2006.203.08:07:49.38#ibcon#read 3, iclass 6, count 0 2006.203.08:07:49.38#ibcon#about to read 4, iclass 6, count 0 2006.203.08:07:49.38#ibcon#read 4, iclass 6, count 0 2006.203.08:07:49.38#ibcon#about to read 5, iclass 6, count 0 2006.203.08:07:49.38#ibcon#read 5, iclass 6, count 0 2006.203.08:07:49.38#ibcon#about to read 6, iclass 6, count 0 2006.203.08:07:49.38#ibcon#read 6, iclass 6, count 0 2006.203.08:07:49.38#ibcon#end of sib2, iclass 6, count 0 2006.203.08:07:49.38#ibcon#*after write, iclass 6, count 0 2006.203.08:07:49.38#ibcon#*before return 0, iclass 6, count 0 2006.203.08:07:49.38#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.203.08:07:49.38#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.203.08:07:49.39#ibcon#about to clear, iclass 6 cls_cnt 0 2006.203.08:07:49.39#ibcon#cleared, iclass 6 cls_cnt 0 2006.203.08:07:49.39$vc4f8/valo=2,572.99 2006.203.08:07:49.39#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.203.08:07:49.39#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.203.08:07:49.39#ibcon#ireg 17 cls_cnt 0 2006.203.08:07:49.39#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.203.08:07:49.39#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.203.08:07:49.39#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.203.08:07:49.39#ibcon#enter wrdev, iclass 10, count 0 2006.203.08:07:49.39#ibcon#first serial, iclass 10, count 0 2006.203.08:07:49.39#ibcon#enter sib2, iclass 10, count 0 2006.203.08:07:49.39#ibcon#flushed, iclass 10, count 0 2006.203.08:07:49.39#ibcon#about to write, iclass 10, count 0 2006.203.08:07:49.39#ibcon#wrote, iclass 10, count 0 2006.203.08:07:49.39#ibcon#about to read 3, iclass 10, count 0 2006.203.08:07:49.41#ibcon#read 3, iclass 10, count 0 2006.203.08:07:49.41#ibcon#about to read 4, iclass 10, count 0 2006.203.08:07:49.41#ibcon#read 4, iclass 10, count 0 2006.203.08:07:49.41#ibcon#about to read 5, iclass 10, count 0 2006.203.08:07:49.41#ibcon#read 5, iclass 10, count 0 2006.203.08:07:49.41#ibcon#about to read 6, iclass 10, count 0 2006.203.08:07:49.41#ibcon#read 6, iclass 10, count 0 2006.203.08:07:49.41#ibcon#end of sib2, iclass 10, count 0 2006.203.08:07:49.41#ibcon#*mode == 0, iclass 10, count 0 2006.203.08:07:49.41#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.203.08:07:49.41#ibcon#[26=FRQ=02,572.99\r\n] 2006.203.08:07:49.41#ibcon#*before write, iclass 10, count 0 2006.203.08:07:49.41#ibcon#enter sib2, iclass 10, count 0 2006.203.08:07:49.41#ibcon#flushed, iclass 10, count 0 2006.203.08:07:49.41#ibcon#about to write, iclass 10, count 0 2006.203.08:07:49.41#ibcon#wrote, iclass 10, count 0 2006.203.08:07:49.41#ibcon#about to read 3, iclass 10, count 0 2006.203.08:07:49.45#ibcon#read 3, iclass 10, count 0 2006.203.08:07:49.45#ibcon#about to read 4, iclass 10, count 0 2006.203.08:07:49.45#ibcon#read 4, iclass 10, count 0 2006.203.08:07:49.45#ibcon#about to read 5, iclass 10, count 0 2006.203.08:07:49.45#ibcon#read 5, iclass 10, count 0 2006.203.08:07:49.45#ibcon#about to read 6, iclass 10, count 0 2006.203.08:07:49.45#ibcon#read 6, iclass 10, count 0 2006.203.08:07:49.45#ibcon#end of sib2, iclass 10, count 0 2006.203.08:07:49.45#ibcon#*after write, iclass 10, count 0 2006.203.08:07:49.45#ibcon#*before return 0, iclass 10, count 0 2006.203.08:07:49.46#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.203.08:07:49.46#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.203.08:07:49.46#ibcon#about to clear, iclass 10 cls_cnt 0 2006.203.08:07:49.46#ibcon#cleared, iclass 10 cls_cnt 0 2006.203.08:07:49.46$vc4f8/va=2,7 2006.203.08:07:49.46#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.203.08:07:49.46#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.203.08:07:49.46#ibcon#ireg 11 cls_cnt 2 2006.203.08:07:49.46#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.203.08:07:49.49#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.203.08:07:49.49#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.203.08:07:49.49#ibcon#enter wrdev, iclass 12, count 2 2006.203.08:07:49.49#ibcon#first serial, iclass 12, count 2 2006.203.08:07:49.49#ibcon#enter sib2, iclass 12, count 2 2006.203.08:07:49.49#ibcon#flushed, iclass 12, count 2 2006.203.08:07:49.49#ibcon#about to write, iclass 12, count 2 2006.203.08:07:49.49#ibcon#wrote, iclass 12, count 2 2006.203.08:07:49.49#ibcon#about to read 3, iclass 12, count 2 2006.203.08:07:49.51#ibcon#read 3, iclass 12, count 2 2006.203.08:07:49.51#ibcon#about to read 4, iclass 12, count 2 2006.203.08:07:49.51#ibcon#read 4, iclass 12, count 2 2006.203.08:07:49.52#ibcon#about to read 5, iclass 12, count 2 2006.203.08:07:49.52#ibcon#read 5, iclass 12, count 2 2006.203.08:07:49.52#ibcon#about to read 6, iclass 12, count 2 2006.203.08:07:49.52#ibcon#read 6, iclass 12, count 2 2006.203.08:07:49.52#ibcon#end of sib2, iclass 12, count 2 2006.203.08:07:49.52#ibcon#*mode == 0, iclass 12, count 2 2006.203.08:07:49.52#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.203.08:07:49.52#ibcon#[25=AT02-07\r\n] 2006.203.08:07:49.52#ibcon#*before write, iclass 12, count 2 2006.203.08:07:49.52#ibcon#enter sib2, iclass 12, count 2 2006.203.08:07:49.52#ibcon#flushed, iclass 12, count 2 2006.203.08:07:49.52#ibcon#about to write, iclass 12, count 2 2006.203.08:07:49.52#ibcon#wrote, iclass 12, count 2 2006.203.08:07:49.52#ibcon#about to read 3, iclass 12, count 2 2006.203.08:07:49.54#ibcon#read 3, iclass 12, count 2 2006.203.08:07:49.54#ibcon#about to read 4, iclass 12, count 2 2006.203.08:07:49.54#ibcon#read 4, iclass 12, count 2 2006.203.08:07:49.54#ibcon#about to read 5, iclass 12, count 2 2006.203.08:07:49.54#ibcon#read 5, iclass 12, count 2 2006.203.08:07:49.54#ibcon#about to read 6, iclass 12, count 2 2006.203.08:07:49.54#ibcon#read 6, iclass 12, count 2 2006.203.08:07:49.54#ibcon#end of sib2, iclass 12, count 2 2006.203.08:07:49.55#ibcon#*after write, iclass 12, count 2 2006.203.08:07:49.55#ibcon#*before return 0, iclass 12, count 2 2006.203.08:07:49.55#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.203.08:07:49.55#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.203.08:07:49.55#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.203.08:07:49.55#ibcon#ireg 7 cls_cnt 0 2006.203.08:07:49.55#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.203.08:07:49.66#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.203.08:07:49.66#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.203.08:07:49.66#ibcon#enter wrdev, iclass 12, count 0 2006.203.08:07:49.66#ibcon#first serial, iclass 12, count 0 2006.203.08:07:49.66#ibcon#enter sib2, iclass 12, count 0 2006.203.08:07:49.66#ibcon#flushed, iclass 12, count 0 2006.203.08:07:49.66#ibcon#about to write, iclass 12, count 0 2006.203.08:07:49.66#ibcon#wrote, iclass 12, count 0 2006.203.08:07:49.66#ibcon#about to read 3, iclass 12, count 0 2006.203.08:07:49.68#ibcon#read 3, iclass 12, count 0 2006.203.08:07:49.68#ibcon#about to read 4, iclass 12, count 0 2006.203.08:07:49.68#ibcon#read 4, iclass 12, count 0 2006.203.08:07:49.68#ibcon#about to read 5, iclass 12, count 0 2006.203.08:07:49.68#ibcon#read 5, iclass 12, count 0 2006.203.08:07:49.68#ibcon#about to read 6, iclass 12, count 0 2006.203.08:07:49.68#ibcon#read 6, iclass 12, count 0 2006.203.08:07:49.68#ibcon#end of sib2, iclass 12, count 0 2006.203.08:07:49.68#ibcon#*mode == 0, iclass 12, count 0 2006.203.08:07:49.68#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.203.08:07:49.68#ibcon#[25=USB\r\n] 2006.203.08:07:49.68#ibcon#*before write, iclass 12, count 0 2006.203.08:07:49.68#ibcon#enter sib2, iclass 12, count 0 2006.203.08:07:49.69#ibcon#flushed, iclass 12, count 0 2006.203.08:07:49.69#ibcon#about to write, iclass 12, count 0 2006.203.08:07:49.69#ibcon#wrote, iclass 12, count 0 2006.203.08:07:49.69#ibcon#about to read 3, iclass 12, count 0 2006.203.08:07:49.71#ibcon#read 3, iclass 12, count 0 2006.203.08:07:49.71#ibcon#about to read 4, iclass 12, count 0 2006.203.08:07:49.71#ibcon#read 4, iclass 12, count 0 2006.203.08:07:49.71#ibcon#about to read 5, iclass 12, count 0 2006.203.08:07:49.71#ibcon#read 5, iclass 12, count 0 2006.203.08:07:49.71#ibcon#about to read 6, iclass 12, count 0 2006.203.08:07:49.71#ibcon#read 6, iclass 12, count 0 2006.203.08:07:49.71#ibcon#end of sib2, iclass 12, count 0 2006.203.08:07:49.71#ibcon#*after write, iclass 12, count 0 2006.203.08:07:49.71#ibcon#*before return 0, iclass 12, count 0 2006.203.08:07:49.71#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.203.08:07:49.71#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.203.08:07:49.72#ibcon#about to clear, iclass 12 cls_cnt 0 2006.203.08:07:49.72#ibcon#cleared, iclass 12 cls_cnt 0 2006.203.08:07:49.72$vc4f8/valo=3,672.99 2006.203.08:07:49.72#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.203.08:07:49.72#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.203.08:07:49.72#ibcon#ireg 17 cls_cnt 0 2006.203.08:07:49.72#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.203.08:07:49.72#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.203.08:07:49.72#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.203.08:07:49.72#ibcon#enter wrdev, iclass 14, count 0 2006.203.08:07:49.72#ibcon#first serial, iclass 14, count 0 2006.203.08:07:49.72#ibcon#enter sib2, iclass 14, count 0 2006.203.08:07:49.72#ibcon#flushed, iclass 14, count 0 2006.203.08:07:49.72#ibcon#about to write, iclass 14, count 0 2006.203.08:07:49.72#ibcon#wrote, iclass 14, count 0 2006.203.08:07:49.72#ibcon#about to read 3, iclass 14, count 0 2006.203.08:07:49.74#ibcon#read 3, iclass 14, count 0 2006.203.08:07:49.74#ibcon#about to read 4, iclass 14, count 0 2006.203.08:07:49.74#ibcon#read 4, iclass 14, count 0 2006.203.08:07:49.74#ibcon#about to read 5, iclass 14, count 0 2006.203.08:07:49.74#ibcon#read 5, iclass 14, count 0 2006.203.08:07:49.74#ibcon#about to read 6, iclass 14, count 0 2006.203.08:07:49.74#ibcon#read 6, iclass 14, count 0 2006.203.08:07:49.74#ibcon#end of sib2, iclass 14, count 0 2006.203.08:07:49.74#ibcon#*mode == 0, iclass 14, count 0 2006.203.08:07:49.74#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.203.08:07:49.74#ibcon#[26=FRQ=03,672.99\r\n] 2006.203.08:07:49.74#ibcon#*before write, iclass 14, count 0 2006.203.08:07:49.74#ibcon#enter sib2, iclass 14, count 0 2006.203.08:07:49.74#ibcon#flushed, iclass 14, count 0 2006.203.08:07:49.74#ibcon#about to write, iclass 14, count 0 2006.203.08:07:49.74#ibcon#wrote, iclass 14, count 0 2006.203.08:07:49.74#ibcon#about to read 3, iclass 14, count 0 2006.203.08:07:49.78#ibcon#read 3, iclass 14, count 0 2006.203.08:07:49.78#ibcon#about to read 4, iclass 14, count 0 2006.203.08:07:49.78#ibcon#read 4, iclass 14, count 0 2006.203.08:07:49.78#ibcon#about to read 5, iclass 14, count 0 2006.203.08:07:49.78#ibcon#read 5, iclass 14, count 0 2006.203.08:07:49.78#ibcon#about to read 6, iclass 14, count 0 2006.203.08:07:49.78#ibcon#read 6, iclass 14, count 0 2006.203.08:07:49.78#ibcon#end of sib2, iclass 14, count 0 2006.203.08:07:49.78#ibcon#*after write, iclass 14, count 0 2006.203.08:07:49.79#ibcon#*before return 0, iclass 14, count 0 2006.203.08:07:49.79#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.203.08:07:49.79#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.203.08:07:49.79#ibcon#about to clear, iclass 14 cls_cnt 0 2006.203.08:07:49.79#ibcon#cleared, iclass 14 cls_cnt 0 2006.203.08:07:49.79$vc4f8/va=3,8 2006.203.08:07:49.79#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.203.08:07:49.79#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.203.08:07:49.79#ibcon#ireg 11 cls_cnt 2 2006.203.08:07:49.79#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.203.08:07:49.82#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.203.08:07:49.82#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.203.08:07:49.82#ibcon#enter wrdev, iclass 16, count 2 2006.203.08:07:49.82#ibcon#first serial, iclass 16, count 2 2006.203.08:07:49.82#ibcon#enter sib2, iclass 16, count 2 2006.203.08:07:49.82#ibcon#flushed, iclass 16, count 2 2006.203.08:07:49.82#ibcon#about to write, iclass 16, count 2 2006.203.08:07:49.82#ibcon#wrote, iclass 16, count 2 2006.203.08:07:49.82#ibcon#about to read 3, iclass 16, count 2 2006.203.08:07:49.84#ibcon#read 3, iclass 16, count 2 2006.203.08:07:49.84#ibcon#about to read 4, iclass 16, count 2 2006.203.08:07:49.84#ibcon#read 4, iclass 16, count 2 2006.203.08:07:49.85#ibcon#about to read 5, iclass 16, count 2 2006.203.08:07:49.85#ibcon#read 5, iclass 16, count 2 2006.203.08:07:49.85#ibcon#about to read 6, iclass 16, count 2 2006.203.08:07:49.85#ibcon#read 6, iclass 16, count 2 2006.203.08:07:49.85#ibcon#end of sib2, iclass 16, count 2 2006.203.08:07:49.85#ibcon#*mode == 0, iclass 16, count 2 2006.203.08:07:49.85#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.203.08:07:49.85#ibcon#[25=AT03-08\r\n] 2006.203.08:07:49.85#ibcon#*before write, iclass 16, count 2 2006.203.08:07:49.85#ibcon#enter sib2, iclass 16, count 2 2006.203.08:07:49.85#ibcon#flushed, iclass 16, count 2 2006.203.08:07:49.85#ibcon#about to write, iclass 16, count 2 2006.203.08:07:49.85#ibcon#wrote, iclass 16, count 2 2006.203.08:07:49.85#ibcon#about to read 3, iclass 16, count 2 2006.203.08:07:49.87#ibcon#read 3, iclass 16, count 2 2006.203.08:07:49.87#ibcon#about to read 4, iclass 16, count 2 2006.203.08:07:49.87#ibcon#read 4, iclass 16, count 2 2006.203.08:07:49.87#ibcon#about to read 5, iclass 16, count 2 2006.203.08:07:49.87#ibcon#read 5, iclass 16, count 2 2006.203.08:07:49.87#ibcon#about to read 6, iclass 16, count 2 2006.203.08:07:49.87#ibcon#read 6, iclass 16, count 2 2006.203.08:07:49.87#ibcon#end of sib2, iclass 16, count 2 2006.203.08:07:49.88#ibcon#*after write, iclass 16, count 2 2006.203.08:07:49.88#ibcon#*before return 0, iclass 16, count 2 2006.203.08:07:49.88#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.203.08:07:49.88#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.203.08:07:49.88#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.203.08:07:49.88#ibcon#ireg 7 cls_cnt 0 2006.203.08:07:49.88#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.203.08:07:49.99#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.203.08:07:49.99#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.203.08:07:49.99#ibcon#enter wrdev, iclass 16, count 0 2006.203.08:07:49.99#ibcon#first serial, iclass 16, count 0 2006.203.08:07:49.99#ibcon#enter sib2, iclass 16, count 0 2006.203.08:07:49.99#ibcon#flushed, iclass 16, count 0 2006.203.08:07:49.99#ibcon#about to write, iclass 16, count 0 2006.203.08:07:49.99#ibcon#wrote, iclass 16, count 0 2006.203.08:07:49.99#ibcon#about to read 3, iclass 16, count 0 2006.203.08:07:50.01#ibcon#read 3, iclass 16, count 0 2006.203.08:07:50.01#ibcon#about to read 4, iclass 16, count 0 2006.203.08:07:50.01#ibcon#read 4, iclass 16, count 0 2006.203.08:07:50.01#ibcon#about to read 5, iclass 16, count 0 2006.203.08:07:50.01#ibcon#read 5, iclass 16, count 0 2006.203.08:07:50.01#ibcon#about to read 6, iclass 16, count 0 2006.203.08:07:50.01#ibcon#read 6, iclass 16, count 0 2006.203.08:07:50.01#ibcon#end of sib2, iclass 16, count 0 2006.203.08:07:50.01#ibcon#*mode == 0, iclass 16, count 0 2006.203.08:07:50.01#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.203.08:07:50.01#ibcon#[25=USB\r\n] 2006.203.08:07:50.01#ibcon#*before write, iclass 16, count 0 2006.203.08:07:50.01#ibcon#enter sib2, iclass 16, count 0 2006.203.08:07:50.02#ibcon#flushed, iclass 16, count 0 2006.203.08:07:50.02#ibcon#about to write, iclass 16, count 0 2006.203.08:07:50.02#ibcon#wrote, iclass 16, count 0 2006.203.08:07:50.02#ibcon#about to read 3, iclass 16, count 0 2006.203.08:07:50.04#ibcon#read 3, iclass 16, count 0 2006.203.08:07:50.04#ibcon#about to read 4, iclass 16, count 0 2006.203.08:07:50.04#ibcon#read 4, iclass 16, count 0 2006.203.08:07:50.04#ibcon#about to read 5, iclass 16, count 0 2006.203.08:07:50.04#ibcon#read 5, iclass 16, count 0 2006.203.08:07:50.04#ibcon#about to read 6, iclass 16, count 0 2006.203.08:07:50.04#ibcon#read 6, iclass 16, count 0 2006.203.08:07:50.04#ibcon#end of sib2, iclass 16, count 0 2006.203.08:07:50.04#ibcon#*after write, iclass 16, count 0 2006.203.08:07:50.04#ibcon#*before return 0, iclass 16, count 0 2006.203.08:07:50.04#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.203.08:07:50.04#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.203.08:07:50.05#ibcon#about to clear, iclass 16 cls_cnt 0 2006.203.08:07:50.05#ibcon#cleared, iclass 16 cls_cnt 0 2006.203.08:07:50.05$vc4f8/valo=4,832.99 2006.203.08:07:50.05#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.203.08:07:50.05#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.203.08:07:50.05#ibcon#ireg 17 cls_cnt 0 2006.203.08:07:50.05#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.203.08:07:50.05#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.203.08:07:50.05#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.203.08:07:50.05#ibcon#enter wrdev, iclass 18, count 0 2006.203.08:07:50.05#ibcon#first serial, iclass 18, count 0 2006.203.08:07:50.05#ibcon#enter sib2, iclass 18, count 0 2006.203.08:07:50.05#ibcon#flushed, iclass 18, count 0 2006.203.08:07:50.05#ibcon#about to write, iclass 18, count 0 2006.203.08:07:50.05#ibcon#wrote, iclass 18, count 0 2006.203.08:07:50.05#ibcon#about to read 3, iclass 18, count 0 2006.203.08:07:50.07#ibcon#read 3, iclass 18, count 0 2006.203.08:07:50.07#ibcon#about to read 4, iclass 18, count 0 2006.203.08:07:50.07#ibcon#read 4, iclass 18, count 0 2006.203.08:07:50.07#ibcon#about to read 5, iclass 18, count 0 2006.203.08:07:50.07#ibcon#read 5, iclass 18, count 0 2006.203.08:07:50.07#ibcon#about to read 6, iclass 18, count 0 2006.203.08:07:50.07#ibcon#read 6, iclass 18, count 0 2006.203.08:07:50.07#ibcon#end of sib2, iclass 18, count 0 2006.203.08:07:50.07#ibcon#*mode == 0, iclass 18, count 0 2006.203.08:07:50.07#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.203.08:07:50.07#ibcon#[26=FRQ=04,832.99\r\n] 2006.203.08:07:50.07#ibcon#*before write, iclass 18, count 0 2006.203.08:07:50.07#ibcon#enter sib2, iclass 18, count 0 2006.203.08:07:50.07#ibcon#flushed, iclass 18, count 0 2006.203.08:07:50.07#ibcon#about to write, iclass 18, count 0 2006.203.08:07:50.07#ibcon#wrote, iclass 18, count 0 2006.203.08:07:50.07#ibcon#about to read 3, iclass 18, count 0 2006.203.08:07:50.11#ibcon#read 3, iclass 18, count 0 2006.203.08:07:50.11#ibcon#about to read 4, iclass 18, count 0 2006.203.08:07:50.11#ibcon#read 4, iclass 18, count 0 2006.203.08:07:50.11#ibcon#about to read 5, iclass 18, count 0 2006.203.08:07:50.11#ibcon#read 5, iclass 18, count 0 2006.203.08:07:50.11#ibcon#about to read 6, iclass 18, count 0 2006.203.08:07:50.11#ibcon#read 6, iclass 18, count 0 2006.203.08:07:50.11#ibcon#end of sib2, iclass 18, count 0 2006.203.08:07:50.11#ibcon#*after write, iclass 18, count 0 2006.203.08:07:50.12#ibcon#*before return 0, iclass 18, count 0 2006.203.08:07:50.12#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.203.08:07:50.12#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.203.08:07:50.12#ibcon#about to clear, iclass 18 cls_cnt 0 2006.203.08:07:50.12#ibcon#cleared, iclass 18 cls_cnt 0 2006.203.08:07:50.12$vc4f8/va=4,7 2006.203.08:07:50.12#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.203.08:07:50.12#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.203.08:07:50.12#ibcon#ireg 11 cls_cnt 2 2006.203.08:07:50.12#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.203.08:07:50.15#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.203.08:07:50.15#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.203.08:07:50.15#ibcon#enter wrdev, iclass 20, count 2 2006.203.08:07:50.15#ibcon#first serial, iclass 20, count 2 2006.203.08:07:50.15#ibcon#enter sib2, iclass 20, count 2 2006.203.08:07:50.15#ibcon#flushed, iclass 20, count 2 2006.203.08:07:50.15#ibcon#about to write, iclass 20, count 2 2006.203.08:07:50.15#ibcon#wrote, iclass 20, count 2 2006.203.08:07:50.15#ibcon#about to read 3, iclass 20, count 2 2006.203.08:07:50.17#ibcon#read 3, iclass 20, count 2 2006.203.08:07:50.17#ibcon#about to read 4, iclass 20, count 2 2006.203.08:07:50.17#ibcon#read 4, iclass 20, count 2 2006.203.08:07:50.17#ibcon#about to read 5, iclass 20, count 2 2006.203.08:07:50.17#ibcon#read 5, iclass 20, count 2 2006.203.08:07:50.17#ibcon#about to read 6, iclass 20, count 2 2006.203.08:07:50.17#ibcon#read 6, iclass 20, count 2 2006.203.08:07:50.17#ibcon#end of sib2, iclass 20, count 2 2006.203.08:07:50.17#ibcon#*mode == 0, iclass 20, count 2 2006.203.08:07:50.17#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.203.08:07:50.17#ibcon#[25=AT04-07\r\n] 2006.203.08:07:50.17#ibcon#*before write, iclass 20, count 2 2006.203.08:07:50.17#ibcon#enter sib2, iclass 20, count 2 2006.203.08:07:50.18#ibcon#flushed, iclass 20, count 2 2006.203.08:07:50.18#ibcon#about to write, iclass 20, count 2 2006.203.08:07:50.18#ibcon#wrote, iclass 20, count 2 2006.203.08:07:50.18#ibcon#about to read 3, iclass 20, count 2 2006.203.08:07:50.20#ibcon#read 3, iclass 20, count 2 2006.203.08:07:50.20#ibcon#about to read 4, iclass 20, count 2 2006.203.08:07:50.20#ibcon#read 4, iclass 20, count 2 2006.203.08:07:50.20#ibcon#about to read 5, iclass 20, count 2 2006.203.08:07:50.20#ibcon#read 5, iclass 20, count 2 2006.203.08:07:50.20#ibcon#about to read 6, iclass 20, count 2 2006.203.08:07:50.20#ibcon#read 6, iclass 20, count 2 2006.203.08:07:50.20#ibcon#end of sib2, iclass 20, count 2 2006.203.08:07:50.20#ibcon#*after write, iclass 20, count 2 2006.203.08:07:50.20#ibcon#*before return 0, iclass 20, count 2 2006.203.08:07:50.20#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.203.08:07:50.20#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.203.08:07:50.21#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.203.08:07:50.21#ibcon#ireg 7 cls_cnt 0 2006.203.08:07:50.21#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.203.08:07:50.31#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.203.08:07:50.31#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.203.08:07:50.31#ibcon#enter wrdev, iclass 20, count 0 2006.203.08:07:50.31#ibcon#first serial, iclass 20, count 0 2006.203.08:07:50.31#ibcon#enter sib2, iclass 20, count 0 2006.203.08:07:50.31#ibcon#flushed, iclass 20, count 0 2006.203.08:07:50.31#ibcon#about to write, iclass 20, count 0 2006.203.08:07:50.31#ibcon#wrote, iclass 20, count 0 2006.203.08:07:50.31#ibcon#about to read 3, iclass 20, count 0 2006.203.08:07:50.33#ibcon#read 3, iclass 20, count 0 2006.203.08:07:50.33#ibcon#about to read 4, iclass 20, count 0 2006.203.08:07:50.33#ibcon#read 4, iclass 20, count 0 2006.203.08:07:50.33#ibcon#about to read 5, iclass 20, count 0 2006.203.08:07:50.33#ibcon#read 5, iclass 20, count 0 2006.203.08:07:50.33#ibcon#about to read 6, iclass 20, count 0 2006.203.08:07:50.33#ibcon#read 6, iclass 20, count 0 2006.203.08:07:50.33#ibcon#end of sib2, iclass 20, count 0 2006.203.08:07:50.33#ibcon#*mode == 0, iclass 20, count 0 2006.203.08:07:50.33#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.203.08:07:50.33#ibcon#[25=USB\r\n] 2006.203.08:07:50.33#ibcon#*before write, iclass 20, count 0 2006.203.08:07:50.33#ibcon#enter sib2, iclass 20, count 0 2006.203.08:07:50.34#ibcon#flushed, iclass 20, count 0 2006.203.08:07:50.34#ibcon#about to write, iclass 20, count 0 2006.203.08:07:50.34#ibcon#wrote, iclass 20, count 0 2006.203.08:07:50.34#ibcon#about to read 3, iclass 20, count 0 2006.203.08:07:50.36#ibcon#read 3, iclass 20, count 0 2006.203.08:07:50.36#ibcon#about to read 4, iclass 20, count 0 2006.203.08:07:50.36#ibcon#read 4, iclass 20, count 0 2006.203.08:07:50.36#ibcon#about to read 5, iclass 20, count 0 2006.203.08:07:50.36#ibcon#read 5, iclass 20, count 0 2006.203.08:07:50.36#ibcon#about to read 6, iclass 20, count 0 2006.203.08:07:50.36#ibcon#read 6, iclass 20, count 0 2006.203.08:07:50.36#ibcon#end of sib2, iclass 20, count 0 2006.203.08:07:50.36#ibcon#*after write, iclass 20, count 0 2006.203.08:07:50.36#ibcon#*before return 0, iclass 20, count 0 2006.203.08:07:50.36#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.203.08:07:50.36#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.203.08:07:50.37#ibcon#about to clear, iclass 20 cls_cnt 0 2006.203.08:07:50.37#ibcon#cleared, iclass 20 cls_cnt 0 2006.203.08:07:50.37$vc4f8/valo=5,652.99 2006.203.08:07:50.37#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.203.08:07:50.37#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.203.08:07:50.37#ibcon#ireg 17 cls_cnt 0 2006.203.08:07:50.37#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.203.08:07:50.37#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.203.08:07:50.37#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.203.08:07:50.37#ibcon#enter wrdev, iclass 22, count 0 2006.203.08:07:50.37#ibcon#first serial, iclass 22, count 0 2006.203.08:07:50.37#ibcon#enter sib2, iclass 22, count 0 2006.203.08:07:50.37#ibcon#flushed, iclass 22, count 0 2006.203.08:07:50.37#ibcon#about to write, iclass 22, count 0 2006.203.08:07:50.37#ibcon#wrote, iclass 22, count 0 2006.203.08:07:50.37#ibcon#about to read 3, iclass 22, count 0 2006.203.08:07:50.38#ibcon#read 3, iclass 22, count 0 2006.203.08:07:50.38#ibcon#about to read 4, iclass 22, count 0 2006.203.08:07:50.38#ibcon#read 4, iclass 22, count 0 2006.203.08:07:50.38#ibcon#about to read 5, iclass 22, count 0 2006.203.08:07:50.38#ibcon#read 5, iclass 22, count 0 2006.203.08:07:50.38#ibcon#about to read 6, iclass 22, count 0 2006.203.08:07:50.38#ibcon#read 6, iclass 22, count 0 2006.203.08:07:50.38#ibcon#end of sib2, iclass 22, count 0 2006.203.08:07:50.38#ibcon#*mode == 0, iclass 22, count 0 2006.203.08:07:50.38#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.203.08:07:50.38#ibcon#[26=FRQ=05,652.99\r\n] 2006.203.08:07:50.38#ibcon#*before write, iclass 22, count 0 2006.203.08:07:50.38#ibcon#enter sib2, iclass 22, count 0 2006.203.08:07:50.39#ibcon#flushed, iclass 22, count 0 2006.203.08:07:50.39#ibcon#about to write, iclass 22, count 0 2006.203.08:07:50.39#ibcon#wrote, iclass 22, count 0 2006.203.08:07:50.39#ibcon#about to read 3, iclass 22, count 0 2006.203.08:07:50.42#ibcon#read 3, iclass 22, count 0 2006.203.08:07:50.42#ibcon#about to read 4, iclass 22, count 0 2006.203.08:07:50.42#ibcon#read 4, iclass 22, count 0 2006.203.08:07:50.42#ibcon#about to read 5, iclass 22, count 0 2006.203.08:07:50.42#ibcon#read 5, iclass 22, count 0 2006.203.08:07:50.42#ibcon#about to read 6, iclass 22, count 0 2006.203.08:07:50.42#ibcon#read 6, iclass 22, count 0 2006.203.08:07:50.42#ibcon#end of sib2, iclass 22, count 0 2006.203.08:07:50.42#ibcon#*after write, iclass 22, count 0 2006.203.08:07:50.42#ibcon#*before return 0, iclass 22, count 0 2006.203.08:07:50.42#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.203.08:07:50.43#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.203.08:07:50.43#ibcon#about to clear, iclass 22 cls_cnt 0 2006.203.08:07:50.43#ibcon#cleared, iclass 22 cls_cnt 0 2006.203.08:07:50.43$vc4f8/va=5,7 2006.203.08:07:50.43#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.203.08:07:50.43#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.203.08:07:50.43#ibcon#ireg 11 cls_cnt 2 2006.203.08:07:50.43#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.203.08:07:50.47#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.203.08:07:50.47#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.203.08:07:50.47#ibcon#enter wrdev, iclass 24, count 2 2006.203.08:07:50.47#ibcon#first serial, iclass 24, count 2 2006.203.08:07:50.47#ibcon#enter sib2, iclass 24, count 2 2006.203.08:07:50.47#ibcon#flushed, iclass 24, count 2 2006.203.08:07:50.47#ibcon#about to write, iclass 24, count 2 2006.203.08:07:50.47#ibcon#wrote, iclass 24, count 2 2006.203.08:07:50.47#ibcon#about to read 3, iclass 24, count 2 2006.203.08:07:50.49#ibcon#read 3, iclass 24, count 2 2006.203.08:07:50.49#ibcon#about to read 4, iclass 24, count 2 2006.203.08:07:50.49#ibcon#read 4, iclass 24, count 2 2006.203.08:07:50.49#ibcon#about to read 5, iclass 24, count 2 2006.203.08:07:50.49#ibcon#read 5, iclass 24, count 2 2006.203.08:07:50.49#ibcon#about to read 6, iclass 24, count 2 2006.203.08:07:50.49#ibcon#read 6, iclass 24, count 2 2006.203.08:07:50.49#ibcon#end of sib2, iclass 24, count 2 2006.203.08:07:50.49#ibcon#*mode == 0, iclass 24, count 2 2006.203.08:07:50.49#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.203.08:07:50.49#ibcon#[25=AT05-07\r\n] 2006.203.08:07:50.49#ibcon#*before write, iclass 24, count 2 2006.203.08:07:50.49#ibcon#enter sib2, iclass 24, count 2 2006.203.08:07:50.50#ibcon#flushed, iclass 24, count 2 2006.203.08:07:50.50#ibcon#about to write, iclass 24, count 2 2006.203.08:07:50.50#ibcon#wrote, iclass 24, count 2 2006.203.08:07:50.50#ibcon#about to read 3, iclass 24, count 2 2006.203.08:07:50.52#ibcon#read 3, iclass 24, count 2 2006.203.08:07:50.52#ibcon#about to read 4, iclass 24, count 2 2006.203.08:07:50.52#ibcon#read 4, iclass 24, count 2 2006.203.08:07:50.52#ibcon#about to read 5, iclass 24, count 2 2006.203.08:07:50.52#ibcon#read 5, iclass 24, count 2 2006.203.08:07:50.52#ibcon#about to read 6, iclass 24, count 2 2006.203.08:07:50.52#ibcon#read 6, iclass 24, count 2 2006.203.08:07:50.52#ibcon#end of sib2, iclass 24, count 2 2006.203.08:07:50.53#ibcon#*after write, iclass 24, count 2 2006.203.08:07:50.53#ibcon#*before return 0, iclass 24, count 2 2006.203.08:07:50.53#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.203.08:07:50.53#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.203.08:07:50.53#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.203.08:07:50.53#ibcon#ireg 7 cls_cnt 0 2006.203.08:07:50.53#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.203.08:07:50.57#abcon#<5=/05 1.9 3.0 23.671001001.1\r\n> 2006.203.08:07:50.60#abcon#{5=INTERFACE CLEAR} 2006.203.08:07:50.64#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.203.08:07:50.64#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.203.08:07:50.64#ibcon#enter wrdev, iclass 24, count 0 2006.203.08:07:50.64#ibcon#first serial, iclass 24, count 0 2006.203.08:07:50.64#ibcon#enter sib2, iclass 24, count 0 2006.203.08:07:50.64#ibcon#flushed, iclass 24, count 0 2006.203.08:07:50.64#ibcon#about to write, iclass 24, count 0 2006.203.08:07:50.64#ibcon#wrote, iclass 24, count 0 2006.203.08:07:50.64#ibcon#about to read 3, iclass 24, count 0 2006.203.08:07:50.65#abcon#[5=S1D000X0/0*\r\n] 2006.203.08:07:50.68#ibcon#read 3, iclass 24, count 0 2006.203.08:07:50.68#ibcon#about to read 4, iclass 24, count 0 2006.203.08:07:50.68#ibcon#read 4, iclass 24, count 0 2006.203.08:07:50.68#ibcon#about to read 5, iclass 24, count 0 2006.203.08:07:50.68#ibcon#read 5, iclass 24, count 0 2006.203.08:07:50.68#ibcon#about to read 6, iclass 24, count 0 2006.203.08:07:50.68#ibcon#read 6, iclass 24, count 0 2006.203.08:07:50.68#ibcon#end of sib2, iclass 24, count 0 2006.203.08:07:50.68#ibcon#*mode == 0, iclass 24, count 0 2006.203.08:07:50.68#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.203.08:07:50.68#ibcon#[25=USB\r\n] 2006.203.08:07:50.68#ibcon#*before write, iclass 24, count 0 2006.203.08:07:50.68#ibcon#enter sib2, iclass 24, count 0 2006.203.08:07:50.68#ibcon#flushed, iclass 24, count 0 2006.203.08:07:50.68#ibcon#about to write, iclass 24, count 0 2006.203.08:07:50.68#ibcon#wrote, iclass 24, count 0 2006.203.08:07:50.68#ibcon#about to read 3, iclass 24, count 0 2006.203.08:07:50.71#ibcon#read 3, iclass 24, count 0 2006.203.08:07:50.71#ibcon#about to read 4, iclass 24, count 0 2006.203.08:07:50.71#ibcon#read 4, iclass 24, count 0 2006.203.08:07:50.71#ibcon#about to read 5, iclass 24, count 0 2006.203.08:07:50.71#ibcon#read 5, iclass 24, count 0 2006.203.08:07:50.71#ibcon#about to read 6, iclass 24, count 0 2006.203.08:07:50.71#ibcon#read 6, iclass 24, count 0 2006.203.08:07:50.71#ibcon#end of sib2, iclass 24, count 0 2006.203.08:07:50.71#ibcon#*after write, iclass 24, count 0 2006.203.08:07:50.71#ibcon#*before return 0, iclass 24, count 0 2006.203.08:07:50.71#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.203.08:07:50.71#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.203.08:07:50.72#ibcon#about to clear, iclass 24 cls_cnt 0 2006.203.08:07:50.72#ibcon#cleared, iclass 24 cls_cnt 0 2006.203.08:07:50.72$vc4f8/valo=6,772.99 2006.203.08:07:50.72#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.203.08:07:50.72#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.203.08:07:50.72#ibcon#ireg 17 cls_cnt 0 2006.203.08:07:50.72#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.203.08:07:50.72#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.203.08:07:50.72#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.203.08:07:50.72#ibcon#enter wrdev, iclass 30, count 0 2006.203.08:07:50.72#ibcon#first serial, iclass 30, count 0 2006.203.08:07:50.72#ibcon#enter sib2, iclass 30, count 0 2006.203.08:07:50.72#ibcon#flushed, iclass 30, count 0 2006.203.08:07:50.72#ibcon#about to write, iclass 30, count 0 2006.203.08:07:50.72#ibcon#wrote, iclass 30, count 0 2006.203.08:07:50.72#ibcon#about to read 3, iclass 30, count 0 2006.203.08:07:50.73#ibcon#read 3, iclass 30, count 0 2006.203.08:07:50.73#ibcon#about to read 4, iclass 30, count 0 2006.203.08:07:50.73#ibcon#read 4, iclass 30, count 0 2006.203.08:07:50.73#ibcon#about to read 5, iclass 30, count 0 2006.203.08:07:50.73#ibcon#read 5, iclass 30, count 0 2006.203.08:07:50.73#ibcon#about to read 6, iclass 30, count 0 2006.203.08:07:50.73#ibcon#read 6, iclass 30, count 0 2006.203.08:07:50.73#ibcon#end of sib2, iclass 30, count 0 2006.203.08:07:50.73#ibcon#*mode == 0, iclass 30, count 0 2006.203.08:07:50.73#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.203.08:07:50.73#ibcon#[26=FRQ=06,772.99\r\n] 2006.203.08:07:50.73#ibcon#*before write, iclass 30, count 0 2006.203.08:07:50.73#ibcon#enter sib2, iclass 30, count 0 2006.203.08:07:50.74#ibcon#flushed, iclass 30, count 0 2006.203.08:07:50.74#ibcon#about to write, iclass 30, count 0 2006.203.08:07:50.74#ibcon#wrote, iclass 30, count 0 2006.203.08:07:50.74#ibcon#about to read 3, iclass 30, count 0 2006.203.08:07:50.77#ibcon#read 3, iclass 30, count 0 2006.203.08:07:50.77#ibcon#about to read 4, iclass 30, count 0 2006.203.08:07:50.77#ibcon#read 4, iclass 30, count 0 2006.203.08:07:50.77#ibcon#about to read 5, iclass 30, count 0 2006.203.08:07:50.77#ibcon#read 5, iclass 30, count 0 2006.203.08:07:50.77#ibcon#about to read 6, iclass 30, count 0 2006.203.08:07:50.77#ibcon#read 6, iclass 30, count 0 2006.203.08:07:50.77#ibcon#end of sib2, iclass 30, count 0 2006.203.08:07:50.77#ibcon#*after write, iclass 30, count 0 2006.203.08:07:50.77#ibcon#*before return 0, iclass 30, count 0 2006.203.08:07:50.77#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.203.08:07:50.77#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.203.08:07:50.78#ibcon#about to clear, iclass 30 cls_cnt 0 2006.203.08:07:50.78#ibcon#cleared, iclass 30 cls_cnt 0 2006.203.08:07:50.78$vc4f8/va=6,6 2006.203.08:07:50.78#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.203.08:07:50.78#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.203.08:07:50.78#ibcon#ireg 11 cls_cnt 2 2006.203.08:07:50.78#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.203.08:07:50.82#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.203.08:07:50.82#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.203.08:07:50.82#ibcon#enter wrdev, iclass 32, count 2 2006.203.08:07:50.82#ibcon#first serial, iclass 32, count 2 2006.203.08:07:50.82#ibcon#enter sib2, iclass 32, count 2 2006.203.08:07:50.82#ibcon#flushed, iclass 32, count 2 2006.203.08:07:50.82#ibcon#about to write, iclass 32, count 2 2006.203.08:07:50.82#ibcon#wrote, iclass 32, count 2 2006.203.08:07:50.82#ibcon#about to read 3, iclass 32, count 2 2006.203.08:07:50.84#ibcon#read 3, iclass 32, count 2 2006.203.08:07:50.84#ibcon#about to read 4, iclass 32, count 2 2006.203.08:07:50.84#ibcon#read 4, iclass 32, count 2 2006.203.08:07:50.84#ibcon#about to read 5, iclass 32, count 2 2006.203.08:07:50.84#ibcon#read 5, iclass 32, count 2 2006.203.08:07:50.84#ibcon#about to read 6, iclass 32, count 2 2006.203.08:07:50.84#ibcon#read 6, iclass 32, count 2 2006.203.08:07:50.84#ibcon#end of sib2, iclass 32, count 2 2006.203.08:07:50.84#ibcon#*mode == 0, iclass 32, count 2 2006.203.08:07:50.84#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.203.08:07:50.84#ibcon#[25=AT06-06\r\n] 2006.203.08:07:50.84#ibcon#*before write, iclass 32, count 2 2006.203.08:07:50.84#ibcon#enter sib2, iclass 32, count 2 2006.203.08:07:50.85#ibcon#flushed, iclass 32, count 2 2006.203.08:07:50.85#ibcon#about to write, iclass 32, count 2 2006.203.08:07:50.85#ibcon#wrote, iclass 32, count 2 2006.203.08:07:50.85#ibcon#about to read 3, iclass 32, count 2 2006.203.08:07:50.87#ibcon#read 3, iclass 32, count 2 2006.203.08:07:50.87#ibcon#about to read 4, iclass 32, count 2 2006.203.08:07:50.87#ibcon#read 4, iclass 32, count 2 2006.203.08:07:50.87#ibcon#about to read 5, iclass 32, count 2 2006.203.08:07:50.87#ibcon#read 5, iclass 32, count 2 2006.203.08:07:50.87#ibcon#about to read 6, iclass 32, count 2 2006.203.08:07:50.87#ibcon#read 6, iclass 32, count 2 2006.203.08:07:50.87#ibcon#end of sib2, iclass 32, count 2 2006.203.08:07:50.87#ibcon#*after write, iclass 32, count 2 2006.203.08:07:50.87#ibcon#*before return 0, iclass 32, count 2 2006.203.08:07:50.87#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.203.08:07:50.87#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.203.08:07:50.88#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.203.08:07:50.88#ibcon#ireg 7 cls_cnt 0 2006.203.08:07:50.88#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.203.08:07:50.98#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.203.08:07:50.98#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.203.08:07:50.98#ibcon#enter wrdev, iclass 32, count 0 2006.203.08:07:50.98#ibcon#first serial, iclass 32, count 0 2006.203.08:07:50.98#ibcon#enter sib2, iclass 32, count 0 2006.203.08:07:50.98#ibcon#flushed, iclass 32, count 0 2006.203.08:07:50.98#ibcon#about to write, iclass 32, count 0 2006.203.08:07:50.98#ibcon#wrote, iclass 32, count 0 2006.203.08:07:50.98#ibcon#about to read 3, iclass 32, count 0 2006.203.08:07:51.00#ibcon#read 3, iclass 32, count 0 2006.203.08:07:51.00#ibcon#about to read 4, iclass 32, count 0 2006.203.08:07:51.00#ibcon#read 4, iclass 32, count 0 2006.203.08:07:51.00#ibcon#about to read 5, iclass 32, count 0 2006.203.08:07:51.00#ibcon#read 5, iclass 32, count 0 2006.203.08:07:51.00#ibcon#about to read 6, iclass 32, count 0 2006.203.08:07:51.00#ibcon#read 6, iclass 32, count 0 2006.203.08:07:51.00#ibcon#end of sib2, iclass 32, count 0 2006.203.08:07:51.00#ibcon#*mode == 0, iclass 32, count 0 2006.203.08:07:51.00#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.203.08:07:51.00#ibcon#[25=USB\r\n] 2006.203.08:07:51.00#ibcon#*before write, iclass 32, count 0 2006.203.08:07:51.01#ibcon#enter sib2, iclass 32, count 0 2006.203.08:07:51.01#ibcon#flushed, iclass 32, count 0 2006.203.08:07:51.01#ibcon#about to write, iclass 32, count 0 2006.203.08:07:51.01#ibcon#wrote, iclass 32, count 0 2006.203.08:07:51.01#ibcon#about to read 3, iclass 32, count 0 2006.203.08:07:51.03#ibcon#read 3, iclass 32, count 0 2006.203.08:07:51.03#ibcon#about to read 4, iclass 32, count 0 2006.203.08:07:51.03#ibcon#read 4, iclass 32, count 0 2006.203.08:07:51.03#ibcon#about to read 5, iclass 32, count 0 2006.203.08:07:51.03#ibcon#read 5, iclass 32, count 0 2006.203.08:07:51.03#ibcon#about to read 6, iclass 32, count 0 2006.203.08:07:51.03#ibcon#read 6, iclass 32, count 0 2006.203.08:07:51.03#ibcon#end of sib2, iclass 32, count 0 2006.203.08:07:51.03#ibcon#*after write, iclass 32, count 0 2006.203.08:07:51.03#ibcon#*before return 0, iclass 32, count 0 2006.203.08:07:51.03#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.203.08:07:51.03#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.203.08:07:51.04#ibcon#about to clear, iclass 32 cls_cnt 0 2006.203.08:07:51.04#ibcon#cleared, iclass 32 cls_cnt 0 2006.203.08:07:51.04$vc4f8/valo=7,832.99 2006.203.08:07:51.04#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.203.08:07:51.04#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.203.08:07:51.04#ibcon#ireg 17 cls_cnt 0 2006.203.08:07:51.04#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.203.08:07:51.04#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.203.08:07:51.04#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.203.08:07:51.04#ibcon#enter wrdev, iclass 34, count 0 2006.203.08:07:51.04#ibcon#first serial, iclass 34, count 0 2006.203.08:07:51.04#ibcon#enter sib2, iclass 34, count 0 2006.203.08:07:51.04#ibcon#flushed, iclass 34, count 0 2006.203.08:07:51.04#ibcon#about to write, iclass 34, count 0 2006.203.08:07:51.04#ibcon#wrote, iclass 34, count 0 2006.203.08:07:51.04#ibcon#about to read 3, iclass 34, count 0 2006.203.08:07:51.05#ibcon#read 3, iclass 34, count 0 2006.203.08:07:51.05#ibcon#about to read 4, iclass 34, count 0 2006.203.08:07:51.05#ibcon#read 4, iclass 34, count 0 2006.203.08:07:51.05#ibcon#about to read 5, iclass 34, count 0 2006.203.08:07:51.05#ibcon#read 5, iclass 34, count 0 2006.203.08:07:51.05#ibcon#about to read 6, iclass 34, count 0 2006.203.08:07:51.05#ibcon#read 6, iclass 34, count 0 2006.203.08:07:51.05#ibcon#end of sib2, iclass 34, count 0 2006.203.08:07:51.05#ibcon#*mode == 0, iclass 34, count 0 2006.203.08:07:51.05#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.203.08:07:51.05#ibcon#[26=FRQ=07,832.99\r\n] 2006.203.08:07:51.06#ibcon#*before write, iclass 34, count 0 2006.203.08:07:51.06#ibcon#enter sib2, iclass 34, count 0 2006.203.08:07:51.06#ibcon#flushed, iclass 34, count 0 2006.203.08:07:51.06#ibcon#about to write, iclass 34, count 0 2006.203.08:07:51.06#ibcon#wrote, iclass 34, count 0 2006.203.08:07:51.06#ibcon#about to read 3, iclass 34, count 0 2006.203.08:07:51.09#ibcon#read 3, iclass 34, count 0 2006.203.08:07:51.09#ibcon#about to read 4, iclass 34, count 0 2006.203.08:07:51.09#ibcon#read 4, iclass 34, count 0 2006.203.08:07:51.09#ibcon#about to read 5, iclass 34, count 0 2006.203.08:07:51.09#ibcon#read 5, iclass 34, count 0 2006.203.08:07:51.09#ibcon#about to read 6, iclass 34, count 0 2006.203.08:07:51.09#ibcon#read 6, iclass 34, count 0 2006.203.08:07:51.09#ibcon#end of sib2, iclass 34, count 0 2006.203.08:07:51.09#ibcon#*after write, iclass 34, count 0 2006.203.08:07:51.09#ibcon#*before return 0, iclass 34, count 0 2006.203.08:07:51.09#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.203.08:07:51.10#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.203.08:07:51.10#ibcon#about to clear, iclass 34 cls_cnt 0 2006.203.08:07:51.10#ibcon#cleared, iclass 34 cls_cnt 0 2006.203.08:07:51.10$vc4f8/va=7,7 2006.203.08:07:51.10#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.203.08:07:51.10#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.203.08:07:51.10#ibcon#ireg 11 cls_cnt 2 2006.203.08:07:51.10#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.203.08:07:51.15#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.203.08:07:51.15#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.203.08:07:51.15#ibcon#enter wrdev, iclass 36, count 2 2006.203.08:07:51.15#ibcon#first serial, iclass 36, count 2 2006.203.08:07:51.15#ibcon#enter sib2, iclass 36, count 2 2006.203.08:07:51.15#ibcon#flushed, iclass 36, count 2 2006.203.08:07:51.15#ibcon#about to write, iclass 36, count 2 2006.203.08:07:51.15#ibcon#wrote, iclass 36, count 2 2006.203.08:07:51.15#ibcon#about to read 3, iclass 36, count 2 2006.203.08:07:51.16#ibcon#read 3, iclass 36, count 2 2006.203.08:07:51.16#ibcon#about to read 4, iclass 36, count 2 2006.203.08:07:51.16#ibcon#read 4, iclass 36, count 2 2006.203.08:07:51.16#ibcon#about to read 5, iclass 36, count 2 2006.203.08:07:51.16#ibcon#read 5, iclass 36, count 2 2006.203.08:07:51.16#ibcon#about to read 6, iclass 36, count 2 2006.203.08:07:51.16#ibcon#read 6, iclass 36, count 2 2006.203.08:07:51.16#ibcon#end of sib2, iclass 36, count 2 2006.203.08:07:51.16#ibcon#*mode == 0, iclass 36, count 2 2006.203.08:07:51.16#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.203.08:07:51.16#ibcon#[25=AT07-07\r\n] 2006.203.08:07:51.17#ibcon#*before write, iclass 36, count 2 2006.203.08:07:51.17#ibcon#enter sib2, iclass 36, count 2 2006.203.08:07:51.17#ibcon#flushed, iclass 36, count 2 2006.203.08:07:51.17#ibcon#about to write, iclass 36, count 2 2006.203.08:07:51.17#ibcon#wrote, iclass 36, count 2 2006.203.08:07:51.17#ibcon#about to read 3, iclass 36, count 2 2006.203.08:07:51.19#ibcon#read 3, iclass 36, count 2 2006.203.08:07:51.19#ibcon#about to read 4, iclass 36, count 2 2006.203.08:07:51.19#ibcon#read 4, iclass 36, count 2 2006.203.08:07:51.19#ibcon#about to read 5, iclass 36, count 2 2006.203.08:07:51.19#ibcon#read 5, iclass 36, count 2 2006.203.08:07:51.19#ibcon#about to read 6, iclass 36, count 2 2006.203.08:07:51.19#ibcon#read 6, iclass 36, count 2 2006.203.08:07:51.19#ibcon#end of sib2, iclass 36, count 2 2006.203.08:07:51.19#ibcon#*after write, iclass 36, count 2 2006.203.08:07:51.19#ibcon#*before return 0, iclass 36, count 2 2006.203.08:07:51.19#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.203.08:07:51.20#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.203.08:07:51.20#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.203.08:07:51.20#ibcon#ireg 7 cls_cnt 0 2006.203.08:07:51.20#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.203.08:07:51.31#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.203.08:07:51.31#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.203.08:07:51.31#ibcon#enter wrdev, iclass 36, count 0 2006.203.08:07:51.31#ibcon#first serial, iclass 36, count 0 2006.203.08:07:51.31#ibcon#enter sib2, iclass 36, count 0 2006.203.08:07:51.31#ibcon#flushed, iclass 36, count 0 2006.203.08:07:51.31#ibcon#about to write, iclass 36, count 0 2006.203.08:07:51.31#ibcon#wrote, iclass 36, count 0 2006.203.08:07:51.31#ibcon#about to read 3, iclass 36, count 0 2006.203.08:07:51.33#ibcon#read 3, iclass 36, count 0 2006.203.08:07:51.33#ibcon#about to read 4, iclass 36, count 0 2006.203.08:07:51.33#ibcon#read 4, iclass 36, count 0 2006.203.08:07:51.33#ibcon#about to read 5, iclass 36, count 0 2006.203.08:07:51.33#ibcon#read 5, iclass 36, count 0 2006.203.08:07:51.33#ibcon#about to read 6, iclass 36, count 0 2006.203.08:07:51.33#ibcon#read 6, iclass 36, count 0 2006.203.08:07:51.33#ibcon#end of sib2, iclass 36, count 0 2006.203.08:07:51.33#ibcon#*mode == 0, iclass 36, count 0 2006.203.08:07:51.33#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.203.08:07:51.33#ibcon#[25=USB\r\n] 2006.203.08:07:51.33#ibcon#*before write, iclass 36, count 0 2006.203.08:07:51.33#ibcon#enter sib2, iclass 36, count 0 2006.203.08:07:51.34#ibcon#flushed, iclass 36, count 0 2006.203.08:07:51.34#ibcon#about to write, iclass 36, count 0 2006.203.08:07:51.34#ibcon#wrote, iclass 36, count 0 2006.203.08:07:51.34#ibcon#about to read 3, iclass 36, count 0 2006.203.08:07:51.36#ibcon#read 3, iclass 36, count 0 2006.203.08:07:51.36#ibcon#about to read 4, iclass 36, count 0 2006.203.08:07:51.36#ibcon#read 4, iclass 36, count 0 2006.203.08:07:51.36#ibcon#about to read 5, iclass 36, count 0 2006.203.08:07:51.36#ibcon#read 5, iclass 36, count 0 2006.203.08:07:51.36#ibcon#about to read 6, iclass 36, count 0 2006.203.08:07:51.36#ibcon#read 6, iclass 36, count 0 2006.203.08:07:51.36#ibcon#end of sib2, iclass 36, count 0 2006.203.08:07:51.36#ibcon#*after write, iclass 36, count 0 2006.203.08:07:51.36#ibcon#*before return 0, iclass 36, count 0 2006.203.08:07:51.36#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.203.08:07:51.36#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.203.08:07:51.37#ibcon#about to clear, iclass 36 cls_cnt 0 2006.203.08:07:51.37#ibcon#cleared, iclass 36 cls_cnt 0 2006.203.08:07:51.37$vc4f8/valo=8,852.99 2006.203.08:07:51.37#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.203.08:07:51.37#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.203.08:07:51.37#ibcon#ireg 17 cls_cnt 0 2006.203.08:07:51.37#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.203.08:07:51.37#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.203.08:07:51.37#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.203.08:07:51.37#ibcon#enter wrdev, iclass 38, count 0 2006.203.08:07:51.37#ibcon#first serial, iclass 38, count 0 2006.203.08:07:51.37#ibcon#enter sib2, iclass 38, count 0 2006.203.08:07:51.37#ibcon#flushed, iclass 38, count 0 2006.203.08:07:51.37#ibcon#about to write, iclass 38, count 0 2006.203.08:07:51.37#ibcon#wrote, iclass 38, count 0 2006.203.08:07:51.37#ibcon#about to read 3, iclass 38, count 0 2006.203.08:07:51.39#ibcon#read 3, iclass 38, count 0 2006.203.08:07:51.39#ibcon#about to read 4, iclass 38, count 0 2006.203.08:07:51.39#ibcon#read 4, iclass 38, count 0 2006.203.08:07:51.39#ibcon#about to read 5, iclass 38, count 0 2006.203.08:07:51.39#ibcon#read 5, iclass 38, count 0 2006.203.08:07:51.39#ibcon#about to read 6, iclass 38, count 0 2006.203.08:07:51.39#ibcon#read 6, iclass 38, count 0 2006.203.08:07:51.39#ibcon#end of sib2, iclass 38, count 0 2006.203.08:07:51.39#ibcon#*mode == 0, iclass 38, count 0 2006.203.08:07:51.39#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.203.08:07:51.39#ibcon#[26=FRQ=08,852.99\r\n] 2006.203.08:07:51.39#ibcon#*before write, iclass 38, count 0 2006.203.08:07:51.39#ibcon#enter sib2, iclass 38, count 0 2006.203.08:07:51.39#ibcon#flushed, iclass 38, count 0 2006.203.08:07:51.39#ibcon#about to write, iclass 38, count 0 2006.203.08:07:51.39#ibcon#wrote, iclass 38, count 0 2006.203.08:07:51.39#ibcon#about to read 3, iclass 38, count 0 2006.203.08:07:51.43#ibcon#read 3, iclass 38, count 0 2006.203.08:07:51.43#ibcon#about to read 4, iclass 38, count 0 2006.203.08:07:51.43#ibcon#read 4, iclass 38, count 0 2006.203.08:07:51.43#ibcon#about to read 5, iclass 38, count 0 2006.203.08:07:51.43#ibcon#read 5, iclass 38, count 0 2006.203.08:07:51.43#ibcon#about to read 6, iclass 38, count 0 2006.203.08:07:51.43#ibcon#read 6, iclass 38, count 0 2006.203.08:07:51.43#ibcon#end of sib2, iclass 38, count 0 2006.203.08:07:51.43#ibcon#*after write, iclass 38, count 0 2006.203.08:07:51.44#ibcon#*before return 0, iclass 38, count 0 2006.203.08:07:51.44#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.203.08:07:51.44#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.203.08:07:51.44#ibcon#about to clear, iclass 38 cls_cnt 0 2006.203.08:07:51.44#ibcon#cleared, iclass 38 cls_cnt 0 2006.203.08:07:51.44$vc4f8/va=8,6 2006.203.08:07:51.44#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.203.08:07:51.44#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.203.08:07:51.44#ibcon#ireg 11 cls_cnt 2 2006.203.08:07:51.44#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.203.08:07:51.47#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.203.08:07:51.47#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.203.08:07:51.47#ibcon#enter wrdev, iclass 40, count 2 2006.203.08:07:51.47#ibcon#first serial, iclass 40, count 2 2006.203.08:07:51.47#ibcon#enter sib2, iclass 40, count 2 2006.203.08:07:51.47#ibcon#flushed, iclass 40, count 2 2006.203.08:07:51.47#ibcon#about to write, iclass 40, count 2 2006.203.08:07:51.47#ibcon#wrote, iclass 40, count 2 2006.203.08:07:51.47#ibcon#about to read 3, iclass 40, count 2 2006.203.08:07:51.49#ibcon#read 3, iclass 40, count 2 2006.203.08:07:51.49#ibcon#about to read 4, iclass 40, count 2 2006.203.08:07:51.49#ibcon#read 4, iclass 40, count 2 2006.203.08:07:51.49#ibcon#about to read 5, iclass 40, count 2 2006.203.08:07:51.49#ibcon#read 5, iclass 40, count 2 2006.203.08:07:51.49#ibcon#about to read 6, iclass 40, count 2 2006.203.08:07:51.49#ibcon#read 6, iclass 40, count 2 2006.203.08:07:51.49#ibcon#end of sib2, iclass 40, count 2 2006.203.08:07:51.49#ibcon#*mode == 0, iclass 40, count 2 2006.203.08:07:51.49#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.203.08:07:51.49#ibcon#[25=AT08-06\r\n] 2006.203.08:07:51.50#ibcon#*before write, iclass 40, count 2 2006.203.08:07:51.50#ibcon#enter sib2, iclass 40, count 2 2006.203.08:07:51.50#ibcon#flushed, iclass 40, count 2 2006.203.08:07:51.50#ibcon#about to write, iclass 40, count 2 2006.203.08:07:51.50#ibcon#wrote, iclass 40, count 2 2006.203.08:07:51.50#ibcon#about to read 3, iclass 40, count 2 2006.203.08:07:51.52#ibcon#read 3, iclass 40, count 2 2006.203.08:07:51.52#ibcon#about to read 4, iclass 40, count 2 2006.203.08:07:51.52#ibcon#read 4, iclass 40, count 2 2006.203.08:07:51.52#ibcon#about to read 5, iclass 40, count 2 2006.203.08:07:51.52#ibcon#read 5, iclass 40, count 2 2006.203.08:07:51.52#ibcon#about to read 6, iclass 40, count 2 2006.203.08:07:51.52#ibcon#read 6, iclass 40, count 2 2006.203.08:07:51.52#ibcon#end of sib2, iclass 40, count 2 2006.203.08:07:51.52#ibcon#*after write, iclass 40, count 2 2006.203.08:07:51.52#ibcon#*before return 0, iclass 40, count 2 2006.203.08:07:51.52#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.203.08:07:51.53#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.203.08:07:51.53#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.203.08:07:51.53#ibcon#ireg 7 cls_cnt 0 2006.203.08:07:51.53#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.203.08:07:51.64#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.203.08:07:51.64#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.203.08:07:51.64#ibcon#enter wrdev, iclass 40, count 0 2006.203.08:07:51.64#ibcon#first serial, iclass 40, count 0 2006.203.08:07:51.64#ibcon#enter sib2, iclass 40, count 0 2006.203.08:07:51.64#ibcon#flushed, iclass 40, count 0 2006.203.08:07:51.64#ibcon#about to write, iclass 40, count 0 2006.203.08:07:51.64#ibcon#wrote, iclass 40, count 0 2006.203.08:07:51.64#ibcon#about to read 3, iclass 40, count 0 2006.203.08:07:51.66#ibcon#read 3, iclass 40, count 0 2006.203.08:07:51.66#ibcon#about to read 4, iclass 40, count 0 2006.203.08:07:51.66#ibcon#read 4, iclass 40, count 0 2006.203.08:07:51.66#ibcon#about to read 5, iclass 40, count 0 2006.203.08:07:51.66#ibcon#read 5, iclass 40, count 0 2006.203.08:07:51.66#ibcon#about to read 6, iclass 40, count 0 2006.203.08:07:51.66#ibcon#read 6, iclass 40, count 0 2006.203.08:07:51.66#ibcon#end of sib2, iclass 40, count 0 2006.203.08:07:51.66#ibcon#*mode == 0, iclass 40, count 0 2006.203.08:07:51.66#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.203.08:07:51.66#ibcon#[25=USB\r\n] 2006.203.08:07:51.66#ibcon#*before write, iclass 40, count 0 2006.203.08:07:51.66#ibcon#enter sib2, iclass 40, count 0 2006.203.08:07:51.67#ibcon#flushed, iclass 40, count 0 2006.203.08:07:51.67#ibcon#about to write, iclass 40, count 0 2006.203.08:07:51.67#ibcon#wrote, iclass 40, count 0 2006.203.08:07:51.67#ibcon#about to read 3, iclass 40, count 0 2006.203.08:07:51.69#ibcon#read 3, iclass 40, count 0 2006.203.08:07:51.69#ibcon#about to read 4, iclass 40, count 0 2006.203.08:07:51.69#ibcon#read 4, iclass 40, count 0 2006.203.08:07:51.69#ibcon#about to read 5, iclass 40, count 0 2006.203.08:07:51.69#ibcon#read 5, iclass 40, count 0 2006.203.08:07:51.69#ibcon#about to read 6, iclass 40, count 0 2006.203.08:07:51.69#ibcon#read 6, iclass 40, count 0 2006.203.08:07:51.69#ibcon#end of sib2, iclass 40, count 0 2006.203.08:07:51.69#ibcon#*after write, iclass 40, count 0 2006.203.08:07:51.69#ibcon#*before return 0, iclass 40, count 0 2006.203.08:07:51.69#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.203.08:07:51.69#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.203.08:07:51.70#ibcon#about to clear, iclass 40 cls_cnt 0 2006.203.08:07:51.70#ibcon#cleared, iclass 40 cls_cnt 0 2006.203.08:07:51.70$vc4f8/vblo=1,632.99 2006.203.08:07:51.70#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.203.08:07:51.70#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.203.08:07:51.70#ibcon#ireg 17 cls_cnt 0 2006.203.08:07:51.70#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.203.08:07:51.70#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.203.08:07:51.70#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.203.08:07:51.70#ibcon#enter wrdev, iclass 4, count 0 2006.203.08:07:51.70#ibcon#first serial, iclass 4, count 0 2006.203.08:07:51.70#ibcon#enter sib2, iclass 4, count 0 2006.203.08:07:51.70#ibcon#flushed, iclass 4, count 0 2006.203.08:07:51.70#ibcon#about to write, iclass 4, count 0 2006.203.08:07:51.70#ibcon#wrote, iclass 4, count 0 2006.203.08:07:51.70#ibcon#about to read 3, iclass 4, count 0 2006.203.08:07:51.71#ibcon#read 3, iclass 4, count 0 2006.203.08:07:51.71#ibcon#about to read 4, iclass 4, count 0 2006.203.08:07:51.71#ibcon#read 4, iclass 4, count 0 2006.203.08:07:51.71#ibcon#about to read 5, iclass 4, count 0 2006.203.08:07:51.71#ibcon#read 5, iclass 4, count 0 2006.203.08:07:51.71#ibcon#about to read 6, iclass 4, count 0 2006.203.08:07:51.71#ibcon#read 6, iclass 4, count 0 2006.203.08:07:51.71#ibcon#end of sib2, iclass 4, count 0 2006.203.08:07:51.71#ibcon#*mode == 0, iclass 4, count 0 2006.203.08:07:51.71#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.203.08:07:51.71#ibcon#[28=FRQ=01,632.99\r\n] 2006.203.08:07:51.71#ibcon#*before write, iclass 4, count 0 2006.203.08:07:51.71#ibcon#enter sib2, iclass 4, count 0 2006.203.08:07:51.72#ibcon#flushed, iclass 4, count 0 2006.203.08:07:51.72#ibcon#about to write, iclass 4, count 0 2006.203.08:07:51.72#ibcon#wrote, iclass 4, count 0 2006.203.08:07:51.72#ibcon#about to read 3, iclass 4, count 0 2006.203.08:07:51.75#ibcon#read 3, iclass 4, count 0 2006.203.08:07:51.75#ibcon#about to read 4, iclass 4, count 0 2006.203.08:07:51.75#ibcon#read 4, iclass 4, count 0 2006.203.08:07:51.75#ibcon#about to read 5, iclass 4, count 0 2006.203.08:07:51.75#ibcon#read 5, iclass 4, count 0 2006.203.08:07:51.75#ibcon#about to read 6, iclass 4, count 0 2006.203.08:07:51.75#ibcon#read 6, iclass 4, count 0 2006.203.08:07:51.75#ibcon#end of sib2, iclass 4, count 0 2006.203.08:07:51.75#ibcon#*after write, iclass 4, count 0 2006.203.08:07:51.75#ibcon#*before return 0, iclass 4, count 0 2006.203.08:07:51.75#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.203.08:07:51.75#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.203.08:07:51.76#ibcon#about to clear, iclass 4 cls_cnt 0 2006.203.08:07:51.76#ibcon#cleared, iclass 4 cls_cnt 0 2006.203.08:07:51.76$vc4f8/vb=1,4 2006.203.08:07:51.76#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.203.08:07:51.76#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.203.08:07:51.76#ibcon#ireg 11 cls_cnt 2 2006.203.08:07:51.76#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.203.08:07:51.76#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.203.08:07:51.76#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.203.08:07:51.76#ibcon#enter wrdev, iclass 6, count 2 2006.203.08:07:51.76#ibcon#first serial, iclass 6, count 2 2006.203.08:07:51.76#ibcon#enter sib2, iclass 6, count 2 2006.203.08:07:51.76#ibcon#flushed, iclass 6, count 2 2006.203.08:07:51.76#ibcon#about to write, iclass 6, count 2 2006.203.08:07:51.76#ibcon#wrote, iclass 6, count 2 2006.203.08:07:51.76#ibcon#about to read 3, iclass 6, count 2 2006.203.08:07:51.77#ibcon#read 3, iclass 6, count 2 2006.203.08:07:51.77#ibcon#about to read 4, iclass 6, count 2 2006.203.08:07:51.77#ibcon#read 4, iclass 6, count 2 2006.203.08:07:51.77#ibcon#about to read 5, iclass 6, count 2 2006.203.08:07:51.77#ibcon#read 5, iclass 6, count 2 2006.203.08:07:51.77#ibcon#about to read 6, iclass 6, count 2 2006.203.08:07:51.77#ibcon#read 6, iclass 6, count 2 2006.203.08:07:51.77#ibcon#end of sib2, iclass 6, count 2 2006.203.08:07:51.77#ibcon#*mode == 0, iclass 6, count 2 2006.203.08:07:51.77#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.203.08:07:51.77#ibcon#[27=AT01-04\r\n] 2006.203.08:07:51.77#ibcon#*before write, iclass 6, count 2 2006.203.08:07:51.77#ibcon#enter sib2, iclass 6, count 2 2006.203.08:07:51.78#ibcon#flushed, iclass 6, count 2 2006.203.08:07:51.78#ibcon#about to write, iclass 6, count 2 2006.203.08:07:51.78#ibcon#wrote, iclass 6, count 2 2006.203.08:07:51.78#ibcon#about to read 3, iclass 6, count 2 2006.203.08:07:51.80#ibcon#read 3, iclass 6, count 2 2006.203.08:07:51.80#ibcon#about to read 4, iclass 6, count 2 2006.203.08:07:51.80#ibcon#read 4, iclass 6, count 2 2006.203.08:07:51.80#ibcon#about to read 5, iclass 6, count 2 2006.203.08:07:51.80#ibcon#read 5, iclass 6, count 2 2006.203.08:07:51.80#ibcon#about to read 6, iclass 6, count 2 2006.203.08:07:51.80#ibcon#read 6, iclass 6, count 2 2006.203.08:07:51.80#ibcon#end of sib2, iclass 6, count 2 2006.203.08:07:51.80#ibcon#*after write, iclass 6, count 2 2006.203.08:07:51.80#ibcon#*before return 0, iclass 6, count 2 2006.203.08:07:51.80#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.203.08:07:51.80#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.203.08:07:51.80#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.203.08:07:51.81#ibcon#ireg 7 cls_cnt 0 2006.203.08:07:51.81#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.203.08:07:51.91#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.203.08:07:51.91#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.203.08:07:51.91#ibcon#enter wrdev, iclass 6, count 0 2006.203.08:07:51.91#ibcon#first serial, iclass 6, count 0 2006.203.08:07:51.91#ibcon#enter sib2, iclass 6, count 0 2006.203.08:07:51.91#ibcon#flushed, iclass 6, count 0 2006.203.08:07:51.91#ibcon#about to write, iclass 6, count 0 2006.203.08:07:51.91#ibcon#wrote, iclass 6, count 0 2006.203.08:07:51.91#ibcon#about to read 3, iclass 6, count 0 2006.203.08:07:51.93#ibcon#read 3, iclass 6, count 0 2006.203.08:07:51.93#ibcon#about to read 4, iclass 6, count 0 2006.203.08:07:51.93#ibcon#read 4, iclass 6, count 0 2006.203.08:07:51.93#ibcon#about to read 5, iclass 6, count 0 2006.203.08:07:51.93#ibcon#read 5, iclass 6, count 0 2006.203.08:07:51.93#ibcon#about to read 6, iclass 6, count 0 2006.203.08:07:51.93#ibcon#read 6, iclass 6, count 0 2006.203.08:07:51.93#ibcon#end of sib2, iclass 6, count 0 2006.203.08:07:51.93#ibcon#*mode == 0, iclass 6, count 0 2006.203.08:07:51.93#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.203.08:07:51.93#ibcon#[27=USB\r\n] 2006.203.08:07:51.93#ibcon#*before write, iclass 6, count 0 2006.203.08:07:51.93#ibcon#enter sib2, iclass 6, count 0 2006.203.08:07:51.94#ibcon#flushed, iclass 6, count 0 2006.203.08:07:51.94#ibcon#about to write, iclass 6, count 0 2006.203.08:07:51.94#ibcon#wrote, iclass 6, count 0 2006.203.08:07:51.94#ibcon#about to read 3, iclass 6, count 0 2006.203.08:07:51.96#ibcon#read 3, iclass 6, count 0 2006.203.08:07:51.96#ibcon#about to read 4, iclass 6, count 0 2006.203.08:07:51.96#ibcon#read 4, iclass 6, count 0 2006.203.08:07:51.96#ibcon#about to read 5, iclass 6, count 0 2006.203.08:07:51.96#ibcon#read 5, iclass 6, count 0 2006.203.08:07:51.96#ibcon#about to read 6, iclass 6, count 0 2006.203.08:07:51.96#ibcon#read 6, iclass 6, count 0 2006.203.08:07:51.96#ibcon#end of sib2, iclass 6, count 0 2006.203.08:07:51.96#ibcon#*after write, iclass 6, count 0 2006.203.08:07:51.96#ibcon#*before return 0, iclass 6, count 0 2006.203.08:07:51.96#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.203.08:07:51.96#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.203.08:07:51.97#ibcon#about to clear, iclass 6 cls_cnt 0 2006.203.08:07:51.97#ibcon#cleared, iclass 6 cls_cnt 0 2006.203.08:07:51.97$vc4f8/vblo=2,640.99 2006.203.08:07:51.97#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.203.08:07:51.97#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.203.08:07:51.97#ibcon#ireg 17 cls_cnt 0 2006.203.08:07:51.97#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.203.08:07:51.97#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.203.08:07:51.97#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.203.08:07:51.97#ibcon#enter wrdev, iclass 10, count 0 2006.203.08:07:51.97#ibcon#first serial, iclass 10, count 0 2006.203.08:07:51.97#ibcon#enter sib2, iclass 10, count 0 2006.203.08:07:51.97#ibcon#flushed, iclass 10, count 0 2006.203.08:07:51.97#ibcon#about to write, iclass 10, count 0 2006.203.08:07:51.97#ibcon#wrote, iclass 10, count 0 2006.203.08:07:51.97#ibcon#about to read 3, iclass 10, count 0 2006.203.08:07:51.99#ibcon#read 3, iclass 10, count 0 2006.203.08:07:51.99#ibcon#about to read 4, iclass 10, count 0 2006.203.08:07:51.99#ibcon#read 4, iclass 10, count 0 2006.203.08:07:51.99#ibcon#about to read 5, iclass 10, count 0 2006.203.08:07:51.99#ibcon#read 5, iclass 10, count 0 2006.203.08:07:51.99#ibcon#about to read 6, iclass 10, count 0 2006.203.08:07:51.99#ibcon#read 6, iclass 10, count 0 2006.203.08:07:51.99#ibcon#end of sib2, iclass 10, count 0 2006.203.08:07:51.99#ibcon#*mode == 0, iclass 10, count 0 2006.203.08:07:51.99#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.203.08:07:51.99#ibcon#[28=FRQ=02,640.99\r\n] 2006.203.08:07:51.99#ibcon#*before write, iclass 10, count 0 2006.203.08:07:51.99#ibcon#enter sib2, iclass 10, count 0 2006.203.08:07:51.99#ibcon#flushed, iclass 10, count 0 2006.203.08:07:51.99#ibcon#about to write, iclass 10, count 0 2006.203.08:07:51.99#ibcon#wrote, iclass 10, count 0 2006.203.08:07:51.99#ibcon#about to read 3, iclass 10, count 0 2006.203.08:07:52.02#ibcon#read 3, iclass 10, count 0 2006.203.08:07:52.02#ibcon#about to read 4, iclass 10, count 0 2006.203.08:07:52.02#ibcon#read 4, iclass 10, count 0 2006.203.08:07:52.02#ibcon#about to read 5, iclass 10, count 0 2006.203.08:07:52.02#ibcon#read 5, iclass 10, count 0 2006.203.08:07:52.02#ibcon#about to read 6, iclass 10, count 0 2006.203.08:07:52.02#ibcon#read 6, iclass 10, count 0 2006.203.08:07:52.02#ibcon#end of sib2, iclass 10, count 0 2006.203.08:07:52.02#ibcon#*after write, iclass 10, count 0 2006.203.08:07:52.02#ibcon#*before return 0, iclass 10, count 0 2006.203.08:07:52.02#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.203.08:07:52.02#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.203.08:07:52.03#ibcon#about to clear, iclass 10 cls_cnt 0 2006.203.08:07:52.03#ibcon#cleared, iclass 10 cls_cnt 0 2006.203.08:07:52.03$vc4f8/vb=2,4 2006.203.08:07:52.03#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.203.08:07:52.03#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.203.08:07:52.03#ibcon#ireg 11 cls_cnt 2 2006.203.08:07:52.03#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.203.08:07:52.07#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.203.08:07:52.07#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.203.08:07:52.07#ibcon#enter wrdev, iclass 12, count 2 2006.203.08:07:52.07#ibcon#first serial, iclass 12, count 2 2006.203.08:07:52.07#ibcon#enter sib2, iclass 12, count 2 2006.203.08:07:52.07#ibcon#flushed, iclass 12, count 2 2006.203.08:07:52.07#ibcon#about to write, iclass 12, count 2 2006.203.08:07:52.07#ibcon#wrote, iclass 12, count 2 2006.203.08:07:52.07#ibcon#about to read 3, iclass 12, count 2 2006.203.08:07:52.09#ibcon#read 3, iclass 12, count 2 2006.203.08:07:52.09#ibcon#about to read 4, iclass 12, count 2 2006.203.08:07:52.09#ibcon#read 4, iclass 12, count 2 2006.203.08:07:52.09#ibcon#about to read 5, iclass 12, count 2 2006.203.08:07:52.09#ibcon#read 5, iclass 12, count 2 2006.203.08:07:52.09#ibcon#about to read 6, iclass 12, count 2 2006.203.08:07:52.09#ibcon#read 6, iclass 12, count 2 2006.203.08:07:52.09#ibcon#end of sib2, iclass 12, count 2 2006.203.08:07:52.09#ibcon#*mode == 0, iclass 12, count 2 2006.203.08:07:52.09#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.203.08:07:52.10#ibcon#[27=AT02-04\r\n] 2006.203.08:07:52.10#ibcon#*before write, iclass 12, count 2 2006.203.08:07:52.10#ibcon#enter sib2, iclass 12, count 2 2006.203.08:07:52.10#ibcon#flushed, iclass 12, count 2 2006.203.08:07:52.10#ibcon#about to write, iclass 12, count 2 2006.203.08:07:52.10#ibcon#wrote, iclass 12, count 2 2006.203.08:07:52.10#ibcon#about to read 3, iclass 12, count 2 2006.203.08:07:52.12#ibcon#read 3, iclass 12, count 2 2006.203.08:07:52.12#ibcon#about to read 4, iclass 12, count 2 2006.203.08:07:52.12#ibcon#read 4, iclass 12, count 2 2006.203.08:07:52.12#ibcon#about to read 5, iclass 12, count 2 2006.203.08:07:52.12#ibcon#read 5, iclass 12, count 2 2006.203.08:07:52.12#ibcon#about to read 6, iclass 12, count 2 2006.203.08:07:52.12#ibcon#read 6, iclass 12, count 2 2006.203.08:07:52.12#ibcon#end of sib2, iclass 12, count 2 2006.203.08:07:52.12#ibcon#*after write, iclass 12, count 2 2006.203.08:07:52.12#ibcon#*before return 0, iclass 12, count 2 2006.203.08:07:52.12#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.203.08:07:52.12#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.203.08:07:52.12#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.203.08:07:52.13#ibcon#ireg 7 cls_cnt 0 2006.203.08:07:52.13#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.203.08:07:52.23#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.203.08:07:52.23#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.203.08:07:52.23#ibcon#enter wrdev, iclass 12, count 0 2006.203.08:07:52.23#ibcon#first serial, iclass 12, count 0 2006.203.08:07:52.23#ibcon#enter sib2, iclass 12, count 0 2006.203.08:07:52.23#ibcon#flushed, iclass 12, count 0 2006.203.08:07:52.23#ibcon#about to write, iclass 12, count 0 2006.203.08:07:52.23#ibcon#wrote, iclass 12, count 0 2006.203.08:07:52.23#ibcon#about to read 3, iclass 12, count 0 2006.203.08:07:52.25#ibcon#read 3, iclass 12, count 0 2006.203.08:07:52.25#ibcon#about to read 4, iclass 12, count 0 2006.203.08:07:52.25#ibcon#read 4, iclass 12, count 0 2006.203.08:07:52.25#ibcon#about to read 5, iclass 12, count 0 2006.203.08:07:52.25#ibcon#read 5, iclass 12, count 0 2006.203.08:07:52.25#ibcon#about to read 6, iclass 12, count 0 2006.203.08:07:52.25#ibcon#read 6, iclass 12, count 0 2006.203.08:07:52.25#ibcon#end of sib2, iclass 12, count 0 2006.203.08:07:52.25#ibcon#*mode == 0, iclass 12, count 0 2006.203.08:07:52.25#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.203.08:07:52.26#ibcon#[27=USB\r\n] 2006.203.08:07:52.26#ibcon#*before write, iclass 12, count 0 2006.203.08:07:52.26#ibcon#enter sib2, iclass 12, count 0 2006.203.08:07:52.26#ibcon#flushed, iclass 12, count 0 2006.203.08:07:52.26#ibcon#about to write, iclass 12, count 0 2006.203.08:07:52.26#ibcon#wrote, iclass 12, count 0 2006.203.08:07:52.26#ibcon#about to read 3, iclass 12, count 0 2006.203.08:07:52.28#ibcon#read 3, iclass 12, count 0 2006.203.08:07:52.28#ibcon#about to read 4, iclass 12, count 0 2006.203.08:07:52.28#ibcon#read 4, iclass 12, count 0 2006.203.08:07:52.28#ibcon#about to read 5, iclass 12, count 0 2006.203.08:07:52.28#ibcon#read 5, iclass 12, count 0 2006.203.08:07:52.28#ibcon#about to read 6, iclass 12, count 0 2006.203.08:07:52.28#ibcon#read 6, iclass 12, count 0 2006.203.08:07:52.28#ibcon#end of sib2, iclass 12, count 0 2006.203.08:07:52.28#ibcon#*after write, iclass 12, count 0 2006.203.08:07:52.28#ibcon#*before return 0, iclass 12, count 0 2006.203.08:07:52.28#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.203.08:07:52.28#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.203.08:07:52.29#ibcon#about to clear, iclass 12 cls_cnt 0 2006.203.08:07:52.29#ibcon#cleared, iclass 12 cls_cnt 0 2006.203.08:07:52.29$vc4f8/vblo=3,656.99 2006.203.08:07:52.29#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.203.08:07:52.29#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.203.08:07:52.29#ibcon#ireg 17 cls_cnt 0 2006.203.08:07:52.29#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.203.08:07:52.29#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.203.08:07:52.29#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.203.08:07:52.29#ibcon#enter wrdev, iclass 14, count 0 2006.203.08:07:52.29#ibcon#first serial, iclass 14, count 0 2006.203.08:07:52.29#ibcon#enter sib2, iclass 14, count 0 2006.203.08:07:52.29#ibcon#flushed, iclass 14, count 0 2006.203.08:07:52.29#ibcon#about to write, iclass 14, count 0 2006.203.08:07:52.29#ibcon#wrote, iclass 14, count 0 2006.203.08:07:52.29#ibcon#about to read 3, iclass 14, count 0 2006.203.08:07:52.30#ibcon#read 3, iclass 14, count 0 2006.203.08:07:52.30#ibcon#about to read 4, iclass 14, count 0 2006.203.08:07:52.30#ibcon#read 4, iclass 14, count 0 2006.203.08:07:52.30#ibcon#about to read 5, iclass 14, count 0 2006.203.08:07:52.30#ibcon#read 5, iclass 14, count 0 2006.203.08:07:52.30#ibcon#about to read 6, iclass 14, count 0 2006.203.08:07:52.30#ibcon#read 6, iclass 14, count 0 2006.203.08:07:52.30#ibcon#end of sib2, iclass 14, count 0 2006.203.08:07:52.30#ibcon#*mode == 0, iclass 14, count 0 2006.203.08:07:52.30#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.203.08:07:52.30#ibcon#[28=FRQ=03,656.99\r\n] 2006.203.08:07:52.30#ibcon#*before write, iclass 14, count 0 2006.203.08:07:52.30#ibcon#enter sib2, iclass 14, count 0 2006.203.08:07:52.30#ibcon#flushed, iclass 14, count 0 2006.203.08:07:52.31#ibcon#about to write, iclass 14, count 0 2006.203.08:07:52.31#ibcon#wrote, iclass 14, count 0 2006.203.08:07:52.31#ibcon#about to read 3, iclass 14, count 0 2006.203.08:07:52.34#ibcon#read 3, iclass 14, count 0 2006.203.08:07:52.34#ibcon#about to read 4, iclass 14, count 0 2006.203.08:07:52.34#ibcon#read 4, iclass 14, count 0 2006.203.08:07:52.34#ibcon#about to read 5, iclass 14, count 0 2006.203.08:07:52.34#ibcon#read 5, iclass 14, count 0 2006.203.08:07:52.34#ibcon#about to read 6, iclass 14, count 0 2006.203.08:07:52.34#ibcon#read 6, iclass 14, count 0 2006.203.08:07:52.34#ibcon#end of sib2, iclass 14, count 0 2006.203.08:07:52.34#ibcon#*after write, iclass 14, count 0 2006.203.08:07:52.34#ibcon#*before return 0, iclass 14, count 0 2006.203.08:07:52.34#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.203.08:07:52.35#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.203.08:07:52.35#ibcon#about to clear, iclass 14 cls_cnt 0 2006.203.08:07:52.35#ibcon#cleared, iclass 14 cls_cnt 0 2006.203.08:07:52.35$vc4f8/vb=3,4 2006.203.08:07:52.35#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.203.08:07:52.35#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.203.08:07:52.35#ibcon#ireg 11 cls_cnt 2 2006.203.08:07:52.35#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.203.08:07:52.39#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.203.08:07:52.39#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.203.08:07:52.39#ibcon#enter wrdev, iclass 16, count 2 2006.203.08:07:52.39#ibcon#first serial, iclass 16, count 2 2006.203.08:07:52.39#ibcon#enter sib2, iclass 16, count 2 2006.203.08:07:52.39#ibcon#flushed, iclass 16, count 2 2006.203.08:07:52.39#ibcon#about to write, iclass 16, count 2 2006.203.08:07:52.39#ibcon#wrote, iclass 16, count 2 2006.203.08:07:52.39#ibcon#about to read 3, iclass 16, count 2 2006.203.08:07:52.41#ibcon#read 3, iclass 16, count 2 2006.203.08:07:52.41#ibcon#about to read 4, iclass 16, count 2 2006.203.08:07:52.41#ibcon#read 4, iclass 16, count 2 2006.203.08:07:52.41#ibcon#about to read 5, iclass 16, count 2 2006.203.08:07:52.41#ibcon#read 5, iclass 16, count 2 2006.203.08:07:52.41#ibcon#about to read 6, iclass 16, count 2 2006.203.08:07:52.41#ibcon#read 6, iclass 16, count 2 2006.203.08:07:52.41#ibcon#end of sib2, iclass 16, count 2 2006.203.08:07:52.41#ibcon#*mode == 0, iclass 16, count 2 2006.203.08:07:52.41#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.203.08:07:52.42#ibcon#[27=AT03-04\r\n] 2006.203.08:07:52.42#ibcon#*before write, iclass 16, count 2 2006.203.08:07:52.42#ibcon#enter sib2, iclass 16, count 2 2006.203.08:07:52.42#ibcon#flushed, iclass 16, count 2 2006.203.08:07:52.42#ibcon#about to write, iclass 16, count 2 2006.203.08:07:52.42#ibcon#wrote, iclass 16, count 2 2006.203.08:07:52.42#ibcon#about to read 3, iclass 16, count 2 2006.203.08:07:52.44#ibcon#read 3, iclass 16, count 2 2006.203.08:07:52.44#ibcon#about to read 4, iclass 16, count 2 2006.203.08:07:52.44#ibcon#read 4, iclass 16, count 2 2006.203.08:07:52.44#ibcon#about to read 5, iclass 16, count 2 2006.203.08:07:52.44#ibcon#read 5, iclass 16, count 2 2006.203.08:07:52.44#ibcon#about to read 6, iclass 16, count 2 2006.203.08:07:52.44#ibcon#read 6, iclass 16, count 2 2006.203.08:07:52.44#ibcon#end of sib2, iclass 16, count 2 2006.203.08:07:52.44#ibcon#*after write, iclass 16, count 2 2006.203.08:07:52.44#ibcon#*before return 0, iclass 16, count 2 2006.203.08:07:52.44#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.203.08:07:52.45#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.203.08:07:52.45#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.203.08:07:52.45#ibcon#ireg 7 cls_cnt 0 2006.203.08:07:52.45#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.203.08:07:52.56#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.203.08:07:52.56#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.203.08:07:52.56#ibcon#enter wrdev, iclass 16, count 0 2006.203.08:07:52.56#ibcon#first serial, iclass 16, count 0 2006.203.08:07:52.56#ibcon#enter sib2, iclass 16, count 0 2006.203.08:07:52.56#ibcon#flushed, iclass 16, count 0 2006.203.08:07:52.56#ibcon#about to write, iclass 16, count 0 2006.203.08:07:52.56#ibcon#wrote, iclass 16, count 0 2006.203.08:07:52.56#ibcon#about to read 3, iclass 16, count 0 2006.203.08:07:52.58#ibcon#read 3, iclass 16, count 0 2006.203.08:07:52.58#ibcon#about to read 4, iclass 16, count 0 2006.203.08:07:52.58#ibcon#read 4, iclass 16, count 0 2006.203.08:07:52.58#ibcon#about to read 5, iclass 16, count 0 2006.203.08:07:52.58#ibcon#read 5, iclass 16, count 0 2006.203.08:07:52.58#ibcon#about to read 6, iclass 16, count 0 2006.203.08:07:52.58#ibcon#read 6, iclass 16, count 0 2006.203.08:07:52.58#ibcon#end of sib2, iclass 16, count 0 2006.203.08:07:52.58#ibcon#*mode == 0, iclass 16, count 0 2006.203.08:07:52.58#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.203.08:07:52.58#ibcon#[27=USB\r\n] 2006.203.08:07:52.58#ibcon#*before write, iclass 16, count 0 2006.203.08:07:52.58#ibcon#enter sib2, iclass 16, count 0 2006.203.08:07:52.59#ibcon#flushed, iclass 16, count 0 2006.203.08:07:52.59#ibcon#about to write, iclass 16, count 0 2006.203.08:07:52.59#ibcon#wrote, iclass 16, count 0 2006.203.08:07:52.59#ibcon#about to read 3, iclass 16, count 0 2006.203.08:07:52.61#ibcon#read 3, iclass 16, count 0 2006.203.08:07:52.61#ibcon#about to read 4, iclass 16, count 0 2006.203.08:07:52.61#ibcon#read 4, iclass 16, count 0 2006.203.08:07:52.61#ibcon#about to read 5, iclass 16, count 0 2006.203.08:07:52.61#ibcon#read 5, iclass 16, count 0 2006.203.08:07:52.61#ibcon#about to read 6, iclass 16, count 0 2006.203.08:07:52.61#ibcon#read 6, iclass 16, count 0 2006.203.08:07:52.61#ibcon#end of sib2, iclass 16, count 0 2006.203.08:07:52.61#ibcon#*after write, iclass 16, count 0 2006.203.08:07:52.61#ibcon#*before return 0, iclass 16, count 0 2006.203.08:07:52.61#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.203.08:07:52.61#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.203.08:07:52.62#ibcon#about to clear, iclass 16 cls_cnt 0 2006.203.08:07:52.62#ibcon#cleared, iclass 16 cls_cnt 0 2006.203.08:07:52.62$vc4f8/vblo=4,712.99 2006.203.08:07:52.62#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.203.08:07:52.62#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.203.08:07:52.62#ibcon#ireg 17 cls_cnt 0 2006.203.08:07:52.62#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.203.08:07:52.62#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.203.08:07:52.62#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.203.08:07:52.62#ibcon#enter wrdev, iclass 18, count 0 2006.203.08:07:52.62#ibcon#first serial, iclass 18, count 0 2006.203.08:07:52.62#ibcon#enter sib2, iclass 18, count 0 2006.203.08:07:52.62#ibcon#flushed, iclass 18, count 0 2006.203.08:07:52.62#ibcon#about to write, iclass 18, count 0 2006.203.08:07:52.62#ibcon#wrote, iclass 18, count 0 2006.203.08:07:52.62#ibcon#about to read 3, iclass 18, count 0 2006.203.08:07:52.63#ibcon#read 3, iclass 18, count 0 2006.203.08:07:52.63#ibcon#about to read 4, iclass 18, count 0 2006.203.08:07:52.63#ibcon#read 4, iclass 18, count 0 2006.203.08:07:52.63#ibcon#about to read 5, iclass 18, count 0 2006.203.08:07:52.63#ibcon#read 5, iclass 18, count 0 2006.203.08:07:52.63#ibcon#about to read 6, iclass 18, count 0 2006.203.08:07:52.63#ibcon#read 6, iclass 18, count 0 2006.203.08:07:52.63#ibcon#end of sib2, iclass 18, count 0 2006.203.08:07:52.63#ibcon#*mode == 0, iclass 18, count 0 2006.203.08:07:52.63#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.203.08:07:52.63#ibcon#[28=FRQ=04,712.99\r\n] 2006.203.08:07:52.63#ibcon#*before write, iclass 18, count 0 2006.203.08:07:52.63#ibcon#enter sib2, iclass 18, count 0 2006.203.08:07:52.64#ibcon#flushed, iclass 18, count 0 2006.203.08:07:52.64#ibcon#about to write, iclass 18, count 0 2006.203.08:07:52.64#ibcon#wrote, iclass 18, count 0 2006.203.08:07:52.64#ibcon#about to read 3, iclass 18, count 0 2006.203.08:07:52.67#ibcon#read 3, iclass 18, count 0 2006.203.08:07:52.67#ibcon#about to read 4, iclass 18, count 0 2006.203.08:07:52.67#ibcon#read 4, iclass 18, count 0 2006.203.08:07:52.67#ibcon#about to read 5, iclass 18, count 0 2006.203.08:07:52.67#ibcon#read 5, iclass 18, count 0 2006.203.08:07:52.67#ibcon#about to read 6, iclass 18, count 0 2006.203.08:07:52.67#ibcon#read 6, iclass 18, count 0 2006.203.08:07:52.67#ibcon#end of sib2, iclass 18, count 0 2006.203.08:07:52.67#ibcon#*after write, iclass 18, count 0 2006.203.08:07:52.67#ibcon#*before return 0, iclass 18, count 0 2006.203.08:07:52.67#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.203.08:07:52.68#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.203.08:07:52.68#ibcon#about to clear, iclass 18 cls_cnt 0 2006.203.08:07:52.68#ibcon#cleared, iclass 18 cls_cnt 0 2006.203.08:07:52.68$vc4f8/vb=4,4 2006.203.08:07:52.68#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.203.08:07:52.68#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.203.08:07:52.68#ibcon#ireg 11 cls_cnt 2 2006.203.08:07:52.68#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.203.08:07:52.72#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.203.08:07:52.72#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.203.08:07:52.72#ibcon#enter wrdev, iclass 20, count 2 2006.203.08:07:52.72#ibcon#first serial, iclass 20, count 2 2006.203.08:07:52.72#ibcon#enter sib2, iclass 20, count 2 2006.203.08:07:52.72#ibcon#flushed, iclass 20, count 2 2006.203.08:07:52.72#ibcon#about to write, iclass 20, count 2 2006.203.08:07:52.72#ibcon#wrote, iclass 20, count 2 2006.203.08:07:52.72#ibcon#about to read 3, iclass 20, count 2 2006.203.08:07:52.74#ibcon#read 3, iclass 20, count 2 2006.203.08:07:52.74#ibcon#about to read 4, iclass 20, count 2 2006.203.08:07:52.74#ibcon#read 4, iclass 20, count 2 2006.203.08:07:52.74#ibcon#about to read 5, iclass 20, count 2 2006.203.08:07:52.74#ibcon#read 5, iclass 20, count 2 2006.203.08:07:52.74#ibcon#about to read 6, iclass 20, count 2 2006.203.08:07:52.74#ibcon#read 6, iclass 20, count 2 2006.203.08:07:52.74#ibcon#end of sib2, iclass 20, count 2 2006.203.08:07:52.74#ibcon#*mode == 0, iclass 20, count 2 2006.203.08:07:52.74#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.203.08:07:52.74#ibcon#[27=AT04-04\r\n] 2006.203.08:07:52.74#ibcon#*before write, iclass 20, count 2 2006.203.08:07:52.74#ibcon#enter sib2, iclass 20, count 2 2006.203.08:07:52.75#ibcon#flushed, iclass 20, count 2 2006.203.08:07:52.75#ibcon#about to write, iclass 20, count 2 2006.203.08:07:52.75#ibcon#wrote, iclass 20, count 2 2006.203.08:07:52.75#ibcon#about to read 3, iclass 20, count 2 2006.203.08:07:52.77#ibcon#read 3, iclass 20, count 2 2006.203.08:07:52.77#ibcon#about to read 4, iclass 20, count 2 2006.203.08:07:52.77#ibcon#read 4, iclass 20, count 2 2006.203.08:07:52.77#ibcon#about to read 5, iclass 20, count 2 2006.203.08:07:52.77#ibcon#read 5, iclass 20, count 2 2006.203.08:07:52.77#ibcon#about to read 6, iclass 20, count 2 2006.203.08:07:52.77#ibcon#read 6, iclass 20, count 2 2006.203.08:07:52.77#ibcon#end of sib2, iclass 20, count 2 2006.203.08:07:52.77#ibcon#*after write, iclass 20, count 2 2006.203.08:07:52.77#ibcon#*before return 0, iclass 20, count 2 2006.203.08:07:52.77#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.203.08:07:52.78#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.203.08:07:52.78#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.203.08:07:52.78#ibcon#ireg 7 cls_cnt 0 2006.203.08:07:52.78#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.203.08:07:52.89#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.203.08:07:52.89#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.203.08:07:52.89#ibcon#enter wrdev, iclass 20, count 0 2006.203.08:07:52.89#ibcon#first serial, iclass 20, count 0 2006.203.08:07:52.89#ibcon#enter sib2, iclass 20, count 0 2006.203.08:07:52.89#ibcon#flushed, iclass 20, count 0 2006.203.08:07:52.89#ibcon#about to write, iclass 20, count 0 2006.203.08:07:52.89#ibcon#wrote, iclass 20, count 0 2006.203.08:07:52.89#ibcon#about to read 3, iclass 20, count 0 2006.203.08:07:52.91#ibcon#read 3, iclass 20, count 0 2006.203.08:07:52.91#ibcon#about to read 4, iclass 20, count 0 2006.203.08:07:52.91#ibcon#read 4, iclass 20, count 0 2006.203.08:07:52.91#ibcon#about to read 5, iclass 20, count 0 2006.203.08:07:52.91#ibcon#read 5, iclass 20, count 0 2006.203.08:07:52.91#ibcon#about to read 6, iclass 20, count 0 2006.203.08:07:52.91#ibcon#read 6, iclass 20, count 0 2006.203.08:07:52.91#ibcon#end of sib2, iclass 20, count 0 2006.203.08:07:52.91#ibcon#*mode == 0, iclass 20, count 0 2006.203.08:07:52.91#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.203.08:07:52.91#ibcon#[27=USB\r\n] 2006.203.08:07:52.91#ibcon#*before write, iclass 20, count 0 2006.203.08:07:52.91#ibcon#enter sib2, iclass 20, count 0 2006.203.08:07:52.92#ibcon#flushed, iclass 20, count 0 2006.203.08:07:52.92#ibcon#about to write, iclass 20, count 0 2006.203.08:07:52.92#ibcon#wrote, iclass 20, count 0 2006.203.08:07:52.92#ibcon#about to read 3, iclass 20, count 0 2006.203.08:07:52.94#ibcon#read 3, iclass 20, count 0 2006.203.08:07:52.94#ibcon#about to read 4, iclass 20, count 0 2006.203.08:07:52.94#ibcon#read 4, iclass 20, count 0 2006.203.08:07:52.94#ibcon#about to read 5, iclass 20, count 0 2006.203.08:07:52.94#ibcon#read 5, iclass 20, count 0 2006.203.08:07:52.94#ibcon#about to read 6, iclass 20, count 0 2006.203.08:07:52.94#ibcon#read 6, iclass 20, count 0 2006.203.08:07:52.94#ibcon#end of sib2, iclass 20, count 0 2006.203.08:07:52.94#ibcon#*after write, iclass 20, count 0 2006.203.08:07:52.94#ibcon#*before return 0, iclass 20, count 0 2006.203.08:07:52.94#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.203.08:07:52.94#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.203.08:07:52.95#ibcon#about to clear, iclass 20 cls_cnt 0 2006.203.08:07:52.95#ibcon#cleared, iclass 20 cls_cnt 0 2006.203.08:07:52.95$vc4f8/vblo=5,744.99 2006.203.08:07:52.95#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.203.08:07:52.95#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.203.08:07:52.95#ibcon#ireg 17 cls_cnt 0 2006.203.08:07:52.95#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.203.08:07:52.95#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.203.08:07:52.95#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.203.08:07:52.95#ibcon#enter wrdev, iclass 22, count 0 2006.203.08:07:52.95#ibcon#first serial, iclass 22, count 0 2006.203.08:07:52.95#ibcon#enter sib2, iclass 22, count 0 2006.203.08:07:52.95#ibcon#flushed, iclass 22, count 0 2006.203.08:07:52.95#ibcon#about to write, iclass 22, count 0 2006.203.08:07:52.95#ibcon#wrote, iclass 22, count 0 2006.203.08:07:52.95#ibcon#about to read 3, iclass 22, count 0 2006.203.08:07:52.97#ibcon#read 3, iclass 22, count 0 2006.203.08:07:52.97#ibcon#about to read 4, iclass 22, count 0 2006.203.08:07:52.97#ibcon#read 4, iclass 22, count 0 2006.203.08:07:52.97#ibcon#about to read 5, iclass 22, count 0 2006.203.08:07:52.97#ibcon#read 5, iclass 22, count 0 2006.203.08:07:52.97#ibcon#about to read 6, iclass 22, count 0 2006.203.08:07:52.97#ibcon#read 6, iclass 22, count 0 2006.203.08:07:52.97#ibcon#end of sib2, iclass 22, count 0 2006.203.08:07:52.97#ibcon#*mode == 0, iclass 22, count 0 2006.203.08:07:52.97#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.203.08:07:52.97#ibcon#[28=FRQ=05,744.99\r\n] 2006.203.08:07:52.97#ibcon#*before write, iclass 22, count 0 2006.203.08:07:52.97#ibcon#enter sib2, iclass 22, count 0 2006.203.08:07:52.97#ibcon#flushed, iclass 22, count 0 2006.203.08:07:52.97#ibcon#about to write, iclass 22, count 0 2006.203.08:07:52.97#ibcon#wrote, iclass 22, count 0 2006.203.08:07:52.97#ibcon#about to read 3, iclass 22, count 0 2006.203.08:07:53.01#ibcon#read 3, iclass 22, count 0 2006.203.08:07:53.01#ibcon#about to read 4, iclass 22, count 0 2006.203.08:07:53.01#ibcon#read 4, iclass 22, count 0 2006.203.08:07:53.01#ibcon#about to read 5, iclass 22, count 0 2006.203.08:07:53.01#ibcon#read 5, iclass 22, count 0 2006.203.08:07:53.01#ibcon#about to read 6, iclass 22, count 0 2006.203.08:07:53.01#ibcon#read 6, iclass 22, count 0 2006.203.08:07:53.01#ibcon#end of sib2, iclass 22, count 0 2006.203.08:07:53.01#ibcon#*after write, iclass 22, count 0 2006.203.08:07:53.01#ibcon#*before return 0, iclass 22, count 0 2006.203.08:07:53.02#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.203.08:07:53.02#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.203.08:07:53.02#ibcon#about to clear, iclass 22 cls_cnt 0 2006.203.08:07:53.02#ibcon#cleared, iclass 22 cls_cnt 0 2006.203.08:07:53.02$vc4f8/vb=5,3 2006.203.08:07:53.02#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.203.08:07:53.02#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.203.08:07:53.02#ibcon#ireg 11 cls_cnt 2 2006.203.08:07:53.02#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.203.08:07:53.05#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.203.08:07:53.05#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.203.08:07:53.05#ibcon#enter wrdev, iclass 24, count 2 2006.203.08:07:53.05#ibcon#first serial, iclass 24, count 2 2006.203.08:07:53.05#ibcon#enter sib2, iclass 24, count 2 2006.203.08:07:53.05#ibcon#flushed, iclass 24, count 2 2006.203.08:07:53.05#ibcon#about to write, iclass 24, count 2 2006.203.08:07:53.05#ibcon#wrote, iclass 24, count 2 2006.203.08:07:53.05#ibcon#about to read 3, iclass 24, count 2 2006.203.08:07:53.07#ibcon#read 3, iclass 24, count 2 2006.203.08:07:53.07#ibcon#about to read 4, iclass 24, count 2 2006.203.08:07:53.07#ibcon#read 4, iclass 24, count 2 2006.203.08:07:53.07#ibcon#about to read 5, iclass 24, count 2 2006.203.08:07:53.07#ibcon#read 5, iclass 24, count 2 2006.203.08:07:53.07#ibcon#about to read 6, iclass 24, count 2 2006.203.08:07:53.07#ibcon#read 6, iclass 24, count 2 2006.203.08:07:53.07#ibcon#end of sib2, iclass 24, count 2 2006.203.08:07:53.07#ibcon#*mode == 0, iclass 24, count 2 2006.203.08:07:53.07#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.203.08:07:53.07#ibcon#[27=AT05-03\r\n] 2006.203.08:07:53.07#ibcon#*before write, iclass 24, count 2 2006.203.08:07:53.07#ibcon#enter sib2, iclass 24, count 2 2006.203.08:07:53.07#ibcon#flushed, iclass 24, count 2 2006.203.08:07:53.08#ibcon#about to write, iclass 24, count 2 2006.203.08:07:53.08#ibcon#wrote, iclass 24, count 2 2006.203.08:07:53.08#ibcon#about to read 3, iclass 24, count 2 2006.203.08:07:53.10#ibcon#read 3, iclass 24, count 2 2006.203.08:07:53.10#ibcon#about to read 4, iclass 24, count 2 2006.203.08:07:53.10#ibcon#read 4, iclass 24, count 2 2006.203.08:07:53.10#ibcon#about to read 5, iclass 24, count 2 2006.203.08:07:53.10#ibcon#read 5, iclass 24, count 2 2006.203.08:07:53.10#ibcon#about to read 6, iclass 24, count 2 2006.203.08:07:53.10#ibcon#read 6, iclass 24, count 2 2006.203.08:07:53.10#ibcon#end of sib2, iclass 24, count 2 2006.203.08:07:53.10#ibcon#*after write, iclass 24, count 2 2006.203.08:07:53.10#ibcon#*before return 0, iclass 24, count 2 2006.203.08:07:53.10#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.203.08:07:53.11#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.203.08:07:53.11#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.203.08:07:53.11#ibcon#ireg 7 cls_cnt 0 2006.203.08:07:53.11#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.203.08:07:53.22#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.203.08:07:53.22#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.203.08:07:53.22#ibcon#enter wrdev, iclass 24, count 0 2006.203.08:07:53.22#ibcon#first serial, iclass 24, count 0 2006.203.08:07:53.22#ibcon#enter sib2, iclass 24, count 0 2006.203.08:07:53.22#ibcon#flushed, iclass 24, count 0 2006.203.08:07:53.22#ibcon#about to write, iclass 24, count 0 2006.203.08:07:53.22#ibcon#wrote, iclass 24, count 0 2006.203.08:07:53.22#ibcon#about to read 3, iclass 24, count 0 2006.203.08:07:53.24#ibcon#read 3, iclass 24, count 0 2006.203.08:07:53.24#ibcon#about to read 4, iclass 24, count 0 2006.203.08:07:53.24#ibcon#read 4, iclass 24, count 0 2006.203.08:07:53.24#ibcon#about to read 5, iclass 24, count 0 2006.203.08:07:53.24#ibcon#read 5, iclass 24, count 0 2006.203.08:07:53.24#ibcon#about to read 6, iclass 24, count 0 2006.203.08:07:53.24#ibcon#read 6, iclass 24, count 0 2006.203.08:07:53.24#ibcon#end of sib2, iclass 24, count 0 2006.203.08:07:53.24#ibcon#*mode == 0, iclass 24, count 0 2006.203.08:07:53.24#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.203.08:07:53.24#ibcon#[27=USB\r\n] 2006.203.08:07:53.24#ibcon#*before write, iclass 24, count 0 2006.203.08:07:53.24#ibcon#enter sib2, iclass 24, count 0 2006.203.08:07:53.25#ibcon#flushed, iclass 24, count 0 2006.203.08:07:53.25#ibcon#about to write, iclass 24, count 0 2006.203.08:07:53.25#ibcon#wrote, iclass 24, count 0 2006.203.08:07:53.25#ibcon#about to read 3, iclass 24, count 0 2006.203.08:07:53.27#ibcon#read 3, iclass 24, count 0 2006.203.08:07:53.27#ibcon#about to read 4, iclass 24, count 0 2006.203.08:07:53.27#ibcon#read 4, iclass 24, count 0 2006.203.08:07:53.27#ibcon#about to read 5, iclass 24, count 0 2006.203.08:07:53.27#ibcon#read 5, iclass 24, count 0 2006.203.08:07:53.27#ibcon#about to read 6, iclass 24, count 0 2006.203.08:07:53.27#ibcon#read 6, iclass 24, count 0 2006.203.08:07:53.27#ibcon#end of sib2, iclass 24, count 0 2006.203.08:07:53.27#ibcon#*after write, iclass 24, count 0 2006.203.08:07:53.27#ibcon#*before return 0, iclass 24, count 0 2006.203.08:07:53.27#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.203.08:07:53.27#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.203.08:07:53.27#ibcon#about to clear, iclass 24 cls_cnt 0 2006.203.08:07:53.28#ibcon#cleared, iclass 24 cls_cnt 0 2006.203.08:07:53.28$vc4f8/vblo=6,752.99 2006.203.08:07:53.28#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.203.08:07:53.28#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.203.08:07:53.28#ibcon#ireg 17 cls_cnt 0 2006.203.08:07:53.28#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.203.08:07:53.28#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.203.08:07:53.28#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.203.08:07:53.28#ibcon#enter wrdev, iclass 26, count 0 2006.203.08:07:53.28#ibcon#first serial, iclass 26, count 0 2006.203.08:07:53.28#ibcon#enter sib2, iclass 26, count 0 2006.203.08:07:53.28#ibcon#flushed, iclass 26, count 0 2006.203.08:07:53.28#ibcon#about to write, iclass 26, count 0 2006.203.08:07:53.28#ibcon#wrote, iclass 26, count 0 2006.203.08:07:53.28#ibcon#about to read 3, iclass 26, count 0 2006.203.08:07:53.29#ibcon#read 3, iclass 26, count 0 2006.203.08:07:53.29#ibcon#about to read 4, iclass 26, count 0 2006.203.08:07:53.29#ibcon#read 4, iclass 26, count 0 2006.203.08:07:53.29#ibcon#about to read 5, iclass 26, count 0 2006.203.08:07:53.29#ibcon#read 5, iclass 26, count 0 2006.203.08:07:53.29#ibcon#about to read 6, iclass 26, count 0 2006.203.08:07:53.29#ibcon#read 6, iclass 26, count 0 2006.203.08:07:53.29#ibcon#end of sib2, iclass 26, count 0 2006.203.08:07:53.29#ibcon#*mode == 0, iclass 26, count 0 2006.203.08:07:53.29#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.203.08:07:53.29#ibcon#[28=FRQ=06,752.99\r\n] 2006.203.08:07:53.29#ibcon#*before write, iclass 26, count 0 2006.203.08:07:53.29#ibcon#enter sib2, iclass 26, count 0 2006.203.08:07:53.30#ibcon#flushed, iclass 26, count 0 2006.203.08:07:53.30#ibcon#about to write, iclass 26, count 0 2006.203.08:07:53.30#ibcon#wrote, iclass 26, count 0 2006.203.08:07:53.30#ibcon#about to read 3, iclass 26, count 0 2006.203.08:07:53.33#ibcon#read 3, iclass 26, count 0 2006.203.08:07:53.33#ibcon#about to read 4, iclass 26, count 0 2006.203.08:07:53.33#ibcon#read 4, iclass 26, count 0 2006.203.08:07:53.33#ibcon#about to read 5, iclass 26, count 0 2006.203.08:07:53.33#ibcon#read 5, iclass 26, count 0 2006.203.08:07:53.33#ibcon#about to read 6, iclass 26, count 0 2006.203.08:07:53.33#ibcon#read 6, iclass 26, count 0 2006.203.08:07:53.33#ibcon#end of sib2, iclass 26, count 0 2006.203.08:07:53.33#ibcon#*after write, iclass 26, count 0 2006.203.08:07:53.33#ibcon#*before return 0, iclass 26, count 0 2006.203.08:07:53.33#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.203.08:07:53.33#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.203.08:07:53.34#ibcon#about to clear, iclass 26 cls_cnt 0 2006.203.08:07:53.34#ibcon#cleared, iclass 26 cls_cnt 0 2006.203.08:07:53.34$vc4f8/vb=6,4 2006.203.08:07:53.34#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.203.08:07:53.34#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.203.08:07:53.34#ibcon#ireg 11 cls_cnt 2 2006.203.08:07:53.34#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.203.08:07:53.38#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.203.08:07:53.38#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.203.08:07:53.38#ibcon#enter wrdev, iclass 28, count 2 2006.203.08:07:53.38#ibcon#first serial, iclass 28, count 2 2006.203.08:07:53.38#ibcon#enter sib2, iclass 28, count 2 2006.203.08:07:53.38#ibcon#flushed, iclass 28, count 2 2006.203.08:07:53.38#ibcon#about to write, iclass 28, count 2 2006.203.08:07:53.38#ibcon#wrote, iclass 28, count 2 2006.203.08:07:53.38#ibcon#about to read 3, iclass 28, count 2 2006.203.08:07:53.40#ibcon#read 3, iclass 28, count 2 2006.203.08:07:53.40#ibcon#about to read 4, iclass 28, count 2 2006.203.08:07:53.40#ibcon#read 4, iclass 28, count 2 2006.203.08:07:53.40#ibcon#about to read 5, iclass 28, count 2 2006.203.08:07:53.40#ibcon#read 5, iclass 28, count 2 2006.203.08:07:53.40#ibcon#about to read 6, iclass 28, count 2 2006.203.08:07:53.40#ibcon#read 6, iclass 28, count 2 2006.203.08:07:53.40#ibcon#end of sib2, iclass 28, count 2 2006.203.08:07:53.40#ibcon#*mode == 0, iclass 28, count 2 2006.203.08:07:53.41#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.203.08:07:53.41#ibcon#[27=AT06-04\r\n] 2006.203.08:07:53.41#ibcon#*before write, iclass 28, count 2 2006.203.08:07:53.41#ibcon#enter sib2, iclass 28, count 2 2006.203.08:07:53.41#ibcon#flushed, iclass 28, count 2 2006.203.08:07:53.41#ibcon#about to write, iclass 28, count 2 2006.203.08:07:53.41#ibcon#wrote, iclass 28, count 2 2006.203.08:07:53.41#ibcon#about to read 3, iclass 28, count 2 2006.203.08:07:53.43#ibcon#read 3, iclass 28, count 2 2006.203.08:07:53.43#ibcon#about to read 4, iclass 28, count 2 2006.203.08:07:53.43#ibcon#read 4, iclass 28, count 2 2006.203.08:07:53.43#ibcon#about to read 5, iclass 28, count 2 2006.203.08:07:53.43#ibcon#read 5, iclass 28, count 2 2006.203.08:07:53.43#ibcon#about to read 6, iclass 28, count 2 2006.203.08:07:53.43#ibcon#read 6, iclass 28, count 2 2006.203.08:07:53.43#ibcon#end of sib2, iclass 28, count 2 2006.203.08:07:53.43#ibcon#*after write, iclass 28, count 2 2006.203.08:07:53.43#ibcon#*before return 0, iclass 28, count 2 2006.203.08:07:53.43#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.203.08:07:53.44#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.203.08:07:53.44#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.203.08:07:53.44#ibcon#ireg 7 cls_cnt 0 2006.203.08:07:53.44#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.203.08:07:53.54#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.203.08:07:53.54#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.203.08:07:53.54#ibcon#enter wrdev, iclass 28, count 0 2006.203.08:07:53.54#ibcon#first serial, iclass 28, count 0 2006.203.08:07:53.54#ibcon#enter sib2, iclass 28, count 0 2006.203.08:07:53.54#ibcon#flushed, iclass 28, count 0 2006.203.08:07:53.54#ibcon#about to write, iclass 28, count 0 2006.203.08:07:53.54#ibcon#wrote, iclass 28, count 0 2006.203.08:07:53.54#ibcon#about to read 3, iclass 28, count 0 2006.203.08:07:53.56#ibcon#read 3, iclass 28, count 0 2006.203.08:07:53.56#ibcon#about to read 4, iclass 28, count 0 2006.203.08:07:53.56#ibcon#read 4, iclass 28, count 0 2006.203.08:07:53.56#ibcon#about to read 5, iclass 28, count 0 2006.203.08:07:53.56#ibcon#read 5, iclass 28, count 0 2006.203.08:07:53.56#ibcon#about to read 6, iclass 28, count 0 2006.203.08:07:53.56#ibcon#read 6, iclass 28, count 0 2006.203.08:07:53.56#ibcon#end of sib2, iclass 28, count 0 2006.203.08:07:53.56#ibcon#*mode == 0, iclass 28, count 0 2006.203.08:07:53.56#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.203.08:07:53.56#ibcon#[27=USB\r\n] 2006.203.08:07:53.56#ibcon#*before write, iclass 28, count 0 2006.203.08:07:53.56#ibcon#enter sib2, iclass 28, count 0 2006.203.08:07:53.56#ibcon#flushed, iclass 28, count 0 2006.203.08:07:53.57#ibcon#about to write, iclass 28, count 0 2006.203.08:07:53.57#ibcon#wrote, iclass 28, count 0 2006.203.08:07:53.57#ibcon#about to read 3, iclass 28, count 0 2006.203.08:07:53.59#ibcon#read 3, iclass 28, count 0 2006.203.08:07:53.59#ibcon#about to read 4, iclass 28, count 0 2006.203.08:07:53.59#ibcon#read 4, iclass 28, count 0 2006.203.08:07:53.59#ibcon#about to read 5, iclass 28, count 0 2006.203.08:07:53.59#ibcon#read 5, iclass 28, count 0 2006.203.08:07:53.59#ibcon#about to read 6, iclass 28, count 0 2006.203.08:07:53.59#ibcon#read 6, iclass 28, count 0 2006.203.08:07:53.59#ibcon#end of sib2, iclass 28, count 0 2006.203.08:07:53.59#ibcon#*after write, iclass 28, count 0 2006.203.08:07:53.59#ibcon#*before return 0, iclass 28, count 0 2006.203.08:07:53.59#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.203.08:07:53.59#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.203.08:07:53.59#ibcon#about to clear, iclass 28 cls_cnt 0 2006.203.08:07:53.60#ibcon#cleared, iclass 28 cls_cnt 0 2006.203.08:07:53.60$vc4f8/vabw=wide 2006.203.08:07:53.60#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.203.08:07:53.60#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.203.08:07:53.60#ibcon#ireg 8 cls_cnt 0 2006.203.08:07:53.60#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.203.08:07:53.60#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.203.08:07:53.60#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.203.08:07:53.60#ibcon#enter wrdev, iclass 30, count 0 2006.203.08:07:53.60#ibcon#first serial, iclass 30, count 0 2006.203.08:07:53.60#ibcon#enter sib2, iclass 30, count 0 2006.203.08:07:53.60#ibcon#flushed, iclass 30, count 0 2006.203.08:07:53.60#ibcon#about to write, iclass 30, count 0 2006.203.08:07:53.60#ibcon#wrote, iclass 30, count 0 2006.203.08:07:53.60#ibcon#about to read 3, iclass 30, count 0 2006.203.08:07:53.62#ibcon#read 3, iclass 30, count 0 2006.203.08:07:53.62#ibcon#about to read 4, iclass 30, count 0 2006.203.08:07:53.62#ibcon#read 4, iclass 30, count 0 2006.203.08:07:53.62#ibcon#about to read 5, iclass 30, count 0 2006.203.08:07:53.62#ibcon#read 5, iclass 30, count 0 2006.203.08:07:53.62#ibcon#about to read 6, iclass 30, count 0 2006.203.08:07:53.62#ibcon#read 6, iclass 30, count 0 2006.203.08:07:53.62#ibcon#end of sib2, iclass 30, count 0 2006.203.08:07:53.62#ibcon#*mode == 0, iclass 30, count 0 2006.203.08:07:53.62#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.203.08:07:53.62#ibcon#[25=BW32\r\n] 2006.203.08:07:53.62#ibcon#*before write, iclass 30, count 0 2006.203.08:07:53.62#ibcon#enter sib2, iclass 30, count 0 2006.203.08:07:53.62#ibcon#flushed, iclass 30, count 0 2006.203.08:07:53.62#ibcon#about to write, iclass 30, count 0 2006.203.08:07:53.62#ibcon#wrote, iclass 30, count 0 2006.203.08:07:53.62#ibcon#about to read 3, iclass 30, count 0 2006.203.08:07:53.65#ibcon#read 3, iclass 30, count 0 2006.203.08:07:53.65#ibcon#about to read 4, iclass 30, count 0 2006.203.08:07:53.65#ibcon#read 4, iclass 30, count 0 2006.203.08:07:53.65#ibcon#about to read 5, iclass 30, count 0 2006.203.08:07:53.65#ibcon#read 5, iclass 30, count 0 2006.203.08:07:53.65#ibcon#about to read 6, iclass 30, count 0 2006.203.08:07:53.65#ibcon#read 6, iclass 30, count 0 2006.203.08:07:53.65#ibcon#end of sib2, iclass 30, count 0 2006.203.08:07:53.65#ibcon#*after write, iclass 30, count 0 2006.203.08:07:53.65#ibcon#*before return 0, iclass 30, count 0 2006.203.08:07:53.65#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.203.08:07:53.66#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.203.08:07:53.66#ibcon#about to clear, iclass 30 cls_cnt 0 2006.203.08:07:53.66#ibcon#cleared, iclass 30 cls_cnt 0 2006.203.08:07:53.66$vc4f8/vbbw=wide 2006.203.08:07:53.66#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.203.08:07:53.66#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.203.08:07:53.66#ibcon#ireg 8 cls_cnt 0 2006.203.08:07:53.66#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.203.08:07:53.70#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.203.08:07:53.70#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.203.08:07:53.70#ibcon#enter wrdev, iclass 32, count 0 2006.203.08:07:53.70#ibcon#first serial, iclass 32, count 0 2006.203.08:07:53.70#ibcon#enter sib2, iclass 32, count 0 2006.203.08:07:53.70#ibcon#flushed, iclass 32, count 0 2006.203.08:07:53.70#ibcon#about to write, iclass 32, count 0 2006.203.08:07:53.70#ibcon#wrote, iclass 32, count 0 2006.203.08:07:53.70#ibcon#about to read 3, iclass 32, count 0 2006.203.08:07:53.72#ibcon#read 3, iclass 32, count 0 2006.203.08:07:53.72#ibcon#about to read 4, iclass 32, count 0 2006.203.08:07:53.72#ibcon#read 4, iclass 32, count 0 2006.203.08:07:53.72#ibcon#about to read 5, iclass 32, count 0 2006.203.08:07:53.72#ibcon#read 5, iclass 32, count 0 2006.203.08:07:53.72#ibcon#about to read 6, iclass 32, count 0 2006.203.08:07:53.72#ibcon#read 6, iclass 32, count 0 2006.203.08:07:53.72#ibcon#end of sib2, iclass 32, count 0 2006.203.08:07:53.72#ibcon#*mode == 0, iclass 32, count 0 2006.203.08:07:53.72#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.203.08:07:53.73#ibcon#[27=BW32\r\n] 2006.203.08:07:53.73#ibcon#*before write, iclass 32, count 0 2006.203.08:07:53.73#ibcon#enter sib2, iclass 32, count 0 2006.203.08:07:53.73#ibcon#flushed, iclass 32, count 0 2006.203.08:07:53.73#ibcon#about to write, iclass 32, count 0 2006.203.08:07:53.73#ibcon#wrote, iclass 32, count 0 2006.203.08:07:53.73#ibcon#about to read 3, iclass 32, count 0 2006.203.08:07:53.75#ibcon#read 3, iclass 32, count 0 2006.203.08:07:53.75#ibcon#about to read 4, iclass 32, count 0 2006.203.08:07:53.75#ibcon#read 4, iclass 32, count 0 2006.203.08:07:53.75#ibcon#about to read 5, iclass 32, count 0 2006.203.08:07:53.75#ibcon#read 5, iclass 32, count 0 2006.203.08:07:53.75#ibcon#about to read 6, iclass 32, count 0 2006.203.08:07:53.75#ibcon#read 6, iclass 32, count 0 2006.203.08:07:53.75#ibcon#end of sib2, iclass 32, count 0 2006.203.08:07:53.75#ibcon#*after write, iclass 32, count 0 2006.203.08:07:53.75#ibcon#*before return 0, iclass 32, count 0 2006.203.08:07:53.75#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.203.08:07:53.76#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.203.08:07:53.76#ibcon#about to clear, iclass 32 cls_cnt 0 2006.203.08:07:53.76#ibcon#cleared, iclass 32 cls_cnt 0 2006.203.08:07:53.76$4f8m12a/ifd4f 2006.203.08:07:53.76$ifd4f/lo= 2006.203.08:07:53.76$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.203.08:07:53.76$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.203.08:07:53.76$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.203.08:07:53.76$ifd4f/patch= 2006.203.08:07:53.76$ifd4f/patch=lo1,a1,a2,a3,a4 2006.203.08:07:53.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.203.08:07:53.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.203.08:07:53.76$4f8m12a/"form=m,16.000,1:2 2006.203.08:07:53.76$4f8m12a/"tpicd 2006.203.08:07:53.76$4f8m12a/echo=off 2006.203.08:07:53.76$4f8m12a/xlog=off 2006.203.08:07:53.76:!2006.203.08:08:20 2006.203.08:08:03.14#trakl#Source acquired 2006.203.08:08:05.15#flagr#flagr/antenna,acquired 2006.203.08:08:20.02:preob 2006.203.08:08:21.15/onsource/TRACKING 2006.203.08:08:21.15:!2006.203.08:08:30 2006.203.08:08:30.02:data_valid=on 2006.203.08:08:30.02:midob 2006.203.08:08:31.15/onsource/TRACKING 2006.203.08:08:31.15/wx/23.67,1001.1,100 2006.203.08:08:31.23/cable/+6.4589E-03 2006.203.08:08:32.32/va/01,08,usb,yes,29,30 2006.203.08:08:32.32/va/02,07,usb,yes,29,30 2006.203.08:08:32.32/va/03,08,usb,yes,22,22 2006.203.08:08:32.32/va/04,07,usb,yes,30,32 2006.203.08:08:32.32/va/05,07,usb,yes,33,34 2006.203.08:08:32.32/va/06,06,usb,yes,32,31 2006.203.08:08:32.32/va/07,07,usb,yes,28,28 2006.203.08:08:32.32/va/08,06,usb,yes,35,34 2006.203.08:08:32.55/valo/01,532.99,yes,locked 2006.203.08:08:32.55/valo/02,572.99,yes,locked 2006.203.08:08:32.55/valo/03,672.99,yes,locked 2006.203.08:08:32.55/valo/04,832.99,yes,locked 2006.203.08:08:32.55/valo/05,652.99,yes,locked 2006.203.08:08:32.55/valo/06,772.99,yes,locked 2006.203.08:08:32.55/valo/07,832.99,yes,locked 2006.203.08:08:32.55/valo/08,852.99,yes,locked 2006.203.08:08:33.64/vb/01,04,usb,yes,28,27 2006.203.08:08:33.64/vb/02,04,usb,yes,30,31 2006.203.08:08:33.64/vb/03,04,usb,yes,26,30 2006.203.08:08:33.64/vb/04,04,usb,yes,27,27 2006.203.08:08:33.64/vb/05,03,usb,yes,32,37 2006.203.08:08:33.64/vb/06,04,usb,yes,27,29 2006.203.08:08:33.64/vb/07,04,usb,yes,29,29 2006.203.08:08:33.64/vb/08,04,usb,yes,26,30 2006.203.08:08:33.87/vblo/01,632.99,yes,locked 2006.203.08:08:33.87/vblo/02,640.99,yes,locked 2006.203.08:08:33.87/vblo/03,656.99,yes,locked 2006.203.08:08:33.87/vblo/04,712.99,yes,locked 2006.203.08:08:33.87/vblo/05,744.99,yes,locked 2006.203.08:08:33.87/vblo/06,752.99,yes,locked 2006.203.08:08:33.87/vblo/07,734.99,yes,locked 2006.203.08:08:33.87/vblo/08,744.99,yes,locked 2006.203.08:08:34.02/vabw/8 2006.203.08:08:34.17/vbbw/8 2006.203.08:08:34.26/xfe/off,on,12.5 2006.203.08:08:34.63/ifatt/23,28,28,28 2006.203.08:08:35.07/fmout-gps/S +4.57E-07 2006.203.08:08:35.15:!2006.203.08:09:30 2006.203.08:09:30.02:data_valid=off 2006.203.08:09:30.02:postob 2006.203.08:09:30.15/cable/+6.4587E-03 2006.203.08:09:30.15/wx/23.65,1001.1,100 2006.203.08:09:31.07/fmout-gps/S +4.56E-07 2006.203.08:09:31.08:scan_name=203-0810,k06203,60 2006.203.08:09:31.08:source=1418+546,141946.60,542314.8,2000.0,cw 2006.203.08:09:32.15#flagr#flagr/antenna,new-source 2006.203.08:09:32.15:checkk5 2006.203.08:09:32.58/chk_autoobs//k5ts1/ autoobs is running! 2006.203.08:09:33.00/chk_autoobs//k5ts2/ autoobs is running! 2006.203.08:09:33.43/chk_autoobs//k5ts3/ autoobs is running! 2006.203.08:09:33.85/chk_autoobs//k5ts4/ autoobs is running! 2006.203.08:09:34.27/chk_obsdata//k5ts1/T2030808??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.08:09:34.68/chk_obsdata//k5ts2/T2030808??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.08:09:35.08/chk_obsdata//k5ts3/T2030808??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.08:09:35.72/chk_obsdata//k5ts4/T2030808??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.08:09:37.15/k5log//k5ts1_log_newline 2006.203.08:09:37.90/k5log//k5ts2_log_newline 2006.203.08:09:38.67/k5log//k5ts3_log_newline 2006.203.08:09:39.57/k5log//k5ts4_log_newline 2006.203.08:09:39.60/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.203.08:09:39.60:4f8m12a=2 2006.203.08:09:39.60$4f8m12a/echo=on 2006.203.08:09:39.60$4f8m12a/pcalon 2006.203.08:09:39.60$pcalon/"no phase cal control is implemented here 2006.203.08:09:39.60$4f8m12a/"tpicd=stop 2006.203.08:09:39.60$4f8m12a/vc4f8 2006.203.08:09:39.60$vc4f8/valo=1,532.99 2006.203.08:09:39.60#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.203.08:09:39.60#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.203.08:09:39.60#ibcon#ireg 17 cls_cnt 0 2006.203.08:09:39.60#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.203.08:09:39.60#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.203.08:09:39.60#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.203.08:09:39.60#ibcon#enter wrdev, iclass 39, count 0 2006.203.08:09:39.60#ibcon#first serial, iclass 39, count 0 2006.203.08:09:39.60#ibcon#enter sib2, iclass 39, count 0 2006.203.08:09:39.60#ibcon#flushed, iclass 39, count 0 2006.203.08:09:39.60#ibcon#about to write, iclass 39, count 0 2006.203.08:09:39.60#ibcon#wrote, iclass 39, count 0 2006.203.08:09:39.60#ibcon#about to read 3, iclass 39, count 0 2006.203.08:09:39.64#ibcon#read 3, iclass 39, count 0 2006.203.08:09:39.64#ibcon#about to read 4, iclass 39, count 0 2006.203.08:09:39.64#ibcon#read 4, iclass 39, count 0 2006.203.08:09:39.64#ibcon#about to read 5, iclass 39, count 0 2006.203.08:09:39.64#ibcon#read 5, iclass 39, count 0 2006.203.08:09:39.64#ibcon#about to read 6, iclass 39, count 0 2006.203.08:09:39.64#ibcon#read 6, iclass 39, count 0 2006.203.08:09:39.64#ibcon#end of sib2, iclass 39, count 0 2006.203.08:09:39.64#ibcon#*mode == 0, iclass 39, count 0 2006.203.08:09:39.64#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.203.08:09:39.64#ibcon#[26=FRQ=01,532.99\r\n] 2006.203.08:09:39.64#ibcon#*before write, iclass 39, count 0 2006.203.08:09:39.64#ibcon#enter sib2, iclass 39, count 0 2006.203.08:09:39.64#ibcon#flushed, iclass 39, count 0 2006.203.08:09:39.64#ibcon#about to write, iclass 39, count 0 2006.203.08:09:39.64#ibcon#wrote, iclass 39, count 0 2006.203.08:09:39.64#ibcon#about to read 3, iclass 39, count 0 2006.203.08:09:39.69#ibcon#read 3, iclass 39, count 0 2006.203.08:09:39.69#ibcon#about to read 4, iclass 39, count 0 2006.203.08:09:39.69#ibcon#read 4, iclass 39, count 0 2006.203.08:09:39.69#ibcon#about to read 5, iclass 39, count 0 2006.203.08:09:39.69#ibcon#read 5, iclass 39, count 0 2006.203.08:09:39.69#ibcon#about to read 6, iclass 39, count 0 2006.203.08:09:39.69#ibcon#read 6, iclass 39, count 0 2006.203.08:09:39.69#ibcon#end of sib2, iclass 39, count 0 2006.203.08:09:39.69#ibcon#*after write, iclass 39, count 0 2006.203.08:09:39.69#ibcon#*before return 0, iclass 39, count 0 2006.203.08:09:39.69#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.203.08:09:39.69#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.203.08:09:39.69#ibcon#about to clear, iclass 39 cls_cnt 0 2006.203.08:09:39.69#ibcon#cleared, iclass 39 cls_cnt 0 2006.203.08:09:39.70$vc4f8/va=1,8 2006.203.08:09:39.70#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.203.08:09:39.70#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.203.08:09:39.70#ibcon#ireg 11 cls_cnt 2 2006.203.08:09:39.70#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.203.08:09:39.70#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.203.08:09:39.70#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.203.08:09:39.70#ibcon#enter wrdev, iclass 3, count 2 2006.203.08:09:39.70#ibcon#first serial, iclass 3, count 2 2006.203.08:09:39.70#ibcon#enter sib2, iclass 3, count 2 2006.203.08:09:39.70#ibcon#flushed, iclass 3, count 2 2006.203.08:09:39.70#ibcon#about to write, iclass 3, count 2 2006.203.08:09:39.70#ibcon#wrote, iclass 3, count 2 2006.203.08:09:39.70#ibcon#about to read 3, iclass 3, count 2 2006.203.08:09:39.72#ibcon#read 3, iclass 3, count 2 2006.203.08:09:39.72#ibcon#about to read 4, iclass 3, count 2 2006.203.08:09:39.72#ibcon#read 4, iclass 3, count 2 2006.203.08:09:39.72#ibcon#about to read 5, iclass 3, count 2 2006.203.08:09:39.72#ibcon#read 5, iclass 3, count 2 2006.203.08:09:39.72#ibcon#about to read 6, iclass 3, count 2 2006.203.08:09:39.72#ibcon#read 6, iclass 3, count 2 2006.203.08:09:39.72#ibcon#end of sib2, iclass 3, count 2 2006.203.08:09:39.72#ibcon#*mode == 0, iclass 3, count 2 2006.203.08:09:39.72#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.203.08:09:39.72#ibcon#[25=AT01-08\r\n] 2006.203.08:09:39.72#ibcon#*before write, iclass 3, count 2 2006.203.08:09:39.72#ibcon#enter sib2, iclass 3, count 2 2006.203.08:09:39.72#ibcon#flushed, iclass 3, count 2 2006.203.08:09:39.72#ibcon#about to write, iclass 3, count 2 2006.203.08:09:39.72#ibcon#wrote, iclass 3, count 2 2006.203.08:09:39.72#ibcon#about to read 3, iclass 3, count 2 2006.203.08:09:39.75#ibcon#read 3, iclass 3, count 2 2006.203.08:09:39.75#ibcon#about to read 4, iclass 3, count 2 2006.203.08:09:39.75#ibcon#read 4, iclass 3, count 2 2006.203.08:09:39.75#ibcon#about to read 5, iclass 3, count 2 2006.203.08:09:39.75#ibcon#read 5, iclass 3, count 2 2006.203.08:09:39.75#ibcon#about to read 6, iclass 3, count 2 2006.203.08:09:39.75#ibcon#read 6, iclass 3, count 2 2006.203.08:09:39.75#ibcon#end of sib2, iclass 3, count 2 2006.203.08:09:39.75#ibcon#*after write, iclass 3, count 2 2006.203.08:09:39.75#ibcon#*before return 0, iclass 3, count 2 2006.203.08:09:39.75#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.203.08:09:39.75#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.203.08:09:39.75#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.203.08:09:39.75#ibcon#ireg 7 cls_cnt 0 2006.203.08:09:39.75#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.203.08:09:39.87#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.203.08:09:39.87#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.203.08:09:39.87#ibcon#enter wrdev, iclass 3, count 0 2006.203.08:09:39.87#ibcon#first serial, iclass 3, count 0 2006.203.08:09:39.87#ibcon#enter sib2, iclass 3, count 0 2006.203.08:09:39.87#ibcon#flushed, iclass 3, count 0 2006.203.08:09:39.87#ibcon#about to write, iclass 3, count 0 2006.203.08:09:39.87#ibcon#wrote, iclass 3, count 0 2006.203.08:09:39.87#ibcon#about to read 3, iclass 3, count 0 2006.203.08:09:39.89#ibcon#read 3, iclass 3, count 0 2006.203.08:09:39.89#ibcon#about to read 4, iclass 3, count 0 2006.203.08:09:39.89#ibcon#read 4, iclass 3, count 0 2006.203.08:09:39.89#ibcon#about to read 5, iclass 3, count 0 2006.203.08:09:39.89#ibcon#read 5, iclass 3, count 0 2006.203.08:09:39.89#ibcon#about to read 6, iclass 3, count 0 2006.203.08:09:39.89#ibcon#read 6, iclass 3, count 0 2006.203.08:09:39.89#ibcon#end of sib2, iclass 3, count 0 2006.203.08:09:39.89#ibcon#*mode == 0, iclass 3, count 0 2006.203.08:09:39.89#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.203.08:09:39.89#ibcon#[25=USB\r\n] 2006.203.08:09:39.89#ibcon#*before write, iclass 3, count 0 2006.203.08:09:39.89#ibcon#enter sib2, iclass 3, count 0 2006.203.08:09:39.89#ibcon#flushed, iclass 3, count 0 2006.203.08:09:39.89#ibcon#about to write, iclass 3, count 0 2006.203.08:09:39.89#ibcon#wrote, iclass 3, count 0 2006.203.08:09:39.89#ibcon#about to read 3, iclass 3, count 0 2006.203.08:09:39.92#ibcon#read 3, iclass 3, count 0 2006.203.08:09:39.92#ibcon#about to read 4, iclass 3, count 0 2006.203.08:09:39.92#ibcon#read 4, iclass 3, count 0 2006.203.08:09:39.92#ibcon#about to read 5, iclass 3, count 0 2006.203.08:09:39.92#ibcon#read 5, iclass 3, count 0 2006.203.08:09:39.92#ibcon#about to read 6, iclass 3, count 0 2006.203.08:09:39.92#ibcon#read 6, iclass 3, count 0 2006.203.08:09:39.92#ibcon#end of sib2, iclass 3, count 0 2006.203.08:09:39.92#ibcon#*after write, iclass 3, count 0 2006.203.08:09:39.92#ibcon#*before return 0, iclass 3, count 0 2006.203.08:09:39.92#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.203.08:09:39.92#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.203.08:09:39.92#ibcon#about to clear, iclass 3 cls_cnt 0 2006.203.08:09:39.92#ibcon#cleared, iclass 3 cls_cnt 0 2006.203.08:09:39.93$vc4f8/valo=2,572.99 2006.203.08:09:39.93#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.203.08:09:39.93#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.203.08:09:39.93#ibcon#ireg 17 cls_cnt 0 2006.203.08:09:39.93#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.203.08:09:39.93#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.203.08:09:39.93#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.203.08:09:39.93#ibcon#enter wrdev, iclass 5, count 0 2006.203.08:09:39.93#ibcon#first serial, iclass 5, count 0 2006.203.08:09:39.93#ibcon#enter sib2, iclass 5, count 0 2006.203.08:09:39.93#ibcon#flushed, iclass 5, count 0 2006.203.08:09:39.93#ibcon#about to write, iclass 5, count 0 2006.203.08:09:39.93#ibcon#wrote, iclass 5, count 0 2006.203.08:09:39.93#ibcon#about to read 3, iclass 5, count 0 2006.203.08:09:39.95#ibcon#read 3, iclass 5, count 0 2006.203.08:09:39.95#ibcon#about to read 4, iclass 5, count 0 2006.203.08:09:39.95#ibcon#read 4, iclass 5, count 0 2006.203.08:09:39.95#ibcon#about to read 5, iclass 5, count 0 2006.203.08:09:39.95#ibcon#read 5, iclass 5, count 0 2006.203.08:09:39.95#ibcon#about to read 6, iclass 5, count 0 2006.203.08:09:39.95#ibcon#read 6, iclass 5, count 0 2006.203.08:09:39.95#ibcon#end of sib2, iclass 5, count 0 2006.203.08:09:39.95#ibcon#*mode == 0, iclass 5, count 0 2006.203.08:09:39.95#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.203.08:09:39.95#ibcon#[26=FRQ=02,572.99\r\n] 2006.203.08:09:39.95#ibcon#*before write, iclass 5, count 0 2006.203.08:09:39.95#ibcon#enter sib2, iclass 5, count 0 2006.203.08:09:39.95#ibcon#flushed, iclass 5, count 0 2006.203.08:09:39.95#ibcon#about to write, iclass 5, count 0 2006.203.08:09:39.95#ibcon#wrote, iclass 5, count 0 2006.203.08:09:39.95#ibcon#about to read 3, iclass 5, count 0 2006.203.08:09:39.99#ibcon#read 3, iclass 5, count 0 2006.203.08:09:39.99#ibcon#about to read 4, iclass 5, count 0 2006.203.08:09:39.99#ibcon#read 4, iclass 5, count 0 2006.203.08:09:39.99#ibcon#about to read 5, iclass 5, count 0 2006.203.08:09:39.99#ibcon#read 5, iclass 5, count 0 2006.203.08:09:39.99#ibcon#about to read 6, iclass 5, count 0 2006.203.08:09:39.99#ibcon#read 6, iclass 5, count 0 2006.203.08:09:39.99#ibcon#end of sib2, iclass 5, count 0 2006.203.08:09:39.99#ibcon#*after write, iclass 5, count 0 2006.203.08:09:39.99#ibcon#*before return 0, iclass 5, count 0 2006.203.08:09:39.99#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.203.08:09:39.99#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.203.08:09:39.99#ibcon#about to clear, iclass 5 cls_cnt 0 2006.203.08:09:39.99#ibcon#cleared, iclass 5 cls_cnt 0 2006.203.08:09:40.00$vc4f8/va=2,7 2006.203.08:09:40.00#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.203.08:09:40.00#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.203.08:09:40.00#ibcon#ireg 11 cls_cnt 2 2006.203.08:09:40.00#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.203.08:09:40.03#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.203.08:09:40.03#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.203.08:09:40.03#ibcon#enter wrdev, iclass 7, count 2 2006.203.08:09:40.03#ibcon#first serial, iclass 7, count 2 2006.203.08:09:40.03#ibcon#enter sib2, iclass 7, count 2 2006.203.08:09:40.03#ibcon#flushed, iclass 7, count 2 2006.203.08:09:40.03#ibcon#about to write, iclass 7, count 2 2006.203.08:09:40.03#ibcon#wrote, iclass 7, count 2 2006.203.08:09:40.03#ibcon#about to read 3, iclass 7, count 2 2006.203.08:09:40.05#ibcon#read 3, iclass 7, count 2 2006.203.08:09:40.05#ibcon#about to read 4, iclass 7, count 2 2006.203.08:09:40.05#ibcon#read 4, iclass 7, count 2 2006.203.08:09:40.05#ibcon#about to read 5, iclass 7, count 2 2006.203.08:09:40.05#ibcon#read 5, iclass 7, count 2 2006.203.08:09:40.05#ibcon#about to read 6, iclass 7, count 2 2006.203.08:09:40.05#ibcon#read 6, iclass 7, count 2 2006.203.08:09:40.05#ibcon#end of sib2, iclass 7, count 2 2006.203.08:09:40.05#ibcon#*mode == 0, iclass 7, count 2 2006.203.08:09:40.05#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.203.08:09:40.05#ibcon#[25=AT02-07\r\n] 2006.203.08:09:40.05#ibcon#*before write, iclass 7, count 2 2006.203.08:09:40.05#ibcon#enter sib2, iclass 7, count 2 2006.203.08:09:40.05#ibcon#flushed, iclass 7, count 2 2006.203.08:09:40.05#ibcon#about to write, iclass 7, count 2 2006.203.08:09:40.05#ibcon#wrote, iclass 7, count 2 2006.203.08:09:40.05#ibcon#about to read 3, iclass 7, count 2 2006.203.08:09:40.08#ibcon#read 3, iclass 7, count 2 2006.203.08:09:40.08#ibcon#about to read 4, iclass 7, count 2 2006.203.08:09:40.08#ibcon#read 4, iclass 7, count 2 2006.203.08:09:40.08#ibcon#about to read 5, iclass 7, count 2 2006.203.08:09:40.08#ibcon#read 5, iclass 7, count 2 2006.203.08:09:40.08#ibcon#about to read 6, iclass 7, count 2 2006.203.08:09:40.08#ibcon#read 6, iclass 7, count 2 2006.203.08:09:40.08#ibcon#end of sib2, iclass 7, count 2 2006.203.08:09:40.08#ibcon#*after write, iclass 7, count 2 2006.203.08:09:40.08#ibcon#*before return 0, iclass 7, count 2 2006.203.08:09:40.08#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.203.08:09:40.08#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.203.08:09:40.08#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.203.08:09:40.08#ibcon#ireg 7 cls_cnt 0 2006.203.08:09:40.08#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.203.08:09:40.20#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.203.08:09:40.20#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.203.08:09:40.20#ibcon#enter wrdev, iclass 7, count 0 2006.203.08:09:40.20#ibcon#first serial, iclass 7, count 0 2006.203.08:09:40.20#ibcon#enter sib2, iclass 7, count 0 2006.203.08:09:40.20#ibcon#flushed, iclass 7, count 0 2006.203.08:09:40.20#ibcon#about to write, iclass 7, count 0 2006.203.08:09:40.20#ibcon#wrote, iclass 7, count 0 2006.203.08:09:40.20#ibcon#about to read 3, iclass 7, count 0 2006.203.08:09:40.22#ibcon#read 3, iclass 7, count 0 2006.203.08:09:40.22#ibcon#about to read 4, iclass 7, count 0 2006.203.08:09:40.22#ibcon#read 4, iclass 7, count 0 2006.203.08:09:40.22#ibcon#about to read 5, iclass 7, count 0 2006.203.08:09:40.22#ibcon#read 5, iclass 7, count 0 2006.203.08:09:40.22#ibcon#about to read 6, iclass 7, count 0 2006.203.08:09:40.22#ibcon#read 6, iclass 7, count 0 2006.203.08:09:40.22#ibcon#end of sib2, iclass 7, count 0 2006.203.08:09:40.22#ibcon#*mode == 0, iclass 7, count 0 2006.203.08:09:40.22#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.203.08:09:40.22#ibcon#[25=USB\r\n] 2006.203.08:09:40.22#ibcon#*before write, iclass 7, count 0 2006.203.08:09:40.22#ibcon#enter sib2, iclass 7, count 0 2006.203.08:09:40.22#ibcon#flushed, iclass 7, count 0 2006.203.08:09:40.22#ibcon#about to write, iclass 7, count 0 2006.203.08:09:40.22#ibcon#wrote, iclass 7, count 0 2006.203.08:09:40.22#ibcon#about to read 3, iclass 7, count 0 2006.203.08:09:40.25#ibcon#read 3, iclass 7, count 0 2006.203.08:09:40.25#ibcon#about to read 4, iclass 7, count 0 2006.203.08:09:40.25#ibcon#read 4, iclass 7, count 0 2006.203.08:09:40.25#ibcon#about to read 5, iclass 7, count 0 2006.203.08:09:40.25#ibcon#read 5, iclass 7, count 0 2006.203.08:09:40.25#ibcon#about to read 6, iclass 7, count 0 2006.203.08:09:40.25#ibcon#read 6, iclass 7, count 0 2006.203.08:09:40.25#ibcon#end of sib2, iclass 7, count 0 2006.203.08:09:40.25#ibcon#*after write, iclass 7, count 0 2006.203.08:09:40.25#ibcon#*before return 0, iclass 7, count 0 2006.203.08:09:40.25#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.203.08:09:40.25#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.203.08:09:40.25#ibcon#about to clear, iclass 7 cls_cnt 0 2006.203.08:09:40.25#ibcon#cleared, iclass 7 cls_cnt 0 2006.203.08:09:40.26$vc4f8/valo=3,672.99 2006.203.08:09:40.26#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.203.08:09:40.26#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.203.08:09:40.26#ibcon#ireg 17 cls_cnt 0 2006.203.08:09:40.26#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.203.08:09:40.26#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.203.08:09:40.26#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.203.08:09:40.26#ibcon#enter wrdev, iclass 11, count 0 2006.203.08:09:40.26#ibcon#first serial, iclass 11, count 0 2006.203.08:09:40.26#ibcon#enter sib2, iclass 11, count 0 2006.203.08:09:40.26#ibcon#flushed, iclass 11, count 0 2006.203.08:09:40.26#ibcon#about to write, iclass 11, count 0 2006.203.08:09:40.26#ibcon#wrote, iclass 11, count 0 2006.203.08:09:40.26#ibcon#about to read 3, iclass 11, count 0 2006.203.08:09:40.27#ibcon#read 3, iclass 11, count 0 2006.203.08:09:40.27#ibcon#about to read 4, iclass 11, count 0 2006.203.08:09:40.27#ibcon#read 4, iclass 11, count 0 2006.203.08:09:40.27#ibcon#about to read 5, iclass 11, count 0 2006.203.08:09:40.27#ibcon#read 5, iclass 11, count 0 2006.203.08:09:40.27#ibcon#about to read 6, iclass 11, count 0 2006.203.08:09:40.27#ibcon#read 6, iclass 11, count 0 2006.203.08:09:40.27#ibcon#end of sib2, iclass 11, count 0 2006.203.08:09:40.27#ibcon#*mode == 0, iclass 11, count 0 2006.203.08:09:40.27#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.203.08:09:40.27#ibcon#[26=FRQ=03,672.99\r\n] 2006.203.08:09:40.27#ibcon#*before write, iclass 11, count 0 2006.203.08:09:40.27#ibcon#enter sib2, iclass 11, count 0 2006.203.08:09:40.27#ibcon#flushed, iclass 11, count 0 2006.203.08:09:40.27#ibcon#about to write, iclass 11, count 0 2006.203.08:09:40.27#ibcon#wrote, iclass 11, count 0 2006.203.08:09:40.27#ibcon#about to read 3, iclass 11, count 0 2006.203.08:09:40.31#ibcon#read 3, iclass 11, count 0 2006.203.08:09:40.31#ibcon#about to read 4, iclass 11, count 0 2006.203.08:09:40.31#ibcon#read 4, iclass 11, count 0 2006.203.08:09:40.31#ibcon#about to read 5, iclass 11, count 0 2006.203.08:09:40.31#ibcon#read 5, iclass 11, count 0 2006.203.08:09:40.31#ibcon#about to read 6, iclass 11, count 0 2006.203.08:09:40.31#ibcon#read 6, iclass 11, count 0 2006.203.08:09:40.31#ibcon#end of sib2, iclass 11, count 0 2006.203.08:09:40.31#ibcon#*after write, iclass 11, count 0 2006.203.08:09:40.31#ibcon#*before return 0, iclass 11, count 0 2006.203.08:09:40.31#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.203.08:09:40.31#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.203.08:09:40.31#ibcon#about to clear, iclass 11 cls_cnt 0 2006.203.08:09:40.31#ibcon#cleared, iclass 11 cls_cnt 0 2006.203.08:09:40.32$vc4f8/va=3,8 2006.203.08:09:40.32#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.203.08:09:40.32#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.203.08:09:40.32#ibcon#ireg 11 cls_cnt 2 2006.203.08:09:40.32#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.203.08:09:40.37#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.203.08:09:40.37#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.203.08:09:40.37#ibcon#enter wrdev, iclass 13, count 2 2006.203.08:09:40.37#ibcon#first serial, iclass 13, count 2 2006.203.08:09:40.37#ibcon#enter sib2, iclass 13, count 2 2006.203.08:09:40.37#ibcon#flushed, iclass 13, count 2 2006.203.08:09:40.37#ibcon#about to write, iclass 13, count 2 2006.203.08:09:40.37#ibcon#wrote, iclass 13, count 2 2006.203.08:09:40.37#ibcon#about to read 3, iclass 13, count 2 2006.203.08:09:40.38#ibcon#read 3, iclass 13, count 2 2006.203.08:09:40.38#ibcon#about to read 4, iclass 13, count 2 2006.203.08:09:40.38#ibcon#read 4, iclass 13, count 2 2006.203.08:09:40.38#ibcon#about to read 5, iclass 13, count 2 2006.203.08:09:40.38#ibcon#read 5, iclass 13, count 2 2006.203.08:09:40.38#ibcon#about to read 6, iclass 13, count 2 2006.203.08:09:40.38#ibcon#read 6, iclass 13, count 2 2006.203.08:09:40.38#ibcon#end of sib2, iclass 13, count 2 2006.203.08:09:40.38#ibcon#*mode == 0, iclass 13, count 2 2006.203.08:09:40.38#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.203.08:09:40.38#ibcon#[25=AT03-08\r\n] 2006.203.08:09:40.38#ibcon#*before write, iclass 13, count 2 2006.203.08:09:40.38#ibcon#enter sib2, iclass 13, count 2 2006.203.08:09:40.38#ibcon#flushed, iclass 13, count 2 2006.203.08:09:40.38#ibcon#about to write, iclass 13, count 2 2006.203.08:09:40.38#ibcon#wrote, iclass 13, count 2 2006.203.08:09:40.38#ibcon#about to read 3, iclass 13, count 2 2006.203.08:09:40.41#ibcon#read 3, iclass 13, count 2 2006.203.08:09:40.41#ibcon#about to read 4, iclass 13, count 2 2006.203.08:09:40.41#ibcon#read 4, iclass 13, count 2 2006.203.08:09:40.41#ibcon#about to read 5, iclass 13, count 2 2006.203.08:09:40.41#ibcon#read 5, iclass 13, count 2 2006.203.08:09:40.41#ibcon#about to read 6, iclass 13, count 2 2006.203.08:09:40.41#ibcon#read 6, iclass 13, count 2 2006.203.08:09:40.41#ibcon#end of sib2, iclass 13, count 2 2006.203.08:09:40.41#ibcon#*after write, iclass 13, count 2 2006.203.08:09:40.41#ibcon#*before return 0, iclass 13, count 2 2006.203.08:09:40.41#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.203.08:09:40.41#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.203.08:09:40.41#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.203.08:09:40.41#ibcon#ireg 7 cls_cnt 0 2006.203.08:09:40.41#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.203.08:09:40.53#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.203.08:09:40.53#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.203.08:09:40.53#ibcon#enter wrdev, iclass 13, count 0 2006.203.08:09:40.53#ibcon#first serial, iclass 13, count 0 2006.203.08:09:40.53#ibcon#enter sib2, iclass 13, count 0 2006.203.08:09:40.53#ibcon#flushed, iclass 13, count 0 2006.203.08:09:40.53#ibcon#about to write, iclass 13, count 0 2006.203.08:09:40.53#ibcon#wrote, iclass 13, count 0 2006.203.08:09:40.53#ibcon#about to read 3, iclass 13, count 0 2006.203.08:09:40.55#ibcon#read 3, iclass 13, count 0 2006.203.08:09:40.55#ibcon#about to read 4, iclass 13, count 0 2006.203.08:09:40.55#ibcon#read 4, iclass 13, count 0 2006.203.08:09:40.55#ibcon#about to read 5, iclass 13, count 0 2006.203.08:09:40.55#ibcon#read 5, iclass 13, count 0 2006.203.08:09:40.55#ibcon#about to read 6, iclass 13, count 0 2006.203.08:09:40.55#ibcon#read 6, iclass 13, count 0 2006.203.08:09:40.55#ibcon#end of sib2, iclass 13, count 0 2006.203.08:09:40.55#ibcon#*mode == 0, iclass 13, count 0 2006.203.08:09:40.55#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.203.08:09:40.55#ibcon#[25=USB\r\n] 2006.203.08:09:40.55#ibcon#*before write, iclass 13, count 0 2006.203.08:09:40.55#ibcon#enter sib2, iclass 13, count 0 2006.203.08:09:40.55#ibcon#flushed, iclass 13, count 0 2006.203.08:09:40.55#ibcon#about to write, iclass 13, count 0 2006.203.08:09:40.55#ibcon#wrote, iclass 13, count 0 2006.203.08:09:40.55#ibcon#about to read 3, iclass 13, count 0 2006.203.08:09:40.58#ibcon#read 3, iclass 13, count 0 2006.203.08:09:40.58#ibcon#about to read 4, iclass 13, count 0 2006.203.08:09:40.58#ibcon#read 4, iclass 13, count 0 2006.203.08:09:40.58#ibcon#about to read 5, iclass 13, count 0 2006.203.08:09:40.58#ibcon#read 5, iclass 13, count 0 2006.203.08:09:40.58#ibcon#about to read 6, iclass 13, count 0 2006.203.08:09:40.58#ibcon#read 6, iclass 13, count 0 2006.203.08:09:40.58#ibcon#end of sib2, iclass 13, count 0 2006.203.08:09:40.58#ibcon#*after write, iclass 13, count 0 2006.203.08:09:40.58#ibcon#*before return 0, iclass 13, count 0 2006.203.08:09:40.58#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.203.08:09:40.58#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.203.08:09:40.58#ibcon#about to clear, iclass 13 cls_cnt 0 2006.203.08:09:40.58#ibcon#cleared, iclass 13 cls_cnt 0 2006.203.08:09:40.59$vc4f8/valo=4,832.99 2006.203.08:09:40.59#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.203.08:09:40.59#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.203.08:09:40.59#ibcon#ireg 17 cls_cnt 0 2006.203.08:09:40.59#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.203.08:09:40.59#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.203.08:09:40.59#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.203.08:09:40.59#ibcon#enter wrdev, iclass 15, count 0 2006.203.08:09:40.59#ibcon#first serial, iclass 15, count 0 2006.203.08:09:40.59#ibcon#enter sib2, iclass 15, count 0 2006.203.08:09:40.59#ibcon#flushed, iclass 15, count 0 2006.203.08:09:40.59#ibcon#about to write, iclass 15, count 0 2006.203.08:09:40.59#ibcon#wrote, iclass 15, count 0 2006.203.08:09:40.59#ibcon#about to read 3, iclass 15, count 0 2006.203.08:09:40.60#ibcon#read 3, iclass 15, count 0 2006.203.08:09:40.60#ibcon#about to read 4, iclass 15, count 0 2006.203.08:09:40.60#ibcon#read 4, iclass 15, count 0 2006.203.08:09:40.60#ibcon#about to read 5, iclass 15, count 0 2006.203.08:09:40.60#ibcon#read 5, iclass 15, count 0 2006.203.08:09:40.60#ibcon#about to read 6, iclass 15, count 0 2006.203.08:09:40.60#ibcon#read 6, iclass 15, count 0 2006.203.08:09:40.60#ibcon#end of sib2, iclass 15, count 0 2006.203.08:09:40.60#ibcon#*mode == 0, iclass 15, count 0 2006.203.08:09:40.60#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.203.08:09:40.60#ibcon#[26=FRQ=04,832.99\r\n] 2006.203.08:09:40.60#ibcon#*before write, iclass 15, count 0 2006.203.08:09:40.60#ibcon#enter sib2, iclass 15, count 0 2006.203.08:09:40.60#ibcon#flushed, iclass 15, count 0 2006.203.08:09:40.60#ibcon#about to write, iclass 15, count 0 2006.203.08:09:40.60#ibcon#wrote, iclass 15, count 0 2006.203.08:09:40.60#ibcon#about to read 3, iclass 15, count 0 2006.203.08:09:40.64#ibcon#read 3, iclass 15, count 0 2006.203.08:09:40.64#ibcon#about to read 4, iclass 15, count 0 2006.203.08:09:40.64#ibcon#read 4, iclass 15, count 0 2006.203.08:09:40.64#ibcon#about to read 5, iclass 15, count 0 2006.203.08:09:40.64#ibcon#read 5, iclass 15, count 0 2006.203.08:09:40.64#ibcon#about to read 6, iclass 15, count 0 2006.203.08:09:40.64#ibcon#read 6, iclass 15, count 0 2006.203.08:09:40.64#ibcon#end of sib2, iclass 15, count 0 2006.203.08:09:40.64#ibcon#*after write, iclass 15, count 0 2006.203.08:09:40.64#ibcon#*before return 0, iclass 15, count 0 2006.203.08:09:40.64#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.203.08:09:40.64#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.203.08:09:40.64#ibcon#about to clear, iclass 15 cls_cnt 0 2006.203.08:09:40.64#ibcon#cleared, iclass 15 cls_cnt 0 2006.203.08:09:40.65$vc4f8/va=4,7 2006.203.08:09:40.65#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.203.08:09:40.65#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.203.08:09:40.65#ibcon#ireg 11 cls_cnt 2 2006.203.08:09:40.65#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.203.08:09:40.69#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.203.08:09:40.69#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.203.08:09:40.69#ibcon#enter wrdev, iclass 17, count 2 2006.203.08:09:40.69#ibcon#first serial, iclass 17, count 2 2006.203.08:09:40.69#ibcon#enter sib2, iclass 17, count 2 2006.203.08:09:40.69#ibcon#flushed, iclass 17, count 2 2006.203.08:09:40.69#ibcon#about to write, iclass 17, count 2 2006.203.08:09:40.69#ibcon#wrote, iclass 17, count 2 2006.203.08:09:40.69#ibcon#about to read 3, iclass 17, count 2 2006.203.08:09:40.71#ibcon#read 3, iclass 17, count 2 2006.203.08:09:40.71#ibcon#about to read 4, iclass 17, count 2 2006.203.08:09:40.71#ibcon#read 4, iclass 17, count 2 2006.203.08:09:40.71#ibcon#about to read 5, iclass 17, count 2 2006.203.08:09:40.71#ibcon#read 5, iclass 17, count 2 2006.203.08:09:40.71#ibcon#about to read 6, iclass 17, count 2 2006.203.08:09:40.71#ibcon#read 6, iclass 17, count 2 2006.203.08:09:40.71#ibcon#end of sib2, iclass 17, count 2 2006.203.08:09:40.71#ibcon#*mode == 0, iclass 17, count 2 2006.203.08:09:40.71#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.203.08:09:40.71#ibcon#[25=AT04-07\r\n] 2006.203.08:09:40.71#ibcon#*before write, iclass 17, count 2 2006.203.08:09:40.71#ibcon#enter sib2, iclass 17, count 2 2006.203.08:09:40.71#ibcon#flushed, iclass 17, count 2 2006.203.08:09:40.71#ibcon#about to write, iclass 17, count 2 2006.203.08:09:40.71#ibcon#wrote, iclass 17, count 2 2006.203.08:09:40.71#ibcon#about to read 3, iclass 17, count 2 2006.203.08:09:40.74#ibcon#read 3, iclass 17, count 2 2006.203.08:09:40.74#ibcon#about to read 4, iclass 17, count 2 2006.203.08:09:40.74#ibcon#read 4, iclass 17, count 2 2006.203.08:09:40.74#ibcon#about to read 5, iclass 17, count 2 2006.203.08:09:40.74#ibcon#read 5, iclass 17, count 2 2006.203.08:09:40.74#ibcon#about to read 6, iclass 17, count 2 2006.203.08:09:40.74#ibcon#read 6, iclass 17, count 2 2006.203.08:09:40.74#ibcon#end of sib2, iclass 17, count 2 2006.203.08:09:40.74#ibcon#*after write, iclass 17, count 2 2006.203.08:09:40.74#ibcon#*before return 0, iclass 17, count 2 2006.203.08:09:40.74#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.203.08:09:40.74#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.203.08:09:40.74#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.203.08:09:40.74#ibcon#ireg 7 cls_cnt 0 2006.203.08:09:40.74#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.203.08:09:40.86#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.203.08:09:40.86#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.203.08:09:40.86#ibcon#enter wrdev, iclass 17, count 0 2006.203.08:09:40.86#ibcon#first serial, iclass 17, count 0 2006.203.08:09:40.86#ibcon#enter sib2, iclass 17, count 0 2006.203.08:09:40.86#ibcon#flushed, iclass 17, count 0 2006.203.08:09:40.86#ibcon#about to write, iclass 17, count 0 2006.203.08:09:40.86#ibcon#wrote, iclass 17, count 0 2006.203.08:09:40.86#ibcon#about to read 3, iclass 17, count 0 2006.203.08:09:40.88#ibcon#read 3, iclass 17, count 0 2006.203.08:09:40.88#ibcon#about to read 4, iclass 17, count 0 2006.203.08:09:40.88#ibcon#read 4, iclass 17, count 0 2006.203.08:09:40.88#ibcon#about to read 5, iclass 17, count 0 2006.203.08:09:40.88#ibcon#read 5, iclass 17, count 0 2006.203.08:09:40.88#ibcon#about to read 6, iclass 17, count 0 2006.203.08:09:40.88#ibcon#read 6, iclass 17, count 0 2006.203.08:09:40.88#ibcon#end of sib2, iclass 17, count 0 2006.203.08:09:40.88#ibcon#*mode == 0, iclass 17, count 0 2006.203.08:09:40.88#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.203.08:09:40.88#ibcon#[25=USB\r\n] 2006.203.08:09:40.88#ibcon#*before write, iclass 17, count 0 2006.203.08:09:40.88#ibcon#enter sib2, iclass 17, count 0 2006.203.08:09:40.88#ibcon#flushed, iclass 17, count 0 2006.203.08:09:40.88#ibcon#about to write, iclass 17, count 0 2006.203.08:09:40.88#ibcon#wrote, iclass 17, count 0 2006.203.08:09:40.88#ibcon#about to read 3, iclass 17, count 0 2006.203.08:09:40.91#ibcon#read 3, iclass 17, count 0 2006.203.08:09:40.91#ibcon#about to read 4, iclass 17, count 0 2006.203.08:09:40.91#ibcon#read 4, iclass 17, count 0 2006.203.08:09:40.91#ibcon#about to read 5, iclass 17, count 0 2006.203.08:09:40.91#ibcon#read 5, iclass 17, count 0 2006.203.08:09:40.91#ibcon#about to read 6, iclass 17, count 0 2006.203.08:09:40.91#ibcon#read 6, iclass 17, count 0 2006.203.08:09:40.91#ibcon#end of sib2, iclass 17, count 0 2006.203.08:09:40.91#ibcon#*after write, iclass 17, count 0 2006.203.08:09:40.91#ibcon#*before return 0, iclass 17, count 0 2006.203.08:09:40.91#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.203.08:09:40.91#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.203.08:09:40.91#ibcon#about to clear, iclass 17 cls_cnt 0 2006.203.08:09:40.91#ibcon#cleared, iclass 17 cls_cnt 0 2006.203.08:09:40.92$vc4f8/valo=5,652.99 2006.203.08:09:40.92#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.203.08:09:40.92#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.203.08:09:40.92#ibcon#ireg 17 cls_cnt 0 2006.203.08:09:40.92#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.203.08:09:40.92#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.203.08:09:40.92#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.203.08:09:40.92#ibcon#enter wrdev, iclass 19, count 0 2006.203.08:09:40.92#ibcon#first serial, iclass 19, count 0 2006.203.08:09:40.92#ibcon#enter sib2, iclass 19, count 0 2006.203.08:09:40.92#ibcon#flushed, iclass 19, count 0 2006.203.08:09:40.92#ibcon#about to write, iclass 19, count 0 2006.203.08:09:40.92#ibcon#wrote, iclass 19, count 0 2006.203.08:09:40.92#ibcon#about to read 3, iclass 19, count 0 2006.203.08:09:40.93#ibcon#read 3, iclass 19, count 0 2006.203.08:09:40.93#ibcon#about to read 4, iclass 19, count 0 2006.203.08:09:40.93#ibcon#read 4, iclass 19, count 0 2006.203.08:09:40.93#ibcon#about to read 5, iclass 19, count 0 2006.203.08:09:40.93#ibcon#read 5, iclass 19, count 0 2006.203.08:09:40.93#ibcon#about to read 6, iclass 19, count 0 2006.203.08:09:40.93#ibcon#read 6, iclass 19, count 0 2006.203.08:09:40.93#ibcon#end of sib2, iclass 19, count 0 2006.203.08:09:40.93#ibcon#*mode == 0, iclass 19, count 0 2006.203.08:09:40.93#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.203.08:09:40.93#ibcon#[26=FRQ=05,652.99\r\n] 2006.203.08:09:40.93#ibcon#*before write, iclass 19, count 0 2006.203.08:09:40.93#ibcon#enter sib2, iclass 19, count 0 2006.203.08:09:40.93#ibcon#flushed, iclass 19, count 0 2006.203.08:09:40.93#ibcon#about to write, iclass 19, count 0 2006.203.08:09:40.93#ibcon#wrote, iclass 19, count 0 2006.203.08:09:40.93#ibcon#about to read 3, iclass 19, count 0 2006.203.08:09:40.97#ibcon#read 3, iclass 19, count 0 2006.203.08:09:40.97#ibcon#about to read 4, iclass 19, count 0 2006.203.08:09:40.97#ibcon#read 4, iclass 19, count 0 2006.203.08:09:40.97#ibcon#about to read 5, iclass 19, count 0 2006.203.08:09:40.97#ibcon#read 5, iclass 19, count 0 2006.203.08:09:40.97#ibcon#about to read 6, iclass 19, count 0 2006.203.08:09:40.97#ibcon#read 6, iclass 19, count 0 2006.203.08:09:40.97#ibcon#end of sib2, iclass 19, count 0 2006.203.08:09:40.97#ibcon#*after write, iclass 19, count 0 2006.203.08:09:40.97#ibcon#*before return 0, iclass 19, count 0 2006.203.08:09:40.97#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.203.08:09:40.97#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.203.08:09:40.97#ibcon#about to clear, iclass 19 cls_cnt 0 2006.203.08:09:40.97#ibcon#cleared, iclass 19 cls_cnt 0 2006.203.08:09:40.98$vc4f8/va=5,7 2006.203.08:09:40.98#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.203.08:09:40.98#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.203.08:09:40.98#ibcon#ireg 11 cls_cnt 2 2006.203.08:09:40.98#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.203.08:09:41.02#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.203.08:09:41.02#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.203.08:09:41.02#ibcon#enter wrdev, iclass 21, count 2 2006.203.08:09:41.02#ibcon#first serial, iclass 21, count 2 2006.203.08:09:41.02#ibcon#enter sib2, iclass 21, count 2 2006.203.08:09:41.02#ibcon#flushed, iclass 21, count 2 2006.203.08:09:41.02#ibcon#about to write, iclass 21, count 2 2006.203.08:09:41.02#ibcon#wrote, iclass 21, count 2 2006.203.08:09:41.02#ibcon#about to read 3, iclass 21, count 2 2006.203.08:09:41.04#ibcon#read 3, iclass 21, count 2 2006.203.08:09:41.04#ibcon#about to read 4, iclass 21, count 2 2006.203.08:09:41.04#ibcon#read 4, iclass 21, count 2 2006.203.08:09:41.04#ibcon#about to read 5, iclass 21, count 2 2006.203.08:09:41.04#ibcon#read 5, iclass 21, count 2 2006.203.08:09:41.04#ibcon#about to read 6, iclass 21, count 2 2006.203.08:09:41.04#ibcon#read 6, iclass 21, count 2 2006.203.08:09:41.04#ibcon#end of sib2, iclass 21, count 2 2006.203.08:09:41.04#ibcon#*mode == 0, iclass 21, count 2 2006.203.08:09:41.04#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.203.08:09:41.04#ibcon#[25=AT05-07\r\n] 2006.203.08:09:41.04#ibcon#*before write, iclass 21, count 2 2006.203.08:09:41.04#ibcon#enter sib2, iclass 21, count 2 2006.203.08:09:41.04#ibcon#flushed, iclass 21, count 2 2006.203.08:09:41.04#ibcon#about to write, iclass 21, count 2 2006.203.08:09:41.04#ibcon#wrote, iclass 21, count 2 2006.203.08:09:41.04#ibcon#about to read 3, iclass 21, count 2 2006.203.08:09:41.07#ibcon#read 3, iclass 21, count 2 2006.203.08:09:41.07#ibcon#about to read 4, iclass 21, count 2 2006.203.08:09:41.07#ibcon#read 4, iclass 21, count 2 2006.203.08:09:41.07#ibcon#about to read 5, iclass 21, count 2 2006.203.08:09:41.07#ibcon#read 5, iclass 21, count 2 2006.203.08:09:41.07#ibcon#about to read 6, iclass 21, count 2 2006.203.08:09:41.07#ibcon#read 6, iclass 21, count 2 2006.203.08:09:41.07#ibcon#end of sib2, iclass 21, count 2 2006.203.08:09:41.07#ibcon#*after write, iclass 21, count 2 2006.203.08:09:41.07#ibcon#*before return 0, iclass 21, count 2 2006.203.08:09:41.07#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.203.08:09:41.07#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.203.08:09:41.07#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.203.08:09:41.07#ibcon#ireg 7 cls_cnt 0 2006.203.08:09:41.07#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.203.08:09:41.19#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.203.08:09:41.19#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.203.08:09:41.19#ibcon#enter wrdev, iclass 21, count 0 2006.203.08:09:41.19#ibcon#first serial, iclass 21, count 0 2006.203.08:09:41.19#ibcon#enter sib2, iclass 21, count 0 2006.203.08:09:41.19#ibcon#flushed, iclass 21, count 0 2006.203.08:09:41.19#ibcon#about to write, iclass 21, count 0 2006.203.08:09:41.19#ibcon#wrote, iclass 21, count 0 2006.203.08:09:41.19#ibcon#about to read 3, iclass 21, count 0 2006.203.08:09:41.21#ibcon#read 3, iclass 21, count 0 2006.203.08:09:41.21#ibcon#about to read 4, iclass 21, count 0 2006.203.08:09:41.21#ibcon#read 4, iclass 21, count 0 2006.203.08:09:41.21#ibcon#about to read 5, iclass 21, count 0 2006.203.08:09:41.21#ibcon#read 5, iclass 21, count 0 2006.203.08:09:41.21#ibcon#about to read 6, iclass 21, count 0 2006.203.08:09:41.21#ibcon#read 6, iclass 21, count 0 2006.203.08:09:41.21#ibcon#end of sib2, iclass 21, count 0 2006.203.08:09:41.21#ibcon#*mode == 0, iclass 21, count 0 2006.203.08:09:41.21#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.203.08:09:41.21#ibcon#[25=USB\r\n] 2006.203.08:09:41.21#ibcon#*before write, iclass 21, count 0 2006.203.08:09:41.21#ibcon#enter sib2, iclass 21, count 0 2006.203.08:09:41.21#ibcon#flushed, iclass 21, count 0 2006.203.08:09:41.21#ibcon#about to write, iclass 21, count 0 2006.203.08:09:41.21#ibcon#wrote, iclass 21, count 0 2006.203.08:09:41.21#ibcon#about to read 3, iclass 21, count 0 2006.203.08:09:41.24#ibcon#read 3, iclass 21, count 0 2006.203.08:09:41.24#ibcon#about to read 4, iclass 21, count 0 2006.203.08:09:41.24#ibcon#read 4, iclass 21, count 0 2006.203.08:09:41.24#ibcon#about to read 5, iclass 21, count 0 2006.203.08:09:41.24#ibcon#read 5, iclass 21, count 0 2006.203.08:09:41.24#ibcon#about to read 6, iclass 21, count 0 2006.203.08:09:41.24#ibcon#read 6, iclass 21, count 0 2006.203.08:09:41.24#ibcon#end of sib2, iclass 21, count 0 2006.203.08:09:41.24#ibcon#*after write, iclass 21, count 0 2006.203.08:09:41.24#ibcon#*before return 0, iclass 21, count 0 2006.203.08:09:41.24#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.203.08:09:41.24#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.203.08:09:41.24#ibcon#about to clear, iclass 21 cls_cnt 0 2006.203.08:09:41.24#ibcon#cleared, iclass 21 cls_cnt 0 2006.203.08:09:41.24$vc4f8/valo=6,772.99 2006.203.08:09:41.25#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.203.08:09:41.25#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.203.08:09:41.25#ibcon#ireg 17 cls_cnt 0 2006.203.08:09:41.25#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.203.08:09:41.25#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.203.08:09:41.25#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.203.08:09:41.25#ibcon#enter wrdev, iclass 23, count 0 2006.203.08:09:41.25#ibcon#first serial, iclass 23, count 0 2006.203.08:09:41.25#ibcon#enter sib2, iclass 23, count 0 2006.203.08:09:41.25#ibcon#flushed, iclass 23, count 0 2006.203.08:09:41.25#ibcon#about to write, iclass 23, count 0 2006.203.08:09:41.25#ibcon#wrote, iclass 23, count 0 2006.203.08:09:41.25#ibcon#about to read 3, iclass 23, count 0 2006.203.08:09:41.26#ibcon#read 3, iclass 23, count 0 2006.203.08:09:41.26#ibcon#about to read 4, iclass 23, count 0 2006.203.08:09:41.26#ibcon#read 4, iclass 23, count 0 2006.203.08:09:41.26#ibcon#about to read 5, iclass 23, count 0 2006.203.08:09:41.26#ibcon#read 5, iclass 23, count 0 2006.203.08:09:41.26#ibcon#about to read 6, iclass 23, count 0 2006.203.08:09:41.26#ibcon#read 6, iclass 23, count 0 2006.203.08:09:41.26#ibcon#end of sib2, iclass 23, count 0 2006.203.08:09:41.26#ibcon#*mode == 0, iclass 23, count 0 2006.203.08:09:41.26#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.203.08:09:41.26#ibcon#[26=FRQ=06,772.99\r\n] 2006.203.08:09:41.26#ibcon#*before write, iclass 23, count 0 2006.203.08:09:41.26#ibcon#enter sib2, iclass 23, count 0 2006.203.08:09:41.26#ibcon#flushed, iclass 23, count 0 2006.203.08:09:41.26#ibcon#about to write, iclass 23, count 0 2006.203.08:09:41.26#ibcon#wrote, iclass 23, count 0 2006.203.08:09:41.26#ibcon#about to read 3, iclass 23, count 0 2006.203.08:09:41.30#ibcon#read 3, iclass 23, count 0 2006.203.08:09:41.30#ibcon#about to read 4, iclass 23, count 0 2006.203.08:09:41.30#ibcon#read 4, iclass 23, count 0 2006.203.08:09:41.30#ibcon#about to read 5, iclass 23, count 0 2006.203.08:09:41.30#ibcon#read 5, iclass 23, count 0 2006.203.08:09:41.30#ibcon#about to read 6, iclass 23, count 0 2006.203.08:09:41.30#ibcon#read 6, iclass 23, count 0 2006.203.08:09:41.30#ibcon#end of sib2, iclass 23, count 0 2006.203.08:09:41.30#ibcon#*after write, iclass 23, count 0 2006.203.08:09:41.30#ibcon#*before return 0, iclass 23, count 0 2006.203.08:09:41.30#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.203.08:09:41.30#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.203.08:09:41.30#ibcon#about to clear, iclass 23 cls_cnt 0 2006.203.08:09:41.30#ibcon#cleared, iclass 23 cls_cnt 0 2006.203.08:09:41.31$vc4f8/va=6,6 2006.203.08:09:41.31#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.203.08:09:41.31#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.203.08:09:41.31#ibcon#ireg 11 cls_cnt 2 2006.203.08:09:41.31#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.203.08:09:41.35#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.203.08:09:41.35#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.203.08:09:41.35#ibcon#enter wrdev, iclass 25, count 2 2006.203.08:09:41.35#ibcon#first serial, iclass 25, count 2 2006.203.08:09:41.35#ibcon#enter sib2, iclass 25, count 2 2006.203.08:09:41.35#ibcon#flushed, iclass 25, count 2 2006.203.08:09:41.35#ibcon#about to write, iclass 25, count 2 2006.203.08:09:41.35#ibcon#wrote, iclass 25, count 2 2006.203.08:09:41.35#ibcon#about to read 3, iclass 25, count 2 2006.203.08:09:41.37#ibcon#read 3, iclass 25, count 2 2006.203.08:09:41.37#ibcon#about to read 4, iclass 25, count 2 2006.203.08:09:41.37#ibcon#read 4, iclass 25, count 2 2006.203.08:09:41.37#ibcon#about to read 5, iclass 25, count 2 2006.203.08:09:41.37#ibcon#read 5, iclass 25, count 2 2006.203.08:09:41.37#ibcon#about to read 6, iclass 25, count 2 2006.203.08:09:41.37#ibcon#read 6, iclass 25, count 2 2006.203.08:09:41.37#ibcon#end of sib2, iclass 25, count 2 2006.203.08:09:41.37#ibcon#*mode == 0, iclass 25, count 2 2006.203.08:09:41.37#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.203.08:09:41.37#ibcon#[25=AT06-06\r\n] 2006.203.08:09:41.37#ibcon#*before write, iclass 25, count 2 2006.203.08:09:41.37#ibcon#enter sib2, iclass 25, count 2 2006.203.08:09:41.37#ibcon#flushed, iclass 25, count 2 2006.203.08:09:41.37#ibcon#about to write, iclass 25, count 2 2006.203.08:09:41.37#ibcon#wrote, iclass 25, count 2 2006.203.08:09:41.37#ibcon#about to read 3, iclass 25, count 2 2006.203.08:09:41.40#ibcon#read 3, iclass 25, count 2 2006.203.08:09:41.40#ibcon#about to read 4, iclass 25, count 2 2006.203.08:09:41.40#ibcon#read 4, iclass 25, count 2 2006.203.08:09:41.40#ibcon#about to read 5, iclass 25, count 2 2006.203.08:09:41.40#ibcon#read 5, iclass 25, count 2 2006.203.08:09:41.40#ibcon#about to read 6, iclass 25, count 2 2006.203.08:09:41.40#ibcon#read 6, iclass 25, count 2 2006.203.08:09:41.40#ibcon#end of sib2, iclass 25, count 2 2006.203.08:09:41.40#ibcon#*after write, iclass 25, count 2 2006.203.08:09:41.40#ibcon#*before return 0, iclass 25, count 2 2006.203.08:09:41.40#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.203.08:09:41.40#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.203.08:09:41.40#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.203.08:09:41.40#ibcon#ireg 7 cls_cnt 0 2006.203.08:09:41.40#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.203.08:09:41.52#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.203.08:09:41.52#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.203.08:09:41.52#ibcon#enter wrdev, iclass 25, count 0 2006.203.08:09:41.52#ibcon#first serial, iclass 25, count 0 2006.203.08:09:41.52#ibcon#enter sib2, iclass 25, count 0 2006.203.08:09:41.52#ibcon#flushed, iclass 25, count 0 2006.203.08:09:41.52#ibcon#about to write, iclass 25, count 0 2006.203.08:09:41.52#ibcon#wrote, iclass 25, count 0 2006.203.08:09:41.52#ibcon#about to read 3, iclass 25, count 0 2006.203.08:09:41.54#ibcon#read 3, iclass 25, count 0 2006.203.08:09:41.54#ibcon#about to read 4, iclass 25, count 0 2006.203.08:09:41.54#ibcon#read 4, iclass 25, count 0 2006.203.08:09:41.54#ibcon#about to read 5, iclass 25, count 0 2006.203.08:09:41.54#ibcon#read 5, iclass 25, count 0 2006.203.08:09:41.54#ibcon#about to read 6, iclass 25, count 0 2006.203.08:09:41.54#ibcon#read 6, iclass 25, count 0 2006.203.08:09:41.54#ibcon#end of sib2, iclass 25, count 0 2006.203.08:09:41.54#ibcon#*mode == 0, iclass 25, count 0 2006.203.08:09:41.54#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.203.08:09:41.54#ibcon#[25=USB\r\n] 2006.203.08:09:41.54#ibcon#*before write, iclass 25, count 0 2006.203.08:09:41.54#ibcon#enter sib2, iclass 25, count 0 2006.203.08:09:41.54#ibcon#flushed, iclass 25, count 0 2006.203.08:09:41.54#ibcon#about to write, iclass 25, count 0 2006.203.08:09:41.54#ibcon#wrote, iclass 25, count 0 2006.203.08:09:41.54#ibcon#about to read 3, iclass 25, count 0 2006.203.08:09:41.57#ibcon#read 3, iclass 25, count 0 2006.203.08:09:41.57#ibcon#about to read 4, iclass 25, count 0 2006.203.08:09:41.57#ibcon#read 4, iclass 25, count 0 2006.203.08:09:41.57#ibcon#about to read 5, iclass 25, count 0 2006.203.08:09:41.57#ibcon#read 5, iclass 25, count 0 2006.203.08:09:41.57#ibcon#about to read 6, iclass 25, count 0 2006.203.08:09:41.57#ibcon#read 6, iclass 25, count 0 2006.203.08:09:41.57#ibcon#end of sib2, iclass 25, count 0 2006.203.08:09:41.57#ibcon#*after write, iclass 25, count 0 2006.203.08:09:41.57#ibcon#*before return 0, iclass 25, count 0 2006.203.08:09:41.57#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.203.08:09:41.57#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.203.08:09:41.57#ibcon#about to clear, iclass 25 cls_cnt 0 2006.203.08:09:41.57#ibcon#cleared, iclass 25 cls_cnt 0 2006.203.08:09:41.58$vc4f8/valo=7,832.99 2006.203.08:09:41.58#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.203.08:09:41.58#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.203.08:09:41.58#ibcon#ireg 17 cls_cnt 0 2006.203.08:09:41.58#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.203.08:09:41.58#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.203.08:09:41.58#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.203.08:09:41.58#ibcon#enter wrdev, iclass 27, count 0 2006.203.08:09:41.58#ibcon#first serial, iclass 27, count 0 2006.203.08:09:41.58#ibcon#enter sib2, iclass 27, count 0 2006.203.08:09:41.58#ibcon#flushed, iclass 27, count 0 2006.203.08:09:41.58#ibcon#about to write, iclass 27, count 0 2006.203.08:09:41.58#ibcon#wrote, iclass 27, count 0 2006.203.08:09:41.58#ibcon#about to read 3, iclass 27, count 0 2006.203.08:09:41.59#ibcon#read 3, iclass 27, count 0 2006.203.08:09:41.59#ibcon#about to read 4, iclass 27, count 0 2006.203.08:09:41.59#ibcon#read 4, iclass 27, count 0 2006.203.08:09:41.59#ibcon#about to read 5, iclass 27, count 0 2006.203.08:09:41.59#ibcon#read 5, iclass 27, count 0 2006.203.08:09:41.59#ibcon#about to read 6, iclass 27, count 0 2006.203.08:09:41.59#ibcon#read 6, iclass 27, count 0 2006.203.08:09:41.59#ibcon#end of sib2, iclass 27, count 0 2006.203.08:09:41.59#ibcon#*mode == 0, iclass 27, count 0 2006.203.08:09:41.59#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.203.08:09:41.59#ibcon#[26=FRQ=07,832.99\r\n] 2006.203.08:09:41.59#ibcon#*before write, iclass 27, count 0 2006.203.08:09:41.59#ibcon#enter sib2, iclass 27, count 0 2006.203.08:09:41.59#ibcon#flushed, iclass 27, count 0 2006.203.08:09:41.59#ibcon#about to write, iclass 27, count 0 2006.203.08:09:41.59#ibcon#wrote, iclass 27, count 0 2006.203.08:09:41.59#ibcon#about to read 3, iclass 27, count 0 2006.203.08:09:41.63#ibcon#read 3, iclass 27, count 0 2006.203.08:09:41.63#ibcon#about to read 4, iclass 27, count 0 2006.203.08:09:41.63#ibcon#read 4, iclass 27, count 0 2006.203.08:09:41.63#ibcon#about to read 5, iclass 27, count 0 2006.203.08:09:41.63#ibcon#read 5, iclass 27, count 0 2006.203.08:09:41.63#ibcon#about to read 6, iclass 27, count 0 2006.203.08:09:41.63#ibcon#read 6, iclass 27, count 0 2006.203.08:09:41.63#ibcon#end of sib2, iclass 27, count 0 2006.203.08:09:41.63#ibcon#*after write, iclass 27, count 0 2006.203.08:09:41.63#ibcon#*before return 0, iclass 27, count 0 2006.203.08:09:41.63#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.203.08:09:41.63#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.203.08:09:41.63#ibcon#about to clear, iclass 27 cls_cnt 0 2006.203.08:09:41.63#ibcon#cleared, iclass 27 cls_cnt 0 2006.203.08:09:41.63$vc4f8/va=7,7 2006.203.08:09:41.64#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.203.08:09:41.64#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.203.08:09:41.64#ibcon#ireg 11 cls_cnt 2 2006.203.08:09:41.64#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.203.08:09:41.68#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.203.08:09:41.68#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.203.08:09:41.68#ibcon#enter wrdev, iclass 29, count 2 2006.203.08:09:41.68#ibcon#first serial, iclass 29, count 2 2006.203.08:09:41.68#ibcon#enter sib2, iclass 29, count 2 2006.203.08:09:41.68#ibcon#flushed, iclass 29, count 2 2006.203.08:09:41.68#ibcon#about to write, iclass 29, count 2 2006.203.08:09:41.68#ibcon#wrote, iclass 29, count 2 2006.203.08:09:41.68#ibcon#about to read 3, iclass 29, count 2 2006.203.08:09:41.70#ibcon#read 3, iclass 29, count 2 2006.203.08:09:41.70#ibcon#about to read 4, iclass 29, count 2 2006.203.08:09:41.70#ibcon#read 4, iclass 29, count 2 2006.203.08:09:41.70#ibcon#about to read 5, iclass 29, count 2 2006.203.08:09:41.70#ibcon#read 5, iclass 29, count 2 2006.203.08:09:41.70#ibcon#about to read 6, iclass 29, count 2 2006.203.08:09:41.70#ibcon#read 6, iclass 29, count 2 2006.203.08:09:41.70#ibcon#end of sib2, iclass 29, count 2 2006.203.08:09:41.70#ibcon#*mode == 0, iclass 29, count 2 2006.203.08:09:41.70#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.203.08:09:41.70#ibcon#[25=AT07-07\r\n] 2006.203.08:09:41.70#ibcon#*before write, iclass 29, count 2 2006.203.08:09:41.70#ibcon#enter sib2, iclass 29, count 2 2006.203.08:09:41.70#ibcon#flushed, iclass 29, count 2 2006.203.08:09:41.70#ibcon#about to write, iclass 29, count 2 2006.203.08:09:41.70#ibcon#wrote, iclass 29, count 2 2006.203.08:09:41.70#ibcon#about to read 3, iclass 29, count 2 2006.203.08:09:41.73#ibcon#read 3, iclass 29, count 2 2006.203.08:09:41.73#ibcon#about to read 4, iclass 29, count 2 2006.203.08:09:41.73#ibcon#read 4, iclass 29, count 2 2006.203.08:09:41.73#ibcon#about to read 5, iclass 29, count 2 2006.203.08:09:41.73#ibcon#read 5, iclass 29, count 2 2006.203.08:09:41.73#ibcon#about to read 6, iclass 29, count 2 2006.203.08:09:41.73#ibcon#read 6, iclass 29, count 2 2006.203.08:09:41.73#ibcon#end of sib2, iclass 29, count 2 2006.203.08:09:41.73#ibcon#*after write, iclass 29, count 2 2006.203.08:09:41.73#ibcon#*before return 0, iclass 29, count 2 2006.203.08:09:41.73#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.203.08:09:41.73#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.203.08:09:41.73#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.203.08:09:41.73#ibcon#ireg 7 cls_cnt 0 2006.203.08:09:41.73#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.203.08:09:41.85#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.203.08:09:41.85#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.203.08:09:41.85#ibcon#enter wrdev, iclass 29, count 0 2006.203.08:09:41.85#ibcon#first serial, iclass 29, count 0 2006.203.08:09:41.85#ibcon#enter sib2, iclass 29, count 0 2006.203.08:09:41.85#ibcon#flushed, iclass 29, count 0 2006.203.08:09:41.85#ibcon#about to write, iclass 29, count 0 2006.203.08:09:41.85#ibcon#wrote, iclass 29, count 0 2006.203.08:09:41.85#ibcon#about to read 3, iclass 29, count 0 2006.203.08:09:41.87#ibcon#read 3, iclass 29, count 0 2006.203.08:09:41.87#ibcon#about to read 4, iclass 29, count 0 2006.203.08:09:41.87#ibcon#read 4, iclass 29, count 0 2006.203.08:09:41.87#ibcon#about to read 5, iclass 29, count 0 2006.203.08:09:41.87#ibcon#read 5, iclass 29, count 0 2006.203.08:09:41.87#ibcon#about to read 6, iclass 29, count 0 2006.203.08:09:41.87#ibcon#read 6, iclass 29, count 0 2006.203.08:09:41.87#ibcon#end of sib2, iclass 29, count 0 2006.203.08:09:41.87#ibcon#*mode == 0, iclass 29, count 0 2006.203.08:09:41.87#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.203.08:09:41.87#ibcon#[25=USB\r\n] 2006.203.08:09:41.87#ibcon#*before write, iclass 29, count 0 2006.203.08:09:41.87#ibcon#enter sib2, iclass 29, count 0 2006.203.08:09:41.87#ibcon#flushed, iclass 29, count 0 2006.203.08:09:41.87#ibcon#about to write, iclass 29, count 0 2006.203.08:09:41.87#ibcon#wrote, iclass 29, count 0 2006.203.08:09:41.87#ibcon#about to read 3, iclass 29, count 0 2006.203.08:09:41.90#ibcon#read 3, iclass 29, count 0 2006.203.08:09:41.90#ibcon#about to read 4, iclass 29, count 0 2006.203.08:09:41.90#ibcon#read 4, iclass 29, count 0 2006.203.08:09:41.90#ibcon#about to read 5, iclass 29, count 0 2006.203.08:09:41.90#ibcon#read 5, iclass 29, count 0 2006.203.08:09:41.90#ibcon#about to read 6, iclass 29, count 0 2006.203.08:09:41.90#ibcon#read 6, iclass 29, count 0 2006.203.08:09:41.90#ibcon#end of sib2, iclass 29, count 0 2006.203.08:09:41.90#ibcon#*after write, iclass 29, count 0 2006.203.08:09:41.90#ibcon#*before return 0, iclass 29, count 0 2006.203.08:09:41.90#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.203.08:09:41.90#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.203.08:09:41.90#ibcon#about to clear, iclass 29 cls_cnt 0 2006.203.08:09:41.90#ibcon#cleared, iclass 29 cls_cnt 0 2006.203.08:09:41.91$vc4f8/valo=8,852.99 2006.203.08:09:41.91#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.203.08:09:41.91#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.203.08:09:41.91#ibcon#ireg 17 cls_cnt 0 2006.203.08:09:41.91#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.203.08:09:41.91#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.203.08:09:41.91#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.203.08:09:41.91#ibcon#enter wrdev, iclass 31, count 0 2006.203.08:09:41.91#ibcon#first serial, iclass 31, count 0 2006.203.08:09:41.91#ibcon#enter sib2, iclass 31, count 0 2006.203.08:09:41.91#ibcon#flushed, iclass 31, count 0 2006.203.08:09:41.91#ibcon#about to write, iclass 31, count 0 2006.203.08:09:41.91#ibcon#wrote, iclass 31, count 0 2006.203.08:09:41.91#ibcon#about to read 3, iclass 31, count 0 2006.203.08:09:41.93#ibcon#read 3, iclass 31, count 0 2006.203.08:09:41.93#ibcon#about to read 4, iclass 31, count 0 2006.203.08:09:41.93#ibcon#read 4, iclass 31, count 0 2006.203.08:09:41.93#ibcon#about to read 5, iclass 31, count 0 2006.203.08:09:41.93#ibcon#read 5, iclass 31, count 0 2006.203.08:09:41.93#ibcon#about to read 6, iclass 31, count 0 2006.203.08:09:41.93#ibcon#read 6, iclass 31, count 0 2006.203.08:09:41.93#ibcon#end of sib2, iclass 31, count 0 2006.203.08:09:41.93#ibcon#*mode == 0, iclass 31, count 0 2006.203.08:09:41.93#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.203.08:09:41.93#ibcon#[26=FRQ=08,852.99\r\n] 2006.203.08:09:41.93#ibcon#*before write, iclass 31, count 0 2006.203.08:09:41.93#ibcon#enter sib2, iclass 31, count 0 2006.203.08:09:41.93#ibcon#flushed, iclass 31, count 0 2006.203.08:09:41.93#ibcon#about to write, iclass 31, count 0 2006.203.08:09:41.93#ibcon#wrote, iclass 31, count 0 2006.203.08:09:41.93#ibcon#about to read 3, iclass 31, count 0 2006.203.08:09:41.97#ibcon#read 3, iclass 31, count 0 2006.203.08:09:41.97#ibcon#about to read 4, iclass 31, count 0 2006.203.08:09:41.97#ibcon#read 4, iclass 31, count 0 2006.203.08:09:41.97#ibcon#about to read 5, iclass 31, count 0 2006.203.08:09:41.97#ibcon#read 5, iclass 31, count 0 2006.203.08:09:41.97#ibcon#about to read 6, iclass 31, count 0 2006.203.08:09:41.97#ibcon#read 6, iclass 31, count 0 2006.203.08:09:41.97#ibcon#end of sib2, iclass 31, count 0 2006.203.08:09:41.97#ibcon#*after write, iclass 31, count 0 2006.203.08:09:41.97#ibcon#*before return 0, iclass 31, count 0 2006.203.08:09:41.97#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.203.08:09:41.97#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.203.08:09:41.97#ibcon#about to clear, iclass 31 cls_cnt 0 2006.203.08:09:41.97#ibcon#cleared, iclass 31 cls_cnt 0 2006.203.08:09:41.98$vc4f8/va=8,6 2006.203.08:09:41.98#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.203.08:09:41.98#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.203.08:09:41.98#ibcon#ireg 11 cls_cnt 2 2006.203.08:09:41.98#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.203.08:09:42.02#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.203.08:09:42.02#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.203.08:09:42.02#ibcon#enter wrdev, iclass 33, count 2 2006.203.08:09:42.02#ibcon#first serial, iclass 33, count 2 2006.203.08:09:42.02#ibcon#enter sib2, iclass 33, count 2 2006.203.08:09:42.02#ibcon#flushed, iclass 33, count 2 2006.203.08:09:42.02#ibcon#about to write, iclass 33, count 2 2006.203.08:09:42.02#ibcon#wrote, iclass 33, count 2 2006.203.08:09:42.02#ibcon#about to read 3, iclass 33, count 2 2006.203.08:09:42.03#ibcon#read 3, iclass 33, count 2 2006.203.08:09:42.03#ibcon#about to read 4, iclass 33, count 2 2006.203.08:09:42.03#ibcon#read 4, iclass 33, count 2 2006.203.08:09:42.03#ibcon#about to read 5, iclass 33, count 2 2006.203.08:09:42.03#ibcon#read 5, iclass 33, count 2 2006.203.08:09:42.03#ibcon#about to read 6, iclass 33, count 2 2006.203.08:09:42.03#ibcon#read 6, iclass 33, count 2 2006.203.08:09:42.03#ibcon#end of sib2, iclass 33, count 2 2006.203.08:09:42.03#ibcon#*mode == 0, iclass 33, count 2 2006.203.08:09:42.03#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.203.08:09:42.03#ibcon#[25=AT08-06\r\n] 2006.203.08:09:42.03#ibcon#*before write, iclass 33, count 2 2006.203.08:09:42.03#ibcon#enter sib2, iclass 33, count 2 2006.203.08:09:42.03#ibcon#flushed, iclass 33, count 2 2006.203.08:09:42.03#ibcon#about to write, iclass 33, count 2 2006.203.08:09:42.03#ibcon#wrote, iclass 33, count 2 2006.203.08:09:42.03#ibcon#about to read 3, iclass 33, count 2 2006.203.08:09:42.06#ibcon#read 3, iclass 33, count 2 2006.203.08:09:42.06#ibcon#about to read 4, iclass 33, count 2 2006.203.08:09:42.06#ibcon#read 4, iclass 33, count 2 2006.203.08:09:42.06#ibcon#about to read 5, iclass 33, count 2 2006.203.08:09:42.06#ibcon#read 5, iclass 33, count 2 2006.203.08:09:42.06#ibcon#about to read 6, iclass 33, count 2 2006.203.08:09:42.06#ibcon#read 6, iclass 33, count 2 2006.203.08:09:42.06#ibcon#end of sib2, iclass 33, count 2 2006.203.08:09:42.06#ibcon#*after write, iclass 33, count 2 2006.203.08:09:42.06#ibcon#*before return 0, iclass 33, count 2 2006.203.08:09:42.06#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.203.08:09:42.06#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.203.08:09:42.06#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.203.08:09:42.06#ibcon#ireg 7 cls_cnt 0 2006.203.08:09:42.06#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.203.08:09:42.18#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.203.08:09:42.18#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.203.08:09:42.18#ibcon#enter wrdev, iclass 33, count 0 2006.203.08:09:42.18#ibcon#first serial, iclass 33, count 0 2006.203.08:09:42.18#ibcon#enter sib2, iclass 33, count 0 2006.203.08:09:42.18#ibcon#flushed, iclass 33, count 0 2006.203.08:09:42.18#ibcon#about to write, iclass 33, count 0 2006.203.08:09:42.18#ibcon#wrote, iclass 33, count 0 2006.203.08:09:42.18#ibcon#about to read 3, iclass 33, count 0 2006.203.08:09:42.20#ibcon#read 3, iclass 33, count 0 2006.203.08:09:42.20#ibcon#about to read 4, iclass 33, count 0 2006.203.08:09:42.20#ibcon#read 4, iclass 33, count 0 2006.203.08:09:42.20#ibcon#about to read 5, iclass 33, count 0 2006.203.08:09:42.20#ibcon#read 5, iclass 33, count 0 2006.203.08:09:42.20#ibcon#about to read 6, iclass 33, count 0 2006.203.08:09:42.20#ibcon#read 6, iclass 33, count 0 2006.203.08:09:42.20#ibcon#end of sib2, iclass 33, count 0 2006.203.08:09:42.20#ibcon#*mode == 0, iclass 33, count 0 2006.203.08:09:42.20#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.203.08:09:42.20#ibcon#[25=USB\r\n] 2006.203.08:09:42.20#ibcon#*before write, iclass 33, count 0 2006.203.08:09:42.20#ibcon#enter sib2, iclass 33, count 0 2006.203.08:09:42.20#ibcon#flushed, iclass 33, count 0 2006.203.08:09:42.20#ibcon#about to write, iclass 33, count 0 2006.203.08:09:42.20#ibcon#wrote, iclass 33, count 0 2006.203.08:09:42.20#ibcon#about to read 3, iclass 33, count 0 2006.203.08:09:42.23#ibcon#read 3, iclass 33, count 0 2006.203.08:09:42.23#ibcon#about to read 4, iclass 33, count 0 2006.203.08:09:42.23#ibcon#read 4, iclass 33, count 0 2006.203.08:09:42.23#ibcon#about to read 5, iclass 33, count 0 2006.203.08:09:42.23#ibcon#read 5, iclass 33, count 0 2006.203.08:09:42.23#ibcon#about to read 6, iclass 33, count 0 2006.203.08:09:42.23#ibcon#read 6, iclass 33, count 0 2006.203.08:09:42.23#ibcon#end of sib2, iclass 33, count 0 2006.203.08:09:42.23#ibcon#*after write, iclass 33, count 0 2006.203.08:09:42.23#ibcon#*before return 0, iclass 33, count 0 2006.203.08:09:42.23#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.203.08:09:42.23#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.203.08:09:42.23#ibcon#about to clear, iclass 33 cls_cnt 0 2006.203.08:09:42.23#ibcon#cleared, iclass 33 cls_cnt 0 2006.203.08:09:42.24$vc4f8/vblo=1,632.99 2006.203.08:09:42.24#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.203.08:09:42.24#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.203.08:09:42.24#ibcon#ireg 17 cls_cnt 0 2006.203.08:09:42.24#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.203.08:09:42.24#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.203.08:09:42.24#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.203.08:09:42.24#ibcon#enter wrdev, iclass 35, count 0 2006.203.08:09:42.24#ibcon#first serial, iclass 35, count 0 2006.203.08:09:42.24#ibcon#enter sib2, iclass 35, count 0 2006.203.08:09:42.24#ibcon#flushed, iclass 35, count 0 2006.203.08:09:42.24#ibcon#about to write, iclass 35, count 0 2006.203.08:09:42.24#ibcon#wrote, iclass 35, count 0 2006.203.08:09:42.24#ibcon#about to read 3, iclass 35, count 0 2006.203.08:09:42.25#ibcon#read 3, iclass 35, count 0 2006.203.08:09:42.25#ibcon#about to read 4, iclass 35, count 0 2006.203.08:09:42.25#ibcon#read 4, iclass 35, count 0 2006.203.08:09:42.25#ibcon#about to read 5, iclass 35, count 0 2006.203.08:09:42.25#ibcon#read 5, iclass 35, count 0 2006.203.08:09:42.25#ibcon#about to read 6, iclass 35, count 0 2006.203.08:09:42.25#ibcon#read 6, iclass 35, count 0 2006.203.08:09:42.25#ibcon#end of sib2, iclass 35, count 0 2006.203.08:09:42.25#ibcon#*mode == 0, iclass 35, count 0 2006.203.08:09:42.25#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.203.08:09:42.25#ibcon#[28=FRQ=01,632.99\r\n] 2006.203.08:09:42.25#ibcon#*before write, iclass 35, count 0 2006.203.08:09:42.25#ibcon#enter sib2, iclass 35, count 0 2006.203.08:09:42.25#ibcon#flushed, iclass 35, count 0 2006.203.08:09:42.25#ibcon#about to write, iclass 35, count 0 2006.203.08:09:42.25#ibcon#wrote, iclass 35, count 0 2006.203.08:09:42.25#ibcon#about to read 3, iclass 35, count 0 2006.203.08:09:42.29#ibcon#read 3, iclass 35, count 0 2006.203.08:09:42.29#ibcon#about to read 4, iclass 35, count 0 2006.203.08:09:42.29#ibcon#read 4, iclass 35, count 0 2006.203.08:09:42.29#ibcon#about to read 5, iclass 35, count 0 2006.203.08:09:42.29#ibcon#read 5, iclass 35, count 0 2006.203.08:09:42.29#ibcon#about to read 6, iclass 35, count 0 2006.203.08:09:42.29#ibcon#read 6, iclass 35, count 0 2006.203.08:09:42.29#ibcon#end of sib2, iclass 35, count 0 2006.203.08:09:42.29#ibcon#*after write, iclass 35, count 0 2006.203.08:09:42.29#ibcon#*before return 0, iclass 35, count 0 2006.203.08:09:42.29#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.203.08:09:42.29#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.203.08:09:42.29#ibcon#about to clear, iclass 35 cls_cnt 0 2006.203.08:09:42.29#ibcon#cleared, iclass 35 cls_cnt 0 2006.203.08:09:42.30$vc4f8/vb=1,4 2006.203.08:09:42.30#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.203.08:09:42.30#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.203.08:09:42.30#ibcon#ireg 11 cls_cnt 2 2006.203.08:09:42.30#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.203.08:09:42.30#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.203.08:09:42.30#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.203.08:09:42.30#ibcon#enter wrdev, iclass 37, count 2 2006.203.08:09:42.30#ibcon#first serial, iclass 37, count 2 2006.203.08:09:42.30#ibcon#enter sib2, iclass 37, count 2 2006.203.08:09:42.30#ibcon#flushed, iclass 37, count 2 2006.203.08:09:42.30#ibcon#about to write, iclass 37, count 2 2006.203.08:09:42.30#ibcon#wrote, iclass 37, count 2 2006.203.08:09:42.30#ibcon#about to read 3, iclass 37, count 2 2006.203.08:09:42.31#ibcon#read 3, iclass 37, count 2 2006.203.08:09:42.31#ibcon#about to read 4, iclass 37, count 2 2006.203.08:09:42.31#ibcon#read 4, iclass 37, count 2 2006.203.08:09:42.31#ibcon#about to read 5, iclass 37, count 2 2006.203.08:09:42.31#ibcon#read 5, iclass 37, count 2 2006.203.08:09:42.31#ibcon#about to read 6, iclass 37, count 2 2006.203.08:09:42.31#ibcon#read 6, iclass 37, count 2 2006.203.08:09:42.31#ibcon#end of sib2, iclass 37, count 2 2006.203.08:09:42.31#ibcon#*mode == 0, iclass 37, count 2 2006.203.08:09:42.31#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.203.08:09:42.31#ibcon#[27=AT01-04\r\n] 2006.203.08:09:42.31#ibcon#*before write, iclass 37, count 2 2006.203.08:09:42.31#ibcon#enter sib2, iclass 37, count 2 2006.203.08:09:42.31#ibcon#flushed, iclass 37, count 2 2006.203.08:09:42.31#ibcon#about to write, iclass 37, count 2 2006.203.08:09:42.31#ibcon#wrote, iclass 37, count 2 2006.203.08:09:42.31#ibcon#about to read 3, iclass 37, count 2 2006.203.08:09:42.34#ibcon#read 3, iclass 37, count 2 2006.203.08:09:42.34#ibcon#about to read 4, iclass 37, count 2 2006.203.08:09:42.34#ibcon#read 4, iclass 37, count 2 2006.203.08:09:42.34#ibcon#about to read 5, iclass 37, count 2 2006.203.08:09:42.34#ibcon#read 5, iclass 37, count 2 2006.203.08:09:42.34#ibcon#about to read 6, iclass 37, count 2 2006.203.08:09:42.34#ibcon#read 6, iclass 37, count 2 2006.203.08:09:42.34#ibcon#end of sib2, iclass 37, count 2 2006.203.08:09:42.34#ibcon#*after write, iclass 37, count 2 2006.203.08:09:42.34#ibcon#*before return 0, iclass 37, count 2 2006.203.08:09:42.34#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.203.08:09:42.34#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.203.08:09:42.34#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.203.08:09:42.34#ibcon#ireg 7 cls_cnt 0 2006.203.08:09:42.34#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.203.08:09:42.44#abcon#<5=/06 1.9 3.1 23.651001001.0\r\n> 2006.203.08:09:42.46#abcon#{5=INTERFACE CLEAR} 2006.203.08:09:42.46#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.203.08:09:42.46#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.203.08:09:42.46#ibcon#enter wrdev, iclass 37, count 0 2006.203.08:09:42.46#ibcon#first serial, iclass 37, count 0 2006.203.08:09:42.47#ibcon#enter sib2, iclass 37, count 0 2006.203.08:09:42.47#ibcon#flushed, iclass 37, count 0 2006.203.08:09:42.47#ibcon#about to write, iclass 37, count 0 2006.203.08:09:42.47#ibcon#wrote, iclass 37, count 0 2006.203.08:09:42.47#ibcon#about to read 3, iclass 37, count 0 2006.203.08:09:42.48#ibcon#read 3, iclass 37, count 0 2006.203.08:09:42.48#ibcon#about to read 4, iclass 37, count 0 2006.203.08:09:42.48#ibcon#read 4, iclass 37, count 0 2006.203.08:09:42.48#ibcon#about to read 5, iclass 37, count 0 2006.203.08:09:42.48#ibcon#read 5, iclass 37, count 0 2006.203.08:09:42.48#ibcon#about to read 6, iclass 37, count 0 2006.203.08:09:42.48#ibcon#read 6, iclass 37, count 0 2006.203.08:09:42.48#ibcon#end of sib2, iclass 37, count 0 2006.203.08:09:42.48#ibcon#*mode == 0, iclass 37, count 0 2006.203.08:09:42.48#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.203.08:09:42.48#ibcon#[27=USB\r\n] 2006.203.08:09:42.48#ibcon#*before write, iclass 37, count 0 2006.203.08:09:42.48#ibcon#enter sib2, iclass 37, count 0 2006.203.08:09:42.48#ibcon#flushed, iclass 37, count 0 2006.203.08:09:42.48#ibcon#about to write, iclass 37, count 0 2006.203.08:09:42.48#ibcon#wrote, iclass 37, count 0 2006.203.08:09:42.48#ibcon#about to read 3, iclass 37, count 0 2006.203.08:09:42.51#ibcon#read 3, iclass 37, count 0 2006.203.08:09:42.51#ibcon#about to read 4, iclass 37, count 0 2006.203.08:09:42.51#ibcon#read 4, iclass 37, count 0 2006.203.08:09:42.51#ibcon#about to read 5, iclass 37, count 0 2006.203.08:09:42.51#ibcon#read 5, iclass 37, count 0 2006.203.08:09:42.51#ibcon#about to read 6, iclass 37, count 0 2006.203.08:09:42.51#ibcon#read 6, iclass 37, count 0 2006.203.08:09:42.51#ibcon#end of sib2, iclass 37, count 0 2006.203.08:09:42.51#ibcon#*after write, iclass 37, count 0 2006.203.08:09:42.51#ibcon#*before return 0, iclass 37, count 0 2006.203.08:09:42.51#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.203.08:09:42.51#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.203.08:09:42.51#ibcon#about to clear, iclass 37 cls_cnt 0 2006.203.08:09:42.51#ibcon#cleared, iclass 37 cls_cnt 0 2006.203.08:09:42.52$vc4f8/vblo=2,640.99 2006.203.08:09:42.52#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.203.08:09:42.52#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.203.08:09:42.52#ibcon#ireg 17 cls_cnt 0 2006.203.08:09:42.52#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.203.08:09:42.52#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.203.08:09:42.52#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.203.08:09:42.52#ibcon#enter wrdev, iclass 5, count 0 2006.203.08:09:42.52#ibcon#first serial, iclass 5, count 0 2006.203.08:09:42.52#ibcon#enter sib2, iclass 5, count 0 2006.203.08:09:42.52#ibcon#flushed, iclass 5, count 0 2006.203.08:09:42.52#ibcon#about to write, iclass 5, count 0 2006.203.08:09:42.52#ibcon#wrote, iclass 5, count 0 2006.203.08:09:42.52#ibcon#about to read 3, iclass 5, count 0 2006.203.08:09:42.52#abcon#[5=S1D000X0/0*\r\n] 2006.203.08:09:42.53#ibcon#read 3, iclass 5, count 0 2006.203.08:09:42.53#ibcon#about to read 4, iclass 5, count 0 2006.203.08:09:42.53#ibcon#read 4, iclass 5, count 0 2006.203.08:09:42.53#ibcon#about to read 5, iclass 5, count 0 2006.203.08:09:42.53#ibcon#read 5, iclass 5, count 0 2006.203.08:09:42.53#ibcon#about to read 6, iclass 5, count 0 2006.203.08:09:42.53#ibcon#read 6, iclass 5, count 0 2006.203.08:09:42.53#ibcon#end of sib2, iclass 5, count 0 2006.203.08:09:42.53#ibcon#*mode == 0, iclass 5, count 0 2006.203.08:09:42.53#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.203.08:09:42.53#ibcon#[28=FRQ=02,640.99\r\n] 2006.203.08:09:42.53#ibcon#*before write, iclass 5, count 0 2006.203.08:09:42.53#ibcon#enter sib2, iclass 5, count 0 2006.203.08:09:42.53#ibcon#flushed, iclass 5, count 0 2006.203.08:09:42.53#ibcon#about to write, iclass 5, count 0 2006.203.08:09:42.53#ibcon#wrote, iclass 5, count 0 2006.203.08:09:42.53#ibcon#about to read 3, iclass 5, count 0 2006.203.08:09:42.57#ibcon#read 3, iclass 5, count 0 2006.203.08:09:42.57#ibcon#about to read 4, iclass 5, count 0 2006.203.08:09:42.57#ibcon#read 4, iclass 5, count 0 2006.203.08:09:42.57#ibcon#about to read 5, iclass 5, count 0 2006.203.08:09:42.57#ibcon#read 5, iclass 5, count 0 2006.203.08:09:42.57#ibcon#about to read 6, iclass 5, count 0 2006.203.08:09:42.57#ibcon#read 6, iclass 5, count 0 2006.203.08:09:42.57#ibcon#end of sib2, iclass 5, count 0 2006.203.08:09:42.57#ibcon#*after write, iclass 5, count 0 2006.203.08:09:42.57#ibcon#*before return 0, iclass 5, count 0 2006.203.08:09:42.57#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.203.08:09:42.57#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.203.08:09:42.57#ibcon#about to clear, iclass 5 cls_cnt 0 2006.203.08:09:42.57#ibcon#cleared, iclass 5 cls_cnt 0 2006.203.08:09:42.58$vc4f8/vb=2,4 2006.203.08:09:42.58#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.203.08:09:42.58#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.203.08:09:42.58#ibcon#ireg 11 cls_cnt 2 2006.203.08:09:42.58#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.203.08:09:42.62#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.203.08:09:42.62#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.203.08:09:42.62#ibcon#enter wrdev, iclass 7, count 2 2006.203.08:09:42.62#ibcon#first serial, iclass 7, count 2 2006.203.08:09:42.62#ibcon#enter sib2, iclass 7, count 2 2006.203.08:09:42.62#ibcon#flushed, iclass 7, count 2 2006.203.08:09:42.62#ibcon#about to write, iclass 7, count 2 2006.203.08:09:42.62#ibcon#wrote, iclass 7, count 2 2006.203.08:09:42.62#ibcon#about to read 3, iclass 7, count 2 2006.203.08:09:42.64#ibcon#read 3, iclass 7, count 2 2006.203.08:09:42.64#ibcon#about to read 4, iclass 7, count 2 2006.203.08:09:42.64#ibcon#read 4, iclass 7, count 2 2006.203.08:09:42.64#ibcon#about to read 5, iclass 7, count 2 2006.203.08:09:42.64#ibcon#read 5, iclass 7, count 2 2006.203.08:09:42.64#ibcon#about to read 6, iclass 7, count 2 2006.203.08:09:42.64#ibcon#read 6, iclass 7, count 2 2006.203.08:09:42.64#ibcon#end of sib2, iclass 7, count 2 2006.203.08:09:42.64#ibcon#*mode == 0, iclass 7, count 2 2006.203.08:09:42.64#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.203.08:09:42.64#ibcon#[27=AT02-04\r\n] 2006.203.08:09:42.64#ibcon#*before write, iclass 7, count 2 2006.203.08:09:42.64#ibcon#enter sib2, iclass 7, count 2 2006.203.08:09:42.64#ibcon#flushed, iclass 7, count 2 2006.203.08:09:42.64#ibcon#about to write, iclass 7, count 2 2006.203.08:09:42.64#ibcon#wrote, iclass 7, count 2 2006.203.08:09:42.64#ibcon#about to read 3, iclass 7, count 2 2006.203.08:09:42.67#ibcon#read 3, iclass 7, count 2 2006.203.08:09:42.67#ibcon#about to read 4, iclass 7, count 2 2006.203.08:09:42.67#ibcon#read 4, iclass 7, count 2 2006.203.08:09:42.67#ibcon#about to read 5, iclass 7, count 2 2006.203.08:09:42.67#ibcon#read 5, iclass 7, count 2 2006.203.08:09:42.67#ibcon#about to read 6, iclass 7, count 2 2006.203.08:09:42.67#ibcon#read 6, iclass 7, count 2 2006.203.08:09:42.67#ibcon#end of sib2, iclass 7, count 2 2006.203.08:09:42.67#ibcon#*after write, iclass 7, count 2 2006.203.08:09:42.67#ibcon#*before return 0, iclass 7, count 2 2006.203.08:09:42.67#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.203.08:09:42.67#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.203.08:09:42.67#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.203.08:09:42.67#ibcon#ireg 7 cls_cnt 0 2006.203.08:09:42.67#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.203.08:09:42.79#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.203.08:09:42.79#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.203.08:09:42.79#ibcon#enter wrdev, iclass 7, count 0 2006.203.08:09:42.79#ibcon#first serial, iclass 7, count 0 2006.203.08:09:42.79#ibcon#enter sib2, iclass 7, count 0 2006.203.08:09:42.79#ibcon#flushed, iclass 7, count 0 2006.203.08:09:42.79#ibcon#about to write, iclass 7, count 0 2006.203.08:09:42.79#ibcon#wrote, iclass 7, count 0 2006.203.08:09:42.79#ibcon#about to read 3, iclass 7, count 0 2006.203.08:09:42.81#ibcon#read 3, iclass 7, count 0 2006.203.08:09:42.81#ibcon#about to read 4, iclass 7, count 0 2006.203.08:09:42.81#ibcon#read 4, iclass 7, count 0 2006.203.08:09:42.81#ibcon#about to read 5, iclass 7, count 0 2006.203.08:09:42.81#ibcon#read 5, iclass 7, count 0 2006.203.08:09:42.81#ibcon#about to read 6, iclass 7, count 0 2006.203.08:09:42.81#ibcon#read 6, iclass 7, count 0 2006.203.08:09:42.81#ibcon#end of sib2, iclass 7, count 0 2006.203.08:09:42.81#ibcon#*mode == 0, iclass 7, count 0 2006.203.08:09:42.81#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.203.08:09:42.81#ibcon#[27=USB\r\n] 2006.203.08:09:42.81#ibcon#*before write, iclass 7, count 0 2006.203.08:09:42.81#ibcon#enter sib2, iclass 7, count 0 2006.203.08:09:42.81#ibcon#flushed, iclass 7, count 0 2006.203.08:09:42.81#ibcon#about to write, iclass 7, count 0 2006.203.08:09:42.81#ibcon#wrote, iclass 7, count 0 2006.203.08:09:42.81#ibcon#about to read 3, iclass 7, count 0 2006.203.08:09:42.84#ibcon#read 3, iclass 7, count 0 2006.203.08:09:42.84#ibcon#about to read 4, iclass 7, count 0 2006.203.08:09:42.84#ibcon#read 4, iclass 7, count 0 2006.203.08:09:42.84#ibcon#about to read 5, iclass 7, count 0 2006.203.08:09:42.84#ibcon#read 5, iclass 7, count 0 2006.203.08:09:42.84#ibcon#about to read 6, iclass 7, count 0 2006.203.08:09:42.84#ibcon#read 6, iclass 7, count 0 2006.203.08:09:42.84#ibcon#end of sib2, iclass 7, count 0 2006.203.08:09:42.84#ibcon#*after write, iclass 7, count 0 2006.203.08:09:42.84#ibcon#*before return 0, iclass 7, count 0 2006.203.08:09:42.84#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.203.08:09:42.84#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.203.08:09:42.84#ibcon#about to clear, iclass 7 cls_cnt 0 2006.203.08:09:42.84#ibcon#cleared, iclass 7 cls_cnt 0 2006.203.08:09:42.85$vc4f8/vblo=3,656.99 2006.203.08:09:42.85#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.203.08:09:42.85#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.203.08:09:42.85#ibcon#ireg 17 cls_cnt 0 2006.203.08:09:42.85#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.203.08:09:42.85#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.203.08:09:42.85#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.203.08:09:42.85#ibcon#enter wrdev, iclass 11, count 0 2006.203.08:09:42.85#ibcon#first serial, iclass 11, count 0 2006.203.08:09:42.85#ibcon#enter sib2, iclass 11, count 0 2006.203.08:09:42.85#ibcon#flushed, iclass 11, count 0 2006.203.08:09:42.85#ibcon#about to write, iclass 11, count 0 2006.203.08:09:42.85#ibcon#wrote, iclass 11, count 0 2006.203.08:09:42.85#ibcon#about to read 3, iclass 11, count 0 2006.203.08:09:42.87#ibcon#read 3, iclass 11, count 0 2006.203.08:09:42.87#ibcon#about to read 4, iclass 11, count 0 2006.203.08:09:42.87#ibcon#read 4, iclass 11, count 0 2006.203.08:09:42.87#ibcon#about to read 5, iclass 11, count 0 2006.203.08:09:42.87#ibcon#read 5, iclass 11, count 0 2006.203.08:09:42.87#ibcon#about to read 6, iclass 11, count 0 2006.203.08:09:42.87#ibcon#read 6, iclass 11, count 0 2006.203.08:09:42.87#ibcon#end of sib2, iclass 11, count 0 2006.203.08:09:42.87#ibcon#*mode == 0, iclass 11, count 0 2006.203.08:09:42.87#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.203.08:09:42.87#ibcon#[28=FRQ=03,656.99\r\n] 2006.203.08:09:42.87#ibcon#*before write, iclass 11, count 0 2006.203.08:09:42.87#ibcon#enter sib2, iclass 11, count 0 2006.203.08:09:42.87#ibcon#flushed, iclass 11, count 0 2006.203.08:09:42.87#ibcon#about to write, iclass 11, count 0 2006.203.08:09:42.87#ibcon#wrote, iclass 11, count 0 2006.203.08:09:42.87#ibcon#about to read 3, iclass 11, count 0 2006.203.08:09:42.91#ibcon#read 3, iclass 11, count 0 2006.203.08:09:42.91#ibcon#about to read 4, iclass 11, count 0 2006.203.08:09:42.91#ibcon#read 4, iclass 11, count 0 2006.203.08:09:42.91#ibcon#about to read 5, iclass 11, count 0 2006.203.08:09:42.91#ibcon#read 5, iclass 11, count 0 2006.203.08:09:42.91#ibcon#about to read 6, iclass 11, count 0 2006.203.08:09:42.91#ibcon#read 6, iclass 11, count 0 2006.203.08:09:42.91#ibcon#end of sib2, iclass 11, count 0 2006.203.08:09:42.91#ibcon#*after write, iclass 11, count 0 2006.203.08:09:42.91#ibcon#*before return 0, iclass 11, count 0 2006.203.08:09:42.91#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.203.08:09:42.91#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.203.08:09:42.91#ibcon#about to clear, iclass 11 cls_cnt 0 2006.203.08:09:42.91#ibcon#cleared, iclass 11 cls_cnt 0 2006.203.08:09:42.92$vc4f8/vb=3,4 2006.203.08:09:42.92#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.203.08:09:42.92#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.203.08:09:42.92#ibcon#ireg 11 cls_cnt 2 2006.203.08:09:42.92#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.203.08:09:42.95#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.203.08:09:42.95#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.203.08:09:42.95#ibcon#enter wrdev, iclass 13, count 2 2006.203.08:09:42.95#ibcon#first serial, iclass 13, count 2 2006.203.08:09:42.95#ibcon#enter sib2, iclass 13, count 2 2006.203.08:09:42.95#ibcon#flushed, iclass 13, count 2 2006.203.08:09:42.95#ibcon#about to write, iclass 13, count 2 2006.203.08:09:42.95#ibcon#wrote, iclass 13, count 2 2006.203.08:09:42.95#ibcon#about to read 3, iclass 13, count 2 2006.203.08:09:42.97#ibcon#read 3, iclass 13, count 2 2006.203.08:09:42.97#ibcon#about to read 4, iclass 13, count 2 2006.203.08:09:42.97#ibcon#read 4, iclass 13, count 2 2006.203.08:09:42.97#ibcon#about to read 5, iclass 13, count 2 2006.203.08:09:42.97#ibcon#read 5, iclass 13, count 2 2006.203.08:09:42.97#ibcon#about to read 6, iclass 13, count 2 2006.203.08:09:42.97#ibcon#read 6, iclass 13, count 2 2006.203.08:09:42.97#ibcon#end of sib2, iclass 13, count 2 2006.203.08:09:42.97#ibcon#*mode == 0, iclass 13, count 2 2006.203.08:09:42.97#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.203.08:09:42.97#ibcon#[27=AT03-04\r\n] 2006.203.08:09:42.97#ibcon#*before write, iclass 13, count 2 2006.203.08:09:42.97#ibcon#enter sib2, iclass 13, count 2 2006.203.08:09:42.97#ibcon#flushed, iclass 13, count 2 2006.203.08:09:42.97#ibcon#about to write, iclass 13, count 2 2006.203.08:09:42.97#ibcon#wrote, iclass 13, count 2 2006.203.08:09:42.97#ibcon#about to read 3, iclass 13, count 2 2006.203.08:09:43.00#ibcon#read 3, iclass 13, count 2 2006.203.08:09:43.00#ibcon#about to read 4, iclass 13, count 2 2006.203.08:09:43.00#ibcon#read 4, iclass 13, count 2 2006.203.08:09:43.00#ibcon#about to read 5, iclass 13, count 2 2006.203.08:09:43.00#ibcon#read 5, iclass 13, count 2 2006.203.08:09:43.00#ibcon#about to read 6, iclass 13, count 2 2006.203.08:09:43.00#ibcon#read 6, iclass 13, count 2 2006.203.08:09:43.00#ibcon#end of sib2, iclass 13, count 2 2006.203.08:09:43.00#ibcon#*after write, iclass 13, count 2 2006.203.08:09:43.00#ibcon#*before return 0, iclass 13, count 2 2006.203.08:09:43.00#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.203.08:09:43.00#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.203.08:09:43.00#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.203.08:09:43.00#ibcon#ireg 7 cls_cnt 0 2006.203.08:09:43.00#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.203.08:09:43.12#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.203.08:09:43.12#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.203.08:09:43.12#ibcon#enter wrdev, iclass 13, count 0 2006.203.08:09:43.12#ibcon#first serial, iclass 13, count 0 2006.203.08:09:43.12#ibcon#enter sib2, iclass 13, count 0 2006.203.08:09:43.12#ibcon#flushed, iclass 13, count 0 2006.203.08:09:43.12#ibcon#about to write, iclass 13, count 0 2006.203.08:09:43.12#ibcon#wrote, iclass 13, count 0 2006.203.08:09:43.12#ibcon#about to read 3, iclass 13, count 0 2006.203.08:09:43.14#ibcon#read 3, iclass 13, count 0 2006.203.08:09:43.14#ibcon#about to read 4, iclass 13, count 0 2006.203.08:09:43.14#ibcon#read 4, iclass 13, count 0 2006.203.08:09:43.14#ibcon#about to read 5, iclass 13, count 0 2006.203.08:09:43.14#ibcon#read 5, iclass 13, count 0 2006.203.08:09:43.14#ibcon#about to read 6, iclass 13, count 0 2006.203.08:09:43.14#ibcon#read 6, iclass 13, count 0 2006.203.08:09:43.14#ibcon#end of sib2, iclass 13, count 0 2006.203.08:09:43.14#ibcon#*mode == 0, iclass 13, count 0 2006.203.08:09:43.14#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.203.08:09:43.14#ibcon#[27=USB\r\n] 2006.203.08:09:43.14#ibcon#*before write, iclass 13, count 0 2006.203.08:09:43.14#ibcon#enter sib2, iclass 13, count 0 2006.203.08:09:43.14#ibcon#flushed, iclass 13, count 0 2006.203.08:09:43.14#ibcon#about to write, iclass 13, count 0 2006.203.08:09:43.14#ibcon#wrote, iclass 13, count 0 2006.203.08:09:43.14#ibcon#about to read 3, iclass 13, count 0 2006.203.08:09:43.17#ibcon#read 3, iclass 13, count 0 2006.203.08:09:43.17#ibcon#about to read 4, iclass 13, count 0 2006.203.08:09:43.17#ibcon#read 4, iclass 13, count 0 2006.203.08:09:43.17#ibcon#about to read 5, iclass 13, count 0 2006.203.08:09:43.17#ibcon#read 5, iclass 13, count 0 2006.203.08:09:43.17#ibcon#about to read 6, iclass 13, count 0 2006.203.08:09:43.17#ibcon#read 6, iclass 13, count 0 2006.203.08:09:43.17#ibcon#end of sib2, iclass 13, count 0 2006.203.08:09:43.17#ibcon#*after write, iclass 13, count 0 2006.203.08:09:43.17#ibcon#*before return 0, iclass 13, count 0 2006.203.08:09:43.17#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.203.08:09:43.17#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.203.08:09:43.17#ibcon#about to clear, iclass 13 cls_cnt 0 2006.203.08:09:43.17#ibcon#cleared, iclass 13 cls_cnt 0 2006.203.08:09:43.18$vc4f8/vblo=4,712.99 2006.203.08:09:43.18#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.203.08:09:43.18#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.203.08:09:43.18#ibcon#ireg 17 cls_cnt 0 2006.203.08:09:43.18#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.203.08:09:43.18#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.203.08:09:43.18#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.203.08:09:43.18#ibcon#enter wrdev, iclass 15, count 0 2006.203.08:09:43.18#ibcon#first serial, iclass 15, count 0 2006.203.08:09:43.18#ibcon#enter sib2, iclass 15, count 0 2006.203.08:09:43.18#ibcon#flushed, iclass 15, count 0 2006.203.08:09:43.18#ibcon#about to write, iclass 15, count 0 2006.203.08:09:43.18#ibcon#wrote, iclass 15, count 0 2006.203.08:09:43.18#ibcon#about to read 3, iclass 15, count 0 2006.203.08:09:43.19#ibcon#read 3, iclass 15, count 0 2006.203.08:09:43.19#ibcon#about to read 4, iclass 15, count 0 2006.203.08:09:43.19#ibcon#read 4, iclass 15, count 0 2006.203.08:09:43.19#ibcon#about to read 5, iclass 15, count 0 2006.203.08:09:43.19#ibcon#read 5, iclass 15, count 0 2006.203.08:09:43.19#ibcon#about to read 6, iclass 15, count 0 2006.203.08:09:43.19#ibcon#read 6, iclass 15, count 0 2006.203.08:09:43.19#ibcon#end of sib2, iclass 15, count 0 2006.203.08:09:43.19#ibcon#*mode == 0, iclass 15, count 0 2006.203.08:09:43.19#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.203.08:09:43.19#ibcon#[28=FRQ=04,712.99\r\n] 2006.203.08:09:43.19#ibcon#*before write, iclass 15, count 0 2006.203.08:09:43.19#ibcon#enter sib2, iclass 15, count 0 2006.203.08:09:43.19#ibcon#flushed, iclass 15, count 0 2006.203.08:09:43.19#ibcon#about to write, iclass 15, count 0 2006.203.08:09:43.19#ibcon#wrote, iclass 15, count 0 2006.203.08:09:43.19#ibcon#about to read 3, iclass 15, count 0 2006.203.08:09:43.23#ibcon#read 3, iclass 15, count 0 2006.203.08:09:43.23#ibcon#about to read 4, iclass 15, count 0 2006.203.08:09:43.23#ibcon#read 4, iclass 15, count 0 2006.203.08:09:43.23#ibcon#about to read 5, iclass 15, count 0 2006.203.08:09:43.23#ibcon#read 5, iclass 15, count 0 2006.203.08:09:43.23#ibcon#about to read 6, iclass 15, count 0 2006.203.08:09:43.23#ibcon#read 6, iclass 15, count 0 2006.203.08:09:43.23#ibcon#end of sib2, iclass 15, count 0 2006.203.08:09:43.23#ibcon#*after write, iclass 15, count 0 2006.203.08:09:43.23#ibcon#*before return 0, iclass 15, count 0 2006.203.08:09:43.23#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.203.08:09:43.23#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.203.08:09:43.23#ibcon#about to clear, iclass 15 cls_cnt 0 2006.203.08:09:43.23#ibcon#cleared, iclass 15 cls_cnt 0 2006.203.08:09:43.24$vc4f8/vb=4,4 2006.203.08:09:43.24#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.203.08:09:43.24#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.203.08:09:43.24#ibcon#ireg 11 cls_cnt 2 2006.203.08:09:43.24#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.203.08:09:43.28#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.203.08:09:43.28#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.203.08:09:43.28#ibcon#enter wrdev, iclass 17, count 2 2006.203.08:09:43.28#ibcon#first serial, iclass 17, count 2 2006.203.08:09:43.28#ibcon#enter sib2, iclass 17, count 2 2006.203.08:09:43.28#ibcon#flushed, iclass 17, count 2 2006.203.08:09:43.28#ibcon#about to write, iclass 17, count 2 2006.203.08:09:43.28#ibcon#wrote, iclass 17, count 2 2006.203.08:09:43.28#ibcon#about to read 3, iclass 17, count 2 2006.203.08:09:43.30#ibcon#read 3, iclass 17, count 2 2006.203.08:09:43.30#ibcon#about to read 4, iclass 17, count 2 2006.203.08:09:43.30#ibcon#read 4, iclass 17, count 2 2006.203.08:09:43.30#ibcon#about to read 5, iclass 17, count 2 2006.203.08:09:43.30#ibcon#read 5, iclass 17, count 2 2006.203.08:09:43.30#ibcon#about to read 6, iclass 17, count 2 2006.203.08:09:43.30#ibcon#read 6, iclass 17, count 2 2006.203.08:09:43.30#ibcon#end of sib2, iclass 17, count 2 2006.203.08:09:43.30#ibcon#*mode == 0, iclass 17, count 2 2006.203.08:09:43.30#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.203.08:09:43.30#ibcon#[27=AT04-04\r\n] 2006.203.08:09:43.30#ibcon#*before write, iclass 17, count 2 2006.203.08:09:43.30#ibcon#enter sib2, iclass 17, count 2 2006.203.08:09:43.30#ibcon#flushed, iclass 17, count 2 2006.203.08:09:43.30#ibcon#about to write, iclass 17, count 2 2006.203.08:09:43.30#ibcon#wrote, iclass 17, count 2 2006.203.08:09:43.30#ibcon#about to read 3, iclass 17, count 2 2006.203.08:09:43.33#ibcon#read 3, iclass 17, count 2 2006.203.08:09:43.33#ibcon#about to read 4, iclass 17, count 2 2006.203.08:09:43.33#ibcon#read 4, iclass 17, count 2 2006.203.08:09:43.33#ibcon#about to read 5, iclass 17, count 2 2006.203.08:09:43.33#ibcon#read 5, iclass 17, count 2 2006.203.08:09:43.33#ibcon#about to read 6, iclass 17, count 2 2006.203.08:09:43.33#ibcon#read 6, iclass 17, count 2 2006.203.08:09:43.33#ibcon#end of sib2, iclass 17, count 2 2006.203.08:09:43.33#ibcon#*after write, iclass 17, count 2 2006.203.08:09:43.33#ibcon#*before return 0, iclass 17, count 2 2006.203.08:09:43.33#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.203.08:09:43.33#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.203.08:09:43.33#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.203.08:09:43.33#ibcon#ireg 7 cls_cnt 0 2006.203.08:09:43.33#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.203.08:09:43.45#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.203.08:09:43.45#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.203.08:09:43.45#ibcon#enter wrdev, iclass 17, count 0 2006.203.08:09:43.45#ibcon#first serial, iclass 17, count 0 2006.203.08:09:43.45#ibcon#enter sib2, iclass 17, count 0 2006.203.08:09:43.45#ibcon#flushed, iclass 17, count 0 2006.203.08:09:43.45#ibcon#about to write, iclass 17, count 0 2006.203.08:09:43.45#ibcon#wrote, iclass 17, count 0 2006.203.08:09:43.45#ibcon#about to read 3, iclass 17, count 0 2006.203.08:09:43.47#ibcon#read 3, iclass 17, count 0 2006.203.08:09:43.47#ibcon#about to read 4, iclass 17, count 0 2006.203.08:09:43.47#ibcon#read 4, iclass 17, count 0 2006.203.08:09:43.47#ibcon#about to read 5, iclass 17, count 0 2006.203.08:09:43.47#ibcon#read 5, iclass 17, count 0 2006.203.08:09:43.47#ibcon#about to read 6, iclass 17, count 0 2006.203.08:09:43.47#ibcon#read 6, iclass 17, count 0 2006.203.08:09:43.47#ibcon#end of sib2, iclass 17, count 0 2006.203.08:09:43.47#ibcon#*mode == 0, iclass 17, count 0 2006.203.08:09:43.47#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.203.08:09:43.47#ibcon#[27=USB\r\n] 2006.203.08:09:43.47#ibcon#*before write, iclass 17, count 0 2006.203.08:09:43.47#ibcon#enter sib2, iclass 17, count 0 2006.203.08:09:43.47#ibcon#flushed, iclass 17, count 0 2006.203.08:09:43.47#ibcon#about to write, iclass 17, count 0 2006.203.08:09:43.47#ibcon#wrote, iclass 17, count 0 2006.203.08:09:43.47#ibcon#about to read 3, iclass 17, count 0 2006.203.08:09:43.50#ibcon#read 3, iclass 17, count 0 2006.203.08:09:43.50#ibcon#about to read 4, iclass 17, count 0 2006.203.08:09:43.50#ibcon#read 4, iclass 17, count 0 2006.203.08:09:43.50#ibcon#about to read 5, iclass 17, count 0 2006.203.08:09:43.50#ibcon#read 5, iclass 17, count 0 2006.203.08:09:43.50#ibcon#about to read 6, iclass 17, count 0 2006.203.08:09:43.50#ibcon#read 6, iclass 17, count 0 2006.203.08:09:43.50#ibcon#end of sib2, iclass 17, count 0 2006.203.08:09:43.50#ibcon#*after write, iclass 17, count 0 2006.203.08:09:43.50#ibcon#*before return 0, iclass 17, count 0 2006.203.08:09:43.50#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.203.08:09:43.50#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.203.08:09:43.50#ibcon#about to clear, iclass 17 cls_cnt 0 2006.203.08:09:43.50#ibcon#cleared, iclass 17 cls_cnt 0 2006.203.08:09:43.51$vc4f8/vblo=5,744.99 2006.203.08:09:43.51#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.203.08:09:43.51#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.203.08:09:43.51#ibcon#ireg 17 cls_cnt 0 2006.203.08:09:43.51#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.203.08:09:43.51#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.203.08:09:43.51#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.203.08:09:43.51#ibcon#enter wrdev, iclass 19, count 0 2006.203.08:09:43.51#ibcon#first serial, iclass 19, count 0 2006.203.08:09:43.51#ibcon#enter sib2, iclass 19, count 0 2006.203.08:09:43.51#ibcon#flushed, iclass 19, count 0 2006.203.08:09:43.51#ibcon#about to write, iclass 19, count 0 2006.203.08:09:43.51#ibcon#wrote, iclass 19, count 0 2006.203.08:09:43.51#ibcon#about to read 3, iclass 19, count 0 2006.203.08:09:43.52#ibcon#read 3, iclass 19, count 0 2006.203.08:09:43.52#ibcon#about to read 4, iclass 19, count 0 2006.203.08:09:43.52#ibcon#read 4, iclass 19, count 0 2006.203.08:09:43.52#ibcon#about to read 5, iclass 19, count 0 2006.203.08:09:43.52#ibcon#read 5, iclass 19, count 0 2006.203.08:09:43.52#ibcon#about to read 6, iclass 19, count 0 2006.203.08:09:43.52#ibcon#read 6, iclass 19, count 0 2006.203.08:09:43.52#ibcon#end of sib2, iclass 19, count 0 2006.203.08:09:43.52#ibcon#*mode == 0, iclass 19, count 0 2006.203.08:09:43.52#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.203.08:09:43.52#ibcon#[28=FRQ=05,744.99\r\n] 2006.203.08:09:43.52#ibcon#*before write, iclass 19, count 0 2006.203.08:09:43.52#ibcon#enter sib2, iclass 19, count 0 2006.203.08:09:43.52#ibcon#flushed, iclass 19, count 0 2006.203.08:09:43.52#ibcon#about to write, iclass 19, count 0 2006.203.08:09:43.52#ibcon#wrote, iclass 19, count 0 2006.203.08:09:43.52#ibcon#about to read 3, iclass 19, count 0 2006.203.08:09:43.56#ibcon#read 3, iclass 19, count 0 2006.203.08:09:43.56#ibcon#about to read 4, iclass 19, count 0 2006.203.08:09:43.56#ibcon#read 4, iclass 19, count 0 2006.203.08:09:43.56#ibcon#about to read 5, iclass 19, count 0 2006.203.08:09:43.56#ibcon#read 5, iclass 19, count 0 2006.203.08:09:43.56#ibcon#about to read 6, iclass 19, count 0 2006.203.08:09:43.56#ibcon#read 6, iclass 19, count 0 2006.203.08:09:43.56#ibcon#end of sib2, iclass 19, count 0 2006.203.08:09:43.56#ibcon#*after write, iclass 19, count 0 2006.203.08:09:43.56#ibcon#*before return 0, iclass 19, count 0 2006.203.08:09:43.56#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.203.08:09:43.56#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.203.08:09:43.56#ibcon#about to clear, iclass 19 cls_cnt 0 2006.203.08:09:43.56#ibcon#cleared, iclass 19 cls_cnt 0 2006.203.08:09:43.57$vc4f8/vb=5,3 2006.203.08:09:43.57#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.203.08:09:43.57#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.203.08:09:43.57#ibcon#ireg 11 cls_cnt 2 2006.203.08:09:43.57#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.203.08:09:43.61#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.203.08:09:43.61#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.203.08:09:43.61#ibcon#enter wrdev, iclass 21, count 2 2006.203.08:09:43.61#ibcon#first serial, iclass 21, count 2 2006.203.08:09:43.61#ibcon#enter sib2, iclass 21, count 2 2006.203.08:09:43.61#ibcon#flushed, iclass 21, count 2 2006.203.08:09:43.61#ibcon#about to write, iclass 21, count 2 2006.203.08:09:43.61#ibcon#wrote, iclass 21, count 2 2006.203.08:09:43.61#ibcon#about to read 3, iclass 21, count 2 2006.203.08:09:43.64#ibcon#read 3, iclass 21, count 2 2006.203.08:09:43.64#ibcon#about to read 4, iclass 21, count 2 2006.203.08:09:43.64#ibcon#read 4, iclass 21, count 2 2006.203.08:09:43.64#ibcon#about to read 5, iclass 21, count 2 2006.203.08:09:43.64#ibcon#read 5, iclass 21, count 2 2006.203.08:09:43.64#ibcon#about to read 6, iclass 21, count 2 2006.203.08:09:43.64#ibcon#read 6, iclass 21, count 2 2006.203.08:09:43.64#ibcon#end of sib2, iclass 21, count 2 2006.203.08:09:43.64#ibcon#*mode == 0, iclass 21, count 2 2006.203.08:09:43.64#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.203.08:09:43.64#ibcon#[27=AT05-03\r\n] 2006.203.08:09:43.64#ibcon#*before write, iclass 21, count 2 2006.203.08:09:43.64#ibcon#enter sib2, iclass 21, count 2 2006.203.08:09:43.64#ibcon#flushed, iclass 21, count 2 2006.203.08:09:43.64#ibcon#about to write, iclass 21, count 2 2006.203.08:09:43.64#ibcon#wrote, iclass 21, count 2 2006.203.08:09:43.64#ibcon#about to read 3, iclass 21, count 2 2006.203.08:09:43.67#ibcon#read 3, iclass 21, count 2 2006.203.08:09:43.67#ibcon#about to read 4, iclass 21, count 2 2006.203.08:09:43.67#ibcon#read 4, iclass 21, count 2 2006.203.08:09:43.67#ibcon#about to read 5, iclass 21, count 2 2006.203.08:09:43.67#ibcon#read 5, iclass 21, count 2 2006.203.08:09:43.67#ibcon#about to read 6, iclass 21, count 2 2006.203.08:09:43.67#ibcon#read 6, iclass 21, count 2 2006.203.08:09:43.67#ibcon#end of sib2, iclass 21, count 2 2006.203.08:09:43.67#ibcon#*after write, iclass 21, count 2 2006.203.08:09:43.67#ibcon#*before return 0, iclass 21, count 2 2006.203.08:09:43.67#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.203.08:09:43.67#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.203.08:09:43.67#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.203.08:09:43.67#ibcon#ireg 7 cls_cnt 0 2006.203.08:09:43.67#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.203.08:09:43.79#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.203.08:09:43.79#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.203.08:09:43.79#ibcon#enter wrdev, iclass 21, count 0 2006.203.08:09:43.79#ibcon#first serial, iclass 21, count 0 2006.203.08:09:43.79#ibcon#enter sib2, iclass 21, count 0 2006.203.08:09:43.79#ibcon#flushed, iclass 21, count 0 2006.203.08:09:43.79#ibcon#about to write, iclass 21, count 0 2006.203.08:09:43.79#ibcon#wrote, iclass 21, count 0 2006.203.08:09:43.79#ibcon#about to read 3, iclass 21, count 0 2006.203.08:09:43.81#ibcon#read 3, iclass 21, count 0 2006.203.08:09:43.81#ibcon#about to read 4, iclass 21, count 0 2006.203.08:09:43.81#ibcon#read 4, iclass 21, count 0 2006.203.08:09:43.81#ibcon#about to read 5, iclass 21, count 0 2006.203.08:09:43.81#ibcon#read 5, iclass 21, count 0 2006.203.08:09:43.81#ibcon#about to read 6, iclass 21, count 0 2006.203.08:09:43.81#ibcon#read 6, iclass 21, count 0 2006.203.08:09:43.81#ibcon#end of sib2, iclass 21, count 0 2006.203.08:09:43.81#ibcon#*mode == 0, iclass 21, count 0 2006.203.08:09:43.81#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.203.08:09:43.81#ibcon#[27=USB\r\n] 2006.203.08:09:43.81#ibcon#*before write, iclass 21, count 0 2006.203.08:09:43.81#ibcon#enter sib2, iclass 21, count 0 2006.203.08:09:43.81#ibcon#flushed, iclass 21, count 0 2006.203.08:09:43.81#ibcon#about to write, iclass 21, count 0 2006.203.08:09:43.81#ibcon#wrote, iclass 21, count 0 2006.203.08:09:43.81#ibcon#about to read 3, iclass 21, count 0 2006.203.08:09:43.84#ibcon#read 3, iclass 21, count 0 2006.203.08:09:43.84#ibcon#about to read 4, iclass 21, count 0 2006.203.08:09:43.84#ibcon#read 4, iclass 21, count 0 2006.203.08:09:43.84#ibcon#about to read 5, iclass 21, count 0 2006.203.08:09:43.84#ibcon#read 5, iclass 21, count 0 2006.203.08:09:43.84#ibcon#about to read 6, iclass 21, count 0 2006.203.08:09:43.84#ibcon#read 6, iclass 21, count 0 2006.203.08:09:43.84#ibcon#end of sib2, iclass 21, count 0 2006.203.08:09:43.84#ibcon#*after write, iclass 21, count 0 2006.203.08:09:43.84#ibcon#*before return 0, iclass 21, count 0 2006.203.08:09:43.84#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.203.08:09:43.84#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.203.08:09:43.84#ibcon#about to clear, iclass 21 cls_cnt 0 2006.203.08:09:43.84#ibcon#cleared, iclass 21 cls_cnt 0 2006.203.08:09:43.85$vc4f8/vblo=6,752.99 2006.203.08:09:43.85#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.203.08:09:43.85#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.203.08:09:43.85#ibcon#ireg 17 cls_cnt 0 2006.203.08:09:43.85#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.203.08:09:43.85#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.203.08:09:43.85#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.203.08:09:43.85#ibcon#enter wrdev, iclass 23, count 0 2006.203.08:09:43.85#ibcon#first serial, iclass 23, count 0 2006.203.08:09:43.85#ibcon#enter sib2, iclass 23, count 0 2006.203.08:09:43.85#ibcon#flushed, iclass 23, count 0 2006.203.08:09:43.85#ibcon#about to write, iclass 23, count 0 2006.203.08:09:43.85#ibcon#wrote, iclass 23, count 0 2006.203.08:09:43.85#ibcon#about to read 3, iclass 23, count 0 2006.203.08:09:43.86#ibcon#read 3, iclass 23, count 0 2006.203.08:09:43.86#ibcon#about to read 4, iclass 23, count 0 2006.203.08:09:43.86#ibcon#read 4, iclass 23, count 0 2006.203.08:09:43.86#ibcon#about to read 5, iclass 23, count 0 2006.203.08:09:43.86#ibcon#read 5, iclass 23, count 0 2006.203.08:09:43.86#ibcon#about to read 6, iclass 23, count 0 2006.203.08:09:43.86#ibcon#read 6, iclass 23, count 0 2006.203.08:09:43.86#ibcon#end of sib2, iclass 23, count 0 2006.203.08:09:43.86#ibcon#*mode == 0, iclass 23, count 0 2006.203.08:09:43.86#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.203.08:09:43.86#ibcon#[28=FRQ=06,752.99\r\n] 2006.203.08:09:43.86#ibcon#*before write, iclass 23, count 0 2006.203.08:09:43.86#ibcon#enter sib2, iclass 23, count 0 2006.203.08:09:43.86#ibcon#flushed, iclass 23, count 0 2006.203.08:09:43.86#ibcon#about to write, iclass 23, count 0 2006.203.08:09:43.86#ibcon#wrote, iclass 23, count 0 2006.203.08:09:43.86#ibcon#about to read 3, iclass 23, count 0 2006.203.08:09:43.90#ibcon#read 3, iclass 23, count 0 2006.203.08:09:43.90#ibcon#about to read 4, iclass 23, count 0 2006.203.08:09:43.90#ibcon#read 4, iclass 23, count 0 2006.203.08:09:43.90#ibcon#about to read 5, iclass 23, count 0 2006.203.08:09:43.90#ibcon#read 5, iclass 23, count 0 2006.203.08:09:43.90#ibcon#about to read 6, iclass 23, count 0 2006.203.08:09:43.90#ibcon#read 6, iclass 23, count 0 2006.203.08:09:43.90#ibcon#end of sib2, iclass 23, count 0 2006.203.08:09:43.90#ibcon#*after write, iclass 23, count 0 2006.203.08:09:43.90#ibcon#*before return 0, iclass 23, count 0 2006.203.08:09:43.90#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.203.08:09:43.90#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.203.08:09:43.90#ibcon#about to clear, iclass 23 cls_cnt 0 2006.203.08:09:43.90#ibcon#cleared, iclass 23 cls_cnt 0 2006.203.08:09:43.91$vc4f8/vb=6,4 2006.203.08:09:43.91#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.203.08:09:43.91#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.203.08:09:43.91#ibcon#ireg 11 cls_cnt 2 2006.203.08:09:43.91#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.203.08:09:43.95#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.203.08:09:43.95#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.203.08:09:43.95#ibcon#enter wrdev, iclass 25, count 2 2006.203.08:09:43.95#ibcon#first serial, iclass 25, count 2 2006.203.08:09:43.95#ibcon#enter sib2, iclass 25, count 2 2006.203.08:09:43.95#ibcon#flushed, iclass 25, count 2 2006.203.08:09:43.95#ibcon#about to write, iclass 25, count 2 2006.203.08:09:43.95#ibcon#wrote, iclass 25, count 2 2006.203.08:09:43.95#ibcon#about to read 3, iclass 25, count 2 2006.203.08:09:43.97#ibcon#read 3, iclass 25, count 2 2006.203.08:09:43.97#ibcon#about to read 4, iclass 25, count 2 2006.203.08:09:43.97#ibcon#read 4, iclass 25, count 2 2006.203.08:09:43.97#ibcon#about to read 5, iclass 25, count 2 2006.203.08:09:43.97#ibcon#read 5, iclass 25, count 2 2006.203.08:09:43.97#ibcon#about to read 6, iclass 25, count 2 2006.203.08:09:43.97#ibcon#read 6, iclass 25, count 2 2006.203.08:09:43.97#ibcon#end of sib2, iclass 25, count 2 2006.203.08:09:43.97#ibcon#*mode == 0, iclass 25, count 2 2006.203.08:09:43.97#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.203.08:09:43.97#ibcon#[27=AT06-04\r\n] 2006.203.08:09:43.97#ibcon#*before write, iclass 25, count 2 2006.203.08:09:43.97#ibcon#enter sib2, iclass 25, count 2 2006.203.08:09:43.97#ibcon#flushed, iclass 25, count 2 2006.203.08:09:43.97#ibcon#about to write, iclass 25, count 2 2006.203.08:09:43.97#ibcon#wrote, iclass 25, count 2 2006.203.08:09:43.97#ibcon#about to read 3, iclass 25, count 2 2006.203.08:09:44.00#ibcon#read 3, iclass 25, count 2 2006.203.08:09:44.00#ibcon#about to read 4, iclass 25, count 2 2006.203.08:09:44.00#ibcon#read 4, iclass 25, count 2 2006.203.08:09:44.00#ibcon#about to read 5, iclass 25, count 2 2006.203.08:09:44.00#ibcon#read 5, iclass 25, count 2 2006.203.08:09:44.00#ibcon#about to read 6, iclass 25, count 2 2006.203.08:09:44.00#ibcon#read 6, iclass 25, count 2 2006.203.08:09:44.00#ibcon#end of sib2, iclass 25, count 2 2006.203.08:09:44.00#ibcon#*after write, iclass 25, count 2 2006.203.08:09:44.00#ibcon#*before return 0, iclass 25, count 2 2006.203.08:09:44.00#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.203.08:09:44.00#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.203.08:09:44.00#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.203.08:09:44.00#ibcon#ireg 7 cls_cnt 0 2006.203.08:09:44.00#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.203.08:09:44.12#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.203.08:09:44.12#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.203.08:09:44.12#ibcon#enter wrdev, iclass 25, count 0 2006.203.08:09:44.12#ibcon#first serial, iclass 25, count 0 2006.203.08:09:44.12#ibcon#enter sib2, iclass 25, count 0 2006.203.08:09:44.12#ibcon#flushed, iclass 25, count 0 2006.203.08:09:44.12#ibcon#about to write, iclass 25, count 0 2006.203.08:09:44.12#ibcon#wrote, iclass 25, count 0 2006.203.08:09:44.12#ibcon#about to read 3, iclass 25, count 0 2006.203.08:09:44.14#ibcon#read 3, iclass 25, count 0 2006.203.08:09:44.14#ibcon#about to read 4, iclass 25, count 0 2006.203.08:09:44.14#ibcon#read 4, iclass 25, count 0 2006.203.08:09:44.14#ibcon#about to read 5, iclass 25, count 0 2006.203.08:09:44.14#ibcon#read 5, iclass 25, count 0 2006.203.08:09:44.14#ibcon#about to read 6, iclass 25, count 0 2006.203.08:09:44.14#ibcon#read 6, iclass 25, count 0 2006.203.08:09:44.14#ibcon#end of sib2, iclass 25, count 0 2006.203.08:09:44.14#ibcon#*mode == 0, iclass 25, count 0 2006.203.08:09:44.14#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.203.08:09:44.14#ibcon#[27=USB\r\n] 2006.203.08:09:44.14#ibcon#*before write, iclass 25, count 0 2006.203.08:09:44.14#ibcon#enter sib2, iclass 25, count 0 2006.203.08:09:44.14#ibcon#flushed, iclass 25, count 0 2006.203.08:09:44.14#ibcon#about to write, iclass 25, count 0 2006.203.08:09:44.14#ibcon#wrote, iclass 25, count 0 2006.203.08:09:44.14#ibcon#about to read 3, iclass 25, count 0 2006.203.08:09:44.17#ibcon#read 3, iclass 25, count 0 2006.203.08:09:44.17#ibcon#about to read 4, iclass 25, count 0 2006.203.08:09:44.17#ibcon#read 4, iclass 25, count 0 2006.203.08:09:44.17#ibcon#about to read 5, iclass 25, count 0 2006.203.08:09:44.17#ibcon#read 5, iclass 25, count 0 2006.203.08:09:44.17#ibcon#about to read 6, iclass 25, count 0 2006.203.08:09:44.17#ibcon#read 6, iclass 25, count 0 2006.203.08:09:44.17#ibcon#end of sib2, iclass 25, count 0 2006.203.08:09:44.17#ibcon#*after write, iclass 25, count 0 2006.203.08:09:44.17#ibcon#*before return 0, iclass 25, count 0 2006.203.08:09:44.17#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.203.08:09:44.17#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.203.08:09:44.17#ibcon#about to clear, iclass 25 cls_cnt 0 2006.203.08:09:44.17#ibcon#cleared, iclass 25 cls_cnt 0 2006.203.08:09:44.18$vc4f8/vabw=wide 2006.203.08:09:44.18#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.203.08:09:44.18#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.203.08:09:44.18#ibcon#ireg 8 cls_cnt 0 2006.203.08:09:44.18#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.203.08:09:44.18#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.203.08:09:44.18#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.203.08:09:44.18#ibcon#enter wrdev, iclass 27, count 0 2006.203.08:09:44.18#ibcon#first serial, iclass 27, count 0 2006.203.08:09:44.18#ibcon#enter sib2, iclass 27, count 0 2006.203.08:09:44.18#ibcon#flushed, iclass 27, count 0 2006.203.08:09:44.18#ibcon#about to write, iclass 27, count 0 2006.203.08:09:44.18#ibcon#wrote, iclass 27, count 0 2006.203.08:09:44.18#ibcon#about to read 3, iclass 27, count 0 2006.203.08:09:44.19#ibcon#read 3, iclass 27, count 0 2006.203.08:09:44.19#ibcon#about to read 4, iclass 27, count 0 2006.203.08:09:44.19#ibcon#read 4, iclass 27, count 0 2006.203.08:09:44.19#ibcon#about to read 5, iclass 27, count 0 2006.203.08:09:44.19#ibcon#read 5, iclass 27, count 0 2006.203.08:09:44.19#ibcon#about to read 6, iclass 27, count 0 2006.203.08:09:44.19#ibcon#read 6, iclass 27, count 0 2006.203.08:09:44.19#ibcon#end of sib2, iclass 27, count 0 2006.203.08:09:44.19#ibcon#*mode == 0, iclass 27, count 0 2006.203.08:09:44.19#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.203.08:09:44.19#ibcon#[25=BW32\r\n] 2006.203.08:09:44.19#ibcon#*before write, iclass 27, count 0 2006.203.08:09:44.19#ibcon#enter sib2, iclass 27, count 0 2006.203.08:09:44.19#ibcon#flushed, iclass 27, count 0 2006.203.08:09:44.19#ibcon#about to write, iclass 27, count 0 2006.203.08:09:44.19#ibcon#wrote, iclass 27, count 0 2006.203.08:09:44.19#ibcon#about to read 3, iclass 27, count 0 2006.203.08:09:44.22#ibcon#read 3, iclass 27, count 0 2006.203.08:09:44.22#ibcon#about to read 4, iclass 27, count 0 2006.203.08:09:44.22#ibcon#read 4, iclass 27, count 0 2006.203.08:09:44.22#ibcon#about to read 5, iclass 27, count 0 2006.203.08:09:44.22#ibcon#read 5, iclass 27, count 0 2006.203.08:09:44.22#ibcon#about to read 6, iclass 27, count 0 2006.203.08:09:44.22#ibcon#read 6, iclass 27, count 0 2006.203.08:09:44.22#ibcon#end of sib2, iclass 27, count 0 2006.203.08:09:44.22#ibcon#*after write, iclass 27, count 0 2006.203.08:09:44.22#ibcon#*before return 0, iclass 27, count 0 2006.203.08:09:44.22#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.203.08:09:44.22#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.203.08:09:44.22#ibcon#about to clear, iclass 27 cls_cnt 0 2006.203.08:09:44.22#ibcon#cleared, iclass 27 cls_cnt 0 2006.203.08:09:44.23$vc4f8/vbbw=wide 2006.203.08:09:44.23#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.203.08:09:44.23#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.203.08:09:44.23#ibcon#ireg 8 cls_cnt 0 2006.203.08:09:44.23#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.203.08:09:44.28#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.203.08:09:44.28#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.203.08:09:44.28#ibcon#enter wrdev, iclass 29, count 0 2006.203.08:09:44.28#ibcon#first serial, iclass 29, count 0 2006.203.08:09:44.28#ibcon#enter sib2, iclass 29, count 0 2006.203.08:09:44.28#ibcon#flushed, iclass 29, count 0 2006.203.08:09:44.28#ibcon#about to write, iclass 29, count 0 2006.203.08:09:44.28#ibcon#wrote, iclass 29, count 0 2006.203.08:09:44.28#ibcon#about to read 3, iclass 29, count 0 2006.203.08:09:44.30#ibcon#read 3, iclass 29, count 0 2006.203.08:09:44.30#ibcon#about to read 4, iclass 29, count 0 2006.203.08:09:44.30#ibcon#read 4, iclass 29, count 0 2006.203.08:09:44.30#ibcon#about to read 5, iclass 29, count 0 2006.203.08:09:44.30#ibcon#read 5, iclass 29, count 0 2006.203.08:09:44.30#ibcon#about to read 6, iclass 29, count 0 2006.203.08:09:44.30#ibcon#read 6, iclass 29, count 0 2006.203.08:09:44.30#ibcon#end of sib2, iclass 29, count 0 2006.203.08:09:44.30#ibcon#*mode == 0, iclass 29, count 0 2006.203.08:09:44.30#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.203.08:09:44.30#ibcon#[27=BW32\r\n] 2006.203.08:09:44.30#ibcon#*before write, iclass 29, count 0 2006.203.08:09:44.30#ibcon#enter sib2, iclass 29, count 0 2006.203.08:09:44.30#ibcon#flushed, iclass 29, count 0 2006.203.08:09:44.30#ibcon#about to write, iclass 29, count 0 2006.203.08:09:44.30#ibcon#wrote, iclass 29, count 0 2006.203.08:09:44.30#ibcon#about to read 3, iclass 29, count 0 2006.203.08:09:44.33#ibcon#read 3, iclass 29, count 0 2006.203.08:09:44.33#ibcon#about to read 4, iclass 29, count 0 2006.203.08:09:44.33#ibcon#read 4, iclass 29, count 0 2006.203.08:09:44.33#ibcon#about to read 5, iclass 29, count 0 2006.203.08:09:44.33#ibcon#read 5, iclass 29, count 0 2006.203.08:09:44.33#ibcon#about to read 6, iclass 29, count 0 2006.203.08:09:44.33#ibcon#read 6, iclass 29, count 0 2006.203.08:09:44.33#ibcon#end of sib2, iclass 29, count 0 2006.203.08:09:44.33#ibcon#*after write, iclass 29, count 0 2006.203.08:09:44.33#ibcon#*before return 0, iclass 29, count 0 2006.203.08:09:44.33#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.203.08:09:44.33#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.203.08:09:44.33#ibcon#about to clear, iclass 29 cls_cnt 0 2006.203.08:09:44.33#ibcon#cleared, iclass 29 cls_cnt 0 2006.203.08:09:44.34$4f8m12a/ifd4f 2006.203.08:09:44.34$ifd4f/lo= 2006.203.08:09:44.34$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.203.08:09:44.34$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.203.08:09:44.34$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.203.08:09:44.34$ifd4f/patch= 2006.203.08:09:44.34$ifd4f/patch=lo1,a1,a2,a3,a4 2006.203.08:09:44.34$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.203.08:09:44.34$ifd4f/patch=lo3,a5,a6,a7,a8 2006.203.08:09:44.34$4f8m12a/"form=m,16.000,1:2 2006.203.08:09:44.34$4f8m12a/"tpicd 2006.203.08:09:44.34$4f8m12a/echo=off 2006.203.08:09:44.34$4f8m12a/xlog=off 2006.203.08:09:44.34:!2006.203.08:10:10 2006.203.08:09:54.14#trakl#Source acquired 2006.203.08:09:55.15#flagr#flagr/antenna,acquired 2006.203.08:10:10.02:preob 2006.203.08:10:11.15/onsource/TRACKING 2006.203.08:10:11.15:!2006.203.08:10:20 2006.203.08:10:20.02:data_valid=on 2006.203.08:10:20.02:midob 2006.203.08:10:21.15/onsource/TRACKING 2006.203.08:10:21.15/wx/23.64,1001.0,100 2006.203.08:10:21.22/cable/+6.4625E-03 2006.203.08:10:22.31/va/01,08,usb,yes,28,30 2006.203.08:10:22.31/va/02,07,usb,yes,28,30 2006.203.08:10:22.31/va/03,08,usb,yes,21,21 2006.203.08:10:22.31/va/04,07,usb,yes,29,31 2006.203.08:10:22.31/va/05,07,usb,yes,32,34 2006.203.08:10:22.31/va/06,06,usb,yes,31,31 2006.203.08:10:22.31/va/07,07,usb,yes,27,27 2006.203.08:10:22.31/va/08,06,usb,yes,34,33 2006.203.08:10:22.54/valo/01,532.99,yes,locked 2006.203.08:10:22.54/valo/02,572.99,yes,locked 2006.203.08:10:22.54/valo/03,672.99,yes,locked 2006.203.08:10:22.54/valo/04,832.99,yes,locked 2006.203.08:10:22.54/valo/05,652.99,yes,locked 2006.203.08:10:22.54/valo/06,772.99,yes,locked 2006.203.08:10:22.54/valo/07,832.99,yes,locked 2006.203.08:10:22.54/valo/08,852.99,yes,locked 2006.203.08:10:23.63/vb/01,04,usb,yes,28,27 2006.203.08:10:23.63/vb/02,04,usb,yes,30,31 2006.203.08:10:23.63/vb/03,04,usb,yes,26,30 2006.203.08:10:23.63/vb/04,04,usb,yes,27,27 2006.203.08:10:23.63/vb/05,03,usb,yes,32,36 2006.203.08:10:23.63/vb/06,04,usb,yes,27,29 2006.203.08:10:23.63/vb/07,04,usb,yes,29,28 2006.203.08:10:23.63/vb/08,04,usb,yes,26,29 2006.203.08:10:23.86/vblo/01,632.99,yes,locked 2006.203.08:10:23.86/vblo/02,640.99,yes,locked 2006.203.08:10:23.86/vblo/03,656.99,yes,locked 2006.203.08:10:23.86/vblo/04,712.99,yes,locked 2006.203.08:10:23.86/vblo/05,744.99,yes,locked 2006.203.08:10:23.86/vblo/06,752.99,yes,locked 2006.203.08:10:23.86/vblo/07,734.99,yes,locked 2006.203.08:10:23.86/vblo/08,744.99,yes,locked 2006.203.08:10:24.01/vabw/8 2006.203.08:10:24.16/vbbw/8 2006.203.08:10:24.25/xfe/off,on,13.7 2006.203.08:10:24.62/ifatt/23,28,28,28 2006.203.08:10:25.07/fmout-gps/S +4.56E-07 2006.203.08:10:25.12:!2006.203.08:11:20 2006.203.08:11:20.02:data_valid=off 2006.203.08:11:20.02:postob 2006.203.08:11:20.17/cable/+6.4585E-03 2006.203.08:11:20.18/wx/23.62,1001.0,100 2006.203.08:11:21.07/fmout-gps/S +4.57E-07 2006.203.08:11:21.08:scan_name=203-0812,k06203,60 2006.203.08:11:21.08:source=3c371,180650.68,694928.1,2000.0,cw 2006.203.08:11:22.14#flagr#flagr/antenna,new-source 2006.203.08:11:22.15:checkk5 2006.203.08:11:22.58/chk_autoobs//k5ts1/ autoobs is running! 2006.203.08:11:22.97/chk_autoobs//k5ts2/ autoobs is running! 2006.203.08:11:23.41/chk_autoobs//k5ts3/ autoobs is running! 2006.203.08:11:23.85/chk_autoobs//k5ts4/ autoobs is running! 2006.203.08:11:24.23/chk_obsdata//k5ts1/T2030810??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.203.08:11:24.66/chk_obsdata//k5ts2/T2030810??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.203.08:11:25.03/chk_obsdata//k5ts3/T2030810??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.203.08:11:25.45/chk_obsdata//k5ts4/T2030810??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.203.08:11:26.28/k5log//k5ts1_log_newline 2006.203.08:11:27.27/k5log//k5ts2_log_newline 2006.203.08:11:28.04/k5log//k5ts3_log_newline 2006.203.08:11:28.81/k5log//k5ts4_log_newline 2006.203.08:11:28.83/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.203.08:11:28.83:4f8m12a=2 2006.203.08:11:28.83$4f8m12a/echo=on 2006.203.08:11:28.83$4f8m12a/pcalon 2006.203.08:11:28.83$pcalon/"no phase cal control is implemented here 2006.203.08:11:28.83$4f8m12a/"tpicd=stop 2006.203.08:11:28.83$4f8m12a/vc4f8 2006.203.08:11:28.83$vc4f8/valo=1,532.99 2006.203.08:11:28.84#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.203.08:11:28.84#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.203.08:11:28.84#ibcon#ireg 17 cls_cnt 0 2006.203.08:11:28.84#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.203.08:11:28.84#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.203.08:11:28.84#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.203.08:11:28.84#ibcon#enter wrdev, iclass 36, count 0 2006.203.08:11:28.84#ibcon#first serial, iclass 36, count 0 2006.203.08:11:28.84#ibcon#enter sib2, iclass 36, count 0 2006.203.08:11:28.84#ibcon#flushed, iclass 36, count 0 2006.203.08:11:28.84#ibcon#about to write, iclass 36, count 0 2006.203.08:11:28.84#ibcon#wrote, iclass 36, count 0 2006.203.08:11:28.84#ibcon#about to read 3, iclass 36, count 0 2006.203.08:11:28.88#ibcon#read 3, iclass 36, count 0 2006.203.08:11:28.88#ibcon#about to read 4, iclass 36, count 0 2006.203.08:11:28.88#ibcon#read 4, iclass 36, count 0 2006.203.08:11:28.88#ibcon#about to read 5, iclass 36, count 0 2006.203.08:11:28.88#ibcon#read 5, iclass 36, count 0 2006.203.08:11:28.88#ibcon#about to read 6, iclass 36, count 0 2006.203.08:11:28.88#ibcon#read 6, iclass 36, count 0 2006.203.08:11:28.88#ibcon#end of sib2, iclass 36, count 0 2006.203.08:11:28.88#ibcon#*mode == 0, iclass 36, count 0 2006.203.08:11:28.88#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.203.08:11:28.88#ibcon#[26=FRQ=01,532.99\r\n] 2006.203.08:11:28.88#ibcon#*before write, iclass 36, count 0 2006.203.08:11:28.88#ibcon#enter sib2, iclass 36, count 0 2006.203.08:11:28.88#ibcon#flushed, iclass 36, count 0 2006.203.08:11:28.88#ibcon#about to write, iclass 36, count 0 2006.203.08:11:28.88#ibcon#wrote, iclass 36, count 0 2006.203.08:11:28.88#ibcon#about to read 3, iclass 36, count 0 2006.203.08:11:28.92#ibcon#read 3, iclass 36, count 0 2006.203.08:11:28.92#ibcon#about to read 4, iclass 36, count 0 2006.203.08:11:28.92#ibcon#read 4, iclass 36, count 0 2006.203.08:11:28.92#ibcon#about to read 5, iclass 36, count 0 2006.203.08:11:28.92#ibcon#read 5, iclass 36, count 0 2006.203.08:11:28.92#ibcon#about to read 6, iclass 36, count 0 2006.203.08:11:28.92#ibcon#read 6, iclass 36, count 0 2006.203.08:11:28.92#ibcon#end of sib2, iclass 36, count 0 2006.203.08:11:28.92#ibcon#*after write, iclass 36, count 0 2006.203.08:11:28.92#ibcon#*before return 0, iclass 36, count 0 2006.203.08:11:28.92#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.203.08:11:28.92#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.203.08:11:28.92#ibcon#about to clear, iclass 36 cls_cnt 0 2006.203.08:11:28.92#ibcon#cleared, iclass 36 cls_cnt 0 2006.203.08:11:28.92$vc4f8/va=1,8 2006.203.08:11:28.92#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.203.08:11:28.92#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.203.08:11:28.92#ibcon#ireg 11 cls_cnt 2 2006.203.08:11:28.92#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.203.08:11:28.92#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.203.08:11:28.92#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.203.08:11:28.92#ibcon#enter wrdev, iclass 38, count 2 2006.203.08:11:28.92#ibcon#first serial, iclass 38, count 2 2006.203.08:11:28.92#ibcon#enter sib2, iclass 38, count 2 2006.203.08:11:28.92#ibcon#flushed, iclass 38, count 2 2006.203.08:11:28.92#ibcon#about to write, iclass 38, count 2 2006.203.08:11:28.93#ibcon#wrote, iclass 38, count 2 2006.203.08:11:28.93#ibcon#about to read 3, iclass 38, count 2 2006.203.08:11:28.95#ibcon#read 3, iclass 38, count 2 2006.203.08:11:28.95#ibcon#about to read 4, iclass 38, count 2 2006.203.08:11:28.95#ibcon#read 4, iclass 38, count 2 2006.203.08:11:28.95#ibcon#about to read 5, iclass 38, count 2 2006.203.08:11:28.95#ibcon#read 5, iclass 38, count 2 2006.203.08:11:28.95#ibcon#about to read 6, iclass 38, count 2 2006.203.08:11:28.95#ibcon#read 6, iclass 38, count 2 2006.203.08:11:28.95#ibcon#end of sib2, iclass 38, count 2 2006.203.08:11:28.95#ibcon#*mode == 0, iclass 38, count 2 2006.203.08:11:28.95#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.203.08:11:28.95#ibcon#[25=AT01-08\r\n] 2006.203.08:11:28.95#ibcon#*before write, iclass 38, count 2 2006.203.08:11:28.95#ibcon#enter sib2, iclass 38, count 2 2006.203.08:11:28.95#ibcon#flushed, iclass 38, count 2 2006.203.08:11:28.95#ibcon#about to write, iclass 38, count 2 2006.203.08:11:28.95#ibcon#wrote, iclass 38, count 2 2006.203.08:11:28.95#ibcon#about to read 3, iclass 38, count 2 2006.203.08:11:28.98#ibcon#read 3, iclass 38, count 2 2006.203.08:11:28.98#ibcon#about to read 4, iclass 38, count 2 2006.203.08:11:28.98#ibcon#read 4, iclass 38, count 2 2006.203.08:11:28.98#ibcon#about to read 5, iclass 38, count 2 2006.203.08:11:28.98#ibcon#read 5, iclass 38, count 2 2006.203.08:11:28.98#ibcon#about to read 6, iclass 38, count 2 2006.203.08:11:28.98#ibcon#read 6, iclass 38, count 2 2006.203.08:11:28.98#ibcon#end of sib2, iclass 38, count 2 2006.203.08:11:28.98#ibcon#*after write, iclass 38, count 2 2006.203.08:11:28.98#ibcon#*before return 0, iclass 38, count 2 2006.203.08:11:28.98#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.203.08:11:28.98#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.203.08:11:28.98#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.203.08:11:28.98#ibcon#ireg 7 cls_cnt 0 2006.203.08:11:28.98#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.203.08:11:29.10#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.203.08:11:29.10#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.203.08:11:29.10#ibcon#enter wrdev, iclass 38, count 0 2006.203.08:11:29.10#ibcon#first serial, iclass 38, count 0 2006.203.08:11:29.10#ibcon#enter sib2, iclass 38, count 0 2006.203.08:11:29.10#ibcon#flushed, iclass 38, count 0 2006.203.08:11:29.10#ibcon#about to write, iclass 38, count 0 2006.203.08:11:29.10#ibcon#wrote, iclass 38, count 0 2006.203.08:11:29.10#ibcon#about to read 3, iclass 38, count 0 2006.203.08:11:29.12#ibcon#read 3, iclass 38, count 0 2006.203.08:11:29.12#ibcon#about to read 4, iclass 38, count 0 2006.203.08:11:29.12#ibcon#read 4, iclass 38, count 0 2006.203.08:11:29.12#ibcon#about to read 5, iclass 38, count 0 2006.203.08:11:29.12#ibcon#read 5, iclass 38, count 0 2006.203.08:11:29.12#ibcon#about to read 6, iclass 38, count 0 2006.203.08:11:29.12#ibcon#read 6, iclass 38, count 0 2006.203.08:11:29.12#ibcon#end of sib2, iclass 38, count 0 2006.203.08:11:29.12#ibcon#*mode == 0, iclass 38, count 0 2006.203.08:11:29.12#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.203.08:11:29.12#ibcon#[25=USB\r\n] 2006.203.08:11:29.12#ibcon#*before write, iclass 38, count 0 2006.203.08:11:29.12#ibcon#enter sib2, iclass 38, count 0 2006.203.08:11:29.12#ibcon#flushed, iclass 38, count 0 2006.203.08:11:29.12#ibcon#about to write, iclass 38, count 0 2006.203.08:11:29.12#ibcon#wrote, iclass 38, count 0 2006.203.08:11:29.12#ibcon#about to read 3, iclass 38, count 0 2006.203.08:11:29.15#ibcon#read 3, iclass 38, count 0 2006.203.08:11:29.15#ibcon#about to read 4, iclass 38, count 0 2006.203.08:11:29.15#ibcon#read 4, iclass 38, count 0 2006.203.08:11:29.15#ibcon#about to read 5, iclass 38, count 0 2006.203.08:11:29.15#ibcon#read 5, iclass 38, count 0 2006.203.08:11:29.15#ibcon#about to read 6, iclass 38, count 0 2006.203.08:11:29.15#ibcon#read 6, iclass 38, count 0 2006.203.08:11:29.15#ibcon#end of sib2, iclass 38, count 0 2006.203.08:11:29.15#ibcon#*after write, iclass 38, count 0 2006.203.08:11:29.15#ibcon#*before return 0, iclass 38, count 0 2006.203.08:11:29.15#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.203.08:11:29.15#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.203.08:11:29.15#ibcon#about to clear, iclass 38 cls_cnt 0 2006.203.08:11:29.15#ibcon#cleared, iclass 38 cls_cnt 0 2006.203.08:11:29.15$vc4f8/valo=2,572.99 2006.203.08:11:29.15#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.203.08:11:29.15#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.203.08:11:29.15#ibcon#ireg 17 cls_cnt 0 2006.203.08:11:29.15#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.203.08:11:29.15#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.203.08:11:29.15#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.203.08:11:29.15#ibcon#enter wrdev, iclass 40, count 0 2006.203.08:11:29.15#ibcon#first serial, iclass 40, count 0 2006.203.08:11:29.15#ibcon#enter sib2, iclass 40, count 0 2006.203.08:11:29.15#ibcon#flushed, iclass 40, count 0 2006.203.08:11:29.16#ibcon#about to write, iclass 40, count 0 2006.203.08:11:29.16#ibcon#wrote, iclass 40, count 0 2006.203.08:11:29.16#ibcon#about to read 3, iclass 40, count 0 2006.203.08:11:29.17#ibcon#read 3, iclass 40, count 0 2006.203.08:11:29.17#ibcon#about to read 4, iclass 40, count 0 2006.203.08:11:29.17#ibcon#read 4, iclass 40, count 0 2006.203.08:11:29.17#ibcon#about to read 5, iclass 40, count 0 2006.203.08:11:29.17#ibcon#read 5, iclass 40, count 0 2006.203.08:11:29.17#ibcon#about to read 6, iclass 40, count 0 2006.203.08:11:29.17#ibcon#read 6, iclass 40, count 0 2006.203.08:11:29.17#ibcon#end of sib2, iclass 40, count 0 2006.203.08:11:29.18#ibcon#*mode == 0, iclass 40, count 0 2006.203.08:11:29.18#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.203.08:11:29.18#ibcon#[26=FRQ=02,572.99\r\n] 2006.203.08:11:29.18#ibcon#*before write, iclass 40, count 0 2006.203.08:11:29.18#ibcon#enter sib2, iclass 40, count 0 2006.203.08:11:29.18#ibcon#flushed, iclass 40, count 0 2006.203.08:11:29.18#ibcon#about to write, iclass 40, count 0 2006.203.08:11:29.18#ibcon#wrote, iclass 40, count 0 2006.203.08:11:29.18#ibcon#about to read 3, iclass 40, count 0 2006.203.08:11:29.21#ibcon#read 3, iclass 40, count 0 2006.203.08:11:29.21#ibcon#about to read 4, iclass 40, count 0 2006.203.08:11:29.21#ibcon#read 4, iclass 40, count 0 2006.203.08:11:29.21#ibcon#about to read 5, iclass 40, count 0 2006.203.08:11:29.21#ibcon#read 5, iclass 40, count 0 2006.203.08:11:29.21#ibcon#about to read 6, iclass 40, count 0 2006.203.08:11:29.21#ibcon#read 6, iclass 40, count 0 2006.203.08:11:29.21#ibcon#end of sib2, iclass 40, count 0 2006.203.08:11:29.21#ibcon#*after write, iclass 40, count 0 2006.203.08:11:29.21#ibcon#*before return 0, iclass 40, count 0 2006.203.08:11:29.21#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.203.08:11:29.21#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.203.08:11:29.21#ibcon#about to clear, iclass 40 cls_cnt 0 2006.203.08:11:29.21#ibcon#cleared, iclass 40 cls_cnt 0 2006.203.08:11:29.21$vc4f8/va=2,7 2006.203.08:11:29.21#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.203.08:11:29.21#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.203.08:11:29.21#ibcon#ireg 11 cls_cnt 2 2006.203.08:11:29.21#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.203.08:11:29.28#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.203.08:11:29.28#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.203.08:11:29.28#ibcon#enter wrdev, iclass 4, count 2 2006.203.08:11:29.28#ibcon#first serial, iclass 4, count 2 2006.203.08:11:29.28#ibcon#enter sib2, iclass 4, count 2 2006.203.08:11:29.28#ibcon#flushed, iclass 4, count 2 2006.203.08:11:29.28#ibcon#about to write, iclass 4, count 2 2006.203.08:11:29.28#ibcon#wrote, iclass 4, count 2 2006.203.08:11:29.28#ibcon#about to read 3, iclass 4, count 2 2006.203.08:11:29.30#ibcon#read 3, iclass 4, count 2 2006.203.08:11:29.30#ibcon#about to read 4, iclass 4, count 2 2006.203.08:11:29.30#ibcon#read 4, iclass 4, count 2 2006.203.08:11:29.30#ibcon#about to read 5, iclass 4, count 2 2006.203.08:11:29.30#ibcon#read 5, iclass 4, count 2 2006.203.08:11:29.30#ibcon#about to read 6, iclass 4, count 2 2006.203.08:11:29.30#ibcon#read 6, iclass 4, count 2 2006.203.08:11:29.30#ibcon#end of sib2, iclass 4, count 2 2006.203.08:11:29.30#ibcon#*mode == 0, iclass 4, count 2 2006.203.08:11:29.30#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.203.08:11:29.30#ibcon#[25=AT02-07\r\n] 2006.203.08:11:29.30#ibcon#*before write, iclass 4, count 2 2006.203.08:11:29.30#ibcon#enter sib2, iclass 4, count 2 2006.203.08:11:29.30#ibcon#flushed, iclass 4, count 2 2006.203.08:11:29.30#ibcon#about to write, iclass 4, count 2 2006.203.08:11:29.30#ibcon#wrote, iclass 4, count 2 2006.203.08:11:29.30#ibcon#about to read 3, iclass 4, count 2 2006.203.08:11:29.32#ibcon#read 3, iclass 4, count 2 2006.203.08:11:29.32#ibcon#about to read 4, iclass 4, count 2 2006.203.08:11:29.32#ibcon#read 4, iclass 4, count 2 2006.203.08:11:29.32#ibcon#about to read 5, iclass 4, count 2 2006.203.08:11:29.32#ibcon#read 5, iclass 4, count 2 2006.203.08:11:29.32#ibcon#about to read 6, iclass 4, count 2 2006.203.08:11:29.32#ibcon#read 6, iclass 4, count 2 2006.203.08:11:29.32#ibcon#end of sib2, iclass 4, count 2 2006.203.08:11:29.32#ibcon#*after write, iclass 4, count 2 2006.203.08:11:29.32#ibcon#*before return 0, iclass 4, count 2 2006.203.08:11:29.32#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.203.08:11:29.32#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.203.08:11:29.32#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.203.08:11:29.32#ibcon#ireg 7 cls_cnt 0 2006.203.08:11:29.32#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.203.08:11:29.44#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.203.08:11:29.44#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.203.08:11:29.44#ibcon#enter wrdev, iclass 4, count 0 2006.203.08:11:29.44#ibcon#first serial, iclass 4, count 0 2006.203.08:11:29.44#ibcon#enter sib2, iclass 4, count 0 2006.203.08:11:29.44#ibcon#flushed, iclass 4, count 0 2006.203.08:11:29.44#ibcon#about to write, iclass 4, count 0 2006.203.08:11:29.44#ibcon#wrote, iclass 4, count 0 2006.203.08:11:29.44#ibcon#about to read 3, iclass 4, count 0 2006.203.08:11:29.46#ibcon#read 3, iclass 4, count 0 2006.203.08:11:29.46#ibcon#about to read 4, iclass 4, count 0 2006.203.08:11:29.46#ibcon#read 4, iclass 4, count 0 2006.203.08:11:29.46#ibcon#about to read 5, iclass 4, count 0 2006.203.08:11:29.46#ibcon#read 5, iclass 4, count 0 2006.203.08:11:29.46#ibcon#about to read 6, iclass 4, count 0 2006.203.08:11:29.46#ibcon#read 6, iclass 4, count 0 2006.203.08:11:29.46#ibcon#end of sib2, iclass 4, count 0 2006.203.08:11:29.46#ibcon#*mode == 0, iclass 4, count 0 2006.203.08:11:29.46#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.203.08:11:29.46#ibcon#[25=USB\r\n] 2006.203.08:11:29.46#ibcon#*before write, iclass 4, count 0 2006.203.08:11:29.46#ibcon#enter sib2, iclass 4, count 0 2006.203.08:11:29.46#ibcon#flushed, iclass 4, count 0 2006.203.08:11:29.46#ibcon#about to write, iclass 4, count 0 2006.203.08:11:29.46#ibcon#wrote, iclass 4, count 0 2006.203.08:11:29.46#ibcon#about to read 3, iclass 4, count 0 2006.203.08:11:29.49#ibcon#read 3, iclass 4, count 0 2006.203.08:11:29.49#ibcon#about to read 4, iclass 4, count 0 2006.203.08:11:29.49#ibcon#read 4, iclass 4, count 0 2006.203.08:11:29.49#ibcon#about to read 5, iclass 4, count 0 2006.203.08:11:29.49#ibcon#read 5, iclass 4, count 0 2006.203.08:11:29.49#ibcon#about to read 6, iclass 4, count 0 2006.203.08:11:29.49#ibcon#read 6, iclass 4, count 0 2006.203.08:11:29.49#ibcon#end of sib2, iclass 4, count 0 2006.203.08:11:29.49#ibcon#*after write, iclass 4, count 0 2006.203.08:11:29.49#ibcon#*before return 0, iclass 4, count 0 2006.203.08:11:29.49#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.203.08:11:29.49#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.203.08:11:29.49#ibcon#about to clear, iclass 4 cls_cnt 0 2006.203.08:11:29.49#ibcon#cleared, iclass 4 cls_cnt 0 2006.203.08:11:29.49$vc4f8/valo=3,672.99 2006.203.08:11:29.49#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.203.08:11:29.49#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.203.08:11:29.49#ibcon#ireg 17 cls_cnt 0 2006.203.08:11:29.49#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.203.08:11:29.49#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.203.08:11:29.49#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.203.08:11:29.49#ibcon#enter wrdev, iclass 6, count 0 2006.203.08:11:29.49#ibcon#first serial, iclass 6, count 0 2006.203.08:11:29.49#ibcon#enter sib2, iclass 6, count 0 2006.203.08:11:29.49#ibcon#flushed, iclass 6, count 0 2006.203.08:11:29.49#ibcon#about to write, iclass 6, count 0 2006.203.08:11:29.50#ibcon#wrote, iclass 6, count 0 2006.203.08:11:29.50#ibcon#about to read 3, iclass 6, count 0 2006.203.08:11:29.51#ibcon#read 3, iclass 6, count 0 2006.203.08:11:29.51#ibcon#about to read 4, iclass 6, count 0 2006.203.08:11:29.51#ibcon#read 4, iclass 6, count 0 2006.203.08:11:29.51#ibcon#about to read 5, iclass 6, count 0 2006.203.08:11:29.51#ibcon#read 5, iclass 6, count 0 2006.203.08:11:29.51#ibcon#about to read 6, iclass 6, count 0 2006.203.08:11:29.51#ibcon#read 6, iclass 6, count 0 2006.203.08:11:29.51#ibcon#end of sib2, iclass 6, count 0 2006.203.08:11:29.51#ibcon#*mode == 0, iclass 6, count 0 2006.203.08:11:29.51#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.203.08:11:29.51#ibcon#[26=FRQ=03,672.99\r\n] 2006.203.08:11:29.51#ibcon#*before write, iclass 6, count 0 2006.203.08:11:29.51#ibcon#enter sib2, iclass 6, count 0 2006.203.08:11:29.51#ibcon#flushed, iclass 6, count 0 2006.203.08:11:29.51#ibcon#about to write, iclass 6, count 0 2006.203.08:11:29.51#ibcon#wrote, iclass 6, count 0 2006.203.08:11:29.51#ibcon#about to read 3, iclass 6, count 0 2006.203.08:11:29.55#ibcon#read 3, iclass 6, count 0 2006.203.08:11:29.55#ibcon#about to read 4, iclass 6, count 0 2006.203.08:11:29.55#ibcon#read 4, iclass 6, count 0 2006.203.08:11:29.55#ibcon#about to read 5, iclass 6, count 0 2006.203.08:11:29.55#ibcon#read 5, iclass 6, count 0 2006.203.08:11:29.55#ibcon#about to read 6, iclass 6, count 0 2006.203.08:11:29.55#ibcon#read 6, iclass 6, count 0 2006.203.08:11:29.55#ibcon#end of sib2, iclass 6, count 0 2006.203.08:11:29.55#ibcon#*after write, iclass 6, count 0 2006.203.08:11:29.55#ibcon#*before return 0, iclass 6, count 0 2006.203.08:11:29.55#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.203.08:11:29.55#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.203.08:11:29.55#ibcon#about to clear, iclass 6 cls_cnt 0 2006.203.08:11:29.55#ibcon#cleared, iclass 6 cls_cnt 0 2006.203.08:11:29.55$vc4f8/va=3,8 2006.203.08:11:29.55#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.203.08:11:29.55#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.203.08:11:29.55#ibcon#ireg 11 cls_cnt 2 2006.203.08:11:29.55#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.203.08:11:29.62#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.203.08:11:29.62#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.203.08:11:29.62#ibcon#enter wrdev, iclass 10, count 2 2006.203.08:11:29.62#ibcon#first serial, iclass 10, count 2 2006.203.08:11:29.62#ibcon#enter sib2, iclass 10, count 2 2006.203.08:11:29.62#ibcon#flushed, iclass 10, count 2 2006.203.08:11:29.62#ibcon#about to write, iclass 10, count 2 2006.203.08:11:29.62#ibcon#wrote, iclass 10, count 2 2006.203.08:11:29.62#ibcon#about to read 3, iclass 10, count 2 2006.203.08:11:29.64#ibcon#read 3, iclass 10, count 2 2006.203.08:11:29.64#ibcon#about to read 4, iclass 10, count 2 2006.203.08:11:29.64#ibcon#read 4, iclass 10, count 2 2006.203.08:11:29.64#ibcon#about to read 5, iclass 10, count 2 2006.203.08:11:29.64#ibcon#read 5, iclass 10, count 2 2006.203.08:11:29.64#ibcon#about to read 6, iclass 10, count 2 2006.203.08:11:29.64#ibcon#read 6, iclass 10, count 2 2006.203.08:11:29.64#ibcon#end of sib2, iclass 10, count 2 2006.203.08:11:29.64#ibcon#*mode == 0, iclass 10, count 2 2006.203.08:11:29.64#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.203.08:11:29.64#ibcon#[25=AT03-08\r\n] 2006.203.08:11:29.64#ibcon#*before write, iclass 10, count 2 2006.203.08:11:29.64#ibcon#enter sib2, iclass 10, count 2 2006.203.08:11:29.64#ibcon#flushed, iclass 10, count 2 2006.203.08:11:29.64#ibcon#about to write, iclass 10, count 2 2006.203.08:11:29.64#ibcon#wrote, iclass 10, count 2 2006.203.08:11:29.64#ibcon#about to read 3, iclass 10, count 2 2006.203.08:11:29.66#ibcon#read 3, iclass 10, count 2 2006.203.08:11:29.66#ibcon#about to read 4, iclass 10, count 2 2006.203.08:11:29.66#ibcon#read 4, iclass 10, count 2 2006.203.08:11:29.66#ibcon#about to read 5, iclass 10, count 2 2006.203.08:11:29.66#ibcon#read 5, iclass 10, count 2 2006.203.08:11:29.66#ibcon#about to read 6, iclass 10, count 2 2006.203.08:11:29.66#ibcon#read 6, iclass 10, count 2 2006.203.08:11:29.66#ibcon#end of sib2, iclass 10, count 2 2006.203.08:11:29.66#ibcon#*after write, iclass 10, count 2 2006.203.08:11:29.66#ibcon#*before return 0, iclass 10, count 2 2006.203.08:11:29.66#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.203.08:11:29.66#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.203.08:11:29.66#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.203.08:11:29.66#ibcon#ireg 7 cls_cnt 0 2006.203.08:11:29.66#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.203.08:11:29.78#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.203.08:11:29.78#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.203.08:11:29.78#ibcon#enter wrdev, iclass 10, count 0 2006.203.08:11:29.78#ibcon#first serial, iclass 10, count 0 2006.203.08:11:29.78#ibcon#enter sib2, iclass 10, count 0 2006.203.08:11:29.78#ibcon#flushed, iclass 10, count 0 2006.203.08:11:29.78#ibcon#about to write, iclass 10, count 0 2006.203.08:11:29.78#ibcon#wrote, iclass 10, count 0 2006.203.08:11:29.78#ibcon#about to read 3, iclass 10, count 0 2006.203.08:11:29.80#ibcon#read 3, iclass 10, count 0 2006.203.08:11:29.80#ibcon#about to read 4, iclass 10, count 0 2006.203.08:11:29.80#ibcon#read 4, iclass 10, count 0 2006.203.08:11:29.80#ibcon#about to read 5, iclass 10, count 0 2006.203.08:11:29.80#ibcon#read 5, iclass 10, count 0 2006.203.08:11:29.80#ibcon#about to read 6, iclass 10, count 0 2006.203.08:11:29.80#ibcon#read 6, iclass 10, count 0 2006.203.08:11:29.80#ibcon#end of sib2, iclass 10, count 0 2006.203.08:11:29.80#ibcon#*mode == 0, iclass 10, count 0 2006.203.08:11:29.80#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.203.08:11:29.80#ibcon#[25=USB\r\n] 2006.203.08:11:29.80#ibcon#*before write, iclass 10, count 0 2006.203.08:11:29.80#ibcon#enter sib2, iclass 10, count 0 2006.203.08:11:29.80#ibcon#flushed, iclass 10, count 0 2006.203.08:11:29.80#ibcon#about to write, iclass 10, count 0 2006.203.08:11:29.80#ibcon#wrote, iclass 10, count 0 2006.203.08:11:29.80#ibcon#about to read 3, iclass 10, count 0 2006.203.08:11:29.83#ibcon#read 3, iclass 10, count 0 2006.203.08:11:29.83#ibcon#about to read 4, iclass 10, count 0 2006.203.08:11:29.83#ibcon#read 4, iclass 10, count 0 2006.203.08:11:29.83#ibcon#about to read 5, iclass 10, count 0 2006.203.08:11:29.83#ibcon#read 5, iclass 10, count 0 2006.203.08:11:29.83#ibcon#about to read 6, iclass 10, count 0 2006.203.08:11:29.83#ibcon#read 6, iclass 10, count 0 2006.203.08:11:29.83#ibcon#end of sib2, iclass 10, count 0 2006.203.08:11:29.83#ibcon#*after write, iclass 10, count 0 2006.203.08:11:29.83#ibcon#*before return 0, iclass 10, count 0 2006.203.08:11:29.83#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.203.08:11:29.83#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.203.08:11:29.83#ibcon#about to clear, iclass 10 cls_cnt 0 2006.203.08:11:29.83#ibcon#cleared, iclass 10 cls_cnt 0 2006.203.08:11:29.83$vc4f8/valo=4,832.99 2006.203.08:11:29.83#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.203.08:11:29.83#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.203.08:11:29.83#ibcon#ireg 17 cls_cnt 0 2006.203.08:11:29.83#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.203.08:11:29.83#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.203.08:11:29.83#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.203.08:11:29.83#ibcon#enter wrdev, iclass 12, count 0 2006.203.08:11:29.83#ibcon#first serial, iclass 12, count 0 2006.203.08:11:29.83#ibcon#enter sib2, iclass 12, count 0 2006.203.08:11:29.83#ibcon#flushed, iclass 12, count 0 2006.203.08:11:29.83#ibcon#about to write, iclass 12, count 0 2006.203.08:11:29.84#ibcon#wrote, iclass 12, count 0 2006.203.08:11:29.84#ibcon#about to read 3, iclass 12, count 0 2006.203.08:11:29.85#ibcon#read 3, iclass 12, count 0 2006.203.08:11:29.85#ibcon#about to read 4, iclass 12, count 0 2006.203.08:11:29.85#ibcon#read 4, iclass 12, count 0 2006.203.08:11:29.85#ibcon#about to read 5, iclass 12, count 0 2006.203.08:11:29.85#ibcon#read 5, iclass 12, count 0 2006.203.08:11:29.85#ibcon#about to read 6, iclass 12, count 0 2006.203.08:11:29.85#ibcon#read 6, iclass 12, count 0 2006.203.08:11:29.85#ibcon#end of sib2, iclass 12, count 0 2006.203.08:11:29.85#ibcon#*mode == 0, iclass 12, count 0 2006.203.08:11:29.85#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.203.08:11:29.85#ibcon#[26=FRQ=04,832.99\r\n] 2006.203.08:11:29.85#ibcon#*before write, iclass 12, count 0 2006.203.08:11:29.85#ibcon#enter sib2, iclass 12, count 0 2006.203.08:11:29.85#ibcon#flushed, iclass 12, count 0 2006.203.08:11:29.85#ibcon#about to write, iclass 12, count 0 2006.203.08:11:29.85#ibcon#wrote, iclass 12, count 0 2006.203.08:11:29.85#ibcon#about to read 3, iclass 12, count 0 2006.203.08:11:29.89#ibcon#read 3, iclass 12, count 0 2006.203.08:11:29.89#ibcon#about to read 4, iclass 12, count 0 2006.203.08:11:29.89#ibcon#read 4, iclass 12, count 0 2006.203.08:11:29.89#ibcon#about to read 5, iclass 12, count 0 2006.203.08:11:29.89#ibcon#read 5, iclass 12, count 0 2006.203.08:11:29.89#ibcon#about to read 6, iclass 12, count 0 2006.203.08:11:29.89#ibcon#read 6, iclass 12, count 0 2006.203.08:11:29.89#ibcon#end of sib2, iclass 12, count 0 2006.203.08:11:29.89#ibcon#*after write, iclass 12, count 0 2006.203.08:11:29.89#ibcon#*before return 0, iclass 12, count 0 2006.203.08:11:29.89#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.203.08:11:29.89#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.203.08:11:29.89#ibcon#about to clear, iclass 12 cls_cnt 0 2006.203.08:11:29.89#ibcon#cleared, iclass 12 cls_cnt 0 2006.203.08:11:29.89$vc4f8/va=4,7 2006.203.08:11:29.89#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.203.08:11:29.89#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.203.08:11:29.89#ibcon#ireg 11 cls_cnt 2 2006.203.08:11:29.89#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.203.08:11:29.95#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.203.08:11:29.95#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.203.08:11:29.95#ibcon#enter wrdev, iclass 14, count 2 2006.203.08:11:29.95#ibcon#first serial, iclass 14, count 2 2006.203.08:11:29.95#ibcon#enter sib2, iclass 14, count 2 2006.203.08:11:29.95#ibcon#flushed, iclass 14, count 2 2006.203.08:11:29.95#ibcon#about to write, iclass 14, count 2 2006.203.08:11:29.95#ibcon#wrote, iclass 14, count 2 2006.203.08:11:29.95#ibcon#about to read 3, iclass 14, count 2 2006.203.08:11:29.97#ibcon#read 3, iclass 14, count 2 2006.203.08:11:29.97#ibcon#about to read 4, iclass 14, count 2 2006.203.08:11:29.97#ibcon#read 4, iclass 14, count 2 2006.203.08:11:29.97#ibcon#about to read 5, iclass 14, count 2 2006.203.08:11:29.97#ibcon#read 5, iclass 14, count 2 2006.203.08:11:29.97#ibcon#about to read 6, iclass 14, count 2 2006.203.08:11:29.97#ibcon#read 6, iclass 14, count 2 2006.203.08:11:29.97#ibcon#end of sib2, iclass 14, count 2 2006.203.08:11:29.97#ibcon#*mode == 0, iclass 14, count 2 2006.203.08:11:29.97#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.203.08:11:29.97#ibcon#[25=AT04-07\r\n] 2006.203.08:11:29.97#ibcon#*before write, iclass 14, count 2 2006.203.08:11:29.97#ibcon#enter sib2, iclass 14, count 2 2006.203.08:11:29.97#ibcon#flushed, iclass 14, count 2 2006.203.08:11:29.97#ibcon#about to write, iclass 14, count 2 2006.203.08:11:29.97#ibcon#wrote, iclass 14, count 2 2006.203.08:11:29.97#ibcon#about to read 3, iclass 14, count 2 2006.203.08:11:30.00#ibcon#read 3, iclass 14, count 2 2006.203.08:11:30.00#ibcon#about to read 4, iclass 14, count 2 2006.203.08:11:30.00#ibcon#read 4, iclass 14, count 2 2006.203.08:11:30.00#ibcon#about to read 5, iclass 14, count 2 2006.203.08:11:30.00#ibcon#read 5, iclass 14, count 2 2006.203.08:11:30.00#ibcon#about to read 6, iclass 14, count 2 2006.203.08:11:30.00#ibcon#read 6, iclass 14, count 2 2006.203.08:11:30.00#ibcon#end of sib2, iclass 14, count 2 2006.203.08:11:30.00#ibcon#*after write, iclass 14, count 2 2006.203.08:11:30.00#ibcon#*before return 0, iclass 14, count 2 2006.203.08:11:30.00#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.203.08:11:30.00#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.203.08:11:30.00#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.203.08:11:30.00#ibcon#ireg 7 cls_cnt 0 2006.203.08:11:30.00#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.203.08:11:30.12#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.203.08:11:30.12#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.203.08:11:30.12#ibcon#enter wrdev, iclass 14, count 0 2006.203.08:11:30.12#ibcon#first serial, iclass 14, count 0 2006.203.08:11:30.12#ibcon#enter sib2, iclass 14, count 0 2006.203.08:11:30.12#ibcon#flushed, iclass 14, count 0 2006.203.08:11:30.12#ibcon#about to write, iclass 14, count 0 2006.203.08:11:30.12#ibcon#wrote, iclass 14, count 0 2006.203.08:11:30.12#ibcon#about to read 3, iclass 14, count 0 2006.203.08:11:30.14#ibcon#read 3, iclass 14, count 0 2006.203.08:11:30.14#ibcon#about to read 4, iclass 14, count 0 2006.203.08:11:30.15#ibcon#read 4, iclass 14, count 0 2006.203.08:11:30.15#ibcon#about to read 5, iclass 14, count 0 2006.203.08:11:30.15#ibcon#read 5, iclass 14, count 0 2006.203.08:11:30.15#ibcon#about to read 6, iclass 14, count 0 2006.203.08:11:30.15#ibcon#read 6, iclass 14, count 0 2006.203.08:11:30.15#ibcon#end of sib2, iclass 14, count 0 2006.203.08:11:30.15#ibcon#*mode == 0, iclass 14, count 0 2006.203.08:11:30.15#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.203.08:11:30.15#ibcon#[25=USB\r\n] 2006.203.08:11:30.15#ibcon#*before write, iclass 14, count 0 2006.203.08:11:30.15#ibcon#enter sib2, iclass 14, count 0 2006.203.08:11:30.15#ibcon#flushed, iclass 14, count 0 2006.203.08:11:30.15#ibcon#about to write, iclass 14, count 0 2006.203.08:11:30.15#ibcon#wrote, iclass 14, count 0 2006.203.08:11:30.15#ibcon#about to read 3, iclass 14, count 0 2006.203.08:11:30.17#ibcon#read 3, iclass 14, count 0 2006.203.08:11:30.17#ibcon#about to read 4, iclass 14, count 0 2006.203.08:11:30.17#ibcon#read 4, iclass 14, count 0 2006.203.08:11:30.17#ibcon#about to read 5, iclass 14, count 0 2006.203.08:11:30.17#ibcon#read 5, iclass 14, count 0 2006.203.08:11:30.17#ibcon#about to read 6, iclass 14, count 0 2006.203.08:11:30.17#ibcon#read 6, iclass 14, count 0 2006.203.08:11:30.17#ibcon#end of sib2, iclass 14, count 0 2006.203.08:11:30.17#ibcon#*after write, iclass 14, count 0 2006.203.08:11:30.17#ibcon#*before return 0, iclass 14, count 0 2006.203.08:11:30.17#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.203.08:11:30.17#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.203.08:11:30.17#ibcon#about to clear, iclass 14 cls_cnt 0 2006.203.08:11:30.17#ibcon#cleared, iclass 14 cls_cnt 0 2006.203.08:11:30.17$vc4f8/valo=5,652.99 2006.203.08:11:30.17#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.203.08:11:30.17#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.203.08:11:30.17#ibcon#ireg 17 cls_cnt 0 2006.203.08:11:30.17#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.203.08:11:30.17#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.203.08:11:30.17#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.203.08:11:30.17#ibcon#enter wrdev, iclass 16, count 0 2006.203.08:11:30.17#ibcon#first serial, iclass 16, count 0 2006.203.08:11:30.17#ibcon#enter sib2, iclass 16, count 0 2006.203.08:11:30.17#ibcon#flushed, iclass 16, count 0 2006.203.08:11:30.18#ibcon#about to write, iclass 16, count 0 2006.203.08:11:30.18#ibcon#wrote, iclass 16, count 0 2006.203.08:11:30.18#ibcon#about to read 3, iclass 16, count 0 2006.203.08:11:30.19#ibcon#read 3, iclass 16, count 0 2006.203.08:11:30.19#ibcon#about to read 4, iclass 16, count 0 2006.203.08:11:30.19#ibcon#read 4, iclass 16, count 0 2006.203.08:11:30.19#ibcon#about to read 5, iclass 16, count 0 2006.203.08:11:30.19#ibcon#read 5, iclass 16, count 0 2006.203.08:11:30.19#ibcon#about to read 6, iclass 16, count 0 2006.203.08:11:30.19#ibcon#read 6, iclass 16, count 0 2006.203.08:11:30.19#ibcon#end of sib2, iclass 16, count 0 2006.203.08:11:30.19#ibcon#*mode == 0, iclass 16, count 0 2006.203.08:11:30.19#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.203.08:11:30.19#ibcon#[26=FRQ=05,652.99\r\n] 2006.203.08:11:30.19#ibcon#*before write, iclass 16, count 0 2006.203.08:11:30.19#ibcon#enter sib2, iclass 16, count 0 2006.203.08:11:30.19#ibcon#flushed, iclass 16, count 0 2006.203.08:11:30.19#ibcon#about to write, iclass 16, count 0 2006.203.08:11:30.19#ibcon#wrote, iclass 16, count 0 2006.203.08:11:30.19#ibcon#about to read 3, iclass 16, count 0 2006.203.08:11:30.23#ibcon#read 3, iclass 16, count 0 2006.203.08:11:30.23#ibcon#about to read 4, iclass 16, count 0 2006.203.08:11:30.23#ibcon#read 4, iclass 16, count 0 2006.203.08:11:30.23#ibcon#about to read 5, iclass 16, count 0 2006.203.08:11:30.23#ibcon#read 5, iclass 16, count 0 2006.203.08:11:30.23#ibcon#about to read 6, iclass 16, count 0 2006.203.08:11:30.23#ibcon#read 6, iclass 16, count 0 2006.203.08:11:30.23#ibcon#end of sib2, iclass 16, count 0 2006.203.08:11:30.23#ibcon#*after write, iclass 16, count 0 2006.203.08:11:30.23#ibcon#*before return 0, iclass 16, count 0 2006.203.08:11:30.23#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.203.08:11:30.23#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.203.08:11:30.23#ibcon#about to clear, iclass 16 cls_cnt 0 2006.203.08:11:30.23#ibcon#cleared, iclass 16 cls_cnt 0 2006.203.08:11:30.23$vc4f8/va=5,7 2006.203.08:11:30.23#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.203.08:11:30.23#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.203.08:11:30.23#ibcon#ireg 11 cls_cnt 2 2006.203.08:11:30.23#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.203.08:11:30.29#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.203.08:11:30.29#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.203.08:11:30.29#ibcon#enter wrdev, iclass 18, count 2 2006.203.08:11:30.29#ibcon#first serial, iclass 18, count 2 2006.203.08:11:30.29#ibcon#enter sib2, iclass 18, count 2 2006.203.08:11:30.29#ibcon#flushed, iclass 18, count 2 2006.203.08:11:30.29#ibcon#about to write, iclass 18, count 2 2006.203.08:11:30.29#ibcon#wrote, iclass 18, count 2 2006.203.08:11:30.29#ibcon#about to read 3, iclass 18, count 2 2006.203.08:11:30.31#ibcon#read 3, iclass 18, count 2 2006.203.08:11:30.31#ibcon#about to read 4, iclass 18, count 2 2006.203.08:11:30.31#ibcon#read 4, iclass 18, count 2 2006.203.08:11:30.31#ibcon#about to read 5, iclass 18, count 2 2006.203.08:11:30.31#ibcon#read 5, iclass 18, count 2 2006.203.08:11:30.31#ibcon#about to read 6, iclass 18, count 2 2006.203.08:11:30.31#ibcon#read 6, iclass 18, count 2 2006.203.08:11:30.31#ibcon#end of sib2, iclass 18, count 2 2006.203.08:11:30.31#ibcon#*mode == 0, iclass 18, count 2 2006.203.08:11:30.31#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.203.08:11:30.31#ibcon#[25=AT05-07\r\n] 2006.203.08:11:30.31#ibcon#*before write, iclass 18, count 2 2006.203.08:11:30.31#ibcon#enter sib2, iclass 18, count 2 2006.203.08:11:30.31#ibcon#flushed, iclass 18, count 2 2006.203.08:11:30.31#ibcon#about to write, iclass 18, count 2 2006.203.08:11:30.31#ibcon#wrote, iclass 18, count 2 2006.203.08:11:30.31#ibcon#about to read 3, iclass 18, count 2 2006.203.08:11:30.34#ibcon#read 3, iclass 18, count 2 2006.203.08:11:30.34#ibcon#about to read 4, iclass 18, count 2 2006.203.08:11:30.34#ibcon#read 4, iclass 18, count 2 2006.203.08:11:30.34#ibcon#about to read 5, iclass 18, count 2 2006.203.08:11:30.34#ibcon#read 5, iclass 18, count 2 2006.203.08:11:30.34#ibcon#about to read 6, iclass 18, count 2 2006.203.08:11:30.34#ibcon#read 6, iclass 18, count 2 2006.203.08:11:30.34#ibcon#end of sib2, iclass 18, count 2 2006.203.08:11:30.34#ibcon#*after write, iclass 18, count 2 2006.203.08:11:30.34#ibcon#*before return 0, iclass 18, count 2 2006.203.08:11:30.34#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.203.08:11:30.34#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.203.08:11:30.34#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.203.08:11:30.34#ibcon#ireg 7 cls_cnt 0 2006.203.08:11:30.34#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.203.08:11:30.46#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.203.08:11:30.46#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.203.08:11:30.46#ibcon#enter wrdev, iclass 18, count 0 2006.203.08:11:30.46#ibcon#first serial, iclass 18, count 0 2006.203.08:11:30.46#ibcon#enter sib2, iclass 18, count 0 2006.203.08:11:30.46#ibcon#flushed, iclass 18, count 0 2006.203.08:11:30.46#ibcon#about to write, iclass 18, count 0 2006.203.08:11:30.46#ibcon#wrote, iclass 18, count 0 2006.203.08:11:30.46#ibcon#about to read 3, iclass 18, count 0 2006.203.08:11:30.48#ibcon#read 3, iclass 18, count 0 2006.203.08:11:30.48#ibcon#about to read 4, iclass 18, count 0 2006.203.08:11:30.48#ibcon#read 4, iclass 18, count 0 2006.203.08:11:30.48#ibcon#about to read 5, iclass 18, count 0 2006.203.08:11:30.48#ibcon#read 5, iclass 18, count 0 2006.203.08:11:30.48#ibcon#about to read 6, iclass 18, count 0 2006.203.08:11:30.48#ibcon#read 6, iclass 18, count 0 2006.203.08:11:30.48#ibcon#end of sib2, iclass 18, count 0 2006.203.08:11:30.48#ibcon#*mode == 0, iclass 18, count 0 2006.203.08:11:30.48#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.203.08:11:30.48#ibcon#[25=USB\r\n] 2006.203.08:11:30.48#ibcon#*before write, iclass 18, count 0 2006.203.08:11:30.48#ibcon#enter sib2, iclass 18, count 0 2006.203.08:11:30.48#ibcon#flushed, iclass 18, count 0 2006.203.08:11:30.48#ibcon#about to write, iclass 18, count 0 2006.203.08:11:30.48#ibcon#wrote, iclass 18, count 0 2006.203.08:11:30.48#ibcon#about to read 3, iclass 18, count 0 2006.203.08:11:30.51#ibcon#read 3, iclass 18, count 0 2006.203.08:11:30.51#ibcon#about to read 4, iclass 18, count 0 2006.203.08:11:30.51#ibcon#read 4, iclass 18, count 0 2006.203.08:11:30.51#ibcon#about to read 5, iclass 18, count 0 2006.203.08:11:30.51#ibcon#read 5, iclass 18, count 0 2006.203.08:11:30.51#ibcon#about to read 6, iclass 18, count 0 2006.203.08:11:30.51#ibcon#read 6, iclass 18, count 0 2006.203.08:11:30.51#ibcon#end of sib2, iclass 18, count 0 2006.203.08:11:30.51#ibcon#*after write, iclass 18, count 0 2006.203.08:11:30.51#ibcon#*before return 0, iclass 18, count 0 2006.203.08:11:30.51#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.203.08:11:30.51#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.203.08:11:30.51#ibcon#about to clear, iclass 18 cls_cnt 0 2006.203.08:11:30.51#ibcon#cleared, iclass 18 cls_cnt 0 2006.203.08:11:30.51$vc4f8/valo=6,772.99 2006.203.08:11:30.51#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.203.08:11:30.51#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.203.08:11:30.51#ibcon#ireg 17 cls_cnt 0 2006.203.08:11:30.51#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.203.08:11:30.51#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.203.08:11:30.51#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.203.08:11:30.51#ibcon#enter wrdev, iclass 20, count 0 2006.203.08:11:30.51#ibcon#first serial, iclass 20, count 0 2006.203.08:11:30.51#ibcon#enter sib2, iclass 20, count 0 2006.203.08:11:30.51#ibcon#flushed, iclass 20, count 0 2006.203.08:11:30.51#ibcon#about to write, iclass 20, count 0 2006.203.08:11:30.52#ibcon#wrote, iclass 20, count 0 2006.203.08:11:30.52#ibcon#about to read 3, iclass 20, count 0 2006.203.08:11:30.53#ibcon#read 3, iclass 20, count 0 2006.203.08:11:30.53#ibcon#about to read 4, iclass 20, count 0 2006.203.08:11:30.53#ibcon#read 4, iclass 20, count 0 2006.203.08:11:30.53#ibcon#about to read 5, iclass 20, count 0 2006.203.08:11:30.53#ibcon#read 5, iclass 20, count 0 2006.203.08:11:30.53#ibcon#about to read 6, iclass 20, count 0 2006.203.08:11:30.53#ibcon#read 6, iclass 20, count 0 2006.203.08:11:30.53#ibcon#end of sib2, iclass 20, count 0 2006.203.08:11:30.53#ibcon#*mode == 0, iclass 20, count 0 2006.203.08:11:30.53#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.203.08:11:30.53#ibcon#[26=FRQ=06,772.99\r\n] 2006.203.08:11:30.53#ibcon#*before write, iclass 20, count 0 2006.203.08:11:30.53#ibcon#enter sib2, iclass 20, count 0 2006.203.08:11:30.53#ibcon#flushed, iclass 20, count 0 2006.203.08:11:30.53#ibcon#about to write, iclass 20, count 0 2006.203.08:11:30.53#ibcon#wrote, iclass 20, count 0 2006.203.08:11:30.53#ibcon#about to read 3, iclass 20, count 0 2006.203.08:11:30.57#ibcon#read 3, iclass 20, count 0 2006.203.08:11:30.57#ibcon#about to read 4, iclass 20, count 0 2006.203.08:11:30.57#ibcon#read 4, iclass 20, count 0 2006.203.08:11:30.57#ibcon#about to read 5, iclass 20, count 0 2006.203.08:11:30.57#ibcon#read 5, iclass 20, count 0 2006.203.08:11:30.57#ibcon#about to read 6, iclass 20, count 0 2006.203.08:11:30.57#ibcon#read 6, iclass 20, count 0 2006.203.08:11:30.57#ibcon#end of sib2, iclass 20, count 0 2006.203.08:11:30.57#ibcon#*after write, iclass 20, count 0 2006.203.08:11:30.57#ibcon#*before return 0, iclass 20, count 0 2006.203.08:11:30.57#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.203.08:11:30.57#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.203.08:11:30.57#ibcon#about to clear, iclass 20 cls_cnt 0 2006.203.08:11:30.57#ibcon#cleared, iclass 20 cls_cnt 0 2006.203.08:11:30.57$vc4f8/va=6,6 2006.203.08:11:30.57#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.203.08:11:30.57#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.203.08:11:30.57#ibcon#ireg 11 cls_cnt 2 2006.203.08:11:30.57#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.203.08:11:30.64#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.203.08:11:30.64#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.203.08:11:30.64#ibcon#enter wrdev, iclass 22, count 2 2006.203.08:11:30.64#ibcon#first serial, iclass 22, count 2 2006.203.08:11:30.64#ibcon#enter sib2, iclass 22, count 2 2006.203.08:11:30.64#ibcon#flushed, iclass 22, count 2 2006.203.08:11:30.64#ibcon#about to write, iclass 22, count 2 2006.203.08:11:30.64#ibcon#wrote, iclass 22, count 2 2006.203.08:11:30.64#ibcon#about to read 3, iclass 22, count 2 2006.203.08:11:30.65#ibcon#read 3, iclass 22, count 2 2006.203.08:11:30.65#ibcon#about to read 4, iclass 22, count 2 2006.203.08:11:30.65#ibcon#read 4, iclass 22, count 2 2006.203.08:11:30.65#ibcon#about to read 5, iclass 22, count 2 2006.203.08:11:30.65#ibcon#read 5, iclass 22, count 2 2006.203.08:11:30.65#ibcon#about to read 6, iclass 22, count 2 2006.203.08:11:30.65#ibcon#read 6, iclass 22, count 2 2006.203.08:11:30.65#ibcon#end of sib2, iclass 22, count 2 2006.203.08:11:30.65#ibcon#*mode == 0, iclass 22, count 2 2006.203.08:11:30.65#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.203.08:11:30.65#ibcon#[25=AT06-06\r\n] 2006.203.08:11:30.65#ibcon#*before write, iclass 22, count 2 2006.203.08:11:30.65#ibcon#enter sib2, iclass 22, count 2 2006.203.08:11:30.65#ibcon#flushed, iclass 22, count 2 2006.203.08:11:30.65#ibcon#about to write, iclass 22, count 2 2006.203.08:11:30.65#ibcon#wrote, iclass 22, count 2 2006.203.08:11:30.65#ibcon#about to read 3, iclass 22, count 2 2006.203.08:11:30.68#ibcon#read 3, iclass 22, count 2 2006.203.08:11:30.68#ibcon#about to read 4, iclass 22, count 2 2006.203.08:11:30.68#ibcon#read 4, iclass 22, count 2 2006.203.08:11:30.68#ibcon#about to read 5, iclass 22, count 2 2006.203.08:11:30.68#ibcon#read 5, iclass 22, count 2 2006.203.08:11:30.68#ibcon#about to read 6, iclass 22, count 2 2006.203.08:11:30.68#ibcon#read 6, iclass 22, count 2 2006.203.08:11:30.68#ibcon#end of sib2, iclass 22, count 2 2006.203.08:11:30.68#ibcon#*after write, iclass 22, count 2 2006.203.08:11:30.68#ibcon#*before return 0, iclass 22, count 2 2006.203.08:11:30.68#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.203.08:11:30.68#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.203.08:11:30.68#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.203.08:11:30.68#ibcon#ireg 7 cls_cnt 0 2006.203.08:11:30.68#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.203.08:11:30.80#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.203.08:11:30.80#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.203.08:11:30.80#ibcon#enter wrdev, iclass 22, count 0 2006.203.08:11:30.80#ibcon#first serial, iclass 22, count 0 2006.203.08:11:30.80#ibcon#enter sib2, iclass 22, count 0 2006.203.08:11:30.80#ibcon#flushed, iclass 22, count 0 2006.203.08:11:30.80#ibcon#about to write, iclass 22, count 0 2006.203.08:11:30.80#ibcon#wrote, iclass 22, count 0 2006.203.08:11:30.80#ibcon#about to read 3, iclass 22, count 0 2006.203.08:11:30.82#ibcon#read 3, iclass 22, count 0 2006.203.08:11:30.82#ibcon#about to read 4, iclass 22, count 0 2006.203.08:11:30.82#ibcon#read 4, iclass 22, count 0 2006.203.08:11:30.82#ibcon#about to read 5, iclass 22, count 0 2006.203.08:11:30.82#ibcon#read 5, iclass 22, count 0 2006.203.08:11:30.82#ibcon#about to read 6, iclass 22, count 0 2006.203.08:11:30.82#ibcon#read 6, iclass 22, count 0 2006.203.08:11:30.82#ibcon#end of sib2, iclass 22, count 0 2006.203.08:11:30.82#ibcon#*mode == 0, iclass 22, count 0 2006.203.08:11:30.82#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.203.08:11:30.82#ibcon#[25=USB\r\n] 2006.203.08:11:30.82#ibcon#*before write, iclass 22, count 0 2006.203.08:11:30.82#ibcon#enter sib2, iclass 22, count 0 2006.203.08:11:30.82#ibcon#flushed, iclass 22, count 0 2006.203.08:11:30.82#ibcon#about to write, iclass 22, count 0 2006.203.08:11:30.82#ibcon#wrote, iclass 22, count 0 2006.203.08:11:30.82#ibcon#about to read 3, iclass 22, count 0 2006.203.08:11:30.85#ibcon#read 3, iclass 22, count 0 2006.203.08:11:30.85#ibcon#about to read 4, iclass 22, count 0 2006.203.08:11:30.85#ibcon#read 4, iclass 22, count 0 2006.203.08:11:30.85#ibcon#about to read 5, iclass 22, count 0 2006.203.08:11:30.85#ibcon#read 5, iclass 22, count 0 2006.203.08:11:30.85#ibcon#about to read 6, iclass 22, count 0 2006.203.08:11:30.85#ibcon#read 6, iclass 22, count 0 2006.203.08:11:30.85#ibcon#end of sib2, iclass 22, count 0 2006.203.08:11:30.85#ibcon#*after write, iclass 22, count 0 2006.203.08:11:30.85#ibcon#*before return 0, iclass 22, count 0 2006.203.08:11:30.85#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.203.08:11:30.85#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.203.08:11:30.85#ibcon#about to clear, iclass 22 cls_cnt 0 2006.203.08:11:30.85#ibcon#cleared, iclass 22 cls_cnt 0 2006.203.08:11:30.85$vc4f8/valo=7,832.99 2006.203.08:11:30.85#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.203.08:11:30.85#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.203.08:11:30.85#ibcon#ireg 17 cls_cnt 0 2006.203.08:11:30.85#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.203.08:11:30.85#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.203.08:11:30.85#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.203.08:11:30.85#ibcon#enter wrdev, iclass 24, count 0 2006.203.08:11:30.85#ibcon#first serial, iclass 24, count 0 2006.203.08:11:30.85#ibcon#enter sib2, iclass 24, count 0 2006.203.08:11:30.85#ibcon#flushed, iclass 24, count 0 2006.203.08:11:30.85#ibcon#about to write, iclass 24, count 0 2006.203.08:11:30.86#ibcon#wrote, iclass 24, count 0 2006.203.08:11:30.86#ibcon#about to read 3, iclass 24, count 0 2006.203.08:11:30.87#ibcon#read 3, iclass 24, count 0 2006.203.08:11:30.87#ibcon#about to read 4, iclass 24, count 0 2006.203.08:11:30.87#ibcon#read 4, iclass 24, count 0 2006.203.08:11:30.87#ibcon#about to read 5, iclass 24, count 0 2006.203.08:11:30.87#ibcon#read 5, iclass 24, count 0 2006.203.08:11:30.87#ibcon#about to read 6, iclass 24, count 0 2006.203.08:11:30.87#ibcon#read 6, iclass 24, count 0 2006.203.08:11:30.87#ibcon#end of sib2, iclass 24, count 0 2006.203.08:11:30.87#ibcon#*mode == 0, iclass 24, count 0 2006.203.08:11:30.87#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.203.08:11:30.87#ibcon#[26=FRQ=07,832.99\r\n] 2006.203.08:11:30.87#ibcon#*before write, iclass 24, count 0 2006.203.08:11:30.87#ibcon#enter sib2, iclass 24, count 0 2006.203.08:11:30.87#ibcon#flushed, iclass 24, count 0 2006.203.08:11:30.87#ibcon#about to write, iclass 24, count 0 2006.203.08:11:30.87#ibcon#wrote, iclass 24, count 0 2006.203.08:11:30.87#ibcon#about to read 3, iclass 24, count 0 2006.203.08:11:30.91#ibcon#read 3, iclass 24, count 0 2006.203.08:11:30.91#ibcon#about to read 4, iclass 24, count 0 2006.203.08:11:30.91#ibcon#read 4, iclass 24, count 0 2006.203.08:11:30.91#ibcon#about to read 5, iclass 24, count 0 2006.203.08:11:30.91#ibcon#read 5, iclass 24, count 0 2006.203.08:11:30.91#ibcon#about to read 6, iclass 24, count 0 2006.203.08:11:30.91#ibcon#read 6, iclass 24, count 0 2006.203.08:11:30.91#ibcon#end of sib2, iclass 24, count 0 2006.203.08:11:30.91#ibcon#*after write, iclass 24, count 0 2006.203.08:11:30.91#ibcon#*before return 0, iclass 24, count 0 2006.203.08:11:30.91#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.203.08:11:30.91#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.203.08:11:30.91#ibcon#about to clear, iclass 24 cls_cnt 0 2006.203.08:11:30.91#ibcon#cleared, iclass 24 cls_cnt 0 2006.203.08:11:30.91$vc4f8/va=7,7 2006.203.08:11:30.91#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.203.08:11:30.91#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.203.08:11:30.91#ibcon#ireg 11 cls_cnt 2 2006.203.08:11:30.91#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.203.08:11:30.97#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.203.08:11:30.97#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.203.08:11:30.97#ibcon#enter wrdev, iclass 26, count 2 2006.203.08:11:30.97#ibcon#first serial, iclass 26, count 2 2006.203.08:11:30.97#ibcon#enter sib2, iclass 26, count 2 2006.203.08:11:30.97#ibcon#flushed, iclass 26, count 2 2006.203.08:11:30.97#ibcon#about to write, iclass 26, count 2 2006.203.08:11:30.97#ibcon#wrote, iclass 26, count 2 2006.203.08:11:30.97#ibcon#about to read 3, iclass 26, count 2 2006.203.08:11:30.99#ibcon#read 3, iclass 26, count 2 2006.203.08:11:30.99#ibcon#about to read 4, iclass 26, count 2 2006.203.08:11:30.99#ibcon#read 4, iclass 26, count 2 2006.203.08:11:30.99#ibcon#about to read 5, iclass 26, count 2 2006.203.08:11:30.99#ibcon#read 5, iclass 26, count 2 2006.203.08:11:30.99#ibcon#about to read 6, iclass 26, count 2 2006.203.08:11:30.99#ibcon#read 6, iclass 26, count 2 2006.203.08:11:30.99#ibcon#end of sib2, iclass 26, count 2 2006.203.08:11:30.99#ibcon#*mode == 0, iclass 26, count 2 2006.203.08:11:30.99#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.203.08:11:30.99#ibcon#[25=AT07-07\r\n] 2006.203.08:11:30.99#ibcon#*before write, iclass 26, count 2 2006.203.08:11:30.99#ibcon#enter sib2, iclass 26, count 2 2006.203.08:11:30.99#ibcon#flushed, iclass 26, count 2 2006.203.08:11:30.99#ibcon#about to write, iclass 26, count 2 2006.203.08:11:30.99#ibcon#wrote, iclass 26, count 2 2006.203.08:11:30.99#ibcon#about to read 3, iclass 26, count 2 2006.203.08:11:31.02#ibcon#read 3, iclass 26, count 2 2006.203.08:11:31.02#ibcon#about to read 4, iclass 26, count 2 2006.203.08:11:31.02#ibcon#read 4, iclass 26, count 2 2006.203.08:11:31.02#ibcon#about to read 5, iclass 26, count 2 2006.203.08:11:31.02#ibcon#read 5, iclass 26, count 2 2006.203.08:11:31.02#ibcon#about to read 6, iclass 26, count 2 2006.203.08:11:31.02#ibcon#read 6, iclass 26, count 2 2006.203.08:11:31.02#ibcon#end of sib2, iclass 26, count 2 2006.203.08:11:31.02#ibcon#*after write, iclass 26, count 2 2006.203.08:11:31.02#ibcon#*before return 0, iclass 26, count 2 2006.203.08:11:31.02#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.203.08:11:31.02#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.203.08:11:31.02#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.203.08:11:31.02#ibcon#ireg 7 cls_cnt 0 2006.203.08:11:31.02#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.203.08:11:31.14#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.203.08:11:31.14#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.203.08:11:31.14#ibcon#enter wrdev, iclass 26, count 0 2006.203.08:11:31.14#ibcon#first serial, iclass 26, count 0 2006.203.08:11:31.14#ibcon#enter sib2, iclass 26, count 0 2006.203.08:11:31.14#ibcon#flushed, iclass 26, count 0 2006.203.08:11:31.14#ibcon#about to write, iclass 26, count 0 2006.203.08:11:31.14#ibcon#wrote, iclass 26, count 0 2006.203.08:11:31.15#ibcon#about to read 3, iclass 26, count 0 2006.203.08:11:31.16#ibcon#read 3, iclass 26, count 0 2006.203.08:11:31.16#ibcon#about to read 4, iclass 26, count 0 2006.203.08:11:31.16#ibcon#read 4, iclass 26, count 0 2006.203.08:11:31.16#ibcon#about to read 5, iclass 26, count 0 2006.203.08:11:31.16#ibcon#read 5, iclass 26, count 0 2006.203.08:11:31.16#ibcon#about to read 6, iclass 26, count 0 2006.203.08:11:31.16#ibcon#read 6, iclass 26, count 0 2006.203.08:11:31.16#ibcon#end of sib2, iclass 26, count 0 2006.203.08:11:31.16#ibcon#*mode == 0, iclass 26, count 0 2006.203.08:11:31.16#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.203.08:11:31.16#ibcon#[25=USB\r\n] 2006.203.08:11:31.16#ibcon#*before write, iclass 26, count 0 2006.203.08:11:31.16#ibcon#enter sib2, iclass 26, count 0 2006.203.08:11:31.16#ibcon#flushed, iclass 26, count 0 2006.203.08:11:31.16#ibcon#about to write, iclass 26, count 0 2006.203.08:11:31.16#ibcon#wrote, iclass 26, count 0 2006.203.08:11:31.16#ibcon#about to read 3, iclass 26, count 0 2006.203.08:11:31.19#ibcon#read 3, iclass 26, count 0 2006.203.08:11:31.19#ibcon#about to read 4, iclass 26, count 0 2006.203.08:11:31.19#ibcon#read 4, iclass 26, count 0 2006.203.08:11:31.19#ibcon#about to read 5, iclass 26, count 0 2006.203.08:11:31.19#ibcon#read 5, iclass 26, count 0 2006.203.08:11:31.19#ibcon#about to read 6, iclass 26, count 0 2006.203.08:11:31.19#ibcon#read 6, iclass 26, count 0 2006.203.08:11:31.19#ibcon#end of sib2, iclass 26, count 0 2006.203.08:11:31.19#ibcon#*after write, iclass 26, count 0 2006.203.08:11:31.19#ibcon#*before return 0, iclass 26, count 0 2006.203.08:11:31.19#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.203.08:11:31.19#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.203.08:11:31.19#ibcon#about to clear, iclass 26 cls_cnt 0 2006.203.08:11:31.19#ibcon#cleared, iclass 26 cls_cnt 0 2006.203.08:11:31.19$vc4f8/valo=8,852.99 2006.203.08:11:31.19#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.203.08:11:31.19#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.203.08:11:31.19#ibcon#ireg 17 cls_cnt 0 2006.203.08:11:31.19#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.203.08:11:31.19#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.203.08:11:31.19#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.203.08:11:31.19#ibcon#enter wrdev, iclass 28, count 0 2006.203.08:11:31.19#ibcon#first serial, iclass 28, count 0 2006.203.08:11:31.19#ibcon#enter sib2, iclass 28, count 0 2006.203.08:11:31.19#ibcon#flushed, iclass 28, count 0 2006.203.08:11:31.19#ibcon#about to write, iclass 28, count 0 2006.203.08:11:31.20#ibcon#wrote, iclass 28, count 0 2006.203.08:11:31.20#ibcon#about to read 3, iclass 28, count 0 2006.203.08:11:31.22#ibcon#read 3, iclass 28, count 0 2006.203.08:11:31.22#ibcon#about to read 4, iclass 28, count 0 2006.203.08:11:31.22#ibcon#read 4, iclass 28, count 0 2006.203.08:11:31.22#ibcon#about to read 5, iclass 28, count 0 2006.203.08:11:31.22#ibcon#read 5, iclass 28, count 0 2006.203.08:11:31.22#ibcon#about to read 6, iclass 28, count 0 2006.203.08:11:31.22#ibcon#read 6, iclass 28, count 0 2006.203.08:11:31.22#ibcon#end of sib2, iclass 28, count 0 2006.203.08:11:31.22#ibcon#*mode == 0, iclass 28, count 0 2006.203.08:11:31.22#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.203.08:11:31.22#ibcon#[26=FRQ=08,852.99\r\n] 2006.203.08:11:31.22#ibcon#*before write, iclass 28, count 0 2006.203.08:11:31.22#ibcon#enter sib2, iclass 28, count 0 2006.203.08:11:31.22#ibcon#flushed, iclass 28, count 0 2006.203.08:11:31.22#ibcon#about to write, iclass 28, count 0 2006.203.08:11:31.22#ibcon#wrote, iclass 28, count 0 2006.203.08:11:31.22#ibcon#about to read 3, iclass 28, count 0 2006.203.08:11:31.26#ibcon#read 3, iclass 28, count 0 2006.203.08:11:31.26#ibcon#about to read 4, iclass 28, count 0 2006.203.08:11:31.26#ibcon#read 4, iclass 28, count 0 2006.203.08:11:31.26#ibcon#about to read 5, iclass 28, count 0 2006.203.08:11:31.26#ibcon#read 5, iclass 28, count 0 2006.203.08:11:31.26#ibcon#about to read 6, iclass 28, count 0 2006.203.08:11:31.26#ibcon#read 6, iclass 28, count 0 2006.203.08:11:31.26#ibcon#end of sib2, iclass 28, count 0 2006.203.08:11:31.26#ibcon#*after write, iclass 28, count 0 2006.203.08:11:31.26#ibcon#*before return 0, iclass 28, count 0 2006.203.08:11:31.26#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.203.08:11:31.26#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.203.08:11:31.26#ibcon#about to clear, iclass 28 cls_cnt 0 2006.203.08:11:31.26#ibcon#cleared, iclass 28 cls_cnt 0 2006.203.08:11:31.26$vc4f8/va=8,6 2006.203.08:11:31.26#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.203.08:11:31.26#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.203.08:11:31.26#ibcon#ireg 11 cls_cnt 2 2006.203.08:11:31.26#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.203.08:11:31.31#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.203.08:11:31.31#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.203.08:11:31.31#ibcon#enter wrdev, iclass 30, count 2 2006.203.08:11:31.31#ibcon#first serial, iclass 30, count 2 2006.203.08:11:31.31#ibcon#enter sib2, iclass 30, count 2 2006.203.08:11:31.31#ibcon#flushed, iclass 30, count 2 2006.203.08:11:31.31#ibcon#about to write, iclass 30, count 2 2006.203.08:11:31.31#ibcon#wrote, iclass 30, count 2 2006.203.08:11:31.31#ibcon#about to read 3, iclass 30, count 2 2006.203.08:11:31.33#ibcon#read 3, iclass 30, count 2 2006.203.08:11:31.33#ibcon#about to read 4, iclass 30, count 2 2006.203.08:11:31.33#ibcon#read 4, iclass 30, count 2 2006.203.08:11:31.33#ibcon#about to read 5, iclass 30, count 2 2006.203.08:11:31.33#ibcon#read 5, iclass 30, count 2 2006.203.08:11:31.33#ibcon#about to read 6, iclass 30, count 2 2006.203.08:11:31.33#ibcon#read 6, iclass 30, count 2 2006.203.08:11:31.33#ibcon#end of sib2, iclass 30, count 2 2006.203.08:11:31.33#ibcon#*mode == 0, iclass 30, count 2 2006.203.08:11:31.33#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.203.08:11:31.33#ibcon#[25=AT08-06\r\n] 2006.203.08:11:31.33#ibcon#*before write, iclass 30, count 2 2006.203.08:11:31.33#ibcon#enter sib2, iclass 30, count 2 2006.203.08:11:31.33#ibcon#flushed, iclass 30, count 2 2006.203.08:11:31.33#ibcon#about to write, iclass 30, count 2 2006.203.08:11:31.33#ibcon#wrote, iclass 30, count 2 2006.203.08:11:31.33#ibcon#about to read 3, iclass 30, count 2 2006.203.08:11:31.36#ibcon#read 3, iclass 30, count 2 2006.203.08:11:31.36#ibcon#about to read 4, iclass 30, count 2 2006.203.08:11:31.36#ibcon#read 4, iclass 30, count 2 2006.203.08:11:31.36#ibcon#about to read 5, iclass 30, count 2 2006.203.08:11:31.36#ibcon#read 5, iclass 30, count 2 2006.203.08:11:31.36#ibcon#about to read 6, iclass 30, count 2 2006.203.08:11:31.36#ibcon#read 6, iclass 30, count 2 2006.203.08:11:31.36#ibcon#end of sib2, iclass 30, count 2 2006.203.08:11:31.36#ibcon#*after write, iclass 30, count 2 2006.203.08:11:31.36#ibcon#*before return 0, iclass 30, count 2 2006.203.08:11:31.36#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.203.08:11:31.36#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.203.08:11:31.36#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.203.08:11:31.36#ibcon#ireg 7 cls_cnt 0 2006.203.08:11:31.36#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.203.08:11:31.48#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.203.08:11:31.48#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.203.08:11:31.48#ibcon#enter wrdev, iclass 30, count 0 2006.203.08:11:31.48#ibcon#first serial, iclass 30, count 0 2006.203.08:11:31.48#ibcon#enter sib2, iclass 30, count 0 2006.203.08:11:31.48#ibcon#flushed, iclass 30, count 0 2006.203.08:11:31.48#ibcon#about to write, iclass 30, count 0 2006.203.08:11:31.48#ibcon#wrote, iclass 30, count 0 2006.203.08:11:31.48#ibcon#about to read 3, iclass 30, count 0 2006.203.08:11:31.50#ibcon#read 3, iclass 30, count 0 2006.203.08:11:31.50#ibcon#about to read 4, iclass 30, count 0 2006.203.08:11:31.50#ibcon#read 4, iclass 30, count 0 2006.203.08:11:31.50#ibcon#about to read 5, iclass 30, count 0 2006.203.08:11:31.50#ibcon#read 5, iclass 30, count 0 2006.203.08:11:31.50#ibcon#about to read 6, iclass 30, count 0 2006.203.08:11:31.50#ibcon#read 6, iclass 30, count 0 2006.203.08:11:31.50#ibcon#end of sib2, iclass 30, count 0 2006.203.08:11:31.50#ibcon#*mode == 0, iclass 30, count 0 2006.203.08:11:31.50#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.203.08:11:31.50#ibcon#[25=USB\r\n] 2006.203.08:11:31.50#ibcon#*before write, iclass 30, count 0 2006.203.08:11:31.50#ibcon#enter sib2, iclass 30, count 0 2006.203.08:11:31.50#ibcon#flushed, iclass 30, count 0 2006.203.08:11:31.50#ibcon#about to write, iclass 30, count 0 2006.203.08:11:31.50#ibcon#wrote, iclass 30, count 0 2006.203.08:11:31.50#ibcon#about to read 3, iclass 30, count 0 2006.203.08:11:31.53#ibcon#read 3, iclass 30, count 0 2006.203.08:11:31.53#ibcon#about to read 4, iclass 30, count 0 2006.203.08:11:31.53#ibcon#read 4, iclass 30, count 0 2006.203.08:11:31.53#ibcon#about to read 5, iclass 30, count 0 2006.203.08:11:31.53#ibcon#read 5, iclass 30, count 0 2006.203.08:11:31.53#ibcon#about to read 6, iclass 30, count 0 2006.203.08:11:31.53#ibcon#read 6, iclass 30, count 0 2006.203.08:11:31.53#ibcon#end of sib2, iclass 30, count 0 2006.203.08:11:31.53#ibcon#*after write, iclass 30, count 0 2006.203.08:11:31.53#ibcon#*before return 0, iclass 30, count 0 2006.203.08:11:31.53#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.203.08:11:31.53#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.203.08:11:31.53#ibcon#about to clear, iclass 30 cls_cnt 0 2006.203.08:11:31.53#ibcon#cleared, iclass 30 cls_cnt 0 2006.203.08:11:31.53$vc4f8/vblo=1,632.99 2006.203.08:11:31.53#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.203.08:11:31.53#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.203.08:11:31.53#ibcon#ireg 17 cls_cnt 0 2006.203.08:11:31.53#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.203.08:11:31.53#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.203.08:11:31.53#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.203.08:11:31.53#ibcon#enter wrdev, iclass 32, count 0 2006.203.08:11:31.53#ibcon#first serial, iclass 32, count 0 2006.203.08:11:31.53#ibcon#enter sib2, iclass 32, count 0 2006.203.08:11:31.53#ibcon#flushed, iclass 32, count 0 2006.203.08:11:31.53#ibcon#about to write, iclass 32, count 0 2006.203.08:11:31.54#ibcon#wrote, iclass 32, count 0 2006.203.08:11:31.54#ibcon#about to read 3, iclass 32, count 0 2006.203.08:11:31.55#ibcon#read 3, iclass 32, count 0 2006.203.08:11:31.55#ibcon#about to read 4, iclass 32, count 0 2006.203.08:11:31.55#ibcon#read 4, iclass 32, count 0 2006.203.08:11:31.55#ibcon#about to read 5, iclass 32, count 0 2006.203.08:11:31.55#ibcon#read 5, iclass 32, count 0 2006.203.08:11:31.55#ibcon#about to read 6, iclass 32, count 0 2006.203.08:11:31.55#ibcon#read 6, iclass 32, count 0 2006.203.08:11:31.55#ibcon#end of sib2, iclass 32, count 0 2006.203.08:11:31.55#ibcon#*mode == 0, iclass 32, count 0 2006.203.08:11:31.55#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.203.08:11:31.55#ibcon#[28=FRQ=01,632.99\r\n] 2006.203.08:11:31.55#ibcon#*before write, iclass 32, count 0 2006.203.08:11:31.55#ibcon#enter sib2, iclass 32, count 0 2006.203.08:11:31.55#ibcon#flushed, iclass 32, count 0 2006.203.08:11:31.55#ibcon#about to write, iclass 32, count 0 2006.203.08:11:31.55#ibcon#wrote, iclass 32, count 0 2006.203.08:11:31.55#ibcon#about to read 3, iclass 32, count 0 2006.203.08:11:31.59#ibcon#read 3, iclass 32, count 0 2006.203.08:11:31.59#ibcon#about to read 4, iclass 32, count 0 2006.203.08:11:31.59#ibcon#read 4, iclass 32, count 0 2006.203.08:11:31.59#ibcon#about to read 5, iclass 32, count 0 2006.203.08:11:31.59#ibcon#read 5, iclass 32, count 0 2006.203.08:11:31.59#ibcon#about to read 6, iclass 32, count 0 2006.203.08:11:31.59#ibcon#read 6, iclass 32, count 0 2006.203.08:11:31.59#ibcon#end of sib2, iclass 32, count 0 2006.203.08:11:31.59#ibcon#*after write, iclass 32, count 0 2006.203.08:11:31.59#ibcon#*before return 0, iclass 32, count 0 2006.203.08:11:31.59#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.203.08:11:31.59#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.203.08:11:31.59#ibcon#about to clear, iclass 32 cls_cnt 0 2006.203.08:11:31.59#ibcon#cleared, iclass 32 cls_cnt 0 2006.203.08:11:31.59$vc4f8/vb=1,4 2006.203.08:11:31.59#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.203.08:11:31.59#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.203.08:11:31.59#ibcon#ireg 11 cls_cnt 2 2006.203.08:11:31.59#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.203.08:11:31.59#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.203.08:11:31.59#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.203.08:11:31.59#ibcon#enter wrdev, iclass 34, count 2 2006.203.08:11:31.59#ibcon#first serial, iclass 34, count 2 2006.203.08:11:31.59#ibcon#enter sib2, iclass 34, count 2 2006.203.08:11:31.59#ibcon#flushed, iclass 34, count 2 2006.203.08:11:31.60#ibcon#about to write, iclass 34, count 2 2006.203.08:11:31.60#ibcon#wrote, iclass 34, count 2 2006.203.08:11:31.60#ibcon#about to read 3, iclass 34, count 2 2006.203.08:11:31.61#ibcon#read 3, iclass 34, count 2 2006.203.08:11:31.61#ibcon#about to read 4, iclass 34, count 2 2006.203.08:11:31.61#ibcon#read 4, iclass 34, count 2 2006.203.08:11:31.61#ibcon#about to read 5, iclass 34, count 2 2006.203.08:11:31.61#ibcon#read 5, iclass 34, count 2 2006.203.08:11:31.61#ibcon#about to read 6, iclass 34, count 2 2006.203.08:11:31.61#ibcon#read 6, iclass 34, count 2 2006.203.08:11:31.61#ibcon#end of sib2, iclass 34, count 2 2006.203.08:11:31.61#ibcon#*mode == 0, iclass 34, count 2 2006.203.08:11:31.61#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.203.08:11:31.61#ibcon#[27=AT01-04\r\n] 2006.203.08:11:31.61#ibcon#*before write, iclass 34, count 2 2006.203.08:11:31.61#ibcon#enter sib2, iclass 34, count 2 2006.203.08:11:31.61#ibcon#flushed, iclass 34, count 2 2006.203.08:11:31.61#ibcon#about to write, iclass 34, count 2 2006.203.08:11:31.61#ibcon#wrote, iclass 34, count 2 2006.203.08:11:31.61#ibcon#about to read 3, iclass 34, count 2 2006.203.08:11:31.64#ibcon#read 3, iclass 34, count 2 2006.203.08:11:31.64#ibcon#about to read 4, iclass 34, count 2 2006.203.08:11:31.64#ibcon#read 4, iclass 34, count 2 2006.203.08:11:31.64#ibcon#about to read 5, iclass 34, count 2 2006.203.08:11:31.64#ibcon#read 5, iclass 34, count 2 2006.203.08:11:31.64#ibcon#about to read 6, iclass 34, count 2 2006.203.08:11:31.64#ibcon#read 6, iclass 34, count 2 2006.203.08:11:31.64#ibcon#end of sib2, iclass 34, count 2 2006.203.08:11:31.64#ibcon#*after write, iclass 34, count 2 2006.203.08:11:31.64#ibcon#*before return 0, iclass 34, count 2 2006.203.08:11:31.64#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.203.08:11:31.64#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.203.08:11:31.64#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.203.08:11:31.64#ibcon#ireg 7 cls_cnt 0 2006.203.08:11:31.64#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.203.08:11:31.76#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.203.08:11:31.76#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.203.08:11:31.76#ibcon#enter wrdev, iclass 34, count 0 2006.203.08:11:31.76#ibcon#first serial, iclass 34, count 0 2006.203.08:11:31.76#ibcon#enter sib2, iclass 34, count 0 2006.203.08:11:31.76#ibcon#flushed, iclass 34, count 0 2006.203.08:11:31.76#ibcon#about to write, iclass 34, count 0 2006.203.08:11:31.76#ibcon#wrote, iclass 34, count 0 2006.203.08:11:31.76#ibcon#about to read 3, iclass 34, count 0 2006.203.08:11:31.78#ibcon#read 3, iclass 34, count 0 2006.203.08:11:31.78#ibcon#about to read 4, iclass 34, count 0 2006.203.08:11:31.78#ibcon#read 4, iclass 34, count 0 2006.203.08:11:31.78#ibcon#about to read 5, iclass 34, count 0 2006.203.08:11:31.78#ibcon#read 5, iclass 34, count 0 2006.203.08:11:31.78#ibcon#about to read 6, iclass 34, count 0 2006.203.08:11:31.78#ibcon#read 6, iclass 34, count 0 2006.203.08:11:31.78#ibcon#end of sib2, iclass 34, count 0 2006.203.08:11:31.78#ibcon#*mode == 0, iclass 34, count 0 2006.203.08:11:31.78#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.203.08:11:31.78#ibcon#[27=USB\r\n] 2006.203.08:11:31.78#ibcon#*before write, iclass 34, count 0 2006.203.08:11:31.78#ibcon#enter sib2, iclass 34, count 0 2006.203.08:11:31.78#ibcon#flushed, iclass 34, count 0 2006.203.08:11:31.78#ibcon#about to write, iclass 34, count 0 2006.203.08:11:31.78#ibcon#wrote, iclass 34, count 0 2006.203.08:11:31.78#ibcon#about to read 3, iclass 34, count 0 2006.203.08:11:31.81#ibcon#read 3, iclass 34, count 0 2006.203.08:11:31.81#ibcon#about to read 4, iclass 34, count 0 2006.203.08:11:31.81#ibcon#read 4, iclass 34, count 0 2006.203.08:11:31.81#ibcon#about to read 5, iclass 34, count 0 2006.203.08:11:31.81#ibcon#read 5, iclass 34, count 0 2006.203.08:11:31.81#ibcon#about to read 6, iclass 34, count 0 2006.203.08:11:31.81#ibcon#read 6, iclass 34, count 0 2006.203.08:11:31.81#ibcon#end of sib2, iclass 34, count 0 2006.203.08:11:31.81#ibcon#*after write, iclass 34, count 0 2006.203.08:11:31.81#ibcon#*before return 0, iclass 34, count 0 2006.203.08:11:31.81#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.203.08:11:31.81#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.203.08:11:31.81#ibcon#about to clear, iclass 34 cls_cnt 0 2006.203.08:11:31.81#ibcon#cleared, iclass 34 cls_cnt 0 2006.203.08:11:31.81$vc4f8/vblo=2,640.99 2006.203.08:11:31.81#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.203.08:11:31.81#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.203.08:11:31.81#ibcon#ireg 17 cls_cnt 0 2006.203.08:11:31.81#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.203.08:11:31.81#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.203.08:11:31.81#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.203.08:11:31.81#ibcon#enter wrdev, iclass 36, count 0 2006.203.08:11:31.81#ibcon#first serial, iclass 36, count 0 2006.203.08:11:31.81#ibcon#enter sib2, iclass 36, count 0 2006.203.08:11:31.81#ibcon#flushed, iclass 36, count 0 2006.203.08:11:31.81#ibcon#about to write, iclass 36, count 0 2006.203.08:11:31.82#ibcon#wrote, iclass 36, count 0 2006.203.08:11:31.82#ibcon#about to read 3, iclass 36, count 0 2006.203.08:11:31.83#ibcon#read 3, iclass 36, count 0 2006.203.08:11:31.83#ibcon#about to read 4, iclass 36, count 0 2006.203.08:11:31.83#ibcon#read 4, iclass 36, count 0 2006.203.08:11:31.83#ibcon#about to read 5, iclass 36, count 0 2006.203.08:11:31.83#ibcon#read 5, iclass 36, count 0 2006.203.08:11:31.83#ibcon#about to read 6, iclass 36, count 0 2006.203.08:11:31.83#ibcon#read 6, iclass 36, count 0 2006.203.08:11:31.83#ibcon#end of sib2, iclass 36, count 0 2006.203.08:11:31.83#ibcon#*mode == 0, iclass 36, count 0 2006.203.08:11:31.83#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.203.08:11:31.83#ibcon#[28=FRQ=02,640.99\r\n] 2006.203.08:11:31.83#ibcon#*before write, iclass 36, count 0 2006.203.08:11:31.83#ibcon#enter sib2, iclass 36, count 0 2006.203.08:11:31.83#ibcon#flushed, iclass 36, count 0 2006.203.08:11:31.83#ibcon#about to write, iclass 36, count 0 2006.203.08:11:31.83#ibcon#wrote, iclass 36, count 0 2006.203.08:11:31.83#ibcon#about to read 3, iclass 36, count 0 2006.203.08:11:31.87#ibcon#read 3, iclass 36, count 0 2006.203.08:11:31.87#ibcon#about to read 4, iclass 36, count 0 2006.203.08:11:31.87#ibcon#read 4, iclass 36, count 0 2006.203.08:11:31.87#ibcon#about to read 5, iclass 36, count 0 2006.203.08:11:31.87#ibcon#read 5, iclass 36, count 0 2006.203.08:11:31.87#ibcon#about to read 6, iclass 36, count 0 2006.203.08:11:31.87#ibcon#read 6, iclass 36, count 0 2006.203.08:11:31.87#ibcon#end of sib2, iclass 36, count 0 2006.203.08:11:31.87#ibcon#*after write, iclass 36, count 0 2006.203.08:11:31.87#ibcon#*before return 0, iclass 36, count 0 2006.203.08:11:31.87#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.203.08:11:31.87#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.203.08:11:31.87#ibcon#about to clear, iclass 36 cls_cnt 0 2006.203.08:11:31.87#ibcon#cleared, iclass 36 cls_cnt 0 2006.203.08:11:31.87$vc4f8/vb=2,4 2006.203.08:11:31.87#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.203.08:11:31.87#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.203.08:11:31.87#ibcon#ireg 11 cls_cnt 2 2006.203.08:11:31.87#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.203.08:11:31.93#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.203.08:11:31.93#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.203.08:11:31.93#ibcon#enter wrdev, iclass 38, count 2 2006.203.08:11:31.93#ibcon#first serial, iclass 38, count 2 2006.203.08:11:31.93#ibcon#enter sib2, iclass 38, count 2 2006.203.08:11:31.93#ibcon#flushed, iclass 38, count 2 2006.203.08:11:31.93#ibcon#about to write, iclass 38, count 2 2006.203.08:11:31.93#ibcon#wrote, iclass 38, count 2 2006.203.08:11:31.93#ibcon#about to read 3, iclass 38, count 2 2006.203.08:11:31.95#ibcon#read 3, iclass 38, count 2 2006.203.08:11:31.95#ibcon#about to read 4, iclass 38, count 2 2006.203.08:11:31.95#ibcon#read 4, iclass 38, count 2 2006.203.08:11:31.95#ibcon#about to read 5, iclass 38, count 2 2006.203.08:11:31.95#ibcon#read 5, iclass 38, count 2 2006.203.08:11:31.95#ibcon#about to read 6, iclass 38, count 2 2006.203.08:11:31.95#ibcon#read 6, iclass 38, count 2 2006.203.08:11:31.95#ibcon#end of sib2, iclass 38, count 2 2006.203.08:11:31.95#ibcon#*mode == 0, iclass 38, count 2 2006.203.08:11:31.95#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.203.08:11:31.95#ibcon#[27=AT02-04\r\n] 2006.203.08:11:31.95#ibcon#*before write, iclass 38, count 2 2006.203.08:11:31.95#ibcon#enter sib2, iclass 38, count 2 2006.203.08:11:31.95#ibcon#flushed, iclass 38, count 2 2006.203.08:11:31.95#ibcon#about to write, iclass 38, count 2 2006.203.08:11:31.95#ibcon#wrote, iclass 38, count 2 2006.203.08:11:31.95#ibcon#about to read 3, iclass 38, count 2 2006.203.08:11:31.98#ibcon#read 3, iclass 38, count 2 2006.203.08:11:31.98#ibcon#about to read 4, iclass 38, count 2 2006.203.08:11:31.98#ibcon#read 4, iclass 38, count 2 2006.203.08:11:31.98#ibcon#about to read 5, iclass 38, count 2 2006.203.08:11:31.98#ibcon#read 5, iclass 38, count 2 2006.203.08:11:31.98#ibcon#about to read 6, iclass 38, count 2 2006.203.08:11:31.98#ibcon#read 6, iclass 38, count 2 2006.203.08:11:31.98#ibcon#end of sib2, iclass 38, count 2 2006.203.08:11:31.98#ibcon#*after write, iclass 38, count 2 2006.203.08:11:31.98#ibcon#*before return 0, iclass 38, count 2 2006.203.08:11:31.98#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.203.08:11:31.98#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.203.08:11:31.98#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.203.08:11:31.98#ibcon#ireg 7 cls_cnt 0 2006.203.08:11:31.98#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.203.08:11:32.10#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.203.08:11:32.10#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.203.08:11:32.10#ibcon#enter wrdev, iclass 38, count 0 2006.203.08:11:32.10#ibcon#first serial, iclass 38, count 0 2006.203.08:11:32.10#ibcon#enter sib2, iclass 38, count 0 2006.203.08:11:32.10#ibcon#flushed, iclass 38, count 0 2006.203.08:11:32.10#ibcon#about to write, iclass 38, count 0 2006.203.08:11:32.10#ibcon#wrote, iclass 38, count 0 2006.203.08:11:32.10#ibcon#about to read 3, iclass 38, count 0 2006.203.08:11:32.12#ibcon#read 3, iclass 38, count 0 2006.203.08:11:32.12#ibcon#about to read 4, iclass 38, count 0 2006.203.08:11:32.12#ibcon#read 4, iclass 38, count 0 2006.203.08:11:32.12#ibcon#about to read 5, iclass 38, count 0 2006.203.08:11:32.12#ibcon#read 5, iclass 38, count 0 2006.203.08:11:32.12#ibcon#about to read 6, iclass 38, count 0 2006.203.08:11:32.12#ibcon#read 6, iclass 38, count 0 2006.203.08:11:32.12#ibcon#end of sib2, iclass 38, count 0 2006.203.08:11:32.12#ibcon#*mode == 0, iclass 38, count 0 2006.203.08:11:32.12#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.203.08:11:32.12#ibcon#[27=USB\r\n] 2006.203.08:11:32.12#ibcon#*before write, iclass 38, count 0 2006.203.08:11:32.12#ibcon#enter sib2, iclass 38, count 0 2006.203.08:11:32.12#ibcon#flushed, iclass 38, count 0 2006.203.08:11:32.12#ibcon#about to write, iclass 38, count 0 2006.203.08:11:32.12#ibcon#wrote, iclass 38, count 0 2006.203.08:11:32.12#ibcon#about to read 3, iclass 38, count 0 2006.203.08:11:32.15#ibcon#read 3, iclass 38, count 0 2006.203.08:11:32.15#ibcon#about to read 4, iclass 38, count 0 2006.203.08:11:32.15#ibcon#read 4, iclass 38, count 0 2006.203.08:11:32.15#ibcon#about to read 5, iclass 38, count 0 2006.203.08:11:32.15#ibcon#read 5, iclass 38, count 0 2006.203.08:11:32.15#ibcon#about to read 6, iclass 38, count 0 2006.203.08:11:32.15#ibcon#read 6, iclass 38, count 0 2006.203.08:11:32.15#ibcon#end of sib2, iclass 38, count 0 2006.203.08:11:32.15#ibcon#*after write, iclass 38, count 0 2006.203.08:11:32.15#ibcon#*before return 0, iclass 38, count 0 2006.203.08:11:32.15#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.203.08:11:32.15#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.203.08:11:32.15#ibcon#about to clear, iclass 38 cls_cnt 0 2006.203.08:11:32.15#ibcon#cleared, iclass 38 cls_cnt 0 2006.203.08:11:32.15$vc4f8/vblo=3,656.99 2006.203.08:11:32.15#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.203.08:11:32.15#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.203.08:11:32.15#ibcon#ireg 17 cls_cnt 0 2006.203.08:11:32.15#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.203.08:11:32.15#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.203.08:11:32.15#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.203.08:11:32.15#ibcon#enter wrdev, iclass 40, count 0 2006.203.08:11:32.15#ibcon#first serial, iclass 40, count 0 2006.203.08:11:32.15#ibcon#enter sib2, iclass 40, count 0 2006.203.08:11:32.15#ibcon#flushed, iclass 40, count 0 2006.203.08:11:32.15#ibcon#about to write, iclass 40, count 0 2006.203.08:11:32.16#ibcon#wrote, iclass 40, count 0 2006.203.08:11:32.16#ibcon#about to read 3, iclass 40, count 0 2006.203.08:11:32.17#ibcon#read 3, iclass 40, count 0 2006.203.08:11:32.17#ibcon#about to read 4, iclass 40, count 0 2006.203.08:11:32.17#ibcon#read 4, iclass 40, count 0 2006.203.08:11:32.17#ibcon#about to read 5, iclass 40, count 0 2006.203.08:11:32.17#ibcon#read 5, iclass 40, count 0 2006.203.08:11:32.17#ibcon#about to read 6, iclass 40, count 0 2006.203.08:11:32.17#ibcon#read 6, iclass 40, count 0 2006.203.08:11:32.17#ibcon#end of sib2, iclass 40, count 0 2006.203.08:11:32.17#ibcon#*mode == 0, iclass 40, count 0 2006.203.08:11:32.17#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.203.08:11:32.17#ibcon#[28=FRQ=03,656.99\r\n] 2006.203.08:11:32.17#ibcon#*before write, iclass 40, count 0 2006.203.08:11:32.17#ibcon#enter sib2, iclass 40, count 0 2006.203.08:11:32.17#ibcon#flushed, iclass 40, count 0 2006.203.08:11:32.17#ibcon#about to write, iclass 40, count 0 2006.203.08:11:32.17#ibcon#wrote, iclass 40, count 0 2006.203.08:11:32.17#ibcon#about to read 3, iclass 40, count 0 2006.203.08:11:32.21#ibcon#read 3, iclass 40, count 0 2006.203.08:11:32.21#ibcon#about to read 4, iclass 40, count 0 2006.203.08:11:32.21#ibcon#read 4, iclass 40, count 0 2006.203.08:11:32.21#ibcon#about to read 5, iclass 40, count 0 2006.203.08:11:32.21#ibcon#read 5, iclass 40, count 0 2006.203.08:11:32.21#ibcon#about to read 6, iclass 40, count 0 2006.203.08:11:32.21#ibcon#read 6, iclass 40, count 0 2006.203.08:11:32.21#ibcon#end of sib2, iclass 40, count 0 2006.203.08:11:32.21#ibcon#*after write, iclass 40, count 0 2006.203.08:11:32.21#ibcon#*before return 0, iclass 40, count 0 2006.203.08:11:32.21#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.203.08:11:32.21#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.203.08:11:32.21#ibcon#about to clear, iclass 40 cls_cnt 0 2006.203.08:11:32.21#ibcon#cleared, iclass 40 cls_cnt 0 2006.203.08:11:32.21$vc4f8/vb=3,4 2006.203.08:11:32.21#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.203.08:11:32.21#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.203.08:11:32.21#ibcon#ireg 11 cls_cnt 2 2006.203.08:11:32.21#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.203.08:11:32.27#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.203.08:11:32.27#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.203.08:11:32.27#ibcon#enter wrdev, iclass 4, count 2 2006.203.08:11:32.27#ibcon#first serial, iclass 4, count 2 2006.203.08:11:32.27#ibcon#enter sib2, iclass 4, count 2 2006.203.08:11:32.27#ibcon#flushed, iclass 4, count 2 2006.203.08:11:32.27#ibcon#about to write, iclass 4, count 2 2006.203.08:11:32.27#ibcon#wrote, iclass 4, count 2 2006.203.08:11:32.27#ibcon#about to read 3, iclass 4, count 2 2006.203.08:11:32.29#ibcon#read 3, iclass 4, count 2 2006.203.08:11:32.29#ibcon#about to read 4, iclass 4, count 2 2006.203.08:11:32.29#ibcon#read 4, iclass 4, count 2 2006.203.08:11:32.29#ibcon#about to read 5, iclass 4, count 2 2006.203.08:11:32.29#ibcon#read 5, iclass 4, count 2 2006.203.08:11:32.29#ibcon#about to read 6, iclass 4, count 2 2006.203.08:11:32.29#ibcon#read 6, iclass 4, count 2 2006.203.08:11:32.29#ibcon#end of sib2, iclass 4, count 2 2006.203.08:11:32.29#ibcon#*mode == 0, iclass 4, count 2 2006.203.08:11:32.29#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.203.08:11:32.29#ibcon#[27=AT03-04\r\n] 2006.203.08:11:32.29#ibcon#*before write, iclass 4, count 2 2006.203.08:11:32.29#ibcon#enter sib2, iclass 4, count 2 2006.203.08:11:32.29#ibcon#flushed, iclass 4, count 2 2006.203.08:11:32.29#ibcon#about to write, iclass 4, count 2 2006.203.08:11:32.29#ibcon#wrote, iclass 4, count 2 2006.203.08:11:32.29#ibcon#about to read 3, iclass 4, count 2 2006.203.08:11:32.32#ibcon#read 3, iclass 4, count 2 2006.203.08:11:32.32#ibcon#about to read 4, iclass 4, count 2 2006.203.08:11:32.32#ibcon#read 4, iclass 4, count 2 2006.203.08:11:32.32#ibcon#about to read 5, iclass 4, count 2 2006.203.08:11:32.32#ibcon#read 5, iclass 4, count 2 2006.203.08:11:32.32#ibcon#about to read 6, iclass 4, count 2 2006.203.08:11:32.32#ibcon#read 6, iclass 4, count 2 2006.203.08:11:32.32#ibcon#end of sib2, iclass 4, count 2 2006.203.08:11:32.32#ibcon#*after write, iclass 4, count 2 2006.203.08:11:32.32#ibcon#*before return 0, iclass 4, count 2 2006.203.08:11:32.32#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.203.08:11:32.32#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.203.08:11:32.32#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.203.08:11:32.32#ibcon#ireg 7 cls_cnt 0 2006.203.08:11:32.32#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.203.08:11:32.44#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.203.08:11:32.44#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.203.08:11:32.44#ibcon#enter wrdev, iclass 4, count 0 2006.203.08:11:32.44#ibcon#first serial, iclass 4, count 0 2006.203.08:11:32.44#ibcon#enter sib2, iclass 4, count 0 2006.203.08:11:32.44#ibcon#flushed, iclass 4, count 0 2006.203.08:11:32.44#ibcon#about to write, iclass 4, count 0 2006.203.08:11:32.44#ibcon#wrote, iclass 4, count 0 2006.203.08:11:32.44#ibcon#about to read 3, iclass 4, count 0 2006.203.08:11:32.46#ibcon#read 3, iclass 4, count 0 2006.203.08:11:32.46#ibcon#about to read 4, iclass 4, count 0 2006.203.08:11:32.46#ibcon#read 4, iclass 4, count 0 2006.203.08:11:32.46#ibcon#about to read 5, iclass 4, count 0 2006.203.08:11:32.46#ibcon#read 5, iclass 4, count 0 2006.203.08:11:32.46#ibcon#about to read 6, iclass 4, count 0 2006.203.08:11:32.46#ibcon#read 6, iclass 4, count 0 2006.203.08:11:32.46#ibcon#end of sib2, iclass 4, count 0 2006.203.08:11:32.46#ibcon#*mode == 0, iclass 4, count 0 2006.203.08:11:32.46#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.203.08:11:32.46#ibcon#[27=USB\r\n] 2006.203.08:11:32.46#ibcon#*before write, iclass 4, count 0 2006.203.08:11:32.46#ibcon#enter sib2, iclass 4, count 0 2006.203.08:11:32.46#ibcon#flushed, iclass 4, count 0 2006.203.08:11:32.46#ibcon#about to write, iclass 4, count 0 2006.203.08:11:32.46#ibcon#wrote, iclass 4, count 0 2006.203.08:11:32.46#ibcon#about to read 3, iclass 4, count 0 2006.203.08:11:32.49#ibcon#read 3, iclass 4, count 0 2006.203.08:11:32.49#ibcon#about to read 4, iclass 4, count 0 2006.203.08:11:32.49#ibcon#read 4, iclass 4, count 0 2006.203.08:11:32.49#ibcon#about to read 5, iclass 4, count 0 2006.203.08:11:32.49#ibcon#read 5, iclass 4, count 0 2006.203.08:11:32.49#ibcon#about to read 6, iclass 4, count 0 2006.203.08:11:32.49#ibcon#read 6, iclass 4, count 0 2006.203.08:11:32.49#ibcon#end of sib2, iclass 4, count 0 2006.203.08:11:32.49#ibcon#*after write, iclass 4, count 0 2006.203.08:11:32.49#ibcon#*before return 0, iclass 4, count 0 2006.203.08:11:32.49#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.203.08:11:32.49#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.203.08:11:32.49#ibcon#about to clear, iclass 4 cls_cnt 0 2006.203.08:11:32.49#ibcon#cleared, iclass 4 cls_cnt 0 2006.203.08:11:32.49$vc4f8/vblo=4,712.99 2006.203.08:11:32.49#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.203.08:11:32.49#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.203.08:11:32.49#ibcon#ireg 17 cls_cnt 0 2006.203.08:11:32.49#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.203.08:11:32.49#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.203.08:11:32.49#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.203.08:11:32.49#ibcon#enter wrdev, iclass 6, count 0 2006.203.08:11:32.49#ibcon#first serial, iclass 6, count 0 2006.203.08:11:32.49#ibcon#enter sib2, iclass 6, count 0 2006.203.08:11:32.49#ibcon#flushed, iclass 6, count 0 2006.203.08:11:32.49#ibcon#about to write, iclass 6, count 0 2006.203.08:11:32.50#ibcon#wrote, iclass 6, count 0 2006.203.08:11:32.50#ibcon#about to read 3, iclass 6, count 0 2006.203.08:11:32.51#ibcon#read 3, iclass 6, count 0 2006.203.08:11:32.51#ibcon#about to read 4, iclass 6, count 0 2006.203.08:11:32.51#ibcon#read 4, iclass 6, count 0 2006.203.08:11:32.51#ibcon#about to read 5, iclass 6, count 0 2006.203.08:11:32.51#ibcon#read 5, iclass 6, count 0 2006.203.08:11:32.51#ibcon#about to read 6, iclass 6, count 0 2006.203.08:11:32.51#ibcon#read 6, iclass 6, count 0 2006.203.08:11:32.51#ibcon#end of sib2, iclass 6, count 0 2006.203.08:11:32.51#ibcon#*mode == 0, iclass 6, count 0 2006.203.08:11:32.51#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.203.08:11:32.51#ibcon#[28=FRQ=04,712.99\r\n] 2006.203.08:11:32.51#ibcon#*before write, iclass 6, count 0 2006.203.08:11:32.51#ibcon#enter sib2, iclass 6, count 0 2006.203.08:11:32.51#ibcon#flushed, iclass 6, count 0 2006.203.08:11:32.51#ibcon#about to write, iclass 6, count 0 2006.203.08:11:32.51#ibcon#wrote, iclass 6, count 0 2006.203.08:11:32.51#ibcon#about to read 3, iclass 6, count 0 2006.203.08:11:32.55#ibcon#read 3, iclass 6, count 0 2006.203.08:11:32.55#ibcon#about to read 4, iclass 6, count 0 2006.203.08:11:32.55#ibcon#read 4, iclass 6, count 0 2006.203.08:11:32.55#ibcon#about to read 5, iclass 6, count 0 2006.203.08:11:32.55#ibcon#read 5, iclass 6, count 0 2006.203.08:11:32.55#ibcon#about to read 6, iclass 6, count 0 2006.203.08:11:32.55#ibcon#read 6, iclass 6, count 0 2006.203.08:11:32.55#ibcon#end of sib2, iclass 6, count 0 2006.203.08:11:32.55#ibcon#*after write, iclass 6, count 0 2006.203.08:11:32.55#ibcon#*before return 0, iclass 6, count 0 2006.203.08:11:32.55#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.203.08:11:32.55#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.203.08:11:32.55#ibcon#about to clear, iclass 6 cls_cnt 0 2006.203.08:11:32.55#ibcon#cleared, iclass 6 cls_cnt 0 2006.203.08:11:32.55$vc4f8/vb=4,4 2006.203.08:11:32.55#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.203.08:11:32.55#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.203.08:11:32.55#ibcon#ireg 11 cls_cnt 2 2006.203.08:11:32.55#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.203.08:11:32.61#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.203.08:11:32.61#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.203.08:11:32.61#ibcon#enter wrdev, iclass 10, count 2 2006.203.08:11:32.61#ibcon#first serial, iclass 10, count 2 2006.203.08:11:32.61#ibcon#enter sib2, iclass 10, count 2 2006.203.08:11:32.61#ibcon#flushed, iclass 10, count 2 2006.203.08:11:32.61#ibcon#about to write, iclass 10, count 2 2006.203.08:11:32.61#ibcon#wrote, iclass 10, count 2 2006.203.08:11:32.61#ibcon#about to read 3, iclass 10, count 2 2006.203.08:11:32.63#ibcon#read 3, iclass 10, count 2 2006.203.08:11:32.63#ibcon#about to read 4, iclass 10, count 2 2006.203.08:11:32.63#ibcon#read 4, iclass 10, count 2 2006.203.08:11:32.63#ibcon#about to read 5, iclass 10, count 2 2006.203.08:11:32.63#ibcon#read 5, iclass 10, count 2 2006.203.08:11:32.63#ibcon#about to read 6, iclass 10, count 2 2006.203.08:11:32.63#ibcon#read 6, iclass 10, count 2 2006.203.08:11:32.63#ibcon#end of sib2, iclass 10, count 2 2006.203.08:11:32.63#ibcon#*mode == 0, iclass 10, count 2 2006.203.08:11:32.63#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.203.08:11:32.63#ibcon#[27=AT04-04\r\n] 2006.203.08:11:32.63#ibcon#*before write, iclass 10, count 2 2006.203.08:11:32.63#ibcon#enter sib2, iclass 10, count 2 2006.203.08:11:32.63#ibcon#flushed, iclass 10, count 2 2006.203.08:11:32.63#ibcon#about to write, iclass 10, count 2 2006.203.08:11:32.63#ibcon#wrote, iclass 10, count 2 2006.203.08:11:32.63#ibcon#about to read 3, iclass 10, count 2 2006.203.08:11:32.66#ibcon#read 3, iclass 10, count 2 2006.203.08:11:32.66#ibcon#about to read 4, iclass 10, count 2 2006.203.08:11:32.66#ibcon#read 4, iclass 10, count 2 2006.203.08:11:32.66#ibcon#about to read 5, iclass 10, count 2 2006.203.08:11:32.66#ibcon#read 5, iclass 10, count 2 2006.203.08:11:32.66#ibcon#about to read 6, iclass 10, count 2 2006.203.08:11:32.66#ibcon#read 6, iclass 10, count 2 2006.203.08:11:32.66#ibcon#end of sib2, iclass 10, count 2 2006.203.08:11:32.66#ibcon#*after write, iclass 10, count 2 2006.203.08:11:32.66#ibcon#*before return 0, iclass 10, count 2 2006.203.08:11:32.66#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.203.08:11:32.66#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.203.08:11:32.66#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.203.08:11:32.66#ibcon#ireg 7 cls_cnt 0 2006.203.08:11:32.66#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.203.08:11:32.78#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.203.08:11:32.78#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.203.08:11:32.78#ibcon#enter wrdev, iclass 10, count 0 2006.203.08:11:32.78#ibcon#first serial, iclass 10, count 0 2006.203.08:11:32.78#ibcon#enter sib2, iclass 10, count 0 2006.203.08:11:32.78#ibcon#flushed, iclass 10, count 0 2006.203.08:11:32.78#ibcon#about to write, iclass 10, count 0 2006.203.08:11:32.78#ibcon#wrote, iclass 10, count 0 2006.203.08:11:32.78#ibcon#about to read 3, iclass 10, count 0 2006.203.08:11:32.80#ibcon#read 3, iclass 10, count 0 2006.203.08:11:32.80#ibcon#about to read 4, iclass 10, count 0 2006.203.08:11:32.80#ibcon#read 4, iclass 10, count 0 2006.203.08:11:32.80#ibcon#about to read 5, iclass 10, count 0 2006.203.08:11:32.80#ibcon#read 5, iclass 10, count 0 2006.203.08:11:32.80#ibcon#about to read 6, iclass 10, count 0 2006.203.08:11:32.80#ibcon#read 6, iclass 10, count 0 2006.203.08:11:32.80#ibcon#end of sib2, iclass 10, count 0 2006.203.08:11:32.80#ibcon#*mode == 0, iclass 10, count 0 2006.203.08:11:32.80#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.203.08:11:32.80#ibcon#[27=USB\r\n] 2006.203.08:11:32.80#ibcon#*before write, iclass 10, count 0 2006.203.08:11:32.80#ibcon#enter sib2, iclass 10, count 0 2006.203.08:11:32.80#ibcon#flushed, iclass 10, count 0 2006.203.08:11:32.80#ibcon#about to write, iclass 10, count 0 2006.203.08:11:32.80#ibcon#wrote, iclass 10, count 0 2006.203.08:11:32.80#ibcon#about to read 3, iclass 10, count 0 2006.203.08:11:32.83#ibcon#read 3, iclass 10, count 0 2006.203.08:11:32.83#ibcon#about to read 4, iclass 10, count 0 2006.203.08:11:32.83#ibcon#read 4, iclass 10, count 0 2006.203.08:11:32.83#ibcon#about to read 5, iclass 10, count 0 2006.203.08:11:32.83#ibcon#read 5, iclass 10, count 0 2006.203.08:11:32.83#ibcon#about to read 6, iclass 10, count 0 2006.203.08:11:32.83#ibcon#read 6, iclass 10, count 0 2006.203.08:11:32.83#ibcon#end of sib2, iclass 10, count 0 2006.203.08:11:32.83#ibcon#*after write, iclass 10, count 0 2006.203.08:11:32.83#ibcon#*before return 0, iclass 10, count 0 2006.203.08:11:32.83#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.203.08:11:32.83#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.203.08:11:32.83#ibcon#about to clear, iclass 10 cls_cnt 0 2006.203.08:11:32.83#ibcon#cleared, iclass 10 cls_cnt 0 2006.203.08:11:32.83$vc4f8/vblo=5,744.99 2006.203.08:11:32.83#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.203.08:11:32.83#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.203.08:11:32.83#ibcon#ireg 17 cls_cnt 0 2006.203.08:11:32.83#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.203.08:11:32.83#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.203.08:11:32.83#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.203.08:11:32.83#ibcon#enter wrdev, iclass 12, count 0 2006.203.08:11:32.83#ibcon#first serial, iclass 12, count 0 2006.203.08:11:32.83#ibcon#enter sib2, iclass 12, count 0 2006.203.08:11:32.83#ibcon#flushed, iclass 12, count 0 2006.203.08:11:32.83#ibcon#about to write, iclass 12, count 0 2006.203.08:11:32.84#ibcon#wrote, iclass 12, count 0 2006.203.08:11:32.84#ibcon#about to read 3, iclass 12, count 0 2006.203.08:11:32.85#ibcon#read 3, iclass 12, count 0 2006.203.08:11:32.85#ibcon#about to read 4, iclass 12, count 0 2006.203.08:11:32.85#ibcon#read 4, iclass 12, count 0 2006.203.08:11:32.85#ibcon#about to read 5, iclass 12, count 0 2006.203.08:11:32.85#ibcon#read 5, iclass 12, count 0 2006.203.08:11:32.85#ibcon#about to read 6, iclass 12, count 0 2006.203.08:11:32.85#ibcon#read 6, iclass 12, count 0 2006.203.08:11:32.85#ibcon#end of sib2, iclass 12, count 0 2006.203.08:11:32.85#ibcon#*mode == 0, iclass 12, count 0 2006.203.08:11:32.85#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.203.08:11:32.85#ibcon#[28=FRQ=05,744.99\r\n] 2006.203.08:11:32.85#ibcon#*before write, iclass 12, count 0 2006.203.08:11:32.85#ibcon#enter sib2, iclass 12, count 0 2006.203.08:11:32.85#ibcon#flushed, iclass 12, count 0 2006.203.08:11:32.85#ibcon#about to write, iclass 12, count 0 2006.203.08:11:32.85#ibcon#wrote, iclass 12, count 0 2006.203.08:11:32.85#ibcon#about to read 3, iclass 12, count 0 2006.203.08:11:32.89#ibcon#read 3, iclass 12, count 0 2006.203.08:11:32.89#ibcon#about to read 4, iclass 12, count 0 2006.203.08:11:32.89#ibcon#read 4, iclass 12, count 0 2006.203.08:11:32.89#ibcon#about to read 5, iclass 12, count 0 2006.203.08:11:32.89#ibcon#read 5, iclass 12, count 0 2006.203.08:11:32.89#ibcon#about to read 6, iclass 12, count 0 2006.203.08:11:32.89#ibcon#read 6, iclass 12, count 0 2006.203.08:11:32.89#ibcon#end of sib2, iclass 12, count 0 2006.203.08:11:32.89#ibcon#*after write, iclass 12, count 0 2006.203.08:11:32.89#ibcon#*before return 0, iclass 12, count 0 2006.203.08:11:32.89#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.203.08:11:32.89#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.203.08:11:32.89#ibcon#about to clear, iclass 12 cls_cnt 0 2006.203.08:11:32.89#ibcon#cleared, iclass 12 cls_cnt 0 2006.203.08:11:32.89$vc4f8/vb=5,3 2006.203.08:11:32.89#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.203.08:11:32.89#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.203.08:11:32.89#ibcon#ireg 11 cls_cnt 2 2006.203.08:11:32.89#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.203.08:11:32.96#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.203.08:11:32.96#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.203.08:11:32.96#ibcon#enter wrdev, iclass 14, count 2 2006.203.08:11:32.96#ibcon#first serial, iclass 14, count 2 2006.203.08:11:32.96#ibcon#enter sib2, iclass 14, count 2 2006.203.08:11:32.96#ibcon#flushed, iclass 14, count 2 2006.203.08:11:32.96#ibcon#about to write, iclass 14, count 2 2006.203.08:11:32.96#ibcon#wrote, iclass 14, count 2 2006.203.08:11:32.96#ibcon#about to read 3, iclass 14, count 2 2006.203.08:11:32.98#ibcon#read 3, iclass 14, count 2 2006.203.08:11:32.98#ibcon#about to read 4, iclass 14, count 2 2006.203.08:11:32.98#ibcon#read 4, iclass 14, count 2 2006.203.08:11:32.98#ibcon#about to read 5, iclass 14, count 2 2006.203.08:11:32.98#ibcon#read 5, iclass 14, count 2 2006.203.08:11:32.98#ibcon#about to read 6, iclass 14, count 2 2006.203.08:11:32.98#ibcon#read 6, iclass 14, count 2 2006.203.08:11:32.98#ibcon#end of sib2, iclass 14, count 2 2006.203.08:11:32.98#ibcon#*mode == 0, iclass 14, count 2 2006.203.08:11:32.98#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.203.08:11:32.98#ibcon#[27=AT05-03\r\n] 2006.203.08:11:32.98#ibcon#*before write, iclass 14, count 2 2006.203.08:11:32.98#ibcon#enter sib2, iclass 14, count 2 2006.203.08:11:32.98#ibcon#flushed, iclass 14, count 2 2006.203.08:11:32.98#ibcon#about to write, iclass 14, count 2 2006.203.08:11:32.98#ibcon#wrote, iclass 14, count 2 2006.203.08:11:32.98#ibcon#about to read 3, iclass 14, count 2 2006.203.08:11:33.00#ibcon#read 3, iclass 14, count 2 2006.203.08:11:33.00#ibcon#about to read 4, iclass 14, count 2 2006.203.08:11:33.00#ibcon#read 4, iclass 14, count 2 2006.203.08:11:33.00#ibcon#about to read 5, iclass 14, count 2 2006.203.08:11:33.00#ibcon#read 5, iclass 14, count 2 2006.203.08:11:33.00#ibcon#about to read 6, iclass 14, count 2 2006.203.08:11:33.00#ibcon#read 6, iclass 14, count 2 2006.203.08:11:33.00#ibcon#end of sib2, iclass 14, count 2 2006.203.08:11:33.00#ibcon#*after write, iclass 14, count 2 2006.203.08:11:33.00#ibcon#*before return 0, iclass 14, count 2 2006.203.08:11:33.00#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.203.08:11:33.00#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.203.08:11:33.00#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.203.08:11:33.00#ibcon#ireg 7 cls_cnt 0 2006.203.08:11:33.00#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.203.08:11:33.12#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.203.08:11:33.12#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.203.08:11:33.12#ibcon#enter wrdev, iclass 14, count 0 2006.203.08:11:33.12#ibcon#first serial, iclass 14, count 0 2006.203.08:11:33.12#ibcon#enter sib2, iclass 14, count 0 2006.203.08:11:33.12#ibcon#flushed, iclass 14, count 0 2006.203.08:11:33.12#ibcon#about to write, iclass 14, count 0 2006.203.08:11:33.12#ibcon#wrote, iclass 14, count 0 2006.203.08:11:33.12#ibcon#about to read 3, iclass 14, count 0 2006.203.08:11:33.14#ibcon#read 3, iclass 14, count 0 2006.203.08:11:33.14#ibcon#about to read 4, iclass 14, count 0 2006.203.08:11:33.15#ibcon#read 4, iclass 14, count 0 2006.203.08:11:33.15#ibcon#about to read 5, iclass 14, count 0 2006.203.08:11:33.15#ibcon#read 5, iclass 14, count 0 2006.203.08:11:33.15#ibcon#about to read 6, iclass 14, count 0 2006.203.08:11:33.15#ibcon#read 6, iclass 14, count 0 2006.203.08:11:33.15#ibcon#end of sib2, iclass 14, count 0 2006.203.08:11:33.15#ibcon#*mode == 0, iclass 14, count 0 2006.203.08:11:33.15#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.203.08:11:33.15#ibcon#[27=USB\r\n] 2006.203.08:11:33.15#ibcon#*before write, iclass 14, count 0 2006.203.08:11:33.15#ibcon#enter sib2, iclass 14, count 0 2006.203.08:11:33.15#ibcon#flushed, iclass 14, count 0 2006.203.08:11:33.15#ibcon#about to write, iclass 14, count 0 2006.203.08:11:33.15#ibcon#wrote, iclass 14, count 0 2006.203.08:11:33.15#ibcon#about to read 3, iclass 14, count 0 2006.203.08:11:33.17#ibcon#read 3, iclass 14, count 0 2006.203.08:11:33.17#ibcon#about to read 4, iclass 14, count 0 2006.203.08:11:33.17#ibcon#read 4, iclass 14, count 0 2006.203.08:11:33.17#ibcon#about to read 5, iclass 14, count 0 2006.203.08:11:33.17#ibcon#read 5, iclass 14, count 0 2006.203.08:11:33.17#ibcon#about to read 6, iclass 14, count 0 2006.203.08:11:33.17#ibcon#read 6, iclass 14, count 0 2006.203.08:11:33.17#ibcon#end of sib2, iclass 14, count 0 2006.203.08:11:33.17#ibcon#*after write, iclass 14, count 0 2006.203.08:11:33.17#ibcon#*before return 0, iclass 14, count 0 2006.203.08:11:33.17#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.203.08:11:33.17#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.203.08:11:33.17#ibcon#about to clear, iclass 14 cls_cnt 0 2006.203.08:11:33.17#ibcon#cleared, iclass 14 cls_cnt 0 2006.203.08:11:33.17$vc4f8/vblo=6,752.99 2006.203.08:11:33.17#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.203.08:11:33.17#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.203.08:11:33.17#ibcon#ireg 17 cls_cnt 0 2006.203.08:11:33.17#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.203.08:11:33.17#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.203.08:11:33.17#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.203.08:11:33.17#ibcon#enter wrdev, iclass 16, count 0 2006.203.08:11:33.17#ibcon#first serial, iclass 16, count 0 2006.203.08:11:33.17#ibcon#enter sib2, iclass 16, count 0 2006.203.08:11:33.17#ibcon#flushed, iclass 16, count 0 2006.203.08:11:33.17#ibcon#about to write, iclass 16, count 0 2006.203.08:11:33.18#ibcon#wrote, iclass 16, count 0 2006.203.08:11:33.18#ibcon#about to read 3, iclass 16, count 0 2006.203.08:11:33.19#ibcon#read 3, iclass 16, count 0 2006.203.08:11:33.19#ibcon#about to read 4, iclass 16, count 0 2006.203.08:11:33.19#ibcon#read 4, iclass 16, count 0 2006.203.08:11:33.19#ibcon#about to read 5, iclass 16, count 0 2006.203.08:11:33.19#ibcon#read 5, iclass 16, count 0 2006.203.08:11:33.19#ibcon#about to read 6, iclass 16, count 0 2006.203.08:11:33.19#ibcon#read 6, iclass 16, count 0 2006.203.08:11:33.19#ibcon#end of sib2, iclass 16, count 0 2006.203.08:11:33.19#ibcon#*mode == 0, iclass 16, count 0 2006.203.08:11:33.19#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.203.08:11:33.19#ibcon#[28=FRQ=06,752.99\r\n] 2006.203.08:11:33.19#ibcon#*before write, iclass 16, count 0 2006.203.08:11:33.19#ibcon#enter sib2, iclass 16, count 0 2006.203.08:11:33.19#ibcon#flushed, iclass 16, count 0 2006.203.08:11:33.19#ibcon#about to write, iclass 16, count 0 2006.203.08:11:33.19#ibcon#wrote, iclass 16, count 0 2006.203.08:11:33.19#ibcon#about to read 3, iclass 16, count 0 2006.203.08:11:33.23#ibcon#read 3, iclass 16, count 0 2006.203.08:11:33.23#ibcon#about to read 4, iclass 16, count 0 2006.203.08:11:33.23#ibcon#read 4, iclass 16, count 0 2006.203.08:11:33.23#ibcon#about to read 5, iclass 16, count 0 2006.203.08:11:33.23#ibcon#read 5, iclass 16, count 0 2006.203.08:11:33.23#ibcon#about to read 6, iclass 16, count 0 2006.203.08:11:33.23#ibcon#read 6, iclass 16, count 0 2006.203.08:11:33.23#ibcon#end of sib2, iclass 16, count 0 2006.203.08:11:33.23#ibcon#*after write, iclass 16, count 0 2006.203.08:11:33.23#ibcon#*before return 0, iclass 16, count 0 2006.203.08:11:33.23#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.203.08:11:33.23#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.203.08:11:33.23#ibcon#about to clear, iclass 16 cls_cnt 0 2006.203.08:11:33.23#ibcon#cleared, iclass 16 cls_cnt 0 2006.203.08:11:33.23$vc4f8/vb=6,4 2006.203.08:11:33.23#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.203.08:11:33.23#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.203.08:11:33.23#ibcon#ireg 11 cls_cnt 2 2006.203.08:11:33.23#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.203.08:11:33.29#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.203.08:11:33.29#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.203.08:11:33.29#ibcon#enter wrdev, iclass 18, count 2 2006.203.08:11:33.29#ibcon#first serial, iclass 18, count 2 2006.203.08:11:33.29#ibcon#enter sib2, iclass 18, count 2 2006.203.08:11:33.29#ibcon#flushed, iclass 18, count 2 2006.203.08:11:33.29#ibcon#about to write, iclass 18, count 2 2006.203.08:11:33.29#ibcon#wrote, iclass 18, count 2 2006.203.08:11:33.29#ibcon#about to read 3, iclass 18, count 2 2006.203.08:11:33.31#ibcon#read 3, iclass 18, count 2 2006.203.08:11:33.31#ibcon#about to read 4, iclass 18, count 2 2006.203.08:11:33.31#ibcon#read 4, iclass 18, count 2 2006.203.08:11:33.31#ibcon#about to read 5, iclass 18, count 2 2006.203.08:11:33.31#ibcon#read 5, iclass 18, count 2 2006.203.08:11:33.31#ibcon#about to read 6, iclass 18, count 2 2006.203.08:11:33.31#ibcon#read 6, iclass 18, count 2 2006.203.08:11:33.31#ibcon#end of sib2, iclass 18, count 2 2006.203.08:11:33.31#ibcon#*mode == 0, iclass 18, count 2 2006.203.08:11:33.31#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.203.08:11:33.31#ibcon#[27=AT06-04\r\n] 2006.203.08:11:33.31#ibcon#*before write, iclass 18, count 2 2006.203.08:11:33.31#ibcon#enter sib2, iclass 18, count 2 2006.203.08:11:33.31#ibcon#flushed, iclass 18, count 2 2006.203.08:11:33.31#ibcon#about to write, iclass 18, count 2 2006.203.08:11:33.31#ibcon#wrote, iclass 18, count 2 2006.203.08:11:33.31#ibcon#about to read 3, iclass 18, count 2 2006.203.08:11:33.34#ibcon#read 3, iclass 18, count 2 2006.203.08:11:33.34#ibcon#about to read 4, iclass 18, count 2 2006.203.08:11:33.34#ibcon#read 4, iclass 18, count 2 2006.203.08:11:33.34#ibcon#about to read 5, iclass 18, count 2 2006.203.08:11:33.34#ibcon#read 5, iclass 18, count 2 2006.203.08:11:33.34#ibcon#about to read 6, iclass 18, count 2 2006.203.08:11:33.34#ibcon#read 6, iclass 18, count 2 2006.203.08:11:33.34#ibcon#end of sib2, iclass 18, count 2 2006.203.08:11:33.34#ibcon#*after write, iclass 18, count 2 2006.203.08:11:33.34#ibcon#*before return 0, iclass 18, count 2 2006.203.08:11:33.34#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.203.08:11:33.34#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.203.08:11:33.34#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.203.08:11:33.34#ibcon#ireg 7 cls_cnt 0 2006.203.08:11:33.34#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.203.08:11:33.46#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.203.08:11:33.46#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.203.08:11:33.46#ibcon#enter wrdev, iclass 18, count 0 2006.203.08:11:33.46#ibcon#first serial, iclass 18, count 0 2006.203.08:11:33.46#ibcon#enter sib2, iclass 18, count 0 2006.203.08:11:33.46#ibcon#flushed, iclass 18, count 0 2006.203.08:11:33.46#ibcon#about to write, iclass 18, count 0 2006.203.08:11:33.46#ibcon#wrote, iclass 18, count 0 2006.203.08:11:33.46#ibcon#about to read 3, iclass 18, count 0 2006.203.08:11:33.48#ibcon#read 3, iclass 18, count 0 2006.203.08:11:33.48#ibcon#about to read 4, iclass 18, count 0 2006.203.08:11:33.48#ibcon#read 4, iclass 18, count 0 2006.203.08:11:33.48#ibcon#about to read 5, iclass 18, count 0 2006.203.08:11:33.48#ibcon#read 5, iclass 18, count 0 2006.203.08:11:33.48#ibcon#about to read 6, iclass 18, count 0 2006.203.08:11:33.48#ibcon#read 6, iclass 18, count 0 2006.203.08:11:33.48#ibcon#end of sib2, iclass 18, count 0 2006.203.08:11:33.48#ibcon#*mode == 0, iclass 18, count 0 2006.203.08:11:33.48#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.203.08:11:33.48#ibcon#[27=USB\r\n] 2006.203.08:11:33.48#ibcon#*before write, iclass 18, count 0 2006.203.08:11:33.48#ibcon#enter sib2, iclass 18, count 0 2006.203.08:11:33.48#ibcon#flushed, iclass 18, count 0 2006.203.08:11:33.48#ibcon#about to write, iclass 18, count 0 2006.203.08:11:33.48#ibcon#wrote, iclass 18, count 0 2006.203.08:11:33.48#ibcon#about to read 3, iclass 18, count 0 2006.203.08:11:33.51#ibcon#read 3, iclass 18, count 0 2006.203.08:11:33.51#ibcon#about to read 4, iclass 18, count 0 2006.203.08:11:33.51#ibcon#read 4, iclass 18, count 0 2006.203.08:11:33.51#ibcon#about to read 5, iclass 18, count 0 2006.203.08:11:33.51#ibcon#read 5, iclass 18, count 0 2006.203.08:11:33.51#ibcon#about to read 6, iclass 18, count 0 2006.203.08:11:33.51#ibcon#read 6, iclass 18, count 0 2006.203.08:11:33.51#ibcon#end of sib2, iclass 18, count 0 2006.203.08:11:33.51#ibcon#*after write, iclass 18, count 0 2006.203.08:11:33.51#ibcon#*before return 0, iclass 18, count 0 2006.203.08:11:33.51#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.203.08:11:33.51#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.203.08:11:33.51#ibcon#about to clear, iclass 18 cls_cnt 0 2006.203.08:11:33.51#ibcon#cleared, iclass 18 cls_cnt 0 2006.203.08:11:33.51$vc4f8/vabw=wide 2006.203.08:11:33.51#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.203.08:11:33.51#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.203.08:11:33.51#ibcon#ireg 8 cls_cnt 0 2006.203.08:11:33.51#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.203.08:11:33.51#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.203.08:11:33.51#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.203.08:11:33.51#ibcon#enter wrdev, iclass 20, count 0 2006.203.08:11:33.51#ibcon#first serial, iclass 20, count 0 2006.203.08:11:33.51#ibcon#enter sib2, iclass 20, count 0 2006.203.08:11:33.51#ibcon#flushed, iclass 20, count 0 2006.203.08:11:33.51#ibcon#about to write, iclass 20, count 0 2006.203.08:11:33.51#ibcon#wrote, iclass 20, count 0 2006.203.08:11:33.52#ibcon#about to read 3, iclass 20, count 0 2006.203.08:11:33.53#ibcon#read 3, iclass 20, count 0 2006.203.08:11:33.53#ibcon#about to read 4, iclass 20, count 0 2006.203.08:11:33.53#ibcon#read 4, iclass 20, count 0 2006.203.08:11:33.53#ibcon#about to read 5, iclass 20, count 0 2006.203.08:11:33.53#ibcon#read 5, iclass 20, count 0 2006.203.08:11:33.53#ibcon#about to read 6, iclass 20, count 0 2006.203.08:11:33.53#ibcon#read 6, iclass 20, count 0 2006.203.08:11:33.53#ibcon#end of sib2, iclass 20, count 0 2006.203.08:11:33.53#ibcon#*mode == 0, iclass 20, count 0 2006.203.08:11:33.53#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.203.08:11:33.53#ibcon#[25=BW32\r\n] 2006.203.08:11:33.53#ibcon#*before write, iclass 20, count 0 2006.203.08:11:33.53#ibcon#enter sib2, iclass 20, count 0 2006.203.08:11:33.53#ibcon#flushed, iclass 20, count 0 2006.203.08:11:33.53#ibcon#about to write, iclass 20, count 0 2006.203.08:11:33.53#ibcon#wrote, iclass 20, count 0 2006.203.08:11:33.53#ibcon#about to read 3, iclass 20, count 0 2006.203.08:11:33.56#ibcon#read 3, iclass 20, count 0 2006.203.08:11:33.56#ibcon#about to read 4, iclass 20, count 0 2006.203.08:11:33.56#ibcon#read 4, iclass 20, count 0 2006.203.08:11:33.56#ibcon#about to read 5, iclass 20, count 0 2006.203.08:11:33.56#ibcon#read 5, iclass 20, count 0 2006.203.08:11:33.56#ibcon#about to read 6, iclass 20, count 0 2006.203.08:11:33.56#ibcon#read 6, iclass 20, count 0 2006.203.08:11:33.56#ibcon#end of sib2, iclass 20, count 0 2006.203.08:11:33.56#ibcon#*after write, iclass 20, count 0 2006.203.08:11:33.56#ibcon#*before return 0, iclass 20, count 0 2006.203.08:11:33.56#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.203.08:11:33.56#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.203.08:11:33.56#ibcon#about to clear, iclass 20 cls_cnt 0 2006.203.08:11:33.56#ibcon#cleared, iclass 20 cls_cnt 0 2006.203.08:11:33.56$vc4f8/vbbw=wide 2006.203.08:11:33.56#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.203.08:11:33.56#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.203.08:11:33.56#ibcon#ireg 8 cls_cnt 0 2006.203.08:11:33.56#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.203.08:11:33.64#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.203.08:11:33.64#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.203.08:11:33.64#ibcon#enter wrdev, iclass 22, count 0 2006.203.08:11:33.64#ibcon#first serial, iclass 22, count 0 2006.203.08:11:33.64#ibcon#enter sib2, iclass 22, count 0 2006.203.08:11:33.64#ibcon#flushed, iclass 22, count 0 2006.203.08:11:33.64#ibcon#about to write, iclass 22, count 0 2006.203.08:11:33.64#ibcon#wrote, iclass 22, count 0 2006.203.08:11:33.64#ibcon#about to read 3, iclass 22, count 0 2006.203.08:11:33.66#ibcon#read 3, iclass 22, count 0 2006.203.08:11:33.66#ibcon#about to read 4, iclass 22, count 0 2006.203.08:11:33.66#ibcon#read 4, iclass 22, count 0 2006.203.08:11:33.66#ibcon#about to read 5, iclass 22, count 0 2006.203.08:11:33.66#ibcon#read 5, iclass 22, count 0 2006.203.08:11:33.66#ibcon#about to read 6, iclass 22, count 0 2006.203.08:11:33.66#ibcon#read 6, iclass 22, count 0 2006.203.08:11:33.66#ibcon#end of sib2, iclass 22, count 0 2006.203.08:11:33.66#ibcon#*mode == 0, iclass 22, count 0 2006.203.08:11:33.66#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.203.08:11:33.66#ibcon#[27=BW32\r\n] 2006.203.08:11:33.66#ibcon#*before write, iclass 22, count 0 2006.203.08:11:33.66#ibcon#enter sib2, iclass 22, count 0 2006.203.08:11:33.66#ibcon#flushed, iclass 22, count 0 2006.203.08:11:33.66#ibcon#about to write, iclass 22, count 0 2006.203.08:11:33.66#ibcon#wrote, iclass 22, count 0 2006.203.08:11:33.66#ibcon#about to read 3, iclass 22, count 0 2006.203.08:11:33.68#ibcon#read 3, iclass 22, count 0 2006.203.08:11:33.68#ibcon#about to read 4, iclass 22, count 0 2006.203.08:11:33.68#ibcon#read 4, iclass 22, count 0 2006.203.08:11:33.68#ibcon#about to read 5, iclass 22, count 0 2006.203.08:11:33.68#ibcon#read 5, iclass 22, count 0 2006.203.08:11:33.68#ibcon#about to read 6, iclass 22, count 0 2006.203.08:11:33.68#ibcon#read 6, iclass 22, count 0 2006.203.08:11:33.68#ibcon#end of sib2, iclass 22, count 0 2006.203.08:11:33.68#ibcon#*after write, iclass 22, count 0 2006.203.08:11:33.68#ibcon#*before return 0, iclass 22, count 0 2006.203.08:11:33.68#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.203.08:11:33.68#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.203.08:11:33.68#ibcon#about to clear, iclass 22 cls_cnt 0 2006.203.08:11:33.68#ibcon#cleared, iclass 22 cls_cnt 0 2006.203.08:11:33.68$4f8m12a/ifd4f 2006.203.08:11:33.68$ifd4f/lo= 2006.203.08:11:33.69$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.203.08:11:33.69$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.203.08:11:33.69$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.203.08:11:33.69$ifd4f/patch= 2006.203.08:11:33.69$ifd4f/patch=lo1,a1,a2,a3,a4 2006.203.08:11:33.69$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.203.08:11:33.69$ifd4f/patch=lo3,a5,a6,a7,a8 2006.203.08:11:33.69$4f8m12a/"form=m,16.000,1:2 2006.203.08:11:33.69$4f8m12a/"tpicd 2006.203.08:11:33.69$4f8m12a/echo=off 2006.203.08:11:33.69$4f8m12a/xlog=off 2006.203.08:11:33.69:!2006.203.08:12:00 2006.203.08:11:43.14#trakl#Source acquired 2006.203.08:11:45.14#flagr#flagr/antenna,acquired 2006.203.08:12:00.01:preob 2006.203.08:12:01.14/onsource/TRACKING 2006.203.08:12:01.14:!2006.203.08:12:10 2006.203.08:12:10.00:data_valid=on 2006.203.08:12:10.00:midob 2006.203.08:12:10.13/onsource/TRACKING 2006.203.08:12:10.14/wx/23.61,1001.0,100 2006.203.08:12:10.34/cable/+6.4581E-03 2006.203.08:12:11.43/va/01,08,usb,yes,29,31 2006.203.08:12:11.43/va/02,07,usb,yes,29,31 2006.203.08:12:11.43/va/03,08,usb,yes,22,22 2006.203.08:12:11.43/va/04,07,usb,yes,30,32 2006.203.08:12:11.43/va/05,07,usb,yes,33,35 2006.203.08:12:11.43/va/06,06,usb,yes,32,32 2006.203.08:12:11.43/va/07,07,usb,yes,28,28 2006.203.08:12:11.43/va/08,06,usb,yes,35,34 2006.203.08:12:11.66/valo/01,532.99,yes,locked 2006.203.08:12:11.66/valo/02,572.99,yes,locked 2006.203.08:12:11.66/valo/03,672.99,yes,locked 2006.203.08:12:11.66/valo/04,832.99,yes,locked 2006.203.08:12:11.66/valo/05,652.99,yes,locked 2006.203.08:12:11.66/valo/06,772.99,yes,locked 2006.203.08:12:11.66/valo/07,832.99,yes,locked 2006.203.08:12:11.66/valo/08,852.99,yes,locked 2006.203.08:12:12.75/vb/01,04,usb,yes,29,27 2006.203.08:12:12.75/vb/02,04,usb,yes,30,32 2006.203.08:12:12.75/vb/03,04,usb,yes,27,30 2006.203.08:12:12.75/vb/04,04,usb,yes,28,28 2006.203.08:12:12.75/vb/05,03,usb,yes,33,37 2006.203.08:12:12.75/vb/06,04,usb,yes,27,30 2006.203.08:12:12.75/vb/07,04,usb,yes,29,29 2006.203.08:12:12.75/vb/08,04,usb,yes,27,30 2006.203.08:12:12.99/vblo/01,632.99,yes,locked 2006.203.08:12:12.99/vblo/02,640.99,yes,locked 2006.203.08:12:12.99/vblo/03,656.99,yes,locked 2006.203.08:12:12.99/vblo/04,712.99,yes,locked 2006.203.08:12:12.99/vblo/05,744.99,yes,locked 2006.203.08:12:12.99/vblo/06,752.99,yes,locked 2006.203.08:12:12.99/vblo/07,734.99,yes,locked 2006.203.08:12:12.99/vblo/08,744.99,yes,locked 2006.203.08:12:13.14/vabw/8 2006.203.08:12:13.29/vbbw/8 2006.203.08:12:13.38/xfe/off,on,13.7 2006.203.08:12:13.75/ifatt/23,28,28,28 2006.203.08:12:14.06/fmout-gps/S +4.58E-07 2006.203.08:12:14.14:!2006.203.08:13:10 2006.203.08:13:10.01:data_valid=off 2006.203.08:13:10.02:postob 2006.203.08:13:10.22/cable/+6.4617E-03 2006.203.08:13:10.23/wx/23.61,1001.0,100 2006.203.08:13:11.07/fmout-gps/S +4.58E-07 2006.203.08:13:11.08:scan_name=203-0814,k06203,60 2006.203.08:13:11.08:source=1300+580,130252.47,574837.6,2000.0,ccw 2006.203.08:13:11.13#flagr#flagr/antenna,new-source 2006.203.08:13:12.14:checkk5 2006.203.08:13:12.52/chk_autoobs//k5ts1/ autoobs is running! 2006.203.08:13:12.92/chk_autoobs//k5ts2/ autoobs is running! 2006.203.08:13:13.37/chk_autoobs//k5ts3/ autoobs is running! 2006.203.08:13:13.79/chk_autoobs//k5ts4/ autoobs is running! 2006.203.08:13:14.22/chk_obsdata//k5ts1/T2030812??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.08:13:14.62/chk_obsdata//k5ts2/T2030812??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.08:13:15.02/chk_obsdata//k5ts3/T2030812??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.08:13:15.42/chk_obsdata//k5ts4/T2030812??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.08:13:16.34/k5log//k5ts1_log_newline 2006.203.08:13:17.08/k5log//k5ts2_log_newline 2006.203.08:13:17.88/k5log//k5ts3_log_newline 2006.203.08:13:18.90/k5log//k5ts4_log_newline 2006.203.08:13:18.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.203.08:13:18.92:4f8m12a=2 2006.203.08:13:18.92$4f8m12a/echo=on 2006.203.08:13:18.92$4f8m12a/pcalon 2006.203.08:13:18.92$pcalon/"no phase cal control is implemented here 2006.203.08:13:18.92$4f8m12a/"tpicd=stop 2006.203.08:13:18.92$4f8m12a/vc4f8 2006.203.08:13:18.92$vc4f8/valo=1,532.99 2006.203.08:13:18.93#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.203.08:13:18.93#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.203.08:13:18.93#ibcon#ireg 17 cls_cnt 0 2006.203.08:13:18.93#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.203.08:13:18.93#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.203.08:13:18.93#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.203.08:13:18.93#ibcon#enter wrdev, iclass 33, count 0 2006.203.08:13:18.93#ibcon#first serial, iclass 33, count 0 2006.203.08:13:18.93#ibcon#enter sib2, iclass 33, count 0 2006.203.08:13:18.93#ibcon#flushed, iclass 33, count 0 2006.203.08:13:18.93#ibcon#about to write, iclass 33, count 0 2006.203.08:13:18.93#ibcon#wrote, iclass 33, count 0 2006.203.08:13:18.93#ibcon#about to read 3, iclass 33, count 0 2006.203.08:13:18.97#ibcon#read 3, iclass 33, count 0 2006.203.08:13:18.97#ibcon#about to read 4, iclass 33, count 0 2006.203.08:13:18.97#ibcon#read 4, iclass 33, count 0 2006.203.08:13:18.97#ibcon#about to read 5, iclass 33, count 0 2006.203.08:13:18.97#ibcon#read 5, iclass 33, count 0 2006.203.08:13:18.97#ibcon#about to read 6, iclass 33, count 0 2006.203.08:13:18.97#ibcon#read 6, iclass 33, count 0 2006.203.08:13:18.97#ibcon#end of sib2, iclass 33, count 0 2006.203.08:13:18.97#ibcon#*mode == 0, iclass 33, count 0 2006.203.08:13:18.97#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.203.08:13:18.97#ibcon#[26=FRQ=01,532.99\r\n] 2006.203.08:13:18.97#ibcon#*before write, iclass 33, count 0 2006.203.08:13:18.97#ibcon#enter sib2, iclass 33, count 0 2006.203.08:13:18.97#ibcon#flushed, iclass 33, count 0 2006.203.08:13:18.97#ibcon#about to write, iclass 33, count 0 2006.203.08:13:18.97#ibcon#wrote, iclass 33, count 0 2006.203.08:13:18.97#ibcon#about to read 3, iclass 33, count 0 2006.203.08:13:19.01#ibcon#read 3, iclass 33, count 0 2006.203.08:13:19.01#ibcon#about to read 4, iclass 33, count 0 2006.203.08:13:19.01#ibcon#read 4, iclass 33, count 0 2006.203.08:13:19.01#ibcon#about to read 5, iclass 33, count 0 2006.203.08:13:19.01#ibcon#read 5, iclass 33, count 0 2006.203.08:13:19.01#ibcon#about to read 6, iclass 33, count 0 2006.203.08:13:19.01#ibcon#read 6, iclass 33, count 0 2006.203.08:13:19.01#ibcon#end of sib2, iclass 33, count 0 2006.203.08:13:19.01#ibcon#*after write, iclass 33, count 0 2006.203.08:13:19.01#ibcon#*before return 0, iclass 33, count 0 2006.203.08:13:19.01#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.203.08:13:19.01#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.203.08:13:19.01#ibcon#about to clear, iclass 33 cls_cnt 0 2006.203.08:13:19.01#ibcon#cleared, iclass 33 cls_cnt 0 2006.203.08:13:19.02$vc4f8/va=1,8 2006.203.08:13:19.02#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.203.08:13:19.02#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.203.08:13:19.02#ibcon#ireg 11 cls_cnt 2 2006.203.08:13:19.02#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.203.08:13:19.02#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.203.08:13:19.02#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.203.08:13:19.02#ibcon#enter wrdev, iclass 35, count 2 2006.203.08:13:19.02#ibcon#first serial, iclass 35, count 2 2006.203.08:13:19.02#ibcon#enter sib2, iclass 35, count 2 2006.203.08:13:19.02#ibcon#flushed, iclass 35, count 2 2006.203.08:13:19.02#ibcon#about to write, iclass 35, count 2 2006.203.08:13:19.02#ibcon#wrote, iclass 35, count 2 2006.203.08:13:19.02#ibcon#about to read 3, iclass 35, count 2 2006.203.08:13:19.03#ibcon#read 3, iclass 35, count 2 2006.203.08:13:19.03#ibcon#about to read 4, iclass 35, count 2 2006.203.08:13:19.03#ibcon#read 4, iclass 35, count 2 2006.203.08:13:19.03#ibcon#about to read 5, iclass 35, count 2 2006.203.08:13:19.03#ibcon#read 5, iclass 35, count 2 2006.203.08:13:19.03#ibcon#about to read 6, iclass 35, count 2 2006.203.08:13:19.03#ibcon#read 6, iclass 35, count 2 2006.203.08:13:19.03#ibcon#end of sib2, iclass 35, count 2 2006.203.08:13:19.03#ibcon#*mode == 0, iclass 35, count 2 2006.203.08:13:19.03#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.203.08:13:19.03#ibcon#[25=AT01-08\r\n] 2006.203.08:13:19.03#ibcon#*before write, iclass 35, count 2 2006.203.08:13:19.03#ibcon#enter sib2, iclass 35, count 2 2006.203.08:13:19.03#ibcon#flushed, iclass 35, count 2 2006.203.08:13:19.03#ibcon#about to write, iclass 35, count 2 2006.203.08:13:19.03#ibcon#wrote, iclass 35, count 2 2006.203.08:13:19.03#ibcon#about to read 3, iclass 35, count 2 2006.203.08:13:19.07#ibcon#read 3, iclass 35, count 2 2006.203.08:13:19.07#ibcon#about to read 4, iclass 35, count 2 2006.203.08:13:19.07#ibcon#read 4, iclass 35, count 2 2006.203.08:13:19.07#ibcon#about to read 5, iclass 35, count 2 2006.203.08:13:19.07#ibcon#read 5, iclass 35, count 2 2006.203.08:13:19.07#ibcon#about to read 6, iclass 35, count 2 2006.203.08:13:19.07#ibcon#read 6, iclass 35, count 2 2006.203.08:13:19.07#ibcon#end of sib2, iclass 35, count 2 2006.203.08:13:19.07#ibcon#*after write, iclass 35, count 2 2006.203.08:13:19.07#ibcon#*before return 0, iclass 35, count 2 2006.203.08:13:19.07#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.203.08:13:19.07#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.203.08:13:19.07#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.203.08:13:19.07#ibcon#ireg 7 cls_cnt 0 2006.203.08:13:19.07#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.203.08:13:19.18#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.203.08:13:19.18#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.203.08:13:19.18#ibcon#enter wrdev, iclass 35, count 0 2006.203.08:13:19.18#ibcon#first serial, iclass 35, count 0 2006.203.08:13:19.18#ibcon#enter sib2, iclass 35, count 0 2006.203.08:13:19.18#ibcon#flushed, iclass 35, count 0 2006.203.08:13:19.18#ibcon#about to write, iclass 35, count 0 2006.203.08:13:19.18#ibcon#wrote, iclass 35, count 0 2006.203.08:13:19.18#ibcon#about to read 3, iclass 35, count 0 2006.203.08:13:19.20#ibcon#read 3, iclass 35, count 0 2006.203.08:13:19.20#ibcon#about to read 4, iclass 35, count 0 2006.203.08:13:19.20#ibcon#read 4, iclass 35, count 0 2006.203.08:13:19.20#ibcon#about to read 5, iclass 35, count 0 2006.203.08:13:19.20#ibcon#read 5, iclass 35, count 0 2006.203.08:13:19.20#ibcon#about to read 6, iclass 35, count 0 2006.203.08:13:19.20#ibcon#read 6, iclass 35, count 0 2006.203.08:13:19.20#ibcon#end of sib2, iclass 35, count 0 2006.203.08:13:19.20#ibcon#*mode == 0, iclass 35, count 0 2006.203.08:13:19.20#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.203.08:13:19.20#ibcon#[25=USB\r\n] 2006.203.08:13:19.20#ibcon#*before write, iclass 35, count 0 2006.203.08:13:19.20#ibcon#enter sib2, iclass 35, count 0 2006.203.08:13:19.20#ibcon#flushed, iclass 35, count 0 2006.203.08:13:19.20#ibcon#about to write, iclass 35, count 0 2006.203.08:13:19.20#ibcon#wrote, iclass 35, count 0 2006.203.08:13:19.20#ibcon#about to read 3, iclass 35, count 0 2006.203.08:13:19.23#ibcon#read 3, iclass 35, count 0 2006.203.08:13:19.23#ibcon#about to read 4, iclass 35, count 0 2006.203.08:13:19.23#ibcon#read 4, iclass 35, count 0 2006.203.08:13:19.23#ibcon#about to read 5, iclass 35, count 0 2006.203.08:13:19.23#ibcon#read 5, iclass 35, count 0 2006.203.08:13:19.23#ibcon#about to read 6, iclass 35, count 0 2006.203.08:13:19.23#ibcon#read 6, iclass 35, count 0 2006.203.08:13:19.23#ibcon#end of sib2, iclass 35, count 0 2006.203.08:13:19.23#ibcon#*after write, iclass 35, count 0 2006.203.08:13:19.23#ibcon#*before return 0, iclass 35, count 0 2006.203.08:13:19.23#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.203.08:13:19.23#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.203.08:13:19.23#ibcon#about to clear, iclass 35 cls_cnt 0 2006.203.08:13:19.23#ibcon#cleared, iclass 35 cls_cnt 0 2006.203.08:13:19.23$vc4f8/valo=2,572.99 2006.203.08:13:19.23#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.203.08:13:19.23#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.203.08:13:19.23#ibcon#ireg 17 cls_cnt 0 2006.203.08:13:19.23#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.203.08:13:19.23#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.203.08:13:19.23#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.203.08:13:19.23#ibcon#enter wrdev, iclass 37, count 0 2006.203.08:13:19.23#ibcon#first serial, iclass 37, count 0 2006.203.08:13:19.23#ibcon#enter sib2, iclass 37, count 0 2006.203.08:13:19.24#ibcon#flushed, iclass 37, count 0 2006.203.08:13:19.24#ibcon#about to write, iclass 37, count 0 2006.203.08:13:19.24#ibcon#wrote, iclass 37, count 0 2006.203.08:13:19.24#ibcon#about to read 3, iclass 37, count 0 2006.203.08:13:19.25#ibcon#read 3, iclass 37, count 0 2006.203.08:13:19.25#ibcon#about to read 4, iclass 37, count 0 2006.203.08:13:19.25#ibcon#read 4, iclass 37, count 0 2006.203.08:13:19.25#ibcon#about to read 5, iclass 37, count 0 2006.203.08:13:19.25#ibcon#read 5, iclass 37, count 0 2006.203.08:13:19.25#ibcon#about to read 6, iclass 37, count 0 2006.203.08:13:19.25#ibcon#read 6, iclass 37, count 0 2006.203.08:13:19.25#ibcon#end of sib2, iclass 37, count 0 2006.203.08:13:19.25#ibcon#*mode == 0, iclass 37, count 0 2006.203.08:13:19.25#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.203.08:13:19.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.203.08:13:19.25#ibcon#*before write, iclass 37, count 0 2006.203.08:13:19.25#ibcon#enter sib2, iclass 37, count 0 2006.203.08:13:19.25#ibcon#flushed, iclass 37, count 0 2006.203.08:13:19.25#ibcon#about to write, iclass 37, count 0 2006.203.08:13:19.25#ibcon#wrote, iclass 37, count 0 2006.203.08:13:19.25#ibcon#about to read 3, iclass 37, count 0 2006.203.08:13:19.29#ibcon#read 3, iclass 37, count 0 2006.203.08:13:19.29#ibcon#about to read 4, iclass 37, count 0 2006.203.08:13:19.29#ibcon#read 4, iclass 37, count 0 2006.203.08:13:19.29#ibcon#about to read 5, iclass 37, count 0 2006.203.08:13:19.29#ibcon#read 5, iclass 37, count 0 2006.203.08:13:19.29#ibcon#about to read 6, iclass 37, count 0 2006.203.08:13:19.29#ibcon#read 6, iclass 37, count 0 2006.203.08:13:19.29#ibcon#end of sib2, iclass 37, count 0 2006.203.08:13:19.29#ibcon#*after write, iclass 37, count 0 2006.203.08:13:19.29#ibcon#*before return 0, iclass 37, count 0 2006.203.08:13:19.29#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.203.08:13:19.29#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.203.08:13:19.29#ibcon#about to clear, iclass 37 cls_cnt 0 2006.203.08:13:19.29#ibcon#cleared, iclass 37 cls_cnt 0 2006.203.08:13:19.30$vc4f8/va=2,7 2006.203.08:13:19.30#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.203.08:13:19.30#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.203.08:13:19.30#ibcon#ireg 11 cls_cnt 2 2006.203.08:13:19.30#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.203.08:13:19.34#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.203.08:13:19.34#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.203.08:13:19.34#ibcon#enter wrdev, iclass 39, count 2 2006.203.08:13:19.34#ibcon#first serial, iclass 39, count 2 2006.203.08:13:19.34#ibcon#enter sib2, iclass 39, count 2 2006.203.08:13:19.34#ibcon#flushed, iclass 39, count 2 2006.203.08:13:19.34#ibcon#about to write, iclass 39, count 2 2006.203.08:13:19.34#ibcon#wrote, iclass 39, count 2 2006.203.08:13:19.34#ibcon#about to read 3, iclass 39, count 2 2006.203.08:13:19.36#ibcon#read 3, iclass 39, count 2 2006.203.08:13:19.36#ibcon#about to read 4, iclass 39, count 2 2006.203.08:13:19.36#ibcon#read 4, iclass 39, count 2 2006.203.08:13:19.36#ibcon#about to read 5, iclass 39, count 2 2006.203.08:13:19.36#ibcon#read 5, iclass 39, count 2 2006.203.08:13:19.36#ibcon#about to read 6, iclass 39, count 2 2006.203.08:13:19.36#ibcon#read 6, iclass 39, count 2 2006.203.08:13:19.36#ibcon#end of sib2, iclass 39, count 2 2006.203.08:13:19.36#ibcon#*mode == 0, iclass 39, count 2 2006.203.08:13:19.36#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.203.08:13:19.36#ibcon#[25=AT02-07\r\n] 2006.203.08:13:19.36#ibcon#*before write, iclass 39, count 2 2006.203.08:13:19.36#ibcon#enter sib2, iclass 39, count 2 2006.203.08:13:19.36#ibcon#flushed, iclass 39, count 2 2006.203.08:13:19.36#ibcon#about to write, iclass 39, count 2 2006.203.08:13:19.36#ibcon#wrote, iclass 39, count 2 2006.203.08:13:19.37#ibcon#about to read 3, iclass 39, count 2 2006.203.08:13:19.39#ibcon#read 3, iclass 39, count 2 2006.203.08:13:19.39#ibcon#about to read 4, iclass 39, count 2 2006.203.08:13:19.39#ibcon#read 4, iclass 39, count 2 2006.203.08:13:19.39#ibcon#about to read 5, iclass 39, count 2 2006.203.08:13:19.39#ibcon#read 5, iclass 39, count 2 2006.203.08:13:19.39#ibcon#about to read 6, iclass 39, count 2 2006.203.08:13:19.39#ibcon#read 6, iclass 39, count 2 2006.203.08:13:19.39#ibcon#end of sib2, iclass 39, count 2 2006.203.08:13:19.39#ibcon#*after write, iclass 39, count 2 2006.203.08:13:19.39#ibcon#*before return 0, iclass 39, count 2 2006.203.08:13:19.40#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.203.08:13:19.40#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.203.08:13:19.40#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.203.08:13:19.40#ibcon#ireg 7 cls_cnt 0 2006.203.08:13:19.40#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.203.08:13:19.51#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.203.08:13:19.51#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.203.08:13:19.51#ibcon#enter wrdev, iclass 39, count 0 2006.203.08:13:19.51#ibcon#first serial, iclass 39, count 0 2006.203.08:13:19.51#ibcon#enter sib2, iclass 39, count 0 2006.203.08:13:19.51#ibcon#flushed, iclass 39, count 0 2006.203.08:13:19.51#ibcon#about to write, iclass 39, count 0 2006.203.08:13:19.51#ibcon#wrote, iclass 39, count 0 2006.203.08:13:19.51#ibcon#about to read 3, iclass 39, count 0 2006.203.08:13:19.53#ibcon#read 3, iclass 39, count 0 2006.203.08:13:19.53#ibcon#about to read 4, iclass 39, count 0 2006.203.08:13:19.53#ibcon#read 4, iclass 39, count 0 2006.203.08:13:19.53#ibcon#about to read 5, iclass 39, count 0 2006.203.08:13:19.53#ibcon#read 5, iclass 39, count 0 2006.203.08:13:19.53#ibcon#about to read 6, iclass 39, count 0 2006.203.08:13:19.53#ibcon#read 6, iclass 39, count 0 2006.203.08:13:19.53#ibcon#end of sib2, iclass 39, count 0 2006.203.08:13:19.53#ibcon#*mode == 0, iclass 39, count 0 2006.203.08:13:19.53#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.203.08:13:19.53#ibcon#[25=USB\r\n] 2006.203.08:13:19.53#ibcon#*before write, iclass 39, count 0 2006.203.08:13:19.53#ibcon#enter sib2, iclass 39, count 0 2006.203.08:13:19.53#ibcon#flushed, iclass 39, count 0 2006.203.08:13:19.53#ibcon#about to write, iclass 39, count 0 2006.203.08:13:19.53#ibcon#wrote, iclass 39, count 0 2006.203.08:13:19.53#ibcon#about to read 3, iclass 39, count 0 2006.203.08:13:19.56#ibcon#read 3, iclass 39, count 0 2006.203.08:13:19.56#ibcon#about to read 4, iclass 39, count 0 2006.203.08:13:19.56#ibcon#read 4, iclass 39, count 0 2006.203.08:13:19.56#ibcon#about to read 5, iclass 39, count 0 2006.203.08:13:19.56#ibcon#read 5, iclass 39, count 0 2006.203.08:13:19.56#ibcon#about to read 6, iclass 39, count 0 2006.203.08:13:19.56#ibcon#read 6, iclass 39, count 0 2006.203.08:13:19.56#ibcon#end of sib2, iclass 39, count 0 2006.203.08:13:19.56#ibcon#*after write, iclass 39, count 0 2006.203.08:13:19.56#ibcon#*before return 0, iclass 39, count 0 2006.203.08:13:19.56#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.203.08:13:19.56#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.203.08:13:19.56#ibcon#about to clear, iclass 39 cls_cnt 0 2006.203.08:13:19.56#ibcon#cleared, iclass 39 cls_cnt 0 2006.203.08:13:19.56$vc4f8/valo=3,672.99 2006.203.08:13:19.56#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.203.08:13:19.56#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.203.08:13:19.56#ibcon#ireg 17 cls_cnt 0 2006.203.08:13:19.56#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.203.08:13:19.56#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.203.08:13:19.56#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.203.08:13:19.56#ibcon#enter wrdev, iclass 3, count 0 2006.203.08:13:19.56#ibcon#first serial, iclass 3, count 0 2006.203.08:13:19.56#ibcon#enter sib2, iclass 3, count 0 2006.203.08:13:19.57#ibcon#flushed, iclass 3, count 0 2006.203.08:13:19.57#ibcon#about to write, iclass 3, count 0 2006.203.08:13:19.57#ibcon#wrote, iclass 3, count 0 2006.203.08:13:19.57#ibcon#about to read 3, iclass 3, count 0 2006.203.08:13:19.59#ibcon#read 3, iclass 3, count 0 2006.203.08:13:19.59#ibcon#about to read 4, iclass 3, count 0 2006.203.08:13:19.59#ibcon#read 4, iclass 3, count 0 2006.203.08:13:19.59#ibcon#about to read 5, iclass 3, count 0 2006.203.08:13:19.59#ibcon#read 5, iclass 3, count 0 2006.203.08:13:19.59#ibcon#about to read 6, iclass 3, count 0 2006.203.08:13:19.59#ibcon#read 6, iclass 3, count 0 2006.203.08:13:19.59#ibcon#end of sib2, iclass 3, count 0 2006.203.08:13:19.59#ibcon#*mode == 0, iclass 3, count 0 2006.203.08:13:19.59#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.203.08:13:19.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.203.08:13:19.59#ibcon#*before write, iclass 3, count 0 2006.203.08:13:19.59#ibcon#enter sib2, iclass 3, count 0 2006.203.08:13:19.59#ibcon#flushed, iclass 3, count 0 2006.203.08:13:19.59#ibcon#about to write, iclass 3, count 0 2006.203.08:13:19.59#ibcon#wrote, iclass 3, count 0 2006.203.08:13:19.59#ibcon#about to read 3, iclass 3, count 0 2006.203.08:13:19.63#ibcon#read 3, iclass 3, count 0 2006.203.08:13:19.63#ibcon#about to read 4, iclass 3, count 0 2006.203.08:13:19.63#ibcon#read 4, iclass 3, count 0 2006.203.08:13:19.63#ibcon#about to read 5, iclass 3, count 0 2006.203.08:13:19.63#ibcon#read 5, iclass 3, count 0 2006.203.08:13:19.63#ibcon#about to read 6, iclass 3, count 0 2006.203.08:13:19.63#ibcon#read 6, iclass 3, count 0 2006.203.08:13:19.63#ibcon#end of sib2, iclass 3, count 0 2006.203.08:13:19.63#ibcon#*after write, iclass 3, count 0 2006.203.08:13:19.63#ibcon#*before return 0, iclass 3, count 0 2006.203.08:13:19.63#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.203.08:13:19.63#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.203.08:13:19.63#ibcon#about to clear, iclass 3 cls_cnt 0 2006.203.08:13:19.63#ibcon#cleared, iclass 3 cls_cnt 0 2006.203.08:13:19.63$vc4f8/va=3,8 2006.203.08:13:19.63#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.203.08:13:19.63#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.203.08:13:19.63#ibcon#ireg 11 cls_cnt 2 2006.203.08:13:19.63#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.203.08:13:19.69#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.203.08:13:19.69#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.203.08:13:19.69#ibcon#enter wrdev, iclass 5, count 2 2006.203.08:13:19.69#ibcon#first serial, iclass 5, count 2 2006.203.08:13:19.69#ibcon#enter sib2, iclass 5, count 2 2006.203.08:13:19.69#ibcon#flushed, iclass 5, count 2 2006.203.08:13:19.69#ibcon#about to write, iclass 5, count 2 2006.203.08:13:19.69#ibcon#wrote, iclass 5, count 2 2006.203.08:13:19.69#ibcon#about to read 3, iclass 5, count 2 2006.203.08:13:19.70#ibcon#read 3, iclass 5, count 2 2006.203.08:13:19.70#ibcon#about to read 4, iclass 5, count 2 2006.203.08:13:19.70#ibcon#read 4, iclass 5, count 2 2006.203.08:13:19.70#ibcon#about to read 5, iclass 5, count 2 2006.203.08:13:19.70#ibcon#read 5, iclass 5, count 2 2006.203.08:13:19.70#ibcon#about to read 6, iclass 5, count 2 2006.203.08:13:19.70#ibcon#read 6, iclass 5, count 2 2006.203.08:13:19.70#ibcon#end of sib2, iclass 5, count 2 2006.203.08:13:19.70#ibcon#*mode == 0, iclass 5, count 2 2006.203.08:13:19.70#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.203.08:13:19.70#ibcon#[25=AT03-08\r\n] 2006.203.08:13:19.70#ibcon#*before write, iclass 5, count 2 2006.203.08:13:19.70#ibcon#enter sib2, iclass 5, count 2 2006.203.08:13:19.70#ibcon#flushed, iclass 5, count 2 2006.203.08:13:19.70#ibcon#about to write, iclass 5, count 2 2006.203.08:13:19.70#ibcon#wrote, iclass 5, count 2 2006.203.08:13:19.70#ibcon#about to read 3, iclass 5, count 2 2006.203.08:13:19.73#ibcon#read 3, iclass 5, count 2 2006.203.08:13:19.73#ibcon#about to read 4, iclass 5, count 2 2006.203.08:13:19.73#ibcon#read 4, iclass 5, count 2 2006.203.08:13:19.73#ibcon#about to read 5, iclass 5, count 2 2006.203.08:13:19.73#ibcon#read 5, iclass 5, count 2 2006.203.08:13:19.73#ibcon#about to read 6, iclass 5, count 2 2006.203.08:13:19.73#ibcon#read 6, iclass 5, count 2 2006.203.08:13:19.73#ibcon#end of sib2, iclass 5, count 2 2006.203.08:13:19.73#ibcon#*after write, iclass 5, count 2 2006.203.08:13:19.73#ibcon#*before return 0, iclass 5, count 2 2006.203.08:13:19.73#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.203.08:13:19.73#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.203.08:13:19.73#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.203.08:13:19.73#ibcon#ireg 7 cls_cnt 0 2006.203.08:13:19.73#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.203.08:13:19.85#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.203.08:13:19.85#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.203.08:13:19.85#ibcon#enter wrdev, iclass 5, count 0 2006.203.08:13:19.85#ibcon#first serial, iclass 5, count 0 2006.203.08:13:19.85#ibcon#enter sib2, iclass 5, count 0 2006.203.08:13:19.85#ibcon#flushed, iclass 5, count 0 2006.203.08:13:19.85#ibcon#about to write, iclass 5, count 0 2006.203.08:13:19.85#ibcon#wrote, iclass 5, count 0 2006.203.08:13:19.85#ibcon#about to read 3, iclass 5, count 0 2006.203.08:13:19.87#ibcon#read 3, iclass 5, count 0 2006.203.08:13:19.87#ibcon#about to read 4, iclass 5, count 0 2006.203.08:13:19.87#ibcon#read 4, iclass 5, count 0 2006.203.08:13:19.87#ibcon#about to read 5, iclass 5, count 0 2006.203.08:13:19.87#ibcon#read 5, iclass 5, count 0 2006.203.08:13:19.87#ibcon#about to read 6, iclass 5, count 0 2006.203.08:13:19.87#ibcon#read 6, iclass 5, count 0 2006.203.08:13:19.87#ibcon#end of sib2, iclass 5, count 0 2006.203.08:13:19.87#ibcon#*mode == 0, iclass 5, count 0 2006.203.08:13:19.87#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.203.08:13:19.87#ibcon#[25=USB\r\n] 2006.203.08:13:19.87#ibcon#*before write, iclass 5, count 0 2006.203.08:13:19.87#ibcon#enter sib2, iclass 5, count 0 2006.203.08:13:19.87#ibcon#flushed, iclass 5, count 0 2006.203.08:13:19.87#ibcon#about to write, iclass 5, count 0 2006.203.08:13:19.87#ibcon#wrote, iclass 5, count 0 2006.203.08:13:19.87#ibcon#about to read 3, iclass 5, count 0 2006.203.08:13:19.90#ibcon#read 3, iclass 5, count 0 2006.203.08:13:19.90#ibcon#about to read 4, iclass 5, count 0 2006.203.08:13:19.90#ibcon#read 4, iclass 5, count 0 2006.203.08:13:19.90#ibcon#about to read 5, iclass 5, count 0 2006.203.08:13:19.90#ibcon#read 5, iclass 5, count 0 2006.203.08:13:19.90#ibcon#about to read 6, iclass 5, count 0 2006.203.08:13:19.90#ibcon#read 6, iclass 5, count 0 2006.203.08:13:19.90#ibcon#end of sib2, iclass 5, count 0 2006.203.08:13:19.90#ibcon#*after write, iclass 5, count 0 2006.203.08:13:19.90#ibcon#*before return 0, iclass 5, count 0 2006.203.08:13:19.90#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.203.08:13:19.90#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.203.08:13:19.90#ibcon#about to clear, iclass 5 cls_cnt 0 2006.203.08:13:19.90#ibcon#cleared, iclass 5 cls_cnt 0 2006.203.08:13:19.90$vc4f8/valo=4,832.99 2006.203.08:13:19.90#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.203.08:13:19.90#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.203.08:13:19.90#ibcon#ireg 17 cls_cnt 0 2006.203.08:13:19.90#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.203.08:13:19.90#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.203.08:13:19.90#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.203.08:13:19.90#ibcon#enter wrdev, iclass 7, count 0 2006.203.08:13:19.90#ibcon#first serial, iclass 7, count 0 2006.203.08:13:19.90#ibcon#enter sib2, iclass 7, count 0 2006.203.08:13:19.91#ibcon#flushed, iclass 7, count 0 2006.203.08:13:19.91#ibcon#about to write, iclass 7, count 0 2006.203.08:13:19.91#ibcon#wrote, iclass 7, count 0 2006.203.08:13:19.91#ibcon#about to read 3, iclass 7, count 0 2006.203.08:13:19.92#ibcon#read 3, iclass 7, count 0 2006.203.08:13:19.92#ibcon#about to read 4, iclass 7, count 0 2006.203.08:13:19.92#ibcon#read 4, iclass 7, count 0 2006.203.08:13:19.92#ibcon#about to read 5, iclass 7, count 0 2006.203.08:13:19.92#ibcon#read 5, iclass 7, count 0 2006.203.08:13:19.92#ibcon#about to read 6, iclass 7, count 0 2006.203.08:13:19.92#ibcon#read 6, iclass 7, count 0 2006.203.08:13:19.92#ibcon#end of sib2, iclass 7, count 0 2006.203.08:13:19.92#ibcon#*mode == 0, iclass 7, count 0 2006.203.08:13:19.92#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.203.08:13:19.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.203.08:13:19.92#ibcon#*before write, iclass 7, count 0 2006.203.08:13:19.92#ibcon#enter sib2, iclass 7, count 0 2006.203.08:13:19.92#ibcon#flushed, iclass 7, count 0 2006.203.08:13:19.92#ibcon#about to write, iclass 7, count 0 2006.203.08:13:19.92#ibcon#wrote, iclass 7, count 0 2006.203.08:13:19.92#ibcon#about to read 3, iclass 7, count 0 2006.203.08:13:19.96#ibcon#read 3, iclass 7, count 0 2006.203.08:13:19.96#ibcon#about to read 4, iclass 7, count 0 2006.203.08:13:19.96#ibcon#read 4, iclass 7, count 0 2006.203.08:13:19.96#ibcon#about to read 5, iclass 7, count 0 2006.203.08:13:19.96#ibcon#read 5, iclass 7, count 0 2006.203.08:13:19.96#ibcon#about to read 6, iclass 7, count 0 2006.203.08:13:19.96#ibcon#read 6, iclass 7, count 0 2006.203.08:13:19.96#ibcon#end of sib2, iclass 7, count 0 2006.203.08:13:19.96#ibcon#*after write, iclass 7, count 0 2006.203.08:13:19.96#ibcon#*before return 0, iclass 7, count 0 2006.203.08:13:19.96#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.203.08:13:19.96#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.203.08:13:19.96#ibcon#about to clear, iclass 7 cls_cnt 0 2006.203.08:13:19.96#ibcon#cleared, iclass 7 cls_cnt 0 2006.203.08:13:19.96$vc4f8/va=4,7 2006.203.08:13:19.96#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.203.08:13:19.96#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.203.08:13:19.96#ibcon#ireg 11 cls_cnt 2 2006.203.08:13:19.96#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.203.08:13:20.02#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.203.08:13:20.02#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.203.08:13:20.02#ibcon#enter wrdev, iclass 11, count 2 2006.203.08:13:20.02#ibcon#first serial, iclass 11, count 2 2006.203.08:13:20.02#ibcon#enter sib2, iclass 11, count 2 2006.203.08:13:20.02#ibcon#flushed, iclass 11, count 2 2006.203.08:13:20.02#ibcon#about to write, iclass 11, count 2 2006.203.08:13:20.02#ibcon#wrote, iclass 11, count 2 2006.203.08:13:20.02#ibcon#about to read 3, iclass 11, count 2 2006.203.08:13:20.04#ibcon#read 3, iclass 11, count 2 2006.203.08:13:20.04#ibcon#about to read 4, iclass 11, count 2 2006.203.08:13:20.04#ibcon#read 4, iclass 11, count 2 2006.203.08:13:20.04#ibcon#about to read 5, iclass 11, count 2 2006.203.08:13:20.04#ibcon#read 5, iclass 11, count 2 2006.203.08:13:20.04#ibcon#about to read 6, iclass 11, count 2 2006.203.08:13:20.04#ibcon#read 6, iclass 11, count 2 2006.203.08:13:20.04#ibcon#end of sib2, iclass 11, count 2 2006.203.08:13:20.04#ibcon#*mode == 0, iclass 11, count 2 2006.203.08:13:20.04#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.203.08:13:20.04#ibcon#[25=AT04-07\r\n] 2006.203.08:13:20.04#ibcon#*before write, iclass 11, count 2 2006.203.08:13:20.04#ibcon#enter sib2, iclass 11, count 2 2006.203.08:13:20.04#ibcon#flushed, iclass 11, count 2 2006.203.08:13:20.04#ibcon#about to write, iclass 11, count 2 2006.203.08:13:20.04#ibcon#wrote, iclass 11, count 2 2006.203.08:13:20.04#ibcon#about to read 3, iclass 11, count 2 2006.203.08:13:20.07#ibcon#read 3, iclass 11, count 2 2006.203.08:13:20.07#ibcon#about to read 4, iclass 11, count 2 2006.203.08:13:20.07#ibcon#read 4, iclass 11, count 2 2006.203.08:13:20.07#ibcon#about to read 5, iclass 11, count 2 2006.203.08:13:20.07#ibcon#read 5, iclass 11, count 2 2006.203.08:13:20.07#ibcon#about to read 6, iclass 11, count 2 2006.203.08:13:20.07#ibcon#read 6, iclass 11, count 2 2006.203.08:13:20.07#ibcon#end of sib2, iclass 11, count 2 2006.203.08:13:20.07#ibcon#*after write, iclass 11, count 2 2006.203.08:13:20.07#ibcon#*before return 0, iclass 11, count 2 2006.203.08:13:20.07#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.203.08:13:20.07#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.203.08:13:20.07#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.203.08:13:20.07#ibcon#ireg 7 cls_cnt 0 2006.203.08:13:20.07#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.203.08:13:20.19#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.203.08:13:20.19#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.203.08:13:20.19#ibcon#enter wrdev, iclass 11, count 0 2006.203.08:13:20.19#ibcon#first serial, iclass 11, count 0 2006.203.08:13:20.19#ibcon#enter sib2, iclass 11, count 0 2006.203.08:13:20.19#ibcon#flushed, iclass 11, count 0 2006.203.08:13:20.19#ibcon#about to write, iclass 11, count 0 2006.203.08:13:20.19#ibcon#wrote, iclass 11, count 0 2006.203.08:13:20.19#ibcon#about to read 3, iclass 11, count 0 2006.203.08:13:20.21#ibcon#read 3, iclass 11, count 0 2006.203.08:13:20.21#ibcon#about to read 4, iclass 11, count 0 2006.203.08:13:20.21#ibcon#read 4, iclass 11, count 0 2006.203.08:13:20.21#ibcon#about to read 5, iclass 11, count 0 2006.203.08:13:20.21#ibcon#read 5, iclass 11, count 0 2006.203.08:13:20.21#ibcon#about to read 6, iclass 11, count 0 2006.203.08:13:20.21#ibcon#read 6, iclass 11, count 0 2006.203.08:13:20.21#ibcon#end of sib2, iclass 11, count 0 2006.203.08:13:20.21#ibcon#*mode == 0, iclass 11, count 0 2006.203.08:13:20.21#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.203.08:13:20.21#ibcon#[25=USB\r\n] 2006.203.08:13:20.21#ibcon#*before write, iclass 11, count 0 2006.203.08:13:20.21#ibcon#enter sib2, iclass 11, count 0 2006.203.08:13:20.21#ibcon#flushed, iclass 11, count 0 2006.203.08:13:20.21#ibcon#about to write, iclass 11, count 0 2006.203.08:13:20.21#ibcon#wrote, iclass 11, count 0 2006.203.08:13:20.21#ibcon#about to read 3, iclass 11, count 0 2006.203.08:13:20.24#ibcon#read 3, iclass 11, count 0 2006.203.08:13:20.24#ibcon#about to read 4, iclass 11, count 0 2006.203.08:13:20.24#ibcon#read 4, iclass 11, count 0 2006.203.08:13:20.24#ibcon#about to read 5, iclass 11, count 0 2006.203.08:13:20.24#ibcon#read 5, iclass 11, count 0 2006.203.08:13:20.24#ibcon#about to read 6, iclass 11, count 0 2006.203.08:13:20.24#ibcon#read 6, iclass 11, count 0 2006.203.08:13:20.24#ibcon#end of sib2, iclass 11, count 0 2006.203.08:13:20.24#ibcon#*after write, iclass 11, count 0 2006.203.08:13:20.24#ibcon#*before return 0, iclass 11, count 0 2006.203.08:13:20.24#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.203.08:13:20.24#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.203.08:13:20.24#ibcon#about to clear, iclass 11 cls_cnt 0 2006.203.08:13:20.24#ibcon#cleared, iclass 11 cls_cnt 0 2006.203.08:13:20.24$vc4f8/valo=5,652.99 2006.203.08:13:20.24#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.203.08:13:20.24#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.203.08:13:20.24#ibcon#ireg 17 cls_cnt 0 2006.203.08:13:20.24#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.203.08:13:20.24#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.203.08:13:20.24#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.203.08:13:20.24#ibcon#enter wrdev, iclass 13, count 0 2006.203.08:13:20.24#ibcon#first serial, iclass 13, count 0 2006.203.08:13:20.24#ibcon#enter sib2, iclass 13, count 0 2006.203.08:13:20.24#ibcon#flushed, iclass 13, count 0 2006.203.08:13:20.24#ibcon#about to write, iclass 13, count 0 2006.203.08:13:20.24#ibcon#wrote, iclass 13, count 0 2006.203.08:13:20.24#ibcon#about to read 3, iclass 13, count 0 2006.203.08:13:20.26#ibcon#read 3, iclass 13, count 0 2006.203.08:13:20.26#ibcon#about to read 4, iclass 13, count 0 2006.203.08:13:20.26#ibcon#read 4, iclass 13, count 0 2006.203.08:13:20.26#ibcon#about to read 5, iclass 13, count 0 2006.203.08:13:20.26#ibcon#read 5, iclass 13, count 0 2006.203.08:13:20.26#ibcon#about to read 6, iclass 13, count 0 2006.203.08:13:20.26#ibcon#read 6, iclass 13, count 0 2006.203.08:13:20.26#ibcon#end of sib2, iclass 13, count 0 2006.203.08:13:20.26#ibcon#*mode == 0, iclass 13, count 0 2006.203.08:13:20.26#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.203.08:13:20.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.203.08:13:20.26#ibcon#*before write, iclass 13, count 0 2006.203.08:13:20.26#ibcon#enter sib2, iclass 13, count 0 2006.203.08:13:20.26#ibcon#flushed, iclass 13, count 0 2006.203.08:13:20.26#ibcon#about to write, iclass 13, count 0 2006.203.08:13:20.26#ibcon#wrote, iclass 13, count 0 2006.203.08:13:20.26#ibcon#about to read 3, iclass 13, count 0 2006.203.08:13:20.30#ibcon#read 3, iclass 13, count 0 2006.203.08:13:20.30#ibcon#about to read 4, iclass 13, count 0 2006.203.08:13:20.30#ibcon#read 4, iclass 13, count 0 2006.203.08:13:20.30#ibcon#about to read 5, iclass 13, count 0 2006.203.08:13:20.30#ibcon#read 5, iclass 13, count 0 2006.203.08:13:20.30#ibcon#about to read 6, iclass 13, count 0 2006.203.08:13:20.30#ibcon#read 6, iclass 13, count 0 2006.203.08:13:20.30#ibcon#end of sib2, iclass 13, count 0 2006.203.08:13:20.30#ibcon#*after write, iclass 13, count 0 2006.203.08:13:20.30#ibcon#*before return 0, iclass 13, count 0 2006.203.08:13:20.30#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.203.08:13:20.30#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.203.08:13:20.30#ibcon#about to clear, iclass 13 cls_cnt 0 2006.203.08:13:20.30#ibcon#cleared, iclass 13 cls_cnt 0 2006.203.08:13:20.30$vc4f8/va=5,7 2006.203.08:13:20.30#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.203.08:13:20.30#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.203.08:13:20.30#ibcon#ireg 11 cls_cnt 2 2006.203.08:13:20.30#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.203.08:13:20.36#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.203.08:13:20.36#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.203.08:13:20.36#ibcon#enter wrdev, iclass 15, count 2 2006.203.08:13:20.36#ibcon#first serial, iclass 15, count 2 2006.203.08:13:20.36#ibcon#enter sib2, iclass 15, count 2 2006.203.08:13:20.36#ibcon#flushed, iclass 15, count 2 2006.203.08:13:20.36#ibcon#about to write, iclass 15, count 2 2006.203.08:13:20.36#ibcon#wrote, iclass 15, count 2 2006.203.08:13:20.36#ibcon#about to read 3, iclass 15, count 2 2006.203.08:13:20.38#ibcon#read 3, iclass 15, count 2 2006.203.08:13:20.38#ibcon#about to read 4, iclass 15, count 2 2006.203.08:13:20.38#ibcon#read 4, iclass 15, count 2 2006.203.08:13:20.38#ibcon#about to read 5, iclass 15, count 2 2006.203.08:13:20.38#ibcon#read 5, iclass 15, count 2 2006.203.08:13:20.38#ibcon#about to read 6, iclass 15, count 2 2006.203.08:13:20.38#ibcon#read 6, iclass 15, count 2 2006.203.08:13:20.38#ibcon#end of sib2, iclass 15, count 2 2006.203.08:13:20.38#ibcon#*mode == 0, iclass 15, count 2 2006.203.08:13:20.38#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.203.08:13:20.38#ibcon#[25=AT05-07\r\n] 2006.203.08:13:20.38#ibcon#*before write, iclass 15, count 2 2006.203.08:13:20.38#ibcon#enter sib2, iclass 15, count 2 2006.203.08:13:20.38#ibcon#flushed, iclass 15, count 2 2006.203.08:13:20.38#ibcon#about to write, iclass 15, count 2 2006.203.08:13:20.38#ibcon#wrote, iclass 15, count 2 2006.203.08:13:20.38#ibcon#about to read 3, iclass 15, count 2 2006.203.08:13:20.41#ibcon#read 3, iclass 15, count 2 2006.203.08:13:20.41#ibcon#about to read 4, iclass 15, count 2 2006.203.08:13:20.41#ibcon#read 4, iclass 15, count 2 2006.203.08:13:20.41#ibcon#about to read 5, iclass 15, count 2 2006.203.08:13:20.41#ibcon#read 5, iclass 15, count 2 2006.203.08:13:20.41#ibcon#about to read 6, iclass 15, count 2 2006.203.08:13:20.41#ibcon#read 6, iclass 15, count 2 2006.203.08:13:20.41#ibcon#end of sib2, iclass 15, count 2 2006.203.08:13:20.41#ibcon#*after write, iclass 15, count 2 2006.203.08:13:20.41#ibcon#*before return 0, iclass 15, count 2 2006.203.08:13:20.41#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.203.08:13:20.41#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.203.08:13:20.41#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.203.08:13:20.41#ibcon#ireg 7 cls_cnt 0 2006.203.08:13:20.41#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.203.08:13:20.53#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.203.08:13:20.53#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.203.08:13:20.53#ibcon#enter wrdev, iclass 15, count 0 2006.203.08:13:20.53#ibcon#first serial, iclass 15, count 0 2006.203.08:13:20.53#ibcon#enter sib2, iclass 15, count 0 2006.203.08:13:20.53#ibcon#flushed, iclass 15, count 0 2006.203.08:13:20.53#ibcon#about to write, iclass 15, count 0 2006.203.08:13:20.53#ibcon#wrote, iclass 15, count 0 2006.203.08:13:20.53#ibcon#about to read 3, iclass 15, count 0 2006.203.08:13:20.55#ibcon#read 3, iclass 15, count 0 2006.203.08:13:20.55#ibcon#about to read 4, iclass 15, count 0 2006.203.08:13:20.55#ibcon#read 4, iclass 15, count 0 2006.203.08:13:20.55#ibcon#about to read 5, iclass 15, count 0 2006.203.08:13:20.55#ibcon#read 5, iclass 15, count 0 2006.203.08:13:20.55#ibcon#about to read 6, iclass 15, count 0 2006.203.08:13:20.55#ibcon#read 6, iclass 15, count 0 2006.203.08:13:20.55#ibcon#end of sib2, iclass 15, count 0 2006.203.08:13:20.55#ibcon#*mode == 0, iclass 15, count 0 2006.203.08:13:20.55#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.203.08:13:20.55#ibcon#[25=USB\r\n] 2006.203.08:13:20.55#ibcon#*before write, iclass 15, count 0 2006.203.08:13:20.55#ibcon#enter sib2, iclass 15, count 0 2006.203.08:13:20.55#ibcon#flushed, iclass 15, count 0 2006.203.08:13:20.55#ibcon#about to write, iclass 15, count 0 2006.203.08:13:20.55#ibcon#wrote, iclass 15, count 0 2006.203.08:13:20.55#ibcon#about to read 3, iclass 15, count 0 2006.203.08:13:20.58#ibcon#read 3, iclass 15, count 0 2006.203.08:13:20.58#ibcon#about to read 4, iclass 15, count 0 2006.203.08:13:20.58#ibcon#read 4, iclass 15, count 0 2006.203.08:13:20.58#ibcon#about to read 5, iclass 15, count 0 2006.203.08:13:20.58#ibcon#read 5, iclass 15, count 0 2006.203.08:13:20.58#ibcon#about to read 6, iclass 15, count 0 2006.203.08:13:20.58#ibcon#read 6, iclass 15, count 0 2006.203.08:13:20.58#ibcon#end of sib2, iclass 15, count 0 2006.203.08:13:20.58#ibcon#*after write, iclass 15, count 0 2006.203.08:13:20.58#ibcon#*before return 0, iclass 15, count 0 2006.203.08:13:20.58#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.203.08:13:20.58#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.203.08:13:20.58#ibcon#about to clear, iclass 15 cls_cnt 0 2006.203.08:13:20.58#ibcon#cleared, iclass 15 cls_cnt 0 2006.203.08:13:20.58$vc4f8/valo=6,772.99 2006.203.08:13:20.58#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.203.08:13:20.58#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.203.08:13:20.58#ibcon#ireg 17 cls_cnt 0 2006.203.08:13:20.58#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.203.08:13:20.58#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.203.08:13:20.58#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.203.08:13:20.58#ibcon#enter wrdev, iclass 17, count 0 2006.203.08:13:20.58#ibcon#first serial, iclass 17, count 0 2006.203.08:13:20.58#ibcon#enter sib2, iclass 17, count 0 2006.203.08:13:20.58#ibcon#flushed, iclass 17, count 0 2006.203.08:13:20.58#ibcon#about to write, iclass 17, count 0 2006.203.08:13:20.58#ibcon#wrote, iclass 17, count 0 2006.203.08:13:20.58#ibcon#about to read 3, iclass 17, count 0 2006.203.08:13:20.61#ibcon#read 3, iclass 17, count 0 2006.203.08:13:20.61#ibcon#about to read 4, iclass 17, count 0 2006.203.08:13:20.61#ibcon#read 4, iclass 17, count 0 2006.203.08:13:20.61#ibcon#about to read 5, iclass 17, count 0 2006.203.08:13:20.61#ibcon#read 5, iclass 17, count 0 2006.203.08:13:20.61#ibcon#about to read 6, iclass 17, count 0 2006.203.08:13:20.61#ibcon#read 6, iclass 17, count 0 2006.203.08:13:20.61#ibcon#end of sib2, iclass 17, count 0 2006.203.08:13:20.61#ibcon#*mode == 0, iclass 17, count 0 2006.203.08:13:20.61#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.203.08:13:20.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.203.08:13:20.61#ibcon#*before write, iclass 17, count 0 2006.203.08:13:20.61#ibcon#enter sib2, iclass 17, count 0 2006.203.08:13:20.61#ibcon#flushed, iclass 17, count 0 2006.203.08:13:20.61#ibcon#about to write, iclass 17, count 0 2006.203.08:13:20.61#ibcon#wrote, iclass 17, count 0 2006.203.08:13:20.61#ibcon#about to read 3, iclass 17, count 0 2006.203.08:13:20.65#ibcon#read 3, iclass 17, count 0 2006.203.08:13:20.65#ibcon#about to read 4, iclass 17, count 0 2006.203.08:13:20.65#ibcon#read 4, iclass 17, count 0 2006.203.08:13:20.65#ibcon#about to read 5, iclass 17, count 0 2006.203.08:13:20.65#ibcon#read 5, iclass 17, count 0 2006.203.08:13:20.65#ibcon#about to read 6, iclass 17, count 0 2006.203.08:13:20.65#ibcon#read 6, iclass 17, count 0 2006.203.08:13:20.65#ibcon#end of sib2, iclass 17, count 0 2006.203.08:13:20.65#ibcon#*after write, iclass 17, count 0 2006.203.08:13:20.65#ibcon#*before return 0, iclass 17, count 0 2006.203.08:13:20.65#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.203.08:13:20.65#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.203.08:13:20.65#ibcon#about to clear, iclass 17 cls_cnt 0 2006.203.08:13:20.65#ibcon#cleared, iclass 17 cls_cnt 0 2006.203.08:13:20.65$vc4f8/va=6,6 2006.203.08:13:20.65#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.203.08:13:20.65#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.203.08:13:20.65#ibcon#ireg 11 cls_cnt 2 2006.203.08:13:20.65#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.203.08:13:20.70#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.203.08:13:20.70#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.203.08:13:20.70#ibcon#enter wrdev, iclass 19, count 2 2006.203.08:13:20.70#ibcon#first serial, iclass 19, count 2 2006.203.08:13:20.70#ibcon#enter sib2, iclass 19, count 2 2006.203.08:13:20.70#ibcon#flushed, iclass 19, count 2 2006.203.08:13:20.70#ibcon#about to write, iclass 19, count 2 2006.203.08:13:20.70#ibcon#wrote, iclass 19, count 2 2006.203.08:13:20.70#ibcon#about to read 3, iclass 19, count 2 2006.203.08:13:20.72#ibcon#read 3, iclass 19, count 2 2006.203.08:13:20.72#ibcon#about to read 4, iclass 19, count 2 2006.203.08:13:20.72#ibcon#read 4, iclass 19, count 2 2006.203.08:13:20.72#ibcon#about to read 5, iclass 19, count 2 2006.203.08:13:20.72#ibcon#read 5, iclass 19, count 2 2006.203.08:13:20.72#ibcon#about to read 6, iclass 19, count 2 2006.203.08:13:20.72#ibcon#read 6, iclass 19, count 2 2006.203.08:13:20.72#ibcon#end of sib2, iclass 19, count 2 2006.203.08:13:20.72#ibcon#*mode == 0, iclass 19, count 2 2006.203.08:13:20.72#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.203.08:13:20.72#ibcon#[25=AT06-06\r\n] 2006.203.08:13:20.72#ibcon#*before write, iclass 19, count 2 2006.203.08:13:20.72#ibcon#enter sib2, iclass 19, count 2 2006.203.08:13:20.72#ibcon#flushed, iclass 19, count 2 2006.203.08:13:20.72#ibcon#about to write, iclass 19, count 2 2006.203.08:13:20.72#ibcon#wrote, iclass 19, count 2 2006.203.08:13:20.72#ibcon#about to read 3, iclass 19, count 2 2006.203.08:13:20.75#ibcon#read 3, iclass 19, count 2 2006.203.08:13:20.75#ibcon#about to read 4, iclass 19, count 2 2006.203.08:13:20.75#ibcon#read 4, iclass 19, count 2 2006.203.08:13:20.75#ibcon#about to read 5, iclass 19, count 2 2006.203.08:13:20.75#ibcon#read 5, iclass 19, count 2 2006.203.08:13:20.75#ibcon#about to read 6, iclass 19, count 2 2006.203.08:13:20.75#ibcon#read 6, iclass 19, count 2 2006.203.08:13:20.75#ibcon#end of sib2, iclass 19, count 2 2006.203.08:13:20.75#ibcon#*after write, iclass 19, count 2 2006.203.08:13:20.75#ibcon#*before return 0, iclass 19, count 2 2006.203.08:13:20.75#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.203.08:13:20.75#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.203.08:13:20.75#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.203.08:13:20.75#ibcon#ireg 7 cls_cnt 0 2006.203.08:13:20.75#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.203.08:13:20.87#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.203.08:13:20.87#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.203.08:13:20.87#ibcon#enter wrdev, iclass 19, count 0 2006.203.08:13:20.87#ibcon#first serial, iclass 19, count 0 2006.203.08:13:20.87#ibcon#enter sib2, iclass 19, count 0 2006.203.08:13:20.87#ibcon#flushed, iclass 19, count 0 2006.203.08:13:20.87#ibcon#about to write, iclass 19, count 0 2006.203.08:13:20.87#ibcon#wrote, iclass 19, count 0 2006.203.08:13:20.87#ibcon#about to read 3, iclass 19, count 0 2006.203.08:13:20.89#ibcon#read 3, iclass 19, count 0 2006.203.08:13:20.89#ibcon#about to read 4, iclass 19, count 0 2006.203.08:13:20.89#ibcon#read 4, iclass 19, count 0 2006.203.08:13:20.89#ibcon#about to read 5, iclass 19, count 0 2006.203.08:13:20.89#ibcon#read 5, iclass 19, count 0 2006.203.08:13:20.89#ibcon#about to read 6, iclass 19, count 0 2006.203.08:13:20.89#ibcon#read 6, iclass 19, count 0 2006.203.08:13:20.89#ibcon#end of sib2, iclass 19, count 0 2006.203.08:13:20.89#ibcon#*mode == 0, iclass 19, count 0 2006.203.08:13:20.89#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.203.08:13:20.89#ibcon#[25=USB\r\n] 2006.203.08:13:20.89#ibcon#*before write, iclass 19, count 0 2006.203.08:13:20.89#ibcon#enter sib2, iclass 19, count 0 2006.203.08:13:20.89#ibcon#flushed, iclass 19, count 0 2006.203.08:13:20.89#ibcon#about to write, iclass 19, count 0 2006.203.08:13:20.89#ibcon#wrote, iclass 19, count 0 2006.203.08:13:20.89#ibcon#about to read 3, iclass 19, count 0 2006.203.08:13:20.92#ibcon#read 3, iclass 19, count 0 2006.203.08:13:20.92#ibcon#about to read 4, iclass 19, count 0 2006.203.08:13:20.92#ibcon#read 4, iclass 19, count 0 2006.203.08:13:20.92#ibcon#about to read 5, iclass 19, count 0 2006.203.08:13:20.92#ibcon#read 5, iclass 19, count 0 2006.203.08:13:20.92#ibcon#about to read 6, iclass 19, count 0 2006.203.08:13:20.92#ibcon#read 6, iclass 19, count 0 2006.203.08:13:20.92#ibcon#end of sib2, iclass 19, count 0 2006.203.08:13:20.92#ibcon#*after write, iclass 19, count 0 2006.203.08:13:20.92#ibcon#*before return 0, iclass 19, count 0 2006.203.08:13:20.92#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.203.08:13:20.92#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.203.08:13:20.92#ibcon#about to clear, iclass 19 cls_cnt 0 2006.203.08:13:20.92#ibcon#cleared, iclass 19 cls_cnt 0 2006.203.08:13:20.92$vc4f8/valo=7,832.99 2006.203.08:13:20.92#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.203.08:13:20.92#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.203.08:13:20.92#ibcon#ireg 17 cls_cnt 0 2006.203.08:13:20.92#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.203.08:13:20.92#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.203.08:13:20.92#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.203.08:13:20.92#ibcon#enter wrdev, iclass 21, count 0 2006.203.08:13:20.92#ibcon#first serial, iclass 21, count 0 2006.203.08:13:20.92#ibcon#enter sib2, iclass 21, count 0 2006.203.08:13:20.92#ibcon#flushed, iclass 21, count 0 2006.203.08:13:20.92#ibcon#about to write, iclass 21, count 0 2006.203.08:13:20.92#ibcon#wrote, iclass 21, count 0 2006.203.08:13:20.92#ibcon#about to read 3, iclass 21, count 0 2006.203.08:13:20.94#ibcon#read 3, iclass 21, count 0 2006.203.08:13:20.94#ibcon#about to read 4, iclass 21, count 0 2006.203.08:13:20.94#ibcon#read 4, iclass 21, count 0 2006.203.08:13:20.94#ibcon#about to read 5, iclass 21, count 0 2006.203.08:13:20.94#ibcon#read 5, iclass 21, count 0 2006.203.08:13:20.94#ibcon#about to read 6, iclass 21, count 0 2006.203.08:13:20.94#ibcon#read 6, iclass 21, count 0 2006.203.08:13:20.94#ibcon#end of sib2, iclass 21, count 0 2006.203.08:13:20.94#ibcon#*mode == 0, iclass 21, count 0 2006.203.08:13:20.94#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.203.08:13:20.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.203.08:13:20.94#ibcon#*before write, iclass 21, count 0 2006.203.08:13:20.94#ibcon#enter sib2, iclass 21, count 0 2006.203.08:13:20.94#ibcon#flushed, iclass 21, count 0 2006.203.08:13:20.94#ibcon#about to write, iclass 21, count 0 2006.203.08:13:20.94#ibcon#wrote, iclass 21, count 0 2006.203.08:13:20.94#ibcon#about to read 3, iclass 21, count 0 2006.203.08:13:20.98#ibcon#read 3, iclass 21, count 0 2006.203.08:13:20.98#ibcon#about to read 4, iclass 21, count 0 2006.203.08:13:20.98#ibcon#read 4, iclass 21, count 0 2006.203.08:13:20.98#ibcon#about to read 5, iclass 21, count 0 2006.203.08:13:20.98#ibcon#read 5, iclass 21, count 0 2006.203.08:13:20.98#ibcon#about to read 6, iclass 21, count 0 2006.203.08:13:20.98#ibcon#read 6, iclass 21, count 0 2006.203.08:13:20.98#ibcon#end of sib2, iclass 21, count 0 2006.203.08:13:20.98#ibcon#*after write, iclass 21, count 0 2006.203.08:13:20.98#ibcon#*before return 0, iclass 21, count 0 2006.203.08:13:20.98#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.203.08:13:20.98#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.203.08:13:20.98#ibcon#about to clear, iclass 21 cls_cnt 0 2006.203.08:13:20.98#ibcon#cleared, iclass 21 cls_cnt 0 2006.203.08:13:20.98$vc4f8/va=7,7 2006.203.08:13:20.98#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.203.08:13:20.98#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.203.08:13:20.98#ibcon#ireg 11 cls_cnt 2 2006.203.08:13:20.98#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.203.08:13:21.04#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.203.08:13:21.04#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.203.08:13:21.04#ibcon#enter wrdev, iclass 23, count 2 2006.203.08:13:21.04#ibcon#first serial, iclass 23, count 2 2006.203.08:13:21.04#ibcon#enter sib2, iclass 23, count 2 2006.203.08:13:21.04#ibcon#flushed, iclass 23, count 2 2006.203.08:13:21.04#ibcon#about to write, iclass 23, count 2 2006.203.08:13:21.04#ibcon#wrote, iclass 23, count 2 2006.203.08:13:21.04#ibcon#about to read 3, iclass 23, count 2 2006.203.08:13:21.06#ibcon#read 3, iclass 23, count 2 2006.203.08:13:21.06#ibcon#about to read 4, iclass 23, count 2 2006.203.08:13:21.06#ibcon#read 4, iclass 23, count 2 2006.203.08:13:21.06#ibcon#about to read 5, iclass 23, count 2 2006.203.08:13:21.06#ibcon#read 5, iclass 23, count 2 2006.203.08:13:21.06#ibcon#about to read 6, iclass 23, count 2 2006.203.08:13:21.06#ibcon#read 6, iclass 23, count 2 2006.203.08:13:21.06#ibcon#end of sib2, iclass 23, count 2 2006.203.08:13:21.06#ibcon#*mode == 0, iclass 23, count 2 2006.203.08:13:21.06#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.203.08:13:21.06#ibcon#[25=AT07-07\r\n] 2006.203.08:13:21.06#ibcon#*before write, iclass 23, count 2 2006.203.08:13:21.06#ibcon#enter sib2, iclass 23, count 2 2006.203.08:13:21.06#ibcon#flushed, iclass 23, count 2 2006.203.08:13:21.06#ibcon#about to write, iclass 23, count 2 2006.203.08:13:21.06#ibcon#wrote, iclass 23, count 2 2006.203.08:13:21.06#ibcon#about to read 3, iclass 23, count 2 2006.203.08:13:21.09#ibcon#read 3, iclass 23, count 2 2006.203.08:13:21.09#ibcon#about to read 4, iclass 23, count 2 2006.203.08:13:21.09#ibcon#read 4, iclass 23, count 2 2006.203.08:13:21.09#ibcon#about to read 5, iclass 23, count 2 2006.203.08:13:21.09#ibcon#read 5, iclass 23, count 2 2006.203.08:13:21.09#ibcon#about to read 6, iclass 23, count 2 2006.203.08:13:21.09#ibcon#read 6, iclass 23, count 2 2006.203.08:13:21.09#ibcon#end of sib2, iclass 23, count 2 2006.203.08:13:21.09#ibcon#*after write, iclass 23, count 2 2006.203.08:13:21.09#ibcon#*before return 0, iclass 23, count 2 2006.203.08:13:21.09#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.203.08:13:21.09#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.203.08:13:21.09#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.203.08:13:21.09#ibcon#ireg 7 cls_cnt 0 2006.203.08:13:21.09#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.203.08:13:21.21#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.203.08:13:21.21#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.203.08:13:21.21#ibcon#enter wrdev, iclass 23, count 0 2006.203.08:13:21.21#ibcon#first serial, iclass 23, count 0 2006.203.08:13:21.21#ibcon#enter sib2, iclass 23, count 0 2006.203.08:13:21.21#ibcon#flushed, iclass 23, count 0 2006.203.08:13:21.21#ibcon#about to write, iclass 23, count 0 2006.203.08:13:21.21#ibcon#wrote, iclass 23, count 0 2006.203.08:13:21.21#ibcon#about to read 3, iclass 23, count 0 2006.203.08:13:21.25#ibcon#read 3, iclass 23, count 0 2006.203.08:13:21.25#ibcon#about to read 4, iclass 23, count 0 2006.203.08:13:21.25#ibcon#read 4, iclass 23, count 0 2006.203.08:13:21.25#ibcon#about to read 5, iclass 23, count 0 2006.203.08:13:21.25#ibcon#read 5, iclass 23, count 0 2006.203.08:13:21.25#ibcon#about to read 6, iclass 23, count 0 2006.203.08:13:21.25#ibcon#read 6, iclass 23, count 0 2006.203.08:13:21.25#ibcon#end of sib2, iclass 23, count 0 2006.203.08:13:21.25#ibcon#*mode == 0, iclass 23, count 0 2006.203.08:13:21.25#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.203.08:13:21.25#ibcon#[25=USB\r\n] 2006.203.08:13:21.25#ibcon#*before write, iclass 23, count 0 2006.203.08:13:21.25#ibcon#enter sib2, iclass 23, count 0 2006.203.08:13:21.25#ibcon#flushed, iclass 23, count 0 2006.203.08:13:21.25#ibcon#about to write, iclass 23, count 0 2006.203.08:13:21.25#ibcon#wrote, iclass 23, count 0 2006.203.08:13:21.25#ibcon#about to read 3, iclass 23, count 0 2006.203.08:13:21.28#ibcon#read 3, iclass 23, count 0 2006.203.08:13:21.28#ibcon#about to read 4, iclass 23, count 0 2006.203.08:13:21.28#ibcon#read 4, iclass 23, count 0 2006.203.08:13:21.28#ibcon#about to read 5, iclass 23, count 0 2006.203.08:13:21.28#ibcon#read 5, iclass 23, count 0 2006.203.08:13:21.28#ibcon#about to read 6, iclass 23, count 0 2006.203.08:13:21.28#ibcon#read 6, iclass 23, count 0 2006.203.08:13:21.28#ibcon#end of sib2, iclass 23, count 0 2006.203.08:13:21.28#ibcon#*after write, iclass 23, count 0 2006.203.08:13:21.28#ibcon#*before return 0, iclass 23, count 0 2006.203.08:13:21.28#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.203.08:13:21.28#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.203.08:13:21.28#ibcon#about to clear, iclass 23 cls_cnt 0 2006.203.08:13:21.28#ibcon#cleared, iclass 23 cls_cnt 0 2006.203.08:13:21.28$vc4f8/valo=8,852.99 2006.203.08:13:21.28#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.203.08:13:21.28#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.203.08:13:21.28#ibcon#ireg 17 cls_cnt 0 2006.203.08:13:21.28#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.203.08:13:21.28#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.203.08:13:21.28#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.203.08:13:21.28#ibcon#enter wrdev, iclass 25, count 0 2006.203.08:13:21.28#ibcon#first serial, iclass 25, count 0 2006.203.08:13:21.28#ibcon#enter sib2, iclass 25, count 0 2006.203.08:13:21.28#ibcon#flushed, iclass 25, count 0 2006.203.08:13:21.28#ibcon#about to write, iclass 25, count 0 2006.203.08:13:21.28#ibcon#wrote, iclass 25, count 0 2006.203.08:13:21.28#ibcon#about to read 3, iclass 25, count 0 2006.203.08:13:21.30#ibcon#read 3, iclass 25, count 0 2006.203.08:13:21.30#ibcon#about to read 4, iclass 25, count 0 2006.203.08:13:21.30#ibcon#read 4, iclass 25, count 0 2006.203.08:13:21.31#ibcon#about to read 5, iclass 25, count 0 2006.203.08:13:21.31#ibcon#read 5, iclass 25, count 0 2006.203.08:13:21.31#ibcon#about to read 6, iclass 25, count 0 2006.203.08:13:21.31#ibcon#read 6, iclass 25, count 0 2006.203.08:13:21.31#ibcon#end of sib2, iclass 25, count 0 2006.203.08:13:21.31#ibcon#*mode == 0, iclass 25, count 0 2006.203.08:13:21.31#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.203.08:13:21.31#ibcon#[26=FRQ=08,852.99\r\n] 2006.203.08:13:21.31#ibcon#*before write, iclass 25, count 0 2006.203.08:13:21.31#ibcon#enter sib2, iclass 25, count 0 2006.203.08:13:21.31#ibcon#flushed, iclass 25, count 0 2006.203.08:13:21.31#ibcon#about to write, iclass 25, count 0 2006.203.08:13:21.31#ibcon#wrote, iclass 25, count 0 2006.203.08:13:21.31#ibcon#about to read 3, iclass 25, count 0 2006.203.08:13:21.34#ibcon#read 3, iclass 25, count 0 2006.203.08:13:21.34#ibcon#about to read 4, iclass 25, count 0 2006.203.08:13:21.34#ibcon#read 4, iclass 25, count 0 2006.203.08:13:21.34#ibcon#about to read 5, iclass 25, count 0 2006.203.08:13:21.34#ibcon#read 5, iclass 25, count 0 2006.203.08:13:21.34#ibcon#about to read 6, iclass 25, count 0 2006.203.08:13:21.34#ibcon#read 6, iclass 25, count 0 2006.203.08:13:21.34#ibcon#end of sib2, iclass 25, count 0 2006.203.08:13:21.34#ibcon#*after write, iclass 25, count 0 2006.203.08:13:21.34#ibcon#*before return 0, iclass 25, count 0 2006.203.08:13:21.34#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.203.08:13:21.34#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.203.08:13:21.34#ibcon#about to clear, iclass 25 cls_cnt 0 2006.203.08:13:21.34#ibcon#cleared, iclass 25 cls_cnt 0 2006.203.08:13:21.34$vc4f8/va=8,6 2006.203.08:13:21.34#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.203.08:13:21.34#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.203.08:13:21.34#ibcon#ireg 11 cls_cnt 2 2006.203.08:13:21.34#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.203.08:13:21.40#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.203.08:13:21.40#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.203.08:13:21.40#ibcon#enter wrdev, iclass 27, count 2 2006.203.08:13:21.40#ibcon#first serial, iclass 27, count 2 2006.203.08:13:21.40#ibcon#enter sib2, iclass 27, count 2 2006.203.08:13:21.40#ibcon#flushed, iclass 27, count 2 2006.203.08:13:21.40#ibcon#about to write, iclass 27, count 2 2006.203.08:13:21.40#ibcon#wrote, iclass 27, count 2 2006.203.08:13:21.40#ibcon#about to read 3, iclass 27, count 2 2006.203.08:13:21.42#ibcon#read 3, iclass 27, count 2 2006.203.08:13:21.42#ibcon#about to read 4, iclass 27, count 2 2006.203.08:13:21.42#ibcon#read 4, iclass 27, count 2 2006.203.08:13:21.42#ibcon#about to read 5, iclass 27, count 2 2006.203.08:13:21.42#ibcon#read 5, iclass 27, count 2 2006.203.08:13:21.42#ibcon#about to read 6, iclass 27, count 2 2006.203.08:13:21.42#ibcon#read 6, iclass 27, count 2 2006.203.08:13:21.42#ibcon#end of sib2, iclass 27, count 2 2006.203.08:13:21.42#ibcon#*mode == 0, iclass 27, count 2 2006.203.08:13:21.42#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.203.08:13:21.42#ibcon#[25=AT08-06\r\n] 2006.203.08:13:21.42#ibcon#*before write, iclass 27, count 2 2006.203.08:13:21.42#ibcon#enter sib2, iclass 27, count 2 2006.203.08:13:21.42#ibcon#flushed, iclass 27, count 2 2006.203.08:13:21.42#ibcon#about to write, iclass 27, count 2 2006.203.08:13:21.42#ibcon#wrote, iclass 27, count 2 2006.203.08:13:21.42#ibcon#about to read 3, iclass 27, count 2 2006.203.08:13:21.45#ibcon#read 3, iclass 27, count 2 2006.203.08:13:21.45#ibcon#about to read 4, iclass 27, count 2 2006.203.08:13:21.45#ibcon#read 4, iclass 27, count 2 2006.203.08:13:21.45#ibcon#about to read 5, iclass 27, count 2 2006.203.08:13:21.45#ibcon#read 5, iclass 27, count 2 2006.203.08:13:21.45#ibcon#about to read 6, iclass 27, count 2 2006.203.08:13:21.45#ibcon#read 6, iclass 27, count 2 2006.203.08:13:21.45#ibcon#end of sib2, iclass 27, count 2 2006.203.08:13:21.45#ibcon#*after write, iclass 27, count 2 2006.203.08:13:21.45#ibcon#*before return 0, iclass 27, count 2 2006.203.08:13:21.45#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.203.08:13:21.45#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.203.08:13:21.45#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.203.08:13:21.45#ibcon#ireg 7 cls_cnt 0 2006.203.08:13:21.45#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.203.08:13:21.57#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.203.08:13:21.57#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.203.08:13:21.57#ibcon#enter wrdev, iclass 27, count 0 2006.203.08:13:21.57#ibcon#first serial, iclass 27, count 0 2006.203.08:13:21.57#ibcon#enter sib2, iclass 27, count 0 2006.203.08:13:21.57#ibcon#flushed, iclass 27, count 0 2006.203.08:13:21.57#ibcon#about to write, iclass 27, count 0 2006.203.08:13:21.57#ibcon#wrote, iclass 27, count 0 2006.203.08:13:21.57#ibcon#about to read 3, iclass 27, count 0 2006.203.08:13:21.59#ibcon#read 3, iclass 27, count 0 2006.203.08:13:21.59#ibcon#about to read 4, iclass 27, count 0 2006.203.08:13:21.59#ibcon#read 4, iclass 27, count 0 2006.203.08:13:21.59#ibcon#about to read 5, iclass 27, count 0 2006.203.08:13:21.59#ibcon#read 5, iclass 27, count 0 2006.203.08:13:21.59#ibcon#about to read 6, iclass 27, count 0 2006.203.08:13:21.59#ibcon#read 6, iclass 27, count 0 2006.203.08:13:21.59#ibcon#end of sib2, iclass 27, count 0 2006.203.08:13:21.59#ibcon#*mode == 0, iclass 27, count 0 2006.203.08:13:21.59#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.203.08:13:21.59#ibcon#[25=USB\r\n] 2006.203.08:13:21.59#ibcon#*before write, iclass 27, count 0 2006.203.08:13:21.59#ibcon#enter sib2, iclass 27, count 0 2006.203.08:13:21.59#ibcon#flushed, iclass 27, count 0 2006.203.08:13:21.59#ibcon#about to write, iclass 27, count 0 2006.203.08:13:21.59#ibcon#wrote, iclass 27, count 0 2006.203.08:13:21.59#ibcon#about to read 3, iclass 27, count 0 2006.203.08:13:21.62#ibcon#read 3, iclass 27, count 0 2006.203.08:13:21.62#ibcon#about to read 4, iclass 27, count 0 2006.203.08:13:21.62#ibcon#read 4, iclass 27, count 0 2006.203.08:13:21.62#ibcon#about to read 5, iclass 27, count 0 2006.203.08:13:21.62#ibcon#read 5, iclass 27, count 0 2006.203.08:13:21.62#ibcon#about to read 6, iclass 27, count 0 2006.203.08:13:21.62#ibcon#read 6, iclass 27, count 0 2006.203.08:13:21.62#ibcon#end of sib2, iclass 27, count 0 2006.203.08:13:21.62#ibcon#*after write, iclass 27, count 0 2006.203.08:13:21.62#ibcon#*before return 0, iclass 27, count 0 2006.203.08:13:21.62#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.203.08:13:21.62#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.203.08:13:21.62#ibcon#about to clear, iclass 27 cls_cnt 0 2006.203.08:13:21.62#ibcon#cleared, iclass 27 cls_cnt 0 2006.203.08:13:21.62$vc4f8/vblo=1,632.99 2006.203.08:13:21.62#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.203.08:13:21.62#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.203.08:13:21.62#ibcon#ireg 17 cls_cnt 0 2006.203.08:13:21.62#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.203.08:13:21.62#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.203.08:13:21.62#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.203.08:13:21.62#ibcon#enter wrdev, iclass 29, count 0 2006.203.08:13:21.62#ibcon#first serial, iclass 29, count 0 2006.203.08:13:21.62#ibcon#enter sib2, iclass 29, count 0 2006.203.08:13:21.62#ibcon#flushed, iclass 29, count 0 2006.203.08:13:21.62#ibcon#about to write, iclass 29, count 0 2006.203.08:13:21.62#ibcon#wrote, iclass 29, count 0 2006.203.08:13:21.62#ibcon#about to read 3, iclass 29, count 0 2006.203.08:13:21.64#ibcon#read 3, iclass 29, count 0 2006.203.08:13:21.64#ibcon#about to read 4, iclass 29, count 0 2006.203.08:13:21.64#ibcon#read 4, iclass 29, count 0 2006.203.08:13:21.64#ibcon#about to read 5, iclass 29, count 0 2006.203.08:13:21.64#ibcon#read 5, iclass 29, count 0 2006.203.08:13:21.64#ibcon#about to read 6, iclass 29, count 0 2006.203.08:13:21.64#ibcon#read 6, iclass 29, count 0 2006.203.08:13:21.64#ibcon#end of sib2, iclass 29, count 0 2006.203.08:13:21.64#ibcon#*mode == 0, iclass 29, count 0 2006.203.08:13:21.64#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.203.08:13:21.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.203.08:13:21.64#ibcon#*before write, iclass 29, count 0 2006.203.08:13:21.64#ibcon#enter sib2, iclass 29, count 0 2006.203.08:13:21.64#ibcon#flushed, iclass 29, count 0 2006.203.08:13:21.64#ibcon#about to write, iclass 29, count 0 2006.203.08:13:21.64#ibcon#wrote, iclass 29, count 0 2006.203.08:13:21.64#ibcon#about to read 3, iclass 29, count 0 2006.203.08:13:21.68#ibcon#read 3, iclass 29, count 0 2006.203.08:13:21.68#ibcon#about to read 4, iclass 29, count 0 2006.203.08:13:21.68#ibcon#read 4, iclass 29, count 0 2006.203.08:13:21.68#ibcon#about to read 5, iclass 29, count 0 2006.203.08:13:21.68#ibcon#read 5, iclass 29, count 0 2006.203.08:13:21.68#ibcon#about to read 6, iclass 29, count 0 2006.203.08:13:21.68#ibcon#read 6, iclass 29, count 0 2006.203.08:13:21.68#ibcon#end of sib2, iclass 29, count 0 2006.203.08:13:21.68#ibcon#*after write, iclass 29, count 0 2006.203.08:13:21.68#ibcon#*before return 0, iclass 29, count 0 2006.203.08:13:21.68#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.203.08:13:21.68#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.203.08:13:21.68#ibcon#about to clear, iclass 29 cls_cnt 0 2006.203.08:13:21.68#ibcon#cleared, iclass 29 cls_cnt 0 2006.203.08:13:21.68$vc4f8/vb=1,4 2006.203.08:13:21.68#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.203.08:13:21.68#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.203.08:13:21.68#ibcon#ireg 11 cls_cnt 2 2006.203.08:13:21.68#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.203.08:13:21.68#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.203.08:13:21.68#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.203.08:13:21.68#ibcon#enter wrdev, iclass 31, count 2 2006.203.08:13:21.68#ibcon#first serial, iclass 31, count 2 2006.203.08:13:21.68#ibcon#enter sib2, iclass 31, count 2 2006.203.08:13:21.68#ibcon#flushed, iclass 31, count 2 2006.203.08:13:21.68#ibcon#about to write, iclass 31, count 2 2006.203.08:13:21.68#ibcon#wrote, iclass 31, count 2 2006.203.08:13:21.68#ibcon#about to read 3, iclass 31, count 2 2006.203.08:13:21.70#ibcon#read 3, iclass 31, count 2 2006.203.08:13:21.70#ibcon#about to read 4, iclass 31, count 2 2006.203.08:13:21.70#ibcon#read 4, iclass 31, count 2 2006.203.08:13:21.70#ibcon#about to read 5, iclass 31, count 2 2006.203.08:13:21.70#ibcon#read 5, iclass 31, count 2 2006.203.08:13:21.70#ibcon#about to read 6, iclass 31, count 2 2006.203.08:13:21.70#ibcon#read 6, iclass 31, count 2 2006.203.08:13:21.70#ibcon#end of sib2, iclass 31, count 2 2006.203.08:13:21.70#ibcon#*mode == 0, iclass 31, count 2 2006.203.08:13:21.70#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.203.08:13:21.70#ibcon#[27=AT01-04\r\n] 2006.203.08:13:21.70#ibcon#*before write, iclass 31, count 2 2006.203.08:13:21.70#ibcon#enter sib2, iclass 31, count 2 2006.203.08:13:21.70#ibcon#flushed, iclass 31, count 2 2006.203.08:13:21.70#ibcon#about to write, iclass 31, count 2 2006.203.08:13:21.70#ibcon#wrote, iclass 31, count 2 2006.203.08:13:21.70#ibcon#about to read 3, iclass 31, count 2 2006.203.08:13:21.73#ibcon#read 3, iclass 31, count 2 2006.203.08:13:21.73#ibcon#about to read 4, iclass 31, count 2 2006.203.08:13:21.73#ibcon#read 4, iclass 31, count 2 2006.203.08:13:21.73#ibcon#about to read 5, iclass 31, count 2 2006.203.08:13:21.73#ibcon#read 5, iclass 31, count 2 2006.203.08:13:21.73#ibcon#about to read 6, iclass 31, count 2 2006.203.08:13:21.73#ibcon#read 6, iclass 31, count 2 2006.203.08:13:21.73#ibcon#end of sib2, iclass 31, count 2 2006.203.08:13:21.73#ibcon#*after write, iclass 31, count 2 2006.203.08:13:21.73#ibcon#*before return 0, iclass 31, count 2 2006.203.08:13:21.73#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.203.08:13:21.73#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.203.08:13:21.73#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.203.08:13:21.73#ibcon#ireg 7 cls_cnt 0 2006.203.08:13:21.73#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.203.08:13:21.85#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.203.08:13:21.85#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.203.08:13:21.85#ibcon#enter wrdev, iclass 31, count 0 2006.203.08:13:21.85#ibcon#first serial, iclass 31, count 0 2006.203.08:13:21.85#ibcon#enter sib2, iclass 31, count 0 2006.203.08:13:21.85#ibcon#flushed, iclass 31, count 0 2006.203.08:13:21.85#ibcon#about to write, iclass 31, count 0 2006.203.08:13:21.85#ibcon#wrote, iclass 31, count 0 2006.203.08:13:21.85#ibcon#about to read 3, iclass 31, count 0 2006.203.08:13:21.87#ibcon#read 3, iclass 31, count 0 2006.203.08:13:21.87#ibcon#about to read 4, iclass 31, count 0 2006.203.08:13:21.87#ibcon#read 4, iclass 31, count 0 2006.203.08:13:21.87#ibcon#about to read 5, iclass 31, count 0 2006.203.08:13:21.87#ibcon#read 5, iclass 31, count 0 2006.203.08:13:21.87#ibcon#about to read 6, iclass 31, count 0 2006.203.08:13:21.87#ibcon#read 6, iclass 31, count 0 2006.203.08:13:21.87#ibcon#end of sib2, iclass 31, count 0 2006.203.08:13:21.87#ibcon#*mode == 0, iclass 31, count 0 2006.203.08:13:21.87#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.203.08:13:21.87#ibcon#[27=USB\r\n] 2006.203.08:13:21.87#ibcon#*before write, iclass 31, count 0 2006.203.08:13:21.87#ibcon#enter sib2, iclass 31, count 0 2006.203.08:13:21.87#ibcon#flushed, iclass 31, count 0 2006.203.08:13:21.87#ibcon#about to write, iclass 31, count 0 2006.203.08:13:21.87#ibcon#wrote, iclass 31, count 0 2006.203.08:13:21.87#ibcon#about to read 3, iclass 31, count 0 2006.203.08:13:21.90#ibcon#read 3, iclass 31, count 0 2006.203.08:13:21.90#ibcon#about to read 4, iclass 31, count 0 2006.203.08:13:21.90#ibcon#read 4, iclass 31, count 0 2006.203.08:13:21.90#ibcon#about to read 5, iclass 31, count 0 2006.203.08:13:21.90#ibcon#read 5, iclass 31, count 0 2006.203.08:13:21.90#ibcon#about to read 6, iclass 31, count 0 2006.203.08:13:21.90#ibcon#read 6, iclass 31, count 0 2006.203.08:13:21.90#ibcon#end of sib2, iclass 31, count 0 2006.203.08:13:21.90#ibcon#*after write, iclass 31, count 0 2006.203.08:13:21.90#ibcon#*before return 0, iclass 31, count 0 2006.203.08:13:21.90#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.203.08:13:21.90#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.203.08:13:21.90#ibcon#about to clear, iclass 31 cls_cnt 0 2006.203.08:13:21.90#ibcon#cleared, iclass 31 cls_cnt 0 2006.203.08:13:21.90$vc4f8/vblo=2,640.99 2006.203.08:13:21.90#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.203.08:13:21.90#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.203.08:13:21.90#ibcon#ireg 17 cls_cnt 0 2006.203.08:13:21.90#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.203.08:13:21.90#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.203.08:13:21.90#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.203.08:13:21.90#ibcon#enter wrdev, iclass 33, count 0 2006.203.08:13:21.90#ibcon#first serial, iclass 33, count 0 2006.203.08:13:21.90#ibcon#enter sib2, iclass 33, count 0 2006.203.08:13:21.90#ibcon#flushed, iclass 33, count 0 2006.203.08:13:21.90#ibcon#about to write, iclass 33, count 0 2006.203.08:13:21.90#ibcon#wrote, iclass 33, count 0 2006.203.08:13:21.90#ibcon#about to read 3, iclass 33, count 0 2006.203.08:13:21.92#ibcon#read 3, iclass 33, count 0 2006.203.08:13:21.92#ibcon#about to read 4, iclass 33, count 0 2006.203.08:13:21.92#ibcon#read 4, iclass 33, count 0 2006.203.08:13:21.92#ibcon#about to read 5, iclass 33, count 0 2006.203.08:13:21.92#ibcon#read 5, iclass 33, count 0 2006.203.08:13:21.92#ibcon#about to read 6, iclass 33, count 0 2006.203.08:13:21.92#ibcon#read 6, iclass 33, count 0 2006.203.08:13:21.92#ibcon#end of sib2, iclass 33, count 0 2006.203.08:13:21.92#ibcon#*mode == 0, iclass 33, count 0 2006.203.08:13:21.92#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.203.08:13:21.92#ibcon#[28=FRQ=02,640.99\r\n] 2006.203.08:13:21.92#ibcon#*before write, iclass 33, count 0 2006.203.08:13:21.92#ibcon#enter sib2, iclass 33, count 0 2006.203.08:13:21.92#ibcon#flushed, iclass 33, count 0 2006.203.08:13:21.92#ibcon#about to write, iclass 33, count 0 2006.203.08:13:21.92#ibcon#wrote, iclass 33, count 0 2006.203.08:13:21.92#ibcon#about to read 3, iclass 33, count 0 2006.203.08:13:21.96#ibcon#read 3, iclass 33, count 0 2006.203.08:13:21.96#ibcon#about to read 4, iclass 33, count 0 2006.203.08:13:21.96#ibcon#read 4, iclass 33, count 0 2006.203.08:13:21.96#ibcon#about to read 5, iclass 33, count 0 2006.203.08:13:21.96#ibcon#read 5, iclass 33, count 0 2006.203.08:13:21.96#ibcon#about to read 6, iclass 33, count 0 2006.203.08:13:21.96#ibcon#read 6, iclass 33, count 0 2006.203.08:13:21.96#ibcon#end of sib2, iclass 33, count 0 2006.203.08:13:21.96#ibcon#*after write, iclass 33, count 0 2006.203.08:13:21.96#ibcon#*before return 0, iclass 33, count 0 2006.203.08:13:21.96#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.203.08:13:21.96#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.203.08:13:21.96#ibcon#about to clear, iclass 33 cls_cnt 0 2006.203.08:13:21.96#ibcon#cleared, iclass 33 cls_cnt 0 2006.203.08:13:21.96$vc4f8/vb=2,4 2006.203.08:13:21.96#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.203.08:13:21.96#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.203.08:13:21.96#ibcon#ireg 11 cls_cnt 2 2006.203.08:13:21.96#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.203.08:13:22.03#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.203.08:13:22.03#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.203.08:13:22.03#ibcon#enter wrdev, iclass 35, count 2 2006.203.08:13:22.03#ibcon#first serial, iclass 35, count 2 2006.203.08:13:22.03#ibcon#enter sib2, iclass 35, count 2 2006.203.08:13:22.03#ibcon#flushed, iclass 35, count 2 2006.203.08:13:22.03#ibcon#about to write, iclass 35, count 2 2006.203.08:13:22.03#ibcon#wrote, iclass 35, count 2 2006.203.08:13:22.03#ibcon#about to read 3, iclass 35, count 2 2006.203.08:13:22.04#ibcon#read 3, iclass 35, count 2 2006.203.08:13:22.04#ibcon#about to read 4, iclass 35, count 2 2006.203.08:13:22.04#ibcon#read 4, iclass 35, count 2 2006.203.08:13:22.04#ibcon#about to read 5, iclass 35, count 2 2006.203.08:13:22.04#ibcon#read 5, iclass 35, count 2 2006.203.08:13:22.04#ibcon#about to read 6, iclass 35, count 2 2006.203.08:13:22.04#ibcon#read 6, iclass 35, count 2 2006.203.08:13:22.04#ibcon#end of sib2, iclass 35, count 2 2006.203.08:13:22.04#ibcon#*mode == 0, iclass 35, count 2 2006.203.08:13:22.04#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.203.08:13:22.04#ibcon#[27=AT02-04\r\n] 2006.203.08:13:22.04#ibcon#*before write, iclass 35, count 2 2006.203.08:13:22.04#ibcon#enter sib2, iclass 35, count 2 2006.203.08:13:22.04#ibcon#flushed, iclass 35, count 2 2006.203.08:13:22.04#ibcon#about to write, iclass 35, count 2 2006.203.08:13:22.04#ibcon#wrote, iclass 35, count 2 2006.203.08:13:22.04#ibcon#about to read 3, iclass 35, count 2 2006.203.08:13:22.07#ibcon#read 3, iclass 35, count 2 2006.203.08:13:22.07#ibcon#about to read 4, iclass 35, count 2 2006.203.08:13:22.07#ibcon#read 4, iclass 35, count 2 2006.203.08:13:22.07#ibcon#about to read 5, iclass 35, count 2 2006.203.08:13:22.07#ibcon#read 5, iclass 35, count 2 2006.203.08:13:22.07#ibcon#about to read 6, iclass 35, count 2 2006.203.08:13:22.07#ibcon#read 6, iclass 35, count 2 2006.203.08:13:22.07#ibcon#end of sib2, iclass 35, count 2 2006.203.08:13:22.07#ibcon#*after write, iclass 35, count 2 2006.203.08:13:22.07#ibcon#*before return 0, iclass 35, count 2 2006.203.08:13:22.07#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.203.08:13:22.07#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.203.08:13:22.07#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.203.08:13:22.07#ibcon#ireg 7 cls_cnt 0 2006.203.08:13:22.07#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.203.08:13:22.19#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.203.08:13:22.19#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.203.08:13:22.19#ibcon#enter wrdev, iclass 35, count 0 2006.203.08:13:22.19#ibcon#first serial, iclass 35, count 0 2006.203.08:13:22.19#ibcon#enter sib2, iclass 35, count 0 2006.203.08:13:22.19#ibcon#flushed, iclass 35, count 0 2006.203.08:13:22.19#ibcon#about to write, iclass 35, count 0 2006.203.08:13:22.19#ibcon#wrote, iclass 35, count 0 2006.203.08:13:22.19#ibcon#about to read 3, iclass 35, count 0 2006.203.08:13:22.21#ibcon#read 3, iclass 35, count 0 2006.203.08:13:22.21#ibcon#about to read 4, iclass 35, count 0 2006.203.08:13:22.21#ibcon#read 4, iclass 35, count 0 2006.203.08:13:22.21#ibcon#about to read 5, iclass 35, count 0 2006.203.08:13:22.21#ibcon#read 5, iclass 35, count 0 2006.203.08:13:22.21#ibcon#about to read 6, iclass 35, count 0 2006.203.08:13:22.21#ibcon#read 6, iclass 35, count 0 2006.203.08:13:22.21#ibcon#end of sib2, iclass 35, count 0 2006.203.08:13:22.21#ibcon#*mode == 0, iclass 35, count 0 2006.203.08:13:22.21#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.203.08:13:22.21#ibcon#[27=USB\r\n] 2006.203.08:13:22.21#ibcon#*before write, iclass 35, count 0 2006.203.08:13:22.21#ibcon#enter sib2, iclass 35, count 0 2006.203.08:13:22.21#ibcon#flushed, iclass 35, count 0 2006.203.08:13:22.21#ibcon#about to write, iclass 35, count 0 2006.203.08:13:22.21#ibcon#wrote, iclass 35, count 0 2006.203.08:13:22.21#ibcon#about to read 3, iclass 35, count 0 2006.203.08:13:22.24#ibcon#read 3, iclass 35, count 0 2006.203.08:13:22.24#ibcon#about to read 4, iclass 35, count 0 2006.203.08:13:22.24#ibcon#read 4, iclass 35, count 0 2006.203.08:13:22.24#ibcon#about to read 5, iclass 35, count 0 2006.203.08:13:22.24#ibcon#read 5, iclass 35, count 0 2006.203.08:13:22.24#ibcon#about to read 6, iclass 35, count 0 2006.203.08:13:22.24#ibcon#read 6, iclass 35, count 0 2006.203.08:13:22.24#ibcon#end of sib2, iclass 35, count 0 2006.203.08:13:22.24#ibcon#*after write, iclass 35, count 0 2006.203.08:13:22.24#ibcon#*before return 0, iclass 35, count 0 2006.203.08:13:22.24#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.203.08:13:22.24#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.203.08:13:22.24#ibcon#about to clear, iclass 35 cls_cnt 0 2006.203.08:13:22.24#ibcon#cleared, iclass 35 cls_cnt 0 2006.203.08:13:22.24$vc4f8/vblo=3,656.99 2006.203.08:13:22.24#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.203.08:13:22.24#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.203.08:13:22.24#ibcon#ireg 17 cls_cnt 0 2006.203.08:13:22.24#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.203.08:13:22.24#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.203.08:13:22.24#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.203.08:13:22.24#ibcon#enter wrdev, iclass 37, count 0 2006.203.08:13:22.24#ibcon#first serial, iclass 37, count 0 2006.203.08:13:22.25#ibcon#enter sib2, iclass 37, count 0 2006.203.08:13:22.25#ibcon#flushed, iclass 37, count 0 2006.203.08:13:22.25#ibcon#about to write, iclass 37, count 0 2006.203.08:13:22.25#ibcon#wrote, iclass 37, count 0 2006.203.08:13:22.25#ibcon#about to read 3, iclass 37, count 0 2006.203.08:13:22.26#ibcon#read 3, iclass 37, count 0 2006.203.08:13:22.26#ibcon#about to read 4, iclass 37, count 0 2006.203.08:13:22.26#ibcon#read 4, iclass 37, count 0 2006.203.08:13:22.26#ibcon#about to read 5, iclass 37, count 0 2006.203.08:13:22.26#ibcon#read 5, iclass 37, count 0 2006.203.08:13:22.26#ibcon#about to read 6, iclass 37, count 0 2006.203.08:13:22.26#ibcon#read 6, iclass 37, count 0 2006.203.08:13:22.26#ibcon#end of sib2, iclass 37, count 0 2006.203.08:13:22.26#ibcon#*mode == 0, iclass 37, count 0 2006.203.08:13:22.26#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.203.08:13:22.26#ibcon#[28=FRQ=03,656.99\r\n] 2006.203.08:13:22.26#ibcon#*before write, iclass 37, count 0 2006.203.08:13:22.26#ibcon#enter sib2, iclass 37, count 0 2006.203.08:13:22.26#ibcon#flushed, iclass 37, count 0 2006.203.08:13:22.26#ibcon#about to write, iclass 37, count 0 2006.203.08:13:22.26#ibcon#wrote, iclass 37, count 0 2006.203.08:13:22.26#ibcon#about to read 3, iclass 37, count 0 2006.203.08:13:22.30#ibcon#read 3, iclass 37, count 0 2006.203.08:13:22.30#ibcon#about to read 4, iclass 37, count 0 2006.203.08:13:22.30#ibcon#read 4, iclass 37, count 0 2006.203.08:13:22.30#ibcon#about to read 5, iclass 37, count 0 2006.203.08:13:22.30#ibcon#read 5, iclass 37, count 0 2006.203.08:13:22.30#ibcon#about to read 6, iclass 37, count 0 2006.203.08:13:22.30#ibcon#read 6, iclass 37, count 0 2006.203.08:13:22.30#ibcon#end of sib2, iclass 37, count 0 2006.203.08:13:22.30#ibcon#*after write, iclass 37, count 0 2006.203.08:13:22.30#ibcon#*before return 0, iclass 37, count 0 2006.203.08:13:22.30#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.203.08:13:22.30#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.203.08:13:22.30#ibcon#about to clear, iclass 37 cls_cnt 0 2006.203.08:13:22.30#ibcon#cleared, iclass 37 cls_cnt 0 2006.203.08:13:22.30$vc4f8/vb=3,4 2006.203.08:13:22.30#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.203.08:13:22.30#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.203.08:13:22.30#ibcon#ireg 11 cls_cnt 2 2006.203.08:13:22.30#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.203.08:13:22.36#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.203.08:13:22.36#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.203.08:13:22.36#ibcon#enter wrdev, iclass 39, count 2 2006.203.08:13:22.36#ibcon#first serial, iclass 39, count 2 2006.203.08:13:22.36#ibcon#enter sib2, iclass 39, count 2 2006.203.08:13:22.36#ibcon#flushed, iclass 39, count 2 2006.203.08:13:22.36#ibcon#about to write, iclass 39, count 2 2006.203.08:13:22.36#ibcon#wrote, iclass 39, count 2 2006.203.08:13:22.36#ibcon#about to read 3, iclass 39, count 2 2006.203.08:13:22.38#ibcon#read 3, iclass 39, count 2 2006.203.08:13:22.38#ibcon#about to read 4, iclass 39, count 2 2006.203.08:13:22.38#ibcon#read 4, iclass 39, count 2 2006.203.08:13:22.38#ibcon#about to read 5, iclass 39, count 2 2006.203.08:13:22.38#ibcon#read 5, iclass 39, count 2 2006.203.08:13:22.38#ibcon#about to read 6, iclass 39, count 2 2006.203.08:13:22.38#ibcon#read 6, iclass 39, count 2 2006.203.08:13:22.38#ibcon#end of sib2, iclass 39, count 2 2006.203.08:13:22.38#ibcon#*mode == 0, iclass 39, count 2 2006.203.08:13:22.38#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.203.08:13:22.38#ibcon#[27=AT03-04\r\n] 2006.203.08:13:22.38#ibcon#*before write, iclass 39, count 2 2006.203.08:13:22.38#ibcon#enter sib2, iclass 39, count 2 2006.203.08:13:22.38#ibcon#flushed, iclass 39, count 2 2006.203.08:13:22.38#ibcon#about to write, iclass 39, count 2 2006.203.08:13:22.38#ibcon#wrote, iclass 39, count 2 2006.203.08:13:22.38#ibcon#about to read 3, iclass 39, count 2 2006.203.08:13:22.41#ibcon#read 3, iclass 39, count 2 2006.203.08:13:22.41#ibcon#about to read 4, iclass 39, count 2 2006.203.08:13:22.41#ibcon#read 4, iclass 39, count 2 2006.203.08:13:22.41#ibcon#about to read 5, iclass 39, count 2 2006.203.08:13:22.41#ibcon#read 5, iclass 39, count 2 2006.203.08:13:22.41#ibcon#about to read 6, iclass 39, count 2 2006.203.08:13:22.41#ibcon#read 6, iclass 39, count 2 2006.203.08:13:22.41#ibcon#end of sib2, iclass 39, count 2 2006.203.08:13:22.41#ibcon#*after write, iclass 39, count 2 2006.203.08:13:22.41#ibcon#*before return 0, iclass 39, count 2 2006.203.08:13:22.41#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.203.08:13:22.41#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.203.08:13:22.41#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.203.08:13:22.41#ibcon#ireg 7 cls_cnt 0 2006.203.08:13:22.41#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.203.08:13:22.53#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.203.08:13:22.53#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.203.08:13:22.53#ibcon#enter wrdev, iclass 39, count 0 2006.203.08:13:22.53#ibcon#first serial, iclass 39, count 0 2006.203.08:13:22.53#ibcon#enter sib2, iclass 39, count 0 2006.203.08:13:22.53#ibcon#flushed, iclass 39, count 0 2006.203.08:13:22.53#ibcon#about to write, iclass 39, count 0 2006.203.08:13:22.53#ibcon#wrote, iclass 39, count 0 2006.203.08:13:22.53#ibcon#about to read 3, iclass 39, count 0 2006.203.08:13:22.55#ibcon#read 3, iclass 39, count 0 2006.203.08:13:22.55#ibcon#about to read 4, iclass 39, count 0 2006.203.08:13:22.55#ibcon#read 4, iclass 39, count 0 2006.203.08:13:22.55#ibcon#about to read 5, iclass 39, count 0 2006.203.08:13:22.55#ibcon#read 5, iclass 39, count 0 2006.203.08:13:22.55#ibcon#about to read 6, iclass 39, count 0 2006.203.08:13:22.55#ibcon#read 6, iclass 39, count 0 2006.203.08:13:22.55#ibcon#end of sib2, iclass 39, count 0 2006.203.08:13:22.55#ibcon#*mode == 0, iclass 39, count 0 2006.203.08:13:22.55#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.203.08:13:22.55#ibcon#[27=USB\r\n] 2006.203.08:13:22.55#ibcon#*before write, iclass 39, count 0 2006.203.08:13:22.55#ibcon#enter sib2, iclass 39, count 0 2006.203.08:13:22.55#ibcon#flushed, iclass 39, count 0 2006.203.08:13:22.55#ibcon#about to write, iclass 39, count 0 2006.203.08:13:22.55#ibcon#wrote, iclass 39, count 0 2006.203.08:13:22.55#ibcon#about to read 3, iclass 39, count 0 2006.203.08:13:22.58#ibcon#read 3, iclass 39, count 0 2006.203.08:13:22.58#ibcon#about to read 4, iclass 39, count 0 2006.203.08:13:22.58#ibcon#read 4, iclass 39, count 0 2006.203.08:13:22.58#ibcon#about to read 5, iclass 39, count 0 2006.203.08:13:22.58#ibcon#read 5, iclass 39, count 0 2006.203.08:13:22.58#ibcon#about to read 6, iclass 39, count 0 2006.203.08:13:22.58#ibcon#read 6, iclass 39, count 0 2006.203.08:13:22.58#ibcon#end of sib2, iclass 39, count 0 2006.203.08:13:22.58#ibcon#*after write, iclass 39, count 0 2006.203.08:13:22.58#ibcon#*before return 0, iclass 39, count 0 2006.203.08:13:22.58#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.203.08:13:22.58#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.203.08:13:22.58#ibcon#about to clear, iclass 39 cls_cnt 0 2006.203.08:13:22.58#ibcon#cleared, iclass 39 cls_cnt 0 2006.203.08:13:22.58$vc4f8/vblo=4,712.99 2006.203.08:13:22.58#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.203.08:13:22.58#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.203.08:13:22.58#ibcon#ireg 17 cls_cnt 0 2006.203.08:13:22.58#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.203.08:13:22.58#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.203.08:13:22.58#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.203.08:13:22.58#ibcon#enter wrdev, iclass 3, count 0 2006.203.08:13:22.58#ibcon#first serial, iclass 3, count 0 2006.203.08:13:22.58#ibcon#enter sib2, iclass 3, count 0 2006.203.08:13:22.58#ibcon#flushed, iclass 3, count 0 2006.203.08:13:22.58#ibcon#about to write, iclass 3, count 0 2006.203.08:13:22.58#ibcon#wrote, iclass 3, count 0 2006.203.08:13:22.58#ibcon#about to read 3, iclass 3, count 0 2006.203.08:13:22.60#ibcon#read 3, iclass 3, count 0 2006.203.08:13:22.60#ibcon#about to read 4, iclass 3, count 0 2006.203.08:13:22.60#ibcon#read 4, iclass 3, count 0 2006.203.08:13:22.60#ibcon#about to read 5, iclass 3, count 0 2006.203.08:13:22.60#ibcon#read 5, iclass 3, count 0 2006.203.08:13:22.60#ibcon#about to read 6, iclass 3, count 0 2006.203.08:13:22.60#ibcon#read 6, iclass 3, count 0 2006.203.08:13:22.60#ibcon#end of sib2, iclass 3, count 0 2006.203.08:13:22.60#ibcon#*mode == 0, iclass 3, count 0 2006.203.08:13:22.60#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.203.08:13:22.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.203.08:13:22.60#ibcon#*before write, iclass 3, count 0 2006.203.08:13:22.60#ibcon#enter sib2, iclass 3, count 0 2006.203.08:13:22.60#ibcon#flushed, iclass 3, count 0 2006.203.08:13:22.60#ibcon#about to write, iclass 3, count 0 2006.203.08:13:22.60#ibcon#wrote, iclass 3, count 0 2006.203.08:13:22.60#ibcon#about to read 3, iclass 3, count 0 2006.203.08:13:22.64#ibcon#read 3, iclass 3, count 0 2006.203.08:13:22.64#ibcon#about to read 4, iclass 3, count 0 2006.203.08:13:22.64#ibcon#read 4, iclass 3, count 0 2006.203.08:13:22.64#ibcon#about to read 5, iclass 3, count 0 2006.203.08:13:22.64#ibcon#read 5, iclass 3, count 0 2006.203.08:13:22.64#ibcon#about to read 6, iclass 3, count 0 2006.203.08:13:22.64#ibcon#read 6, iclass 3, count 0 2006.203.08:13:22.64#ibcon#end of sib2, iclass 3, count 0 2006.203.08:13:22.64#ibcon#*after write, iclass 3, count 0 2006.203.08:13:22.64#ibcon#*before return 0, iclass 3, count 0 2006.203.08:13:22.64#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.203.08:13:22.64#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.203.08:13:22.64#ibcon#about to clear, iclass 3 cls_cnt 0 2006.203.08:13:22.64#ibcon#cleared, iclass 3 cls_cnt 0 2006.203.08:13:22.64$vc4f8/vb=4,4 2006.203.08:13:22.64#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.203.08:13:22.64#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.203.08:13:22.64#ibcon#ireg 11 cls_cnt 2 2006.203.08:13:22.64#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.203.08:13:22.70#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.203.08:13:22.70#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.203.08:13:22.70#ibcon#enter wrdev, iclass 5, count 2 2006.203.08:13:22.70#ibcon#first serial, iclass 5, count 2 2006.203.08:13:22.70#ibcon#enter sib2, iclass 5, count 2 2006.203.08:13:22.70#ibcon#flushed, iclass 5, count 2 2006.203.08:13:22.70#ibcon#about to write, iclass 5, count 2 2006.203.08:13:22.70#ibcon#wrote, iclass 5, count 2 2006.203.08:13:22.70#ibcon#about to read 3, iclass 5, count 2 2006.203.08:13:22.72#ibcon#read 3, iclass 5, count 2 2006.203.08:13:22.72#ibcon#about to read 4, iclass 5, count 2 2006.203.08:13:22.72#ibcon#read 4, iclass 5, count 2 2006.203.08:13:22.72#ibcon#about to read 5, iclass 5, count 2 2006.203.08:13:22.72#ibcon#read 5, iclass 5, count 2 2006.203.08:13:22.72#ibcon#about to read 6, iclass 5, count 2 2006.203.08:13:22.72#ibcon#read 6, iclass 5, count 2 2006.203.08:13:22.72#ibcon#end of sib2, iclass 5, count 2 2006.203.08:13:22.72#ibcon#*mode == 0, iclass 5, count 2 2006.203.08:13:22.72#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.203.08:13:22.72#ibcon#[27=AT04-04\r\n] 2006.203.08:13:22.72#ibcon#*before write, iclass 5, count 2 2006.203.08:13:22.72#ibcon#enter sib2, iclass 5, count 2 2006.203.08:13:22.72#ibcon#flushed, iclass 5, count 2 2006.203.08:13:22.72#ibcon#about to write, iclass 5, count 2 2006.203.08:13:22.72#ibcon#wrote, iclass 5, count 2 2006.203.08:13:22.72#ibcon#about to read 3, iclass 5, count 2 2006.203.08:13:22.75#ibcon#read 3, iclass 5, count 2 2006.203.08:13:22.75#ibcon#about to read 4, iclass 5, count 2 2006.203.08:13:22.75#ibcon#read 4, iclass 5, count 2 2006.203.08:13:22.75#ibcon#about to read 5, iclass 5, count 2 2006.203.08:13:22.75#ibcon#read 5, iclass 5, count 2 2006.203.08:13:22.75#ibcon#about to read 6, iclass 5, count 2 2006.203.08:13:22.75#ibcon#read 6, iclass 5, count 2 2006.203.08:13:22.75#ibcon#end of sib2, iclass 5, count 2 2006.203.08:13:22.75#ibcon#*after write, iclass 5, count 2 2006.203.08:13:22.75#ibcon#*before return 0, iclass 5, count 2 2006.203.08:13:22.75#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.203.08:13:22.75#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.203.08:13:22.75#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.203.08:13:22.75#ibcon#ireg 7 cls_cnt 0 2006.203.08:13:22.75#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.203.08:13:22.87#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.203.08:13:22.87#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.203.08:13:22.87#ibcon#enter wrdev, iclass 5, count 0 2006.203.08:13:22.87#ibcon#first serial, iclass 5, count 0 2006.203.08:13:22.87#ibcon#enter sib2, iclass 5, count 0 2006.203.08:13:22.87#ibcon#flushed, iclass 5, count 0 2006.203.08:13:22.87#ibcon#about to write, iclass 5, count 0 2006.203.08:13:22.87#ibcon#wrote, iclass 5, count 0 2006.203.08:13:22.87#ibcon#about to read 3, iclass 5, count 0 2006.203.08:13:22.89#ibcon#read 3, iclass 5, count 0 2006.203.08:13:22.89#ibcon#about to read 4, iclass 5, count 0 2006.203.08:13:22.89#ibcon#read 4, iclass 5, count 0 2006.203.08:13:22.89#ibcon#about to read 5, iclass 5, count 0 2006.203.08:13:22.89#ibcon#read 5, iclass 5, count 0 2006.203.08:13:22.89#ibcon#about to read 6, iclass 5, count 0 2006.203.08:13:22.89#ibcon#read 6, iclass 5, count 0 2006.203.08:13:22.89#ibcon#end of sib2, iclass 5, count 0 2006.203.08:13:22.89#ibcon#*mode == 0, iclass 5, count 0 2006.203.08:13:22.89#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.203.08:13:22.89#ibcon#[27=USB\r\n] 2006.203.08:13:22.89#ibcon#*before write, iclass 5, count 0 2006.203.08:13:22.89#ibcon#enter sib2, iclass 5, count 0 2006.203.08:13:22.89#ibcon#flushed, iclass 5, count 0 2006.203.08:13:22.89#ibcon#about to write, iclass 5, count 0 2006.203.08:13:22.89#ibcon#wrote, iclass 5, count 0 2006.203.08:13:22.89#ibcon#about to read 3, iclass 5, count 0 2006.203.08:13:22.92#ibcon#read 3, iclass 5, count 0 2006.203.08:13:22.92#ibcon#about to read 4, iclass 5, count 0 2006.203.08:13:22.92#ibcon#read 4, iclass 5, count 0 2006.203.08:13:22.92#ibcon#about to read 5, iclass 5, count 0 2006.203.08:13:22.92#ibcon#read 5, iclass 5, count 0 2006.203.08:13:22.92#ibcon#about to read 6, iclass 5, count 0 2006.203.08:13:22.92#ibcon#read 6, iclass 5, count 0 2006.203.08:13:22.92#ibcon#end of sib2, iclass 5, count 0 2006.203.08:13:22.92#ibcon#*after write, iclass 5, count 0 2006.203.08:13:22.92#ibcon#*before return 0, iclass 5, count 0 2006.203.08:13:22.92#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.203.08:13:22.92#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.203.08:13:22.92#ibcon#about to clear, iclass 5 cls_cnt 0 2006.203.08:13:22.92#ibcon#cleared, iclass 5 cls_cnt 0 2006.203.08:13:22.92$vc4f8/vblo=5,744.99 2006.203.08:13:22.92#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.203.08:13:22.92#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.203.08:13:22.92#ibcon#ireg 17 cls_cnt 0 2006.203.08:13:22.92#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.203.08:13:22.92#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.203.08:13:22.92#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.203.08:13:22.92#ibcon#enter wrdev, iclass 7, count 0 2006.203.08:13:22.92#ibcon#first serial, iclass 7, count 0 2006.203.08:13:22.92#ibcon#enter sib2, iclass 7, count 0 2006.203.08:13:22.92#ibcon#flushed, iclass 7, count 0 2006.203.08:13:22.92#ibcon#about to write, iclass 7, count 0 2006.203.08:13:22.92#ibcon#wrote, iclass 7, count 0 2006.203.08:13:22.92#ibcon#about to read 3, iclass 7, count 0 2006.203.08:13:22.94#ibcon#read 3, iclass 7, count 0 2006.203.08:13:22.94#ibcon#about to read 4, iclass 7, count 0 2006.203.08:13:22.94#ibcon#read 4, iclass 7, count 0 2006.203.08:13:22.94#ibcon#about to read 5, iclass 7, count 0 2006.203.08:13:22.94#ibcon#read 5, iclass 7, count 0 2006.203.08:13:22.94#ibcon#about to read 6, iclass 7, count 0 2006.203.08:13:22.94#ibcon#read 6, iclass 7, count 0 2006.203.08:13:22.94#ibcon#end of sib2, iclass 7, count 0 2006.203.08:13:22.94#ibcon#*mode == 0, iclass 7, count 0 2006.203.08:13:22.94#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.203.08:13:22.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.203.08:13:22.94#ibcon#*before write, iclass 7, count 0 2006.203.08:13:22.94#ibcon#enter sib2, iclass 7, count 0 2006.203.08:13:22.94#ibcon#flushed, iclass 7, count 0 2006.203.08:13:22.94#ibcon#about to write, iclass 7, count 0 2006.203.08:13:22.94#ibcon#wrote, iclass 7, count 0 2006.203.08:13:22.94#ibcon#about to read 3, iclass 7, count 0 2006.203.08:13:22.98#ibcon#read 3, iclass 7, count 0 2006.203.08:13:22.98#ibcon#about to read 4, iclass 7, count 0 2006.203.08:13:22.98#ibcon#read 4, iclass 7, count 0 2006.203.08:13:22.98#ibcon#about to read 5, iclass 7, count 0 2006.203.08:13:22.98#ibcon#read 5, iclass 7, count 0 2006.203.08:13:22.98#ibcon#about to read 6, iclass 7, count 0 2006.203.08:13:22.98#ibcon#read 6, iclass 7, count 0 2006.203.08:13:22.98#ibcon#end of sib2, iclass 7, count 0 2006.203.08:13:22.98#ibcon#*after write, iclass 7, count 0 2006.203.08:13:22.98#ibcon#*before return 0, iclass 7, count 0 2006.203.08:13:22.98#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.203.08:13:22.98#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.203.08:13:22.98#ibcon#about to clear, iclass 7 cls_cnt 0 2006.203.08:13:22.98#ibcon#cleared, iclass 7 cls_cnt 0 2006.203.08:13:22.98$vc4f8/vb=5,3 2006.203.08:13:22.98#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.203.08:13:22.98#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.203.08:13:22.98#ibcon#ireg 11 cls_cnt 2 2006.203.08:13:22.98#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.203.08:13:23.04#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.203.08:13:23.04#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.203.08:13:23.04#ibcon#enter wrdev, iclass 11, count 2 2006.203.08:13:23.04#ibcon#first serial, iclass 11, count 2 2006.203.08:13:23.04#ibcon#enter sib2, iclass 11, count 2 2006.203.08:13:23.04#ibcon#flushed, iclass 11, count 2 2006.203.08:13:23.04#ibcon#about to write, iclass 11, count 2 2006.203.08:13:23.04#ibcon#wrote, iclass 11, count 2 2006.203.08:13:23.04#ibcon#about to read 3, iclass 11, count 2 2006.203.08:13:23.06#ibcon#read 3, iclass 11, count 2 2006.203.08:13:23.06#ibcon#about to read 4, iclass 11, count 2 2006.203.08:13:23.06#ibcon#read 4, iclass 11, count 2 2006.203.08:13:23.06#ibcon#about to read 5, iclass 11, count 2 2006.203.08:13:23.06#ibcon#read 5, iclass 11, count 2 2006.203.08:13:23.06#ibcon#about to read 6, iclass 11, count 2 2006.203.08:13:23.06#ibcon#read 6, iclass 11, count 2 2006.203.08:13:23.06#ibcon#end of sib2, iclass 11, count 2 2006.203.08:13:23.06#ibcon#*mode == 0, iclass 11, count 2 2006.203.08:13:23.06#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.203.08:13:23.06#ibcon#[27=AT05-03\r\n] 2006.203.08:13:23.06#ibcon#*before write, iclass 11, count 2 2006.203.08:13:23.06#ibcon#enter sib2, iclass 11, count 2 2006.203.08:13:23.06#ibcon#flushed, iclass 11, count 2 2006.203.08:13:23.06#ibcon#about to write, iclass 11, count 2 2006.203.08:13:23.06#ibcon#wrote, iclass 11, count 2 2006.203.08:13:23.06#ibcon#about to read 3, iclass 11, count 2 2006.203.08:13:23.09#ibcon#read 3, iclass 11, count 2 2006.203.08:13:23.09#ibcon#about to read 4, iclass 11, count 2 2006.203.08:13:23.09#ibcon#read 4, iclass 11, count 2 2006.203.08:13:23.09#ibcon#about to read 5, iclass 11, count 2 2006.203.08:13:23.09#ibcon#read 5, iclass 11, count 2 2006.203.08:13:23.09#ibcon#about to read 6, iclass 11, count 2 2006.203.08:13:23.09#ibcon#read 6, iclass 11, count 2 2006.203.08:13:23.09#ibcon#end of sib2, iclass 11, count 2 2006.203.08:13:23.09#ibcon#*after write, iclass 11, count 2 2006.203.08:13:23.09#ibcon#*before return 0, iclass 11, count 2 2006.203.08:13:23.09#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.203.08:13:23.09#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.203.08:13:23.09#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.203.08:13:23.09#ibcon#ireg 7 cls_cnt 0 2006.203.08:13:23.09#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.203.08:13:23.21#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.203.08:13:23.21#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.203.08:13:23.21#ibcon#enter wrdev, iclass 11, count 0 2006.203.08:13:23.21#ibcon#first serial, iclass 11, count 0 2006.203.08:13:23.21#ibcon#enter sib2, iclass 11, count 0 2006.203.08:13:23.21#ibcon#flushed, iclass 11, count 0 2006.203.08:13:23.21#ibcon#about to write, iclass 11, count 0 2006.203.08:13:23.21#ibcon#wrote, iclass 11, count 0 2006.203.08:13:23.21#ibcon#about to read 3, iclass 11, count 0 2006.203.08:13:23.23#ibcon#read 3, iclass 11, count 0 2006.203.08:13:23.23#ibcon#about to read 4, iclass 11, count 0 2006.203.08:13:23.23#ibcon#read 4, iclass 11, count 0 2006.203.08:13:23.23#ibcon#about to read 5, iclass 11, count 0 2006.203.08:13:23.23#ibcon#read 5, iclass 11, count 0 2006.203.08:13:23.23#ibcon#about to read 6, iclass 11, count 0 2006.203.08:13:23.23#ibcon#read 6, iclass 11, count 0 2006.203.08:13:23.23#ibcon#end of sib2, iclass 11, count 0 2006.203.08:13:23.23#ibcon#*mode == 0, iclass 11, count 0 2006.203.08:13:23.23#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.203.08:13:23.23#ibcon#[27=USB\r\n] 2006.203.08:13:23.23#ibcon#*before write, iclass 11, count 0 2006.203.08:13:23.23#ibcon#enter sib2, iclass 11, count 0 2006.203.08:13:23.23#ibcon#flushed, iclass 11, count 0 2006.203.08:13:23.23#ibcon#about to write, iclass 11, count 0 2006.203.08:13:23.23#ibcon#wrote, iclass 11, count 0 2006.203.08:13:23.23#ibcon#about to read 3, iclass 11, count 0 2006.203.08:13:23.26#ibcon#read 3, iclass 11, count 0 2006.203.08:13:23.26#ibcon#about to read 4, iclass 11, count 0 2006.203.08:13:23.26#ibcon#read 4, iclass 11, count 0 2006.203.08:13:23.26#ibcon#about to read 5, iclass 11, count 0 2006.203.08:13:23.26#ibcon#read 5, iclass 11, count 0 2006.203.08:13:23.26#ibcon#about to read 6, iclass 11, count 0 2006.203.08:13:23.26#ibcon#read 6, iclass 11, count 0 2006.203.08:13:23.26#ibcon#end of sib2, iclass 11, count 0 2006.203.08:13:23.26#ibcon#*after write, iclass 11, count 0 2006.203.08:13:23.26#ibcon#*before return 0, iclass 11, count 0 2006.203.08:13:23.26#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.203.08:13:23.26#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.203.08:13:23.26#ibcon#about to clear, iclass 11 cls_cnt 0 2006.203.08:13:23.26#ibcon#cleared, iclass 11 cls_cnt 0 2006.203.08:13:23.26$vc4f8/vblo=6,752.99 2006.203.08:13:23.26#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.203.08:13:23.26#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.203.08:13:23.26#ibcon#ireg 17 cls_cnt 0 2006.203.08:13:23.26#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.203.08:13:23.26#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.203.08:13:23.26#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.203.08:13:23.26#ibcon#enter wrdev, iclass 13, count 0 2006.203.08:13:23.26#ibcon#first serial, iclass 13, count 0 2006.203.08:13:23.26#ibcon#enter sib2, iclass 13, count 0 2006.203.08:13:23.26#ibcon#flushed, iclass 13, count 0 2006.203.08:13:23.26#ibcon#about to write, iclass 13, count 0 2006.203.08:13:23.26#ibcon#wrote, iclass 13, count 0 2006.203.08:13:23.26#ibcon#about to read 3, iclass 13, count 0 2006.203.08:13:23.28#ibcon#read 3, iclass 13, count 0 2006.203.08:13:23.28#ibcon#about to read 4, iclass 13, count 0 2006.203.08:13:23.28#ibcon#read 4, iclass 13, count 0 2006.203.08:13:23.28#ibcon#about to read 5, iclass 13, count 0 2006.203.08:13:23.28#ibcon#read 5, iclass 13, count 0 2006.203.08:13:23.28#ibcon#about to read 6, iclass 13, count 0 2006.203.08:13:23.28#ibcon#read 6, iclass 13, count 0 2006.203.08:13:23.28#ibcon#end of sib2, iclass 13, count 0 2006.203.08:13:23.28#ibcon#*mode == 0, iclass 13, count 0 2006.203.08:13:23.28#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.203.08:13:23.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.203.08:13:23.28#ibcon#*before write, iclass 13, count 0 2006.203.08:13:23.28#ibcon#enter sib2, iclass 13, count 0 2006.203.08:13:23.28#ibcon#flushed, iclass 13, count 0 2006.203.08:13:23.28#ibcon#about to write, iclass 13, count 0 2006.203.08:13:23.28#ibcon#wrote, iclass 13, count 0 2006.203.08:13:23.28#ibcon#about to read 3, iclass 13, count 0 2006.203.08:13:23.32#ibcon#read 3, iclass 13, count 0 2006.203.08:13:23.32#ibcon#about to read 4, iclass 13, count 0 2006.203.08:13:23.32#ibcon#read 4, iclass 13, count 0 2006.203.08:13:23.32#ibcon#about to read 5, iclass 13, count 0 2006.203.08:13:23.32#ibcon#read 5, iclass 13, count 0 2006.203.08:13:23.32#ibcon#about to read 6, iclass 13, count 0 2006.203.08:13:23.32#ibcon#read 6, iclass 13, count 0 2006.203.08:13:23.32#ibcon#end of sib2, iclass 13, count 0 2006.203.08:13:23.32#ibcon#*after write, iclass 13, count 0 2006.203.08:13:23.32#ibcon#*before return 0, iclass 13, count 0 2006.203.08:13:23.32#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.203.08:13:23.32#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.203.08:13:23.32#ibcon#about to clear, iclass 13 cls_cnt 0 2006.203.08:13:23.32#ibcon#cleared, iclass 13 cls_cnt 0 2006.203.08:13:23.32$vc4f8/vb=6,4 2006.203.08:13:23.32#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.203.08:13:23.32#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.203.08:13:23.32#ibcon#ireg 11 cls_cnt 2 2006.203.08:13:23.32#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.203.08:13:23.38#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.203.08:13:23.38#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.203.08:13:23.38#ibcon#enter wrdev, iclass 15, count 2 2006.203.08:13:23.38#ibcon#first serial, iclass 15, count 2 2006.203.08:13:23.38#ibcon#enter sib2, iclass 15, count 2 2006.203.08:13:23.38#ibcon#flushed, iclass 15, count 2 2006.203.08:13:23.38#ibcon#about to write, iclass 15, count 2 2006.203.08:13:23.38#ibcon#wrote, iclass 15, count 2 2006.203.08:13:23.38#ibcon#about to read 3, iclass 15, count 2 2006.203.08:13:23.40#ibcon#read 3, iclass 15, count 2 2006.203.08:13:23.40#ibcon#about to read 4, iclass 15, count 2 2006.203.08:13:23.40#ibcon#read 4, iclass 15, count 2 2006.203.08:13:23.40#ibcon#about to read 5, iclass 15, count 2 2006.203.08:13:23.40#ibcon#read 5, iclass 15, count 2 2006.203.08:13:23.40#ibcon#about to read 6, iclass 15, count 2 2006.203.08:13:23.40#ibcon#read 6, iclass 15, count 2 2006.203.08:13:23.40#ibcon#end of sib2, iclass 15, count 2 2006.203.08:13:23.40#ibcon#*mode == 0, iclass 15, count 2 2006.203.08:13:23.40#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.203.08:13:23.40#ibcon#[27=AT06-04\r\n] 2006.203.08:13:23.40#ibcon#*before write, iclass 15, count 2 2006.203.08:13:23.40#ibcon#enter sib2, iclass 15, count 2 2006.203.08:13:23.40#ibcon#flushed, iclass 15, count 2 2006.203.08:13:23.40#ibcon#about to write, iclass 15, count 2 2006.203.08:13:23.40#ibcon#wrote, iclass 15, count 2 2006.203.08:13:23.40#ibcon#about to read 3, iclass 15, count 2 2006.203.08:13:23.43#ibcon#read 3, iclass 15, count 2 2006.203.08:13:23.43#ibcon#about to read 4, iclass 15, count 2 2006.203.08:13:23.43#ibcon#read 4, iclass 15, count 2 2006.203.08:13:23.43#ibcon#about to read 5, iclass 15, count 2 2006.203.08:13:23.43#ibcon#read 5, iclass 15, count 2 2006.203.08:13:23.43#ibcon#about to read 6, iclass 15, count 2 2006.203.08:13:23.43#ibcon#read 6, iclass 15, count 2 2006.203.08:13:23.43#ibcon#end of sib2, iclass 15, count 2 2006.203.08:13:23.43#ibcon#*after write, iclass 15, count 2 2006.203.08:13:23.43#ibcon#*before return 0, iclass 15, count 2 2006.203.08:13:23.43#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.203.08:13:23.43#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.203.08:13:23.43#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.203.08:13:23.43#ibcon#ireg 7 cls_cnt 0 2006.203.08:13:23.43#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.203.08:13:23.55#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.203.08:13:23.55#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.203.08:13:23.55#ibcon#enter wrdev, iclass 15, count 0 2006.203.08:13:23.55#ibcon#first serial, iclass 15, count 0 2006.203.08:13:23.55#ibcon#enter sib2, iclass 15, count 0 2006.203.08:13:23.55#ibcon#flushed, iclass 15, count 0 2006.203.08:13:23.55#ibcon#about to write, iclass 15, count 0 2006.203.08:13:23.55#ibcon#wrote, iclass 15, count 0 2006.203.08:13:23.55#ibcon#about to read 3, iclass 15, count 0 2006.203.08:13:23.57#ibcon#read 3, iclass 15, count 0 2006.203.08:13:23.57#ibcon#about to read 4, iclass 15, count 0 2006.203.08:13:23.57#ibcon#read 4, iclass 15, count 0 2006.203.08:13:23.57#ibcon#about to read 5, iclass 15, count 0 2006.203.08:13:23.57#ibcon#read 5, iclass 15, count 0 2006.203.08:13:23.57#ibcon#about to read 6, iclass 15, count 0 2006.203.08:13:23.57#ibcon#read 6, iclass 15, count 0 2006.203.08:13:23.57#ibcon#end of sib2, iclass 15, count 0 2006.203.08:13:23.57#ibcon#*mode == 0, iclass 15, count 0 2006.203.08:13:23.57#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.203.08:13:23.57#ibcon#[27=USB\r\n] 2006.203.08:13:23.57#ibcon#*before write, iclass 15, count 0 2006.203.08:13:23.57#ibcon#enter sib2, iclass 15, count 0 2006.203.08:13:23.57#ibcon#flushed, iclass 15, count 0 2006.203.08:13:23.57#ibcon#about to write, iclass 15, count 0 2006.203.08:13:23.57#ibcon#wrote, iclass 15, count 0 2006.203.08:13:23.57#ibcon#about to read 3, iclass 15, count 0 2006.203.08:13:23.60#ibcon#read 3, iclass 15, count 0 2006.203.08:13:23.60#ibcon#about to read 4, iclass 15, count 0 2006.203.08:13:23.60#ibcon#read 4, iclass 15, count 0 2006.203.08:13:23.60#ibcon#about to read 5, iclass 15, count 0 2006.203.08:13:23.60#ibcon#read 5, iclass 15, count 0 2006.203.08:13:23.60#ibcon#about to read 6, iclass 15, count 0 2006.203.08:13:23.60#ibcon#read 6, iclass 15, count 0 2006.203.08:13:23.60#ibcon#end of sib2, iclass 15, count 0 2006.203.08:13:23.60#ibcon#*after write, iclass 15, count 0 2006.203.08:13:23.60#ibcon#*before return 0, iclass 15, count 0 2006.203.08:13:23.60#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.203.08:13:23.60#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.203.08:13:23.60#ibcon#about to clear, iclass 15 cls_cnt 0 2006.203.08:13:23.60#ibcon#cleared, iclass 15 cls_cnt 0 2006.203.08:13:23.60$vc4f8/vabw=wide 2006.203.08:13:23.60#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.203.08:13:23.60#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.203.08:13:23.60#ibcon#ireg 8 cls_cnt 0 2006.203.08:13:23.60#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.203.08:13:23.60#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.203.08:13:23.60#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.203.08:13:23.60#ibcon#enter wrdev, iclass 17, count 0 2006.203.08:13:23.60#ibcon#first serial, iclass 17, count 0 2006.203.08:13:23.60#ibcon#enter sib2, iclass 17, count 0 2006.203.08:13:23.60#ibcon#flushed, iclass 17, count 0 2006.203.08:13:23.60#ibcon#about to write, iclass 17, count 0 2006.203.08:13:23.60#ibcon#wrote, iclass 17, count 0 2006.203.08:13:23.60#ibcon#about to read 3, iclass 17, count 0 2006.203.08:13:23.63#ibcon#read 3, iclass 17, count 0 2006.203.08:13:23.63#ibcon#about to read 4, iclass 17, count 0 2006.203.08:13:23.63#ibcon#read 4, iclass 17, count 0 2006.203.08:13:23.63#ibcon#about to read 5, iclass 17, count 0 2006.203.08:13:23.63#ibcon#read 5, iclass 17, count 0 2006.203.08:13:23.63#ibcon#about to read 6, iclass 17, count 0 2006.203.08:13:23.63#ibcon#read 6, iclass 17, count 0 2006.203.08:13:23.63#ibcon#end of sib2, iclass 17, count 0 2006.203.08:13:23.63#ibcon#*mode == 0, iclass 17, count 0 2006.203.08:13:23.63#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.203.08:13:23.63#ibcon#[25=BW32\r\n] 2006.203.08:13:23.63#ibcon#*before write, iclass 17, count 0 2006.203.08:13:23.63#ibcon#enter sib2, iclass 17, count 0 2006.203.08:13:23.63#ibcon#flushed, iclass 17, count 0 2006.203.08:13:23.63#ibcon#about to write, iclass 17, count 0 2006.203.08:13:23.63#ibcon#wrote, iclass 17, count 0 2006.203.08:13:23.63#ibcon#about to read 3, iclass 17, count 0 2006.203.08:13:23.66#ibcon#read 3, iclass 17, count 0 2006.203.08:13:23.66#ibcon#about to read 4, iclass 17, count 0 2006.203.08:13:23.66#ibcon#read 4, iclass 17, count 0 2006.203.08:13:23.66#ibcon#about to read 5, iclass 17, count 0 2006.203.08:13:23.66#ibcon#read 5, iclass 17, count 0 2006.203.08:13:23.66#ibcon#about to read 6, iclass 17, count 0 2006.203.08:13:23.66#ibcon#read 6, iclass 17, count 0 2006.203.08:13:23.66#ibcon#end of sib2, iclass 17, count 0 2006.203.08:13:23.66#ibcon#*after write, iclass 17, count 0 2006.203.08:13:23.66#ibcon#*before return 0, iclass 17, count 0 2006.203.08:13:23.66#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.203.08:13:23.66#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.203.08:13:23.66#ibcon#about to clear, iclass 17 cls_cnt 0 2006.203.08:13:23.66#ibcon#cleared, iclass 17 cls_cnt 0 2006.203.08:13:23.66$vc4f8/vbbw=wide 2006.203.08:13:23.66#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.203.08:13:23.66#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.203.08:13:23.66#ibcon#ireg 8 cls_cnt 0 2006.203.08:13:23.66#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.203.08:13:23.72#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.203.08:13:23.72#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.203.08:13:23.72#ibcon#enter wrdev, iclass 19, count 0 2006.203.08:13:23.72#ibcon#first serial, iclass 19, count 0 2006.203.08:13:23.72#ibcon#enter sib2, iclass 19, count 0 2006.203.08:13:23.72#ibcon#flushed, iclass 19, count 0 2006.203.08:13:23.72#ibcon#about to write, iclass 19, count 0 2006.203.08:13:23.72#ibcon#wrote, iclass 19, count 0 2006.203.08:13:23.72#ibcon#about to read 3, iclass 19, count 0 2006.203.08:13:23.74#ibcon#read 3, iclass 19, count 0 2006.203.08:13:23.74#ibcon#about to read 4, iclass 19, count 0 2006.203.08:13:23.74#ibcon#read 4, iclass 19, count 0 2006.203.08:13:23.74#ibcon#about to read 5, iclass 19, count 0 2006.203.08:13:23.74#ibcon#read 5, iclass 19, count 0 2006.203.08:13:23.74#ibcon#about to read 6, iclass 19, count 0 2006.203.08:13:23.74#ibcon#read 6, iclass 19, count 0 2006.203.08:13:23.74#ibcon#end of sib2, iclass 19, count 0 2006.203.08:13:23.74#ibcon#*mode == 0, iclass 19, count 0 2006.203.08:13:23.74#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.203.08:13:23.74#ibcon#[27=BW32\r\n] 2006.203.08:13:23.74#ibcon#*before write, iclass 19, count 0 2006.203.08:13:23.74#ibcon#enter sib2, iclass 19, count 0 2006.203.08:13:23.74#ibcon#flushed, iclass 19, count 0 2006.203.08:13:23.74#ibcon#about to write, iclass 19, count 0 2006.203.08:13:23.74#ibcon#wrote, iclass 19, count 0 2006.203.08:13:23.74#ibcon#about to read 3, iclass 19, count 0 2006.203.08:13:23.77#ibcon#read 3, iclass 19, count 0 2006.203.08:13:23.77#ibcon#about to read 4, iclass 19, count 0 2006.203.08:13:23.77#ibcon#read 4, iclass 19, count 0 2006.203.08:13:23.77#ibcon#about to read 5, iclass 19, count 0 2006.203.08:13:23.77#ibcon#read 5, iclass 19, count 0 2006.203.08:13:23.77#ibcon#about to read 6, iclass 19, count 0 2006.203.08:13:23.77#ibcon#read 6, iclass 19, count 0 2006.203.08:13:23.77#ibcon#end of sib2, iclass 19, count 0 2006.203.08:13:23.77#ibcon#*after write, iclass 19, count 0 2006.203.08:13:23.77#ibcon#*before return 0, iclass 19, count 0 2006.203.08:13:23.77#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.203.08:13:23.77#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.203.08:13:23.77#ibcon#about to clear, iclass 19 cls_cnt 0 2006.203.08:13:23.77#ibcon#cleared, iclass 19 cls_cnt 0 2006.203.08:13:23.77$4f8m12a/ifd4f 2006.203.08:13:23.77$ifd4f/lo= 2006.203.08:13:23.77$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.203.08:13:23.77$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.203.08:13:23.78$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.203.08:13:23.78$ifd4f/patch= 2006.203.08:13:23.78$ifd4f/patch=lo1,a1,a2,a3,a4 2006.203.08:13:23.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.203.08:13:23.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.203.08:13:23.78$4f8m12a/"form=m,16.000,1:2 2006.203.08:13:23.78$4f8m12a/"tpicd 2006.203.08:13:23.78$4f8m12a/echo=off 2006.203.08:13:23.78$4f8m12a/xlog=off 2006.203.08:13:23.78:!2006.203.08:13:50 2006.203.08:13:34.13#trakl#Source acquired 2006.203.08:13:35.13#flagr#flagr/antenna,acquired 2006.203.08:13:50.01:preob 2006.203.08:13:51.13/onsource/TRACKING 2006.203.08:13:51.13:!2006.203.08:14:00 2006.203.08:14:00.00:data_valid=on 2006.203.08:14:00.00:midob 2006.203.08:14:00.13/onsource/TRACKING 2006.203.08:14:00.13/wx/23.60,1001.0,100 2006.203.08:14:00.33/cable/+6.4593E-03 2006.203.08:14:01.42/va/01,08,usb,yes,28,30 2006.203.08:14:01.42/va/02,07,usb,yes,28,29 2006.203.08:14:01.42/va/03,08,usb,yes,21,21 2006.203.08:14:01.42/va/04,07,usb,yes,29,31 2006.203.08:14:01.42/va/05,07,usb,yes,31,33 2006.203.08:14:01.42/va/06,06,usb,yes,30,30 2006.203.08:14:01.42/va/07,07,usb,yes,27,27 2006.203.08:14:01.42/va/08,06,usb,yes,33,32 2006.203.08:14:01.65/valo/01,532.99,yes,locked 2006.203.08:14:01.65/valo/02,572.99,yes,locked 2006.203.08:14:01.65/valo/03,672.99,yes,locked 2006.203.08:14:01.65/valo/04,832.99,yes,locked 2006.203.08:14:01.65/valo/05,652.99,yes,locked 2006.203.08:14:01.65/valo/06,772.99,yes,locked 2006.203.08:14:01.65/valo/07,832.99,yes,locked 2006.203.08:14:01.65/valo/08,852.99,yes,locked 2006.203.08:14:02.74/vb/01,04,usb,yes,28,27 2006.203.08:14:02.74/vb/02,04,usb,yes,30,31 2006.203.08:14:02.74/vb/03,04,usb,yes,26,30 2006.203.08:14:02.74/vb/04,04,usb,yes,27,27 2006.203.08:14:02.74/vb/05,03,usb,yes,32,36 2006.203.08:14:02.74/vb/06,04,usb,yes,27,29 2006.203.08:14:02.74/vb/07,04,usb,yes,29,28 2006.203.08:14:02.74/vb/08,04,usb,yes,26,29 2006.203.08:14:02.98/vblo/01,632.99,yes,locked 2006.203.08:14:02.98/vblo/02,640.99,yes,locked 2006.203.08:14:02.98/vblo/03,656.99,yes,locked 2006.203.08:14:02.98/vblo/04,712.99,yes,locked 2006.203.08:14:02.98/vblo/05,744.99,yes,locked 2006.203.08:14:02.98/vblo/06,752.99,yes,locked 2006.203.08:14:02.98/vblo/07,734.99,yes,locked 2006.203.08:14:02.98/vblo/08,744.99,yes,locked 2006.203.08:14:03.13/vabw/8 2006.203.08:14:03.28/vbbw/8 2006.203.08:14:03.37/xfe/off,on,12.7 2006.203.08:14:03.75/ifatt/23,28,28,28 2006.203.08:14:04.07/fmout-gps/S +4.58E-07 2006.203.08:14:04.15:!2006.203.08:15:00 2006.203.08:15:00.01:data_valid=off 2006.203.08:15:00.02:postob 2006.203.08:15:00.18/cable/+6.4598E-03 2006.203.08:15:00.22/wx/23.59,1001.1,100 2006.203.08:15:01.07/fmout-gps/S +4.58E-07 2006.203.08:15:01.08:scan_name=203-0815,k06203,60 2006.203.08:15:01.08:source=0804+499,080839.67,495036.5,2000.0,ccw 2006.203.08:15:01.14#flagr#flagr/antenna,new-source 2006.203.08:15:02.14:checkk5 2006.203.08:15:02.56/chk_autoobs//k5ts1/ autoobs is running! 2006.203.08:15:02.95/chk_autoobs//k5ts2/ autoobs is running! 2006.203.08:15:03.38/chk_autoobs//k5ts3/ autoobs is running! 2006.203.08:15:03.81/chk_autoobs//k5ts4/ autoobs is running! 2006.203.08:15:04.23/chk_obsdata//k5ts1/T2030814??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.08:15:04.61/chk_obsdata//k5ts2/T2030814??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.08:15:04.97/chk_obsdata//k5ts3/T2030814??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.08:15:05.40/chk_obsdata//k5ts4/T2030814??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.08:15:06.13/k5log//k5ts1_log_newline 2006.203.08:15:07.02/k5log//k5ts2_log_newline 2006.203.08:15:08.07/k5log//k5ts3_log_newline 2006.203.08:15:09.05/k5log//k5ts4_log_newline 2006.203.08:15:09.11/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.203.08:15:09.11:4f8m12a=2 2006.203.08:15:09.11$4f8m12a/echo=on 2006.203.08:15:09.11$4f8m12a/pcalon 2006.203.08:15:09.11$pcalon/"no phase cal control is implemented here 2006.203.08:15:09.11$4f8m12a/"tpicd=stop 2006.203.08:15:09.11$4f8m12a/vc4f8 2006.203.08:15:09.11$vc4f8/valo=1,532.99 2006.203.08:15:09.11#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.203.08:15:09.11#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.203.08:15:09.11#ibcon#ireg 17 cls_cnt 0 2006.203.08:15:09.11#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.203.08:15:09.11#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.203.08:15:09.11#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.203.08:15:09.11#ibcon#enter wrdev, iclass 30, count 0 2006.203.08:15:09.11#ibcon#first serial, iclass 30, count 0 2006.203.08:15:09.11#ibcon#enter sib2, iclass 30, count 0 2006.203.08:15:09.11#ibcon#flushed, iclass 30, count 0 2006.203.08:15:09.11#ibcon#about to write, iclass 30, count 0 2006.203.08:15:09.11#ibcon#wrote, iclass 30, count 0 2006.203.08:15:09.11#ibcon#about to read 3, iclass 30, count 0 2006.203.08:15:09.13#ibcon#read 3, iclass 30, count 0 2006.203.08:15:09.13#ibcon#about to read 4, iclass 30, count 0 2006.203.08:15:09.13#ibcon#read 4, iclass 30, count 0 2006.203.08:15:09.13#ibcon#about to read 5, iclass 30, count 0 2006.203.08:15:09.13#ibcon#read 5, iclass 30, count 0 2006.203.08:15:09.13#ibcon#about to read 6, iclass 30, count 0 2006.203.08:15:09.13#ibcon#read 6, iclass 30, count 0 2006.203.08:15:09.13#ibcon#end of sib2, iclass 30, count 0 2006.203.08:15:09.13#ibcon#*mode == 0, iclass 30, count 0 2006.203.08:15:09.13#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.203.08:15:09.13#ibcon#[26=FRQ=01,532.99\r\n] 2006.203.08:15:09.13#ibcon#*before write, iclass 30, count 0 2006.203.08:15:09.13#ibcon#enter sib2, iclass 30, count 0 2006.203.08:15:09.13#ibcon#flushed, iclass 30, count 0 2006.203.08:15:09.13#ibcon#about to write, iclass 30, count 0 2006.203.08:15:09.13#ibcon#wrote, iclass 30, count 0 2006.203.08:15:09.13#ibcon#about to read 3, iclass 30, count 0 2006.203.08:15:09.18#ibcon#read 3, iclass 30, count 0 2006.203.08:15:09.18#ibcon#about to read 4, iclass 30, count 0 2006.203.08:15:09.18#ibcon#read 4, iclass 30, count 0 2006.203.08:15:09.18#ibcon#about to read 5, iclass 30, count 0 2006.203.08:15:09.18#ibcon#read 5, iclass 30, count 0 2006.203.08:15:09.18#ibcon#about to read 6, iclass 30, count 0 2006.203.08:15:09.18#ibcon#read 6, iclass 30, count 0 2006.203.08:15:09.18#ibcon#end of sib2, iclass 30, count 0 2006.203.08:15:09.18#ibcon#*after write, iclass 30, count 0 2006.203.08:15:09.18#ibcon#*before return 0, iclass 30, count 0 2006.203.08:15:09.18#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.203.08:15:09.18#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.203.08:15:09.18#ibcon#about to clear, iclass 30 cls_cnt 0 2006.203.08:15:09.19#ibcon#cleared, iclass 30 cls_cnt 0 2006.203.08:15:09.19$vc4f8/va=1,8 2006.203.08:15:09.19#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.203.08:15:09.19#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.203.08:15:09.19#ibcon#ireg 11 cls_cnt 2 2006.203.08:15:09.19#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.203.08:15:09.19#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.203.08:15:09.19#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.203.08:15:09.19#ibcon#enter wrdev, iclass 32, count 2 2006.203.08:15:09.19#ibcon#first serial, iclass 32, count 2 2006.203.08:15:09.19#ibcon#enter sib2, iclass 32, count 2 2006.203.08:15:09.19#ibcon#flushed, iclass 32, count 2 2006.203.08:15:09.19#ibcon#about to write, iclass 32, count 2 2006.203.08:15:09.19#ibcon#wrote, iclass 32, count 2 2006.203.08:15:09.19#ibcon#about to read 3, iclass 32, count 2 2006.203.08:15:09.20#ibcon#read 3, iclass 32, count 2 2006.203.08:15:09.20#ibcon#about to read 4, iclass 32, count 2 2006.203.08:15:09.20#ibcon#read 4, iclass 32, count 2 2006.203.08:15:09.20#ibcon#about to read 5, iclass 32, count 2 2006.203.08:15:09.20#ibcon#read 5, iclass 32, count 2 2006.203.08:15:09.20#ibcon#about to read 6, iclass 32, count 2 2006.203.08:15:09.20#ibcon#read 6, iclass 32, count 2 2006.203.08:15:09.20#ibcon#end of sib2, iclass 32, count 2 2006.203.08:15:09.20#ibcon#*mode == 0, iclass 32, count 2 2006.203.08:15:09.20#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.203.08:15:09.20#ibcon#[25=AT01-08\r\n] 2006.203.08:15:09.20#ibcon#*before write, iclass 32, count 2 2006.203.08:15:09.20#ibcon#enter sib2, iclass 32, count 2 2006.203.08:15:09.20#ibcon#flushed, iclass 32, count 2 2006.203.08:15:09.20#ibcon#about to write, iclass 32, count 2 2006.203.08:15:09.20#ibcon#wrote, iclass 32, count 2 2006.203.08:15:09.20#ibcon#about to read 3, iclass 32, count 2 2006.203.08:15:09.23#ibcon#read 3, iclass 32, count 2 2006.203.08:15:09.23#ibcon#about to read 4, iclass 32, count 2 2006.203.08:15:09.23#ibcon#read 4, iclass 32, count 2 2006.203.08:15:09.23#ibcon#about to read 5, iclass 32, count 2 2006.203.08:15:09.23#ibcon#read 5, iclass 32, count 2 2006.203.08:15:09.23#ibcon#about to read 6, iclass 32, count 2 2006.203.08:15:09.23#ibcon#read 6, iclass 32, count 2 2006.203.08:15:09.23#ibcon#end of sib2, iclass 32, count 2 2006.203.08:15:09.23#ibcon#*after write, iclass 32, count 2 2006.203.08:15:09.23#ibcon#*before return 0, iclass 32, count 2 2006.203.08:15:09.23#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.203.08:15:09.23#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.203.08:15:09.23#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.203.08:15:09.23#ibcon#ireg 7 cls_cnt 0 2006.203.08:15:09.23#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.203.08:15:09.35#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.203.08:15:09.35#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.203.08:15:09.35#ibcon#enter wrdev, iclass 32, count 0 2006.203.08:15:09.35#ibcon#first serial, iclass 32, count 0 2006.203.08:15:09.35#ibcon#enter sib2, iclass 32, count 0 2006.203.08:15:09.35#ibcon#flushed, iclass 32, count 0 2006.203.08:15:09.35#ibcon#about to write, iclass 32, count 0 2006.203.08:15:09.35#ibcon#wrote, iclass 32, count 0 2006.203.08:15:09.35#ibcon#about to read 3, iclass 32, count 0 2006.203.08:15:09.37#ibcon#read 3, iclass 32, count 0 2006.203.08:15:09.37#ibcon#about to read 4, iclass 32, count 0 2006.203.08:15:09.37#ibcon#read 4, iclass 32, count 0 2006.203.08:15:09.37#ibcon#about to read 5, iclass 32, count 0 2006.203.08:15:09.37#ibcon#read 5, iclass 32, count 0 2006.203.08:15:09.37#ibcon#about to read 6, iclass 32, count 0 2006.203.08:15:09.37#ibcon#read 6, iclass 32, count 0 2006.203.08:15:09.37#ibcon#end of sib2, iclass 32, count 0 2006.203.08:15:09.37#ibcon#*mode == 0, iclass 32, count 0 2006.203.08:15:09.37#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.203.08:15:09.37#ibcon#[25=USB\r\n] 2006.203.08:15:09.37#ibcon#*before write, iclass 32, count 0 2006.203.08:15:09.37#ibcon#enter sib2, iclass 32, count 0 2006.203.08:15:09.37#ibcon#flushed, iclass 32, count 0 2006.203.08:15:09.37#ibcon#about to write, iclass 32, count 0 2006.203.08:15:09.37#ibcon#wrote, iclass 32, count 0 2006.203.08:15:09.37#ibcon#about to read 3, iclass 32, count 0 2006.203.08:15:09.40#ibcon#read 3, iclass 32, count 0 2006.203.08:15:09.40#ibcon#about to read 4, iclass 32, count 0 2006.203.08:15:09.40#ibcon#read 4, iclass 32, count 0 2006.203.08:15:09.40#ibcon#about to read 5, iclass 32, count 0 2006.203.08:15:09.40#ibcon#read 5, iclass 32, count 0 2006.203.08:15:09.40#ibcon#about to read 6, iclass 32, count 0 2006.203.08:15:09.40#ibcon#read 6, iclass 32, count 0 2006.203.08:15:09.40#ibcon#end of sib2, iclass 32, count 0 2006.203.08:15:09.40#ibcon#*after write, iclass 32, count 0 2006.203.08:15:09.40#ibcon#*before return 0, iclass 32, count 0 2006.203.08:15:09.40#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.203.08:15:09.40#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.203.08:15:09.40#ibcon#about to clear, iclass 32 cls_cnt 0 2006.203.08:15:09.40#ibcon#cleared, iclass 32 cls_cnt 0 2006.203.08:15:09.40$vc4f8/valo=2,572.99 2006.203.08:15:09.40#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.203.08:15:09.40#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.203.08:15:09.40#ibcon#ireg 17 cls_cnt 0 2006.203.08:15:09.40#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.203.08:15:09.40#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.203.08:15:09.40#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.203.08:15:09.40#ibcon#enter wrdev, iclass 34, count 0 2006.203.08:15:09.40#ibcon#first serial, iclass 34, count 0 2006.203.08:15:09.40#ibcon#enter sib2, iclass 34, count 0 2006.203.08:15:09.40#ibcon#flushed, iclass 34, count 0 2006.203.08:15:09.40#ibcon#about to write, iclass 34, count 0 2006.203.08:15:09.40#ibcon#wrote, iclass 34, count 0 2006.203.08:15:09.40#ibcon#about to read 3, iclass 34, count 0 2006.203.08:15:09.43#ibcon#read 3, iclass 34, count 0 2006.203.08:15:09.43#ibcon#about to read 4, iclass 34, count 0 2006.203.08:15:09.43#ibcon#read 4, iclass 34, count 0 2006.203.08:15:09.43#ibcon#about to read 5, iclass 34, count 0 2006.203.08:15:09.43#ibcon#read 5, iclass 34, count 0 2006.203.08:15:09.43#ibcon#about to read 6, iclass 34, count 0 2006.203.08:15:09.43#ibcon#read 6, iclass 34, count 0 2006.203.08:15:09.43#ibcon#end of sib2, iclass 34, count 0 2006.203.08:15:09.43#ibcon#*mode == 0, iclass 34, count 0 2006.203.08:15:09.43#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.203.08:15:09.43#ibcon#[26=FRQ=02,572.99\r\n] 2006.203.08:15:09.43#ibcon#*before write, iclass 34, count 0 2006.203.08:15:09.43#ibcon#enter sib2, iclass 34, count 0 2006.203.08:15:09.43#ibcon#flushed, iclass 34, count 0 2006.203.08:15:09.43#ibcon#about to write, iclass 34, count 0 2006.203.08:15:09.43#ibcon#wrote, iclass 34, count 0 2006.203.08:15:09.43#ibcon#about to read 3, iclass 34, count 0 2006.203.08:15:09.47#ibcon#read 3, iclass 34, count 0 2006.203.08:15:09.47#ibcon#about to read 4, iclass 34, count 0 2006.203.08:15:09.47#ibcon#read 4, iclass 34, count 0 2006.203.08:15:09.47#ibcon#about to read 5, iclass 34, count 0 2006.203.08:15:09.47#ibcon#read 5, iclass 34, count 0 2006.203.08:15:09.47#ibcon#about to read 6, iclass 34, count 0 2006.203.08:15:09.47#ibcon#read 6, iclass 34, count 0 2006.203.08:15:09.47#ibcon#end of sib2, iclass 34, count 0 2006.203.08:15:09.47#ibcon#*after write, iclass 34, count 0 2006.203.08:15:09.47#ibcon#*before return 0, iclass 34, count 0 2006.203.08:15:09.47#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.203.08:15:09.47#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.203.08:15:09.47#ibcon#about to clear, iclass 34 cls_cnt 0 2006.203.08:15:09.47#ibcon#cleared, iclass 34 cls_cnt 0 2006.203.08:15:09.47$vc4f8/va=2,7 2006.203.08:15:09.47#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.203.08:15:09.47#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.203.08:15:09.47#ibcon#ireg 11 cls_cnt 2 2006.203.08:15:09.47#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.203.08:15:09.53#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.203.08:15:09.53#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.203.08:15:09.53#ibcon#enter wrdev, iclass 36, count 2 2006.203.08:15:09.53#ibcon#first serial, iclass 36, count 2 2006.203.08:15:09.53#ibcon#enter sib2, iclass 36, count 2 2006.203.08:15:09.53#ibcon#flushed, iclass 36, count 2 2006.203.08:15:09.53#ibcon#about to write, iclass 36, count 2 2006.203.08:15:09.53#ibcon#wrote, iclass 36, count 2 2006.203.08:15:09.53#ibcon#about to read 3, iclass 36, count 2 2006.203.08:15:09.54#ibcon#read 3, iclass 36, count 2 2006.203.08:15:09.54#ibcon#about to read 4, iclass 36, count 2 2006.203.08:15:09.54#ibcon#read 4, iclass 36, count 2 2006.203.08:15:09.54#ibcon#about to read 5, iclass 36, count 2 2006.203.08:15:09.54#ibcon#read 5, iclass 36, count 2 2006.203.08:15:09.54#ibcon#about to read 6, iclass 36, count 2 2006.203.08:15:09.54#ibcon#read 6, iclass 36, count 2 2006.203.08:15:09.54#ibcon#end of sib2, iclass 36, count 2 2006.203.08:15:09.54#ibcon#*mode == 0, iclass 36, count 2 2006.203.08:15:09.54#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.203.08:15:09.54#ibcon#[25=AT02-07\r\n] 2006.203.08:15:09.54#ibcon#*before write, iclass 36, count 2 2006.203.08:15:09.54#ibcon#enter sib2, iclass 36, count 2 2006.203.08:15:09.54#ibcon#flushed, iclass 36, count 2 2006.203.08:15:09.54#ibcon#about to write, iclass 36, count 2 2006.203.08:15:09.54#ibcon#wrote, iclass 36, count 2 2006.203.08:15:09.54#ibcon#about to read 3, iclass 36, count 2 2006.203.08:15:09.57#ibcon#read 3, iclass 36, count 2 2006.203.08:15:09.57#ibcon#about to read 4, iclass 36, count 2 2006.203.08:15:09.57#ibcon#read 4, iclass 36, count 2 2006.203.08:15:09.57#ibcon#about to read 5, iclass 36, count 2 2006.203.08:15:09.57#ibcon#read 5, iclass 36, count 2 2006.203.08:15:09.57#ibcon#about to read 6, iclass 36, count 2 2006.203.08:15:09.57#ibcon#read 6, iclass 36, count 2 2006.203.08:15:09.57#ibcon#end of sib2, iclass 36, count 2 2006.203.08:15:09.57#ibcon#*after write, iclass 36, count 2 2006.203.08:15:09.57#ibcon#*before return 0, iclass 36, count 2 2006.203.08:15:09.57#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.203.08:15:09.57#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.203.08:15:09.57#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.203.08:15:09.57#ibcon#ireg 7 cls_cnt 0 2006.203.08:15:09.57#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.203.08:15:09.69#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.203.08:15:09.69#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.203.08:15:09.69#ibcon#enter wrdev, iclass 36, count 0 2006.203.08:15:09.69#ibcon#first serial, iclass 36, count 0 2006.203.08:15:09.69#ibcon#enter sib2, iclass 36, count 0 2006.203.08:15:09.69#ibcon#flushed, iclass 36, count 0 2006.203.08:15:09.69#ibcon#about to write, iclass 36, count 0 2006.203.08:15:09.69#ibcon#wrote, iclass 36, count 0 2006.203.08:15:09.69#ibcon#about to read 3, iclass 36, count 0 2006.203.08:15:09.71#ibcon#read 3, iclass 36, count 0 2006.203.08:15:09.71#ibcon#about to read 4, iclass 36, count 0 2006.203.08:15:09.71#ibcon#read 4, iclass 36, count 0 2006.203.08:15:09.71#ibcon#about to read 5, iclass 36, count 0 2006.203.08:15:09.71#ibcon#read 5, iclass 36, count 0 2006.203.08:15:09.71#ibcon#about to read 6, iclass 36, count 0 2006.203.08:15:09.71#ibcon#read 6, iclass 36, count 0 2006.203.08:15:09.71#ibcon#end of sib2, iclass 36, count 0 2006.203.08:15:09.71#ibcon#*mode == 0, iclass 36, count 0 2006.203.08:15:09.71#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.203.08:15:09.71#ibcon#[25=USB\r\n] 2006.203.08:15:09.71#ibcon#*before write, iclass 36, count 0 2006.203.08:15:09.71#ibcon#enter sib2, iclass 36, count 0 2006.203.08:15:09.71#ibcon#flushed, iclass 36, count 0 2006.203.08:15:09.71#ibcon#about to write, iclass 36, count 0 2006.203.08:15:09.71#ibcon#wrote, iclass 36, count 0 2006.203.08:15:09.71#ibcon#about to read 3, iclass 36, count 0 2006.203.08:15:09.74#ibcon#read 3, iclass 36, count 0 2006.203.08:15:09.74#ibcon#about to read 4, iclass 36, count 0 2006.203.08:15:09.74#ibcon#read 4, iclass 36, count 0 2006.203.08:15:09.74#ibcon#about to read 5, iclass 36, count 0 2006.203.08:15:09.74#ibcon#read 5, iclass 36, count 0 2006.203.08:15:09.74#ibcon#about to read 6, iclass 36, count 0 2006.203.08:15:09.74#ibcon#read 6, iclass 36, count 0 2006.203.08:15:09.74#ibcon#end of sib2, iclass 36, count 0 2006.203.08:15:09.74#ibcon#*after write, iclass 36, count 0 2006.203.08:15:09.74#ibcon#*before return 0, iclass 36, count 0 2006.203.08:15:09.74#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.203.08:15:09.74#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.203.08:15:09.74#ibcon#about to clear, iclass 36 cls_cnt 0 2006.203.08:15:09.74#ibcon#cleared, iclass 36 cls_cnt 0 2006.203.08:15:09.74$vc4f8/valo=3,672.99 2006.203.08:15:09.74#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.203.08:15:09.74#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.203.08:15:09.74#ibcon#ireg 17 cls_cnt 0 2006.203.08:15:09.74#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.203.08:15:09.74#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.203.08:15:09.74#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.203.08:15:09.74#ibcon#enter wrdev, iclass 38, count 0 2006.203.08:15:09.74#ibcon#first serial, iclass 38, count 0 2006.203.08:15:09.74#ibcon#enter sib2, iclass 38, count 0 2006.203.08:15:09.74#ibcon#flushed, iclass 38, count 0 2006.203.08:15:09.74#ibcon#about to write, iclass 38, count 0 2006.203.08:15:09.74#ibcon#wrote, iclass 38, count 0 2006.203.08:15:09.74#ibcon#about to read 3, iclass 38, count 0 2006.203.08:15:09.77#ibcon#read 3, iclass 38, count 0 2006.203.08:15:09.77#ibcon#about to read 4, iclass 38, count 0 2006.203.08:15:09.77#ibcon#read 4, iclass 38, count 0 2006.203.08:15:09.77#ibcon#about to read 5, iclass 38, count 0 2006.203.08:15:09.77#ibcon#read 5, iclass 38, count 0 2006.203.08:15:09.77#ibcon#about to read 6, iclass 38, count 0 2006.203.08:15:09.77#ibcon#read 6, iclass 38, count 0 2006.203.08:15:09.77#ibcon#end of sib2, iclass 38, count 0 2006.203.08:15:09.77#ibcon#*mode == 0, iclass 38, count 0 2006.203.08:15:09.77#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.203.08:15:09.77#ibcon#[26=FRQ=03,672.99\r\n] 2006.203.08:15:09.77#ibcon#*before write, iclass 38, count 0 2006.203.08:15:09.77#ibcon#enter sib2, iclass 38, count 0 2006.203.08:15:09.77#ibcon#flushed, iclass 38, count 0 2006.203.08:15:09.77#ibcon#about to write, iclass 38, count 0 2006.203.08:15:09.77#ibcon#wrote, iclass 38, count 0 2006.203.08:15:09.77#ibcon#about to read 3, iclass 38, count 0 2006.203.08:15:09.81#ibcon#read 3, iclass 38, count 0 2006.203.08:15:09.81#ibcon#about to read 4, iclass 38, count 0 2006.203.08:15:09.81#ibcon#read 4, iclass 38, count 0 2006.203.08:15:09.81#ibcon#about to read 5, iclass 38, count 0 2006.203.08:15:09.81#ibcon#read 5, iclass 38, count 0 2006.203.08:15:09.81#ibcon#about to read 6, iclass 38, count 0 2006.203.08:15:09.81#ibcon#read 6, iclass 38, count 0 2006.203.08:15:09.81#ibcon#end of sib2, iclass 38, count 0 2006.203.08:15:09.81#ibcon#*after write, iclass 38, count 0 2006.203.08:15:09.81#ibcon#*before return 0, iclass 38, count 0 2006.203.08:15:09.81#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.203.08:15:09.81#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.203.08:15:09.81#ibcon#about to clear, iclass 38 cls_cnt 0 2006.203.08:15:09.81#ibcon#cleared, iclass 38 cls_cnt 0 2006.203.08:15:09.81$vc4f8/va=3,8 2006.203.08:15:09.81#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.203.08:15:09.81#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.203.08:15:09.81#ibcon#ireg 11 cls_cnt 2 2006.203.08:15:09.81#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.203.08:15:09.87#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.203.08:15:09.87#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.203.08:15:09.87#ibcon#enter wrdev, iclass 40, count 2 2006.203.08:15:09.87#ibcon#first serial, iclass 40, count 2 2006.203.08:15:09.87#ibcon#enter sib2, iclass 40, count 2 2006.203.08:15:09.87#ibcon#flushed, iclass 40, count 2 2006.203.08:15:09.87#ibcon#about to write, iclass 40, count 2 2006.203.08:15:09.87#ibcon#wrote, iclass 40, count 2 2006.203.08:15:09.87#ibcon#about to read 3, iclass 40, count 2 2006.203.08:15:09.88#ibcon#read 3, iclass 40, count 2 2006.203.08:15:09.88#ibcon#about to read 4, iclass 40, count 2 2006.203.08:15:09.88#ibcon#read 4, iclass 40, count 2 2006.203.08:15:09.88#ibcon#about to read 5, iclass 40, count 2 2006.203.08:15:09.88#ibcon#read 5, iclass 40, count 2 2006.203.08:15:09.88#ibcon#about to read 6, iclass 40, count 2 2006.203.08:15:09.88#ibcon#read 6, iclass 40, count 2 2006.203.08:15:09.88#ibcon#end of sib2, iclass 40, count 2 2006.203.08:15:09.88#ibcon#*mode == 0, iclass 40, count 2 2006.203.08:15:09.88#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.203.08:15:09.88#ibcon#[25=AT03-08\r\n] 2006.203.08:15:09.88#ibcon#*before write, iclass 40, count 2 2006.203.08:15:09.88#ibcon#enter sib2, iclass 40, count 2 2006.203.08:15:09.88#ibcon#flushed, iclass 40, count 2 2006.203.08:15:09.88#ibcon#about to write, iclass 40, count 2 2006.203.08:15:09.88#ibcon#wrote, iclass 40, count 2 2006.203.08:15:09.88#ibcon#about to read 3, iclass 40, count 2 2006.203.08:15:09.91#ibcon#read 3, iclass 40, count 2 2006.203.08:15:09.91#ibcon#about to read 4, iclass 40, count 2 2006.203.08:15:09.91#ibcon#read 4, iclass 40, count 2 2006.203.08:15:09.91#ibcon#about to read 5, iclass 40, count 2 2006.203.08:15:09.91#ibcon#read 5, iclass 40, count 2 2006.203.08:15:09.91#ibcon#about to read 6, iclass 40, count 2 2006.203.08:15:09.91#ibcon#read 6, iclass 40, count 2 2006.203.08:15:09.91#ibcon#end of sib2, iclass 40, count 2 2006.203.08:15:09.91#ibcon#*after write, iclass 40, count 2 2006.203.08:15:09.91#ibcon#*before return 0, iclass 40, count 2 2006.203.08:15:09.91#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.203.08:15:09.91#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.203.08:15:09.91#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.203.08:15:09.91#ibcon#ireg 7 cls_cnt 0 2006.203.08:15:09.91#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.203.08:15:10.03#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.203.08:15:10.03#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.203.08:15:10.03#ibcon#enter wrdev, iclass 40, count 0 2006.203.08:15:10.03#ibcon#first serial, iclass 40, count 0 2006.203.08:15:10.03#ibcon#enter sib2, iclass 40, count 0 2006.203.08:15:10.03#ibcon#flushed, iclass 40, count 0 2006.203.08:15:10.03#ibcon#about to write, iclass 40, count 0 2006.203.08:15:10.03#ibcon#wrote, iclass 40, count 0 2006.203.08:15:10.03#ibcon#about to read 3, iclass 40, count 0 2006.203.08:15:10.05#ibcon#read 3, iclass 40, count 0 2006.203.08:15:10.05#ibcon#about to read 4, iclass 40, count 0 2006.203.08:15:10.05#ibcon#read 4, iclass 40, count 0 2006.203.08:15:10.05#ibcon#about to read 5, iclass 40, count 0 2006.203.08:15:10.05#ibcon#read 5, iclass 40, count 0 2006.203.08:15:10.05#ibcon#about to read 6, iclass 40, count 0 2006.203.08:15:10.05#ibcon#read 6, iclass 40, count 0 2006.203.08:15:10.05#ibcon#end of sib2, iclass 40, count 0 2006.203.08:15:10.05#ibcon#*mode == 0, iclass 40, count 0 2006.203.08:15:10.05#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.203.08:15:10.05#ibcon#[25=USB\r\n] 2006.203.08:15:10.05#ibcon#*before write, iclass 40, count 0 2006.203.08:15:10.05#ibcon#enter sib2, iclass 40, count 0 2006.203.08:15:10.05#ibcon#flushed, iclass 40, count 0 2006.203.08:15:10.05#ibcon#about to write, iclass 40, count 0 2006.203.08:15:10.05#ibcon#wrote, iclass 40, count 0 2006.203.08:15:10.05#ibcon#about to read 3, iclass 40, count 0 2006.203.08:15:10.08#ibcon#read 3, iclass 40, count 0 2006.203.08:15:10.08#ibcon#about to read 4, iclass 40, count 0 2006.203.08:15:10.08#ibcon#read 4, iclass 40, count 0 2006.203.08:15:10.08#ibcon#about to read 5, iclass 40, count 0 2006.203.08:15:10.08#ibcon#read 5, iclass 40, count 0 2006.203.08:15:10.08#ibcon#about to read 6, iclass 40, count 0 2006.203.08:15:10.08#ibcon#read 6, iclass 40, count 0 2006.203.08:15:10.08#ibcon#end of sib2, iclass 40, count 0 2006.203.08:15:10.08#ibcon#*after write, iclass 40, count 0 2006.203.08:15:10.08#ibcon#*before return 0, iclass 40, count 0 2006.203.08:15:10.08#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.203.08:15:10.08#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.203.08:15:10.08#ibcon#about to clear, iclass 40 cls_cnt 0 2006.203.08:15:10.08#ibcon#cleared, iclass 40 cls_cnt 0 2006.203.08:15:10.08$vc4f8/valo=4,832.99 2006.203.08:15:10.08#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.203.08:15:10.08#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.203.08:15:10.08#ibcon#ireg 17 cls_cnt 0 2006.203.08:15:10.08#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.203.08:15:10.08#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.203.08:15:10.08#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.203.08:15:10.08#ibcon#enter wrdev, iclass 4, count 0 2006.203.08:15:10.08#ibcon#first serial, iclass 4, count 0 2006.203.08:15:10.08#ibcon#enter sib2, iclass 4, count 0 2006.203.08:15:10.08#ibcon#flushed, iclass 4, count 0 2006.203.08:15:10.08#ibcon#about to write, iclass 4, count 0 2006.203.08:15:10.08#ibcon#wrote, iclass 4, count 0 2006.203.08:15:10.08#ibcon#about to read 3, iclass 4, count 0 2006.203.08:15:10.10#ibcon#read 3, iclass 4, count 0 2006.203.08:15:10.10#ibcon#about to read 4, iclass 4, count 0 2006.203.08:15:10.10#ibcon#read 4, iclass 4, count 0 2006.203.08:15:10.10#ibcon#about to read 5, iclass 4, count 0 2006.203.08:15:10.10#ibcon#read 5, iclass 4, count 0 2006.203.08:15:10.10#ibcon#about to read 6, iclass 4, count 0 2006.203.08:15:10.10#ibcon#read 6, iclass 4, count 0 2006.203.08:15:10.10#ibcon#end of sib2, iclass 4, count 0 2006.203.08:15:10.10#ibcon#*mode == 0, iclass 4, count 0 2006.203.08:15:10.10#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.203.08:15:10.10#ibcon#[26=FRQ=04,832.99\r\n] 2006.203.08:15:10.10#ibcon#*before write, iclass 4, count 0 2006.203.08:15:10.10#ibcon#enter sib2, iclass 4, count 0 2006.203.08:15:10.10#ibcon#flushed, iclass 4, count 0 2006.203.08:15:10.10#ibcon#about to write, iclass 4, count 0 2006.203.08:15:10.10#ibcon#wrote, iclass 4, count 0 2006.203.08:15:10.10#ibcon#about to read 3, iclass 4, count 0 2006.203.08:15:10.14#ibcon#read 3, iclass 4, count 0 2006.203.08:15:10.14#ibcon#about to read 4, iclass 4, count 0 2006.203.08:15:10.14#ibcon#read 4, iclass 4, count 0 2006.203.08:15:10.14#ibcon#about to read 5, iclass 4, count 0 2006.203.08:15:10.14#ibcon#read 5, iclass 4, count 0 2006.203.08:15:10.14#ibcon#about to read 6, iclass 4, count 0 2006.203.08:15:10.14#ibcon#read 6, iclass 4, count 0 2006.203.08:15:10.14#ibcon#end of sib2, iclass 4, count 0 2006.203.08:15:10.14#ibcon#*after write, iclass 4, count 0 2006.203.08:15:10.14#ibcon#*before return 0, iclass 4, count 0 2006.203.08:15:10.14#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.203.08:15:10.14#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.203.08:15:10.14#ibcon#about to clear, iclass 4 cls_cnt 0 2006.203.08:15:10.14#ibcon#cleared, iclass 4 cls_cnt 0 2006.203.08:15:10.14$vc4f8/va=4,7 2006.203.08:15:10.14#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.203.08:15:10.14#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.203.08:15:10.14#ibcon#ireg 11 cls_cnt 2 2006.203.08:15:10.14#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.203.08:15:10.20#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.203.08:15:10.20#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.203.08:15:10.20#ibcon#enter wrdev, iclass 6, count 2 2006.203.08:15:10.20#ibcon#first serial, iclass 6, count 2 2006.203.08:15:10.20#ibcon#enter sib2, iclass 6, count 2 2006.203.08:15:10.20#ibcon#flushed, iclass 6, count 2 2006.203.08:15:10.20#ibcon#about to write, iclass 6, count 2 2006.203.08:15:10.20#ibcon#wrote, iclass 6, count 2 2006.203.08:15:10.20#ibcon#about to read 3, iclass 6, count 2 2006.203.08:15:10.22#ibcon#read 3, iclass 6, count 2 2006.203.08:15:10.22#ibcon#about to read 4, iclass 6, count 2 2006.203.08:15:10.22#ibcon#read 4, iclass 6, count 2 2006.203.08:15:10.22#ibcon#about to read 5, iclass 6, count 2 2006.203.08:15:10.22#ibcon#read 5, iclass 6, count 2 2006.203.08:15:10.22#ibcon#about to read 6, iclass 6, count 2 2006.203.08:15:10.22#ibcon#read 6, iclass 6, count 2 2006.203.08:15:10.22#ibcon#end of sib2, iclass 6, count 2 2006.203.08:15:10.22#ibcon#*mode == 0, iclass 6, count 2 2006.203.08:15:10.22#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.203.08:15:10.22#ibcon#[25=AT04-07\r\n] 2006.203.08:15:10.22#ibcon#*before write, iclass 6, count 2 2006.203.08:15:10.22#ibcon#enter sib2, iclass 6, count 2 2006.203.08:15:10.22#ibcon#flushed, iclass 6, count 2 2006.203.08:15:10.22#ibcon#about to write, iclass 6, count 2 2006.203.08:15:10.22#ibcon#wrote, iclass 6, count 2 2006.203.08:15:10.22#ibcon#about to read 3, iclass 6, count 2 2006.203.08:15:10.25#ibcon#read 3, iclass 6, count 2 2006.203.08:15:10.25#ibcon#about to read 4, iclass 6, count 2 2006.203.08:15:10.25#ibcon#read 4, iclass 6, count 2 2006.203.08:15:10.25#ibcon#about to read 5, iclass 6, count 2 2006.203.08:15:10.25#ibcon#read 5, iclass 6, count 2 2006.203.08:15:10.25#ibcon#about to read 6, iclass 6, count 2 2006.203.08:15:10.25#ibcon#read 6, iclass 6, count 2 2006.203.08:15:10.25#ibcon#end of sib2, iclass 6, count 2 2006.203.08:15:10.25#ibcon#*after write, iclass 6, count 2 2006.203.08:15:10.25#ibcon#*before return 0, iclass 6, count 2 2006.203.08:15:10.25#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.203.08:15:10.25#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.203.08:15:10.25#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.203.08:15:10.25#ibcon#ireg 7 cls_cnt 0 2006.203.08:15:10.25#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.203.08:15:10.37#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.203.08:15:10.37#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.203.08:15:10.37#ibcon#enter wrdev, iclass 6, count 0 2006.203.08:15:10.37#ibcon#first serial, iclass 6, count 0 2006.203.08:15:10.37#ibcon#enter sib2, iclass 6, count 0 2006.203.08:15:10.37#ibcon#flushed, iclass 6, count 0 2006.203.08:15:10.37#ibcon#about to write, iclass 6, count 0 2006.203.08:15:10.37#ibcon#wrote, iclass 6, count 0 2006.203.08:15:10.37#ibcon#about to read 3, iclass 6, count 0 2006.203.08:15:10.39#ibcon#read 3, iclass 6, count 0 2006.203.08:15:10.39#ibcon#about to read 4, iclass 6, count 0 2006.203.08:15:10.39#ibcon#read 4, iclass 6, count 0 2006.203.08:15:10.39#ibcon#about to read 5, iclass 6, count 0 2006.203.08:15:10.39#ibcon#read 5, iclass 6, count 0 2006.203.08:15:10.39#ibcon#about to read 6, iclass 6, count 0 2006.203.08:15:10.39#ibcon#read 6, iclass 6, count 0 2006.203.08:15:10.39#ibcon#end of sib2, iclass 6, count 0 2006.203.08:15:10.39#ibcon#*mode == 0, iclass 6, count 0 2006.203.08:15:10.39#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.203.08:15:10.39#ibcon#[25=USB\r\n] 2006.203.08:15:10.39#ibcon#*before write, iclass 6, count 0 2006.203.08:15:10.39#ibcon#enter sib2, iclass 6, count 0 2006.203.08:15:10.39#ibcon#flushed, iclass 6, count 0 2006.203.08:15:10.39#ibcon#about to write, iclass 6, count 0 2006.203.08:15:10.39#ibcon#wrote, iclass 6, count 0 2006.203.08:15:10.39#ibcon#about to read 3, iclass 6, count 0 2006.203.08:15:10.42#ibcon#read 3, iclass 6, count 0 2006.203.08:15:10.42#ibcon#about to read 4, iclass 6, count 0 2006.203.08:15:10.42#ibcon#read 4, iclass 6, count 0 2006.203.08:15:10.42#ibcon#about to read 5, iclass 6, count 0 2006.203.08:15:10.42#ibcon#read 5, iclass 6, count 0 2006.203.08:15:10.42#ibcon#about to read 6, iclass 6, count 0 2006.203.08:15:10.42#ibcon#read 6, iclass 6, count 0 2006.203.08:15:10.42#ibcon#end of sib2, iclass 6, count 0 2006.203.08:15:10.42#ibcon#*after write, iclass 6, count 0 2006.203.08:15:10.42#ibcon#*before return 0, iclass 6, count 0 2006.203.08:15:10.42#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.203.08:15:10.42#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.203.08:15:10.42#ibcon#about to clear, iclass 6 cls_cnt 0 2006.203.08:15:10.42#ibcon#cleared, iclass 6 cls_cnt 0 2006.203.08:15:10.42$vc4f8/valo=5,652.99 2006.203.08:15:10.42#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.203.08:15:10.42#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.203.08:15:10.42#ibcon#ireg 17 cls_cnt 0 2006.203.08:15:10.42#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.203.08:15:10.42#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.203.08:15:10.42#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.203.08:15:10.42#ibcon#enter wrdev, iclass 10, count 0 2006.203.08:15:10.42#ibcon#first serial, iclass 10, count 0 2006.203.08:15:10.42#ibcon#enter sib2, iclass 10, count 0 2006.203.08:15:10.42#ibcon#flushed, iclass 10, count 0 2006.203.08:15:10.42#ibcon#about to write, iclass 10, count 0 2006.203.08:15:10.42#ibcon#wrote, iclass 10, count 0 2006.203.08:15:10.42#ibcon#about to read 3, iclass 10, count 0 2006.203.08:15:10.44#ibcon#read 3, iclass 10, count 0 2006.203.08:15:10.44#ibcon#about to read 4, iclass 10, count 0 2006.203.08:15:10.44#ibcon#read 4, iclass 10, count 0 2006.203.08:15:10.44#ibcon#about to read 5, iclass 10, count 0 2006.203.08:15:10.44#ibcon#read 5, iclass 10, count 0 2006.203.08:15:10.44#ibcon#about to read 6, iclass 10, count 0 2006.203.08:15:10.44#ibcon#read 6, iclass 10, count 0 2006.203.08:15:10.44#ibcon#end of sib2, iclass 10, count 0 2006.203.08:15:10.44#ibcon#*mode == 0, iclass 10, count 0 2006.203.08:15:10.44#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.203.08:15:10.44#ibcon#[26=FRQ=05,652.99\r\n] 2006.203.08:15:10.44#ibcon#*before write, iclass 10, count 0 2006.203.08:15:10.44#ibcon#enter sib2, iclass 10, count 0 2006.203.08:15:10.44#ibcon#flushed, iclass 10, count 0 2006.203.08:15:10.44#ibcon#about to write, iclass 10, count 0 2006.203.08:15:10.44#ibcon#wrote, iclass 10, count 0 2006.203.08:15:10.44#ibcon#about to read 3, iclass 10, count 0 2006.203.08:15:10.48#ibcon#read 3, iclass 10, count 0 2006.203.08:15:10.48#ibcon#about to read 4, iclass 10, count 0 2006.203.08:15:10.48#ibcon#read 4, iclass 10, count 0 2006.203.08:15:10.48#ibcon#about to read 5, iclass 10, count 0 2006.203.08:15:10.48#ibcon#read 5, iclass 10, count 0 2006.203.08:15:10.48#ibcon#about to read 6, iclass 10, count 0 2006.203.08:15:10.48#ibcon#read 6, iclass 10, count 0 2006.203.08:15:10.48#ibcon#end of sib2, iclass 10, count 0 2006.203.08:15:10.48#ibcon#*after write, iclass 10, count 0 2006.203.08:15:10.48#ibcon#*before return 0, iclass 10, count 0 2006.203.08:15:10.48#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.203.08:15:10.48#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.203.08:15:10.48#ibcon#about to clear, iclass 10 cls_cnt 0 2006.203.08:15:10.48#ibcon#cleared, iclass 10 cls_cnt 0 2006.203.08:15:10.48$vc4f8/va=5,7 2006.203.08:15:10.48#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.203.08:15:10.48#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.203.08:15:10.48#ibcon#ireg 11 cls_cnt 2 2006.203.08:15:10.48#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.203.08:15:10.54#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.203.08:15:10.54#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.203.08:15:10.54#ibcon#enter wrdev, iclass 12, count 2 2006.203.08:15:10.54#ibcon#first serial, iclass 12, count 2 2006.203.08:15:10.54#ibcon#enter sib2, iclass 12, count 2 2006.203.08:15:10.54#ibcon#flushed, iclass 12, count 2 2006.203.08:15:10.54#ibcon#about to write, iclass 12, count 2 2006.203.08:15:10.54#ibcon#wrote, iclass 12, count 2 2006.203.08:15:10.54#ibcon#about to read 3, iclass 12, count 2 2006.203.08:15:10.56#ibcon#read 3, iclass 12, count 2 2006.203.08:15:10.56#ibcon#about to read 4, iclass 12, count 2 2006.203.08:15:10.56#ibcon#read 4, iclass 12, count 2 2006.203.08:15:10.56#ibcon#about to read 5, iclass 12, count 2 2006.203.08:15:10.56#ibcon#read 5, iclass 12, count 2 2006.203.08:15:10.56#ibcon#about to read 6, iclass 12, count 2 2006.203.08:15:10.56#ibcon#read 6, iclass 12, count 2 2006.203.08:15:10.56#ibcon#end of sib2, iclass 12, count 2 2006.203.08:15:10.56#ibcon#*mode == 0, iclass 12, count 2 2006.203.08:15:10.56#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.203.08:15:10.56#ibcon#[25=AT05-07\r\n] 2006.203.08:15:10.56#ibcon#*before write, iclass 12, count 2 2006.203.08:15:10.56#ibcon#enter sib2, iclass 12, count 2 2006.203.08:15:10.56#ibcon#flushed, iclass 12, count 2 2006.203.08:15:10.56#ibcon#about to write, iclass 12, count 2 2006.203.08:15:10.56#ibcon#wrote, iclass 12, count 2 2006.203.08:15:10.56#ibcon#about to read 3, iclass 12, count 2 2006.203.08:15:10.59#ibcon#read 3, iclass 12, count 2 2006.203.08:15:10.59#ibcon#about to read 4, iclass 12, count 2 2006.203.08:15:10.59#ibcon#read 4, iclass 12, count 2 2006.203.08:15:10.59#ibcon#about to read 5, iclass 12, count 2 2006.203.08:15:10.59#ibcon#read 5, iclass 12, count 2 2006.203.08:15:10.59#ibcon#about to read 6, iclass 12, count 2 2006.203.08:15:10.59#ibcon#read 6, iclass 12, count 2 2006.203.08:15:10.59#ibcon#end of sib2, iclass 12, count 2 2006.203.08:15:10.59#ibcon#*after write, iclass 12, count 2 2006.203.08:15:10.59#ibcon#*before return 0, iclass 12, count 2 2006.203.08:15:10.59#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.203.08:15:10.59#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.203.08:15:10.59#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.203.08:15:10.59#ibcon#ireg 7 cls_cnt 0 2006.203.08:15:10.59#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.203.08:15:10.71#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.203.08:15:10.71#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.203.08:15:10.71#ibcon#enter wrdev, iclass 12, count 0 2006.203.08:15:10.71#ibcon#first serial, iclass 12, count 0 2006.203.08:15:10.71#ibcon#enter sib2, iclass 12, count 0 2006.203.08:15:10.71#ibcon#flushed, iclass 12, count 0 2006.203.08:15:10.71#ibcon#about to write, iclass 12, count 0 2006.203.08:15:10.71#ibcon#wrote, iclass 12, count 0 2006.203.08:15:10.71#ibcon#about to read 3, iclass 12, count 0 2006.203.08:15:10.73#ibcon#read 3, iclass 12, count 0 2006.203.08:15:10.73#ibcon#about to read 4, iclass 12, count 0 2006.203.08:15:10.73#ibcon#read 4, iclass 12, count 0 2006.203.08:15:10.73#ibcon#about to read 5, iclass 12, count 0 2006.203.08:15:10.73#ibcon#read 5, iclass 12, count 0 2006.203.08:15:10.73#ibcon#about to read 6, iclass 12, count 0 2006.203.08:15:10.73#ibcon#read 6, iclass 12, count 0 2006.203.08:15:10.73#ibcon#end of sib2, iclass 12, count 0 2006.203.08:15:10.73#ibcon#*mode == 0, iclass 12, count 0 2006.203.08:15:10.73#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.203.08:15:10.73#ibcon#[25=USB\r\n] 2006.203.08:15:10.73#ibcon#*before write, iclass 12, count 0 2006.203.08:15:10.73#ibcon#enter sib2, iclass 12, count 0 2006.203.08:15:10.73#ibcon#flushed, iclass 12, count 0 2006.203.08:15:10.73#ibcon#about to write, iclass 12, count 0 2006.203.08:15:10.73#ibcon#wrote, iclass 12, count 0 2006.203.08:15:10.73#ibcon#about to read 3, iclass 12, count 0 2006.203.08:15:10.76#ibcon#read 3, iclass 12, count 0 2006.203.08:15:10.76#ibcon#about to read 4, iclass 12, count 0 2006.203.08:15:10.76#ibcon#read 4, iclass 12, count 0 2006.203.08:15:10.76#ibcon#about to read 5, iclass 12, count 0 2006.203.08:15:10.76#ibcon#read 5, iclass 12, count 0 2006.203.08:15:10.76#ibcon#about to read 6, iclass 12, count 0 2006.203.08:15:10.76#ibcon#read 6, iclass 12, count 0 2006.203.08:15:10.76#ibcon#end of sib2, iclass 12, count 0 2006.203.08:15:10.76#ibcon#*after write, iclass 12, count 0 2006.203.08:15:10.76#ibcon#*before return 0, iclass 12, count 0 2006.203.08:15:10.76#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.203.08:15:10.76#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.203.08:15:10.76#ibcon#about to clear, iclass 12 cls_cnt 0 2006.203.08:15:10.76#ibcon#cleared, iclass 12 cls_cnt 0 2006.203.08:15:10.76$vc4f8/valo=6,772.99 2006.203.08:15:10.76#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.203.08:15:10.76#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.203.08:15:10.76#ibcon#ireg 17 cls_cnt 0 2006.203.08:15:10.76#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.203.08:15:10.76#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.203.08:15:10.76#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.203.08:15:10.76#ibcon#enter wrdev, iclass 14, count 0 2006.203.08:15:10.76#ibcon#first serial, iclass 14, count 0 2006.203.08:15:10.76#ibcon#enter sib2, iclass 14, count 0 2006.203.08:15:10.76#ibcon#flushed, iclass 14, count 0 2006.203.08:15:10.76#ibcon#about to write, iclass 14, count 0 2006.203.08:15:10.76#ibcon#wrote, iclass 14, count 0 2006.203.08:15:10.76#ibcon#about to read 3, iclass 14, count 0 2006.203.08:15:10.79#ibcon#read 3, iclass 14, count 0 2006.203.08:15:10.79#ibcon#about to read 4, iclass 14, count 0 2006.203.08:15:10.79#ibcon#read 4, iclass 14, count 0 2006.203.08:15:10.79#ibcon#about to read 5, iclass 14, count 0 2006.203.08:15:10.79#ibcon#read 5, iclass 14, count 0 2006.203.08:15:10.79#ibcon#about to read 6, iclass 14, count 0 2006.203.08:15:10.79#ibcon#read 6, iclass 14, count 0 2006.203.08:15:10.79#ibcon#end of sib2, iclass 14, count 0 2006.203.08:15:10.79#ibcon#*mode == 0, iclass 14, count 0 2006.203.08:15:10.79#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.203.08:15:10.79#ibcon#[26=FRQ=06,772.99\r\n] 2006.203.08:15:10.79#ibcon#*before write, iclass 14, count 0 2006.203.08:15:10.79#ibcon#enter sib2, iclass 14, count 0 2006.203.08:15:10.79#ibcon#flushed, iclass 14, count 0 2006.203.08:15:10.79#ibcon#about to write, iclass 14, count 0 2006.203.08:15:10.79#ibcon#wrote, iclass 14, count 0 2006.203.08:15:10.79#ibcon#about to read 3, iclass 14, count 0 2006.203.08:15:10.83#ibcon#read 3, iclass 14, count 0 2006.203.08:15:10.83#ibcon#about to read 4, iclass 14, count 0 2006.203.08:15:10.83#ibcon#read 4, iclass 14, count 0 2006.203.08:15:10.83#ibcon#about to read 5, iclass 14, count 0 2006.203.08:15:10.83#ibcon#read 5, iclass 14, count 0 2006.203.08:15:10.83#ibcon#about to read 6, iclass 14, count 0 2006.203.08:15:10.83#ibcon#read 6, iclass 14, count 0 2006.203.08:15:10.83#ibcon#end of sib2, iclass 14, count 0 2006.203.08:15:10.83#ibcon#*after write, iclass 14, count 0 2006.203.08:15:10.83#ibcon#*before return 0, iclass 14, count 0 2006.203.08:15:10.83#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.203.08:15:10.83#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.203.08:15:10.83#ibcon#about to clear, iclass 14 cls_cnt 0 2006.203.08:15:10.83#ibcon#cleared, iclass 14 cls_cnt 0 2006.203.08:15:10.83$vc4f8/va=6,6 2006.203.08:15:10.83#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.203.08:15:10.83#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.203.08:15:10.83#ibcon#ireg 11 cls_cnt 2 2006.203.08:15:10.83#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.203.08:15:10.88#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.203.08:15:10.88#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.203.08:15:10.88#ibcon#enter wrdev, iclass 16, count 2 2006.203.08:15:10.88#ibcon#first serial, iclass 16, count 2 2006.203.08:15:10.88#ibcon#enter sib2, iclass 16, count 2 2006.203.08:15:10.88#ibcon#flushed, iclass 16, count 2 2006.203.08:15:10.88#ibcon#about to write, iclass 16, count 2 2006.203.08:15:10.88#ibcon#wrote, iclass 16, count 2 2006.203.08:15:10.88#ibcon#about to read 3, iclass 16, count 2 2006.203.08:15:10.90#ibcon#read 3, iclass 16, count 2 2006.203.08:15:10.90#ibcon#about to read 4, iclass 16, count 2 2006.203.08:15:10.90#ibcon#read 4, iclass 16, count 2 2006.203.08:15:10.90#ibcon#about to read 5, iclass 16, count 2 2006.203.08:15:10.90#ibcon#read 5, iclass 16, count 2 2006.203.08:15:10.90#ibcon#about to read 6, iclass 16, count 2 2006.203.08:15:10.90#ibcon#read 6, iclass 16, count 2 2006.203.08:15:10.90#ibcon#end of sib2, iclass 16, count 2 2006.203.08:15:10.90#ibcon#*mode == 0, iclass 16, count 2 2006.203.08:15:10.90#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.203.08:15:10.90#ibcon#[25=AT06-06\r\n] 2006.203.08:15:10.90#ibcon#*before write, iclass 16, count 2 2006.203.08:15:10.90#ibcon#enter sib2, iclass 16, count 2 2006.203.08:15:10.90#ibcon#flushed, iclass 16, count 2 2006.203.08:15:10.90#ibcon#about to write, iclass 16, count 2 2006.203.08:15:10.90#ibcon#wrote, iclass 16, count 2 2006.203.08:15:10.90#ibcon#about to read 3, iclass 16, count 2 2006.203.08:15:10.93#ibcon#read 3, iclass 16, count 2 2006.203.08:15:10.93#ibcon#about to read 4, iclass 16, count 2 2006.203.08:15:10.93#ibcon#read 4, iclass 16, count 2 2006.203.08:15:10.93#ibcon#about to read 5, iclass 16, count 2 2006.203.08:15:10.93#ibcon#read 5, iclass 16, count 2 2006.203.08:15:10.93#ibcon#about to read 6, iclass 16, count 2 2006.203.08:15:10.93#ibcon#read 6, iclass 16, count 2 2006.203.08:15:10.93#ibcon#end of sib2, iclass 16, count 2 2006.203.08:15:10.93#ibcon#*after write, iclass 16, count 2 2006.203.08:15:10.93#ibcon#*before return 0, iclass 16, count 2 2006.203.08:15:10.93#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.203.08:15:10.93#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.203.08:15:10.93#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.203.08:15:10.93#ibcon#ireg 7 cls_cnt 0 2006.203.08:15:10.93#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.203.08:15:11.05#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.203.08:15:11.05#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.203.08:15:11.05#ibcon#enter wrdev, iclass 16, count 0 2006.203.08:15:11.05#ibcon#first serial, iclass 16, count 0 2006.203.08:15:11.05#ibcon#enter sib2, iclass 16, count 0 2006.203.08:15:11.05#ibcon#flushed, iclass 16, count 0 2006.203.08:15:11.05#ibcon#about to write, iclass 16, count 0 2006.203.08:15:11.05#ibcon#wrote, iclass 16, count 0 2006.203.08:15:11.05#ibcon#about to read 3, iclass 16, count 0 2006.203.08:15:11.07#ibcon#read 3, iclass 16, count 0 2006.203.08:15:11.07#ibcon#about to read 4, iclass 16, count 0 2006.203.08:15:11.07#ibcon#read 4, iclass 16, count 0 2006.203.08:15:11.07#ibcon#about to read 5, iclass 16, count 0 2006.203.08:15:11.07#ibcon#read 5, iclass 16, count 0 2006.203.08:15:11.07#ibcon#about to read 6, iclass 16, count 0 2006.203.08:15:11.07#ibcon#read 6, iclass 16, count 0 2006.203.08:15:11.07#ibcon#end of sib2, iclass 16, count 0 2006.203.08:15:11.07#ibcon#*mode == 0, iclass 16, count 0 2006.203.08:15:11.07#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.203.08:15:11.07#ibcon#[25=USB\r\n] 2006.203.08:15:11.07#ibcon#*before write, iclass 16, count 0 2006.203.08:15:11.07#ibcon#enter sib2, iclass 16, count 0 2006.203.08:15:11.07#ibcon#flushed, iclass 16, count 0 2006.203.08:15:11.07#ibcon#about to write, iclass 16, count 0 2006.203.08:15:11.07#ibcon#wrote, iclass 16, count 0 2006.203.08:15:11.07#ibcon#about to read 3, iclass 16, count 0 2006.203.08:15:11.10#ibcon#read 3, iclass 16, count 0 2006.203.08:15:11.10#ibcon#about to read 4, iclass 16, count 0 2006.203.08:15:11.10#ibcon#read 4, iclass 16, count 0 2006.203.08:15:11.10#ibcon#about to read 5, iclass 16, count 0 2006.203.08:15:11.10#ibcon#read 5, iclass 16, count 0 2006.203.08:15:11.10#ibcon#about to read 6, iclass 16, count 0 2006.203.08:15:11.10#ibcon#read 6, iclass 16, count 0 2006.203.08:15:11.10#ibcon#end of sib2, iclass 16, count 0 2006.203.08:15:11.10#ibcon#*after write, iclass 16, count 0 2006.203.08:15:11.10#ibcon#*before return 0, iclass 16, count 0 2006.203.08:15:11.10#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.203.08:15:11.10#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.203.08:15:11.10#ibcon#about to clear, iclass 16 cls_cnt 0 2006.203.08:15:11.10#ibcon#cleared, iclass 16 cls_cnt 0 2006.203.08:15:11.10$vc4f8/valo=7,832.99 2006.203.08:15:11.10#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.203.08:15:11.10#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.203.08:15:11.10#ibcon#ireg 17 cls_cnt 0 2006.203.08:15:11.10#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.203.08:15:11.10#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.203.08:15:11.10#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.203.08:15:11.10#ibcon#enter wrdev, iclass 18, count 0 2006.203.08:15:11.10#ibcon#first serial, iclass 18, count 0 2006.203.08:15:11.10#ibcon#enter sib2, iclass 18, count 0 2006.203.08:15:11.10#ibcon#flushed, iclass 18, count 0 2006.203.08:15:11.10#ibcon#about to write, iclass 18, count 0 2006.203.08:15:11.10#ibcon#wrote, iclass 18, count 0 2006.203.08:15:11.10#ibcon#about to read 3, iclass 18, count 0 2006.203.08:15:11.12#ibcon#read 3, iclass 18, count 0 2006.203.08:15:11.12#ibcon#about to read 4, iclass 18, count 0 2006.203.08:15:11.12#ibcon#read 4, iclass 18, count 0 2006.203.08:15:11.12#ibcon#about to read 5, iclass 18, count 0 2006.203.08:15:11.12#ibcon#read 5, iclass 18, count 0 2006.203.08:15:11.12#ibcon#about to read 6, iclass 18, count 0 2006.203.08:15:11.12#ibcon#read 6, iclass 18, count 0 2006.203.08:15:11.12#ibcon#end of sib2, iclass 18, count 0 2006.203.08:15:11.12#ibcon#*mode == 0, iclass 18, count 0 2006.203.08:15:11.12#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.203.08:15:11.12#ibcon#[26=FRQ=07,832.99\r\n] 2006.203.08:15:11.12#ibcon#*before write, iclass 18, count 0 2006.203.08:15:11.12#ibcon#enter sib2, iclass 18, count 0 2006.203.08:15:11.12#ibcon#flushed, iclass 18, count 0 2006.203.08:15:11.12#ibcon#about to write, iclass 18, count 0 2006.203.08:15:11.12#ibcon#wrote, iclass 18, count 0 2006.203.08:15:11.12#ibcon#about to read 3, iclass 18, count 0 2006.203.08:15:11.16#ibcon#read 3, iclass 18, count 0 2006.203.08:15:11.16#ibcon#about to read 4, iclass 18, count 0 2006.203.08:15:11.16#ibcon#read 4, iclass 18, count 0 2006.203.08:15:11.16#ibcon#about to read 5, iclass 18, count 0 2006.203.08:15:11.16#ibcon#read 5, iclass 18, count 0 2006.203.08:15:11.16#ibcon#about to read 6, iclass 18, count 0 2006.203.08:15:11.16#ibcon#read 6, iclass 18, count 0 2006.203.08:15:11.16#ibcon#end of sib2, iclass 18, count 0 2006.203.08:15:11.16#ibcon#*after write, iclass 18, count 0 2006.203.08:15:11.16#ibcon#*before return 0, iclass 18, count 0 2006.203.08:15:11.16#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.203.08:15:11.16#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.203.08:15:11.16#ibcon#about to clear, iclass 18 cls_cnt 0 2006.203.08:15:11.16#ibcon#cleared, iclass 18 cls_cnt 0 2006.203.08:15:11.16$vc4f8/va=7,7 2006.203.08:15:11.16#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.203.08:15:11.16#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.203.08:15:11.16#ibcon#ireg 11 cls_cnt 2 2006.203.08:15:11.16#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.203.08:15:11.22#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.203.08:15:11.22#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.203.08:15:11.22#ibcon#enter wrdev, iclass 20, count 2 2006.203.08:15:11.22#ibcon#first serial, iclass 20, count 2 2006.203.08:15:11.22#ibcon#enter sib2, iclass 20, count 2 2006.203.08:15:11.22#ibcon#flushed, iclass 20, count 2 2006.203.08:15:11.22#ibcon#about to write, iclass 20, count 2 2006.203.08:15:11.22#ibcon#wrote, iclass 20, count 2 2006.203.08:15:11.22#ibcon#about to read 3, iclass 20, count 2 2006.203.08:15:11.24#ibcon#read 3, iclass 20, count 2 2006.203.08:15:11.24#ibcon#about to read 4, iclass 20, count 2 2006.203.08:15:11.24#ibcon#read 4, iclass 20, count 2 2006.203.08:15:11.24#ibcon#about to read 5, iclass 20, count 2 2006.203.08:15:11.24#ibcon#read 5, iclass 20, count 2 2006.203.08:15:11.24#ibcon#about to read 6, iclass 20, count 2 2006.203.08:15:11.24#ibcon#read 6, iclass 20, count 2 2006.203.08:15:11.24#ibcon#end of sib2, iclass 20, count 2 2006.203.08:15:11.24#ibcon#*mode == 0, iclass 20, count 2 2006.203.08:15:11.24#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.203.08:15:11.24#ibcon#[25=AT07-07\r\n] 2006.203.08:15:11.24#ibcon#*before write, iclass 20, count 2 2006.203.08:15:11.24#ibcon#enter sib2, iclass 20, count 2 2006.203.08:15:11.24#ibcon#flushed, iclass 20, count 2 2006.203.08:15:11.24#ibcon#about to write, iclass 20, count 2 2006.203.08:15:11.24#ibcon#wrote, iclass 20, count 2 2006.203.08:15:11.24#ibcon#about to read 3, iclass 20, count 2 2006.203.08:15:11.27#ibcon#read 3, iclass 20, count 2 2006.203.08:15:11.27#ibcon#about to read 4, iclass 20, count 2 2006.203.08:15:11.27#ibcon#read 4, iclass 20, count 2 2006.203.08:15:11.27#ibcon#about to read 5, iclass 20, count 2 2006.203.08:15:11.27#ibcon#read 5, iclass 20, count 2 2006.203.08:15:11.27#ibcon#about to read 6, iclass 20, count 2 2006.203.08:15:11.27#ibcon#read 6, iclass 20, count 2 2006.203.08:15:11.27#ibcon#end of sib2, iclass 20, count 2 2006.203.08:15:11.27#ibcon#*after write, iclass 20, count 2 2006.203.08:15:11.27#ibcon#*before return 0, iclass 20, count 2 2006.203.08:15:11.27#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.203.08:15:11.27#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.203.08:15:11.27#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.203.08:15:11.27#ibcon#ireg 7 cls_cnt 0 2006.203.08:15:11.27#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.203.08:15:11.39#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.203.08:15:11.39#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.203.08:15:11.39#ibcon#enter wrdev, iclass 20, count 0 2006.203.08:15:11.39#ibcon#first serial, iclass 20, count 0 2006.203.08:15:11.39#ibcon#enter sib2, iclass 20, count 0 2006.203.08:15:11.39#ibcon#flushed, iclass 20, count 0 2006.203.08:15:11.39#ibcon#about to write, iclass 20, count 0 2006.203.08:15:11.39#ibcon#wrote, iclass 20, count 0 2006.203.08:15:11.39#ibcon#about to read 3, iclass 20, count 0 2006.203.08:15:11.41#ibcon#read 3, iclass 20, count 0 2006.203.08:15:11.41#ibcon#about to read 4, iclass 20, count 0 2006.203.08:15:11.41#ibcon#read 4, iclass 20, count 0 2006.203.08:15:11.41#ibcon#about to read 5, iclass 20, count 0 2006.203.08:15:11.41#ibcon#read 5, iclass 20, count 0 2006.203.08:15:11.41#ibcon#about to read 6, iclass 20, count 0 2006.203.08:15:11.41#ibcon#read 6, iclass 20, count 0 2006.203.08:15:11.41#ibcon#end of sib2, iclass 20, count 0 2006.203.08:15:11.41#ibcon#*mode == 0, iclass 20, count 0 2006.203.08:15:11.41#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.203.08:15:11.41#ibcon#[25=USB\r\n] 2006.203.08:15:11.41#ibcon#*before write, iclass 20, count 0 2006.203.08:15:11.41#ibcon#enter sib2, iclass 20, count 0 2006.203.08:15:11.41#ibcon#flushed, iclass 20, count 0 2006.203.08:15:11.41#ibcon#about to write, iclass 20, count 0 2006.203.08:15:11.41#ibcon#wrote, iclass 20, count 0 2006.203.08:15:11.41#ibcon#about to read 3, iclass 20, count 0 2006.203.08:15:11.44#ibcon#read 3, iclass 20, count 0 2006.203.08:15:11.44#ibcon#about to read 4, iclass 20, count 0 2006.203.08:15:11.44#ibcon#read 4, iclass 20, count 0 2006.203.08:15:11.44#ibcon#about to read 5, iclass 20, count 0 2006.203.08:15:11.44#ibcon#read 5, iclass 20, count 0 2006.203.08:15:11.44#ibcon#about to read 6, iclass 20, count 0 2006.203.08:15:11.44#ibcon#read 6, iclass 20, count 0 2006.203.08:15:11.44#ibcon#end of sib2, iclass 20, count 0 2006.203.08:15:11.44#ibcon#*after write, iclass 20, count 0 2006.203.08:15:11.44#ibcon#*before return 0, iclass 20, count 0 2006.203.08:15:11.44#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.203.08:15:11.44#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.203.08:15:11.44#ibcon#about to clear, iclass 20 cls_cnt 0 2006.203.08:15:11.44#ibcon#cleared, iclass 20 cls_cnt 0 2006.203.08:15:11.44$vc4f8/valo=8,852.99 2006.203.08:15:11.44#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.203.08:15:11.44#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.203.08:15:11.44#ibcon#ireg 17 cls_cnt 0 2006.203.08:15:11.44#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.203.08:15:11.44#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.203.08:15:11.44#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.203.08:15:11.44#ibcon#enter wrdev, iclass 22, count 0 2006.203.08:15:11.44#ibcon#first serial, iclass 22, count 0 2006.203.08:15:11.44#ibcon#enter sib2, iclass 22, count 0 2006.203.08:15:11.44#ibcon#flushed, iclass 22, count 0 2006.203.08:15:11.44#ibcon#about to write, iclass 22, count 0 2006.203.08:15:11.44#ibcon#wrote, iclass 22, count 0 2006.203.08:15:11.44#ibcon#about to read 3, iclass 22, count 0 2006.203.08:15:11.47#ibcon#read 3, iclass 22, count 0 2006.203.08:15:11.47#ibcon#about to read 4, iclass 22, count 0 2006.203.08:15:11.47#ibcon#read 4, iclass 22, count 0 2006.203.08:15:11.47#ibcon#about to read 5, iclass 22, count 0 2006.203.08:15:11.47#ibcon#read 5, iclass 22, count 0 2006.203.08:15:11.47#ibcon#about to read 6, iclass 22, count 0 2006.203.08:15:11.47#ibcon#read 6, iclass 22, count 0 2006.203.08:15:11.47#ibcon#end of sib2, iclass 22, count 0 2006.203.08:15:11.47#ibcon#*mode == 0, iclass 22, count 0 2006.203.08:15:11.47#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.203.08:15:11.47#ibcon#[26=FRQ=08,852.99\r\n] 2006.203.08:15:11.47#ibcon#*before write, iclass 22, count 0 2006.203.08:15:11.47#ibcon#enter sib2, iclass 22, count 0 2006.203.08:15:11.47#ibcon#flushed, iclass 22, count 0 2006.203.08:15:11.47#ibcon#about to write, iclass 22, count 0 2006.203.08:15:11.47#ibcon#wrote, iclass 22, count 0 2006.203.08:15:11.47#ibcon#about to read 3, iclass 22, count 0 2006.203.08:15:11.51#ibcon#read 3, iclass 22, count 0 2006.203.08:15:11.51#ibcon#about to read 4, iclass 22, count 0 2006.203.08:15:11.51#ibcon#read 4, iclass 22, count 0 2006.203.08:15:11.51#ibcon#about to read 5, iclass 22, count 0 2006.203.08:15:11.51#ibcon#read 5, iclass 22, count 0 2006.203.08:15:11.51#ibcon#about to read 6, iclass 22, count 0 2006.203.08:15:11.51#ibcon#read 6, iclass 22, count 0 2006.203.08:15:11.51#ibcon#end of sib2, iclass 22, count 0 2006.203.08:15:11.51#ibcon#*after write, iclass 22, count 0 2006.203.08:15:11.51#ibcon#*before return 0, iclass 22, count 0 2006.203.08:15:11.51#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.203.08:15:11.51#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.203.08:15:11.51#ibcon#about to clear, iclass 22 cls_cnt 0 2006.203.08:15:11.51#ibcon#cleared, iclass 22 cls_cnt 0 2006.203.08:15:11.51$vc4f8/va=8,6 2006.203.08:15:11.51#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.203.08:15:11.51#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.203.08:15:11.51#ibcon#ireg 11 cls_cnt 2 2006.203.08:15:11.51#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.203.08:15:11.57#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.203.08:15:11.57#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.203.08:15:11.57#ibcon#enter wrdev, iclass 24, count 2 2006.203.08:15:11.57#ibcon#first serial, iclass 24, count 2 2006.203.08:15:11.57#ibcon#enter sib2, iclass 24, count 2 2006.203.08:15:11.57#ibcon#flushed, iclass 24, count 2 2006.203.08:15:11.57#ibcon#about to write, iclass 24, count 2 2006.203.08:15:11.57#ibcon#wrote, iclass 24, count 2 2006.203.08:15:11.57#ibcon#about to read 3, iclass 24, count 2 2006.203.08:15:11.58#ibcon#read 3, iclass 24, count 2 2006.203.08:15:11.58#ibcon#about to read 4, iclass 24, count 2 2006.203.08:15:11.58#ibcon#read 4, iclass 24, count 2 2006.203.08:15:11.58#ibcon#about to read 5, iclass 24, count 2 2006.203.08:15:11.58#ibcon#read 5, iclass 24, count 2 2006.203.08:15:11.58#ibcon#about to read 6, iclass 24, count 2 2006.203.08:15:11.58#ibcon#read 6, iclass 24, count 2 2006.203.08:15:11.58#ibcon#end of sib2, iclass 24, count 2 2006.203.08:15:11.58#ibcon#*mode == 0, iclass 24, count 2 2006.203.08:15:11.58#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.203.08:15:11.58#ibcon#[25=AT08-06\r\n] 2006.203.08:15:11.58#ibcon#*before write, iclass 24, count 2 2006.203.08:15:11.58#ibcon#enter sib2, iclass 24, count 2 2006.203.08:15:11.58#ibcon#flushed, iclass 24, count 2 2006.203.08:15:11.58#ibcon#about to write, iclass 24, count 2 2006.203.08:15:11.58#ibcon#wrote, iclass 24, count 2 2006.203.08:15:11.58#ibcon#about to read 3, iclass 24, count 2 2006.203.08:15:11.61#ibcon#read 3, iclass 24, count 2 2006.203.08:15:11.61#ibcon#about to read 4, iclass 24, count 2 2006.203.08:15:11.61#ibcon#read 4, iclass 24, count 2 2006.203.08:15:11.61#ibcon#about to read 5, iclass 24, count 2 2006.203.08:15:11.61#ibcon#read 5, iclass 24, count 2 2006.203.08:15:11.61#ibcon#about to read 6, iclass 24, count 2 2006.203.08:15:11.61#ibcon#read 6, iclass 24, count 2 2006.203.08:15:11.61#ibcon#end of sib2, iclass 24, count 2 2006.203.08:15:11.61#ibcon#*after write, iclass 24, count 2 2006.203.08:15:11.61#ibcon#*before return 0, iclass 24, count 2 2006.203.08:15:11.61#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.203.08:15:11.61#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.203.08:15:11.61#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.203.08:15:11.61#ibcon#ireg 7 cls_cnt 0 2006.203.08:15:11.61#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.203.08:15:11.73#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.203.08:15:11.73#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.203.08:15:11.73#ibcon#enter wrdev, iclass 24, count 0 2006.203.08:15:11.73#ibcon#first serial, iclass 24, count 0 2006.203.08:15:11.73#ibcon#enter sib2, iclass 24, count 0 2006.203.08:15:11.73#ibcon#flushed, iclass 24, count 0 2006.203.08:15:11.73#ibcon#about to write, iclass 24, count 0 2006.203.08:15:11.73#ibcon#wrote, iclass 24, count 0 2006.203.08:15:11.73#ibcon#about to read 3, iclass 24, count 0 2006.203.08:15:11.75#ibcon#read 3, iclass 24, count 0 2006.203.08:15:11.75#ibcon#about to read 4, iclass 24, count 0 2006.203.08:15:11.75#ibcon#read 4, iclass 24, count 0 2006.203.08:15:11.75#ibcon#about to read 5, iclass 24, count 0 2006.203.08:15:11.75#ibcon#read 5, iclass 24, count 0 2006.203.08:15:11.75#ibcon#about to read 6, iclass 24, count 0 2006.203.08:15:11.75#ibcon#read 6, iclass 24, count 0 2006.203.08:15:11.75#ibcon#end of sib2, iclass 24, count 0 2006.203.08:15:11.75#ibcon#*mode == 0, iclass 24, count 0 2006.203.08:15:11.75#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.203.08:15:11.75#ibcon#[25=USB\r\n] 2006.203.08:15:11.75#ibcon#*before write, iclass 24, count 0 2006.203.08:15:11.75#ibcon#enter sib2, iclass 24, count 0 2006.203.08:15:11.75#ibcon#flushed, iclass 24, count 0 2006.203.08:15:11.75#ibcon#about to write, iclass 24, count 0 2006.203.08:15:11.75#ibcon#wrote, iclass 24, count 0 2006.203.08:15:11.75#ibcon#about to read 3, iclass 24, count 0 2006.203.08:15:11.78#ibcon#read 3, iclass 24, count 0 2006.203.08:15:11.78#ibcon#about to read 4, iclass 24, count 0 2006.203.08:15:11.78#ibcon#read 4, iclass 24, count 0 2006.203.08:15:11.78#ibcon#about to read 5, iclass 24, count 0 2006.203.08:15:11.78#ibcon#read 5, iclass 24, count 0 2006.203.08:15:11.78#ibcon#about to read 6, iclass 24, count 0 2006.203.08:15:11.78#ibcon#read 6, iclass 24, count 0 2006.203.08:15:11.78#ibcon#end of sib2, iclass 24, count 0 2006.203.08:15:11.78#ibcon#*after write, iclass 24, count 0 2006.203.08:15:11.78#ibcon#*before return 0, iclass 24, count 0 2006.203.08:15:11.78#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.203.08:15:11.78#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.203.08:15:11.78#ibcon#about to clear, iclass 24 cls_cnt 0 2006.203.08:15:11.78#ibcon#cleared, iclass 24 cls_cnt 0 2006.203.08:15:11.78$vc4f8/vblo=1,632.99 2006.203.08:15:11.78#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.203.08:15:11.78#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.203.08:15:11.78#ibcon#ireg 17 cls_cnt 0 2006.203.08:15:11.78#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.203.08:15:11.78#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.203.08:15:11.78#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.203.08:15:11.78#ibcon#enter wrdev, iclass 26, count 0 2006.203.08:15:11.78#ibcon#first serial, iclass 26, count 0 2006.203.08:15:11.78#ibcon#enter sib2, iclass 26, count 0 2006.203.08:15:11.78#ibcon#flushed, iclass 26, count 0 2006.203.08:15:11.78#ibcon#about to write, iclass 26, count 0 2006.203.08:15:11.78#ibcon#wrote, iclass 26, count 0 2006.203.08:15:11.78#ibcon#about to read 3, iclass 26, count 0 2006.203.08:15:11.80#ibcon#read 3, iclass 26, count 0 2006.203.08:15:11.80#ibcon#about to read 4, iclass 26, count 0 2006.203.08:15:11.80#ibcon#read 4, iclass 26, count 0 2006.203.08:15:11.80#ibcon#about to read 5, iclass 26, count 0 2006.203.08:15:11.80#ibcon#read 5, iclass 26, count 0 2006.203.08:15:11.80#ibcon#about to read 6, iclass 26, count 0 2006.203.08:15:11.80#ibcon#read 6, iclass 26, count 0 2006.203.08:15:11.80#ibcon#end of sib2, iclass 26, count 0 2006.203.08:15:11.80#ibcon#*mode == 0, iclass 26, count 0 2006.203.08:15:11.80#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.203.08:15:11.80#ibcon#[28=FRQ=01,632.99\r\n] 2006.203.08:15:11.80#ibcon#*before write, iclass 26, count 0 2006.203.08:15:11.80#ibcon#enter sib2, iclass 26, count 0 2006.203.08:15:11.80#ibcon#flushed, iclass 26, count 0 2006.203.08:15:11.80#ibcon#about to write, iclass 26, count 0 2006.203.08:15:11.80#ibcon#wrote, iclass 26, count 0 2006.203.08:15:11.80#ibcon#about to read 3, iclass 26, count 0 2006.203.08:15:11.84#ibcon#read 3, iclass 26, count 0 2006.203.08:15:11.84#ibcon#about to read 4, iclass 26, count 0 2006.203.08:15:11.84#ibcon#read 4, iclass 26, count 0 2006.203.08:15:11.84#ibcon#about to read 5, iclass 26, count 0 2006.203.08:15:11.84#ibcon#read 5, iclass 26, count 0 2006.203.08:15:11.84#ibcon#about to read 6, iclass 26, count 0 2006.203.08:15:11.84#ibcon#read 6, iclass 26, count 0 2006.203.08:15:11.84#ibcon#end of sib2, iclass 26, count 0 2006.203.08:15:11.84#ibcon#*after write, iclass 26, count 0 2006.203.08:15:11.84#ibcon#*before return 0, iclass 26, count 0 2006.203.08:15:11.84#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.203.08:15:11.84#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.203.08:15:11.84#ibcon#about to clear, iclass 26 cls_cnt 0 2006.203.08:15:11.84#ibcon#cleared, iclass 26 cls_cnt 0 2006.203.08:15:11.84$vc4f8/vb=1,4 2006.203.08:15:11.84#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.203.08:15:11.84#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.203.08:15:11.84#ibcon#ireg 11 cls_cnt 2 2006.203.08:15:11.84#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.203.08:15:11.84#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.203.08:15:11.84#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.203.08:15:11.84#ibcon#enter wrdev, iclass 28, count 2 2006.203.08:15:11.84#ibcon#first serial, iclass 28, count 2 2006.203.08:15:11.84#ibcon#enter sib2, iclass 28, count 2 2006.203.08:15:11.84#ibcon#flushed, iclass 28, count 2 2006.203.08:15:11.84#ibcon#about to write, iclass 28, count 2 2006.203.08:15:11.84#ibcon#wrote, iclass 28, count 2 2006.203.08:15:11.84#ibcon#about to read 3, iclass 28, count 2 2006.203.08:15:11.86#ibcon#read 3, iclass 28, count 2 2006.203.08:15:11.86#ibcon#about to read 4, iclass 28, count 2 2006.203.08:15:11.86#ibcon#read 4, iclass 28, count 2 2006.203.08:15:11.86#ibcon#about to read 5, iclass 28, count 2 2006.203.08:15:11.86#ibcon#read 5, iclass 28, count 2 2006.203.08:15:11.86#ibcon#about to read 6, iclass 28, count 2 2006.203.08:15:11.86#ibcon#read 6, iclass 28, count 2 2006.203.08:15:11.86#ibcon#end of sib2, iclass 28, count 2 2006.203.08:15:11.86#ibcon#*mode == 0, iclass 28, count 2 2006.203.08:15:11.86#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.203.08:15:11.86#ibcon#[27=AT01-04\r\n] 2006.203.08:15:11.86#ibcon#*before write, iclass 28, count 2 2006.203.08:15:11.86#ibcon#enter sib2, iclass 28, count 2 2006.203.08:15:11.86#ibcon#flushed, iclass 28, count 2 2006.203.08:15:11.86#ibcon#about to write, iclass 28, count 2 2006.203.08:15:11.86#ibcon#wrote, iclass 28, count 2 2006.203.08:15:11.86#ibcon#about to read 3, iclass 28, count 2 2006.203.08:15:11.89#ibcon#read 3, iclass 28, count 2 2006.203.08:15:11.89#ibcon#about to read 4, iclass 28, count 2 2006.203.08:15:11.89#ibcon#read 4, iclass 28, count 2 2006.203.08:15:11.89#ibcon#about to read 5, iclass 28, count 2 2006.203.08:15:11.89#ibcon#read 5, iclass 28, count 2 2006.203.08:15:11.89#ibcon#about to read 6, iclass 28, count 2 2006.203.08:15:11.89#ibcon#read 6, iclass 28, count 2 2006.203.08:15:11.89#ibcon#end of sib2, iclass 28, count 2 2006.203.08:15:11.89#ibcon#*after write, iclass 28, count 2 2006.203.08:15:11.89#ibcon#*before return 0, iclass 28, count 2 2006.203.08:15:11.89#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.203.08:15:11.89#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.203.08:15:11.89#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.203.08:15:11.89#ibcon#ireg 7 cls_cnt 0 2006.203.08:15:11.89#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.203.08:15:12.01#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.203.08:15:12.01#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.203.08:15:12.01#ibcon#enter wrdev, iclass 28, count 0 2006.203.08:15:12.01#ibcon#first serial, iclass 28, count 0 2006.203.08:15:12.01#ibcon#enter sib2, iclass 28, count 0 2006.203.08:15:12.01#ibcon#flushed, iclass 28, count 0 2006.203.08:15:12.01#ibcon#about to write, iclass 28, count 0 2006.203.08:15:12.01#ibcon#wrote, iclass 28, count 0 2006.203.08:15:12.01#ibcon#about to read 3, iclass 28, count 0 2006.203.08:15:12.03#ibcon#read 3, iclass 28, count 0 2006.203.08:15:12.03#ibcon#about to read 4, iclass 28, count 0 2006.203.08:15:12.03#ibcon#read 4, iclass 28, count 0 2006.203.08:15:12.03#ibcon#about to read 5, iclass 28, count 0 2006.203.08:15:12.03#ibcon#read 5, iclass 28, count 0 2006.203.08:15:12.03#ibcon#about to read 6, iclass 28, count 0 2006.203.08:15:12.03#ibcon#read 6, iclass 28, count 0 2006.203.08:15:12.03#ibcon#end of sib2, iclass 28, count 0 2006.203.08:15:12.03#ibcon#*mode == 0, iclass 28, count 0 2006.203.08:15:12.03#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.203.08:15:12.03#ibcon#[27=USB\r\n] 2006.203.08:15:12.03#ibcon#*before write, iclass 28, count 0 2006.203.08:15:12.03#ibcon#enter sib2, iclass 28, count 0 2006.203.08:15:12.03#ibcon#flushed, iclass 28, count 0 2006.203.08:15:12.03#ibcon#about to write, iclass 28, count 0 2006.203.08:15:12.03#ibcon#wrote, iclass 28, count 0 2006.203.08:15:12.03#ibcon#about to read 3, iclass 28, count 0 2006.203.08:15:12.06#ibcon#read 3, iclass 28, count 0 2006.203.08:15:12.06#ibcon#about to read 4, iclass 28, count 0 2006.203.08:15:12.06#ibcon#read 4, iclass 28, count 0 2006.203.08:15:12.06#ibcon#about to read 5, iclass 28, count 0 2006.203.08:15:12.06#ibcon#read 5, iclass 28, count 0 2006.203.08:15:12.06#ibcon#about to read 6, iclass 28, count 0 2006.203.08:15:12.06#ibcon#read 6, iclass 28, count 0 2006.203.08:15:12.06#ibcon#end of sib2, iclass 28, count 0 2006.203.08:15:12.06#ibcon#*after write, iclass 28, count 0 2006.203.08:15:12.06#ibcon#*before return 0, iclass 28, count 0 2006.203.08:15:12.06#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.203.08:15:12.06#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.203.08:15:12.06#ibcon#about to clear, iclass 28 cls_cnt 0 2006.203.08:15:12.06#ibcon#cleared, iclass 28 cls_cnt 0 2006.203.08:15:12.06$vc4f8/vblo=2,640.99 2006.203.08:15:12.06#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.203.08:15:12.06#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.203.08:15:12.06#ibcon#ireg 17 cls_cnt 0 2006.203.08:15:12.06#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.203.08:15:12.06#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.203.08:15:12.06#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.203.08:15:12.06#ibcon#enter wrdev, iclass 30, count 0 2006.203.08:15:12.06#ibcon#first serial, iclass 30, count 0 2006.203.08:15:12.06#ibcon#enter sib2, iclass 30, count 0 2006.203.08:15:12.06#ibcon#flushed, iclass 30, count 0 2006.203.08:15:12.06#ibcon#about to write, iclass 30, count 0 2006.203.08:15:12.06#ibcon#wrote, iclass 30, count 0 2006.203.08:15:12.06#ibcon#about to read 3, iclass 30, count 0 2006.203.08:15:12.08#ibcon#read 3, iclass 30, count 0 2006.203.08:15:12.08#ibcon#about to read 4, iclass 30, count 0 2006.203.08:15:12.08#ibcon#read 4, iclass 30, count 0 2006.203.08:15:12.08#ibcon#about to read 5, iclass 30, count 0 2006.203.08:15:12.08#ibcon#read 5, iclass 30, count 0 2006.203.08:15:12.08#ibcon#about to read 6, iclass 30, count 0 2006.203.08:15:12.08#ibcon#read 6, iclass 30, count 0 2006.203.08:15:12.08#ibcon#end of sib2, iclass 30, count 0 2006.203.08:15:12.08#ibcon#*mode == 0, iclass 30, count 0 2006.203.08:15:12.08#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.203.08:15:12.08#ibcon#[28=FRQ=02,640.99\r\n] 2006.203.08:15:12.08#ibcon#*before write, iclass 30, count 0 2006.203.08:15:12.08#ibcon#enter sib2, iclass 30, count 0 2006.203.08:15:12.08#ibcon#flushed, iclass 30, count 0 2006.203.08:15:12.08#ibcon#about to write, iclass 30, count 0 2006.203.08:15:12.08#ibcon#wrote, iclass 30, count 0 2006.203.08:15:12.08#ibcon#about to read 3, iclass 30, count 0 2006.203.08:15:12.12#ibcon#read 3, iclass 30, count 0 2006.203.08:15:12.12#ibcon#about to read 4, iclass 30, count 0 2006.203.08:15:12.12#ibcon#read 4, iclass 30, count 0 2006.203.08:15:12.12#ibcon#about to read 5, iclass 30, count 0 2006.203.08:15:12.12#ibcon#read 5, iclass 30, count 0 2006.203.08:15:12.12#ibcon#about to read 6, iclass 30, count 0 2006.203.08:15:12.12#ibcon#read 6, iclass 30, count 0 2006.203.08:15:12.12#ibcon#end of sib2, iclass 30, count 0 2006.203.08:15:12.12#ibcon#*after write, iclass 30, count 0 2006.203.08:15:12.12#ibcon#*before return 0, iclass 30, count 0 2006.203.08:15:12.12#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.203.08:15:12.12#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.203.08:15:12.12#ibcon#about to clear, iclass 30 cls_cnt 0 2006.203.08:15:12.12#ibcon#cleared, iclass 30 cls_cnt 0 2006.203.08:15:12.12$vc4f8/vb=2,4 2006.203.08:15:12.12#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.203.08:15:12.12#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.203.08:15:12.12#ibcon#ireg 11 cls_cnt 2 2006.203.08:15:12.12#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.203.08:15:12.18#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.203.08:15:12.18#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.203.08:15:12.18#ibcon#enter wrdev, iclass 32, count 2 2006.203.08:15:12.18#ibcon#first serial, iclass 32, count 2 2006.203.08:15:12.18#ibcon#enter sib2, iclass 32, count 2 2006.203.08:15:12.18#ibcon#flushed, iclass 32, count 2 2006.203.08:15:12.18#ibcon#about to write, iclass 32, count 2 2006.203.08:15:12.18#ibcon#wrote, iclass 32, count 2 2006.203.08:15:12.18#ibcon#about to read 3, iclass 32, count 2 2006.203.08:15:12.20#ibcon#read 3, iclass 32, count 2 2006.203.08:15:12.20#ibcon#about to read 4, iclass 32, count 2 2006.203.08:15:12.20#ibcon#read 4, iclass 32, count 2 2006.203.08:15:12.20#ibcon#about to read 5, iclass 32, count 2 2006.203.08:15:12.20#ibcon#read 5, iclass 32, count 2 2006.203.08:15:12.20#ibcon#about to read 6, iclass 32, count 2 2006.203.08:15:12.20#ibcon#read 6, iclass 32, count 2 2006.203.08:15:12.20#ibcon#end of sib2, iclass 32, count 2 2006.203.08:15:12.20#ibcon#*mode == 0, iclass 32, count 2 2006.203.08:15:12.20#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.203.08:15:12.20#ibcon#[27=AT02-04\r\n] 2006.203.08:15:12.20#ibcon#*before write, iclass 32, count 2 2006.203.08:15:12.20#ibcon#enter sib2, iclass 32, count 2 2006.203.08:15:12.20#ibcon#flushed, iclass 32, count 2 2006.203.08:15:12.20#ibcon#about to write, iclass 32, count 2 2006.203.08:15:12.20#ibcon#wrote, iclass 32, count 2 2006.203.08:15:12.20#ibcon#about to read 3, iclass 32, count 2 2006.203.08:15:12.23#ibcon#read 3, iclass 32, count 2 2006.203.08:15:12.23#ibcon#about to read 4, iclass 32, count 2 2006.203.08:15:12.23#ibcon#read 4, iclass 32, count 2 2006.203.08:15:12.23#ibcon#about to read 5, iclass 32, count 2 2006.203.08:15:12.23#ibcon#read 5, iclass 32, count 2 2006.203.08:15:12.23#ibcon#about to read 6, iclass 32, count 2 2006.203.08:15:12.23#ibcon#read 6, iclass 32, count 2 2006.203.08:15:12.23#ibcon#end of sib2, iclass 32, count 2 2006.203.08:15:12.23#ibcon#*after write, iclass 32, count 2 2006.203.08:15:12.23#ibcon#*before return 0, iclass 32, count 2 2006.203.08:15:12.23#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.203.08:15:12.23#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.203.08:15:12.23#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.203.08:15:12.23#ibcon#ireg 7 cls_cnt 0 2006.203.08:15:12.23#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.203.08:15:12.35#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.203.08:15:12.35#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.203.08:15:12.35#ibcon#enter wrdev, iclass 32, count 0 2006.203.08:15:12.35#ibcon#first serial, iclass 32, count 0 2006.203.08:15:12.35#ibcon#enter sib2, iclass 32, count 0 2006.203.08:15:12.35#ibcon#flushed, iclass 32, count 0 2006.203.08:15:12.35#ibcon#about to write, iclass 32, count 0 2006.203.08:15:12.35#ibcon#wrote, iclass 32, count 0 2006.203.08:15:12.35#ibcon#about to read 3, iclass 32, count 0 2006.203.08:15:12.37#ibcon#read 3, iclass 32, count 0 2006.203.08:15:12.37#ibcon#about to read 4, iclass 32, count 0 2006.203.08:15:12.37#ibcon#read 4, iclass 32, count 0 2006.203.08:15:12.37#ibcon#about to read 5, iclass 32, count 0 2006.203.08:15:12.37#ibcon#read 5, iclass 32, count 0 2006.203.08:15:12.37#ibcon#about to read 6, iclass 32, count 0 2006.203.08:15:12.37#ibcon#read 6, iclass 32, count 0 2006.203.08:15:12.37#ibcon#end of sib2, iclass 32, count 0 2006.203.08:15:12.37#ibcon#*mode == 0, iclass 32, count 0 2006.203.08:15:12.37#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.203.08:15:12.37#ibcon#[27=USB\r\n] 2006.203.08:15:12.37#ibcon#*before write, iclass 32, count 0 2006.203.08:15:12.37#ibcon#enter sib2, iclass 32, count 0 2006.203.08:15:12.37#ibcon#flushed, iclass 32, count 0 2006.203.08:15:12.37#ibcon#about to write, iclass 32, count 0 2006.203.08:15:12.37#ibcon#wrote, iclass 32, count 0 2006.203.08:15:12.37#ibcon#about to read 3, iclass 32, count 0 2006.203.08:15:12.40#ibcon#read 3, iclass 32, count 0 2006.203.08:15:12.40#ibcon#about to read 4, iclass 32, count 0 2006.203.08:15:12.40#ibcon#read 4, iclass 32, count 0 2006.203.08:15:12.40#ibcon#about to read 5, iclass 32, count 0 2006.203.08:15:12.40#ibcon#read 5, iclass 32, count 0 2006.203.08:15:12.40#ibcon#about to read 6, iclass 32, count 0 2006.203.08:15:12.40#ibcon#read 6, iclass 32, count 0 2006.203.08:15:12.40#ibcon#end of sib2, iclass 32, count 0 2006.203.08:15:12.40#ibcon#*after write, iclass 32, count 0 2006.203.08:15:12.40#ibcon#*before return 0, iclass 32, count 0 2006.203.08:15:12.40#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.203.08:15:12.40#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.203.08:15:12.40#ibcon#about to clear, iclass 32 cls_cnt 0 2006.203.08:15:12.40#ibcon#cleared, iclass 32 cls_cnt 0 2006.203.08:15:12.40$vc4f8/vblo=3,656.99 2006.203.08:15:12.40#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.203.08:15:12.40#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.203.08:15:12.40#ibcon#ireg 17 cls_cnt 0 2006.203.08:15:12.40#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.203.08:15:12.40#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.203.08:15:12.40#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.203.08:15:12.40#ibcon#enter wrdev, iclass 34, count 0 2006.203.08:15:12.40#ibcon#first serial, iclass 34, count 0 2006.203.08:15:12.40#ibcon#enter sib2, iclass 34, count 0 2006.203.08:15:12.40#ibcon#flushed, iclass 34, count 0 2006.203.08:15:12.40#ibcon#about to write, iclass 34, count 0 2006.203.08:15:12.40#ibcon#wrote, iclass 34, count 0 2006.203.08:15:12.40#ibcon#about to read 3, iclass 34, count 0 2006.203.08:15:12.42#ibcon#read 3, iclass 34, count 0 2006.203.08:15:12.42#ibcon#about to read 4, iclass 34, count 0 2006.203.08:15:12.42#ibcon#read 4, iclass 34, count 0 2006.203.08:15:12.42#ibcon#about to read 5, iclass 34, count 0 2006.203.08:15:12.42#ibcon#read 5, iclass 34, count 0 2006.203.08:15:12.42#ibcon#about to read 6, iclass 34, count 0 2006.203.08:15:12.42#ibcon#read 6, iclass 34, count 0 2006.203.08:15:12.42#ibcon#end of sib2, iclass 34, count 0 2006.203.08:15:12.42#ibcon#*mode == 0, iclass 34, count 0 2006.203.08:15:12.42#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.203.08:15:12.42#ibcon#[28=FRQ=03,656.99\r\n] 2006.203.08:15:12.42#ibcon#*before write, iclass 34, count 0 2006.203.08:15:12.42#ibcon#enter sib2, iclass 34, count 0 2006.203.08:15:12.42#ibcon#flushed, iclass 34, count 0 2006.203.08:15:12.42#ibcon#about to write, iclass 34, count 0 2006.203.08:15:12.42#ibcon#wrote, iclass 34, count 0 2006.203.08:15:12.42#ibcon#about to read 3, iclass 34, count 0 2006.203.08:15:12.46#ibcon#read 3, iclass 34, count 0 2006.203.08:15:12.46#ibcon#about to read 4, iclass 34, count 0 2006.203.08:15:12.46#ibcon#read 4, iclass 34, count 0 2006.203.08:15:12.46#ibcon#about to read 5, iclass 34, count 0 2006.203.08:15:12.46#ibcon#read 5, iclass 34, count 0 2006.203.08:15:12.46#ibcon#about to read 6, iclass 34, count 0 2006.203.08:15:12.46#ibcon#read 6, iclass 34, count 0 2006.203.08:15:12.46#ibcon#end of sib2, iclass 34, count 0 2006.203.08:15:12.46#ibcon#*after write, iclass 34, count 0 2006.203.08:15:12.46#ibcon#*before return 0, iclass 34, count 0 2006.203.08:15:12.46#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.203.08:15:12.46#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.203.08:15:12.46#ibcon#about to clear, iclass 34 cls_cnt 0 2006.203.08:15:12.46#ibcon#cleared, iclass 34 cls_cnt 0 2006.203.08:15:12.46$vc4f8/vb=3,4 2006.203.08:15:12.46#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.203.08:15:12.46#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.203.08:15:12.46#ibcon#ireg 11 cls_cnt 2 2006.203.08:15:12.46#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.203.08:15:12.52#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.203.08:15:12.52#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.203.08:15:12.52#ibcon#enter wrdev, iclass 36, count 2 2006.203.08:15:12.52#ibcon#first serial, iclass 36, count 2 2006.203.08:15:12.52#ibcon#enter sib2, iclass 36, count 2 2006.203.08:15:12.52#ibcon#flushed, iclass 36, count 2 2006.203.08:15:12.52#ibcon#about to write, iclass 36, count 2 2006.203.08:15:12.52#ibcon#wrote, iclass 36, count 2 2006.203.08:15:12.52#ibcon#about to read 3, iclass 36, count 2 2006.203.08:15:12.54#ibcon#read 3, iclass 36, count 2 2006.203.08:15:12.54#ibcon#about to read 4, iclass 36, count 2 2006.203.08:15:12.54#ibcon#read 4, iclass 36, count 2 2006.203.08:15:12.54#ibcon#about to read 5, iclass 36, count 2 2006.203.08:15:12.54#ibcon#read 5, iclass 36, count 2 2006.203.08:15:12.54#ibcon#about to read 6, iclass 36, count 2 2006.203.08:15:12.54#ibcon#read 6, iclass 36, count 2 2006.203.08:15:12.54#ibcon#end of sib2, iclass 36, count 2 2006.203.08:15:12.54#ibcon#*mode == 0, iclass 36, count 2 2006.203.08:15:12.54#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.203.08:15:12.54#ibcon#[27=AT03-04\r\n] 2006.203.08:15:12.54#ibcon#*before write, iclass 36, count 2 2006.203.08:15:12.54#ibcon#enter sib2, iclass 36, count 2 2006.203.08:15:12.54#ibcon#flushed, iclass 36, count 2 2006.203.08:15:12.54#ibcon#about to write, iclass 36, count 2 2006.203.08:15:12.54#ibcon#wrote, iclass 36, count 2 2006.203.08:15:12.54#ibcon#about to read 3, iclass 36, count 2 2006.203.08:15:12.57#ibcon#read 3, iclass 36, count 2 2006.203.08:15:12.57#ibcon#about to read 4, iclass 36, count 2 2006.203.08:15:12.57#ibcon#read 4, iclass 36, count 2 2006.203.08:15:12.57#ibcon#about to read 5, iclass 36, count 2 2006.203.08:15:12.57#ibcon#read 5, iclass 36, count 2 2006.203.08:15:12.57#ibcon#about to read 6, iclass 36, count 2 2006.203.08:15:12.57#ibcon#read 6, iclass 36, count 2 2006.203.08:15:12.57#ibcon#end of sib2, iclass 36, count 2 2006.203.08:15:12.57#ibcon#*after write, iclass 36, count 2 2006.203.08:15:12.57#ibcon#*before return 0, iclass 36, count 2 2006.203.08:15:12.57#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.203.08:15:12.57#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.203.08:15:12.57#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.203.08:15:12.57#ibcon#ireg 7 cls_cnt 0 2006.203.08:15:12.57#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.203.08:15:12.69#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.203.08:15:12.69#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.203.08:15:12.69#ibcon#enter wrdev, iclass 36, count 0 2006.203.08:15:12.69#ibcon#first serial, iclass 36, count 0 2006.203.08:15:12.69#ibcon#enter sib2, iclass 36, count 0 2006.203.08:15:12.69#ibcon#flushed, iclass 36, count 0 2006.203.08:15:12.69#ibcon#about to write, iclass 36, count 0 2006.203.08:15:12.69#ibcon#wrote, iclass 36, count 0 2006.203.08:15:12.69#ibcon#about to read 3, iclass 36, count 0 2006.203.08:15:12.71#ibcon#read 3, iclass 36, count 0 2006.203.08:15:12.71#ibcon#about to read 4, iclass 36, count 0 2006.203.08:15:12.71#ibcon#read 4, iclass 36, count 0 2006.203.08:15:12.71#ibcon#about to read 5, iclass 36, count 0 2006.203.08:15:12.71#ibcon#read 5, iclass 36, count 0 2006.203.08:15:12.71#ibcon#about to read 6, iclass 36, count 0 2006.203.08:15:12.71#ibcon#read 6, iclass 36, count 0 2006.203.08:15:12.71#ibcon#end of sib2, iclass 36, count 0 2006.203.08:15:12.71#ibcon#*mode == 0, iclass 36, count 0 2006.203.08:15:12.71#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.203.08:15:12.71#ibcon#[27=USB\r\n] 2006.203.08:15:12.71#ibcon#*before write, iclass 36, count 0 2006.203.08:15:12.71#ibcon#enter sib2, iclass 36, count 0 2006.203.08:15:12.71#ibcon#flushed, iclass 36, count 0 2006.203.08:15:12.71#ibcon#about to write, iclass 36, count 0 2006.203.08:15:12.71#ibcon#wrote, iclass 36, count 0 2006.203.08:15:12.71#ibcon#about to read 3, iclass 36, count 0 2006.203.08:15:12.74#ibcon#read 3, iclass 36, count 0 2006.203.08:15:12.74#ibcon#about to read 4, iclass 36, count 0 2006.203.08:15:12.74#ibcon#read 4, iclass 36, count 0 2006.203.08:15:12.74#ibcon#about to read 5, iclass 36, count 0 2006.203.08:15:12.74#ibcon#read 5, iclass 36, count 0 2006.203.08:15:12.74#ibcon#about to read 6, iclass 36, count 0 2006.203.08:15:12.74#ibcon#read 6, iclass 36, count 0 2006.203.08:15:12.74#ibcon#end of sib2, iclass 36, count 0 2006.203.08:15:12.74#ibcon#*after write, iclass 36, count 0 2006.203.08:15:12.74#ibcon#*before return 0, iclass 36, count 0 2006.203.08:15:12.74#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.203.08:15:12.74#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.203.08:15:12.74#ibcon#about to clear, iclass 36 cls_cnt 0 2006.203.08:15:12.74#ibcon#cleared, iclass 36 cls_cnt 0 2006.203.08:15:12.74$vc4f8/vblo=4,712.99 2006.203.08:15:12.74#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.203.08:15:12.74#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.203.08:15:12.74#ibcon#ireg 17 cls_cnt 0 2006.203.08:15:12.74#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.203.08:15:12.74#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.203.08:15:12.74#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.203.08:15:12.74#ibcon#enter wrdev, iclass 38, count 0 2006.203.08:15:12.74#ibcon#first serial, iclass 38, count 0 2006.203.08:15:12.74#ibcon#enter sib2, iclass 38, count 0 2006.203.08:15:12.74#ibcon#flushed, iclass 38, count 0 2006.203.08:15:12.74#ibcon#about to write, iclass 38, count 0 2006.203.08:15:12.74#ibcon#wrote, iclass 38, count 0 2006.203.08:15:12.74#ibcon#about to read 3, iclass 38, count 0 2006.203.08:15:12.76#ibcon#read 3, iclass 38, count 0 2006.203.08:15:12.76#ibcon#about to read 4, iclass 38, count 0 2006.203.08:15:12.76#ibcon#read 4, iclass 38, count 0 2006.203.08:15:12.76#ibcon#about to read 5, iclass 38, count 0 2006.203.08:15:12.76#ibcon#read 5, iclass 38, count 0 2006.203.08:15:12.76#ibcon#about to read 6, iclass 38, count 0 2006.203.08:15:12.76#ibcon#read 6, iclass 38, count 0 2006.203.08:15:12.76#ibcon#end of sib2, iclass 38, count 0 2006.203.08:15:12.76#ibcon#*mode == 0, iclass 38, count 0 2006.203.08:15:12.76#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.203.08:15:12.76#ibcon#[28=FRQ=04,712.99\r\n] 2006.203.08:15:12.76#ibcon#*before write, iclass 38, count 0 2006.203.08:15:12.76#ibcon#enter sib2, iclass 38, count 0 2006.203.08:15:12.76#ibcon#flushed, iclass 38, count 0 2006.203.08:15:12.76#ibcon#about to write, iclass 38, count 0 2006.203.08:15:12.76#ibcon#wrote, iclass 38, count 0 2006.203.08:15:12.76#ibcon#about to read 3, iclass 38, count 0 2006.203.08:15:12.80#ibcon#read 3, iclass 38, count 0 2006.203.08:15:12.80#ibcon#about to read 4, iclass 38, count 0 2006.203.08:15:12.80#ibcon#read 4, iclass 38, count 0 2006.203.08:15:12.80#ibcon#about to read 5, iclass 38, count 0 2006.203.08:15:12.80#ibcon#read 5, iclass 38, count 0 2006.203.08:15:12.80#ibcon#about to read 6, iclass 38, count 0 2006.203.08:15:12.80#ibcon#read 6, iclass 38, count 0 2006.203.08:15:12.80#ibcon#end of sib2, iclass 38, count 0 2006.203.08:15:12.80#ibcon#*after write, iclass 38, count 0 2006.203.08:15:12.80#ibcon#*before return 0, iclass 38, count 0 2006.203.08:15:12.80#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.203.08:15:12.80#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.203.08:15:12.80#ibcon#about to clear, iclass 38 cls_cnt 0 2006.203.08:15:12.80#ibcon#cleared, iclass 38 cls_cnt 0 2006.203.08:15:12.80$vc4f8/vb=4,4 2006.203.08:15:12.80#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.203.08:15:12.80#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.203.08:15:12.80#ibcon#ireg 11 cls_cnt 2 2006.203.08:15:12.80#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.203.08:15:12.87#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.203.08:15:12.87#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.203.08:15:12.87#ibcon#enter wrdev, iclass 40, count 2 2006.203.08:15:12.87#ibcon#first serial, iclass 40, count 2 2006.203.08:15:12.87#ibcon#enter sib2, iclass 40, count 2 2006.203.08:15:12.87#ibcon#flushed, iclass 40, count 2 2006.203.08:15:12.87#ibcon#about to write, iclass 40, count 2 2006.203.08:15:12.87#ibcon#wrote, iclass 40, count 2 2006.203.08:15:12.87#ibcon#about to read 3, iclass 40, count 2 2006.203.08:15:12.88#ibcon#read 3, iclass 40, count 2 2006.203.08:15:12.88#ibcon#about to read 4, iclass 40, count 2 2006.203.08:15:12.88#ibcon#read 4, iclass 40, count 2 2006.203.08:15:12.88#ibcon#about to read 5, iclass 40, count 2 2006.203.08:15:12.88#ibcon#read 5, iclass 40, count 2 2006.203.08:15:12.88#ibcon#about to read 6, iclass 40, count 2 2006.203.08:15:12.88#ibcon#read 6, iclass 40, count 2 2006.203.08:15:12.88#ibcon#end of sib2, iclass 40, count 2 2006.203.08:15:12.88#ibcon#*mode == 0, iclass 40, count 2 2006.203.08:15:12.88#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.203.08:15:12.88#ibcon#[27=AT04-04\r\n] 2006.203.08:15:12.88#ibcon#*before write, iclass 40, count 2 2006.203.08:15:12.88#ibcon#enter sib2, iclass 40, count 2 2006.203.08:15:12.88#ibcon#flushed, iclass 40, count 2 2006.203.08:15:12.88#ibcon#about to write, iclass 40, count 2 2006.203.08:15:12.88#ibcon#wrote, iclass 40, count 2 2006.203.08:15:12.88#ibcon#about to read 3, iclass 40, count 2 2006.203.08:15:12.91#ibcon#read 3, iclass 40, count 2 2006.203.08:15:12.91#ibcon#about to read 4, iclass 40, count 2 2006.203.08:15:12.91#ibcon#read 4, iclass 40, count 2 2006.203.08:15:12.91#ibcon#about to read 5, iclass 40, count 2 2006.203.08:15:12.91#ibcon#read 5, iclass 40, count 2 2006.203.08:15:12.91#ibcon#about to read 6, iclass 40, count 2 2006.203.08:15:12.91#ibcon#read 6, iclass 40, count 2 2006.203.08:15:12.91#ibcon#end of sib2, iclass 40, count 2 2006.203.08:15:12.91#ibcon#*after write, iclass 40, count 2 2006.203.08:15:12.91#ibcon#*before return 0, iclass 40, count 2 2006.203.08:15:12.91#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.203.08:15:12.91#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.203.08:15:12.91#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.203.08:15:12.91#ibcon#ireg 7 cls_cnt 0 2006.203.08:15:12.91#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.203.08:15:13.03#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.203.08:15:13.03#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.203.08:15:13.03#ibcon#enter wrdev, iclass 40, count 0 2006.203.08:15:13.03#ibcon#first serial, iclass 40, count 0 2006.203.08:15:13.03#ibcon#enter sib2, iclass 40, count 0 2006.203.08:15:13.03#ibcon#flushed, iclass 40, count 0 2006.203.08:15:13.03#ibcon#about to write, iclass 40, count 0 2006.203.08:15:13.03#ibcon#wrote, iclass 40, count 0 2006.203.08:15:13.03#ibcon#about to read 3, iclass 40, count 0 2006.203.08:15:13.05#ibcon#read 3, iclass 40, count 0 2006.203.08:15:13.05#ibcon#about to read 4, iclass 40, count 0 2006.203.08:15:13.05#ibcon#read 4, iclass 40, count 0 2006.203.08:15:13.05#ibcon#about to read 5, iclass 40, count 0 2006.203.08:15:13.05#ibcon#read 5, iclass 40, count 0 2006.203.08:15:13.05#ibcon#about to read 6, iclass 40, count 0 2006.203.08:15:13.05#ibcon#read 6, iclass 40, count 0 2006.203.08:15:13.05#ibcon#end of sib2, iclass 40, count 0 2006.203.08:15:13.05#ibcon#*mode == 0, iclass 40, count 0 2006.203.08:15:13.05#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.203.08:15:13.05#ibcon#[27=USB\r\n] 2006.203.08:15:13.05#ibcon#*before write, iclass 40, count 0 2006.203.08:15:13.05#ibcon#enter sib2, iclass 40, count 0 2006.203.08:15:13.05#ibcon#flushed, iclass 40, count 0 2006.203.08:15:13.05#ibcon#about to write, iclass 40, count 0 2006.203.08:15:13.05#ibcon#wrote, iclass 40, count 0 2006.203.08:15:13.05#ibcon#about to read 3, iclass 40, count 0 2006.203.08:15:13.08#ibcon#read 3, iclass 40, count 0 2006.203.08:15:13.08#ibcon#about to read 4, iclass 40, count 0 2006.203.08:15:13.08#ibcon#read 4, iclass 40, count 0 2006.203.08:15:13.08#ibcon#about to read 5, iclass 40, count 0 2006.203.08:15:13.08#ibcon#read 5, iclass 40, count 0 2006.203.08:15:13.08#ibcon#about to read 6, iclass 40, count 0 2006.203.08:15:13.08#ibcon#read 6, iclass 40, count 0 2006.203.08:15:13.08#ibcon#end of sib2, iclass 40, count 0 2006.203.08:15:13.08#ibcon#*after write, iclass 40, count 0 2006.203.08:15:13.08#ibcon#*before return 0, iclass 40, count 0 2006.203.08:15:13.08#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.203.08:15:13.08#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.203.08:15:13.08#ibcon#about to clear, iclass 40 cls_cnt 0 2006.203.08:15:13.08#ibcon#cleared, iclass 40 cls_cnt 0 2006.203.08:15:13.08$vc4f8/vblo=5,744.99 2006.203.08:15:13.08#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.203.08:15:13.08#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.203.08:15:13.08#ibcon#ireg 17 cls_cnt 0 2006.203.08:15:13.08#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.203.08:15:13.08#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.203.08:15:13.08#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.203.08:15:13.08#ibcon#enter wrdev, iclass 4, count 0 2006.203.08:15:13.08#ibcon#first serial, iclass 4, count 0 2006.203.08:15:13.08#ibcon#enter sib2, iclass 4, count 0 2006.203.08:15:13.08#ibcon#flushed, iclass 4, count 0 2006.203.08:15:13.08#ibcon#about to write, iclass 4, count 0 2006.203.08:15:13.08#ibcon#wrote, iclass 4, count 0 2006.203.08:15:13.08#ibcon#about to read 3, iclass 4, count 0 2006.203.08:15:13.10#ibcon#read 3, iclass 4, count 0 2006.203.08:15:13.10#ibcon#about to read 4, iclass 4, count 0 2006.203.08:15:13.10#ibcon#read 4, iclass 4, count 0 2006.203.08:15:13.10#ibcon#about to read 5, iclass 4, count 0 2006.203.08:15:13.10#ibcon#read 5, iclass 4, count 0 2006.203.08:15:13.10#ibcon#about to read 6, iclass 4, count 0 2006.203.08:15:13.10#ibcon#read 6, iclass 4, count 0 2006.203.08:15:13.10#ibcon#end of sib2, iclass 4, count 0 2006.203.08:15:13.10#ibcon#*mode == 0, iclass 4, count 0 2006.203.08:15:13.10#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.203.08:15:13.10#ibcon#[28=FRQ=05,744.99\r\n] 2006.203.08:15:13.10#ibcon#*before write, iclass 4, count 0 2006.203.08:15:13.10#ibcon#enter sib2, iclass 4, count 0 2006.203.08:15:13.10#ibcon#flushed, iclass 4, count 0 2006.203.08:15:13.10#ibcon#about to write, iclass 4, count 0 2006.203.08:15:13.10#ibcon#wrote, iclass 4, count 0 2006.203.08:15:13.10#ibcon#about to read 3, iclass 4, count 0 2006.203.08:15:13.14#ibcon#read 3, iclass 4, count 0 2006.203.08:15:13.14#ibcon#about to read 4, iclass 4, count 0 2006.203.08:15:13.14#ibcon#read 4, iclass 4, count 0 2006.203.08:15:13.14#ibcon#about to read 5, iclass 4, count 0 2006.203.08:15:13.14#ibcon#read 5, iclass 4, count 0 2006.203.08:15:13.14#ibcon#about to read 6, iclass 4, count 0 2006.203.08:15:13.14#ibcon#read 6, iclass 4, count 0 2006.203.08:15:13.14#ibcon#end of sib2, iclass 4, count 0 2006.203.08:15:13.14#ibcon#*after write, iclass 4, count 0 2006.203.08:15:13.14#ibcon#*before return 0, iclass 4, count 0 2006.203.08:15:13.14#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.203.08:15:13.14#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.203.08:15:13.14#ibcon#about to clear, iclass 4 cls_cnt 0 2006.203.08:15:13.14#ibcon#cleared, iclass 4 cls_cnt 0 2006.203.08:15:13.14$vc4f8/vb=5,3 2006.203.08:15:13.14#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.203.08:15:13.14#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.203.08:15:13.14#ibcon#ireg 11 cls_cnt 2 2006.203.08:15:13.14#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.203.08:15:13.20#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.203.08:15:13.20#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.203.08:15:13.20#ibcon#enter wrdev, iclass 6, count 2 2006.203.08:15:13.20#ibcon#first serial, iclass 6, count 2 2006.203.08:15:13.20#ibcon#enter sib2, iclass 6, count 2 2006.203.08:15:13.20#ibcon#flushed, iclass 6, count 2 2006.203.08:15:13.20#ibcon#about to write, iclass 6, count 2 2006.203.08:15:13.20#ibcon#wrote, iclass 6, count 2 2006.203.08:15:13.20#ibcon#about to read 3, iclass 6, count 2 2006.203.08:15:13.22#ibcon#read 3, iclass 6, count 2 2006.203.08:15:13.22#ibcon#about to read 4, iclass 6, count 2 2006.203.08:15:13.22#ibcon#read 4, iclass 6, count 2 2006.203.08:15:13.22#ibcon#about to read 5, iclass 6, count 2 2006.203.08:15:13.22#ibcon#read 5, iclass 6, count 2 2006.203.08:15:13.22#ibcon#about to read 6, iclass 6, count 2 2006.203.08:15:13.22#ibcon#read 6, iclass 6, count 2 2006.203.08:15:13.22#ibcon#end of sib2, iclass 6, count 2 2006.203.08:15:13.22#ibcon#*mode == 0, iclass 6, count 2 2006.203.08:15:13.22#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.203.08:15:13.22#ibcon#[27=AT05-03\r\n] 2006.203.08:15:13.22#ibcon#*before write, iclass 6, count 2 2006.203.08:15:13.22#ibcon#enter sib2, iclass 6, count 2 2006.203.08:15:13.22#ibcon#flushed, iclass 6, count 2 2006.203.08:15:13.22#ibcon#about to write, iclass 6, count 2 2006.203.08:15:13.22#ibcon#wrote, iclass 6, count 2 2006.203.08:15:13.22#ibcon#about to read 3, iclass 6, count 2 2006.203.08:15:13.25#ibcon#read 3, iclass 6, count 2 2006.203.08:15:13.25#ibcon#about to read 4, iclass 6, count 2 2006.203.08:15:13.25#ibcon#read 4, iclass 6, count 2 2006.203.08:15:13.25#ibcon#about to read 5, iclass 6, count 2 2006.203.08:15:13.25#ibcon#read 5, iclass 6, count 2 2006.203.08:15:13.25#ibcon#about to read 6, iclass 6, count 2 2006.203.08:15:13.25#ibcon#read 6, iclass 6, count 2 2006.203.08:15:13.25#ibcon#end of sib2, iclass 6, count 2 2006.203.08:15:13.25#ibcon#*after write, iclass 6, count 2 2006.203.08:15:13.25#ibcon#*before return 0, iclass 6, count 2 2006.203.08:15:13.25#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.203.08:15:13.25#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.203.08:15:13.25#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.203.08:15:13.25#ibcon#ireg 7 cls_cnt 0 2006.203.08:15:13.25#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.203.08:15:13.37#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.203.08:15:13.37#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.203.08:15:13.37#ibcon#enter wrdev, iclass 6, count 0 2006.203.08:15:13.37#ibcon#first serial, iclass 6, count 0 2006.203.08:15:13.37#ibcon#enter sib2, iclass 6, count 0 2006.203.08:15:13.37#ibcon#flushed, iclass 6, count 0 2006.203.08:15:13.37#ibcon#about to write, iclass 6, count 0 2006.203.08:15:13.37#ibcon#wrote, iclass 6, count 0 2006.203.08:15:13.37#ibcon#about to read 3, iclass 6, count 0 2006.203.08:15:13.39#ibcon#read 3, iclass 6, count 0 2006.203.08:15:13.39#ibcon#about to read 4, iclass 6, count 0 2006.203.08:15:13.39#ibcon#read 4, iclass 6, count 0 2006.203.08:15:13.39#ibcon#about to read 5, iclass 6, count 0 2006.203.08:15:13.39#ibcon#read 5, iclass 6, count 0 2006.203.08:15:13.39#ibcon#about to read 6, iclass 6, count 0 2006.203.08:15:13.39#ibcon#read 6, iclass 6, count 0 2006.203.08:15:13.39#ibcon#end of sib2, iclass 6, count 0 2006.203.08:15:13.39#ibcon#*mode == 0, iclass 6, count 0 2006.203.08:15:13.39#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.203.08:15:13.39#ibcon#[27=USB\r\n] 2006.203.08:15:13.39#ibcon#*before write, iclass 6, count 0 2006.203.08:15:13.39#ibcon#enter sib2, iclass 6, count 0 2006.203.08:15:13.39#ibcon#flushed, iclass 6, count 0 2006.203.08:15:13.39#ibcon#about to write, iclass 6, count 0 2006.203.08:15:13.39#ibcon#wrote, iclass 6, count 0 2006.203.08:15:13.39#ibcon#about to read 3, iclass 6, count 0 2006.203.08:15:13.42#ibcon#read 3, iclass 6, count 0 2006.203.08:15:13.42#ibcon#about to read 4, iclass 6, count 0 2006.203.08:15:13.42#ibcon#read 4, iclass 6, count 0 2006.203.08:15:13.42#ibcon#about to read 5, iclass 6, count 0 2006.203.08:15:13.42#ibcon#read 5, iclass 6, count 0 2006.203.08:15:13.42#ibcon#about to read 6, iclass 6, count 0 2006.203.08:15:13.42#ibcon#read 6, iclass 6, count 0 2006.203.08:15:13.42#ibcon#end of sib2, iclass 6, count 0 2006.203.08:15:13.42#ibcon#*after write, iclass 6, count 0 2006.203.08:15:13.42#ibcon#*before return 0, iclass 6, count 0 2006.203.08:15:13.42#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.203.08:15:13.42#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.203.08:15:13.42#ibcon#about to clear, iclass 6 cls_cnt 0 2006.203.08:15:13.42#ibcon#cleared, iclass 6 cls_cnt 0 2006.203.08:15:13.42$vc4f8/vblo=6,752.99 2006.203.08:15:13.42#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.203.08:15:13.42#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.203.08:15:13.42#ibcon#ireg 17 cls_cnt 0 2006.203.08:15:13.42#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.203.08:15:13.42#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.203.08:15:13.42#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.203.08:15:13.42#ibcon#enter wrdev, iclass 10, count 0 2006.203.08:15:13.42#ibcon#first serial, iclass 10, count 0 2006.203.08:15:13.42#ibcon#enter sib2, iclass 10, count 0 2006.203.08:15:13.42#ibcon#flushed, iclass 10, count 0 2006.203.08:15:13.42#ibcon#about to write, iclass 10, count 0 2006.203.08:15:13.42#ibcon#wrote, iclass 10, count 0 2006.203.08:15:13.42#ibcon#about to read 3, iclass 10, count 0 2006.203.08:15:13.44#ibcon#read 3, iclass 10, count 0 2006.203.08:15:13.44#ibcon#about to read 4, iclass 10, count 0 2006.203.08:15:13.44#ibcon#read 4, iclass 10, count 0 2006.203.08:15:13.44#ibcon#about to read 5, iclass 10, count 0 2006.203.08:15:13.44#ibcon#read 5, iclass 10, count 0 2006.203.08:15:13.44#ibcon#about to read 6, iclass 10, count 0 2006.203.08:15:13.44#ibcon#read 6, iclass 10, count 0 2006.203.08:15:13.44#ibcon#end of sib2, iclass 10, count 0 2006.203.08:15:13.44#ibcon#*mode == 0, iclass 10, count 0 2006.203.08:15:13.44#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.203.08:15:13.44#ibcon#[28=FRQ=06,752.99\r\n] 2006.203.08:15:13.44#ibcon#*before write, iclass 10, count 0 2006.203.08:15:13.44#ibcon#enter sib2, iclass 10, count 0 2006.203.08:15:13.44#ibcon#flushed, iclass 10, count 0 2006.203.08:15:13.44#ibcon#about to write, iclass 10, count 0 2006.203.08:15:13.44#ibcon#wrote, iclass 10, count 0 2006.203.08:15:13.44#ibcon#about to read 3, iclass 10, count 0 2006.203.08:15:13.48#ibcon#read 3, iclass 10, count 0 2006.203.08:15:13.48#ibcon#about to read 4, iclass 10, count 0 2006.203.08:15:13.48#ibcon#read 4, iclass 10, count 0 2006.203.08:15:13.48#ibcon#about to read 5, iclass 10, count 0 2006.203.08:15:13.48#ibcon#read 5, iclass 10, count 0 2006.203.08:15:13.48#ibcon#about to read 6, iclass 10, count 0 2006.203.08:15:13.48#ibcon#read 6, iclass 10, count 0 2006.203.08:15:13.48#ibcon#end of sib2, iclass 10, count 0 2006.203.08:15:13.48#ibcon#*after write, iclass 10, count 0 2006.203.08:15:13.48#ibcon#*before return 0, iclass 10, count 0 2006.203.08:15:13.48#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.203.08:15:13.48#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.203.08:15:13.48#ibcon#about to clear, iclass 10 cls_cnt 0 2006.203.08:15:13.48#ibcon#cleared, iclass 10 cls_cnt 0 2006.203.08:15:13.48$vc4f8/vb=6,4 2006.203.08:15:13.48#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.203.08:15:13.48#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.203.08:15:13.48#ibcon#ireg 11 cls_cnt 2 2006.203.08:15:13.48#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.203.08:15:13.54#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.203.08:15:13.54#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.203.08:15:13.54#ibcon#enter wrdev, iclass 12, count 2 2006.203.08:15:13.54#ibcon#first serial, iclass 12, count 2 2006.203.08:15:13.54#ibcon#enter sib2, iclass 12, count 2 2006.203.08:15:13.54#ibcon#flushed, iclass 12, count 2 2006.203.08:15:13.54#ibcon#about to write, iclass 12, count 2 2006.203.08:15:13.54#ibcon#wrote, iclass 12, count 2 2006.203.08:15:13.54#ibcon#about to read 3, iclass 12, count 2 2006.203.08:15:13.56#ibcon#read 3, iclass 12, count 2 2006.203.08:15:13.56#ibcon#about to read 4, iclass 12, count 2 2006.203.08:15:13.56#ibcon#read 4, iclass 12, count 2 2006.203.08:15:13.56#ibcon#about to read 5, iclass 12, count 2 2006.203.08:15:13.56#ibcon#read 5, iclass 12, count 2 2006.203.08:15:13.56#ibcon#about to read 6, iclass 12, count 2 2006.203.08:15:13.56#ibcon#read 6, iclass 12, count 2 2006.203.08:15:13.56#ibcon#end of sib2, iclass 12, count 2 2006.203.08:15:13.56#ibcon#*mode == 0, iclass 12, count 2 2006.203.08:15:13.56#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.203.08:15:13.56#ibcon#[27=AT06-04\r\n] 2006.203.08:15:13.56#ibcon#*before write, iclass 12, count 2 2006.203.08:15:13.56#ibcon#enter sib2, iclass 12, count 2 2006.203.08:15:13.56#ibcon#flushed, iclass 12, count 2 2006.203.08:15:13.56#ibcon#about to write, iclass 12, count 2 2006.203.08:15:13.56#ibcon#wrote, iclass 12, count 2 2006.203.08:15:13.56#ibcon#about to read 3, iclass 12, count 2 2006.203.08:15:13.59#ibcon#read 3, iclass 12, count 2 2006.203.08:15:13.59#ibcon#about to read 4, iclass 12, count 2 2006.203.08:15:13.59#ibcon#read 4, iclass 12, count 2 2006.203.08:15:13.59#ibcon#about to read 5, iclass 12, count 2 2006.203.08:15:13.59#ibcon#read 5, iclass 12, count 2 2006.203.08:15:13.59#ibcon#about to read 6, iclass 12, count 2 2006.203.08:15:13.59#ibcon#read 6, iclass 12, count 2 2006.203.08:15:13.59#ibcon#end of sib2, iclass 12, count 2 2006.203.08:15:13.59#ibcon#*after write, iclass 12, count 2 2006.203.08:15:13.59#ibcon#*before return 0, iclass 12, count 2 2006.203.08:15:13.59#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.203.08:15:13.59#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.203.08:15:13.59#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.203.08:15:13.59#ibcon#ireg 7 cls_cnt 0 2006.203.08:15:13.59#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.203.08:15:13.71#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.203.08:15:13.71#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.203.08:15:13.71#ibcon#enter wrdev, iclass 12, count 0 2006.203.08:15:13.71#ibcon#first serial, iclass 12, count 0 2006.203.08:15:13.71#ibcon#enter sib2, iclass 12, count 0 2006.203.08:15:13.71#ibcon#flushed, iclass 12, count 0 2006.203.08:15:13.71#ibcon#about to write, iclass 12, count 0 2006.203.08:15:13.71#ibcon#wrote, iclass 12, count 0 2006.203.08:15:13.71#ibcon#about to read 3, iclass 12, count 0 2006.203.08:15:13.73#ibcon#read 3, iclass 12, count 0 2006.203.08:15:13.73#ibcon#about to read 4, iclass 12, count 0 2006.203.08:15:13.73#ibcon#read 4, iclass 12, count 0 2006.203.08:15:13.73#ibcon#about to read 5, iclass 12, count 0 2006.203.08:15:13.73#ibcon#read 5, iclass 12, count 0 2006.203.08:15:13.73#ibcon#about to read 6, iclass 12, count 0 2006.203.08:15:13.73#ibcon#read 6, iclass 12, count 0 2006.203.08:15:13.73#ibcon#end of sib2, iclass 12, count 0 2006.203.08:15:13.73#ibcon#*mode == 0, iclass 12, count 0 2006.203.08:15:13.73#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.203.08:15:13.73#ibcon#[27=USB\r\n] 2006.203.08:15:13.73#ibcon#*before write, iclass 12, count 0 2006.203.08:15:13.73#ibcon#enter sib2, iclass 12, count 0 2006.203.08:15:13.73#ibcon#flushed, iclass 12, count 0 2006.203.08:15:13.73#ibcon#about to write, iclass 12, count 0 2006.203.08:15:13.73#ibcon#wrote, iclass 12, count 0 2006.203.08:15:13.73#ibcon#about to read 3, iclass 12, count 0 2006.203.08:15:13.76#ibcon#read 3, iclass 12, count 0 2006.203.08:15:13.76#ibcon#about to read 4, iclass 12, count 0 2006.203.08:15:13.76#ibcon#read 4, iclass 12, count 0 2006.203.08:15:13.76#ibcon#about to read 5, iclass 12, count 0 2006.203.08:15:13.76#ibcon#read 5, iclass 12, count 0 2006.203.08:15:13.76#ibcon#about to read 6, iclass 12, count 0 2006.203.08:15:13.76#ibcon#read 6, iclass 12, count 0 2006.203.08:15:13.76#ibcon#end of sib2, iclass 12, count 0 2006.203.08:15:13.76#ibcon#*after write, iclass 12, count 0 2006.203.08:15:13.76#ibcon#*before return 0, iclass 12, count 0 2006.203.08:15:13.76#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.203.08:15:13.76#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.203.08:15:13.76#ibcon#about to clear, iclass 12 cls_cnt 0 2006.203.08:15:13.76#ibcon#cleared, iclass 12 cls_cnt 0 2006.203.08:15:13.76$vc4f8/vabw=wide 2006.203.08:15:13.76#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.203.08:15:13.76#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.203.08:15:13.76#ibcon#ireg 8 cls_cnt 0 2006.203.08:15:13.76#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.203.08:15:13.76#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.203.08:15:13.76#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.203.08:15:13.76#ibcon#enter wrdev, iclass 14, count 0 2006.203.08:15:13.76#ibcon#first serial, iclass 14, count 0 2006.203.08:15:13.76#ibcon#enter sib2, iclass 14, count 0 2006.203.08:15:13.76#ibcon#flushed, iclass 14, count 0 2006.203.08:15:13.76#ibcon#about to write, iclass 14, count 0 2006.203.08:15:13.76#ibcon#wrote, iclass 14, count 0 2006.203.08:15:13.76#ibcon#about to read 3, iclass 14, count 0 2006.203.08:15:13.78#ibcon#read 3, iclass 14, count 0 2006.203.08:15:13.78#ibcon#about to read 4, iclass 14, count 0 2006.203.08:15:13.78#ibcon#read 4, iclass 14, count 0 2006.203.08:15:13.78#ibcon#about to read 5, iclass 14, count 0 2006.203.08:15:13.78#ibcon#read 5, iclass 14, count 0 2006.203.08:15:13.78#ibcon#about to read 6, iclass 14, count 0 2006.203.08:15:13.78#ibcon#read 6, iclass 14, count 0 2006.203.08:15:13.78#ibcon#end of sib2, iclass 14, count 0 2006.203.08:15:13.78#ibcon#*mode == 0, iclass 14, count 0 2006.203.08:15:13.78#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.203.08:15:13.78#ibcon#[25=BW32\r\n] 2006.203.08:15:13.78#ibcon#*before write, iclass 14, count 0 2006.203.08:15:13.78#ibcon#enter sib2, iclass 14, count 0 2006.203.08:15:13.78#ibcon#flushed, iclass 14, count 0 2006.203.08:15:13.78#ibcon#about to write, iclass 14, count 0 2006.203.08:15:13.78#ibcon#wrote, iclass 14, count 0 2006.203.08:15:13.78#ibcon#about to read 3, iclass 14, count 0 2006.203.08:15:13.81#ibcon#read 3, iclass 14, count 0 2006.203.08:15:13.81#ibcon#about to read 4, iclass 14, count 0 2006.203.08:15:13.81#ibcon#read 4, iclass 14, count 0 2006.203.08:15:13.81#ibcon#about to read 5, iclass 14, count 0 2006.203.08:15:13.81#ibcon#read 5, iclass 14, count 0 2006.203.08:15:13.81#ibcon#about to read 6, iclass 14, count 0 2006.203.08:15:13.81#ibcon#read 6, iclass 14, count 0 2006.203.08:15:13.81#ibcon#end of sib2, iclass 14, count 0 2006.203.08:15:13.81#ibcon#*after write, iclass 14, count 0 2006.203.08:15:13.81#ibcon#*before return 0, iclass 14, count 0 2006.203.08:15:13.81#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.203.08:15:13.81#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.203.08:15:13.81#ibcon#about to clear, iclass 14 cls_cnt 0 2006.203.08:15:13.81#ibcon#cleared, iclass 14 cls_cnt 0 2006.203.08:15:13.81$vc4f8/vbbw=wide 2006.203.08:15:13.81#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.203.08:15:13.81#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.203.08:15:13.81#ibcon#ireg 8 cls_cnt 0 2006.203.08:15:13.81#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.203.08:15:13.88#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.203.08:15:13.88#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.203.08:15:13.88#ibcon#enter wrdev, iclass 16, count 0 2006.203.08:15:13.88#ibcon#first serial, iclass 16, count 0 2006.203.08:15:13.88#ibcon#enter sib2, iclass 16, count 0 2006.203.08:15:13.88#ibcon#flushed, iclass 16, count 0 2006.203.08:15:13.88#ibcon#about to write, iclass 16, count 0 2006.203.08:15:13.88#ibcon#wrote, iclass 16, count 0 2006.203.08:15:13.88#ibcon#about to read 3, iclass 16, count 0 2006.203.08:15:13.90#ibcon#read 3, iclass 16, count 0 2006.203.08:15:13.90#ibcon#about to read 4, iclass 16, count 0 2006.203.08:15:13.90#ibcon#read 4, iclass 16, count 0 2006.203.08:15:13.90#ibcon#about to read 5, iclass 16, count 0 2006.203.08:15:13.90#ibcon#read 5, iclass 16, count 0 2006.203.08:15:13.90#ibcon#about to read 6, iclass 16, count 0 2006.203.08:15:13.90#ibcon#read 6, iclass 16, count 0 2006.203.08:15:13.90#ibcon#end of sib2, iclass 16, count 0 2006.203.08:15:13.90#ibcon#*mode == 0, iclass 16, count 0 2006.203.08:15:13.90#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.203.08:15:13.90#ibcon#[27=BW32\r\n] 2006.203.08:15:13.90#ibcon#*before write, iclass 16, count 0 2006.203.08:15:13.90#ibcon#enter sib2, iclass 16, count 0 2006.203.08:15:13.90#ibcon#flushed, iclass 16, count 0 2006.203.08:15:13.90#ibcon#about to write, iclass 16, count 0 2006.203.08:15:13.90#ibcon#wrote, iclass 16, count 0 2006.203.08:15:13.90#ibcon#about to read 3, iclass 16, count 0 2006.203.08:15:13.93#ibcon#read 3, iclass 16, count 0 2006.203.08:15:13.93#ibcon#about to read 4, iclass 16, count 0 2006.203.08:15:13.93#ibcon#read 4, iclass 16, count 0 2006.203.08:15:13.93#ibcon#about to read 5, iclass 16, count 0 2006.203.08:15:13.93#ibcon#read 5, iclass 16, count 0 2006.203.08:15:13.93#ibcon#about to read 6, iclass 16, count 0 2006.203.08:15:13.93#ibcon#read 6, iclass 16, count 0 2006.203.08:15:13.93#ibcon#end of sib2, iclass 16, count 0 2006.203.08:15:13.93#ibcon#*after write, iclass 16, count 0 2006.203.08:15:13.93#ibcon#*before return 0, iclass 16, count 0 2006.203.08:15:13.93#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.203.08:15:13.93#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.203.08:15:13.93#ibcon#about to clear, iclass 16 cls_cnt 0 2006.203.08:15:13.93#ibcon#cleared, iclass 16 cls_cnt 0 2006.203.08:15:13.93$4f8m12a/ifd4f 2006.203.08:15:13.93$ifd4f/lo= 2006.203.08:15:13.93$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.203.08:15:13.93$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.203.08:15:13.93$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.203.08:15:13.93$ifd4f/patch= 2006.203.08:15:13.94$ifd4f/patch=lo1,a1,a2,a3,a4 2006.203.08:15:13.94$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.203.08:15:13.94$ifd4f/patch=lo3,a5,a6,a7,a8 2006.203.08:15:13.94$4f8m12a/"form=m,16.000,1:2 2006.203.08:15:13.94$4f8m12a/"tpicd 2006.203.08:15:13.94$4f8m12a/echo=off 2006.203.08:15:13.94$4f8m12a/xlog=off 2006.203.08:15:13.94:!2006.203.08:15:40 2006.203.08:15:26.14#trakl#Source acquired 2006.203.08:15:28.14#flagr#flagr/antenna,acquired 2006.203.08:15:40.01:preob 2006.203.08:15:41.14/onsource/TRACKING 2006.203.08:15:41.14:!2006.203.08:15:50 2006.203.08:15:50.00:data_valid=on 2006.203.08:15:50.00:midob 2006.203.08:15:50.14/onsource/TRACKING 2006.203.08:15:50.14/wx/23.58,1001.1,100 2006.203.08:15:50.30/cable/+6.4612E-03 2006.203.08:15:51.39/va/01,08,usb,yes,29,31 2006.203.08:15:51.39/va/02,07,usb,yes,29,31 2006.203.08:15:51.39/va/03,08,usb,yes,22,22 2006.203.08:15:51.39/va/04,07,usb,yes,30,32 2006.203.08:15:51.39/va/05,07,usb,yes,33,35 2006.203.08:15:51.39/va/06,06,usb,yes,32,32 2006.203.08:15:51.39/va/07,07,usb,yes,28,28 2006.203.08:15:51.39/va/08,06,usb,yes,35,34 2006.203.08:15:51.62/valo/01,532.99,yes,locked 2006.203.08:15:51.62/valo/02,572.99,yes,locked 2006.203.08:15:51.62/valo/03,672.99,yes,locked 2006.203.08:15:51.62/valo/04,832.99,yes,locked 2006.203.08:15:51.62/valo/05,652.99,yes,locked 2006.203.08:15:51.62/valo/06,772.99,yes,locked 2006.203.08:15:51.62/valo/07,832.99,yes,locked 2006.203.08:15:51.62/valo/08,852.99,yes,locked 2006.203.08:15:52.71/vb/01,04,usb,yes,29,28 2006.203.08:15:52.71/vb/02,04,usb,yes,31,32 2006.203.08:15:52.71/vb/03,04,usb,yes,27,31 2006.203.08:15:52.71/vb/04,04,usb,yes,28,28 2006.203.08:15:52.71/vb/05,03,usb,yes,33,37 2006.203.08:15:52.71/vb/06,04,usb,yes,27,30 2006.203.08:15:52.71/vb/07,04,usb,yes,29,29 2006.203.08:15:52.71/vb/08,04,usb,yes,27,30 2006.203.08:15:52.95/vblo/01,632.99,yes,locked 2006.203.08:15:52.95/vblo/02,640.99,yes,locked 2006.203.08:15:52.95/vblo/03,656.99,yes,locked 2006.203.08:15:52.95/vblo/04,712.99,yes,locked 2006.203.08:15:52.95/vblo/05,744.99,yes,locked 2006.203.08:15:52.95/vblo/06,752.99,yes,locked 2006.203.08:15:52.95/vblo/07,734.99,yes,locked 2006.203.08:15:52.95/vblo/08,744.99,yes,locked 2006.203.08:15:53.10/vabw/8 2006.203.08:15:53.25/vbbw/8 2006.203.08:15:53.34/xfe/off,on,12.7 2006.203.08:15:53.72/ifatt/23,28,28,28 2006.203.08:15:54.07/fmout-gps/S +4.58E-07 2006.203.08:15:54.15:!2006.203.08:16:50 2006.203.08:16:50.01:data_valid=off 2006.203.08:16:50.02:postob 2006.203.08:16:50.26/cable/+6.4599E-03 2006.203.08:16:50.27/wx/23.57,1001.1,100 2006.203.08:16:51.07/fmout-gps/S +4.59E-07 2006.203.08:16:51.07:scan_name=203-0817,k06203,60 2006.203.08:16:51.07:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.203.08:16:51.14#flagr#flagr/antenna,new-source 2006.203.08:16:52.14:checkk5 2006.203.08:16:52.54/chk_autoobs//k5ts1/ autoobs is running! 2006.203.08:16:52.97/chk_autoobs//k5ts2/ autoobs is running! 2006.203.08:16:53.44/chk_autoobs//k5ts3/ autoobs is running! 2006.203.08:16:53.85/chk_autoobs//k5ts4/ autoobs is running! 2006.203.08:16:54.28/chk_obsdata//k5ts1/T2030815??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.08:16:54.76/chk_obsdata//k5ts2/T2030815??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.08:16:55.20/chk_obsdata//k5ts3/T2030815??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.08:16:55.62/chk_obsdata//k5ts4/T2030815??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.08:16:56.50/k5log//k5ts1_log_newline 2006.203.08:16:57.24/k5log//k5ts2_log_newline 2006.203.08:16:58.29/k5log//k5ts3_log_newline 2006.203.08:16:59.12/k5log//k5ts4_log_newline 2006.203.08:16:59.14/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.203.08:16:59.14:4f8m12a=2 2006.203.08:16:59.14$4f8m12a/echo=on 2006.203.08:16:59.14$4f8m12a/pcalon 2006.203.08:16:59.14$pcalon/"no phase cal control is implemented here 2006.203.08:16:59.15$4f8m12a/"tpicd=stop 2006.203.08:16:59.15$4f8m12a/vc4f8 2006.203.08:16:59.15$vc4f8/valo=1,532.99 2006.203.08:16:59.15#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.203.08:16:59.15#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.203.08:16:59.15#ibcon#ireg 17 cls_cnt 0 2006.203.08:16:59.15#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.203.08:16:59.15#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.203.08:16:59.15#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.203.08:16:59.15#ibcon#enter wrdev, iclass 23, count 0 2006.203.08:16:59.15#ibcon#first serial, iclass 23, count 0 2006.203.08:16:59.15#ibcon#enter sib2, iclass 23, count 0 2006.203.08:16:59.15#ibcon#flushed, iclass 23, count 0 2006.203.08:16:59.15#ibcon#about to write, iclass 23, count 0 2006.203.08:16:59.15#ibcon#wrote, iclass 23, count 0 2006.203.08:16:59.15#ibcon#about to read 3, iclass 23, count 0 2006.203.08:16:59.19#ibcon#read 3, iclass 23, count 0 2006.203.08:16:59.19#ibcon#about to read 4, iclass 23, count 0 2006.203.08:16:59.19#ibcon#read 4, iclass 23, count 0 2006.203.08:16:59.19#ibcon#about to read 5, iclass 23, count 0 2006.203.08:16:59.19#ibcon#read 5, iclass 23, count 0 2006.203.08:16:59.19#ibcon#about to read 6, iclass 23, count 0 2006.203.08:16:59.19#ibcon#read 6, iclass 23, count 0 2006.203.08:16:59.19#ibcon#end of sib2, iclass 23, count 0 2006.203.08:16:59.19#ibcon#*mode == 0, iclass 23, count 0 2006.203.08:16:59.19#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.203.08:16:59.19#ibcon#[26=FRQ=01,532.99\r\n] 2006.203.08:16:59.19#ibcon#*before write, iclass 23, count 0 2006.203.08:16:59.19#ibcon#enter sib2, iclass 23, count 0 2006.203.08:16:59.19#ibcon#flushed, iclass 23, count 0 2006.203.08:16:59.19#ibcon#about to write, iclass 23, count 0 2006.203.08:16:59.19#ibcon#wrote, iclass 23, count 0 2006.203.08:16:59.19#ibcon#about to read 3, iclass 23, count 0 2006.203.08:16:59.23#ibcon#read 3, iclass 23, count 0 2006.203.08:16:59.23#ibcon#about to read 4, iclass 23, count 0 2006.203.08:16:59.23#ibcon#read 4, iclass 23, count 0 2006.203.08:16:59.23#ibcon#about to read 5, iclass 23, count 0 2006.203.08:16:59.23#ibcon#read 5, iclass 23, count 0 2006.203.08:16:59.23#ibcon#about to read 6, iclass 23, count 0 2006.203.08:16:59.23#ibcon#read 6, iclass 23, count 0 2006.203.08:16:59.23#ibcon#end of sib2, iclass 23, count 0 2006.203.08:16:59.23#ibcon#*after write, iclass 23, count 0 2006.203.08:16:59.23#ibcon#*before return 0, iclass 23, count 0 2006.203.08:16:59.23#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.203.08:16:59.23#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.203.08:16:59.23#ibcon#about to clear, iclass 23 cls_cnt 0 2006.203.08:16:59.23#ibcon#cleared, iclass 23 cls_cnt 0 2006.203.08:16:59.23$vc4f8/va=1,8 2006.203.08:16:59.23#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.203.08:16:59.23#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.203.08:16:59.23#ibcon#ireg 11 cls_cnt 2 2006.203.08:16:59.23#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.203.08:16:59.23#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.203.08:16:59.23#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.203.08:16:59.23#ibcon#enter wrdev, iclass 25, count 2 2006.203.08:16:59.23#ibcon#first serial, iclass 25, count 2 2006.203.08:16:59.23#ibcon#enter sib2, iclass 25, count 2 2006.203.08:16:59.23#ibcon#flushed, iclass 25, count 2 2006.203.08:16:59.23#ibcon#about to write, iclass 25, count 2 2006.203.08:16:59.23#ibcon#wrote, iclass 25, count 2 2006.203.08:16:59.23#ibcon#about to read 3, iclass 25, count 2 2006.203.08:16:59.26#ibcon#read 3, iclass 25, count 2 2006.203.08:16:59.26#ibcon#about to read 4, iclass 25, count 2 2006.203.08:16:59.26#ibcon#read 4, iclass 25, count 2 2006.203.08:16:59.26#ibcon#about to read 5, iclass 25, count 2 2006.203.08:16:59.26#ibcon#read 5, iclass 25, count 2 2006.203.08:16:59.26#ibcon#about to read 6, iclass 25, count 2 2006.203.08:16:59.27#ibcon#read 6, iclass 25, count 2 2006.203.08:16:59.27#ibcon#end of sib2, iclass 25, count 2 2006.203.08:16:59.27#ibcon#*mode == 0, iclass 25, count 2 2006.203.08:16:59.27#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.203.08:16:59.27#ibcon#[25=AT01-08\r\n] 2006.203.08:16:59.27#ibcon#*before write, iclass 25, count 2 2006.203.08:16:59.27#ibcon#enter sib2, iclass 25, count 2 2006.203.08:16:59.27#ibcon#flushed, iclass 25, count 2 2006.203.08:16:59.27#ibcon#about to write, iclass 25, count 2 2006.203.08:16:59.27#ibcon#wrote, iclass 25, count 2 2006.203.08:16:59.27#ibcon#about to read 3, iclass 25, count 2 2006.203.08:16:59.29#ibcon#read 3, iclass 25, count 2 2006.203.08:16:59.29#ibcon#about to read 4, iclass 25, count 2 2006.203.08:16:59.29#ibcon#read 4, iclass 25, count 2 2006.203.08:16:59.29#ibcon#about to read 5, iclass 25, count 2 2006.203.08:16:59.29#ibcon#read 5, iclass 25, count 2 2006.203.08:16:59.29#ibcon#about to read 6, iclass 25, count 2 2006.203.08:16:59.29#ibcon#read 6, iclass 25, count 2 2006.203.08:16:59.29#ibcon#end of sib2, iclass 25, count 2 2006.203.08:16:59.29#ibcon#*after write, iclass 25, count 2 2006.203.08:16:59.29#ibcon#*before return 0, iclass 25, count 2 2006.203.08:16:59.29#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.203.08:16:59.29#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.203.08:16:59.29#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.203.08:16:59.29#ibcon#ireg 7 cls_cnt 0 2006.203.08:16:59.29#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.203.08:16:59.41#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.203.08:16:59.41#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.203.08:16:59.41#ibcon#enter wrdev, iclass 25, count 0 2006.203.08:16:59.41#ibcon#first serial, iclass 25, count 0 2006.203.08:16:59.41#ibcon#enter sib2, iclass 25, count 0 2006.203.08:16:59.41#ibcon#flushed, iclass 25, count 0 2006.203.08:16:59.41#ibcon#about to write, iclass 25, count 0 2006.203.08:16:59.41#ibcon#wrote, iclass 25, count 0 2006.203.08:16:59.41#ibcon#about to read 3, iclass 25, count 0 2006.203.08:16:59.43#ibcon#read 3, iclass 25, count 0 2006.203.08:16:59.43#ibcon#about to read 4, iclass 25, count 0 2006.203.08:16:59.43#ibcon#read 4, iclass 25, count 0 2006.203.08:16:59.43#ibcon#about to read 5, iclass 25, count 0 2006.203.08:16:59.43#ibcon#read 5, iclass 25, count 0 2006.203.08:16:59.43#ibcon#about to read 6, iclass 25, count 0 2006.203.08:16:59.43#ibcon#read 6, iclass 25, count 0 2006.203.08:16:59.43#ibcon#end of sib2, iclass 25, count 0 2006.203.08:16:59.43#ibcon#*mode == 0, iclass 25, count 0 2006.203.08:16:59.43#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.203.08:16:59.43#ibcon#[25=USB\r\n] 2006.203.08:16:59.43#ibcon#*before write, iclass 25, count 0 2006.203.08:16:59.43#ibcon#enter sib2, iclass 25, count 0 2006.203.08:16:59.43#ibcon#flushed, iclass 25, count 0 2006.203.08:16:59.43#ibcon#about to write, iclass 25, count 0 2006.203.08:16:59.43#ibcon#wrote, iclass 25, count 0 2006.203.08:16:59.43#ibcon#about to read 3, iclass 25, count 0 2006.203.08:16:59.46#ibcon#read 3, iclass 25, count 0 2006.203.08:16:59.46#ibcon#about to read 4, iclass 25, count 0 2006.203.08:16:59.46#ibcon#read 4, iclass 25, count 0 2006.203.08:16:59.46#ibcon#about to read 5, iclass 25, count 0 2006.203.08:16:59.46#ibcon#read 5, iclass 25, count 0 2006.203.08:16:59.46#ibcon#about to read 6, iclass 25, count 0 2006.203.08:16:59.46#ibcon#read 6, iclass 25, count 0 2006.203.08:16:59.46#ibcon#end of sib2, iclass 25, count 0 2006.203.08:16:59.46#ibcon#*after write, iclass 25, count 0 2006.203.08:16:59.46#ibcon#*before return 0, iclass 25, count 0 2006.203.08:16:59.46#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.203.08:16:59.46#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.203.08:16:59.46#ibcon#about to clear, iclass 25 cls_cnt 0 2006.203.08:16:59.46#ibcon#cleared, iclass 25 cls_cnt 0 2006.203.08:16:59.46$vc4f8/valo=2,572.99 2006.203.08:16:59.46#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.203.08:16:59.46#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.203.08:16:59.46#ibcon#ireg 17 cls_cnt 0 2006.203.08:16:59.46#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.203.08:16:59.46#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.203.08:16:59.46#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.203.08:16:59.46#ibcon#enter wrdev, iclass 27, count 0 2006.203.08:16:59.46#ibcon#first serial, iclass 27, count 0 2006.203.08:16:59.46#ibcon#enter sib2, iclass 27, count 0 2006.203.08:16:59.46#ibcon#flushed, iclass 27, count 0 2006.203.08:16:59.46#ibcon#about to write, iclass 27, count 0 2006.203.08:16:59.46#ibcon#wrote, iclass 27, count 0 2006.203.08:16:59.46#ibcon#about to read 3, iclass 27, count 0 2006.203.08:16:59.48#ibcon#read 3, iclass 27, count 0 2006.203.08:16:59.48#ibcon#about to read 4, iclass 27, count 0 2006.203.08:16:59.48#ibcon#read 4, iclass 27, count 0 2006.203.08:16:59.48#ibcon#about to read 5, iclass 27, count 0 2006.203.08:16:59.48#ibcon#read 5, iclass 27, count 0 2006.203.08:16:59.48#ibcon#about to read 6, iclass 27, count 0 2006.203.08:16:59.48#ibcon#read 6, iclass 27, count 0 2006.203.08:16:59.48#ibcon#end of sib2, iclass 27, count 0 2006.203.08:16:59.48#ibcon#*mode == 0, iclass 27, count 0 2006.203.08:16:59.48#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.203.08:16:59.48#ibcon#[26=FRQ=02,572.99\r\n] 2006.203.08:16:59.48#ibcon#*before write, iclass 27, count 0 2006.203.08:16:59.48#ibcon#enter sib2, iclass 27, count 0 2006.203.08:16:59.48#ibcon#flushed, iclass 27, count 0 2006.203.08:16:59.48#ibcon#about to write, iclass 27, count 0 2006.203.08:16:59.48#ibcon#wrote, iclass 27, count 0 2006.203.08:16:59.48#ibcon#about to read 3, iclass 27, count 0 2006.203.08:16:59.52#ibcon#read 3, iclass 27, count 0 2006.203.08:16:59.52#ibcon#about to read 4, iclass 27, count 0 2006.203.08:16:59.52#ibcon#read 4, iclass 27, count 0 2006.203.08:16:59.52#ibcon#about to read 5, iclass 27, count 0 2006.203.08:16:59.52#ibcon#read 5, iclass 27, count 0 2006.203.08:16:59.52#ibcon#about to read 6, iclass 27, count 0 2006.203.08:16:59.52#ibcon#read 6, iclass 27, count 0 2006.203.08:16:59.52#ibcon#end of sib2, iclass 27, count 0 2006.203.08:16:59.52#ibcon#*after write, iclass 27, count 0 2006.203.08:16:59.52#ibcon#*before return 0, iclass 27, count 0 2006.203.08:16:59.52#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.203.08:16:59.52#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.203.08:16:59.52#ibcon#about to clear, iclass 27 cls_cnt 0 2006.203.08:16:59.52#ibcon#cleared, iclass 27 cls_cnt 0 2006.203.08:16:59.52$vc4f8/va=2,7 2006.203.08:16:59.52#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.203.08:16:59.52#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.203.08:16:59.52#ibcon#ireg 11 cls_cnt 2 2006.203.08:16:59.52#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.203.08:16:59.59#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.203.08:16:59.59#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.203.08:16:59.59#ibcon#enter wrdev, iclass 29, count 2 2006.203.08:16:59.59#ibcon#first serial, iclass 29, count 2 2006.203.08:16:59.59#ibcon#enter sib2, iclass 29, count 2 2006.203.08:16:59.59#ibcon#flushed, iclass 29, count 2 2006.203.08:16:59.59#ibcon#about to write, iclass 29, count 2 2006.203.08:16:59.59#ibcon#wrote, iclass 29, count 2 2006.203.08:16:59.59#ibcon#about to read 3, iclass 29, count 2 2006.203.08:16:59.61#ibcon#read 3, iclass 29, count 2 2006.203.08:16:59.61#ibcon#about to read 4, iclass 29, count 2 2006.203.08:16:59.61#ibcon#read 4, iclass 29, count 2 2006.203.08:16:59.61#ibcon#about to read 5, iclass 29, count 2 2006.203.08:16:59.61#ibcon#read 5, iclass 29, count 2 2006.203.08:16:59.61#ibcon#about to read 6, iclass 29, count 2 2006.203.08:16:59.61#ibcon#read 6, iclass 29, count 2 2006.203.08:16:59.61#ibcon#end of sib2, iclass 29, count 2 2006.203.08:16:59.61#ibcon#*mode == 0, iclass 29, count 2 2006.203.08:16:59.61#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.203.08:16:59.61#ibcon#[25=AT02-07\r\n] 2006.203.08:16:59.61#ibcon#*before write, iclass 29, count 2 2006.203.08:16:59.61#ibcon#enter sib2, iclass 29, count 2 2006.203.08:16:59.61#ibcon#flushed, iclass 29, count 2 2006.203.08:16:59.61#ibcon#about to write, iclass 29, count 2 2006.203.08:16:59.61#ibcon#wrote, iclass 29, count 2 2006.203.08:16:59.61#ibcon#about to read 3, iclass 29, count 2 2006.203.08:16:59.63#ibcon#read 3, iclass 29, count 2 2006.203.08:16:59.63#ibcon#about to read 4, iclass 29, count 2 2006.203.08:16:59.63#ibcon#read 4, iclass 29, count 2 2006.203.08:16:59.63#ibcon#about to read 5, iclass 29, count 2 2006.203.08:16:59.63#ibcon#read 5, iclass 29, count 2 2006.203.08:16:59.63#ibcon#about to read 6, iclass 29, count 2 2006.203.08:16:59.63#ibcon#read 6, iclass 29, count 2 2006.203.08:16:59.63#ibcon#end of sib2, iclass 29, count 2 2006.203.08:16:59.63#ibcon#*after write, iclass 29, count 2 2006.203.08:16:59.63#ibcon#*before return 0, iclass 29, count 2 2006.203.08:16:59.63#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.203.08:16:59.63#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.203.08:16:59.63#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.203.08:16:59.63#ibcon#ireg 7 cls_cnt 0 2006.203.08:16:59.63#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.203.08:16:59.75#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.203.08:16:59.75#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.203.08:16:59.75#ibcon#enter wrdev, iclass 29, count 0 2006.203.08:16:59.75#ibcon#first serial, iclass 29, count 0 2006.203.08:16:59.75#ibcon#enter sib2, iclass 29, count 0 2006.203.08:16:59.75#ibcon#flushed, iclass 29, count 0 2006.203.08:16:59.75#ibcon#about to write, iclass 29, count 0 2006.203.08:16:59.75#ibcon#wrote, iclass 29, count 0 2006.203.08:16:59.75#ibcon#about to read 3, iclass 29, count 0 2006.203.08:16:59.77#ibcon#read 3, iclass 29, count 0 2006.203.08:16:59.77#ibcon#about to read 4, iclass 29, count 0 2006.203.08:16:59.77#ibcon#read 4, iclass 29, count 0 2006.203.08:16:59.77#ibcon#about to read 5, iclass 29, count 0 2006.203.08:16:59.77#ibcon#read 5, iclass 29, count 0 2006.203.08:16:59.77#ibcon#about to read 6, iclass 29, count 0 2006.203.08:16:59.77#ibcon#read 6, iclass 29, count 0 2006.203.08:16:59.77#ibcon#end of sib2, iclass 29, count 0 2006.203.08:16:59.77#ibcon#*mode == 0, iclass 29, count 0 2006.203.08:16:59.77#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.203.08:16:59.77#ibcon#[25=USB\r\n] 2006.203.08:16:59.77#ibcon#*before write, iclass 29, count 0 2006.203.08:16:59.77#ibcon#enter sib2, iclass 29, count 0 2006.203.08:16:59.77#ibcon#flushed, iclass 29, count 0 2006.203.08:16:59.77#ibcon#about to write, iclass 29, count 0 2006.203.08:16:59.77#ibcon#wrote, iclass 29, count 0 2006.203.08:16:59.77#ibcon#about to read 3, iclass 29, count 0 2006.203.08:16:59.80#ibcon#read 3, iclass 29, count 0 2006.203.08:16:59.80#ibcon#about to read 4, iclass 29, count 0 2006.203.08:16:59.80#ibcon#read 4, iclass 29, count 0 2006.203.08:16:59.80#ibcon#about to read 5, iclass 29, count 0 2006.203.08:16:59.80#ibcon#read 5, iclass 29, count 0 2006.203.08:16:59.80#ibcon#about to read 6, iclass 29, count 0 2006.203.08:16:59.80#ibcon#read 6, iclass 29, count 0 2006.203.08:16:59.80#ibcon#end of sib2, iclass 29, count 0 2006.203.08:16:59.80#ibcon#*after write, iclass 29, count 0 2006.203.08:16:59.80#ibcon#*before return 0, iclass 29, count 0 2006.203.08:16:59.80#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.203.08:16:59.80#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.203.08:16:59.80#ibcon#about to clear, iclass 29 cls_cnt 0 2006.203.08:16:59.80#ibcon#cleared, iclass 29 cls_cnt 0 2006.203.08:16:59.80$vc4f8/valo=3,672.99 2006.203.08:16:59.80#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.203.08:16:59.80#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.203.08:16:59.80#ibcon#ireg 17 cls_cnt 0 2006.203.08:16:59.80#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.203.08:16:59.80#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.203.08:16:59.80#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.203.08:16:59.80#ibcon#enter wrdev, iclass 31, count 0 2006.203.08:16:59.80#ibcon#first serial, iclass 31, count 0 2006.203.08:16:59.80#ibcon#enter sib2, iclass 31, count 0 2006.203.08:16:59.80#ibcon#flushed, iclass 31, count 0 2006.203.08:16:59.80#ibcon#about to write, iclass 31, count 0 2006.203.08:16:59.80#ibcon#wrote, iclass 31, count 0 2006.203.08:16:59.80#ibcon#about to read 3, iclass 31, count 0 2006.203.08:16:59.82#ibcon#read 3, iclass 31, count 0 2006.203.08:16:59.82#ibcon#about to read 4, iclass 31, count 0 2006.203.08:16:59.82#ibcon#read 4, iclass 31, count 0 2006.203.08:16:59.82#ibcon#about to read 5, iclass 31, count 0 2006.203.08:16:59.82#ibcon#read 5, iclass 31, count 0 2006.203.08:16:59.82#ibcon#about to read 6, iclass 31, count 0 2006.203.08:16:59.82#ibcon#read 6, iclass 31, count 0 2006.203.08:16:59.82#ibcon#end of sib2, iclass 31, count 0 2006.203.08:16:59.82#ibcon#*mode == 0, iclass 31, count 0 2006.203.08:16:59.82#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.203.08:16:59.82#ibcon#[26=FRQ=03,672.99\r\n] 2006.203.08:16:59.82#ibcon#*before write, iclass 31, count 0 2006.203.08:16:59.82#ibcon#enter sib2, iclass 31, count 0 2006.203.08:16:59.82#ibcon#flushed, iclass 31, count 0 2006.203.08:16:59.82#ibcon#about to write, iclass 31, count 0 2006.203.08:16:59.82#ibcon#wrote, iclass 31, count 0 2006.203.08:16:59.82#ibcon#about to read 3, iclass 31, count 0 2006.203.08:16:59.86#ibcon#read 3, iclass 31, count 0 2006.203.08:16:59.86#ibcon#about to read 4, iclass 31, count 0 2006.203.08:16:59.86#ibcon#read 4, iclass 31, count 0 2006.203.08:16:59.86#ibcon#about to read 5, iclass 31, count 0 2006.203.08:16:59.86#ibcon#read 5, iclass 31, count 0 2006.203.08:16:59.86#ibcon#about to read 6, iclass 31, count 0 2006.203.08:16:59.86#ibcon#read 6, iclass 31, count 0 2006.203.08:16:59.86#ibcon#end of sib2, iclass 31, count 0 2006.203.08:16:59.86#ibcon#*after write, iclass 31, count 0 2006.203.08:16:59.86#ibcon#*before return 0, iclass 31, count 0 2006.203.08:16:59.86#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.203.08:16:59.86#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.203.08:16:59.86#ibcon#about to clear, iclass 31 cls_cnt 0 2006.203.08:16:59.86#ibcon#cleared, iclass 31 cls_cnt 0 2006.203.08:16:59.86$vc4f8/va=3,8 2006.203.08:16:59.86#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.203.08:16:59.86#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.203.08:16:59.86#ibcon#ireg 11 cls_cnt 2 2006.203.08:16:59.86#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.203.08:16:59.88#abcon#<5=/05 1.6 3.1 23.571001001.1\r\n> 2006.203.08:16:59.90#abcon#{5=INTERFACE CLEAR} 2006.203.08:16:59.93#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.203.08:16:59.93#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.203.08:16:59.93#ibcon#enter wrdev, iclass 34, count 2 2006.203.08:16:59.93#ibcon#first serial, iclass 34, count 2 2006.203.08:16:59.93#ibcon#enter sib2, iclass 34, count 2 2006.203.08:16:59.93#ibcon#flushed, iclass 34, count 2 2006.203.08:16:59.93#ibcon#about to write, iclass 34, count 2 2006.203.08:16:59.93#ibcon#wrote, iclass 34, count 2 2006.203.08:16:59.93#ibcon#about to read 3, iclass 34, count 2 2006.203.08:16:59.95#ibcon#read 3, iclass 34, count 2 2006.203.08:16:59.95#ibcon#about to read 4, iclass 34, count 2 2006.203.08:16:59.95#ibcon#read 4, iclass 34, count 2 2006.203.08:16:59.95#ibcon#about to read 5, iclass 34, count 2 2006.203.08:16:59.95#ibcon#read 5, iclass 34, count 2 2006.203.08:16:59.95#ibcon#about to read 6, iclass 34, count 2 2006.203.08:16:59.95#ibcon#read 6, iclass 34, count 2 2006.203.08:16:59.95#ibcon#end of sib2, iclass 34, count 2 2006.203.08:16:59.95#ibcon#*mode == 0, iclass 34, count 2 2006.203.08:16:59.95#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.203.08:16:59.95#ibcon#[25=AT03-08\r\n] 2006.203.08:16:59.95#ibcon#*before write, iclass 34, count 2 2006.203.08:16:59.95#ibcon#enter sib2, iclass 34, count 2 2006.203.08:16:59.95#ibcon#flushed, iclass 34, count 2 2006.203.08:16:59.95#ibcon#about to write, iclass 34, count 2 2006.203.08:16:59.95#ibcon#wrote, iclass 34, count 2 2006.203.08:16:59.95#ibcon#about to read 3, iclass 34, count 2 2006.203.08:16:59.96#abcon#[5=S1D000X0/0*\r\n] 2006.203.08:16:59.97#ibcon#read 3, iclass 34, count 2 2006.203.08:16:59.97#ibcon#about to read 4, iclass 34, count 2 2006.203.08:16:59.97#ibcon#read 4, iclass 34, count 2 2006.203.08:16:59.97#ibcon#about to read 5, iclass 34, count 2 2006.203.08:16:59.97#ibcon#read 5, iclass 34, count 2 2006.203.08:16:59.97#ibcon#about to read 6, iclass 34, count 2 2006.203.08:16:59.97#ibcon#read 6, iclass 34, count 2 2006.203.08:16:59.97#ibcon#end of sib2, iclass 34, count 2 2006.203.08:16:59.97#ibcon#*after write, iclass 34, count 2 2006.203.08:16:59.97#ibcon#*before return 0, iclass 34, count 2 2006.203.08:16:59.97#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.203.08:16:59.97#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.203.08:16:59.97#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.203.08:16:59.97#ibcon#ireg 7 cls_cnt 0 2006.203.08:16:59.97#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.203.08:17:00.09#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.203.08:17:00.09#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.203.08:17:00.09#ibcon#enter wrdev, iclass 34, count 0 2006.203.08:17:00.09#ibcon#first serial, iclass 34, count 0 2006.203.08:17:00.09#ibcon#enter sib2, iclass 34, count 0 2006.203.08:17:00.09#ibcon#flushed, iclass 34, count 0 2006.203.08:17:00.09#ibcon#about to write, iclass 34, count 0 2006.203.08:17:00.09#ibcon#wrote, iclass 34, count 0 2006.203.08:17:00.09#ibcon#about to read 3, iclass 34, count 0 2006.203.08:17:00.11#ibcon#read 3, iclass 34, count 0 2006.203.08:17:00.11#ibcon#about to read 4, iclass 34, count 0 2006.203.08:17:00.11#ibcon#read 4, iclass 34, count 0 2006.203.08:17:00.11#ibcon#about to read 5, iclass 34, count 0 2006.203.08:17:00.11#ibcon#read 5, iclass 34, count 0 2006.203.08:17:00.11#ibcon#about to read 6, iclass 34, count 0 2006.203.08:17:00.11#ibcon#read 6, iclass 34, count 0 2006.203.08:17:00.11#ibcon#end of sib2, iclass 34, count 0 2006.203.08:17:00.11#ibcon#*mode == 0, iclass 34, count 0 2006.203.08:17:00.11#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.203.08:17:00.11#ibcon#[25=USB\r\n] 2006.203.08:17:00.11#ibcon#*before write, iclass 34, count 0 2006.203.08:17:00.11#ibcon#enter sib2, iclass 34, count 0 2006.203.08:17:00.11#ibcon#flushed, iclass 34, count 0 2006.203.08:17:00.11#ibcon#about to write, iclass 34, count 0 2006.203.08:17:00.11#ibcon#wrote, iclass 34, count 0 2006.203.08:17:00.11#ibcon#about to read 3, iclass 34, count 0 2006.203.08:17:00.14#ibcon#read 3, iclass 34, count 0 2006.203.08:17:00.14#ibcon#about to read 4, iclass 34, count 0 2006.203.08:17:00.14#ibcon#read 4, iclass 34, count 0 2006.203.08:17:00.14#ibcon#about to read 5, iclass 34, count 0 2006.203.08:17:00.14#ibcon#read 5, iclass 34, count 0 2006.203.08:17:00.14#ibcon#about to read 6, iclass 34, count 0 2006.203.08:17:00.14#ibcon#read 6, iclass 34, count 0 2006.203.08:17:00.14#ibcon#end of sib2, iclass 34, count 0 2006.203.08:17:00.14#ibcon#*after write, iclass 34, count 0 2006.203.08:17:00.14#ibcon#*before return 0, iclass 34, count 0 2006.203.08:17:00.14#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.203.08:17:00.14#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.203.08:17:00.14#ibcon#about to clear, iclass 34 cls_cnt 0 2006.203.08:17:00.14#ibcon#cleared, iclass 34 cls_cnt 0 2006.203.08:17:00.14$vc4f8/valo=4,832.99 2006.203.08:17:00.14#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.203.08:17:00.14#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.203.08:17:00.14#ibcon#ireg 17 cls_cnt 0 2006.203.08:17:00.14#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.203.08:17:00.14#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.203.08:17:00.14#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.203.08:17:00.14#ibcon#enter wrdev, iclass 39, count 0 2006.203.08:17:00.14#ibcon#first serial, iclass 39, count 0 2006.203.08:17:00.14#ibcon#enter sib2, iclass 39, count 0 2006.203.08:17:00.14#ibcon#flushed, iclass 39, count 0 2006.203.08:17:00.14#ibcon#about to write, iclass 39, count 0 2006.203.08:17:00.14#ibcon#wrote, iclass 39, count 0 2006.203.08:17:00.14#ibcon#about to read 3, iclass 39, count 0 2006.203.08:17:00.16#ibcon#read 3, iclass 39, count 0 2006.203.08:17:00.16#ibcon#about to read 4, iclass 39, count 0 2006.203.08:17:00.16#ibcon#read 4, iclass 39, count 0 2006.203.08:17:00.16#ibcon#about to read 5, iclass 39, count 0 2006.203.08:17:00.16#ibcon#read 5, iclass 39, count 0 2006.203.08:17:00.16#ibcon#about to read 6, iclass 39, count 0 2006.203.08:17:00.16#ibcon#read 6, iclass 39, count 0 2006.203.08:17:00.16#ibcon#end of sib2, iclass 39, count 0 2006.203.08:17:00.16#ibcon#*mode == 0, iclass 39, count 0 2006.203.08:17:00.16#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.203.08:17:00.16#ibcon#[26=FRQ=04,832.99\r\n] 2006.203.08:17:00.16#ibcon#*before write, iclass 39, count 0 2006.203.08:17:00.16#ibcon#enter sib2, iclass 39, count 0 2006.203.08:17:00.16#ibcon#flushed, iclass 39, count 0 2006.203.08:17:00.16#ibcon#about to write, iclass 39, count 0 2006.203.08:17:00.16#ibcon#wrote, iclass 39, count 0 2006.203.08:17:00.16#ibcon#about to read 3, iclass 39, count 0 2006.203.08:17:00.20#ibcon#read 3, iclass 39, count 0 2006.203.08:17:00.20#ibcon#about to read 4, iclass 39, count 0 2006.203.08:17:00.20#ibcon#read 4, iclass 39, count 0 2006.203.08:17:00.20#ibcon#about to read 5, iclass 39, count 0 2006.203.08:17:00.20#ibcon#read 5, iclass 39, count 0 2006.203.08:17:00.20#ibcon#about to read 6, iclass 39, count 0 2006.203.08:17:00.20#ibcon#read 6, iclass 39, count 0 2006.203.08:17:00.20#ibcon#end of sib2, iclass 39, count 0 2006.203.08:17:00.20#ibcon#*after write, iclass 39, count 0 2006.203.08:17:00.20#ibcon#*before return 0, iclass 39, count 0 2006.203.08:17:00.20#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.203.08:17:00.20#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.203.08:17:00.20#ibcon#about to clear, iclass 39 cls_cnt 0 2006.203.08:17:00.20#ibcon#cleared, iclass 39 cls_cnt 0 2006.203.08:17:00.20$vc4f8/va=4,7 2006.203.08:17:00.20#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.203.08:17:00.20#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.203.08:17:00.20#ibcon#ireg 11 cls_cnt 2 2006.203.08:17:00.20#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.203.08:17:00.26#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.203.08:17:00.26#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.203.08:17:00.26#ibcon#enter wrdev, iclass 3, count 2 2006.203.08:17:00.26#ibcon#first serial, iclass 3, count 2 2006.203.08:17:00.26#ibcon#enter sib2, iclass 3, count 2 2006.203.08:17:00.26#ibcon#flushed, iclass 3, count 2 2006.203.08:17:00.26#ibcon#about to write, iclass 3, count 2 2006.203.08:17:00.26#ibcon#wrote, iclass 3, count 2 2006.203.08:17:00.26#ibcon#about to read 3, iclass 3, count 2 2006.203.08:17:00.28#ibcon#read 3, iclass 3, count 2 2006.203.08:17:00.28#ibcon#about to read 4, iclass 3, count 2 2006.203.08:17:00.28#ibcon#read 4, iclass 3, count 2 2006.203.08:17:00.28#ibcon#about to read 5, iclass 3, count 2 2006.203.08:17:00.28#ibcon#read 5, iclass 3, count 2 2006.203.08:17:00.28#ibcon#about to read 6, iclass 3, count 2 2006.203.08:17:00.28#ibcon#read 6, iclass 3, count 2 2006.203.08:17:00.28#ibcon#end of sib2, iclass 3, count 2 2006.203.08:17:00.28#ibcon#*mode == 0, iclass 3, count 2 2006.203.08:17:00.28#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.203.08:17:00.28#ibcon#[25=AT04-07\r\n] 2006.203.08:17:00.28#ibcon#*before write, iclass 3, count 2 2006.203.08:17:00.28#ibcon#enter sib2, iclass 3, count 2 2006.203.08:17:00.28#ibcon#flushed, iclass 3, count 2 2006.203.08:17:00.28#ibcon#about to write, iclass 3, count 2 2006.203.08:17:00.28#ibcon#wrote, iclass 3, count 2 2006.203.08:17:00.28#ibcon#about to read 3, iclass 3, count 2 2006.203.08:17:00.31#ibcon#read 3, iclass 3, count 2 2006.203.08:17:00.31#ibcon#about to read 4, iclass 3, count 2 2006.203.08:17:00.31#ibcon#read 4, iclass 3, count 2 2006.203.08:17:00.31#ibcon#about to read 5, iclass 3, count 2 2006.203.08:17:00.31#ibcon#read 5, iclass 3, count 2 2006.203.08:17:00.31#ibcon#about to read 6, iclass 3, count 2 2006.203.08:17:00.31#ibcon#read 6, iclass 3, count 2 2006.203.08:17:00.31#ibcon#end of sib2, iclass 3, count 2 2006.203.08:17:00.31#ibcon#*after write, iclass 3, count 2 2006.203.08:17:00.31#ibcon#*before return 0, iclass 3, count 2 2006.203.08:17:00.31#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.203.08:17:00.31#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.203.08:17:00.31#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.203.08:17:00.31#ibcon#ireg 7 cls_cnt 0 2006.203.08:17:00.31#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.203.08:17:00.43#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.203.08:17:00.43#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.203.08:17:00.43#ibcon#enter wrdev, iclass 3, count 0 2006.203.08:17:00.43#ibcon#first serial, iclass 3, count 0 2006.203.08:17:00.43#ibcon#enter sib2, iclass 3, count 0 2006.203.08:17:00.43#ibcon#flushed, iclass 3, count 0 2006.203.08:17:00.43#ibcon#about to write, iclass 3, count 0 2006.203.08:17:00.43#ibcon#wrote, iclass 3, count 0 2006.203.08:17:00.43#ibcon#about to read 3, iclass 3, count 0 2006.203.08:17:00.45#ibcon#read 3, iclass 3, count 0 2006.203.08:17:00.45#ibcon#about to read 4, iclass 3, count 0 2006.203.08:17:00.45#ibcon#read 4, iclass 3, count 0 2006.203.08:17:00.45#ibcon#about to read 5, iclass 3, count 0 2006.203.08:17:00.45#ibcon#read 5, iclass 3, count 0 2006.203.08:17:00.45#ibcon#about to read 6, iclass 3, count 0 2006.203.08:17:00.45#ibcon#read 6, iclass 3, count 0 2006.203.08:17:00.45#ibcon#end of sib2, iclass 3, count 0 2006.203.08:17:00.45#ibcon#*mode == 0, iclass 3, count 0 2006.203.08:17:00.45#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.203.08:17:00.45#ibcon#[25=USB\r\n] 2006.203.08:17:00.45#ibcon#*before write, iclass 3, count 0 2006.203.08:17:00.45#ibcon#enter sib2, iclass 3, count 0 2006.203.08:17:00.45#ibcon#flushed, iclass 3, count 0 2006.203.08:17:00.45#ibcon#about to write, iclass 3, count 0 2006.203.08:17:00.45#ibcon#wrote, iclass 3, count 0 2006.203.08:17:00.45#ibcon#about to read 3, iclass 3, count 0 2006.203.08:17:00.48#ibcon#read 3, iclass 3, count 0 2006.203.08:17:00.48#ibcon#about to read 4, iclass 3, count 0 2006.203.08:17:00.48#ibcon#read 4, iclass 3, count 0 2006.203.08:17:00.48#ibcon#about to read 5, iclass 3, count 0 2006.203.08:17:00.48#ibcon#read 5, iclass 3, count 0 2006.203.08:17:00.48#ibcon#about to read 6, iclass 3, count 0 2006.203.08:17:00.48#ibcon#read 6, iclass 3, count 0 2006.203.08:17:00.48#ibcon#end of sib2, iclass 3, count 0 2006.203.08:17:00.48#ibcon#*after write, iclass 3, count 0 2006.203.08:17:00.48#ibcon#*before return 0, iclass 3, count 0 2006.203.08:17:00.48#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.203.08:17:00.48#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.203.08:17:00.48#ibcon#about to clear, iclass 3 cls_cnt 0 2006.203.08:17:00.48#ibcon#cleared, iclass 3 cls_cnt 0 2006.203.08:17:00.48$vc4f8/valo=5,652.99 2006.203.08:17:00.48#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.203.08:17:00.48#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.203.08:17:00.48#ibcon#ireg 17 cls_cnt 0 2006.203.08:17:00.48#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.203.08:17:00.48#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.203.08:17:00.48#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.203.08:17:00.48#ibcon#enter wrdev, iclass 5, count 0 2006.203.08:17:00.48#ibcon#first serial, iclass 5, count 0 2006.203.08:17:00.48#ibcon#enter sib2, iclass 5, count 0 2006.203.08:17:00.48#ibcon#flushed, iclass 5, count 0 2006.203.08:17:00.48#ibcon#about to write, iclass 5, count 0 2006.203.08:17:00.48#ibcon#wrote, iclass 5, count 0 2006.203.08:17:00.48#ibcon#about to read 3, iclass 5, count 0 2006.203.08:17:00.50#ibcon#read 3, iclass 5, count 0 2006.203.08:17:00.50#ibcon#about to read 4, iclass 5, count 0 2006.203.08:17:00.50#ibcon#read 4, iclass 5, count 0 2006.203.08:17:00.50#ibcon#about to read 5, iclass 5, count 0 2006.203.08:17:00.50#ibcon#read 5, iclass 5, count 0 2006.203.08:17:00.50#ibcon#about to read 6, iclass 5, count 0 2006.203.08:17:00.50#ibcon#read 6, iclass 5, count 0 2006.203.08:17:00.50#ibcon#end of sib2, iclass 5, count 0 2006.203.08:17:00.50#ibcon#*mode == 0, iclass 5, count 0 2006.203.08:17:00.50#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.203.08:17:00.50#ibcon#[26=FRQ=05,652.99\r\n] 2006.203.08:17:00.50#ibcon#*before write, iclass 5, count 0 2006.203.08:17:00.50#ibcon#enter sib2, iclass 5, count 0 2006.203.08:17:00.50#ibcon#flushed, iclass 5, count 0 2006.203.08:17:00.50#ibcon#about to write, iclass 5, count 0 2006.203.08:17:00.50#ibcon#wrote, iclass 5, count 0 2006.203.08:17:00.50#ibcon#about to read 3, iclass 5, count 0 2006.203.08:17:00.54#ibcon#read 3, iclass 5, count 0 2006.203.08:17:00.54#ibcon#about to read 4, iclass 5, count 0 2006.203.08:17:00.54#ibcon#read 4, iclass 5, count 0 2006.203.08:17:00.54#ibcon#about to read 5, iclass 5, count 0 2006.203.08:17:00.54#ibcon#read 5, iclass 5, count 0 2006.203.08:17:00.54#ibcon#about to read 6, iclass 5, count 0 2006.203.08:17:00.54#ibcon#read 6, iclass 5, count 0 2006.203.08:17:00.54#ibcon#end of sib2, iclass 5, count 0 2006.203.08:17:00.54#ibcon#*after write, iclass 5, count 0 2006.203.08:17:00.54#ibcon#*before return 0, iclass 5, count 0 2006.203.08:17:00.54#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.203.08:17:00.54#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.203.08:17:00.54#ibcon#about to clear, iclass 5 cls_cnt 0 2006.203.08:17:00.54#ibcon#cleared, iclass 5 cls_cnt 0 2006.203.08:17:00.54$vc4f8/va=5,7 2006.203.08:17:00.54#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.203.08:17:00.54#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.203.08:17:00.54#ibcon#ireg 11 cls_cnt 2 2006.203.08:17:00.54#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.203.08:17:00.61#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.203.08:17:00.61#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.203.08:17:00.61#ibcon#enter wrdev, iclass 7, count 2 2006.203.08:17:00.61#ibcon#first serial, iclass 7, count 2 2006.203.08:17:00.61#ibcon#enter sib2, iclass 7, count 2 2006.203.08:17:00.61#ibcon#flushed, iclass 7, count 2 2006.203.08:17:00.61#ibcon#about to write, iclass 7, count 2 2006.203.08:17:00.61#ibcon#wrote, iclass 7, count 2 2006.203.08:17:00.61#ibcon#about to read 3, iclass 7, count 2 2006.203.08:17:00.63#ibcon#read 3, iclass 7, count 2 2006.203.08:17:00.63#ibcon#about to read 4, iclass 7, count 2 2006.203.08:17:00.63#ibcon#read 4, iclass 7, count 2 2006.203.08:17:00.63#ibcon#about to read 5, iclass 7, count 2 2006.203.08:17:00.63#ibcon#read 5, iclass 7, count 2 2006.203.08:17:00.63#ibcon#about to read 6, iclass 7, count 2 2006.203.08:17:00.63#ibcon#read 6, iclass 7, count 2 2006.203.08:17:00.63#ibcon#end of sib2, iclass 7, count 2 2006.203.08:17:00.63#ibcon#*mode == 0, iclass 7, count 2 2006.203.08:17:00.63#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.203.08:17:00.63#ibcon#[25=AT05-07\r\n] 2006.203.08:17:00.63#ibcon#*before write, iclass 7, count 2 2006.203.08:17:00.63#ibcon#enter sib2, iclass 7, count 2 2006.203.08:17:00.63#ibcon#flushed, iclass 7, count 2 2006.203.08:17:00.63#ibcon#about to write, iclass 7, count 2 2006.203.08:17:00.63#ibcon#wrote, iclass 7, count 2 2006.203.08:17:00.63#ibcon#about to read 3, iclass 7, count 2 2006.203.08:17:00.65#ibcon#read 3, iclass 7, count 2 2006.203.08:17:00.65#ibcon#about to read 4, iclass 7, count 2 2006.203.08:17:00.65#ibcon#read 4, iclass 7, count 2 2006.203.08:17:00.65#ibcon#about to read 5, iclass 7, count 2 2006.203.08:17:00.65#ibcon#read 5, iclass 7, count 2 2006.203.08:17:00.65#ibcon#about to read 6, iclass 7, count 2 2006.203.08:17:00.65#ibcon#read 6, iclass 7, count 2 2006.203.08:17:00.65#ibcon#end of sib2, iclass 7, count 2 2006.203.08:17:00.65#ibcon#*after write, iclass 7, count 2 2006.203.08:17:00.65#ibcon#*before return 0, iclass 7, count 2 2006.203.08:17:00.65#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.203.08:17:00.65#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.203.08:17:00.65#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.203.08:17:00.65#ibcon#ireg 7 cls_cnt 0 2006.203.08:17:00.65#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.203.08:17:00.77#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.203.08:17:00.77#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.203.08:17:00.77#ibcon#enter wrdev, iclass 7, count 0 2006.203.08:17:00.77#ibcon#first serial, iclass 7, count 0 2006.203.08:17:00.77#ibcon#enter sib2, iclass 7, count 0 2006.203.08:17:00.77#ibcon#flushed, iclass 7, count 0 2006.203.08:17:00.77#ibcon#about to write, iclass 7, count 0 2006.203.08:17:00.77#ibcon#wrote, iclass 7, count 0 2006.203.08:17:00.77#ibcon#about to read 3, iclass 7, count 0 2006.203.08:17:00.79#ibcon#read 3, iclass 7, count 0 2006.203.08:17:00.79#ibcon#about to read 4, iclass 7, count 0 2006.203.08:17:00.79#ibcon#read 4, iclass 7, count 0 2006.203.08:17:00.79#ibcon#about to read 5, iclass 7, count 0 2006.203.08:17:00.79#ibcon#read 5, iclass 7, count 0 2006.203.08:17:00.79#ibcon#about to read 6, iclass 7, count 0 2006.203.08:17:00.79#ibcon#read 6, iclass 7, count 0 2006.203.08:17:00.79#ibcon#end of sib2, iclass 7, count 0 2006.203.08:17:00.79#ibcon#*mode == 0, iclass 7, count 0 2006.203.08:17:00.79#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.203.08:17:00.79#ibcon#[25=USB\r\n] 2006.203.08:17:00.79#ibcon#*before write, iclass 7, count 0 2006.203.08:17:00.79#ibcon#enter sib2, iclass 7, count 0 2006.203.08:17:00.79#ibcon#flushed, iclass 7, count 0 2006.203.08:17:00.79#ibcon#about to write, iclass 7, count 0 2006.203.08:17:00.79#ibcon#wrote, iclass 7, count 0 2006.203.08:17:00.79#ibcon#about to read 3, iclass 7, count 0 2006.203.08:17:00.82#ibcon#read 3, iclass 7, count 0 2006.203.08:17:00.82#ibcon#about to read 4, iclass 7, count 0 2006.203.08:17:00.82#ibcon#read 4, iclass 7, count 0 2006.203.08:17:00.82#ibcon#about to read 5, iclass 7, count 0 2006.203.08:17:00.82#ibcon#read 5, iclass 7, count 0 2006.203.08:17:00.82#ibcon#about to read 6, iclass 7, count 0 2006.203.08:17:00.82#ibcon#read 6, iclass 7, count 0 2006.203.08:17:00.82#ibcon#end of sib2, iclass 7, count 0 2006.203.08:17:00.82#ibcon#*after write, iclass 7, count 0 2006.203.08:17:00.82#ibcon#*before return 0, iclass 7, count 0 2006.203.08:17:00.82#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.203.08:17:00.82#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.203.08:17:00.82#ibcon#about to clear, iclass 7 cls_cnt 0 2006.203.08:17:00.82#ibcon#cleared, iclass 7 cls_cnt 0 2006.203.08:17:00.82$vc4f8/valo=6,772.99 2006.203.08:17:00.82#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.203.08:17:00.82#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.203.08:17:00.82#ibcon#ireg 17 cls_cnt 0 2006.203.08:17:00.82#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.203.08:17:00.82#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.203.08:17:00.82#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.203.08:17:00.82#ibcon#enter wrdev, iclass 11, count 0 2006.203.08:17:00.82#ibcon#first serial, iclass 11, count 0 2006.203.08:17:00.82#ibcon#enter sib2, iclass 11, count 0 2006.203.08:17:00.82#ibcon#flushed, iclass 11, count 0 2006.203.08:17:00.82#ibcon#about to write, iclass 11, count 0 2006.203.08:17:00.82#ibcon#wrote, iclass 11, count 0 2006.203.08:17:00.82#ibcon#about to read 3, iclass 11, count 0 2006.203.08:17:00.84#ibcon#read 3, iclass 11, count 0 2006.203.08:17:00.84#ibcon#about to read 4, iclass 11, count 0 2006.203.08:17:00.84#ibcon#read 4, iclass 11, count 0 2006.203.08:17:00.84#ibcon#about to read 5, iclass 11, count 0 2006.203.08:17:00.84#ibcon#read 5, iclass 11, count 0 2006.203.08:17:00.84#ibcon#about to read 6, iclass 11, count 0 2006.203.08:17:00.84#ibcon#read 6, iclass 11, count 0 2006.203.08:17:00.84#ibcon#end of sib2, iclass 11, count 0 2006.203.08:17:00.84#ibcon#*mode == 0, iclass 11, count 0 2006.203.08:17:00.84#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.203.08:17:00.84#ibcon#[26=FRQ=06,772.99\r\n] 2006.203.08:17:00.84#ibcon#*before write, iclass 11, count 0 2006.203.08:17:00.84#ibcon#enter sib2, iclass 11, count 0 2006.203.08:17:00.84#ibcon#flushed, iclass 11, count 0 2006.203.08:17:00.84#ibcon#about to write, iclass 11, count 0 2006.203.08:17:00.84#ibcon#wrote, iclass 11, count 0 2006.203.08:17:00.84#ibcon#about to read 3, iclass 11, count 0 2006.203.08:17:00.88#ibcon#read 3, iclass 11, count 0 2006.203.08:17:00.88#ibcon#about to read 4, iclass 11, count 0 2006.203.08:17:00.88#ibcon#read 4, iclass 11, count 0 2006.203.08:17:00.88#ibcon#about to read 5, iclass 11, count 0 2006.203.08:17:00.88#ibcon#read 5, iclass 11, count 0 2006.203.08:17:00.88#ibcon#about to read 6, iclass 11, count 0 2006.203.08:17:00.88#ibcon#read 6, iclass 11, count 0 2006.203.08:17:00.88#ibcon#end of sib2, iclass 11, count 0 2006.203.08:17:00.88#ibcon#*after write, iclass 11, count 0 2006.203.08:17:00.88#ibcon#*before return 0, iclass 11, count 0 2006.203.08:17:00.88#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.203.08:17:00.88#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.203.08:17:00.88#ibcon#about to clear, iclass 11 cls_cnt 0 2006.203.08:17:00.88#ibcon#cleared, iclass 11 cls_cnt 0 2006.203.08:17:00.88$vc4f8/va=6,6 2006.203.08:17:00.88#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.203.08:17:00.88#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.203.08:17:00.88#ibcon#ireg 11 cls_cnt 2 2006.203.08:17:00.88#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.203.08:17:00.94#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.203.08:17:00.94#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.203.08:17:00.94#ibcon#enter wrdev, iclass 13, count 2 2006.203.08:17:00.94#ibcon#first serial, iclass 13, count 2 2006.203.08:17:00.94#ibcon#enter sib2, iclass 13, count 2 2006.203.08:17:00.94#ibcon#flushed, iclass 13, count 2 2006.203.08:17:00.94#ibcon#about to write, iclass 13, count 2 2006.203.08:17:00.94#ibcon#wrote, iclass 13, count 2 2006.203.08:17:00.94#ibcon#about to read 3, iclass 13, count 2 2006.203.08:17:00.96#ibcon#read 3, iclass 13, count 2 2006.203.08:17:00.96#ibcon#about to read 4, iclass 13, count 2 2006.203.08:17:00.96#ibcon#read 4, iclass 13, count 2 2006.203.08:17:00.96#ibcon#about to read 5, iclass 13, count 2 2006.203.08:17:00.96#ibcon#read 5, iclass 13, count 2 2006.203.08:17:00.96#ibcon#about to read 6, iclass 13, count 2 2006.203.08:17:00.96#ibcon#read 6, iclass 13, count 2 2006.203.08:17:00.96#ibcon#end of sib2, iclass 13, count 2 2006.203.08:17:00.96#ibcon#*mode == 0, iclass 13, count 2 2006.203.08:17:00.96#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.203.08:17:00.96#ibcon#[25=AT06-06\r\n] 2006.203.08:17:00.96#ibcon#*before write, iclass 13, count 2 2006.203.08:17:00.96#ibcon#enter sib2, iclass 13, count 2 2006.203.08:17:00.96#ibcon#flushed, iclass 13, count 2 2006.203.08:17:00.96#ibcon#about to write, iclass 13, count 2 2006.203.08:17:00.96#ibcon#wrote, iclass 13, count 2 2006.203.08:17:00.96#ibcon#about to read 3, iclass 13, count 2 2006.203.08:17:00.99#ibcon#read 3, iclass 13, count 2 2006.203.08:17:00.99#ibcon#about to read 4, iclass 13, count 2 2006.203.08:17:00.99#ibcon#read 4, iclass 13, count 2 2006.203.08:17:00.99#ibcon#about to read 5, iclass 13, count 2 2006.203.08:17:00.99#ibcon#read 5, iclass 13, count 2 2006.203.08:17:00.99#ibcon#about to read 6, iclass 13, count 2 2006.203.08:17:00.99#ibcon#read 6, iclass 13, count 2 2006.203.08:17:00.99#ibcon#end of sib2, iclass 13, count 2 2006.203.08:17:00.99#ibcon#*after write, iclass 13, count 2 2006.203.08:17:00.99#ibcon#*before return 0, iclass 13, count 2 2006.203.08:17:00.99#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.203.08:17:00.99#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.203.08:17:00.99#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.203.08:17:00.99#ibcon#ireg 7 cls_cnt 0 2006.203.08:17:00.99#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.203.08:17:01.11#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.203.08:17:01.11#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.203.08:17:01.11#ibcon#enter wrdev, iclass 13, count 0 2006.203.08:17:01.11#ibcon#first serial, iclass 13, count 0 2006.203.08:17:01.11#ibcon#enter sib2, iclass 13, count 0 2006.203.08:17:01.11#ibcon#flushed, iclass 13, count 0 2006.203.08:17:01.11#ibcon#about to write, iclass 13, count 0 2006.203.08:17:01.11#ibcon#wrote, iclass 13, count 0 2006.203.08:17:01.11#ibcon#about to read 3, iclass 13, count 0 2006.203.08:17:01.13#ibcon#read 3, iclass 13, count 0 2006.203.08:17:01.13#ibcon#about to read 4, iclass 13, count 0 2006.203.08:17:01.13#ibcon#read 4, iclass 13, count 0 2006.203.08:17:01.13#ibcon#about to read 5, iclass 13, count 0 2006.203.08:17:01.13#ibcon#read 5, iclass 13, count 0 2006.203.08:17:01.13#ibcon#about to read 6, iclass 13, count 0 2006.203.08:17:01.13#ibcon#read 6, iclass 13, count 0 2006.203.08:17:01.13#ibcon#end of sib2, iclass 13, count 0 2006.203.08:17:01.13#ibcon#*mode == 0, iclass 13, count 0 2006.203.08:17:01.13#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.203.08:17:01.13#ibcon#[25=USB\r\n] 2006.203.08:17:01.13#ibcon#*before write, iclass 13, count 0 2006.203.08:17:01.13#ibcon#enter sib2, iclass 13, count 0 2006.203.08:17:01.13#ibcon#flushed, iclass 13, count 0 2006.203.08:17:01.13#ibcon#about to write, iclass 13, count 0 2006.203.08:17:01.13#ibcon#wrote, iclass 13, count 0 2006.203.08:17:01.13#ibcon#about to read 3, iclass 13, count 0 2006.203.08:17:01.16#ibcon#read 3, iclass 13, count 0 2006.203.08:17:01.16#ibcon#about to read 4, iclass 13, count 0 2006.203.08:17:01.16#ibcon#read 4, iclass 13, count 0 2006.203.08:17:01.16#ibcon#about to read 5, iclass 13, count 0 2006.203.08:17:01.16#ibcon#read 5, iclass 13, count 0 2006.203.08:17:01.16#ibcon#about to read 6, iclass 13, count 0 2006.203.08:17:01.16#ibcon#read 6, iclass 13, count 0 2006.203.08:17:01.16#ibcon#end of sib2, iclass 13, count 0 2006.203.08:17:01.16#ibcon#*after write, iclass 13, count 0 2006.203.08:17:01.16#ibcon#*before return 0, iclass 13, count 0 2006.203.08:17:01.16#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.203.08:17:01.16#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.203.08:17:01.16#ibcon#about to clear, iclass 13 cls_cnt 0 2006.203.08:17:01.16#ibcon#cleared, iclass 13 cls_cnt 0 2006.203.08:17:01.16$vc4f8/valo=7,832.99 2006.203.08:17:01.16#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.203.08:17:01.16#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.203.08:17:01.16#ibcon#ireg 17 cls_cnt 0 2006.203.08:17:01.16#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.203.08:17:01.16#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.203.08:17:01.16#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.203.08:17:01.16#ibcon#enter wrdev, iclass 15, count 0 2006.203.08:17:01.16#ibcon#first serial, iclass 15, count 0 2006.203.08:17:01.16#ibcon#enter sib2, iclass 15, count 0 2006.203.08:17:01.16#ibcon#flushed, iclass 15, count 0 2006.203.08:17:01.16#ibcon#about to write, iclass 15, count 0 2006.203.08:17:01.16#ibcon#wrote, iclass 15, count 0 2006.203.08:17:01.16#ibcon#about to read 3, iclass 15, count 0 2006.203.08:17:01.18#ibcon#read 3, iclass 15, count 0 2006.203.08:17:01.18#ibcon#about to read 4, iclass 15, count 0 2006.203.08:17:01.18#ibcon#read 4, iclass 15, count 0 2006.203.08:17:01.18#ibcon#about to read 5, iclass 15, count 0 2006.203.08:17:01.18#ibcon#read 5, iclass 15, count 0 2006.203.08:17:01.18#ibcon#about to read 6, iclass 15, count 0 2006.203.08:17:01.18#ibcon#read 6, iclass 15, count 0 2006.203.08:17:01.18#ibcon#end of sib2, iclass 15, count 0 2006.203.08:17:01.18#ibcon#*mode == 0, iclass 15, count 0 2006.203.08:17:01.18#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.203.08:17:01.18#ibcon#[26=FRQ=07,832.99\r\n] 2006.203.08:17:01.18#ibcon#*before write, iclass 15, count 0 2006.203.08:17:01.18#ibcon#enter sib2, iclass 15, count 0 2006.203.08:17:01.18#ibcon#flushed, iclass 15, count 0 2006.203.08:17:01.18#ibcon#about to write, iclass 15, count 0 2006.203.08:17:01.18#ibcon#wrote, iclass 15, count 0 2006.203.08:17:01.18#ibcon#about to read 3, iclass 15, count 0 2006.203.08:17:01.22#ibcon#read 3, iclass 15, count 0 2006.203.08:17:01.22#ibcon#about to read 4, iclass 15, count 0 2006.203.08:17:01.22#ibcon#read 4, iclass 15, count 0 2006.203.08:17:01.22#ibcon#about to read 5, iclass 15, count 0 2006.203.08:17:01.22#ibcon#read 5, iclass 15, count 0 2006.203.08:17:01.22#ibcon#about to read 6, iclass 15, count 0 2006.203.08:17:01.22#ibcon#read 6, iclass 15, count 0 2006.203.08:17:01.22#ibcon#end of sib2, iclass 15, count 0 2006.203.08:17:01.22#ibcon#*after write, iclass 15, count 0 2006.203.08:17:01.22#ibcon#*before return 0, iclass 15, count 0 2006.203.08:17:01.22#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.203.08:17:01.22#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.203.08:17:01.22#ibcon#about to clear, iclass 15 cls_cnt 0 2006.203.08:17:01.22#ibcon#cleared, iclass 15 cls_cnt 0 2006.203.08:17:01.22$vc4f8/va=7,7 2006.203.08:17:01.22#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.203.08:17:01.22#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.203.08:17:01.22#ibcon#ireg 11 cls_cnt 2 2006.203.08:17:01.22#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.203.08:17:01.29#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.203.08:17:01.29#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.203.08:17:01.29#ibcon#enter wrdev, iclass 17, count 2 2006.203.08:17:01.29#ibcon#first serial, iclass 17, count 2 2006.203.08:17:01.29#ibcon#enter sib2, iclass 17, count 2 2006.203.08:17:01.29#ibcon#flushed, iclass 17, count 2 2006.203.08:17:01.29#ibcon#about to write, iclass 17, count 2 2006.203.08:17:01.29#ibcon#wrote, iclass 17, count 2 2006.203.08:17:01.29#ibcon#about to read 3, iclass 17, count 2 2006.203.08:17:01.31#ibcon#read 3, iclass 17, count 2 2006.203.08:17:01.31#ibcon#about to read 4, iclass 17, count 2 2006.203.08:17:01.31#ibcon#read 4, iclass 17, count 2 2006.203.08:17:01.31#ibcon#about to read 5, iclass 17, count 2 2006.203.08:17:01.31#ibcon#read 5, iclass 17, count 2 2006.203.08:17:01.31#ibcon#about to read 6, iclass 17, count 2 2006.203.08:17:01.31#ibcon#read 6, iclass 17, count 2 2006.203.08:17:01.31#ibcon#end of sib2, iclass 17, count 2 2006.203.08:17:01.31#ibcon#*mode == 0, iclass 17, count 2 2006.203.08:17:01.31#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.203.08:17:01.31#ibcon#[25=AT07-07\r\n] 2006.203.08:17:01.31#ibcon#*before write, iclass 17, count 2 2006.203.08:17:01.31#ibcon#enter sib2, iclass 17, count 2 2006.203.08:17:01.31#ibcon#flushed, iclass 17, count 2 2006.203.08:17:01.31#ibcon#about to write, iclass 17, count 2 2006.203.08:17:01.31#ibcon#wrote, iclass 17, count 2 2006.203.08:17:01.31#ibcon#about to read 3, iclass 17, count 2 2006.203.08:17:01.33#ibcon#read 3, iclass 17, count 2 2006.203.08:17:01.33#ibcon#about to read 4, iclass 17, count 2 2006.203.08:17:01.33#ibcon#read 4, iclass 17, count 2 2006.203.08:17:01.33#ibcon#about to read 5, iclass 17, count 2 2006.203.08:17:01.33#ibcon#read 5, iclass 17, count 2 2006.203.08:17:01.33#ibcon#about to read 6, iclass 17, count 2 2006.203.08:17:01.33#ibcon#read 6, iclass 17, count 2 2006.203.08:17:01.33#ibcon#end of sib2, iclass 17, count 2 2006.203.08:17:01.33#ibcon#*after write, iclass 17, count 2 2006.203.08:17:01.33#ibcon#*before return 0, iclass 17, count 2 2006.203.08:17:01.33#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.203.08:17:01.33#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.203.08:17:01.33#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.203.08:17:01.33#ibcon#ireg 7 cls_cnt 0 2006.203.08:17:01.33#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.203.08:17:01.45#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.203.08:17:01.45#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.203.08:17:01.45#ibcon#enter wrdev, iclass 17, count 0 2006.203.08:17:01.45#ibcon#first serial, iclass 17, count 0 2006.203.08:17:01.45#ibcon#enter sib2, iclass 17, count 0 2006.203.08:17:01.45#ibcon#flushed, iclass 17, count 0 2006.203.08:17:01.45#ibcon#about to write, iclass 17, count 0 2006.203.08:17:01.45#ibcon#wrote, iclass 17, count 0 2006.203.08:17:01.45#ibcon#about to read 3, iclass 17, count 0 2006.203.08:17:01.47#ibcon#read 3, iclass 17, count 0 2006.203.08:17:01.47#ibcon#about to read 4, iclass 17, count 0 2006.203.08:17:01.47#ibcon#read 4, iclass 17, count 0 2006.203.08:17:01.47#ibcon#about to read 5, iclass 17, count 0 2006.203.08:17:01.47#ibcon#read 5, iclass 17, count 0 2006.203.08:17:01.47#ibcon#about to read 6, iclass 17, count 0 2006.203.08:17:01.47#ibcon#read 6, iclass 17, count 0 2006.203.08:17:01.47#ibcon#end of sib2, iclass 17, count 0 2006.203.08:17:01.47#ibcon#*mode == 0, iclass 17, count 0 2006.203.08:17:01.47#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.203.08:17:01.47#ibcon#[25=USB\r\n] 2006.203.08:17:01.47#ibcon#*before write, iclass 17, count 0 2006.203.08:17:01.47#ibcon#enter sib2, iclass 17, count 0 2006.203.08:17:01.47#ibcon#flushed, iclass 17, count 0 2006.203.08:17:01.47#ibcon#about to write, iclass 17, count 0 2006.203.08:17:01.47#ibcon#wrote, iclass 17, count 0 2006.203.08:17:01.47#ibcon#about to read 3, iclass 17, count 0 2006.203.08:17:01.50#ibcon#read 3, iclass 17, count 0 2006.203.08:17:01.50#ibcon#about to read 4, iclass 17, count 0 2006.203.08:17:01.50#ibcon#read 4, iclass 17, count 0 2006.203.08:17:01.50#ibcon#about to read 5, iclass 17, count 0 2006.203.08:17:01.50#ibcon#read 5, iclass 17, count 0 2006.203.08:17:01.50#ibcon#about to read 6, iclass 17, count 0 2006.203.08:17:01.50#ibcon#read 6, iclass 17, count 0 2006.203.08:17:01.50#ibcon#end of sib2, iclass 17, count 0 2006.203.08:17:01.50#ibcon#*after write, iclass 17, count 0 2006.203.08:17:01.50#ibcon#*before return 0, iclass 17, count 0 2006.203.08:17:01.50#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.203.08:17:01.50#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.203.08:17:01.50#ibcon#about to clear, iclass 17 cls_cnt 0 2006.203.08:17:01.50#ibcon#cleared, iclass 17 cls_cnt 0 2006.203.08:17:01.50$vc4f8/valo=8,852.99 2006.203.08:17:01.50#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.203.08:17:01.50#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.203.08:17:01.50#ibcon#ireg 17 cls_cnt 0 2006.203.08:17:01.50#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.203.08:17:01.50#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.203.08:17:01.50#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.203.08:17:01.50#ibcon#enter wrdev, iclass 19, count 0 2006.203.08:17:01.50#ibcon#first serial, iclass 19, count 0 2006.203.08:17:01.50#ibcon#enter sib2, iclass 19, count 0 2006.203.08:17:01.50#ibcon#flushed, iclass 19, count 0 2006.203.08:17:01.50#ibcon#about to write, iclass 19, count 0 2006.203.08:17:01.50#ibcon#wrote, iclass 19, count 0 2006.203.08:17:01.50#ibcon#about to read 3, iclass 19, count 0 2006.203.08:17:01.52#ibcon#read 3, iclass 19, count 0 2006.203.08:17:01.52#ibcon#about to read 4, iclass 19, count 0 2006.203.08:17:01.52#ibcon#read 4, iclass 19, count 0 2006.203.08:17:01.52#ibcon#about to read 5, iclass 19, count 0 2006.203.08:17:01.52#ibcon#read 5, iclass 19, count 0 2006.203.08:17:01.52#ibcon#about to read 6, iclass 19, count 0 2006.203.08:17:01.52#ibcon#read 6, iclass 19, count 0 2006.203.08:17:01.52#ibcon#end of sib2, iclass 19, count 0 2006.203.08:17:01.52#ibcon#*mode == 0, iclass 19, count 0 2006.203.08:17:01.52#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.203.08:17:01.52#ibcon#[26=FRQ=08,852.99\r\n] 2006.203.08:17:01.52#ibcon#*before write, iclass 19, count 0 2006.203.08:17:01.52#ibcon#enter sib2, iclass 19, count 0 2006.203.08:17:01.52#ibcon#flushed, iclass 19, count 0 2006.203.08:17:01.52#ibcon#about to write, iclass 19, count 0 2006.203.08:17:01.52#ibcon#wrote, iclass 19, count 0 2006.203.08:17:01.52#ibcon#about to read 3, iclass 19, count 0 2006.203.08:17:01.56#ibcon#read 3, iclass 19, count 0 2006.203.08:17:01.56#ibcon#about to read 4, iclass 19, count 0 2006.203.08:17:01.56#ibcon#read 4, iclass 19, count 0 2006.203.08:17:01.56#ibcon#about to read 5, iclass 19, count 0 2006.203.08:17:01.56#ibcon#read 5, iclass 19, count 0 2006.203.08:17:01.56#ibcon#about to read 6, iclass 19, count 0 2006.203.08:17:01.56#ibcon#read 6, iclass 19, count 0 2006.203.08:17:01.56#ibcon#end of sib2, iclass 19, count 0 2006.203.08:17:01.56#ibcon#*after write, iclass 19, count 0 2006.203.08:17:01.56#ibcon#*before return 0, iclass 19, count 0 2006.203.08:17:01.56#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.203.08:17:01.56#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.203.08:17:01.56#ibcon#about to clear, iclass 19 cls_cnt 0 2006.203.08:17:01.56#ibcon#cleared, iclass 19 cls_cnt 0 2006.203.08:17:01.56$vc4f8/va=8,6 2006.203.08:17:01.56#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.203.08:17:01.56#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.203.08:17:01.56#ibcon#ireg 11 cls_cnt 2 2006.203.08:17:01.56#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.203.08:17:01.62#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.203.08:17:01.62#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.203.08:17:01.62#ibcon#enter wrdev, iclass 21, count 2 2006.203.08:17:01.62#ibcon#first serial, iclass 21, count 2 2006.203.08:17:01.62#ibcon#enter sib2, iclass 21, count 2 2006.203.08:17:01.62#ibcon#flushed, iclass 21, count 2 2006.203.08:17:01.62#ibcon#about to write, iclass 21, count 2 2006.203.08:17:01.62#ibcon#wrote, iclass 21, count 2 2006.203.08:17:01.62#ibcon#about to read 3, iclass 21, count 2 2006.203.08:17:01.64#ibcon#read 3, iclass 21, count 2 2006.203.08:17:01.64#ibcon#about to read 4, iclass 21, count 2 2006.203.08:17:01.64#ibcon#read 4, iclass 21, count 2 2006.203.08:17:01.64#ibcon#about to read 5, iclass 21, count 2 2006.203.08:17:01.64#ibcon#read 5, iclass 21, count 2 2006.203.08:17:01.64#ibcon#about to read 6, iclass 21, count 2 2006.203.08:17:01.64#ibcon#read 6, iclass 21, count 2 2006.203.08:17:01.64#ibcon#end of sib2, iclass 21, count 2 2006.203.08:17:01.64#ibcon#*mode == 0, iclass 21, count 2 2006.203.08:17:01.64#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.203.08:17:01.64#ibcon#[25=AT08-06\r\n] 2006.203.08:17:01.64#ibcon#*before write, iclass 21, count 2 2006.203.08:17:01.64#ibcon#enter sib2, iclass 21, count 2 2006.203.08:17:01.64#ibcon#flushed, iclass 21, count 2 2006.203.08:17:01.64#ibcon#about to write, iclass 21, count 2 2006.203.08:17:01.64#ibcon#wrote, iclass 21, count 2 2006.203.08:17:01.64#ibcon#about to read 3, iclass 21, count 2 2006.203.08:17:01.67#ibcon#read 3, iclass 21, count 2 2006.203.08:17:01.67#ibcon#about to read 4, iclass 21, count 2 2006.203.08:17:01.67#ibcon#read 4, iclass 21, count 2 2006.203.08:17:01.67#ibcon#about to read 5, iclass 21, count 2 2006.203.08:17:01.67#ibcon#read 5, iclass 21, count 2 2006.203.08:17:01.67#ibcon#about to read 6, iclass 21, count 2 2006.203.08:17:01.67#ibcon#read 6, iclass 21, count 2 2006.203.08:17:01.67#ibcon#end of sib2, iclass 21, count 2 2006.203.08:17:01.67#ibcon#*after write, iclass 21, count 2 2006.203.08:17:01.67#ibcon#*before return 0, iclass 21, count 2 2006.203.08:17:01.67#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.203.08:17:01.67#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.203.08:17:01.67#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.203.08:17:01.67#ibcon#ireg 7 cls_cnt 0 2006.203.08:17:01.67#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.203.08:17:01.79#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.203.08:17:01.79#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.203.08:17:01.79#ibcon#enter wrdev, iclass 21, count 0 2006.203.08:17:01.79#ibcon#first serial, iclass 21, count 0 2006.203.08:17:01.79#ibcon#enter sib2, iclass 21, count 0 2006.203.08:17:01.79#ibcon#flushed, iclass 21, count 0 2006.203.08:17:01.79#ibcon#about to write, iclass 21, count 0 2006.203.08:17:01.79#ibcon#wrote, iclass 21, count 0 2006.203.08:17:01.79#ibcon#about to read 3, iclass 21, count 0 2006.203.08:17:01.81#ibcon#read 3, iclass 21, count 0 2006.203.08:17:01.81#ibcon#about to read 4, iclass 21, count 0 2006.203.08:17:01.81#ibcon#read 4, iclass 21, count 0 2006.203.08:17:01.81#ibcon#about to read 5, iclass 21, count 0 2006.203.08:17:01.81#ibcon#read 5, iclass 21, count 0 2006.203.08:17:01.81#ibcon#about to read 6, iclass 21, count 0 2006.203.08:17:01.81#ibcon#read 6, iclass 21, count 0 2006.203.08:17:01.81#ibcon#end of sib2, iclass 21, count 0 2006.203.08:17:01.81#ibcon#*mode == 0, iclass 21, count 0 2006.203.08:17:01.81#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.203.08:17:01.81#ibcon#[25=USB\r\n] 2006.203.08:17:01.81#ibcon#*before write, iclass 21, count 0 2006.203.08:17:01.81#ibcon#enter sib2, iclass 21, count 0 2006.203.08:17:01.81#ibcon#flushed, iclass 21, count 0 2006.203.08:17:01.81#ibcon#about to write, iclass 21, count 0 2006.203.08:17:01.81#ibcon#wrote, iclass 21, count 0 2006.203.08:17:01.81#ibcon#about to read 3, iclass 21, count 0 2006.203.08:17:01.84#ibcon#read 3, iclass 21, count 0 2006.203.08:17:01.84#ibcon#about to read 4, iclass 21, count 0 2006.203.08:17:01.84#ibcon#read 4, iclass 21, count 0 2006.203.08:17:01.84#ibcon#about to read 5, iclass 21, count 0 2006.203.08:17:01.84#ibcon#read 5, iclass 21, count 0 2006.203.08:17:01.84#ibcon#about to read 6, iclass 21, count 0 2006.203.08:17:01.84#ibcon#read 6, iclass 21, count 0 2006.203.08:17:01.84#ibcon#end of sib2, iclass 21, count 0 2006.203.08:17:01.84#ibcon#*after write, iclass 21, count 0 2006.203.08:17:01.84#ibcon#*before return 0, iclass 21, count 0 2006.203.08:17:01.84#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.203.08:17:01.84#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.203.08:17:01.84#ibcon#about to clear, iclass 21 cls_cnt 0 2006.203.08:17:01.84#ibcon#cleared, iclass 21 cls_cnt 0 2006.203.08:17:01.84$vc4f8/vblo=1,632.99 2006.203.08:17:01.84#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.203.08:17:01.84#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.203.08:17:01.84#ibcon#ireg 17 cls_cnt 0 2006.203.08:17:01.84#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.203.08:17:01.84#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.203.08:17:01.84#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.203.08:17:01.84#ibcon#enter wrdev, iclass 23, count 0 2006.203.08:17:01.84#ibcon#first serial, iclass 23, count 0 2006.203.08:17:01.84#ibcon#enter sib2, iclass 23, count 0 2006.203.08:17:01.84#ibcon#flushed, iclass 23, count 0 2006.203.08:17:01.84#ibcon#about to write, iclass 23, count 0 2006.203.08:17:01.84#ibcon#wrote, iclass 23, count 0 2006.203.08:17:01.84#ibcon#about to read 3, iclass 23, count 0 2006.203.08:17:01.86#ibcon#read 3, iclass 23, count 0 2006.203.08:17:01.86#ibcon#about to read 4, iclass 23, count 0 2006.203.08:17:01.86#ibcon#read 4, iclass 23, count 0 2006.203.08:17:01.86#ibcon#about to read 5, iclass 23, count 0 2006.203.08:17:01.86#ibcon#read 5, iclass 23, count 0 2006.203.08:17:01.86#ibcon#about to read 6, iclass 23, count 0 2006.203.08:17:01.86#ibcon#read 6, iclass 23, count 0 2006.203.08:17:01.86#ibcon#end of sib2, iclass 23, count 0 2006.203.08:17:01.86#ibcon#*mode == 0, iclass 23, count 0 2006.203.08:17:01.86#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.203.08:17:01.86#ibcon#[28=FRQ=01,632.99\r\n] 2006.203.08:17:01.86#ibcon#*before write, iclass 23, count 0 2006.203.08:17:01.86#ibcon#enter sib2, iclass 23, count 0 2006.203.08:17:01.86#ibcon#flushed, iclass 23, count 0 2006.203.08:17:01.86#ibcon#about to write, iclass 23, count 0 2006.203.08:17:01.86#ibcon#wrote, iclass 23, count 0 2006.203.08:17:01.86#ibcon#about to read 3, iclass 23, count 0 2006.203.08:17:01.90#ibcon#read 3, iclass 23, count 0 2006.203.08:17:01.90#ibcon#about to read 4, iclass 23, count 0 2006.203.08:17:01.90#ibcon#read 4, iclass 23, count 0 2006.203.08:17:01.90#ibcon#about to read 5, iclass 23, count 0 2006.203.08:17:01.90#ibcon#read 5, iclass 23, count 0 2006.203.08:17:01.90#ibcon#about to read 6, iclass 23, count 0 2006.203.08:17:01.90#ibcon#read 6, iclass 23, count 0 2006.203.08:17:01.90#ibcon#end of sib2, iclass 23, count 0 2006.203.08:17:01.90#ibcon#*after write, iclass 23, count 0 2006.203.08:17:01.90#ibcon#*before return 0, iclass 23, count 0 2006.203.08:17:01.90#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.203.08:17:01.90#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.203.08:17:01.90#ibcon#about to clear, iclass 23 cls_cnt 0 2006.203.08:17:01.90#ibcon#cleared, iclass 23 cls_cnt 0 2006.203.08:17:01.90$vc4f8/vb=1,4 2006.203.08:17:01.90#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.203.08:17:01.90#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.203.08:17:01.90#ibcon#ireg 11 cls_cnt 2 2006.203.08:17:01.90#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.203.08:17:01.90#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.203.08:17:01.90#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.203.08:17:01.90#ibcon#enter wrdev, iclass 25, count 2 2006.203.08:17:01.90#ibcon#first serial, iclass 25, count 2 2006.203.08:17:01.90#ibcon#enter sib2, iclass 25, count 2 2006.203.08:17:01.90#ibcon#flushed, iclass 25, count 2 2006.203.08:17:01.90#ibcon#about to write, iclass 25, count 2 2006.203.08:17:01.90#ibcon#wrote, iclass 25, count 2 2006.203.08:17:01.90#ibcon#about to read 3, iclass 25, count 2 2006.203.08:17:01.92#ibcon#read 3, iclass 25, count 2 2006.203.08:17:01.92#ibcon#about to read 4, iclass 25, count 2 2006.203.08:17:01.92#ibcon#read 4, iclass 25, count 2 2006.203.08:17:01.92#ibcon#about to read 5, iclass 25, count 2 2006.203.08:17:01.92#ibcon#read 5, iclass 25, count 2 2006.203.08:17:01.92#ibcon#about to read 6, iclass 25, count 2 2006.203.08:17:01.92#ibcon#read 6, iclass 25, count 2 2006.203.08:17:01.92#ibcon#end of sib2, iclass 25, count 2 2006.203.08:17:01.92#ibcon#*mode == 0, iclass 25, count 2 2006.203.08:17:01.92#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.203.08:17:01.92#ibcon#[27=AT01-04\r\n] 2006.203.08:17:01.92#ibcon#*before write, iclass 25, count 2 2006.203.08:17:01.92#ibcon#enter sib2, iclass 25, count 2 2006.203.08:17:01.92#ibcon#flushed, iclass 25, count 2 2006.203.08:17:01.92#ibcon#about to write, iclass 25, count 2 2006.203.08:17:01.92#ibcon#wrote, iclass 25, count 2 2006.203.08:17:01.92#ibcon#about to read 3, iclass 25, count 2 2006.203.08:17:01.95#ibcon#read 3, iclass 25, count 2 2006.203.08:17:01.95#ibcon#about to read 4, iclass 25, count 2 2006.203.08:17:01.95#ibcon#read 4, iclass 25, count 2 2006.203.08:17:01.95#ibcon#about to read 5, iclass 25, count 2 2006.203.08:17:01.95#ibcon#read 5, iclass 25, count 2 2006.203.08:17:01.95#ibcon#about to read 6, iclass 25, count 2 2006.203.08:17:01.95#ibcon#read 6, iclass 25, count 2 2006.203.08:17:01.95#ibcon#end of sib2, iclass 25, count 2 2006.203.08:17:01.95#ibcon#*after write, iclass 25, count 2 2006.203.08:17:01.95#ibcon#*before return 0, iclass 25, count 2 2006.203.08:17:01.95#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.203.08:17:01.95#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.203.08:17:01.95#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.203.08:17:01.95#ibcon#ireg 7 cls_cnt 0 2006.203.08:17:01.95#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.203.08:17:02.07#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.203.08:17:02.07#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.203.08:17:02.07#ibcon#enter wrdev, iclass 25, count 0 2006.203.08:17:02.07#ibcon#first serial, iclass 25, count 0 2006.203.08:17:02.07#ibcon#enter sib2, iclass 25, count 0 2006.203.08:17:02.07#ibcon#flushed, iclass 25, count 0 2006.203.08:17:02.07#ibcon#about to write, iclass 25, count 0 2006.203.08:17:02.07#ibcon#wrote, iclass 25, count 0 2006.203.08:17:02.07#ibcon#about to read 3, iclass 25, count 0 2006.203.08:17:02.09#ibcon#read 3, iclass 25, count 0 2006.203.08:17:02.09#ibcon#about to read 4, iclass 25, count 0 2006.203.08:17:02.09#ibcon#read 4, iclass 25, count 0 2006.203.08:17:02.09#ibcon#about to read 5, iclass 25, count 0 2006.203.08:17:02.09#ibcon#read 5, iclass 25, count 0 2006.203.08:17:02.09#ibcon#about to read 6, iclass 25, count 0 2006.203.08:17:02.09#ibcon#read 6, iclass 25, count 0 2006.203.08:17:02.09#ibcon#end of sib2, iclass 25, count 0 2006.203.08:17:02.09#ibcon#*mode == 0, iclass 25, count 0 2006.203.08:17:02.09#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.203.08:17:02.09#ibcon#[27=USB\r\n] 2006.203.08:17:02.09#ibcon#*before write, iclass 25, count 0 2006.203.08:17:02.09#ibcon#enter sib2, iclass 25, count 0 2006.203.08:17:02.09#ibcon#flushed, iclass 25, count 0 2006.203.08:17:02.09#ibcon#about to write, iclass 25, count 0 2006.203.08:17:02.09#ibcon#wrote, iclass 25, count 0 2006.203.08:17:02.09#ibcon#about to read 3, iclass 25, count 0 2006.203.08:17:02.12#ibcon#read 3, iclass 25, count 0 2006.203.08:17:02.12#ibcon#about to read 4, iclass 25, count 0 2006.203.08:17:02.12#ibcon#read 4, iclass 25, count 0 2006.203.08:17:02.12#ibcon#about to read 5, iclass 25, count 0 2006.203.08:17:02.12#ibcon#read 5, iclass 25, count 0 2006.203.08:17:02.12#ibcon#about to read 6, iclass 25, count 0 2006.203.08:17:02.12#ibcon#read 6, iclass 25, count 0 2006.203.08:17:02.12#ibcon#end of sib2, iclass 25, count 0 2006.203.08:17:02.12#ibcon#*after write, iclass 25, count 0 2006.203.08:17:02.12#ibcon#*before return 0, iclass 25, count 0 2006.203.08:17:02.12#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.203.08:17:02.12#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.203.08:17:02.12#ibcon#about to clear, iclass 25 cls_cnt 0 2006.203.08:17:02.12#ibcon#cleared, iclass 25 cls_cnt 0 2006.203.08:17:02.12$vc4f8/vblo=2,640.99 2006.203.08:17:02.12#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.203.08:17:02.12#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.203.08:17:02.12#ibcon#ireg 17 cls_cnt 0 2006.203.08:17:02.12#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.203.08:17:02.12#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.203.08:17:02.12#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.203.08:17:02.12#ibcon#enter wrdev, iclass 27, count 0 2006.203.08:17:02.12#ibcon#first serial, iclass 27, count 0 2006.203.08:17:02.12#ibcon#enter sib2, iclass 27, count 0 2006.203.08:17:02.12#ibcon#flushed, iclass 27, count 0 2006.203.08:17:02.12#ibcon#about to write, iclass 27, count 0 2006.203.08:17:02.12#ibcon#wrote, iclass 27, count 0 2006.203.08:17:02.12#ibcon#about to read 3, iclass 27, count 0 2006.203.08:17:02.15#ibcon#read 3, iclass 27, count 0 2006.203.08:17:02.15#ibcon#about to read 4, iclass 27, count 0 2006.203.08:17:02.15#ibcon#read 4, iclass 27, count 0 2006.203.08:17:02.15#ibcon#about to read 5, iclass 27, count 0 2006.203.08:17:02.15#ibcon#read 5, iclass 27, count 0 2006.203.08:17:02.15#ibcon#about to read 6, iclass 27, count 0 2006.203.08:17:02.15#ibcon#read 6, iclass 27, count 0 2006.203.08:17:02.15#ibcon#end of sib2, iclass 27, count 0 2006.203.08:17:02.15#ibcon#*mode == 0, iclass 27, count 0 2006.203.08:17:02.15#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.203.08:17:02.15#ibcon#[28=FRQ=02,640.99\r\n] 2006.203.08:17:02.15#ibcon#*before write, iclass 27, count 0 2006.203.08:17:02.15#ibcon#enter sib2, iclass 27, count 0 2006.203.08:17:02.15#ibcon#flushed, iclass 27, count 0 2006.203.08:17:02.15#ibcon#about to write, iclass 27, count 0 2006.203.08:17:02.15#ibcon#wrote, iclass 27, count 0 2006.203.08:17:02.15#ibcon#about to read 3, iclass 27, count 0 2006.203.08:17:02.19#ibcon#read 3, iclass 27, count 0 2006.203.08:17:02.19#ibcon#about to read 4, iclass 27, count 0 2006.203.08:17:02.19#ibcon#read 4, iclass 27, count 0 2006.203.08:17:02.19#ibcon#about to read 5, iclass 27, count 0 2006.203.08:17:02.19#ibcon#read 5, iclass 27, count 0 2006.203.08:17:02.19#ibcon#about to read 6, iclass 27, count 0 2006.203.08:17:02.19#ibcon#read 6, iclass 27, count 0 2006.203.08:17:02.19#ibcon#end of sib2, iclass 27, count 0 2006.203.08:17:02.19#ibcon#*after write, iclass 27, count 0 2006.203.08:17:02.19#ibcon#*before return 0, iclass 27, count 0 2006.203.08:17:02.19#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.203.08:17:02.19#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.203.08:17:02.19#ibcon#about to clear, iclass 27 cls_cnt 0 2006.203.08:17:02.19#ibcon#cleared, iclass 27 cls_cnt 0 2006.203.08:17:02.19$vc4f8/vb=2,4 2006.203.08:17:02.19#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.203.08:17:02.19#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.203.08:17:02.19#ibcon#ireg 11 cls_cnt 2 2006.203.08:17:02.19#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.203.08:17:02.25#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.203.08:17:02.25#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.203.08:17:02.25#ibcon#enter wrdev, iclass 29, count 2 2006.203.08:17:02.25#ibcon#first serial, iclass 29, count 2 2006.203.08:17:02.25#ibcon#enter sib2, iclass 29, count 2 2006.203.08:17:02.25#ibcon#flushed, iclass 29, count 2 2006.203.08:17:02.25#ibcon#about to write, iclass 29, count 2 2006.203.08:17:02.25#ibcon#wrote, iclass 29, count 2 2006.203.08:17:02.25#ibcon#about to read 3, iclass 29, count 2 2006.203.08:17:02.26#ibcon#read 3, iclass 29, count 2 2006.203.08:17:02.26#ibcon#about to read 4, iclass 29, count 2 2006.203.08:17:02.26#ibcon#read 4, iclass 29, count 2 2006.203.08:17:02.26#ibcon#about to read 5, iclass 29, count 2 2006.203.08:17:02.26#ibcon#read 5, iclass 29, count 2 2006.203.08:17:02.26#ibcon#about to read 6, iclass 29, count 2 2006.203.08:17:02.26#ibcon#read 6, iclass 29, count 2 2006.203.08:17:02.26#ibcon#end of sib2, iclass 29, count 2 2006.203.08:17:02.26#ibcon#*mode == 0, iclass 29, count 2 2006.203.08:17:02.26#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.203.08:17:02.26#ibcon#[27=AT02-04\r\n] 2006.203.08:17:02.26#ibcon#*before write, iclass 29, count 2 2006.203.08:17:02.26#ibcon#enter sib2, iclass 29, count 2 2006.203.08:17:02.26#ibcon#flushed, iclass 29, count 2 2006.203.08:17:02.26#ibcon#about to write, iclass 29, count 2 2006.203.08:17:02.26#ibcon#wrote, iclass 29, count 2 2006.203.08:17:02.26#ibcon#about to read 3, iclass 29, count 2 2006.203.08:17:02.29#ibcon#read 3, iclass 29, count 2 2006.203.08:17:02.29#ibcon#about to read 4, iclass 29, count 2 2006.203.08:17:02.29#ibcon#read 4, iclass 29, count 2 2006.203.08:17:02.29#ibcon#about to read 5, iclass 29, count 2 2006.203.08:17:02.29#ibcon#read 5, iclass 29, count 2 2006.203.08:17:02.29#ibcon#about to read 6, iclass 29, count 2 2006.203.08:17:02.29#ibcon#read 6, iclass 29, count 2 2006.203.08:17:02.29#ibcon#end of sib2, iclass 29, count 2 2006.203.08:17:02.29#ibcon#*after write, iclass 29, count 2 2006.203.08:17:02.29#ibcon#*before return 0, iclass 29, count 2 2006.203.08:17:02.29#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.203.08:17:02.29#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.203.08:17:02.29#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.203.08:17:02.29#ibcon#ireg 7 cls_cnt 0 2006.203.08:17:02.29#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.203.08:17:02.41#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.203.08:17:02.41#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.203.08:17:02.41#ibcon#enter wrdev, iclass 29, count 0 2006.203.08:17:02.41#ibcon#first serial, iclass 29, count 0 2006.203.08:17:02.41#ibcon#enter sib2, iclass 29, count 0 2006.203.08:17:02.41#ibcon#flushed, iclass 29, count 0 2006.203.08:17:02.41#ibcon#about to write, iclass 29, count 0 2006.203.08:17:02.41#ibcon#wrote, iclass 29, count 0 2006.203.08:17:02.41#ibcon#about to read 3, iclass 29, count 0 2006.203.08:17:02.43#ibcon#read 3, iclass 29, count 0 2006.203.08:17:02.43#ibcon#about to read 4, iclass 29, count 0 2006.203.08:17:02.43#ibcon#read 4, iclass 29, count 0 2006.203.08:17:02.43#ibcon#about to read 5, iclass 29, count 0 2006.203.08:17:02.43#ibcon#read 5, iclass 29, count 0 2006.203.08:17:02.43#ibcon#about to read 6, iclass 29, count 0 2006.203.08:17:02.43#ibcon#read 6, iclass 29, count 0 2006.203.08:17:02.43#ibcon#end of sib2, iclass 29, count 0 2006.203.08:17:02.43#ibcon#*mode == 0, iclass 29, count 0 2006.203.08:17:02.43#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.203.08:17:02.43#ibcon#[27=USB\r\n] 2006.203.08:17:02.43#ibcon#*before write, iclass 29, count 0 2006.203.08:17:02.43#ibcon#enter sib2, iclass 29, count 0 2006.203.08:17:02.43#ibcon#flushed, iclass 29, count 0 2006.203.08:17:02.43#ibcon#about to write, iclass 29, count 0 2006.203.08:17:02.43#ibcon#wrote, iclass 29, count 0 2006.203.08:17:02.43#ibcon#about to read 3, iclass 29, count 0 2006.203.08:17:02.46#ibcon#read 3, iclass 29, count 0 2006.203.08:17:02.46#ibcon#about to read 4, iclass 29, count 0 2006.203.08:17:02.46#ibcon#read 4, iclass 29, count 0 2006.203.08:17:02.46#ibcon#about to read 5, iclass 29, count 0 2006.203.08:17:02.46#ibcon#read 5, iclass 29, count 0 2006.203.08:17:02.46#ibcon#about to read 6, iclass 29, count 0 2006.203.08:17:02.46#ibcon#read 6, iclass 29, count 0 2006.203.08:17:02.46#ibcon#end of sib2, iclass 29, count 0 2006.203.08:17:02.46#ibcon#*after write, iclass 29, count 0 2006.203.08:17:02.46#ibcon#*before return 0, iclass 29, count 0 2006.203.08:17:02.46#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.203.08:17:02.46#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.203.08:17:02.46#ibcon#about to clear, iclass 29 cls_cnt 0 2006.203.08:17:02.46#ibcon#cleared, iclass 29 cls_cnt 0 2006.203.08:17:02.46$vc4f8/vblo=3,656.99 2006.203.08:17:02.46#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.203.08:17:02.46#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.203.08:17:02.46#ibcon#ireg 17 cls_cnt 0 2006.203.08:17:02.46#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.203.08:17:02.46#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.203.08:17:02.46#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.203.08:17:02.46#ibcon#enter wrdev, iclass 31, count 0 2006.203.08:17:02.46#ibcon#first serial, iclass 31, count 0 2006.203.08:17:02.46#ibcon#enter sib2, iclass 31, count 0 2006.203.08:17:02.46#ibcon#flushed, iclass 31, count 0 2006.203.08:17:02.46#ibcon#about to write, iclass 31, count 0 2006.203.08:17:02.46#ibcon#wrote, iclass 31, count 0 2006.203.08:17:02.46#ibcon#about to read 3, iclass 31, count 0 2006.203.08:17:02.48#ibcon#read 3, iclass 31, count 0 2006.203.08:17:02.48#ibcon#about to read 4, iclass 31, count 0 2006.203.08:17:02.48#ibcon#read 4, iclass 31, count 0 2006.203.08:17:02.48#ibcon#about to read 5, iclass 31, count 0 2006.203.08:17:02.48#ibcon#read 5, iclass 31, count 0 2006.203.08:17:02.48#ibcon#about to read 6, iclass 31, count 0 2006.203.08:17:02.48#ibcon#read 6, iclass 31, count 0 2006.203.08:17:02.48#ibcon#end of sib2, iclass 31, count 0 2006.203.08:17:02.48#ibcon#*mode == 0, iclass 31, count 0 2006.203.08:17:02.48#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.203.08:17:02.48#ibcon#[28=FRQ=03,656.99\r\n] 2006.203.08:17:02.48#ibcon#*before write, iclass 31, count 0 2006.203.08:17:02.48#ibcon#enter sib2, iclass 31, count 0 2006.203.08:17:02.48#ibcon#flushed, iclass 31, count 0 2006.203.08:17:02.48#ibcon#about to write, iclass 31, count 0 2006.203.08:17:02.48#ibcon#wrote, iclass 31, count 0 2006.203.08:17:02.48#ibcon#about to read 3, iclass 31, count 0 2006.203.08:17:02.52#ibcon#read 3, iclass 31, count 0 2006.203.08:17:02.52#ibcon#about to read 4, iclass 31, count 0 2006.203.08:17:02.52#ibcon#read 4, iclass 31, count 0 2006.203.08:17:02.52#ibcon#about to read 5, iclass 31, count 0 2006.203.08:17:02.52#ibcon#read 5, iclass 31, count 0 2006.203.08:17:02.52#ibcon#about to read 6, iclass 31, count 0 2006.203.08:17:02.52#ibcon#read 6, iclass 31, count 0 2006.203.08:17:02.52#ibcon#end of sib2, iclass 31, count 0 2006.203.08:17:02.52#ibcon#*after write, iclass 31, count 0 2006.203.08:17:02.52#ibcon#*before return 0, iclass 31, count 0 2006.203.08:17:02.52#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.203.08:17:02.52#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.203.08:17:02.52#ibcon#about to clear, iclass 31 cls_cnt 0 2006.203.08:17:02.52#ibcon#cleared, iclass 31 cls_cnt 0 2006.203.08:17:02.52$vc4f8/vb=3,4 2006.203.08:17:02.52#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.203.08:17:02.52#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.203.08:17:02.52#ibcon#ireg 11 cls_cnt 2 2006.203.08:17:02.52#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.203.08:17:02.58#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.203.08:17:02.58#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.203.08:17:02.58#ibcon#enter wrdev, iclass 33, count 2 2006.203.08:17:02.58#ibcon#first serial, iclass 33, count 2 2006.203.08:17:02.58#ibcon#enter sib2, iclass 33, count 2 2006.203.08:17:02.58#ibcon#flushed, iclass 33, count 2 2006.203.08:17:02.58#ibcon#about to write, iclass 33, count 2 2006.203.08:17:02.58#ibcon#wrote, iclass 33, count 2 2006.203.08:17:02.58#ibcon#about to read 3, iclass 33, count 2 2006.203.08:17:02.60#ibcon#read 3, iclass 33, count 2 2006.203.08:17:02.60#ibcon#about to read 4, iclass 33, count 2 2006.203.08:17:02.60#ibcon#read 4, iclass 33, count 2 2006.203.08:17:02.60#ibcon#about to read 5, iclass 33, count 2 2006.203.08:17:02.60#ibcon#read 5, iclass 33, count 2 2006.203.08:17:02.60#ibcon#about to read 6, iclass 33, count 2 2006.203.08:17:02.60#ibcon#read 6, iclass 33, count 2 2006.203.08:17:02.60#ibcon#end of sib2, iclass 33, count 2 2006.203.08:17:02.60#ibcon#*mode == 0, iclass 33, count 2 2006.203.08:17:02.60#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.203.08:17:02.60#ibcon#[27=AT03-04\r\n] 2006.203.08:17:02.60#ibcon#*before write, iclass 33, count 2 2006.203.08:17:02.60#ibcon#enter sib2, iclass 33, count 2 2006.203.08:17:02.60#ibcon#flushed, iclass 33, count 2 2006.203.08:17:02.60#ibcon#about to write, iclass 33, count 2 2006.203.08:17:02.60#ibcon#wrote, iclass 33, count 2 2006.203.08:17:02.60#ibcon#about to read 3, iclass 33, count 2 2006.203.08:17:02.63#ibcon#read 3, iclass 33, count 2 2006.203.08:17:02.63#ibcon#about to read 4, iclass 33, count 2 2006.203.08:17:02.63#ibcon#read 4, iclass 33, count 2 2006.203.08:17:02.63#ibcon#about to read 5, iclass 33, count 2 2006.203.08:17:02.63#ibcon#read 5, iclass 33, count 2 2006.203.08:17:02.63#ibcon#about to read 6, iclass 33, count 2 2006.203.08:17:02.63#ibcon#read 6, iclass 33, count 2 2006.203.08:17:02.63#ibcon#end of sib2, iclass 33, count 2 2006.203.08:17:02.63#ibcon#*after write, iclass 33, count 2 2006.203.08:17:02.63#ibcon#*before return 0, iclass 33, count 2 2006.203.08:17:02.63#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.203.08:17:02.63#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.203.08:17:02.63#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.203.08:17:02.63#ibcon#ireg 7 cls_cnt 0 2006.203.08:17:02.63#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.203.08:17:02.75#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.203.08:17:02.75#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.203.08:17:02.75#ibcon#enter wrdev, iclass 33, count 0 2006.203.08:17:02.75#ibcon#first serial, iclass 33, count 0 2006.203.08:17:02.75#ibcon#enter sib2, iclass 33, count 0 2006.203.08:17:02.75#ibcon#flushed, iclass 33, count 0 2006.203.08:17:02.75#ibcon#about to write, iclass 33, count 0 2006.203.08:17:02.75#ibcon#wrote, iclass 33, count 0 2006.203.08:17:02.75#ibcon#about to read 3, iclass 33, count 0 2006.203.08:17:02.77#ibcon#read 3, iclass 33, count 0 2006.203.08:17:02.77#ibcon#about to read 4, iclass 33, count 0 2006.203.08:17:02.77#ibcon#read 4, iclass 33, count 0 2006.203.08:17:02.77#ibcon#about to read 5, iclass 33, count 0 2006.203.08:17:02.77#ibcon#read 5, iclass 33, count 0 2006.203.08:17:02.77#ibcon#about to read 6, iclass 33, count 0 2006.203.08:17:02.77#ibcon#read 6, iclass 33, count 0 2006.203.08:17:02.77#ibcon#end of sib2, iclass 33, count 0 2006.203.08:17:02.77#ibcon#*mode == 0, iclass 33, count 0 2006.203.08:17:02.77#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.203.08:17:02.77#ibcon#[27=USB\r\n] 2006.203.08:17:02.77#ibcon#*before write, iclass 33, count 0 2006.203.08:17:02.77#ibcon#enter sib2, iclass 33, count 0 2006.203.08:17:02.77#ibcon#flushed, iclass 33, count 0 2006.203.08:17:02.77#ibcon#about to write, iclass 33, count 0 2006.203.08:17:02.77#ibcon#wrote, iclass 33, count 0 2006.203.08:17:02.77#ibcon#about to read 3, iclass 33, count 0 2006.203.08:17:02.80#ibcon#read 3, iclass 33, count 0 2006.203.08:17:02.80#ibcon#about to read 4, iclass 33, count 0 2006.203.08:17:02.80#ibcon#read 4, iclass 33, count 0 2006.203.08:17:02.80#ibcon#about to read 5, iclass 33, count 0 2006.203.08:17:02.80#ibcon#read 5, iclass 33, count 0 2006.203.08:17:02.80#ibcon#about to read 6, iclass 33, count 0 2006.203.08:17:02.80#ibcon#read 6, iclass 33, count 0 2006.203.08:17:02.80#ibcon#end of sib2, iclass 33, count 0 2006.203.08:17:02.80#ibcon#*after write, iclass 33, count 0 2006.203.08:17:02.80#ibcon#*before return 0, iclass 33, count 0 2006.203.08:17:02.80#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.203.08:17:02.80#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.203.08:17:02.80#ibcon#about to clear, iclass 33 cls_cnt 0 2006.203.08:17:02.80#ibcon#cleared, iclass 33 cls_cnt 0 2006.203.08:17:02.80$vc4f8/vblo=4,712.99 2006.203.08:17:02.80#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.203.08:17:02.80#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.203.08:17:02.80#ibcon#ireg 17 cls_cnt 0 2006.203.08:17:02.80#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.203.08:17:02.80#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.203.08:17:02.80#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.203.08:17:02.80#ibcon#enter wrdev, iclass 35, count 0 2006.203.08:17:02.80#ibcon#first serial, iclass 35, count 0 2006.203.08:17:02.80#ibcon#enter sib2, iclass 35, count 0 2006.203.08:17:02.80#ibcon#flushed, iclass 35, count 0 2006.203.08:17:02.80#ibcon#about to write, iclass 35, count 0 2006.203.08:17:02.80#ibcon#wrote, iclass 35, count 0 2006.203.08:17:02.80#ibcon#about to read 3, iclass 35, count 0 2006.203.08:17:02.82#ibcon#read 3, iclass 35, count 0 2006.203.08:17:02.82#ibcon#about to read 4, iclass 35, count 0 2006.203.08:17:02.82#ibcon#read 4, iclass 35, count 0 2006.203.08:17:02.82#ibcon#about to read 5, iclass 35, count 0 2006.203.08:17:02.82#ibcon#read 5, iclass 35, count 0 2006.203.08:17:02.82#ibcon#about to read 6, iclass 35, count 0 2006.203.08:17:02.82#ibcon#read 6, iclass 35, count 0 2006.203.08:17:02.82#ibcon#end of sib2, iclass 35, count 0 2006.203.08:17:02.82#ibcon#*mode == 0, iclass 35, count 0 2006.203.08:17:02.82#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.203.08:17:02.82#ibcon#[28=FRQ=04,712.99\r\n] 2006.203.08:17:02.82#ibcon#*before write, iclass 35, count 0 2006.203.08:17:02.82#ibcon#enter sib2, iclass 35, count 0 2006.203.08:17:02.82#ibcon#flushed, iclass 35, count 0 2006.203.08:17:02.82#ibcon#about to write, iclass 35, count 0 2006.203.08:17:02.82#ibcon#wrote, iclass 35, count 0 2006.203.08:17:02.82#ibcon#about to read 3, iclass 35, count 0 2006.203.08:17:02.86#ibcon#read 3, iclass 35, count 0 2006.203.08:17:02.86#ibcon#about to read 4, iclass 35, count 0 2006.203.08:17:02.86#ibcon#read 4, iclass 35, count 0 2006.203.08:17:02.86#ibcon#about to read 5, iclass 35, count 0 2006.203.08:17:02.86#ibcon#read 5, iclass 35, count 0 2006.203.08:17:02.86#ibcon#about to read 6, iclass 35, count 0 2006.203.08:17:02.86#ibcon#read 6, iclass 35, count 0 2006.203.08:17:02.86#ibcon#end of sib2, iclass 35, count 0 2006.203.08:17:02.86#ibcon#*after write, iclass 35, count 0 2006.203.08:17:02.86#ibcon#*before return 0, iclass 35, count 0 2006.203.08:17:02.86#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.203.08:17:02.86#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.203.08:17:02.86#ibcon#about to clear, iclass 35 cls_cnt 0 2006.203.08:17:02.86#ibcon#cleared, iclass 35 cls_cnt 0 2006.203.08:17:02.86$vc4f8/vb=4,4 2006.203.08:17:02.86#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.203.08:17:02.86#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.203.08:17:02.86#ibcon#ireg 11 cls_cnt 2 2006.203.08:17:02.86#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.203.08:17:02.93#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.203.08:17:02.93#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.203.08:17:02.93#ibcon#enter wrdev, iclass 37, count 2 2006.203.08:17:02.93#ibcon#first serial, iclass 37, count 2 2006.203.08:17:02.93#ibcon#enter sib2, iclass 37, count 2 2006.203.08:17:02.93#ibcon#flushed, iclass 37, count 2 2006.203.08:17:02.93#ibcon#about to write, iclass 37, count 2 2006.203.08:17:02.93#ibcon#wrote, iclass 37, count 2 2006.203.08:17:02.93#ibcon#about to read 3, iclass 37, count 2 2006.203.08:17:02.95#ibcon#read 3, iclass 37, count 2 2006.203.08:17:02.95#ibcon#about to read 4, iclass 37, count 2 2006.203.08:17:02.95#ibcon#read 4, iclass 37, count 2 2006.203.08:17:02.95#ibcon#about to read 5, iclass 37, count 2 2006.203.08:17:02.95#ibcon#read 5, iclass 37, count 2 2006.203.08:17:02.95#ibcon#about to read 6, iclass 37, count 2 2006.203.08:17:02.95#ibcon#read 6, iclass 37, count 2 2006.203.08:17:02.95#ibcon#end of sib2, iclass 37, count 2 2006.203.08:17:02.95#ibcon#*mode == 0, iclass 37, count 2 2006.203.08:17:02.95#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.203.08:17:02.95#ibcon#[27=AT04-04\r\n] 2006.203.08:17:02.95#ibcon#*before write, iclass 37, count 2 2006.203.08:17:02.95#ibcon#enter sib2, iclass 37, count 2 2006.203.08:17:02.95#ibcon#flushed, iclass 37, count 2 2006.203.08:17:02.95#ibcon#about to write, iclass 37, count 2 2006.203.08:17:02.95#ibcon#wrote, iclass 37, count 2 2006.203.08:17:02.95#ibcon#about to read 3, iclass 37, count 2 2006.203.08:17:02.97#ibcon#read 3, iclass 37, count 2 2006.203.08:17:02.97#ibcon#about to read 4, iclass 37, count 2 2006.203.08:17:02.97#ibcon#read 4, iclass 37, count 2 2006.203.08:17:02.97#ibcon#about to read 5, iclass 37, count 2 2006.203.08:17:02.97#ibcon#read 5, iclass 37, count 2 2006.203.08:17:02.97#ibcon#about to read 6, iclass 37, count 2 2006.203.08:17:02.97#ibcon#read 6, iclass 37, count 2 2006.203.08:17:02.97#ibcon#end of sib2, iclass 37, count 2 2006.203.08:17:02.97#ibcon#*after write, iclass 37, count 2 2006.203.08:17:02.97#ibcon#*before return 0, iclass 37, count 2 2006.203.08:17:02.97#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.203.08:17:02.97#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.203.08:17:02.97#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.203.08:17:02.97#ibcon#ireg 7 cls_cnt 0 2006.203.08:17:02.97#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.203.08:17:03.09#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.203.08:17:03.09#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.203.08:17:03.09#ibcon#enter wrdev, iclass 37, count 0 2006.203.08:17:03.09#ibcon#first serial, iclass 37, count 0 2006.203.08:17:03.09#ibcon#enter sib2, iclass 37, count 0 2006.203.08:17:03.09#ibcon#flushed, iclass 37, count 0 2006.203.08:17:03.09#ibcon#about to write, iclass 37, count 0 2006.203.08:17:03.09#ibcon#wrote, iclass 37, count 0 2006.203.08:17:03.09#ibcon#about to read 3, iclass 37, count 0 2006.203.08:17:03.11#ibcon#read 3, iclass 37, count 0 2006.203.08:17:03.11#ibcon#about to read 4, iclass 37, count 0 2006.203.08:17:03.11#ibcon#read 4, iclass 37, count 0 2006.203.08:17:03.11#ibcon#about to read 5, iclass 37, count 0 2006.203.08:17:03.11#ibcon#read 5, iclass 37, count 0 2006.203.08:17:03.11#ibcon#about to read 6, iclass 37, count 0 2006.203.08:17:03.11#ibcon#read 6, iclass 37, count 0 2006.203.08:17:03.11#ibcon#end of sib2, iclass 37, count 0 2006.203.08:17:03.11#ibcon#*mode == 0, iclass 37, count 0 2006.203.08:17:03.11#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.203.08:17:03.11#ibcon#[27=USB\r\n] 2006.203.08:17:03.11#ibcon#*before write, iclass 37, count 0 2006.203.08:17:03.11#ibcon#enter sib2, iclass 37, count 0 2006.203.08:17:03.11#ibcon#flushed, iclass 37, count 0 2006.203.08:17:03.11#ibcon#about to write, iclass 37, count 0 2006.203.08:17:03.11#ibcon#wrote, iclass 37, count 0 2006.203.08:17:03.11#ibcon#about to read 3, iclass 37, count 0 2006.203.08:17:03.14#ibcon#read 3, iclass 37, count 0 2006.203.08:17:03.14#ibcon#about to read 4, iclass 37, count 0 2006.203.08:17:03.14#ibcon#read 4, iclass 37, count 0 2006.203.08:17:03.14#ibcon#about to read 5, iclass 37, count 0 2006.203.08:17:03.14#ibcon#read 5, iclass 37, count 0 2006.203.08:17:03.14#ibcon#about to read 6, iclass 37, count 0 2006.203.08:17:03.14#ibcon#read 6, iclass 37, count 0 2006.203.08:17:03.14#ibcon#end of sib2, iclass 37, count 0 2006.203.08:17:03.14#ibcon#*after write, iclass 37, count 0 2006.203.08:17:03.14#ibcon#*before return 0, iclass 37, count 0 2006.203.08:17:03.14#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.203.08:17:03.14#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.203.08:17:03.14#ibcon#about to clear, iclass 37 cls_cnt 0 2006.203.08:17:03.14#ibcon#cleared, iclass 37 cls_cnt 0 2006.203.08:17:03.14$vc4f8/vblo=5,744.99 2006.203.08:17:03.14#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.203.08:17:03.14#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.203.08:17:03.14#ibcon#ireg 17 cls_cnt 0 2006.203.08:17:03.14#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.203.08:17:03.14#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.203.08:17:03.14#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.203.08:17:03.14#ibcon#enter wrdev, iclass 39, count 0 2006.203.08:17:03.14#ibcon#first serial, iclass 39, count 0 2006.203.08:17:03.14#ibcon#enter sib2, iclass 39, count 0 2006.203.08:17:03.14#ibcon#flushed, iclass 39, count 0 2006.203.08:17:03.14#ibcon#about to write, iclass 39, count 0 2006.203.08:17:03.14#ibcon#wrote, iclass 39, count 0 2006.203.08:17:03.14#ibcon#about to read 3, iclass 39, count 0 2006.203.08:17:03.16#ibcon#read 3, iclass 39, count 0 2006.203.08:17:03.16#ibcon#about to read 4, iclass 39, count 0 2006.203.08:17:03.16#ibcon#read 4, iclass 39, count 0 2006.203.08:17:03.16#ibcon#about to read 5, iclass 39, count 0 2006.203.08:17:03.16#ibcon#read 5, iclass 39, count 0 2006.203.08:17:03.16#ibcon#about to read 6, iclass 39, count 0 2006.203.08:17:03.16#ibcon#read 6, iclass 39, count 0 2006.203.08:17:03.16#ibcon#end of sib2, iclass 39, count 0 2006.203.08:17:03.16#ibcon#*mode == 0, iclass 39, count 0 2006.203.08:17:03.16#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.203.08:17:03.16#ibcon#[28=FRQ=05,744.99\r\n] 2006.203.08:17:03.16#ibcon#*before write, iclass 39, count 0 2006.203.08:17:03.16#ibcon#enter sib2, iclass 39, count 0 2006.203.08:17:03.16#ibcon#flushed, iclass 39, count 0 2006.203.08:17:03.16#ibcon#about to write, iclass 39, count 0 2006.203.08:17:03.16#ibcon#wrote, iclass 39, count 0 2006.203.08:17:03.16#ibcon#about to read 3, iclass 39, count 0 2006.203.08:17:03.20#ibcon#read 3, iclass 39, count 0 2006.203.08:17:03.20#ibcon#about to read 4, iclass 39, count 0 2006.203.08:17:03.20#ibcon#read 4, iclass 39, count 0 2006.203.08:17:03.20#ibcon#about to read 5, iclass 39, count 0 2006.203.08:17:03.20#ibcon#read 5, iclass 39, count 0 2006.203.08:17:03.20#ibcon#about to read 6, iclass 39, count 0 2006.203.08:17:03.20#ibcon#read 6, iclass 39, count 0 2006.203.08:17:03.20#ibcon#end of sib2, iclass 39, count 0 2006.203.08:17:03.20#ibcon#*after write, iclass 39, count 0 2006.203.08:17:03.20#ibcon#*before return 0, iclass 39, count 0 2006.203.08:17:03.20#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.203.08:17:03.20#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.203.08:17:03.20#ibcon#about to clear, iclass 39 cls_cnt 0 2006.203.08:17:03.20#ibcon#cleared, iclass 39 cls_cnt 0 2006.203.08:17:03.20$vc4f8/vb=5,3 2006.203.08:17:03.20#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.203.08:17:03.20#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.203.08:17:03.20#ibcon#ireg 11 cls_cnt 2 2006.203.08:17:03.20#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.203.08:17:03.26#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.203.08:17:03.26#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.203.08:17:03.26#ibcon#enter wrdev, iclass 3, count 2 2006.203.08:17:03.26#ibcon#first serial, iclass 3, count 2 2006.203.08:17:03.26#ibcon#enter sib2, iclass 3, count 2 2006.203.08:17:03.26#ibcon#flushed, iclass 3, count 2 2006.203.08:17:03.26#ibcon#about to write, iclass 3, count 2 2006.203.08:17:03.26#ibcon#wrote, iclass 3, count 2 2006.203.08:17:03.26#ibcon#about to read 3, iclass 3, count 2 2006.203.08:17:03.28#ibcon#read 3, iclass 3, count 2 2006.203.08:17:03.28#ibcon#about to read 4, iclass 3, count 2 2006.203.08:17:03.28#ibcon#read 4, iclass 3, count 2 2006.203.08:17:03.28#ibcon#about to read 5, iclass 3, count 2 2006.203.08:17:03.28#ibcon#read 5, iclass 3, count 2 2006.203.08:17:03.28#ibcon#about to read 6, iclass 3, count 2 2006.203.08:17:03.28#ibcon#read 6, iclass 3, count 2 2006.203.08:17:03.28#ibcon#end of sib2, iclass 3, count 2 2006.203.08:17:03.28#ibcon#*mode == 0, iclass 3, count 2 2006.203.08:17:03.28#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.203.08:17:03.28#ibcon#[27=AT05-03\r\n] 2006.203.08:17:03.28#ibcon#*before write, iclass 3, count 2 2006.203.08:17:03.28#ibcon#enter sib2, iclass 3, count 2 2006.203.08:17:03.28#ibcon#flushed, iclass 3, count 2 2006.203.08:17:03.28#ibcon#about to write, iclass 3, count 2 2006.203.08:17:03.28#ibcon#wrote, iclass 3, count 2 2006.203.08:17:03.28#ibcon#about to read 3, iclass 3, count 2 2006.203.08:17:03.31#ibcon#read 3, iclass 3, count 2 2006.203.08:17:03.31#ibcon#about to read 4, iclass 3, count 2 2006.203.08:17:03.31#ibcon#read 4, iclass 3, count 2 2006.203.08:17:03.31#ibcon#about to read 5, iclass 3, count 2 2006.203.08:17:03.31#ibcon#read 5, iclass 3, count 2 2006.203.08:17:03.31#ibcon#about to read 6, iclass 3, count 2 2006.203.08:17:03.31#ibcon#read 6, iclass 3, count 2 2006.203.08:17:03.31#ibcon#end of sib2, iclass 3, count 2 2006.203.08:17:03.31#ibcon#*after write, iclass 3, count 2 2006.203.08:17:03.31#ibcon#*before return 0, iclass 3, count 2 2006.203.08:17:03.31#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.203.08:17:03.31#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.203.08:17:03.31#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.203.08:17:03.31#ibcon#ireg 7 cls_cnt 0 2006.203.08:17:03.31#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.203.08:17:03.43#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.203.08:17:03.43#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.203.08:17:03.43#ibcon#enter wrdev, iclass 3, count 0 2006.203.08:17:03.43#ibcon#first serial, iclass 3, count 0 2006.203.08:17:03.43#ibcon#enter sib2, iclass 3, count 0 2006.203.08:17:03.43#ibcon#flushed, iclass 3, count 0 2006.203.08:17:03.43#ibcon#about to write, iclass 3, count 0 2006.203.08:17:03.43#ibcon#wrote, iclass 3, count 0 2006.203.08:17:03.43#ibcon#about to read 3, iclass 3, count 0 2006.203.08:17:03.45#ibcon#read 3, iclass 3, count 0 2006.203.08:17:03.45#ibcon#about to read 4, iclass 3, count 0 2006.203.08:17:03.45#ibcon#read 4, iclass 3, count 0 2006.203.08:17:03.45#ibcon#about to read 5, iclass 3, count 0 2006.203.08:17:03.45#ibcon#read 5, iclass 3, count 0 2006.203.08:17:03.45#ibcon#about to read 6, iclass 3, count 0 2006.203.08:17:03.45#ibcon#read 6, iclass 3, count 0 2006.203.08:17:03.45#ibcon#end of sib2, iclass 3, count 0 2006.203.08:17:03.45#ibcon#*mode == 0, iclass 3, count 0 2006.203.08:17:03.45#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.203.08:17:03.45#ibcon#[27=USB\r\n] 2006.203.08:17:03.45#ibcon#*before write, iclass 3, count 0 2006.203.08:17:03.45#ibcon#enter sib2, iclass 3, count 0 2006.203.08:17:03.45#ibcon#flushed, iclass 3, count 0 2006.203.08:17:03.45#ibcon#about to write, iclass 3, count 0 2006.203.08:17:03.45#ibcon#wrote, iclass 3, count 0 2006.203.08:17:03.45#ibcon#about to read 3, iclass 3, count 0 2006.203.08:17:03.48#ibcon#read 3, iclass 3, count 0 2006.203.08:17:03.48#ibcon#about to read 4, iclass 3, count 0 2006.203.08:17:03.48#ibcon#read 4, iclass 3, count 0 2006.203.08:17:03.48#ibcon#about to read 5, iclass 3, count 0 2006.203.08:17:03.48#ibcon#read 5, iclass 3, count 0 2006.203.08:17:03.48#ibcon#about to read 6, iclass 3, count 0 2006.203.08:17:03.48#ibcon#read 6, iclass 3, count 0 2006.203.08:17:03.48#ibcon#end of sib2, iclass 3, count 0 2006.203.08:17:03.48#ibcon#*after write, iclass 3, count 0 2006.203.08:17:03.48#ibcon#*before return 0, iclass 3, count 0 2006.203.08:17:03.48#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.203.08:17:03.48#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.203.08:17:03.48#ibcon#about to clear, iclass 3 cls_cnt 0 2006.203.08:17:03.48#ibcon#cleared, iclass 3 cls_cnt 0 2006.203.08:17:03.48$vc4f8/vblo=6,752.99 2006.203.08:17:03.48#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.203.08:17:03.48#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.203.08:17:03.48#ibcon#ireg 17 cls_cnt 0 2006.203.08:17:03.48#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.203.08:17:03.48#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.203.08:17:03.48#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.203.08:17:03.48#ibcon#enter wrdev, iclass 5, count 0 2006.203.08:17:03.48#ibcon#first serial, iclass 5, count 0 2006.203.08:17:03.48#ibcon#enter sib2, iclass 5, count 0 2006.203.08:17:03.48#ibcon#flushed, iclass 5, count 0 2006.203.08:17:03.48#ibcon#about to write, iclass 5, count 0 2006.203.08:17:03.48#ibcon#wrote, iclass 5, count 0 2006.203.08:17:03.48#ibcon#about to read 3, iclass 5, count 0 2006.203.08:17:03.50#ibcon#read 3, iclass 5, count 0 2006.203.08:17:03.50#ibcon#about to read 4, iclass 5, count 0 2006.203.08:17:03.50#ibcon#read 4, iclass 5, count 0 2006.203.08:17:03.50#ibcon#about to read 5, iclass 5, count 0 2006.203.08:17:03.50#ibcon#read 5, iclass 5, count 0 2006.203.08:17:03.50#ibcon#about to read 6, iclass 5, count 0 2006.203.08:17:03.50#ibcon#read 6, iclass 5, count 0 2006.203.08:17:03.50#ibcon#end of sib2, iclass 5, count 0 2006.203.08:17:03.50#ibcon#*mode == 0, iclass 5, count 0 2006.203.08:17:03.50#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.203.08:17:03.50#ibcon#[28=FRQ=06,752.99\r\n] 2006.203.08:17:03.50#ibcon#*before write, iclass 5, count 0 2006.203.08:17:03.50#ibcon#enter sib2, iclass 5, count 0 2006.203.08:17:03.50#ibcon#flushed, iclass 5, count 0 2006.203.08:17:03.50#ibcon#about to write, iclass 5, count 0 2006.203.08:17:03.50#ibcon#wrote, iclass 5, count 0 2006.203.08:17:03.50#ibcon#about to read 3, iclass 5, count 0 2006.203.08:17:03.54#ibcon#read 3, iclass 5, count 0 2006.203.08:17:03.54#ibcon#about to read 4, iclass 5, count 0 2006.203.08:17:03.54#ibcon#read 4, iclass 5, count 0 2006.203.08:17:03.54#ibcon#about to read 5, iclass 5, count 0 2006.203.08:17:03.54#ibcon#read 5, iclass 5, count 0 2006.203.08:17:03.54#ibcon#about to read 6, iclass 5, count 0 2006.203.08:17:03.54#ibcon#read 6, iclass 5, count 0 2006.203.08:17:03.54#ibcon#end of sib2, iclass 5, count 0 2006.203.08:17:03.54#ibcon#*after write, iclass 5, count 0 2006.203.08:17:03.54#ibcon#*before return 0, iclass 5, count 0 2006.203.08:17:03.54#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.203.08:17:03.54#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.203.08:17:03.54#ibcon#about to clear, iclass 5 cls_cnt 0 2006.203.08:17:03.54#ibcon#cleared, iclass 5 cls_cnt 0 2006.203.08:17:03.54$vc4f8/vb=6,4 2006.203.08:17:03.54#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.203.08:17:03.54#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.203.08:17:03.54#ibcon#ireg 11 cls_cnt 2 2006.203.08:17:03.54#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.203.08:17:03.61#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.203.08:17:03.61#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.203.08:17:03.61#ibcon#enter wrdev, iclass 7, count 2 2006.203.08:17:03.61#ibcon#first serial, iclass 7, count 2 2006.203.08:17:03.61#ibcon#enter sib2, iclass 7, count 2 2006.203.08:17:03.61#ibcon#flushed, iclass 7, count 2 2006.203.08:17:03.61#ibcon#about to write, iclass 7, count 2 2006.203.08:17:03.61#ibcon#wrote, iclass 7, count 2 2006.203.08:17:03.61#ibcon#about to read 3, iclass 7, count 2 2006.203.08:17:03.63#ibcon#read 3, iclass 7, count 2 2006.203.08:17:03.63#ibcon#about to read 4, iclass 7, count 2 2006.203.08:17:03.63#ibcon#read 4, iclass 7, count 2 2006.203.08:17:03.63#ibcon#about to read 5, iclass 7, count 2 2006.203.08:17:03.63#ibcon#read 5, iclass 7, count 2 2006.203.08:17:03.63#ibcon#about to read 6, iclass 7, count 2 2006.203.08:17:03.63#ibcon#read 6, iclass 7, count 2 2006.203.08:17:03.63#ibcon#end of sib2, iclass 7, count 2 2006.203.08:17:03.63#ibcon#*mode == 0, iclass 7, count 2 2006.203.08:17:03.63#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.203.08:17:03.63#ibcon#[27=AT06-04\r\n] 2006.203.08:17:03.63#ibcon#*before write, iclass 7, count 2 2006.203.08:17:03.63#ibcon#enter sib2, iclass 7, count 2 2006.203.08:17:03.63#ibcon#flushed, iclass 7, count 2 2006.203.08:17:03.63#ibcon#about to write, iclass 7, count 2 2006.203.08:17:03.63#ibcon#wrote, iclass 7, count 2 2006.203.08:17:03.63#ibcon#about to read 3, iclass 7, count 2 2006.203.08:17:03.65#ibcon#read 3, iclass 7, count 2 2006.203.08:17:03.65#ibcon#about to read 4, iclass 7, count 2 2006.203.08:17:03.65#ibcon#read 4, iclass 7, count 2 2006.203.08:17:03.65#ibcon#about to read 5, iclass 7, count 2 2006.203.08:17:03.65#ibcon#read 5, iclass 7, count 2 2006.203.08:17:03.65#ibcon#about to read 6, iclass 7, count 2 2006.203.08:17:03.65#ibcon#read 6, iclass 7, count 2 2006.203.08:17:03.65#ibcon#end of sib2, iclass 7, count 2 2006.203.08:17:03.65#ibcon#*after write, iclass 7, count 2 2006.203.08:17:03.65#ibcon#*before return 0, iclass 7, count 2 2006.203.08:17:03.65#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.203.08:17:03.65#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.203.08:17:03.65#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.203.08:17:03.65#ibcon#ireg 7 cls_cnt 0 2006.203.08:17:03.65#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.203.08:17:03.77#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.203.08:17:03.77#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.203.08:17:03.77#ibcon#enter wrdev, iclass 7, count 0 2006.203.08:17:03.77#ibcon#first serial, iclass 7, count 0 2006.203.08:17:03.77#ibcon#enter sib2, iclass 7, count 0 2006.203.08:17:03.77#ibcon#flushed, iclass 7, count 0 2006.203.08:17:03.77#ibcon#about to write, iclass 7, count 0 2006.203.08:17:03.77#ibcon#wrote, iclass 7, count 0 2006.203.08:17:03.77#ibcon#about to read 3, iclass 7, count 0 2006.203.08:17:03.79#ibcon#read 3, iclass 7, count 0 2006.203.08:17:03.79#ibcon#about to read 4, iclass 7, count 0 2006.203.08:17:03.79#ibcon#read 4, iclass 7, count 0 2006.203.08:17:03.79#ibcon#about to read 5, iclass 7, count 0 2006.203.08:17:03.79#ibcon#read 5, iclass 7, count 0 2006.203.08:17:03.79#ibcon#about to read 6, iclass 7, count 0 2006.203.08:17:03.79#ibcon#read 6, iclass 7, count 0 2006.203.08:17:03.79#ibcon#end of sib2, iclass 7, count 0 2006.203.08:17:03.79#ibcon#*mode == 0, iclass 7, count 0 2006.203.08:17:03.79#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.203.08:17:03.79#ibcon#[27=USB\r\n] 2006.203.08:17:03.79#ibcon#*before write, iclass 7, count 0 2006.203.08:17:03.79#ibcon#enter sib2, iclass 7, count 0 2006.203.08:17:03.79#ibcon#flushed, iclass 7, count 0 2006.203.08:17:03.79#ibcon#about to write, iclass 7, count 0 2006.203.08:17:03.79#ibcon#wrote, iclass 7, count 0 2006.203.08:17:03.79#ibcon#about to read 3, iclass 7, count 0 2006.203.08:17:03.82#ibcon#read 3, iclass 7, count 0 2006.203.08:17:03.82#ibcon#about to read 4, iclass 7, count 0 2006.203.08:17:03.82#ibcon#read 4, iclass 7, count 0 2006.203.08:17:03.82#ibcon#about to read 5, iclass 7, count 0 2006.203.08:17:03.82#ibcon#read 5, iclass 7, count 0 2006.203.08:17:03.82#ibcon#about to read 6, iclass 7, count 0 2006.203.08:17:03.82#ibcon#read 6, iclass 7, count 0 2006.203.08:17:03.82#ibcon#end of sib2, iclass 7, count 0 2006.203.08:17:03.82#ibcon#*after write, iclass 7, count 0 2006.203.08:17:03.82#ibcon#*before return 0, iclass 7, count 0 2006.203.08:17:03.82#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.203.08:17:03.82#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.203.08:17:03.82#ibcon#about to clear, iclass 7 cls_cnt 0 2006.203.08:17:03.82#ibcon#cleared, iclass 7 cls_cnt 0 2006.203.08:17:03.82$vc4f8/vabw=wide 2006.203.08:17:03.82#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.203.08:17:03.82#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.203.08:17:03.82#ibcon#ireg 8 cls_cnt 0 2006.203.08:17:03.82#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.203.08:17:03.82#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.203.08:17:03.82#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.203.08:17:03.82#ibcon#enter wrdev, iclass 11, count 0 2006.203.08:17:03.82#ibcon#first serial, iclass 11, count 0 2006.203.08:17:03.82#ibcon#enter sib2, iclass 11, count 0 2006.203.08:17:03.82#ibcon#flushed, iclass 11, count 0 2006.203.08:17:03.82#ibcon#about to write, iclass 11, count 0 2006.203.08:17:03.82#ibcon#wrote, iclass 11, count 0 2006.203.08:17:03.82#ibcon#about to read 3, iclass 11, count 0 2006.203.08:17:03.84#ibcon#read 3, iclass 11, count 0 2006.203.08:17:03.84#ibcon#about to read 4, iclass 11, count 0 2006.203.08:17:03.84#ibcon#read 4, iclass 11, count 0 2006.203.08:17:03.84#ibcon#about to read 5, iclass 11, count 0 2006.203.08:17:03.84#ibcon#read 5, iclass 11, count 0 2006.203.08:17:03.84#ibcon#about to read 6, iclass 11, count 0 2006.203.08:17:03.84#ibcon#read 6, iclass 11, count 0 2006.203.08:17:03.84#ibcon#end of sib2, iclass 11, count 0 2006.203.08:17:03.84#ibcon#*mode == 0, iclass 11, count 0 2006.203.08:17:03.84#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.203.08:17:03.84#ibcon#[25=BW32\r\n] 2006.203.08:17:03.84#ibcon#*before write, iclass 11, count 0 2006.203.08:17:03.84#ibcon#enter sib2, iclass 11, count 0 2006.203.08:17:03.84#ibcon#flushed, iclass 11, count 0 2006.203.08:17:03.84#ibcon#about to write, iclass 11, count 0 2006.203.08:17:03.84#ibcon#wrote, iclass 11, count 0 2006.203.08:17:03.84#ibcon#about to read 3, iclass 11, count 0 2006.203.08:17:03.87#ibcon#read 3, iclass 11, count 0 2006.203.08:17:03.87#ibcon#about to read 4, iclass 11, count 0 2006.203.08:17:03.87#ibcon#read 4, iclass 11, count 0 2006.203.08:17:03.87#ibcon#about to read 5, iclass 11, count 0 2006.203.08:17:03.87#ibcon#read 5, iclass 11, count 0 2006.203.08:17:03.87#ibcon#about to read 6, iclass 11, count 0 2006.203.08:17:03.87#ibcon#read 6, iclass 11, count 0 2006.203.08:17:03.87#ibcon#end of sib2, iclass 11, count 0 2006.203.08:17:03.87#ibcon#*after write, iclass 11, count 0 2006.203.08:17:03.87#ibcon#*before return 0, iclass 11, count 0 2006.203.08:17:03.87#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.203.08:17:03.87#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.203.08:17:03.87#ibcon#about to clear, iclass 11 cls_cnt 0 2006.203.08:17:03.87#ibcon#cleared, iclass 11 cls_cnt 0 2006.203.08:17:03.87$vc4f8/vbbw=wide 2006.203.08:17:03.87#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.203.08:17:03.87#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.203.08:17:03.87#ibcon#ireg 8 cls_cnt 0 2006.203.08:17:03.87#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.203.08:17:03.94#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.203.08:17:03.94#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.203.08:17:03.94#ibcon#enter wrdev, iclass 13, count 0 2006.203.08:17:03.94#ibcon#first serial, iclass 13, count 0 2006.203.08:17:03.94#ibcon#enter sib2, iclass 13, count 0 2006.203.08:17:03.94#ibcon#flushed, iclass 13, count 0 2006.203.08:17:03.94#ibcon#about to write, iclass 13, count 0 2006.203.08:17:03.94#ibcon#wrote, iclass 13, count 0 2006.203.08:17:03.94#ibcon#about to read 3, iclass 13, count 0 2006.203.08:17:03.96#ibcon#read 3, iclass 13, count 0 2006.203.08:17:03.96#ibcon#about to read 4, iclass 13, count 0 2006.203.08:17:03.96#ibcon#read 4, iclass 13, count 0 2006.203.08:17:03.96#ibcon#about to read 5, iclass 13, count 0 2006.203.08:17:03.96#ibcon#read 5, iclass 13, count 0 2006.203.08:17:03.96#ibcon#about to read 6, iclass 13, count 0 2006.203.08:17:03.96#ibcon#read 6, iclass 13, count 0 2006.203.08:17:03.96#ibcon#end of sib2, iclass 13, count 0 2006.203.08:17:03.96#ibcon#*mode == 0, iclass 13, count 0 2006.203.08:17:03.96#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.203.08:17:03.96#ibcon#[27=BW32\r\n] 2006.203.08:17:03.96#ibcon#*before write, iclass 13, count 0 2006.203.08:17:03.96#ibcon#enter sib2, iclass 13, count 0 2006.203.08:17:03.96#ibcon#flushed, iclass 13, count 0 2006.203.08:17:03.96#ibcon#about to write, iclass 13, count 0 2006.203.08:17:03.96#ibcon#wrote, iclass 13, count 0 2006.203.08:17:03.96#ibcon#about to read 3, iclass 13, count 0 2006.203.08:17:03.99#ibcon#read 3, iclass 13, count 0 2006.203.08:17:03.99#ibcon#about to read 4, iclass 13, count 0 2006.203.08:17:03.99#ibcon#read 4, iclass 13, count 0 2006.203.08:17:03.99#ibcon#about to read 5, iclass 13, count 0 2006.203.08:17:03.99#ibcon#read 5, iclass 13, count 0 2006.203.08:17:03.99#ibcon#about to read 6, iclass 13, count 0 2006.203.08:17:03.99#ibcon#read 6, iclass 13, count 0 2006.203.08:17:03.99#ibcon#end of sib2, iclass 13, count 0 2006.203.08:17:03.99#ibcon#*after write, iclass 13, count 0 2006.203.08:17:03.99#ibcon#*before return 0, iclass 13, count 0 2006.203.08:17:03.99#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.203.08:17:03.99#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.203.08:17:03.99#ibcon#about to clear, iclass 13 cls_cnt 0 2006.203.08:17:03.99#ibcon#cleared, iclass 13 cls_cnt 0 2006.203.08:17:03.99$4f8m12a/ifd4f 2006.203.08:17:03.99$ifd4f/lo= 2006.203.08:17:03.99$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.203.08:17:03.99$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.203.08:17:03.99$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.203.08:17:03.99$ifd4f/patch= 2006.203.08:17:03.99$ifd4f/patch=lo1,a1,a2,a3,a4 2006.203.08:17:04.00$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.203.08:17:04.00$ifd4f/patch=lo3,a5,a6,a7,a8 2006.203.08:17:04.00$4f8m12a/"form=m,16.000,1:2 2006.203.08:17:04.00$4f8m12a/"tpicd 2006.203.08:17:04.00$4f8m12a/echo=off 2006.203.08:17:04.00$4f8m12a/xlog=off 2006.203.08:17:04.00:!2006.203.08:17:30 2006.203.08:17:13.14#trakl#Source acquired 2006.203.08:17:15.14#flagr#flagr/antenna,acquired 2006.203.08:17:30.01:preob 2006.203.08:17:31.14/onsource/TRACKING 2006.203.08:17:31.14:!2006.203.08:17:40 2006.203.08:17:40.00:data_valid=on 2006.203.08:17:40.00:midob 2006.203.08:17:40.14/onsource/TRACKING 2006.203.08:17:40.14/wx/23.56,1001.1,100 2006.203.08:17:40.25/cable/+6.4603E-03 2006.203.08:17:41.34/va/01,08,usb,yes,28,29 2006.203.08:17:41.34/va/02,07,usb,yes,28,29 2006.203.08:17:41.34/va/03,08,usb,yes,21,21 2006.203.08:17:41.34/va/04,07,usb,yes,29,31 2006.203.08:17:41.34/va/05,07,usb,yes,31,33 2006.203.08:17:41.34/va/06,06,usb,yes,30,30 2006.203.08:17:41.34/va/07,07,usb,yes,27,27 2006.203.08:17:41.34/va/08,06,usb,yes,33,32 2006.203.08:17:41.57/valo/01,532.99,yes,locked 2006.203.08:17:41.57/valo/02,572.99,yes,locked 2006.203.08:17:41.57/valo/03,672.99,yes,locked 2006.203.08:17:41.57/valo/04,832.99,yes,locked 2006.203.08:17:41.57/valo/05,652.99,yes,locked 2006.203.08:17:41.57/valo/06,772.99,yes,locked 2006.203.08:17:41.57/valo/07,832.99,yes,locked 2006.203.08:17:41.57/valo/08,852.99,yes,locked 2006.203.08:17:42.66/vb/01,04,usb,yes,28,27 2006.203.08:17:42.66/vb/02,04,usb,yes,30,31 2006.203.08:17:42.66/vb/03,04,usb,yes,26,30 2006.203.08:17:42.66/vb/04,04,usb,yes,27,27 2006.203.08:17:42.66/vb/05,03,usb,yes,32,36 2006.203.08:17:42.66/vb/06,04,usb,yes,26,29 2006.203.08:17:42.66/vb/07,04,usb,yes,28,28 2006.203.08:17:42.66/vb/08,04,usb,yes,26,29 2006.203.08:17:42.89/vblo/01,632.99,yes,locked 2006.203.08:17:42.89/vblo/02,640.99,yes,locked 2006.203.08:17:42.89/vblo/03,656.99,yes,locked 2006.203.08:17:42.89/vblo/04,712.99,yes,locked 2006.203.08:17:42.89/vblo/05,744.99,yes,locked 2006.203.08:17:42.89/vblo/06,752.99,yes,locked 2006.203.08:17:42.89/vblo/07,734.99,yes,locked 2006.203.08:17:42.89/vblo/08,744.99,yes,locked 2006.203.08:17:43.04/vabw/8 2006.203.08:17:43.19/vbbw/8 2006.203.08:17:43.28/xfe/off,on,12.5 2006.203.08:17:43.66/ifatt/23,28,28,28 2006.203.08:17:44.07/fmout-gps/S +4.59E-07 2006.203.08:17:44.12:!2006.203.08:18:40 2006.203.08:18:40.01:data_valid=off 2006.203.08:18:40.01:postob 2006.203.08:18:40.21/cable/+6.4608E-03 2006.203.08:18:40.21/wx/23.56,1001.1,100 2006.203.08:18:41.07/fmout-gps/S +4.58E-07 2006.203.08:18:41.07:scan_name=203-0820,k06203,60 2006.203.08:18:41.07:source=3c418,203837.03,511912.7,2000.0,cw 2006.203.08:18:41.14#flagr#flagr/antenna,new-source 2006.203.08:18:42.14:checkk5 2006.203.08:18:42.56/chk_autoobs//k5ts1/ autoobs is running! 2006.203.08:18:43.02/chk_autoobs//k5ts2/ autoobs is running! 2006.203.08:18:43.45/chk_autoobs//k5ts3/ autoobs is running! 2006.203.08:18:43.90/chk_autoobs//k5ts4/ autoobs is running! 2006.203.08:18:44.53/chk_obsdata//k5ts1/T2030817??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.08:18:44.93/chk_obsdata//k5ts2/T2030817??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.08:18:45.34/chk_obsdata//k5ts3/T2030817??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.08:18:45.78/chk_obsdata//k5ts4/T2030817??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.08:18:46.56/k5log//k5ts1_log_newline 2006.203.08:18:47.28/k5log//k5ts2_log_newline 2006.203.08:18:48.04/k5log//k5ts3_log_newline 2006.203.08:18:49.11/k5log//k5ts4_log_newline 2006.203.08:18:49.14/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.203.08:18:49.14:4f8m12a=3 2006.203.08:18:49.14$4f8m12a/echo=on 2006.203.08:18:49.14$4f8m12a/pcalon 2006.203.08:18:49.14$pcalon/"no phase cal control is implemented here 2006.203.08:18:49.14$4f8m12a/"tpicd=stop 2006.203.08:18:49.14$4f8m12a/vc4f8 2006.203.08:18:49.14$vc4f8/valo=1,532.99 2006.203.08:18:49.14#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.203.08:18:49.14#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.203.08:18:49.14#ibcon#ireg 17 cls_cnt 0 2006.203.08:18:49.14#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.203.08:18:49.14#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.203.08:18:49.14#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.203.08:18:49.14#ibcon#enter wrdev, iclass 20, count 0 2006.203.08:18:49.14#ibcon#first serial, iclass 20, count 0 2006.203.08:18:49.14#ibcon#enter sib2, iclass 20, count 0 2006.203.08:18:49.14#ibcon#flushed, iclass 20, count 0 2006.203.08:18:49.14#ibcon#about to write, iclass 20, count 0 2006.203.08:18:49.14#ibcon#wrote, iclass 20, count 0 2006.203.08:18:49.14#ibcon#about to read 3, iclass 20, count 0 2006.203.08:18:49.18#ibcon#read 3, iclass 20, count 0 2006.203.08:18:49.18#ibcon#about to read 4, iclass 20, count 0 2006.203.08:18:49.18#ibcon#read 4, iclass 20, count 0 2006.203.08:18:49.18#ibcon#about to read 5, iclass 20, count 0 2006.203.08:18:49.18#ibcon#read 5, iclass 20, count 0 2006.203.08:18:49.18#ibcon#about to read 6, iclass 20, count 0 2006.203.08:18:49.18#ibcon#read 6, iclass 20, count 0 2006.203.08:18:49.18#ibcon#end of sib2, iclass 20, count 0 2006.203.08:18:49.18#ibcon#*mode == 0, iclass 20, count 0 2006.203.08:18:49.18#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.203.08:18:49.18#ibcon#[26=FRQ=01,532.99\r\n] 2006.203.08:18:49.18#ibcon#*before write, iclass 20, count 0 2006.203.08:18:49.18#ibcon#enter sib2, iclass 20, count 0 2006.203.08:18:49.18#ibcon#flushed, iclass 20, count 0 2006.203.08:18:49.18#ibcon#about to write, iclass 20, count 0 2006.203.08:18:49.18#ibcon#wrote, iclass 20, count 0 2006.203.08:18:49.18#ibcon#about to read 3, iclass 20, count 0 2006.203.08:18:49.23#ibcon#read 3, iclass 20, count 0 2006.203.08:18:49.23#ibcon#about to read 4, iclass 20, count 0 2006.203.08:18:49.23#ibcon#read 4, iclass 20, count 0 2006.203.08:18:49.23#ibcon#about to read 5, iclass 20, count 0 2006.203.08:18:49.23#ibcon#read 5, iclass 20, count 0 2006.203.08:18:49.23#ibcon#about to read 6, iclass 20, count 0 2006.203.08:18:49.23#ibcon#read 6, iclass 20, count 0 2006.203.08:18:49.23#ibcon#end of sib2, iclass 20, count 0 2006.203.08:18:49.23#ibcon#*after write, iclass 20, count 0 2006.203.08:18:49.23#ibcon#*before return 0, iclass 20, count 0 2006.203.08:18:49.23#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.203.08:18:49.23#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.203.08:18:49.23#ibcon#about to clear, iclass 20 cls_cnt 0 2006.203.08:18:49.23#ibcon#cleared, iclass 20 cls_cnt 0 2006.203.08:18:49.23$vc4f8/va=1,8 2006.203.08:18:49.23#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.203.08:18:49.23#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.203.08:18:49.23#ibcon#ireg 11 cls_cnt 2 2006.203.08:18:49.23#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.203.08:18:49.23#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.203.08:18:49.23#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.203.08:18:49.23#ibcon#enter wrdev, iclass 22, count 2 2006.203.08:18:49.23#ibcon#first serial, iclass 22, count 2 2006.203.08:18:49.23#ibcon#enter sib2, iclass 22, count 2 2006.203.08:18:49.23#ibcon#flushed, iclass 22, count 2 2006.203.08:18:49.23#ibcon#about to write, iclass 22, count 2 2006.203.08:18:49.23#ibcon#wrote, iclass 22, count 2 2006.203.08:18:49.23#ibcon#about to read 3, iclass 22, count 2 2006.203.08:18:49.26#ibcon#read 3, iclass 22, count 2 2006.203.08:18:49.26#ibcon#about to read 4, iclass 22, count 2 2006.203.08:18:49.26#ibcon#read 4, iclass 22, count 2 2006.203.08:18:49.26#ibcon#about to read 5, iclass 22, count 2 2006.203.08:18:49.26#ibcon#read 5, iclass 22, count 2 2006.203.08:18:49.26#ibcon#about to read 6, iclass 22, count 2 2006.203.08:18:49.26#ibcon#read 6, iclass 22, count 2 2006.203.08:18:49.26#ibcon#end of sib2, iclass 22, count 2 2006.203.08:18:49.26#ibcon#*mode == 0, iclass 22, count 2 2006.203.08:18:49.26#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.203.08:18:49.26#ibcon#[25=AT01-08\r\n] 2006.203.08:18:49.26#ibcon#*before write, iclass 22, count 2 2006.203.08:18:49.26#ibcon#enter sib2, iclass 22, count 2 2006.203.08:18:49.26#ibcon#flushed, iclass 22, count 2 2006.203.08:18:49.26#ibcon#about to write, iclass 22, count 2 2006.203.08:18:49.26#ibcon#wrote, iclass 22, count 2 2006.203.08:18:49.26#ibcon#about to read 3, iclass 22, count 2 2006.203.08:18:49.29#ibcon#read 3, iclass 22, count 2 2006.203.08:18:49.29#ibcon#about to read 4, iclass 22, count 2 2006.203.08:18:49.29#ibcon#read 4, iclass 22, count 2 2006.203.08:18:49.29#ibcon#about to read 5, iclass 22, count 2 2006.203.08:18:49.29#ibcon#read 5, iclass 22, count 2 2006.203.08:18:49.29#ibcon#about to read 6, iclass 22, count 2 2006.203.08:18:49.29#ibcon#read 6, iclass 22, count 2 2006.203.08:18:49.29#ibcon#end of sib2, iclass 22, count 2 2006.203.08:18:49.29#ibcon#*after write, iclass 22, count 2 2006.203.08:18:49.29#ibcon#*before return 0, iclass 22, count 2 2006.203.08:18:49.29#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.203.08:18:49.29#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.203.08:18:49.29#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.203.08:18:49.29#ibcon#ireg 7 cls_cnt 0 2006.203.08:18:49.29#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.203.08:18:49.41#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.203.08:18:49.41#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.203.08:18:49.41#ibcon#enter wrdev, iclass 22, count 0 2006.203.08:18:49.41#ibcon#first serial, iclass 22, count 0 2006.203.08:18:49.41#ibcon#enter sib2, iclass 22, count 0 2006.203.08:18:49.41#ibcon#flushed, iclass 22, count 0 2006.203.08:18:49.41#ibcon#about to write, iclass 22, count 0 2006.203.08:18:49.41#ibcon#wrote, iclass 22, count 0 2006.203.08:18:49.41#ibcon#about to read 3, iclass 22, count 0 2006.203.08:18:49.43#ibcon#read 3, iclass 22, count 0 2006.203.08:18:49.43#ibcon#about to read 4, iclass 22, count 0 2006.203.08:18:49.43#ibcon#read 4, iclass 22, count 0 2006.203.08:18:49.43#ibcon#about to read 5, iclass 22, count 0 2006.203.08:18:49.43#ibcon#read 5, iclass 22, count 0 2006.203.08:18:49.43#ibcon#about to read 6, iclass 22, count 0 2006.203.08:18:49.43#ibcon#read 6, iclass 22, count 0 2006.203.08:18:49.43#ibcon#end of sib2, iclass 22, count 0 2006.203.08:18:49.43#ibcon#*mode == 0, iclass 22, count 0 2006.203.08:18:49.43#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.203.08:18:49.43#ibcon#[25=USB\r\n] 2006.203.08:18:49.43#ibcon#*before write, iclass 22, count 0 2006.203.08:18:49.43#ibcon#enter sib2, iclass 22, count 0 2006.203.08:18:49.43#ibcon#flushed, iclass 22, count 0 2006.203.08:18:49.43#ibcon#about to write, iclass 22, count 0 2006.203.08:18:49.43#ibcon#wrote, iclass 22, count 0 2006.203.08:18:49.43#ibcon#about to read 3, iclass 22, count 0 2006.203.08:18:49.46#ibcon#read 3, iclass 22, count 0 2006.203.08:18:49.46#ibcon#about to read 4, iclass 22, count 0 2006.203.08:18:49.46#ibcon#read 4, iclass 22, count 0 2006.203.08:18:49.46#ibcon#about to read 5, iclass 22, count 0 2006.203.08:18:49.46#ibcon#read 5, iclass 22, count 0 2006.203.08:18:49.46#ibcon#about to read 6, iclass 22, count 0 2006.203.08:18:49.46#ibcon#read 6, iclass 22, count 0 2006.203.08:18:49.46#ibcon#end of sib2, iclass 22, count 0 2006.203.08:18:49.46#ibcon#*after write, iclass 22, count 0 2006.203.08:18:49.46#ibcon#*before return 0, iclass 22, count 0 2006.203.08:18:49.46#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.203.08:18:49.46#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.203.08:18:49.46#ibcon#about to clear, iclass 22 cls_cnt 0 2006.203.08:18:49.46#ibcon#cleared, iclass 22 cls_cnt 0 2006.203.08:18:49.46$vc4f8/valo=2,572.99 2006.203.08:18:49.46#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.203.08:18:49.46#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.203.08:18:49.46#ibcon#ireg 17 cls_cnt 0 2006.203.08:18:49.46#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.203.08:18:49.46#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.203.08:18:49.46#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.203.08:18:49.46#ibcon#enter wrdev, iclass 24, count 0 2006.203.08:18:49.46#ibcon#first serial, iclass 24, count 0 2006.203.08:18:49.46#ibcon#enter sib2, iclass 24, count 0 2006.203.08:18:49.46#ibcon#flushed, iclass 24, count 0 2006.203.08:18:49.46#ibcon#about to write, iclass 24, count 0 2006.203.08:18:49.46#ibcon#wrote, iclass 24, count 0 2006.203.08:18:49.46#ibcon#about to read 3, iclass 24, count 0 2006.203.08:18:49.49#ibcon#read 3, iclass 24, count 0 2006.203.08:18:49.49#ibcon#about to read 4, iclass 24, count 0 2006.203.08:18:49.49#ibcon#read 4, iclass 24, count 0 2006.203.08:18:49.49#ibcon#about to read 5, iclass 24, count 0 2006.203.08:18:49.49#ibcon#read 5, iclass 24, count 0 2006.203.08:18:49.49#ibcon#about to read 6, iclass 24, count 0 2006.203.08:18:49.49#ibcon#read 6, iclass 24, count 0 2006.203.08:18:49.49#ibcon#end of sib2, iclass 24, count 0 2006.203.08:18:49.49#ibcon#*mode == 0, iclass 24, count 0 2006.203.08:18:49.49#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.203.08:18:49.49#ibcon#[26=FRQ=02,572.99\r\n] 2006.203.08:18:49.49#ibcon#*before write, iclass 24, count 0 2006.203.08:18:49.49#ibcon#enter sib2, iclass 24, count 0 2006.203.08:18:49.49#ibcon#flushed, iclass 24, count 0 2006.203.08:18:49.49#ibcon#about to write, iclass 24, count 0 2006.203.08:18:49.49#ibcon#wrote, iclass 24, count 0 2006.203.08:18:49.49#ibcon#about to read 3, iclass 24, count 0 2006.203.08:18:49.53#ibcon#read 3, iclass 24, count 0 2006.203.08:18:49.53#ibcon#about to read 4, iclass 24, count 0 2006.203.08:18:49.53#ibcon#read 4, iclass 24, count 0 2006.203.08:18:49.53#ibcon#about to read 5, iclass 24, count 0 2006.203.08:18:49.53#ibcon#read 5, iclass 24, count 0 2006.203.08:18:49.53#ibcon#about to read 6, iclass 24, count 0 2006.203.08:18:49.53#ibcon#read 6, iclass 24, count 0 2006.203.08:18:49.53#ibcon#end of sib2, iclass 24, count 0 2006.203.08:18:49.53#ibcon#*after write, iclass 24, count 0 2006.203.08:18:49.53#ibcon#*before return 0, iclass 24, count 0 2006.203.08:18:49.53#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.203.08:18:49.53#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.203.08:18:49.53#ibcon#about to clear, iclass 24 cls_cnt 0 2006.203.08:18:49.53#ibcon#cleared, iclass 24 cls_cnt 0 2006.203.08:18:49.53$vc4f8/va=2,7 2006.203.08:18:49.53#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.203.08:18:49.53#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.203.08:18:49.53#ibcon#ireg 11 cls_cnt 2 2006.203.08:18:49.53#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.203.08:18:49.59#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.203.08:18:49.59#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.203.08:18:49.59#ibcon#enter wrdev, iclass 26, count 2 2006.203.08:18:49.59#ibcon#first serial, iclass 26, count 2 2006.203.08:18:49.59#ibcon#enter sib2, iclass 26, count 2 2006.203.08:18:49.59#ibcon#flushed, iclass 26, count 2 2006.203.08:18:49.59#ibcon#about to write, iclass 26, count 2 2006.203.08:18:49.59#ibcon#wrote, iclass 26, count 2 2006.203.08:18:49.59#ibcon#about to read 3, iclass 26, count 2 2006.203.08:18:49.60#ibcon#read 3, iclass 26, count 2 2006.203.08:18:49.60#ibcon#about to read 4, iclass 26, count 2 2006.203.08:18:49.60#ibcon#read 4, iclass 26, count 2 2006.203.08:18:49.60#ibcon#about to read 5, iclass 26, count 2 2006.203.08:18:49.60#ibcon#read 5, iclass 26, count 2 2006.203.08:18:49.60#ibcon#about to read 6, iclass 26, count 2 2006.203.08:18:49.60#ibcon#read 6, iclass 26, count 2 2006.203.08:18:49.60#ibcon#end of sib2, iclass 26, count 2 2006.203.08:18:49.60#ibcon#*mode == 0, iclass 26, count 2 2006.203.08:18:49.60#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.203.08:18:49.60#ibcon#[25=AT02-07\r\n] 2006.203.08:18:49.60#ibcon#*before write, iclass 26, count 2 2006.203.08:18:49.60#ibcon#enter sib2, iclass 26, count 2 2006.203.08:18:49.60#ibcon#flushed, iclass 26, count 2 2006.203.08:18:49.60#ibcon#about to write, iclass 26, count 2 2006.203.08:18:49.60#ibcon#wrote, iclass 26, count 2 2006.203.08:18:49.60#ibcon#about to read 3, iclass 26, count 2 2006.203.08:18:49.63#ibcon#read 3, iclass 26, count 2 2006.203.08:18:49.63#ibcon#about to read 4, iclass 26, count 2 2006.203.08:18:49.63#ibcon#read 4, iclass 26, count 2 2006.203.08:18:49.63#ibcon#about to read 5, iclass 26, count 2 2006.203.08:18:49.63#ibcon#read 5, iclass 26, count 2 2006.203.08:18:49.63#ibcon#about to read 6, iclass 26, count 2 2006.203.08:18:49.63#ibcon#read 6, iclass 26, count 2 2006.203.08:18:49.63#ibcon#end of sib2, iclass 26, count 2 2006.203.08:18:49.63#ibcon#*after write, iclass 26, count 2 2006.203.08:18:49.63#ibcon#*before return 0, iclass 26, count 2 2006.203.08:18:49.63#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.203.08:18:49.63#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.203.08:18:49.63#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.203.08:18:49.63#ibcon#ireg 7 cls_cnt 0 2006.203.08:18:49.63#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.203.08:18:49.75#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.203.08:18:49.75#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.203.08:18:49.75#ibcon#enter wrdev, iclass 26, count 0 2006.203.08:18:49.75#ibcon#first serial, iclass 26, count 0 2006.203.08:18:49.75#ibcon#enter sib2, iclass 26, count 0 2006.203.08:18:49.75#ibcon#flushed, iclass 26, count 0 2006.203.08:18:49.75#ibcon#about to write, iclass 26, count 0 2006.203.08:18:49.75#ibcon#wrote, iclass 26, count 0 2006.203.08:18:49.75#ibcon#about to read 3, iclass 26, count 0 2006.203.08:18:49.77#ibcon#read 3, iclass 26, count 0 2006.203.08:18:49.77#ibcon#about to read 4, iclass 26, count 0 2006.203.08:18:49.77#ibcon#read 4, iclass 26, count 0 2006.203.08:18:49.77#ibcon#about to read 5, iclass 26, count 0 2006.203.08:18:49.77#ibcon#read 5, iclass 26, count 0 2006.203.08:18:49.77#ibcon#about to read 6, iclass 26, count 0 2006.203.08:18:49.77#ibcon#read 6, iclass 26, count 0 2006.203.08:18:49.77#ibcon#end of sib2, iclass 26, count 0 2006.203.08:18:49.77#ibcon#*mode == 0, iclass 26, count 0 2006.203.08:18:49.77#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.203.08:18:49.77#ibcon#[25=USB\r\n] 2006.203.08:18:49.77#ibcon#*before write, iclass 26, count 0 2006.203.08:18:49.77#ibcon#enter sib2, iclass 26, count 0 2006.203.08:18:49.77#ibcon#flushed, iclass 26, count 0 2006.203.08:18:49.77#ibcon#about to write, iclass 26, count 0 2006.203.08:18:49.77#ibcon#wrote, iclass 26, count 0 2006.203.08:18:49.77#ibcon#about to read 3, iclass 26, count 0 2006.203.08:18:49.80#ibcon#read 3, iclass 26, count 0 2006.203.08:18:49.80#ibcon#about to read 4, iclass 26, count 0 2006.203.08:18:49.80#ibcon#read 4, iclass 26, count 0 2006.203.08:18:49.80#ibcon#about to read 5, iclass 26, count 0 2006.203.08:18:49.80#ibcon#read 5, iclass 26, count 0 2006.203.08:18:49.80#ibcon#about to read 6, iclass 26, count 0 2006.203.08:18:49.80#ibcon#read 6, iclass 26, count 0 2006.203.08:18:49.80#ibcon#end of sib2, iclass 26, count 0 2006.203.08:18:49.80#ibcon#*after write, iclass 26, count 0 2006.203.08:18:49.80#ibcon#*before return 0, iclass 26, count 0 2006.203.08:18:49.80#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.203.08:18:49.80#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.203.08:18:49.80#ibcon#about to clear, iclass 26 cls_cnt 0 2006.203.08:18:49.80#ibcon#cleared, iclass 26 cls_cnt 0 2006.203.08:18:49.80$vc4f8/valo=3,672.99 2006.203.08:18:49.80#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.203.08:18:49.80#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.203.08:18:49.80#ibcon#ireg 17 cls_cnt 0 2006.203.08:18:49.80#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.203.08:18:49.80#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.203.08:18:49.80#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.203.08:18:49.80#ibcon#enter wrdev, iclass 28, count 0 2006.203.08:18:49.80#ibcon#first serial, iclass 28, count 0 2006.203.08:18:49.80#ibcon#enter sib2, iclass 28, count 0 2006.203.08:18:49.80#ibcon#flushed, iclass 28, count 0 2006.203.08:18:49.80#ibcon#about to write, iclass 28, count 0 2006.203.08:18:49.80#ibcon#wrote, iclass 28, count 0 2006.203.08:18:49.80#ibcon#about to read 3, iclass 28, count 0 2006.203.08:18:49.83#ibcon#read 3, iclass 28, count 0 2006.203.08:18:49.83#ibcon#about to read 4, iclass 28, count 0 2006.203.08:18:49.83#ibcon#read 4, iclass 28, count 0 2006.203.08:18:49.83#ibcon#about to read 5, iclass 28, count 0 2006.203.08:18:49.83#ibcon#read 5, iclass 28, count 0 2006.203.08:18:49.83#ibcon#about to read 6, iclass 28, count 0 2006.203.08:18:49.83#ibcon#read 6, iclass 28, count 0 2006.203.08:18:49.83#ibcon#end of sib2, iclass 28, count 0 2006.203.08:18:49.83#ibcon#*mode == 0, iclass 28, count 0 2006.203.08:18:49.83#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.203.08:18:49.83#ibcon#[26=FRQ=03,672.99\r\n] 2006.203.08:18:49.83#ibcon#*before write, iclass 28, count 0 2006.203.08:18:49.83#ibcon#enter sib2, iclass 28, count 0 2006.203.08:18:49.83#ibcon#flushed, iclass 28, count 0 2006.203.08:18:49.83#ibcon#about to write, iclass 28, count 0 2006.203.08:18:49.83#ibcon#wrote, iclass 28, count 0 2006.203.08:18:49.83#ibcon#about to read 3, iclass 28, count 0 2006.203.08:18:49.87#ibcon#read 3, iclass 28, count 0 2006.203.08:18:49.87#ibcon#about to read 4, iclass 28, count 0 2006.203.08:18:49.87#ibcon#read 4, iclass 28, count 0 2006.203.08:18:49.87#ibcon#about to read 5, iclass 28, count 0 2006.203.08:18:49.87#ibcon#read 5, iclass 28, count 0 2006.203.08:18:49.87#ibcon#about to read 6, iclass 28, count 0 2006.203.08:18:49.87#ibcon#read 6, iclass 28, count 0 2006.203.08:18:49.87#ibcon#end of sib2, iclass 28, count 0 2006.203.08:18:49.87#ibcon#*after write, iclass 28, count 0 2006.203.08:18:49.87#ibcon#*before return 0, iclass 28, count 0 2006.203.08:18:49.87#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.203.08:18:49.87#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.203.08:18:49.87#ibcon#about to clear, iclass 28 cls_cnt 0 2006.203.08:18:49.87#ibcon#cleared, iclass 28 cls_cnt 0 2006.203.08:18:49.87$vc4f8/va=3,8 2006.203.08:18:49.87#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.203.08:18:49.87#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.203.08:18:49.87#ibcon#ireg 11 cls_cnt 2 2006.203.08:18:49.87#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.203.08:18:49.93#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.203.08:18:49.93#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.203.08:18:49.93#ibcon#enter wrdev, iclass 30, count 2 2006.203.08:18:49.93#ibcon#first serial, iclass 30, count 2 2006.203.08:18:49.93#ibcon#enter sib2, iclass 30, count 2 2006.203.08:18:49.93#ibcon#flushed, iclass 30, count 2 2006.203.08:18:49.93#ibcon#about to write, iclass 30, count 2 2006.203.08:18:49.93#ibcon#wrote, iclass 30, count 2 2006.203.08:18:49.93#ibcon#about to read 3, iclass 30, count 2 2006.203.08:18:49.94#ibcon#read 3, iclass 30, count 2 2006.203.08:18:49.94#ibcon#about to read 4, iclass 30, count 2 2006.203.08:18:49.94#ibcon#read 4, iclass 30, count 2 2006.203.08:18:49.94#ibcon#about to read 5, iclass 30, count 2 2006.203.08:18:49.94#ibcon#read 5, iclass 30, count 2 2006.203.08:18:49.94#ibcon#about to read 6, iclass 30, count 2 2006.203.08:18:49.94#ibcon#read 6, iclass 30, count 2 2006.203.08:18:49.94#ibcon#end of sib2, iclass 30, count 2 2006.203.08:18:49.94#ibcon#*mode == 0, iclass 30, count 2 2006.203.08:18:49.94#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.203.08:18:49.94#ibcon#[25=AT03-08\r\n] 2006.203.08:18:49.94#ibcon#*before write, iclass 30, count 2 2006.203.08:18:49.94#ibcon#enter sib2, iclass 30, count 2 2006.203.08:18:49.94#ibcon#flushed, iclass 30, count 2 2006.203.08:18:49.94#ibcon#about to write, iclass 30, count 2 2006.203.08:18:49.94#ibcon#wrote, iclass 30, count 2 2006.203.08:18:49.94#ibcon#about to read 3, iclass 30, count 2 2006.203.08:18:49.97#ibcon#read 3, iclass 30, count 2 2006.203.08:18:49.97#ibcon#about to read 4, iclass 30, count 2 2006.203.08:18:49.97#ibcon#read 4, iclass 30, count 2 2006.203.08:18:49.97#ibcon#about to read 5, iclass 30, count 2 2006.203.08:18:49.97#ibcon#read 5, iclass 30, count 2 2006.203.08:18:49.97#ibcon#about to read 6, iclass 30, count 2 2006.203.08:18:49.97#ibcon#read 6, iclass 30, count 2 2006.203.08:18:49.97#ibcon#end of sib2, iclass 30, count 2 2006.203.08:18:49.97#ibcon#*after write, iclass 30, count 2 2006.203.08:18:49.97#ibcon#*before return 0, iclass 30, count 2 2006.203.08:18:49.97#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.203.08:18:49.97#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.203.08:18:49.97#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.203.08:18:49.97#ibcon#ireg 7 cls_cnt 0 2006.203.08:18:49.97#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.203.08:18:50.09#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.203.08:18:50.09#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.203.08:18:50.09#ibcon#enter wrdev, iclass 30, count 0 2006.203.08:18:50.09#ibcon#first serial, iclass 30, count 0 2006.203.08:18:50.09#ibcon#enter sib2, iclass 30, count 0 2006.203.08:18:50.09#ibcon#flushed, iclass 30, count 0 2006.203.08:18:50.09#ibcon#about to write, iclass 30, count 0 2006.203.08:18:50.09#ibcon#wrote, iclass 30, count 0 2006.203.08:18:50.09#ibcon#about to read 3, iclass 30, count 0 2006.203.08:18:50.11#ibcon#read 3, iclass 30, count 0 2006.203.08:18:50.11#ibcon#about to read 4, iclass 30, count 0 2006.203.08:18:50.11#ibcon#read 4, iclass 30, count 0 2006.203.08:18:50.11#ibcon#about to read 5, iclass 30, count 0 2006.203.08:18:50.11#ibcon#read 5, iclass 30, count 0 2006.203.08:18:50.11#ibcon#about to read 6, iclass 30, count 0 2006.203.08:18:50.11#ibcon#read 6, iclass 30, count 0 2006.203.08:18:50.11#ibcon#end of sib2, iclass 30, count 0 2006.203.08:18:50.11#ibcon#*mode == 0, iclass 30, count 0 2006.203.08:18:50.11#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.203.08:18:50.11#ibcon#[25=USB\r\n] 2006.203.08:18:50.11#ibcon#*before write, iclass 30, count 0 2006.203.08:18:50.11#ibcon#enter sib2, iclass 30, count 0 2006.203.08:18:50.11#ibcon#flushed, iclass 30, count 0 2006.203.08:18:50.11#ibcon#about to write, iclass 30, count 0 2006.203.08:18:50.11#ibcon#wrote, iclass 30, count 0 2006.203.08:18:50.11#ibcon#about to read 3, iclass 30, count 0 2006.203.08:18:50.14#ibcon#read 3, iclass 30, count 0 2006.203.08:18:50.14#ibcon#about to read 4, iclass 30, count 0 2006.203.08:18:50.14#ibcon#read 4, iclass 30, count 0 2006.203.08:18:50.14#ibcon#about to read 5, iclass 30, count 0 2006.203.08:18:50.14#ibcon#read 5, iclass 30, count 0 2006.203.08:18:50.14#ibcon#about to read 6, iclass 30, count 0 2006.203.08:18:50.14#ibcon#read 6, iclass 30, count 0 2006.203.08:18:50.14#ibcon#end of sib2, iclass 30, count 0 2006.203.08:18:50.14#ibcon#*after write, iclass 30, count 0 2006.203.08:18:50.14#ibcon#*before return 0, iclass 30, count 0 2006.203.08:18:50.14#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.203.08:18:50.14#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.203.08:18:50.14#ibcon#about to clear, iclass 30 cls_cnt 0 2006.203.08:18:50.14#ibcon#cleared, iclass 30 cls_cnt 0 2006.203.08:18:50.14$vc4f8/valo=4,832.99 2006.203.08:18:50.14#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.203.08:18:50.14#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.203.08:18:50.14#ibcon#ireg 17 cls_cnt 0 2006.203.08:18:50.14#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.203.08:18:50.14#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.203.08:18:50.14#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.203.08:18:50.14#ibcon#enter wrdev, iclass 32, count 0 2006.203.08:18:50.14#ibcon#first serial, iclass 32, count 0 2006.203.08:18:50.14#ibcon#enter sib2, iclass 32, count 0 2006.203.08:18:50.14#ibcon#flushed, iclass 32, count 0 2006.203.08:18:50.14#ibcon#about to write, iclass 32, count 0 2006.203.08:18:50.14#ibcon#wrote, iclass 32, count 0 2006.203.08:18:50.14#ibcon#about to read 3, iclass 32, count 0 2006.203.08:18:50.16#ibcon#read 3, iclass 32, count 0 2006.203.08:18:50.16#ibcon#about to read 4, iclass 32, count 0 2006.203.08:18:50.16#ibcon#read 4, iclass 32, count 0 2006.203.08:18:50.16#ibcon#about to read 5, iclass 32, count 0 2006.203.08:18:50.16#ibcon#read 5, iclass 32, count 0 2006.203.08:18:50.16#ibcon#about to read 6, iclass 32, count 0 2006.203.08:18:50.16#ibcon#read 6, iclass 32, count 0 2006.203.08:18:50.16#ibcon#end of sib2, iclass 32, count 0 2006.203.08:18:50.16#ibcon#*mode == 0, iclass 32, count 0 2006.203.08:18:50.16#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.203.08:18:50.16#ibcon#[26=FRQ=04,832.99\r\n] 2006.203.08:18:50.16#ibcon#*before write, iclass 32, count 0 2006.203.08:18:50.16#ibcon#enter sib2, iclass 32, count 0 2006.203.08:18:50.16#ibcon#flushed, iclass 32, count 0 2006.203.08:18:50.16#ibcon#about to write, iclass 32, count 0 2006.203.08:18:50.16#ibcon#wrote, iclass 32, count 0 2006.203.08:18:50.16#ibcon#about to read 3, iclass 32, count 0 2006.203.08:18:50.20#ibcon#read 3, iclass 32, count 0 2006.203.08:18:50.20#ibcon#about to read 4, iclass 32, count 0 2006.203.08:18:50.20#ibcon#read 4, iclass 32, count 0 2006.203.08:18:50.20#ibcon#about to read 5, iclass 32, count 0 2006.203.08:18:50.20#ibcon#read 5, iclass 32, count 0 2006.203.08:18:50.20#ibcon#about to read 6, iclass 32, count 0 2006.203.08:18:50.20#ibcon#read 6, iclass 32, count 0 2006.203.08:18:50.20#ibcon#end of sib2, iclass 32, count 0 2006.203.08:18:50.20#ibcon#*after write, iclass 32, count 0 2006.203.08:18:50.20#ibcon#*before return 0, iclass 32, count 0 2006.203.08:18:50.20#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.203.08:18:50.20#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.203.08:18:50.20#ibcon#about to clear, iclass 32 cls_cnt 0 2006.203.08:18:50.20#ibcon#cleared, iclass 32 cls_cnt 0 2006.203.08:18:50.20$vc4f8/va=4,7 2006.203.08:18:50.20#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.203.08:18:50.20#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.203.08:18:50.20#ibcon#ireg 11 cls_cnt 2 2006.203.08:18:50.20#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.203.08:18:50.26#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.203.08:18:50.26#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.203.08:18:50.26#ibcon#enter wrdev, iclass 34, count 2 2006.203.08:18:50.26#ibcon#first serial, iclass 34, count 2 2006.203.08:18:50.26#ibcon#enter sib2, iclass 34, count 2 2006.203.08:18:50.26#ibcon#flushed, iclass 34, count 2 2006.203.08:18:50.26#ibcon#about to write, iclass 34, count 2 2006.203.08:18:50.26#ibcon#wrote, iclass 34, count 2 2006.203.08:18:50.26#ibcon#about to read 3, iclass 34, count 2 2006.203.08:18:50.28#ibcon#read 3, iclass 34, count 2 2006.203.08:18:50.28#ibcon#about to read 4, iclass 34, count 2 2006.203.08:18:50.28#ibcon#read 4, iclass 34, count 2 2006.203.08:18:50.28#ibcon#about to read 5, iclass 34, count 2 2006.203.08:18:50.28#ibcon#read 5, iclass 34, count 2 2006.203.08:18:50.28#ibcon#about to read 6, iclass 34, count 2 2006.203.08:18:50.28#ibcon#read 6, iclass 34, count 2 2006.203.08:18:50.28#ibcon#end of sib2, iclass 34, count 2 2006.203.08:18:50.28#ibcon#*mode == 0, iclass 34, count 2 2006.203.08:18:50.28#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.203.08:18:50.28#ibcon#[25=AT04-07\r\n] 2006.203.08:18:50.28#ibcon#*before write, iclass 34, count 2 2006.203.08:18:50.28#ibcon#enter sib2, iclass 34, count 2 2006.203.08:18:50.28#ibcon#flushed, iclass 34, count 2 2006.203.08:18:50.28#ibcon#about to write, iclass 34, count 2 2006.203.08:18:50.28#ibcon#wrote, iclass 34, count 2 2006.203.08:18:50.28#ibcon#about to read 3, iclass 34, count 2 2006.203.08:18:50.31#ibcon#read 3, iclass 34, count 2 2006.203.08:18:50.31#ibcon#about to read 4, iclass 34, count 2 2006.203.08:18:50.31#ibcon#read 4, iclass 34, count 2 2006.203.08:18:50.31#ibcon#about to read 5, iclass 34, count 2 2006.203.08:18:50.31#ibcon#read 5, iclass 34, count 2 2006.203.08:18:50.31#ibcon#about to read 6, iclass 34, count 2 2006.203.08:18:50.31#ibcon#read 6, iclass 34, count 2 2006.203.08:18:50.31#ibcon#end of sib2, iclass 34, count 2 2006.203.08:18:50.31#ibcon#*after write, iclass 34, count 2 2006.203.08:18:50.31#ibcon#*before return 0, iclass 34, count 2 2006.203.08:18:50.31#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.203.08:18:50.31#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.203.08:18:50.31#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.203.08:18:50.31#ibcon#ireg 7 cls_cnt 0 2006.203.08:18:50.31#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.203.08:18:50.43#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.203.08:18:50.43#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.203.08:18:50.43#ibcon#enter wrdev, iclass 34, count 0 2006.203.08:18:50.43#ibcon#first serial, iclass 34, count 0 2006.203.08:18:50.43#ibcon#enter sib2, iclass 34, count 0 2006.203.08:18:50.43#ibcon#flushed, iclass 34, count 0 2006.203.08:18:50.43#ibcon#about to write, iclass 34, count 0 2006.203.08:18:50.43#ibcon#wrote, iclass 34, count 0 2006.203.08:18:50.43#ibcon#about to read 3, iclass 34, count 0 2006.203.08:18:50.45#ibcon#read 3, iclass 34, count 0 2006.203.08:18:50.45#ibcon#about to read 4, iclass 34, count 0 2006.203.08:18:50.45#ibcon#read 4, iclass 34, count 0 2006.203.08:18:50.45#ibcon#about to read 5, iclass 34, count 0 2006.203.08:18:50.45#ibcon#read 5, iclass 34, count 0 2006.203.08:18:50.45#ibcon#about to read 6, iclass 34, count 0 2006.203.08:18:50.45#ibcon#read 6, iclass 34, count 0 2006.203.08:18:50.45#ibcon#end of sib2, iclass 34, count 0 2006.203.08:18:50.45#ibcon#*mode == 0, iclass 34, count 0 2006.203.08:18:50.45#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.203.08:18:50.45#ibcon#[25=USB\r\n] 2006.203.08:18:50.45#ibcon#*before write, iclass 34, count 0 2006.203.08:18:50.45#ibcon#enter sib2, iclass 34, count 0 2006.203.08:18:50.45#ibcon#flushed, iclass 34, count 0 2006.203.08:18:50.45#ibcon#about to write, iclass 34, count 0 2006.203.08:18:50.45#ibcon#wrote, iclass 34, count 0 2006.203.08:18:50.45#ibcon#about to read 3, iclass 34, count 0 2006.203.08:18:50.48#ibcon#read 3, iclass 34, count 0 2006.203.08:18:50.48#ibcon#about to read 4, iclass 34, count 0 2006.203.08:18:50.48#ibcon#read 4, iclass 34, count 0 2006.203.08:18:50.48#ibcon#about to read 5, iclass 34, count 0 2006.203.08:18:50.48#ibcon#read 5, iclass 34, count 0 2006.203.08:18:50.48#ibcon#about to read 6, iclass 34, count 0 2006.203.08:18:50.48#ibcon#read 6, iclass 34, count 0 2006.203.08:18:50.48#ibcon#end of sib2, iclass 34, count 0 2006.203.08:18:50.48#ibcon#*after write, iclass 34, count 0 2006.203.08:18:50.48#ibcon#*before return 0, iclass 34, count 0 2006.203.08:18:50.48#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.203.08:18:50.48#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.203.08:18:50.48#ibcon#about to clear, iclass 34 cls_cnt 0 2006.203.08:18:50.48#ibcon#cleared, iclass 34 cls_cnt 0 2006.203.08:18:50.48$vc4f8/valo=5,652.99 2006.203.08:18:50.48#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.203.08:18:50.48#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.203.08:18:50.48#ibcon#ireg 17 cls_cnt 0 2006.203.08:18:50.48#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.203.08:18:50.48#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.203.08:18:50.48#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.203.08:18:50.48#ibcon#enter wrdev, iclass 36, count 0 2006.203.08:18:50.48#ibcon#first serial, iclass 36, count 0 2006.203.08:18:50.48#ibcon#enter sib2, iclass 36, count 0 2006.203.08:18:50.48#ibcon#flushed, iclass 36, count 0 2006.203.08:18:50.48#ibcon#about to write, iclass 36, count 0 2006.203.08:18:50.48#ibcon#wrote, iclass 36, count 0 2006.203.08:18:50.48#ibcon#about to read 3, iclass 36, count 0 2006.203.08:18:50.50#ibcon#read 3, iclass 36, count 0 2006.203.08:18:50.50#ibcon#about to read 4, iclass 36, count 0 2006.203.08:18:50.50#ibcon#read 4, iclass 36, count 0 2006.203.08:18:50.50#ibcon#about to read 5, iclass 36, count 0 2006.203.08:18:50.50#ibcon#read 5, iclass 36, count 0 2006.203.08:18:50.50#ibcon#about to read 6, iclass 36, count 0 2006.203.08:18:50.50#ibcon#read 6, iclass 36, count 0 2006.203.08:18:50.50#ibcon#end of sib2, iclass 36, count 0 2006.203.08:18:50.50#ibcon#*mode == 0, iclass 36, count 0 2006.203.08:18:50.50#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.203.08:18:50.50#ibcon#[26=FRQ=05,652.99\r\n] 2006.203.08:18:50.50#ibcon#*before write, iclass 36, count 0 2006.203.08:18:50.50#ibcon#enter sib2, iclass 36, count 0 2006.203.08:18:50.50#ibcon#flushed, iclass 36, count 0 2006.203.08:18:50.50#ibcon#about to write, iclass 36, count 0 2006.203.08:18:50.50#ibcon#wrote, iclass 36, count 0 2006.203.08:18:50.50#ibcon#about to read 3, iclass 36, count 0 2006.203.08:18:50.54#ibcon#read 3, iclass 36, count 0 2006.203.08:18:50.54#ibcon#about to read 4, iclass 36, count 0 2006.203.08:18:50.54#ibcon#read 4, iclass 36, count 0 2006.203.08:18:50.54#ibcon#about to read 5, iclass 36, count 0 2006.203.08:18:50.54#ibcon#read 5, iclass 36, count 0 2006.203.08:18:50.54#ibcon#about to read 6, iclass 36, count 0 2006.203.08:18:50.54#ibcon#read 6, iclass 36, count 0 2006.203.08:18:50.54#ibcon#end of sib2, iclass 36, count 0 2006.203.08:18:50.54#ibcon#*after write, iclass 36, count 0 2006.203.08:18:50.54#ibcon#*before return 0, iclass 36, count 0 2006.203.08:18:50.54#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.203.08:18:50.54#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.203.08:18:50.54#ibcon#about to clear, iclass 36 cls_cnt 0 2006.203.08:18:50.54#ibcon#cleared, iclass 36 cls_cnt 0 2006.203.08:18:50.54$vc4f8/va=5,7 2006.203.08:18:50.54#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.203.08:18:50.54#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.203.08:18:50.54#ibcon#ireg 11 cls_cnt 2 2006.203.08:18:50.54#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.203.08:18:50.61#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.203.08:18:50.61#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.203.08:18:50.61#ibcon#enter wrdev, iclass 38, count 2 2006.203.08:18:50.61#ibcon#first serial, iclass 38, count 2 2006.203.08:18:50.61#ibcon#enter sib2, iclass 38, count 2 2006.203.08:18:50.61#ibcon#flushed, iclass 38, count 2 2006.203.08:18:50.61#ibcon#about to write, iclass 38, count 2 2006.203.08:18:50.61#ibcon#wrote, iclass 38, count 2 2006.203.08:18:50.61#ibcon#about to read 3, iclass 38, count 2 2006.203.08:18:50.62#ibcon#read 3, iclass 38, count 2 2006.203.08:18:50.62#ibcon#about to read 4, iclass 38, count 2 2006.203.08:18:50.62#ibcon#read 4, iclass 38, count 2 2006.203.08:18:50.62#ibcon#about to read 5, iclass 38, count 2 2006.203.08:18:50.62#ibcon#read 5, iclass 38, count 2 2006.203.08:18:50.62#ibcon#about to read 6, iclass 38, count 2 2006.203.08:18:50.62#ibcon#read 6, iclass 38, count 2 2006.203.08:18:50.62#ibcon#end of sib2, iclass 38, count 2 2006.203.08:18:50.62#ibcon#*mode == 0, iclass 38, count 2 2006.203.08:18:50.62#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.203.08:18:50.62#ibcon#[25=AT05-07\r\n] 2006.203.08:18:50.62#ibcon#*before write, iclass 38, count 2 2006.203.08:18:50.62#ibcon#enter sib2, iclass 38, count 2 2006.203.08:18:50.62#ibcon#flushed, iclass 38, count 2 2006.203.08:18:50.62#ibcon#about to write, iclass 38, count 2 2006.203.08:18:50.62#ibcon#wrote, iclass 38, count 2 2006.203.08:18:50.62#ibcon#about to read 3, iclass 38, count 2 2006.203.08:18:50.65#ibcon#read 3, iclass 38, count 2 2006.203.08:18:50.65#ibcon#about to read 4, iclass 38, count 2 2006.203.08:18:50.65#ibcon#read 4, iclass 38, count 2 2006.203.08:18:50.65#ibcon#about to read 5, iclass 38, count 2 2006.203.08:18:50.65#ibcon#read 5, iclass 38, count 2 2006.203.08:18:50.65#ibcon#about to read 6, iclass 38, count 2 2006.203.08:18:50.65#ibcon#read 6, iclass 38, count 2 2006.203.08:18:50.65#ibcon#end of sib2, iclass 38, count 2 2006.203.08:18:50.65#ibcon#*after write, iclass 38, count 2 2006.203.08:18:50.65#ibcon#*before return 0, iclass 38, count 2 2006.203.08:18:50.65#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.203.08:18:50.65#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.203.08:18:50.65#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.203.08:18:50.65#ibcon#ireg 7 cls_cnt 0 2006.203.08:18:50.65#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.203.08:18:50.77#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.203.08:18:50.77#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.203.08:18:50.77#ibcon#enter wrdev, iclass 38, count 0 2006.203.08:18:50.77#ibcon#first serial, iclass 38, count 0 2006.203.08:18:50.77#ibcon#enter sib2, iclass 38, count 0 2006.203.08:18:50.77#ibcon#flushed, iclass 38, count 0 2006.203.08:18:50.77#ibcon#about to write, iclass 38, count 0 2006.203.08:18:50.77#ibcon#wrote, iclass 38, count 0 2006.203.08:18:50.77#ibcon#about to read 3, iclass 38, count 0 2006.203.08:18:50.79#ibcon#read 3, iclass 38, count 0 2006.203.08:18:50.79#ibcon#about to read 4, iclass 38, count 0 2006.203.08:18:50.79#ibcon#read 4, iclass 38, count 0 2006.203.08:18:50.79#ibcon#about to read 5, iclass 38, count 0 2006.203.08:18:50.79#ibcon#read 5, iclass 38, count 0 2006.203.08:18:50.79#ibcon#about to read 6, iclass 38, count 0 2006.203.08:18:50.79#ibcon#read 6, iclass 38, count 0 2006.203.08:18:50.79#ibcon#end of sib2, iclass 38, count 0 2006.203.08:18:50.79#ibcon#*mode == 0, iclass 38, count 0 2006.203.08:18:50.79#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.203.08:18:50.79#ibcon#[25=USB\r\n] 2006.203.08:18:50.79#ibcon#*before write, iclass 38, count 0 2006.203.08:18:50.79#ibcon#enter sib2, iclass 38, count 0 2006.203.08:18:50.79#ibcon#flushed, iclass 38, count 0 2006.203.08:18:50.79#ibcon#about to write, iclass 38, count 0 2006.203.08:18:50.79#ibcon#wrote, iclass 38, count 0 2006.203.08:18:50.79#ibcon#about to read 3, iclass 38, count 0 2006.203.08:18:50.82#ibcon#read 3, iclass 38, count 0 2006.203.08:18:50.82#ibcon#about to read 4, iclass 38, count 0 2006.203.08:18:50.82#ibcon#read 4, iclass 38, count 0 2006.203.08:18:50.82#ibcon#about to read 5, iclass 38, count 0 2006.203.08:18:50.82#ibcon#read 5, iclass 38, count 0 2006.203.08:18:50.82#ibcon#about to read 6, iclass 38, count 0 2006.203.08:18:50.82#ibcon#read 6, iclass 38, count 0 2006.203.08:18:50.82#ibcon#end of sib2, iclass 38, count 0 2006.203.08:18:50.82#ibcon#*after write, iclass 38, count 0 2006.203.08:18:50.82#ibcon#*before return 0, iclass 38, count 0 2006.203.08:18:50.82#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.203.08:18:50.82#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.203.08:18:50.82#ibcon#about to clear, iclass 38 cls_cnt 0 2006.203.08:18:50.82#ibcon#cleared, iclass 38 cls_cnt 0 2006.203.08:18:50.82$vc4f8/valo=6,772.99 2006.203.08:18:50.82#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.203.08:18:50.82#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.203.08:18:50.82#ibcon#ireg 17 cls_cnt 0 2006.203.08:18:50.82#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.203.08:18:50.82#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.203.08:18:50.82#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.203.08:18:50.82#ibcon#enter wrdev, iclass 40, count 0 2006.203.08:18:50.82#ibcon#first serial, iclass 40, count 0 2006.203.08:18:50.82#ibcon#enter sib2, iclass 40, count 0 2006.203.08:18:50.82#ibcon#flushed, iclass 40, count 0 2006.203.08:18:50.82#ibcon#about to write, iclass 40, count 0 2006.203.08:18:50.82#ibcon#wrote, iclass 40, count 0 2006.203.08:18:50.82#ibcon#about to read 3, iclass 40, count 0 2006.203.08:18:50.84#ibcon#read 3, iclass 40, count 0 2006.203.08:18:50.84#ibcon#about to read 4, iclass 40, count 0 2006.203.08:18:50.84#ibcon#read 4, iclass 40, count 0 2006.203.08:18:50.84#ibcon#about to read 5, iclass 40, count 0 2006.203.08:18:50.84#ibcon#read 5, iclass 40, count 0 2006.203.08:18:50.84#ibcon#about to read 6, iclass 40, count 0 2006.203.08:18:50.84#ibcon#read 6, iclass 40, count 0 2006.203.08:18:50.84#ibcon#end of sib2, iclass 40, count 0 2006.203.08:18:50.84#ibcon#*mode == 0, iclass 40, count 0 2006.203.08:18:50.84#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.203.08:18:50.84#ibcon#[26=FRQ=06,772.99\r\n] 2006.203.08:18:50.84#ibcon#*before write, iclass 40, count 0 2006.203.08:18:50.84#ibcon#enter sib2, iclass 40, count 0 2006.203.08:18:50.84#ibcon#flushed, iclass 40, count 0 2006.203.08:18:50.84#ibcon#about to write, iclass 40, count 0 2006.203.08:18:50.84#ibcon#wrote, iclass 40, count 0 2006.203.08:18:50.84#ibcon#about to read 3, iclass 40, count 0 2006.203.08:18:50.88#ibcon#read 3, iclass 40, count 0 2006.203.08:18:50.88#ibcon#about to read 4, iclass 40, count 0 2006.203.08:18:50.88#ibcon#read 4, iclass 40, count 0 2006.203.08:18:50.88#ibcon#about to read 5, iclass 40, count 0 2006.203.08:18:50.88#ibcon#read 5, iclass 40, count 0 2006.203.08:18:50.88#ibcon#about to read 6, iclass 40, count 0 2006.203.08:18:50.88#ibcon#read 6, iclass 40, count 0 2006.203.08:18:50.88#ibcon#end of sib2, iclass 40, count 0 2006.203.08:18:50.88#ibcon#*after write, iclass 40, count 0 2006.203.08:18:50.88#ibcon#*before return 0, iclass 40, count 0 2006.203.08:18:50.88#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.203.08:18:50.88#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.203.08:18:50.88#ibcon#about to clear, iclass 40 cls_cnt 0 2006.203.08:18:50.88#ibcon#cleared, iclass 40 cls_cnt 0 2006.203.08:18:50.88$vc4f8/va=6,6 2006.203.08:18:50.88#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.203.08:18:50.88#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.203.08:18:50.88#ibcon#ireg 11 cls_cnt 2 2006.203.08:18:50.88#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.203.08:18:50.94#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.203.08:18:50.94#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.203.08:18:50.94#ibcon#enter wrdev, iclass 4, count 2 2006.203.08:18:50.94#ibcon#first serial, iclass 4, count 2 2006.203.08:18:50.94#ibcon#enter sib2, iclass 4, count 2 2006.203.08:18:50.94#ibcon#flushed, iclass 4, count 2 2006.203.08:18:50.94#ibcon#about to write, iclass 4, count 2 2006.203.08:18:50.94#ibcon#wrote, iclass 4, count 2 2006.203.08:18:50.94#ibcon#about to read 3, iclass 4, count 2 2006.203.08:18:50.96#ibcon#read 3, iclass 4, count 2 2006.203.08:18:50.96#ibcon#about to read 4, iclass 4, count 2 2006.203.08:18:50.96#ibcon#read 4, iclass 4, count 2 2006.203.08:18:50.96#ibcon#about to read 5, iclass 4, count 2 2006.203.08:18:50.96#ibcon#read 5, iclass 4, count 2 2006.203.08:18:50.96#ibcon#about to read 6, iclass 4, count 2 2006.203.08:18:50.96#ibcon#read 6, iclass 4, count 2 2006.203.08:18:50.96#ibcon#end of sib2, iclass 4, count 2 2006.203.08:18:50.96#ibcon#*mode == 0, iclass 4, count 2 2006.203.08:18:50.96#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.203.08:18:50.96#ibcon#[25=AT06-06\r\n] 2006.203.08:18:50.96#ibcon#*before write, iclass 4, count 2 2006.203.08:18:50.96#ibcon#enter sib2, iclass 4, count 2 2006.203.08:18:50.96#ibcon#flushed, iclass 4, count 2 2006.203.08:18:50.96#ibcon#about to write, iclass 4, count 2 2006.203.08:18:50.96#ibcon#wrote, iclass 4, count 2 2006.203.08:18:50.96#ibcon#about to read 3, iclass 4, count 2 2006.203.08:18:50.99#ibcon#read 3, iclass 4, count 2 2006.203.08:18:50.99#ibcon#about to read 4, iclass 4, count 2 2006.203.08:18:50.99#ibcon#read 4, iclass 4, count 2 2006.203.08:18:50.99#ibcon#about to read 5, iclass 4, count 2 2006.203.08:18:50.99#ibcon#read 5, iclass 4, count 2 2006.203.08:18:50.99#ibcon#about to read 6, iclass 4, count 2 2006.203.08:18:50.99#ibcon#read 6, iclass 4, count 2 2006.203.08:18:50.99#ibcon#end of sib2, iclass 4, count 2 2006.203.08:18:50.99#ibcon#*after write, iclass 4, count 2 2006.203.08:18:50.99#ibcon#*before return 0, iclass 4, count 2 2006.203.08:18:50.99#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.203.08:18:50.99#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.203.08:18:50.99#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.203.08:18:50.99#ibcon#ireg 7 cls_cnt 0 2006.203.08:18:50.99#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.203.08:18:51.11#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.203.08:18:51.11#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.203.08:18:51.11#ibcon#enter wrdev, iclass 4, count 0 2006.203.08:18:51.11#ibcon#first serial, iclass 4, count 0 2006.203.08:18:51.11#ibcon#enter sib2, iclass 4, count 0 2006.203.08:18:51.11#ibcon#flushed, iclass 4, count 0 2006.203.08:18:51.11#ibcon#about to write, iclass 4, count 0 2006.203.08:18:51.11#ibcon#wrote, iclass 4, count 0 2006.203.08:18:51.11#ibcon#about to read 3, iclass 4, count 0 2006.203.08:18:51.13#ibcon#read 3, iclass 4, count 0 2006.203.08:18:51.13#ibcon#about to read 4, iclass 4, count 0 2006.203.08:18:51.13#ibcon#read 4, iclass 4, count 0 2006.203.08:18:51.13#ibcon#about to read 5, iclass 4, count 0 2006.203.08:18:51.13#ibcon#read 5, iclass 4, count 0 2006.203.08:18:51.13#ibcon#about to read 6, iclass 4, count 0 2006.203.08:18:51.13#ibcon#read 6, iclass 4, count 0 2006.203.08:18:51.13#ibcon#end of sib2, iclass 4, count 0 2006.203.08:18:51.13#ibcon#*mode == 0, iclass 4, count 0 2006.203.08:18:51.13#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.203.08:18:51.13#ibcon#[25=USB\r\n] 2006.203.08:18:51.13#ibcon#*before write, iclass 4, count 0 2006.203.08:18:51.13#ibcon#enter sib2, iclass 4, count 0 2006.203.08:18:51.13#ibcon#flushed, iclass 4, count 0 2006.203.08:18:51.13#ibcon#about to write, iclass 4, count 0 2006.203.08:18:51.13#ibcon#wrote, iclass 4, count 0 2006.203.08:18:51.13#ibcon#about to read 3, iclass 4, count 0 2006.203.08:18:51.16#ibcon#read 3, iclass 4, count 0 2006.203.08:18:51.16#ibcon#about to read 4, iclass 4, count 0 2006.203.08:18:51.16#ibcon#read 4, iclass 4, count 0 2006.203.08:18:51.16#ibcon#about to read 5, iclass 4, count 0 2006.203.08:18:51.16#ibcon#read 5, iclass 4, count 0 2006.203.08:18:51.16#ibcon#about to read 6, iclass 4, count 0 2006.203.08:18:51.16#ibcon#read 6, iclass 4, count 0 2006.203.08:18:51.16#ibcon#end of sib2, iclass 4, count 0 2006.203.08:18:51.16#ibcon#*after write, iclass 4, count 0 2006.203.08:18:51.16#ibcon#*before return 0, iclass 4, count 0 2006.203.08:18:51.16#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.203.08:18:51.16#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.203.08:18:51.16#ibcon#about to clear, iclass 4 cls_cnt 0 2006.203.08:18:51.16#ibcon#cleared, iclass 4 cls_cnt 0 2006.203.08:18:51.16$vc4f8/valo=7,832.99 2006.203.08:18:51.16#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.203.08:18:51.16#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.203.08:18:51.16#ibcon#ireg 17 cls_cnt 0 2006.203.08:18:51.16#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.203.08:18:51.16#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.203.08:18:51.16#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.203.08:18:51.16#ibcon#enter wrdev, iclass 6, count 0 2006.203.08:18:51.16#ibcon#first serial, iclass 6, count 0 2006.203.08:18:51.16#ibcon#enter sib2, iclass 6, count 0 2006.203.08:18:51.16#ibcon#flushed, iclass 6, count 0 2006.203.08:18:51.16#ibcon#about to write, iclass 6, count 0 2006.203.08:18:51.16#ibcon#wrote, iclass 6, count 0 2006.203.08:18:51.16#ibcon#about to read 3, iclass 6, count 0 2006.203.08:18:51.18#ibcon#read 3, iclass 6, count 0 2006.203.08:18:51.18#ibcon#about to read 4, iclass 6, count 0 2006.203.08:18:51.18#ibcon#read 4, iclass 6, count 0 2006.203.08:18:51.18#ibcon#about to read 5, iclass 6, count 0 2006.203.08:18:51.18#ibcon#read 5, iclass 6, count 0 2006.203.08:18:51.18#ibcon#about to read 6, iclass 6, count 0 2006.203.08:18:51.18#ibcon#read 6, iclass 6, count 0 2006.203.08:18:51.18#ibcon#end of sib2, iclass 6, count 0 2006.203.08:18:51.18#ibcon#*mode == 0, iclass 6, count 0 2006.203.08:18:51.18#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.203.08:18:51.18#ibcon#[26=FRQ=07,832.99\r\n] 2006.203.08:18:51.18#ibcon#*before write, iclass 6, count 0 2006.203.08:18:51.18#ibcon#enter sib2, iclass 6, count 0 2006.203.08:18:51.18#ibcon#flushed, iclass 6, count 0 2006.203.08:18:51.18#ibcon#about to write, iclass 6, count 0 2006.203.08:18:51.18#ibcon#wrote, iclass 6, count 0 2006.203.08:18:51.18#ibcon#about to read 3, iclass 6, count 0 2006.203.08:18:51.22#ibcon#read 3, iclass 6, count 0 2006.203.08:18:51.22#ibcon#about to read 4, iclass 6, count 0 2006.203.08:18:51.22#ibcon#read 4, iclass 6, count 0 2006.203.08:18:51.22#ibcon#about to read 5, iclass 6, count 0 2006.203.08:18:51.22#ibcon#read 5, iclass 6, count 0 2006.203.08:18:51.22#ibcon#about to read 6, iclass 6, count 0 2006.203.08:18:51.22#ibcon#read 6, iclass 6, count 0 2006.203.08:18:51.22#ibcon#end of sib2, iclass 6, count 0 2006.203.08:18:51.22#ibcon#*after write, iclass 6, count 0 2006.203.08:18:51.22#ibcon#*before return 0, iclass 6, count 0 2006.203.08:18:51.22#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.203.08:18:51.22#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.203.08:18:51.22#ibcon#about to clear, iclass 6 cls_cnt 0 2006.203.08:18:51.22#ibcon#cleared, iclass 6 cls_cnt 0 2006.203.08:18:51.22$vc4f8/va=7,7 2006.203.08:18:51.22#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.203.08:18:51.22#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.203.08:18:51.22#ibcon#ireg 11 cls_cnt 2 2006.203.08:18:51.22#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.203.08:18:51.28#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.203.08:18:51.28#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.203.08:18:51.28#ibcon#enter wrdev, iclass 10, count 2 2006.203.08:18:51.28#ibcon#first serial, iclass 10, count 2 2006.203.08:18:51.28#ibcon#enter sib2, iclass 10, count 2 2006.203.08:18:51.28#ibcon#flushed, iclass 10, count 2 2006.203.08:18:51.28#ibcon#about to write, iclass 10, count 2 2006.203.08:18:51.28#ibcon#wrote, iclass 10, count 2 2006.203.08:18:51.28#ibcon#about to read 3, iclass 10, count 2 2006.203.08:18:51.31#ibcon#read 3, iclass 10, count 2 2006.203.08:18:51.31#ibcon#about to read 4, iclass 10, count 2 2006.203.08:18:51.31#ibcon#read 4, iclass 10, count 2 2006.203.08:18:51.31#ibcon#about to read 5, iclass 10, count 2 2006.203.08:18:51.31#ibcon#read 5, iclass 10, count 2 2006.203.08:18:51.31#ibcon#about to read 6, iclass 10, count 2 2006.203.08:18:51.31#ibcon#read 6, iclass 10, count 2 2006.203.08:18:51.31#ibcon#end of sib2, iclass 10, count 2 2006.203.08:18:51.31#ibcon#*mode == 0, iclass 10, count 2 2006.203.08:18:51.31#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.203.08:18:51.31#ibcon#[25=AT07-07\r\n] 2006.203.08:18:51.31#ibcon#*before write, iclass 10, count 2 2006.203.08:18:51.31#ibcon#enter sib2, iclass 10, count 2 2006.203.08:18:51.31#ibcon#flushed, iclass 10, count 2 2006.203.08:18:51.31#ibcon#about to write, iclass 10, count 2 2006.203.08:18:51.31#ibcon#wrote, iclass 10, count 2 2006.203.08:18:51.31#ibcon#about to read 3, iclass 10, count 2 2006.203.08:18:51.34#ibcon#read 3, iclass 10, count 2 2006.203.08:18:51.34#ibcon#about to read 4, iclass 10, count 2 2006.203.08:18:51.34#ibcon#read 4, iclass 10, count 2 2006.203.08:18:51.34#ibcon#about to read 5, iclass 10, count 2 2006.203.08:18:51.34#ibcon#read 5, iclass 10, count 2 2006.203.08:18:51.34#ibcon#about to read 6, iclass 10, count 2 2006.203.08:18:51.34#ibcon#read 6, iclass 10, count 2 2006.203.08:18:51.34#ibcon#end of sib2, iclass 10, count 2 2006.203.08:18:51.34#ibcon#*after write, iclass 10, count 2 2006.203.08:18:51.34#ibcon#*before return 0, iclass 10, count 2 2006.203.08:18:51.34#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.203.08:18:51.34#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.203.08:18:51.34#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.203.08:18:51.34#ibcon#ireg 7 cls_cnt 0 2006.203.08:18:51.34#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.203.08:18:51.46#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.203.08:18:51.46#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.203.08:18:51.46#ibcon#enter wrdev, iclass 10, count 0 2006.203.08:18:51.46#ibcon#first serial, iclass 10, count 0 2006.203.08:18:51.46#ibcon#enter sib2, iclass 10, count 0 2006.203.08:18:51.46#ibcon#flushed, iclass 10, count 0 2006.203.08:18:51.46#ibcon#about to write, iclass 10, count 0 2006.203.08:18:51.46#ibcon#wrote, iclass 10, count 0 2006.203.08:18:51.46#ibcon#about to read 3, iclass 10, count 0 2006.203.08:18:51.48#ibcon#read 3, iclass 10, count 0 2006.203.08:18:51.48#ibcon#about to read 4, iclass 10, count 0 2006.203.08:18:51.48#ibcon#read 4, iclass 10, count 0 2006.203.08:18:51.48#ibcon#about to read 5, iclass 10, count 0 2006.203.08:18:51.48#ibcon#read 5, iclass 10, count 0 2006.203.08:18:51.48#ibcon#about to read 6, iclass 10, count 0 2006.203.08:18:51.48#ibcon#read 6, iclass 10, count 0 2006.203.08:18:51.48#ibcon#end of sib2, iclass 10, count 0 2006.203.08:18:51.48#ibcon#*mode == 0, iclass 10, count 0 2006.203.08:18:51.48#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.203.08:18:51.48#ibcon#[25=USB\r\n] 2006.203.08:18:51.48#ibcon#*before write, iclass 10, count 0 2006.203.08:18:51.48#ibcon#enter sib2, iclass 10, count 0 2006.203.08:18:51.48#ibcon#flushed, iclass 10, count 0 2006.203.08:18:51.48#ibcon#about to write, iclass 10, count 0 2006.203.08:18:51.48#ibcon#wrote, iclass 10, count 0 2006.203.08:18:51.48#ibcon#about to read 3, iclass 10, count 0 2006.203.08:18:51.51#ibcon#read 3, iclass 10, count 0 2006.203.08:18:51.51#ibcon#about to read 4, iclass 10, count 0 2006.203.08:18:51.51#ibcon#read 4, iclass 10, count 0 2006.203.08:18:51.51#ibcon#about to read 5, iclass 10, count 0 2006.203.08:18:51.51#ibcon#read 5, iclass 10, count 0 2006.203.08:18:51.51#ibcon#about to read 6, iclass 10, count 0 2006.203.08:18:51.51#ibcon#read 6, iclass 10, count 0 2006.203.08:18:51.51#ibcon#end of sib2, iclass 10, count 0 2006.203.08:18:51.51#ibcon#*after write, iclass 10, count 0 2006.203.08:18:51.51#ibcon#*before return 0, iclass 10, count 0 2006.203.08:18:51.51#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.203.08:18:51.51#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.203.08:18:51.51#ibcon#about to clear, iclass 10 cls_cnt 0 2006.203.08:18:51.51#ibcon#cleared, iclass 10 cls_cnt 0 2006.203.08:18:51.51$vc4f8/valo=8,852.99 2006.203.08:18:51.51#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.203.08:18:51.51#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.203.08:18:51.51#ibcon#ireg 17 cls_cnt 0 2006.203.08:18:51.51#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.203.08:18:51.51#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.203.08:18:51.51#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.203.08:18:51.51#ibcon#enter wrdev, iclass 12, count 0 2006.203.08:18:51.51#ibcon#first serial, iclass 12, count 0 2006.203.08:18:51.51#ibcon#enter sib2, iclass 12, count 0 2006.203.08:18:51.51#ibcon#flushed, iclass 12, count 0 2006.203.08:18:51.51#ibcon#about to write, iclass 12, count 0 2006.203.08:18:51.51#ibcon#wrote, iclass 12, count 0 2006.203.08:18:51.51#ibcon#about to read 3, iclass 12, count 0 2006.203.08:18:51.53#ibcon#read 3, iclass 12, count 0 2006.203.08:18:51.53#ibcon#about to read 4, iclass 12, count 0 2006.203.08:18:51.53#ibcon#read 4, iclass 12, count 0 2006.203.08:18:51.53#ibcon#about to read 5, iclass 12, count 0 2006.203.08:18:51.53#ibcon#read 5, iclass 12, count 0 2006.203.08:18:51.53#ibcon#about to read 6, iclass 12, count 0 2006.203.08:18:51.53#ibcon#read 6, iclass 12, count 0 2006.203.08:18:51.53#ibcon#end of sib2, iclass 12, count 0 2006.203.08:18:51.53#ibcon#*mode == 0, iclass 12, count 0 2006.203.08:18:51.53#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.203.08:18:51.53#ibcon#[26=FRQ=08,852.99\r\n] 2006.203.08:18:51.53#ibcon#*before write, iclass 12, count 0 2006.203.08:18:51.53#ibcon#enter sib2, iclass 12, count 0 2006.203.08:18:51.53#ibcon#flushed, iclass 12, count 0 2006.203.08:18:51.53#ibcon#about to write, iclass 12, count 0 2006.203.08:18:51.53#ibcon#wrote, iclass 12, count 0 2006.203.08:18:51.53#ibcon#about to read 3, iclass 12, count 0 2006.203.08:18:51.57#ibcon#read 3, iclass 12, count 0 2006.203.08:18:51.57#ibcon#about to read 4, iclass 12, count 0 2006.203.08:18:51.57#ibcon#read 4, iclass 12, count 0 2006.203.08:18:51.57#ibcon#about to read 5, iclass 12, count 0 2006.203.08:18:51.57#ibcon#read 5, iclass 12, count 0 2006.203.08:18:51.57#ibcon#about to read 6, iclass 12, count 0 2006.203.08:18:51.57#ibcon#read 6, iclass 12, count 0 2006.203.08:18:51.57#ibcon#end of sib2, iclass 12, count 0 2006.203.08:18:51.57#ibcon#*after write, iclass 12, count 0 2006.203.08:18:51.57#ibcon#*before return 0, iclass 12, count 0 2006.203.08:18:51.57#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.203.08:18:51.57#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.203.08:18:51.57#ibcon#about to clear, iclass 12 cls_cnt 0 2006.203.08:18:51.57#ibcon#cleared, iclass 12 cls_cnt 0 2006.203.08:18:51.57$vc4f8/va=8,6 2006.203.08:18:51.57#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.203.08:18:51.57#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.203.08:18:51.57#ibcon#ireg 11 cls_cnt 2 2006.203.08:18:51.57#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.203.08:18:51.63#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.203.08:18:51.63#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.203.08:18:51.63#ibcon#enter wrdev, iclass 14, count 2 2006.203.08:18:51.63#ibcon#first serial, iclass 14, count 2 2006.203.08:18:51.63#ibcon#enter sib2, iclass 14, count 2 2006.203.08:18:51.63#ibcon#flushed, iclass 14, count 2 2006.203.08:18:51.63#ibcon#about to write, iclass 14, count 2 2006.203.08:18:51.63#ibcon#wrote, iclass 14, count 2 2006.203.08:18:51.63#ibcon#about to read 3, iclass 14, count 2 2006.203.08:18:51.65#ibcon#read 3, iclass 14, count 2 2006.203.08:18:51.65#ibcon#about to read 4, iclass 14, count 2 2006.203.08:18:51.65#ibcon#read 4, iclass 14, count 2 2006.203.08:18:51.65#ibcon#about to read 5, iclass 14, count 2 2006.203.08:18:51.65#ibcon#read 5, iclass 14, count 2 2006.203.08:18:51.65#ibcon#about to read 6, iclass 14, count 2 2006.203.08:18:51.65#ibcon#read 6, iclass 14, count 2 2006.203.08:18:51.65#ibcon#end of sib2, iclass 14, count 2 2006.203.08:18:51.65#ibcon#*mode == 0, iclass 14, count 2 2006.203.08:18:51.65#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.203.08:18:51.65#ibcon#[25=AT08-06\r\n] 2006.203.08:18:51.65#ibcon#*before write, iclass 14, count 2 2006.203.08:18:51.65#ibcon#enter sib2, iclass 14, count 2 2006.203.08:18:51.65#ibcon#flushed, iclass 14, count 2 2006.203.08:18:51.65#ibcon#about to write, iclass 14, count 2 2006.203.08:18:51.65#ibcon#wrote, iclass 14, count 2 2006.203.08:18:51.65#ibcon#about to read 3, iclass 14, count 2 2006.203.08:18:51.68#ibcon#read 3, iclass 14, count 2 2006.203.08:18:51.68#ibcon#about to read 4, iclass 14, count 2 2006.203.08:18:51.68#ibcon#read 4, iclass 14, count 2 2006.203.08:18:51.68#ibcon#about to read 5, iclass 14, count 2 2006.203.08:18:51.68#ibcon#read 5, iclass 14, count 2 2006.203.08:18:51.68#ibcon#about to read 6, iclass 14, count 2 2006.203.08:18:51.68#ibcon#read 6, iclass 14, count 2 2006.203.08:18:51.68#ibcon#end of sib2, iclass 14, count 2 2006.203.08:18:51.68#ibcon#*after write, iclass 14, count 2 2006.203.08:18:51.68#ibcon#*before return 0, iclass 14, count 2 2006.203.08:18:51.68#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.203.08:18:51.68#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.203.08:18:51.68#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.203.08:18:51.68#ibcon#ireg 7 cls_cnt 0 2006.203.08:18:51.68#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.203.08:18:51.75#abcon#<5=/04 1.4 3.1 23.561001001.1\r\n> 2006.203.08:18:51.77#abcon#{5=INTERFACE CLEAR} 2006.203.08:18:51.80#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.203.08:18:51.80#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.203.08:18:51.80#ibcon#enter wrdev, iclass 14, count 0 2006.203.08:18:51.80#ibcon#first serial, iclass 14, count 0 2006.203.08:18:51.80#ibcon#enter sib2, iclass 14, count 0 2006.203.08:18:51.80#ibcon#flushed, iclass 14, count 0 2006.203.08:18:51.80#ibcon#about to write, iclass 14, count 0 2006.203.08:18:51.80#ibcon#wrote, iclass 14, count 0 2006.203.08:18:51.80#ibcon#about to read 3, iclass 14, count 0 2006.203.08:18:51.82#ibcon#read 3, iclass 14, count 0 2006.203.08:18:51.82#ibcon#about to read 4, iclass 14, count 0 2006.203.08:18:51.82#ibcon#read 4, iclass 14, count 0 2006.203.08:18:51.82#ibcon#about to read 5, iclass 14, count 0 2006.203.08:18:51.82#ibcon#read 5, iclass 14, count 0 2006.203.08:18:51.82#ibcon#about to read 6, iclass 14, count 0 2006.203.08:18:51.82#ibcon#read 6, iclass 14, count 0 2006.203.08:18:51.82#ibcon#end of sib2, iclass 14, count 0 2006.203.08:18:51.82#ibcon#*mode == 0, iclass 14, count 0 2006.203.08:18:51.82#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.203.08:18:51.82#ibcon#[25=USB\r\n] 2006.203.08:18:51.82#ibcon#*before write, iclass 14, count 0 2006.203.08:18:51.82#ibcon#enter sib2, iclass 14, count 0 2006.203.08:18:51.82#ibcon#flushed, iclass 14, count 0 2006.203.08:18:51.82#ibcon#about to write, iclass 14, count 0 2006.203.08:18:51.82#ibcon#wrote, iclass 14, count 0 2006.203.08:18:51.82#ibcon#about to read 3, iclass 14, count 0 2006.203.08:18:51.83#abcon#[5=S1D000X0/0*\r\n] 2006.203.08:18:51.85#ibcon#read 3, iclass 14, count 0 2006.203.08:18:51.85#ibcon#about to read 4, iclass 14, count 0 2006.203.08:18:51.85#ibcon#read 4, iclass 14, count 0 2006.203.08:18:51.85#ibcon#about to read 5, iclass 14, count 0 2006.203.08:18:51.85#ibcon#read 5, iclass 14, count 0 2006.203.08:18:51.85#ibcon#about to read 6, iclass 14, count 0 2006.203.08:18:51.85#ibcon#read 6, iclass 14, count 0 2006.203.08:18:51.85#ibcon#end of sib2, iclass 14, count 0 2006.203.08:18:51.85#ibcon#*after write, iclass 14, count 0 2006.203.08:18:51.85#ibcon#*before return 0, iclass 14, count 0 2006.203.08:18:51.85#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.203.08:18:51.85#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.203.08:18:51.85#ibcon#about to clear, iclass 14 cls_cnt 0 2006.203.08:18:51.85#ibcon#cleared, iclass 14 cls_cnt 0 2006.203.08:18:51.85$vc4f8/vblo=1,632.99 2006.203.08:18:51.85#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.203.08:18:51.85#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.203.08:18:51.85#ibcon#ireg 17 cls_cnt 0 2006.203.08:18:51.85#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.203.08:18:51.85#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.203.08:18:51.85#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.203.08:18:51.85#ibcon#enter wrdev, iclass 20, count 0 2006.203.08:18:51.85#ibcon#first serial, iclass 20, count 0 2006.203.08:18:51.85#ibcon#enter sib2, iclass 20, count 0 2006.203.08:18:51.85#ibcon#flushed, iclass 20, count 0 2006.203.08:18:51.85#ibcon#about to write, iclass 20, count 0 2006.203.08:18:51.85#ibcon#wrote, iclass 20, count 0 2006.203.08:18:51.85#ibcon#about to read 3, iclass 20, count 0 2006.203.08:18:51.87#ibcon#read 3, iclass 20, count 0 2006.203.08:18:51.87#ibcon#about to read 4, iclass 20, count 0 2006.203.08:18:51.87#ibcon#read 4, iclass 20, count 0 2006.203.08:18:51.87#ibcon#about to read 5, iclass 20, count 0 2006.203.08:18:51.87#ibcon#read 5, iclass 20, count 0 2006.203.08:18:51.87#ibcon#about to read 6, iclass 20, count 0 2006.203.08:18:51.87#ibcon#read 6, iclass 20, count 0 2006.203.08:18:51.87#ibcon#end of sib2, iclass 20, count 0 2006.203.08:18:51.87#ibcon#*mode == 0, iclass 20, count 0 2006.203.08:18:51.87#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.203.08:18:51.87#ibcon#[28=FRQ=01,632.99\r\n] 2006.203.08:18:51.87#ibcon#*before write, iclass 20, count 0 2006.203.08:18:51.87#ibcon#enter sib2, iclass 20, count 0 2006.203.08:18:51.87#ibcon#flushed, iclass 20, count 0 2006.203.08:18:51.87#ibcon#about to write, iclass 20, count 0 2006.203.08:18:51.87#ibcon#wrote, iclass 20, count 0 2006.203.08:18:51.87#ibcon#about to read 3, iclass 20, count 0 2006.203.08:18:51.91#ibcon#read 3, iclass 20, count 0 2006.203.08:18:51.91#ibcon#about to read 4, iclass 20, count 0 2006.203.08:18:51.91#ibcon#read 4, iclass 20, count 0 2006.203.08:18:51.91#ibcon#about to read 5, iclass 20, count 0 2006.203.08:18:51.91#ibcon#read 5, iclass 20, count 0 2006.203.08:18:51.91#ibcon#about to read 6, iclass 20, count 0 2006.203.08:18:51.91#ibcon#read 6, iclass 20, count 0 2006.203.08:18:51.91#ibcon#end of sib2, iclass 20, count 0 2006.203.08:18:51.91#ibcon#*after write, iclass 20, count 0 2006.203.08:18:51.91#ibcon#*before return 0, iclass 20, count 0 2006.203.08:18:51.91#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.203.08:18:51.91#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.203.08:18:51.91#ibcon#about to clear, iclass 20 cls_cnt 0 2006.203.08:18:51.91#ibcon#cleared, iclass 20 cls_cnt 0 2006.203.08:18:51.91$vc4f8/vb=1,4 2006.203.08:18:51.91#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.203.08:18:51.91#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.203.08:18:51.91#ibcon#ireg 11 cls_cnt 2 2006.203.08:18:51.91#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.203.08:18:51.91#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.203.08:18:51.91#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.203.08:18:51.91#ibcon#enter wrdev, iclass 22, count 2 2006.203.08:18:51.91#ibcon#first serial, iclass 22, count 2 2006.203.08:18:51.91#ibcon#enter sib2, iclass 22, count 2 2006.203.08:18:51.91#ibcon#flushed, iclass 22, count 2 2006.203.08:18:51.91#ibcon#about to write, iclass 22, count 2 2006.203.08:18:51.91#ibcon#wrote, iclass 22, count 2 2006.203.08:18:51.91#ibcon#about to read 3, iclass 22, count 2 2006.203.08:18:51.93#ibcon#read 3, iclass 22, count 2 2006.203.08:18:51.93#ibcon#about to read 4, iclass 22, count 2 2006.203.08:18:51.93#ibcon#read 4, iclass 22, count 2 2006.203.08:18:51.93#ibcon#about to read 5, iclass 22, count 2 2006.203.08:18:51.93#ibcon#read 5, iclass 22, count 2 2006.203.08:18:51.93#ibcon#about to read 6, iclass 22, count 2 2006.203.08:18:51.93#ibcon#read 6, iclass 22, count 2 2006.203.08:18:51.93#ibcon#end of sib2, iclass 22, count 2 2006.203.08:18:51.93#ibcon#*mode == 0, iclass 22, count 2 2006.203.08:18:51.93#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.203.08:18:51.93#ibcon#[27=AT01-04\r\n] 2006.203.08:18:51.93#ibcon#*before write, iclass 22, count 2 2006.203.08:18:51.93#ibcon#enter sib2, iclass 22, count 2 2006.203.08:18:51.93#ibcon#flushed, iclass 22, count 2 2006.203.08:18:51.93#ibcon#about to write, iclass 22, count 2 2006.203.08:18:51.93#ibcon#wrote, iclass 22, count 2 2006.203.08:18:51.93#ibcon#about to read 3, iclass 22, count 2 2006.203.08:18:51.96#ibcon#read 3, iclass 22, count 2 2006.203.08:18:51.96#ibcon#about to read 4, iclass 22, count 2 2006.203.08:18:51.96#ibcon#read 4, iclass 22, count 2 2006.203.08:18:51.96#ibcon#about to read 5, iclass 22, count 2 2006.203.08:18:51.96#ibcon#read 5, iclass 22, count 2 2006.203.08:18:51.96#ibcon#about to read 6, iclass 22, count 2 2006.203.08:18:51.96#ibcon#read 6, iclass 22, count 2 2006.203.08:18:51.96#ibcon#end of sib2, iclass 22, count 2 2006.203.08:18:51.96#ibcon#*after write, iclass 22, count 2 2006.203.08:18:51.96#ibcon#*before return 0, iclass 22, count 2 2006.203.08:18:51.96#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.203.08:18:51.96#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.203.08:18:51.96#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.203.08:18:51.96#ibcon#ireg 7 cls_cnt 0 2006.203.08:18:51.96#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.203.08:18:52.08#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.203.08:18:52.08#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.203.08:18:52.08#ibcon#enter wrdev, iclass 22, count 0 2006.203.08:18:52.08#ibcon#first serial, iclass 22, count 0 2006.203.08:18:52.08#ibcon#enter sib2, iclass 22, count 0 2006.203.08:18:52.08#ibcon#flushed, iclass 22, count 0 2006.203.08:18:52.08#ibcon#about to write, iclass 22, count 0 2006.203.08:18:52.08#ibcon#wrote, iclass 22, count 0 2006.203.08:18:52.08#ibcon#about to read 3, iclass 22, count 0 2006.203.08:18:52.12#ibcon#read 3, iclass 22, count 0 2006.203.08:18:52.12#ibcon#about to read 4, iclass 22, count 0 2006.203.08:18:52.12#ibcon#read 4, iclass 22, count 0 2006.203.08:18:52.12#ibcon#about to read 5, iclass 22, count 0 2006.203.08:18:52.12#ibcon#read 5, iclass 22, count 0 2006.203.08:18:52.12#ibcon#about to read 6, iclass 22, count 0 2006.203.08:18:52.12#ibcon#read 6, iclass 22, count 0 2006.203.08:18:52.12#ibcon#end of sib2, iclass 22, count 0 2006.203.08:18:52.12#ibcon#*mode == 0, iclass 22, count 0 2006.203.08:18:52.12#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.203.08:18:52.12#ibcon#[27=USB\r\n] 2006.203.08:18:52.12#ibcon#*before write, iclass 22, count 0 2006.203.08:18:52.12#ibcon#enter sib2, iclass 22, count 0 2006.203.08:18:52.12#ibcon#flushed, iclass 22, count 0 2006.203.08:18:52.12#ibcon#about to write, iclass 22, count 0 2006.203.08:18:52.12#ibcon#wrote, iclass 22, count 0 2006.203.08:18:52.12#ibcon#about to read 3, iclass 22, count 0 2006.203.08:18:52.15#ibcon#read 3, iclass 22, count 0 2006.203.08:18:52.15#ibcon#about to read 4, iclass 22, count 0 2006.203.08:18:52.15#ibcon#read 4, iclass 22, count 0 2006.203.08:18:52.15#ibcon#about to read 5, iclass 22, count 0 2006.203.08:18:52.15#ibcon#read 5, iclass 22, count 0 2006.203.08:18:52.15#ibcon#about to read 6, iclass 22, count 0 2006.203.08:18:52.15#ibcon#read 6, iclass 22, count 0 2006.203.08:18:52.15#ibcon#end of sib2, iclass 22, count 0 2006.203.08:18:52.15#ibcon#*after write, iclass 22, count 0 2006.203.08:18:52.15#ibcon#*before return 0, iclass 22, count 0 2006.203.08:18:52.15#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.203.08:18:52.15#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.203.08:18:52.15#ibcon#about to clear, iclass 22 cls_cnt 0 2006.203.08:18:52.15#ibcon#cleared, iclass 22 cls_cnt 0 2006.203.08:18:52.15$vc4f8/vblo=2,640.99 2006.203.08:18:52.15#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.203.08:18:52.15#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.203.08:18:52.15#ibcon#ireg 17 cls_cnt 0 2006.203.08:18:52.15#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.203.08:18:52.15#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.203.08:18:52.15#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.203.08:18:52.15#ibcon#enter wrdev, iclass 24, count 0 2006.203.08:18:52.15#ibcon#first serial, iclass 24, count 0 2006.203.08:18:52.15#ibcon#enter sib2, iclass 24, count 0 2006.203.08:18:52.15#ibcon#flushed, iclass 24, count 0 2006.203.08:18:52.15#ibcon#about to write, iclass 24, count 0 2006.203.08:18:52.15#ibcon#wrote, iclass 24, count 0 2006.203.08:18:52.15#ibcon#about to read 3, iclass 24, count 0 2006.203.08:18:52.17#ibcon#read 3, iclass 24, count 0 2006.203.08:18:52.17#ibcon#about to read 4, iclass 24, count 0 2006.203.08:18:52.17#ibcon#read 4, iclass 24, count 0 2006.203.08:18:52.17#ibcon#about to read 5, iclass 24, count 0 2006.203.08:18:52.17#ibcon#read 5, iclass 24, count 0 2006.203.08:18:52.17#ibcon#about to read 6, iclass 24, count 0 2006.203.08:18:52.17#ibcon#read 6, iclass 24, count 0 2006.203.08:18:52.17#ibcon#end of sib2, iclass 24, count 0 2006.203.08:18:52.17#ibcon#*mode == 0, iclass 24, count 0 2006.203.08:18:52.17#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.203.08:18:52.17#ibcon#[28=FRQ=02,640.99\r\n] 2006.203.08:18:52.17#ibcon#*before write, iclass 24, count 0 2006.203.08:18:52.17#ibcon#enter sib2, iclass 24, count 0 2006.203.08:18:52.17#ibcon#flushed, iclass 24, count 0 2006.203.08:18:52.17#ibcon#about to write, iclass 24, count 0 2006.203.08:18:52.17#ibcon#wrote, iclass 24, count 0 2006.203.08:18:52.17#ibcon#about to read 3, iclass 24, count 0 2006.203.08:18:52.21#ibcon#read 3, iclass 24, count 0 2006.203.08:18:52.21#ibcon#about to read 4, iclass 24, count 0 2006.203.08:18:52.21#ibcon#read 4, iclass 24, count 0 2006.203.08:18:52.21#ibcon#about to read 5, iclass 24, count 0 2006.203.08:18:52.21#ibcon#read 5, iclass 24, count 0 2006.203.08:18:52.21#ibcon#about to read 6, iclass 24, count 0 2006.203.08:18:52.21#ibcon#read 6, iclass 24, count 0 2006.203.08:18:52.21#ibcon#end of sib2, iclass 24, count 0 2006.203.08:18:52.21#ibcon#*after write, iclass 24, count 0 2006.203.08:18:52.21#ibcon#*before return 0, iclass 24, count 0 2006.203.08:18:52.21#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.203.08:18:52.21#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.203.08:18:52.21#ibcon#about to clear, iclass 24 cls_cnt 0 2006.203.08:18:52.21#ibcon#cleared, iclass 24 cls_cnt 0 2006.203.08:18:52.21$vc4f8/vb=2,4 2006.203.08:18:52.21#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.203.08:18:52.21#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.203.08:18:52.21#ibcon#ireg 11 cls_cnt 2 2006.203.08:18:52.21#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.203.08:18:52.27#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.203.08:18:52.27#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.203.08:18:52.27#ibcon#enter wrdev, iclass 26, count 2 2006.203.08:18:52.27#ibcon#first serial, iclass 26, count 2 2006.203.08:18:52.27#ibcon#enter sib2, iclass 26, count 2 2006.203.08:18:52.27#ibcon#flushed, iclass 26, count 2 2006.203.08:18:52.27#ibcon#about to write, iclass 26, count 2 2006.203.08:18:52.27#ibcon#wrote, iclass 26, count 2 2006.203.08:18:52.27#ibcon#about to read 3, iclass 26, count 2 2006.203.08:18:52.29#ibcon#read 3, iclass 26, count 2 2006.203.08:18:52.29#ibcon#about to read 4, iclass 26, count 2 2006.203.08:18:52.29#ibcon#read 4, iclass 26, count 2 2006.203.08:18:52.29#ibcon#about to read 5, iclass 26, count 2 2006.203.08:18:52.29#ibcon#read 5, iclass 26, count 2 2006.203.08:18:52.29#ibcon#about to read 6, iclass 26, count 2 2006.203.08:18:52.29#ibcon#read 6, iclass 26, count 2 2006.203.08:18:52.29#ibcon#end of sib2, iclass 26, count 2 2006.203.08:18:52.29#ibcon#*mode == 0, iclass 26, count 2 2006.203.08:18:52.29#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.203.08:18:52.29#ibcon#[27=AT02-04\r\n] 2006.203.08:18:52.29#ibcon#*before write, iclass 26, count 2 2006.203.08:18:52.29#ibcon#enter sib2, iclass 26, count 2 2006.203.08:18:52.29#ibcon#flushed, iclass 26, count 2 2006.203.08:18:52.29#ibcon#about to write, iclass 26, count 2 2006.203.08:18:52.29#ibcon#wrote, iclass 26, count 2 2006.203.08:18:52.29#ibcon#about to read 3, iclass 26, count 2 2006.203.08:18:52.32#ibcon#read 3, iclass 26, count 2 2006.203.08:18:52.32#ibcon#about to read 4, iclass 26, count 2 2006.203.08:18:52.32#ibcon#read 4, iclass 26, count 2 2006.203.08:18:52.32#ibcon#about to read 5, iclass 26, count 2 2006.203.08:18:52.32#ibcon#read 5, iclass 26, count 2 2006.203.08:18:52.32#ibcon#about to read 6, iclass 26, count 2 2006.203.08:18:52.32#ibcon#read 6, iclass 26, count 2 2006.203.08:18:52.32#ibcon#end of sib2, iclass 26, count 2 2006.203.08:18:52.32#ibcon#*after write, iclass 26, count 2 2006.203.08:18:52.32#ibcon#*before return 0, iclass 26, count 2 2006.203.08:18:52.32#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.203.08:18:52.32#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.203.08:18:52.32#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.203.08:18:52.32#ibcon#ireg 7 cls_cnt 0 2006.203.08:18:52.32#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.203.08:18:52.44#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.203.08:18:52.44#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.203.08:18:52.44#ibcon#enter wrdev, iclass 26, count 0 2006.203.08:18:52.44#ibcon#first serial, iclass 26, count 0 2006.203.08:18:52.44#ibcon#enter sib2, iclass 26, count 0 2006.203.08:18:52.44#ibcon#flushed, iclass 26, count 0 2006.203.08:18:52.44#ibcon#about to write, iclass 26, count 0 2006.203.08:18:52.44#ibcon#wrote, iclass 26, count 0 2006.203.08:18:52.44#ibcon#about to read 3, iclass 26, count 0 2006.203.08:18:52.46#ibcon#read 3, iclass 26, count 0 2006.203.08:18:52.46#ibcon#about to read 4, iclass 26, count 0 2006.203.08:18:52.46#ibcon#read 4, iclass 26, count 0 2006.203.08:18:52.46#ibcon#about to read 5, iclass 26, count 0 2006.203.08:18:52.46#ibcon#read 5, iclass 26, count 0 2006.203.08:18:52.46#ibcon#about to read 6, iclass 26, count 0 2006.203.08:18:52.46#ibcon#read 6, iclass 26, count 0 2006.203.08:18:52.46#ibcon#end of sib2, iclass 26, count 0 2006.203.08:18:52.46#ibcon#*mode == 0, iclass 26, count 0 2006.203.08:18:52.46#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.203.08:18:52.46#ibcon#[27=USB\r\n] 2006.203.08:18:52.46#ibcon#*before write, iclass 26, count 0 2006.203.08:18:52.46#ibcon#enter sib2, iclass 26, count 0 2006.203.08:18:52.46#ibcon#flushed, iclass 26, count 0 2006.203.08:18:52.46#ibcon#about to write, iclass 26, count 0 2006.203.08:18:52.46#ibcon#wrote, iclass 26, count 0 2006.203.08:18:52.46#ibcon#about to read 3, iclass 26, count 0 2006.203.08:18:52.49#ibcon#read 3, iclass 26, count 0 2006.203.08:18:52.49#ibcon#about to read 4, iclass 26, count 0 2006.203.08:18:52.49#ibcon#read 4, iclass 26, count 0 2006.203.08:18:52.49#ibcon#about to read 5, iclass 26, count 0 2006.203.08:18:52.49#ibcon#read 5, iclass 26, count 0 2006.203.08:18:52.49#ibcon#about to read 6, iclass 26, count 0 2006.203.08:18:52.49#ibcon#read 6, iclass 26, count 0 2006.203.08:18:52.49#ibcon#end of sib2, iclass 26, count 0 2006.203.08:18:52.49#ibcon#*after write, iclass 26, count 0 2006.203.08:18:52.49#ibcon#*before return 0, iclass 26, count 0 2006.203.08:18:52.49#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.203.08:18:52.49#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.203.08:18:52.49#ibcon#about to clear, iclass 26 cls_cnt 0 2006.203.08:18:52.49#ibcon#cleared, iclass 26 cls_cnt 0 2006.203.08:18:52.49$vc4f8/vblo=3,656.99 2006.203.08:18:52.49#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.203.08:18:52.49#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.203.08:18:52.49#ibcon#ireg 17 cls_cnt 0 2006.203.08:18:52.49#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.203.08:18:52.49#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.203.08:18:52.49#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.203.08:18:52.49#ibcon#enter wrdev, iclass 28, count 0 2006.203.08:18:52.49#ibcon#first serial, iclass 28, count 0 2006.203.08:18:52.49#ibcon#enter sib2, iclass 28, count 0 2006.203.08:18:52.49#ibcon#flushed, iclass 28, count 0 2006.203.08:18:52.49#ibcon#about to write, iclass 28, count 0 2006.203.08:18:52.49#ibcon#wrote, iclass 28, count 0 2006.203.08:18:52.49#ibcon#about to read 3, iclass 28, count 0 2006.203.08:18:52.51#ibcon#read 3, iclass 28, count 0 2006.203.08:18:52.51#ibcon#about to read 4, iclass 28, count 0 2006.203.08:18:52.51#ibcon#read 4, iclass 28, count 0 2006.203.08:18:52.51#ibcon#about to read 5, iclass 28, count 0 2006.203.08:18:52.51#ibcon#read 5, iclass 28, count 0 2006.203.08:18:52.51#ibcon#about to read 6, iclass 28, count 0 2006.203.08:18:52.51#ibcon#read 6, iclass 28, count 0 2006.203.08:18:52.51#ibcon#end of sib2, iclass 28, count 0 2006.203.08:18:52.51#ibcon#*mode == 0, iclass 28, count 0 2006.203.08:18:52.51#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.203.08:18:52.51#ibcon#[28=FRQ=03,656.99\r\n] 2006.203.08:18:52.51#ibcon#*before write, iclass 28, count 0 2006.203.08:18:52.51#ibcon#enter sib2, iclass 28, count 0 2006.203.08:18:52.51#ibcon#flushed, iclass 28, count 0 2006.203.08:18:52.51#ibcon#about to write, iclass 28, count 0 2006.203.08:18:52.51#ibcon#wrote, iclass 28, count 0 2006.203.08:18:52.51#ibcon#about to read 3, iclass 28, count 0 2006.203.08:18:52.55#ibcon#read 3, iclass 28, count 0 2006.203.08:18:52.55#ibcon#about to read 4, iclass 28, count 0 2006.203.08:18:52.55#ibcon#read 4, iclass 28, count 0 2006.203.08:18:52.55#ibcon#about to read 5, iclass 28, count 0 2006.203.08:18:52.55#ibcon#read 5, iclass 28, count 0 2006.203.08:18:52.55#ibcon#about to read 6, iclass 28, count 0 2006.203.08:18:52.55#ibcon#read 6, iclass 28, count 0 2006.203.08:18:52.55#ibcon#end of sib2, iclass 28, count 0 2006.203.08:18:52.55#ibcon#*after write, iclass 28, count 0 2006.203.08:18:52.55#ibcon#*before return 0, iclass 28, count 0 2006.203.08:18:52.55#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.203.08:18:52.55#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.203.08:18:52.55#ibcon#about to clear, iclass 28 cls_cnt 0 2006.203.08:18:52.55#ibcon#cleared, iclass 28 cls_cnt 0 2006.203.08:18:52.55$vc4f8/vb=3,4 2006.203.08:18:52.55#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.203.08:18:52.55#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.203.08:18:52.55#ibcon#ireg 11 cls_cnt 2 2006.203.08:18:52.55#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.203.08:18:52.61#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.203.08:18:52.61#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.203.08:18:52.61#ibcon#enter wrdev, iclass 30, count 2 2006.203.08:18:52.61#ibcon#first serial, iclass 30, count 2 2006.203.08:18:52.61#ibcon#enter sib2, iclass 30, count 2 2006.203.08:18:52.61#ibcon#flushed, iclass 30, count 2 2006.203.08:18:52.61#ibcon#about to write, iclass 30, count 2 2006.203.08:18:52.61#ibcon#wrote, iclass 30, count 2 2006.203.08:18:52.61#ibcon#about to read 3, iclass 30, count 2 2006.203.08:18:52.63#ibcon#read 3, iclass 30, count 2 2006.203.08:18:52.63#ibcon#about to read 4, iclass 30, count 2 2006.203.08:18:52.63#ibcon#read 4, iclass 30, count 2 2006.203.08:18:52.63#ibcon#about to read 5, iclass 30, count 2 2006.203.08:18:52.63#ibcon#read 5, iclass 30, count 2 2006.203.08:18:52.63#ibcon#about to read 6, iclass 30, count 2 2006.203.08:18:52.63#ibcon#read 6, iclass 30, count 2 2006.203.08:18:52.63#ibcon#end of sib2, iclass 30, count 2 2006.203.08:18:52.63#ibcon#*mode == 0, iclass 30, count 2 2006.203.08:18:52.63#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.203.08:18:52.63#ibcon#[27=AT03-04\r\n] 2006.203.08:18:52.63#ibcon#*before write, iclass 30, count 2 2006.203.08:18:52.63#ibcon#enter sib2, iclass 30, count 2 2006.203.08:18:52.63#ibcon#flushed, iclass 30, count 2 2006.203.08:18:52.63#ibcon#about to write, iclass 30, count 2 2006.203.08:18:52.63#ibcon#wrote, iclass 30, count 2 2006.203.08:18:52.63#ibcon#about to read 3, iclass 30, count 2 2006.203.08:18:52.66#ibcon#read 3, iclass 30, count 2 2006.203.08:18:52.66#ibcon#about to read 4, iclass 30, count 2 2006.203.08:18:52.66#ibcon#read 4, iclass 30, count 2 2006.203.08:18:52.66#ibcon#about to read 5, iclass 30, count 2 2006.203.08:18:52.66#ibcon#read 5, iclass 30, count 2 2006.203.08:18:52.66#ibcon#about to read 6, iclass 30, count 2 2006.203.08:18:52.66#ibcon#read 6, iclass 30, count 2 2006.203.08:18:52.66#ibcon#end of sib2, iclass 30, count 2 2006.203.08:18:52.66#ibcon#*after write, iclass 30, count 2 2006.203.08:18:52.66#ibcon#*before return 0, iclass 30, count 2 2006.203.08:18:52.66#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.203.08:18:52.66#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.203.08:18:52.66#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.203.08:18:52.66#ibcon#ireg 7 cls_cnt 0 2006.203.08:18:52.66#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.203.08:18:52.78#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.203.08:18:52.78#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.203.08:18:52.78#ibcon#enter wrdev, iclass 30, count 0 2006.203.08:18:52.78#ibcon#first serial, iclass 30, count 0 2006.203.08:18:52.78#ibcon#enter sib2, iclass 30, count 0 2006.203.08:18:52.78#ibcon#flushed, iclass 30, count 0 2006.203.08:18:52.78#ibcon#about to write, iclass 30, count 0 2006.203.08:18:52.78#ibcon#wrote, iclass 30, count 0 2006.203.08:18:52.78#ibcon#about to read 3, iclass 30, count 0 2006.203.08:18:52.80#ibcon#read 3, iclass 30, count 0 2006.203.08:18:52.80#ibcon#about to read 4, iclass 30, count 0 2006.203.08:18:52.80#ibcon#read 4, iclass 30, count 0 2006.203.08:18:52.80#ibcon#about to read 5, iclass 30, count 0 2006.203.08:18:52.80#ibcon#read 5, iclass 30, count 0 2006.203.08:18:52.80#ibcon#about to read 6, iclass 30, count 0 2006.203.08:18:52.80#ibcon#read 6, iclass 30, count 0 2006.203.08:18:52.80#ibcon#end of sib2, iclass 30, count 0 2006.203.08:18:52.80#ibcon#*mode == 0, iclass 30, count 0 2006.203.08:18:52.80#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.203.08:18:52.80#ibcon#[27=USB\r\n] 2006.203.08:18:52.80#ibcon#*before write, iclass 30, count 0 2006.203.08:18:52.80#ibcon#enter sib2, iclass 30, count 0 2006.203.08:18:52.80#ibcon#flushed, iclass 30, count 0 2006.203.08:18:52.80#ibcon#about to write, iclass 30, count 0 2006.203.08:18:52.80#ibcon#wrote, iclass 30, count 0 2006.203.08:18:52.80#ibcon#about to read 3, iclass 30, count 0 2006.203.08:18:52.83#ibcon#read 3, iclass 30, count 0 2006.203.08:18:52.83#ibcon#about to read 4, iclass 30, count 0 2006.203.08:18:52.83#ibcon#read 4, iclass 30, count 0 2006.203.08:18:52.83#ibcon#about to read 5, iclass 30, count 0 2006.203.08:18:52.83#ibcon#read 5, iclass 30, count 0 2006.203.08:18:52.83#ibcon#about to read 6, iclass 30, count 0 2006.203.08:18:52.83#ibcon#read 6, iclass 30, count 0 2006.203.08:18:52.83#ibcon#end of sib2, iclass 30, count 0 2006.203.08:18:52.83#ibcon#*after write, iclass 30, count 0 2006.203.08:18:52.83#ibcon#*before return 0, iclass 30, count 0 2006.203.08:18:52.83#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.203.08:18:52.83#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.203.08:18:52.83#ibcon#about to clear, iclass 30 cls_cnt 0 2006.203.08:18:52.83#ibcon#cleared, iclass 30 cls_cnt 0 2006.203.08:18:52.83$vc4f8/vblo=4,712.99 2006.203.08:18:52.83#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.203.08:18:52.83#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.203.08:18:52.83#ibcon#ireg 17 cls_cnt 0 2006.203.08:18:52.83#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.203.08:18:52.83#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.203.08:18:52.83#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.203.08:18:52.83#ibcon#enter wrdev, iclass 32, count 0 2006.203.08:18:52.83#ibcon#first serial, iclass 32, count 0 2006.203.08:18:52.83#ibcon#enter sib2, iclass 32, count 0 2006.203.08:18:52.83#ibcon#flushed, iclass 32, count 0 2006.203.08:18:52.83#ibcon#about to write, iclass 32, count 0 2006.203.08:18:52.83#ibcon#wrote, iclass 32, count 0 2006.203.08:18:52.83#ibcon#about to read 3, iclass 32, count 0 2006.203.08:18:52.86#ibcon#read 3, iclass 32, count 0 2006.203.08:18:52.86#ibcon#about to read 4, iclass 32, count 0 2006.203.08:18:52.86#ibcon#read 4, iclass 32, count 0 2006.203.08:18:52.86#ibcon#about to read 5, iclass 32, count 0 2006.203.08:18:52.86#ibcon#read 5, iclass 32, count 0 2006.203.08:18:52.86#ibcon#about to read 6, iclass 32, count 0 2006.203.08:18:52.86#ibcon#read 6, iclass 32, count 0 2006.203.08:18:52.86#ibcon#end of sib2, iclass 32, count 0 2006.203.08:18:52.86#ibcon#*mode == 0, iclass 32, count 0 2006.203.08:18:52.86#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.203.08:18:52.86#ibcon#[28=FRQ=04,712.99\r\n] 2006.203.08:18:52.86#ibcon#*before write, iclass 32, count 0 2006.203.08:18:52.86#ibcon#enter sib2, iclass 32, count 0 2006.203.08:18:52.86#ibcon#flushed, iclass 32, count 0 2006.203.08:18:52.86#ibcon#about to write, iclass 32, count 0 2006.203.08:18:52.86#ibcon#wrote, iclass 32, count 0 2006.203.08:18:52.86#ibcon#about to read 3, iclass 32, count 0 2006.203.08:18:52.90#ibcon#read 3, iclass 32, count 0 2006.203.08:18:52.90#ibcon#about to read 4, iclass 32, count 0 2006.203.08:18:52.90#ibcon#read 4, iclass 32, count 0 2006.203.08:18:52.90#ibcon#about to read 5, iclass 32, count 0 2006.203.08:18:52.90#ibcon#read 5, iclass 32, count 0 2006.203.08:18:52.90#ibcon#about to read 6, iclass 32, count 0 2006.203.08:18:52.90#ibcon#read 6, iclass 32, count 0 2006.203.08:18:52.90#ibcon#end of sib2, iclass 32, count 0 2006.203.08:18:52.90#ibcon#*after write, iclass 32, count 0 2006.203.08:18:52.90#ibcon#*before return 0, iclass 32, count 0 2006.203.08:18:52.90#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.203.08:18:52.90#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.203.08:18:52.90#ibcon#about to clear, iclass 32 cls_cnt 0 2006.203.08:18:52.90#ibcon#cleared, iclass 32 cls_cnt 0 2006.203.08:18:52.90$vc4f8/vb=4,4 2006.203.08:18:52.90#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.203.08:18:52.90#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.203.08:18:52.90#ibcon#ireg 11 cls_cnt 2 2006.203.08:18:52.90#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.203.08:18:52.96#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.203.08:18:52.96#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.203.08:18:52.96#ibcon#enter wrdev, iclass 34, count 2 2006.203.08:18:52.96#ibcon#first serial, iclass 34, count 2 2006.203.08:18:52.96#ibcon#enter sib2, iclass 34, count 2 2006.203.08:18:52.96#ibcon#flushed, iclass 34, count 2 2006.203.08:18:52.96#ibcon#about to write, iclass 34, count 2 2006.203.08:18:52.96#ibcon#wrote, iclass 34, count 2 2006.203.08:18:52.96#ibcon#about to read 3, iclass 34, count 2 2006.203.08:18:52.97#ibcon#read 3, iclass 34, count 2 2006.203.08:18:52.97#ibcon#about to read 4, iclass 34, count 2 2006.203.08:18:52.97#ibcon#read 4, iclass 34, count 2 2006.203.08:18:52.97#ibcon#about to read 5, iclass 34, count 2 2006.203.08:18:52.97#ibcon#read 5, iclass 34, count 2 2006.203.08:18:52.97#ibcon#about to read 6, iclass 34, count 2 2006.203.08:18:52.97#ibcon#read 6, iclass 34, count 2 2006.203.08:18:52.97#ibcon#end of sib2, iclass 34, count 2 2006.203.08:18:52.97#ibcon#*mode == 0, iclass 34, count 2 2006.203.08:18:52.97#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.203.08:18:52.97#ibcon#[27=AT04-04\r\n] 2006.203.08:18:52.97#ibcon#*before write, iclass 34, count 2 2006.203.08:18:52.97#ibcon#enter sib2, iclass 34, count 2 2006.203.08:18:52.97#ibcon#flushed, iclass 34, count 2 2006.203.08:18:52.97#ibcon#about to write, iclass 34, count 2 2006.203.08:18:52.97#ibcon#wrote, iclass 34, count 2 2006.203.08:18:52.97#ibcon#about to read 3, iclass 34, count 2 2006.203.08:18:53.00#ibcon#read 3, iclass 34, count 2 2006.203.08:18:53.00#ibcon#about to read 4, iclass 34, count 2 2006.203.08:18:53.00#ibcon#read 4, iclass 34, count 2 2006.203.08:18:53.00#ibcon#about to read 5, iclass 34, count 2 2006.203.08:18:53.00#ibcon#read 5, iclass 34, count 2 2006.203.08:18:53.00#ibcon#about to read 6, iclass 34, count 2 2006.203.08:18:53.00#ibcon#read 6, iclass 34, count 2 2006.203.08:18:53.00#ibcon#end of sib2, iclass 34, count 2 2006.203.08:18:53.00#ibcon#*after write, iclass 34, count 2 2006.203.08:18:53.00#ibcon#*before return 0, iclass 34, count 2 2006.203.08:18:53.00#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.203.08:18:53.00#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.203.08:18:53.00#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.203.08:18:53.00#ibcon#ireg 7 cls_cnt 0 2006.203.08:18:53.00#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.203.08:18:53.12#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.203.08:18:53.12#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.203.08:18:53.12#ibcon#enter wrdev, iclass 34, count 0 2006.203.08:18:53.12#ibcon#first serial, iclass 34, count 0 2006.203.08:18:53.12#ibcon#enter sib2, iclass 34, count 0 2006.203.08:18:53.12#ibcon#flushed, iclass 34, count 0 2006.203.08:18:53.12#ibcon#about to write, iclass 34, count 0 2006.203.08:18:53.12#ibcon#wrote, iclass 34, count 0 2006.203.08:18:53.12#ibcon#about to read 3, iclass 34, count 0 2006.203.08:18:53.14#ibcon#read 3, iclass 34, count 0 2006.203.08:18:53.14#ibcon#about to read 4, iclass 34, count 0 2006.203.08:18:53.14#ibcon#read 4, iclass 34, count 0 2006.203.08:18:53.14#ibcon#about to read 5, iclass 34, count 0 2006.203.08:18:53.14#ibcon#read 5, iclass 34, count 0 2006.203.08:18:53.14#ibcon#about to read 6, iclass 34, count 0 2006.203.08:18:53.14#ibcon#read 6, iclass 34, count 0 2006.203.08:18:53.14#ibcon#end of sib2, iclass 34, count 0 2006.203.08:18:53.14#ibcon#*mode == 0, iclass 34, count 0 2006.203.08:18:53.14#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.203.08:18:53.14#ibcon#[27=USB\r\n] 2006.203.08:18:53.14#ibcon#*before write, iclass 34, count 0 2006.203.08:18:53.14#ibcon#enter sib2, iclass 34, count 0 2006.203.08:18:53.14#ibcon#flushed, iclass 34, count 0 2006.203.08:18:53.14#ibcon#about to write, iclass 34, count 0 2006.203.08:18:53.14#ibcon#wrote, iclass 34, count 0 2006.203.08:18:53.14#ibcon#about to read 3, iclass 34, count 0 2006.203.08:18:53.17#ibcon#read 3, iclass 34, count 0 2006.203.08:18:53.17#ibcon#about to read 4, iclass 34, count 0 2006.203.08:18:53.17#ibcon#read 4, iclass 34, count 0 2006.203.08:18:53.17#ibcon#about to read 5, iclass 34, count 0 2006.203.08:18:53.17#ibcon#read 5, iclass 34, count 0 2006.203.08:18:53.17#ibcon#about to read 6, iclass 34, count 0 2006.203.08:18:53.17#ibcon#read 6, iclass 34, count 0 2006.203.08:18:53.17#ibcon#end of sib2, iclass 34, count 0 2006.203.08:18:53.17#ibcon#*after write, iclass 34, count 0 2006.203.08:18:53.17#ibcon#*before return 0, iclass 34, count 0 2006.203.08:18:53.17#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.203.08:18:53.17#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.203.08:18:53.17#ibcon#about to clear, iclass 34 cls_cnt 0 2006.203.08:18:53.17#ibcon#cleared, iclass 34 cls_cnt 0 2006.203.08:18:53.17$vc4f8/vblo=5,744.99 2006.203.08:18:53.17#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.203.08:18:53.17#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.203.08:18:53.17#ibcon#ireg 17 cls_cnt 0 2006.203.08:18:53.17#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.203.08:18:53.17#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.203.08:18:53.17#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.203.08:18:53.17#ibcon#enter wrdev, iclass 36, count 0 2006.203.08:18:53.17#ibcon#first serial, iclass 36, count 0 2006.203.08:18:53.17#ibcon#enter sib2, iclass 36, count 0 2006.203.08:18:53.17#ibcon#flushed, iclass 36, count 0 2006.203.08:18:53.17#ibcon#about to write, iclass 36, count 0 2006.203.08:18:53.17#ibcon#wrote, iclass 36, count 0 2006.203.08:18:53.17#ibcon#about to read 3, iclass 36, count 0 2006.203.08:18:53.19#ibcon#read 3, iclass 36, count 0 2006.203.08:18:53.19#ibcon#about to read 4, iclass 36, count 0 2006.203.08:18:53.19#ibcon#read 4, iclass 36, count 0 2006.203.08:18:53.19#ibcon#about to read 5, iclass 36, count 0 2006.203.08:18:53.19#ibcon#read 5, iclass 36, count 0 2006.203.08:18:53.19#ibcon#about to read 6, iclass 36, count 0 2006.203.08:18:53.19#ibcon#read 6, iclass 36, count 0 2006.203.08:18:53.19#ibcon#end of sib2, iclass 36, count 0 2006.203.08:18:53.19#ibcon#*mode == 0, iclass 36, count 0 2006.203.08:18:53.19#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.203.08:18:53.19#ibcon#[28=FRQ=05,744.99\r\n] 2006.203.08:18:53.19#ibcon#*before write, iclass 36, count 0 2006.203.08:18:53.19#ibcon#enter sib2, iclass 36, count 0 2006.203.08:18:53.19#ibcon#flushed, iclass 36, count 0 2006.203.08:18:53.19#ibcon#about to write, iclass 36, count 0 2006.203.08:18:53.19#ibcon#wrote, iclass 36, count 0 2006.203.08:18:53.19#ibcon#about to read 3, iclass 36, count 0 2006.203.08:18:53.23#ibcon#read 3, iclass 36, count 0 2006.203.08:18:53.23#ibcon#about to read 4, iclass 36, count 0 2006.203.08:18:53.23#ibcon#read 4, iclass 36, count 0 2006.203.08:18:53.23#ibcon#about to read 5, iclass 36, count 0 2006.203.08:18:53.23#ibcon#read 5, iclass 36, count 0 2006.203.08:18:53.23#ibcon#about to read 6, iclass 36, count 0 2006.203.08:18:53.23#ibcon#read 6, iclass 36, count 0 2006.203.08:18:53.23#ibcon#end of sib2, iclass 36, count 0 2006.203.08:18:53.23#ibcon#*after write, iclass 36, count 0 2006.203.08:18:53.23#ibcon#*before return 0, iclass 36, count 0 2006.203.08:18:53.23#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.203.08:18:53.23#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.203.08:18:53.23#ibcon#about to clear, iclass 36 cls_cnt 0 2006.203.08:18:53.23#ibcon#cleared, iclass 36 cls_cnt 0 2006.203.08:18:53.23$vc4f8/vb=5,3 2006.203.08:18:53.23#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.203.08:18:53.23#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.203.08:18:53.23#ibcon#ireg 11 cls_cnt 2 2006.203.08:18:53.23#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.203.08:18:53.29#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.203.08:18:53.29#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.203.08:18:53.29#ibcon#enter wrdev, iclass 38, count 2 2006.203.08:18:53.29#ibcon#first serial, iclass 38, count 2 2006.203.08:18:53.29#ibcon#enter sib2, iclass 38, count 2 2006.203.08:18:53.29#ibcon#flushed, iclass 38, count 2 2006.203.08:18:53.29#ibcon#about to write, iclass 38, count 2 2006.203.08:18:53.29#ibcon#wrote, iclass 38, count 2 2006.203.08:18:53.29#ibcon#about to read 3, iclass 38, count 2 2006.203.08:18:53.31#ibcon#read 3, iclass 38, count 2 2006.203.08:18:53.31#ibcon#about to read 4, iclass 38, count 2 2006.203.08:18:53.31#ibcon#read 4, iclass 38, count 2 2006.203.08:18:53.31#ibcon#about to read 5, iclass 38, count 2 2006.203.08:18:53.31#ibcon#read 5, iclass 38, count 2 2006.203.08:18:53.31#ibcon#about to read 6, iclass 38, count 2 2006.203.08:18:53.31#ibcon#read 6, iclass 38, count 2 2006.203.08:18:53.31#ibcon#end of sib2, iclass 38, count 2 2006.203.08:18:53.31#ibcon#*mode == 0, iclass 38, count 2 2006.203.08:18:53.31#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.203.08:18:53.31#ibcon#[27=AT05-03\r\n] 2006.203.08:18:53.31#ibcon#*before write, iclass 38, count 2 2006.203.08:18:53.31#ibcon#enter sib2, iclass 38, count 2 2006.203.08:18:53.31#ibcon#flushed, iclass 38, count 2 2006.203.08:18:53.31#ibcon#about to write, iclass 38, count 2 2006.203.08:18:53.31#ibcon#wrote, iclass 38, count 2 2006.203.08:18:53.31#ibcon#about to read 3, iclass 38, count 2 2006.203.08:18:53.34#ibcon#read 3, iclass 38, count 2 2006.203.08:18:53.34#ibcon#about to read 4, iclass 38, count 2 2006.203.08:18:53.34#ibcon#read 4, iclass 38, count 2 2006.203.08:18:53.34#ibcon#about to read 5, iclass 38, count 2 2006.203.08:18:53.34#ibcon#read 5, iclass 38, count 2 2006.203.08:18:53.34#ibcon#about to read 6, iclass 38, count 2 2006.203.08:18:53.34#ibcon#read 6, iclass 38, count 2 2006.203.08:18:53.34#ibcon#end of sib2, iclass 38, count 2 2006.203.08:18:53.34#ibcon#*after write, iclass 38, count 2 2006.203.08:18:53.34#ibcon#*before return 0, iclass 38, count 2 2006.203.08:18:53.34#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.203.08:18:53.34#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.203.08:18:53.34#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.203.08:18:53.34#ibcon#ireg 7 cls_cnt 0 2006.203.08:18:53.34#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.203.08:18:53.46#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.203.08:18:53.46#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.203.08:18:53.46#ibcon#enter wrdev, iclass 38, count 0 2006.203.08:18:53.46#ibcon#first serial, iclass 38, count 0 2006.203.08:18:53.46#ibcon#enter sib2, iclass 38, count 0 2006.203.08:18:53.46#ibcon#flushed, iclass 38, count 0 2006.203.08:18:53.46#ibcon#about to write, iclass 38, count 0 2006.203.08:18:53.46#ibcon#wrote, iclass 38, count 0 2006.203.08:18:53.46#ibcon#about to read 3, iclass 38, count 0 2006.203.08:18:53.48#ibcon#read 3, iclass 38, count 0 2006.203.08:18:53.48#ibcon#about to read 4, iclass 38, count 0 2006.203.08:18:53.48#ibcon#read 4, iclass 38, count 0 2006.203.08:18:53.48#ibcon#about to read 5, iclass 38, count 0 2006.203.08:18:53.48#ibcon#read 5, iclass 38, count 0 2006.203.08:18:53.48#ibcon#about to read 6, iclass 38, count 0 2006.203.08:18:53.48#ibcon#read 6, iclass 38, count 0 2006.203.08:18:53.48#ibcon#end of sib2, iclass 38, count 0 2006.203.08:18:53.48#ibcon#*mode == 0, iclass 38, count 0 2006.203.08:18:53.48#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.203.08:18:53.48#ibcon#[27=USB\r\n] 2006.203.08:18:53.48#ibcon#*before write, iclass 38, count 0 2006.203.08:18:53.48#ibcon#enter sib2, iclass 38, count 0 2006.203.08:18:53.48#ibcon#flushed, iclass 38, count 0 2006.203.08:18:53.48#ibcon#about to write, iclass 38, count 0 2006.203.08:18:53.48#ibcon#wrote, iclass 38, count 0 2006.203.08:18:53.48#ibcon#about to read 3, iclass 38, count 0 2006.203.08:18:53.51#ibcon#read 3, iclass 38, count 0 2006.203.08:18:53.51#ibcon#about to read 4, iclass 38, count 0 2006.203.08:18:53.51#ibcon#read 4, iclass 38, count 0 2006.203.08:18:53.51#ibcon#about to read 5, iclass 38, count 0 2006.203.08:18:53.51#ibcon#read 5, iclass 38, count 0 2006.203.08:18:53.51#ibcon#about to read 6, iclass 38, count 0 2006.203.08:18:53.51#ibcon#read 6, iclass 38, count 0 2006.203.08:18:53.51#ibcon#end of sib2, iclass 38, count 0 2006.203.08:18:53.51#ibcon#*after write, iclass 38, count 0 2006.203.08:18:53.51#ibcon#*before return 0, iclass 38, count 0 2006.203.08:18:53.51#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.203.08:18:53.51#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.203.08:18:53.51#ibcon#about to clear, iclass 38 cls_cnt 0 2006.203.08:18:53.51#ibcon#cleared, iclass 38 cls_cnt 0 2006.203.08:18:53.51$vc4f8/vblo=6,752.99 2006.203.08:18:53.51#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.203.08:18:53.51#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.203.08:18:53.51#ibcon#ireg 17 cls_cnt 0 2006.203.08:18:53.51#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.203.08:18:53.51#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.203.08:18:53.51#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.203.08:18:53.51#ibcon#enter wrdev, iclass 40, count 0 2006.203.08:18:53.51#ibcon#first serial, iclass 40, count 0 2006.203.08:18:53.51#ibcon#enter sib2, iclass 40, count 0 2006.203.08:18:53.51#ibcon#flushed, iclass 40, count 0 2006.203.08:18:53.51#ibcon#about to write, iclass 40, count 0 2006.203.08:18:53.51#ibcon#wrote, iclass 40, count 0 2006.203.08:18:53.51#ibcon#about to read 3, iclass 40, count 0 2006.203.08:18:53.53#ibcon#read 3, iclass 40, count 0 2006.203.08:18:53.53#ibcon#about to read 4, iclass 40, count 0 2006.203.08:18:53.53#ibcon#read 4, iclass 40, count 0 2006.203.08:18:53.53#ibcon#about to read 5, iclass 40, count 0 2006.203.08:18:53.53#ibcon#read 5, iclass 40, count 0 2006.203.08:18:53.53#ibcon#about to read 6, iclass 40, count 0 2006.203.08:18:53.53#ibcon#read 6, iclass 40, count 0 2006.203.08:18:53.53#ibcon#end of sib2, iclass 40, count 0 2006.203.08:18:53.53#ibcon#*mode == 0, iclass 40, count 0 2006.203.08:18:53.53#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.203.08:18:53.53#ibcon#[28=FRQ=06,752.99\r\n] 2006.203.08:18:53.53#ibcon#*before write, iclass 40, count 0 2006.203.08:18:53.53#ibcon#enter sib2, iclass 40, count 0 2006.203.08:18:53.53#ibcon#flushed, iclass 40, count 0 2006.203.08:18:53.53#ibcon#about to write, iclass 40, count 0 2006.203.08:18:53.53#ibcon#wrote, iclass 40, count 0 2006.203.08:18:53.53#ibcon#about to read 3, iclass 40, count 0 2006.203.08:18:53.57#ibcon#read 3, iclass 40, count 0 2006.203.08:18:53.57#ibcon#about to read 4, iclass 40, count 0 2006.203.08:18:53.57#ibcon#read 4, iclass 40, count 0 2006.203.08:18:53.57#ibcon#about to read 5, iclass 40, count 0 2006.203.08:18:53.57#ibcon#read 5, iclass 40, count 0 2006.203.08:18:53.57#ibcon#about to read 6, iclass 40, count 0 2006.203.08:18:53.57#ibcon#read 6, iclass 40, count 0 2006.203.08:18:53.57#ibcon#end of sib2, iclass 40, count 0 2006.203.08:18:53.57#ibcon#*after write, iclass 40, count 0 2006.203.08:18:53.57#ibcon#*before return 0, iclass 40, count 0 2006.203.08:18:53.57#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.203.08:18:53.57#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.203.08:18:53.57#ibcon#about to clear, iclass 40 cls_cnt 0 2006.203.08:18:53.57#ibcon#cleared, iclass 40 cls_cnt 0 2006.203.08:18:53.57$vc4f8/vb=6,4 2006.203.08:18:53.57#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.203.08:18:53.57#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.203.08:18:53.57#ibcon#ireg 11 cls_cnt 2 2006.203.08:18:53.57#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.203.08:18:53.63#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.203.08:18:53.63#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.203.08:18:53.64#ibcon#enter wrdev, iclass 4, count 2 2006.203.08:18:53.64#ibcon#first serial, iclass 4, count 2 2006.203.08:18:53.64#ibcon#enter sib2, iclass 4, count 2 2006.203.08:18:53.64#ibcon#flushed, iclass 4, count 2 2006.203.08:18:53.64#ibcon#about to write, iclass 4, count 2 2006.203.08:18:53.64#ibcon#wrote, iclass 4, count 2 2006.203.08:18:53.64#ibcon#about to read 3, iclass 4, count 2 2006.203.08:18:53.65#ibcon#read 3, iclass 4, count 2 2006.203.08:18:53.65#ibcon#about to read 4, iclass 4, count 2 2006.203.08:18:53.65#ibcon#read 4, iclass 4, count 2 2006.203.08:18:53.65#ibcon#about to read 5, iclass 4, count 2 2006.203.08:18:53.65#ibcon#read 5, iclass 4, count 2 2006.203.08:18:53.65#ibcon#about to read 6, iclass 4, count 2 2006.203.08:18:53.65#ibcon#read 6, iclass 4, count 2 2006.203.08:18:53.65#ibcon#end of sib2, iclass 4, count 2 2006.203.08:18:53.65#ibcon#*mode == 0, iclass 4, count 2 2006.203.08:18:53.65#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.203.08:18:53.65#ibcon#[27=AT06-04\r\n] 2006.203.08:18:53.65#ibcon#*before write, iclass 4, count 2 2006.203.08:18:53.65#ibcon#enter sib2, iclass 4, count 2 2006.203.08:18:53.65#ibcon#flushed, iclass 4, count 2 2006.203.08:18:53.65#ibcon#about to write, iclass 4, count 2 2006.203.08:18:53.65#ibcon#wrote, iclass 4, count 2 2006.203.08:18:53.65#ibcon#about to read 3, iclass 4, count 2 2006.203.08:18:53.68#ibcon#read 3, iclass 4, count 2 2006.203.08:18:53.68#ibcon#about to read 4, iclass 4, count 2 2006.203.08:18:53.68#ibcon#read 4, iclass 4, count 2 2006.203.08:18:53.68#ibcon#about to read 5, iclass 4, count 2 2006.203.08:18:53.68#ibcon#read 5, iclass 4, count 2 2006.203.08:18:53.68#ibcon#about to read 6, iclass 4, count 2 2006.203.08:18:53.68#ibcon#read 6, iclass 4, count 2 2006.203.08:18:53.68#ibcon#end of sib2, iclass 4, count 2 2006.203.08:18:53.68#ibcon#*after write, iclass 4, count 2 2006.203.08:18:53.68#ibcon#*before return 0, iclass 4, count 2 2006.203.08:18:53.68#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.203.08:18:53.68#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.203.08:18:53.68#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.203.08:18:53.68#ibcon#ireg 7 cls_cnt 0 2006.203.08:18:53.68#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.203.08:18:53.80#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.203.08:18:53.80#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.203.08:18:53.80#ibcon#enter wrdev, iclass 4, count 0 2006.203.08:18:53.80#ibcon#first serial, iclass 4, count 0 2006.203.08:18:53.80#ibcon#enter sib2, iclass 4, count 0 2006.203.08:18:53.80#ibcon#flushed, iclass 4, count 0 2006.203.08:18:53.80#ibcon#about to write, iclass 4, count 0 2006.203.08:18:53.80#ibcon#wrote, iclass 4, count 0 2006.203.08:18:53.80#ibcon#about to read 3, iclass 4, count 0 2006.203.08:18:53.82#ibcon#read 3, iclass 4, count 0 2006.203.08:18:53.82#ibcon#about to read 4, iclass 4, count 0 2006.203.08:18:53.82#ibcon#read 4, iclass 4, count 0 2006.203.08:18:53.82#ibcon#about to read 5, iclass 4, count 0 2006.203.08:18:53.82#ibcon#read 5, iclass 4, count 0 2006.203.08:18:53.82#ibcon#about to read 6, iclass 4, count 0 2006.203.08:18:53.82#ibcon#read 6, iclass 4, count 0 2006.203.08:18:53.82#ibcon#end of sib2, iclass 4, count 0 2006.203.08:18:53.82#ibcon#*mode == 0, iclass 4, count 0 2006.203.08:18:53.82#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.203.08:18:53.82#ibcon#[27=USB\r\n] 2006.203.08:18:53.82#ibcon#*before write, iclass 4, count 0 2006.203.08:18:53.82#ibcon#enter sib2, iclass 4, count 0 2006.203.08:18:53.82#ibcon#flushed, iclass 4, count 0 2006.203.08:18:53.82#ibcon#about to write, iclass 4, count 0 2006.203.08:18:53.82#ibcon#wrote, iclass 4, count 0 2006.203.08:18:53.82#ibcon#about to read 3, iclass 4, count 0 2006.203.08:18:53.85#ibcon#read 3, iclass 4, count 0 2006.203.08:18:53.85#ibcon#about to read 4, iclass 4, count 0 2006.203.08:18:53.85#ibcon#read 4, iclass 4, count 0 2006.203.08:18:53.85#ibcon#about to read 5, iclass 4, count 0 2006.203.08:18:53.85#ibcon#read 5, iclass 4, count 0 2006.203.08:18:53.85#ibcon#about to read 6, iclass 4, count 0 2006.203.08:18:53.85#ibcon#read 6, iclass 4, count 0 2006.203.08:18:53.85#ibcon#end of sib2, iclass 4, count 0 2006.203.08:18:53.85#ibcon#*after write, iclass 4, count 0 2006.203.08:18:53.85#ibcon#*before return 0, iclass 4, count 0 2006.203.08:18:53.85#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.203.08:18:53.85#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.203.08:18:53.85#ibcon#about to clear, iclass 4 cls_cnt 0 2006.203.08:18:53.85#ibcon#cleared, iclass 4 cls_cnt 0 2006.203.08:18:53.85$vc4f8/vabw=wide 2006.203.08:18:53.85#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.203.08:18:53.85#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.203.08:18:53.85#ibcon#ireg 8 cls_cnt 0 2006.203.08:18:53.85#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.203.08:18:53.85#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.203.08:18:53.85#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.203.08:18:53.85#ibcon#enter wrdev, iclass 6, count 0 2006.203.08:18:53.85#ibcon#first serial, iclass 6, count 0 2006.203.08:18:53.85#ibcon#enter sib2, iclass 6, count 0 2006.203.08:18:53.85#ibcon#flushed, iclass 6, count 0 2006.203.08:18:53.85#ibcon#about to write, iclass 6, count 0 2006.203.08:18:53.85#ibcon#wrote, iclass 6, count 0 2006.203.08:18:53.85#ibcon#about to read 3, iclass 6, count 0 2006.203.08:18:53.87#ibcon#read 3, iclass 6, count 0 2006.203.08:18:53.87#ibcon#about to read 4, iclass 6, count 0 2006.203.08:18:53.87#ibcon#read 4, iclass 6, count 0 2006.203.08:18:53.87#ibcon#about to read 5, iclass 6, count 0 2006.203.08:18:53.87#ibcon#read 5, iclass 6, count 0 2006.203.08:18:53.87#ibcon#about to read 6, iclass 6, count 0 2006.203.08:18:53.87#ibcon#read 6, iclass 6, count 0 2006.203.08:18:53.87#ibcon#end of sib2, iclass 6, count 0 2006.203.08:18:53.87#ibcon#*mode == 0, iclass 6, count 0 2006.203.08:18:53.87#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.203.08:18:53.87#ibcon#[25=BW32\r\n] 2006.203.08:18:53.87#ibcon#*before write, iclass 6, count 0 2006.203.08:18:53.87#ibcon#enter sib2, iclass 6, count 0 2006.203.08:18:53.87#ibcon#flushed, iclass 6, count 0 2006.203.08:18:53.87#ibcon#about to write, iclass 6, count 0 2006.203.08:18:53.87#ibcon#wrote, iclass 6, count 0 2006.203.08:18:53.87#ibcon#about to read 3, iclass 6, count 0 2006.203.08:18:53.90#ibcon#read 3, iclass 6, count 0 2006.203.08:18:53.90#ibcon#about to read 4, iclass 6, count 0 2006.203.08:18:53.90#ibcon#read 4, iclass 6, count 0 2006.203.08:18:53.90#ibcon#about to read 5, iclass 6, count 0 2006.203.08:18:53.90#ibcon#read 5, iclass 6, count 0 2006.203.08:18:53.90#ibcon#about to read 6, iclass 6, count 0 2006.203.08:18:53.90#ibcon#read 6, iclass 6, count 0 2006.203.08:18:53.90#ibcon#end of sib2, iclass 6, count 0 2006.203.08:18:53.90#ibcon#*after write, iclass 6, count 0 2006.203.08:18:53.90#ibcon#*before return 0, iclass 6, count 0 2006.203.08:18:53.90#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.203.08:18:53.90#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.203.08:18:53.90#ibcon#about to clear, iclass 6 cls_cnt 0 2006.203.08:18:53.90#ibcon#cleared, iclass 6 cls_cnt 0 2006.203.08:18:53.90$vc4f8/vbbw=wide 2006.203.08:18:53.90#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.203.08:18:53.90#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.203.08:18:53.90#ibcon#ireg 8 cls_cnt 0 2006.203.08:18:53.90#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.203.08:18:53.97#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.203.08:18:53.97#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.203.08:18:53.97#ibcon#enter wrdev, iclass 10, count 0 2006.203.08:18:53.97#ibcon#first serial, iclass 10, count 0 2006.203.08:18:53.97#ibcon#enter sib2, iclass 10, count 0 2006.203.08:18:53.97#ibcon#flushed, iclass 10, count 0 2006.203.08:18:53.97#ibcon#about to write, iclass 10, count 0 2006.203.08:18:53.97#ibcon#wrote, iclass 10, count 0 2006.203.08:18:53.97#ibcon#about to read 3, iclass 10, count 0 2006.203.08:18:53.99#ibcon#read 3, iclass 10, count 0 2006.203.08:18:53.99#ibcon#about to read 4, iclass 10, count 0 2006.203.08:18:53.99#ibcon#read 4, iclass 10, count 0 2006.203.08:18:53.99#ibcon#about to read 5, iclass 10, count 0 2006.203.08:18:53.99#ibcon#read 5, iclass 10, count 0 2006.203.08:18:53.99#ibcon#about to read 6, iclass 10, count 0 2006.203.08:18:53.99#ibcon#read 6, iclass 10, count 0 2006.203.08:18:53.99#ibcon#end of sib2, iclass 10, count 0 2006.203.08:18:53.99#ibcon#*mode == 0, iclass 10, count 0 2006.203.08:18:53.99#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.203.08:18:53.99#ibcon#[27=BW32\r\n] 2006.203.08:18:53.99#ibcon#*before write, iclass 10, count 0 2006.203.08:18:53.99#ibcon#enter sib2, iclass 10, count 0 2006.203.08:18:53.99#ibcon#flushed, iclass 10, count 0 2006.203.08:18:53.99#ibcon#about to write, iclass 10, count 0 2006.203.08:18:53.99#ibcon#wrote, iclass 10, count 0 2006.203.08:18:53.99#ibcon#about to read 3, iclass 10, count 0 2006.203.08:18:54.02#ibcon#read 3, iclass 10, count 0 2006.203.08:18:54.02#ibcon#about to read 4, iclass 10, count 0 2006.203.08:18:54.02#ibcon#read 4, iclass 10, count 0 2006.203.08:18:54.02#ibcon#about to read 5, iclass 10, count 0 2006.203.08:18:54.02#ibcon#read 5, iclass 10, count 0 2006.203.08:18:54.02#ibcon#about to read 6, iclass 10, count 0 2006.203.08:18:54.02#ibcon#read 6, iclass 10, count 0 2006.203.08:18:54.02#ibcon#end of sib2, iclass 10, count 0 2006.203.08:18:54.02#ibcon#*after write, iclass 10, count 0 2006.203.08:18:54.02#ibcon#*before return 0, iclass 10, count 0 2006.203.08:18:54.02#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.203.08:18:54.02#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.203.08:18:54.02#ibcon#about to clear, iclass 10 cls_cnt 0 2006.203.08:18:54.02#ibcon#cleared, iclass 10 cls_cnt 0 2006.203.08:18:54.02$4f8m12a/ifd4f 2006.203.08:18:54.02$ifd4f/lo= 2006.203.08:18:54.02$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.203.08:18:54.02$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.203.08:18:54.02$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.203.08:18:54.02$ifd4f/patch= 2006.203.08:18:54.02$ifd4f/patch=lo1,a1,a2,a3,a4 2006.203.08:18:54.02$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.203.08:18:54.02$ifd4f/patch=lo3,a5,a6,a7,a8 2006.203.08:18:54.03$4f8m12a/"form=m,16.000,1:2 2006.203.08:18:54.03$4f8m12a/"tpicd 2006.203.08:18:54.03$4f8m12a/echo=off 2006.203.08:18:54.03$4f8m12a/xlog=off 2006.203.08:18:54.03:!2006.203.08:20:30 2006.203.08:19:27.14#trakl#Source acquired 2006.203.08:19:29.14#flagr#flagr/antenna,acquired 2006.203.08:20:30.01:preob 2006.203.08:20:31.14/onsource/TRACKING 2006.203.08:20:31.14:!2006.203.08:20:40 2006.203.08:20:40.00:data_valid=on 2006.203.08:20:40.00:midob 2006.203.08:20:40.13/onsource/TRACKING 2006.203.08:20:40.13/wx/23.55,1001.1,100 2006.203.08:20:40.29/cable/+6.4609E-03 2006.203.08:20:41.38/va/01,08,usb,yes,31,32 2006.203.08:20:41.38/va/02,07,usb,yes,31,32 2006.203.08:20:41.38/va/03,08,usb,yes,23,23 2006.203.08:20:41.38/va/04,07,usb,yes,32,34 2006.203.08:20:41.38/va/05,07,usb,yes,35,37 2006.203.08:20:41.38/va/06,06,usb,yes,34,34 2006.203.08:20:41.38/va/07,07,usb,yes,30,30 2006.203.08:20:41.38/va/08,06,usb,yes,37,36 2006.203.08:20:41.61/valo/01,532.99,yes,locked 2006.203.08:20:41.61/valo/02,572.99,yes,locked 2006.203.08:20:41.61/valo/03,672.99,yes,locked 2006.203.08:20:41.61/valo/04,832.99,yes,locked 2006.203.08:20:41.61/valo/05,652.99,yes,locked 2006.203.08:20:41.61/valo/06,772.99,yes,locked 2006.203.08:20:41.61/valo/07,832.99,yes,locked 2006.203.08:20:41.61/valo/08,852.99,yes,locked 2006.203.08:20:42.70/vb/01,04,usb,yes,29,28 2006.203.08:20:42.70/vb/02,04,usb,yes,31,33 2006.203.08:20:42.70/vb/03,04,usb,yes,28,31 2006.203.08:20:42.70/vb/04,04,usb,yes,29,29 2006.203.08:20:42.70/vb/05,03,usb,yes,34,38 2006.203.08:20:42.70/vb/06,04,usb,yes,28,31 2006.203.08:20:42.70/vb/07,04,usb,yes,30,30 2006.203.08:20:42.70/vb/08,04,usb,yes,28,31 2006.203.08:20:42.93/vblo/01,632.99,yes,locked 2006.203.08:20:42.93/vblo/02,640.99,yes,locked 2006.203.08:20:42.93/vblo/03,656.99,yes,locked 2006.203.08:20:42.93/vblo/04,712.99,yes,locked 2006.203.08:20:42.93/vblo/05,744.99,yes,locked 2006.203.08:20:42.93/vblo/06,752.99,yes,locked 2006.203.08:20:42.93/vblo/07,734.99,yes,locked 2006.203.08:20:42.93/vblo/08,744.99,yes,locked 2006.203.08:20:43.08/vabw/8 2006.203.08:20:43.23/vbbw/8 2006.203.08:20:43.32/xfe/off,on,12.2 2006.203.08:20:43.72/ifatt/23,28,28,28 2006.203.08:20:44.07/fmout-gps/S +4.57E-07 2006.203.08:20:44.15:!2006.203.08:21:40 2006.203.08:21:40.00:data_valid=off 2006.203.08:21:40.01:postob 2006.203.08:21:40.17/cable/+6.4586E-03 2006.203.08:21:40.21/wx/23.56,1001.1,100 2006.203.08:21:41.07/fmout-gps/S +4.57E-07 2006.203.08:21:41.08:scan_name=203-0824,k06203,60 2006.203.08:21:41.08:source=0823+033,082550.34,030924.5,2000.0,ccw 2006.203.08:21:42.13#flagr#flagr/antenna,new-source 2006.203.08:21:42.14:checkk5 2006.203.08:21:42.75/chk_autoobs//k5ts1/ autoobs is running! 2006.203.08:21:43.18/chk_autoobs//k5ts2/ autoobs is running! 2006.203.08:21:43.56/chk_autoobs//k5ts3/ autoobs is running! 2006.203.08:21:43.95/chk_autoobs//k5ts4/ autoobs is running! 2006.203.08:21:44.41/chk_obsdata//k5ts1/T2030820??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.08:21:44.81/chk_obsdata//k5ts2/T2030820??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.08:21:45.22/chk_obsdata//k5ts3/T2030820??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.08:21:45.63/chk_obsdata//k5ts4/T2030820??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.08:21:46.47/k5log//k5ts1_log_newline 2006.203.08:21:47.48/k5log//k5ts2_log_newline 2006.203.08:21:48.24/k5log//k5ts3_log_newline 2006.203.08:21:48.99/k5log//k5ts4_log_newline 2006.203.08:21:49.01/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.203.08:21:49.02:4f8m12a=3 2006.203.08:21:49.02$4f8m12a/echo=on 2006.203.08:21:49.02$4f8m12a/pcalon 2006.203.08:21:49.02$pcalon/"no phase cal control is implemented here 2006.203.08:21:49.02$4f8m12a/"tpicd=stop 2006.203.08:21:49.02$4f8m12a/vc4f8 2006.203.08:21:49.02$vc4f8/valo=1,532.99 2006.203.08:21:49.02#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.203.08:21:49.02#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.203.08:21:49.02#ibcon#ireg 17 cls_cnt 0 2006.203.08:21:49.02#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.203.08:21:49.02#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.203.08:21:49.02#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.203.08:21:49.02#ibcon#enter wrdev, iclass 7, count 0 2006.203.08:21:49.02#ibcon#first serial, iclass 7, count 0 2006.203.08:21:49.02#ibcon#enter sib2, iclass 7, count 0 2006.203.08:21:49.02#ibcon#flushed, iclass 7, count 0 2006.203.08:21:49.02#ibcon#about to write, iclass 7, count 0 2006.203.08:21:49.02#ibcon#wrote, iclass 7, count 0 2006.203.08:21:49.02#ibcon#about to read 3, iclass 7, count 0 2006.203.08:21:49.06#ibcon#read 3, iclass 7, count 0 2006.203.08:21:49.06#ibcon#about to read 4, iclass 7, count 0 2006.203.08:21:49.06#ibcon#read 4, iclass 7, count 0 2006.203.08:21:49.06#ibcon#about to read 5, iclass 7, count 0 2006.203.08:21:49.06#ibcon#read 5, iclass 7, count 0 2006.203.08:21:49.06#ibcon#about to read 6, iclass 7, count 0 2006.203.08:21:49.06#ibcon#read 6, iclass 7, count 0 2006.203.08:21:49.06#ibcon#end of sib2, iclass 7, count 0 2006.203.08:21:49.06#ibcon#*mode == 0, iclass 7, count 0 2006.203.08:21:49.06#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.203.08:21:49.06#ibcon#[26=FRQ=01,532.99\r\n] 2006.203.08:21:49.06#ibcon#*before write, iclass 7, count 0 2006.203.08:21:49.06#ibcon#enter sib2, iclass 7, count 0 2006.203.08:21:49.06#ibcon#flushed, iclass 7, count 0 2006.203.08:21:49.06#ibcon#about to write, iclass 7, count 0 2006.203.08:21:49.06#ibcon#wrote, iclass 7, count 0 2006.203.08:21:49.06#ibcon#about to read 3, iclass 7, count 0 2006.203.08:21:49.10#ibcon#read 3, iclass 7, count 0 2006.203.08:21:49.10#ibcon#about to read 4, iclass 7, count 0 2006.203.08:21:49.10#ibcon#read 4, iclass 7, count 0 2006.203.08:21:49.10#ibcon#about to read 5, iclass 7, count 0 2006.203.08:21:49.10#ibcon#read 5, iclass 7, count 0 2006.203.08:21:49.10#ibcon#about to read 6, iclass 7, count 0 2006.203.08:21:49.10#ibcon#read 6, iclass 7, count 0 2006.203.08:21:49.10#ibcon#end of sib2, iclass 7, count 0 2006.203.08:21:49.10#ibcon#*after write, iclass 7, count 0 2006.203.08:21:49.10#ibcon#*before return 0, iclass 7, count 0 2006.203.08:21:49.10#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.203.08:21:49.10#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.203.08:21:49.10#ibcon#about to clear, iclass 7 cls_cnt 0 2006.203.08:21:49.10#ibcon#cleared, iclass 7 cls_cnt 0 2006.203.08:21:49.10$vc4f8/va=1,8 2006.203.08:21:49.10#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.203.08:21:49.10#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.203.08:21:49.10#ibcon#ireg 11 cls_cnt 2 2006.203.08:21:49.10#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.203.08:21:49.10#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.203.08:21:49.10#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.203.08:21:49.10#ibcon#enter wrdev, iclass 11, count 2 2006.203.08:21:49.10#ibcon#first serial, iclass 11, count 2 2006.203.08:21:49.10#ibcon#enter sib2, iclass 11, count 2 2006.203.08:21:49.10#ibcon#flushed, iclass 11, count 2 2006.203.08:21:49.10#ibcon#about to write, iclass 11, count 2 2006.203.08:21:49.10#ibcon#wrote, iclass 11, count 2 2006.203.08:21:49.10#ibcon#about to read 3, iclass 11, count 2 2006.203.08:21:49.13#ibcon#read 3, iclass 11, count 2 2006.203.08:21:49.13#ibcon#about to read 4, iclass 11, count 2 2006.203.08:21:49.13#ibcon#read 4, iclass 11, count 2 2006.203.08:21:49.13#ibcon#about to read 5, iclass 11, count 2 2006.203.08:21:49.13#ibcon#read 5, iclass 11, count 2 2006.203.08:21:49.13#ibcon#about to read 6, iclass 11, count 2 2006.203.08:21:49.13#ibcon#read 6, iclass 11, count 2 2006.203.08:21:49.13#ibcon#end of sib2, iclass 11, count 2 2006.203.08:21:49.13#ibcon#*mode == 0, iclass 11, count 2 2006.203.08:21:49.13#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.203.08:21:49.13#ibcon#[25=AT01-08\r\n] 2006.203.08:21:49.13#ibcon#*before write, iclass 11, count 2 2006.203.08:21:49.13#ibcon#enter sib2, iclass 11, count 2 2006.203.08:21:49.13#ibcon#flushed, iclass 11, count 2 2006.203.08:21:49.13#ibcon#about to write, iclass 11, count 2 2006.203.08:21:49.13#ibcon#wrote, iclass 11, count 2 2006.203.08:21:49.13#ibcon#about to read 3, iclass 11, count 2 2006.203.08:21:49.16#ibcon#read 3, iclass 11, count 2 2006.203.08:21:49.16#ibcon#about to read 4, iclass 11, count 2 2006.203.08:21:49.16#ibcon#read 4, iclass 11, count 2 2006.203.08:21:49.16#ibcon#about to read 5, iclass 11, count 2 2006.203.08:21:49.16#ibcon#read 5, iclass 11, count 2 2006.203.08:21:49.16#ibcon#about to read 6, iclass 11, count 2 2006.203.08:21:49.16#ibcon#read 6, iclass 11, count 2 2006.203.08:21:49.16#ibcon#end of sib2, iclass 11, count 2 2006.203.08:21:49.16#ibcon#*after write, iclass 11, count 2 2006.203.08:21:49.16#ibcon#*before return 0, iclass 11, count 2 2006.203.08:21:49.16#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.203.08:21:49.16#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.203.08:21:49.16#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.203.08:21:49.16#ibcon#ireg 7 cls_cnt 0 2006.203.08:21:49.16#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.203.08:21:49.27#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.203.08:21:49.27#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.203.08:21:49.27#ibcon#enter wrdev, iclass 11, count 0 2006.203.08:21:49.27#ibcon#first serial, iclass 11, count 0 2006.203.08:21:49.27#ibcon#enter sib2, iclass 11, count 0 2006.203.08:21:49.27#ibcon#flushed, iclass 11, count 0 2006.203.08:21:49.27#ibcon#about to write, iclass 11, count 0 2006.203.08:21:49.27#ibcon#wrote, iclass 11, count 0 2006.203.08:21:49.28#ibcon#about to read 3, iclass 11, count 0 2006.203.08:21:49.29#ibcon#read 3, iclass 11, count 0 2006.203.08:21:49.29#ibcon#about to read 4, iclass 11, count 0 2006.203.08:21:49.29#ibcon#read 4, iclass 11, count 0 2006.203.08:21:49.29#ibcon#about to read 5, iclass 11, count 0 2006.203.08:21:49.29#ibcon#read 5, iclass 11, count 0 2006.203.08:21:49.29#ibcon#about to read 6, iclass 11, count 0 2006.203.08:21:49.29#ibcon#read 6, iclass 11, count 0 2006.203.08:21:49.29#ibcon#end of sib2, iclass 11, count 0 2006.203.08:21:49.29#ibcon#*mode == 0, iclass 11, count 0 2006.203.08:21:49.29#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.203.08:21:49.29#ibcon#[25=USB\r\n] 2006.203.08:21:49.29#ibcon#*before write, iclass 11, count 0 2006.203.08:21:49.29#ibcon#enter sib2, iclass 11, count 0 2006.203.08:21:49.29#ibcon#flushed, iclass 11, count 0 2006.203.08:21:49.29#ibcon#about to write, iclass 11, count 0 2006.203.08:21:49.29#ibcon#wrote, iclass 11, count 0 2006.203.08:21:49.29#ibcon#about to read 3, iclass 11, count 0 2006.203.08:21:49.32#ibcon#read 3, iclass 11, count 0 2006.203.08:21:49.32#ibcon#about to read 4, iclass 11, count 0 2006.203.08:21:49.32#ibcon#read 4, iclass 11, count 0 2006.203.08:21:49.32#ibcon#about to read 5, iclass 11, count 0 2006.203.08:21:49.32#ibcon#read 5, iclass 11, count 0 2006.203.08:21:49.32#ibcon#about to read 6, iclass 11, count 0 2006.203.08:21:49.32#ibcon#read 6, iclass 11, count 0 2006.203.08:21:49.32#ibcon#end of sib2, iclass 11, count 0 2006.203.08:21:49.32#ibcon#*after write, iclass 11, count 0 2006.203.08:21:49.32#ibcon#*before return 0, iclass 11, count 0 2006.203.08:21:49.32#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.203.08:21:49.32#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.203.08:21:49.32#ibcon#about to clear, iclass 11 cls_cnt 0 2006.203.08:21:49.32#ibcon#cleared, iclass 11 cls_cnt 0 2006.203.08:21:49.32$vc4f8/valo=2,572.99 2006.203.08:21:49.32#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.203.08:21:49.32#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.203.08:21:49.32#ibcon#ireg 17 cls_cnt 0 2006.203.08:21:49.32#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.203.08:21:49.32#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.203.08:21:49.32#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.203.08:21:49.32#ibcon#enter wrdev, iclass 13, count 0 2006.203.08:21:49.32#ibcon#first serial, iclass 13, count 0 2006.203.08:21:49.32#ibcon#enter sib2, iclass 13, count 0 2006.203.08:21:49.32#ibcon#flushed, iclass 13, count 0 2006.203.08:21:49.32#ibcon#about to write, iclass 13, count 0 2006.203.08:21:49.32#ibcon#wrote, iclass 13, count 0 2006.203.08:21:49.32#ibcon#about to read 3, iclass 13, count 0 2006.203.08:21:49.35#ibcon#read 3, iclass 13, count 0 2006.203.08:21:49.35#ibcon#about to read 4, iclass 13, count 0 2006.203.08:21:49.35#ibcon#read 4, iclass 13, count 0 2006.203.08:21:49.35#ibcon#about to read 5, iclass 13, count 0 2006.203.08:21:49.35#ibcon#read 5, iclass 13, count 0 2006.203.08:21:49.35#ibcon#about to read 6, iclass 13, count 0 2006.203.08:21:49.35#ibcon#read 6, iclass 13, count 0 2006.203.08:21:49.35#ibcon#end of sib2, iclass 13, count 0 2006.203.08:21:49.35#ibcon#*mode == 0, iclass 13, count 0 2006.203.08:21:49.35#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.203.08:21:49.35#ibcon#[26=FRQ=02,572.99\r\n] 2006.203.08:21:49.35#ibcon#*before write, iclass 13, count 0 2006.203.08:21:49.35#ibcon#enter sib2, iclass 13, count 0 2006.203.08:21:49.35#ibcon#flushed, iclass 13, count 0 2006.203.08:21:49.35#ibcon#about to write, iclass 13, count 0 2006.203.08:21:49.35#ibcon#wrote, iclass 13, count 0 2006.203.08:21:49.35#ibcon#about to read 3, iclass 13, count 0 2006.203.08:21:49.39#ibcon#read 3, iclass 13, count 0 2006.203.08:21:49.39#ibcon#about to read 4, iclass 13, count 0 2006.203.08:21:49.39#ibcon#read 4, iclass 13, count 0 2006.203.08:21:49.39#ibcon#about to read 5, iclass 13, count 0 2006.203.08:21:49.39#ibcon#read 5, iclass 13, count 0 2006.203.08:21:49.39#ibcon#about to read 6, iclass 13, count 0 2006.203.08:21:49.39#ibcon#read 6, iclass 13, count 0 2006.203.08:21:49.39#ibcon#end of sib2, iclass 13, count 0 2006.203.08:21:49.39#ibcon#*after write, iclass 13, count 0 2006.203.08:21:49.39#ibcon#*before return 0, iclass 13, count 0 2006.203.08:21:49.39#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.203.08:21:49.39#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.203.08:21:49.39#ibcon#about to clear, iclass 13 cls_cnt 0 2006.203.08:21:49.39#ibcon#cleared, iclass 13 cls_cnt 0 2006.203.08:21:49.39$vc4f8/va=2,7 2006.203.08:21:49.39#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.203.08:21:49.39#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.203.08:21:49.39#ibcon#ireg 11 cls_cnt 2 2006.203.08:21:49.39#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.203.08:21:49.44#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.203.08:21:49.44#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.203.08:21:49.44#ibcon#enter wrdev, iclass 15, count 2 2006.203.08:21:49.44#ibcon#first serial, iclass 15, count 2 2006.203.08:21:49.44#ibcon#enter sib2, iclass 15, count 2 2006.203.08:21:49.44#ibcon#flushed, iclass 15, count 2 2006.203.08:21:49.44#ibcon#about to write, iclass 15, count 2 2006.203.08:21:49.44#ibcon#wrote, iclass 15, count 2 2006.203.08:21:49.44#ibcon#about to read 3, iclass 15, count 2 2006.203.08:21:49.46#ibcon#read 3, iclass 15, count 2 2006.203.08:21:49.46#ibcon#about to read 4, iclass 15, count 2 2006.203.08:21:49.46#ibcon#read 4, iclass 15, count 2 2006.203.08:21:49.46#ibcon#about to read 5, iclass 15, count 2 2006.203.08:21:49.46#ibcon#read 5, iclass 15, count 2 2006.203.08:21:49.46#ibcon#about to read 6, iclass 15, count 2 2006.203.08:21:49.46#ibcon#read 6, iclass 15, count 2 2006.203.08:21:49.46#ibcon#end of sib2, iclass 15, count 2 2006.203.08:21:49.46#ibcon#*mode == 0, iclass 15, count 2 2006.203.08:21:49.46#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.203.08:21:49.46#ibcon#[25=AT02-07\r\n] 2006.203.08:21:49.46#ibcon#*before write, iclass 15, count 2 2006.203.08:21:49.46#ibcon#enter sib2, iclass 15, count 2 2006.203.08:21:49.46#ibcon#flushed, iclass 15, count 2 2006.203.08:21:49.46#ibcon#about to write, iclass 15, count 2 2006.203.08:21:49.46#ibcon#wrote, iclass 15, count 2 2006.203.08:21:49.46#ibcon#about to read 3, iclass 15, count 2 2006.203.08:21:49.49#ibcon#read 3, iclass 15, count 2 2006.203.08:21:49.49#ibcon#about to read 4, iclass 15, count 2 2006.203.08:21:49.49#ibcon#read 4, iclass 15, count 2 2006.203.08:21:49.49#ibcon#about to read 5, iclass 15, count 2 2006.203.08:21:49.49#ibcon#read 5, iclass 15, count 2 2006.203.08:21:49.49#ibcon#about to read 6, iclass 15, count 2 2006.203.08:21:49.49#ibcon#read 6, iclass 15, count 2 2006.203.08:21:49.49#ibcon#end of sib2, iclass 15, count 2 2006.203.08:21:49.49#ibcon#*after write, iclass 15, count 2 2006.203.08:21:49.49#ibcon#*before return 0, iclass 15, count 2 2006.203.08:21:49.49#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.203.08:21:49.49#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.203.08:21:49.49#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.203.08:21:49.49#ibcon#ireg 7 cls_cnt 0 2006.203.08:21:49.49#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.203.08:21:49.61#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.203.08:21:49.61#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.203.08:21:49.61#ibcon#enter wrdev, iclass 15, count 0 2006.203.08:21:49.61#ibcon#first serial, iclass 15, count 0 2006.203.08:21:49.61#ibcon#enter sib2, iclass 15, count 0 2006.203.08:21:49.61#ibcon#flushed, iclass 15, count 0 2006.203.08:21:49.61#ibcon#about to write, iclass 15, count 0 2006.203.08:21:49.61#ibcon#wrote, iclass 15, count 0 2006.203.08:21:49.61#ibcon#about to read 3, iclass 15, count 0 2006.203.08:21:49.63#ibcon#read 3, iclass 15, count 0 2006.203.08:21:49.63#ibcon#about to read 4, iclass 15, count 0 2006.203.08:21:49.63#ibcon#read 4, iclass 15, count 0 2006.203.08:21:49.63#ibcon#about to read 5, iclass 15, count 0 2006.203.08:21:49.63#ibcon#read 5, iclass 15, count 0 2006.203.08:21:49.63#ibcon#about to read 6, iclass 15, count 0 2006.203.08:21:49.63#ibcon#read 6, iclass 15, count 0 2006.203.08:21:49.63#ibcon#end of sib2, iclass 15, count 0 2006.203.08:21:49.63#ibcon#*mode == 0, iclass 15, count 0 2006.203.08:21:49.63#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.203.08:21:49.63#ibcon#[25=USB\r\n] 2006.203.08:21:49.63#ibcon#*before write, iclass 15, count 0 2006.203.08:21:49.63#ibcon#enter sib2, iclass 15, count 0 2006.203.08:21:49.63#ibcon#flushed, iclass 15, count 0 2006.203.08:21:49.63#ibcon#about to write, iclass 15, count 0 2006.203.08:21:49.63#ibcon#wrote, iclass 15, count 0 2006.203.08:21:49.63#ibcon#about to read 3, iclass 15, count 0 2006.203.08:21:49.66#ibcon#read 3, iclass 15, count 0 2006.203.08:21:49.66#ibcon#about to read 4, iclass 15, count 0 2006.203.08:21:49.66#ibcon#read 4, iclass 15, count 0 2006.203.08:21:49.66#ibcon#about to read 5, iclass 15, count 0 2006.203.08:21:49.66#ibcon#read 5, iclass 15, count 0 2006.203.08:21:49.66#ibcon#about to read 6, iclass 15, count 0 2006.203.08:21:49.66#ibcon#read 6, iclass 15, count 0 2006.203.08:21:49.66#ibcon#end of sib2, iclass 15, count 0 2006.203.08:21:49.66#ibcon#*after write, iclass 15, count 0 2006.203.08:21:49.66#ibcon#*before return 0, iclass 15, count 0 2006.203.08:21:49.66#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.203.08:21:49.66#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.203.08:21:49.66#ibcon#about to clear, iclass 15 cls_cnt 0 2006.203.08:21:49.66#ibcon#cleared, iclass 15 cls_cnt 0 2006.203.08:21:49.66$vc4f8/valo=3,672.99 2006.203.08:21:49.66#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.203.08:21:49.66#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.203.08:21:49.66#ibcon#ireg 17 cls_cnt 0 2006.203.08:21:49.66#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.203.08:21:49.66#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.203.08:21:49.66#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.203.08:21:49.66#ibcon#enter wrdev, iclass 17, count 0 2006.203.08:21:49.66#ibcon#first serial, iclass 17, count 0 2006.203.08:21:49.66#ibcon#enter sib2, iclass 17, count 0 2006.203.08:21:49.66#ibcon#flushed, iclass 17, count 0 2006.203.08:21:49.66#ibcon#about to write, iclass 17, count 0 2006.203.08:21:49.66#ibcon#wrote, iclass 17, count 0 2006.203.08:21:49.66#ibcon#about to read 3, iclass 17, count 0 2006.203.08:21:49.69#ibcon#read 3, iclass 17, count 0 2006.203.08:21:49.69#ibcon#about to read 4, iclass 17, count 0 2006.203.08:21:49.69#ibcon#read 4, iclass 17, count 0 2006.203.08:21:49.69#ibcon#about to read 5, iclass 17, count 0 2006.203.08:21:49.69#ibcon#read 5, iclass 17, count 0 2006.203.08:21:49.69#ibcon#about to read 6, iclass 17, count 0 2006.203.08:21:49.69#ibcon#read 6, iclass 17, count 0 2006.203.08:21:49.69#ibcon#end of sib2, iclass 17, count 0 2006.203.08:21:49.69#ibcon#*mode == 0, iclass 17, count 0 2006.203.08:21:49.69#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.203.08:21:49.69#ibcon#[26=FRQ=03,672.99\r\n] 2006.203.08:21:49.69#ibcon#*before write, iclass 17, count 0 2006.203.08:21:49.69#ibcon#enter sib2, iclass 17, count 0 2006.203.08:21:49.69#ibcon#flushed, iclass 17, count 0 2006.203.08:21:49.69#ibcon#about to write, iclass 17, count 0 2006.203.08:21:49.69#ibcon#wrote, iclass 17, count 0 2006.203.08:21:49.69#ibcon#about to read 3, iclass 17, count 0 2006.203.08:21:49.73#ibcon#read 3, iclass 17, count 0 2006.203.08:21:49.73#ibcon#about to read 4, iclass 17, count 0 2006.203.08:21:49.73#ibcon#read 4, iclass 17, count 0 2006.203.08:21:49.73#ibcon#about to read 5, iclass 17, count 0 2006.203.08:21:49.73#ibcon#read 5, iclass 17, count 0 2006.203.08:21:49.73#ibcon#about to read 6, iclass 17, count 0 2006.203.08:21:49.73#ibcon#read 6, iclass 17, count 0 2006.203.08:21:49.73#ibcon#end of sib2, iclass 17, count 0 2006.203.08:21:49.73#ibcon#*after write, iclass 17, count 0 2006.203.08:21:49.73#ibcon#*before return 0, iclass 17, count 0 2006.203.08:21:49.73#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.203.08:21:49.73#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.203.08:21:49.73#ibcon#about to clear, iclass 17 cls_cnt 0 2006.203.08:21:49.73#ibcon#cleared, iclass 17 cls_cnt 0 2006.203.08:21:49.73$vc4f8/va=3,8 2006.203.08:21:49.73#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.203.08:21:49.73#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.203.08:21:49.73#ibcon#ireg 11 cls_cnt 2 2006.203.08:21:49.73#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.203.08:21:49.78#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.203.08:21:49.78#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.203.08:21:49.78#ibcon#enter wrdev, iclass 19, count 2 2006.203.08:21:49.78#ibcon#first serial, iclass 19, count 2 2006.203.08:21:49.78#ibcon#enter sib2, iclass 19, count 2 2006.203.08:21:49.78#ibcon#flushed, iclass 19, count 2 2006.203.08:21:49.78#ibcon#about to write, iclass 19, count 2 2006.203.08:21:49.78#ibcon#wrote, iclass 19, count 2 2006.203.08:21:49.78#ibcon#about to read 3, iclass 19, count 2 2006.203.08:21:49.80#ibcon#read 3, iclass 19, count 2 2006.203.08:21:49.80#ibcon#about to read 4, iclass 19, count 2 2006.203.08:21:49.80#ibcon#read 4, iclass 19, count 2 2006.203.08:21:49.80#ibcon#about to read 5, iclass 19, count 2 2006.203.08:21:49.80#ibcon#read 5, iclass 19, count 2 2006.203.08:21:49.80#ibcon#about to read 6, iclass 19, count 2 2006.203.08:21:49.80#ibcon#read 6, iclass 19, count 2 2006.203.08:21:49.80#ibcon#end of sib2, iclass 19, count 2 2006.203.08:21:49.80#ibcon#*mode == 0, iclass 19, count 2 2006.203.08:21:49.80#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.203.08:21:49.80#ibcon#[25=AT03-08\r\n] 2006.203.08:21:49.80#ibcon#*before write, iclass 19, count 2 2006.203.08:21:49.80#ibcon#enter sib2, iclass 19, count 2 2006.203.08:21:49.80#ibcon#flushed, iclass 19, count 2 2006.203.08:21:49.80#ibcon#about to write, iclass 19, count 2 2006.203.08:21:49.80#ibcon#wrote, iclass 19, count 2 2006.203.08:21:49.80#ibcon#about to read 3, iclass 19, count 2 2006.203.08:21:49.83#ibcon#read 3, iclass 19, count 2 2006.203.08:21:49.83#ibcon#about to read 4, iclass 19, count 2 2006.203.08:21:49.83#ibcon#read 4, iclass 19, count 2 2006.203.08:21:49.83#ibcon#about to read 5, iclass 19, count 2 2006.203.08:21:49.83#ibcon#read 5, iclass 19, count 2 2006.203.08:21:49.83#ibcon#about to read 6, iclass 19, count 2 2006.203.08:21:49.83#ibcon#read 6, iclass 19, count 2 2006.203.08:21:49.83#ibcon#end of sib2, iclass 19, count 2 2006.203.08:21:49.83#ibcon#*after write, iclass 19, count 2 2006.203.08:21:49.83#ibcon#*before return 0, iclass 19, count 2 2006.203.08:21:49.83#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.203.08:21:49.83#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.203.08:21:49.83#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.203.08:21:49.83#ibcon#ireg 7 cls_cnt 0 2006.203.08:21:49.83#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.203.08:21:49.95#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.203.08:21:49.95#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.203.08:21:49.95#ibcon#enter wrdev, iclass 19, count 0 2006.203.08:21:49.95#ibcon#first serial, iclass 19, count 0 2006.203.08:21:49.95#ibcon#enter sib2, iclass 19, count 0 2006.203.08:21:49.95#ibcon#flushed, iclass 19, count 0 2006.203.08:21:49.95#ibcon#about to write, iclass 19, count 0 2006.203.08:21:49.95#ibcon#wrote, iclass 19, count 0 2006.203.08:21:49.95#ibcon#about to read 3, iclass 19, count 0 2006.203.08:21:49.97#ibcon#read 3, iclass 19, count 0 2006.203.08:21:49.97#ibcon#about to read 4, iclass 19, count 0 2006.203.08:21:49.97#ibcon#read 4, iclass 19, count 0 2006.203.08:21:49.97#ibcon#about to read 5, iclass 19, count 0 2006.203.08:21:49.97#ibcon#read 5, iclass 19, count 0 2006.203.08:21:49.97#ibcon#about to read 6, iclass 19, count 0 2006.203.08:21:49.97#ibcon#read 6, iclass 19, count 0 2006.203.08:21:49.97#ibcon#end of sib2, iclass 19, count 0 2006.203.08:21:49.97#ibcon#*mode == 0, iclass 19, count 0 2006.203.08:21:49.97#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.203.08:21:49.97#ibcon#[25=USB\r\n] 2006.203.08:21:49.97#ibcon#*before write, iclass 19, count 0 2006.203.08:21:49.97#ibcon#enter sib2, iclass 19, count 0 2006.203.08:21:49.97#ibcon#flushed, iclass 19, count 0 2006.203.08:21:49.97#ibcon#about to write, iclass 19, count 0 2006.203.08:21:49.97#ibcon#wrote, iclass 19, count 0 2006.203.08:21:49.97#ibcon#about to read 3, iclass 19, count 0 2006.203.08:21:50.00#ibcon#read 3, iclass 19, count 0 2006.203.08:21:50.00#ibcon#about to read 4, iclass 19, count 0 2006.203.08:21:50.00#ibcon#read 4, iclass 19, count 0 2006.203.08:21:50.00#ibcon#about to read 5, iclass 19, count 0 2006.203.08:21:50.00#ibcon#read 5, iclass 19, count 0 2006.203.08:21:50.00#ibcon#about to read 6, iclass 19, count 0 2006.203.08:21:50.00#ibcon#read 6, iclass 19, count 0 2006.203.08:21:50.00#ibcon#end of sib2, iclass 19, count 0 2006.203.08:21:50.00#ibcon#*after write, iclass 19, count 0 2006.203.08:21:50.00#ibcon#*before return 0, iclass 19, count 0 2006.203.08:21:50.00#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.203.08:21:50.00#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.203.08:21:50.00#ibcon#about to clear, iclass 19 cls_cnt 0 2006.203.08:21:50.00#ibcon#cleared, iclass 19 cls_cnt 0 2006.203.08:21:50.00$vc4f8/valo=4,832.99 2006.203.08:21:50.00#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.203.08:21:50.00#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.203.08:21:50.00#ibcon#ireg 17 cls_cnt 0 2006.203.08:21:50.00#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.203.08:21:50.00#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.203.08:21:50.00#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.203.08:21:50.00#ibcon#enter wrdev, iclass 21, count 0 2006.203.08:21:50.00#ibcon#first serial, iclass 21, count 0 2006.203.08:21:50.00#ibcon#enter sib2, iclass 21, count 0 2006.203.08:21:50.00#ibcon#flushed, iclass 21, count 0 2006.203.08:21:50.00#ibcon#about to write, iclass 21, count 0 2006.203.08:21:50.00#ibcon#wrote, iclass 21, count 0 2006.203.08:21:50.00#ibcon#about to read 3, iclass 21, count 0 2006.203.08:21:50.02#ibcon#read 3, iclass 21, count 0 2006.203.08:21:50.02#ibcon#about to read 4, iclass 21, count 0 2006.203.08:21:50.02#ibcon#read 4, iclass 21, count 0 2006.203.08:21:50.02#ibcon#about to read 5, iclass 21, count 0 2006.203.08:21:50.02#ibcon#read 5, iclass 21, count 0 2006.203.08:21:50.02#ibcon#about to read 6, iclass 21, count 0 2006.203.08:21:50.02#ibcon#read 6, iclass 21, count 0 2006.203.08:21:50.02#ibcon#end of sib2, iclass 21, count 0 2006.203.08:21:50.02#ibcon#*mode == 0, iclass 21, count 0 2006.203.08:21:50.02#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.203.08:21:50.02#ibcon#[26=FRQ=04,832.99\r\n] 2006.203.08:21:50.02#ibcon#*before write, iclass 21, count 0 2006.203.08:21:50.02#ibcon#enter sib2, iclass 21, count 0 2006.203.08:21:50.02#ibcon#flushed, iclass 21, count 0 2006.203.08:21:50.02#ibcon#about to write, iclass 21, count 0 2006.203.08:21:50.02#ibcon#wrote, iclass 21, count 0 2006.203.08:21:50.02#ibcon#about to read 3, iclass 21, count 0 2006.203.08:21:50.06#ibcon#read 3, iclass 21, count 0 2006.203.08:21:50.06#ibcon#about to read 4, iclass 21, count 0 2006.203.08:21:50.06#ibcon#read 4, iclass 21, count 0 2006.203.08:21:50.06#ibcon#about to read 5, iclass 21, count 0 2006.203.08:21:50.06#ibcon#read 5, iclass 21, count 0 2006.203.08:21:50.06#ibcon#about to read 6, iclass 21, count 0 2006.203.08:21:50.06#ibcon#read 6, iclass 21, count 0 2006.203.08:21:50.06#ibcon#end of sib2, iclass 21, count 0 2006.203.08:21:50.06#ibcon#*after write, iclass 21, count 0 2006.203.08:21:50.06#ibcon#*before return 0, iclass 21, count 0 2006.203.08:21:50.06#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.203.08:21:50.06#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.203.08:21:50.06#ibcon#about to clear, iclass 21 cls_cnt 0 2006.203.08:21:50.06#ibcon#cleared, iclass 21 cls_cnt 0 2006.203.08:21:50.06$vc4f8/va=4,7 2006.203.08:21:50.06#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.203.08:21:50.06#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.203.08:21:50.06#ibcon#ireg 11 cls_cnt 2 2006.203.08:21:50.06#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.203.08:21:50.12#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.203.08:21:50.12#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.203.08:21:50.12#ibcon#enter wrdev, iclass 23, count 2 2006.203.08:21:50.12#ibcon#first serial, iclass 23, count 2 2006.203.08:21:50.12#ibcon#enter sib2, iclass 23, count 2 2006.203.08:21:50.12#ibcon#flushed, iclass 23, count 2 2006.203.08:21:50.12#ibcon#about to write, iclass 23, count 2 2006.203.08:21:50.12#ibcon#wrote, iclass 23, count 2 2006.203.08:21:50.12#ibcon#about to read 3, iclass 23, count 2 2006.203.08:21:50.14#ibcon#read 3, iclass 23, count 2 2006.203.08:21:50.14#ibcon#about to read 4, iclass 23, count 2 2006.203.08:21:50.14#ibcon#read 4, iclass 23, count 2 2006.203.08:21:50.14#ibcon#about to read 5, iclass 23, count 2 2006.203.08:21:50.14#ibcon#read 5, iclass 23, count 2 2006.203.08:21:50.14#ibcon#about to read 6, iclass 23, count 2 2006.203.08:21:50.14#ibcon#read 6, iclass 23, count 2 2006.203.08:21:50.14#ibcon#end of sib2, iclass 23, count 2 2006.203.08:21:50.14#ibcon#*mode == 0, iclass 23, count 2 2006.203.08:21:50.14#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.203.08:21:50.14#ibcon#[25=AT04-07\r\n] 2006.203.08:21:50.14#ibcon#*before write, iclass 23, count 2 2006.203.08:21:50.14#ibcon#enter sib2, iclass 23, count 2 2006.203.08:21:50.14#ibcon#flushed, iclass 23, count 2 2006.203.08:21:50.14#ibcon#about to write, iclass 23, count 2 2006.203.08:21:50.14#ibcon#wrote, iclass 23, count 2 2006.203.08:21:50.14#ibcon#about to read 3, iclass 23, count 2 2006.203.08:21:50.17#ibcon#read 3, iclass 23, count 2 2006.203.08:21:50.17#ibcon#about to read 4, iclass 23, count 2 2006.203.08:21:50.17#ibcon#read 4, iclass 23, count 2 2006.203.08:21:50.17#ibcon#about to read 5, iclass 23, count 2 2006.203.08:21:50.17#ibcon#read 5, iclass 23, count 2 2006.203.08:21:50.17#ibcon#about to read 6, iclass 23, count 2 2006.203.08:21:50.17#ibcon#read 6, iclass 23, count 2 2006.203.08:21:50.17#ibcon#end of sib2, iclass 23, count 2 2006.203.08:21:50.17#ibcon#*after write, iclass 23, count 2 2006.203.08:21:50.17#ibcon#*before return 0, iclass 23, count 2 2006.203.08:21:50.17#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.203.08:21:50.17#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.203.08:21:50.17#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.203.08:21:50.17#ibcon#ireg 7 cls_cnt 0 2006.203.08:21:50.17#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.203.08:21:50.29#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.203.08:21:50.29#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.203.08:21:50.29#ibcon#enter wrdev, iclass 23, count 0 2006.203.08:21:50.29#ibcon#first serial, iclass 23, count 0 2006.203.08:21:50.29#ibcon#enter sib2, iclass 23, count 0 2006.203.08:21:50.29#ibcon#flushed, iclass 23, count 0 2006.203.08:21:50.29#ibcon#about to write, iclass 23, count 0 2006.203.08:21:50.29#ibcon#wrote, iclass 23, count 0 2006.203.08:21:50.29#ibcon#about to read 3, iclass 23, count 0 2006.203.08:21:50.31#ibcon#read 3, iclass 23, count 0 2006.203.08:21:50.31#ibcon#about to read 4, iclass 23, count 0 2006.203.08:21:50.31#ibcon#read 4, iclass 23, count 0 2006.203.08:21:50.31#ibcon#about to read 5, iclass 23, count 0 2006.203.08:21:50.31#ibcon#read 5, iclass 23, count 0 2006.203.08:21:50.31#ibcon#about to read 6, iclass 23, count 0 2006.203.08:21:50.31#ibcon#read 6, iclass 23, count 0 2006.203.08:21:50.31#ibcon#end of sib2, iclass 23, count 0 2006.203.08:21:50.31#ibcon#*mode == 0, iclass 23, count 0 2006.203.08:21:50.31#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.203.08:21:50.31#ibcon#[25=USB\r\n] 2006.203.08:21:50.31#ibcon#*before write, iclass 23, count 0 2006.203.08:21:50.31#ibcon#enter sib2, iclass 23, count 0 2006.203.08:21:50.31#ibcon#flushed, iclass 23, count 0 2006.203.08:21:50.31#ibcon#about to write, iclass 23, count 0 2006.203.08:21:50.31#ibcon#wrote, iclass 23, count 0 2006.203.08:21:50.31#ibcon#about to read 3, iclass 23, count 0 2006.203.08:21:50.34#ibcon#read 3, iclass 23, count 0 2006.203.08:21:50.34#ibcon#about to read 4, iclass 23, count 0 2006.203.08:21:50.34#ibcon#read 4, iclass 23, count 0 2006.203.08:21:50.34#ibcon#about to read 5, iclass 23, count 0 2006.203.08:21:50.34#ibcon#read 5, iclass 23, count 0 2006.203.08:21:50.34#ibcon#about to read 6, iclass 23, count 0 2006.203.08:21:50.34#ibcon#read 6, iclass 23, count 0 2006.203.08:21:50.34#ibcon#end of sib2, iclass 23, count 0 2006.203.08:21:50.34#ibcon#*after write, iclass 23, count 0 2006.203.08:21:50.34#ibcon#*before return 0, iclass 23, count 0 2006.203.08:21:50.34#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.203.08:21:50.34#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.203.08:21:50.34#ibcon#about to clear, iclass 23 cls_cnt 0 2006.203.08:21:50.34#ibcon#cleared, iclass 23 cls_cnt 0 2006.203.08:21:50.34$vc4f8/valo=5,652.99 2006.203.08:21:50.34#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.203.08:21:50.34#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.203.08:21:50.34#ibcon#ireg 17 cls_cnt 0 2006.203.08:21:50.34#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.203.08:21:50.34#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.203.08:21:50.34#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.203.08:21:50.34#ibcon#enter wrdev, iclass 25, count 0 2006.203.08:21:50.34#ibcon#first serial, iclass 25, count 0 2006.203.08:21:50.34#ibcon#enter sib2, iclass 25, count 0 2006.203.08:21:50.34#ibcon#flushed, iclass 25, count 0 2006.203.08:21:50.34#ibcon#about to write, iclass 25, count 0 2006.203.08:21:50.34#ibcon#wrote, iclass 25, count 0 2006.203.08:21:50.34#ibcon#about to read 3, iclass 25, count 0 2006.203.08:21:50.37#ibcon#read 3, iclass 25, count 0 2006.203.08:21:50.37#ibcon#about to read 4, iclass 25, count 0 2006.203.08:21:50.37#ibcon#read 4, iclass 25, count 0 2006.203.08:21:50.37#ibcon#about to read 5, iclass 25, count 0 2006.203.08:21:50.37#ibcon#read 5, iclass 25, count 0 2006.203.08:21:50.37#ibcon#about to read 6, iclass 25, count 0 2006.203.08:21:50.37#ibcon#read 6, iclass 25, count 0 2006.203.08:21:50.37#ibcon#end of sib2, iclass 25, count 0 2006.203.08:21:50.37#ibcon#*mode == 0, iclass 25, count 0 2006.203.08:21:50.37#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.203.08:21:50.37#ibcon#[26=FRQ=05,652.99\r\n] 2006.203.08:21:50.37#ibcon#*before write, iclass 25, count 0 2006.203.08:21:50.37#ibcon#enter sib2, iclass 25, count 0 2006.203.08:21:50.37#ibcon#flushed, iclass 25, count 0 2006.203.08:21:50.37#ibcon#about to write, iclass 25, count 0 2006.203.08:21:50.37#ibcon#wrote, iclass 25, count 0 2006.203.08:21:50.37#ibcon#about to read 3, iclass 25, count 0 2006.203.08:21:50.41#ibcon#read 3, iclass 25, count 0 2006.203.08:21:50.41#ibcon#about to read 4, iclass 25, count 0 2006.203.08:21:50.41#ibcon#read 4, iclass 25, count 0 2006.203.08:21:50.41#ibcon#about to read 5, iclass 25, count 0 2006.203.08:21:50.41#ibcon#read 5, iclass 25, count 0 2006.203.08:21:50.41#ibcon#about to read 6, iclass 25, count 0 2006.203.08:21:50.41#ibcon#read 6, iclass 25, count 0 2006.203.08:21:50.41#ibcon#end of sib2, iclass 25, count 0 2006.203.08:21:50.41#ibcon#*after write, iclass 25, count 0 2006.203.08:21:50.41#ibcon#*before return 0, iclass 25, count 0 2006.203.08:21:50.41#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.203.08:21:50.41#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.203.08:21:50.41#ibcon#about to clear, iclass 25 cls_cnt 0 2006.203.08:21:50.41#ibcon#cleared, iclass 25 cls_cnt 0 2006.203.08:21:50.41$vc4f8/va=5,7 2006.203.08:21:50.41#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.203.08:21:50.41#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.203.08:21:50.41#ibcon#ireg 11 cls_cnt 2 2006.203.08:21:50.41#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.203.08:21:50.46#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.203.08:21:50.46#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.203.08:21:50.46#ibcon#enter wrdev, iclass 27, count 2 2006.203.08:21:50.46#ibcon#first serial, iclass 27, count 2 2006.203.08:21:50.46#ibcon#enter sib2, iclass 27, count 2 2006.203.08:21:50.46#ibcon#flushed, iclass 27, count 2 2006.203.08:21:50.46#ibcon#about to write, iclass 27, count 2 2006.203.08:21:50.46#ibcon#wrote, iclass 27, count 2 2006.203.08:21:50.46#ibcon#about to read 3, iclass 27, count 2 2006.203.08:21:50.48#ibcon#read 3, iclass 27, count 2 2006.203.08:21:50.48#ibcon#about to read 4, iclass 27, count 2 2006.203.08:21:50.48#ibcon#read 4, iclass 27, count 2 2006.203.08:21:50.48#ibcon#about to read 5, iclass 27, count 2 2006.203.08:21:50.48#ibcon#read 5, iclass 27, count 2 2006.203.08:21:50.48#ibcon#about to read 6, iclass 27, count 2 2006.203.08:21:50.48#ibcon#read 6, iclass 27, count 2 2006.203.08:21:50.48#ibcon#end of sib2, iclass 27, count 2 2006.203.08:21:50.48#ibcon#*mode == 0, iclass 27, count 2 2006.203.08:21:50.48#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.203.08:21:50.48#ibcon#[25=AT05-07\r\n] 2006.203.08:21:50.48#ibcon#*before write, iclass 27, count 2 2006.203.08:21:50.48#ibcon#enter sib2, iclass 27, count 2 2006.203.08:21:50.48#ibcon#flushed, iclass 27, count 2 2006.203.08:21:50.48#ibcon#about to write, iclass 27, count 2 2006.203.08:21:50.48#ibcon#wrote, iclass 27, count 2 2006.203.08:21:50.48#ibcon#about to read 3, iclass 27, count 2 2006.203.08:21:50.51#ibcon#read 3, iclass 27, count 2 2006.203.08:21:50.51#ibcon#about to read 4, iclass 27, count 2 2006.203.08:21:50.51#ibcon#read 4, iclass 27, count 2 2006.203.08:21:50.51#ibcon#about to read 5, iclass 27, count 2 2006.203.08:21:50.51#ibcon#read 5, iclass 27, count 2 2006.203.08:21:50.51#ibcon#about to read 6, iclass 27, count 2 2006.203.08:21:50.51#ibcon#read 6, iclass 27, count 2 2006.203.08:21:50.51#ibcon#end of sib2, iclass 27, count 2 2006.203.08:21:50.51#ibcon#*after write, iclass 27, count 2 2006.203.08:21:50.51#ibcon#*before return 0, iclass 27, count 2 2006.203.08:21:50.51#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.203.08:21:50.51#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.203.08:21:50.51#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.203.08:21:50.51#ibcon#ireg 7 cls_cnt 0 2006.203.08:21:50.51#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.203.08:21:50.63#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.203.08:21:50.63#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.203.08:21:50.63#ibcon#enter wrdev, iclass 27, count 0 2006.203.08:21:50.63#ibcon#first serial, iclass 27, count 0 2006.203.08:21:50.63#ibcon#enter sib2, iclass 27, count 0 2006.203.08:21:50.63#ibcon#flushed, iclass 27, count 0 2006.203.08:21:50.63#ibcon#about to write, iclass 27, count 0 2006.203.08:21:50.63#ibcon#wrote, iclass 27, count 0 2006.203.08:21:50.63#ibcon#about to read 3, iclass 27, count 0 2006.203.08:21:50.65#ibcon#read 3, iclass 27, count 0 2006.203.08:21:50.65#ibcon#about to read 4, iclass 27, count 0 2006.203.08:21:50.65#ibcon#read 4, iclass 27, count 0 2006.203.08:21:50.65#ibcon#about to read 5, iclass 27, count 0 2006.203.08:21:50.65#ibcon#read 5, iclass 27, count 0 2006.203.08:21:50.65#ibcon#about to read 6, iclass 27, count 0 2006.203.08:21:50.65#ibcon#read 6, iclass 27, count 0 2006.203.08:21:50.65#ibcon#end of sib2, iclass 27, count 0 2006.203.08:21:50.65#ibcon#*mode == 0, iclass 27, count 0 2006.203.08:21:50.65#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.203.08:21:50.65#ibcon#[25=USB\r\n] 2006.203.08:21:50.65#ibcon#*before write, iclass 27, count 0 2006.203.08:21:50.65#ibcon#enter sib2, iclass 27, count 0 2006.203.08:21:50.65#ibcon#flushed, iclass 27, count 0 2006.203.08:21:50.65#ibcon#about to write, iclass 27, count 0 2006.203.08:21:50.65#ibcon#wrote, iclass 27, count 0 2006.203.08:21:50.65#ibcon#about to read 3, iclass 27, count 0 2006.203.08:21:50.68#ibcon#read 3, iclass 27, count 0 2006.203.08:21:50.68#ibcon#about to read 4, iclass 27, count 0 2006.203.08:21:50.68#ibcon#read 4, iclass 27, count 0 2006.203.08:21:50.68#ibcon#about to read 5, iclass 27, count 0 2006.203.08:21:50.68#ibcon#read 5, iclass 27, count 0 2006.203.08:21:50.68#ibcon#about to read 6, iclass 27, count 0 2006.203.08:21:50.68#ibcon#read 6, iclass 27, count 0 2006.203.08:21:50.68#ibcon#end of sib2, iclass 27, count 0 2006.203.08:21:50.68#ibcon#*after write, iclass 27, count 0 2006.203.08:21:50.68#ibcon#*before return 0, iclass 27, count 0 2006.203.08:21:50.68#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.203.08:21:50.68#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.203.08:21:50.68#ibcon#about to clear, iclass 27 cls_cnt 0 2006.203.08:21:50.68#ibcon#cleared, iclass 27 cls_cnt 0 2006.203.08:21:50.68$vc4f8/valo=6,772.99 2006.203.08:21:50.68#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.203.08:21:50.68#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.203.08:21:50.68#ibcon#ireg 17 cls_cnt 0 2006.203.08:21:50.68#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.203.08:21:50.68#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.203.08:21:50.68#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.203.08:21:50.68#ibcon#enter wrdev, iclass 29, count 0 2006.203.08:21:50.68#ibcon#first serial, iclass 29, count 0 2006.203.08:21:50.68#ibcon#enter sib2, iclass 29, count 0 2006.203.08:21:50.68#ibcon#flushed, iclass 29, count 0 2006.203.08:21:50.68#ibcon#about to write, iclass 29, count 0 2006.203.08:21:50.68#ibcon#wrote, iclass 29, count 0 2006.203.08:21:50.68#ibcon#about to read 3, iclass 29, count 0 2006.203.08:21:50.70#ibcon#read 3, iclass 29, count 0 2006.203.08:21:50.70#ibcon#about to read 4, iclass 29, count 0 2006.203.08:21:50.70#ibcon#read 4, iclass 29, count 0 2006.203.08:21:50.70#ibcon#about to read 5, iclass 29, count 0 2006.203.08:21:50.70#ibcon#read 5, iclass 29, count 0 2006.203.08:21:50.70#ibcon#about to read 6, iclass 29, count 0 2006.203.08:21:50.70#ibcon#read 6, iclass 29, count 0 2006.203.08:21:50.70#ibcon#end of sib2, iclass 29, count 0 2006.203.08:21:50.70#ibcon#*mode == 0, iclass 29, count 0 2006.203.08:21:50.70#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.203.08:21:50.70#ibcon#[26=FRQ=06,772.99\r\n] 2006.203.08:21:50.70#ibcon#*before write, iclass 29, count 0 2006.203.08:21:50.70#ibcon#enter sib2, iclass 29, count 0 2006.203.08:21:50.70#ibcon#flushed, iclass 29, count 0 2006.203.08:21:50.70#ibcon#about to write, iclass 29, count 0 2006.203.08:21:50.70#ibcon#wrote, iclass 29, count 0 2006.203.08:21:50.70#ibcon#about to read 3, iclass 29, count 0 2006.203.08:21:50.74#ibcon#read 3, iclass 29, count 0 2006.203.08:21:50.74#ibcon#about to read 4, iclass 29, count 0 2006.203.08:21:50.74#ibcon#read 4, iclass 29, count 0 2006.203.08:21:50.74#ibcon#about to read 5, iclass 29, count 0 2006.203.08:21:50.74#ibcon#read 5, iclass 29, count 0 2006.203.08:21:50.74#ibcon#about to read 6, iclass 29, count 0 2006.203.08:21:50.74#ibcon#read 6, iclass 29, count 0 2006.203.08:21:50.74#ibcon#end of sib2, iclass 29, count 0 2006.203.08:21:50.74#ibcon#*after write, iclass 29, count 0 2006.203.08:21:50.74#ibcon#*before return 0, iclass 29, count 0 2006.203.08:21:50.74#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.203.08:21:50.74#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.203.08:21:50.74#ibcon#about to clear, iclass 29 cls_cnt 0 2006.203.08:21:50.74#ibcon#cleared, iclass 29 cls_cnt 0 2006.203.08:21:50.74$vc4f8/va=6,6 2006.203.08:21:50.74#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.203.08:21:50.74#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.203.08:21:50.74#ibcon#ireg 11 cls_cnt 2 2006.203.08:21:50.74#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.203.08:21:50.80#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.203.08:21:50.80#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.203.08:21:50.80#ibcon#enter wrdev, iclass 31, count 2 2006.203.08:21:50.80#ibcon#first serial, iclass 31, count 2 2006.203.08:21:50.80#ibcon#enter sib2, iclass 31, count 2 2006.203.08:21:50.80#ibcon#flushed, iclass 31, count 2 2006.203.08:21:50.80#ibcon#about to write, iclass 31, count 2 2006.203.08:21:50.80#ibcon#wrote, iclass 31, count 2 2006.203.08:21:50.80#ibcon#about to read 3, iclass 31, count 2 2006.203.08:21:50.82#ibcon#read 3, iclass 31, count 2 2006.203.08:21:50.82#ibcon#about to read 4, iclass 31, count 2 2006.203.08:21:50.82#ibcon#read 4, iclass 31, count 2 2006.203.08:21:50.82#ibcon#about to read 5, iclass 31, count 2 2006.203.08:21:50.82#ibcon#read 5, iclass 31, count 2 2006.203.08:21:50.82#ibcon#about to read 6, iclass 31, count 2 2006.203.08:21:50.82#ibcon#read 6, iclass 31, count 2 2006.203.08:21:50.82#ibcon#end of sib2, iclass 31, count 2 2006.203.08:21:50.82#ibcon#*mode == 0, iclass 31, count 2 2006.203.08:21:50.82#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.203.08:21:50.82#ibcon#[25=AT06-06\r\n] 2006.203.08:21:50.82#ibcon#*before write, iclass 31, count 2 2006.203.08:21:50.82#ibcon#enter sib2, iclass 31, count 2 2006.203.08:21:50.82#ibcon#flushed, iclass 31, count 2 2006.203.08:21:50.82#ibcon#about to write, iclass 31, count 2 2006.203.08:21:50.82#ibcon#wrote, iclass 31, count 2 2006.203.08:21:50.82#ibcon#about to read 3, iclass 31, count 2 2006.203.08:21:50.85#ibcon#read 3, iclass 31, count 2 2006.203.08:21:50.85#ibcon#about to read 4, iclass 31, count 2 2006.203.08:21:50.85#ibcon#read 4, iclass 31, count 2 2006.203.08:21:50.85#ibcon#about to read 5, iclass 31, count 2 2006.203.08:21:50.85#ibcon#read 5, iclass 31, count 2 2006.203.08:21:50.85#ibcon#about to read 6, iclass 31, count 2 2006.203.08:21:50.85#ibcon#read 6, iclass 31, count 2 2006.203.08:21:50.85#ibcon#end of sib2, iclass 31, count 2 2006.203.08:21:50.85#ibcon#*after write, iclass 31, count 2 2006.203.08:21:50.85#ibcon#*before return 0, iclass 31, count 2 2006.203.08:21:50.85#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.203.08:21:50.85#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.203.08:21:50.85#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.203.08:21:50.85#ibcon#ireg 7 cls_cnt 0 2006.203.08:21:50.85#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.203.08:21:50.97#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.203.08:21:50.97#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.203.08:21:50.97#ibcon#enter wrdev, iclass 31, count 0 2006.203.08:21:50.97#ibcon#first serial, iclass 31, count 0 2006.203.08:21:50.97#ibcon#enter sib2, iclass 31, count 0 2006.203.08:21:50.97#ibcon#flushed, iclass 31, count 0 2006.203.08:21:50.97#ibcon#about to write, iclass 31, count 0 2006.203.08:21:50.97#ibcon#wrote, iclass 31, count 0 2006.203.08:21:50.97#ibcon#about to read 3, iclass 31, count 0 2006.203.08:21:50.99#ibcon#read 3, iclass 31, count 0 2006.203.08:21:50.99#ibcon#about to read 4, iclass 31, count 0 2006.203.08:21:50.99#ibcon#read 4, iclass 31, count 0 2006.203.08:21:50.99#ibcon#about to read 5, iclass 31, count 0 2006.203.08:21:50.99#ibcon#read 5, iclass 31, count 0 2006.203.08:21:50.99#ibcon#about to read 6, iclass 31, count 0 2006.203.08:21:50.99#ibcon#read 6, iclass 31, count 0 2006.203.08:21:50.99#ibcon#end of sib2, iclass 31, count 0 2006.203.08:21:50.99#ibcon#*mode == 0, iclass 31, count 0 2006.203.08:21:50.99#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.203.08:21:50.99#ibcon#[25=USB\r\n] 2006.203.08:21:50.99#ibcon#*before write, iclass 31, count 0 2006.203.08:21:50.99#ibcon#enter sib2, iclass 31, count 0 2006.203.08:21:50.99#ibcon#flushed, iclass 31, count 0 2006.203.08:21:50.99#ibcon#about to write, iclass 31, count 0 2006.203.08:21:50.99#ibcon#wrote, iclass 31, count 0 2006.203.08:21:50.99#ibcon#about to read 3, iclass 31, count 0 2006.203.08:21:51.02#ibcon#read 3, iclass 31, count 0 2006.203.08:21:51.02#ibcon#about to read 4, iclass 31, count 0 2006.203.08:21:51.02#ibcon#read 4, iclass 31, count 0 2006.203.08:21:51.02#ibcon#about to read 5, iclass 31, count 0 2006.203.08:21:51.02#ibcon#read 5, iclass 31, count 0 2006.203.08:21:51.02#ibcon#about to read 6, iclass 31, count 0 2006.203.08:21:51.02#ibcon#read 6, iclass 31, count 0 2006.203.08:21:51.02#ibcon#end of sib2, iclass 31, count 0 2006.203.08:21:51.02#ibcon#*after write, iclass 31, count 0 2006.203.08:21:51.02#ibcon#*before return 0, iclass 31, count 0 2006.203.08:21:51.02#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.203.08:21:51.02#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.203.08:21:51.02#ibcon#about to clear, iclass 31 cls_cnt 0 2006.203.08:21:51.02#ibcon#cleared, iclass 31 cls_cnt 0 2006.203.08:21:51.02$vc4f8/valo=7,832.99 2006.203.08:21:51.02#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.203.08:21:51.02#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.203.08:21:51.02#ibcon#ireg 17 cls_cnt 0 2006.203.08:21:51.02#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.203.08:21:51.02#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.203.08:21:51.02#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.203.08:21:51.02#ibcon#enter wrdev, iclass 33, count 0 2006.203.08:21:51.02#ibcon#first serial, iclass 33, count 0 2006.203.08:21:51.02#ibcon#enter sib2, iclass 33, count 0 2006.203.08:21:51.02#ibcon#flushed, iclass 33, count 0 2006.203.08:21:51.02#ibcon#about to write, iclass 33, count 0 2006.203.08:21:51.02#ibcon#wrote, iclass 33, count 0 2006.203.08:21:51.02#ibcon#about to read 3, iclass 33, count 0 2006.203.08:21:51.04#ibcon#read 3, iclass 33, count 0 2006.203.08:21:51.04#ibcon#about to read 4, iclass 33, count 0 2006.203.08:21:51.04#ibcon#read 4, iclass 33, count 0 2006.203.08:21:51.04#ibcon#about to read 5, iclass 33, count 0 2006.203.08:21:51.04#ibcon#read 5, iclass 33, count 0 2006.203.08:21:51.04#ibcon#about to read 6, iclass 33, count 0 2006.203.08:21:51.04#ibcon#read 6, iclass 33, count 0 2006.203.08:21:51.04#ibcon#end of sib2, iclass 33, count 0 2006.203.08:21:51.04#ibcon#*mode == 0, iclass 33, count 0 2006.203.08:21:51.04#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.203.08:21:51.04#ibcon#[26=FRQ=07,832.99\r\n] 2006.203.08:21:51.04#ibcon#*before write, iclass 33, count 0 2006.203.08:21:51.04#ibcon#enter sib2, iclass 33, count 0 2006.203.08:21:51.04#ibcon#flushed, iclass 33, count 0 2006.203.08:21:51.04#ibcon#about to write, iclass 33, count 0 2006.203.08:21:51.04#ibcon#wrote, iclass 33, count 0 2006.203.08:21:51.04#ibcon#about to read 3, iclass 33, count 0 2006.203.08:21:51.08#ibcon#read 3, iclass 33, count 0 2006.203.08:21:51.08#ibcon#about to read 4, iclass 33, count 0 2006.203.08:21:51.08#ibcon#read 4, iclass 33, count 0 2006.203.08:21:51.08#ibcon#about to read 5, iclass 33, count 0 2006.203.08:21:51.08#ibcon#read 5, iclass 33, count 0 2006.203.08:21:51.08#ibcon#about to read 6, iclass 33, count 0 2006.203.08:21:51.08#ibcon#read 6, iclass 33, count 0 2006.203.08:21:51.08#ibcon#end of sib2, iclass 33, count 0 2006.203.08:21:51.08#ibcon#*after write, iclass 33, count 0 2006.203.08:21:51.08#ibcon#*before return 0, iclass 33, count 0 2006.203.08:21:51.08#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.203.08:21:51.08#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.203.08:21:51.08#ibcon#about to clear, iclass 33 cls_cnt 0 2006.203.08:21:51.08#ibcon#cleared, iclass 33 cls_cnt 0 2006.203.08:21:51.08$vc4f8/va=7,7 2006.203.08:21:51.08#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.203.08:21:51.08#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.203.08:21:51.08#ibcon#ireg 11 cls_cnt 2 2006.203.08:21:51.08#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.203.08:21:51.15#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.203.08:21:51.15#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.203.08:21:51.15#ibcon#enter wrdev, iclass 35, count 2 2006.203.08:21:51.15#ibcon#first serial, iclass 35, count 2 2006.203.08:21:51.15#ibcon#enter sib2, iclass 35, count 2 2006.203.08:21:51.15#ibcon#flushed, iclass 35, count 2 2006.203.08:21:51.15#ibcon#about to write, iclass 35, count 2 2006.203.08:21:51.15#ibcon#wrote, iclass 35, count 2 2006.203.08:21:51.15#ibcon#about to read 3, iclass 35, count 2 2006.203.08:21:51.17#ibcon#read 3, iclass 35, count 2 2006.203.08:21:51.17#ibcon#about to read 4, iclass 35, count 2 2006.203.08:21:51.17#ibcon#read 4, iclass 35, count 2 2006.203.08:21:51.17#ibcon#about to read 5, iclass 35, count 2 2006.203.08:21:51.17#ibcon#read 5, iclass 35, count 2 2006.203.08:21:51.17#ibcon#about to read 6, iclass 35, count 2 2006.203.08:21:51.17#ibcon#read 6, iclass 35, count 2 2006.203.08:21:51.17#ibcon#end of sib2, iclass 35, count 2 2006.203.08:21:51.17#ibcon#*mode == 0, iclass 35, count 2 2006.203.08:21:51.17#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.203.08:21:51.17#ibcon#[25=AT07-07\r\n] 2006.203.08:21:51.17#ibcon#*before write, iclass 35, count 2 2006.203.08:21:51.17#ibcon#enter sib2, iclass 35, count 2 2006.203.08:21:51.17#ibcon#flushed, iclass 35, count 2 2006.203.08:21:51.17#ibcon#about to write, iclass 35, count 2 2006.203.08:21:51.17#ibcon#wrote, iclass 35, count 2 2006.203.08:21:51.17#ibcon#about to read 3, iclass 35, count 2 2006.203.08:21:51.19#ibcon#read 3, iclass 35, count 2 2006.203.08:21:51.19#ibcon#about to read 4, iclass 35, count 2 2006.203.08:21:51.19#ibcon#read 4, iclass 35, count 2 2006.203.08:21:51.19#ibcon#about to read 5, iclass 35, count 2 2006.203.08:21:51.19#ibcon#read 5, iclass 35, count 2 2006.203.08:21:51.19#ibcon#about to read 6, iclass 35, count 2 2006.203.08:21:51.19#ibcon#read 6, iclass 35, count 2 2006.203.08:21:51.19#ibcon#end of sib2, iclass 35, count 2 2006.203.08:21:51.19#ibcon#*after write, iclass 35, count 2 2006.203.08:21:51.19#ibcon#*before return 0, iclass 35, count 2 2006.203.08:21:51.19#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.203.08:21:51.19#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.203.08:21:51.19#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.203.08:21:51.19#ibcon#ireg 7 cls_cnt 0 2006.203.08:21:51.19#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.203.08:21:51.31#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.203.08:21:51.31#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.203.08:21:51.31#ibcon#enter wrdev, iclass 35, count 0 2006.203.08:21:51.31#ibcon#first serial, iclass 35, count 0 2006.203.08:21:51.31#ibcon#enter sib2, iclass 35, count 0 2006.203.08:21:51.31#ibcon#flushed, iclass 35, count 0 2006.203.08:21:51.31#ibcon#about to write, iclass 35, count 0 2006.203.08:21:51.31#ibcon#wrote, iclass 35, count 0 2006.203.08:21:51.31#ibcon#about to read 3, iclass 35, count 0 2006.203.08:21:51.33#ibcon#read 3, iclass 35, count 0 2006.203.08:21:51.33#ibcon#about to read 4, iclass 35, count 0 2006.203.08:21:51.33#ibcon#read 4, iclass 35, count 0 2006.203.08:21:51.33#ibcon#about to read 5, iclass 35, count 0 2006.203.08:21:51.33#ibcon#read 5, iclass 35, count 0 2006.203.08:21:51.33#ibcon#about to read 6, iclass 35, count 0 2006.203.08:21:51.33#ibcon#read 6, iclass 35, count 0 2006.203.08:21:51.33#ibcon#end of sib2, iclass 35, count 0 2006.203.08:21:51.33#ibcon#*mode == 0, iclass 35, count 0 2006.203.08:21:51.33#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.203.08:21:51.33#ibcon#[25=USB\r\n] 2006.203.08:21:51.33#ibcon#*before write, iclass 35, count 0 2006.203.08:21:51.33#ibcon#enter sib2, iclass 35, count 0 2006.203.08:21:51.33#ibcon#flushed, iclass 35, count 0 2006.203.08:21:51.33#ibcon#about to write, iclass 35, count 0 2006.203.08:21:51.33#ibcon#wrote, iclass 35, count 0 2006.203.08:21:51.33#ibcon#about to read 3, iclass 35, count 0 2006.203.08:21:51.36#ibcon#read 3, iclass 35, count 0 2006.203.08:21:51.36#ibcon#about to read 4, iclass 35, count 0 2006.203.08:21:51.36#ibcon#read 4, iclass 35, count 0 2006.203.08:21:51.36#ibcon#about to read 5, iclass 35, count 0 2006.203.08:21:51.36#ibcon#read 5, iclass 35, count 0 2006.203.08:21:51.36#ibcon#about to read 6, iclass 35, count 0 2006.203.08:21:51.36#ibcon#read 6, iclass 35, count 0 2006.203.08:21:51.36#ibcon#end of sib2, iclass 35, count 0 2006.203.08:21:51.36#ibcon#*after write, iclass 35, count 0 2006.203.08:21:51.36#ibcon#*before return 0, iclass 35, count 0 2006.203.08:21:51.36#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.203.08:21:51.36#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.203.08:21:51.36#ibcon#about to clear, iclass 35 cls_cnt 0 2006.203.08:21:51.36#ibcon#cleared, iclass 35 cls_cnt 0 2006.203.08:21:51.36$vc4f8/valo=8,852.99 2006.203.08:21:51.36#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.203.08:21:51.36#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.203.08:21:51.36#ibcon#ireg 17 cls_cnt 0 2006.203.08:21:51.36#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.203.08:21:51.36#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.203.08:21:51.36#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.203.08:21:51.36#ibcon#enter wrdev, iclass 37, count 0 2006.203.08:21:51.36#ibcon#first serial, iclass 37, count 0 2006.203.08:21:51.36#ibcon#enter sib2, iclass 37, count 0 2006.203.08:21:51.36#ibcon#flushed, iclass 37, count 0 2006.203.08:21:51.36#ibcon#about to write, iclass 37, count 0 2006.203.08:21:51.36#ibcon#wrote, iclass 37, count 0 2006.203.08:21:51.36#ibcon#about to read 3, iclass 37, count 0 2006.203.08:21:51.38#ibcon#read 3, iclass 37, count 0 2006.203.08:21:51.38#ibcon#about to read 4, iclass 37, count 0 2006.203.08:21:51.38#ibcon#read 4, iclass 37, count 0 2006.203.08:21:51.38#ibcon#about to read 5, iclass 37, count 0 2006.203.08:21:51.38#ibcon#read 5, iclass 37, count 0 2006.203.08:21:51.38#ibcon#about to read 6, iclass 37, count 0 2006.203.08:21:51.38#ibcon#read 6, iclass 37, count 0 2006.203.08:21:51.38#ibcon#end of sib2, iclass 37, count 0 2006.203.08:21:51.38#ibcon#*mode == 0, iclass 37, count 0 2006.203.08:21:51.38#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.203.08:21:51.38#ibcon#[26=FRQ=08,852.99\r\n] 2006.203.08:21:51.38#ibcon#*before write, iclass 37, count 0 2006.203.08:21:51.38#ibcon#enter sib2, iclass 37, count 0 2006.203.08:21:51.38#ibcon#flushed, iclass 37, count 0 2006.203.08:21:51.38#ibcon#about to write, iclass 37, count 0 2006.203.08:21:51.38#ibcon#wrote, iclass 37, count 0 2006.203.08:21:51.38#ibcon#about to read 3, iclass 37, count 0 2006.203.08:21:51.42#ibcon#read 3, iclass 37, count 0 2006.203.08:21:51.42#ibcon#about to read 4, iclass 37, count 0 2006.203.08:21:51.42#ibcon#read 4, iclass 37, count 0 2006.203.08:21:51.42#ibcon#about to read 5, iclass 37, count 0 2006.203.08:21:51.42#ibcon#read 5, iclass 37, count 0 2006.203.08:21:51.42#ibcon#about to read 6, iclass 37, count 0 2006.203.08:21:51.42#ibcon#read 6, iclass 37, count 0 2006.203.08:21:51.42#ibcon#end of sib2, iclass 37, count 0 2006.203.08:21:51.42#ibcon#*after write, iclass 37, count 0 2006.203.08:21:51.42#ibcon#*before return 0, iclass 37, count 0 2006.203.08:21:51.42#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.203.08:21:51.42#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.203.08:21:51.42#ibcon#about to clear, iclass 37 cls_cnt 0 2006.203.08:21:51.42#ibcon#cleared, iclass 37 cls_cnt 0 2006.203.08:21:51.42$vc4f8/va=8,6 2006.203.08:21:51.42#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.203.08:21:51.42#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.203.08:21:51.42#ibcon#ireg 11 cls_cnt 2 2006.203.08:21:51.42#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.203.08:21:51.48#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.203.08:21:51.48#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.203.08:21:51.48#ibcon#enter wrdev, iclass 39, count 2 2006.203.08:21:51.48#ibcon#first serial, iclass 39, count 2 2006.203.08:21:51.48#ibcon#enter sib2, iclass 39, count 2 2006.203.08:21:51.48#ibcon#flushed, iclass 39, count 2 2006.203.08:21:51.48#ibcon#about to write, iclass 39, count 2 2006.203.08:21:51.48#ibcon#wrote, iclass 39, count 2 2006.203.08:21:51.48#ibcon#about to read 3, iclass 39, count 2 2006.203.08:21:51.50#ibcon#read 3, iclass 39, count 2 2006.203.08:21:51.50#ibcon#about to read 4, iclass 39, count 2 2006.203.08:21:51.50#ibcon#read 4, iclass 39, count 2 2006.203.08:21:51.50#ibcon#about to read 5, iclass 39, count 2 2006.203.08:21:51.50#ibcon#read 5, iclass 39, count 2 2006.203.08:21:51.50#ibcon#about to read 6, iclass 39, count 2 2006.203.08:21:51.50#ibcon#read 6, iclass 39, count 2 2006.203.08:21:51.50#ibcon#end of sib2, iclass 39, count 2 2006.203.08:21:51.50#ibcon#*mode == 0, iclass 39, count 2 2006.203.08:21:51.50#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.203.08:21:51.50#ibcon#[25=AT08-06\r\n] 2006.203.08:21:51.50#ibcon#*before write, iclass 39, count 2 2006.203.08:21:51.50#ibcon#enter sib2, iclass 39, count 2 2006.203.08:21:51.50#ibcon#flushed, iclass 39, count 2 2006.203.08:21:51.50#ibcon#about to write, iclass 39, count 2 2006.203.08:21:51.50#ibcon#wrote, iclass 39, count 2 2006.203.08:21:51.50#ibcon#about to read 3, iclass 39, count 2 2006.203.08:21:51.53#ibcon#read 3, iclass 39, count 2 2006.203.08:21:51.53#ibcon#about to read 4, iclass 39, count 2 2006.203.08:21:51.53#ibcon#read 4, iclass 39, count 2 2006.203.08:21:51.53#ibcon#about to read 5, iclass 39, count 2 2006.203.08:21:51.53#ibcon#read 5, iclass 39, count 2 2006.203.08:21:51.53#ibcon#about to read 6, iclass 39, count 2 2006.203.08:21:51.53#ibcon#read 6, iclass 39, count 2 2006.203.08:21:51.53#ibcon#end of sib2, iclass 39, count 2 2006.203.08:21:51.53#ibcon#*after write, iclass 39, count 2 2006.203.08:21:51.53#ibcon#*before return 0, iclass 39, count 2 2006.203.08:21:51.53#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.203.08:21:51.53#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.203.08:21:51.53#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.203.08:21:51.53#ibcon#ireg 7 cls_cnt 0 2006.203.08:21:51.53#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.203.08:21:51.65#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.203.08:21:51.65#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.203.08:21:51.65#ibcon#enter wrdev, iclass 39, count 0 2006.203.08:21:51.65#ibcon#first serial, iclass 39, count 0 2006.203.08:21:51.65#ibcon#enter sib2, iclass 39, count 0 2006.203.08:21:51.65#ibcon#flushed, iclass 39, count 0 2006.203.08:21:51.65#ibcon#about to write, iclass 39, count 0 2006.203.08:21:51.65#ibcon#wrote, iclass 39, count 0 2006.203.08:21:51.65#ibcon#about to read 3, iclass 39, count 0 2006.203.08:21:51.67#ibcon#read 3, iclass 39, count 0 2006.203.08:21:51.67#ibcon#about to read 4, iclass 39, count 0 2006.203.08:21:51.67#ibcon#read 4, iclass 39, count 0 2006.203.08:21:51.67#ibcon#about to read 5, iclass 39, count 0 2006.203.08:21:51.67#ibcon#read 5, iclass 39, count 0 2006.203.08:21:51.67#ibcon#about to read 6, iclass 39, count 0 2006.203.08:21:51.67#ibcon#read 6, iclass 39, count 0 2006.203.08:21:51.67#ibcon#end of sib2, iclass 39, count 0 2006.203.08:21:51.67#ibcon#*mode == 0, iclass 39, count 0 2006.203.08:21:51.67#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.203.08:21:51.67#ibcon#[25=USB\r\n] 2006.203.08:21:51.67#ibcon#*before write, iclass 39, count 0 2006.203.08:21:51.67#ibcon#enter sib2, iclass 39, count 0 2006.203.08:21:51.67#ibcon#flushed, iclass 39, count 0 2006.203.08:21:51.67#ibcon#about to write, iclass 39, count 0 2006.203.08:21:51.67#ibcon#wrote, iclass 39, count 0 2006.203.08:21:51.67#ibcon#about to read 3, iclass 39, count 0 2006.203.08:21:51.70#ibcon#read 3, iclass 39, count 0 2006.203.08:21:51.70#ibcon#about to read 4, iclass 39, count 0 2006.203.08:21:51.70#ibcon#read 4, iclass 39, count 0 2006.203.08:21:51.70#ibcon#about to read 5, iclass 39, count 0 2006.203.08:21:51.70#ibcon#read 5, iclass 39, count 0 2006.203.08:21:51.70#ibcon#about to read 6, iclass 39, count 0 2006.203.08:21:51.70#ibcon#read 6, iclass 39, count 0 2006.203.08:21:51.70#ibcon#end of sib2, iclass 39, count 0 2006.203.08:21:51.70#ibcon#*after write, iclass 39, count 0 2006.203.08:21:51.70#ibcon#*before return 0, iclass 39, count 0 2006.203.08:21:51.70#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.203.08:21:51.70#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.203.08:21:51.70#ibcon#about to clear, iclass 39 cls_cnt 0 2006.203.08:21:51.70#ibcon#cleared, iclass 39 cls_cnt 0 2006.203.08:21:51.70$vc4f8/vblo=1,632.99 2006.203.08:21:51.70#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.203.08:21:51.70#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.203.08:21:51.70#ibcon#ireg 17 cls_cnt 0 2006.203.08:21:51.70#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.203.08:21:51.70#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.203.08:21:51.70#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.203.08:21:51.70#ibcon#enter wrdev, iclass 3, count 0 2006.203.08:21:51.70#ibcon#first serial, iclass 3, count 0 2006.203.08:21:51.70#ibcon#enter sib2, iclass 3, count 0 2006.203.08:21:51.70#ibcon#flushed, iclass 3, count 0 2006.203.08:21:51.70#ibcon#about to write, iclass 3, count 0 2006.203.08:21:51.70#ibcon#wrote, iclass 3, count 0 2006.203.08:21:51.70#ibcon#about to read 3, iclass 3, count 0 2006.203.08:21:51.73#ibcon#read 3, iclass 3, count 0 2006.203.08:21:51.73#ibcon#about to read 4, iclass 3, count 0 2006.203.08:21:51.73#ibcon#read 4, iclass 3, count 0 2006.203.08:21:51.73#ibcon#about to read 5, iclass 3, count 0 2006.203.08:21:51.73#ibcon#read 5, iclass 3, count 0 2006.203.08:21:51.73#ibcon#about to read 6, iclass 3, count 0 2006.203.08:21:51.73#ibcon#read 6, iclass 3, count 0 2006.203.08:21:51.73#ibcon#end of sib2, iclass 3, count 0 2006.203.08:21:51.73#ibcon#*mode == 0, iclass 3, count 0 2006.203.08:21:51.73#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.203.08:21:51.73#ibcon#[28=FRQ=01,632.99\r\n] 2006.203.08:21:51.73#ibcon#*before write, iclass 3, count 0 2006.203.08:21:51.73#ibcon#enter sib2, iclass 3, count 0 2006.203.08:21:51.73#ibcon#flushed, iclass 3, count 0 2006.203.08:21:51.73#ibcon#about to write, iclass 3, count 0 2006.203.08:21:51.73#ibcon#wrote, iclass 3, count 0 2006.203.08:21:51.73#ibcon#about to read 3, iclass 3, count 0 2006.203.08:21:51.77#ibcon#read 3, iclass 3, count 0 2006.203.08:21:51.77#ibcon#about to read 4, iclass 3, count 0 2006.203.08:21:51.77#ibcon#read 4, iclass 3, count 0 2006.203.08:21:51.77#ibcon#about to read 5, iclass 3, count 0 2006.203.08:21:51.77#ibcon#read 5, iclass 3, count 0 2006.203.08:21:51.77#ibcon#about to read 6, iclass 3, count 0 2006.203.08:21:51.77#ibcon#read 6, iclass 3, count 0 2006.203.08:21:51.77#ibcon#end of sib2, iclass 3, count 0 2006.203.08:21:51.77#ibcon#*after write, iclass 3, count 0 2006.203.08:21:51.77#ibcon#*before return 0, iclass 3, count 0 2006.203.08:21:51.77#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.203.08:21:51.77#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.203.08:21:51.77#ibcon#about to clear, iclass 3 cls_cnt 0 2006.203.08:21:51.77#ibcon#cleared, iclass 3 cls_cnt 0 2006.203.08:21:51.77$vc4f8/vb=1,4 2006.203.08:21:51.77#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.203.08:21:51.77#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.203.08:21:51.77#ibcon#ireg 11 cls_cnt 2 2006.203.08:21:51.77#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.203.08:21:51.77#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.203.08:21:51.77#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.203.08:21:51.77#ibcon#enter wrdev, iclass 5, count 2 2006.203.08:21:51.77#ibcon#first serial, iclass 5, count 2 2006.203.08:21:51.77#ibcon#enter sib2, iclass 5, count 2 2006.203.08:21:51.77#ibcon#flushed, iclass 5, count 2 2006.203.08:21:51.77#ibcon#about to write, iclass 5, count 2 2006.203.08:21:51.77#ibcon#wrote, iclass 5, count 2 2006.203.08:21:51.77#ibcon#about to read 3, iclass 5, count 2 2006.203.08:21:51.79#ibcon#read 3, iclass 5, count 2 2006.203.08:21:51.79#ibcon#about to read 4, iclass 5, count 2 2006.203.08:21:51.79#ibcon#read 4, iclass 5, count 2 2006.203.08:21:51.79#ibcon#about to read 5, iclass 5, count 2 2006.203.08:21:51.79#ibcon#read 5, iclass 5, count 2 2006.203.08:21:51.79#ibcon#about to read 6, iclass 5, count 2 2006.203.08:21:51.79#ibcon#read 6, iclass 5, count 2 2006.203.08:21:51.79#ibcon#end of sib2, iclass 5, count 2 2006.203.08:21:51.79#ibcon#*mode == 0, iclass 5, count 2 2006.203.08:21:51.79#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.203.08:21:51.79#ibcon#[27=AT01-04\r\n] 2006.203.08:21:51.79#ibcon#*before write, iclass 5, count 2 2006.203.08:21:51.79#ibcon#enter sib2, iclass 5, count 2 2006.203.08:21:51.79#ibcon#flushed, iclass 5, count 2 2006.203.08:21:51.79#ibcon#about to write, iclass 5, count 2 2006.203.08:21:51.79#ibcon#wrote, iclass 5, count 2 2006.203.08:21:51.79#ibcon#about to read 3, iclass 5, count 2 2006.203.08:21:51.83#ibcon#read 3, iclass 5, count 2 2006.203.08:21:51.83#ibcon#about to read 4, iclass 5, count 2 2006.203.08:21:51.83#ibcon#read 4, iclass 5, count 2 2006.203.08:21:51.83#ibcon#about to read 5, iclass 5, count 2 2006.203.08:21:51.83#ibcon#read 5, iclass 5, count 2 2006.203.08:21:51.83#ibcon#about to read 6, iclass 5, count 2 2006.203.08:21:51.83#ibcon#read 6, iclass 5, count 2 2006.203.08:21:51.83#ibcon#end of sib2, iclass 5, count 2 2006.203.08:21:51.83#ibcon#*after write, iclass 5, count 2 2006.203.08:21:51.83#ibcon#*before return 0, iclass 5, count 2 2006.203.08:21:51.83#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.203.08:21:51.83#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.203.08:21:51.83#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.203.08:21:51.83#ibcon#ireg 7 cls_cnt 0 2006.203.08:21:51.83#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.203.08:21:51.94#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.203.08:21:51.94#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.203.08:21:51.94#ibcon#enter wrdev, iclass 5, count 0 2006.203.08:21:51.94#ibcon#first serial, iclass 5, count 0 2006.203.08:21:51.94#ibcon#enter sib2, iclass 5, count 0 2006.203.08:21:51.94#ibcon#flushed, iclass 5, count 0 2006.203.08:21:51.94#ibcon#about to write, iclass 5, count 0 2006.203.08:21:51.94#ibcon#wrote, iclass 5, count 0 2006.203.08:21:51.94#ibcon#about to read 3, iclass 5, count 0 2006.203.08:21:51.96#ibcon#read 3, iclass 5, count 0 2006.203.08:21:51.96#ibcon#about to read 4, iclass 5, count 0 2006.203.08:21:51.96#ibcon#read 4, iclass 5, count 0 2006.203.08:21:51.96#ibcon#about to read 5, iclass 5, count 0 2006.203.08:21:51.96#ibcon#read 5, iclass 5, count 0 2006.203.08:21:51.96#ibcon#about to read 6, iclass 5, count 0 2006.203.08:21:51.96#ibcon#read 6, iclass 5, count 0 2006.203.08:21:51.96#ibcon#end of sib2, iclass 5, count 0 2006.203.08:21:51.96#ibcon#*mode == 0, iclass 5, count 0 2006.203.08:21:51.96#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.203.08:21:51.96#ibcon#[27=USB\r\n] 2006.203.08:21:51.96#ibcon#*before write, iclass 5, count 0 2006.203.08:21:51.96#ibcon#enter sib2, iclass 5, count 0 2006.203.08:21:51.96#ibcon#flushed, iclass 5, count 0 2006.203.08:21:51.96#ibcon#about to write, iclass 5, count 0 2006.203.08:21:51.96#ibcon#wrote, iclass 5, count 0 2006.203.08:21:51.96#ibcon#about to read 3, iclass 5, count 0 2006.203.08:21:51.99#ibcon#read 3, iclass 5, count 0 2006.203.08:21:51.99#ibcon#about to read 4, iclass 5, count 0 2006.203.08:21:51.99#ibcon#read 4, iclass 5, count 0 2006.203.08:21:51.99#ibcon#about to read 5, iclass 5, count 0 2006.203.08:21:51.99#ibcon#read 5, iclass 5, count 0 2006.203.08:21:51.99#ibcon#about to read 6, iclass 5, count 0 2006.203.08:21:51.99#ibcon#read 6, iclass 5, count 0 2006.203.08:21:51.99#ibcon#end of sib2, iclass 5, count 0 2006.203.08:21:51.99#ibcon#*after write, iclass 5, count 0 2006.203.08:21:51.99#ibcon#*before return 0, iclass 5, count 0 2006.203.08:21:51.99#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.203.08:21:51.99#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.203.08:21:51.99#ibcon#about to clear, iclass 5 cls_cnt 0 2006.203.08:21:51.99#ibcon#cleared, iclass 5 cls_cnt 0 2006.203.08:21:51.99$vc4f8/vblo=2,640.99 2006.203.08:21:51.99#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.203.08:21:51.99#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.203.08:21:51.99#ibcon#ireg 17 cls_cnt 0 2006.203.08:21:51.99#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.203.08:21:51.99#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.203.08:21:51.99#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.203.08:21:51.99#ibcon#enter wrdev, iclass 7, count 0 2006.203.08:21:51.99#ibcon#first serial, iclass 7, count 0 2006.203.08:21:51.99#ibcon#enter sib2, iclass 7, count 0 2006.203.08:21:51.99#ibcon#flushed, iclass 7, count 0 2006.203.08:21:51.99#ibcon#about to write, iclass 7, count 0 2006.203.08:21:51.99#ibcon#wrote, iclass 7, count 0 2006.203.08:21:51.99#ibcon#about to read 3, iclass 7, count 0 2006.203.08:21:52.01#ibcon#read 3, iclass 7, count 0 2006.203.08:21:52.01#ibcon#about to read 4, iclass 7, count 0 2006.203.08:21:52.01#ibcon#read 4, iclass 7, count 0 2006.203.08:21:52.01#ibcon#about to read 5, iclass 7, count 0 2006.203.08:21:52.01#ibcon#read 5, iclass 7, count 0 2006.203.08:21:52.01#ibcon#about to read 6, iclass 7, count 0 2006.203.08:21:52.01#ibcon#read 6, iclass 7, count 0 2006.203.08:21:52.01#ibcon#end of sib2, iclass 7, count 0 2006.203.08:21:52.01#ibcon#*mode == 0, iclass 7, count 0 2006.203.08:21:52.01#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.203.08:21:52.01#ibcon#[28=FRQ=02,640.99\r\n] 2006.203.08:21:52.01#ibcon#*before write, iclass 7, count 0 2006.203.08:21:52.01#ibcon#enter sib2, iclass 7, count 0 2006.203.08:21:52.01#ibcon#flushed, iclass 7, count 0 2006.203.08:21:52.01#ibcon#about to write, iclass 7, count 0 2006.203.08:21:52.01#ibcon#wrote, iclass 7, count 0 2006.203.08:21:52.01#ibcon#about to read 3, iclass 7, count 0 2006.203.08:21:52.05#ibcon#read 3, iclass 7, count 0 2006.203.08:21:52.05#ibcon#about to read 4, iclass 7, count 0 2006.203.08:21:52.05#ibcon#read 4, iclass 7, count 0 2006.203.08:21:52.05#ibcon#about to read 5, iclass 7, count 0 2006.203.08:21:52.05#ibcon#read 5, iclass 7, count 0 2006.203.08:21:52.05#ibcon#about to read 6, iclass 7, count 0 2006.203.08:21:52.05#ibcon#read 6, iclass 7, count 0 2006.203.08:21:52.05#ibcon#end of sib2, iclass 7, count 0 2006.203.08:21:52.05#ibcon#*after write, iclass 7, count 0 2006.203.08:21:52.05#ibcon#*before return 0, iclass 7, count 0 2006.203.08:21:52.05#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.203.08:21:52.05#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.203.08:21:52.05#ibcon#about to clear, iclass 7 cls_cnt 0 2006.203.08:21:52.05#ibcon#cleared, iclass 7 cls_cnt 0 2006.203.08:21:52.05$vc4f8/vb=2,4 2006.203.08:21:52.05#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.203.08:21:52.05#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.203.08:21:52.05#ibcon#ireg 11 cls_cnt 2 2006.203.08:21:52.05#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.203.08:21:52.11#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.203.08:21:52.11#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.203.08:21:52.11#ibcon#enter wrdev, iclass 11, count 2 2006.203.08:21:52.11#ibcon#first serial, iclass 11, count 2 2006.203.08:21:52.11#ibcon#enter sib2, iclass 11, count 2 2006.203.08:21:52.11#ibcon#flushed, iclass 11, count 2 2006.203.08:21:52.11#ibcon#about to write, iclass 11, count 2 2006.203.08:21:52.11#ibcon#wrote, iclass 11, count 2 2006.203.08:21:52.11#ibcon#about to read 3, iclass 11, count 2 2006.203.08:21:52.13#ibcon#read 3, iclass 11, count 2 2006.203.08:21:52.13#ibcon#about to read 4, iclass 11, count 2 2006.203.08:21:52.13#ibcon#read 4, iclass 11, count 2 2006.203.08:21:52.13#ibcon#about to read 5, iclass 11, count 2 2006.203.08:21:52.13#ibcon#read 5, iclass 11, count 2 2006.203.08:21:52.13#ibcon#about to read 6, iclass 11, count 2 2006.203.08:21:52.13#ibcon#read 6, iclass 11, count 2 2006.203.08:21:52.13#ibcon#end of sib2, iclass 11, count 2 2006.203.08:21:52.13#ibcon#*mode == 0, iclass 11, count 2 2006.203.08:21:52.13#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.203.08:21:52.13#ibcon#[27=AT02-04\r\n] 2006.203.08:21:52.13#ibcon#*before write, iclass 11, count 2 2006.203.08:21:52.13#ibcon#enter sib2, iclass 11, count 2 2006.203.08:21:52.13#ibcon#flushed, iclass 11, count 2 2006.203.08:21:52.13#ibcon#about to write, iclass 11, count 2 2006.203.08:21:52.13#ibcon#wrote, iclass 11, count 2 2006.203.08:21:52.13#ibcon#about to read 3, iclass 11, count 2 2006.203.08:21:52.16#ibcon#read 3, iclass 11, count 2 2006.203.08:21:52.16#ibcon#about to read 4, iclass 11, count 2 2006.203.08:21:52.16#ibcon#read 4, iclass 11, count 2 2006.203.08:21:52.16#ibcon#about to read 5, iclass 11, count 2 2006.203.08:21:52.16#ibcon#read 5, iclass 11, count 2 2006.203.08:21:52.16#ibcon#about to read 6, iclass 11, count 2 2006.203.08:21:52.16#ibcon#read 6, iclass 11, count 2 2006.203.08:21:52.16#ibcon#end of sib2, iclass 11, count 2 2006.203.08:21:52.16#ibcon#*after write, iclass 11, count 2 2006.203.08:21:52.16#ibcon#*before return 0, iclass 11, count 2 2006.203.08:21:52.16#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.203.08:21:52.16#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.203.08:21:52.16#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.203.08:21:52.16#ibcon#ireg 7 cls_cnt 0 2006.203.08:21:52.16#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.203.08:21:52.28#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.203.08:21:52.28#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.203.08:21:52.28#ibcon#enter wrdev, iclass 11, count 0 2006.203.08:21:52.28#ibcon#first serial, iclass 11, count 0 2006.203.08:21:52.28#ibcon#enter sib2, iclass 11, count 0 2006.203.08:21:52.28#ibcon#flushed, iclass 11, count 0 2006.203.08:21:52.28#ibcon#about to write, iclass 11, count 0 2006.203.08:21:52.28#ibcon#wrote, iclass 11, count 0 2006.203.08:21:52.28#ibcon#about to read 3, iclass 11, count 0 2006.203.08:21:52.30#ibcon#read 3, iclass 11, count 0 2006.203.08:21:52.30#ibcon#about to read 4, iclass 11, count 0 2006.203.08:21:52.30#ibcon#read 4, iclass 11, count 0 2006.203.08:21:52.30#ibcon#about to read 5, iclass 11, count 0 2006.203.08:21:52.30#ibcon#read 5, iclass 11, count 0 2006.203.08:21:52.30#ibcon#about to read 6, iclass 11, count 0 2006.203.08:21:52.30#ibcon#read 6, iclass 11, count 0 2006.203.08:21:52.30#ibcon#end of sib2, iclass 11, count 0 2006.203.08:21:52.30#ibcon#*mode == 0, iclass 11, count 0 2006.203.08:21:52.30#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.203.08:21:52.30#ibcon#[27=USB\r\n] 2006.203.08:21:52.30#ibcon#*before write, iclass 11, count 0 2006.203.08:21:52.30#ibcon#enter sib2, iclass 11, count 0 2006.203.08:21:52.30#ibcon#flushed, iclass 11, count 0 2006.203.08:21:52.30#ibcon#about to write, iclass 11, count 0 2006.203.08:21:52.30#ibcon#wrote, iclass 11, count 0 2006.203.08:21:52.30#ibcon#about to read 3, iclass 11, count 0 2006.203.08:21:52.33#ibcon#read 3, iclass 11, count 0 2006.203.08:21:52.33#ibcon#about to read 4, iclass 11, count 0 2006.203.08:21:52.33#ibcon#read 4, iclass 11, count 0 2006.203.08:21:52.33#ibcon#about to read 5, iclass 11, count 0 2006.203.08:21:52.33#ibcon#read 5, iclass 11, count 0 2006.203.08:21:52.33#ibcon#about to read 6, iclass 11, count 0 2006.203.08:21:52.33#ibcon#read 6, iclass 11, count 0 2006.203.08:21:52.33#ibcon#end of sib2, iclass 11, count 0 2006.203.08:21:52.33#ibcon#*after write, iclass 11, count 0 2006.203.08:21:52.33#ibcon#*before return 0, iclass 11, count 0 2006.203.08:21:52.33#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.203.08:21:52.33#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.203.08:21:52.33#ibcon#about to clear, iclass 11 cls_cnt 0 2006.203.08:21:52.33#ibcon#cleared, iclass 11 cls_cnt 0 2006.203.08:21:52.33$vc4f8/vblo=3,656.99 2006.203.08:21:52.33#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.203.08:21:52.33#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.203.08:21:52.33#ibcon#ireg 17 cls_cnt 0 2006.203.08:21:52.33#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.203.08:21:52.33#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.203.08:21:52.33#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.203.08:21:52.33#ibcon#enter wrdev, iclass 13, count 0 2006.203.08:21:52.33#ibcon#first serial, iclass 13, count 0 2006.203.08:21:52.33#ibcon#enter sib2, iclass 13, count 0 2006.203.08:21:52.33#ibcon#flushed, iclass 13, count 0 2006.203.08:21:52.33#ibcon#about to write, iclass 13, count 0 2006.203.08:21:52.33#ibcon#wrote, iclass 13, count 0 2006.203.08:21:52.33#ibcon#about to read 3, iclass 13, count 0 2006.203.08:21:52.35#ibcon#read 3, iclass 13, count 0 2006.203.08:21:52.35#ibcon#about to read 4, iclass 13, count 0 2006.203.08:21:52.35#ibcon#read 4, iclass 13, count 0 2006.203.08:21:52.35#ibcon#about to read 5, iclass 13, count 0 2006.203.08:21:52.35#ibcon#read 5, iclass 13, count 0 2006.203.08:21:52.35#ibcon#about to read 6, iclass 13, count 0 2006.203.08:21:52.35#ibcon#read 6, iclass 13, count 0 2006.203.08:21:52.35#ibcon#end of sib2, iclass 13, count 0 2006.203.08:21:52.35#ibcon#*mode == 0, iclass 13, count 0 2006.203.08:21:52.35#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.203.08:21:52.35#ibcon#[28=FRQ=03,656.99\r\n] 2006.203.08:21:52.35#ibcon#*before write, iclass 13, count 0 2006.203.08:21:52.35#ibcon#enter sib2, iclass 13, count 0 2006.203.08:21:52.35#ibcon#flushed, iclass 13, count 0 2006.203.08:21:52.35#ibcon#about to write, iclass 13, count 0 2006.203.08:21:52.35#ibcon#wrote, iclass 13, count 0 2006.203.08:21:52.35#ibcon#about to read 3, iclass 13, count 0 2006.203.08:21:52.39#ibcon#read 3, iclass 13, count 0 2006.203.08:21:52.39#ibcon#about to read 4, iclass 13, count 0 2006.203.08:21:52.39#ibcon#read 4, iclass 13, count 0 2006.203.08:21:52.39#ibcon#about to read 5, iclass 13, count 0 2006.203.08:21:52.39#ibcon#read 5, iclass 13, count 0 2006.203.08:21:52.39#ibcon#about to read 6, iclass 13, count 0 2006.203.08:21:52.39#ibcon#read 6, iclass 13, count 0 2006.203.08:21:52.39#ibcon#end of sib2, iclass 13, count 0 2006.203.08:21:52.39#ibcon#*after write, iclass 13, count 0 2006.203.08:21:52.39#ibcon#*before return 0, iclass 13, count 0 2006.203.08:21:52.39#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.203.08:21:52.39#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.203.08:21:52.39#ibcon#about to clear, iclass 13 cls_cnt 0 2006.203.08:21:52.39#ibcon#cleared, iclass 13 cls_cnt 0 2006.203.08:21:52.39$vc4f8/vb=3,4 2006.203.08:21:52.39#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.203.08:21:52.39#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.203.08:21:52.39#ibcon#ireg 11 cls_cnt 2 2006.203.08:21:52.39#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.203.08:21:52.45#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.203.08:21:52.45#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.203.08:21:52.45#ibcon#enter wrdev, iclass 15, count 2 2006.203.08:21:52.45#ibcon#first serial, iclass 15, count 2 2006.203.08:21:52.45#ibcon#enter sib2, iclass 15, count 2 2006.203.08:21:52.45#ibcon#flushed, iclass 15, count 2 2006.203.08:21:52.45#ibcon#about to write, iclass 15, count 2 2006.203.08:21:52.45#ibcon#wrote, iclass 15, count 2 2006.203.08:21:52.45#ibcon#about to read 3, iclass 15, count 2 2006.203.08:21:52.47#ibcon#read 3, iclass 15, count 2 2006.203.08:21:52.47#ibcon#about to read 4, iclass 15, count 2 2006.203.08:21:52.47#ibcon#read 4, iclass 15, count 2 2006.203.08:21:52.47#ibcon#about to read 5, iclass 15, count 2 2006.203.08:21:52.47#ibcon#read 5, iclass 15, count 2 2006.203.08:21:52.47#ibcon#about to read 6, iclass 15, count 2 2006.203.08:21:52.47#ibcon#read 6, iclass 15, count 2 2006.203.08:21:52.47#ibcon#end of sib2, iclass 15, count 2 2006.203.08:21:52.47#ibcon#*mode == 0, iclass 15, count 2 2006.203.08:21:52.47#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.203.08:21:52.47#ibcon#[27=AT03-04\r\n] 2006.203.08:21:52.47#ibcon#*before write, iclass 15, count 2 2006.203.08:21:52.47#ibcon#enter sib2, iclass 15, count 2 2006.203.08:21:52.47#ibcon#flushed, iclass 15, count 2 2006.203.08:21:52.47#ibcon#about to write, iclass 15, count 2 2006.203.08:21:52.47#ibcon#wrote, iclass 15, count 2 2006.203.08:21:52.47#ibcon#about to read 3, iclass 15, count 2 2006.203.08:21:52.50#ibcon#read 3, iclass 15, count 2 2006.203.08:21:52.50#ibcon#about to read 4, iclass 15, count 2 2006.203.08:21:52.50#ibcon#read 4, iclass 15, count 2 2006.203.08:21:52.50#ibcon#about to read 5, iclass 15, count 2 2006.203.08:21:52.50#ibcon#read 5, iclass 15, count 2 2006.203.08:21:52.50#ibcon#about to read 6, iclass 15, count 2 2006.203.08:21:52.50#ibcon#read 6, iclass 15, count 2 2006.203.08:21:52.50#ibcon#end of sib2, iclass 15, count 2 2006.203.08:21:52.50#ibcon#*after write, iclass 15, count 2 2006.203.08:21:52.50#ibcon#*before return 0, iclass 15, count 2 2006.203.08:21:52.50#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.203.08:21:52.50#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.203.08:21:52.50#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.203.08:21:52.50#ibcon#ireg 7 cls_cnt 0 2006.203.08:21:52.50#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.203.08:21:52.62#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.203.08:21:52.62#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.203.08:21:52.62#ibcon#enter wrdev, iclass 15, count 0 2006.203.08:21:52.62#ibcon#first serial, iclass 15, count 0 2006.203.08:21:52.62#ibcon#enter sib2, iclass 15, count 0 2006.203.08:21:52.62#ibcon#flushed, iclass 15, count 0 2006.203.08:21:52.62#ibcon#about to write, iclass 15, count 0 2006.203.08:21:52.62#ibcon#wrote, iclass 15, count 0 2006.203.08:21:52.62#ibcon#about to read 3, iclass 15, count 0 2006.203.08:21:52.64#ibcon#read 3, iclass 15, count 0 2006.203.08:21:52.64#ibcon#about to read 4, iclass 15, count 0 2006.203.08:21:52.64#ibcon#read 4, iclass 15, count 0 2006.203.08:21:52.64#ibcon#about to read 5, iclass 15, count 0 2006.203.08:21:52.64#ibcon#read 5, iclass 15, count 0 2006.203.08:21:52.64#ibcon#about to read 6, iclass 15, count 0 2006.203.08:21:52.64#ibcon#read 6, iclass 15, count 0 2006.203.08:21:52.64#ibcon#end of sib2, iclass 15, count 0 2006.203.08:21:52.64#ibcon#*mode == 0, iclass 15, count 0 2006.203.08:21:52.64#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.203.08:21:52.64#ibcon#[27=USB\r\n] 2006.203.08:21:52.64#ibcon#*before write, iclass 15, count 0 2006.203.08:21:52.64#ibcon#enter sib2, iclass 15, count 0 2006.203.08:21:52.64#ibcon#flushed, iclass 15, count 0 2006.203.08:21:52.64#ibcon#about to write, iclass 15, count 0 2006.203.08:21:52.64#ibcon#wrote, iclass 15, count 0 2006.203.08:21:52.64#ibcon#about to read 3, iclass 15, count 0 2006.203.08:21:52.67#ibcon#read 3, iclass 15, count 0 2006.203.08:21:52.67#ibcon#about to read 4, iclass 15, count 0 2006.203.08:21:52.67#ibcon#read 4, iclass 15, count 0 2006.203.08:21:52.67#ibcon#about to read 5, iclass 15, count 0 2006.203.08:21:52.67#ibcon#read 5, iclass 15, count 0 2006.203.08:21:52.67#ibcon#about to read 6, iclass 15, count 0 2006.203.08:21:52.67#ibcon#read 6, iclass 15, count 0 2006.203.08:21:52.67#ibcon#end of sib2, iclass 15, count 0 2006.203.08:21:52.67#ibcon#*after write, iclass 15, count 0 2006.203.08:21:52.67#ibcon#*before return 0, iclass 15, count 0 2006.203.08:21:52.67#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.203.08:21:52.67#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.203.08:21:52.67#ibcon#about to clear, iclass 15 cls_cnt 0 2006.203.08:21:52.67#ibcon#cleared, iclass 15 cls_cnt 0 2006.203.08:21:52.67$vc4f8/vblo=4,712.99 2006.203.08:21:52.67#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.203.08:21:52.67#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.203.08:21:52.67#ibcon#ireg 17 cls_cnt 0 2006.203.08:21:52.67#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.203.08:21:52.67#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.203.08:21:52.67#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.203.08:21:52.67#ibcon#enter wrdev, iclass 17, count 0 2006.203.08:21:52.67#ibcon#first serial, iclass 17, count 0 2006.203.08:21:52.67#ibcon#enter sib2, iclass 17, count 0 2006.203.08:21:52.67#ibcon#flushed, iclass 17, count 0 2006.203.08:21:52.67#ibcon#about to write, iclass 17, count 0 2006.203.08:21:52.67#ibcon#wrote, iclass 17, count 0 2006.203.08:21:52.67#ibcon#about to read 3, iclass 17, count 0 2006.203.08:21:52.69#ibcon#read 3, iclass 17, count 0 2006.203.08:21:52.69#ibcon#about to read 4, iclass 17, count 0 2006.203.08:21:52.69#ibcon#read 4, iclass 17, count 0 2006.203.08:21:52.69#ibcon#about to read 5, iclass 17, count 0 2006.203.08:21:52.69#ibcon#read 5, iclass 17, count 0 2006.203.08:21:52.69#ibcon#about to read 6, iclass 17, count 0 2006.203.08:21:52.69#ibcon#read 6, iclass 17, count 0 2006.203.08:21:52.69#ibcon#end of sib2, iclass 17, count 0 2006.203.08:21:52.69#ibcon#*mode == 0, iclass 17, count 0 2006.203.08:21:52.69#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.203.08:21:52.69#ibcon#[28=FRQ=04,712.99\r\n] 2006.203.08:21:52.69#ibcon#*before write, iclass 17, count 0 2006.203.08:21:52.69#ibcon#enter sib2, iclass 17, count 0 2006.203.08:21:52.69#ibcon#flushed, iclass 17, count 0 2006.203.08:21:52.69#ibcon#about to write, iclass 17, count 0 2006.203.08:21:52.69#ibcon#wrote, iclass 17, count 0 2006.203.08:21:52.69#ibcon#about to read 3, iclass 17, count 0 2006.203.08:21:52.73#ibcon#read 3, iclass 17, count 0 2006.203.08:21:52.73#ibcon#about to read 4, iclass 17, count 0 2006.203.08:21:52.73#ibcon#read 4, iclass 17, count 0 2006.203.08:21:52.73#ibcon#about to read 5, iclass 17, count 0 2006.203.08:21:52.73#ibcon#read 5, iclass 17, count 0 2006.203.08:21:52.73#ibcon#about to read 6, iclass 17, count 0 2006.203.08:21:52.73#ibcon#read 6, iclass 17, count 0 2006.203.08:21:52.73#ibcon#end of sib2, iclass 17, count 0 2006.203.08:21:52.73#ibcon#*after write, iclass 17, count 0 2006.203.08:21:52.73#ibcon#*before return 0, iclass 17, count 0 2006.203.08:21:52.73#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.203.08:21:52.73#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.203.08:21:52.73#ibcon#about to clear, iclass 17 cls_cnt 0 2006.203.08:21:52.73#ibcon#cleared, iclass 17 cls_cnt 0 2006.203.08:21:52.73$vc4f8/vb=4,4 2006.203.08:21:52.73#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.203.08:21:52.73#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.203.08:21:52.73#ibcon#ireg 11 cls_cnt 2 2006.203.08:21:52.73#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.203.08:21:52.79#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.203.08:21:52.79#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.203.08:21:52.79#ibcon#enter wrdev, iclass 19, count 2 2006.203.08:21:52.79#ibcon#first serial, iclass 19, count 2 2006.203.08:21:52.79#ibcon#enter sib2, iclass 19, count 2 2006.203.08:21:52.79#ibcon#flushed, iclass 19, count 2 2006.203.08:21:52.79#ibcon#about to write, iclass 19, count 2 2006.203.08:21:52.79#ibcon#wrote, iclass 19, count 2 2006.203.08:21:52.79#ibcon#about to read 3, iclass 19, count 2 2006.203.08:21:52.81#ibcon#read 3, iclass 19, count 2 2006.203.08:21:52.81#ibcon#about to read 4, iclass 19, count 2 2006.203.08:21:52.81#ibcon#read 4, iclass 19, count 2 2006.203.08:21:52.81#ibcon#about to read 5, iclass 19, count 2 2006.203.08:21:52.81#ibcon#read 5, iclass 19, count 2 2006.203.08:21:52.81#ibcon#about to read 6, iclass 19, count 2 2006.203.08:21:52.81#ibcon#read 6, iclass 19, count 2 2006.203.08:21:52.81#ibcon#end of sib2, iclass 19, count 2 2006.203.08:21:52.81#ibcon#*mode == 0, iclass 19, count 2 2006.203.08:21:52.81#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.203.08:21:52.81#ibcon#[27=AT04-04\r\n] 2006.203.08:21:52.81#ibcon#*before write, iclass 19, count 2 2006.203.08:21:52.81#ibcon#enter sib2, iclass 19, count 2 2006.203.08:21:52.81#ibcon#flushed, iclass 19, count 2 2006.203.08:21:52.81#ibcon#about to write, iclass 19, count 2 2006.203.08:21:52.81#ibcon#wrote, iclass 19, count 2 2006.203.08:21:52.81#ibcon#about to read 3, iclass 19, count 2 2006.203.08:21:52.84#ibcon#read 3, iclass 19, count 2 2006.203.08:21:52.84#ibcon#about to read 4, iclass 19, count 2 2006.203.08:21:52.84#ibcon#read 4, iclass 19, count 2 2006.203.08:21:52.84#ibcon#about to read 5, iclass 19, count 2 2006.203.08:21:52.84#ibcon#read 5, iclass 19, count 2 2006.203.08:21:52.84#ibcon#about to read 6, iclass 19, count 2 2006.203.08:21:52.84#ibcon#read 6, iclass 19, count 2 2006.203.08:21:52.84#ibcon#end of sib2, iclass 19, count 2 2006.203.08:21:52.84#ibcon#*after write, iclass 19, count 2 2006.203.08:21:52.84#ibcon#*before return 0, iclass 19, count 2 2006.203.08:21:52.84#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.203.08:21:52.84#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.203.08:21:52.84#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.203.08:21:52.84#ibcon#ireg 7 cls_cnt 0 2006.203.08:21:52.84#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.203.08:21:52.96#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.203.08:21:52.96#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.203.08:21:52.96#ibcon#enter wrdev, iclass 19, count 0 2006.203.08:21:52.96#ibcon#first serial, iclass 19, count 0 2006.203.08:21:52.96#ibcon#enter sib2, iclass 19, count 0 2006.203.08:21:52.96#ibcon#flushed, iclass 19, count 0 2006.203.08:21:52.96#ibcon#about to write, iclass 19, count 0 2006.203.08:21:52.96#ibcon#wrote, iclass 19, count 0 2006.203.08:21:52.96#ibcon#about to read 3, iclass 19, count 0 2006.203.08:21:52.98#ibcon#read 3, iclass 19, count 0 2006.203.08:21:52.98#ibcon#about to read 4, iclass 19, count 0 2006.203.08:21:52.98#ibcon#read 4, iclass 19, count 0 2006.203.08:21:52.98#ibcon#about to read 5, iclass 19, count 0 2006.203.08:21:52.98#ibcon#read 5, iclass 19, count 0 2006.203.08:21:52.98#ibcon#about to read 6, iclass 19, count 0 2006.203.08:21:52.98#ibcon#read 6, iclass 19, count 0 2006.203.08:21:52.98#ibcon#end of sib2, iclass 19, count 0 2006.203.08:21:52.98#ibcon#*mode == 0, iclass 19, count 0 2006.203.08:21:52.98#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.203.08:21:52.98#ibcon#[27=USB\r\n] 2006.203.08:21:52.98#ibcon#*before write, iclass 19, count 0 2006.203.08:21:52.98#ibcon#enter sib2, iclass 19, count 0 2006.203.08:21:52.98#ibcon#flushed, iclass 19, count 0 2006.203.08:21:52.98#ibcon#about to write, iclass 19, count 0 2006.203.08:21:52.98#ibcon#wrote, iclass 19, count 0 2006.203.08:21:52.98#ibcon#about to read 3, iclass 19, count 0 2006.203.08:21:53.01#ibcon#read 3, iclass 19, count 0 2006.203.08:21:53.01#ibcon#about to read 4, iclass 19, count 0 2006.203.08:21:53.01#ibcon#read 4, iclass 19, count 0 2006.203.08:21:53.01#ibcon#about to read 5, iclass 19, count 0 2006.203.08:21:53.01#ibcon#read 5, iclass 19, count 0 2006.203.08:21:53.01#ibcon#about to read 6, iclass 19, count 0 2006.203.08:21:53.01#ibcon#read 6, iclass 19, count 0 2006.203.08:21:53.01#ibcon#end of sib2, iclass 19, count 0 2006.203.08:21:53.01#ibcon#*after write, iclass 19, count 0 2006.203.08:21:53.01#ibcon#*before return 0, iclass 19, count 0 2006.203.08:21:53.01#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.203.08:21:53.01#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.203.08:21:53.01#ibcon#about to clear, iclass 19 cls_cnt 0 2006.203.08:21:53.01#ibcon#cleared, iclass 19 cls_cnt 0 2006.203.08:21:53.01$vc4f8/vblo=5,744.99 2006.203.08:21:53.01#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.203.08:21:53.01#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.203.08:21:53.01#ibcon#ireg 17 cls_cnt 0 2006.203.08:21:53.01#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.203.08:21:53.01#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.203.08:21:53.01#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.203.08:21:53.01#ibcon#enter wrdev, iclass 21, count 0 2006.203.08:21:53.01#ibcon#first serial, iclass 21, count 0 2006.203.08:21:53.01#ibcon#enter sib2, iclass 21, count 0 2006.203.08:21:53.01#ibcon#flushed, iclass 21, count 0 2006.203.08:21:53.01#ibcon#about to write, iclass 21, count 0 2006.203.08:21:53.01#ibcon#wrote, iclass 21, count 0 2006.203.08:21:53.01#ibcon#about to read 3, iclass 21, count 0 2006.203.08:21:53.03#ibcon#read 3, iclass 21, count 0 2006.203.08:21:53.03#ibcon#about to read 4, iclass 21, count 0 2006.203.08:21:53.03#ibcon#read 4, iclass 21, count 0 2006.203.08:21:53.03#ibcon#about to read 5, iclass 21, count 0 2006.203.08:21:53.03#ibcon#read 5, iclass 21, count 0 2006.203.08:21:53.03#ibcon#about to read 6, iclass 21, count 0 2006.203.08:21:53.03#ibcon#read 6, iclass 21, count 0 2006.203.08:21:53.03#ibcon#end of sib2, iclass 21, count 0 2006.203.08:21:53.03#ibcon#*mode == 0, iclass 21, count 0 2006.203.08:21:53.03#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.203.08:21:53.03#ibcon#[28=FRQ=05,744.99\r\n] 2006.203.08:21:53.03#ibcon#*before write, iclass 21, count 0 2006.203.08:21:53.03#ibcon#enter sib2, iclass 21, count 0 2006.203.08:21:53.03#ibcon#flushed, iclass 21, count 0 2006.203.08:21:53.03#ibcon#about to write, iclass 21, count 0 2006.203.08:21:53.03#ibcon#wrote, iclass 21, count 0 2006.203.08:21:53.03#ibcon#about to read 3, iclass 21, count 0 2006.203.08:21:53.07#ibcon#read 3, iclass 21, count 0 2006.203.08:21:53.07#ibcon#about to read 4, iclass 21, count 0 2006.203.08:21:53.07#ibcon#read 4, iclass 21, count 0 2006.203.08:21:53.07#ibcon#about to read 5, iclass 21, count 0 2006.203.08:21:53.07#ibcon#read 5, iclass 21, count 0 2006.203.08:21:53.07#ibcon#about to read 6, iclass 21, count 0 2006.203.08:21:53.07#ibcon#read 6, iclass 21, count 0 2006.203.08:21:53.07#ibcon#end of sib2, iclass 21, count 0 2006.203.08:21:53.07#ibcon#*after write, iclass 21, count 0 2006.203.08:21:53.07#ibcon#*before return 0, iclass 21, count 0 2006.203.08:21:53.07#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.203.08:21:53.07#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.203.08:21:53.07#ibcon#about to clear, iclass 21 cls_cnt 0 2006.203.08:21:53.07#ibcon#cleared, iclass 21 cls_cnt 0 2006.203.08:21:53.07$vc4f8/vb=5,3 2006.203.08:21:53.07#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.203.08:21:53.07#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.203.08:21:53.07#ibcon#ireg 11 cls_cnt 2 2006.203.08:21:53.07#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.203.08:21:53.13#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.203.08:21:53.13#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.203.08:21:53.13#ibcon#enter wrdev, iclass 23, count 2 2006.203.08:21:53.13#ibcon#first serial, iclass 23, count 2 2006.203.08:21:53.13#ibcon#enter sib2, iclass 23, count 2 2006.203.08:21:53.13#ibcon#flushed, iclass 23, count 2 2006.203.08:21:53.13#ibcon#about to write, iclass 23, count 2 2006.203.08:21:53.13#ibcon#wrote, iclass 23, count 2 2006.203.08:21:53.13#ibcon#about to read 3, iclass 23, count 2 2006.203.08:21:53.15#ibcon#read 3, iclass 23, count 2 2006.203.08:21:53.15#ibcon#about to read 4, iclass 23, count 2 2006.203.08:21:53.15#ibcon#read 4, iclass 23, count 2 2006.203.08:21:53.15#ibcon#about to read 5, iclass 23, count 2 2006.203.08:21:53.15#ibcon#read 5, iclass 23, count 2 2006.203.08:21:53.15#ibcon#about to read 6, iclass 23, count 2 2006.203.08:21:53.15#ibcon#read 6, iclass 23, count 2 2006.203.08:21:53.15#ibcon#end of sib2, iclass 23, count 2 2006.203.08:21:53.15#ibcon#*mode == 0, iclass 23, count 2 2006.203.08:21:53.15#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.203.08:21:53.15#ibcon#[27=AT05-03\r\n] 2006.203.08:21:53.15#ibcon#*before write, iclass 23, count 2 2006.203.08:21:53.15#ibcon#enter sib2, iclass 23, count 2 2006.203.08:21:53.15#ibcon#flushed, iclass 23, count 2 2006.203.08:21:53.15#ibcon#about to write, iclass 23, count 2 2006.203.08:21:53.15#ibcon#wrote, iclass 23, count 2 2006.203.08:21:53.15#ibcon#about to read 3, iclass 23, count 2 2006.203.08:21:53.18#ibcon#read 3, iclass 23, count 2 2006.203.08:21:53.18#ibcon#about to read 4, iclass 23, count 2 2006.203.08:21:53.18#ibcon#read 4, iclass 23, count 2 2006.203.08:21:53.18#ibcon#about to read 5, iclass 23, count 2 2006.203.08:21:53.18#ibcon#read 5, iclass 23, count 2 2006.203.08:21:53.18#ibcon#about to read 6, iclass 23, count 2 2006.203.08:21:53.18#ibcon#read 6, iclass 23, count 2 2006.203.08:21:53.18#ibcon#end of sib2, iclass 23, count 2 2006.203.08:21:53.18#ibcon#*after write, iclass 23, count 2 2006.203.08:21:53.18#ibcon#*before return 0, iclass 23, count 2 2006.203.08:21:53.18#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.203.08:21:53.18#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.203.08:21:53.18#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.203.08:21:53.18#ibcon#ireg 7 cls_cnt 0 2006.203.08:21:53.18#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.203.08:21:53.30#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.203.08:21:53.30#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.203.08:21:53.30#ibcon#enter wrdev, iclass 23, count 0 2006.203.08:21:53.30#ibcon#first serial, iclass 23, count 0 2006.203.08:21:53.30#ibcon#enter sib2, iclass 23, count 0 2006.203.08:21:53.30#ibcon#flushed, iclass 23, count 0 2006.203.08:21:53.30#ibcon#about to write, iclass 23, count 0 2006.203.08:21:53.30#ibcon#wrote, iclass 23, count 0 2006.203.08:21:53.30#ibcon#about to read 3, iclass 23, count 0 2006.203.08:21:53.32#ibcon#read 3, iclass 23, count 0 2006.203.08:21:53.32#ibcon#about to read 4, iclass 23, count 0 2006.203.08:21:53.32#ibcon#read 4, iclass 23, count 0 2006.203.08:21:53.32#ibcon#about to read 5, iclass 23, count 0 2006.203.08:21:53.32#ibcon#read 5, iclass 23, count 0 2006.203.08:21:53.32#ibcon#about to read 6, iclass 23, count 0 2006.203.08:21:53.32#ibcon#read 6, iclass 23, count 0 2006.203.08:21:53.32#ibcon#end of sib2, iclass 23, count 0 2006.203.08:21:53.32#ibcon#*mode == 0, iclass 23, count 0 2006.203.08:21:53.32#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.203.08:21:53.32#ibcon#[27=USB\r\n] 2006.203.08:21:53.32#ibcon#*before write, iclass 23, count 0 2006.203.08:21:53.32#ibcon#enter sib2, iclass 23, count 0 2006.203.08:21:53.32#ibcon#flushed, iclass 23, count 0 2006.203.08:21:53.32#ibcon#about to write, iclass 23, count 0 2006.203.08:21:53.32#ibcon#wrote, iclass 23, count 0 2006.203.08:21:53.32#ibcon#about to read 3, iclass 23, count 0 2006.203.08:21:53.35#ibcon#read 3, iclass 23, count 0 2006.203.08:21:53.35#ibcon#about to read 4, iclass 23, count 0 2006.203.08:21:53.35#ibcon#read 4, iclass 23, count 0 2006.203.08:21:53.35#ibcon#about to read 5, iclass 23, count 0 2006.203.08:21:53.35#ibcon#read 5, iclass 23, count 0 2006.203.08:21:53.35#ibcon#about to read 6, iclass 23, count 0 2006.203.08:21:53.35#ibcon#read 6, iclass 23, count 0 2006.203.08:21:53.35#ibcon#end of sib2, iclass 23, count 0 2006.203.08:21:53.35#ibcon#*after write, iclass 23, count 0 2006.203.08:21:53.35#ibcon#*before return 0, iclass 23, count 0 2006.203.08:21:53.35#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.203.08:21:53.35#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.203.08:21:53.35#ibcon#about to clear, iclass 23 cls_cnt 0 2006.203.08:21:53.35#ibcon#cleared, iclass 23 cls_cnt 0 2006.203.08:21:53.35$vc4f8/vblo=6,752.99 2006.203.08:21:53.35#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.203.08:21:53.35#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.203.08:21:53.35#ibcon#ireg 17 cls_cnt 0 2006.203.08:21:53.35#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.203.08:21:53.35#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.203.08:21:53.35#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.203.08:21:53.35#ibcon#enter wrdev, iclass 25, count 0 2006.203.08:21:53.35#ibcon#first serial, iclass 25, count 0 2006.203.08:21:53.35#ibcon#enter sib2, iclass 25, count 0 2006.203.08:21:53.35#ibcon#flushed, iclass 25, count 0 2006.203.08:21:53.35#ibcon#about to write, iclass 25, count 0 2006.203.08:21:53.35#ibcon#wrote, iclass 25, count 0 2006.203.08:21:53.35#ibcon#about to read 3, iclass 25, count 0 2006.203.08:21:53.38#ibcon#read 3, iclass 25, count 0 2006.203.08:21:53.38#ibcon#about to read 4, iclass 25, count 0 2006.203.08:21:53.38#ibcon#read 4, iclass 25, count 0 2006.203.08:21:53.38#ibcon#about to read 5, iclass 25, count 0 2006.203.08:21:53.38#ibcon#read 5, iclass 25, count 0 2006.203.08:21:53.38#ibcon#about to read 6, iclass 25, count 0 2006.203.08:21:53.38#ibcon#read 6, iclass 25, count 0 2006.203.08:21:53.38#ibcon#end of sib2, iclass 25, count 0 2006.203.08:21:53.38#ibcon#*mode == 0, iclass 25, count 0 2006.203.08:21:53.38#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.203.08:21:53.38#ibcon#[28=FRQ=06,752.99\r\n] 2006.203.08:21:53.38#ibcon#*before write, iclass 25, count 0 2006.203.08:21:53.38#ibcon#enter sib2, iclass 25, count 0 2006.203.08:21:53.38#ibcon#flushed, iclass 25, count 0 2006.203.08:21:53.38#ibcon#about to write, iclass 25, count 0 2006.203.08:21:53.38#ibcon#wrote, iclass 25, count 0 2006.203.08:21:53.38#ibcon#about to read 3, iclass 25, count 0 2006.203.08:21:53.42#ibcon#read 3, iclass 25, count 0 2006.203.08:21:53.42#ibcon#about to read 4, iclass 25, count 0 2006.203.08:21:53.42#ibcon#read 4, iclass 25, count 0 2006.203.08:21:53.42#ibcon#about to read 5, iclass 25, count 0 2006.203.08:21:53.42#ibcon#read 5, iclass 25, count 0 2006.203.08:21:53.42#ibcon#about to read 6, iclass 25, count 0 2006.203.08:21:53.42#ibcon#read 6, iclass 25, count 0 2006.203.08:21:53.42#ibcon#end of sib2, iclass 25, count 0 2006.203.08:21:53.42#ibcon#*after write, iclass 25, count 0 2006.203.08:21:53.42#ibcon#*before return 0, iclass 25, count 0 2006.203.08:21:53.42#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.203.08:21:53.42#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.203.08:21:53.42#ibcon#about to clear, iclass 25 cls_cnt 0 2006.203.08:21:53.42#ibcon#cleared, iclass 25 cls_cnt 0 2006.203.08:21:53.42$vc4f8/vb=6,4 2006.203.08:21:53.42#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.203.08:21:53.42#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.203.08:21:53.42#ibcon#ireg 11 cls_cnt 2 2006.203.08:21:53.42#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.203.08:21:53.47#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.203.08:21:53.47#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.203.08:21:53.47#ibcon#enter wrdev, iclass 27, count 2 2006.203.08:21:53.47#ibcon#first serial, iclass 27, count 2 2006.203.08:21:53.47#ibcon#enter sib2, iclass 27, count 2 2006.203.08:21:53.47#ibcon#flushed, iclass 27, count 2 2006.203.08:21:53.47#ibcon#about to write, iclass 27, count 2 2006.203.08:21:53.47#ibcon#wrote, iclass 27, count 2 2006.203.08:21:53.47#ibcon#about to read 3, iclass 27, count 2 2006.203.08:21:53.49#ibcon#read 3, iclass 27, count 2 2006.203.08:21:53.49#ibcon#about to read 4, iclass 27, count 2 2006.203.08:21:53.49#ibcon#read 4, iclass 27, count 2 2006.203.08:21:53.49#ibcon#about to read 5, iclass 27, count 2 2006.203.08:21:53.49#ibcon#read 5, iclass 27, count 2 2006.203.08:21:53.49#ibcon#about to read 6, iclass 27, count 2 2006.203.08:21:53.49#ibcon#read 6, iclass 27, count 2 2006.203.08:21:53.49#ibcon#end of sib2, iclass 27, count 2 2006.203.08:21:53.49#ibcon#*mode == 0, iclass 27, count 2 2006.203.08:21:53.49#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.203.08:21:53.49#ibcon#[27=AT06-04\r\n] 2006.203.08:21:53.49#ibcon#*before write, iclass 27, count 2 2006.203.08:21:53.49#ibcon#enter sib2, iclass 27, count 2 2006.203.08:21:53.49#ibcon#flushed, iclass 27, count 2 2006.203.08:21:53.49#ibcon#about to write, iclass 27, count 2 2006.203.08:21:53.49#ibcon#wrote, iclass 27, count 2 2006.203.08:21:53.49#ibcon#about to read 3, iclass 27, count 2 2006.203.08:21:53.52#ibcon#read 3, iclass 27, count 2 2006.203.08:21:53.52#ibcon#about to read 4, iclass 27, count 2 2006.203.08:21:53.52#ibcon#read 4, iclass 27, count 2 2006.203.08:21:53.52#ibcon#about to read 5, iclass 27, count 2 2006.203.08:21:53.52#ibcon#read 5, iclass 27, count 2 2006.203.08:21:53.52#ibcon#about to read 6, iclass 27, count 2 2006.203.08:21:53.52#ibcon#read 6, iclass 27, count 2 2006.203.08:21:53.52#ibcon#end of sib2, iclass 27, count 2 2006.203.08:21:53.52#ibcon#*after write, iclass 27, count 2 2006.203.08:21:53.52#ibcon#*before return 0, iclass 27, count 2 2006.203.08:21:53.52#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.203.08:21:53.52#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.203.08:21:53.52#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.203.08:21:53.52#ibcon#ireg 7 cls_cnt 0 2006.203.08:21:53.52#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.203.08:21:53.64#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.203.08:21:53.64#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.203.08:21:53.64#ibcon#enter wrdev, iclass 27, count 0 2006.203.08:21:53.64#ibcon#first serial, iclass 27, count 0 2006.203.08:21:53.64#ibcon#enter sib2, iclass 27, count 0 2006.203.08:21:53.64#ibcon#flushed, iclass 27, count 0 2006.203.08:21:53.64#ibcon#about to write, iclass 27, count 0 2006.203.08:21:53.64#ibcon#wrote, iclass 27, count 0 2006.203.08:21:53.64#ibcon#about to read 3, iclass 27, count 0 2006.203.08:21:53.66#ibcon#read 3, iclass 27, count 0 2006.203.08:21:53.66#ibcon#about to read 4, iclass 27, count 0 2006.203.08:21:53.66#ibcon#read 4, iclass 27, count 0 2006.203.08:21:53.66#ibcon#about to read 5, iclass 27, count 0 2006.203.08:21:53.66#ibcon#read 5, iclass 27, count 0 2006.203.08:21:53.66#ibcon#about to read 6, iclass 27, count 0 2006.203.08:21:53.66#ibcon#read 6, iclass 27, count 0 2006.203.08:21:53.66#ibcon#end of sib2, iclass 27, count 0 2006.203.08:21:53.66#ibcon#*mode == 0, iclass 27, count 0 2006.203.08:21:53.66#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.203.08:21:53.66#ibcon#[27=USB\r\n] 2006.203.08:21:53.66#ibcon#*before write, iclass 27, count 0 2006.203.08:21:53.66#ibcon#enter sib2, iclass 27, count 0 2006.203.08:21:53.66#ibcon#flushed, iclass 27, count 0 2006.203.08:21:53.66#ibcon#about to write, iclass 27, count 0 2006.203.08:21:53.66#ibcon#wrote, iclass 27, count 0 2006.203.08:21:53.66#ibcon#about to read 3, iclass 27, count 0 2006.203.08:21:53.69#ibcon#read 3, iclass 27, count 0 2006.203.08:21:53.69#ibcon#about to read 4, iclass 27, count 0 2006.203.08:21:53.69#ibcon#read 4, iclass 27, count 0 2006.203.08:21:53.69#ibcon#about to read 5, iclass 27, count 0 2006.203.08:21:53.69#ibcon#read 5, iclass 27, count 0 2006.203.08:21:53.69#ibcon#about to read 6, iclass 27, count 0 2006.203.08:21:53.69#ibcon#read 6, iclass 27, count 0 2006.203.08:21:53.69#ibcon#end of sib2, iclass 27, count 0 2006.203.08:21:53.69#ibcon#*after write, iclass 27, count 0 2006.203.08:21:53.69#ibcon#*before return 0, iclass 27, count 0 2006.203.08:21:53.69#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.203.08:21:53.69#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.203.08:21:53.69#ibcon#about to clear, iclass 27 cls_cnt 0 2006.203.08:21:53.69#ibcon#cleared, iclass 27 cls_cnt 0 2006.203.08:21:53.69$vc4f8/vabw=wide 2006.203.08:21:53.69#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.203.08:21:53.69#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.203.08:21:53.69#ibcon#ireg 8 cls_cnt 0 2006.203.08:21:53.69#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.203.08:21:53.69#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.203.08:21:53.69#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.203.08:21:53.69#ibcon#enter wrdev, iclass 29, count 0 2006.203.08:21:53.69#ibcon#first serial, iclass 29, count 0 2006.203.08:21:53.69#ibcon#enter sib2, iclass 29, count 0 2006.203.08:21:53.69#ibcon#flushed, iclass 29, count 0 2006.203.08:21:53.69#ibcon#about to write, iclass 29, count 0 2006.203.08:21:53.69#ibcon#wrote, iclass 29, count 0 2006.203.08:21:53.69#ibcon#about to read 3, iclass 29, count 0 2006.203.08:21:53.71#ibcon#read 3, iclass 29, count 0 2006.203.08:21:53.71#ibcon#about to read 4, iclass 29, count 0 2006.203.08:21:53.71#ibcon#read 4, iclass 29, count 0 2006.203.08:21:53.71#ibcon#about to read 5, iclass 29, count 0 2006.203.08:21:53.71#ibcon#read 5, iclass 29, count 0 2006.203.08:21:53.71#ibcon#about to read 6, iclass 29, count 0 2006.203.08:21:53.71#ibcon#read 6, iclass 29, count 0 2006.203.08:21:53.71#ibcon#end of sib2, iclass 29, count 0 2006.203.08:21:53.71#ibcon#*mode == 0, iclass 29, count 0 2006.203.08:21:53.71#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.203.08:21:53.71#ibcon#[25=BW32\r\n] 2006.203.08:21:53.71#ibcon#*before write, iclass 29, count 0 2006.203.08:21:53.71#ibcon#enter sib2, iclass 29, count 0 2006.203.08:21:53.71#ibcon#flushed, iclass 29, count 0 2006.203.08:21:53.71#ibcon#about to write, iclass 29, count 0 2006.203.08:21:53.71#ibcon#wrote, iclass 29, count 0 2006.203.08:21:53.71#ibcon#about to read 3, iclass 29, count 0 2006.203.08:21:53.74#ibcon#read 3, iclass 29, count 0 2006.203.08:21:53.74#ibcon#about to read 4, iclass 29, count 0 2006.203.08:21:53.74#ibcon#read 4, iclass 29, count 0 2006.203.08:21:53.74#ibcon#about to read 5, iclass 29, count 0 2006.203.08:21:53.74#ibcon#read 5, iclass 29, count 0 2006.203.08:21:53.74#ibcon#about to read 6, iclass 29, count 0 2006.203.08:21:53.74#ibcon#read 6, iclass 29, count 0 2006.203.08:21:53.74#ibcon#end of sib2, iclass 29, count 0 2006.203.08:21:53.74#ibcon#*after write, iclass 29, count 0 2006.203.08:21:53.74#ibcon#*before return 0, iclass 29, count 0 2006.203.08:21:53.74#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.203.08:21:53.74#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.203.08:21:53.74#ibcon#about to clear, iclass 29 cls_cnt 0 2006.203.08:21:53.74#ibcon#cleared, iclass 29 cls_cnt 0 2006.203.08:21:53.74$vc4f8/vbbw=wide 2006.203.08:21:53.74#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.203.08:21:53.74#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.203.08:21:53.74#ibcon#ireg 8 cls_cnt 0 2006.203.08:21:53.74#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.203.08:21:53.81#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.203.08:21:53.81#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.203.08:21:53.81#ibcon#enter wrdev, iclass 31, count 0 2006.203.08:21:53.81#ibcon#first serial, iclass 31, count 0 2006.203.08:21:53.81#ibcon#enter sib2, iclass 31, count 0 2006.203.08:21:53.81#ibcon#flushed, iclass 31, count 0 2006.203.08:21:53.81#ibcon#about to write, iclass 31, count 0 2006.203.08:21:53.81#ibcon#wrote, iclass 31, count 0 2006.203.08:21:53.81#ibcon#about to read 3, iclass 31, count 0 2006.203.08:21:53.83#ibcon#read 3, iclass 31, count 0 2006.203.08:21:53.83#ibcon#about to read 4, iclass 31, count 0 2006.203.08:21:53.83#ibcon#read 4, iclass 31, count 0 2006.203.08:21:53.83#ibcon#about to read 5, iclass 31, count 0 2006.203.08:21:53.83#ibcon#read 5, iclass 31, count 0 2006.203.08:21:53.83#ibcon#about to read 6, iclass 31, count 0 2006.203.08:21:53.83#ibcon#read 6, iclass 31, count 0 2006.203.08:21:53.83#ibcon#end of sib2, iclass 31, count 0 2006.203.08:21:53.83#ibcon#*mode == 0, iclass 31, count 0 2006.203.08:21:53.83#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.203.08:21:53.83#ibcon#[27=BW32\r\n] 2006.203.08:21:53.83#ibcon#*before write, iclass 31, count 0 2006.203.08:21:53.83#ibcon#enter sib2, iclass 31, count 0 2006.203.08:21:53.83#ibcon#flushed, iclass 31, count 0 2006.203.08:21:53.83#ibcon#about to write, iclass 31, count 0 2006.203.08:21:53.83#ibcon#wrote, iclass 31, count 0 2006.203.08:21:53.83#ibcon#about to read 3, iclass 31, count 0 2006.203.08:21:53.86#ibcon#read 3, iclass 31, count 0 2006.203.08:21:53.86#ibcon#about to read 4, iclass 31, count 0 2006.203.08:21:53.86#ibcon#read 4, iclass 31, count 0 2006.203.08:21:53.86#ibcon#about to read 5, iclass 31, count 0 2006.203.08:21:53.86#ibcon#read 5, iclass 31, count 0 2006.203.08:21:53.86#ibcon#about to read 6, iclass 31, count 0 2006.203.08:21:53.86#ibcon#read 6, iclass 31, count 0 2006.203.08:21:53.86#ibcon#end of sib2, iclass 31, count 0 2006.203.08:21:53.86#ibcon#*after write, iclass 31, count 0 2006.203.08:21:53.86#ibcon#*before return 0, iclass 31, count 0 2006.203.08:21:53.86#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.203.08:21:53.86#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.203.08:21:53.86#ibcon#about to clear, iclass 31 cls_cnt 0 2006.203.08:21:53.86#ibcon#cleared, iclass 31 cls_cnt 0 2006.203.08:21:53.86$4f8m12a/ifd4f 2006.203.08:21:53.86$ifd4f/lo= 2006.203.08:21:53.86$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.203.08:21:53.86$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.203.08:21:53.86$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.203.08:21:53.86$ifd4f/patch= 2006.203.08:21:53.86$ifd4f/patch=lo1,a1,a2,a3,a4 2006.203.08:21:53.86$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.203.08:21:53.86$ifd4f/patch=lo3,a5,a6,a7,a8 2006.203.08:21:53.86$4f8m12a/"form=m,16.000,1:2 2006.203.08:21:53.86$4f8m12a/"tpicd 2006.203.08:21:53.86$4f8m12a/echo=off 2006.203.08:21:53.86$4f8m12a/xlog=off 2006.203.08:21:53.87:!2006.203.08:24:00 2006.203.08:22:33.13#trakl#Source acquired 2006.203.08:22:34.13#flagr#flagr/antenna,acquired 2006.203.08:24:00.01:preob 2006.203.08:24:01.14/onsource/TRACKING 2006.203.08:24:01.14:!2006.203.08:24:10 2006.203.08:24:10.00:data_valid=on 2006.203.08:24:10.00:midob 2006.203.08:24:10.14/onsource/TRACKING 2006.203.08:24:10.14/wx/23.55,1001.2,100 2006.203.08:24:10.27/cable/+6.4597E-03 2006.203.08:24:11.36/va/01,08,usb,yes,34,36 2006.203.08:24:11.36/va/02,07,usb,yes,34,36 2006.203.08:24:11.36/va/03,08,usb,yes,25,26 2006.203.08:24:11.36/va/04,07,usb,yes,35,37 2006.203.08:24:11.36/va/05,07,usb,yes,38,40 2006.203.08:24:11.36/va/06,06,usb,yes,37,37 2006.203.08:24:11.36/va/07,07,usb,yes,33,33 2006.203.08:24:11.36/va/08,06,usb,yes,40,39 2006.203.08:24:11.59/valo/01,532.99,yes,locked 2006.203.08:24:11.59/valo/02,572.99,yes,locked 2006.203.08:24:11.59/valo/03,672.99,yes,locked 2006.203.08:24:11.59/valo/04,832.99,yes,locked 2006.203.08:24:11.59/valo/05,652.99,yes,locked 2006.203.08:24:11.59/valo/06,772.99,yes,locked 2006.203.08:24:11.59/valo/07,832.99,yes,locked 2006.203.08:24:11.59/valo/08,852.99,yes,locked 2006.203.08:24:12.68/vb/01,04,usb,yes,30,29 2006.203.08:24:12.68/vb/02,04,usb,yes,32,33 2006.203.08:24:12.68/vb/03,04,usb,yes,28,32 2006.203.08:24:12.68/vb/04,04,usb,yes,29,29 2006.203.08:24:12.68/vb/05,03,usb,yes,34,39 2006.203.08:24:12.68/vb/06,04,usb,yes,28,31 2006.203.08:24:12.68/vb/07,04,usb,yes,30,30 2006.203.08:24:12.68/vb/08,04,usb,yes,28,31 2006.203.08:24:12.91/vblo/01,632.99,yes,locked 2006.203.08:24:12.91/vblo/02,640.99,yes,locked 2006.203.08:24:12.91/vblo/03,656.99,yes,locked 2006.203.08:24:12.91/vblo/04,712.99,yes,locked 2006.203.08:24:12.91/vblo/05,744.99,yes,locked 2006.203.08:24:12.91/vblo/06,752.99,yes,locked 2006.203.08:24:12.91/vblo/07,734.99,yes,locked 2006.203.08:24:12.91/vblo/08,744.99,yes,locked 2006.203.08:24:13.06/vabw/8 2006.203.08:24:13.21/vbbw/8 2006.203.08:24:13.30/xfe/off,on,12.2 2006.203.08:24:13.69/ifatt/23,28,28,28 2006.203.08:24:14.07/fmout-gps/S +4.57E-07 2006.203.08:24:14.15:!2006.203.08:25:10 2006.203.08:25:10.00:data_valid=off 2006.203.08:25:10.01:postob 2006.203.08:25:10.18/cable/+6.4617E-03 2006.203.08:25:10.22/wx/23.54,1001.3,99 2006.203.08:25:11.07/fmout-gps/S +4.58E-07 2006.203.08:25:11.08:scan_name=203-0826,k06203,60 2006.203.08:25:11.08:source=0602+673,060752.67,672055.4,2000.0,ccw 2006.203.08:25:12.14#flagr#flagr/antenna,new-source 2006.203.08:25:12.14:checkk5 2006.203.08:25:12.55/chk_autoobs//k5ts1/ autoobs is running! 2006.203.08:25:12.97/chk_autoobs//k5ts2/ autoobs is running! 2006.203.08:25:13.40/chk_autoobs//k5ts3/ autoobs is running! 2006.203.08:25:13.82/chk_autoobs//k5ts4/ autoobs is running! 2006.203.08:25:14.23/chk_obsdata//k5ts1/T2030824??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.08:25:14.67/chk_obsdata//k5ts2/T2030824??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.08:25:15.06/chk_obsdata//k5ts3/T2030824??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.08:25:15.48/chk_obsdata//k5ts4/T2030824??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.08:25:16.39/k5log//k5ts1_log_newline 2006.203.08:25:17.42/k5log//k5ts2_log_newline 2006.203.08:25:18.18/k5log//k5ts3_log_newline 2006.203.08:25:18.99/k5log//k5ts4_log_newline 2006.203.08:25:19.02/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.203.08:25:19.02:4f8m12a=3 2006.203.08:25:19.02$4f8m12a/echo=on 2006.203.08:25:19.02$4f8m12a/pcalon 2006.203.08:25:19.02$pcalon/"no phase cal control is implemented here 2006.203.08:25:19.02$4f8m12a/"tpicd=stop 2006.203.08:25:19.02$4f8m12a/vc4f8 2006.203.08:25:19.02$vc4f8/valo=1,532.99 2006.203.08:25:19.02#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.203.08:25:19.02#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.203.08:25:19.02#ibcon#ireg 17 cls_cnt 0 2006.203.08:25:19.02#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.203.08:25:19.02#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.203.08:25:19.02#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.203.08:25:19.02#ibcon#enter wrdev, iclass 37, count 0 2006.203.08:25:19.02#ibcon#first serial, iclass 37, count 0 2006.203.08:25:19.02#ibcon#enter sib2, iclass 37, count 0 2006.203.08:25:19.02#ibcon#flushed, iclass 37, count 0 2006.203.08:25:19.02#ibcon#about to write, iclass 37, count 0 2006.203.08:25:19.02#ibcon#wrote, iclass 37, count 0 2006.203.08:25:19.02#ibcon#about to read 3, iclass 37, count 0 2006.203.08:25:19.06#ibcon#read 3, iclass 37, count 0 2006.203.08:25:19.06#ibcon#about to read 4, iclass 37, count 0 2006.203.08:25:19.06#ibcon#read 4, iclass 37, count 0 2006.203.08:25:19.06#ibcon#about to read 5, iclass 37, count 0 2006.203.08:25:19.06#ibcon#read 5, iclass 37, count 0 2006.203.08:25:19.06#ibcon#about to read 6, iclass 37, count 0 2006.203.08:25:19.06#ibcon#read 6, iclass 37, count 0 2006.203.08:25:19.06#ibcon#end of sib2, iclass 37, count 0 2006.203.08:25:19.06#ibcon#*mode == 0, iclass 37, count 0 2006.203.08:25:19.06#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.203.08:25:19.06#ibcon#[26=FRQ=01,532.99\r\n] 2006.203.08:25:19.06#ibcon#*before write, iclass 37, count 0 2006.203.08:25:19.06#ibcon#enter sib2, iclass 37, count 0 2006.203.08:25:19.06#ibcon#flushed, iclass 37, count 0 2006.203.08:25:19.06#ibcon#about to write, iclass 37, count 0 2006.203.08:25:19.06#ibcon#wrote, iclass 37, count 0 2006.203.08:25:19.06#ibcon#about to read 3, iclass 37, count 0 2006.203.08:25:19.11#ibcon#read 3, iclass 37, count 0 2006.203.08:25:19.11#ibcon#about to read 4, iclass 37, count 0 2006.203.08:25:19.11#ibcon#read 4, iclass 37, count 0 2006.203.08:25:19.11#ibcon#about to read 5, iclass 37, count 0 2006.203.08:25:19.11#ibcon#read 5, iclass 37, count 0 2006.203.08:25:19.11#ibcon#about to read 6, iclass 37, count 0 2006.203.08:25:19.11#ibcon#read 6, iclass 37, count 0 2006.203.08:25:19.11#ibcon#end of sib2, iclass 37, count 0 2006.203.08:25:19.11#ibcon#*after write, iclass 37, count 0 2006.203.08:25:19.11#ibcon#*before return 0, iclass 37, count 0 2006.203.08:25:19.11#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.203.08:25:19.11#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.203.08:25:19.11#ibcon#about to clear, iclass 37 cls_cnt 0 2006.203.08:25:19.11#ibcon#cleared, iclass 37 cls_cnt 0 2006.203.08:25:19.11$vc4f8/va=1,8 2006.203.08:25:19.11#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.203.08:25:19.11#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.203.08:25:19.11#ibcon#ireg 11 cls_cnt 2 2006.203.08:25:19.11#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.203.08:25:19.11#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.203.08:25:19.11#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.203.08:25:19.11#ibcon#enter wrdev, iclass 39, count 2 2006.203.08:25:19.11#ibcon#first serial, iclass 39, count 2 2006.203.08:25:19.11#ibcon#enter sib2, iclass 39, count 2 2006.203.08:25:19.11#ibcon#flushed, iclass 39, count 2 2006.203.08:25:19.11#ibcon#about to write, iclass 39, count 2 2006.203.08:25:19.11#ibcon#wrote, iclass 39, count 2 2006.203.08:25:19.11#ibcon#about to read 3, iclass 39, count 2 2006.203.08:25:19.14#ibcon#read 3, iclass 39, count 2 2006.203.08:25:19.14#ibcon#about to read 4, iclass 39, count 2 2006.203.08:25:19.14#ibcon#read 4, iclass 39, count 2 2006.203.08:25:19.14#ibcon#about to read 5, iclass 39, count 2 2006.203.08:25:19.14#ibcon#read 5, iclass 39, count 2 2006.203.08:25:19.14#ibcon#about to read 6, iclass 39, count 2 2006.203.08:25:19.14#ibcon#read 6, iclass 39, count 2 2006.203.08:25:19.14#ibcon#end of sib2, iclass 39, count 2 2006.203.08:25:19.14#ibcon#*mode == 0, iclass 39, count 2 2006.203.08:25:19.14#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.203.08:25:19.14#ibcon#[25=AT01-08\r\n] 2006.203.08:25:19.14#ibcon#*before write, iclass 39, count 2 2006.203.08:25:19.14#ibcon#enter sib2, iclass 39, count 2 2006.203.08:25:19.14#ibcon#flushed, iclass 39, count 2 2006.203.08:25:19.14#ibcon#about to write, iclass 39, count 2 2006.203.08:25:19.14#ibcon#wrote, iclass 39, count 2 2006.203.08:25:19.14#ibcon#about to read 3, iclass 39, count 2 2006.203.08:25:19.17#ibcon#read 3, iclass 39, count 2 2006.203.08:25:19.17#ibcon#about to read 4, iclass 39, count 2 2006.203.08:25:19.17#ibcon#read 4, iclass 39, count 2 2006.203.08:25:19.17#ibcon#about to read 5, iclass 39, count 2 2006.203.08:25:19.17#ibcon#read 5, iclass 39, count 2 2006.203.08:25:19.17#ibcon#about to read 6, iclass 39, count 2 2006.203.08:25:19.17#ibcon#read 6, iclass 39, count 2 2006.203.08:25:19.17#ibcon#end of sib2, iclass 39, count 2 2006.203.08:25:19.17#ibcon#*after write, iclass 39, count 2 2006.203.08:25:19.17#ibcon#*before return 0, iclass 39, count 2 2006.203.08:25:19.17#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.203.08:25:19.17#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.203.08:25:19.17#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.203.08:25:19.17#ibcon#ireg 7 cls_cnt 0 2006.203.08:25:19.17#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.203.08:25:19.29#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.203.08:25:19.29#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.203.08:25:19.29#ibcon#enter wrdev, iclass 39, count 0 2006.203.08:25:19.29#ibcon#first serial, iclass 39, count 0 2006.203.08:25:19.29#ibcon#enter sib2, iclass 39, count 0 2006.203.08:25:19.29#ibcon#flushed, iclass 39, count 0 2006.203.08:25:19.29#ibcon#about to write, iclass 39, count 0 2006.203.08:25:19.29#ibcon#wrote, iclass 39, count 0 2006.203.08:25:19.29#ibcon#about to read 3, iclass 39, count 0 2006.203.08:25:19.31#ibcon#read 3, iclass 39, count 0 2006.203.08:25:19.31#ibcon#about to read 4, iclass 39, count 0 2006.203.08:25:19.31#ibcon#read 4, iclass 39, count 0 2006.203.08:25:19.31#ibcon#about to read 5, iclass 39, count 0 2006.203.08:25:19.31#ibcon#read 5, iclass 39, count 0 2006.203.08:25:19.31#ibcon#about to read 6, iclass 39, count 0 2006.203.08:25:19.31#ibcon#read 6, iclass 39, count 0 2006.203.08:25:19.31#ibcon#end of sib2, iclass 39, count 0 2006.203.08:25:19.31#ibcon#*mode == 0, iclass 39, count 0 2006.203.08:25:19.31#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.203.08:25:19.31#ibcon#[25=USB\r\n] 2006.203.08:25:19.31#ibcon#*before write, iclass 39, count 0 2006.203.08:25:19.31#ibcon#enter sib2, iclass 39, count 0 2006.203.08:25:19.31#ibcon#flushed, iclass 39, count 0 2006.203.08:25:19.31#ibcon#about to write, iclass 39, count 0 2006.203.08:25:19.31#ibcon#wrote, iclass 39, count 0 2006.203.08:25:19.31#ibcon#about to read 3, iclass 39, count 0 2006.203.08:25:19.34#ibcon#read 3, iclass 39, count 0 2006.203.08:25:19.34#ibcon#about to read 4, iclass 39, count 0 2006.203.08:25:19.34#ibcon#read 4, iclass 39, count 0 2006.203.08:25:19.34#ibcon#about to read 5, iclass 39, count 0 2006.203.08:25:19.34#ibcon#read 5, iclass 39, count 0 2006.203.08:25:19.34#ibcon#about to read 6, iclass 39, count 0 2006.203.08:25:19.34#ibcon#read 6, iclass 39, count 0 2006.203.08:25:19.34#ibcon#end of sib2, iclass 39, count 0 2006.203.08:25:19.34#ibcon#*after write, iclass 39, count 0 2006.203.08:25:19.34#ibcon#*before return 0, iclass 39, count 0 2006.203.08:25:19.34#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.203.08:25:19.34#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.203.08:25:19.34#ibcon#about to clear, iclass 39 cls_cnt 0 2006.203.08:25:19.34#ibcon#cleared, iclass 39 cls_cnt 0 2006.203.08:25:19.34$vc4f8/valo=2,572.99 2006.203.08:25:19.34#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.203.08:25:19.34#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.203.08:25:19.34#ibcon#ireg 17 cls_cnt 0 2006.203.08:25:19.34#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.203.08:25:19.34#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.203.08:25:19.34#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.203.08:25:19.34#ibcon#enter wrdev, iclass 3, count 0 2006.203.08:25:19.34#ibcon#first serial, iclass 3, count 0 2006.203.08:25:19.34#ibcon#enter sib2, iclass 3, count 0 2006.203.08:25:19.34#ibcon#flushed, iclass 3, count 0 2006.203.08:25:19.34#ibcon#about to write, iclass 3, count 0 2006.203.08:25:19.34#ibcon#wrote, iclass 3, count 0 2006.203.08:25:19.34#ibcon#about to read 3, iclass 3, count 0 2006.203.08:25:19.37#ibcon#read 3, iclass 3, count 0 2006.203.08:25:19.37#ibcon#about to read 4, iclass 3, count 0 2006.203.08:25:19.37#ibcon#read 4, iclass 3, count 0 2006.203.08:25:19.37#ibcon#about to read 5, iclass 3, count 0 2006.203.08:25:19.37#ibcon#read 5, iclass 3, count 0 2006.203.08:25:19.37#ibcon#about to read 6, iclass 3, count 0 2006.203.08:25:19.37#ibcon#read 6, iclass 3, count 0 2006.203.08:25:19.37#ibcon#end of sib2, iclass 3, count 0 2006.203.08:25:19.37#ibcon#*mode == 0, iclass 3, count 0 2006.203.08:25:19.37#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.203.08:25:19.37#ibcon#[26=FRQ=02,572.99\r\n] 2006.203.08:25:19.37#ibcon#*before write, iclass 3, count 0 2006.203.08:25:19.37#ibcon#enter sib2, iclass 3, count 0 2006.203.08:25:19.37#ibcon#flushed, iclass 3, count 0 2006.203.08:25:19.37#ibcon#about to write, iclass 3, count 0 2006.203.08:25:19.37#ibcon#wrote, iclass 3, count 0 2006.203.08:25:19.37#ibcon#about to read 3, iclass 3, count 0 2006.203.08:25:19.41#ibcon#read 3, iclass 3, count 0 2006.203.08:25:19.41#ibcon#about to read 4, iclass 3, count 0 2006.203.08:25:19.41#ibcon#read 4, iclass 3, count 0 2006.203.08:25:19.41#ibcon#about to read 5, iclass 3, count 0 2006.203.08:25:19.41#ibcon#read 5, iclass 3, count 0 2006.203.08:25:19.41#ibcon#about to read 6, iclass 3, count 0 2006.203.08:25:19.41#ibcon#read 6, iclass 3, count 0 2006.203.08:25:19.41#ibcon#end of sib2, iclass 3, count 0 2006.203.08:25:19.41#ibcon#*after write, iclass 3, count 0 2006.203.08:25:19.41#ibcon#*before return 0, iclass 3, count 0 2006.203.08:25:19.41#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.203.08:25:19.41#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.203.08:25:19.41#ibcon#about to clear, iclass 3 cls_cnt 0 2006.203.08:25:19.41#ibcon#cleared, iclass 3 cls_cnt 0 2006.203.08:25:19.41$vc4f8/va=2,7 2006.203.08:25:19.41#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.203.08:25:19.41#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.203.08:25:19.41#ibcon#ireg 11 cls_cnt 2 2006.203.08:25:19.41#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.203.08:25:19.46#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.203.08:25:19.46#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.203.08:25:19.46#ibcon#enter wrdev, iclass 5, count 2 2006.203.08:25:19.46#ibcon#first serial, iclass 5, count 2 2006.203.08:25:19.46#ibcon#enter sib2, iclass 5, count 2 2006.203.08:25:19.46#ibcon#flushed, iclass 5, count 2 2006.203.08:25:19.46#ibcon#about to write, iclass 5, count 2 2006.203.08:25:19.46#ibcon#wrote, iclass 5, count 2 2006.203.08:25:19.46#ibcon#about to read 3, iclass 5, count 2 2006.203.08:25:19.48#ibcon#read 3, iclass 5, count 2 2006.203.08:25:19.48#ibcon#about to read 4, iclass 5, count 2 2006.203.08:25:19.48#ibcon#read 4, iclass 5, count 2 2006.203.08:25:19.48#ibcon#about to read 5, iclass 5, count 2 2006.203.08:25:19.48#ibcon#read 5, iclass 5, count 2 2006.203.08:25:19.48#ibcon#about to read 6, iclass 5, count 2 2006.203.08:25:19.48#ibcon#read 6, iclass 5, count 2 2006.203.08:25:19.48#ibcon#end of sib2, iclass 5, count 2 2006.203.08:25:19.48#ibcon#*mode == 0, iclass 5, count 2 2006.203.08:25:19.48#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.203.08:25:19.48#ibcon#[25=AT02-07\r\n] 2006.203.08:25:19.48#ibcon#*before write, iclass 5, count 2 2006.203.08:25:19.48#ibcon#enter sib2, iclass 5, count 2 2006.203.08:25:19.48#ibcon#flushed, iclass 5, count 2 2006.203.08:25:19.48#ibcon#about to write, iclass 5, count 2 2006.203.08:25:19.48#ibcon#wrote, iclass 5, count 2 2006.203.08:25:19.48#ibcon#about to read 3, iclass 5, count 2 2006.203.08:25:19.51#ibcon#read 3, iclass 5, count 2 2006.203.08:25:19.51#ibcon#about to read 4, iclass 5, count 2 2006.203.08:25:19.51#ibcon#read 4, iclass 5, count 2 2006.203.08:25:19.51#ibcon#about to read 5, iclass 5, count 2 2006.203.08:25:19.51#ibcon#read 5, iclass 5, count 2 2006.203.08:25:19.51#ibcon#about to read 6, iclass 5, count 2 2006.203.08:25:19.51#ibcon#read 6, iclass 5, count 2 2006.203.08:25:19.51#ibcon#end of sib2, iclass 5, count 2 2006.203.08:25:19.51#ibcon#*after write, iclass 5, count 2 2006.203.08:25:19.51#ibcon#*before return 0, iclass 5, count 2 2006.203.08:25:19.51#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.203.08:25:19.51#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.203.08:25:19.51#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.203.08:25:19.51#ibcon#ireg 7 cls_cnt 0 2006.203.08:25:19.51#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.203.08:25:19.63#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.203.08:25:19.63#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.203.08:25:19.63#ibcon#enter wrdev, iclass 5, count 0 2006.203.08:25:19.63#ibcon#first serial, iclass 5, count 0 2006.203.08:25:19.63#ibcon#enter sib2, iclass 5, count 0 2006.203.08:25:19.63#ibcon#flushed, iclass 5, count 0 2006.203.08:25:19.63#ibcon#about to write, iclass 5, count 0 2006.203.08:25:19.63#ibcon#wrote, iclass 5, count 0 2006.203.08:25:19.63#ibcon#about to read 3, iclass 5, count 0 2006.203.08:25:19.65#ibcon#read 3, iclass 5, count 0 2006.203.08:25:19.65#ibcon#about to read 4, iclass 5, count 0 2006.203.08:25:19.65#ibcon#read 4, iclass 5, count 0 2006.203.08:25:19.65#ibcon#about to read 5, iclass 5, count 0 2006.203.08:25:19.65#ibcon#read 5, iclass 5, count 0 2006.203.08:25:19.65#ibcon#about to read 6, iclass 5, count 0 2006.203.08:25:19.65#ibcon#read 6, iclass 5, count 0 2006.203.08:25:19.65#ibcon#end of sib2, iclass 5, count 0 2006.203.08:25:19.65#ibcon#*mode == 0, iclass 5, count 0 2006.203.08:25:19.65#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.203.08:25:19.65#ibcon#[25=USB\r\n] 2006.203.08:25:19.65#ibcon#*before write, iclass 5, count 0 2006.203.08:25:19.65#ibcon#enter sib2, iclass 5, count 0 2006.203.08:25:19.65#ibcon#flushed, iclass 5, count 0 2006.203.08:25:19.65#ibcon#about to write, iclass 5, count 0 2006.203.08:25:19.65#ibcon#wrote, iclass 5, count 0 2006.203.08:25:19.65#ibcon#about to read 3, iclass 5, count 0 2006.203.08:25:19.68#ibcon#read 3, iclass 5, count 0 2006.203.08:25:19.68#ibcon#about to read 4, iclass 5, count 0 2006.203.08:25:19.68#ibcon#read 4, iclass 5, count 0 2006.203.08:25:19.68#ibcon#about to read 5, iclass 5, count 0 2006.203.08:25:19.68#ibcon#read 5, iclass 5, count 0 2006.203.08:25:19.68#ibcon#about to read 6, iclass 5, count 0 2006.203.08:25:19.68#ibcon#read 6, iclass 5, count 0 2006.203.08:25:19.68#ibcon#end of sib2, iclass 5, count 0 2006.203.08:25:19.68#ibcon#*after write, iclass 5, count 0 2006.203.08:25:19.68#ibcon#*before return 0, iclass 5, count 0 2006.203.08:25:19.68#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.203.08:25:19.68#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.203.08:25:19.68#ibcon#about to clear, iclass 5 cls_cnt 0 2006.203.08:25:19.68#ibcon#cleared, iclass 5 cls_cnt 0 2006.203.08:25:19.68$vc4f8/valo=3,672.99 2006.203.08:25:19.68#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.203.08:25:19.68#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.203.08:25:19.68#ibcon#ireg 17 cls_cnt 0 2006.203.08:25:19.68#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.203.08:25:19.68#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.203.08:25:19.68#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.203.08:25:19.68#ibcon#enter wrdev, iclass 7, count 0 2006.203.08:25:19.68#ibcon#first serial, iclass 7, count 0 2006.203.08:25:19.68#ibcon#enter sib2, iclass 7, count 0 2006.203.08:25:19.68#ibcon#flushed, iclass 7, count 0 2006.203.08:25:19.68#ibcon#about to write, iclass 7, count 0 2006.203.08:25:19.68#ibcon#wrote, iclass 7, count 0 2006.203.08:25:19.68#ibcon#about to read 3, iclass 7, count 0 2006.203.08:25:19.71#ibcon#read 3, iclass 7, count 0 2006.203.08:25:19.71#ibcon#about to read 4, iclass 7, count 0 2006.203.08:25:19.71#ibcon#read 4, iclass 7, count 0 2006.203.08:25:19.71#ibcon#about to read 5, iclass 7, count 0 2006.203.08:25:19.71#ibcon#read 5, iclass 7, count 0 2006.203.08:25:19.71#ibcon#about to read 6, iclass 7, count 0 2006.203.08:25:19.71#ibcon#read 6, iclass 7, count 0 2006.203.08:25:19.71#ibcon#end of sib2, iclass 7, count 0 2006.203.08:25:19.71#ibcon#*mode == 0, iclass 7, count 0 2006.203.08:25:19.71#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.203.08:25:19.71#ibcon#[26=FRQ=03,672.99\r\n] 2006.203.08:25:19.71#ibcon#*before write, iclass 7, count 0 2006.203.08:25:19.71#ibcon#enter sib2, iclass 7, count 0 2006.203.08:25:19.71#ibcon#flushed, iclass 7, count 0 2006.203.08:25:19.71#ibcon#about to write, iclass 7, count 0 2006.203.08:25:19.71#ibcon#wrote, iclass 7, count 0 2006.203.08:25:19.71#ibcon#about to read 3, iclass 7, count 0 2006.203.08:25:19.75#ibcon#read 3, iclass 7, count 0 2006.203.08:25:19.75#ibcon#about to read 4, iclass 7, count 0 2006.203.08:25:19.75#ibcon#read 4, iclass 7, count 0 2006.203.08:25:19.75#ibcon#about to read 5, iclass 7, count 0 2006.203.08:25:19.75#ibcon#read 5, iclass 7, count 0 2006.203.08:25:19.75#ibcon#about to read 6, iclass 7, count 0 2006.203.08:25:19.75#ibcon#read 6, iclass 7, count 0 2006.203.08:25:19.75#ibcon#end of sib2, iclass 7, count 0 2006.203.08:25:19.75#ibcon#*after write, iclass 7, count 0 2006.203.08:25:19.75#ibcon#*before return 0, iclass 7, count 0 2006.203.08:25:19.75#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.203.08:25:19.75#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.203.08:25:19.75#ibcon#about to clear, iclass 7 cls_cnt 0 2006.203.08:25:19.75#ibcon#cleared, iclass 7 cls_cnt 0 2006.203.08:25:19.75$vc4f8/va=3,8 2006.203.08:25:19.75#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.203.08:25:19.75#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.203.08:25:19.75#ibcon#ireg 11 cls_cnt 2 2006.203.08:25:19.75#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.203.08:25:19.80#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.203.08:25:19.80#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.203.08:25:19.80#ibcon#enter wrdev, iclass 11, count 2 2006.203.08:25:19.80#ibcon#first serial, iclass 11, count 2 2006.203.08:25:19.80#ibcon#enter sib2, iclass 11, count 2 2006.203.08:25:19.80#ibcon#flushed, iclass 11, count 2 2006.203.08:25:19.80#ibcon#about to write, iclass 11, count 2 2006.203.08:25:19.80#ibcon#wrote, iclass 11, count 2 2006.203.08:25:19.80#ibcon#about to read 3, iclass 11, count 2 2006.203.08:25:19.82#ibcon#read 3, iclass 11, count 2 2006.203.08:25:19.82#ibcon#about to read 4, iclass 11, count 2 2006.203.08:25:19.82#ibcon#read 4, iclass 11, count 2 2006.203.08:25:19.82#ibcon#about to read 5, iclass 11, count 2 2006.203.08:25:19.82#ibcon#read 5, iclass 11, count 2 2006.203.08:25:19.82#ibcon#about to read 6, iclass 11, count 2 2006.203.08:25:19.82#ibcon#read 6, iclass 11, count 2 2006.203.08:25:19.82#ibcon#end of sib2, iclass 11, count 2 2006.203.08:25:19.82#ibcon#*mode == 0, iclass 11, count 2 2006.203.08:25:19.82#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.203.08:25:19.82#ibcon#[25=AT03-08\r\n] 2006.203.08:25:19.82#ibcon#*before write, iclass 11, count 2 2006.203.08:25:19.82#ibcon#enter sib2, iclass 11, count 2 2006.203.08:25:19.82#ibcon#flushed, iclass 11, count 2 2006.203.08:25:19.82#ibcon#about to write, iclass 11, count 2 2006.203.08:25:19.82#ibcon#wrote, iclass 11, count 2 2006.203.08:25:19.82#ibcon#about to read 3, iclass 11, count 2 2006.203.08:25:19.85#ibcon#read 3, iclass 11, count 2 2006.203.08:25:19.85#ibcon#about to read 4, iclass 11, count 2 2006.203.08:25:19.85#ibcon#read 4, iclass 11, count 2 2006.203.08:25:19.85#ibcon#about to read 5, iclass 11, count 2 2006.203.08:25:19.85#ibcon#read 5, iclass 11, count 2 2006.203.08:25:19.85#ibcon#about to read 6, iclass 11, count 2 2006.203.08:25:19.85#ibcon#read 6, iclass 11, count 2 2006.203.08:25:19.85#ibcon#end of sib2, iclass 11, count 2 2006.203.08:25:19.85#ibcon#*after write, iclass 11, count 2 2006.203.08:25:19.85#ibcon#*before return 0, iclass 11, count 2 2006.203.08:25:19.85#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.203.08:25:19.85#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.203.08:25:19.85#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.203.08:25:19.85#ibcon#ireg 7 cls_cnt 0 2006.203.08:25:19.85#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.203.08:25:19.97#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.203.08:25:19.97#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.203.08:25:19.97#ibcon#enter wrdev, iclass 11, count 0 2006.203.08:25:19.97#ibcon#first serial, iclass 11, count 0 2006.203.08:25:19.97#ibcon#enter sib2, iclass 11, count 0 2006.203.08:25:19.97#ibcon#flushed, iclass 11, count 0 2006.203.08:25:19.97#ibcon#about to write, iclass 11, count 0 2006.203.08:25:19.97#ibcon#wrote, iclass 11, count 0 2006.203.08:25:19.97#ibcon#about to read 3, iclass 11, count 0 2006.203.08:25:19.99#ibcon#read 3, iclass 11, count 0 2006.203.08:25:19.99#ibcon#about to read 4, iclass 11, count 0 2006.203.08:25:19.99#ibcon#read 4, iclass 11, count 0 2006.203.08:25:19.99#ibcon#about to read 5, iclass 11, count 0 2006.203.08:25:19.99#ibcon#read 5, iclass 11, count 0 2006.203.08:25:19.99#ibcon#about to read 6, iclass 11, count 0 2006.203.08:25:19.99#ibcon#read 6, iclass 11, count 0 2006.203.08:25:19.99#ibcon#end of sib2, iclass 11, count 0 2006.203.08:25:19.99#ibcon#*mode == 0, iclass 11, count 0 2006.203.08:25:19.99#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.203.08:25:19.99#ibcon#[25=USB\r\n] 2006.203.08:25:19.99#ibcon#*before write, iclass 11, count 0 2006.203.08:25:19.99#ibcon#enter sib2, iclass 11, count 0 2006.203.08:25:19.99#ibcon#flushed, iclass 11, count 0 2006.203.08:25:19.99#ibcon#about to write, iclass 11, count 0 2006.203.08:25:19.99#ibcon#wrote, iclass 11, count 0 2006.203.08:25:19.99#ibcon#about to read 3, iclass 11, count 0 2006.203.08:25:20.02#ibcon#read 3, iclass 11, count 0 2006.203.08:25:20.02#ibcon#about to read 4, iclass 11, count 0 2006.203.08:25:20.02#ibcon#read 4, iclass 11, count 0 2006.203.08:25:20.02#ibcon#about to read 5, iclass 11, count 0 2006.203.08:25:20.02#ibcon#read 5, iclass 11, count 0 2006.203.08:25:20.02#ibcon#about to read 6, iclass 11, count 0 2006.203.08:25:20.02#ibcon#read 6, iclass 11, count 0 2006.203.08:25:20.02#ibcon#end of sib2, iclass 11, count 0 2006.203.08:25:20.02#ibcon#*after write, iclass 11, count 0 2006.203.08:25:20.02#ibcon#*before return 0, iclass 11, count 0 2006.203.08:25:20.02#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.203.08:25:20.02#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.203.08:25:20.02#ibcon#about to clear, iclass 11 cls_cnt 0 2006.203.08:25:20.02#ibcon#cleared, iclass 11 cls_cnt 0 2006.203.08:25:20.02$vc4f8/valo=4,832.99 2006.203.08:25:20.02#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.203.08:25:20.02#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.203.08:25:20.02#ibcon#ireg 17 cls_cnt 0 2006.203.08:25:20.02#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.203.08:25:20.02#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.203.08:25:20.02#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.203.08:25:20.02#ibcon#enter wrdev, iclass 13, count 0 2006.203.08:25:20.02#ibcon#first serial, iclass 13, count 0 2006.203.08:25:20.02#ibcon#enter sib2, iclass 13, count 0 2006.203.08:25:20.02#ibcon#flushed, iclass 13, count 0 2006.203.08:25:20.02#ibcon#about to write, iclass 13, count 0 2006.203.08:25:20.02#ibcon#wrote, iclass 13, count 0 2006.203.08:25:20.02#ibcon#about to read 3, iclass 13, count 0 2006.203.08:25:20.04#ibcon#read 3, iclass 13, count 0 2006.203.08:25:20.04#ibcon#about to read 4, iclass 13, count 0 2006.203.08:25:20.04#ibcon#read 4, iclass 13, count 0 2006.203.08:25:20.04#ibcon#about to read 5, iclass 13, count 0 2006.203.08:25:20.04#ibcon#read 5, iclass 13, count 0 2006.203.08:25:20.04#ibcon#about to read 6, iclass 13, count 0 2006.203.08:25:20.04#ibcon#read 6, iclass 13, count 0 2006.203.08:25:20.04#ibcon#end of sib2, iclass 13, count 0 2006.203.08:25:20.04#ibcon#*mode == 0, iclass 13, count 0 2006.203.08:25:20.04#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.203.08:25:20.04#ibcon#[26=FRQ=04,832.99\r\n] 2006.203.08:25:20.04#ibcon#*before write, iclass 13, count 0 2006.203.08:25:20.04#ibcon#enter sib2, iclass 13, count 0 2006.203.08:25:20.04#ibcon#flushed, iclass 13, count 0 2006.203.08:25:20.04#ibcon#about to write, iclass 13, count 0 2006.203.08:25:20.04#ibcon#wrote, iclass 13, count 0 2006.203.08:25:20.04#ibcon#about to read 3, iclass 13, count 0 2006.203.08:25:20.08#ibcon#read 3, iclass 13, count 0 2006.203.08:25:20.08#ibcon#about to read 4, iclass 13, count 0 2006.203.08:25:20.08#ibcon#read 4, iclass 13, count 0 2006.203.08:25:20.08#ibcon#about to read 5, iclass 13, count 0 2006.203.08:25:20.08#ibcon#read 5, iclass 13, count 0 2006.203.08:25:20.08#ibcon#about to read 6, iclass 13, count 0 2006.203.08:25:20.08#ibcon#read 6, iclass 13, count 0 2006.203.08:25:20.08#ibcon#end of sib2, iclass 13, count 0 2006.203.08:25:20.08#ibcon#*after write, iclass 13, count 0 2006.203.08:25:20.08#ibcon#*before return 0, iclass 13, count 0 2006.203.08:25:20.08#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.203.08:25:20.08#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.203.08:25:20.08#ibcon#about to clear, iclass 13 cls_cnt 0 2006.203.08:25:20.08#ibcon#cleared, iclass 13 cls_cnt 0 2006.203.08:25:20.08$vc4f8/va=4,7 2006.203.08:25:20.08#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.203.08:25:20.08#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.203.08:25:20.08#ibcon#ireg 11 cls_cnt 2 2006.203.08:25:20.08#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.203.08:25:20.14#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.203.08:25:20.14#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.203.08:25:20.14#ibcon#enter wrdev, iclass 15, count 2 2006.203.08:25:20.14#ibcon#first serial, iclass 15, count 2 2006.203.08:25:20.14#ibcon#enter sib2, iclass 15, count 2 2006.203.08:25:20.14#ibcon#flushed, iclass 15, count 2 2006.203.08:25:20.14#ibcon#about to write, iclass 15, count 2 2006.203.08:25:20.14#ibcon#wrote, iclass 15, count 2 2006.203.08:25:20.14#ibcon#about to read 3, iclass 15, count 2 2006.203.08:25:20.16#ibcon#read 3, iclass 15, count 2 2006.203.08:25:20.16#ibcon#about to read 4, iclass 15, count 2 2006.203.08:25:20.16#ibcon#read 4, iclass 15, count 2 2006.203.08:25:20.16#ibcon#about to read 5, iclass 15, count 2 2006.203.08:25:20.16#ibcon#read 5, iclass 15, count 2 2006.203.08:25:20.16#ibcon#about to read 6, iclass 15, count 2 2006.203.08:25:20.16#ibcon#read 6, iclass 15, count 2 2006.203.08:25:20.16#ibcon#end of sib2, iclass 15, count 2 2006.203.08:25:20.16#ibcon#*mode == 0, iclass 15, count 2 2006.203.08:25:20.16#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.203.08:25:20.16#ibcon#[25=AT04-07\r\n] 2006.203.08:25:20.16#ibcon#*before write, iclass 15, count 2 2006.203.08:25:20.16#ibcon#enter sib2, iclass 15, count 2 2006.203.08:25:20.16#ibcon#flushed, iclass 15, count 2 2006.203.08:25:20.16#ibcon#about to write, iclass 15, count 2 2006.203.08:25:20.16#ibcon#wrote, iclass 15, count 2 2006.203.08:25:20.16#ibcon#about to read 3, iclass 15, count 2 2006.203.08:25:20.19#ibcon#read 3, iclass 15, count 2 2006.203.08:25:20.19#ibcon#about to read 4, iclass 15, count 2 2006.203.08:25:20.19#ibcon#read 4, iclass 15, count 2 2006.203.08:25:20.19#ibcon#about to read 5, iclass 15, count 2 2006.203.08:25:20.19#ibcon#read 5, iclass 15, count 2 2006.203.08:25:20.19#ibcon#about to read 6, iclass 15, count 2 2006.203.08:25:20.19#ibcon#read 6, iclass 15, count 2 2006.203.08:25:20.19#ibcon#end of sib2, iclass 15, count 2 2006.203.08:25:20.19#ibcon#*after write, iclass 15, count 2 2006.203.08:25:20.19#ibcon#*before return 0, iclass 15, count 2 2006.203.08:25:20.19#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.203.08:25:20.19#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.203.08:25:20.19#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.203.08:25:20.19#ibcon#ireg 7 cls_cnt 0 2006.203.08:25:20.19#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.203.08:25:20.31#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.203.08:25:20.31#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.203.08:25:20.31#ibcon#enter wrdev, iclass 15, count 0 2006.203.08:25:20.31#ibcon#first serial, iclass 15, count 0 2006.203.08:25:20.31#ibcon#enter sib2, iclass 15, count 0 2006.203.08:25:20.31#ibcon#flushed, iclass 15, count 0 2006.203.08:25:20.31#ibcon#about to write, iclass 15, count 0 2006.203.08:25:20.31#ibcon#wrote, iclass 15, count 0 2006.203.08:25:20.31#ibcon#about to read 3, iclass 15, count 0 2006.203.08:25:20.33#ibcon#read 3, iclass 15, count 0 2006.203.08:25:20.33#ibcon#about to read 4, iclass 15, count 0 2006.203.08:25:20.33#ibcon#read 4, iclass 15, count 0 2006.203.08:25:20.33#ibcon#about to read 5, iclass 15, count 0 2006.203.08:25:20.33#ibcon#read 5, iclass 15, count 0 2006.203.08:25:20.33#ibcon#about to read 6, iclass 15, count 0 2006.203.08:25:20.33#ibcon#read 6, iclass 15, count 0 2006.203.08:25:20.33#ibcon#end of sib2, iclass 15, count 0 2006.203.08:25:20.33#ibcon#*mode == 0, iclass 15, count 0 2006.203.08:25:20.33#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.203.08:25:20.33#ibcon#[25=USB\r\n] 2006.203.08:25:20.33#ibcon#*before write, iclass 15, count 0 2006.203.08:25:20.33#ibcon#enter sib2, iclass 15, count 0 2006.203.08:25:20.33#ibcon#flushed, iclass 15, count 0 2006.203.08:25:20.33#ibcon#about to write, iclass 15, count 0 2006.203.08:25:20.33#ibcon#wrote, iclass 15, count 0 2006.203.08:25:20.33#ibcon#about to read 3, iclass 15, count 0 2006.203.08:25:20.36#ibcon#read 3, iclass 15, count 0 2006.203.08:25:20.36#ibcon#about to read 4, iclass 15, count 0 2006.203.08:25:20.36#ibcon#read 4, iclass 15, count 0 2006.203.08:25:20.36#ibcon#about to read 5, iclass 15, count 0 2006.203.08:25:20.36#ibcon#read 5, iclass 15, count 0 2006.203.08:25:20.36#ibcon#about to read 6, iclass 15, count 0 2006.203.08:25:20.36#ibcon#read 6, iclass 15, count 0 2006.203.08:25:20.36#ibcon#end of sib2, iclass 15, count 0 2006.203.08:25:20.36#ibcon#*after write, iclass 15, count 0 2006.203.08:25:20.36#ibcon#*before return 0, iclass 15, count 0 2006.203.08:25:20.36#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.203.08:25:20.36#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.203.08:25:20.36#ibcon#about to clear, iclass 15 cls_cnt 0 2006.203.08:25:20.36#ibcon#cleared, iclass 15 cls_cnt 0 2006.203.08:25:20.36$vc4f8/valo=5,652.99 2006.203.08:25:20.36#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.203.08:25:20.36#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.203.08:25:20.36#ibcon#ireg 17 cls_cnt 0 2006.203.08:25:20.36#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.203.08:25:20.36#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.203.08:25:20.36#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.203.08:25:20.36#ibcon#enter wrdev, iclass 17, count 0 2006.203.08:25:20.36#ibcon#first serial, iclass 17, count 0 2006.203.08:25:20.36#ibcon#enter sib2, iclass 17, count 0 2006.203.08:25:20.36#ibcon#flushed, iclass 17, count 0 2006.203.08:25:20.36#ibcon#about to write, iclass 17, count 0 2006.203.08:25:20.36#ibcon#wrote, iclass 17, count 0 2006.203.08:25:20.36#ibcon#about to read 3, iclass 17, count 0 2006.203.08:25:20.38#ibcon#read 3, iclass 17, count 0 2006.203.08:25:20.38#ibcon#about to read 4, iclass 17, count 0 2006.203.08:25:20.38#ibcon#read 4, iclass 17, count 0 2006.203.08:25:20.38#ibcon#about to read 5, iclass 17, count 0 2006.203.08:25:20.38#ibcon#read 5, iclass 17, count 0 2006.203.08:25:20.38#ibcon#about to read 6, iclass 17, count 0 2006.203.08:25:20.38#ibcon#read 6, iclass 17, count 0 2006.203.08:25:20.38#ibcon#end of sib2, iclass 17, count 0 2006.203.08:25:20.38#ibcon#*mode == 0, iclass 17, count 0 2006.203.08:25:20.38#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.203.08:25:20.38#ibcon#[26=FRQ=05,652.99\r\n] 2006.203.08:25:20.38#ibcon#*before write, iclass 17, count 0 2006.203.08:25:20.38#ibcon#enter sib2, iclass 17, count 0 2006.203.08:25:20.38#ibcon#flushed, iclass 17, count 0 2006.203.08:25:20.38#ibcon#about to write, iclass 17, count 0 2006.203.08:25:20.38#ibcon#wrote, iclass 17, count 0 2006.203.08:25:20.38#ibcon#about to read 3, iclass 17, count 0 2006.203.08:25:20.42#ibcon#read 3, iclass 17, count 0 2006.203.08:25:20.42#ibcon#about to read 4, iclass 17, count 0 2006.203.08:25:20.42#ibcon#read 4, iclass 17, count 0 2006.203.08:25:20.42#ibcon#about to read 5, iclass 17, count 0 2006.203.08:25:20.42#ibcon#read 5, iclass 17, count 0 2006.203.08:25:20.42#ibcon#about to read 6, iclass 17, count 0 2006.203.08:25:20.42#ibcon#read 6, iclass 17, count 0 2006.203.08:25:20.42#ibcon#end of sib2, iclass 17, count 0 2006.203.08:25:20.42#ibcon#*after write, iclass 17, count 0 2006.203.08:25:20.42#ibcon#*before return 0, iclass 17, count 0 2006.203.08:25:20.42#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.203.08:25:20.42#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.203.08:25:20.42#ibcon#about to clear, iclass 17 cls_cnt 0 2006.203.08:25:20.42#ibcon#cleared, iclass 17 cls_cnt 0 2006.203.08:25:20.42$vc4f8/va=5,7 2006.203.08:25:20.42#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.203.08:25:20.42#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.203.08:25:20.42#ibcon#ireg 11 cls_cnt 2 2006.203.08:25:20.42#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.203.08:25:20.48#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.203.08:25:20.48#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.203.08:25:20.48#ibcon#enter wrdev, iclass 19, count 2 2006.203.08:25:20.48#ibcon#first serial, iclass 19, count 2 2006.203.08:25:20.48#ibcon#enter sib2, iclass 19, count 2 2006.203.08:25:20.48#ibcon#flushed, iclass 19, count 2 2006.203.08:25:20.48#ibcon#about to write, iclass 19, count 2 2006.203.08:25:20.48#ibcon#wrote, iclass 19, count 2 2006.203.08:25:20.48#ibcon#about to read 3, iclass 19, count 2 2006.203.08:25:20.50#ibcon#read 3, iclass 19, count 2 2006.203.08:25:20.50#ibcon#about to read 4, iclass 19, count 2 2006.203.08:25:20.50#ibcon#read 4, iclass 19, count 2 2006.203.08:25:20.50#ibcon#about to read 5, iclass 19, count 2 2006.203.08:25:20.50#ibcon#read 5, iclass 19, count 2 2006.203.08:25:20.50#ibcon#about to read 6, iclass 19, count 2 2006.203.08:25:20.50#ibcon#read 6, iclass 19, count 2 2006.203.08:25:20.50#ibcon#end of sib2, iclass 19, count 2 2006.203.08:25:20.50#ibcon#*mode == 0, iclass 19, count 2 2006.203.08:25:20.50#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.203.08:25:20.50#ibcon#[25=AT05-07\r\n] 2006.203.08:25:20.50#ibcon#*before write, iclass 19, count 2 2006.203.08:25:20.50#ibcon#enter sib2, iclass 19, count 2 2006.203.08:25:20.50#ibcon#flushed, iclass 19, count 2 2006.203.08:25:20.50#ibcon#about to write, iclass 19, count 2 2006.203.08:25:20.50#ibcon#wrote, iclass 19, count 2 2006.203.08:25:20.50#ibcon#about to read 3, iclass 19, count 2 2006.203.08:25:20.53#ibcon#read 3, iclass 19, count 2 2006.203.08:25:20.53#ibcon#about to read 4, iclass 19, count 2 2006.203.08:25:20.53#ibcon#read 4, iclass 19, count 2 2006.203.08:25:20.53#ibcon#about to read 5, iclass 19, count 2 2006.203.08:25:20.53#ibcon#read 5, iclass 19, count 2 2006.203.08:25:20.53#ibcon#about to read 6, iclass 19, count 2 2006.203.08:25:20.53#ibcon#read 6, iclass 19, count 2 2006.203.08:25:20.53#ibcon#end of sib2, iclass 19, count 2 2006.203.08:25:20.53#ibcon#*after write, iclass 19, count 2 2006.203.08:25:20.53#ibcon#*before return 0, iclass 19, count 2 2006.203.08:25:20.53#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.203.08:25:20.53#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.203.08:25:20.53#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.203.08:25:20.53#ibcon#ireg 7 cls_cnt 0 2006.203.08:25:20.53#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.203.08:25:20.65#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.203.08:25:20.65#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.203.08:25:20.65#ibcon#enter wrdev, iclass 19, count 0 2006.203.08:25:20.65#ibcon#first serial, iclass 19, count 0 2006.203.08:25:20.65#ibcon#enter sib2, iclass 19, count 0 2006.203.08:25:20.65#ibcon#flushed, iclass 19, count 0 2006.203.08:25:20.65#ibcon#about to write, iclass 19, count 0 2006.203.08:25:20.65#ibcon#wrote, iclass 19, count 0 2006.203.08:25:20.65#ibcon#about to read 3, iclass 19, count 0 2006.203.08:25:20.67#ibcon#read 3, iclass 19, count 0 2006.203.08:25:20.67#ibcon#about to read 4, iclass 19, count 0 2006.203.08:25:20.67#ibcon#read 4, iclass 19, count 0 2006.203.08:25:20.67#ibcon#about to read 5, iclass 19, count 0 2006.203.08:25:20.67#ibcon#read 5, iclass 19, count 0 2006.203.08:25:20.67#ibcon#about to read 6, iclass 19, count 0 2006.203.08:25:20.67#ibcon#read 6, iclass 19, count 0 2006.203.08:25:20.67#ibcon#end of sib2, iclass 19, count 0 2006.203.08:25:20.67#ibcon#*mode == 0, iclass 19, count 0 2006.203.08:25:20.67#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.203.08:25:20.67#ibcon#[25=USB\r\n] 2006.203.08:25:20.67#ibcon#*before write, iclass 19, count 0 2006.203.08:25:20.67#ibcon#enter sib2, iclass 19, count 0 2006.203.08:25:20.67#ibcon#flushed, iclass 19, count 0 2006.203.08:25:20.67#ibcon#about to write, iclass 19, count 0 2006.203.08:25:20.67#ibcon#wrote, iclass 19, count 0 2006.203.08:25:20.67#ibcon#about to read 3, iclass 19, count 0 2006.203.08:25:20.70#ibcon#read 3, iclass 19, count 0 2006.203.08:25:20.70#ibcon#about to read 4, iclass 19, count 0 2006.203.08:25:20.70#ibcon#read 4, iclass 19, count 0 2006.203.08:25:20.70#ibcon#about to read 5, iclass 19, count 0 2006.203.08:25:20.70#ibcon#read 5, iclass 19, count 0 2006.203.08:25:20.70#ibcon#about to read 6, iclass 19, count 0 2006.203.08:25:20.70#ibcon#read 6, iclass 19, count 0 2006.203.08:25:20.70#ibcon#end of sib2, iclass 19, count 0 2006.203.08:25:20.70#ibcon#*after write, iclass 19, count 0 2006.203.08:25:20.70#ibcon#*before return 0, iclass 19, count 0 2006.203.08:25:20.70#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.203.08:25:20.70#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.203.08:25:20.70#ibcon#about to clear, iclass 19 cls_cnt 0 2006.203.08:25:20.70#ibcon#cleared, iclass 19 cls_cnt 0 2006.203.08:25:20.70$vc4f8/valo=6,772.99 2006.203.08:25:20.70#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.203.08:25:20.70#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.203.08:25:20.70#ibcon#ireg 17 cls_cnt 0 2006.203.08:25:20.70#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.203.08:25:20.70#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.203.08:25:20.70#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.203.08:25:20.70#ibcon#enter wrdev, iclass 21, count 0 2006.203.08:25:20.70#ibcon#first serial, iclass 21, count 0 2006.203.08:25:20.70#ibcon#enter sib2, iclass 21, count 0 2006.203.08:25:20.70#ibcon#flushed, iclass 21, count 0 2006.203.08:25:20.70#ibcon#about to write, iclass 21, count 0 2006.203.08:25:20.70#ibcon#wrote, iclass 21, count 0 2006.203.08:25:20.70#ibcon#about to read 3, iclass 21, count 0 2006.203.08:25:20.73#ibcon#read 3, iclass 21, count 0 2006.203.08:25:20.73#ibcon#about to read 4, iclass 21, count 0 2006.203.08:25:20.73#ibcon#read 4, iclass 21, count 0 2006.203.08:25:20.73#ibcon#about to read 5, iclass 21, count 0 2006.203.08:25:20.73#ibcon#read 5, iclass 21, count 0 2006.203.08:25:20.73#ibcon#about to read 6, iclass 21, count 0 2006.203.08:25:20.73#ibcon#read 6, iclass 21, count 0 2006.203.08:25:20.73#ibcon#end of sib2, iclass 21, count 0 2006.203.08:25:20.73#ibcon#*mode == 0, iclass 21, count 0 2006.203.08:25:20.73#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.203.08:25:20.73#ibcon#[26=FRQ=06,772.99\r\n] 2006.203.08:25:20.73#ibcon#*before write, iclass 21, count 0 2006.203.08:25:20.73#ibcon#enter sib2, iclass 21, count 0 2006.203.08:25:20.73#ibcon#flushed, iclass 21, count 0 2006.203.08:25:20.73#ibcon#about to write, iclass 21, count 0 2006.203.08:25:20.73#ibcon#wrote, iclass 21, count 0 2006.203.08:25:20.73#ibcon#about to read 3, iclass 21, count 0 2006.203.08:25:20.77#ibcon#read 3, iclass 21, count 0 2006.203.08:25:20.77#ibcon#about to read 4, iclass 21, count 0 2006.203.08:25:20.77#ibcon#read 4, iclass 21, count 0 2006.203.08:25:20.77#ibcon#about to read 5, iclass 21, count 0 2006.203.08:25:20.77#ibcon#read 5, iclass 21, count 0 2006.203.08:25:20.77#ibcon#about to read 6, iclass 21, count 0 2006.203.08:25:20.77#ibcon#read 6, iclass 21, count 0 2006.203.08:25:20.77#ibcon#end of sib2, iclass 21, count 0 2006.203.08:25:20.77#ibcon#*after write, iclass 21, count 0 2006.203.08:25:20.77#ibcon#*before return 0, iclass 21, count 0 2006.203.08:25:20.77#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.203.08:25:20.77#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.203.08:25:20.77#ibcon#about to clear, iclass 21 cls_cnt 0 2006.203.08:25:20.77#ibcon#cleared, iclass 21 cls_cnt 0 2006.203.08:25:20.77$vc4f8/va=6,6 2006.203.08:25:20.77#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.203.08:25:20.77#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.203.08:25:20.77#ibcon#ireg 11 cls_cnt 2 2006.203.08:25:20.77#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.203.08:25:20.82#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.203.08:25:20.82#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.203.08:25:20.82#ibcon#enter wrdev, iclass 23, count 2 2006.203.08:25:20.82#ibcon#first serial, iclass 23, count 2 2006.203.08:25:20.82#ibcon#enter sib2, iclass 23, count 2 2006.203.08:25:20.82#ibcon#flushed, iclass 23, count 2 2006.203.08:25:20.82#ibcon#about to write, iclass 23, count 2 2006.203.08:25:20.82#ibcon#wrote, iclass 23, count 2 2006.203.08:25:20.82#ibcon#about to read 3, iclass 23, count 2 2006.203.08:25:20.84#ibcon#read 3, iclass 23, count 2 2006.203.08:25:20.84#ibcon#about to read 4, iclass 23, count 2 2006.203.08:25:20.84#ibcon#read 4, iclass 23, count 2 2006.203.08:25:20.84#ibcon#about to read 5, iclass 23, count 2 2006.203.08:25:20.84#ibcon#read 5, iclass 23, count 2 2006.203.08:25:20.84#ibcon#about to read 6, iclass 23, count 2 2006.203.08:25:20.84#ibcon#read 6, iclass 23, count 2 2006.203.08:25:20.84#ibcon#end of sib2, iclass 23, count 2 2006.203.08:25:20.84#ibcon#*mode == 0, iclass 23, count 2 2006.203.08:25:20.84#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.203.08:25:20.84#ibcon#[25=AT06-06\r\n] 2006.203.08:25:20.84#ibcon#*before write, iclass 23, count 2 2006.203.08:25:20.84#ibcon#enter sib2, iclass 23, count 2 2006.203.08:25:20.84#ibcon#flushed, iclass 23, count 2 2006.203.08:25:20.84#ibcon#about to write, iclass 23, count 2 2006.203.08:25:20.84#ibcon#wrote, iclass 23, count 2 2006.203.08:25:20.84#ibcon#about to read 3, iclass 23, count 2 2006.203.08:25:20.87#ibcon#read 3, iclass 23, count 2 2006.203.08:25:20.87#ibcon#about to read 4, iclass 23, count 2 2006.203.08:25:20.87#ibcon#read 4, iclass 23, count 2 2006.203.08:25:20.87#ibcon#about to read 5, iclass 23, count 2 2006.203.08:25:20.87#ibcon#read 5, iclass 23, count 2 2006.203.08:25:20.87#ibcon#about to read 6, iclass 23, count 2 2006.203.08:25:20.87#ibcon#read 6, iclass 23, count 2 2006.203.08:25:20.87#ibcon#end of sib2, iclass 23, count 2 2006.203.08:25:20.87#ibcon#*after write, iclass 23, count 2 2006.203.08:25:20.87#ibcon#*before return 0, iclass 23, count 2 2006.203.08:25:20.87#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.203.08:25:20.87#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.203.08:25:20.87#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.203.08:25:20.87#ibcon#ireg 7 cls_cnt 0 2006.203.08:25:20.87#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.203.08:25:20.99#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.203.08:25:20.99#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.203.08:25:20.99#ibcon#enter wrdev, iclass 23, count 0 2006.203.08:25:20.99#ibcon#first serial, iclass 23, count 0 2006.203.08:25:20.99#ibcon#enter sib2, iclass 23, count 0 2006.203.08:25:20.99#ibcon#flushed, iclass 23, count 0 2006.203.08:25:20.99#ibcon#about to write, iclass 23, count 0 2006.203.08:25:20.99#ibcon#wrote, iclass 23, count 0 2006.203.08:25:20.99#ibcon#about to read 3, iclass 23, count 0 2006.203.08:25:21.01#ibcon#read 3, iclass 23, count 0 2006.203.08:25:21.01#ibcon#about to read 4, iclass 23, count 0 2006.203.08:25:21.01#ibcon#read 4, iclass 23, count 0 2006.203.08:25:21.01#ibcon#about to read 5, iclass 23, count 0 2006.203.08:25:21.01#ibcon#read 5, iclass 23, count 0 2006.203.08:25:21.01#ibcon#about to read 6, iclass 23, count 0 2006.203.08:25:21.01#ibcon#read 6, iclass 23, count 0 2006.203.08:25:21.01#ibcon#end of sib2, iclass 23, count 0 2006.203.08:25:21.01#ibcon#*mode == 0, iclass 23, count 0 2006.203.08:25:21.01#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.203.08:25:21.01#ibcon#[25=USB\r\n] 2006.203.08:25:21.01#ibcon#*before write, iclass 23, count 0 2006.203.08:25:21.01#ibcon#enter sib2, iclass 23, count 0 2006.203.08:25:21.01#ibcon#flushed, iclass 23, count 0 2006.203.08:25:21.01#ibcon#about to write, iclass 23, count 0 2006.203.08:25:21.01#ibcon#wrote, iclass 23, count 0 2006.203.08:25:21.01#ibcon#about to read 3, iclass 23, count 0 2006.203.08:25:21.04#ibcon#read 3, iclass 23, count 0 2006.203.08:25:21.04#ibcon#about to read 4, iclass 23, count 0 2006.203.08:25:21.04#ibcon#read 4, iclass 23, count 0 2006.203.08:25:21.04#ibcon#about to read 5, iclass 23, count 0 2006.203.08:25:21.04#ibcon#read 5, iclass 23, count 0 2006.203.08:25:21.04#ibcon#about to read 6, iclass 23, count 0 2006.203.08:25:21.04#ibcon#read 6, iclass 23, count 0 2006.203.08:25:21.04#ibcon#end of sib2, iclass 23, count 0 2006.203.08:25:21.04#ibcon#*after write, iclass 23, count 0 2006.203.08:25:21.04#ibcon#*before return 0, iclass 23, count 0 2006.203.08:25:21.04#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.203.08:25:21.04#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.203.08:25:21.04#ibcon#about to clear, iclass 23 cls_cnt 0 2006.203.08:25:21.04#ibcon#cleared, iclass 23 cls_cnt 0 2006.203.08:25:21.04$vc4f8/valo=7,832.99 2006.203.08:25:21.04#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.203.08:25:21.04#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.203.08:25:21.04#ibcon#ireg 17 cls_cnt 0 2006.203.08:25:21.04#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.203.08:25:21.04#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.203.08:25:21.04#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.203.08:25:21.04#ibcon#enter wrdev, iclass 25, count 0 2006.203.08:25:21.04#ibcon#first serial, iclass 25, count 0 2006.203.08:25:21.04#ibcon#enter sib2, iclass 25, count 0 2006.203.08:25:21.04#ibcon#flushed, iclass 25, count 0 2006.203.08:25:21.04#ibcon#about to write, iclass 25, count 0 2006.203.08:25:21.04#ibcon#wrote, iclass 25, count 0 2006.203.08:25:21.04#ibcon#about to read 3, iclass 25, count 0 2006.203.08:25:21.06#ibcon#read 3, iclass 25, count 0 2006.203.08:25:21.06#ibcon#about to read 4, iclass 25, count 0 2006.203.08:25:21.06#ibcon#read 4, iclass 25, count 0 2006.203.08:25:21.06#ibcon#about to read 5, iclass 25, count 0 2006.203.08:25:21.06#ibcon#read 5, iclass 25, count 0 2006.203.08:25:21.06#ibcon#about to read 6, iclass 25, count 0 2006.203.08:25:21.06#ibcon#read 6, iclass 25, count 0 2006.203.08:25:21.06#ibcon#end of sib2, iclass 25, count 0 2006.203.08:25:21.06#ibcon#*mode == 0, iclass 25, count 0 2006.203.08:25:21.06#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.203.08:25:21.06#ibcon#[26=FRQ=07,832.99\r\n] 2006.203.08:25:21.06#ibcon#*before write, iclass 25, count 0 2006.203.08:25:21.06#ibcon#enter sib2, iclass 25, count 0 2006.203.08:25:21.06#ibcon#flushed, iclass 25, count 0 2006.203.08:25:21.06#ibcon#about to write, iclass 25, count 0 2006.203.08:25:21.06#ibcon#wrote, iclass 25, count 0 2006.203.08:25:21.06#ibcon#about to read 3, iclass 25, count 0 2006.203.08:25:21.10#ibcon#read 3, iclass 25, count 0 2006.203.08:25:21.10#ibcon#about to read 4, iclass 25, count 0 2006.203.08:25:21.10#ibcon#read 4, iclass 25, count 0 2006.203.08:25:21.10#ibcon#about to read 5, iclass 25, count 0 2006.203.08:25:21.10#ibcon#read 5, iclass 25, count 0 2006.203.08:25:21.10#ibcon#about to read 6, iclass 25, count 0 2006.203.08:25:21.10#ibcon#read 6, iclass 25, count 0 2006.203.08:25:21.10#ibcon#end of sib2, iclass 25, count 0 2006.203.08:25:21.10#ibcon#*after write, iclass 25, count 0 2006.203.08:25:21.10#ibcon#*before return 0, iclass 25, count 0 2006.203.08:25:21.10#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.203.08:25:21.10#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.203.08:25:21.10#ibcon#about to clear, iclass 25 cls_cnt 0 2006.203.08:25:21.10#ibcon#cleared, iclass 25 cls_cnt 0 2006.203.08:25:21.10$vc4f8/va=7,7 2006.203.08:25:21.10#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.203.08:25:21.10#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.203.08:25:21.10#ibcon#ireg 11 cls_cnt 2 2006.203.08:25:21.10#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.203.08:25:21.16#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.203.08:25:21.16#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.203.08:25:21.16#ibcon#enter wrdev, iclass 27, count 2 2006.203.08:25:21.16#ibcon#first serial, iclass 27, count 2 2006.203.08:25:21.16#ibcon#enter sib2, iclass 27, count 2 2006.203.08:25:21.16#ibcon#flushed, iclass 27, count 2 2006.203.08:25:21.16#ibcon#about to write, iclass 27, count 2 2006.203.08:25:21.16#ibcon#wrote, iclass 27, count 2 2006.203.08:25:21.16#ibcon#about to read 3, iclass 27, count 2 2006.203.08:25:21.18#ibcon#read 3, iclass 27, count 2 2006.203.08:25:21.18#ibcon#about to read 4, iclass 27, count 2 2006.203.08:25:21.18#ibcon#read 4, iclass 27, count 2 2006.203.08:25:21.18#ibcon#about to read 5, iclass 27, count 2 2006.203.08:25:21.18#ibcon#read 5, iclass 27, count 2 2006.203.08:25:21.18#ibcon#about to read 6, iclass 27, count 2 2006.203.08:25:21.18#ibcon#read 6, iclass 27, count 2 2006.203.08:25:21.18#ibcon#end of sib2, iclass 27, count 2 2006.203.08:25:21.18#ibcon#*mode == 0, iclass 27, count 2 2006.203.08:25:21.18#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.203.08:25:21.18#ibcon#[25=AT07-07\r\n] 2006.203.08:25:21.18#ibcon#*before write, iclass 27, count 2 2006.203.08:25:21.18#ibcon#enter sib2, iclass 27, count 2 2006.203.08:25:21.18#ibcon#flushed, iclass 27, count 2 2006.203.08:25:21.18#ibcon#about to write, iclass 27, count 2 2006.203.08:25:21.18#ibcon#wrote, iclass 27, count 2 2006.203.08:25:21.18#ibcon#about to read 3, iclass 27, count 2 2006.203.08:25:21.21#ibcon#read 3, iclass 27, count 2 2006.203.08:25:21.21#ibcon#about to read 4, iclass 27, count 2 2006.203.08:25:21.21#ibcon#read 4, iclass 27, count 2 2006.203.08:25:21.21#ibcon#about to read 5, iclass 27, count 2 2006.203.08:25:21.21#ibcon#read 5, iclass 27, count 2 2006.203.08:25:21.21#ibcon#about to read 6, iclass 27, count 2 2006.203.08:25:21.21#ibcon#read 6, iclass 27, count 2 2006.203.08:25:21.21#ibcon#end of sib2, iclass 27, count 2 2006.203.08:25:21.21#ibcon#*after write, iclass 27, count 2 2006.203.08:25:21.21#ibcon#*before return 0, iclass 27, count 2 2006.203.08:25:21.21#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.203.08:25:21.21#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.203.08:25:21.21#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.203.08:25:21.21#ibcon#ireg 7 cls_cnt 0 2006.203.08:25:21.21#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.203.08:25:21.22#abcon#<5=/04 1.1 2.5 23.54 991001.3\r\n> 2006.203.08:25:21.24#abcon#{5=INTERFACE CLEAR} 2006.203.08:25:21.30#abcon#[5=S1D000X0/0*\r\n] 2006.203.08:25:21.33#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.203.08:25:21.33#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.203.08:25:21.33#ibcon#enter wrdev, iclass 27, count 0 2006.203.08:25:21.33#ibcon#first serial, iclass 27, count 0 2006.203.08:25:21.33#ibcon#enter sib2, iclass 27, count 0 2006.203.08:25:21.33#ibcon#flushed, iclass 27, count 0 2006.203.08:25:21.33#ibcon#about to write, iclass 27, count 0 2006.203.08:25:21.33#ibcon#wrote, iclass 27, count 0 2006.203.08:25:21.33#ibcon#about to read 3, iclass 27, count 0 2006.203.08:25:21.37#ibcon#read 3, iclass 27, count 0 2006.203.08:25:21.37#ibcon#about to read 4, iclass 27, count 0 2006.203.08:25:21.37#ibcon#read 4, iclass 27, count 0 2006.203.08:25:21.37#ibcon#about to read 5, iclass 27, count 0 2006.203.08:25:21.37#ibcon#read 5, iclass 27, count 0 2006.203.08:25:21.37#ibcon#about to read 6, iclass 27, count 0 2006.203.08:25:21.37#ibcon#read 6, iclass 27, count 0 2006.203.08:25:21.37#ibcon#end of sib2, iclass 27, count 0 2006.203.08:25:21.37#ibcon#*mode == 0, iclass 27, count 0 2006.203.08:25:21.37#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.203.08:25:21.37#ibcon#[25=USB\r\n] 2006.203.08:25:21.37#ibcon#*before write, iclass 27, count 0 2006.203.08:25:21.37#ibcon#enter sib2, iclass 27, count 0 2006.203.08:25:21.37#ibcon#flushed, iclass 27, count 0 2006.203.08:25:21.37#ibcon#about to write, iclass 27, count 0 2006.203.08:25:21.37#ibcon#wrote, iclass 27, count 0 2006.203.08:25:21.37#ibcon#about to read 3, iclass 27, count 0 2006.203.08:25:21.39#ibcon#read 3, iclass 27, count 0 2006.203.08:25:21.39#ibcon#about to read 4, iclass 27, count 0 2006.203.08:25:21.39#ibcon#read 4, iclass 27, count 0 2006.203.08:25:21.39#ibcon#about to read 5, iclass 27, count 0 2006.203.08:25:21.39#ibcon#read 5, iclass 27, count 0 2006.203.08:25:21.39#ibcon#about to read 6, iclass 27, count 0 2006.203.08:25:21.39#ibcon#read 6, iclass 27, count 0 2006.203.08:25:21.39#ibcon#end of sib2, iclass 27, count 0 2006.203.08:25:21.39#ibcon#*after write, iclass 27, count 0 2006.203.08:25:21.39#ibcon#*before return 0, iclass 27, count 0 2006.203.08:25:21.39#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.203.08:25:21.39#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.203.08:25:21.39#ibcon#about to clear, iclass 27 cls_cnt 0 2006.203.08:25:21.39#ibcon#cleared, iclass 27 cls_cnt 0 2006.203.08:25:21.39$vc4f8/valo=8,852.99 2006.203.08:25:21.39#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.203.08:25:21.39#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.203.08:25:21.39#ibcon#ireg 17 cls_cnt 0 2006.203.08:25:21.39#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.203.08:25:21.39#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.203.08:25:21.39#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.203.08:25:21.39#ibcon#enter wrdev, iclass 33, count 0 2006.203.08:25:21.39#ibcon#first serial, iclass 33, count 0 2006.203.08:25:21.39#ibcon#enter sib2, iclass 33, count 0 2006.203.08:25:21.39#ibcon#flushed, iclass 33, count 0 2006.203.08:25:21.39#ibcon#about to write, iclass 33, count 0 2006.203.08:25:21.39#ibcon#wrote, iclass 33, count 0 2006.203.08:25:21.39#ibcon#about to read 3, iclass 33, count 0 2006.203.08:25:21.41#ibcon#read 3, iclass 33, count 0 2006.203.08:25:21.41#ibcon#about to read 4, iclass 33, count 0 2006.203.08:25:21.41#ibcon#read 4, iclass 33, count 0 2006.203.08:25:21.41#ibcon#about to read 5, iclass 33, count 0 2006.203.08:25:21.41#ibcon#read 5, iclass 33, count 0 2006.203.08:25:21.41#ibcon#about to read 6, iclass 33, count 0 2006.203.08:25:21.41#ibcon#read 6, iclass 33, count 0 2006.203.08:25:21.41#ibcon#end of sib2, iclass 33, count 0 2006.203.08:25:21.41#ibcon#*mode == 0, iclass 33, count 0 2006.203.08:25:21.41#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.203.08:25:21.41#ibcon#[26=FRQ=08,852.99\r\n] 2006.203.08:25:21.41#ibcon#*before write, iclass 33, count 0 2006.203.08:25:21.41#ibcon#enter sib2, iclass 33, count 0 2006.203.08:25:21.41#ibcon#flushed, iclass 33, count 0 2006.203.08:25:21.41#ibcon#about to write, iclass 33, count 0 2006.203.08:25:21.41#ibcon#wrote, iclass 33, count 0 2006.203.08:25:21.41#ibcon#about to read 3, iclass 33, count 0 2006.203.08:25:21.45#ibcon#read 3, iclass 33, count 0 2006.203.08:25:21.45#ibcon#about to read 4, iclass 33, count 0 2006.203.08:25:21.45#ibcon#read 4, iclass 33, count 0 2006.203.08:25:21.45#ibcon#about to read 5, iclass 33, count 0 2006.203.08:25:21.45#ibcon#read 5, iclass 33, count 0 2006.203.08:25:21.45#ibcon#about to read 6, iclass 33, count 0 2006.203.08:25:21.45#ibcon#read 6, iclass 33, count 0 2006.203.08:25:21.45#ibcon#end of sib2, iclass 33, count 0 2006.203.08:25:21.45#ibcon#*after write, iclass 33, count 0 2006.203.08:25:21.45#ibcon#*before return 0, iclass 33, count 0 2006.203.08:25:21.45#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.203.08:25:21.45#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.203.08:25:21.45#ibcon#about to clear, iclass 33 cls_cnt 0 2006.203.08:25:21.45#ibcon#cleared, iclass 33 cls_cnt 0 2006.203.08:25:21.45$vc4f8/va=8,6 2006.203.08:25:21.45#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.203.08:25:21.45#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.203.08:25:21.45#ibcon#ireg 11 cls_cnt 2 2006.203.08:25:21.45#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.203.08:25:21.51#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.203.08:25:21.51#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.203.08:25:21.51#ibcon#enter wrdev, iclass 35, count 2 2006.203.08:25:21.51#ibcon#first serial, iclass 35, count 2 2006.203.08:25:21.51#ibcon#enter sib2, iclass 35, count 2 2006.203.08:25:21.51#ibcon#flushed, iclass 35, count 2 2006.203.08:25:21.51#ibcon#about to write, iclass 35, count 2 2006.203.08:25:21.51#ibcon#wrote, iclass 35, count 2 2006.203.08:25:21.51#ibcon#about to read 3, iclass 35, count 2 2006.203.08:25:21.53#ibcon#read 3, iclass 35, count 2 2006.203.08:25:21.53#ibcon#about to read 4, iclass 35, count 2 2006.203.08:25:21.53#ibcon#read 4, iclass 35, count 2 2006.203.08:25:21.53#ibcon#about to read 5, iclass 35, count 2 2006.203.08:25:21.53#ibcon#read 5, iclass 35, count 2 2006.203.08:25:21.53#ibcon#about to read 6, iclass 35, count 2 2006.203.08:25:21.53#ibcon#read 6, iclass 35, count 2 2006.203.08:25:21.53#ibcon#end of sib2, iclass 35, count 2 2006.203.08:25:21.53#ibcon#*mode == 0, iclass 35, count 2 2006.203.08:25:21.53#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.203.08:25:21.53#ibcon#[25=AT08-06\r\n] 2006.203.08:25:21.53#ibcon#*before write, iclass 35, count 2 2006.203.08:25:21.53#ibcon#enter sib2, iclass 35, count 2 2006.203.08:25:21.53#ibcon#flushed, iclass 35, count 2 2006.203.08:25:21.53#ibcon#about to write, iclass 35, count 2 2006.203.08:25:21.53#ibcon#wrote, iclass 35, count 2 2006.203.08:25:21.53#ibcon#about to read 3, iclass 35, count 2 2006.203.08:25:21.56#ibcon#read 3, iclass 35, count 2 2006.203.08:25:21.56#ibcon#about to read 4, iclass 35, count 2 2006.203.08:25:21.56#ibcon#read 4, iclass 35, count 2 2006.203.08:25:21.56#ibcon#about to read 5, iclass 35, count 2 2006.203.08:25:21.56#ibcon#read 5, iclass 35, count 2 2006.203.08:25:21.56#ibcon#about to read 6, iclass 35, count 2 2006.203.08:25:21.56#ibcon#read 6, iclass 35, count 2 2006.203.08:25:21.56#ibcon#end of sib2, iclass 35, count 2 2006.203.08:25:21.56#ibcon#*after write, iclass 35, count 2 2006.203.08:25:21.56#ibcon#*before return 0, iclass 35, count 2 2006.203.08:25:21.56#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.203.08:25:21.56#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.203.08:25:21.56#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.203.08:25:21.56#ibcon#ireg 7 cls_cnt 0 2006.203.08:25:21.56#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.203.08:25:21.68#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.203.08:25:21.68#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.203.08:25:21.68#ibcon#enter wrdev, iclass 35, count 0 2006.203.08:25:21.68#ibcon#first serial, iclass 35, count 0 2006.203.08:25:21.68#ibcon#enter sib2, iclass 35, count 0 2006.203.08:25:21.68#ibcon#flushed, iclass 35, count 0 2006.203.08:25:21.68#ibcon#about to write, iclass 35, count 0 2006.203.08:25:21.68#ibcon#wrote, iclass 35, count 0 2006.203.08:25:21.68#ibcon#about to read 3, iclass 35, count 0 2006.203.08:25:21.70#ibcon#read 3, iclass 35, count 0 2006.203.08:25:21.70#ibcon#about to read 4, iclass 35, count 0 2006.203.08:25:21.70#ibcon#read 4, iclass 35, count 0 2006.203.08:25:21.70#ibcon#about to read 5, iclass 35, count 0 2006.203.08:25:21.70#ibcon#read 5, iclass 35, count 0 2006.203.08:25:21.70#ibcon#about to read 6, iclass 35, count 0 2006.203.08:25:21.70#ibcon#read 6, iclass 35, count 0 2006.203.08:25:21.70#ibcon#end of sib2, iclass 35, count 0 2006.203.08:25:21.70#ibcon#*mode == 0, iclass 35, count 0 2006.203.08:25:21.70#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.203.08:25:21.70#ibcon#[25=USB\r\n] 2006.203.08:25:21.70#ibcon#*before write, iclass 35, count 0 2006.203.08:25:21.70#ibcon#enter sib2, iclass 35, count 0 2006.203.08:25:21.70#ibcon#flushed, iclass 35, count 0 2006.203.08:25:21.70#ibcon#about to write, iclass 35, count 0 2006.203.08:25:21.70#ibcon#wrote, iclass 35, count 0 2006.203.08:25:21.70#ibcon#about to read 3, iclass 35, count 0 2006.203.08:25:21.73#ibcon#read 3, iclass 35, count 0 2006.203.08:25:21.73#ibcon#about to read 4, iclass 35, count 0 2006.203.08:25:21.73#ibcon#read 4, iclass 35, count 0 2006.203.08:25:21.73#ibcon#about to read 5, iclass 35, count 0 2006.203.08:25:21.73#ibcon#read 5, iclass 35, count 0 2006.203.08:25:21.73#ibcon#about to read 6, iclass 35, count 0 2006.203.08:25:21.73#ibcon#read 6, iclass 35, count 0 2006.203.08:25:21.73#ibcon#end of sib2, iclass 35, count 0 2006.203.08:25:21.73#ibcon#*after write, iclass 35, count 0 2006.203.08:25:21.73#ibcon#*before return 0, iclass 35, count 0 2006.203.08:25:21.73#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.203.08:25:21.73#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.203.08:25:21.73#ibcon#about to clear, iclass 35 cls_cnt 0 2006.203.08:25:21.73#ibcon#cleared, iclass 35 cls_cnt 0 2006.203.08:25:21.73$vc4f8/vblo=1,632.99 2006.203.08:25:21.73#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.203.08:25:21.73#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.203.08:25:21.73#ibcon#ireg 17 cls_cnt 0 2006.203.08:25:21.73#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.203.08:25:21.73#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.203.08:25:21.73#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.203.08:25:21.73#ibcon#enter wrdev, iclass 37, count 0 2006.203.08:25:21.73#ibcon#first serial, iclass 37, count 0 2006.203.08:25:21.73#ibcon#enter sib2, iclass 37, count 0 2006.203.08:25:21.73#ibcon#flushed, iclass 37, count 0 2006.203.08:25:21.73#ibcon#about to write, iclass 37, count 0 2006.203.08:25:21.73#ibcon#wrote, iclass 37, count 0 2006.203.08:25:21.73#ibcon#about to read 3, iclass 37, count 0 2006.203.08:25:21.75#ibcon#read 3, iclass 37, count 0 2006.203.08:25:21.75#ibcon#about to read 4, iclass 37, count 0 2006.203.08:25:21.75#ibcon#read 4, iclass 37, count 0 2006.203.08:25:21.75#ibcon#about to read 5, iclass 37, count 0 2006.203.08:25:21.75#ibcon#read 5, iclass 37, count 0 2006.203.08:25:21.75#ibcon#about to read 6, iclass 37, count 0 2006.203.08:25:21.75#ibcon#read 6, iclass 37, count 0 2006.203.08:25:21.75#ibcon#end of sib2, iclass 37, count 0 2006.203.08:25:21.75#ibcon#*mode == 0, iclass 37, count 0 2006.203.08:25:21.75#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.203.08:25:21.75#ibcon#[28=FRQ=01,632.99\r\n] 2006.203.08:25:21.75#ibcon#*before write, iclass 37, count 0 2006.203.08:25:21.75#ibcon#enter sib2, iclass 37, count 0 2006.203.08:25:21.75#ibcon#flushed, iclass 37, count 0 2006.203.08:25:21.75#ibcon#about to write, iclass 37, count 0 2006.203.08:25:21.75#ibcon#wrote, iclass 37, count 0 2006.203.08:25:21.75#ibcon#about to read 3, iclass 37, count 0 2006.203.08:25:21.79#ibcon#read 3, iclass 37, count 0 2006.203.08:25:21.79#ibcon#about to read 4, iclass 37, count 0 2006.203.08:25:21.79#ibcon#read 4, iclass 37, count 0 2006.203.08:25:21.79#ibcon#about to read 5, iclass 37, count 0 2006.203.08:25:21.79#ibcon#read 5, iclass 37, count 0 2006.203.08:25:21.79#ibcon#about to read 6, iclass 37, count 0 2006.203.08:25:21.79#ibcon#read 6, iclass 37, count 0 2006.203.08:25:21.79#ibcon#end of sib2, iclass 37, count 0 2006.203.08:25:21.79#ibcon#*after write, iclass 37, count 0 2006.203.08:25:21.79#ibcon#*before return 0, iclass 37, count 0 2006.203.08:25:21.79#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.203.08:25:21.79#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.203.08:25:21.79#ibcon#about to clear, iclass 37 cls_cnt 0 2006.203.08:25:21.79#ibcon#cleared, iclass 37 cls_cnt 0 2006.203.08:25:21.79$vc4f8/vb=1,4 2006.203.08:25:21.79#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.203.08:25:21.79#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.203.08:25:21.79#ibcon#ireg 11 cls_cnt 2 2006.203.08:25:21.79#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.203.08:25:21.79#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.203.08:25:21.79#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.203.08:25:21.79#ibcon#enter wrdev, iclass 39, count 2 2006.203.08:25:21.79#ibcon#first serial, iclass 39, count 2 2006.203.08:25:21.79#ibcon#enter sib2, iclass 39, count 2 2006.203.08:25:21.79#ibcon#flushed, iclass 39, count 2 2006.203.08:25:21.79#ibcon#about to write, iclass 39, count 2 2006.203.08:25:21.79#ibcon#wrote, iclass 39, count 2 2006.203.08:25:21.79#ibcon#about to read 3, iclass 39, count 2 2006.203.08:25:21.81#ibcon#read 3, iclass 39, count 2 2006.203.08:25:21.81#ibcon#about to read 4, iclass 39, count 2 2006.203.08:25:21.81#ibcon#read 4, iclass 39, count 2 2006.203.08:25:21.81#ibcon#about to read 5, iclass 39, count 2 2006.203.08:25:21.81#ibcon#read 5, iclass 39, count 2 2006.203.08:25:21.81#ibcon#about to read 6, iclass 39, count 2 2006.203.08:25:21.81#ibcon#read 6, iclass 39, count 2 2006.203.08:25:21.81#ibcon#end of sib2, iclass 39, count 2 2006.203.08:25:21.81#ibcon#*mode == 0, iclass 39, count 2 2006.203.08:25:21.81#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.203.08:25:21.81#ibcon#[27=AT01-04\r\n] 2006.203.08:25:21.81#ibcon#*before write, iclass 39, count 2 2006.203.08:25:21.81#ibcon#enter sib2, iclass 39, count 2 2006.203.08:25:21.81#ibcon#flushed, iclass 39, count 2 2006.203.08:25:21.81#ibcon#about to write, iclass 39, count 2 2006.203.08:25:21.81#ibcon#wrote, iclass 39, count 2 2006.203.08:25:21.81#ibcon#about to read 3, iclass 39, count 2 2006.203.08:25:21.84#ibcon#read 3, iclass 39, count 2 2006.203.08:25:21.84#ibcon#about to read 4, iclass 39, count 2 2006.203.08:25:21.84#ibcon#read 4, iclass 39, count 2 2006.203.08:25:21.84#ibcon#about to read 5, iclass 39, count 2 2006.203.08:25:21.84#ibcon#read 5, iclass 39, count 2 2006.203.08:25:21.84#ibcon#about to read 6, iclass 39, count 2 2006.203.08:25:21.84#ibcon#read 6, iclass 39, count 2 2006.203.08:25:21.84#ibcon#end of sib2, iclass 39, count 2 2006.203.08:25:21.84#ibcon#*after write, iclass 39, count 2 2006.203.08:25:21.84#ibcon#*before return 0, iclass 39, count 2 2006.203.08:25:21.84#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.203.08:25:21.84#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.203.08:25:21.84#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.203.08:25:21.84#ibcon#ireg 7 cls_cnt 0 2006.203.08:25:21.84#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.203.08:25:21.96#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.203.08:25:21.96#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.203.08:25:21.96#ibcon#enter wrdev, iclass 39, count 0 2006.203.08:25:21.96#ibcon#first serial, iclass 39, count 0 2006.203.08:25:21.96#ibcon#enter sib2, iclass 39, count 0 2006.203.08:25:21.96#ibcon#flushed, iclass 39, count 0 2006.203.08:25:21.96#ibcon#about to write, iclass 39, count 0 2006.203.08:25:21.96#ibcon#wrote, iclass 39, count 0 2006.203.08:25:21.96#ibcon#about to read 3, iclass 39, count 0 2006.203.08:25:21.98#ibcon#read 3, iclass 39, count 0 2006.203.08:25:21.98#ibcon#about to read 4, iclass 39, count 0 2006.203.08:25:21.98#ibcon#read 4, iclass 39, count 0 2006.203.08:25:21.98#ibcon#about to read 5, iclass 39, count 0 2006.203.08:25:21.98#ibcon#read 5, iclass 39, count 0 2006.203.08:25:21.98#ibcon#about to read 6, iclass 39, count 0 2006.203.08:25:21.98#ibcon#read 6, iclass 39, count 0 2006.203.08:25:21.98#ibcon#end of sib2, iclass 39, count 0 2006.203.08:25:21.98#ibcon#*mode == 0, iclass 39, count 0 2006.203.08:25:21.98#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.203.08:25:21.98#ibcon#[27=USB\r\n] 2006.203.08:25:21.98#ibcon#*before write, iclass 39, count 0 2006.203.08:25:21.98#ibcon#enter sib2, iclass 39, count 0 2006.203.08:25:21.98#ibcon#flushed, iclass 39, count 0 2006.203.08:25:21.98#ibcon#about to write, iclass 39, count 0 2006.203.08:25:21.98#ibcon#wrote, iclass 39, count 0 2006.203.08:25:21.98#ibcon#about to read 3, iclass 39, count 0 2006.203.08:25:22.01#ibcon#read 3, iclass 39, count 0 2006.203.08:25:22.01#ibcon#about to read 4, iclass 39, count 0 2006.203.08:25:22.01#ibcon#read 4, iclass 39, count 0 2006.203.08:25:22.01#ibcon#about to read 5, iclass 39, count 0 2006.203.08:25:22.01#ibcon#read 5, iclass 39, count 0 2006.203.08:25:22.01#ibcon#about to read 6, iclass 39, count 0 2006.203.08:25:22.01#ibcon#read 6, iclass 39, count 0 2006.203.08:25:22.01#ibcon#end of sib2, iclass 39, count 0 2006.203.08:25:22.01#ibcon#*after write, iclass 39, count 0 2006.203.08:25:22.01#ibcon#*before return 0, iclass 39, count 0 2006.203.08:25:22.01#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.203.08:25:22.01#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.203.08:25:22.01#ibcon#about to clear, iclass 39 cls_cnt 0 2006.203.08:25:22.01#ibcon#cleared, iclass 39 cls_cnt 0 2006.203.08:25:22.01$vc4f8/vblo=2,640.99 2006.203.08:25:22.01#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.203.08:25:22.01#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.203.08:25:22.01#ibcon#ireg 17 cls_cnt 0 2006.203.08:25:22.01#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.203.08:25:22.01#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.203.08:25:22.01#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.203.08:25:22.01#ibcon#enter wrdev, iclass 3, count 0 2006.203.08:25:22.01#ibcon#first serial, iclass 3, count 0 2006.203.08:25:22.01#ibcon#enter sib2, iclass 3, count 0 2006.203.08:25:22.01#ibcon#flushed, iclass 3, count 0 2006.203.08:25:22.01#ibcon#about to write, iclass 3, count 0 2006.203.08:25:22.01#ibcon#wrote, iclass 3, count 0 2006.203.08:25:22.01#ibcon#about to read 3, iclass 3, count 0 2006.203.08:25:22.04#ibcon#read 3, iclass 3, count 0 2006.203.08:25:22.04#ibcon#about to read 4, iclass 3, count 0 2006.203.08:25:22.04#ibcon#read 4, iclass 3, count 0 2006.203.08:25:22.04#ibcon#about to read 5, iclass 3, count 0 2006.203.08:25:22.04#ibcon#read 5, iclass 3, count 0 2006.203.08:25:22.04#ibcon#about to read 6, iclass 3, count 0 2006.203.08:25:22.04#ibcon#read 6, iclass 3, count 0 2006.203.08:25:22.04#ibcon#end of sib2, iclass 3, count 0 2006.203.08:25:22.04#ibcon#*mode == 0, iclass 3, count 0 2006.203.08:25:22.04#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.203.08:25:22.04#ibcon#[28=FRQ=02,640.99\r\n] 2006.203.08:25:22.04#ibcon#*before write, iclass 3, count 0 2006.203.08:25:22.04#ibcon#enter sib2, iclass 3, count 0 2006.203.08:25:22.04#ibcon#flushed, iclass 3, count 0 2006.203.08:25:22.04#ibcon#about to write, iclass 3, count 0 2006.203.08:25:22.04#ibcon#wrote, iclass 3, count 0 2006.203.08:25:22.04#ibcon#about to read 3, iclass 3, count 0 2006.203.08:25:22.08#ibcon#read 3, iclass 3, count 0 2006.203.08:25:22.08#ibcon#about to read 4, iclass 3, count 0 2006.203.08:25:22.08#ibcon#read 4, iclass 3, count 0 2006.203.08:25:22.08#ibcon#about to read 5, iclass 3, count 0 2006.203.08:25:22.08#ibcon#read 5, iclass 3, count 0 2006.203.08:25:22.08#ibcon#about to read 6, iclass 3, count 0 2006.203.08:25:22.08#ibcon#read 6, iclass 3, count 0 2006.203.08:25:22.08#ibcon#end of sib2, iclass 3, count 0 2006.203.08:25:22.08#ibcon#*after write, iclass 3, count 0 2006.203.08:25:22.08#ibcon#*before return 0, iclass 3, count 0 2006.203.08:25:22.08#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.203.08:25:22.08#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.203.08:25:22.08#ibcon#about to clear, iclass 3 cls_cnt 0 2006.203.08:25:22.08#ibcon#cleared, iclass 3 cls_cnt 0 2006.203.08:25:22.08$vc4f8/vb=2,4 2006.203.08:25:22.08#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.203.08:25:22.08#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.203.08:25:22.08#ibcon#ireg 11 cls_cnt 2 2006.203.08:25:22.08#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.203.08:25:22.13#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.203.08:25:22.13#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.203.08:25:22.13#ibcon#enter wrdev, iclass 5, count 2 2006.203.08:25:22.13#ibcon#first serial, iclass 5, count 2 2006.203.08:25:22.13#ibcon#enter sib2, iclass 5, count 2 2006.203.08:25:22.13#ibcon#flushed, iclass 5, count 2 2006.203.08:25:22.13#ibcon#about to write, iclass 5, count 2 2006.203.08:25:22.13#ibcon#wrote, iclass 5, count 2 2006.203.08:25:22.13#ibcon#about to read 3, iclass 5, count 2 2006.203.08:25:22.15#ibcon#read 3, iclass 5, count 2 2006.203.08:25:22.15#ibcon#about to read 4, iclass 5, count 2 2006.203.08:25:22.15#ibcon#read 4, iclass 5, count 2 2006.203.08:25:22.15#ibcon#about to read 5, iclass 5, count 2 2006.203.08:25:22.15#ibcon#read 5, iclass 5, count 2 2006.203.08:25:22.15#ibcon#about to read 6, iclass 5, count 2 2006.203.08:25:22.15#ibcon#read 6, iclass 5, count 2 2006.203.08:25:22.15#ibcon#end of sib2, iclass 5, count 2 2006.203.08:25:22.15#ibcon#*mode == 0, iclass 5, count 2 2006.203.08:25:22.15#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.203.08:25:22.15#ibcon#[27=AT02-04\r\n] 2006.203.08:25:22.15#ibcon#*before write, iclass 5, count 2 2006.203.08:25:22.15#ibcon#enter sib2, iclass 5, count 2 2006.203.08:25:22.15#ibcon#flushed, iclass 5, count 2 2006.203.08:25:22.15#ibcon#about to write, iclass 5, count 2 2006.203.08:25:22.15#ibcon#wrote, iclass 5, count 2 2006.203.08:25:22.15#ibcon#about to read 3, iclass 5, count 2 2006.203.08:25:22.18#ibcon#read 3, iclass 5, count 2 2006.203.08:25:22.18#ibcon#about to read 4, iclass 5, count 2 2006.203.08:25:22.18#ibcon#read 4, iclass 5, count 2 2006.203.08:25:22.18#ibcon#about to read 5, iclass 5, count 2 2006.203.08:25:22.18#ibcon#read 5, iclass 5, count 2 2006.203.08:25:22.18#ibcon#about to read 6, iclass 5, count 2 2006.203.08:25:22.18#ibcon#read 6, iclass 5, count 2 2006.203.08:25:22.18#ibcon#end of sib2, iclass 5, count 2 2006.203.08:25:22.18#ibcon#*after write, iclass 5, count 2 2006.203.08:25:22.18#ibcon#*before return 0, iclass 5, count 2 2006.203.08:25:22.18#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.203.08:25:22.18#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.203.08:25:22.18#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.203.08:25:22.18#ibcon#ireg 7 cls_cnt 0 2006.203.08:25:22.18#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.203.08:25:22.30#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.203.08:25:22.30#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.203.08:25:22.30#ibcon#enter wrdev, iclass 5, count 0 2006.203.08:25:22.30#ibcon#first serial, iclass 5, count 0 2006.203.08:25:22.30#ibcon#enter sib2, iclass 5, count 0 2006.203.08:25:22.30#ibcon#flushed, iclass 5, count 0 2006.203.08:25:22.30#ibcon#about to write, iclass 5, count 0 2006.203.08:25:22.30#ibcon#wrote, iclass 5, count 0 2006.203.08:25:22.30#ibcon#about to read 3, iclass 5, count 0 2006.203.08:25:22.32#ibcon#read 3, iclass 5, count 0 2006.203.08:25:22.32#ibcon#about to read 4, iclass 5, count 0 2006.203.08:25:22.32#ibcon#read 4, iclass 5, count 0 2006.203.08:25:22.32#ibcon#about to read 5, iclass 5, count 0 2006.203.08:25:22.32#ibcon#read 5, iclass 5, count 0 2006.203.08:25:22.32#ibcon#about to read 6, iclass 5, count 0 2006.203.08:25:22.32#ibcon#read 6, iclass 5, count 0 2006.203.08:25:22.32#ibcon#end of sib2, iclass 5, count 0 2006.203.08:25:22.32#ibcon#*mode == 0, iclass 5, count 0 2006.203.08:25:22.32#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.203.08:25:22.32#ibcon#[27=USB\r\n] 2006.203.08:25:22.32#ibcon#*before write, iclass 5, count 0 2006.203.08:25:22.32#ibcon#enter sib2, iclass 5, count 0 2006.203.08:25:22.32#ibcon#flushed, iclass 5, count 0 2006.203.08:25:22.32#ibcon#about to write, iclass 5, count 0 2006.203.08:25:22.32#ibcon#wrote, iclass 5, count 0 2006.203.08:25:22.32#ibcon#about to read 3, iclass 5, count 0 2006.203.08:25:22.35#ibcon#read 3, iclass 5, count 0 2006.203.08:25:22.35#ibcon#about to read 4, iclass 5, count 0 2006.203.08:25:22.35#ibcon#read 4, iclass 5, count 0 2006.203.08:25:22.35#ibcon#about to read 5, iclass 5, count 0 2006.203.08:25:22.35#ibcon#read 5, iclass 5, count 0 2006.203.08:25:22.35#ibcon#about to read 6, iclass 5, count 0 2006.203.08:25:22.35#ibcon#read 6, iclass 5, count 0 2006.203.08:25:22.35#ibcon#end of sib2, iclass 5, count 0 2006.203.08:25:22.35#ibcon#*after write, iclass 5, count 0 2006.203.08:25:22.35#ibcon#*before return 0, iclass 5, count 0 2006.203.08:25:22.35#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.203.08:25:22.35#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.203.08:25:22.35#ibcon#about to clear, iclass 5 cls_cnt 0 2006.203.08:25:22.35#ibcon#cleared, iclass 5 cls_cnt 0 2006.203.08:25:22.35$vc4f8/vblo=3,656.99 2006.203.08:25:22.35#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.203.08:25:22.35#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.203.08:25:22.35#ibcon#ireg 17 cls_cnt 0 2006.203.08:25:22.35#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.203.08:25:22.35#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.203.08:25:22.35#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.203.08:25:22.35#ibcon#enter wrdev, iclass 7, count 0 2006.203.08:25:22.35#ibcon#first serial, iclass 7, count 0 2006.203.08:25:22.35#ibcon#enter sib2, iclass 7, count 0 2006.203.08:25:22.35#ibcon#flushed, iclass 7, count 0 2006.203.08:25:22.35#ibcon#about to write, iclass 7, count 0 2006.203.08:25:22.35#ibcon#wrote, iclass 7, count 0 2006.203.08:25:22.35#ibcon#about to read 3, iclass 7, count 0 2006.203.08:25:22.37#ibcon#read 3, iclass 7, count 0 2006.203.08:25:22.37#ibcon#about to read 4, iclass 7, count 0 2006.203.08:25:22.37#ibcon#read 4, iclass 7, count 0 2006.203.08:25:22.37#ibcon#about to read 5, iclass 7, count 0 2006.203.08:25:22.37#ibcon#read 5, iclass 7, count 0 2006.203.08:25:22.37#ibcon#about to read 6, iclass 7, count 0 2006.203.08:25:22.37#ibcon#read 6, iclass 7, count 0 2006.203.08:25:22.37#ibcon#end of sib2, iclass 7, count 0 2006.203.08:25:22.37#ibcon#*mode == 0, iclass 7, count 0 2006.203.08:25:22.37#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.203.08:25:22.37#ibcon#[28=FRQ=03,656.99\r\n] 2006.203.08:25:22.37#ibcon#*before write, iclass 7, count 0 2006.203.08:25:22.37#ibcon#enter sib2, iclass 7, count 0 2006.203.08:25:22.37#ibcon#flushed, iclass 7, count 0 2006.203.08:25:22.37#ibcon#about to write, iclass 7, count 0 2006.203.08:25:22.37#ibcon#wrote, iclass 7, count 0 2006.203.08:25:22.37#ibcon#about to read 3, iclass 7, count 0 2006.203.08:25:22.41#ibcon#read 3, iclass 7, count 0 2006.203.08:25:22.41#ibcon#about to read 4, iclass 7, count 0 2006.203.08:25:22.41#ibcon#read 4, iclass 7, count 0 2006.203.08:25:22.41#ibcon#about to read 5, iclass 7, count 0 2006.203.08:25:22.41#ibcon#read 5, iclass 7, count 0 2006.203.08:25:22.41#ibcon#about to read 6, iclass 7, count 0 2006.203.08:25:22.41#ibcon#read 6, iclass 7, count 0 2006.203.08:25:22.41#ibcon#end of sib2, iclass 7, count 0 2006.203.08:25:22.41#ibcon#*after write, iclass 7, count 0 2006.203.08:25:22.41#ibcon#*before return 0, iclass 7, count 0 2006.203.08:25:22.41#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.203.08:25:22.41#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.203.08:25:22.41#ibcon#about to clear, iclass 7 cls_cnt 0 2006.203.08:25:22.41#ibcon#cleared, iclass 7 cls_cnt 0 2006.203.08:25:22.41$vc4f8/vb=3,4 2006.203.08:25:22.41#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.203.08:25:22.41#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.203.08:25:22.41#ibcon#ireg 11 cls_cnt 2 2006.203.08:25:22.41#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.203.08:25:22.47#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.203.08:25:22.47#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.203.08:25:22.47#ibcon#enter wrdev, iclass 11, count 2 2006.203.08:25:22.47#ibcon#first serial, iclass 11, count 2 2006.203.08:25:22.47#ibcon#enter sib2, iclass 11, count 2 2006.203.08:25:22.47#ibcon#flushed, iclass 11, count 2 2006.203.08:25:22.47#ibcon#about to write, iclass 11, count 2 2006.203.08:25:22.47#ibcon#wrote, iclass 11, count 2 2006.203.08:25:22.47#ibcon#about to read 3, iclass 11, count 2 2006.203.08:25:22.49#ibcon#read 3, iclass 11, count 2 2006.203.08:25:22.49#ibcon#about to read 4, iclass 11, count 2 2006.203.08:25:22.49#ibcon#read 4, iclass 11, count 2 2006.203.08:25:22.49#ibcon#about to read 5, iclass 11, count 2 2006.203.08:25:22.49#ibcon#read 5, iclass 11, count 2 2006.203.08:25:22.49#ibcon#about to read 6, iclass 11, count 2 2006.203.08:25:22.49#ibcon#read 6, iclass 11, count 2 2006.203.08:25:22.49#ibcon#end of sib2, iclass 11, count 2 2006.203.08:25:22.49#ibcon#*mode == 0, iclass 11, count 2 2006.203.08:25:22.49#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.203.08:25:22.49#ibcon#[27=AT03-04\r\n] 2006.203.08:25:22.49#ibcon#*before write, iclass 11, count 2 2006.203.08:25:22.49#ibcon#enter sib2, iclass 11, count 2 2006.203.08:25:22.49#ibcon#flushed, iclass 11, count 2 2006.203.08:25:22.49#ibcon#about to write, iclass 11, count 2 2006.203.08:25:22.49#ibcon#wrote, iclass 11, count 2 2006.203.08:25:22.49#ibcon#about to read 3, iclass 11, count 2 2006.203.08:25:22.52#ibcon#read 3, iclass 11, count 2 2006.203.08:25:22.52#ibcon#about to read 4, iclass 11, count 2 2006.203.08:25:22.52#ibcon#read 4, iclass 11, count 2 2006.203.08:25:22.52#ibcon#about to read 5, iclass 11, count 2 2006.203.08:25:22.52#ibcon#read 5, iclass 11, count 2 2006.203.08:25:22.52#ibcon#about to read 6, iclass 11, count 2 2006.203.08:25:22.52#ibcon#read 6, iclass 11, count 2 2006.203.08:25:22.52#ibcon#end of sib2, iclass 11, count 2 2006.203.08:25:22.52#ibcon#*after write, iclass 11, count 2 2006.203.08:25:22.52#ibcon#*before return 0, iclass 11, count 2 2006.203.08:25:22.52#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.203.08:25:22.52#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.203.08:25:22.52#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.203.08:25:22.52#ibcon#ireg 7 cls_cnt 0 2006.203.08:25:22.52#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.203.08:25:22.64#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.203.08:25:22.64#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.203.08:25:22.64#ibcon#enter wrdev, iclass 11, count 0 2006.203.08:25:22.64#ibcon#first serial, iclass 11, count 0 2006.203.08:25:22.64#ibcon#enter sib2, iclass 11, count 0 2006.203.08:25:22.64#ibcon#flushed, iclass 11, count 0 2006.203.08:25:22.64#ibcon#about to write, iclass 11, count 0 2006.203.08:25:22.64#ibcon#wrote, iclass 11, count 0 2006.203.08:25:22.64#ibcon#about to read 3, iclass 11, count 0 2006.203.08:25:22.66#ibcon#read 3, iclass 11, count 0 2006.203.08:25:22.66#ibcon#about to read 4, iclass 11, count 0 2006.203.08:25:22.66#ibcon#read 4, iclass 11, count 0 2006.203.08:25:22.66#ibcon#about to read 5, iclass 11, count 0 2006.203.08:25:22.66#ibcon#read 5, iclass 11, count 0 2006.203.08:25:22.66#ibcon#about to read 6, iclass 11, count 0 2006.203.08:25:22.66#ibcon#read 6, iclass 11, count 0 2006.203.08:25:22.66#ibcon#end of sib2, iclass 11, count 0 2006.203.08:25:22.66#ibcon#*mode == 0, iclass 11, count 0 2006.203.08:25:22.66#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.203.08:25:22.66#ibcon#[27=USB\r\n] 2006.203.08:25:22.66#ibcon#*before write, iclass 11, count 0 2006.203.08:25:22.66#ibcon#enter sib2, iclass 11, count 0 2006.203.08:25:22.66#ibcon#flushed, iclass 11, count 0 2006.203.08:25:22.66#ibcon#about to write, iclass 11, count 0 2006.203.08:25:22.66#ibcon#wrote, iclass 11, count 0 2006.203.08:25:22.66#ibcon#about to read 3, iclass 11, count 0 2006.203.08:25:22.69#ibcon#read 3, iclass 11, count 0 2006.203.08:25:22.69#ibcon#about to read 4, iclass 11, count 0 2006.203.08:25:22.69#ibcon#read 4, iclass 11, count 0 2006.203.08:25:22.69#ibcon#about to read 5, iclass 11, count 0 2006.203.08:25:22.69#ibcon#read 5, iclass 11, count 0 2006.203.08:25:22.69#ibcon#about to read 6, iclass 11, count 0 2006.203.08:25:22.69#ibcon#read 6, iclass 11, count 0 2006.203.08:25:22.69#ibcon#end of sib2, iclass 11, count 0 2006.203.08:25:22.69#ibcon#*after write, iclass 11, count 0 2006.203.08:25:22.69#ibcon#*before return 0, iclass 11, count 0 2006.203.08:25:22.69#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.203.08:25:22.69#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.203.08:25:22.69#ibcon#about to clear, iclass 11 cls_cnt 0 2006.203.08:25:22.69#ibcon#cleared, iclass 11 cls_cnt 0 2006.203.08:25:22.69$vc4f8/vblo=4,712.99 2006.203.08:25:22.69#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.203.08:25:22.69#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.203.08:25:22.69#ibcon#ireg 17 cls_cnt 0 2006.203.08:25:22.69#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.203.08:25:22.69#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.203.08:25:22.69#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.203.08:25:22.69#ibcon#enter wrdev, iclass 13, count 0 2006.203.08:25:22.69#ibcon#first serial, iclass 13, count 0 2006.203.08:25:22.69#ibcon#enter sib2, iclass 13, count 0 2006.203.08:25:22.69#ibcon#flushed, iclass 13, count 0 2006.203.08:25:22.69#ibcon#about to write, iclass 13, count 0 2006.203.08:25:22.69#ibcon#wrote, iclass 13, count 0 2006.203.08:25:22.69#ibcon#about to read 3, iclass 13, count 0 2006.203.08:25:22.71#ibcon#read 3, iclass 13, count 0 2006.203.08:25:22.71#ibcon#about to read 4, iclass 13, count 0 2006.203.08:25:22.71#ibcon#read 4, iclass 13, count 0 2006.203.08:25:22.71#ibcon#about to read 5, iclass 13, count 0 2006.203.08:25:22.71#ibcon#read 5, iclass 13, count 0 2006.203.08:25:22.71#ibcon#about to read 6, iclass 13, count 0 2006.203.08:25:22.71#ibcon#read 6, iclass 13, count 0 2006.203.08:25:22.71#ibcon#end of sib2, iclass 13, count 0 2006.203.08:25:22.71#ibcon#*mode == 0, iclass 13, count 0 2006.203.08:25:22.71#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.203.08:25:22.71#ibcon#[28=FRQ=04,712.99\r\n] 2006.203.08:25:22.71#ibcon#*before write, iclass 13, count 0 2006.203.08:25:22.71#ibcon#enter sib2, iclass 13, count 0 2006.203.08:25:22.71#ibcon#flushed, iclass 13, count 0 2006.203.08:25:22.71#ibcon#about to write, iclass 13, count 0 2006.203.08:25:22.71#ibcon#wrote, iclass 13, count 0 2006.203.08:25:22.71#ibcon#about to read 3, iclass 13, count 0 2006.203.08:25:22.75#ibcon#read 3, iclass 13, count 0 2006.203.08:25:22.75#ibcon#about to read 4, iclass 13, count 0 2006.203.08:25:22.75#ibcon#read 4, iclass 13, count 0 2006.203.08:25:22.75#ibcon#about to read 5, iclass 13, count 0 2006.203.08:25:22.75#ibcon#read 5, iclass 13, count 0 2006.203.08:25:22.75#ibcon#about to read 6, iclass 13, count 0 2006.203.08:25:22.75#ibcon#read 6, iclass 13, count 0 2006.203.08:25:22.75#ibcon#end of sib2, iclass 13, count 0 2006.203.08:25:22.75#ibcon#*after write, iclass 13, count 0 2006.203.08:25:22.75#ibcon#*before return 0, iclass 13, count 0 2006.203.08:25:22.75#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.203.08:25:22.75#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.203.08:25:22.75#ibcon#about to clear, iclass 13 cls_cnt 0 2006.203.08:25:22.75#ibcon#cleared, iclass 13 cls_cnt 0 2006.203.08:25:22.75$vc4f8/vb=4,4 2006.203.08:25:22.75#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.203.08:25:22.75#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.203.08:25:22.75#ibcon#ireg 11 cls_cnt 2 2006.203.08:25:22.75#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.203.08:25:22.81#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.203.08:25:22.81#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.203.08:25:22.81#ibcon#enter wrdev, iclass 15, count 2 2006.203.08:25:22.81#ibcon#first serial, iclass 15, count 2 2006.203.08:25:22.81#ibcon#enter sib2, iclass 15, count 2 2006.203.08:25:22.81#ibcon#flushed, iclass 15, count 2 2006.203.08:25:22.81#ibcon#about to write, iclass 15, count 2 2006.203.08:25:22.81#ibcon#wrote, iclass 15, count 2 2006.203.08:25:22.81#ibcon#about to read 3, iclass 15, count 2 2006.203.08:25:22.83#ibcon#read 3, iclass 15, count 2 2006.203.08:25:22.83#ibcon#about to read 4, iclass 15, count 2 2006.203.08:25:22.83#ibcon#read 4, iclass 15, count 2 2006.203.08:25:22.83#ibcon#about to read 5, iclass 15, count 2 2006.203.08:25:22.83#ibcon#read 5, iclass 15, count 2 2006.203.08:25:22.83#ibcon#about to read 6, iclass 15, count 2 2006.203.08:25:22.83#ibcon#read 6, iclass 15, count 2 2006.203.08:25:22.83#ibcon#end of sib2, iclass 15, count 2 2006.203.08:25:22.83#ibcon#*mode == 0, iclass 15, count 2 2006.203.08:25:22.83#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.203.08:25:22.83#ibcon#[27=AT04-04\r\n] 2006.203.08:25:22.83#ibcon#*before write, iclass 15, count 2 2006.203.08:25:22.83#ibcon#enter sib2, iclass 15, count 2 2006.203.08:25:22.83#ibcon#flushed, iclass 15, count 2 2006.203.08:25:22.83#ibcon#about to write, iclass 15, count 2 2006.203.08:25:22.83#ibcon#wrote, iclass 15, count 2 2006.203.08:25:22.83#ibcon#about to read 3, iclass 15, count 2 2006.203.08:25:22.86#ibcon#read 3, iclass 15, count 2 2006.203.08:25:22.86#ibcon#about to read 4, iclass 15, count 2 2006.203.08:25:22.86#ibcon#read 4, iclass 15, count 2 2006.203.08:25:22.86#ibcon#about to read 5, iclass 15, count 2 2006.203.08:25:22.86#ibcon#read 5, iclass 15, count 2 2006.203.08:25:22.86#ibcon#about to read 6, iclass 15, count 2 2006.203.08:25:22.86#ibcon#read 6, iclass 15, count 2 2006.203.08:25:22.86#ibcon#end of sib2, iclass 15, count 2 2006.203.08:25:22.86#ibcon#*after write, iclass 15, count 2 2006.203.08:25:22.86#ibcon#*before return 0, iclass 15, count 2 2006.203.08:25:22.86#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.203.08:25:22.86#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.203.08:25:22.86#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.203.08:25:22.86#ibcon#ireg 7 cls_cnt 0 2006.203.08:25:22.86#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.203.08:25:22.98#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.203.08:25:22.98#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.203.08:25:22.98#ibcon#enter wrdev, iclass 15, count 0 2006.203.08:25:22.98#ibcon#first serial, iclass 15, count 0 2006.203.08:25:22.98#ibcon#enter sib2, iclass 15, count 0 2006.203.08:25:22.98#ibcon#flushed, iclass 15, count 0 2006.203.08:25:22.98#ibcon#about to write, iclass 15, count 0 2006.203.08:25:22.98#ibcon#wrote, iclass 15, count 0 2006.203.08:25:22.98#ibcon#about to read 3, iclass 15, count 0 2006.203.08:25:23.00#ibcon#read 3, iclass 15, count 0 2006.203.08:25:23.00#ibcon#about to read 4, iclass 15, count 0 2006.203.08:25:23.00#ibcon#read 4, iclass 15, count 0 2006.203.08:25:23.00#ibcon#about to read 5, iclass 15, count 0 2006.203.08:25:23.00#ibcon#read 5, iclass 15, count 0 2006.203.08:25:23.00#ibcon#about to read 6, iclass 15, count 0 2006.203.08:25:23.00#ibcon#read 6, iclass 15, count 0 2006.203.08:25:23.00#ibcon#end of sib2, iclass 15, count 0 2006.203.08:25:23.00#ibcon#*mode == 0, iclass 15, count 0 2006.203.08:25:23.00#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.203.08:25:23.00#ibcon#[27=USB\r\n] 2006.203.08:25:23.00#ibcon#*before write, iclass 15, count 0 2006.203.08:25:23.00#ibcon#enter sib2, iclass 15, count 0 2006.203.08:25:23.00#ibcon#flushed, iclass 15, count 0 2006.203.08:25:23.00#ibcon#about to write, iclass 15, count 0 2006.203.08:25:23.00#ibcon#wrote, iclass 15, count 0 2006.203.08:25:23.00#ibcon#about to read 3, iclass 15, count 0 2006.203.08:25:23.03#ibcon#read 3, iclass 15, count 0 2006.203.08:25:23.03#ibcon#about to read 4, iclass 15, count 0 2006.203.08:25:23.03#ibcon#read 4, iclass 15, count 0 2006.203.08:25:23.03#ibcon#about to read 5, iclass 15, count 0 2006.203.08:25:23.03#ibcon#read 5, iclass 15, count 0 2006.203.08:25:23.03#ibcon#about to read 6, iclass 15, count 0 2006.203.08:25:23.03#ibcon#read 6, iclass 15, count 0 2006.203.08:25:23.03#ibcon#end of sib2, iclass 15, count 0 2006.203.08:25:23.03#ibcon#*after write, iclass 15, count 0 2006.203.08:25:23.03#ibcon#*before return 0, iclass 15, count 0 2006.203.08:25:23.03#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.203.08:25:23.03#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.203.08:25:23.03#ibcon#about to clear, iclass 15 cls_cnt 0 2006.203.08:25:23.03#ibcon#cleared, iclass 15 cls_cnt 0 2006.203.08:25:23.03$vc4f8/vblo=5,744.99 2006.203.08:25:23.03#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.203.08:25:23.03#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.203.08:25:23.03#ibcon#ireg 17 cls_cnt 0 2006.203.08:25:23.03#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.203.08:25:23.03#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.203.08:25:23.03#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.203.08:25:23.03#ibcon#enter wrdev, iclass 17, count 0 2006.203.08:25:23.03#ibcon#first serial, iclass 17, count 0 2006.203.08:25:23.03#ibcon#enter sib2, iclass 17, count 0 2006.203.08:25:23.03#ibcon#flushed, iclass 17, count 0 2006.203.08:25:23.03#ibcon#about to write, iclass 17, count 0 2006.203.08:25:23.03#ibcon#wrote, iclass 17, count 0 2006.203.08:25:23.03#ibcon#about to read 3, iclass 17, count 0 2006.203.08:25:23.05#ibcon#read 3, iclass 17, count 0 2006.203.08:25:23.05#ibcon#about to read 4, iclass 17, count 0 2006.203.08:25:23.05#ibcon#read 4, iclass 17, count 0 2006.203.08:25:23.05#ibcon#about to read 5, iclass 17, count 0 2006.203.08:25:23.05#ibcon#read 5, iclass 17, count 0 2006.203.08:25:23.05#ibcon#about to read 6, iclass 17, count 0 2006.203.08:25:23.05#ibcon#read 6, iclass 17, count 0 2006.203.08:25:23.05#ibcon#end of sib2, iclass 17, count 0 2006.203.08:25:23.05#ibcon#*mode == 0, iclass 17, count 0 2006.203.08:25:23.05#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.203.08:25:23.05#ibcon#[28=FRQ=05,744.99\r\n] 2006.203.08:25:23.05#ibcon#*before write, iclass 17, count 0 2006.203.08:25:23.05#ibcon#enter sib2, iclass 17, count 0 2006.203.08:25:23.05#ibcon#flushed, iclass 17, count 0 2006.203.08:25:23.05#ibcon#about to write, iclass 17, count 0 2006.203.08:25:23.05#ibcon#wrote, iclass 17, count 0 2006.203.08:25:23.05#ibcon#about to read 3, iclass 17, count 0 2006.203.08:25:23.09#ibcon#read 3, iclass 17, count 0 2006.203.08:25:23.09#ibcon#about to read 4, iclass 17, count 0 2006.203.08:25:23.09#ibcon#read 4, iclass 17, count 0 2006.203.08:25:23.09#ibcon#about to read 5, iclass 17, count 0 2006.203.08:25:23.09#ibcon#read 5, iclass 17, count 0 2006.203.08:25:23.09#ibcon#about to read 6, iclass 17, count 0 2006.203.08:25:23.09#ibcon#read 6, iclass 17, count 0 2006.203.08:25:23.09#ibcon#end of sib2, iclass 17, count 0 2006.203.08:25:23.09#ibcon#*after write, iclass 17, count 0 2006.203.08:25:23.09#ibcon#*before return 0, iclass 17, count 0 2006.203.08:25:23.09#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.203.08:25:23.09#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.203.08:25:23.09#ibcon#about to clear, iclass 17 cls_cnt 0 2006.203.08:25:23.09#ibcon#cleared, iclass 17 cls_cnt 0 2006.203.08:25:23.09$vc4f8/vb=5,3 2006.203.08:25:23.09#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.203.08:25:23.09#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.203.08:25:23.09#ibcon#ireg 11 cls_cnt 2 2006.203.08:25:23.09#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.203.08:25:23.15#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.203.08:25:23.15#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.203.08:25:23.15#ibcon#enter wrdev, iclass 19, count 2 2006.203.08:25:23.15#ibcon#first serial, iclass 19, count 2 2006.203.08:25:23.15#ibcon#enter sib2, iclass 19, count 2 2006.203.08:25:23.15#ibcon#flushed, iclass 19, count 2 2006.203.08:25:23.15#ibcon#about to write, iclass 19, count 2 2006.203.08:25:23.15#ibcon#wrote, iclass 19, count 2 2006.203.08:25:23.15#ibcon#about to read 3, iclass 19, count 2 2006.203.08:25:23.17#ibcon#read 3, iclass 19, count 2 2006.203.08:25:23.17#ibcon#about to read 4, iclass 19, count 2 2006.203.08:25:23.17#ibcon#read 4, iclass 19, count 2 2006.203.08:25:23.17#ibcon#about to read 5, iclass 19, count 2 2006.203.08:25:23.17#ibcon#read 5, iclass 19, count 2 2006.203.08:25:23.17#ibcon#about to read 6, iclass 19, count 2 2006.203.08:25:23.17#ibcon#read 6, iclass 19, count 2 2006.203.08:25:23.17#ibcon#end of sib2, iclass 19, count 2 2006.203.08:25:23.17#ibcon#*mode == 0, iclass 19, count 2 2006.203.08:25:23.17#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.203.08:25:23.17#ibcon#[27=AT05-03\r\n] 2006.203.08:25:23.17#ibcon#*before write, iclass 19, count 2 2006.203.08:25:23.17#ibcon#enter sib2, iclass 19, count 2 2006.203.08:25:23.17#ibcon#flushed, iclass 19, count 2 2006.203.08:25:23.17#ibcon#about to write, iclass 19, count 2 2006.203.08:25:23.17#ibcon#wrote, iclass 19, count 2 2006.203.08:25:23.17#ibcon#about to read 3, iclass 19, count 2 2006.203.08:25:23.20#ibcon#read 3, iclass 19, count 2 2006.203.08:25:23.20#ibcon#about to read 4, iclass 19, count 2 2006.203.08:25:23.20#ibcon#read 4, iclass 19, count 2 2006.203.08:25:23.20#ibcon#about to read 5, iclass 19, count 2 2006.203.08:25:23.20#ibcon#read 5, iclass 19, count 2 2006.203.08:25:23.20#ibcon#about to read 6, iclass 19, count 2 2006.203.08:25:23.20#ibcon#read 6, iclass 19, count 2 2006.203.08:25:23.20#ibcon#end of sib2, iclass 19, count 2 2006.203.08:25:23.20#ibcon#*after write, iclass 19, count 2 2006.203.08:25:23.20#ibcon#*before return 0, iclass 19, count 2 2006.203.08:25:23.20#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.203.08:25:23.20#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.203.08:25:23.20#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.203.08:25:23.20#ibcon#ireg 7 cls_cnt 0 2006.203.08:25:23.20#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.203.08:25:23.32#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.203.08:25:23.32#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.203.08:25:23.32#ibcon#enter wrdev, iclass 19, count 0 2006.203.08:25:23.32#ibcon#first serial, iclass 19, count 0 2006.203.08:25:23.32#ibcon#enter sib2, iclass 19, count 0 2006.203.08:25:23.32#ibcon#flushed, iclass 19, count 0 2006.203.08:25:23.32#ibcon#about to write, iclass 19, count 0 2006.203.08:25:23.32#ibcon#wrote, iclass 19, count 0 2006.203.08:25:23.32#ibcon#about to read 3, iclass 19, count 0 2006.203.08:25:23.34#ibcon#read 3, iclass 19, count 0 2006.203.08:25:23.34#ibcon#about to read 4, iclass 19, count 0 2006.203.08:25:23.34#ibcon#read 4, iclass 19, count 0 2006.203.08:25:23.34#ibcon#about to read 5, iclass 19, count 0 2006.203.08:25:23.34#ibcon#read 5, iclass 19, count 0 2006.203.08:25:23.34#ibcon#about to read 6, iclass 19, count 0 2006.203.08:25:23.34#ibcon#read 6, iclass 19, count 0 2006.203.08:25:23.34#ibcon#end of sib2, iclass 19, count 0 2006.203.08:25:23.34#ibcon#*mode == 0, iclass 19, count 0 2006.203.08:25:23.34#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.203.08:25:23.34#ibcon#[27=USB\r\n] 2006.203.08:25:23.34#ibcon#*before write, iclass 19, count 0 2006.203.08:25:23.34#ibcon#enter sib2, iclass 19, count 0 2006.203.08:25:23.34#ibcon#flushed, iclass 19, count 0 2006.203.08:25:23.34#ibcon#about to write, iclass 19, count 0 2006.203.08:25:23.34#ibcon#wrote, iclass 19, count 0 2006.203.08:25:23.34#ibcon#about to read 3, iclass 19, count 0 2006.203.08:25:23.37#ibcon#read 3, iclass 19, count 0 2006.203.08:25:23.37#ibcon#about to read 4, iclass 19, count 0 2006.203.08:25:23.37#ibcon#read 4, iclass 19, count 0 2006.203.08:25:23.37#ibcon#about to read 5, iclass 19, count 0 2006.203.08:25:23.37#ibcon#read 5, iclass 19, count 0 2006.203.08:25:23.37#ibcon#about to read 6, iclass 19, count 0 2006.203.08:25:23.37#ibcon#read 6, iclass 19, count 0 2006.203.08:25:23.37#ibcon#end of sib2, iclass 19, count 0 2006.203.08:25:23.37#ibcon#*after write, iclass 19, count 0 2006.203.08:25:23.37#ibcon#*before return 0, iclass 19, count 0 2006.203.08:25:23.37#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.203.08:25:23.37#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.203.08:25:23.37#ibcon#about to clear, iclass 19 cls_cnt 0 2006.203.08:25:23.37#ibcon#cleared, iclass 19 cls_cnt 0 2006.203.08:25:23.37$vc4f8/vblo=6,752.99 2006.203.08:25:23.37#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.203.08:25:23.37#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.203.08:25:23.37#ibcon#ireg 17 cls_cnt 0 2006.203.08:25:23.37#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.203.08:25:23.37#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.203.08:25:23.37#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.203.08:25:23.37#ibcon#enter wrdev, iclass 21, count 0 2006.203.08:25:23.37#ibcon#first serial, iclass 21, count 0 2006.203.08:25:23.37#ibcon#enter sib2, iclass 21, count 0 2006.203.08:25:23.37#ibcon#flushed, iclass 21, count 0 2006.203.08:25:23.37#ibcon#about to write, iclass 21, count 0 2006.203.08:25:23.37#ibcon#wrote, iclass 21, count 0 2006.203.08:25:23.37#ibcon#about to read 3, iclass 21, count 0 2006.203.08:25:23.39#ibcon#read 3, iclass 21, count 0 2006.203.08:25:23.39#ibcon#about to read 4, iclass 21, count 0 2006.203.08:25:23.39#ibcon#read 4, iclass 21, count 0 2006.203.08:25:23.39#ibcon#about to read 5, iclass 21, count 0 2006.203.08:25:23.39#ibcon#read 5, iclass 21, count 0 2006.203.08:25:23.39#ibcon#about to read 6, iclass 21, count 0 2006.203.08:25:23.39#ibcon#read 6, iclass 21, count 0 2006.203.08:25:23.39#ibcon#end of sib2, iclass 21, count 0 2006.203.08:25:23.39#ibcon#*mode == 0, iclass 21, count 0 2006.203.08:25:23.39#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.203.08:25:23.39#ibcon#[28=FRQ=06,752.99\r\n] 2006.203.08:25:23.39#ibcon#*before write, iclass 21, count 0 2006.203.08:25:23.39#ibcon#enter sib2, iclass 21, count 0 2006.203.08:25:23.39#ibcon#flushed, iclass 21, count 0 2006.203.08:25:23.39#ibcon#about to write, iclass 21, count 0 2006.203.08:25:23.39#ibcon#wrote, iclass 21, count 0 2006.203.08:25:23.39#ibcon#about to read 3, iclass 21, count 0 2006.203.08:25:23.43#ibcon#read 3, iclass 21, count 0 2006.203.08:25:23.43#ibcon#about to read 4, iclass 21, count 0 2006.203.08:25:23.43#ibcon#read 4, iclass 21, count 0 2006.203.08:25:23.43#ibcon#about to read 5, iclass 21, count 0 2006.203.08:25:23.43#ibcon#read 5, iclass 21, count 0 2006.203.08:25:23.43#ibcon#about to read 6, iclass 21, count 0 2006.203.08:25:23.43#ibcon#read 6, iclass 21, count 0 2006.203.08:25:23.43#ibcon#end of sib2, iclass 21, count 0 2006.203.08:25:23.43#ibcon#*after write, iclass 21, count 0 2006.203.08:25:23.43#ibcon#*before return 0, iclass 21, count 0 2006.203.08:25:23.43#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.203.08:25:23.43#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.203.08:25:23.43#ibcon#about to clear, iclass 21 cls_cnt 0 2006.203.08:25:23.43#ibcon#cleared, iclass 21 cls_cnt 0 2006.203.08:25:23.43$vc4f8/vb=6,4 2006.203.08:25:23.43#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.203.08:25:23.43#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.203.08:25:23.43#ibcon#ireg 11 cls_cnt 2 2006.203.08:25:23.43#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.203.08:25:23.49#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.203.08:25:23.49#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.203.08:25:23.49#ibcon#enter wrdev, iclass 23, count 2 2006.203.08:25:23.49#ibcon#first serial, iclass 23, count 2 2006.203.08:25:23.49#ibcon#enter sib2, iclass 23, count 2 2006.203.08:25:23.49#ibcon#flushed, iclass 23, count 2 2006.203.08:25:23.49#ibcon#about to write, iclass 23, count 2 2006.203.08:25:23.49#ibcon#wrote, iclass 23, count 2 2006.203.08:25:23.49#ibcon#about to read 3, iclass 23, count 2 2006.203.08:25:23.51#ibcon#read 3, iclass 23, count 2 2006.203.08:25:23.51#ibcon#about to read 4, iclass 23, count 2 2006.203.08:25:23.51#ibcon#read 4, iclass 23, count 2 2006.203.08:25:23.51#ibcon#about to read 5, iclass 23, count 2 2006.203.08:25:23.51#ibcon#read 5, iclass 23, count 2 2006.203.08:25:23.51#ibcon#about to read 6, iclass 23, count 2 2006.203.08:25:23.51#ibcon#read 6, iclass 23, count 2 2006.203.08:25:23.51#ibcon#end of sib2, iclass 23, count 2 2006.203.08:25:23.51#ibcon#*mode == 0, iclass 23, count 2 2006.203.08:25:23.51#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.203.08:25:23.51#ibcon#[27=AT06-04\r\n] 2006.203.08:25:23.51#ibcon#*before write, iclass 23, count 2 2006.203.08:25:23.51#ibcon#enter sib2, iclass 23, count 2 2006.203.08:25:23.51#ibcon#flushed, iclass 23, count 2 2006.203.08:25:23.51#ibcon#about to write, iclass 23, count 2 2006.203.08:25:23.51#ibcon#wrote, iclass 23, count 2 2006.203.08:25:23.51#ibcon#about to read 3, iclass 23, count 2 2006.203.08:25:23.54#ibcon#read 3, iclass 23, count 2 2006.203.08:25:23.54#ibcon#about to read 4, iclass 23, count 2 2006.203.08:25:23.54#ibcon#read 4, iclass 23, count 2 2006.203.08:25:23.54#ibcon#about to read 5, iclass 23, count 2 2006.203.08:25:23.54#ibcon#read 5, iclass 23, count 2 2006.203.08:25:23.54#ibcon#about to read 6, iclass 23, count 2 2006.203.08:25:23.54#ibcon#read 6, iclass 23, count 2 2006.203.08:25:23.54#ibcon#end of sib2, iclass 23, count 2 2006.203.08:25:23.54#ibcon#*after write, iclass 23, count 2 2006.203.08:25:23.54#ibcon#*before return 0, iclass 23, count 2 2006.203.08:25:23.54#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.203.08:25:23.54#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.203.08:25:23.54#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.203.08:25:23.54#ibcon#ireg 7 cls_cnt 0 2006.203.08:25:23.54#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.203.08:25:23.66#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.203.08:25:23.66#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.203.08:25:23.66#ibcon#enter wrdev, iclass 23, count 0 2006.203.08:25:23.66#ibcon#first serial, iclass 23, count 0 2006.203.08:25:23.66#ibcon#enter sib2, iclass 23, count 0 2006.203.08:25:23.66#ibcon#flushed, iclass 23, count 0 2006.203.08:25:23.66#ibcon#about to write, iclass 23, count 0 2006.203.08:25:23.66#ibcon#wrote, iclass 23, count 0 2006.203.08:25:23.66#ibcon#about to read 3, iclass 23, count 0 2006.203.08:25:23.68#ibcon#read 3, iclass 23, count 0 2006.203.08:25:23.68#ibcon#about to read 4, iclass 23, count 0 2006.203.08:25:23.68#ibcon#read 4, iclass 23, count 0 2006.203.08:25:23.68#ibcon#about to read 5, iclass 23, count 0 2006.203.08:25:23.68#ibcon#read 5, iclass 23, count 0 2006.203.08:25:23.68#ibcon#about to read 6, iclass 23, count 0 2006.203.08:25:23.68#ibcon#read 6, iclass 23, count 0 2006.203.08:25:23.68#ibcon#end of sib2, iclass 23, count 0 2006.203.08:25:23.68#ibcon#*mode == 0, iclass 23, count 0 2006.203.08:25:23.68#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.203.08:25:23.68#ibcon#[27=USB\r\n] 2006.203.08:25:23.68#ibcon#*before write, iclass 23, count 0 2006.203.08:25:23.68#ibcon#enter sib2, iclass 23, count 0 2006.203.08:25:23.68#ibcon#flushed, iclass 23, count 0 2006.203.08:25:23.68#ibcon#about to write, iclass 23, count 0 2006.203.08:25:23.68#ibcon#wrote, iclass 23, count 0 2006.203.08:25:23.68#ibcon#about to read 3, iclass 23, count 0 2006.203.08:25:23.71#ibcon#read 3, iclass 23, count 0 2006.203.08:25:23.71#ibcon#about to read 4, iclass 23, count 0 2006.203.08:25:23.71#ibcon#read 4, iclass 23, count 0 2006.203.08:25:23.71#ibcon#about to read 5, iclass 23, count 0 2006.203.08:25:23.71#ibcon#read 5, iclass 23, count 0 2006.203.08:25:23.71#ibcon#about to read 6, iclass 23, count 0 2006.203.08:25:23.71#ibcon#read 6, iclass 23, count 0 2006.203.08:25:23.71#ibcon#end of sib2, iclass 23, count 0 2006.203.08:25:23.71#ibcon#*after write, iclass 23, count 0 2006.203.08:25:23.71#ibcon#*before return 0, iclass 23, count 0 2006.203.08:25:23.71#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.203.08:25:23.71#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.203.08:25:23.71#ibcon#about to clear, iclass 23 cls_cnt 0 2006.203.08:25:23.71#ibcon#cleared, iclass 23 cls_cnt 0 2006.203.08:25:23.71$vc4f8/vabw=wide 2006.203.08:25:23.71#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.203.08:25:23.71#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.203.08:25:23.71#ibcon#ireg 8 cls_cnt 0 2006.203.08:25:23.71#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.203.08:25:23.71#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.203.08:25:23.71#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.203.08:25:23.71#ibcon#enter wrdev, iclass 25, count 0 2006.203.08:25:23.71#ibcon#first serial, iclass 25, count 0 2006.203.08:25:23.71#ibcon#enter sib2, iclass 25, count 0 2006.203.08:25:23.71#ibcon#flushed, iclass 25, count 0 2006.203.08:25:23.71#ibcon#about to write, iclass 25, count 0 2006.203.08:25:23.71#ibcon#wrote, iclass 25, count 0 2006.203.08:25:23.71#ibcon#about to read 3, iclass 25, count 0 2006.203.08:25:23.74#ibcon#read 3, iclass 25, count 0 2006.203.08:25:23.74#ibcon#about to read 4, iclass 25, count 0 2006.203.08:25:23.74#ibcon#read 4, iclass 25, count 0 2006.203.08:25:23.74#ibcon#about to read 5, iclass 25, count 0 2006.203.08:25:23.74#ibcon#read 5, iclass 25, count 0 2006.203.08:25:23.74#ibcon#about to read 6, iclass 25, count 0 2006.203.08:25:23.74#ibcon#read 6, iclass 25, count 0 2006.203.08:25:23.74#ibcon#end of sib2, iclass 25, count 0 2006.203.08:25:23.74#ibcon#*mode == 0, iclass 25, count 0 2006.203.08:25:23.74#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.203.08:25:23.74#ibcon#[25=BW32\r\n] 2006.203.08:25:23.74#ibcon#*before write, iclass 25, count 0 2006.203.08:25:23.74#ibcon#enter sib2, iclass 25, count 0 2006.203.08:25:23.74#ibcon#flushed, iclass 25, count 0 2006.203.08:25:23.74#ibcon#about to write, iclass 25, count 0 2006.203.08:25:23.74#ibcon#wrote, iclass 25, count 0 2006.203.08:25:23.74#ibcon#about to read 3, iclass 25, count 0 2006.203.08:25:23.77#ibcon#read 3, iclass 25, count 0 2006.203.08:25:23.77#ibcon#about to read 4, iclass 25, count 0 2006.203.08:25:23.77#ibcon#read 4, iclass 25, count 0 2006.203.08:25:23.77#ibcon#about to read 5, iclass 25, count 0 2006.203.08:25:23.77#ibcon#read 5, iclass 25, count 0 2006.203.08:25:23.77#ibcon#about to read 6, iclass 25, count 0 2006.203.08:25:23.77#ibcon#read 6, iclass 25, count 0 2006.203.08:25:23.77#ibcon#end of sib2, iclass 25, count 0 2006.203.08:25:23.77#ibcon#*after write, iclass 25, count 0 2006.203.08:25:23.77#ibcon#*before return 0, iclass 25, count 0 2006.203.08:25:23.77#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.203.08:25:23.77#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.203.08:25:23.77#ibcon#about to clear, iclass 25 cls_cnt 0 2006.203.08:25:23.77#ibcon#cleared, iclass 25 cls_cnt 0 2006.203.08:25:23.77$vc4f8/vbbw=wide 2006.203.08:25:23.77#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.203.08:25:23.77#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.203.08:25:23.77#ibcon#ireg 8 cls_cnt 0 2006.203.08:25:23.77#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.203.08:25:23.83#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.203.08:25:23.83#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.203.08:25:23.83#ibcon#enter wrdev, iclass 27, count 0 2006.203.08:25:23.83#ibcon#first serial, iclass 27, count 0 2006.203.08:25:23.83#ibcon#enter sib2, iclass 27, count 0 2006.203.08:25:23.83#ibcon#flushed, iclass 27, count 0 2006.203.08:25:23.83#ibcon#about to write, iclass 27, count 0 2006.203.08:25:23.83#ibcon#wrote, iclass 27, count 0 2006.203.08:25:23.83#ibcon#about to read 3, iclass 27, count 0 2006.203.08:25:23.85#ibcon#read 3, iclass 27, count 0 2006.203.08:25:23.85#ibcon#about to read 4, iclass 27, count 0 2006.203.08:25:23.85#ibcon#read 4, iclass 27, count 0 2006.203.08:25:23.85#ibcon#about to read 5, iclass 27, count 0 2006.203.08:25:23.85#ibcon#read 5, iclass 27, count 0 2006.203.08:25:23.85#ibcon#about to read 6, iclass 27, count 0 2006.203.08:25:23.85#ibcon#read 6, iclass 27, count 0 2006.203.08:25:23.85#ibcon#end of sib2, iclass 27, count 0 2006.203.08:25:23.85#ibcon#*mode == 0, iclass 27, count 0 2006.203.08:25:23.85#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.203.08:25:23.85#ibcon#[27=BW32\r\n] 2006.203.08:25:23.85#ibcon#*before write, iclass 27, count 0 2006.203.08:25:23.85#ibcon#enter sib2, iclass 27, count 0 2006.203.08:25:23.85#ibcon#flushed, iclass 27, count 0 2006.203.08:25:23.85#ibcon#about to write, iclass 27, count 0 2006.203.08:25:23.85#ibcon#wrote, iclass 27, count 0 2006.203.08:25:23.85#ibcon#about to read 3, iclass 27, count 0 2006.203.08:25:23.88#ibcon#read 3, iclass 27, count 0 2006.203.08:25:23.88#ibcon#about to read 4, iclass 27, count 0 2006.203.08:25:23.88#ibcon#read 4, iclass 27, count 0 2006.203.08:25:23.88#ibcon#about to read 5, iclass 27, count 0 2006.203.08:25:23.88#ibcon#read 5, iclass 27, count 0 2006.203.08:25:23.88#ibcon#about to read 6, iclass 27, count 0 2006.203.08:25:23.88#ibcon#read 6, iclass 27, count 0 2006.203.08:25:23.88#ibcon#end of sib2, iclass 27, count 0 2006.203.08:25:23.88#ibcon#*after write, iclass 27, count 0 2006.203.08:25:23.88#ibcon#*before return 0, iclass 27, count 0 2006.203.08:25:23.88#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.203.08:25:23.88#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.203.08:25:23.88#ibcon#about to clear, iclass 27 cls_cnt 0 2006.203.08:25:23.88#ibcon#cleared, iclass 27 cls_cnt 0 2006.203.08:25:23.88$4f8m12a/ifd4f 2006.203.08:25:23.88$ifd4f/lo= 2006.203.08:25:23.88$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.203.08:25:23.88$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.203.08:25:23.88$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.203.08:25:23.88$ifd4f/patch= 2006.203.08:25:23.88$ifd4f/patch=lo1,a1,a2,a3,a4 2006.203.08:25:23.88$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.203.08:25:23.88$ifd4f/patch=lo3,a5,a6,a7,a8 2006.203.08:25:23.88$4f8m12a/"form=m,16.000,1:2 2006.203.08:25:23.88$4f8m12a/"tpicd 2006.203.08:25:23.88$4f8m12a/echo=off 2006.203.08:25:23.88$4f8m12a/xlog=off 2006.203.08:25:23.88:!2006.203.08:26:00 2006.203.08:25:43.14#trakl#Source acquired 2006.203.08:25:43.14#flagr#flagr/antenna,acquired 2006.203.08:26:00.00:preob 2006.203.08:26:00.14/onsource/TRACKING 2006.203.08:26:00.14:!2006.203.08:26:10 2006.203.08:26:10.00:data_valid=on 2006.203.08:26:10.00:midob 2006.203.08:26:10.14/onsource/TRACKING 2006.203.08:26:10.14/wx/23.53,1001.3,99 2006.203.08:26:10.22/cable/+6.4595E-03 2006.203.08:26:11.31/va/01,08,usb,yes,30,32 2006.203.08:26:11.31/va/02,07,usb,yes,30,31 2006.203.08:26:11.31/va/03,08,usb,yes,22,23 2006.203.08:26:11.31/va/04,07,usb,yes,31,33 2006.203.08:26:11.31/va/05,07,usb,yes,33,35 2006.203.08:26:11.31/va/06,06,usb,yes,33,32 2006.203.08:26:11.31/va/07,07,usb,yes,29,29 2006.203.08:26:11.31/va/08,06,usb,yes,35,35 2006.203.08:26:11.54/valo/01,532.99,yes,locked 2006.203.08:26:11.54/valo/02,572.99,yes,locked 2006.203.08:26:11.54/valo/03,672.99,yes,locked 2006.203.08:26:11.54/valo/04,832.99,yes,locked 2006.203.08:26:11.54/valo/05,652.99,yes,locked 2006.203.08:26:11.54/valo/06,772.99,yes,locked 2006.203.08:26:11.54/valo/07,832.99,yes,locked 2006.203.08:26:11.54/valo/08,852.99,yes,locked 2006.203.08:26:12.63/vb/01,04,usb,yes,29,28 2006.203.08:26:12.63/vb/02,04,usb,yes,31,32 2006.203.08:26:12.63/vb/03,04,usb,yes,27,31 2006.203.08:26:12.63/vb/04,04,usb,yes,28,28 2006.203.08:26:12.63/vb/05,03,usb,yes,34,38 2006.203.08:26:12.63/vb/06,04,usb,yes,28,30 2006.203.08:26:12.63/vb/07,04,usb,yes,30,30 2006.203.08:26:12.63/vb/08,04,usb,yes,27,31 2006.203.08:26:12.87/vblo/01,632.99,yes,locked 2006.203.08:26:12.87/vblo/02,640.99,yes,locked 2006.203.08:26:12.87/vblo/03,656.99,yes,locked 2006.203.08:26:12.87/vblo/04,712.99,yes,locked 2006.203.08:26:12.87/vblo/05,744.99,yes,locked 2006.203.08:26:12.87/vblo/06,752.99,yes,locked 2006.203.08:26:12.87/vblo/07,734.99,yes,locked 2006.203.08:26:12.87/vblo/08,744.99,yes,locked 2006.203.08:26:13.02/vabw/8 2006.203.08:26:13.17/vbbw/8 2006.203.08:26:13.26/xfe/off,on,12.7 2006.203.08:26:13.65/ifatt/23,28,28,28 2006.203.08:26:14.08/fmout-gps/S +4.57E-07 2006.203.08:26:14.12:!2006.203.08:27:10 2006.203.08:27:10.00:data_valid=off 2006.203.08:27:10.01:postob 2006.203.08:27:10.18/cable/+6.4600E-03 2006.203.08:27:10.18/wx/23.52,1001.3,99 2006.203.08:27:11.07/fmout-gps/S +4.57E-07 2006.203.08:27:11.08:checkk5last 2006.203.08:27:11.08&checkk5last/chk_obsdata=1 2006.203.08:27:11.08&checkk5last/chk_obsdata=2 2006.203.08:27:11.08&checkk5last/chk_obsdata=3 2006.203.08:27:11.08&checkk5last/chk_obsdata=4 2006.203.08:27:11.08&checkk5last/k5log=1 2006.203.08:27:11.08&checkk5last/k5log=2 2006.203.08:27:11.08&checkk5last/k5log=3 2006.203.08:27:11.08&checkk5last/k5log=4 2006.203.08:27:11.08&checkk5last/obsinfo 2006.203.08:27:11.63/chk_obsdata//k5ts1/T2030826??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.08:27:12.05/chk_obsdata//k5ts2/T2030826??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.08:27:12.46/chk_obsdata//k5ts3/T2030826??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.08:27:12.89/chk_obsdata//k5ts4/T2030826??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.203.08:27:13.91/k5log//k5ts1_log_newline 2006.203.08:27:15.40/k5log//k5ts2_log_newline 2006.203.08:27:16.31/k5log//k5ts3_log_newline 2006.203.08:27:17.61/k5log//k5ts4_log_newline 2006.203.08:27:17.63/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.203.08:27:17.63:"sched_end 2006.203.08:27:17.63:source=idle 2006.203.08:27:19.14:stow 2006.203.08:27:19.14&stow/source=idle 2006.203.08:27:19.14&stow/"this is stow command. 2006.203.08:27:19.14&stow/antenna=m3 2006.203.08:27:19.14#flagr#flagr/antenna,new-source 2006.203.08:27:22.01:!+10m 2006.203.08:37:22.02:standby 2006.203.08:37:22.02&standby/"this is standby command. 2006.203.08:37:22.02&standby/antenna=m0 2006.203.08:37:23.01:checkk5hdd 2006.203.08:37:23.01&checkk5hdd/chk_hdd=1 2006.203.08:37:23.01&checkk5hdd/chk_hdd=2 2006.203.08:37:23.01&checkk5hdd/chk_hdd=3 2006.203.08:37:23.01&checkk5hdd/chk_hdd=4 2006.203.08:37:26.12/chk_hdd//k5ts1/GSI00275:T203073000a.dat~T203082610a.dat[12785483776Byte] 2006.203.08:37:29.54/chk_hdd//k5ts2/GSI00290:T203073000b.dat~T203082610b.dat[12785483776Byte] 2006.203.08:37:33.45/chk_hdd//k5ts3/GSI00278:T203073000c.dat~T203082610c.dat[12785483776Byte] 2006.203.08:37:36.81/chk_hdd//k5ts4/GSI00220:T203073000d.dat~T203082610d.dat[12785483776Byte] 2006.203.08:37:36.81:sy=cp /usr2/log/k06203ts.log /usr2/log_backup/ 2006.203.08:37:36.91:log=k06204ts