2006.196.08:43:20.09:Log Opened: Mark IV Field System Version 9.7.7 2006.196.08:43:20.10:location,TSUKUB32,-140.09,36.10,61.0 2006.196.08:43:20.10:horizon1,0.,5.,360. 2006.196.08:43:20.10:antenna,32.0,180.0,180.0,10.0,710.0,5.0,88.0,azel 2006.196.08:43:20.11:equip,k42c/mk4,vlbab,vlbab,mk4,500.10,3,a/d,101,60,20,none,41,1,in,8bit,cdp,3 2006.196.08:43:20.11:drivev11,330,270,no 2006.196.08:43:20.11:drivev12,mvme117,0,11.400,2548.000,152.780,-6.655,0.014,152,10.000,54500 2006.196.08:43:20.11:drivev13,15.000,268,10.000,10.000,10.000 2006.196.08:43:20.11:drivev21,330,270,no 2006.196.08:43:20.11:drivev22,mvme117,0,11.500,2821.000,127.500,-8.640,0.015,152,14.000,54500 2006.196.08:43:20.11:drivev23,15.000,268,10.000,10.000,10.000 2006.196.08:43:20.11:head10,all,all,all,odd,adaptive,no,5.0000,1 2006.196.08:43:20.11:head11,131.5,16.4,-291.0,131.5,16.4,0.8,168.30,168.30 2006.196.08:43:20.11:head12,122.8,13.9,-150.8,122.8,14.7,2.5,167.61,167.61 2006.196.08:43:20.11:head20,all,all,all,odd,adaptive,no,5.0000,1 2006.196.08:43:20.11:head21,145.3,16.1,-209.3,137.2,16.1,58.9,165.28,165.28 2006.196.08:43:20.11:head22,157.5,17.4,-203.7,149.2,16.6,56.5,169.73,169.73 2006.196.08:43:20.11:time,-0.364,101.533,rate 2006.196.08:43:20.11:flagr,200 2006.196.08:43:20.11:proc=k06197ts 2006.196.08:43:20.11:" k06197 2006 tsukub32 t ts 2006.196.08:43:20.11:" t tsukub32 azel .0000 180.0 14 10.0 710.0 180.0 14 5.0 88.0 32.0 ts 108 2006.196.08:43:20.11:" ts tsukub32 -3957408.75120 3310229.34660 3737494.83600 73452301 2006.196.08:43:20.11:" 108 tsukub32 14 17400 2006.196.08:43:20.11:" drudg version 050216 compiled under fs 9.7.07 2006.196.08:43:20.11:" rack=k4-2/m4 recorder 1=k5 recorder 2=none 2006.196.08:43:20.11:!2006.197.06:29:50 2006.197.06:29:50.00:sy=/usr2/oper/k5/bin/freeze_chk.pl & 2006.197.06:29:50.02:!2006.197.07:19:50 2006.197.07:19:50.00:unstow 2006.197.07:19:50.00&unstow/antenna=e 2006.197.07:19:50.00&unstow/!+10s 2006.197.07:19:50.00&unstow/antenna=m2 2006.197.07:20:02.01:scan_name=197-0730,k06197,60 2006.197.07:20:02.01:source=3c418,203837.03,511912.7,2000.0,ccw 2006.197.07:20:02.01#antcn#PM 1 00019 2005 228 00 22 31 00 2006.197.07:20:02.01#antcn#PM 2 90.0000 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 2006.197.07:20:02.01#antcn#PM 2 -0.0279715 0.0000000 -0.0282214 -0.0241630 -0.0014011 2006.197.07:20:02.01#antcn#PM 3 -0.0059899 0.0042895 -0.0643783 0.0000000 0.0000000 2006.197.07:20:02.01#antcn#PM 4 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.197.07:20:02.01#antcn#PM 5 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.197.07:20:03.14:ready_k5 2006.197.07:20:03.14&ready_k5/obsinfo=st 2006.197.07:20:03.14&ready_k5/autoobs=1 2006.197.07:20:03.14&ready_k5/autoobs=2 2006.197.07:20:03.14&ready_k5/autoobs=3 2006.197.07:20:03.14&ready_k5/autoobs=4 2006.197.07:20:03.14&ready_k5/obsinfo 2006.197.07:20:03.14/obsinfo=st/error_log.tmp was not found (or not removed). 2006.197.07:20:03.14#flagr#flagr/antenna,new-source 2006.197.07:20:06.31/autoobs//k5ts1/ autoobs started! 2006.197.07:20:09.42/autoobs//k5ts2/ autoobs started! 2006.197.07:20:12.52/autoobs//k5ts3/ autoobs started! 2006.197.07:20:15.63/autoobs//k5ts4/ autoobs started! 2006.197.07:20:15.66/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.197.07:20:15.66:4f8m12a=1 2006.197.07:20:15.66&4f8m12a/xlog=on 2006.197.07:20:15.66&4f8m12a/echo=on 2006.197.07:20:15.66&4f8m12a/pcalon 2006.197.07:20:15.66&4f8m12a/"tpicd=stop 2006.197.07:20:15.66&4f8m12a/vc4f8 2006.197.07:20:15.66&4f8m12a/ifd4f 2006.197.07:20:15.66&4f8m12a/"form=m,16.000,1:2 2006.197.07:20:15.66&4f8m12a/"tpicd 2006.197.07:20:15.66&4f8m12a/echo=off 2006.197.07:20:15.66&4f8m12a/xlog=off 2006.197.07:20:15.66$4f8m12a/echo=on 2006.197.07:20:15.66$4f8m12a/pcalon 2006.197.07:20:15.66&pcalon/"no phase cal control is implemented here 2006.197.07:20:15.66$pcalon/"no phase cal control is implemented here 2006.197.07:20:15.66$4f8m12a/"tpicd=stop 2006.197.07:20:15.66$4f8m12a/vc4f8 2006.197.07:20:15.66&vc4f8/valo=1,532.99 2006.197.07:20:15.66&vc4f8/va=1,8 2006.197.07:20:15.66&vc4f8/valo=2,572.99 2006.197.07:20:15.66&vc4f8/va=2,7 2006.197.07:20:15.66&vc4f8/valo=3,672.99 2006.197.07:20:15.66&vc4f8/va=3,6 2006.197.07:20:15.66&vc4f8/valo=4,832.99 2006.197.07:20:15.66&vc4f8/va=4,7 2006.197.07:20:15.66&vc4f8/valo=5,652.99 2006.197.07:20:15.66&vc4f8/va=5,7 2006.197.07:20:15.66&vc4f8/valo=6,772.99 2006.197.07:20:15.66&vc4f8/va=6,6 2006.197.07:20:15.66&vc4f8/valo=7,832.99 2006.197.07:20:15.66&vc4f8/va=7,6 2006.197.07:20:15.66&vc4f8/valo=8,852.99 2006.197.07:20:15.66&vc4f8/va=8,7 2006.197.07:20:15.66&vc4f8/vblo=1,632.99 2006.197.07:20:15.66&vc4f8/vb=1,4 2006.197.07:20:15.66&vc4f8/vblo=2,640.99 2006.197.07:20:15.66&vc4f8/vb=2,4 2006.197.07:20:15.66&vc4f8/vblo=3,656.99 2006.197.07:20:15.66&vc4f8/vb=3,4 2006.197.07:20:15.66&vc4f8/vblo=4,712.99 2006.197.07:20:15.66&vc4f8/vb=4,4 2006.197.07:20:15.66&vc4f8/vblo=5,744.99 2006.197.07:20:15.66&vc4f8/vb=5,4 2006.197.07:20:15.66&vc4f8/vblo=6,752.99 2006.197.07:20:15.66&vc4f8/vb=6,4 2006.197.07:20:15.66&vc4f8/vabw=wide 2006.197.07:20:15.66&vc4f8/vbbw=wide 2006.197.07:20:15.66$vc4f8/valo=1,532.99 2006.197.07:20:15.67#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.197.07:20:15.67#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.197.07:20:15.67#ibcon#ireg 17 cls_cnt 0 2006.197.07:20:15.67#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.197.07:20:15.67#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.197.07:20:15.67#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.197.07:20:15.67#ibcon#enter wrdev, iclass 12, count 0 2006.197.07:20:15.67#ibcon#first serial, iclass 12, count 0 2006.197.07:20:15.67#ibcon#enter sib2, iclass 12, count 0 2006.197.07:20:15.67#ibcon#flushed, iclass 12, count 0 2006.197.07:20:15.67#ibcon#about to write, iclass 12, count 0 2006.197.07:20:15.67#ibcon#wrote, iclass 12, count 0 2006.197.07:20:15.67#ibcon#about to read 3, iclass 12, count 0 2006.197.07:20:15.69#ibcon#read 3, iclass 12, count 0 2006.197.07:20:15.69#ibcon#about to read 4, iclass 12, count 0 2006.197.07:20:15.69#ibcon#read 4, iclass 12, count 0 2006.197.07:20:15.69#ibcon#about to read 5, iclass 12, count 0 2006.197.07:20:15.69#ibcon#read 5, iclass 12, count 0 2006.197.07:20:15.69#ibcon#about to read 6, iclass 12, count 0 2006.197.07:20:15.69#ibcon#read 6, iclass 12, count 0 2006.197.07:20:15.69#ibcon#end of sib2, iclass 12, count 0 2006.197.07:20:15.69#ibcon#*mode == 0, iclass 12, count 0 2006.197.07:20:15.69#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.197.07:20:15.69#ibcon#[26=FRQ=01,532.99\r\n] 2006.197.07:20:15.69#ibcon#*before write, iclass 12, count 0 2006.197.07:20:15.69#ibcon#enter sib2, iclass 12, count 0 2006.197.07:20:15.69#ibcon#flushed, iclass 12, count 0 2006.197.07:20:15.69#ibcon#about to write, iclass 12, count 0 2006.197.07:20:15.69#ibcon#wrote, iclass 12, count 0 2006.197.07:20:15.69#ibcon#about to read 3, iclass 12, count 0 2006.197.07:20:15.74#ibcon#read 3, iclass 12, count 0 2006.197.07:20:15.74#ibcon#about to read 4, iclass 12, count 0 2006.197.07:20:15.74#ibcon#read 4, iclass 12, count 0 2006.197.07:20:15.74#ibcon#about to read 5, iclass 12, count 0 2006.197.07:20:15.74#ibcon#read 5, iclass 12, count 0 2006.197.07:20:15.74#ibcon#about to read 6, iclass 12, count 0 2006.197.07:20:15.74#ibcon#read 6, iclass 12, count 0 2006.197.07:20:15.74#ibcon#end of sib2, iclass 12, count 0 2006.197.07:20:15.74#ibcon#*after write, iclass 12, count 0 2006.197.07:20:15.74#ibcon#*before return 0, iclass 12, count 0 2006.197.07:20:15.74#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.197.07:20:15.74#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.197.07:20:15.74#ibcon#about to clear, iclass 12 cls_cnt 0 2006.197.07:20:15.74#ibcon#cleared, iclass 12 cls_cnt 0 2006.197.07:20:15.74$vc4f8/va=1,8 2006.197.07:20:15.74#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.197.07:20:15.74#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.197.07:20:15.74#ibcon#ireg 11 cls_cnt 2 2006.197.07:20:15.74#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.197.07:20:15.74#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.197.07:20:15.74#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.197.07:20:15.74#ibcon#enter wrdev, iclass 14, count 2 2006.197.07:20:15.74#ibcon#first serial, iclass 14, count 2 2006.197.07:20:15.74#ibcon#enter sib2, iclass 14, count 2 2006.197.07:20:15.74#ibcon#flushed, iclass 14, count 2 2006.197.07:20:15.74#ibcon#about to write, iclass 14, count 2 2006.197.07:20:15.74#ibcon#wrote, iclass 14, count 2 2006.197.07:20:15.74#ibcon#about to read 3, iclass 14, count 2 2006.197.07:20:15.76#ibcon#read 3, iclass 14, count 2 2006.197.07:20:15.76#ibcon#about to read 4, iclass 14, count 2 2006.197.07:20:15.76#ibcon#read 4, iclass 14, count 2 2006.197.07:20:15.76#ibcon#about to read 5, iclass 14, count 2 2006.197.07:20:15.76#ibcon#read 5, iclass 14, count 2 2006.197.07:20:15.76#ibcon#about to read 6, iclass 14, count 2 2006.197.07:20:15.76#ibcon#read 6, iclass 14, count 2 2006.197.07:20:15.76#ibcon#end of sib2, iclass 14, count 2 2006.197.07:20:15.76#ibcon#*mode == 0, iclass 14, count 2 2006.197.07:20:15.76#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.197.07:20:15.76#ibcon#[25=AT01-08\r\n] 2006.197.07:20:15.76#ibcon#*before write, iclass 14, count 2 2006.197.07:20:15.76#ibcon#enter sib2, iclass 14, count 2 2006.197.07:20:15.76#ibcon#flushed, iclass 14, count 2 2006.197.07:20:15.76#ibcon#about to write, iclass 14, count 2 2006.197.07:20:15.76#ibcon#wrote, iclass 14, count 2 2006.197.07:20:15.76#ibcon#about to read 3, iclass 14, count 2 2006.197.07:20:15.79#ibcon#read 3, iclass 14, count 2 2006.197.07:20:15.79#ibcon#about to read 4, iclass 14, count 2 2006.197.07:20:15.79#ibcon#read 4, iclass 14, count 2 2006.197.07:20:15.79#ibcon#about to read 5, iclass 14, count 2 2006.197.07:20:15.79#ibcon#read 5, iclass 14, count 2 2006.197.07:20:15.79#ibcon#about to read 6, iclass 14, count 2 2006.197.07:20:15.79#ibcon#read 6, iclass 14, count 2 2006.197.07:20:15.79#ibcon#end of sib2, iclass 14, count 2 2006.197.07:20:15.79#ibcon#*after write, iclass 14, count 2 2006.197.07:20:15.79#ibcon#*before return 0, iclass 14, count 2 2006.197.07:20:15.79#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.197.07:20:15.79#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.197.07:20:15.79#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.197.07:20:15.79#ibcon#ireg 7 cls_cnt 0 2006.197.07:20:15.79#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.197.07:20:15.91#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.197.07:20:15.91#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.197.07:20:15.91#ibcon#enter wrdev, iclass 14, count 0 2006.197.07:20:15.91#ibcon#first serial, iclass 14, count 0 2006.197.07:20:15.91#ibcon#enter sib2, iclass 14, count 0 2006.197.07:20:15.91#ibcon#flushed, iclass 14, count 0 2006.197.07:20:15.91#ibcon#about to write, iclass 14, count 0 2006.197.07:20:15.91#ibcon#wrote, iclass 14, count 0 2006.197.07:20:15.91#ibcon#about to read 3, iclass 14, count 0 2006.197.07:20:15.93#ibcon#read 3, iclass 14, count 0 2006.197.07:20:15.93#ibcon#about to read 4, iclass 14, count 0 2006.197.07:20:15.93#ibcon#read 4, iclass 14, count 0 2006.197.07:20:15.93#ibcon#about to read 5, iclass 14, count 0 2006.197.07:20:15.93#ibcon#read 5, iclass 14, count 0 2006.197.07:20:15.93#ibcon#about to read 6, iclass 14, count 0 2006.197.07:20:15.93#ibcon#read 6, iclass 14, count 0 2006.197.07:20:15.93#ibcon#end of sib2, iclass 14, count 0 2006.197.07:20:15.93#ibcon#*mode == 0, iclass 14, count 0 2006.197.07:20:15.93#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.197.07:20:15.93#ibcon#[25=USB\r\n] 2006.197.07:20:15.93#ibcon#*before write, iclass 14, count 0 2006.197.07:20:15.93#ibcon#enter sib2, iclass 14, count 0 2006.197.07:20:15.93#ibcon#flushed, iclass 14, count 0 2006.197.07:20:15.93#ibcon#about to write, iclass 14, count 0 2006.197.07:20:15.93#ibcon#wrote, iclass 14, count 0 2006.197.07:20:15.93#ibcon#about to read 3, iclass 14, count 0 2006.197.07:20:15.96#ibcon#read 3, iclass 14, count 0 2006.197.07:20:15.96#ibcon#about to read 4, iclass 14, count 0 2006.197.07:20:15.96#ibcon#read 4, iclass 14, count 0 2006.197.07:20:15.96#ibcon#about to read 5, iclass 14, count 0 2006.197.07:20:15.96#ibcon#read 5, iclass 14, count 0 2006.197.07:20:15.96#ibcon#about to read 6, iclass 14, count 0 2006.197.07:20:15.96#ibcon#read 6, iclass 14, count 0 2006.197.07:20:15.96#ibcon#end of sib2, iclass 14, count 0 2006.197.07:20:15.96#ibcon#*after write, iclass 14, count 0 2006.197.07:20:15.96#ibcon#*before return 0, iclass 14, count 0 2006.197.07:20:15.96#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.197.07:20:15.96#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.197.07:20:15.96#ibcon#about to clear, iclass 14 cls_cnt 0 2006.197.07:20:15.96#ibcon#cleared, iclass 14 cls_cnt 0 2006.197.07:20:15.96$vc4f8/valo=2,572.99 2006.197.07:20:15.96#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.197.07:20:15.96#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.197.07:20:15.96#ibcon#ireg 17 cls_cnt 0 2006.197.07:20:15.96#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.197.07:20:15.96#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.197.07:20:15.96#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.197.07:20:15.96#ibcon#enter wrdev, iclass 16, count 0 2006.197.07:20:15.96#ibcon#first serial, iclass 16, count 0 2006.197.07:20:15.96#ibcon#enter sib2, iclass 16, count 0 2006.197.07:20:15.96#ibcon#flushed, iclass 16, count 0 2006.197.07:20:15.96#ibcon#about to write, iclass 16, count 0 2006.197.07:20:15.96#ibcon#wrote, iclass 16, count 0 2006.197.07:20:15.96#ibcon#about to read 3, iclass 16, count 0 2006.197.07:20:15.98#ibcon#read 3, iclass 16, count 0 2006.197.07:20:15.98#ibcon#about to read 4, iclass 16, count 0 2006.197.07:20:15.98#ibcon#read 4, iclass 16, count 0 2006.197.07:20:15.98#ibcon#about to read 5, iclass 16, count 0 2006.197.07:20:15.98#ibcon#read 5, iclass 16, count 0 2006.197.07:20:15.98#ibcon#about to read 6, iclass 16, count 0 2006.197.07:20:15.98#ibcon#read 6, iclass 16, count 0 2006.197.07:20:15.98#ibcon#end of sib2, iclass 16, count 0 2006.197.07:20:15.98#ibcon#*mode == 0, iclass 16, count 0 2006.197.07:20:15.98#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.197.07:20:15.98#ibcon#[26=FRQ=02,572.99\r\n] 2006.197.07:20:15.98#ibcon#*before write, iclass 16, count 0 2006.197.07:20:15.98#ibcon#enter sib2, iclass 16, count 0 2006.197.07:20:15.98#ibcon#flushed, iclass 16, count 0 2006.197.07:20:15.98#ibcon#about to write, iclass 16, count 0 2006.197.07:20:15.98#ibcon#wrote, iclass 16, count 0 2006.197.07:20:15.98#ibcon#about to read 3, iclass 16, count 0 2006.197.07:20:16.02#ibcon#read 3, iclass 16, count 0 2006.197.07:20:16.02#ibcon#about to read 4, iclass 16, count 0 2006.197.07:20:16.02#ibcon#read 4, iclass 16, count 0 2006.197.07:20:16.02#ibcon#about to read 5, iclass 16, count 0 2006.197.07:20:16.02#ibcon#read 5, iclass 16, count 0 2006.197.07:20:16.02#ibcon#about to read 6, iclass 16, count 0 2006.197.07:20:16.02#ibcon#read 6, iclass 16, count 0 2006.197.07:20:16.02#ibcon#end of sib2, iclass 16, count 0 2006.197.07:20:16.02#ibcon#*after write, iclass 16, count 0 2006.197.07:20:16.02#ibcon#*before return 0, iclass 16, count 0 2006.197.07:20:16.02#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.197.07:20:16.02#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.197.07:20:16.02#ibcon#about to clear, iclass 16 cls_cnt 0 2006.197.07:20:16.02#ibcon#cleared, iclass 16 cls_cnt 0 2006.197.07:20:16.02$vc4f8/va=2,7 2006.197.07:20:16.02#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.197.07:20:16.02#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.197.07:20:16.02#ibcon#ireg 11 cls_cnt 2 2006.197.07:20:16.02#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.197.07:20:16.08#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.197.07:20:16.08#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.197.07:20:16.08#ibcon#enter wrdev, iclass 18, count 2 2006.197.07:20:16.08#ibcon#first serial, iclass 18, count 2 2006.197.07:20:16.08#ibcon#enter sib2, iclass 18, count 2 2006.197.07:20:16.08#ibcon#flushed, iclass 18, count 2 2006.197.07:20:16.08#ibcon#about to write, iclass 18, count 2 2006.197.07:20:16.08#ibcon#wrote, iclass 18, count 2 2006.197.07:20:16.08#ibcon#about to read 3, iclass 18, count 2 2006.197.07:20:16.10#ibcon#read 3, iclass 18, count 2 2006.197.07:20:16.10#ibcon#about to read 4, iclass 18, count 2 2006.197.07:20:16.10#ibcon#read 4, iclass 18, count 2 2006.197.07:20:16.10#ibcon#about to read 5, iclass 18, count 2 2006.197.07:20:16.10#ibcon#read 5, iclass 18, count 2 2006.197.07:20:16.10#ibcon#about to read 6, iclass 18, count 2 2006.197.07:20:16.10#ibcon#read 6, iclass 18, count 2 2006.197.07:20:16.10#ibcon#end of sib2, iclass 18, count 2 2006.197.07:20:16.10#ibcon#*mode == 0, iclass 18, count 2 2006.197.07:20:16.10#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.197.07:20:16.10#ibcon#[25=AT02-07\r\n] 2006.197.07:20:16.10#ibcon#*before write, iclass 18, count 2 2006.197.07:20:16.10#ibcon#enter sib2, iclass 18, count 2 2006.197.07:20:16.10#ibcon#flushed, iclass 18, count 2 2006.197.07:20:16.10#ibcon#about to write, iclass 18, count 2 2006.197.07:20:16.10#ibcon#wrote, iclass 18, count 2 2006.197.07:20:16.10#ibcon#about to read 3, iclass 18, count 2 2006.197.07:20:16.13#ibcon#read 3, iclass 18, count 2 2006.197.07:20:16.13#ibcon#about to read 4, iclass 18, count 2 2006.197.07:20:16.13#ibcon#read 4, iclass 18, count 2 2006.197.07:20:16.13#ibcon#about to read 5, iclass 18, count 2 2006.197.07:20:16.13#ibcon#read 5, iclass 18, count 2 2006.197.07:20:16.13#ibcon#about to read 6, iclass 18, count 2 2006.197.07:20:16.13#ibcon#read 6, iclass 18, count 2 2006.197.07:20:16.13#ibcon#end of sib2, iclass 18, count 2 2006.197.07:20:16.13#ibcon#*after write, iclass 18, count 2 2006.197.07:20:16.13#ibcon#*before return 0, iclass 18, count 2 2006.197.07:20:16.13#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.197.07:20:16.13#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.197.07:20:16.13#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.197.07:20:16.13#ibcon#ireg 7 cls_cnt 0 2006.197.07:20:16.13#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.197.07:20:16.25#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.197.07:20:16.25#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.197.07:20:16.25#ibcon#enter wrdev, iclass 18, count 0 2006.197.07:20:16.25#ibcon#first serial, iclass 18, count 0 2006.197.07:20:16.25#ibcon#enter sib2, iclass 18, count 0 2006.197.07:20:16.25#ibcon#flushed, iclass 18, count 0 2006.197.07:20:16.25#ibcon#about to write, iclass 18, count 0 2006.197.07:20:16.25#ibcon#wrote, iclass 18, count 0 2006.197.07:20:16.25#ibcon#about to read 3, iclass 18, count 0 2006.197.07:20:16.27#ibcon#read 3, iclass 18, count 0 2006.197.07:20:16.27#ibcon#about to read 4, iclass 18, count 0 2006.197.07:20:16.27#ibcon#read 4, iclass 18, count 0 2006.197.07:20:16.27#ibcon#about to read 5, iclass 18, count 0 2006.197.07:20:16.27#ibcon#read 5, iclass 18, count 0 2006.197.07:20:16.27#ibcon#about to read 6, iclass 18, count 0 2006.197.07:20:16.27#ibcon#read 6, iclass 18, count 0 2006.197.07:20:16.27#ibcon#end of sib2, iclass 18, count 0 2006.197.07:20:16.27#ibcon#*mode == 0, iclass 18, count 0 2006.197.07:20:16.27#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.197.07:20:16.27#ibcon#[25=USB\r\n] 2006.197.07:20:16.27#ibcon#*before write, iclass 18, count 0 2006.197.07:20:16.27#ibcon#enter sib2, iclass 18, count 0 2006.197.07:20:16.27#ibcon#flushed, iclass 18, count 0 2006.197.07:20:16.27#ibcon#about to write, iclass 18, count 0 2006.197.07:20:16.27#ibcon#wrote, iclass 18, count 0 2006.197.07:20:16.27#ibcon#about to read 3, iclass 18, count 0 2006.197.07:20:16.30#ibcon#read 3, iclass 18, count 0 2006.197.07:20:16.30#ibcon#about to read 4, iclass 18, count 0 2006.197.07:20:16.30#ibcon#read 4, iclass 18, count 0 2006.197.07:20:16.30#ibcon#about to read 5, iclass 18, count 0 2006.197.07:20:16.30#ibcon#read 5, iclass 18, count 0 2006.197.07:20:16.30#ibcon#about to read 6, iclass 18, count 0 2006.197.07:20:16.30#ibcon#read 6, iclass 18, count 0 2006.197.07:20:16.30#ibcon#end of sib2, iclass 18, count 0 2006.197.07:20:16.30#ibcon#*after write, iclass 18, count 0 2006.197.07:20:16.30#ibcon#*before return 0, iclass 18, count 0 2006.197.07:20:16.30#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.197.07:20:16.30#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.197.07:20:16.30#ibcon#about to clear, iclass 18 cls_cnt 0 2006.197.07:20:16.30#ibcon#cleared, iclass 18 cls_cnt 0 2006.197.07:20:16.30$vc4f8/valo=3,672.99 2006.197.07:20:16.30#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.197.07:20:16.30#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.197.07:20:16.30#ibcon#ireg 17 cls_cnt 0 2006.197.07:20:16.30#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.197.07:20:16.30#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.197.07:20:16.30#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.197.07:20:16.30#ibcon#enter wrdev, iclass 20, count 0 2006.197.07:20:16.30#ibcon#first serial, iclass 20, count 0 2006.197.07:20:16.30#ibcon#enter sib2, iclass 20, count 0 2006.197.07:20:16.30#ibcon#flushed, iclass 20, count 0 2006.197.07:20:16.30#ibcon#about to write, iclass 20, count 0 2006.197.07:20:16.30#ibcon#wrote, iclass 20, count 0 2006.197.07:20:16.30#ibcon#about to read 3, iclass 20, count 0 2006.197.07:20:16.32#ibcon#read 3, iclass 20, count 0 2006.197.07:20:16.32#ibcon#about to read 4, iclass 20, count 0 2006.197.07:20:16.32#ibcon#read 4, iclass 20, count 0 2006.197.07:20:16.32#ibcon#about to read 5, iclass 20, count 0 2006.197.07:20:16.32#ibcon#read 5, iclass 20, count 0 2006.197.07:20:16.32#ibcon#about to read 6, iclass 20, count 0 2006.197.07:20:16.32#ibcon#read 6, iclass 20, count 0 2006.197.07:20:16.32#ibcon#end of sib2, iclass 20, count 0 2006.197.07:20:16.32#ibcon#*mode == 0, iclass 20, count 0 2006.197.07:20:16.32#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.197.07:20:16.32#ibcon#[26=FRQ=03,672.99\r\n] 2006.197.07:20:16.32#ibcon#*before write, iclass 20, count 0 2006.197.07:20:16.32#ibcon#enter sib2, iclass 20, count 0 2006.197.07:20:16.32#ibcon#flushed, iclass 20, count 0 2006.197.07:20:16.32#ibcon#about to write, iclass 20, count 0 2006.197.07:20:16.32#ibcon#wrote, iclass 20, count 0 2006.197.07:20:16.32#ibcon#about to read 3, iclass 20, count 0 2006.197.07:20:16.36#ibcon#read 3, iclass 20, count 0 2006.197.07:20:16.36#ibcon#about to read 4, iclass 20, count 0 2006.197.07:20:16.36#ibcon#read 4, iclass 20, count 0 2006.197.07:20:16.36#ibcon#about to read 5, iclass 20, count 0 2006.197.07:20:16.36#ibcon#read 5, iclass 20, count 0 2006.197.07:20:16.36#ibcon#about to read 6, iclass 20, count 0 2006.197.07:20:16.36#ibcon#read 6, iclass 20, count 0 2006.197.07:20:16.36#ibcon#end of sib2, iclass 20, count 0 2006.197.07:20:16.36#ibcon#*after write, iclass 20, count 0 2006.197.07:20:16.36#ibcon#*before return 0, iclass 20, count 0 2006.197.07:20:16.36#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.197.07:20:16.36#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.197.07:20:16.36#ibcon#about to clear, iclass 20 cls_cnt 0 2006.197.07:20:16.36#ibcon#cleared, iclass 20 cls_cnt 0 2006.197.07:20:16.36$vc4f8/va=3,6 2006.197.07:20:16.36#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.197.07:20:16.36#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.197.07:20:16.36#ibcon#ireg 11 cls_cnt 2 2006.197.07:20:16.36#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.197.07:20:16.42#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.197.07:20:16.42#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.197.07:20:16.42#ibcon#enter wrdev, iclass 22, count 2 2006.197.07:20:16.42#ibcon#first serial, iclass 22, count 2 2006.197.07:20:16.42#ibcon#enter sib2, iclass 22, count 2 2006.197.07:20:16.42#ibcon#flushed, iclass 22, count 2 2006.197.07:20:16.42#ibcon#about to write, iclass 22, count 2 2006.197.07:20:16.42#ibcon#wrote, iclass 22, count 2 2006.197.07:20:16.42#ibcon#about to read 3, iclass 22, count 2 2006.197.07:20:16.44#ibcon#read 3, iclass 22, count 2 2006.197.07:20:16.44#ibcon#about to read 4, iclass 22, count 2 2006.197.07:20:16.44#ibcon#read 4, iclass 22, count 2 2006.197.07:20:16.44#ibcon#about to read 5, iclass 22, count 2 2006.197.07:20:16.44#ibcon#read 5, iclass 22, count 2 2006.197.07:20:16.44#ibcon#about to read 6, iclass 22, count 2 2006.197.07:20:16.44#ibcon#read 6, iclass 22, count 2 2006.197.07:20:16.44#ibcon#end of sib2, iclass 22, count 2 2006.197.07:20:16.44#ibcon#*mode == 0, iclass 22, count 2 2006.197.07:20:16.44#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.197.07:20:16.44#ibcon#[25=AT03-06\r\n] 2006.197.07:20:16.44#ibcon#*before write, iclass 22, count 2 2006.197.07:20:16.44#ibcon#enter sib2, iclass 22, count 2 2006.197.07:20:16.44#ibcon#flushed, iclass 22, count 2 2006.197.07:20:16.44#ibcon#about to write, iclass 22, count 2 2006.197.07:20:16.44#ibcon#wrote, iclass 22, count 2 2006.197.07:20:16.44#ibcon#about to read 3, iclass 22, count 2 2006.197.07:20:16.47#ibcon#read 3, iclass 22, count 2 2006.197.07:20:16.47#ibcon#about to read 4, iclass 22, count 2 2006.197.07:20:16.47#ibcon#read 4, iclass 22, count 2 2006.197.07:20:16.47#ibcon#about to read 5, iclass 22, count 2 2006.197.07:20:16.47#ibcon#read 5, iclass 22, count 2 2006.197.07:20:16.47#ibcon#about to read 6, iclass 22, count 2 2006.197.07:20:16.47#ibcon#read 6, iclass 22, count 2 2006.197.07:20:16.47#ibcon#end of sib2, iclass 22, count 2 2006.197.07:20:16.47#ibcon#*after write, iclass 22, count 2 2006.197.07:20:16.47#ibcon#*before return 0, iclass 22, count 2 2006.197.07:20:16.47#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.197.07:20:16.47#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.197.07:20:16.47#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.197.07:20:16.47#ibcon#ireg 7 cls_cnt 0 2006.197.07:20:16.47#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.197.07:20:16.59#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.197.07:20:16.59#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.197.07:20:16.59#ibcon#enter wrdev, iclass 22, count 0 2006.197.07:20:16.59#ibcon#first serial, iclass 22, count 0 2006.197.07:20:16.59#ibcon#enter sib2, iclass 22, count 0 2006.197.07:20:16.59#ibcon#flushed, iclass 22, count 0 2006.197.07:20:16.59#ibcon#about to write, iclass 22, count 0 2006.197.07:20:16.59#ibcon#wrote, iclass 22, count 0 2006.197.07:20:16.59#ibcon#about to read 3, iclass 22, count 0 2006.197.07:20:16.61#ibcon#read 3, iclass 22, count 0 2006.197.07:20:16.61#ibcon#about to read 4, iclass 22, count 0 2006.197.07:20:16.61#ibcon#read 4, iclass 22, count 0 2006.197.07:20:16.61#ibcon#about to read 5, iclass 22, count 0 2006.197.07:20:16.61#ibcon#read 5, iclass 22, count 0 2006.197.07:20:16.61#ibcon#about to read 6, iclass 22, count 0 2006.197.07:20:16.61#ibcon#read 6, iclass 22, count 0 2006.197.07:20:16.61#ibcon#end of sib2, iclass 22, count 0 2006.197.07:20:16.61#ibcon#*mode == 0, iclass 22, count 0 2006.197.07:20:16.61#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.197.07:20:16.61#ibcon#[25=USB\r\n] 2006.197.07:20:16.61#ibcon#*before write, iclass 22, count 0 2006.197.07:20:16.61#ibcon#enter sib2, iclass 22, count 0 2006.197.07:20:16.61#ibcon#flushed, iclass 22, count 0 2006.197.07:20:16.61#ibcon#about to write, iclass 22, count 0 2006.197.07:20:16.61#ibcon#wrote, iclass 22, count 0 2006.197.07:20:16.61#ibcon#about to read 3, iclass 22, count 0 2006.197.07:20:16.64#ibcon#read 3, iclass 22, count 0 2006.197.07:20:16.64#ibcon#about to read 4, iclass 22, count 0 2006.197.07:20:16.64#ibcon#read 4, iclass 22, count 0 2006.197.07:20:16.64#ibcon#about to read 5, iclass 22, count 0 2006.197.07:20:16.64#ibcon#read 5, iclass 22, count 0 2006.197.07:20:16.64#ibcon#about to read 6, iclass 22, count 0 2006.197.07:20:16.64#ibcon#read 6, iclass 22, count 0 2006.197.07:20:16.64#ibcon#end of sib2, iclass 22, count 0 2006.197.07:20:16.64#ibcon#*after write, iclass 22, count 0 2006.197.07:20:16.64#ibcon#*before return 0, iclass 22, count 0 2006.197.07:20:16.64#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.197.07:20:16.64#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.197.07:20:16.64#ibcon#about to clear, iclass 22 cls_cnt 0 2006.197.07:20:16.64#ibcon#cleared, iclass 22 cls_cnt 0 2006.197.07:20:16.64$vc4f8/valo=4,832.99 2006.197.07:20:16.64#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.197.07:20:16.64#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.197.07:20:16.64#ibcon#ireg 17 cls_cnt 0 2006.197.07:20:16.64#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.197.07:20:16.64#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.197.07:20:16.64#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.197.07:20:16.64#ibcon#enter wrdev, iclass 24, count 0 2006.197.07:20:16.64#ibcon#first serial, iclass 24, count 0 2006.197.07:20:16.64#ibcon#enter sib2, iclass 24, count 0 2006.197.07:20:16.64#ibcon#flushed, iclass 24, count 0 2006.197.07:20:16.64#ibcon#about to write, iclass 24, count 0 2006.197.07:20:16.64#ibcon#wrote, iclass 24, count 0 2006.197.07:20:16.64#ibcon#about to read 3, iclass 24, count 0 2006.197.07:20:16.66#ibcon#read 3, iclass 24, count 0 2006.197.07:20:16.66#ibcon#about to read 4, iclass 24, count 0 2006.197.07:20:16.66#ibcon#read 4, iclass 24, count 0 2006.197.07:20:16.66#ibcon#about to read 5, iclass 24, count 0 2006.197.07:20:16.66#ibcon#read 5, iclass 24, count 0 2006.197.07:20:16.66#ibcon#about to read 6, iclass 24, count 0 2006.197.07:20:16.66#ibcon#read 6, iclass 24, count 0 2006.197.07:20:16.66#ibcon#end of sib2, iclass 24, count 0 2006.197.07:20:16.66#ibcon#*mode == 0, iclass 24, count 0 2006.197.07:20:16.66#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.197.07:20:16.66#ibcon#[26=FRQ=04,832.99\r\n] 2006.197.07:20:16.66#ibcon#*before write, iclass 24, count 0 2006.197.07:20:16.66#ibcon#enter sib2, iclass 24, count 0 2006.197.07:20:16.66#ibcon#flushed, iclass 24, count 0 2006.197.07:20:16.66#ibcon#about to write, iclass 24, count 0 2006.197.07:20:16.66#ibcon#wrote, iclass 24, count 0 2006.197.07:20:16.66#ibcon#about to read 3, iclass 24, count 0 2006.197.07:20:16.70#ibcon#read 3, iclass 24, count 0 2006.197.07:20:16.70#ibcon#about to read 4, iclass 24, count 0 2006.197.07:20:16.70#ibcon#read 4, iclass 24, count 0 2006.197.07:20:16.70#ibcon#about to read 5, iclass 24, count 0 2006.197.07:20:16.70#ibcon#read 5, iclass 24, count 0 2006.197.07:20:16.70#ibcon#about to read 6, iclass 24, count 0 2006.197.07:20:16.70#ibcon#read 6, iclass 24, count 0 2006.197.07:20:16.70#ibcon#end of sib2, iclass 24, count 0 2006.197.07:20:16.70#ibcon#*after write, iclass 24, count 0 2006.197.07:20:16.70#ibcon#*before return 0, iclass 24, count 0 2006.197.07:20:16.70#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.197.07:20:16.70#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.197.07:20:16.70#ibcon#about to clear, iclass 24 cls_cnt 0 2006.197.07:20:16.70#ibcon#cleared, iclass 24 cls_cnt 0 2006.197.07:20:16.70$vc4f8/va=4,7 2006.197.07:20:16.70#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.197.07:20:16.70#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.197.07:20:16.70#ibcon#ireg 11 cls_cnt 2 2006.197.07:20:16.70#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.197.07:20:16.76#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.197.07:20:16.76#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.197.07:20:16.76#ibcon#enter wrdev, iclass 26, count 2 2006.197.07:20:16.76#ibcon#first serial, iclass 26, count 2 2006.197.07:20:16.76#ibcon#enter sib2, iclass 26, count 2 2006.197.07:20:16.76#ibcon#flushed, iclass 26, count 2 2006.197.07:20:16.76#ibcon#about to write, iclass 26, count 2 2006.197.07:20:16.76#ibcon#wrote, iclass 26, count 2 2006.197.07:20:16.76#ibcon#about to read 3, iclass 26, count 2 2006.197.07:20:16.78#ibcon#read 3, iclass 26, count 2 2006.197.07:20:16.78#ibcon#about to read 4, iclass 26, count 2 2006.197.07:20:16.78#ibcon#read 4, iclass 26, count 2 2006.197.07:20:16.78#ibcon#about to read 5, iclass 26, count 2 2006.197.07:20:16.78#ibcon#read 5, iclass 26, count 2 2006.197.07:20:16.78#ibcon#about to read 6, iclass 26, count 2 2006.197.07:20:16.78#ibcon#read 6, iclass 26, count 2 2006.197.07:20:16.78#ibcon#end of sib2, iclass 26, count 2 2006.197.07:20:16.78#ibcon#*mode == 0, iclass 26, count 2 2006.197.07:20:16.78#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.197.07:20:16.78#ibcon#[25=AT04-07\r\n] 2006.197.07:20:16.78#ibcon#*before write, iclass 26, count 2 2006.197.07:20:16.78#ibcon#enter sib2, iclass 26, count 2 2006.197.07:20:16.78#ibcon#flushed, iclass 26, count 2 2006.197.07:20:16.78#ibcon#about to write, iclass 26, count 2 2006.197.07:20:16.78#ibcon#wrote, iclass 26, count 2 2006.197.07:20:16.78#ibcon#about to read 3, iclass 26, count 2 2006.197.07:20:16.81#ibcon#read 3, iclass 26, count 2 2006.197.07:20:16.81#ibcon#about to read 4, iclass 26, count 2 2006.197.07:20:16.81#ibcon#read 4, iclass 26, count 2 2006.197.07:20:16.81#ibcon#about to read 5, iclass 26, count 2 2006.197.07:20:16.81#ibcon#read 5, iclass 26, count 2 2006.197.07:20:16.81#ibcon#about to read 6, iclass 26, count 2 2006.197.07:20:16.81#ibcon#read 6, iclass 26, count 2 2006.197.07:20:16.81#ibcon#end of sib2, iclass 26, count 2 2006.197.07:20:16.81#ibcon#*after write, iclass 26, count 2 2006.197.07:20:16.81#ibcon#*before return 0, iclass 26, count 2 2006.197.07:20:16.81#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.197.07:20:16.81#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.197.07:20:16.81#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.197.07:20:16.81#ibcon#ireg 7 cls_cnt 0 2006.197.07:20:16.81#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.197.07:20:16.93#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.197.07:20:16.93#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.197.07:20:16.93#ibcon#enter wrdev, iclass 26, count 0 2006.197.07:20:16.93#ibcon#first serial, iclass 26, count 0 2006.197.07:20:16.93#ibcon#enter sib2, iclass 26, count 0 2006.197.07:20:16.93#ibcon#flushed, iclass 26, count 0 2006.197.07:20:16.93#ibcon#about to write, iclass 26, count 0 2006.197.07:20:16.93#ibcon#wrote, iclass 26, count 0 2006.197.07:20:16.93#ibcon#about to read 3, iclass 26, count 0 2006.197.07:20:16.95#ibcon#read 3, iclass 26, count 0 2006.197.07:20:16.95#ibcon#about to read 4, iclass 26, count 0 2006.197.07:20:16.95#ibcon#read 4, iclass 26, count 0 2006.197.07:20:16.95#ibcon#about to read 5, iclass 26, count 0 2006.197.07:20:16.95#ibcon#read 5, iclass 26, count 0 2006.197.07:20:16.95#ibcon#about to read 6, iclass 26, count 0 2006.197.07:20:16.95#ibcon#read 6, iclass 26, count 0 2006.197.07:20:16.95#ibcon#end of sib2, iclass 26, count 0 2006.197.07:20:16.95#ibcon#*mode == 0, iclass 26, count 0 2006.197.07:20:16.95#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.197.07:20:16.95#ibcon#[25=USB\r\n] 2006.197.07:20:16.95#ibcon#*before write, iclass 26, count 0 2006.197.07:20:16.95#ibcon#enter sib2, iclass 26, count 0 2006.197.07:20:16.95#ibcon#flushed, iclass 26, count 0 2006.197.07:20:16.95#ibcon#about to write, iclass 26, count 0 2006.197.07:20:16.95#ibcon#wrote, iclass 26, count 0 2006.197.07:20:16.95#ibcon#about to read 3, iclass 26, count 0 2006.197.07:20:16.98#ibcon#read 3, iclass 26, count 0 2006.197.07:20:16.98#ibcon#about to read 4, iclass 26, count 0 2006.197.07:20:16.98#ibcon#read 4, iclass 26, count 0 2006.197.07:20:16.98#ibcon#about to read 5, iclass 26, count 0 2006.197.07:20:16.98#ibcon#read 5, iclass 26, count 0 2006.197.07:20:16.98#ibcon#about to read 6, iclass 26, count 0 2006.197.07:20:16.98#ibcon#read 6, iclass 26, count 0 2006.197.07:20:16.98#ibcon#end of sib2, iclass 26, count 0 2006.197.07:20:16.98#ibcon#*after write, iclass 26, count 0 2006.197.07:20:16.98#ibcon#*before return 0, iclass 26, count 0 2006.197.07:20:16.98#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.197.07:20:16.98#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.197.07:20:16.98#ibcon#about to clear, iclass 26 cls_cnt 0 2006.197.07:20:16.98#ibcon#cleared, iclass 26 cls_cnt 0 2006.197.07:20:16.98$vc4f8/valo=5,652.99 2006.197.07:20:16.98#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.197.07:20:16.98#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.197.07:20:16.98#ibcon#ireg 17 cls_cnt 0 2006.197.07:20:16.98#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.197.07:20:16.98#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.197.07:20:16.98#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.197.07:20:16.98#ibcon#enter wrdev, iclass 28, count 0 2006.197.07:20:16.98#ibcon#first serial, iclass 28, count 0 2006.197.07:20:16.98#ibcon#enter sib2, iclass 28, count 0 2006.197.07:20:16.98#ibcon#flushed, iclass 28, count 0 2006.197.07:20:16.98#ibcon#about to write, iclass 28, count 0 2006.197.07:20:16.98#ibcon#wrote, iclass 28, count 0 2006.197.07:20:16.98#ibcon#about to read 3, iclass 28, count 0 2006.197.07:20:17.00#ibcon#read 3, iclass 28, count 0 2006.197.07:20:17.00#ibcon#about to read 4, iclass 28, count 0 2006.197.07:20:17.00#ibcon#read 4, iclass 28, count 0 2006.197.07:20:17.00#ibcon#about to read 5, iclass 28, count 0 2006.197.07:20:17.00#ibcon#read 5, iclass 28, count 0 2006.197.07:20:17.00#ibcon#about to read 6, iclass 28, count 0 2006.197.07:20:17.00#ibcon#read 6, iclass 28, count 0 2006.197.07:20:17.00#ibcon#end of sib2, iclass 28, count 0 2006.197.07:20:17.00#ibcon#*mode == 0, iclass 28, count 0 2006.197.07:20:17.00#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.197.07:20:17.00#ibcon#[26=FRQ=05,652.99\r\n] 2006.197.07:20:17.00#ibcon#*before write, iclass 28, count 0 2006.197.07:20:17.00#ibcon#enter sib2, iclass 28, count 0 2006.197.07:20:17.00#ibcon#flushed, iclass 28, count 0 2006.197.07:20:17.00#ibcon#about to write, iclass 28, count 0 2006.197.07:20:17.00#ibcon#wrote, iclass 28, count 0 2006.197.07:20:17.00#ibcon#about to read 3, iclass 28, count 0 2006.197.07:20:17.04#ibcon#read 3, iclass 28, count 0 2006.197.07:20:17.04#ibcon#about to read 4, iclass 28, count 0 2006.197.07:20:17.04#ibcon#read 4, iclass 28, count 0 2006.197.07:20:17.04#ibcon#about to read 5, iclass 28, count 0 2006.197.07:20:17.04#ibcon#read 5, iclass 28, count 0 2006.197.07:20:17.04#ibcon#about to read 6, iclass 28, count 0 2006.197.07:20:17.04#ibcon#read 6, iclass 28, count 0 2006.197.07:20:17.04#ibcon#end of sib2, iclass 28, count 0 2006.197.07:20:17.04#ibcon#*after write, iclass 28, count 0 2006.197.07:20:17.04#ibcon#*before return 0, iclass 28, count 0 2006.197.07:20:17.04#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.197.07:20:17.04#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.197.07:20:17.04#ibcon#about to clear, iclass 28 cls_cnt 0 2006.197.07:20:17.04#ibcon#cleared, iclass 28 cls_cnt 0 2006.197.07:20:17.04$vc4f8/va=5,7 2006.197.07:20:17.04#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.197.07:20:17.04#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.197.07:20:17.04#ibcon#ireg 11 cls_cnt 2 2006.197.07:20:17.04#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.197.07:20:17.10#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.197.07:20:17.10#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.197.07:20:17.10#ibcon#enter wrdev, iclass 30, count 2 2006.197.07:20:17.10#ibcon#first serial, iclass 30, count 2 2006.197.07:20:17.10#ibcon#enter sib2, iclass 30, count 2 2006.197.07:20:17.10#ibcon#flushed, iclass 30, count 2 2006.197.07:20:17.10#ibcon#about to write, iclass 30, count 2 2006.197.07:20:17.10#ibcon#wrote, iclass 30, count 2 2006.197.07:20:17.10#ibcon#about to read 3, iclass 30, count 2 2006.197.07:20:17.12#ibcon#read 3, iclass 30, count 2 2006.197.07:20:17.12#ibcon#about to read 4, iclass 30, count 2 2006.197.07:20:17.12#ibcon#read 4, iclass 30, count 2 2006.197.07:20:17.12#ibcon#about to read 5, iclass 30, count 2 2006.197.07:20:17.12#ibcon#read 5, iclass 30, count 2 2006.197.07:20:17.12#ibcon#about to read 6, iclass 30, count 2 2006.197.07:20:17.12#ibcon#read 6, iclass 30, count 2 2006.197.07:20:17.12#ibcon#end of sib2, iclass 30, count 2 2006.197.07:20:17.12#ibcon#*mode == 0, iclass 30, count 2 2006.197.07:20:17.12#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.197.07:20:17.12#ibcon#[25=AT05-07\r\n] 2006.197.07:20:17.12#ibcon#*before write, iclass 30, count 2 2006.197.07:20:17.12#ibcon#enter sib2, iclass 30, count 2 2006.197.07:20:17.12#ibcon#flushed, iclass 30, count 2 2006.197.07:20:17.12#ibcon#about to write, iclass 30, count 2 2006.197.07:20:17.12#ibcon#wrote, iclass 30, count 2 2006.197.07:20:17.12#ibcon#about to read 3, iclass 30, count 2 2006.197.07:20:17.14#abcon#<5=/04 2.6 5.1 25.84 971003.2\r\n> 2006.197.07:20:17.15#ibcon#read 3, iclass 30, count 2 2006.197.07:20:17.15#ibcon#about to read 4, iclass 30, count 2 2006.197.07:20:17.15#ibcon#read 4, iclass 30, count 2 2006.197.07:20:17.15#ibcon#about to read 5, iclass 30, count 2 2006.197.07:20:17.15#ibcon#read 5, iclass 30, count 2 2006.197.07:20:17.15#ibcon#about to read 6, iclass 30, count 2 2006.197.07:20:17.15#ibcon#read 6, iclass 30, count 2 2006.197.07:20:17.15#ibcon#end of sib2, iclass 30, count 2 2006.197.07:20:17.15#ibcon#*after write, iclass 30, count 2 2006.197.07:20:17.15#ibcon#*before return 0, iclass 30, count 2 2006.197.07:20:17.15#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.197.07:20:17.15#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.197.07:20:17.15#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.197.07:20:17.15#ibcon#ireg 7 cls_cnt 0 2006.197.07:20:17.15#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.197.07:20:17.16#abcon#{5=INTERFACE CLEAR} 2006.197.07:20:17.22#abcon#[5=S1D000X0/0*\r\n] 2006.197.07:20:17.27#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.197.07:20:17.27#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.197.07:20:17.27#ibcon#enter wrdev, iclass 30, count 0 2006.197.07:20:17.27#ibcon#first serial, iclass 30, count 0 2006.197.07:20:17.27#ibcon#enter sib2, iclass 30, count 0 2006.197.07:20:17.27#ibcon#flushed, iclass 30, count 0 2006.197.07:20:17.27#ibcon#about to write, iclass 30, count 0 2006.197.07:20:17.27#ibcon#wrote, iclass 30, count 0 2006.197.07:20:17.27#ibcon#about to read 3, iclass 30, count 0 2006.197.07:20:17.29#ibcon#read 3, iclass 30, count 0 2006.197.07:20:17.29#ibcon#about to read 4, iclass 30, count 0 2006.197.07:20:17.29#ibcon#read 4, iclass 30, count 0 2006.197.07:20:17.29#ibcon#about to read 5, iclass 30, count 0 2006.197.07:20:17.29#ibcon#read 5, iclass 30, count 0 2006.197.07:20:17.29#ibcon#about to read 6, iclass 30, count 0 2006.197.07:20:17.29#ibcon#read 6, iclass 30, count 0 2006.197.07:20:17.29#ibcon#end of sib2, iclass 30, count 0 2006.197.07:20:17.29#ibcon#*mode == 0, iclass 30, count 0 2006.197.07:20:17.29#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.197.07:20:17.29#ibcon#[25=USB\r\n] 2006.197.07:20:17.29#ibcon#*before write, iclass 30, count 0 2006.197.07:20:17.29#ibcon#enter sib2, iclass 30, count 0 2006.197.07:20:17.29#ibcon#flushed, iclass 30, count 0 2006.197.07:20:17.29#ibcon#about to write, iclass 30, count 0 2006.197.07:20:17.29#ibcon#wrote, iclass 30, count 0 2006.197.07:20:17.29#ibcon#about to read 3, iclass 30, count 0 2006.197.07:20:17.32#ibcon#read 3, iclass 30, count 0 2006.197.07:20:17.32#ibcon#about to read 4, iclass 30, count 0 2006.197.07:20:17.32#ibcon#read 4, iclass 30, count 0 2006.197.07:20:17.32#ibcon#about to read 5, iclass 30, count 0 2006.197.07:20:17.32#ibcon#read 5, iclass 30, count 0 2006.197.07:20:17.32#ibcon#about to read 6, iclass 30, count 0 2006.197.07:20:17.32#ibcon#read 6, iclass 30, count 0 2006.197.07:20:17.32#ibcon#end of sib2, iclass 30, count 0 2006.197.07:20:17.32#ibcon#*after write, iclass 30, count 0 2006.197.07:20:17.32#ibcon#*before return 0, iclass 30, count 0 2006.197.07:20:17.32#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.197.07:20:17.32#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.197.07:20:17.32#ibcon#about to clear, iclass 30 cls_cnt 0 2006.197.07:20:17.32#ibcon#cleared, iclass 30 cls_cnt 0 2006.197.07:20:17.32$vc4f8/valo=6,772.99 2006.197.07:20:17.32#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.197.07:20:17.32#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.197.07:20:17.32#ibcon#ireg 17 cls_cnt 0 2006.197.07:20:17.32#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.197.07:20:17.32#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.197.07:20:17.32#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.197.07:20:17.32#ibcon#enter wrdev, iclass 36, count 0 2006.197.07:20:17.32#ibcon#first serial, iclass 36, count 0 2006.197.07:20:17.32#ibcon#enter sib2, iclass 36, count 0 2006.197.07:20:17.32#ibcon#flushed, iclass 36, count 0 2006.197.07:20:17.32#ibcon#about to write, iclass 36, count 0 2006.197.07:20:17.32#ibcon#wrote, iclass 36, count 0 2006.197.07:20:17.32#ibcon#about to read 3, iclass 36, count 0 2006.197.07:20:17.34#ibcon#read 3, iclass 36, count 0 2006.197.07:20:17.34#ibcon#about to read 4, iclass 36, count 0 2006.197.07:20:17.34#ibcon#read 4, iclass 36, count 0 2006.197.07:20:17.34#ibcon#about to read 5, iclass 36, count 0 2006.197.07:20:17.34#ibcon#read 5, iclass 36, count 0 2006.197.07:20:17.34#ibcon#about to read 6, iclass 36, count 0 2006.197.07:20:17.34#ibcon#read 6, iclass 36, count 0 2006.197.07:20:17.34#ibcon#end of sib2, iclass 36, count 0 2006.197.07:20:17.34#ibcon#*mode == 0, iclass 36, count 0 2006.197.07:20:17.34#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.197.07:20:17.34#ibcon#[26=FRQ=06,772.99\r\n] 2006.197.07:20:17.34#ibcon#*before write, iclass 36, count 0 2006.197.07:20:17.34#ibcon#enter sib2, iclass 36, count 0 2006.197.07:20:17.34#ibcon#flushed, iclass 36, count 0 2006.197.07:20:17.34#ibcon#about to write, iclass 36, count 0 2006.197.07:20:17.34#ibcon#wrote, iclass 36, count 0 2006.197.07:20:17.34#ibcon#about to read 3, iclass 36, count 0 2006.197.07:20:17.38#ibcon#read 3, iclass 36, count 0 2006.197.07:20:17.38#ibcon#about to read 4, iclass 36, count 0 2006.197.07:20:17.38#ibcon#read 4, iclass 36, count 0 2006.197.07:20:17.38#ibcon#about to read 5, iclass 36, count 0 2006.197.07:20:17.38#ibcon#read 5, iclass 36, count 0 2006.197.07:20:17.38#ibcon#about to read 6, iclass 36, count 0 2006.197.07:20:17.38#ibcon#read 6, iclass 36, count 0 2006.197.07:20:17.38#ibcon#end of sib2, iclass 36, count 0 2006.197.07:20:17.38#ibcon#*after write, iclass 36, count 0 2006.197.07:20:17.38#ibcon#*before return 0, iclass 36, count 0 2006.197.07:20:17.38#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.197.07:20:17.38#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.197.07:20:17.38#ibcon#about to clear, iclass 36 cls_cnt 0 2006.197.07:20:17.38#ibcon#cleared, iclass 36 cls_cnt 0 2006.197.07:20:17.38$vc4f8/va=6,6 2006.197.07:20:17.38#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.197.07:20:17.38#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.197.07:20:17.38#ibcon#ireg 11 cls_cnt 2 2006.197.07:20:17.38#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.197.07:20:17.44#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.197.07:20:17.44#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.197.07:20:17.44#ibcon#enter wrdev, iclass 38, count 2 2006.197.07:20:17.44#ibcon#first serial, iclass 38, count 2 2006.197.07:20:17.44#ibcon#enter sib2, iclass 38, count 2 2006.197.07:20:17.44#ibcon#flushed, iclass 38, count 2 2006.197.07:20:17.44#ibcon#about to write, iclass 38, count 2 2006.197.07:20:17.44#ibcon#wrote, iclass 38, count 2 2006.197.07:20:17.44#ibcon#about to read 3, iclass 38, count 2 2006.197.07:20:17.46#ibcon#read 3, iclass 38, count 2 2006.197.07:20:17.46#ibcon#about to read 4, iclass 38, count 2 2006.197.07:20:17.46#ibcon#read 4, iclass 38, count 2 2006.197.07:20:17.46#ibcon#about to read 5, iclass 38, count 2 2006.197.07:20:17.46#ibcon#read 5, iclass 38, count 2 2006.197.07:20:17.46#ibcon#about to read 6, iclass 38, count 2 2006.197.07:20:17.46#ibcon#read 6, iclass 38, count 2 2006.197.07:20:17.46#ibcon#end of sib2, iclass 38, count 2 2006.197.07:20:17.46#ibcon#*mode == 0, iclass 38, count 2 2006.197.07:20:17.46#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.197.07:20:17.46#ibcon#[25=AT06-06\r\n] 2006.197.07:20:17.46#ibcon#*before write, iclass 38, count 2 2006.197.07:20:17.46#ibcon#enter sib2, iclass 38, count 2 2006.197.07:20:17.46#ibcon#flushed, iclass 38, count 2 2006.197.07:20:17.46#ibcon#about to write, iclass 38, count 2 2006.197.07:20:17.46#ibcon#wrote, iclass 38, count 2 2006.197.07:20:17.46#ibcon#about to read 3, iclass 38, count 2 2006.197.07:20:17.49#ibcon#read 3, iclass 38, count 2 2006.197.07:20:17.49#ibcon#about to read 4, iclass 38, count 2 2006.197.07:20:17.49#ibcon#read 4, iclass 38, count 2 2006.197.07:20:17.49#ibcon#about to read 5, iclass 38, count 2 2006.197.07:20:17.49#ibcon#read 5, iclass 38, count 2 2006.197.07:20:17.49#ibcon#about to read 6, iclass 38, count 2 2006.197.07:20:17.49#ibcon#read 6, iclass 38, count 2 2006.197.07:20:17.49#ibcon#end of sib2, iclass 38, count 2 2006.197.07:20:17.49#ibcon#*after write, iclass 38, count 2 2006.197.07:20:17.49#ibcon#*before return 0, iclass 38, count 2 2006.197.07:20:17.49#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.197.07:20:17.49#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.197.07:20:17.49#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.197.07:20:17.49#ibcon#ireg 7 cls_cnt 0 2006.197.07:20:17.49#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.197.07:20:17.61#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.197.07:20:17.61#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.197.07:20:17.61#ibcon#enter wrdev, iclass 38, count 0 2006.197.07:20:17.61#ibcon#first serial, iclass 38, count 0 2006.197.07:20:17.61#ibcon#enter sib2, iclass 38, count 0 2006.197.07:20:17.61#ibcon#flushed, iclass 38, count 0 2006.197.07:20:17.61#ibcon#about to write, iclass 38, count 0 2006.197.07:20:17.61#ibcon#wrote, iclass 38, count 0 2006.197.07:20:17.61#ibcon#about to read 3, iclass 38, count 0 2006.197.07:20:17.63#ibcon#read 3, iclass 38, count 0 2006.197.07:20:17.63#ibcon#about to read 4, iclass 38, count 0 2006.197.07:20:17.63#ibcon#read 4, iclass 38, count 0 2006.197.07:20:17.63#ibcon#about to read 5, iclass 38, count 0 2006.197.07:20:17.63#ibcon#read 5, iclass 38, count 0 2006.197.07:20:17.63#ibcon#about to read 6, iclass 38, count 0 2006.197.07:20:17.63#ibcon#read 6, iclass 38, count 0 2006.197.07:20:17.63#ibcon#end of sib2, iclass 38, count 0 2006.197.07:20:17.63#ibcon#*mode == 0, iclass 38, count 0 2006.197.07:20:17.63#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.197.07:20:17.63#ibcon#[25=USB\r\n] 2006.197.07:20:17.63#ibcon#*before write, iclass 38, count 0 2006.197.07:20:17.63#ibcon#enter sib2, iclass 38, count 0 2006.197.07:20:17.63#ibcon#flushed, iclass 38, count 0 2006.197.07:20:17.63#ibcon#about to write, iclass 38, count 0 2006.197.07:20:17.63#ibcon#wrote, iclass 38, count 0 2006.197.07:20:17.63#ibcon#about to read 3, iclass 38, count 0 2006.197.07:20:17.66#ibcon#read 3, iclass 38, count 0 2006.197.07:20:17.66#ibcon#about to read 4, iclass 38, count 0 2006.197.07:20:17.66#ibcon#read 4, iclass 38, count 0 2006.197.07:20:17.66#ibcon#about to read 5, iclass 38, count 0 2006.197.07:20:17.66#ibcon#read 5, iclass 38, count 0 2006.197.07:20:17.66#ibcon#about to read 6, iclass 38, count 0 2006.197.07:20:17.66#ibcon#read 6, iclass 38, count 0 2006.197.07:20:17.66#ibcon#end of sib2, iclass 38, count 0 2006.197.07:20:17.66#ibcon#*after write, iclass 38, count 0 2006.197.07:20:17.66#ibcon#*before return 0, iclass 38, count 0 2006.197.07:20:17.66#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.197.07:20:17.66#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.197.07:20:17.66#ibcon#about to clear, iclass 38 cls_cnt 0 2006.197.07:20:17.66#ibcon#cleared, iclass 38 cls_cnt 0 2006.197.07:20:17.66$vc4f8/valo=7,832.99 2006.197.07:20:17.66#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.197.07:20:17.66#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.197.07:20:17.66#ibcon#ireg 17 cls_cnt 0 2006.197.07:20:17.66#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.197.07:20:17.66#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.197.07:20:17.66#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.197.07:20:17.66#ibcon#enter wrdev, iclass 40, count 0 2006.197.07:20:17.66#ibcon#first serial, iclass 40, count 0 2006.197.07:20:17.66#ibcon#enter sib2, iclass 40, count 0 2006.197.07:20:17.66#ibcon#flushed, iclass 40, count 0 2006.197.07:20:17.66#ibcon#about to write, iclass 40, count 0 2006.197.07:20:17.66#ibcon#wrote, iclass 40, count 0 2006.197.07:20:17.66#ibcon#about to read 3, iclass 40, count 0 2006.197.07:20:17.68#ibcon#read 3, iclass 40, count 0 2006.197.07:20:17.68#ibcon#about to read 4, iclass 40, count 0 2006.197.07:20:17.68#ibcon#read 4, iclass 40, count 0 2006.197.07:20:17.68#ibcon#about to read 5, iclass 40, count 0 2006.197.07:20:17.68#ibcon#read 5, iclass 40, count 0 2006.197.07:20:17.68#ibcon#about to read 6, iclass 40, count 0 2006.197.07:20:17.68#ibcon#read 6, iclass 40, count 0 2006.197.07:20:17.68#ibcon#end of sib2, iclass 40, count 0 2006.197.07:20:17.68#ibcon#*mode == 0, iclass 40, count 0 2006.197.07:20:17.68#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.197.07:20:17.68#ibcon#[26=FRQ=07,832.99\r\n] 2006.197.07:20:17.68#ibcon#*before write, iclass 40, count 0 2006.197.07:20:17.68#ibcon#enter sib2, iclass 40, count 0 2006.197.07:20:17.68#ibcon#flushed, iclass 40, count 0 2006.197.07:20:17.68#ibcon#about to write, iclass 40, count 0 2006.197.07:20:17.68#ibcon#wrote, iclass 40, count 0 2006.197.07:20:17.68#ibcon#about to read 3, iclass 40, count 0 2006.197.07:20:17.72#ibcon#read 3, iclass 40, count 0 2006.197.07:20:17.72#ibcon#about to read 4, iclass 40, count 0 2006.197.07:20:17.72#ibcon#read 4, iclass 40, count 0 2006.197.07:20:17.72#ibcon#about to read 5, iclass 40, count 0 2006.197.07:20:17.72#ibcon#read 5, iclass 40, count 0 2006.197.07:20:17.72#ibcon#about to read 6, iclass 40, count 0 2006.197.07:20:17.72#ibcon#read 6, iclass 40, count 0 2006.197.07:20:17.72#ibcon#end of sib2, iclass 40, count 0 2006.197.07:20:17.72#ibcon#*after write, iclass 40, count 0 2006.197.07:20:17.72#ibcon#*before return 0, iclass 40, count 0 2006.197.07:20:17.72#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.197.07:20:17.72#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.197.07:20:17.72#ibcon#about to clear, iclass 40 cls_cnt 0 2006.197.07:20:17.72#ibcon#cleared, iclass 40 cls_cnt 0 2006.197.07:20:17.72$vc4f8/va=7,6 2006.197.07:20:17.72#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.197.07:20:17.72#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.197.07:20:17.72#ibcon#ireg 11 cls_cnt 2 2006.197.07:20:17.72#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.197.07:20:17.78#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.197.07:20:17.78#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.197.07:20:17.78#ibcon#enter wrdev, iclass 4, count 2 2006.197.07:20:17.78#ibcon#first serial, iclass 4, count 2 2006.197.07:20:17.78#ibcon#enter sib2, iclass 4, count 2 2006.197.07:20:17.78#ibcon#flushed, iclass 4, count 2 2006.197.07:20:17.78#ibcon#about to write, iclass 4, count 2 2006.197.07:20:17.78#ibcon#wrote, iclass 4, count 2 2006.197.07:20:17.78#ibcon#about to read 3, iclass 4, count 2 2006.197.07:20:17.80#ibcon#read 3, iclass 4, count 2 2006.197.07:20:17.80#ibcon#about to read 4, iclass 4, count 2 2006.197.07:20:17.80#ibcon#read 4, iclass 4, count 2 2006.197.07:20:17.80#ibcon#about to read 5, iclass 4, count 2 2006.197.07:20:17.80#ibcon#read 5, iclass 4, count 2 2006.197.07:20:17.80#ibcon#about to read 6, iclass 4, count 2 2006.197.07:20:17.80#ibcon#read 6, iclass 4, count 2 2006.197.07:20:17.80#ibcon#end of sib2, iclass 4, count 2 2006.197.07:20:17.80#ibcon#*mode == 0, iclass 4, count 2 2006.197.07:20:17.80#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.197.07:20:17.80#ibcon#[25=AT07-06\r\n] 2006.197.07:20:17.80#ibcon#*before write, iclass 4, count 2 2006.197.07:20:17.80#ibcon#enter sib2, iclass 4, count 2 2006.197.07:20:17.80#ibcon#flushed, iclass 4, count 2 2006.197.07:20:17.80#ibcon#about to write, iclass 4, count 2 2006.197.07:20:17.80#ibcon#wrote, iclass 4, count 2 2006.197.07:20:17.80#ibcon#about to read 3, iclass 4, count 2 2006.197.07:20:17.83#ibcon#read 3, iclass 4, count 2 2006.197.07:20:17.83#ibcon#about to read 4, iclass 4, count 2 2006.197.07:20:17.83#ibcon#read 4, iclass 4, count 2 2006.197.07:20:17.83#ibcon#about to read 5, iclass 4, count 2 2006.197.07:20:17.83#ibcon#read 5, iclass 4, count 2 2006.197.07:20:17.83#ibcon#about to read 6, iclass 4, count 2 2006.197.07:20:17.83#ibcon#read 6, iclass 4, count 2 2006.197.07:20:17.83#ibcon#end of sib2, iclass 4, count 2 2006.197.07:20:17.83#ibcon#*after write, iclass 4, count 2 2006.197.07:20:17.83#ibcon#*before return 0, iclass 4, count 2 2006.197.07:20:17.83#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.197.07:20:17.83#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.197.07:20:17.83#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.197.07:20:17.83#ibcon#ireg 7 cls_cnt 0 2006.197.07:20:17.83#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.197.07:20:17.95#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.197.07:20:17.95#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.197.07:20:17.95#ibcon#enter wrdev, iclass 4, count 0 2006.197.07:20:17.95#ibcon#first serial, iclass 4, count 0 2006.197.07:20:17.95#ibcon#enter sib2, iclass 4, count 0 2006.197.07:20:17.95#ibcon#flushed, iclass 4, count 0 2006.197.07:20:17.95#ibcon#about to write, iclass 4, count 0 2006.197.07:20:17.95#ibcon#wrote, iclass 4, count 0 2006.197.07:20:17.95#ibcon#about to read 3, iclass 4, count 0 2006.197.07:20:17.97#ibcon#read 3, iclass 4, count 0 2006.197.07:20:17.97#ibcon#about to read 4, iclass 4, count 0 2006.197.07:20:17.97#ibcon#read 4, iclass 4, count 0 2006.197.07:20:17.97#ibcon#about to read 5, iclass 4, count 0 2006.197.07:20:17.97#ibcon#read 5, iclass 4, count 0 2006.197.07:20:17.97#ibcon#about to read 6, iclass 4, count 0 2006.197.07:20:17.97#ibcon#read 6, iclass 4, count 0 2006.197.07:20:17.97#ibcon#end of sib2, iclass 4, count 0 2006.197.07:20:17.97#ibcon#*mode == 0, iclass 4, count 0 2006.197.07:20:17.97#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.197.07:20:17.97#ibcon#[25=USB\r\n] 2006.197.07:20:17.97#ibcon#*before write, iclass 4, count 0 2006.197.07:20:17.97#ibcon#enter sib2, iclass 4, count 0 2006.197.07:20:17.97#ibcon#flushed, iclass 4, count 0 2006.197.07:20:17.97#ibcon#about to write, iclass 4, count 0 2006.197.07:20:17.97#ibcon#wrote, iclass 4, count 0 2006.197.07:20:17.97#ibcon#about to read 3, iclass 4, count 0 2006.197.07:20:18.00#ibcon#read 3, iclass 4, count 0 2006.197.07:20:18.00#ibcon#about to read 4, iclass 4, count 0 2006.197.07:20:18.00#ibcon#read 4, iclass 4, count 0 2006.197.07:20:18.00#ibcon#about to read 5, iclass 4, count 0 2006.197.07:20:18.00#ibcon#read 5, iclass 4, count 0 2006.197.07:20:18.00#ibcon#about to read 6, iclass 4, count 0 2006.197.07:20:18.00#ibcon#read 6, iclass 4, count 0 2006.197.07:20:18.00#ibcon#end of sib2, iclass 4, count 0 2006.197.07:20:18.00#ibcon#*after write, iclass 4, count 0 2006.197.07:20:18.00#ibcon#*before return 0, iclass 4, count 0 2006.197.07:20:18.00#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.197.07:20:18.00#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.197.07:20:18.00#ibcon#about to clear, iclass 4 cls_cnt 0 2006.197.07:20:18.00#ibcon#cleared, iclass 4 cls_cnt 0 2006.197.07:20:18.00$vc4f8/valo=8,852.99 2006.197.07:20:18.00#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.197.07:20:18.00#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.197.07:20:18.00#ibcon#ireg 17 cls_cnt 0 2006.197.07:20:18.00#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.197.07:20:18.00#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.197.07:20:18.00#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.197.07:20:18.00#ibcon#enter wrdev, iclass 6, count 0 2006.197.07:20:18.00#ibcon#first serial, iclass 6, count 0 2006.197.07:20:18.00#ibcon#enter sib2, iclass 6, count 0 2006.197.07:20:18.00#ibcon#flushed, iclass 6, count 0 2006.197.07:20:18.00#ibcon#about to write, iclass 6, count 0 2006.197.07:20:18.00#ibcon#wrote, iclass 6, count 0 2006.197.07:20:18.00#ibcon#about to read 3, iclass 6, count 0 2006.197.07:20:18.02#ibcon#read 3, iclass 6, count 0 2006.197.07:20:18.02#ibcon#about to read 4, iclass 6, count 0 2006.197.07:20:18.02#ibcon#read 4, iclass 6, count 0 2006.197.07:20:18.02#ibcon#about to read 5, iclass 6, count 0 2006.197.07:20:18.02#ibcon#read 5, iclass 6, count 0 2006.197.07:20:18.02#ibcon#about to read 6, iclass 6, count 0 2006.197.07:20:18.02#ibcon#read 6, iclass 6, count 0 2006.197.07:20:18.02#ibcon#end of sib2, iclass 6, count 0 2006.197.07:20:18.02#ibcon#*mode == 0, iclass 6, count 0 2006.197.07:20:18.02#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.197.07:20:18.02#ibcon#[26=FRQ=08,852.99\r\n] 2006.197.07:20:18.02#ibcon#*before write, iclass 6, count 0 2006.197.07:20:18.02#ibcon#enter sib2, iclass 6, count 0 2006.197.07:20:18.02#ibcon#flushed, iclass 6, count 0 2006.197.07:20:18.02#ibcon#about to write, iclass 6, count 0 2006.197.07:20:18.02#ibcon#wrote, iclass 6, count 0 2006.197.07:20:18.02#ibcon#about to read 3, iclass 6, count 0 2006.197.07:20:18.06#ibcon#read 3, iclass 6, count 0 2006.197.07:20:18.06#ibcon#about to read 4, iclass 6, count 0 2006.197.07:20:18.06#ibcon#read 4, iclass 6, count 0 2006.197.07:20:18.06#ibcon#about to read 5, iclass 6, count 0 2006.197.07:20:18.06#ibcon#read 5, iclass 6, count 0 2006.197.07:20:18.06#ibcon#about to read 6, iclass 6, count 0 2006.197.07:20:18.06#ibcon#read 6, iclass 6, count 0 2006.197.07:20:18.06#ibcon#end of sib2, iclass 6, count 0 2006.197.07:20:18.06#ibcon#*after write, iclass 6, count 0 2006.197.07:20:18.06#ibcon#*before return 0, iclass 6, count 0 2006.197.07:20:18.06#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.197.07:20:18.06#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.197.07:20:18.06#ibcon#about to clear, iclass 6 cls_cnt 0 2006.197.07:20:18.06#ibcon#cleared, iclass 6 cls_cnt 0 2006.197.07:20:18.06$vc4f8/va=8,7 2006.197.07:20:18.06#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.197.07:20:18.06#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.197.07:20:18.06#ibcon#ireg 11 cls_cnt 2 2006.197.07:20:18.06#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.197.07:20:18.12#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.197.07:20:18.12#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.197.07:20:18.12#ibcon#enter wrdev, iclass 10, count 2 2006.197.07:20:18.12#ibcon#first serial, iclass 10, count 2 2006.197.07:20:18.12#ibcon#enter sib2, iclass 10, count 2 2006.197.07:20:18.12#ibcon#flushed, iclass 10, count 2 2006.197.07:20:18.12#ibcon#about to write, iclass 10, count 2 2006.197.07:20:18.12#ibcon#wrote, iclass 10, count 2 2006.197.07:20:18.12#ibcon#about to read 3, iclass 10, count 2 2006.197.07:20:18.14#ibcon#read 3, iclass 10, count 2 2006.197.07:20:18.14#ibcon#about to read 4, iclass 10, count 2 2006.197.07:20:18.14#ibcon#read 4, iclass 10, count 2 2006.197.07:20:18.14#ibcon#about to read 5, iclass 10, count 2 2006.197.07:20:18.14#ibcon#read 5, iclass 10, count 2 2006.197.07:20:18.14#ibcon#about to read 6, iclass 10, count 2 2006.197.07:20:18.14#ibcon#read 6, iclass 10, count 2 2006.197.07:20:18.14#ibcon#end of sib2, iclass 10, count 2 2006.197.07:20:18.14#ibcon#*mode == 0, iclass 10, count 2 2006.197.07:20:18.14#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.197.07:20:18.14#ibcon#[25=AT08-07\r\n] 2006.197.07:20:18.14#ibcon#*before write, iclass 10, count 2 2006.197.07:20:18.14#ibcon#enter sib2, iclass 10, count 2 2006.197.07:20:18.14#ibcon#flushed, iclass 10, count 2 2006.197.07:20:18.14#ibcon#about to write, iclass 10, count 2 2006.197.07:20:18.14#ibcon#wrote, iclass 10, count 2 2006.197.07:20:18.14#ibcon#about to read 3, iclass 10, count 2 2006.197.07:20:18.17#ibcon#read 3, iclass 10, count 2 2006.197.07:20:18.17#ibcon#about to read 4, iclass 10, count 2 2006.197.07:20:18.17#ibcon#read 4, iclass 10, count 2 2006.197.07:20:18.17#ibcon#about to read 5, iclass 10, count 2 2006.197.07:20:18.17#ibcon#read 5, iclass 10, count 2 2006.197.07:20:18.17#ibcon#about to read 6, iclass 10, count 2 2006.197.07:20:18.17#ibcon#read 6, iclass 10, count 2 2006.197.07:20:18.17#ibcon#end of sib2, iclass 10, count 2 2006.197.07:20:18.17#ibcon#*after write, iclass 10, count 2 2006.197.07:20:18.17#ibcon#*before return 0, iclass 10, count 2 2006.197.07:20:18.17#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.197.07:20:18.17#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.197.07:20:18.17#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.197.07:20:18.17#ibcon#ireg 7 cls_cnt 0 2006.197.07:20:18.17#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.197.07:20:18.29#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.197.07:20:18.29#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.197.07:20:18.29#ibcon#enter wrdev, iclass 10, count 0 2006.197.07:20:18.29#ibcon#first serial, iclass 10, count 0 2006.197.07:20:18.29#ibcon#enter sib2, iclass 10, count 0 2006.197.07:20:18.29#ibcon#flushed, iclass 10, count 0 2006.197.07:20:18.29#ibcon#about to write, iclass 10, count 0 2006.197.07:20:18.29#ibcon#wrote, iclass 10, count 0 2006.197.07:20:18.29#ibcon#about to read 3, iclass 10, count 0 2006.197.07:20:18.31#ibcon#read 3, iclass 10, count 0 2006.197.07:20:18.31#ibcon#about to read 4, iclass 10, count 0 2006.197.07:20:18.31#ibcon#read 4, iclass 10, count 0 2006.197.07:20:18.31#ibcon#about to read 5, iclass 10, count 0 2006.197.07:20:18.31#ibcon#read 5, iclass 10, count 0 2006.197.07:20:18.31#ibcon#about to read 6, iclass 10, count 0 2006.197.07:20:18.31#ibcon#read 6, iclass 10, count 0 2006.197.07:20:18.31#ibcon#end of sib2, iclass 10, count 0 2006.197.07:20:18.31#ibcon#*mode == 0, iclass 10, count 0 2006.197.07:20:18.31#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.197.07:20:18.31#ibcon#[25=USB\r\n] 2006.197.07:20:18.31#ibcon#*before write, iclass 10, count 0 2006.197.07:20:18.31#ibcon#enter sib2, iclass 10, count 0 2006.197.07:20:18.31#ibcon#flushed, iclass 10, count 0 2006.197.07:20:18.31#ibcon#about to write, iclass 10, count 0 2006.197.07:20:18.31#ibcon#wrote, iclass 10, count 0 2006.197.07:20:18.31#ibcon#about to read 3, iclass 10, count 0 2006.197.07:20:18.34#ibcon#read 3, iclass 10, count 0 2006.197.07:20:18.34#ibcon#about to read 4, iclass 10, count 0 2006.197.07:20:18.34#ibcon#read 4, iclass 10, count 0 2006.197.07:20:18.34#ibcon#about to read 5, iclass 10, count 0 2006.197.07:20:18.34#ibcon#read 5, iclass 10, count 0 2006.197.07:20:18.34#ibcon#about to read 6, iclass 10, count 0 2006.197.07:20:18.34#ibcon#read 6, iclass 10, count 0 2006.197.07:20:18.34#ibcon#end of sib2, iclass 10, count 0 2006.197.07:20:18.34#ibcon#*after write, iclass 10, count 0 2006.197.07:20:18.34#ibcon#*before return 0, iclass 10, count 0 2006.197.07:20:18.34#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.197.07:20:18.34#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.197.07:20:18.34#ibcon#about to clear, iclass 10 cls_cnt 0 2006.197.07:20:18.34#ibcon#cleared, iclass 10 cls_cnt 0 2006.197.07:20:18.34$vc4f8/vblo=1,632.99 2006.197.07:20:18.34#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.197.07:20:18.34#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.197.07:20:18.34#ibcon#ireg 17 cls_cnt 0 2006.197.07:20:18.34#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.197.07:20:18.34#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.197.07:20:18.34#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.197.07:20:18.34#ibcon#enter wrdev, iclass 12, count 0 2006.197.07:20:18.34#ibcon#first serial, iclass 12, count 0 2006.197.07:20:18.34#ibcon#enter sib2, iclass 12, count 0 2006.197.07:20:18.34#ibcon#flushed, iclass 12, count 0 2006.197.07:20:18.34#ibcon#about to write, iclass 12, count 0 2006.197.07:20:18.34#ibcon#wrote, iclass 12, count 0 2006.197.07:20:18.34#ibcon#about to read 3, iclass 12, count 0 2006.197.07:20:18.36#ibcon#read 3, iclass 12, count 0 2006.197.07:20:18.36#ibcon#about to read 4, iclass 12, count 0 2006.197.07:20:18.36#ibcon#read 4, iclass 12, count 0 2006.197.07:20:18.36#ibcon#about to read 5, iclass 12, count 0 2006.197.07:20:18.36#ibcon#read 5, iclass 12, count 0 2006.197.07:20:18.36#ibcon#about to read 6, iclass 12, count 0 2006.197.07:20:18.36#ibcon#read 6, iclass 12, count 0 2006.197.07:20:18.36#ibcon#end of sib2, iclass 12, count 0 2006.197.07:20:18.36#ibcon#*mode == 0, iclass 12, count 0 2006.197.07:20:18.36#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.197.07:20:18.36#ibcon#[28=FRQ=01,632.99\r\n] 2006.197.07:20:18.36#ibcon#*before write, iclass 12, count 0 2006.197.07:20:18.36#ibcon#enter sib2, iclass 12, count 0 2006.197.07:20:18.36#ibcon#flushed, iclass 12, count 0 2006.197.07:20:18.36#ibcon#about to write, iclass 12, count 0 2006.197.07:20:18.36#ibcon#wrote, iclass 12, count 0 2006.197.07:20:18.36#ibcon#about to read 3, iclass 12, count 0 2006.197.07:20:18.40#ibcon#read 3, iclass 12, count 0 2006.197.07:20:18.40#ibcon#about to read 4, iclass 12, count 0 2006.197.07:20:18.40#ibcon#read 4, iclass 12, count 0 2006.197.07:20:18.40#ibcon#about to read 5, iclass 12, count 0 2006.197.07:20:18.40#ibcon#read 5, iclass 12, count 0 2006.197.07:20:18.40#ibcon#about to read 6, iclass 12, count 0 2006.197.07:20:18.40#ibcon#read 6, iclass 12, count 0 2006.197.07:20:18.40#ibcon#end of sib2, iclass 12, count 0 2006.197.07:20:18.40#ibcon#*after write, iclass 12, count 0 2006.197.07:20:18.40#ibcon#*before return 0, iclass 12, count 0 2006.197.07:20:18.40#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.197.07:20:18.40#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.197.07:20:18.40#ibcon#about to clear, iclass 12 cls_cnt 0 2006.197.07:20:18.40#ibcon#cleared, iclass 12 cls_cnt 0 2006.197.07:20:18.40$vc4f8/vb=1,4 2006.197.07:20:18.40#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.197.07:20:18.40#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.197.07:20:18.40#ibcon#ireg 11 cls_cnt 2 2006.197.07:20:18.40#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.197.07:20:18.40#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.197.07:20:18.40#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.197.07:20:18.40#ibcon#enter wrdev, iclass 14, count 2 2006.197.07:20:18.40#ibcon#first serial, iclass 14, count 2 2006.197.07:20:18.40#ibcon#enter sib2, iclass 14, count 2 2006.197.07:20:18.40#ibcon#flushed, iclass 14, count 2 2006.197.07:20:18.40#ibcon#about to write, iclass 14, count 2 2006.197.07:20:18.40#ibcon#wrote, iclass 14, count 2 2006.197.07:20:18.40#ibcon#about to read 3, iclass 14, count 2 2006.197.07:20:18.42#ibcon#read 3, iclass 14, count 2 2006.197.07:20:18.42#ibcon#about to read 4, iclass 14, count 2 2006.197.07:20:18.42#ibcon#read 4, iclass 14, count 2 2006.197.07:20:18.42#ibcon#about to read 5, iclass 14, count 2 2006.197.07:20:18.42#ibcon#read 5, iclass 14, count 2 2006.197.07:20:18.42#ibcon#about to read 6, iclass 14, count 2 2006.197.07:20:18.42#ibcon#read 6, iclass 14, count 2 2006.197.07:20:18.42#ibcon#end of sib2, iclass 14, count 2 2006.197.07:20:18.42#ibcon#*mode == 0, iclass 14, count 2 2006.197.07:20:18.42#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.197.07:20:18.42#ibcon#[27=AT01-04\r\n] 2006.197.07:20:18.42#ibcon#*before write, iclass 14, count 2 2006.197.07:20:18.42#ibcon#enter sib2, iclass 14, count 2 2006.197.07:20:18.42#ibcon#flushed, iclass 14, count 2 2006.197.07:20:18.42#ibcon#about to write, iclass 14, count 2 2006.197.07:20:18.42#ibcon#wrote, iclass 14, count 2 2006.197.07:20:18.42#ibcon#about to read 3, iclass 14, count 2 2006.197.07:20:18.45#ibcon#read 3, iclass 14, count 2 2006.197.07:20:18.45#ibcon#about to read 4, iclass 14, count 2 2006.197.07:20:18.45#ibcon#read 4, iclass 14, count 2 2006.197.07:20:18.45#ibcon#about to read 5, iclass 14, count 2 2006.197.07:20:18.45#ibcon#read 5, iclass 14, count 2 2006.197.07:20:18.45#ibcon#about to read 6, iclass 14, count 2 2006.197.07:20:18.45#ibcon#read 6, iclass 14, count 2 2006.197.07:20:18.45#ibcon#end of sib2, iclass 14, count 2 2006.197.07:20:18.45#ibcon#*after write, iclass 14, count 2 2006.197.07:20:18.45#ibcon#*before return 0, iclass 14, count 2 2006.197.07:20:18.45#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.197.07:20:18.45#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.197.07:20:18.45#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.197.07:20:18.45#ibcon#ireg 7 cls_cnt 0 2006.197.07:20:18.45#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.197.07:20:18.57#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.197.07:20:18.57#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.197.07:20:18.57#ibcon#enter wrdev, iclass 14, count 0 2006.197.07:20:18.57#ibcon#first serial, iclass 14, count 0 2006.197.07:20:18.57#ibcon#enter sib2, iclass 14, count 0 2006.197.07:20:18.57#ibcon#flushed, iclass 14, count 0 2006.197.07:20:18.57#ibcon#about to write, iclass 14, count 0 2006.197.07:20:18.57#ibcon#wrote, iclass 14, count 0 2006.197.07:20:18.57#ibcon#about to read 3, iclass 14, count 0 2006.197.07:20:18.59#ibcon#read 3, iclass 14, count 0 2006.197.07:20:18.59#ibcon#about to read 4, iclass 14, count 0 2006.197.07:20:18.59#ibcon#read 4, iclass 14, count 0 2006.197.07:20:18.59#ibcon#about to read 5, iclass 14, count 0 2006.197.07:20:18.59#ibcon#read 5, iclass 14, count 0 2006.197.07:20:18.59#ibcon#about to read 6, iclass 14, count 0 2006.197.07:20:18.59#ibcon#read 6, iclass 14, count 0 2006.197.07:20:18.59#ibcon#end of sib2, iclass 14, count 0 2006.197.07:20:18.59#ibcon#*mode == 0, iclass 14, count 0 2006.197.07:20:18.59#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.197.07:20:18.59#ibcon#[27=USB\r\n] 2006.197.07:20:18.59#ibcon#*before write, iclass 14, count 0 2006.197.07:20:18.59#ibcon#enter sib2, iclass 14, count 0 2006.197.07:20:18.59#ibcon#flushed, iclass 14, count 0 2006.197.07:20:18.59#ibcon#about to write, iclass 14, count 0 2006.197.07:20:18.59#ibcon#wrote, iclass 14, count 0 2006.197.07:20:18.59#ibcon#about to read 3, iclass 14, count 0 2006.197.07:20:18.62#ibcon#read 3, iclass 14, count 0 2006.197.07:20:18.62#ibcon#about to read 4, iclass 14, count 0 2006.197.07:20:18.62#ibcon#read 4, iclass 14, count 0 2006.197.07:20:18.62#ibcon#about to read 5, iclass 14, count 0 2006.197.07:20:18.62#ibcon#read 5, iclass 14, count 0 2006.197.07:20:18.62#ibcon#about to read 6, iclass 14, count 0 2006.197.07:20:18.62#ibcon#read 6, iclass 14, count 0 2006.197.07:20:18.62#ibcon#end of sib2, iclass 14, count 0 2006.197.07:20:18.62#ibcon#*after write, iclass 14, count 0 2006.197.07:20:18.62#ibcon#*before return 0, iclass 14, count 0 2006.197.07:20:18.62#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.197.07:20:18.62#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.197.07:20:18.62#ibcon#about to clear, iclass 14 cls_cnt 0 2006.197.07:20:18.62#ibcon#cleared, iclass 14 cls_cnt 0 2006.197.07:20:18.62$vc4f8/vblo=2,640.99 2006.197.07:20:18.62#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.197.07:20:18.62#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.197.07:20:18.62#ibcon#ireg 17 cls_cnt 0 2006.197.07:20:18.62#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.197.07:20:18.62#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.197.07:20:18.62#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.197.07:20:18.62#ibcon#enter wrdev, iclass 16, count 0 2006.197.07:20:18.62#ibcon#first serial, iclass 16, count 0 2006.197.07:20:18.62#ibcon#enter sib2, iclass 16, count 0 2006.197.07:20:18.62#ibcon#flushed, iclass 16, count 0 2006.197.07:20:18.62#ibcon#about to write, iclass 16, count 0 2006.197.07:20:18.62#ibcon#wrote, iclass 16, count 0 2006.197.07:20:18.62#ibcon#about to read 3, iclass 16, count 0 2006.197.07:20:18.64#ibcon#read 3, iclass 16, count 0 2006.197.07:20:18.64#ibcon#about to read 4, iclass 16, count 0 2006.197.07:20:18.64#ibcon#read 4, iclass 16, count 0 2006.197.07:20:18.64#ibcon#about to read 5, iclass 16, count 0 2006.197.07:20:18.64#ibcon#read 5, iclass 16, count 0 2006.197.07:20:18.64#ibcon#about to read 6, iclass 16, count 0 2006.197.07:20:18.64#ibcon#read 6, iclass 16, count 0 2006.197.07:20:18.64#ibcon#end of sib2, iclass 16, count 0 2006.197.07:20:18.64#ibcon#*mode == 0, iclass 16, count 0 2006.197.07:20:18.64#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.197.07:20:18.64#ibcon#[28=FRQ=02,640.99\r\n] 2006.197.07:20:18.64#ibcon#*before write, iclass 16, count 0 2006.197.07:20:18.64#ibcon#enter sib2, iclass 16, count 0 2006.197.07:20:18.64#ibcon#flushed, iclass 16, count 0 2006.197.07:20:18.64#ibcon#about to write, iclass 16, count 0 2006.197.07:20:18.64#ibcon#wrote, iclass 16, count 0 2006.197.07:20:18.64#ibcon#about to read 3, iclass 16, count 0 2006.197.07:20:18.68#ibcon#read 3, iclass 16, count 0 2006.197.07:20:18.68#ibcon#about to read 4, iclass 16, count 0 2006.197.07:20:18.68#ibcon#read 4, iclass 16, count 0 2006.197.07:20:18.68#ibcon#about to read 5, iclass 16, count 0 2006.197.07:20:18.68#ibcon#read 5, iclass 16, count 0 2006.197.07:20:18.68#ibcon#about to read 6, iclass 16, count 0 2006.197.07:20:18.68#ibcon#read 6, iclass 16, count 0 2006.197.07:20:18.68#ibcon#end of sib2, iclass 16, count 0 2006.197.07:20:18.68#ibcon#*after write, iclass 16, count 0 2006.197.07:20:18.68#ibcon#*before return 0, iclass 16, count 0 2006.197.07:20:18.68#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.197.07:20:18.68#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.197.07:20:18.68#ibcon#about to clear, iclass 16 cls_cnt 0 2006.197.07:20:18.68#ibcon#cleared, iclass 16 cls_cnt 0 2006.197.07:20:18.68$vc4f8/vb=2,4 2006.197.07:20:18.68#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.197.07:20:18.68#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.197.07:20:18.68#ibcon#ireg 11 cls_cnt 2 2006.197.07:20:18.68#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.197.07:20:18.74#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.197.07:20:18.74#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.197.07:20:18.74#ibcon#enter wrdev, iclass 18, count 2 2006.197.07:20:18.74#ibcon#first serial, iclass 18, count 2 2006.197.07:20:18.74#ibcon#enter sib2, iclass 18, count 2 2006.197.07:20:18.74#ibcon#flushed, iclass 18, count 2 2006.197.07:20:18.74#ibcon#about to write, iclass 18, count 2 2006.197.07:20:18.74#ibcon#wrote, iclass 18, count 2 2006.197.07:20:18.74#ibcon#about to read 3, iclass 18, count 2 2006.197.07:20:18.76#ibcon#read 3, iclass 18, count 2 2006.197.07:20:18.76#ibcon#about to read 4, iclass 18, count 2 2006.197.07:20:18.76#ibcon#read 4, iclass 18, count 2 2006.197.07:20:18.76#ibcon#about to read 5, iclass 18, count 2 2006.197.07:20:18.76#ibcon#read 5, iclass 18, count 2 2006.197.07:20:18.76#ibcon#about to read 6, iclass 18, count 2 2006.197.07:20:18.76#ibcon#read 6, iclass 18, count 2 2006.197.07:20:18.76#ibcon#end of sib2, iclass 18, count 2 2006.197.07:20:18.76#ibcon#*mode == 0, iclass 18, count 2 2006.197.07:20:18.76#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.197.07:20:18.76#ibcon#[27=AT02-04\r\n] 2006.197.07:20:18.76#ibcon#*before write, iclass 18, count 2 2006.197.07:20:18.76#ibcon#enter sib2, iclass 18, count 2 2006.197.07:20:18.76#ibcon#flushed, iclass 18, count 2 2006.197.07:20:18.76#ibcon#about to write, iclass 18, count 2 2006.197.07:20:18.76#ibcon#wrote, iclass 18, count 2 2006.197.07:20:18.76#ibcon#about to read 3, iclass 18, count 2 2006.197.07:20:18.79#ibcon#read 3, iclass 18, count 2 2006.197.07:20:18.79#ibcon#about to read 4, iclass 18, count 2 2006.197.07:20:18.79#ibcon#read 4, iclass 18, count 2 2006.197.07:20:18.79#ibcon#about to read 5, iclass 18, count 2 2006.197.07:20:18.79#ibcon#read 5, iclass 18, count 2 2006.197.07:20:18.79#ibcon#about to read 6, iclass 18, count 2 2006.197.07:20:18.79#ibcon#read 6, iclass 18, count 2 2006.197.07:20:18.79#ibcon#end of sib2, iclass 18, count 2 2006.197.07:20:18.79#ibcon#*after write, iclass 18, count 2 2006.197.07:20:18.79#ibcon#*before return 0, iclass 18, count 2 2006.197.07:20:18.79#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.197.07:20:18.79#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.197.07:20:18.79#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.197.07:20:18.79#ibcon#ireg 7 cls_cnt 0 2006.197.07:20:18.79#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.197.07:20:18.91#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.197.07:20:18.91#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.197.07:20:18.91#ibcon#enter wrdev, iclass 18, count 0 2006.197.07:20:18.91#ibcon#first serial, iclass 18, count 0 2006.197.07:20:18.91#ibcon#enter sib2, iclass 18, count 0 2006.197.07:20:18.91#ibcon#flushed, iclass 18, count 0 2006.197.07:20:18.91#ibcon#about to write, iclass 18, count 0 2006.197.07:20:18.91#ibcon#wrote, iclass 18, count 0 2006.197.07:20:18.91#ibcon#about to read 3, iclass 18, count 0 2006.197.07:20:18.93#ibcon#read 3, iclass 18, count 0 2006.197.07:20:18.93#ibcon#about to read 4, iclass 18, count 0 2006.197.07:20:18.93#ibcon#read 4, iclass 18, count 0 2006.197.07:20:18.93#ibcon#about to read 5, iclass 18, count 0 2006.197.07:20:18.93#ibcon#read 5, iclass 18, count 0 2006.197.07:20:18.93#ibcon#about to read 6, iclass 18, count 0 2006.197.07:20:18.93#ibcon#read 6, iclass 18, count 0 2006.197.07:20:18.93#ibcon#end of sib2, iclass 18, count 0 2006.197.07:20:18.93#ibcon#*mode == 0, iclass 18, count 0 2006.197.07:20:18.93#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.197.07:20:18.93#ibcon#[27=USB\r\n] 2006.197.07:20:18.93#ibcon#*before write, iclass 18, count 0 2006.197.07:20:18.93#ibcon#enter sib2, iclass 18, count 0 2006.197.07:20:18.93#ibcon#flushed, iclass 18, count 0 2006.197.07:20:18.93#ibcon#about to write, iclass 18, count 0 2006.197.07:20:18.93#ibcon#wrote, iclass 18, count 0 2006.197.07:20:18.93#ibcon#about to read 3, iclass 18, count 0 2006.197.07:20:18.96#ibcon#read 3, iclass 18, count 0 2006.197.07:20:18.96#ibcon#about to read 4, iclass 18, count 0 2006.197.07:20:18.96#ibcon#read 4, iclass 18, count 0 2006.197.07:20:18.96#ibcon#about to read 5, iclass 18, count 0 2006.197.07:20:18.96#ibcon#read 5, iclass 18, count 0 2006.197.07:20:18.96#ibcon#about to read 6, iclass 18, count 0 2006.197.07:20:18.96#ibcon#read 6, iclass 18, count 0 2006.197.07:20:18.96#ibcon#end of sib2, iclass 18, count 0 2006.197.07:20:18.96#ibcon#*after write, iclass 18, count 0 2006.197.07:20:18.96#ibcon#*before return 0, iclass 18, count 0 2006.197.07:20:18.96#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.197.07:20:18.96#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.197.07:20:18.96#ibcon#about to clear, iclass 18 cls_cnt 0 2006.197.07:20:18.96#ibcon#cleared, iclass 18 cls_cnt 0 2006.197.07:20:18.96$vc4f8/vblo=3,656.99 2006.197.07:20:18.96#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.197.07:20:18.96#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.197.07:20:18.96#ibcon#ireg 17 cls_cnt 0 2006.197.07:20:18.96#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.197.07:20:18.96#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.197.07:20:18.96#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.197.07:20:18.96#ibcon#enter wrdev, iclass 20, count 0 2006.197.07:20:18.96#ibcon#first serial, iclass 20, count 0 2006.197.07:20:18.96#ibcon#enter sib2, iclass 20, count 0 2006.197.07:20:18.96#ibcon#flushed, iclass 20, count 0 2006.197.07:20:18.96#ibcon#about to write, iclass 20, count 0 2006.197.07:20:18.96#ibcon#wrote, iclass 20, count 0 2006.197.07:20:18.96#ibcon#about to read 3, iclass 20, count 0 2006.197.07:20:18.98#ibcon#read 3, iclass 20, count 0 2006.197.07:20:18.98#ibcon#about to read 4, iclass 20, count 0 2006.197.07:20:18.98#ibcon#read 4, iclass 20, count 0 2006.197.07:20:18.98#ibcon#about to read 5, iclass 20, count 0 2006.197.07:20:18.98#ibcon#read 5, iclass 20, count 0 2006.197.07:20:18.98#ibcon#about to read 6, iclass 20, count 0 2006.197.07:20:18.98#ibcon#read 6, iclass 20, count 0 2006.197.07:20:18.98#ibcon#end of sib2, iclass 20, count 0 2006.197.07:20:18.98#ibcon#*mode == 0, iclass 20, count 0 2006.197.07:20:18.98#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.197.07:20:18.98#ibcon#[28=FRQ=03,656.99\r\n] 2006.197.07:20:18.98#ibcon#*before write, iclass 20, count 0 2006.197.07:20:18.98#ibcon#enter sib2, iclass 20, count 0 2006.197.07:20:18.98#ibcon#flushed, iclass 20, count 0 2006.197.07:20:18.98#ibcon#about to write, iclass 20, count 0 2006.197.07:20:18.98#ibcon#wrote, iclass 20, count 0 2006.197.07:20:18.98#ibcon#about to read 3, iclass 20, count 0 2006.197.07:20:19.02#ibcon#read 3, iclass 20, count 0 2006.197.07:20:19.02#ibcon#about to read 4, iclass 20, count 0 2006.197.07:20:19.02#ibcon#read 4, iclass 20, count 0 2006.197.07:20:19.02#ibcon#about to read 5, iclass 20, count 0 2006.197.07:20:19.02#ibcon#read 5, iclass 20, count 0 2006.197.07:20:19.02#ibcon#about to read 6, iclass 20, count 0 2006.197.07:20:19.02#ibcon#read 6, iclass 20, count 0 2006.197.07:20:19.02#ibcon#end of sib2, iclass 20, count 0 2006.197.07:20:19.02#ibcon#*after write, iclass 20, count 0 2006.197.07:20:19.02#ibcon#*before return 0, iclass 20, count 0 2006.197.07:20:19.02#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.197.07:20:19.02#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.197.07:20:19.02#ibcon#about to clear, iclass 20 cls_cnt 0 2006.197.07:20:19.02#ibcon#cleared, iclass 20 cls_cnt 0 2006.197.07:20:19.02$vc4f8/vb=3,4 2006.197.07:20:19.02#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.197.07:20:19.02#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.197.07:20:19.02#ibcon#ireg 11 cls_cnt 2 2006.197.07:20:19.02#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.197.07:20:19.08#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.197.07:20:19.08#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.197.07:20:19.08#ibcon#enter wrdev, iclass 22, count 2 2006.197.07:20:19.08#ibcon#first serial, iclass 22, count 2 2006.197.07:20:19.08#ibcon#enter sib2, iclass 22, count 2 2006.197.07:20:19.08#ibcon#flushed, iclass 22, count 2 2006.197.07:20:19.08#ibcon#about to write, iclass 22, count 2 2006.197.07:20:19.08#ibcon#wrote, iclass 22, count 2 2006.197.07:20:19.08#ibcon#about to read 3, iclass 22, count 2 2006.197.07:20:19.10#ibcon#read 3, iclass 22, count 2 2006.197.07:20:19.10#ibcon#about to read 4, iclass 22, count 2 2006.197.07:20:19.10#ibcon#read 4, iclass 22, count 2 2006.197.07:20:19.10#ibcon#about to read 5, iclass 22, count 2 2006.197.07:20:19.10#ibcon#read 5, iclass 22, count 2 2006.197.07:20:19.10#ibcon#about to read 6, iclass 22, count 2 2006.197.07:20:19.10#ibcon#read 6, iclass 22, count 2 2006.197.07:20:19.10#ibcon#end of sib2, iclass 22, count 2 2006.197.07:20:19.10#ibcon#*mode == 0, iclass 22, count 2 2006.197.07:20:19.10#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.197.07:20:19.10#ibcon#[27=AT03-04\r\n] 2006.197.07:20:19.10#ibcon#*before write, iclass 22, count 2 2006.197.07:20:19.10#ibcon#enter sib2, iclass 22, count 2 2006.197.07:20:19.10#ibcon#flushed, iclass 22, count 2 2006.197.07:20:19.10#ibcon#about to write, iclass 22, count 2 2006.197.07:20:19.10#ibcon#wrote, iclass 22, count 2 2006.197.07:20:19.10#ibcon#about to read 3, iclass 22, count 2 2006.197.07:20:19.13#ibcon#read 3, iclass 22, count 2 2006.197.07:20:19.13#ibcon#about to read 4, iclass 22, count 2 2006.197.07:20:19.13#ibcon#read 4, iclass 22, count 2 2006.197.07:20:19.13#ibcon#about to read 5, iclass 22, count 2 2006.197.07:20:19.13#ibcon#read 5, iclass 22, count 2 2006.197.07:20:19.13#ibcon#about to read 6, iclass 22, count 2 2006.197.07:20:19.13#ibcon#read 6, iclass 22, count 2 2006.197.07:20:19.13#ibcon#end of sib2, iclass 22, count 2 2006.197.07:20:19.13#ibcon#*after write, iclass 22, count 2 2006.197.07:20:19.13#ibcon#*before return 0, iclass 22, count 2 2006.197.07:20:19.13#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.197.07:20:19.13#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.197.07:20:19.13#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.197.07:20:19.13#ibcon#ireg 7 cls_cnt 0 2006.197.07:20:19.13#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.197.07:20:19.25#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.197.07:20:19.25#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.197.07:20:19.25#ibcon#enter wrdev, iclass 22, count 0 2006.197.07:20:19.25#ibcon#first serial, iclass 22, count 0 2006.197.07:20:19.25#ibcon#enter sib2, iclass 22, count 0 2006.197.07:20:19.25#ibcon#flushed, iclass 22, count 0 2006.197.07:20:19.25#ibcon#about to write, iclass 22, count 0 2006.197.07:20:19.25#ibcon#wrote, iclass 22, count 0 2006.197.07:20:19.25#ibcon#about to read 3, iclass 22, count 0 2006.197.07:20:19.27#ibcon#read 3, iclass 22, count 0 2006.197.07:20:19.27#ibcon#about to read 4, iclass 22, count 0 2006.197.07:20:19.27#ibcon#read 4, iclass 22, count 0 2006.197.07:20:19.27#ibcon#about to read 5, iclass 22, count 0 2006.197.07:20:19.27#ibcon#read 5, iclass 22, count 0 2006.197.07:20:19.27#ibcon#about to read 6, iclass 22, count 0 2006.197.07:20:19.27#ibcon#read 6, iclass 22, count 0 2006.197.07:20:19.27#ibcon#end of sib2, iclass 22, count 0 2006.197.07:20:19.27#ibcon#*mode == 0, iclass 22, count 0 2006.197.07:20:19.27#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.197.07:20:19.27#ibcon#[27=USB\r\n] 2006.197.07:20:19.27#ibcon#*before write, iclass 22, count 0 2006.197.07:20:19.27#ibcon#enter sib2, iclass 22, count 0 2006.197.07:20:19.27#ibcon#flushed, iclass 22, count 0 2006.197.07:20:19.27#ibcon#about to write, iclass 22, count 0 2006.197.07:20:19.27#ibcon#wrote, iclass 22, count 0 2006.197.07:20:19.27#ibcon#about to read 3, iclass 22, count 0 2006.197.07:20:19.30#ibcon#read 3, iclass 22, count 0 2006.197.07:20:19.30#ibcon#about to read 4, iclass 22, count 0 2006.197.07:20:19.30#ibcon#read 4, iclass 22, count 0 2006.197.07:20:19.30#ibcon#about to read 5, iclass 22, count 0 2006.197.07:20:19.30#ibcon#read 5, iclass 22, count 0 2006.197.07:20:19.30#ibcon#about to read 6, iclass 22, count 0 2006.197.07:20:19.30#ibcon#read 6, iclass 22, count 0 2006.197.07:20:19.30#ibcon#end of sib2, iclass 22, count 0 2006.197.07:20:19.30#ibcon#*after write, iclass 22, count 0 2006.197.07:20:19.30#ibcon#*before return 0, iclass 22, count 0 2006.197.07:20:19.30#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.197.07:20:19.30#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.197.07:20:19.30#ibcon#about to clear, iclass 22 cls_cnt 0 2006.197.07:20:19.30#ibcon#cleared, iclass 22 cls_cnt 0 2006.197.07:20:19.30$vc4f8/vblo=4,712.99 2006.197.07:20:19.30#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.197.07:20:19.30#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.197.07:20:19.30#ibcon#ireg 17 cls_cnt 0 2006.197.07:20:19.30#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.197.07:20:19.30#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.197.07:20:19.30#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.197.07:20:19.30#ibcon#enter wrdev, iclass 24, count 0 2006.197.07:20:19.30#ibcon#first serial, iclass 24, count 0 2006.197.07:20:19.30#ibcon#enter sib2, iclass 24, count 0 2006.197.07:20:19.30#ibcon#flushed, iclass 24, count 0 2006.197.07:20:19.30#ibcon#about to write, iclass 24, count 0 2006.197.07:20:19.30#ibcon#wrote, iclass 24, count 0 2006.197.07:20:19.30#ibcon#about to read 3, iclass 24, count 0 2006.197.07:20:19.32#ibcon#read 3, iclass 24, count 0 2006.197.07:20:19.32#ibcon#about to read 4, iclass 24, count 0 2006.197.07:20:19.32#ibcon#read 4, iclass 24, count 0 2006.197.07:20:19.32#ibcon#about to read 5, iclass 24, count 0 2006.197.07:20:19.32#ibcon#read 5, iclass 24, count 0 2006.197.07:20:19.32#ibcon#about to read 6, iclass 24, count 0 2006.197.07:20:19.32#ibcon#read 6, iclass 24, count 0 2006.197.07:20:19.32#ibcon#end of sib2, iclass 24, count 0 2006.197.07:20:19.32#ibcon#*mode == 0, iclass 24, count 0 2006.197.07:20:19.32#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.197.07:20:19.32#ibcon#[28=FRQ=04,712.99\r\n] 2006.197.07:20:19.32#ibcon#*before write, iclass 24, count 0 2006.197.07:20:19.32#ibcon#enter sib2, iclass 24, count 0 2006.197.07:20:19.32#ibcon#flushed, iclass 24, count 0 2006.197.07:20:19.32#ibcon#about to write, iclass 24, count 0 2006.197.07:20:19.32#ibcon#wrote, iclass 24, count 0 2006.197.07:20:19.32#ibcon#about to read 3, iclass 24, count 0 2006.197.07:20:19.36#ibcon#read 3, iclass 24, count 0 2006.197.07:20:19.36#ibcon#about to read 4, iclass 24, count 0 2006.197.07:20:19.36#ibcon#read 4, iclass 24, count 0 2006.197.07:20:19.36#ibcon#about to read 5, iclass 24, count 0 2006.197.07:20:19.36#ibcon#read 5, iclass 24, count 0 2006.197.07:20:19.36#ibcon#about to read 6, iclass 24, count 0 2006.197.07:20:19.36#ibcon#read 6, iclass 24, count 0 2006.197.07:20:19.36#ibcon#end of sib2, iclass 24, count 0 2006.197.07:20:19.36#ibcon#*after write, iclass 24, count 0 2006.197.07:20:19.36#ibcon#*before return 0, iclass 24, count 0 2006.197.07:20:19.36#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.197.07:20:19.36#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.197.07:20:19.36#ibcon#about to clear, iclass 24 cls_cnt 0 2006.197.07:20:19.36#ibcon#cleared, iclass 24 cls_cnt 0 2006.197.07:20:19.36$vc4f8/vb=4,4 2006.197.07:20:19.36#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.197.07:20:19.36#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.197.07:20:19.36#ibcon#ireg 11 cls_cnt 2 2006.197.07:20:19.36#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.197.07:20:19.42#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.197.07:20:19.42#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.197.07:20:19.42#ibcon#enter wrdev, iclass 26, count 2 2006.197.07:20:19.42#ibcon#first serial, iclass 26, count 2 2006.197.07:20:19.42#ibcon#enter sib2, iclass 26, count 2 2006.197.07:20:19.42#ibcon#flushed, iclass 26, count 2 2006.197.07:20:19.42#ibcon#about to write, iclass 26, count 2 2006.197.07:20:19.42#ibcon#wrote, iclass 26, count 2 2006.197.07:20:19.42#ibcon#about to read 3, iclass 26, count 2 2006.197.07:20:19.44#ibcon#read 3, iclass 26, count 2 2006.197.07:20:19.44#ibcon#about to read 4, iclass 26, count 2 2006.197.07:20:19.44#ibcon#read 4, iclass 26, count 2 2006.197.07:20:19.44#ibcon#about to read 5, iclass 26, count 2 2006.197.07:20:19.44#ibcon#read 5, iclass 26, count 2 2006.197.07:20:19.44#ibcon#about to read 6, iclass 26, count 2 2006.197.07:20:19.44#ibcon#read 6, iclass 26, count 2 2006.197.07:20:19.44#ibcon#end of sib2, iclass 26, count 2 2006.197.07:20:19.44#ibcon#*mode == 0, iclass 26, count 2 2006.197.07:20:19.44#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.197.07:20:19.44#ibcon#[27=AT04-04\r\n] 2006.197.07:20:19.44#ibcon#*before write, iclass 26, count 2 2006.197.07:20:19.44#ibcon#enter sib2, iclass 26, count 2 2006.197.07:20:19.44#ibcon#flushed, iclass 26, count 2 2006.197.07:20:19.44#ibcon#about to write, iclass 26, count 2 2006.197.07:20:19.44#ibcon#wrote, iclass 26, count 2 2006.197.07:20:19.44#ibcon#about to read 3, iclass 26, count 2 2006.197.07:20:19.47#ibcon#read 3, iclass 26, count 2 2006.197.07:20:19.47#ibcon#about to read 4, iclass 26, count 2 2006.197.07:20:19.47#ibcon#read 4, iclass 26, count 2 2006.197.07:20:19.47#ibcon#about to read 5, iclass 26, count 2 2006.197.07:20:19.47#ibcon#read 5, iclass 26, count 2 2006.197.07:20:19.47#ibcon#about to read 6, iclass 26, count 2 2006.197.07:20:19.47#ibcon#read 6, iclass 26, count 2 2006.197.07:20:19.47#ibcon#end of sib2, iclass 26, count 2 2006.197.07:20:19.47#ibcon#*after write, iclass 26, count 2 2006.197.07:20:19.47#ibcon#*before return 0, iclass 26, count 2 2006.197.07:20:19.47#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.197.07:20:19.47#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.197.07:20:19.47#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.197.07:20:19.47#ibcon#ireg 7 cls_cnt 0 2006.197.07:20:19.47#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.197.07:20:19.59#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.197.07:20:19.59#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.197.07:20:19.59#ibcon#enter wrdev, iclass 26, count 0 2006.197.07:20:19.59#ibcon#first serial, iclass 26, count 0 2006.197.07:20:19.59#ibcon#enter sib2, iclass 26, count 0 2006.197.07:20:19.59#ibcon#flushed, iclass 26, count 0 2006.197.07:20:19.59#ibcon#about to write, iclass 26, count 0 2006.197.07:20:19.59#ibcon#wrote, iclass 26, count 0 2006.197.07:20:19.59#ibcon#about to read 3, iclass 26, count 0 2006.197.07:20:19.61#ibcon#read 3, iclass 26, count 0 2006.197.07:20:19.61#ibcon#about to read 4, iclass 26, count 0 2006.197.07:20:19.61#ibcon#read 4, iclass 26, count 0 2006.197.07:20:19.61#ibcon#about to read 5, iclass 26, count 0 2006.197.07:20:19.61#ibcon#read 5, iclass 26, count 0 2006.197.07:20:19.61#ibcon#about to read 6, iclass 26, count 0 2006.197.07:20:19.61#ibcon#read 6, iclass 26, count 0 2006.197.07:20:19.61#ibcon#end of sib2, iclass 26, count 0 2006.197.07:20:19.61#ibcon#*mode == 0, iclass 26, count 0 2006.197.07:20:19.61#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.197.07:20:19.61#ibcon#[27=USB\r\n] 2006.197.07:20:19.61#ibcon#*before write, iclass 26, count 0 2006.197.07:20:19.61#ibcon#enter sib2, iclass 26, count 0 2006.197.07:20:19.61#ibcon#flushed, iclass 26, count 0 2006.197.07:20:19.61#ibcon#about to write, iclass 26, count 0 2006.197.07:20:19.61#ibcon#wrote, iclass 26, count 0 2006.197.07:20:19.61#ibcon#about to read 3, iclass 26, count 0 2006.197.07:20:19.64#ibcon#read 3, iclass 26, count 0 2006.197.07:20:19.64#ibcon#about to read 4, iclass 26, count 0 2006.197.07:20:19.64#ibcon#read 4, iclass 26, count 0 2006.197.07:20:19.64#ibcon#about to read 5, iclass 26, count 0 2006.197.07:20:19.64#ibcon#read 5, iclass 26, count 0 2006.197.07:20:19.64#ibcon#about to read 6, iclass 26, count 0 2006.197.07:20:19.64#ibcon#read 6, iclass 26, count 0 2006.197.07:20:19.64#ibcon#end of sib2, iclass 26, count 0 2006.197.07:20:19.64#ibcon#*after write, iclass 26, count 0 2006.197.07:20:19.64#ibcon#*before return 0, iclass 26, count 0 2006.197.07:20:19.64#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.197.07:20:19.64#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.197.07:20:19.64#ibcon#about to clear, iclass 26 cls_cnt 0 2006.197.07:20:19.64#ibcon#cleared, iclass 26 cls_cnt 0 2006.197.07:20:19.64$vc4f8/vblo=5,744.99 2006.197.07:20:19.64#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.197.07:20:19.64#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.197.07:20:19.64#ibcon#ireg 17 cls_cnt 0 2006.197.07:20:19.64#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.197.07:20:19.64#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.197.07:20:19.64#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.197.07:20:19.64#ibcon#enter wrdev, iclass 28, count 0 2006.197.07:20:19.64#ibcon#first serial, iclass 28, count 0 2006.197.07:20:19.64#ibcon#enter sib2, iclass 28, count 0 2006.197.07:20:19.64#ibcon#flushed, iclass 28, count 0 2006.197.07:20:19.64#ibcon#about to write, iclass 28, count 0 2006.197.07:20:19.64#ibcon#wrote, iclass 28, count 0 2006.197.07:20:19.64#ibcon#about to read 3, iclass 28, count 0 2006.197.07:20:19.66#ibcon#read 3, iclass 28, count 0 2006.197.07:20:19.66#ibcon#about to read 4, iclass 28, count 0 2006.197.07:20:19.66#ibcon#read 4, iclass 28, count 0 2006.197.07:20:19.66#ibcon#about to read 5, iclass 28, count 0 2006.197.07:20:19.66#ibcon#read 5, iclass 28, count 0 2006.197.07:20:19.66#ibcon#about to read 6, iclass 28, count 0 2006.197.07:20:19.66#ibcon#read 6, iclass 28, count 0 2006.197.07:20:19.66#ibcon#end of sib2, iclass 28, count 0 2006.197.07:20:19.66#ibcon#*mode == 0, iclass 28, count 0 2006.197.07:20:19.66#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.197.07:20:19.66#ibcon#[28=FRQ=05,744.99\r\n] 2006.197.07:20:19.66#ibcon#*before write, iclass 28, count 0 2006.197.07:20:19.66#ibcon#enter sib2, iclass 28, count 0 2006.197.07:20:19.66#ibcon#flushed, iclass 28, count 0 2006.197.07:20:19.66#ibcon#about to write, iclass 28, count 0 2006.197.07:20:19.66#ibcon#wrote, iclass 28, count 0 2006.197.07:20:19.66#ibcon#about to read 3, iclass 28, count 0 2006.197.07:20:19.70#ibcon#read 3, iclass 28, count 0 2006.197.07:20:19.70#ibcon#about to read 4, iclass 28, count 0 2006.197.07:20:19.70#ibcon#read 4, iclass 28, count 0 2006.197.07:20:19.70#ibcon#about to read 5, iclass 28, count 0 2006.197.07:20:19.70#ibcon#read 5, iclass 28, count 0 2006.197.07:20:19.70#ibcon#about to read 6, iclass 28, count 0 2006.197.07:20:19.70#ibcon#read 6, iclass 28, count 0 2006.197.07:20:19.70#ibcon#end of sib2, iclass 28, count 0 2006.197.07:20:19.70#ibcon#*after write, iclass 28, count 0 2006.197.07:20:19.70#ibcon#*before return 0, iclass 28, count 0 2006.197.07:20:19.70#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.197.07:20:19.70#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.197.07:20:19.70#ibcon#about to clear, iclass 28 cls_cnt 0 2006.197.07:20:19.70#ibcon#cleared, iclass 28 cls_cnt 0 2006.197.07:20:19.70$vc4f8/vb=5,4 2006.197.07:20:19.70#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.197.07:20:19.70#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.197.07:20:19.70#ibcon#ireg 11 cls_cnt 2 2006.197.07:20:19.70#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.197.07:20:19.76#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.197.07:20:19.76#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.197.07:20:19.76#ibcon#enter wrdev, iclass 30, count 2 2006.197.07:20:19.76#ibcon#first serial, iclass 30, count 2 2006.197.07:20:19.76#ibcon#enter sib2, iclass 30, count 2 2006.197.07:20:19.76#ibcon#flushed, iclass 30, count 2 2006.197.07:20:19.76#ibcon#about to write, iclass 30, count 2 2006.197.07:20:19.76#ibcon#wrote, iclass 30, count 2 2006.197.07:20:19.76#ibcon#about to read 3, iclass 30, count 2 2006.197.07:20:19.78#ibcon#read 3, iclass 30, count 2 2006.197.07:20:19.78#ibcon#about to read 4, iclass 30, count 2 2006.197.07:20:19.78#ibcon#read 4, iclass 30, count 2 2006.197.07:20:19.78#ibcon#about to read 5, iclass 30, count 2 2006.197.07:20:19.78#ibcon#read 5, iclass 30, count 2 2006.197.07:20:19.78#ibcon#about to read 6, iclass 30, count 2 2006.197.07:20:19.78#ibcon#read 6, iclass 30, count 2 2006.197.07:20:19.78#ibcon#end of sib2, iclass 30, count 2 2006.197.07:20:19.78#ibcon#*mode == 0, iclass 30, count 2 2006.197.07:20:19.78#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.197.07:20:19.78#ibcon#[27=AT05-04\r\n] 2006.197.07:20:19.78#ibcon#*before write, iclass 30, count 2 2006.197.07:20:19.78#ibcon#enter sib2, iclass 30, count 2 2006.197.07:20:19.78#ibcon#flushed, iclass 30, count 2 2006.197.07:20:19.78#ibcon#about to write, iclass 30, count 2 2006.197.07:20:19.78#ibcon#wrote, iclass 30, count 2 2006.197.07:20:19.78#ibcon#about to read 3, iclass 30, count 2 2006.197.07:20:19.81#ibcon#read 3, iclass 30, count 2 2006.197.07:20:19.81#ibcon#about to read 4, iclass 30, count 2 2006.197.07:20:19.81#ibcon#read 4, iclass 30, count 2 2006.197.07:20:19.81#ibcon#about to read 5, iclass 30, count 2 2006.197.07:20:19.81#ibcon#read 5, iclass 30, count 2 2006.197.07:20:19.81#ibcon#about to read 6, iclass 30, count 2 2006.197.07:20:19.81#ibcon#read 6, iclass 30, count 2 2006.197.07:20:19.81#ibcon#end of sib2, iclass 30, count 2 2006.197.07:20:19.81#ibcon#*after write, iclass 30, count 2 2006.197.07:20:19.81#ibcon#*before return 0, iclass 30, count 2 2006.197.07:20:19.81#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.197.07:20:19.81#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.197.07:20:19.81#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.197.07:20:19.81#ibcon#ireg 7 cls_cnt 0 2006.197.07:20:19.81#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.197.07:20:19.93#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.197.07:20:19.93#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.197.07:20:19.93#ibcon#enter wrdev, iclass 30, count 0 2006.197.07:20:19.93#ibcon#first serial, iclass 30, count 0 2006.197.07:20:19.93#ibcon#enter sib2, iclass 30, count 0 2006.197.07:20:19.93#ibcon#flushed, iclass 30, count 0 2006.197.07:20:19.93#ibcon#about to write, iclass 30, count 0 2006.197.07:20:19.93#ibcon#wrote, iclass 30, count 0 2006.197.07:20:19.93#ibcon#about to read 3, iclass 30, count 0 2006.197.07:20:19.95#ibcon#read 3, iclass 30, count 0 2006.197.07:20:19.95#ibcon#about to read 4, iclass 30, count 0 2006.197.07:20:19.95#ibcon#read 4, iclass 30, count 0 2006.197.07:20:19.95#ibcon#about to read 5, iclass 30, count 0 2006.197.07:20:19.95#ibcon#read 5, iclass 30, count 0 2006.197.07:20:19.95#ibcon#about to read 6, iclass 30, count 0 2006.197.07:20:19.95#ibcon#read 6, iclass 30, count 0 2006.197.07:20:19.95#ibcon#end of sib2, iclass 30, count 0 2006.197.07:20:19.95#ibcon#*mode == 0, iclass 30, count 0 2006.197.07:20:19.95#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.197.07:20:19.95#ibcon#[27=USB\r\n] 2006.197.07:20:19.95#ibcon#*before write, iclass 30, count 0 2006.197.07:20:19.95#ibcon#enter sib2, iclass 30, count 0 2006.197.07:20:19.95#ibcon#flushed, iclass 30, count 0 2006.197.07:20:19.95#ibcon#about to write, iclass 30, count 0 2006.197.07:20:19.95#ibcon#wrote, iclass 30, count 0 2006.197.07:20:19.95#ibcon#about to read 3, iclass 30, count 0 2006.197.07:20:19.98#ibcon#read 3, iclass 30, count 0 2006.197.07:20:19.98#ibcon#about to read 4, iclass 30, count 0 2006.197.07:20:19.98#ibcon#read 4, iclass 30, count 0 2006.197.07:20:19.98#ibcon#about to read 5, iclass 30, count 0 2006.197.07:20:19.98#ibcon#read 5, iclass 30, count 0 2006.197.07:20:19.98#ibcon#about to read 6, iclass 30, count 0 2006.197.07:20:19.98#ibcon#read 6, iclass 30, count 0 2006.197.07:20:19.98#ibcon#end of sib2, iclass 30, count 0 2006.197.07:20:19.98#ibcon#*after write, iclass 30, count 0 2006.197.07:20:19.98#ibcon#*before return 0, iclass 30, count 0 2006.197.07:20:19.98#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.197.07:20:19.98#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.197.07:20:19.98#ibcon#about to clear, iclass 30 cls_cnt 0 2006.197.07:20:19.98#ibcon#cleared, iclass 30 cls_cnt 0 2006.197.07:20:19.98$vc4f8/vblo=6,752.99 2006.197.07:20:19.98#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.197.07:20:19.98#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.197.07:20:19.98#ibcon#ireg 17 cls_cnt 0 2006.197.07:20:19.98#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.197.07:20:19.98#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.197.07:20:19.98#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.197.07:20:19.98#ibcon#enter wrdev, iclass 32, count 0 2006.197.07:20:19.98#ibcon#first serial, iclass 32, count 0 2006.197.07:20:19.98#ibcon#enter sib2, iclass 32, count 0 2006.197.07:20:19.98#ibcon#flushed, iclass 32, count 0 2006.197.07:20:19.98#ibcon#about to write, iclass 32, count 0 2006.197.07:20:19.98#ibcon#wrote, iclass 32, count 0 2006.197.07:20:19.98#ibcon#about to read 3, iclass 32, count 0 2006.197.07:20:20.00#ibcon#read 3, iclass 32, count 0 2006.197.07:20:20.00#ibcon#about to read 4, iclass 32, count 0 2006.197.07:20:20.00#ibcon#read 4, iclass 32, count 0 2006.197.07:20:20.00#ibcon#about to read 5, iclass 32, count 0 2006.197.07:20:20.00#ibcon#read 5, iclass 32, count 0 2006.197.07:20:20.00#ibcon#about to read 6, iclass 32, count 0 2006.197.07:20:20.00#ibcon#read 6, iclass 32, count 0 2006.197.07:20:20.00#ibcon#end of sib2, iclass 32, count 0 2006.197.07:20:20.00#ibcon#*mode == 0, iclass 32, count 0 2006.197.07:20:20.00#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.197.07:20:20.00#ibcon#[28=FRQ=06,752.99\r\n] 2006.197.07:20:20.00#ibcon#*before write, iclass 32, count 0 2006.197.07:20:20.00#ibcon#enter sib2, iclass 32, count 0 2006.197.07:20:20.00#ibcon#flushed, iclass 32, count 0 2006.197.07:20:20.00#ibcon#about to write, iclass 32, count 0 2006.197.07:20:20.00#ibcon#wrote, iclass 32, count 0 2006.197.07:20:20.00#ibcon#about to read 3, iclass 32, count 0 2006.197.07:20:20.04#ibcon#read 3, iclass 32, count 0 2006.197.07:20:20.04#ibcon#about to read 4, iclass 32, count 0 2006.197.07:20:20.04#ibcon#read 4, iclass 32, count 0 2006.197.07:20:20.04#ibcon#about to read 5, iclass 32, count 0 2006.197.07:20:20.04#ibcon#read 5, iclass 32, count 0 2006.197.07:20:20.04#ibcon#about to read 6, iclass 32, count 0 2006.197.07:20:20.04#ibcon#read 6, iclass 32, count 0 2006.197.07:20:20.04#ibcon#end of sib2, iclass 32, count 0 2006.197.07:20:20.04#ibcon#*after write, iclass 32, count 0 2006.197.07:20:20.04#ibcon#*before return 0, iclass 32, count 0 2006.197.07:20:20.04#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.197.07:20:20.04#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.197.07:20:20.04#ibcon#about to clear, iclass 32 cls_cnt 0 2006.197.07:20:20.04#ibcon#cleared, iclass 32 cls_cnt 0 2006.197.07:20:20.04$vc4f8/vb=6,4 2006.197.07:20:20.04#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.197.07:20:20.04#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.197.07:20:20.04#ibcon#ireg 11 cls_cnt 2 2006.197.07:20:20.04#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.197.07:20:20.10#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.197.07:20:20.10#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.197.07:20:20.10#ibcon#enter wrdev, iclass 34, count 2 2006.197.07:20:20.10#ibcon#first serial, iclass 34, count 2 2006.197.07:20:20.10#ibcon#enter sib2, iclass 34, count 2 2006.197.07:20:20.10#ibcon#flushed, iclass 34, count 2 2006.197.07:20:20.10#ibcon#about to write, iclass 34, count 2 2006.197.07:20:20.10#ibcon#wrote, iclass 34, count 2 2006.197.07:20:20.10#ibcon#about to read 3, iclass 34, count 2 2006.197.07:20:20.12#ibcon#read 3, iclass 34, count 2 2006.197.07:20:20.12#ibcon#about to read 4, iclass 34, count 2 2006.197.07:20:20.12#ibcon#read 4, iclass 34, count 2 2006.197.07:20:20.12#ibcon#about to read 5, iclass 34, count 2 2006.197.07:20:20.12#ibcon#read 5, iclass 34, count 2 2006.197.07:20:20.12#ibcon#about to read 6, iclass 34, count 2 2006.197.07:20:20.12#ibcon#read 6, iclass 34, count 2 2006.197.07:20:20.12#ibcon#end of sib2, iclass 34, count 2 2006.197.07:20:20.12#ibcon#*mode == 0, iclass 34, count 2 2006.197.07:20:20.12#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.197.07:20:20.12#ibcon#[27=AT06-04\r\n] 2006.197.07:20:20.12#ibcon#*before write, iclass 34, count 2 2006.197.07:20:20.12#ibcon#enter sib2, iclass 34, count 2 2006.197.07:20:20.12#ibcon#flushed, iclass 34, count 2 2006.197.07:20:20.12#ibcon#about to write, iclass 34, count 2 2006.197.07:20:20.12#ibcon#wrote, iclass 34, count 2 2006.197.07:20:20.12#ibcon#about to read 3, iclass 34, count 2 2006.197.07:20:20.15#ibcon#read 3, iclass 34, count 2 2006.197.07:20:20.15#ibcon#about to read 4, iclass 34, count 2 2006.197.07:20:20.15#ibcon#read 4, iclass 34, count 2 2006.197.07:20:20.15#ibcon#about to read 5, iclass 34, count 2 2006.197.07:20:20.15#ibcon#read 5, iclass 34, count 2 2006.197.07:20:20.15#ibcon#about to read 6, iclass 34, count 2 2006.197.07:20:20.15#ibcon#read 6, iclass 34, count 2 2006.197.07:20:20.15#ibcon#end of sib2, iclass 34, count 2 2006.197.07:20:20.15#ibcon#*after write, iclass 34, count 2 2006.197.07:20:20.15#ibcon#*before return 0, iclass 34, count 2 2006.197.07:20:20.15#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.197.07:20:20.15#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.197.07:20:20.15#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.197.07:20:20.15#ibcon#ireg 7 cls_cnt 0 2006.197.07:20:20.15#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.197.07:20:20.27#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.197.07:20:20.27#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.197.07:20:20.27#ibcon#enter wrdev, iclass 34, count 0 2006.197.07:20:20.27#ibcon#first serial, iclass 34, count 0 2006.197.07:20:20.27#ibcon#enter sib2, iclass 34, count 0 2006.197.07:20:20.27#ibcon#flushed, iclass 34, count 0 2006.197.07:20:20.27#ibcon#about to write, iclass 34, count 0 2006.197.07:20:20.27#ibcon#wrote, iclass 34, count 0 2006.197.07:20:20.27#ibcon#about to read 3, iclass 34, count 0 2006.197.07:20:20.29#ibcon#read 3, iclass 34, count 0 2006.197.07:20:20.29#ibcon#about to read 4, iclass 34, count 0 2006.197.07:20:20.29#ibcon#read 4, iclass 34, count 0 2006.197.07:20:20.29#ibcon#about to read 5, iclass 34, count 0 2006.197.07:20:20.29#ibcon#read 5, iclass 34, count 0 2006.197.07:20:20.29#ibcon#about to read 6, iclass 34, count 0 2006.197.07:20:20.29#ibcon#read 6, iclass 34, count 0 2006.197.07:20:20.29#ibcon#end of sib2, iclass 34, count 0 2006.197.07:20:20.29#ibcon#*mode == 0, iclass 34, count 0 2006.197.07:20:20.29#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.197.07:20:20.29#ibcon#[27=USB\r\n] 2006.197.07:20:20.29#ibcon#*before write, iclass 34, count 0 2006.197.07:20:20.29#ibcon#enter sib2, iclass 34, count 0 2006.197.07:20:20.29#ibcon#flushed, iclass 34, count 0 2006.197.07:20:20.29#ibcon#about to write, iclass 34, count 0 2006.197.07:20:20.29#ibcon#wrote, iclass 34, count 0 2006.197.07:20:20.29#ibcon#about to read 3, iclass 34, count 0 2006.197.07:20:20.32#ibcon#read 3, iclass 34, count 0 2006.197.07:20:20.32#ibcon#about to read 4, iclass 34, count 0 2006.197.07:20:20.32#ibcon#read 4, iclass 34, count 0 2006.197.07:20:20.32#ibcon#about to read 5, iclass 34, count 0 2006.197.07:20:20.32#ibcon#read 5, iclass 34, count 0 2006.197.07:20:20.32#ibcon#about to read 6, iclass 34, count 0 2006.197.07:20:20.32#ibcon#read 6, iclass 34, count 0 2006.197.07:20:20.32#ibcon#end of sib2, iclass 34, count 0 2006.197.07:20:20.32#ibcon#*after write, iclass 34, count 0 2006.197.07:20:20.32#ibcon#*before return 0, iclass 34, count 0 2006.197.07:20:20.32#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.197.07:20:20.32#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.197.07:20:20.32#ibcon#about to clear, iclass 34 cls_cnt 0 2006.197.07:20:20.32#ibcon#cleared, iclass 34 cls_cnt 0 2006.197.07:20:20.32$vc4f8/vabw=wide 2006.197.07:20:20.32#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.197.07:20:20.32#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.197.07:20:20.32#ibcon#ireg 8 cls_cnt 0 2006.197.07:20:20.32#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.197.07:20:20.32#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.197.07:20:20.32#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.197.07:20:20.32#ibcon#enter wrdev, iclass 36, count 0 2006.197.07:20:20.32#ibcon#first serial, iclass 36, count 0 2006.197.07:20:20.32#ibcon#enter sib2, iclass 36, count 0 2006.197.07:20:20.32#ibcon#flushed, iclass 36, count 0 2006.197.07:20:20.32#ibcon#about to write, iclass 36, count 0 2006.197.07:20:20.32#ibcon#wrote, iclass 36, count 0 2006.197.07:20:20.32#ibcon#about to read 3, iclass 36, count 0 2006.197.07:20:20.34#ibcon#read 3, iclass 36, count 0 2006.197.07:20:20.34#ibcon#about to read 4, iclass 36, count 0 2006.197.07:20:20.34#ibcon#read 4, iclass 36, count 0 2006.197.07:20:20.34#ibcon#about to read 5, iclass 36, count 0 2006.197.07:20:20.34#ibcon#read 5, iclass 36, count 0 2006.197.07:20:20.34#ibcon#about to read 6, iclass 36, count 0 2006.197.07:20:20.34#ibcon#read 6, iclass 36, count 0 2006.197.07:20:20.34#ibcon#end of sib2, iclass 36, count 0 2006.197.07:20:20.34#ibcon#*mode == 0, iclass 36, count 0 2006.197.07:20:20.34#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.197.07:20:20.34#ibcon#[25=BW32\r\n] 2006.197.07:20:20.34#ibcon#*before write, iclass 36, count 0 2006.197.07:20:20.34#ibcon#enter sib2, iclass 36, count 0 2006.197.07:20:20.34#ibcon#flushed, iclass 36, count 0 2006.197.07:20:20.34#ibcon#about to write, iclass 36, count 0 2006.197.07:20:20.34#ibcon#wrote, iclass 36, count 0 2006.197.07:20:20.34#ibcon#about to read 3, iclass 36, count 0 2006.197.07:20:20.37#ibcon#read 3, iclass 36, count 0 2006.197.07:20:20.37#ibcon#about to read 4, iclass 36, count 0 2006.197.07:20:20.37#ibcon#read 4, iclass 36, count 0 2006.197.07:20:20.37#ibcon#about to read 5, iclass 36, count 0 2006.197.07:20:20.37#ibcon#read 5, iclass 36, count 0 2006.197.07:20:20.37#ibcon#about to read 6, iclass 36, count 0 2006.197.07:20:20.37#ibcon#read 6, iclass 36, count 0 2006.197.07:20:20.37#ibcon#end of sib2, iclass 36, count 0 2006.197.07:20:20.37#ibcon#*after write, iclass 36, count 0 2006.197.07:20:20.37#ibcon#*before return 0, iclass 36, count 0 2006.197.07:20:20.37#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.197.07:20:20.37#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.197.07:20:20.37#ibcon#about to clear, iclass 36 cls_cnt 0 2006.197.07:20:20.37#ibcon#cleared, iclass 36 cls_cnt 0 2006.197.07:20:20.37$vc4f8/vbbw=wide 2006.197.07:20:20.37#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.197.07:20:20.37#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.197.07:20:20.37#ibcon#ireg 8 cls_cnt 0 2006.197.07:20:20.37#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.197.07:20:20.44#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.197.07:20:20.44#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.197.07:20:20.44#ibcon#enter wrdev, iclass 38, count 0 2006.197.07:20:20.44#ibcon#first serial, iclass 38, count 0 2006.197.07:20:20.44#ibcon#enter sib2, iclass 38, count 0 2006.197.07:20:20.44#ibcon#flushed, iclass 38, count 0 2006.197.07:20:20.44#ibcon#about to write, iclass 38, count 0 2006.197.07:20:20.44#ibcon#wrote, iclass 38, count 0 2006.197.07:20:20.44#ibcon#about to read 3, iclass 38, count 0 2006.197.07:20:20.46#ibcon#read 3, iclass 38, count 0 2006.197.07:20:20.46#ibcon#about to read 4, iclass 38, count 0 2006.197.07:20:20.46#ibcon#read 4, iclass 38, count 0 2006.197.07:20:20.46#ibcon#about to read 5, iclass 38, count 0 2006.197.07:20:20.46#ibcon#read 5, iclass 38, count 0 2006.197.07:20:20.46#ibcon#about to read 6, iclass 38, count 0 2006.197.07:20:20.46#ibcon#read 6, iclass 38, count 0 2006.197.07:20:20.46#ibcon#end of sib2, iclass 38, count 0 2006.197.07:20:20.46#ibcon#*mode == 0, iclass 38, count 0 2006.197.07:20:20.46#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.197.07:20:20.46#ibcon#[27=BW32\r\n] 2006.197.07:20:20.46#ibcon#*before write, iclass 38, count 0 2006.197.07:20:20.46#ibcon#enter sib2, iclass 38, count 0 2006.197.07:20:20.46#ibcon#flushed, iclass 38, count 0 2006.197.07:20:20.46#ibcon#about to write, iclass 38, count 0 2006.197.07:20:20.46#ibcon#wrote, iclass 38, count 0 2006.197.07:20:20.46#ibcon#about to read 3, iclass 38, count 0 2006.197.07:20:20.49#ibcon#read 3, iclass 38, count 0 2006.197.07:20:20.49#ibcon#about to read 4, iclass 38, count 0 2006.197.07:20:20.49#ibcon#read 4, iclass 38, count 0 2006.197.07:20:20.49#ibcon#about to read 5, iclass 38, count 0 2006.197.07:20:20.49#ibcon#read 5, iclass 38, count 0 2006.197.07:20:20.49#ibcon#about to read 6, iclass 38, count 0 2006.197.07:20:20.49#ibcon#read 6, iclass 38, count 0 2006.197.07:20:20.49#ibcon#end of sib2, iclass 38, count 0 2006.197.07:20:20.49#ibcon#*after write, iclass 38, count 0 2006.197.07:20:20.49#ibcon#*before return 0, iclass 38, count 0 2006.197.07:20:20.49#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.197.07:20:20.49#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.197.07:20:20.49#ibcon#about to clear, iclass 38 cls_cnt 0 2006.197.07:20:20.49#ibcon#cleared, iclass 38 cls_cnt 0 2006.197.07:20:20.49$4f8m12a/ifd4f 2006.197.07:20:20.49&ifd4f/lo= 2006.197.07:20:20.49&ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.197.07:20:20.49&ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.197.07:20:20.49&ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.197.07:20:20.49&ifd4f/patch= 2006.197.07:20:20.49&ifd4f/patch=lo1,a1,a2,a3,a4 2006.197.07:20:20.49&ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.197.07:20:20.49&ifd4f/patch=lo3,a5,a6,a7,a8 2006.197.07:20:20.49$ifd4f/lo= 2006.197.07:20:20.49$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.197.07:20:20.49$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.197.07:20:20.49$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.197.07:20:20.49$ifd4f/patch= 2006.197.07:20:20.49$ifd4f/patch=lo1,a1,a2,a3,a4 2006.197.07:20:20.49$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.197.07:20:20.49$ifd4f/patch=lo3,a5,a6,a7,a8 2006.197.07:20:20.49$4f8m12a/"form=m,16.000,1:2 2006.197.07:20:20.49$4f8m12a/"tpicd 2006.197.07:20:20.49$4f8m12a/echo=off 2006.197.07:20:20.49$4f8m12a/xlog=off 2006.197.07:20:20.49:!2006.197.07:29:50 2006.197.07:20:44.13#trakl#Source acquired 2006.197.07:20:44.13#flagr#flagr/antenna,acquired 2006.197.07:29:50.00:preob 2006.197.07:29:50.00&preob/onsource 2006.197.07:29:51.13/onsource/TRACKING 2006.197.07:29:51.13:!2006.197.07:30:00 2006.197.07:30:00.00:data_valid=on 2006.197.07:30:00.00:midob 2006.197.07:30:00.00&midob/onsource 2006.197.07:30:00.00&midob/wx 2006.197.07:30:00.00&midob/cable 2006.197.07:30:00.00&midob/va 2006.197.07:30:00.00&midob/valo 2006.197.07:30:00.00&midob/vb 2006.197.07:30:00.00&midob/vblo 2006.197.07:30:00.00&midob/vabw 2006.197.07:30:00.00&midob/vbbw 2006.197.07:30:00.00&midob/"form 2006.197.07:30:00.00&midob/xfe 2006.197.07:30:00.00&midob/ifatt 2006.197.07:30:00.00&midob/clockoff 2006.197.07:30:00.00&midob/sy=logmail 2006.197.07:30:00.00&midob/"sy=run setcl adapt & 2006.197.07:30:00.13/onsource/TRACKING 2006.197.07:30:00.13/wx/25.94,1003.0,97 2006.197.07:30:00.30/cable/+6.3677E-03 2006.197.07:30:01.39/va/01,08,usb,yes,34,36 2006.197.07:30:01.39/va/02,07,usb,yes,35,36 2006.197.07:30:01.39/va/03,06,usb,yes,37,37 2006.197.07:30:01.39/va/04,07,usb,yes,36,39 2006.197.07:30:01.39/va/05,07,usb,yes,41,43 2006.197.07:30:01.39/va/06,06,usb,yes,40,40 2006.197.07:30:01.39/va/07,06,usb,yes,40,40 2006.197.07:30:01.39/va/08,07,usb,yes,38,38 2006.197.07:30:01.62/valo/01,532.99,yes,locked 2006.197.07:30:01.62/valo/02,572.99,yes,locked 2006.197.07:30:01.62/valo/03,672.99,yes,locked 2006.197.07:30:01.62/valo/04,832.99,yes,locked 2006.197.07:30:01.62/valo/05,652.99,yes,locked 2006.197.07:30:01.62/valo/06,772.99,yes,locked 2006.197.07:30:01.62/valo/07,832.99,yes,locked 2006.197.07:30:01.62/valo/08,852.99,yes,locked 2006.197.07:30:02.71/vb/01,04,usb,yes,32,30 2006.197.07:30:02.71/vb/02,04,usb,yes,34,35 2006.197.07:30:02.71/vb/03,04,usb,yes,30,34 2006.197.07:30:02.71/vb/04,04,usb,yes,31,31 2006.197.07:30:02.71/vb/05,04,usb,yes,29,34 2006.197.07:30:02.71/vb/06,04,usb,yes,30,33 2006.197.07:30:02.71/vb/07,04,usb,yes,33,33 2006.197.07:30:02.71/vb/08,04,usb,yes,30,33 2006.197.07:30:02.94/vblo/01,632.99,yes,locked 2006.197.07:30:02.94/vblo/02,640.99,yes,locked 2006.197.07:30:02.94/vblo/03,656.99,yes,locked 2006.197.07:30:02.94/vblo/04,712.99,yes,locked 2006.197.07:30:02.94/vblo/05,744.99,yes,locked 2006.197.07:30:02.94/vblo/06,752.99,yes,locked 2006.197.07:30:02.94/vblo/07,734.99,yes,locked 2006.197.07:30:02.94/vblo/08,744.99,yes,locked 2006.197.07:30:03.09/vabw/8 2006.197.07:30:03.24/vbbw/8 2006.197.07:30:03.33/xfe/off,on,15.2 2006.197.07:30:03.72/ifatt/23,28,28,28 2006.197.07:30:03.72&clockoff/"gps-fmout=1p 2006.197.07:30:03.72&clockoff/fmout-gps=1p 2006.197.07:30:04.09/fmout-gps/S +3.01E-07 2006.197.07:30:04.13:!2006.197.07:31:00 2006.197.07:31:00.00:data_valid=off 2006.197.07:31:00.00:postob 2006.197.07:31:00.00&postob/cable 2006.197.07:31:00.00&postob/wx 2006.197.07:31:00.00&postob/clockoff 2006.197.07:31:00.09/cable/+6.3681E-03 2006.197.07:31:00.09/wx/25.94,1003.0,98 2006.197.07:31:01.10/fmout-gps/S +2.99E-07 2006.197.07:31:01.10:scan_name=197-0733,k06197,60 2006.197.07:31:01.10:source=0823+033,082550.34,030924.5,2000.0,ccw 2006.197.07:31:01.13#flagr#flagr/antenna,new-source 2006.197.07:31:02.13:checkk5 2006.197.07:31:02.13&checkk5/chk_autoobs=1 2006.197.07:31:02.13&checkk5/chk_autoobs=2 2006.197.07:31:02.13&checkk5/chk_autoobs=3 2006.197.07:31:02.13&checkk5/chk_autoobs=4 2006.197.07:31:02.13&checkk5/chk_obsdata=1 2006.197.07:31:02.13&checkk5/chk_obsdata=2 2006.197.07:31:02.13&checkk5/chk_obsdata=3 2006.197.07:31:02.13&checkk5/chk_obsdata=4 2006.197.07:31:02.13&checkk5/k5log=1 2006.197.07:31:02.13&checkk5/k5log=2 2006.197.07:31:02.13&checkk5/k5log=3 2006.197.07:31:02.13&checkk5/k5log=4 2006.197.07:31:02.13&checkk5/obsinfo 2006.197.07:31:02.48/chk_autoobs//k5ts1/ autoobs is running! 2006.197.07:31:02.82/chk_autoobs//k5ts2/ autoobs is running! 2006.197.07:31:03.18/chk_autoobs//k5ts3/ autoobs is running! 2006.197.07:31:03.52/chk_autoobs//k5ts4/ autoobs is running! 2006.197.07:31:03.86/chk_obsdata//k5ts1/T1970730??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.07:31:04.20/chk_obsdata//k5ts2/T1970730??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.07:31:04.54/chk_obsdata//k5ts3/T1970730??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.07:31:04.87/chk_obsdata//k5ts4/T1970730??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.07:31:05.54/k5log//k5ts1_log_newline 2006.197.07:31:06.20/k5log//k5ts2_log_newline 2006.197.07:31:06.86/k5log//k5ts3_log_newline 2006.197.07:31:07.51/k5log//k5ts4_log_newline 2006.197.07:31:07.54/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.197.07:31:07.54:4f8m12a=1 2006.197.07:31:07.54$4f8m12a/echo=on 2006.197.07:31:07.54$4f8m12a/pcalon 2006.197.07:31:07.54$pcalon/"no phase cal control is implemented here 2006.197.07:31:07.54$4f8m12a/"tpicd=stop 2006.197.07:31:07.54$4f8m12a/vc4f8 2006.197.07:31:07.54$vc4f8/valo=1,532.99 2006.197.07:31:07.54#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.197.07:31:07.54#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.197.07:31:07.54#ibcon#ireg 17 cls_cnt 0 2006.197.07:31:07.54#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.197.07:31:07.54#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.197.07:31:07.54#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.197.07:31:07.54#ibcon#enter wrdev, iclass 3, count 0 2006.197.07:31:07.54#ibcon#first serial, iclass 3, count 0 2006.197.07:31:07.54#ibcon#enter sib2, iclass 3, count 0 2006.197.07:31:07.54#ibcon#flushed, iclass 3, count 0 2006.197.07:31:07.54#ibcon#about to write, iclass 3, count 0 2006.197.07:31:07.54#ibcon#wrote, iclass 3, count 0 2006.197.07:31:07.54#ibcon#about to read 3, iclass 3, count 0 2006.197.07:31:07.56#ibcon#read 3, iclass 3, count 0 2006.197.07:31:07.56#ibcon#about to read 4, iclass 3, count 0 2006.197.07:31:07.56#ibcon#read 4, iclass 3, count 0 2006.197.07:31:07.56#ibcon#about to read 5, iclass 3, count 0 2006.197.07:31:07.56#ibcon#read 5, iclass 3, count 0 2006.197.07:31:07.56#ibcon#about to read 6, iclass 3, count 0 2006.197.07:31:07.56#ibcon#read 6, iclass 3, count 0 2006.197.07:31:07.56#ibcon#end of sib2, iclass 3, count 0 2006.197.07:31:07.56#ibcon#*mode == 0, iclass 3, count 0 2006.197.07:31:07.56#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.197.07:31:07.56#ibcon#[26=FRQ=01,532.99\r\n] 2006.197.07:31:07.56#ibcon#*before write, iclass 3, count 0 2006.197.07:31:07.56#ibcon#enter sib2, iclass 3, count 0 2006.197.07:31:07.56#ibcon#flushed, iclass 3, count 0 2006.197.07:31:07.56#ibcon#about to write, iclass 3, count 0 2006.197.07:31:07.56#ibcon#wrote, iclass 3, count 0 2006.197.07:31:07.56#ibcon#about to read 3, iclass 3, count 0 2006.197.07:31:07.61#ibcon#read 3, iclass 3, count 0 2006.197.07:31:07.61#ibcon#about to read 4, iclass 3, count 0 2006.197.07:31:07.61#ibcon#read 4, iclass 3, count 0 2006.197.07:31:07.61#ibcon#about to read 5, iclass 3, count 0 2006.197.07:31:07.61#ibcon#read 5, iclass 3, count 0 2006.197.07:31:07.61#ibcon#about to read 6, iclass 3, count 0 2006.197.07:31:07.61#ibcon#read 6, iclass 3, count 0 2006.197.07:31:07.61#ibcon#end of sib2, iclass 3, count 0 2006.197.07:31:07.61#ibcon#*after write, iclass 3, count 0 2006.197.07:31:07.61#ibcon#*before return 0, iclass 3, count 0 2006.197.07:31:07.61#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.197.07:31:07.61#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.197.07:31:07.61#ibcon#about to clear, iclass 3 cls_cnt 0 2006.197.07:31:07.61#ibcon#cleared, iclass 3 cls_cnt 0 2006.197.07:31:07.61$vc4f8/va=1,8 2006.197.07:31:07.61#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.197.07:31:07.61#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.197.07:31:07.61#ibcon#ireg 11 cls_cnt 2 2006.197.07:31:07.61#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.197.07:31:07.61#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.197.07:31:07.61#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.197.07:31:07.61#ibcon#enter wrdev, iclass 5, count 2 2006.197.07:31:07.61#ibcon#first serial, iclass 5, count 2 2006.197.07:31:07.61#ibcon#enter sib2, iclass 5, count 2 2006.197.07:31:07.61#ibcon#flushed, iclass 5, count 2 2006.197.07:31:07.61#ibcon#about to write, iclass 5, count 2 2006.197.07:31:07.61#ibcon#wrote, iclass 5, count 2 2006.197.07:31:07.61#ibcon#about to read 3, iclass 5, count 2 2006.197.07:31:07.63#ibcon#read 3, iclass 5, count 2 2006.197.07:31:07.63#ibcon#about to read 4, iclass 5, count 2 2006.197.07:31:07.63#ibcon#read 4, iclass 5, count 2 2006.197.07:31:07.63#ibcon#about to read 5, iclass 5, count 2 2006.197.07:31:07.63#ibcon#read 5, iclass 5, count 2 2006.197.07:31:07.63#ibcon#about to read 6, iclass 5, count 2 2006.197.07:31:07.63#ibcon#read 6, iclass 5, count 2 2006.197.07:31:07.63#ibcon#end of sib2, iclass 5, count 2 2006.197.07:31:07.63#ibcon#*mode == 0, iclass 5, count 2 2006.197.07:31:07.63#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.197.07:31:07.63#ibcon#[25=AT01-08\r\n] 2006.197.07:31:07.63#ibcon#*before write, iclass 5, count 2 2006.197.07:31:07.63#ibcon#enter sib2, iclass 5, count 2 2006.197.07:31:07.63#ibcon#flushed, iclass 5, count 2 2006.197.07:31:07.63#ibcon#about to write, iclass 5, count 2 2006.197.07:31:07.63#ibcon#wrote, iclass 5, count 2 2006.197.07:31:07.63#ibcon#about to read 3, iclass 5, count 2 2006.197.07:31:07.66#ibcon#read 3, iclass 5, count 2 2006.197.07:31:07.66#ibcon#about to read 4, iclass 5, count 2 2006.197.07:31:07.66#ibcon#read 4, iclass 5, count 2 2006.197.07:31:07.66#ibcon#about to read 5, iclass 5, count 2 2006.197.07:31:07.66#ibcon#read 5, iclass 5, count 2 2006.197.07:31:07.66#ibcon#about to read 6, iclass 5, count 2 2006.197.07:31:07.66#ibcon#read 6, iclass 5, count 2 2006.197.07:31:07.66#ibcon#end of sib2, iclass 5, count 2 2006.197.07:31:07.66#ibcon#*after write, iclass 5, count 2 2006.197.07:31:07.66#ibcon#*before return 0, iclass 5, count 2 2006.197.07:31:07.66#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.197.07:31:07.66#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.197.07:31:07.66#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.197.07:31:07.66#ibcon#ireg 7 cls_cnt 0 2006.197.07:31:07.66#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.197.07:31:07.78#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.197.07:31:07.78#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.197.07:31:07.78#ibcon#enter wrdev, iclass 5, count 0 2006.197.07:31:07.78#ibcon#first serial, iclass 5, count 0 2006.197.07:31:07.78#ibcon#enter sib2, iclass 5, count 0 2006.197.07:31:07.78#ibcon#flushed, iclass 5, count 0 2006.197.07:31:07.78#ibcon#about to write, iclass 5, count 0 2006.197.07:31:07.78#ibcon#wrote, iclass 5, count 0 2006.197.07:31:07.78#ibcon#about to read 3, iclass 5, count 0 2006.197.07:31:07.80#ibcon#read 3, iclass 5, count 0 2006.197.07:31:07.80#ibcon#about to read 4, iclass 5, count 0 2006.197.07:31:07.80#ibcon#read 4, iclass 5, count 0 2006.197.07:31:07.80#ibcon#about to read 5, iclass 5, count 0 2006.197.07:31:07.80#ibcon#read 5, iclass 5, count 0 2006.197.07:31:07.80#ibcon#about to read 6, iclass 5, count 0 2006.197.07:31:07.80#ibcon#read 6, iclass 5, count 0 2006.197.07:31:07.80#ibcon#end of sib2, iclass 5, count 0 2006.197.07:31:07.80#ibcon#*mode == 0, iclass 5, count 0 2006.197.07:31:07.80#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.197.07:31:07.80#ibcon#[25=USB\r\n] 2006.197.07:31:07.80#ibcon#*before write, iclass 5, count 0 2006.197.07:31:07.80#ibcon#enter sib2, iclass 5, count 0 2006.197.07:31:07.80#ibcon#flushed, iclass 5, count 0 2006.197.07:31:07.80#ibcon#about to write, iclass 5, count 0 2006.197.07:31:07.80#ibcon#wrote, iclass 5, count 0 2006.197.07:31:07.80#ibcon#about to read 3, iclass 5, count 0 2006.197.07:31:07.83#ibcon#read 3, iclass 5, count 0 2006.197.07:31:07.83#ibcon#about to read 4, iclass 5, count 0 2006.197.07:31:07.83#ibcon#read 4, iclass 5, count 0 2006.197.07:31:07.83#ibcon#about to read 5, iclass 5, count 0 2006.197.07:31:07.83#ibcon#read 5, iclass 5, count 0 2006.197.07:31:07.83#ibcon#about to read 6, iclass 5, count 0 2006.197.07:31:07.83#ibcon#read 6, iclass 5, count 0 2006.197.07:31:07.83#ibcon#end of sib2, iclass 5, count 0 2006.197.07:31:07.83#ibcon#*after write, iclass 5, count 0 2006.197.07:31:07.83#ibcon#*before return 0, iclass 5, count 0 2006.197.07:31:07.83#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.197.07:31:07.83#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.197.07:31:07.83#ibcon#about to clear, iclass 5 cls_cnt 0 2006.197.07:31:07.83#ibcon#cleared, iclass 5 cls_cnt 0 2006.197.07:31:07.83$vc4f8/valo=2,572.99 2006.197.07:31:07.83#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.197.07:31:07.83#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.197.07:31:07.83#ibcon#ireg 17 cls_cnt 0 2006.197.07:31:07.83#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.197.07:31:07.83#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.197.07:31:07.83#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.197.07:31:07.83#ibcon#enter wrdev, iclass 7, count 0 2006.197.07:31:07.83#ibcon#first serial, iclass 7, count 0 2006.197.07:31:07.83#ibcon#enter sib2, iclass 7, count 0 2006.197.07:31:07.83#ibcon#flushed, iclass 7, count 0 2006.197.07:31:07.83#ibcon#about to write, iclass 7, count 0 2006.197.07:31:07.83#ibcon#wrote, iclass 7, count 0 2006.197.07:31:07.83#ibcon#about to read 3, iclass 7, count 0 2006.197.07:31:07.85#ibcon#read 3, iclass 7, count 0 2006.197.07:31:07.85#ibcon#about to read 4, iclass 7, count 0 2006.197.07:31:07.85#ibcon#read 4, iclass 7, count 0 2006.197.07:31:07.85#ibcon#about to read 5, iclass 7, count 0 2006.197.07:31:07.85#ibcon#read 5, iclass 7, count 0 2006.197.07:31:07.85#ibcon#about to read 6, iclass 7, count 0 2006.197.07:31:07.85#ibcon#read 6, iclass 7, count 0 2006.197.07:31:07.85#ibcon#end of sib2, iclass 7, count 0 2006.197.07:31:07.85#ibcon#*mode == 0, iclass 7, count 0 2006.197.07:31:07.85#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.197.07:31:07.85#ibcon#[26=FRQ=02,572.99\r\n] 2006.197.07:31:07.85#ibcon#*before write, iclass 7, count 0 2006.197.07:31:07.85#ibcon#enter sib2, iclass 7, count 0 2006.197.07:31:07.85#ibcon#flushed, iclass 7, count 0 2006.197.07:31:07.85#ibcon#about to write, iclass 7, count 0 2006.197.07:31:07.85#ibcon#wrote, iclass 7, count 0 2006.197.07:31:07.85#ibcon#about to read 3, iclass 7, count 0 2006.197.07:31:07.89#ibcon#read 3, iclass 7, count 0 2006.197.07:31:07.89#ibcon#about to read 4, iclass 7, count 0 2006.197.07:31:07.89#ibcon#read 4, iclass 7, count 0 2006.197.07:31:07.89#ibcon#about to read 5, iclass 7, count 0 2006.197.07:31:07.89#ibcon#read 5, iclass 7, count 0 2006.197.07:31:07.89#ibcon#about to read 6, iclass 7, count 0 2006.197.07:31:07.89#ibcon#read 6, iclass 7, count 0 2006.197.07:31:07.89#ibcon#end of sib2, iclass 7, count 0 2006.197.07:31:07.89#ibcon#*after write, iclass 7, count 0 2006.197.07:31:07.89#ibcon#*before return 0, iclass 7, count 0 2006.197.07:31:07.89#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.197.07:31:07.89#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.197.07:31:07.89#ibcon#about to clear, iclass 7 cls_cnt 0 2006.197.07:31:07.89#ibcon#cleared, iclass 7 cls_cnt 0 2006.197.07:31:07.89$vc4f8/va=2,7 2006.197.07:31:07.89#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.197.07:31:07.89#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.197.07:31:07.89#ibcon#ireg 11 cls_cnt 2 2006.197.07:31:07.89#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.197.07:31:07.95#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.197.07:31:07.95#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.197.07:31:07.95#ibcon#enter wrdev, iclass 11, count 2 2006.197.07:31:07.95#ibcon#first serial, iclass 11, count 2 2006.197.07:31:07.95#ibcon#enter sib2, iclass 11, count 2 2006.197.07:31:07.95#ibcon#flushed, iclass 11, count 2 2006.197.07:31:07.95#ibcon#about to write, iclass 11, count 2 2006.197.07:31:07.95#ibcon#wrote, iclass 11, count 2 2006.197.07:31:07.95#ibcon#about to read 3, iclass 11, count 2 2006.197.07:31:07.97#ibcon#read 3, iclass 11, count 2 2006.197.07:31:07.97#ibcon#about to read 4, iclass 11, count 2 2006.197.07:31:07.97#ibcon#read 4, iclass 11, count 2 2006.197.07:31:07.97#ibcon#about to read 5, iclass 11, count 2 2006.197.07:31:07.97#ibcon#read 5, iclass 11, count 2 2006.197.07:31:07.97#ibcon#about to read 6, iclass 11, count 2 2006.197.07:31:07.97#ibcon#read 6, iclass 11, count 2 2006.197.07:31:07.97#ibcon#end of sib2, iclass 11, count 2 2006.197.07:31:07.97#ibcon#*mode == 0, iclass 11, count 2 2006.197.07:31:07.97#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.197.07:31:07.97#ibcon#[25=AT02-07\r\n] 2006.197.07:31:07.97#ibcon#*before write, iclass 11, count 2 2006.197.07:31:07.97#ibcon#enter sib2, iclass 11, count 2 2006.197.07:31:07.97#ibcon#flushed, iclass 11, count 2 2006.197.07:31:07.97#ibcon#about to write, iclass 11, count 2 2006.197.07:31:07.97#ibcon#wrote, iclass 11, count 2 2006.197.07:31:07.97#ibcon#about to read 3, iclass 11, count 2 2006.197.07:31:08.00#ibcon#read 3, iclass 11, count 2 2006.197.07:31:08.00#ibcon#about to read 4, iclass 11, count 2 2006.197.07:31:08.00#ibcon#read 4, iclass 11, count 2 2006.197.07:31:08.00#ibcon#about to read 5, iclass 11, count 2 2006.197.07:31:08.00#ibcon#read 5, iclass 11, count 2 2006.197.07:31:08.00#ibcon#about to read 6, iclass 11, count 2 2006.197.07:31:08.00#ibcon#read 6, iclass 11, count 2 2006.197.07:31:08.00#ibcon#end of sib2, iclass 11, count 2 2006.197.07:31:08.00#ibcon#*after write, iclass 11, count 2 2006.197.07:31:08.00#ibcon#*before return 0, iclass 11, count 2 2006.197.07:31:08.00#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.197.07:31:08.00#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.197.07:31:08.00#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.197.07:31:08.00#ibcon#ireg 7 cls_cnt 0 2006.197.07:31:08.00#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.197.07:31:08.12#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.197.07:31:08.12#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.197.07:31:08.12#ibcon#enter wrdev, iclass 11, count 0 2006.197.07:31:08.12#ibcon#first serial, iclass 11, count 0 2006.197.07:31:08.12#ibcon#enter sib2, iclass 11, count 0 2006.197.07:31:08.12#ibcon#flushed, iclass 11, count 0 2006.197.07:31:08.12#ibcon#about to write, iclass 11, count 0 2006.197.07:31:08.12#ibcon#wrote, iclass 11, count 0 2006.197.07:31:08.12#ibcon#about to read 3, iclass 11, count 0 2006.197.07:31:08.14#ibcon#read 3, iclass 11, count 0 2006.197.07:31:08.14#ibcon#about to read 4, iclass 11, count 0 2006.197.07:31:08.14#ibcon#read 4, iclass 11, count 0 2006.197.07:31:08.14#ibcon#about to read 5, iclass 11, count 0 2006.197.07:31:08.14#ibcon#read 5, iclass 11, count 0 2006.197.07:31:08.14#ibcon#about to read 6, iclass 11, count 0 2006.197.07:31:08.14#ibcon#read 6, iclass 11, count 0 2006.197.07:31:08.14#ibcon#end of sib2, iclass 11, count 0 2006.197.07:31:08.14#ibcon#*mode == 0, iclass 11, count 0 2006.197.07:31:08.14#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.197.07:31:08.14#ibcon#[25=USB\r\n] 2006.197.07:31:08.14#ibcon#*before write, iclass 11, count 0 2006.197.07:31:08.14#ibcon#enter sib2, iclass 11, count 0 2006.197.07:31:08.14#ibcon#flushed, iclass 11, count 0 2006.197.07:31:08.14#ibcon#about to write, iclass 11, count 0 2006.197.07:31:08.14#ibcon#wrote, iclass 11, count 0 2006.197.07:31:08.14#ibcon#about to read 3, iclass 11, count 0 2006.197.07:31:08.16#abcon#<5=/04 2.8 6.6 25.94 981003.0\r\n> 2006.197.07:31:08.17#ibcon#read 3, iclass 11, count 0 2006.197.07:31:08.17#ibcon#about to read 4, iclass 11, count 0 2006.197.07:31:08.17#ibcon#read 4, iclass 11, count 0 2006.197.07:31:08.17#ibcon#about to read 5, iclass 11, count 0 2006.197.07:31:08.17#ibcon#read 5, iclass 11, count 0 2006.197.07:31:08.17#ibcon#about to read 6, iclass 11, count 0 2006.197.07:31:08.17#ibcon#read 6, iclass 11, count 0 2006.197.07:31:08.17#ibcon#end of sib2, iclass 11, count 0 2006.197.07:31:08.17#ibcon#*after write, iclass 11, count 0 2006.197.07:31:08.17#ibcon#*before return 0, iclass 11, count 0 2006.197.07:31:08.17#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.197.07:31:08.17#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.197.07:31:08.17#ibcon#about to clear, iclass 11 cls_cnt 0 2006.197.07:31:08.17#ibcon#cleared, iclass 11 cls_cnt 0 2006.197.07:31:08.17$vc4f8/valo=3,672.99 2006.197.07:31:08.17#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.197.07:31:08.17#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.197.07:31:08.17#ibcon#ireg 17 cls_cnt 0 2006.197.07:31:08.17#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.197.07:31:08.17#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.197.07:31:08.17#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.197.07:31:08.17#ibcon#enter wrdev, iclass 16, count 0 2006.197.07:31:08.17#ibcon#first serial, iclass 16, count 0 2006.197.07:31:08.17#ibcon#enter sib2, iclass 16, count 0 2006.197.07:31:08.17#ibcon#flushed, iclass 16, count 0 2006.197.07:31:08.17#ibcon#about to write, iclass 16, count 0 2006.197.07:31:08.17#ibcon#wrote, iclass 16, count 0 2006.197.07:31:08.17#ibcon#about to read 3, iclass 16, count 0 2006.197.07:31:08.18#abcon#{5=INTERFACE CLEAR} 2006.197.07:31:08.19#ibcon#read 3, iclass 16, count 0 2006.197.07:31:08.19#ibcon#about to read 4, iclass 16, count 0 2006.197.07:31:08.19#ibcon#read 4, iclass 16, count 0 2006.197.07:31:08.19#ibcon#about to read 5, iclass 16, count 0 2006.197.07:31:08.19#ibcon#read 5, iclass 16, count 0 2006.197.07:31:08.19#ibcon#about to read 6, iclass 16, count 0 2006.197.07:31:08.19#ibcon#read 6, iclass 16, count 0 2006.197.07:31:08.19#ibcon#end of sib2, iclass 16, count 0 2006.197.07:31:08.19#ibcon#*mode == 0, iclass 16, count 0 2006.197.07:31:08.19#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.197.07:31:08.19#ibcon#[26=FRQ=03,672.99\r\n] 2006.197.07:31:08.19#ibcon#*before write, iclass 16, count 0 2006.197.07:31:08.19#ibcon#enter sib2, iclass 16, count 0 2006.197.07:31:08.19#ibcon#flushed, iclass 16, count 0 2006.197.07:31:08.19#ibcon#about to write, iclass 16, count 0 2006.197.07:31:08.19#ibcon#wrote, iclass 16, count 0 2006.197.07:31:08.19#ibcon#about to read 3, iclass 16, count 0 2006.197.07:31:08.23#ibcon#read 3, iclass 16, count 0 2006.197.07:31:08.23#ibcon#about to read 4, iclass 16, count 0 2006.197.07:31:08.23#ibcon#read 4, iclass 16, count 0 2006.197.07:31:08.23#ibcon#about to read 5, iclass 16, count 0 2006.197.07:31:08.23#ibcon#read 5, iclass 16, count 0 2006.197.07:31:08.23#ibcon#about to read 6, iclass 16, count 0 2006.197.07:31:08.23#ibcon#read 6, iclass 16, count 0 2006.197.07:31:08.23#ibcon#end of sib2, iclass 16, count 0 2006.197.07:31:08.23#ibcon#*after write, iclass 16, count 0 2006.197.07:31:08.23#ibcon#*before return 0, iclass 16, count 0 2006.197.07:31:08.23#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.197.07:31:08.23#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.197.07:31:08.23#ibcon#about to clear, iclass 16 cls_cnt 0 2006.197.07:31:08.23#ibcon#cleared, iclass 16 cls_cnt 0 2006.197.07:31:08.23$vc4f8/va=3,6 2006.197.07:31:08.23#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.197.07:31:08.23#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.197.07:31:08.23#ibcon#ireg 11 cls_cnt 2 2006.197.07:31:08.23#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.197.07:31:08.24#abcon#[5=S1D000X0/0*\r\n] 2006.197.07:31:08.29#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.197.07:31:08.29#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.197.07:31:08.29#ibcon#enter wrdev, iclass 19, count 2 2006.197.07:31:08.29#ibcon#first serial, iclass 19, count 2 2006.197.07:31:08.29#ibcon#enter sib2, iclass 19, count 2 2006.197.07:31:08.29#ibcon#flushed, iclass 19, count 2 2006.197.07:31:08.29#ibcon#about to write, iclass 19, count 2 2006.197.07:31:08.29#ibcon#wrote, iclass 19, count 2 2006.197.07:31:08.29#ibcon#about to read 3, iclass 19, count 2 2006.197.07:31:08.31#ibcon#read 3, iclass 19, count 2 2006.197.07:31:08.31#ibcon#about to read 4, iclass 19, count 2 2006.197.07:31:08.31#ibcon#read 4, iclass 19, count 2 2006.197.07:31:08.31#ibcon#about to read 5, iclass 19, count 2 2006.197.07:31:08.31#ibcon#read 5, iclass 19, count 2 2006.197.07:31:08.31#ibcon#about to read 6, iclass 19, count 2 2006.197.07:31:08.31#ibcon#read 6, iclass 19, count 2 2006.197.07:31:08.31#ibcon#end of sib2, iclass 19, count 2 2006.197.07:31:08.31#ibcon#*mode == 0, iclass 19, count 2 2006.197.07:31:08.31#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.197.07:31:08.31#ibcon#[25=AT03-06\r\n] 2006.197.07:31:08.31#ibcon#*before write, iclass 19, count 2 2006.197.07:31:08.31#ibcon#enter sib2, iclass 19, count 2 2006.197.07:31:08.31#ibcon#flushed, iclass 19, count 2 2006.197.07:31:08.31#ibcon#about to write, iclass 19, count 2 2006.197.07:31:08.31#ibcon#wrote, iclass 19, count 2 2006.197.07:31:08.31#ibcon#about to read 3, iclass 19, count 2 2006.197.07:31:08.34#ibcon#read 3, iclass 19, count 2 2006.197.07:31:08.34#ibcon#about to read 4, iclass 19, count 2 2006.197.07:31:08.34#ibcon#read 4, iclass 19, count 2 2006.197.07:31:08.34#ibcon#about to read 5, iclass 19, count 2 2006.197.07:31:08.34#ibcon#read 5, iclass 19, count 2 2006.197.07:31:08.34#ibcon#about to read 6, iclass 19, count 2 2006.197.07:31:08.34#ibcon#read 6, iclass 19, count 2 2006.197.07:31:08.34#ibcon#end of sib2, iclass 19, count 2 2006.197.07:31:08.34#ibcon#*after write, iclass 19, count 2 2006.197.07:31:08.34#ibcon#*before return 0, iclass 19, count 2 2006.197.07:31:08.34#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.197.07:31:08.34#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.197.07:31:08.34#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.197.07:31:08.34#ibcon#ireg 7 cls_cnt 0 2006.197.07:31:08.34#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.197.07:31:08.46#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.197.07:31:08.46#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.197.07:31:08.46#ibcon#enter wrdev, iclass 19, count 0 2006.197.07:31:08.46#ibcon#first serial, iclass 19, count 0 2006.197.07:31:08.46#ibcon#enter sib2, iclass 19, count 0 2006.197.07:31:08.46#ibcon#flushed, iclass 19, count 0 2006.197.07:31:08.46#ibcon#about to write, iclass 19, count 0 2006.197.07:31:08.46#ibcon#wrote, iclass 19, count 0 2006.197.07:31:08.46#ibcon#about to read 3, iclass 19, count 0 2006.197.07:31:08.48#ibcon#read 3, iclass 19, count 0 2006.197.07:31:08.48#ibcon#about to read 4, iclass 19, count 0 2006.197.07:31:08.48#ibcon#read 4, iclass 19, count 0 2006.197.07:31:08.48#ibcon#about to read 5, iclass 19, count 0 2006.197.07:31:08.48#ibcon#read 5, iclass 19, count 0 2006.197.07:31:08.48#ibcon#about to read 6, iclass 19, count 0 2006.197.07:31:08.48#ibcon#read 6, iclass 19, count 0 2006.197.07:31:08.48#ibcon#end of sib2, iclass 19, count 0 2006.197.07:31:08.48#ibcon#*mode == 0, iclass 19, count 0 2006.197.07:31:08.48#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.197.07:31:08.48#ibcon#[25=USB\r\n] 2006.197.07:31:08.48#ibcon#*before write, iclass 19, count 0 2006.197.07:31:08.48#ibcon#enter sib2, iclass 19, count 0 2006.197.07:31:08.48#ibcon#flushed, iclass 19, count 0 2006.197.07:31:08.48#ibcon#about to write, iclass 19, count 0 2006.197.07:31:08.48#ibcon#wrote, iclass 19, count 0 2006.197.07:31:08.48#ibcon#about to read 3, iclass 19, count 0 2006.197.07:31:08.51#ibcon#read 3, iclass 19, count 0 2006.197.07:31:08.51#ibcon#about to read 4, iclass 19, count 0 2006.197.07:31:08.51#ibcon#read 4, iclass 19, count 0 2006.197.07:31:08.51#ibcon#about to read 5, iclass 19, count 0 2006.197.07:31:08.51#ibcon#read 5, iclass 19, count 0 2006.197.07:31:08.51#ibcon#about to read 6, iclass 19, count 0 2006.197.07:31:08.51#ibcon#read 6, iclass 19, count 0 2006.197.07:31:08.51#ibcon#end of sib2, iclass 19, count 0 2006.197.07:31:08.51#ibcon#*after write, iclass 19, count 0 2006.197.07:31:08.51#ibcon#*before return 0, iclass 19, count 0 2006.197.07:31:08.51#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.197.07:31:08.51#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.197.07:31:08.51#ibcon#about to clear, iclass 19 cls_cnt 0 2006.197.07:31:08.51#ibcon#cleared, iclass 19 cls_cnt 0 2006.197.07:31:08.51$vc4f8/valo=4,832.99 2006.197.07:31:08.51#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.197.07:31:08.51#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.197.07:31:08.51#ibcon#ireg 17 cls_cnt 0 2006.197.07:31:08.51#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.197.07:31:08.51#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.197.07:31:08.51#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.197.07:31:08.51#ibcon#enter wrdev, iclass 21, count 0 2006.197.07:31:08.51#ibcon#first serial, iclass 21, count 0 2006.197.07:31:08.51#ibcon#enter sib2, iclass 21, count 0 2006.197.07:31:08.51#ibcon#flushed, iclass 21, count 0 2006.197.07:31:08.51#ibcon#about to write, iclass 21, count 0 2006.197.07:31:08.51#ibcon#wrote, iclass 21, count 0 2006.197.07:31:08.51#ibcon#about to read 3, iclass 21, count 0 2006.197.07:31:08.53#ibcon#read 3, iclass 21, count 0 2006.197.07:31:08.53#ibcon#about to read 4, iclass 21, count 0 2006.197.07:31:08.53#ibcon#read 4, iclass 21, count 0 2006.197.07:31:08.53#ibcon#about to read 5, iclass 21, count 0 2006.197.07:31:08.53#ibcon#read 5, iclass 21, count 0 2006.197.07:31:08.53#ibcon#about to read 6, iclass 21, count 0 2006.197.07:31:08.53#ibcon#read 6, iclass 21, count 0 2006.197.07:31:08.53#ibcon#end of sib2, iclass 21, count 0 2006.197.07:31:08.53#ibcon#*mode == 0, iclass 21, count 0 2006.197.07:31:08.53#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.197.07:31:08.53#ibcon#[26=FRQ=04,832.99\r\n] 2006.197.07:31:08.53#ibcon#*before write, iclass 21, count 0 2006.197.07:31:08.53#ibcon#enter sib2, iclass 21, count 0 2006.197.07:31:08.53#ibcon#flushed, iclass 21, count 0 2006.197.07:31:08.53#ibcon#about to write, iclass 21, count 0 2006.197.07:31:08.53#ibcon#wrote, iclass 21, count 0 2006.197.07:31:08.53#ibcon#about to read 3, iclass 21, count 0 2006.197.07:31:08.57#ibcon#read 3, iclass 21, count 0 2006.197.07:31:08.57#ibcon#about to read 4, iclass 21, count 0 2006.197.07:31:08.57#ibcon#read 4, iclass 21, count 0 2006.197.07:31:08.57#ibcon#about to read 5, iclass 21, count 0 2006.197.07:31:08.57#ibcon#read 5, iclass 21, count 0 2006.197.07:31:08.57#ibcon#about to read 6, iclass 21, count 0 2006.197.07:31:08.57#ibcon#read 6, iclass 21, count 0 2006.197.07:31:08.57#ibcon#end of sib2, iclass 21, count 0 2006.197.07:31:08.57#ibcon#*after write, iclass 21, count 0 2006.197.07:31:08.57#ibcon#*before return 0, iclass 21, count 0 2006.197.07:31:08.57#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.197.07:31:08.57#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.197.07:31:08.57#ibcon#about to clear, iclass 21 cls_cnt 0 2006.197.07:31:08.57#ibcon#cleared, iclass 21 cls_cnt 0 2006.197.07:31:08.57$vc4f8/va=4,7 2006.197.07:31:08.57#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.197.07:31:08.57#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.197.07:31:08.57#ibcon#ireg 11 cls_cnt 2 2006.197.07:31:08.57#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.197.07:31:08.63#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.197.07:31:08.63#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.197.07:31:08.63#ibcon#enter wrdev, iclass 23, count 2 2006.197.07:31:08.63#ibcon#first serial, iclass 23, count 2 2006.197.07:31:08.63#ibcon#enter sib2, iclass 23, count 2 2006.197.07:31:08.63#ibcon#flushed, iclass 23, count 2 2006.197.07:31:08.63#ibcon#about to write, iclass 23, count 2 2006.197.07:31:08.63#ibcon#wrote, iclass 23, count 2 2006.197.07:31:08.63#ibcon#about to read 3, iclass 23, count 2 2006.197.07:31:08.65#ibcon#read 3, iclass 23, count 2 2006.197.07:31:08.65#ibcon#about to read 4, iclass 23, count 2 2006.197.07:31:08.65#ibcon#read 4, iclass 23, count 2 2006.197.07:31:08.65#ibcon#about to read 5, iclass 23, count 2 2006.197.07:31:08.65#ibcon#read 5, iclass 23, count 2 2006.197.07:31:08.65#ibcon#about to read 6, iclass 23, count 2 2006.197.07:31:08.65#ibcon#read 6, iclass 23, count 2 2006.197.07:31:08.65#ibcon#end of sib2, iclass 23, count 2 2006.197.07:31:08.65#ibcon#*mode == 0, iclass 23, count 2 2006.197.07:31:08.65#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.197.07:31:08.65#ibcon#[25=AT04-07\r\n] 2006.197.07:31:08.65#ibcon#*before write, iclass 23, count 2 2006.197.07:31:08.65#ibcon#enter sib2, iclass 23, count 2 2006.197.07:31:08.65#ibcon#flushed, iclass 23, count 2 2006.197.07:31:08.65#ibcon#about to write, iclass 23, count 2 2006.197.07:31:08.65#ibcon#wrote, iclass 23, count 2 2006.197.07:31:08.65#ibcon#about to read 3, iclass 23, count 2 2006.197.07:31:08.68#ibcon#read 3, iclass 23, count 2 2006.197.07:31:08.68#ibcon#about to read 4, iclass 23, count 2 2006.197.07:31:08.68#ibcon#read 4, iclass 23, count 2 2006.197.07:31:08.68#ibcon#about to read 5, iclass 23, count 2 2006.197.07:31:08.68#ibcon#read 5, iclass 23, count 2 2006.197.07:31:08.68#ibcon#about to read 6, iclass 23, count 2 2006.197.07:31:08.68#ibcon#read 6, iclass 23, count 2 2006.197.07:31:08.68#ibcon#end of sib2, iclass 23, count 2 2006.197.07:31:08.68#ibcon#*after write, iclass 23, count 2 2006.197.07:31:08.68#ibcon#*before return 0, iclass 23, count 2 2006.197.07:31:08.68#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.197.07:31:08.68#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.197.07:31:08.68#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.197.07:31:08.68#ibcon#ireg 7 cls_cnt 0 2006.197.07:31:08.68#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.197.07:31:08.80#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.197.07:31:08.80#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.197.07:31:08.80#ibcon#enter wrdev, iclass 23, count 0 2006.197.07:31:08.80#ibcon#first serial, iclass 23, count 0 2006.197.07:31:08.80#ibcon#enter sib2, iclass 23, count 0 2006.197.07:31:08.80#ibcon#flushed, iclass 23, count 0 2006.197.07:31:08.80#ibcon#about to write, iclass 23, count 0 2006.197.07:31:08.80#ibcon#wrote, iclass 23, count 0 2006.197.07:31:08.80#ibcon#about to read 3, iclass 23, count 0 2006.197.07:31:08.82#ibcon#read 3, iclass 23, count 0 2006.197.07:31:08.82#ibcon#about to read 4, iclass 23, count 0 2006.197.07:31:08.82#ibcon#read 4, iclass 23, count 0 2006.197.07:31:08.82#ibcon#about to read 5, iclass 23, count 0 2006.197.07:31:08.82#ibcon#read 5, iclass 23, count 0 2006.197.07:31:08.82#ibcon#about to read 6, iclass 23, count 0 2006.197.07:31:08.82#ibcon#read 6, iclass 23, count 0 2006.197.07:31:08.82#ibcon#end of sib2, iclass 23, count 0 2006.197.07:31:08.82#ibcon#*mode == 0, iclass 23, count 0 2006.197.07:31:08.82#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.197.07:31:08.82#ibcon#[25=USB\r\n] 2006.197.07:31:08.82#ibcon#*before write, iclass 23, count 0 2006.197.07:31:08.82#ibcon#enter sib2, iclass 23, count 0 2006.197.07:31:08.82#ibcon#flushed, iclass 23, count 0 2006.197.07:31:08.82#ibcon#about to write, iclass 23, count 0 2006.197.07:31:08.82#ibcon#wrote, iclass 23, count 0 2006.197.07:31:08.82#ibcon#about to read 3, iclass 23, count 0 2006.197.07:31:08.85#ibcon#read 3, iclass 23, count 0 2006.197.07:31:08.85#ibcon#about to read 4, iclass 23, count 0 2006.197.07:31:08.85#ibcon#read 4, iclass 23, count 0 2006.197.07:31:08.85#ibcon#about to read 5, iclass 23, count 0 2006.197.07:31:08.85#ibcon#read 5, iclass 23, count 0 2006.197.07:31:08.85#ibcon#about to read 6, iclass 23, count 0 2006.197.07:31:08.85#ibcon#read 6, iclass 23, count 0 2006.197.07:31:08.85#ibcon#end of sib2, iclass 23, count 0 2006.197.07:31:08.85#ibcon#*after write, iclass 23, count 0 2006.197.07:31:08.85#ibcon#*before return 0, iclass 23, count 0 2006.197.07:31:08.85#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.197.07:31:08.85#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.197.07:31:08.85#ibcon#about to clear, iclass 23 cls_cnt 0 2006.197.07:31:08.85#ibcon#cleared, iclass 23 cls_cnt 0 2006.197.07:31:08.85$vc4f8/valo=5,652.99 2006.197.07:31:08.85#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.197.07:31:08.85#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.197.07:31:08.85#ibcon#ireg 17 cls_cnt 0 2006.197.07:31:08.85#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.197.07:31:08.85#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.197.07:31:08.85#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.197.07:31:08.85#ibcon#enter wrdev, iclass 25, count 0 2006.197.07:31:08.85#ibcon#first serial, iclass 25, count 0 2006.197.07:31:08.85#ibcon#enter sib2, iclass 25, count 0 2006.197.07:31:08.85#ibcon#flushed, iclass 25, count 0 2006.197.07:31:08.85#ibcon#about to write, iclass 25, count 0 2006.197.07:31:08.85#ibcon#wrote, iclass 25, count 0 2006.197.07:31:08.85#ibcon#about to read 3, iclass 25, count 0 2006.197.07:31:08.87#ibcon#read 3, iclass 25, count 0 2006.197.07:31:08.87#ibcon#about to read 4, iclass 25, count 0 2006.197.07:31:08.87#ibcon#read 4, iclass 25, count 0 2006.197.07:31:08.87#ibcon#about to read 5, iclass 25, count 0 2006.197.07:31:08.87#ibcon#read 5, iclass 25, count 0 2006.197.07:31:08.87#ibcon#about to read 6, iclass 25, count 0 2006.197.07:31:08.87#ibcon#read 6, iclass 25, count 0 2006.197.07:31:08.87#ibcon#end of sib2, iclass 25, count 0 2006.197.07:31:08.87#ibcon#*mode == 0, iclass 25, count 0 2006.197.07:31:08.87#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.197.07:31:08.87#ibcon#[26=FRQ=05,652.99\r\n] 2006.197.07:31:08.87#ibcon#*before write, iclass 25, count 0 2006.197.07:31:08.87#ibcon#enter sib2, iclass 25, count 0 2006.197.07:31:08.87#ibcon#flushed, iclass 25, count 0 2006.197.07:31:08.87#ibcon#about to write, iclass 25, count 0 2006.197.07:31:08.87#ibcon#wrote, iclass 25, count 0 2006.197.07:31:08.87#ibcon#about to read 3, iclass 25, count 0 2006.197.07:31:08.91#ibcon#read 3, iclass 25, count 0 2006.197.07:31:08.91#ibcon#about to read 4, iclass 25, count 0 2006.197.07:31:08.91#ibcon#read 4, iclass 25, count 0 2006.197.07:31:08.91#ibcon#about to read 5, iclass 25, count 0 2006.197.07:31:08.91#ibcon#read 5, iclass 25, count 0 2006.197.07:31:08.91#ibcon#about to read 6, iclass 25, count 0 2006.197.07:31:08.91#ibcon#read 6, iclass 25, count 0 2006.197.07:31:08.91#ibcon#end of sib2, iclass 25, count 0 2006.197.07:31:08.91#ibcon#*after write, iclass 25, count 0 2006.197.07:31:08.91#ibcon#*before return 0, iclass 25, count 0 2006.197.07:31:08.91#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.197.07:31:08.91#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.197.07:31:08.91#ibcon#about to clear, iclass 25 cls_cnt 0 2006.197.07:31:08.91#ibcon#cleared, iclass 25 cls_cnt 0 2006.197.07:31:08.91$vc4f8/va=5,7 2006.197.07:31:08.91#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.197.07:31:08.91#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.197.07:31:08.91#ibcon#ireg 11 cls_cnt 2 2006.197.07:31:08.91#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.197.07:31:08.97#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.197.07:31:08.97#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.197.07:31:08.97#ibcon#enter wrdev, iclass 27, count 2 2006.197.07:31:08.97#ibcon#first serial, iclass 27, count 2 2006.197.07:31:08.97#ibcon#enter sib2, iclass 27, count 2 2006.197.07:31:08.97#ibcon#flushed, iclass 27, count 2 2006.197.07:31:08.97#ibcon#about to write, iclass 27, count 2 2006.197.07:31:08.97#ibcon#wrote, iclass 27, count 2 2006.197.07:31:08.97#ibcon#about to read 3, iclass 27, count 2 2006.197.07:31:08.99#ibcon#read 3, iclass 27, count 2 2006.197.07:31:08.99#ibcon#about to read 4, iclass 27, count 2 2006.197.07:31:08.99#ibcon#read 4, iclass 27, count 2 2006.197.07:31:08.99#ibcon#about to read 5, iclass 27, count 2 2006.197.07:31:08.99#ibcon#read 5, iclass 27, count 2 2006.197.07:31:08.99#ibcon#about to read 6, iclass 27, count 2 2006.197.07:31:08.99#ibcon#read 6, iclass 27, count 2 2006.197.07:31:08.99#ibcon#end of sib2, iclass 27, count 2 2006.197.07:31:08.99#ibcon#*mode == 0, iclass 27, count 2 2006.197.07:31:08.99#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.197.07:31:08.99#ibcon#[25=AT05-07\r\n] 2006.197.07:31:08.99#ibcon#*before write, iclass 27, count 2 2006.197.07:31:08.99#ibcon#enter sib2, iclass 27, count 2 2006.197.07:31:08.99#ibcon#flushed, iclass 27, count 2 2006.197.07:31:08.99#ibcon#about to write, iclass 27, count 2 2006.197.07:31:08.99#ibcon#wrote, iclass 27, count 2 2006.197.07:31:08.99#ibcon#about to read 3, iclass 27, count 2 2006.197.07:31:09.02#ibcon#read 3, iclass 27, count 2 2006.197.07:31:09.02#ibcon#about to read 4, iclass 27, count 2 2006.197.07:31:09.02#ibcon#read 4, iclass 27, count 2 2006.197.07:31:09.02#ibcon#about to read 5, iclass 27, count 2 2006.197.07:31:09.02#ibcon#read 5, iclass 27, count 2 2006.197.07:31:09.02#ibcon#about to read 6, iclass 27, count 2 2006.197.07:31:09.02#ibcon#read 6, iclass 27, count 2 2006.197.07:31:09.02#ibcon#end of sib2, iclass 27, count 2 2006.197.07:31:09.02#ibcon#*after write, iclass 27, count 2 2006.197.07:31:09.02#ibcon#*before return 0, iclass 27, count 2 2006.197.07:31:09.02#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.197.07:31:09.02#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.197.07:31:09.02#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.197.07:31:09.02#ibcon#ireg 7 cls_cnt 0 2006.197.07:31:09.02#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.197.07:31:09.14#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.197.07:31:09.14#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.197.07:31:09.14#ibcon#enter wrdev, iclass 27, count 0 2006.197.07:31:09.14#ibcon#first serial, iclass 27, count 0 2006.197.07:31:09.14#ibcon#enter sib2, iclass 27, count 0 2006.197.07:31:09.14#ibcon#flushed, iclass 27, count 0 2006.197.07:31:09.14#ibcon#about to write, iclass 27, count 0 2006.197.07:31:09.14#ibcon#wrote, iclass 27, count 0 2006.197.07:31:09.14#ibcon#about to read 3, iclass 27, count 0 2006.197.07:31:09.16#ibcon#read 3, iclass 27, count 0 2006.197.07:31:09.16#ibcon#about to read 4, iclass 27, count 0 2006.197.07:31:09.16#ibcon#read 4, iclass 27, count 0 2006.197.07:31:09.16#ibcon#about to read 5, iclass 27, count 0 2006.197.07:31:09.16#ibcon#read 5, iclass 27, count 0 2006.197.07:31:09.16#ibcon#about to read 6, iclass 27, count 0 2006.197.07:31:09.16#ibcon#read 6, iclass 27, count 0 2006.197.07:31:09.16#ibcon#end of sib2, iclass 27, count 0 2006.197.07:31:09.16#ibcon#*mode == 0, iclass 27, count 0 2006.197.07:31:09.16#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.197.07:31:09.16#ibcon#[25=USB\r\n] 2006.197.07:31:09.16#ibcon#*before write, iclass 27, count 0 2006.197.07:31:09.16#ibcon#enter sib2, iclass 27, count 0 2006.197.07:31:09.16#ibcon#flushed, iclass 27, count 0 2006.197.07:31:09.16#ibcon#about to write, iclass 27, count 0 2006.197.07:31:09.16#ibcon#wrote, iclass 27, count 0 2006.197.07:31:09.16#ibcon#about to read 3, iclass 27, count 0 2006.197.07:31:09.19#ibcon#read 3, iclass 27, count 0 2006.197.07:31:09.19#ibcon#about to read 4, iclass 27, count 0 2006.197.07:31:09.19#ibcon#read 4, iclass 27, count 0 2006.197.07:31:09.19#ibcon#about to read 5, iclass 27, count 0 2006.197.07:31:09.19#ibcon#read 5, iclass 27, count 0 2006.197.07:31:09.19#ibcon#about to read 6, iclass 27, count 0 2006.197.07:31:09.19#ibcon#read 6, iclass 27, count 0 2006.197.07:31:09.19#ibcon#end of sib2, iclass 27, count 0 2006.197.07:31:09.19#ibcon#*after write, iclass 27, count 0 2006.197.07:31:09.19#ibcon#*before return 0, iclass 27, count 0 2006.197.07:31:09.19#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.197.07:31:09.19#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.197.07:31:09.19#ibcon#about to clear, iclass 27 cls_cnt 0 2006.197.07:31:09.19#ibcon#cleared, iclass 27 cls_cnt 0 2006.197.07:31:09.19$vc4f8/valo=6,772.99 2006.197.07:31:09.19#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.197.07:31:09.19#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.197.07:31:09.19#ibcon#ireg 17 cls_cnt 0 2006.197.07:31:09.19#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.197.07:31:09.19#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.197.07:31:09.19#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.197.07:31:09.19#ibcon#enter wrdev, iclass 29, count 0 2006.197.07:31:09.19#ibcon#first serial, iclass 29, count 0 2006.197.07:31:09.19#ibcon#enter sib2, iclass 29, count 0 2006.197.07:31:09.19#ibcon#flushed, iclass 29, count 0 2006.197.07:31:09.19#ibcon#about to write, iclass 29, count 0 2006.197.07:31:09.19#ibcon#wrote, iclass 29, count 0 2006.197.07:31:09.19#ibcon#about to read 3, iclass 29, count 0 2006.197.07:31:09.21#ibcon#read 3, iclass 29, count 0 2006.197.07:31:09.21#ibcon#about to read 4, iclass 29, count 0 2006.197.07:31:09.21#ibcon#read 4, iclass 29, count 0 2006.197.07:31:09.21#ibcon#about to read 5, iclass 29, count 0 2006.197.07:31:09.21#ibcon#read 5, iclass 29, count 0 2006.197.07:31:09.21#ibcon#about to read 6, iclass 29, count 0 2006.197.07:31:09.21#ibcon#read 6, iclass 29, count 0 2006.197.07:31:09.21#ibcon#end of sib2, iclass 29, count 0 2006.197.07:31:09.21#ibcon#*mode == 0, iclass 29, count 0 2006.197.07:31:09.21#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.197.07:31:09.21#ibcon#[26=FRQ=06,772.99\r\n] 2006.197.07:31:09.21#ibcon#*before write, iclass 29, count 0 2006.197.07:31:09.21#ibcon#enter sib2, iclass 29, count 0 2006.197.07:31:09.21#ibcon#flushed, iclass 29, count 0 2006.197.07:31:09.21#ibcon#about to write, iclass 29, count 0 2006.197.07:31:09.21#ibcon#wrote, iclass 29, count 0 2006.197.07:31:09.21#ibcon#about to read 3, iclass 29, count 0 2006.197.07:31:09.25#ibcon#read 3, iclass 29, count 0 2006.197.07:31:09.25#ibcon#about to read 4, iclass 29, count 0 2006.197.07:31:09.25#ibcon#read 4, iclass 29, count 0 2006.197.07:31:09.25#ibcon#about to read 5, iclass 29, count 0 2006.197.07:31:09.25#ibcon#read 5, iclass 29, count 0 2006.197.07:31:09.25#ibcon#about to read 6, iclass 29, count 0 2006.197.07:31:09.25#ibcon#read 6, iclass 29, count 0 2006.197.07:31:09.25#ibcon#end of sib2, iclass 29, count 0 2006.197.07:31:09.25#ibcon#*after write, iclass 29, count 0 2006.197.07:31:09.25#ibcon#*before return 0, iclass 29, count 0 2006.197.07:31:09.25#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.197.07:31:09.25#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.197.07:31:09.25#ibcon#about to clear, iclass 29 cls_cnt 0 2006.197.07:31:09.25#ibcon#cleared, iclass 29 cls_cnt 0 2006.197.07:31:09.25$vc4f8/va=6,6 2006.197.07:31:09.25#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.197.07:31:09.25#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.197.07:31:09.25#ibcon#ireg 11 cls_cnt 2 2006.197.07:31:09.25#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.197.07:31:09.31#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.197.07:31:09.31#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.197.07:31:09.31#ibcon#enter wrdev, iclass 31, count 2 2006.197.07:31:09.31#ibcon#first serial, iclass 31, count 2 2006.197.07:31:09.31#ibcon#enter sib2, iclass 31, count 2 2006.197.07:31:09.31#ibcon#flushed, iclass 31, count 2 2006.197.07:31:09.31#ibcon#about to write, iclass 31, count 2 2006.197.07:31:09.31#ibcon#wrote, iclass 31, count 2 2006.197.07:31:09.31#ibcon#about to read 3, iclass 31, count 2 2006.197.07:31:09.33#ibcon#read 3, iclass 31, count 2 2006.197.07:31:09.33#ibcon#about to read 4, iclass 31, count 2 2006.197.07:31:09.33#ibcon#read 4, iclass 31, count 2 2006.197.07:31:09.33#ibcon#about to read 5, iclass 31, count 2 2006.197.07:31:09.33#ibcon#read 5, iclass 31, count 2 2006.197.07:31:09.33#ibcon#about to read 6, iclass 31, count 2 2006.197.07:31:09.33#ibcon#read 6, iclass 31, count 2 2006.197.07:31:09.33#ibcon#end of sib2, iclass 31, count 2 2006.197.07:31:09.33#ibcon#*mode == 0, iclass 31, count 2 2006.197.07:31:09.33#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.197.07:31:09.33#ibcon#[25=AT06-06\r\n] 2006.197.07:31:09.33#ibcon#*before write, iclass 31, count 2 2006.197.07:31:09.33#ibcon#enter sib2, iclass 31, count 2 2006.197.07:31:09.33#ibcon#flushed, iclass 31, count 2 2006.197.07:31:09.33#ibcon#about to write, iclass 31, count 2 2006.197.07:31:09.33#ibcon#wrote, iclass 31, count 2 2006.197.07:31:09.33#ibcon#about to read 3, iclass 31, count 2 2006.197.07:31:09.36#ibcon#read 3, iclass 31, count 2 2006.197.07:31:09.36#ibcon#about to read 4, iclass 31, count 2 2006.197.07:31:09.36#ibcon#read 4, iclass 31, count 2 2006.197.07:31:09.36#ibcon#about to read 5, iclass 31, count 2 2006.197.07:31:09.36#ibcon#read 5, iclass 31, count 2 2006.197.07:31:09.36#ibcon#about to read 6, iclass 31, count 2 2006.197.07:31:09.36#ibcon#read 6, iclass 31, count 2 2006.197.07:31:09.36#ibcon#end of sib2, iclass 31, count 2 2006.197.07:31:09.36#ibcon#*after write, iclass 31, count 2 2006.197.07:31:09.36#ibcon#*before return 0, iclass 31, count 2 2006.197.07:31:09.36#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.197.07:31:09.36#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.197.07:31:09.36#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.197.07:31:09.36#ibcon#ireg 7 cls_cnt 0 2006.197.07:31:09.36#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.197.07:31:09.48#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.197.07:31:09.48#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.197.07:31:09.48#ibcon#enter wrdev, iclass 31, count 0 2006.197.07:31:09.48#ibcon#first serial, iclass 31, count 0 2006.197.07:31:09.48#ibcon#enter sib2, iclass 31, count 0 2006.197.07:31:09.48#ibcon#flushed, iclass 31, count 0 2006.197.07:31:09.48#ibcon#about to write, iclass 31, count 0 2006.197.07:31:09.48#ibcon#wrote, iclass 31, count 0 2006.197.07:31:09.48#ibcon#about to read 3, iclass 31, count 0 2006.197.07:31:09.50#ibcon#read 3, iclass 31, count 0 2006.197.07:31:09.50#ibcon#about to read 4, iclass 31, count 0 2006.197.07:31:09.50#ibcon#read 4, iclass 31, count 0 2006.197.07:31:09.50#ibcon#about to read 5, iclass 31, count 0 2006.197.07:31:09.50#ibcon#read 5, iclass 31, count 0 2006.197.07:31:09.50#ibcon#about to read 6, iclass 31, count 0 2006.197.07:31:09.50#ibcon#read 6, iclass 31, count 0 2006.197.07:31:09.50#ibcon#end of sib2, iclass 31, count 0 2006.197.07:31:09.50#ibcon#*mode == 0, iclass 31, count 0 2006.197.07:31:09.50#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.197.07:31:09.50#ibcon#[25=USB\r\n] 2006.197.07:31:09.50#ibcon#*before write, iclass 31, count 0 2006.197.07:31:09.50#ibcon#enter sib2, iclass 31, count 0 2006.197.07:31:09.50#ibcon#flushed, iclass 31, count 0 2006.197.07:31:09.50#ibcon#about to write, iclass 31, count 0 2006.197.07:31:09.50#ibcon#wrote, iclass 31, count 0 2006.197.07:31:09.50#ibcon#about to read 3, iclass 31, count 0 2006.197.07:31:09.53#ibcon#read 3, iclass 31, count 0 2006.197.07:31:09.53#ibcon#about to read 4, iclass 31, count 0 2006.197.07:31:09.53#ibcon#read 4, iclass 31, count 0 2006.197.07:31:09.53#ibcon#about to read 5, iclass 31, count 0 2006.197.07:31:09.53#ibcon#read 5, iclass 31, count 0 2006.197.07:31:09.53#ibcon#about to read 6, iclass 31, count 0 2006.197.07:31:09.53#ibcon#read 6, iclass 31, count 0 2006.197.07:31:09.53#ibcon#end of sib2, iclass 31, count 0 2006.197.07:31:09.53#ibcon#*after write, iclass 31, count 0 2006.197.07:31:09.53#ibcon#*before return 0, iclass 31, count 0 2006.197.07:31:09.53#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.197.07:31:09.53#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.197.07:31:09.53#ibcon#about to clear, iclass 31 cls_cnt 0 2006.197.07:31:09.53#ibcon#cleared, iclass 31 cls_cnt 0 2006.197.07:31:09.53$vc4f8/valo=7,832.99 2006.197.07:31:09.53#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.197.07:31:09.53#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.197.07:31:09.53#ibcon#ireg 17 cls_cnt 0 2006.197.07:31:09.53#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.197.07:31:09.53#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.197.07:31:09.53#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.197.07:31:09.53#ibcon#enter wrdev, iclass 33, count 0 2006.197.07:31:09.53#ibcon#first serial, iclass 33, count 0 2006.197.07:31:09.53#ibcon#enter sib2, iclass 33, count 0 2006.197.07:31:09.53#ibcon#flushed, iclass 33, count 0 2006.197.07:31:09.53#ibcon#about to write, iclass 33, count 0 2006.197.07:31:09.53#ibcon#wrote, iclass 33, count 0 2006.197.07:31:09.53#ibcon#about to read 3, iclass 33, count 0 2006.197.07:31:09.55#ibcon#read 3, iclass 33, count 0 2006.197.07:31:09.55#ibcon#about to read 4, iclass 33, count 0 2006.197.07:31:09.55#ibcon#read 4, iclass 33, count 0 2006.197.07:31:09.55#ibcon#about to read 5, iclass 33, count 0 2006.197.07:31:09.55#ibcon#read 5, iclass 33, count 0 2006.197.07:31:09.55#ibcon#about to read 6, iclass 33, count 0 2006.197.07:31:09.55#ibcon#read 6, iclass 33, count 0 2006.197.07:31:09.55#ibcon#end of sib2, iclass 33, count 0 2006.197.07:31:09.55#ibcon#*mode == 0, iclass 33, count 0 2006.197.07:31:09.55#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.197.07:31:09.55#ibcon#[26=FRQ=07,832.99\r\n] 2006.197.07:31:09.55#ibcon#*before write, iclass 33, count 0 2006.197.07:31:09.55#ibcon#enter sib2, iclass 33, count 0 2006.197.07:31:09.55#ibcon#flushed, iclass 33, count 0 2006.197.07:31:09.55#ibcon#about to write, iclass 33, count 0 2006.197.07:31:09.55#ibcon#wrote, iclass 33, count 0 2006.197.07:31:09.55#ibcon#about to read 3, iclass 33, count 0 2006.197.07:31:09.59#ibcon#read 3, iclass 33, count 0 2006.197.07:31:09.59#ibcon#about to read 4, iclass 33, count 0 2006.197.07:31:09.59#ibcon#read 4, iclass 33, count 0 2006.197.07:31:09.59#ibcon#about to read 5, iclass 33, count 0 2006.197.07:31:09.59#ibcon#read 5, iclass 33, count 0 2006.197.07:31:09.59#ibcon#about to read 6, iclass 33, count 0 2006.197.07:31:09.59#ibcon#read 6, iclass 33, count 0 2006.197.07:31:09.59#ibcon#end of sib2, iclass 33, count 0 2006.197.07:31:09.59#ibcon#*after write, iclass 33, count 0 2006.197.07:31:09.59#ibcon#*before return 0, iclass 33, count 0 2006.197.07:31:09.59#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.197.07:31:09.59#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.197.07:31:09.59#ibcon#about to clear, iclass 33 cls_cnt 0 2006.197.07:31:09.59#ibcon#cleared, iclass 33 cls_cnt 0 2006.197.07:31:09.59$vc4f8/va=7,6 2006.197.07:31:09.59#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.197.07:31:09.59#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.197.07:31:09.59#ibcon#ireg 11 cls_cnt 2 2006.197.07:31:09.59#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.197.07:31:09.65#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.197.07:31:09.65#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.197.07:31:09.65#ibcon#enter wrdev, iclass 35, count 2 2006.197.07:31:09.65#ibcon#first serial, iclass 35, count 2 2006.197.07:31:09.65#ibcon#enter sib2, iclass 35, count 2 2006.197.07:31:09.65#ibcon#flushed, iclass 35, count 2 2006.197.07:31:09.65#ibcon#about to write, iclass 35, count 2 2006.197.07:31:09.65#ibcon#wrote, iclass 35, count 2 2006.197.07:31:09.65#ibcon#about to read 3, iclass 35, count 2 2006.197.07:31:09.67#ibcon#read 3, iclass 35, count 2 2006.197.07:31:09.67#ibcon#about to read 4, iclass 35, count 2 2006.197.07:31:09.67#ibcon#read 4, iclass 35, count 2 2006.197.07:31:09.67#ibcon#about to read 5, iclass 35, count 2 2006.197.07:31:09.67#ibcon#read 5, iclass 35, count 2 2006.197.07:31:09.67#ibcon#about to read 6, iclass 35, count 2 2006.197.07:31:09.67#ibcon#read 6, iclass 35, count 2 2006.197.07:31:09.67#ibcon#end of sib2, iclass 35, count 2 2006.197.07:31:09.67#ibcon#*mode == 0, iclass 35, count 2 2006.197.07:31:09.67#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.197.07:31:09.67#ibcon#[25=AT07-06\r\n] 2006.197.07:31:09.67#ibcon#*before write, iclass 35, count 2 2006.197.07:31:09.67#ibcon#enter sib2, iclass 35, count 2 2006.197.07:31:09.67#ibcon#flushed, iclass 35, count 2 2006.197.07:31:09.67#ibcon#about to write, iclass 35, count 2 2006.197.07:31:09.67#ibcon#wrote, iclass 35, count 2 2006.197.07:31:09.67#ibcon#about to read 3, iclass 35, count 2 2006.197.07:31:09.70#ibcon#read 3, iclass 35, count 2 2006.197.07:31:09.70#ibcon#about to read 4, iclass 35, count 2 2006.197.07:31:09.70#ibcon#read 4, iclass 35, count 2 2006.197.07:31:09.70#ibcon#about to read 5, iclass 35, count 2 2006.197.07:31:09.70#ibcon#read 5, iclass 35, count 2 2006.197.07:31:09.70#ibcon#about to read 6, iclass 35, count 2 2006.197.07:31:09.70#ibcon#read 6, iclass 35, count 2 2006.197.07:31:09.70#ibcon#end of sib2, iclass 35, count 2 2006.197.07:31:09.70#ibcon#*after write, iclass 35, count 2 2006.197.07:31:09.70#ibcon#*before return 0, iclass 35, count 2 2006.197.07:31:09.70#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.197.07:31:09.70#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.197.07:31:09.70#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.197.07:31:09.70#ibcon#ireg 7 cls_cnt 0 2006.197.07:31:09.70#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.197.07:31:09.82#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.197.07:31:09.82#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.197.07:31:09.82#ibcon#enter wrdev, iclass 35, count 0 2006.197.07:31:09.82#ibcon#first serial, iclass 35, count 0 2006.197.07:31:09.82#ibcon#enter sib2, iclass 35, count 0 2006.197.07:31:09.82#ibcon#flushed, iclass 35, count 0 2006.197.07:31:09.82#ibcon#about to write, iclass 35, count 0 2006.197.07:31:09.82#ibcon#wrote, iclass 35, count 0 2006.197.07:31:09.82#ibcon#about to read 3, iclass 35, count 0 2006.197.07:31:09.84#ibcon#read 3, iclass 35, count 0 2006.197.07:31:09.84#ibcon#about to read 4, iclass 35, count 0 2006.197.07:31:09.84#ibcon#read 4, iclass 35, count 0 2006.197.07:31:09.84#ibcon#about to read 5, iclass 35, count 0 2006.197.07:31:09.84#ibcon#read 5, iclass 35, count 0 2006.197.07:31:09.84#ibcon#about to read 6, iclass 35, count 0 2006.197.07:31:09.84#ibcon#read 6, iclass 35, count 0 2006.197.07:31:09.84#ibcon#end of sib2, iclass 35, count 0 2006.197.07:31:09.84#ibcon#*mode == 0, iclass 35, count 0 2006.197.07:31:09.84#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.197.07:31:09.84#ibcon#[25=USB\r\n] 2006.197.07:31:09.84#ibcon#*before write, iclass 35, count 0 2006.197.07:31:09.84#ibcon#enter sib2, iclass 35, count 0 2006.197.07:31:09.84#ibcon#flushed, iclass 35, count 0 2006.197.07:31:09.84#ibcon#about to write, iclass 35, count 0 2006.197.07:31:09.84#ibcon#wrote, iclass 35, count 0 2006.197.07:31:09.84#ibcon#about to read 3, iclass 35, count 0 2006.197.07:31:09.87#ibcon#read 3, iclass 35, count 0 2006.197.07:31:09.87#ibcon#about to read 4, iclass 35, count 0 2006.197.07:31:09.87#ibcon#read 4, iclass 35, count 0 2006.197.07:31:09.87#ibcon#about to read 5, iclass 35, count 0 2006.197.07:31:09.87#ibcon#read 5, iclass 35, count 0 2006.197.07:31:09.87#ibcon#about to read 6, iclass 35, count 0 2006.197.07:31:09.87#ibcon#read 6, iclass 35, count 0 2006.197.07:31:09.87#ibcon#end of sib2, iclass 35, count 0 2006.197.07:31:09.87#ibcon#*after write, iclass 35, count 0 2006.197.07:31:09.87#ibcon#*before return 0, iclass 35, count 0 2006.197.07:31:09.87#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.197.07:31:09.87#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.197.07:31:09.87#ibcon#about to clear, iclass 35 cls_cnt 0 2006.197.07:31:09.87#ibcon#cleared, iclass 35 cls_cnt 0 2006.197.07:31:09.87$vc4f8/valo=8,852.99 2006.197.07:31:09.87#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.197.07:31:09.87#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.197.07:31:09.87#ibcon#ireg 17 cls_cnt 0 2006.197.07:31:09.87#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.197.07:31:09.87#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.197.07:31:09.87#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.197.07:31:09.87#ibcon#enter wrdev, iclass 37, count 0 2006.197.07:31:09.87#ibcon#first serial, iclass 37, count 0 2006.197.07:31:09.87#ibcon#enter sib2, iclass 37, count 0 2006.197.07:31:09.87#ibcon#flushed, iclass 37, count 0 2006.197.07:31:09.87#ibcon#about to write, iclass 37, count 0 2006.197.07:31:09.87#ibcon#wrote, iclass 37, count 0 2006.197.07:31:09.87#ibcon#about to read 3, iclass 37, count 0 2006.197.07:31:09.89#ibcon#read 3, iclass 37, count 0 2006.197.07:31:09.89#ibcon#about to read 4, iclass 37, count 0 2006.197.07:31:09.89#ibcon#read 4, iclass 37, count 0 2006.197.07:31:09.89#ibcon#about to read 5, iclass 37, count 0 2006.197.07:31:09.89#ibcon#read 5, iclass 37, count 0 2006.197.07:31:09.89#ibcon#about to read 6, iclass 37, count 0 2006.197.07:31:09.89#ibcon#read 6, iclass 37, count 0 2006.197.07:31:09.89#ibcon#end of sib2, iclass 37, count 0 2006.197.07:31:09.89#ibcon#*mode == 0, iclass 37, count 0 2006.197.07:31:09.89#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.197.07:31:09.89#ibcon#[26=FRQ=08,852.99\r\n] 2006.197.07:31:09.89#ibcon#*before write, iclass 37, count 0 2006.197.07:31:09.89#ibcon#enter sib2, iclass 37, count 0 2006.197.07:31:09.89#ibcon#flushed, iclass 37, count 0 2006.197.07:31:09.89#ibcon#about to write, iclass 37, count 0 2006.197.07:31:09.89#ibcon#wrote, iclass 37, count 0 2006.197.07:31:09.89#ibcon#about to read 3, iclass 37, count 0 2006.197.07:31:09.93#ibcon#read 3, iclass 37, count 0 2006.197.07:31:09.93#ibcon#about to read 4, iclass 37, count 0 2006.197.07:31:09.93#ibcon#read 4, iclass 37, count 0 2006.197.07:31:09.93#ibcon#about to read 5, iclass 37, count 0 2006.197.07:31:09.93#ibcon#read 5, iclass 37, count 0 2006.197.07:31:09.93#ibcon#about to read 6, iclass 37, count 0 2006.197.07:31:09.93#ibcon#read 6, iclass 37, count 0 2006.197.07:31:09.93#ibcon#end of sib2, iclass 37, count 0 2006.197.07:31:09.93#ibcon#*after write, iclass 37, count 0 2006.197.07:31:09.93#ibcon#*before return 0, iclass 37, count 0 2006.197.07:31:09.93#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.197.07:31:09.93#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.197.07:31:09.93#ibcon#about to clear, iclass 37 cls_cnt 0 2006.197.07:31:09.93#ibcon#cleared, iclass 37 cls_cnt 0 2006.197.07:31:09.93$vc4f8/va=8,7 2006.197.07:31:09.93#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.197.07:31:09.93#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.197.07:31:09.93#ibcon#ireg 11 cls_cnt 2 2006.197.07:31:09.93#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.197.07:31:09.99#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.197.07:31:09.99#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.197.07:31:09.99#ibcon#enter wrdev, iclass 39, count 2 2006.197.07:31:09.99#ibcon#first serial, iclass 39, count 2 2006.197.07:31:09.99#ibcon#enter sib2, iclass 39, count 2 2006.197.07:31:09.99#ibcon#flushed, iclass 39, count 2 2006.197.07:31:09.99#ibcon#about to write, iclass 39, count 2 2006.197.07:31:09.99#ibcon#wrote, iclass 39, count 2 2006.197.07:31:09.99#ibcon#about to read 3, iclass 39, count 2 2006.197.07:31:10.01#ibcon#read 3, iclass 39, count 2 2006.197.07:31:10.01#ibcon#about to read 4, iclass 39, count 2 2006.197.07:31:10.01#ibcon#read 4, iclass 39, count 2 2006.197.07:31:10.01#ibcon#about to read 5, iclass 39, count 2 2006.197.07:31:10.01#ibcon#read 5, iclass 39, count 2 2006.197.07:31:10.01#ibcon#about to read 6, iclass 39, count 2 2006.197.07:31:10.01#ibcon#read 6, iclass 39, count 2 2006.197.07:31:10.01#ibcon#end of sib2, iclass 39, count 2 2006.197.07:31:10.01#ibcon#*mode == 0, iclass 39, count 2 2006.197.07:31:10.01#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.197.07:31:10.01#ibcon#[25=AT08-07\r\n] 2006.197.07:31:10.01#ibcon#*before write, iclass 39, count 2 2006.197.07:31:10.01#ibcon#enter sib2, iclass 39, count 2 2006.197.07:31:10.01#ibcon#flushed, iclass 39, count 2 2006.197.07:31:10.01#ibcon#about to write, iclass 39, count 2 2006.197.07:31:10.01#ibcon#wrote, iclass 39, count 2 2006.197.07:31:10.01#ibcon#about to read 3, iclass 39, count 2 2006.197.07:31:10.04#ibcon#read 3, iclass 39, count 2 2006.197.07:31:10.04#ibcon#about to read 4, iclass 39, count 2 2006.197.07:31:10.04#ibcon#read 4, iclass 39, count 2 2006.197.07:31:10.04#ibcon#about to read 5, iclass 39, count 2 2006.197.07:31:10.04#ibcon#read 5, iclass 39, count 2 2006.197.07:31:10.04#ibcon#about to read 6, iclass 39, count 2 2006.197.07:31:10.04#ibcon#read 6, iclass 39, count 2 2006.197.07:31:10.04#ibcon#end of sib2, iclass 39, count 2 2006.197.07:31:10.04#ibcon#*after write, iclass 39, count 2 2006.197.07:31:10.04#ibcon#*before return 0, iclass 39, count 2 2006.197.07:31:10.04#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.197.07:31:10.04#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.197.07:31:10.04#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.197.07:31:10.04#ibcon#ireg 7 cls_cnt 0 2006.197.07:31:10.04#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.197.07:31:10.16#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.197.07:31:10.16#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.197.07:31:10.16#ibcon#enter wrdev, iclass 39, count 0 2006.197.07:31:10.16#ibcon#first serial, iclass 39, count 0 2006.197.07:31:10.16#ibcon#enter sib2, iclass 39, count 0 2006.197.07:31:10.16#ibcon#flushed, iclass 39, count 0 2006.197.07:31:10.16#ibcon#about to write, iclass 39, count 0 2006.197.07:31:10.16#ibcon#wrote, iclass 39, count 0 2006.197.07:31:10.16#ibcon#about to read 3, iclass 39, count 0 2006.197.07:31:10.18#ibcon#read 3, iclass 39, count 0 2006.197.07:31:10.18#ibcon#about to read 4, iclass 39, count 0 2006.197.07:31:10.18#ibcon#read 4, iclass 39, count 0 2006.197.07:31:10.18#ibcon#about to read 5, iclass 39, count 0 2006.197.07:31:10.18#ibcon#read 5, iclass 39, count 0 2006.197.07:31:10.18#ibcon#about to read 6, iclass 39, count 0 2006.197.07:31:10.18#ibcon#read 6, iclass 39, count 0 2006.197.07:31:10.18#ibcon#end of sib2, iclass 39, count 0 2006.197.07:31:10.18#ibcon#*mode == 0, iclass 39, count 0 2006.197.07:31:10.18#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.197.07:31:10.18#ibcon#[25=USB\r\n] 2006.197.07:31:10.18#ibcon#*before write, iclass 39, count 0 2006.197.07:31:10.18#ibcon#enter sib2, iclass 39, count 0 2006.197.07:31:10.18#ibcon#flushed, iclass 39, count 0 2006.197.07:31:10.18#ibcon#about to write, iclass 39, count 0 2006.197.07:31:10.18#ibcon#wrote, iclass 39, count 0 2006.197.07:31:10.18#ibcon#about to read 3, iclass 39, count 0 2006.197.07:31:10.21#ibcon#read 3, iclass 39, count 0 2006.197.07:31:10.21#ibcon#about to read 4, iclass 39, count 0 2006.197.07:31:10.21#ibcon#read 4, iclass 39, count 0 2006.197.07:31:10.21#ibcon#about to read 5, iclass 39, count 0 2006.197.07:31:10.21#ibcon#read 5, iclass 39, count 0 2006.197.07:31:10.21#ibcon#about to read 6, iclass 39, count 0 2006.197.07:31:10.21#ibcon#read 6, iclass 39, count 0 2006.197.07:31:10.21#ibcon#end of sib2, iclass 39, count 0 2006.197.07:31:10.21#ibcon#*after write, iclass 39, count 0 2006.197.07:31:10.21#ibcon#*before return 0, iclass 39, count 0 2006.197.07:31:10.21#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.197.07:31:10.21#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.197.07:31:10.21#ibcon#about to clear, iclass 39 cls_cnt 0 2006.197.07:31:10.21#ibcon#cleared, iclass 39 cls_cnt 0 2006.197.07:31:10.21$vc4f8/vblo=1,632.99 2006.197.07:31:10.21#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.197.07:31:10.21#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.197.07:31:10.21#ibcon#ireg 17 cls_cnt 0 2006.197.07:31:10.21#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.197.07:31:10.21#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.197.07:31:10.21#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.197.07:31:10.21#ibcon#enter wrdev, iclass 3, count 0 2006.197.07:31:10.21#ibcon#first serial, iclass 3, count 0 2006.197.07:31:10.21#ibcon#enter sib2, iclass 3, count 0 2006.197.07:31:10.21#ibcon#flushed, iclass 3, count 0 2006.197.07:31:10.21#ibcon#about to write, iclass 3, count 0 2006.197.07:31:10.21#ibcon#wrote, iclass 3, count 0 2006.197.07:31:10.21#ibcon#about to read 3, iclass 3, count 0 2006.197.07:31:10.23#ibcon#read 3, iclass 3, count 0 2006.197.07:31:10.23#ibcon#about to read 4, iclass 3, count 0 2006.197.07:31:10.23#ibcon#read 4, iclass 3, count 0 2006.197.07:31:10.23#ibcon#about to read 5, iclass 3, count 0 2006.197.07:31:10.23#ibcon#read 5, iclass 3, count 0 2006.197.07:31:10.23#ibcon#about to read 6, iclass 3, count 0 2006.197.07:31:10.23#ibcon#read 6, iclass 3, count 0 2006.197.07:31:10.23#ibcon#end of sib2, iclass 3, count 0 2006.197.07:31:10.23#ibcon#*mode == 0, iclass 3, count 0 2006.197.07:31:10.23#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.197.07:31:10.23#ibcon#[28=FRQ=01,632.99\r\n] 2006.197.07:31:10.23#ibcon#*before write, iclass 3, count 0 2006.197.07:31:10.23#ibcon#enter sib2, iclass 3, count 0 2006.197.07:31:10.23#ibcon#flushed, iclass 3, count 0 2006.197.07:31:10.23#ibcon#about to write, iclass 3, count 0 2006.197.07:31:10.23#ibcon#wrote, iclass 3, count 0 2006.197.07:31:10.23#ibcon#about to read 3, iclass 3, count 0 2006.197.07:31:10.27#ibcon#read 3, iclass 3, count 0 2006.197.07:31:10.27#ibcon#about to read 4, iclass 3, count 0 2006.197.07:31:10.27#ibcon#read 4, iclass 3, count 0 2006.197.07:31:10.27#ibcon#about to read 5, iclass 3, count 0 2006.197.07:31:10.27#ibcon#read 5, iclass 3, count 0 2006.197.07:31:10.27#ibcon#about to read 6, iclass 3, count 0 2006.197.07:31:10.27#ibcon#read 6, iclass 3, count 0 2006.197.07:31:10.27#ibcon#end of sib2, iclass 3, count 0 2006.197.07:31:10.27#ibcon#*after write, iclass 3, count 0 2006.197.07:31:10.27#ibcon#*before return 0, iclass 3, count 0 2006.197.07:31:10.27#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.197.07:31:10.27#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.197.07:31:10.27#ibcon#about to clear, iclass 3 cls_cnt 0 2006.197.07:31:10.27#ibcon#cleared, iclass 3 cls_cnt 0 2006.197.07:31:10.27$vc4f8/vb=1,4 2006.197.07:31:10.27#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.197.07:31:10.27#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.197.07:31:10.27#ibcon#ireg 11 cls_cnt 2 2006.197.07:31:10.27#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.197.07:31:10.27#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.197.07:31:10.27#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.197.07:31:10.27#ibcon#enter wrdev, iclass 5, count 2 2006.197.07:31:10.27#ibcon#first serial, iclass 5, count 2 2006.197.07:31:10.27#ibcon#enter sib2, iclass 5, count 2 2006.197.07:31:10.27#ibcon#flushed, iclass 5, count 2 2006.197.07:31:10.27#ibcon#about to write, iclass 5, count 2 2006.197.07:31:10.27#ibcon#wrote, iclass 5, count 2 2006.197.07:31:10.27#ibcon#about to read 3, iclass 5, count 2 2006.197.07:31:10.29#ibcon#read 3, iclass 5, count 2 2006.197.07:31:10.29#ibcon#about to read 4, iclass 5, count 2 2006.197.07:31:10.29#ibcon#read 4, iclass 5, count 2 2006.197.07:31:10.29#ibcon#about to read 5, iclass 5, count 2 2006.197.07:31:10.29#ibcon#read 5, iclass 5, count 2 2006.197.07:31:10.29#ibcon#about to read 6, iclass 5, count 2 2006.197.07:31:10.29#ibcon#read 6, iclass 5, count 2 2006.197.07:31:10.29#ibcon#end of sib2, iclass 5, count 2 2006.197.07:31:10.29#ibcon#*mode == 0, iclass 5, count 2 2006.197.07:31:10.29#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.197.07:31:10.29#ibcon#[27=AT01-04\r\n] 2006.197.07:31:10.29#ibcon#*before write, iclass 5, count 2 2006.197.07:31:10.29#ibcon#enter sib2, iclass 5, count 2 2006.197.07:31:10.29#ibcon#flushed, iclass 5, count 2 2006.197.07:31:10.29#ibcon#about to write, iclass 5, count 2 2006.197.07:31:10.29#ibcon#wrote, iclass 5, count 2 2006.197.07:31:10.29#ibcon#about to read 3, iclass 5, count 2 2006.197.07:31:10.32#ibcon#read 3, iclass 5, count 2 2006.197.07:31:10.32#ibcon#about to read 4, iclass 5, count 2 2006.197.07:31:10.32#ibcon#read 4, iclass 5, count 2 2006.197.07:31:10.32#ibcon#about to read 5, iclass 5, count 2 2006.197.07:31:10.32#ibcon#read 5, iclass 5, count 2 2006.197.07:31:10.32#ibcon#about to read 6, iclass 5, count 2 2006.197.07:31:10.32#ibcon#read 6, iclass 5, count 2 2006.197.07:31:10.32#ibcon#end of sib2, iclass 5, count 2 2006.197.07:31:10.32#ibcon#*after write, iclass 5, count 2 2006.197.07:31:10.32#ibcon#*before return 0, iclass 5, count 2 2006.197.07:31:10.32#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.197.07:31:10.32#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.197.07:31:10.32#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.197.07:31:10.32#ibcon#ireg 7 cls_cnt 0 2006.197.07:31:10.32#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.197.07:31:10.44#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.197.07:31:10.44#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.197.07:31:10.44#ibcon#enter wrdev, iclass 5, count 0 2006.197.07:31:10.44#ibcon#first serial, iclass 5, count 0 2006.197.07:31:10.44#ibcon#enter sib2, iclass 5, count 0 2006.197.07:31:10.44#ibcon#flushed, iclass 5, count 0 2006.197.07:31:10.44#ibcon#about to write, iclass 5, count 0 2006.197.07:31:10.44#ibcon#wrote, iclass 5, count 0 2006.197.07:31:10.44#ibcon#about to read 3, iclass 5, count 0 2006.197.07:31:10.46#ibcon#read 3, iclass 5, count 0 2006.197.07:31:10.46#ibcon#about to read 4, iclass 5, count 0 2006.197.07:31:10.46#ibcon#read 4, iclass 5, count 0 2006.197.07:31:10.46#ibcon#about to read 5, iclass 5, count 0 2006.197.07:31:10.46#ibcon#read 5, iclass 5, count 0 2006.197.07:31:10.46#ibcon#about to read 6, iclass 5, count 0 2006.197.07:31:10.46#ibcon#read 6, iclass 5, count 0 2006.197.07:31:10.46#ibcon#end of sib2, iclass 5, count 0 2006.197.07:31:10.46#ibcon#*mode == 0, iclass 5, count 0 2006.197.07:31:10.46#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.197.07:31:10.46#ibcon#[27=USB\r\n] 2006.197.07:31:10.46#ibcon#*before write, iclass 5, count 0 2006.197.07:31:10.46#ibcon#enter sib2, iclass 5, count 0 2006.197.07:31:10.46#ibcon#flushed, iclass 5, count 0 2006.197.07:31:10.46#ibcon#about to write, iclass 5, count 0 2006.197.07:31:10.46#ibcon#wrote, iclass 5, count 0 2006.197.07:31:10.46#ibcon#about to read 3, iclass 5, count 0 2006.197.07:31:10.49#ibcon#read 3, iclass 5, count 0 2006.197.07:31:10.49#ibcon#about to read 4, iclass 5, count 0 2006.197.07:31:10.49#ibcon#read 4, iclass 5, count 0 2006.197.07:31:10.49#ibcon#about to read 5, iclass 5, count 0 2006.197.07:31:10.49#ibcon#read 5, iclass 5, count 0 2006.197.07:31:10.49#ibcon#about to read 6, iclass 5, count 0 2006.197.07:31:10.49#ibcon#read 6, iclass 5, count 0 2006.197.07:31:10.49#ibcon#end of sib2, iclass 5, count 0 2006.197.07:31:10.49#ibcon#*after write, iclass 5, count 0 2006.197.07:31:10.49#ibcon#*before return 0, iclass 5, count 0 2006.197.07:31:10.49#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.197.07:31:10.49#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.197.07:31:10.49#ibcon#about to clear, iclass 5 cls_cnt 0 2006.197.07:31:10.49#ibcon#cleared, iclass 5 cls_cnt 0 2006.197.07:31:10.49$vc4f8/vblo=2,640.99 2006.197.07:31:10.49#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.197.07:31:10.49#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.197.07:31:10.49#ibcon#ireg 17 cls_cnt 0 2006.197.07:31:10.49#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.197.07:31:10.49#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.197.07:31:10.49#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.197.07:31:10.49#ibcon#enter wrdev, iclass 7, count 0 2006.197.07:31:10.49#ibcon#first serial, iclass 7, count 0 2006.197.07:31:10.49#ibcon#enter sib2, iclass 7, count 0 2006.197.07:31:10.49#ibcon#flushed, iclass 7, count 0 2006.197.07:31:10.49#ibcon#about to write, iclass 7, count 0 2006.197.07:31:10.49#ibcon#wrote, iclass 7, count 0 2006.197.07:31:10.49#ibcon#about to read 3, iclass 7, count 0 2006.197.07:31:10.51#ibcon#read 3, iclass 7, count 0 2006.197.07:31:10.51#ibcon#about to read 4, iclass 7, count 0 2006.197.07:31:10.51#ibcon#read 4, iclass 7, count 0 2006.197.07:31:10.51#ibcon#about to read 5, iclass 7, count 0 2006.197.07:31:10.51#ibcon#read 5, iclass 7, count 0 2006.197.07:31:10.51#ibcon#about to read 6, iclass 7, count 0 2006.197.07:31:10.51#ibcon#read 6, iclass 7, count 0 2006.197.07:31:10.51#ibcon#end of sib2, iclass 7, count 0 2006.197.07:31:10.51#ibcon#*mode == 0, iclass 7, count 0 2006.197.07:31:10.51#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.197.07:31:10.51#ibcon#[28=FRQ=02,640.99\r\n] 2006.197.07:31:10.51#ibcon#*before write, iclass 7, count 0 2006.197.07:31:10.51#ibcon#enter sib2, iclass 7, count 0 2006.197.07:31:10.51#ibcon#flushed, iclass 7, count 0 2006.197.07:31:10.51#ibcon#about to write, iclass 7, count 0 2006.197.07:31:10.51#ibcon#wrote, iclass 7, count 0 2006.197.07:31:10.51#ibcon#about to read 3, iclass 7, count 0 2006.197.07:31:10.55#ibcon#read 3, iclass 7, count 0 2006.197.07:31:10.55#ibcon#about to read 4, iclass 7, count 0 2006.197.07:31:10.55#ibcon#read 4, iclass 7, count 0 2006.197.07:31:10.55#ibcon#about to read 5, iclass 7, count 0 2006.197.07:31:10.55#ibcon#read 5, iclass 7, count 0 2006.197.07:31:10.55#ibcon#about to read 6, iclass 7, count 0 2006.197.07:31:10.55#ibcon#read 6, iclass 7, count 0 2006.197.07:31:10.55#ibcon#end of sib2, iclass 7, count 0 2006.197.07:31:10.55#ibcon#*after write, iclass 7, count 0 2006.197.07:31:10.55#ibcon#*before return 0, iclass 7, count 0 2006.197.07:31:10.55#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.197.07:31:10.55#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.197.07:31:10.55#ibcon#about to clear, iclass 7 cls_cnt 0 2006.197.07:31:10.55#ibcon#cleared, iclass 7 cls_cnt 0 2006.197.07:31:10.55$vc4f8/vb=2,4 2006.197.07:31:10.55#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.197.07:31:10.55#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.197.07:31:10.55#ibcon#ireg 11 cls_cnt 2 2006.197.07:31:10.55#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.197.07:31:10.61#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.197.07:31:10.61#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.197.07:31:10.61#ibcon#enter wrdev, iclass 11, count 2 2006.197.07:31:10.61#ibcon#first serial, iclass 11, count 2 2006.197.07:31:10.61#ibcon#enter sib2, iclass 11, count 2 2006.197.07:31:10.61#ibcon#flushed, iclass 11, count 2 2006.197.07:31:10.61#ibcon#about to write, iclass 11, count 2 2006.197.07:31:10.61#ibcon#wrote, iclass 11, count 2 2006.197.07:31:10.61#ibcon#about to read 3, iclass 11, count 2 2006.197.07:31:10.63#ibcon#read 3, iclass 11, count 2 2006.197.07:31:10.63#ibcon#about to read 4, iclass 11, count 2 2006.197.07:31:10.63#ibcon#read 4, iclass 11, count 2 2006.197.07:31:10.63#ibcon#about to read 5, iclass 11, count 2 2006.197.07:31:10.63#ibcon#read 5, iclass 11, count 2 2006.197.07:31:10.63#ibcon#about to read 6, iclass 11, count 2 2006.197.07:31:10.63#ibcon#read 6, iclass 11, count 2 2006.197.07:31:10.63#ibcon#end of sib2, iclass 11, count 2 2006.197.07:31:10.63#ibcon#*mode == 0, iclass 11, count 2 2006.197.07:31:10.63#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.197.07:31:10.63#ibcon#[27=AT02-04\r\n] 2006.197.07:31:10.63#ibcon#*before write, iclass 11, count 2 2006.197.07:31:10.63#ibcon#enter sib2, iclass 11, count 2 2006.197.07:31:10.63#ibcon#flushed, iclass 11, count 2 2006.197.07:31:10.63#ibcon#about to write, iclass 11, count 2 2006.197.07:31:10.63#ibcon#wrote, iclass 11, count 2 2006.197.07:31:10.63#ibcon#about to read 3, iclass 11, count 2 2006.197.07:31:10.66#ibcon#read 3, iclass 11, count 2 2006.197.07:31:10.66#ibcon#about to read 4, iclass 11, count 2 2006.197.07:31:10.66#ibcon#read 4, iclass 11, count 2 2006.197.07:31:10.66#ibcon#about to read 5, iclass 11, count 2 2006.197.07:31:10.66#ibcon#read 5, iclass 11, count 2 2006.197.07:31:10.66#ibcon#about to read 6, iclass 11, count 2 2006.197.07:31:10.66#ibcon#read 6, iclass 11, count 2 2006.197.07:31:10.66#ibcon#end of sib2, iclass 11, count 2 2006.197.07:31:10.66#ibcon#*after write, iclass 11, count 2 2006.197.07:31:10.66#ibcon#*before return 0, iclass 11, count 2 2006.197.07:31:10.66#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.197.07:31:10.66#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.197.07:31:10.66#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.197.07:31:10.66#ibcon#ireg 7 cls_cnt 0 2006.197.07:31:10.66#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.197.07:31:10.78#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.197.07:31:10.78#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.197.07:31:10.78#ibcon#enter wrdev, iclass 11, count 0 2006.197.07:31:10.78#ibcon#first serial, iclass 11, count 0 2006.197.07:31:10.78#ibcon#enter sib2, iclass 11, count 0 2006.197.07:31:10.78#ibcon#flushed, iclass 11, count 0 2006.197.07:31:10.78#ibcon#about to write, iclass 11, count 0 2006.197.07:31:10.78#ibcon#wrote, iclass 11, count 0 2006.197.07:31:10.78#ibcon#about to read 3, iclass 11, count 0 2006.197.07:31:10.80#ibcon#read 3, iclass 11, count 0 2006.197.07:31:10.80#ibcon#about to read 4, iclass 11, count 0 2006.197.07:31:10.80#ibcon#read 4, iclass 11, count 0 2006.197.07:31:10.80#ibcon#about to read 5, iclass 11, count 0 2006.197.07:31:10.80#ibcon#read 5, iclass 11, count 0 2006.197.07:31:10.80#ibcon#about to read 6, iclass 11, count 0 2006.197.07:31:10.80#ibcon#read 6, iclass 11, count 0 2006.197.07:31:10.80#ibcon#end of sib2, iclass 11, count 0 2006.197.07:31:10.80#ibcon#*mode == 0, iclass 11, count 0 2006.197.07:31:10.80#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.197.07:31:10.80#ibcon#[27=USB\r\n] 2006.197.07:31:10.80#ibcon#*before write, iclass 11, count 0 2006.197.07:31:10.80#ibcon#enter sib2, iclass 11, count 0 2006.197.07:31:10.80#ibcon#flushed, iclass 11, count 0 2006.197.07:31:10.80#ibcon#about to write, iclass 11, count 0 2006.197.07:31:10.80#ibcon#wrote, iclass 11, count 0 2006.197.07:31:10.80#ibcon#about to read 3, iclass 11, count 0 2006.197.07:31:10.83#ibcon#read 3, iclass 11, count 0 2006.197.07:31:10.83#ibcon#about to read 4, iclass 11, count 0 2006.197.07:31:10.83#ibcon#read 4, iclass 11, count 0 2006.197.07:31:10.83#ibcon#about to read 5, iclass 11, count 0 2006.197.07:31:10.83#ibcon#read 5, iclass 11, count 0 2006.197.07:31:10.83#ibcon#about to read 6, iclass 11, count 0 2006.197.07:31:10.83#ibcon#read 6, iclass 11, count 0 2006.197.07:31:10.83#ibcon#end of sib2, iclass 11, count 0 2006.197.07:31:10.83#ibcon#*after write, iclass 11, count 0 2006.197.07:31:10.83#ibcon#*before return 0, iclass 11, count 0 2006.197.07:31:10.83#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.197.07:31:10.83#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.197.07:31:10.83#ibcon#about to clear, iclass 11 cls_cnt 0 2006.197.07:31:10.83#ibcon#cleared, iclass 11 cls_cnt 0 2006.197.07:31:10.83$vc4f8/vblo=3,656.99 2006.197.07:31:10.83#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.197.07:31:10.83#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.197.07:31:10.83#ibcon#ireg 17 cls_cnt 0 2006.197.07:31:10.83#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.197.07:31:10.83#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.197.07:31:10.83#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.197.07:31:10.83#ibcon#enter wrdev, iclass 13, count 0 2006.197.07:31:10.83#ibcon#first serial, iclass 13, count 0 2006.197.07:31:10.83#ibcon#enter sib2, iclass 13, count 0 2006.197.07:31:10.83#ibcon#flushed, iclass 13, count 0 2006.197.07:31:10.83#ibcon#about to write, iclass 13, count 0 2006.197.07:31:10.83#ibcon#wrote, iclass 13, count 0 2006.197.07:31:10.83#ibcon#about to read 3, iclass 13, count 0 2006.197.07:31:10.85#ibcon#read 3, iclass 13, count 0 2006.197.07:31:10.85#ibcon#about to read 4, iclass 13, count 0 2006.197.07:31:10.85#ibcon#read 4, iclass 13, count 0 2006.197.07:31:10.85#ibcon#about to read 5, iclass 13, count 0 2006.197.07:31:10.85#ibcon#read 5, iclass 13, count 0 2006.197.07:31:10.85#ibcon#about to read 6, iclass 13, count 0 2006.197.07:31:10.85#ibcon#read 6, iclass 13, count 0 2006.197.07:31:10.85#ibcon#end of sib2, iclass 13, count 0 2006.197.07:31:10.85#ibcon#*mode == 0, iclass 13, count 0 2006.197.07:31:10.85#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.197.07:31:10.85#ibcon#[28=FRQ=03,656.99\r\n] 2006.197.07:31:10.85#ibcon#*before write, iclass 13, count 0 2006.197.07:31:10.85#ibcon#enter sib2, iclass 13, count 0 2006.197.07:31:10.85#ibcon#flushed, iclass 13, count 0 2006.197.07:31:10.85#ibcon#about to write, iclass 13, count 0 2006.197.07:31:10.85#ibcon#wrote, iclass 13, count 0 2006.197.07:31:10.85#ibcon#about to read 3, iclass 13, count 0 2006.197.07:31:10.89#ibcon#read 3, iclass 13, count 0 2006.197.07:31:10.89#ibcon#about to read 4, iclass 13, count 0 2006.197.07:31:10.89#ibcon#read 4, iclass 13, count 0 2006.197.07:31:10.89#ibcon#about to read 5, iclass 13, count 0 2006.197.07:31:10.89#ibcon#read 5, iclass 13, count 0 2006.197.07:31:10.89#ibcon#about to read 6, iclass 13, count 0 2006.197.07:31:10.89#ibcon#read 6, iclass 13, count 0 2006.197.07:31:10.89#ibcon#end of sib2, iclass 13, count 0 2006.197.07:31:10.89#ibcon#*after write, iclass 13, count 0 2006.197.07:31:10.89#ibcon#*before return 0, iclass 13, count 0 2006.197.07:31:10.89#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.197.07:31:10.89#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.197.07:31:10.89#ibcon#about to clear, iclass 13 cls_cnt 0 2006.197.07:31:10.89#ibcon#cleared, iclass 13 cls_cnt 0 2006.197.07:31:10.89$vc4f8/vb=3,4 2006.197.07:31:10.89#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.197.07:31:10.89#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.197.07:31:10.89#ibcon#ireg 11 cls_cnt 2 2006.197.07:31:10.89#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.197.07:31:10.95#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.197.07:31:10.95#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.197.07:31:10.95#ibcon#enter wrdev, iclass 15, count 2 2006.197.07:31:10.95#ibcon#first serial, iclass 15, count 2 2006.197.07:31:10.95#ibcon#enter sib2, iclass 15, count 2 2006.197.07:31:10.95#ibcon#flushed, iclass 15, count 2 2006.197.07:31:10.95#ibcon#about to write, iclass 15, count 2 2006.197.07:31:10.95#ibcon#wrote, iclass 15, count 2 2006.197.07:31:10.95#ibcon#about to read 3, iclass 15, count 2 2006.197.07:31:10.97#ibcon#read 3, iclass 15, count 2 2006.197.07:31:10.97#ibcon#about to read 4, iclass 15, count 2 2006.197.07:31:10.97#ibcon#read 4, iclass 15, count 2 2006.197.07:31:10.97#ibcon#about to read 5, iclass 15, count 2 2006.197.07:31:10.97#ibcon#read 5, iclass 15, count 2 2006.197.07:31:10.97#ibcon#about to read 6, iclass 15, count 2 2006.197.07:31:10.97#ibcon#read 6, iclass 15, count 2 2006.197.07:31:10.97#ibcon#end of sib2, iclass 15, count 2 2006.197.07:31:10.97#ibcon#*mode == 0, iclass 15, count 2 2006.197.07:31:10.97#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.197.07:31:10.97#ibcon#[27=AT03-04\r\n] 2006.197.07:31:10.97#ibcon#*before write, iclass 15, count 2 2006.197.07:31:10.97#ibcon#enter sib2, iclass 15, count 2 2006.197.07:31:10.97#ibcon#flushed, iclass 15, count 2 2006.197.07:31:10.97#ibcon#about to write, iclass 15, count 2 2006.197.07:31:10.97#ibcon#wrote, iclass 15, count 2 2006.197.07:31:10.97#ibcon#about to read 3, iclass 15, count 2 2006.197.07:31:11.00#ibcon#read 3, iclass 15, count 2 2006.197.07:31:11.00#ibcon#about to read 4, iclass 15, count 2 2006.197.07:31:11.00#ibcon#read 4, iclass 15, count 2 2006.197.07:31:11.00#ibcon#about to read 5, iclass 15, count 2 2006.197.07:31:11.00#ibcon#read 5, iclass 15, count 2 2006.197.07:31:11.00#ibcon#about to read 6, iclass 15, count 2 2006.197.07:31:11.00#ibcon#read 6, iclass 15, count 2 2006.197.07:31:11.00#ibcon#end of sib2, iclass 15, count 2 2006.197.07:31:11.00#ibcon#*after write, iclass 15, count 2 2006.197.07:31:11.00#ibcon#*before return 0, iclass 15, count 2 2006.197.07:31:11.00#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.197.07:31:11.00#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.197.07:31:11.00#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.197.07:31:11.00#ibcon#ireg 7 cls_cnt 0 2006.197.07:31:11.00#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.197.07:31:11.12#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.197.07:31:11.12#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.197.07:31:11.12#ibcon#enter wrdev, iclass 15, count 0 2006.197.07:31:11.12#ibcon#first serial, iclass 15, count 0 2006.197.07:31:11.12#ibcon#enter sib2, iclass 15, count 0 2006.197.07:31:11.12#ibcon#flushed, iclass 15, count 0 2006.197.07:31:11.12#ibcon#about to write, iclass 15, count 0 2006.197.07:31:11.12#ibcon#wrote, iclass 15, count 0 2006.197.07:31:11.12#ibcon#about to read 3, iclass 15, count 0 2006.197.07:31:11.14#ibcon#read 3, iclass 15, count 0 2006.197.07:31:11.14#ibcon#about to read 4, iclass 15, count 0 2006.197.07:31:11.14#ibcon#read 4, iclass 15, count 0 2006.197.07:31:11.14#ibcon#about to read 5, iclass 15, count 0 2006.197.07:31:11.14#ibcon#read 5, iclass 15, count 0 2006.197.07:31:11.14#ibcon#about to read 6, iclass 15, count 0 2006.197.07:31:11.14#ibcon#read 6, iclass 15, count 0 2006.197.07:31:11.14#ibcon#end of sib2, iclass 15, count 0 2006.197.07:31:11.14#ibcon#*mode == 0, iclass 15, count 0 2006.197.07:31:11.14#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.197.07:31:11.14#ibcon#[27=USB\r\n] 2006.197.07:31:11.14#ibcon#*before write, iclass 15, count 0 2006.197.07:31:11.14#ibcon#enter sib2, iclass 15, count 0 2006.197.07:31:11.14#ibcon#flushed, iclass 15, count 0 2006.197.07:31:11.14#ibcon#about to write, iclass 15, count 0 2006.197.07:31:11.14#ibcon#wrote, iclass 15, count 0 2006.197.07:31:11.14#ibcon#about to read 3, iclass 15, count 0 2006.197.07:31:11.17#ibcon#read 3, iclass 15, count 0 2006.197.07:31:11.17#ibcon#about to read 4, iclass 15, count 0 2006.197.07:31:11.17#ibcon#read 4, iclass 15, count 0 2006.197.07:31:11.17#ibcon#about to read 5, iclass 15, count 0 2006.197.07:31:11.17#ibcon#read 5, iclass 15, count 0 2006.197.07:31:11.17#ibcon#about to read 6, iclass 15, count 0 2006.197.07:31:11.17#ibcon#read 6, iclass 15, count 0 2006.197.07:31:11.17#ibcon#end of sib2, iclass 15, count 0 2006.197.07:31:11.17#ibcon#*after write, iclass 15, count 0 2006.197.07:31:11.17#ibcon#*before return 0, iclass 15, count 0 2006.197.07:31:11.17#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.197.07:31:11.17#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.197.07:31:11.17#ibcon#about to clear, iclass 15 cls_cnt 0 2006.197.07:31:11.17#ibcon#cleared, iclass 15 cls_cnt 0 2006.197.07:31:11.17$vc4f8/vblo=4,712.99 2006.197.07:31:11.17#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.197.07:31:11.17#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.197.07:31:11.17#ibcon#ireg 17 cls_cnt 0 2006.197.07:31:11.17#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.197.07:31:11.17#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.197.07:31:11.17#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.197.07:31:11.17#ibcon#enter wrdev, iclass 17, count 0 2006.197.07:31:11.17#ibcon#first serial, iclass 17, count 0 2006.197.07:31:11.17#ibcon#enter sib2, iclass 17, count 0 2006.197.07:31:11.17#ibcon#flushed, iclass 17, count 0 2006.197.07:31:11.17#ibcon#about to write, iclass 17, count 0 2006.197.07:31:11.17#ibcon#wrote, iclass 17, count 0 2006.197.07:31:11.17#ibcon#about to read 3, iclass 17, count 0 2006.197.07:31:11.19#ibcon#read 3, iclass 17, count 0 2006.197.07:31:11.19#ibcon#about to read 4, iclass 17, count 0 2006.197.07:31:11.19#ibcon#read 4, iclass 17, count 0 2006.197.07:31:11.19#ibcon#about to read 5, iclass 17, count 0 2006.197.07:31:11.19#ibcon#read 5, iclass 17, count 0 2006.197.07:31:11.19#ibcon#about to read 6, iclass 17, count 0 2006.197.07:31:11.19#ibcon#read 6, iclass 17, count 0 2006.197.07:31:11.19#ibcon#end of sib2, iclass 17, count 0 2006.197.07:31:11.19#ibcon#*mode == 0, iclass 17, count 0 2006.197.07:31:11.19#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.197.07:31:11.19#ibcon#[28=FRQ=04,712.99\r\n] 2006.197.07:31:11.19#ibcon#*before write, iclass 17, count 0 2006.197.07:31:11.19#ibcon#enter sib2, iclass 17, count 0 2006.197.07:31:11.19#ibcon#flushed, iclass 17, count 0 2006.197.07:31:11.19#ibcon#about to write, iclass 17, count 0 2006.197.07:31:11.19#ibcon#wrote, iclass 17, count 0 2006.197.07:31:11.19#ibcon#about to read 3, iclass 17, count 0 2006.197.07:31:11.23#ibcon#read 3, iclass 17, count 0 2006.197.07:31:11.23#ibcon#about to read 4, iclass 17, count 0 2006.197.07:31:11.23#ibcon#read 4, iclass 17, count 0 2006.197.07:31:11.23#ibcon#about to read 5, iclass 17, count 0 2006.197.07:31:11.23#ibcon#read 5, iclass 17, count 0 2006.197.07:31:11.23#ibcon#about to read 6, iclass 17, count 0 2006.197.07:31:11.23#ibcon#read 6, iclass 17, count 0 2006.197.07:31:11.23#ibcon#end of sib2, iclass 17, count 0 2006.197.07:31:11.23#ibcon#*after write, iclass 17, count 0 2006.197.07:31:11.23#ibcon#*before return 0, iclass 17, count 0 2006.197.07:31:11.23#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.197.07:31:11.23#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.197.07:31:11.23#ibcon#about to clear, iclass 17 cls_cnt 0 2006.197.07:31:11.23#ibcon#cleared, iclass 17 cls_cnt 0 2006.197.07:31:11.23$vc4f8/vb=4,4 2006.197.07:31:11.23#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.197.07:31:11.23#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.197.07:31:11.23#ibcon#ireg 11 cls_cnt 2 2006.197.07:31:11.23#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.197.07:31:11.29#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.197.07:31:11.29#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.197.07:31:11.29#ibcon#enter wrdev, iclass 19, count 2 2006.197.07:31:11.29#ibcon#first serial, iclass 19, count 2 2006.197.07:31:11.29#ibcon#enter sib2, iclass 19, count 2 2006.197.07:31:11.29#ibcon#flushed, iclass 19, count 2 2006.197.07:31:11.29#ibcon#about to write, iclass 19, count 2 2006.197.07:31:11.29#ibcon#wrote, iclass 19, count 2 2006.197.07:31:11.29#ibcon#about to read 3, iclass 19, count 2 2006.197.07:31:11.31#ibcon#read 3, iclass 19, count 2 2006.197.07:31:11.31#ibcon#about to read 4, iclass 19, count 2 2006.197.07:31:11.31#ibcon#read 4, iclass 19, count 2 2006.197.07:31:11.31#ibcon#about to read 5, iclass 19, count 2 2006.197.07:31:11.31#ibcon#read 5, iclass 19, count 2 2006.197.07:31:11.31#ibcon#about to read 6, iclass 19, count 2 2006.197.07:31:11.31#ibcon#read 6, iclass 19, count 2 2006.197.07:31:11.31#ibcon#end of sib2, iclass 19, count 2 2006.197.07:31:11.31#ibcon#*mode == 0, iclass 19, count 2 2006.197.07:31:11.31#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.197.07:31:11.31#ibcon#[27=AT04-04\r\n] 2006.197.07:31:11.31#ibcon#*before write, iclass 19, count 2 2006.197.07:31:11.31#ibcon#enter sib2, iclass 19, count 2 2006.197.07:31:11.31#ibcon#flushed, iclass 19, count 2 2006.197.07:31:11.31#ibcon#about to write, iclass 19, count 2 2006.197.07:31:11.31#ibcon#wrote, iclass 19, count 2 2006.197.07:31:11.31#ibcon#about to read 3, iclass 19, count 2 2006.197.07:31:11.34#ibcon#read 3, iclass 19, count 2 2006.197.07:31:11.34#ibcon#about to read 4, iclass 19, count 2 2006.197.07:31:11.34#ibcon#read 4, iclass 19, count 2 2006.197.07:31:11.34#ibcon#about to read 5, iclass 19, count 2 2006.197.07:31:11.34#ibcon#read 5, iclass 19, count 2 2006.197.07:31:11.34#ibcon#about to read 6, iclass 19, count 2 2006.197.07:31:11.34#ibcon#read 6, iclass 19, count 2 2006.197.07:31:11.34#ibcon#end of sib2, iclass 19, count 2 2006.197.07:31:11.34#ibcon#*after write, iclass 19, count 2 2006.197.07:31:11.34#ibcon#*before return 0, iclass 19, count 2 2006.197.07:31:11.34#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.197.07:31:11.34#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.197.07:31:11.34#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.197.07:31:11.34#ibcon#ireg 7 cls_cnt 0 2006.197.07:31:11.34#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.197.07:31:11.46#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.197.07:31:11.46#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.197.07:31:11.46#ibcon#enter wrdev, iclass 19, count 0 2006.197.07:31:11.46#ibcon#first serial, iclass 19, count 0 2006.197.07:31:11.46#ibcon#enter sib2, iclass 19, count 0 2006.197.07:31:11.46#ibcon#flushed, iclass 19, count 0 2006.197.07:31:11.46#ibcon#about to write, iclass 19, count 0 2006.197.07:31:11.46#ibcon#wrote, iclass 19, count 0 2006.197.07:31:11.46#ibcon#about to read 3, iclass 19, count 0 2006.197.07:31:11.48#ibcon#read 3, iclass 19, count 0 2006.197.07:31:11.48#ibcon#about to read 4, iclass 19, count 0 2006.197.07:31:11.48#ibcon#read 4, iclass 19, count 0 2006.197.07:31:11.48#ibcon#about to read 5, iclass 19, count 0 2006.197.07:31:11.48#ibcon#read 5, iclass 19, count 0 2006.197.07:31:11.48#ibcon#about to read 6, iclass 19, count 0 2006.197.07:31:11.48#ibcon#read 6, iclass 19, count 0 2006.197.07:31:11.48#ibcon#end of sib2, iclass 19, count 0 2006.197.07:31:11.48#ibcon#*mode == 0, iclass 19, count 0 2006.197.07:31:11.48#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.197.07:31:11.48#ibcon#[27=USB\r\n] 2006.197.07:31:11.48#ibcon#*before write, iclass 19, count 0 2006.197.07:31:11.48#ibcon#enter sib2, iclass 19, count 0 2006.197.07:31:11.48#ibcon#flushed, iclass 19, count 0 2006.197.07:31:11.48#ibcon#about to write, iclass 19, count 0 2006.197.07:31:11.48#ibcon#wrote, iclass 19, count 0 2006.197.07:31:11.48#ibcon#about to read 3, iclass 19, count 0 2006.197.07:31:11.51#ibcon#read 3, iclass 19, count 0 2006.197.07:31:11.51#ibcon#about to read 4, iclass 19, count 0 2006.197.07:31:11.51#ibcon#read 4, iclass 19, count 0 2006.197.07:31:11.51#ibcon#about to read 5, iclass 19, count 0 2006.197.07:31:11.51#ibcon#read 5, iclass 19, count 0 2006.197.07:31:11.51#ibcon#about to read 6, iclass 19, count 0 2006.197.07:31:11.51#ibcon#read 6, iclass 19, count 0 2006.197.07:31:11.51#ibcon#end of sib2, iclass 19, count 0 2006.197.07:31:11.51#ibcon#*after write, iclass 19, count 0 2006.197.07:31:11.51#ibcon#*before return 0, iclass 19, count 0 2006.197.07:31:11.51#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.197.07:31:11.51#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.197.07:31:11.51#ibcon#about to clear, iclass 19 cls_cnt 0 2006.197.07:31:11.51#ibcon#cleared, iclass 19 cls_cnt 0 2006.197.07:31:11.51$vc4f8/vblo=5,744.99 2006.197.07:31:11.51#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.197.07:31:11.51#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.197.07:31:11.51#ibcon#ireg 17 cls_cnt 0 2006.197.07:31:11.51#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.197.07:31:11.51#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.197.07:31:11.51#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.197.07:31:11.51#ibcon#enter wrdev, iclass 21, count 0 2006.197.07:31:11.51#ibcon#first serial, iclass 21, count 0 2006.197.07:31:11.51#ibcon#enter sib2, iclass 21, count 0 2006.197.07:31:11.51#ibcon#flushed, iclass 21, count 0 2006.197.07:31:11.51#ibcon#about to write, iclass 21, count 0 2006.197.07:31:11.51#ibcon#wrote, iclass 21, count 0 2006.197.07:31:11.51#ibcon#about to read 3, iclass 21, count 0 2006.197.07:31:11.53#ibcon#read 3, iclass 21, count 0 2006.197.07:31:11.53#ibcon#about to read 4, iclass 21, count 0 2006.197.07:31:11.53#ibcon#read 4, iclass 21, count 0 2006.197.07:31:11.53#ibcon#about to read 5, iclass 21, count 0 2006.197.07:31:11.53#ibcon#read 5, iclass 21, count 0 2006.197.07:31:11.53#ibcon#about to read 6, iclass 21, count 0 2006.197.07:31:11.53#ibcon#read 6, iclass 21, count 0 2006.197.07:31:11.53#ibcon#end of sib2, iclass 21, count 0 2006.197.07:31:11.53#ibcon#*mode == 0, iclass 21, count 0 2006.197.07:31:11.53#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.197.07:31:11.53#ibcon#[28=FRQ=05,744.99\r\n] 2006.197.07:31:11.53#ibcon#*before write, iclass 21, count 0 2006.197.07:31:11.53#ibcon#enter sib2, iclass 21, count 0 2006.197.07:31:11.53#ibcon#flushed, iclass 21, count 0 2006.197.07:31:11.53#ibcon#about to write, iclass 21, count 0 2006.197.07:31:11.53#ibcon#wrote, iclass 21, count 0 2006.197.07:31:11.53#ibcon#about to read 3, iclass 21, count 0 2006.197.07:31:11.57#ibcon#read 3, iclass 21, count 0 2006.197.07:31:11.57#ibcon#about to read 4, iclass 21, count 0 2006.197.07:31:11.57#ibcon#read 4, iclass 21, count 0 2006.197.07:31:11.57#ibcon#about to read 5, iclass 21, count 0 2006.197.07:31:11.57#ibcon#read 5, iclass 21, count 0 2006.197.07:31:11.57#ibcon#about to read 6, iclass 21, count 0 2006.197.07:31:11.57#ibcon#read 6, iclass 21, count 0 2006.197.07:31:11.57#ibcon#end of sib2, iclass 21, count 0 2006.197.07:31:11.57#ibcon#*after write, iclass 21, count 0 2006.197.07:31:11.57#ibcon#*before return 0, iclass 21, count 0 2006.197.07:31:11.57#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.197.07:31:11.57#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.197.07:31:11.57#ibcon#about to clear, iclass 21 cls_cnt 0 2006.197.07:31:11.57#ibcon#cleared, iclass 21 cls_cnt 0 2006.197.07:31:11.57$vc4f8/vb=5,4 2006.197.07:31:11.57#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.197.07:31:11.57#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.197.07:31:11.57#ibcon#ireg 11 cls_cnt 2 2006.197.07:31:11.57#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.197.07:31:11.63#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.197.07:31:11.63#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.197.07:31:11.63#ibcon#enter wrdev, iclass 23, count 2 2006.197.07:31:11.63#ibcon#first serial, iclass 23, count 2 2006.197.07:31:11.63#ibcon#enter sib2, iclass 23, count 2 2006.197.07:31:11.63#ibcon#flushed, iclass 23, count 2 2006.197.07:31:11.63#ibcon#about to write, iclass 23, count 2 2006.197.07:31:11.63#ibcon#wrote, iclass 23, count 2 2006.197.07:31:11.63#ibcon#about to read 3, iclass 23, count 2 2006.197.07:31:11.65#ibcon#read 3, iclass 23, count 2 2006.197.07:31:11.65#ibcon#about to read 4, iclass 23, count 2 2006.197.07:31:11.65#ibcon#read 4, iclass 23, count 2 2006.197.07:31:11.65#ibcon#about to read 5, iclass 23, count 2 2006.197.07:31:11.65#ibcon#read 5, iclass 23, count 2 2006.197.07:31:11.65#ibcon#about to read 6, iclass 23, count 2 2006.197.07:31:11.65#ibcon#read 6, iclass 23, count 2 2006.197.07:31:11.65#ibcon#end of sib2, iclass 23, count 2 2006.197.07:31:11.65#ibcon#*mode == 0, iclass 23, count 2 2006.197.07:31:11.65#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.197.07:31:11.65#ibcon#[27=AT05-04\r\n] 2006.197.07:31:11.65#ibcon#*before write, iclass 23, count 2 2006.197.07:31:11.65#ibcon#enter sib2, iclass 23, count 2 2006.197.07:31:11.65#ibcon#flushed, iclass 23, count 2 2006.197.07:31:11.65#ibcon#about to write, iclass 23, count 2 2006.197.07:31:11.65#ibcon#wrote, iclass 23, count 2 2006.197.07:31:11.65#ibcon#about to read 3, iclass 23, count 2 2006.197.07:31:11.68#ibcon#read 3, iclass 23, count 2 2006.197.07:31:11.68#ibcon#about to read 4, iclass 23, count 2 2006.197.07:31:11.68#ibcon#read 4, iclass 23, count 2 2006.197.07:31:11.68#ibcon#about to read 5, iclass 23, count 2 2006.197.07:31:11.68#ibcon#read 5, iclass 23, count 2 2006.197.07:31:11.68#ibcon#about to read 6, iclass 23, count 2 2006.197.07:31:11.68#ibcon#read 6, iclass 23, count 2 2006.197.07:31:11.68#ibcon#end of sib2, iclass 23, count 2 2006.197.07:31:11.68#ibcon#*after write, iclass 23, count 2 2006.197.07:31:11.68#ibcon#*before return 0, iclass 23, count 2 2006.197.07:31:11.68#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.197.07:31:11.68#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.197.07:31:11.68#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.197.07:31:11.68#ibcon#ireg 7 cls_cnt 0 2006.197.07:31:11.68#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.197.07:31:11.80#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.197.07:31:11.80#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.197.07:31:11.80#ibcon#enter wrdev, iclass 23, count 0 2006.197.07:31:11.80#ibcon#first serial, iclass 23, count 0 2006.197.07:31:11.80#ibcon#enter sib2, iclass 23, count 0 2006.197.07:31:11.80#ibcon#flushed, iclass 23, count 0 2006.197.07:31:11.80#ibcon#about to write, iclass 23, count 0 2006.197.07:31:11.80#ibcon#wrote, iclass 23, count 0 2006.197.07:31:11.80#ibcon#about to read 3, iclass 23, count 0 2006.197.07:31:11.82#ibcon#read 3, iclass 23, count 0 2006.197.07:31:11.82#ibcon#about to read 4, iclass 23, count 0 2006.197.07:31:11.82#ibcon#read 4, iclass 23, count 0 2006.197.07:31:11.82#ibcon#about to read 5, iclass 23, count 0 2006.197.07:31:11.82#ibcon#read 5, iclass 23, count 0 2006.197.07:31:11.82#ibcon#about to read 6, iclass 23, count 0 2006.197.07:31:11.82#ibcon#read 6, iclass 23, count 0 2006.197.07:31:11.82#ibcon#end of sib2, iclass 23, count 0 2006.197.07:31:11.82#ibcon#*mode == 0, iclass 23, count 0 2006.197.07:31:11.82#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.197.07:31:11.82#ibcon#[27=USB\r\n] 2006.197.07:31:11.82#ibcon#*before write, iclass 23, count 0 2006.197.07:31:11.82#ibcon#enter sib2, iclass 23, count 0 2006.197.07:31:11.82#ibcon#flushed, iclass 23, count 0 2006.197.07:31:11.82#ibcon#about to write, iclass 23, count 0 2006.197.07:31:11.82#ibcon#wrote, iclass 23, count 0 2006.197.07:31:11.82#ibcon#about to read 3, iclass 23, count 0 2006.197.07:31:11.85#ibcon#read 3, iclass 23, count 0 2006.197.07:31:11.85#ibcon#about to read 4, iclass 23, count 0 2006.197.07:31:11.85#ibcon#read 4, iclass 23, count 0 2006.197.07:31:11.85#ibcon#about to read 5, iclass 23, count 0 2006.197.07:31:11.85#ibcon#read 5, iclass 23, count 0 2006.197.07:31:11.85#ibcon#about to read 6, iclass 23, count 0 2006.197.07:31:11.85#ibcon#read 6, iclass 23, count 0 2006.197.07:31:11.85#ibcon#end of sib2, iclass 23, count 0 2006.197.07:31:11.85#ibcon#*after write, iclass 23, count 0 2006.197.07:31:11.85#ibcon#*before return 0, iclass 23, count 0 2006.197.07:31:11.85#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.197.07:31:11.85#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.197.07:31:11.85#ibcon#about to clear, iclass 23 cls_cnt 0 2006.197.07:31:11.85#ibcon#cleared, iclass 23 cls_cnt 0 2006.197.07:31:11.85$vc4f8/vblo=6,752.99 2006.197.07:31:11.85#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.197.07:31:11.85#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.197.07:31:11.85#ibcon#ireg 17 cls_cnt 0 2006.197.07:31:11.85#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.197.07:31:11.85#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.197.07:31:11.85#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.197.07:31:11.85#ibcon#enter wrdev, iclass 25, count 0 2006.197.07:31:11.85#ibcon#first serial, iclass 25, count 0 2006.197.07:31:11.85#ibcon#enter sib2, iclass 25, count 0 2006.197.07:31:11.85#ibcon#flushed, iclass 25, count 0 2006.197.07:31:11.85#ibcon#about to write, iclass 25, count 0 2006.197.07:31:11.85#ibcon#wrote, iclass 25, count 0 2006.197.07:31:11.85#ibcon#about to read 3, iclass 25, count 0 2006.197.07:31:11.87#ibcon#read 3, iclass 25, count 0 2006.197.07:31:11.87#ibcon#about to read 4, iclass 25, count 0 2006.197.07:31:11.87#ibcon#read 4, iclass 25, count 0 2006.197.07:31:11.87#ibcon#about to read 5, iclass 25, count 0 2006.197.07:31:11.87#ibcon#read 5, iclass 25, count 0 2006.197.07:31:11.87#ibcon#about to read 6, iclass 25, count 0 2006.197.07:31:11.87#ibcon#read 6, iclass 25, count 0 2006.197.07:31:11.87#ibcon#end of sib2, iclass 25, count 0 2006.197.07:31:11.87#ibcon#*mode == 0, iclass 25, count 0 2006.197.07:31:11.87#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.197.07:31:11.87#ibcon#[28=FRQ=06,752.99\r\n] 2006.197.07:31:11.87#ibcon#*before write, iclass 25, count 0 2006.197.07:31:11.87#ibcon#enter sib2, iclass 25, count 0 2006.197.07:31:11.87#ibcon#flushed, iclass 25, count 0 2006.197.07:31:11.87#ibcon#about to write, iclass 25, count 0 2006.197.07:31:11.87#ibcon#wrote, iclass 25, count 0 2006.197.07:31:11.87#ibcon#about to read 3, iclass 25, count 0 2006.197.07:31:11.91#ibcon#read 3, iclass 25, count 0 2006.197.07:31:11.91#ibcon#about to read 4, iclass 25, count 0 2006.197.07:31:11.91#ibcon#read 4, iclass 25, count 0 2006.197.07:31:11.91#ibcon#about to read 5, iclass 25, count 0 2006.197.07:31:11.91#ibcon#read 5, iclass 25, count 0 2006.197.07:31:11.91#ibcon#about to read 6, iclass 25, count 0 2006.197.07:31:11.91#ibcon#read 6, iclass 25, count 0 2006.197.07:31:11.91#ibcon#end of sib2, iclass 25, count 0 2006.197.07:31:11.91#ibcon#*after write, iclass 25, count 0 2006.197.07:31:11.91#ibcon#*before return 0, iclass 25, count 0 2006.197.07:31:11.91#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.197.07:31:11.91#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.197.07:31:11.91#ibcon#about to clear, iclass 25 cls_cnt 0 2006.197.07:31:11.91#ibcon#cleared, iclass 25 cls_cnt 0 2006.197.07:31:11.91$vc4f8/vb=6,4 2006.197.07:31:11.91#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.197.07:31:11.91#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.197.07:31:11.91#ibcon#ireg 11 cls_cnt 2 2006.197.07:31:11.91#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.197.07:31:11.97#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.197.07:31:11.97#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.197.07:31:11.97#ibcon#enter wrdev, iclass 27, count 2 2006.197.07:31:11.97#ibcon#first serial, iclass 27, count 2 2006.197.07:31:11.97#ibcon#enter sib2, iclass 27, count 2 2006.197.07:31:11.97#ibcon#flushed, iclass 27, count 2 2006.197.07:31:11.97#ibcon#about to write, iclass 27, count 2 2006.197.07:31:11.97#ibcon#wrote, iclass 27, count 2 2006.197.07:31:11.97#ibcon#about to read 3, iclass 27, count 2 2006.197.07:31:11.99#ibcon#read 3, iclass 27, count 2 2006.197.07:31:11.99#ibcon#about to read 4, iclass 27, count 2 2006.197.07:31:11.99#ibcon#read 4, iclass 27, count 2 2006.197.07:31:11.99#ibcon#about to read 5, iclass 27, count 2 2006.197.07:31:11.99#ibcon#read 5, iclass 27, count 2 2006.197.07:31:11.99#ibcon#about to read 6, iclass 27, count 2 2006.197.07:31:11.99#ibcon#read 6, iclass 27, count 2 2006.197.07:31:11.99#ibcon#end of sib2, iclass 27, count 2 2006.197.07:31:11.99#ibcon#*mode == 0, iclass 27, count 2 2006.197.07:31:11.99#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.197.07:31:11.99#ibcon#[27=AT06-04\r\n] 2006.197.07:31:11.99#ibcon#*before write, iclass 27, count 2 2006.197.07:31:11.99#ibcon#enter sib2, iclass 27, count 2 2006.197.07:31:11.99#ibcon#flushed, iclass 27, count 2 2006.197.07:31:11.99#ibcon#about to write, iclass 27, count 2 2006.197.07:31:11.99#ibcon#wrote, iclass 27, count 2 2006.197.07:31:11.99#ibcon#about to read 3, iclass 27, count 2 2006.197.07:31:12.02#ibcon#read 3, iclass 27, count 2 2006.197.07:31:12.02#ibcon#about to read 4, iclass 27, count 2 2006.197.07:31:12.02#ibcon#read 4, iclass 27, count 2 2006.197.07:31:12.02#ibcon#about to read 5, iclass 27, count 2 2006.197.07:31:12.02#ibcon#read 5, iclass 27, count 2 2006.197.07:31:12.02#ibcon#about to read 6, iclass 27, count 2 2006.197.07:31:12.02#ibcon#read 6, iclass 27, count 2 2006.197.07:31:12.02#ibcon#end of sib2, iclass 27, count 2 2006.197.07:31:12.02#ibcon#*after write, iclass 27, count 2 2006.197.07:31:12.02#ibcon#*before return 0, iclass 27, count 2 2006.197.07:31:12.02#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.197.07:31:12.02#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.197.07:31:12.02#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.197.07:31:12.02#ibcon#ireg 7 cls_cnt 0 2006.197.07:31:12.02#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.197.07:31:12.14#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.197.07:31:12.14#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.197.07:31:12.14#ibcon#enter wrdev, iclass 27, count 0 2006.197.07:31:12.14#ibcon#first serial, iclass 27, count 0 2006.197.07:31:12.14#ibcon#enter sib2, iclass 27, count 0 2006.197.07:31:12.14#ibcon#flushed, iclass 27, count 0 2006.197.07:31:12.14#ibcon#about to write, iclass 27, count 0 2006.197.07:31:12.14#ibcon#wrote, iclass 27, count 0 2006.197.07:31:12.14#ibcon#about to read 3, iclass 27, count 0 2006.197.07:31:12.16#ibcon#read 3, iclass 27, count 0 2006.197.07:31:12.16#ibcon#about to read 4, iclass 27, count 0 2006.197.07:31:12.16#ibcon#read 4, iclass 27, count 0 2006.197.07:31:12.16#ibcon#about to read 5, iclass 27, count 0 2006.197.07:31:12.16#ibcon#read 5, iclass 27, count 0 2006.197.07:31:12.16#ibcon#about to read 6, iclass 27, count 0 2006.197.07:31:12.16#ibcon#read 6, iclass 27, count 0 2006.197.07:31:12.16#ibcon#end of sib2, iclass 27, count 0 2006.197.07:31:12.16#ibcon#*mode == 0, iclass 27, count 0 2006.197.07:31:12.16#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.197.07:31:12.16#ibcon#[27=USB\r\n] 2006.197.07:31:12.16#ibcon#*before write, iclass 27, count 0 2006.197.07:31:12.16#ibcon#enter sib2, iclass 27, count 0 2006.197.07:31:12.16#ibcon#flushed, iclass 27, count 0 2006.197.07:31:12.16#ibcon#about to write, iclass 27, count 0 2006.197.07:31:12.16#ibcon#wrote, iclass 27, count 0 2006.197.07:31:12.16#ibcon#about to read 3, iclass 27, count 0 2006.197.07:31:12.19#ibcon#read 3, iclass 27, count 0 2006.197.07:31:12.19#ibcon#about to read 4, iclass 27, count 0 2006.197.07:31:12.19#ibcon#read 4, iclass 27, count 0 2006.197.07:31:12.19#ibcon#about to read 5, iclass 27, count 0 2006.197.07:31:12.19#ibcon#read 5, iclass 27, count 0 2006.197.07:31:12.19#ibcon#about to read 6, iclass 27, count 0 2006.197.07:31:12.19#ibcon#read 6, iclass 27, count 0 2006.197.07:31:12.19#ibcon#end of sib2, iclass 27, count 0 2006.197.07:31:12.19#ibcon#*after write, iclass 27, count 0 2006.197.07:31:12.19#ibcon#*before return 0, iclass 27, count 0 2006.197.07:31:12.19#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.197.07:31:12.19#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.197.07:31:12.19#ibcon#about to clear, iclass 27 cls_cnt 0 2006.197.07:31:12.19#ibcon#cleared, iclass 27 cls_cnt 0 2006.197.07:31:12.19$vc4f8/vabw=wide 2006.197.07:31:12.19#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.197.07:31:12.19#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.197.07:31:12.19#ibcon#ireg 8 cls_cnt 0 2006.197.07:31:12.19#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.197.07:31:12.19#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.197.07:31:12.19#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.197.07:31:12.19#ibcon#enter wrdev, iclass 29, count 0 2006.197.07:31:12.19#ibcon#first serial, iclass 29, count 0 2006.197.07:31:12.19#ibcon#enter sib2, iclass 29, count 0 2006.197.07:31:12.19#ibcon#flushed, iclass 29, count 0 2006.197.07:31:12.19#ibcon#about to write, iclass 29, count 0 2006.197.07:31:12.19#ibcon#wrote, iclass 29, count 0 2006.197.07:31:12.19#ibcon#about to read 3, iclass 29, count 0 2006.197.07:31:12.21#ibcon#read 3, iclass 29, count 0 2006.197.07:31:12.21#ibcon#about to read 4, iclass 29, count 0 2006.197.07:31:12.21#ibcon#read 4, iclass 29, count 0 2006.197.07:31:12.21#ibcon#about to read 5, iclass 29, count 0 2006.197.07:31:12.21#ibcon#read 5, iclass 29, count 0 2006.197.07:31:12.21#ibcon#about to read 6, iclass 29, count 0 2006.197.07:31:12.21#ibcon#read 6, iclass 29, count 0 2006.197.07:31:12.21#ibcon#end of sib2, iclass 29, count 0 2006.197.07:31:12.21#ibcon#*mode == 0, iclass 29, count 0 2006.197.07:31:12.21#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.197.07:31:12.21#ibcon#[25=BW32\r\n] 2006.197.07:31:12.21#ibcon#*before write, iclass 29, count 0 2006.197.07:31:12.21#ibcon#enter sib2, iclass 29, count 0 2006.197.07:31:12.21#ibcon#flushed, iclass 29, count 0 2006.197.07:31:12.21#ibcon#about to write, iclass 29, count 0 2006.197.07:31:12.21#ibcon#wrote, iclass 29, count 0 2006.197.07:31:12.21#ibcon#about to read 3, iclass 29, count 0 2006.197.07:31:12.24#ibcon#read 3, iclass 29, count 0 2006.197.07:31:12.24#ibcon#about to read 4, iclass 29, count 0 2006.197.07:31:12.24#ibcon#read 4, iclass 29, count 0 2006.197.07:31:12.24#ibcon#about to read 5, iclass 29, count 0 2006.197.07:31:12.24#ibcon#read 5, iclass 29, count 0 2006.197.07:31:12.24#ibcon#about to read 6, iclass 29, count 0 2006.197.07:31:12.24#ibcon#read 6, iclass 29, count 0 2006.197.07:31:12.24#ibcon#end of sib2, iclass 29, count 0 2006.197.07:31:12.24#ibcon#*after write, iclass 29, count 0 2006.197.07:31:12.24#ibcon#*before return 0, iclass 29, count 0 2006.197.07:31:12.24#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.197.07:31:12.24#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.197.07:31:12.24#ibcon#about to clear, iclass 29 cls_cnt 0 2006.197.07:31:12.24#ibcon#cleared, iclass 29 cls_cnt 0 2006.197.07:31:12.24$vc4f8/vbbw=wide 2006.197.07:31:12.24#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.197.07:31:12.24#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.197.07:31:12.24#ibcon#ireg 8 cls_cnt 0 2006.197.07:31:12.24#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.197.07:31:12.31#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.197.07:31:12.31#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.197.07:31:12.31#ibcon#enter wrdev, iclass 31, count 0 2006.197.07:31:12.31#ibcon#first serial, iclass 31, count 0 2006.197.07:31:12.31#ibcon#enter sib2, iclass 31, count 0 2006.197.07:31:12.31#ibcon#flushed, iclass 31, count 0 2006.197.07:31:12.31#ibcon#about to write, iclass 31, count 0 2006.197.07:31:12.31#ibcon#wrote, iclass 31, count 0 2006.197.07:31:12.31#ibcon#about to read 3, iclass 31, count 0 2006.197.07:31:12.33#ibcon#read 3, iclass 31, count 0 2006.197.07:31:12.33#ibcon#about to read 4, iclass 31, count 0 2006.197.07:31:12.33#ibcon#read 4, iclass 31, count 0 2006.197.07:31:12.33#ibcon#about to read 5, iclass 31, count 0 2006.197.07:31:12.33#ibcon#read 5, iclass 31, count 0 2006.197.07:31:12.33#ibcon#about to read 6, iclass 31, count 0 2006.197.07:31:12.33#ibcon#read 6, iclass 31, count 0 2006.197.07:31:12.33#ibcon#end of sib2, iclass 31, count 0 2006.197.07:31:12.33#ibcon#*mode == 0, iclass 31, count 0 2006.197.07:31:12.33#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.197.07:31:12.33#ibcon#[27=BW32\r\n] 2006.197.07:31:12.33#ibcon#*before write, iclass 31, count 0 2006.197.07:31:12.33#ibcon#enter sib2, iclass 31, count 0 2006.197.07:31:12.33#ibcon#flushed, iclass 31, count 0 2006.197.07:31:12.33#ibcon#about to write, iclass 31, count 0 2006.197.07:31:12.33#ibcon#wrote, iclass 31, count 0 2006.197.07:31:12.33#ibcon#about to read 3, iclass 31, count 0 2006.197.07:31:12.36#ibcon#read 3, iclass 31, count 0 2006.197.07:31:12.36#ibcon#about to read 4, iclass 31, count 0 2006.197.07:31:12.36#ibcon#read 4, iclass 31, count 0 2006.197.07:31:12.36#ibcon#about to read 5, iclass 31, count 0 2006.197.07:31:12.36#ibcon#read 5, iclass 31, count 0 2006.197.07:31:12.36#ibcon#about to read 6, iclass 31, count 0 2006.197.07:31:12.36#ibcon#read 6, iclass 31, count 0 2006.197.07:31:12.36#ibcon#end of sib2, iclass 31, count 0 2006.197.07:31:12.36#ibcon#*after write, iclass 31, count 0 2006.197.07:31:12.36#ibcon#*before return 0, iclass 31, count 0 2006.197.07:31:12.36#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.197.07:31:12.36#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.197.07:31:12.36#ibcon#about to clear, iclass 31 cls_cnt 0 2006.197.07:31:12.36#ibcon#cleared, iclass 31 cls_cnt 0 2006.197.07:31:12.36$4f8m12a/ifd4f 2006.197.07:31:12.36$ifd4f/lo= 2006.197.07:31:12.36$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.197.07:31:12.36$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.197.07:31:12.36$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.197.07:31:12.36$ifd4f/patch= 2006.197.07:31:12.36$ifd4f/patch=lo1,a1,a2,a3,a4 2006.197.07:31:12.36$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.197.07:31:12.36$ifd4f/patch=lo3,a5,a6,a7,a8 2006.197.07:31:12.36$4f8m12a/"form=m,16.000,1:2 2006.197.07:31:12.36$4f8m12a/"tpicd 2006.197.07:31:12.36$4f8m12a/echo=off 2006.197.07:31:12.36$4f8m12a/xlog=off 2006.197.07:31:12.36:!2006.197.07:33:20 2006.197.07:31:55.14#trakl#Source acquired 2006.197.07:31:55.14#flagr#flagr/antenna,acquired 2006.197.07:33:20.00:preob 2006.197.07:33:20.14/onsource/TRACKING 2006.197.07:33:20.14:!2006.197.07:33:30 2006.197.07:33:30.00:data_valid=on 2006.197.07:33:30.00:midob 2006.197.07:33:31.14/onsource/TRACKING 2006.197.07:33:31.14/wx/25.93,1003.0,97 2006.197.07:33:31.25/cable/+6.3709E-03 2006.197.07:33:32.34/va/01,08,usb,yes,30,32 2006.197.07:33:32.34/va/02,07,usb,yes,30,32 2006.197.07:33:32.34/va/03,06,usb,yes,32,32 2006.197.07:33:32.34/va/04,07,usb,yes,31,33 2006.197.07:33:32.34/va/05,07,usb,yes,35,37 2006.197.07:33:32.34/va/06,06,usb,yes,34,33 2006.197.07:33:32.34/va/07,06,usb,yes,34,34 2006.197.07:33:32.34/va/08,07,usb,yes,32,32 2006.197.07:33:32.57/valo/01,532.99,yes,locked 2006.197.07:33:32.57/valo/02,572.99,yes,locked 2006.197.07:33:32.57/valo/03,672.99,yes,locked 2006.197.07:33:32.57/valo/04,832.99,yes,locked 2006.197.07:33:32.57/valo/05,652.99,yes,locked 2006.197.07:33:32.57/valo/06,772.99,yes,locked 2006.197.07:33:32.57/valo/07,832.99,yes,locked 2006.197.07:33:32.57/valo/08,852.99,yes,locked 2006.197.07:33:33.66/vb/01,04,usb,yes,29,28 2006.197.07:33:33.66/vb/02,04,usb,yes,31,33 2006.197.07:33:33.66/vb/03,04,usb,yes,28,31 2006.197.07:33:33.66/vb/04,04,usb,yes,28,28 2006.197.07:33:33.66/vb/05,04,usb,yes,27,31 2006.197.07:33:33.66/vb/06,04,usb,yes,28,31 2006.197.07:33:33.66/vb/07,04,usb,yes,30,30 2006.197.07:33:33.66/vb/08,04,usb,yes,27,31 2006.197.07:33:33.89/vblo/01,632.99,yes,locked 2006.197.07:33:33.89/vblo/02,640.99,yes,locked 2006.197.07:33:33.89/vblo/03,656.99,yes,locked 2006.197.07:33:33.89/vblo/04,712.99,yes,locked 2006.197.07:33:33.89/vblo/05,744.99,yes,locked 2006.197.07:33:33.89/vblo/06,752.99,yes,locked 2006.197.07:33:33.89/vblo/07,734.99,yes,locked 2006.197.07:33:33.89/vblo/08,744.99,yes,locked 2006.197.07:33:34.04/vabw/8 2006.197.07:33:34.19/vbbw/8 2006.197.07:33:34.39/xfe/off,on,15.2 2006.197.07:33:34.76/ifatt/23,28,28,28 2006.197.07:33:35.10/fmout-gps/S +2.96E-07 2006.197.07:33:35.14:!2006.197.07:34:30 2006.197.07:34:30.00:data_valid=off 2006.197.07:34:30.00:postob 2006.197.07:34:30.10/cable/+6.3701E-03 2006.197.07:34:30.10/wx/25.93,1003.0,97 2006.197.07:34:31.10/fmout-gps/S +2.96E-07 2006.197.07:34:31.10:scan_name=197-0735,k06197,60 2006.197.07:34:31.10:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.197.07:34:31.14#flagr#flagr/antenna,new-source 2006.197.07:34:32.14:checkk5 2006.197.07:34:32.48/chk_autoobs//k5ts1/ autoobs is running! 2006.197.07:34:32.82/chk_autoobs//k5ts2/ autoobs is running! 2006.197.07:34:33.16/chk_autoobs//k5ts3/ autoobs is running! 2006.197.07:34:33.49/chk_autoobs//k5ts4/ autoobs is running! 2006.197.07:34:33.83/chk_obsdata//k5ts1/T1970733??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.07:34:34.14/chk_obsdata//k5ts2/T1970733??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.07:34:34.48/chk_obsdata//k5ts3/T1970733??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.07:34:34.82/chk_obsdata//k5ts4/T1970733??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.07:34:35.47/k5log//k5ts1_log_newline 2006.197.07:34:36.12/k5log//k5ts2_log_newline 2006.197.07:34:36.78/k5log//k5ts3_log_newline 2006.197.07:34:37.45/k5log//k5ts4_log_newline 2006.197.07:34:37.47/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.197.07:34:37.47:4f8m12a=1 2006.197.07:34:37.47$4f8m12a/echo=on 2006.197.07:34:37.47$4f8m12a/pcalon 2006.197.07:34:37.47$pcalon/"no phase cal control is implemented here 2006.197.07:34:37.47$4f8m12a/"tpicd=stop 2006.197.07:34:37.47$4f8m12a/vc4f8 2006.197.07:34:37.47$vc4f8/valo=1,532.99 2006.197.07:34:37.48#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.197.07:34:37.48#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.197.07:34:37.48#ibcon#ireg 17 cls_cnt 0 2006.197.07:34:37.48#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.197.07:34:37.48#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.197.07:34:37.48#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.197.07:34:37.48#ibcon#enter wrdev, iclass 4, count 0 2006.197.07:34:37.48#ibcon#first serial, iclass 4, count 0 2006.197.07:34:37.48#ibcon#enter sib2, iclass 4, count 0 2006.197.07:34:37.48#ibcon#flushed, iclass 4, count 0 2006.197.07:34:37.48#ibcon#about to write, iclass 4, count 0 2006.197.07:34:37.48#ibcon#wrote, iclass 4, count 0 2006.197.07:34:37.48#ibcon#about to read 3, iclass 4, count 0 2006.197.07:34:37.50#ibcon#read 3, iclass 4, count 0 2006.197.07:34:37.50#ibcon#about to read 4, iclass 4, count 0 2006.197.07:34:37.50#ibcon#read 4, iclass 4, count 0 2006.197.07:34:37.50#ibcon#about to read 5, iclass 4, count 0 2006.197.07:34:37.50#ibcon#read 5, iclass 4, count 0 2006.197.07:34:37.50#ibcon#about to read 6, iclass 4, count 0 2006.197.07:34:37.50#ibcon#read 6, iclass 4, count 0 2006.197.07:34:37.50#ibcon#end of sib2, iclass 4, count 0 2006.197.07:34:37.50#ibcon#*mode == 0, iclass 4, count 0 2006.197.07:34:37.50#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.197.07:34:37.50#ibcon#[26=FRQ=01,532.99\r\n] 2006.197.07:34:37.50#ibcon#*before write, iclass 4, count 0 2006.197.07:34:37.50#ibcon#enter sib2, iclass 4, count 0 2006.197.07:34:37.50#ibcon#flushed, iclass 4, count 0 2006.197.07:34:37.50#ibcon#about to write, iclass 4, count 0 2006.197.07:34:37.50#ibcon#wrote, iclass 4, count 0 2006.197.07:34:37.50#ibcon#about to read 3, iclass 4, count 0 2006.197.07:34:37.55#ibcon#read 3, iclass 4, count 0 2006.197.07:34:37.55#ibcon#about to read 4, iclass 4, count 0 2006.197.07:34:37.55#ibcon#read 4, iclass 4, count 0 2006.197.07:34:37.55#ibcon#about to read 5, iclass 4, count 0 2006.197.07:34:37.55#ibcon#read 5, iclass 4, count 0 2006.197.07:34:37.55#ibcon#about to read 6, iclass 4, count 0 2006.197.07:34:37.55#ibcon#read 6, iclass 4, count 0 2006.197.07:34:37.55#ibcon#end of sib2, iclass 4, count 0 2006.197.07:34:37.55#ibcon#*after write, iclass 4, count 0 2006.197.07:34:37.55#ibcon#*before return 0, iclass 4, count 0 2006.197.07:34:37.55#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.197.07:34:37.55#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.197.07:34:37.55#ibcon#about to clear, iclass 4 cls_cnt 0 2006.197.07:34:37.55#ibcon#cleared, iclass 4 cls_cnt 0 2006.197.07:34:37.55$vc4f8/va=1,8 2006.197.07:34:37.55#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.197.07:34:37.55#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.197.07:34:37.55#ibcon#ireg 11 cls_cnt 2 2006.197.07:34:37.55#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.197.07:34:37.55#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.197.07:34:37.55#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.197.07:34:37.55#ibcon#enter wrdev, iclass 6, count 2 2006.197.07:34:37.55#ibcon#first serial, iclass 6, count 2 2006.197.07:34:37.55#ibcon#enter sib2, iclass 6, count 2 2006.197.07:34:37.55#ibcon#flushed, iclass 6, count 2 2006.197.07:34:37.55#ibcon#about to write, iclass 6, count 2 2006.197.07:34:37.55#ibcon#wrote, iclass 6, count 2 2006.197.07:34:37.55#ibcon#about to read 3, iclass 6, count 2 2006.197.07:34:37.57#ibcon#read 3, iclass 6, count 2 2006.197.07:34:37.57#ibcon#about to read 4, iclass 6, count 2 2006.197.07:34:37.57#ibcon#read 4, iclass 6, count 2 2006.197.07:34:37.57#ibcon#about to read 5, iclass 6, count 2 2006.197.07:34:37.57#ibcon#read 5, iclass 6, count 2 2006.197.07:34:37.57#ibcon#about to read 6, iclass 6, count 2 2006.197.07:34:37.57#ibcon#read 6, iclass 6, count 2 2006.197.07:34:37.57#ibcon#end of sib2, iclass 6, count 2 2006.197.07:34:37.57#ibcon#*mode == 0, iclass 6, count 2 2006.197.07:34:37.57#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.197.07:34:37.57#ibcon#[25=AT01-08\r\n] 2006.197.07:34:37.57#ibcon#*before write, iclass 6, count 2 2006.197.07:34:37.57#ibcon#enter sib2, iclass 6, count 2 2006.197.07:34:37.57#ibcon#flushed, iclass 6, count 2 2006.197.07:34:37.57#ibcon#about to write, iclass 6, count 2 2006.197.07:34:37.57#ibcon#wrote, iclass 6, count 2 2006.197.07:34:37.57#ibcon#about to read 3, iclass 6, count 2 2006.197.07:34:37.60#ibcon#read 3, iclass 6, count 2 2006.197.07:34:37.60#ibcon#about to read 4, iclass 6, count 2 2006.197.07:34:37.60#ibcon#read 4, iclass 6, count 2 2006.197.07:34:37.60#ibcon#about to read 5, iclass 6, count 2 2006.197.07:34:37.60#ibcon#read 5, iclass 6, count 2 2006.197.07:34:37.60#ibcon#about to read 6, iclass 6, count 2 2006.197.07:34:37.60#ibcon#read 6, iclass 6, count 2 2006.197.07:34:37.60#ibcon#end of sib2, iclass 6, count 2 2006.197.07:34:37.60#ibcon#*after write, iclass 6, count 2 2006.197.07:34:37.60#ibcon#*before return 0, iclass 6, count 2 2006.197.07:34:37.60#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.197.07:34:37.60#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.197.07:34:37.60#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.197.07:34:37.60#ibcon#ireg 7 cls_cnt 0 2006.197.07:34:37.60#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.197.07:34:37.72#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.197.07:34:37.72#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.197.07:34:37.72#ibcon#enter wrdev, iclass 6, count 0 2006.197.07:34:37.72#ibcon#first serial, iclass 6, count 0 2006.197.07:34:37.72#ibcon#enter sib2, iclass 6, count 0 2006.197.07:34:37.72#ibcon#flushed, iclass 6, count 0 2006.197.07:34:37.72#ibcon#about to write, iclass 6, count 0 2006.197.07:34:37.72#ibcon#wrote, iclass 6, count 0 2006.197.07:34:37.72#ibcon#about to read 3, iclass 6, count 0 2006.197.07:34:37.74#ibcon#read 3, iclass 6, count 0 2006.197.07:34:37.74#ibcon#about to read 4, iclass 6, count 0 2006.197.07:34:37.74#ibcon#read 4, iclass 6, count 0 2006.197.07:34:37.74#ibcon#about to read 5, iclass 6, count 0 2006.197.07:34:37.74#ibcon#read 5, iclass 6, count 0 2006.197.07:34:37.74#ibcon#about to read 6, iclass 6, count 0 2006.197.07:34:37.74#ibcon#read 6, iclass 6, count 0 2006.197.07:34:37.74#ibcon#end of sib2, iclass 6, count 0 2006.197.07:34:37.74#ibcon#*mode == 0, iclass 6, count 0 2006.197.07:34:37.74#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.197.07:34:37.74#ibcon#[25=USB\r\n] 2006.197.07:34:37.74#ibcon#*before write, iclass 6, count 0 2006.197.07:34:37.74#ibcon#enter sib2, iclass 6, count 0 2006.197.07:34:37.74#ibcon#flushed, iclass 6, count 0 2006.197.07:34:37.74#ibcon#about to write, iclass 6, count 0 2006.197.07:34:37.74#ibcon#wrote, iclass 6, count 0 2006.197.07:34:37.74#ibcon#about to read 3, iclass 6, count 0 2006.197.07:34:37.77#ibcon#read 3, iclass 6, count 0 2006.197.07:34:37.77#ibcon#about to read 4, iclass 6, count 0 2006.197.07:34:37.77#ibcon#read 4, iclass 6, count 0 2006.197.07:34:37.77#ibcon#about to read 5, iclass 6, count 0 2006.197.07:34:37.77#ibcon#read 5, iclass 6, count 0 2006.197.07:34:37.77#ibcon#about to read 6, iclass 6, count 0 2006.197.07:34:37.77#ibcon#read 6, iclass 6, count 0 2006.197.07:34:37.77#ibcon#end of sib2, iclass 6, count 0 2006.197.07:34:37.77#ibcon#*after write, iclass 6, count 0 2006.197.07:34:37.77#ibcon#*before return 0, iclass 6, count 0 2006.197.07:34:37.77#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.197.07:34:37.77#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.197.07:34:37.77#ibcon#about to clear, iclass 6 cls_cnt 0 2006.197.07:34:37.77#ibcon#cleared, iclass 6 cls_cnt 0 2006.197.07:34:37.77$vc4f8/valo=2,572.99 2006.197.07:34:37.77#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.197.07:34:37.77#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.197.07:34:37.77#ibcon#ireg 17 cls_cnt 0 2006.197.07:34:37.77#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.197.07:34:37.77#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.197.07:34:37.77#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.197.07:34:37.77#ibcon#enter wrdev, iclass 10, count 0 2006.197.07:34:37.77#ibcon#first serial, iclass 10, count 0 2006.197.07:34:37.77#ibcon#enter sib2, iclass 10, count 0 2006.197.07:34:37.77#ibcon#flushed, iclass 10, count 0 2006.197.07:34:37.77#ibcon#about to write, iclass 10, count 0 2006.197.07:34:37.77#ibcon#wrote, iclass 10, count 0 2006.197.07:34:37.77#ibcon#about to read 3, iclass 10, count 0 2006.197.07:34:37.79#ibcon#read 3, iclass 10, count 0 2006.197.07:34:37.79#ibcon#about to read 4, iclass 10, count 0 2006.197.07:34:37.79#ibcon#read 4, iclass 10, count 0 2006.197.07:34:37.79#ibcon#about to read 5, iclass 10, count 0 2006.197.07:34:37.79#ibcon#read 5, iclass 10, count 0 2006.197.07:34:37.79#ibcon#about to read 6, iclass 10, count 0 2006.197.07:34:37.79#ibcon#read 6, iclass 10, count 0 2006.197.07:34:37.79#ibcon#end of sib2, iclass 10, count 0 2006.197.07:34:37.79#ibcon#*mode == 0, iclass 10, count 0 2006.197.07:34:37.79#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.197.07:34:37.79#ibcon#[26=FRQ=02,572.99\r\n] 2006.197.07:34:37.79#ibcon#*before write, iclass 10, count 0 2006.197.07:34:37.79#ibcon#enter sib2, iclass 10, count 0 2006.197.07:34:37.79#ibcon#flushed, iclass 10, count 0 2006.197.07:34:37.79#ibcon#about to write, iclass 10, count 0 2006.197.07:34:37.79#ibcon#wrote, iclass 10, count 0 2006.197.07:34:37.79#ibcon#about to read 3, iclass 10, count 0 2006.197.07:34:37.83#ibcon#read 3, iclass 10, count 0 2006.197.07:34:37.83#ibcon#about to read 4, iclass 10, count 0 2006.197.07:34:37.83#ibcon#read 4, iclass 10, count 0 2006.197.07:34:37.83#ibcon#about to read 5, iclass 10, count 0 2006.197.07:34:37.83#ibcon#read 5, iclass 10, count 0 2006.197.07:34:37.83#ibcon#about to read 6, iclass 10, count 0 2006.197.07:34:37.83#ibcon#read 6, iclass 10, count 0 2006.197.07:34:37.83#ibcon#end of sib2, iclass 10, count 0 2006.197.07:34:37.83#ibcon#*after write, iclass 10, count 0 2006.197.07:34:37.83#ibcon#*before return 0, iclass 10, count 0 2006.197.07:34:37.83#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.197.07:34:37.83#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.197.07:34:37.83#ibcon#about to clear, iclass 10 cls_cnt 0 2006.197.07:34:37.83#ibcon#cleared, iclass 10 cls_cnt 0 2006.197.07:34:37.83$vc4f8/va=2,7 2006.197.07:34:37.83#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.197.07:34:37.83#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.197.07:34:37.83#ibcon#ireg 11 cls_cnt 2 2006.197.07:34:37.83#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.197.07:34:37.89#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.197.07:34:37.89#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.197.07:34:37.89#ibcon#enter wrdev, iclass 12, count 2 2006.197.07:34:37.89#ibcon#first serial, iclass 12, count 2 2006.197.07:34:37.89#ibcon#enter sib2, iclass 12, count 2 2006.197.07:34:37.89#ibcon#flushed, iclass 12, count 2 2006.197.07:34:37.89#ibcon#about to write, iclass 12, count 2 2006.197.07:34:37.89#ibcon#wrote, iclass 12, count 2 2006.197.07:34:37.89#ibcon#about to read 3, iclass 12, count 2 2006.197.07:34:37.91#ibcon#read 3, iclass 12, count 2 2006.197.07:34:37.91#ibcon#about to read 4, iclass 12, count 2 2006.197.07:34:37.91#ibcon#read 4, iclass 12, count 2 2006.197.07:34:37.91#ibcon#about to read 5, iclass 12, count 2 2006.197.07:34:37.91#ibcon#read 5, iclass 12, count 2 2006.197.07:34:37.91#ibcon#about to read 6, iclass 12, count 2 2006.197.07:34:37.91#ibcon#read 6, iclass 12, count 2 2006.197.07:34:37.91#ibcon#end of sib2, iclass 12, count 2 2006.197.07:34:37.91#ibcon#*mode == 0, iclass 12, count 2 2006.197.07:34:37.91#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.197.07:34:37.91#ibcon#[25=AT02-07\r\n] 2006.197.07:34:37.91#ibcon#*before write, iclass 12, count 2 2006.197.07:34:37.91#ibcon#enter sib2, iclass 12, count 2 2006.197.07:34:37.91#ibcon#flushed, iclass 12, count 2 2006.197.07:34:37.91#ibcon#about to write, iclass 12, count 2 2006.197.07:34:37.91#ibcon#wrote, iclass 12, count 2 2006.197.07:34:37.91#ibcon#about to read 3, iclass 12, count 2 2006.197.07:34:37.94#ibcon#read 3, iclass 12, count 2 2006.197.07:34:37.94#ibcon#about to read 4, iclass 12, count 2 2006.197.07:34:37.94#ibcon#read 4, iclass 12, count 2 2006.197.07:34:37.94#ibcon#about to read 5, iclass 12, count 2 2006.197.07:34:37.94#ibcon#read 5, iclass 12, count 2 2006.197.07:34:37.94#ibcon#about to read 6, iclass 12, count 2 2006.197.07:34:37.94#ibcon#read 6, iclass 12, count 2 2006.197.07:34:37.94#ibcon#end of sib2, iclass 12, count 2 2006.197.07:34:37.94#ibcon#*after write, iclass 12, count 2 2006.197.07:34:37.94#ibcon#*before return 0, iclass 12, count 2 2006.197.07:34:37.94#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.197.07:34:37.94#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.197.07:34:37.94#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.197.07:34:37.94#ibcon#ireg 7 cls_cnt 0 2006.197.07:34:37.94#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.197.07:34:38.06#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.197.07:34:38.06#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.197.07:34:38.06#ibcon#enter wrdev, iclass 12, count 0 2006.197.07:34:38.06#ibcon#first serial, iclass 12, count 0 2006.197.07:34:38.06#ibcon#enter sib2, iclass 12, count 0 2006.197.07:34:38.06#ibcon#flushed, iclass 12, count 0 2006.197.07:34:38.06#ibcon#about to write, iclass 12, count 0 2006.197.07:34:38.06#ibcon#wrote, iclass 12, count 0 2006.197.07:34:38.06#ibcon#about to read 3, iclass 12, count 0 2006.197.07:34:38.08#ibcon#read 3, iclass 12, count 0 2006.197.07:34:38.08#ibcon#about to read 4, iclass 12, count 0 2006.197.07:34:38.08#ibcon#read 4, iclass 12, count 0 2006.197.07:34:38.08#ibcon#about to read 5, iclass 12, count 0 2006.197.07:34:38.08#ibcon#read 5, iclass 12, count 0 2006.197.07:34:38.08#ibcon#about to read 6, iclass 12, count 0 2006.197.07:34:38.08#ibcon#read 6, iclass 12, count 0 2006.197.07:34:38.08#ibcon#end of sib2, iclass 12, count 0 2006.197.07:34:38.08#ibcon#*mode == 0, iclass 12, count 0 2006.197.07:34:38.08#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.197.07:34:38.08#ibcon#[25=USB\r\n] 2006.197.07:34:38.08#ibcon#*before write, iclass 12, count 0 2006.197.07:34:38.08#ibcon#enter sib2, iclass 12, count 0 2006.197.07:34:38.08#ibcon#flushed, iclass 12, count 0 2006.197.07:34:38.08#ibcon#about to write, iclass 12, count 0 2006.197.07:34:38.08#ibcon#wrote, iclass 12, count 0 2006.197.07:34:38.08#ibcon#about to read 3, iclass 12, count 0 2006.197.07:34:38.11#ibcon#read 3, iclass 12, count 0 2006.197.07:34:38.11#ibcon#about to read 4, iclass 12, count 0 2006.197.07:34:38.11#ibcon#read 4, iclass 12, count 0 2006.197.07:34:38.11#ibcon#about to read 5, iclass 12, count 0 2006.197.07:34:38.11#ibcon#read 5, iclass 12, count 0 2006.197.07:34:38.11#ibcon#about to read 6, iclass 12, count 0 2006.197.07:34:38.11#ibcon#read 6, iclass 12, count 0 2006.197.07:34:38.11#ibcon#end of sib2, iclass 12, count 0 2006.197.07:34:38.11#ibcon#*after write, iclass 12, count 0 2006.197.07:34:38.11#ibcon#*before return 0, iclass 12, count 0 2006.197.07:34:38.11#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.197.07:34:38.11#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.197.07:34:38.11#ibcon#about to clear, iclass 12 cls_cnt 0 2006.197.07:34:38.11#ibcon#cleared, iclass 12 cls_cnt 0 2006.197.07:34:38.11$vc4f8/valo=3,672.99 2006.197.07:34:38.11#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.197.07:34:38.11#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.197.07:34:38.11#ibcon#ireg 17 cls_cnt 0 2006.197.07:34:38.11#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.197.07:34:38.11#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.197.07:34:38.11#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.197.07:34:38.11#ibcon#enter wrdev, iclass 14, count 0 2006.197.07:34:38.11#ibcon#first serial, iclass 14, count 0 2006.197.07:34:38.11#ibcon#enter sib2, iclass 14, count 0 2006.197.07:34:38.11#ibcon#flushed, iclass 14, count 0 2006.197.07:34:38.11#ibcon#about to write, iclass 14, count 0 2006.197.07:34:38.11#ibcon#wrote, iclass 14, count 0 2006.197.07:34:38.11#ibcon#about to read 3, iclass 14, count 0 2006.197.07:34:38.13#ibcon#read 3, iclass 14, count 0 2006.197.07:34:38.13#ibcon#about to read 4, iclass 14, count 0 2006.197.07:34:38.13#ibcon#read 4, iclass 14, count 0 2006.197.07:34:38.13#ibcon#about to read 5, iclass 14, count 0 2006.197.07:34:38.13#ibcon#read 5, iclass 14, count 0 2006.197.07:34:38.13#ibcon#about to read 6, iclass 14, count 0 2006.197.07:34:38.13#ibcon#read 6, iclass 14, count 0 2006.197.07:34:38.13#ibcon#end of sib2, iclass 14, count 0 2006.197.07:34:38.13#ibcon#*mode == 0, iclass 14, count 0 2006.197.07:34:38.13#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.197.07:34:38.13#ibcon#[26=FRQ=03,672.99\r\n] 2006.197.07:34:38.13#ibcon#*before write, iclass 14, count 0 2006.197.07:34:38.13#ibcon#enter sib2, iclass 14, count 0 2006.197.07:34:38.13#ibcon#flushed, iclass 14, count 0 2006.197.07:34:38.13#ibcon#about to write, iclass 14, count 0 2006.197.07:34:38.13#ibcon#wrote, iclass 14, count 0 2006.197.07:34:38.13#ibcon#about to read 3, iclass 14, count 0 2006.197.07:34:38.17#ibcon#read 3, iclass 14, count 0 2006.197.07:34:38.17#ibcon#about to read 4, iclass 14, count 0 2006.197.07:34:38.17#ibcon#read 4, iclass 14, count 0 2006.197.07:34:38.17#ibcon#about to read 5, iclass 14, count 0 2006.197.07:34:38.17#ibcon#read 5, iclass 14, count 0 2006.197.07:34:38.17#ibcon#about to read 6, iclass 14, count 0 2006.197.07:34:38.17#ibcon#read 6, iclass 14, count 0 2006.197.07:34:38.17#ibcon#end of sib2, iclass 14, count 0 2006.197.07:34:38.17#ibcon#*after write, iclass 14, count 0 2006.197.07:34:38.17#ibcon#*before return 0, iclass 14, count 0 2006.197.07:34:38.17#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.197.07:34:38.17#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.197.07:34:38.17#ibcon#about to clear, iclass 14 cls_cnt 0 2006.197.07:34:38.17#ibcon#cleared, iclass 14 cls_cnt 0 2006.197.07:34:38.17$vc4f8/va=3,6 2006.197.07:34:38.17#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.197.07:34:38.17#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.197.07:34:38.17#ibcon#ireg 11 cls_cnt 2 2006.197.07:34:38.17#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.197.07:34:38.23#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.197.07:34:38.23#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.197.07:34:38.23#ibcon#enter wrdev, iclass 16, count 2 2006.197.07:34:38.23#ibcon#first serial, iclass 16, count 2 2006.197.07:34:38.23#ibcon#enter sib2, iclass 16, count 2 2006.197.07:34:38.23#ibcon#flushed, iclass 16, count 2 2006.197.07:34:38.23#ibcon#about to write, iclass 16, count 2 2006.197.07:34:38.23#ibcon#wrote, iclass 16, count 2 2006.197.07:34:38.23#ibcon#about to read 3, iclass 16, count 2 2006.197.07:34:38.25#ibcon#read 3, iclass 16, count 2 2006.197.07:34:38.25#ibcon#about to read 4, iclass 16, count 2 2006.197.07:34:38.25#ibcon#read 4, iclass 16, count 2 2006.197.07:34:38.25#ibcon#about to read 5, iclass 16, count 2 2006.197.07:34:38.25#ibcon#read 5, iclass 16, count 2 2006.197.07:34:38.25#ibcon#about to read 6, iclass 16, count 2 2006.197.07:34:38.25#ibcon#read 6, iclass 16, count 2 2006.197.07:34:38.25#ibcon#end of sib2, iclass 16, count 2 2006.197.07:34:38.25#ibcon#*mode == 0, iclass 16, count 2 2006.197.07:34:38.25#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.197.07:34:38.25#ibcon#[25=AT03-06\r\n] 2006.197.07:34:38.25#ibcon#*before write, iclass 16, count 2 2006.197.07:34:38.25#ibcon#enter sib2, iclass 16, count 2 2006.197.07:34:38.25#ibcon#flushed, iclass 16, count 2 2006.197.07:34:38.25#ibcon#about to write, iclass 16, count 2 2006.197.07:34:38.25#ibcon#wrote, iclass 16, count 2 2006.197.07:34:38.25#ibcon#about to read 3, iclass 16, count 2 2006.197.07:34:38.28#ibcon#read 3, iclass 16, count 2 2006.197.07:34:38.28#ibcon#about to read 4, iclass 16, count 2 2006.197.07:34:38.28#ibcon#read 4, iclass 16, count 2 2006.197.07:34:38.28#ibcon#about to read 5, iclass 16, count 2 2006.197.07:34:38.28#ibcon#read 5, iclass 16, count 2 2006.197.07:34:38.28#ibcon#about to read 6, iclass 16, count 2 2006.197.07:34:38.28#ibcon#read 6, iclass 16, count 2 2006.197.07:34:38.28#ibcon#end of sib2, iclass 16, count 2 2006.197.07:34:38.28#ibcon#*after write, iclass 16, count 2 2006.197.07:34:38.28#ibcon#*before return 0, iclass 16, count 2 2006.197.07:34:38.28#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.197.07:34:38.28#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.197.07:34:38.28#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.197.07:34:38.28#ibcon#ireg 7 cls_cnt 0 2006.197.07:34:38.28#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.197.07:34:38.40#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.197.07:34:38.40#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.197.07:34:38.40#ibcon#enter wrdev, iclass 16, count 0 2006.197.07:34:38.40#ibcon#first serial, iclass 16, count 0 2006.197.07:34:38.40#ibcon#enter sib2, iclass 16, count 0 2006.197.07:34:38.40#ibcon#flushed, iclass 16, count 0 2006.197.07:34:38.40#ibcon#about to write, iclass 16, count 0 2006.197.07:34:38.40#ibcon#wrote, iclass 16, count 0 2006.197.07:34:38.40#ibcon#about to read 3, iclass 16, count 0 2006.197.07:34:38.42#ibcon#read 3, iclass 16, count 0 2006.197.07:34:38.42#ibcon#about to read 4, iclass 16, count 0 2006.197.07:34:38.42#ibcon#read 4, iclass 16, count 0 2006.197.07:34:38.42#ibcon#about to read 5, iclass 16, count 0 2006.197.07:34:38.42#ibcon#read 5, iclass 16, count 0 2006.197.07:34:38.42#ibcon#about to read 6, iclass 16, count 0 2006.197.07:34:38.42#ibcon#read 6, iclass 16, count 0 2006.197.07:34:38.42#ibcon#end of sib2, iclass 16, count 0 2006.197.07:34:38.42#ibcon#*mode == 0, iclass 16, count 0 2006.197.07:34:38.42#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.197.07:34:38.42#ibcon#[25=USB\r\n] 2006.197.07:34:38.42#ibcon#*before write, iclass 16, count 0 2006.197.07:34:38.42#ibcon#enter sib2, iclass 16, count 0 2006.197.07:34:38.42#ibcon#flushed, iclass 16, count 0 2006.197.07:34:38.42#ibcon#about to write, iclass 16, count 0 2006.197.07:34:38.42#ibcon#wrote, iclass 16, count 0 2006.197.07:34:38.42#ibcon#about to read 3, iclass 16, count 0 2006.197.07:34:38.45#ibcon#read 3, iclass 16, count 0 2006.197.07:34:38.45#ibcon#about to read 4, iclass 16, count 0 2006.197.07:34:38.45#ibcon#read 4, iclass 16, count 0 2006.197.07:34:38.45#ibcon#about to read 5, iclass 16, count 0 2006.197.07:34:38.45#ibcon#read 5, iclass 16, count 0 2006.197.07:34:38.45#ibcon#about to read 6, iclass 16, count 0 2006.197.07:34:38.45#ibcon#read 6, iclass 16, count 0 2006.197.07:34:38.45#ibcon#end of sib2, iclass 16, count 0 2006.197.07:34:38.45#ibcon#*after write, iclass 16, count 0 2006.197.07:34:38.45#ibcon#*before return 0, iclass 16, count 0 2006.197.07:34:38.45#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.197.07:34:38.45#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.197.07:34:38.45#ibcon#about to clear, iclass 16 cls_cnt 0 2006.197.07:34:38.45#ibcon#cleared, iclass 16 cls_cnt 0 2006.197.07:34:38.45$vc4f8/valo=4,832.99 2006.197.07:34:38.45#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.197.07:34:38.45#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.197.07:34:38.45#ibcon#ireg 17 cls_cnt 0 2006.197.07:34:38.45#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.197.07:34:38.45#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.197.07:34:38.45#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.197.07:34:38.45#ibcon#enter wrdev, iclass 18, count 0 2006.197.07:34:38.45#ibcon#first serial, iclass 18, count 0 2006.197.07:34:38.45#ibcon#enter sib2, iclass 18, count 0 2006.197.07:34:38.45#ibcon#flushed, iclass 18, count 0 2006.197.07:34:38.45#ibcon#about to write, iclass 18, count 0 2006.197.07:34:38.45#ibcon#wrote, iclass 18, count 0 2006.197.07:34:38.45#ibcon#about to read 3, iclass 18, count 0 2006.197.07:34:38.47#ibcon#read 3, iclass 18, count 0 2006.197.07:34:38.47#ibcon#about to read 4, iclass 18, count 0 2006.197.07:34:38.47#ibcon#read 4, iclass 18, count 0 2006.197.07:34:38.47#ibcon#about to read 5, iclass 18, count 0 2006.197.07:34:38.47#ibcon#read 5, iclass 18, count 0 2006.197.07:34:38.47#ibcon#about to read 6, iclass 18, count 0 2006.197.07:34:38.47#ibcon#read 6, iclass 18, count 0 2006.197.07:34:38.47#ibcon#end of sib2, iclass 18, count 0 2006.197.07:34:38.47#ibcon#*mode == 0, iclass 18, count 0 2006.197.07:34:38.47#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.197.07:34:38.47#ibcon#[26=FRQ=04,832.99\r\n] 2006.197.07:34:38.47#ibcon#*before write, iclass 18, count 0 2006.197.07:34:38.47#ibcon#enter sib2, iclass 18, count 0 2006.197.07:34:38.47#ibcon#flushed, iclass 18, count 0 2006.197.07:34:38.47#ibcon#about to write, iclass 18, count 0 2006.197.07:34:38.47#ibcon#wrote, iclass 18, count 0 2006.197.07:34:38.47#ibcon#about to read 3, iclass 18, count 0 2006.197.07:34:38.51#ibcon#read 3, iclass 18, count 0 2006.197.07:34:38.51#ibcon#about to read 4, iclass 18, count 0 2006.197.07:34:38.51#ibcon#read 4, iclass 18, count 0 2006.197.07:34:38.51#ibcon#about to read 5, iclass 18, count 0 2006.197.07:34:38.51#ibcon#read 5, iclass 18, count 0 2006.197.07:34:38.51#ibcon#about to read 6, iclass 18, count 0 2006.197.07:34:38.51#ibcon#read 6, iclass 18, count 0 2006.197.07:34:38.51#ibcon#end of sib2, iclass 18, count 0 2006.197.07:34:38.51#ibcon#*after write, iclass 18, count 0 2006.197.07:34:38.51#ibcon#*before return 0, iclass 18, count 0 2006.197.07:34:38.51#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.197.07:34:38.51#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.197.07:34:38.51#ibcon#about to clear, iclass 18 cls_cnt 0 2006.197.07:34:38.51#ibcon#cleared, iclass 18 cls_cnt 0 2006.197.07:34:38.51$vc4f8/va=4,7 2006.197.07:34:38.51#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.197.07:34:38.51#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.197.07:34:38.51#ibcon#ireg 11 cls_cnt 2 2006.197.07:34:38.51#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.197.07:34:38.57#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.197.07:34:38.57#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.197.07:34:38.57#ibcon#enter wrdev, iclass 20, count 2 2006.197.07:34:38.57#ibcon#first serial, iclass 20, count 2 2006.197.07:34:38.57#ibcon#enter sib2, iclass 20, count 2 2006.197.07:34:38.57#ibcon#flushed, iclass 20, count 2 2006.197.07:34:38.57#ibcon#about to write, iclass 20, count 2 2006.197.07:34:38.57#ibcon#wrote, iclass 20, count 2 2006.197.07:34:38.57#ibcon#about to read 3, iclass 20, count 2 2006.197.07:34:38.59#ibcon#read 3, iclass 20, count 2 2006.197.07:34:38.59#ibcon#about to read 4, iclass 20, count 2 2006.197.07:34:38.59#ibcon#read 4, iclass 20, count 2 2006.197.07:34:38.59#ibcon#about to read 5, iclass 20, count 2 2006.197.07:34:38.59#ibcon#read 5, iclass 20, count 2 2006.197.07:34:38.59#ibcon#about to read 6, iclass 20, count 2 2006.197.07:34:38.59#ibcon#read 6, iclass 20, count 2 2006.197.07:34:38.59#ibcon#end of sib2, iclass 20, count 2 2006.197.07:34:38.59#ibcon#*mode == 0, iclass 20, count 2 2006.197.07:34:38.59#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.197.07:34:38.59#ibcon#[25=AT04-07\r\n] 2006.197.07:34:38.59#ibcon#*before write, iclass 20, count 2 2006.197.07:34:38.59#ibcon#enter sib2, iclass 20, count 2 2006.197.07:34:38.59#ibcon#flushed, iclass 20, count 2 2006.197.07:34:38.59#ibcon#about to write, iclass 20, count 2 2006.197.07:34:38.59#ibcon#wrote, iclass 20, count 2 2006.197.07:34:38.59#ibcon#about to read 3, iclass 20, count 2 2006.197.07:34:38.62#ibcon#read 3, iclass 20, count 2 2006.197.07:34:38.62#ibcon#about to read 4, iclass 20, count 2 2006.197.07:34:38.62#ibcon#read 4, iclass 20, count 2 2006.197.07:34:38.62#ibcon#about to read 5, iclass 20, count 2 2006.197.07:34:38.62#ibcon#read 5, iclass 20, count 2 2006.197.07:34:38.62#ibcon#about to read 6, iclass 20, count 2 2006.197.07:34:38.62#ibcon#read 6, iclass 20, count 2 2006.197.07:34:38.62#ibcon#end of sib2, iclass 20, count 2 2006.197.07:34:38.62#ibcon#*after write, iclass 20, count 2 2006.197.07:34:38.62#ibcon#*before return 0, iclass 20, count 2 2006.197.07:34:38.62#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.197.07:34:38.62#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.197.07:34:38.62#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.197.07:34:38.62#ibcon#ireg 7 cls_cnt 0 2006.197.07:34:38.62#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.197.07:34:38.74#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.197.07:34:38.74#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.197.07:34:38.74#ibcon#enter wrdev, iclass 20, count 0 2006.197.07:34:38.74#ibcon#first serial, iclass 20, count 0 2006.197.07:34:38.74#ibcon#enter sib2, iclass 20, count 0 2006.197.07:34:38.74#ibcon#flushed, iclass 20, count 0 2006.197.07:34:38.74#ibcon#about to write, iclass 20, count 0 2006.197.07:34:38.74#ibcon#wrote, iclass 20, count 0 2006.197.07:34:38.74#ibcon#about to read 3, iclass 20, count 0 2006.197.07:34:38.76#ibcon#read 3, iclass 20, count 0 2006.197.07:34:38.76#ibcon#about to read 4, iclass 20, count 0 2006.197.07:34:38.76#ibcon#read 4, iclass 20, count 0 2006.197.07:34:38.76#ibcon#about to read 5, iclass 20, count 0 2006.197.07:34:38.76#ibcon#read 5, iclass 20, count 0 2006.197.07:34:38.76#ibcon#about to read 6, iclass 20, count 0 2006.197.07:34:38.76#ibcon#read 6, iclass 20, count 0 2006.197.07:34:38.76#ibcon#end of sib2, iclass 20, count 0 2006.197.07:34:38.76#ibcon#*mode == 0, iclass 20, count 0 2006.197.07:34:38.76#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.197.07:34:38.76#ibcon#[25=USB\r\n] 2006.197.07:34:38.76#ibcon#*before write, iclass 20, count 0 2006.197.07:34:38.76#ibcon#enter sib2, iclass 20, count 0 2006.197.07:34:38.76#ibcon#flushed, iclass 20, count 0 2006.197.07:34:38.76#ibcon#about to write, iclass 20, count 0 2006.197.07:34:38.76#ibcon#wrote, iclass 20, count 0 2006.197.07:34:38.76#ibcon#about to read 3, iclass 20, count 0 2006.197.07:34:38.79#ibcon#read 3, iclass 20, count 0 2006.197.07:34:38.79#ibcon#about to read 4, iclass 20, count 0 2006.197.07:34:38.79#ibcon#read 4, iclass 20, count 0 2006.197.07:34:38.79#ibcon#about to read 5, iclass 20, count 0 2006.197.07:34:38.79#ibcon#read 5, iclass 20, count 0 2006.197.07:34:38.79#ibcon#about to read 6, iclass 20, count 0 2006.197.07:34:38.79#ibcon#read 6, iclass 20, count 0 2006.197.07:34:38.79#ibcon#end of sib2, iclass 20, count 0 2006.197.07:34:38.79#ibcon#*after write, iclass 20, count 0 2006.197.07:34:38.79#ibcon#*before return 0, iclass 20, count 0 2006.197.07:34:38.79#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.197.07:34:38.79#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.197.07:34:38.79#ibcon#about to clear, iclass 20 cls_cnt 0 2006.197.07:34:38.79#ibcon#cleared, iclass 20 cls_cnt 0 2006.197.07:34:38.79$vc4f8/valo=5,652.99 2006.197.07:34:38.79#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.197.07:34:38.79#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.197.07:34:38.79#ibcon#ireg 17 cls_cnt 0 2006.197.07:34:38.79#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.197.07:34:38.79#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.197.07:34:38.79#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.197.07:34:38.79#ibcon#enter wrdev, iclass 22, count 0 2006.197.07:34:38.79#ibcon#first serial, iclass 22, count 0 2006.197.07:34:38.79#ibcon#enter sib2, iclass 22, count 0 2006.197.07:34:38.79#ibcon#flushed, iclass 22, count 0 2006.197.07:34:38.79#ibcon#about to write, iclass 22, count 0 2006.197.07:34:38.79#ibcon#wrote, iclass 22, count 0 2006.197.07:34:38.79#ibcon#about to read 3, iclass 22, count 0 2006.197.07:34:38.81#ibcon#read 3, iclass 22, count 0 2006.197.07:34:38.81#ibcon#about to read 4, iclass 22, count 0 2006.197.07:34:38.81#ibcon#read 4, iclass 22, count 0 2006.197.07:34:38.81#ibcon#about to read 5, iclass 22, count 0 2006.197.07:34:38.81#ibcon#read 5, iclass 22, count 0 2006.197.07:34:38.81#ibcon#about to read 6, iclass 22, count 0 2006.197.07:34:38.81#ibcon#read 6, iclass 22, count 0 2006.197.07:34:38.81#ibcon#end of sib2, iclass 22, count 0 2006.197.07:34:38.81#ibcon#*mode == 0, iclass 22, count 0 2006.197.07:34:38.81#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.197.07:34:38.81#ibcon#[26=FRQ=05,652.99\r\n] 2006.197.07:34:38.81#ibcon#*before write, iclass 22, count 0 2006.197.07:34:38.81#ibcon#enter sib2, iclass 22, count 0 2006.197.07:34:38.81#ibcon#flushed, iclass 22, count 0 2006.197.07:34:38.81#ibcon#about to write, iclass 22, count 0 2006.197.07:34:38.81#ibcon#wrote, iclass 22, count 0 2006.197.07:34:38.81#ibcon#about to read 3, iclass 22, count 0 2006.197.07:34:38.85#ibcon#read 3, iclass 22, count 0 2006.197.07:34:38.85#ibcon#about to read 4, iclass 22, count 0 2006.197.07:34:38.85#ibcon#read 4, iclass 22, count 0 2006.197.07:34:38.85#ibcon#about to read 5, iclass 22, count 0 2006.197.07:34:38.85#ibcon#read 5, iclass 22, count 0 2006.197.07:34:38.85#ibcon#about to read 6, iclass 22, count 0 2006.197.07:34:38.85#ibcon#read 6, iclass 22, count 0 2006.197.07:34:38.85#ibcon#end of sib2, iclass 22, count 0 2006.197.07:34:38.85#ibcon#*after write, iclass 22, count 0 2006.197.07:34:38.85#ibcon#*before return 0, iclass 22, count 0 2006.197.07:34:38.85#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.197.07:34:38.85#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.197.07:34:38.85#ibcon#about to clear, iclass 22 cls_cnt 0 2006.197.07:34:38.85#ibcon#cleared, iclass 22 cls_cnt 0 2006.197.07:34:38.85$vc4f8/va=5,7 2006.197.07:34:38.85#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.197.07:34:38.85#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.197.07:34:38.85#ibcon#ireg 11 cls_cnt 2 2006.197.07:34:38.85#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.197.07:34:38.91#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.197.07:34:38.91#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.197.07:34:38.91#ibcon#enter wrdev, iclass 24, count 2 2006.197.07:34:38.91#ibcon#first serial, iclass 24, count 2 2006.197.07:34:38.91#ibcon#enter sib2, iclass 24, count 2 2006.197.07:34:38.91#ibcon#flushed, iclass 24, count 2 2006.197.07:34:38.91#ibcon#about to write, iclass 24, count 2 2006.197.07:34:38.91#ibcon#wrote, iclass 24, count 2 2006.197.07:34:38.91#ibcon#about to read 3, iclass 24, count 2 2006.197.07:34:38.93#ibcon#read 3, iclass 24, count 2 2006.197.07:34:38.93#ibcon#about to read 4, iclass 24, count 2 2006.197.07:34:38.93#ibcon#read 4, iclass 24, count 2 2006.197.07:34:38.93#ibcon#about to read 5, iclass 24, count 2 2006.197.07:34:38.93#ibcon#read 5, iclass 24, count 2 2006.197.07:34:38.93#ibcon#about to read 6, iclass 24, count 2 2006.197.07:34:38.93#ibcon#read 6, iclass 24, count 2 2006.197.07:34:38.93#ibcon#end of sib2, iclass 24, count 2 2006.197.07:34:38.93#ibcon#*mode == 0, iclass 24, count 2 2006.197.07:34:38.93#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.197.07:34:38.93#ibcon#[25=AT05-07\r\n] 2006.197.07:34:38.93#ibcon#*before write, iclass 24, count 2 2006.197.07:34:38.93#ibcon#enter sib2, iclass 24, count 2 2006.197.07:34:38.93#ibcon#flushed, iclass 24, count 2 2006.197.07:34:38.93#ibcon#about to write, iclass 24, count 2 2006.197.07:34:38.93#ibcon#wrote, iclass 24, count 2 2006.197.07:34:38.93#ibcon#about to read 3, iclass 24, count 2 2006.197.07:34:38.96#ibcon#read 3, iclass 24, count 2 2006.197.07:34:38.96#ibcon#about to read 4, iclass 24, count 2 2006.197.07:34:38.96#ibcon#read 4, iclass 24, count 2 2006.197.07:34:38.96#ibcon#about to read 5, iclass 24, count 2 2006.197.07:34:38.96#ibcon#read 5, iclass 24, count 2 2006.197.07:34:38.96#ibcon#about to read 6, iclass 24, count 2 2006.197.07:34:38.96#ibcon#read 6, iclass 24, count 2 2006.197.07:34:38.96#ibcon#end of sib2, iclass 24, count 2 2006.197.07:34:38.96#ibcon#*after write, iclass 24, count 2 2006.197.07:34:38.96#ibcon#*before return 0, iclass 24, count 2 2006.197.07:34:38.96#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.197.07:34:38.96#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.197.07:34:38.96#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.197.07:34:38.96#ibcon#ireg 7 cls_cnt 0 2006.197.07:34:38.96#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.197.07:34:39.08#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.197.07:34:39.08#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.197.07:34:39.08#ibcon#enter wrdev, iclass 24, count 0 2006.197.07:34:39.08#ibcon#first serial, iclass 24, count 0 2006.197.07:34:39.08#ibcon#enter sib2, iclass 24, count 0 2006.197.07:34:39.08#ibcon#flushed, iclass 24, count 0 2006.197.07:34:39.08#ibcon#about to write, iclass 24, count 0 2006.197.07:34:39.08#ibcon#wrote, iclass 24, count 0 2006.197.07:34:39.08#ibcon#about to read 3, iclass 24, count 0 2006.197.07:34:39.10#ibcon#read 3, iclass 24, count 0 2006.197.07:34:39.10#ibcon#about to read 4, iclass 24, count 0 2006.197.07:34:39.10#ibcon#read 4, iclass 24, count 0 2006.197.07:34:39.10#ibcon#about to read 5, iclass 24, count 0 2006.197.07:34:39.10#ibcon#read 5, iclass 24, count 0 2006.197.07:34:39.10#ibcon#about to read 6, iclass 24, count 0 2006.197.07:34:39.10#ibcon#read 6, iclass 24, count 0 2006.197.07:34:39.10#ibcon#end of sib2, iclass 24, count 0 2006.197.07:34:39.10#ibcon#*mode == 0, iclass 24, count 0 2006.197.07:34:39.10#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.197.07:34:39.10#ibcon#[25=USB\r\n] 2006.197.07:34:39.10#ibcon#*before write, iclass 24, count 0 2006.197.07:34:39.10#ibcon#enter sib2, iclass 24, count 0 2006.197.07:34:39.10#ibcon#flushed, iclass 24, count 0 2006.197.07:34:39.10#ibcon#about to write, iclass 24, count 0 2006.197.07:34:39.10#ibcon#wrote, iclass 24, count 0 2006.197.07:34:39.10#ibcon#about to read 3, iclass 24, count 0 2006.197.07:34:39.13#ibcon#read 3, iclass 24, count 0 2006.197.07:34:39.13#ibcon#about to read 4, iclass 24, count 0 2006.197.07:34:39.13#ibcon#read 4, iclass 24, count 0 2006.197.07:34:39.13#ibcon#about to read 5, iclass 24, count 0 2006.197.07:34:39.13#ibcon#read 5, iclass 24, count 0 2006.197.07:34:39.13#ibcon#about to read 6, iclass 24, count 0 2006.197.07:34:39.13#ibcon#read 6, iclass 24, count 0 2006.197.07:34:39.13#ibcon#end of sib2, iclass 24, count 0 2006.197.07:34:39.13#ibcon#*after write, iclass 24, count 0 2006.197.07:34:39.13#ibcon#*before return 0, iclass 24, count 0 2006.197.07:34:39.13#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.197.07:34:39.13#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.197.07:34:39.13#ibcon#about to clear, iclass 24 cls_cnt 0 2006.197.07:34:39.13#ibcon#cleared, iclass 24 cls_cnt 0 2006.197.07:34:39.13$vc4f8/valo=6,772.99 2006.197.07:34:39.13#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.197.07:34:39.13#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.197.07:34:39.13#ibcon#ireg 17 cls_cnt 0 2006.197.07:34:39.13#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.197.07:34:39.13#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.197.07:34:39.13#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.197.07:34:39.13#ibcon#enter wrdev, iclass 26, count 0 2006.197.07:34:39.13#ibcon#first serial, iclass 26, count 0 2006.197.07:34:39.13#ibcon#enter sib2, iclass 26, count 0 2006.197.07:34:39.13#ibcon#flushed, iclass 26, count 0 2006.197.07:34:39.13#ibcon#about to write, iclass 26, count 0 2006.197.07:34:39.13#ibcon#wrote, iclass 26, count 0 2006.197.07:34:39.13#ibcon#about to read 3, iclass 26, count 0 2006.197.07:34:39.15#ibcon#read 3, iclass 26, count 0 2006.197.07:34:39.15#ibcon#about to read 4, iclass 26, count 0 2006.197.07:34:39.15#ibcon#read 4, iclass 26, count 0 2006.197.07:34:39.15#ibcon#about to read 5, iclass 26, count 0 2006.197.07:34:39.15#ibcon#read 5, iclass 26, count 0 2006.197.07:34:39.15#ibcon#about to read 6, iclass 26, count 0 2006.197.07:34:39.15#ibcon#read 6, iclass 26, count 0 2006.197.07:34:39.15#ibcon#end of sib2, iclass 26, count 0 2006.197.07:34:39.15#ibcon#*mode == 0, iclass 26, count 0 2006.197.07:34:39.15#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.197.07:34:39.15#ibcon#[26=FRQ=06,772.99\r\n] 2006.197.07:34:39.15#ibcon#*before write, iclass 26, count 0 2006.197.07:34:39.15#ibcon#enter sib2, iclass 26, count 0 2006.197.07:34:39.15#ibcon#flushed, iclass 26, count 0 2006.197.07:34:39.15#ibcon#about to write, iclass 26, count 0 2006.197.07:34:39.15#ibcon#wrote, iclass 26, count 0 2006.197.07:34:39.15#ibcon#about to read 3, iclass 26, count 0 2006.197.07:34:39.19#ibcon#read 3, iclass 26, count 0 2006.197.07:34:39.19#ibcon#about to read 4, iclass 26, count 0 2006.197.07:34:39.19#ibcon#read 4, iclass 26, count 0 2006.197.07:34:39.19#ibcon#about to read 5, iclass 26, count 0 2006.197.07:34:39.19#ibcon#read 5, iclass 26, count 0 2006.197.07:34:39.19#ibcon#about to read 6, iclass 26, count 0 2006.197.07:34:39.19#ibcon#read 6, iclass 26, count 0 2006.197.07:34:39.19#ibcon#end of sib2, iclass 26, count 0 2006.197.07:34:39.19#ibcon#*after write, iclass 26, count 0 2006.197.07:34:39.19#ibcon#*before return 0, iclass 26, count 0 2006.197.07:34:39.19#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.197.07:34:39.19#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.197.07:34:39.19#ibcon#about to clear, iclass 26 cls_cnt 0 2006.197.07:34:39.19#ibcon#cleared, iclass 26 cls_cnt 0 2006.197.07:34:39.19$vc4f8/va=6,6 2006.197.07:34:39.19#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.197.07:34:39.19#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.197.07:34:39.19#ibcon#ireg 11 cls_cnt 2 2006.197.07:34:39.19#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.197.07:34:39.25#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.197.07:34:39.25#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.197.07:34:39.25#ibcon#enter wrdev, iclass 28, count 2 2006.197.07:34:39.25#ibcon#first serial, iclass 28, count 2 2006.197.07:34:39.25#ibcon#enter sib2, iclass 28, count 2 2006.197.07:34:39.25#ibcon#flushed, iclass 28, count 2 2006.197.07:34:39.25#ibcon#about to write, iclass 28, count 2 2006.197.07:34:39.25#ibcon#wrote, iclass 28, count 2 2006.197.07:34:39.25#ibcon#about to read 3, iclass 28, count 2 2006.197.07:34:39.27#ibcon#read 3, iclass 28, count 2 2006.197.07:34:39.27#ibcon#about to read 4, iclass 28, count 2 2006.197.07:34:39.27#ibcon#read 4, iclass 28, count 2 2006.197.07:34:39.27#ibcon#about to read 5, iclass 28, count 2 2006.197.07:34:39.27#ibcon#read 5, iclass 28, count 2 2006.197.07:34:39.27#ibcon#about to read 6, iclass 28, count 2 2006.197.07:34:39.27#ibcon#read 6, iclass 28, count 2 2006.197.07:34:39.27#ibcon#end of sib2, iclass 28, count 2 2006.197.07:34:39.27#ibcon#*mode == 0, iclass 28, count 2 2006.197.07:34:39.27#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.197.07:34:39.27#ibcon#[25=AT06-06\r\n] 2006.197.07:34:39.27#ibcon#*before write, iclass 28, count 2 2006.197.07:34:39.27#ibcon#enter sib2, iclass 28, count 2 2006.197.07:34:39.27#ibcon#flushed, iclass 28, count 2 2006.197.07:34:39.27#ibcon#about to write, iclass 28, count 2 2006.197.07:34:39.27#ibcon#wrote, iclass 28, count 2 2006.197.07:34:39.27#ibcon#about to read 3, iclass 28, count 2 2006.197.07:34:39.30#ibcon#read 3, iclass 28, count 2 2006.197.07:34:39.30#ibcon#about to read 4, iclass 28, count 2 2006.197.07:34:39.30#ibcon#read 4, iclass 28, count 2 2006.197.07:34:39.30#ibcon#about to read 5, iclass 28, count 2 2006.197.07:34:39.30#ibcon#read 5, iclass 28, count 2 2006.197.07:34:39.30#ibcon#about to read 6, iclass 28, count 2 2006.197.07:34:39.30#ibcon#read 6, iclass 28, count 2 2006.197.07:34:39.30#ibcon#end of sib2, iclass 28, count 2 2006.197.07:34:39.30#ibcon#*after write, iclass 28, count 2 2006.197.07:34:39.30#ibcon#*before return 0, iclass 28, count 2 2006.197.07:34:39.30#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.197.07:34:39.30#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.197.07:34:39.30#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.197.07:34:39.30#ibcon#ireg 7 cls_cnt 0 2006.197.07:34:39.30#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.197.07:34:39.42#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.197.07:34:39.42#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.197.07:34:39.42#ibcon#enter wrdev, iclass 28, count 0 2006.197.07:34:39.42#ibcon#first serial, iclass 28, count 0 2006.197.07:34:39.42#ibcon#enter sib2, iclass 28, count 0 2006.197.07:34:39.42#ibcon#flushed, iclass 28, count 0 2006.197.07:34:39.42#ibcon#about to write, iclass 28, count 0 2006.197.07:34:39.42#ibcon#wrote, iclass 28, count 0 2006.197.07:34:39.42#ibcon#about to read 3, iclass 28, count 0 2006.197.07:34:39.44#ibcon#read 3, iclass 28, count 0 2006.197.07:34:39.44#ibcon#about to read 4, iclass 28, count 0 2006.197.07:34:39.44#ibcon#read 4, iclass 28, count 0 2006.197.07:34:39.44#ibcon#about to read 5, iclass 28, count 0 2006.197.07:34:39.44#ibcon#read 5, iclass 28, count 0 2006.197.07:34:39.44#ibcon#about to read 6, iclass 28, count 0 2006.197.07:34:39.44#ibcon#read 6, iclass 28, count 0 2006.197.07:34:39.44#ibcon#end of sib2, iclass 28, count 0 2006.197.07:34:39.44#ibcon#*mode == 0, iclass 28, count 0 2006.197.07:34:39.44#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.197.07:34:39.44#ibcon#[25=USB\r\n] 2006.197.07:34:39.44#ibcon#*before write, iclass 28, count 0 2006.197.07:34:39.44#ibcon#enter sib2, iclass 28, count 0 2006.197.07:34:39.44#ibcon#flushed, iclass 28, count 0 2006.197.07:34:39.44#ibcon#about to write, iclass 28, count 0 2006.197.07:34:39.44#ibcon#wrote, iclass 28, count 0 2006.197.07:34:39.44#ibcon#about to read 3, iclass 28, count 0 2006.197.07:34:39.47#ibcon#read 3, iclass 28, count 0 2006.197.07:34:39.47#ibcon#about to read 4, iclass 28, count 0 2006.197.07:34:39.47#ibcon#read 4, iclass 28, count 0 2006.197.07:34:39.47#ibcon#about to read 5, iclass 28, count 0 2006.197.07:34:39.47#ibcon#read 5, iclass 28, count 0 2006.197.07:34:39.47#ibcon#about to read 6, iclass 28, count 0 2006.197.07:34:39.47#ibcon#read 6, iclass 28, count 0 2006.197.07:34:39.47#ibcon#end of sib2, iclass 28, count 0 2006.197.07:34:39.47#ibcon#*after write, iclass 28, count 0 2006.197.07:34:39.47#ibcon#*before return 0, iclass 28, count 0 2006.197.07:34:39.47#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.197.07:34:39.47#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.197.07:34:39.47#ibcon#about to clear, iclass 28 cls_cnt 0 2006.197.07:34:39.47#ibcon#cleared, iclass 28 cls_cnt 0 2006.197.07:34:39.47$vc4f8/valo=7,832.99 2006.197.07:34:39.47#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.197.07:34:39.47#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.197.07:34:39.47#ibcon#ireg 17 cls_cnt 0 2006.197.07:34:39.47#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.197.07:34:39.47#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.197.07:34:39.47#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.197.07:34:39.47#ibcon#enter wrdev, iclass 30, count 0 2006.197.07:34:39.47#ibcon#first serial, iclass 30, count 0 2006.197.07:34:39.47#ibcon#enter sib2, iclass 30, count 0 2006.197.07:34:39.47#ibcon#flushed, iclass 30, count 0 2006.197.07:34:39.47#ibcon#about to write, iclass 30, count 0 2006.197.07:34:39.47#ibcon#wrote, iclass 30, count 0 2006.197.07:34:39.47#ibcon#about to read 3, iclass 30, count 0 2006.197.07:34:39.49#ibcon#read 3, iclass 30, count 0 2006.197.07:34:39.49#ibcon#about to read 4, iclass 30, count 0 2006.197.07:34:39.49#ibcon#read 4, iclass 30, count 0 2006.197.07:34:39.49#ibcon#about to read 5, iclass 30, count 0 2006.197.07:34:39.49#ibcon#read 5, iclass 30, count 0 2006.197.07:34:39.49#ibcon#about to read 6, iclass 30, count 0 2006.197.07:34:39.49#ibcon#read 6, iclass 30, count 0 2006.197.07:34:39.49#ibcon#end of sib2, iclass 30, count 0 2006.197.07:34:39.49#ibcon#*mode == 0, iclass 30, count 0 2006.197.07:34:39.49#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.197.07:34:39.49#ibcon#[26=FRQ=07,832.99\r\n] 2006.197.07:34:39.49#ibcon#*before write, iclass 30, count 0 2006.197.07:34:39.49#ibcon#enter sib2, iclass 30, count 0 2006.197.07:34:39.49#ibcon#flushed, iclass 30, count 0 2006.197.07:34:39.49#ibcon#about to write, iclass 30, count 0 2006.197.07:34:39.49#ibcon#wrote, iclass 30, count 0 2006.197.07:34:39.49#ibcon#about to read 3, iclass 30, count 0 2006.197.07:34:39.53#ibcon#read 3, iclass 30, count 0 2006.197.07:34:39.53#ibcon#about to read 4, iclass 30, count 0 2006.197.07:34:39.53#ibcon#read 4, iclass 30, count 0 2006.197.07:34:39.53#ibcon#about to read 5, iclass 30, count 0 2006.197.07:34:39.53#ibcon#read 5, iclass 30, count 0 2006.197.07:34:39.53#ibcon#about to read 6, iclass 30, count 0 2006.197.07:34:39.53#ibcon#read 6, iclass 30, count 0 2006.197.07:34:39.53#ibcon#end of sib2, iclass 30, count 0 2006.197.07:34:39.53#ibcon#*after write, iclass 30, count 0 2006.197.07:34:39.53#ibcon#*before return 0, iclass 30, count 0 2006.197.07:34:39.53#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.197.07:34:39.53#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.197.07:34:39.53#ibcon#about to clear, iclass 30 cls_cnt 0 2006.197.07:34:39.53#ibcon#cleared, iclass 30 cls_cnt 0 2006.197.07:34:39.53$vc4f8/va=7,6 2006.197.07:34:39.53#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.197.07:34:39.53#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.197.07:34:39.53#ibcon#ireg 11 cls_cnt 2 2006.197.07:34:39.53#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.197.07:34:39.59#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.197.07:34:39.59#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.197.07:34:39.59#ibcon#enter wrdev, iclass 32, count 2 2006.197.07:34:39.59#ibcon#first serial, iclass 32, count 2 2006.197.07:34:39.59#ibcon#enter sib2, iclass 32, count 2 2006.197.07:34:39.59#ibcon#flushed, iclass 32, count 2 2006.197.07:34:39.59#ibcon#about to write, iclass 32, count 2 2006.197.07:34:39.59#ibcon#wrote, iclass 32, count 2 2006.197.07:34:39.59#ibcon#about to read 3, iclass 32, count 2 2006.197.07:34:39.61#ibcon#read 3, iclass 32, count 2 2006.197.07:34:39.61#ibcon#about to read 4, iclass 32, count 2 2006.197.07:34:39.61#ibcon#read 4, iclass 32, count 2 2006.197.07:34:39.61#ibcon#about to read 5, iclass 32, count 2 2006.197.07:34:39.61#ibcon#read 5, iclass 32, count 2 2006.197.07:34:39.61#ibcon#about to read 6, iclass 32, count 2 2006.197.07:34:39.61#ibcon#read 6, iclass 32, count 2 2006.197.07:34:39.61#ibcon#end of sib2, iclass 32, count 2 2006.197.07:34:39.61#ibcon#*mode == 0, iclass 32, count 2 2006.197.07:34:39.61#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.197.07:34:39.61#ibcon#[25=AT07-06\r\n] 2006.197.07:34:39.61#ibcon#*before write, iclass 32, count 2 2006.197.07:34:39.61#ibcon#enter sib2, iclass 32, count 2 2006.197.07:34:39.61#ibcon#flushed, iclass 32, count 2 2006.197.07:34:39.61#ibcon#about to write, iclass 32, count 2 2006.197.07:34:39.61#ibcon#wrote, iclass 32, count 2 2006.197.07:34:39.61#ibcon#about to read 3, iclass 32, count 2 2006.197.07:34:39.64#ibcon#read 3, iclass 32, count 2 2006.197.07:34:39.64#ibcon#about to read 4, iclass 32, count 2 2006.197.07:34:39.64#ibcon#read 4, iclass 32, count 2 2006.197.07:34:39.64#ibcon#about to read 5, iclass 32, count 2 2006.197.07:34:39.64#ibcon#read 5, iclass 32, count 2 2006.197.07:34:39.64#ibcon#about to read 6, iclass 32, count 2 2006.197.07:34:39.64#ibcon#read 6, iclass 32, count 2 2006.197.07:34:39.64#ibcon#end of sib2, iclass 32, count 2 2006.197.07:34:39.64#ibcon#*after write, iclass 32, count 2 2006.197.07:34:39.64#ibcon#*before return 0, iclass 32, count 2 2006.197.07:34:39.64#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.197.07:34:39.64#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.197.07:34:39.64#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.197.07:34:39.64#ibcon#ireg 7 cls_cnt 0 2006.197.07:34:39.64#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.197.07:34:39.76#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.197.07:34:39.76#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.197.07:34:39.76#ibcon#enter wrdev, iclass 32, count 0 2006.197.07:34:39.76#ibcon#first serial, iclass 32, count 0 2006.197.07:34:39.76#ibcon#enter sib2, iclass 32, count 0 2006.197.07:34:39.76#ibcon#flushed, iclass 32, count 0 2006.197.07:34:39.76#ibcon#about to write, iclass 32, count 0 2006.197.07:34:39.76#ibcon#wrote, iclass 32, count 0 2006.197.07:34:39.76#ibcon#about to read 3, iclass 32, count 0 2006.197.07:34:39.78#ibcon#read 3, iclass 32, count 0 2006.197.07:34:39.78#ibcon#about to read 4, iclass 32, count 0 2006.197.07:34:39.78#ibcon#read 4, iclass 32, count 0 2006.197.07:34:39.78#ibcon#about to read 5, iclass 32, count 0 2006.197.07:34:39.78#ibcon#read 5, iclass 32, count 0 2006.197.07:34:39.78#ibcon#about to read 6, iclass 32, count 0 2006.197.07:34:39.78#ibcon#read 6, iclass 32, count 0 2006.197.07:34:39.78#ibcon#end of sib2, iclass 32, count 0 2006.197.07:34:39.78#ibcon#*mode == 0, iclass 32, count 0 2006.197.07:34:39.78#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.197.07:34:39.78#ibcon#[25=USB\r\n] 2006.197.07:34:39.78#ibcon#*before write, iclass 32, count 0 2006.197.07:34:39.78#ibcon#enter sib2, iclass 32, count 0 2006.197.07:34:39.78#ibcon#flushed, iclass 32, count 0 2006.197.07:34:39.78#ibcon#about to write, iclass 32, count 0 2006.197.07:34:39.78#ibcon#wrote, iclass 32, count 0 2006.197.07:34:39.78#ibcon#about to read 3, iclass 32, count 0 2006.197.07:34:39.81#ibcon#read 3, iclass 32, count 0 2006.197.07:34:39.81#ibcon#about to read 4, iclass 32, count 0 2006.197.07:34:39.81#ibcon#read 4, iclass 32, count 0 2006.197.07:34:39.81#ibcon#about to read 5, iclass 32, count 0 2006.197.07:34:39.81#ibcon#read 5, iclass 32, count 0 2006.197.07:34:39.81#ibcon#about to read 6, iclass 32, count 0 2006.197.07:34:39.81#ibcon#read 6, iclass 32, count 0 2006.197.07:34:39.81#ibcon#end of sib2, iclass 32, count 0 2006.197.07:34:39.81#ibcon#*after write, iclass 32, count 0 2006.197.07:34:39.81#ibcon#*before return 0, iclass 32, count 0 2006.197.07:34:39.81#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.197.07:34:39.81#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.197.07:34:39.81#ibcon#about to clear, iclass 32 cls_cnt 0 2006.197.07:34:39.81#ibcon#cleared, iclass 32 cls_cnt 0 2006.197.07:34:39.81$vc4f8/valo=8,852.99 2006.197.07:34:39.81#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.197.07:34:39.81#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.197.07:34:39.81#ibcon#ireg 17 cls_cnt 0 2006.197.07:34:39.81#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.197.07:34:39.81#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.197.07:34:39.81#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.197.07:34:39.81#ibcon#enter wrdev, iclass 34, count 0 2006.197.07:34:39.81#ibcon#first serial, iclass 34, count 0 2006.197.07:34:39.81#ibcon#enter sib2, iclass 34, count 0 2006.197.07:34:39.81#ibcon#flushed, iclass 34, count 0 2006.197.07:34:39.81#ibcon#about to write, iclass 34, count 0 2006.197.07:34:39.81#ibcon#wrote, iclass 34, count 0 2006.197.07:34:39.81#ibcon#about to read 3, iclass 34, count 0 2006.197.07:34:39.83#ibcon#read 3, iclass 34, count 0 2006.197.07:34:39.83#ibcon#about to read 4, iclass 34, count 0 2006.197.07:34:39.83#ibcon#read 4, iclass 34, count 0 2006.197.07:34:39.83#ibcon#about to read 5, iclass 34, count 0 2006.197.07:34:39.83#ibcon#read 5, iclass 34, count 0 2006.197.07:34:39.83#ibcon#about to read 6, iclass 34, count 0 2006.197.07:34:39.83#ibcon#read 6, iclass 34, count 0 2006.197.07:34:39.83#ibcon#end of sib2, iclass 34, count 0 2006.197.07:34:39.83#ibcon#*mode == 0, iclass 34, count 0 2006.197.07:34:39.83#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.197.07:34:39.83#ibcon#[26=FRQ=08,852.99\r\n] 2006.197.07:34:39.83#ibcon#*before write, iclass 34, count 0 2006.197.07:34:39.83#ibcon#enter sib2, iclass 34, count 0 2006.197.07:34:39.83#ibcon#flushed, iclass 34, count 0 2006.197.07:34:39.83#ibcon#about to write, iclass 34, count 0 2006.197.07:34:39.83#ibcon#wrote, iclass 34, count 0 2006.197.07:34:39.83#ibcon#about to read 3, iclass 34, count 0 2006.197.07:34:39.87#ibcon#read 3, iclass 34, count 0 2006.197.07:34:39.87#ibcon#about to read 4, iclass 34, count 0 2006.197.07:34:39.87#ibcon#read 4, iclass 34, count 0 2006.197.07:34:39.87#ibcon#about to read 5, iclass 34, count 0 2006.197.07:34:39.87#ibcon#read 5, iclass 34, count 0 2006.197.07:34:39.87#ibcon#about to read 6, iclass 34, count 0 2006.197.07:34:39.87#ibcon#read 6, iclass 34, count 0 2006.197.07:34:39.87#ibcon#end of sib2, iclass 34, count 0 2006.197.07:34:39.87#ibcon#*after write, iclass 34, count 0 2006.197.07:34:39.87#ibcon#*before return 0, iclass 34, count 0 2006.197.07:34:39.87#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.197.07:34:39.87#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.197.07:34:39.87#ibcon#about to clear, iclass 34 cls_cnt 0 2006.197.07:34:39.87#ibcon#cleared, iclass 34 cls_cnt 0 2006.197.07:34:39.87$vc4f8/va=8,7 2006.197.07:34:39.87#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.197.07:34:39.87#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.197.07:34:39.87#ibcon#ireg 11 cls_cnt 2 2006.197.07:34:39.87#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.197.07:34:39.93#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.197.07:34:39.93#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.197.07:34:39.93#ibcon#enter wrdev, iclass 36, count 2 2006.197.07:34:39.93#ibcon#first serial, iclass 36, count 2 2006.197.07:34:39.93#ibcon#enter sib2, iclass 36, count 2 2006.197.07:34:39.93#ibcon#flushed, iclass 36, count 2 2006.197.07:34:39.93#ibcon#about to write, iclass 36, count 2 2006.197.07:34:39.93#ibcon#wrote, iclass 36, count 2 2006.197.07:34:39.93#ibcon#about to read 3, iclass 36, count 2 2006.197.07:34:39.95#ibcon#read 3, iclass 36, count 2 2006.197.07:34:39.95#ibcon#about to read 4, iclass 36, count 2 2006.197.07:34:39.95#ibcon#read 4, iclass 36, count 2 2006.197.07:34:39.95#ibcon#about to read 5, iclass 36, count 2 2006.197.07:34:39.95#ibcon#read 5, iclass 36, count 2 2006.197.07:34:39.95#ibcon#about to read 6, iclass 36, count 2 2006.197.07:34:39.95#ibcon#read 6, iclass 36, count 2 2006.197.07:34:39.95#ibcon#end of sib2, iclass 36, count 2 2006.197.07:34:39.95#ibcon#*mode == 0, iclass 36, count 2 2006.197.07:34:39.95#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.197.07:34:39.95#ibcon#[25=AT08-07\r\n] 2006.197.07:34:39.95#ibcon#*before write, iclass 36, count 2 2006.197.07:34:39.95#ibcon#enter sib2, iclass 36, count 2 2006.197.07:34:39.95#ibcon#flushed, iclass 36, count 2 2006.197.07:34:39.95#ibcon#about to write, iclass 36, count 2 2006.197.07:34:39.95#ibcon#wrote, iclass 36, count 2 2006.197.07:34:39.95#ibcon#about to read 3, iclass 36, count 2 2006.197.07:34:39.98#ibcon#read 3, iclass 36, count 2 2006.197.07:34:39.98#ibcon#about to read 4, iclass 36, count 2 2006.197.07:34:39.98#ibcon#read 4, iclass 36, count 2 2006.197.07:34:39.98#ibcon#about to read 5, iclass 36, count 2 2006.197.07:34:39.98#ibcon#read 5, iclass 36, count 2 2006.197.07:34:39.98#ibcon#about to read 6, iclass 36, count 2 2006.197.07:34:39.98#ibcon#read 6, iclass 36, count 2 2006.197.07:34:39.98#ibcon#end of sib2, iclass 36, count 2 2006.197.07:34:39.98#ibcon#*after write, iclass 36, count 2 2006.197.07:34:39.98#ibcon#*before return 0, iclass 36, count 2 2006.197.07:34:39.98#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.197.07:34:39.98#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.197.07:34:39.98#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.197.07:34:39.98#ibcon#ireg 7 cls_cnt 0 2006.197.07:34:39.98#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.197.07:34:40.10#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.197.07:34:40.10#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.197.07:34:40.10#ibcon#enter wrdev, iclass 36, count 0 2006.197.07:34:40.10#ibcon#first serial, iclass 36, count 0 2006.197.07:34:40.10#ibcon#enter sib2, iclass 36, count 0 2006.197.07:34:40.10#ibcon#flushed, iclass 36, count 0 2006.197.07:34:40.10#ibcon#about to write, iclass 36, count 0 2006.197.07:34:40.10#ibcon#wrote, iclass 36, count 0 2006.197.07:34:40.10#ibcon#about to read 3, iclass 36, count 0 2006.197.07:34:40.12#ibcon#read 3, iclass 36, count 0 2006.197.07:34:40.12#ibcon#about to read 4, iclass 36, count 0 2006.197.07:34:40.12#ibcon#read 4, iclass 36, count 0 2006.197.07:34:40.12#ibcon#about to read 5, iclass 36, count 0 2006.197.07:34:40.12#ibcon#read 5, iclass 36, count 0 2006.197.07:34:40.12#ibcon#about to read 6, iclass 36, count 0 2006.197.07:34:40.12#ibcon#read 6, iclass 36, count 0 2006.197.07:34:40.12#ibcon#end of sib2, iclass 36, count 0 2006.197.07:34:40.12#ibcon#*mode == 0, iclass 36, count 0 2006.197.07:34:40.12#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.197.07:34:40.12#ibcon#[25=USB\r\n] 2006.197.07:34:40.12#ibcon#*before write, iclass 36, count 0 2006.197.07:34:40.12#ibcon#enter sib2, iclass 36, count 0 2006.197.07:34:40.12#ibcon#flushed, iclass 36, count 0 2006.197.07:34:40.12#ibcon#about to write, iclass 36, count 0 2006.197.07:34:40.12#ibcon#wrote, iclass 36, count 0 2006.197.07:34:40.12#ibcon#about to read 3, iclass 36, count 0 2006.197.07:34:40.15#ibcon#read 3, iclass 36, count 0 2006.197.07:34:40.15#ibcon#about to read 4, iclass 36, count 0 2006.197.07:34:40.15#ibcon#read 4, iclass 36, count 0 2006.197.07:34:40.15#ibcon#about to read 5, iclass 36, count 0 2006.197.07:34:40.15#ibcon#read 5, iclass 36, count 0 2006.197.07:34:40.15#ibcon#about to read 6, iclass 36, count 0 2006.197.07:34:40.15#ibcon#read 6, iclass 36, count 0 2006.197.07:34:40.15#ibcon#end of sib2, iclass 36, count 0 2006.197.07:34:40.15#ibcon#*after write, iclass 36, count 0 2006.197.07:34:40.15#ibcon#*before return 0, iclass 36, count 0 2006.197.07:34:40.15#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.197.07:34:40.15#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.197.07:34:40.15#ibcon#about to clear, iclass 36 cls_cnt 0 2006.197.07:34:40.15#ibcon#cleared, iclass 36 cls_cnt 0 2006.197.07:34:40.15$vc4f8/vblo=1,632.99 2006.197.07:34:40.15#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.197.07:34:40.15#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.197.07:34:40.15#ibcon#ireg 17 cls_cnt 0 2006.197.07:34:40.15#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.197.07:34:40.15#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.197.07:34:40.15#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.197.07:34:40.15#ibcon#enter wrdev, iclass 38, count 0 2006.197.07:34:40.15#ibcon#first serial, iclass 38, count 0 2006.197.07:34:40.15#ibcon#enter sib2, iclass 38, count 0 2006.197.07:34:40.15#ibcon#flushed, iclass 38, count 0 2006.197.07:34:40.15#ibcon#about to write, iclass 38, count 0 2006.197.07:34:40.15#ibcon#wrote, iclass 38, count 0 2006.197.07:34:40.15#ibcon#about to read 3, iclass 38, count 0 2006.197.07:34:40.17#ibcon#read 3, iclass 38, count 0 2006.197.07:34:40.17#ibcon#about to read 4, iclass 38, count 0 2006.197.07:34:40.17#ibcon#read 4, iclass 38, count 0 2006.197.07:34:40.17#ibcon#about to read 5, iclass 38, count 0 2006.197.07:34:40.17#ibcon#read 5, iclass 38, count 0 2006.197.07:34:40.17#ibcon#about to read 6, iclass 38, count 0 2006.197.07:34:40.17#ibcon#read 6, iclass 38, count 0 2006.197.07:34:40.17#ibcon#end of sib2, iclass 38, count 0 2006.197.07:34:40.17#ibcon#*mode == 0, iclass 38, count 0 2006.197.07:34:40.17#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.197.07:34:40.17#ibcon#[28=FRQ=01,632.99\r\n] 2006.197.07:34:40.17#ibcon#*before write, iclass 38, count 0 2006.197.07:34:40.17#ibcon#enter sib2, iclass 38, count 0 2006.197.07:34:40.17#ibcon#flushed, iclass 38, count 0 2006.197.07:34:40.17#ibcon#about to write, iclass 38, count 0 2006.197.07:34:40.17#ibcon#wrote, iclass 38, count 0 2006.197.07:34:40.17#ibcon#about to read 3, iclass 38, count 0 2006.197.07:34:40.21#ibcon#read 3, iclass 38, count 0 2006.197.07:34:40.21#ibcon#about to read 4, iclass 38, count 0 2006.197.07:34:40.21#ibcon#read 4, iclass 38, count 0 2006.197.07:34:40.21#ibcon#about to read 5, iclass 38, count 0 2006.197.07:34:40.21#ibcon#read 5, iclass 38, count 0 2006.197.07:34:40.21#ibcon#about to read 6, iclass 38, count 0 2006.197.07:34:40.21#ibcon#read 6, iclass 38, count 0 2006.197.07:34:40.21#ibcon#end of sib2, iclass 38, count 0 2006.197.07:34:40.21#ibcon#*after write, iclass 38, count 0 2006.197.07:34:40.21#ibcon#*before return 0, iclass 38, count 0 2006.197.07:34:40.21#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.197.07:34:40.21#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.197.07:34:40.21#ibcon#about to clear, iclass 38 cls_cnt 0 2006.197.07:34:40.21#ibcon#cleared, iclass 38 cls_cnt 0 2006.197.07:34:40.21$vc4f8/vb=1,4 2006.197.07:34:40.21#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.197.07:34:40.21#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.197.07:34:40.21#ibcon#ireg 11 cls_cnt 2 2006.197.07:34:40.21#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.197.07:34:40.21#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.197.07:34:40.21#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.197.07:34:40.21#ibcon#enter wrdev, iclass 40, count 2 2006.197.07:34:40.21#ibcon#first serial, iclass 40, count 2 2006.197.07:34:40.21#ibcon#enter sib2, iclass 40, count 2 2006.197.07:34:40.21#ibcon#flushed, iclass 40, count 2 2006.197.07:34:40.21#ibcon#about to write, iclass 40, count 2 2006.197.07:34:40.21#ibcon#wrote, iclass 40, count 2 2006.197.07:34:40.21#ibcon#about to read 3, iclass 40, count 2 2006.197.07:34:40.23#ibcon#read 3, iclass 40, count 2 2006.197.07:34:40.23#ibcon#about to read 4, iclass 40, count 2 2006.197.07:34:40.23#ibcon#read 4, iclass 40, count 2 2006.197.07:34:40.23#ibcon#about to read 5, iclass 40, count 2 2006.197.07:34:40.23#ibcon#read 5, iclass 40, count 2 2006.197.07:34:40.23#ibcon#about to read 6, iclass 40, count 2 2006.197.07:34:40.23#ibcon#read 6, iclass 40, count 2 2006.197.07:34:40.23#ibcon#end of sib2, iclass 40, count 2 2006.197.07:34:40.23#ibcon#*mode == 0, iclass 40, count 2 2006.197.07:34:40.23#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.197.07:34:40.23#ibcon#[27=AT01-04\r\n] 2006.197.07:34:40.23#ibcon#*before write, iclass 40, count 2 2006.197.07:34:40.23#ibcon#enter sib2, iclass 40, count 2 2006.197.07:34:40.23#ibcon#flushed, iclass 40, count 2 2006.197.07:34:40.23#ibcon#about to write, iclass 40, count 2 2006.197.07:34:40.23#ibcon#wrote, iclass 40, count 2 2006.197.07:34:40.23#ibcon#about to read 3, iclass 40, count 2 2006.197.07:34:40.26#ibcon#read 3, iclass 40, count 2 2006.197.07:34:40.26#ibcon#about to read 4, iclass 40, count 2 2006.197.07:34:40.26#ibcon#read 4, iclass 40, count 2 2006.197.07:34:40.26#ibcon#about to read 5, iclass 40, count 2 2006.197.07:34:40.26#ibcon#read 5, iclass 40, count 2 2006.197.07:34:40.26#ibcon#about to read 6, iclass 40, count 2 2006.197.07:34:40.26#ibcon#read 6, iclass 40, count 2 2006.197.07:34:40.26#ibcon#end of sib2, iclass 40, count 2 2006.197.07:34:40.26#ibcon#*after write, iclass 40, count 2 2006.197.07:34:40.26#ibcon#*before return 0, iclass 40, count 2 2006.197.07:34:40.26#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.197.07:34:40.26#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.197.07:34:40.26#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.197.07:34:40.26#ibcon#ireg 7 cls_cnt 0 2006.197.07:34:40.26#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.197.07:34:40.38#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.197.07:34:40.38#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.197.07:34:40.38#ibcon#enter wrdev, iclass 40, count 0 2006.197.07:34:40.38#ibcon#first serial, iclass 40, count 0 2006.197.07:34:40.38#ibcon#enter sib2, iclass 40, count 0 2006.197.07:34:40.38#ibcon#flushed, iclass 40, count 0 2006.197.07:34:40.38#ibcon#about to write, iclass 40, count 0 2006.197.07:34:40.38#ibcon#wrote, iclass 40, count 0 2006.197.07:34:40.38#ibcon#about to read 3, iclass 40, count 0 2006.197.07:34:40.40#ibcon#read 3, iclass 40, count 0 2006.197.07:34:40.40#ibcon#about to read 4, iclass 40, count 0 2006.197.07:34:40.40#ibcon#read 4, iclass 40, count 0 2006.197.07:34:40.40#ibcon#about to read 5, iclass 40, count 0 2006.197.07:34:40.40#ibcon#read 5, iclass 40, count 0 2006.197.07:34:40.40#ibcon#about to read 6, iclass 40, count 0 2006.197.07:34:40.40#ibcon#read 6, iclass 40, count 0 2006.197.07:34:40.40#ibcon#end of sib2, iclass 40, count 0 2006.197.07:34:40.40#ibcon#*mode == 0, iclass 40, count 0 2006.197.07:34:40.40#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.197.07:34:40.40#ibcon#[27=USB\r\n] 2006.197.07:34:40.40#ibcon#*before write, iclass 40, count 0 2006.197.07:34:40.40#ibcon#enter sib2, iclass 40, count 0 2006.197.07:34:40.40#ibcon#flushed, iclass 40, count 0 2006.197.07:34:40.40#ibcon#about to write, iclass 40, count 0 2006.197.07:34:40.40#ibcon#wrote, iclass 40, count 0 2006.197.07:34:40.40#ibcon#about to read 3, iclass 40, count 0 2006.197.07:34:40.43#ibcon#read 3, iclass 40, count 0 2006.197.07:34:40.43#ibcon#about to read 4, iclass 40, count 0 2006.197.07:34:40.43#ibcon#read 4, iclass 40, count 0 2006.197.07:34:40.43#ibcon#about to read 5, iclass 40, count 0 2006.197.07:34:40.43#ibcon#read 5, iclass 40, count 0 2006.197.07:34:40.43#ibcon#about to read 6, iclass 40, count 0 2006.197.07:34:40.43#ibcon#read 6, iclass 40, count 0 2006.197.07:34:40.43#ibcon#end of sib2, iclass 40, count 0 2006.197.07:34:40.43#ibcon#*after write, iclass 40, count 0 2006.197.07:34:40.43#ibcon#*before return 0, iclass 40, count 0 2006.197.07:34:40.43#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.197.07:34:40.43#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.197.07:34:40.43#ibcon#about to clear, iclass 40 cls_cnt 0 2006.197.07:34:40.43#ibcon#cleared, iclass 40 cls_cnt 0 2006.197.07:34:40.43$vc4f8/vblo=2,640.99 2006.197.07:34:40.43#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.197.07:34:40.43#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.197.07:34:40.43#ibcon#ireg 17 cls_cnt 0 2006.197.07:34:40.43#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.197.07:34:40.43#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.197.07:34:40.43#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.197.07:34:40.43#ibcon#enter wrdev, iclass 4, count 0 2006.197.07:34:40.43#ibcon#first serial, iclass 4, count 0 2006.197.07:34:40.43#ibcon#enter sib2, iclass 4, count 0 2006.197.07:34:40.43#ibcon#flushed, iclass 4, count 0 2006.197.07:34:40.43#ibcon#about to write, iclass 4, count 0 2006.197.07:34:40.43#ibcon#wrote, iclass 4, count 0 2006.197.07:34:40.43#ibcon#about to read 3, iclass 4, count 0 2006.197.07:34:40.45#ibcon#read 3, iclass 4, count 0 2006.197.07:34:40.45#ibcon#about to read 4, iclass 4, count 0 2006.197.07:34:40.45#ibcon#read 4, iclass 4, count 0 2006.197.07:34:40.45#ibcon#about to read 5, iclass 4, count 0 2006.197.07:34:40.45#ibcon#read 5, iclass 4, count 0 2006.197.07:34:40.45#ibcon#about to read 6, iclass 4, count 0 2006.197.07:34:40.45#ibcon#read 6, iclass 4, count 0 2006.197.07:34:40.45#ibcon#end of sib2, iclass 4, count 0 2006.197.07:34:40.45#ibcon#*mode == 0, iclass 4, count 0 2006.197.07:34:40.45#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.197.07:34:40.45#ibcon#[28=FRQ=02,640.99\r\n] 2006.197.07:34:40.45#ibcon#*before write, iclass 4, count 0 2006.197.07:34:40.45#ibcon#enter sib2, iclass 4, count 0 2006.197.07:34:40.45#ibcon#flushed, iclass 4, count 0 2006.197.07:34:40.45#ibcon#about to write, iclass 4, count 0 2006.197.07:34:40.45#ibcon#wrote, iclass 4, count 0 2006.197.07:34:40.45#ibcon#about to read 3, iclass 4, count 0 2006.197.07:34:40.49#ibcon#read 3, iclass 4, count 0 2006.197.07:34:40.49#ibcon#about to read 4, iclass 4, count 0 2006.197.07:34:40.49#ibcon#read 4, iclass 4, count 0 2006.197.07:34:40.49#ibcon#about to read 5, iclass 4, count 0 2006.197.07:34:40.49#ibcon#read 5, iclass 4, count 0 2006.197.07:34:40.49#ibcon#about to read 6, iclass 4, count 0 2006.197.07:34:40.49#ibcon#read 6, iclass 4, count 0 2006.197.07:34:40.49#ibcon#end of sib2, iclass 4, count 0 2006.197.07:34:40.49#ibcon#*after write, iclass 4, count 0 2006.197.07:34:40.49#ibcon#*before return 0, iclass 4, count 0 2006.197.07:34:40.49#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.197.07:34:40.49#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.197.07:34:40.49#ibcon#about to clear, iclass 4 cls_cnt 0 2006.197.07:34:40.49#ibcon#cleared, iclass 4 cls_cnt 0 2006.197.07:34:40.49$vc4f8/vb=2,4 2006.197.07:34:40.49#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.197.07:34:40.49#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.197.07:34:40.49#ibcon#ireg 11 cls_cnt 2 2006.197.07:34:40.49#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.197.07:34:40.55#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.197.07:34:40.55#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.197.07:34:40.55#ibcon#enter wrdev, iclass 6, count 2 2006.197.07:34:40.55#ibcon#first serial, iclass 6, count 2 2006.197.07:34:40.55#ibcon#enter sib2, iclass 6, count 2 2006.197.07:34:40.55#ibcon#flushed, iclass 6, count 2 2006.197.07:34:40.55#ibcon#about to write, iclass 6, count 2 2006.197.07:34:40.55#ibcon#wrote, iclass 6, count 2 2006.197.07:34:40.55#ibcon#about to read 3, iclass 6, count 2 2006.197.07:34:40.57#ibcon#read 3, iclass 6, count 2 2006.197.07:34:40.57#ibcon#about to read 4, iclass 6, count 2 2006.197.07:34:40.57#ibcon#read 4, iclass 6, count 2 2006.197.07:34:40.57#ibcon#about to read 5, iclass 6, count 2 2006.197.07:34:40.57#ibcon#read 5, iclass 6, count 2 2006.197.07:34:40.57#ibcon#about to read 6, iclass 6, count 2 2006.197.07:34:40.57#ibcon#read 6, iclass 6, count 2 2006.197.07:34:40.57#ibcon#end of sib2, iclass 6, count 2 2006.197.07:34:40.57#ibcon#*mode == 0, iclass 6, count 2 2006.197.07:34:40.57#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.197.07:34:40.57#ibcon#[27=AT02-04\r\n] 2006.197.07:34:40.57#ibcon#*before write, iclass 6, count 2 2006.197.07:34:40.57#ibcon#enter sib2, iclass 6, count 2 2006.197.07:34:40.57#ibcon#flushed, iclass 6, count 2 2006.197.07:34:40.57#ibcon#about to write, iclass 6, count 2 2006.197.07:34:40.57#ibcon#wrote, iclass 6, count 2 2006.197.07:34:40.57#ibcon#about to read 3, iclass 6, count 2 2006.197.07:34:40.60#ibcon#read 3, iclass 6, count 2 2006.197.07:34:40.60#ibcon#about to read 4, iclass 6, count 2 2006.197.07:34:40.60#ibcon#read 4, iclass 6, count 2 2006.197.07:34:40.60#ibcon#about to read 5, iclass 6, count 2 2006.197.07:34:40.60#ibcon#read 5, iclass 6, count 2 2006.197.07:34:40.60#ibcon#about to read 6, iclass 6, count 2 2006.197.07:34:40.60#ibcon#read 6, iclass 6, count 2 2006.197.07:34:40.60#ibcon#end of sib2, iclass 6, count 2 2006.197.07:34:40.60#ibcon#*after write, iclass 6, count 2 2006.197.07:34:40.60#ibcon#*before return 0, iclass 6, count 2 2006.197.07:34:40.60#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.197.07:34:40.60#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.197.07:34:40.60#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.197.07:34:40.60#ibcon#ireg 7 cls_cnt 0 2006.197.07:34:40.60#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.197.07:34:40.72#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.197.07:34:40.72#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.197.07:34:40.72#ibcon#enter wrdev, iclass 6, count 0 2006.197.07:34:40.72#ibcon#first serial, iclass 6, count 0 2006.197.07:34:40.72#ibcon#enter sib2, iclass 6, count 0 2006.197.07:34:40.72#ibcon#flushed, iclass 6, count 0 2006.197.07:34:40.72#ibcon#about to write, iclass 6, count 0 2006.197.07:34:40.72#ibcon#wrote, iclass 6, count 0 2006.197.07:34:40.72#ibcon#about to read 3, iclass 6, count 0 2006.197.07:34:40.74#ibcon#read 3, iclass 6, count 0 2006.197.07:34:40.74#ibcon#about to read 4, iclass 6, count 0 2006.197.07:34:40.74#ibcon#read 4, iclass 6, count 0 2006.197.07:34:40.74#ibcon#about to read 5, iclass 6, count 0 2006.197.07:34:40.74#ibcon#read 5, iclass 6, count 0 2006.197.07:34:40.74#ibcon#about to read 6, iclass 6, count 0 2006.197.07:34:40.74#ibcon#read 6, iclass 6, count 0 2006.197.07:34:40.74#ibcon#end of sib2, iclass 6, count 0 2006.197.07:34:40.74#ibcon#*mode == 0, iclass 6, count 0 2006.197.07:34:40.74#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.197.07:34:40.74#ibcon#[27=USB\r\n] 2006.197.07:34:40.74#ibcon#*before write, iclass 6, count 0 2006.197.07:34:40.74#ibcon#enter sib2, iclass 6, count 0 2006.197.07:34:40.74#ibcon#flushed, iclass 6, count 0 2006.197.07:34:40.74#ibcon#about to write, iclass 6, count 0 2006.197.07:34:40.74#ibcon#wrote, iclass 6, count 0 2006.197.07:34:40.74#ibcon#about to read 3, iclass 6, count 0 2006.197.07:34:40.77#ibcon#read 3, iclass 6, count 0 2006.197.07:34:40.77#ibcon#about to read 4, iclass 6, count 0 2006.197.07:34:40.77#ibcon#read 4, iclass 6, count 0 2006.197.07:34:40.77#ibcon#about to read 5, iclass 6, count 0 2006.197.07:34:40.77#ibcon#read 5, iclass 6, count 0 2006.197.07:34:40.77#ibcon#about to read 6, iclass 6, count 0 2006.197.07:34:40.77#ibcon#read 6, iclass 6, count 0 2006.197.07:34:40.77#ibcon#end of sib2, iclass 6, count 0 2006.197.07:34:40.77#ibcon#*after write, iclass 6, count 0 2006.197.07:34:40.77#ibcon#*before return 0, iclass 6, count 0 2006.197.07:34:40.77#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.197.07:34:40.77#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.197.07:34:40.77#ibcon#about to clear, iclass 6 cls_cnt 0 2006.197.07:34:40.77#ibcon#cleared, iclass 6 cls_cnt 0 2006.197.07:34:40.77$vc4f8/vblo=3,656.99 2006.197.07:34:40.77#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.197.07:34:40.77#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.197.07:34:40.77#ibcon#ireg 17 cls_cnt 0 2006.197.07:34:40.77#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.197.07:34:40.77#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.197.07:34:40.77#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.197.07:34:40.77#ibcon#enter wrdev, iclass 10, count 0 2006.197.07:34:40.77#ibcon#first serial, iclass 10, count 0 2006.197.07:34:40.77#ibcon#enter sib2, iclass 10, count 0 2006.197.07:34:40.77#ibcon#flushed, iclass 10, count 0 2006.197.07:34:40.77#ibcon#about to write, iclass 10, count 0 2006.197.07:34:40.77#ibcon#wrote, iclass 10, count 0 2006.197.07:34:40.77#ibcon#about to read 3, iclass 10, count 0 2006.197.07:34:40.79#ibcon#read 3, iclass 10, count 0 2006.197.07:34:40.79#ibcon#about to read 4, iclass 10, count 0 2006.197.07:34:40.79#ibcon#read 4, iclass 10, count 0 2006.197.07:34:40.79#ibcon#about to read 5, iclass 10, count 0 2006.197.07:34:40.79#ibcon#read 5, iclass 10, count 0 2006.197.07:34:40.79#ibcon#about to read 6, iclass 10, count 0 2006.197.07:34:40.79#ibcon#read 6, iclass 10, count 0 2006.197.07:34:40.79#ibcon#end of sib2, iclass 10, count 0 2006.197.07:34:40.79#ibcon#*mode == 0, iclass 10, count 0 2006.197.07:34:40.79#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.197.07:34:40.79#ibcon#[28=FRQ=03,656.99\r\n] 2006.197.07:34:40.79#ibcon#*before write, iclass 10, count 0 2006.197.07:34:40.79#ibcon#enter sib2, iclass 10, count 0 2006.197.07:34:40.79#ibcon#flushed, iclass 10, count 0 2006.197.07:34:40.79#ibcon#about to write, iclass 10, count 0 2006.197.07:34:40.79#ibcon#wrote, iclass 10, count 0 2006.197.07:34:40.79#ibcon#about to read 3, iclass 10, count 0 2006.197.07:34:40.83#ibcon#read 3, iclass 10, count 0 2006.197.07:34:40.83#ibcon#about to read 4, iclass 10, count 0 2006.197.07:34:40.83#ibcon#read 4, iclass 10, count 0 2006.197.07:34:40.83#ibcon#about to read 5, iclass 10, count 0 2006.197.07:34:40.83#ibcon#read 5, iclass 10, count 0 2006.197.07:34:40.83#ibcon#about to read 6, iclass 10, count 0 2006.197.07:34:40.83#ibcon#read 6, iclass 10, count 0 2006.197.07:34:40.83#ibcon#end of sib2, iclass 10, count 0 2006.197.07:34:40.83#ibcon#*after write, iclass 10, count 0 2006.197.07:34:40.83#ibcon#*before return 0, iclass 10, count 0 2006.197.07:34:40.83#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.197.07:34:40.83#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.197.07:34:40.83#ibcon#about to clear, iclass 10 cls_cnt 0 2006.197.07:34:40.83#ibcon#cleared, iclass 10 cls_cnt 0 2006.197.07:34:40.83$vc4f8/vb=3,4 2006.197.07:34:40.83#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.197.07:34:40.83#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.197.07:34:40.83#ibcon#ireg 11 cls_cnt 2 2006.197.07:34:40.83#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.197.07:34:40.89#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.197.07:34:40.89#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.197.07:34:40.89#ibcon#enter wrdev, iclass 12, count 2 2006.197.07:34:40.89#ibcon#first serial, iclass 12, count 2 2006.197.07:34:40.89#ibcon#enter sib2, iclass 12, count 2 2006.197.07:34:40.89#ibcon#flushed, iclass 12, count 2 2006.197.07:34:40.89#ibcon#about to write, iclass 12, count 2 2006.197.07:34:40.89#ibcon#wrote, iclass 12, count 2 2006.197.07:34:40.89#ibcon#about to read 3, iclass 12, count 2 2006.197.07:34:40.91#ibcon#read 3, iclass 12, count 2 2006.197.07:34:40.91#ibcon#about to read 4, iclass 12, count 2 2006.197.07:34:40.91#ibcon#read 4, iclass 12, count 2 2006.197.07:34:40.91#ibcon#about to read 5, iclass 12, count 2 2006.197.07:34:40.91#ibcon#read 5, iclass 12, count 2 2006.197.07:34:40.91#ibcon#about to read 6, iclass 12, count 2 2006.197.07:34:40.91#ibcon#read 6, iclass 12, count 2 2006.197.07:34:40.91#ibcon#end of sib2, iclass 12, count 2 2006.197.07:34:40.91#ibcon#*mode == 0, iclass 12, count 2 2006.197.07:34:40.91#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.197.07:34:40.91#ibcon#[27=AT03-04\r\n] 2006.197.07:34:40.91#ibcon#*before write, iclass 12, count 2 2006.197.07:34:40.91#ibcon#enter sib2, iclass 12, count 2 2006.197.07:34:40.91#ibcon#flushed, iclass 12, count 2 2006.197.07:34:40.91#ibcon#about to write, iclass 12, count 2 2006.197.07:34:40.91#ibcon#wrote, iclass 12, count 2 2006.197.07:34:40.91#ibcon#about to read 3, iclass 12, count 2 2006.197.07:34:40.94#ibcon#read 3, iclass 12, count 2 2006.197.07:34:40.94#ibcon#about to read 4, iclass 12, count 2 2006.197.07:34:40.94#ibcon#read 4, iclass 12, count 2 2006.197.07:34:40.94#ibcon#about to read 5, iclass 12, count 2 2006.197.07:34:40.94#ibcon#read 5, iclass 12, count 2 2006.197.07:34:40.94#ibcon#about to read 6, iclass 12, count 2 2006.197.07:34:40.94#ibcon#read 6, iclass 12, count 2 2006.197.07:34:40.94#ibcon#end of sib2, iclass 12, count 2 2006.197.07:34:40.94#ibcon#*after write, iclass 12, count 2 2006.197.07:34:40.94#ibcon#*before return 0, iclass 12, count 2 2006.197.07:34:40.94#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.197.07:34:40.94#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.197.07:34:40.94#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.197.07:34:40.94#ibcon#ireg 7 cls_cnt 0 2006.197.07:34:40.94#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.197.07:34:41.06#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.197.07:34:41.06#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.197.07:34:41.06#ibcon#enter wrdev, iclass 12, count 0 2006.197.07:34:41.06#ibcon#first serial, iclass 12, count 0 2006.197.07:34:41.06#ibcon#enter sib2, iclass 12, count 0 2006.197.07:34:41.06#ibcon#flushed, iclass 12, count 0 2006.197.07:34:41.06#ibcon#about to write, iclass 12, count 0 2006.197.07:34:41.06#ibcon#wrote, iclass 12, count 0 2006.197.07:34:41.06#ibcon#about to read 3, iclass 12, count 0 2006.197.07:34:41.08#ibcon#read 3, iclass 12, count 0 2006.197.07:34:41.08#ibcon#about to read 4, iclass 12, count 0 2006.197.07:34:41.08#ibcon#read 4, iclass 12, count 0 2006.197.07:34:41.08#ibcon#about to read 5, iclass 12, count 0 2006.197.07:34:41.08#ibcon#read 5, iclass 12, count 0 2006.197.07:34:41.08#ibcon#about to read 6, iclass 12, count 0 2006.197.07:34:41.08#ibcon#read 6, iclass 12, count 0 2006.197.07:34:41.08#ibcon#end of sib2, iclass 12, count 0 2006.197.07:34:41.08#ibcon#*mode == 0, iclass 12, count 0 2006.197.07:34:41.08#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.197.07:34:41.08#ibcon#[27=USB\r\n] 2006.197.07:34:41.08#ibcon#*before write, iclass 12, count 0 2006.197.07:34:41.08#ibcon#enter sib2, iclass 12, count 0 2006.197.07:34:41.08#ibcon#flushed, iclass 12, count 0 2006.197.07:34:41.08#ibcon#about to write, iclass 12, count 0 2006.197.07:34:41.08#ibcon#wrote, iclass 12, count 0 2006.197.07:34:41.08#ibcon#about to read 3, iclass 12, count 0 2006.197.07:34:41.11#ibcon#read 3, iclass 12, count 0 2006.197.07:34:41.11#ibcon#about to read 4, iclass 12, count 0 2006.197.07:34:41.11#ibcon#read 4, iclass 12, count 0 2006.197.07:34:41.11#ibcon#about to read 5, iclass 12, count 0 2006.197.07:34:41.11#ibcon#read 5, iclass 12, count 0 2006.197.07:34:41.11#ibcon#about to read 6, iclass 12, count 0 2006.197.07:34:41.11#ibcon#read 6, iclass 12, count 0 2006.197.07:34:41.11#ibcon#end of sib2, iclass 12, count 0 2006.197.07:34:41.11#ibcon#*after write, iclass 12, count 0 2006.197.07:34:41.11#ibcon#*before return 0, iclass 12, count 0 2006.197.07:34:41.11#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.197.07:34:41.11#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.197.07:34:41.11#ibcon#about to clear, iclass 12 cls_cnt 0 2006.197.07:34:41.11#ibcon#cleared, iclass 12 cls_cnt 0 2006.197.07:34:41.11$vc4f8/vblo=4,712.99 2006.197.07:34:41.11#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.197.07:34:41.11#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.197.07:34:41.11#ibcon#ireg 17 cls_cnt 0 2006.197.07:34:41.11#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.197.07:34:41.11#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.197.07:34:41.11#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.197.07:34:41.11#ibcon#enter wrdev, iclass 14, count 0 2006.197.07:34:41.11#ibcon#first serial, iclass 14, count 0 2006.197.07:34:41.11#ibcon#enter sib2, iclass 14, count 0 2006.197.07:34:41.11#ibcon#flushed, iclass 14, count 0 2006.197.07:34:41.11#ibcon#about to write, iclass 14, count 0 2006.197.07:34:41.11#ibcon#wrote, iclass 14, count 0 2006.197.07:34:41.11#ibcon#about to read 3, iclass 14, count 0 2006.197.07:34:41.13#ibcon#read 3, iclass 14, count 0 2006.197.07:34:41.13#ibcon#about to read 4, iclass 14, count 0 2006.197.07:34:41.13#ibcon#read 4, iclass 14, count 0 2006.197.07:34:41.13#ibcon#about to read 5, iclass 14, count 0 2006.197.07:34:41.13#ibcon#read 5, iclass 14, count 0 2006.197.07:34:41.13#ibcon#about to read 6, iclass 14, count 0 2006.197.07:34:41.13#ibcon#read 6, iclass 14, count 0 2006.197.07:34:41.13#ibcon#end of sib2, iclass 14, count 0 2006.197.07:34:41.13#ibcon#*mode == 0, iclass 14, count 0 2006.197.07:34:41.13#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.197.07:34:41.13#ibcon#[28=FRQ=04,712.99\r\n] 2006.197.07:34:41.13#ibcon#*before write, iclass 14, count 0 2006.197.07:34:41.13#ibcon#enter sib2, iclass 14, count 0 2006.197.07:34:41.13#ibcon#flushed, iclass 14, count 0 2006.197.07:34:41.13#ibcon#about to write, iclass 14, count 0 2006.197.07:34:41.13#ibcon#wrote, iclass 14, count 0 2006.197.07:34:41.13#ibcon#about to read 3, iclass 14, count 0 2006.197.07:34:41.17#ibcon#read 3, iclass 14, count 0 2006.197.07:34:41.17#ibcon#about to read 4, iclass 14, count 0 2006.197.07:34:41.17#ibcon#read 4, iclass 14, count 0 2006.197.07:34:41.17#ibcon#about to read 5, iclass 14, count 0 2006.197.07:34:41.17#ibcon#read 5, iclass 14, count 0 2006.197.07:34:41.17#ibcon#about to read 6, iclass 14, count 0 2006.197.07:34:41.17#ibcon#read 6, iclass 14, count 0 2006.197.07:34:41.17#ibcon#end of sib2, iclass 14, count 0 2006.197.07:34:41.17#ibcon#*after write, iclass 14, count 0 2006.197.07:34:41.17#ibcon#*before return 0, iclass 14, count 0 2006.197.07:34:41.17#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.197.07:34:41.17#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.197.07:34:41.17#ibcon#about to clear, iclass 14 cls_cnt 0 2006.197.07:34:41.17#ibcon#cleared, iclass 14 cls_cnt 0 2006.197.07:34:41.17$vc4f8/vb=4,4 2006.197.07:34:41.17#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.197.07:34:41.17#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.197.07:34:41.17#ibcon#ireg 11 cls_cnt 2 2006.197.07:34:41.17#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.197.07:34:41.23#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.197.07:34:41.23#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.197.07:34:41.23#ibcon#enter wrdev, iclass 16, count 2 2006.197.07:34:41.23#ibcon#first serial, iclass 16, count 2 2006.197.07:34:41.23#ibcon#enter sib2, iclass 16, count 2 2006.197.07:34:41.23#ibcon#flushed, iclass 16, count 2 2006.197.07:34:41.23#ibcon#about to write, iclass 16, count 2 2006.197.07:34:41.23#ibcon#wrote, iclass 16, count 2 2006.197.07:34:41.23#ibcon#about to read 3, iclass 16, count 2 2006.197.07:34:41.25#ibcon#read 3, iclass 16, count 2 2006.197.07:34:41.25#ibcon#about to read 4, iclass 16, count 2 2006.197.07:34:41.25#ibcon#read 4, iclass 16, count 2 2006.197.07:34:41.25#ibcon#about to read 5, iclass 16, count 2 2006.197.07:34:41.25#ibcon#read 5, iclass 16, count 2 2006.197.07:34:41.25#ibcon#about to read 6, iclass 16, count 2 2006.197.07:34:41.25#ibcon#read 6, iclass 16, count 2 2006.197.07:34:41.25#ibcon#end of sib2, iclass 16, count 2 2006.197.07:34:41.25#ibcon#*mode == 0, iclass 16, count 2 2006.197.07:34:41.25#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.197.07:34:41.25#ibcon#[27=AT04-04\r\n] 2006.197.07:34:41.25#ibcon#*before write, iclass 16, count 2 2006.197.07:34:41.25#ibcon#enter sib2, iclass 16, count 2 2006.197.07:34:41.25#ibcon#flushed, iclass 16, count 2 2006.197.07:34:41.25#ibcon#about to write, iclass 16, count 2 2006.197.07:34:41.25#ibcon#wrote, iclass 16, count 2 2006.197.07:34:41.25#ibcon#about to read 3, iclass 16, count 2 2006.197.07:34:41.28#ibcon#read 3, iclass 16, count 2 2006.197.07:34:41.28#ibcon#about to read 4, iclass 16, count 2 2006.197.07:34:41.28#ibcon#read 4, iclass 16, count 2 2006.197.07:34:41.28#ibcon#about to read 5, iclass 16, count 2 2006.197.07:34:41.28#ibcon#read 5, iclass 16, count 2 2006.197.07:34:41.28#ibcon#about to read 6, iclass 16, count 2 2006.197.07:34:41.28#ibcon#read 6, iclass 16, count 2 2006.197.07:34:41.28#ibcon#end of sib2, iclass 16, count 2 2006.197.07:34:41.28#ibcon#*after write, iclass 16, count 2 2006.197.07:34:41.28#ibcon#*before return 0, iclass 16, count 2 2006.197.07:34:41.28#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.197.07:34:41.28#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.197.07:34:41.28#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.197.07:34:41.28#ibcon#ireg 7 cls_cnt 0 2006.197.07:34:41.28#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.197.07:34:41.40#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.197.07:34:41.40#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.197.07:34:41.40#ibcon#enter wrdev, iclass 16, count 0 2006.197.07:34:41.40#ibcon#first serial, iclass 16, count 0 2006.197.07:34:41.40#ibcon#enter sib2, iclass 16, count 0 2006.197.07:34:41.40#ibcon#flushed, iclass 16, count 0 2006.197.07:34:41.40#ibcon#about to write, iclass 16, count 0 2006.197.07:34:41.40#ibcon#wrote, iclass 16, count 0 2006.197.07:34:41.40#ibcon#about to read 3, iclass 16, count 0 2006.197.07:34:41.42#ibcon#read 3, iclass 16, count 0 2006.197.07:34:41.42#ibcon#about to read 4, iclass 16, count 0 2006.197.07:34:41.42#ibcon#read 4, iclass 16, count 0 2006.197.07:34:41.42#ibcon#about to read 5, iclass 16, count 0 2006.197.07:34:41.42#ibcon#read 5, iclass 16, count 0 2006.197.07:34:41.42#ibcon#about to read 6, iclass 16, count 0 2006.197.07:34:41.42#ibcon#read 6, iclass 16, count 0 2006.197.07:34:41.42#ibcon#end of sib2, iclass 16, count 0 2006.197.07:34:41.42#ibcon#*mode == 0, iclass 16, count 0 2006.197.07:34:41.42#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.197.07:34:41.42#ibcon#[27=USB\r\n] 2006.197.07:34:41.42#ibcon#*before write, iclass 16, count 0 2006.197.07:34:41.42#ibcon#enter sib2, iclass 16, count 0 2006.197.07:34:41.42#ibcon#flushed, iclass 16, count 0 2006.197.07:34:41.42#ibcon#about to write, iclass 16, count 0 2006.197.07:34:41.42#ibcon#wrote, iclass 16, count 0 2006.197.07:34:41.42#ibcon#about to read 3, iclass 16, count 0 2006.197.07:34:41.45#ibcon#read 3, iclass 16, count 0 2006.197.07:34:41.45#ibcon#about to read 4, iclass 16, count 0 2006.197.07:34:41.45#ibcon#read 4, iclass 16, count 0 2006.197.07:34:41.45#ibcon#about to read 5, iclass 16, count 0 2006.197.07:34:41.45#ibcon#read 5, iclass 16, count 0 2006.197.07:34:41.45#ibcon#about to read 6, iclass 16, count 0 2006.197.07:34:41.45#ibcon#read 6, iclass 16, count 0 2006.197.07:34:41.45#ibcon#end of sib2, iclass 16, count 0 2006.197.07:34:41.45#ibcon#*after write, iclass 16, count 0 2006.197.07:34:41.45#ibcon#*before return 0, iclass 16, count 0 2006.197.07:34:41.45#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.197.07:34:41.45#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.197.07:34:41.45#ibcon#about to clear, iclass 16 cls_cnt 0 2006.197.07:34:41.45#ibcon#cleared, iclass 16 cls_cnt 0 2006.197.07:34:41.45$vc4f8/vblo=5,744.99 2006.197.07:34:41.45#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.197.07:34:41.45#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.197.07:34:41.45#ibcon#ireg 17 cls_cnt 0 2006.197.07:34:41.45#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.197.07:34:41.45#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.197.07:34:41.45#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.197.07:34:41.45#ibcon#enter wrdev, iclass 18, count 0 2006.197.07:34:41.45#ibcon#first serial, iclass 18, count 0 2006.197.07:34:41.45#ibcon#enter sib2, iclass 18, count 0 2006.197.07:34:41.45#ibcon#flushed, iclass 18, count 0 2006.197.07:34:41.45#ibcon#about to write, iclass 18, count 0 2006.197.07:34:41.45#ibcon#wrote, iclass 18, count 0 2006.197.07:34:41.45#ibcon#about to read 3, iclass 18, count 0 2006.197.07:34:41.47#ibcon#read 3, iclass 18, count 0 2006.197.07:34:41.47#ibcon#about to read 4, iclass 18, count 0 2006.197.07:34:41.47#ibcon#read 4, iclass 18, count 0 2006.197.07:34:41.47#ibcon#about to read 5, iclass 18, count 0 2006.197.07:34:41.47#ibcon#read 5, iclass 18, count 0 2006.197.07:34:41.47#ibcon#about to read 6, iclass 18, count 0 2006.197.07:34:41.47#ibcon#read 6, iclass 18, count 0 2006.197.07:34:41.47#ibcon#end of sib2, iclass 18, count 0 2006.197.07:34:41.47#ibcon#*mode == 0, iclass 18, count 0 2006.197.07:34:41.47#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.197.07:34:41.47#ibcon#[28=FRQ=05,744.99\r\n] 2006.197.07:34:41.47#ibcon#*before write, iclass 18, count 0 2006.197.07:34:41.47#ibcon#enter sib2, iclass 18, count 0 2006.197.07:34:41.47#ibcon#flushed, iclass 18, count 0 2006.197.07:34:41.47#ibcon#about to write, iclass 18, count 0 2006.197.07:34:41.47#ibcon#wrote, iclass 18, count 0 2006.197.07:34:41.47#ibcon#about to read 3, iclass 18, count 0 2006.197.07:34:41.51#ibcon#read 3, iclass 18, count 0 2006.197.07:34:41.51#ibcon#about to read 4, iclass 18, count 0 2006.197.07:34:41.51#ibcon#read 4, iclass 18, count 0 2006.197.07:34:41.51#ibcon#about to read 5, iclass 18, count 0 2006.197.07:34:41.51#ibcon#read 5, iclass 18, count 0 2006.197.07:34:41.51#ibcon#about to read 6, iclass 18, count 0 2006.197.07:34:41.51#ibcon#read 6, iclass 18, count 0 2006.197.07:34:41.51#ibcon#end of sib2, iclass 18, count 0 2006.197.07:34:41.51#ibcon#*after write, iclass 18, count 0 2006.197.07:34:41.51#ibcon#*before return 0, iclass 18, count 0 2006.197.07:34:41.51#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.197.07:34:41.51#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.197.07:34:41.51#ibcon#about to clear, iclass 18 cls_cnt 0 2006.197.07:34:41.51#ibcon#cleared, iclass 18 cls_cnt 0 2006.197.07:34:41.51$vc4f8/vb=5,4 2006.197.07:34:41.51#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.197.07:34:41.51#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.197.07:34:41.51#ibcon#ireg 11 cls_cnt 2 2006.197.07:34:41.51#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.197.07:34:41.57#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.197.07:34:41.57#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.197.07:34:41.57#ibcon#enter wrdev, iclass 20, count 2 2006.197.07:34:41.57#ibcon#first serial, iclass 20, count 2 2006.197.07:34:41.57#ibcon#enter sib2, iclass 20, count 2 2006.197.07:34:41.57#ibcon#flushed, iclass 20, count 2 2006.197.07:34:41.57#ibcon#about to write, iclass 20, count 2 2006.197.07:34:41.57#ibcon#wrote, iclass 20, count 2 2006.197.07:34:41.57#ibcon#about to read 3, iclass 20, count 2 2006.197.07:34:41.59#ibcon#read 3, iclass 20, count 2 2006.197.07:34:41.59#ibcon#about to read 4, iclass 20, count 2 2006.197.07:34:41.59#ibcon#read 4, iclass 20, count 2 2006.197.07:34:41.59#ibcon#about to read 5, iclass 20, count 2 2006.197.07:34:41.59#ibcon#read 5, iclass 20, count 2 2006.197.07:34:41.59#ibcon#about to read 6, iclass 20, count 2 2006.197.07:34:41.59#ibcon#read 6, iclass 20, count 2 2006.197.07:34:41.59#ibcon#end of sib2, iclass 20, count 2 2006.197.07:34:41.59#ibcon#*mode == 0, iclass 20, count 2 2006.197.07:34:41.59#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.197.07:34:41.59#ibcon#[27=AT05-04\r\n] 2006.197.07:34:41.59#ibcon#*before write, iclass 20, count 2 2006.197.07:34:41.59#ibcon#enter sib2, iclass 20, count 2 2006.197.07:34:41.59#ibcon#flushed, iclass 20, count 2 2006.197.07:34:41.59#ibcon#about to write, iclass 20, count 2 2006.197.07:34:41.59#ibcon#wrote, iclass 20, count 2 2006.197.07:34:41.59#ibcon#about to read 3, iclass 20, count 2 2006.197.07:34:41.62#ibcon#read 3, iclass 20, count 2 2006.197.07:34:41.62#ibcon#about to read 4, iclass 20, count 2 2006.197.07:34:41.62#ibcon#read 4, iclass 20, count 2 2006.197.07:34:41.62#ibcon#about to read 5, iclass 20, count 2 2006.197.07:34:41.62#ibcon#read 5, iclass 20, count 2 2006.197.07:34:41.62#ibcon#about to read 6, iclass 20, count 2 2006.197.07:34:41.62#ibcon#read 6, iclass 20, count 2 2006.197.07:34:41.62#ibcon#end of sib2, iclass 20, count 2 2006.197.07:34:41.62#ibcon#*after write, iclass 20, count 2 2006.197.07:34:41.62#ibcon#*before return 0, iclass 20, count 2 2006.197.07:34:41.62#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.197.07:34:41.62#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.197.07:34:41.62#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.197.07:34:41.62#ibcon#ireg 7 cls_cnt 0 2006.197.07:34:41.62#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.197.07:34:41.73#abcon#<5=/04 3.1 6.6 25.92 971003.0\r\n> 2006.197.07:34:41.74#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.197.07:34:41.74#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.197.07:34:41.74#ibcon#enter wrdev, iclass 20, count 0 2006.197.07:34:41.74#ibcon#first serial, iclass 20, count 0 2006.197.07:34:41.74#ibcon#enter sib2, iclass 20, count 0 2006.197.07:34:41.74#ibcon#flushed, iclass 20, count 0 2006.197.07:34:41.74#ibcon#about to write, iclass 20, count 0 2006.197.07:34:41.74#ibcon#wrote, iclass 20, count 0 2006.197.07:34:41.74#ibcon#about to read 3, iclass 20, count 0 2006.197.07:34:41.75#abcon#{5=INTERFACE CLEAR} 2006.197.07:34:41.76#ibcon#read 3, iclass 20, count 0 2006.197.07:34:41.76#ibcon#about to read 4, iclass 20, count 0 2006.197.07:34:41.76#ibcon#read 4, iclass 20, count 0 2006.197.07:34:41.76#ibcon#about to read 5, iclass 20, count 0 2006.197.07:34:41.76#ibcon#read 5, iclass 20, count 0 2006.197.07:34:41.76#ibcon#about to read 6, iclass 20, count 0 2006.197.07:34:41.76#ibcon#read 6, iclass 20, count 0 2006.197.07:34:41.76#ibcon#end of sib2, iclass 20, count 0 2006.197.07:34:41.76#ibcon#*mode == 0, iclass 20, count 0 2006.197.07:34:41.76#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.197.07:34:41.76#ibcon#[27=USB\r\n] 2006.197.07:34:41.76#ibcon#*before write, iclass 20, count 0 2006.197.07:34:41.76#ibcon#enter sib2, iclass 20, count 0 2006.197.07:34:41.76#ibcon#flushed, iclass 20, count 0 2006.197.07:34:41.76#ibcon#about to write, iclass 20, count 0 2006.197.07:34:41.76#ibcon#wrote, iclass 20, count 0 2006.197.07:34:41.76#ibcon#about to read 3, iclass 20, count 0 2006.197.07:34:41.79#ibcon#read 3, iclass 20, count 0 2006.197.07:34:41.79#ibcon#about to read 4, iclass 20, count 0 2006.197.07:34:41.79#ibcon#read 4, iclass 20, count 0 2006.197.07:34:41.79#ibcon#about to read 5, iclass 20, count 0 2006.197.07:34:41.79#ibcon#read 5, iclass 20, count 0 2006.197.07:34:41.79#ibcon#about to read 6, iclass 20, count 0 2006.197.07:34:41.79#ibcon#read 6, iclass 20, count 0 2006.197.07:34:41.79#ibcon#end of sib2, iclass 20, count 0 2006.197.07:34:41.79#ibcon#*after write, iclass 20, count 0 2006.197.07:34:41.79#ibcon#*before return 0, iclass 20, count 0 2006.197.07:34:41.79#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.197.07:34:41.79#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.197.07:34:41.79#ibcon#about to clear, iclass 20 cls_cnt 0 2006.197.07:34:41.79#ibcon#cleared, iclass 20 cls_cnt 0 2006.197.07:34:41.79$vc4f8/vblo=6,752.99 2006.197.07:34:41.79#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.197.07:34:41.79#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.197.07:34:41.79#ibcon#ireg 17 cls_cnt 0 2006.197.07:34:41.79#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.197.07:34:41.79#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.197.07:34:41.79#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.197.07:34:41.79#ibcon#enter wrdev, iclass 25, count 0 2006.197.07:34:41.79#ibcon#first serial, iclass 25, count 0 2006.197.07:34:41.79#ibcon#enter sib2, iclass 25, count 0 2006.197.07:34:41.79#ibcon#flushed, iclass 25, count 0 2006.197.07:34:41.79#ibcon#about to write, iclass 25, count 0 2006.197.07:34:41.79#ibcon#wrote, iclass 25, count 0 2006.197.07:34:41.79#ibcon#about to read 3, iclass 25, count 0 2006.197.07:34:41.81#ibcon#read 3, iclass 25, count 0 2006.197.07:34:41.81#ibcon#about to read 4, iclass 25, count 0 2006.197.07:34:41.81#ibcon#read 4, iclass 25, count 0 2006.197.07:34:41.81#ibcon#about to read 5, iclass 25, count 0 2006.197.07:34:41.81#ibcon#read 5, iclass 25, count 0 2006.197.07:34:41.81#ibcon#about to read 6, iclass 25, count 0 2006.197.07:34:41.81#ibcon#read 6, iclass 25, count 0 2006.197.07:34:41.81#ibcon#end of sib2, iclass 25, count 0 2006.197.07:34:41.81#ibcon#*mode == 0, iclass 25, count 0 2006.197.07:34:41.81#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.197.07:34:41.81#ibcon#[28=FRQ=06,752.99\r\n] 2006.197.07:34:41.81#ibcon#*before write, iclass 25, count 0 2006.197.07:34:41.81#ibcon#enter sib2, iclass 25, count 0 2006.197.07:34:41.81#ibcon#flushed, iclass 25, count 0 2006.197.07:34:41.81#ibcon#about to write, iclass 25, count 0 2006.197.07:34:41.81#ibcon#wrote, iclass 25, count 0 2006.197.07:34:41.81#ibcon#about to read 3, iclass 25, count 0 2006.197.07:34:41.81#abcon#[5=S1D000X0/0*\r\n] 2006.197.07:34:41.85#ibcon#read 3, iclass 25, count 0 2006.197.07:34:41.85#ibcon#about to read 4, iclass 25, count 0 2006.197.07:34:41.85#ibcon#read 4, iclass 25, count 0 2006.197.07:34:41.85#ibcon#about to read 5, iclass 25, count 0 2006.197.07:34:41.85#ibcon#read 5, iclass 25, count 0 2006.197.07:34:41.85#ibcon#about to read 6, iclass 25, count 0 2006.197.07:34:41.85#ibcon#read 6, iclass 25, count 0 2006.197.07:34:41.85#ibcon#end of sib2, iclass 25, count 0 2006.197.07:34:41.85#ibcon#*after write, iclass 25, count 0 2006.197.07:34:41.85#ibcon#*before return 0, iclass 25, count 0 2006.197.07:34:41.85#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.197.07:34:41.85#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.197.07:34:41.85#ibcon#about to clear, iclass 25 cls_cnt 0 2006.197.07:34:41.85#ibcon#cleared, iclass 25 cls_cnt 0 2006.197.07:34:41.85$vc4f8/vb=6,4 2006.197.07:34:41.85#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.197.07:34:41.85#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.197.07:34:41.85#ibcon#ireg 11 cls_cnt 2 2006.197.07:34:41.85#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.197.07:34:41.91#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.197.07:34:41.91#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.197.07:34:41.91#ibcon#enter wrdev, iclass 28, count 2 2006.197.07:34:41.91#ibcon#first serial, iclass 28, count 2 2006.197.07:34:41.91#ibcon#enter sib2, iclass 28, count 2 2006.197.07:34:41.91#ibcon#flushed, iclass 28, count 2 2006.197.07:34:41.91#ibcon#about to write, iclass 28, count 2 2006.197.07:34:41.91#ibcon#wrote, iclass 28, count 2 2006.197.07:34:41.91#ibcon#about to read 3, iclass 28, count 2 2006.197.07:34:41.93#ibcon#read 3, iclass 28, count 2 2006.197.07:34:41.93#ibcon#about to read 4, iclass 28, count 2 2006.197.07:34:41.93#ibcon#read 4, iclass 28, count 2 2006.197.07:34:41.93#ibcon#about to read 5, iclass 28, count 2 2006.197.07:34:41.93#ibcon#read 5, iclass 28, count 2 2006.197.07:34:41.93#ibcon#about to read 6, iclass 28, count 2 2006.197.07:34:41.93#ibcon#read 6, iclass 28, count 2 2006.197.07:34:41.93#ibcon#end of sib2, iclass 28, count 2 2006.197.07:34:41.93#ibcon#*mode == 0, iclass 28, count 2 2006.197.07:34:41.93#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.197.07:34:41.93#ibcon#[27=AT06-04\r\n] 2006.197.07:34:41.93#ibcon#*before write, iclass 28, count 2 2006.197.07:34:41.93#ibcon#enter sib2, iclass 28, count 2 2006.197.07:34:41.93#ibcon#flushed, iclass 28, count 2 2006.197.07:34:41.93#ibcon#about to write, iclass 28, count 2 2006.197.07:34:41.93#ibcon#wrote, iclass 28, count 2 2006.197.07:34:41.93#ibcon#about to read 3, iclass 28, count 2 2006.197.07:34:41.96#ibcon#read 3, iclass 28, count 2 2006.197.07:34:41.96#ibcon#about to read 4, iclass 28, count 2 2006.197.07:34:41.96#ibcon#read 4, iclass 28, count 2 2006.197.07:34:41.96#ibcon#about to read 5, iclass 28, count 2 2006.197.07:34:41.96#ibcon#read 5, iclass 28, count 2 2006.197.07:34:41.96#ibcon#about to read 6, iclass 28, count 2 2006.197.07:34:41.96#ibcon#read 6, iclass 28, count 2 2006.197.07:34:41.96#ibcon#end of sib2, iclass 28, count 2 2006.197.07:34:41.96#ibcon#*after write, iclass 28, count 2 2006.197.07:34:41.96#ibcon#*before return 0, iclass 28, count 2 2006.197.07:34:41.96#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.197.07:34:41.96#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.197.07:34:41.96#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.197.07:34:41.96#ibcon#ireg 7 cls_cnt 0 2006.197.07:34:41.96#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.197.07:34:42.08#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.197.07:34:42.08#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.197.07:34:42.08#ibcon#enter wrdev, iclass 28, count 0 2006.197.07:34:42.08#ibcon#first serial, iclass 28, count 0 2006.197.07:34:42.08#ibcon#enter sib2, iclass 28, count 0 2006.197.07:34:42.08#ibcon#flushed, iclass 28, count 0 2006.197.07:34:42.08#ibcon#about to write, iclass 28, count 0 2006.197.07:34:42.08#ibcon#wrote, iclass 28, count 0 2006.197.07:34:42.08#ibcon#about to read 3, iclass 28, count 0 2006.197.07:34:42.10#ibcon#read 3, iclass 28, count 0 2006.197.07:34:42.10#ibcon#about to read 4, iclass 28, count 0 2006.197.07:34:42.10#ibcon#read 4, iclass 28, count 0 2006.197.07:34:42.10#ibcon#about to read 5, iclass 28, count 0 2006.197.07:34:42.10#ibcon#read 5, iclass 28, count 0 2006.197.07:34:42.10#ibcon#about to read 6, iclass 28, count 0 2006.197.07:34:42.10#ibcon#read 6, iclass 28, count 0 2006.197.07:34:42.10#ibcon#end of sib2, iclass 28, count 0 2006.197.07:34:42.10#ibcon#*mode == 0, iclass 28, count 0 2006.197.07:34:42.10#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.197.07:34:42.10#ibcon#[27=USB\r\n] 2006.197.07:34:42.10#ibcon#*before write, iclass 28, count 0 2006.197.07:34:42.10#ibcon#enter sib2, iclass 28, count 0 2006.197.07:34:42.10#ibcon#flushed, iclass 28, count 0 2006.197.07:34:42.10#ibcon#about to write, iclass 28, count 0 2006.197.07:34:42.10#ibcon#wrote, iclass 28, count 0 2006.197.07:34:42.10#ibcon#about to read 3, iclass 28, count 0 2006.197.07:34:42.13#ibcon#read 3, iclass 28, count 0 2006.197.07:34:42.13#ibcon#about to read 4, iclass 28, count 0 2006.197.07:34:42.13#ibcon#read 4, iclass 28, count 0 2006.197.07:34:42.13#ibcon#about to read 5, iclass 28, count 0 2006.197.07:34:42.13#ibcon#read 5, iclass 28, count 0 2006.197.07:34:42.13#ibcon#about to read 6, iclass 28, count 0 2006.197.07:34:42.13#ibcon#read 6, iclass 28, count 0 2006.197.07:34:42.13#ibcon#end of sib2, iclass 28, count 0 2006.197.07:34:42.13#ibcon#*after write, iclass 28, count 0 2006.197.07:34:42.13#ibcon#*before return 0, iclass 28, count 0 2006.197.07:34:42.13#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.197.07:34:42.13#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.197.07:34:42.13#ibcon#about to clear, iclass 28 cls_cnt 0 2006.197.07:34:42.13#ibcon#cleared, iclass 28 cls_cnt 0 2006.197.07:34:42.13$vc4f8/vabw=wide 2006.197.07:34:42.13#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.197.07:34:42.13#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.197.07:34:42.13#ibcon#ireg 8 cls_cnt 0 2006.197.07:34:42.13#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.197.07:34:42.13#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.197.07:34:42.13#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.197.07:34:42.13#ibcon#enter wrdev, iclass 30, count 0 2006.197.07:34:42.13#ibcon#first serial, iclass 30, count 0 2006.197.07:34:42.13#ibcon#enter sib2, iclass 30, count 0 2006.197.07:34:42.13#ibcon#flushed, iclass 30, count 0 2006.197.07:34:42.13#ibcon#about to write, iclass 30, count 0 2006.197.07:34:42.13#ibcon#wrote, iclass 30, count 0 2006.197.07:34:42.13#ibcon#about to read 3, iclass 30, count 0 2006.197.07:34:42.15#ibcon#read 3, iclass 30, count 0 2006.197.07:34:42.15#ibcon#about to read 4, iclass 30, count 0 2006.197.07:34:42.15#ibcon#read 4, iclass 30, count 0 2006.197.07:34:42.15#ibcon#about to read 5, iclass 30, count 0 2006.197.07:34:42.15#ibcon#read 5, iclass 30, count 0 2006.197.07:34:42.15#ibcon#about to read 6, iclass 30, count 0 2006.197.07:34:42.15#ibcon#read 6, iclass 30, count 0 2006.197.07:34:42.15#ibcon#end of sib2, iclass 30, count 0 2006.197.07:34:42.15#ibcon#*mode == 0, iclass 30, count 0 2006.197.07:34:42.15#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.197.07:34:42.15#ibcon#[25=BW32\r\n] 2006.197.07:34:42.15#ibcon#*before write, iclass 30, count 0 2006.197.07:34:42.15#ibcon#enter sib2, iclass 30, count 0 2006.197.07:34:42.15#ibcon#flushed, iclass 30, count 0 2006.197.07:34:42.15#ibcon#about to write, iclass 30, count 0 2006.197.07:34:42.15#ibcon#wrote, iclass 30, count 0 2006.197.07:34:42.15#ibcon#about to read 3, iclass 30, count 0 2006.197.07:34:42.18#ibcon#read 3, iclass 30, count 0 2006.197.07:34:42.18#ibcon#about to read 4, iclass 30, count 0 2006.197.07:34:42.18#ibcon#read 4, iclass 30, count 0 2006.197.07:34:42.18#ibcon#about to read 5, iclass 30, count 0 2006.197.07:34:42.18#ibcon#read 5, iclass 30, count 0 2006.197.07:34:42.18#ibcon#about to read 6, iclass 30, count 0 2006.197.07:34:42.18#ibcon#read 6, iclass 30, count 0 2006.197.07:34:42.18#ibcon#end of sib2, iclass 30, count 0 2006.197.07:34:42.18#ibcon#*after write, iclass 30, count 0 2006.197.07:34:42.18#ibcon#*before return 0, iclass 30, count 0 2006.197.07:34:42.18#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.197.07:34:42.18#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.197.07:34:42.18#ibcon#about to clear, iclass 30 cls_cnt 0 2006.197.07:34:42.18#ibcon#cleared, iclass 30 cls_cnt 0 2006.197.07:34:42.18$vc4f8/vbbw=wide 2006.197.07:34:42.18#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.197.07:34:42.18#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.197.07:34:42.18#ibcon#ireg 8 cls_cnt 0 2006.197.07:34:42.18#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.197.07:34:42.25#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.197.07:34:42.25#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.197.07:34:42.25#ibcon#enter wrdev, iclass 32, count 0 2006.197.07:34:42.25#ibcon#first serial, iclass 32, count 0 2006.197.07:34:42.25#ibcon#enter sib2, iclass 32, count 0 2006.197.07:34:42.25#ibcon#flushed, iclass 32, count 0 2006.197.07:34:42.25#ibcon#about to write, iclass 32, count 0 2006.197.07:34:42.25#ibcon#wrote, iclass 32, count 0 2006.197.07:34:42.25#ibcon#about to read 3, iclass 32, count 0 2006.197.07:34:42.27#ibcon#read 3, iclass 32, count 0 2006.197.07:34:42.27#ibcon#about to read 4, iclass 32, count 0 2006.197.07:34:42.27#ibcon#read 4, iclass 32, count 0 2006.197.07:34:42.27#ibcon#about to read 5, iclass 32, count 0 2006.197.07:34:42.27#ibcon#read 5, iclass 32, count 0 2006.197.07:34:42.27#ibcon#about to read 6, iclass 32, count 0 2006.197.07:34:42.27#ibcon#read 6, iclass 32, count 0 2006.197.07:34:42.27#ibcon#end of sib2, iclass 32, count 0 2006.197.07:34:42.27#ibcon#*mode == 0, iclass 32, count 0 2006.197.07:34:42.27#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.197.07:34:42.27#ibcon#[27=BW32\r\n] 2006.197.07:34:42.27#ibcon#*before write, iclass 32, count 0 2006.197.07:34:42.27#ibcon#enter sib2, iclass 32, count 0 2006.197.07:34:42.27#ibcon#flushed, iclass 32, count 0 2006.197.07:34:42.27#ibcon#about to write, iclass 32, count 0 2006.197.07:34:42.27#ibcon#wrote, iclass 32, count 0 2006.197.07:34:42.27#ibcon#about to read 3, iclass 32, count 0 2006.197.07:34:42.30#ibcon#read 3, iclass 32, count 0 2006.197.07:34:42.30#ibcon#about to read 4, iclass 32, count 0 2006.197.07:34:42.30#ibcon#read 4, iclass 32, count 0 2006.197.07:34:42.30#ibcon#about to read 5, iclass 32, count 0 2006.197.07:34:42.30#ibcon#read 5, iclass 32, count 0 2006.197.07:34:42.30#ibcon#about to read 6, iclass 32, count 0 2006.197.07:34:42.30#ibcon#read 6, iclass 32, count 0 2006.197.07:34:42.30#ibcon#end of sib2, iclass 32, count 0 2006.197.07:34:42.30#ibcon#*after write, iclass 32, count 0 2006.197.07:34:42.30#ibcon#*before return 0, iclass 32, count 0 2006.197.07:34:42.30#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.197.07:34:42.30#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.197.07:34:42.30#ibcon#about to clear, iclass 32 cls_cnt 0 2006.197.07:34:42.30#ibcon#cleared, iclass 32 cls_cnt 0 2006.197.07:34:42.30$4f8m12a/ifd4f 2006.197.07:34:42.30$ifd4f/lo= 2006.197.07:34:42.30$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.197.07:34:42.30$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.197.07:34:42.30$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.197.07:34:42.30$ifd4f/patch= 2006.197.07:34:42.30$ifd4f/patch=lo1,a1,a2,a3,a4 2006.197.07:34:42.30$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.197.07:34:42.30$ifd4f/patch=lo3,a5,a6,a7,a8 2006.197.07:34:42.30$4f8m12a/"form=m,16.000,1:2 2006.197.07:34:42.30$4f8m12a/"tpicd 2006.197.07:34:42.30$4f8m12a/echo=off 2006.197.07:34:42.30$4f8m12a/xlog=off 2006.197.07:34:42.30:!2006.197.07:35:10 2006.197.07:34:53.14#trakl#Source acquired 2006.197.07:34:55.14#flagr#flagr/antenna,acquired 2006.197.07:35:10.00:preob 2006.197.07:35:11.14/onsource/TRACKING 2006.197.07:35:11.14:!2006.197.07:35:20 2006.197.07:35:20.00:data_valid=on 2006.197.07:35:20.00:midob 2006.197.07:35:20.14/onsource/TRACKING 2006.197.07:35:20.14/wx/25.92,1003.0,97 2006.197.07:35:20.34/cable/+6.3723E-03 2006.197.07:35:21.43/va/01,08,usb,yes,29,31 2006.197.07:35:21.43/va/02,07,usb,yes,29,31 2006.197.07:35:21.43/va/03,06,usb,yes,31,31 2006.197.07:35:21.43/va/04,07,usb,yes,30,32 2006.197.07:35:21.43/va/05,07,usb,yes,34,35 2006.197.07:35:21.43/va/06,06,usb,yes,33,32 2006.197.07:35:21.43/va/07,06,usb,yes,33,33 2006.197.07:35:21.43/va/08,07,usb,yes,31,31 2006.197.07:35:21.66/valo/01,532.99,yes,locked 2006.197.07:35:21.66/valo/02,572.99,yes,locked 2006.197.07:35:21.66/valo/03,672.99,yes,locked 2006.197.07:35:21.66/valo/04,832.99,yes,locked 2006.197.07:35:21.66/valo/05,652.99,yes,locked 2006.197.07:35:21.66/valo/06,772.99,yes,locked 2006.197.07:35:21.66/valo/07,832.99,yes,locked 2006.197.07:35:21.66/valo/08,852.99,yes,locked 2006.197.07:35:22.75/vb/01,04,usb,yes,29,28 2006.197.07:35:22.75/vb/02,04,usb,yes,30,32 2006.197.07:35:22.75/vb/03,04,usb,yes,27,30 2006.197.07:35:22.75/vb/04,04,usb,yes,28,28 2006.197.07:35:22.75/vb/05,04,usb,yes,26,30 2006.197.07:35:22.75/vb/06,04,usb,yes,27,30 2006.197.07:35:22.75/vb/07,04,usb,yes,29,29 2006.197.07:35:22.75/vb/08,04,usb,yes,27,30 2006.197.07:35:22.98/vblo/01,632.99,yes,locked 2006.197.07:35:22.98/vblo/02,640.99,yes,locked 2006.197.07:35:22.98/vblo/03,656.99,yes,locked 2006.197.07:35:22.98/vblo/04,712.99,yes,locked 2006.197.07:35:22.98/vblo/05,744.99,yes,locked 2006.197.07:35:22.98/vblo/06,752.99,yes,locked 2006.197.07:35:22.98/vblo/07,734.99,yes,locked 2006.197.07:35:22.98/vblo/08,744.99,yes,locked 2006.197.07:35:23.13/vabw/8 2006.197.07:35:23.28/vbbw/8 2006.197.07:35:23.49/xfe/off,on,15.2 2006.197.07:35:23.86/ifatt/23,28,28,28 2006.197.07:35:24.10/fmout-gps/S +2.96E-07 2006.197.07:35:24.13:!2006.197.07:36:20 2006.197.07:36:20.00:data_valid=off 2006.197.07:36:20.00:postob 2006.197.07:36:20.13/cable/+6.3684E-03 2006.197.07:36:20.13/wx/25.92,1003.0,97 2006.197.07:36:21.09/fmout-gps/S +2.95E-07 2006.197.07:36:21.09:scan_name=197-0737,k06197,60 2006.197.07:36:21.09:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.197.07:36:21.14#flagr#flagr/antenna,new-source 2006.197.07:36:22.14:checkk5 2006.197.07:36:22.48/chk_autoobs//k5ts1/ autoobs is running! 2006.197.07:36:22.80/chk_autoobs//k5ts2/ autoobs is running! 2006.197.07:36:23.14/chk_autoobs//k5ts3/ autoobs is running! 2006.197.07:36:23.49/chk_autoobs//k5ts4/ autoobs is running! 2006.197.07:36:23.82/chk_obsdata//k5ts1/T1970735??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.07:36:24.15/chk_obsdata//k5ts2/T1970735??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.07:36:24.50/chk_obsdata//k5ts3/T1970735??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.07:36:24.83/chk_obsdata//k5ts4/T1970735??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.07:36:25.49/k5log//k5ts1_log_newline 2006.197.07:36:26.15/k5log//k5ts2_log_newline 2006.197.07:36:26.80/k5log//k5ts3_log_newline 2006.197.07:36:27.47/k5log//k5ts4_log_newline 2006.197.07:36:27.49/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.197.07:36:27.49:4f8m12a=1 2006.197.07:36:27.49$4f8m12a/echo=on 2006.197.07:36:27.49$4f8m12a/pcalon 2006.197.07:36:27.49$pcalon/"no phase cal control is implemented here 2006.197.07:36:27.49$4f8m12a/"tpicd=stop 2006.197.07:36:27.49$4f8m12a/vc4f8 2006.197.07:36:27.49$vc4f8/valo=1,532.99 2006.197.07:36:27.50#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.197.07:36:27.50#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.197.07:36:27.50#ibcon#ireg 17 cls_cnt 0 2006.197.07:36:27.50#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.197.07:36:27.50#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.197.07:36:27.50#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.197.07:36:27.50#ibcon#enter wrdev, iclass 39, count 0 2006.197.07:36:27.50#ibcon#first serial, iclass 39, count 0 2006.197.07:36:27.50#ibcon#enter sib2, iclass 39, count 0 2006.197.07:36:27.50#ibcon#flushed, iclass 39, count 0 2006.197.07:36:27.50#ibcon#about to write, iclass 39, count 0 2006.197.07:36:27.50#ibcon#wrote, iclass 39, count 0 2006.197.07:36:27.50#ibcon#about to read 3, iclass 39, count 0 2006.197.07:36:27.52#ibcon#read 3, iclass 39, count 0 2006.197.07:36:27.52#ibcon#about to read 4, iclass 39, count 0 2006.197.07:36:27.52#ibcon#read 4, iclass 39, count 0 2006.197.07:36:27.52#ibcon#about to read 5, iclass 39, count 0 2006.197.07:36:27.52#ibcon#read 5, iclass 39, count 0 2006.197.07:36:27.52#ibcon#about to read 6, iclass 39, count 0 2006.197.07:36:27.52#ibcon#read 6, iclass 39, count 0 2006.197.07:36:27.52#ibcon#end of sib2, iclass 39, count 0 2006.197.07:36:27.52#ibcon#*mode == 0, iclass 39, count 0 2006.197.07:36:27.52#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.197.07:36:27.52#ibcon#[26=FRQ=01,532.99\r\n] 2006.197.07:36:27.52#ibcon#*before write, iclass 39, count 0 2006.197.07:36:27.52#ibcon#enter sib2, iclass 39, count 0 2006.197.07:36:27.52#ibcon#flushed, iclass 39, count 0 2006.197.07:36:27.52#ibcon#about to write, iclass 39, count 0 2006.197.07:36:27.52#ibcon#wrote, iclass 39, count 0 2006.197.07:36:27.52#ibcon#about to read 3, iclass 39, count 0 2006.197.07:36:27.57#ibcon#read 3, iclass 39, count 0 2006.197.07:36:27.57#ibcon#about to read 4, iclass 39, count 0 2006.197.07:36:27.57#ibcon#read 4, iclass 39, count 0 2006.197.07:36:27.57#ibcon#about to read 5, iclass 39, count 0 2006.197.07:36:27.57#ibcon#read 5, iclass 39, count 0 2006.197.07:36:27.57#ibcon#about to read 6, iclass 39, count 0 2006.197.07:36:27.57#ibcon#read 6, iclass 39, count 0 2006.197.07:36:27.57#ibcon#end of sib2, iclass 39, count 0 2006.197.07:36:27.57#ibcon#*after write, iclass 39, count 0 2006.197.07:36:27.57#ibcon#*before return 0, iclass 39, count 0 2006.197.07:36:27.57#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.197.07:36:27.57#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.197.07:36:27.57#ibcon#about to clear, iclass 39 cls_cnt 0 2006.197.07:36:27.57#ibcon#cleared, iclass 39 cls_cnt 0 2006.197.07:36:27.57$vc4f8/va=1,8 2006.197.07:36:27.57#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.197.07:36:27.57#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.197.07:36:27.57#ibcon#ireg 11 cls_cnt 2 2006.197.07:36:27.57#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.197.07:36:27.57#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.197.07:36:27.57#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.197.07:36:27.57#ibcon#enter wrdev, iclass 3, count 2 2006.197.07:36:27.57#ibcon#first serial, iclass 3, count 2 2006.197.07:36:27.57#ibcon#enter sib2, iclass 3, count 2 2006.197.07:36:27.57#ibcon#flushed, iclass 3, count 2 2006.197.07:36:27.57#ibcon#about to write, iclass 3, count 2 2006.197.07:36:27.57#ibcon#wrote, iclass 3, count 2 2006.197.07:36:27.57#ibcon#about to read 3, iclass 3, count 2 2006.197.07:36:27.59#ibcon#read 3, iclass 3, count 2 2006.197.07:36:27.59#ibcon#about to read 4, iclass 3, count 2 2006.197.07:36:27.59#ibcon#read 4, iclass 3, count 2 2006.197.07:36:27.59#ibcon#about to read 5, iclass 3, count 2 2006.197.07:36:27.59#ibcon#read 5, iclass 3, count 2 2006.197.07:36:27.59#ibcon#about to read 6, iclass 3, count 2 2006.197.07:36:27.59#ibcon#read 6, iclass 3, count 2 2006.197.07:36:27.59#ibcon#end of sib2, iclass 3, count 2 2006.197.07:36:27.59#ibcon#*mode == 0, iclass 3, count 2 2006.197.07:36:27.59#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.197.07:36:27.59#ibcon#[25=AT01-08\r\n] 2006.197.07:36:27.59#ibcon#*before write, iclass 3, count 2 2006.197.07:36:27.59#ibcon#enter sib2, iclass 3, count 2 2006.197.07:36:27.59#ibcon#flushed, iclass 3, count 2 2006.197.07:36:27.59#ibcon#about to write, iclass 3, count 2 2006.197.07:36:27.59#ibcon#wrote, iclass 3, count 2 2006.197.07:36:27.59#ibcon#about to read 3, iclass 3, count 2 2006.197.07:36:27.62#ibcon#read 3, iclass 3, count 2 2006.197.07:36:27.62#ibcon#about to read 4, iclass 3, count 2 2006.197.07:36:27.62#ibcon#read 4, iclass 3, count 2 2006.197.07:36:27.62#ibcon#about to read 5, iclass 3, count 2 2006.197.07:36:27.62#ibcon#read 5, iclass 3, count 2 2006.197.07:36:27.62#ibcon#about to read 6, iclass 3, count 2 2006.197.07:36:27.62#ibcon#read 6, iclass 3, count 2 2006.197.07:36:27.62#ibcon#end of sib2, iclass 3, count 2 2006.197.07:36:27.62#ibcon#*after write, iclass 3, count 2 2006.197.07:36:27.62#ibcon#*before return 0, iclass 3, count 2 2006.197.07:36:27.62#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.197.07:36:27.62#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.197.07:36:27.62#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.197.07:36:27.62#ibcon#ireg 7 cls_cnt 0 2006.197.07:36:27.62#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.197.07:36:27.74#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.197.07:36:27.74#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.197.07:36:27.74#ibcon#enter wrdev, iclass 3, count 0 2006.197.07:36:27.74#ibcon#first serial, iclass 3, count 0 2006.197.07:36:27.74#ibcon#enter sib2, iclass 3, count 0 2006.197.07:36:27.74#ibcon#flushed, iclass 3, count 0 2006.197.07:36:27.74#ibcon#about to write, iclass 3, count 0 2006.197.07:36:27.74#ibcon#wrote, iclass 3, count 0 2006.197.07:36:27.74#ibcon#about to read 3, iclass 3, count 0 2006.197.07:36:27.76#ibcon#read 3, iclass 3, count 0 2006.197.07:36:27.76#ibcon#about to read 4, iclass 3, count 0 2006.197.07:36:27.76#ibcon#read 4, iclass 3, count 0 2006.197.07:36:27.76#ibcon#about to read 5, iclass 3, count 0 2006.197.07:36:27.76#ibcon#read 5, iclass 3, count 0 2006.197.07:36:27.76#ibcon#about to read 6, iclass 3, count 0 2006.197.07:36:27.76#ibcon#read 6, iclass 3, count 0 2006.197.07:36:27.76#ibcon#end of sib2, iclass 3, count 0 2006.197.07:36:27.76#ibcon#*mode == 0, iclass 3, count 0 2006.197.07:36:27.76#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.197.07:36:27.76#ibcon#[25=USB\r\n] 2006.197.07:36:27.76#ibcon#*before write, iclass 3, count 0 2006.197.07:36:27.76#ibcon#enter sib2, iclass 3, count 0 2006.197.07:36:27.76#ibcon#flushed, iclass 3, count 0 2006.197.07:36:27.76#ibcon#about to write, iclass 3, count 0 2006.197.07:36:27.76#ibcon#wrote, iclass 3, count 0 2006.197.07:36:27.76#ibcon#about to read 3, iclass 3, count 0 2006.197.07:36:27.79#ibcon#read 3, iclass 3, count 0 2006.197.07:36:27.79#ibcon#about to read 4, iclass 3, count 0 2006.197.07:36:27.79#ibcon#read 4, iclass 3, count 0 2006.197.07:36:27.79#ibcon#about to read 5, iclass 3, count 0 2006.197.07:36:27.79#ibcon#read 5, iclass 3, count 0 2006.197.07:36:27.79#ibcon#about to read 6, iclass 3, count 0 2006.197.07:36:27.79#ibcon#read 6, iclass 3, count 0 2006.197.07:36:27.79#ibcon#end of sib2, iclass 3, count 0 2006.197.07:36:27.79#ibcon#*after write, iclass 3, count 0 2006.197.07:36:27.79#ibcon#*before return 0, iclass 3, count 0 2006.197.07:36:27.79#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.197.07:36:27.79#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.197.07:36:27.79#ibcon#about to clear, iclass 3 cls_cnt 0 2006.197.07:36:27.79#ibcon#cleared, iclass 3 cls_cnt 0 2006.197.07:36:27.79$vc4f8/valo=2,572.99 2006.197.07:36:27.79#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.197.07:36:27.79#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.197.07:36:27.79#ibcon#ireg 17 cls_cnt 0 2006.197.07:36:27.79#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.197.07:36:27.79#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.197.07:36:27.79#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.197.07:36:27.79#ibcon#enter wrdev, iclass 5, count 0 2006.197.07:36:27.79#ibcon#first serial, iclass 5, count 0 2006.197.07:36:27.79#ibcon#enter sib2, iclass 5, count 0 2006.197.07:36:27.79#ibcon#flushed, iclass 5, count 0 2006.197.07:36:27.79#ibcon#about to write, iclass 5, count 0 2006.197.07:36:27.79#ibcon#wrote, iclass 5, count 0 2006.197.07:36:27.79#ibcon#about to read 3, iclass 5, count 0 2006.197.07:36:27.81#ibcon#read 3, iclass 5, count 0 2006.197.07:36:27.81#ibcon#about to read 4, iclass 5, count 0 2006.197.07:36:27.81#ibcon#read 4, iclass 5, count 0 2006.197.07:36:27.81#ibcon#about to read 5, iclass 5, count 0 2006.197.07:36:27.81#ibcon#read 5, iclass 5, count 0 2006.197.07:36:27.81#ibcon#about to read 6, iclass 5, count 0 2006.197.07:36:27.81#ibcon#read 6, iclass 5, count 0 2006.197.07:36:27.81#ibcon#end of sib2, iclass 5, count 0 2006.197.07:36:27.81#ibcon#*mode == 0, iclass 5, count 0 2006.197.07:36:27.81#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.197.07:36:27.81#ibcon#[26=FRQ=02,572.99\r\n] 2006.197.07:36:27.81#ibcon#*before write, iclass 5, count 0 2006.197.07:36:27.81#ibcon#enter sib2, iclass 5, count 0 2006.197.07:36:27.81#ibcon#flushed, iclass 5, count 0 2006.197.07:36:27.81#ibcon#about to write, iclass 5, count 0 2006.197.07:36:27.81#ibcon#wrote, iclass 5, count 0 2006.197.07:36:27.81#ibcon#about to read 3, iclass 5, count 0 2006.197.07:36:27.85#ibcon#read 3, iclass 5, count 0 2006.197.07:36:27.85#ibcon#about to read 4, iclass 5, count 0 2006.197.07:36:27.85#ibcon#read 4, iclass 5, count 0 2006.197.07:36:27.85#ibcon#about to read 5, iclass 5, count 0 2006.197.07:36:27.85#ibcon#read 5, iclass 5, count 0 2006.197.07:36:27.85#ibcon#about to read 6, iclass 5, count 0 2006.197.07:36:27.85#ibcon#read 6, iclass 5, count 0 2006.197.07:36:27.85#ibcon#end of sib2, iclass 5, count 0 2006.197.07:36:27.85#ibcon#*after write, iclass 5, count 0 2006.197.07:36:27.85#ibcon#*before return 0, iclass 5, count 0 2006.197.07:36:27.85#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.197.07:36:27.85#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.197.07:36:27.85#ibcon#about to clear, iclass 5 cls_cnt 0 2006.197.07:36:27.85#ibcon#cleared, iclass 5 cls_cnt 0 2006.197.07:36:27.85$vc4f8/va=2,7 2006.197.07:36:27.85#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.197.07:36:27.85#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.197.07:36:27.85#ibcon#ireg 11 cls_cnt 2 2006.197.07:36:27.85#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.197.07:36:27.91#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.197.07:36:27.91#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.197.07:36:27.91#ibcon#enter wrdev, iclass 7, count 2 2006.197.07:36:27.91#ibcon#first serial, iclass 7, count 2 2006.197.07:36:27.91#ibcon#enter sib2, iclass 7, count 2 2006.197.07:36:27.91#ibcon#flushed, iclass 7, count 2 2006.197.07:36:27.91#ibcon#about to write, iclass 7, count 2 2006.197.07:36:27.91#ibcon#wrote, iclass 7, count 2 2006.197.07:36:27.91#ibcon#about to read 3, iclass 7, count 2 2006.197.07:36:27.93#ibcon#read 3, iclass 7, count 2 2006.197.07:36:27.93#ibcon#about to read 4, iclass 7, count 2 2006.197.07:36:27.93#ibcon#read 4, iclass 7, count 2 2006.197.07:36:27.93#ibcon#about to read 5, iclass 7, count 2 2006.197.07:36:27.93#ibcon#read 5, iclass 7, count 2 2006.197.07:36:27.93#ibcon#about to read 6, iclass 7, count 2 2006.197.07:36:27.93#ibcon#read 6, iclass 7, count 2 2006.197.07:36:27.93#ibcon#end of sib2, iclass 7, count 2 2006.197.07:36:27.93#ibcon#*mode == 0, iclass 7, count 2 2006.197.07:36:27.93#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.197.07:36:27.93#ibcon#[25=AT02-07\r\n] 2006.197.07:36:27.93#ibcon#*before write, iclass 7, count 2 2006.197.07:36:27.93#ibcon#enter sib2, iclass 7, count 2 2006.197.07:36:27.93#ibcon#flushed, iclass 7, count 2 2006.197.07:36:27.93#ibcon#about to write, iclass 7, count 2 2006.197.07:36:27.93#ibcon#wrote, iclass 7, count 2 2006.197.07:36:27.93#ibcon#about to read 3, iclass 7, count 2 2006.197.07:36:27.96#ibcon#read 3, iclass 7, count 2 2006.197.07:36:27.96#ibcon#about to read 4, iclass 7, count 2 2006.197.07:36:27.96#ibcon#read 4, iclass 7, count 2 2006.197.07:36:27.96#ibcon#about to read 5, iclass 7, count 2 2006.197.07:36:27.96#ibcon#read 5, iclass 7, count 2 2006.197.07:36:27.96#ibcon#about to read 6, iclass 7, count 2 2006.197.07:36:27.96#ibcon#read 6, iclass 7, count 2 2006.197.07:36:27.96#ibcon#end of sib2, iclass 7, count 2 2006.197.07:36:27.96#ibcon#*after write, iclass 7, count 2 2006.197.07:36:27.96#ibcon#*before return 0, iclass 7, count 2 2006.197.07:36:27.96#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.197.07:36:27.96#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.197.07:36:27.96#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.197.07:36:27.96#ibcon#ireg 7 cls_cnt 0 2006.197.07:36:27.96#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.197.07:36:28.08#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.197.07:36:28.08#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.197.07:36:28.08#ibcon#enter wrdev, iclass 7, count 0 2006.197.07:36:28.08#ibcon#first serial, iclass 7, count 0 2006.197.07:36:28.08#ibcon#enter sib2, iclass 7, count 0 2006.197.07:36:28.08#ibcon#flushed, iclass 7, count 0 2006.197.07:36:28.08#ibcon#about to write, iclass 7, count 0 2006.197.07:36:28.08#ibcon#wrote, iclass 7, count 0 2006.197.07:36:28.08#ibcon#about to read 3, iclass 7, count 0 2006.197.07:36:28.10#ibcon#read 3, iclass 7, count 0 2006.197.07:36:28.10#ibcon#about to read 4, iclass 7, count 0 2006.197.07:36:28.10#ibcon#read 4, iclass 7, count 0 2006.197.07:36:28.10#ibcon#about to read 5, iclass 7, count 0 2006.197.07:36:28.10#ibcon#read 5, iclass 7, count 0 2006.197.07:36:28.10#ibcon#about to read 6, iclass 7, count 0 2006.197.07:36:28.10#ibcon#read 6, iclass 7, count 0 2006.197.07:36:28.10#ibcon#end of sib2, iclass 7, count 0 2006.197.07:36:28.10#ibcon#*mode == 0, iclass 7, count 0 2006.197.07:36:28.10#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.197.07:36:28.10#ibcon#[25=USB\r\n] 2006.197.07:36:28.10#ibcon#*before write, iclass 7, count 0 2006.197.07:36:28.10#ibcon#enter sib2, iclass 7, count 0 2006.197.07:36:28.10#ibcon#flushed, iclass 7, count 0 2006.197.07:36:28.10#ibcon#about to write, iclass 7, count 0 2006.197.07:36:28.10#ibcon#wrote, iclass 7, count 0 2006.197.07:36:28.10#ibcon#about to read 3, iclass 7, count 0 2006.197.07:36:28.13#ibcon#read 3, iclass 7, count 0 2006.197.07:36:28.13#ibcon#about to read 4, iclass 7, count 0 2006.197.07:36:28.13#ibcon#read 4, iclass 7, count 0 2006.197.07:36:28.13#ibcon#about to read 5, iclass 7, count 0 2006.197.07:36:28.13#ibcon#read 5, iclass 7, count 0 2006.197.07:36:28.13#ibcon#about to read 6, iclass 7, count 0 2006.197.07:36:28.13#ibcon#read 6, iclass 7, count 0 2006.197.07:36:28.13#ibcon#end of sib2, iclass 7, count 0 2006.197.07:36:28.13#ibcon#*after write, iclass 7, count 0 2006.197.07:36:28.13#ibcon#*before return 0, iclass 7, count 0 2006.197.07:36:28.13#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.197.07:36:28.13#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.197.07:36:28.13#ibcon#about to clear, iclass 7 cls_cnt 0 2006.197.07:36:28.13#ibcon#cleared, iclass 7 cls_cnt 0 2006.197.07:36:28.13$vc4f8/valo=3,672.99 2006.197.07:36:28.13#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.197.07:36:28.13#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.197.07:36:28.13#ibcon#ireg 17 cls_cnt 0 2006.197.07:36:28.13#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.197.07:36:28.13#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.197.07:36:28.13#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.197.07:36:28.13#ibcon#enter wrdev, iclass 11, count 0 2006.197.07:36:28.13#ibcon#first serial, iclass 11, count 0 2006.197.07:36:28.13#ibcon#enter sib2, iclass 11, count 0 2006.197.07:36:28.13#ibcon#flushed, iclass 11, count 0 2006.197.07:36:28.13#ibcon#about to write, iclass 11, count 0 2006.197.07:36:28.13#ibcon#wrote, iclass 11, count 0 2006.197.07:36:28.13#ibcon#about to read 3, iclass 11, count 0 2006.197.07:36:28.15#ibcon#read 3, iclass 11, count 0 2006.197.07:36:28.15#ibcon#about to read 4, iclass 11, count 0 2006.197.07:36:28.15#ibcon#read 4, iclass 11, count 0 2006.197.07:36:28.15#ibcon#about to read 5, iclass 11, count 0 2006.197.07:36:28.15#ibcon#read 5, iclass 11, count 0 2006.197.07:36:28.15#ibcon#about to read 6, iclass 11, count 0 2006.197.07:36:28.15#ibcon#read 6, iclass 11, count 0 2006.197.07:36:28.15#ibcon#end of sib2, iclass 11, count 0 2006.197.07:36:28.15#ibcon#*mode == 0, iclass 11, count 0 2006.197.07:36:28.15#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.197.07:36:28.15#ibcon#[26=FRQ=03,672.99\r\n] 2006.197.07:36:28.15#ibcon#*before write, iclass 11, count 0 2006.197.07:36:28.15#ibcon#enter sib2, iclass 11, count 0 2006.197.07:36:28.15#ibcon#flushed, iclass 11, count 0 2006.197.07:36:28.15#ibcon#about to write, iclass 11, count 0 2006.197.07:36:28.15#ibcon#wrote, iclass 11, count 0 2006.197.07:36:28.15#ibcon#about to read 3, iclass 11, count 0 2006.197.07:36:28.19#ibcon#read 3, iclass 11, count 0 2006.197.07:36:28.19#ibcon#about to read 4, iclass 11, count 0 2006.197.07:36:28.19#ibcon#read 4, iclass 11, count 0 2006.197.07:36:28.19#ibcon#about to read 5, iclass 11, count 0 2006.197.07:36:28.19#ibcon#read 5, iclass 11, count 0 2006.197.07:36:28.19#ibcon#about to read 6, iclass 11, count 0 2006.197.07:36:28.19#ibcon#read 6, iclass 11, count 0 2006.197.07:36:28.19#ibcon#end of sib2, iclass 11, count 0 2006.197.07:36:28.19#ibcon#*after write, iclass 11, count 0 2006.197.07:36:28.19#ibcon#*before return 0, iclass 11, count 0 2006.197.07:36:28.19#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.197.07:36:28.19#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.197.07:36:28.19#ibcon#about to clear, iclass 11 cls_cnt 0 2006.197.07:36:28.19#ibcon#cleared, iclass 11 cls_cnt 0 2006.197.07:36:28.19$vc4f8/va=3,6 2006.197.07:36:28.19#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.197.07:36:28.19#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.197.07:36:28.19#ibcon#ireg 11 cls_cnt 2 2006.197.07:36:28.19#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.197.07:36:28.25#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.197.07:36:28.25#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.197.07:36:28.25#ibcon#enter wrdev, iclass 13, count 2 2006.197.07:36:28.25#ibcon#first serial, iclass 13, count 2 2006.197.07:36:28.25#ibcon#enter sib2, iclass 13, count 2 2006.197.07:36:28.25#ibcon#flushed, iclass 13, count 2 2006.197.07:36:28.25#ibcon#about to write, iclass 13, count 2 2006.197.07:36:28.25#ibcon#wrote, iclass 13, count 2 2006.197.07:36:28.25#ibcon#about to read 3, iclass 13, count 2 2006.197.07:36:28.27#ibcon#read 3, iclass 13, count 2 2006.197.07:36:28.27#ibcon#about to read 4, iclass 13, count 2 2006.197.07:36:28.27#ibcon#read 4, iclass 13, count 2 2006.197.07:36:28.27#ibcon#about to read 5, iclass 13, count 2 2006.197.07:36:28.27#ibcon#read 5, iclass 13, count 2 2006.197.07:36:28.27#ibcon#about to read 6, iclass 13, count 2 2006.197.07:36:28.27#ibcon#read 6, iclass 13, count 2 2006.197.07:36:28.27#ibcon#end of sib2, iclass 13, count 2 2006.197.07:36:28.27#ibcon#*mode == 0, iclass 13, count 2 2006.197.07:36:28.27#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.197.07:36:28.27#ibcon#[25=AT03-06\r\n] 2006.197.07:36:28.27#ibcon#*before write, iclass 13, count 2 2006.197.07:36:28.27#ibcon#enter sib2, iclass 13, count 2 2006.197.07:36:28.27#ibcon#flushed, iclass 13, count 2 2006.197.07:36:28.27#ibcon#about to write, iclass 13, count 2 2006.197.07:36:28.27#ibcon#wrote, iclass 13, count 2 2006.197.07:36:28.27#ibcon#about to read 3, iclass 13, count 2 2006.197.07:36:28.30#ibcon#read 3, iclass 13, count 2 2006.197.07:36:28.30#ibcon#about to read 4, iclass 13, count 2 2006.197.07:36:28.30#ibcon#read 4, iclass 13, count 2 2006.197.07:36:28.30#ibcon#about to read 5, iclass 13, count 2 2006.197.07:36:28.30#ibcon#read 5, iclass 13, count 2 2006.197.07:36:28.30#ibcon#about to read 6, iclass 13, count 2 2006.197.07:36:28.30#ibcon#read 6, iclass 13, count 2 2006.197.07:36:28.30#ibcon#end of sib2, iclass 13, count 2 2006.197.07:36:28.30#ibcon#*after write, iclass 13, count 2 2006.197.07:36:28.30#ibcon#*before return 0, iclass 13, count 2 2006.197.07:36:28.30#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.197.07:36:28.30#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.197.07:36:28.30#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.197.07:36:28.30#ibcon#ireg 7 cls_cnt 0 2006.197.07:36:28.30#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.197.07:36:28.42#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.197.07:36:28.42#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.197.07:36:28.42#ibcon#enter wrdev, iclass 13, count 0 2006.197.07:36:28.42#ibcon#first serial, iclass 13, count 0 2006.197.07:36:28.42#ibcon#enter sib2, iclass 13, count 0 2006.197.07:36:28.42#ibcon#flushed, iclass 13, count 0 2006.197.07:36:28.42#ibcon#about to write, iclass 13, count 0 2006.197.07:36:28.42#ibcon#wrote, iclass 13, count 0 2006.197.07:36:28.42#ibcon#about to read 3, iclass 13, count 0 2006.197.07:36:28.44#ibcon#read 3, iclass 13, count 0 2006.197.07:36:28.44#ibcon#about to read 4, iclass 13, count 0 2006.197.07:36:28.44#ibcon#read 4, iclass 13, count 0 2006.197.07:36:28.44#ibcon#about to read 5, iclass 13, count 0 2006.197.07:36:28.44#ibcon#read 5, iclass 13, count 0 2006.197.07:36:28.44#ibcon#about to read 6, iclass 13, count 0 2006.197.07:36:28.44#ibcon#read 6, iclass 13, count 0 2006.197.07:36:28.44#ibcon#end of sib2, iclass 13, count 0 2006.197.07:36:28.44#ibcon#*mode == 0, iclass 13, count 0 2006.197.07:36:28.44#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.197.07:36:28.44#ibcon#[25=USB\r\n] 2006.197.07:36:28.44#ibcon#*before write, iclass 13, count 0 2006.197.07:36:28.44#ibcon#enter sib2, iclass 13, count 0 2006.197.07:36:28.44#ibcon#flushed, iclass 13, count 0 2006.197.07:36:28.44#ibcon#about to write, iclass 13, count 0 2006.197.07:36:28.44#ibcon#wrote, iclass 13, count 0 2006.197.07:36:28.44#ibcon#about to read 3, iclass 13, count 0 2006.197.07:36:28.47#ibcon#read 3, iclass 13, count 0 2006.197.07:36:28.47#ibcon#about to read 4, iclass 13, count 0 2006.197.07:36:28.47#ibcon#read 4, iclass 13, count 0 2006.197.07:36:28.47#ibcon#about to read 5, iclass 13, count 0 2006.197.07:36:28.47#ibcon#read 5, iclass 13, count 0 2006.197.07:36:28.47#ibcon#about to read 6, iclass 13, count 0 2006.197.07:36:28.47#ibcon#read 6, iclass 13, count 0 2006.197.07:36:28.47#ibcon#end of sib2, iclass 13, count 0 2006.197.07:36:28.47#ibcon#*after write, iclass 13, count 0 2006.197.07:36:28.47#ibcon#*before return 0, iclass 13, count 0 2006.197.07:36:28.47#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.197.07:36:28.47#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.197.07:36:28.47#ibcon#about to clear, iclass 13 cls_cnt 0 2006.197.07:36:28.47#ibcon#cleared, iclass 13 cls_cnt 0 2006.197.07:36:28.47$vc4f8/valo=4,832.99 2006.197.07:36:28.47#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.197.07:36:28.47#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.197.07:36:28.47#ibcon#ireg 17 cls_cnt 0 2006.197.07:36:28.47#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.197.07:36:28.47#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.197.07:36:28.47#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.197.07:36:28.47#ibcon#enter wrdev, iclass 15, count 0 2006.197.07:36:28.47#ibcon#first serial, iclass 15, count 0 2006.197.07:36:28.47#ibcon#enter sib2, iclass 15, count 0 2006.197.07:36:28.47#ibcon#flushed, iclass 15, count 0 2006.197.07:36:28.47#ibcon#about to write, iclass 15, count 0 2006.197.07:36:28.47#ibcon#wrote, iclass 15, count 0 2006.197.07:36:28.47#ibcon#about to read 3, iclass 15, count 0 2006.197.07:36:28.49#ibcon#read 3, iclass 15, count 0 2006.197.07:36:28.49#ibcon#about to read 4, iclass 15, count 0 2006.197.07:36:28.49#ibcon#read 4, iclass 15, count 0 2006.197.07:36:28.49#ibcon#about to read 5, iclass 15, count 0 2006.197.07:36:28.49#ibcon#read 5, iclass 15, count 0 2006.197.07:36:28.49#ibcon#about to read 6, iclass 15, count 0 2006.197.07:36:28.49#ibcon#read 6, iclass 15, count 0 2006.197.07:36:28.49#ibcon#end of sib2, iclass 15, count 0 2006.197.07:36:28.49#ibcon#*mode == 0, iclass 15, count 0 2006.197.07:36:28.49#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.197.07:36:28.49#ibcon#[26=FRQ=04,832.99\r\n] 2006.197.07:36:28.49#ibcon#*before write, iclass 15, count 0 2006.197.07:36:28.49#ibcon#enter sib2, iclass 15, count 0 2006.197.07:36:28.49#ibcon#flushed, iclass 15, count 0 2006.197.07:36:28.49#ibcon#about to write, iclass 15, count 0 2006.197.07:36:28.49#ibcon#wrote, iclass 15, count 0 2006.197.07:36:28.49#ibcon#about to read 3, iclass 15, count 0 2006.197.07:36:28.53#ibcon#read 3, iclass 15, count 0 2006.197.07:36:28.53#ibcon#about to read 4, iclass 15, count 0 2006.197.07:36:28.53#ibcon#read 4, iclass 15, count 0 2006.197.07:36:28.53#ibcon#about to read 5, iclass 15, count 0 2006.197.07:36:28.53#ibcon#read 5, iclass 15, count 0 2006.197.07:36:28.53#ibcon#about to read 6, iclass 15, count 0 2006.197.07:36:28.53#ibcon#read 6, iclass 15, count 0 2006.197.07:36:28.53#ibcon#end of sib2, iclass 15, count 0 2006.197.07:36:28.53#ibcon#*after write, iclass 15, count 0 2006.197.07:36:28.53#ibcon#*before return 0, iclass 15, count 0 2006.197.07:36:28.53#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.197.07:36:28.53#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.197.07:36:28.53#ibcon#about to clear, iclass 15 cls_cnt 0 2006.197.07:36:28.53#ibcon#cleared, iclass 15 cls_cnt 0 2006.197.07:36:28.53$vc4f8/va=4,7 2006.197.07:36:28.53#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.197.07:36:28.53#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.197.07:36:28.53#ibcon#ireg 11 cls_cnt 2 2006.197.07:36:28.53#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.197.07:36:28.59#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.197.07:36:28.59#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.197.07:36:28.59#ibcon#enter wrdev, iclass 17, count 2 2006.197.07:36:28.59#ibcon#first serial, iclass 17, count 2 2006.197.07:36:28.59#ibcon#enter sib2, iclass 17, count 2 2006.197.07:36:28.59#ibcon#flushed, iclass 17, count 2 2006.197.07:36:28.59#ibcon#about to write, iclass 17, count 2 2006.197.07:36:28.59#ibcon#wrote, iclass 17, count 2 2006.197.07:36:28.59#ibcon#about to read 3, iclass 17, count 2 2006.197.07:36:28.61#ibcon#read 3, iclass 17, count 2 2006.197.07:36:28.61#ibcon#about to read 4, iclass 17, count 2 2006.197.07:36:28.61#ibcon#read 4, iclass 17, count 2 2006.197.07:36:28.61#ibcon#about to read 5, iclass 17, count 2 2006.197.07:36:28.61#ibcon#read 5, iclass 17, count 2 2006.197.07:36:28.61#ibcon#about to read 6, iclass 17, count 2 2006.197.07:36:28.61#ibcon#read 6, iclass 17, count 2 2006.197.07:36:28.61#ibcon#end of sib2, iclass 17, count 2 2006.197.07:36:28.61#ibcon#*mode == 0, iclass 17, count 2 2006.197.07:36:28.61#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.197.07:36:28.61#ibcon#[25=AT04-07\r\n] 2006.197.07:36:28.61#ibcon#*before write, iclass 17, count 2 2006.197.07:36:28.61#ibcon#enter sib2, iclass 17, count 2 2006.197.07:36:28.61#ibcon#flushed, iclass 17, count 2 2006.197.07:36:28.61#ibcon#about to write, iclass 17, count 2 2006.197.07:36:28.61#ibcon#wrote, iclass 17, count 2 2006.197.07:36:28.61#ibcon#about to read 3, iclass 17, count 2 2006.197.07:36:28.64#ibcon#read 3, iclass 17, count 2 2006.197.07:36:28.64#ibcon#about to read 4, iclass 17, count 2 2006.197.07:36:28.64#ibcon#read 4, iclass 17, count 2 2006.197.07:36:28.64#ibcon#about to read 5, iclass 17, count 2 2006.197.07:36:28.64#ibcon#read 5, iclass 17, count 2 2006.197.07:36:28.64#ibcon#about to read 6, iclass 17, count 2 2006.197.07:36:28.64#ibcon#read 6, iclass 17, count 2 2006.197.07:36:28.64#ibcon#end of sib2, iclass 17, count 2 2006.197.07:36:28.64#ibcon#*after write, iclass 17, count 2 2006.197.07:36:28.64#ibcon#*before return 0, iclass 17, count 2 2006.197.07:36:28.64#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.197.07:36:28.64#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.197.07:36:28.64#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.197.07:36:28.64#ibcon#ireg 7 cls_cnt 0 2006.197.07:36:28.64#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.197.07:36:28.76#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.197.07:36:28.76#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.197.07:36:28.76#ibcon#enter wrdev, iclass 17, count 0 2006.197.07:36:28.76#ibcon#first serial, iclass 17, count 0 2006.197.07:36:28.76#ibcon#enter sib2, iclass 17, count 0 2006.197.07:36:28.76#ibcon#flushed, iclass 17, count 0 2006.197.07:36:28.76#ibcon#about to write, iclass 17, count 0 2006.197.07:36:28.76#ibcon#wrote, iclass 17, count 0 2006.197.07:36:28.76#ibcon#about to read 3, iclass 17, count 0 2006.197.07:36:28.78#ibcon#read 3, iclass 17, count 0 2006.197.07:36:28.78#ibcon#about to read 4, iclass 17, count 0 2006.197.07:36:28.78#ibcon#read 4, iclass 17, count 0 2006.197.07:36:28.78#ibcon#about to read 5, iclass 17, count 0 2006.197.07:36:28.78#ibcon#read 5, iclass 17, count 0 2006.197.07:36:28.78#ibcon#about to read 6, iclass 17, count 0 2006.197.07:36:28.78#ibcon#read 6, iclass 17, count 0 2006.197.07:36:28.78#ibcon#end of sib2, iclass 17, count 0 2006.197.07:36:28.78#ibcon#*mode == 0, iclass 17, count 0 2006.197.07:36:28.78#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.197.07:36:28.78#ibcon#[25=USB\r\n] 2006.197.07:36:28.78#ibcon#*before write, iclass 17, count 0 2006.197.07:36:28.78#ibcon#enter sib2, iclass 17, count 0 2006.197.07:36:28.78#ibcon#flushed, iclass 17, count 0 2006.197.07:36:28.78#ibcon#about to write, iclass 17, count 0 2006.197.07:36:28.78#ibcon#wrote, iclass 17, count 0 2006.197.07:36:28.78#ibcon#about to read 3, iclass 17, count 0 2006.197.07:36:28.81#ibcon#read 3, iclass 17, count 0 2006.197.07:36:28.81#ibcon#about to read 4, iclass 17, count 0 2006.197.07:36:28.81#ibcon#read 4, iclass 17, count 0 2006.197.07:36:28.81#ibcon#about to read 5, iclass 17, count 0 2006.197.07:36:28.81#ibcon#read 5, iclass 17, count 0 2006.197.07:36:28.81#ibcon#about to read 6, iclass 17, count 0 2006.197.07:36:28.81#ibcon#read 6, iclass 17, count 0 2006.197.07:36:28.81#ibcon#end of sib2, iclass 17, count 0 2006.197.07:36:28.81#ibcon#*after write, iclass 17, count 0 2006.197.07:36:28.81#ibcon#*before return 0, iclass 17, count 0 2006.197.07:36:28.81#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.197.07:36:28.81#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.197.07:36:28.81#ibcon#about to clear, iclass 17 cls_cnt 0 2006.197.07:36:28.81#ibcon#cleared, iclass 17 cls_cnt 0 2006.197.07:36:28.81$vc4f8/valo=5,652.99 2006.197.07:36:28.81#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.197.07:36:28.81#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.197.07:36:28.81#ibcon#ireg 17 cls_cnt 0 2006.197.07:36:28.81#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.197.07:36:28.81#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.197.07:36:28.81#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.197.07:36:28.81#ibcon#enter wrdev, iclass 19, count 0 2006.197.07:36:28.81#ibcon#first serial, iclass 19, count 0 2006.197.07:36:28.81#ibcon#enter sib2, iclass 19, count 0 2006.197.07:36:28.81#ibcon#flushed, iclass 19, count 0 2006.197.07:36:28.81#ibcon#about to write, iclass 19, count 0 2006.197.07:36:28.81#ibcon#wrote, iclass 19, count 0 2006.197.07:36:28.81#ibcon#about to read 3, iclass 19, count 0 2006.197.07:36:28.83#ibcon#read 3, iclass 19, count 0 2006.197.07:36:28.83#ibcon#about to read 4, iclass 19, count 0 2006.197.07:36:28.83#ibcon#read 4, iclass 19, count 0 2006.197.07:36:28.83#ibcon#about to read 5, iclass 19, count 0 2006.197.07:36:28.83#ibcon#read 5, iclass 19, count 0 2006.197.07:36:28.83#ibcon#about to read 6, iclass 19, count 0 2006.197.07:36:28.83#ibcon#read 6, iclass 19, count 0 2006.197.07:36:28.83#ibcon#end of sib2, iclass 19, count 0 2006.197.07:36:28.83#ibcon#*mode == 0, iclass 19, count 0 2006.197.07:36:28.83#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.197.07:36:28.83#ibcon#[26=FRQ=05,652.99\r\n] 2006.197.07:36:28.83#ibcon#*before write, iclass 19, count 0 2006.197.07:36:28.83#ibcon#enter sib2, iclass 19, count 0 2006.197.07:36:28.83#ibcon#flushed, iclass 19, count 0 2006.197.07:36:28.83#ibcon#about to write, iclass 19, count 0 2006.197.07:36:28.83#ibcon#wrote, iclass 19, count 0 2006.197.07:36:28.83#ibcon#about to read 3, iclass 19, count 0 2006.197.07:36:28.87#ibcon#read 3, iclass 19, count 0 2006.197.07:36:28.87#ibcon#about to read 4, iclass 19, count 0 2006.197.07:36:28.87#ibcon#read 4, iclass 19, count 0 2006.197.07:36:28.87#ibcon#about to read 5, iclass 19, count 0 2006.197.07:36:28.87#ibcon#read 5, iclass 19, count 0 2006.197.07:36:28.87#ibcon#about to read 6, iclass 19, count 0 2006.197.07:36:28.87#ibcon#read 6, iclass 19, count 0 2006.197.07:36:28.87#ibcon#end of sib2, iclass 19, count 0 2006.197.07:36:28.87#ibcon#*after write, iclass 19, count 0 2006.197.07:36:28.87#ibcon#*before return 0, iclass 19, count 0 2006.197.07:36:28.87#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.197.07:36:28.87#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.197.07:36:28.87#ibcon#about to clear, iclass 19 cls_cnt 0 2006.197.07:36:28.87#ibcon#cleared, iclass 19 cls_cnt 0 2006.197.07:36:28.87$vc4f8/va=5,7 2006.197.07:36:28.87#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.197.07:36:28.87#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.197.07:36:28.87#ibcon#ireg 11 cls_cnt 2 2006.197.07:36:28.87#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.197.07:36:28.93#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.197.07:36:28.93#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.197.07:36:28.93#ibcon#enter wrdev, iclass 21, count 2 2006.197.07:36:28.93#ibcon#first serial, iclass 21, count 2 2006.197.07:36:28.93#ibcon#enter sib2, iclass 21, count 2 2006.197.07:36:28.93#ibcon#flushed, iclass 21, count 2 2006.197.07:36:28.93#ibcon#about to write, iclass 21, count 2 2006.197.07:36:28.93#ibcon#wrote, iclass 21, count 2 2006.197.07:36:28.93#ibcon#about to read 3, iclass 21, count 2 2006.197.07:36:28.95#ibcon#read 3, iclass 21, count 2 2006.197.07:36:28.95#ibcon#about to read 4, iclass 21, count 2 2006.197.07:36:28.95#ibcon#read 4, iclass 21, count 2 2006.197.07:36:28.95#ibcon#about to read 5, iclass 21, count 2 2006.197.07:36:28.95#ibcon#read 5, iclass 21, count 2 2006.197.07:36:28.95#ibcon#about to read 6, iclass 21, count 2 2006.197.07:36:28.95#ibcon#read 6, iclass 21, count 2 2006.197.07:36:28.95#ibcon#end of sib2, iclass 21, count 2 2006.197.07:36:28.95#ibcon#*mode == 0, iclass 21, count 2 2006.197.07:36:28.95#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.197.07:36:28.95#ibcon#[25=AT05-07\r\n] 2006.197.07:36:28.95#ibcon#*before write, iclass 21, count 2 2006.197.07:36:28.95#ibcon#enter sib2, iclass 21, count 2 2006.197.07:36:28.95#ibcon#flushed, iclass 21, count 2 2006.197.07:36:28.95#ibcon#about to write, iclass 21, count 2 2006.197.07:36:28.95#ibcon#wrote, iclass 21, count 2 2006.197.07:36:28.95#ibcon#about to read 3, iclass 21, count 2 2006.197.07:36:28.98#ibcon#read 3, iclass 21, count 2 2006.197.07:36:28.98#ibcon#about to read 4, iclass 21, count 2 2006.197.07:36:28.98#ibcon#read 4, iclass 21, count 2 2006.197.07:36:28.98#ibcon#about to read 5, iclass 21, count 2 2006.197.07:36:28.98#ibcon#read 5, iclass 21, count 2 2006.197.07:36:28.98#ibcon#about to read 6, iclass 21, count 2 2006.197.07:36:28.98#ibcon#read 6, iclass 21, count 2 2006.197.07:36:28.98#ibcon#end of sib2, iclass 21, count 2 2006.197.07:36:28.98#ibcon#*after write, iclass 21, count 2 2006.197.07:36:28.98#ibcon#*before return 0, iclass 21, count 2 2006.197.07:36:28.98#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.197.07:36:28.98#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.197.07:36:28.98#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.197.07:36:28.98#ibcon#ireg 7 cls_cnt 0 2006.197.07:36:28.98#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.197.07:36:29.10#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.197.07:36:29.10#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.197.07:36:29.10#ibcon#enter wrdev, iclass 21, count 0 2006.197.07:36:29.10#ibcon#first serial, iclass 21, count 0 2006.197.07:36:29.10#ibcon#enter sib2, iclass 21, count 0 2006.197.07:36:29.10#ibcon#flushed, iclass 21, count 0 2006.197.07:36:29.10#ibcon#about to write, iclass 21, count 0 2006.197.07:36:29.10#ibcon#wrote, iclass 21, count 0 2006.197.07:36:29.10#ibcon#about to read 3, iclass 21, count 0 2006.197.07:36:29.12#ibcon#read 3, iclass 21, count 0 2006.197.07:36:29.12#ibcon#about to read 4, iclass 21, count 0 2006.197.07:36:29.12#ibcon#read 4, iclass 21, count 0 2006.197.07:36:29.12#ibcon#about to read 5, iclass 21, count 0 2006.197.07:36:29.12#ibcon#read 5, iclass 21, count 0 2006.197.07:36:29.12#ibcon#about to read 6, iclass 21, count 0 2006.197.07:36:29.12#ibcon#read 6, iclass 21, count 0 2006.197.07:36:29.12#ibcon#end of sib2, iclass 21, count 0 2006.197.07:36:29.12#ibcon#*mode == 0, iclass 21, count 0 2006.197.07:36:29.12#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.197.07:36:29.12#ibcon#[25=USB\r\n] 2006.197.07:36:29.12#ibcon#*before write, iclass 21, count 0 2006.197.07:36:29.12#ibcon#enter sib2, iclass 21, count 0 2006.197.07:36:29.12#ibcon#flushed, iclass 21, count 0 2006.197.07:36:29.12#ibcon#about to write, iclass 21, count 0 2006.197.07:36:29.12#ibcon#wrote, iclass 21, count 0 2006.197.07:36:29.12#ibcon#about to read 3, iclass 21, count 0 2006.197.07:36:29.15#ibcon#read 3, iclass 21, count 0 2006.197.07:36:29.15#ibcon#about to read 4, iclass 21, count 0 2006.197.07:36:29.15#ibcon#read 4, iclass 21, count 0 2006.197.07:36:29.15#ibcon#about to read 5, iclass 21, count 0 2006.197.07:36:29.15#ibcon#read 5, iclass 21, count 0 2006.197.07:36:29.15#ibcon#about to read 6, iclass 21, count 0 2006.197.07:36:29.15#ibcon#read 6, iclass 21, count 0 2006.197.07:36:29.15#ibcon#end of sib2, iclass 21, count 0 2006.197.07:36:29.15#ibcon#*after write, iclass 21, count 0 2006.197.07:36:29.15#ibcon#*before return 0, iclass 21, count 0 2006.197.07:36:29.15#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.197.07:36:29.15#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.197.07:36:29.15#ibcon#about to clear, iclass 21 cls_cnt 0 2006.197.07:36:29.15#ibcon#cleared, iclass 21 cls_cnt 0 2006.197.07:36:29.15$vc4f8/valo=6,772.99 2006.197.07:36:29.15#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.197.07:36:29.15#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.197.07:36:29.15#ibcon#ireg 17 cls_cnt 0 2006.197.07:36:29.15#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.197.07:36:29.15#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.197.07:36:29.15#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.197.07:36:29.15#ibcon#enter wrdev, iclass 23, count 0 2006.197.07:36:29.15#ibcon#first serial, iclass 23, count 0 2006.197.07:36:29.15#ibcon#enter sib2, iclass 23, count 0 2006.197.07:36:29.15#ibcon#flushed, iclass 23, count 0 2006.197.07:36:29.15#ibcon#about to write, iclass 23, count 0 2006.197.07:36:29.15#ibcon#wrote, iclass 23, count 0 2006.197.07:36:29.15#ibcon#about to read 3, iclass 23, count 0 2006.197.07:36:29.17#ibcon#read 3, iclass 23, count 0 2006.197.07:36:29.17#ibcon#about to read 4, iclass 23, count 0 2006.197.07:36:29.17#ibcon#read 4, iclass 23, count 0 2006.197.07:36:29.17#ibcon#about to read 5, iclass 23, count 0 2006.197.07:36:29.17#ibcon#read 5, iclass 23, count 0 2006.197.07:36:29.17#ibcon#about to read 6, iclass 23, count 0 2006.197.07:36:29.17#ibcon#read 6, iclass 23, count 0 2006.197.07:36:29.17#ibcon#end of sib2, iclass 23, count 0 2006.197.07:36:29.17#ibcon#*mode == 0, iclass 23, count 0 2006.197.07:36:29.17#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.197.07:36:29.17#ibcon#[26=FRQ=06,772.99\r\n] 2006.197.07:36:29.17#ibcon#*before write, iclass 23, count 0 2006.197.07:36:29.17#ibcon#enter sib2, iclass 23, count 0 2006.197.07:36:29.17#ibcon#flushed, iclass 23, count 0 2006.197.07:36:29.17#ibcon#about to write, iclass 23, count 0 2006.197.07:36:29.17#ibcon#wrote, iclass 23, count 0 2006.197.07:36:29.17#ibcon#about to read 3, iclass 23, count 0 2006.197.07:36:29.21#ibcon#read 3, iclass 23, count 0 2006.197.07:36:29.21#ibcon#about to read 4, iclass 23, count 0 2006.197.07:36:29.21#ibcon#read 4, iclass 23, count 0 2006.197.07:36:29.21#ibcon#about to read 5, iclass 23, count 0 2006.197.07:36:29.21#ibcon#read 5, iclass 23, count 0 2006.197.07:36:29.21#ibcon#about to read 6, iclass 23, count 0 2006.197.07:36:29.21#ibcon#read 6, iclass 23, count 0 2006.197.07:36:29.21#ibcon#end of sib2, iclass 23, count 0 2006.197.07:36:29.21#ibcon#*after write, iclass 23, count 0 2006.197.07:36:29.21#ibcon#*before return 0, iclass 23, count 0 2006.197.07:36:29.21#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.197.07:36:29.21#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.197.07:36:29.21#ibcon#about to clear, iclass 23 cls_cnt 0 2006.197.07:36:29.21#ibcon#cleared, iclass 23 cls_cnt 0 2006.197.07:36:29.21$vc4f8/va=6,6 2006.197.07:36:29.21#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.197.07:36:29.21#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.197.07:36:29.21#ibcon#ireg 11 cls_cnt 2 2006.197.07:36:29.21#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.197.07:36:29.27#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.197.07:36:29.27#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.197.07:36:29.27#ibcon#enter wrdev, iclass 25, count 2 2006.197.07:36:29.27#ibcon#first serial, iclass 25, count 2 2006.197.07:36:29.27#ibcon#enter sib2, iclass 25, count 2 2006.197.07:36:29.27#ibcon#flushed, iclass 25, count 2 2006.197.07:36:29.27#ibcon#about to write, iclass 25, count 2 2006.197.07:36:29.27#ibcon#wrote, iclass 25, count 2 2006.197.07:36:29.27#ibcon#about to read 3, iclass 25, count 2 2006.197.07:36:29.29#ibcon#read 3, iclass 25, count 2 2006.197.07:36:29.29#ibcon#about to read 4, iclass 25, count 2 2006.197.07:36:29.29#ibcon#read 4, iclass 25, count 2 2006.197.07:36:29.29#ibcon#about to read 5, iclass 25, count 2 2006.197.07:36:29.29#ibcon#read 5, iclass 25, count 2 2006.197.07:36:29.29#ibcon#about to read 6, iclass 25, count 2 2006.197.07:36:29.29#ibcon#read 6, iclass 25, count 2 2006.197.07:36:29.29#ibcon#end of sib2, iclass 25, count 2 2006.197.07:36:29.29#ibcon#*mode == 0, iclass 25, count 2 2006.197.07:36:29.29#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.197.07:36:29.29#ibcon#[25=AT06-06\r\n] 2006.197.07:36:29.29#ibcon#*before write, iclass 25, count 2 2006.197.07:36:29.29#ibcon#enter sib2, iclass 25, count 2 2006.197.07:36:29.29#ibcon#flushed, iclass 25, count 2 2006.197.07:36:29.29#ibcon#about to write, iclass 25, count 2 2006.197.07:36:29.29#ibcon#wrote, iclass 25, count 2 2006.197.07:36:29.29#ibcon#about to read 3, iclass 25, count 2 2006.197.07:36:29.32#ibcon#read 3, iclass 25, count 2 2006.197.07:36:29.32#ibcon#about to read 4, iclass 25, count 2 2006.197.07:36:29.32#ibcon#read 4, iclass 25, count 2 2006.197.07:36:29.32#ibcon#about to read 5, iclass 25, count 2 2006.197.07:36:29.32#ibcon#read 5, iclass 25, count 2 2006.197.07:36:29.32#ibcon#about to read 6, iclass 25, count 2 2006.197.07:36:29.32#ibcon#read 6, iclass 25, count 2 2006.197.07:36:29.32#ibcon#end of sib2, iclass 25, count 2 2006.197.07:36:29.32#ibcon#*after write, iclass 25, count 2 2006.197.07:36:29.32#ibcon#*before return 0, iclass 25, count 2 2006.197.07:36:29.32#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.197.07:36:29.32#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.197.07:36:29.32#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.197.07:36:29.32#ibcon#ireg 7 cls_cnt 0 2006.197.07:36:29.32#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.197.07:36:29.44#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.197.07:36:29.44#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.197.07:36:29.44#ibcon#enter wrdev, iclass 25, count 0 2006.197.07:36:29.44#ibcon#first serial, iclass 25, count 0 2006.197.07:36:29.44#ibcon#enter sib2, iclass 25, count 0 2006.197.07:36:29.44#ibcon#flushed, iclass 25, count 0 2006.197.07:36:29.44#ibcon#about to write, iclass 25, count 0 2006.197.07:36:29.44#ibcon#wrote, iclass 25, count 0 2006.197.07:36:29.44#ibcon#about to read 3, iclass 25, count 0 2006.197.07:36:29.46#ibcon#read 3, iclass 25, count 0 2006.197.07:36:29.46#ibcon#about to read 4, iclass 25, count 0 2006.197.07:36:29.46#ibcon#read 4, iclass 25, count 0 2006.197.07:36:29.46#ibcon#about to read 5, iclass 25, count 0 2006.197.07:36:29.46#ibcon#read 5, iclass 25, count 0 2006.197.07:36:29.46#ibcon#about to read 6, iclass 25, count 0 2006.197.07:36:29.46#ibcon#read 6, iclass 25, count 0 2006.197.07:36:29.46#ibcon#end of sib2, iclass 25, count 0 2006.197.07:36:29.46#ibcon#*mode == 0, iclass 25, count 0 2006.197.07:36:29.46#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.197.07:36:29.46#ibcon#[25=USB\r\n] 2006.197.07:36:29.46#ibcon#*before write, iclass 25, count 0 2006.197.07:36:29.46#ibcon#enter sib2, iclass 25, count 0 2006.197.07:36:29.46#ibcon#flushed, iclass 25, count 0 2006.197.07:36:29.46#ibcon#about to write, iclass 25, count 0 2006.197.07:36:29.46#ibcon#wrote, iclass 25, count 0 2006.197.07:36:29.46#ibcon#about to read 3, iclass 25, count 0 2006.197.07:36:29.49#ibcon#read 3, iclass 25, count 0 2006.197.07:36:29.49#ibcon#about to read 4, iclass 25, count 0 2006.197.07:36:29.49#ibcon#read 4, iclass 25, count 0 2006.197.07:36:29.49#ibcon#about to read 5, iclass 25, count 0 2006.197.07:36:29.49#ibcon#read 5, iclass 25, count 0 2006.197.07:36:29.49#ibcon#about to read 6, iclass 25, count 0 2006.197.07:36:29.49#ibcon#read 6, iclass 25, count 0 2006.197.07:36:29.49#ibcon#end of sib2, iclass 25, count 0 2006.197.07:36:29.49#ibcon#*after write, iclass 25, count 0 2006.197.07:36:29.49#ibcon#*before return 0, iclass 25, count 0 2006.197.07:36:29.49#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.197.07:36:29.49#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.197.07:36:29.49#ibcon#about to clear, iclass 25 cls_cnt 0 2006.197.07:36:29.49#ibcon#cleared, iclass 25 cls_cnt 0 2006.197.07:36:29.49$vc4f8/valo=7,832.99 2006.197.07:36:29.49#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.197.07:36:29.49#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.197.07:36:29.49#ibcon#ireg 17 cls_cnt 0 2006.197.07:36:29.49#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.197.07:36:29.49#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.197.07:36:29.49#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.197.07:36:29.49#ibcon#enter wrdev, iclass 27, count 0 2006.197.07:36:29.49#ibcon#first serial, iclass 27, count 0 2006.197.07:36:29.49#ibcon#enter sib2, iclass 27, count 0 2006.197.07:36:29.49#ibcon#flushed, iclass 27, count 0 2006.197.07:36:29.49#ibcon#about to write, iclass 27, count 0 2006.197.07:36:29.49#ibcon#wrote, iclass 27, count 0 2006.197.07:36:29.49#ibcon#about to read 3, iclass 27, count 0 2006.197.07:36:29.51#ibcon#read 3, iclass 27, count 0 2006.197.07:36:29.51#ibcon#about to read 4, iclass 27, count 0 2006.197.07:36:29.51#ibcon#read 4, iclass 27, count 0 2006.197.07:36:29.51#ibcon#about to read 5, iclass 27, count 0 2006.197.07:36:29.51#ibcon#read 5, iclass 27, count 0 2006.197.07:36:29.51#ibcon#about to read 6, iclass 27, count 0 2006.197.07:36:29.51#ibcon#read 6, iclass 27, count 0 2006.197.07:36:29.51#ibcon#end of sib2, iclass 27, count 0 2006.197.07:36:29.51#ibcon#*mode == 0, iclass 27, count 0 2006.197.07:36:29.51#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.197.07:36:29.51#ibcon#[26=FRQ=07,832.99\r\n] 2006.197.07:36:29.51#ibcon#*before write, iclass 27, count 0 2006.197.07:36:29.51#ibcon#enter sib2, iclass 27, count 0 2006.197.07:36:29.51#ibcon#flushed, iclass 27, count 0 2006.197.07:36:29.51#ibcon#about to write, iclass 27, count 0 2006.197.07:36:29.51#ibcon#wrote, iclass 27, count 0 2006.197.07:36:29.51#ibcon#about to read 3, iclass 27, count 0 2006.197.07:36:29.55#ibcon#read 3, iclass 27, count 0 2006.197.07:36:29.55#ibcon#about to read 4, iclass 27, count 0 2006.197.07:36:29.55#ibcon#read 4, iclass 27, count 0 2006.197.07:36:29.55#ibcon#about to read 5, iclass 27, count 0 2006.197.07:36:29.55#ibcon#read 5, iclass 27, count 0 2006.197.07:36:29.55#ibcon#about to read 6, iclass 27, count 0 2006.197.07:36:29.55#ibcon#read 6, iclass 27, count 0 2006.197.07:36:29.55#ibcon#end of sib2, iclass 27, count 0 2006.197.07:36:29.55#ibcon#*after write, iclass 27, count 0 2006.197.07:36:29.55#ibcon#*before return 0, iclass 27, count 0 2006.197.07:36:29.55#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.197.07:36:29.55#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.197.07:36:29.55#ibcon#about to clear, iclass 27 cls_cnt 0 2006.197.07:36:29.55#ibcon#cleared, iclass 27 cls_cnt 0 2006.197.07:36:29.55$vc4f8/va=7,6 2006.197.07:36:29.55#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.197.07:36:29.55#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.197.07:36:29.55#ibcon#ireg 11 cls_cnt 2 2006.197.07:36:29.55#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.197.07:36:29.61#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.197.07:36:29.61#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.197.07:36:29.61#ibcon#enter wrdev, iclass 29, count 2 2006.197.07:36:29.61#ibcon#first serial, iclass 29, count 2 2006.197.07:36:29.61#ibcon#enter sib2, iclass 29, count 2 2006.197.07:36:29.61#ibcon#flushed, iclass 29, count 2 2006.197.07:36:29.61#ibcon#about to write, iclass 29, count 2 2006.197.07:36:29.61#ibcon#wrote, iclass 29, count 2 2006.197.07:36:29.61#ibcon#about to read 3, iclass 29, count 2 2006.197.07:36:29.63#ibcon#read 3, iclass 29, count 2 2006.197.07:36:29.63#ibcon#about to read 4, iclass 29, count 2 2006.197.07:36:29.63#ibcon#read 4, iclass 29, count 2 2006.197.07:36:29.63#ibcon#about to read 5, iclass 29, count 2 2006.197.07:36:29.63#ibcon#read 5, iclass 29, count 2 2006.197.07:36:29.63#ibcon#about to read 6, iclass 29, count 2 2006.197.07:36:29.63#ibcon#read 6, iclass 29, count 2 2006.197.07:36:29.63#ibcon#end of sib2, iclass 29, count 2 2006.197.07:36:29.63#ibcon#*mode == 0, iclass 29, count 2 2006.197.07:36:29.63#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.197.07:36:29.63#ibcon#[25=AT07-06\r\n] 2006.197.07:36:29.63#ibcon#*before write, iclass 29, count 2 2006.197.07:36:29.63#ibcon#enter sib2, iclass 29, count 2 2006.197.07:36:29.63#ibcon#flushed, iclass 29, count 2 2006.197.07:36:29.63#ibcon#about to write, iclass 29, count 2 2006.197.07:36:29.63#ibcon#wrote, iclass 29, count 2 2006.197.07:36:29.63#ibcon#about to read 3, iclass 29, count 2 2006.197.07:36:29.66#ibcon#read 3, iclass 29, count 2 2006.197.07:36:29.66#ibcon#about to read 4, iclass 29, count 2 2006.197.07:36:29.66#ibcon#read 4, iclass 29, count 2 2006.197.07:36:29.66#ibcon#about to read 5, iclass 29, count 2 2006.197.07:36:29.66#ibcon#read 5, iclass 29, count 2 2006.197.07:36:29.66#ibcon#about to read 6, iclass 29, count 2 2006.197.07:36:29.66#ibcon#read 6, iclass 29, count 2 2006.197.07:36:29.66#ibcon#end of sib2, iclass 29, count 2 2006.197.07:36:29.66#ibcon#*after write, iclass 29, count 2 2006.197.07:36:29.66#ibcon#*before return 0, iclass 29, count 2 2006.197.07:36:29.66#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.197.07:36:29.66#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.197.07:36:29.66#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.197.07:36:29.66#ibcon#ireg 7 cls_cnt 0 2006.197.07:36:29.66#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.197.07:36:29.78#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.197.07:36:29.78#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.197.07:36:29.78#ibcon#enter wrdev, iclass 29, count 0 2006.197.07:36:29.78#ibcon#first serial, iclass 29, count 0 2006.197.07:36:29.78#ibcon#enter sib2, iclass 29, count 0 2006.197.07:36:29.78#ibcon#flushed, iclass 29, count 0 2006.197.07:36:29.78#ibcon#about to write, iclass 29, count 0 2006.197.07:36:29.78#ibcon#wrote, iclass 29, count 0 2006.197.07:36:29.78#ibcon#about to read 3, iclass 29, count 0 2006.197.07:36:29.80#ibcon#read 3, iclass 29, count 0 2006.197.07:36:29.80#ibcon#about to read 4, iclass 29, count 0 2006.197.07:36:29.80#ibcon#read 4, iclass 29, count 0 2006.197.07:36:29.80#ibcon#about to read 5, iclass 29, count 0 2006.197.07:36:29.80#ibcon#read 5, iclass 29, count 0 2006.197.07:36:29.80#ibcon#about to read 6, iclass 29, count 0 2006.197.07:36:29.80#ibcon#read 6, iclass 29, count 0 2006.197.07:36:29.80#ibcon#end of sib2, iclass 29, count 0 2006.197.07:36:29.80#ibcon#*mode == 0, iclass 29, count 0 2006.197.07:36:29.80#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.197.07:36:29.80#ibcon#[25=USB\r\n] 2006.197.07:36:29.80#ibcon#*before write, iclass 29, count 0 2006.197.07:36:29.80#ibcon#enter sib2, iclass 29, count 0 2006.197.07:36:29.80#ibcon#flushed, iclass 29, count 0 2006.197.07:36:29.80#ibcon#about to write, iclass 29, count 0 2006.197.07:36:29.80#ibcon#wrote, iclass 29, count 0 2006.197.07:36:29.80#ibcon#about to read 3, iclass 29, count 0 2006.197.07:36:29.83#ibcon#read 3, iclass 29, count 0 2006.197.07:36:29.83#ibcon#about to read 4, iclass 29, count 0 2006.197.07:36:29.83#ibcon#read 4, iclass 29, count 0 2006.197.07:36:29.83#ibcon#about to read 5, iclass 29, count 0 2006.197.07:36:29.83#ibcon#read 5, iclass 29, count 0 2006.197.07:36:29.83#ibcon#about to read 6, iclass 29, count 0 2006.197.07:36:29.83#ibcon#read 6, iclass 29, count 0 2006.197.07:36:29.83#ibcon#end of sib2, iclass 29, count 0 2006.197.07:36:29.83#ibcon#*after write, iclass 29, count 0 2006.197.07:36:29.83#ibcon#*before return 0, iclass 29, count 0 2006.197.07:36:29.83#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.197.07:36:29.83#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.197.07:36:29.83#ibcon#about to clear, iclass 29 cls_cnt 0 2006.197.07:36:29.83#ibcon#cleared, iclass 29 cls_cnt 0 2006.197.07:36:29.83$vc4f8/valo=8,852.99 2006.197.07:36:29.83#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.197.07:36:29.83#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.197.07:36:29.83#ibcon#ireg 17 cls_cnt 0 2006.197.07:36:29.83#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.197.07:36:29.83#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.197.07:36:29.83#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.197.07:36:29.83#ibcon#enter wrdev, iclass 31, count 0 2006.197.07:36:29.83#ibcon#first serial, iclass 31, count 0 2006.197.07:36:29.83#ibcon#enter sib2, iclass 31, count 0 2006.197.07:36:29.83#ibcon#flushed, iclass 31, count 0 2006.197.07:36:29.83#ibcon#about to write, iclass 31, count 0 2006.197.07:36:29.83#ibcon#wrote, iclass 31, count 0 2006.197.07:36:29.83#ibcon#about to read 3, iclass 31, count 0 2006.197.07:36:29.85#ibcon#read 3, iclass 31, count 0 2006.197.07:36:29.85#ibcon#about to read 4, iclass 31, count 0 2006.197.07:36:29.85#ibcon#read 4, iclass 31, count 0 2006.197.07:36:29.85#ibcon#about to read 5, iclass 31, count 0 2006.197.07:36:29.85#ibcon#read 5, iclass 31, count 0 2006.197.07:36:29.85#ibcon#about to read 6, iclass 31, count 0 2006.197.07:36:29.85#ibcon#read 6, iclass 31, count 0 2006.197.07:36:29.85#ibcon#end of sib2, iclass 31, count 0 2006.197.07:36:29.85#ibcon#*mode == 0, iclass 31, count 0 2006.197.07:36:29.85#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.197.07:36:29.85#ibcon#[26=FRQ=08,852.99\r\n] 2006.197.07:36:29.85#ibcon#*before write, iclass 31, count 0 2006.197.07:36:29.85#ibcon#enter sib2, iclass 31, count 0 2006.197.07:36:29.85#ibcon#flushed, iclass 31, count 0 2006.197.07:36:29.85#ibcon#about to write, iclass 31, count 0 2006.197.07:36:29.85#ibcon#wrote, iclass 31, count 0 2006.197.07:36:29.85#ibcon#about to read 3, iclass 31, count 0 2006.197.07:36:29.89#ibcon#read 3, iclass 31, count 0 2006.197.07:36:29.89#ibcon#about to read 4, iclass 31, count 0 2006.197.07:36:29.89#ibcon#read 4, iclass 31, count 0 2006.197.07:36:29.89#ibcon#about to read 5, iclass 31, count 0 2006.197.07:36:29.89#ibcon#read 5, iclass 31, count 0 2006.197.07:36:29.89#ibcon#about to read 6, iclass 31, count 0 2006.197.07:36:29.89#ibcon#read 6, iclass 31, count 0 2006.197.07:36:29.89#ibcon#end of sib2, iclass 31, count 0 2006.197.07:36:29.89#ibcon#*after write, iclass 31, count 0 2006.197.07:36:29.89#ibcon#*before return 0, iclass 31, count 0 2006.197.07:36:29.89#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.197.07:36:29.89#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.197.07:36:29.89#ibcon#about to clear, iclass 31 cls_cnt 0 2006.197.07:36:29.89#ibcon#cleared, iclass 31 cls_cnt 0 2006.197.07:36:29.89$vc4f8/va=8,7 2006.197.07:36:29.89#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.197.07:36:29.89#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.197.07:36:29.89#ibcon#ireg 11 cls_cnt 2 2006.197.07:36:29.89#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.197.07:36:29.95#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.197.07:36:29.95#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.197.07:36:29.95#ibcon#enter wrdev, iclass 33, count 2 2006.197.07:36:29.95#ibcon#first serial, iclass 33, count 2 2006.197.07:36:29.95#ibcon#enter sib2, iclass 33, count 2 2006.197.07:36:29.95#ibcon#flushed, iclass 33, count 2 2006.197.07:36:29.95#ibcon#about to write, iclass 33, count 2 2006.197.07:36:29.95#ibcon#wrote, iclass 33, count 2 2006.197.07:36:29.95#ibcon#about to read 3, iclass 33, count 2 2006.197.07:36:29.97#ibcon#read 3, iclass 33, count 2 2006.197.07:36:29.97#ibcon#about to read 4, iclass 33, count 2 2006.197.07:36:29.97#ibcon#read 4, iclass 33, count 2 2006.197.07:36:29.97#ibcon#about to read 5, iclass 33, count 2 2006.197.07:36:29.97#ibcon#read 5, iclass 33, count 2 2006.197.07:36:29.97#ibcon#about to read 6, iclass 33, count 2 2006.197.07:36:29.97#ibcon#read 6, iclass 33, count 2 2006.197.07:36:29.97#ibcon#end of sib2, iclass 33, count 2 2006.197.07:36:29.97#ibcon#*mode == 0, iclass 33, count 2 2006.197.07:36:29.97#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.197.07:36:29.97#ibcon#[25=AT08-07\r\n] 2006.197.07:36:29.97#ibcon#*before write, iclass 33, count 2 2006.197.07:36:29.97#ibcon#enter sib2, iclass 33, count 2 2006.197.07:36:29.97#ibcon#flushed, iclass 33, count 2 2006.197.07:36:29.97#ibcon#about to write, iclass 33, count 2 2006.197.07:36:29.97#ibcon#wrote, iclass 33, count 2 2006.197.07:36:29.97#ibcon#about to read 3, iclass 33, count 2 2006.197.07:36:30.00#ibcon#read 3, iclass 33, count 2 2006.197.07:36:30.00#ibcon#about to read 4, iclass 33, count 2 2006.197.07:36:30.00#ibcon#read 4, iclass 33, count 2 2006.197.07:36:30.00#ibcon#about to read 5, iclass 33, count 2 2006.197.07:36:30.00#ibcon#read 5, iclass 33, count 2 2006.197.07:36:30.00#ibcon#about to read 6, iclass 33, count 2 2006.197.07:36:30.00#ibcon#read 6, iclass 33, count 2 2006.197.07:36:30.00#ibcon#end of sib2, iclass 33, count 2 2006.197.07:36:30.00#ibcon#*after write, iclass 33, count 2 2006.197.07:36:30.00#ibcon#*before return 0, iclass 33, count 2 2006.197.07:36:30.00#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.197.07:36:30.00#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.197.07:36:30.00#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.197.07:36:30.00#ibcon#ireg 7 cls_cnt 0 2006.197.07:36:30.00#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.197.07:36:30.12#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.197.07:36:30.12#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.197.07:36:30.12#ibcon#enter wrdev, iclass 33, count 0 2006.197.07:36:30.12#ibcon#first serial, iclass 33, count 0 2006.197.07:36:30.12#ibcon#enter sib2, iclass 33, count 0 2006.197.07:36:30.12#ibcon#flushed, iclass 33, count 0 2006.197.07:36:30.12#ibcon#about to write, iclass 33, count 0 2006.197.07:36:30.12#ibcon#wrote, iclass 33, count 0 2006.197.07:36:30.12#ibcon#about to read 3, iclass 33, count 0 2006.197.07:36:30.14#ibcon#read 3, iclass 33, count 0 2006.197.07:36:30.14#ibcon#about to read 4, iclass 33, count 0 2006.197.07:36:30.14#ibcon#read 4, iclass 33, count 0 2006.197.07:36:30.14#ibcon#about to read 5, iclass 33, count 0 2006.197.07:36:30.14#ibcon#read 5, iclass 33, count 0 2006.197.07:36:30.14#ibcon#about to read 6, iclass 33, count 0 2006.197.07:36:30.14#ibcon#read 6, iclass 33, count 0 2006.197.07:36:30.14#ibcon#end of sib2, iclass 33, count 0 2006.197.07:36:30.14#ibcon#*mode == 0, iclass 33, count 0 2006.197.07:36:30.14#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.197.07:36:30.14#ibcon#[25=USB\r\n] 2006.197.07:36:30.14#ibcon#*before write, iclass 33, count 0 2006.197.07:36:30.14#ibcon#enter sib2, iclass 33, count 0 2006.197.07:36:30.14#ibcon#flushed, iclass 33, count 0 2006.197.07:36:30.14#ibcon#about to write, iclass 33, count 0 2006.197.07:36:30.14#ibcon#wrote, iclass 33, count 0 2006.197.07:36:30.14#ibcon#about to read 3, iclass 33, count 0 2006.197.07:36:30.17#ibcon#read 3, iclass 33, count 0 2006.197.07:36:30.17#ibcon#about to read 4, iclass 33, count 0 2006.197.07:36:30.17#ibcon#read 4, iclass 33, count 0 2006.197.07:36:30.17#ibcon#about to read 5, iclass 33, count 0 2006.197.07:36:30.17#ibcon#read 5, iclass 33, count 0 2006.197.07:36:30.17#ibcon#about to read 6, iclass 33, count 0 2006.197.07:36:30.17#ibcon#read 6, iclass 33, count 0 2006.197.07:36:30.17#ibcon#end of sib2, iclass 33, count 0 2006.197.07:36:30.17#ibcon#*after write, iclass 33, count 0 2006.197.07:36:30.17#ibcon#*before return 0, iclass 33, count 0 2006.197.07:36:30.17#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.197.07:36:30.17#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.197.07:36:30.17#ibcon#about to clear, iclass 33 cls_cnt 0 2006.197.07:36:30.17#ibcon#cleared, iclass 33 cls_cnt 0 2006.197.07:36:30.17$vc4f8/vblo=1,632.99 2006.197.07:36:30.17#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.197.07:36:30.17#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.197.07:36:30.17#ibcon#ireg 17 cls_cnt 0 2006.197.07:36:30.17#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.197.07:36:30.17#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.197.07:36:30.17#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.197.07:36:30.17#ibcon#enter wrdev, iclass 35, count 0 2006.197.07:36:30.17#ibcon#first serial, iclass 35, count 0 2006.197.07:36:30.17#ibcon#enter sib2, iclass 35, count 0 2006.197.07:36:30.17#ibcon#flushed, iclass 35, count 0 2006.197.07:36:30.17#ibcon#about to write, iclass 35, count 0 2006.197.07:36:30.17#ibcon#wrote, iclass 35, count 0 2006.197.07:36:30.17#ibcon#about to read 3, iclass 35, count 0 2006.197.07:36:30.19#ibcon#read 3, iclass 35, count 0 2006.197.07:36:30.19#ibcon#about to read 4, iclass 35, count 0 2006.197.07:36:30.19#ibcon#read 4, iclass 35, count 0 2006.197.07:36:30.19#ibcon#about to read 5, iclass 35, count 0 2006.197.07:36:30.19#ibcon#read 5, iclass 35, count 0 2006.197.07:36:30.19#ibcon#about to read 6, iclass 35, count 0 2006.197.07:36:30.19#ibcon#read 6, iclass 35, count 0 2006.197.07:36:30.19#ibcon#end of sib2, iclass 35, count 0 2006.197.07:36:30.19#ibcon#*mode == 0, iclass 35, count 0 2006.197.07:36:30.19#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.197.07:36:30.19#ibcon#[28=FRQ=01,632.99\r\n] 2006.197.07:36:30.19#ibcon#*before write, iclass 35, count 0 2006.197.07:36:30.19#ibcon#enter sib2, iclass 35, count 0 2006.197.07:36:30.19#ibcon#flushed, iclass 35, count 0 2006.197.07:36:30.19#ibcon#about to write, iclass 35, count 0 2006.197.07:36:30.19#ibcon#wrote, iclass 35, count 0 2006.197.07:36:30.19#ibcon#about to read 3, iclass 35, count 0 2006.197.07:36:30.23#ibcon#read 3, iclass 35, count 0 2006.197.07:36:30.23#ibcon#about to read 4, iclass 35, count 0 2006.197.07:36:30.23#ibcon#read 4, iclass 35, count 0 2006.197.07:36:30.23#ibcon#about to read 5, iclass 35, count 0 2006.197.07:36:30.23#ibcon#read 5, iclass 35, count 0 2006.197.07:36:30.23#ibcon#about to read 6, iclass 35, count 0 2006.197.07:36:30.23#ibcon#read 6, iclass 35, count 0 2006.197.07:36:30.23#ibcon#end of sib2, iclass 35, count 0 2006.197.07:36:30.23#ibcon#*after write, iclass 35, count 0 2006.197.07:36:30.23#ibcon#*before return 0, iclass 35, count 0 2006.197.07:36:30.23#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.197.07:36:30.23#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.197.07:36:30.23#ibcon#about to clear, iclass 35 cls_cnt 0 2006.197.07:36:30.23#ibcon#cleared, iclass 35 cls_cnt 0 2006.197.07:36:30.23$vc4f8/vb=1,4 2006.197.07:36:30.23#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.197.07:36:30.23#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.197.07:36:30.23#ibcon#ireg 11 cls_cnt 2 2006.197.07:36:30.23#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.197.07:36:30.23#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.197.07:36:30.23#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.197.07:36:30.23#ibcon#enter wrdev, iclass 37, count 2 2006.197.07:36:30.23#ibcon#first serial, iclass 37, count 2 2006.197.07:36:30.23#ibcon#enter sib2, iclass 37, count 2 2006.197.07:36:30.23#ibcon#flushed, iclass 37, count 2 2006.197.07:36:30.23#ibcon#about to write, iclass 37, count 2 2006.197.07:36:30.23#ibcon#wrote, iclass 37, count 2 2006.197.07:36:30.23#ibcon#about to read 3, iclass 37, count 2 2006.197.07:36:30.25#ibcon#read 3, iclass 37, count 2 2006.197.07:36:30.25#ibcon#about to read 4, iclass 37, count 2 2006.197.07:36:30.25#ibcon#read 4, iclass 37, count 2 2006.197.07:36:30.25#ibcon#about to read 5, iclass 37, count 2 2006.197.07:36:30.25#ibcon#read 5, iclass 37, count 2 2006.197.07:36:30.25#ibcon#about to read 6, iclass 37, count 2 2006.197.07:36:30.25#ibcon#read 6, iclass 37, count 2 2006.197.07:36:30.25#ibcon#end of sib2, iclass 37, count 2 2006.197.07:36:30.25#ibcon#*mode == 0, iclass 37, count 2 2006.197.07:36:30.25#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.197.07:36:30.25#ibcon#[27=AT01-04\r\n] 2006.197.07:36:30.25#ibcon#*before write, iclass 37, count 2 2006.197.07:36:30.25#ibcon#enter sib2, iclass 37, count 2 2006.197.07:36:30.25#ibcon#flushed, iclass 37, count 2 2006.197.07:36:30.25#ibcon#about to write, iclass 37, count 2 2006.197.07:36:30.25#ibcon#wrote, iclass 37, count 2 2006.197.07:36:30.25#ibcon#about to read 3, iclass 37, count 2 2006.197.07:36:30.28#ibcon#read 3, iclass 37, count 2 2006.197.07:36:30.28#ibcon#about to read 4, iclass 37, count 2 2006.197.07:36:30.28#ibcon#read 4, iclass 37, count 2 2006.197.07:36:30.28#ibcon#about to read 5, iclass 37, count 2 2006.197.07:36:30.28#ibcon#read 5, iclass 37, count 2 2006.197.07:36:30.28#ibcon#about to read 6, iclass 37, count 2 2006.197.07:36:30.28#ibcon#read 6, iclass 37, count 2 2006.197.07:36:30.28#ibcon#end of sib2, iclass 37, count 2 2006.197.07:36:30.28#ibcon#*after write, iclass 37, count 2 2006.197.07:36:30.28#ibcon#*before return 0, iclass 37, count 2 2006.197.07:36:30.28#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.197.07:36:30.28#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.197.07:36:30.28#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.197.07:36:30.28#ibcon#ireg 7 cls_cnt 0 2006.197.07:36:30.28#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.197.07:36:30.40#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.197.07:36:30.40#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.197.07:36:30.40#ibcon#enter wrdev, iclass 37, count 0 2006.197.07:36:30.40#ibcon#first serial, iclass 37, count 0 2006.197.07:36:30.40#ibcon#enter sib2, iclass 37, count 0 2006.197.07:36:30.40#ibcon#flushed, iclass 37, count 0 2006.197.07:36:30.40#ibcon#about to write, iclass 37, count 0 2006.197.07:36:30.40#ibcon#wrote, iclass 37, count 0 2006.197.07:36:30.40#ibcon#about to read 3, iclass 37, count 0 2006.197.07:36:30.42#ibcon#read 3, iclass 37, count 0 2006.197.07:36:30.42#ibcon#about to read 4, iclass 37, count 0 2006.197.07:36:30.42#ibcon#read 4, iclass 37, count 0 2006.197.07:36:30.42#ibcon#about to read 5, iclass 37, count 0 2006.197.07:36:30.42#ibcon#read 5, iclass 37, count 0 2006.197.07:36:30.42#ibcon#about to read 6, iclass 37, count 0 2006.197.07:36:30.42#ibcon#read 6, iclass 37, count 0 2006.197.07:36:30.42#ibcon#end of sib2, iclass 37, count 0 2006.197.07:36:30.42#ibcon#*mode == 0, iclass 37, count 0 2006.197.07:36:30.42#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.197.07:36:30.42#ibcon#[27=USB\r\n] 2006.197.07:36:30.42#ibcon#*before write, iclass 37, count 0 2006.197.07:36:30.42#ibcon#enter sib2, iclass 37, count 0 2006.197.07:36:30.42#ibcon#flushed, iclass 37, count 0 2006.197.07:36:30.42#ibcon#about to write, iclass 37, count 0 2006.197.07:36:30.42#ibcon#wrote, iclass 37, count 0 2006.197.07:36:30.42#ibcon#about to read 3, iclass 37, count 0 2006.197.07:36:30.45#ibcon#read 3, iclass 37, count 0 2006.197.07:36:30.45#ibcon#about to read 4, iclass 37, count 0 2006.197.07:36:30.45#ibcon#read 4, iclass 37, count 0 2006.197.07:36:30.45#ibcon#about to read 5, iclass 37, count 0 2006.197.07:36:30.45#ibcon#read 5, iclass 37, count 0 2006.197.07:36:30.45#ibcon#about to read 6, iclass 37, count 0 2006.197.07:36:30.45#ibcon#read 6, iclass 37, count 0 2006.197.07:36:30.45#ibcon#end of sib2, iclass 37, count 0 2006.197.07:36:30.45#ibcon#*after write, iclass 37, count 0 2006.197.07:36:30.45#ibcon#*before return 0, iclass 37, count 0 2006.197.07:36:30.45#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.197.07:36:30.45#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.197.07:36:30.45#ibcon#about to clear, iclass 37 cls_cnt 0 2006.197.07:36:30.45#ibcon#cleared, iclass 37 cls_cnt 0 2006.197.07:36:30.45$vc4f8/vblo=2,640.99 2006.197.07:36:30.45#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.197.07:36:30.45#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.197.07:36:30.45#ibcon#ireg 17 cls_cnt 0 2006.197.07:36:30.45#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.197.07:36:30.45#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.197.07:36:30.45#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.197.07:36:30.45#ibcon#enter wrdev, iclass 39, count 0 2006.197.07:36:30.45#ibcon#first serial, iclass 39, count 0 2006.197.07:36:30.45#ibcon#enter sib2, iclass 39, count 0 2006.197.07:36:30.45#ibcon#flushed, iclass 39, count 0 2006.197.07:36:30.45#ibcon#about to write, iclass 39, count 0 2006.197.07:36:30.45#ibcon#wrote, iclass 39, count 0 2006.197.07:36:30.45#ibcon#about to read 3, iclass 39, count 0 2006.197.07:36:30.47#ibcon#read 3, iclass 39, count 0 2006.197.07:36:30.47#ibcon#about to read 4, iclass 39, count 0 2006.197.07:36:30.47#ibcon#read 4, iclass 39, count 0 2006.197.07:36:30.47#ibcon#about to read 5, iclass 39, count 0 2006.197.07:36:30.47#ibcon#read 5, iclass 39, count 0 2006.197.07:36:30.47#ibcon#about to read 6, iclass 39, count 0 2006.197.07:36:30.47#ibcon#read 6, iclass 39, count 0 2006.197.07:36:30.47#ibcon#end of sib2, iclass 39, count 0 2006.197.07:36:30.47#ibcon#*mode == 0, iclass 39, count 0 2006.197.07:36:30.47#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.197.07:36:30.47#ibcon#[28=FRQ=02,640.99\r\n] 2006.197.07:36:30.47#ibcon#*before write, iclass 39, count 0 2006.197.07:36:30.47#ibcon#enter sib2, iclass 39, count 0 2006.197.07:36:30.47#ibcon#flushed, iclass 39, count 0 2006.197.07:36:30.47#ibcon#about to write, iclass 39, count 0 2006.197.07:36:30.47#ibcon#wrote, iclass 39, count 0 2006.197.07:36:30.47#ibcon#about to read 3, iclass 39, count 0 2006.197.07:36:30.51#ibcon#read 3, iclass 39, count 0 2006.197.07:36:30.51#ibcon#about to read 4, iclass 39, count 0 2006.197.07:36:30.51#ibcon#read 4, iclass 39, count 0 2006.197.07:36:30.51#ibcon#about to read 5, iclass 39, count 0 2006.197.07:36:30.51#ibcon#read 5, iclass 39, count 0 2006.197.07:36:30.51#ibcon#about to read 6, iclass 39, count 0 2006.197.07:36:30.51#ibcon#read 6, iclass 39, count 0 2006.197.07:36:30.51#ibcon#end of sib2, iclass 39, count 0 2006.197.07:36:30.51#ibcon#*after write, iclass 39, count 0 2006.197.07:36:30.51#ibcon#*before return 0, iclass 39, count 0 2006.197.07:36:30.51#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.197.07:36:30.51#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.197.07:36:30.51#ibcon#about to clear, iclass 39 cls_cnt 0 2006.197.07:36:30.51#ibcon#cleared, iclass 39 cls_cnt 0 2006.197.07:36:30.51$vc4f8/vb=2,4 2006.197.07:36:30.51#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.197.07:36:30.51#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.197.07:36:30.51#ibcon#ireg 11 cls_cnt 2 2006.197.07:36:30.51#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.197.07:36:30.57#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.197.07:36:30.57#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.197.07:36:30.57#ibcon#enter wrdev, iclass 3, count 2 2006.197.07:36:30.57#ibcon#first serial, iclass 3, count 2 2006.197.07:36:30.57#ibcon#enter sib2, iclass 3, count 2 2006.197.07:36:30.57#ibcon#flushed, iclass 3, count 2 2006.197.07:36:30.57#ibcon#about to write, iclass 3, count 2 2006.197.07:36:30.57#ibcon#wrote, iclass 3, count 2 2006.197.07:36:30.57#ibcon#about to read 3, iclass 3, count 2 2006.197.07:36:30.59#ibcon#read 3, iclass 3, count 2 2006.197.07:36:30.59#ibcon#about to read 4, iclass 3, count 2 2006.197.07:36:30.59#ibcon#read 4, iclass 3, count 2 2006.197.07:36:30.59#ibcon#about to read 5, iclass 3, count 2 2006.197.07:36:30.59#ibcon#read 5, iclass 3, count 2 2006.197.07:36:30.59#ibcon#about to read 6, iclass 3, count 2 2006.197.07:36:30.59#ibcon#read 6, iclass 3, count 2 2006.197.07:36:30.59#ibcon#end of sib2, iclass 3, count 2 2006.197.07:36:30.59#ibcon#*mode == 0, iclass 3, count 2 2006.197.07:36:30.59#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.197.07:36:30.59#ibcon#[27=AT02-04\r\n] 2006.197.07:36:30.59#ibcon#*before write, iclass 3, count 2 2006.197.07:36:30.59#ibcon#enter sib2, iclass 3, count 2 2006.197.07:36:30.59#ibcon#flushed, iclass 3, count 2 2006.197.07:36:30.59#ibcon#about to write, iclass 3, count 2 2006.197.07:36:30.59#ibcon#wrote, iclass 3, count 2 2006.197.07:36:30.59#ibcon#about to read 3, iclass 3, count 2 2006.197.07:36:30.62#ibcon#read 3, iclass 3, count 2 2006.197.07:36:30.62#ibcon#about to read 4, iclass 3, count 2 2006.197.07:36:30.62#ibcon#read 4, iclass 3, count 2 2006.197.07:36:30.62#ibcon#about to read 5, iclass 3, count 2 2006.197.07:36:30.62#ibcon#read 5, iclass 3, count 2 2006.197.07:36:30.62#ibcon#about to read 6, iclass 3, count 2 2006.197.07:36:30.62#ibcon#read 6, iclass 3, count 2 2006.197.07:36:30.62#ibcon#end of sib2, iclass 3, count 2 2006.197.07:36:30.62#ibcon#*after write, iclass 3, count 2 2006.197.07:36:30.62#ibcon#*before return 0, iclass 3, count 2 2006.197.07:36:30.62#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.197.07:36:30.62#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.197.07:36:30.62#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.197.07:36:30.62#ibcon#ireg 7 cls_cnt 0 2006.197.07:36:30.62#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.197.07:36:30.74#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.197.07:36:30.74#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.197.07:36:30.74#ibcon#enter wrdev, iclass 3, count 0 2006.197.07:36:30.74#ibcon#first serial, iclass 3, count 0 2006.197.07:36:30.74#ibcon#enter sib2, iclass 3, count 0 2006.197.07:36:30.74#ibcon#flushed, iclass 3, count 0 2006.197.07:36:30.74#ibcon#about to write, iclass 3, count 0 2006.197.07:36:30.74#ibcon#wrote, iclass 3, count 0 2006.197.07:36:30.74#ibcon#about to read 3, iclass 3, count 0 2006.197.07:36:30.76#ibcon#read 3, iclass 3, count 0 2006.197.07:36:30.76#ibcon#about to read 4, iclass 3, count 0 2006.197.07:36:30.76#ibcon#read 4, iclass 3, count 0 2006.197.07:36:30.76#ibcon#about to read 5, iclass 3, count 0 2006.197.07:36:30.76#ibcon#read 5, iclass 3, count 0 2006.197.07:36:30.76#ibcon#about to read 6, iclass 3, count 0 2006.197.07:36:30.76#ibcon#read 6, iclass 3, count 0 2006.197.07:36:30.76#ibcon#end of sib2, iclass 3, count 0 2006.197.07:36:30.76#ibcon#*mode == 0, iclass 3, count 0 2006.197.07:36:30.76#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.197.07:36:30.76#ibcon#[27=USB\r\n] 2006.197.07:36:30.76#ibcon#*before write, iclass 3, count 0 2006.197.07:36:30.76#ibcon#enter sib2, iclass 3, count 0 2006.197.07:36:30.76#ibcon#flushed, iclass 3, count 0 2006.197.07:36:30.76#ibcon#about to write, iclass 3, count 0 2006.197.07:36:30.76#ibcon#wrote, iclass 3, count 0 2006.197.07:36:30.76#ibcon#about to read 3, iclass 3, count 0 2006.197.07:36:30.79#ibcon#read 3, iclass 3, count 0 2006.197.07:36:30.79#ibcon#about to read 4, iclass 3, count 0 2006.197.07:36:30.79#ibcon#read 4, iclass 3, count 0 2006.197.07:36:30.79#ibcon#about to read 5, iclass 3, count 0 2006.197.07:36:30.79#ibcon#read 5, iclass 3, count 0 2006.197.07:36:30.79#ibcon#about to read 6, iclass 3, count 0 2006.197.07:36:30.79#ibcon#read 6, iclass 3, count 0 2006.197.07:36:30.79#ibcon#end of sib2, iclass 3, count 0 2006.197.07:36:30.79#ibcon#*after write, iclass 3, count 0 2006.197.07:36:30.79#ibcon#*before return 0, iclass 3, count 0 2006.197.07:36:30.79#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.197.07:36:30.79#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.197.07:36:30.79#ibcon#about to clear, iclass 3 cls_cnt 0 2006.197.07:36:30.79#ibcon#cleared, iclass 3 cls_cnt 0 2006.197.07:36:30.79$vc4f8/vblo=3,656.99 2006.197.07:36:30.79#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.197.07:36:30.79#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.197.07:36:30.79#ibcon#ireg 17 cls_cnt 0 2006.197.07:36:30.79#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.197.07:36:30.79#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.197.07:36:30.79#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.197.07:36:30.79#ibcon#enter wrdev, iclass 5, count 0 2006.197.07:36:30.79#ibcon#first serial, iclass 5, count 0 2006.197.07:36:30.79#ibcon#enter sib2, iclass 5, count 0 2006.197.07:36:30.79#ibcon#flushed, iclass 5, count 0 2006.197.07:36:30.79#ibcon#about to write, iclass 5, count 0 2006.197.07:36:30.79#ibcon#wrote, iclass 5, count 0 2006.197.07:36:30.79#ibcon#about to read 3, iclass 5, count 0 2006.197.07:36:30.81#ibcon#read 3, iclass 5, count 0 2006.197.07:36:30.81#ibcon#about to read 4, iclass 5, count 0 2006.197.07:36:30.81#ibcon#read 4, iclass 5, count 0 2006.197.07:36:30.81#ibcon#about to read 5, iclass 5, count 0 2006.197.07:36:30.81#ibcon#read 5, iclass 5, count 0 2006.197.07:36:30.81#ibcon#about to read 6, iclass 5, count 0 2006.197.07:36:30.81#ibcon#read 6, iclass 5, count 0 2006.197.07:36:30.81#ibcon#end of sib2, iclass 5, count 0 2006.197.07:36:30.81#ibcon#*mode == 0, iclass 5, count 0 2006.197.07:36:30.81#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.197.07:36:30.81#ibcon#[28=FRQ=03,656.99\r\n] 2006.197.07:36:30.81#ibcon#*before write, iclass 5, count 0 2006.197.07:36:30.81#ibcon#enter sib2, iclass 5, count 0 2006.197.07:36:30.81#ibcon#flushed, iclass 5, count 0 2006.197.07:36:30.81#ibcon#about to write, iclass 5, count 0 2006.197.07:36:30.81#ibcon#wrote, iclass 5, count 0 2006.197.07:36:30.81#ibcon#about to read 3, iclass 5, count 0 2006.197.07:36:30.85#ibcon#read 3, iclass 5, count 0 2006.197.07:36:30.85#ibcon#about to read 4, iclass 5, count 0 2006.197.07:36:30.85#ibcon#read 4, iclass 5, count 0 2006.197.07:36:30.85#ibcon#about to read 5, iclass 5, count 0 2006.197.07:36:30.85#ibcon#read 5, iclass 5, count 0 2006.197.07:36:30.85#ibcon#about to read 6, iclass 5, count 0 2006.197.07:36:30.85#ibcon#read 6, iclass 5, count 0 2006.197.07:36:30.85#ibcon#end of sib2, iclass 5, count 0 2006.197.07:36:30.85#ibcon#*after write, iclass 5, count 0 2006.197.07:36:30.85#ibcon#*before return 0, iclass 5, count 0 2006.197.07:36:30.85#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.197.07:36:30.85#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.197.07:36:30.85#ibcon#about to clear, iclass 5 cls_cnt 0 2006.197.07:36:30.85#ibcon#cleared, iclass 5 cls_cnt 0 2006.197.07:36:30.85$vc4f8/vb=3,4 2006.197.07:36:30.85#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.197.07:36:30.85#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.197.07:36:30.85#ibcon#ireg 11 cls_cnt 2 2006.197.07:36:30.85#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.197.07:36:30.91#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.197.07:36:30.91#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.197.07:36:30.91#ibcon#enter wrdev, iclass 7, count 2 2006.197.07:36:30.91#ibcon#first serial, iclass 7, count 2 2006.197.07:36:30.91#ibcon#enter sib2, iclass 7, count 2 2006.197.07:36:30.91#ibcon#flushed, iclass 7, count 2 2006.197.07:36:30.91#ibcon#about to write, iclass 7, count 2 2006.197.07:36:30.91#ibcon#wrote, iclass 7, count 2 2006.197.07:36:30.91#ibcon#about to read 3, iclass 7, count 2 2006.197.07:36:30.93#ibcon#read 3, iclass 7, count 2 2006.197.07:36:30.93#ibcon#about to read 4, iclass 7, count 2 2006.197.07:36:30.93#ibcon#read 4, iclass 7, count 2 2006.197.07:36:30.93#ibcon#about to read 5, iclass 7, count 2 2006.197.07:36:30.93#ibcon#read 5, iclass 7, count 2 2006.197.07:36:30.93#ibcon#about to read 6, iclass 7, count 2 2006.197.07:36:30.93#ibcon#read 6, iclass 7, count 2 2006.197.07:36:30.93#ibcon#end of sib2, iclass 7, count 2 2006.197.07:36:30.93#ibcon#*mode == 0, iclass 7, count 2 2006.197.07:36:30.93#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.197.07:36:30.93#ibcon#[27=AT03-04\r\n] 2006.197.07:36:30.93#ibcon#*before write, iclass 7, count 2 2006.197.07:36:30.93#ibcon#enter sib2, iclass 7, count 2 2006.197.07:36:30.93#ibcon#flushed, iclass 7, count 2 2006.197.07:36:30.93#ibcon#about to write, iclass 7, count 2 2006.197.07:36:30.93#ibcon#wrote, iclass 7, count 2 2006.197.07:36:30.93#ibcon#about to read 3, iclass 7, count 2 2006.197.07:36:30.96#ibcon#read 3, iclass 7, count 2 2006.197.07:36:30.96#ibcon#about to read 4, iclass 7, count 2 2006.197.07:36:30.96#ibcon#read 4, iclass 7, count 2 2006.197.07:36:30.96#ibcon#about to read 5, iclass 7, count 2 2006.197.07:36:30.96#ibcon#read 5, iclass 7, count 2 2006.197.07:36:30.96#ibcon#about to read 6, iclass 7, count 2 2006.197.07:36:30.96#ibcon#read 6, iclass 7, count 2 2006.197.07:36:30.96#ibcon#end of sib2, iclass 7, count 2 2006.197.07:36:30.96#ibcon#*after write, iclass 7, count 2 2006.197.07:36:30.96#ibcon#*before return 0, iclass 7, count 2 2006.197.07:36:30.96#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.197.07:36:30.96#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.197.07:36:30.96#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.197.07:36:30.96#ibcon#ireg 7 cls_cnt 0 2006.197.07:36:30.96#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.197.07:36:31.08#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.197.07:36:31.08#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.197.07:36:31.08#ibcon#enter wrdev, iclass 7, count 0 2006.197.07:36:31.08#ibcon#first serial, iclass 7, count 0 2006.197.07:36:31.08#ibcon#enter sib2, iclass 7, count 0 2006.197.07:36:31.08#ibcon#flushed, iclass 7, count 0 2006.197.07:36:31.08#ibcon#about to write, iclass 7, count 0 2006.197.07:36:31.08#ibcon#wrote, iclass 7, count 0 2006.197.07:36:31.08#ibcon#about to read 3, iclass 7, count 0 2006.197.07:36:31.10#ibcon#read 3, iclass 7, count 0 2006.197.07:36:31.10#ibcon#about to read 4, iclass 7, count 0 2006.197.07:36:31.10#ibcon#read 4, iclass 7, count 0 2006.197.07:36:31.10#ibcon#about to read 5, iclass 7, count 0 2006.197.07:36:31.10#ibcon#read 5, iclass 7, count 0 2006.197.07:36:31.10#ibcon#about to read 6, iclass 7, count 0 2006.197.07:36:31.10#ibcon#read 6, iclass 7, count 0 2006.197.07:36:31.10#ibcon#end of sib2, iclass 7, count 0 2006.197.07:36:31.10#ibcon#*mode == 0, iclass 7, count 0 2006.197.07:36:31.10#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.197.07:36:31.10#ibcon#[27=USB\r\n] 2006.197.07:36:31.10#ibcon#*before write, iclass 7, count 0 2006.197.07:36:31.10#ibcon#enter sib2, iclass 7, count 0 2006.197.07:36:31.10#ibcon#flushed, iclass 7, count 0 2006.197.07:36:31.10#ibcon#about to write, iclass 7, count 0 2006.197.07:36:31.10#ibcon#wrote, iclass 7, count 0 2006.197.07:36:31.10#ibcon#about to read 3, iclass 7, count 0 2006.197.07:36:31.13#ibcon#read 3, iclass 7, count 0 2006.197.07:36:31.13#ibcon#about to read 4, iclass 7, count 0 2006.197.07:36:31.13#ibcon#read 4, iclass 7, count 0 2006.197.07:36:31.13#ibcon#about to read 5, iclass 7, count 0 2006.197.07:36:31.13#ibcon#read 5, iclass 7, count 0 2006.197.07:36:31.13#ibcon#about to read 6, iclass 7, count 0 2006.197.07:36:31.13#ibcon#read 6, iclass 7, count 0 2006.197.07:36:31.13#ibcon#end of sib2, iclass 7, count 0 2006.197.07:36:31.13#ibcon#*after write, iclass 7, count 0 2006.197.07:36:31.13#ibcon#*before return 0, iclass 7, count 0 2006.197.07:36:31.13#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.197.07:36:31.13#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.197.07:36:31.13#ibcon#about to clear, iclass 7 cls_cnt 0 2006.197.07:36:31.13#ibcon#cleared, iclass 7 cls_cnt 0 2006.197.07:36:31.13$vc4f8/vblo=4,712.99 2006.197.07:36:31.13#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.197.07:36:31.13#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.197.07:36:31.13#ibcon#ireg 17 cls_cnt 0 2006.197.07:36:31.13#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.197.07:36:31.13#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.197.07:36:31.13#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.197.07:36:31.13#ibcon#enter wrdev, iclass 11, count 0 2006.197.07:36:31.13#ibcon#first serial, iclass 11, count 0 2006.197.07:36:31.13#ibcon#enter sib2, iclass 11, count 0 2006.197.07:36:31.13#ibcon#flushed, iclass 11, count 0 2006.197.07:36:31.13#ibcon#about to write, iclass 11, count 0 2006.197.07:36:31.13#ibcon#wrote, iclass 11, count 0 2006.197.07:36:31.13#ibcon#about to read 3, iclass 11, count 0 2006.197.07:36:31.15#ibcon#read 3, iclass 11, count 0 2006.197.07:36:31.15#ibcon#about to read 4, iclass 11, count 0 2006.197.07:36:31.15#ibcon#read 4, iclass 11, count 0 2006.197.07:36:31.15#ibcon#about to read 5, iclass 11, count 0 2006.197.07:36:31.15#ibcon#read 5, iclass 11, count 0 2006.197.07:36:31.15#ibcon#about to read 6, iclass 11, count 0 2006.197.07:36:31.15#ibcon#read 6, iclass 11, count 0 2006.197.07:36:31.15#ibcon#end of sib2, iclass 11, count 0 2006.197.07:36:31.15#ibcon#*mode == 0, iclass 11, count 0 2006.197.07:36:31.15#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.197.07:36:31.15#ibcon#[28=FRQ=04,712.99\r\n] 2006.197.07:36:31.15#ibcon#*before write, iclass 11, count 0 2006.197.07:36:31.15#ibcon#enter sib2, iclass 11, count 0 2006.197.07:36:31.15#ibcon#flushed, iclass 11, count 0 2006.197.07:36:31.15#ibcon#about to write, iclass 11, count 0 2006.197.07:36:31.15#ibcon#wrote, iclass 11, count 0 2006.197.07:36:31.15#ibcon#about to read 3, iclass 11, count 0 2006.197.07:36:31.19#ibcon#read 3, iclass 11, count 0 2006.197.07:36:31.19#ibcon#about to read 4, iclass 11, count 0 2006.197.07:36:31.19#ibcon#read 4, iclass 11, count 0 2006.197.07:36:31.19#ibcon#about to read 5, iclass 11, count 0 2006.197.07:36:31.19#ibcon#read 5, iclass 11, count 0 2006.197.07:36:31.19#ibcon#about to read 6, iclass 11, count 0 2006.197.07:36:31.19#ibcon#read 6, iclass 11, count 0 2006.197.07:36:31.19#ibcon#end of sib2, iclass 11, count 0 2006.197.07:36:31.19#ibcon#*after write, iclass 11, count 0 2006.197.07:36:31.19#ibcon#*before return 0, iclass 11, count 0 2006.197.07:36:31.19#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.197.07:36:31.19#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.197.07:36:31.19#ibcon#about to clear, iclass 11 cls_cnt 0 2006.197.07:36:31.19#ibcon#cleared, iclass 11 cls_cnt 0 2006.197.07:36:31.19$vc4f8/vb=4,4 2006.197.07:36:31.19#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.197.07:36:31.19#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.197.07:36:31.19#ibcon#ireg 11 cls_cnt 2 2006.197.07:36:31.19#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.197.07:36:31.25#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.197.07:36:31.25#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.197.07:36:31.25#ibcon#enter wrdev, iclass 13, count 2 2006.197.07:36:31.25#ibcon#first serial, iclass 13, count 2 2006.197.07:36:31.25#ibcon#enter sib2, iclass 13, count 2 2006.197.07:36:31.25#ibcon#flushed, iclass 13, count 2 2006.197.07:36:31.25#ibcon#about to write, iclass 13, count 2 2006.197.07:36:31.25#ibcon#wrote, iclass 13, count 2 2006.197.07:36:31.25#ibcon#about to read 3, iclass 13, count 2 2006.197.07:36:31.27#ibcon#read 3, iclass 13, count 2 2006.197.07:36:31.27#ibcon#about to read 4, iclass 13, count 2 2006.197.07:36:31.27#ibcon#read 4, iclass 13, count 2 2006.197.07:36:31.27#ibcon#about to read 5, iclass 13, count 2 2006.197.07:36:31.27#ibcon#read 5, iclass 13, count 2 2006.197.07:36:31.27#ibcon#about to read 6, iclass 13, count 2 2006.197.07:36:31.27#ibcon#read 6, iclass 13, count 2 2006.197.07:36:31.27#ibcon#end of sib2, iclass 13, count 2 2006.197.07:36:31.27#ibcon#*mode == 0, iclass 13, count 2 2006.197.07:36:31.27#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.197.07:36:31.27#ibcon#[27=AT04-04\r\n] 2006.197.07:36:31.27#ibcon#*before write, iclass 13, count 2 2006.197.07:36:31.27#ibcon#enter sib2, iclass 13, count 2 2006.197.07:36:31.27#ibcon#flushed, iclass 13, count 2 2006.197.07:36:31.27#ibcon#about to write, iclass 13, count 2 2006.197.07:36:31.27#ibcon#wrote, iclass 13, count 2 2006.197.07:36:31.27#ibcon#about to read 3, iclass 13, count 2 2006.197.07:36:31.30#ibcon#read 3, iclass 13, count 2 2006.197.07:36:31.30#ibcon#about to read 4, iclass 13, count 2 2006.197.07:36:31.30#ibcon#read 4, iclass 13, count 2 2006.197.07:36:31.30#ibcon#about to read 5, iclass 13, count 2 2006.197.07:36:31.30#ibcon#read 5, iclass 13, count 2 2006.197.07:36:31.30#ibcon#about to read 6, iclass 13, count 2 2006.197.07:36:31.30#ibcon#read 6, iclass 13, count 2 2006.197.07:36:31.30#ibcon#end of sib2, iclass 13, count 2 2006.197.07:36:31.30#ibcon#*after write, iclass 13, count 2 2006.197.07:36:31.30#ibcon#*before return 0, iclass 13, count 2 2006.197.07:36:31.30#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.197.07:36:31.30#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.197.07:36:31.30#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.197.07:36:31.30#ibcon#ireg 7 cls_cnt 0 2006.197.07:36:31.30#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.197.07:36:31.42#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.197.07:36:31.42#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.197.07:36:31.42#ibcon#enter wrdev, iclass 13, count 0 2006.197.07:36:31.42#ibcon#first serial, iclass 13, count 0 2006.197.07:36:31.42#ibcon#enter sib2, iclass 13, count 0 2006.197.07:36:31.42#ibcon#flushed, iclass 13, count 0 2006.197.07:36:31.42#ibcon#about to write, iclass 13, count 0 2006.197.07:36:31.42#ibcon#wrote, iclass 13, count 0 2006.197.07:36:31.42#ibcon#about to read 3, iclass 13, count 0 2006.197.07:36:31.44#ibcon#read 3, iclass 13, count 0 2006.197.07:36:31.44#ibcon#about to read 4, iclass 13, count 0 2006.197.07:36:31.44#ibcon#read 4, iclass 13, count 0 2006.197.07:36:31.44#ibcon#about to read 5, iclass 13, count 0 2006.197.07:36:31.44#ibcon#read 5, iclass 13, count 0 2006.197.07:36:31.44#ibcon#about to read 6, iclass 13, count 0 2006.197.07:36:31.44#ibcon#read 6, iclass 13, count 0 2006.197.07:36:31.44#ibcon#end of sib2, iclass 13, count 0 2006.197.07:36:31.44#ibcon#*mode == 0, iclass 13, count 0 2006.197.07:36:31.44#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.197.07:36:31.44#ibcon#[27=USB\r\n] 2006.197.07:36:31.44#ibcon#*before write, iclass 13, count 0 2006.197.07:36:31.44#ibcon#enter sib2, iclass 13, count 0 2006.197.07:36:31.44#ibcon#flushed, iclass 13, count 0 2006.197.07:36:31.44#ibcon#about to write, iclass 13, count 0 2006.197.07:36:31.44#ibcon#wrote, iclass 13, count 0 2006.197.07:36:31.44#ibcon#about to read 3, iclass 13, count 0 2006.197.07:36:31.47#ibcon#read 3, iclass 13, count 0 2006.197.07:36:31.47#ibcon#about to read 4, iclass 13, count 0 2006.197.07:36:31.47#ibcon#read 4, iclass 13, count 0 2006.197.07:36:31.47#ibcon#about to read 5, iclass 13, count 0 2006.197.07:36:31.47#ibcon#read 5, iclass 13, count 0 2006.197.07:36:31.47#ibcon#about to read 6, iclass 13, count 0 2006.197.07:36:31.47#ibcon#read 6, iclass 13, count 0 2006.197.07:36:31.47#ibcon#end of sib2, iclass 13, count 0 2006.197.07:36:31.47#ibcon#*after write, iclass 13, count 0 2006.197.07:36:31.47#ibcon#*before return 0, iclass 13, count 0 2006.197.07:36:31.47#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.197.07:36:31.47#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.197.07:36:31.47#ibcon#about to clear, iclass 13 cls_cnt 0 2006.197.07:36:31.47#ibcon#cleared, iclass 13 cls_cnt 0 2006.197.07:36:31.47$vc4f8/vblo=5,744.99 2006.197.07:36:31.47#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.197.07:36:31.47#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.197.07:36:31.47#ibcon#ireg 17 cls_cnt 0 2006.197.07:36:31.47#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.197.07:36:31.47#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.197.07:36:31.47#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.197.07:36:31.47#ibcon#enter wrdev, iclass 15, count 0 2006.197.07:36:31.47#ibcon#first serial, iclass 15, count 0 2006.197.07:36:31.47#ibcon#enter sib2, iclass 15, count 0 2006.197.07:36:31.47#ibcon#flushed, iclass 15, count 0 2006.197.07:36:31.47#ibcon#about to write, iclass 15, count 0 2006.197.07:36:31.47#ibcon#wrote, iclass 15, count 0 2006.197.07:36:31.47#ibcon#about to read 3, iclass 15, count 0 2006.197.07:36:31.49#ibcon#read 3, iclass 15, count 0 2006.197.07:36:31.49#ibcon#about to read 4, iclass 15, count 0 2006.197.07:36:31.49#ibcon#read 4, iclass 15, count 0 2006.197.07:36:31.49#ibcon#about to read 5, iclass 15, count 0 2006.197.07:36:31.49#ibcon#read 5, iclass 15, count 0 2006.197.07:36:31.49#ibcon#about to read 6, iclass 15, count 0 2006.197.07:36:31.49#ibcon#read 6, iclass 15, count 0 2006.197.07:36:31.49#ibcon#end of sib2, iclass 15, count 0 2006.197.07:36:31.49#ibcon#*mode == 0, iclass 15, count 0 2006.197.07:36:31.49#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.197.07:36:31.49#ibcon#[28=FRQ=05,744.99\r\n] 2006.197.07:36:31.49#ibcon#*before write, iclass 15, count 0 2006.197.07:36:31.49#ibcon#enter sib2, iclass 15, count 0 2006.197.07:36:31.49#ibcon#flushed, iclass 15, count 0 2006.197.07:36:31.49#ibcon#about to write, iclass 15, count 0 2006.197.07:36:31.49#ibcon#wrote, iclass 15, count 0 2006.197.07:36:31.49#ibcon#about to read 3, iclass 15, count 0 2006.197.07:36:31.53#ibcon#read 3, iclass 15, count 0 2006.197.07:36:31.53#ibcon#about to read 4, iclass 15, count 0 2006.197.07:36:31.53#ibcon#read 4, iclass 15, count 0 2006.197.07:36:31.53#ibcon#about to read 5, iclass 15, count 0 2006.197.07:36:31.53#ibcon#read 5, iclass 15, count 0 2006.197.07:36:31.53#ibcon#about to read 6, iclass 15, count 0 2006.197.07:36:31.53#ibcon#read 6, iclass 15, count 0 2006.197.07:36:31.53#ibcon#end of sib2, iclass 15, count 0 2006.197.07:36:31.53#ibcon#*after write, iclass 15, count 0 2006.197.07:36:31.53#ibcon#*before return 0, iclass 15, count 0 2006.197.07:36:31.53#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.197.07:36:31.53#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.197.07:36:31.53#ibcon#about to clear, iclass 15 cls_cnt 0 2006.197.07:36:31.53#ibcon#cleared, iclass 15 cls_cnt 0 2006.197.07:36:31.53$vc4f8/vb=5,4 2006.197.07:36:31.53#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.197.07:36:31.53#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.197.07:36:31.53#ibcon#ireg 11 cls_cnt 2 2006.197.07:36:31.53#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.197.07:36:31.59#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.197.07:36:31.59#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.197.07:36:31.59#ibcon#enter wrdev, iclass 17, count 2 2006.197.07:36:31.59#ibcon#first serial, iclass 17, count 2 2006.197.07:36:31.59#ibcon#enter sib2, iclass 17, count 2 2006.197.07:36:31.59#ibcon#flushed, iclass 17, count 2 2006.197.07:36:31.59#ibcon#about to write, iclass 17, count 2 2006.197.07:36:31.59#ibcon#wrote, iclass 17, count 2 2006.197.07:36:31.59#ibcon#about to read 3, iclass 17, count 2 2006.197.07:36:31.61#ibcon#read 3, iclass 17, count 2 2006.197.07:36:31.61#ibcon#about to read 4, iclass 17, count 2 2006.197.07:36:31.61#ibcon#read 4, iclass 17, count 2 2006.197.07:36:31.61#ibcon#about to read 5, iclass 17, count 2 2006.197.07:36:31.61#ibcon#read 5, iclass 17, count 2 2006.197.07:36:31.61#ibcon#about to read 6, iclass 17, count 2 2006.197.07:36:31.61#ibcon#read 6, iclass 17, count 2 2006.197.07:36:31.61#ibcon#end of sib2, iclass 17, count 2 2006.197.07:36:31.61#ibcon#*mode == 0, iclass 17, count 2 2006.197.07:36:31.61#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.197.07:36:31.61#ibcon#[27=AT05-04\r\n] 2006.197.07:36:31.61#ibcon#*before write, iclass 17, count 2 2006.197.07:36:31.61#ibcon#enter sib2, iclass 17, count 2 2006.197.07:36:31.61#ibcon#flushed, iclass 17, count 2 2006.197.07:36:31.61#ibcon#about to write, iclass 17, count 2 2006.197.07:36:31.61#ibcon#wrote, iclass 17, count 2 2006.197.07:36:31.61#ibcon#about to read 3, iclass 17, count 2 2006.197.07:36:31.64#ibcon#read 3, iclass 17, count 2 2006.197.07:36:31.64#ibcon#about to read 4, iclass 17, count 2 2006.197.07:36:31.64#ibcon#read 4, iclass 17, count 2 2006.197.07:36:31.64#ibcon#about to read 5, iclass 17, count 2 2006.197.07:36:31.64#ibcon#read 5, iclass 17, count 2 2006.197.07:36:31.64#ibcon#about to read 6, iclass 17, count 2 2006.197.07:36:31.64#ibcon#read 6, iclass 17, count 2 2006.197.07:36:31.64#ibcon#end of sib2, iclass 17, count 2 2006.197.07:36:31.64#ibcon#*after write, iclass 17, count 2 2006.197.07:36:31.64#ibcon#*before return 0, iclass 17, count 2 2006.197.07:36:31.64#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.197.07:36:31.64#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.197.07:36:31.64#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.197.07:36:31.64#ibcon#ireg 7 cls_cnt 0 2006.197.07:36:31.64#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.197.07:36:31.76#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.197.07:36:31.76#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.197.07:36:31.76#ibcon#enter wrdev, iclass 17, count 0 2006.197.07:36:31.76#ibcon#first serial, iclass 17, count 0 2006.197.07:36:31.76#ibcon#enter sib2, iclass 17, count 0 2006.197.07:36:31.76#ibcon#flushed, iclass 17, count 0 2006.197.07:36:31.76#ibcon#about to write, iclass 17, count 0 2006.197.07:36:31.76#ibcon#wrote, iclass 17, count 0 2006.197.07:36:31.76#ibcon#about to read 3, iclass 17, count 0 2006.197.07:36:31.78#ibcon#read 3, iclass 17, count 0 2006.197.07:36:31.78#ibcon#about to read 4, iclass 17, count 0 2006.197.07:36:31.78#ibcon#read 4, iclass 17, count 0 2006.197.07:36:31.78#ibcon#about to read 5, iclass 17, count 0 2006.197.07:36:31.78#ibcon#read 5, iclass 17, count 0 2006.197.07:36:31.78#ibcon#about to read 6, iclass 17, count 0 2006.197.07:36:31.78#ibcon#read 6, iclass 17, count 0 2006.197.07:36:31.78#ibcon#end of sib2, iclass 17, count 0 2006.197.07:36:31.78#ibcon#*mode == 0, iclass 17, count 0 2006.197.07:36:31.78#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.197.07:36:31.78#ibcon#[27=USB\r\n] 2006.197.07:36:31.78#ibcon#*before write, iclass 17, count 0 2006.197.07:36:31.78#ibcon#enter sib2, iclass 17, count 0 2006.197.07:36:31.78#ibcon#flushed, iclass 17, count 0 2006.197.07:36:31.78#ibcon#about to write, iclass 17, count 0 2006.197.07:36:31.78#ibcon#wrote, iclass 17, count 0 2006.197.07:36:31.78#ibcon#about to read 3, iclass 17, count 0 2006.197.07:36:31.81#ibcon#read 3, iclass 17, count 0 2006.197.07:36:31.81#ibcon#about to read 4, iclass 17, count 0 2006.197.07:36:31.81#ibcon#read 4, iclass 17, count 0 2006.197.07:36:31.81#ibcon#about to read 5, iclass 17, count 0 2006.197.07:36:31.81#ibcon#read 5, iclass 17, count 0 2006.197.07:36:31.81#ibcon#about to read 6, iclass 17, count 0 2006.197.07:36:31.81#ibcon#read 6, iclass 17, count 0 2006.197.07:36:31.81#ibcon#end of sib2, iclass 17, count 0 2006.197.07:36:31.81#ibcon#*after write, iclass 17, count 0 2006.197.07:36:31.81#ibcon#*before return 0, iclass 17, count 0 2006.197.07:36:31.81#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.197.07:36:31.81#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.197.07:36:31.81#ibcon#about to clear, iclass 17 cls_cnt 0 2006.197.07:36:31.81#ibcon#cleared, iclass 17 cls_cnt 0 2006.197.07:36:31.81$vc4f8/vblo=6,752.99 2006.197.07:36:31.81#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.197.07:36:31.81#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.197.07:36:31.81#ibcon#ireg 17 cls_cnt 0 2006.197.07:36:31.81#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.197.07:36:31.81#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.197.07:36:31.81#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.197.07:36:31.81#ibcon#enter wrdev, iclass 19, count 0 2006.197.07:36:31.81#ibcon#first serial, iclass 19, count 0 2006.197.07:36:31.81#ibcon#enter sib2, iclass 19, count 0 2006.197.07:36:31.81#ibcon#flushed, iclass 19, count 0 2006.197.07:36:31.81#ibcon#about to write, iclass 19, count 0 2006.197.07:36:31.81#ibcon#wrote, iclass 19, count 0 2006.197.07:36:31.81#ibcon#about to read 3, iclass 19, count 0 2006.197.07:36:31.83#ibcon#read 3, iclass 19, count 0 2006.197.07:36:31.83#ibcon#about to read 4, iclass 19, count 0 2006.197.07:36:31.83#ibcon#read 4, iclass 19, count 0 2006.197.07:36:31.83#ibcon#about to read 5, iclass 19, count 0 2006.197.07:36:31.83#ibcon#read 5, iclass 19, count 0 2006.197.07:36:31.83#ibcon#about to read 6, iclass 19, count 0 2006.197.07:36:31.83#ibcon#read 6, iclass 19, count 0 2006.197.07:36:31.83#ibcon#end of sib2, iclass 19, count 0 2006.197.07:36:31.83#ibcon#*mode == 0, iclass 19, count 0 2006.197.07:36:31.83#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.197.07:36:31.83#ibcon#[28=FRQ=06,752.99\r\n] 2006.197.07:36:31.83#ibcon#*before write, iclass 19, count 0 2006.197.07:36:31.83#ibcon#enter sib2, iclass 19, count 0 2006.197.07:36:31.83#ibcon#flushed, iclass 19, count 0 2006.197.07:36:31.83#ibcon#about to write, iclass 19, count 0 2006.197.07:36:31.83#ibcon#wrote, iclass 19, count 0 2006.197.07:36:31.83#ibcon#about to read 3, iclass 19, count 0 2006.197.07:36:31.87#ibcon#read 3, iclass 19, count 0 2006.197.07:36:31.87#ibcon#about to read 4, iclass 19, count 0 2006.197.07:36:31.87#ibcon#read 4, iclass 19, count 0 2006.197.07:36:31.87#ibcon#about to read 5, iclass 19, count 0 2006.197.07:36:31.87#ibcon#read 5, iclass 19, count 0 2006.197.07:36:31.87#ibcon#about to read 6, iclass 19, count 0 2006.197.07:36:31.87#ibcon#read 6, iclass 19, count 0 2006.197.07:36:31.87#ibcon#end of sib2, iclass 19, count 0 2006.197.07:36:31.87#ibcon#*after write, iclass 19, count 0 2006.197.07:36:31.87#ibcon#*before return 0, iclass 19, count 0 2006.197.07:36:31.87#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.197.07:36:31.87#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.197.07:36:31.87#ibcon#about to clear, iclass 19 cls_cnt 0 2006.197.07:36:31.87#ibcon#cleared, iclass 19 cls_cnt 0 2006.197.07:36:31.87$vc4f8/vb=6,4 2006.197.07:36:31.87#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.197.07:36:31.87#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.197.07:36:31.87#ibcon#ireg 11 cls_cnt 2 2006.197.07:36:31.87#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.197.07:36:31.93#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.197.07:36:31.93#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.197.07:36:31.93#ibcon#enter wrdev, iclass 21, count 2 2006.197.07:36:31.93#ibcon#first serial, iclass 21, count 2 2006.197.07:36:31.93#ibcon#enter sib2, iclass 21, count 2 2006.197.07:36:31.93#ibcon#flushed, iclass 21, count 2 2006.197.07:36:31.93#ibcon#about to write, iclass 21, count 2 2006.197.07:36:31.93#ibcon#wrote, iclass 21, count 2 2006.197.07:36:31.93#ibcon#about to read 3, iclass 21, count 2 2006.197.07:36:31.95#ibcon#read 3, iclass 21, count 2 2006.197.07:36:31.95#ibcon#about to read 4, iclass 21, count 2 2006.197.07:36:31.95#ibcon#read 4, iclass 21, count 2 2006.197.07:36:31.95#ibcon#about to read 5, iclass 21, count 2 2006.197.07:36:31.95#ibcon#read 5, iclass 21, count 2 2006.197.07:36:31.95#ibcon#about to read 6, iclass 21, count 2 2006.197.07:36:31.95#ibcon#read 6, iclass 21, count 2 2006.197.07:36:31.95#ibcon#end of sib2, iclass 21, count 2 2006.197.07:36:31.95#ibcon#*mode == 0, iclass 21, count 2 2006.197.07:36:31.95#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.197.07:36:31.95#ibcon#[27=AT06-04\r\n] 2006.197.07:36:31.95#ibcon#*before write, iclass 21, count 2 2006.197.07:36:31.95#ibcon#enter sib2, iclass 21, count 2 2006.197.07:36:31.95#ibcon#flushed, iclass 21, count 2 2006.197.07:36:31.95#ibcon#about to write, iclass 21, count 2 2006.197.07:36:31.95#ibcon#wrote, iclass 21, count 2 2006.197.07:36:31.95#ibcon#about to read 3, iclass 21, count 2 2006.197.07:36:31.98#ibcon#read 3, iclass 21, count 2 2006.197.07:36:31.98#ibcon#about to read 4, iclass 21, count 2 2006.197.07:36:31.98#ibcon#read 4, iclass 21, count 2 2006.197.07:36:31.98#ibcon#about to read 5, iclass 21, count 2 2006.197.07:36:31.98#ibcon#read 5, iclass 21, count 2 2006.197.07:36:31.98#ibcon#about to read 6, iclass 21, count 2 2006.197.07:36:31.98#ibcon#read 6, iclass 21, count 2 2006.197.07:36:31.98#ibcon#end of sib2, iclass 21, count 2 2006.197.07:36:31.98#ibcon#*after write, iclass 21, count 2 2006.197.07:36:31.98#ibcon#*before return 0, iclass 21, count 2 2006.197.07:36:31.98#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.197.07:36:31.98#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.197.07:36:31.98#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.197.07:36:31.98#ibcon#ireg 7 cls_cnt 0 2006.197.07:36:31.98#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.197.07:36:32.10#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.197.07:36:32.10#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.197.07:36:32.10#ibcon#enter wrdev, iclass 21, count 0 2006.197.07:36:32.10#ibcon#first serial, iclass 21, count 0 2006.197.07:36:32.10#ibcon#enter sib2, iclass 21, count 0 2006.197.07:36:32.10#ibcon#flushed, iclass 21, count 0 2006.197.07:36:32.10#ibcon#about to write, iclass 21, count 0 2006.197.07:36:32.10#ibcon#wrote, iclass 21, count 0 2006.197.07:36:32.10#ibcon#about to read 3, iclass 21, count 0 2006.197.07:36:32.12#ibcon#read 3, iclass 21, count 0 2006.197.07:36:32.12#ibcon#about to read 4, iclass 21, count 0 2006.197.07:36:32.12#ibcon#read 4, iclass 21, count 0 2006.197.07:36:32.12#ibcon#about to read 5, iclass 21, count 0 2006.197.07:36:32.12#ibcon#read 5, iclass 21, count 0 2006.197.07:36:32.12#ibcon#about to read 6, iclass 21, count 0 2006.197.07:36:32.12#ibcon#read 6, iclass 21, count 0 2006.197.07:36:32.12#ibcon#end of sib2, iclass 21, count 0 2006.197.07:36:32.12#ibcon#*mode == 0, iclass 21, count 0 2006.197.07:36:32.12#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.197.07:36:32.12#ibcon#[27=USB\r\n] 2006.197.07:36:32.12#ibcon#*before write, iclass 21, count 0 2006.197.07:36:32.12#ibcon#enter sib2, iclass 21, count 0 2006.197.07:36:32.12#ibcon#flushed, iclass 21, count 0 2006.197.07:36:32.12#ibcon#about to write, iclass 21, count 0 2006.197.07:36:32.12#ibcon#wrote, iclass 21, count 0 2006.197.07:36:32.12#ibcon#about to read 3, iclass 21, count 0 2006.197.07:36:32.15#ibcon#read 3, iclass 21, count 0 2006.197.07:36:32.15#ibcon#about to read 4, iclass 21, count 0 2006.197.07:36:32.15#ibcon#read 4, iclass 21, count 0 2006.197.07:36:32.15#ibcon#about to read 5, iclass 21, count 0 2006.197.07:36:32.15#ibcon#read 5, iclass 21, count 0 2006.197.07:36:32.15#ibcon#about to read 6, iclass 21, count 0 2006.197.07:36:32.15#ibcon#read 6, iclass 21, count 0 2006.197.07:36:32.15#ibcon#end of sib2, iclass 21, count 0 2006.197.07:36:32.15#ibcon#*after write, iclass 21, count 0 2006.197.07:36:32.15#ibcon#*before return 0, iclass 21, count 0 2006.197.07:36:32.15#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.197.07:36:32.15#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.197.07:36:32.15#ibcon#about to clear, iclass 21 cls_cnt 0 2006.197.07:36:32.15#ibcon#cleared, iclass 21 cls_cnt 0 2006.197.07:36:32.15$vc4f8/vabw=wide 2006.197.07:36:32.15#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.197.07:36:32.15#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.197.07:36:32.15#ibcon#ireg 8 cls_cnt 0 2006.197.07:36:32.15#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.197.07:36:32.15#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.197.07:36:32.15#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.197.07:36:32.15#ibcon#enter wrdev, iclass 23, count 0 2006.197.07:36:32.15#ibcon#first serial, iclass 23, count 0 2006.197.07:36:32.15#ibcon#enter sib2, iclass 23, count 0 2006.197.07:36:32.15#ibcon#flushed, iclass 23, count 0 2006.197.07:36:32.15#ibcon#about to write, iclass 23, count 0 2006.197.07:36:32.15#ibcon#wrote, iclass 23, count 0 2006.197.07:36:32.15#ibcon#about to read 3, iclass 23, count 0 2006.197.07:36:32.17#ibcon#read 3, iclass 23, count 0 2006.197.07:36:32.17#ibcon#about to read 4, iclass 23, count 0 2006.197.07:36:32.17#ibcon#read 4, iclass 23, count 0 2006.197.07:36:32.17#ibcon#about to read 5, iclass 23, count 0 2006.197.07:36:32.17#ibcon#read 5, iclass 23, count 0 2006.197.07:36:32.17#ibcon#about to read 6, iclass 23, count 0 2006.197.07:36:32.17#ibcon#read 6, iclass 23, count 0 2006.197.07:36:32.17#ibcon#end of sib2, iclass 23, count 0 2006.197.07:36:32.17#ibcon#*mode == 0, iclass 23, count 0 2006.197.07:36:32.17#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.197.07:36:32.17#ibcon#[25=BW32\r\n] 2006.197.07:36:32.17#ibcon#*before write, iclass 23, count 0 2006.197.07:36:32.17#ibcon#enter sib2, iclass 23, count 0 2006.197.07:36:32.17#ibcon#flushed, iclass 23, count 0 2006.197.07:36:32.17#ibcon#about to write, iclass 23, count 0 2006.197.07:36:32.17#ibcon#wrote, iclass 23, count 0 2006.197.07:36:32.17#ibcon#about to read 3, iclass 23, count 0 2006.197.07:36:32.20#ibcon#read 3, iclass 23, count 0 2006.197.07:36:32.20#ibcon#about to read 4, iclass 23, count 0 2006.197.07:36:32.20#ibcon#read 4, iclass 23, count 0 2006.197.07:36:32.20#ibcon#about to read 5, iclass 23, count 0 2006.197.07:36:32.20#ibcon#read 5, iclass 23, count 0 2006.197.07:36:32.20#ibcon#about to read 6, iclass 23, count 0 2006.197.07:36:32.20#ibcon#read 6, iclass 23, count 0 2006.197.07:36:32.20#ibcon#end of sib2, iclass 23, count 0 2006.197.07:36:32.20#ibcon#*after write, iclass 23, count 0 2006.197.07:36:32.20#ibcon#*before return 0, iclass 23, count 0 2006.197.07:36:32.20#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.197.07:36:32.20#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.197.07:36:32.20#ibcon#about to clear, iclass 23 cls_cnt 0 2006.197.07:36:32.20#ibcon#cleared, iclass 23 cls_cnt 0 2006.197.07:36:32.20$vc4f8/vbbw=wide 2006.197.07:36:32.20#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.197.07:36:32.20#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.197.07:36:32.20#ibcon#ireg 8 cls_cnt 0 2006.197.07:36:32.20#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.197.07:36:32.27#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.197.07:36:32.27#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.197.07:36:32.27#ibcon#enter wrdev, iclass 25, count 0 2006.197.07:36:32.27#ibcon#first serial, iclass 25, count 0 2006.197.07:36:32.27#ibcon#enter sib2, iclass 25, count 0 2006.197.07:36:32.27#ibcon#flushed, iclass 25, count 0 2006.197.07:36:32.27#ibcon#about to write, iclass 25, count 0 2006.197.07:36:32.27#ibcon#wrote, iclass 25, count 0 2006.197.07:36:32.27#ibcon#about to read 3, iclass 25, count 0 2006.197.07:36:32.29#ibcon#read 3, iclass 25, count 0 2006.197.07:36:32.29#ibcon#about to read 4, iclass 25, count 0 2006.197.07:36:32.29#ibcon#read 4, iclass 25, count 0 2006.197.07:36:32.29#ibcon#about to read 5, iclass 25, count 0 2006.197.07:36:32.29#ibcon#read 5, iclass 25, count 0 2006.197.07:36:32.29#ibcon#about to read 6, iclass 25, count 0 2006.197.07:36:32.29#ibcon#read 6, iclass 25, count 0 2006.197.07:36:32.29#ibcon#end of sib2, iclass 25, count 0 2006.197.07:36:32.29#ibcon#*mode == 0, iclass 25, count 0 2006.197.07:36:32.29#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.197.07:36:32.29#ibcon#[27=BW32\r\n] 2006.197.07:36:32.29#ibcon#*before write, iclass 25, count 0 2006.197.07:36:32.29#ibcon#enter sib2, iclass 25, count 0 2006.197.07:36:32.29#ibcon#flushed, iclass 25, count 0 2006.197.07:36:32.29#ibcon#about to write, iclass 25, count 0 2006.197.07:36:32.29#ibcon#wrote, iclass 25, count 0 2006.197.07:36:32.29#ibcon#about to read 3, iclass 25, count 0 2006.197.07:36:32.32#ibcon#read 3, iclass 25, count 0 2006.197.07:36:32.32#ibcon#about to read 4, iclass 25, count 0 2006.197.07:36:32.32#ibcon#read 4, iclass 25, count 0 2006.197.07:36:32.32#ibcon#about to read 5, iclass 25, count 0 2006.197.07:36:32.32#ibcon#read 5, iclass 25, count 0 2006.197.07:36:32.32#ibcon#about to read 6, iclass 25, count 0 2006.197.07:36:32.32#ibcon#read 6, iclass 25, count 0 2006.197.07:36:32.32#ibcon#end of sib2, iclass 25, count 0 2006.197.07:36:32.32#ibcon#*after write, iclass 25, count 0 2006.197.07:36:32.32#ibcon#*before return 0, iclass 25, count 0 2006.197.07:36:32.32#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.197.07:36:32.32#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.197.07:36:32.32#ibcon#about to clear, iclass 25 cls_cnt 0 2006.197.07:36:32.32#ibcon#cleared, iclass 25 cls_cnt 0 2006.197.07:36:32.32$4f8m12a/ifd4f 2006.197.07:36:32.32$ifd4f/lo= 2006.197.07:36:32.32$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.197.07:36:32.32$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.197.07:36:32.32$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.197.07:36:32.32$ifd4f/patch= 2006.197.07:36:32.32$ifd4f/patch=lo1,a1,a2,a3,a4 2006.197.07:36:32.32$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.197.07:36:32.32$ifd4f/patch=lo3,a5,a6,a7,a8 2006.197.07:36:32.32$4f8m12a/"form=m,16.000,1:2 2006.197.07:36:32.32$4f8m12a/"tpicd 2006.197.07:36:32.32$4f8m12a/echo=off 2006.197.07:36:32.32$4f8m12a/xlog=off 2006.197.07:36:32.32:!2006.197.07:37:00 2006.197.07:36:46.14#trakl#Source acquired 2006.197.07:36:48.14#flagr#flagr/antenna,acquired 2006.197.07:37:00.00:preob 2006.197.07:37:01.14/onsource/TRACKING 2006.197.07:37:01.14:!2006.197.07:37:10 2006.197.07:37:10.00:data_valid=on 2006.197.07:37:10.00:midob 2006.197.07:37:10.14/onsource/TRACKING 2006.197.07:37:10.14/wx/25.91,1003.1,97 2006.197.07:37:10.34/cable/+6.3702E-03 2006.197.07:37:11.43/va/01,08,usb,yes,36,38 2006.197.07:37:11.43/va/02,07,usb,yes,37,38 2006.197.07:37:11.43/va/03,06,usb,yes,38,38 2006.197.07:37:11.43/va/04,07,usb,yes,37,40 2006.197.07:37:11.43/va/05,07,usb,yes,42,45 2006.197.07:37:11.43/va/06,06,usb,yes,41,41 2006.197.07:37:11.43/va/07,06,usb,yes,41,41 2006.197.07:37:11.43/va/08,07,usb,yes,39,39 2006.197.07:37:11.66/valo/01,532.99,yes,locked 2006.197.07:37:11.66/valo/02,572.99,yes,locked 2006.197.07:37:11.66/valo/03,672.99,yes,locked 2006.197.07:37:11.66/valo/04,832.99,yes,locked 2006.197.07:37:11.66/valo/05,652.99,yes,locked 2006.197.07:37:11.66/valo/06,772.99,yes,locked 2006.197.07:37:11.66/valo/07,832.99,yes,locked 2006.197.07:37:11.66/valo/08,852.99,yes,locked 2006.197.07:37:12.75/vb/01,04,usb,yes,32,30 2006.197.07:37:12.75/vb/02,04,usb,yes,34,35 2006.197.07:37:12.75/vb/03,04,usb,yes,30,34 2006.197.07:37:12.75/vb/04,04,usb,yes,31,31 2006.197.07:37:12.75/vb/05,04,usb,yes,29,34 2006.197.07:37:12.75/vb/06,04,usb,yes,31,34 2006.197.07:37:12.75/vb/07,04,usb,yes,33,33 2006.197.07:37:12.75/vb/08,04,usb,yes,30,34 2006.197.07:37:12.98/vblo/01,632.99,yes,locked 2006.197.07:37:12.98/vblo/02,640.99,yes,locked 2006.197.07:37:12.98/vblo/03,656.99,yes,locked 2006.197.07:37:12.98/vblo/04,712.99,yes,locked 2006.197.07:37:12.98/vblo/05,744.99,yes,locked 2006.197.07:37:12.98/vblo/06,752.99,yes,locked 2006.197.07:37:12.98/vblo/07,734.99,yes,locked 2006.197.07:37:12.98/vblo/08,744.99,yes,locked 2006.197.07:37:13.13/vabw/8 2006.197.07:37:13.28/vbbw/8 2006.197.07:37:13.37/xfe/off,on,15.2 2006.197.07:37:13.74/ifatt/23,28,28,28 2006.197.07:37:14.10/fmout-gps/S +2.96E-07 2006.197.07:37:14.14:!2006.197.07:38:10 2006.197.07:38:10.00:data_valid=off 2006.197.07:38:10.00:postob 2006.197.07:38:10.17/cable/+6.3728E-03 2006.197.07:38:10.17/wx/25.90,1003.1,97 2006.197.07:38:11.10/fmout-gps/S +2.96E-07 2006.197.07:38:11.10:scan_name=197-0739,k06197,60 2006.197.07:38:11.10:source=0602+673,060752.67,672055.4,2000.0,ccw 2006.197.07:38:11.13#flagr#flagr/antenna,new-source 2006.197.07:38:12.13:checkk5 2006.197.07:38:12.47/chk_autoobs//k5ts1/ autoobs is running! 2006.197.07:38:12.81/chk_autoobs//k5ts2/ autoobs is running! 2006.197.07:38:13.16/chk_autoobs//k5ts3/ autoobs is running! 2006.197.07:38:13.51/chk_autoobs//k5ts4/ autoobs is running! 2006.197.07:38:13.86/chk_obsdata//k5ts1/T1970737??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.07:38:14.19/chk_obsdata//k5ts2/T1970737??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.07:38:14.53/chk_obsdata//k5ts3/T1970737??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.07:38:14.86/chk_obsdata//k5ts4/T1970737??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.07:38:15.53/k5log//k5ts1_log_newline 2006.197.07:38:16.19/k5log//k5ts2_log_newline 2006.197.07:38:16.84/k5log//k5ts3_log_newline 2006.197.07:38:17.51/k5log//k5ts4_log_newline 2006.197.07:38:17.53/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.197.07:38:17.53:4f8m12a=1 2006.197.07:38:17.53$4f8m12a/echo=on 2006.197.07:38:17.53$4f8m12a/pcalon 2006.197.07:38:17.53$pcalon/"no phase cal control is implemented here 2006.197.07:38:17.53$4f8m12a/"tpicd=stop 2006.197.07:38:17.53$4f8m12a/vc4f8 2006.197.07:38:17.53$vc4f8/valo=1,532.99 2006.197.07:38:17.54#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.197.07:38:17.54#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.197.07:38:17.54#ibcon#ireg 17 cls_cnt 0 2006.197.07:38:17.54#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.197.07:38:17.54#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.197.07:38:17.54#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.197.07:38:17.54#ibcon#enter wrdev, iclass 36, count 0 2006.197.07:38:17.54#ibcon#first serial, iclass 36, count 0 2006.197.07:38:17.54#ibcon#enter sib2, iclass 36, count 0 2006.197.07:38:17.54#ibcon#flushed, iclass 36, count 0 2006.197.07:38:17.54#ibcon#about to write, iclass 36, count 0 2006.197.07:38:17.54#ibcon#wrote, iclass 36, count 0 2006.197.07:38:17.54#ibcon#about to read 3, iclass 36, count 0 2006.197.07:38:17.56#ibcon#read 3, iclass 36, count 0 2006.197.07:38:17.56#ibcon#about to read 4, iclass 36, count 0 2006.197.07:38:17.56#ibcon#read 4, iclass 36, count 0 2006.197.07:38:17.56#ibcon#about to read 5, iclass 36, count 0 2006.197.07:38:17.56#ibcon#read 5, iclass 36, count 0 2006.197.07:38:17.56#ibcon#about to read 6, iclass 36, count 0 2006.197.07:38:17.56#ibcon#read 6, iclass 36, count 0 2006.197.07:38:17.56#ibcon#end of sib2, iclass 36, count 0 2006.197.07:38:17.56#ibcon#*mode == 0, iclass 36, count 0 2006.197.07:38:17.56#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.197.07:38:17.56#ibcon#[26=FRQ=01,532.99\r\n] 2006.197.07:38:17.56#ibcon#*before write, iclass 36, count 0 2006.197.07:38:17.56#ibcon#enter sib2, iclass 36, count 0 2006.197.07:38:17.56#ibcon#flushed, iclass 36, count 0 2006.197.07:38:17.56#ibcon#about to write, iclass 36, count 0 2006.197.07:38:17.56#ibcon#wrote, iclass 36, count 0 2006.197.07:38:17.56#ibcon#about to read 3, iclass 36, count 0 2006.197.07:38:17.61#ibcon#read 3, iclass 36, count 0 2006.197.07:38:17.61#ibcon#about to read 4, iclass 36, count 0 2006.197.07:38:17.61#ibcon#read 4, iclass 36, count 0 2006.197.07:38:17.61#ibcon#about to read 5, iclass 36, count 0 2006.197.07:38:17.61#ibcon#read 5, iclass 36, count 0 2006.197.07:38:17.61#ibcon#about to read 6, iclass 36, count 0 2006.197.07:38:17.61#ibcon#read 6, iclass 36, count 0 2006.197.07:38:17.61#ibcon#end of sib2, iclass 36, count 0 2006.197.07:38:17.61#ibcon#*after write, iclass 36, count 0 2006.197.07:38:17.61#ibcon#*before return 0, iclass 36, count 0 2006.197.07:38:17.61#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.197.07:38:17.61#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.197.07:38:17.61#ibcon#about to clear, iclass 36 cls_cnt 0 2006.197.07:38:17.61#ibcon#cleared, iclass 36 cls_cnt 0 2006.197.07:38:17.61$vc4f8/va=1,8 2006.197.07:38:17.61#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.197.07:38:17.61#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.197.07:38:17.61#ibcon#ireg 11 cls_cnt 2 2006.197.07:38:17.61#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.197.07:38:17.61#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.197.07:38:17.61#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.197.07:38:17.61#ibcon#enter wrdev, iclass 38, count 2 2006.197.07:38:17.61#ibcon#first serial, iclass 38, count 2 2006.197.07:38:17.61#ibcon#enter sib2, iclass 38, count 2 2006.197.07:38:17.61#ibcon#flushed, iclass 38, count 2 2006.197.07:38:17.61#ibcon#about to write, iclass 38, count 2 2006.197.07:38:17.61#ibcon#wrote, iclass 38, count 2 2006.197.07:38:17.61#ibcon#about to read 3, iclass 38, count 2 2006.197.07:38:17.63#ibcon#read 3, iclass 38, count 2 2006.197.07:38:17.63#ibcon#about to read 4, iclass 38, count 2 2006.197.07:38:17.63#ibcon#read 4, iclass 38, count 2 2006.197.07:38:17.63#ibcon#about to read 5, iclass 38, count 2 2006.197.07:38:17.63#ibcon#read 5, iclass 38, count 2 2006.197.07:38:17.63#ibcon#about to read 6, iclass 38, count 2 2006.197.07:38:17.63#ibcon#read 6, iclass 38, count 2 2006.197.07:38:17.63#ibcon#end of sib2, iclass 38, count 2 2006.197.07:38:17.63#ibcon#*mode == 0, iclass 38, count 2 2006.197.07:38:17.63#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.197.07:38:17.63#ibcon#[25=AT01-08\r\n] 2006.197.07:38:17.63#ibcon#*before write, iclass 38, count 2 2006.197.07:38:17.63#ibcon#enter sib2, iclass 38, count 2 2006.197.07:38:17.63#ibcon#flushed, iclass 38, count 2 2006.197.07:38:17.63#ibcon#about to write, iclass 38, count 2 2006.197.07:38:17.63#ibcon#wrote, iclass 38, count 2 2006.197.07:38:17.63#ibcon#about to read 3, iclass 38, count 2 2006.197.07:38:17.66#ibcon#read 3, iclass 38, count 2 2006.197.07:38:17.66#ibcon#about to read 4, iclass 38, count 2 2006.197.07:38:17.66#ibcon#read 4, iclass 38, count 2 2006.197.07:38:17.66#ibcon#about to read 5, iclass 38, count 2 2006.197.07:38:17.66#ibcon#read 5, iclass 38, count 2 2006.197.07:38:17.66#ibcon#about to read 6, iclass 38, count 2 2006.197.07:38:17.66#ibcon#read 6, iclass 38, count 2 2006.197.07:38:17.66#ibcon#end of sib2, iclass 38, count 2 2006.197.07:38:17.66#ibcon#*after write, iclass 38, count 2 2006.197.07:38:17.66#ibcon#*before return 0, iclass 38, count 2 2006.197.07:38:17.66#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.197.07:38:17.66#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.197.07:38:17.66#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.197.07:38:17.66#ibcon#ireg 7 cls_cnt 0 2006.197.07:38:17.66#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.197.07:38:17.78#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.197.07:38:17.78#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.197.07:38:17.78#ibcon#enter wrdev, iclass 38, count 0 2006.197.07:38:17.78#ibcon#first serial, iclass 38, count 0 2006.197.07:38:17.78#ibcon#enter sib2, iclass 38, count 0 2006.197.07:38:17.78#ibcon#flushed, iclass 38, count 0 2006.197.07:38:17.78#ibcon#about to write, iclass 38, count 0 2006.197.07:38:17.78#ibcon#wrote, iclass 38, count 0 2006.197.07:38:17.78#ibcon#about to read 3, iclass 38, count 0 2006.197.07:38:17.80#ibcon#read 3, iclass 38, count 0 2006.197.07:38:17.80#ibcon#about to read 4, iclass 38, count 0 2006.197.07:38:17.80#ibcon#read 4, iclass 38, count 0 2006.197.07:38:17.80#ibcon#about to read 5, iclass 38, count 0 2006.197.07:38:17.80#ibcon#read 5, iclass 38, count 0 2006.197.07:38:17.80#ibcon#about to read 6, iclass 38, count 0 2006.197.07:38:17.80#ibcon#read 6, iclass 38, count 0 2006.197.07:38:17.80#ibcon#end of sib2, iclass 38, count 0 2006.197.07:38:17.80#ibcon#*mode == 0, iclass 38, count 0 2006.197.07:38:17.80#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.197.07:38:17.80#ibcon#[25=USB\r\n] 2006.197.07:38:17.80#ibcon#*before write, iclass 38, count 0 2006.197.07:38:17.80#ibcon#enter sib2, iclass 38, count 0 2006.197.07:38:17.80#ibcon#flushed, iclass 38, count 0 2006.197.07:38:17.80#ibcon#about to write, iclass 38, count 0 2006.197.07:38:17.80#ibcon#wrote, iclass 38, count 0 2006.197.07:38:17.80#ibcon#about to read 3, iclass 38, count 0 2006.197.07:38:17.83#ibcon#read 3, iclass 38, count 0 2006.197.07:38:17.83#ibcon#about to read 4, iclass 38, count 0 2006.197.07:38:17.83#ibcon#read 4, iclass 38, count 0 2006.197.07:38:17.83#ibcon#about to read 5, iclass 38, count 0 2006.197.07:38:17.83#ibcon#read 5, iclass 38, count 0 2006.197.07:38:17.83#ibcon#about to read 6, iclass 38, count 0 2006.197.07:38:17.83#ibcon#read 6, iclass 38, count 0 2006.197.07:38:17.83#ibcon#end of sib2, iclass 38, count 0 2006.197.07:38:17.83#ibcon#*after write, iclass 38, count 0 2006.197.07:38:17.83#ibcon#*before return 0, iclass 38, count 0 2006.197.07:38:17.83#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.197.07:38:17.83#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.197.07:38:17.83#ibcon#about to clear, iclass 38 cls_cnt 0 2006.197.07:38:17.83#ibcon#cleared, iclass 38 cls_cnt 0 2006.197.07:38:17.83$vc4f8/valo=2,572.99 2006.197.07:38:17.83#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.197.07:38:17.83#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.197.07:38:17.83#ibcon#ireg 17 cls_cnt 0 2006.197.07:38:17.83#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.197.07:38:17.83#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.197.07:38:17.83#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.197.07:38:17.83#ibcon#enter wrdev, iclass 40, count 0 2006.197.07:38:17.83#ibcon#first serial, iclass 40, count 0 2006.197.07:38:17.83#ibcon#enter sib2, iclass 40, count 0 2006.197.07:38:17.83#ibcon#flushed, iclass 40, count 0 2006.197.07:38:17.83#ibcon#about to write, iclass 40, count 0 2006.197.07:38:17.83#ibcon#wrote, iclass 40, count 0 2006.197.07:38:17.83#ibcon#about to read 3, iclass 40, count 0 2006.197.07:38:17.85#ibcon#read 3, iclass 40, count 0 2006.197.07:38:17.85#ibcon#about to read 4, iclass 40, count 0 2006.197.07:38:17.85#ibcon#read 4, iclass 40, count 0 2006.197.07:38:17.85#ibcon#about to read 5, iclass 40, count 0 2006.197.07:38:17.85#ibcon#read 5, iclass 40, count 0 2006.197.07:38:17.85#ibcon#about to read 6, iclass 40, count 0 2006.197.07:38:17.85#ibcon#read 6, iclass 40, count 0 2006.197.07:38:17.85#ibcon#end of sib2, iclass 40, count 0 2006.197.07:38:17.85#ibcon#*mode == 0, iclass 40, count 0 2006.197.07:38:17.85#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.197.07:38:17.85#ibcon#[26=FRQ=02,572.99\r\n] 2006.197.07:38:17.85#ibcon#*before write, iclass 40, count 0 2006.197.07:38:17.85#ibcon#enter sib2, iclass 40, count 0 2006.197.07:38:17.85#ibcon#flushed, iclass 40, count 0 2006.197.07:38:17.85#ibcon#about to write, iclass 40, count 0 2006.197.07:38:17.85#ibcon#wrote, iclass 40, count 0 2006.197.07:38:17.85#ibcon#about to read 3, iclass 40, count 0 2006.197.07:38:17.89#ibcon#read 3, iclass 40, count 0 2006.197.07:38:17.89#ibcon#about to read 4, iclass 40, count 0 2006.197.07:38:17.89#ibcon#read 4, iclass 40, count 0 2006.197.07:38:17.89#ibcon#about to read 5, iclass 40, count 0 2006.197.07:38:17.89#ibcon#read 5, iclass 40, count 0 2006.197.07:38:17.89#ibcon#about to read 6, iclass 40, count 0 2006.197.07:38:17.89#ibcon#read 6, iclass 40, count 0 2006.197.07:38:17.89#ibcon#end of sib2, iclass 40, count 0 2006.197.07:38:17.89#ibcon#*after write, iclass 40, count 0 2006.197.07:38:17.89#ibcon#*before return 0, iclass 40, count 0 2006.197.07:38:17.89#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.197.07:38:17.89#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.197.07:38:17.89#ibcon#about to clear, iclass 40 cls_cnt 0 2006.197.07:38:17.89#ibcon#cleared, iclass 40 cls_cnt 0 2006.197.07:38:17.89$vc4f8/va=2,7 2006.197.07:38:17.89#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.197.07:38:17.89#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.197.07:38:17.89#ibcon#ireg 11 cls_cnt 2 2006.197.07:38:17.89#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.197.07:38:17.95#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.197.07:38:17.95#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.197.07:38:17.95#ibcon#enter wrdev, iclass 4, count 2 2006.197.07:38:17.95#ibcon#first serial, iclass 4, count 2 2006.197.07:38:17.95#ibcon#enter sib2, iclass 4, count 2 2006.197.07:38:17.95#ibcon#flushed, iclass 4, count 2 2006.197.07:38:17.95#ibcon#about to write, iclass 4, count 2 2006.197.07:38:17.95#ibcon#wrote, iclass 4, count 2 2006.197.07:38:17.95#ibcon#about to read 3, iclass 4, count 2 2006.197.07:38:17.97#ibcon#read 3, iclass 4, count 2 2006.197.07:38:17.97#ibcon#about to read 4, iclass 4, count 2 2006.197.07:38:17.97#ibcon#read 4, iclass 4, count 2 2006.197.07:38:17.97#ibcon#about to read 5, iclass 4, count 2 2006.197.07:38:17.97#ibcon#read 5, iclass 4, count 2 2006.197.07:38:17.97#ibcon#about to read 6, iclass 4, count 2 2006.197.07:38:17.97#ibcon#read 6, iclass 4, count 2 2006.197.07:38:17.97#ibcon#end of sib2, iclass 4, count 2 2006.197.07:38:17.97#ibcon#*mode == 0, iclass 4, count 2 2006.197.07:38:17.97#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.197.07:38:17.97#ibcon#[25=AT02-07\r\n] 2006.197.07:38:17.97#ibcon#*before write, iclass 4, count 2 2006.197.07:38:17.97#ibcon#enter sib2, iclass 4, count 2 2006.197.07:38:17.97#ibcon#flushed, iclass 4, count 2 2006.197.07:38:17.97#ibcon#about to write, iclass 4, count 2 2006.197.07:38:17.97#ibcon#wrote, iclass 4, count 2 2006.197.07:38:17.97#ibcon#about to read 3, iclass 4, count 2 2006.197.07:38:18.00#ibcon#read 3, iclass 4, count 2 2006.197.07:38:18.00#ibcon#about to read 4, iclass 4, count 2 2006.197.07:38:18.00#ibcon#read 4, iclass 4, count 2 2006.197.07:38:18.00#ibcon#about to read 5, iclass 4, count 2 2006.197.07:38:18.00#ibcon#read 5, iclass 4, count 2 2006.197.07:38:18.00#ibcon#about to read 6, iclass 4, count 2 2006.197.07:38:18.00#ibcon#read 6, iclass 4, count 2 2006.197.07:38:18.00#ibcon#end of sib2, iclass 4, count 2 2006.197.07:38:18.00#ibcon#*after write, iclass 4, count 2 2006.197.07:38:18.00#ibcon#*before return 0, iclass 4, count 2 2006.197.07:38:18.00#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.197.07:38:18.00#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.197.07:38:18.00#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.197.07:38:18.00#ibcon#ireg 7 cls_cnt 0 2006.197.07:38:18.00#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.197.07:38:18.12#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.197.07:38:18.12#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.197.07:38:18.12#ibcon#enter wrdev, iclass 4, count 0 2006.197.07:38:18.12#ibcon#first serial, iclass 4, count 0 2006.197.07:38:18.12#ibcon#enter sib2, iclass 4, count 0 2006.197.07:38:18.12#ibcon#flushed, iclass 4, count 0 2006.197.07:38:18.12#ibcon#about to write, iclass 4, count 0 2006.197.07:38:18.12#ibcon#wrote, iclass 4, count 0 2006.197.07:38:18.12#ibcon#about to read 3, iclass 4, count 0 2006.197.07:38:18.14#ibcon#read 3, iclass 4, count 0 2006.197.07:38:18.14#ibcon#about to read 4, iclass 4, count 0 2006.197.07:38:18.14#ibcon#read 4, iclass 4, count 0 2006.197.07:38:18.14#ibcon#about to read 5, iclass 4, count 0 2006.197.07:38:18.14#ibcon#read 5, iclass 4, count 0 2006.197.07:38:18.14#ibcon#about to read 6, iclass 4, count 0 2006.197.07:38:18.14#ibcon#read 6, iclass 4, count 0 2006.197.07:38:18.14#ibcon#end of sib2, iclass 4, count 0 2006.197.07:38:18.14#ibcon#*mode == 0, iclass 4, count 0 2006.197.07:38:18.14#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.197.07:38:18.14#ibcon#[25=USB\r\n] 2006.197.07:38:18.14#ibcon#*before write, iclass 4, count 0 2006.197.07:38:18.14#ibcon#enter sib2, iclass 4, count 0 2006.197.07:38:18.14#ibcon#flushed, iclass 4, count 0 2006.197.07:38:18.14#ibcon#about to write, iclass 4, count 0 2006.197.07:38:18.14#ibcon#wrote, iclass 4, count 0 2006.197.07:38:18.14#ibcon#about to read 3, iclass 4, count 0 2006.197.07:38:18.17#ibcon#read 3, iclass 4, count 0 2006.197.07:38:18.17#ibcon#about to read 4, iclass 4, count 0 2006.197.07:38:18.17#ibcon#read 4, iclass 4, count 0 2006.197.07:38:18.17#ibcon#about to read 5, iclass 4, count 0 2006.197.07:38:18.17#ibcon#read 5, iclass 4, count 0 2006.197.07:38:18.17#ibcon#about to read 6, iclass 4, count 0 2006.197.07:38:18.17#ibcon#read 6, iclass 4, count 0 2006.197.07:38:18.17#ibcon#end of sib2, iclass 4, count 0 2006.197.07:38:18.17#ibcon#*after write, iclass 4, count 0 2006.197.07:38:18.17#ibcon#*before return 0, iclass 4, count 0 2006.197.07:38:18.17#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.197.07:38:18.17#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.197.07:38:18.17#ibcon#about to clear, iclass 4 cls_cnt 0 2006.197.07:38:18.17#ibcon#cleared, iclass 4 cls_cnt 0 2006.197.07:38:18.17$vc4f8/valo=3,672.99 2006.197.07:38:18.17#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.197.07:38:18.17#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.197.07:38:18.17#ibcon#ireg 17 cls_cnt 0 2006.197.07:38:18.17#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.197.07:38:18.17#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.197.07:38:18.17#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.197.07:38:18.17#ibcon#enter wrdev, iclass 6, count 0 2006.197.07:38:18.17#ibcon#first serial, iclass 6, count 0 2006.197.07:38:18.17#ibcon#enter sib2, iclass 6, count 0 2006.197.07:38:18.17#ibcon#flushed, iclass 6, count 0 2006.197.07:38:18.17#ibcon#about to write, iclass 6, count 0 2006.197.07:38:18.17#ibcon#wrote, iclass 6, count 0 2006.197.07:38:18.17#ibcon#about to read 3, iclass 6, count 0 2006.197.07:38:18.19#ibcon#read 3, iclass 6, count 0 2006.197.07:38:18.19#ibcon#about to read 4, iclass 6, count 0 2006.197.07:38:18.19#ibcon#read 4, iclass 6, count 0 2006.197.07:38:18.19#ibcon#about to read 5, iclass 6, count 0 2006.197.07:38:18.19#ibcon#read 5, iclass 6, count 0 2006.197.07:38:18.19#ibcon#about to read 6, iclass 6, count 0 2006.197.07:38:18.19#ibcon#read 6, iclass 6, count 0 2006.197.07:38:18.19#ibcon#end of sib2, iclass 6, count 0 2006.197.07:38:18.19#ibcon#*mode == 0, iclass 6, count 0 2006.197.07:38:18.19#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.197.07:38:18.19#ibcon#[26=FRQ=03,672.99\r\n] 2006.197.07:38:18.19#ibcon#*before write, iclass 6, count 0 2006.197.07:38:18.19#ibcon#enter sib2, iclass 6, count 0 2006.197.07:38:18.19#ibcon#flushed, iclass 6, count 0 2006.197.07:38:18.19#ibcon#about to write, iclass 6, count 0 2006.197.07:38:18.19#ibcon#wrote, iclass 6, count 0 2006.197.07:38:18.19#ibcon#about to read 3, iclass 6, count 0 2006.197.07:38:18.23#ibcon#read 3, iclass 6, count 0 2006.197.07:38:18.23#ibcon#about to read 4, iclass 6, count 0 2006.197.07:38:18.23#ibcon#read 4, iclass 6, count 0 2006.197.07:38:18.23#ibcon#about to read 5, iclass 6, count 0 2006.197.07:38:18.23#ibcon#read 5, iclass 6, count 0 2006.197.07:38:18.23#ibcon#about to read 6, iclass 6, count 0 2006.197.07:38:18.23#ibcon#read 6, iclass 6, count 0 2006.197.07:38:18.23#ibcon#end of sib2, iclass 6, count 0 2006.197.07:38:18.23#ibcon#*after write, iclass 6, count 0 2006.197.07:38:18.23#ibcon#*before return 0, iclass 6, count 0 2006.197.07:38:18.23#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.197.07:38:18.23#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.197.07:38:18.23#ibcon#about to clear, iclass 6 cls_cnt 0 2006.197.07:38:18.23#ibcon#cleared, iclass 6 cls_cnt 0 2006.197.07:38:18.23$vc4f8/va=3,6 2006.197.07:38:18.23#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.197.07:38:18.23#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.197.07:38:18.23#ibcon#ireg 11 cls_cnt 2 2006.197.07:38:18.23#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.197.07:38:18.29#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.197.07:38:18.29#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.197.07:38:18.29#ibcon#enter wrdev, iclass 10, count 2 2006.197.07:38:18.29#ibcon#first serial, iclass 10, count 2 2006.197.07:38:18.29#ibcon#enter sib2, iclass 10, count 2 2006.197.07:38:18.29#ibcon#flushed, iclass 10, count 2 2006.197.07:38:18.29#ibcon#about to write, iclass 10, count 2 2006.197.07:38:18.29#ibcon#wrote, iclass 10, count 2 2006.197.07:38:18.29#ibcon#about to read 3, iclass 10, count 2 2006.197.07:38:18.31#ibcon#read 3, iclass 10, count 2 2006.197.07:38:18.31#ibcon#about to read 4, iclass 10, count 2 2006.197.07:38:18.31#ibcon#read 4, iclass 10, count 2 2006.197.07:38:18.31#ibcon#about to read 5, iclass 10, count 2 2006.197.07:38:18.31#ibcon#read 5, iclass 10, count 2 2006.197.07:38:18.31#ibcon#about to read 6, iclass 10, count 2 2006.197.07:38:18.31#ibcon#read 6, iclass 10, count 2 2006.197.07:38:18.31#ibcon#end of sib2, iclass 10, count 2 2006.197.07:38:18.31#ibcon#*mode == 0, iclass 10, count 2 2006.197.07:38:18.31#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.197.07:38:18.31#ibcon#[25=AT03-06\r\n] 2006.197.07:38:18.31#ibcon#*before write, iclass 10, count 2 2006.197.07:38:18.31#ibcon#enter sib2, iclass 10, count 2 2006.197.07:38:18.31#ibcon#flushed, iclass 10, count 2 2006.197.07:38:18.31#ibcon#about to write, iclass 10, count 2 2006.197.07:38:18.31#ibcon#wrote, iclass 10, count 2 2006.197.07:38:18.31#ibcon#about to read 3, iclass 10, count 2 2006.197.07:38:18.34#ibcon#read 3, iclass 10, count 2 2006.197.07:38:18.34#ibcon#about to read 4, iclass 10, count 2 2006.197.07:38:18.34#ibcon#read 4, iclass 10, count 2 2006.197.07:38:18.34#ibcon#about to read 5, iclass 10, count 2 2006.197.07:38:18.34#ibcon#read 5, iclass 10, count 2 2006.197.07:38:18.34#ibcon#about to read 6, iclass 10, count 2 2006.197.07:38:18.34#ibcon#read 6, iclass 10, count 2 2006.197.07:38:18.34#ibcon#end of sib2, iclass 10, count 2 2006.197.07:38:18.34#ibcon#*after write, iclass 10, count 2 2006.197.07:38:18.34#ibcon#*before return 0, iclass 10, count 2 2006.197.07:38:18.34#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.197.07:38:18.34#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.197.07:38:18.34#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.197.07:38:18.34#ibcon#ireg 7 cls_cnt 0 2006.197.07:38:18.34#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.197.07:38:18.46#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.197.07:38:18.46#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.197.07:38:18.46#ibcon#enter wrdev, iclass 10, count 0 2006.197.07:38:18.46#ibcon#first serial, iclass 10, count 0 2006.197.07:38:18.46#ibcon#enter sib2, iclass 10, count 0 2006.197.07:38:18.46#ibcon#flushed, iclass 10, count 0 2006.197.07:38:18.46#ibcon#about to write, iclass 10, count 0 2006.197.07:38:18.46#ibcon#wrote, iclass 10, count 0 2006.197.07:38:18.46#ibcon#about to read 3, iclass 10, count 0 2006.197.07:38:18.48#ibcon#read 3, iclass 10, count 0 2006.197.07:38:18.48#ibcon#about to read 4, iclass 10, count 0 2006.197.07:38:18.48#ibcon#read 4, iclass 10, count 0 2006.197.07:38:18.48#ibcon#about to read 5, iclass 10, count 0 2006.197.07:38:18.48#ibcon#read 5, iclass 10, count 0 2006.197.07:38:18.48#ibcon#about to read 6, iclass 10, count 0 2006.197.07:38:18.48#ibcon#read 6, iclass 10, count 0 2006.197.07:38:18.48#ibcon#end of sib2, iclass 10, count 0 2006.197.07:38:18.48#ibcon#*mode == 0, iclass 10, count 0 2006.197.07:38:18.48#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.197.07:38:18.48#ibcon#[25=USB\r\n] 2006.197.07:38:18.48#ibcon#*before write, iclass 10, count 0 2006.197.07:38:18.48#ibcon#enter sib2, iclass 10, count 0 2006.197.07:38:18.48#ibcon#flushed, iclass 10, count 0 2006.197.07:38:18.48#ibcon#about to write, iclass 10, count 0 2006.197.07:38:18.48#ibcon#wrote, iclass 10, count 0 2006.197.07:38:18.48#ibcon#about to read 3, iclass 10, count 0 2006.197.07:38:18.51#ibcon#read 3, iclass 10, count 0 2006.197.07:38:18.51#ibcon#about to read 4, iclass 10, count 0 2006.197.07:38:18.51#ibcon#read 4, iclass 10, count 0 2006.197.07:38:18.51#ibcon#about to read 5, iclass 10, count 0 2006.197.07:38:18.51#ibcon#read 5, iclass 10, count 0 2006.197.07:38:18.51#ibcon#about to read 6, iclass 10, count 0 2006.197.07:38:18.51#ibcon#read 6, iclass 10, count 0 2006.197.07:38:18.51#ibcon#end of sib2, iclass 10, count 0 2006.197.07:38:18.51#ibcon#*after write, iclass 10, count 0 2006.197.07:38:18.51#ibcon#*before return 0, iclass 10, count 0 2006.197.07:38:18.51#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.197.07:38:18.51#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.197.07:38:18.51#ibcon#about to clear, iclass 10 cls_cnt 0 2006.197.07:38:18.51#ibcon#cleared, iclass 10 cls_cnt 0 2006.197.07:38:18.51$vc4f8/valo=4,832.99 2006.197.07:38:18.51#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.197.07:38:18.51#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.197.07:38:18.51#ibcon#ireg 17 cls_cnt 0 2006.197.07:38:18.51#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.197.07:38:18.51#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.197.07:38:18.51#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.197.07:38:18.51#ibcon#enter wrdev, iclass 12, count 0 2006.197.07:38:18.51#ibcon#first serial, iclass 12, count 0 2006.197.07:38:18.51#ibcon#enter sib2, iclass 12, count 0 2006.197.07:38:18.51#ibcon#flushed, iclass 12, count 0 2006.197.07:38:18.51#ibcon#about to write, iclass 12, count 0 2006.197.07:38:18.51#ibcon#wrote, iclass 12, count 0 2006.197.07:38:18.51#ibcon#about to read 3, iclass 12, count 0 2006.197.07:38:18.53#ibcon#read 3, iclass 12, count 0 2006.197.07:38:18.53#ibcon#about to read 4, iclass 12, count 0 2006.197.07:38:18.53#ibcon#read 4, iclass 12, count 0 2006.197.07:38:18.53#ibcon#about to read 5, iclass 12, count 0 2006.197.07:38:18.53#ibcon#read 5, iclass 12, count 0 2006.197.07:38:18.53#ibcon#about to read 6, iclass 12, count 0 2006.197.07:38:18.53#ibcon#read 6, iclass 12, count 0 2006.197.07:38:18.53#ibcon#end of sib2, iclass 12, count 0 2006.197.07:38:18.53#ibcon#*mode == 0, iclass 12, count 0 2006.197.07:38:18.53#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.197.07:38:18.53#ibcon#[26=FRQ=04,832.99\r\n] 2006.197.07:38:18.53#ibcon#*before write, iclass 12, count 0 2006.197.07:38:18.53#ibcon#enter sib2, iclass 12, count 0 2006.197.07:38:18.53#ibcon#flushed, iclass 12, count 0 2006.197.07:38:18.53#ibcon#about to write, iclass 12, count 0 2006.197.07:38:18.53#ibcon#wrote, iclass 12, count 0 2006.197.07:38:18.53#ibcon#about to read 3, iclass 12, count 0 2006.197.07:38:18.57#ibcon#read 3, iclass 12, count 0 2006.197.07:38:18.57#ibcon#about to read 4, iclass 12, count 0 2006.197.07:38:18.57#ibcon#read 4, iclass 12, count 0 2006.197.07:38:18.57#ibcon#about to read 5, iclass 12, count 0 2006.197.07:38:18.57#ibcon#read 5, iclass 12, count 0 2006.197.07:38:18.57#ibcon#about to read 6, iclass 12, count 0 2006.197.07:38:18.57#ibcon#read 6, iclass 12, count 0 2006.197.07:38:18.57#ibcon#end of sib2, iclass 12, count 0 2006.197.07:38:18.57#ibcon#*after write, iclass 12, count 0 2006.197.07:38:18.57#ibcon#*before return 0, iclass 12, count 0 2006.197.07:38:18.57#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.197.07:38:18.57#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.197.07:38:18.57#ibcon#about to clear, iclass 12 cls_cnt 0 2006.197.07:38:18.57#ibcon#cleared, iclass 12 cls_cnt 0 2006.197.07:38:18.57$vc4f8/va=4,7 2006.197.07:38:18.57#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.197.07:38:18.57#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.197.07:38:18.57#ibcon#ireg 11 cls_cnt 2 2006.197.07:38:18.57#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.197.07:38:18.63#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.197.07:38:18.63#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.197.07:38:18.63#ibcon#enter wrdev, iclass 14, count 2 2006.197.07:38:18.63#ibcon#first serial, iclass 14, count 2 2006.197.07:38:18.63#ibcon#enter sib2, iclass 14, count 2 2006.197.07:38:18.63#ibcon#flushed, iclass 14, count 2 2006.197.07:38:18.63#ibcon#about to write, iclass 14, count 2 2006.197.07:38:18.63#ibcon#wrote, iclass 14, count 2 2006.197.07:38:18.63#ibcon#about to read 3, iclass 14, count 2 2006.197.07:38:18.65#ibcon#read 3, iclass 14, count 2 2006.197.07:38:18.65#ibcon#about to read 4, iclass 14, count 2 2006.197.07:38:18.65#ibcon#read 4, iclass 14, count 2 2006.197.07:38:18.65#ibcon#about to read 5, iclass 14, count 2 2006.197.07:38:18.65#ibcon#read 5, iclass 14, count 2 2006.197.07:38:18.65#ibcon#about to read 6, iclass 14, count 2 2006.197.07:38:18.65#ibcon#read 6, iclass 14, count 2 2006.197.07:38:18.65#ibcon#end of sib2, iclass 14, count 2 2006.197.07:38:18.65#ibcon#*mode == 0, iclass 14, count 2 2006.197.07:38:18.65#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.197.07:38:18.65#ibcon#[25=AT04-07\r\n] 2006.197.07:38:18.65#ibcon#*before write, iclass 14, count 2 2006.197.07:38:18.65#ibcon#enter sib2, iclass 14, count 2 2006.197.07:38:18.65#ibcon#flushed, iclass 14, count 2 2006.197.07:38:18.65#ibcon#about to write, iclass 14, count 2 2006.197.07:38:18.65#ibcon#wrote, iclass 14, count 2 2006.197.07:38:18.65#ibcon#about to read 3, iclass 14, count 2 2006.197.07:38:18.68#ibcon#read 3, iclass 14, count 2 2006.197.07:38:18.68#ibcon#about to read 4, iclass 14, count 2 2006.197.07:38:18.68#ibcon#read 4, iclass 14, count 2 2006.197.07:38:18.68#ibcon#about to read 5, iclass 14, count 2 2006.197.07:38:18.68#ibcon#read 5, iclass 14, count 2 2006.197.07:38:18.68#ibcon#about to read 6, iclass 14, count 2 2006.197.07:38:18.68#ibcon#read 6, iclass 14, count 2 2006.197.07:38:18.68#ibcon#end of sib2, iclass 14, count 2 2006.197.07:38:18.68#ibcon#*after write, iclass 14, count 2 2006.197.07:38:18.68#ibcon#*before return 0, iclass 14, count 2 2006.197.07:38:18.68#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.197.07:38:18.68#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.197.07:38:18.68#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.197.07:38:18.68#ibcon#ireg 7 cls_cnt 0 2006.197.07:38:18.68#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.197.07:38:18.80#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.197.07:38:18.80#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.197.07:38:18.80#ibcon#enter wrdev, iclass 14, count 0 2006.197.07:38:18.80#ibcon#first serial, iclass 14, count 0 2006.197.07:38:18.80#ibcon#enter sib2, iclass 14, count 0 2006.197.07:38:18.80#ibcon#flushed, iclass 14, count 0 2006.197.07:38:18.80#ibcon#about to write, iclass 14, count 0 2006.197.07:38:18.80#ibcon#wrote, iclass 14, count 0 2006.197.07:38:18.80#ibcon#about to read 3, iclass 14, count 0 2006.197.07:38:18.82#ibcon#read 3, iclass 14, count 0 2006.197.07:38:18.82#ibcon#about to read 4, iclass 14, count 0 2006.197.07:38:18.82#ibcon#read 4, iclass 14, count 0 2006.197.07:38:18.82#ibcon#about to read 5, iclass 14, count 0 2006.197.07:38:18.82#ibcon#read 5, iclass 14, count 0 2006.197.07:38:18.82#ibcon#about to read 6, iclass 14, count 0 2006.197.07:38:18.82#ibcon#read 6, iclass 14, count 0 2006.197.07:38:18.82#ibcon#end of sib2, iclass 14, count 0 2006.197.07:38:18.82#ibcon#*mode == 0, iclass 14, count 0 2006.197.07:38:18.82#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.197.07:38:18.82#ibcon#[25=USB\r\n] 2006.197.07:38:18.82#ibcon#*before write, iclass 14, count 0 2006.197.07:38:18.82#ibcon#enter sib2, iclass 14, count 0 2006.197.07:38:18.82#ibcon#flushed, iclass 14, count 0 2006.197.07:38:18.82#ibcon#about to write, iclass 14, count 0 2006.197.07:38:18.82#ibcon#wrote, iclass 14, count 0 2006.197.07:38:18.82#ibcon#about to read 3, iclass 14, count 0 2006.197.07:38:18.85#ibcon#read 3, iclass 14, count 0 2006.197.07:38:18.85#ibcon#about to read 4, iclass 14, count 0 2006.197.07:38:18.85#ibcon#read 4, iclass 14, count 0 2006.197.07:38:18.85#ibcon#about to read 5, iclass 14, count 0 2006.197.07:38:18.85#ibcon#read 5, iclass 14, count 0 2006.197.07:38:18.85#ibcon#about to read 6, iclass 14, count 0 2006.197.07:38:18.85#ibcon#read 6, iclass 14, count 0 2006.197.07:38:18.85#ibcon#end of sib2, iclass 14, count 0 2006.197.07:38:18.85#ibcon#*after write, iclass 14, count 0 2006.197.07:38:18.85#ibcon#*before return 0, iclass 14, count 0 2006.197.07:38:18.85#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.197.07:38:18.85#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.197.07:38:18.85#ibcon#about to clear, iclass 14 cls_cnt 0 2006.197.07:38:18.85#ibcon#cleared, iclass 14 cls_cnt 0 2006.197.07:38:18.85$vc4f8/valo=5,652.99 2006.197.07:38:18.85#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.197.07:38:18.85#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.197.07:38:18.85#ibcon#ireg 17 cls_cnt 0 2006.197.07:38:18.85#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.197.07:38:18.85#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.197.07:38:18.85#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.197.07:38:18.85#ibcon#enter wrdev, iclass 16, count 0 2006.197.07:38:18.85#ibcon#first serial, iclass 16, count 0 2006.197.07:38:18.85#ibcon#enter sib2, iclass 16, count 0 2006.197.07:38:18.85#ibcon#flushed, iclass 16, count 0 2006.197.07:38:18.85#ibcon#about to write, iclass 16, count 0 2006.197.07:38:18.85#ibcon#wrote, iclass 16, count 0 2006.197.07:38:18.85#ibcon#about to read 3, iclass 16, count 0 2006.197.07:38:18.87#ibcon#read 3, iclass 16, count 0 2006.197.07:38:18.87#ibcon#about to read 4, iclass 16, count 0 2006.197.07:38:18.87#ibcon#read 4, iclass 16, count 0 2006.197.07:38:18.87#ibcon#about to read 5, iclass 16, count 0 2006.197.07:38:18.87#ibcon#read 5, iclass 16, count 0 2006.197.07:38:18.87#ibcon#about to read 6, iclass 16, count 0 2006.197.07:38:18.87#ibcon#read 6, iclass 16, count 0 2006.197.07:38:18.87#ibcon#end of sib2, iclass 16, count 0 2006.197.07:38:18.87#ibcon#*mode == 0, iclass 16, count 0 2006.197.07:38:18.87#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.197.07:38:18.87#ibcon#[26=FRQ=05,652.99\r\n] 2006.197.07:38:18.87#ibcon#*before write, iclass 16, count 0 2006.197.07:38:18.87#ibcon#enter sib2, iclass 16, count 0 2006.197.07:38:18.87#ibcon#flushed, iclass 16, count 0 2006.197.07:38:18.87#ibcon#about to write, iclass 16, count 0 2006.197.07:38:18.87#ibcon#wrote, iclass 16, count 0 2006.197.07:38:18.87#ibcon#about to read 3, iclass 16, count 0 2006.197.07:38:18.91#ibcon#read 3, iclass 16, count 0 2006.197.07:38:18.91#ibcon#about to read 4, iclass 16, count 0 2006.197.07:38:18.91#ibcon#read 4, iclass 16, count 0 2006.197.07:38:18.91#ibcon#about to read 5, iclass 16, count 0 2006.197.07:38:18.91#ibcon#read 5, iclass 16, count 0 2006.197.07:38:18.91#ibcon#about to read 6, iclass 16, count 0 2006.197.07:38:18.91#ibcon#read 6, iclass 16, count 0 2006.197.07:38:18.91#ibcon#end of sib2, iclass 16, count 0 2006.197.07:38:18.91#ibcon#*after write, iclass 16, count 0 2006.197.07:38:18.91#ibcon#*before return 0, iclass 16, count 0 2006.197.07:38:18.91#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.197.07:38:18.91#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.197.07:38:18.91#ibcon#about to clear, iclass 16 cls_cnt 0 2006.197.07:38:18.91#ibcon#cleared, iclass 16 cls_cnt 0 2006.197.07:38:18.91$vc4f8/va=5,7 2006.197.07:38:18.91#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.197.07:38:18.91#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.197.07:38:18.91#ibcon#ireg 11 cls_cnt 2 2006.197.07:38:18.91#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.197.07:38:18.97#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.197.07:38:18.97#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.197.07:38:18.97#ibcon#enter wrdev, iclass 18, count 2 2006.197.07:38:18.97#ibcon#first serial, iclass 18, count 2 2006.197.07:38:18.97#ibcon#enter sib2, iclass 18, count 2 2006.197.07:38:18.97#ibcon#flushed, iclass 18, count 2 2006.197.07:38:18.97#ibcon#about to write, iclass 18, count 2 2006.197.07:38:18.97#ibcon#wrote, iclass 18, count 2 2006.197.07:38:18.97#ibcon#about to read 3, iclass 18, count 2 2006.197.07:38:18.99#ibcon#read 3, iclass 18, count 2 2006.197.07:38:18.99#ibcon#about to read 4, iclass 18, count 2 2006.197.07:38:18.99#ibcon#read 4, iclass 18, count 2 2006.197.07:38:18.99#ibcon#about to read 5, iclass 18, count 2 2006.197.07:38:18.99#ibcon#read 5, iclass 18, count 2 2006.197.07:38:18.99#ibcon#about to read 6, iclass 18, count 2 2006.197.07:38:18.99#ibcon#read 6, iclass 18, count 2 2006.197.07:38:18.99#ibcon#end of sib2, iclass 18, count 2 2006.197.07:38:18.99#ibcon#*mode == 0, iclass 18, count 2 2006.197.07:38:18.99#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.197.07:38:18.99#ibcon#[25=AT05-07\r\n] 2006.197.07:38:18.99#ibcon#*before write, iclass 18, count 2 2006.197.07:38:18.99#ibcon#enter sib2, iclass 18, count 2 2006.197.07:38:18.99#ibcon#flushed, iclass 18, count 2 2006.197.07:38:18.99#ibcon#about to write, iclass 18, count 2 2006.197.07:38:18.99#ibcon#wrote, iclass 18, count 2 2006.197.07:38:18.99#ibcon#about to read 3, iclass 18, count 2 2006.197.07:38:19.02#ibcon#read 3, iclass 18, count 2 2006.197.07:38:19.02#ibcon#about to read 4, iclass 18, count 2 2006.197.07:38:19.02#ibcon#read 4, iclass 18, count 2 2006.197.07:38:19.02#ibcon#about to read 5, iclass 18, count 2 2006.197.07:38:19.02#ibcon#read 5, iclass 18, count 2 2006.197.07:38:19.02#ibcon#about to read 6, iclass 18, count 2 2006.197.07:38:19.02#ibcon#read 6, iclass 18, count 2 2006.197.07:38:19.02#ibcon#end of sib2, iclass 18, count 2 2006.197.07:38:19.02#ibcon#*after write, iclass 18, count 2 2006.197.07:38:19.02#ibcon#*before return 0, iclass 18, count 2 2006.197.07:38:19.02#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.197.07:38:19.02#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.197.07:38:19.02#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.197.07:38:19.02#ibcon#ireg 7 cls_cnt 0 2006.197.07:38:19.02#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.197.07:38:19.14#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.197.07:38:19.14#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.197.07:38:19.14#ibcon#enter wrdev, iclass 18, count 0 2006.197.07:38:19.14#ibcon#first serial, iclass 18, count 0 2006.197.07:38:19.14#ibcon#enter sib2, iclass 18, count 0 2006.197.07:38:19.14#ibcon#flushed, iclass 18, count 0 2006.197.07:38:19.14#ibcon#about to write, iclass 18, count 0 2006.197.07:38:19.14#ibcon#wrote, iclass 18, count 0 2006.197.07:38:19.14#ibcon#about to read 3, iclass 18, count 0 2006.197.07:38:19.16#ibcon#read 3, iclass 18, count 0 2006.197.07:38:19.16#ibcon#about to read 4, iclass 18, count 0 2006.197.07:38:19.16#ibcon#read 4, iclass 18, count 0 2006.197.07:38:19.16#ibcon#about to read 5, iclass 18, count 0 2006.197.07:38:19.16#ibcon#read 5, iclass 18, count 0 2006.197.07:38:19.16#ibcon#about to read 6, iclass 18, count 0 2006.197.07:38:19.16#ibcon#read 6, iclass 18, count 0 2006.197.07:38:19.16#ibcon#end of sib2, iclass 18, count 0 2006.197.07:38:19.16#ibcon#*mode == 0, iclass 18, count 0 2006.197.07:38:19.16#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.197.07:38:19.16#ibcon#[25=USB\r\n] 2006.197.07:38:19.16#ibcon#*before write, iclass 18, count 0 2006.197.07:38:19.16#ibcon#enter sib2, iclass 18, count 0 2006.197.07:38:19.16#ibcon#flushed, iclass 18, count 0 2006.197.07:38:19.16#ibcon#about to write, iclass 18, count 0 2006.197.07:38:19.16#ibcon#wrote, iclass 18, count 0 2006.197.07:38:19.16#ibcon#about to read 3, iclass 18, count 0 2006.197.07:38:19.19#ibcon#read 3, iclass 18, count 0 2006.197.07:38:19.19#ibcon#about to read 4, iclass 18, count 0 2006.197.07:38:19.19#ibcon#read 4, iclass 18, count 0 2006.197.07:38:19.19#ibcon#about to read 5, iclass 18, count 0 2006.197.07:38:19.19#ibcon#read 5, iclass 18, count 0 2006.197.07:38:19.19#ibcon#about to read 6, iclass 18, count 0 2006.197.07:38:19.19#ibcon#read 6, iclass 18, count 0 2006.197.07:38:19.19#ibcon#end of sib2, iclass 18, count 0 2006.197.07:38:19.19#ibcon#*after write, iclass 18, count 0 2006.197.07:38:19.19#ibcon#*before return 0, iclass 18, count 0 2006.197.07:38:19.19#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.197.07:38:19.19#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.197.07:38:19.19#ibcon#about to clear, iclass 18 cls_cnt 0 2006.197.07:38:19.19#ibcon#cleared, iclass 18 cls_cnt 0 2006.197.07:38:19.19$vc4f8/valo=6,772.99 2006.197.07:38:19.19#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.197.07:38:19.19#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.197.07:38:19.19#ibcon#ireg 17 cls_cnt 0 2006.197.07:38:19.19#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.197.07:38:19.19#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.197.07:38:19.19#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.197.07:38:19.19#ibcon#enter wrdev, iclass 20, count 0 2006.197.07:38:19.19#ibcon#first serial, iclass 20, count 0 2006.197.07:38:19.19#ibcon#enter sib2, iclass 20, count 0 2006.197.07:38:19.19#ibcon#flushed, iclass 20, count 0 2006.197.07:38:19.19#ibcon#about to write, iclass 20, count 0 2006.197.07:38:19.19#ibcon#wrote, iclass 20, count 0 2006.197.07:38:19.19#ibcon#about to read 3, iclass 20, count 0 2006.197.07:38:19.21#ibcon#read 3, iclass 20, count 0 2006.197.07:38:19.21#ibcon#about to read 4, iclass 20, count 0 2006.197.07:38:19.21#ibcon#read 4, iclass 20, count 0 2006.197.07:38:19.21#ibcon#about to read 5, iclass 20, count 0 2006.197.07:38:19.21#ibcon#read 5, iclass 20, count 0 2006.197.07:38:19.21#ibcon#about to read 6, iclass 20, count 0 2006.197.07:38:19.21#ibcon#read 6, iclass 20, count 0 2006.197.07:38:19.21#ibcon#end of sib2, iclass 20, count 0 2006.197.07:38:19.21#ibcon#*mode == 0, iclass 20, count 0 2006.197.07:38:19.21#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.197.07:38:19.21#ibcon#[26=FRQ=06,772.99\r\n] 2006.197.07:38:19.21#ibcon#*before write, iclass 20, count 0 2006.197.07:38:19.21#ibcon#enter sib2, iclass 20, count 0 2006.197.07:38:19.21#ibcon#flushed, iclass 20, count 0 2006.197.07:38:19.21#ibcon#about to write, iclass 20, count 0 2006.197.07:38:19.21#ibcon#wrote, iclass 20, count 0 2006.197.07:38:19.21#ibcon#about to read 3, iclass 20, count 0 2006.197.07:38:19.25#ibcon#read 3, iclass 20, count 0 2006.197.07:38:19.25#ibcon#about to read 4, iclass 20, count 0 2006.197.07:38:19.25#ibcon#read 4, iclass 20, count 0 2006.197.07:38:19.25#ibcon#about to read 5, iclass 20, count 0 2006.197.07:38:19.25#ibcon#read 5, iclass 20, count 0 2006.197.07:38:19.25#ibcon#about to read 6, iclass 20, count 0 2006.197.07:38:19.25#ibcon#read 6, iclass 20, count 0 2006.197.07:38:19.25#ibcon#end of sib2, iclass 20, count 0 2006.197.07:38:19.25#ibcon#*after write, iclass 20, count 0 2006.197.07:38:19.25#ibcon#*before return 0, iclass 20, count 0 2006.197.07:38:19.25#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.197.07:38:19.25#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.197.07:38:19.25#ibcon#about to clear, iclass 20 cls_cnt 0 2006.197.07:38:19.25#ibcon#cleared, iclass 20 cls_cnt 0 2006.197.07:38:19.25$vc4f8/va=6,6 2006.197.07:38:19.25#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.197.07:38:19.25#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.197.07:38:19.25#ibcon#ireg 11 cls_cnt 2 2006.197.07:38:19.25#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.197.07:38:19.31#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.197.07:38:19.31#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.197.07:38:19.31#ibcon#enter wrdev, iclass 22, count 2 2006.197.07:38:19.31#ibcon#first serial, iclass 22, count 2 2006.197.07:38:19.31#ibcon#enter sib2, iclass 22, count 2 2006.197.07:38:19.31#ibcon#flushed, iclass 22, count 2 2006.197.07:38:19.31#ibcon#about to write, iclass 22, count 2 2006.197.07:38:19.31#ibcon#wrote, iclass 22, count 2 2006.197.07:38:19.31#ibcon#about to read 3, iclass 22, count 2 2006.197.07:38:19.33#ibcon#read 3, iclass 22, count 2 2006.197.07:38:19.33#ibcon#about to read 4, iclass 22, count 2 2006.197.07:38:19.33#ibcon#read 4, iclass 22, count 2 2006.197.07:38:19.33#ibcon#about to read 5, iclass 22, count 2 2006.197.07:38:19.33#ibcon#read 5, iclass 22, count 2 2006.197.07:38:19.33#ibcon#about to read 6, iclass 22, count 2 2006.197.07:38:19.33#ibcon#read 6, iclass 22, count 2 2006.197.07:38:19.33#ibcon#end of sib2, iclass 22, count 2 2006.197.07:38:19.33#ibcon#*mode == 0, iclass 22, count 2 2006.197.07:38:19.33#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.197.07:38:19.33#ibcon#[25=AT06-06\r\n] 2006.197.07:38:19.33#ibcon#*before write, iclass 22, count 2 2006.197.07:38:19.33#ibcon#enter sib2, iclass 22, count 2 2006.197.07:38:19.33#ibcon#flushed, iclass 22, count 2 2006.197.07:38:19.33#ibcon#about to write, iclass 22, count 2 2006.197.07:38:19.33#ibcon#wrote, iclass 22, count 2 2006.197.07:38:19.33#ibcon#about to read 3, iclass 22, count 2 2006.197.07:38:19.36#ibcon#read 3, iclass 22, count 2 2006.197.07:38:19.36#ibcon#about to read 4, iclass 22, count 2 2006.197.07:38:19.36#ibcon#read 4, iclass 22, count 2 2006.197.07:38:19.36#ibcon#about to read 5, iclass 22, count 2 2006.197.07:38:19.36#ibcon#read 5, iclass 22, count 2 2006.197.07:38:19.36#ibcon#about to read 6, iclass 22, count 2 2006.197.07:38:19.36#ibcon#read 6, iclass 22, count 2 2006.197.07:38:19.36#ibcon#end of sib2, iclass 22, count 2 2006.197.07:38:19.36#ibcon#*after write, iclass 22, count 2 2006.197.07:38:19.36#ibcon#*before return 0, iclass 22, count 2 2006.197.07:38:19.36#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.197.07:38:19.36#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.197.07:38:19.36#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.197.07:38:19.36#ibcon#ireg 7 cls_cnt 0 2006.197.07:38:19.36#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.197.07:38:19.48#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.197.07:38:19.48#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.197.07:38:19.48#ibcon#enter wrdev, iclass 22, count 0 2006.197.07:38:19.48#ibcon#first serial, iclass 22, count 0 2006.197.07:38:19.48#ibcon#enter sib2, iclass 22, count 0 2006.197.07:38:19.48#ibcon#flushed, iclass 22, count 0 2006.197.07:38:19.48#ibcon#about to write, iclass 22, count 0 2006.197.07:38:19.48#ibcon#wrote, iclass 22, count 0 2006.197.07:38:19.48#ibcon#about to read 3, iclass 22, count 0 2006.197.07:38:19.50#ibcon#read 3, iclass 22, count 0 2006.197.07:38:19.50#ibcon#about to read 4, iclass 22, count 0 2006.197.07:38:19.50#ibcon#read 4, iclass 22, count 0 2006.197.07:38:19.50#ibcon#about to read 5, iclass 22, count 0 2006.197.07:38:19.50#ibcon#read 5, iclass 22, count 0 2006.197.07:38:19.50#ibcon#about to read 6, iclass 22, count 0 2006.197.07:38:19.50#ibcon#read 6, iclass 22, count 0 2006.197.07:38:19.50#ibcon#end of sib2, iclass 22, count 0 2006.197.07:38:19.50#ibcon#*mode == 0, iclass 22, count 0 2006.197.07:38:19.50#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.197.07:38:19.50#ibcon#[25=USB\r\n] 2006.197.07:38:19.50#ibcon#*before write, iclass 22, count 0 2006.197.07:38:19.50#ibcon#enter sib2, iclass 22, count 0 2006.197.07:38:19.50#ibcon#flushed, iclass 22, count 0 2006.197.07:38:19.50#ibcon#about to write, iclass 22, count 0 2006.197.07:38:19.50#ibcon#wrote, iclass 22, count 0 2006.197.07:38:19.50#ibcon#about to read 3, iclass 22, count 0 2006.197.07:38:19.53#ibcon#read 3, iclass 22, count 0 2006.197.07:38:19.53#ibcon#about to read 4, iclass 22, count 0 2006.197.07:38:19.53#ibcon#read 4, iclass 22, count 0 2006.197.07:38:19.53#ibcon#about to read 5, iclass 22, count 0 2006.197.07:38:19.53#ibcon#read 5, iclass 22, count 0 2006.197.07:38:19.53#ibcon#about to read 6, iclass 22, count 0 2006.197.07:38:19.53#ibcon#read 6, iclass 22, count 0 2006.197.07:38:19.53#ibcon#end of sib2, iclass 22, count 0 2006.197.07:38:19.53#ibcon#*after write, iclass 22, count 0 2006.197.07:38:19.53#ibcon#*before return 0, iclass 22, count 0 2006.197.07:38:19.53#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.197.07:38:19.53#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.197.07:38:19.53#ibcon#about to clear, iclass 22 cls_cnt 0 2006.197.07:38:19.53#ibcon#cleared, iclass 22 cls_cnt 0 2006.197.07:38:19.53$vc4f8/valo=7,832.99 2006.197.07:38:19.53#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.197.07:38:19.53#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.197.07:38:19.53#ibcon#ireg 17 cls_cnt 0 2006.197.07:38:19.53#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.197.07:38:19.53#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.197.07:38:19.53#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.197.07:38:19.53#ibcon#enter wrdev, iclass 24, count 0 2006.197.07:38:19.53#ibcon#first serial, iclass 24, count 0 2006.197.07:38:19.53#ibcon#enter sib2, iclass 24, count 0 2006.197.07:38:19.53#ibcon#flushed, iclass 24, count 0 2006.197.07:38:19.53#ibcon#about to write, iclass 24, count 0 2006.197.07:38:19.53#ibcon#wrote, iclass 24, count 0 2006.197.07:38:19.53#ibcon#about to read 3, iclass 24, count 0 2006.197.07:38:19.55#ibcon#read 3, iclass 24, count 0 2006.197.07:38:19.55#ibcon#about to read 4, iclass 24, count 0 2006.197.07:38:19.55#ibcon#read 4, iclass 24, count 0 2006.197.07:38:19.55#ibcon#about to read 5, iclass 24, count 0 2006.197.07:38:19.55#ibcon#read 5, iclass 24, count 0 2006.197.07:38:19.55#ibcon#about to read 6, iclass 24, count 0 2006.197.07:38:19.55#ibcon#read 6, iclass 24, count 0 2006.197.07:38:19.55#ibcon#end of sib2, iclass 24, count 0 2006.197.07:38:19.55#ibcon#*mode == 0, iclass 24, count 0 2006.197.07:38:19.55#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.197.07:38:19.55#ibcon#[26=FRQ=07,832.99\r\n] 2006.197.07:38:19.55#ibcon#*before write, iclass 24, count 0 2006.197.07:38:19.55#ibcon#enter sib2, iclass 24, count 0 2006.197.07:38:19.55#ibcon#flushed, iclass 24, count 0 2006.197.07:38:19.55#ibcon#about to write, iclass 24, count 0 2006.197.07:38:19.55#ibcon#wrote, iclass 24, count 0 2006.197.07:38:19.55#ibcon#about to read 3, iclass 24, count 0 2006.197.07:38:19.59#ibcon#read 3, iclass 24, count 0 2006.197.07:38:19.59#ibcon#about to read 4, iclass 24, count 0 2006.197.07:38:19.59#ibcon#read 4, iclass 24, count 0 2006.197.07:38:19.59#ibcon#about to read 5, iclass 24, count 0 2006.197.07:38:19.59#ibcon#read 5, iclass 24, count 0 2006.197.07:38:19.59#ibcon#about to read 6, iclass 24, count 0 2006.197.07:38:19.59#ibcon#read 6, iclass 24, count 0 2006.197.07:38:19.59#ibcon#end of sib2, iclass 24, count 0 2006.197.07:38:19.59#ibcon#*after write, iclass 24, count 0 2006.197.07:38:19.59#ibcon#*before return 0, iclass 24, count 0 2006.197.07:38:19.59#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.197.07:38:19.59#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.197.07:38:19.59#ibcon#about to clear, iclass 24 cls_cnt 0 2006.197.07:38:19.59#ibcon#cleared, iclass 24 cls_cnt 0 2006.197.07:38:19.59$vc4f8/va=7,6 2006.197.07:38:19.59#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.197.07:38:19.59#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.197.07:38:19.59#ibcon#ireg 11 cls_cnt 2 2006.197.07:38:19.59#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.197.07:38:19.65#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.197.07:38:19.65#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.197.07:38:19.65#ibcon#enter wrdev, iclass 26, count 2 2006.197.07:38:19.65#ibcon#first serial, iclass 26, count 2 2006.197.07:38:19.65#ibcon#enter sib2, iclass 26, count 2 2006.197.07:38:19.65#ibcon#flushed, iclass 26, count 2 2006.197.07:38:19.65#ibcon#about to write, iclass 26, count 2 2006.197.07:38:19.65#ibcon#wrote, iclass 26, count 2 2006.197.07:38:19.65#ibcon#about to read 3, iclass 26, count 2 2006.197.07:38:19.67#ibcon#read 3, iclass 26, count 2 2006.197.07:38:19.67#ibcon#about to read 4, iclass 26, count 2 2006.197.07:38:19.67#ibcon#read 4, iclass 26, count 2 2006.197.07:38:19.67#ibcon#about to read 5, iclass 26, count 2 2006.197.07:38:19.67#ibcon#read 5, iclass 26, count 2 2006.197.07:38:19.67#ibcon#about to read 6, iclass 26, count 2 2006.197.07:38:19.67#ibcon#read 6, iclass 26, count 2 2006.197.07:38:19.67#ibcon#end of sib2, iclass 26, count 2 2006.197.07:38:19.67#ibcon#*mode == 0, iclass 26, count 2 2006.197.07:38:19.67#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.197.07:38:19.67#ibcon#[25=AT07-06\r\n] 2006.197.07:38:19.67#ibcon#*before write, iclass 26, count 2 2006.197.07:38:19.67#ibcon#enter sib2, iclass 26, count 2 2006.197.07:38:19.67#ibcon#flushed, iclass 26, count 2 2006.197.07:38:19.67#ibcon#about to write, iclass 26, count 2 2006.197.07:38:19.67#ibcon#wrote, iclass 26, count 2 2006.197.07:38:19.67#ibcon#about to read 3, iclass 26, count 2 2006.197.07:38:19.70#ibcon#read 3, iclass 26, count 2 2006.197.07:38:19.70#ibcon#about to read 4, iclass 26, count 2 2006.197.07:38:19.70#ibcon#read 4, iclass 26, count 2 2006.197.07:38:19.70#ibcon#about to read 5, iclass 26, count 2 2006.197.07:38:19.70#ibcon#read 5, iclass 26, count 2 2006.197.07:38:19.70#ibcon#about to read 6, iclass 26, count 2 2006.197.07:38:19.70#ibcon#read 6, iclass 26, count 2 2006.197.07:38:19.70#ibcon#end of sib2, iclass 26, count 2 2006.197.07:38:19.70#ibcon#*after write, iclass 26, count 2 2006.197.07:38:19.70#ibcon#*before return 0, iclass 26, count 2 2006.197.07:38:19.70#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.197.07:38:19.70#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.197.07:38:19.70#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.197.07:38:19.70#ibcon#ireg 7 cls_cnt 0 2006.197.07:38:19.70#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.197.07:38:19.82#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.197.07:38:19.82#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.197.07:38:19.82#ibcon#enter wrdev, iclass 26, count 0 2006.197.07:38:19.82#ibcon#first serial, iclass 26, count 0 2006.197.07:38:19.82#ibcon#enter sib2, iclass 26, count 0 2006.197.07:38:19.82#ibcon#flushed, iclass 26, count 0 2006.197.07:38:19.82#ibcon#about to write, iclass 26, count 0 2006.197.07:38:19.82#ibcon#wrote, iclass 26, count 0 2006.197.07:38:19.82#ibcon#about to read 3, iclass 26, count 0 2006.197.07:38:19.84#ibcon#read 3, iclass 26, count 0 2006.197.07:38:19.84#ibcon#about to read 4, iclass 26, count 0 2006.197.07:38:19.84#ibcon#read 4, iclass 26, count 0 2006.197.07:38:19.84#ibcon#about to read 5, iclass 26, count 0 2006.197.07:38:19.84#ibcon#read 5, iclass 26, count 0 2006.197.07:38:19.84#ibcon#about to read 6, iclass 26, count 0 2006.197.07:38:19.84#ibcon#read 6, iclass 26, count 0 2006.197.07:38:19.84#ibcon#end of sib2, iclass 26, count 0 2006.197.07:38:19.84#ibcon#*mode == 0, iclass 26, count 0 2006.197.07:38:19.84#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.197.07:38:19.84#ibcon#[25=USB\r\n] 2006.197.07:38:19.84#ibcon#*before write, iclass 26, count 0 2006.197.07:38:19.84#ibcon#enter sib2, iclass 26, count 0 2006.197.07:38:19.84#ibcon#flushed, iclass 26, count 0 2006.197.07:38:19.84#ibcon#about to write, iclass 26, count 0 2006.197.07:38:19.84#ibcon#wrote, iclass 26, count 0 2006.197.07:38:19.84#ibcon#about to read 3, iclass 26, count 0 2006.197.07:38:19.87#ibcon#read 3, iclass 26, count 0 2006.197.07:38:19.87#ibcon#about to read 4, iclass 26, count 0 2006.197.07:38:19.87#ibcon#read 4, iclass 26, count 0 2006.197.07:38:19.87#ibcon#about to read 5, iclass 26, count 0 2006.197.07:38:19.87#ibcon#read 5, iclass 26, count 0 2006.197.07:38:19.87#ibcon#about to read 6, iclass 26, count 0 2006.197.07:38:19.87#ibcon#read 6, iclass 26, count 0 2006.197.07:38:19.87#ibcon#end of sib2, iclass 26, count 0 2006.197.07:38:19.87#ibcon#*after write, iclass 26, count 0 2006.197.07:38:19.87#ibcon#*before return 0, iclass 26, count 0 2006.197.07:38:19.87#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.197.07:38:19.87#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.197.07:38:19.87#ibcon#about to clear, iclass 26 cls_cnt 0 2006.197.07:38:19.87#ibcon#cleared, iclass 26 cls_cnt 0 2006.197.07:38:19.87$vc4f8/valo=8,852.99 2006.197.07:38:19.87#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.197.07:38:19.87#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.197.07:38:19.87#ibcon#ireg 17 cls_cnt 0 2006.197.07:38:19.87#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.197.07:38:19.87#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.197.07:38:19.87#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.197.07:38:19.87#ibcon#enter wrdev, iclass 28, count 0 2006.197.07:38:19.87#ibcon#first serial, iclass 28, count 0 2006.197.07:38:19.87#ibcon#enter sib2, iclass 28, count 0 2006.197.07:38:19.87#ibcon#flushed, iclass 28, count 0 2006.197.07:38:19.87#ibcon#about to write, iclass 28, count 0 2006.197.07:38:19.87#ibcon#wrote, iclass 28, count 0 2006.197.07:38:19.87#ibcon#about to read 3, iclass 28, count 0 2006.197.07:38:19.89#ibcon#read 3, iclass 28, count 0 2006.197.07:38:19.89#ibcon#about to read 4, iclass 28, count 0 2006.197.07:38:19.89#ibcon#read 4, iclass 28, count 0 2006.197.07:38:19.89#ibcon#about to read 5, iclass 28, count 0 2006.197.07:38:19.89#ibcon#read 5, iclass 28, count 0 2006.197.07:38:19.89#ibcon#about to read 6, iclass 28, count 0 2006.197.07:38:19.89#ibcon#read 6, iclass 28, count 0 2006.197.07:38:19.89#ibcon#end of sib2, iclass 28, count 0 2006.197.07:38:19.89#ibcon#*mode == 0, iclass 28, count 0 2006.197.07:38:19.89#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.197.07:38:19.89#ibcon#[26=FRQ=08,852.99\r\n] 2006.197.07:38:19.89#ibcon#*before write, iclass 28, count 0 2006.197.07:38:19.89#ibcon#enter sib2, iclass 28, count 0 2006.197.07:38:19.89#ibcon#flushed, iclass 28, count 0 2006.197.07:38:19.89#ibcon#about to write, iclass 28, count 0 2006.197.07:38:19.89#ibcon#wrote, iclass 28, count 0 2006.197.07:38:19.89#ibcon#about to read 3, iclass 28, count 0 2006.197.07:38:19.93#ibcon#read 3, iclass 28, count 0 2006.197.07:38:19.93#ibcon#about to read 4, iclass 28, count 0 2006.197.07:38:19.93#ibcon#read 4, iclass 28, count 0 2006.197.07:38:19.93#ibcon#about to read 5, iclass 28, count 0 2006.197.07:38:19.93#ibcon#read 5, iclass 28, count 0 2006.197.07:38:19.93#ibcon#about to read 6, iclass 28, count 0 2006.197.07:38:19.93#ibcon#read 6, iclass 28, count 0 2006.197.07:38:19.93#ibcon#end of sib2, iclass 28, count 0 2006.197.07:38:19.93#ibcon#*after write, iclass 28, count 0 2006.197.07:38:19.93#ibcon#*before return 0, iclass 28, count 0 2006.197.07:38:19.93#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.197.07:38:19.93#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.197.07:38:19.93#ibcon#about to clear, iclass 28 cls_cnt 0 2006.197.07:38:19.93#ibcon#cleared, iclass 28 cls_cnt 0 2006.197.07:38:19.93$vc4f8/va=8,7 2006.197.07:38:19.93#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.197.07:38:19.93#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.197.07:38:19.93#ibcon#ireg 11 cls_cnt 2 2006.197.07:38:19.93#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.197.07:38:19.99#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.197.07:38:19.99#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.197.07:38:19.99#ibcon#enter wrdev, iclass 30, count 2 2006.197.07:38:19.99#ibcon#first serial, iclass 30, count 2 2006.197.07:38:19.99#ibcon#enter sib2, iclass 30, count 2 2006.197.07:38:19.99#ibcon#flushed, iclass 30, count 2 2006.197.07:38:19.99#ibcon#about to write, iclass 30, count 2 2006.197.07:38:19.99#ibcon#wrote, iclass 30, count 2 2006.197.07:38:19.99#ibcon#about to read 3, iclass 30, count 2 2006.197.07:38:20.01#ibcon#read 3, iclass 30, count 2 2006.197.07:38:20.01#ibcon#about to read 4, iclass 30, count 2 2006.197.07:38:20.01#ibcon#read 4, iclass 30, count 2 2006.197.07:38:20.01#ibcon#about to read 5, iclass 30, count 2 2006.197.07:38:20.01#ibcon#read 5, iclass 30, count 2 2006.197.07:38:20.01#ibcon#about to read 6, iclass 30, count 2 2006.197.07:38:20.01#ibcon#read 6, iclass 30, count 2 2006.197.07:38:20.01#ibcon#end of sib2, iclass 30, count 2 2006.197.07:38:20.01#ibcon#*mode == 0, iclass 30, count 2 2006.197.07:38:20.01#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.197.07:38:20.01#ibcon#[25=AT08-07\r\n] 2006.197.07:38:20.01#ibcon#*before write, iclass 30, count 2 2006.197.07:38:20.01#ibcon#enter sib2, iclass 30, count 2 2006.197.07:38:20.01#ibcon#flushed, iclass 30, count 2 2006.197.07:38:20.01#ibcon#about to write, iclass 30, count 2 2006.197.07:38:20.01#ibcon#wrote, iclass 30, count 2 2006.197.07:38:20.01#ibcon#about to read 3, iclass 30, count 2 2006.197.07:38:20.04#ibcon#read 3, iclass 30, count 2 2006.197.07:38:20.04#ibcon#about to read 4, iclass 30, count 2 2006.197.07:38:20.04#ibcon#read 4, iclass 30, count 2 2006.197.07:38:20.04#ibcon#about to read 5, iclass 30, count 2 2006.197.07:38:20.04#ibcon#read 5, iclass 30, count 2 2006.197.07:38:20.04#ibcon#about to read 6, iclass 30, count 2 2006.197.07:38:20.04#ibcon#read 6, iclass 30, count 2 2006.197.07:38:20.04#ibcon#end of sib2, iclass 30, count 2 2006.197.07:38:20.04#ibcon#*after write, iclass 30, count 2 2006.197.07:38:20.04#ibcon#*before return 0, iclass 30, count 2 2006.197.07:38:20.04#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.197.07:38:20.04#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.197.07:38:20.04#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.197.07:38:20.04#ibcon#ireg 7 cls_cnt 0 2006.197.07:38:20.04#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.197.07:38:20.16#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.197.07:38:20.16#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.197.07:38:20.16#ibcon#enter wrdev, iclass 30, count 0 2006.197.07:38:20.16#ibcon#first serial, iclass 30, count 0 2006.197.07:38:20.16#ibcon#enter sib2, iclass 30, count 0 2006.197.07:38:20.16#ibcon#flushed, iclass 30, count 0 2006.197.07:38:20.16#ibcon#about to write, iclass 30, count 0 2006.197.07:38:20.16#ibcon#wrote, iclass 30, count 0 2006.197.07:38:20.16#ibcon#about to read 3, iclass 30, count 0 2006.197.07:38:20.18#ibcon#read 3, iclass 30, count 0 2006.197.07:38:20.18#ibcon#about to read 4, iclass 30, count 0 2006.197.07:38:20.18#ibcon#read 4, iclass 30, count 0 2006.197.07:38:20.18#ibcon#about to read 5, iclass 30, count 0 2006.197.07:38:20.18#ibcon#read 5, iclass 30, count 0 2006.197.07:38:20.18#ibcon#about to read 6, iclass 30, count 0 2006.197.07:38:20.18#ibcon#read 6, iclass 30, count 0 2006.197.07:38:20.18#ibcon#end of sib2, iclass 30, count 0 2006.197.07:38:20.18#ibcon#*mode == 0, iclass 30, count 0 2006.197.07:38:20.18#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.197.07:38:20.18#ibcon#[25=USB\r\n] 2006.197.07:38:20.18#ibcon#*before write, iclass 30, count 0 2006.197.07:38:20.18#ibcon#enter sib2, iclass 30, count 0 2006.197.07:38:20.18#ibcon#flushed, iclass 30, count 0 2006.197.07:38:20.18#ibcon#about to write, iclass 30, count 0 2006.197.07:38:20.18#ibcon#wrote, iclass 30, count 0 2006.197.07:38:20.18#ibcon#about to read 3, iclass 30, count 0 2006.197.07:38:20.21#ibcon#read 3, iclass 30, count 0 2006.197.07:38:20.21#ibcon#about to read 4, iclass 30, count 0 2006.197.07:38:20.21#ibcon#read 4, iclass 30, count 0 2006.197.07:38:20.21#ibcon#about to read 5, iclass 30, count 0 2006.197.07:38:20.21#ibcon#read 5, iclass 30, count 0 2006.197.07:38:20.21#ibcon#about to read 6, iclass 30, count 0 2006.197.07:38:20.21#ibcon#read 6, iclass 30, count 0 2006.197.07:38:20.21#ibcon#end of sib2, iclass 30, count 0 2006.197.07:38:20.21#ibcon#*after write, iclass 30, count 0 2006.197.07:38:20.21#ibcon#*before return 0, iclass 30, count 0 2006.197.07:38:20.21#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.197.07:38:20.21#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.197.07:38:20.21#ibcon#about to clear, iclass 30 cls_cnt 0 2006.197.07:38:20.21#ibcon#cleared, iclass 30 cls_cnt 0 2006.197.07:38:20.21$vc4f8/vblo=1,632.99 2006.197.07:38:20.21#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.197.07:38:20.21#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.197.07:38:20.21#ibcon#ireg 17 cls_cnt 0 2006.197.07:38:20.21#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.197.07:38:20.21#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.197.07:38:20.21#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.197.07:38:20.21#ibcon#enter wrdev, iclass 32, count 0 2006.197.07:38:20.21#ibcon#first serial, iclass 32, count 0 2006.197.07:38:20.21#ibcon#enter sib2, iclass 32, count 0 2006.197.07:38:20.21#ibcon#flushed, iclass 32, count 0 2006.197.07:38:20.21#ibcon#about to write, iclass 32, count 0 2006.197.07:38:20.21#ibcon#wrote, iclass 32, count 0 2006.197.07:38:20.21#ibcon#about to read 3, iclass 32, count 0 2006.197.07:38:20.23#ibcon#read 3, iclass 32, count 0 2006.197.07:38:20.23#ibcon#about to read 4, iclass 32, count 0 2006.197.07:38:20.23#ibcon#read 4, iclass 32, count 0 2006.197.07:38:20.23#ibcon#about to read 5, iclass 32, count 0 2006.197.07:38:20.23#ibcon#read 5, iclass 32, count 0 2006.197.07:38:20.23#ibcon#about to read 6, iclass 32, count 0 2006.197.07:38:20.23#ibcon#read 6, iclass 32, count 0 2006.197.07:38:20.23#ibcon#end of sib2, iclass 32, count 0 2006.197.07:38:20.23#ibcon#*mode == 0, iclass 32, count 0 2006.197.07:38:20.23#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.197.07:38:20.23#ibcon#[28=FRQ=01,632.99\r\n] 2006.197.07:38:20.23#ibcon#*before write, iclass 32, count 0 2006.197.07:38:20.23#ibcon#enter sib2, iclass 32, count 0 2006.197.07:38:20.23#ibcon#flushed, iclass 32, count 0 2006.197.07:38:20.23#ibcon#about to write, iclass 32, count 0 2006.197.07:38:20.23#ibcon#wrote, iclass 32, count 0 2006.197.07:38:20.23#ibcon#about to read 3, iclass 32, count 0 2006.197.07:38:20.27#ibcon#read 3, iclass 32, count 0 2006.197.07:38:20.27#ibcon#about to read 4, iclass 32, count 0 2006.197.07:38:20.27#ibcon#read 4, iclass 32, count 0 2006.197.07:38:20.27#ibcon#about to read 5, iclass 32, count 0 2006.197.07:38:20.27#ibcon#read 5, iclass 32, count 0 2006.197.07:38:20.27#ibcon#about to read 6, iclass 32, count 0 2006.197.07:38:20.27#ibcon#read 6, iclass 32, count 0 2006.197.07:38:20.27#ibcon#end of sib2, iclass 32, count 0 2006.197.07:38:20.27#ibcon#*after write, iclass 32, count 0 2006.197.07:38:20.27#ibcon#*before return 0, iclass 32, count 0 2006.197.07:38:20.27#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.197.07:38:20.27#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.197.07:38:20.27#ibcon#about to clear, iclass 32 cls_cnt 0 2006.197.07:38:20.27#ibcon#cleared, iclass 32 cls_cnt 0 2006.197.07:38:20.27$vc4f8/vb=1,4 2006.197.07:38:20.27#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.197.07:38:20.27#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.197.07:38:20.27#ibcon#ireg 11 cls_cnt 2 2006.197.07:38:20.27#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.197.07:38:20.27#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.197.07:38:20.27#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.197.07:38:20.27#ibcon#enter wrdev, iclass 34, count 2 2006.197.07:38:20.27#ibcon#first serial, iclass 34, count 2 2006.197.07:38:20.27#ibcon#enter sib2, iclass 34, count 2 2006.197.07:38:20.27#ibcon#flushed, iclass 34, count 2 2006.197.07:38:20.27#ibcon#about to write, iclass 34, count 2 2006.197.07:38:20.27#ibcon#wrote, iclass 34, count 2 2006.197.07:38:20.27#ibcon#about to read 3, iclass 34, count 2 2006.197.07:38:20.29#ibcon#read 3, iclass 34, count 2 2006.197.07:38:20.29#ibcon#about to read 4, iclass 34, count 2 2006.197.07:38:20.29#ibcon#read 4, iclass 34, count 2 2006.197.07:38:20.29#ibcon#about to read 5, iclass 34, count 2 2006.197.07:38:20.29#ibcon#read 5, iclass 34, count 2 2006.197.07:38:20.29#ibcon#about to read 6, iclass 34, count 2 2006.197.07:38:20.29#ibcon#read 6, iclass 34, count 2 2006.197.07:38:20.29#ibcon#end of sib2, iclass 34, count 2 2006.197.07:38:20.29#ibcon#*mode == 0, iclass 34, count 2 2006.197.07:38:20.29#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.197.07:38:20.29#ibcon#[27=AT01-04\r\n] 2006.197.07:38:20.29#ibcon#*before write, iclass 34, count 2 2006.197.07:38:20.29#ibcon#enter sib2, iclass 34, count 2 2006.197.07:38:20.29#ibcon#flushed, iclass 34, count 2 2006.197.07:38:20.29#ibcon#about to write, iclass 34, count 2 2006.197.07:38:20.29#ibcon#wrote, iclass 34, count 2 2006.197.07:38:20.29#ibcon#about to read 3, iclass 34, count 2 2006.197.07:38:20.32#ibcon#read 3, iclass 34, count 2 2006.197.07:38:20.32#ibcon#about to read 4, iclass 34, count 2 2006.197.07:38:20.32#ibcon#read 4, iclass 34, count 2 2006.197.07:38:20.32#ibcon#about to read 5, iclass 34, count 2 2006.197.07:38:20.32#ibcon#read 5, iclass 34, count 2 2006.197.07:38:20.32#ibcon#about to read 6, iclass 34, count 2 2006.197.07:38:20.32#ibcon#read 6, iclass 34, count 2 2006.197.07:38:20.32#ibcon#end of sib2, iclass 34, count 2 2006.197.07:38:20.32#ibcon#*after write, iclass 34, count 2 2006.197.07:38:20.32#ibcon#*before return 0, iclass 34, count 2 2006.197.07:38:20.32#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.197.07:38:20.32#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.197.07:38:20.32#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.197.07:38:20.32#ibcon#ireg 7 cls_cnt 0 2006.197.07:38:20.32#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.197.07:38:20.44#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.197.07:38:20.44#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.197.07:38:20.44#ibcon#enter wrdev, iclass 34, count 0 2006.197.07:38:20.44#ibcon#first serial, iclass 34, count 0 2006.197.07:38:20.44#ibcon#enter sib2, iclass 34, count 0 2006.197.07:38:20.44#ibcon#flushed, iclass 34, count 0 2006.197.07:38:20.44#ibcon#about to write, iclass 34, count 0 2006.197.07:38:20.44#ibcon#wrote, iclass 34, count 0 2006.197.07:38:20.44#ibcon#about to read 3, iclass 34, count 0 2006.197.07:38:20.46#ibcon#read 3, iclass 34, count 0 2006.197.07:38:20.46#ibcon#about to read 4, iclass 34, count 0 2006.197.07:38:20.46#ibcon#read 4, iclass 34, count 0 2006.197.07:38:20.46#ibcon#about to read 5, iclass 34, count 0 2006.197.07:38:20.46#ibcon#read 5, iclass 34, count 0 2006.197.07:38:20.46#ibcon#about to read 6, iclass 34, count 0 2006.197.07:38:20.46#ibcon#read 6, iclass 34, count 0 2006.197.07:38:20.46#ibcon#end of sib2, iclass 34, count 0 2006.197.07:38:20.46#ibcon#*mode == 0, iclass 34, count 0 2006.197.07:38:20.46#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.197.07:38:20.46#ibcon#[27=USB\r\n] 2006.197.07:38:20.46#ibcon#*before write, iclass 34, count 0 2006.197.07:38:20.46#ibcon#enter sib2, iclass 34, count 0 2006.197.07:38:20.46#ibcon#flushed, iclass 34, count 0 2006.197.07:38:20.46#ibcon#about to write, iclass 34, count 0 2006.197.07:38:20.46#ibcon#wrote, iclass 34, count 0 2006.197.07:38:20.46#ibcon#about to read 3, iclass 34, count 0 2006.197.07:38:20.49#ibcon#read 3, iclass 34, count 0 2006.197.07:38:20.49#ibcon#about to read 4, iclass 34, count 0 2006.197.07:38:20.49#ibcon#read 4, iclass 34, count 0 2006.197.07:38:20.49#ibcon#about to read 5, iclass 34, count 0 2006.197.07:38:20.49#ibcon#read 5, iclass 34, count 0 2006.197.07:38:20.49#ibcon#about to read 6, iclass 34, count 0 2006.197.07:38:20.49#ibcon#read 6, iclass 34, count 0 2006.197.07:38:20.49#ibcon#end of sib2, iclass 34, count 0 2006.197.07:38:20.49#ibcon#*after write, iclass 34, count 0 2006.197.07:38:20.49#ibcon#*before return 0, iclass 34, count 0 2006.197.07:38:20.49#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.197.07:38:20.49#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.197.07:38:20.49#ibcon#about to clear, iclass 34 cls_cnt 0 2006.197.07:38:20.49#ibcon#cleared, iclass 34 cls_cnt 0 2006.197.07:38:20.49$vc4f8/vblo=2,640.99 2006.197.07:38:20.49#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.197.07:38:20.49#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.197.07:38:20.49#ibcon#ireg 17 cls_cnt 0 2006.197.07:38:20.49#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.197.07:38:20.49#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.197.07:38:20.49#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.197.07:38:20.49#ibcon#enter wrdev, iclass 36, count 0 2006.197.07:38:20.49#ibcon#first serial, iclass 36, count 0 2006.197.07:38:20.49#ibcon#enter sib2, iclass 36, count 0 2006.197.07:38:20.49#ibcon#flushed, iclass 36, count 0 2006.197.07:38:20.49#ibcon#about to write, iclass 36, count 0 2006.197.07:38:20.49#ibcon#wrote, iclass 36, count 0 2006.197.07:38:20.49#ibcon#about to read 3, iclass 36, count 0 2006.197.07:38:20.51#ibcon#read 3, iclass 36, count 0 2006.197.07:38:20.51#ibcon#about to read 4, iclass 36, count 0 2006.197.07:38:20.51#ibcon#read 4, iclass 36, count 0 2006.197.07:38:20.51#ibcon#about to read 5, iclass 36, count 0 2006.197.07:38:20.51#ibcon#read 5, iclass 36, count 0 2006.197.07:38:20.51#ibcon#about to read 6, iclass 36, count 0 2006.197.07:38:20.51#ibcon#read 6, iclass 36, count 0 2006.197.07:38:20.51#ibcon#end of sib2, iclass 36, count 0 2006.197.07:38:20.51#ibcon#*mode == 0, iclass 36, count 0 2006.197.07:38:20.51#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.197.07:38:20.51#ibcon#[28=FRQ=02,640.99\r\n] 2006.197.07:38:20.51#ibcon#*before write, iclass 36, count 0 2006.197.07:38:20.51#ibcon#enter sib2, iclass 36, count 0 2006.197.07:38:20.51#ibcon#flushed, iclass 36, count 0 2006.197.07:38:20.51#ibcon#about to write, iclass 36, count 0 2006.197.07:38:20.51#ibcon#wrote, iclass 36, count 0 2006.197.07:38:20.51#ibcon#about to read 3, iclass 36, count 0 2006.197.07:38:20.55#ibcon#read 3, iclass 36, count 0 2006.197.07:38:20.55#ibcon#about to read 4, iclass 36, count 0 2006.197.07:38:20.55#ibcon#read 4, iclass 36, count 0 2006.197.07:38:20.55#ibcon#about to read 5, iclass 36, count 0 2006.197.07:38:20.55#ibcon#read 5, iclass 36, count 0 2006.197.07:38:20.55#ibcon#about to read 6, iclass 36, count 0 2006.197.07:38:20.55#ibcon#read 6, iclass 36, count 0 2006.197.07:38:20.55#ibcon#end of sib2, iclass 36, count 0 2006.197.07:38:20.55#ibcon#*after write, iclass 36, count 0 2006.197.07:38:20.55#ibcon#*before return 0, iclass 36, count 0 2006.197.07:38:20.55#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.197.07:38:20.55#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.197.07:38:20.55#ibcon#about to clear, iclass 36 cls_cnt 0 2006.197.07:38:20.55#ibcon#cleared, iclass 36 cls_cnt 0 2006.197.07:38:20.55$vc4f8/vb=2,4 2006.197.07:38:20.55#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.197.07:38:20.55#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.197.07:38:20.55#ibcon#ireg 11 cls_cnt 2 2006.197.07:38:20.55#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.197.07:38:20.61#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.197.07:38:20.61#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.197.07:38:20.61#ibcon#enter wrdev, iclass 38, count 2 2006.197.07:38:20.61#ibcon#first serial, iclass 38, count 2 2006.197.07:38:20.61#ibcon#enter sib2, iclass 38, count 2 2006.197.07:38:20.61#ibcon#flushed, iclass 38, count 2 2006.197.07:38:20.61#ibcon#about to write, iclass 38, count 2 2006.197.07:38:20.61#ibcon#wrote, iclass 38, count 2 2006.197.07:38:20.61#ibcon#about to read 3, iclass 38, count 2 2006.197.07:38:20.63#ibcon#read 3, iclass 38, count 2 2006.197.07:38:20.63#ibcon#about to read 4, iclass 38, count 2 2006.197.07:38:20.63#ibcon#read 4, iclass 38, count 2 2006.197.07:38:20.63#ibcon#about to read 5, iclass 38, count 2 2006.197.07:38:20.63#ibcon#read 5, iclass 38, count 2 2006.197.07:38:20.63#ibcon#about to read 6, iclass 38, count 2 2006.197.07:38:20.63#ibcon#read 6, iclass 38, count 2 2006.197.07:38:20.63#ibcon#end of sib2, iclass 38, count 2 2006.197.07:38:20.63#ibcon#*mode == 0, iclass 38, count 2 2006.197.07:38:20.63#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.197.07:38:20.63#ibcon#[27=AT02-04\r\n] 2006.197.07:38:20.63#ibcon#*before write, iclass 38, count 2 2006.197.07:38:20.63#ibcon#enter sib2, iclass 38, count 2 2006.197.07:38:20.63#ibcon#flushed, iclass 38, count 2 2006.197.07:38:20.63#ibcon#about to write, iclass 38, count 2 2006.197.07:38:20.63#ibcon#wrote, iclass 38, count 2 2006.197.07:38:20.63#ibcon#about to read 3, iclass 38, count 2 2006.197.07:38:20.66#ibcon#read 3, iclass 38, count 2 2006.197.07:38:20.66#ibcon#about to read 4, iclass 38, count 2 2006.197.07:38:20.66#ibcon#read 4, iclass 38, count 2 2006.197.07:38:20.66#ibcon#about to read 5, iclass 38, count 2 2006.197.07:38:20.66#ibcon#read 5, iclass 38, count 2 2006.197.07:38:20.66#ibcon#about to read 6, iclass 38, count 2 2006.197.07:38:20.66#ibcon#read 6, iclass 38, count 2 2006.197.07:38:20.66#ibcon#end of sib2, iclass 38, count 2 2006.197.07:38:20.66#ibcon#*after write, iclass 38, count 2 2006.197.07:38:20.66#ibcon#*before return 0, iclass 38, count 2 2006.197.07:38:20.66#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.197.07:38:20.66#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.197.07:38:20.66#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.197.07:38:20.66#ibcon#ireg 7 cls_cnt 0 2006.197.07:38:20.66#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.197.07:38:20.78#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.197.07:38:20.78#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.197.07:38:20.78#ibcon#enter wrdev, iclass 38, count 0 2006.197.07:38:20.78#ibcon#first serial, iclass 38, count 0 2006.197.07:38:20.78#ibcon#enter sib2, iclass 38, count 0 2006.197.07:38:20.78#ibcon#flushed, iclass 38, count 0 2006.197.07:38:20.78#ibcon#about to write, iclass 38, count 0 2006.197.07:38:20.78#ibcon#wrote, iclass 38, count 0 2006.197.07:38:20.78#ibcon#about to read 3, iclass 38, count 0 2006.197.07:38:20.80#ibcon#read 3, iclass 38, count 0 2006.197.07:38:20.80#ibcon#about to read 4, iclass 38, count 0 2006.197.07:38:20.80#ibcon#read 4, iclass 38, count 0 2006.197.07:38:20.80#ibcon#about to read 5, iclass 38, count 0 2006.197.07:38:20.80#ibcon#read 5, iclass 38, count 0 2006.197.07:38:20.80#ibcon#about to read 6, iclass 38, count 0 2006.197.07:38:20.80#ibcon#read 6, iclass 38, count 0 2006.197.07:38:20.80#ibcon#end of sib2, iclass 38, count 0 2006.197.07:38:20.80#ibcon#*mode == 0, iclass 38, count 0 2006.197.07:38:20.80#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.197.07:38:20.80#ibcon#[27=USB\r\n] 2006.197.07:38:20.80#ibcon#*before write, iclass 38, count 0 2006.197.07:38:20.80#ibcon#enter sib2, iclass 38, count 0 2006.197.07:38:20.80#ibcon#flushed, iclass 38, count 0 2006.197.07:38:20.80#ibcon#about to write, iclass 38, count 0 2006.197.07:38:20.80#ibcon#wrote, iclass 38, count 0 2006.197.07:38:20.80#ibcon#about to read 3, iclass 38, count 0 2006.197.07:38:20.83#ibcon#read 3, iclass 38, count 0 2006.197.07:38:20.83#ibcon#about to read 4, iclass 38, count 0 2006.197.07:38:20.83#ibcon#read 4, iclass 38, count 0 2006.197.07:38:20.83#ibcon#about to read 5, iclass 38, count 0 2006.197.07:38:20.83#ibcon#read 5, iclass 38, count 0 2006.197.07:38:20.83#ibcon#about to read 6, iclass 38, count 0 2006.197.07:38:20.83#ibcon#read 6, iclass 38, count 0 2006.197.07:38:20.83#ibcon#end of sib2, iclass 38, count 0 2006.197.07:38:20.83#ibcon#*after write, iclass 38, count 0 2006.197.07:38:20.83#ibcon#*before return 0, iclass 38, count 0 2006.197.07:38:20.83#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.197.07:38:20.83#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.197.07:38:20.83#ibcon#about to clear, iclass 38 cls_cnt 0 2006.197.07:38:20.83#ibcon#cleared, iclass 38 cls_cnt 0 2006.197.07:38:20.83$vc4f8/vblo=3,656.99 2006.197.07:38:20.83#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.197.07:38:20.83#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.197.07:38:20.83#ibcon#ireg 17 cls_cnt 0 2006.197.07:38:20.83#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.197.07:38:20.83#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.197.07:38:20.83#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.197.07:38:20.83#ibcon#enter wrdev, iclass 40, count 0 2006.197.07:38:20.83#ibcon#first serial, iclass 40, count 0 2006.197.07:38:20.83#ibcon#enter sib2, iclass 40, count 0 2006.197.07:38:20.83#ibcon#flushed, iclass 40, count 0 2006.197.07:38:20.83#ibcon#about to write, iclass 40, count 0 2006.197.07:38:20.83#ibcon#wrote, iclass 40, count 0 2006.197.07:38:20.83#ibcon#about to read 3, iclass 40, count 0 2006.197.07:38:20.85#ibcon#read 3, iclass 40, count 0 2006.197.07:38:20.85#ibcon#about to read 4, iclass 40, count 0 2006.197.07:38:20.85#ibcon#read 4, iclass 40, count 0 2006.197.07:38:20.85#ibcon#about to read 5, iclass 40, count 0 2006.197.07:38:20.85#ibcon#read 5, iclass 40, count 0 2006.197.07:38:20.85#ibcon#about to read 6, iclass 40, count 0 2006.197.07:38:20.85#ibcon#read 6, iclass 40, count 0 2006.197.07:38:20.85#ibcon#end of sib2, iclass 40, count 0 2006.197.07:38:20.85#ibcon#*mode == 0, iclass 40, count 0 2006.197.07:38:20.85#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.197.07:38:20.85#ibcon#[28=FRQ=03,656.99\r\n] 2006.197.07:38:20.85#ibcon#*before write, iclass 40, count 0 2006.197.07:38:20.85#ibcon#enter sib2, iclass 40, count 0 2006.197.07:38:20.85#ibcon#flushed, iclass 40, count 0 2006.197.07:38:20.85#ibcon#about to write, iclass 40, count 0 2006.197.07:38:20.85#ibcon#wrote, iclass 40, count 0 2006.197.07:38:20.85#ibcon#about to read 3, iclass 40, count 0 2006.197.07:38:20.89#ibcon#read 3, iclass 40, count 0 2006.197.07:38:20.89#ibcon#about to read 4, iclass 40, count 0 2006.197.07:38:20.89#ibcon#read 4, iclass 40, count 0 2006.197.07:38:20.89#ibcon#about to read 5, iclass 40, count 0 2006.197.07:38:20.89#ibcon#read 5, iclass 40, count 0 2006.197.07:38:20.89#ibcon#about to read 6, iclass 40, count 0 2006.197.07:38:20.89#ibcon#read 6, iclass 40, count 0 2006.197.07:38:20.89#ibcon#end of sib2, iclass 40, count 0 2006.197.07:38:20.89#ibcon#*after write, iclass 40, count 0 2006.197.07:38:20.89#ibcon#*before return 0, iclass 40, count 0 2006.197.07:38:20.89#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.197.07:38:20.89#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.197.07:38:20.89#ibcon#about to clear, iclass 40 cls_cnt 0 2006.197.07:38:20.89#ibcon#cleared, iclass 40 cls_cnt 0 2006.197.07:38:20.89$vc4f8/vb=3,4 2006.197.07:38:20.89#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.197.07:38:20.89#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.197.07:38:20.89#ibcon#ireg 11 cls_cnt 2 2006.197.07:38:20.89#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.197.07:38:20.95#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.197.07:38:20.95#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.197.07:38:20.95#ibcon#enter wrdev, iclass 4, count 2 2006.197.07:38:20.95#ibcon#first serial, iclass 4, count 2 2006.197.07:38:20.95#ibcon#enter sib2, iclass 4, count 2 2006.197.07:38:20.95#ibcon#flushed, iclass 4, count 2 2006.197.07:38:20.95#ibcon#about to write, iclass 4, count 2 2006.197.07:38:20.95#ibcon#wrote, iclass 4, count 2 2006.197.07:38:20.95#ibcon#about to read 3, iclass 4, count 2 2006.197.07:38:20.97#ibcon#read 3, iclass 4, count 2 2006.197.07:38:20.97#ibcon#about to read 4, iclass 4, count 2 2006.197.07:38:20.97#ibcon#read 4, iclass 4, count 2 2006.197.07:38:20.97#ibcon#about to read 5, iclass 4, count 2 2006.197.07:38:20.97#ibcon#read 5, iclass 4, count 2 2006.197.07:38:20.97#ibcon#about to read 6, iclass 4, count 2 2006.197.07:38:20.97#ibcon#read 6, iclass 4, count 2 2006.197.07:38:20.97#ibcon#end of sib2, iclass 4, count 2 2006.197.07:38:20.97#ibcon#*mode == 0, iclass 4, count 2 2006.197.07:38:20.97#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.197.07:38:20.97#ibcon#[27=AT03-04\r\n] 2006.197.07:38:20.97#ibcon#*before write, iclass 4, count 2 2006.197.07:38:20.97#ibcon#enter sib2, iclass 4, count 2 2006.197.07:38:20.97#ibcon#flushed, iclass 4, count 2 2006.197.07:38:20.97#ibcon#about to write, iclass 4, count 2 2006.197.07:38:20.97#ibcon#wrote, iclass 4, count 2 2006.197.07:38:20.97#ibcon#about to read 3, iclass 4, count 2 2006.197.07:38:21.00#ibcon#read 3, iclass 4, count 2 2006.197.07:38:21.00#ibcon#about to read 4, iclass 4, count 2 2006.197.07:38:21.00#ibcon#read 4, iclass 4, count 2 2006.197.07:38:21.00#ibcon#about to read 5, iclass 4, count 2 2006.197.07:38:21.00#ibcon#read 5, iclass 4, count 2 2006.197.07:38:21.00#ibcon#about to read 6, iclass 4, count 2 2006.197.07:38:21.00#ibcon#read 6, iclass 4, count 2 2006.197.07:38:21.00#ibcon#end of sib2, iclass 4, count 2 2006.197.07:38:21.00#ibcon#*after write, iclass 4, count 2 2006.197.07:38:21.00#ibcon#*before return 0, iclass 4, count 2 2006.197.07:38:21.00#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.197.07:38:21.00#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.197.07:38:21.00#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.197.07:38:21.00#ibcon#ireg 7 cls_cnt 0 2006.197.07:38:21.00#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.197.07:38:21.12#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.197.07:38:21.12#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.197.07:38:21.12#ibcon#enter wrdev, iclass 4, count 0 2006.197.07:38:21.12#ibcon#first serial, iclass 4, count 0 2006.197.07:38:21.12#ibcon#enter sib2, iclass 4, count 0 2006.197.07:38:21.12#ibcon#flushed, iclass 4, count 0 2006.197.07:38:21.12#ibcon#about to write, iclass 4, count 0 2006.197.07:38:21.12#ibcon#wrote, iclass 4, count 0 2006.197.07:38:21.12#ibcon#about to read 3, iclass 4, count 0 2006.197.07:38:21.14#ibcon#read 3, iclass 4, count 0 2006.197.07:38:21.14#ibcon#about to read 4, iclass 4, count 0 2006.197.07:38:21.14#ibcon#read 4, iclass 4, count 0 2006.197.07:38:21.14#ibcon#about to read 5, iclass 4, count 0 2006.197.07:38:21.14#ibcon#read 5, iclass 4, count 0 2006.197.07:38:21.14#ibcon#about to read 6, iclass 4, count 0 2006.197.07:38:21.14#ibcon#read 6, iclass 4, count 0 2006.197.07:38:21.14#ibcon#end of sib2, iclass 4, count 0 2006.197.07:38:21.14#ibcon#*mode == 0, iclass 4, count 0 2006.197.07:38:21.14#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.197.07:38:21.14#ibcon#[27=USB\r\n] 2006.197.07:38:21.14#ibcon#*before write, iclass 4, count 0 2006.197.07:38:21.14#ibcon#enter sib2, iclass 4, count 0 2006.197.07:38:21.14#ibcon#flushed, iclass 4, count 0 2006.197.07:38:21.14#ibcon#about to write, iclass 4, count 0 2006.197.07:38:21.14#ibcon#wrote, iclass 4, count 0 2006.197.07:38:21.14#ibcon#about to read 3, iclass 4, count 0 2006.197.07:38:21.17#ibcon#read 3, iclass 4, count 0 2006.197.07:38:21.17#ibcon#about to read 4, iclass 4, count 0 2006.197.07:38:21.17#ibcon#read 4, iclass 4, count 0 2006.197.07:38:21.17#ibcon#about to read 5, iclass 4, count 0 2006.197.07:38:21.17#ibcon#read 5, iclass 4, count 0 2006.197.07:38:21.17#ibcon#about to read 6, iclass 4, count 0 2006.197.07:38:21.17#ibcon#read 6, iclass 4, count 0 2006.197.07:38:21.17#ibcon#end of sib2, iclass 4, count 0 2006.197.07:38:21.17#ibcon#*after write, iclass 4, count 0 2006.197.07:38:21.17#ibcon#*before return 0, iclass 4, count 0 2006.197.07:38:21.17#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.197.07:38:21.17#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.197.07:38:21.17#ibcon#about to clear, iclass 4 cls_cnt 0 2006.197.07:38:21.17#ibcon#cleared, iclass 4 cls_cnt 0 2006.197.07:38:21.17$vc4f8/vblo=4,712.99 2006.197.07:38:21.17#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.197.07:38:21.17#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.197.07:38:21.17#ibcon#ireg 17 cls_cnt 0 2006.197.07:38:21.17#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.197.07:38:21.17#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.197.07:38:21.17#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.197.07:38:21.17#ibcon#enter wrdev, iclass 6, count 0 2006.197.07:38:21.17#ibcon#first serial, iclass 6, count 0 2006.197.07:38:21.17#ibcon#enter sib2, iclass 6, count 0 2006.197.07:38:21.17#ibcon#flushed, iclass 6, count 0 2006.197.07:38:21.17#ibcon#about to write, iclass 6, count 0 2006.197.07:38:21.17#ibcon#wrote, iclass 6, count 0 2006.197.07:38:21.17#ibcon#about to read 3, iclass 6, count 0 2006.197.07:38:21.19#ibcon#read 3, iclass 6, count 0 2006.197.07:38:21.19#ibcon#about to read 4, iclass 6, count 0 2006.197.07:38:21.19#ibcon#read 4, iclass 6, count 0 2006.197.07:38:21.19#ibcon#about to read 5, iclass 6, count 0 2006.197.07:38:21.19#ibcon#read 5, iclass 6, count 0 2006.197.07:38:21.19#ibcon#about to read 6, iclass 6, count 0 2006.197.07:38:21.19#ibcon#read 6, iclass 6, count 0 2006.197.07:38:21.19#ibcon#end of sib2, iclass 6, count 0 2006.197.07:38:21.19#ibcon#*mode == 0, iclass 6, count 0 2006.197.07:38:21.19#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.197.07:38:21.19#ibcon#[28=FRQ=04,712.99\r\n] 2006.197.07:38:21.19#ibcon#*before write, iclass 6, count 0 2006.197.07:38:21.19#ibcon#enter sib2, iclass 6, count 0 2006.197.07:38:21.19#ibcon#flushed, iclass 6, count 0 2006.197.07:38:21.19#ibcon#about to write, iclass 6, count 0 2006.197.07:38:21.19#ibcon#wrote, iclass 6, count 0 2006.197.07:38:21.19#ibcon#about to read 3, iclass 6, count 0 2006.197.07:38:21.23#ibcon#read 3, iclass 6, count 0 2006.197.07:38:21.23#ibcon#about to read 4, iclass 6, count 0 2006.197.07:38:21.23#ibcon#read 4, iclass 6, count 0 2006.197.07:38:21.23#ibcon#about to read 5, iclass 6, count 0 2006.197.07:38:21.23#ibcon#read 5, iclass 6, count 0 2006.197.07:38:21.23#ibcon#about to read 6, iclass 6, count 0 2006.197.07:38:21.23#ibcon#read 6, iclass 6, count 0 2006.197.07:38:21.23#ibcon#end of sib2, iclass 6, count 0 2006.197.07:38:21.23#ibcon#*after write, iclass 6, count 0 2006.197.07:38:21.23#ibcon#*before return 0, iclass 6, count 0 2006.197.07:38:21.23#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.197.07:38:21.23#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.197.07:38:21.23#ibcon#about to clear, iclass 6 cls_cnt 0 2006.197.07:38:21.23#ibcon#cleared, iclass 6 cls_cnt 0 2006.197.07:38:21.23$vc4f8/vb=4,4 2006.197.07:38:21.23#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.197.07:38:21.23#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.197.07:38:21.23#ibcon#ireg 11 cls_cnt 2 2006.197.07:38:21.23#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.197.07:38:21.29#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.197.07:38:21.29#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.197.07:38:21.29#ibcon#enter wrdev, iclass 10, count 2 2006.197.07:38:21.29#ibcon#first serial, iclass 10, count 2 2006.197.07:38:21.29#ibcon#enter sib2, iclass 10, count 2 2006.197.07:38:21.29#ibcon#flushed, iclass 10, count 2 2006.197.07:38:21.29#ibcon#about to write, iclass 10, count 2 2006.197.07:38:21.29#ibcon#wrote, iclass 10, count 2 2006.197.07:38:21.29#ibcon#about to read 3, iclass 10, count 2 2006.197.07:38:21.31#ibcon#read 3, iclass 10, count 2 2006.197.07:38:21.31#ibcon#about to read 4, iclass 10, count 2 2006.197.07:38:21.31#ibcon#read 4, iclass 10, count 2 2006.197.07:38:21.31#ibcon#about to read 5, iclass 10, count 2 2006.197.07:38:21.31#ibcon#read 5, iclass 10, count 2 2006.197.07:38:21.31#ibcon#about to read 6, iclass 10, count 2 2006.197.07:38:21.31#ibcon#read 6, iclass 10, count 2 2006.197.07:38:21.31#ibcon#end of sib2, iclass 10, count 2 2006.197.07:38:21.31#ibcon#*mode == 0, iclass 10, count 2 2006.197.07:38:21.31#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.197.07:38:21.31#ibcon#[27=AT04-04\r\n] 2006.197.07:38:21.31#ibcon#*before write, iclass 10, count 2 2006.197.07:38:21.31#ibcon#enter sib2, iclass 10, count 2 2006.197.07:38:21.31#ibcon#flushed, iclass 10, count 2 2006.197.07:38:21.31#ibcon#about to write, iclass 10, count 2 2006.197.07:38:21.31#ibcon#wrote, iclass 10, count 2 2006.197.07:38:21.31#ibcon#about to read 3, iclass 10, count 2 2006.197.07:38:21.34#ibcon#read 3, iclass 10, count 2 2006.197.07:38:21.34#ibcon#about to read 4, iclass 10, count 2 2006.197.07:38:21.34#ibcon#read 4, iclass 10, count 2 2006.197.07:38:21.34#ibcon#about to read 5, iclass 10, count 2 2006.197.07:38:21.34#ibcon#read 5, iclass 10, count 2 2006.197.07:38:21.34#ibcon#about to read 6, iclass 10, count 2 2006.197.07:38:21.34#ibcon#read 6, iclass 10, count 2 2006.197.07:38:21.34#ibcon#end of sib2, iclass 10, count 2 2006.197.07:38:21.34#ibcon#*after write, iclass 10, count 2 2006.197.07:38:21.34#ibcon#*before return 0, iclass 10, count 2 2006.197.07:38:21.34#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.197.07:38:21.34#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.197.07:38:21.34#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.197.07:38:21.34#ibcon#ireg 7 cls_cnt 0 2006.197.07:38:21.34#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.197.07:38:21.46#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.197.07:38:21.46#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.197.07:38:21.46#ibcon#enter wrdev, iclass 10, count 0 2006.197.07:38:21.46#ibcon#first serial, iclass 10, count 0 2006.197.07:38:21.46#ibcon#enter sib2, iclass 10, count 0 2006.197.07:38:21.46#ibcon#flushed, iclass 10, count 0 2006.197.07:38:21.46#ibcon#about to write, iclass 10, count 0 2006.197.07:38:21.46#ibcon#wrote, iclass 10, count 0 2006.197.07:38:21.46#ibcon#about to read 3, iclass 10, count 0 2006.197.07:38:21.48#ibcon#read 3, iclass 10, count 0 2006.197.07:38:21.48#ibcon#about to read 4, iclass 10, count 0 2006.197.07:38:21.48#ibcon#read 4, iclass 10, count 0 2006.197.07:38:21.48#ibcon#about to read 5, iclass 10, count 0 2006.197.07:38:21.48#ibcon#read 5, iclass 10, count 0 2006.197.07:38:21.48#ibcon#about to read 6, iclass 10, count 0 2006.197.07:38:21.48#ibcon#read 6, iclass 10, count 0 2006.197.07:38:21.48#ibcon#end of sib2, iclass 10, count 0 2006.197.07:38:21.48#ibcon#*mode == 0, iclass 10, count 0 2006.197.07:38:21.48#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.197.07:38:21.48#ibcon#[27=USB\r\n] 2006.197.07:38:21.48#ibcon#*before write, iclass 10, count 0 2006.197.07:38:21.48#ibcon#enter sib2, iclass 10, count 0 2006.197.07:38:21.48#ibcon#flushed, iclass 10, count 0 2006.197.07:38:21.48#ibcon#about to write, iclass 10, count 0 2006.197.07:38:21.48#ibcon#wrote, iclass 10, count 0 2006.197.07:38:21.48#ibcon#about to read 3, iclass 10, count 0 2006.197.07:38:21.51#ibcon#read 3, iclass 10, count 0 2006.197.07:38:21.51#ibcon#about to read 4, iclass 10, count 0 2006.197.07:38:21.51#ibcon#read 4, iclass 10, count 0 2006.197.07:38:21.51#ibcon#about to read 5, iclass 10, count 0 2006.197.07:38:21.51#ibcon#read 5, iclass 10, count 0 2006.197.07:38:21.51#ibcon#about to read 6, iclass 10, count 0 2006.197.07:38:21.51#ibcon#read 6, iclass 10, count 0 2006.197.07:38:21.51#ibcon#end of sib2, iclass 10, count 0 2006.197.07:38:21.51#ibcon#*after write, iclass 10, count 0 2006.197.07:38:21.51#ibcon#*before return 0, iclass 10, count 0 2006.197.07:38:21.51#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.197.07:38:21.51#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.197.07:38:21.51#ibcon#about to clear, iclass 10 cls_cnt 0 2006.197.07:38:21.51#ibcon#cleared, iclass 10 cls_cnt 0 2006.197.07:38:21.51$vc4f8/vblo=5,744.99 2006.197.07:38:21.51#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.197.07:38:21.51#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.197.07:38:21.51#ibcon#ireg 17 cls_cnt 0 2006.197.07:38:21.51#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.197.07:38:21.51#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.197.07:38:21.51#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.197.07:38:21.51#ibcon#enter wrdev, iclass 12, count 0 2006.197.07:38:21.51#ibcon#first serial, iclass 12, count 0 2006.197.07:38:21.51#ibcon#enter sib2, iclass 12, count 0 2006.197.07:38:21.51#ibcon#flushed, iclass 12, count 0 2006.197.07:38:21.51#ibcon#about to write, iclass 12, count 0 2006.197.07:38:21.51#ibcon#wrote, iclass 12, count 0 2006.197.07:38:21.51#ibcon#about to read 3, iclass 12, count 0 2006.197.07:38:21.53#ibcon#read 3, iclass 12, count 0 2006.197.07:38:21.53#ibcon#about to read 4, iclass 12, count 0 2006.197.07:38:21.53#ibcon#read 4, iclass 12, count 0 2006.197.07:38:21.53#ibcon#about to read 5, iclass 12, count 0 2006.197.07:38:21.53#ibcon#read 5, iclass 12, count 0 2006.197.07:38:21.53#ibcon#about to read 6, iclass 12, count 0 2006.197.07:38:21.53#ibcon#read 6, iclass 12, count 0 2006.197.07:38:21.53#ibcon#end of sib2, iclass 12, count 0 2006.197.07:38:21.53#ibcon#*mode == 0, iclass 12, count 0 2006.197.07:38:21.53#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.197.07:38:21.53#ibcon#[28=FRQ=05,744.99\r\n] 2006.197.07:38:21.53#ibcon#*before write, iclass 12, count 0 2006.197.07:38:21.53#ibcon#enter sib2, iclass 12, count 0 2006.197.07:38:21.53#ibcon#flushed, iclass 12, count 0 2006.197.07:38:21.53#ibcon#about to write, iclass 12, count 0 2006.197.07:38:21.53#ibcon#wrote, iclass 12, count 0 2006.197.07:38:21.53#ibcon#about to read 3, iclass 12, count 0 2006.197.07:38:21.57#ibcon#read 3, iclass 12, count 0 2006.197.07:38:21.57#ibcon#about to read 4, iclass 12, count 0 2006.197.07:38:21.57#ibcon#read 4, iclass 12, count 0 2006.197.07:38:21.57#ibcon#about to read 5, iclass 12, count 0 2006.197.07:38:21.57#ibcon#read 5, iclass 12, count 0 2006.197.07:38:21.57#ibcon#about to read 6, iclass 12, count 0 2006.197.07:38:21.57#ibcon#read 6, iclass 12, count 0 2006.197.07:38:21.57#ibcon#end of sib2, iclass 12, count 0 2006.197.07:38:21.57#ibcon#*after write, iclass 12, count 0 2006.197.07:38:21.57#ibcon#*before return 0, iclass 12, count 0 2006.197.07:38:21.57#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.197.07:38:21.57#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.197.07:38:21.57#ibcon#about to clear, iclass 12 cls_cnt 0 2006.197.07:38:21.57#ibcon#cleared, iclass 12 cls_cnt 0 2006.197.07:38:21.57$vc4f8/vb=5,4 2006.197.07:38:21.57#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.197.07:38:21.57#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.197.07:38:21.57#ibcon#ireg 11 cls_cnt 2 2006.197.07:38:21.57#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.197.07:38:21.63#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.197.07:38:21.63#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.197.07:38:21.63#ibcon#enter wrdev, iclass 14, count 2 2006.197.07:38:21.63#ibcon#first serial, iclass 14, count 2 2006.197.07:38:21.63#ibcon#enter sib2, iclass 14, count 2 2006.197.07:38:21.63#ibcon#flushed, iclass 14, count 2 2006.197.07:38:21.63#ibcon#about to write, iclass 14, count 2 2006.197.07:38:21.63#ibcon#wrote, iclass 14, count 2 2006.197.07:38:21.63#ibcon#about to read 3, iclass 14, count 2 2006.197.07:38:21.65#ibcon#read 3, iclass 14, count 2 2006.197.07:38:21.65#ibcon#about to read 4, iclass 14, count 2 2006.197.07:38:21.65#ibcon#read 4, iclass 14, count 2 2006.197.07:38:21.65#ibcon#about to read 5, iclass 14, count 2 2006.197.07:38:21.65#ibcon#read 5, iclass 14, count 2 2006.197.07:38:21.65#ibcon#about to read 6, iclass 14, count 2 2006.197.07:38:21.65#ibcon#read 6, iclass 14, count 2 2006.197.07:38:21.65#ibcon#end of sib2, iclass 14, count 2 2006.197.07:38:21.65#ibcon#*mode == 0, iclass 14, count 2 2006.197.07:38:21.65#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.197.07:38:21.65#ibcon#[27=AT05-04\r\n] 2006.197.07:38:21.65#ibcon#*before write, iclass 14, count 2 2006.197.07:38:21.65#ibcon#enter sib2, iclass 14, count 2 2006.197.07:38:21.65#ibcon#flushed, iclass 14, count 2 2006.197.07:38:21.65#ibcon#about to write, iclass 14, count 2 2006.197.07:38:21.65#ibcon#wrote, iclass 14, count 2 2006.197.07:38:21.65#ibcon#about to read 3, iclass 14, count 2 2006.197.07:38:21.68#ibcon#read 3, iclass 14, count 2 2006.197.07:38:21.68#ibcon#about to read 4, iclass 14, count 2 2006.197.07:38:21.68#ibcon#read 4, iclass 14, count 2 2006.197.07:38:21.68#ibcon#about to read 5, iclass 14, count 2 2006.197.07:38:21.68#ibcon#read 5, iclass 14, count 2 2006.197.07:38:21.68#ibcon#about to read 6, iclass 14, count 2 2006.197.07:38:21.68#ibcon#read 6, iclass 14, count 2 2006.197.07:38:21.68#ibcon#end of sib2, iclass 14, count 2 2006.197.07:38:21.68#ibcon#*after write, iclass 14, count 2 2006.197.07:38:21.68#ibcon#*before return 0, iclass 14, count 2 2006.197.07:38:21.68#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.197.07:38:21.68#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.197.07:38:21.68#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.197.07:38:21.68#ibcon#ireg 7 cls_cnt 0 2006.197.07:38:21.68#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.197.07:38:21.80#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.197.07:38:21.80#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.197.07:38:21.80#ibcon#enter wrdev, iclass 14, count 0 2006.197.07:38:21.80#ibcon#first serial, iclass 14, count 0 2006.197.07:38:21.80#ibcon#enter sib2, iclass 14, count 0 2006.197.07:38:21.80#ibcon#flushed, iclass 14, count 0 2006.197.07:38:21.80#ibcon#about to write, iclass 14, count 0 2006.197.07:38:21.80#ibcon#wrote, iclass 14, count 0 2006.197.07:38:21.80#ibcon#about to read 3, iclass 14, count 0 2006.197.07:38:21.82#ibcon#read 3, iclass 14, count 0 2006.197.07:38:21.82#ibcon#about to read 4, iclass 14, count 0 2006.197.07:38:21.82#ibcon#read 4, iclass 14, count 0 2006.197.07:38:21.82#ibcon#about to read 5, iclass 14, count 0 2006.197.07:38:21.82#ibcon#read 5, iclass 14, count 0 2006.197.07:38:21.82#ibcon#about to read 6, iclass 14, count 0 2006.197.07:38:21.82#ibcon#read 6, iclass 14, count 0 2006.197.07:38:21.82#ibcon#end of sib2, iclass 14, count 0 2006.197.07:38:21.82#ibcon#*mode == 0, iclass 14, count 0 2006.197.07:38:21.82#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.197.07:38:21.82#ibcon#[27=USB\r\n] 2006.197.07:38:21.82#ibcon#*before write, iclass 14, count 0 2006.197.07:38:21.82#ibcon#enter sib2, iclass 14, count 0 2006.197.07:38:21.82#ibcon#flushed, iclass 14, count 0 2006.197.07:38:21.82#ibcon#about to write, iclass 14, count 0 2006.197.07:38:21.82#ibcon#wrote, iclass 14, count 0 2006.197.07:38:21.82#ibcon#about to read 3, iclass 14, count 0 2006.197.07:38:21.85#ibcon#read 3, iclass 14, count 0 2006.197.07:38:21.85#ibcon#about to read 4, iclass 14, count 0 2006.197.07:38:21.85#ibcon#read 4, iclass 14, count 0 2006.197.07:38:21.85#ibcon#about to read 5, iclass 14, count 0 2006.197.07:38:21.85#ibcon#read 5, iclass 14, count 0 2006.197.07:38:21.85#ibcon#about to read 6, iclass 14, count 0 2006.197.07:38:21.85#ibcon#read 6, iclass 14, count 0 2006.197.07:38:21.85#ibcon#end of sib2, iclass 14, count 0 2006.197.07:38:21.85#ibcon#*after write, iclass 14, count 0 2006.197.07:38:21.85#ibcon#*before return 0, iclass 14, count 0 2006.197.07:38:21.85#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.197.07:38:21.85#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.197.07:38:21.85#ibcon#about to clear, iclass 14 cls_cnt 0 2006.197.07:38:21.85#ibcon#cleared, iclass 14 cls_cnt 0 2006.197.07:38:21.85$vc4f8/vblo=6,752.99 2006.197.07:38:21.85#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.197.07:38:21.85#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.197.07:38:21.85#ibcon#ireg 17 cls_cnt 0 2006.197.07:38:21.85#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.197.07:38:21.85#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.197.07:38:21.85#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.197.07:38:21.85#ibcon#enter wrdev, iclass 16, count 0 2006.197.07:38:21.85#ibcon#first serial, iclass 16, count 0 2006.197.07:38:21.85#ibcon#enter sib2, iclass 16, count 0 2006.197.07:38:21.85#ibcon#flushed, iclass 16, count 0 2006.197.07:38:21.85#ibcon#about to write, iclass 16, count 0 2006.197.07:38:21.85#ibcon#wrote, iclass 16, count 0 2006.197.07:38:21.85#ibcon#about to read 3, iclass 16, count 0 2006.197.07:38:21.87#ibcon#read 3, iclass 16, count 0 2006.197.07:38:21.87#ibcon#about to read 4, iclass 16, count 0 2006.197.07:38:21.87#ibcon#read 4, iclass 16, count 0 2006.197.07:38:21.87#ibcon#about to read 5, iclass 16, count 0 2006.197.07:38:21.87#ibcon#read 5, iclass 16, count 0 2006.197.07:38:21.87#ibcon#about to read 6, iclass 16, count 0 2006.197.07:38:21.87#ibcon#read 6, iclass 16, count 0 2006.197.07:38:21.87#ibcon#end of sib2, iclass 16, count 0 2006.197.07:38:21.87#ibcon#*mode == 0, iclass 16, count 0 2006.197.07:38:21.87#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.197.07:38:21.87#ibcon#[28=FRQ=06,752.99\r\n] 2006.197.07:38:21.87#ibcon#*before write, iclass 16, count 0 2006.197.07:38:21.87#ibcon#enter sib2, iclass 16, count 0 2006.197.07:38:21.87#ibcon#flushed, iclass 16, count 0 2006.197.07:38:21.87#ibcon#about to write, iclass 16, count 0 2006.197.07:38:21.87#ibcon#wrote, iclass 16, count 0 2006.197.07:38:21.87#ibcon#about to read 3, iclass 16, count 0 2006.197.07:38:21.91#ibcon#read 3, iclass 16, count 0 2006.197.07:38:21.91#ibcon#about to read 4, iclass 16, count 0 2006.197.07:38:21.91#ibcon#read 4, iclass 16, count 0 2006.197.07:38:21.91#ibcon#about to read 5, iclass 16, count 0 2006.197.07:38:21.91#ibcon#read 5, iclass 16, count 0 2006.197.07:38:21.91#ibcon#about to read 6, iclass 16, count 0 2006.197.07:38:21.91#ibcon#read 6, iclass 16, count 0 2006.197.07:38:21.91#ibcon#end of sib2, iclass 16, count 0 2006.197.07:38:21.91#ibcon#*after write, iclass 16, count 0 2006.197.07:38:21.91#ibcon#*before return 0, iclass 16, count 0 2006.197.07:38:21.91#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.197.07:38:21.91#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.197.07:38:21.91#ibcon#about to clear, iclass 16 cls_cnt 0 2006.197.07:38:21.91#ibcon#cleared, iclass 16 cls_cnt 0 2006.197.07:38:21.91$vc4f8/vb=6,4 2006.197.07:38:21.91#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.197.07:38:21.91#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.197.07:38:21.91#ibcon#ireg 11 cls_cnt 2 2006.197.07:38:21.91#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.197.07:38:21.97#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.197.07:38:21.97#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.197.07:38:21.97#ibcon#enter wrdev, iclass 18, count 2 2006.197.07:38:21.97#ibcon#first serial, iclass 18, count 2 2006.197.07:38:21.97#ibcon#enter sib2, iclass 18, count 2 2006.197.07:38:21.97#ibcon#flushed, iclass 18, count 2 2006.197.07:38:21.97#ibcon#about to write, iclass 18, count 2 2006.197.07:38:21.97#ibcon#wrote, iclass 18, count 2 2006.197.07:38:21.97#ibcon#about to read 3, iclass 18, count 2 2006.197.07:38:21.99#ibcon#read 3, iclass 18, count 2 2006.197.07:38:21.99#ibcon#about to read 4, iclass 18, count 2 2006.197.07:38:21.99#ibcon#read 4, iclass 18, count 2 2006.197.07:38:21.99#ibcon#about to read 5, iclass 18, count 2 2006.197.07:38:21.99#ibcon#read 5, iclass 18, count 2 2006.197.07:38:21.99#ibcon#about to read 6, iclass 18, count 2 2006.197.07:38:21.99#ibcon#read 6, iclass 18, count 2 2006.197.07:38:21.99#ibcon#end of sib2, iclass 18, count 2 2006.197.07:38:21.99#ibcon#*mode == 0, iclass 18, count 2 2006.197.07:38:21.99#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.197.07:38:21.99#ibcon#[27=AT06-04\r\n] 2006.197.07:38:21.99#ibcon#*before write, iclass 18, count 2 2006.197.07:38:21.99#ibcon#enter sib2, iclass 18, count 2 2006.197.07:38:21.99#ibcon#flushed, iclass 18, count 2 2006.197.07:38:21.99#ibcon#about to write, iclass 18, count 2 2006.197.07:38:21.99#ibcon#wrote, iclass 18, count 2 2006.197.07:38:21.99#ibcon#about to read 3, iclass 18, count 2 2006.197.07:38:22.02#ibcon#read 3, iclass 18, count 2 2006.197.07:38:22.02#ibcon#about to read 4, iclass 18, count 2 2006.197.07:38:22.02#ibcon#read 4, iclass 18, count 2 2006.197.07:38:22.02#ibcon#about to read 5, iclass 18, count 2 2006.197.07:38:22.02#ibcon#read 5, iclass 18, count 2 2006.197.07:38:22.02#ibcon#about to read 6, iclass 18, count 2 2006.197.07:38:22.02#ibcon#read 6, iclass 18, count 2 2006.197.07:38:22.02#ibcon#end of sib2, iclass 18, count 2 2006.197.07:38:22.02#ibcon#*after write, iclass 18, count 2 2006.197.07:38:22.02#ibcon#*before return 0, iclass 18, count 2 2006.197.07:38:22.02#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.197.07:38:22.02#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.197.07:38:22.02#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.197.07:38:22.02#ibcon#ireg 7 cls_cnt 0 2006.197.07:38:22.02#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.197.07:38:22.14#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.197.07:38:22.14#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.197.07:38:22.14#ibcon#enter wrdev, iclass 18, count 0 2006.197.07:38:22.14#ibcon#first serial, iclass 18, count 0 2006.197.07:38:22.14#ibcon#enter sib2, iclass 18, count 0 2006.197.07:38:22.14#ibcon#flushed, iclass 18, count 0 2006.197.07:38:22.14#ibcon#about to write, iclass 18, count 0 2006.197.07:38:22.14#ibcon#wrote, iclass 18, count 0 2006.197.07:38:22.14#ibcon#about to read 3, iclass 18, count 0 2006.197.07:38:22.16#ibcon#read 3, iclass 18, count 0 2006.197.07:38:22.16#ibcon#about to read 4, iclass 18, count 0 2006.197.07:38:22.16#ibcon#read 4, iclass 18, count 0 2006.197.07:38:22.16#ibcon#about to read 5, iclass 18, count 0 2006.197.07:38:22.16#ibcon#read 5, iclass 18, count 0 2006.197.07:38:22.16#ibcon#about to read 6, iclass 18, count 0 2006.197.07:38:22.16#ibcon#read 6, iclass 18, count 0 2006.197.07:38:22.16#ibcon#end of sib2, iclass 18, count 0 2006.197.07:38:22.16#ibcon#*mode == 0, iclass 18, count 0 2006.197.07:38:22.16#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.197.07:38:22.16#ibcon#[27=USB\r\n] 2006.197.07:38:22.16#ibcon#*before write, iclass 18, count 0 2006.197.07:38:22.16#ibcon#enter sib2, iclass 18, count 0 2006.197.07:38:22.16#ibcon#flushed, iclass 18, count 0 2006.197.07:38:22.16#ibcon#about to write, iclass 18, count 0 2006.197.07:38:22.16#ibcon#wrote, iclass 18, count 0 2006.197.07:38:22.16#ibcon#about to read 3, iclass 18, count 0 2006.197.07:38:22.19#ibcon#read 3, iclass 18, count 0 2006.197.07:38:22.19#ibcon#about to read 4, iclass 18, count 0 2006.197.07:38:22.19#ibcon#read 4, iclass 18, count 0 2006.197.07:38:22.19#ibcon#about to read 5, iclass 18, count 0 2006.197.07:38:22.19#ibcon#read 5, iclass 18, count 0 2006.197.07:38:22.19#ibcon#about to read 6, iclass 18, count 0 2006.197.07:38:22.19#ibcon#read 6, iclass 18, count 0 2006.197.07:38:22.19#ibcon#end of sib2, iclass 18, count 0 2006.197.07:38:22.19#ibcon#*after write, iclass 18, count 0 2006.197.07:38:22.19#ibcon#*before return 0, iclass 18, count 0 2006.197.07:38:22.19#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.197.07:38:22.19#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.197.07:38:22.19#ibcon#about to clear, iclass 18 cls_cnt 0 2006.197.07:38:22.19#ibcon#cleared, iclass 18 cls_cnt 0 2006.197.07:38:22.19$vc4f8/vabw=wide 2006.197.07:38:22.19#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.197.07:38:22.19#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.197.07:38:22.19#ibcon#ireg 8 cls_cnt 0 2006.197.07:38:22.19#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.197.07:38:22.19#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.197.07:38:22.19#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.197.07:38:22.19#ibcon#enter wrdev, iclass 20, count 0 2006.197.07:38:22.19#ibcon#first serial, iclass 20, count 0 2006.197.07:38:22.19#ibcon#enter sib2, iclass 20, count 0 2006.197.07:38:22.19#ibcon#flushed, iclass 20, count 0 2006.197.07:38:22.19#ibcon#about to write, iclass 20, count 0 2006.197.07:38:22.19#ibcon#wrote, iclass 20, count 0 2006.197.07:38:22.19#ibcon#about to read 3, iclass 20, count 0 2006.197.07:38:22.21#ibcon#read 3, iclass 20, count 0 2006.197.07:38:22.21#ibcon#about to read 4, iclass 20, count 0 2006.197.07:38:22.21#ibcon#read 4, iclass 20, count 0 2006.197.07:38:22.21#ibcon#about to read 5, iclass 20, count 0 2006.197.07:38:22.21#ibcon#read 5, iclass 20, count 0 2006.197.07:38:22.21#ibcon#about to read 6, iclass 20, count 0 2006.197.07:38:22.21#ibcon#read 6, iclass 20, count 0 2006.197.07:38:22.21#ibcon#end of sib2, iclass 20, count 0 2006.197.07:38:22.21#ibcon#*mode == 0, iclass 20, count 0 2006.197.07:38:22.21#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.197.07:38:22.21#ibcon#[25=BW32\r\n] 2006.197.07:38:22.21#ibcon#*before write, iclass 20, count 0 2006.197.07:38:22.21#ibcon#enter sib2, iclass 20, count 0 2006.197.07:38:22.21#ibcon#flushed, iclass 20, count 0 2006.197.07:38:22.21#ibcon#about to write, iclass 20, count 0 2006.197.07:38:22.21#ibcon#wrote, iclass 20, count 0 2006.197.07:38:22.21#ibcon#about to read 3, iclass 20, count 0 2006.197.07:38:22.24#ibcon#read 3, iclass 20, count 0 2006.197.07:38:22.24#ibcon#about to read 4, iclass 20, count 0 2006.197.07:38:22.24#ibcon#read 4, iclass 20, count 0 2006.197.07:38:22.24#ibcon#about to read 5, iclass 20, count 0 2006.197.07:38:22.24#ibcon#read 5, iclass 20, count 0 2006.197.07:38:22.24#ibcon#about to read 6, iclass 20, count 0 2006.197.07:38:22.24#ibcon#read 6, iclass 20, count 0 2006.197.07:38:22.24#ibcon#end of sib2, iclass 20, count 0 2006.197.07:38:22.24#ibcon#*after write, iclass 20, count 0 2006.197.07:38:22.24#ibcon#*before return 0, iclass 20, count 0 2006.197.07:38:22.24#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.197.07:38:22.24#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.197.07:38:22.24#ibcon#about to clear, iclass 20 cls_cnt 0 2006.197.07:38:22.24#ibcon#cleared, iclass 20 cls_cnt 0 2006.197.07:38:22.24$vc4f8/vbbw=wide 2006.197.07:38:22.24#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.197.07:38:22.24#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.197.07:38:22.24#ibcon#ireg 8 cls_cnt 0 2006.197.07:38:22.24#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.197.07:38:22.31#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.197.07:38:22.31#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.197.07:38:22.31#ibcon#enter wrdev, iclass 22, count 0 2006.197.07:38:22.31#ibcon#first serial, iclass 22, count 0 2006.197.07:38:22.31#ibcon#enter sib2, iclass 22, count 0 2006.197.07:38:22.31#ibcon#flushed, iclass 22, count 0 2006.197.07:38:22.31#ibcon#about to write, iclass 22, count 0 2006.197.07:38:22.31#ibcon#wrote, iclass 22, count 0 2006.197.07:38:22.31#ibcon#about to read 3, iclass 22, count 0 2006.197.07:38:22.33#ibcon#read 3, iclass 22, count 0 2006.197.07:38:22.33#ibcon#about to read 4, iclass 22, count 0 2006.197.07:38:22.33#ibcon#read 4, iclass 22, count 0 2006.197.07:38:22.33#ibcon#about to read 5, iclass 22, count 0 2006.197.07:38:22.33#ibcon#read 5, iclass 22, count 0 2006.197.07:38:22.33#ibcon#about to read 6, iclass 22, count 0 2006.197.07:38:22.33#ibcon#read 6, iclass 22, count 0 2006.197.07:38:22.33#ibcon#end of sib2, iclass 22, count 0 2006.197.07:38:22.33#ibcon#*mode == 0, iclass 22, count 0 2006.197.07:38:22.33#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.197.07:38:22.33#ibcon#[27=BW32\r\n] 2006.197.07:38:22.33#ibcon#*before write, iclass 22, count 0 2006.197.07:38:22.33#ibcon#enter sib2, iclass 22, count 0 2006.197.07:38:22.33#ibcon#flushed, iclass 22, count 0 2006.197.07:38:22.33#ibcon#about to write, iclass 22, count 0 2006.197.07:38:22.33#ibcon#wrote, iclass 22, count 0 2006.197.07:38:22.33#ibcon#about to read 3, iclass 22, count 0 2006.197.07:38:22.36#ibcon#read 3, iclass 22, count 0 2006.197.07:38:22.36#ibcon#about to read 4, iclass 22, count 0 2006.197.07:38:22.36#ibcon#read 4, iclass 22, count 0 2006.197.07:38:22.36#ibcon#about to read 5, iclass 22, count 0 2006.197.07:38:22.36#ibcon#read 5, iclass 22, count 0 2006.197.07:38:22.36#ibcon#about to read 6, iclass 22, count 0 2006.197.07:38:22.36#ibcon#read 6, iclass 22, count 0 2006.197.07:38:22.36#ibcon#end of sib2, iclass 22, count 0 2006.197.07:38:22.36#ibcon#*after write, iclass 22, count 0 2006.197.07:38:22.36#ibcon#*before return 0, iclass 22, count 0 2006.197.07:38:22.36#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.197.07:38:22.36#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.197.07:38:22.36#ibcon#about to clear, iclass 22 cls_cnt 0 2006.197.07:38:22.36#ibcon#cleared, iclass 22 cls_cnt 0 2006.197.07:38:22.36$4f8m12a/ifd4f 2006.197.07:38:22.36$ifd4f/lo= 2006.197.07:38:22.36$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.197.07:38:22.36$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.197.07:38:22.36$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.197.07:38:22.36$ifd4f/patch= 2006.197.07:38:22.36$ifd4f/patch=lo1,a1,a2,a3,a4 2006.197.07:38:22.36$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.197.07:38:22.36$ifd4f/patch=lo3,a5,a6,a7,a8 2006.197.07:38:22.36$4f8m12a/"form=m,16.000,1:2 2006.197.07:38:22.36$4f8m12a/"tpicd 2006.197.07:38:22.36$4f8m12a/echo=off 2006.197.07:38:22.36$4f8m12a/xlog=off 2006.197.07:38:22.36:!2006.197.07:38:50 2006.197.07:38:29.13#trakl#Source acquired 2006.197.07:38:29.13#flagr#flagr/antenna,acquired 2006.197.07:38:50.00:preob 2006.197.07:38:51.13/onsource/TRACKING 2006.197.07:38:51.13:!2006.197.07:39:00 2006.197.07:39:00.00:data_valid=on 2006.197.07:39:00.00:midob 2006.197.07:39:00.13/onsource/TRACKING 2006.197.07:39:00.13/wx/25.89,1003.2,97 2006.197.07:39:00.18/cable/+6.3689E-03 2006.197.07:39:01.27/va/01,08,usb,yes,29,31 2006.197.07:39:01.27/va/02,07,usb,yes,30,31 2006.197.07:39:01.27/va/03,06,usb,yes,31,31 2006.197.07:39:01.27/va/04,07,usb,yes,31,33 2006.197.07:39:01.27/va/05,07,usb,yes,34,36 2006.197.07:39:01.27/va/06,06,usb,yes,33,33 2006.197.07:39:01.27/va/07,06,usb,yes,34,34 2006.197.07:39:01.27/va/08,07,usb,yes,32,32 2006.197.07:39:01.50/valo/01,532.99,yes,locked 2006.197.07:39:01.50/valo/02,572.99,yes,locked 2006.197.07:39:01.50/valo/03,672.99,yes,locked 2006.197.07:39:01.50/valo/04,832.99,yes,locked 2006.197.07:39:01.50/valo/05,652.99,yes,locked 2006.197.07:39:01.50/valo/06,772.99,yes,locked 2006.197.07:39:01.50/valo/07,832.99,yes,locked 2006.197.07:39:01.50/valo/08,852.99,yes,locked 2006.197.07:39:02.59/vb/01,04,usb,yes,29,28 2006.197.07:39:02.59/vb/02,04,usb,yes,31,32 2006.197.07:39:02.59/vb/03,04,usb,yes,27,31 2006.197.07:39:02.59/vb/04,04,usb,yes,28,28 2006.197.07:39:02.59/vb/05,04,usb,yes,27,31 2006.197.07:39:02.59/vb/06,04,usb,yes,28,30 2006.197.07:39:02.59/vb/07,04,usb,yes,30,30 2006.197.07:39:02.59/vb/08,04,usb,yes,27,31 2006.197.07:39:02.82/vblo/01,632.99,yes,locked 2006.197.07:39:02.82/vblo/02,640.99,yes,locked 2006.197.07:39:02.82/vblo/03,656.99,yes,locked 2006.197.07:39:02.82/vblo/04,712.99,yes,locked 2006.197.07:39:02.82/vblo/05,744.99,yes,locked 2006.197.07:39:02.82/vblo/06,752.99,yes,locked 2006.197.07:39:02.82/vblo/07,734.99,yes,locked 2006.197.07:39:02.82/vblo/08,744.99,yes,locked 2006.197.07:39:02.97/vabw/8 2006.197.07:39:03.12/vbbw/8 2006.197.07:39:03.21/xfe/off,on,15.2 2006.197.07:39:03.58/ifatt/23,28,28,28 2006.197.07:39:04.10/fmout-gps/S +2.97E-07 2006.197.07:39:04.13:!2006.197.07:40:00 2006.197.07:40:00.00:data_valid=off 2006.197.07:40:00.00:postob 2006.197.07:40:00.21/cable/+6.3684E-03 2006.197.07:40:00.21/wx/25.87,1003.2,97 2006.197.07:40:01.10/fmout-gps/S +2.98E-07 2006.197.07:40:01.10:scan_name=197-0740,k06197,60 2006.197.07:40:01.10:source=1803+784,180045.68,782804.0,2000.0,cw 2006.197.07:40:01.14#flagr#flagr/antenna,new-source 2006.197.07:40:02.14:checkk5 2006.197.07:40:02.48/chk_autoobs//k5ts1/ autoobs is running! 2006.197.07:40:02.82/chk_autoobs//k5ts2/ autoobs is running! 2006.197.07:40:03.16/chk_autoobs//k5ts3/ autoobs is running! 2006.197.07:40:03.51/chk_autoobs//k5ts4/ autoobs is running! 2006.197.07:40:03.86/chk_obsdata//k5ts1/T1970739??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.07:40:04.20/chk_obsdata//k5ts2/T1970739??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.07:40:04.54/chk_obsdata//k5ts3/T1970739??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.07:40:04.87/chk_obsdata//k5ts4/T1970739??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.07:40:05.53/k5log//k5ts1_log_newline 2006.197.07:40:06.19/k5log//k5ts2_log_newline 2006.197.07:40:06.84/k5log//k5ts3_log_newline 2006.197.07:40:07.51/k5log//k5ts4_log_newline 2006.197.07:40:07.53/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.197.07:40:07.53:4f8m12a=1 2006.197.07:40:07.53$4f8m12a/echo=on 2006.197.07:40:07.53$4f8m12a/pcalon 2006.197.07:40:07.53$pcalon/"no phase cal control is implemented here 2006.197.07:40:07.53$4f8m12a/"tpicd=stop 2006.197.07:40:07.53$4f8m12a/vc4f8 2006.197.07:40:07.53$vc4f8/valo=1,532.99 2006.197.07:40:07.54#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.197.07:40:07.54#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.197.07:40:07.54#ibcon#ireg 17 cls_cnt 0 2006.197.07:40:07.54#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.197.07:40:07.54#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.197.07:40:07.54#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.197.07:40:07.54#ibcon#enter wrdev, iclass 33, count 0 2006.197.07:40:07.54#ibcon#first serial, iclass 33, count 0 2006.197.07:40:07.54#ibcon#enter sib2, iclass 33, count 0 2006.197.07:40:07.54#ibcon#flushed, iclass 33, count 0 2006.197.07:40:07.54#ibcon#about to write, iclass 33, count 0 2006.197.07:40:07.54#ibcon#wrote, iclass 33, count 0 2006.197.07:40:07.54#ibcon#about to read 3, iclass 33, count 0 2006.197.07:40:07.56#ibcon#read 3, iclass 33, count 0 2006.197.07:40:07.56#ibcon#about to read 4, iclass 33, count 0 2006.197.07:40:07.56#ibcon#read 4, iclass 33, count 0 2006.197.07:40:07.56#ibcon#about to read 5, iclass 33, count 0 2006.197.07:40:07.56#ibcon#read 5, iclass 33, count 0 2006.197.07:40:07.56#ibcon#about to read 6, iclass 33, count 0 2006.197.07:40:07.56#ibcon#read 6, iclass 33, count 0 2006.197.07:40:07.56#ibcon#end of sib2, iclass 33, count 0 2006.197.07:40:07.56#ibcon#*mode == 0, iclass 33, count 0 2006.197.07:40:07.56#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.197.07:40:07.56#ibcon#[26=FRQ=01,532.99\r\n] 2006.197.07:40:07.56#ibcon#*before write, iclass 33, count 0 2006.197.07:40:07.56#ibcon#enter sib2, iclass 33, count 0 2006.197.07:40:07.56#ibcon#flushed, iclass 33, count 0 2006.197.07:40:07.56#ibcon#about to write, iclass 33, count 0 2006.197.07:40:07.56#ibcon#wrote, iclass 33, count 0 2006.197.07:40:07.56#ibcon#about to read 3, iclass 33, count 0 2006.197.07:40:07.61#ibcon#read 3, iclass 33, count 0 2006.197.07:40:07.61#ibcon#about to read 4, iclass 33, count 0 2006.197.07:40:07.61#ibcon#read 4, iclass 33, count 0 2006.197.07:40:07.61#ibcon#about to read 5, iclass 33, count 0 2006.197.07:40:07.61#ibcon#read 5, iclass 33, count 0 2006.197.07:40:07.61#ibcon#about to read 6, iclass 33, count 0 2006.197.07:40:07.61#ibcon#read 6, iclass 33, count 0 2006.197.07:40:07.61#ibcon#end of sib2, iclass 33, count 0 2006.197.07:40:07.61#ibcon#*after write, iclass 33, count 0 2006.197.07:40:07.61#ibcon#*before return 0, iclass 33, count 0 2006.197.07:40:07.61#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.197.07:40:07.61#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.197.07:40:07.61#ibcon#about to clear, iclass 33 cls_cnt 0 2006.197.07:40:07.61#ibcon#cleared, iclass 33 cls_cnt 0 2006.197.07:40:07.61$vc4f8/va=1,8 2006.197.07:40:07.61#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.197.07:40:07.61#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.197.07:40:07.61#ibcon#ireg 11 cls_cnt 2 2006.197.07:40:07.61#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.197.07:40:07.61#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.197.07:40:07.61#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.197.07:40:07.61#ibcon#enter wrdev, iclass 35, count 2 2006.197.07:40:07.61#ibcon#first serial, iclass 35, count 2 2006.197.07:40:07.61#ibcon#enter sib2, iclass 35, count 2 2006.197.07:40:07.61#ibcon#flushed, iclass 35, count 2 2006.197.07:40:07.61#ibcon#about to write, iclass 35, count 2 2006.197.07:40:07.61#ibcon#wrote, iclass 35, count 2 2006.197.07:40:07.61#ibcon#about to read 3, iclass 35, count 2 2006.197.07:40:07.63#ibcon#read 3, iclass 35, count 2 2006.197.07:40:07.63#ibcon#about to read 4, iclass 35, count 2 2006.197.07:40:07.63#ibcon#read 4, iclass 35, count 2 2006.197.07:40:07.63#ibcon#about to read 5, iclass 35, count 2 2006.197.07:40:07.63#ibcon#read 5, iclass 35, count 2 2006.197.07:40:07.63#ibcon#about to read 6, iclass 35, count 2 2006.197.07:40:07.63#ibcon#read 6, iclass 35, count 2 2006.197.07:40:07.63#ibcon#end of sib2, iclass 35, count 2 2006.197.07:40:07.63#ibcon#*mode == 0, iclass 35, count 2 2006.197.07:40:07.63#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.197.07:40:07.63#ibcon#[25=AT01-08\r\n] 2006.197.07:40:07.63#ibcon#*before write, iclass 35, count 2 2006.197.07:40:07.63#ibcon#enter sib2, iclass 35, count 2 2006.197.07:40:07.63#ibcon#flushed, iclass 35, count 2 2006.197.07:40:07.63#ibcon#about to write, iclass 35, count 2 2006.197.07:40:07.63#ibcon#wrote, iclass 35, count 2 2006.197.07:40:07.63#ibcon#about to read 3, iclass 35, count 2 2006.197.07:40:07.66#ibcon#read 3, iclass 35, count 2 2006.197.07:40:07.66#ibcon#about to read 4, iclass 35, count 2 2006.197.07:40:07.66#ibcon#read 4, iclass 35, count 2 2006.197.07:40:07.66#ibcon#about to read 5, iclass 35, count 2 2006.197.07:40:07.66#ibcon#read 5, iclass 35, count 2 2006.197.07:40:07.66#ibcon#about to read 6, iclass 35, count 2 2006.197.07:40:07.66#ibcon#read 6, iclass 35, count 2 2006.197.07:40:07.66#ibcon#end of sib2, iclass 35, count 2 2006.197.07:40:07.66#ibcon#*after write, iclass 35, count 2 2006.197.07:40:07.66#ibcon#*before return 0, iclass 35, count 2 2006.197.07:40:07.66#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.197.07:40:07.66#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.197.07:40:07.66#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.197.07:40:07.66#ibcon#ireg 7 cls_cnt 0 2006.197.07:40:07.66#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.197.07:40:07.78#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.197.07:40:07.78#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.197.07:40:07.78#ibcon#enter wrdev, iclass 35, count 0 2006.197.07:40:07.78#ibcon#first serial, iclass 35, count 0 2006.197.07:40:07.78#ibcon#enter sib2, iclass 35, count 0 2006.197.07:40:07.78#ibcon#flushed, iclass 35, count 0 2006.197.07:40:07.78#ibcon#about to write, iclass 35, count 0 2006.197.07:40:07.78#ibcon#wrote, iclass 35, count 0 2006.197.07:40:07.78#ibcon#about to read 3, iclass 35, count 0 2006.197.07:40:07.80#ibcon#read 3, iclass 35, count 0 2006.197.07:40:07.80#ibcon#about to read 4, iclass 35, count 0 2006.197.07:40:07.80#ibcon#read 4, iclass 35, count 0 2006.197.07:40:07.80#ibcon#about to read 5, iclass 35, count 0 2006.197.07:40:07.80#ibcon#read 5, iclass 35, count 0 2006.197.07:40:07.80#ibcon#about to read 6, iclass 35, count 0 2006.197.07:40:07.80#ibcon#read 6, iclass 35, count 0 2006.197.07:40:07.80#ibcon#end of sib2, iclass 35, count 0 2006.197.07:40:07.80#ibcon#*mode == 0, iclass 35, count 0 2006.197.07:40:07.80#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.197.07:40:07.80#ibcon#[25=USB\r\n] 2006.197.07:40:07.80#ibcon#*before write, iclass 35, count 0 2006.197.07:40:07.80#ibcon#enter sib2, iclass 35, count 0 2006.197.07:40:07.80#ibcon#flushed, iclass 35, count 0 2006.197.07:40:07.80#ibcon#about to write, iclass 35, count 0 2006.197.07:40:07.80#ibcon#wrote, iclass 35, count 0 2006.197.07:40:07.80#ibcon#about to read 3, iclass 35, count 0 2006.197.07:40:07.83#ibcon#read 3, iclass 35, count 0 2006.197.07:40:07.83#ibcon#about to read 4, iclass 35, count 0 2006.197.07:40:07.83#ibcon#read 4, iclass 35, count 0 2006.197.07:40:07.83#ibcon#about to read 5, iclass 35, count 0 2006.197.07:40:07.83#ibcon#read 5, iclass 35, count 0 2006.197.07:40:07.83#ibcon#about to read 6, iclass 35, count 0 2006.197.07:40:07.83#ibcon#read 6, iclass 35, count 0 2006.197.07:40:07.83#ibcon#end of sib2, iclass 35, count 0 2006.197.07:40:07.83#ibcon#*after write, iclass 35, count 0 2006.197.07:40:07.83#ibcon#*before return 0, iclass 35, count 0 2006.197.07:40:07.83#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.197.07:40:07.83#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.197.07:40:07.83#ibcon#about to clear, iclass 35 cls_cnt 0 2006.197.07:40:07.83#ibcon#cleared, iclass 35 cls_cnt 0 2006.197.07:40:07.83$vc4f8/valo=2,572.99 2006.197.07:40:07.83#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.197.07:40:07.83#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.197.07:40:07.83#ibcon#ireg 17 cls_cnt 0 2006.197.07:40:07.83#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.197.07:40:07.83#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.197.07:40:07.83#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.197.07:40:07.83#ibcon#enter wrdev, iclass 37, count 0 2006.197.07:40:07.83#ibcon#first serial, iclass 37, count 0 2006.197.07:40:07.83#ibcon#enter sib2, iclass 37, count 0 2006.197.07:40:07.83#ibcon#flushed, iclass 37, count 0 2006.197.07:40:07.83#ibcon#about to write, iclass 37, count 0 2006.197.07:40:07.83#ibcon#wrote, iclass 37, count 0 2006.197.07:40:07.83#ibcon#about to read 3, iclass 37, count 0 2006.197.07:40:07.85#ibcon#read 3, iclass 37, count 0 2006.197.07:40:07.85#ibcon#about to read 4, iclass 37, count 0 2006.197.07:40:07.85#ibcon#read 4, iclass 37, count 0 2006.197.07:40:07.85#ibcon#about to read 5, iclass 37, count 0 2006.197.07:40:07.85#ibcon#read 5, iclass 37, count 0 2006.197.07:40:07.85#ibcon#about to read 6, iclass 37, count 0 2006.197.07:40:07.85#ibcon#read 6, iclass 37, count 0 2006.197.07:40:07.85#ibcon#end of sib2, iclass 37, count 0 2006.197.07:40:07.85#ibcon#*mode == 0, iclass 37, count 0 2006.197.07:40:07.85#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.197.07:40:07.85#ibcon#[26=FRQ=02,572.99\r\n] 2006.197.07:40:07.85#ibcon#*before write, iclass 37, count 0 2006.197.07:40:07.85#ibcon#enter sib2, iclass 37, count 0 2006.197.07:40:07.85#ibcon#flushed, iclass 37, count 0 2006.197.07:40:07.85#ibcon#about to write, iclass 37, count 0 2006.197.07:40:07.85#ibcon#wrote, iclass 37, count 0 2006.197.07:40:07.85#ibcon#about to read 3, iclass 37, count 0 2006.197.07:40:07.89#ibcon#read 3, iclass 37, count 0 2006.197.07:40:07.89#ibcon#about to read 4, iclass 37, count 0 2006.197.07:40:07.89#ibcon#read 4, iclass 37, count 0 2006.197.07:40:07.89#ibcon#about to read 5, iclass 37, count 0 2006.197.07:40:07.89#ibcon#read 5, iclass 37, count 0 2006.197.07:40:07.89#ibcon#about to read 6, iclass 37, count 0 2006.197.07:40:07.89#ibcon#read 6, iclass 37, count 0 2006.197.07:40:07.89#ibcon#end of sib2, iclass 37, count 0 2006.197.07:40:07.89#ibcon#*after write, iclass 37, count 0 2006.197.07:40:07.89#ibcon#*before return 0, iclass 37, count 0 2006.197.07:40:07.89#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.197.07:40:07.89#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.197.07:40:07.89#ibcon#about to clear, iclass 37 cls_cnt 0 2006.197.07:40:07.89#ibcon#cleared, iclass 37 cls_cnt 0 2006.197.07:40:07.89$vc4f8/va=2,7 2006.197.07:40:07.89#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.197.07:40:07.89#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.197.07:40:07.89#ibcon#ireg 11 cls_cnt 2 2006.197.07:40:07.89#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.197.07:40:07.95#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.197.07:40:07.95#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.197.07:40:07.95#ibcon#enter wrdev, iclass 39, count 2 2006.197.07:40:07.95#ibcon#first serial, iclass 39, count 2 2006.197.07:40:07.95#ibcon#enter sib2, iclass 39, count 2 2006.197.07:40:07.95#ibcon#flushed, iclass 39, count 2 2006.197.07:40:07.95#ibcon#about to write, iclass 39, count 2 2006.197.07:40:07.95#ibcon#wrote, iclass 39, count 2 2006.197.07:40:07.95#ibcon#about to read 3, iclass 39, count 2 2006.197.07:40:07.97#ibcon#read 3, iclass 39, count 2 2006.197.07:40:07.97#ibcon#about to read 4, iclass 39, count 2 2006.197.07:40:07.97#ibcon#read 4, iclass 39, count 2 2006.197.07:40:07.97#ibcon#about to read 5, iclass 39, count 2 2006.197.07:40:07.97#ibcon#read 5, iclass 39, count 2 2006.197.07:40:07.97#ibcon#about to read 6, iclass 39, count 2 2006.197.07:40:07.97#ibcon#read 6, iclass 39, count 2 2006.197.07:40:07.97#ibcon#end of sib2, iclass 39, count 2 2006.197.07:40:07.97#ibcon#*mode == 0, iclass 39, count 2 2006.197.07:40:07.97#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.197.07:40:07.97#ibcon#[25=AT02-07\r\n] 2006.197.07:40:07.97#ibcon#*before write, iclass 39, count 2 2006.197.07:40:07.97#ibcon#enter sib2, iclass 39, count 2 2006.197.07:40:07.97#ibcon#flushed, iclass 39, count 2 2006.197.07:40:07.97#ibcon#about to write, iclass 39, count 2 2006.197.07:40:07.97#ibcon#wrote, iclass 39, count 2 2006.197.07:40:07.97#ibcon#about to read 3, iclass 39, count 2 2006.197.07:40:08.00#ibcon#read 3, iclass 39, count 2 2006.197.07:40:08.00#ibcon#about to read 4, iclass 39, count 2 2006.197.07:40:08.00#ibcon#read 4, iclass 39, count 2 2006.197.07:40:08.00#ibcon#about to read 5, iclass 39, count 2 2006.197.07:40:08.00#ibcon#read 5, iclass 39, count 2 2006.197.07:40:08.00#ibcon#about to read 6, iclass 39, count 2 2006.197.07:40:08.00#ibcon#read 6, iclass 39, count 2 2006.197.07:40:08.00#ibcon#end of sib2, iclass 39, count 2 2006.197.07:40:08.00#ibcon#*after write, iclass 39, count 2 2006.197.07:40:08.00#ibcon#*before return 0, iclass 39, count 2 2006.197.07:40:08.00#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.197.07:40:08.00#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.197.07:40:08.00#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.197.07:40:08.00#ibcon#ireg 7 cls_cnt 0 2006.197.07:40:08.00#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.197.07:40:08.12#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.197.07:40:08.12#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.197.07:40:08.12#ibcon#enter wrdev, iclass 39, count 0 2006.197.07:40:08.12#ibcon#first serial, iclass 39, count 0 2006.197.07:40:08.12#ibcon#enter sib2, iclass 39, count 0 2006.197.07:40:08.12#ibcon#flushed, iclass 39, count 0 2006.197.07:40:08.12#ibcon#about to write, iclass 39, count 0 2006.197.07:40:08.12#ibcon#wrote, iclass 39, count 0 2006.197.07:40:08.12#ibcon#about to read 3, iclass 39, count 0 2006.197.07:40:08.14#ibcon#read 3, iclass 39, count 0 2006.197.07:40:08.14#ibcon#about to read 4, iclass 39, count 0 2006.197.07:40:08.14#ibcon#read 4, iclass 39, count 0 2006.197.07:40:08.14#ibcon#about to read 5, iclass 39, count 0 2006.197.07:40:08.14#ibcon#read 5, iclass 39, count 0 2006.197.07:40:08.14#ibcon#about to read 6, iclass 39, count 0 2006.197.07:40:08.14#ibcon#read 6, iclass 39, count 0 2006.197.07:40:08.14#ibcon#end of sib2, iclass 39, count 0 2006.197.07:40:08.14#ibcon#*mode == 0, iclass 39, count 0 2006.197.07:40:08.14#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.197.07:40:08.14#ibcon#[25=USB\r\n] 2006.197.07:40:08.14#ibcon#*before write, iclass 39, count 0 2006.197.07:40:08.14#ibcon#enter sib2, iclass 39, count 0 2006.197.07:40:08.14#ibcon#flushed, iclass 39, count 0 2006.197.07:40:08.14#ibcon#about to write, iclass 39, count 0 2006.197.07:40:08.14#ibcon#wrote, iclass 39, count 0 2006.197.07:40:08.14#ibcon#about to read 3, iclass 39, count 0 2006.197.07:40:08.17#ibcon#read 3, iclass 39, count 0 2006.197.07:40:08.17#ibcon#about to read 4, iclass 39, count 0 2006.197.07:40:08.17#ibcon#read 4, iclass 39, count 0 2006.197.07:40:08.17#ibcon#about to read 5, iclass 39, count 0 2006.197.07:40:08.17#ibcon#read 5, iclass 39, count 0 2006.197.07:40:08.17#ibcon#about to read 6, iclass 39, count 0 2006.197.07:40:08.17#ibcon#read 6, iclass 39, count 0 2006.197.07:40:08.17#ibcon#end of sib2, iclass 39, count 0 2006.197.07:40:08.17#ibcon#*after write, iclass 39, count 0 2006.197.07:40:08.17#ibcon#*before return 0, iclass 39, count 0 2006.197.07:40:08.17#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.197.07:40:08.17#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.197.07:40:08.17#ibcon#about to clear, iclass 39 cls_cnt 0 2006.197.07:40:08.17#ibcon#cleared, iclass 39 cls_cnt 0 2006.197.07:40:08.17$vc4f8/valo=3,672.99 2006.197.07:40:08.17#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.197.07:40:08.17#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.197.07:40:08.17#ibcon#ireg 17 cls_cnt 0 2006.197.07:40:08.17#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.197.07:40:08.17#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.197.07:40:08.17#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.197.07:40:08.17#ibcon#enter wrdev, iclass 3, count 0 2006.197.07:40:08.17#ibcon#first serial, iclass 3, count 0 2006.197.07:40:08.17#ibcon#enter sib2, iclass 3, count 0 2006.197.07:40:08.17#ibcon#flushed, iclass 3, count 0 2006.197.07:40:08.17#ibcon#about to write, iclass 3, count 0 2006.197.07:40:08.17#ibcon#wrote, iclass 3, count 0 2006.197.07:40:08.17#ibcon#about to read 3, iclass 3, count 0 2006.197.07:40:08.19#ibcon#read 3, iclass 3, count 0 2006.197.07:40:08.19#ibcon#about to read 4, iclass 3, count 0 2006.197.07:40:08.19#ibcon#read 4, iclass 3, count 0 2006.197.07:40:08.19#ibcon#about to read 5, iclass 3, count 0 2006.197.07:40:08.19#ibcon#read 5, iclass 3, count 0 2006.197.07:40:08.19#ibcon#about to read 6, iclass 3, count 0 2006.197.07:40:08.19#ibcon#read 6, iclass 3, count 0 2006.197.07:40:08.19#ibcon#end of sib2, iclass 3, count 0 2006.197.07:40:08.19#ibcon#*mode == 0, iclass 3, count 0 2006.197.07:40:08.19#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.197.07:40:08.19#ibcon#[26=FRQ=03,672.99\r\n] 2006.197.07:40:08.19#ibcon#*before write, iclass 3, count 0 2006.197.07:40:08.19#ibcon#enter sib2, iclass 3, count 0 2006.197.07:40:08.19#ibcon#flushed, iclass 3, count 0 2006.197.07:40:08.19#ibcon#about to write, iclass 3, count 0 2006.197.07:40:08.19#ibcon#wrote, iclass 3, count 0 2006.197.07:40:08.19#ibcon#about to read 3, iclass 3, count 0 2006.197.07:40:08.23#ibcon#read 3, iclass 3, count 0 2006.197.07:40:08.23#ibcon#about to read 4, iclass 3, count 0 2006.197.07:40:08.23#ibcon#read 4, iclass 3, count 0 2006.197.07:40:08.23#ibcon#about to read 5, iclass 3, count 0 2006.197.07:40:08.23#ibcon#read 5, iclass 3, count 0 2006.197.07:40:08.23#ibcon#about to read 6, iclass 3, count 0 2006.197.07:40:08.23#ibcon#read 6, iclass 3, count 0 2006.197.07:40:08.23#ibcon#end of sib2, iclass 3, count 0 2006.197.07:40:08.23#ibcon#*after write, iclass 3, count 0 2006.197.07:40:08.23#ibcon#*before return 0, iclass 3, count 0 2006.197.07:40:08.23#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.197.07:40:08.23#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.197.07:40:08.23#ibcon#about to clear, iclass 3 cls_cnt 0 2006.197.07:40:08.23#ibcon#cleared, iclass 3 cls_cnt 0 2006.197.07:40:08.23$vc4f8/va=3,6 2006.197.07:40:08.23#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.197.07:40:08.23#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.197.07:40:08.23#ibcon#ireg 11 cls_cnt 2 2006.197.07:40:08.23#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.197.07:40:08.29#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.197.07:40:08.29#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.197.07:40:08.29#ibcon#enter wrdev, iclass 5, count 2 2006.197.07:40:08.29#ibcon#first serial, iclass 5, count 2 2006.197.07:40:08.29#ibcon#enter sib2, iclass 5, count 2 2006.197.07:40:08.29#ibcon#flushed, iclass 5, count 2 2006.197.07:40:08.29#ibcon#about to write, iclass 5, count 2 2006.197.07:40:08.29#ibcon#wrote, iclass 5, count 2 2006.197.07:40:08.29#ibcon#about to read 3, iclass 5, count 2 2006.197.07:40:08.31#ibcon#read 3, iclass 5, count 2 2006.197.07:40:08.31#ibcon#about to read 4, iclass 5, count 2 2006.197.07:40:08.31#ibcon#read 4, iclass 5, count 2 2006.197.07:40:08.31#ibcon#about to read 5, iclass 5, count 2 2006.197.07:40:08.31#ibcon#read 5, iclass 5, count 2 2006.197.07:40:08.31#ibcon#about to read 6, iclass 5, count 2 2006.197.07:40:08.31#ibcon#read 6, iclass 5, count 2 2006.197.07:40:08.31#ibcon#end of sib2, iclass 5, count 2 2006.197.07:40:08.31#ibcon#*mode == 0, iclass 5, count 2 2006.197.07:40:08.31#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.197.07:40:08.31#ibcon#[25=AT03-06\r\n] 2006.197.07:40:08.31#ibcon#*before write, iclass 5, count 2 2006.197.07:40:08.31#ibcon#enter sib2, iclass 5, count 2 2006.197.07:40:08.31#ibcon#flushed, iclass 5, count 2 2006.197.07:40:08.31#ibcon#about to write, iclass 5, count 2 2006.197.07:40:08.31#ibcon#wrote, iclass 5, count 2 2006.197.07:40:08.31#ibcon#about to read 3, iclass 5, count 2 2006.197.07:40:08.34#ibcon#read 3, iclass 5, count 2 2006.197.07:40:08.34#ibcon#about to read 4, iclass 5, count 2 2006.197.07:40:08.34#ibcon#read 4, iclass 5, count 2 2006.197.07:40:08.34#ibcon#about to read 5, iclass 5, count 2 2006.197.07:40:08.34#ibcon#read 5, iclass 5, count 2 2006.197.07:40:08.34#ibcon#about to read 6, iclass 5, count 2 2006.197.07:40:08.34#ibcon#read 6, iclass 5, count 2 2006.197.07:40:08.34#ibcon#end of sib2, iclass 5, count 2 2006.197.07:40:08.34#ibcon#*after write, iclass 5, count 2 2006.197.07:40:08.34#ibcon#*before return 0, iclass 5, count 2 2006.197.07:40:08.34#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.197.07:40:08.34#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.197.07:40:08.34#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.197.07:40:08.34#ibcon#ireg 7 cls_cnt 0 2006.197.07:40:08.34#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.197.07:40:08.46#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.197.07:40:08.46#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.197.07:40:08.46#ibcon#enter wrdev, iclass 5, count 0 2006.197.07:40:08.46#ibcon#first serial, iclass 5, count 0 2006.197.07:40:08.46#ibcon#enter sib2, iclass 5, count 0 2006.197.07:40:08.46#ibcon#flushed, iclass 5, count 0 2006.197.07:40:08.46#ibcon#about to write, iclass 5, count 0 2006.197.07:40:08.46#ibcon#wrote, iclass 5, count 0 2006.197.07:40:08.46#ibcon#about to read 3, iclass 5, count 0 2006.197.07:40:08.48#ibcon#read 3, iclass 5, count 0 2006.197.07:40:08.48#ibcon#about to read 4, iclass 5, count 0 2006.197.07:40:08.48#ibcon#read 4, iclass 5, count 0 2006.197.07:40:08.48#ibcon#about to read 5, iclass 5, count 0 2006.197.07:40:08.48#ibcon#read 5, iclass 5, count 0 2006.197.07:40:08.48#ibcon#about to read 6, iclass 5, count 0 2006.197.07:40:08.48#ibcon#read 6, iclass 5, count 0 2006.197.07:40:08.48#ibcon#end of sib2, iclass 5, count 0 2006.197.07:40:08.48#ibcon#*mode == 0, iclass 5, count 0 2006.197.07:40:08.48#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.197.07:40:08.48#ibcon#[25=USB\r\n] 2006.197.07:40:08.48#ibcon#*before write, iclass 5, count 0 2006.197.07:40:08.48#ibcon#enter sib2, iclass 5, count 0 2006.197.07:40:08.48#ibcon#flushed, iclass 5, count 0 2006.197.07:40:08.48#ibcon#about to write, iclass 5, count 0 2006.197.07:40:08.48#ibcon#wrote, iclass 5, count 0 2006.197.07:40:08.48#ibcon#about to read 3, iclass 5, count 0 2006.197.07:40:08.51#ibcon#read 3, iclass 5, count 0 2006.197.07:40:08.51#ibcon#about to read 4, iclass 5, count 0 2006.197.07:40:08.51#ibcon#read 4, iclass 5, count 0 2006.197.07:40:08.51#ibcon#about to read 5, iclass 5, count 0 2006.197.07:40:08.51#ibcon#read 5, iclass 5, count 0 2006.197.07:40:08.51#ibcon#about to read 6, iclass 5, count 0 2006.197.07:40:08.51#ibcon#read 6, iclass 5, count 0 2006.197.07:40:08.51#ibcon#end of sib2, iclass 5, count 0 2006.197.07:40:08.51#ibcon#*after write, iclass 5, count 0 2006.197.07:40:08.51#ibcon#*before return 0, iclass 5, count 0 2006.197.07:40:08.51#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.197.07:40:08.51#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.197.07:40:08.51#ibcon#about to clear, iclass 5 cls_cnt 0 2006.197.07:40:08.51#ibcon#cleared, iclass 5 cls_cnt 0 2006.197.07:40:08.51$vc4f8/valo=4,832.99 2006.197.07:40:08.51#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.197.07:40:08.51#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.197.07:40:08.51#ibcon#ireg 17 cls_cnt 0 2006.197.07:40:08.51#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.197.07:40:08.51#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.197.07:40:08.51#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.197.07:40:08.51#ibcon#enter wrdev, iclass 7, count 0 2006.197.07:40:08.51#ibcon#first serial, iclass 7, count 0 2006.197.07:40:08.51#ibcon#enter sib2, iclass 7, count 0 2006.197.07:40:08.51#ibcon#flushed, iclass 7, count 0 2006.197.07:40:08.51#ibcon#about to write, iclass 7, count 0 2006.197.07:40:08.51#ibcon#wrote, iclass 7, count 0 2006.197.07:40:08.51#ibcon#about to read 3, iclass 7, count 0 2006.197.07:40:08.53#ibcon#read 3, iclass 7, count 0 2006.197.07:40:08.53#ibcon#about to read 4, iclass 7, count 0 2006.197.07:40:08.53#ibcon#read 4, iclass 7, count 0 2006.197.07:40:08.53#ibcon#about to read 5, iclass 7, count 0 2006.197.07:40:08.53#ibcon#read 5, iclass 7, count 0 2006.197.07:40:08.53#ibcon#about to read 6, iclass 7, count 0 2006.197.07:40:08.53#ibcon#read 6, iclass 7, count 0 2006.197.07:40:08.53#ibcon#end of sib2, iclass 7, count 0 2006.197.07:40:08.53#ibcon#*mode == 0, iclass 7, count 0 2006.197.07:40:08.53#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.197.07:40:08.53#ibcon#[26=FRQ=04,832.99\r\n] 2006.197.07:40:08.53#ibcon#*before write, iclass 7, count 0 2006.197.07:40:08.53#ibcon#enter sib2, iclass 7, count 0 2006.197.07:40:08.53#ibcon#flushed, iclass 7, count 0 2006.197.07:40:08.53#ibcon#about to write, iclass 7, count 0 2006.197.07:40:08.53#ibcon#wrote, iclass 7, count 0 2006.197.07:40:08.53#ibcon#about to read 3, iclass 7, count 0 2006.197.07:40:08.57#ibcon#read 3, iclass 7, count 0 2006.197.07:40:08.57#ibcon#about to read 4, iclass 7, count 0 2006.197.07:40:08.57#ibcon#read 4, iclass 7, count 0 2006.197.07:40:08.57#ibcon#about to read 5, iclass 7, count 0 2006.197.07:40:08.57#ibcon#read 5, iclass 7, count 0 2006.197.07:40:08.57#ibcon#about to read 6, iclass 7, count 0 2006.197.07:40:08.57#ibcon#read 6, iclass 7, count 0 2006.197.07:40:08.57#ibcon#end of sib2, iclass 7, count 0 2006.197.07:40:08.57#ibcon#*after write, iclass 7, count 0 2006.197.07:40:08.57#ibcon#*before return 0, iclass 7, count 0 2006.197.07:40:08.57#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.197.07:40:08.57#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.197.07:40:08.57#ibcon#about to clear, iclass 7 cls_cnt 0 2006.197.07:40:08.57#ibcon#cleared, iclass 7 cls_cnt 0 2006.197.07:40:08.57$vc4f8/va=4,7 2006.197.07:40:08.57#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.197.07:40:08.57#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.197.07:40:08.57#ibcon#ireg 11 cls_cnt 2 2006.197.07:40:08.57#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.197.07:40:08.63#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.197.07:40:08.63#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.197.07:40:08.63#ibcon#enter wrdev, iclass 11, count 2 2006.197.07:40:08.63#ibcon#first serial, iclass 11, count 2 2006.197.07:40:08.63#ibcon#enter sib2, iclass 11, count 2 2006.197.07:40:08.63#ibcon#flushed, iclass 11, count 2 2006.197.07:40:08.63#ibcon#about to write, iclass 11, count 2 2006.197.07:40:08.63#ibcon#wrote, iclass 11, count 2 2006.197.07:40:08.63#ibcon#about to read 3, iclass 11, count 2 2006.197.07:40:08.65#ibcon#read 3, iclass 11, count 2 2006.197.07:40:08.65#ibcon#about to read 4, iclass 11, count 2 2006.197.07:40:08.65#ibcon#read 4, iclass 11, count 2 2006.197.07:40:08.65#ibcon#about to read 5, iclass 11, count 2 2006.197.07:40:08.65#ibcon#read 5, iclass 11, count 2 2006.197.07:40:08.65#ibcon#about to read 6, iclass 11, count 2 2006.197.07:40:08.65#ibcon#read 6, iclass 11, count 2 2006.197.07:40:08.65#ibcon#end of sib2, iclass 11, count 2 2006.197.07:40:08.65#ibcon#*mode == 0, iclass 11, count 2 2006.197.07:40:08.65#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.197.07:40:08.65#ibcon#[25=AT04-07\r\n] 2006.197.07:40:08.65#ibcon#*before write, iclass 11, count 2 2006.197.07:40:08.65#ibcon#enter sib2, iclass 11, count 2 2006.197.07:40:08.65#ibcon#flushed, iclass 11, count 2 2006.197.07:40:08.65#ibcon#about to write, iclass 11, count 2 2006.197.07:40:08.65#ibcon#wrote, iclass 11, count 2 2006.197.07:40:08.65#ibcon#about to read 3, iclass 11, count 2 2006.197.07:40:08.68#ibcon#read 3, iclass 11, count 2 2006.197.07:40:08.68#ibcon#about to read 4, iclass 11, count 2 2006.197.07:40:08.68#ibcon#read 4, iclass 11, count 2 2006.197.07:40:08.68#ibcon#about to read 5, iclass 11, count 2 2006.197.07:40:08.68#ibcon#read 5, iclass 11, count 2 2006.197.07:40:08.68#ibcon#about to read 6, iclass 11, count 2 2006.197.07:40:08.68#ibcon#read 6, iclass 11, count 2 2006.197.07:40:08.68#ibcon#end of sib2, iclass 11, count 2 2006.197.07:40:08.68#ibcon#*after write, iclass 11, count 2 2006.197.07:40:08.68#ibcon#*before return 0, iclass 11, count 2 2006.197.07:40:08.68#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.197.07:40:08.68#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.197.07:40:08.68#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.197.07:40:08.68#ibcon#ireg 7 cls_cnt 0 2006.197.07:40:08.68#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.197.07:40:08.80#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.197.07:40:08.80#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.197.07:40:08.80#ibcon#enter wrdev, iclass 11, count 0 2006.197.07:40:08.80#ibcon#first serial, iclass 11, count 0 2006.197.07:40:08.80#ibcon#enter sib2, iclass 11, count 0 2006.197.07:40:08.80#ibcon#flushed, iclass 11, count 0 2006.197.07:40:08.80#ibcon#about to write, iclass 11, count 0 2006.197.07:40:08.80#ibcon#wrote, iclass 11, count 0 2006.197.07:40:08.80#ibcon#about to read 3, iclass 11, count 0 2006.197.07:40:08.82#ibcon#read 3, iclass 11, count 0 2006.197.07:40:08.82#ibcon#about to read 4, iclass 11, count 0 2006.197.07:40:08.82#ibcon#read 4, iclass 11, count 0 2006.197.07:40:08.82#ibcon#about to read 5, iclass 11, count 0 2006.197.07:40:08.82#ibcon#read 5, iclass 11, count 0 2006.197.07:40:08.82#ibcon#about to read 6, iclass 11, count 0 2006.197.07:40:08.82#ibcon#read 6, iclass 11, count 0 2006.197.07:40:08.82#ibcon#end of sib2, iclass 11, count 0 2006.197.07:40:08.82#ibcon#*mode == 0, iclass 11, count 0 2006.197.07:40:08.82#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.197.07:40:08.82#ibcon#[25=USB\r\n] 2006.197.07:40:08.82#ibcon#*before write, iclass 11, count 0 2006.197.07:40:08.82#ibcon#enter sib2, iclass 11, count 0 2006.197.07:40:08.82#ibcon#flushed, iclass 11, count 0 2006.197.07:40:08.82#ibcon#about to write, iclass 11, count 0 2006.197.07:40:08.82#ibcon#wrote, iclass 11, count 0 2006.197.07:40:08.82#ibcon#about to read 3, iclass 11, count 0 2006.197.07:40:08.85#ibcon#read 3, iclass 11, count 0 2006.197.07:40:08.85#ibcon#about to read 4, iclass 11, count 0 2006.197.07:40:08.85#ibcon#read 4, iclass 11, count 0 2006.197.07:40:08.85#ibcon#about to read 5, iclass 11, count 0 2006.197.07:40:08.85#ibcon#read 5, iclass 11, count 0 2006.197.07:40:08.85#ibcon#about to read 6, iclass 11, count 0 2006.197.07:40:08.85#ibcon#read 6, iclass 11, count 0 2006.197.07:40:08.85#ibcon#end of sib2, iclass 11, count 0 2006.197.07:40:08.85#ibcon#*after write, iclass 11, count 0 2006.197.07:40:08.85#ibcon#*before return 0, iclass 11, count 0 2006.197.07:40:08.85#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.197.07:40:08.85#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.197.07:40:08.85#ibcon#about to clear, iclass 11 cls_cnt 0 2006.197.07:40:08.85#ibcon#cleared, iclass 11 cls_cnt 0 2006.197.07:40:08.85$vc4f8/valo=5,652.99 2006.197.07:40:08.85#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.197.07:40:08.85#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.197.07:40:08.85#ibcon#ireg 17 cls_cnt 0 2006.197.07:40:08.85#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.197.07:40:08.85#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.197.07:40:08.85#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.197.07:40:08.85#ibcon#enter wrdev, iclass 13, count 0 2006.197.07:40:08.85#ibcon#first serial, iclass 13, count 0 2006.197.07:40:08.85#ibcon#enter sib2, iclass 13, count 0 2006.197.07:40:08.85#ibcon#flushed, iclass 13, count 0 2006.197.07:40:08.85#ibcon#about to write, iclass 13, count 0 2006.197.07:40:08.85#ibcon#wrote, iclass 13, count 0 2006.197.07:40:08.85#ibcon#about to read 3, iclass 13, count 0 2006.197.07:40:08.87#ibcon#read 3, iclass 13, count 0 2006.197.07:40:08.87#ibcon#about to read 4, iclass 13, count 0 2006.197.07:40:08.87#ibcon#read 4, iclass 13, count 0 2006.197.07:40:08.87#ibcon#about to read 5, iclass 13, count 0 2006.197.07:40:08.87#ibcon#read 5, iclass 13, count 0 2006.197.07:40:08.87#ibcon#about to read 6, iclass 13, count 0 2006.197.07:40:08.87#ibcon#read 6, iclass 13, count 0 2006.197.07:40:08.87#ibcon#end of sib2, iclass 13, count 0 2006.197.07:40:08.87#ibcon#*mode == 0, iclass 13, count 0 2006.197.07:40:08.87#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.197.07:40:08.87#ibcon#[26=FRQ=05,652.99\r\n] 2006.197.07:40:08.87#ibcon#*before write, iclass 13, count 0 2006.197.07:40:08.87#ibcon#enter sib2, iclass 13, count 0 2006.197.07:40:08.87#ibcon#flushed, iclass 13, count 0 2006.197.07:40:08.87#ibcon#about to write, iclass 13, count 0 2006.197.07:40:08.87#ibcon#wrote, iclass 13, count 0 2006.197.07:40:08.87#ibcon#about to read 3, iclass 13, count 0 2006.197.07:40:08.91#ibcon#read 3, iclass 13, count 0 2006.197.07:40:08.91#ibcon#about to read 4, iclass 13, count 0 2006.197.07:40:08.91#ibcon#read 4, iclass 13, count 0 2006.197.07:40:08.91#ibcon#about to read 5, iclass 13, count 0 2006.197.07:40:08.91#ibcon#read 5, iclass 13, count 0 2006.197.07:40:08.91#ibcon#about to read 6, iclass 13, count 0 2006.197.07:40:08.91#ibcon#read 6, iclass 13, count 0 2006.197.07:40:08.91#ibcon#end of sib2, iclass 13, count 0 2006.197.07:40:08.91#ibcon#*after write, iclass 13, count 0 2006.197.07:40:08.91#ibcon#*before return 0, iclass 13, count 0 2006.197.07:40:08.91#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.197.07:40:08.91#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.197.07:40:08.91#ibcon#about to clear, iclass 13 cls_cnt 0 2006.197.07:40:08.91#ibcon#cleared, iclass 13 cls_cnt 0 2006.197.07:40:08.91$vc4f8/va=5,7 2006.197.07:40:08.91#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.197.07:40:08.91#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.197.07:40:08.91#ibcon#ireg 11 cls_cnt 2 2006.197.07:40:08.91#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.197.07:40:08.97#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.197.07:40:08.97#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.197.07:40:08.97#ibcon#enter wrdev, iclass 15, count 2 2006.197.07:40:08.97#ibcon#first serial, iclass 15, count 2 2006.197.07:40:08.97#ibcon#enter sib2, iclass 15, count 2 2006.197.07:40:08.97#ibcon#flushed, iclass 15, count 2 2006.197.07:40:08.97#ibcon#about to write, iclass 15, count 2 2006.197.07:40:08.97#ibcon#wrote, iclass 15, count 2 2006.197.07:40:08.97#ibcon#about to read 3, iclass 15, count 2 2006.197.07:40:08.99#ibcon#read 3, iclass 15, count 2 2006.197.07:40:08.99#ibcon#about to read 4, iclass 15, count 2 2006.197.07:40:08.99#ibcon#read 4, iclass 15, count 2 2006.197.07:40:08.99#ibcon#about to read 5, iclass 15, count 2 2006.197.07:40:08.99#ibcon#read 5, iclass 15, count 2 2006.197.07:40:08.99#ibcon#about to read 6, iclass 15, count 2 2006.197.07:40:08.99#ibcon#read 6, iclass 15, count 2 2006.197.07:40:08.99#ibcon#end of sib2, iclass 15, count 2 2006.197.07:40:08.99#ibcon#*mode == 0, iclass 15, count 2 2006.197.07:40:08.99#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.197.07:40:08.99#ibcon#[25=AT05-07\r\n] 2006.197.07:40:08.99#ibcon#*before write, iclass 15, count 2 2006.197.07:40:08.99#ibcon#enter sib2, iclass 15, count 2 2006.197.07:40:08.99#ibcon#flushed, iclass 15, count 2 2006.197.07:40:08.99#ibcon#about to write, iclass 15, count 2 2006.197.07:40:08.99#ibcon#wrote, iclass 15, count 2 2006.197.07:40:08.99#ibcon#about to read 3, iclass 15, count 2 2006.197.07:40:09.02#ibcon#read 3, iclass 15, count 2 2006.197.07:40:09.02#ibcon#about to read 4, iclass 15, count 2 2006.197.07:40:09.02#ibcon#read 4, iclass 15, count 2 2006.197.07:40:09.02#ibcon#about to read 5, iclass 15, count 2 2006.197.07:40:09.02#ibcon#read 5, iclass 15, count 2 2006.197.07:40:09.02#ibcon#about to read 6, iclass 15, count 2 2006.197.07:40:09.02#ibcon#read 6, iclass 15, count 2 2006.197.07:40:09.02#ibcon#end of sib2, iclass 15, count 2 2006.197.07:40:09.02#ibcon#*after write, iclass 15, count 2 2006.197.07:40:09.02#ibcon#*before return 0, iclass 15, count 2 2006.197.07:40:09.02#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.197.07:40:09.02#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.197.07:40:09.02#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.197.07:40:09.02#ibcon#ireg 7 cls_cnt 0 2006.197.07:40:09.02#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.197.07:40:09.14#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.197.07:40:09.14#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.197.07:40:09.14#ibcon#enter wrdev, iclass 15, count 0 2006.197.07:40:09.14#ibcon#first serial, iclass 15, count 0 2006.197.07:40:09.14#ibcon#enter sib2, iclass 15, count 0 2006.197.07:40:09.14#ibcon#flushed, iclass 15, count 0 2006.197.07:40:09.14#ibcon#about to write, iclass 15, count 0 2006.197.07:40:09.14#ibcon#wrote, iclass 15, count 0 2006.197.07:40:09.14#ibcon#about to read 3, iclass 15, count 0 2006.197.07:40:09.16#ibcon#read 3, iclass 15, count 0 2006.197.07:40:09.16#ibcon#about to read 4, iclass 15, count 0 2006.197.07:40:09.16#ibcon#read 4, iclass 15, count 0 2006.197.07:40:09.16#ibcon#about to read 5, iclass 15, count 0 2006.197.07:40:09.16#ibcon#read 5, iclass 15, count 0 2006.197.07:40:09.16#ibcon#about to read 6, iclass 15, count 0 2006.197.07:40:09.16#ibcon#read 6, iclass 15, count 0 2006.197.07:40:09.16#ibcon#end of sib2, iclass 15, count 0 2006.197.07:40:09.16#ibcon#*mode == 0, iclass 15, count 0 2006.197.07:40:09.16#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.197.07:40:09.16#ibcon#[25=USB\r\n] 2006.197.07:40:09.16#ibcon#*before write, iclass 15, count 0 2006.197.07:40:09.16#ibcon#enter sib2, iclass 15, count 0 2006.197.07:40:09.16#ibcon#flushed, iclass 15, count 0 2006.197.07:40:09.16#ibcon#about to write, iclass 15, count 0 2006.197.07:40:09.16#ibcon#wrote, iclass 15, count 0 2006.197.07:40:09.16#ibcon#about to read 3, iclass 15, count 0 2006.197.07:40:09.19#ibcon#read 3, iclass 15, count 0 2006.197.07:40:09.19#ibcon#about to read 4, iclass 15, count 0 2006.197.07:40:09.19#ibcon#read 4, iclass 15, count 0 2006.197.07:40:09.19#ibcon#about to read 5, iclass 15, count 0 2006.197.07:40:09.19#ibcon#read 5, iclass 15, count 0 2006.197.07:40:09.19#ibcon#about to read 6, iclass 15, count 0 2006.197.07:40:09.19#ibcon#read 6, iclass 15, count 0 2006.197.07:40:09.19#ibcon#end of sib2, iclass 15, count 0 2006.197.07:40:09.19#ibcon#*after write, iclass 15, count 0 2006.197.07:40:09.19#ibcon#*before return 0, iclass 15, count 0 2006.197.07:40:09.19#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.197.07:40:09.19#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.197.07:40:09.19#ibcon#about to clear, iclass 15 cls_cnt 0 2006.197.07:40:09.19#ibcon#cleared, iclass 15 cls_cnt 0 2006.197.07:40:09.19$vc4f8/valo=6,772.99 2006.197.07:40:09.19#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.197.07:40:09.19#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.197.07:40:09.19#ibcon#ireg 17 cls_cnt 0 2006.197.07:40:09.19#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.197.07:40:09.19#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.197.07:40:09.19#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.197.07:40:09.19#ibcon#enter wrdev, iclass 17, count 0 2006.197.07:40:09.19#ibcon#first serial, iclass 17, count 0 2006.197.07:40:09.19#ibcon#enter sib2, iclass 17, count 0 2006.197.07:40:09.19#ibcon#flushed, iclass 17, count 0 2006.197.07:40:09.19#ibcon#about to write, iclass 17, count 0 2006.197.07:40:09.19#ibcon#wrote, iclass 17, count 0 2006.197.07:40:09.19#ibcon#about to read 3, iclass 17, count 0 2006.197.07:40:09.21#ibcon#read 3, iclass 17, count 0 2006.197.07:40:09.21#ibcon#about to read 4, iclass 17, count 0 2006.197.07:40:09.21#ibcon#read 4, iclass 17, count 0 2006.197.07:40:09.21#ibcon#about to read 5, iclass 17, count 0 2006.197.07:40:09.21#ibcon#read 5, iclass 17, count 0 2006.197.07:40:09.21#ibcon#about to read 6, iclass 17, count 0 2006.197.07:40:09.21#ibcon#read 6, iclass 17, count 0 2006.197.07:40:09.21#ibcon#end of sib2, iclass 17, count 0 2006.197.07:40:09.21#ibcon#*mode == 0, iclass 17, count 0 2006.197.07:40:09.21#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.197.07:40:09.21#ibcon#[26=FRQ=06,772.99\r\n] 2006.197.07:40:09.21#ibcon#*before write, iclass 17, count 0 2006.197.07:40:09.21#ibcon#enter sib2, iclass 17, count 0 2006.197.07:40:09.21#ibcon#flushed, iclass 17, count 0 2006.197.07:40:09.21#ibcon#about to write, iclass 17, count 0 2006.197.07:40:09.21#ibcon#wrote, iclass 17, count 0 2006.197.07:40:09.21#ibcon#about to read 3, iclass 17, count 0 2006.197.07:40:09.25#ibcon#read 3, iclass 17, count 0 2006.197.07:40:09.25#ibcon#about to read 4, iclass 17, count 0 2006.197.07:40:09.25#ibcon#read 4, iclass 17, count 0 2006.197.07:40:09.25#ibcon#about to read 5, iclass 17, count 0 2006.197.07:40:09.25#ibcon#read 5, iclass 17, count 0 2006.197.07:40:09.25#ibcon#about to read 6, iclass 17, count 0 2006.197.07:40:09.25#ibcon#read 6, iclass 17, count 0 2006.197.07:40:09.25#ibcon#end of sib2, iclass 17, count 0 2006.197.07:40:09.25#ibcon#*after write, iclass 17, count 0 2006.197.07:40:09.25#ibcon#*before return 0, iclass 17, count 0 2006.197.07:40:09.25#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.197.07:40:09.25#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.197.07:40:09.25#ibcon#about to clear, iclass 17 cls_cnt 0 2006.197.07:40:09.25#ibcon#cleared, iclass 17 cls_cnt 0 2006.197.07:40:09.25$vc4f8/va=6,6 2006.197.07:40:09.25#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.197.07:40:09.25#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.197.07:40:09.25#ibcon#ireg 11 cls_cnt 2 2006.197.07:40:09.25#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.197.07:40:09.31#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.197.07:40:09.31#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.197.07:40:09.31#ibcon#enter wrdev, iclass 19, count 2 2006.197.07:40:09.31#ibcon#first serial, iclass 19, count 2 2006.197.07:40:09.31#ibcon#enter sib2, iclass 19, count 2 2006.197.07:40:09.31#ibcon#flushed, iclass 19, count 2 2006.197.07:40:09.31#ibcon#about to write, iclass 19, count 2 2006.197.07:40:09.31#ibcon#wrote, iclass 19, count 2 2006.197.07:40:09.31#ibcon#about to read 3, iclass 19, count 2 2006.197.07:40:09.33#ibcon#read 3, iclass 19, count 2 2006.197.07:40:09.33#ibcon#about to read 4, iclass 19, count 2 2006.197.07:40:09.33#ibcon#read 4, iclass 19, count 2 2006.197.07:40:09.33#ibcon#about to read 5, iclass 19, count 2 2006.197.07:40:09.33#ibcon#read 5, iclass 19, count 2 2006.197.07:40:09.33#ibcon#about to read 6, iclass 19, count 2 2006.197.07:40:09.33#ibcon#read 6, iclass 19, count 2 2006.197.07:40:09.33#ibcon#end of sib2, iclass 19, count 2 2006.197.07:40:09.33#ibcon#*mode == 0, iclass 19, count 2 2006.197.07:40:09.33#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.197.07:40:09.33#ibcon#[25=AT06-06\r\n] 2006.197.07:40:09.33#ibcon#*before write, iclass 19, count 2 2006.197.07:40:09.33#ibcon#enter sib2, iclass 19, count 2 2006.197.07:40:09.33#ibcon#flushed, iclass 19, count 2 2006.197.07:40:09.33#ibcon#about to write, iclass 19, count 2 2006.197.07:40:09.33#ibcon#wrote, iclass 19, count 2 2006.197.07:40:09.33#ibcon#about to read 3, iclass 19, count 2 2006.197.07:40:09.36#ibcon#read 3, iclass 19, count 2 2006.197.07:40:09.36#ibcon#about to read 4, iclass 19, count 2 2006.197.07:40:09.36#ibcon#read 4, iclass 19, count 2 2006.197.07:40:09.36#ibcon#about to read 5, iclass 19, count 2 2006.197.07:40:09.36#ibcon#read 5, iclass 19, count 2 2006.197.07:40:09.36#ibcon#about to read 6, iclass 19, count 2 2006.197.07:40:09.36#ibcon#read 6, iclass 19, count 2 2006.197.07:40:09.36#ibcon#end of sib2, iclass 19, count 2 2006.197.07:40:09.36#ibcon#*after write, iclass 19, count 2 2006.197.07:40:09.36#ibcon#*before return 0, iclass 19, count 2 2006.197.07:40:09.36#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.197.07:40:09.36#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.197.07:40:09.36#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.197.07:40:09.36#ibcon#ireg 7 cls_cnt 0 2006.197.07:40:09.36#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.197.07:40:09.48#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.197.07:40:09.48#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.197.07:40:09.48#ibcon#enter wrdev, iclass 19, count 0 2006.197.07:40:09.48#ibcon#first serial, iclass 19, count 0 2006.197.07:40:09.48#ibcon#enter sib2, iclass 19, count 0 2006.197.07:40:09.48#ibcon#flushed, iclass 19, count 0 2006.197.07:40:09.48#ibcon#about to write, iclass 19, count 0 2006.197.07:40:09.48#ibcon#wrote, iclass 19, count 0 2006.197.07:40:09.48#ibcon#about to read 3, iclass 19, count 0 2006.197.07:40:09.50#ibcon#read 3, iclass 19, count 0 2006.197.07:40:09.50#ibcon#about to read 4, iclass 19, count 0 2006.197.07:40:09.50#ibcon#read 4, iclass 19, count 0 2006.197.07:40:09.50#ibcon#about to read 5, iclass 19, count 0 2006.197.07:40:09.50#ibcon#read 5, iclass 19, count 0 2006.197.07:40:09.50#ibcon#about to read 6, iclass 19, count 0 2006.197.07:40:09.50#ibcon#read 6, iclass 19, count 0 2006.197.07:40:09.50#ibcon#end of sib2, iclass 19, count 0 2006.197.07:40:09.50#ibcon#*mode == 0, iclass 19, count 0 2006.197.07:40:09.50#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.197.07:40:09.50#ibcon#[25=USB\r\n] 2006.197.07:40:09.50#ibcon#*before write, iclass 19, count 0 2006.197.07:40:09.50#ibcon#enter sib2, iclass 19, count 0 2006.197.07:40:09.50#ibcon#flushed, iclass 19, count 0 2006.197.07:40:09.50#ibcon#about to write, iclass 19, count 0 2006.197.07:40:09.50#ibcon#wrote, iclass 19, count 0 2006.197.07:40:09.50#ibcon#about to read 3, iclass 19, count 0 2006.197.07:40:09.53#ibcon#read 3, iclass 19, count 0 2006.197.07:40:09.53#ibcon#about to read 4, iclass 19, count 0 2006.197.07:40:09.53#ibcon#read 4, iclass 19, count 0 2006.197.07:40:09.53#ibcon#about to read 5, iclass 19, count 0 2006.197.07:40:09.53#ibcon#read 5, iclass 19, count 0 2006.197.07:40:09.53#ibcon#about to read 6, iclass 19, count 0 2006.197.07:40:09.53#ibcon#read 6, iclass 19, count 0 2006.197.07:40:09.53#ibcon#end of sib2, iclass 19, count 0 2006.197.07:40:09.53#ibcon#*after write, iclass 19, count 0 2006.197.07:40:09.53#ibcon#*before return 0, iclass 19, count 0 2006.197.07:40:09.53#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.197.07:40:09.53#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.197.07:40:09.53#ibcon#about to clear, iclass 19 cls_cnt 0 2006.197.07:40:09.53#ibcon#cleared, iclass 19 cls_cnt 0 2006.197.07:40:09.53$vc4f8/valo=7,832.99 2006.197.07:40:09.53#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.197.07:40:09.53#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.197.07:40:09.53#ibcon#ireg 17 cls_cnt 0 2006.197.07:40:09.53#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.197.07:40:09.53#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.197.07:40:09.53#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.197.07:40:09.53#ibcon#enter wrdev, iclass 21, count 0 2006.197.07:40:09.53#ibcon#first serial, iclass 21, count 0 2006.197.07:40:09.53#ibcon#enter sib2, iclass 21, count 0 2006.197.07:40:09.53#ibcon#flushed, iclass 21, count 0 2006.197.07:40:09.53#ibcon#about to write, iclass 21, count 0 2006.197.07:40:09.53#ibcon#wrote, iclass 21, count 0 2006.197.07:40:09.53#ibcon#about to read 3, iclass 21, count 0 2006.197.07:40:09.55#ibcon#read 3, iclass 21, count 0 2006.197.07:40:09.55#ibcon#about to read 4, iclass 21, count 0 2006.197.07:40:09.55#ibcon#read 4, iclass 21, count 0 2006.197.07:40:09.55#ibcon#about to read 5, iclass 21, count 0 2006.197.07:40:09.55#ibcon#read 5, iclass 21, count 0 2006.197.07:40:09.55#ibcon#about to read 6, iclass 21, count 0 2006.197.07:40:09.55#ibcon#read 6, iclass 21, count 0 2006.197.07:40:09.55#ibcon#end of sib2, iclass 21, count 0 2006.197.07:40:09.55#ibcon#*mode == 0, iclass 21, count 0 2006.197.07:40:09.55#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.197.07:40:09.55#ibcon#[26=FRQ=07,832.99\r\n] 2006.197.07:40:09.55#ibcon#*before write, iclass 21, count 0 2006.197.07:40:09.55#ibcon#enter sib2, iclass 21, count 0 2006.197.07:40:09.55#ibcon#flushed, iclass 21, count 0 2006.197.07:40:09.55#ibcon#about to write, iclass 21, count 0 2006.197.07:40:09.55#ibcon#wrote, iclass 21, count 0 2006.197.07:40:09.55#ibcon#about to read 3, iclass 21, count 0 2006.197.07:40:09.59#ibcon#read 3, iclass 21, count 0 2006.197.07:40:09.59#ibcon#about to read 4, iclass 21, count 0 2006.197.07:40:09.59#ibcon#read 4, iclass 21, count 0 2006.197.07:40:09.59#ibcon#about to read 5, iclass 21, count 0 2006.197.07:40:09.59#ibcon#read 5, iclass 21, count 0 2006.197.07:40:09.59#ibcon#about to read 6, iclass 21, count 0 2006.197.07:40:09.59#ibcon#read 6, iclass 21, count 0 2006.197.07:40:09.59#ibcon#end of sib2, iclass 21, count 0 2006.197.07:40:09.59#ibcon#*after write, iclass 21, count 0 2006.197.07:40:09.59#ibcon#*before return 0, iclass 21, count 0 2006.197.07:40:09.59#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.197.07:40:09.59#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.197.07:40:09.59#ibcon#about to clear, iclass 21 cls_cnt 0 2006.197.07:40:09.59#ibcon#cleared, iclass 21 cls_cnt 0 2006.197.07:40:09.59$vc4f8/va=7,6 2006.197.07:40:09.59#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.197.07:40:09.59#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.197.07:40:09.59#ibcon#ireg 11 cls_cnt 2 2006.197.07:40:09.59#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.197.07:40:09.65#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.197.07:40:09.65#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.197.07:40:09.65#ibcon#enter wrdev, iclass 23, count 2 2006.197.07:40:09.65#ibcon#first serial, iclass 23, count 2 2006.197.07:40:09.65#ibcon#enter sib2, iclass 23, count 2 2006.197.07:40:09.65#ibcon#flushed, iclass 23, count 2 2006.197.07:40:09.65#ibcon#about to write, iclass 23, count 2 2006.197.07:40:09.65#ibcon#wrote, iclass 23, count 2 2006.197.07:40:09.65#ibcon#about to read 3, iclass 23, count 2 2006.197.07:40:09.67#ibcon#read 3, iclass 23, count 2 2006.197.07:40:09.67#ibcon#about to read 4, iclass 23, count 2 2006.197.07:40:09.67#ibcon#read 4, iclass 23, count 2 2006.197.07:40:09.67#ibcon#about to read 5, iclass 23, count 2 2006.197.07:40:09.67#ibcon#read 5, iclass 23, count 2 2006.197.07:40:09.67#ibcon#about to read 6, iclass 23, count 2 2006.197.07:40:09.67#ibcon#read 6, iclass 23, count 2 2006.197.07:40:09.67#ibcon#end of sib2, iclass 23, count 2 2006.197.07:40:09.67#ibcon#*mode == 0, iclass 23, count 2 2006.197.07:40:09.67#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.197.07:40:09.67#ibcon#[25=AT07-06\r\n] 2006.197.07:40:09.67#ibcon#*before write, iclass 23, count 2 2006.197.07:40:09.67#ibcon#enter sib2, iclass 23, count 2 2006.197.07:40:09.67#ibcon#flushed, iclass 23, count 2 2006.197.07:40:09.67#ibcon#about to write, iclass 23, count 2 2006.197.07:40:09.67#ibcon#wrote, iclass 23, count 2 2006.197.07:40:09.67#ibcon#about to read 3, iclass 23, count 2 2006.197.07:40:09.70#ibcon#read 3, iclass 23, count 2 2006.197.07:40:09.70#ibcon#about to read 4, iclass 23, count 2 2006.197.07:40:09.70#ibcon#read 4, iclass 23, count 2 2006.197.07:40:09.70#ibcon#about to read 5, iclass 23, count 2 2006.197.07:40:09.70#ibcon#read 5, iclass 23, count 2 2006.197.07:40:09.70#ibcon#about to read 6, iclass 23, count 2 2006.197.07:40:09.70#ibcon#read 6, iclass 23, count 2 2006.197.07:40:09.70#ibcon#end of sib2, iclass 23, count 2 2006.197.07:40:09.70#ibcon#*after write, iclass 23, count 2 2006.197.07:40:09.70#ibcon#*before return 0, iclass 23, count 2 2006.197.07:40:09.70#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.197.07:40:09.70#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.197.07:40:09.70#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.197.07:40:09.70#ibcon#ireg 7 cls_cnt 0 2006.197.07:40:09.70#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.197.07:40:09.82#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.197.07:40:09.82#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.197.07:40:09.82#ibcon#enter wrdev, iclass 23, count 0 2006.197.07:40:09.82#ibcon#first serial, iclass 23, count 0 2006.197.07:40:09.82#ibcon#enter sib2, iclass 23, count 0 2006.197.07:40:09.82#ibcon#flushed, iclass 23, count 0 2006.197.07:40:09.82#ibcon#about to write, iclass 23, count 0 2006.197.07:40:09.82#ibcon#wrote, iclass 23, count 0 2006.197.07:40:09.82#ibcon#about to read 3, iclass 23, count 0 2006.197.07:40:09.84#ibcon#read 3, iclass 23, count 0 2006.197.07:40:09.84#ibcon#about to read 4, iclass 23, count 0 2006.197.07:40:09.84#ibcon#read 4, iclass 23, count 0 2006.197.07:40:09.84#ibcon#about to read 5, iclass 23, count 0 2006.197.07:40:09.84#ibcon#read 5, iclass 23, count 0 2006.197.07:40:09.84#ibcon#about to read 6, iclass 23, count 0 2006.197.07:40:09.84#ibcon#read 6, iclass 23, count 0 2006.197.07:40:09.84#ibcon#end of sib2, iclass 23, count 0 2006.197.07:40:09.84#ibcon#*mode == 0, iclass 23, count 0 2006.197.07:40:09.84#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.197.07:40:09.84#ibcon#[25=USB\r\n] 2006.197.07:40:09.84#ibcon#*before write, iclass 23, count 0 2006.197.07:40:09.84#ibcon#enter sib2, iclass 23, count 0 2006.197.07:40:09.84#ibcon#flushed, iclass 23, count 0 2006.197.07:40:09.84#ibcon#about to write, iclass 23, count 0 2006.197.07:40:09.84#ibcon#wrote, iclass 23, count 0 2006.197.07:40:09.84#ibcon#about to read 3, iclass 23, count 0 2006.197.07:40:09.87#ibcon#read 3, iclass 23, count 0 2006.197.07:40:09.87#ibcon#about to read 4, iclass 23, count 0 2006.197.07:40:09.87#ibcon#read 4, iclass 23, count 0 2006.197.07:40:09.87#ibcon#about to read 5, iclass 23, count 0 2006.197.07:40:09.87#ibcon#read 5, iclass 23, count 0 2006.197.07:40:09.87#ibcon#about to read 6, iclass 23, count 0 2006.197.07:40:09.87#ibcon#read 6, iclass 23, count 0 2006.197.07:40:09.87#ibcon#end of sib2, iclass 23, count 0 2006.197.07:40:09.87#ibcon#*after write, iclass 23, count 0 2006.197.07:40:09.87#ibcon#*before return 0, iclass 23, count 0 2006.197.07:40:09.87#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.197.07:40:09.87#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.197.07:40:09.87#ibcon#about to clear, iclass 23 cls_cnt 0 2006.197.07:40:09.87#ibcon#cleared, iclass 23 cls_cnt 0 2006.197.07:40:09.87$vc4f8/valo=8,852.99 2006.197.07:40:09.87#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.197.07:40:09.87#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.197.07:40:09.87#ibcon#ireg 17 cls_cnt 0 2006.197.07:40:09.87#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.197.07:40:09.87#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.197.07:40:09.87#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.197.07:40:09.87#ibcon#enter wrdev, iclass 25, count 0 2006.197.07:40:09.87#ibcon#first serial, iclass 25, count 0 2006.197.07:40:09.87#ibcon#enter sib2, iclass 25, count 0 2006.197.07:40:09.87#ibcon#flushed, iclass 25, count 0 2006.197.07:40:09.87#ibcon#about to write, iclass 25, count 0 2006.197.07:40:09.87#ibcon#wrote, iclass 25, count 0 2006.197.07:40:09.87#ibcon#about to read 3, iclass 25, count 0 2006.197.07:40:09.89#ibcon#read 3, iclass 25, count 0 2006.197.07:40:09.89#ibcon#about to read 4, iclass 25, count 0 2006.197.07:40:09.89#ibcon#read 4, iclass 25, count 0 2006.197.07:40:09.89#ibcon#about to read 5, iclass 25, count 0 2006.197.07:40:09.89#ibcon#read 5, iclass 25, count 0 2006.197.07:40:09.89#ibcon#about to read 6, iclass 25, count 0 2006.197.07:40:09.89#ibcon#read 6, iclass 25, count 0 2006.197.07:40:09.89#ibcon#end of sib2, iclass 25, count 0 2006.197.07:40:09.89#ibcon#*mode == 0, iclass 25, count 0 2006.197.07:40:09.89#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.197.07:40:09.89#ibcon#[26=FRQ=08,852.99\r\n] 2006.197.07:40:09.89#ibcon#*before write, iclass 25, count 0 2006.197.07:40:09.89#ibcon#enter sib2, iclass 25, count 0 2006.197.07:40:09.89#ibcon#flushed, iclass 25, count 0 2006.197.07:40:09.89#ibcon#about to write, iclass 25, count 0 2006.197.07:40:09.89#ibcon#wrote, iclass 25, count 0 2006.197.07:40:09.89#ibcon#about to read 3, iclass 25, count 0 2006.197.07:40:09.93#ibcon#read 3, iclass 25, count 0 2006.197.07:40:09.93#ibcon#about to read 4, iclass 25, count 0 2006.197.07:40:09.93#ibcon#read 4, iclass 25, count 0 2006.197.07:40:09.93#ibcon#about to read 5, iclass 25, count 0 2006.197.07:40:09.93#ibcon#read 5, iclass 25, count 0 2006.197.07:40:09.93#ibcon#about to read 6, iclass 25, count 0 2006.197.07:40:09.93#ibcon#read 6, iclass 25, count 0 2006.197.07:40:09.93#ibcon#end of sib2, iclass 25, count 0 2006.197.07:40:09.93#ibcon#*after write, iclass 25, count 0 2006.197.07:40:09.93#ibcon#*before return 0, iclass 25, count 0 2006.197.07:40:09.93#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.197.07:40:09.93#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.197.07:40:09.93#ibcon#about to clear, iclass 25 cls_cnt 0 2006.197.07:40:09.93#ibcon#cleared, iclass 25 cls_cnt 0 2006.197.07:40:09.93$vc4f8/va=8,7 2006.197.07:40:09.93#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.197.07:40:09.93#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.197.07:40:09.93#ibcon#ireg 11 cls_cnt 2 2006.197.07:40:09.93#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.197.07:40:09.99#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.197.07:40:09.99#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.197.07:40:09.99#ibcon#enter wrdev, iclass 27, count 2 2006.197.07:40:09.99#ibcon#first serial, iclass 27, count 2 2006.197.07:40:09.99#ibcon#enter sib2, iclass 27, count 2 2006.197.07:40:09.99#ibcon#flushed, iclass 27, count 2 2006.197.07:40:09.99#ibcon#about to write, iclass 27, count 2 2006.197.07:40:09.99#ibcon#wrote, iclass 27, count 2 2006.197.07:40:09.99#ibcon#about to read 3, iclass 27, count 2 2006.197.07:40:10.01#ibcon#read 3, iclass 27, count 2 2006.197.07:40:10.01#ibcon#about to read 4, iclass 27, count 2 2006.197.07:40:10.01#ibcon#read 4, iclass 27, count 2 2006.197.07:40:10.01#ibcon#about to read 5, iclass 27, count 2 2006.197.07:40:10.01#ibcon#read 5, iclass 27, count 2 2006.197.07:40:10.01#ibcon#about to read 6, iclass 27, count 2 2006.197.07:40:10.01#ibcon#read 6, iclass 27, count 2 2006.197.07:40:10.01#ibcon#end of sib2, iclass 27, count 2 2006.197.07:40:10.01#ibcon#*mode == 0, iclass 27, count 2 2006.197.07:40:10.01#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.197.07:40:10.01#ibcon#[25=AT08-07\r\n] 2006.197.07:40:10.01#ibcon#*before write, iclass 27, count 2 2006.197.07:40:10.01#ibcon#enter sib2, iclass 27, count 2 2006.197.07:40:10.01#ibcon#flushed, iclass 27, count 2 2006.197.07:40:10.01#ibcon#about to write, iclass 27, count 2 2006.197.07:40:10.01#ibcon#wrote, iclass 27, count 2 2006.197.07:40:10.01#ibcon#about to read 3, iclass 27, count 2 2006.197.07:40:10.04#ibcon#read 3, iclass 27, count 2 2006.197.07:40:10.04#ibcon#about to read 4, iclass 27, count 2 2006.197.07:40:10.04#ibcon#read 4, iclass 27, count 2 2006.197.07:40:10.04#ibcon#about to read 5, iclass 27, count 2 2006.197.07:40:10.04#ibcon#read 5, iclass 27, count 2 2006.197.07:40:10.04#ibcon#about to read 6, iclass 27, count 2 2006.197.07:40:10.04#ibcon#read 6, iclass 27, count 2 2006.197.07:40:10.04#ibcon#end of sib2, iclass 27, count 2 2006.197.07:40:10.04#ibcon#*after write, iclass 27, count 2 2006.197.07:40:10.04#ibcon#*before return 0, iclass 27, count 2 2006.197.07:40:10.04#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.197.07:40:10.04#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.197.07:40:10.04#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.197.07:40:10.04#ibcon#ireg 7 cls_cnt 0 2006.197.07:40:10.04#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.197.07:40:10.16#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.197.07:40:10.16#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.197.07:40:10.16#ibcon#enter wrdev, iclass 27, count 0 2006.197.07:40:10.16#ibcon#first serial, iclass 27, count 0 2006.197.07:40:10.16#ibcon#enter sib2, iclass 27, count 0 2006.197.07:40:10.16#ibcon#flushed, iclass 27, count 0 2006.197.07:40:10.16#ibcon#about to write, iclass 27, count 0 2006.197.07:40:10.16#ibcon#wrote, iclass 27, count 0 2006.197.07:40:10.16#ibcon#about to read 3, iclass 27, count 0 2006.197.07:40:10.18#ibcon#read 3, iclass 27, count 0 2006.197.07:40:10.18#ibcon#about to read 4, iclass 27, count 0 2006.197.07:40:10.18#ibcon#read 4, iclass 27, count 0 2006.197.07:40:10.18#ibcon#about to read 5, iclass 27, count 0 2006.197.07:40:10.18#ibcon#read 5, iclass 27, count 0 2006.197.07:40:10.18#ibcon#about to read 6, iclass 27, count 0 2006.197.07:40:10.18#ibcon#read 6, iclass 27, count 0 2006.197.07:40:10.18#ibcon#end of sib2, iclass 27, count 0 2006.197.07:40:10.18#ibcon#*mode == 0, iclass 27, count 0 2006.197.07:40:10.18#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.197.07:40:10.18#ibcon#[25=USB\r\n] 2006.197.07:40:10.18#ibcon#*before write, iclass 27, count 0 2006.197.07:40:10.18#ibcon#enter sib2, iclass 27, count 0 2006.197.07:40:10.18#ibcon#flushed, iclass 27, count 0 2006.197.07:40:10.18#ibcon#about to write, iclass 27, count 0 2006.197.07:40:10.18#ibcon#wrote, iclass 27, count 0 2006.197.07:40:10.18#ibcon#about to read 3, iclass 27, count 0 2006.197.07:40:10.21#ibcon#read 3, iclass 27, count 0 2006.197.07:40:10.21#ibcon#about to read 4, iclass 27, count 0 2006.197.07:40:10.21#ibcon#read 4, iclass 27, count 0 2006.197.07:40:10.21#ibcon#about to read 5, iclass 27, count 0 2006.197.07:40:10.21#ibcon#read 5, iclass 27, count 0 2006.197.07:40:10.21#ibcon#about to read 6, iclass 27, count 0 2006.197.07:40:10.21#ibcon#read 6, iclass 27, count 0 2006.197.07:40:10.21#ibcon#end of sib2, iclass 27, count 0 2006.197.07:40:10.21#ibcon#*after write, iclass 27, count 0 2006.197.07:40:10.21#ibcon#*before return 0, iclass 27, count 0 2006.197.07:40:10.21#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.197.07:40:10.21#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.197.07:40:10.21#ibcon#about to clear, iclass 27 cls_cnt 0 2006.197.07:40:10.21#ibcon#cleared, iclass 27 cls_cnt 0 2006.197.07:40:10.21$vc4f8/vblo=1,632.99 2006.197.07:40:10.21#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.197.07:40:10.21#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.197.07:40:10.21#ibcon#ireg 17 cls_cnt 0 2006.197.07:40:10.21#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.197.07:40:10.21#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.197.07:40:10.21#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.197.07:40:10.21#ibcon#enter wrdev, iclass 29, count 0 2006.197.07:40:10.21#ibcon#first serial, iclass 29, count 0 2006.197.07:40:10.21#ibcon#enter sib2, iclass 29, count 0 2006.197.07:40:10.21#ibcon#flushed, iclass 29, count 0 2006.197.07:40:10.21#ibcon#about to write, iclass 29, count 0 2006.197.07:40:10.21#ibcon#wrote, iclass 29, count 0 2006.197.07:40:10.21#ibcon#about to read 3, iclass 29, count 0 2006.197.07:40:10.23#ibcon#read 3, iclass 29, count 0 2006.197.07:40:10.23#ibcon#about to read 4, iclass 29, count 0 2006.197.07:40:10.23#ibcon#read 4, iclass 29, count 0 2006.197.07:40:10.23#ibcon#about to read 5, iclass 29, count 0 2006.197.07:40:10.23#ibcon#read 5, iclass 29, count 0 2006.197.07:40:10.23#ibcon#about to read 6, iclass 29, count 0 2006.197.07:40:10.23#ibcon#read 6, iclass 29, count 0 2006.197.07:40:10.23#ibcon#end of sib2, iclass 29, count 0 2006.197.07:40:10.23#ibcon#*mode == 0, iclass 29, count 0 2006.197.07:40:10.23#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.197.07:40:10.23#ibcon#[28=FRQ=01,632.99\r\n] 2006.197.07:40:10.23#ibcon#*before write, iclass 29, count 0 2006.197.07:40:10.23#ibcon#enter sib2, iclass 29, count 0 2006.197.07:40:10.23#ibcon#flushed, iclass 29, count 0 2006.197.07:40:10.23#ibcon#about to write, iclass 29, count 0 2006.197.07:40:10.23#ibcon#wrote, iclass 29, count 0 2006.197.07:40:10.23#ibcon#about to read 3, iclass 29, count 0 2006.197.07:40:10.27#ibcon#read 3, iclass 29, count 0 2006.197.07:40:10.27#ibcon#about to read 4, iclass 29, count 0 2006.197.07:40:10.27#ibcon#read 4, iclass 29, count 0 2006.197.07:40:10.27#ibcon#about to read 5, iclass 29, count 0 2006.197.07:40:10.27#ibcon#read 5, iclass 29, count 0 2006.197.07:40:10.27#ibcon#about to read 6, iclass 29, count 0 2006.197.07:40:10.27#ibcon#read 6, iclass 29, count 0 2006.197.07:40:10.27#ibcon#end of sib2, iclass 29, count 0 2006.197.07:40:10.27#ibcon#*after write, iclass 29, count 0 2006.197.07:40:10.27#ibcon#*before return 0, iclass 29, count 0 2006.197.07:40:10.27#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.197.07:40:10.27#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.197.07:40:10.27#ibcon#about to clear, iclass 29 cls_cnt 0 2006.197.07:40:10.27#ibcon#cleared, iclass 29 cls_cnt 0 2006.197.07:40:10.27$vc4f8/vb=1,4 2006.197.07:40:10.27#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.197.07:40:10.27#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.197.07:40:10.27#ibcon#ireg 11 cls_cnt 2 2006.197.07:40:10.27#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.197.07:40:10.27#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.197.07:40:10.27#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.197.07:40:10.27#ibcon#enter wrdev, iclass 31, count 2 2006.197.07:40:10.27#ibcon#first serial, iclass 31, count 2 2006.197.07:40:10.27#ibcon#enter sib2, iclass 31, count 2 2006.197.07:40:10.27#ibcon#flushed, iclass 31, count 2 2006.197.07:40:10.27#ibcon#about to write, iclass 31, count 2 2006.197.07:40:10.27#ibcon#wrote, iclass 31, count 2 2006.197.07:40:10.27#ibcon#about to read 3, iclass 31, count 2 2006.197.07:40:10.29#ibcon#read 3, iclass 31, count 2 2006.197.07:40:10.29#ibcon#about to read 4, iclass 31, count 2 2006.197.07:40:10.29#ibcon#read 4, iclass 31, count 2 2006.197.07:40:10.29#ibcon#about to read 5, iclass 31, count 2 2006.197.07:40:10.29#ibcon#read 5, iclass 31, count 2 2006.197.07:40:10.29#ibcon#about to read 6, iclass 31, count 2 2006.197.07:40:10.29#ibcon#read 6, iclass 31, count 2 2006.197.07:40:10.29#ibcon#end of sib2, iclass 31, count 2 2006.197.07:40:10.29#ibcon#*mode == 0, iclass 31, count 2 2006.197.07:40:10.29#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.197.07:40:10.29#ibcon#[27=AT01-04\r\n] 2006.197.07:40:10.29#ibcon#*before write, iclass 31, count 2 2006.197.07:40:10.29#ibcon#enter sib2, iclass 31, count 2 2006.197.07:40:10.29#ibcon#flushed, iclass 31, count 2 2006.197.07:40:10.29#ibcon#about to write, iclass 31, count 2 2006.197.07:40:10.29#ibcon#wrote, iclass 31, count 2 2006.197.07:40:10.29#ibcon#about to read 3, iclass 31, count 2 2006.197.07:40:10.32#ibcon#read 3, iclass 31, count 2 2006.197.07:40:10.32#ibcon#about to read 4, iclass 31, count 2 2006.197.07:40:10.32#ibcon#read 4, iclass 31, count 2 2006.197.07:40:10.32#ibcon#about to read 5, iclass 31, count 2 2006.197.07:40:10.32#ibcon#read 5, iclass 31, count 2 2006.197.07:40:10.32#ibcon#about to read 6, iclass 31, count 2 2006.197.07:40:10.32#ibcon#read 6, iclass 31, count 2 2006.197.07:40:10.32#ibcon#end of sib2, iclass 31, count 2 2006.197.07:40:10.32#ibcon#*after write, iclass 31, count 2 2006.197.07:40:10.32#ibcon#*before return 0, iclass 31, count 2 2006.197.07:40:10.32#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.197.07:40:10.32#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.197.07:40:10.32#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.197.07:40:10.32#ibcon#ireg 7 cls_cnt 0 2006.197.07:40:10.32#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.197.07:40:10.44#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.197.07:40:10.44#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.197.07:40:10.44#ibcon#enter wrdev, iclass 31, count 0 2006.197.07:40:10.44#ibcon#first serial, iclass 31, count 0 2006.197.07:40:10.44#ibcon#enter sib2, iclass 31, count 0 2006.197.07:40:10.44#ibcon#flushed, iclass 31, count 0 2006.197.07:40:10.44#ibcon#about to write, iclass 31, count 0 2006.197.07:40:10.44#ibcon#wrote, iclass 31, count 0 2006.197.07:40:10.44#ibcon#about to read 3, iclass 31, count 0 2006.197.07:40:10.46#ibcon#read 3, iclass 31, count 0 2006.197.07:40:10.46#ibcon#about to read 4, iclass 31, count 0 2006.197.07:40:10.46#ibcon#read 4, iclass 31, count 0 2006.197.07:40:10.46#ibcon#about to read 5, iclass 31, count 0 2006.197.07:40:10.46#ibcon#read 5, iclass 31, count 0 2006.197.07:40:10.46#ibcon#about to read 6, iclass 31, count 0 2006.197.07:40:10.46#ibcon#read 6, iclass 31, count 0 2006.197.07:40:10.46#ibcon#end of sib2, iclass 31, count 0 2006.197.07:40:10.46#ibcon#*mode == 0, iclass 31, count 0 2006.197.07:40:10.46#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.197.07:40:10.46#ibcon#[27=USB\r\n] 2006.197.07:40:10.46#ibcon#*before write, iclass 31, count 0 2006.197.07:40:10.46#ibcon#enter sib2, iclass 31, count 0 2006.197.07:40:10.46#ibcon#flushed, iclass 31, count 0 2006.197.07:40:10.46#ibcon#about to write, iclass 31, count 0 2006.197.07:40:10.46#ibcon#wrote, iclass 31, count 0 2006.197.07:40:10.46#ibcon#about to read 3, iclass 31, count 0 2006.197.07:40:10.49#ibcon#read 3, iclass 31, count 0 2006.197.07:40:10.49#ibcon#about to read 4, iclass 31, count 0 2006.197.07:40:10.49#ibcon#read 4, iclass 31, count 0 2006.197.07:40:10.49#ibcon#about to read 5, iclass 31, count 0 2006.197.07:40:10.49#ibcon#read 5, iclass 31, count 0 2006.197.07:40:10.49#ibcon#about to read 6, iclass 31, count 0 2006.197.07:40:10.49#ibcon#read 6, iclass 31, count 0 2006.197.07:40:10.49#ibcon#end of sib2, iclass 31, count 0 2006.197.07:40:10.49#ibcon#*after write, iclass 31, count 0 2006.197.07:40:10.49#ibcon#*before return 0, iclass 31, count 0 2006.197.07:40:10.49#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.197.07:40:10.49#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.197.07:40:10.49#ibcon#about to clear, iclass 31 cls_cnt 0 2006.197.07:40:10.49#ibcon#cleared, iclass 31 cls_cnt 0 2006.197.07:40:10.49$vc4f8/vblo=2,640.99 2006.197.07:40:10.49#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.197.07:40:10.49#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.197.07:40:10.49#ibcon#ireg 17 cls_cnt 0 2006.197.07:40:10.49#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.197.07:40:10.49#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.197.07:40:10.49#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.197.07:40:10.49#ibcon#enter wrdev, iclass 33, count 0 2006.197.07:40:10.49#ibcon#first serial, iclass 33, count 0 2006.197.07:40:10.49#ibcon#enter sib2, iclass 33, count 0 2006.197.07:40:10.49#ibcon#flushed, iclass 33, count 0 2006.197.07:40:10.49#ibcon#about to write, iclass 33, count 0 2006.197.07:40:10.49#ibcon#wrote, iclass 33, count 0 2006.197.07:40:10.49#ibcon#about to read 3, iclass 33, count 0 2006.197.07:40:10.51#ibcon#read 3, iclass 33, count 0 2006.197.07:40:10.51#ibcon#about to read 4, iclass 33, count 0 2006.197.07:40:10.51#ibcon#read 4, iclass 33, count 0 2006.197.07:40:10.51#ibcon#about to read 5, iclass 33, count 0 2006.197.07:40:10.51#ibcon#read 5, iclass 33, count 0 2006.197.07:40:10.51#ibcon#about to read 6, iclass 33, count 0 2006.197.07:40:10.51#ibcon#read 6, iclass 33, count 0 2006.197.07:40:10.51#ibcon#end of sib2, iclass 33, count 0 2006.197.07:40:10.51#ibcon#*mode == 0, iclass 33, count 0 2006.197.07:40:10.51#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.197.07:40:10.51#ibcon#[28=FRQ=02,640.99\r\n] 2006.197.07:40:10.51#ibcon#*before write, iclass 33, count 0 2006.197.07:40:10.51#ibcon#enter sib2, iclass 33, count 0 2006.197.07:40:10.51#ibcon#flushed, iclass 33, count 0 2006.197.07:40:10.51#ibcon#about to write, iclass 33, count 0 2006.197.07:40:10.51#ibcon#wrote, iclass 33, count 0 2006.197.07:40:10.51#ibcon#about to read 3, iclass 33, count 0 2006.197.07:40:10.55#ibcon#read 3, iclass 33, count 0 2006.197.07:40:10.55#ibcon#about to read 4, iclass 33, count 0 2006.197.07:40:10.55#ibcon#read 4, iclass 33, count 0 2006.197.07:40:10.55#ibcon#about to read 5, iclass 33, count 0 2006.197.07:40:10.55#ibcon#read 5, iclass 33, count 0 2006.197.07:40:10.55#ibcon#about to read 6, iclass 33, count 0 2006.197.07:40:10.55#ibcon#read 6, iclass 33, count 0 2006.197.07:40:10.55#ibcon#end of sib2, iclass 33, count 0 2006.197.07:40:10.55#ibcon#*after write, iclass 33, count 0 2006.197.07:40:10.55#ibcon#*before return 0, iclass 33, count 0 2006.197.07:40:10.55#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.197.07:40:10.55#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.197.07:40:10.55#ibcon#about to clear, iclass 33 cls_cnt 0 2006.197.07:40:10.55#ibcon#cleared, iclass 33 cls_cnt 0 2006.197.07:40:10.55$vc4f8/vb=2,4 2006.197.07:40:10.55#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.197.07:40:10.55#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.197.07:40:10.55#ibcon#ireg 11 cls_cnt 2 2006.197.07:40:10.55#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.197.07:40:10.61#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.197.07:40:10.61#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.197.07:40:10.61#ibcon#enter wrdev, iclass 35, count 2 2006.197.07:40:10.61#ibcon#first serial, iclass 35, count 2 2006.197.07:40:10.61#ibcon#enter sib2, iclass 35, count 2 2006.197.07:40:10.61#ibcon#flushed, iclass 35, count 2 2006.197.07:40:10.61#ibcon#about to write, iclass 35, count 2 2006.197.07:40:10.61#ibcon#wrote, iclass 35, count 2 2006.197.07:40:10.61#ibcon#about to read 3, iclass 35, count 2 2006.197.07:40:10.63#ibcon#read 3, iclass 35, count 2 2006.197.07:40:10.63#ibcon#about to read 4, iclass 35, count 2 2006.197.07:40:10.63#ibcon#read 4, iclass 35, count 2 2006.197.07:40:10.63#ibcon#about to read 5, iclass 35, count 2 2006.197.07:40:10.63#ibcon#read 5, iclass 35, count 2 2006.197.07:40:10.63#ibcon#about to read 6, iclass 35, count 2 2006.197.07:40:10.63#ibcon#read 6, iclass 35, count 2 2006.197.07:40:10.63#ibcon#end of sib2, iclass 35, count 2 2006.197.07:40:10.63#ibcon#*mode == 0, iclass 35, count 2 2006.197.07:40:10.63#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.197.07:40:10.63#ibcon#[27=AT02-04\r\n] 2006.197.07:40:10.63#ibcon#*before write, iclass 35, count 2 2006.197.07:40:10.63#ibcon#enter sib2, iclass 35, count 2 2006.197.07:40:10.63#ibcon#flushed, iclass 35, count 2 2006.197.07:40:10.63#ibcon#about to write, iclass 35, count 2 2006.197.07:40:10.63#ibcon#wrote, iclass 35, count 2 2006.197.07:40:10.63#ibcon#about to read 3, iclass 35, count 2 2006.197.07:40:10.66#ibcon#read 3, iclass 35, count 2 2006.197.07:40:10.66#ibcon#about to read 4, iclass 35, count 2 2006.197.07:40:10.66#ibcon#read 4, iclass 35, count 2 2006.197.07:40:10.66#ibcon#about to read 5, iclass 35, count 2 2006.197.07:40:10.66#ibcon#read 5, iclass 35, count 2 2006.197.07:40:10.66#ibcon#about to read 6, iclass 35, count 2 2006.197.07:40:10.66#ibcon#read 6, iclass 35, count 2 2006.197.07:40:10.66#ibcon#end of sib2, iclass 35, count 2 2006.197.07:40:10.66#ibcon#*after write, iclass 35, count 2 2006.197.07:40:10.66#ibcon#*before return 0, iclass 35, count 2 2006.197.07:40:10.66#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.197.07:40:10.66#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.197.07:40:10.66#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.197.07:40:10.66#ibcon#ireg 7 cls_cnt 0 2006.197.07:40:10.66#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.197.07:40:10.78#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.197.07:40:10.78#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.197.07:40:10.78#ibcon#enter wrdev, iclass 35, count 0 2006.197.07:40:10.78#ibcon#first serial, iclass 35, count 0 2006.197.07:40:10.78#ibcon#enter sib2, iclass 35, count 0 2006.197.07:40:10.78#ibcon#flushed, iclass 35, count 0 2006.197.07:40:10.78#ibcon#about to write, iclass 35, count 0 2006.197.07:40:10.78#ibcon#wrote, iclass 35, count 0 2006.197.07:40:10.78#ibcon#about to read 3, iclass 35, count 0 2006.197.07:40:10.80#ibcon#read 3, iclass 35, count 0 2006.197.07:40:10.80#ibcon#about to read 4, iclass 35, count 0 2006.197.07:40:10.80#ibcon#read 4, iclass 35, count 0 2006.197.07:40:10.80#ibcon#about to read 5, iclass 35, count 0 2006.197.07:40:10.80#ibcon#read 5, iclass 35, count 0 2006.197.07:40:10.80#ibcon#about to read 6, iclass 35, count 0 2006.197.07:40:10.80#ibcon#read 6, iclass 35, count 0 2006.197.07:40:10.80#ibcon#end of sib2, iclass 35, count 0 2006.197.07:40:10.80#ibcon#*mode == 0, iclass 35, count 0 2006.197.07:40:10.80#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.197.07:40:10.80#ibcon#[27=USB\r\n] 2006.197.07:40:10.80#ibcon#*before write, iclass 35, count 0 2006.197.07:40:10.80#ibcon#enter sib2, iclass 35, count 0 2006.197.07:40:10.80#ibcon#flushed, iclass 35, count 0 2006.197.07:40:10.80#ibcon#about to write, iclass 35, count 0 2006.197.07:40:10.80#ibcon#wrote, iclass 35, count 0 2006.197.07:40:10.80#ibcon#about to read 3, iclass 35, count 0 2006.197.07:40:10.83#ibcon#read 3, iclass 35, count 0 2006.197.07:40:10.83#ibcon#about to read 4, iclass 35, count 0 2006.197.07:40:10.83#ibcon#read 4, iclass 35, count 0 2006.197.07:40:10.83#ibcon#about to read 5, iclass 35, count 0 2006.197.07:40:10.83#ibcon#read 5, iclass 35, count 0 2006.197.07:40:10.83#ibcon#about to read 6, iclass 35, count 0 2006.197.07:40:10.83#ibcon#read 6, iclass 35, count 0 2006.197.07:40:10.83#ibcon#end of sib2, iclass 35, count 0 2006.197.07:40:10.83#ibcon#*after write, iclass 35, count 0 2006.197.07:40:10.83#ibcon#*before return 0, iclass 35, count 0 2006.197.07:40:10.83#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.197.07:40:10.83#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.197.07:40:10.83#ibcon#about to clear, iclass 35 cls_cnt 0 2006.197.07:40:10.83#ibcon#cleared, iclass 35 cls_cnt 0 2006.197.07:40:10.83$vc4f8/vblo=3,656.99 2006.197.07:40:10.83#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.197.07:40:10.83#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.197.07:40:10.83#ibcon#ireg 17 cls_cnt 0 2006.197.07:40:10.83#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.197.07:40:10.83#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.197.07:40:10.83#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.197.07:40:10.83#ibcon#enter wrdev, iclass 37, count 0 2006.197.07:40:10.83#ibcon#first serial, iclass 37, count 0 2006.197.07:40:10.83#ibcon#enter sib2, iclass 37, count 0 2006.197.07:40:10.83#ibcon#flushed, iclass 37, count 0 2006.197.07:40:10.83#ibcon#about to write, iclass 37, count 0 2006.197.07:40:10.83#ibcon#wrote, iclass 37, count 0 2006.197.07:40:10.83#ibcon#about to read 3, iclass 37, count 0 2006.197.07:40:10.85#ibcon#read 3, iclass 37, count 0 2006.197.07:40:10.85#ibcon#about to read 4, iclass 37, count 0 2006.197.07:40:10.85#ibcon#read 4, iclass 37, count 0 2006.197.07:40:10.85#ibcon#about to read 5, iclass 37, count 0 2006.197.07:40:10.85#ibcon#read 5, iclass 37, count 0 2006.197.07:40:10.85#ibcon#about to read 6, iclass 37, count 0 2006.197.07:40:10.85#ibcon#read 6, iclass 37, count 0 2006.197.07:40:10.85#ibcon#end of sib2, iclass 37, count 0 2006.197.07:40:10.85#ibcon#*mode == 0, iclass 37, count 0 2006.197.07:40:10.85#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.197.07:40:10.85#ibcon#[28=FRQ=03,656.99\r\n] 2006.197.07:40:10.85#ibcon#*before write, iclass 37, count 0 2006.197.07:40:10.85#ibcon#enter sib2, iclass 37, count 0 2006.197.07:40:10.85#ibcon#flushed, iclass 37, count 0 2006.197.07:40:10.85#ibcon#about to write, iclass 37, count 0 2006.197.07:40:10.85#ibcon#wrote, iclass 37, count 0 2006.197.07:40:10.85#ibcon#about to read 3, iclass 37, count 0 2006.197.07:40:10.89#ibcon#read 3, iclass 37, count 0 2006.197.07:40:10.89#ibcon#about to read 4, iclass 37, count 0 2006.197.07:40:10.89#ibcon#read 4, iclass 37, count 0 2006.197.07:40:10.89#ibcon#about to read 5, iclass 37, count 0 2006.197.07:40:10.89#ibcon#read 5, iclass 37, count 0 2006.197.07:40:10.89#ibcon#about to read 6, iclass 37, count 0 2006.197.07:40:10.89#ibcon#read 6, iclass 37, count 0 2006.197.07:40:10.89#ibcon#end of sib2, iclass 37, count 0 2006.197.07:40:10.89#ibcon#*after write, iclass 37, count 0 2006.197.07:40:10.89#ibcon#*before return 0, iclass 37, count 0 2006.197.07:40:10.89#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.197.07:40:10.89#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.197.07:40:10.89#ibcon#about to clear, iclass 37 cls_cnt 0 2006.197.07:40:10.89#ibcon#cleared, iclass 37 cls_cnt 0 2006.197.07:40:10.89$vc4f8/vb=3,4 2006.197.07:40:10.89#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.197.07:40:10.89#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.197.07:40:10.89#ibcon#ireg 11 cls_cnt 2 2006.197.07:40:10.89#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.197.07:40:10.95#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.197.07:40:10.95#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.197.07:40:10.95#ibcon#enter wrdev, iclass 39, count 2 2006.197.07:40:10.95#ibcon#first serial, iclass 39, count 2 2006.197.07:40:10.95#ibcon#enter sib2, iclass 39, count 2 2006.197.07:40:10.95#ibcon#flushed, iclass 39, count 2 2006.197.07:40:10.95#ibcon#about to write, iclass 39, count 2 2006.197.07:40:10.95#ibcon#wrote, iclass 39, count 2 2006.197.07:40:10.95#ibcon#about to read 3, iclass 39, count 2 2006.197.07:40:10.97#ibcon#read 3, iclass 39, count 2 2006.197.07:40:10.97#ibcon#about to read 4, iclass 39, count 2 2006.197.07:40:10.97#ibcon#read 4, iclass 39, count 2 2006.197.07:40:10.97#ibcon#about to read 5, iclass 39, count 2 2006.197.07:40:10.97#ibcon#read 5, iclass 39, count 2 2006.197.07:40:10.97#ibcon#about to read 6, iclass 39, count 2 2006.197.07:40:10.97#ibcon#read 6, iclass 39, count 2 2006.197.07:40:10.97#ibcon#end of sib2, iclass 39, count 2 2006.197.07:40:10.97#ibcon#*mode == 0, iclass 39, count 2 2006.197.07:40:10.97#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.197.07:40:10.97#ibcon#[27=AT03-04\r\n] 2006.197.07:40:10.97#ibcon#*before write, iclass 39, count 2 2006.197.07:40:10.97#ibcon#enter sib2, iclass 39, count 2 2006.197.07:40:10.97#ibcon#flushed, iclass 39, count 2 2006.197.07:40:10.97#ibcon#about to write, iclass 39, count 2 2006.197.07:40:10.97#ibcon#wrote, iclass 39, count 2 2006.197.07:40:10.97#ibcon#about to read 3, iclass 39, count 2 2006.197.07:40:11.00#ibcon#read 3, iclass 39, count 2 2006.197.07:40:11.00#ibcon#about to read 4, iclass 39, count 2 2006.197.07:40:11.00#ibcon#read 4, iclass 39, count 2 2006.197.07:40:11.00#ibcon#about to read 5, iclass 39, count 2 2006.197.07:40:11.00#ibcon#read 5, iclass 39, count 2 2006.197.07:40:11.00#ibcon#about to read 6, iclass 39, count 2 2006.197.07:40:11.00#ibcon#read 6, iclass 39, count 2 2006.197.07:40:11.00#ibcon#end of sib2, iclass 39, count 2 2006.197.07:40:11.00#ibcon#*after write, iclass 39, count 2 2006.197.07:40:11.00#ibcon#*before return 0, iclass 39, count 2 2006.197.07:40:11.00#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.197.07:40:11.00#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.197.07:40:11.00#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.197.07:40:11.00#ibcon#ireg 7 cls_cnt 0 2006.197.07:40:11.00#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.197.07:40:11.12#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.197.07:40:11.12#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.197.07:40:11.12#ibcon#enter wrdev, iclass 39, count 0 2006.197.07:40:11.12#ibcon#first serial, iclass 39, count 0 2006.197.07:40:11.12#ibcon#enter sib2, iclass 39, count 0 2006.197.07:40:11.12#ibcon#flushed, iclass 39, count 0 2006.197.07:40:11.12#ibcon#about to write, iclass 39, count 0 2006.197.07:40:11.12#ibcon#wrote, iclass 39, count 0 2006.197.07:40:11.12#ibcon#about to read 3, iclass 39, count 0 2006.197.07:40:11.14#ibcon#read 3, iclass 39, count 0 2006.197.07:40:11.14#ibcon#about to read 4, iclass 39, count 0 2006.197.07:40:11.14#ibcon#read 4, iclass 39, count 0 2006.197.07:40:11.14#ibcon#about to read 5, iclass 39, count 0 2006.197.07:40:11.14#ibcon#read 5, iclass 39, count 0 2006.197.07:40:11.14#ibcon#about to read 6, iclass 39, count 0 2006.197.07:40:11.14#ibcon#read 6, iclass 39, count 0 2006.197.07:40:11.14#ibcon#end of sib2, iclass 39, count 0 2006.197.07:40:11.14#ibcon#*mode == 0, iclass 39, count 0 2006.197.07:40:11.14#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.197.07:40:11.14#ibcon#[27=USB\r\n] 2006.197.07:40:11.14#ibcon#*before write, iclass 39, count 0 2006.197.07:40:11.14#ibcon#enter sib2, iclass 39, count 0 2006.197.07:40:11.14#ibcon#flushed, iclass 39, count 0 2006.197.07:40:11.14#ibcon#about to write, iclass 39, count 0 2006.197.07:40:11.14#ibcon#wrote, iclass 39, count 0 2006.197.07:40:11.14#ibcon#about to read 3, iclass 39, count 0 2006.197.07:40:11.17#ibcon#read 3, iclass 39, count 0 2006.197.07:40:11.17#ibcon#about to read 4, iclass 39, count 0 2006.197.07:40:11.17#ibcon#read 4, iclass 39, count 0 2006.197.07:40:11.17#ibcon#about to read 5, iclass 39, count 0 2006.197.07:40:11.17#ibcon#read 5, iclass 39, count 0 2006.197.07:40:11.17#ibcon#about to read 6, iclass 39, count 0 2006.197.07:40:11.17#ibcon#read 6, iclass 39, count 0 2006.197.07:40:11.17#ibcon#end of sib2, iclass 39, count 0 2006.197.07:40:11.17#ibcon#*after write, iclass 39, count 0 2006.197.07:40:11.17#ibcon#*before return 0, iclass 39, count 0 2006.197.07:40:11.17#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.197.07:40:11.17#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.197.07:40:11.17#ibcon#about to clear, iclass 39 cls_cnt 0 2006.197.07:40:11.17#ibcon#cleared, iclass 39 cls_cnt 0 2006.197.07:40:11.17$vc4f8/vblo=4,712.99 2006.197.07:40:11.17#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.197.07:40:11.17#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.197.07:40:11.17#ibcon#ireg 17 cls_cnt 0 2006.197.07:40:11.17#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.197.07:40:11.17#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.197.07:40:11.17#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.197.07:40:11.17#ibcon#enter wrdev, iclass 3, count 0 2006.197.07:40:11.17#ibcon#first serial, iclass 3, count 0 2006.197.07:40:11.17#ibcon#enter sib2, iclass 3, count 0 2006.197.07:40:11.17#ibcon#flushed, iclass 3, count 0 2006.197.07:40:11.17#ibcon#about to write, iclass 3, count 0 2006.197.07:40:11.17#ibcon#wrote, iclass 3, count 0 2006.197.07:40:11.17#ibcon#about to read 3, iclass 3, count 0 2006.197.07:40:11.19#ibcon#read 3, iclass 3, count 0 2006.197.07:40:11.19#ibcon#about to read 4, iclass 3, count 0 2006.197.07:40:11.19#ibcon#read 4, iclass 3, count 0 2006.197.07:40:11.19#ibcon#about to read 5, iclass 3, count 0 2006.197.07:40:11.19#ibcon#read 5, iclass 3, count 0 2006.197.07:40:11.19#ibcon#about to read 6, iclass 3, count 0 2006.197.07:40:11.19#ibcon#read 6, iclass 3, count 0 2006.197.07:40:11.19#ibcon#end of sib2, iclass 3, count 0 2006.197.07:40:11.19#ibcon#*mode == 0, iclass 3, count 0 2006.197.07:40:11.19#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.197.07:40:11.19#ibcon#[28=FRQ=04,712.99\r\n] 2006.197.07:40:11.19#ibcon#*before write, iclass 3, count 0 2006.197.07:40:11.19#ibcon#enter sib2, iclass 3, count 0 2006.197.07:40:11.19#ibcon#flushed, iclass 3, count 0 2006.197.07:40:11.19#ibcon#about to write, iclass 3, count 0 2006.197.07:40:11.19#ibcon#wrote, iclass 3, count 0 2006.197.07:40:11.19#ibcon#about to read 3, iclass 3, count 0 2006.197.07:40:11.23#ibcon#read 3, iclass 3, count 0 2006.197.07:40:11.23#ibcon#about to read 4, iclass 3, count 0 2006.197.07:40:11.23#ibcon#read 4, iclass 3, count 0 2006.197.07:40:11.23#ibcon#about to read 5, iclass 3, count 0 2006.197.07:40:11.23#ibcon#read 5, iclass 3, count 0 2006.197.07:40:11.23#ibcon#about to read 6, iclass 3, count 0 2006.197.07:40:11.23#ibcon#read 6, iclass 3, count 0 2006.197.07:40:11.23#ibcon#end of sib2, iclass 3, count 0 2006.197.07:40:11.23#ibcon#*after write, iclass 3, count 0 2006.197.07:40:11.23#ibcon#*before return 0, iclass 3, count 0 2006.197.07:40:11.23#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.197.07:40:11.23#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.197.07:40:11.23#ibcon#about to clear, iclass 3 cls_cnt 0 2006.197.07:40:11.23#ibcon#cleared, iclass 3 cls_cnt 0 2006.197.07:40:11.23$vc4f8/vb=4,4 2006.197.07:40:11.23#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.197.07:40:11.23#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.197.07:40:11.23#ibcon#ireg 11 cls_cnt 2 2006.197.07:40:11.23#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.197.07:40:11.29#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.197.07:40:11.29#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.197.07:40:11.29#ibcon#enter wrdev, iclass 5, count 2 2006.197.07:40:11.29#ibcon#first serial, iclass 5, count 2 2006.197.07:40:11.29#ibcon#enter sib2, iclass 5, count 2 2006.197.07:40:11.29#ibcon#flushed, iclass 5, count 2 2006.197.07:40:11.29#ibcon#about to write, iclass 5, count 2 2006.197.07:40:11.29#ibcon#wrote, iclass 5, count 2 2006.197.07:40:11.29#ibcon#about to read 3, iclass 5, count 2 2006.197.07:40:11.31#ibcon#read 3, iclass 5, count 2 2006.197.07:40:11.31#ibcon#about to read 4, iclass 5, count 2 2006.197.07:40:11.31#ibcon#read 4, iclass 5, count 2 2006.197.07:40:11.31#ibcon#about to read 5, iclass 5, count 2 2006.197.07:40:11.31#ibcon#read 5, iclass 5, count 2 2006.197.07:40:11.31#ibcon#about to read 6, iclass 5, count 2 2006.197.07:40:11.31#ibcon#read 6, iclass 5, count 2 2006.197.07:40:11.31#ibcon#end of sib2, iclass 5, count 2 2006.197.07:40:11.31#ibcon#*mode == 0, iclass 5, count 2 2006.197.07:40:11.31#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.197.07:40:11.31#ibcon#[27=AT04-04\r\n] 2006.197.07:40:11.31#ibcon#*before write, iclass 5, count 2 2006.197.07:40:11.31#ibcon#enter sib2, iclass 5, count 2 2006.197.07:40:11.31#ibcon#flushed, iclass 5, count 2 2006.197.07:40:11.31#ibcon#about to write, iclass 5, count 2 2006.197.07:40:11.31#ibcon#wrote, iclass 5, count 2 2006.197.07:40:11.31#ibcon#about to read 3, iclass 5, count 2 2006.197.07:40:11.34#ibcon#read 3, iclass 5, count 2 2006.197.07:40:11.34#ibcon#about to read 4, iclass 5, count 2 2006.197.07:40:11.34#ibcon#read 4, iclass 5, count 2 2006.197.07:40:11.34#ibcon#about to read 5, iclass 5, count 2 2006.197.07:40:11.34#ibcon#read 5, iclass 5, count 2 2006.197.07:40:11.34#ibcon#about to read 6, iclass 5, count 2 2006.197.07:40:11.34#ibcon#read 6, iclass 5, count 2 2006.197.07:40:11.34#ibcon#end of sib2, iclass 5, count 2 2006.197.07:40:11.34#ibcon#*after write, iclass 5, count 2 2006.197.07:40:11.34#ibcon#*before return 0, iclass 5, count 2 2006.197.07:40:11.34#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.197.07:40:11.34#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.197.07:40:11.34#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.197.07:40:11.34#ibcon#ireg 7 cls_cnt 0 2006.197.07:40:11.34#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.197.07:40:11.46#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.197.07:40:11.46#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.197.07:40:11.46#ibcon#enter wrdev, iclass 5, count 0 2006.197.07:40:11.46#ibcon#first serial, iclass 5, count 0 2006.197.07:40:11.46#ibcon#enter sib2, iclass 5, count 0 2006.197.07:40:11.46#ibcon#flushed, iclass 5, count 0 2006.197.07:40:11.46#ibcon#about to write, iclass 5, count 0 2006.197.07:40:11.46#ibcon#wrote, iclass 5, count 0 2006.197.07:40:11.46#ibcon#about to read 3, iclass 5, count 0 2006.197.07:40:11.48#ibcon#read 3, iclass 5, count 0 2006.197.07:40:11.48#ibcon#about to read 4, iclass 5, count 0 2006.197.07:40:11.48#ibcon#read 4, iclass 5, count 0 2006.197.07:40:11.48#ibcon#about to read 5, iclass 5, count 0 2006.197.07:40:11.48#ibcon#read 5, iclass 5, count 0 2006.197.07:40:11.48#ibcon#about to read 6, iclass 5, count 0 2006.197.07:40:11.48#ibcon#read 6, iclass 5, count 0 2006.197.07:40:11.48#ibcon#end of sib2, iclass 5, count 0 2006.197.07:40:11.48#ibcon#*mode == 0, iclass 5, count 0 2006.197.07:40:11.48#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.197.07:40:11.48#ibcon#[27=USB\r\n] 2006.197.07:40:11.48#ibcon#*before write, iclass 5, count 0 2006.197.07:40:11.48#ibcon#enter sib2, iclass 5, count 0 2006.197.07:40:11.48#ibcon#flushed, iclass 5, count 0 2006.197.07:40:11.48#ibcon#about to write, iclass 5, count 0 2006.197.07:40:11.48#ibcon#wrote, iclass 5, count 0 2006.197.07:40:11.48#ibcon#about to read 3, iclass 5, count 0 2006.197.07:40:11.51#ibcon#read 3, iclass 5, count 0 2006.197.07:40:11.51#ibcon#about to read 4, iclass 5, count 0 2006.197.07:40:11.51#ibcon#read 4, iclass 5, count 0 2006.197.07:40:11.51#ibcon#about to read 5, iclass 5, count 0 2006.197.07:40:11.51#ibcon#read 5, iclass 5, count 0 2006.197.07:40:11.51#ibcon#about to read 6, iclass 5, count 0 2006.197.07:40:11.51#ibcon#read 6, iclass 5, count 0 2006.197.07:40:11.51#ibcon#end of sib2, iclass 5, count 0 2006.197.07:40:11.51#ibcon#*after write, iclass 5, count 0 2006.197.07:40:11.51#ibcon#*before return 0, iclass 5, count 0 2006.197.07:40:11.51#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.197.07:40:11.51#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.197.07:40:11.51#ibcon#about to clear, iclass 5 cls_cnt 0 2006.197.07:40:11.51#ibcon#cleared, iclass 5 cls_cnt 0 2006.197.07:40:11.51$vc4f8/vblo=5,744.99 2006.197.07:40:11.51#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.197.07:40:11.51#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.197.07:40:11.51#ibcon#ireg 17 cls_cnt 0 2006.197.07:40:11.51#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.197.07:40:11.51#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.197.07:40:11.51#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.197.07:40:11.51#ibcon#enter wrdev, iclass 7, count 0 2006.197.07:40:11.51#ibcon#first serial, iclass 7, count 0 2006.197.07:40:11.51#ibcon#enter sib2, iclass 7, count 0 2006.197.07:40:11.51#ibcon#flushed, iclass 7, count 0 2006.197.07:40:11.51#ibcon#about to write, iclass 7, count 0 2006.197.07:40:11.51#ibcon#wrote, iclass 7, count 0 2006.197.07:40:11.51#ibcon#about to read 3, iclass 7, count 0 2006.197.07:40:11.53#ibcon#read 3, iclass 7, count 0 2006.197.07:40:11.53#ibcon#about to read 4, iclass 7, count 0 2006.197.07:40:11.53#ibcon#read 4, iclass 7, count 0 2006.197.07:40:11.53#ibcon#about to read 5, iclass 7, count 0 2006.197.07:40:11.53#ibcon#read 5, iclass 7, count 0 2006.197.07:40:11.53#ibcon#about to read 6, iclass 7, count 0 2006.197.07:40:11.53#ibcon#read 6, iclass 7, count 0 2006.197.07:40:11.53#ibcon#end of sib2, iclass 7, count 0 2006.197.07:40:11.53#ibcon#*mode == 0, iclass 7, count 0 2006.197.07:40:11.53#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.197.07:40:11.53#ibcon#[28=FRQ=05,744.99\r\n] 2006.197.07:40:11.53#ibcon#*before write, iclass 7, count 0 2006.197.07:40:11.53#ibcon#enter sib2, iclass 7, count 0 2006.197.07:40:11.53#ibcon#flushed, iclass 7, count 0 2006.197.07:40:11.53#ibcon#about to write, iclass 7, count 0 2006.197.07:40:11.53#ibcon#wrote, iclass 7, count 0 2006.197.07:40:11.53#ibcon#about to read 3, iclass 7, count 0 2006.197.07:40:11.57#ibcon#read 3, iclass 7, count 0 2006.197.07:40:11.57#ibcon#about to read 4, iclass 7, count 0 2006.197.07:40:11.57#ibcon#read 4, iclass 7, count 0 2006.197.07:40:11.57#ibcon#about to read 5, iclass 7, count 0 2006.197.07:40:11.57#ibcon#read 5, iclass 7, count 0 2006.197.07:40:11.57#ibcon#about to read 6, iclass 7, count 0 2006.197.07:40:11.57#ibcon#read 6, iclass 7, count 0 2006.197.07:40:11.57#ibcon#end of sib2, iclass 7, count 0 2006.197.07:40:11.57#ibcon#*after write, iclass 7, count 0 2006.197.07:40:11.57#ibcon#*before return 0, iclass 7, count 0 2006.197.07:40:11.57#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.197.07:40:11.57#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.197.07:40:11.57#ibcon#about to clear, iclass 7 cls_cnt 0 2006.197.07:40:11.57#ibcon#cleared, iclass 7 cls_cnt 0 2006.197.07:40:11.57$vc4f8/vb=5,4 2006.197.07:40:11.57#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.197.07:40:11.57#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.197.07:40:11.57#ibcon#ireg 11 cls_cnt 2 2006.197.07:40:11.57#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.197.07:40:11.63#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.197.07:40:11.63#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.197.07:40:11.63#ibcon#enter wrdev, iclass 11, count 2 2006.197.07:40:11.63#ibcon#first serial, iclass 11, count 2 2006.197.07:40:11.63#ibcon#enter sib2, iclass 11, count 2 2006.197.07:40:11.63#ibcon#flushed, iclass 11, count 2 2006.197.07:40:11.63#ibcon#about to write, iclass 11, count 2 2006.197.07:40:11.63#ibcon#wrote, iclass 11, count 2 2006.197.07:40:11.63#ibcon#about to read 3, iclass 11, count 2 2006.197.07:40:11.65#ibcon#read 3, iclass 11, count 2 2006.197.07:40:11.65#ibcon#about to read 4, iclass 11, count 2 2006.197.07:40:11.65#ibcon#read 4, iclass 11, count 2 2006.197.07:40:11.65#ibcon#about to read 5, iclass 11, count 2 2006.197.07:40:11.65#ibcon#read 5, iclass 11, count 2 2006.197.07:40:11.65#ibcon#about to read 6, iclass 11, count 2 2006.197.07:40:11.65#ibcon#read 6, iclass 11, count 2 2006.197.07:40:11.65#ibcon#end of sib2, iclass 11, count 2 2006.197.07:40:11.65#ibcon#*mode == 0, iclass 11, count 2 2006.197.07:40:11.65#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.197.07:40:11.65#ibcon#[27=AT05-04\r\n] 2006.197.07:40:11.65#ibcon#*before write, iclass 11, count 2 2006.197.07:40:11.65#ibcon#enter sib2, iclass 11, count 2 2006.197.07:40:11.65#ibcon#flushed, iclass 11, count 2 2006.197.07:40:11.65#ibcon#about to write, iclass 11, count 2 2006.197.07:40:11.65#ibcon#wrote, iclass 11, count 2 2006.197.07:40:11.65#ibcon#about to read 3, iclass 11, count 2 2006.197.07:40:11.68#ibcon#read 3, iclass 11, count 2 2006.197.07:40:11.68#ibcon#about to read 4, iclass 11, count 2 2006.197.07:40:11.68#ibcon#read 4, iclass 11, count 2 2006.197.07:40:11.68#ibcon#about to read 5, iclass 11, count 2 2006.197.07:40:11.68#ibcon#read 5, iclass 11, count 2 2006.197.07:40:11.68#ibcon#about to read 6, iclass 11, count 2 2006.197.07:40:11.68#ibcon#read 6, iclass 11, count 2 2006.197.07:40:11.68#ibcon#end of sib2, iclass 11, count 2 2006.197.07:40:11.68#ibcon#*after write, iclass 11, count 2 2006.197.07:40:11.68#ibcon#*before return 0, iclass 11, count 2 2006.197.07:40:11.68#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.197.07:40:11.68#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.197.07:40:11.68#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.197.07:40:11.68#ibcon#ireg 7 cls_cnt 0 2006.197.07:40:11.68#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.197.07:40:11.80#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.197.07:40:11.80#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.197.07:40:11.80#ibcon#enter wrdev, iclass 11, count 0 2006.197.07:40:11.80#ibcon#first serial, iclass 11, count 0 2006.197.07:40:11.80#ibcon#enter sib2, iclass 11, count 0 2006.197.07:40:11.80#ibcon#flushed, iclass 11, count 0 2006.197.07:40:11.80#ibcon#about to write, iclass 11, count 0 2006.197.07:40:11.80#ibcon#wrote, iclass 11, count 0 2006.197.07:40:11.80#ibcon#about to read 3, iclass 11, count 0 2006.197.07:40:11.82#ibcon#read 3, iclass 11, count 0 2006.197.07:40:11.82#ibcon#about to read 4, iclass 11, count 0 2006.197.07:40:11.82#ibcon#read 4, iclass 11, count 0 2006.197.07:40:11.82#ibcon#about to read 5, iclass 11, count 0 2006.197.07:40:11.82#ibcon#read 5, iclass 11, count 0 2006.197.07:40:11.82#ibcon#about to read 6, iclass 11, count 0 2006.197.07:40:11.82#ibcon#read 6, iclass 11, count 0 2006.197.07:40:11.82#ibcon#end of sib2, iclass 11, count 0 2006.197.07:40:11.82#ibcon#*mode == 0, iclass 11, count 0 2006.197.07:40:11.82#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.197.07:40:11.82#ibcon#[27=USB\r\n] 2006.197.07:40:11.82#ibcon#*before write, iclass 11, count 0 2006.197.07:40:11.82#ibcon#enter sib2, iclass 11, count 0 2006.197.07:40:11.82#ibcon#flushed, iclass 11, count 0 2006.197.07:40:11.82#ibcon#about to write, iclass 11, count 0 2006.197.07:40:11.82#ibcon#wrote, iclass 11, count 0 2006.197.07:40:11.82#ibcon#about to read 3, iclass 11, count 0 2006.197.07:40:11.85#ibcon#read 3, iclass 11, count 0 2006.197.07:40:11.85#ibcon#about to read 4, iclass 11, count 0 2006.197.07:40:11.85#ibcon#read 4, iclass 11, count 0 2006.197.07:40:11.85#ibcon#about to read 5, iclass 11, count 0 2006.197.07:40:11.85#ibcon#read 5, iclass 11, count 0 2006.197.07:40:11.85#ibcon#about to read 6, iclass 11, count 0 2006.197.07:40:11.85#ibcon#read 6, iclass 11, count 0 2006.197.07:40:11.85#ibcon#end of sib2, iclass 11, count 0 2006.197.07:40:11.85#ibcon#*after write, iclass 11, count 0 2006.197.07:40:11.85#ibcon#*before return 0, iclass 11, count 0 2006.197.07:40:11.85#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.197.07:40:11.85#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.197.07:40:11.85#ibcon#about to clear, iclass 11 cls_cnt 0 2006.197.07:40:11.85#ibcon#cleared, iclass 11 cls_cnt 0 2006.197.07:40:11.85$vc4f8/vblo=6,752.99 2006.197.07:40:11.85#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.197.07:40:11.85#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.197.07:40:11.85#ibcon#ireg 17 cls_cnt 0 2006.197.07:40:11.85#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.197.07:40:11.85#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.197.07:40:11.85#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.197.07:40:11.85#ibcon#enter wrdev, iclass 13, count 0 2006.197.07:40:11.85#ibcon#first serial, iclass 13, count 0 2006.197.07:40:11.85#ibcon#enter sib2, iclass 13, count 0 2006.197.07:40:11.85#ibcon#flushed, iclass 13, count 0 2006.197.07:40:11.85#ibcon#about to write, iclass 13, count 0 2006.197.07:40:11.85#ibcon#wrote, iclass 13, count 0 2006.197.07:40:11.85#ibcon#about to read 3, iclass 13, count 0 2006.197.07:40:11.87#ibcon#read 3, iclass 13, count 0 2006.197.07:40:11.87#ibcon#about to read 4, iclass 13, count 0 2006.197.07:40:11.87#ibcon#read 4, iclass 13, count 0 2006.197.07:40:11.87#ibcon#about to read 5, iclass 13, count 0 2006.197.07:40:11.87#ibcon#read 5, iclass 13, count 0 2006.197.07:40:11.87#ibcon#about to read 6, iclass 13, count 0 2006.197.07:40:11.87#ibcon#read 6, iclass 13, count 0 2006.197.07:40:11.87#ibcon#end of sib2, iclass 13, count 0 2006.197.07:40:11.87#ibcon#*mode == 0, iclass 13, count 0 2006.197.07:40:11.87#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.197.07:40:11.87#ibcon#[28=FRQ=06,752.99\r\n] 2006.197.07:40:11.87#ibcon#*before write, iclass 13, count 0 2006.197.07:40:11.87#ibcon#enter sib2, iclass 13, count 0 2006.197.07:40:11.87#ibcon#flushed, iclass 13, count 0 2006.197.07:40:11.87#ibcon#about to write, iclass 13, count 0 2006.197.07:40:11.87#ibcon#wrote, iclass 13, count 0 2006.197.07:40:11.87#ibcon#about to read 3, iclass 13, count 0 2006.197.07:40:11.91#ibcon#read 3, iclass 13, count 0 2006.197.07:40:11.91#ibcon#about to read 4, iclass 13, count 0 2006.197.07:40:11.91#ibcon#read 4, iclass 13, count 0 2006.197.07:40:11.91#ibcon#about to read 5, iclass 13, count 0 2006.197.07:40:11.91#ibcon#read 5, iclass 13, count 0 2006.197.07:40:11.91#ibcon#about to read 6, iclass 13, count 0 2006.197.07:40:11.91#ibcon#read 6, iclass 13, count 0 2006.197.07:40:11.91#ibcon#end of sib2, iclass 13, count 0 2006.197.07:40:11.91#ibcon#*after write, iclass 13, count 0 2006.197.07:40:11.91#ibcon#*before return 0, iclass 13, count 0 2006.197.07:40:11.91#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.197.07:40:11.91#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.197.07:40:11.91#ibcon#about to clear, iclass 13 cls_cnt 0 2006.197.07:40:11.91#ibcon#cleared, iclass 13 cls_cnt 0 2006.197.07:40:11.91$vc4f8/vb=6,4 2006.197.07:40:11.91#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.197.07:40:11.91#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.197.07:40:11.91#ibcon#ireg 11 cls_cnt 2 2006.197.07:40:11.91#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.197.07:40:11.97#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.197.07:40:11.97#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.197.07:40:11.97#ibcon#enter wrdev, iclass 15, count 2 2006.197.07:40:11.97#ibcon#first serial, iclass 15, count 2 2006.197.07:40:11.97#ibcon#enter sib2, iclass 15, count 2 2006.197.07:40:11.97#ibcon#flushed, iclass 15, count 2 2006.197.07:40:11.97#ibcon#about to write, iclass 15, count 2 2006.197.07:40:11.97#ibcon#wrote, iclass 15, count 2 2006.197.07:40:11.97#ibcon#about to read 3, iclass 15, count 2 2006.197.07:40:11.99#ibcon#read 3, iclass 15, count 2 2006.197.07:40:11.99#ibcon#about to read 4, iclass 15, count 2 2006.197.07:40:11.99#ibcon#read 4, iclass 15, count 2 2006.197.07:40:11.99#ibcon#about to read 5, iclass 15, count 2 2006.197.07:40:11.99#ibcon#read 5, iclass 15, count 2 2006.197.07:40:11.99#ibcon#about to read 6, iclass 15, count 2 2006.197.07:40:11.99#ibcon#read 6, iclass 15, count 2 2006.197.07:40:11.99#ibcon#end of sib2, iclass 15, count 2 2006.197.07:40:11.99#ibcon#*mode == 0, iclass 15, count 2 2006.197.07:40:11.99#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.197.07:40:11.99#ibcon#[27=AT06-04\r\n] 2006.197.07:40:11.99#ibcon#*before write, iclass 15, count 2 2006.197.07:40:11.99#ibcon#enter sib2, iclass 15, count 2 2006.197.07:40:11.99#ibcon#flushed, iclass 15, count 2 2006.197.07:40:11.99#ibcon#about to write, iclass 15, count 2 2006.197.07:40:11.99#ibcon#wrote, iclass 15, count 2 2006.197.07:40:11.99#ibcon#about to read 3, iclass 15, count 2 2006.197.07:40:12.02#ibcon#read 3, iclass 15, count 2 2006.197.07:40:12.02#ibcon#about to read 4, iclass 15, count 2 2006.197.07:40:12.02#ibcon#read 4, iclass 15, count 2 2006.197.07:40:12.02#ibcon#about to read 5, iclass 15, count 2 2006.197.07:40:12.02#ibcon#read 5, iclass 15, count 2 2006.197.07:40:12.02#ibcon#about to read 6, iclass 15, count 2 2006.197.07:40:12.02#ibcon#read 6, iclass 15, count 2 2006.197.07:40:12.02#ibcon#end of sib2, iclass 15, count 2 2006.197.07:40:12.02#ibcon#*after write, iclass 15, count 2 2006.197.07:40:12.02#ibcon#*before return 0, iclass 15, count 2 2006.197.07:40:12.02#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.197.07:40:12.02#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.197.07:40:12.02#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.197.07:40:12.02#ibcon#ireg 7 cls_cnt 0 2006.197.07:40:12.02#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.197.07:40:12.14#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.197.07:40:12.14#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.197.07:40:12.14#ibcon#enter wrdev, iclass 15, count 0 2006.197.07:40:12.14#ibcon#first serial, iclass 15, count 0 2006.197.07:40:12.14#ibcon#enter sib2, iclass 15, count 0 2006.197.07:40:12.14#ibcon#flushed, iclass 15, count 0 2006.197.07:40:12.14#ibcon#about to write, iclass 15, count 0 2006.197.07:40:12.14#ibcon#wrote, iclass 15, count 0 2006.197.07:40:12.14#ibcon#about to read 3, iclass 15, count 0 2006.197.07:40:12.16#ibcon#read 3, iclass 15, count 0 2006.197.07:40:12.16#ibcon#about to read 4, iclass 15, count 0 2006.197.07:40:12.16#ibcon#read 4, iclass 15, count 0 2006.197.07:40:12.16#ibcon#about to read 5, iclass 15, count 0 2006.197.07:40:12.16#ibcon#read 5, iclass 15, count 0 2006.197.07:40:12.16#ibcon#about to read 6, iclass 15, count 0 2006.197.07:40:12.16#ibcon#read 6, iclass 15, count 0 2006.197.07:40:12.16#ibcon#end of sib2, iclass 15, count 0 2006.197.07:40:12.16#ibcon#*mode == 0, iclass 15, count 0 2006.197.07:40:12.16#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.197.07:40:12.16#ibcon#[27=USB\r\n] 2006.197.07:40:12.16#ibcon#*before write, iclass 15, count 0 2006.197.07:40:12.16#ibcon#enter sib2, iclass 15, count 0 2006.197.07:40:12.16#ibcon#flushed, iclass 15, count 0 2006.197.07:40:12.16#ibcon#about to write, iclass 15, count 0 2006.197.07:40:12.16#ibcon#wrote, iclass 15, count 0 2006.197.07:40:12.16#ibcon#about to read 3, iclass 15, count 0 2006.197.07:40:12.19#ibcon#read 3, iclass 15, count 0 2006.197.07:40:12.19#ibcon#about to read 4, iclass 15, count 0 2006.197.07:40:12.19#ibcon#read 4, iclass 15, count 0 2006.197.07:40:12.19#ibcon#about to read 5, iclass 15, count 0 2006.197.07:40:12.19#ibcon#read 5, iclass 15, count 0 2006.197.07:40:12.19#ibcon#about to read 6, iclass 15, count 0 2006.197.07:40:12.19#ibcon#read 6, iclass 15, count 0 2006.197.07:40:12.19#ibcon#end of sib2, iclass 15, count 0 2006.197.07:40:12.19#ibcon#*after write, iclass 15, count 0 2006.197.07:40:12.19#ibcon#*before return 0, iclass 15, count 0 2006.197.07:40:12.19#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.197.07:40:12.19#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.197.07:40:12.19#ibcon#about to clear, iclass 15 cls_cnt 0 2006.197.07:40:12.19#ibcon#cleared, iclass 15 cls_cnt 0 2006.197.07:40:12.19$vc4f8/vabw=wide 2006.197.07:40:12.19#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.197.07:40:12.19#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.197.07:40:12.19#ibcon#ireg 8 cls_cnt 0 2006.197.07:40:12.19#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.197.07:40:12.19#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.197.07:40:12.19#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.197.07:40:12.19#ibcon#enter wrdev, iclass 17, count 0 2006.197.07:40:12.19#ibcon#first serial, iclass 17, count 0 2006.197.07:40:12.19#ibcon#enter sib2, iclass 17, count 0 2006.197.07:40:12.19#ibcon#flushed, iclass 17, count 0 2006.197.07:40:12.19#ibcon#about to write, iclass 17, count 0 2006.197.07:40:12.19#ibcon#wrote, iclass 17, count 0 2006.197.07:40:12.19#ibcon#about to read 3, iclass 17, count 0 2006.197.07:40:12.21#ibcon#read 3, iclass 17, count 0 2006.197.07:40:12.21#ibcon#about to read 4, iclass 17, count 0 2006.197.07:40:12.21#ibcon#read 4, iclass 17, count 0 2006.197.07:40:12.21#ibcon#about to read 5, iclass 17, count 0 2006.197.07:40:12.21#ibcon#read 5, iclass 17, count 0 2006.197.07:40:12.21#ibcon#about to read 6, iclass 17, count 0 2006.197.07:40:12.21#ibcon#read 6, iclass 17, count 0 2006.197.07:40:12.21#ibcon#end of sib2, iclass 17, count 0 2006.197.07:40:12.21#ibcon#*mode == 0, iclass 17, count 0 2006.197.07:40:12.21#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.197.07:40:12.21#ibcon#[25=BW32\r\n] 2006.197.07:40:12.21#ibcon#*before write, iclass 17, count 0 2006.197.07:40:12.21#ibcon#enter sib2, iclass 17, count 0 2006.197.07:40:12.21#ibcon#flushed, iclass 17, count 0 2006.197.07:40:12.21#ibcon#about to write, iclass 17, count 0 2006.197.07:40:12.21#ibcon#wrote, iclass 17, count 0 2006.197.07:40:12.21#ibcon#about to read 3, iclass 17, count 0 2006.197.07:40:12.24#ibcon#read 3, iclass 17, count 0 2006.197.07:40:12.24#ibcon#about to read 4, iclass 17, count 0 2006.197.07:40:12.24#ibcon#read 4, iclass 17, count 0 2006.197.07:40:12.24#ibcon#about to read 5, iclass 17, count 0 2006.197.07:40:12.24#ibcon#read 5, iclass 17, count 0 2006.197.07:40:12.24#ibcon#about to read 6, iclass 17, count 0 2006.197.07:40:12.24#ibcon#read 6, iclass 17, count 0 2006.197.07:40:12.24#ibcon#end of sib2, iclass 17, count 0 2006.197.07:40:12.24#ibcon#*after write, iclass 17, count 0 2006.197.07:40:12.24#ibcon#*before return 0, iclass 17, count 0 2006.197.07:40:12.24#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.197.07:40:12.24#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.197.07:40:12.24#ibcon#about to clear, iclass 17 cls_cnt 0 2006.197.07:40:12.24#ibcon#cleared, iclass 17 cls_cnt 0 2006.197.07:40:12.24$vc4f8/vbbw=wide 2006.197.07:40:12.24#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.197.07:40:12.24#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.197.07:40:12.24#ibcon#ireg 8 cls_cnt 0 2006.197.07:40:12.24#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.197.07:40:12.31#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.197.07:40:12.31#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.197.07:40:12.31#ibcon#enter wrdev, iclass 19, count 0 2006.197.07:40:12.31#ibcon#first serial, iclass 19, count 0 2006.197.07:40:12.31#ibcon#enter sib2, iclass 19, count 0 2006.197.07:40:12.31#ibcon#flushed, iclass 19, count 0 2006.197.07:40:12.31#ibcon#about to write, iclass 19, count 0 2006.197.07:40:12.31#ibcon#wrote, iclass 19, count 0 2006.197.07:40:12.31#ibcon#about to read 3, iclass 19, count 0 2006.197.07:40:12.33#ibcon#read 3, iclass 19, count 0 2006.197.07:40:12.33#ibcon#about to read 4, iclass 19, count 0 2006.197.07:40:12.33#ibcon#read 4, iclass 19, count 0 2006.197.07:40:12.33#ibcon#about to read 5, iclass 19, count 0 2006.197.07:40:12.33#ibcon#read 5, iclass 19, count 0 2006.197.07:40:12.33#ibcon#about to read 6, iclass 19, count 0 2006.197.07:40:12.33#ibcon#read 6, iclass 19, count 0 2006.197.07:40:12.33#ibcon#end of sib2, iclass 19, count 0 2006.197.07:40:12.33#ibcon#*mode == 0, iclass 19, count 0 2006.197.07:40:12.33#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.197.07:40:12.33#ibcon#[27=BW32\r\n] 2006.197.07:40:12.33#ibcon#*before write, iclass 19, count 0 2006.197.07:40:12.33#ibcon#enter sib2, iclass 19, count 0 2006.197.07:40:12.33#ibcon#flushed, iclass 19, count 0 2006.197.07:40:12.33#ibcon#about to write, iclass 19, count 0 2006.197.07:40:12.33#ibcon#wrote, iclass 19, count 0 2006.197.07:40:12.33#ibcon#about to read 3, iclass 19, count 0 2006.197.07:40:12.36#ibcon#read 3, iclass 19, count 0 2006.197.07:40:12.36#ibcon#about to read 4, iclass 19, count 0 2006.197.07:40:12.36#ibcon#read 4, iclass 19, count 0 2006.197.07:40:12.36#ibcon#about to read 5, iclass 19, count 0 2006.197.07:40:12.36#ibcon#read 5, iclass 19, count 0 2006.197.07:40:12.36#ibcon#about to read 6, iclass 19, count 0 2006.197.07:40:12.36#ibcon#read 6, iclass 19, count 0 2006.197.07:40:12.36#ibcon#end of sib2, iclass 19, count 0 2006.197.07:40:12.36#ibcon#*after write, iclass 19, count 0 2006.197.07:40:12.36#ibcon#*before return 0, iclass 19, count 0 2006.197.07:40:12.36#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.197.07:40:12.36#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.197.07:40:12.36#ibcon#about to clear, iclass 19 cls_cnt 0 2006.197.07:40:12.36#ibcon#cleared, iclass 19 cls_cnt 0 2006.197.07:40:12.36$4f8m12a/ifd4f 2006.197.07:40:12.36$ifd4f/lo= 2006.197.07:40:12.36$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.197.07:40:12.36$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.197.07:40:12.36$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.197.07:40:12.36$ifd4f/patch= 2006.197.07:40:12.36$ifd4f/patch=lo1,a1,a2,a3,a4 2006.197.07:40:12.36$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.197.07:40:12.36$ifd4f/patch=lo3,a5,a6,a7,a8 2006.197.07:40:12.36$4f8m12a/"form=m,16.000,1:2 2006.197.07:40:12.36$4f8m12a/"tpicd 2006.197.07:40:12.36$4f8m12a/echo=off 2006.197.07:40:12.36$4f8m12a/xlog=off 2006.197.07:40:12.36:!2006.197.07:40:40 2006.197.07:40:25.14#trakl#Source acquired 2006.197.07:40:25.14#flagr#flagr/antenna,acquired 2006.197.07:40:40.00:preob 2006.197.07:40:41.14/onsource/TRACKING 2006.197.07:40:41.14:!2006.197.07:40:50 2006.197.07:40:50.00:data_valid=on 2006.197.07:40:50.00:midob 2006.197.07:40:50.14/onsource/TRACKING 2006.197.07:40:50.14/wx/25.86,1003.2,96 2006.197.07:40:50.29/cable/+6.3704E-03 2006.197.07:40:51.38/va/01,08,usb,yes,29,31 2006.197.07:40:51.38/va/02,07,usb,yes,29,31 2006.197.07:40:51.38/va/03,06,usb,yes,31,31 2006.197.07:40:51.38/va/04,07,usb,yes,30,32 2006.197.07:40:51.38/va/05,07,usb,yes,34,36 2006.197.07:40:51.38/va/06,06,usb,yes,33,33 2006.197.07:40:51.38/va/07,06,usb,yes,33,33 2006.197.07:40:51.38/va/08,07,usb,yes,31,31 2006.197.07:40:51.61/valo/01,532.99,yes,locked 2006.197.07:40:51.61/valo/02,572.99,yes,locked 2006.197.07:40:51.61/valo/03,672.99,yes,locked 2006.197.07:40:51.61/valo/04,832.99,yes,locked 2006.197.07:40:51.61/valo/05,652.99,yes,locked 2006.197.07:40:51.61/valo/06,772.99,yes,locked 2006.197.07:40:51.61/valo/07,832.99,yes,locked 2006.197.07:40:51.61/valo/08,852.99,yes,locked 2006.197.07:40:52.70/vb/01,04,usb,yes,29,27 2006.197.07:40:52.70/vb/02,04,usb,yes,30,32 2006.197.07:40:52.70/vb/03,04,usb,yes,27,30 2006.197.07:40:52.70/vb/04,04,usb,yes,28,28 2006.197.07:40:52.70/vb/05,04,usb,yes,26,30 2006.197.07:40:52.70/vb/06,04,usb,yes,27,30 2006.197.07:40:52.70/vb/07,04,usb,yes,29,29 2006.197.07:40:52.70/vb/08,04,usb,yes,27,30 2006.197.07:40:52.94/vblo/01,632.99,yes,locked 2006.197.07:40:52.94/vblo/02,640.99,yes,locked 2006.197.07:40:52.94/vblo/03,656.99,yes,locked 2006.197.07:40:52.94/vblo/04,712.99,yes,locked 2006.197.07:40:52.94/vblo/05,744.99,yes,locked 2006.197.07:40:52.94/vblo/06,752.99,yes,locked 2006.197.07:40:52.94/vblo/07,734.99,yes,locked 2006.197.07:40:52.94/vblo/08,744.99,yes,locked 2006.197.07:40:53.09/vabw/8 2006.197.07:40:53.24/vbbw/8 2006.197.07:40:53.33/xfe/off,on,15.0 2006.197.07:40:53.71/ifatt/23,28,28,28 2006.197.07:40:54.10/fmout-gps/S +2.97E-07 2006.197.07:40:54.14:!2006.197.07:41:50 2006.197.07:41:50.00:data_valid=off 2006.197.07:41:50.00:postob 2006.197.07:41:50.13/cable/+6.3701E-03 2006.197.07:41:50.13/wx/25.85,1003.2,96 2006.197.07:41:51.10/fmout-gps/S +2.99E-07 2006.197.07:41:51.10:scan_name=197-0743,k06197,170 2006.197.07:41:51.10:source=0808+019,081126.71,014652.2,2000.0,ccw 2006.197.07:41:51.14#flagr#flagr/antenna,new-source 2006.197.07:41:52.14:checkk5 2006.197.07:41:52.47/chk_autoobs//k5ts1/ autoobs is running! 2006.197.07:41:52.81/chk_autoobs//k5ts2/ autoobs is running! 2006.197.07:41:53.15/chk_autoobs//k5ts3/ autoobs is running! 2006.197.07:41:53.50/chk_autoobs//k5ts4/ autoobs is running! 2006.197.07:41:53.84/chk_obsdata//k5ts1/T1970740??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.07:41:54.18/chk_obsdata//k5ts2/T1970740??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.07:41:54.52/chk_obsdata//k5ts3/T1970740??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.07:41:54.85/chk_obsdata//k5ts4/T1970740??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.07:41:55.52/k5log//k5ts1_log_newline 2006.197.07:41:56.18/k5log//k5ts2_log_newline 2006.197.07:41:56.85/k5log//k5ts3_log_newline 2006.197.07:41:57.50/k5log//k5ts4_log_newline 2006.197.07:41:57.52/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.197.07:41:57.52:4f8m12a=1 2006.197.07:41:57.52$4f8m12a/echo=on 2006.197.07:41:57.52$4f8m12a/pcalon 2006.197.07:41:57.52$pcalon/"no phase cal control is implemented here 2006.197.07:41:57.52$4f8m12a/"tpicd=stop 2006.197.07:41:57.52$4f8m12a/vc4f8 2006.197.07:41:57.52$vc4f8/valo=1,532.99 2006.197.07:41:57.53#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.197.07:41:57.53#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.197.07:41:57.53#ibcon#ireg 17 cls_cnt 0 2006.197.07:41:57.53#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.197.07:41:57.53#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.197.07:41:57.53#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.197.07:41:57.53#ibcon#enter wrdev, iclass 26, count 0 2006.197.07:41:57.53#ibcon#first serial, iclass 26, count 0 2006.197.07:41:57.53#ibcon#enter sib2, iclass 26, count 0 2006.197.07:41:57.53#ibcon#flushed, iclass 26, count 0 2006.197.07:41:57.53#ibcon#about to write, iclass 26, count 0 2006.197.07:41:57.53#ibcon#wrote, iclass 26, count 0 2006.197.07:41:57.53#ibcon#about to read 3, iclass 26, count 0 2006.197.07:41:57.55#ibcon#read 3, iclass 26, count 0 2006.197.07:41:57.55#ibcon#about to read 4, iclass 26, count 0 2006.197.07:41:57.55#ibcon#read 4, iclass 26, count 0 2006.197.07:41:57.55#ibcon#about to read 5, iclass 26, count 0 2006.197.07:41:57.55#ibcon#read 5, iclass 26, count 0 2006.197.07:41:57.55#ibcon#about to read 6, iclass 26, count 0 2006.197.07:41:57.55#ibcon#read 6, iclass 26, count 0 2006.197.07:41:57.55#ibcon#end of sib2, iclass 26, count 0 2006.197.07:41:57.55#ibcon#*mode == 0, iclass 26, count 0 2006.197.07:41:57.55#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.197.07:41:57.55#ibcon#[26=FRQ=01,532.99\r\n] 2006.197.07:41:57.55#ibcon#*before write, iclass 26, count 0 2006.197.07:41:57.55#ibcon#enter sib2, iclass 26, count 0 2006.197.07:41:57.55#ibcon#flushed, iclass 26, count 0 2006.197.07:41:57.55#ibcon#about to write, iclass 26, count 0 2006.197.07:41:57.55#ibcon#wrote, iclass 26, count 0 2006.197.07:41:57.55#ibcon#about to read 3, iclass 26, count 0 2006.197.07:41:57.60#ibcon#read 3, iclass 26, count 0 2006.197.07:41:57.60#ibcon#about to read 4, iclass 26, count 0 2006.197.07:41:57.60#ibcon#read 4, iclass 26, count 0 2006.197.07:41:57.60#ibcon#about to read 5, iclass 26, count 0 2006.197.07:41:57.60#ibcon#read 5, iclass 26, count 0 2006.197.07:41:57.60#ibcon#about to read 6, iclass 26, count 0 2006.197.07:41:57.60#ibcon#read 6, iclass 26, count 0 2006.197.07:41:57.60#ibcon#end of sib2, iclass 26, count 0 2006.197.07:41:57.60#ibcon#*after write, iclass 26, count 0 2006.197.07:41:57.60#ibcon#*before return 0, iclass 26, count 0 2006.197.07:41:57.60#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.197.07:41:57.60#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.197.07:41:57.60#ibcon#about to clear, iclass 26 cls_cnt 0 2006.197.07:41:57.60#ibcon#cleared, iclass 26 cls_cnt 0 2006.197.07:41:57.60$vc4f8/va=1,8 2006.197.07:41:57.60#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.197.07:41:57.60#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.197.07:41:57.60#ibcon#ireg 11 cls_cnt 2 2006.197.07:41:57.60#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.197.07:41:57.60#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.197.07:41:57.60#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.197.07:41:57.60#ibcon#enter wrdev, iclass 28, count 2 2006.197.07:41:57.60#ibcon#first serial, iclass 28, count 2 2006.197.07:41:57.60#ibcon#enter sib2, iclass 28, count 2 2006.197.07:41:57.60#ibcon#flushed, iclass 28, count 2 2006.197.07:41:57.60#ibcon#about to write, iclass 28, count 2 2006.197.07:41:57.60#ibcon#wrote, iclass 28, count 2 2006.197.07:41:57.60#ibcon#about to read 3, iclass 28, count 2 2006.197.07:41:57.62#ibcon#read 3, iclass 28, count 2 2006.197.07:41:57.62#ibcon#about to read 4, iclass 28, count 2 2006.197.07:41:57.62#ibcon#read 4, iclass 28, count 2 2006.197.07:41:57.62#ibcon#about to read 5, iclass 28, count 2 2006.197.07:41:57.62#ibcon#read 5, iclass 28, count 2 2006.197.07:41:57.62#ibcon#about to read 6, iclass 28, count 2 2006.197.07:41:57.62#ibcon#read 6, iclass 28, count 2 2006.197.07:41:57.62#ibcon#end of sib2, iclass 28, count 2 2006.197.07:41:57.62#ibcon#*mode == 0, iclass 28, count 2 2006.197.07:41:57.62#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.197.07:41:57.62#ibcon#[25=AT01-08\r\n] 2006.197.07:41:57.62#ibcon#*before write, iclass 28, count 2 2006.197.07:41:57.62#ibcon#enter sib2, iclass 28, count 2 2006.197.07:41:57.62#ibcon#flushed, iclass 28, count 2 2006.197.07:41:57.62#ibcon#about to write, iclass 28, count 2 2006.197.07:41:57.62#ibcon#wrote, iclass 28, count 2 2006.197.07:41:57.62#ibcon#about to read 3, iclass 28, count 2 2006.197.07:41:57.65#ibcon#read 3, iclass 28, count 2 2006.197.07:41:57.65#ibcon#about to read 4, iclass 28, count 2 2006.197.07:41:57.65#ibcon#read 4, iclass 28, count 2 2006.197.07:41:57.65#ibcon#about to read 5, iclass 28, count 2 2006.197.07:41:57.65#ibcon#read 5, iclass 28, count 2 2006.197.07:41:57.65#ibcon#about to read 6, iclass 28, count 2 2006.197.07:41:57.65#ibcon#read 6, iclass 28, count 2 2006.197.07:41:57.65#ibcon#end of sib2, iclass 28, count 2 2006.197.07:41:57.65#ibcon#*after write, iclass 28, count 2 2006.197.07:41:57.65#ibcon#*before return 0, iclass 28, count 2 2006.197.07:41:57.65#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.197.07:41:57.65#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.197.07:41:57.65#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.197.07:41:57.65#ibcon#ireg 7 cls_cnt 0 2006.197.07:41:57.65#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.197.07:41:57.77#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.197.07:41:57.77#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.197.07:41:57.77#ibcon#enter wrdev, iclass 28, count 0 2006.197.07:41:57.77#ibcon#first serial, iclass 28, count 0 2006.197.07:41:57.77#ibcon#enter sib2, iclass 28, count 0 2006.197.07:41:57.77#ibcon#flushed, iclass 28, count 0 2006.197.07:41:57.77#ibcon#about to write, iclass 28, count 0 2006.197.07:41:57.77#ibcon#wrote, iclass 28, count 0 2006.197.07:41:57.77#ibcon#about to read 3, iclass 28, count 0 2006.197.07:41:57.79#ibcon#read 3, iclass 28, count 0 2006.197.07:41:57.79#ibcon#about to read 4, iclass 28, count 0 2006.197.07:41:57.79#ibcon#read 4, iclass 28, count 0 2006.197.07:41:57.79#ibcon#about to read 5, iclass 28, count 0 2006.197.07:41:57.79#ibcon#read 5, iclass 28, count 0 2006.197.07:41:57.79#ibcon#about to read 6, iclass 28, count 0 2006.197.07:41:57.79#ibcon#read 6, iclass 28, count 0 2006.197.07:41:57.79#ibcon#end of sib2, iclass 28, count 0 2006.197.07:41:57.79#ibcon#*mode == 0, iclass 28, count 0 2006.197.07:41:57.79#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.197.07:41:57.79#ibcon#[25=USB\r\n] 2006.197.07:41:57.79#ibcon#*before write, iclass 28, count 0 2006.197.07:41:57.79#ibcon#enter sib2, iclass 28, count 0 2006.197.07:41:57.79#ibcon#flushed, iclass 28, count 0 2006.197.07:41:57.79#ibcon#about to write, iclass 28, count 0 2006.197.07:41:57.79#ibcon#wrote, iclass 28, count 0 2006.197.07:41:57.79#ibcon#about to read 3, iclass 28, count 0 2006.197.07:41:57.82#ibcon#read 3, iclass 28, count 0 2006.197.07:41:57.82#ibcon#about to read 4, iclass 28, count 0 2006.197.07:41:57.82#ibcon#read 4, iclass 28, count 0 2006.197.07:41:57.82#ibcon#about to read 5, iclass 28, count 0 2006.197.07:41:57.82#ibcon#read 5, iclass 28, count 0 2006.197.07:41:57.82#ibcon#about to read 6, iclass 28, count 0 2006.197.07:41:57.82#ibcon#read 6, iclass 28, count 0 2006.197.07:41:57.82#ibcon#end of sib2, iclass 28, count 0 2006.197.07:41:57.82#ibcon#*after write, iclass 28, count 0 2006.197.07:41:57.82#ibcon#*before return 0, iclass 28, count 0 2006.197.07:41:57.82#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.197.07:41:57.82#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.197.07:41:57.82#ibcon#about to clear, iclass 28 cls_cnt 0 2006.197.07:41:57.82#ibcon#cleared, iclass 28 cls_cnt 0 2006.197.07:41:57.82$vc4f8/valo=2,572.99 2006.197.07:41:57.82#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.197.07:41:57.82#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.197.07:41:57.82#ibcon#ireg 17 cls_cnt 0 2006.197.07:41:57.82#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.197.07:41:57.82#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.197.07:41:57.82#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.197.07:41:57.82#ibcon#enter wrdev, iclass 30, count 0 2006.197.07:41:57.82#ibcon#first serial, iclass 30, count 0 2006.197.07:41:57.82#ibcon#enter sib2, iclass 30, count 0 2006.197.07:41:57.82#ibcon#flushed, iclass 30, count 0 2006.197.07:41:57.82#ibcon#about to write, iclass 30, count 0 2006.197.07:41:57.82#ibcon#wrote, iclass 30, count 0 2006.197.07:41:57.82#ibcon#about to read 3, iclass 30, count 0 2006.197.07:41:57.84#ibcon#read 3, iclass 30, count 0 2006.197.07:41:57.84#ibcon#about to read 4, iclass 30, count 0 2006.197.07:41:57.84#ibcon#read 4, iclass 30, count 0 2006.197.07:41:57.84#ibcon#about to read 5, iclass 30, count 0 2006.197.07:41:57.84#ibcon#read 5, iclass 30, count 0 2006.197.07:41:57.84#ibcon#about to read 6, iclass 30, count 0 2006.197.07:41:57.84#ibcon#read 6, iclass 30, count 0 2006.197.07:41:57.84#ibcon#end of sib2, iclass 30, count 0 2006.197.07:41:57.84#ibcon#*mode == 0, iclass 30, count 0 2006.197.07:41:57.84#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.197.07:41:57.84#ibcon#[26=FRQ=02,572.99\r\n] 2006.197.07:41:57.84#ibcon#*before write, iclass 30, count 0 2006.197.07:41:57.84#ibcon#enter sib2, iclass 30, count 0 2006.197.07:41:57.84#ibcon#flushed, iclass 30, count 0 2006.197.07:41:57.84#ibcon#about to write, iclass 30, count 0 2006.197.07:41:57.84#ibcon#wrote, iclass 30, count 0 2006.197.07:41:57.84#ibcon#about to read 3, iclass 30, count 0 2006.197.07:41:57.88#ibcon#read 3, iclass 30, count 0 2006.197.07:41:57.88#ibcon#about to read 4, iclass 30, count 0 2006.197.07:41:57.88#ibcon#read 4, iclass 30, count 0 2006.197.07:41:57.88#ibcon#about to read 5, iclass 30, count 0 2006.197.07:41:57.88#ibcon#read 5, iclass 30, count 0 2006.197.07:41:57.88#ibcon#about to read 6, iclass 30, count 0 2006.197.07:41:57.88#ibcon#read 6, iclass 30, count 0 2006.197.07:41:57.88#ibcon#end of sib2, iclass 30, count 0 2006.197.07:41:57.88#ibcon#*after write, iclass 30, count 0 2006.197.07:41:57.88#ibcon#*before return 0, iclass 30, count 0 2006.197.07:41:57.88#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.197.07:41:57.88#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.197.07:41:57.88#ibcon#about to clear, iclass 30 cls_cnt 0 2006.197.07:41:57.88#ibcon#cleared, iclass 30 cls_cnt 0 2006.197.07:41:57.88$vc4f8/va=2,7 2006.197.07:41:57.88#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.197.07:41:57.88#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.197.07:41:57.88#ibcon#ireg 11 cls_cnt 2 2006.197.07:41:57.88#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.197.07:41:57.94#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.197.07:41:57.94#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.197.07:41:57.94#ibcon#enter wrdev, iclass 32, count 2 2006.197.07:41:57.94#ibcon#first serial, iclass 32, count 2 2006.197.07:41:57.94#ibcon#enter sib2, iclass 32, count 2 2006.197.07:41:57.94#ibcon#flushed, iclass 32, count 2 2006.197.07:41:57.94#ibcon#about to write, iclass 32, count 2 2006.197.07:41:57.94#ibcon#wrote, iclass 32, count 2 2006.197.07:41:57.94#ibcon#about to read 3, iclass 32, count 2 2006.197.07:41:57.96#ibcon#read 3, iclass 32, count 2 2006.197.07:41:57.96#ibcon#about to read 4, iclass 32, count 2 2006.197.07:41:57.96#ibcon#read 4, iclass 32, count 2 2006.197.07:41:57.96#ibcon#about to read 5, iclass 32, count 2 2006.197.07:41:57.96#ibcon#read 5, iclass 32, count 2 2006.197.07:41:57.96#ibcon#about to read 6, iclass 32, count 2 2006.197.07:41:57.96#ibcon#read 6, iclass 32, count 2 2006.197.07:41:57.96#ibcon#end of sib2, iclass 32, count 2 2006.197.07:41:57.96#ibcon#*mode == 0, iclass 32, count 2 2006.197.07:41:57.96#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.197.07:41:57.96#ibcon#[25=AT02-07\r\n] 2006.197.07:41:57.96#ibcon#*before write, iclass 32, count 2 2006.197.07:41:57.96#ibcon#enter sib2, iclass 32, count 2 2006.197.07:41:57.96#ibcon#flushed, iclass 32, count 2 2006.197.07:41:57.96#ibcon#about to write, iclass 32, count 2 2006.197.07:41:57.96#ibcon#wrote, iclass 32, count 2 2006.197.07:41:57.96#ibcon#about to read 3, iclass 32, count 2 2006.197.07:41:57.99#ibcon#read 3, iclass 32, count 2 2006.197.07:41:57.99#ibcon#about to read 4, iclass 32, count 2 2006.197.07:41:57.99#ibcon#read 4, iclass 32, count 2 2006.197.07:41:57.99#ibcon#about to read 5, iclass 32, count 2 2006.197.07:41:57.99#ibcon#read 5, iclass 32, count 2 2006.197.07:41:57.99#ibcon#about to read 6, iclass 32, count 2 2006.197.07:41:57.99#ibcon#read 6, iclass 32, count 2 2006.197.07:41:57.99#ibcon#end of sib2, iclass 32, count 2 2006.197.07:41:57.99#ibcon#*after write, iclass 32, count 2 2006.197.07:41:57.99#ibcon#*before return 0, iclass 32, count 2 2006.197.07:41:57.99#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.197.07:41:57.99#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.197.07:41:57.99#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.197.07:41:57.99#ibcon#ireg 7 cls_cnt 0 2006.197.07:41:57.99#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.197.07:41:58.11#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.197.07:41:58.11#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.197.07:41:58.11#ibcon#enter wrdev, iclass 32, count 0 2006.197.07:41:58.11#ibcon#first serial, iclass 32, count 0 2006.197.07:41:58.11#ibcon#enter sib2, iclass 32, count 0 2006.197.07:41:58.11#ibcon#flushed, iclass 32, count 0 2006.197.07:41:58.11#ibcon#about to write, iclass 32, count 0 2006.197.07:41:58.11#ibcon#wrote, iclass 32, count 0 2006.197.07:41:58.11#ibcon#about to read 3, iclass 32, count 0 2006.197.07:41:58.13#ibcon#read 3, iclass 32, count 0 2006.197.07:41:58.13#ibcon#about to read 4, iclass 32, count 0 2006.197.07:41:58.13#ibcon#read 4, iclass 32, count 0 2006.197.07:41:58.13#ibcon#about to read 5, iclass 32, count 0 2006.197.07:41:58.13#ibcon#read 5, iclass 32, count 0 2006.197.07:41:58.13#ibcon#about to read 6, iclass 32, count 0 2006.197.07:41:58.13#ibcon#read 6, iclass 32, count 0 2006.197.07:41:58.13#ibcon#end of sib2, iclass 32, count 0 2006.197.07:41:58.13#ibcon#*mode == 0, iclass 32, count 0 2006.197.07:41:58.13#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.197.07:41:58.13#ibcon#[25=USB\r\n] 2006.197.07:41:58.13#ibcon#*before write, iclass 32, count 0 2006.197.07:41:58.13#ibcon#enter sib2, iclass 32, count 0 2006.197.07:41:58.13#ibcon#flushed, iclass 32, count 0 2006.197.07:41:58.13#ibcon#about to write, iclass 32, count 0 2006.197.07:41:58.13#ibcon#wrote, iclass 32, count 0 2006.197.07:41:58.13#ibcon#about to read 3, iclass 32, count 0 2006.197.07:41:58.16#ibcon#read 3, iclass 32, count 0 2006.197.07:41:58.16#ibcon#about to read 4, iclass 32, count 0 2006.197.07:41:58.16#ibcon#read 4, iclass 32, count 0 2006.197.07:41:58.16#ibcon#about to read 5, iclass 32, count 0 2006.197.07:41:58.16#ibcon#read 5, iclass 32, count 0 2006.197.07:41:58.16#ibcon#about to read 6, iclass 32, count 0 2006.197.07:41:58.16#ibcon#read 6, iclass 32, count 0 2006.197.07:41:58.16#ibcon#end of sib2, iclass 32, count 0 2006.197.07:41:58.16#ibcon#*after write, iclass 32, count 0 2006.197.07:41:58.16#ibcon#*before return 0, iclass 32, count 0 2006.197.07:41:58.16#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.197.07:41:58.16#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.197.07:41:58.16#ibcon#about to clear, iclass 32 cls_cnt 0 2006.197.07:41:58.16#ibcon#cleared, iclass 32 cls_cnt 0 2006.197.07:41:58.16$vc4f8/valo=3,672.99 2006.197.07:41:58.16#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.197.07:41:58.16#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.197.07:41:58.16#ibcon#ireg 17 cls_cnt 0 2006.197.07:41:58.16#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.197.07:41:58.16#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.197.07:41:58.16#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.197.07:41:58.16#ibcon#enter wrdev, iclass 34, count 0 2006.197.07:41:58.16#ibcon#first serial, iclass 34, count 0 2006.197.07:41:58.16#ibcon#enter sib2, iclass 34, count 0 2006.197.07:41:58.16#ibcon#flushed, iclass 34, count 0 2006.197.07:41:58.16#ibcon#about to write, iclass 34, count 0 2006.197.07:41:58.16#ibcon#wrote, iclass 34, count 0 2006.197.07:41:58.16#ibcon#about to read 3, iclass 34, count 0 2006.197.07:41:58.18#ibcon#read 3, iclass 34, count 0 2006.197.07:41:58.18#ibcon#about to read 4, iclass 34, count 0 2006.197.07:41:58.18#ibcon#read 4, iclass 34, count 0 2006.197.07:41:58.18#ibcon#about to read 5, iclass 34, count 0 2006.197.07:41:58.18#ibcon#read 5, iclass 34, count 0 2006.197.07:41:58.18#ibcon#about to read 6, iclass 34, count 0 2006.197.07:41:58.18#ibcon#read 6, iclass 34, count 0 2006.197.07:41:58.18#ibcon#end of sib2, iclass 34, count 0 2006.197.07:41:58.18#ibcon#*mode == 0, iclass 34, count 0 2006.197.07:41:58.18#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.197.07:41:58.18#ibcon#[26=FRQ=03,672.99\r\n] 2006.197.07:41:58.18#ibcon#*before write, iclass 34, count 0 2006.197.07:41:58.18#ibcon#enter sib2, iclass 34, count 0 2006.197.07:41:58.18#ibcon#flushed, iclass 34, count 0 2006.197.07:41:58.18#ibcon#about to write, iclass 34, count 0 2006.197.07:41:58.18#ibcon#wrote, iclass 34, count 0 2006.197.07:41:58.18#ibcon#about to read 3, iclass 34, count 0 2006.197.07:41:58.22#ibcon#read 3, iclass 34, count 0 2006.197.07:41:58.22#ibcon#about to read 4, iclass 34, count 0 2006.197.07:41:58.22#ibcon#read 4, iclass 34, count 0 2006.197.07:41:58.22#ibcon#about to read 5, iclass 34, count 0 2006.197.07:41:58.22#ibcon#read 5, iclass 34, count 0 2006.197.07:41:58.22#ibcon#about to read 6, iclass 34, count 0 2006.197.07:41:58.22#ibcon#read 6, iclass 34, count 0 2006.197.07:41:58.22#ibcon#end of sib2, iclass 34, count 0 2006.197.07:41:58.22#ibcon#*after write, iclass 34, count 0 2006.197.07:41:58.22#ibcon#*before return 0, iclass 34, count 0 2006.197.07:41:58.22#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.197.07:41:58.22#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.197.07:41:58.22#ibcon#about to clear, iclass 34 cls_cnt 0 2006.197.07:41:58.22#ibcon#cleared, iclass 34 cls_cnt 0 2006.197.07:41:58.22$vc4f8/va=3,6 2006.197.07:41:58.22#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.197.07:41:58.22#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.197.07:41:58.22#ibcon#ireg 11 cls_cnt 2 2006.197.07:41:58.22#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.197.07:41:58.28#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.197.07:41:58.28#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.197.07:41:58.28#ibcon#enter wrdev, iclass 36, count 2 2006.197.07:41:58.28#ibcon#first serial, iclass 36, count 2 2006.197.07:41:58.28#ibcon#enter sib2, iclass 36, count 2 2006.197.07:41:58.28#ibcon#flushed, iclass 36, count 2 2006.197.07:41:58.28#ibcon#about to write, iclass 36, count 2 2006.197.07:41:58.28#ibcon#wrote, iclass 36, count 2 2006.197.07:41:58.28#ibcon#about to read 3, iclass 36, count 2 2006.197.07:41:58.30#ibcon#read 3, iclass 36, count 2 2006.197.07:41:58.30#ibcon#about to read 4, iclass 36, count 2 2006.197.07:41:58.30#ibcon#read 4, iclass 36, count 2 2006.197.07:41:58.30#ibcon#about to read 5, iclass 36, count 2 2006.197.07:41:58.30#ibcon#read 5, iclass 36, count 2 2006.197.07:41:58.30#ibcon#about to read 6, iclass 36, count 2 2006.197.07:41:58.30#ibcon#read 6, iclass 36, count 2 2006.197.07:41:58.30#ibcon#end of sib2, iclass 36, count 2 2006.197.07:41:58.30#ibcon#*mode == 0, iclass 36, count 2 2006.197.07:41:58.30#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.197.07:41:58.30#ibcon#[25=AT03-06\r\n] 2006.197.07:41:58.30#ibcon#*before write, iclass 36, count 2 2006.197.07:41:58.30#ibcon#enter sib2, iclass 36, count 2 2006.197.07:41:58.30#ibcon#flushed, iclass 36, count 2 2006.197.07:41:58.30#ibcon#about to write, iclass 36, count 2 2006.197.07:41:58.30#ibcon#wrote, iclass 36, count 2 2006.197.07:41:58.30#ibcon#about to read 3, iclass 36, count 2 2006.197.07:41:58.33#ibcon#read 3, iclass 36, count 2 2006.197.07:41:58.33#ibcon#about to read 4, iclass 36, count 2 2006.197.07:41:58.33#ibcon#read 4, iclass 36, count 2 2006.197.07:41:58.33#ibcon#about to read 5, iclass 36, count 2 2006.197.07:41:58.33#ibcon#read 5, iclass 36, count 2 2006.197.07:41:58.33#ibcon#about to read 6, iclass 36, count 2 2006.197.07:41:58.33#ibcon#read 6, iclass 36, count 2 2006.197.07:41:58.33#ibcon#end of sib2, iclass 36, count 2 2006.197.07:41:58.33#ibcon#*after write, iclass 36, count 2 2006.197.07:41:58.33#ibcon#*before return 0, iclass 36, count 2 2006.197.07:41:58.33#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.197.07:41:58.33#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.197.07:41:58.33#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.197.07:41:58.33#ibcon#ireg 7 cls_cnt 0 2006.197.07:41:58.33#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.197.07:41:58.45#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.197.07:41:58.45#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.197.07:41:58.45#ibcon#enter wrdev, iclass 36, count 0 2006.197.07:41:58.45#ibcon#first serial, iclass 36, count 0 2006.197.07:41:58.45#ibcon#enter sib2, iclass 36, count 0 2006.197.07:41:58.45#ibcon#flushed, iclass 36, count 0 2006.197.07:41:58.45#ibcon#about to write, iclass 36, count 0 2006.197.07:41:58.45#ibcon#wrote, iclass 36, count 0 2006.197.07:41:58.45#ibcon#about to read 3, iclass 36, count 0 2006.197.07:41:58.47#ibcon#read 3, iclass 36, count 0 2006.197.07:41:58.47#ibcon#about to read 4, iclass 36, count 0 2006.197.07:41:58.47#ibcon#read 4, iclass 36, count 0 2006.197.07:41:58.47#ibcon#about to read 5, iclass 36, count 0 2006.197.07:41:58.47#ibcon#read 5, iclass 36, count 0 2006.197.07:41:58.47#ibcon#about to read 6, iclass 36, count 0 2006.197.07:41:58.47#ibcon#read 6, iclass 36, count 0 2006.197.07:41:58.47#ibcon#end of sib2, iclass 36, count 0 2006.197.07:41:58.47#ibcon#*mode == 0, iclass 36, count 0 2006.197.07:41:58.47#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.197.07:41:58.47#ibcon#[25=USB\r\n] 2006.197.07:41:58.47#ibcon#*before write, iclass 36, count 0 2006.197.07:41:58.47#ibcon#enter sib2, iclass 36, count 0 2006.197.07:41:58.47#ibcon#flushed, iclass 36, count 0 2006.197.07:41:58.47#ibcon#about to write, iclass 36, count 0 2006.197.07:41:58.47#ibcon#wrote, iclass 36, count 0 2006.197.07:41:58.47#ibcon#about to read 3, iclass 36, count 0 2006.197.07:41:58.50#ibcon#read 3, iclass 36, count 0 2006.197.07:41:58.50#ibcon#about to read 4, iclass 36, count 0 2006.197.07:41:58.50#ibcon#read 4, iclass 36, count 0 2006.197.07:41:58.50#ibcon#about to read 5, iclass 36, count 0 2006.197.07:41:58.50#ibcon#read 5, iclass 36, count 0 2006.197.07:41:58.50#ibcon#about to read 6, iclass 36, count 0 2006.197.07:41:58.50#ibcon#read 6, iclass 36, count 0 2006.197.07:41:58.50#ibcon#end of sib2, iclass 36, count 0 2006.197.07:41:58.50#ibcon#*after write, iclass 36, count 0 2006.197.07:41:58.50#ibcon#*before return 0, iclass 36, count 0 2006.197.07:41:58.50#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.197.07:41:58.50#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.197.07:41:58.50#ibcon#about to clear, iclass 36 cls_cnt 0 2006.197.07:41:58.50#ibcon#cleared, iclass 36 cls_cnt 0 2006.197.07:41:58.50$vc4f8/valo=4,832.99 2006.197.07:41:58.50#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.197.07:41:58.50#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.197.07:41:58.50#ibcon#ireg 17 cls_cnt 0 2006.197.07:41:58.50#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.197.07:41:58.50#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.197.07:41:58.50#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.197.07:41:58.50#ibcon#enter wrdev, iclass 38, count 0 2006.197.07:41:58.50#ibcon#first serial, iclass 38, count 0 2006.197.07:41:58.50#ibcon#enter sib2, iclass 38, count 0 2006.197.07:41:58.50#ibcon#flushed, iclass 38, count 0 2006.197.07:41:58.50#ibcon#about to write, iclass 38, count 0 2006.197.07:41:58.50#ibcon#wrote, iclass 38, count 0 2006.197.07:41:58.50#ibcon#about to read 3, iclass 38, count 0 2006.197.07:41:58.52#ibcon#read 3, iclass 38, count 0 2006.197.07:41:58.52#ibcon#about to read 4, iclass 38, count 0 2006.197.07:41:58.52#ibcon#read 4, iclass 38, count 0 2006.197.07:41:58.52#ibcon#about to read 5, iclass 38, count 0 2006.197.07:41:58.52#ibcon#read 5, iclass 38, count 0 2006.197.07:41:58.52#ibcon#about to read 6, iclass 38, count 0 2006.197.07:41:58.52#ibcon#read 6, iclass 38, count 0 2006.197.07:41:58.52#ibcon#end of sib2, iclass 38, count 0 2006.197.07:41:58.52#ibcon#*mode == 0, iclass 38, count 0 2006.197.07:41:58.52#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.197.07:41:58.52#ibcon#[26=FRQ=04,832.99\r\n] 2006.197.07:41:58.52#ibcon#*before write, iclass 38, count 0 2006.197.07:41:58.52#ibcon#enter sib2, iclass 38, count 0 2006.197.07:41:58.52#ibcon#flushed, iclass 38, count 0 2006.197.07:41:58.52#ibcon#about to write, iclass 38, count 0 2006.197.07:41:58.52#ibcon#wrote, iclass 38, count 0 2006.197.07:41:58.52#ibcon#about to read 3, iclass 38, count 0 2006.197.07:41:58.56#ibcon#read 3, iclass 38, count 0 2006.197.07:41:58.56#ibcon#about to read 4, iclass 38, count 0 2006.197.07:41:58.56#ibcon#read 4, iclass 38, count 0 2006.197.07:41:58.56#ibcon#about to read 5, iclass 38, count 0 2006.197.07:41:58.56#ibcon#read 5, iclass 38, count 0 2006.197.07:41:58.56#ibcon#about to read 6, iclass 38, count 0 2006.197.07:41:58.56#ibcon#read 6, iclass 38, count 0 2006.197.07:41:58.56#ibcon#end of sib2, iclass 38, count 0 2006.197.07:41:58.56#ibcon#*after write, iclass 38, count 0 2006.197.07:41:58.56#ibcon#*before return 0, iclass 38, count 0 2006.197.07:41:58.56#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.197.07:41:58.56#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.197.07:41:58.56#ibcon#about to clear, iclass 38 cls_cnt 0 2006.197.07:41:58.56#ibcon#cleared, iclass 38 cls_cnt 0 2006.197.07:41:58.56$vc4f8/va=4,7 2006.197.07:41:58.56#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.197.07:41:58.56#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.197.07:41:58.56#ibcon#ireg 11 cls_cnt 2 2006.197.07:41:58.56#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.197.07:41:58.62#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.197.07:41:58.62#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.197.07:41:58.62#ibcon#enter wrdev, iclass 40, count 2 2006.197.07:41:58.62#ibcon#first serial, iclass 40, count 2 2006.197.07:41:58.62#ibcon#enter sib2, iclass 40, count 2 2006.197.07:41:58.62#ibcon#flushed, iclass 40, count 2 2006.197.07:41:58.62#ibcon#about to write, iclass 40, count 2 2006.197.07:41:58.62#ibcon#wrote, iclass 40, count 2 2006.197.07:41:58.62#ibcon#about to read 3, iclass 40, count 2 2006.197.07:41:58.64#ibcon#read 3, iclass 40, count 2 2006.197.07:41:58.64#ibcon#about to read 4, iclass 40, count 2 2006.197.07:41:58.64#ibcon#read 4, iclass 40, count 2 2006.197.07:41:58.64#ibcon#about to read 5, iclass 40, count 2 2006.197.07:41:58.64#ibcon#read 5, iclass 40, count 2 2006.197.07:41:58.64#ibcon#about to read 6, iclass 40, count 2 2006.197.07:41:58.64#ibcon#read 6, iclass 40, count 2 2006.197.07:41:58.64#ibcon#end of sib2, iclass 40, count 2 2006.197.07:41:58.64#ibcon#*mode == 0, iclass 40, count 2 2006.197.07:41:58.64#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.197.07:41:58.64#ibcon#[25=AT04-07\r\n] 2006.197.07:41:58.64#ibcon#*before write, iclass 40, count 2 2006.197.07:41:58.64#ibcon#enter sib2, iclass 40, count 2 2006.197.07:41:58.64#ibcon#flushed, iclass 40, count 2 2006.197.07:41:58.64#ibcon#about to write, iclass 40, count 2 2006.197.07:41:58.64#ibcon#wrote, iclass 40, count 2 2006.197.07:41:58.64#ibcon#about to read 3, iclass 40, count 2 2006.197.07:41:58.67#ibcon#read 3, iclass 40, count 2 2006.197.07:41:58.67#ibcon#about to read 4, iclass 40, count 2 2006.197.07:41:58.67#ibcon#read 4, iclass 40, count 2 2006.197.07:41:58.67#ibcon#about to read 5, iclass 40, count 2 2006.197.07:41:58.67#ibcon#read 5, iclass 40, count 2 2006.197.07:41:58.67#ibcon#about to read 6, iclass 40, count 2 2006.197.07:41:58.67#ibcon#read 6, iclass 40, count 2 2006.197.07:41:58.67#ibcon#end of sib2, iclass 40, count 2 2006.197.07:41:58.67#ibcon#*after write, iclass 40, count 2 2006.197.07:41:58.67#ibcon#*before return 0, iclass 40, count 2 2006.197.07:41:58.67#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.197.07:41:58.67#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.197.07:41:58.67#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.197.07:41:58.67#ibcon#ireg 7 cls_cnt 0 2006.197.07:41:58.67#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.197.07:41:58.79#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.197.07:41:58.79#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.197.07:41:58.79#ibcon#enter wrdev, iclass 40, count 0 2006.197.07:41:58.79#ibcon#first serial, iclass 40, count 0 2006.197.07:41:58.79#ibcon#enter sib2, iclass 40, count 0 2006.197.07:41:58.79#ibcon#flushed, iclass 40, count 0 2006.197.07:41:58.79#ibcon#about to write, iclass 40, count 0 2006.197.07:41:58.79#ibcon#wrote, iclass 40, count 0 2006.197.07:41:58.79#ibcon#about to read 3, iclass 40, count 0 2006.197.07:41:58.81#ibcon#read 3, iclass 40, count 0 2006.197.07:41:58.81#ibcon#about to read 4, iclass 40, count 0 2006.197.07:41:58.81#ibcon#read 4, iclass 40, count 0 2006.197.07:41:58.81#ibcon#about to read 5, iclass 40, count 0 2006.197.07:41:58.81#ibcon#read 5, iclass 40, count 0 2006.197.07:41:58.81#ibcon#about to read 6, iclass 40, count 0 2006.197.07:41:58.81#ibcon#read 6, iclass 40, count 0 2006.197.07:41:58.81#ibcon#end of sib2, iclass 40, count 0 2006.197.07:41:58.81#ibcon#*mode == 0, iclass 40, count 0 2006.197.07:41:58.81#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.197.07:41:58.81#ibcon#[25=USB\r\n] 2006.197.07:41:58.81#ibcon#*before write, iclass 40, count 0 2006.197.07:41:58.81#ibcon#enter sib2, iclass 40, count 0 2006.197.07:41:58.81#ibcon#flushed, iclass 40, count 0 2006.197.07:41:58.81#ibcon#about to write, iclass 40, count 0 2006.197.07:41:58.81#ibcon#wrote, iclass 40, count 0 2006.197.07:41:58.81#ibcon#about to read 3, iclass 40, count 0 2006.197.07:41:58.84#ibcon#read 3, iclass 40, count 0 2006.197.07:41:58.84#ibcon#about to read 4, iclass 40, count 0 2006.197.07:41:58.84#ibcon#read 4, iclass 40, count 0 2006.197.07:41:58.84#ibcon#about to read 5, iclass 40, count 0 2006.197.07:41:58.84#ibcon#read 5, iclass 40, count 0 2006.197.07:41:58.84#ibcon#about to read 6, iclass 40, count 0 2006.197.07:41:58.84#ibcon#read 6, iclass 40, count 0 2006.197.07:41:58.84#ibcon#end of sib2, iclass 40, count 0 2006.197.07:41:58.84#ibcon#*after write, iclass 40, count 0 2006.197.07:41:58.84#ibcon#*before return 0, iclass 40, count 0 2006.197.07:41:58.84#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.197.07:41:58.84#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.197.07:41:58.84#ibcon#about to clear, iclass 40 cls_cnt 0 2006.197.07:41:58.84#ibcon#cleared, iclass 40 cls_cnt 0 2006.197.07:41:58.84$vc4f8/valo=5,652.99 2006.197.07:41:58.84#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.197.07:41:58.84#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.197.07:41:58.84#ibcon#ireg 17 cls_cnt 0 2006.197.07:41:58.84#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.197.07:41:58.84#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.197.07:41:58.84#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.197.07:41:58.84#ibcon#enter wrdev, iclass 4, count 0 2006.197.07:41:58.84#ibcon#first serial, iclass 4, count 0 2006.197.07:41:58.84#ibcon#enter sib2, iclass 4, count 0 2006.197.07:41:58.84#ibcon#flushed, iclass 4, count 0 2006.197.07:41:58.84#ibcon#about to write, iclass 4, count 0 2006.197.07:41:58.84#ibcon#wrote, iclass 4, count 0 2006.197.07:41:58.84#ibcon#about to read 3, iclass 4, count 0 2006.197.07:41:58.86#ibcon#read 3, iclass 4, count 0 2006.197.07:41:58.86#ibcon#about to read 4, iclass 4, count 0 2006.197.07:41:58.86#ibcon#read 4, iclass 4, count 0 2006.197.07:41:58.86#ibcon#about to read 5, iclass 4, count 0 2006.197.07:41:58.86#ibcon#read 5, iclass 4, count 0 2006.197.07:41:58.86#ibcon#about to read 6, iclass 4, count 0 2006.197.07:41:58.86#ibcon#read 6, iclass 4, count 0 2006.197.07:41:58.86#ibcon#end of sib2, iclass 4, count 0 2006.197.07:41:58.86#ibcon#*mode == 0, iclass 4, count 0 2006.197.07:41:58.86#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.197.07:41:58.86#ibcon#[26=FRQ=05,652.99\r\n] 2006.197.07:41:58.86#ibcon#*before write, iclass 4, count 0 2006.197.07:41:58.86#ibcon#enter sib2, iclass 4, count 0 2006.197.07:41:58.86#ibcon#flushed, iclass 4, count 0 2006.197.07:41:58.86#ibcon#about to write, iclass 4, count 0 2006.197.07:41:58.86#ibcon#wrote, iclass 4, count 0 2006.197.07:41:58.86#ibcon#about to read 3, iclass 4, count 0 2006.197.07:41:58.90#ibcon#read 3, iclass 4, count 0 2006.197.07:41:58.90#ibcon#about to read 4, iclass 4, count 0 2006.197.07:41:58.90#ibcon#read 4, iclass 4, count 0 2006.197.07:41:58.90#ibcon#about to read 5, iclass 4, count 0 2006.197.07:41:58.90#ibcon#read 5, iclass 4, count 0 2006.197.07:41:58.90#ibcon#about to read 6, iclass 4, count 0 2006.197.07:41:58.90#ibcon#read 6, iclass 4, count 0 2006.197.07:41:58.90#ibcon#end of sib2, iclass 4, count 0 2006.197.07:41:58.90#ibcon#*after write, iclass 4, count 0 2006.197.07:41:58.90#ibcon#*before return 0, iclass 4, count 0 2006.197.07:41:58.90#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.197.07:41:58.90#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.197.07:41:58.90#ibcon#about to clear, iclass 4 cls_cnt 0 2006.197.07:41:58.90#ibcon#cleared, iclass 4 cls_cnt 0 2006.197.07:41:58.90$vc4f8/va=5,7 2006.197.07:41:58.90#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.197.07:41:58.90#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.197.07:41:58.90#ibcon#ireg 11 cls_cnt 2 2006.197.07:41:58.90#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.197.07:41:58.96#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.197.07:41:58.96#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.197.07:41:58.96#ibcon#enter wrdev, iclass 6, count 2 2006.197.07:41:58.96#ibcon#first serial, iclass 6, count 2 2006.197.07:41:58.96#ibcon#enter sib2, iclass 6, count 2 2006.197.07:41:58.96#ibcon#flushed, iclass 6, count 2 2006.197.07:41:58.96#ibcon#about to write, iclass 6, count 2 2006.197.07:41:58.96#ibcon#wrote, iclass 6, count 2 2006.197.07:41:58.96#ibcon#about to read 3, iclass 6, count 2 2006.197.07:41:58.98#ibcon#read 3, iclass 6, count 2 2006.197.07:41:58.98#ibcon#about to read 4, iclass 6, count 2 2006.197.07:41:58.98#ibcon#read 4, iclass 6, count 2 2006.197.07:41:58.98#ibcon#about to read 5, iclass 6, count 2 2006.197.07:41:58.98#ibcon#read 5, iclass 6, count 2 2006.197.07:41:58.98#ibcon#about to read 6, iclass 6, count 2 2006.197.07:41:58.98#ibcon#read 6, iclass 6, count 2 2006.197.07:41:58.98#ibcon#end of sib2, iclass 6, count 2 2006.197.07:41:58.98#ibcon#*mode == 0, iclass 6, count 2 2006.197.07:41:58.98#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.197.07:41:58.98#ibcon#[25=AT05-07\r\n] 2006.197.07:41:58.98#ibcon#*before write, iclass 6, count 2 2006.197.07:41:58.98#ibcon#enter sib2, iclass 6, count 2 2006.197.07:41:58.98#ibcon#flushed, iclass 6, count 2 2006.197.07:41:58.98#ibcon#about to write, iclass 6, count 2 2006.197.07:41:58.98#ibcon#wrote, iclass 6, count 2 2006.197.07:41:58.98#ibcon#about to read 3, iclass 6, count 2 2006.197.07:41:59.01#ibcon#read 3, iclass 6, count 2 2006.197.07:41:59.01#ibcon#about to read 4, iclass 6, count 2 2006.197.07:41:59.01#ibcon#read 4, iclass 6, count 2 2006.197.07:41:59.01#ibcon#about to read 5, iclass 6, count 2 2006.197.07:41:59.01#ibcon#read 5, iclass 6, count 2 2006.197.07:41:59.01#ibcon#about to read 6, iclass 6, count 2 2006.197.07:41:59.01#ibcon#read 6, iclass 6, count 2 2006.197.07:41:59.01#ibcon#end of sib2, iclass 6, count 2 2006.197.07:41:59.01#ibcon#*after write, iclass 6, count 2 2006.197.07:41:59.01#ibcon#*before return 0, iclass 6, count 2 2006.197.07:41:59.01#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.197.07:41:59.01#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.197.07:41:59.01#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.197.07:41:59.01#ibcon#ireg 7 cls_cnt 0 2006.197.07:41:59.01#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.197.07:41:59.13#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.197.07:41:59.13#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.197.07:41:59.13#ibcon#enter wrdev, iclass 6, count 0 2006.197.07:41:59.13#ibcon#first serial, iclass 6, count 0 2006.197.07:41:59.13#ibcon#enter sib2, iclass 6, count 0 2006.197.07:41:59.13#ibcon#flushed, iclass 6, count 0 2006.197.07:41:59.13#ibcon#about to write, iclass 6, count 0 2006.197.07:41:59.13#ibcon#wrote, iclass 6, count 0 2006.197.07:41:59.13#ibcon#about to read 3, iclass 6, count 0 2006.197.07:41:59.15#ibcon#read 3, iclass 6, count 0 2006.197.07:41:59.15#ibcon#about to read 4, iclass 6, count 0 2006.197.07:41:59.15#ibcon#read 4, iclass 6, count 0 2006.197.07:41:59.15#ibcon#about to read 5, iclass 6, count 0 2006.197.07:41:59.15#ibcon#read 5, iclass 6, count 0 2006.197.07:41:59.15#ibcon#about to read 6, iclass 6, count 0 2006.197.07:41:59.15#ibcon#read 6, iclass 6, count 0 2006.197.07:41:59.15#ibcon#end of sib2, iclass 6, count 0 2006.197.07:41:59.15#ibcon#*mode == 0, iclass 6, count 0 2006.197.07:41:59.15#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.197.07:41:59.15#ibcon#[25=USB\r\n] 2006.197.07:41:59.15#ibcon#*before write, iclass 6, count 0 2006.197.07:41:59.15#ibcon#enter sib2, iclass 6, count 0 2006.197.07:41:59.15#ibcon#flushed, iclass 6, count 0 2006.197.07:41:59.15#ibcon#about to write, iclass 6, count 0 2006.197.07:41:59.15#ibcon#wrote, iclass 6, count 0 2006.197.07:41:59.15#ibcon#about to read 3, iclass 6, count 0 2006.197.07:41:59.18#ibcon#read 3, iclass 6, count 0 2006.197.07:41:59.18#ibcon#about to read 4, iclass 6, count 0 2006.197.07:41:59.18#ibcon#read 4, iclass 6, count 0 2006.197.07:41:59.18#ibcon#about to read 5, iclass 6, count 0 2006.197.07:41:59.18#ibcon#read 5, iclass 6, count 0 2006.197.07:41:59.18#ibcon#about to read 6, iclass 6, count 0 2006.197.07:41:59.18#ibcon#read 6, iclass 6, count 0 2006.197.07:41:59.18#ibcon#end of sib2, iclass 6, count 0 2006.197.07:41:59.18#ibcon#*after write, iclass 6, count 0 2006.197.07:41:59.18#ibcon#*before return 0, iclass 6, count 0 2006.197.07:41:59.18#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.197.07:41:59.18#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.197.07:41:59.18#ibcon#about to clear, iclass 6 cls_cnt 0 2006.197.07:41:59.18#ibcon#cleared, iclass 6 cls_cnt 0 2006.197.07:41:59.18$vc4f8/valo=6,772.99 2006.197.07:41:59.18#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.197.07:41:59.18#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.197.07:41:59.18#ibcon#ireg 17 cls_cnt 0 2006.197.07:41:59.18#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.197.07:41:59.18#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.197.07:41:59.18#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.197.07:41:59.18#ibcon#enter wrdev, iclass 11, count 0 2006.197.07:41:59.18#ibcon#first serial, iclass 11, count 0 2006.197.07:41:59.18#ibcon#enter sib2, iclass 11, count 0 2006.197.07:41:59.18#ibcon#flushed, iclass 11, count 0 2006.197.07:41:59.18#ibcon#about to write, iclass 11, count 0 2006.197.07:41:59.18#ibcon#wrote, iclass 11, count 0 2006.197.07:41:59.18#ibcon#about to read 3, iclass 11, count 0 2006.197.07:41:59.19#abcon#<5=/04 3.5 6.1 25.84 961003.2\r\n> 2006.197.07:41:59.20#ibcon#read 3, iclass 11, count 0 2006.197.07:41:59.20#ibcon#about to read 4, iclass 11, count 0 2006.197.07:41:59.20#ibcon#read 4, iclass 11, count 0 2006.197.07:41:59.20#ibcon#about to read 5, iclass 11, count 0 2006.197.07:41:59.20#ibcon#read 5, iclass 11, count 0 2006.197.07:41:59.20#ibcon#about to read 6, iclass 11, count 0 2006.197.07:41:59.20#ibcon#read 6, iclass 11, count 0 2006.197.07:41:59.20#ibcon#end of sib2, iclass 11, count 0 2006.197.07:41:59.20#ibcon#*mode == 0, iclass 11, count 0 2006.197.07:41:59.20#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.197.07:41:59.20#ibcon#[26=FRQ=06,772.99\r\n] 2006.197.07:41:59.20#ibcon#*before write, iclass 11, count 0 2006.197.07:41:59.20#ibcon#enter sib2, iclass 11, count 0 2006.197.07:41:59.20#ibcon#flushed, iclass 11, count 0 2006.197.07:41:59.20#ibcon#about to write, iclass 11, count 0 2006.197.07:41:59.20#ibcon#wrote, iclass 11, count 0 2006.197.07:41:59.20#ibcon#about to read 3, iclass 11, count 0 2006.197.07:41:59.21#abcon#{5=INTERFACE CLEAR} 2006.197.07:41:59.24#ibcon#read 3, iclass 11, count 0 2006.197.07:41:59.24#ibcon#about to read 4, iclass 11, count 0 2006.197.07:41:59.24#ibcon#read 4, iclass 11, count 0 2006.197.07:41:59.24#ibcon#about to read 5, iclass 11, count 0 2006.197.07:41:59.24#ibcon#read 5, iclass 11, count 0 2006.197.07:41:59.24#ibcon#about to read 6, iclass 11, count 0 2006.197.07:41:59.24#ibcon#read 6, iclass 11, count 0 2006.197.07:41:59.24#ibcon#end of sib2, iclass 11, count 0 2006.197.07:41:59.24#ibcon#*after write, iclass 11, count 0 2006.197.07:41:59.24#ibcon#*before return 0, iclass 11, count 0 2006.197.07:41:59.24#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.197.07:41:59.24#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.197.07:41:59.24#ibcon#about to clear, iclass 11 cls_cnt 0 2006.197.07:41:59.24#ibcon#cleared, iclass 11 cls_cnt 0 2006.197.07:41:59.24$vc4f8/va=6,6 2006.197.07:41:59.24#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.197.07:41:59.24#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.197.07:41:59.24#ibcon#ireg 11 cls_cnt 2 2006.197.07:41:59.24#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.197.07:41:59.27#abcon#[5=S1D000X0/0*\r\n] 2006.197.07:41:59.30#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.197.07:41:59.30#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.197.07:41:59.30#ibcon#enter wrdev, iclass 15, count 2 2006.197.07:41:59.30#ibcon#first serial, iclass 15, count 2 2006.197.07:41:59.30#ibcon#enter sib2, iclass 15, count 2 2006.197.07:41:59.30#ibcon#flushed, iclass 15, count 2 2006.197.07:41:59.30#ibcon#about to write, iclass 15, count 2 2006.197.07:41:59.30#ibcon#wrote, iclass 15, count 2 2006.197.07:41:59.30#ibcon#about to read 3, iclass 15, count 2 2006.197.07:41:59.32#ibcon#read 3, iclass 15, count 2 2006.197.07:41:59.32#ibcon#about to read 4, iclass 15, count 2 2006.197.07:41:59.32#ibcon#read 4, iclass 15, count 2 2006.197.07:41:59.32#ibcon#about to read 5, iclass 15, count 2 2006.197.07:41:59.32#ibcon#read 5, iclass 15, count 2 2006.197.07:41:59.32#ibcon#about to read 6, iclass 15, count 2 2006.197.07:41:59.32#ibcon#read 6, iclass 15, count 2 2006.197.07:41:59.32#ibcon#end of sib2, iclass 15, count 2 2006.197.07:41:59.32#ibcon#*mode == 0, iclass 15, count 2 2006.197.07:41:59.32#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.197.07:41:59.32#ibcon#[25=AT06-06\r\n] 2006.197.07:41:59.32#ibcon#*before write, iclass 15, count 2 2006.197.07:41:59.32#ibcon#enter sib2, iclass 15, count 2 2006.197.07:41:59.32#ibcon#flushed, iclass 15, count 2 2006.197.07:41:59.32#ibcon#about to write, iclass 15, count 2 2006.197.07:41:59.32#ibcon#wrote, iclass 15, count 2 2006.197.07:41:59.32#ibcon#about to read 3, iclass 15, count 2 2006.197.07:41:59.35#ibcon#read 3, iclass 15, count 2 2006.197.07:41:59.35#ibcon#about to read 4, iclass 15, count 2 2006.197.07:41:59.35#ibcon#read 4, iclass 15, count 2 2006.197.07:41:59.35#ibcon#about to read 5, iclass 15, count 2 2006.197.07:41:59.35#ibcon#read 5, iclass 15, count 2 2006.197.07:41:59.35#ibcon#about to read 6, iclass 15, count 2 2006.197.07:41:59.35#ibcon#read 6, iclass 15, count 2 2006.197.07:41:59.35#ibcon#end of sib2, iclass 15, count 2 2006.197.07:41:59.35#ibcon#*after write, iclass 15, count 2 2006.197.07:41:59.35#ibcon#*before return 0, iclass 15, count 2 2006.197.07:41:59.35#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.197.07:41:59.35#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.197.07:41:59.35#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.197.07:41:59.35#ibcon#ireg 7 cls_cnt 0 2006.197.07:41:59.35#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.197.07:41:59.47#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.197.07:41:59.47#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.197.07:41:59.47#ibcon#enter wrdev, iclass 15, count 0 2006.197.07:41:59.47#ibcon#first serial, iclass 15, count 0 2006.197.07:41:59.47#ibcon#enter sib2, iclass 15, count 0 2006.197.07:41:59.47#ibcon#flushed, iclass 15, count 0 2006.197.07:41:59.47#ibcon#about to write, iclass 15, count 0 2006.197.07:41:59.47#ibcon#wrote, iclass 15, count 0 2006.197.07:41:59.47#ibcon#about to read 3, iclass 15, count 0 2006.197.07:41:59.49#ibcon#read 3, iclass 15, count 0 2006.197.07:41:59.49#ibcon#about to read 4, iclass 15, count 0 2006.197.07:41:59.49#ibcon#read 4, iclass 15, count 0 2006.197.07:41:59.49#ibcon#about to read 5, iclass 15, count 0 2006.197.07:41:59.49#ibcon#read 5, iclass 15, count 0 2006.197.07:41:59.49#ibcon#about to read 6, iclass 15, count 0 2006.197.07:41:59.49#ibcon#read 6, iclass 15, count 0 2006.197.07:41:59.49#ibcon#end of sib2, iclass 15, count 0 2006.197.07:41:59.49#ibcon#*mode == 0, iclass 15, count 0 2006.197.07:41:59.49#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.197.07:41:59.49#ibcon#[25=USB\r\n] 2006.197.07:41:59.49#ibcon#*before write, iclass 15, count 0 2006.197.07:41:59.49#ibcon#enter sib2, iclass 15, count 0 2006.197.07:41:59.49#ibcon#flushed, iclass 15, count 0 2006.197.07:41:59.49#ibcon#about to write, iclass 15, count 0 2006.197.07:41:59.49#ibcon#wrote, iclass 15, count 0 2006.197.07:41:59.49#ibcon#about to read 3, iclass 15, count 0 2006.197.07:41:59.52#ibcon#read 3, iclass 15, count 0 2006.197.07:41:59.52#ibcon#about to read 4, iclass 15, count 0 2006.197.07:41:59.52#ibcon#read 4, iclass 15, count 0 2006.197.07:41:59.52#ibcon#about to read 5, iclass 15, count 0 2006.197.07:41:59.52#ibcon#read 5, iclass 15, count 0 2006.197.07:41:59.52#ibcon#about to read 6, iclass 15, count 0 2006.197.07:41:59.52#ibcon#read 6, iclass 15, count 0 2006.197.07:41:59.52#ibcon#end of sib2, iclass 15, count 0 2006.197.07:41:59.52#ibcon#*after write, iclass 15, count 0 2006.197.07:41:59.52#ibcon#*before return 0, iclass 15, count 0 2006.197.07:41:59.52#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.197.07:41:59.52#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.197.07:41:59.52#ibcon#about to clear, iclass 15 cls_cnt 0 2006.197.07:41:59.52#ibcon#cleared, iclass 15 cls_cnt 0 2006.197.07:41:59.52$vc4f8/valo=7,832.99 2006.197.07:41:59.52#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.197.07:41:59.52#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.197.07:41:59.52#ibcon#ireg 17 cls_cnt 0 2006.197.07:41:59.52#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.197.07:41:59.52#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.197.07:41:59.52#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.197.07:41:59.52#ibcon#enter wrdev, iclass 18, count 0 2006.197.07:41:59.52#ibcon#first serial, iclass 18, count 0 2006.197.07:41:59.52#ibcon#enter sib2, iclass 18, count 0 2006.197.07:41:59.52#ibcon#flushed, iclass 18, count 0 2006.197.07:41:59.52#ibcon#about to write, iclass 18, count 0 2006.197.07:41:59.52#ibcon#wrote, iclass 18, count 0 2006.197.07:41:59.52#ibcon#about to read 3, iclass 18, count 0 2006.197.07:41:59.54#ibcon#read 3, iclass 18, count 0 2006.197.07:41:59.54#ibcon#about to read 4, iclass 18, count 0 2006.197.07:41:59.54#ibcon#read 4, iclass 18, count 0 2006.197.07:41:59.54#ibcon#about to read 5, iclass 18, count 0 2006.197.07:41:59.54#ibcon#read 5, iclass 18, count 0 2006.197.07:41:59.54#ibcon#about to read 6, iclass 18, count 0 2006.197.07:41:59.54#ibcon#read 6, iclass 18, count 0 2006.197.07:41:59.54#ibcon#end of sib2, iclass 18, count 0 2006.197.07:41:59.54#ibcon#*mode == 0, iclass 18, count 0 2006.197.07:41:59.54#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.197.07:41:59.54#ibcon#[26=FRQ=07,832.99\r\n] 2006.197.07:41:59.54#ibcon#*before write, iclass 18, count 0 2006.197.07:41:59.54#ibcon#enter sib2, iclass 18, count 0 2006.197.07:41:59.54#ibcon#flushed, iclass 18, count 0 2006.197.07:41:59.54#ibcon#about to write, iclass 18, count 0 2006.197.07:41:59.54#ibcon#wrote, iclass 18, count 0 2006.197.07:41:59.54#ibcon#about to read 3, iclass 18, count 0 2006.197.07:41:59.58#ibcon#read 3, iclass 18, count 0 2006.197.07:41:59.58#ibcon#about to read 4, iclass 18, count 0 2006.197.07:41:59.58#ibcon#read 4, iclass 18, count 0 2006.197.07:41:59.58#ibcon#about to read 5, iclass 18, count 0 2006.197.07:41:59.58#ibcon#read 5, iclass 18, count 0 2006.197.07:41:59.58#ibcon#about to read 6, iclass 18, count 0 2006.197.07:41:59.58#ibcon#read 6, iclass 18, count 0 2006.197.07:41:59.58#ibcon#end of sib2, iclass 18, count 0 2006.197.07:41:59.58#ibcon#*after write, iclass 18, count 0 2006.197.07:41:59.58#ibcon#*before return 0, iclass 18, count 0 2006.197.07:41:59.58#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.197.07:41:59.58#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.197.07:41:59.58#ibcon#about to clear, iclass 18 cls_cnt 0 2006.197.07:41:59.58#ibcon#cleared, iclass 18 cls_cnt 0 2006.197.07:41:59.58$vc4f8/va=7,6 2006.197.07:41:59.58#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.197.07:41:59.58#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.197.07:41:59.58#ibcon#ireg 11 cls_cnt 2 2006.197.07:41:59.58#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.197.07:41:59.64#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.197.07:41:59.64#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.197.07:41:59.64#ibcon#enter wrdev, iclass 20, count 2 2006.197.07:41:59.64#ibcon#first serial, iclass 20, count 2 2006.197.07:41:59.64#ibcon#enter sib2, iclass 20, count 2 2006.197.07:41:59.64#ibcon#flushed, iclass 20, count 2 2006.197.07:41:59.64#ibcon#about to write, iclass 20, count 2 2006.197.07:41:59.64#ibcon#wrote, iclass 20, count 2 2006.197.07:41:59.64#ibcon#about to read 3, iclass 20, count 2 2006.197.07:41:59.66#ibcon#read 3, iclass 20, count 2 2006.197.07:41:59.66#ibcon#about to read 4, iclass 20, count 2 2006.197.07:41:59.66#ibcon#read 4, iclass 20, count 2 2006.197.07:41:59.66#ibcon#about to read 5, iclass 20, count 2 2006.197.07:41:59.66#ibcon#read 5, iclass 20, count 2 2006.197.07:41:59.66#ibcon#about to read 6, iclass 20, count 2 2006.197.07:41:59.66#ibcon#read 6, iclass 20, count 2 2006.197.07:41:59.66#ibcon#end of sib2, iclass 20, count 2 2006.197.07:41:59.66#ibcon#*mode == 0, iclass 20, count 2 2006.197.07:41:59.66#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.197.07:41:59.66#ibcon#[25=AT07-06\r\n] 2006.197.07:41:59.66#ibcon#*before write, iclass 20, count 2 2006.197.07:41:59.66#ibcon#enter sib2, iclass 20, count 2 2006.197.07:41:59.66#ibcon#flushed, iclass 20, count 2 2006.197.07:41:59.66#ibcon#about to write, iclass 20, count 2 2006.197.07:41:59.66#ibcon#wrote, iclass 20, count 2 2006.197.07:41:59.66#ibcon#about to read 3, iclass 20, count 2 2006.197.07:41:59.69#ibcon#read 3, iclass 20, count 2 2006.197.07:41:59.69#ibcon#about to read 4, iclass 20, count 2 2006.197.07:41:59.69#ibcon#read 4, iclass 20, count 2 2006.197.07:41:59.69#ibcon#about to read 5, iclass 20, count 2 2006.197.07:41:59.69#ibcon#read 5, iclass 20, count 2 2006.197.07:41:59.69#ibcon#about to read 6, iclass 20, count 2 2006.197.07:41:59.69#ibcon#read 6, iclass 20, count 2 2006.197.07:41:59.69#ibcon#end of sib2, iclass 20, count 2 2006.197.07:41:59.69#ibcon#*after write, iclass 20, count 2 2006.197.07:41:59.69#ibcon#*before return 0, iclass 20, count 2 2006.197.07:41:59.69#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.197.07:41:59.69#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.197.07:41:59.69#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.197.07:41:59.69#ibcon#ireg 7 cls_cnt 0 2006.197.07:41:59.69#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.197.07:41:59.81#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.197.07:41:59.81#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.197.07:41:59.81#ibcon#enter wrdev, iclass 20, count 0 2006.197.07:41:59.81#ibcon#first serial, iclass 20, count 0 2006.197.07:41:59.81#ibcon#enter sib2, iclass 20, count 0 2006.197.07:41:59.81#ibcon#flushed, iclass 20, count 0 2006.197.07:41:59.81#ibcon#about to write, iclass 20, count 0 2006.197.07:41:59.81#ibcon#wrote, iclass 20, count 0 2006.197.07:41:59.81#ibcon#about to read 3, iclass 20, count 0 2006.197.07:41:59.83#ibcon#read 3, iclass 20, count 0 2006.197.07:41:59.83#ibcon#about to read 4, iclass 20, count 0 2006.197.07:41:59.83#ibcon#read 4, iclass 20, count 0 2006.197.07:41:59.83#ibcon#about to read 5, iclass 20, count 0 2006.197.07:41:59.83#ibcon#read 5, iclass 20, count 0 2006.197.07:41:59.83#ibcon#about to read 6, iclass 20, count 0 2006.197.07:41:59.83#ibcon#read 6, iclass 20, count 0 2006.197.07:41:59.83#ibcon#end of sib2, iclass 20, count 0 2006.197.07:41:59.83#ibcon#*mode == 0, iclass 20, count 0 2006.197.07:41:59.83#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.197.07:41:59.83#ibcon#[25=USB\r\n] 2006.197.07:41:59.83#ibcon#*before write, iclass 20, count 0 2006.197.07:41:59.83#ibcon#enter sib2, iclass 20, count 0 2006.197.07:41:59.83#ibcon#flushed, iclass 20, count 0 2006.197.07:41:59.83#ibcon#about to write, iclass 20, count 0 2006.197.07:41:59.83#ibcon#wrote, iclass 20, count 0 2006.197.07:41:59.83#ibcon#about to read 3, iclass 20, count 0 2006.197.07:41:59.86#ibcon#read 3, iclass 20, count 0 2006.197.07:41:59.86#ibcon#about to read 4, iclass 20, count 0 2006.197.07:41:59.86#ibcon#read 4, iclass 20, count 0 2006.197.07:41:59.86#ibcon#about to read 5, iclass 20, count 0 2006.197.07:41:59.86#ibcon#read 5, iclass 20, count 0 2006.197.07:41:59.86#ibcon#about to read 6, iclass 20, count 0 2006.197.07:41:59.86#ibcon#read 6, iclass 20, count 0 2006.197.07:41:59.86#ibcon#end of sib2, iclass 20, count 0 2006.197.07:41:59.86#ibcon#*after write, iclass 20, count 0 2006.197.07:41:59.86#ibcon#*before return 0, iclass 20, count 0 2006.197.07:41:59.86#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.197.07:41:59.86#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.197.07:41:59.86#ibcon#about to clear, iclass 20 cls_cnt 0 2006.197.07:41:59.86#ibcon#cleared, iclass 20 cls_cnt 0 2006.197.07:41:59.86$vc4f8/valo=8,852.99 2006.197.07:41:59.86#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.197.07:41:59.86#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.197.07:41:59.86#ibcon#ireg 17 cls_cnt 0 2006.197.07:41:59.86#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.197.07:41:59.86#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.197.07:41:59.86#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.197.07:41:59.86#ibcon#enter wrdev, iclass 22, count 0 2006.197.07:41:59.86#ibcon#first serial, iclass 22, count 0 2006.197.07:41:59.86#ibcon#enter sib2, iclass 22, count 0 2006.197.07:41:59.86#ibcon#flushed, iclass 22, count 0 2006.197.07:41:59.86#ibcon#about to write, iclass 22, count 0 2006.197.07:41:59.86#ibcon#wrote, iclass 22, count 0 2006.197.07:41:59.86#ibcon#about to read 3, iclass 22, count 0 2006.197.07:41:59.88#ibcon#read 3, iclass 22, count 0 2006.197.07:41:59.88#ibcon#about to read 4, iclass 22, count 0 2006.197.07:41:59.88#ibcon#read 4, iclass 22, count 0 2006.197.07:41:59.88#ibcon#about to read 5, iclass 22, count 0 2006.197.07:41:59.88#ibcon#read 5, iclass 22, count 0 2006.197.07:41:59.88#ibcon#about to read 6, iclass 22, count 0 2006.197.07:41:59.88#ibcon#read 6, iclass 22, count 0 2006.197.07:41:59.88#ibcon#end of sib2, iclass 22, count 0 2006.197.07:41:59.88#ibcon#*mode == 0, iclass 22, count 0 2006.197.07:41:59.88#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.197.07:41:59.88#ibcon#[26=FRQ=08,852.99\r\n] 2006.197.07:41:59.88#ibcon#*before write, iclass 22, count 0 2006.197.07:41:59.88#ibcon#enter sib2, iclass 22, count 0 2006.197.07:41:59.88#ibcon#flushed, iclass 22, count 0 2006.197.07:41:59.88#ibcon#about to write, iclass 22, count 0 2006.197.07:41:59.88#ibcon#wrote, iclass 22, count 0 2006.197.07:41:59.88#ibcon#about to read 3, iclass 22, count 0 2006.197.07:41:59.92#ibcon#read 3, iclass 22, count 0 2006.197.07:41:59.92#ibcon#about to read 4, iclass 22, count 0 2006.197.07:41:59.92#ibcon#read 4, iclass 22, count 0 2006.197.07:41:59.92#ibcon#about to read 5, iclass 22, count 0 2006.197.07:41:59.92#ibcon#read 5, iclass 22, count 0 2006.197.07:41:59.92#ibcon#about to read 6, iclass 22, count 0 2006.197.07:41:59.92#ibcon#read 6, iclass 22, count 0 2006.197.07:41:59.92#ibcon#end of sib2, iclass 22, count 0 2006.197.07:41:59.92#ibcon#*after write, iclass 22, count 0 2006.197.07:41:59.92#ibcon#*before return 0, iclass 22, count 0 2006.197.07:41:59.92#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.197.07:41:59.92#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.197.07:41:59.92#ibcon#about to clear, iclass 22 cls_cnt 0 2006.197.07:41:59.92#ibcon#cleared, iclass 22 cls_cnt 0 2006.197.07:41:59.92$vc4f8/va=8,7 2006.197.07:41:59.92#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.197.07:41:59.92#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.197.07:41:59.92#ibcon#ireg 11 cls_cnt 2 2006.197.07:41:59.92#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.197.07:41:59.98#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.197.07:41:59.98#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.197.07:41:59.98#ibcon#enter wrdev, iclass 24, count 2 2006.197.07:41:59.98#ibcon#first serial, iclass 24, count 2 2006.197.07:41:59.98#ibcon#enter sib2, iclass 24, count 2 2006.197.07:41:59.98#ibcon#flushed, iclass 24, count 2 2006.197.07:41:59.98#ibcon#about to write, iclass 24, count 2 2006.197.07:41:59.98#ibcon#wrote, iclass 24, count 2 2006.197.07:41:59.98#ibcon#about to read 3, iclass 24, count 2 2006.197.07:42:00.00#ibcon#read 3, iclass 24, count 2 2006.197.07:42:00.00#ibcon#about to read 4, iclass 24, count 2 2006.197.07:42:00.00#ibcon#read 4, iclass 24, count 2 2006.197.07:42:00.00#ibcon#about to read 5, iclass 24, count 2 2006.197.07:42:00.00#ibcon#read 5, iclass 24, count 2 2006.197.07:42:00.00#ibcon#about to read 6, iclass 24, count 2 2006.197.07:42:00.00#ibcon#read 6, iclass 24, count 2 2006.197.07:42:00.00#ibcon#end of sib2, iclass 24, count 2 2006.197.07:42:00.00#ibcon#*mode == 0, iclass 24, count 2 2006.197.07:42:00.00#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.197.07:42:00.00#ibcon#[25=AT08-07\r\n] 2006.197.07:42:00.00#ibcon#*before write, iclass 24, count 2 2006.197.07:42:00.00#ibcon#enter sib2, iclass 24, count 2 2006.197.07:42:00.00#ibcon#flushed, iclass 24, count 2 2006.197.07:42:00.00#ibcon#about to write, iclass 24, count 2 2006.197.07:42:00.00#ibcon#wrote, iclass 24, count 2 2006.197.07:42:00.00#ibcon#about to read 3, iclass 24, count 2 2006.197.07:42:00.03#ibcon#read 3, iclass 24, count 2 2006.197.07:42:00.03#ibcon#about to read 4, iclass 24, count 2 2006.197.07:42:00.03#ibcon#read 4, iclass 24, count 2 2006.197.07:42:00.03#ibcon#about to read 5, iclass 24, count 2 2006.197.07:42:00.03#ibcon#read 5, iclass 24, count 2 2006.197.07:42:00.03#ibcon#about to read 6, iclass 24, count 2 2006.197.07:42:00.03#ibcon#read 6, iclass 24, count 2 2006.197.07:42:00.03#ibcon#end of sib2, iclass 24, count 2 2006.197.07:42:00.03#ibcon#*after write, iclass 24, count 2 2006.197.07:42:00.03#ibcon#*before return 0, iclass 24, count 2 2006.197.07:42:00.03#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.197.07:42:00.03#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.197.07:42:00.03#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.197.07:42:00.03#ibcon#ireg 7 cls_cnt 0 2006.197.07:42:00.03#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.197.07:42:00.15#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.197.07:42:00.15#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.197.07:42:00.15#ibcon#enter wrdev, iclass 24, count 0 2006.197.07:42:00.15#ibcon#first serial, iclass 24, count 0 2006.197.07:42:00.15#ibcon#enter sib2, iclass 24, count 0 2006.197.07:42:00.15#ibcon#flushed, iclass 24, count 0 2006.197.07:42:00.15#ibcon#about to write, iclass 24, count 0 2006.197.07:42:00.15#ibcon#wrote, iclass 24, count 0 2006.197.07:42:00.15#ibcon#about to read 3, iclass 24, count 0 2006.197.07:42:00.17#ibcon#read 3, iclass 24, count 0 2006.197.07:42:00.17#ibcon#about to read 4, iclass 24, count 0 2006.197.07:42:00.17#ibcon#read 4, iclass 24, count 0 2006.197.07:42:00.17#ibcon#about to read 5, iclass 24, count 0 2006.197.07:42:00.17#ibcon#read 5, iclass 24, count 0 2006.197.07:42:00.17#ibcon#about to read 6, iclass 24, count 0 2006.197.07:42:00.17#ibcon#read 6, iclass 24, count 0 2006.197.07:42:00.17#ibcon#end of sib2, iclass 24, count 0 2006.197.07:42:00.17#ibcon#*mode == 0, iclass 24, count 0 2006.197.07:42:00.17#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.197.07:42:00.17#ibcon#[25=USB\r\n] 2006.197.07:42:00.17#ibcon#*before write, iclass 24, count 0 2006.197.07:42:00.17#ibcon#enter sib2, iclass 24, count 0 2006.197.07:42:00.17#ibcon#flushed, iclass 24, count 0 2006.197.07:42:00.17#ibcon#about to write, iclass 24, count 0 2006.197.07:42:00.17#ibcon#wrote, iclass 24, count 0 2006.197.07:42:00.17#ibcon#about to read 3, iclass 24, count 0 2006.197.07:42:00.20#ibcon#read 3, iclass 24, count 0 2006.197.07:42:00.20#ibcon#about to read 4, iclass 24, count 0 2006.197.07:42:00.20#ibcon#read 4, iclass 24, count 0 2006.197.07:42:00.20#ibcon#about to read 5, iclass 24, count 0 2006.197.07:42:00.20#ibcon#read 5, iclass 24, count 0 2006.197.07:42:00.20#ibcon#about to read 6, iclass 24, count 0 2006.197.07:42:00.20#ibcon#read 6, iclass 24, count 0 2006.197.07:42:00.20#ibcon#end of sib2, iclass 24, count 0 2006.197.07:42:00.20#ibcon#*after write, iclass 24, count 0 2006.197.07:42:00.20#ibcon#*before return 0, iclass 24, count 0 2006.197.07:42:00.20#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.197.07:42:00.20#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.197.07:42:00.20#ibcon#about to clear, iclass 24 cls_cnt 0 2006.197.07:42:00.20#ibcon#cleared, iclass 24 cls_cnt 0 2006.197.07:42:00.20$vc4f8/vblo=1,632.99 2006.197.07:42:00.20#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.197.07:42:00.20#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.197.07:42:00.20#ibcon#ireg 17 cls_cnt 0 2006.197.07:42:00.20#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.197.07:42:00.20#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.197.07:42:00.20#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.197.07:42:00.20#ibcon#enter wrdev, iclass 26, count 0 2006.197.07:42:00.20#ibcon#first serial, iclass 26, count 0 2006.197.07:42:00.20#ibcon#enter sib2, iclass 26, count 0 2006.197.07:42:00.20#ibcon#flushed, iclass 26, count 0 2006.197.07:42:00.20#ibcon#about to write, iclass 26, count 0 2006.197.07:42:00.20#ibcon#wrote, iclass 26, count 0 2006.197.07:42:00.20#ibcon#about to read 3, iclass 26, count 0 2006.197.07:42:00.22#ibcon#read 3, iclass 26, count 0 2006.197.07:42:00.22#ibcon#about to read 4, iclass 26, count 0 2006.197.07:42:00.22#ibcon#read 4, iclass 26, count 0 2006.197.07:42:00.22#ibcon#about to read 5, iclass 26, count 0 2006.197.07:42:00.22#ibcon#read 5, iclass 26, count 0 2006.197.07:42:00.22#ibcon#about to read 6, iclass 26, count 0 2006.197.07:42:00.22#ibcon#read 6, iclass 26, count 0 2006.197.07:42:00.22#ibcon#end of sib2, iclass 26, count 0 2006.197.07:42:00.22#ibcon#*mode == 0, iclass 26, count 0 2006.197.07:42:00.22#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.197.07:42:00.22#ibcon#[28=FRQ=01,632.99\r\n] 2006.197.07:42:00.22#ibcon#*before write, iclass 26, count 0 2006.197.07:42:00.22#ibcon#enter sib2, iclass 26, count 0 2006.197.07:42:00.22#ibcon#flushed, iclass 26, count 0 2006.197.07:42:00.22#ibcon#about to write, iclass 26, count 0 2006.197.07:42:00.22#ibcon#wrote, iclass 26, count 0 2006.197.07:42:00.22#ibcon#about to read 3, iclass 26, count 0 2006.197.07:42:00.26#ibcon#read 3, iclass 26, count 0 2006.197.07:42:00.26#ibcon#about to read 4, iclass 26, count 0 2006.197.07:42:00.26#ibcon#read 4, iclass 26, count 0 2006.197.07:42:00.26#ibcon#about to read 5, iclass 26, count 0 2006.197.07:42:00.26#ibcon#read 5, iclass 26, count 0 2006.197.07:42:00.26#ibcon#about to read 6, iclass 26, count 0 2006.197.07:42:00.26#ibcon#read 6, iclass 26, count 0 2006.197.07:42:00.26#ibcon#end of sib2, iclass 26, count 0 2006.197.07:42:00.26#ibcon#*after write, iclass 26, count 0 2006.197.07:42:00.26#ibcon#*before return 0, iclass 26, count 0 2006.197.07:42:00.26#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.197.07:42:00.26#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.197.07:42:00.26#ibcon#about to clear, iclass 26 cls_cnt 0 2006.197.07:42:00.26#ibcon#cleared, iclass 26 cls_cnt 0 2006.197.07:42:00.26$vc4f8/vb=1,4 2006.197.07:42:00.26#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.197.07:42:00.26#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.197.07:42:00.26#ibcon#ireg 11 cls_cnt 2 2006.197.07:42:00.26#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.197.07:42:00.26#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.197.07:42:00.26#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.197.07:42:00.26#ibcon#enter wrdev, iclass 28, count 2 2006.197.07:42:00.26#ibcon#first serial, iclass 28, count 2 2006.197.07:42:00.26#ibcon#enter sib2, iclass 28, count 2 2006.197.07:42:00.26#ibcon#flushed, iclass 28, count 2 2006.197.07:42:00.26#ibcon#about to write, iclass 28, count 2 2006.197.07:42:00.26#ibcon#wrote, iclass 28, count 2 2006.197.07:42:00.26#ibcon#about to read 3, iclass 28, count 2 2006.197.07:42:00.28#ibcon#read 3, iclass 28, count 2 2006.197.07:42:00.28#ibcon#about to read 4, iclass 28, count 2 2006.197.07:42:00.28#ibcon#read 4, iclass 28, count 2 2006.197.07:42:00.28#ibcon#about to read 5, iclass 28, count 2 2006.197.07:42:00.28#ibcon#read 5, iclass 28, count 2 2006.197.07:42:00.28#ibcon#about to read 6, iclass 28, count 2 2006.197.07:42:00.28#ibcon#read 6, iclass 28, count 2 2006.197.07:42:00.28#ibcon#end of sib2, iclass 28, count 2 2006.197.07:42:00.28#ibcon#*mode == 0, iclass 28, count 2 2006.197.07:42:00.28#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.197.07:42:00.28#ibcon#[27=AT01-04\r\n] 2006.197.07:42:00.28#ibcon#*before write, iclass 28, count 2 2006.197.07:42:00.28#ibcon#enter sib2, iclass 28, count 2 2006.197.07:42:00.28#ibcon#flushed, iclass 28, count 2 2006.197.07:42:00.28#ibcon#about to write, iclass 28, count 2 2006.197.07:42:00.28#ibcon#wrote, iclass 28, count 2 2006.197.07:42:00.28#ibcon#about to read 3, iclass 28, count 2 2006.197.07:42:00.31#ibcon#read 3, iclass 28, count 2 2006.197.07:42:00.31#ibcon#about to read 4, iclass 28, count 2 2006.197.07:42:00.31#ibcon#read 4, iclass 28, count 2 2006.197.07:42:00.31#ibcon#about to read 5, iclass 28, count 2 2006.197.07:42:00.31#ibcon#read 5, iclass 28, count 2 2006.197.07:42:00.31#ibcon#about to read 6, iclass 28, count 2 2006.197.07:42:00.31#ibcon#read 6, iclass 28, count 2 2006.197.07:42:00.31#ibcon#end of sib2, iclass 28, count 2 2006.197.07:42:00.31#ibcon#*after write, iclass 28, count 2 2006.197.07:42:00.31#ibcon#*before return 0, iclass 28, count 2 2006.197.07:42:00.31#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.197.07:42:00.31#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.197.07:42:00.31#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.197.07:42:00.31#ibcon#ireg 7 cls_cnt 0 2006.197.07:42:00.31#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.197.07:42:00.43#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.197.07:42:00.43#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.197.07:42:00.43#ibcon#enter wrdev, iclass 28, count 0 2006.197.07:42:00.43#ibcon#first serial, iclass 28, count 0 2006.197.07:42:00.43#ibcon#enter sib2, iclass 28, count 0 2006.197.07:42:00.43#ibcon#flushed, iclass 28, count 0 2006.197.07:42:00.43#ibcon#about to write, iclass 28, count 0 2006.197.07:42:00.43#ibcon#wrote, iclass 28, count 0 2006.197.07:42:00.43#ibcon#about to read 3, iclass 28, count 0 2006.197.07:42:00.45#ibcon#read 3, iclass 28, count 0 2006.197.07:42:00.45#ibcon#about to read 4, iclass 28, count 0 2006.197.07:42:00.45#ibcon#read 4, iclass 28, count 0 2006.197.07:42:00.45#ibcon#about to read 5, iclass 28, count 0 2006.197.07:42:00.45#ibcon#read 5, iclass 28, count 0 2006.197.07:42:00.45#ibcon#about to read 6, iclass 28, count 0 2006.197.07:42:00.45#ibcon#read 6, iclass 28, count 0 2006.197.07:42:00.45#ibcon#end of sib2, iclass 28, count 0 2006.197.07:42:00.45#ibcon#*mode == 0, iclass 28, count 0 2006.197.07:42:00.45#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.197.07:42:00.45#ibcon#[27=USB\r\n] 2006.197.07:42:00.45#ibcon#*before write, iclass 28, count 0 2006.197.07:42:00.45#ibcon#enter sib2, iclass 28, count 0 2006.197.07:42:00.45#ibcon#flushed, iclass 28, count 0 2006.197.07:42:00.45#ibcon#about to write, iclass 28, count 0 2006.197.07:42:00.45#ibcon#wrote, iclass 28, count 0 2006.197.07:42:00.45#ibcon#about to read 3, iclass 28, count 0 2006.197.07:42:00.48#ibcon#read 3, iclass 28, count 0 2006.197.07:42:00.48#ibcon#about to read 4, iclass 28, count 0 2006.197.07:42:00.48#ibcon#read 4, iclass 28, count 0 2006.197.07:42:00.48#ibcon#about to read 5, iclass 28, count 0 2006.197.07:42:00.48#ibcon#read 5, iclass 28, count 0 2006.197.07:42:00.48#ibcon#about to read 6, iclass 28, count 0 2006.197.07:42:00.48#ibcon#read 6, iclass 28, count 0 2006.197.07:42:00.48#ibcon#end of sib2, iclass 28, count 0 2006.197.07:42:00.48#ibcon#*after write, iclass 28, count 0 2006.197.07:42:00.48#ibcon#*before return 0, iclass 28, count 0 2006.197.07:42:00.48#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.197.07:42:00.48#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.197.07:42:00.48#ibcon#about to clear, iclass 28 cls_cnt 0 2006.197.07:42:00.48#ibcon#cleared, iclass 28 cls_cnt 0 2006.197.07:42:00.48$vc4f8/vblo=2,640.99 2006.197.07:42:00.48#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.197.07:42:00.48#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.197.07:42:00.48#ibcon#ireg 17 cls_cnt 0 2006.197.07:42:00.48#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.197.07:42:00.48#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.197.07:42:00.48#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.197.07:42:00.48#ibcon#enter wrdev, iclass 30, count 0 2006.197.07:42:00.48#ibcon#first serial, iclass 30, count 0 2006.197.07:42:00.48#ibcon#enter sib2, iclass 30, count 0 2006.197.07:42:00.48#ibcon#flushed, iclass 30, count 0 2006.197.07:42:00.48#ibcon#about to write, iclass 30, count 0 2006.197.07:42:00.48#ibcon#wrote, iclass 30, count 0 2006.197.07:42:00.48#ibcon#about to read 3, iclass 30, count 0 2006.197.07:42:00.50#ibcon#read 3, iclass 30, count 0 2006.197.07:42:00.50#ibcon#about to read 4, iclass 30, count 0 2006.197.07:42:00.50#ibcon#read 4, iclass 30, count 0 2006.197.07:42:00.50#ibcon#about to read 5, iclass 30, count 0 2006.197.07:42:00.50#ibcon#read 5, iclass 30, count 0 2006.197.07:42:00.50#ibcon#about to read 6, iclass 30, count 0 2006.197.07:42:00.50#ibcon#read 6, iclass 30, count 0 2006.197.07:42:00.50#ibcon#end of sib2, iclass 30, count 0 2006.197.07:42:00.50#ibcon#*mode == 0, iclass 30, count 0 2006.197.07:42:00.50#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.197.07:42:00.50#ibcon#[28=FRQ=02,640.99\r\n] 2006.197.07:42:00.50#ibcon#*before write, iclass 30, count 0 2006.197.07:42:00.50#ibcon#enter sib2, iclass 30, count 0 2006.197.07:42:00.50#ibcon#flushed, iclass 30, count 0 2006.197.07:42:00.50#ibcon#about to write, iclass 30, count 0 2006.197.07:42:00.50#ibcon#wrote, iclass 30, count 0 2006.197.07:42:00.50#ibcon#about to read 3, iclass 30, count 0 2006.197.07:42:00.54#ibcon#read 3, iclass 30, count 0 2006.197.07:42:00.54#ibcon#about to read 4, iclass 30, count 0 2006.197.07:42:00.54#ibcon#read 4, iclass 30, count 0 2006.197.07:42:00.54#ibcon#about to read 5, iclass 30, count 0 2006.197.07:42:00.54#ibcon#read 5, iclass 30, count 0 2006.197.07:42:00.54#ibcon#about to read 6, iclass 30, count 0 2006.197.07:42:00.54#ibcon#read 6, iclass 30, count 0 2006.197.07:42:00.54#ibcon#end of sib2, iclass 30, count 0 2006.197.07:42:00.54#ibcon#*after write, iclass 30, count 0 2006.197.07:42:00.54#ibcon#*before return 0, iclass 30, count 0 2006.197.07:42:00.54#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.197.07:42:00.54#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.197.07:42:00.54#ibcon#about to clear, iclass 30 cls_cnt 0 2006.197.07:42:00.54#ibcon#cleared, iclass 30 cls_cnt 0 2006.197.07:42:00.54$vc4f8/vb=2,4 2006.197.07:42:00.54#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.197.07:42:00.54#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.197.07:42:00.54#ibcon#ireg 11 cls_cnt 2 2006.197.07:42:00.54#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.197.07:42:00.60#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.197.07:42:00.60#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.197.07:42:00.60#ibcon#enter wrdev, iclass 32, count 2 2006.197.07:42:00.60#ibcon#first serial, iclass 32, count 2 2006.197.07:42:00.60#ibcon#enter sib2, iclass 32, count 2 2006.197.07:42:00.60#ibcon#flushed, iclass 32, count 2 2006.197.07:42:00.60#ibcon#about to write, iclass 32, count 2 2006.197.07:42:00.60#ibcon#wrote, iclass 32, count 2 2006.197.07:42:00.60#ibcon#about to read 3, iclass 32, count 2 2006.197.07:42:00.62#ibcon#read 3, iclass 32, count 2 2006.197.07:42:00.62#ibcon#about to read 4, iclass 32, count 2 2006.197.07:42:00.62#ibcon#read 4, iclass 32, count 2 2006.197.07:42:00.62#ibcon#about to read 5, iclass 32, count 2 2006.197.07:42:00.62#ibcon#read 5, iclass 32, count 2 2006.197.07:42:00.62#ibcon#about to read 6, iclass 32, count 2 2006.197.07:42:00.62#ibcon#read 6, iclass 32, count 2 2006.197.07:42:00.62#ibcon#end of sib2, iclass 32, count 2 2006.197.07:42:00.62#ibcon#*mode == 0, iclass 32, count 2 2006.197.07:42:00.62#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.197.07:42:00.62#ibcon#[27=AT02-04\r\n] 2006.197.07:42:00.62#ibcon#*before write, iclass 32, count 2 2006.197.07:42:00.62#ibcon#enter sib2, iclass 32, count 2 2006.197.07:42:00.62#ibcon#flushed, iclass 32, count 2 2006.197.07:42:00.62#ibcon#about to write, iclass 32, count 2 2006.197.07:42:00.62#ibcon#wrote, iclass 32, count 2 2006.197.07:42:00.62#ibcon#about to read 3, iclass 32, count 2 2006.197.07:42:00.65#ibcon#read 3, iclass 32, count 2 2006.197.07:42:00.65#ibcon#about to read 4, iclass 32, count 2 2006.197.07:42:00.65#ibcon#read 4, iclass 32, count 2 2006.197.07:42:00.65#ibcon#about to read 5, iclass 32, count 2 2006.197.07:42:00.65#ibcon#read 5, iclass 32, count 2 2006.197.07:42:00.65#ibcon#about to read 6, iclass 32, count 2 2006.197.07:42:00.65#ibcon#read 6, iclass 32, count 2 2006.197.07:42:00.65#ibcon#end of sib2, iclass 32, count 2 2006.197.07:42:00.65#ibcon#*after write, iclass 32, count 2 2006.197.07:42:00.65#ibcon#*before return 0, iclass 32, count 2 2006.197.07:42:00.65#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.197.07:42:00.65#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.197.07:42:00.65#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.197.07:42:00.65#ibcon#ireg 7 cls_cnt 0 2006.197.07:42:00.65#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.197.07:42:00.77#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.197.07:42:00.77#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.197.07:42:00.77#ibcon#enter wrdev, iclass 32, count 0 2006.197.07:42:00.77#ibcon#first serial, iclass 32, count 0 2006.197.07:42:00.77#ibcon#enter sib2, iclass 32, count 0 2006.197.07:42:00.77#ibcon#flushed, iclass 32, count 0 2006.197.07:42:00.77#ibcon#about to write, iclass 32, count 0 2006.197.07:42:00.77#ibcon#wrote, iclass 32, count 0 2006.197.07:42:00.77#ibcon#about to read 3, iclass 32, count 0 2006.197.07:42:00.79#ibcon#read 3, iclass 32, count 0 2006.197.07:42:00.79#ibcon#about to read 4, iclass 32, count 0 2006.197.07:42:00.79#ibcon#read 4, iclass 32, count 0 2006.197.07:42:00.79#ibcon#about to read 5, iclass 32, count 0 2006.197.07:42:00.79#ibcon#read 5, iclass 32, count 0 2006.197.07:42:00.79#ibcon#about to read 6, iclass 32, count 0 2006.197.07:42:00.79#ibcon#read 6, iclass 32, count 0 2006.197.07:42:00.79#ibcon#end of sib2, iclass 32, count 0 2006.197.07:42:00.79#ibcon#*mode == 0, iclass 32, count 0 2006.197.07:42:00.79#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.197.07:42:00.79#ibcon#[27=USB\r\n] 2006.197.07:42:00.79#ibcon#*before write, iclass 32, count 0 2006.197.07:42:00.79#ibcon#enter sib2, iclass 32, count 0 2006.197.07:42:00.79#ibcon#flushed, iclass 32, count 0 2006.197.07:42:00.79#ibcon#about to write, iclass 32, count 0 2006.197.07:42:00.79#ibcon#wrote, iclass 32, count 0 2006.197.07:42:00.79#ibcon#about to read 3, iclass 32, count 0 2006.197.07:42:00.82#ibcon#read 3, iclass 32, count 0 2006.197.07:42:00.82#ibcon#about to read 4, iclass 32, count 0 2006.197.07:42:00.82#ibcon#read 4, iclass 32, count 0 2006.197.07:42:00.82#ibcon#about to read 5, iclass 32, count 0 2006.197.07:42:00.82#ibcon#read 5, iclass 32, count 0 2006.197.07:42:00.82#ibcon#about to read 6, iclass 32, count 0 2006.197.07:42:00.82#ibcon#read 6, iclass 32, count 0 2006.197.07:42:00.82#ibcon#end of sib2, iclass 32, count 0 2006.197.07:42:00.82#ibcon#*after write, iclass 32, count 0 2006.197.07:42:00.82#ibcon#*before return 0, iclass 32, count 0 2006.197.07:42:00.82#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.197.07:42:00.82#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.197.07:42:00.82#ibcon#about to clear, iclass 32 cls_cnt 0 2006.197.07:42:00.82#ibcon#cleared, iclass 32 cls_cnt 0 2006.197.07:42:00.82$vc4f8/vblo=3,656.99 2006.197.07:42:00.82#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.197.07:42:00.82#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.197.07:42:00.82#ibcon#ireg 17 cls_cnt 0 2006.197.07:42:00.82#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.197.07:42:00.82#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.197.07:42:00.82#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.197.07:42:00.82#ibcon#enter wrdev, iclass 34, count 0 2006.197.07:42:00.82#ibcon#first serial, iclass 34, count 0 2006.197.07:42:00.82#ibcon#enter sib2, iclass 34, count 0 2006.197.07:42:00.82#ibcon#flushed, iclass 34, count 0 2006.197.07:42:00.82#ibcon#about to write, iclass 34, count 0 2006.197.07:42:00.82#ibcon#wrote, iclass 34, count 0 2006.197.07:42:00.82#ibcon#about to read 3, iclass 34, count 0 2006.197.07:42:00.84#ibcon#read 3, iclass 34, count 0 2006.197.07:42:00.84#ibcon#about to read 4, iclass 34, count 0 2006.197.07:42:00.84#ibcon#read 4, iclass 34, count 0 2006.197.07:42:00.84#ibcon#about to read 5, iclass 34, count 0 2006.197.07:42:00.84#ibcon#read 5, iclass 34, count 0 2006.197.07:42:00.84#ibcon#about to read 6, iclass 34, count 0 2006.197.07:42:00.84#ibcon#read 6, iclass 34, count 0 2006.197.07:42:00.84#ibcon#end of sib2, iclass 34, count 0 2006.197.07:42:00.84#ibcon#*mode == 0, iclass 34, count 0 2006.197.07:42:00.84#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.197.07:42:00.84#ibcon#[28=FRQ=03,656.99\r\n] 2006.197.07:42:00.84#ibcon#*before write, iclass 34, count 0 2006.197.07:42:00.84#ibcon#enter sib2, iclass 34, count 0 2006.197.07:42:00.84#ibcon#flushed, iclass 34, count 0 2006.197.07:42:00.84#ibcon#about to write, iclass 34, count 0 2006.197.07:42:00.84#ibcon#wrote, iclass 34, count 0 2006.197.07:42:00.84#ibcon#about to read 3, iclass 34, count 0 2006.197.07:42:00.88#ibcon#read 3, iclass 34, count 0 2006.197.07:42:00.88#ibcon#about to read 4, iclass 34, count 0 2006.197.07:42:00.88#ibcon#read 4, iclass 34, count 0 2006.197.07:42:00.88#ibcon#about to read 5, iclass 34, count 0 2006.197.07:42:00.88#ibcon#read 5, iclass 34, count 0 2006.197.07:42:00.88#ibcon#about to read 6, iclass 34, count 0 2006.197.07:42:00.88#ibcon#read 6, iclass 34, count 0 2006.197.07:42:00.88#ibcon#end of sib2, iclass 34, count 0 2006.197.07:42:00.88#ibcon#*after write, iclass 34, count 0 2006.197.07:42:00.88#ibcon#*before return 0, iclass 34, count 0 2006.197.07:42:00.88#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.197.07:42:00.88#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.197.07:42:00.88#ibcon#about to clear, iclass 34 cls_cnt 0 2006.197.07:42:00.88#ibcon#cleared, iclass 34 cls_cnt 0 2006.197.07:42:00.88$vc4f8/vb=3,4 2006.197.07:42:00.88#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.197.07:42:00.88#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.197.07:42:00.88#ibcon#ireg 11 cls_cnt 2 2006.197.07:42:00.88#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.197.07:42:00.94#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.197.07:42:00.94#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.197.07:42:00.94#ibcon#enter wrdev, iclass 36, count 2 2006.197.07:42:00.94#ibcon#first serial, iclass 36, count 2 2006.197.07:42:00.94#ibcon#enter sib2, iclass 36, count 2 2006.197.07:42:00.94#ibcon#flushed, iclass 36, count 2 2006.197.07:42:00.94#ibcon#about to write, iclass 36, count 2 2006.197.07:42:00.94#ibcon#wrote, iclass 36, count 2 2006.197.07:42:00.94#ibcon#about to read 3, iclass 36, count 2 2006.197.07:42:00.96#ibcon#read 3, iclass 36, count 2 2006.197.07:42:00.96#ibcon#about to read 4, iclass 36, count 2 2006.197.07:42:00.96#ibcon#read 4, iclass 36, count 2 2006.197.07:42:00.96#ibcon#about to read 5, iclass 36, count 2 2006.197.07:42:00.96#ibcon#read 5, iclass 36, count 2 2006.197.07:42:00.96#ibcon#about to read 6, iclass 36, count 2 2006.197.07:42:00.96#ibcon#read 6, iclass 36, count 2 2006.197.07:42:00.96#ibcon#end of sib2, iclass 36, count 2 2006.197.07:42:00.96#ibcon#*mode == 0, iclass 36, count 2 2006.197.07:42:00.96#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.197.07:42:00.96#ibcon#[27=AT03-04\r\n] 2006.197.07:42:00.96#ibcon#*before write, iclass 36, count 2 2006.197.07:42:00.96#ibcon#enter sib2, iclass 36, count 2 2006.197.07:42:00.96#ibcon#flushed, iclass 36, count 2 2006.197.07:42:00.96#ibcon#about to write, iclass 36, count 2 2006.197.07:42:00.96#ibcon#wrote, iclass 36, count 2 2006.197.07:42:00.96#ibcon#about to read 3, iclass 36, count 2 2006.197.07:42:00.99#ibcon#read 3, iclass 36, count 2 2006.197.07:42:00.99#ibcon#about to read 4, iclass 36, count 2 2006.197.07:42:00.99#ibcon#read 4, iclass 36, count 2 2006.197.07:42:00.99#ibcon#about to read 5, iclass 36, count 2 2006.197.07:42:00.99#ibcon#read 5, iclass 36, count 2 2006.197.07:42:00.99#ibcon#about to read 6, iclass 36, count 2 2006.197.07:42:00.99#ibcon#read 6, iclass 36, count 2 2006.197.07:42:00.99#ibcon#end of sib2, iclass 36, count 2 2006.197.07:42:00.99#ibcon#*after write, iclass 36, count 2 2006.197.07:42:00.99#ibcon#*before return 0, iclass 36, count 2 2006.197.07:42:00.99#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.197.07:42:00.99#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.197.07:42:00.99#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.197.07:42:00.99#ibcon#ireg 7 cls_cnt 0 2006.197.07:42:00.99#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.197.07:42:01.11#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.197.07:42:01.11#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.197.07:42:01.11#ibcon#enter wrdev, iclass 36, count 0 2006.197.07:42:01.11#ibcon#first serial, iclass 36, count 0 2006.197.07:42:01.11#ibcon#enter sib2, iclass 36, count 0 2006.197.07:42:01.11#ibcon#flushed, iclass 36, count 0 2006.197.07:42:01.11#ibcon#about to write, iclass 36, count 0 2006.197.07:42:01.11#ibcon#wrote, iclass 36, count 0 2006.197.07:42:01.11#ibcon#about to read 3, iclass 36, count 0 2006.197.07:42:01.13#ibcon#read 3, iclass 36, count 0 2006.197.07:42:01.13#ibcon#about to read 4, iclass 36, count 0 2006.197.07:42:01.13#ibcon#read 4, iclass 36, count 0 2006.197.07:42:01.13#ibcon#about to read 5, iclass 36, count 0 2006.197.07:42:01.13#ibcon#read 5, iclass 36, count 0 2006.197.07:42:01.13#ibcon#about to read 6, iclass 36, count 0 2006.197.07:42:01.13#ibcon#read 6, iclass 36, count 0 2006.197.07:42:01.13#ibcon#end of sib2, iclass 36, count 0 2006.197.07:42:01.13#ibcon#*mode == 0, iclass 36, count 0 2006.197.07:42:01.13#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.197.07:42:01.13#ibcon#[27=USB\r\n] 2006.197.07:42:01.13#ibcon#*before write, iclass 36, count 0 2006.197.07:42:01.13#ibcon#enter sib2, iclass 36, count 0 2006.197.07:42:01.13#ibcon#flushed, iclass 36, count 0 2006.197.07:42:01.13#ibcon#about to write, iclass 36, count 0 2006.197.07:42:01.13#ibcon#wrote, iclass 36, count 0 2006.197.07:42:01.13#ibcon#about to read 3, iclass 36, count 0 2006.197.07:42:01.16#ibcon#read 3, iclass 36, count 0 2006.197.07:42:01.16#ibcon#about to read 4, iclass 36, count 0 2006.197.07:42:01.16#ibcon#read 4, iclass 36, count 0 2006.197.07:42:01.16#ibcon#about to read 5, iclass 36, count 0 2006.197.07:42:01.16#ibcon#read 5, iclass 36, count 0 2006.197.07:42:01.16#ibcon#about to read 6, iclass 36, count 0 2006.197.07:42:01.16#ibcon#read 6, iclass 36, count 0 2006.197.07:42:01.16#ibcon#end of sib2, iclass 36, count 0 2006.197.07:42:01.16#ibcon#*after write, iclass 36, count 0 2006.197.07:42:01.16#ibcon#*before return 0, iclass 36, count 0 2006.197.07:42:01.16#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.197.07:42:01.16#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.197.07:42:01.16#ibcon#about to clear, iclass 36 cls_cnt 0 2006.197.07:42:01.16#ibcon#cleared, iclass 36 cls_cnt 0 2006.197.07:42:01.16$vc4f8/vblo=4,712.99 2006.197.07:42:01.16#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.197.07:42:01.16#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.197.07:42:01.16#ibcon#ireg 17 cls_cnt 0 2006.197.07:42:01.16#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.197.07:42:01.16#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.197.07:42:01.16#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.197.07:42:01.16#ibcon#enter wrdev, iclass 38, count 0 2006.197.07:42:01.16#ibcon#first serial, iclass 38, count 0 2006.197.07:42:01.16#ibcon#enter sib2, iclass 38, count 0 2006.197.07:42:01.16#ibcon#flushed, iclass 38, count 0 2006.197.07:42:01.16#ibcon#about to write, iclass 38, count 0 2006.197.07:42:01.16#ibcon#wrote, iclass 38, count 0 2006.197.07:42:01.16#ibcon#about to read 3, iclass 38, count 0 2006.197.07:42:01.18#ibcon#read 3, iclass 38, count 0 2006.197.07:42:01.18#ibcon#about to read 4, iclass 38, count 0 2006.197.07:42:01.18#ibcon#read 4, iclass 38, count 0 2006.197.07:42:01.18#ibcon#about to read 5, iclass 38, count 0 2006.197.07:42:01.18#ibcon#read 5, iclass 38, count 0 2006.197.07:42:01.18#ibcon#about to read 6, iclass 38, count 0 2006.197.07:42:01.18#ibcon#read 6, iclass 38, count 0 2006.197.07:42:01.18#ibcon#end of sib2, iclass 38, count 0 2006.197.07:42:01.18#ibcon#*mode == 0, iclass 38, count 0 2006.197.07:42:01.18#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.197.07:42:01.18#ibcon#[28=FRQ=04,712.99\r\n] 2006.197.07:42:01.18#ibcon#*before write, iclass 38, count 0 2006.197.07:42:01.18#ibcon#enter sib2, iclass 38, count 0 2006.197.07:42:01.18#ibcon#flushed, iclass 38, count 0 2006.197.07:42:01.18#ibcon#about to write, iclass 38, count 0 2006.197.07:42:01.18#ibcon#wrote, iclass 38, count 0 2006.197.07:42:01.18#ibcon#about to read 3, iclass 38, count 0 2006.197.07:42:01.22#ibcon#read 3, iclass 38, count 0 2006.197.07:42:01.22#ibcon#about to read 4, iclass 38, count 0 2006.197.07:42:01.22#ibcon#read 4, iclass 38, count 0 2006.197.07:42:01.22#ibcon#about to read 5, iclass 38, count 0 2006.197.07:42:01.22#ibcon#read 5, iclass 38, count 0 2006.197.07:42:01.22#ibcon#about to read 6, iclass 38, count 0 2006.197.07:42:01.22#ibcon#read 6, iclass 38, count 0 2006.197.07:42:01.22#ibcon#end of sib2, iclass 38, count 0 2006.197.07:42:01.22#ibcon#*after write, iclass 38, count 0 2006.197.07:42:01.22#ibcon#*before return 0, iclass 38, count 0 2006.197.07:42:01.22#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.197.07:42:01.22#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.197.07:42:01.22#ibcon#about to clear, iclass 38 cls_cnt 0 2006.197.07:42:01.22#ibcon#cleared, iclass 38 cls_cnt 0 2006.197.07:42:01.22$vc4f8/vb=4,4 2006.197.07:42:01.22#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.197.07:42:01.22#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.197.07:42:01.22#ibcon#ireg 11 cls_cnt 2 2006.197.07:42:01.22#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.197.07:42:01.28#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.197.07:42:01.28#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.197.07:42:01.28#ibcon#enter wrdev, iclass 40, count 2 2006.197.07:42:01.28#ibcon#first serial, iclass 40, count 2 2006.197.07:42:01.28#ibcon#enter sib2, iclass 40, count 2 2006.197.07:42:01.28#ibcon#flushed, iclass 40, count 2 2006.197.07:42:01.28#ibcon#about to write, iclass 40, count 2 2006.197.07:42:01.28#ibcon#wrote, iclass 40, count 2 2006.197.07:42:01.28#ibcon#about to read 3, iclass 40, count 2 2006.197.07:42:01.30#ibcon#read 3, iclass 40, count 2 2006.197.07:42:01.30#ibcon#about to read 4, iclass 40, count 2 2006.197.07:42:01.30#ibcon#read 4, iclass 40, count 2 2006.197.07:42:01.30#ibcon#about to read 5, iclass 40, count 2 2006.197.07:42:01.30#ibcon#read 5, iclass 40, count 2 2006.197.07:42:01.30#ibcon#about to read 6, iclass 40, count 2 2006.197.07:42:01.30#ibcon#read 6, iclass 40, count 2 2006.197.07:42:01.30#ibcon#end of sib2, iclass 40, count 2 2006.197.07:42:01.30#ibcon#*mode == 0, iclass 40, count 2 2006.197.07:42:01.30#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.197.07:42:01.30#ibcon#[27=AT04-04\r\n] 2006.197.07:42:01.30#ibcon#*before write, iclass 40, count 2 2006.197.07:42:01.30#ibcon#enter sib2, iclass 40, count 2 2006.197.07:42:01.30#ibcon#flushed, iclass 40, count 2 2006.197.07:42:01.30#ibcon#about to write, iclass 40, count 2 2006.197.07:42:01.30#ibcon#wrote, iclass 40, count 2 2006.197.07:42:01.30#ibcon#about to read 3, iclass 40, count 2 2006.197.07:42:01.33#ibcon#read 3, iclass 40, count 2 2006.197.07:42:01.33#ibcon#about to read 4, iclass 40, count 2 2006.197.07:42:01.33#ibcon#read 4, iclass 40, count 2 2006.197.07:42:01.33#ibcon#about to read 5, iclass 40, count 2 2006.197.07:42:01.33#ibcon#read 5, iclass 40, count 2 2006.197.07:42:01.33#ibcon#about to read 6, iclass 40, count 2 2006.197.07:42:01.33#ibcon#read 6, iclass 40, count 2 2006.197.07:42:01.33#ibcon#end of sib2, iclass 40, count 2 2006.197.07:42:01.33#ibcon#*after write, iclass 40, count 2 2006.197.07:42:01.33#ibcon#*before return 0, iclass 40, count 2 2006.197.07:42:01.33#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.197.07:42:01.33#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.197.07:42:01.33#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.197.07:42:01.33#ibcon#ireg 7 cls_cnt 0 2006.197.07:42:01.33#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.197.07:42:01.45#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.197.07:42:01.45#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.197.07:42:01.45#ibcon#enter wrdev, iclass 40, count 0 2006.197.07:42:01.45#ibcon#first serial, iclass 40, count 0 2006.197.07:42:01.45#ibcon#enter sib2, iclass 40, count 0 2006.197.07:42:01.45#ibcon#flushed, iclass 40, count 0 2006.197.07:42:01.45#ibcon#about to write, iclass 40, count 0 2006.197.07:42:01.45#ibcon#wrote, iclass 40, count 0 2006.197.07:42:01.45#ibcon#about to read 3, iclass 40, count 0 2006.197.07:42:01.47#ibcon#read 3, iclass 40, count 0 2006.197.07:42:01.47#ibcon#about to read 4, iclass 40, count 0 2006.197.07:42:01.47#ibcon#read 4, iclass 40, count 0 2006.197.07:42:01.47#ibcon#about to read 5, iclass 40, count 0 2006.197.07:42:01.47#ibcon#read 5, iclass 40, count 0 2006.197.07:42:01.47#ibcon#about to read 6, iclass 40, count 0 2006.197.07:42:01.47#ibcon#read 6, iclass 40, count 0 2006.197.07:42:01.47#ibcon#end of sib2, iclass 40, count 0 2006.197.07:42:01.47#ibcon#*mode == 0, iclass 40, count 0 2006.197.07:42:01.47#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.197.07:42:01.47#ibcon#[27=USB\r\n] 2006.197.07:42:01.47#ibcon#*before write, iclass 40, count 0 2006.197.07:42:01.47#ibcon#enter sib2, iclass 40, count 0 2006.197.07:42:01.47#ibcon#flushed, iclass 40, count 0 2006.197.07:42:01.47#ibcon#about to write, iclass 40, count 0 2006.197.07:42:01.47#ibcon#wrote, iclass 40, count 0 2006.197.07:42:01.47#ibcon#about to read 3, iclass 40, count 0 2006.197.07:42:01.50#ibcon#read 3, iclass 40, count 0 2006.197.07:42:01.50#ibcon#about to read 4, iclass 40, count 0 2006.197.07:42:01.50#ibcon#read 4, iclass 40, count 0 2006.197.07:42:01.50#ibcon#about to read 5, iclass 40, count 0 2006.197.07:42:01.50#ibcon#read 5, iclass 40, count 0 2006.197.07:42:01.50#ibcon#about to read 6, iclass 40, count 0 2006.197.07:42:01.50#ibcon#read 6, iclass 40, count 0 2006.197.07:42:01.50#ibcon#end of sib2, iclass 40, count 0 2006.197.07:42:01.50#ibcon#*after write, iclass 40, count 0 2006.197.07:42:01.50#ibcon#*before return 0, iclass 40, count 0 2006.197.07:42:01.50#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.197.07:42:01.50#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.197.07:42:01.50#ibcon#about to clear, iclass 40 cls_cnt 0 2006.197.07:42:01.50#ibcon#cleared, iclass 40 cls_cnt 0 2006.197.07:42:01.50$vc4f8/vblo=5,744.99 2006.197.07:42:01.50#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.197.07:42:01.50#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.197.07:42:01.50#ibcon#ireg 17 cls_cnt 0 2006.197.07:42:01.50#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.197.07:42:01.50#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.197.07:42:01.50#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.197.07:42:01.50#ibcon#enter wrdev, iclass 4, count 0 2006.197.07:42:01.50#ibcon#first serial, iclass 4, count 0 2006.197.07:42:01.50#ibcon#enter sib2, iclass 4, count 0 2006.197.07:42:01.50#ibcon#flushed, iclass 4, count 0 2006.197.07:42:01.50#ibcon#about to write, iclass 4, count 0 2006.197.07:42:01.50#ibcon#wrote, iclass 4, count 0 2006.197.07:42:01.50#ibcon#about to read 3, iclass 4, count 0 2006.197.07:42:01.52#ibcon#read 3, iclass 4, count 0 2006.197.07:42:01.52#ibcon#about to read 4, iclass 4, count 0 2006.197.07:42:01.52#ibcon#read 4, iclass 4, count 0 2006.197.07:42:01.52#ibcon#about to read 5, iclass 4, count 0 2006.197.07:42:01.52#ibcon#read 5, iclass 4, count 0 2006.197.07:42:01.52#ibcon#about to read 6, iclass 4, count 0 2006.197.07:42:01.52#ibcon#read 6, iclass 4, count 0 2006.197.07:42:01.52#ibcon#end of sib2, iclass 4, count 0 2006.197.07:42:01.52#ibcon#*mode == 0, iclass 4, count 0 2006.197.07:42:01.52#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.197.07:42:01.52#ibcon#[28=FRQ=05,744.99\r\n] 2006.197.07:42:01.52#ibcon#*before write, iclass 4, count 0 2006.197.07:42:01.52#ibcon#enter sib2, iclass 4, count 0 2006.197.07:42:01.52#ibcon#flushed, iclass 4, count 0 2006.197.07:42:01.52#ibcon#about to write, iclass 4, count 0 2006.197.07:42:01.52#ibcon#wrote, iclass 4, count 0 2006.197.07:42:01.52#ibcon#about to read 3, iclass 4, count 0 2006.197.07:42:01.56#ibcon#read 3, iclass 4, count 0 2006.197.07:42:01.56#ibcon#about to read 4, iclass 4, count 0 2006.197.07:42:01.56#ibcon#read 4, iclass 4, count 0 2006.197.07:42:01.56#ibcon#about to read 5, iclass 4, count 0 2006.197.07:42:01.56#ibcon#read 5, iclass 4, count 0 2006.197.07:42:01.56#ibcon#about to read 6, iclass 4, count 0 2006.197.07:42:01.56#ibcon#read 6, iclass 4, count 0 2006.197.07:42:01.56#ibcon#end of sib2, iclass 4, count 0 2006.197.07:42:01.56#ibcon#*after write, iclass 4, count 0 2006.197.07:42:01.56#ibcon#*before return 0, iclass 4, count 0 2006.197.07:42:01.56#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.197.07:42:01.56#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.197.07:42:01.56#ibcon#about to clear, iclass 4 cls_cnt 0 2006.197.07:42:01.56#ibcon#cleared, iclass 4 cls_cnt 0 2006.197.07:42:01.56$vc4f8/vb=5,4 2006.197.07:42:01.56#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.197.07:42:01.56#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.197.07:42:01.56#ibcon#ireg 11 cls_cnt 2 2006.197.07:42:01.56#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.197.07:42:01.62#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.197.07:42:01.62#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.197.07:42:01.62#ibcon#enter wrdev, iclass 6, count 2 2006.197.07:42:01.62#ibcon#first serial, iclass 6, count 2 2006.197.07:42:01.62#ibcon#enter sib2, iclass 6, count 2 2006.197.07:42:01.62#ibcon#flushed, iclass 6, count 2 2006.197.07:42:01.62#ibcon#about to write, iclass 6, count 2 2006.197.07:42:01.62#ibcon#wrote, iclass 6, count 2 2006.197.07:42:01.62#ibcon#about to read 3, iclass 6, count 2 2006.197.07:42:01.64#ibcon#read 3, iclass 6, count 2 2006.197.07:42:01.64#ibcon#about to read 4, iclass 6, count 2 2006.197.07:42:01.64#ibcon#read 4, iclass 6, count 2 2006.197.07:42:01.64#ibcon#about to read 5, iclass 6, count 2 2006.197.07:42:01.64#ibcon#read 5, iclass 6, count 2 2006.197.07:42:01.64#ibcon#about to read 6, iclass 6, count 2 2006.197.07:42:01.64#ibcon#read 6, iclass 6, count 2 2006.197.07:42:01.64#ibcon#end of sib2, iclass 6, count 2 2006.197.07:42:01.64#ibcon#*mode == 0, iclass 6, count 2 2006.197.07:42:01.64#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.197.07:42:01.64#ibcon#[27=AT05-04\r\n] 2006.197.07:42:01.64#ibcon#*before write, iclass 6, count 2 2006.197.07:42:01.64#ibcon#enter sib2, iclass 6, count 2 2006.197.07:42:01.64#ibcon#flushed, iclass 6, count 2 2006.197.07:42:01.64#ibcon#about to write, iclass 6, count 2 2006.197.07:42:01.64#ibcon#wrote, iclass 6, count 2 2006.197.07:42:01.64#ibcon#about to read 3, iclass 6, count 2 2006.197.07:42:01.67#ibcon#read 3, iclass 6, count 2 2006.197.07:42:01.67#ibcon#about to read 4, iclass 6, count 2 2006.197.07:42:01.67#ibcon#read 4, iclass 6, count 2 2006.197.07:42:01.67#ibcon#about to read 5, iclass 6, count 2 2006.197.07:42:01.67#ibcon#read 5, iclass 6, count 2 2006.197.07:42:01.67#ibcon#about to read 6, iclass 6, count 2 2006.197.07:42:01.67#ibcon#read 6, iclass 6, count 2 2006.197.07:42:01.67#ibcon#end of sib2, iclass 6, count 2 2006.197.07:42:01.67#ibcon#*after write, iclass 6, count 2 2006.197.07:42:01.67#ibcon#*before return 0, iclass 6, count 2 2006.197.07:42:01.67#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.197.07:42:01.67#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.197.07:42:01.67#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.197.07:42:01.67#ibcon#ireg 7 cls_cnt 0 2006.197.07:42:01.67#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.197.07:42:01.79#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.197.07:42:01.79#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.197.07:42:01.79#ibcon#enter wrdev, iclass 6, count 0 2006.197.07:42:01.79#ibcon#first serial, iclass 6, count 0 2006.197.07:42:01.79#ibcon#enter sib2, iclass 6, count 0 2006.197.07:42:01.79#ibcon#flushed, iclass 6, count 0 2006.197.07:42:01.79#ibcon#about to write, iclass 6, count 0 2006.197.07:42:01.79#ibcon#wrote, iclass 6, count 0 2006.197.07:42:01.79#ibcon#about to read 3, iclass 6, count 0 2006.197.07:42:01.81#ibcon#read 3, iclass 6, count 0 2006.197.07:42:01.81#ibcon#about to read 4, iclass 6, count 0 2006.197.07:42:01.81#ibcon#read 4, iclass 6, count 0 2006.197.07:42:01.81#ibcon#about to read 5, iclass 6, count 0 2006.197.07:42:01.81#ibcon#read 5, iclass 6, count 0 2006.197.07:42:01.81#ibcon#about to read 6, iclass 6, count 0 2006.197.07:42:01.81#ibcon#read 6, iclass 6, count 0 2006.197.07:42:01.81#ibcon#end of sib2, iclass 6, count 0 2006.197.07:42:01.81#ibcon#*mode == 0, iclass 6, count 0 2006.197.07:42:01.81#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.197.07:42:01.81#ibcon#[27=USB\r\n] 2006.197.07:42:01.81#ibcon#*before write, iclass 6, count 0 2006.197.07:42:01.81#ibcon#enter sib2, iclass 6, count 0 2006.197.07:42:01.81#ibcon#flushed, iclass 6, count 0 2006.197.07:42:01.81#ibcon#about to write, iclass 6, count 0 2006.197.07:42:01.81#ibcon#wrote, iclass 6, count 0 2006.197.07:42:01.81#ibcon#about to read 3, iclass 6, count 0 2006.197.07:42:01.84#ibcon#read 3, iclass 6, count 0 2006.197.07:42:01.84#ibcon#about to read 4, iclass 6, count 0 2006.197.07:42:01.84#ibcon#read 4, iclass 6, count 0 2006.197.07:42:01.84#ibcon#about to read 5, iclass 6, count 0 2006.197.07:42:01.84#ibcon#read 5, iclass 6, count 0 2006.197.07:42:01.84#ibcon#about to read 6, iclass 6, count 0 2006.197.07:42:01.84#ibcon#read 6, iclass 6, count 0 2006.197.07:42:01.84#ibcon#end of sib2, iclass 6, count 0 2006.197.07:42:01.84#ibcon#*after write, iclass 6, count 0 2006.197.07:42:01.84#ibcon#*before return 0, iclass 6, count 0 2006.197.07:42:01.84#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.197.07:42:01.84#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.197.07:42:01.84#ibcon#about to clear, iclass 6 cls_cnt 0 2006.197.07:42:01.84#ibcon#cleared, iclass 6 cls_cnt 0 2006.197.07:42:01.84$vc4f8/vblo=6,752.99 2006.197.07:42:01.84#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.197.07:42:01.84#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.197.07:42:01.84#ibcon#ireg 17 cls_cnt 0 2006.197.07:42:01.84#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.197.07:42:01.84#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.197.07:42:01.84#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.197.07:42:01.84#ibcon#enter wrdev, iclass 10, count 0 2006.197.07:42:01.84#ibcon#first serial, iclass 10, count 0 2006.197.07:42:01.84#ibcon#enter sib2, iclass 10, count 0 2006.197.07:42:01.84#ibcon#flushed, iclass 10, count 0 2006.197.07:42:01.84#ibcon#about to write, iclass 10, count 0 2006.197.07:42:01.84#ibcon#wrote, iclass 10, count 0 2006.197.07:42:01.84#ibcon#about to read 3, iclass 10, count 0 2006.197.07:42:01.86#ibcon#read 3, iclass 10, count 0 2006.197.07:42:01.86#ibcon#about to read 4, iclass 10, count 0 2006.197.07:42:01.86#ibcon#read 4, iclass 10, count 0 2006.197.07:42:01.86#ibcon#about to read 5, iclass 10, count 0 2006.197.07:42:01.86#ibcon#read 5, iclass 10, count 0 2006.197.07:42:01.86#ibcon#about to read 6, iclass 10, count 0 2006.197.07:42:01.86#ibcon#read 6, iclass 10, count 0 2006.197.07:42:01.86#ibcon#end of sib2, iclass 10, count 0 2006.197.07:42:01.86#ibcon#*mode == 0, iclass 10, count 0 2006.197.07:42:01.86#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.197.07:42:01.86#ibcon#[28=FRQ=06,752.99\r\n] 2006.197.07:42:01.86#ibcon#*before write, iclass 10, count 0 2006.197.07:42:01.86#ibcon#enter sib2, iclass 10, count 0 2006.197.07:42:01.86#ibcon#flushed, iclass 10, count 0 2006.197.07:42:01.86#ibcon#about to write, iclass 10, count 0 2006.197.07:42:01.86#ibcon#wrote, iclass 10, count 0 2006.197.07:42:01.86#ibcon#about to read 3, iclass 10, count 0 2006.197.07:42:01.90#ibcon#read 3, iclass 10, count 0 2006.197.07:42:01.90#ibcon#about to read 4, iclass 10, count 0 2006.197.07:42:01.90#ibcon#read 4, iclass 10, count 0 2006.197.07:42:01.90#ibcon#about to read 5, iclass 10, count 0 2006.197.07:42:01.90#ibcon#read 5, iclass 10, count 0 2006.197.07:42:01.90#ibcon#about to read 6, iclass 10, count 0 2006.197.07:42:01.90#ibcon#read 6, iclass 10, count 0 2006.197.07:42:01.90#ibcon#end of sib2, iclass 10, count 0 2006.197.07:42:01.90#ibcon#*after write, iclass 10, count 0 2006.197.07:42:01.90#ibcon#*before return 0, iclass 10, count 0 2006.197.07:42:01.90#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.197.07:42:01.90#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.197.07:42:01.90#ibcon#about to clear, iclass 10 cls_cnt 0 2006.197.07:42:01.90#ibcon#cleared, iclass 10 cls_cnt 0 2006.197.07:42:01.90$vc4f8/vb=6,4 2006.197.07:42:01.90#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.197.07:42:01.90#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.197.07:42:01.90#ibcon#ireg 11 cls_cnt 2 2006.197.07:42:01.90#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.197.07:42:01.96#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.197.07:42:01.96#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.197.07:42:01.96#ibcon#enter wrdev, iclass 12, count 2 2006.197.07:42:01.96#ibcon#first serial, iclass 12, count 2 2006.197.07:42:01.96#ibcon#enter sib2, iclass 12, count 2 2006.197.07:42:01.96#ibcon#flushed, iclass 12, count 2 2006.197.07:42:01.96#ibcon#about to write, iclass 12, count 2 2006.197.07:42:01.96#ibcon#wrote, iclass 12, count 2 2006.197.07:42:01.96#ibcon#about to read 3, iclass 12, count 2 2006.197.07:42:01.98#ibcon#read 3, iclass 12, count 2 2006.197.07:42:01.98#ibcon#about to read 4, iclass 12, count 2 2006.197.07:42:01.98#ibcon#read 4, iclass 12, count 2 2006.197.07:42:01.98#ibcon#about to read 5, iclass 12, count 2 2006.197.07:42:01.98#ibcon#read 5, iclass 12, count 2 2006.197.07:42:01.98#ibcon#about to read 6, iclass 12, count 2 2006.197.07:42:01.98#ibcon#read 6, iclass 12, count 2 2006.197.07:42:01.98#ibcon#end of sib2, iclass 12, count 2 2006.197.07:42:01.98#ibcon#*mode == 0, iclass 12, count 2 2006.197.07:42:01.98#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.197.07:42:01.98#ibcon#[27=AT06-04\r\n] 2006.197.07:42:01.98#ibcon#*before write, iclass 12, count 2 2006.197.07:42:01.98#ibcon#enter sib2, iclass 12, count 2 2006.197.07:42:01.98#ibcon#flushed, iclass 12, count 2 2006.197.07:42:01.98#ibcon#about to write, iclass 12, count 2 2006.197.07:42:01.98#ibcon#wrote, iclass 12, count 2 2006.197.07:42:01.98#ibcon#about to read 3, iclass 12, count 2 2006.197.07:42:02.01#ibcon#read 3, iclass 12, count 2 2006.197.07:42:02.01#ibcon#about to read 4, iclass 12, count 2 2006.197.07:42:02.01#ibcon#read 4, iclass 12, count 2 2006.197.07:42:02.01#ibcon#about to read 5, iclass 12, count 2 2006.197.07:42:02.01#ibcon#read 5, iclass 12, count 2 2006.197.07:42:02.01#ibcon#about to read 6, iclass 12, count 2 2006.197.07:42:02.01#ibcon#read 6, iclass 12, count 2 2006.197.07:42:02.01#ibcon#end of sib2, iclass 12, count 2 2006.197.07:42:02.01#ibcon#*after write, iclass 12, count 2 2006.197.07:42:02.01#ibcon#*before return 0, iclass 12, count 2 2006.197.07:42:02.01#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.197.07:42:02.01#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.197.07:42:02.01#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.197.07:42:02.01#ibcon#ireg 7 cls_cnt 0 2006.197.07:42:02.01#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.197.07:42:02.13#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.197.07:42:02.13#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.197.07:42:02.13#ibcon#enter wrdev, iclass 12, count 0 2006.197.07:42:02.13#ibcon#first serial, iclass 12, count 0 2006.197.07:42:02.13#ibcon#enter sib2, iclass 12, count 0 2006.197.07:42:02.13#ibcon#flushed, iclass 12, count 0 2006.197.07:42:02.13#ibcon#about to write, iclass 12, count 0 2006.197.07:42:02.13#ibcon#wrote, iclass 12, count 0 2006.197.07:42:02.13#ibcon#about to read 3, iclass 12, count 0 2006.197.07:42:02.15#ibcon#read 3, iclass 12, count 0 2006.197.07:42:02.15#ibcon#about to read 4, iclass 12, count 0 2006.197.07:42:02.15#ibcon#read 4, iclass 12, count 0 2006.197.07:42:02.15#ibcon#about to read 5, iclass 12, count 0 2006.197.07:42:02.15#ibcon#read 5, iclass 12, count 0 2006.197.07:42:02.15#ibcon#about to read 6, iclass 12, count 0 2006.197.07:42:02.15#ibcon#read 6, iclass 12, count 0 2006.197.07:42:02.15#ibcon#end of sib2, iclass 12, count 0 2006.197.07:42:02.15#ibcon#*mode == 0, iclass 12, count 0 2006.197.07:42:02.15#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.197.07:42:02.15#ibcon#[27=USB\r\n] 2006.197.07:42:02.15#ibcon#*before write, iclass 12, count 0 2006.197.07:42:02.15#ibcon#enter sib2, iclass 12, count 0 2006.197.07:42:02.15#ibcon#flushed, iclass 12, count 0 2006.197.07:42:02.15#ibcon#about to write, iclass 12, count 0 2006.197.07:42:02.15#ibcon#wrote, iclass 12, count 0 2006.197.07:42:02.15#ibcon#about to read 3, iclass 12, count 0 2006.197.07:42:02.18#ibcon#read 3, iclass 12, count 0 2006.197.07:42:02.18#ibcon#about to read 4, iclass 12, count 0 2006.197.07:42:02.18#ibcon#read 4, iclass 12, count 0 2006.197.07:42:02.18#ibcon#about to read 5, iclass 12, count 0 2006.197.07:42:02.18#ibcon#read 5, iclass 12, count 0 2006.197.07:42:02.18#ibcon#about to read 6, iclass 12, count 0 2006.197.07:42:02.18#ibcon#read 6, iclass 12, count 0 2006.197.07:42:02.18#ibcon#end of sib2, iclass 12, count 0 2006.197.07:42:02.18#ibcon#*after write, iclass 12, count 0 2006.197.07:42:02.18#ibcon#*before return 0, iclass 12, count 0 2006.197.07:42:02.18#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.197.07:42:02.18#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.197.07:42:02.18#ibcon#about to clear, iclass 12 cls_cnt 0 2006.197.07:42:02.18#ibcon#cleared, iclass 12 cls_cnt 0 2006.197.07:42:02.18$vc4f8/vabw=wide 2006.197.07:42:02.18#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.197.07:42:02.18#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.197.07:42:02.18#ibcon#ireg 8 cls_cnt 0 2006.197.07:42:02.18#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.197.07:42:02.18#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.197.07:42:02.18#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.197.07:42:02.18#ibcon#enter wrdev, iclass 14, count 0 2006.197.07:42:02.18#ibcon#first serial, iclass 14, count 0 2006.197.07:42:02.18#ibcon#enter sib2, iclass 14, count 0 2006.197.07:42:02.18#ibcon#flushed, iclass 14, count 0 2006.197.07:42:02.18#ibcon#about to write, iclass 14, count 0 2006.197.07:42:02.18#ibcon#wrote, iclass 14, count 0 2006.197.07:42:02.18#ibcon#about to read 3, iclass 14, count 0 2006.197.07:42:02.20#ibcon#read 3, iclass 14, count 0 2006.197.07:42:02.20#ibcon#about to read 4, iclass 14, count 0 2006.197.07:42:02.20#ibcon#read 4, iclass 14, count 0 2006.197.07:42:02.20#ibcon#about to read 5, iclass 14, count 0 2006.197.07:42:02.20#ibcon#read 5, iclass 14, count 0 2006.197.07:42:02.20#ibcon#about to read 6, iclass 14, count 0 2006.197.07:42:02.20#ibcon#read 6, iclass 14, count 0 2006.197.07:42:02.20#ibcon#end of sib2, iclass 14, count 0 2006.197.07:42:02.20#ibcon#*mode == 0, iclass 14, count 0 2006.197.07:42:02.20#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.197.07:42:02.20#ibcon#[25=BW32\r\n] 2006.197.07:42:02.20#ibcon#*before write, iclass 14, count 0 2006.197.07:42:02.20#ibcon#enter sib2, iclass 14, count 0 2006.197.07:42:02.20#ibcon#flushed, iclass 14, count 0 2006.197.07:42:02.20#ibcon#about to write, iclass 14, count 0 2006.197.07:42:02.20#ibcon#wrote, iclass 14, count 0 2006.197.07:42:02.20#ibcon#about to read 3, iclass 14, count 0 2006.197.07:42:02.23#ibcon#read 3, iclass 14, count 0 2006.197.07:42:02.23#ibcon#about to read 4, iclass 14, count 0 2006.197.07:42:02.23#ibcon#read 4, iclass 14, count 0 2006.197.07:42:02.23#ibcon#about to read 5, iclass 14, count 0 2006.197.07:42:02.23#ibcon#read 5, iclass 14, count 0 2006.197.07:42:02.23#ibcon#about to read 6, iclass 14, count 0 2006.197.07:42:02.23#ibcon#read 6, iclass 14, count 0 2006.197.07:42:02.23#ibcon#end of sib2, iclass 14, count 0 2006.197.07:42:02.23#ibcon#*after write, iclass 14, count 0 2006.197.07:42:02.23#ibcon#*before return 0, iclass 14, count 0 2006.197.07:42:02.23#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.197.07:42:02.23#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.197.07:42:02.23#ibcon#about to clear, iclass 14 cls_cnt 0 2006.197.07:42:02.23#ibcon#cleared, iclass 14 cls_cnt 0 2006.197.07:42:02.23$vc4f8/vbbw=wide 2006.197.07:42:02.23#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.197.07:42:02.23#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.197.07:42:02.23#ibcon#ireg 8 cls_cnt 0 2006.197.07:42:02.23#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.197.07:42:02.30#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.197.07:42:02.30#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.197.07:42:02.30#ibcon#enter wrdev, iclass 16, count 0 2006.197.07:42:02.30#ibcon#first serial, iclass 16, count 0 2006.197.07:42:02.30#ibcon#enter sib2, iclass 16, count 0 2006.197.07:42:02.30#ibcon#flushed, iclass 16, count 0 2006.197.07:42:02.30#ibcon#about to write, iclass 16, count 0 2006.197.07:42:02.30#ibcon#wrote, iclass 16, count 0 2006.197.07:42:02.30#ibcon#about to read 3, iclass 16, count 0 2006.197.07:42:02.32#ibcon#read 3, iclass 16, count 0 2006.197.07:42:02.32#ibcon#about to read 4, iclass 16, count 0 2006.197.07:42:02.32#ibcon#read 4, iclass 16, count 0 2006.197.07:42:02.32#ibcon#about to read 5, iclass 16, count 0 2006.197.07:42:02.32#ibcon#read 5, iclass 16, count 0 2006.197.07:42:02.32#ibcon#about to read 6, iclass 16, count 0 2006.197.07:42:02.32#ibcon#read 6, iclass 16, count 0 2006.197.07:42:02.32#ibcon#end of sib2, iclass 16, count 0 2006.197.07:42:02.32#ibcon#*mode == 0, iclass 16, count 0 2006.197.07:42:02.32#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.197.07:42:02.32#ibcon#[27=BW32\r\n] 2006.197.07:42:02.32#ibcon#*before write, iclass 16, count 0 2006.197.07:42:02.32#ibcon#enter sib2, iclass 16, count 0 2006.197.07:42:02.32#ibcon#flushed, iclass 16, count 0 2006.197.07:42:02.32#ibcon#about to write, iclass 16, count 0 2006.197.07:42:02.32#ibcon#wrote, iclass 16, count 0 2006.197.07:42:02.32#ibcon#about to read 3, iclass 16, count 0 2006.197.07:42:02.35#ibcon#read 3, iclass 16, count 0 2006.197.07:42:02.35#ibcon#about to read 4, iclass 16, count 0 2006.197.07:42:02.35#ibcon#read 4, iclass 16, count 0 2006.197.07:42:02.35#ibcon#about to read 5, iclass 16, count 0 2006.197.07:42:02.35#ibcon#read 5, iclass 16, count 0 2006.197.07:42:02.35#ibcon#about to read 6, iclass 16, count 0 2006.197.07:42:02.35#ibcon#read 6, iclass 16, count 0 2006.197.07:42:02.35#ibcon#end of sib2, iclass 16, count 0 2006.197.07:42:02.35#ibcon#*after write, iclass 16, count 0 2006.197.07:42:02.35#ibcon#*before return 0, iclass 16, count 0 2006.197.07:42:02.35#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.197.07:42:02.35#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.197.07:42:02.35#ibcon#about to clear, iclass 16 cls_cnt 0 2006.197.07:42:02.35#ibcon#cleared, iclass 16 cls_cnt 0 2006.197.07:42:02.35$4f8m12a/ifd4f 2006.197.07:42:02.35$ifd4f/lo= 2006.197.07:42:02.35$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.197.07:42:02.35$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.197.07:42:02.35$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.197.07:42:02.35$ifd4f/patch= 2006.197.07:42:02.35$ifd4f/patch=lo1,a1,a2,a3,a4 2006.197.07:42:02.35$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.197.07:42:02.35$ifd4f/patch=lo3,a5,a6,a7,a8 2006.197.07:42:02.35$4f8m12a/"form=m,16.000,1:2 2006.197.07:42:02.35$4f8m12a/"tpicd 2006.197.07:42:02.35$4f8m12a/echo=off 2006.197.07:42:02.35$4f8m12a/xlog=off 2006.197.07:42:02.35:!2006.197.07:43:00 2006.197.07:42:39.14#trakl#Source acquired 2006.197.07:42:39.14#flagr#flagr/antenna,acquired 2006.197.07:43:00.00:preob 2006.197.07:43:01.14/onsource/TRACKING 2006.197.07:43:01.14:!2006.197.07:43:10 2006.197.07:43:10.00:data_valid=on 2006.197.07:43:10.00:midob 2006.197.07:43:10.14/onsource/TRACKING 2006.197.07:43:10.14/wx/25.83,1003.2,97 2006.197.07:43:10.34/cable/+6.3723E-03 2006.197.07:43:11.43/va/01,08,usb,yes,31,33 2006.197.07:43:11.43/va/02,07,usb,yes,31,33 2006.197.07:43:11.43/va/03,06,usb,yes,33,33 2006.197.07:43:11.43/va/04,07,usb,yes,32,34 2006.197.07:43:11.43/va/05,07,usb,yes,36,38 2006.197.07:43:11.43/va/06,06,usb,yes,35,35 2006.197.07:43:11.43/va/07,06,usb,yes,35,35 2006.197.07:43:11.43/va/08,07,usb,yes,34,33 2006.197.07:43:11.66/valo/01,532.99,yes,locked 2006.197.07:43:11.66/valo/02,572.99,yes,locked 2006.197.07:43:11.66/valo/03,672.99,yes,locked 2006.197.07:43:11.66/valo/04,832.99,yes,locked 2006.197.07:43:11.66/valo/05,652.99,yes,locked 2006.197.07:43:11.66/valo/06,772.99,yes,locked 2006.197.07:43:11.66/valo/07,832.99,yes,locked 2006.197.07:43:11.66/valo/08,852.99,yes,locked 2006.197.07:43:12.75/vb/01,04,usb,yes,30,28 2006.197.07:43:12.75/vb/02,04,usb,yes,31,33 2006.197.07:43:12.75/vb/03,04,usb,yes,28,31 2006.197.07:43:12.75/vb/04,04,usb,yes,29,29 2006.197.07:43:12.75/vb/05,04,usb,yes,27,31 2006.197.07:43:12.75/vb/06,04,usb,yes,28,31 2006.197.07:43:12.75/vb/07,04,usb,yes,30,30 2006.197.07:43:12.75/vb/08,04,usb,yes,28,31 2006.197.07:43:12.99/vblo/01,632.99,yes,locked 2006.197.07:43:12.99/vblo/02,640.99,yes,locked 2006.197.07:43:12.99/vblo/03,656.99,yes,locked 2006.197.07:43:12.99/vblo/04,712.99,yes,locked 2006.197.07:43:12.99/vblo/05,744.99,yes,locked 2006.197.07:43:12.99/vblo/06,752.99,yes,locked 2006.197.07:43:12.99/vblo/07,734.99,yes,locked 2006.197.07:43:12.99/vblo/08,744.99,yes,locked 2006.197.07:43:13.14/vabw/8 2006.197.07:43:13.29/vbbw/8 2006.197.07:43:13.38/xfe/off,on,14.7 2006.197.07:43:13.75/ifatt/23,28,28,28 2006.197.07:43:14.10/fmout-gps/S +2.98E-07 2006.197.07:43:14.13:!2006.197.07:46:00 2006.197.07:46:00.00:data_valid=off 2006.197.07:46:00.00:postob 2006.197.07:46:00.14/cable/+6.3713E-03 2006.197.07:46:00.14/wx/25.81,1003.1,97 2006.197.07:46:01.10/fmout-gps/S +2.98E-07 2006.197.07:46:01.10:scan_name=197-0747,k06197,60 2006.197.07:46:01.10:source=1739+522,174036.98,521143.4,2000.0,cw 2006.197.07:46:02.14#flagr#flagr/antenna,new-source 2006.197.07:46:02.14:checkk5 2006.197.07:46:02.48/chk_autoobs//k5ts1/ autoobs is running! 2006.197.07:46:02.84/chk_autoobs//k5ts2/ autoobs is running! 2006.197.07:46:03.18/chk_autoobs//k5ts3/ autoobs is running! 2006.197.07:46:03.52/chk_autoobs//k5ts4/ autoobs is running! 2006.197.07:46:03.87/chk_obsdata//k5ts1/T1970743??a.dat file size is correct (nominal:1360MB, actual:1352MB). 2006.197.07:46:04.20/chk_obsdata//k5ts2/T1970743??b.dat file size is correct (nominal:1360MB, actual:1352MB). 2006.197.07:46:04.54/chk_obsdata//k5ts3/T1970743??c.dat file size is correct (nominal:1360MB, actual:1352MB). 2006.197.07:46:04.88/chk_obsdata//k5ts4/T1970743??d.dat file size is correct (nominal:1360MB, actual:1352MB). 2006.197.07:46:05.54/k5log//k5ts1_log_newline 2006.197.07:46:06.21/k5log//k5ts2_log_newline 2006.197.07:46:06.87/k5log//k5ts3_log_newline 2006.197.07:46:07.53/k5log//k5ts4_log_newline 2006.197.07:46:07.55/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.197.07:46:07.55:4f8m12a=1 2006.197.07:46:07.55$4f8m12a/echo=on 2006.197.07:46:07.55$4f8m12a/pcalon 2006.197.07:46:07.55$pcalon/"no phase cal control is implemented here 2006.197.07:46:07.55$4f8m12a/"tpicd=stop 2006.197.07:46:07.55$4f8m12a/vc4f8 2006.197.07:46:07.55$vc4f8/valo=1,532.99 2006.197.07:46:07.56#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.197.07:46:07.56#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.197.07:46:07.56#ibcon#ireg 17 cls_cnt 0 2006.197.07:46:07.56#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.197.07:46:07.56#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.197.07:46:07.56#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.197.07:46:07.56#ibcon#enter wrdev, iclass 5, count 0 2006.197.07:46:07.56#ibcon#first serial, iclass 5, count 0 2006.197.07:46:07.56#ibcon#enter sib2, iclass 5, count 0 2006.197.07:46:07.56#ibcon#flushed, iclass 5, count 0 2006.197.07:46:07.56#ibcon#about to write, iclass 5, count 0 2006.197.07:46:07.56#ibcon#wrote, iclass 5, count 0 2006.197.07:46:07.56#ibcon#about to read 3, iclass 5, count 0 2006.197.07:46:07.58#ibcon#read 3, iclass 5, count 0 2006.197.07:46:07.58#ibcon#about to read 4, iclass 5, count 0 2006.197.07:46:07.58#ibcon#read 4, iclass 5, count 0 2006.197.07:46:07.58#ibcon#about to read 5, iclass 5, count 0 2006.197.07:46:07.58#ibcon#read 5, iclass 5, count 0 2006.197.07:46:07.58#ibcon#about to read 6, iclass 5, count 0 2006.197.07:46:07.58#ibcon#read 6, iclass 5, count 0 2006.197.07:46:07.58#ibcon#end of sib2, iclass 5, count 0 2006.197.07:46:07.58#ibcon#*mode == 0, iclass 5, count 0 2006.197.07:46:07.58#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.197.07:46:07.58#ibcon#[26=FRQ=01,532.99\r\n] 2006.197.07:46:07.58#ibcon#*before write, iclass 5, count 0 2006.197.07:46:07.58#ibcon#enter sib2, iclass 5, count 0 2006.197.07:46:07.58#ibcon#flushed, iclass 5, count 0 2006.197.07:46:07.58#ibcon#about to write, iclass 5, count 0 2006.197.07:46:07.58#ibcon#wrote, iclass 5, count 0 2006.197.07:46:07.58#ibcon#about to read 3, iclass 5, count 0 2006.197.07:46:07.63#ibcon#read 3, iclass 5, count 0 2006.197.07:46:07.63#ibcon#about to read 4, iclass 5, count 0 2006.197.07:46:07.63#ibcon#read 4, iclass 5, count 0 2006.197.07:46:07.63#ibcon#about to read 5, iclass 5, count 0 2006.197.07:46:07.63#ibcon#read 5, iclass 5, count 0 2006.197.07:46:07.63#ibcon#about to read 6, iclass 5, count 0 2006.197.07:46:07.63#ibcon#read 6, iclass 5, count 0 2006.197.07:46:07.63#ibcon#end of sib2, iclass 5, count 0 2006.197.07:46:07.63#ibcon#*after write, iclass 5, count 0 2006.197.07:46:07.63#ibcon#*before return 0, iclass 5, count 0 2006.197.07:46:07.63#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.197.07:46:07.63#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.197.07:46:07.63#ibcon#about to clear, iclass 5 cls_cnt 0 2006.197.07:46:07.63#ibcon#cleared, iclass 5 cls_cnt 0 2006.197.07:46:07.63$vc4f8/va=1,8 2006.197.07:46:07.63#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.197.07:46:07.63#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.197.07:46:07.63#ibcon#ireg 11 cls_cnt 2 2006.197.07:46:07.63#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.197.07:46:07.63#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.197.07:46:07.63#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.197.07:46:07.63#ibcon#enter wrdev, iclass 7, count 2 2006.197.07:46:07.63#ibcon#first serial, iclass 7, count 2 2006.197.07:46:07.63#ibcon#enter sib2, iclass 7, count 2 2006.197.07:46:07.63#ibcon#flushed, iclass 7, count 2 2006.197.07:46:07.63#ibcon#about to write, iclass 7, count 2 2006.197.07:46:07.63#ibcon#wrote, iclass 7, count 2 2006.197.07:46:07.63#ibcon#about to read 3, iclass 7, count 2 2006.197.07:46:07.65#ibcon#read 3, iclass 7, count 2 2006.197.07:46:07.65#ibcon#about to read 4, iclass 7, count 2 2006.197.07:46:07.65#ibcon#read 4, iclass 7, count 2 2006.197.07:46:07.65#ibcon#about to read 5, iclass 7, count 2 2006.197.07:46:07.65#ibcon#read 5, iclass 7, count 2 2006.197.07:46:07.65#ibcon#about to read 6, iclass 7, count 2 2006.197.07:46:07.65#ibcon#read 6, iclass 7, count 2 2006.197.07:46:07.65#ibcon#end of sib2, iclass 7, count 2 2006.197.07:46:07.65#ibcon#*mode == 0, iclass 7, count 2 2006.197.07:46:07.65#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.197.07:46:07.65#ibcon#[25=AT01-08\r\n] 2006.197.07:46:07.65#ibcon#*before write, iclass 7, count 2 2006.197.07:46:07.65#ibcon#enter sib2, iclass 7, count 2 2006.197.07:46:07.65#ibcon#flushed, iclass 7, count 2 2006.197.07:46:07.65#ibcon#about to write, iclass 7, count 2 2006.197.07:46:07.65#ibcon#wrote, iclass 7, count 2 2006.197.07:46:07.65#ibcon#about to read 3, iclass 7, count 2 2006.197.07:46:07.68#ibcon#read 3, iclass 7, count 2 2006.197.07:46:07.68#ibcon#about to read 4, iclass 7, count 2 2006.197.07:46:07.68#ibcon#read 4, iclass 7, count 2 2006.197.07:46:07.68#ibcon#about to read 5, iclass 7, count 2 2006.197.07:46:07.68#ibcon#read 5, iclass 7, count 2 2006.197.07:46:07.68#ibcon#about to read 6, iclass 7, count 2 2006.197.07:46:07.68#ibcon#read 6, iclass 7, count 2 2006.197.07:46:07.68#ibcon#end of sib2, iclass 7, count 2 2006.197.07:46:07.68#ibcon#*after write, iclass 7, count 2 2006.197.07:46:07.68#ibcon#*before return 0, iclass 7, count 2 2006.197.07:46:07.68#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.197.07:46:07.68#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.197.07:46:07.68#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.197.07:46:07.68#ibcon#ireg 7 cls_cnt 0 2006.197.07:46:07.68#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.197.07:46:07.80#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.197.07:46:07.80#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.197.07:46:07.80#ibcon#enter wrdev, iclass 7, count 0 2006.197.07:46:07.80#ibcon#first serial, iclass 7, count 0 2006.197.07:46:07.80#ibcon#enter sib2, iclass 7, count 0 2006.197.07:46:07.80#ibcon#flushed, iclass 7, count 0 2006.197.07:46:07.80#ibcon#about to write, iclass 7, count 0 2006.197.07:46:07.80#ibcon#wrote, iclass 7, count 0 2006.197.07:46:07.80#ibcon#about to read 3, iclass 7, count 0 2006.197.07:46:07.82#ibcon#read 3, iclass 7, count 0 2006.197.07:46:07.82#ibcon#about to read 4, iclass 7, count 0 2006.197.07:46:07.82#ibcon#read 4, iclass 7, count 0 2006.197.07:46:07.82#ibcon#about to read 5, iclass 7, count 0 2006.197.07:46:07.82#ibcon#read 5, iclass 7, count 0 2006.197.07:46:07.82#ibcon#about to read 6, iclass 7, count 0 2006.197.07:46:07.82#ibcon#read 6, iclass 7, count 0 2006.197.07:46:07.82#ibcon#end of sib2, iclass 7, count 0 2006.197.07:46:07.82#ibcon#*mode == 0, iclass 7, count 0 2006.197.07:46:07.82#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.197.07:46:07.82#ibcon#[25=USB\r\n] 2006.197.07:46:07.82#ibcon#*before write, iclass 7, count 0 2006.197.07:46:07.82#ibcon#enter sib2, iclass 7, count 0 2006.197.07:46:07.82#ibcon#flushed, iclass 7, count 0 2006.197.07:46:07.82#ibcon#about to write, iclass 7, count 0 2006.197.07:46:07.82#ibcon#wrote, iclass 7, count 0 2006.197.07:46:07.82#ibcon#about to read 3, iclass 7, count 0 2006.197.07:46:07.85#ibcon#read 3, iclass 7, count 0 2006.197.07:46:07.85#ibcon#about to read 4, iclass 7, count 0 2006.197.07:46:07.85#ibcon#read 4, iclass 7, count 0 2006.197.07:46:07.85#ibcon#about to read 5, iclass 7, count 0 2006.197.07:46:07.85#ibcon#read 5, iclass 7, count 0 2006.197.07:46:07.85#ibcon#about to read 6, iclass 7, count 0 2006.197.07:46:07.85#ibcon#read 6, iclass 7, count 0 2006.197.07:46:07.85#ibcon#end of sib2, iclass 7, count 0 2006.197.07:46:07.85#ibcon#*after write, iclass 7, count 0 2006.197.07:46:07.85#ibcon#*before return 0, iclass 7, count 0 2006.197.07:46:07.85#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.197.07:46:07.85#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.197.07:46:07.85#ibcon#about to clear, iclass 7 cls_cnt 0 2006.197.07:46:07.85#ibcon#cleared, iclass 7 cls_cnt 0 2006.197.07:46:07.85$vc4f8/valo=2,572.99 2006.197.07:46:07.85#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.197.07:46:07.85#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.197.07:46:07.85#ibcon#ireg 17 cls_cnt 0 2006.197.07:46:07.85#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.197.07:46:07.85#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.197.07:46:07.85#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.197.07:46:07.85#ibcon#enter wrdev, iclass 11, count 0 2006.197.07:46:07.85#ibcon#first serial, iclass 11, count 0 2006.197.07:46:07.85#ibcon#enter sib2, iclass 11, count 0 2006.197.07:46:07.85#ibcon#flushed, iclass 11, count 0 2006.197.07:46:07.85#ibcon#about to write, iclass 11, count 0 2006.197.07:46:07.85#ibcon#wrote, iclass 11, count 0 2006.197.07:46:07.85#ibcon#about to read 3, iclass 11, count 0 2006.197.07:46:07.87#ibcon#read 3, iclass 11, count 0 2006.197.07:46:07.87#ibcon#about to read 4, iclass 11, count 0 2006.197.07:46:07.87#ibcon#read 4, iclass 11, count 0 2006.197.07:46:07.87#ibcon#about to read 5, iclass 11, count 0 2006.197.07:46:07.87#ibcon#read 5, iclass 11, count 0 2006.197.07:46:07.87#ibcon#about to read 6, iclass 11, count 0 2006.197.07:46:07.87#ibcon#read 6, iclass 11, count 0 2006.197.07:46:07.87#ibcon#end of sib2, iclass 11, count 0 2006.197.07:46:07.87#ibcon#*mode == 0, iclass 11, count 0 2006.197.07:46:07.87#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.197.07:46:07.87#ibcon#[26=FRQ=02,572.99\r\n] 2006.197.07:46:07.87#ibcon#*before write, iclass 11, count 0 2006.197.07:46:07.87#ibcon#enter sib2, iclass 11, count 0 2006.197.07:46:07.87#ibcon#flushed, iclass 11, count 0 2006.197.07:46:07.87#ibcon#about to write, iclass 11, count 0 2006.197.07:46:07.87#ibcon#wrote, iclass 11, count 0 2006.197.07:46:07.87#ibcon#about to read 3, iclass 11, count 0 2006.197.07:46:07.91#ibcon#read 3, iclass 11, count 0 2006.197.07:46:07.91#ibcon#about to read 4, iclass 11, count 0 2006.197.07:46:07.91#ibcon#read 4, iclass 11, count 0 2006.197.07:46:07.91#ibcon#about to read 5, iclass 11, count 0 2006.197.07:46:07.91#ibcon#read 5, iclass 11, count 0 2006.197.07:46:07.91#ibcon#about to read 6, iclass 11, count 0 2006.197.07:46:07.91#ibcon#read 6, iclass 11, count 0 2006.197.07:46:07.91#ibcon#end of sib2, iclass 11, count 0 2006.197.07:46:07.91#ibcon#*after write, iclass 11, count 0 2006.197.07:46:07.91#ibcon#*before return 0, iclass 11, count 0 2006.197.07:46:07.91#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.197.07:46:07.91#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.197.07:46:07.91#ibcon#about to clear, iclass 11 cls_cnt 0 2006.197.07:46:07.91#ibcon#cleared, iclass 11 cls_cnt 0 2006.197.07:46:07.91$vc4f8/va=2,7 2006.197.07:46:07.91#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.197.07:46:07.91#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.197.07:46:07.91#ibcon#ireg 11 cls_cnt 2 2006.197.07:46:07.91#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.197.07:46:07.97#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.197.07:46:07.97#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.197.07:46:07.97#ibcon#enter wrdev, iclass 13, count 2 2006.197.07:46:07.97#ibcon#first serial, iclass 13, count 2 2006.197.07:46:07.97#ibcon#enter sib2, iclass 13, count 2 2006.197.07:46:07.97#ibcon#flushed, iclass 13, count 2 2006.197.07:46:07.97#ibcon#about to write, iclass 13, count 2 2006.197.07:46:07.97#ibcon#wrote, iclass 13, count 2 2006.197.07:46:07.97#ibcon#about to read 3, iclass 13, count 2 2006.197.07:46:07.99#ibcon#read 3, iclass 13, count 2 2006.197.07:46:07.99#ibcon#about to read 4, iclass 13, count 2 2006.197.07:46:07.99#ibcon#read 4, iclass 13, count 2 2006.197.07:46:07.99#ibcon#about to read 5, iclass 13, count 2 2006.197.07:46:07.99#ibcon#read 5, iclass 13, count 2 2006.197.07:46:07.99#ibcon#about to read 6, iclass 13, count 2 2006.197.07:46:07.99#ibcon#read 6, iclass 13, count 2 2006.197.07:46:07.99#ibcon#end of sib2, iclass 13, count 2 2006.197.07:46:07.99#ibcon#*mode == 0, iclass 13, count 2 2006.197.07:46:07.99#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.197.07:46:07.99#ibcon#[25=AT02-07\r\n] 2006.197.07:46:07.99#ibcon#*before write, iclass 13, count 2 2006.197.07:46:07.99#ibcon#enter sib2, iclass 13, count 2 2006.197.07:46:07.99#ibcon#flushed, iclass 13, count 2 2006.197.07:46:07.99#ibcon#about to write, iclass 13, count 2 2006.197.07:46:07.99#ibcon#wrote, iclass 13, count 2 2006.197.07:46:07.99#ibcon#about to read 3, iclass 13, count 2 2006.197.07:46:08.02#ibcon#read 3, iclass 13, count 2 2006.197.07:46:08.02#ibcon#about to read 4, iclass 13, count 2 2006.197.07:46:08.02#ibcon#read 4, iclass 13, count 2 2006.197.07:46:08.02#ibcon#about to read 5, iclass 13, count 2 2006.197.07:46:08.02#ibcon#read 5, iclass 13, count 2 2006.197.07:46:08.02#ibcon#about to read 6, iclass 13, count 2 2006.197.07:46:08.02#ibcon#read 6, iclass 13, count 2 2006.197.07:46:08.02#ibcon#end of sib2, iclass 13, count 2 2006.197.07:46:08.02#ibcon#*after write, iclass 13, count 2 2006.197.07:46:08.02#ibcon#*before return 0, iclass 13, count 2 2006.197.07:46:08.02#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.197.07:46:08.02#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.197.07:46:08.02#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.197.07:46:08.02#ibcon#ireg 7 cls_cnt 0 2006.197.07:46:08.02#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.197.07:46:08.14#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.197.07:46:08.14#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.197.07:46:08.14#ibcon#enter wrdev, iclass 13, count 0 2006.197.07:46:08.14#ibcon#first serial, iclass 13, count 0 2006.197.07:46:08.14#ibcon#enter sib2, iclass 13, count 0 2006.197.07:46:08.14#ibcon#flushed, iclass 13, count 0 2006.197.07:46:08.14#ibcon#about to write, iclass 13, count 0 2006.197.07:46:08.14#ibcon#wrote, iclass 13, count 0 2006.197.07:46:08.14#ibcon#about to read 3, iclass 13, count 0 2006.197.07:46:08.16#ibcon#read 3, iclass 13, count 0 2006.197.07:46:08.16#ibcon#about to read 4, iclass 13, count 0 2006.197.07:46:08.16#ibcon#read 4, iclass 13, count 0 2006.197.07:46:08.16#ibcon#about to read 5, iclass 13, count 0 2006.197.07:46:08.16#ibcon#read 5, iclass 13, count 0 2006.197.07:46:08.16#ibcon#about to read 6, iclass 13, count 0 2006.197.07:46:08.16#ibcon#read 6, iclass 13, count 0 2006.197.07:46:08.16#ibcon#end of sib2, iclass 13, count 0 2006.197.07:46:08.16#ibcon#*mode == 0, iclass 13, count 0 2006.197.07:46:08.16#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.197.07:46:08.16#ibcon#[25=USB\r\n] 2006.197.07:46:08.16#ibcon#*before write, iclass 13, count 0 2006.197.07:46:08.16#ibcon#enter sib2, iclass 13, count 0 2006.197.07:46:08.16#ibcon#flushed, iclass 13, count 0 2006.197.07:46:08.16#ibcon#about to write, iclass 13, count 0 2006.197.07:46:08.16#ibcon#wrote, iclass 13, count 0 2006.197.07:46:08.16#ibcon#about to read 3, iclass 13, count 0 2006.197.07:46:08.19#ibcon#read 3, iclass 13, count 0 2006.197.07:46:08.19#ibcon#about to read 4, iclass 13, count 0 2006.197.07:46:08.19#ibcon#read 4, iclass 13, count 0 2006.197.07:46:08.19#ibcon#about to read 5, iclass 13, count 0 2006.197.07:46:08.19#ibcon#read 5, iclass 13, count 0 2006.197.07:46:08.19#ibcon#about to read 6, iclass 13, count 0 2006.197.07:46:08.19#ibcon#read 6, iclass 13, count 0 2006.197.07:46:08.19#ibcon#end of sib2, iclass 13, count 0 2006.197.07:46:08.19#ibcon#*after write, iclass 13, count 0 2006.197.07:46:08.19#ibcon#*before return 0, iclass 13, count 0 2006.197.07:46:08.19#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.197.07:46:08.19#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.197.07:46:08.19#ibcon#about to clear, iclass 13 cls_cnt 0 2006.197.07:46:08.19#ibcon#cleared, iclass 13 cls_cnt 0 2006.197.07:46:08.19$vc4f8/valo=3,672.99 2006.197.07:46:08.19#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.197.07:46:08.19#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.197.07:46:08.19#ibcon#ireg 17 cls_cnt 0 2006.197.07:46:08.19#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.197.07:46:08.19#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.197.07:46:08.19#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.197.07:46:08.19#ibcon#enter wrdev, iclass 15, count 0 2006.197.07:46:08.19#ibcon#first serial, iclass 15, count 0 2006.197.07:46:08.19#ibcon#enter sib2, iclass 15, count 0 2006.197.07:46:08.19#ibcon#flushed, iclass 15, count 0 2006.197.07:46:08.19#ibcon#about to write, iclass 15, count 0 2006.197.07:46:08.19#ibcon#wrote, iclass 15, count 0 2006.197.07:46:08.19#ibcon#about to read 3, iclass 15, count 0 2006.197.07:46:08.21#ibcon#read 3, iclass 15, count 0 2006.197.07:46:08.21#ibcon#about to read 4, iclass 15, count 0 2006.197.07:46:08.21#ibcon#read 4, iclass 15, count 0 2006.197.07:46:08.21#ibcon#about to read 5, iclass 15, count 0 2006.197.07:46:08.21#ibcon#read 5, iclass 15, count 0 2006.197.07:46:08.21#ibcon#about to read 6, iclass 15, count 0 2006.197.07:46:08.21#ibcon#read 6, iclass 15, count 0 2006.197.07:46:08.21#ibcon#end of sib2, iclass 15, count 0 2006.197.07:46:08.21#ibcon#*mode == 0, iclass 15, count 0 2006.197.07:46:08.21#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.197.07:46:08.21#ibcon#[26=FRQ=03,672.99\r\n] 2006.197.07:46:08.21#ibcon#*before write, iclass 15, count 0 2006.197.07:46:08.21#ibcon#enter sib2, iclass 15, count 0 2006.197.07:46:08.21#ibcon#flushed, iclass 15, count 0 2006.197.07:46:08.21#ibcon#about to write, iclass 15, count 0 2006.197.07:46:08.21#ibcon#wrote, iclass 15, count 0 2006.197.07:46:08.21#ibcon#about to read 3, iclass 15, count 0 2006.197.07:46:08.25#ibcon#read 3, iclass 15, count 0 2006.197.07:46:08.25#ibcon#about to read 4, iclass 15, count 0 2006.197.07:46:08.25#ibcon#read 4, iclass 15, count 0 2006.197.07:46:08.25#ibcon#about to read 5, iclass 15, count 0 2006.197.07:46:08.25#ibcon#read 5, iclass 15, count 0 2006.197.07:46:08.25#ibcon#about to read 6, iclass 15, count 0 2006.197.07:46:08.25#ibcon#read 6, iclass 15, count 0 2006.197.07:46:08.25#ibcon#end of sib2, iclass 15, count 0 2006.197.07:46:08.25#ibcon#*after write, iclass 15, count 0 2006.197.07:46:08.25#ibcon#*before return 0, iclass 15, count 0 2006.197.07:46:08.25#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.197.07:46:08.25#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.197.07:46:08.25#ibcon#about to clear, iclass 15 cls_cnt 0 2006.197.07:46:08.25#ibcon#cleared, iclass 15 cls_cnt 0 2006.197.07:46:08.25$vc4f8/va=3,6 2006.197.07:46:08.25#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.197.07:46:08.25#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.197.07:46:08.25#ibcon#ireg 11 cls_cnt 2 2006.197.07:46:08.25#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.197.07:46:08.31#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.197.07:46:08.31#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.197.07:46:08.31#ibcon#enter wrdev, iclass 17, count 2 2006.197.07:46:08.31#ibcon#first serial, iclass 17, count 2 2006.197.07:46:08.31#ibcon#enter sib2, iclass 17, count 2 2006.197.07:46:08.31#ibcon#flushed, iclass 17, count 2 2006.197.07:46:08.31#ibcon#about to write, iclass 17, count 2 2006.197.07:46:08.31#ibcon#wrote, iclass 17, count 2 2006.197.07:46:08.31#ibcon#about to read 3, iclass 17, count 2 2006.197.07:46:08.33#ibcon#read 3, iclass 17, count 2 2006.197.07:46:08.33#ibcon#about to read 4, iclass 17, count 2 2006.197.07:46:08.33#ibcon#read 4, iclass 17, count 2 2006.197.07:46:08.33#ibcon#about to read 5, iclass 17, count 2 2006.197.07:46:08.33#ibcon#read 5, iclass 17, count 2 2006.197.07:46:08.33#ibcon#about to read 6, iclass 17, count 2 2006.197.07:46:08.33#ibcon#read 6, iclass 17, count 2 2006.197.07:46:08.33#ibcon#end of sib2, iclass 17, count 2 2006.197.07:46:08.33#ibcon#*mode == 0, iclass 17, count 2 2006.197.07:46:08.33#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.197.07:46:08.33#ibcon#[25=AT03-06\r\n] 2006.197.07:46:08.33#ibcon#*before write, iclass 17, count 2 2006.197.07:46:08.33#ibcon#enter sib2, iclass 17, count 2 2006.197.07:46:08.33#ibcon#flushed, iclass 17, count 2 2006.197.07:46:08.33#ibcon#about to write, iclass 17, count 2 2006.197.07:46:08.33#ibcon#wrote, iclass 17, count 2 2006.197.07:46:08.33#ibcon#about to read 3, iclass 17, count 2 2006.197.07:46:08.36#ibcon#read 3, iclass 17, count 2 2006.197.07:46:08.36#ibcon#about to read 4, iclass 17, count 2 2006.197.07:46:08.36#ibcon#read 4, iclass 17, count 2 2006.197.07:46:08.36#ibcon#about to read 5, iclass 17, count 2 2006.197.07:46:08.36#ibcon#read 5, iclass 17, count 2 2006.197.07:46:08.36#ibcon#about to read 6, iclass 17, count 2 2006.197.07:46:08.36#ibcon#read 6, iclass 17, count 2 2006.197.07:46:08.36#ibcon#end of sib2, iclass 17, count 2 2006.197.07:46:08.36#ibcon#*after write, iclass 17, count 2 2006.197.07:46:08.36#ibcon#*before return 0, iclass 17, count 2 2006.197.07:46:08.36#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.197.07:46:08.36#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.197.07:46:08.36#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.197.07:46:08.36#ibcon#ireg 7 cls_cnt 0 2006.197.07:46:08.36#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.197.07:46:08.48#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.197.07:46:08.48#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.197.07:46:08.48#ibcon#enter wrdev, iclass 17, count 0 2006.197.07:46:08.48#ibcon#first serial, iclass 17, count 0 2006.197.07:46:08.48#ibcon#enter sib2, iclass 17, count 0 2006.197.07:46:08.48#ibcon#flushed, iclass 17, count 0 2006.197.07:46:08.48#ibcon#about to write, iclass 17, count 0 2006.197.07:46:08.48#ibcon#wrote, iclass 17, count 0 2006.197.07:46:08.48#ibcon#about to read 3, iclass 17, count 0 2006.197.07:46:08.50#ibcon#read 3, iclass 17, count 0 2006.197.07:46:08.50#ibcon#about to read 4, iclass 17, count 0 2006.197.07:46:08.50#ibcon#read 4, iclass 17, count 0 2006.197.07:46:08.50#ibcon#about to read 5, iclass 17, count 0 2006.197.07:46:08.50#ibcon#read 5, iclass 17, count 0 2006.197.07:46:08.50#ibcon#about to read 6, iclass 17, count 0 2006.197.07:46:08.50#ibcon#read 6, iclass 17, count 0 2006.197.07:46:08.50#ibcon#end of sib2, iclass 17, count 0 2006.197.07:46:08.50#ibcon#*mode == 0, iclass 17, count 0 2006.197.07:46:08.50#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.197.07:46:08.50#ibcon#[25=USB\r\n] 2006.197.07:46:08.50#ibcon#*before write, iclass 17, count 0 2006.197.07:46:08.50#ibcon#enter sib2, iclass 17, count 0 2006.197.07:46:08.50#ibcon#flushed, iclass 17, count 0 2006.197.07:46:08.50#ibcon#about to write, iclass 17, count 0 2006.197.07:46:08.50#ibcon#wrote, iclass 17, count 0 2006.197.07:46:08.50#ibcon#about to read 3, iclass 17, count 0 2006.197.07:46:08.53#ibcon#read 3, iclass 17, count 0 2006.197.07:46:08.53#ibcon#about to read 4, iclass 17, count 0 2006.197.07:46:08.53#ibcon#read 4, iclass 17, count 0 2006.197.07:46:08.53#ibcon#about to read 5, iclass 17, count 0 2006.197.07:46:08.53#ibcon#read 5, iclass 17, count 0 2006.197.07:46:08.53#ibcon#about to read 6, iclass 17, count 0 2006.197.07:46:08.53#ibcon#read 6, iclass 17, count 0 2006.197.07:46:08.53#ibcon#end of sib2, iclass 17, count 0 2006.197.07:46:08.53#ibcon#*after write, iclass 17, count 0 2006.197.07:46:08.53#ibcon#*before return 0, iclass 17, count 0 2006.197.07:46:08.53#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.197.07:46:08.53#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.197.07:46:08.53#ibcon#about to clear, iclass 17 cls_cnt 0 2006.197.07:46:08.53#ibcon#cleared, iclass 17 cls_cnt 0 2006.197.07:46:08.53$vc4f8/valo=4,832.99 2006.197.07:46:08.53#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.197.07:46:08.53#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.197.07:46:08.53#ibcon#ireg 17 cls_cnt 0 2006.197.07:46:08.53#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.197.07:46:08.53#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.197.07:46:08.53#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.197.07:46:08.53#ibcon#enter wrdev, iclass 19, count 0 2006.197.07:46:08.53#ibcon#first serial, iclass 19, count 0 2006.197.07:46:08.53#ibcon#enter sib2, iclass 19, count 0 2006.197.07:46:08.53#ibcon#flushed, iclass 19, count 0 2006.197.07:46:08.53#ibcon#about to write, iclass 19, count 0 2006.197.07:46:08.53#ibcon#wrote, iclass 19, count 0 2006.197.07:46:08.53#ibcon#about to read 3, iclass 19, count 0 2006.197.07:46:08.55#ibcon#read 3, iclass 19, count 0 2006.197.07:46:08.55#ibcon#about to read 4, iclass 19, count 0 2006.197.07:46:08.55#ibcon#read 4, iclass 19, count 0 2006.197.07:46:08.55#ibcon#about to read 5, iclass 19, count 0 2006.197.07:46:08.55#ibcon#read 5, iclass 19, count 0 2006.197.07:46:08.55#ibcon#about to read 6, iclass 19, count 0 2006.197.07:46:08.55#ibcon#read 6, iclass 19, count 0 2006.197.07:46:08.55#ibcon#end of sib2, iclass 19, count 0 2006.197.07:46:08.55#ibcon#*mode == 0, iclass 19, count 0 2006.197.07:46:08.55#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.197.07:46:08.55#ibcon#[26=FRQ=04,832.99\r\n] 2006.197.07:46:08.55#ibcon#*before write, iclass 19, count 0 2006.197.07:46:08.55#ibcon#enter sib2, iclass 19, count 0 2006.197.07:46:08.55#ibcon#flushed, iclass 19, count 0 2006.197.07:46:08.55#ibcon#about to write, iclass 19, count 0 2006.197.07:46:08.55#ibcon#wrote, iclass 19, count 0 2006.197.07:46:08.55#ibcon#about to read 3, iclass 19, count 0 2006.197.07:46:08.59#ibcon#read 3, iclass 19, count 0 2006.197.07:46:08.59#ibcon#about to read 4, iclass 19, count 0 2006.197.07:46:08.59#ibcon#read 4, iclass 19, count 0 2006.197.07:46:08.59#ibcon#about to read 5, iclass 19, count 0 2006.197.07:46:08.59#ibcon#read 5, iclass 19, count 0 2006.197.07:46:08.59#ibcon#about to read 6, iclass 19, count 0 2006.197.07:46:08.59#ibcon#read 6, iclass 19, count 0 2006.197.07:46:08.59#ibcon#end of sib2, iclass 19, count 0 2006.197.07:46:08.59#ibcon#*after write, iclass 19, count 0 2006.197.07:46:08.59#ibcon#*before return 0, iclass 19, count 0 2006.197.07:46:08.59#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.197.07:46:08.59#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.197.07:46:08.59#ibcon#about to clear, iclass 19 cls_cnt 0 2006.197.07:46:08.59#ibcon#cleared, iclass 19 cls_cnt 0 2006.197.07:46:08.59$vc4f8/va=4,7 2006.197.07:46:08.59#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.197.07:46:08.59#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.197.07:46:08.59#ibcon#ireg 11 cls_cnt 2 2006.197.07:46:08.59#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.197.07:46:08.65#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.197.07:46:08.65#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.197.07:46:08.65#ibcon#enter wrdev, iclass 21, count 2 2006.197.07:46:08.65#ibcon#first serial, iclass 21, count 2 2006.197.07:46:08.65#ibcon#enter sib2, iclass 21, count 2 2006.197.07:46:08.65#ibcon#flushed, iclass 21, count 2 2006.197.07:46:08.65#ibcon#about to write, iclass 21, count 2 2006.197.07:46:08.65#ibcon#wrote, iclass 21, count 2 2006.197.07:46:08.65#ibcon#about to read 3, iclass 21, count 2 2006.197.07:46:08.67#ibcon#read 3, iclass 21, count 2 2006.197.07:46:08.67#ibcon#about to read 4, iclass 21, count 2 2006.197.07:46:08.67#ibcon#read 4, iclass 21, count 2 2006.197.07:46:08.67#ibcon#about to read 5, iclass 21, count 2 2006.197.07:46:08.67#ibcon#read 5, iclass 21, count 2 2006.197.07:46:08.67#ibcon#about to read 6, iclass 21, count 2 2006.197.07:46:08.67#ibcon#read 6, iclass 21, count 2 2006.197.07:46:08.67#ibcon#end of sib2, iclass 21, count 2 2006.197.07:46:08.67#ibcon#*mode == 0, iclass 21, count 2 2006.197.07:46:08.67#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.197.07:46:08.67#ibcon#[25=AT04-07\r\n] 2006.197.07:46:08.67#ibcon#*before write, iclass 21, count 2 2006.197.07:46:08.67#ibcon#enter sib2, iclass 21, count 2 2006.197.07:46:08.67#ibcon#flushed, iclass 21, count 2 2006.197.07:46:08.67#ibcon#about to write, iclass 21, count 2 2006.197.07:46:08.67#ibcon#wrote, iclass 21, count 2 2006.197.07:46:08.67#ibcon#about to read 3, iclass 21, count 2 2006.197.07:46:08.70#ibcon#read 3, iclass 21, count 2 2006.197.07:46:08.70#ibcon#about to read 4, iclass 21, count 2 2006.197.07:46:08.70#ibcon#read 4, iclass 21, count 2 2006.197.07:46:08.70#ibcon#about to read 5, iclass 21, count 2 2006.197.07:46:08.70#ibcon#read 5, iclass 21, count 2 2006.197.07:46:08.70#ibcon#about to read 6, iclass 21, count 2 2006.197.07:46:08.70#ibcon#read 6, iclass 21, count 2 2006.197.07:46:08.70#ibcon#end of sib2, iclass 21, count 2 2006.197.07:46:08.70#ibcon#*after write, iclass 21, count 2 2006.197.07:46:08.70#ibcon#*before return 0, iclass 21, count 2 2006.197.07:46:08.70#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.197.07:46:08.70#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.197.07:46:08.70#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.197.07:46:08.70#ibcon#ireg 7 cls_cnt 0 2006.197.07:46:08.70#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.197.07:46:08.82#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.197.07:46:08.82#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.197.07:46:08.82#ibcon#enter wrdev, iclass 21, count 0 2006.197.07:46:08.82#ibcon#first serial, iclass 21, count 0 2006.197.07:46:08.82#ibcon#enter sib2, iclass 21, count 0 2006.197.07:46:08.82#ibcon#flushed, iclass 21, count 0 2006.197.07:46:08.82#ibcon#about to write, iclass 21, count 0 2006.197.07:46:08.82#ibcon#wrote, iclass 21, count 0 2006.197.07:46:08.82#ibcon#about to read 3, iclass 21, count 0 2006.197.07:46:08.84#ibcon#read 3, iclass 21, count 0 2006.197.07:46:08.84#ibcon#about to read 4, iclass 21, count 0 2006.197.07:46:08.84#ibcon#read 4, iclass 21, count 0 2006.197.07:46:08.84#ibcon#about to read 5, iclass 21, count 0 2006.197.07:46:08.84#ibcon#read 5, iclass 21, count 0 2006.197.07:46:08.84#ibcon#about to read 6, iclass 21, count 0 2006.197.07:46:08.84#ibcon#read 6, iclass 21, count 0 2006.197.07:46:08.84#ibcon#end of sib2, iclass 21, count 0 2006.197.07:46:08.84#ibcon#*mode == 0, iclass 21, count 0 2006.197.07:46:08.84#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.197.07:46:08.84#ibcon#[25=USB\r\n] 2006.197.07:46:08.84#ibcon#*before write, iclass 21, count 0 2006.197.07:46:08.84#ibcon#enter sib2, iclass 21, count 0 2006.197.07:46:08.84#ibcon#flushed, iclass 21, count 0 2006.197.07:46:08.84#ibcon#about to write, iclass 21, count 0 2006.197.07:46:08.84#ibcon#wrote, iclass 21, count 0 2006.197.07:46:08.84#ibcon#about to read 3, iclass 21, count 0 2006.197.07:46:08.87#ibcon#read 3, iclass 21, count 0 2006.197.07:46:08.87#ibcon#about to read 4, iclass 21, count 0 2006.197.07:46:08.87#ibcon#read 4, iclass 21, count 0 2006.197.07:46:08.87#ibcon#about to read 5, iclass 21, count 0 2006.197.07:46:08.87#ibcon#read 5, iclass 21, count 0 2006.197.07:46:08.87#ibcon#about to read 6, iclass 21, count 0 2006.197.07:46:08.87#ibcon#read 6, iclass 21, count 0 2006.197.07:46:08.87#ibcon#end of sib2, iclass 21, count 0 2006.197.07:46:08.87#ibcon#*after write, iclass 21, count 0 2006.197.07:46:08.87#ibcon#*before return 0, iclass 21, count 0 2006.197.07:46:08.87#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.197.07:46:08.87#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.197.07:46:08.87#ibcon#about to clear, iclass 21 cls_cnt 0 2006.197.07:46:08.87#ibcon#cleared, iclass 21 cls_cnt 0 2006.197.07:46:08.87$vc4f8/valo=5,652.99 2006.197.07:46:08.87#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.197.07:46:08.87#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.197.07:46:08.87#ibcon#ireg 17 cls_cnt 0 2006.197.07:46:08.87#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.197.07:46:08.87#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.197.07:46:08.87#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.197.07:46:08.87#ibcon#enter wrdev, iclass 23, count 0 2006.197.07:46:08.87#ibcon#first serial, iclass 23, count 0 2006.197.07:46:08.87#ibcon#enter sib2, iclass 23, count 0 2006.197.07:46:08.87#ibcon#flushed, iclass 23, count 0 2006.197.07:46:08.87#ibcon#about to write, iclass 23, count 0 2006.197.07:46:08.87#ibcon#wrote, iclass 23, count 0 2006.197.07:46:08.87#ibcon#about to read 3, iclass 23, count 0 2006.197.07:46:08.89#ibcon#read 3, iclass 23, count 0 2006.197.07:46:08.89#ibcon#about to read 4, iclass 23, count 0 2006.197.07:46:08.89#ibcon#read 4, iclass 23, count 0 2006.197.07:46:08.89#ibcon#about to read 5, iclass 23, count 0 2006.197.07:46:08.89#ibcon#read 5, iclass 23, count 0 2006.197.07:46:08.89#ibcon#about to read 6, iclass 23, count 0 2006.197.07:46:08.89#ibcon#read 6, iclass 23, count 0 2006.197.07:46:08.89#ibcon#end of sib2, iclass 23, count 0 2006.197.07:46:08.89#ibcon#*mode == 0, iclass 23, count 0 2006.197.07:46:08.89#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.197.07:46:08.89#ibcon#[26=FRQ=05,652.99\r\n] 2006.197.07:46:08.89#ibcon#*before write, iclass 23, count 0 2006.197.07:46:08.89#ibcon#enter sib2, iclass 23, count 0 2006.197.07:46:08.89#ibcon#flushed, iclass 23, count 0 2006.197.07:46:08.89#ibcon#about to write, iclass 23, count 0 2006.197.07:46:08.89#ibcon#wrote, iclass 23, count 0 2006.197.07:46:08.89#ibcon#about to read 3, iclass 23, count 0 2006.197.07:46:08.93#ibcon#read 3, iclass 23, count 0 2006.197.07:46:08.93#ibcon#about to read 4, iclass 23, count 0 2006.197.07:46:08.93#ibcon#read 4, iclass 23, count 0 2006.197.07:46:08.93#ibcon#about to read 5, iclass 23, count 0 2006.197.07:46:08.93#ibcon#read 5, iclass 23, count 0 2006.197.07:46:08.93#ibcon#about to read 6, iclass 23, count 0 2006.197.07:46:08.93#ibcon#read 6, iclass 23, count 0 2006.197.07:46:08.93#ibcon#end of sib2, iclass 23, count 0 2006.197.07:46:08.93#ibcon#*after write, iclass 23, count 0 2006.197.07:46:08.93#ibcon#*before return 0, iclass 23, count 0 2006.197.07:46:08.93#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.197.07:46:08.93#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.197.07:46:08.93#ibcon#about to clear, iclass 23 cls_cnt 0 2006.197.07:46:08.93#ibcon#cleared, iclass 23 cls_cnt 0 2006.197.07:46:08.93$vc4f8/va=5,7 2006.197.07:46:08.93#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.197.07:46:08.93#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.197.07:46:08.93#ibcon#ireg 11 cls_cnt 2 2006.197.07:46:08.93#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.197.07:46:08.99#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.197.07:46:08.99#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.197.07:46:08.99#ibcon#enter wrdev, iclass 25, count 2 2006.197.07:46:08.99#ibcon#first serial, iclass 25, count 2 2006.197.07:46:08.99#ibcon#enter sib2, iclass 25, count 2 2006.197.07:46:08.99#ibcon#flushed, iclass 25, count 2 2006.197.07:46:08.99#ibcon#about to write, iclass 25, count 2 2006.197.07:46:08.99#ibcon#wrote, iclass 25, count 2 2006.197.07:46:08.99#ibcon#about to read 3, iclass 25, count 2 2006.197.07:46:09.01#ibcon#read 3, iclass 25, count 2 2006.197.07:46:09.01#ibcon#about to read 4, iclass 25, count 2 2006.197.07:46:09.01#ibcon#read 4, iclass 25, count 2 2006.197.07:46:09.01#ibcon#about to read 5, iclass 25, count 2 2006.197.07:46:09.01#ibcon#read 5, iclass 25, count 2 2006.197.07:46:09.01#ibcon#about to read 6, iclass 25, count 2 2006.197.07:46:09.01#ibcon#read 6, iclass 25, count 2 2006.197.07:46:09.01#ibcon#end of sib2, iclass 25, count 2 2006.197.07:46:09.01#ibcon#*mode == 0, iclass 25, count 2 2006.197.07:46:09.01#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.197.07:46:09.01#ibcon#[25=AT05-07\r\n] 2006.197.07:46:09.01#ibcon#*before write, iclass 25, count 2 2006.197.07:46:09.01#ibcon#enter sib2, iclass 25, count 2 2006.197.07:46:09.01#ibcon#flushed, iclass 25, count 2 2006.197.07:46:09.01#ibcon#about to write, iclass 25, count 2 2006.197.07:46:09.01#ibcon#wrote, iclass 25, count 2 2006.197.07:46:09.01#ibcon#about to read 3, iclass 25, count 2 2006.197.07:46:09.04#ibcon#read 3, iclass 25, count 2 2006.197.07:46:09.04#ibcon#about to read 4, iclass 25, count 2 2006.197.07:46:09.04#ibcon#read 4, iclass 25, count 2 2006.197.07:46:09.04#ibcon#about to read 5, iclass 25, count 2 2006.197.07:46:09.04#ibcon#read 5, iclass 25, count 2 2006.197.07:46:09.04#ibcon#about to read 6, iclass 25, count 2 2006.197.07:46:09.04#ibcon#read 6, iclass 25, count 2 2006.197.07:46:09.04#ibcon#end of sib2, iclass 25, count 2 2006.197.07:46:09.04#ibcon#*after write, iclass 25, count 2 2006.197.07:46:09.04#ibcon#*before return 0, iclass 25, count 2 2006.197.07:46:09.04#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.197.07:46:09.04#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.197.07:46:09.04#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.197.07:46:09.04#ibcon#ireg 7 cls_cnt 0 2006.197.07:46:09.04#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.197.07:46:09.16#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.197.07:46:09.16#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.197.07:46:09.16#ibcon#enter wrdev, iclass 25, count 0 2006.197.07:46:09.16#ibcon#first serial, iclass 25, count 0 2006.197.07:46:09.16#ibcon#enter sib2, iclass 25, count 0 2006.197.07:46:09.16#ibcon#flushed, iclass 25, count 0 2006.197.07:46:09.16#ibcon#about to write, iclass 25, count 0 2006.197.07:46:09.16#ibcon#wrote, iclass 25, count 0 2006.197.07:46:09.16#ibcon#about to read 3, iclass 25, count 0 2006.197.07:46:09.18#ibcon#read 3, iclass 25, count 0 2006.197.07:46:09.18#ibcon#about to read 4, iclass 25, count 0 2006.197.07:46:09.18#ibcon#read 4, iclass 25, count 0 2006.197.07:46:09.18#ibcon#about to read 5, iclass 25, count 0 2006.197.07:46:09.18#ibcon#read 5, iclass 25, count 0 2006.197.07:46:09.18#ibcon#about to read 6, iclass 25, count 0 2006.197.07:46:09.18#ibcon#read 6, iclass 25, count 0 2006.197.07:46:09.18#ibcon#end of sib2, iclass 25, count 0 2006.197.07:46:09.18#ibcon#*mode == 0, iclass 25, count 0 2006.197.07:46:09.18#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.197.07:46:09.18#ibcon#[25=USB\r\n] 2006.197.07:46:09.18#ibcon#*before write, iclass 25, count 0 2006.197.07:46:09.18#ibcon#enter sib2, iclass 25, count 0 2006.197.07:46:09.18#ibcon#flushed, iclass 25, count 0 2006.197.07:46:09.18#ibcon#about to write, iclass 25, count 0 2006.197.07:46:09.18#ibcon#wrote, iclass 25, count 0 2006.197.07:46:09.18#ibcon#about to read 3, iclass 25, count 0 2006.197.07:46:09.21#ibcon#read 3, iclass 25, count 0 2006.197.07:46:09.21#ibcon#about to read 4, iclass 25, count 0 2006.197.07:46:09.21#ibcon#read 4, iclass 25, count 0 2006.197.07:46:09.21#ibcon#about to read 5, iclass 25, count 0 2006.197.07:46:09.21#ibcon#read 5, iclass 25, count 0 2006.197.07:46:09.21#ibcon#about to read 6, iclass 25, count 0 2006.197.07:46:09.21#ibcon#read 6, iclass 25, count 0 2006.197.07:46:09.21#ibcon#end of sib2, iclass 25, count 0 2006.197.07:46:09.21#ibcon#*after write, iclass 25, count 0 2006.197.07:46:09.21#ibcon#*before return 0, iclass 25, count 0 2006.197.07:46:09.21#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.197.07:46:09.21#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.197.07:46:09.21#ibcon#about to clear, iclass 25 cls_cnt 0 2006.197.07:46:09.21#ibcon#cleared, iclass 25 cls_cnt 0 2006.197.07:46:09.21$vc4f8/valo=6,772.99 2006.197.07:46:09.21#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.197.07:46:09.21#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.197.07:46:09.21#ibcon#ireg 17 cls_cnt 0 2006.197.07:46:09.21#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.197.07:46:09.21#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.197.07:46:09.21#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.197.07:46:09.21#ibcon#enter wrdev, iclass 27, count 0 2006.197.07:46:09.21#ibcon#first serial, iclass 27, count 0 2006.197.07:46:09.21#ibcon#enter sib2, iclass 27, count 0 2006.197.07:46:09.21#ibcon#flushed, iclass 27, count 0 2006.197.07:46:09.21#ibcon#about to write, iclass 27, count 0 2006.197.07:46:09.21#ibcon#wrote, iclass 27, count 0 2006.197.07:46:09.21#ibcon#about to read 3, iclass 27, count 0 2006.197.07:46:09.23#ibcon#read 3, iclass 27, count 0 2006.197.07:46:09.23#ibcon#about to read 4, iclass 27, count 0 2006.197.07:46:09.23#ibcon#read 4, iclass 27, count 0 2006.197.07:46:09.23#ibcon#about to read 5, iclass 27, count 0 2006.197.07:46:09.23#ibcon#read 5, iclass 27, count 0 2006.197.07:46:09.23#ibcon#about to read 6, iclass 27, count 0 2006.197.07:46:09.23#ibcon#read 6, iclass 27, count 0 2006.197.07:46:09.23#ibcon#end of sib2, iclass 27, count 0 2006.197.07:46:09.23#ibcon#*mode == 0, iclass 27, count 0 2006.197.07:46:09.23#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.197.07:46:09.23#ibcon#[26=FRQ=06,772.99\r\n] 2006.197.07:46:09.23#ibcon#*before write, iclass 27, count 0 2006.197.07:46:09.23#ibcon#enter sib2, iclass 27, count 0 2006.197.07:46:09.23#ibcon#flushed, iclass 27, count 0 2006.197.07:46:09.23#ibcon#about to write, iclass 27, count 0 2006.197.07:46:09.23#ibcon#wrote, iclass 27, count 0 2006.197.07:46:09.23#ibcon#about to read 3, iclass 27, count 0 2006.197.07:46:09.27#ibcon#read 3, iclass 27, count 0 2006.197.07:46:09.27#ibcon#about to read 4, iclass 27, count 0 2006.197.07:46:09.27#ibcon#read 4, iclass 27, count 0 2006.197.07:46:09.27#ibcon#about to read 5, iclass 27, count 0 2006.197.07:46:09.27#ibcon#read 5, iclass 27, count 0 2006.197.07:46:09.27#ibcon#about to read 6, iclass 27, count 0 2006.197.07:46:09.27#ibcon#read 6, iclass 27, count 0 2006.197.07:46:09.27#ibcon#end of sib2, iclass 27, count 0 2006.197.07:46:09.27#ibcon#*after write, iclass 27, count 0 2006.197.07:46:09.27#ibcon#*before return 0, iclass 27, count 0 2006.197.07:46:09.27#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.197.07:46:09.27#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.197.07:46:09.27#ibcon#about to clear, iclass 27 cls_cnt 0 2006.197.07:46:09.27#ibcon#cleared, iclass 27 cls_cnt 0 2006.197.07:46:09.27$vc4f8/va=6,6 2006.197.07:46:09.27#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.197.07:46:09.27#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.197.07:46:09.27#ibcon#ireg 11 cls_cnt 2 2006.197.07:46:09.27#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.197.07:46:09.33#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.197.07:46:09.33#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.197.07:46:09.33#ibcon#enter wrdev, iclass 29, count 2 2006.197.07:46:09.33#ibcon#first serial, iclass 29, count 2 2006.197.07:46:09.33#ibcon#enter sib2, iclass 29, count 2 2006.197.07:46:09.33#ibcon#flushed, iclass 29, count 2 2006.197.07:46:09.33#ibcon#about to write, iclass 29, count 2 2006.197.07:46:09.33#ibcon#wrote, iclass 29, count 2 2006.197.07:46:09.33#ibcon#about to read 3, iclass 29, count 2 2006.197.07:46:09.35#ibcon#read 3, iclass 29, count 2 2006.197.07:46:09.35#ibcon#about to read 4, iclass 29, count 2 2006.197.07:46:09.35#ibcon#read 4, iclass 29, count 2 2006.197.07:46:09.35#ibcon#about to read 5, iclass 29, count 2 2006.197.07:46:09.35#ibcon#read 5, iclass 29, count 2 2006.197.07:46:09.35#ibcon#about to read 6, iclass 29, count 2 2006.197.07:46:09.35#ibcon#read 6, iclass 29, count 2 2006.197.07:46:09.35#ibcon#end of sib2, iclass 29, count 2 2006.197.07:46:09.35#ibcon#*mode == 0, iclass 29, count 2 2006.197.07:46:09.35#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.197.07:46:09.35#ibcon#[25=AT06-06\r\n] 2006.197.07:46:09.35#ibcon#*before write, iclass 29, count 2 2006.197.07:46:09.35#ibcon#enter sib2, iclass 29, count 2 2006.197.07:46:09.35#ibcon#flushed, iclass 29, count 2 2006.197.07:46:09.35#ibcon#about to write, iclass 29, count 2 2006.197.07:46:09.35#ibcon#wrote, iclass 29, count 2 2006.197.07:46:09.35#ibcon#about to read 3, iclass 29, count 2 2006.197.07:46:09.38#ibcon#read 3, iclass 29, count 2 2006.197.07:46:09.38#ibcon#about to read 4, iclass 29, count 2 2006.197.07:46:09.38#ibcon#read 4, iclass 29, count 2 2006.197.07:46:09.38#ibcon#about to read 5, iclass 29, count 2 2006.197.07:46:09.38#ibcon#read 5, iclass 29, count 2 2006.197.07:46:09.38#ibcon#about to read 6, iclass 29, count 2 2006.197.07:46:09.38#ibcon#read 6, iclass 29, count 2 2006.197.07:46:09.38#ibcon#end of sib2, iclass 29, count 2 2006.197.07:46:09.38#ibcon#*after write, iclass 29, count 2 2006.197.07:46:09.38#ibcon#*before return 0, iclass 29, count 2 2006.197.07:46:09.38#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.197.07:46:09.38#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.197.07:46:09.38#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.197.07:46:09.38#ibcon#ireg 7 cls_cnt 0 2006.197.07:46:09.38#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.197.07:46:09.50#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.197.07:46:09.50#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.197.07:46:09.50#ibcon#enter wrdev, iclass 29, count 0 2006.197.07:46:09.50#ibcon#first serial, iclass 29, count 0 2006.197.07:46:09.50#ibcon#enter sib2, iclass 29, count 0 2006.197.07:46:09.50#ibcon#flushed, iclass 29, count 0 2006.197.07:46:09.50#ibcon#about to write, iclass 29, count 0 2006.197.07:46:09.50#ibcon#wrote, iclass 29, count 0 2006.197.07:46:09.50#ibcon#about to read 3, iclass 29, count 0 2006.197.07:46:09.52#ibcon#read 3, iclass 29, count 0 2006.197.07:46:09.52#ibcon#about to read 4, iclass 29, count 0 2006.197.07:46:09.52#ibcon#read 4, iclass 29, count 0 2006.197.07:46:09.52#ibcon#about to read 5, iclass 29, count 0 2006.197.07:46:09.52#ibcon#read 5, iclass 29, count 0 2006.197.07:46:09.52#ibcon#about to read 6, iclass 29, count 0 2006.197.07:46:09.52#ibcon#read 6, iclass 29, count 0 2006.197.07:46:09.52#ibcon#end of sib2, iclass 29, count 0 2006.197.07:46:09.52#ibcon#*mode == 0, iclass 29, count 0 2006.197.07:46:09.52#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.197.07:46:09.52#ibcon#[25=USB\r\n] 2006.197.07:46:09.52#ibcon#*before write, iclass 29, count 0 2006.197.07:46:09.52#ibcon#enter sib2, iclass 29, count 0 2006.197.07:46:09.52#ibcon#flushed, iclass 29, count 0 2006.197.07:46:09.52#ibcon#about to write, iclass 29, count 0 2006.197.07:46:09.52#ibcon#wrote, iclass 29, count 0 2006.197.07:46:09.52#ibcon#about to read 3, iclass 29, count 0 2006.197.07:46:09.55#ibcon#read 3, iclass 29, count 0 2006.197.07:46:09.55#ibcon#about to read 4, iclass 29, count 0 2006.197.07:46:09.55#ibcon#read 4, iclass 29, count 0 2006.197.07:46:09.55#ibcon#about to read 5, iclass 29, count 0 2006.197.07:46:09.55#ibcon#read 5, iclass 29, count 0 2006.197.07:46:09.55#ibcon#about to read 6, iclass 29, count 0 2006.197.07:46:09.55#ibcon#read 6, iclass 29, count 0 2006.197.07:46:09.55#ibcon#end of sib2, iclass 29, count 0 2006.197.07:46:09.55#ibcon#*after write, iclass 29, count 0 2006.197.07:46:09.55#ibcon#*before return 0, iclass 29, count 0 2006.197.07:46:09.55#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.197.07:46:09.55#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.197.07:46:09.55#ibcon#about to clear, iclass 29 cls_cnt 0 2006.197.07:46:09.55#ibcon#cleared, iclass 29 cls_cnt 0 2006.197.07:46:09.55$vc4f8/valo=7,832.99 2006.197.07:46:09.55#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.197.07:46:09.55#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.197.07:46:09.55#ibcon#ireg 17 cls_cnt 0 2006.197.07:46:09.55#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.197.07:46:09.55#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.197.07:46:09.55#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.197.07:46:09.55#ibcon#enter wrdev, iclass 31, count 0 2006.197.07:46:09.55#ibcon#first serial, iclass 31, count 0 2006.197.07:46:09.55#ibcon#enter sib2, iclass 31, count 0 2006.197.07:46:09.55#ibcon#flushed, iclass 31, count 0 2006.197.07:46:09.55#ibcon#about to write, iclass 31, count 0 2006.197.07:46:09.55#ibcon#wrote, iclass 31, count 0 2006.197.07:46:09.55#ibcon#about to read 3, iclass 31, count 0 2006.197.07:46:09.57#ibcon#read 3, iclass 31, count 0 2006.197.07:46:09.57#ibcon#about to read 4, iclass 31, count 0 2006.197.07:46:09.57#ibcon#read 4, iclass 31, count 0 2006.197.07:46:09.57#ibcon#about to read 5, iclass 31, count 0 2006.197.07:46:09.57#ibcon#read 5, iclass 31, count 0 2006.197.07:46:09.57#ibcon#about to read 6, iclass 31, count 0 2006.197.07:46:09.57#ibcon#read 6, iclass 31, count 0 2006.197.07:46:09.57#ibcon#end of sib2, iclass 31, count 0 2006.197.07:46:09.57#ibcon#*mode == 0, iclass 31, count 0 2006.197.07:46:09.57#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.197.07:46:09.57#ibcon#[26=FRQ=07,832.99\r\n] 2006.197.07:46:09.57#ibcon#*before write, iclass 31, count 0 2006.197.07:46:09.57#ibcon#enter sib2, iclass 31, count 0 2006.197.07:46:09.57#ibcon#flushed, iclass 31, count 0 2006.197.07:46:09.57#ibcon#about to write, iclass 31, count 0 2006.197.07:46:09.57#ibcon#wrote, iclass 31, count 0 2006.197.07:46:09.57#ibcon#about to read 3, iclass 31, count 0 2006.197.07:46:09.61#ibcon#read 3, iclass 31, count 0 2006.197.07:46:09.61#ibcon#about to read 4, iclass 31, count 0 2006.197.07:46:09.61#ibcon#read 4, iclass 31, count 0 2006.197.07:46:09.61#ibcon#about to read 5, iclass 31, count 0 2006.197.07:46:09.61#ibcon#read 5, iclass 31, count 0 2006.197.07:46:09.61#ibcon#about to read 6, iclass 31, count 0 2006.197.07:46:09.61#ibcon#read 6, iclass 31, count 0 2006.197.07:46:09.61#ibcon#end of sib2, iclass 31, count 0 2006.197.07:46:09.61#ibcon#*after write, iclass 31, count 0 2006.197.07:46:09.61#ibcon#*before return 0, iclass 31, count 0 2006.197.07:46:09.61#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.197.07:46:09.61#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.197.07:46:09.61#ibcon#about to clear, iclass 31 cls_cnt 0 2006.197.07:46:09.61#ibcon#cleared, iclass 31 cls_cnt 0 2006.197.07:46:09.61$vc4f8/va=7,6 2006.197.07:46:09.61#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.197.07:46:09.61#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.197.07:46:09.61#ibcon#ireg 11 cls_cnt 2 2006.197.07:46:09.61#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.197.07:46:09.67#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.197.07:46:09.67#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.197.07:46:09.67#ibcon#enter wrdev, iclass 33, count 2 2006.197.07:46:09.67#ibcon#first serial, iclass 33, count 2 2006.197.07:46:09.67#ibcon#enter sib2, iclass 33, count 2 2006.197.07:46:09.67#ibcon#flushed, iclass 33, count 2 2006.197.07:46:09.67#ibcon#about to write, iclass 33, count 2 2006.197.07:46:09.67#ibcon#wrote, iclass 33, count 2 2006.197.07:46:09.67#ibcon#about to read 3, iclass 33, count 2 2006.197.07:46:09.69#ibcon#read 3, iclass 33, count 2 2006.197.07:46:09.69#ibcon#about to read 4, iclass 33, count 2 2006.197.07:46:09.69#ibcon#read 4, iclass 33, count 2 2006.197.07:46:09.69#ibcon#about to read 5, iclass 33, count 2 2006.197.07:46:09.69#ibcon#read 5, iclass 33, count 2 2006.197.07:46:09.69#ibcon#about to read 6, iclass 33, count 2 2006.197.07:46:09.69#ibcon#read 6, iclass 33, count 2 2006.197.07:46:09.69#ibcon#end of sib2, iclass 33, count 2 2006.197.07:46:09.69#ibcon#*mode == 0, iclass 33, count 2 2006.197.07:46:09.69#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.197.07:46:09.69#ibcon#[25=AT07-06\r\n] 2006.197.07:46:09.69#ibcon#*before write, iclass 33, count 2 2006.197.07:46:09.69#ibcon#enter sib2, iclass 33, count 2 2006.197.07:46:09.69#ibcon#flushed, iclass 33, count 2 2006.197.07:46:09.69#ibcon#about to write, iclass 33, count 2 2006.197.07:46:09.69#ibcon#wrote, iclass 33, count 2 2006.197.07:46:09.69#ibcon#about to read 3, iclass 33, count 2 2006.197.07:46:09.72#ibcon#read 3, iclass 33, count 2 2006.197.07:46:09.72#ibcon#about to read 4, iclass 33, count 2 2006.197.07:46:09.72#ibcon#read 4, iclass 33, count 2 2006.197.07:46:09.72#ibcon#about to read 5, iclass 33, count 2 2006.197.07:46:09.72#ibcon#read 5, iclass 33, count 2 2006.197.07:46:09.72#ibcon#about to read 6, iclass 33, count 2 2006.197.07:46:09.72#ibcon#read 6, iclass 33, count 2 2006.197.07:46:09.72#ibcon#end of sib2, iclass 33, count 2 2006.197.07:46:09.72#ibcon#*after write, iclass 33, count 2 2006.197.07:46:09.72#ibcon#*before return 0, iclass 33, count 2 2006.197.07:46:09.72#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.197.07:46:09.72#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.197.07:46:09.72#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.197.07:46:09.72#ibcon#ireg 7 cls_cnt 0 2006.197.07:46:09.72#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.197.07:46:09.84#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.197.07:46:09.84#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.197.07:46:09.84#ibcon#enter wrdev, iclass 33, count 0 2006.197.07:46:09.84#ibcon#first serial, iclass 33, count 0 2006.197.07:46:09.84#ibcon#enter sib2, iclass 33, count 0 2006.197.07:46:09.84#ibcon#flushed, iclass 33, count 0 2006.197.07:46:09.84#ibcon#about to write, iclass 33, count 0 2006.197.07:46:09.84#ibcon#wrote, iclass 33, count 0 2006.197.07:46:09.84#ibcon#about to read 3, iclass 33, count 0 2006.197.07:46:09.86#ibcon#read 3, iclass 33, count 0 2006.197.07:46:09.86#ibcon#about to read 4, iclass 33, count 0 2006.197.07:46:09.86#ibcon#read 4, iclass 33, count 0 2006.197.07:46:09.86#ibcon#about to read 5, iclass 33, count 0 2006.197.07:46:09.86#ibcon#read 5, iclass 33, count 0 2006.197.07:46:09.86#ibcon#about to read 6, iclass 33, count 0 2006.197.07:46:09.86#ibcon#read 6, iclass 33, count 0 2006.197.07:46:09.86#ibcon#end of sib2, iclass 33, count 0 2006.197.07:46:09.86#ibcon#*mode == 0, iclass 33, count 0 2006.197.07:46:09.86#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.197.07:46:09.86#ibcon#[25=USB\r\n] 2006.197.07:46:09.86#ibcon#*before write, iclass 33, count 0 2006.197.07:46:09.86#ibcon#enter sib2, iclass 33, count 0 2006.197.07:46:09.86#ibcon#flushed, iclass 33, count 0 2006.197.07:46:09.86#ibcon#about to write, iclass 33, count 0 2006.197.07:46:09.86#ibcon#wrote, iclass 33, count 0 2006.197.07:46:09.86#ibcon#about to read 3, iclass 33, count 0 2006.197.07:46:09.89#ibcon#read 3, iclass 33, count 0 2006.197.07:46:09.89#ibcon#about to read 4, iclass 33, count 0 2006.197.07:46:09.89#ibcon#read 4, iclass 33, count 0 2006.197.07:46:09.89#ibcon#about to read 5, iclass 33, count 0 2006.197.07:46:09.89#ibcon#read 5, iclass 33, count 0 2006.197.07:46:09.89#ibcon#about to read 6, iclass 33, count 0 2006.197.07:46:09.89#ibcon#read 6, iclass 33, count 0 2006.197.07:46:09.89#ibcon#end of sib2, iclass 33, count 0 2006.197.07:46:09.89#ibcon#*after write, iclass 33, count 0 2006.197.07:46:09.89#ibcon#*before return 0, iclass 33, count 0 2006.197.07:46:09.89#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.197.07:46:09.89#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.197.07:46:09.89#ibcon#about to clear, iclass 33 cls_cnt 0 2006.197.07:46:09.89#ibcon#cleared, iclass 33 cls_cnt 0 2006.197.07:46:09.89$vc4f8/valo=8,852.99 2006.197.07:46:09.89#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.197.07:46:09.89#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.197.07:46:09.89#ibcon#ireg 17 cls_cnt 0 2006.197.07:46:09.89#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.197.07:46:09.89#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.197.07:46:09.89#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.197.07:46:09.89#ibcon#enter wrdev, iclass 35, count 0 2006.197.07:46:09.89#ibcon#first serial, iclass 35, count 0 2006.197.07:46:09.89#ibcon#enter sib2, iclass 35, count 0 2006.197.07:46:09.89#ibcon#flushed, iclass 35, count 0 2006.197.07:46:09.89#ibcon#about to write, iclass 35, count 0 2006.197.07:46:09.89#ibcon#wrote, iclass 35, count 0 2006.197.07:46:09.89#ibcon#about to read 3, iclass 35, count 0 2006.197.07:46:09.91#ibcon#read 3, iclass 35, count 0 2006.197.07:46:09.91#ibcon#about to read 4, iclass 35, count 0 2006.197.07:46:09.91#ibcon#read 4, iclass 35, count 0 2006.197.07:46:09.91#ibcon#about to read 5, iclass 35, count 0 2006.197.07:46:09.91#ibcon#read 5, iclass 35, count 0 2006.197.07:46:09.91#ibcon#about to read 6, iclass 35, count 0 2006.197.07:46:09.91#ibcon#read 6, iclass 35, count 0 2006.197.07:46:09.91#ibcon#end of sib2, iclass 35, count 0 2006.197.07:46:09.91#ibcon#*mode == 0, iclass 35, count 0 2006.197.07:46:09.91#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.197.07:46:09.91#ibcon#[26=FRQ=08,852.99\r\n] 2006.197.07:46:09.91#ibcon#*before write, iclass 35, count 0 2006.197.07:46:09.91#ibcon#enter sib2, iclass 35, count 0 2006.197.07:46:09.91#ibcon#flushed, iclass 35, count 0 2006.197.07:46:09.91#ibcon#about to write, iclass 35, count 0 2006.197.07:46:09.91#ibcon#wrote, iclass 35, count 0 2006.197.07:46:09.91#ibcon#about to read 3, iclass 35, count 0 2006.197.07:46:09.95#ibcon#read 3, iclass 35, count 0 2006.197.07:46:09.95#ibcon#about to read 4, iclass 35, count 0 2006.197.07:46:09.95#ibcon#read 4, iclass 35, count 0 2006.197.07:46:09.95#ibcon#about to read 5, iclass 35, count 0 2006.197.07:46:09.95#ibcon#read 5, iclass 35, count 0 2006.197.07:46:09.95#ibcon#about to read 6, iclass 35, count 0 2006.197.07:46:09.95#ibcon#read 6, iclass 35, count 0 2006.197.07:46:09.95#ibcon#end of sib2, iclass 35, count 0 2006.197.07:46:09.95#ibcon#*after write, iclass 35, count 0 2006.197.07:46:09.95#ibcon#*before return 0, iclass 35, count 0 2006.197.07:46:09.95#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.197.07:46:09.95#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.197.07:46:09.95#ibcon#about to clear, iclass 35 cls_cnt 0 2006.197.07:46:09.95#ibcon#cleared, iclass 35 cls_cnt 0 2006.197.07:46:09.95$vc4f8/va=8,7 2006.197.07:46:09.95#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.197.07:46:09.95#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.197.07:46:09.95#ibcon#ireg 11 cls_cnt 2 2006.197.07:46:09.95#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.197.07:46:10.01#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.197.07:46:10.01#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.197.07:46:10.01#ibcon#enter wrdev, iclass 37, count 2 2006.197.07:46:10.01#ibcon#first serial, iclass 37, count 2 2006.197.07:46:10.01#ibcon#enter sib2, iclass 37, count 2 2006.197.07:46:10.01#ibcon#flushed, iclass 37, count 2 2006.197.07:46:10.01#ibcon#about to write, iclass 37, count 2 2006.197.07:46:10.01#ibcon#wrote, iclass 37, count 2 2006.197.07:46:10.01#ibcon#about to read 3, iclass 37, count 2 2006.197.07:46:10.03#ibcon#read 3, iclass 37, count 2 2006.197.07:46:10.03#ibcon#about to read 4, iclass 37, count 2 2006.197.07:46:10.03#ibcon#read 4, iclass 37, count 2 2006.197.07:46:10.03#ibcon#about to read 5, iclass 37, count 2 2006.197.07:46:10.03#ibcon#read 5, iclass 37, count 2 2006.197.07:46:10.03#ibcon#about to read 6, iclass 37, count 2 2006.197.07:46:10.03#ibcon#read 6, iclass 37, count 2 2006.197.07:46:10.03#ibcon#end of sib2, iclass 37, count 2 2006.197.07:46:10.03#ibcon#*mode == 0, iclass 37, count 2 2006.197.07:46:10.03#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.197.07:46:10.03#ibcon#[25=AT08-07\r\n] 2006.197.07:46:10.03#ibcon#*before write, iclass 37, count 2 2006.197.07:46:10.03#ibcon#enter sib2, iclass 37, count 2 2006.197.07:46:10.03#ibcon#flushed, iclass 37, count 2 2006.197.07:46:10.03#ibcon#about to write, iclass 37, count 2 2006.197.07:46:10.03#ibcon#wrote, iclass 37, count 2 2006.197.07:46:10.03#ibcon#about to read 3, iclass 37, count 2 2006.197.07:46:10.06#ibcon#read 3, iclass 37, count 2 2006.197.07:46:10.06#ibcon#about to read 4, iclass 37, count 2 2006.197.07:46:10.06#ibcon#read 4, iclass 37, count 2 2006.197.07:46:10.06#ibcon#about to read 5, iclass 37, count 2 2006.197.07:46:10.06#ibcon#read 5, iclass 37, count 2 2006.197.07:46:10.06#ibcon#about to read 6, iclass 37, count 2 2006.197.07:46:10.06#ibcon#read 6, iclass 37, count 2 2006.197.07:46:10.06#ibcon#end of sib2, iclass 37, count 2 2006.197.07:46:10.06#ibcon#*after write, iclass 37, count 2 2006.197.07:46:10.06#ibcon#*before return 0, iclass 37, count 2 2006.197.07:46:10.06#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.197.07:46:10.06#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.197.07:46:10.06#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.197.07:46:10.06#ibcon#ireg 7 cls_cnt 0 2006.197.07:46:10.06#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.197.07:46:10.18#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.197.07:46:10.18#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.197.07:46:10.18#ibcon#enter wrdev, iclass 37, count 0 2006.197.07:46:10.18#ibcon#first serial, iclass 37, count 0 2006.197.07:46:10.18#ibcon#enter sib2, iclass 37, count 0 2006.197.07:46:10.18#ibcon#flushed, iclass 37, count 0 2006.197.07:46:10.18#ibcon#about to write, iclass 37, count 0 2006.197.07:46:10.18#ibcon#wrote, iclass 37, count 0 2006.197.07:46:10.18#ibcon#about to read 3, iclass 37, count 0 2006.197.07:46:10.20#ibcon#read 3, iclass 37, count 0 2006.197.07:46:10.20#ibcon#about to read 4, iclass 37, count 0 2006.197.07:46:10.20#ibcon#read 4, iclass 37, count 0 2006.197.07:46:10.20#ibcon#about to read 5, iclass 37, count 0 2006.197.07:46:10.20#ibcon#read 5, iclass 37, count 0 2006.197.07:46:10.20#ibcon#about to read 6, iclass 37, count 0 2006.197.07:46:10.20#ibcon#read 6, iclass 37, count 0 2006.197.07:46:10.20#ibcon#end of sib2, iclass 37, count 0 2006.197.07:46:10.20#ibcon#*mode == 0, iclass 37, count 0 2006.197.07:46:10.20#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.197.07:46:10.20#ibcon#[25=USB\r\n] 2006.197.07:46:10.20#ibcon#*before write, iclass 37, count 0 2006.197.07:46:10.20#ibcon#enter sib2, iclass 37, count 0 2006.197.07:46:10.20#ibcon#flushed, iclass 37, count 0 2006.197.07:46:10.20#ibcon#about to write, iclass 37, count 0 2006.197.07:46:10.20#ibcon#wrote, iclass 37, count 0 2006.197.07:46:10.20#ibcon#about to read 3, iclass 37, count 0 2006.197.07:46:10.23#ibcon#read 3, iclass 37, count 0 2006.197.07:46:10.23#ibcon#about to read 4, iclass 37, count 0 2006.197.07:46:10.23#ibcon#read 4, iclass 37, count 0 2006.197.07:46:10.23#ibcon#about to read 5, iclass 37, count 0 2006.197.07:46:10.23#ibcon#read 5, iclass 37, count 0 2006.197.07:46:10.23#ibcon#about to read 6, iclass 37, count 0 2006.197.07:46:10.23#ibcon#read 6, iclass 37, count 0 2006.197.07:46:10.23#ibcon#end of sib2, iclass 37, count 0 2006.197.07:46:10.23#ibcon#*after write, iclass 37, count 0 2006.197.07:46:10.23#ibcon#*before return 0, iclass 37, count 0 2006.197.07:46:10.23#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.197.07:46:10.23#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.197.07:46:10.23#ibcon#about to clear, iclass 37 cls_cnt 0 2006.197.07:46:10.23#ibcon#cleared, iclass 37 cls_cnt 0 2006.197.07:46:10.23$vc4f8/vblo=1,632.99 2006.197.07:46:10.23#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.197.07:46:10.23#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.197.07:46:10.23#ibcon#ireg 17 cls_cnt 0 2006.197.07:46:10.23#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.197.07:46:10.23#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.197.07:46:10.23#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.197.07:46:10.23#ibcon#enter wrdev, iclass 39, count 0 2006.197.07:46:10.23#ibcon#first serial, iclass 39, count 0 2006.197.07:46:10.23#ibcon#enter sib2, iclass 39, count 0 2006.197.07:46:10.23#ibcon#flushed, iclass 39, count 0 2006.197.07:46:10.23#ibcon#about to write, iclass 39, count 0 2006.197.07:46:10.23#ibcon#wrote, iclass 39, count 0 2006.197.07:46:10.23#ibcon#about to read 3, iclass 39, count 0 2006.197.07:46:10.25#ibcon#read 3, iclass 39, count 0 2006.197.07:46:10.25#ibcon#about to read 4, iclass 39, count 0 2006.197.07:46:10.25#ibcon#read 4, iclass 39, count 0 2006.197.07:46:10.25#ibcon#about to read 5, iclass 39, count 0 2006.197.07:46:10.25#ibcon#read 5, iclass 39, count 0 2006.197.07:46:10.25#ibcon#about to read 6, iclass 39, count 0 2006.197.07:46:10.25#ibcon#read 6, iclass 39, count 0 2006.197.07:46:10.25#ibcon#end of sib2, iclass 39, count 0 2006.197.07:46:10.25#ibcon#*mode == 0, iclass 39, count 0 2006.197.07:46:10.25#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.197.07:46:10.25#ibcon#[28=FRQ=01,632.99\r\n] 2006.197.07:46:10.25#ibcon#*before write, iclass 39, count 0 2006.197.07:46:10.25#ibcon#enter sib2, iclass 39, count 0 2006.197.07:46:10.25#ibcon#flushed, iclass 39, count 0 2006.197.07:46:10.25#ibcon#about to write, iclass 39, count 0 2006.197.07:46:10.25#ibcon#wrote, iclass 39, count 0 2006.197.07:46:10.25#ibcon#about to read 3, iclass 39, count 0 2006.197.07:46:10.29#ibcon#read 3, iclass 39, count 0 2006.197.07:46:10.29#ibcon#about to read 4, iclass 39, count 0 2006.197.07:46:10.29#ibcon#read 4, iclass 39, count 0 2006.197.07:46:10.29#ibcon#about to read 5, iclass 39, count 0 2006.197.07:46:10.29#ibcon#read 5, iclass 39, count 0 2006.197.07:46:10.29#ibcon#about to read 6, iclass 39, count 0 2006.197.07:46:10.29#ibcon#read 6, iclass 39, count 0 2006.197.07:46:10.29#ibcon#end of sib2, iclass 39, count 0 2006.197.07:46:10.29#ibcon#*after write, iclass 39, count 0 2006.197.07:46:10.29#ibcon#*before return 0, iclass 39, count 0 2006.197.07:46:10.29#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.197.07:46:10.29#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.197.07:46:10.29#ibcon#about to clear, iclass 39 cls_cnt 0 2006.197.07:46:10.29#ibcon#cleared, iclass 39 cls_cnt 0 2006.197.07:46:10.29$vc4f8/vb=1,4 2006.197.07:46:10.29#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.197.07:46:10.29#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.197.07:46:10.29#ibcon#ireg 11 cls_cnt 2 2006.197.07:46:10.29#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.197.07:46:10.29#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.197.07:46:10.29#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.197.07:46:10.29#ibcon#enter wrdev, iclass 3, count 2 2006.197.07:46:10.29#ibcon#first serial, iclass 3, count 2 2006.197.07:46:10.29#ibcon#enter sib2, iclass 3, count 2 2006.197.07:46:10.29#ibcon#flushed, iclass 3, count 2 2006.197.07:46:10.29#ibcon#about to write, iclass 3, count 2 2006.197.07:46:10.29#ibcon#wrote, iclass 3, count 2 2006.197.07:46:10.29#ibcon#about to read 3, iclass 3, count 2 2006.197.07:46:10.31#ibcon#read 3, iclass 3, count 2 2006.197.07:46:10.31#ibcon#about to read 4, iclass 3, count 2 2006.197.07:46:10.31#ibcon#read 4, iclass 3, count 2 2006.197.07:46:10.31#ibcon#about to read 5, iclass 3, count 2 2006.197.07:46:10.31#ibcon#read 5, iclass 3, count 2 2006.197.07:46:10.31#ibcon#about to read 6, iclass 3, count 2 2006.197.07:46:10.31#ibcon#read 6, iclass 3, count 2 2006.197.07:46:10.31#ibcon#end of sib2, iclass 3, count 2 2006.197.07:46:10.31#ibcon#*mode == 0, iclass 3, count 2 2006.197.07:46:10.31#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.197.07:46:10.31#ibcon#[27=AT01-04\r\n] 2006.197.07:46:10.31#ibcon#*before write, iclass 3, count 2 2006.197.07:46:10.31#ibcon#enter sib2, iclass 3, count 2 2006.197.07:46:10.31#ibcon#flushed, iclass 3, count 2 2006.197.07:46:10.31#ibcon#about to write, iclass 3, count 2 2006.197.07:46:10.31#ibcon#wrote, iclass 3, count 2 2006.197.07:46:10.31#ibcon#about to read 3, iclass 3, count 2 2006.197.07:46:10.34#ibcon#read 3, iclass 3, count 2 2006.197.07:46:10.34#ibcon#about to read 4, iclass 3, count 2 2006.197.07:46:10.34#ibcon#read 4, iclass 3, count 2 2006.197.07:46:10.34#ibcon#about to read 5, iclass 3, count 2 2006.197.07:46:10.34#ibcon#read 5, iclass 3, count 2 2006.197.07:46:10.34#ibcon#about to read 6, iclass 3, count 2 2006.197.07:46:10.34#ibcon#read 6, iclass 3, count 2 2006.197.07:46:10.34#ibcon#end of sib2, iclass 3, count 2 2006.197.07:46:10.34#ibcon#*after write, iclass 3, count 2 2006.197.07:46:10.34#ibcon#*before return 0, iclass 3, count 2 2006.197.07:46:10.34#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.197.07:46:10.34#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.197.07:46:10.34#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.197.07:46:10.34#ibcon#ireg 7 cls_cnt 0 2006.197.07:46:10.34#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.197.07:46:10.46#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.197.07:46:10.46#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.197.07:46:10.46#ibcon#enter wrdev, iclass 3, count 0 2006.197.07:46:10.46#ibcon#first serial, iclass 3, count 0 2006.197.07:46:10.46#ibcon#enter sib2, iclass 3, count 0 2006.197.07:46:10.46#ibcon#flushed, iclass 3, count 0 2006.197.07:46:10.46#ibcon#about to write, iclass 3, count 0 2006.197.07:46:10.46#ibcon#wrote, iclass 3, count 0 2006.197.07:46:10.46#ibcon#about to read 3, iclass 3, count 0 2006.197.07:46:10.48#ibcon#read 3, iclass 3, count 0 2006.197.07:46:10.48#ibcon#about to read 4, iclass 3, count 0 2006.197.07:46:10.48#ibcon#read 4, iclass 3, count 0 2006.197.07:46:10.48#ibcon#about to read 5, iclass 3, count 0 2006.197.07:46:10.48#ibcon#read 5, iclass 3, count 0 2006.197.07:46:10.48#ibcon#about to read 6, iclass 3, count 0 2006.197.07:46:10.48#ibcon#read 6, iclass 3, count 0 2006.197.07:46:10.48#ibcon#end of sib2, iclass 3, count 0 2006.197.07:46:10.48#ibcon#*mode == 0, iclass 3, count 0 2006.197.07:46:10.48#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.197.07:46:10.48#ibcon#[27=USB\r\n] 2006.197.07:46:10.48#ibcon#*before write, iclass 3, count 0 2006.197.07:46:10.48#ibcon#enter sib2, iclass 3, count 0 2006.197.07:46:10.48#ibcon#flushed, iclass 3, count 0 2006.197.07:46:10.48#ibcon#about to write, iclass 3, count 0 2006.197.07:46:10.48#ibcon#wrote, iclass 3, count 0 2006.197.07:46:10.48#ibcon#about to read 3, iclass 3, count 0 2006.197.07:46:10.51#ibcon#read 3, iclass 3, count 0 2006.197.07:46:10.51#ibcon#about to read 4, iclass 3, count 0 2006.197.07:46:10.51#ibcon#read 4, iclass 3, count 0 2006.197.07:46:10.51#ibcon#about to read 5, iclass 3, count 0 2006.197.07:46:10.51#ibcon#read 5, iclass 3, count 0 2006.197.07:46:10.51#ibcon#about to read 6, iclass 3, count 0 2006.197.07:46:10.51#ibcon#read 6, iclass 3, count 0 2006.197.07:46:10.51#ibcon#end of sib2, iclass 3, count 0 2006.197.07:46:10.51#ibcon#*after write, iclass 3, count 0 2006.197.07:46:10.51#ibcon#*before return 0, iclass 3, count 0 2006.197.07:46:10.51#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.197.07:46:10.51#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.197.07:46:10.51#ibcon#about to clear, iclass 3 cls_cnt 0 2006.197.07:46:10.51#ibcon#cleared, iclass 3 cls_cnt 0 2006.197.07:46:10.51$vc4f8/vblo=2,640.99 2006.197.07:46:10.51#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.197.07:46:10.51#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.197.07:46:10.51#ibcon#ireg 17 cls_cnt 0 2006.197.07:46:10.51#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.197.07:46:10.51#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.197.07:46:10.51#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.197.07:46:10.51#ibcon#enter wrdev, iclass 5, count 0 2006.197.07:46:10.51#ibcon#first serial, iclass 5, count 0 2006.197.07:46:10.51#ibcon#enter sib2, iclass 5, count 0 2006.197.07:46:10.51#ibcon#flushed, iclass 5, count 0 2006.197.07:46:10.51#ibcon#about to write, iclass 5, count 0 2006.197.07:46:10.51#ibcon#wrote, iclass 5, count 0 2006.197.07:46:10.51#ibcon#about to read 3, iclass 5, count 0 2006.197.07:46:10.53#ibcon#read 3, iclass 5, count 0 2006.197.07:46:10.53#ibcon#about to read 4, iclass 5, count 0 2006.197.07:46:10.53#ibcon#read 4, iclass 5, count 0 2006.197.07:46:10.53#ibcon#about to read 5, iclass 5, count 0 2006.197.07:46:10.53#ibcon#read 5, iclass 5, count 0 2006.197.07:46:10.53#ibcon#about to read 6, iclass 5, count 0 2006.197.07:46:10.53#ibcon#read 6, iclass 5, count 0 2006.197.07:46:10.53#ibcon#end of sib2, iclass 5, count 0 2006.197.07:46:10.53#ibcon#*mode == 0, iclass 5, count 0 2006.197.07:46:10.53#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.197.07:46:10.53#ibcon#[28=FRQ=02,640.99\r\n] 2006.197.07:46:10.53#ibcon#*before write, iclass 5, count 0 2006.197.07:46:10.53#ibcon#enter sib2, iclass 5, count 0 2006.197.07:46:10.53#ibcon#flushed, iclass 5, count 0 2006.197.07:46:10.53#ibcon#about to write, iclass 5, count 0 2006.197.07:46:10.53#ibcon#wrote, iclass 5, count 0 2006.197.07:46:10.53#ibcon#about to read 3, iclass 5, count 0 2006.197.07:46:10.57#ibcon#read 3, iclass 5, count 0 2006.197.07:46:10.57#ibcon#about to read 4, iclass 5, count 0 2006.197.07:46:10.57#ibcon#read 4, iclass 5, count 0 2006.197.07:46:10.57#ibcon#about to read 5, iclass 5, count 0 2006.197.07:46:10.57#ibcon#read 5, iclass 5, count 0 2006.197.07:46:10.57#ibcon#about to read 6, iclass 5, count 0 2006.197.07:46:10.57#ibcon#read 6, iclass 5, count 0 2006.197.07:46:10.57#ibcon#end of sib2, iclass 5, count 0 2006.197.07:46:10.57#ibcon#*after write, iclass 5, count 0 2006.197.07:46:10.57#ibcon#*before return 0, iclass 5, count 0 2006.197.07:46:10.57#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.197.07:46:10.57#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.197.07:46:10.57#ibcon#about to clear, iclass 5 cls_cnt 0 2006.197.07:46:10.57#ibcon#cleared, iclass 5 cls_cnt 0 2006.197.07:46:10.57$vc4f8/vb=2,4 2006.197.07:46:10.57#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.197.07:46:10.57#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.197.07:46:10.57#ibcon#ireg 11 cls_cnt 2 2006.197.07:46:10.57#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.197.07:46:10.63#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.197.07:46:10.63#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.197.07:46:10.63#ibcon#enter wrdev, iclass 7, count 2 2006.197.07:46:10.63#ibcon#first serial, iclass 7, count 2 2006.197.07:46:10.63#ibcon#enter sib2, iclass 7, count 2 2006.197.07:46:10.63#ibcon#flushed, iclass 7, count 2 2006.197.07:46:10.63#ibcon#about to write, iclass 7, count 2 2006.197.07:46:10.63#ibcon#wrote, iclass 7, count 2 2006.197.07:46:10.63#ibcon#about to read 3, iclass 7, count 2 2006.197.07:46:10.65#ibcon#read 3, iclass 7, count 2 2006.197.07:46:10.65#ibcon#about to read 4, iclass 7, count 2 2006.197.07:46:10.65#ibcon#read 4, iclass 7, count 2 2006.197.07:46:10.65#ibcon#about to read 5, iclass 7, count 2 2006.197.07:46:10.65#ibcon#read 5, iclass 7, count 2 2006.197.07:46:10.65#ibcon#about to read 6, iclass 7, count 2 2006.197.07:46:10.65#ibcon#read 6, iclass 7, count 2 2006.197.07:46:10.65#ibcon#end of sib2, iclass 7, count 2 2006.197.07:46:10.65#ibcon#*mode == 0, iclass 7, count 2 2006.197.07:46:10.65#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.197.07:46:10.65#ibcon#[27=AT02-04\r\n] 2006.197.07:46:10.65#ibcon#*before write, iclass 7, count 2 2006.197.07:46:10.65#ibcon#enter sib2, iclass 7, count 2 2006.197.07:46:10.65#ibcon#flushed, iclass 7, count 2 2006.197.07:46:10.65#ibcon#about to write, iclass 7, count 2 2006.197.07:46:10.65#ibcon#wrote, iclass 7, count 2 2006.197.07:46:10.65#ibcon#about to read 3, iclass 7, count 2 2006.197.07:46:10.68#ibcon#read 3, iclass 7, count 2 2006.197.07:46:10.68#ibcon#about to read 4, iclass 7, count 2 2006.197.07:46:10.68#ibcon#read 4, iclass 7, count 2 2006.197.07:46:10.68#ibcon#about to read 5, iclass 7, count 2 2006.197.07:46:10.68#ibcon#read 5, iclass 7, count 2 2006.197.07:46:10.68#ibcon#about to read 6, iclass 7, count 2 2006.197.07:46:10.68#ibcon#read 6, iclass 7, count 2 2006.197.07:46:10.68#ibcon#end of sib2, iclass 7, count 2 2006.197.07:46:10.68#ibcon#*after write, iclass 7, count 2 2006.197.07:46:10.68#ibcon#*before return 0, iclass 7, count 2 2006.197.07:46:10.68#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.197.07:46:10.68#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.197.07:46:10.68#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.197.07:46:10.68#ibcon#ireg 7 cls_cnt 0 2006.197.07:46:10.68#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.197.07:46:10.80#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.197.07:46:10.80#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.197.07:46:10.80#ibcon#enter wrdev, iclass 7, count 0 2006.197.07:46:10.80#ibcon#first serial, iclass 7, count 0 2006.197.07:46:10.80#ibcon#enter sib2, iclass 7, count 0 2006.197.07:46:10.80#ibcon#flushed, iclass 7, count 0 2006.197.07:46:10.80#ibcon#about to write, iclass 7, count 0 2006.197.07:46:10.80#ibcon#wrote, iclass 7, count 0 2006.197.07:46:10.80#ibcon#about to read 3, iclass 7, count 0 2006.197.07:46:10.82#ibcon#read 3, iclass 7, count 0 2006.197.07:46:10.82#ibcon#about to read 4, iclass 7, count 0 2006.197.07:46:10.82#ibcon#read 4, iclass 7, count 0 2006.197.07:46:10.82#ibcon#about to read 5, iclass 7, count 0 2006.197.07:46:10.82#ibcon#read 5, iclass 7, count 0 2006.197.07:46:10.82#ibcon#about to read 6, iclass 7, count 0 2006.197.07:46:10.82#ibcon#read 6, iclass 7, count 0 2006.197.07:46:10.82#ibcon#end of sib2, iclass 7, count 0 2006.197.07:46:10.82#ibcon#*mode == 0, iclass 7, count 0 2006.197.07:46:10.82#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.197.07:46:10.82#ibcon#[27=USB\r\n] 2006.197.07:46:10.82#ibcon#*before write, iclass 7, count 0 2006.197.07:46:10.82#ibcon#enter sib2, iclass 7, count 0 2006.197.07:46:10.82#ibcon#flushed, iclass 7, count 0 2006.197.07:46:10.82#ibcon#about to write, iclass 7, count 0 2006.197.07:46:10.82#ibcon#wrote, iclass 7, count 0 2006.197.07:46:10.82#ibcon#about to read 3, iclass 7, count 0 2006.197.07:46:10.85#ibcon#read 3, iclass 7, count 0 2006.197.07:46:10.85#ibcon#about to read 4, iclass 7, count 0 2006.197.07:46:10.85#ibcon#read 4, iclass 7, count 0 2006.197.07:46:10.85#ibcon#about to read 5, iclass 7, count 0 2006.197.07:46:10.85#ibcon#read 5, iclass 7, count 0 2006.197.07:46:10.85#ibcon#about to read 6, iclass 7, count 0 2006.197.07:46:10.85#ibcon#read 6, iclass 7, count 0 2006.197.07:46:10.85#ibcon#end of sib2, iclass 7, count 0 2006.197.07:46:10.85#ibcon#*after write, iclass 7, count 0 2006.197.07:46:10.85#ibcon#*before return 0, iclass 7, count 0 2006.197.07:46:10.85#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.197.07:46:10.85#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.197.07:46:10.85#ibcon#about to clear, iclass 7 cls_cnt 0 2006.197.07:46:10.85#ibcon#cleared, iclass 7 cls_cnt 0 2006.197.07:46:10.85$vc4f8/vblo=3,656.99 2006.197.07:46:10.85#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.197.07:46:10.85#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.197.07:46:10.85#ibcon#ireg 17 cls_cnt 0 2006.197.07:46:10.85#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.197.07:46:10.85#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.197.07:46:10.85#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.197.07:46:10.85#ibcon#enter wrdev, iclass 11, count 0 2006.197.07:46:10.85#ibcon#first serial, iclass 11, count 0 2006.197.07:46:10.85#ibcon#enter sib2, iclass 11, count 0 2006.197.07:46:10.85#ibcon#flushed, iclass 11, count 0 2006.197.07:46:10.85#ibcon#about to write, iclass 11, count 0 2006.197.07:46:10.85#ibcon#wrote, iclass 11, count 0 2006.197.07:46:10.85#ibcon#about to read 3, iclass 11, count 0 2006.197.07:46:10.87#ibcon#read 3, iclass 11, count 0 2006.197.07:46:10.87#ibcon#about to read 4, iclass 11, count 0 2006.197.07:46:10.87#ibcon#read 4, iclass 11, count 0 2006.197.07:46:10.87#ibcon#about to read 5, iclass 11, count 0 2006.197.07:46:10.87#ibcon#read 5, iclass 11, count 0 2006.197.07:46:10.87#ibcon#about to read 6, iclass 11, count 0 2006.197.07:46:10.87#ibcon#read 6, iclass 11, count 0 2006.197.07:46:10.87#ibcon#end of sib2, iclass 11, count 0 2006.197.07:46:10.87#ibcon#*mode == 0, iclass 11, count 0 2006.197.07:46:10.87#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.197.07:46:10.87#ibcon#[28=FRQ=03,656.99\r\n] 2006.197.07:46:10.87#ibcon#*before write, iclass 11, count 0 2006.197.07:46:10.87#ibcon#enter sib2, iclass 11, count 0 2006.197.07:46:10.87#ibcon#flushed, iclass 11, count 0 2006.197.07:46:10.87#ibcon#about to write, iclass 11, count 0 2006.197.07:46:10.87#ibcon#wrote, iclass 11, count 0 2006.197.07:46:10.87#ibcon#about to read 3, iclass 11, count 0 2006.197.07:46:10.91#ibcon#read 3, iclass 11, count 0 2006.197.07:46:10.91#ibcon#about to read 4, iclass 11, count 0 2006.197.07:46:10.91#ibcon#read 4, iclass 11, count 0 2006.197.07:46:10.91#ibcon#about to read 5, iclass 11, count 0 2006.197.07:46:10.91#ibcon#read 5, iclass 11, count 0 2006.197.07:46:10.91#ibcon#about to read 6, iclass 11, count 0 2006.197.07:46:10.91#ibcon#read 6, iclass 11, count 0 2006.197.07:46:10.91#ibcon#end of sib2, iclass 11, count 0 2006.197.07:46:10.91#ibcon#*after write, iclass 11, count 0 2006.197.07:46:10.91#ibcon#*before return 0, iclass 11, count 0 2006.197.07:46:10.91#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.197.07:46:10.91#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.197.07:46:10.91#ibcon#about to clear, iclass 11 cls_cnt 0 2006.197.07:46:10.91#ibcon#cleared, iclass 11 cls_cnt 0 2006.197.07:46:10.91$vc4f8/vb=3,4 2006.197.07:46:10.91#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.197.07:46:10.91#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.197.07:46:10.91#ibcon#ireg 11 cls_cnt 2 2006.197.07:46:10.91#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.197.07:46:10.97#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.197.07:46:10.97#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.197.07:46:10.97#ibcon#enter wrdev, iclass 13, count 2 2006.197.07:46:10.97#ibcon#first serial, iclass 13, count 2 2006.197.07:46:10.97#ibcon#enter sib2, iclass 13, count 2 2006.197.07:46:10.97#ibcon#flushed, iclass 13, count 2 2006.197.07:46:10.97#ibcon#about to write, iclass 13, count 2 2006.197.07:46:10.97#ibcon#wrote, iclass 13, count 2 2006.197.07:46:10.97#ibcon#about to read 3, iclass 13, count 2 2006.197.07:46:10.99#ibcon#read 3, iclass 13, count 2 2006.197.07:46:10.99#ibcon#about to read 4, iclass 13, count 2 2006.197.07:46:10.99#ibcon#read 4, iclass 13, count 2 2006.197.07:46:10.99#ibcon#about to read 5, iclass 13, count 2 2006.197.07:46:10.99#ibcon#read 5, iclass 13, count 2 2006.197.07:46:10.99#ibcon#about to read 6, iclass 13, count 2 2006.197.07:46:10.99#ibcon#read 6, iclass 13, count 2 2006.197.07:46:10.99#ibcon#end of sib2, iclass 13, count 2 2006.197.07:46:10.99#ibcon#*mode == 0, iclass 13, count 2 2006.197.07:46:10.99#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.197.07:46:10.99#ibcon#[27=AT03-04\r\n] 2006.197.07:46:10.99#ibcon#*before write, iclass 13, count 2 2006.197.07:46:10.99#ibcon#enter sib2, iclass 13, count 2 2006.197.07:46:10.99#ibcon#flushed, iclass 13, count 2 2006.197.07:46:10.99#ibcon#about to write, iclass 13, count 2 2006.197.07:46:10.99#ibcon#wrote, iclass 13, count 2 2006.197.07:46:10.99#ibcon#about to read 3, iclass 13, count 2 2006.197.07:46:11.02#ibcon#read 3, iclass 13, count 2 2006.197.07:46:11.02#ibcon#about to read 4, iclass 13, count 2 2006.197.07:46:11.02#ibcon#read 4, iclass 13, count 2 2006.197.07:46:11.02#ibcon#about to read 5, iclass 13, count 2 2006.197.07:46:11.02#ibcon#read 5, iclass 13, count 2 2006.197.07:46:11.02#ibcon#about to read 6, iclass 13, count 2 2006.197.07:46:11.02#ibcon#read 6, iclass 13, count 2 2006.197.07:46:11.02#ibcon#end of sib2, iclass 13, count 2 2006.197.07:46:11.02#ibcon#*after write, iclass 13, count 2 2006.197.07:46:11.02#ibcon#*before return 0, iclass 13, count 2 2006.197.07:46:11.02#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.197.07:46:11.02#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.197.07:46:11.02#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.197.07:46:11.02#ibcon#ireg 7 cls_cnt 0 2006.197.07:46:11.02#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.197.07:46:11.14#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.197.07:46:11.14#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.197.07:46:11.14#ibcon#enter wrdev, iclass 13, count 0 2006.197.07:46:11.14#ibcon#first serial, iclass 13, count 0 2006.197.07:46:11.14#ibcon#enter sib2, iclass 13, count 0 2006.197.07:46:11.14#ibcon#flushed, iclass 13, count 0 2006.197.07:46:11.14#ibcon#about to write, iclass 13, count 0 2006.197.07:46:11.14#ibcon#wrote, iclass 13, count 0 2006.197.07:46:11.14#ibcon#about to read 3, iclass 13, count 0 2006.197.07:46:11.16#ibcon#read 3, iclass 13, count 0 2006.197.07:46:11.16#ibcon#about to read 4, iclass 13, count 0 2006.197.07:46:11.16#ibcon#read 4, iclass 13, count 0 2006.197.07:46:11.16#ibcon#about to read 5, iclass 13, count 0 2006.197.07:46:11.16#ibcon#read 5, iclass 13, count 0 2006.197.07:46:11.16#ibcon#about to read 6, iclass 13, count 0 2006.197.07:46:11.16#ibcon#read 6, iclass 13, count 0 2006.197.07:46:11.16#ibcon#end of sib2, iclass 13, count 0 2006.197.07:46:11.16#ibcon#*mode == 0, iclass 13, count 0 2006.197.07:46:11.16#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.197.07:46:11.16#ibcon#[27=USB\r\n] 2006.197.07:46:11.16#ibcon#*before write, iclass 13, count 0 2006.197.07:46:11.16#ibcon#enter sib2, iclass 13, count 0 2006.197.07:46:11.16#ibcon#flushed, iclass 13, count 0 2006.197.07:46:11.16#ibcon#about to write, iclass 13, count 0 2006.197.07:46:11.16#ibcon#wrote, iclass 13, count 0 2006.197.07:46:11.16#ibcon#about to read 3, iclass 13, count 0 2006.197.07:46:11.19#ibcon#read 3, iclass 13, count 0 2006.197.07:46:11.19#ibcon#about to read 4, iclass 13, count 0 2006.197.07:46:11.19#ibcon#read 4, iclass 13, count 0 2006.197.07:46:11.19#ibcon#about to read 5, iclass 13, count 0 2006.197.07:46:11.19#ibcon#read 5, iclass 13, count 0 2006.197.07:46:11.19#ibcon#about to read 6, iclass 13, count 0 2006.197.07:46:11.19#ibcon#read 6, iclass 13, count 0 2006.197.07:46:11.19#ibcon#end of sib2, iclass 13, count 0 2006.197.07:46:11.19#ibcon#*after write, iclass 13, count 0 2006.197.07:46:11.19#ibcon#*before return 0, iclass 13, count 0 2006.197.07:46:11.19#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.197.07:46:11.19#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.197.07:46:11.19#ibcon#about to clear, iclass 13 cls_cnt 0 2006.197.07:46:11.19#ibcon#cleared, iclass 13 cls_cnt 0 2006.197.07:46:11.19$vc4f8/vblo=4,712.99 2006.197.07:46:11.19#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.197.07:46:11.19#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.197.07:46:11.19#ibcon#ireg 17 cls_cnt 0 2006.197.07:46:11.19#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.197.07:46:11.19#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.197.07:46:11.19#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.197.07:46:11.19#ibcon#enter wrdev, iclass 15, count 0 2006.197.07:46:11.19#ibcon#first serial, iclass 15, count 0 2006.197.07:46:11.19#ibcon#enter sib2, iclass 15, count 0 2006.197.07:46:11.19#ibcon#flushed, iclass 15, count 0 2006.197.07:46:11.19#ibcon#about to write, iclass 15, count 0 2006.197.07:46:11.19#ibcon#wrote, iclass 15, count 0 2006.197.07:46:11.19#ibcon#about to read 3, iclass 15, count 0 2006.197.07:46:11.21#ibcon#read 3, iclass 15, count 0 2006.197.07:46:11.21#ibcon#about to read 4, iclass 15, count 0 2006.197.07:46:11.21#ibcon#read 4, iclass 15, count 0 2006.197.07:46:11.21#ibcon#about to read 5, iclass 15, count 0 2006.197.07:46:11.21#ibcon#read 5, iclass 15, count 0 2006.197.07:46:11.21#ibcon#about to read 6, iclass 15, count 0 2006.197.07:46:11.21#ibcon#read 6, iclass 15, count 0 2006.197.07:46:11.21#ibcon#end of sib2, iclass 15, count 0 2006.197.07:46:11.21#ibcon#*mode == 0, iclass 15, count 0 2006.197.07:46:11.21#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.197.07:46:11.21#ibcon#[28=FRQ=04,712.99\r\n] 2006.197.07:46:11.21#ibcon#*before write, iclass 15, count 0 2006.197.07:46:11.21#ibcon#enter sib2, iclass 15, count 0 2006.197.07:46:11.21#ibcon#flushed, iclass 15, count 0 2006.197.07:46:11.21#ibcon#about to write, iclass 15, count 0 2006.197.07:46:11.21#ibcon#wrote, iclass 15, count 0 2006.197.07:46:11.21#ibcon#about to read 3, iclass 15, count 0 2006.197.07:46:11.25#ibcon#read 3, iclass 15, count 0 2006.197.07:46:11.25#ibcon#about to read 4, iclass 15, count 0 2006.197.07:46:11.25#ibcon#read 4, iclass 15, count 0 2006.197.07:46:11.25#ibcon#about to read 5, iclass 15, count 0 2006.197.07:46:11.25#ibcon#read 5, iclass 15, count 0 2006.197.07:46:11.25#ibcon#about to read 6, iclass 15, count 0 2006.197.07:46:11.25#ibcon#read 6, iclass 15, count 0 2006.197.07:46:11.25#ibcon#end of sib2, iclass 15, count 0 2006.197.07:46:11.25#ibcon#*after write, iclass 15, count 0 2006.197.07:46:11.25#ibcon#*before return 0, iclass 15, count 0 2006.197.07:46:11.25#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.197.07:46:11.25#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.197.07:46:11.25#ibcon#about to clear, iclass 15 cls_cnt 0 2006.197.07:46:11.25#ibcon#cleared, iclass 15 cls_cnt 0 2006.197.07:46:11.25$vc4f8/vb=4,4 2006.197.07:46:11.25#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.197.07:46:11.25#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.197.07:46:11.25#ibcon#ireg 11 cls_cnt 2 2006.197.07:46:11.25#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.197.07:46:11.31#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.197.07:46:11.31#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.197.07:46:11.31#ibcon#enter wrdev, iclass 17, count 2 2006.197.07:46:11.31#ibcon#first serial, iclass 17, count 2 2006.197.07:46:11.31#ibcon#enter sib2, iclass 17, count 2 2006.197.07:46:11.31#ibcon#flushed, iclass 17, count 2 2006.197.07:46:11.31#ibcon#about to write, iclass 17, count 2 2006.197.07:46:11.31#ibcon#wrote, iclass 17, count 2 2006.197.07:46:11.31#ibcon#about to read 3, iclass 17, count 2 2006.197.07:46:11.33#ibcon#read 3, iclass 17, count 2 2006.197.07:46:11.33#ibcon#about to read 4, iclass 17, count 2 2006.197.07:46:11.33#ibcon#read 4, iclass 17, count 2 2006.197.07:46:11.33#ibcon#about to read 5, iclass 17, count 2 2006.197.07:46:11.33#ibcon#read 5, iclass 17, count 2 2006.197.07:46:11.33#ibcon#about to read 6, iclass 17, count 2 2006.197.07:46:11.33#ibcon#read 6, iclass 17, count 2 2006.197.07:46:11.33#ibcon#end of sib2, iclass 17, count 2 2006.197.07:46:11.33#ibcon#*mode == 0, iclass 17, count 2 2006.197.07:46:11.33#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.197.07:46:11.33#ibcon#[27=AT04-04\r\n] 2006.197.07:46:11.33#ibcon#*before write, iclass 17, count 2 2006.197.07:46:11.33#ibcon#enter sib2, iclass 17, count 2 2006.197.07:46:11.33#ibcon#flushed, iclass 17, count 2 2006.197.07:46:11.33#ibcon#about to write, iclass 17, count 2 2006.197.07:46:11.33#ibcon#wrote, iclass 17, count 2 2006.197.07:46:11.33#ibcon#about to read 3, iclass 17, count 2 2006.197.07:46:11.36#ibcon#read 3, iclass 17, count 2 2006.197.07:46:11.36#ibcon#about to read 4, iclass 17, count 2 2006.197.07:46:11.36#ibcon#read 4, iclass 17, count 2 2006.197.07:46:11.36#ibcon#about to read 5, iclass 17, count 2 2006.197.07:46:11.36#ibcon#read 5, iclass 17, count 2 2006.197.07:46:11.36#ibcon#about to read 6, iclass 17, count 2 2006.197.07:46:11.36#ibcon#read 6, iclass 17, count 2 2006.197.07:46:11.36#ibcon#end of sib2, iclass 17, count 2 2006.197.07:46:11.36#ibcon#*after write, iclass 17, count 2 2006.197.07:46:11.36#ibcon#*before return 0, iclass 17, count 2 2006.197.07:46:11.36#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.197.07:46:11.36#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.197.07:46:11.36#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.197.07:46:11.36#ibcon#ireg 7 cls_cnt 0 2006.197.07:46:11.36#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.197.07:46:11.48#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.197.07:46:11.48#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.197.07:46:11.48#ibcon#enter wrdev, iclass 17, count 0 2006.197.07:46:11.48#ibcon#first serial, iclass 17, count 0 2006.197.07:46:11.48#ibcon#enter sib2, iclass 17, count 0 2006.197.07:46:11.48#ibcon#flushed, iclass 17, count 0 2006.197.07:46:11.48#ibcon#about to write, iclass 17, count 0 2006.197.07:46:11.48#ibcon#wrote, iclass 17, count 0 2006.197.07:46:11.48#ibcon#about to read 3, iclass 17, count 0 2006.197.07:46:11.50#ibcon#read 3, iclass 17, count 0 2006.197.07:46:11.50#ibcon#about to read 4, iclass 17, count 0 2006.197.07:46:11.50#ibcon#read 4, iclass 17, count 0 2006.197.07:46:11.50#ibcon#about to read 5, iclass 17, count 0 2006.197.07:46:11.50#ibcon#read 5, iclass 17, count 0 2006.197.07:46:11.50#ibcon#about to read 6, iclass 17, count 0 2006.197.07:46:11.50#ibcon#read 6, iclass 17, count 0 2006.197.07:46:11.50#ibcon#end of sib2, iclass 17, count 0 2006.197.07:46:11.50#ibcon#*mode == 0, iclass 17, count 0 2006.197.07:46:11.50#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.197.07:46:11.50#ibcon#[27=USB\r\n] 2006.197.07:46:11.50#ibcon#*before write, iclass 17, count 0 2006.197.07:46:11.50#ibcon#enter sib2, iclass 17, count 0 2006.197.07:46:11.50#ibcon#flushed, iclass 17, count 0 2006.197.07:46:11.50#ibcon#about to write, iclass 17, count 0 2006.197.07:46:11.50#ibcon#wrote, iclass 17, count 0 2006.197.07:46:11.50#ibcon#about to read 3, iclass 17, count 0 2006.197.07:46:11.53#ibcon#read 3, iclass 17, count 0 2006.197.07:46:11.53#ibcon#about to read 4, iclass 17, count 0 2006.197.07:46:11.53#ibcon#read 4, iclass 17, count 0 2006.197.07:46:11.53#ibcon#about to read 5, iclass 17, count 0 2006.197.07:46:11.53#ibcon#read 5, iclass 17, count 0 2006.197.07:46:11.53#ibcon#about to read 6, iclass 17, count 0 2006.197.07:46:11.53#ibcon#read 6, iclass 17, count 0 2006.197.07:46:11.53#ibcon#end of sib2, iclass 17, count 0 2006.197.07:46:11.53#ibcon#*after write, iclass 17, count 0 2006.197.07:46:11.53#ibcon#*before return 0, iclass 17, count 0 2006.197.07:46:11.53#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.197.07:46:11.53#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.197.07:46:11.53#ibcon#about to clear, iclass 17 cls_cnt 0 2006.197.07:46:11.53#ibcon#cleared, iclass 17 cls_cnt 0 2006.197.07:46:11.53$vc4f8/vblo=5,744.99 2006.197.07:46:11.53#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.197.07:46:11.53#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.197.07:46:11.53#ibcon#ireg 17 cls_cnt 0 2006.197.07:46:11.53#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.197.07:46:11.53#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.197.07:46:11.53#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.197.07:46:11.53#ibcon#enter wrdev, iclass 19, count 0 2006.197.07:46:11.53#ibcon#first serial, iclass 19, count 0 2006.197.07:46:11.53#ibcon#enter sib2, iclass 19, count 0 2006.197.07:46:11.53#ibcon#flushed, iclass 19, count 0 2006.197.07:46:11.53#ibcon#about to write, iclass 19, count 0 2006.197.07:46:11.53#ibcon#wrote, iclass 19, count 0 2006.197.07:46:11.53#ibcon#about to read 3, iclass 19, count 0 2006.197.07:46:11.55#ibcon#read 3, iclass 19, count 0 2006.197.07:46:11.55#ibcon#about to read 4, iclass 19, count 0 2006.197.07:46:11.55#ibcon#read 4, iclass 19, count 0 2006.197.07:46:11.55#ibcon#about to read 5, iclass 19, count 0 2006.197.07:46:11.55#ibcon#read 5, iclass 19, count 0 2006.197.07:46:11.55#ibcon#about to read 6, iclass 19, count 0 2006.197.07:46:11.55#ibcon#read 6, iclass 19, count 0 2006.197.07:46:11.55#ibcon#end of sib2, iclass 19, count 0 2006.197.07:46:11.55#ibcon#*mode == 0, iclass 19, count 0 2006.197.07:46:11.55#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.197.07:46:11.55#ibcon#[28=FRQ=05,744.99\r\n] 2006.197.07:46:11.55#ibcon#*before write, iclass 19, count 0 2006.197.07:46:11.55#ibcon#enter sib2, iclass 19, count 0 2006.197.07:46:11.55#ibcon#flushed, iclass 19, count 0 2006.197.07:46:11.55#ibcon#about to write, iclass 19, count 0 2006.197.07:46:11.55#ibcon#wrote, iclass 19, count 0 2006.197.07:46:11.55#ibcon#about to read 3, iclass 19, count 0 2006.197.07:46:11.59#ibcon#read 3, iclass 19, count 0 2006.197.07:46:11.59#ibcon#about to read 4, iclass 19, count 0 2006.197.07:46:11.59#ibcon#read 4, iclass 19, count 0 2006.197.07:46:11.59#ibcon#about to read 5, iclass 19, count 0 2006.197.07:46:11.59#ibcon#read 5, iclass 19, count 0 2006.197.07:46:11.59#ibcon#about to read 6, iclass 19, count 0 2006.197.07:46:11.59#ibcon#read 6, iclass 19, count 0 2006.197.07:46:11.59#ibcon#end of sib2, iclass 19, count 0 2006.197.07:46:11.59#ibcon#*after write, iclass 19, count 0 2006.197.07:46:11.59#ibcon#*before return 0, iclass 19, count 0 2006.197.07:46:11.59#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.197.07:46:11.59#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.197.07:46:11.59#ibcon#about to clear, iclass 19 cls_cnt 0 2006.197.07:46:11.59#ibcon#cleared, iclass 19 cls_cnt 0 2006.197.07:46:11.59$vc4f8/vb=5,4 2006.197.07:46:11.59#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.197.07:46:11.59#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.197.07:46:11.59#ibcon#ireg 11 cls_cnt 2 2006.197.07:46:11.59#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.197.07:46:11.65#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.197.07:46:11.65#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.197.07:46:11.65#ibcon#enter wrdev, iclass 21, count 2 2006.197.07:46:11.65#ibcon#first serial, iclass 21, count 2 2006.197.07:46:11.65#ibcon#enter sib2, iclass 21, count 2 2006.197.07:46:11.65#ibcon#flushed, iclass 21, count 2 2006.197.07:46:11.65#ibcon#about to write, iclass 21, count 2 2006.197.07:46:11.65#ibcon#wrote, iclass 21, count 2 2006.197.07:46:11.65#ibcon#about to read 3, iclass 21, count 2 2006.197.07:46:11.67#ibcon#read 3, iclass 21, count 2 2006.197.07:46:11.67#ibcon#about to read 4, iclass 21, count 2 2006.197.07:46:11.67#ibcon#read 4, iclass 21, count 2 2006.197.07:46:11.67#ibcon#about to read 5, iclass 21, count 2 2006.197.07:46:11.67#ibcon#read 5, iclass 21, count 2 2006.197.07:46:11.67#ibcon#about to read 6, iclass 21, count 2 2006.197.07:46:11.67#ibcon#read 6, iclass 21, count 2 2006.197.07:46:11.67#ibcon#end of sib2, iclass 21, count 2 2006.197.07:46:11.67#ibcon#*mode == 0, iclass 21, count 2 2006.197.07:46:11.67#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.197.07:46:11.67#ibcon#[27=AT05-04\r\n] 2006.197.07:46:11.67#ibcon#*before write, iclass 21, count 2 2006.197.07:46:11.67#ibcon#enter sib2, iclass 21, count 2 2006.197.07:46:11.67#ibcon#flushed, iclass 21, count 2 2006.197.07:46:11.67#ibcon#about to write, iclass 21, count 2 2006.197.07:46:11.67#ibcon#wrote, iclass 21, count 2 2006.197.07:46:11.67#ibcon#about to read 3, iclass 21, count 2 2006.197.07:46:11.70#ibcon#read 3, iclass 21, count 2 2006.197.07:46:11.70#ibcon#about to read 4, iclass 21, count 2 2006.197.07:46:11.70#ibcon#read 4, iclass 21, count 2 2006.197.07:46:11.70#ibcon#about to read 5, iclass 21, count 2 2006.197.07:46:11.70#ibcon#read 5, iclass 21, count 2 2006.197.07:46:11.70#ibcon#about to read 6, iclass 21, count 2 2006.197.07:46:11.70#ibcon#read 6, iclass 21, count 2 2006.197.07:46:11.70#ibcon#end of sib2, iclass 21, count 2 2006.197.07:46:11.70#ibcon#*after write, iclass 21, count 2 2006.197.07:46:11.70#ibcon#*before return 0, iclass 21, count 2 2006.197.07:46:11.70#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.197.07:46:11.70#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.197.07:46:11.70#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.197.07:46:11.70#ibcon#ireg 7 cls_cnt 0 2006.197.07:46:11.70#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.197.07:46:11.82#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.197.07:46:11.82#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.197.07:46:11.82#ibcon#enter wrdev, iclass 21, count 0 2006.197.07:46:11.82#ibcon#first serial, iclass 21, count 0 2006.197.07:46:11.82#ibcon#enter sib2, iclass 21, count 0 2006.197.07:46:11.82#ibcon#flushed, iclass 21, count 0 2006.197.07:46:11.82#ibcon#about to write, iclass 21, count 0 2006.197.07:46:11.82#ibcon#wrote, iclass 21, count 0 2006.197.07:46:11.82#ibcon#about to read 3, iclass 21, count 0 2006.197.07:46:11.84#ibcon#read 3, iclass 21, count 0 2006.197.07:46:11.84#ibcon#about to read 4, iclass 21, count 0 2006.197.07:46:11.84#ibcon#read 4, iclass 21, count 0 2006.197.07:46:11.84#ibcon#about to read 5, iclass 21, count 0 2006.197.07:46:11.84#ibcon#read 5, iclass 21, count 0 2006.197.07:46:11.84#ibcon#about to read 6, iclass 21, count 0 2006.197.07:46:11.84#ibcon#read 6, iclass 21, count 0 2006.197.07:46:11.84#ibcon#end of sib2, iclass 21, count 0 2006.197.07:46:11.84#ibcon#*mode == 0, iclass 21, count 0 2006.197.07:46:11.84#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.197.07:46:11.84#ibcon#[27=USB\r\n] 2006.197.07:46:11.84#ibcon#*before write, iclass 21, count 0 2006.197.07:46:11.84#ibcon#enter sib2, iclass 21, count 0 2006.197.07:46:11.84#ibcon#flushed, iclass 21, count 0 2006.197.07:46:11.84#ibcon#about to write, iclass 21, count 0 2006.197.07:46:11.84#ibcon#wrote, iclass 21, count 0 2006.197.07:46:11.84#ibcon#about to read 3, iclass 21, count 0 2006.197.07:46:11.87#ibcon#read 3, iclass 21, count 0 2006.197.07:46:11.87#ibcon#about to read 4, iclass 21, count 0 2006.197.07:46:11.87#ibcon#read 4, iclass 21, count 0 2006.197.07:46:11.87#ibcon#about to read 5, iclass 21, count 0 2006.197.07:46:11.87#ibcon#read 5, iclass 21, count 0 2006.197.07:46:11.87#ibcon#about to read 6, iclass 21, count 0 2006.197.07:46:11.87#ibcon#read 6, iclass 21, count 0 2006.197.07:46:11.87#ibcon#end of sib2, iclass 21, count 0 2006.197.07:46:11.87#ibcon#*after write, iclass 21, count 0 2006.197.07:46:11.87#ibcon#*before return 0, iclass 21, count 0 2006.197.07:46:11.87#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.197.07:46:11.87#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.197.07:46:11.87#ibcon#about to clear, iclass 21 cls_cnt 0 2006.197.07:46:11.87#ibcon#cleared, iclass 21 cls_cnt 0 2006.197.07:46:11.87$vc4f8/vblo=6,752.99 2006.197.07:46:11.87#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.197.07:46:11.87#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.197.07:46:11.87#ibcon#ireg 17 cls_cnt 0 2006.197.07:46:11.87#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.197.07:46:11.87#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.197.07:46:11.87#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.197.07:46:11.87#ibcon#enter wrdev, iclass 23, count 0 2006.197.07:46:11.87#ibcon#first serial, iclass 23, count 0 2006.197.07:46:11.87#ibcon#enter sib2, iclass 23, count 0 2006.197.07:46:11.87#ibcon#flushed, iclass 23, count 0 2006.197.07:46:11.87#ibcon#about to write, iclass 23, count 0 2006.197.07:46:11.87#ibcon#wrote, iclass 23, count 0 2006.197.07:46:11.87#ibcon#about to read 3, iclass 23, count 0 2006.197.07:46:11.89#ibcon#read 3, iclass 23, count 0 2006.197.07:46:11.89#ibcon#about to read 4, iclass 23, count 0 2006.197.07:46:11.89#ibcon#read 4, iclass 23, count 0 2006.197.07:46:11.89#ibcon#about to read 5, iclass 23, count 0 2006.197.07:46:11.89#ibcon#read 5, iclass 23, count 0 2006.197.07:46:11.89#ibcon#about to read 6, iclass 23, count 0 2006.197.07:46:11.89#ibcon#read 6, iclass 23, count 0 2006.197.07:46:11.89#ibcon#end of sib2, iclass 23, count 0 2006.197.07:46:11.89#ibcon#*mode == 0, iclass 23, count 0 2006.197.07:46:11.89#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.197.07:46:11.89#ibcon#[28=FRQ=06,752.99\r\n] 2006.197.07:46:11.89#ibcon#*before write, iclass 23, count 0 2006.197.07:46:11.89#ibcon#enter sib2, iclass 23, count 0 2006.197.07:46:11.89#ibcon#flushed, iclass 23, count 0 2006.197.07:46:11.89#ibcon#about to write, iclass 23, count 0 2006.197.07:46:11.89#ibcon#wrote, iclass 23, count 0 2006.197.07:46:11.89#ibcon#about to read 3, iclass 23, count 0 2006.197.07:46:11.93#ibcon#read 3, iclass 23, count 0 2006.197.07:46:11.93#ibcon#about to read 4, iclass 23, count 0 2006.197.07:46:11.93#ibcon#read 4, iclass 23, count 0 2006.197.07:46:11.93#ibcon#about to read 5, iclass 23, count 0 2006.197.07:46:11.93#ibcon#read 5, iclass 23, count 0 2006.197.07:46:11.93#ibcon#about to read 6, iclass 23, count 0 2006.197.07:46:11.93#ibcon#read 6, iclass 23, count 0 2006.197.07:46:11.93#ibcon#end of sib2, iclass 23, count 0 2006.197.07:46:11.93#ibcon#*after write, iclass 23, count 0 2006.197.07:46:11.93#ibcon#*before return 0, iclass 23, count 0 2006.197.07:46:11.93#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.197.07:46:11.93#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.197.07:46:11.93#ibcon#about to clear, iclass 23 cls_cnt 0 2006.197.07:46:11.93#ibcon#cleared, iclass 23 cls_cnt 0 2006.197.07:46:11.93$vc4f8/vb=6,4 2006.197.07:46:11.93#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.197.07:46:11.93#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.197.07:46:11.93#ibcon#ireg 11 cls_cnt 2 2006.197.07:46:11.93#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.197.07:46:11.99#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.197.07:46:11.99#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.197.07:46:11.99#ibcon#enter wrdev, iclass 25, count 2 2006.197.07:46:11.99#ibcon#first serial, iclass 25, count 2 2006.197.07:46:11.99#ibcon#enter sib2, iclass 25, count 2 2006.197.07:46:11.99#ibcon#flushed, iclass 25, count 2 2006.197.07:46:11.99#ibcon#about to write, iclass 25, count 2 2006.197.07:46:11.99#ibcon#wrote, iclass 25, count 2 2006.197.07:46:11.99#ibcon#about to read 3, iclass 25, count 2 2006.197.07:46:12.01#ibcon#read 3, iclass 25, count 2 2006.197.07:46:12.01#ibcon#about to read 4, iclass 25, count 2 2006.197.07:46:12.01#ibcon#read 4, iclass 25, count 2 2006.197.07:46:12.01#ibcon#about to read 5, iclass 25, count 2 2006.197.07:46:12.01#ibcon#read 5, iclass 25, count 2 2006.197.07:46:12.01#ibcon#about to read 6, iclass 25, count 2 2006.197.07:46:12.01#ibcon#read 6, iclass 25, count 2 2006.197.07:46:12.01#ibcon#end of sib2, iclass 25, count 2 2006.197.07:46:12.01#ibcon#*mode == 0, iclass 25, count 2 2006.197.07:46:12.01#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.197.07:46:12.01#ibcon#[27=AT06-04\r\n] 2006.197.07:46:12.01#ibcon#*before write, iclass 25, count 2 2006.197.07:46:12.01#ibcon#enter sib2, iclass 25, count 2 2006.197.07:46:12.01#ibcon#flushed, iclass 25, count 2 2006.197.07:46:12.01#ibcon#about to write, iclass 25, count 2 2006.197.07:46:12.01#ibcon#wrote, iclass 25, count 2 2006.197.07:46:12.01#ibcon#about to read 3, iclass 25, count 2 2006.197.07:46:12.04#ibcon#read 3, iclass 25, count 2 2006.197.07:46:12.04#ibcon#about to read 4, iclass 25, count 2 2006.197.07:46:12.04#ibcon#read 4, iclass 25, count 2 2006.197.07:46:12.04#ibcon#about to read 5, iclass 25, count 2 2006.197.07:46:12.04#ibcon#read 5, iclass 25, count 2 2006.197.07:46:12.04#ibcon#about to read 6, iclass 25, count 2 2006.197.07:46:12.04#ibcon#read 6, iclass 25, count 2 2006.197.07:46:12.04#ibcon#end of sib2, iclass 25, count 2 2006.197.07:46:12.04#ibcon#*after write, iclass 25, count 2 2006.197.07:46:12.04#ibcon#*before return 0, iclass 25, count 2 2006.197.07:46:12.04#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.197.07:46:12.04#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.197.07:46:12.04#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.197.07:46:12.04#ibcon#ireg 7 cls_cnt 0 2006.197.07:46:12.04#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.197.07:46:12.16#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.197.07:46:12.16#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.197.07:46:12.16#ibcon#enter wrdev, iclass 25, count 0 2006.197.07:46:12.16#ibcon#first serial, iclass 25, count 0 2006.197.07:46:12.16#ibcon#enter sib2, iclass 25, count 0 2006.197.07:46:12.16#ibcon#flushed, iclass 25, count 0 2006.197.07:46:12.16#ibcon#about to write, iclass 25, count 0 2006.197.07:46:12.16#ibcon#wrote, iclass 25, count 0 2006.197.07:46:12.16#ibcon#about to read 3, iclass 25, count 0 2006.197.07:46:12.18#ibcon#read 3, iclass 25, count 0 2006.197.07:46:12.18#ibcon#about to read 4, iclass 25, count 0 2006.197.07:46:12.18#ibcon#read 4, iclass 25, count 0 2006.197.07:46:12.18#ibcon#about to read 5, iclass 25, count 0 2006.197.07:46:12.18#ibcon#read 5, iclass 25, count 0 2006.197.07:46:12.18#ibcon#about to read 6, iclass 25, count 0 2006.197.07:46:12.18#ibcon#read 6, iclass 25, count 0 2006.197.07:46:12.18#ibcon#end of sib2, iclass 25, count 0 2006.197.07:46:12.18#ibcon#*mode == 0, iclass 25, count 0 2006.197.07:46:12.18#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.197.07:46:12.18#ibcon#[27=USB\r\n] 2006.197.07:46:12.18#ibcon#*before write, iclass 25, count 0 2006.197.07:46:12.18#ibcon#enter sib2, iclass 25, count 0 2006.197.07:46:12.18#ibcon#flushed, iclass 25, count 0 2006.197.07:46:12.18#ibcon#about to write, iclass 25, count 0 2006.197.07:46:12.18#ibcon#wrote, iclass 25, count 0 2006.197.07:46:12.18#ibcon#about to read 3, iclass 25, count 0 2006.197.07:46:12.21#ibcon#read 3, iclass 25, count 0 2006.197.07:46:12.21#ibcon#about to read 4, iclass 25, count 0 2006.197.07:46:12.21#ibcon#read 4, iclass 25, count 0 2006.197.07:46:12.21#ibcon#about to read 5, iclass 25, count 0 2006.197.07:46:12.21#ibcon#read 5, iclass 25, count 0 2006.197.07:46:12.21#ibcon#about to read 6, iclass 25, count 0 2006.197.07:46:12.21#ibcon#read 6, iclass 25, count 0 2006.197.07:46:12.21#ibcon#end of sib2, iclass 25, count 0 2006.197.07:46:12.21#ibcon#*after write, iclass 25, count 0 2006.197.07:46:12.21#ibcon#*before return 0, iclass 25, count 0 2006.197.07:46:12.21#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.197.07:46:12.21#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.197.07:46:12.21#ibcon#about to clear, iclass 25 cls_cnt 0 2006.197.07:46:12.21#ibcon#cleared, iclass 25 cls_cnt 0 2006.197.07:46:12.21$vc4f8/vabw=wide 2006.197.07:46:12.21#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.197.07:46:12.21#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.197.07:46:12.21#ibcon#ireg 8 cls_cnt 0 2006.197.07:46:12.21#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.197.07:46:12.21#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.197.07:46:12.21#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.197.07:46:12.21#ibcon#enter wrdev, iclass 27, count 0 2006.197.07:46:12.21#ibcon#first serial, iclass 27, count 0 2006.197.07:46:12.21#ibcon#enter sib2, iclass 27, count 0 2006.197.07:46:12.21#ibcon#flushed, iclass 27, count 0 2006.197.07:46:12.21#ibcon#about to write, iclass 27, count 0 2006.197.07:46:12.21#ibcon#wrote, iclass 27, count 0 2006.197.07:46:12.21#ibcon#about to read 3, iclass 27, count 0 2006.197.07:46:12.23#ibcon#read 3, iclass 27, count 0 2006.197.07:46:12.23#ibcon#about to read 4, iclass 27, count 0 2006.197.07:46:12.23#ibcon#read 4, iclass 27, count 0 2006.197.07:46:12.23#ibcon#about to read 5, iclass 27, count 0 2006.197.07:46:12.23#ibcon#read 5, iclass 27, count 0 2006.197.07:46:12.23#ibcon#about to read 6, iclass 27, count 0 2006.197.07:46:12.23#ibcon#read 6, iclass 27, count 0 2006.197.07:46:12.23#ibcon#end of sib2, iclass 27, count 0 2006.197.07:46:12.23#ibcon#*mode == 0, iclass 27, count 0 2006.197.07:46:12.23#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.197.07:46:12.23#ibcon#[25=BW32\r\n] 2006.197.07:46:12.23#ibcon#*before write, iclass 27, count 0 2006.197.07:46:12.23#ibcon#enter sib2, iclass 27, count 0 2006.197.07:46:12.23#ibcon#flushed, iclass 27, count 0 2006.197.07:46:12.23#ibcon#about to write, iclass 27, count 0 2006.197.07:46:12.23#ibcon#wrote, iclass 27, count 0 2006.197.07:46:12.23#ibcon#about to read 3, iclass 27, count 0 2006.197.07:46:12.26#ibcon#read 3, iclass 27, count 0 2006.197.07:46:12.26#ibcon#about to read 4, iclass 27, count 0 2006.197.07:46:12.26#ibcon#read 4, iclass 27, count 0 2006.197.07:46:12.26#ibcon#about to read 5, iclass 27, count 0 2006.197.07:46:12.26#ibcon#read 5, iclass 27, count 0 2006.197.07:46:12.26#ibcon#about to read 6, iclass 27, count 0 2006.197.07:46:12.26#ibcon#read 6, iclass 27, count 0 2006.197.07:46:12.26#ibcon#end of sib2, iclass 27, count 0 2006.197.07:46:12.26#ibcon#*after write, iclass 27, count 0 2006.197.07:46:12.26#ibcon#*before return 0, iclass 27, count 0 2006.197.07:46:12.26#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.197.07:46:12.26#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.197.07:46:12.26#ibcon#about to clear, iclass 27 cls_cnt 0 2006.197.07:46:12.26#ibcon#cleared, iclass 27 cls_cnt 0 2006.197.07:46:12.26$vc4f8/vbbw=wide 2006.197.07:46:12.26#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.197.07:46:12.26#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.197.07:46:12.26#ibcon#ireg 8 cls_cnt 0 2006.197.07:46:12.26#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.197.07:46:12.33#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.197.07:46:12.33#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.197.07:46:12.33#ibcon#enter wrdev, iclass 29, count 0 2006.197.07:46:12.33#ibcon#first serial, iclass 29, count 0 2006.197.07:46:12.33#ibcon#enter sib2, iclass 29, count 0 2006.197.07:46:12.33#ibcon#flushed, iclass 29, count 0 2006.197.07:46:12.33#ibcon#about to write, iclass 29, count 0 2006.197.07:46:12.33#ibcon#wrote, iclass 29, count 0 2006.197.07:46:12.33#ibcon#about to read 3, iclass 29, count 0 2006.197.07:46:12.35#ibcon#read 3, iclass 29, count 0 2006.197.07:46:12.35#ibcon#about to read 4, iclass 29, count 0 2006.197.07:46:12.35#ibcon#read 4, iclass 29, count 0 2006.197.07:46:12.35#ibcon#about to read 5, iclass 29, count 0 2006.197.07:46:12.35#ibcon#read 5, iclass 29, count 0 2006.197.07:46:12.35#ibcon#about to read 6, iclass 29, count 0 2006.197.07:46:12.35#ibcon#read 6, iclass 29, count 0 2006.197.07:46:12.35#ibcon#end of sib2, iclass 29, count 0 2006.197.07:46:12.35#ibcon#*mode == 0, iclass 29, count 0 2006.197.07:46:12.35#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.197.07:46:12.35#ibcon#[27=BW32\r\n] 2006.197.07:46:12.35#ibcon#*before write, iclass 29, count 0 2006.197.07:46:12.35#ibcon#enter sib2, iclass 29, count 0 2006.197.07:46:12.35#ibcon#flushed, iclass 29, count 0 2006.197.07:46:12.35#ibcon#about to write, iclass 29, count 0 2006.197.07:46:12.35#ibcon#wrote, iclass 29, count 0 2006.197.07:46:12.35#ibcon#about to read 3, iclass 29, count 0 2006.197.07:46:12.38#ibcon#read 3, iclass 29, count 0 2006.197.07:46:12.38#ibcon#about to read 4, iclass 29, count 0 2006.197.07:46:12.38#ibcon#read 4, iclass 29, count 0 2006.197.07:46:12.38#ibcon#about to read 5, iclass 29, count 0 2006.197.07:46:12.38#ibcon#read 5, iclass 29, count 0 2006.197.07:46:12.38#ibcon#about to read 6, iclass 29, count 0 2006.197.07:46:12.38#ibcon#read 6, iclass 29, count 0 2006.197.07:46:12.38#ibcon#end of sib2, iclass 29, count 0 2006.197.07:46:12.38#ibcon#*after write, iclass 29, count 0 2006.197.07:46:12.38#ibcon#*before return 0, iclass 29, count 0 2006.197.07:46:12.38#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.197.07:46:12.38#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.197.07:46:12.38#ibcon#about to clear, iclass 29 cls_cnt 0 2006.197.07:46:12.38#ibcon#cleared, iclass 29 cls_cnt 0 2006.197.07:46:12.38$4f8m12a/ifd4f 2006.197.07:46:12.38$ifd4f/lo= 2006.197.07:46:12.38$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.197.07:46:12.38$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.197.07:46:12.38$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.197.07:46:12.38$ifd4f/patch= 2006.197.07:46:12.38$ifd4f/patch=lo1,a1,a2,a3,a4 2006.197.07:46:12.38$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.197.07:46:12.38$ifd4f/patch=lo3,a5,a6,a7,a8 2006.197.07:46:12.38$4f8m12a/"form=m,16.000,1:2 2006.197.07:46:12.38$4f8m12a/"tpicd 2006.197.07:46:12.38$4f8m12a/echo=off 2006.197.07:46:12.38$4f8m12a/xlog=off 2006.197.07:46:12.38:!2006.197.07:47:20 2006.197.07:46:59.13#trakl#Source acquired 2006.197.07:47:01.13#flagr#flagr/antenna,acquired 2006.197.07:47:20.00:preob 2006.197.07:47:20.13/onsource/TRACKING 2006.197.07:47:20.13:!2006.197.07:47:30 2006.197.07:47:30.00:data_valid=on 2006.197.07:47:30.00:midob 2006.197.07:47:31.13/onsource/TRACKING 2006.197.07:47:31.13/wx/25.80,1003.1,97 2006.197.07:47:31.26/cable/+6.3711E-03 2006.197.07:47:32.35/va/01,08,usb,yes,29,31 2006.197.07:47:32.35/va/02,07,usb,yes,29,31 2006.197.07:47:32.35/va/03,06,usb,yes,31,31 2006.197.07:47:32.35/va/04,07,usb,yes,30,32 2006.197.07:47:32.35/va/05,07,usb,yes,34,36 2006.197.07:47:32.35/va/06,06,usb,yes,33,33 2006.197.07:47:32.35/va/07,06,usb,yes,34,33 2006.197.07:47:32.35/va/08,07,usb,yes,32,31 2006.197.07:47:32.58/valo/01,532.99,yes,locked 2006.197.07:47:32.58/valo/02,572.99,yes,locked 2006.197.07:47:32.58/valo/03,672.99,yes,locked 2006.197.07:47:32.58/valo/04,832.99,yes,locked 2006.197.07:47:32.58/valo/05,652.99,yes,locked 2006.197.07:47:32.58/valo/06,772.99,yes,locked 2006.197.07:47:32.58/valo/07,832.99,yes,locked 2006.197.07:47:32.58/valo/08,852.99,yes,locked 2006.197.07:47:33.67/vb/01,04,usb,yes,29,28 2006.197.07:47:33.67/vb/02,04,usb,yes,31,32 2006.197.07:47:33.67/vb/03,04,usb,yes,27,31 2006.197.07:47:33.67/vb/04,04,usb,yes,28,28 2006.197.07:47:33.67/vb/05,04,usb,yes,26,30 2006.197.07:47:33.67/vb/06,04,usb,yes,27,30 2006.197.07:47:33.67/vb/07,04,usb,yes,29,29 2006.197.07:47:33.67/vb/08,04,usb,yes,27,30 2006.197.07:47:33.91/vblo/01,632.99,yes,locked 2006.197.07:47:33.91/vblo/02,640.99,yes,locked 2006.197.07:47:33.91/vblo/03,656.99,yes,locked 2006.197.07:47:33.91/vblo/04,712.99,yes,locked 2006.197.07:47:33.91/vblo/05,744.99,yes,locked 2006.197.07:47:33.91/vblo/06,752.99,yes,locked 2006.197.07:47:33.91/vblo/07,734.99,yes,locked 2006.197.07:47:33.91/vblo/08,744.99,yes,locked 2006.197.07:47:34.06/vabw/8 2006.197.07:47:34.21/vbbw/8 2006.197.07:47:34.36/xfe/off,on,14.7 2006.197.07:47:34.75/ifatt/23,28,28,28 2006.197.07:47:35.10/fmout-gps/S +2.98E-07 2006.197.07:47:35.14:!2006.197.07:48:30 2006.197.07:48:30.00:data_valid=off 2006.197.07:48:30.00:postob 2006.197.07:48:30.22/cable/+6.3695E-03 2006.197.07:48:30.22/wx/25.80,1003.1,97 2006.197.07:48:31.10/fmout-gps/S +2.98E-07 2006.197.07:48:31.10:scan_name=197-0749,k06197,60 2006.197.07:48:31.10:source=1357+769,135755.37,764321.1,2000.0,neutral 2006.197.07:48:31.14#flagr#flagr/antenna,new-source 2006.197.07:48:32.14:checkk5 2006.197.07:48:32.48/chk_autoobs//k5ts1/ autoobs is running! 2006.197.07:48:32.85/chk_autoobs//k5ts2/ autoobs is running! 2006.197.07:48:33.19/chk_autoobs//k5ts3/ autoobs is running! 2006.197.07:48:33.53/chk_autoobs//k5ts4/ autoobs is running! 2006.197.07:48:33.87/chk_obsdata//k5ts1/T1970747??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.07:48:34.20/chk_obsdata//k5ts2/T1970747??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.07:48:34.55/chk_obsdata//k5ts3/T1970747??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.07:48:34.88/chk_obsdata//k5ts4/T1970747??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.07:48:35.55/k5log//k5ts1_log_newline 2006.197.07:48:36.24/k5log//k5ts2_log_newline 2006.197.07:48:36.92/k5log//k5ts3_log_newline 2006.197.07:48:37.58/k5log//k5ts4_log_newline 2006.197.07:48:37.61/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.197.07:48:37.61:4f8m12a=1 2006.197.07:48:37.61$4f8m12a/echo=on 2006.197.07:48:37.61$4f8m12a/pcalon 2006.197.07:48:37.61$pcalon/"no phase cal control is implemented here 2006.197.07:48:37.61$4f8m12a/"tpicd=stop 2006.197.07:48:37.61$4f8m12a/vc4f8 2006.197.07:48:37.61$vc4f8/valo=1,532.99 2006.197.07:48:37.61#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.197.07:48:37.61#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.197.07:48:37.61#ibcon#ireg 17 cls_cnt 0 2006.197.07:48:37.61#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.197.07:48:37.61#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.197.07:48:37.61#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.197.07:48:37.61#ibcon#enter wrdev, iclass 20, count 0 2006.197.07:48:37.61#ibcon#first serial, iclass 20, count 0 2006.197.07:48:37.61#ibcon#enter sib2, iclass 20, count 0 2006.197.07:48:37.61#ibcon#flushed, iclass 20, count 0 2006.197.07:48:37.61#ibcon#about to write, iclass 20, count 0 2006.197.07:48:37.61#ibcon#wrote, iclass 20, count 0 2006.197.07:48:37.61#ibcon#about to read 3, iclass 20, count 0 2006.197.07:48:37.63#ibcon#read 3, iclass 20, count 0 2006.197.07:48:37.63#ibcon#about to read 4, iclass 20, count 0 2006.197.07:48:37.63#ibcon#read 4, iclass 20, count 0 2006.197.07:48:37.63#ibcon#about to read 5, iclass 20, count 0 2006.197.07:48:37.63#ibcon#read 5, iclass 20, count 0 2006.197.07:48:37.63#ibcon#about to read 6, iclass 20, count 0 2006.197.07:48:37.63#ibcon#read 6, iclass 20, count 0 2006.197.07:48:37.63#ibcon#end of sib2, iclass 20, count 0 2006.197.07:48:37.63#ibcon#*mode == 0, iclass 20, count 0 2006.197.07:48:37.63#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.197.07:48:37.63#ibcon#[26=FRQ=01,532.99\r\n] 2006.197.07:48:37.63#ibcon#*before write, iclass 20, count 0 2006.197.07:48:37.63#ibcon#enter sib2, iclass 20, count 0 2006.197.07:48:37.63#ibcon#flushed, iclass 20, count 0 2006.197.07:48:37.63#ibcon#about to write, iclass 20, count 0 2006.197.07:48:37.63#ibcon#wrote, iclass 20, count 0 2006.197.07:48:37.63#ibcon#about to read 3, iclass 20, count 0 2006.197.07:48:37.68#ibcon#read 3, iclass 20, count 0 2006.197.07:48:37.68#ibcon#about to read 4, iclass 20, count 0 2006.197.07:48:37.68#ibcon#read 4, iclass 20, count 0 2006.197.07:48:37.68#ibcon#about to read 5, iclass 20, count 0 2006.197.07:48:37.68#ibcon#read 5, iclass 20, count 0 2006.197.07:48:37.68#ibcon#about to read 6, iclass 20, count 0 2006.197.07:48:37.68#ibcon#read 6, iclass 20, count 0 2006.197.07:48:37.68#ibcon#end of sib2, iclass 20, count 0 2006.197.07:48:37.68#ibcon#*after write, iclass 20, count 0 2006.197.07:48:37.68#ibcon#*before return 0, iclass 20, count 0 2006.197.07:48:37.68#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.197.07:48:37.68#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.197.07:48:37.68#ibcon#about to clear, iclass 20 cls_cnt 0 2006.197.07:48:37.68#ibcon#cleared, iclass 20 cls_cnt 0 2006.197.07:48:37.68$vc4f8/va=1,8 2006.197.07:48:37.68#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.197.07:48:37.68#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.197.07:48:37.68#ibcon#ireg 11 cls_cnt 2 2006.197.07:48:37.68#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.197.07:48:37.68#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.197.07:48:37.68#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.197.07:48:37.68#ibcon#enter wrdev, iclass 22, count 2 2006.197.07:48:37.68#ibcon#first serial, iclass 22, count 2 2006.197.07:48:37.68#ibcon#enter sib2, iclass 22, count 2 2006.197.07:48:37.68#ibcon#flushed, iclass 22, count 2 2006.197.07:48:37.68#ibcon#about to write, iclass 22, count 2 2006.197.07:48:37.68#ibcon#wrote, iclass 22, count 2 2006.197.07:48:37.68#ibcon#about to read 3, iclass 22, count 2 2006.197.07:48:37.70#ibcon#read 3, iclass 22, count 2 2006.197.07:48:37.70#ibcon#about to read 4, iclass 22, count 2 2006.197.07:48:37.70#ibcon#read 4, iclass 22, count 2 2006.197.07:48:37.70#ibcon#about to read 5, iclass 22, count 2 2006.197.07:48:37.70#ibcon#read 5, iclass 22, count 2 2006.197.07:48:37.70#ibcon#about to read 6, iclass 22, count 2 2006.197.07:48:37.70#ibcon#read 6, iclass 22, count 2 2006.197.07:48:37.70#ibcon#end of sib2, iclass 22, count 2 2006.197.07:48:37.70#ibcon#*mode == 0, iclass 22, count 2 2006.197.07:48:37.70#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.197.07:48:37.70#ibcon#[25=AT01-08\r\n] 2006.197.07:48:37.70#ibcon#*before write, iclass 22, count 2 2006.197.07:48:37.70#ibcon#enter sib2, iclass 22, count 2 2006.197.07:48:37.70#ibcon#flushed, iclass 22, count 2 2006.197.07:48:37.70#ibcon#about to write, iclass 22, count 2 2006.197.07:48:37.70#ibcon#wrote, iclass 22, count 2 2006.197.07:48:37.70#ibcon#about to read 3, iclass 22, count 2 2006.197.07:48:37.73#ibcon#read 3, iclass 22, count 2 2006.197.07:48:37.73#ibcon#about to read 4, iclass 22, count 2 2006.197.07:48:37.73#ibcon#read 4, iclass 22, count 2 2006.197.07:48:37.73#ibcon#about to read 5, iclass 22, count 2 2006.197.07:48:37.73#ibcon#read 5, iclass 22, count 2 2006.197.07:48:37.73#ibcon#about to read 6, iclass 22, count 2 2006.197.07:48:37.73#ibcon#read 6, iclass 22, count 2 2006.197.07:48:37.73#ibcon#end of sib2, iclass 22, count 2 2006.197.07:48:37.73#ibcon#*after write, iclass 22, count 2 2006.197.07:48:37.73#ibcon#*before return 0, iclass 22, count 2 2006.197.07:48:37.73#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.197.07:48:37.73#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.197.07:48:37.73#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.197.07:48:37.73#ibcon#ireg 7 cls_cnt 0 2006.197.07:48:37.73#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.197.07:48:37.85#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.197.07:48:37.85#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.197.07:48:37.85#ibcon#enter wrdev, iclass 22, count 0 2006.197.07:48:37.85#ibcon#first serial, iclass 22, count 0 2006.197.07:48:37.85#ibcon#enter sib2, iclass 22, count 0 2006.197.07:48:37.85#ibcon#flushed, iclass 22, count 0 2006.197.07:48:37.85#ibcon#about to write, iclass 22, count 0 2006.197.07:48:37.85#ibcon#wrote, iclass 22, count 0 2006.197.07:48:37.85#ibcon#about to read 3, iclass 22, count 0 2006.197.07:48:37.87#ibcon#read 3, iclass 22, count 0 2006.197.07:48:37.87#ibcon#about to read 4, iclass 22, count 0 2006.197.07:48:37.87#ibcon#read 4, iclass 22, count 0 2006.197.07:48:37.87#ibcon#about to read 5, iclass 22, count 0 2006.197.07:48:37.87#ibcon#read 5, iclass 22, count 0 2006.197.07:48:37.87#ibcon#about to read 6, iclass 22, count 0 2006.197.07:48:37.87#ibcon#read 6, iclass 22, count 0 2006.197.07:48:37.87#ibcon#end of sib2, iclass 22, count 0 2006.197.07:48:37.87#ibcon#*mode == 0, iclass 22, count 0 2006.197.07:48:37.87#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.197.07:48:37.87#ibcon#[25=USB\r\n] 2006.197.07:48:37.87#ibcon#*before write, iclass 22, count 0 2006.197.07:48:37.87#ibcon#enter sib2, iclass 22, count 0 2006.197.07:48:37.87#ibcon#flushed, iclass 22, count 0 2006.197.07:48:37.87#ibcon#about to write, iclass 22, count 0 2006.197.07:48:37.87#ibcon#wrote, iclass 22, count 0 2006.197.07:48:37.87#ibcon#about to read 3, iclass 22, count 0 2006.197.07:48:37.90#ibcon#read 3, iclass 22, count 0 2006.197.07:48:37.90#ibcon#about to read 4, iclass 22, count 0 2006.197.07:48:37.90#ibcon#read 4, iclass 22, count 0 2006.197.07:48:37.90#ibcon#about to read 5, iclass 22, count 0 2006.197.07:48:37.90#ibcon#read 5, iclass 22, count 0 2006.197.07:48:37.90#ibcon#about to read 6, iclass 22, count 0 2006.197.07:48:37.90#ibcon#read 6, iclass 22, count 0 2006.197.07:48:37.90#ibcon#end of sib2, iclass 22, count 0 2006.197.07:48:37.90#ibcon#*after write, iclass 22, count 0 2006.197.07:48:37.90#ibcon#*before return 0, iclass 22, count 0 2006.197.07:48:37.90#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.197.07:48:37.90#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.197.07:48:37.90#ibcon#about to clear, iclass 22 cls_cnt 0 2006.197.07:48:37.90#ibcon#cleared, iclass 22 cls_cnt 0 2006.197.07:48:37.90$vc4f8/valo=2,572.99 2006.197.07:48:37.90#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.197.07:48:37.90#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.197.07:48:37.90#ibcon#ireg 17 cls_cnt 0 2006.197.07:48:37.90#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.197.07:48:37.90#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.197.07:48:37.90#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.197.07:48:37.90#ibcon#enter wrdev, iclass 24, count 0 2006.197.07:48:37.90#ibcon#first serial, iclass 24, count 0 2006.197.07:48:37.90#ibcon#enter sib2, iclass 24, count 0 2006.197.07:48:37.90#ibcon#flushed, iclass 24, count 0 2006.197.07:48:37.90#ibcon#about to write, iclass 24, count 0 2006.197.07:48:37.90#ibcon#wrote, iclass 24, count 0 2006.197.07:48:37.90#ibcon#about to read 3, iclass 24, count 0 2006.197.07:48:37.92#ibcon#read 3, iclass 24, count 0 2006.197.07:48:37.92#ibcon#about to read 4, iclass 24, count 0 2006.197.07:48:37.92#ibcon#read 4, iclass 24, count 0 2006.197.07:48:37.92#ibcon#about to read 5, iclass 24, count 0 2006.197.07:48:37.92#ibcon#read 5, iclass 24, count 0 2006.197.07:48:37.92#ibcon#about to read 6, iclass 24, count 0 2006.197.07:48:37.92#ibcon#read 6, iclass 24, count 0 2006.197.07:48:37.92#ibcon#end of sib2, iclass 24, count 0 2006.197.07:48:37.92#ibcon#*mode == 0, iclass 24, count 0 2006.197.07:48:37.92#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.197.07:48:37.92#ibcon#[26=FRQ=02,572.99\r\n] 2006.197.07:48:37.92#ibcon#*before write, iclass 24, count 0 2006.197.07:48:37.92#ibcon#enter sib2, iclass 24, count 0 2006.197.07:48:37.92#ibcon#flushed, iclass 24, count 0 2006.197.07:48:37.92#ibcon#about to write, iclass 24, count 0 2006.197.07:48:37.92#ibcon#wrote, iclass 24, count 0 2006.197.07:48:37.92#ibcon#about to read 3, iclass 24, count 0 2006.197.07:48:37.96#ibcon#read 3, iclass 24, count 0 2006.197.07:48:37.96#ibcon#about to read 4, iclass 24, count 0 2006.197.07:48:37.96#ibcon#read 4, iclass 24, count 0 2006.197.07:48:37.96#ibcon#about to read 5, iclass 24, count 0 2006.197.07:48:37.96#ibcon#read 5, iclass 24, count 0 2006.197.07:48:37.96#ibcon#about to read 6, iclass 24, count 0 2006.197.07:48:37.96#ibcon#read 6, iclass 24, count 0 2006.197.07:48:37.96#ibcon#end of sib2, iclass 24, count 0 2006.197.07:48:37.96#ibcon#*after write, iclass 24, count 0 2006.197.07:48:37.96#ibcon#*before return 0, iclass 24, count 0 2006.197.07:48:37.96#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.197.07:48:37.96#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.197.07:48:37.96#ibcon#about to clear, iclass 24 cls_cnt 0 2006.197.07:48:37.96#ibcon#cleared, iclass 24 cls_cnt 0 2006.197.07:48:37.96$vc4f8/va=2,7 2006.197.07:48:37.96#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.197.07:48:37.96#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.197.07:48:37.96#ibcon#ireg 11 cls_cnt 2 2006.197.07:48:37.96#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.197.07:48:38.02#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.197.07:48:38.02#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.197.07:48:38.02#ibcon#enter wrdev, iclass 26, count 2 2006.197.07:48:38.02#ibcon#first serial, iclass 26, count 2 2006.197.07:48:38.02#ibcon#enter sib2, iclass 26, count 2 2006.197.07:48:38.02#ibcon#flushed, iclass 26, count 2 2006.197.07:48:38.02#ibcon#about to write, iclass 26, count 2 2006.197.07:48:38.02#ibcon#wrote, iclass 26, count 2 2006.197.07:48:38.02#ibcon#about to read 3, iclass 26, count 2 2006.197.07:48:38.04#ibcon#read 3, iclass 26, count 2 2006.197.07:48:38.04#ibcon#about to read 4, iclass 26, count 2 2006.197.07:48:38.04#ibcon#read 4, iclass 26, count 2 2006.197.07:48:38.04#ibcon#about to read 5, iclass 26, count 2 2006.197.07:48:38.04#ibcon#read 5, iclass 26, count 2 2006.197.07:48:38.04#ibcon#about to read 6, iclass 26, count 2 2006.197.07:48:38.04#ibcon#read 6, iclass 26, count 2 2006.197.07:48:38.04#ibcon#end of sib2, iclass 26, count 2 2006.197.07:48:38.04#ibcon#*mode == 0, iclass 26, count 2 2006.197.07:48:38.04#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.197.07:48:38.04#ibcon#[25=AT02-07\r\n] 2006.197.07:48:38.04#ibcon#*before write, iclass 26, count 2 2006.197.07:48:38.04#ibcon#enter sib2, iclass 26, count 2 2006.197.07:48:38.04#ibcon#flushed, iclass 26, count 2 2006.197.07:48:38.04#ibcon#about to write, iclass 26, count 2 2006.197.07:48:38.04#ibcon#wrote, iclass 26, count 2 2006.197.07:48:38.04#ibcon#about to read 3, iclass 26, count 2 2006.197.07:48:38.07#ibcon#read 3, iclass 26, count 2 2006.197.07:48:38.07#ibcon#about to read 4, iclass 26, count 2 2006.197.07:48:38.07#ibcon#read 4, iclass 26, count 2 2006.197.07:48:38.07#ibcon#about to read 5, iclass 26, count 2 2006.197.07:48:38.07#ibcon#read 5, iclass 26, count 2 2006.197.07:48:38.07#ibcon#about to read 6, iclass 26, count 2 2006.197.07:48:38.07#ibcon#read 6, iclass 26, count 2 2006.197.07:48:38.07#ibcon#end of sib2, iclass 26, count 2 2006.197.07:48:38.07#ibcon#*after write, iclass 26, count 2 2006.197.07:48:38.07#ibcon#*before return 0, iclass 26, count 2 2006.197.07:48:38.07#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.197.07:48:38.07#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.197.07:48:38.07#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.197.07:48:38.07#ibcon#ireg 7 cls_cnt 0 2006.197.07:48:38.07#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.197.07:48:38.19#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.197.07:48:38.19#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.197.07:48:38.19#ibcon#enter wrdev, iclass 26, count 0 2006.197.07:48:38.19#ibcon#first serial, iclass 26, count 0 2006.197.07:48:38.19#ibcon#enter sib2, iclass 26, count 0 2006.197.07:48:38.19#ibcon#flushed, iclass 26, count 0 2006.197.07:48:38.19#ibcon#about to write, iclass 26, count 0 2006.197.07:48:38.19#ibcon#wrote, iclass 26, count 0 2006.197.07:48:38.19#ibcon#about to read 3, iclass 26, count 0 2006.197.07:48:38.21#ibcon#read 3, iclass 26, count 0 2006.197.07:48:38.21#ibcon#about to read 4, iclass 26, count 0 2006.197.07:48:38.21#ibcon#read 4, iclass 26, count 0 2006.197.07:48:38.21#ibcon#about to read 5, iclass 26, count 0 2006.197.07:48:38.21#ibcon#read 5, iclass 26, count 0 2006.197.07:48:38.21#ibcon#about to read 6, iclass 26, count 0 2006.197.07:48:38.21#ibcon#read 6, iclass 26, count 0 2006.197.07:48:38.21#ibcon#end of sib2, iclass 26, count 0 2006.197.07:48:38.21#ibcon#*mode == 0, iclass 26, count 0 2006.197.07:48:38.21#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.197.07:48:38.21#ibcon#[25=USB\r\n] 2006.197.07:48:38.21#ibcon#*before write, iclass 26, count 0 2006.197.07:48:38.21#ibcon#enter sib2, iclass 26, count 0 2006.197.07:48:38.21#ibcon#flushed, iclass 26, count 0 2006.197.07:48:38.21#ibcon#about to write, iclass 26, count 0 2006.197.07:48:38.21#ibcon#wrote, iclass 26, count 0 2006.197.07:48:38.21#ibcon#about to read 3, iclass 26, count 0 2006.197.07:48:38.24#ibcon#read 3, iclass 26, count 0 2006.197.07:48:38.24#ibcon#about to read 4, iclass 26, count 0 2006.197.07:48:38.24#ibcon#read 4, iclass 26, count 0 2006.197.07:48:38.24#ibcon#about to read 5, iclass 26, count 0 2006.197.07:48:38.24#ibcon#read 5, iclass 26, count 0 2006.197.07:48:38.24#ibcon#about to read 6, iclass 26, count 0 2006.197.07:48:38.24#ibcon#read 6, iclass 26, count 0 2006.197.07:48:38.24#ibcon#end of sib2, iclass 26, count 0 2006.197.07:48:38.24#ibcon#*after write, iclass 26, count 0 2006.197.07:48:38.24#ibcon#*before return 0, iclass 26, count 0 2006.197.07:48:38.24#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.197.07:48:38.24#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.197.07:48:38.24#ibcon#about to clear, iclass 26 cls_cnt 0 2006.197.07:48:38.24#ibcon#cleared, iclass 26 cls_cnt 0 2006.197.07:48:38.24$vc4f8/valo=3,672.99 2006.197.07:48:38.24#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.197.07:48:38.24#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.197.07:48:38.24#ibcon#ireg 17 cls_cnt 0 2006.197.07:48:38.24#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.197.07:48:38.24#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.197.07:48:38.24#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.197.07:48:38.24#ibcon#enter wrdev, iclass 28, count 0 2006.197.07:48:38.24#ibcon#first serial, iclass 28, count 0 2006.197.07:48:38.24#ibcon#enter sib2, iclass 28, count 0 2006.197.07:48:38.24#ibcon#flushed, iclass 28, count 0 2006.197.07:48:38.24#ibcon#about to write, iclass 28, count 0 2006.197.07:48:38.24#ibcon#wrote, iclass 28, count 0 2006.197.07:48:38.24#ibcon#about to read 3, iclass 28, count 0 2006.197.07:48:38.26#ibcon#read 3, iclass 28, count 0 2006.197.07:48:38.26#ibcon#about to read 4, iclass 28, count 0 2006.197.07:48:38.26#ibcon#read 4, iclass 28, count 0 2006.197.07:48:38.26#ibcon#about to read 5, iclass 28, count 0 2006.197.07:48:38.26#ibcon#read 5, iclass 28, count 0 2006.197.07:48:38.26#ibcon#about to read 6, iclass 28, count 0 2006.197.07:48:38.26#ibcon#read 6, iclass 28, count 0 2006.197.07:48:38.26#ibcon#end of sib2, iclass 28, count 0 2006.197.07:48:38.26#ibcon#*mode == 0, iclass 28, count 0 2006.197.07:48:38.26#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.197.07:48:38.26#ibcon#[26=FRQ=03,672.99\r\n] 2006.197.07:48:38.26#ibcon#*before write, iclass 28, count 0 2006.197.07:48:38.26#ibcon#enter sib2, iclass 28, count 0 2006.197.07:48:38.26#ibcon#flushed, iclass 28, count 0 2006.197.07:48:38.26#ibcon#about to write, iclass 28, count 0 2006.197.07:48:38.26#ibcon#wrote, iclass 28, count 0 2006.197.07:48:38.26#ibcon#about to read 3, iclass 28, count 0 2006.197.07:48:38.30#ibcon#read 3, iclass 28, count 0 2006.197.07:48:38.30#ibcon#about to read 4, iclass 28, count 0 2006.197.07:48:38.30#ibcon#read 4, iclass 28, count 0 2006.197.07:48:38.30#ibcon#about to read 5, iclass 28, count 0 2006.197.07:48:38.30#ibcon#read 5, iclass 28, count 0 2006.197.07:48:38.30#ibcon#about to read 6, iclass 28, count 0 2006.197.07:48:38.30#ibcon#read 6, iclass 28, count 0 2006.197.07:48:38.30#ibcon#end of sib2, iclass 28, count 0 2006.197.07:48:38.30#ibcon#*after write, iclass 28, count 0 2006.197.07:48:38.30#ibcon#*before return 0, iclass 28, count 0 2006.197.07:48:38.30#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.197.07:48:38.30#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.197.07:48:38.30#ibcon#about to clear, iclass 28 cls_cnt 0 2006.197.07:48:38.30#ibcon#cleared, iclass 28 cls_cnt 0 2006.197.07:48:38.30$vc4f8/va=3,6 2006.197.07:48:38.30#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.197.07:48:38.30#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.197.07:48:38.30#ibcon#ireg 11 cls_cnt 2 2006.197.07:48:38.30#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.197.07:48:38.36#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.197.07:48:38.36#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.197.07:48:38.36#ibcon#enter wrdev, iclass 30, count 2 2006.197.07:48:38.36#ibcon#first serial, iclass 30, count 2 2006.197.07:48:38.36#ibcon#enter sib2, iclass 30, count 2 2006.197.07:48:38.36#ibcon#flushed, iclass 30, count 2 2006.197.07:48:38.36#ibcon#about to write, iclass 30, count 2 2006.197.07:48:38.36#ibcon#wrote, iclass 30, count 2 2006.197.07:48:38.36#ibcon#about to read 3, iclass 30, count 2 2006.197.07:48:38.38#ibcon#read 3, iclass 30, count 2 2006.197.07:48:38.38#ibcon#about to read 4, iclass 30, count 2 2006.197.07:48:38.38#ibcon#read 4, iclass 30, count 2 2006.197.07:48:38.38#ibcon#about to read 5, iclass 30, count 2 2006.197.07:48:38.38#ibcon#read 5, iclass 30, count 2 2006.197.07:48:38.38#ibcon#about to read 6, iclass 30, count 2 2006.197.07:48:38.38#ibcon#read 6, iclass 30, count 2 2006.197.07:48:38.38#ibcon#end of sib2, iclass 30, count 2 2006.197.07:48:38.38#ibcon#*mode == 0, iclass 30, count 2 2006.197.07:48:38.38#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.197.07:48:38.38#ibcon#[25=AT03-06\r\n] 2006.197.07:48:38.38#ibcon#*before write, iclass 30, count 2 2006.197.07:48:38.38#ibcon#enter sib2, iclass 30, count 2 2006.197.07:48:38.38#ibcon#flushed, iclass 30, count 2 2006.197.07:48:38.38#ibcon#about to write, iclass 30, count 2 2006.197.07:48:38.38#ibcon#wrote, iclass 30, count 2 2006.197.07:48:38.38#ibcon#about to read 3, iclass 30, count 2 2006.197.07:48:38.41#ibcon#read 3, iclass 30, count 2 2006.197.07:48:38.41#ibcon#about to read 4, iclass 30, count 2 2006.197.07:48:38.41#ibcon#read 4, iclass 30, count 2 2006.197.07:48:38.41#ibcon#about to read 5, iclass 30, count 2 2006.197.07:48:38.41#ibcon#read 5, iclass 30, count 2 2006.197.07:48:38.41#ibcon#about to read 6, iclass 30, count 2 2006.197.07:48:38.41#ibcon#read 6, iclass 30, count 2 2006.197.07:48:38.41#ibcon#end of sib2, iclass 30, count 2 2006.197.07:48:38.41#ibcon#*after write, iclass 30, count 2 2006.197.07:48:38.41#ibcon#*before return 0, iclass 30, count 2 2006.197.07:48:38.41#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.197.07:48:38.41#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.197.07:48:38.41#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.197.07:48:38.41#ibcon#ireg 7 cls_cnt 0 2006.197.07:48:38.41#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.197.07:48:38.53#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.197.07:48:38.53#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.197.07:48:38.53#ibcon#enter wrdev, iclass 30, count 0 2006.197.07:48:38.53#ibcon#first serial, iclass 30, count 0 2006.197.07:48:38.53#ibcon#enter sib2, iclass 30, count 0 2006.197.07:48:38.53#ibcon#flushed, iclass 30, count 0 2006.197.07:48:38.53#ibcon#about to write, iclass 30, count 0 2006.197.07:48:38.53#ibcon#wrote, iclass 30, count 0 2006.197.07:48:38.53#ibcon#about to read 3, iclass 30, count 0 2006.197.07:48:38.55#ibcon#read 3, iclass 30, count 0 2006.197.07:48:38.55#ibcon#about to read 4, iclass 30, count 0 2006.197.07:48:38.55#ibcon#read 4, iclass 30, count 0 2006.197.07:48:38.55#ibcon#about to read 5, iclass 30, count 0 2006.197.07:48:38.55#ibcon#read 5, iclass 30, count 0 2006.197.07:48:38.55#ibcon#about to read 6, iclass 30, count 0 2006.197.07:48:38.55#ibcon#read 6, iclass 30, count 0 2006.197.07:48:38.55#ibcon#end of sib2, iclass 30, count 0 2006.197.07:48:38.55#ibcon#*mode == 0, iclass 30, count 0 2006.197.07:48:38.55#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.197.07:48:38.55#ibcon#[25=USB\r\n] 2006.197.07:48:38.55#ibcon#*before write, iclass 30, count 0 2006.197.07:48:38.55#ibcon#enter sib2, iclass 30, count 0 2006.197.07:48:38.55#ibcon#flushed, iclass 30, count 0 2006.197.07:48:38.55#ibcon#about to write, iclass 30, count 0 2006.197.07:48:38.55#ibcon#wrote, iclass 30, count 0 2006.197.07:48:38.55#ibcon#about to read 3, iclass 30, count 0 2006.197.07:48:38.58#ibcon#read 3, iclass 30, count 0 2006.197.07:48:38.58#ibcon#about to read 4, iclass 30, count 0 2006.197.07:48:38.58#ibcon#read 4, iclass 30, count 0 2006.197.07:48:38.58#ibcon#about to read 5, iclass 30, count 0 2006.197.07:48:38.58#ibcon#read 5, iclass 30, count 0 2006.197.07:48:38.58#ibcon#about to read 6, iclass 30, count 0 2006.197.07:48:38.58#ibcon#read 6, iclass 30, count 0 2006.197.07:48:38.58#ibcon#end of sib2, iclass 30, count 0 2006.197.07:48:38.58#ibcon#*after write, iclass 30, count 0 2006.197.07:48:38.58#ibcon#*before return 0, iclass 30, count 0 2006.197.07:48:38.58#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.197.07:48:38.58#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.197.07:48:38.58#ibcon#about to clear, iclass 30 cls_cnt 0 2006.197.07:48:38.58#ibcon#cleared, iclass 30 cls_cnt 0 2006.197.07:48:38.58$vc4f8/valo=4,832.99 2006.197.07:48:38.58#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.197.07:48:38.58#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.197.07:48:38.58#ibcon#ireg 17 cls_cnt 0 2006.197.07:48:38.58#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.197.07:48:38.58#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.197.07:48:38.58#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.197.07:48:38.58#ibcon#enter wrdev, iclass 32, count 0 2006.197.07:48:38.58#ibcon#first serial, iclass 32, count 0 2006.197.07:48:38.58#ibcon#enter sib2, iclass 32, count 0 2006.197.07:48:38.58#ibcon#flushed, iclass 32, count 0 2006.197.07:48:38.58#ibcon#about to write, iclass 32, count 0 2006.197.07:48:38.58#ibcon#wrote, iclass 32, count 0 2006.197.07:48:38.58#ibcon#about to read 3, iclass 32, count 0 2006.197.07:48:38.60#ibcon#read 3, iclass 32, count 0 2006.197.07:48:38.60#ibcon#about to read 4, iclass 32, count 0 2006.197.07:48:38.60#ibcon#read 4, iclass 32, count 0 2006.197.07:48:38.60#ibcon#about to read 5, iclass 32, count 0 2006.197.07:48:38.60#ibcon#read 5, iclass 32, count 0 2006.197.07:48:38.60#ibcon#about to read 6, iclass 32, count 0 2006.197.07:48:38.60#ibcon#read 6, iclass 32, count 0 2006.197.07:48:38.60#ibcon#end of sib2, iclass 32, count 0 2006.197.07:48:38.60#ibcon#*mode == 0, iclass 32, count 0 2006.197.07:48:38.60#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.197.07:48:38.60#ibcon#[26=FRQ=04,832.99\r\n] 2006.197.07:48:38.60#ibcon#*before write, iclass 32, count 0 2006.197.07:48:38.60#ibcon#enter sib2, iclass 32, count 0 2006.197.07:48:38.60#ibcon#flushed, iclass 32, count 0 2006.197.07:48:38.60#ibcon#about to write, iclass 32, count 0 2006.197.07:48:38.60#ibcon#wrote, iclass 32, count 0 2006.197.07:48:38.60#ibcon#about to read 3, iclass 32, count 0 2006.197.07:48:38.64#ibcon#read 3, iclass 32, count 0 2006.197.07:48:38.64#ibcon#about to read 4, iclass 32, count 0 2006.197.07:48:38.64#ibcon#read 4, iclass 32, count 0 2006.197.07:48:38.64#ibcon#about to read 5, iclass 32, count 0 2006.197.07:48:38.64#ibcon#read 5, iclass 32, count 0 2006.197.07:48:38.64#ibcon#about to read 6, iclass 32, count 0 2006.197.07:48:38.64#ibcon#read 6, iclass 32, count 0 2006.197.07:48:38.64#ibcon#end of sib2, iclass 32, count 0 2006.197.07:48:38.64#ibcon#*after write, iclass 32, count 0 2006.197.07:48:38.64#ibcon#*before return 0, iclass 32, count 0 2006.197.07:48:38.64#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.197.07:48:38.64#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.197.07:48:38.64#ibcon#about to clear, iclass 32 cls_cnt 0 2006.197.07:48:38.64#ibcon#cleared, iclass 32 cls_cnt 0 2006.197.07:48:38.64$vc4f8/va=4,7 2006.197.07:48:38.64#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.197.07:48:38.64#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.197.07:48:38.64#ibcon#ireg 11 cls_cnt 2 2006.197.07:48:38.64#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.197.07:48:38.70#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.197.07:48:38.70#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.197.07:48:38.70#ibcon#enter wrdev, iclass 34, count 2 2006.197.07:48:38.70#ibcon#first serial, iclass 34, count 2 2006.197.07:48:38.70#ibcon#enter sib2, iclass 34, count 2 2006.197.07:48:38.70#ibcon#flushed, iclass 34, count 2 2006.197.07:48:38.70#ibcon#about to write, iclass 34, count 2 2006.197.07:48:38.70#ibcon#wrote, iclass 34, count 2 2006.197.07:48:38.70#ibcon#about to read 3, iclass 34, count 2 2006.197.07:48:38.72#ibcon#read 3, iclass 34, count 2 2006.197.07:48:38.72#ibcon#about to read 4, iclass 34, count 2 2006.197.07:48:38.72#ibcon#read 4, iclass 34, count 2 2006.197.07:48:38.72#ibcon#about to read 5, iclass 34, count 2 2006.197.07:48:38.72#ibcon#read 5, iclass 34, count 2 2006.197.07:48:38.72#ibcon#about to read 6, iclass 34, count 2 2006.197.07:48:38.72#ibcon#read 6, iclass 34, count 2 2006.197.07:48:38.72#ibcon#end of sib2, iclass 34, count 2 2006.197.07:48:38.72#ibcon#*mode == 0, iclass 34, count 2 2006.197.07:48:38.72#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.197.07:48:38.72#ibcon#[25=AT04-07\r\n] 2006.197.07:48:38.72#ibcon#*before write, iclass 34, count 2 2006.197.07:48:38.72#ibcon#enter sib2, iclass 34, count 2 2006.197.07:48:38.72#ibcon#flushed, iclass 34, count 2 2006.197.07:48:38.72#ibcon#about to write, iclass 34, count 2 2006.197.07:48:38.72#ibcon#wrote, iclass 34, count 2 2006.197.07:48:38.72#ibcon#about to read 3, iclass 34, count 2 2006.197.07:48:38.75#ibcon#read 3, iclass 34, count 2 2006.197.07:48:38.75#ibcon#about to read 4, iclass 34, count 2 2006.197.07:48:38.75#ibcon#read 4, iclass 34, count 2 2006.197.07:48:38.75#ibcon#about to read 5, iclass 34, count 2 2006.197.07:48:38.75#ibcon#read 5, iclass 34, count 2 2006.197.07:48:38.75#ibcon#about to read 6, iclass 34, count 2 2006.197.07:48:38.75#ibcon#read 6, iclass 34, count 2 2006.197.07:48:38.75#ibcon#end of sib2, iclass 34, count 2 2006.197.07:48:38.75#ibcon#*after write, iclass 34, count 2 2006.197.07:48:38.75#ibcon#*before return 0, iclass 34, count 2 2006.197.07:48:38.75#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.197.07:48:38.75#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.197.07:48:38.75#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.197.07:48:38.75#ibcon#ireg 7 cls_cnt 0 2006.197.07:48:38.75#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.197.07:48:38.87#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.197.07:48:38.87#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.197.07:48:38.87#ibcon#enter wrdev, iclass 34, count 0 2006.197.07:48:38.87#ibcon#first serial, iclass 34, count 0 2006.197.07:48:38.87#ibcon#enter sib2, iclass 34, count 0 2006.197.07:48:38.87#ibcon#flushed, iclass 34, count 0 2006.197.07:48:38.87#ibcon#about to write, iclass 34, count 0 2006.197.07:48:38.87#ibcon#wrote, iclass 34, count 0 2006.197.07:48:38.87#ibcon#about to read 3, iclass 34, count 0 2006.197.07:48:38.89#ibcon#read 3, iclass 34, count 0 2006.197.07:48:38.89#ibcon#about to read 4, iclass 34, count 0 2006.197.07:48:38.89#ibcon#read 4, iclass 34, count 0 2006.197.07:48:38.89#ibcon#about to read 5, iclass 34, count 0 2006.197.07:48:38.89#ibcon#read 5, iclass 34, count 0 2006.197.07:48:38.89#ibcon#about to read 6, iclass 34, count 0 2006.197.07:48:38.89#ibcon#read 6, iclass 34, count 0 2006.197.07:48:38.89#ibcon#end of sib2, iclass 34, count 0 2006.197.07:48:38.89#ibcon#*mode == 0, iclass 34, count 0 2006.197.07:48:38.89#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.197.07:48:38.89#ibcon#[25=USB\r\n] 2006.197.07:48:38.89#ibcon#*before write, iclass 34, count 0 2006.197.07:48:38.89#ibcon#enter sib2, iclass 34, count 0 2006.197.07:48:38.89#ibcon#flushed, iclass 34, count 0 2006.197.07:48:38.89#ibcon#about to write, iclass 34, count 0 2006.197.07:48:38.89#ibcon#wrote, iclass 34, count 0 2006.197.07:48:38.89#ibcon#about to read 3, iclass 34, count 0 2006.197.07:48:38.92#ibcon#read 3, iclass 34, count 0 2006.197.07:48:38.92#ibcon#about to read 4, iclass 34, count 0 2006.197.07:48:38.92#ibcon#read 4, iclass 34, count 0 2006.197.07:48:38.92#ibcon#about to read 5, iclass 34, count 0 2006.197.07:48:38.92#ibcon#read 5, iclass 34, count 0 2006.197.07:48:38.92#ibcon#about to read 6, iclass 34, count 0 2006.197.07:48:38.92#ibcon#read 6, iclass 34, count 0 2006.197.07:48:38.92#ibcon#end of sib2, iclass 34, count 0 2006.197.07:48:38.92#ibcon#*after write, iclass 34, count 0 2006.197.07:48:38.92#ibcon#*before return 0, iclass 34, count 0 2006.197.07:48:38.92#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.197.07:48:38.92#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.197.07:48:38.92#ibcon#about to clear, iclass 34 cls_cnt 0 2006.197.07:48:38.92#ibcon#cleared, iclass 34 cls_cnt 0 2006.197.07:48:38.92$vc4f8/valo=5,652.99 2006.197.07:48:38.92#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.197.07:48:38.92#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.197.07:48:38.92#ibcon#ireg 17 cls_cnt 0 2006.197.07:48:38.92#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.197.07:48:38.92#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.197.07:48:38.92#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.197.07:48:38.92#ibcon#enter wrdev, iclass 36, count 0 2006.197.07:48:38.92#ibcon#first serial, iclass 36, count 0 2006.197.07:48:38.92#ibcon#enter sib2, iclass 36, count 0 2006.197.07:48:38.92#ibcon#flushed, iclass 36, count 0 2006.197.07:48:38.92#ibcon#about to write, iclass 36, count 0 2006.197.07:48:38.92#ibcon#wrote, iclass 36, count 0 2006.197.07:48:38.92#ibcon#about to read 3, iclass 36, count 0 2006.197.07:48:38.94#ibcon#read 3, iclass 36, count 0 2006.197.07:48:38.94#ibcon#about to read 4, iclass 36, count 0 2006.197.07:48:38.94#ibcon#read 4, iclass 36, count 0 2006.197.07:48:38.94#ibcon#about to read 5, iclass 36, count 0 2006.197.07:48:38.94#ibcon#read 5, iclass 36, count 0 2006.197.07:48:38.94#ibcon#about to read 6, iclass 36, count 0 2006.197.07:48:38.94#ibcon#read 6, iclass 36, count 0 2006.197.07:48:38.94#ibcon#end of sib2, iclass 36, count 0 2006.197.07:48:38.94#ibcon#*mode == 0, iclass 36, count 0 2006.197.07:48:38.94#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.197.07:48:38.94#ibcon#[26=FRQ=05,652.99\r\n] 2006.197.07:48:38.94#ibcon#*before write, iclass 36, count 0 2006.197.07:48:38.94#ibcon#enter sib2, iclass 36, count 0 2006.197.07:48:38.94#ibcon#flushed, iclass 36, count 0 2006.197.07:48:38.94#ibcon#about to write, iclass 36, count 0 2006.197.07:48:38.94#ibcon#wrote, iclass 36, count 0 2006.197.07:48:38.94#ibcon#about to read 3, iclass 36, count 0 2006.197.07:48:38.98#ibcon#read 3, iclass 36, count 0 2006.197.07:48:38.98#ibcon#about to read 4, iclass 36, count 0 2006.197.07:48:38.98#ibcon#read 4, iclass 36, count 0 2006.197.07:48:38.98#ibcon#about to read 5, iclass 36, count 0 2006.197.07:48:38.98#ibcon#read 5, iclass 36, count 0 2006.197.07:48:38.98#ibcon#about to read 6, iclass 36, count 0 2006.197.07:48:38.98#ibcon#read 6, iclass 36, count 0 2006.197.07:48:38.98#ibcon#end of sib2, iclass 36, count 0 2006.197.07:48:38.98#ibcon#*after write, iclass 36, count 0 2006.197.07:48:38.98#ibcon#*before return 0, iclass 36, count 0 2006.197.07:48:38.98#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.197.07:48:38.98#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.197.07:48:38.98#ibcon#about to clear, iclass 36 cls_cnt 0 2006.197.07:48:38.98#ibcon#cleared, iclass 36 cls_cnt 0 2006.197.07:48:38.98$vc4f8/va=5,7 2006.197.07:48:38.98#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.197.07:48:38.98#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.197.07:48:38.98#ibcon#ireg 11 cls_cnt 2 2006.197.07:48:38.98#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.197.07:48:39.04#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.197.07:48:39.04#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.197.07:48:39.04#ibcon#enter wrdev, iclass 38, count 2 2006.197.07:48:39.04#ibcon#first serial, iclass 38, count 2 2006.197.07:48:39.04#ibcon#enter sib2, iclass 38, count 2 2006.197.07:48:39.04#ibcon#flushed, iclass 38, count 2 2006.197.07:48:39.04#ibcon#about to write, iclass 38, count 2 2006.197.07:48:39.04#ibcon#wrote, iclass 38, count 2 2006.197.07:48:39.04#ibcon#about to read 3, iclass 38, count 2 2006.197.07:48:39.06#ibcon#read 3, iclass 38, count 2 2006.197.07:48:39.06#ibcon#about to read 4, iclass 38, count 2 2006.197.07:48:39.06#ibcon#read 4, iclass 38, count 2 2006.197.07:48:39.06#ibcon#about to read 5, iclass 38, count 2 2006.197.07:48:39.06#ibcon#read 5, iclass 38, count 2 2006.197.07:48:39.06#ibcon#about to read 6, iclass 38, count 2 2006.197.07:48:39.06#ibcon#read 6, iclass 38, count 2 2006.197.07:48:39.06#ibcon#end of sib2, iclass 38, count 2 2006.197.07:48:39.06#ibcon#*mode == 0, iclass 38, count 2 2006.197.07:48:39.06#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.197.07:48:39.06#ibcon#[25=AT05-07\r\n] 2006.197.07:48:39.06#ibcon#*before write, iclass 38, count 2 2006.197.07:48:39.06#ibcon#enter sib2, iclass 38, count 2 2006.197.07:48:39.06#ibcon#flushed, iclass 38, count 2 2006.197.07:48:39.06#ibcon#about to write, iclass 38, count 2 2006.197.07:48:39.06#ibcon#wrote, iclass 38, count 2 2006.197.07:48:39.06#ibcon#about to read 3, iclass 38, count 2 2006.197.07:48:39.09#ibcon#read 3, iclass 38, count 2 2006.197.07:48:39.09#ibcon#about to read 4, iclass 38, count 2 2006.197.07:48:39.09#ibcon#read 4, iclass 38, count 2 2006.197.07:48:39.09#ibcon#about to read 5, iclass 38, count 2 2006.197.07:48:39.09#ibcon#read 5, iclass 38, count 2 2006.197.07:48:39.09#ibcon#about to read 6, iclass 38, count 2 2006.197.07:48:39.09#ibcon#read 6, iclass 38, count 2 2006.197.07:48:39.09#ibcon#end of sib2, iclass 38, count 2 2006.197.07:48:39.09#ibcon#*after write, iclass 38, count 2 2006.197.07:48:39.09#ibcon#*before return 0, iclass 38, count 2 2006.197.07:48:39.09#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.197.07:48:39.09#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.197.07:48:39.09#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.197.07:48:39.09#ibcon#ireg 7 cls_cnt 0 2006.197.07:48:39.09#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.197.07:48:39.21#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.197.07:48:39.21#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.197.07:48:39.21#ibcon#enter wrdev, iclass 38, count 0 2006.197.07:48:39.21#ibcon#first serial, iclass 38, count 0 2006.197.07:48:39.21#ibcon#enter sib2, iclass 38, count 0 2006.197.07:48:39.21#ibcon#flushed, iclass 38, count 0 2006.197.07:48:39.21#ibcon#about to write, iclass 38, count 0 2006.197.07:48:39.21#ibcon#wrote, iclass 38, count 0 2006.197.07:48:39.21#ibcon#about to read 3, iclass 38, count 0 2006.197.07:48:39.23#ibcon#read 3, iclass 38, count 0 2006.197.07:48:39.23#ibcon#about to read 4, iclass 38, count 0 2006.197.07:48:39.23#ibcon#read 4, iclass 38, count 0 2006.197.07:48:39.23#ibcon#about to read 5, iclass 38, count 0 2006.197.07:48:39.23#ibcon#read 5, iclass 38, count 0 2006.197.07:48:39.23#ibcon#about to read 6, iclass 38, count 0 2006.197.07:48:39.23#ibcon#read 6, iclass 38, count 0 2006.197.07:48:39.23#ibcon#end of sib2, iclass 38, count 0 2006.197.07:48:39.23#ibcon#*mode == 0, iclass 38, count 0 2006.197.07:48:39.23#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.197.07:48:39.23#ibcon#[25=USB\r\n] 2006.197.07:48:39.23#ibcon#*before write, iclass 38, count 0 2006.197.07:48:39.23#ibcon#enter sib2, iclass 38, count 0 2006.197.07:48:39.23#ibcon#flushed, iclass 38, count 0 2006.197.07:48:39.23#ibcon#about to write, iclass 38, count 0 2006.197.07:48:39.23#ibcon#wrote, iclass 38, count 0 2006.197.07:48:39.23#ibcon#about to read 3, iclass 38, count 0 2006.197.07:48:39.26#ibcon#read 3, iclass 38, count 0 2006.197.07:48:39.26#ibcon#about to read 4, iclass 38, count 0 2006.197.07:48:39.26#ibcon#read 4, iclass 38, count 0 2006.197.07:48:39.26#ibcon#about to read 5, iclass 38, count 0 2006.197.07:48:39.26#ibcon#read 5, iclass 38, count 0 2006.197.07:48:39.26#ibcon#about to read 6, iclass 38, count 0 2006.197.07:48:39.26#ibcon#read 6, iclass 38, count 0 2006.197.07:48:39.26#ibcon#end of sib2, iclass 38, count 0 2006.197.07:48:39.26#ibcon#*after write, iclass 38, count 0 2006.197.07:48:39.26#ibcon#*before return 0, iclass 38, count 0 2006.197.07:48:39.26#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.197.07:48:39.26#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.197.07:48:39.26#ibcon#about to clear, iclass 38 cls_cnt 0 2006.197.07:48:39.26#ibcon#cleared, iclass 38 cls_cnt 0 2006.197.07:48:39.26$vc4f8/valo=6,772.99 2006.197.07:48:39.26#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.197.07:48:39.26#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.197.07:48:39.26#ibcon#ireg 17 cls_cnt 0 2006.197.07:48:39.26#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.197.07:48:39.26#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.197.07:48:39.26#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.197.07:48:39.26#ibcon#enter wrdev, iclass 40, count 0 2006.197.07:48:39.26#ibcon#first serial, iclass 40, count 0 2006.197.07:48:39.26#ibcon#enter sib2, iclass 40, count 0 2006.197.07:48:39.26#ibcon#flushed, iclass 40, count 0 2006.197.07:48:39.26#ibcon#about to write, iclass 40, count 0 2006.197.07:48:39.26#ibcon#wrote, iclass 40, count 0 2006.197.07:48:39.26#ibcon#about to read 3, iclass 40, count 0 2006.197.07:48:39.28#ibcon#read 3, iclass 40, count 0 2006.197.07:48:39.28#ibcon#about to read 4, iclass 40, count 0 2006.197.07:48:39.28#ibcon#read 4, iclass 40, count 0 2006.197.07:48:39.28#ibcon#about to read 5, iclass 40, count 0 2006.197.07:48:39.28#ibcon#read 5, iclass 40, count 0 2006.197.07:48:39.28#ibcon#about to read 6, iclass 40, count 0 2006.197.07:48:39.28#ibcon#read 6, iclass 40, count 0 2006.197.07:48:39.28#ibcon#end of sib2, iclass 40, count 0 2006.197.07:48:39.28#ibcon#*mode == 0, iclass 40, count 0 2006.197.07:48:39.28#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.197.07:48:39.28#ibcon#[26=FRQ=06,772.99\r\n] 2006.197.07:48:39.28#ibcon#*before write, iclass 40, count 0 2006.197.07:48:39.28#ibcon#enter sib2, iclass 40, count 0 2006.197.07:48:39.28#ibcon#flushed, iclass 40, count 0 2006.197.07:48:39.28#ibcon#about to write, iclass 40, count 0 2006.197.07:48:39.28#ibcon#wrote, iclass 40, count 0 2006.197.07:48:39.28#ibcon#about to read 3, iclass 40, count 0 2006.197.07:48:39.32#ibcon#read 3, iclass 40, count 0 2006.197.07:48:39.32#ibcon#about to read 4, iclass 40, count 0 2006.197.07:48:39.32#ibcon#read 4, iclass 40, count 0 2006.197.07:48:39.32#ibcon#about to read 5, iclass 40, count 0 2006.197.07:48:39.32#ibcon#read 5, iclass 40, count 0 2006.197.07:48:39.32#ibcon#about to read 6, iclass 40, count 0 2006.197.07:48:39.32#ibcon#read 6, iclass 40, count 0 2006.197.07:48:39.32#ibcon#end of sib2, iclass 40, count 0 2006.197.07:48:39.32#ibcon#*after write, iclass 40, count 0 2006.197.07:48:39.32#ibcon#*before return 0, iclass 40, count 0 2006.197.07:48:39.32#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.197.07:48:39.32#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.197.07:48:39.32#ibcon#about to clear, iclass 40 cls_cnt 0 2006.197.07:48:39.32#ibcon#cleared, iclass 40 cls_cnt 0 2006.197.07:48:39.32$vc4f8/va=6,6 2006.197.07:48:39.32#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.197.07:48:39.32#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.197.07:48:39.32#ibcon#ireg 11 cls_cnt 2 2006.197.07:48:39.32#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.197.07:48:39.38#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.197.07:48:39.38#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.197.07:48:39.38#ibcon#enter wrdev, iclass 4, count 2 2006.197.07:48:39.38#ibcon#first serial, iclass 4, count 2 2006.197.07:48:39.38#ibcon#enter sib2, iclass 4, count 2 2006.197.07:48:39.38#ibcon#flushed, iclass 4, count 2 2006.197.07:48:39.38#ibcon#about to write, iclass 4, count 2 2006.197.07:48:39.38#ibcon#wrote, iclass 4, count 2 2006.197.07:48:39.38#ibcon#about to read 3, iclass 4, count 2 2006.197.07:48:39.40#ibcon#read 3, iclass 4, count 2 2006.197.07:48:39.40#ibcon#about to read 4, iclass 4, count 2 2006.197.07:48:39.40#ibcon#read 4, iclass 4, count 2 2006.197.07:48:39.40#ibcon#about to read 5, iclass 4, count 2 2006.197.07:48:39.40#ibcon#read 5, iclass 4, count 2 2006.197.07:48:39.40#ibcon#about to read 6, iclass 4, count 2 2006.197.07:48:39.40#ibcon#read 6, iclass 4, count 2 2006.197.07:48:39.40#ibcon#end of sib2, iclass 4, count 2 2006.197.07:48:39.40#ibcon#*mode == 0, iclass 4, count 2 2006.197.07:48:39.40#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.197.07:48:39.40#ibcon#[25=AT06-06\r\n] 2006.197.07:48:39.40#ibcon#*before write, iclass 4, count 2 2006.197.07:48:39.40#ibcon#enter sib2, iclass 4, count 2 2006.197.07:48:39.40#ibcon#flushed, iclass 4, count 2 2006.197.07:48:39.40#ibcon#about to write, iclass 4, count 2 2006.197.07:48:39.40#ibcon#wrote, iclass 4, count 2 2006.197.07:48:39.40#ibcon#about to read 3, iclass 4, count 2 2006.197.07:48:39.43#ibcon#read 3, iclass 4, count 2 2006.197.07:48:39.43#ibcon#about to read 4, iclass 4, count 2 2006.197.07:48:39.43#ibcon#read 4, iclass 4, count 2 2006.197.07:48:39.43#ibcon#about to read 5, iclass 4, count 2 2006.197.07:48:39.43#ibcon#read 5, iclass 4, count 2 2006.197.07:48:39.43#ibcon#about to read 6, iclass 4, count 2 2006.197.07:48:39.43#ibcon#read 6, iclass 4, count 2 2006.197.07:48:39.43#ibcon#end of sib2, iclass 4, count 2 2006.197.07:48:39.43#ibcon#*after write, iclass 4, count 2 2006.197.07:48:39.43#ibcon#*before return 0, iclass 4, count 2 2006.197.07:48:39.43#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.197.07:48:39.43#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.197.07:48:39.43#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.197.07:48:39.43#ibcon#ireg 7 cls_cnt 0 2006.197.07:48:39.43#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.197.07:48:39.55#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.197.07:48:39.55#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.197.07:48:39.55#ibcon#enter wrdev, iclass 4, count 0 2006.197.07:48:39.55#ibcon#first serial, iclass 4, count 0 2006.197.07:48:39.55#ibcon#enter sib2, iclass 4, count 0 2006.197.07:48:39.55#ibcon#flushed, iclass 4, count 0 2006.197.07:48:39.55#ibcon#about to write, iclass 4, count 0 2006.197.07:48:39.55#ibcon#wrote, iclass 4, count 0 2006.197.07:48:39.55#ibcon#about to read 3, iclass 4, count 0 2006.197.07:48:39.57#ibcon#read 3, iclass 4, count 0 2006.197.07:48:39.57#ibcon#about to read 4, iclass 4, count 0 2006.197.07:48:39.57#ibcon#read 4, iclass 4, count 0 2006.197.07:48:39.57#ibcon#about to read 5, iclass 4, count 0 2006.197.07:48:39.57#ibcon#read 5, iclass 4, count 0 2006.197.07:48:39.57#ibcon#about to read 6, iclass 4, count 0 2006.197.07:48:39.57#ibcon#read 6, iclass 4, count 0 2006.197.07:48:39.57#ibcon#end of sib2, iclass 4, count 0 2006.197.07:48:39.57#ibcon#*mode == 0, iclass 4, count 0 2006.197.07:48:39.57#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.197.07:48:39.57#ibcon#[25=USB\r\n] 2006.197.07:48:39.57#ibcon#*before write, iclass 4, count 0 2006.197.07:48:39.57#ibcon#enter sib2, iclass 4, count 0 2006.197.07:48:39.57#ibcon#flushed, iclass 4, count 0 2006.197.07:48:39.57#ibcon#about to write, iclass 4, count 0 2006.197.07:48:39.57#ibcon#wrote, iclass 4, count 0 2006.197.07:48:39.57#ibcon#about to read 3, iclass 4, count 0 2006.197.07:48:39.60#ibcon#read 3, iclass 4, count 0 2006.197.07:48:39.60#ibcon#about to read 4, iclass 4, count 0 2006.197.07:48:39.60#ibcon#read 4, iclass 4, count 0 2006.197.07:48:39.60#ibcon#about to read 5, iclass 4, count 0 2006.197.07:48:39.60#ibcon#read 5, iclass 4, count 0 2006.197.07:48:39.60#ibcon#about to read 6, iclass 4, count 0 2006.197.07:48:39.60#ibcon#read 6, iclass 4, count 0 2006.197.07:48:39.60#ibcon#end of sib2, iclass 4, count 0 2006.197.07:48:39.60#ibcon#*after write, iclass 4, count 0 2006.197.07:48:39.60#ibcon#*before return 0, iclass 4, count 0 2006.197.07:48:39.60#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.197.07:48:39.60#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.197.07:48:39.60#ibcon#about to clear, iclass 4 cls_cnt 0 2006.197.07:48:39.60#ibcon#cleared, iclass 4 cls_cnt 0 2006.197.07:48:39.60$vc4f8/valo=7,832.99 2006.197.07:48:39.60#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.197.07:48:39.60#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.197.07:48:39.60#ibcon#ireg 17 cls_cnt 0 2006.197.07:48:39.60#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.197.07:48:39.60#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.197.07:48:39.60#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.197.07:48:39.60#ibcon#enter wrdev, iclass 6, count 0 2006.197.07:48:39.60#ibcon#first serial, iclass 6, count 0 2006.197.07:48:39.60#ibcon#enter sib2, iclass 6, count 0 2006.197.07:48:39.60#ibcon#flushed, iclass 6, count 0 2006.197.07:48:39.60#ibcon#about to write, iclass 6, count 0 2006.197.07:48:39.60#ibcon#wrote, iclass 6, count 0 2006.197.07:48:39.60#ibcon#about to read 3, iclass 6, count 0 2006.197.07:48:39.62#ibcon#read 3, iclass 6, count 0 2006.197.07:48:39.62#ibcon#about to read 4, iclass 6, count 0 2006.197.07:48:39.62#ibcon#read 4, iclass 6, count 0 2006.197.07:48:39.62#ibcon#about to read 5, iclass 6, count 0 2006.197.07:48:39.62#ibcon#read 5, iclass 6, count 0 2006.197.07:48:39.62#ibcon#about to read 6, iclass 6, count 0 2006.197.07:48:39.62#ibcon#read 6, iclass 6, count 0 2006.197.07:48:39.62#ibcon#end of sib2, iclass 6, count 0 2006.197.07:48:39.62#ibcon#*mode == 0, iclass 6, count 0 2006.197.07:48:39.62#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.197.07:48:39.62#ibcon#[26=FRQ=07,832.99\r\n] 2006.197.07:48:39.62#ibcon#*before write, iclass 6, count 0 2006.197.07:48:39.62#ibcon#enter sib2, iclass 6, count 0 2006.197.07:48:39.62#ibcon#flushed, iclass 6, count 0 2006.197.07:48:39.62#ibcon#about to write, iclass 6, count 0 2006.197.07:48:39.62#ibcon#wrote, iclass 6, count 0 2006.197.07:48:39.62#ibcon#about to read 3, iclass 6, count 0 2006.197.07:48:39.66#ibcon#read 3, iclass 6, count 0 2006.197.07:48:39.66#ibcon#about to read 4, iclass 6, count 0 2006.197.07:48:39.66#ibcon#read 4, iclass 6, count 0 2006.197.07:48:39.66#ibcon#about to read 5, iclass 6, count 0 2006.197.07:48:39.66#ibcon#read 5, iclass 6, count 0 2006.197.07:48:39.66#ibcon#about to read 6, iclass 6, count 0 2006.197.07:48:39.66#ibcon#read 6, iclass 6, count 0 2006.197.07:48:39.66#ibcon#end of sib2, iclass 6, count 0 2006.197.07:48:39.66#ibcon#*after write, iclass 6, count 0 2006.197.07:48:39.66#ibcon#*before return 0, iclass 6, count 0 2006.197.07:48:39.66#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.197.07:48:39.66#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.197.07:48:39.66#ibcon#about to clear, iclass 6 cls_cnt 0 2006.197.07:48:39.66#ibcon#cleared, iclass 6 cls_cnt 0 2006.197.07:48:39.66$vc4f8/va=7,6 2006.197.07:48:39.66#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.197.07:48:39.66#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.197.07:48:39.66#ibcon#ireg 11 cls_cnt 2 2006.197.07:48:39.66#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.197.07:48:39.72#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.197.07:48:39.72#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.197.07:48:39.72#ibcon#enter wrdev, iclass 10, count 2 2006.197.07:48:39.72#ibcon#first serial, iclass 10, count 2 2006.197.07:48:39.72#ibcon#enter sib2, iclass 10, count 2 2006.197.07:48:39.72#ibcon#flushed, iclass 10, count 2 2006.197.07:48:39.72#ibcon#about to write, iclass 10, count 2 2006.197.07:48:39.72#ibcon#wrote, iclass 10, count 2 2006.197.07:48:39.72#ibcon#about to read 3, iclass 10, count 2 2006.197.07:48:39.74#ibcon#read 3, iclass 10, count 2 2006.197.07:48:39.74#ibcon#about to read 4, iclass 10, count 2 2006.197.07:48:39.74#ibcon#read 4, iclass 10, count 2 2006.197.07:48:39.74#ibcon#about to read 5, iclass 10, count 2 2006.197.07:48:39.74#ibcon#read 5, iclass 10, count 2 2006.197.07:48:39.74#ibcon#about to read 6, iclass 10, count 2 2006.197.07:48:39.74#ibcon#read 6, iclass 10, count 2 2006.197.07:48:39.74#ibcon#end of sib2, iclass 10, count 2 2006.197.07:48:39.74#ibcon#*mode == 0, iclass 10, count 2 2006.197.07:48:39.74#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.197.07:48:39.74#ibcon#[25=AT07-06\r\n] 2006.197.07:48:39.74#ibcon#*before write, iclass 10, count 2 2006.197.07:48:39.74#ibcon#enter sib2, iclass 10, count 2 2006.197.07:48:39.74#ibcon#flushed, iclass 10, count 2 2006.197.07:48:39.74#ibcon#about to write, iclass 10, count 2 2006.197.07:48:39.74#ibcon#wrote, iclass 10, count 2 2006.197.07:48:39.74#ibcon#about to read 3, iclass 10, count 2 2006.197.07:48:39.77#ibcon#read 3, iclass 10, count 2 2006.197.07:48:39.77#ibcon#about to read 4, iclass 10, count 2 2006.197.07:48:39.77#ibcon#read 4, iclass 10, count 2 2006.197.07:48:39.77#ibcon#about to read 5, iclass 10, count 2 2006.197.07:48:39.77#ibcon#read 5, iclass 10, count 2 2006.197.07:48:39.77#ibcon#about to read 6, iclass 10, count 2 2006.197.07:48:39.77#ibcon#read 6, iclass 10, count 2 2006.197.07:48:39.77#ibcon#end of sib2, iclass 10, count 2 2006.197.07:48:39.77#ibcon#*after write, iclass 10, count 2 2006.197.07:48:39.77#ibcon#*before return 0, iclass 10, count 2 2006.197.07:48:39.77#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.197.07:48:39.77#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.197.07:48:39.77#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.197.07:48:39.77#ibcon#ireg 7 cls_cnt 0 2006.197.07:48:39.77#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.197.07:48:39.89#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.197.07:48:39.89#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.197.07:48:39.89#ibcon#enter wrdev, iclass 10, count 0 2006.197.07:48:39.89#ibcon#first serial, iclass 10, count 0 2006.197.07:48:39.89#ibcon#enter sib2, iclass 10, count 0 2006.197.07:48:39.89#ibcon#flushed, iclass 10, count 0 2006.197.07:48:39.89#ibcon#about to write, iclass 10, count 0 2006.197.07:48:39.89#ibcon#wrote, iclass 10, count 0 2006.197.07:48:39.89#ibcon#about to read 3, iclass 10, count 0 2006.197.07:48:39.91#ibcon#read 3, iclass 10, count 0 2006.197.07:48:39.91#ibcon#about to read 4, iclass 10, count 0 2006.197.07:48:39.91#ibcon#read 4, iclass 10, count 0 2006.197.07:48:39.91#ibcon#about to read 5, iclass 10, count 0 2006.197.07:48:39.91#ibcon#read 5, iclass 10, count 0 2006.197.07:48:39.91#ibcon#about to read 6, iclass 10, count 0 2006.197.07:48:39.91#ibcon#read 6, iclass 10, count 0 2006.197.07:48:39.91#ibcon#end of sib2, iclass 10, count 0 2006.197.07:48:39.91#ibcon#*mode == 0, iclass 10, count 0 2006.197.07:48:39.91#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.197.07:48:39.91#ibcon#[25=USB\r\n] 2006.197.07:48:39.91#ibcon#*before write, iclass 10, count 0 2006.197.07:48:39.91#ibcon#enter sib2, iclass 10, count 0 2006.197.07:48:39.91#ibcon#flushed, iclass 10, count 0 2006.197.07:48:39.91#ibcon#about to write, iclass 10, count 0 2006.197.07:48:39.91#ibcon#wrote, iclass 10, count 0 2006.197.07:48:39.91#ibcon#about to read 3, iclass 10, count 0 2006.197.07:48:39.94#ibcon#read 3, iclass 10, count 0 2006.197.07:48:39.94#ibcon#about to read 4, iclass 10, count 0 2006.197.07:48:39.94#ibcon#read 4, iclass 10, count 0 2006.197.07:48:39.94#ibcon#about to read 5, iclass 10, count 0 2006.197.07:48:39.94#ibcon#read 5, iclass 10, count 0 2006.197.07:48:39.94#ibcon#about to read 6, iclass 10, count 0 2006.197.07:48:39.94#ibcon#read 6, iclass 10, count 0 2006.197.07:48:39.94#ibcon#end of sib2, iclass 10, count 0 2006.197.07:48:39.94#ibcon#*after write, iclass 10, count 0 2006.197.07:48:39.94#ibcon#*before return 0, iclass 10, count 0 2006.197.07:48:39.94#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.197.07:48:39.94#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.197.07:48:39.94#ibcon#about to clear, iclass 10 cls_cnt 0 2006.197.07:48:39.94#ibcon#cleared, iclass 10 cls_cnt 0 2006.197.07:48:39.94$vc4f8/valo=8,852.99 2006.197.07:48:39.94#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.197.07:48:39.94#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.197.07:48:39.94#ibcon#ireg 17 cls_cnt 0 2006.197.07:48:39.94#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.197.07:48:39.94#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.197.07:48:39.94#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.197.07:48:39.94#ibcon#enter wrdev, iclass 12, count 0 2006.197.07:48:39.94#ibcon#first serial, iclass 12, count 0 2006.197.07:48:39.94#ibcon#enter sib2, iclass 12, count 0 2006.197.07:48:39.94#ibcon#flushed, iclass 12, count 0 2006.197.07:48:39.94#ibcon#about to write, iclass 12, count 0 2006.197.07:48:39.94#ibcon#wrote, iclass 12, count 0 2006.197.07:48:39.94#ibcon#about to read 3, iclass 12, count 0 2006.197.07:48:39.96#ibcon#read 3, iclass 12, count 0 2006.197.07:48:39.96#ibcon#about to read 4, iclass 12, count 0 2006.197.07:48:39.96#ibcon#read 4, iclass 12, count 0 2006.197.07:48:39.96#ibcon#about to read 5, iclass 12, count 0 2006.197.07:48:39.96#ibcon#read 5, iclass 12, count 0 2006.197.07:48:39.96#ibcon#about to read 6, iclass 12, count 0 2006.197.07:48:39.96#ibcon#read 6, iclass 12, count 0 2006.197.07:48:39.96#ibcon#end of sib2, iclass 12, count 0 2006.197.07:48:39.96#ibcon#*mode == 0, iclass 12, count 0 2006.197.07:48:39.96#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.197.07:48:39.96#ibcon#[26=FRQ=08,852.99\r\n] 2006.197.07:48:39.96#ibcon#*before write, iclass 12, count 0 2006.197.07:48:39.96#ibcon#enter sib2, iclass 12, count 0 2006.197.07:48:39.96#ibcon#flushed, iclass 12, count 0 2006.197.07:48:39.96#ibcon#about to write, iclass 12, count 0 2006.197.07:48:39.96#ibcon#wrote, iclass 12, count 0 2006.197.07:48:39.96#ibcon#about to read 3, iclass 12, count 0 2006.197.07:48:40.00#ibcon#read 3, iclass 12, count 0 2006.197.07:48:40.00#ibcon#about to read 4, iclass 12, count 0 2006.197.07:48:40.00#ibcon#read 4, iclass 12, count 0 2006.197.07:48:40.00#ibcon#about to read 5, iclass 12, count 0 2006.197.07:48:40.00#ibcon#read 5, iclass 12, count 0 2006.197.07:48:40.00#ibcon#about to read 6, iclass 12, count 0 2006.197.07:48:40.00#ibcon#read 6, iclass 12, count 0 2006.197.07:48:40.00#ibcon#end of sib2, iclass 12, count 0 2006.197.07:48:40.00#ibcon#*after write, iclass 12, count 0 2006.197.07:48:40.00#ibcon#*before return 0, iclass 12, count 0 2006.197.07:48:40.00#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.197.07:48:40.00#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.197.07:48:40.00#ibcon#about to clear, iclass 12 cls_cnt 0 2006.197.07:48:40.00#ibcon#cleared, iclass 12 cls_cnt 0 2006.197.07:48:40.00$vc4f8/va=8,7 2006.197.07:48:40.00#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.197.07:48:40.00#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.197.07:48:40.00#ibcon#ireg 11 cls_cnt 2 2006.197.07:48:40.00#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.197.07:48:40.06#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.197.07:48:40.06#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.197.07:48:40.06#ibcon#enter wrdev, iclass 14, count 2 2006.197.07:48:40.06#ibcon#first serial, iclass 14, count 2 2006.197.07:48:40.06#ibcon#enter sib2, iclass 14, count 2 2006.197.07:48:40.06#ibcon#flushed, iclass 14, count 2 2006.197.07:48:40.06#ibcon#about to write, iclass 14, count 2 2006.197.07:48:40.06#ibcon#wrote, iclass 14, count 2 2006.197.07:48:40.06#ibcon#about to read 3, iclass 14, count 2 2006.197.07:48:40.08#ibcon#read 3, iclass 14, count 2 2006.197.07:48:40.08#ibcon#about to read 4, iclass 14, count 2 2006.197.07:48:40.08#ibcon#read 4, iclass 14, count 2 2006.197.07:48:40.08#ibcon#about to read 5, iclass 14, count 2 2006.197.07:48:40.08#ibcon#read 5, iclass 14, count 2 2006.197.07:48:40.08#ibcon#about to read 6, iclass 14, count 2 2006.197.07:48:40.08#ibcon#read 6, iclass 14, count 2 2006.197.07:48:40.08#ibcon#end of sib2, iclass 14, count 2 2006.197.07:48:40.08#ibcon#*mode == 0, iclass 14, count 2 2006.197.07:48:40.08#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.197.07:48:40.08#ibcon#[25=AT08-07\r\n] 2006.197.07:48:40.08#ibcon#*before write, iclass 14, count 2 2006.197.07:48:40.08#ibcon#enter sib2, iclass 14, count 2 2006.197.07:48:40.08#ibcon#flushed, iclass 14, count 2 2006.197.07:48:40.08#ibcon#about to write, iclass 14, count 2 2006.197.07:48:40.08#ibcon#wrote, iclass 14, count 2 2006.197.07:48:40.08#ibcon#about to read 3, iclass 14, count 2 2006.197.07:48:40.11#ibcon#read 3, iclass 14, count 2 2006.197.07:48:40.11#ibcon#about to read 4, iclass 14, count 2 2006.197.07:48:40.11#ibcon#read 4, iclass 14, count 2 2006.197.07:48:40.11#ibcon#about to read 5, iclass 14, count 2 2006.197.07:48:40.11#ibcon#read 5, iclass 14, count 2 2006.197.07:48:40.11#ibcon#about to read 6, iclass 14, count 2 2006.197.07:48:40.11#ibcon#read 6, iclass 14, count 2 2006.197.07:48:40.11#ibcon#end of sib2, iclass 14, count 2 2006.197.07:48:40.11#ibcon#*after write, iclass 14, count 2 2006.197.07:48:40.11#ibcon#*before return 0, iclass 14, count 2 2006.197.07:48:40.11#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.197.07:48:40.11#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.197.07:48:40.11#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.197.07:48:40.11#ibcon#ireg 7 cls_cnt 0 2006.197.07:48:40.11#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.197.07:48:40.23#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.197.07:48:40.23#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.197.07:48:40.23#ibcon#enter wrdev, iclass 14, count 0 2006.197.07:48:40.23#ibcon#first serial, iclass 14, count 0 2006.197.07:48:40.23#ibcon#enter sib2, iclass 14, count 0 2006.197.07:48:40.23#ibcon#flushed, iclass 14, count 0 2006.197.07:48:40.23#ibcon#about to write, iclass 14, count 0 2006.197.07:48:40.23#ibcon#wrote, iclass 14, count 0 2006.197.07:48:40.23#ibcon#about to read 3, iclass 14, count 0 2006.197.07:48:40.25#ibcon#read 3, iclass 14, count 0 2006.197.07:48:40.25#ibcon#about to read 4, iclass 14, count 0 2006.197.07:48:40.25#ibcon#read 4, iclass 14, count 0 2006.197.07:48:40.25#ibcon#about to read 5, iclass 14, count 0 2006.197.07:48:40.25#ibcon#read 5, iclass 14, count 0 2006.197.07:48:40.25#ibcon#about to read 6, iclass 14, count 0 2006.197.07:48:40.25#ibcon#read 6, iclass 14, count 0 2006.197.07:48:40.25#ibcon#end of sib2, iclass 14, count 0 2006.197.07:48:40.25#ibcon#*mode == 0, iclass 14, count 0 2006.197.07:48:40.25#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.197.07:48:40.25#ibcon#[25=USB\r\n] 2006.197.07:48:40.25#ibcon#*before write, iclass 14, count 0 2006.197.07:48:40.25#ibcon#enter sib2, iclass 14, count 0 2006.197.07:48:40.25#ibcon#flushed, iclass 14, count 0 2006.197.07:48:40.25#ibcon#about to write, iclass 14, count 0 2006.197.07:48:40.25#ibcon#wrote, iclass 14, count 0 2006.197.07:48:40.25#ibcon#about to read 3, iclass 14, count 0 2006.197.07:48:40.28#ibcon#read 3, iclass 14, count 0 2006.197.07:48:40.28#ibcon#about to read 4, iclass 14, count 0 2006.197.07:48:40.28#ibcon#read 4, iclass 14, count 0 2006.197.07:48:40.28#ibcon#about to read 5, iclass 14, count 0 2006.197.07:48:40.28#ibcon#read 5, iclass 14, count 0 2006.197.07:48:40.28#ibcon#about to read 6, iclass 14, count 0 2006.197.07:48:40.28#ibcon#read 6, iclass 14, count 0 2006.197.07:48:40.28#ibcon#end of sib2, iclass 14, count 0 2006.197.07:48:40.28#ibcon#*after write, iclass 14, count 0 2006.197.07:48:40.28#ibcon#*before return 0, iclass 14, count 0 2006.197.07:48:40.28#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.197.07:48:40.28#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.197.07:48:40.28#ibcon#about to clear, iclass 14 cls_cnt 0 2006.197.07:48:40.28#ibcon#cleared, iclass 14 cls_cnt 0 2006.197.07:48:40.28$vc4f8/vblo=1,632.99 2006.197.07:48:40.28#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.197.07:48:40.28#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.197.07:48:40.28#ibcon#ireg 17 cls_cnt 0 2006.197.07:48:40.28#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.197.07:48:40.28#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.197.07:48:40.28#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.197.07:48:40.28#ibcon#enter wrdev, iclass 16, count 0 2006.197.07:48:40.28#ibcon#first serial, iclass 16, count 0 2006.197.07:48:40.28#ibcon#enter sib2, iclass 16, count 0 2006.197.07:48:40.28#ibcon#flushed, iclass 16, count 0 2006.197.07:48:40.28#ibcon#about to write, iclass 16, count 0 2006.197.07:48:40.28#ibcon#wrote, iclass 16, count 0 2006.197.07:48:40.28#ibcon#about to read 3, iclass 16, count 0 2006.197.07:48:40.30#ibcon#read 3, iclass 16, count 0 2006.197.07:48:40.30#ibcon#about to read 4, iclass 16, count 0 2006.197.07:48:40.30#ibcon#read 4, iclass 16, count 0 2006.197.07:48:40.30#ibcon#about to read 5, iclass 16, count 0 2006.197.07:48:40.30#ibcon#read 5, iclass 16, count 0 2006.197.07:48:40.30#ibcon#about to read 6, iclass 16, count 0 2006.197.07:48:40.30#ibcon#read 6, iclass 16, count 0 2006.197.07:48:40.30#ibcon#end of sib2, iclass 16, count 0 2006.197.07:48:40.30#ibcon#*mode == 0, iclass 16, count 0 2006.197.07:48:40.30#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.197.07:48:40.30#ibcon#[28=FRQ=01,632.99\r\n] 2006.197.07:48:40.30#ibcon#*before write, iclass 16, count 0 2006.197.07:48:40.30#ibcon#enter sib2, iclass 16, count 0 2006.197.07:48:40.30#ibcon#flushed, iclass 16, count 0 2006.197.07:48:40.30#ibcon#about to write, iclass 16, count 0 2006.197.07:48:40.30#ibcon#wrote, iclass 16, count 0 2006.197.07:48:40.30#ibcon#about to read 3, iclass 16, count 0 2006.197.07:48:40.34#ibcon#read 3, iclass 16, count 0 2006.197.07:48:40.34#ibcon#about to read 4, iclass 16, count 0 2006.197.07:48:40.34#ibcon#read 4, iclass 16, count 0 2006.197.07:48:40.34#ibcon#about to read 5, iclass 16, count 0 2006.197.07:48:40.34#ibcon#read 5, iclass 16, count 0 2006.197.07:48:40.34#ibcon#about to read 6, iclass 16, count 0 2006.197.07:48:40.34#ibcon#read 6, iclass 16, count 0 2006.197.07:48:40.34#ibcon#end of sib2, iclass 16, count 0 2006.197.07:48:40.34#ibcon#*after write, iclass 16, count 0 2006.197.07:48:40.34#ibcon#*before return 0, iclass 16, count 0 2006.197.07:48:40.34#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.197.07:48:40.34#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.197.07:48:40.34#ibcon#about to clear, iclass 16 cls_cnt 0 2006.197.07:48:40.34#ibcon#cleared, iclass 16 cls_cnt 0 2006.197.07:48:40.34$vc4f8/vb=1,4 2006.197.07:48:40.34#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.197.07:48:40.34#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.197.07:48:40.34#ibcon#ireg 11 cls_cnt 2 2006.197.07:48:40.34#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.197.07:48:40.34#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.197.07:48:40.34#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.197.07:48:40.34#ibcon#enter wrdev, iclass 18, count 2 2006.197.07:48:40.34#ibcon#first serial, iclass 18, count 2 2006.197.07:48:40.34#ibcon#enter sib2, iclass 18, count 2 2006.197.07:48:40.34#ibcon#flushed, iclass 18, count 2 2006.197.07:48:40.34#ibcon#about to write, iclass 18, count 2 2006.197.07:48:40.34#ibcon#wrote, iclass 18, count 2 2006.197.07:48:40.34#ibcon#about to read 3, iclass 18, count 2 2006.197.07:48:40.36#ibcon#read 3, iclass 18, count 2 2006.197.07:48:40.36#ibcon#about to read 4, iclass 18, count 2 2006.197.07:48:40.36#ibcon#read 4, iclass 18, count 2 2006.197.07:48:40.36#ibcon#about to read 5, iclass 18, count 2 2006.197.07:48:40.36#ibcon#read 5, iclass 18, count 2 2006.197.07:48:40.36#ibcon#about to read 6, iclass 18, count 2 2006.197.07:48:40.36#ibcon#read 6, iclass 18, count 2 2006.197.07:48:40.36#ibcon#end of sib2, iclass 18, count 2 2006.197.07:48:40.36#ibcon#*mode == 0, iclass 18, count 2 2006.197.07:48:40.36#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.197.07:48:40.36#ibcon#[27=AT01-04\r\n] 2006.197.07:48:40.36#ibcon#*before write, iclass 18, count 2 2006.197.07:48:40.36#ibcon#enter sib2, iclass 18, count 2 2006.197.07:48:40.36#ibcon#flushed, iclass 18, count 2 2006.197.07:48:40.36#ibcon#about to write, iclass 18, count 2 2006.197.07:48:40.36#ibcon#wrote, iclass 18, count 2 2006.197.07:48:40.36#ibcon#about to read 3, iclass 18, count 2 2006.197.07:48:40.39#ibcon#read 3, iclass 18, count 2 2006.197.07:48:40.39#ibcon#about to read 4, iclass 18, count 2 2006.197.07:48:40.39#ibcon#read 4, iclass 18, count 2 2006.197.07:48:40.39#ibcon#about to read 5, iclass 18, count 2 2006.197.07:48:40.39#ibcon#read 5, iclass 18, count 2 2006.197.07:48:40.39#ibcon#about to read 6, iclass 18, count 2 2006.197.07:48:40.39#ibcon#read 6, iclass 18, count 2 2006.197.07:48:40.39#ibcon#end of sib2, iclass 18, count 2 2006.197.07:48:40.39#ibcon#*after write, iclass 18, count 2 2006.197.07:48:40.39#ibcon#*before return 0, iclass 18, count 2 2006.197.07:48:40.39#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.197.07:48:40.39#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.197.07:48:40.39#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.197.07:48:40.39#ibcon#ireg 7 cls_cnt 0 2006.197.07:48:40.39#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.197.07:48:40.51#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.197.07:48:40.51#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.197.07:48:40.51#ibcon#enter wrdev, iclass 18, count 0 2006.197.07:48:40.51#ibcon#first serial, iclass 18, count 0 2006.197.07:48:40.51#ibcon#enter sib2, iclass 18, count 0 2006.197.07:48:40.51#ibcon#flushed, iclass 18, count 0 2006.197.07:48:40.51#ibcon#about to write, iclass 18, count 0 2006.197.07:48:40.51#ibcon#wrote, iclass 18, count 0 2006.197.07:48:40.51#ibcon#about to read 3, iclass 18, count 0 2006.197.07:48:40.53#ibcon#read 3, iclass 18, count 0 2006.197.07:48:40.53#ibcon#about to read 4, iclass 18, count 0 2006.197.07:48:40.53#ibcon#read 4, iclass 18, count 0 2006.197.07:48:40.53#ibcon#about to read 5, iclass 18, count 0 2006.197.07:48:40.53#ibcon#read 5, iclass 18, count 0 2006.197.07:48:40.53#ibcon#about to read 6, iclass 18, count 0 2006.197.07:48:40.53#ibcon#read 6, iclass 18, count 0 2006.197.07:48:40.53#ibcon#end of sib2, iclass 18, count 0 2006.197.07:48:40.53#ibcon#*mode == 0, iclass 18, count 0 2006.197.07:48:40.53#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.197.07:48:40.53#ibcon#[27=USB\r\n] 2006.197.07:48:40.53#ibcon#*before write, iclass 18, count 0 2006.197.07:48:40.53#ibcon#enter sib2, iclass 18, count 0 2006.197.07:48:40.53#ibcon#flushed, iclass 18, count 0 2006.197.07:48:40.53#ibcon#about to write, iclass 18, count 0 2006.197.07:48:40.53#ibcon#wrote, iclass 18, count 0 2006.197.07:48:40.53#ibcon#about to read 3, iclass 18, count 0 2006.197.07:48:40.56#ibcon#read 3, iclass 18, count 0 2006.197.07:48:40.56#ibcon#about to read 4, iclass 18, count 0 2006.197.07:48:40.56#ibcon#read 4, iclass 18, count 0 2006.197.07:48:40.56#ibcon#about to read 5, iclass 18, count 0 2006.197.07:48:40.56#ibcon#read 5, iclass 18, count 0 2006.197.07:48:40.56#ibcon#about to read 6, iclass 18, count 0 2006.197.07:48:40.56#ibcon#read 6, iclass 18, count 0 2006.197.07:48:40.56#ibcon#end of sib2, iclass 18, count 0 2006.197.07:48:40.56#ibcon#*after write, iclass 18, count 0 2006.197.07:48:40.56#ibcon#*before return 0, iclass 18, count 0 2006.197.07:48:40.56#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.197.07:48:40.56#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.197.07:48:40.56#ibcon#about to clear, iclass 18 cls_cnt 0 2006.197.07:48:40.56#ibcon#cleared, iclass 18 cls_cnt 0 2006.197.07:48:40.56$vc4f8/vblo=2,640.99 2006.197.07:48:40.56#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.197.07:48:40.56#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.197.07:48:40.56#ibcon#ireg 17 cls_cnt 0 2006.197.07:48:40.56#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.197.07:48:40.56#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.197.07:48:40.56#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.197.07:48:40.56#ibcon#enter wrdev, iclass 20, count 0 2006.197.07:48:40.56#ibcon#first serial, iclass 20, count 0 2006.197.07:48:40.56#ibcon#enter sib2, iclass 20, count 0 2006.197.07:48:40.56#ibcon#flushed, iclass 20, count 0 2006.197.07:48:40.56#ibcon#about to write, iclass 20, count 0 2006.197.07:48:40.56#ibcon#wrote, iclass 20, count 0 2006.197.07:48:40.56#ibcon#about to read 3, iclass 20, count 0 2006.197.07:48:40.58#ibcon#read 3, iclass 20, count 0 2006.197.07:48:40.58#ibcon#about to read 4, iclass 20, count 0 2006.197.07:48:40.58#ibcon#read 4, iclass 20, count 0 2006.197.07:48:40.58#ibcon#about to read 5, iclass 20, count 0 2006.197.07:48:40.58#ibcon#read 5, iclass 20, count 0 2006.197.07:48:40.58#ibcon#about to read 6, iclass 20, count 0 2006.197.07:48:40.58#ibcon#read 6, iclass 20, count 0 2006.197.07:48:40.58#ibcon#end of sib2, iclass 20, count 0 2006.197.07:48:40.58#ibcon#*mode == 0, iclass 20, count 0 2006.197.07:48:40.58#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.197.07:48:40.58#ibcon#[28=FRQ=02,640.99\r\n] 2006.197.07:48:40.58#ibcon#*before write, iclass 20, count 0 2006.197.07:48:40.58#ibcon#enter sib2, iclass 20, count 0 2006.197.07:48:40.58#ibcon#flushed, iclass 20, count 0 2006.197.07:48:40.58#ibcon#about to write, iclass 20, count 0 2006.197.07:48:40.58#ibcon#wrote, iclass 20, count 0 2006.197.07:48:40.58#ibcon#about to read 3, iclass 20, count 0 2006.197.07:48:40.62#ibcon#read 3, iclass 20, count 0 2006.197.07:48:40.62#ibcon#about to read 4, iclass 20, count 0 2006.197.07:48:40.62#ibcon#read 4, iclass 20, count 0 2006.197.07:48:40.62#ibcon#about to read 5, iclass 20, count 0 2006.197.07:48:40.62#ibcon#read 5, iclass 20, count 0 2006.197.07:48:40.62#ibcon#about to read 6, iclass 20, count 0 2006.197.07:48:40.62#ibcon#read 6, iclass 20, count 0 2006.197.07:48:40.62#ibcon#end of sib2, iclass 20, count 0 2006.197.07:48:40.62#ibcon#*after write, iclass 20, count 0 2006.197.07:48:40.62#ibcon#*before return 0, iclass 20, count 0 2006.197.07:48:40.62#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.197.07:48:40.62#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.197.07:48:40.62#ibcon#about to clear, iclass 20 cls_cnt 0 2006.197.07:48:40.62#ibcon#cleared, iclass 20 cls_cnt 0 2006.197.07:48:40.62$vc4f8/vb=2,4 2006.197.07:48:40.62#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.197.07:48:40.62#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.197.07:48:40.62#ibcon#ireg 11 cls_cnt 2 2006.197.07:48:40.62#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.197.07:48:40.68#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.197.07:48:40.68#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.197.07:48:40.68#ibcon#enter wrdev, iclass 22, count 2 2006.197.07:48:40.68#ibcon#first serial, iclass 22, count 2 2006.197.07:48:40.68#ibcon#enter sib2, iclass 22, count 2 2006.197.07:48:40.68#ibcon#flushed, iclass 22, count 2 2006.197.07:48:40.68#ibcon#about to write, iclass 22, count 2 2006.197.07:48:40.68#ibcon#wrote, iclass 22, count 2 2006.197.07:48:40.68#ibcon#about to read 3, iclass 22, count 2 2006.197.07:48:40.70#ibcon#read 3, iclass 22, count 2 2006.197.07:48:40.70#ibcon#about to read 4, iclass 22, count 2 2006.197.07:48:40.70#ibcon#read 4, iclass 22, count 2 2006.197.07:48:40.70#ibcon#about to read 5, iclass 22, count 2 2006.197.07:48:40.70#ibcon#read 5, iclass 22, count 2 2006.197.07:48:40.70#ibcon#about to read 6, iclass 22, count 2 2006.197.07:48:40.70#ibcon#read 6, iclass 22, count 2 2006.197.07:48:40.70#ibcon#end of sib2, iclass 22, count 2 2006.197.07:48:40.70#ibcon#*mode == 0, iclass 22, count 2 2006.197.07:48:40.70#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.197.07:48:40.70#ibcon#[27=AT02-04\r\n] 2006.197.07:48:40.70#ibcon#*before write, iclass 22, count 2 2006.197.07:48:40.70#ibcon#enter sib2, iclass 22, count 2 2006.197.07:48:40.70#ibcon#flushed, iclass 22, count 2 2006.197.07:48:40.70#ibcon#about to write, iclass 22, count 2 2006.197.07:48:40.70#ibcon#wrote, iclass 22, count 2 2006.197.07:48:40.70#ibcon#about to read 3, iclass 22, count 2 2006.197.07:48:40.73#ibcon#read 3, iclass 22, count 2 2006.197.07:48:40.73#ibcon#about to read 4, iclass 22, count 2 2006.197.07:48:40.73#ibcon#read 4, iclass 22, count 2 2006.197.07:48:40.73#ibcon#about to read 5, iclass 22, count 2 2006.197.07:48:40.73#ibcon#read 5, iclass 22, count 2 2006.197.07:48:40.73#ibcon#about to read 6, iclass 22, count 2 2006.197.07:48:40.73#ibcon#read 6, iclass 22, count 2 2006.197.07:48:40.73#ibcon#end of sib2, iclass 22, count 2 2006.197.07:48:40.73#ibcon#*after write, iclass 22, count 2 2006.197.07:48:40.73#ibcon#*before return 0, iclass 22, count 2 2006.197.07:48:40.73#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.197.07:48:40.73#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.197.07:48:40.73#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.197.07:48:40.73#ibcon#ireg 7 cls_cnt 0 2006.197.07:48:40.73#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.197.07:48:40.85#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.197.07:48:40.85#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.197.07:48:40.85#ibcon#enter wrdev, iclass 22, count 0 2006.197.07:48:40.85#ibcon#first serial, iclass 22, count 0 2006.197.07:48:40.85#ibcon#enter sib2, iclass 22, count 0 2006.197.07:48:40.85#ibcon#flushed, iclass 22, count 0 2006.197.07:48:40.85#ibcon#about to write, iclass 22, count 0 2006.197.07:48:40.85#ibcon#wrote, iclass 22, count 0 2006.197.07:48:40.85#ibcon#about to read 3, iclass 22, count 0 2006.197.07:48:40.87#ibcon#read 3, iclass 22, count 0 2006.197.07:48:40.87#ibcon#about to read 4, iclass 22, count 0 2006.197.07:48:40.87#ibcon#read 4, iclass 22, count 0 2006.197.07:48:40.87#ibcon#about to read 5, iclass 22, count 0 2006.197.07:48:40.87#ibcon#read 5, iclass 22, count 0 2006.197.07:48:40.87#ibcon#about to read 6, iclass 22, count 0 2006.197.07:48:40.87#ibcon#read 6, iclass 22, count 0 2006.197.07:48:40.87#ibcon#end of sib2, iclass 22, count 0 2006.197.07:48:40.87#ibcon#*mode == 0, iclass 22, count 0 2006.197.07:48:40.87#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.197.07:48:40.87#ibcon#[27=USB\r\n] 2006.197.07:48:40.87#ibcon#*before write, iclass 22, count 0 2006.197.07:48:40.87#ibcon#enter sib2, iclass 22, count 0 2006.197.07:48:40.87#ibcon#flushed, iclass 22, count 0 2006.197.07:48:40.87#ibcon#about to write, iclass 22, count 0 2006.197.07:48:40.87#ibcon#wrote, iclass 22, count 0 2006.197.07:48:40.87#ibcon#about to read 3, iclass 22, count 0 2006.197.07:48:40.90#ibcon#read 3, iclass 22, count 0 2006.197.07:48:40.90#ibcon#about to read 4, iclass 22, count 0 2006.197.07:48:40.90#ibcon#read 4, iclass 22, count 0 2006.197.07:48:40.90#ibcon#about to read 5, iclass 22, count 0 2006.197.07:48:40.90#ibcon#read 5, iclass 22, count 0 2006.197.07:48:40.90#ibcon#about to read 6, iclass 22, count 0 2006.197.07:48:40.90#ibcon#read 6, iclass 22, count 0 2006.197.07:48:40.90#ibcon#end of sib2, iclass 22, count 0 2006.197.07:48:40.90#ibcon#*after write, iclass 22, count 0 2006.197.07:48:40.90#ibcon#*before return 0, iclass 22, count 0 2006.197.07:48:40.90#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.197.07:48:40.90#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.197.07:48:40.90#ibcon#about to clear, iclass 22 cls_cnt 0 2006.197.07:48:40.90#ibcon#cleared, iclass 22 cls_cnt 0 2006.197.07:48:40.90$vc4f8/vblo=3,656.99 2006.197.07:48:40.90#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.197.07:48:40.90#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.197.07:48:40.90#ibcon#ireg 17 cls_cnt 0 2006.197.07:48:40.90#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.197.07:48:40.90#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.197.07:48:40.90#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.197.07:48:40.90#ibcon#enter wrdev, iclass 24, count 0 2006.197.07:48:40.90#ibcon#first serial, iclass 24, count 0 2006.197.07:48:40.90#ibcon#enter sib2, iclass 24, count 0 2006.197.07:48:40.90#ibcon#flushed, iclass 24, count 0 2006.197.07:48:40.90#ibcon#about to write, iclass 24, count 0 2006.197.07:48:40.90#ibcon#wrote, iclass 24, count 0 2006.197.07:48:40.90#ibcon#about to read 3, iclass 24, count 0 2006.197.07:48:40.92#ibcon#read 3, iclass 24, count 0 2006.197.07:48:40.92#ibcon#about to read 4, iclass 24, count 0 2006.197.07:48:40.92#ibcon#read 4, iclass 24, count 0 2006.197.07:48:40.92#ibcon#about to read 5, iclass 24, count 0 2006.197.07:48:40.92#ibcon#read 5, iclass 24, count 0 2006.197.07:48:40.92#ibcon#about to read 6, iclass 24, count 0 2006.197.07:48:40.92#ibcon#read 6, iclass 24, count 0 2006.197.07:48:40.92#ibcon#end of sib2, iclass 24, count 0 2006.197.07:48:40.92#ibcon#*mode == 0, iclass 24, count 0 2006.197.07:48:40.92#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.197.07:48:40.92#ibcon#[28=FRQ=03,656.99\r\n] 2006.197.07:48:40.92#ibcon#*before write, iclass 24, count 0 2006.197.07:48:40.92#ibcon#enter sib2, iclass 24, count 0 2006.197.07:48:40.92#ibcon#flushed, iclass 24, count 0 2006.197.07:48:40.92#ibcon#about to write, iclass 24, count 0 2006.197.07:48:40.92#ibcon#wrote, iclass 24, count 0 2006.197.07:48:40.92#ibcon#about to read 3, iclass 24, count 0 2006.197.07:48:40.96#ibcon#read 3, iclass 24, count 0 2006.197.07:48:40.96#ibcon#about to read 4, iclass 24, count 0 2006.197.07:48:40.96#ibcon#read 4, iclass 24, count 0 2006.197.07:48:40.96#ibcon#about to read 5, iclass 24, count 0 2006.197.07:48:40.96#ibcon#read 5, iclass 24, count 0 2006.197.07:48:40.96#ibcon#about to read 6, iclass 24, count 0 2006.197.07:48:40.96#ibcon#read 6, iclass 24, count 0 2006.197.07:48:40.96#ibcon#end of sib2, iclass 24, count 0 2006.197.07:48:40.96#ibcon#*after write, iclass 24, count 0 2006.197.07:48:40.96#ibcon#*before return 0, iclass 24, count 0 2006.197.07:48:40.96#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.197.07:48:40.96#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.197.07:48:40.96#ibcon#about to clear, iclass 24 cls_cnt 0 2006.197.07:48:40.96#ibcon#cleared, iclass 24 cls_cnt 0 2006.197.07:48:40.96$vc4f8/vb=3,4 2006.197.07:48:40.96#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.197.07:48:40.96#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.197.07:48:40.96#ibcon#ireg 11 cls_cnt 2 2006.197.07:48:40.96#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.197.07:48:41.02#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.197.07:48:41.02#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.197.07:48:41.02#ibcon#enter wrdev, iclass 26, count 2 2006.197.07:48:41.02#ibcon#first serial, iclass 26, count 2 2006.197.07:48:41.02#ibcon#enter sib2, iclass 26, count 2 2006.197.07:48:41.02#ibcon#flushed, iclass 26, count 2 2006.197.07:48:41.02#ibcon#about to write, iclass 26, count 2 2006.197.07:48:41.02#ibcon#wrote, iclass 26, count 2 2006.197.07:48:41.02#ibcon#about to read 3, iclass 26, count 2 2006.197.07:48:41.04#ibcon#read 3, iclass 26, count 2 2006.197.07:48:41.04#ibcon#about to read 4, iclass 26, count 2 2006.197.07:48:41.04#ibcon#read 4, iclass 26, count 2 2006.197.07:48:41.04#ibcon#about to read 5, iclass 26, count 2 2006.197.07:48:41.04#ibcon#read 5, iclass 26, count 2 2006.197.07:48:41.04#ibcon#about to read 6, iclass 26, count 2 2006.197.07:48:41.04#ibcon#read 6, iclass 26, count 2 2006.197.07:48:41.04#ibcon#end of sib2, iclass 26, count 2 2006.197.07:48:41.04#ibcon#*mode == 0, iclass 26, count 2 2006.197.07:48:41.04#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.197.07:48:41.04#ibcon#[27=AT03-04\r\n] 2006.197.07:48:41.04#ibcon#*before write, iclass 26, count 2 2006.197.07:48:41.04#ibcon#enter sib2, iclass 26, count 2 2006.197.07:48:41.04#ibcon#flushed, iclass 26, count 2 2006.197.07:48:41.04#ibcon#about to write, iclass 26, count 2 2006.197.07:48:41.04#ibcon#wrote, iclass 26, count 2 2006.197.07:48:41.04#ibcon#about to read 3, iclass 26, count 2 2006.197.07:48:41.07#ibcon#read 3, iclass 26, count 2 2006.197.07:48:41.07#ibcon#about to read 4, iclass 26, count 2 2006.197.07:48:41.07#ibcon#read 4, iclass 26, count 2 2006.197.07:48:41.07#ibcon#about to read 5, iclass 26, count 2 2006.197.07:48:41.07#ibcon#read 5, iclass 26, count 2 2006.197.07:48:41.07#ibcon#about to read 6, iclass 26, count 2 2006.197.07:48:41.07#ibcon#read 6, iclass 26, count 2 2006.197.07:48:41.07#ibcon#end of sib2, iclass 26, count 2 2006.197.07:48:41.07#ibcon#*after write, iclass 26, count 2 2006.197.07:48:41.07#ibcon#*before return 0, iclass 26, count 2 2006.197.07:48:41.07#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.197.07:48:41.07#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.197.07:48:41.07#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.197.07:48:41.07#ibcon#ireg 7 cls_cnt 0 2006.197.07:48:41.07#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.197.07:48:41.19#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.197.07:48:41.19#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.197.07:48:41.19#ibcon#enter wrdev, iclass 26, count 0 2006.197.07:48:41.19#ibcon#first serial, iclass 26, count 0 2006.197.07:48:41.19#ibcon#enter sib2, iclass 26, count 0 2006.197.07:48:41.19#ibcon#flushed, iclass 26, count 0 2006.197.07:48:41.19#ibcon#about to write, iclass 26, count 0 2006.197.07:48:41.19#ibcon#wrote, iclass 26, count 0 2006.197.07:48:41.19#ibcon#about to read 3, iclass 26, count 0 2006.197.07:48:41.21#ibcon#read 3, iclass 26, count 0 2006.197.07:48:41.21#ibcon#about to read 4, iclass 26, count 0 2006.197.07:48:41.21#ibcon#read 4, iclass 26, count 0 2006.197.07:48:41.21#ibcon#about to read 5, iclass 26, count 0 2006.197.07:48:41.21#ibcon#read 5, iclass 26, count 0 2006.197.07:48:41.21#ibcon#about to read 6, iclass 26, count 0 2006.197.07:48:41.21#ibcon#read 6, iclass 26, count 0 2006.197.07:48:41.21#ibcon#end of sib2, iclass 26, count 0 2006.197.07:48:41.21#ibcon#*mode == 0, iclass 26, count 0 2006.197.07:48:41.21#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.197.07:48:41.21#ibcon#[27=USB\r\n] 2006.197.07:48:41.21#ibcon#*before write, iclass 26, count 0 2006.197.07:48:41.21#ibcon#enter sib2, iclass 26, count 0 2006.197.07:48:41.21#ibcon#flushed, iclass 26, count 0 2006.197.07:48:41.21#ibcon#about to write, iclass 26, count 0 2006.197.07:48:41.21#ibcon#wrote, iclass 26, count 0 2006.197.07:48:41.21#ibcon#about to read 3, iclass 26, count 0 2006.197.07:48:41.24#ibcon#read 3, iclass 26, count 0 2006.197.07:48:41.24#ibcon#about to read 4, iclass 26, count 0 2006.197.07:48:41.24#ibcon#read 4, iclass 26, count 0 2006.197.07:48:41.24#ibcon#about to read 5, iclass 26, count 0 2006.197.07:48:41.24#ibcon#read 5, iclass 26, count 0 2006.197.07:48:41.24#ibcon#about to read 6, iclass 26, count 0 2006.197.07:48:41.24#ibcon#read 6, iclass 26, count 0 2006.197.07:48:41.24#ibcon#end of sib2, iclass 26, count 0 2006.197.07:48:41.24#ibcon#*after write, iclass 26, count 0 2006.197.07:48:41.24#ibcon#*before return 0, iclass 26, count 0 2006.197.07:48:41.24#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.197.07:48:41.24#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.197.07:48:41.24#ibcon#about to clear, iclass 26 cls_cnt 0 2006.197.07:48:41.24#ibcon#cleared, iclass 26 cls_cnt 0 2006.197.07:48:41.24$vc4f8/vblo=4,712.99 2006.197.07:48:41.24#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.197.07:48:41.24#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.197.07:48:41.24#ibcon#ireg 17 cls_cnt 0 2006.197.07:48:41.24#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.197.07:48:41.24#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.197.07:48:41.24#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.197.07:48:41.24#ibcon#enter wrdev, iclass 28, count 0 2006.197.07:48:41.24#ibcon#first serial, iclass 28, count 0 2006.197.07:48:41.24#ibcon#enter sib2, iclass 28, count 0 2006.197.07:48:41.24#ibcon#flushed, iclass 28, count 0 2006.197.07:48:41.24#ibcon#about to write, iclass 28, count 0 2006.197.07:48:41.24#ibcon#wrote, iclass 28, count 0 2006.197.07:48:41.24#ibcon#about to read 3, iclass 28, count 0 2006.197.07:48:41.26#ibcon#read 3, iclass 28, count 0 2006.197.07:48:41.26#ibcon#about to read 4, iclass 28, count 0 2006.197.07:48:41.26#ibcon#read 4, iclass 28, count 0 2006.197.07:48:41.26#ibcon#about to read 5, iclass 28, count 0 2006.197.07:48:41.26#ibcon#read 5, iclass 28, count 0 2006.197.07:48:41.26#ibcon#about to read 6, iclass 28, count 0 2006.197.07:48:41.26#ibcon#read 6, iclass 28, count 0 2006.197.07:48:41.26#ibcon#end of sib2, iclass 28, count 0 2006.197.07:48:41.26#ibcon#*mode == 0, iclass 28, count 0 2006.197.07:48:41.26#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.197.07:48:41.26#ibcon#[28=FRQ=04,712.99\r\n] 2006.197.07:48:41.26#ibcon#*before write, iclass 28, count 0 2006.197.07:48:41.26#ibcon#enter sib2, iclass 28, count 0 2006.197.07:48:41.26#ibcon#flushed, iclass 28, count 0 2006.197.07:48:41.26#ibcon#about to write, iclass 28, count 0 2006.197.07:48:41.26#ibcon#wrote, iclass 28, count 0 2006.197.07:48:41.26#ibcon#about to read 3, iclass 28, count 0 2006.197.07:48:41.30#ibcon#read 3, iclass 28, count 0 2006.197.07:48:41.30#ibcon#about to read 4, iclass 28, count 0 2006.197.07:48:41.30#ibcon#read 4, iclass 28, count 0 2006.197.07:48:41.30#ibcon#about to read 5, iclass 28, count 0 2006.197.07:48:41.30#ibcon#read 5, iclass 28, count 0 2006.197.07:48:41.30#ibcon#about to read 6, iclass 28, count 0 2006.197.07:48:41.30#ibcon#read 6, iclass 28, count 0 2006.197.07:48:41.30#ibcon#end of sib2, iclass 28, count 0 2006.197.07:48:41.30#ibcon#*after write, iclass 28, count 0 2006.197.07:48:41.30#ibcon#*before return 0, iclass 28, count 0 2006.197.07:48:41.30#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.197.07:48:41.30#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.197.07:48:41.30#ibcon#about to clear, iclass 28 cls_cnt 0 2006.197.07:48:41.30#ibcon#cleared, iclass 28 cls_cnt 0 2006.197.07:48:41.30$vc4f8/vb=4,4 2006.197.07:48:41.30#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.197.07:48:41.30#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.197.07:48:41.30#ibcon#ireg 11 cls_cnt 2 2006.197.07:48:41.30#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.197.07:48:41.36#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.197.07:48:41.36#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.197.07:48:41.36#ibcon#enter wrdev, iclass 30, count 2 2006.197.07:48:41.36#ibcon#first serial, iclass 30, count 2 2006.197.07:48:41.36#ibcon#enter sib2, iclass 30, count 2 2006.197.07:48:41.36#ibcon#flushed, iclass 30, count 2 2006.197.07:48:41.36#ibcon#about to write, iclass 30, count 2 2006.197.07:48:41.36#ibcon#wrote, iclass 30, count 2 2006.197.07:48:41.36#ibcon#about to read 3, iclass 30, count 2 2006.197.07:48:41.38#ibcon#read 3, iclass 30, count 2 2006.197.07:48:41.38#ibcon#about to read 4, iclass 30, count 2 2006.197.07:48:41.38#ibcon#read 4, iclass 30, count 2 2006.197.07:48:41.38#ibcon#about to read 5, iclass 30, count 2 2006.197.07:48:41.38#ibcon#read 5, iclass 30, count 2 2006.197.07:48:41.38#ibcon#about to read 6, iclass 30, count 2 2006.197.07:48:41.38#ibcon#read 6, iclass 30, count 2 2006.197.07:48:41.38#ibcon#end of sib2, iclass 30, count 2 2006.197.07:48:41.38#ibcon#*mode == 0, iclass 30, count 2 2006.197.07:48:41.38#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.197.07:48:41.38#ibcon#[27=AT04-04\r\n] 2006.197.07:48:41.38#ibcon#*before write, iclass 30, count 2 2006.197.07:48:41.38#ibcon#enter sib2, iclass 30, count 2 2006.197.07:48:41.38#ibcon#flushed, iclass 30, count 2 2006.197.07:48:41.38#ibcon#about to write, iclass 30, count 2 2006.197.07:48:41.38#ibcon#wrote, iclass 30, count 2 2006.197.07:48:41.38#ibcon#about to read 3, iclass 30, count 2 2006.197.07:48:41.41#ibcon#read 3, iclass 30, count 2 2006.197.07:48:41.41#ibcon#about to read 4, iclass 30, count 2 2006.197.07:48:41.41#ibcon#read 4, iclass 30, count 2 2006.197.07:48:41.41#ibcon#about to read 5, iclass 30, count 2 2006.197.07:48:41.41#ibcon#read 5, iclass 30, count 2 2006.197.07:48:41.41#ibcon#about to read 6, iclass 30, count 2 2006.197.07:48:41.41#ibcon#read 6, iclass 30, count 2 2006.197.07:48:41.41#ibcon#end of sib2, iclass 30, count 2 2006.197.07:48:41.41#ibcon#*after write, iclass 30, count 2 2006.197.07:48:41.41#ibcon#*before return 0, iclass 30, count 2 2006.197.07:48:41.41#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.197.07:48:41.41#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.197.07:48:41.41#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.197.07:48:41.41#ibcon#ireg 7 cls_cnt 0 2006.197.07:48:41.41#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.197.07:48:41.53#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.197.07:48:41.53#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.197.07:48:41.53#ibcon#enter wrdev, iclass 30, count 0 2006.197.07:48:41.53#ibcon#first serial, iclass 30, count 0 2006.197.07:48:41.53#ibcon#enter sib2, iclass 30, count 0 2006.197.07:48:41.53#ibcon#flushed, iclass 30, count 0 2006.197.07:48:41.53#ibcon#about to write, iclass 30, count 0 2006.197.07:48:41.53#ibcon#wrote, iclass 30, count 0 2006.197.07:48:41.53#ibcon#about to read 3, iclass 30, count 0 2006.197.07:48:41.55#ibcon#read 3, iclass 30, count 0 2006.197.07:48:41.55#ibcon#about to read 4, iclass 30, count 0 2006.197.07:48:41.55#ibcon#read 4, iclass 30, count 0 2006.197.07:48:41.55#ibcon#about to read 5, iclass 30, count 0 2006.197.07:48:41.55#ibcon#read 5, iclass 30, count 0 2006.197.07:48:41.55#ibcon#about to read 6, iclass 30, count 0 2006.197.07:48:41.55#ibcon#read 6, iclass 30, count 0 2006.197.07:48:41.55#ibcon#end of sib2, iclass 30, count 0 2006.197.07:48:41.55#ibcon#*mode == 0, iclass 30, count 0 2006.197.07:48:41.55#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.197.07:48:41.55#ibcon#[27=USB\r\n] 2006.197.07:48:41.55#ibcon#*before write, iclass 30, count 0 2006.197.07:48:41.55#ibcon#enter sib2, iclass 30, count 0 2006.197.07:48:41.55#ibcon#flushed, iclass 30, count 0 2006.197.07:48:41.55#ibcon#about to write, iclass 30, count 0 2006.197.07:48:41.55#ibcon#wrote, iclass 30, count 0 2006.197.07:48:41.55#ibcon#about to read 3, iclass 30, count 0 2006.197.07:48:41.58#ibcon#read 3, iclass 30, count 0 2006.197.07:48:41.58#ibcon#about to read 4, iclass 30, count 0 2006.197.07:48:41.58#ibcon#read 4, iclass 30, count 0 2006.197.07:48:41.58#ibcon#about to read 5, iclass 30, count 0 2006.197.07:48:41.58#ibcon#read 5, iclass 30, count 0 2006.197.07:48:41.58#ibcon#about to read 6, iclass 30, count 0 2006.197.07:48:41.58#ibcon#read 6, iclass 30, count 0 2006.197.07:48:41.58#ibcon#end of sib2, iclass 30, count 0 2006.197.07:48:41.58#ibcon#*after write, iclass 30, count 0 2006.197.07:48:41.58#ibcon#*before return 0, iclass 30, count 0 2006.197.07:48:41.58#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.197.07:48:41.58#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.197.07:48:41.58#ibcon#about to clear, iclass 30 cls_cnt 0 2006.197.07:48:41.58#ibcon#cleared, iclass 30 cls_cnt 0 2006.197.07:48:41.58$vc4f8/vblo=5,744.99 2006.197.07:48:41.58#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.197.07:48:41.58#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.197.07:48:41.58#ibcon#ireg 17 cls_cnt 0 2006.197.07:48:41.58#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.197.07:48:41.58#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.197.07:48:41.58#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.197.07:48:41.58#ibcon#enter wrdev, iclass 32, count 0 2006.197.07:48:41.58#ibcon#first serial, iclass 32, count 0 2006.197.07:48:41.58#ibcon#enter sib2, iclass 32, count 0 2006.197.07:48:41.58#ibcon#flushed, iclass 32, count 0 2006.197.07:48:41.58#ibcon#about to write, iclass 32, count 0 2006.197.07:48:41.58#ibcon#wrote, iclass 32, count 0 2006.197.07:48:41.58#ibcon#about to read 3, iclass 32, count 0 2006.197.07:48:41.60#ibcon#read 3, iclass 32, count 0 2006.197.07:48:41.60#ibcon#about to read 4, iclass 32, count 0 2006.197.07:48:41.60#ibcon#read 4, iclass 32, count 0 2006.197.07:48:41.60#ibcon#about to read 5, iclass 32, count 0 2006.197.07:48:41.60#ibcon#read 5, iclass 32, count 0 2006.197.07:48:41.60#ibcon#about to read 6, iclass 32, count 0 2006.197.07:48:41.60#ibcon#read 6, iclass 32, count 0 2006.197.07:48:41.60#ibcon#end of sib2, iclass 32, count 0 2006.197.07:48:41.60#ibcon#*mode == 0, iclass 32, count 0 2006.197.07:48:41.60#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.197.07:48:41.60#ibcon#[28=FRQ=05,744.99\r\n] 2006.197.07:48:41.60#ibcon#*before write, iclass 32, count 0 2006.197.07:48:41.60#ibcon#enter sib2, iclass 32, count 0 2006.197.07:48:41.60#ibcon#flushed, iclass 32, count 0 2006.197.07:48:41.60#ibcon#about to write, iclass 32, count 0 2006.197.07:48:41.60#ibcon#wrote, iclass 32, count 0 2006.197.07:48:41.60#ibcon#about to read 3, iclass 32, count 0 2006.197.07:48:41.64#ibcon#read 3, iclass 32, count 0 2006.197.07:48:41.64#ibcon#about to read 4, iclass 32, count 0 2006.197.07:48:41.64#ibcon#read 4, iclass 32, count 0 2006.197.07:48:41.64#ibcon#about to read 5, iclass 32, count 0 2006.197.07:48:41.64#ibcon#read 5, iclass 32, count 0 2006.197.07:48:41.64#ibcon#about to read 6, iclass 32, count 0 2006.197.07:48:41.64#ibcon#read 6, iclass 32, count 0 2006.197.07:48:41.64#ibcon#end of sib2, iclass 32, count 0 2006.197.07:48:41.64#ibcon#*after write, iclass 32, count 0 2006.197.07:48:41.64#ibcon#*before return 0, iclass 32, count 0 2006.197.07:48:41.64#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.197.07:48:41.64#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.197.07:48:41.64#ibcon#about to clear, iclass 32 cls_cnt 0 2006.197.07:48:41.64#ibcon#cleared, iclass 32 cls_cnt 0 2006.197.07:48:41.64$vc4f8/vb=5,4 2006.197.07:48:41.64#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.197.07:48:41.64#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.197.07:48:41.64#ibcon#ireg 11 cls_cnt 2 2006.197.07:48:41.64#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.197.07:48:41.70#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.197.07:48:41.70#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.197.07:48:41.70#ibcon#enter wrdev, iclass 34, count 2 2006.197.07:48:41.70#ibcon#first serial, iclass 34, count 2 2006.197.07:48:41.70#ibcon#enter sib2, iclass 34, count 2 2006.197.07:48:41.70#ibcon#flushed, iclass 34, count 2 2006.197.07:48:41.70#ibcon#about to write, iclass 34, count 2 2006.197.07:48:41.70#ibcon#wrote, iclass 34, count 2 2006.197.07:48:41.70#ibcon#about to read 3, iclass 34, count 2 2006.197.07:48:41.72#ibcon#read 3, iclass 34, count 2 2006.197.07:48:41.72#ibcon#about to read 4, iclass 34, count 2 2006.197.07:48:41.72#ibcon#read 4, iclass 34, count 2 2006.197.07:48:41.72#ibcon#about to read 5, iclass 34, count 2 2006.197.07:48:41.72#ibcon#read 5, iclass 34, count 2 2006.197.07:48:41.72#ibcon#about to read 6, iclass 34, count 2 2006.197.07:48:41.72#ibcon#read 6, iclass 34, count 2 2006.197.07:48:41.72#ibcon#end of sib2, iclass 34, count 2 2006.197.07:48:41.72#ibcon#*mode == 0, iclass 34, count 2 2006.197.07:48:41.72#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.197.07:48:41.72#ibcon#[27=AT05-04\r\n] 2006.197.07:48:41.72#ibcon#*before write, iclass 34, count 2 2006.197.07:48:41.72#ibcon#enter sib2, iclass 34, count 2 2006.197.07:48:41.72#ibcon#flushed, iclass 34, count 2 2006.197.07:48:41.72#ibcon#about to write, iclass 34, count 2 2006.197.07:48:41.72#ibcon#wrote, iclass 34, count 2 2006.197.07:48:41.72#ibcon#about to read 3, iclass 34, count 2 2006.197.07:48:41.75#ibcon#read 3, iclass 34, count 2 2006.197.07:48:41.75#ibcon#about to read 4, iclass 34, count 2 2006.197.07:48:41.75#ibcon#read 4, iclass 34, count 2 2006.197.07:48:41.75#ibcon#about to read 5, iclass 34, count 2 2006.197.07:48:41.75#ibcon#read 5, iclass 34, count 2 2006.197.07:48:41.75#ibcon#about to read 6, iclass 34, count 2 2006.197.07:48:41.75#ibcon#read 6, iclass 34, count 2 2006.197.07:48:41.75#ibcon#end of sib2, iclass 34, count 2 2006.197.07:48:41.75#ibcon#*after write, iclass 34, count 2 2006.197.07:48:41.75#ibcon#*before return 0, iclass 34, count 2 2006.197.07:48:41.75#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.197.07:48:41.75#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.197.07:48:41.75#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.197.07:48:41.75#ibcon#ireg 7 cls_cnt 0 2006.197.07:48:41.75#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.197.07:48:41.87#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.197.07:48:41.87#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.197.07:48:41.87#ibcon#enter wrdev, iclass 34, count 0 2006.197.07:48:41.87#ibcon#first serial, iclass 34, count 0 2006.197.07:48:41.87#ibcon#enter sib2, iclass 34, count 0 2006.197.07:48:41.87#ibcon#flushed, iclass 34, count 0 2006.197.07:48:41.87#ibcon#about to write, iclass 34, count 0 2006.197.07:48:41.87#ibcon#wrote, iclass 34, count 0 2006.197.07:48:41.87#ibcon#about to read 3, iclass 34, count 0 2006.197.07:48:41.89#ibcon#read 3, iclass 34, count 0 2006.197.07:48:41.89#ibcon#about to read 4, iclass 34, count 0 2006.197.07:48:41.89#ibcon#read 4, iclass 34, count 0 2006.197.07:48:41.89#ibcon#about to read 5, iclass 34, count 0 2006.197.07:48:41.89#ibcon#read 5, iclass 34, count 0 2006.197.07:48:41.89#ibcon#about to read 6, iclass 34, count 0 2006.197.07:48:41.89#ibcon#read 6, iclass 34, count 0 2006.197.07:48:41.89#ibcon#end of sib2, iclass 34, count 0 2006.197.07:48:41.89#ibcon#*mode == 0, iclass 34, count 0 2006.197.07:48:41.89#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.197.07:48:41.89#ibcon#[27=USB\r\n] 2006.197.07:48:41.89#ibcon#*before write, iclass 34, count 0 2006.197.07:48:41.89#ibcon#enter sib2, iclass 34, count 0 2006.197.07:48:41.89#ibcon#flushed, iclass 34, count 0 2006.197.07:48:41.89#ibcon#about to write, iclass 34, count 0 2006.197.07:48:41.89#ibcon#wrote, iclass 34, count 0 2006.197.07:48:41.89#ibcon#about to read 3, iclass 34, count 0 2006.197.07:48:41.92#ibcon#read 3, iclass 34, count 0 2006.197.07:48:41.92#ibcon#about to read 4, iclass 34, count 0 2006.197.07:48:41.92#ibcon#read 4, iclass 34, count 0 2006.197.07:48:41.92#ibcon#about to read 5, iclass 34, count 0 2006.197.07:48:41.92#ibcon#read 5, iclass 34, count 0 2006.197.07:48:41.92#ibcon#about to read 6, iclass 34, count 0 2006.197.07:48:41.92#ibcon#read 6, iclass 34, count 0 2006.197.07:48:41.92#ibcon#end of sib2, iclass 34, count 0 2006.197.07:48:41.92#ibcon#*after write, iclass 34, count 0 2006.197.07:48:41.92#ibcon#*before return 0, iclass 34, count 0 2006.197.07:48:41.92#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.197.07:48:41.92#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.197.07:48:41.92#ibcon#about to clear, iclass 34 cls_cnt 0 2006.197.07:48:41.92#ibcon#cleared, iclass 34 cls_cnt 0 2006.197.07:48:41.92$vc4f8/vblo=6,752.99 2006.197.07:48:41.92#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.197.07:48:41.92#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.197.07:48:41.92#ibcon#ireg 17 cls_cnt 0 2006.197.07:48:41.92#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.197.07:48:41.92#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.197.07:48:41.92#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.197.07:48:41.92#ibcon#enter wrdev, iclass 36, count 0 2006.197.07:48:41.92#ibcon#first serial, iclass 36, count 0 2006.197.07:48:41.92#ibcon#enter sib2, iclass 36, count 0 2006.197.07:48:41.92#ibcon#flushed, iclass 36, count 0 2006.197.07:48:41.92#ibcon#about to write, iclass 36, count 0 2006.197.07:48:41.92#ibcon#wrote, iclass 36, count 0 2006.197.07:48:41.92#ibcon#about to read 3, iclass 36, count 0 2006.197.07:48:41.94#ibcon#read 3, iclass 36, count 0 2006.197.07:48:41.94#ibcon#about to read 4, iclass 36, count 0 2006.197.07:48:41.94#ibcon#read 4, iclass 36, count 0 2006.197.07:48:41.94#ibcon#about to read 5, iclass 36, count 0 2006.197.07:48:41.94#ibcon#read 5, iclass 36, count 0 2006.197.07:48:41.94#ibcon#about to read 6, iclass 36, count 0 2006.197.07:48:41.94#ibcon#read 6, iclass 36, count 0 2006.197.07:48:41.94#ibcon#end of sib2, iclass 36, count 0 2006.197.07:48:41.94#ibcon#*mode == 0, iclass 36, count 0 2006.197.07:48:41.94#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.197.07:48:41.94#ibcon#[28=FRQ=06,752.99\r\n] 2006.197.07:48:41.94#ibcon#*before write, iclass 36, count 0 2006.197.07:48:41.94#ibcon#enter sib2, iclass 36, count 0 2006.197.07:48:41.94#ibcon#flushed, iclass 36, count 0 2006.197.07:48:41.94#ibcon#about to write, iclass 36, count 0 2006.197.07:48:41.94#ibcon#wrote, iclass 36, count 0 2006.197.07:48:41.94#ibcon#about to read 3, iclass 36, count 0 2006.197.07:48:41.98#ibcon#read 3, iclass 36, count 0 2006.197.07:48:41.98#ibcon#about to read 4, iclass 36, count 0 2006.197.07:48:41.98#ibcon#read 4, iclass 36, count 0 2006.197.07:48:41.98#ibcon#about to read 5, iclass 36, count 0 2006.197.07:48:41.98#ibcon#read 5, iclass 36, count 0 2006.197.07:48:41.98#ibcon#about to read 6, iclass 36, count 0 2006.197.07:48:41.98#ibcon#read 6, iclass 36, count 0 2006.197.07:48:41.98#ibcon#end of sib2, iclass 36, count 0 2006.197.07:48:41.98#ibcon#*after write, iclass 36, count 0 2006.197.07:48:41.98#ibcon#*before return 0, iclass 36, count 0 2006.197.07:48:41.98#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.197.07:48:41.98#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.197.07:48:41.98#ibcon#about to clear, iclass 36 cls_cnt 0 2006.197.07:48:41.98#ibcon#cleared, iclass 36 cls_cnt 0 2006.197.07:48:41.98$vc4f8/vb=6,4 2006.197.07:48:41.98#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.197.07:48:41.98#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.197.07:48:41.98#ibcon#ireg 11 cls_cnt 2 2006.197.07:48:41.98#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.197.07:48:42.04#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.197.07:48:42.04#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.197.07:48:42.04#ibcon#enter wrdev, iclass 38, count 2 2006.197.07:48:42.04#ibcon#first serial, iclass 38, count 2 2006.197.07:48:42.04#ibcon#enter sib2, iclass 38, count 2 2006.197.07:48:42.04#ibcon#flushed, iclass 38, count 2 2006.197.07:48:42.04#ibcon#about to write, iclass 38, count 2 2006.197.07:48:42.04#ibcon#wrote, iclass 38, count 2 2006.197.07:48:42.04#ibcon#about to read 3, iclass 38, count 2 2006.197.07:48:42.06#ibcon#read 3, iclass 38, count 2 2006.197.07:48:42.06#ibcon#about to read 4, iclass 38, count 2 2006.197.07:48:42.06#ibcon#read 4, iclass 38, count 2 2006.197.07:48:42.06#ibcon#about to read 5, iclass 38, count 2 2006.197.07:48:42.06#ibcon#read 5, iclass 38, count 2 2006.197.07:48:42.06#ibcon#about to read 6, iclass 38, count 2 2006.197.07:48:42.06#ibcon#read 6, iclass 38, count 2 2006.197.07:48:42.06#ibcon#end of sib2, iclass 38, count 2 2006.197.07:48:42.06#ibcon#*mode == 0, iclass 38, count 2 2006.197.07:48:42.06#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.197.07:48:42.06#ibcon#[27=AT06-04\r\n] 2006.197.07:48:42.06#ibcon#*before write, iclass 38, count 2 2006.197.07:48:42.06#ibcon#enter sib2, iclass 38, count 2 2006.197.07:48:42.06#ibcon#flushed, iclass 38, count 2 2006.197.07:48:42.06#ibcon#about to write, iclass 38, count 2 2006.197.07:48:42.06#ibcon#wrote, iclass 38, count 2 2006.197.07:48:42.06#ibcon#about to read 3, iclass 38, count 2 2006.197.07:48:42.09#ibcon#read 3, iclass 38, count 2 2006.197.07:48:42.09#ibcon#about to read 4, iclass 38, count 2 2006.197.07:48:42.09#ibcon#read 4, iclass 38, count 2 2006.197.07:48:42.09#ibcon#about to read 5, iclass 38, count 2 2006.197.07:48:42.09#ibcon#read 5, iclass 38, count 2 2006.197.07:48:42.09#ibcon#about to read 6, iclass 38, count 2 2006.197.07:48:42.09#ibcon#read 6, iclass 38, count 2 2006.197.07:48:42.09#ibcon#end of sib2, iclass 38, count 2 2006.197.07:48:42.09#ibcon#*after write, iclass 38, count 2 2006.197.07:48:42.09#ibcon#*before return 0, iclass 38, count 2 2006.197.07:48:42.09#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.197.07:48:42.09#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.197.07:48:42.09#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.197.07:48:42.09#ibcon#ireg 7 cls_cnt 0 2006.197.07:48:42.09#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.197.07:48:42.21#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.197.07:48:42.21#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.197.07:48:42.21#ibcon#enter wrdev, iclass 38, count 0 2006.197.07:48:42.21#ibcon#first serial, iclass 38, count 0 2006.197.07:48:42.21#ibcon#enter sib2, iclass 38, count 0 2006.197.07:48:42.21#ibcon#flushed, iclass 38, count 0 2006.197.07:48:42.21#ibcon#about to write, iclass 38, count 0 2006.197.07:48:42.21#ibcon#wrote, iclass 38, count 0 2006.197.07:48:42.21#ibcon#about to read 3, iclass 38, count 0 2006.197.07:48:42.23#ibcon#read 3, iclass 38, count 0 2006.197.07:48:42.23#ibcon#about to read 4, iclass 38, count 0 2006.197.07:48:42.23#ibcon#read 4, iclass 38, count 0 2006.197.07:48:42.23#ibcon#about to read 5, iclass 38, count 0 2006.197.07:48:42.23#ibcon#read 5, iclass 38, count 0 2006.197.07:48:42.23#ibcon#about to read 6, iclass 38, count 0 2006.197.07:48:42.23#ibcon#read 6, iclass 38, count 0 2006.197.07:48:42.23#ibcon#end of sib2, iclass 38, count 0 2006.197.07:48:42.23#ibcon#*mode == 0, iclass 38, count 0 2006.197.07:48:42.23#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.197.07:48:42.23#ibcon#[27=USB\r\n] 2006.197.07:48:42.23#ibcon#*before write, iclass 38, count 0 2006.197.07:48:42.23#ibcon#enter sib2, iclass 38, count 0 2006.197.07:48:42.23#ibcon#flushed, iclass 38, count 0 2006.197.07:48:42.23#ibcon#about to write, iclass 38, count 0 2006.197.07:48:42.23#ibcon#wrote, iclass 38, count 0 2006.197.07:48:42.23#ibcon#about to read 3, iclass 38, count 0 2006.197.07:48:42.26#ibcon#read 3, iclass 38, count 0 2006.197.07:48:42.26#ibcon#about to read 4, iclass 38, count 0 2006.197.07:48:42.26#ibcon#read 4, iclass 38, count 0 2006.197.07:48:42.26#ibcon#about to read 5, iclass 38, count 0 2006.197.07:48:42.26#ibcon#read 5, iclass 38, count 0 2006.197.07:48:42.26#ibcon#about to read 6, iclass 38, count 0 2006.197.07:48:42.26#ibcon#read 6, iclass 38, count 0 2006.197.07:48:42.26#ibcon#end of sib2, iclass 38, count 0 2006.197.07:48:42.26#ibcon#*after write, iclass 38, count 0 2006.197.07:48:42.26#ibcon#*before return 0, iclass 38, count 0 2006.197.07:48:42.26#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.197.07:48:42.26#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.197.07:48:42.26#ibcon#about to clear, iclass 38 cls_cnt 0 2006.197.07:48:42.26#ibcon#cleared, iclass 38 cls_cnt 0 2006.197.07:48:42.26$vc4f8/vabw=wide 2006.197.07:48:42.26#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.197.07:48:42.26#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.197.07:48:42.26#ibcon#ireg 8 cls_cnt 0 2006.197.07:48:42.26#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.197.07:48:42.26#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.197.07:48:42.26#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.197.07:48:42.26#ibcon#enter wrdev, iclass 40, count 0 2006.197.07:48:42.26#ibcon#first serial, iclass 40, count 0 2006.197.07:48:42.26#ibcon#enter sib2, iclass 40, count 0 2006.197.07:48:42.26#ibcon#flushed, iclass 40, count 0 2006.197.07:48:42.26#ibcon#about to write, iclass 40, count 0 2006.197.07:48:42.26#ibcon#wrote, iclass 40, count 0 2006.197.07:48:42.26#ibcon#about to read 3, iclass 40, count 0 2006.197.07:48:42.28#ibcon#read 3, iclass 40, count 0 2006.197.07:48:42.28#ibcon#about to read 4, iclass 40, count 0 2006.197.07:48:42.28#ibcon#read 4, iclass 40, count 0 2006.197.07:48:42.28#ibcon#about to read 5, iclass 40, count 0 2006.197.07:48:42.28#ibcon#read 5, iclass 40, count 0 2006.197.07:48:42.28#ibcon#about to read 6, iclass 40, count 0 2006.197.07:48:42.28#ibcon#read 6, iclass 40, count 0 2006.197.07:48:42.28#ibcon#end of sib2, iclass 40, count 0 2006.197.07:48:42.28#ibcon#*mode == 0, iclass 40, count 0 2006.197.07:48:42.28#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.197.07:48:42.28#ibcon#[25=BW32\r\n] 2006.197.07:48:42.28#ibcon#*before write, iclass 40, count 0 2006.197.07:48:42.28#ibcon#enter sib2, iclass 40, count 0 2006.197.07:48:42.28#ibcon#flushed, iclass 40, count 0 2006.197.07:48:42.28#ibcon#about to write, iclass 40, count 0 2006.197.07:48:42.28#ibcon#wrote, iclass 40, count 0 2006.197.07:48:42.28#ibcon#about to read 3, iclass 40, count 0 2006.197.07:48:42.31#ibcon#read 3, iclass 40, count 0 2006.197.07:48:42.31#ibcon#about to read 4, iclass 40, count 0 2006.197.07:48:42.31#ibcon#read 4, iclass 40, count 0 2006.197.07:48:42.31#ibcon#about to read 5, iclass 40, count 0 2006.197.07:48:42.31#ibcon#read 5, iclass 40, count 0 2006.197.07:48:42.31#ibcon#about to read 6, iclass 40, count 0 2006.197.07:48:42.31#ibcon#read 6, iclass 40, count 0 2006.197.07:48:42.31#ibcon#end of sib2, iclass 40, count 0 2006.197.07:48:42.31#ibcon#*after write, iclass 40, count 0 2006.197.07:48:42.31#ibcon#*before return 0, iclass 40, count 0 2006.197.07:48:42.31#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.197.07:48:42.31#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.197.07:48:42.31#ibcon#about to clear, iclass 40 cls_cnt 0 2006.197.07:48:42.31#ibcon#cleared, iclass 40 cls_cnt 0 2006.197.07:48:42.31$vc4f8/vbbw=wide 2006.197.07:48:42.31#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.197.07:48:42.31#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.197.07:48:42.31#ibcon#ireg 8 cls_cnt 0 2006.197.07:48:42.31#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.197.07:48:42.38#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.197.07:48:42.38#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.197.07:48:42.38#ibcon#enter wrdev, iclass 4, count 0 2006.197.07:48:42.38#ibcon#first serial, iclass 4, count 0 2006.197.07:48:42.38#ibcon#enter sib2, iclass 4, count 0 2006.197.07:48:42.38#ibcon#flushed, iclass 4, count 0 2006.197.07:48:42.38#ibcon#about to write, iclass 4, count 0 2006.197.07:48:42.38#ibcon#wrote, iclass 4, count 0 2006.197.07:48:42.38#ibcon#about to read 3, iclass 4, count 0 2006.197.07:48:42.40#ibcon#read 3, iclass 4, count 0 2006.197.07:48:42.40#ibcon#about to read 4, iclass 4, count 0 2006.197.07:48:42.40#ibcon#read 4, iclass 4, count 0 2006.197.07:48:42.40#ibcon#about to read 5, iclass 4, count 0 2006.197.07:48:42.40#ibcon#read 5, iclass 4, count 0 2006.197.07:48:42.40#ibcon#about to read 6, iclass 4, count 0 2006.197.07:48:42.40#ibcon#read 6, iclass 4, count 0 2006.197.07:48:42.40#ibcon#end of sib2, iclass 4, count 0 2006.197.07:48:42.40#ibcon#*mode == 0, iclass 4, count 0 2006.197.07:48:42.40#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.197.07:48:42.40#ibcon#[27=BW32\r\n] 2006.197.07:48:42.40#ibcon#*before write, iclass 4, count 0 2006.197.07:48:42.40#ibcon#enter sib2, iclass 4, count 0 2006.197.07:48:42.40#ibcon#flushed, iclass 4, count 0 2006.197.07:48:42.40#ibcon#about to write, iclass 4, count 0 2006.197.07:48:42.40#ibcon#wrote, iclass 4, count 0 2006.197.07:48:42.40#ibcon#about to read 3, iclass 4, count 0 2006.197.07:48:42.43#ibcon#read 3, iclass 4, count 0 2006.197.07:48:42.43#ibcon#about to read 4, iclass 4, count 0 2006.197.07:48:42.43#ibcon#read 4, iclass 4, count 0 2006.197.07:48:42.43#ibcon#about to read 5, iclass 4, count 0 2006.197.07:48:42.43#ibcon#read 5, iclass 4, count 0 2006.197.07:48:42.43#ibcon#about to read 6, iclass 4, count 0 2006.197.07:48:42.43#ibcon#read 6, iclass 4, count 0 2006.197.07:48:42.43#ibcon#end of sib2, iclass 4, count 0 2006.197.07:48:42.43#ibcon#*after write, iclass 4, count 0 2006.197.07:48:42.43#ibcon#*before return 0, iclass 4, count 0 2006.197.07:48:42.43#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.197.07:48:42.43#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.197.07:48:42.43#ibcon#about to clear, iclass 4 cls_cnt 0 2006.197.07:48:42.43#ibcon#cleared, iclass 4 cls_cnt 0 2006.197.07:48:42.43$4f8m12a/ifd4f 2006.197.07:48:42.43$ifd4f/lo= 2006.197.07:48:42.43$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.197.07:48:42.43$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.197.07:48:42.43$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.197.07:48:42.43$ifd4f/patch= 2006.197.07:48:42.43$ifd4f/patch=lo1,a1,a2,a3,a4 2006.197.07:48:42.43$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.197.07:48:42.43$ifd4f/patch=lo3,a5,a6,a7,a8 2006.197.07:48:42.43$4f8m12a/"form=m,16.000,1:2 2006.197.07:48:42.43$4f8m12a/"tpicd 2006.197.07:48:42.43$4f8m12a/echo=off 2006.197.07:48:42.43$4f8m12a/xlog=off 2006.197.07:48:42.43:!2006.197.07:49:10 2006.197.07:48:54.14#trakl#Source acquired 2006.197.07:48:55.14#flagr#flagr/antenna,acquired 2006.197.07:49:10.00:preob 2006.197.07:49:11.14/onsource/TRACKING 2006.197.07:49:11.14:!2006.197.07:49:20 2006.197.07:49:20.00:data_valid=on 2006.197.07:49:20.00:midob 2006.197.07:49:20.14/onsource/TRACKING 2006.197.07:49:20.14/wx/25.80,1003.1,97 2006.197.07:49:20.26/cable/+6.3738E-03 2006.197.07:49:21.35/va/01,08,usb,yes,28,30 2006.197.07:49:21.35/va/02,07,usb,yes,29,30 2006.197.07:49:21.35/va/03,06,usb,yes,30,30 2006.197.07:49:21.35/va/04,07,usb,yes,29,32 2006.197.07:49:21.35/va/05,07,usb,yes,33,35 2006.197.07:49:21.35/va/06,06,usb,yes,32,32 2006.197.07:49:21.35/va/07,06,usb,yes,32,32 2006.197.07:49:21.35/va/08,07,usb,yes,31,30 2006.197.07:49:21.58/valo/01,532.99,yes,locked 2006.197.07:49:21.58/valo/02,572.99,yes,locked 2006.197.07:49:21.58/valo/03,672.99,yes,locked 2006.197.07:49:21.58/valo/04,832.99,yes,locked 2006.197.07:49:21.58/valo/05,652.99,yes,locked 2006.197.07:49:21.58/valo/06,772.99,yes,locked 2006.197.07:49:21.58/valo/07,832.99,yes,locked 2006.197.07:49:21.58/valo/08,852.99,yes,locked 2006.197.07:49:22.67/vb/01,04,usb,yes,28,27 2006.197.07:49:22.67/vb/02,04,usb,yes,30,32 2006.197.07:49:22.67/vb/03,04,usb,yes,27,30 2006.197.07:49:22.67/vb/04,04,usb,yes,27,28 2006.197.07:49:22.67/vb/05,04,usb,yes,26,30 2006.197.07:49:22.67/vb/06,04,usb,yes,27,30 2006.197.07:49:22.67/vb/07,04,usb,yes,29,29 2006.197.07:49:22.67/vb/08,04,usb,yes,27,30 2006.197.07:49:22.91/vblo/01,632.99,yes,locked 2006.197.07:49:22.91/vblo/02,640.99,yes,locked 2006.197.07:49:22.91/vblo/03,656.99,yes,locked 2006.197.07:49:22.91/vblo/04,712.99,yes,locked 2006.197.07:49:22.91/vblo/05,744.99,yes,locked 2006.197.07:49:22.91/vblo/06,752.99,yes,locked 2006.197.07:49:22.91/vblo/07,734.99,yes,locked 2006.197.07:49:22.91/vblo/08,744.99,yes,locked 2006.197.07:49:23.06/vabw/8 2006.197.07:49:23.21/vbbw/8 2006.197.07:49:23.30/xfe/off,on,15.0 2006.197.07:49:23.67/ifatt/23,28,28,28 2006.197.07:49:24.10/fmout-gps/S +2.98E-07 2006.197.07:49:24.13:!2006.197.07:50:20 2006.197.07:50:20.00:data_valid=off 2006.197.07:50:20.00:postob 2006.197.07:50:20.17/cable/+6.3691E-03 2006.197.07:50:20.17/wx/25.79,1003.1,97 2006.197.07:50:21.10/fmout-gps/S +2.99E-07 2006.197.07:50:21.10:scan_name=197-0751,k06197,60 2006.197.07:50:21.10:source=1418+546,141946.60,542314.8,2000.0,cw 2006.197.07:50:21.14#flagr#flagr/antenna,new-source 2006.197.07:50:22.14:checkk5 2006.197.07:50:22.47/chk_autoobs//k5ts1/ autoobs is running! 2006.197.07:50:22.82/chk_autoobs//k5ts2/ autoobs is running! 2006.197.07:50:23.16/chk_autoobs//k5ts3/ autoobs is running! 2006.197.07:50:23.51/chk_autoobs//k5ts4/ autoobs is running! 2006.197.07:50:23.84/chk_obsdata//k5ts1/T1970749??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.07:50:24.15/chk_obsdata//k5ts2/T1970749??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.07:50:24.49/chk_obsdata//k5ts3/T1970749??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.07:50:24.82/chk_obsdata//k5ts4/T1970749??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.07:50:25.49/k5log//k5ts1_log_newline 2006.197.07:50:26.18/k5log//k5ts2_log_newline 2006.197.07:50:26.85/k5log//k5ts3_log_newline 2006.197.07:50:27.51/k5log//k5ts4_log_newline 2006.197.07:50:27.54/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.197.07:50:27.54:4f8m12a=1 2006.197.07:50:27.54$4f8m12a/echo=on 2006.197.07:50:27.54$4f8m12a/pcalon 2006.197.07:50:27.54$pcalon/"no phase cal control is implemented here 2006.197.07:50:27.54$4f8m12a/"tpicd=stop 2006.197.07:50:27.54$4f8m12a/vc4f8 2006.197.07:50:27.54$vc4f8/valo=1,532.99 2006.197.07:50:27.54#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.197.07:50:27.54#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.197.07:50:27.54#ibcon#ireg 17 cls_cnt 0 2006.197.07:50:27.54#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.197.07:50:27.54#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.197.07:50:27.54#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.197.07:50:27.54#ibcon#enter wrdev, iclass 13, count 0 2006.197.07:50:27.54#ibcon#first serial, iclass 13, count 0 2006.197.07:50:27.54#ibcon#enter sib2, iclass 13, count 0 2006.197.07:50:27.54#ibcon#flushed, iclass 13, count 0 2006.197.07:50:27.54#ibcon#about to write, iclass 13, count 0 2006.197.07:50:27.54#ibcon#wrote, iclass 13, count 0 2006.197.07:50:27.54#ibcon#about to read 3, iclass 13, count 0 2006.197.07:50:27.56#ibcon#read 3, iclass 13, count 0 2006.197.07:50:27.56#ibcon#about to read 4, iclass 13, count 0 2006.197.07:50:27.56#ibcon#read 4, iclass 13, count 0 2006.197.07:50:27.56#ibcon#about to read 5, iclass 13, count 0 2006.197.07:50:27.56#ibcon#read 5, iclass 13, count 0 2006.197.07:50:27.56#ibcon#about to read 6, iclass 13, count 0 2006.197.07:50:27.56#ibcon#read 6, iclass 13, count 0 2006.197.07:50:27.56#ibcon#end of sib2, iclass 13, count 0 2006.197.07:50:27.56#ibcon#*mode == 0, iclass 13, count 0 2006.197.07:50:27.56#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.197.07:50:27.56#ibcon#[26=FRQ=01,532.99\r\n] 2006.197.07:50:27.56#ibcon#*before write, iclass 13, count 0 2006.197.07:50:27.56#ibcon#enter sib2, iclass 13, count 0 2006.197.07:50:27.56#ibcon#flushed, iclass 13, count 0 2006.197.07:50:27.56#ibcon#about to write, iclass 13, count 0 2006.197.07:50:27.56#ibcon#wrote, iclass 13, count 0 2006.197.07:50:27.56#ibcon#about to read 3, iclass 13, count 0 2006.197.07:50:27.61#ibcon#read 3, iclass 13, count 0 2006.197.07:50:27.61#ibcon#about to read 4, iclass 13, count 0 2006.197.07:50:27.61#ibcon#read 4, iclass 13, count 0 2006.197.07:50:27.61#ibcon#about to read 5, iclass 13, count 0 2006.197.07:50:27.61#ibcon#read 5, iclass 13, count 0 2006.197.07:50:27.61#ibcon#about to read 6, iclass 13, count 0 2006.197.07:50:27.61#ibcon#read 6, iclass 13, count 0 2006.197.07:50:27.61#ibcon#end of sib2, iclass 13, count 0 2006.197.07:50:27.61#ibcon#*after write, iclass 13, count 0 2006.197.07:50:27.61#ibcon#*before return 0, iclass 13, count 0 2006.197.07:50:27.61#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.197.07:50:27.61#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.197.07:50:27.61#ibcon#about to clear, iclass 13 cls_cnt 0 2006.197.07:50:27.61#ibcon#cleared, iclass 13 cls_cnt 0 2006.197.07:50:27.61$vc4f8/va=1,8 2006.197.07:50:27.61#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.197.07:50:27.61#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.197.07:50:27.61#ibcon#ireg 11 cls_cnt 2 2006.197.07:50:27.61#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.197.07:50:27.61#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.197.07:50:27.61#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.197.07:50:27.61#ibcon#enter wrdev, iclass 15, count 2 2006.197.07:50:27.61#ibcon#first serial, iclass 15, count 2 2006.197.07:50:27.61#ibcon#enter sib2, iclass 15, count 2 2006.197.07:50:27.61#ibcon#flushed, iclass 15, count 2 2006.197.07:50:27.61#ibcon#about to write, iclass 15, count 2 2006.197.07:50:27.61#ibcon#wrote, iclass 15, count 2 2006.197.07:50:27.61#ibcon#about to read 3, iclass 15, count 2 2006.197.07:50:27.63#ibcon#read 3, iclass 15, count 2 2006.197.07:50:27.63#ibcon#about to read 4, iclass 15, count 2 2006.197.07:50:27.63#ibcon#read 4, iclass 15, count 2 2006.197.07:50:27.63#ibcon#about to read 5, iclass 15, count 2 2006.197.07:50:27.63#ibcon#read 5, iclass 15, count 2 2006.197.07:50:27.63#ibcon#about to read 6, iclass 15, count 2 2006.197.07:50:27.63#ibcon#read 6, iclass 15, count 2 2006.197.07:50:27.63#ibcon#end of sib2, iclass 15, count 2 2006.197.07:50:27.63#ibcon#*mode == 0, iclass 15, count 2 2006.197.07:50:27.63#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.197.07:50:27.63#ibcon#[25=AT01-08\r\n] 2006.197.07:50:27.63#ibcon#*before write, iclass 15, count 2 2006.197.07:50:27.63#ibcon#enter sib2, iclass 15, count 2 2006.197.07:50:27.63#ibcon#flushed, iclass 15, count 2 2006.197.07:50:27.63#ibcon#about to write, iclass 15, count 2 2006.197.07:50:27.63#ibcon#wrote, iclass 15, count 2 2006.197.07:50:27.63#ibcon#about to read 3, iclass 15, count 2 2006.197.07:50:27.66#ibcon#read 3, iclass 15, count 2 2006.197.07:50:27.66#ibcon#about to read 4, iclass 15, count 2 2006.197.07:50:27.66#ibcon#read 4, iclass 15, count 2 2006.197.07:50:27.66#ibcon#about to read 5, iclass 15, count 2 2006.197.07:50:27.66#ibcon#read 5, iclass 15, count 2 2006.197.07:50:27.66#ibcon#about to read 6, iclass 15, count 2 2006.197.07:50:27.66#ibcon#read 6, iclass 15, count 2 2006.197.07:50:27.66#ibcon#end of sib2, iclass 15, count 2 2006.197.07:50:27.66#ibcon#*after write, iclass 15, count 2 2006.197.07:50:27.66#ibcon#*before return 0, iclass 15, count 2 2006.197.07:50:27.66#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.197.07:50:27.66#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.197.07:50:27.66#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.197.07:50:27.66#ibcon#ireg 7 cls_cnt 0 2006.197.07:50:27.66#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.197.07:50:27.78#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.197.07:50:27.78#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.197.07:50:27.78#ibcon#enter wrdev, iclass 15, count 0 2006.197.07:50:27.78#ibcon#first serial, iclass 15, count 0 2006.197.07:50:27.78#ibcon#enter sib2, iclass 15, count 0 2006.197.07:50:27.78#ibcon#flushed, iclass 15, count 0 2006.197.07:50:27.78#ibcon#about to write, iclass 15, count 0 2006.197.07:50:27.78#ibcon#wrote, iclass 15, count 0 2006.197.07:50:27.78#ibcon#about to read 3, iclass 15, count 0 2006.197.07:50:27.80#ibcon#read 3, iclass 15, count 0 2006.197.07:50:27.80#ibcon#about to read 4, iclass 15, count 0 2006.197.07:50:27.80#ibcon#read 4, iclass 15, count 0 2006.197.07:50:27.80#ibcon#about to read 5, iclass 15, count 0 2006.197.07:50:27.80#ibcon#read 5, iclass 15, count 0 2006.197.07:50:27.80#ibcon#about to read 6, iclass 15, count 0 2006.197.07:50:27.80#ibcon#read 6, iclass 15, count 0 2006.197.07:50:27.80#ibcon#end of sib2, iclass 15, count 0 2006.197.07:50:27.80#ibcon#*mode == 0, iclass 15, count 0 2006.197.07:50:27.80#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.197.07:50:27.80#ibcon#[25=USB\r\n] 2006.197.07:50:27.80#ibcon#*before write, iclass 15, count 0 2006.197.07:50:27.80#ibcon#enter sib2, iclass 15, count 0 2006.197.07:50:27.80#ibcon#flushed, iclass 15, count 0 2006.197.07:50:27.80#ibcon#about to write, iclass 15, count 0 2006.197.07:50:27.80#ibcon#wrote, iclass 15, count 0 2006.197.07:50:27.80#ibcon#about to read 3, iclass 15, count 0 2006.197.07:50:27.83#abcon#<5=/05 3.3 6.1 25.79 971003.1\r\n> 2006.197.07:50:27.83#ibcon#read 3, iclass 15, count 0 2006.197.07:50:27.83#ibcon#about to read 4, iclass 15, count 0 2006.197.07:50:27.83#ibcon#read 4, iclass 15, count 0 2006.197.07:50:27.83#ibcon#about to read 5, iclass 15, count 0 2006.197.07:50:27.83#ibcon#read 5, iclass 15, count 0 2006.197.07:50:27.83#ibcon#about to read 6, iclass 15, count 0 2006.197.07:50:27.83#ibcon#read 6, iclass 15, count 0 2006.197.07:50:27.83#ibcon#end of sib2, iclass 15, count 0 2006.197.07:50:27.83#ibcon#*after write, iclass 15, count 0 2006.197.07:50:27.83#ibcon#*before return 0, iclass 15, count 0 2006.197.07:50:27.83#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.197.07:50:27.83#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.197.07:50:27.83#ibcon#about to clear, iclass 15 cls_cnt 0 2006.197.07:50:27.83#ibcon#cleared, iclass 15 cls_cnt 0 2006.197.07:50:27.83$vc4f8/valo=2,572.99 2006.197.07:50:27.83#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.197.07:50:27.83#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.197.07:50:27.83#ibcon#ireg 17 cls_cnt 0 2006.197.07:50:27.83#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.197.07:50:27.83#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.197.07:50:27.83#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.197.07:50:27.83#ibcon#enter wrdev, iclass 20, count 0 2006.197.07:50:27.83#ibcon#first serial, iclass 20, count 0 2006.197.07:50:27.83#ibcon#enter sib2, iclass 20, count 0 2006.197.07:50:27.83#ibcon#flushed, iclass 20, count 0 2006.197.07:50:27.83#ibcon#about to write, iclass 20, count 0 2006.197.07:50:27.83#ibcon#wrote, iclass 20, count 0 2006.197.07:50:27.83#ibcon#about to read 3, iclass 20, count 0 2006.197.07:50:27.85#abcon#{5=INTERFACE CLEAR} 2006.197.07:50:27.85#ibcon#read 3, iclass 20, count 0 2006.197.07:50:27.85#ibcon#about to read 4, iclass 20, count 0 2006.197.07:50:27.85#ibcon#read 4, iclass 20, count 0 2006.197.07:50:27.85#ibcon#about to read 5, iclass 20, count 0 2006.197.07:50:27.85#ibcon#read 5, iclass 20, count 0 2006.197.07:50:27.85#ibcon#about to read 6, iclass 20, count 0 2006.197.07:50:27.85#ibcon#read 6, iclass 20, count 0 2006.197.07:50:27.85#ibcon#end of sib2, iclass 20, count 0 2006.197.07:50:27.85#ibcon#*mode == 0, iclass 20, count 0 2006.197.07:50:27.85#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.197.07:50:27.85#ibcon#[26=FRQ=02,572.99\r\n] 2006.197.07:50:27.85#ibcon#*before write, iclass 20, count 0 2006.197.07:50:27.85#ibcon#enter sib2, iclass 20, count 0 2006.197.07:50:27.85#ibcon#flushed, iclass 20, count 0 2006.197.07:50:27.85#ibcon#about to write, iclass 20, count 0 2006.197.07:50:27.85#ibcon#wrote, iclass 20, count 0 2006.197.07:50:27.85#ibcon#about to read 3, iclass 20, count 0 2006.197.07:50:27.89#ibcon#read 3, iclass 20, count 0 2006.197.07:50:27.89#ibcon#about to read 4, iclass 20, count 0 2006.197.07:50:27.89#ibcon#read 4, iclass 20, count 0 2006.197.07:50:27.89#ibcon#about to read 5, iclass 20, count 0 2006.197.07:50:27.89#ibcon#read 5, iclass 20, count 0 2006.197.07:50:27.89#ibcon#about to read 6, iclass 20, count 0 2006.197.07:50:27.89#ibcon#read 6, iclass 20, count 0 2006.197.07:50:27.89#ibcon#end of sib2, iclass 20, count 0 2006.197.07:50:27.89#ibcon#*after write, iclass 20, count 0 2006.197.07:50:27.89#ibcon#*before return 0, iclass 20, count 0 2006.197.07:50:27.89#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.197.07:50:27.89#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.197.07:50:27.89#ibcon#about to clear, iclass 20 cls_cnt 0 2006.197.07:50:27.89#ibcon#cleared, iclass 20 cls_cnt 0 2006.197.07:50:27.89$vc4f8/va=2,7 2006.197.07:50:27.89#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.197.07:50:27.89#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.197.07:50:27.89#ibcon#ireg 11 cls_cnt 2 2006.197.07:50:27.89#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.197.07:50:27.91#abcon#[5=S1D000X0/0*\r\n] 2006.197.07:50:27.95#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.197.07:50:27.95#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.197.07:50:27.95#ibcon#enter wrdev, iclass 22, count 2 2006.197.07:50:27.95#ibcon#first serial, iclass 22, count 2 2006.197.07:50:27.95#ibcon#enter sib2, iclass 22, count 2 2006.197.07:50:27.95#ibcon#flushed, iclass 22, count 2 2006.197.07:50:27.95#ibcon#about to write, iclass 22, count 2 2006.197.07:50:27.95#ibcon#wrote, iclass 22, count 2 2006.197.07:50:27.95#ibcon#about to read 3, iclass 22, count 2 2006.197.07:50:27.97#ibcon#read 3, iclass 22, count 2 2006.197.07:50:27.97#ibcon#about to read 4, iclass 22, count 2 2006.197.07:50:27.97#ibcon#read 4, iclass 22, count 2 2006.197.07:50:27.97#ibcon#about to read 5, iclass 22, count 2 2006.197.07:50:27.97#ibcon#read 5, iclass 22, count 2 2006.197.07:50:27.97#ibcon#about to read 6, iclass 22, count 2 2006.197.07:50:27.97#ibcon#read 6, iclass 22, count 2 2006.197.07:50:27.97#ibcon#end of sib2, iclass 22, count 2 2006.197.07:50:27.97#ibcon#*mode == 0, iclass 22, count 2 2006.197.07:50:27.97#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.197.07:50:27.97#ibcon#[25=AT02-07\r\n] 2006.197.07:50:27.97#ibcon#*before write, iclass 22, count 2 2006.197.07:50:27.97#ibcon#enter sib2, iclass 22, count 2 2006.197.07:50:27.97#ibcon#flushed, iclass 22, count 2 2006.197.07:50:27.97#ibcon#about to write, iclass 22, count 2 2006.197.07:50:27.97#ibcon#wrote, iclass 22, count 2 2006.197.07:50:27.97#ibcon#about to read 3, iclass 22, count 2 2006.197.07:50:28.00#ibcon#read 3, iclass 22, count 2 2006.197.07:50:28.00#ibcon#about to read 4, iclass 22, count 2 2006.197.07:50:28.00#ibcon#read 4, iclass 22, count 2 2006.197.07:50:28.00#ibcon#about to read 5, iclass 22, count 2 2006.197.07:50:28.00#ibcon#read 5, iclass 22, count 2 2006.197.07:50:28.00#ibcon#about to read 6, iclass 22, count 2 2006.197.07:50:28.00#ibcon#read 6, iclass 22, count 2 2006.197.07:50:28.00#ibcon#end of sib2, iclass 22, count 2 2006.197.07:50:28.00#ibcon#*after write, iclass 22, count 2 2006.197.07:50:28.00#ibcon#*before return 0, iclass 22, count 2 2006.197.07:50:28.00#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.197.07:50:28.00#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.197.07:50:28.00#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.197.07:50:28.00#ibcon#ireg 7 cls_cnt 0 2006.197.07:50:28.00#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.197.07:50:28.12#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.197.07:50:28.12#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.197.07:50:28.12#ibcon#enter wrdev, iclass 22, count 0 2006.197.07:50:28.12#ibcon#first serial, iclass 22, count 0 2006.197.07:50:28.12#ibcon#enter sib2, iclass 22, count 0 2006.197.07:50:28.12#ibcon#flushed, iclass 22, count 0 2006.197.07:50:28.12#ibcon#about to write, iclass 22, count 0 2006.197.07:50:28.12#ibcon#wrote, iclass 22, count 0 2006.197.07:50:28.12#ibcon#about to read 3, iclass 22, count 0 2006.197.07:50:28.14#ibcon#read 3, iclass 22, count 0 2006.197.07:50:28.14#ibcon#about to read 4, iclass 22, count 0 2006.197.07:50:28.14#ibcon#read 4, iclass 22, count 0 2006.197.07:50:28.14#ibcon#about to read 5, iclass 22, count 0 2006.197.07:50:28.14#ibcon#read 5, iclass 22, count 0 2006.197.07:50:28.14#ibcon#about to read 6, iclass 22, count 0 2006.197.07:50:28.14#ibcon#read 6, iclass 22, count 0 2006.197.07:50:28.14#ibcon#end of sib2, iclass 22, count 0 2006.197.07:50:28.14#ibcon#*mode == 0, iclass 22, count 0 2006.197.07:50:28.14#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.197.07:50:28.14#ibcon#[25=USB\r\n] 2006.197.07:50:28.14#ibcon#*before write, iclass 22, count 0 2006.197.07:50:28.14#ibcon#enter sib2, iclass 22, count 0 2006.197.07:50:28.14#ibcon#flushed, iclass 22, count 0 2006.197.07:50:28.14#ibcon#about to write, iclass 22, count 0 2006.197.07:50:28.14#ibcon#wrote, iclass 22, count 0 2006.197.07:50:28.14#ibcon#about to read 3, iclass 22, count 0 2006.197.07:50:28.17#ibcon#read 3, iclass 22, count 0 2006.197.07:50:28.17#ibcon#about to read 4, iclass 22, count 0 2006.197.07:50:28.17#ibcon#read 4, iclass 22, count 0 2006.197.07:50:28.17#ibcon#about to read 5, iclass 22, count 0 2006.197.07:50:28.17#ibcon#read 5, iclass 22, count 0 2006.197.07:50:28.17#ibcon#about to read 6, iclass 22, count 0 2006.197.07:50:28.17#ibcon#read 6, iclass 22, count 0 2006.197.07:50:28.17#ibcon#end of sib2, iclass 22, count 0 2006.197.07:50:28.17#ibcon#*after write, iclass 22, count 0 2006.197.07:50:28.17#ibcon#*before return 0, iclass 22, count 0 2006.197.07:50:28.17#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.197.07:50:28.17#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.197.07:50:28.17#ibcon#about to clear, iclass 22 cls_cnt 0 2006.197.07:50:28.17#ibcon#cleared, iclass 22 cls_cnt 0 2006.197.07:50:28.17$vc4f8/valo=3,672.99 2006.197.07:50:28.17#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.197.07:50:28.17#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.197.07:50:28.17#ibcon#ireg 17 cls_cnt 0 2006.197.07:50:28.17#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.197.07:50:28.17#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.197.07:50:28.17#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.197.07:50:28.17#ibcon#enter wrdev, iclass 25, count 0 2006.197.07:50:28.17#ibcon#first serial, iclass 25, count 0 2006.197.07:50:28.17#ibcon#enter sib2, iclass 25, count 0 2006.197.07:50:28.17#ibcon#flushed, iclass 25, count 0 2006.197.07:50:28.17#ibcon#about to write, iclass 25, count 0 2006.197.07:50:28.17#ibcon#wrote, iclass 25, count 0 2006.197.07:50:28.17#ibcon#about to read 3, iclass 25, count 0 2006.197.07:50:28.19#ibcon#read 3, iclass 25, count 0 2006.197.07:50:28.19#ibcon#about to read 4, iclass 25, count 0 2006.197.07:50:28.19#ibcon#read 4, iclass 25, count 0 2006.197.07:50:28.19#ibcon#about to read 5, iclass 25, count 0 2006.197.07:50:28.19#ibcon#read 5, iclass 25, count 0 2006.197.07:50:28.19#ibcon#about to read 6, iclass 25, count 0 2006.197.07:50:28.19#ibcon#read 6, iclass 25, count 0 2006.197.07:50:28.19#ibcon#end of sib2, iclass 25, count 0 2006.197.07:50:28.19#ibcon#*mode == 0, iclass 25, count 0 2006.197.07:50:28.19#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.197.07:50:28.19#ibcon#[26=FRQ=03,672.99\r\n] 2006.197.07:50:28.19#ibcon#*before write, iclass 25, count 0 2006.197.07:50:28.19#ibcon#enter sib2, iclass 25, count 0 2006.197.07:50:28.19#ibcon#flushed, iclass 25, count 0 2006.197.07:50:28.19#ibcon#about to write, iclass 25, count 0 2006.197.07:50:28.19#ibcon#wrote, iclass 25, count 0 2006.197.07:50:28.19#ibcon#about to read 3, iclass 25, count 0 2006.197.07:50:28.23#ibcon#read 3, iclass 25, count 0 2006.197.07:50:28.23#ibcon#about to read 4, iclass 25, count 0 2006.197.07:50:28.23#ibcon#read 4, iclass 25, count 0 2006.197.07:50:28.23#ibcon#about to read 5, iclass 25, count 0 2006.197.07:50:28.23#ibcon#read 5, iclass 25, count 0 2006.197.07:50:28.23#ibcon#about to read 6, iclass 25, count 0 2006.197.07:50:28.23#ibcon#read 6, iclass 25, count 0 2006.197.07:50:28.23#ibcon#end of sib2, iclass 25, count 0 2006.197.07:50:28.23#ibcon#*after write, iclass 25, count 0 2006.197.07:50:28.23#ibcon#*before return 0, iclass 25, count 0 2006.197.07:50:28.23#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.197.07:50:28.23#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.197.07:50:28.23#ibcon#about to clear, iclass 25 cls_cnt 0 2006.197.07:50:28.23#ibcon#cleared, iclass 25 cls_cnt 0 2006.197.07:50:28.23$vc4f8/va=3,6 2006.197.07:50:28.23#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.197.07:50:28.23#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.197.07:50:28.23#ibcon#ireg 11 cls_cnt 2 2006.197.07:50:28.23#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.197.07:50:28.29#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.197.07:50:28.29#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.197.07:50:28.29#ibcon#enter wrdev, iclass 27, count 2 2006.197.07:50:28.29#ibcon#first serial, iclass 27, count 2 2006.197.07:50:28.29#ibcon#enter sib2, iclass 27, count 2 2006.197.07:50:28.29#ibcon#flushed, iclass 27, count 2 2006.197.07:50:28.29#ibcon#about to write, iclass 27, count 2 2006.197.07:50:28.29#ibcon#wrote, iclass 27, count 2 2006.197.07:50:28.29#ibcon#about to read 3, iclass 27, count 2 2006.197.07:50:28.31#ibcon#read 3, iclass 27, count 2 2006.197.07:50:28.31#ibcon#about to read 4, iclass 27, count 2 2006.197.07:50:28.31#ibcon#read 4, iclass 27, count 2 2006.197.07:50:28.31#ibcon#about to read 5, iclass 27, count 2 2006.197.07:50:28.31#ibcon#read 5, iclass 27, count 2 2006.197.07:50:28.31#ibcon#about to read 6, iclass 27, count 2 2006.197.07:50:28.31#ibcon#read 6, iclass 27, count 2 2006.197.07:50:28.31#ibcon#end of sib2, iclass 27, count 2 2006.197.07:50:28.31#ibcon#*mode == 0, iclass 27, count 2 2006.197.07:50:28.31#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.197.07:50:28.31#ibcon#[25=AT03-06\r\n] 2006.197.07:50:28.31#ibcon#*before write, iclass 27, count 2 2006.197.07:50:28.31#ibcon#enter sib2, iclass 27, count 2 2006.197.07:50:28.31#ibcon#flushed, iclass 27, count 2 2006.197.07:50:28.31#ibcon#about to write, iclass 27, count 2 2006.197.07:50:28.31#ibcon#wrote, iclass 27, count 2 2006.197.07:50:28.31#ibcon#about to read 3, iclass 27, count 2 2006.197.07:50:28.34#ibcon#read 3, iclass 27, count 2 2006.197.07:50:28.34#ibcon#about to read 4, iclass 27, count 2 2006.197.07:50:28.34#ibcon#read 4, iclass 27, count 2 2006.197.07:50:28.34#ibcon#about to read 5, iclass 27, count 2 2006.197.07:50:28.34#ibcon#read 5, iclass 27, count 2 2006.197.07:50:28.34#ibcon#about to read 6, iclass 27, count 2 2006.197.07:50:28.34#ibcon#read 6, iclass 27, count 2 2006.197.07:50:28.34#ibcon#end of sib2, iclass 27, count 2 2006.197.07:50:28.34#ibcon#*after write, iclass 27, count 2 2006.197.07:50:28.34#ibcon#*before return 0, iclass 27, count 2 2006.197.07:50:28.34#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.197.07:50:28.34#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.197.07:50:28.34#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.197.07:50:28.34#ibcon#ireg 7 cls_cnt 0 2006.197.07:50:28.34#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.197.07:50:28.46#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.197.07:50:28.46#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.197.07:50:28.46#ibcon#enter wrdev, iclass 27, count 0 2006.197.07:50:28.46#ibcon#first serial, iclass 27, count 0 2006.197.07:50:28.46#ibcon#enter sib2, iclass 27, count 0 2006.197.07:50:28.46#ibcon#flushed, iclass 27, count 0 2006.197.07:50:28.46#ibcon#about to write, iclass 27, count 0 2006.197.07:50:28.46#ibcon#wrote, iclass 27, count 0 2006.197.07:50:28.46#ibcon#about to read 3, iclass 27, count 0 2006.197.07:50:28.48#ibcon#read 3, iclass 27, count 0 2006.197.07:50:28.48#ibcon#about to read 4, iclass 27, count 0 2006.197.07:50:28.48#ibcon#read 4, iclass 27, count 0 2006.197.07:50:28.48#ibcon#about to read 5, iclass 27, count 0 2006.197.07:50:28.48#ibcon#read 5, iclass 27, count 0 2006.197.07:50:28.48#ibcon#about to read 6, iclass 27, count 0 2006.197.07:50:28.48#ibcon#read 6, iclass 27, count 0 2006.197.07:50:28.48#ibcon#end of sib2, iclass 27, count 0 2006.197.07:50:28.48#ibcon#*mode == 0, iclass 27, count 0 2006.197.07:50:28.48#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.197.07:50:28.48#ibcon#[25=USB\r\n] 2006.197.07:50:28.48#ibcon#*before write, iclass 27, count 0 2006.197.07:50:28.48#ibcon#enter sib2, iclass 27, count 0 2006.197.07:50:28.48#ibcon#flushed, iclass 27, count 0 2006.197.07:50:28.48#ibcon#about to write, iclass 27, count 0 2006.197.07:50:28.48#ibcon#wrote, iclass 27, count 0 2006.197.07:50:28.48#ibcon#about to read 3, iclass 27, count 0 2006.197.07:50:28.51#ibcon#read 3, iclass 27, count 0 2006.197.07:50:28.51#ibcon#about to read 4, iclass 27, count 0 2006.197.07:50:28.51#ibcon#read 4, iclass 27, count 0 2006.197.07:50:28.51#ibcon#about to read 5, iclass 27, count 0 2006.197.07:50:28.51#ibcon#read 5, iclass 27, count 0 2006.197.07:50:28.51#ibcon#about to read 6, iclass 27, count 0 2006.197.07:50:28.51#ibcon#read 6, iclass 27, count 0 2006.197.07:50:28.51#ibcon#end of sib2, iclass 27, count 0 2006.197.07:50:28.51#ibcon#*after write, iclass 27, count 0 2006.197.07:50:28.51#ibcon#*before return 0, iclass 27, count 0 2006.197.07:50:28.51#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.197.07:50:28.51#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.197.07:50:28.51#ibcon#about to clear, iclass 27 cls_cnt 0 2006.197.07:50:28.51#ibcon#cleared, iclass 27 cls_cnt 0 2006.197.07:50:28.51$vc4f8/valo=4,832.99 2006.197.07:50:28.51#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.197.07:50:28.51#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.197.07:50:28.51#ibcon#ireg 17 cls_cnt 0 2006.197.07:50:28.51#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.197.07:50:28.51#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.197.07:50:28.51#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.197.07:50:28.51#ibcon#enter wrdev, iclass 29, count 0 2006.197.07:50:28.51#ibcon#first serial, iclass 29, count 0 2006.197.07:50:28.51#ibcon#enter sib2, iclass 29, count 0 2006.197.07:50:28.51#ibcon#flushed, iclass 29, count 0 2006.197.07:50:28.51#ibcon#about to write, iclass 29, count 0 2006.197.07:50:28.51#ibcon#wrote, iclass 29, count 0 2006.197.07:50:28.51#ibcon#about to read 3, iclass 29, count 0 2006.197.07:50:28.53#ibcon#read 3, iclass 29, count 0 2006.197.07:50:28.53#ibcon#about to read 4, iclass 29, count 0 2006.197.07:50:28.53#ibcon#read 4, iclass 29, count 0 2006.197.07:50:28.53#ibcon#about to read 5, iclass 29, count 0 2006.197.07:50:28.53#ibcon#read 5, iclass 29, count 0 2006.197.07:50:28.53#ibcon#about to read 6, iclass 29, count 0 2006.197.07:50:28.53#ibcon#read 6, iclass 29, count 0 2006.197.07:50:28.53#ibcon#end of sib2, iclass 29, count 0 2006.197.07:50:28.53#ibcon#*mode == 0, iclass 29, count 0 2006.197.07:50:28.53#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.197.07:50:28.53#ibcon#[26=FRQ=04,832.99\r\n] 2006.197.07:50:28.53#ibcon#*before write, iclass 29, count 0 2006.197.07:50:28.53#ibcon#enter sib2, iclass 29, count 0 2006.197.07:50:28.53#ibcon#flushed, iclass 29, count 0 2006.197.07:50:28.53#ibcon#about to write, iclass 29, count 0 2006.197.07:50:28.53#ibcon#wrote, iclass 29, count 0 2006.197.07:50:28.53#ibcon#about to read 3, iclass 29, count 0 2006.197.07:50:28.57#ibcon#read 3, iclass 29, count 0 2006.197.07:50:28.57#ibcon#about to read 4, iclass 29, count 0 2006.197.07:50:28.57#ibcon#read 4, iclass 29, count 0 2006.197.07:50:28.57#ibcon#about to read 5, iclass 29, count 0 2006.197.07:50:28.57#ibcon#read 5, iclass 29, count 0 2006.197.07:50:28.57#ibcon#about to read 6, iclass 29, count 0 2006.197.07:50:28.57#ibcon#read 6, iclass 29, count 0 2006.197.07:50:28.57#ibcon#end of sib2, iclass 29, count 0 2006.197.07:50:28.57#ibcon#*after write, iclass 29, count 0 2006.197.07:50:28.57#ibcon#*before return 0, iclass 29, count 0 2006.197.07:50:28.57#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.197.07:50:28.57#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.197.07:50:28.57#ibcon#about to clear, iclass 29 cls_cnt 0 2006.197.07:50:28.57#ibcon#cleared, iclass 29 cls_cnt 0 2006.197.07:50:28.57$vc4f8/va=4,7 2006.197.07:50:28.57#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.197.07:50:28.57#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.197.07:50:28.57#ibcon#ireg 11 cls_cnt 2 2006.197.07:50:28.57#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.197.07:50:28.63#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.197.07:50:28.63#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.197.07:50:28.63#ibcon#enter wrdev, iclass 31, count 2 2006.197.07:50:28.63#ibcon#first serial, iclass 31, count 2 2006.197.07:50:28.63#ibcon#enter sib2, iclass 31, count 2 2006.197.07:50:28.63#ibcon#flushed, iclass 31, count 2 2006.197.07:50:28.63#ibcon#about to write, iclass 31, count 2 2006.197.07:50:28.63#ibcon#wrote, iclass 31, count 2 2006.197.07:50:28.63#ibcon#about to read 3, iclass 31, count 2 2006.197.07:50:28.65#ibcon#read 3, iclass 31, count 2 2006.197.07:50:28.65#ibcon#about to read 4, iclass 31, count 2 2006.197.07:50:28.65#ibcon#read 4, iclass 31, count 2 2006.197.07:50:28.65#ibcon#about to read 5, iclass 31, count 2 2006.197.07:50:28.65#ibcon#read 5, iclass 31, count 2 2006.197.07:50:28.65#ibcon#about to read 6, iclass 31, count 2 2006.197.07:50:28.65#ibcon#read 6, iclass 31, count 2 2006.197.07:50:28.65#ibcon#end of sib2, iclass 31, count 2 2006.197.07:50:28.65#ibcon#*mode == 0, iclass 31, count 2 2006.197.07:50:28.65#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.197.07:50:28.65#ibcon#[25=AT04-07\r\n] 2006.197.07:50:28.65#ibcon#*before write, iclass 31, count 2 2006.197.07:50:28.65#ibcon#enter sib2, iclass 31, count 2 2006.197.07:50:28.65#ibcon#flushed, iclass 31, count 2 2006.197.07:50:28.65#ibcon#about to write, iclass 31, count 2 2006.197.07:50:28.65#ibcon#wrote, iclass 31, count 2 2006.197.07:50:28.65#ibcon#about to read 3, iclass 31, count 2 2006.197.07:50:28.68#ibcon#read 3, iclass 31, count 2 2006.197.07:50:28.68#ibcon#about to read 4, iclass 31, count 2 2006.197.07:50:28.68#ibcon#read 4, iclass 31, count 2 2006.197.07:50:28.68#ibcon#about to read 5, iclass 31, count 2 2006.197.07:50:28.68#ibcon#read 5, iclass 31, count 2 2006.197.07:50:28.68#ibcon#about to read 6, iclass 31, count 2 2006.197.07:50:28.68#ibcon#read 6, iclass 31, count 2 2006.197.07:50:28.68#ibcon#end of sib2, iclass 31, count 2 2006.197.07:50:28.68#ibcon#*after write, iclass 31, count 2 2006.197.07:50:28.68#ibcon#*before return 0, iclass 31, count 2 2006.197.07:50:28.68#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.197.07:50:28.68#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.197.07:50:28.68#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.197.07:50:28.68#ibcon#ireg 7 cls_cnt 0 2006.197.07:50:28.68#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.197.07:50:28.80#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.197.07:50:28.80#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.197.07:50:28.80#ibcon#enter wrdev, iclass 31, count 0 2006.197.07:50:28.80#ibcon#first serial, iclass 31, count 0 2006.197.07:50:28.80#ibcon#enter sib2, iclass 31, count 0 2006.197.07:50:28.80#ibcon#flushed, iclass 31, count 0 2006.197.07:50:28.80#ibcon#about to write, iclass 31, count 0 2006.197.07:50:28.80#ibcon#wrote, iclass 31, count 0 2006.197.07:50:28.80#ibcon#about to read 3, iclass 31, count 0 2006.197.07:50:28.82#ibcon#read 3, iclass 31, count 0 2006.197.07:50:28.82#ibcon#about to read 4, iclass 31, count 0 2006.197.07:50:28.82#ibcon#read 4, iclass 31, count 0 2006.197.07:50:28.82#ibcon#about to read 5, iclass 31, count 0 2006.197.07:50:28.82#ibcon#read 5, iclass 31, count 0 2006.197.07:50:28.82#ibcon#about to read 6, iclass 31, count 0 2006.197.07:50:28.82#ibcon#read 6, iclass 31, count 0 2006.197.07:50:28.82#ibcon#end of sib2, iclass 31, count 0 2006.197.07:50:28.82#ibcon#*mode == 0, iclass 31, count 0 2006.197.07:50:28.82#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.197.07:50:28.82#ibcon#[25=USB\r\n] 2006.197.07:50:28.82#ibcon#*before write, iclass 31, count 0 2006.197.07:50:28.82#ibcon#enter sib2, iclass 31, count 0 2006.197.07:50:28.82#ibcon#flushed, iclass 31, count 0 2006.197.07:50:28.82#ibcon#about to write, iclass 31, count 0 2006.197.07:50:28.82#ibcon#wrote, iclass 31, count 0 2006.197.07:50:28.82#ibcon#about to read 3, iclass 31, count 0 2006.197.07:50:28.85#ibcon#read 3, iclass 31, count 0 2006.197.07:50:28.85#ibcon#about to read 4, iclass 31, count 0 2006.197.07:50:28.85#ibcon#read 4, iclass 31, count 0 2006.197.07:50:28.85#ibcon#about to read 5, iclass 31, count 0 2006.197.07:50:28.85#ibcon#read 5, iclass 31, count 0 2006.197.07:50:28.85#ibcon#about to read 6, iclass 31, count 0 2006.197.07:50:28.85#ibcon#read 6, iclass 31, count 0 2006.197.07:50:28.85#ibcon#end of sib2, iclass 31, count 0 2006.197.07:50:28.85#ibcon#*after write, iclass 31, count 0 2006.197.07:50:28.85#ibcon#*before return 0, iclass 31, count 0 2006.197.07:50:28.85#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.197.07:50:28.85#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.197.07:50:28.85#ibcon#about to clear, iclass 31 cls_cnt 0 2006.197.07:50:28.85#ibcon#cleared, iclass 31 cls_cnt 0 2006.197.07:50:28.85$vc4f8/valo=5,652.99 2006.197.07:50:28.85#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.197.07:50:28.85#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.197.07:50:28.85#ibcon#ireg 17 cls_cnt 0 2006.197.07:50:28.85#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.197.07:50:28.85#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.197.07:50:28.85#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.197.07:50:28.85#ibcon#enter wrdev, iclass 33, count 0 2006.197.07:50:28.85#ibcon#first serial, iclass 33, count 0 2006.197.07:50:28.85#ibcon#enter sib2, iclass 33, count 0 2006.197.07:50:28.85#ibcon#flushed, iclass 33, count 0 2006.197.07:50:28.85#ibcon#about to write, iclass 33, count 0 2006.197.07:50:28.85#ibcon#wrote, iclass 33, count 0 2006.197.07:50:28.85#ibcon#about to read 3, iclass 33, count 0 2006.197.07:50:28.87#ibcon#read 3, iclass 33, count 0 2006.197.07:50:28.87#ibcon#about to read 4, iclass 33, count 0 2006.197.07:50:28.87#ibcon#read 4, iclass 33, count 0 2006.197.07:50:28.87#ibcon#about to read 5, iclass 33, count 0 2006.197.07:50:28.87#ibcon#read 5, iclass 33, count 0 2006.197.07:50:28.87#ibcon#about to read 6, iclass 33, count 0 2006.197.07:50:28.87#ibcon#read 6, iclass 33, count 0 2006.197.07:50:28.87#ibcon#end of sib2, iclass 33, count 0 2006.197.07:50:28.87#ibcon#*mode == 0, iclass 33, count 0 2006.197.07:50:28.87#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.197.07:50:28.87#ibcon#[26=FRQ=05,652.99\r\n] 2006.197.07:50:28.87#ibcon#*before write, iclass 33, count 0 2006.197.07:50:28.87#ibcon#enter sib2, iclass 33, count 0 2006.197.07:50:28.87#ibcon#flushed, iclass 33, count 0 2006.197.07:50:28.87#ibcon#about to write, iclass 33, count 0 2006.197.07:50:28.87#ibcon#wrote, iclass 33, count 0 2006.197.07:50:28.87#ibcon#about to read 3, iclass 33, count 0 2006.197.07:50:28.91#ibcon#read 3, iclass 33, count 0 2006.197.07:50:28.91#ibcon#about to read 4, iclass 33, count 0 2006.197.07:50:28.91#ibcon#read 4, iclass 33, count 0 2006.197.07:50:28.91#ibcon#about to read 5, iclass 33, count 0 2006.197.07:50:28.91#ibcon#read 5, iclass 33, count 0 2006.197.07:50:28.91#ibcon#about to read 6, iclass 33, count 0 2006.197.07:50:28.91#ibcon#read 6, iclass 33, count 0 2006.197.07:50:28.91#ibcon#end of sib2, iclass 33, count 0 2006.197.07:50:28.91#ibcon#*after write, iclass 33, count 0 2006.197.07:50:28.91#ibcon#*before return 0, iclass 33, count 0 2006.197.07:50:28.91#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.197.07:50:28.91#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.197.07:50:28.91#ibcon#about to clear, iclass 33 cls_cnt 0 2006.197.07:50:28.91#ibcon#cleared, iclass 33 cls_cnt 0 2006.197.07:50:28.91$vc4f8/va=5,7 2006.197.07:50:28.91#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.197.07:50:28.91#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.197.07:50:28.91#ibcon#ireg 11 cls_cnt 2 2006.197.07:50:28.91#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.197.07:50:28.97#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.197.07:50:28.97#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.197.07:50:28.97#ibcon#enter wrdev, iclass 35, count 2 2006.197.07:50:28.97#ibcon#first serial, iclass 35, count 2 2006.197.07:50:28.97#ibcon#enter sib2, iclass 35, count 2 2006.197.07:50:28.97#ibcon#flushed, iclass 35, count 2 2006.197.07:50:28.97#ibcon#about to write, iclass 35, count 2 2006.197.07:50:28.97#ibcon#wrote, iclass 35, count 2 2006.197.07:50:28.97#ibcon#about to read 3, iclass 35, count 2 2006.197.07:50:28.99#ibcon#read 3, iclass 35, count 2 2006.197.07:50:28.99#ibcon#about to read 4, iclass 35, count 2 2006.197.07:50:28.99#ibcon#read 4, iclass 35, count 2 2006.197.07:50:28.99#ibcon#about to read 5, iclass 35, count 2 2006.197.07:50:28.99#ibcon#read 5, iclass 35, count 2 2006.197.07:50:28.99#ibcon#about to read 6, iclass 35, count 2 2006.197.07:50:28.99#ibcon#read 6, iclass 35, count 2 2006.197.07:50:28.99#ibcon#end of sib2, iclass 35, count 2 2006.197.07:50:28.99#ibcon#*mode == 0, iclass 35, count 2 2006.197.07:50:28.99#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.197.07:50:28.99#ibcon#[25=AT05-07\r\n] 2006.197.07:50:28.99#ibcon#*before write, iclass 35, count 2 2006.197.07:50:28.99#ibcon#enter sib2, iclass 35, count 2 2006.197.07:50:28.99#ibcon#flushed, iclass 35, count 2 2006.197.07:50:28.99#ibcon#about to write, iclass 35, count 2 2006.197.07:50:28.99#ibcon#wrote, iclass 35, count 2 2006.197.07:50:28.99#ibcon#about to read 3, iclass 35, count 2 2006.197.07:50:29.02#ibcon#read 3, iclass 35, count 2 2006.197.07:50:29.02#ibcon#about to read 4, iclass 35, count 2 2006.197.07:50:29.02#ibcon#read 4, iclass 35, count 2 2006.197.07:50:29.02#ibcon#about to read 5, iclass 35, count 2 2006.197.07:50:29.02#ibcon#read 5, iclass 35, count 2 2006.197.07:50:29.02#ibcon#about to read 6, iclass 35, count 2 2006.197.07:50:29.02#ibcon#read 6, iclass 35, count 2 2006.197.07:50:29.02#ibcon#end of sib2, iclass 35, count 2 2006.197.07:50:29.02#ibcon#*after write, iclass 35, count 2 2006.197.07:50:29.02#ibcon#*before return 0, iclass 35, count 2 2006.197.07:50:29.02#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.197.07:50:29.02#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.197.07:50:29.02#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.197.07:50:29.02#ibcon#ireg 7 cls_cnt 0 2006.197.07:50:29.02#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.197.07:50:29.14#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.197.07:50:29.14#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.197.07:50:29.14#ibcon#enter wrdev, iclass 35, count 0 2006.197.07:50:29.14#ibcon#first serial, iclass 35, count 0 2006.197.07:50:29.14#ibcon#enter sib2, iclass 35, count 0 2006.197.07:50:29.14#ibcon#flushed, iclass 35, count 0 2006.197.07:50:29.14#ibcon#about to write, iclass 35, count 0 2006.197.07:50:29.14#ibcon#wrote, iclass 35, count 0 2006.197.07:50:29.14#ibcon#about to read 3, iclass 35, count 0 2006.197.07:50:29.16#ibcon#read 3, iclass 35, count 0 2006.197.07:50:29.16#ibcon#about to read 4, iclass 35, count 0 2006.197.07:50:29.16#ibcon#read 4, iclass 35, count 0 2006.197.07:50:29.16#ibcon#about to read 5, iclass 35, count 0 2006.197.07:50:29.16#ibcon#read 5, iclass 35, count 0 2006.197.07:50:29.16#ibcon#about to read 6, iclass 35, count 0 2006.197.07:50:29.16#ibcon#read 6, iclass 35, count 0 2006.197.07:50:29.16#ibcon#end of sib2, iclass 35, count 0 2006.197.07:50:29.16#ibcon#*mode == 0, iclass 35, count 0 2006.197.07:50:29.16#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.197.07:50:29.16#ibcon#[25=USB\r\n] 2006.197.07:50:29.16#ibcon#*before write, iclass 35, count 0 2006.197.07:50:29.16#ibcon#enter sib2, iclass 35, count 0 2006.197.07:50:29.16#ibcon#flushed, iclass 35, count 0 2006.197.07:50:29.16#ibcon#about to write, iclass 35, count 0 2006.197.07:50:29.16#ibcon#wrote, iclass 35, count 0 2006.197.07:50:29.16#ibcon#about to read 3, iclass 35, count 0 2006.197.07:50:29.19#ibcon#read 3, iclass 35, count 0 2006.197.07:50:29.19#ibcon#about to read 4, iclass 35, count 0 2006.197.07:50:29.19#ibcon#read 4, iclass 35, count 0 2006.197.07:50:29.19#ibcon#about to read 5, iclass 35, count 0 2006.197.07:50:29.19#ibcon#read 5, iclass 35, count 0 2006.197.07:50:29.19#ibcon#about to read 6, iclass 35, count 0 2006.197.07:50:29.19#ibcon#read 6, iclass 35, count 0 2006.197.07:50:29.19#ibcon#end of sib2, iclass 35, count 0 2006.197.07:50:29.19#ibcon#*after write, iclass 35, count 0 2006.197.07:50:29.19#ibcon#*before return 0, iclass 35, count 0 2006.197.07:50:29.19#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.197.07:50:29.19#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.197.07:50:29.19#ibcon#about to clear, iclass 35 cls_cnt 0 2006.197.07:50:29.19#ibcon#cleared, iclass 35 cls_cnt 0 2006.197.07:50:29.19$vc4f8/valo=6,772.99 2006.197.07:50:29.19#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.197.07:50:29.19#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.197.07:50:29.19#ibcon#ireg 17 cls_cnt 0 2006.197.07:50:29.19#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.197.07:50:29.19#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.197.07:50:29.19#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.197.07:50:29.19#ibcon#enter wrdev, iclass 37, count 0 2006.197.07:50:29.19#ibcon#first serial, iclass 37, count 0 2006.197.07:50:29.19#ibcon#enter sib2, iclass 37, count 0 2006.197.07:50:29.19#ibcon#flushed, iclass 37, count 0 2006.197.07:50:29.19#ibcon#about to write, iclass 37, count 0 2006.197.07:50:29.19#ibcon#wrote, iclass 37, count 0 2006.197.07:50:29.19#ibcon#about to read 3, iclass 37, count 0 2006.197.07:50:29.21#ibcon#read 3, iclass 37, count 0 2006.197.07:50:29.21#ibcon#about to read 4, iclass 37, count 0 2006.197.07:50:29.21#ibcon#read 4, iclass 37, count 0 2006.197.07:50:29.21#ibcon#about to read 5, iclass 37, count 0 2006.197.07:50:29.21#ibcon#read 5, iclass 37, count 0 2006.197.07:50:29.21#ibcon#about to read 6, iclass 37, count 0 2006.197.07:50:29.21#ibcon#read 6, iclass 37, count 0 2006.197.07:50:29.21#ibcon#end of sib2, iclass 37, count 0 2006.197.07:50:29.21#ibcon#*mode == 0, iclass 37, count 0 2006.197.07:50:29.21#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.197.07:50:29.21#ibcon#[26=FRQ=06,772.99\r\n] 2006.197.07:50:29.21#ibcon#*before write, iclass 37, count 0 2006.197.07:50:29.21#ibcon#enter sib2, iclass 37, count 0 2006.197.07:50:29.21#ibcon#flushed, iclass 37, count 0 2006.197.07:50:29.21#ibcon#about to write, iclass 37, count 0 2006.197.07:50:29.21#ibcon#wrote, iclass 37, count 0 2006.197.07:50:29.21#ibcon#about to read 3, iclass 37, count 0 2006.197.07:50:29.25#ibcon#read 3, iclass 37, count 0 2006.197.07:50:29.25#ibcon#about to read 4, iclass 37, count 0 2006.197.07:50:29.25#ibcon#read 4, iclass 37, count 0 2006.197.07:50:29.25#ibcon#about to read 5, iclass 37, count 0 2006.197.07:50:29.25#ibcon#read 5, iclass 37, count 0 2006.197.07:50:29.25#ibcon#about to read 6, iclass 37, count 0 2006.197.07:50:29.25#ibcon#read 6, iclass 37, count 0 2006.197.07:50:29.25#ibcon#end of sib2, iclass 37, count 0 2006.197.07:50:29.25#ibcon#*after write, iclass 37, count 0 2006.197.07:50:29.25#ibcon#*before return 0, iclass 37, count 0 2006.197.07:50:29.25#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.197.07:50:29.25#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.197.07:50:29.25#ibcon#about to clear, iclass 37 cls_cnt 0 2006.197.07:50:29.25#ibcon#cleared, iclass 37 cls_cnt 0 2006.197.07:50:29.25$vc4f8/va=6,6 2006.197.07:50:29.25#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.197.07:50:29.25#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.197.07:50:29.25#ibcon#ireg 11 cls_cnt 2 2006.197.07:50:29.25#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.197.07:50:29.31#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.197.07:50:29.31#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.197.07:50:29.31#ibcon#enter wrdev, iclass 39, count 2 2006.197.07:50:29.31#ibcon#first serial, iclass 39, count 2 2006.197.07:50:29.31#ibcon#enter sib2, iclass 39, count 2 2006.197.07:50:29.31#ibcon#flushed, iclass 39, count 2 2006.197.07:50:29.31#ibcon#about to write, iclass 39, count 2 2006.197.07:50:29.31#ibcon#wrote, iclass 39, count 2 2006.197.07:50:29.31#ibcon#about to read 3, iclass 39, count 2 2006.197.07:50:29.33#ibcon#read 3, iclass 39, count 2 2006.197.07:50:29.33#ibcon#about to read 4, iclass 39, count 2 2006.197.07:50:29.33#ibcon#read 4, iclass 39, count 2 2006.197.07:50:29.33#ibcon#about to read 5, iclass 39, count 2 2006.197.07:50:29.33#ibcon#read 5, iclass 39, count 2 2006.197.07:50:29.33#ibcon#about to read 6, iclass 39, count 2 2006.197.07:50:29.33#ibcon#read 6, iclass 39, count 2 2006.197.07:50:29.33#ibcon#end of sib2, iclass 39, count 2 2006.197.07:50:29.33#ibcon#*mode == 0, iclass 39, count 2 2006.197.07:50:29.33#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.197.07:50:29.33#ibcon#[25=AT06-06\r\n] 2006.197.07:50:29.33#ibcon#*before write, iclass 39, count 2 2006.197.07:50:29.33#ibcon#enter sib2, iclass 39, count 2 2006.197.07:50:29.33#ibcon#flushed, iclass 39, count 2 2006.197.07:50:29.33#ibcon#about to write, iclass 39, count 2 2006.197.07:50:29.33#ibcon#wrote, iclass 39, count 2 2006.197.07:50:29.33#ibcon#about to read 3, iclass 39, count 2 2006.197.07:50:29.36#ibcon#read 3, iclass 39, count 2 2006.197.07:50:29.36#ibcon#about to read 4, iclass 39, count 2 2006.197.07:50:29.36#ibcon#read 4, iclass 39, count 2 2006.197.07:50:29.36#ibcon#about to read 5, iclass 39, count 2 2006.197.07:50:29.36#ibcon#read 5, iclass 39, count 2 2006.197.07:50:29.36#ibcon#about to read 6, iclass 39, count 2 2006.197.07:50:29.36#ibcon#read 6, iclass 39, count 2 2006.197.07:50:29.36#ibcon#end of sib2, iclass 39, count 2 2006.197.07:50:29.36#ibcon#*after write, iclass 39, count 2 2006.197.07:50:29.36#ibcon#*before return 0, iclass 39, count 2 2006.197.07:50:29.36#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.197.07:50:29.36#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.197.07:50:29.36#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.197.07:50:29.36#ibcon#ireg 7 cls_cnt 0 2006.197.07:50:29.36#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.197.07:50:29.48#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.197.07:50:29.48#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.197.07:50:29.48#ibcon#enter wrdev, iclass 39, count 0 2006.197.07:50:29.48#ibcon#first serial, iclass 39, count 0 2006.197.07:50:29.48#ibcon#enter sib2, iclass 39, count 0 2006.197.07:50:29.48#ibcon#flushed, iclass 39, count 0 2006.197.07:50:29.48#ibcon#about to write, iclass 39, count 0 2006.197.07:50:29.48#ibcon#wrote, iclass 39, count 0 2006.197.07:50:29.48#ibcon#about to read 3, iclass 39, count 0 2006.197.07:50:29.50#ibcon#read 3, iclass 39, count 0 2006.197.07:50:29.50#ibcon#about to read 4, iclass 39, count 0 2006.197.07:50:29.50#ibcon#read 4, iclass 39, count 0 2006.197.07:50:29.50#ibcon#about to read 5, iclass 39, count 0 2006.197.07:50:29.50#ibcon#read 5, iclass 39, count 0 2006.197.07:50:29.50#ibcon#about to read 6, iclass 39, count 0 2006.197.07:50:29.50#ibcon#read 6, iclass 39, count 0 2006.197.07:50:29.50#ibcon#end of sib2, iclass 39, count 0 2006.197.07:50:29.50#ibcon#*mode == 0, iclass 39, count 0 2006.197.07:50:29.50#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.197.07:50:29.50#ibcon#[25=USB\r\n] 2006.197.07:50:29.50#ibcon#*before write, iclass 39, count 0 2006.197.07:50:29.50#ibcon#enter sib2, iclass 39, count 0 2006.197.07:50:29.50#ibcon#flushed, iclass 39, count 0 2006.197.07:50:29.50#ibcon#about to write, iclass 39, count 0 2006.197.07:50:29.50#ibcon#wrote, iclass 39, count 0 2006.197.07:50:29.50#ibcon#about to read 3, iclass 39, count 0 2006.197.07:50:29.53#ibcon#read 3, iclass 39, count 0 2006.197.07:50:29.53#ibcon#about to read 4, iclass 39, count 0 2006.197.07:50:29.53#ibcon#read 4, iclass 39, count 0 2006.197.07:50:29.53#ibcon#about to read 5, iclass 39, count 0 2006.197.07:50:29.53#ibcon#read 5, iclass 39, count 0 2006.197.07:50:29.53#ibcon#about to read 6, iclass 39, count 0 2006.197.07:50:29.53#ibcon#read 6, iclass 39, count 0 2006.197.07:50:29.53#ibcon#end of sib2, iclass 39, count 0 2006.197.07:50:29.53#ibcon#*after write, iclass 39, count 0 2006.197.07:50:29.53#ibcon#*before return 0, iclass 39, count 0 2006.197.07:50:29.53#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.197.07:50:29.53#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.197.07:50:29.53#ibcon#about to clear, iclass 39 cls_cnt 0 2006.197.07:50:29.53#ibcon#cleared, iclass 39 cls_cnt 0 2006.197.07:50:29.53$vc4f8/valo=7,832.99 2006.197.07:50:29.53#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.197.07:50:29.53#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.197.07:50:29.53#ibcon#ireg 17 cls_cnt 0 2006.197.07:50:29.53#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.197.07:50:29.53#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.197.07:50:29.53#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.197.07:50:29.53#ibcon#enter wrdev, iclass 3, count 0 2006.197.07:50:29.53#ibcon#first serial, iclass 3, count 0 2006.197.07:50:29.53#ibcon#enter sib2, iclass 3, count 0 2006.197.07:50:29.53#ibcon#flushed, iclass 3, count 0 2006.197.07:50:29.53#ibcon#about to write, iclass 3, count 0 2006.197.07:50:29.53#ibcon#wrote, iclass 3, count 0 2006.197.07:50:29.53#ibcon#about to read 3, iclass 3, count 0 2006.197.07:50:29.55#ibcon#read 3, iclass 3, count 0 2006.197.07:50:29.55#ibcon#about to read 4, iclass 3, count 0 2006.197.07:50:29.55#ibcon#read 4, iclass 3, count 0 2006.197.07:50:29.55#ibcon#about to read 5, iclass 3, count 0 2006.197.07:50:29.55#ibcon#read 5, iclass 3, count 0 2006.197.07:50:29.55#ibcon#about to read 6, iclass 3, count 0 2006.197.07:50:29.55#ibcon#read 6, iclass 3, count 0 2006.197.07:50:29.55#ibcon#end of sib2, iclass 3, count 0 2006.197.07:50:29.55#ibcon#*mode == 0, iclass 3, count 0 2006.197.07:50:29.55#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.197.07:50:29.55#ibcon#[26=FRQ=07,832.99\r\n] 2006.197.07:50:29.55#ibcon#*before write, iclass 3, count 0 2006.197.07:50:29.55#ibcon#enter sib2, iclass 3, count 0 2006.197.07:50:29.55#ibcon#flushed, iclass 3, count 0 2006.197.07:50:29.55#ibcon#about to write, iclass 3, count 0 2006.197.07:50:29.55#ibcon#wrote, iclass 3, count 0 2006.197.07:50:29.55#ibcon#about to read 3, iclass 3, count 0 2006.197.07:50:29.59#ibcon#read 3, iclass 3, count 0 2006.197.07:50:29.59#ibcon#about to read 4, iclass 3, count 0 2006.197.07:50:29.59#ibcon#read 4, iclass 3, count 0 2006.197.07:50:29.59#ibcon#about to read 5, iclass 3, count 0 2006.197.07:50:29.59#ibcon#read 5, iclass 3, count 0 2006.197.07:50:29.59#ibcon#about to read 6, iclass 3, count 0 2006.197.07:50:29.59#ibcon#read 6, iclass 3, count 0 2006.197.07:50:29.59#ibcon#end of sib2, iclass 3, count 0 2006.197.07:50:29.59#ibcon#*after write, iclass 3, count 0 2006.197.07:50:29.59#ibcon#*before return 0, iclass 3, count 0 2006.197.07:50:29.59#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.197.07:50:29.59#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.197.07:50:29.59#ibcon#about to clear, iclass 3 cls_cnt 0 2006.197.07:50:29.59#ibcon#cleared, iclass 3 cls_cnt 0 2006.197.07:50:29.59$vc4f8/va=7,6 2006.197.07:50:29.59#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.197.07:50:29.59#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.197.07:50:29.59#ibcon#ireg 11 cls_cnt 2 2006.197.07:50:29.59#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.197.07:50:29.65#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.197.07:50:29.65#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.197.07:50:29.65#ibcon#enter wrdev, iclass 5, count 2 2006.197.07:50:29.65#ibcon#first serial, iclass 5, count 2 2006.197.07:50:29.65#ibcon#enter sib2, iclass 5, count 2 2006.197.07:50:29.65#ibcon#flushed, iclass 5, count 2 2006.197.07:50:29.65#ibcon#about to write, iclass 5, count 2 2006.197.07:50:29.65#ibcon#wrote, iclass 5, count 2 2006.197.07:50:29.65#ibcon#about to read 3, iclass 5, count 2 2006.197.07:50:29.67#ibcon#read 3, iclass 5, count 2 2006.197.07:50:29.67#ibcon#about to read 4, iclass 5, count 2 2006.197.07:50:29.67#ibcon#read 4, iclass 5, count 2 2006.197.07:50:29.67#ibcon#about to read 5, iclass 5, count 2 2006.197.07:50:29.67#ibcon#read 5, iclass 5, count 2 2006.197.07:50:29.67#ibcon#about to read 6, iclass 5, count 2 2006.197.07:50:29.67#ibcon#read 6, iclass 5, count 2 2006.197.07:50:29.67#ibcon#end of sib2, iclass 5, count 2 2006.197.07:50:29.67#ibcon#*mode == 0, iclass 5, count 2 2006.197.07:50:29.67#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.197.07:50:29.67#ibcon#[25=AT07-06\r\n] 2006.197.07:50:29.67#ibcon#*before write, iclass 5, count 2 2006.197.07:50:29.67#ibcon#enter sib2, iclass 5, count 2 2006.197.07:50:29.67#ibcon#flushed, iclass 5, count 2 2006.197.07:50:29.67#ibcon#about to write, iclass 5, count 2 2006.197.07:50:29.67#ibcon#wrote, iclass 5, count 2 2006.197.07:50:29.67#ibcon#about to read 3, iclass 5, count 2 2006.197.07:50:29.70#ibcon#read 3, iclass 5, count 2 2006.197.07:50:29.70#ibcon#about to read 4, iclass 5, count 2 2006.197.07:50:29.70#ibcon#read 4, iclass 5, count 2 2006.197.07:50:29.70#ibcon#about to read 5, iclass 5, count 2 2006.197.07:50:29.70#ibcon#read 5, iclass 5, count 2 2006.197.07:50:29.70#ibcon#about to read 6, iclass 5, count 2 2006.197.07:50:29.70#ibcon#read 6, iclass 5, count 2 2006.197.07:50:29.70#ibcon#end of sib2, iclass 5, count 2 2006.197.07:50:29.70#ibcon#*after write, iclass 5, count 2 2006.197.07:50:29.70#ibcon#*before return 0, iclass 5, count 2 2006.197.07:50:29.70#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.197.07:50:29.70#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.197.07:50:29.70#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.197.07:50:29.70#ibcon#ireg 7 cls_cnt 0 2006.197.07:50:29.70#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.197.07:50:29.82#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.197.07:50:29.82#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.197.07:50:29.82#ibcon#enter wrdev, iclass 5, count 0 2006.197.07:50:29.82#ibcon#first serial, iclass 5, count 0 2006.197.07:50:29.82#ibcon#enter sib2, iclass 5, count 0 2006.197.07:50:29.82#ibcon#flushed, iclass 5, count 0 2006.197.07:50:29.82#ibcon#about to write, iclass 5, count 0 2006.197.07:50:29.82#ibcon#wrote, iclass 5, count 0 2006.197.07:50:29.82#ibcon#about to read 3, iclass 5, count 0 2006.197.07:50:29.84#ibcon#read 3, iclass 5, count 0 2006.197.07:50:29.84#ibcon#about to read 4, iclass 5, count 0 2006.197.07:50:29.84#ibcon#read 4, iclass 5, count 0 2006.197.07:50:29.84#ibcon#about to read 5, iclass 5, count 0 2006.197.07:50:29.84#ibcon#read 5, iclass 5, count 0 2006.197.07:50:29.84#ibcon#about to read 6, iclass 5, count 0 2006.197.07:50:29.84#ibcon#read 6, iclass 5, count 0 2006.197.07:50:29.84#ibcon#end of sib2, iclass 5, count 0 2006.197.07:50:29.84#ibcon#*mode == 0, iclass 5, count 0 2006.197.07:50:29.84#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.197.07:50:29.84#ibcon#[25=USB\r\n] 2006.197.07:50:29.84#ibcon#*before write, iclass 5, count 0 2006.197.07:50:29.84#ibcon#enter sib2, iclass 5, count 0 2006.197.07:50:29.84#ibcon#flushed, iclass 5, count 0 2006.197.07:50:29.84#ibcon#about to write, iclass 5, count 0 2006.197.07:50:29.84#ibcon#wrote, iclass 5, count 0 2006.197.07:50:29.84#ibcon#about to read 3, iclass 5, count 0 2006.197.07:50:29.87#ibcon#read 3, iclass 5, count 0 2006.197.07:50:29.87#ibcon#about to read 4, iclass 5, count 0 2006.197.07:50:29.87#ibcon#read 4, iclass 5, count 0 2006.197.07:50:29.87#ibcon#about to read 5, iclass 5, count 0 2006.197.07:50:29.87#ibcon#read 5, iclass 5, count 0 2006.197.07:50:29.87#ibcon#about to read 6, iclass 5, count 0 2006.197.07:50:29.87#ibcon#read 6, iclass 5, count 0 2006.197.07:50:29.87#ibcon#end of sib2, iclass 5, count 0 2006.197.07:50:29.87#ibcon#*after write, iclass 5, count 0 2006.197.07:50:29.87#ibcon#*before return 0, iclass 5, count 0 2006.197.07:50:29.87#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.197.07:50:29.87#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.197.07:50:29.87#ibcon#about to clear, iclass 5 cls_cnt 0 2006.197.07:50:29.87#ibcon#cleared, iclass 5 cls_cnt 0 2006.197.07:50:29.87$vc4f8/valo=8,852.99 2006.197.07:50:29.87#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.197.07:50:29.87#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.197.07:50:29.87#ibcon#ireg 17 cls_cnt 0 2006.197.07:50:29.87#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.197.07:50:29.87#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.197.07:50:29.87#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.197.07:50:29.87#ibcon#enter wrdev, iclass 7, count 0 2006.197.07:50:29.87#ibcon#first serial, iclass 7, count 0 2006.197.07:50:29.87#ibcon#enter sib2, iclass 7, count 0 2006.197.07:50:29.87#ibcon#flushed, iclass 7, count 0 2006.197.07:50:29.87#ibcon#about to write, iclass 7, count 0 2006.197.07:50:29.87#ibcon#wrote, iclass 7, count 0 2006.197.07:50:29.87#ibcon#about to read 3, iclass 7, count 0 2006.197.07:50:29.89#ibcon#read 3, iclass 7, count 0 2006.197.07:50:29.89#ibcon#about to read 4, iclass 7, count 0 2006.197.07:50:29.89#ibcon#read 4, iclass 7, count 0 2006.197.07:50:29.89#ibcon#about to read 5, iclass 7, count 0 2006.197.07:50:29.89#ibcon#read 5, iclass 7, count 0 2006.197.07:50:29.89#ibcon#about to read 6, iclass 7, count 0 2006.197.07:50:29.89#ibcon#read 6, iclass 7, count 0 2006.197.07:50:29.89#ibcon#end of sib2, iclass 7, count 0 2006.197.07:50:29.89#ibcon#*mode == 0, iclass 7, count 0 2006.197.07:50:29.89#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.197.07:50:29.89#ibcon#[26=FRQ=08,852.99\r\n] 2006.197.07:50:29.89#ibcon#*before write, iclass 7, count 0 2006.197.07:50:29.89#ibcon#enter sib2, iclass 7, count 0 2006.197.07:50:29.89#ibcon#flushed, iclass 7, count 0 2006.197.07:50:29.89#ibcon#about to write, iclass 7, count 0 2006.197.07:50:29.89#ibcon#wrote, iclass 7, count 0 2006.197.07:50:29.89#ibcon#about to read 3, iclass 7, count 0 2006.197.07:50:29.93#ibcon#read 3, iclass 7, count 0 2006.197.07:50:29.93#ibcon#about to read 4, iclass 7, count 0 2006.197.07:50:29.93#ibcon#read 4, iclass 7, count 0 2006.197.07:50:29.93#ibcon#about to read 5, iclass 7, count 0 2006.197.07:50:29.93#ibcon#read 5, iclass 7, count 0 2006.197.07:50:29.93#ibcon#about to read 6, iclass 7, count 0 2006.197.07:50:29.93#ibcon#read 6, iclass 7, count 0 2006.197.07:50:29.93#ibcon#end of sib2, iclass 7, count 0 2006.197.07:50:29.93#ibcon#*after write, iclass 7, count 0 2006.197.07:50:29.93#ibcon#*before return 0, iclass 7, count 0 2006.197.07:50:29.93#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.197.07:50:29.93#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.197.07:50:29.93#ibcon#about to clear, iclass 7 cls_cnt 0 2006.197.07:50:29.93#ibcon#cleared, iclass 7 cls_cnt 0 2006.197.07:50:29.93$vc4f8/va=8,7 2006.197.07:50:29.93#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.197.07:50:29.93#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.197.07:50:29.93#ibcon#ireg 11 cls_cnt 2 2006.197.07:50:29.93#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.197.07:50:29.99#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.197.07:50:29.99#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.197.07:50:29.99#ibcon#enter wrdev, iclass 11, count 2 2006.197.07:50:29.99#ibcon#first serial, iclass 11, count 2 2006.197.07:50:29.99#ibcon#enter sib2, iclass 11, count 2 2006.197.07:50:29.99#ibcon#flushed, iclass 11, count 2 2006.197.07:50:29.99#ibcon#about to write, iclass 11, count 2 2006.197.07:50:29.99#ibcon#wrote, iclass 11, count 2 2006.197.07:50:29.99#ibcon#about to read 3, iclass 11, count 2 2006.197.07:50:30.01#ibcon#read 3, iclass 11, count 2 2006.197.07:50:30.01#ibcon#about to read 4, iclass 11, count 2 2006.197.07:50:30.01#ibcon#read 4, iclass 11, count 2 2006.197.07:50:30.01#ibcon#about to read 5, iclass 11, count 2 2006.197.07:50:30.01#ibcon#read 5, iclass 11, count 2 2006.197.07:50:30.01#ibcon#about to read 6, iclass 11, count 2 2006.197.07:50:30.01#ibcon#read 6, iclass 11, count 2 2006.197.07:50:30.01#ibcon#end of sib2, iclass 11, count 2 2006.197.07:50:30.01#ibcon#*mode == 0, iclass 11, count 2 2006.197.07:50:30.01#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.197.07:50:30.01#ibcon#[25=AT08-07\r\n] 2006.197.07:50:30.01#ibcon#*before write, iclass 11, count 2 2006.197.07:50:30.01#ibcon#enter sib2, iclass 11, count 2 2006.197.07:50:30.01#ibcon#flushed, iclass 11, count 2 2006.197.07:50:30.01#ibcon#about to write, iclass 11, count 2 2006.197.07:50:30.01#ibcon#wrote, iclass 11, count 2 2006.197.07:50:30.01#ibcon#about to read 3, iclass 11, count 2 2006.197.07:50:30.04#ibcon#read 3, iclass 11, count 2 2006.197.07:50:30.04#ibcon#about to read 4, iclass 11, count 2 2006.197.07:50:30.04#ibcon#read 4, iclass 11, count 2 2006.197.07:50:30.04#ibcon#about to read 5, iclass 11, count 2 2006.197.07:50:30.04#ibcon#read 5, iclass 11, count 2 2006.197.07:50:30.04#ibcon#about to read 6, iclass 11, count 2 2006.197.07:50:30.04#ibcon#read 6, iclass 11, count 2 2006.197.07:50:30.04#ibcon#end of sib2, iclass 11, count 2 2006.197.07:50:30.04#ibcon#*after write, iclass 11, count 2 2006.197.07:50:30.04#ibcon#*before return 0, iclass 11, count 2 2006.197.07:50:30.04#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.197.07:50:30.04#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.197.07:50:30.04#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.197.07:50:30.04#ibcon#ireg 7 cls_cnt 0 2006.197.07:50:30.04#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.197.07:50:30.16#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.197.07:50:30.16#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.197.07:50:30.16#ibcon#enter wrdev, iclass 11, count 0 2006.197.07:50:30.16#ibcon#first serial, iclass 11, count 0 2006.197.07:50:30.16#ibcon#enter sib2, iclass 11, count 0 2006.197.07:50:30.16#ibcon#flushed, iclass 11, count 0 2006.197.07:50:30.16#ibcon#about to write, iclass 11, count 0 2006.197.07:50:30.16#ibcon#wrote, iclass 11, count 0 2006.197.07:50:30.16#ibcon#about to read 3, iclass 11, count 0 2006.197.07:50:30.18#ibcon#read 3, iclass 11, count 0 2006.197.07:50:30.18#ibcon#about to read 4, iclass 11, count 0 2006.197.07:50:30.18#ibcon#read 4, iclass 11, count 0 2006.197.07:50:30.18#ibcon#about to read 5, iclass 11, count 0 2006.197.07:50:30.18#ibcon#read 5, iclass 11, count 0 2006.197.07:50:30.18#ibcon#about to read 6, iclass 11, count 0 2006.197.07:50:30.18#ibcon#read 6, iclass 11, count 0 2006.197.07:50:30.18#ibcon#end of sib2, iclass 11, count 0 2006.197.07:50:30.18#ibcon#*mode == 0, iclass 11, count 0 2006.197.07:50:30.18#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.197.07:50:30.18#ibcon#[25=USB\r\n] 2006.197.07:50:30.18#ibcon#*before write, iclass 11, count 0 2006.197.07:50:30.18#ibcon#enter sib2, iclass 11, count 0 2006.197.07:50:30.18#ibcon#flushed, iclass 11, count 0 2006.197.07:50:30.18#ibcon#about to write, iclass 11, count 0 2006.197.07:50:30.18#ibcon#wrote, iclass 11, count 0 2006.197.07:50:30.18#ibcon#about to read 3, iclass 11, count 0 2006.197.07:50:30.21#ibcon#read 3, iclass 11, count 0 2006.197.07:50:30.21#ibcon#about to read 4, iclass 11, count 0 2006.197.07:50:30.21#ibcon#read 4, iclass 11, count 0 2006.197.07:50:30.21#ibcon#about to read 5, iclass 11, count 0 2006.197.07:50:30.21#ibcon#read 5, iclass 11, count 0 2006.197.07:50:30.21#ibcon#about to read 6, iclass 11, count 0 2006.197.07:50:30.21#ibcon#read 6, iclass 11, count 0 2006.197.07:50:30.21#ibcon#end of sib2, iclass 11, count 0 2006.197.07:50:30.21#ibcon#*after write, iclass 11, count 0 2006.197.07:50:30.21#ibcon#*before return 0, iclass 11, count 0 2006.197.07:50:30.21#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.197.07:50:30.21#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.197.07:50:30.21#ibcon#about to clear, iclass 11 cls_cnt 0 2006.197.07:50:30.21#ibcon#cleared, iclass 11 cls_cnt 0 2006.197.07:50:30.21$vc4f8/vblo=1,632.99 2006.197.07:50:30.21#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.197.07:50:30.21#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.197.07:50:30.21#ibcon#ireg 17 cls_cnt 0 2006.197.07:50:30.21#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.197.07:50:30.21#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.197.07:50:30.21#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.197.07:50:30.21#ibcon#enter wrdev, iclass 13, count 0 2006.197.07:50:30.21#ibcon#first serial, iclass 13, count 0 2006.197.07:50:30.21#ibcon#enter sib2, iclass 13, count 0 2006.197.07:50:30.21#ibcon#flushed, iclass 13, count 0 2006.197.07:50:30.21#ibcon#about to write, iclass 13, count 0 2006.197.07:50:30.21#ibcon#wrote, iclass 13, count 0 2006.197.07:50:30.21#ibcon#about to read 3, iclass 13, count 0 2006.197.07:50:30.23#ibcon#read 3, iclass 13, count 0 2006.197.07:50:30.23#ibcon#about to read 4, iclass 13, count 0 2006.197.07:50:30.23#ibcon#read 4, iclass 13, count 0 2006.197.07:50:30.23#ibcon#about to read 5, iclass 13, count 0 2006.197.07:50:30.23#ibcon#read 5, iclass 13, count 0 2006.197.07:50:30.23#ibcon#about to read 6, iclass 13, count 0 2006.197.07:50:30.23#ibcon#read 6, iclass 13, count 0 2006.197.07:50:30.23#ibcon#end of sib2, iclass 13, count 0 2006.197.07:50:30.23#ibcon#*mode == 0, iclass 13, count 0 2006.197.07:50:30.23#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.197.07:50:30.23#ibcon#[28=FRQ=01,632.99\r\n] 2006.197.07:50:30.23#ibcon#*before write, iclass 13, count 0 2006.197.07:50:30.23#ibcon#enter sib2, iclass 13, count 0 2006.197.07:50:30.23#ibcon#flushed, iclass 13, count 0 2006.197.07:50:30.23#ibcon#about to write, iclass 13, count 0 2006.197.07:50:30.23#ibcon#wrote, iclass 13, count 0 2006.197.07:50:30.23#ibcon#about to read 3, iclass 13, count 0 2006.197.07:50:30.27#ibcon#read 3, iclass 13, count 0 2006.197.07:50:30.27#ibcon#about to read 4, iclass 13, count 0 2006.197.07:50:30.27#ibcon#read 4, iclass 13, count 0 2006.197.07:50:30.27#ibcon#about to read 5, iclass 13, count 0 2006.197.07:50:30.27#ibcon#read 5, iclass 13, count 0 2006.197.07:50:30.27#ibcon#about to read 6, iclass 13, count 0 2006.197.07:50:30.27#ibcon#read 6, iclass 13, count 0 2006.197.07:50:30.27#ibcon#end of sib2, iclass 13, count 0 2006.197.07:50:30.27#ibcon#*after write, iclass 13, count 0 2006.197.07:50:30.27#ibcon#*before return 0, iclass 13, count 0 2006.197.07:50:30.27#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.197.07:50:30.27#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.197.07:50:30.27#ibcon#about to clear, iclass 13 cls_cnt 0 2006.197.07:50:30.27#ibcon#cleared, iclass 13 cls_cnt 0 2006.197.07:50:30.27$vc4f8/vb=1,4 2006.197.07:50:30.27#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.197.07:50:30.27#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.197.07:50:30.27#ibcon#ireg 11 cls_cnt 2 2006.197.07:50:30.27#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.197.07:50:30.27#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.197.07:50:30.27#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.197.07:50:30.27#ibcon#enter wrdev, iclass 15, count 2 2006.197.07:50:30.27#ibcon#first serial, iclass 15, count 2 2006.197.07:50:30.27#ibcon#enter sib2, iclass 15, count 2 2006.197.07:50:30.27#ibcon#flushed, iclass 15, count 2 2006.197.07:50:30.27#ibcon#about to write, iclass 15, count 2 2006.197.07:50:30.27#ibcon#wrote, iclass 15, count 2 2006.197.07:50:30.27#ibcon#about to read 3, iclass 15, count 2 2006.197.07:50:30.29#ibcon#read 3, iclass 15, count 2 2006.197.07:50:30.29#ibcon#about to read 4, iclass 15, count 2 2006.197.07:50:30.29#ibcon#read 4, iclass 15, count 2 2006.197.07:50:30.29#ibcon#about to read 5, iclass 15, count 2 2006.197.07:50:30.29#ibcon#read 5, iclass 15, count 2 2006.197.07:50:30.29#ibcon#about to read 6, iclass 15, count 2 2006.197.07:50:30.29#ibcon#read 6, iclass 15, count 2 2006.197.07:50:30.29#ibcon#end of sib2, iclass 15, count 2 2006.197.07:50:30.29#ibcon#*mode == 0, iclass 15, count 2 2006.197.07:50:30.29#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.197.07:50:30.29#ibcon#[27=AT01-04\r\n] 2006.197.07:50:30.29#ibcon#*before write, iclass 15, count 2 2006.197.07:50:30.29#ibcon#enter sib2, iclass 15, count 2 2006.197.07:50:30.29#ibcon#flushed, iclass 15, count 2 2006.197.07:50:30.29#ibcon#about to write, iclass 15, count 2 2006.197.07:50:30.29#ibcon#wrote, iclass 15, count 2 2006.197.07:50:30.29#ibcon#about to read 3, iclass 15, count 2 2006.197.07:50:30.32#ibcon#read 3, iclass 15, count 2 2006.197.07:50:30.32#ibcon#about to read 4, iclass 15, count 2 2006.197.07:50:30.32#ibcon#read 4, iclass 15, count 2 2006.197.07:50:30.32#ibcon#about to read 5, iclass 15, count 2 2006.197.07:50:30.32#ibcon#read 5, iclass 15, count 2 2006.197.07:50:30.32#ibcon#about to read 6, iclass 15, count 2 2006.197.07:50:30.32#ibcon#read 6, iclass 15, count 2 2006.197.07:50:30.32#ibcon#end of sib2, iclass 15, count 2 2006.197.07:50:30.32#ibcon#*after write, iclass 15, count 2 2006.197.07:50:30.32#ibcon#*before return 0, iclass 15, count 2 2006.197.07:50:30.32#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.197.07:50:30.32#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.197.07:50:30.32#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.197.07:50:30.32#ibcon#ireg 7 cls_cnt 0 2006.197.07:50:30.32#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.197.07:50:30.44#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.197.07:50:30.44#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.197.07:50:30.44#ibcon#enter wrdev, iclass 15, count 0 2006.197.07:50:30.44#ibcon#first serial, iclass 15, count 0 2006.197.07:50:30.44#ibcon#enter sib2, iclass 15, count 0 2006.197.07:50:30.44#ibcon#flushed, iclass 15, count 0 2006.197.07:50:30.44#ibcon#about to write, iclass 15, count 0 2006.197.07:50:30.44#ibcon#wrote, iclass 15, count 0 2006.197.07:50:30.44#ibcon#about to read 3, iclass 15, count 0 2006.197.07:50:30.46#ibcon#read 3, iclass 15, count 0 2006.197.07:50:30.46#ibcon#about to read 4, iclass 15, count 0 2006.197.07:50:30.46#ibcon#read 4, iclass 15, count 0 2006.197.07:50:30.46#ibcon#about to read 5, iclass 15, count 0 2006.197.07:50:30.46#ibcon#read 5, iclass 15, count 0 2006.197.07:50:30.46#ibcon#about to read 6, iclass 15, count 0 2006.197.07:50:30.46#ibcon#read 6, iclass 15, count 0 2006.197.07:50:30.46#ibcon#end of sib2, iclass 15, count 0 2006.197.07:50:30.46#ibcon#*mode == 0, iclass 15, count 0 2006.197.07:50:30.46#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.197.07:50:30.46#ibcon#[27=USB\r\n] 2006.197.07:50:30.46#ibcon#*before write, iclass 15, count 0 2006.197.07:50:30.46#ibcon#enter sib2, iclass 15, count 0 2006.197.07:50:30.46#ibcon#flushed, iclass 15, count 0 2006.197.07:50:30.46#ibcon#about to write, iclass 15, count 0 2006.197.07:50:30.46#ibcon#wrote, iclass 15, count 0 2006.197.07:50:30.46#ibcon#about to read 3, iclass 15, count 0 2006.197.07:50:30.49#ibcon#read 3, iclass 15, count 0 2006.197.07:50:30.49#ibcon#about to read 4, iclass 15, count 0 2006.197.07:50:30.49#ibcon#read 4, iclass 15, count 0 2006.197.07:50:30.49#ibcon#about to read 5, iclass 15, count 0 2006.197.07:50:30.49#ibcon#read 5, iclass 15, count 0 2006.197.07:50:30.49#ibcon#about to read 6, iclass 15, count 0 2006.197.07:50:30.49#ibcon#read 6, iclass 15, count 0 2006.197.07:50:30.49#ibcon#end of sib2, iclass 15, count 0 2006.197.07:50:30.49#ibcon#*after write, iclass 15, count 0 2006.197.07:50:30.49#ibcon#*before return 0, iclass 15, count 0 2006.197.07:50:30.49#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.197.07:50:30.49#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.197.07:50:30.49#ibcon#about to clear, iclass 15 cls_cnt 0 2006.197.07:50:30.49#ibcon#cleared, iclass 15 cls_cnt 0 2006.197.07:50:30.49$vc4f8/vblo=2,640.99 2006.197.07:50:30.49#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.197.07:50:30.49#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.197.07:50:30.49#ibcon#ireg 17 cls_cnt 0 2006.197.07:50:30.49#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.197.07:50:30.49#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.197.07:50:30.49#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.197.07:50:30.49#ibcon#enter wrdev, iclass 17, count 0 2006.197.07:50:30.49#ibcon#first serial, iclass 17, count 0 2006.197.07:50:30.49#ibcon#enter sib2, iclass 17, count 0 2006.197.07:50:30.49#ibcon#flushed, iclass 17, count 0 2006.197.07:50:30.49#ibcon#about to write, iclass 17, count 0 2006.197.07:50:30.49#ibcon#wrote, iclass 17, count 0 2006.197.07:50:30.49#ibcon#about to read 3, iclass 17, count 0 2006.197.07:50:30.51#ibcon#read 3, iclass 17, count 0 2006.197.07:50:30.51#ibcon#about to read 4, iclass 17, count 0 2006.197.07:50:30.51#ibcon#read 4, iclass 17, count 0 2006.197.07:50:30.51#ibcon#about to read 5, iclass 17, count 0 2006.197.07:50:30.51#ibcon#read 5, iclass 17, count 0 2006.197.07:50:30.51#ibcon#about to read 6, iclass 17, count 0 2006.197.07:50:30.51#ibcon#read 6, iclass 17, count 0 2006.197.07:50:30.51#ibcon#end of sib2, iclass 17, count 0 2006.197.07:50:30.51#ibcon#*mode == 0, iclass 17, count 0 2006.197.07:50:30.51#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.197.07:50:30.51#ibcon#[28=FRQ=02,640.99\r\n] 2006.197.07:50:30.51#ibcon#*before write, iclass 17, count 0 2006.197.07:50:30.51#ibcon#enter sib2, iclass 17, count 0 2006.197.07:50:30.51#ibcon#flushed, iclass 17, count 0 2006.197.07:50:30.51#ibcon#about to write, iclass 17, count 0 2006.197.07:50:30.51#ibcon#wrote, iclass 17, count 0 2006.197.07:50:30.51#ibcon#about to read 3, iclass 17, count 0 2006.197.07:50:30.55#ibcon#read 3, iclass 17, count 0 2006.197.07:50:30.55#ibcon#about to read 4, iclass 17, count 0 2006.197.07:50:30.55#ibcon#read 4, iclass 17, count 0 2006.197.07:50:30.55#ibcon#about to read 5, iclass 17, count 0 2006.197.07:50:30.55#ibcon#read 5, iclass 17, count 0 2006.197.07:50:30.55#ibcon#about to read 6, iclass 17, count 0 2006.197.07:50:30.55#ibcon#read 6, iclass 17, count 0 2006.197.07:50:30.55#ibcon#end of sib2, iclass 17, count 0 2006.197.07:50:30.55#ibcon#*after write, iclass 17, count 0 2006.197.07:50:30.55#ibcon#*before return 0, iclass 17, count 0 2006.197.07:50:30.55#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.197.07:50:30.55#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.197.07:50:30.55#ibcon#about to clear, iclass 17 cls_cnt 0 2006.197.07:50:30.55#ibcon#cleared, iclass 17 cls_cnt 0 2006.197.07:50:30.55$vc4f8/vb=2,4 2006.197.07:50:30.55#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.197.07:50:30.55#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.197.07:50:30.55#ibcon#ireg 11 cls_cnt 2 2006.197.07:50:30.55#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.197.07:50:30.61#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.197.07:50:30.61#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.197.07:50:30.61#ibcon#enter wrdev, iclass 19, count 2 2006.197.07:50:30.61#ibcon#first serial, iclass 19, count 2 2006.197.07:50:30.61#ibcon#enter sib2, iclass 19, count 2 2006.197.07:50:30.61#ibcon#flushed, iclass 19, count 2 2006.197.07:50:30.61#ibcon#about to write, iclass 19, count 2 2006.197.07:50:30.61#ibcon#wrote, iclass 19, count 2 2006.197.07:50:30.61#ibcon#about to read 3, iclass 19, count 2 2006.197.07:50:30.63#ibcon#read 3, iclass 19, count 2 2006.197.07:50:30.63#ibcon#about to read 4, iclass 19, count 2 2006.197.07:50:30.63#ibcon#read 4, iclass 19, count 2 2006.197.07:50:30.63#ibcon#about to read 5, iclass 19, count 2 2006.197.07:50:30.63#ibcon#read 5, iclass 19, count 2 2006.197.07:50:30.63#ibcon#about to read 6, iclass 19, count 2 2006.197.07:50:30.63#ibcon#read 6, iclass 19, count 2 2006.197.07:50:30.63#ibcon#end of sib2, iclass 19, count 2 2006.197.07:50:30.63#ibcon#*mode == 0, iclass 19, count 2 2006.197.07:50:30.63#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.197.07:50:30.63#ibcon#[27=AT02-04\r\n] 2006.197.07:50:30.63#ibcon#*before write, iclass 19, count 2 2006.197.07:50:30.63#ibcon#enter sib2, iclass 19, count 2 2006.197.07:50:30.63#ibcon#flushed, iclass 19, count 2 2006.197.07:50:30.63#ibcon#about to write, iclass 19, count 2 2006.197.07:50:30.63#ibcon#wrote, iclass 19, count 2 2006.197.07:50:30.63#ibcon#about to read 3, iclass 19, count 2 2006.197.07:50:30.66#ibcon#read 3, iclass 19, count 2 2006.197.07:50:30.66#ibcon#about to read 4, iclass 19, count 2 2006.197.07:50:30.66#ibcon#read 4, iclass 19, count 2 2006.197.07:50:30.66#ibcon#about to read 5, iclass 19, count 2 2006.197.07:50:30.66#ibcon#read 5, iclass 19, count 2 2006.197.07:50:30.66#ibcon#about to read 6, iclass 19, count 2 2006.197.07:50:30.66#ibcon#read 6, iclass 19, count 2 2006.197.07:50:30.66#ibcon#end of sib2, iclass 19, count 2 2006.197.07:50:30.66#ibcon#*after write, iclass 19, count 2 2006.197.07:50:30.66#ibcon#*before return 0, iclass 19, count 2 2006.197.07:50:30.66#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.197.07:50:30.66#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.197.07:50:30.66#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.197.07:50:30.66#ibcon#ireg 7 cls_cnt 0 2006.197.07:50:30.66#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.197.07:50:30.78#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.197.07:50:30.78#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.197.07:50:30.78#ibcon#enter wrdev, iclass 19, count 0 2006.197.07:50:30.78#ibcon#first serial, iclass 19, count 0 2006.197.07:50:30.78#ibcon#enter sib2, iclass 19, count 0 2006.197.07:50:30.78#ibcon#flushed, iclass 19, count 0 2006.197.07:50:30.78#ibcon#about to write, iclass 19, count 0 2006.197.07:50:30.78#ibcon#wrote, iclass 19, count 0 2006.197.07:50:30.78#ibcon#about to read 3, iclass 19, count 0 2006.197.07:50:30.80#ibcon#read 3, iclass 19, count 0 2006.197.07:50:30.80#ibcon#about to read 4, iclass 19, count 0 2006.197.07:50:30.80#ibcon#read 4, iclass 19, count 0 2006.197.07:50:30.80#ibcon#about to read 5, iclass 19, count 0 2006.197.07:50:30.80#ibcon#read 5, iclass 19, count 0 2006.197.07:50:30.80#ibcon#about to read 6, iclass 19, count 0 2006.197.07:50:30.80#ibcon#read 6, iclass 19, count 0 2006.197.07:50:30.80#ibcon#end of sib2, iclass 19, count 0 2006.197.07:50:30.80#ibcon#*mode == 0, iclass 19, count 0 2006.197.07:50:30.80#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.197.07:50:30.80#ibcon#[27=USB\r\n] 2006.197.07:50:30.80#ibcon#*before write, iclass 19, count 0 2006.197.07:50:30.80#ibcon#enter sib2, iclass 19, count 0 2006.197.07:50:30.80#ibcon#flushed, iclass 19, count 0 2006.197.07:50:30.80#ibcon#about to write, iclass 19, count 0 2006.197.07:50:30.80#ibcon#wrote, iclass 19, count 0 2006.197.07:50:30.80#ibcon#about to read 3, iclass 19, count 0 2006.197.07:50:30.83#ibcon#read 3, iclass 19, count 0 2006.197.07:50:30.83#ibcon#about to read 4, iclass 19, count 0 2006.197.07:50:30.83#ibcon#read 4, iclass 19, count 0 2006.197.07:50:30.83#ibcon#about to read 5, iclass 19, count 0 2006.197.07:50:30.83#ibcon#read 5, iclass 19, count 0 2006.197.07:50:30.83#ibcon#about to read 6, iclass 19, count 0 2006.197.07:50:30.83#ibcon#read 6, iclass 19, count 0 2006.197.07:50:30.83#ibcon#end of sib2, iclass 19, count 0 2006.197.07:50:30.83#ibcon#*after write, iclass 19, count 0 2006.197.07:50:30.83#ibcon#*before return 0, iclass 19, count 0 2006.197.07:50:30.83#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.197.07:50:30.83#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.197.07:50:30.83#ibcon#about to clear, iclass 19 cls_cnt 0 2006.197.07:50:30.83#ibcon#cleared, iclass 19 cls_cnt 0 2006.197.07:50:30.83$vc4f8/vblo=3,656.99 2006.197.07:50:30.83#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.197.07:50:30.83#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.197.07:50:30.83#ibcon#ireg 17 cls_cnt 0 2006.197.07:50:30.83#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.197.07:50:30.83#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.197.07:50:30.83#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.197.07:50:30.83#ibcon#enter wrdev, iclass 21, count 0 2006.197.07:50:30.83#ibcon#first serial, iclass 21, count 0 2006.197.07:50:30.83#ibcon#enter sib2, iclass 21, count 0 2006.197.07:50:30.83#ibcon#flushed, iclass 21, count 0 2006.197.07:50:30.83#ibcon#about to write, iclass 21, count 0 2006.197.07:50:30.83#ibcon#wrote, iclass 21, count 0 2006.197.07:50:30.83#ibcon#about to read 3, iclass 21, count 0 2006.197.07:50:30.85#ibcon#read 3, iclass 21, count 0 2006.197.07:50:30.85#ibcon#about to read 4, iclass 21, count 0 2006.197.07:50:30.85#ibcon#read 4, iclass 21, count 0 2006.197.07:50:30.85#ibcon#about to read 5, iclass 21, count 0 2006.197.07:50:30.85#ibcon#read 5, iclass 21, count 0 2006.197.07:50:30.85#ibcon#about to read 6, iclass 21, count 0 2006.197.07:50:30.85#ibcon#read 6, iclass 21, count 0 2006.197.07:50:30.85#ibcon#end of sib2, iclass 21, count 0 2006.197.07:50:30.85#ibcon#*mode == 0, iclass 21, count 0 2006.197.07:50:30.85#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.197.07:50:30.85#ibcon#[28=FRQ=03,656.99\r\n] 2006.197.07:50:30.85#ibcon#*before write, iclass 21, count 0 2006.197.07:50:30.85#ibcon#enter sib2, iclass 21, count 0 2006.197.07:50:30.85#ibcon#flushed, iclass 21, count 0 2006.197.07:50:30.85#ibcon#about to write, iclass 21, count 0 2006.197.07:50:30.85#ibcon#wrote, iclass 21, count 0 2006.197.07:50:30.85#ibcon#about to read 3, iclass 21, count 0 2006.197.07:50:30.89#ibcon#read 3, iclass 21, count 0 2006.197.07:50:30.89#ibcon#about to read 4, iclass 21, count 0 2006.197.07:50:30.89#ibcon#read 4, iclass 21, count 0 2006.197.07:50:30.89#ibcon#about to read 5, iclass 21, count 0 2006.197.07:50:30.89#ibcon#read 5, iclass 21, count 0 2006.197.07:50:30.89#ibcon#about to read 6, iclass 21, count 0 2006.197.07:50:30.89#ibcon#read 6, iclass 21, count 0 2006.197.07:50:30.89#ibcon#end of sib2, iclass 21, count 0 2006.197.07:50:30.89#ibcon#*after write, iclass 21, count 0 2006.197.07:50:30.89#ibcon#*before return 0, iclass 21, count 0 2006.197.07:50:30.89#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.197.07:50:30.89#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.197.07:50:30.89#ibcon#about to clear, iclass 21 cls_cnt 0 2006.197.07:50:30.89#ibcon#cleared, iclass 21 cls_cnt 0 2006.197.07:50:30.89$vc4f8/vb=3,4 2006.197.07:50:30.89#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.197.07:50:30.89#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.197.07:50:30.89#ibcon#ireg 11 cls_cnt 2 2006.197.07:50:30.89#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.197.07:50:30.95#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.197.07:50:30.95#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.197.07:50:30.95#ibcon#enter wrdev, iclass 23, count 2 2006.197.07:50:30.95#ibcon#first serial, iclass 23, count 2 2006.197.07:50:30.95#ibcon#enter sib2, iclass 23, count 2 2006.197.07:50:30.95#ibcon#flushed, iclass 23, count 2 2006.197.07:50:30.95#ibcon#about to write, iclass 23, count 2 2006.197.07:50:30.95#ibcon#wrote, iclass 23, count 2 2006.197.07:50:30.95#ibcon#about to read 3, iclass 23, count 2 2006.197.07:50:30.97#ibcon#read 3, iclass 23, count 2 2006.197.07:50:30.97#ibcon#about to read 4, iclass 23, count 2 2006.197.07:50:30.97#ibcon#read 4, iclass 23, count 2 2006.197.07:50:30.97#ibcon#about to read 5, iclass 23, count 2 2006.197.07:50:30.97#ibcon#read 5, iclass 23, count 2 2006.197.07:50:30.97#ibcon#about to read 6, iclass 23, count 2 2006.197.07:50:30.97#ibcon#read 6, iclass 23, count 2 2006.197.07:50:30.97#ibcon#end of sib2, iclass 23, count 2 2006.197.07:50:30.97#ibcon#*mode == 0, iclass 23, count 2 2006.197.07:50:30.97#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.197.07:50:30.97#ibcon#[27=AT03-04\r\n] 2006.197.07:50:30.97#ibcon#*before write, iclass 23, count 2 2006.197.07:50:30.97#ibcon#enter sib2, iclass 23, count 2 2006.197.07:50:30.97#ibcon#flushed, iclass 23, count 2 2006.197.07:50:30.97#ibcon#about to write, iclass 23, count 2 2006.197.07:50:30.97#ibcon#wrote, iclass 23, count 2 2006.197.07:50:30.97#ibcon#about to read 3, iclass 23, count 2 2006.197.07:50:31.00#ibcon#read 3, iclass 23, count 2 2006.197.07:50:31.00#ibcon#about to read 4, iclass 23, count 2 2006.197.07:50:31.00#ibcon#read 4, iclass 23, count 2 2006.197.07:50:31.00#ibcon#about to read 5, iclass 23, count 2 2006.197.07:50:31.00#ibcon#read 5, iclass 23, count 2 2006.197.07:50:31.00#ibcon#about to read 6, iclass 23, count 2 2006.197.07:50:31.00#ibcon#read 6, iclass 23, count 2 2006.197.07:50:31.00#ibcon#end of sib2, iclass 23, count 2 2006.197.07:50:31.00#ibcon#*after write, iclass 23, count 2 2006.197.07:50:31.00#ibcon#*before return 0, iclass 23, count 2 2006.197.07:50:31.00#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.197.07:50:31.00#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.197.07:50:31.00#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.197.07:50:31.00#ibcon#ireg 7 cls_cnt 0 2006.197.07:50:31.00#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.197.07:50:31.12#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.197.07:50:31.12#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.197.07:50:31.12#ibcon#enter wrdev, iclass 23, count 0 2006.197.07:50:31.12#ibcon#first serial, iclass 23, count 0 2006.197.07:50:31.12#ibcon#enter sib2, iclass 23, count 0 2006.197.07:50:31.12#ibcon#flushed, iclass 23, count 0 2006.197.07:50:31.12#ibcon#about to write, iclass 23, count 0 2006.197.07:50:31.12#ibcon#wrote, iclass 23, count 0 2006.197.07:50:31.12#ibcon#about to read 3, iclass 23, count 0 2006.197.07:50:31.14#ibcon#read 3, iclass 23, count 0 2006.197.07:50:31.14#ibcon#about to read 4, iclass 23, count 0 2006.197.07:50:31.14#ibcon#read 4, iclass 23, count 0 2006.197.07:50:31.14#ibcon#about to read 5, iclass 23, count 0 2006.197.07:50:31.14#ibcon#read 5, iclass 23, count 0 2006.197.07:50:31.14#ibcon#about to read 6, iclass 23, count 0 2006.197.07:50:31.14#ibcon#read 6, iclass 23, count 0 2006.197.07:50:31.14#ibcon#end of sib2, iclass 23, count 0 2006.197.07:50:31.14#ibcon#*mode == 0, iclass 23, count 0 2006.197.07:50:31.14#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.197.07:50:31.14#ibcon#[27=USB\r\n] 2006.197.07:50:31.14#ibcon#*before write, iclass 23, count 0 2006.197.07:50:31.14#ibcon#enter sib2, iclass 23, count 0 2006.197.07:50:31.14#ibcon#flushed, iclass 23, count 0 2006.197.07:50:31.14#ibcon#about to write, iclass 23, count 0 2006.197.07:50:31.14#ibcon#wrote, iclass 23, count 0 2006.197.07:50:31.14#ibcon#about to read 3, iclass 23, count 0 2006.197.07:50:31.17#ibcon#read 3, iclass 23, count 0 2006.197.07:50:31.17#ibcon#about to read 4, iclass 23, count 0 2006.197.07:50:31.17#ibcon#read 4, iclass 23, count 0 2006.197.07:50:31.17#ibcon#about to read 5, iclass 23, count 0 2006.197.07:50:31.17#ibcon#read 5, iclass 23, count 0 2006.197.07:50:31.17#ibcon#about to read 6, iclass 23, count 0 2006.197.07:50:31.17#ibcon#read 6, iclass 23, count 0 2006.197.07:50:31.17#ibcon#end of sib2, iclass 23, count 0 2006.197.07:50:31.17#ibcon#*after write, iclass 23, count 0 2006.197.07:50:31.17#ibcon#*before return 0, iclass 23, count 0 2006.197.07:50:31.17#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.197.07:50:31.17#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.197.07:50:31.17#ibcon#about to clear, iclass 23 cls_cnt 0 2006.197.07:50:31.17#ibcon#cleared, iclass 23 cls_cnt 0 2006.197.07:50:31.17$vc4f8/vblo=4,712.99 2006.197.07:50:31.17#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.197.07:50:31.17#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.197.07:50:31.17#ibcon#ireg 17 cls_cnt 0 2006.197.07:50:31.17#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.197.07:50:31.17#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.197.07:50:31.17#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.197.07:50:31.17#ibcon#enter wrdev, iclass 25, count 0 2006.197.07:50:31.17#ibcon#first serial, iclass 25, count 0 2006.197.07:50:31.17#ibcon#enter sib2, iclass 25, count 0 2006.197.07:50:31.17#ibcon#flushed, iclass 25, count 0 2006.197.07:50:31.17#ibcon#about to write, iclass 25, count 0 2006.197.07:50:31.17#ibcon#wrote, iclass 25, count 0 2006.197.07:50:31.17#ibcon#about to read 3, iclass 25, count 0 2006.197.07:50:31.19#ibcon#read 3, iclass 25, count 0 2006.197.07:50:31.19#ibcon#about to read 4, iclass 25, count 0 2006.197.07:50:31.19#ibcon#read 4, iclass 25, count 0 2006.197.07:50:31.19#ibcon#about to read 5, iclass 25, count 0 2006.197.07:50:31.19#ibcon#read 5, iclass 25, count 0 2006.197.07:50:31.19#ibcon#about to read 6, iclass 25, count 0 2006.197.07:50:31.19#ibcon#read 6, iclass 25, count 0 2006.197.07:50:31.19#ibcon#end of sib2, iclass 25, count 0 2006.197.07:50:31.19#ibcon#*mode == 0, iclass 25, count 0 2006.197.07:50:31.19#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.197.07:50:31.19#ibcon#[28=FRQ=04,712.99\r\n] 2006.197.07:50:31.19#ibcon#*before write, iclass 25, count 0 2006.197.07:50:31.19#ibcon#enter sib2, iclass 25, count 0 2006.197.07:50:31.19#ibcon#flushed, iclass 25, count 0 2006.197.07:50:31.19#ibcon#about to write, iclass 25, count 0 2006.197.07:50:31.19#ibcon#wrote, iclass 25, count 0 2006.197.07:50:31.19#ibcon#about to read 3, iclass 25, count 0 2006.197.07:50:31.23#ibcon#read 3, iclass 25, count 0 2006.197.07:50:31.23#ibcon#about to read 4, iclass 25, count 0 2006.197.07:50:31.23#ibcon#read 4, iclass 25, count 0 2006.197.07:50:31.23#ibcon#about to read 5, iclass 25, count 0 2006.197.07:50:31.23#ibcon#read 5, iclass 25, count 0 2006.197.07:50:31.23#ibcon#about to read 6, iclass 25, count 0 2006.197.07:50:31.23#ibcon#read 6, iclass 25, count 0 2006.197.07:50:31.23#ibcon#end of sib2, iclass 25, count 0 2006.197.07:50:31.23#ibcon#*after write, iclass 25, count 0 2006.197.07:50:31.23#ibcon#*before return 0, iclass 25, count 0 2006.197.07:50:31.23#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.197.07:50:31.23#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.197.07:50:31.23#ibcon#about to clear, iclass 25 cls_cnt 0 2006.197.07:50:31.23#ibcon#cleared, iclass 25 cls_cnt 0 2006.197.07:50:31.23$vc4f8/vb=4,4 2006.197.07:50:31.23#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.197.07:50:31.23#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.197.07:50:31.23#ibcon#ireg 11 cls_cnt 2 2006.197.07:50:31.23#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.197.07:50:31.29#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.197.07:50:31.29#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.197.07:50:31.29#ibcon#enter wrdev, iclass 27, count 2 2006.197.07:50:31.29#ibcon#first serial, iclass 27, count 2 2006.197.07:50:31.29#ibcon#enter sib2, iclass 27, count 2 2006.197.07:50:31.29#ibcon#flushed, iclass 27, count 2 2006.197.07:50:31.29#ibcon#about to write, iclass 27, count 2 2006.197.07:50:31.29#ibcon#wrote, iclass 27, count 2 2006.197.07:50:31.29#ibcon#about to read 3, iclass 27, count 2 2006.197.07:50:31.31#ibcon#read 3, iclass 27, count 2 2006.197.07:50:31.31#ibcon#about to read 4, iclass 27, count 2 2006.197.07:50:31.31#ibcon#read 4, iclass 27, count 2 2006.197.07:50:31.31#ibcon#about to read 5, iclass 27, count 2 2006.197.07:50:31.31#ibcon#read 5, iclass 27, count 2 2006.197.07:50:31.31#ibcon#about to read 6, iclass 27, count 2 2006.197.07:50:31.31#ibcon#read 6, iclass 27, count 2 2006.197.07:50:31.31#ibcon#end of sib2, iclass 27, count 2 2006.197.07:50:31.31#ibcon#*mode == 0, iclass 27, count 2 2006.197.07:50:31.31#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.197.07:50:31.31#ibcon#[27=AT04-04\r\n] 2006.197.07:50:31.31#ibcon#*before write, iclass 27, count 2 2006.197.07:50:31.31#ibcon#enter sib2, iclass 27, count 2 2006.197.07:50:31.31#ibcon#flushed, iclass 27, count 2 2006.197.07:50:31.31#ibcon#about to write, iclass 27, count 2 2006.197.07:50:31.31#ibcon#wrote, iclass 27, count 2 2006.197.07:50:31.31#ibcon#about to read 3, iclass 27, count 2 2006.197.07:50:31.34#ibcon#read 3, iclass 27, count 2 2006.197.07:50:31.34#ibcon#about to read 4, iclass 27, count 2 2006.197.07:50:31.34#ibcon#read 4, iclass 27, count 2 2006.197.07:50:31.34#ibcon#about to read 5, iclass 27, count 2 2006.197.07:50:31.34#ibcon#read 5, iclass 27, count 2 2006.197.07:50:31.34#ibcon#about to read 6, iclass 27, count 2 2006.197.07:50:31.34#ibcon#read 6, iclass 27, count 2 2006.197.07:50:31.34#ibcon#end of sib2, iclass 27, count 2 2006.197.07:50:31.34#ibcon#*after write, iclass 27, count 2 2006.197.07:50:31.34#ibcon#*before return 0, iclass 27, count 2 2006.197.07:50:31.34#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.197.07:50:31.34#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.197.07:50:31.34#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.197.07:50:31.34#ibcon#ireg 7 cls_cnt 0 2006.197.07:50:31.34#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.197.07:50:31.46#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.197.07:50:31.46#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.197.07:50:31.46#ibcon#enter wrdev, iclass 27, count 0 2006.197.07:50:31.46#ibcon#first serial, iclass 27, count 0 2006.197.07:50:31.46#ibcon#enter sib2, iclass 27, count 0 2006.197.07:50:31.46#ibcon#flushed, iclass 27, count 0 2006.197.07:50:31.46#ibcon#about to write, iclass 27, count 0 2006.197.07:50:31.46#ibcon#wrote, iclass 27, count 0 2006.197.07:50:31.46#ibcon#about to read 3, iclass 27, count 0 2006.197.07:50:31.48#ibcon#read 3, iclass 27, count 0 2006.197.07:50:31.48#ibcon#about to read 4, iclass 27, count 0 2006.197.07:50:31.48#ibcon#read 4, iclass 27, count 0 2006.197.07:50:31.48#ibcon#about to read 5, iclass 27, count 0 2006.197.07:50:31.48#ibcon#read 5, iclass 27, count 0 2006.197.07:50:31.48#ibcon#about to read 6, iclass 27, count 0 2006.197.07:50:31.48#ibcon#read 6, iclass 27, count 0 2006.197.07:50:31.48#ibcon#end of sib2, iclass 27, count 0 2006.197.07:50:31.48#ibcon#*mode == 0, iclass 27, count 0 2006.197.07:50:31.48#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.197.07:50:31.48#ibcon#[27=USB\r\n] 2006.197.07:50:31.48#ibcon#*before write, iclass 27, count 0 2006.197.07:50:31.48#ibcon#enter sib2, iclass 27, count 0 2006.197.07:50:31.48#ibcon#flushed, iclass 27, count 0 2006.197.07:50:31.48#ibcon#about to write, iclass 27, count 0 2006.197.07:50:31.48#ibcon#wrote, iclass 27, count 0 2006.197.07:50:31.48#ibcon#about to read 3, iclass 27, count 0 2006.197.07:50:31.51#ibcon#read 3, iclass 27, count 0 2006.197.07:50:31.51#ibcon#about to read 4, iclass 27, count 0 2006.197.07:50:31.51#ibcon#read 4, iclass 27, count 0 2006.197.07:50:31.51#ibcon#about to read 5, iclass 27, count 0 2006.197.07:50:31.51#ibcon#read 5, iclass 27, count 0 2006.197.07:50:31.51#ibcon#about to read 6, iclass 27, count 0 2006.197.07:50:31.51#ibcon#read 6, iclass 27, count 0 2006.197.07:50:31.51#ibcon#end of sib2, iclass 27, count 0 2006.197.07:50:31.51#ibcon#*after write, iclass 27, count 0 2006.197.07:50:31.51#ibcon#*before return 0, iclass 27, count 0 2006.197.07:50:31.51#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.197.07:50:31.51#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.197.07:50:31.51#ibcon#about to clear, iclass 27 cls_cnt 0 2006.197.07:50:31.51#ibcon#cleared, iclass 27 cls_cnt 0 2006.197.07:50:31.51$vc4f8/vblo=5,744.99 2006.197.07:50:31.51#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.197.07:50:31.51#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.197.07:50:31.51#ibcon#ireg 17 cls_cnt 0 2006.197.07:50:31.51#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.197.07:50:31.51#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.197.07:50:31.51#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.197.07:50:31.51#ibcon#enter wrdev, iclass 29, count 0 2006.197.07:50:31.51#ibcon#first serial, iclass 29, count 0 2006.197.07:50:31.51#ibcon#enter sib2, iclass 29, count 0 2006.197.07:50:31.51#ibcon#flushed, iclass 29, count 0 2006.197.07:50:31.51#ibcon#about to write, iclass 29, count 0 2006.197.07:50:31.51#ibcon#wrote, iclass 29, count 0 2006.197.07:50:31.51#ibcon#about to read 3, iclass 29, count 0 2006.197.07:50:31.53#ibcon#read 3, iclass 29, count 0 2006.197.07:50:31.53#ibcon#about to read 4, iclass 29, count 0 2006.197.07:50:31.53#ibcon#read 4, iclass 29, count 0 2006.197.07:50:31.53#ibcon#about to read 5, iclass 29, count 0 2006.197.07:50:31.53#ibcon#read 5, iclass 29, count 0 2006.197.07:50:31.53#ibcon#about to read 6, iclass 29, count 0 2006.197.07:50:31.53#ibcon#read 6, iclass 29, count 0 2006.197.07:50:31.53#ibcon#end of sib2, iclass 29, count 0 2006.197.07:50:31.53#ibcon#*mode == 0, iclass 29, count 0 2006.197.07:50:31.53#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.197.07:50:31.53#ibcon#[28=FRQ=05,744.99\r\n] 2006.197.07:50:31.53#ibcon#*before write, iclass 29, count 0 2006.197.07:50:31.53#ibcon#enter sib2, iclass 29, count 0 2006.197.07:50:31.53#ibcon#flushed, iclass 29, count 0 2006.197.07:50:31.53#ibcon#about to write, iclass 29, count 0 2006.197.07:50:31.53#ibcon#wrote, iclass 29, count 0 2006.197.07:50:31.53#ibcon#about to read 3, iclass 29, count 0 2006.197.07:50:31.57#ibcon#read 3, iclass 29, count 0 2006.197.07:50:31.57#ibcon#about to read 4, iclass 29, count 0 2006.197.07:50:31.57#ibcon#read 4, iclass 29, count 0 2006.197.07:50:31.57#ibcon#about to read 5, iclass 29, count 0 2006.197.07:50:31.57#ibcon#read 5, iclass 29, count 0 2006.197.07:50:31.57#ibcon#about to read 6, iclass 29, count 0 2006.197.07:50:31.57#ibcon#read 6, iclass 29, count 0 2006.197.07:50:31.57#ibcon#end of sib2, iclass 29, count 0 2006.197.07:50:31.57#ibcon#*after write, iclass 29, count 0 2006.197.07:50:31.57#ibcon#*before return 0, iclass 29, count 0 2006.197.07:50:31.57#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.197.07:50:31.57#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.197.07:50:31.57#ibcon#about to clear, iclass 29 cls_cnt 0 2006.197.07:50:31.57#ibcon#cleared, iclass 29 cls_cnt 0 2006.197.07:50:31.57$vc4f8/vb=5,4 2006.197.07:50:31.57#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.197.07:50:31.57#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.197.07:50:31.57#ibcon#ireg 11 cls_cnt 2 2006.197.07:50:31.57#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.197.07:50:31.63#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.197.07:50:31.63#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.197.07:50:31.63#ibcon#enter wrdev, iclass 31, count 2 2006.197.07:50:31.63#ibcon#first serial, iclass 31, count 2 2006.197.07:50:31.63#ibcon#enter sib2, iclass 31, count 2 2006.197.07:50:31.63#ibcon#flushed, iclass 31, count 2 2006.197.07:50:31.63#ibcon#about to write, iclass 31, count 2 2006.197.07:50:31.63#ibcon#wrote, iclass 31, count 2 2006.197.07:50:31.63#ibcon#about to read 3, iclass 31, count 2 2006.197.07:50:31.65#ibcon#read 3, iclass 31, count 2 2006.197.07:50:31.65#ibcon#about to read 4, iclass 31, count 2 2006.197.07:50:31.65#ibcon#read 4, iclass 31, count 2 2006.197.07:50:31.65#ibcon#about to read 5, iclass 31, count 2 2006.197.07:50:31.65#ibcon#read 5, iclass 31, count 2 2006.197.07:50:31.65#ibcon#about to read 6, iclass 31, count 2 2006.197.07:50:31.65#ibcon#read 6, iclass 31, count 2 2006.197.07:50:31.65#ibcon#end of sib2, iclass 31, count 2 2006.197.07:50:31.65#ibcon#*mode == 0, iclass 31, count 2 2006.197.07:50:31.65#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.197.07:50:31.65#ibcon#[27=AT05-04\r\n] 2006.197.07:50:31.65#ibcon#*before write, iclass 31, count 2 2006.197.07:50:31.65#ibcon#enter sib2, iclass 31, count 2 2006.197.07:50:31.65#ibcon#flushed, iclass 31, count 2 2006.197.07:50:31.65#ibcon#about to write, iclass 31, count 2 2006.197.07:50:31.65#ibcon#wrote, iclass 31, count 2 2006.197.07:50:31.65#ibcon#about to read 3, iclass 31, count 2 2006.197.07:50:31.68#ibcon#read 3, iclass 31, count 2 2006.197.07:50:31.68#ibcon#about to read 4, iclass 31, count 2 2006.197.07:50:31.68#ibcon#read 4, iclass 31, count 2 2006.197.07:50:31.68#ibcon#about to read 5, iclass 31, count 2 2006.197.07:50:31.68#ibcon#read 5, iclass 31, count 2 2006.197.07:50:31.68#ibcon#about to read 6, iclass 31, count 2 2006.197.07:50:31.68#ibcon#read 6, iclass 31, count 2 2006.197.07:50:31.68#ibcon#end of sib2, iclass 31, count 2 2006.197.07:50:31.68#ibcon#*after write, iclass 31, count 2 2006.197.07:50:31.68#ibcon#*before return 0, iclass 31, count 2 2006.197.07:50:31.68#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.197.07:50:31.68#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.197.07:50:31.68#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.197.07:50:31.68#ibcon#ireg 7 cls_cnt 0 2006.197.07:50:31.68#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.197.07:50:31.80#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.197.07:50:31.80#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.197.07:50:31.80#ibcon#enter wrdev, iclass 31, count 0 2006.197.07:50:31.80#ibcon#first serial, iclass 31, count 0 2006.197.07:50:31.80#ibcon#enter sib2, iclass 31, count 0 2006.197.07:50:31.80#ibcon#flushed, iclass 31, count 0 2006.197.07:50:31.80#ibcon#about to write, iclass 31, count 0 2006.197.07:50:31.80#ibcon#wrote, iclass 31, count 0 2006.197.07:50:31.80#ibcon#about to read 3, iclass 31, count 0 2006.197.07:50:31.82#ibcon#read 3, iclass 31, count 0 2006.197.07:50:31.82#ibcon#about to read 4, iclass 31, count 0 2006.197.07:50:31.82#ibcon#read 4, iclass 31, count 0 2006.197.07:50:31.82#ibcon#about to read 5, iclass 31, count 0 2006.197.07:50:31.82#ibcon#read 5, iclass 31, count 0 2006.197.07:50:31.82#ibcon#about to read 6, iclass 31, count 0 2006.197.07:50:31.82#ibcon#read 6, iclass 31, count 0 2006.197.07:50:31.82#ibcon#end of sib2, iclass 31, count 0 2006.197.07:50:31.82#ibcon#*mode == 0, iclass 31, count 0 2006.197.07:50:31.82#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.197.07:50:31.82#ibcon#[27=USB\r\n] 2006.197.07:50:31.82#ibcon#*before write, iclass 31, count 0 2006.197.07:50:31.82#ibcon#enter sib2, iclass 31, count 0 2006.197.07:50:31.82#ibcon#flushed, iclass 31, count 0 2006.197.07:50:31.82#ibcon#about to write, iclass 31, count 0 2006.197.07:50:31.82#ibcon#wrote, iclass 31, count 0 2006.197.07:50:31.82#ibcon#about to read 3, iclass 31, count 0 2006.197.07:50:31.85#ibcon#read 3, iclass 31, count 0 2006.197.07:50:31.85#ibcon#about to read 4, iclass 31, count 0 2006.197.07:50:31.85#ibcon#read 4, iclass 31, count 0 2006.197.07:50:31.85#ibcon#about to read 5, iclass 31, count 0 2006.197.07:50:31.85#ibcon#read 5, iclass 31, count 0 2006.197.07:50:31.85#ibcon#about to read 6, iclass 31, count 0 2006.197.07:50:31.85#ibcon#read 6, iclass 31, count 0 2006.197.07:50:31.85#ibcon#end of sib2, iclass 31, count 0 2006.197.07:50:31.85#ibcon#*after write, iclass 31, count 0 2006.197.07:50:31.85#ibcon#*before return 0, iclass 31, count 0 2006.197.07:50:31.85#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.197.07:50:31.85#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.197.07:50:31.85#ibcon#about to clear, iclass 31 cls_cnt 0 2006.197.07:50:31.85#ibcon#cleared, iclass 31 cls_cnt 0 2006.197.07:50:31.85$vc4f8/vblo=6,752.99 2006.197.07:50:31.85#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.197.07:50:31.85#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.197.07:50:31.85#ibcon#ireg 17 cls_cnt 0 2006.197.07:50:31.85#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.197.07:50:31.85#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.197.07:50:31.85#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.197.07:50:31.85#ibcon#enter wrdev, iclass 33, count 0 2006.197.07:50:31.85#ibcon#first serial, iclass 33, count 0 2006.197.07:50:31.85#ibcon#enter sib2, iclass 33, count 0 2006.197.07:50:31.85#ibcon#flushed, iclass 33, count 0 2006.197.07:50:31.85#ibcon#about to write, iclass 33, count 0 2006.197.07:50:31.85#ibcon#wrote, iclass 33, count 0 2006.197.07:50:31.85#ibcon#about to read 3, iclass 33, count 0 2006.197.07:50:31.87#ibcon#read 3, iclass 33, count 0 2006.197.07:50:31.87#ibcon#about to read 4, iclass 33, count 0 2006.197.07:50:31.87#ibcon#read 4, iclass 33, count 0 2006.197.07:50:31.87#ibcon#about to read 5, iclass 33, count 0 2006.197.07:50:31.87#ibcon#read 5, iclass 33, count 0 2006.197.07:50:31.87#ibcon#about to read 6, iclass 33, count 0 2006.197.07:50:31.87#ibcon#read 6, iclass 33, count 0 2006.197.07:50:31.87#ibcon#end of sib2, iclass 33, count 0 2006.197.07:50:31.87#ibcon#*mode == 0, iclass 33, count 0 2006.197.07:50:31.87#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.197.07:50:31.87#ibcon#[28=FRQ=06,752.99\r\n] 2006.197.07:50:31.87#ibcon#*before write, iclass 33, count 0 2006.197.07:50:31.87#ibcon#enter sib2, iclass 33, count 0 2006.197.07:50:31.87#ibcon#flushed, iclass 33, count 0 2006.197.07:50:31.87#ibcon#about to write, iclass 33, count 0 2006.197.07:50:31.87#ibcon#wrote, iclass 33, count 0 2006.197.07:50:31.87#ibcon#about to read 3, iclass 33, count 0 2006.197.07:50:31.91#ibcon#read 3, iclass 33, count 0 2006.197.07:50:31.91#ibcon#about to read 4, iclass 33, count 0 2006.197.07:50:31.91#ibcon#read 4, iclass 33, count 0 2006.197.07:50:31.91#ibcon#about to read 5, iclass 33, count 0 2006.197.07:50:31.91#ibcon#read 5, iclass 33, count 0 2006.197.07:50:31.91#ibcon#about to read 6, iclass 33, count 0 2006.197.07:50:31.91#ibcon#read 6, iclass 33, count 0 2006.197.07:50:31.91#ibcon#end of sib2, iclass 33, count 0 2006.197.07:50:31.91#ibcon#*after write, iclass 33, count 0 2006.197.07:50:31.91#ibcon#*before return 0, iclass 33, count 0 2006.197.07:50:31.91#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.197.07:50:31.91#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.197.07:50:31.91#ibcon#about to clear, iclass 33 cls_cnt 0 2006.197.07:50:31.91#ibcon#cleared, iclass 33 cls_cnt 0 2006.197.07:50:31.91$vc4f8/vb=6,4 2006.197.07:50:31.91#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.197.07:50:31.91#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.197.07:50:31.91#ibcon#ireg 11 cls_cnt 2 2006.197.07:50:31.91#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.197.07:50:31.97#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.197.07:50:31.97#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.197.07:50:31.97#ibcon#enter wrdev, iclass 35, count 2 2006.197.07:50:31.97#ibcon#first serial, iclass 35, count 2 2006.197.07:50:31.97#ibcon#enter sib2, iclass 35, count 2 2006.197.07:50:31.97#ibcon#flushed, iclass 35, count 2 2006.197.07:50:31.97#ibcon#about to write, iclass 35, count 2 2006.197.07:50:31.97#ibcon#wrote, iclass 35, count 2 2006.197.07:50:31.97#ibcon#about to read 3, iclass 35, count 2 2006.197.07:50:31.99#ibcon#read 3, iclass 35, count 2 2006.197.07:50:31.99#ibcon#about to read 4, iclass 35, count 2 2006.197.07:50:31.99#ibcon#read 4, iclass 35, count 2 2006.197.07:50:31.99#ibcon#about to read 5, iclass 35, count 2 2006.197.07:50:31.99#ibcon#read 5, iclass 35, count 2 2006.197.07:50:31.99#ibcon#about to read 6, iclass 35, count 2 2006.197.07:50:31.99#ibcon#read 6, iclass 35, count 2 2006.197.07:50:31.99#ibcon#end of sib2, iclass 35, count 2 2006.197.07:50:31.99#ibcon#*mode == 0, iclass 35, count 2 2006.197.07:50:31.99#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.197.07:50:31.99#ibcon#[27=AT06-04\r\n] 2006.197.07:50:31.99#ibcon#*before write, iclass 35, count 2 2006.197.07:50:31.99#ibcon#enter sib2, iclass 35, count 2 2006.197.07:50:31.99#ibcon#flushed, iclass 35, count 2 2006.197.07:50:31.99#ibcon#about to write, iclass 35, count 2 2006.197.07:50:31.99#ibcon#wrote, iclass 35, count 2 2006.197.07:50:31.99#ibcon#about to read 3, iclass 35, count 2 2006.197.07:50:32.02#ibcon#read 3, iclass 35, count 2 2006.197.07:50:32.02#ibcon#about to read 4, iclass 35, count 2 2006.197.07:50:32.02#ibcon#read 4, iclass 35, count 2 2006.197.07:50:32.02#ibcon#about to read 5, iclass 35, count 2 2006.197.07:50:32.02#ibcon#read 5, iclass 35, count 2 2006.197.07:50:32.02#ibcon#about to read 6, iclass 35, count 2 2006.197.07:50:32.02#ibcon#read 6, iclass 35, count 2 2006.197.07:50:32.02#ibcon#end of sib2, iclass 35, count 2 2006.197.07:50:32.02#ibcon#*after write, iclass 35, count 2 2006.197.07:50:32.02#ibcon#*before return 0, iclass 35, count 2 2006.197.07:50:32.02#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.197.07:50:32.02#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.197.07:50:32.02#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.197.07:50:32.02#ibcon#ireg 7 cls_cnt 0 2006.197.07:50:32.02#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.197.07:50:32.14#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.197.07:50:32.14#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.197.07:50:32.14#ibcon#enter wrdev, iclass 35, count 0 2006.197.07:50:32.14#ibcon#first serial, iclass 35, count 0 2006.197.07:50:32.14#ibcon#enter sib2, iclass 35, count 0 2006.197.07:50:32.14#ibcon#flushed, iclass 35, count 0 2006.197.07:50:32.14#ibcon#about to write, iclass 35, count 0 2006.197.07:50:32.14#ibcon#wrote, iclass 35, count 0 2006.197.07:50:32.14#ibcon#about to read 3, iclass 35, count 0 2006.197.07:50:32.16#ibcon#read 3, iclass 35, count 0 2006.197.07:50:32.16#ibcon#about to read 4, iclass 35, count 0 2006.197.07:50:32.16#ibcon#read 4, iclass 35, count 0 2006.197.07:50:32.16#ibcon#about to read 5, iclass 35, count 0 2006.197.07:50:32.16#ibcon#read 5, iclass 35, count 0 2006.197.07:50:32.16#ibcon#about to read 6, iclass 35, count 0 2006.197.07:50:32.16#ibcon#read 6, iclass 35, count 0 2006.197.07:50:32.16#ibcon#end of sib2, iclass 35, count 0 2006.197.07:50:32.16#ibcon#*mode == 0, iclass 35, count 0 2006.197.07:50:32.16#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.197.07:50:32.16#ibcon#[27=USB\r\n] 2006.197.07:50:32.16#ibcon#*before write, iclass 35, count 0 2006.197.07:50:32.16#ibcon#enter sib2, iclass 35, count 0 2006.197.07:50:32.16#ibcon#flushed, iclass 35, count 0 2006.197.07:50:32.16#ibcon#about to write, iclass 35, count 0 2006.197.07:50:32.16#ibcon#wrote, iclass 35, count 0 2006.197.07:50:32.16#ibcon#about to read 3, iclass 35, count 0 2006.197.07:50:32.19#ibcon#read 3, iclass 35, count 0 2006.197.07:50:32.19#ibcon#about to read 4, iclass 35, count 0 2006.197.07:50:32.19#ibcon#read 4, iclass 35, count 0 2006.197.07:50:32.19#ibcon#about to read 5, iclass 35, count 0 2006.197.07:50:32.19#ibcon#read 5, iclass 35, count 0 2006.197.07:50:32.19#ibcon#about to read 6, iclass 35, count 0 2006.197.07:50:32.19#ibcon#read 6, iclass 35, count 0 2006.197.07:50:32.19#ibcon#end of sib2, iclass 35, count 0 2006.197.07:50:32.19#ibcon#*after write, iclass 35, count 0 2006.197.07:50:32.19#ibcon#*before return 0, iclass 35, count 0 2006.197.07:50:32.19#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.197.07:50:32.19#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.197.07:50:32.19#ibcon#about to clear, iclass 35 cls_cnt 0 2006.197.07:50:32.19#ibcon#cleared, iclass 35 cls_cnt 0 2006.197.07:50:32.19$vc4f8/vabw=wide 2006.197.07:50:32.19#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.197.07:50:32.19#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.197.07:50:32.19#ibcon#ireg 8 cls_cnt 0 2006.197.07:50:32.19#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.197.07:50:32.19#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.197.07:50:32.19#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.197.07:50:32.19#ibcon#enter wrdev, iclass 37, count 0 2006.197.07:50:32.19#ibcon#first serial, iclass 37, count 0 2006.197.07:50:32.19#ibcon#enter sib2, iclass 37, count 0 2006.197.07:50:32.19#ibcon#flushed, iclass 37, count 0 2006.197.07:50:32.19#ibcon#about to write, iclass 37, count 0 2006.197.07:50:32.19#ibcon#wrote, iclass 37, count 0 2006.197.07:50:32.19#ibcon#about to read 3, iclass 37, count 0 2006.197.07:50:32.21#ibcon#read 3, iclass 37, count 0 2006.197.07:50:32.21#ibcon#about to read 4, iclass 37, count 0 2006.197.07:50:32.21#ibcon#read 4, iclass 37, count 0 2006.197.07:50:32.21#ibcon#about to read 5, iclass 37, count 0 2006.197.07:50:32.21#ibcon#read 5, iclass 37, count 0 2006.197.07:50:32.21#ibcon#about to read 6, iclass 37, count 0 2006.197.07:50:32.21#ibcon#read 6, iclass 37, count 0 2006.197.07:50:32.21#ibcon#end of sib2, iclass 37, count 0 2006.197.07:50:32.21#ibcon#*mode == 0, iclass 37, count 0 2006.197.07:50:32.21#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.197.07:50:32.21#ibcon#[25=BW32\r\n] 2006.197.07:50:32.21#ibcon#*before write, iclass 37, count 0 2006.197.07:50:32.21#ibcon#enter sib2, iclass 37, count 0 2006.197.07:50:32.21#ibcon#flushed, iclass 37, count 0 2006.197.07:50:32.21#ibcon#about to write, iclass 37, count 0 2006.197.07:50:32.21#ibcon#wrote, iclass 37, count 0 2006.197.07:50:32.21#ibcon#about to read 3, iclass 37, count 0 2006.197.07:50:32.24#ibcon#read 3, iclass 37, count 0 2006.197.07:50:32.24#ibcon#about to read 4, iclass 37, count 0 2006.197.07:50:32.24#ibcon#read 4, iclass 37, count 0 2006.197.07:50:32.24#ibcon#about to read 5, iclass 37, count 0 2006.197.07:50:32.24#ibcon#read 5, iclass 37, count 0 2006.197.07:50:32.24#ibcon#about to read 6, iclass 37, count 0 2006.197.07:50:32.24#ibcon#read 6, iclass 37, count 0 2006.197.07:50:32.24#ibcon#end of sib2, iclass 37, count 0 2006.197.07:50:32.24#ibcon#*after write, iclass 37, count 0 2006.197.07:50:32.24#ibcon#*before return 0, iclass 37, count 0 2006.197.07:50:32.24#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.197.07:50:32.24#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.197.07:50:32.24#ibcon#about to clear, iclass 37 cls_cnt 0 2006.197.07:50:32.24#ibcon#cleared, iclass 37 cls_cnt 0 2006.197.07:50:32.24$vc4f8/vbbw=wide 2006.197.07:50:32.24#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.197.07:50:32.24#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.197.07:50:32.24#ibcon#ireg 8 cls_cnt 0 2006.197.07:50:32.24#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.197.07:50:32.31#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.197.07:50:32.31#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.197.07:50:32.31#ibcon#enter wrdev, iclass 39, count 0 2006.197.07:50:32.31#ibcon#first serial, iclass 39, count 0 2006.197.07:50:32.31#ibcon#enter sib2, iclass 39, count 0 2006.197.07:50:32.31#ibcon#flushed, iclass 39, count 0 2006.197.07:50:32.31#ibcon#about to write, iclass 39, count 0 2006.197.07:50:32.31#ibcon#wrote, iclass 39, count 0 2006.197.07:50:32.31#ibcon#about to read 3, iclass 39, count 0 2006.197.07:50:32.33#ibcon#read 3, iclass 39, count 0 2006.197.07:50:32.33#ibcon#about to read 4, iclass 39, count 0 2006.197.07:50:32.33#ibcon#read 4, iclass 39, count 0 2006.197.07:50:32.33#ibcon#about to read 5, iclass 39, count 0 2006.197.07:50:32.33#ibcon#read 5, iclass 39, count 0 2006.197.07:50:32.33#ibcon#about to read 6, iclass 39, count 0 2006.197.07:50:32.33#ibcon#read 6, iclass 39, count 0 2006.197.07:50:32.33#ibcon#end of sib2, iclass 39, count 0 2006.197.07:50:32.33#ibcon#*mode == 0, iclass 39, count 0 2006.197.07:50:32.33#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.197.07:50:32.33#ibcon#[27=BW32\r\n] 2006.197.07:50:32.33#ibcon#*before write, iclass 39, count 0 2006.197.07:50:32.33#ibcon#enter sib2, iclass 39, count 0 2006.197.07:50:32.33#ibcon#flushed, iclass 39, count 0 2006.197.07:50:32.33#ibcon#about to write, iclass 39, count 0 2006.197.07:50:32.33#ibcon#wrote, iclass 39, count 0 2006.197.07:50:32.33#ibcon#about to read 3, iclass 39, count 0 2006.197.07:50:32.36#ibcon#read 3, iclass 39, count 0 2006.197.07:50:32.36#ibcon#about to read 4, iclass 39, count 0 2006.197.07:50:32.36#ibcon#read 4, iclass 39, count 0 2006.197.07:50:32.36#ibcon#about to read 5, iclass 39, count 0 2006.197.07:50:32.36#ibcon#read 5, iclass 39, count 0 2006.197.07:50:32.36#ibcon#about to read 6, iclass 39, count 0 2006.197.07:50:32.36#ibcon#read 6, iclass 39, count 0 2006.197.07:50:32.36#ibcon#end of sib2, iclass 39, count 0 2006.197.07:50:32.36#ibcon#*after write, iclass 39, count 0 2006.197.07:50:32.36#ibcon#*before return 0, iclass 39, count 0 2006.197.07:50:32.36#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.197.07:50:32.36#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.197.07:50:32.36#ibcon#about to clear, iclass 39 cls_cnt 0 2006.197.07:50:32.36#ibcon#cleared, iclass 39 cls_cnt 0 2006.197.07:50:32.36$4f8m12a/ifd4f 2006.197.07:50:32.36$ifd4f/lo= 2006.197.07:50:32.36$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.197.07:50:32.36$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.197.07:50:32.36$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.197.07:50:32.36$ifd4f/patch= 2006.197.07:50:32.36$ifd4f/patch=lo1,a1,a2,a3,a4 2006.197.07:50:32.36$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.197.07:50:32.36$ifd4f/patch=lo3,a5,a6,a7,a8 2006.197.07:50:32.36$4f8m12a/"form=m,16.000,1:2 2006.197.07:50:32.36$4f8m12a/"tpicd 2006.197.07:50:32.36$4f8m12a/echo=off 2006.197.07:50:32.36$4f8m12a/xlog=off 2006.197.07:50:32.36:!2006.197.07:51:00 2006.197.07:50:42.14#trakl#Source acquired 2006.197.07:50:42.14#flagr#flagr/antenna,acquired 2006.197.07:51:00.00:preob 2006.197.07:51:01.14/onsource/TRACKING 2006.197.07:51:01.14:!2006.197.07:51:10 2006.197.07:51:10.00:data_valid=on 2006.197.07:51:10.00:midob 2006.197.07:51:10.14/onsource/TRACKING 2006.197.07:51:10.14/wx/25.78,1003.2,97 2006.197.07:51:10.34/cable/+6.3720E-03 2006.197.07:51:11.43/va/01,08,usb,yes,28,30 2006.197.07:51:11.43/va/02,07,usb,yes,28,30 2006.197.07:51:11.43/va/03,06,usb,yes,30,30 2006.197.07:51:11.43/va/04,07,usb,yes,29,31 2006.197.07:51:11.43/va/05,07,usb,yes,33,35 2006.197.07:51:11.43/va/06,06,usb,yes,32,32 2006.197.07:51:11.43/va/07,06,usb,yes,32,32 2006.197.07:51:11.43/va/08,07,usb,yes,31,30 2006.197.07:51:11.66/valo/01,532.99,yes,locked 2006.197.07:51:11.66/valo/02,572.99,yes,locked 2006.197.07:51:11.66/valo/03,672.99,yes,locked 2006.197.07:51:11.66/valo/04,832.99,yes,locked 2006.197.07:51:11.66/valo/05,652.99,yes,locked 2006.197.07:51:11.66/valo/06,772.99,yes,locked 2006.197.07:51:11.66/valo/07,832.99,yes,locked 2006.197.07:51:11.66/valo/08,852.99,yes,locked 2006.197.07:51:12.75/vb/01,04,usb,yes,28,27 2006.197.07:51:12.75/vb/02,04,usb,yes,30,31 2006.197.07:51:12.75/vb/03,04,usb,yes,26,30 2006.197.07:51:12.75/vb/04,04,usb,yes,27,27 2006.197.07:51:12.75/vb/05,04,usb,yes,26,30 2006.197.07:51:12.75/vb/06,04,usb,yes,27,29 2006.197.07:51:12.75/vb/07,04,usb,yes,29,28 2006.197.07:51:12.75/vb/08,04,usb,yes,26,30 2006.197.07:51:12.98/vblo/01,632.99,yes,locked 2006.197.07:51:12.98/vblo/02,640.99,yes,locked 2006.197.07:51:12.98/vblo/03,656.99,yes,locked 2006.197.07:51:12.98/vblo/04,712.99,yes,locked 2006.197.07:51:12.98/vblo/05,744.99,yes,locked 2006.197.07:51:12.98/vblo/06,752.99,yes,locked 2006.197.07:51:12.98/vblo/07,734.99,yes,locked 2006.197.07:51:12.98/vblo/08,744.99,yes,locked 2006.197.07:51:13.13/vabw/8 2006.197.07:51:13.28/vbbw/8 2006.197.07:51:13.37/xfe/off,on,15.2 2006.197.07:51:13.77/ifatt/23,28,28,28 2006.197.07:51:14.10/fmout-gps/S +2.98E-07 2006.197.07:51:14.14:!2006.197.07:52:10 2006.197.07:52:10.00:data_valid=off 2006.197.07:52:10.00:postob 2006.197.07:52:10.11/cable/+6.3708E-03 2006.197.07:52:10.11/wx/25.78,1003.1,97 2006.197.07:52:11.11/fmout-gps/S +2.99E-07 2006.197.07:52:11.11:scan_name=197-0753,k06197,60 2006.197.07:52:11.11:source=3c418,203837.03,511912.7,2000.0,cw 2006.197.07:52:11.14#flagr#flagr/antenna,new-source 2006.197.07:52:12.14:checkk5 2006.197.07:52:12.48/chk_autoobs//k5ts1/ autoobs is running! 2006.197.07:52:12.82/chk_autoobs//k5ts2/ autoobs is running! 2006.197.07:52:13.16/chk_autoobs//k5ts3/ autoobs is running! 2006.197.07:52:13.50/chk_autoobs//k5ts4/ autoobs is running! 2006.197.07:52:13.84/chk_obsdata//k5ts1/T1970751??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.07:52:14.17/chk_obsdata//k5ts2/T1970751??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.07:52:14.51/chk_obsdata//k5ts3/T1970751??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.07:52:14.84/chk_obsdata//k5ts4/T1970751??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.07:52:15.52/k5log//k5ts1_log_newline 2006.197.07:52:16.17/k5log//k5ts2_log_newline 2006.197.07:52:16.83/k5log//k5ts3_log_newline 2006.197.07:52:17.49/k5log//k5ts4_log_newline 2006.197.07:52:17.52/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.197.07:52:17.52:4f8m12a=1 2006.197.07:52:17.52$4f8m12a/echo=on 2006.197.07:52:17.52$4f8m12a/pcalon 2006.197.07:52:17.52$pcalon/"no phase cal control is implemented here 2006.197.07:52:17.52$4f8m12a/"tpicd=stop 2006.197.07:52:17.52$4f8m12a/vc4f8 2006.197.07:52:17.52$vc4f8/valo=1,532.99 2006.197.07:52:17.52#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.197.07:52:17.52#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.197.07:52:17.52#ibcon#ireg 17 cls_cnt 0 2006.197.07:52:17.52#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.197.07:52:17.52#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.197.07:52:17.52#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.197.07:52:17.52#ibcon#enter wrdev, iclass 10, count 0 2006.197.07:52:17.52#ibcon#first serial, iclass 10, count 0 2006.197.07:52:17.52#ibcon#enter sib2, iclass 10, count 0 2006.197.07:52:17.52#ibcon#flushed, iclass 10, count 0 2006.197.07:52:17.52#ibcon#about to write, iclass 10, count 0 2006.197.07:52:17.52#ibcon#wrote, iclass 10, count 0 2006.197.07:52:17.52#ibcon#about to read 3, iclass 10, count 0 2006.197.07:52:17.54#ibcon#read 3, iclass 10, count 0 2006.197.07:52:17.54#ibcon#about to read 4, iclass 10, count 0 2006.197.07:52:17.54#ibcon#read 4, iclass 10, count 0 2006.197.07:52:17.54#ibcon#about to read 5, iclass 10, count 0 2006.197.07:52:17.54#ibcon#read 5, iclass 10, count 0 2006.197.07:52:17.54#ibcon#about to read 6, iclass 10, count 0 2006.197.07:52:17.54#ibcon#read 6, iclass 10, count 0 2006.197.07:52:17.54#ibcon#end of sib2, iclass 10, count 0 2006.197.07:52:17.54#ibcon#*mode == 0, iclass 10, count 0 2006.197.07:52:17.54#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.197.07:52:17.54#ibcon#[26=FRQ=01,532.99\r\n] 2006.197.07:52:17.54#ibcon#*before write, iclass 10, count 0 2006.197.07:52:17.54#ibcon#enter sib2, iclass 10, count 0 2006.197.07:52:17.54#ibcon#flushed, iclass 10, count 0 2006.197.07:52:17.54#ibcon#about to write, iclass 10, count 0 2006.197.07:52:17.54#ibcon#wrote, iclass 10, count 0 2006.197.07:52:17.54#ibcon#about to read 3, iclass 10, count 0 2006.197.07:52:17.59#ibcon#read 3, iclass 10, count 0 2006.197.07:52:17.59#ibcon#about to read 4, iclass 10, count 0 2006.197.07:52:17.59#ibcon#read 4, iclass 10, count 0 2006.197.07:52:17.59#ibcon#about to read 5, iclass 10, count 0 2006.197.07:52:17.59#ibcon#read 5, iclass 10, count 0 2006.197.07:52:17.59#ibcon#about to read 6, iclass 10, count 0 2006.197.07:52:17.59#ibcon#read 6, iclass 10, count 0 2006.197.07:52:17.59#ibcon#end of sib2, iclass 10, count 0 2006.197.07:52:17.59#ibcon#*after write, iclass 10, count 0 2006.197.07:52:17.59#ibcon#*before return 0, iclass 10, count 0 2006.197.07:52:17.59#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.197.07:52:17.59#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.197.07:52:17.59#ibcon#about to clear, iclass 10 cls_cnt 0 2006.197.07:52:17.59#ibcon#cleared, iclass 10 cls_cnt 0 2006.197.07:52:17.59$vc4f8/va=1,8 2006.197.07:52:17.59#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.197.07:52:17.59#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.197.07:52:17.59#ibcon#ireg 11 cls_cnt 2 2006.197.07:52:17.59#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.197.07:52:17.59#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.197.07:52:17.59#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.197.07:52:17.59#ibcon#enter wrdev, iclass 12, count 2 2006.197.07:52:17.59#ibcon#first serial, iclass 12, count 2 2006.197.07:52:17.59#ibcon#enter sib2, iclass 12, count 2 2006.197.07:52:17.59#ibcon#flushed, iclass 12, count 2 2006.197.07:52:17.59#ibcon#about to write, iclass 12, count 2 2006.197.07:52:17.59#ibcon#wrote, iclass 12, count 2 2006.197.07:52:17.59#ibcon#about to read 3, iclass 12, count 2 2006.197.07:52:17.61#ibcon#read 3, iclass 12, count 2 2006.197.07:52:17.61#ibcon#about to read 4, iclass 12, count 2 2006.197.07:52:17.61#ibcon#read 4, iclass 12, count 2 2006.197.07:52:17.61#ibcon#about to read 5, iclass 12, count 2 2006.197.07:52:17.61#ibcon#read 5, iclass 12, count 2 2006.197.07:52:17.61#ibcon#about to read 6, iclass 12, count 2 2006.197.07:52:17.61#ibcon#read 6, iclass 12, count 2 2006.197.07:52:17.61#ibcon#end of sib2, iclass 12, count 2 2006.197.07:52:17.61#ibcon#*mode == 0, iclass 12, count 2 2006.197.07:52:17.61#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.197.07:52:17.61#ibcon#[25=AT01-08\r\n] 2006.197.07:52:17.61#ibcon#*before write, iclass 12, count 2 2006.197.07:52:17.61#ibcon#enter sib2, iclass 12, count 2 2006.197.07:52:17.61#ibcon#flushed, iclass 12, count 2 2006.197.07:52:17.61#ibcon#about to write, iclass 12, count 2 2006.197.07:52:17.61#ibcon#wrote, iclass 12, count 2 2006.197.07:52:17.61#ibcon#about to read 3, iclass 12, count 2 2006.197.07:52:17.64#ibcon#read 3, iclass 12, count 2 2006.197.07:52:17.64#ibcon#about to read 4, iclass 12, count 2 2006.197.07:52:17.64#ibcon#read 4, iclass 12, count 2 2006.197.07:52:17.64#ibcon#about to read 5, iclass 12, count 2 2006.197.07:52:17.64#ibcon#read 5, iclass 12, count 2 2006.197.07:52:17.64#ibcon#about to read 6, iclass 12, count 2 2006.197.07:52:17.64#ibcon#read 6, iclass 12, count 2 2006.197.07:52:17.64#ibcon#end of sib2, iclass 12, count 2 2006.197.07:52:17.64#ibcon#*after write, iclass 12, count 2 2006.197.07:52:17.64#ibcon#*before return 0, iclass 12, count 2 2006.197.07:52:17.64#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.197.07:52:17.64#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.197.07:52:17.64#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.197.07:52:17.64#ibcon#ireg 7 cls_cnt 0 2006.197.07:52:17.64#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.197.07:52:17.76#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.197.07:52:17.76#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.197.07:52:17.76#ibcon#enter wrdev, iclass 12, count 0 2006.197.07:52:17.76#ibcon#first serial, iclass 12, count 0 2006.197.07:52:17.76#ibcon#enter sib2, iclass 12, count 0 2006.197.07:52:17.76#ibcon#flushed, iclass 12, count 0 2006.197.07:52:17.76#ibcon#about to write, iclass 12, count 0 2006.197.07:52:17.76#ibcon#wrote, iclass 12, count 0 2006.197.07:52:17.76#ibcon#about to read 3, iclass 12, count 0 2006.197.07:52:17.78#ibcon#read 3, iclass 12, count 0 2006.197.07:52:17.78#ibcon#about to read 4, iclass 12, count 0 2006.197.07:52:17.78#ibcon#read 4, iclass 12, count 0 2006.197.07:52:17.78#ibcon#about to read 5, iclass 12, count 0 2006.197.07:52:17.78#ibcon#read 5, iclass 12, count 0 2006.197.07:52:17.78#ibcon#about to read 6, iclass 12, count 0 2006.197.07:52:17.78#ibcon#read 6, iclass 12, count 0 2006.197.07:52:17.78#ibcon#end of sib2, iclass 12, count 0 2006.197.07:52:17.78#ibcon#*mode == 0, iclass 12, count 0 2006.197.07:52:17.78#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.197.07:52:17.78#ibcon#[25=USB\r\n] 2006.197.07:52:17.78#ibcon#*before write, iclass 12, count 0 2006.197.07:52:17.78#ibcon#enter sib2, iclass 12, count 0 2006.197.07:52:17.78#ibcon#flushed, iclass 12, count 0 2006.197.07:52:17.78#ibcon#about to write, iclass 12, count 0 2006.197.07:52:17.78#ibcon#wrote, iclass 12, count 0 2006.197.07:52:17.78#ibcon#about to read 3, iclass 12, count 0 2006.197.07:52:17.81#ibcon#read 3, iclass 12, count 0 2006.197.07:52:17.81#ibcon#about to read 4, iclass 12, count 0 2006.197.07:52:17.81#ibcon#read 4, iclass 12, count 0 2006.197.07:52:17.81#ibcon#about to read 5, iclass 12, count 0 2006.197.07:52:17.81#ibcon#read 5, iclass 12, count 0 2006.197.07:52:17.81#ibcon#about to read 6, iclass 12, count 0 2006.197.07:52:17.81#ibcon#read 6, iclass 12, count 0 2006.197.07:52:17.81#ibcon#end of sib2, iclass 12, count 0 2006.197.07:52:17.81#ibcon#*after write, iclass 12, count 0 2006.197.07:52:17.81#ibcon#*before return 0, iclass 12, count 0 2006.197.07:52:17.81#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.197.07:52:17.81#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.197.07:52:17.81#ibcon#about to clear, iclass 12 cls_cnt 0 2006.197.07:52:17.81#ibcon#cleared, iclass 12 cls_cnt 0 2006.197.07:52:17.81$vc4f8/valo=2,572.99 2006.197.07:52:17.81#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.197.07:52:17.81#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.197.07:52:17.81#ibcon#ireg 17 cls_cnt 0 2006.197.07:52:17.81#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.197.07:52:17.81#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.197.07:52:17.81#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.197.07:52:17.81#ibcon#enter wrdev, iclass 14, count 0 2006.197.07:52:17.81#ibcon#first serial, iclass 14, count 0 2006.197.07:52:17.81#ibcon#enter sib2, iclass 14, count 0 2006.197.07:52:17.81#ibcon#flushed, iclass 14, count 0 2006.197.07:52:17.81#ibcon#about to write, iclass 14, count 0 2006.197.07:52:17.81#ibcon#wrote, iclass 14, count 0 2006.197.07:52:17.81#ibcon#about to read 3, iclass 14, count 0 2006.197.07:52:17.83#ibcon#read 3, iclass 14, count 0 2006.197.07:52:17.83#ibcon#about to read 4, iclass 14, count 0 2006.197.07:52:17.83#ibcon#read 4, iclass 14, count 0 2006.197.07:52:17.83#ibcon#about to read 5, iclass 14, count 0 2006.197.07:52:17.83#ibcon#read 5, iclass 14, count 0 2006.197.07:52:17.83#ibcon#about to read 6, iclass 14, count 0 2006.197.07:52:17.83#ibcon#read 6, iclass 14, count 0 2006.197.07:52:17.83#ibcon#end of sib2, iclass 14, count 0 2006.197.07:52:17.83#ibcon#*mode == 0, iclass 14, count 0 2006.197.07:52:17.83#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.197.07:52:17.83#ibcon#[26=FRQ=02,572.99\r\n] 2006.197.07:52:17.83#ibcon#*before write, iclass 14, count 0 2006.197.07:52:17.83#ibcon#enter sib2, iclass 14, count 0 2006.197.07:52:17.83#ibcon#flushed, iclass 14, count 0 2006.197.07:52:17.83#ibcon#about to write, iclass 14, count 0 2006.197.07:52:17.83#ibcon#wrote, iclass 14, count 0 2006.197.07:52:17.83#ibcon#about to read 3, iclass 14, count 0 2006.197.07:52:17.87#ibcon#read 3, iclass 14, count 0 2006.197.07:52:17.87#ibcon#about to read 4, iclass 14, count 0 2006.197.07:52:17.87#ibcon#read 4, iclass 14, count 0 2006.197.07:52:17.87#ibcon#about to read 5, iclass 14, count 0 2006.197.07:52:17.87#ibcon#read 5, iclass 14, count 0 2006.197.07:52:17.87#ibcon#about to read 6, iclass 14, count 0 2006.197.07:52:17.87#ibcon#read 6, iclass 14, count 0 2006.197.07:52:17.87#ibcon#end of sib2, iclass 14, count 0 2006.197.07:52:17.87#ibcon#*after write, iclass 14, count 0 2006.197.07:52:17.87#ibcon#*before return 0, iclass 14, count 0 2006.197.07:52:17.87#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.197.07:52:17.87#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.197.07:52:17.87#ibcon#about to clear, iclass 14 cls_cnt 0 2006.197.07:52:17.87#ibcon#cleared, iclass 14 cls_cnt 0 2006.197.07:52:17.87$vc4f8/va=2,7 2006.197.07:52:17.87#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.197.07:52:17.87#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.197.07:52:17.87#ibcon#ireg 11 cls_cnt 2 2006.197.07:52:17.87#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.197.07:52:17.93#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.197.07:52:17.93#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.197.07:52:17.93#ibcon#enter wrdev, iclass 16, count 2 2006.197.07:52:17.93#ibcon#first serial, iclass 16, count 2 2006.197.07:52:17.93#ibcon#enter sib2, iclass 16, count 2 2006.197.07:52:17.93#ibcon#flushed, iclass 16, count 2 2006.197.07:52:17.93#ibcon#about to write, iclass 16, count 2 2006.197.07:52:17.93#ibcon#wrote, iclass 16, count 2 2006.197.07:52:17.93#ibcon#about to read 3, iclass 16, count 2 2006.197.07:52:17.95#ibcon#read 3, iclass 16, count 2 2006.197.07:52:17.95#ibcon#about to read 4, iclass 16, count 2 2006.197.07:52:17.95#ibcon#read 4, iclass 16, count 2 2006.197.07:52:17.95#ibcon#about to read 5, iclass 16, count 2 2006.197.07:52:17.95#ibcon#read 5, iclass 16, count 2 2006.197.07:52:17.95#ibcon#about to read 6, iclass 16, count 2 2006.197.07:52:17.95#ibcon#read 6, iclass 16, count 2 2006.197.07:52:17.95#ibcon#end of sib2, iclass 16, count 2 2006.197.07:52:17.95#ibcon#*mode == 0, iclass 16, count 2 2006.197.07:52:17.95#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.197.07:52:17.95#ibcon#[25=AT02-07\r\n] 2006.197.07:52:17.95#ibcon#*before write, iclass 16, count 2 2006.197.07:52:17.95#ibcon#enter sib2, iclass 16, count 2 2006.197.07:52:17.95#ibcon#flushed, iclass 16, count 2 2006.197.07:52:17.95#ibcon#about to write, iclass 16, count 2 2006.197.07:52:17.95#ibcon#wrote, iclass 16, count 2 2006.197.07:52:17.95#ibcon#about to read 3, iclass 16, count 2 2006.197.07:52:17.98#ibcon#read 3, iclass 16, count 2 2006.197.07:52:17.98#ibcon#about to read 4, iclass 16, count 2 2006.197.07:52:17.98#ibcon#read 4, iclass 16, count 2 2006.197.07:52:17.98#ibcon#about to read 5, iclass 16, count 2 2006.197.07:52:17.98#ibcon#read 5, iclass 16, count 2 2006.197.07:52:17.98#ibcon#about to read 6, iclass 16, count 2 2006.197.07:52:17.98#ibcon#read 6, iclass 16, count 2 2006.197.07:52:17.98#ibcon#end of sib2, iclass 16, count 2 2006.197.07:52:17.98#ibcon#*after write, iclass 16, count 2 2006.197.07:52:17.98#ibcon#*before return 0, iclass 16, count 2 2006.197.07:52:17.98#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.197.07:52:17.98#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.197.07:52:17.98#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.197.07:52:17.98#ibcon#ireg 7 cls_cnt 0 2006.197.07:52:17.98#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.197.07:52:18.10#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.197.07:52:18.10#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.197.07:52:18.10#ibcon#enter wrdev, iclass 16, count 0 2006.197.07:52:18.10#ibcon#first serial, iclass 16, count 0 2006.197.07:52:18.10#ibcon#enter sib2, iclass 16, count 0 2006.197.07:52:18.10#ibcon#flushed, iclass 16, count 0 2006.197.07:52:18.10#ibcon#about to write, iclass 16, count 0 2006.197.07:52:18.10#ibcon#wrote, iclass 16, count 0 2006.197.07:52:18.10#ibcon#about to read 3, iclass 16, count 0 2006.197.07:52:18.12#ibcon#read 3, iclass 16, count 0 2006.197.07:52:18.12#ibcon#about to read 4, iclass 16, count 0 2006.197.07:52:18.12#ibcon#read 4, iclass 16, count 0 2006.197.07:52:18.12#ibcon#about to read 5, iclass 16, count 0 2006.197.07:52:18.12#ibcon#read 5, iclass 16, count 0 2006.197.07:52:18.12#ibcon#about to read 6, iclass 16, count 0 2006.197.07:52:18.12#ibcon#read 6, iclass 16, count 0 2006.197.07:52:18.12#ibcon#end of sib2, iclass 16, count 0 2006.197.07:52:18.12#ibcon#*mode == 0, iclass 16, count 0 2006.197.07:52:18.12#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.197.07:52:18.12#ibcon#[25=USB\r\n] 2006.197.07:52:18.12#ibcon#*before write, iclass 16, count 0 2006.197.07:52:18.12#ibcon#enter sib2, iclass 16, count 0 2006.197.07:52:18.12#ibcon#flushed, iclass 16, count 0 2006.197.07:52:18.12#ibcon#about to write, iclass 16, count 0 2006.197.07:52:18.12#ibcon#wrote, iclass 16, count 0 2006.197.07:52:18.12#ibcon#about to read 3, iclass 16, count 0 2006.197.07:52:18.15#ibcon#read 3, iclass 16, count 0 2006.197.07:52:18.15#ibcon#about to read 4, iclass 16, count 0 2006.197.07:52:18.15#ibcon#read 4, iclass 16, count 0 2006.197.07:52:18.15#ibcon#about to read 5, iclass 16, count 0 2006.197.07:52:18.15#ibcon#read 5, iclass 16, count 0 2006.197.07:52:18.15#ibcon#about to read 6, iclass 16, count 0 2006.197.07:52:18.15#ibcon#read 6, iclass 16, count 0 2006.197.07:52:18.15#ibcon#end of sib2, iclass 16, count 0 2006.197.07:52:18.15#ibcon#*after write, iclass 16, count 0 2006.197.07:52:18.15#ibcon#*before return 0, iclass 16, count 0 2006.197.07:52:18.15#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.197.07:52:18.15#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.197.07:52:18.15#ibcon#about to clear, iclass 16 cls_cnt 0 2006.197.07:52:18.15#ibcon#cleared, iclass 16 cls_cnt 0 2006.197.07:52:18.15$vc4f8/valo=3,672.99 2006.197.07:52:18.15#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.197.07:52:18.15#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.197.07:52:18.15#ibcon#ireg 17 cls_cnt 0 2006.197.07:52:18.15#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.197.07:52:18.15#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.197.07:52:18.15#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.197.07:52:18.15#ibcon#enter wrdev, iclass 18, count 0 2006.197.07:52:18.15#ibcon#first serial, iclass 18, count 0 2006.197.07:52:18.15#ibcon#enter sib2, iclass 18, count 0 2006.197.07:52:18.15#ibcon#flushed, iclass 18, count 0 2006.197.07:52:18.15#ibcon#about to write, iclass 18, count 0 2006.197.07:52:18.15#ibcon#wrote, iclass 18, count 0 2006.197.07:52:18.15#ibcon#about to read 3, iclass 18, count 0 2006.197.07:52:18.17#ibcon#read 3, iclass 18, count 0 2006.197.07:52:18.17#ibcon#about to read 4, iclass 18, count 0 2006.197.07:52:18.17#ibcon#read 4, iclass 18, count 0 2006.197.07:52:18.17#ibcon#about to read 5, iclass 18, count 0 2006.197.07:52:18.17#ibcon#read 5, iclass 18, count 0 2006.197.07:52:18.17#ibcon#about to read 6, iclass 18, count 0 2006.197.07:52:18.17#ibcon#read 6, iclass 18, count 0 2006.197.07:52:18.17#ibcon#end of sib2, iclass 18, count 0 2006.197.07:52:18.17#ibcon#*mode == 0, iclass 18, count 0 2006.197.07:52:18.17#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.197.07:52:18.17#ibcon#[26=FRQ=03,672.99\r\n] 2006.197.07:52:18.17#ibcon#*before write, iclass 18, count 0 2006.197.07:52:18.17#ibcon#enter sib2, iclass 18, count 0 2006.197.07:52:18.17#ibcon#flushed, iclass 18, count 0 2006.197.07:52:18.17#ibcon#about to write, iclass 18, count 0 2006.197.07:52:18.17#ibcon#wrote, iclass 18, count 0 2006.197.07:52:18.17#ibcon#about to read 3, iclass 18, count 0 2006.197.07:52:18.21#ibcon#read 3, iclass 18, count 0 2006.197.07:52:18.21#ibcon#about to read 4, iclass 18, count 0 2006.197.07:52:18.21#ibcon#read 4, iclass 18, count 0 2006.197.07:52:18.21#ibcon#about to read 5, iclass 18, count 0 2006.197.07:52:18.21#ibcon#read 5, iclass 18, count 0 2006.197.07:52:18.21#ibcon#about to read 6, iclass 18, count 0 2006.197.07:52:18.21#ibcon#read 6, iclass 18, count 0 2006.197.07:52:18.21#ibcon#end of sib2, iclass 18, count 0 2006.197.07:52:18.21#ibcon#*after write, iclass 18, count 0 2006.197.07:52:18.21#ibcon#*before return 0, iclass 18, count 0 2006.197.07:52:18.21#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.197.07:52:18.21#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.197.07:52:18.21#ibcon#about to clear, iclass 18 cls_cnt 0 2006.197.07:52:18.21#ibcon#cleared, iclass 18 cls_cnt 0 2006.197.07:52:18.21$vc4f8/va=3,6 2006.197.07:52:18.21#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.197.07:52:18.21#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.197.07:52:18.21#ibcon#ireg 11 cls_cnt 2 2006.197.07:52:18.21#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.197.07:52:18.27#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.197.07:52:18.27#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.197.07:52:18.27#ibcon#enter wrdev, iclass 20, count 2 2006.197.07:52:18.27#ibcon#first serial, iclass 20, count 2 2006.197.07:52:18.27#ibcon#enter sib2, iclass 20, count 2 2006.197.07:52:18.27#ibcon#flushed, iclass 20, count 2 2006.197.07:52:18.27#ibcon#about to write, iclass 20, count 2 2006.197.07:52:18.27#ibcon#wrote, iclass 20, count 2 2006.197.07:52:18.27#ibcon#about to read 3, iclass 20, count 2 2006.197.07:52:18.29#ibcon#read 3, iclass 20, count 2 2006.197.07:52:18.29#ibcon#about to read 4, iclass 20, count 2 2006.197.07:52:18.29#ibcon#read 4, iclass 20, count 2 2006.197.07:52:18.29#ibcon#about to read 5, iclass 20, count 2 2006.197.07:52:18.29#ibcon#read 5, iclass 20, count 2 2006.197.07:52:18.29#ibcon#about to read 6, iclass 20, count 2 2006.197.07:52:18.29#ibcon#read 6, iclass 20, count 2 2006.197.07:52:18.29#ibcon#end of sib2, iclass 20, count 2 2006.197.07:52:18.29#ibcon#*mode == 0, iclass 20, count 2 2006.197.07:52:18.29#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.197.07:52:18.29#ibcon#[25=AT03-06\r\n] 2006.197.07:52:18.29#ibcon#*before write, iclass 20, count 2 2006.197.07:52:18.29#ibcon#enter sib2, iclass 20, count 2 2006.197.07:52:18.29#ibcon#flushed, iclass 20, count 2 2006.197.07:52:18.29#ibcon#about to write, iclass 20, count 2 2006.197.07:52:18.29#ibcon#wrote, iclass 20, count 2 2006.197.07:52:18.29#ibcon#about to read 3, iclass 20, count 2 2006.197.07:52:18.32#ibcon#read 3, iclass 20, count 2 2006.197.07:52:18.32#ibcon#about to read 4, iclass 20, count 2 2006.197.07:52:18.32#ibcon#read 4, iclass 20, count 2 2006.197.07:52:18.32#ibcon#about to read 5, iclass 20, count 2 2006.197.07:52:18.32#ibcon#read 5, iclass 20, count 2 2006.197.07:52:18.32#ibcon#about to read 6, iclass 20, count 2 2006.197.07:52:18.32#ibcon#read 6, iclass 20, count 2 2006.197.07:52:18.32#ibcon#end of sib2, iclass 20, count 2 2006.197.07:52:18.32#ibcon#*after write, iclass 20, count 2 2006.197.07:52:18.32#ibcon#*before return 0, iclass 20, count 2 2006.197.07:52:18.32#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.197.07:52:18.32#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.197.07:52:18.32#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.197.07:52:18.32#ibcon#ireg 7 cls_cnt 0 2006.197.07:52:18.32#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.197.07:52:18.44#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.197.07:52:18.44#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.197.07:52:18.44#ibcon#enter wrdev, iclass 20, count 0 2006.197.07:52:18.44#ibcon#first serial, iclass 20, count 0 2006.197.07:52:18.44#ibcon#enter sib2, iclass 20, count 0 2006.197.07:52:18.44#ibcon#flushed, iclass 20, count 0 2006.197.07:52:18.44#ibcon#about to write, iclass 20, count 0 2006.197.07:52:18.44#ibcon#wrote, iclass 20, count 0 2006.197.07:52:18.44#ibcon#about to read 3, iclass 20, count 0 2006.197.07:52:18.46#ibcon#read 3, iclass 20, count 0 2006.197.07:52:18.46#ibcon#about to read 4, iclass 20, count 0 2006.197.07:52:18.46#ibcon#read 4, iclass 20, count 0 2006.197.07:52:18.46#ibcon#about to read 5, iclass 20, count 0 2006.197.07:52:18.46#ibcon#read 5, iclass 20, count 0 2006.197.07:52:18.46#ibcon#about to read 6, iclass 20, count 0 2006.197.07:52:18.46#ibcon#read 6, iclass 20, count 0 2006.197.07:52:18.46#ibcon#end of sib2, iclass 20, count 0 2006.197.07:52:18.46#ibcon#*mode == 0, iclass 20, count 0 2006.197.07:52:18.46#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.197.07:52:18.46#ibcon#[25=USB\r\n] 2006.197.07:52:18.46#ibcon#*before write, iclass 20, count 0 2006.197.07:52:18.46#ibcon#enter sib2, iclass 20, count 0 2006.197.07:52:18.46#ibcon#flushed, iclass 20, count 0 2006.197.07:52:18.46#ibcon#about to write, iclass 20, count 0 2006.197.07:52:18.46#ibcon#wrote, iclass 20, count 0 2006.197.07:52:18.46#ibcon#about to read 3, iclass 20, count 0 2006.197.07:52:18.49#ibcon#read 3, iclass 20, count 0 2006.197.07:52:18.49#ibcon#about to read 4, iclass 20, count 0 2006.197.07:52:18.49#ibcon#read 4, iclass 20, count 0 2006.197.07:52:18.49#ibcon#about to read 5, iclass 20, count 0 2006.197.07:52:18.49#ibcon#read 5, iclass 20, count 0 2006.197.07:52:18.49#ibcon#about to read 6, iclass 20, count 0 2006.197.07:52:18.49#ibcon#read 6, iclass 20, count 0 2006.197.07:52:18.49#ibcon#end of sib2, iclass 20, count 0 2006.197.07:52:18.49#ibcon#*after write, iclass 20, count 0 2006.197.07:52:18.49#ibcon#*before return 0, iclass 20, count 0 2006.197.07:52:18.49#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.197.07:52:18.49#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.197.07:52:18.49#ibcon#about to clear, iclass 20 cls_cnt 0 2006.197.07:52:18.49#ibcon#cleared, iclass 20 cls_cnt 0 2006.197.07:52:18.49$vc4f8/valo=4,832.99 2006.197.07:52:18.49#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.197.07:52:18.49#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.197.07:52:18.49#ibcon#ireg 17 cls_cnt 0 2006.197.07:52:18.49#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.197.07:52:18.49#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.197.07:52:18.49#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.197.07:52:18.49#ibcon#enter wrdev, iclass 22, count 0 2006.197.07:52:18.49#ibcon#first serial, iclass 22, count 0 2006.197.07:52:18.49#ibcon#enter sib2, iclass 22, count 0 2006.197.07:52:18.49#ibcon#flushed, iclass 22, count 0 2006.197.07:52:18.49#ibcon#about to write, iclass 22, count 0 2006.197.07:52:18.49#ibcon#wrote, iclass 22, count 0 2006.197.07:52:18.49#ibcon#about to read 3, iclass 22, count 0 2006.197.07:52:18.51#ibcon#read 3, iclass 22, count 0 2006.197.07:52:18.51#ibcon#about to read 4, iclass 22, count 0 2006.197.07:52:18.51#ibcon#read 4, iclass 22, count 0 2006.197.07:52:18.51#ibcon#about to read 5, iclass 22, count 0 2006.197.07:52:18.51#ibcon#read 5, iclass 22, count 0 2006.197.07:52:18.51#ibcon#about to read 6, iclass 22, count 0 2006.197.07:52:18.51#ibcon#read 6, iclass 22, count 0 2006.197.07:52:18.51#ibcon#end of sib2, iclass 22, count 0 2006.197.07:52:18.51#ibcon#*mode == 0, iclass 22, count 0 2006.197.07:52:18.51#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.197.07:52:18.51#ibcon#[26=FRQ=04,832.99\r\n] 2006.197.07:52:18.51#ibcon#*before write, iclass 22, count 0 2006.197.07:52:18.51#ibcon#enter sib2, iclass 22, count 0 2006.197.07:52:18.51#ibcon#flushed, iclass 22, count 0 2006.197.07:52:18.51#ibcon#about to write, iclass 22, count 0 2006.197.07:52:18.51#ibcon#wrote, iclass 22, count 0 2006.197.07:52:18.51#ibcon#about to read 3, iclass 22, count 0 2006.197.07:52:18.55#ibcon#read 3, iclass 22, count 0 2006.197.07:52:18.55#ibcon#about to read 4, iclass 22, count 0 2006.197.07:52:18.55#ibcon#read 4, iclass 22, count 0 2006.197.07:52:18.55#ibcon#about to read 5, iclass 22, count 0 2006.197.07:52:18.55#ibcon#read 5, iclass 22, count 0 2006.197.07:52:18.55#ibcon#about to read 6, iclass 22, count 0 2006.197.07:52:18.55#ibcon#read 6, iclass 22, count 0 2006.197.07:52:18.55#ibcon#end of sib2, iclass 22, count 0 2006.197.07:52:18.55#ibcon#*after write, iclass 22, count 0 2006.197.07:52:18.55#ibcon#*before return 0, iclass 22, count 0 2006.197.07:52:18.55#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.197.07:52:18.55#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.197.07:52:18.55#ibcon#about to clear, iclass 22 cls_cnt 0 2006.197.07:52:18.55#ibcon#cleared, iclass 22 cls_cnt 0 2006.197.07:52:18.55$vc4f8/va=4,7 2006.197.07:52:18.55#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.197.07:52:18.55#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.197.07:52:18.55#ibcon#ireg 11 cls_cnt 2 2006.197.07:52:18.55#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.197.07:52:18.61#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.197.07:52:18.61#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.197.07:52:18.61#ibcon#enter wrdev, iclass 24, count 2 2006.197.07:52:18.61#ibcon#first serial, iclass 24, count 2 2006.197.07:52:18.61#ibcon#enter sib2, iclass 24, count 2 2006.197.07:52:18.61#ibcon#flushed, iclass 24, count 2 2006.197.07:52:18.61#ibcon#about to write, iclass 24, count 2 2006.197.07:52:18.61#ibcon#wrote, iclass 24, count 2 2006.197.07:52:18.61#ibcon#about to read 3, iclass 24, count 2 2006.197.07:52:18.63#ibcon#read 3, iclass 24, count 2 2006.197.07:52:18.63#ibcon#about to read 4, iclass 24, count 2 2006.197.07:52:18.63#ibcon#read 4, iclass 24, count 2 2006.197.07:52:18.63#ibcon#about to read 5, iclass 24, count 2 2006.197.07:52:18.63#ibcon#read 5, iclass 24, count 2 2006.197.07:52:18.63#ibcon#about to read 6, iclass 24, count 2 2006.197.07:52:18.63#ibcon#read 6, iclass 24, count 2 2006.197.07:52:18.63#ibcon#end of sib2, iclass 24, count 2 2006.197.07:52:18.63#ibcon#*mode == 0, iclass 24, count 2 2006.197.07:52:18.63#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.197.07:52:18.63#ibcon#[25=AT04-07\r\n] 2006.197.07:52:18.63#ibcon#*before write, iclass 24, count 2 2006.197.07:52:18.63#ibcon#enter sib2, iclass 24, count 2 2006.197.07:52:18.63#ibcon#flushed, iclass 24, count 2 2006.197.07:52:18.63#ibcon#about to write, iclass 24, count 2 2006.197.07:52:18.63#ibcon#wrote, iclass 24, count 2 2006.197.07:52:18.63#ibcon#about to read 3, iclass 24, count 2 2006.197.07:52:18.66#ibcon#read 3, iclass 24, count 2 2006.197.07:52:18.66#ibcon#about to read 4, iclass 24, count 2 2006.197.07:52:18.66#ibcon#read 4, iclass 24, count 2 2006.197.07:52:18.66#ibcon#about to read 5, iclass 24, count 2 2006.197.07:52:18.66#ibcon#read 5, iclass 24, count 2 2006.197.07:52:18.66#ibcon#about to read 6, iclass 24, count 2 2006.197.07:52:18.66#ibcon#read 6, iclass 24, count 2 2006.197.07:52:18.66#ibcon#end of sib2, iclass 24, count 2 2006.197.07:52:18.66#ibcon#*after write, iclass 24, count 2 2006.197.07:52:18.66#ibcon#*before return 0, iclass 24, count 2 2006.197.07:52:18.66#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.197.07:52:18.66#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.197.07:52:18.66#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.197.07:52:18.66#ibcon#ireg 7 cls_cnt 0 2006.197.07:52:18.66#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.197.07:52:18.78#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.197.07:52:18.78#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.197.07:52:18.78#ibcon#enter wrdev, iclass 24, count 0 2006.197.07:52:18.78#ibcon#first serial, iclass 24, count 0 2006.197.07:52:18.78#ibcon#enter sib2, iclass 24, count 0 2006.197.07:52:18.78#ibcon#flushed, iclass 24, count 0 2006.197.07:52:18.78#ibcon#about to write, iclass 24, count 0 2006.197.07:52:18.78#ibcon#wrote, iclass 24, count 0 2006.197.07:52:18.78#ibcon#about to read 3, iclass 24, count 0 2006.197.07:52:18.80#ibcon#read 3, iclass 24, count 0 2006.197.07:52:18.80#ibcon#about to read 4, iclass 24, count 0 2006.197.07:52:18.80#ibcon#read 4, iclass 24, count 0 2006.197.07:52:18.80#ibcon#about to read 5, iclass 24, count 0 2006.197.07:52:18.80#ibcon#read 5, iclass 24, count 0 2006.197.07:52:18.80#ibcon#about to read 6, iclass 24, count 0 2006.197.07:52:18.80#ibcon#read 6, iclass 24, count 0 2006.197.07:52:18.80#ibcon#end of sib2, iclass 24, count 0 2006.197.07:52:18.80#ibcon#*mode == 0, iclass 24, count 0 2006.197.07:52:18.80#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.197.07:52:18.80#ibcon#[25=USB\r\n] 2006.197.07:52:18.80#ibcon#*before write, iclass 24, count 0 2006.197.07:52:18.80#ibcon#enter sib2, iclass 24, count 0 2006.197.07:52:18.80#ibcon#flushed, iclass 24, count 0 2006.197.07:52:18.80#ibcon#about to write, iclass 24, count 0 2006.197.07:52:18.80#ibcon#wrote, iclass 24, count 0 2006.197.07:52:18.80#ibcon#about to read 3, iclass 24, count 0 2006.197.07:52:18.83#ibcon#read 3, iclass 24, count 0 2006.197.07:52:18.83#ibcon#about to read 4, iclass 24, count 0 2006.197.07:52:18.83#ibcon#read 4, iclass 24, count 0 2006.197.07:52:18.83#ibcon#about to read 5, iclass 24, count 0 2006.197.07:52:18.83#ibcon#read 5, iclass 24, count 0 2006.197.07:52:18.83#ibcon#about to read 6, iclass 24, count 0 2006.197.07:52:18.83#ibcon#read 6, iclass 24, count 0 2006.197.07:52:18.83#ibcon#end of sib2, iclass 24, count 0 2006.197.07:52:18.83#ibcon#*after write, iclass 24, count 0 2006.197.07:52:18.83#ibcon#*before return 0, iclass 24, count 0 2006.197.07:52:18.83#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.197.07:52:18.83#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.197.07:52:18.83#ibcon#about to clear, iclass 24 cls_cnt 0 2006.197.07:52:18.83#ibcon#cleared, iclass 24 cls_cnt 0 2006.197.07:52:18.83$vc4f8/valo=5,652.99 2006.197.07:52:18.83#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.197.07:52:18.83#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.197.07:52:18.83#ibcon#ireg 17 cls_cnt 0 2006.197.07:52:18.83#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.197.07:52:18.83#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.197.07:52:18.83#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.197.07:52:18.83#ibcon#enter wrdev, iclass 26, count 0 2006.197.07:52:18.83#ibcon#first serial, iclass 26, count 0 2006.197.07:52:18.83#ibcon#enter sib2, iclass 26, count 0 2006.197.07:52:18.83#ibcon#flushed, iclass 26, count 0 2006.197.07:52:18.83#ibcon#about to write, iclass 26, count 0 2006.197.07:52:18.83#ibcon#wrote, iclass 26, count 0 2006.197.07:52:18.83#ibcon#about to read 3, iclass 26, count 0 2006.197.07:52:18.85#ibcon#read 3, iclass 26, count 0 2006.197.07:52:18.85#ibcon#about to read 4, iclass 26, count 0 2006.197.07:52:18.85#ibcon#read 4, iclass 26, count 0 2006.197.07:52:18.85#ibcon#about to read 5, iclass 26, count 0 2006.197.07:52:18.85#ibcon#read 5, iclass 26, count 0 2006.197.07:52:18.85#ibcon#about to read 6, iclass 26, count 0 2006.197.07:52:18.85#ibcon#read 6, iclass 26, count 0 2006.197.07:52:18.85#ibcon#end of sib2, iclass 26, count 0 2006.197.07:52:18.85#ibcon#*mode == 0, iclass 26, count 0 2006.197.07:52:18.85#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.197.07:52:18.85#ibcon#[26=FRQ=05,652.99\r\n] 2006.197.07:52:18.85#ibcon#*before write, iclass 26, count 0 2006.197.07:52:18.85#ibcon#enter sib2, iclass 26, count 0 2006.197.07:52:18.85#ibcon#flushed, iclass 26, count 0 2006.197.07:52:18.85#ibcon#about to write, iclass 26, count 0 2006.197.07:52:18.85#ibcon#wrote, iclass 26, count 0 2006.197.07:52:18.85#ibcon#about to read 3, iclass 26, count 0 2006.197.07:52:18.89#ibcon#read 3, iclass 26, count 0 2006.197.07:52:18.89#ibcon#about to read 4, iclass 26, count 0 2006.197.07:52:18.89#ibcon#read 4, iclass 26, count 0 2006.197.07:52:18.89#ibcon#about to read 5, iclass 26, count 0 2006.197.07:52:18.89#ibcon#read 5, iclass 26, count 0 2006.197.07:52:18.89#ibcon#about to read 6, iclass 26, count 0 2006.197.07:52:18.89#ibcon#read 6, iclass 26, count 0 2006.197.07:52:18.89#ibcon#end of sib2, iclass 26, count 0 2006.197.07:52:18.89#ibcon#*after write, iclass 26, count 0 2006.197.07:52:18.89#ibcon#*before return 0, iclass 26, count 0 2006.197.07:52:18.89#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.197.07:52:18.89#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.197.07:52:18.89#ibcon#about to clear, iclass 26 cls_cnt 0 2006.197.07:52:18.89#ibcon#cleared, iclass 26 cls_cnt 0 2006.197.07:52:18.89$vc4f8/va=5,7 2006.197.07:52:18.89#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.197.07:52:18.89#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.197.07:52:18.89#ibcon#ireg 11 cls_cnt 2 2006.197.07:52:18.89#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.197.07:52:18.95#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.197.07:52:18.95#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.197.07:52:18.95#ibcon#enter wrdev, iclass 28, count 2 2006.197.07:52:18.95#ibcon#first serial, iclass 28, count 2 2006.197.07:52:18.95#ibcon#enter sib2, iclass 28, count 2 2006.197.07:52:18.95#ibcon#flushed, iclass 28, count 2 2006.197.07:52:18.95#ibcon#about to write, iclass 28, count 2 2006.197.07:52:18.95#ibcon#wrote, iclass 28, count 2 2006.197.07:52:18.95#ibcon#about to read 3, iclass 28, count 2 2006.197.07:52:18.97#ibcon#read 3, iclass 28, count 2 2006.197.07:52:18.97#ibcon#about to read 4, iclass 28, count 2 2006.197.07:52:18.97#ibcon#read 4, iclass 28, count 2 2006.197.07:52:18.97#ibcon#about to read 5, iclass 28, count 2 2006.197.07:52:18.97#ibcon#read 5, iclass 28, count 2 2006.197.07:52:18.97#ibcon#about to read 6, iclass 28, count 2 2006.197.07:52:18.97#ibcon#read 6, iclass 28, count 2 2006.197.07:52:18.97#ibcon#end of sib2, iclass 28, count 2 2006.197.07:52:18.97#ibcon#*mode == 0, iclass 28, count 2 2006.197.07:52:18.97#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.197.07:52:18.97#ibcon#[25=AT05-07\r\n] 2006.197.07:52:18.97#ibcon#*before write, iclass 28, count 2 2006.197.07:52:18.97#ibcon#enter sib2, iclass 28, count 2 2006.197.07:52:18.97#ibcon#flushed, iclass 28, count 2 2006.197.07:52:18.97#ibcon#about to write, iclass 28, count 2 2006.197.07:52:18.97#ibcon#wrote, iclass 28, count 2 2006.197.07:52:18.97#ibcon#about to read 3, iclass 28, count 2 2006.197.07:52:19.00#ibcon#read 3, iclass 28, count 2 2006.197.07:52:19.00#ibcon#about to read 4, iclass 28, count 2 2006.197.07:52:19.00#ibcon#read 4, iclass 28, count 2 2006.197.07:52:19.00#ibcon#about to read 5, iclass 28, count 2 2006.197.07:52:19.00#ibcon#read 5, iclass 28, count 2 2006.197.07:52:19.00#ibcon#about to read 6, iclass 28, count 2 2006.197.07:52:19.00#ibcon#read 6, iclass 28, count 2 2006.197.07:52:19.00#ibcon#end of sib2, iclass 28, count 2 2006.197.07:52:19.00#ibcon#*after write, iclass 28, count 2 2006.197.07:52:19.00#ibcon#*before return 0, iclass 28, count 2 2006.197.07:52:19.00#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.197.07:52:19.00#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.197.07:52:19.00#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.197.07:52:19.00#ibcon#ireg 7 cls_cnt 0 2006.197.07:52:19.00#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.197.07:52:19.12#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.197.07:52:19.12#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.197.07:52:19.12#ibcon#enter wrdev, iclass 28, count 0 2006.197.07:52:19.12#ibcon#first serial, iclass 28, count 0 2006.197.07:52:19.12#ibcon#enter sib2, iclass 28, count 0 2006.197.07:52:19.12#ibcon#flushed, iclass 28, count 0 2006.197.07:52:19.12#ibcon#about to write, iclass 28, count 0 2006.197.07:52:19.12#ibcon#wrote, iclass 28, count 0 2006.197.07:52:19.12#ibcon#about to read 3, iclass 28, count 0 2006.197.07:52:19.14#ibcon#read 3, iclass 28, count 0 2006.197.07:52:19.14#ibcon#about to read 4, iclass 28, count 0 2006.197.07:52:19.14#ibcon#read 4, iclass 28, count 0 2006.197.07:52:19.14#ibcon#about to read 5, iclass 28, count 0 2006.197.07:52:19.14#ibcon#read 5, iclass 28, count 0 2006.197.07:52:19.14#ibcon#about to read 6, iclass 28, count 0 2006.197.07:52:19.14#ibcon#read 6, iclass 28, count 0 2006.197.07:52:19.14#ibcon#end of sib2, iclass 28, count 0 2006.197.07:52:19.14#ibcon#*mode == 0, iclass 28, count 0 2006.197.07:52:19.14#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.197.07:52:19.14#ibcon#[25=USB\r\n] 2006.197.07:52:19.14#ibcon#*before write, iclass 28, count 0 2006.197.07:52:19.14#ibcon#enter sib2, iclass 28, count 0 2006.197.07:52:19.14#ibcon#flushed, iclass 28, count 0 2006.197.07:52:19.14#ibcon#about to write, iclass 28, count 0 2006.197.07:52:19.14#ibcon#wrote, iclass 28, count 0 2006.197.07:52:19.14#ibcon#about to read 3, iclass 28, count 0 2006.197.07:52:19.17#ibcon#read 3, iclass 28, count 0 2006.197.07:52:19.17#ibcon#about to read 4, iclass 28, count 0 2006.197.07:52:19.17#ibcon#read 4, iclass 28, count 0 2006.197.07:52:19.17#ibcon#about to read 5, iclass 28, count 0 2006.197.07:52:19.17#ibcon#read 5, iclass 28, count 0 2006.197.07:52:19.17#ibcon#about to read 6, iclass 28, count 0 2006.197.07:52:19.17#ibcon#read 6, iclass 28, count 0 2006.197.07:52:19.17#ibcon#end of sib2, iclass 28, count 0 2006.197.07:52:19.17#ibcon#*after write, iclass 28, count 0 2006.197.07:52:19.17#ibcon#*before return 0, iclass 28, count 0 2006.197.07:52:19.17#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.197.07:52:19.17#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.197.07:52:19.17#ibcon#about to clear, iclass 28 cls_cnt 0 2006.197.07:52:19.17#ibcon#cleared, iclass 28 cls_cnt 0 2006.197.07:52:19.17$vc4f8/valo=6,772.99 2006.197.07:52:19.17#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.197.07:52:19.17#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.197.07:52:19.17#ibcon#ireg 17 cls_cnt 0 2006.197.07:52:19.17#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.197.07:52:19.17#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.197.07:52:19.17#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.197.07:52:19.17#ibcon#enter wrdev, iclass 30, count 0 2006.197.07:52:19.17#ibcon#first serial, iclass 30, count 0 2006.197.07:52:19.17#ibcon#enter sib2, iclass 30, count 0 2006.197.07:52:19.17#ibcon#flushed, iclass 30, count 0 2006.197.07:52:19.17#ibcon#about to write, iclass 30, count 0 2006.197.07:52:19.17#ibcon#wrote, iclass 30, count 0 2006.197.07:52:19.17#ibcon#about to read 3, iclass 30, count 0 2006.197.07:52:19.19#ibcon#read 3, iclass 30, count 0 2006.197.07:52:19.19#ibcon#about to read 4, iclass 30, count 0 2006.197.07:52:19.19#ibcon#read 4, iclass 30, count 0 2006.197.07:52:19.19#ibcon#about to read 5, iclass 30, count 0 2006.197.07:52:19.19#ibcon#read 5, iclass 30, count 0 2006.197.07:52:19.19#ibcon#about to read 6, iclass 30, count 0 2006.197.07:52:19.19#ibcon#read 6, iclass 30, count 0 2006.197.07:52:19.19#ibcon#end of sib2, iclass 30, count 0 2006.197.07:52:19.19#ibcon#*mode == 0, iclass 30, count 0 2006.197.07:52:19.19#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.197.07:52:19.19#ibcon#[26=FRQ=06,772.99\r\n] 2006.197.07:52:19.19#ibcon#*before write, iclass 30, count 0 2006.197.07:52:19.19#ibcon#enter sib2, iclass 30, count 0 2006.197.07:52:19.19#ibcon#flushed, iclass 30, count 0 2006.197.07:52:19.19#ibcon#about to write, iclass 30, count 0 2006.197.07:52:19.19#ibcon#wrote, iclass 30, count 0 2006.197.07:52:19.19#ibcon#about to read 3, iclass 30, count 0 2006.197.07:52:19.23#ibcon#read 3, iclass 30, count 0 2006.197.07:52:19.23#ibcon#about to read 4, iclass 30, count 0 2006.197.07:52:19.23#ibcon#read 4, iclass 30, count 0 2006.197.07:52:19.23#ibcon#about to read 5, iclass 30, count 0 2006.197.07:52:19.23#ibcon#read 5, iclass 30, count 0 2006.197.07:52:19.23#ibcon#about to read 6, iclass 30, count 0 2006.197.07:52:19.23#ibcon#read 6, iclass 30, count 0 2006.197.07:52:19.23#ibcon#end of sib2, iclass 30, count 0 2006.197.07:52:19.23#ibcon#*after write, iclass 30, count 0 2006.197.07:52:19.23#ibcon#*before return 0, iclass 30, count 0 2006.197.07:52:19.23#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.197.07:52:19.23#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.197.07:52:19.23#ibcon#about to clear, iclass 30 cls_cnt 0 2006.197.07:52:19.23#ibcon#cleared, iclass 30 cls_cnt 0 2006.197.07:52:19.23$vc4f8/va=6,6 2006.197.07:52:19.23#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.197.07:52:19.23#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.197.07:52:19.23#ibcon#ireg 11 cls_cnt 2 2006.197.07:52:19.23#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.197.07:52:19.29#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.197.07:52:19.29#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.197.07:52:19.29#ibcon#enter wrdev, iclass 32, count 2 2006.197.07:52:19.29#ibcon#first serial, iclass 32, count 2 2006.197.07:52:19.29#ibcon#enter sib2, iclass 32, count 2 2006.197.07:52:19.29#ibcon#flushed, iclass 32, count 2 2006.197.07:52:19.29#ibcon#about to write, iclass 32, count 2 2006.197.07:52:19.29#ibcon#wrote, iclass 32, count 2 2006.197.07:52:19.29#ibcon#about to read 3, iclass 32, count 2 2006.197.07:52:19.31#ibcon#read 3, iclass 32, count 2 2006.197.07:52:19.31#ibcon#about to read 4, iclass 32, count 2 2006.197.07:52:19.31#ibcon#read 4, iclass 32, count 2 2006.197.07:52:19.31#ibcon#about to read 5, iclass 32, count 2 2006.197.07:52:19.31#ibcon#read 5, iclass 32, count 2 2006.197.07:52:19.31#ibcon#about to read 6, iclass 32, count 2 2006.197.07:52:19.31#ibcon#read 6, iclass 32, count 2 2006.197.07:52:19.31#ibcon#end of sib2, iclass 32, count 2 2006.197.07:52:19.31#ibcon#*mode == 0, iclass 32, count 2 2006.197.07:52:19.31#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.197.07:52:19.31#ibcon#[25=AT06-06\r\n] 2006.197.07:52:19.31#ibcon#*before write, iclass 32, count 2 2006.197.07:52:19.31#ibcon#enter sib2, iclass 32, count 2 2006.197.07:52:19.31#ibcon#flushed, iclass 32, count 2 2006.197.07:52:19.31#ibcon#about to write, iclass 32, count 2 2006.197.07:52:19.31#ibcon#wrote, iclass 32, count 2 2006.197.07:52:19.31#ibcon#about to read 3, iclass 32, count 2 2006.197.07:52:19.34#ibcon#read 3, iclass 32, count 2 2006.197.07:52:19.34#ibcon#about to read 4, iclass 32, count 2 2006.197.07:52:19.34#ibcon#read 4, iclass 32, count 2 2006.197.07:52:19.34#ibcon#about to read 5, iclass 32, count 2 2006.197.07:52:19.34#ibcon#read 5, iclass 32, count 2 2006.197.07:52:19.34#ibcon#about to read 6, iclass 32, count 2 2006.197.07:52:19.34#ibcon#read 6, iclass 32, count 2 2006.197.07:52:19.34#ibcon#end of sib2, iclass 32, count 2 2006.197.07:52:19.34#ibcon#*after write, iclass 32, count 2 2006.197.07:52:19.34#ibcon#*before return 0, iclass 32, count 2 2006.197.07:52:19.34#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.197.07:52:19.34#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.197.07:52:19.34#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.197.07:52:19.34#ibcon#ireg 7 cls_cnt 0 2006.197.07:52:19.34#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.197.07:52:19.46#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.197.07:52:19.46#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.197.07:52:19.46#ibcon#enter wrdev, iclass 32, count 0 2006.197.07:52:19.46#ibcon#first serial, iclass 32, count 0 2006.197.07:52:19.46#ibcon#enter sib2, iclass 32, count 0 2006.197.07:52:19.46#ibcon#flushed, iclass 32, count 0 2006.197.07:52:19.46#ibcon#about to write, iclass 32, count 0 2006.197.07:52:19.46#ibcon#wrote, iclass 32, count 0 2006.197.07:52:19.46#ibcon#about to read 3, iclass 32, count 0 2006.197.07:52:19.48#ibcon#read 3, iclass 32, count 0 2006.197.07:52:19.48#ibcon#about to read 4, iclass 32, count 0 2006.197.07:52:19.48#ibcon#read 4, iclass 32, count 0 2006.197.07:52:19.48#ibcon#about to read 5, iclass 32, count 0 2006.197.07:52:19.48#ibcon#read 5, iclass 32, count 0 2006.197.07:52:19.48#ibcon#about to read 6, iclass 32, count 0 2006.197.07:52:19.48#ibcon#read 6, iclass 32, count 0 2006.197.07:52:19.48#ibcon#end of sib2, iclass 32, count 0 2006.197.07:52:19.48#ibcon#*mode == 0, iclass 32, count 0 2006.197.07:52:19.48#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.197.07:52:19.48#ibcon#[25=USB\r\n] 2006.197.07:52:19.48#ibcon#*before write, iclass 32, count 0 2006.197.07:52:19.48#ibcon#enter sib2, iclass 32, count 0 2006.197.07:52:19.48#ibcon#flushed, iclass 32, count 0 2006.197.07:52:19.48#ibcon#about to write, iclass 32, count 0 2006.197.07:52:19.48#ibcon#wrote, iclass 32, count 0 2006.197.07:52:19.48#ibcon#about to read 3, iclass 32, count 0 2006.197.07:52:19.51#ibcon#read 3, iclass 32, count 0 2006.197.07:52:19.51#ibcon#about to read 4, iclass 32, count 0 2006.197.07:52:19.51#ibcon#read 4, iclass 32, count 0 2006.197.07:52:19.51#ibcon#about to read 5, iclass 32, count 0 2006.197.07:52:19.51#ibcon#read 5, iclass 32, count 0 2006.197.07:52:19.51#ibcon#about to read 6, iclass 32, count 0 2006.197.07:52:19.51#ibcon#read 6, iclass 32, count 0 2006.197.07:52:19.51#ibcon#end of sib2, iclass 32, count 0 2006.197.07:52:19.51#ibcon#*after write, iclass 32, count 0 2006.197.07:52:19.51#ibcon#*before return 0, iclass 32, count 0 2006.197.07:52:19.51#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.197.07:52:19.51#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.197.07:52:19.51#ibcon#about to clear, iclass 32 cls_cnt 0 2006.197.07:52:19.51#ibcon#cleared, iclass 32 cls_cnt 0 2006.197.07:52:19.51$vc4f8/valo=7,832.99 2006.197.07:52:19.51#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.197.07:52:19.51#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.197.07:52:19.51#ibcon#ireg 17 cls_cnt 0 2006.197.07:52:19.51#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.197.07:52:19.51#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.197.07:52:19.51#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.197.07:52:19.51#ibcon#enter wrdev, iclass 34, count 0 2006.197.07:52:19.51#ibcon#first serial, iclass 34, count 0 2006.197.07:52:19.51#ibcon#enter sib2, iclass 34, count 0 2006.197.07:52:19.51#ibcon#flushed, iclass 34, count 0 2006.197.07:52:19.51#ibcon#about to write, iclass 34, count 0 2006.197.07:52:19.51#ibcon#wrote, iclass 34, count 0 2006.197.07:52:19.51#ibcon#about to read 3, iclass 34, count 0 2006.197.07:52:19.53#ibcon#read 3, iclass 34, count 0 2006.197.07:52:19.53#ibcon#about to read 4, iclass 34, count 0 2006.197.07:52:19.53#ibcon#read 4, iclass 34, count 0 2006.197.07:52:19.53#ibcon#about to read 5, iclass 34, count 0 2006.197.07:52:19.53#ibcon#read 5, iclass 34, count 0 2006.197.07:52:19.53#ibcon#about to read 6, iclass 34, count 0 2006.197.07:52:19.53#ibcon#read 6, iclass 34, count 0 2006.197.07:52:19.53#ibcon#end of sib2, iclass 34, count 0 2006.197.07:52:19.53#ibcon#*mode == 0, iclass 34, count 0 2006.197.07:52:19.53#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.197.07:52:19.53#ibcon#[26=FRQ=07,832.99\r\n] 2006.197.07:52:19.53#ibcon#*before write, iclass 34, count 0 2006.197.07:52:19.53#ibcon#enter sib2, iclass 34, count 0 2006.197.07:52:19.53#ibcon#flushed, iclass 34, count 0 2006.197.07:52:19.53#ibcon#about to write, iclass 34, count 0 2006.197.07:52:19.53#ibcon#wrote, iclass 34, count 0 2006.197.07:52:19.53#ibcon#about to read 3, iclass 34, count 0 2006.197.07:52:19.57#ibcon#read 3, iclass 34, count 0 2006.197.07:52:19.57#ibcon#about to read 4, iclass 34, count 0 2006.197.07:52:19.57#ibcon#read 4, iclass 34, count 0 2006.197.07:52:19.57#ibcon#about to read 5, iclass 34, count 0 2006.197.07:52:19.57#ibcon#read 5, iclass 34, count 0 2006.197.07:52:19.57#ibcon#about to read 6, iclass 34, count 0 2006.197.07:52:19.57#ibcon#read 6, iclass 34, count 0 2006.197.07:52:19.57#ibcon#end of sib2, iclass 34, count 0 2006.197.07:52:19.57#ibcon#*after write, iclass 34, count 0 2006.197.07:52:19.57#ibcon#*before return 0, iclass 34, count 0 2006.197.07:52:19.57#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.197.07:52:19.57#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.197.07:52:19.57#ibcon#about to clear, iclass 34 cls_cnt 0 2006.197.07:52:19.57#ibcon#cleared, iclass 34 cls_cnt 0 2006.197.07:52:19.57$vc4f8/va=7,6 2006.197.07:52:19.57#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.197.07:52:19.57#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.197.07:52:19.57#ibcon#ireg 11 cls_cnt 2 2006.197.07:52:19.57#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.197.07:52:19.63#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.197.07:52:19.63#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.197.07:52:19.63#ibcon#enter wrdev, iclass 36, count 2 2006.197.07:52:19.63#ibcon#first serial, iclass 36, count 2 2006.197.07:52:19.63#ibcon#enter sib2, iclass 36, count 2 2006.197.07:52:19.63#ibcon#flushed, iclass 36, count 2 2006.197.07:52:19.63#ibcon#about to write, iclass 36, count 2 2006.197.07:52:19.63#ibcon#wrote, iclass 36, count 2 2006.197.07:52:19.63#ibcon#about to read 3, iclass 36, count 2 2006.197.07:52:19.65#ibcon#read 3, iclass 36, count 2 2006.197.07:52:19.65#ibcon#about to read 4, iclass 36, count 2 2006.197.07:52:19.65#ibcon#read 4, iclass 36, count 2 2006.197.07:52:19.65#ibcon#about to read 5, iclass 36, count 2 2006.197.07:52:19.65#ibcon#read 5, iclass 36, count 2 2006.197.07:52:19.65#ibcon#about to read 6, iclass 36, count 2 2006.197.07:52:19.65#ibcon#read 6, iclass 36, count 2 2006.197.07:52:19.65#ibcon#end of sib2, iclass 36, count 2 2006.197.07:52:19.65#ibcon#*mode == 0, iclass 36, count 2 2006.197.07:52:19.65#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.197.07:52:19.65#ibcon#[25=AT07-06\r\n] 2006.197.07:52:19.65#ibcon#*before write, iclass 36, count 2 2006.197.07:52:19.65#ibcon#enter sib2, iclass 36, count 2 2006.197.07:52:19.65#ibcon#flushed, iclass 36, count 2 2006.197.07:52:19.65#ibcon#about to write, iclass 36, count 2 2006.197.07:52:19.65#ibcon#wrote, iclass 36, count 2 2006.197.07:52:19.65#ibcon#about to read 3, iclass 36, count 2 2006.197.07:52:19.68#ibcon#read 3, iclass 36, count 2 2006.197.07:52:19.68#ibcon#about to read 4, iclass 36, count 2 2006.197.07:52:19.68#ibcon#read 4, iclass 36, count 2 2006.197.07:52:19.68#ibcon#about to read 5, iclass 36, count 2 2006.197.07:52:19.68#ibcon#read 5, iclass 36, count 2 2006.197.07:52:19.68#ibcon#about to read 6, iclass 36, count 2 2006.197.07:52:19.68#ibcon#read 6, iclass 36, count 2 2006.197.07:52:19.68#ibcon#end of sib2, iclass 36, count 2 2006.197.07:52:19.68#ibcon#*after write, iclass 36, count 2 2006.197.07:52:19.68#ibcon#*before return 0, iclass 36, count 2 2006.197.07:52:19.68#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.197.07:52:19.68#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.197.07:52:19.68#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.197.07:52:19.68#ibcon#ireg 7 cls_cnt 0 2006.197.07:52:19.68#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.197.07:52:19.70#abcon#<5=/05 3.1 5.2 25.78 971003.1\r\n> 2006.197.07:52:19.72#abcon#{5=INTERFACE CLEAR} 2006.197.07:52:19.78#abcon#[5=S1D000X0/0*\r\n] 2006.197.07:52:19.80#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.197.07:52:19.80#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.197.07:52:19.80#ibcon#enter wrdev, iclass 36, count 0 2006.197.07:52:19.80#ibcon#first serial, iclass 36, count 0 2006.197.07:52:19.80#ibcon#enter sib2, iclass 36, count 0 2006.197.07:52:19.80#ibcon#flushed, iclass 36, count 0 2006.197.07:52:19.80#ibcon#about to write, iclass 36, count 0 2006.197.07:52:19.80#ibcon#wrote, iclass 36, count 0 2006.197.07:52:19.80#ibcon#about to read 3, iclass 36, count 0 2006.197.07:52:19.82#ibcon#read 3, iclass 36, count 0 2006.197.07:52:19.82#ibcon#about to read 4, iclass 36, count 0 2006.197.07:52:19.82#ibcon#read 4, iclass 36, count 0 2006.197.07:52:19.82#ibcon#about to read 5, iclass 36, count 0 2006.197.07:52:19.82#ibcon#read 5, iclass 36, count 0 2006.197.07:52:19.82#ibcon#about to read 6, iclass 36, count 0 2006.197.07:52:19.82#ibcon#read 6, iclass 36, count 0 2006.197.07:52:19.82#ibcon#end of sib2, iclass 36, count 0 2006.197.07:52:19.82#ibcon#*mode == 0, iclass 36, count 0 2006.197.07:52:19.82#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.197.07:52:19.82#ibcon#[25=USB\r\n] 2006.197.07:52:19.82#ibcon#*before write, iclass 36, count 0 2006.197.07:52:19.82#ibcon#enter sib2, iclass 36, count 0 2006.197.07:52:19.82#ibcon#flushed, iclass 36, count 0 2006.197.07:52:19.82#ibcon#about to write, iclass 36, count 0 2006.197.07:52:19.82#ibcon#wrote, iclass 36, count 0 2006.197.07:52:19.82#ibcon#about to read 3, iclass 36, count 0 2006.197.07:52:19.85#ibcon#read 3, iclass 36, count 0 2006.197.07:52:19.85#ibcon#about to read 4, iclass 36, count 0 2006.197.07:52:19.85#ibcon#read 4, iclass 36, count 0 2006.197.07:52:19.85#ibcon#about to read 5, iclass 36, count 0 2006.197.07:52:19.85#ibcon#read 5, iclass 36, count 0 2006.197.07:52:19.85#ibcon#about to read 6, iclass 36, count 0 2006.197.07:52:19.85#ibcon#read 6, iclass 36, count 0 2006.197.07:52:19.85#ibcon#end of sib2, iclass 36, count 0 2006.197.07:52:19.85#ibcon#*after write, iclass 36, count 0 2006.197.07:52:19.85#ibcon#*before return 0, iclass 36, count 0 2006.197.07:52:19.85#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.197.07:52:19.85#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.197.07:52:19.85#ibcon#about to clear, iclass 36 cls_cnt 0 2006.197.07:52:19.85#ibcon#cleared, iclass 36 cls_cnt 0 2006.197.07:52:19.85$vc4f8/valo=8,852.99 2006.197.07:52:19.85#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.197.07:52:19.85#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.197.07:52:19.85#ibcon#ireg 17 cls_cnt 0 2006.197.07:52:19.85#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.197.07:52:19.85#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.197.07:52:19.85#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.197.07:52:19.85#ibcon#enter wrdev, iclass 4, count 0 2006.197.07:52:19.85#ibcon#first serial, iclass 4, count 0 2006.197.07:52:19.85#ibcon#enter sib2, iclass 4, count 0 2006.197.07:52:19.85#ibcon#flushed, iclass 4, count 0 2006.197.07:52:19.85#ibcon#about to write, iclass 4, count 0 2006.197.07:52:19.85#ibcon#wrote, iclass 4, count 0 2006.197.07:52:19.85#ibcon#about to read 3, iclass 4, count 0 2006.197.07:52:19.87#ibcon#read 3, iclass 4, count 0 2006.197.07:52:19.87#ibcon#about to read 4, iclass 4, count 0 2006.197.07:52:19.87#ibcon#read 4, iclass 4, count 0 2006.197.07:52:19.87#ibcon#about to read 5, iclass 4, count 0 2006.197.07:52:19.87#ibcon#read 5, iclass 4, count 0 2006.197.07:52:19.87#ibcon#about to read 6, iclass 4, count 0 2006.197.07:52:19.87#ibcon#read 6, iclass 4, count 0 2006.197.07:52:19.87#ibcon#end of sib2, iclass 4, count 0 2006.197.07:52:19.87#ibcon#*mode == 0, iclass 4, count 0 2006.197.07:52:19.87#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.197.07:52:19.87#ibcon#[26=FRQ=08,852.99\r\n] 2006.197.07:52:19.87#ibcon#*before write, iclass 4, count 0 2006.197.07:52:19.87#ibcon#enter sib2, iclass 4, count 0 2006.197.07:52:19.87#ibcon#flushed, iclass 4, count 0 2006.197.07:52:19.87#ibcon#about to write, iclass 4, count 0 2006.197.07:52:19.87#ibcon#wrote, iclass 4, count 0 2006.197.07:52:19.87#ibcon#about to read 3, iclass 4, count 0 2006.197.07:52:19.91#ibcon#read 3, iclass 4, count 0 2006.197.07:52:19.91#ibcon#about to read 4, iclass 4, count 0 2006.197.07:52:19.91#ibcon#read 4, iclass 4, count 0 2006.197.07:52:19.91#ibcon#about to read 5, iclass 4, count 0 2006.197.07:52:19.91#ibcon#read 5, iclass 4, count 0 2006.197.07:52:19.91#ibcon#about to read 6, iclass 4, count 0 2006.197.07:52:19.91#ibcon#read 6, iclass 4, count 0 2006.197.07:52:19.91#ibcon#end of sib2, iclass 4, count 0 2006.197.07:52:19.91#ibcon#*after write, iclass 4, count 0 2006.197.07:52:19.91#ibcon#*before return 0, iclass 4, count 0 2006.197.07:52:19.91#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.197.07:52:19.91#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.197.07:52:19.91#ibcon#about to clear, iclass 4 cls_cnt 0 2006.197.07:52:19.91#ibcon#cleared, iclass 4 cls_cnt 0 2006.197.07:52:19.91$vc4f8/va=8,7 2006.197.07:52:19.91#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.197.07:52:19.91#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.197.07:52:19.91#ibcon#ireg 11 cls_cnt 2 2006.197.07:52:19.91#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.197.07:52:19.97#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.197.07:52:19.97#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.197.07:52:19.97#ibcon#enter wrdev, iclass 6, count 2 2006.197.07:52:19.97#ibcon#first serial, iclass 6, count 2 2006.197.07:52:19.97#ibcon#enter sib2, iclass 6, count 2 2006.197.07:52:19.97#ibcon#flushed, iclass 6, count 2 2006.197.07:52:19.97#ibcon#about to write, iclass 6, count 2 2006.197.07:52:19.97#ibcon#wrote, iclass 6, count 2 2006.197.07:52:19.97#ibcon#about to read 3, iclass 6, count 2 2006.197.07:52:19.99#ibcon#read 3, iclass 6, count 2 2006.197.07:52:19.99#ibcon#about to read 4, iclass 6, count 2 2006.197.07:52:19.99#ibcon#read 4, iclass 6, count 2 2006.197.07:52:19.99#ibcon#about to read 5, iclass 6, count 2 2006.197.07:52:19.99#ibcon#read 5, iclass 6, count 2 2006.197.07:52:19.99#ibcon#about to read 6, iclass 6, count 2 2006.197.07:52:19.99#ibcon#read 6, iclass 6, count 2 2006.197.07:52:19.99#ibcon#end of sib2, iclass 6, count 2 2006.197.07:52:19.99#ibcon#*mode == 0, iclass 6, count 2 2006.197.07:52:19.99#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.197.07:52:19.99#ibcon#[25=AT08-07\r\n] 2006.197.07:52:19.99#ibcon#*before write, iclass 6, count 2 2006.197.07:52:19.99#ibcon#enter sib2, iclass 6, count 2 2006.197.07:52:19.99#ibcon#flushed, iclass 6, count 2 2006.197.07:52:19.99#ibcon#about to write, iclass 6, count 2 2006.197.07:52:19.99#ibcon#wrote, iclass 6, count 2 2006.197.07:52:19.99#ibcon#about to read 3, iclass 6, count 2 2006.197.07:52:20.02#ibcon#read 3, iclass 6, count 2 2006.197.07:52:20.02#ibcon#about to read 4, iclass 6, count 2 2006.197.07:52:20.02#ibcon#read 4, iclass 6, count 2 2006.197.07:52:20.02#ibcon#about to read 5, iclass 6, count 2 2006.197.07:52:20.02#ibcon#read 5, iclass 6, count 2 2006.197.07:52:20.02#ibcon#about to read 6, iclass 6, count 2 2006.197.07:52:20.02#ibcon#read 6, iclass 6, count 2 2006.197.07:52:20.02#ibcon#end of sib2, iclass 6, count 2 2006.197.07:52:20.02#ibcon#*after write, iclass 6, count 2 2006.197.07:52:20.02#ibcon#*before return 0, iclass 6, count 2 2006.197.07:52:20.02#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.197.07:52:20.02#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.197.07:52:20.02#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.197.07:52:20.02#ibcon#ireg 7 cls_cnt 0 2006.197.07:52:20.02#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.197.07:52:20.14#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.197.07:52:20.14#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.197.07:52:20.14#ibcon#enter wrdev, iclass 6, count 0 2006.197.07:52:20.14#ibcon#first serial, iclass 6, count 0 2006.197.07:52:20.14#ibcon#enter sib2, iclass 6, count 0 2006.197.07:52:20.14#ibcon#flushed, iclass 6, count 0 2006.197.07:52:20.14#ibcon#about to write, iclass 6, count 0 2006.197.07:52:20.14#ibcon#wrote, iclass 6, count 0 2006.197.07:52:20.14#ibcon#about to read 3, iclass 6, count 0 2006.197.07:52:20.16#ibcon#read 3, iclass 6, count 0 2006.197.07:52:20.16#ibcon#about to read 4, iclass 6, count 0 2006.197.07:52:20.16#ibcon#read 4, iclass 6, count 0 2006.197.07:52:20.16#ibcon#about to read 5, iclass 6, count 0 2006.197.07:52:20.16#ibcon#read 5, iclass 6, count 0 2006.197.07:52:20.16#ibcon#about to read 6, iclass 6, count 0 2006.197.07:52:20.16#ibcon#read 6, iclass 6, count 0 2006.197.07:52:20.16#ibcon#end of sib2, iclass 6, count 0 2006.197.07:52:20.16#ibcon#*mode == 0, iclass 6, count 0 2006.197.07:52:20.16#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.197.07:52:20.16#ibcon#[25=USB\r\n] 2006.197.07:52:20.16#ibcon#*before write, iclass 6, count 0 2006.197.07:52:20.16#ibcon#enter sib2, iclass 6, count 0 2006.197.07:52:20.16#ibcon#flushed, iclass 6, count 0 2006.197.07:52:20.16#ibcon#about to write, iclass 6, count 0 2006.197.07:52:20.16#ibcon#wrote, iclass 6, count 0 2006.197.07:52:20.16#ibcon#about to read 3, iclass 6, count 0 2006.197.07:52:20.19#ibcon#read 3, iclass 6, count 0 2006.197.07:52:20.19#ibcon#about to read 4, iclass 6, count 0 2006.197.07:52:20.19#ibcon#read 4, iclass 6, count 0 2006.197.07:52:20.19#ibcon#about to read 5, iclass 6, count 0 2006.197.07:52:20.19#ibcon#read 5, iclass 6, count 0 2006.197.07:52:20.19#ibcon#about to read 6, iclass 6, count 0 2006.197.07:52:20.19#ibcon#read 6, iclass 6, count 0 2006.197.07:52:20.19#ibcon#end of sib2, iclass 6, count 0 2006.197.07:52:20.19#ibcon#*after write, iclass 6, count 0 2006.197.07:52:20.19#ibcon#*before return 0, iclass 6, count 0 2006.197.07:52:20.19#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.197.07:52:20.19#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.197.07:52:20.19#ibcon#about to clear, iclass 6 cls_cnt 0 2006.197.07:52:20.19#ibcon#cleared, iclass 6 cls_cnt 0 2006.197.07:52:20.19$vc4f8/vblo=1,632.99 2006.197.07:52:20.19#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.197.07:52:20.19#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.197.07:52:20.19#ibcon#ireg 17 cls_cnt 0 2006.197.07:52:20.19#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.197.07:52:20.19#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.197.07:52:20.19#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.197.07:52:20.19#ibcon#enter wrdev, iclass 10, count 0 2006.197.07:52:20.19#ibcon#first serial, iclass 10, count 0 2006.197.07:52:20.19#ibcon#enter sib2, iclass 10, count 0 2006.197.07:52:20.19#ibcon#flushed, iclass 10, count 0 2006.197.07:52:20.19#ibcon#about to write, iclass 10, count 0 2006.197.07:52:20.19#ibcon#wrote, iclass 10, count 0 2006.197.07:52:20.19#ibcon#about to read 3, iclass 10, count 0 2006.197.07:52:20.21#ibcon#read 3, iclass 10, count 0 2006.197.07:52:20.21#ibcon#about to read 4, iclass 10, count 0 2006.197.07:52:20.21#ibcon#read 4, iclass 10, count 0 2006.197.07:52:20.21#ibcon#about to read 5, iclass 10, count 0 2006.197.07:52:20.21#ibcon#read 5, iclass 10, count 0 2006.197.07:52:20.21#ibcon#about to read 6, iclass 10, count 0 2006.197.07:52:20.21#ibcon#read 6, iclass 10, count 0 2006.197.07:52:20.21#ibcon#end of sib2, iclass 10, count 0 2006.197.07:52:20.21#ibcon#*mode == 0, iclass 10, count 0 2006.197.07:52:20.21#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.197.07:52:20.21#ibcon#[28=FRQ=01,632.99\r\n] 2006.197.07:52:20.21#ibcon#*before write, iclass 10, count 0 2006.197.07:52:20.21#ibcon#enter sib2, iclass 10, count 0 2006.197.07:52:20.21#ibcon#flushed, iclass 10, count 0 2006.197.07:52:20.21#ibcon#about to write, iclass 10, count 0 2006.197.07:52:20.21#ibcon#wrote, iclass 10, count 0 2006.197.07:52:20.21#ibcon#about to read 3, iclass 10, count 0 2006.197.07:52:20.25#ibcon#read 3, iclass 10, count 0 2006.197.07:52:20.25#ibcon#about to read 4, iclass 10, count 0 2006.197.07:52:20.25#ibcon#read 4, iclass 10, count 0 2006.197.07:52:20.25#ibcon#about to read 5, iclass 10, count 0 2006.197.07:52:20.25#ibcon#read 5, iclass 10, count 0 2006.197.07:52:20.25#ibcon#about to read 6, iclass 10, count 0 2006.197.07:52:20.25#ibcon#read 6, iclass 10, count 0 2006.197.07:52:20.25#ibcon#end of sib2, iclass 10, count 0 2006.197.07:52:20.25#ibcon#*after write, iclass 10, count 0 2006.197.07:52:20.25#ibcon#*before return 0, iclass 10, count 0 2006.197.07:52:20.25#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.197.07:52:20.25#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.197.07:52:20.25#ibcon#about to clear, iclass 10 cls_cnt 0 2006.197.07:52:20.25#ibcon#cleared, iclass 10 cls_cnt 0 2006.197.07:52:20.25$vc4f8/vb=1,4 2006.197.07:52:20.25#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.197.07:52:20.25#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.197.07:52:20.25#ibcon#ireg 11 cls_cnt 2 2006.197.07:52:20.25#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.197.07:52:20.25#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.197.07:52:20.25#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.197.07:52:20.25#ibcon#enter wrdev, iclass 12, count 2 2006.197.07:52:20.25#ibcon#first serial, iclass 12, count 2 2006.197.07:52:20.25#ibcon#enter sib2, iclass 12, count 2 2006.197.07:52:20.25#ibcon#flushed, iclass 12, count 2 2006.197.07:52:20.25#ibcon#about to write, iclass 12, count 2 2006.197.07:52:20.25#ibcon#wrote, iclass 12, count 2 2006.197.07:52:20.25#ibcon#about to read 3, iclass 12, count 2 2006.197.07:52:20.27#ibcon#read 3, iclass 12, count 2 2006.197.07:52:20.27#ibcon#about to read 4, iclass 12, count 2 2006.197.07:52:20.27#ibcon#read 4, iclass 12, count 2 2006.197.07:52:20.27#ibcon#about to read 5, iclass 12, count 2 2006.197.07:52:20.27#ibcon#read 5, iclass 12, count 2 2006.197.07:52:20.27#ibcon#about to read 6, iclass 12, count 2 2006.197.07:52:20.27#ibcon#read 6, iclass 12, count 2 2006.197.07:52:20.27#ibcon#end of sib2, iclass 12, count 2 2006.197.07:52:20.27#ibcon#*mode == 0, iclass 12, count 2 2006.197.07:52:20.27#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.197.07:52:20.27#ibcon#[27=AT01-04\r\n] 2006.197.07:52:20.27#ibcon#*before write, iclass 12, count 2 2006.197.07:52:20.27#ibcon#enter sib2, iclass 12, count 2 2006.197.07:52:20.27#ibcon#flushed, iclass 12, count 2 2006.197.07:52:20.27#ibcon#about to write, iclass 12, count 2 2006.197.07:52:20.27#ibcon#wrote, iclass 12, count 2 2006.197.07:52:20.27#ibcon#about to read 3, iclass 12, count 2 2006.197.07:52:20.30#ibcon#read 3, iclass 12, count 2 2006.197.07:52:20.30#ibcon#about to read 4, iclass 12, count 2 2006.197.07:52:20.30#ibcon#read 4, iclass 12, count 2 2006.197.07:52:20.30#ibcon#about to read 5, iclass 12, count 2 2006.197.07:52:20.30#ibcon#read 5, iclass 12, count 2 2006.197.07:52:20.30#ibcon#about to read 6, iclass 12, count 2 2006.197.07:52:20.30#ibcon#read 6, iclass 12, count 2 2006.197.07:52:20.30#ibcon#end of sib2, iclass 12, count 2 2006.197.07:52:20.30#ibcon#*after write, iclass 12, count 2 2006.197.07:52:20.30#ibcon#*before return 0, iclass 12, count 2 2006.197.07:52:20.30#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.197.07:52:20.30#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.197.07:52:20.30#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.197.07:52:20.30#ibcon#ireg 7 cls_cnt 0 2006.197.07:52:20.30#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.197.07:52:20.42#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.197.07:52:20.42#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.197.07:52:20.42#ibcon#enter wrdev, iclass 12, count 0 2006.197.07:52:20.42#ibcon#first serial, iclass 12, count 0 2006.197.07:52:20.42#ibcon#enter sib2, iclass 12, count 0 2006.197.07:52:20.42#ibcon#flushed, iclass 12, count 0 2006.197.07:52:20.42#ibcon#about to write, iclass 12, count 0 2006.197.07:52:20.42#ibcon#wrote, iclass 12, count 0 2006.197.07:52:20.42#ibcon#about to read 3, iclass 12, count 0 2006.197.07:52:20.44#ibcon#read 3, iclass 12, count 0 2006.197.07:52:20.44#ibcon#about to read 4, iclass 12, count 0 2006.197.07:52:20.44#ibcon#read 4, iclass 12, count 0 2006.197.07:52:20.44#ibcon#about to read 5, iclass 12, count 0 2006.197.07:52:20.44#ibcon#read 5, iclass 12, count 0 2006.197.07:52:20.44#ibcon#about to read 6, iclass 12, count 0 2006.197.07:52:20.44#ibcon#read 6, iclass 12, count 0 2006.197.07:52:20.44#ibcon#end of sib2, iclass 12, count 0 2006.197.07:52:20.44#ibcon#*mode == 0, iclass 12, count 0 2006.197.07:52:20.44#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.197.07:52:20.44#ibcon#[27=USB\r\n] 2006.197.07:52:20.44#ibcon#*before write, iclass 12, count 0 2006.197.07:52:20.44#ibcon#enter sib2, iclass 12, count 0 2006.197.07:52:20.44#ibcon#flushed, iclass 12, count 0 2006.197.07:52:20.44#ibcon#about to write, iclass 12, count 0 2006.197.07:52:20.44#ibcon#wrote, iclass 12, count 0 2006.197.07:52:20.44#ibcon#about to read 3, iclass 12, count 0 2006.197.07:52:20.47#ibcon#read 3, iclass 12, count 0 2006.197.07:52:20.47#ibcon#about to read 4, iclass 12, count 0 2006.197.07:52:20.47#ibcon#read 4, iclass 12, count 0 2006.197.07:52:20.47#ibcon#about to read 5, iclass 12, count 0 2006.197.07:52:20.47#ibcon#read 5, iclass 12, count 0 2006.197.07:52:20.47#ibcon#about to read 6, iclass 12, count 0 2006.197.07:52:20.47#ibcon#read 6, iclass 12, count 0 2006.197.07:52:20.47#ibcon#end of sib2, iclass 12, count 0 2006.197.07:52:20.47#ibcon#*after write, iclass 12, count 0 2006.197.07:52:20.47#ibcon#*before return 0, iclass 12, count 0 2006.197.07:52:20.47#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.197.07:52:20.47#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.197.07:52:20.47#ibcon#about to clear, iclass 12 cls_cnt 0 2006.197.07:52:20.47#ibcon#cleared, iclass 12 cls_cnt 0 2006.197.07:52:20.47$vc4f8/vblo=2,640.99 2006.197.07:52:20.47#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.197.07:52:20.47#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.197.07:52:20.47#ibcon#ireg 17 cls_cnt 0 2006.197.07:52:20.47#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.197.07:52:20.47#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.197.07:52:20.47#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.197.07:52:20.47#ibcon#enter wrdev, iclass 14, count 0 2006.197.07:52:20.47#ibcon#first serial, iclass 14, count 0 2006.197.07:52:20.47#ibcon#enter sib2, iclass 14, count 0 2006.197.07:52:20.47#ibcon#flushed, iclass 14, count 0 2006.197.07:52:20.47#ibcon#about to write, iclass 14, count 0 2006.197.07:52:20.47#ibcon#wrote, iclass 14, count 0 2006.197.07:52:20.47#ibcon#about to read 3, iclass 14, count 0 2006.197.07:52:20.49#ibcon#read 3, iclass 14, count 0 2006.197.07:52:20.49#ibcon#about to read 4, iclass 14, count 0 2006.197.07:52:20.49#ibcon#read 4, iclass 14, count 0 2006.197.07:52:20.49#ibcon#about to read 5, iclass 14, count 0 2006.197.07:52:20.49#ibcon#read 5, iclass 14, count 0 2006.197.07:52:20.49#ibcon#about to read 6, iclass 14, count 0 2006.197.07:52:20.49#ibcon#read 6, iclass 14, count 0 2006.197.07:52:20.49#ibcon#end of sib2, iclass 14, count 0 2006.197.07:52:20.49#ibcon#*mode == 0, iclass 14, count 0 2006.197.07:52:20.49#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.197.07:52:20.49#ibcon#[28=FRQ=02,640.99\r\n] 2006.197.07:52:20.49#ibcon#*before write, iclass 14, count 0 2006.197.07:52:20.49#ibcon#enter sib2, iclass 14, count 0 2006.197.07:52:20.49#ibcon#flushed, iclass 14, count 0 2006.197.07:52:20.49#ibcon#about to write, iclass 14, count 0 2006.197.07:52:20.49#ibcon#wrote, iclass 14, count 0 2006.197.07:52:20.49#ibcon#about to read 3, iclass 14, count 0 2006.197.07:52:20.53#ibcon#read 3, iclass 14, count 0 2006.197.07:52:20.53#ibcon#about to read 4, iclass 14, count 0 2006.197.07:52:20.53#ibcon#read 4, iclass 14, count 0 2006.197.07:52:20.53#ibcon#about to read 5, iclass 14, count 0 2006.197.07:52:20.53#ibcon#read 5, iclass 14, count 0 2006.197.07:52:20.53#ibcon#about to read 6, iclass 14, count 0 2006.197.07:52:20.53#ibcon#read 6, iclass 14, count 0 2006.197.07:52:20.53#ibcon#end of sib2, iclass 14, count 0 2006.197.07:52:20.53#ibcon#*after write, iclass 14, count 0 2006.197.07:52:20.53#ibcon#*before return 0, iclass 14, count 0 2006.197.07:52:20.53#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.197.07:52:20.53#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.197.07:52:20.53#ibcon#about to clear, iclass 14 cls_cnt 0 2006.197.07:52:20.53#ibcon#cleared, iclass 14 cls_cnt 0 2006.197.07:52:20.53$vc4f8/vb=2,4 2006.197.07:52:20.53#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.197.07:52:20.53#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.197.07:52:20.53#ibcon#ireg 11 cls_cnt 2 2006.197.07:52:20.53#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.197.07:52:20.59#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.197.07:52:20.59#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.197.07:52:20.59#ibcon#enter wrdev, iclass 16, count 2 2006.197.07:52:20.59#ibcon#first serial, iclass 16, count 2 2006.197.07:52:20.59#ibcon#enter sib2, iclass 16, count 2 2006.197.07:52:20.59#ibcon#flushed, iclass 16, count 2 2006.197.07:52:20.59#ibcon#about to write, iclass 16, count 2 2006.197.07:52:20.59#ibcon#wrote, iclass 16, count 2 2006.197.07:52:20.59#ibcon#about to read 3, iclass 16, count 2 2006.197.07:52:20.61#ibcon#read 3, iclass 16, count 2 2006.197.07:52:20.61#ibcon#about to read 4, iclass 16, count 2 2006.197.07:52:20.61#ibcon#read 4, iclass 16, count 2 2006.197.07:52:20.61#ibcon#about to read 5, iclass 16, count 2 2006.197.07:52:20.61#ibcon#read 5, iclass 16, count 2 2006.197.07:52:20.61#ibcon#about to read 6, iclass 16, count 2 2006.197.07:52:20.61#ibcon#read 6, iclass 16, count 2 2006.197.07:52:20.61#ibcon#end of sib2, iclass 16, count 2 2006.197.07:52:20.61#ibcon#*mode == 0, iclass 16, count 2 2006.197.07:52:20.61#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.197.07:52:20.61#ibcon#[27=AT02-04\r\n] 2006.197.07:52:20.61#ibcon#*before write, iclass 16, count 2 2006.197.07:52:20.61#ibcon#enter sib2, iclass 16, count 2 2006.197.07:52:20.61#ibcon#flushed, iclass 16, count 2 2006.197.07:52:20.61#ibcon#about to write, iclass 16, count 2 2006.197.07:52:20.61#ibcon#wrote, iclass 16, count 2 2006.197.07:52:20.61#ibcon#about to read 3, iclass 16, count 2 2006.197.07:52:20.64#ibcon#read 3, iclass 16, count 2 2006.197.07:52:20.64#ibcon#about to read 4, iclass 16, count 2 2006.197.07:52:20.64#ibcon#read 4, iclass 16, count 2 2006.197.07:52:20.64#ibcon#about to read 5, iclass 16, count 2 2006.197.07:52:20.64#ibcon#read 5, iclass 16, count 2 2006.197.07:52:20.64#ibcon#about to read 6, iclass 16, count 2 2006.197.07:52:20.64#ibcon#read 6, iclass 16, count 2 2006.197.07:52:20.64#ibcon#end of sib2, iclass 16, count 2 2006.197.07:52:20.64#ibcon#*after write, iclass 16, count 2 2006.197.07:52:20.64#ibcon#*before return 0, iclass 16, count 2 2006.197.07:52:20.64#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.197.07:52:20.64#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.197.07:52:20.64#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.197.07:52:20.64#ibcon#ireg 7 cls_cnt 0 2006.197.07:52:20.64#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.197.07:52:20.76#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.197.07:52:20.76#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.197.07:52:20.76#ibcon#enter wrdev, iclass 16, count 0 2006.197.07:52:20.76#ibcon#first serial, iclass 16, count 0 2006.197.07:52:20.76#ibcon#enter sib2, iclass 16, count 0 2006.197.07:52:20.76#ibcon#flushed, iclass 16, count 0 2006.197.07:52:20.76#ibcon#about to write, iclass 16, count 0 2006.197.07:52:20.76#ibcon#wrote, iclass 16, count 0 2006.197.07:52:20.76#ibcon#about to read 3, iclass 16, count 0 2006.197.07:52:20.78#ibcon#read 3, iclass 16, count 0 2006.197.07:52:20.78#ibcon#about to read 4, iclass 16, count 0 2006.197.07:52:20.78#ibcon#read 4, iclass 16, count 0 2006.197.07:52:20.78#ibcon#about to read 5, iclass 16, count 0 2006.197.07:52:20.78#ibcon#read 5, iclass 16, count 0 2006.197.07:52:20.78#ibcon#about to read 6, iclass 16, count 0 2006.197.07:52:20.78#ibcon#read 6, iclass 16, count 0 2006.197.07:52:20.78#ibcon#end of sib2, iclass 16, count 0 2006.197.07:52:20.78#ibcon#*mode == 0, iclass 16, count 0 2006.197.07:52:20.78#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.197.07:52:20.78#ibcon#[27=USB\r\n] 2006.197.07:52:20.78#ibcon#*before write, iclass 16, count 0 2006.197.07:52:20.78#ibcon#enter sib2, iclass 16, count 0 2006.197.07:52:20.78#ibcon#flushed, iclass 16, count 0 2006.197.07:52:20.78#ibcon#about to write, iclass 16, count 0 2006.197.07:52:20.78#ibcon#wrote, iclass 16, count 0 2006.197.07:52:20.78#ibcon#about to read 3, iclass 16, count 0 2006.197.07:52:20.81#ibcon#read 3, iclass 16, count 0 2006.197.07:52:20.81#ibcon#about to read 4, iclass 16, count 0 2006.197.07:52:20.81#ibcon#read 4, iclass 16, count 0 2006.197.07:52:20.81#ibcon#about to read 5, iclass 16, count 0 2006.197.07:52:20.81#ibcon#read 5, iclass 16, count 0 2006.197.07:52:20.81#ibcon#about to read 6, iclass 16, count 0 2006.197.07:52:20.81#ibcon#read 6, iclass 16, count 0 2006.197.07:52:20.81#ibcon#end of sib2, iclass 16, count 0 2006.197.07:52:20.81#ibcon#*after write, iclass 16, count 0 2006.197.07:52:20.81#ibcon#*before return 0, iclass 16, count 0 2006.197.07:52:20.81#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.197.07:52:20.81#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.197.07:52:20.81#ibcon#about to clear, iclass 16 cls_cnt 0 2006.197.07:52:20.81#ibcon#cleared, iclass 16 cls_cnt 0 2006.197.07:52:20.81$vc4f8/vblo=3,656.99 2006.197.07:52:20.81#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.197.07:52:20.81#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.197.07:52:20.81#ibcon#ireg 17 cls_cnt 0 2006.197.07:52:20.81#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.197.07:52:20.81#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.197.07:52:20.81#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.197.07:52:20.81#ibcon#enter wrdev, iclass 18, count 0 2006.197.07:52:20.81#ibcon#first serial, iclass 18, count 0 2006.197.07:52:20.81#ibcon#enter sib2, iclass 18, count 0 2006.197.07:52:20.81#ibcon#flushed, iclass 18, count 0 2006.197.07:52:20.81#ibcon#about to write, iclass 18, count 0 2006.197.07:52:20.81#ibcon#wrote, iclass 18, count 0 2006.197.07:52:20.81#ibcon#about to read 3, iclass 18, count 0 2006.197.07:52:20.83#ibcon#read 3, iclass 18, count 0 2006.197.07:52:20.83#ibcon#about to read 4, iclass 18, count 0 2006.197.07:52:20.83#ibcon#read 4, iclass 18, count 0 2006.197.07:52:20.83#ibcon#about to read 5, iclass 18, count 0 2006.197.07:52:20.83#ibcon#read 5, iclass 18, count 0 2006.197.07:52:20.83#ibcon#about to read 6, iclass 18, count 0 2006.197.07:52:20.83#ibcon#read 6, iclass 18, count 0 2006.197.07:52:20.83#ibcon#end of sib2, iclass 18, count 0 2006.197.07:52:20.83#ibcon#*mode == 0, iclass 18, count 0 2006.197.07:52:20.83#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.197.07:52:20.83#ibcon#[28=FRQ=03,656.99\r\n] 2006.197.07:52:20.83#ibcon#*before write, iclass 18, count 0 2006.197.07:52:20.83#ibcon#enter sib2, iclass 18, count 0 2006.197.07:52:20.83#ibcon#flushed, iclass 18, count 0 2006.197.07:52:20.83#ibcon#about to write, iclass 18, count 0 2006.197.07:52:20.83#ibcon#wrote, iclass 18, count 0 2006.197.07:52:20.83#ibcon#about to read 3, iclass 18, count 0 2006.197.07:52:20.87#ibcon#read 3, iclass 18, count 0 2006.197.07:52:20.87#ibcon#about to read 4, iclass 18, count 0 2006.197.07:52:20.87#ibcon#read 4, iclass 18, count 0 2006.197.07:52:20.87#ibcon#about to read 5, iclass 18, count 0 2006.197.07:52:20.87#ibcon#read 5, iclass 18, count 0 2006.197.07:52:20.87#ibcon#about to read 6, iclass 18, count 0 2006.197.07:52:20.87#ibcon#read 6, iclass 18, count 0 2006.197.07:52:20.87#ibcon#end of sib2, iclass 18, count 0 2006.197.07:52:20.87#ibcon#*after write, iclass 18, count 0 2006.197.07:52:20.87#ibcon#*before return 0, iclass 18, count 0 2006.197.07:52:20.87#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.197.07:52:20.87#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.197.07:52:20.87#ibcon#about to clear, iclass 18 cls_cnt 0 2006.197.07:52:20.87#ibcon#cleared, iclass 18 cls_cnt 0 2006.197.07:52:20.87$vc4f8/vb=3,4 2006.197.07:52:20.87#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.197.07:52:20.87#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.197.07:52:20.87#ibcon#ireg 11 cls_cnt 2 2006.197.07:52:20.87#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.197.07:52:20.93#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.197.07:52:20.93#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.197.07:52:20.93#ibcon#enter wrdev, iclass 20, count 2 2006.197.07:52:20.93#ibcon#first serial, iclass 20, count 2 2006.197.07:52:20.93#ibcon#enter sib2, iclass 20, count 2 2006.197.07:52:20.93#ibcon#flushed, iclass 20, count 2 2006.197.07:52:20.93#ibcon#about to write, iclass 20, count 2 2006.197.07:52:20.93#ibcon#wrote, iclass 20, count 2 2006.197.07:52:20.93#ibcon#about to read 3, iclass 20, count 2 2006.197.07:52:20.95#ibcon#read 3, iclass 20, count 2 2006.197.07:52:20.95#ibcon#about to read 4, iclass 20, count 2 2006.197.07:52:20.95#ibcon#read 4, iclass 20, count 2 2006.197.07:52:20.95#ibcon#about to read 5, iclass 20, count 2 2006.197.07:52:20.95#ibcon#read 5, iclass 20, count 2 2006.197.07:52:20.95#ibcon#about to read 6, iclass 20, count 2 2006.197.07:52:20.95#ibcon#read 6, iclass 20, count 2 2006.197.07:52:20.95#ibcon#end of sib2, iclass 20, count 2 2006.197.07:52:20.95#ibcon#*mode == 0, iclass 20, count 2 2006.197.07:52:20.95#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.197.07:52:20.95#ibcon#[27=AT03-04\r\n] 2006.197.07:52:20.95#ibcon#*before write, iclass 20, count 2 2006.197.07:52:20.95#ibcon#enter sib2, iclass 20, count 2 2006.197.07:52:20.95#ibcon#flushed, iclass 20, count 2 2006.197.07:52:20.95#ibcon#about to write, iclass 20, count 2 2006.197.07:52:20.95#ibcon#wrote, iclass 20, count 2 2006.197.07:52:20.95#ibcon#about to read 3, iclass 20, count 2 2006.197.07:52:20.98#ibcon#read 3, iclass 20, count 2 2006.197.07:52:20.98#ibcon#about to read 4, iclass 20, count 2 2006.197.07:52:20.98#ibcon#read 4, iclass 20, count 2 2006.197.07:52:20.98#ibcon#about to read 5, iclass 20, count 2 2006.197.07:52:20.98#ibcon#read 5, iclass 20, count 2 2006.197.07:52:20.98#ibcon#about to read 6, iclass 20, count 2 2006.197.07:52:20.98#ibcon#read 6, iclass 20, count 2 2006.197.07:52:20.98#ibcon#end of sib2, iclass 20, count 2 2006.197.07:52:20.98#ibcon#*after write, iclass 20, count 2 2006.197.07:52:20.98#ibcon#*before return 0, iclass 20, count 2 2006.197.07:52:20.98#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.197.07:52:20.98#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.197.07:52:20.98#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.197.07:52:20.98#ibcon#ireg 7 cls_cnt 0 2006.197.07:52:20.98#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.197.07:52:21.10#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.197.07:52:21.10#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.197.07:52:21.10#ibcon#enter wrdev, iclass 20, count 0 2006.197.07:52:21.10#ibcon#first serial, iclass 20, count 0 2006.197.07:52:21.10#ibcon#enter sib2, iclass 20, count 0 2006.197.07:52:21.10#ibcon#flushed, iclass 20, count 0 2006.197.07:52:21.10#ibcon#about to write, iclass 20, count 0 2006.197.07:52:21.10#ibcon#wrote, iclass 20, count 0 2006.197.07:52:21.10#ibcon#about to read 3, iclass 20, count 0 2006.197.07:52:21.12#ibcon#read 3, iclass 20, count 0 2006.197.07:52:21.12#ibcon#about to read 4, iclass 20, count 0 2006.197.07:52:21.12#ibcon#read 4, iclass 20, count 0 2006.197.07:52:21.12#ibcon#about to read 5, iclass 20, count 0 2006.197.07:52:21.12#ibcon#read 5, iclass 20, count 0 2006.197.07:52:21.12#ibcon#about to read 6, iclass 20, count 0 2006.197.07:52:21.12#ibcon#read 6, iclass 20, count 0 2006.197.07:52:21.12#ibcon#end of sib2, iclass 20, count 0 2006.197.07:52:21.12#ibcon#*mode == 0, iclass 20, count 0 2006.197.07:52:21.12#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.197.07:52:21.12#ibcon#[27=USB\r\n] 2006.197.07:52:21.12#ibcon#*before write, iclass 20, count 0 2006.197.07:52:21.12#ibcon#enter sib2, iclass 20, count 0 2006.197.07:52:21.12#ibcon#flushed, iclass 20, count 0 2006.197.07:52:21.12#ibcon#about to write, iclass 20, count 0 2006.197.07:52:21.12#ibcon#wrote, iclass 20, count 0 2006.197.07:52:21.12#ibcon#about to read 3, iclass 20, count 0 2006.197.07:52:21.15#ibcon#read 3, iclass 20, count 0 2006.197.07:52:21.15#ibcon#about to read 4, iclass 20, count 0 2006.197.07:52:21.15#ibcon#read 4, iclass 20, count 0 2006.197.07:52:21.15#ibcon#about to read 5, iclass 20, count 0 2006.197.07:52:21.15#ibcon#read 5, iclass 20, count 0 2006.197.07:52:21.15#ibcon#about to read 6, iclass 20, count 0 2006.197.07:52:21.15#ibcon#read 6, iclass 20, count 0 2006.197.07:52:21.15#ibcon#end of sib2, iclass 20, count 0 2006.197.07:52:21.15#ibcon#*after write, iclass 20, count 0 2006.197.07:52:21.15#ibcon#*before return 0, iclass 20, count 0 2006.197.07:52:21.15#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.197.07:52:21.15#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.197.07:52:21.15#ibcon#about to clear, iclass 20 cls_cnt 0 2006.197.07:52:21.15#ibcon#cleared, iclass 20 cls_cnt 0 2006.197.07:52:21.15$vc4f8/vblo=4,712.99 2006.197.07:52:21.15#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.197.07:52:21.15#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.197.07:52:21.15#ibcon#ireg 17 cls_cnt 0 2006.197.07:52:21.15#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.197.07:52:21.15#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.197.07:52:21.15#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.197.07:52:21.15#ibcon#enter wrdev, iclass 22, count 0 2006.197.07:52:21.15#ibcon#first serial, iclass 22, count 0 2006.197.07:52:21.15#ibcon#enter sib2, iclass 22, count 0 2006.197.07:52:21.15#ibcon#flushed, iclass 22, count 0 2006.197.07:52:21.15#ibcon#about to write, iclass 22, count 0 2006.197.07:52:21.15#ibcon#wrote, iclass 22, count 0 2006.197.07:52:21.15#ibcon#about to read 3, iclass 22, count 0 2006.197.07:52:21.17#ibcon#read 3, iclass 22, count 0 2006.197.07:52:21.17#ibcon#about to read 4, iclass 22, count 0 2006.197.07:52:21.17#ibcon#read 4, iclass 22, count 0 2006.197.07:52:21.17#ibcon#about to read 5, iclass 22, count 0 2006.197.07:52:21.17#ibcon#read 5, iclass 22, count 0 2006.197.07:52:21.17#ibcon#about to read 6, iclass 22, count 0 2006.197.07:52:21.17#ibcon#read 6, iclass 22, count 0 2006.197.07:52:21.17#ibcon#end of sib2, iclass 22, count 0 2006.197.07:52:21.17#ibcon#*mode == 0, iclass 22, count 0 2006.197.07:52:21.17#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.197.07:52:21.17#ibcon#[28=FRQ=04,712.99\r\n] 2006.197.07:52:21.17#ibcon#*before write, iclass 22, count 0 2006.197.07:52:21.17#ibcon#enter sib2, iclass 22, count 0 2006.197.07:52:21.17#ibcon#flushed, iclass 22, count 0 2006.197.07:52:21.17#ibcon#about to write, iclass 22, count 0 2006.197.07:52:21.17#ibcon#wrote, iclass 22, count 0 2006.197.07:52:21.17#ibcon#about to read 3, iclass 22, count 0 2006.197.07:52:21.21#ibcon#read 3, iclass 22, count 0 2006.197.07:52:21.21#ibcon#about to read 4, iclass 22, count 0 2006.197.07:52:21.21#ibcon#read 4, iclass 22, count 0 2006.197.07:52:21.21#ibcon#about to read 5, iclass 22, count 0 2006.197.07:52:21.21#ibcon#read 5, iclass 22, count 0 2006.197.07:52:21.21#ibcon#about to read 6, iclass 22, count 0 2006.197.07:52:21.21#ibcon#read 6, iclass 22, count 0 2006.197.07:52:21.21#ibcon#end of sib2, iclass 22, count 0 2006.197.07:52:21.21#ibcon#*after write, iclass 22, count 0 2006.197.07:52:21.21#ibcon#*before return 0, iclass 22, count 0 2006.197.07:52:21.21#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.197.07:52:21.21#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.197.07:52:21.21#ibcon#about to clear, iclass 22 cls_cnt 0 2006.197.07:52:21.21#ibcon#cleared, iclass 22 cls_cnt 0 2006.197.07:52:21.21$vc4f8/vb=4,4 2006.197.07:52:21.21#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.197.07:52:21.21#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.197.07:52:21.21#ibcon#ireg 11 cls_cnt 2 2006.197.07:52:21.21#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.197.07:52:21.27#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.197.07:52:21.27#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.197.07:52:21.27#ibcon#enter wrdev, iclass 24, count 2 2006.197.07:52:21.27#ibcon#first serial, iclass 24, count 2 2006.197.07:52:21.27#ibcon#enter sib2, iclass 24, count 2 2006.197.07:52:21.27#ibcon#flushed, iclass 24, count 2 2006.197.07:52:21.27#ibcon#about to write, iclass 24, count 2 2006.197.07:52:21.27#ibcon#wrote, iclass 24, count 2 2006.197.07:52:21.27#ibcon#about to read 3, iclass 24, count 2 2006.197.07:52:21.29#ibcon#read 3, iclass 24, count 2 2006.197.07:52:21.29#ibcon#about to read 4, iclass 24, count 2 2006.197.07:52:21.29#ibcon#read 4, iclass 24, count 2 2006.197.07:52:21.29#ibcon#about to read 5, iclass 24, count 2 2006.197.07:52:21.29#ibcon#read 5, iclass 24, count 2 2006.197.07:52:21.29#ibcon#about to read 6, iclass 24, count 2 2006.197.07:52:21.29#ibcon#read 6, iclass 24, count 2 2006.197.07:52:21.29#ibcon#end of sib2, iclass 24, count 2 2006.197.07:52:21.29#ibcon#*mode == 0, iclass 24, count 2 2006.197.07:52:21.29#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.197.07:52:21.29#ibcon#[27=AT04-04\r\n] 2006.197.07:52:21.29#ibcon#*before write, iclass 24, count 2 2006.197.07:52:21.29#ibcon#enter sib2, iclass 24, count 2 2006.197.07:52:21.29#ibcon#flushed, iclass 24, count 2 2006.197.07:52:21.29#ibcon#about to write, iclass 24, count 2 2006.197.07:52:21.29#ibcon#wrote, iclass 24, count 2 2006.197.07:52:21.29#ibcon#about to read 3, iclass 24, count 2 2006.197.07:52:21.32#ibcon#read 3, iclass 24, count 2 2006.197.07:52:21.32#ibcon#about to read 4, iclass 24, count 2 2006.197.07:52:21.32#ibcon#read 4, iclass 24, count 2 2006.197.07:52:21.32#ibcon#about to read 5, iclass 24, count 2 2006.197.07:52:21.32#ibcon#read 5, iclass 24, count 2 2006.197.07:52:21.32#ibcon#about to read 6, iclass 24, count 2 2006.197.07:52:21.32#ibcon#read 6, iclass 24, count 2 2006.197.07:52:21.32#ibcon#end of sib2, iclass 24, count 2 2006.197.07:52:21.32#ibcon#*after write, iclass 24, count 2 2006.197.07:52:21.32#ibcon#*before return 0, iclass 24, count 2 2006.197.07:52:21.32#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.197.07:52:21.32#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.197.07:52:21.32#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.197.07:52:21.32#ibcon#ireg 7 cls_cnt 0 2006.197.07:52:21.32#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.197.07:52:21.44#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.197.07:52:21.44#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.197.07:52:21.44#ibcon#enter wrdev, iclass 24, count 0 2006.197.07:52:21.44#ibcon#first serial, iclass 24, count 0 2006.197.07:52:21.44#ibcon#enter sib2, iclass 24, count 0 2006.197.07:52:21.44#ibcon#flushed, iclass 24, count 0 2006.197.07:52:21.44#ibcon#about to write, iclass 24, count 0 2006.197.07:52:21.44#ibcon#wrote, iclass 24, count 0 2006.197.07:52:21.44#ibcon#about to read 3, iclass 24, count 0 2006.197.07:52:21.46#ibcon#read 3, iclass 24, count 0 2006.197.07:52:21.46#ibcon#about to read 4, iclass 24, count 0 2006.197.07:52:21.46#ibcon#read 4, iclass 24, count 0 2006.197.07:52:21.46#ibcon#about to read 5, iclass 24, count 0 2006.197.07:52:21.46#ibcon#read 5, iclass 24, count 0 2006.197.07:52:21.46#ibcon#about to read 6, iclass 24, count 0 2006.197.07:52:21.46#ibcon#read 6, iclass 24, count 0 2006.197.07:52:21.46#ibcon#end of sib2, iclass 24, count 0 2006.197.07:52:21.46#ibcon#*mode == 0, iclass 24, count 0 2006.197.07:52:21.46#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.197.07:52:21.46#ibcon#[27=USB\r\n] 2006.197.07:52:21.46#ibcon#*before write, iclass 24, count 0 2006.197.07:52:21.46#ibcon#enter sib2, iclass 24, count 0 2006.197.07:52:21.46#ibcon#flushed, iclass 24, count 0 2006.197.07:52:21.46#ibcon#about to write, iclass 24, count 0 2006.197.07:52:21.46#ibcon#wrote, iclass 24, count 0 2006.197.07:52:21.46#ibcon#about to read 3, iclass 24, count 0 2006.197.07:52:21.49#ibcon#read 3, iclass 24, count 0 2006.197.07:52:21.49#ibcon#about to read 4, iclass 24, count 0 2006.197.07:52:21.49#ibcon#read 4, iclass 24, count 0 2006.197.07:52:21.49#ibcon#about to read 5, iclass 24, count 0 2006.197.07:52:21.49#ibcon#read 5, iclass 24, count 0 2006.197.07:52:21.49#ibcon#about to read 6, iclass 24, count 0 2006.197.07:52:21.49#ibcon#read 6, iclass 24, count 0 2006.197.07:52:21.49#ibcon#end of sib2, iclass 24, count 0 2006.197.07:52:21.49#ibcon#*after write, iclass 24, count 0 2006.197.07:52:21.49#ibcon#*before return 0, iclass 24, count 0 2006.197.07:52:21.49#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.197.07:52:21.49#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.197.07:52:21.49#ibcon#about to clear, iclass 24 cls_cnt 0 2006.197.07:52:21.49#ibcon#cleared, iclass 24 cls_cnt 0 2006.197.07:52:21.49$vc4f8/vblo=5,744.99 2006.197.07:52:21.49#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.197.07:52:21.49#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.197.07:52:21.49#ibcon#ireg 17 cls_cnt 0 2006.197.07:52:21.49#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.197.07:52:21.49#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.197.07:52:21.49#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.197.07:52:21.49#ibcon#enter wrdev, iclass 26, count 0 2006.197.07:52:21.49#ibcon#first serial, iclass 26, count 0 2006.197.07:52:21.49#ibcon#enter sib2, iclass 26, count 0 2006.197.07:52:21.49#ibcon#flushed, iclass 26, count 0 2006.197.07:52:21.49#ibcon#about to write, iclass 26, count 0 2006.197.07:52:21.49#ibcon#wrote, iclass 26, count 0 2006.197.07:52:21.49#ibcon#about to read 3, iclass 26, count 0 2006.197.07:52:21.51#ibcon#read 3, iclass 26, count 0 2006.197.07:52:21.51#ibcon#about to read 4, iclass 26, count 0 2006.197.07:52:21.51#ibcon#read 4, iclass 26, count 0 2006.197.07:52:21.51#ibcon#about to read 5, iclass 26, count 0 2006.197.07:52:21.51#ibcon#read 5, iclass 26, count 0 2006.197.07:52:21.51#ibcon#about to read 6, iclass 26, count 0 2006.197.07:52:21.51#ibcon#read 6, iclass 26, count 0 2006.197.07:52:21.51#ibcon#end of sib2, iclass 26, count 0 2006.197.07:52:21.51#ibcon#*mode == 0, iclass 26, count 0 2006.197.07:52:21.51#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.197.07:52:21.51#ibcon#[28=FRQ=05,744.99\r\n] 2006.197.07:52:21.51#ibcon#*before write, iclass 26, count 0 2006.197.07:52:21.51#ibcon#enter sib2, iclass 26, count 0 2006.197.07:52:21.51#ibcon#flushed, iclass 26, count 0 2006.197.07:52:21.51#ibcon#about to write, iclass 26, count 0 2006.197.07:52:21.51#ibcon#wrote, iclass 26, count 0 2006.197.07:52:21.51#ibcon#about to read 3, iclass 26, count 0 2006.197.07:52:21.55#ibcon#read 3, iclass 26, count 0 2006.197.07:52:21.55#ibcon#about to read 4, iclass 26, count 0 2006.197.07:52:21.55#ibcon#read 4, iclass 26, count 0 2006.197.07:52:21.55#ibcon#about to read 5, iclass 26, count 0 2006.197.07:52:21.55#ibcon#read 5, iclass 26, count 0 2006.197.07:52:21.55#ibcon#about to read 6, iclass 26, count 0 2006.197.07:52:21.55#ibcon#read 6, iclass 26, count 0 2006.197.07:52:21.55#ibcon#end of sib2, iclass 26, count 0 2006.197.07:52:21.55#ibcon#*after write, iclass 26, count 0 2006.197.07:52:21.55#ibcon#*before return 0, iclass 26, count 0 2006.197.07:52:21.55#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.197.07:52:21.55#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.197.07:52:21.55#ibcon#about to clear, iclass 26 cls_cnt 0 2006.197.07:52:21.55#ibcon#cleared, iclass 26 cls_cnt 0 2006.197.07:52:21.55$vc4f8/vb=5,4 2006.197.07:52:21.55#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.197.07:52:21.55#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.197.07:52:21.55#ibcon#ireg 11 cls_cnt 2 2006.197.07:52:21.55#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.197.07:52:21.61#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.197.07:52:21.61#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.197.07:52:21.61#ibcon#enter wrdev, iclass 28, count 2 2006.197.07:52:21.61#ibcon#first serial, iclass 28, count 2 2006.197.07:52:21.61#ibcon#enter sib2, iclass 28, count 2 2006.197.07:52:21.61#ibcon#flushed, iclass 28, count 2 2006.197.07:52:21.61#ibcon#about to write, iclass 28, count 2 2006.197.07:52:21.61#ibcon#wrote, iclass 28, count 2 2006.197.07:52:21.61#ibcon#about to read 3, iclass 28, count 2 2006.197.07:52:21.63#ibcon#read 3, iclass 28, count 2 2006.197.07:52:21.63#ibcon#about to read 4, iclass 28, count 2 2006.197.07:52:21.63#ibcon#read 4, iclass 28, count 2 2006.197.07:52:21.63#ibcon#about to read 5, iclass 28, count 2 2006.197.07:52:21.63#ibcon#read 5, iclass 28, count 2 2006.197.07:52:21.63#ibcon#about to read 6, iclass 28, count 2 2006.197.07:52:21.63#ibcon#read 6, iclass 28, count 2 2006.197.07:52:21.63#ibcon#end of sib2, iclass 28, count 2 2006.197.07:52:21.63#ibcon#*mode == 0, iclass 28, count 2 2006.197.07:52:21.63#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.197.07:52:21.63#ibcon#[27=AT05-04\r\n] 2006.197.07:52:21.63#ibcon#*before write, iclass 28, count 2 2006.197.07:52:21.63#ibcon#enter sib2, iclass 28, count 2 2006.197.07:52:21.63#ibcon#flushed, iclass 28, count 2 2006.197.07:52:21.63#ibcon#about to write, iclass 28, count 2 2006.197.07:52:21.63#ibcon#wrote, iclass 28, count 2 2006.197.07:52:21.63#ibcon#about to read 3, iclass 28, count 2 2006.197.07:52:21.66#ibcon#read 3, iclass 28, count 2 2006.197.07:52:21.66#ibcon#about to read 4, iclass 28, count 2 2006.197.07:52:21.66#ibcon#read 4, iclass 28, count 2 2006.197.07:52:21.66#ibcon#about to read 5, iclass 28, count 2 2006.197.07:52:21.66#ibcon#read 5, iclass 28, count 2 2006.197.07:52:21.66#ibcon#about to read 6, iclass 28, count 2 2006.197.07:52:21.66#ibcon#read 6, iclass 28, count 2 2006.197.07:52:21.66#ibcon#end of sib2, iclass 28, count 2 2006.197.07:52:21.66#ibcon#*after write, iclass 28, count 2 2006.197.07:52:21.66#ibcon#*before return 0, iclass 28, count 2 2006.197.07:52:21.66#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.197.07:52:21.66#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.197.07:52:21.66#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.197.07:52:21.66#ibcon#ireg 7 cls_cnt 0 2006.197.07:52:21.66#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.197.07:52:21.78#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.197.07:52:21.78#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.197.07:52:21.78#ibcon#enter wrdev, iclass 28, count 0 2006.197.07:52:21.78#ibcon#first serial, iclass 28, count 0 2006.197.07:52:21.78#ibcon#enter sib2, iclass 28, count 0 2006.197.07:52:21.78#ibcon#flushed, iclass 28, count 0 2006.197.07:52:21.78#ibcon#about to write, iclass 28, count 0 2006.197.07:52:21.78#ibcon#wrote, iclass 28, count 0 2006.197.07:52:21.78#ibcon#about to read 3, iclass 28, count 0 2006.197.07:52:21.80#ibcon#read 3, iclass 28, count 0 2006.197.07:52:21.80#ibcon#about to read 4, iclass 28, count 0 2006.197.07:52:21.80#ibcon#read 4, iclass 28, count 0 2006.197.07:52:21.80#ibcon#about to read 5, iclass 28, count 0 2006.197.07:52:21.80#ibcon#read 5, iclass 28, count 0 2006.197.07:52:21.80#ibcon#about to read 6, iclass 28, count 0 2006.197.07:52:21.80#ibcon#read 6, iclass 28, count 0 2006.197.07:52:21.80#ibcon#end of sib2, iclass 28, count 0 2006.197.07:52:21.80#ibcon#*mode == 0, iclass 28, count 0 2006.197.07:52:21.80#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.197.07:52:21.80#ibcon#[27=USB\r\n] 2006.197.07:52:21.80#ibcon#*before write, iclass 28, count 0 2006.197.07:52:21.80#ibcon#enter sib2, iclass 28, count 0 2006.197.07:52:21.80#ibcon#flushed, iclass 28, count 0 2006.197.07:52:21.80#ibcon#about to write, iclass 28, count 0 2006.197.07:52:21.80#ibcon#wrote, iclass 28, count 0 2006.197.07:52:21.80#ibcon#about to read 3, iclass 28, count 0 2006.197.07:52:21.83#ibcon#read 3, iclass 28, count 0 2006.197.07:52:21.83#ibcon#about to read 4, iclass 28, count 0 2006.197.07:52:21.83#ibcon#read 4, iclass 28, count 0 2006.197.07:52:21.83#ibcon#about to read 5, iclass 28, count 0 2006.197.07:52:21.83#ibcon#read 5, iclass 28, count 0 2006.197.07:52:21.83#ibcon#about to read 6, iclass 28, count 0 2006.197.07:52:21.83#ibcon#read 6, iclass 28, count 0 2006.197.07:52:21.83#ibcon#end of sib2, iclass 28, count 0 2006.197.07:52:21.83#ibcon#*after write, iclass 28, count 0 2006.197.07:52:21.83#ibcon#*before return 0, iclass 28, count 0 2006.197.07:52:21.83#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.197.07:52:21.83#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.197.07:52:21.83#ibcon#about to clear, iclass 28 cls_cnt 0 2006.197.07:52:21.83#ibcon#cleared, iclass 28 cls_cnt 0 2006.197.07:52:21.83$vc4f8/vblo=6,752.99 2006.197.07:52:21.83#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.197.07:52:21.83#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.197.07:52:21.83#ibcon#ireg 17 cls_cnt 0 2006.197.07:52:21.83#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.197.07:52:21.83#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.197.07:52:21.83#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.197.07:52:21.83#ibcon#enter wrdev, iclass 30, count 0 2006.197.07:52:21.83#ibcon#first serial, iclass 30, count 0 2006.197.07:52:21.83#ibcon#enter sib2, iclass 30, count 0 2006.197.07:52:21.83#ibcon#flushed, iclass 30, count 0 2006.197.07:52:21.83#ibcon#about to write, iclass 30, count 0 2006.197.07:52:21.83#ibcon#wrote, iclass 30, count 0 2006.197.07:52:21.83#ibcon#about to read 3, iclass 30, count 0 2006.197.07:52:21.85#ibcon#read 3, iclass 30, count 0 2006.197.07:52:21.85#ibcon#about to read 4, iclass 30, count 0 2006.197.07:52:21.85#ibcon#read 4, iclass 30, count 0 2006.197.07:52:21.85#ibcon#about to read 5, iclass 30, count 0 2006.197.07:52:21.85#ibcon#read 5, iclass 30, count 0 2006.197.07:52:21.85#ibcon#about to read 6, iclass 30, count 0 2006.197.07:52:21.85#ibcon#read 6, iclass 30, count 0 2006.197.07:52:21.85#ibcon#end of sib2, iclass 30, count 0 2006.197.07:52:21.85#ibcon#*mode == 0, iclass 30, count 0 2006.197.07:52:21.85#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.197.07:52:21.85#ibcon#[28=FRQ=06,752.99\r\n] 2006.197.07:52:21.85#ibcon#*before write, iclass 30, count 0 2006.197.07:52:21.85#ibcon#enter sib2, iclass 30, count 0 2006.197.07:52:21.85#ibcon#flushed, iclass 30, count 0 2006.197.07:52:21.85#ibcon#about to write, iclass 30, count 0 2006.197.07:52:21.85#ibcon#wrote, iclass 30, count 0 2006.197.07:52:21.85#ibcon#about to read 3, iclass 30, count 0 2006.197.07:52:21.89#ibcon#read 3, iclass 30, count 0 2006.197.07:52:21.89#ibcon#about to read 4, iclass 30, count 0 2006.197.07:52:21.89#ibcon#read 4, iclass 30, count 0 2006.197.07:52:21.89#ibcon#about to read 5, iclass 30, count 0 2006.197.07:52:21.89#ibcon#read 5, iclass 30, count 0 2006.197.07:52:21.89#ibcon#about to read 6, iclass 30, count 0 2006.197.07:52:21.89#ibcon#read 6, iclass 30, count 0 2006.197.07:52:21.89#ibcon#end of sib2, iclass 30, count 0 2006.197.07:52:21.89#ibcon#*after write, iclass 30, count 0 2006.197.07:52:21.89#ibcon#*before return 0, iclass 30, count 0 2006.197.07:52:21.89#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.197.07:52:21.89#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.197.07:52:21.89#ibcon#about to clear, iclass 30 cls_cnt 0 2006.197.07:52:21.89#ibcon#cleared, iclass 30 cls_cnt 0 2006.197.07:52:21.89$vc4f8/vb=6,4 2006.197.07:52:21.89#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.197.07:52:21.89#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.197.07:52:21.89#ibcon#ireg 11 cls_cnt 2 2006.197.07:52:21.89#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.197.07:52:21.95#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.197.07:52:21.95#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.197.07:52:21.95#ibcon#enter wrdev, iclass 32, count 2 2006.197.07:52:21.95#ibcon#first serial, iclass 32, count 2 2006.197.07:52:21.95#ibcon#enter sib2, iclass 32, count 2 2006.197.07:52:21.95#ibcon#flushed, iclass 32, count 2 2006.197.07:52:21.95#ibcon#about to write, iclass 32, count 2 2006.197.07:52:21.95#ibcon#wrote, iclass 32, count 2 2006.197.07:52:21.95#ibcon#about to read 3, iclass 32, count 2 2006.197.07:52:21.97#ibcon#read 3, iclass 32, count 2 2006.197.07:52:21.97#ibcon#about to read 4, iclass 32, count 2 2006.197.07:52:21.97#ibcon#read 4, iclass 32, count 2 2006.197.07:52:21.97#ibcon#about to read 5, iclass 32, count 2 2006.197.07:52:21.97#ibcon#read 5, iclass 32, count 2 2006.197.07:52:21.97#ibcon#about to read 6, iclass 32, count 2 2006.197.07:52:21.97#ibcon#read 6, iclass 32, count 2 2006.197.07:52:21.97#ibcon#end of sib2, iclass 32, count 2 2006.197.07:52:21.97#ibcon#*mode == 0, iclass 32, count 2 2006.197.07:52:21.97#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.197.07:52:21.97#ibcon#[27=AT06-04\r\n] 2006.197.07:52:21.97#ibcon#*before write, iclass 32, count 2 2006.197.07:52:21.97#ibcon#enter sib2, iclass 32, count 2 2006.197.07:52:21.97#ibcon#flushed, iclass 32, count 2 2006.197.07:52:21.97#ibcon#about to write, iclass 32, count 2 2006.197.07:52:21.97#ibcon#wrote, iclass 32, count 2 2006.197.07:52:21.97#ibcon#about to read 3, iclass 32, count 2 2006.197.07:52:22.00#ibcon#read 3, iclass 32, count 2 2006.197.07:52:22.00#ibcon#about to read 4, iclass 32, count 2 2006.197.07:52:22.00#ibcon#read 4, iclass 32, count 2 2006.197.07:52:22.00#ibcon#about to read 5, iclass 32, count 2 2006.197.07:52:22.00#ibcon#read 5, iclass 32, count 2 2006.197.07:52:22.00#ibcon#about to read 6, iclass 32, count 2 2006.197.07:52:22.00#ibcon#read 6, iclass 32, count 2 2006.197.07:52:22.00#ibcon#end of sib2, iclass 32, count 2 2006.197.07:52:22.00#ibcon#*after write, iclass 32, count 2 2006.197.07:52:22.00#ibcon#*before return 0, iclass 32, count 2 2006.197.07:52:22.00#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.197.07:52:22.00#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.197.07:52:22.00#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.197.07:52:22.00#ibcon#ireg 7 cls_cnt 0 2006.197.07:52:22.00#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.197.07:52:22.12#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.197.07:52:22.12#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.197.07:52:22.12#ibcon#enter wrdev, iclass 32, count 0 2006.197.07:52:22.12#ibcon#first serial, iclass 32, count 0 2006.197.07:52:22.12#ibcon#enter sib2, iclass 32, count 0 2006.197.07:52:22.12#ibcon#flushed, iclass 32, count 0 2006.197.07:52:22.12#ibcon#about to write, iclass 32, count 0 2006.197.07:52:22.12#ibcon#wrote, iclass 32, count 0 2006.197.07:52:22.12#ibcon#about to read 3, iclass 32, count 0 2006.197.07:52:22.14#ibcon#read 3, iclass 32, count 0 2006.197.07:52:22.14#ibcon#about to read 4, iclass 32, count 0 2006.197.07:52:22.14#ibcon#read 4, iclass 32, count 0 2006.197.07:52:22.14#ibcon#about to read 5, iclass 32, count 0 2006.197.07:52:22.14#ibcon#read 5, iclass 32, count 0 2006.197.07:52:22.14#ibcon#about to read 6, iclass 32, count 0 2006.197.07:52:22.14#ibcon#read 6, iclass 32, count 0 2006.197.07:52:22.14#ibcon#end of sib2, iclass 32, count 0 2006.197.07:52:22.14#ibcon#*mode == 0, iclass 32, count 0 2006.197.07:52:22.14#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.197.07:52:22.14#ibcon#[27=USB\r\n] 2006.197.07:52:22.14#ibcon#*before write, iclass 32, count 0 2006.197.07:52:22.14#ibcon#enter sib2, iclass 32, count 0 2006.197.07:52:22.14#ibcon#flushed, iclass 32, count 0 2006.197.07:52:22.14#ibcon#about to write, iclass 32, count 0 2006.197.07:52:22.14#ibcon#wrote, iclass 32, count 0 2006.197.07:52:22.14#ibcon#about to read 3, iclass 32, count 0 2006.197.07:52:22.17#ibcon#read 3, iclass 32, count 0 2006.197.07:52:22.17#ibcon#about to read 4, iclass 32, count 0 2006.197.07:52:22.17#ibcon#read 4, iclass 32, count 0 2006.197.07:52:22.17#ibcon#about to read 5, iclass 32, count 0 2006.197.07:52:22.17#ibcon#read 5, iclass 32, count 0 2006.197.07:52:22.17#ibcon#about to read 6, iclass 32, count 0 2006.197.07:52:22.17#ibcon#read 6, iclass 32, count 0 2006.197.07:52:22.17#ibcon#end of sib2, iclass 32, count 0 2006.197.07:52:22.17#ibcon#*after write, iclass 32, count 0 2006.197.07:52:22.17#ibcon#*before return 0, iclass 32, count 0 2006.197.07:52:22.17#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.197.07:52:22.17#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.197.07:52:22.17#ibcon#about to clear, iclass 32 cls_cnt 0 2006.197.07:52:22.17#ibcon#cleared, iclass 32 cls_cnt 0 2006.197.07:52:22.17$vc4f8/vabw=wide 2006.197.07:52:22.17#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.197.07:52:22.17#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.197.07:52:22.17#ibcon#ireg 8 cls_cnt 0 2006.197.07:52:22.17#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.197.07:52:22.17#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.197.07:52:22.17#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.197.07:52:22.17#ibcon#enter wrdev, iclass 34, count 0 2006.197.07:52:22.17#ibcon#first serial, iclass 34, count 0 2006.197.07:52:22.17#ibcon#enter sib2, iclass 34, count 0 2006.197.07:52:22.17#ibcon#flushed, iclass 34, count 0 2006.197.07:52:22.17#ibcon#about to write, iclass 34, count 0 2006.197.07:52:22.17#ibcon#wrote, iclass 34, count 0 2006.197.07:52:22.17#ibcon#about to read 3, iclass 34, count 0 2006.197.07:52:22.19#ibcon#read 3, iclass 34, count 0 2006.197.07:52:22.19#ibcon#about to read 4, iclass 34, count 0 2006.197.07:52:22.19#ibcon#read 4, iclass 34, count 0 2006.197.07:52:22.19#ibcon#about to read 5, iclass 34, count 0 2006.197.07:52:22.19#ibcon#read 5, iclass 34, count 0 2006.197.07:52:22.19#ibcon#about to read 6, iclass 34, count 0 2006.197.07:52:22.19#ibcon#read 6, iclass 34, count 0 2006.197.07:52:22.19#ibcon#end of sib2, iclass 34, count 0 2006.197.07:52:22.19#ibcon#*mode == 0, iclass 34, count 0 2006.197.07:52:22.19#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.197.07:52:22.19#ibcon#[25=BW32\r\n] 2006.197.07:52:22.19#ibcon#*before write, iclass 34, count 0 2006.197.07:52:22.19#ibcon#enter sib2, iclass 34, count 0 2006.197.07:52:22.19#ibcon#flushed, iclass 34, count 0 2006.197.07:52:22.19#ibcon#about to write, iclass 34, count 0 2006.197.07:52:22.19#ibcon#wrote, iclass 34, count 0 2006.197.07:52:22.19#ibcon#about to read 3, iclass 34, count 0 2006.197.07:52:22.22#ibcon#read 3, iclass 34, count 0 2006.197.07:52:22.22#ibcon#about to read 4, iclass 34, count 0 2006.197.07:52:22.22#ibcon#read 4, iclass 34, count 0 2006.197.07:52:22.22#ibcon#about to read 5, iclass 34, count 0 2006.197.07:52:22.22#ibcon#read 5, iclass 34, count 0 2006.197.07:52:22.22#ibcon#about to read 6, iclass 34, count 0 2006.197.07:52:22.22#ibcon#read 6, iclass 34, count 0 2006.197.07:52:22.22#ibcon#end of sib2, iclass 34, count 0 2006.197.07:52:22.22#ibcon#*after write, iclass 34, count 0 2006.197.07:52:22.22#ibcon#*before return 0, iclass 34, count 0 2006.197.07:52:22.22#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.197.07:52:22.22#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.197.07:52:22.22#ibcon#about to clear, iclass 34 cls_cnt 0 2006.197.07:52:22.22#ibcon#cleared, iclass 34 cls_cnt 0 2006.197.07:52:22.22$vc4f8/vbbw=wide 2006.197.07:52:22.22#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.197.07:52:22.22#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.197.07:52:22.22#ibcon#ireg 8 cls_cnt 0 2006.197.07:52:22.22#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.197.07:52:22.29#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.197.07:52:22.29#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.197.07:52:22.29#ibcon#enter wrdev, iclass 36, count 0 2006.197.07:52:22.29#ibcon#first serial, iclass 36, count 0 2006.197.07:52:22.29#ibcon#enter sib2, iclass 36, count 0 2006.197.07:52:22.29#ibcon#flushed, iclass 36, count 0 2006.197.07:52:22.29#ibcon#about to write, iclass 36, count 0 2006.197.07:52:22.29#ibcon#wrote, iclass 36, count 0 2006.197.07:52:22.29#ibcon#about to read 3, iclass 36, count 0 2006.197.07:52:22.31#ibcon#read 3, iclass 36, count 0 2006.197.07:52:22.31#ibcon#about to read 4, iclass 36, count 0 2006.197.07:52:22.31#ibcon#read 4, iclass 36, count 0 2006.197.07:52:22.31#ibcon#about to read 5, iclass 36, count 0 2006.197.07:52:22.31#ibcon#read 5, iclass 36, count 0 2006.197.07:52:22.31#ibcon#about to read 6, iclass 36, count 0 2006.197.07:52:22.31#ibcon#read 6, iclass 36, count 0 2006.197.07:52:22.31#ibcon#end of sib2, iclass 36, count 0 2006.197.07:52:22.31#ibcon#*mode == 0, iclass 36, count 0 2006.197.07:52:22.31#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.197.07:52:22.31#ibcon#[27=BW32\r\n] 2006.197.07:52:22.31#ibcon#*before write, iclass 36, count 0 2006.197.07:52:22.31#ibcon#enter sib2, iclass 36, count 0 2006.197.07:52:22.31#ibcon#flushed, iclass 36, count 0 2006.197.07:52:22.31#ibcon#about to write, iclass 36, count 0 2006.197.07:52:22.31#ibcon#wrote, iclass 36, count 0 2006.197.07:52:22.31#ibcon#about to read 3, iclass 36, count 0 2006.197.07:52:22.34#ibcon#read 3, iclass 36, count 0 2006.197.07:52:22.34#ibcon#about to read 4, iclass 36, count 0 2006.197.07:52:22.34#ibcon#read 4, iclass 36, count 0 2006.197.07:52:22.34#ibcon#about to read 5, iclass 36, count 0 2006.197.07:52:22.34#ibcon#read 5, iclass 36, count 0 2006.197.07:52:22.34#ibcon#about to read 6, iclass 36, count 0 2006.197.07:52:22.34#ibcon#read 6, iclass 36, count 0 2006.197.07:52:22.34#ibcon#end of sib2, iclass 36, count 0 2006.197.07:52:22.34#ibcon#*after write, iclass 36, count 0 2006.197.07:52:22.34#ibcon#*before return 0, iclass 36, count 0 2006.197.07:52:22.34#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.197.07:52:22.34#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.197.07:52:22.34#ibcon#about to clear, iclass 36 cls_cnt 0 2006.197.07:52:22.34#ibcon#cleared, iclass 36 cls_cnt 0 2006.197.07:52:22.34$4f8m12a/ifd4f 2006.197.07:52:22.34$ifd4f/lo= 2006.197.07:52:22.34$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.197.07:52:22.34$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.197.07:52:22.34$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.197.07:52:22.34$ifd4f/patch= 2006.197.07:52:22.34$ifd4f/patch=lo1,a1,a2,a3,a4 2006.197.07:52:22.34$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.197.07:52:22.34$ifd4f/patch=lo3,a5,a6,a7,a8 2006.197.07:52:22.34$4f8m12a/"form=m,16.000,1:2 2006.197.07:52:22.34$4f8m12a/"tpicd 2006.197.07:52:22.34$4f8m12a/echo=off 2006.197.07:52:22.34$4f8m12a/xlog=off 2006.197.07:52:22.34:!2006.197.07:53:00 2006.197.07:52:41.14#trakl#Source acquired 2006.197.07:52:41.14#flagr#flagr/antenna,acquired 2006.197.07:53:00.00:preob 2006.197.07:53:00.14/onsource/TRACKING 2006.197.07:53:00.14:!2006.197.07:53:10 2006.197.07:53:10.00:data_valid=on 2006.197.07:53:10.00:midob 2006.197.07:53:11.14/onsource/TRACKING 2006.197.07:53:11.14/wx/25.77,1003.1,97 2006.197.07:53:11.30/cable/+6.3702E-03 2006.197.07:53:12.39/va/01,08,usb,yes,33,35 2006.197.07:53:12.39/va/02,07,usb,yes,33,35 2006.197.07:53:12.39/va/03,06,usb,yes,35,35 2006.197.07:53:12.39/va/04,07,usb,yes,34,37 2006.197.07:53:12.39/va/05,07,usb,yes,39,41 2006.197.07:53:12.39/va/06,06,usb,yes,38,38 2006.197.07:53:12.39/va/07,06,usb,yes,39,38 2006.197.07:53:12.39/va/08,07,usb,yes,37,36 2006.197.07:53:12.62/valo/01,532.99,yes,locked 2006.197.07:53:12.62/valo/02,572.99,yes,locked 2006.197.07:53:12.62/valo/03,672.99,yes,locked 2006.197.07:53:12.62/valo/04,832.99,yes,locked 2006.197.07:53:12.62/valo/05,652.99,yes,locked 2006.197.07:53:12.62/valo/06,772.99,yes,locked 2006.197.07:53:12.62/valo/07,832.99,yes,locked 2006.197.07:53:12.62/valo/08,852.99,yes,locked 2006.197.07:53:13.71/vb/01,04,usb,yes,31,30 2006.197.07:53:13.71/vb/02,04,usb,yes,33,34 2006.197.07:53:13.71/vb/03,04,usb,yes,29,33 2006.197.07:53:13.71/vb/04,04,usb,yes,31,31 2006.197.07:53:13.71/vb/05,04,usb,yes,29,33 2006.197.07:53:13.71/vb/06,04,usb,yes,30,33 2006.197.07:53:13.71/vb/07,04,usb,yes,32,33 2006.197.07:53:13.71/vb/08,04,usb,yes,29,33 2006.197.07:53:13.94/vblo/01,632.99,yes,locked 2006.197.07:53:13.94/vblo/02,640.99,yes,locked 2006.197.07:53:13.94/vblo/03,656.99,yes,locked 2006.197.07:53:13.94/vblo/04,712.99,yes,locked 2006.197.07:53:13.94/vblo/05,744.99,yes,locked 2006.197.07:53:13.94/vblo/06,752.99,yes,locked 2006.197.07:53:13.94/vblo/07,734.99,yes,locked 2006.197.07:53:13.94/vblo/08,744.99,yes,locked 2006.197.07:53:14.09/vabw/8 2006.197.07:53:14.24/vbbw/8 2006.197.07:53:14.36/xfe/off,on,15.2 2006.197.07:53:14.75/ifatt/23,28,28,28 2006.197.07:53:15.10/fmout-gps/S +2.99E-07 2006.197.07:53:15.14:!2006.197.07:54:10 2006.197.07:54:10.00:data_valid=off 2006.197.07:54:10.00:postob 2006.197.07:54:10.13/cable/+6.3706E-03 2006.197.07:54:10.13/wx/25.78,1003.1,97 2006.197.07:54:11.11/fmout-gps/S +2.99E-07 2006.197.07:54:11.11:scan_name=197-0755,k06197,60 2006.197.07:54:11.11:source=0602+673,060752.67,672055.4,2000.0,ccw 2006.197.07:54:11.14#flagr#flagr/antenna,new-source 2006.197.07:54:12.14:checkk5 2006.197.07:54:12.48/chk_autoobs//k5ts1/ autoobs is running! 2006.197.07:54:12.82/chk_autoobs//k5ts2/ autoobs is running! 2006.197.07:54:13.20/chk_autoobs//k5ts3/ autoobs is running! 2006.197.07:54:13.55/chk_autoobs//k5ts4/ autoobs is running! 2006.197.07:54:13.88/chk_obsdata//k5ts1/T1970753??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.07:54:14.22/chk_obsdata//k5ts2/T1970753??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.07:54:14.55/chk_obsdata//k5ts3/T1970753??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.07:54:14.88/chk_obsdata//k5ts4/T1970753??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.07:54:15.54/k5log//k5ts1_log_newline 2006.197.07:54:16.19/k5log//k5ts2_log_newline 2006.197.07:54:16.85/k5log//k5ts3_log_newline 2006.197.07:54:17.51/k5log//k5ts4_log_newline 2006.197.07:54:17.54/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.197.07:54:17.54:4f8m12a=2 2006.197.07:54:17.54$4f8m12a/echo=on 2006.197.07:54:17.54$4f8m12a/pcalon 2006.197.07:54:17.54$pcalon/"no phase cal control is implemented here 2006.197.07:54:17.54$4f8m12a/"tpicd=stop 2006.197.07:54:17.54$4f8m12a/vc4f8 2006.197.07:54:17.54$vc4f8/valo=1,532.99 2006.197.07:54:17.54#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.197.07:54:17.54#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.197.07:54:17.54#ibcon#ireg 17 cls_cnt 0 2006.197.07:54:17.54#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.197.07:54:17.54#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.197.07:54:17.54#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.197.07:54:17.54#ibcon#enter wrdev, iclass 11, count 0 2006.197.07:54:17.54#ibcon#first serial, iclass 11, count 0 2006.197.07:54:17.54#ibcon#enter sib2, iclass 11, count 0 2006.197.07:54:17.54#ibcon#flushed, iclass 11, count 0 2006.197.07:54:17.54#ibcon#about to write, iclass 11, count 0 2006.197.07:54:17.54#ibcon#wrote, iclass 11, count 0 2006.197.07:54:17.54#ibcon#about to read 3, iclass 11, count 0 2006.197.07:54:17.56#ibcon#read 3, iclass 11, count 0 2006.197.07:54:17.56#ibcon#about to read 4, iclass 11, count 0 2006.197.07:54:17.56#ibcon#read 4, iclass 11, count 0 2006.197.07:54:17.56#ibcon#about to read 5, iclass 11, count 0 2006.197.07:54:17.56#ibcon#read 5, iclass 11, count 0 2006.197.07:54:17.56#ibcon#about to read 6, iclass 11, count 0 2006.197.07:54:17.56#ibcon#read 6, iclass 11, count 0 2006.197.07:54:17.56#ibcon#end of sib2, iclass 11, count 0 2006.197.07:54:17.56#ibcon#*mode == 0, iclass 11, count 0 2006.197.07:54:17.56#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.197.07:54:17.56#ibcon#[26=FRQ=01,532.99\r\n] 2006.197.07:54:17.56#ibcon#*before write, iclass 11, count 0 2006.197.07:54:17.56#ibcon#enter sib2, iclass 11, count 0 2006.197.07:54:17.56#ibcon#flushed, iclass 11, count 0 2006.197.07:54:17.56#ibcon#about to write, iclass 11, count 0 2006.197.07:54:17.56#ibcon#wrote, iclass 11, count 0 2006.197.07:54:17.56#ibcon#about to read 3, iclass 11, count 0 2006.197.07:54:17.61#ibcon#read 3, iclass 11, count 0 2006.197.07:54:17.61#ibcon#about to read 4, iclass 11, count 0 2006.197.07:54:17.61#ibcon#read 4, iclass 11, count 0 2006.197.07:54:17.61#ibcon#about to read 5, iclass 11, count 0 2006.197.07:54:17.61#ibcon#read 5, iclass 11, count 0 2006.197.07:54:17.61#ibcon#about to read 6, iclass 11, count 0 2006.197.07:54:17.61#ibcon#read 6, iclass 11, count 0 2006.197.07:54:17.61#ibcon#end of sib2, iclass 11, count 0 2006.197.07:54:17.61#ibcon#*after write, iclass 11, count 0 2006.197.07:54:17.61#ibcon#*before return 0, iclass 11, count 0 2006.197.07:54:17.61#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.197.07:54:17.61#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.197.07:54:17.61#ibcon#about to clear, iclass 11 cls_cnt 0 2006.197.07:54:17.61#ibcon#cleared, iclass 11 cls_cnt 0 2006.197.07:54:17.61$vc4f8/va=1,8 2006.197.07:54:17.61#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.197.07:54:17.61#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.197.07:54:17.61#ibcon#ireg 11 cls_cnt 2 2006.197.07:54:17.61#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.197.07:54:17.61#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.197.07:54:17.61#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.197.07:54:17.61#ibcon#enter wrdev, iclass 13, count 2 2006.197.07:54:17.61#ibcon#first serial, iclass 13, count 2 2006.197.07:54:17.61#ibcon#enter sib2, iclass 13, count 2 2006.197.07:54:17.61#ibcon#flushed, iclass 13, count 2 2006.197.07:54:17.61#ibcon#about to write, iclass 13, count 2 2006.197.07:54:17.61#ibcon#wrote, iclass 13, count 2 2006.197.07:54:17.61#ibcon#about to read 3, iclass 13, count 2 2006.197.07:54:17.63#ibcon#read 3, iclass 13, count 2 2006.197.07:54:17.63#ibcon#about to read 4, iclass 13, count 2 2006.197.07:54:17.63#ibcon#read 4, iclass 13, count 2 2006.197.07:54:17.63#ibcon#about to read 5, iclass 13, count 2 2006.197.07:54:17.63#ibcon#read 5, iclass 13, count 2 2006.197.07:54:17.63#ibcon#about to read 6, iclass 13, count 2 2006.197.07:54:17.63#ibcon#read 6, iclass 13, count 2 2006.197.07:54:17.63#ibcon#end of sib2, iclass 13, count 2 2006.197.07:54:17.63#ibcon#*mode == 0, iclass 13, count 2 2006.197.07:54:17.63#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.197.07:54:17.63#ibcon#[25=AT01-08\r\n] 2006.197.07:54:17.63#ibcon#*before write, iclass 13, count 2 2006.197.07:54:17.63#ibcon#enter sib2, iclass 13, count 2 2006.197.07:54:17.63#ibcon#flushed, iclass 13, count 2 2006.197.07:54:17.63#ibcon#about to write, iclass 13, count 2 2006.197.07:54:17.63#ibcon#wrote, iclass 13, count 2 2006.197.07:54:17.63#ibcon#about to read 3, iclass 13, count 2 2006.197.07:54:17.66#ibcon#read 3, iclass 13, count 2 2006.197.07:54:17.66#ibcon#about to read 4, iclass 13, count 2 2006.197.07:54:17.66#ibcon#read 4, iclass 13, count 2 2006.197.07:54:17.66#ibcon#about to read 5, iclass 13, count 2 2006.197.07:54:17.66#ibcon#read 5, iclass 13, count 2 2006.197.07:54:17.66#ibcon#about to read 6, iclass 13, count 2 2006.197.07:54:17.66#ibcon#read 6, iclass 13, count 2 2006.197.07:54:17.66#ibcon#end of sib2, iclass 13, count 2 2006.197.07:54:17.66#ibcon#*after write, iclass 13, count 2 2006.197.07:54:17.66#ibcon#*before return 0, iclass 13, count 2 2006.197.07:54:17.66#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.197.07:54:17.66#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.197.07:54:17.66#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.197.07:54:17.66#ibcon#ireg 7 cls_cnt 0 2006.197.07:54:17.66#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.197.07:54:17.78#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.197.07:54:17.78#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.197.07:54:17.78#ibcon#enter wrdev, iclass 13, count 0 2006.197.07:54:17.78#ibcon#first serial, iclass 13, count 0 2006.197.07:54:17.78#ibcon#enter sib2, iclass 13, count 0 2006.197.07:54:17.78#ibcon#flushed, iclass 13, count 0 2006.197.07:54:17.78#ibcon#about to write, iclass 13, count 0 2006.197.07:54:17.78#ibcon#wrote, iclass 13, count 0 2006.197.07:54:17.78#ibcon#about to read 3, iclass 13, count 0 2006.197.07:54:17.80#ibcon#read 3, iclass 13, count 0 2006.197.07:54:17.80#ibcon#about to read 4, iclass 13, count 0 2006.197.07:54:17.80#ibcon#read 4, iclass 13, count 0 2006.197.07:54:17.80#ibcon#about to read 5, iclass 13, count 0 2006.197.07:54:17.80#ibcon#read 5, iclass 13, count 0 2006.197.07:54:17.80#ibcon#about to read 6, iclass 13, count 0 2006.197.07:54:17.80#ibcon#read 6, iclass 13, count 0 2006.197.07:54:17.80#ibcon#end of sib2, iclass 13, count 0 2006.197.07:54:17.80#ibcon#*mode == 0, iclass 13, count 0 2006.197.07:54:17.80#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.197.07:54:17.80#ibcon#[25=USB\r\n] 2006.197.07:54:17.80#ibcon#*before write, iclass 13, count 0 2006.197.07:54:17.80#ibcon#enter sib2, iclass 13, count 0 2006.197.07:54:17.80#ibcon#flushed, iclass 13, count 0 2006.197.07:54:17.80#ibcon#about to write, iclass 13, count 0 2006.197.07:54:17.80#ibcon#wrote, iclass 13, count 0 2006.197.07:54:17.80#ibcon#about to read 3, iclass 13, count 0 2006.197.07:54:17.83#ibcon#read 3, iclass 13, count 0 2006.197.07:54:17.83#ibcon#about to read 4, iclass 13, count 0 2006.197.07:54:17.83#ibcon#read 4, iclass 13, count 0 2006.197.07:54:17.83#ibcon#about to read 5, iclass 13, count 0 2006.197.07:54:17.83#ibcon#read 5, iclass 13, count 0 2006.197.07:54:17.83#ibcon#about to read 6, iclass 13, count 0 2006.197.07:54:17.83#ibcon#read 6, iclass 13, count 0 2006.197.07:54:17.83#ibcon#end of sib2, iclass 13, count 0 2006.197.07:54:17.83#ibcon#*after write, iclass 13, count 0 2006.197.07:54:17.83#ibcon#*before return 0, iclass 13, count 0 2006.197.07:54:17.83#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.197.07:54:17.83#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.197.07:54:17.83#ibcon#about to clear, iclass 13 cls_cnt 0 2006.197.07:54:17.83#ibcon#cleared, iclass 13 cls_cnt 0 2006.197.07:54:17.83$vc4f8/valo=2,572.99 2006.197.07:54:17.83#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.197.07:54:17.83#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.197.07:54:17.83#ibcon#ireg 17 cls_cnt 0 2006.197.07:54:17.83#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.197.07:54:17.83#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.197.07:54:17.83#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.197.07:54:17.83#ibcon#enter wrdev, iclass 15, count 0 2006.197.07:54:17.83#ibcon#first serial, iclass 15, count 0 2006.197.07:54:17.83#ibcon#enter sib2, iclass 15, count 0 2006.197.07:54:17.83#ibcon#flushed, iclass 15, count 0 2006.197.07:54:17.83#ibcon#about to write, iclass 15, count 0 2006.197.07:54:17.83#ibcon#wrote, iclass 15, count 0 2006.197.07:54:17.83#ibcon#about to read 3, iclass 15, count 0 2006.197.07:54:17.85#ibcon#read 3, iclass 15, count 0 2006.197.07:54:17.85#ibcon#about to read 4, iclass 15, count 0 2006.197.07:54:17.85#ibcon#read 4, iclass 15, count 0 2006.197.07:54:17.85#ibcon#about to read 5, iclass 15, count 0 2006.197.07:54:17.85#ibcon#read 5, iclass 15, count 0 2006.197.07:54:17.85#ibcon#about to read 6, iclass 15, count 0 2006.197.07:54:17.85#ibcon#read 6, iclass 15, count 0 2006.197.07:54:17.85#ibcon#end of sib2, iclass 15, count 0 2006.197.07:54:17.85#ibcon#*mode == 0, iclass 15, count 0 2006.197.07:54:17.85#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.197.07:54:17.85#ibcon#[26=FRQ=02,572.99\r\n] 2006.197.07:54:17.85#ibcon#*before write, iclass 15, count 0 2006.197.07:54:17.85#ibcon#enter sib2, iclass 15, count 0 2006.197.07:54:17.85#ibcon#flushed, iclass 15, count 0 2006.197.07:54:17.85#ibcon#about to write, iclass 15, count 0 2006.197.07:54:17.85#ibcon#wrote, iclass 15, count 0 2006.197.07:54:17.85#ibcon#about to read 3, iclass 15, count 0 2006.197.07:54:17.89#ibcon#read 3, iclass 15, count 0 2006.197.07:54:17.89#ibcon#about to read 4, iclass 15, count 0 2006.197.07:54:17.89#ibcon#read 4, iclass 15, count 0 2006.197.07:54:17.89#ibcon#about to read 5, iclass 15, count 0 2006.197.07:54:17.89#ibcon#read 5, iclass 15, count 0 2006.197.07:54:17.89#ibcon#about to read 6, iclass 15, count 0 2006.197.07:54:17.89#ibcon#read 6, iclass 15, count 0 2006.197.07:54:17.89#ibcon#end of sib2, iclass 15, count 0 2006.197.07:54:17.89#ibcon#*after write, iclass 15, count 0 2006.197.07:54:17.89#ibcon#*before return 0, iclass 15, count 0 2006.197.07:54:17.89#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.197.07:54:17.89#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.197.07:54:17.89#ibcon#about to clear, iclass 15 cls_cnt 0 2006.197.07:54:17.89#ibcon#cleared, iclass 15 cls_cnt 0 2006.197.07:54:17.89$vc4f8/va=2,7 2006.197.07:54:17.89#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.197.07:54:17.89#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.197.07:54:17.89#ibcon#ireg 11 cls_cnt 2 2006.197.07:54:17.89#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.197.07:54:17.95#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.197.07:54:17.95#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.197.07:54:17.95#ibcon#enter wrdev, iclass 17, count 2 2006.197.07:54:17.95#ibcon#first serial, iclass 17, count 2 2006.197.07:54:17.95#ibcon#enter sib2, iclass 17, count 2 2006.197.07:54:17.95#ibcon#flushed, iclass 17, count 2 2006.197.07:54:17.95#ibcon#about to write, iclass 17, count 2 2006.197.07:54:17.95#ibcon#wrote, iclass 17, count 2 2006.197.07:54:17.95#ibcon#about to read 3, iclass 17, count 2 2006.197.07:54:17.97#ibcon#read 3, iclass 17, count 2 2006.197.07:54:17.97#ibcon#about to read 4, iclass 17, count 2 2006.197.07:54:17.97#ibcon#read 4, iclass 17, count 2 2006.197.07:54:17.97#ibcon#about to read 5, iclass 17, count 2 2006.197.07:54:17.97#ibcon#read 5, iclass 17, count 2 2006.197.07:54:17.97#ibcon#about to read 6, iclass 17, count 2 2006.197.07:54:17.97#ibcon#read 6, iclass 17, count 2 2006.197.07:54:17.97#ibcon#end of sib2, iclass 17, count 2 2006.197.07:54:17.97#ibcon#*mode == 0, iclass 17, count 2 2006.197.07:54:17.97#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.197.07:54:17.97#ibcon#[25=AT02-07\r\n] 2006.197.07:54:17.97#ibcon#*before write, iclass 17, count 2 2006.197.07:54:17.97#ibcon#enter sib2, iclass 17, count 2 2006.197.07:54:17.97#ibcon#flushed, iclass 17, count 2 2006.197.07:54:17.97#ibcon#about to write, iclass 17, count 2 2006.197.07:54:17.97#ibcon#wrote, iclass 17, count 2 2006.197.07:54:17.97#ibcon#about to read 3, iclass 17, count 2 2006.197.07:54:18.00#ibcon#read 3, iclass 17, count 2 2006.197.07:54:18.00#ibcon#about to read 4, iclass 17, count 2 2006.197.07:54:18.00#ibcon#read 4, iclass 17, count 2 2006.197.07:54:18.00#ibcon#about to read 5, iclass 17, count 2 2006.197.07:54:18.00#ibcon#read 5, iclass 17, count 2 2006.197.07:54:18.00#ibcon#about to read 6, iclass 17, count 2 2006.197.07:54:18.00#ibcon#read 6, iclass 17, count 2 2006.197.07:54:18.00#ibcon#end of sib2, iclass 17, count 2 2006.197.07:54:18.00#ibcon#*after write, iclass 17, count 2 2006.197.07:54:18.00#ibcon#*before return 0, iclass 17, count 2 2006.197.07:54:18.00#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.197.07:54:18.00#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.197.07:54:18.00#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.197.07:54:18.00#ibcon#ireg 7 cls_cnt 0 2006.197.07:54:18.00#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.197.07:54:18.12#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.197.07:54:18.12#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.197.07:54:18.12#ibcon#enter wrdev, iclass 17, count 0 2006.197.07:54:18.12#ibcon#first serial, iclass 17, count 0 2006.197.07:54:18.12#ibcon#enter sib2, iclass 17, count 0 2006.197.07:54:18.12#ibcon#flushed, iclass 17, count 0 2006.197.07:54:18.12#ibcon#about to write, iclass 17, count 0 2006.197.07:54:18.12#ibcon#wrote, iclass 17, count 0 2006.197.07:54:18.12#ibcon#about to read 3, iclass 17, count 0 2006.197.07:54:18.14#ibcon#read 3, iclass 17, count 0 2006.197.07:54:18.14#ibcon#about to read 4, iclass 17, count 0 2006.197.07:54:18.14#ibcon#read 4, iclass 17, count 0 2006.197.07:54:18.14#ibcon#about to read 5, iclass 17, count 0 2006.197.07:54:18.14#ibcon#read 5, iclass 17, count 0 2006.197.07:54:18.14#ibcon#about to read 6, iclass 17, count 0 2006.197.07:54:18.14#ibcon#read 6, iclass 17, count 0 2006.197.07:54:18.14#ibcon#end of sib2, iclass 17, count 0 2006.197.07:54:18.14#ibcon#*mode == 0, iclass 17, count 0 2006.197.07:54:18.14#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.197.07:54:18.14#ibcon#[25=USB\r\n] 2006.197.07:54:18.14#ibcon#*before write, iclass 17, count 0 2006.197.07:54:18.14#ibcon#enter sib2, iclass 17, count 0 2006.197.07:54:18.14#ibcon#flushed, iclass 17, count 0 2006.197.07:54:18.14#ibcon#about to write, iclass 17, count 0 2006.197.07:54:18.14#ibcon#wrote, iclass 17, count 0 2006.197.07:54:18.14#ibcon#about to read 3, iclass 17, count 0 2006.197.07:54:18.17#ibcon#read 3, iclass 17, count 0 2006.197.07:54:18.17#ibcon#about to read 4, iclass 17, count 0 2006.197.07:54:18.17#ibcon#read 4, iclass 17, count 0 2006.197.07:54:18.17#ibcon#about to read 5, iclass 17, count 0 2006.197.07:54:18.17#ibcon#read 5, iclass 17, count 0 2006.197.07:54:18.17#ibcon#about to read 6, iclass 17, count 0 2006.197.07:54:18.17#ibcon#read 6, iclass 17, count 0 2006.197.07:54:18.17#ibcon#end of sib2, iclass 17, count 0 2006.197.07:54:18.17#ibcon#*after write, iclass 17, count 0 2006.197.07:54:18.17#ibcon#*before return 0, iclass 17, count 0 2006.197.07:54:18.17#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.197.07:54:18.17#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.197.07:54:18.17#ibcon#about to clear, iclass 17 cls_cnt 0 2006.197.07:54:18.17#ibcon#cleared, iclass 17 cls_cnt 0 2006.197.07:54:18.17$vc4f8/valo=3,672.99 2006.197.07:54:18.17#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.197.07:54:18.17#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.197.07:54:18.17#ibcon#ireg 17 cls_cnt 0 2006.197.07:54:18.17#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.197.07:54:18.17#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.197.07:54:18.17#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.197.07:54:18.17#ibcon#enter wrdev, iclass 19, count 0 2006.197.07:54:18.17#ibcon#first serial, iclass 19, count 0 2006.197.07:54:18.17#ibcon#enter sib2, iclass 19, count 0 2006.197.07:54:18.17#ibcon#flushed, iclass 19, count 0 2006.197.07:54:18.17#ibcon#about to write, iclass 19, count 0 2006.197.07:54:18.17#ibcon#wrote, iclass 19, count 0 2006.197.07:54:18.17#ibcon#about to read 3, iclass 19, count 0 2006.197.07:54:18.19#ibcon#read 3, iclass 19, count 0 2006.197.07:54:18.19#ibcon#about to read 4, iclass 19, count 0 2006.197.07:54:18.19#ibcon#read 4, iclass 19, count 0 2006.197.07:54:18.19#ibcon#about to read 5, iclass 19, count 0 2006.197.07:54:18.19#ibcon#read 5, iclass 19, count 0 2006.197.07:54:18.19#ibcon#about to read 6, iclass 19, count 0 2006.197.07:54:18.19#ibcon#read 6, iclass 19, count 0 2006.197.07:54:18.19#ibcon#end of sib2, iclass 19, count 0 2006.197.07:54:18.19#ibcon#*mode == 0, iclass 19, count 0 2006.197.07:54:18.19#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.197.07:54:18.19#ibcon#[26=FRQ=03,672.99\r\n] 2006.197.07:54:18.19#ibcon#*before write, iclass 19, count 0 2006.197.07:54:18.19#ibcon#enter sib2, iclass 19, count 0 2006.197.07:54:18.19#ibcon#flushed, iclass 19, count 0 2006.197.07:54:18.19#ibcon#about to write, iclass 19, count 0 2006.197.07:54:18.19#ibcon#wrote, iclass 19, count 0 2006.197.07:54:18.19#ibcon#about to read 3, iclass 19, count 0 2006.197.07:54:18.23#ibcon#read 3, iclass 19, count 0 2006.197.07:54:18.23#ibcon#about to read 4, iclass 19, count 0 2006.197.07:54:18.23#ibcon#read 4, iclass 19, count 0 2006.197.07:54:18.23#ibcon#about to read 5, iclass 19, count 0 2006.197.07:54:18.23#ibcon#read 5, iclass 19, count 0 2006.197.07:54:18.23#ibcon#about to read 6, iclass 19, count 0 2006.197.07:54:18.23#ibcon#read 6, iclass 19, count 0 2006.197.07:54:18.23#ibcon#end of sib2, iclass 19, count 0 2006.197.07:54:18.23#ibcon#*after write, iclass 19, count 0 2006.197.07:54:18.23#ibcon#*before return 0, iclass 19, count 0 2006.197.07:54:18.23#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.197.07:54:18.23#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.197.07:54:18.23#ibcon#about to clear, iclass 19 cls_cnt 0 2006.197.07:54:18.23#ibcon#cleared, iclass 19 cls_cnt 0 2006.197.07:54:18.23$vc4f8/va=3,6 2006.197.07:54:18.23#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.197.07:54:18.23#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.197.07:54:18.23#ibcon#ireg 11 cls_cnt 2 2006.197.07:54:18.23#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.197.07:54:18.29#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.197.07:54:18.29#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.197.07:54:18.29#ibcon#enter wrdev, iclass 21, count 2 2006.197.07:54:18.29#ibcon#first serial, iclass 21, count 2 2006.197.07:54:18.29#ibcon#enter sib2, iclass 21, count 2 2006.197.07:54:18.29#ibcon#flushed, iclass 21, count 2 2006.197.07:54:18.29#ibcon#about to write, iclass 21, count 2 2006.197.07:54:18.29#ibcon#wrote, iclass 21, count 2 2006.197.07:54:18.29#ibcon#about to read 3, iclass 21, count 2 2006.197.07:54:18.31#ibcon#read 3, iclass 21, count 2 2006.197.07:54:18.31#ibcon#about to read 4, iclass 21, count 2 2006.197.07:54:18.31#ibcon#read 4, iclass 21, count 2 2006.197.07:54:18.31#ibcon#about to read 5, iclass 21, count 2 2006.197.07:54:18.31#ibcon#read 5, iclass 21, count 2 2006.197.07:54:18.31#ibcon#about to read 6, iclass 21, count 2 2006.197.07:54:18.31#ibcon#read 6, iclass 21, count 2 2006.197.07:54:18.31#ibcon#end of sib2, iclass 21, count 2 2006.197.07:54:18.31#ibcon#*mode == 0, iclass 21, count 2 2006.197.07:54:18.31#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.197.07:54:18.31#ibcon#[25=AT03-06\r\n] 2006.197.07:54:18.31#ibcon#*before write, iclass 21, count 2 2006.197.07:54:18.31#ibcon#enter sib2, iclass 21, count 2 2006.197.07:54:18.31#ibcon#flushed, iclass 21, count 2 2006.197.07:54:18.31#ibcon#about to write, iclass 21, count 2 2006.197.07:54:18.31#ibcon#wrote, iclass 21, count 2 2006.197.07:54:18.31#ibcon#about to read 3, iclass 21, count 2 2006.197.07:54:18.34#ibcon#read 3, iclass 21, count 2 2006.197.07:54:18.34#ibcon#about to read 4, iclass 21, count 2 2006.197.07:54:18.34#ibcon#read 4, iclass 21, count 2 2006.197.07:54:18.34#ibcon#about to read 5, iclass 21, count 2 2006.197.07:54:18.34#ibcon#read 5, iclass 21, count 2 2006.197.07:54:18.34#ibcon#about to read 6, iclass 21, count 2 2006.197.07:54:18.34#ibcon#read 6, iclass 21, count 2 2006.197.07:54:18.34#ibcon#end of sib2, iclass 21, count 2 2006.197.07:54:18.34#ibcon#*after write, iclass 21, count 2 2006.197.07:54:18.34#ibcon#*before return 0, iclass 21, count 2 2006.197.07:54:18.34#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.197.07:54:18.34#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.197.07:54:18.34#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.197.07:54:18.34#ibcon#ireg 7 cls_cnt 0 2006.197.07:54:18.34#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.197.07:54:18.46#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.197.07:54:18.46#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.197.07:54:18.46#ibcon#enter wrdev, iclass 21, count 0 2006.197.07:54:18.46#ibcon#first serial, iclass 21, count 0 2006.197.07:54:18.46#ibcon#enter sib2, iclass 21, count 0 2006.197.07:54:18.46#ibcon#flushed, iclass 21, count 0 2006.197.07:54:18.46#ibcon#about to write, iclass 21, count 0 2006.197.07:54:18.46#ibcon#wrote, iclass 21, count 0 2006.197.07:54:18.46#ibcon#about to read 3, iclass 21, count 0 2006.197.07:54:18.48#ibcon#read 3, iclass 21, count 0 2006.197.07:54:18.48#ibcon#about to read 4, iclass 21, count 0 2006.197.07:54:18.48#ibcon#read 4, iclass 21, count 0 2006.197.07:54:18.48#ibcon#about to read 5, iclass 21, count 0 2006.197.07:54:18.48#ibcon#read 5, iclass 21, count 0 2006.197.07:54:18.48#ibcon#about to read 6, iclass 21, count 0 2006.197.07:54:18.48#ibcon#read 6, iclass 21, count 0 2006.197.07:54:18.48#ibcon#end of sib2, iclass 21, count 0 2006.197.07:54:18.48#ibcon#*mode == 0, iclass 21, count 0 2006.197.07:54:18.48#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.197.07:54:18.48#ibcon#[25=USB\r\n] 2006.197.07:54:18.48#ibcon#*before write, iclass 21, count 0 2006.197.07:54:18.48#ibcon#enter sib2, iclass 21, count 0 2006.197.07:54:18.48#ibcon#flushed, iclass 21, count 0 2006.197.07:54:18.48#ibcon#about to write, iclass 21, count 0 2006.197.07:54:18.48#ibcon#wrote, iclass 21, count 0 2006.197.07:54:18.48#ibcon#about to read 3, iclass 21, count 0 2006.197.07:54:18.51#ibcon#read 3, iclass 21, count 0 2006.197.07:54:18.51#ibcon#about to read 4, iclass 21, count 0 2006.197.07:54:18.51#ibcon#read 4, iclass 21, count 0 2006.197.07:54:18.51#ibcon#about to read 5, iclass 21, count 0 2006.197.07:54:18.51#ibcon#read 5, iclass 21, count 0 2006.197.07:54:18.51#ibcon#about to read 6, iclass 21, count 0 2006.197.07:54:18.51#ibcon#read 6, iclass 21, count 0 2006.197.07:54:18.51#ibcon#end of sib2, iclass 21, count 0 2006.197.07:54:18.51#ibcon#*after write, iclass 21, count 0 2006.197.07:54:18.51#ibcon#*before return 0, iclass 21, count 0 2006.197.07:54:18.51#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.197.07:54:18.51#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.197.07:54:18.51#ibcon#about to clear, iclass 21 cls_cnt 0 2006.197.07:54:18.51#ibcon#cleared, iclass 21 cls_cnt 0 2006.197.07:54:18.51$vc4f8/valo=4,832.99 2006.197.07:54:18.51#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.197.07:54:18.51#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.197.07:54:18.51#ibcon#ireg 17 cls_cnt 0 2006.197.07:54:18.51#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.197.07:54:18.51#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.197.07:54:18.51#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.197.07:54:18.51#ibcon#enter wrdev, iclass 23, count 0 2006.197.07:54:18.51#ibcon#first serial, iclass 23, count 0 2006.197.07:54:18.51#ibcon#enter sib2, iclass 23, count 0 2006.197.07:54:18.51#ibcon#flushed, iclass 23, count 0 2006.197.07:54:18.51#ibcon#about to write, iclass 23, count 0 2006.197.07:54:18.51#ibcon#wrote, iclass 23, count 0 2006.197.07:54:18.51#ibcon#about to read 3, iclass 23, count 0 2006.197.07:54:18.53#ibcon#read 3, iclass 23, count 0 2006.197.07:54:18.53#ibcon#about to read 4, iclass 23, count 0 2006.197.07:54:18.53#ibcon#read 4, iclass 23, count 0 2006.197.07:54:18.53#ibcon#about to read 5, iclass 23, count 0 2006.197.07:54:18.53#ibcon#read 5, iclass 23, count 0 2006.197.07:54:18.53#ibcon#about to read 6, iclass 23, count 0 2006.197.07:54:18.53#ibcon#read 6, iclass 23, count 0 2006.197.07:54:18.53#ibcon#end of sib2, iclass 23, count 0 2006.197.07:54:18.53#ibcon#*mode == 0, iclass 23, count 0 2006.197.07:54:18.53#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.197.07:54:18.53#ibcon#[26=FRQ=04,832.99\r\n] 2006.197.07:54:18.53#ibcon#*before write, iclass 23, count 0 2006.197.07:54:18.53#ibcon#enter sib2, iclass 23, count 0 2006.197.07:54:18.53#ibcon#flushed, iclass 23, count 0 2006.197.07:54:18.53#ibcon#about to write, iclass 23, count 0 2006.197.07:54:18.53#ibcon#wrote, iclass 23, count 0 2006.197.07:54:18.53#ibcon#about to read 3, iclass 23, count 0 2006.197.07:54:18.57#ibcon#read 3, iclass 23, count 0 2006.197.07:54:18.57#ibcon#about to read 4, iclass 23, count 0 2006.197.07:54:18.57#ibcon#read 4, iclass 23, count 0 2006.197.07:54:18.57#ibcon#about to read 5, iclass 23, count 0 2006.197.07:54:18.57#ibcon#read 5, iclass 23, count 0 2006.197.07:54:18.57#ibcon#about to read 6, iclass 23, count 0 2006.197.07:54:18.57#ibcon#read 6, iclass 23, count 0 2006.197.07:54:18.57#ibcon#end of sib2, iclass 23, count 0 2006.197.07:54:18.57#ibcon#*after write, iclass 23, count 0 2006.197.07:54:18.57#ibcon#*before return 0, iclass 23, count 0 2006.197.07:54:18.57#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.197.07:54:18.57#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.197.07:54:18.57#ibcon#about to clear, iclass 23 cls_cnt 0 2006.197.07:54:18.57#ibcon#cleared, iclass 23 cls_cnt 0 2006.197.07:54:18.57$vc4f8/va=4,7 2006.197.07:54:18.57#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.197.07:54:18.57#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.197.07:54:18.57#ibcon#ireg 11 cls_cnt 2 2006.197.07:54:18.57#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.197.07:54:18.63#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.197.07:54:18.63#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.197.07:54:18.63#ibcon#enter wrdev, iclass 25, count 2 2006.197.07:54:18.63#ibcon#first serial, iclass 25, count 2 2006.197.07:54:18.63#ibcon#enter sib2, iclass 25, count 2 2006.197.07:54:18.63#ibcon#flushed, iclass 25, count 2 2006.197.07:54:18.63#ibcon#about to write, iclass 25, count 2 2006.197.07:54:18.63#ibcon#wrote, iclass 25, count 2 2006.197.07:54:18.63#ibcon#about to read 3, iclass 25, count 2 2006.197.07:54:18.65#ibcon#read 3, iclass 25, count 2 2006.197.07:54:18.65#ibcon#about to read 4, iclass 25, count 2 2006.197.07:54:18.65#ibcon#read 4, iclass 25, count 2 2006.197.07:54:18.65#ibcon#about to read 5, iclass 25, count 2 2006.197.07:54:18.65#ibcon#read 5, iclass 25, count 2 2006.197.07:54:18.65#ibcon#about to read 6, iclass 25, count 2 2006.197.07:54:18.65#ibcon#read 6, iclass 25, count 2 2006.197.07:54:18.65#ibcon#end of sib2, iclass 25, count 2 2006.197.07:54:18.65#ibcon#*mode == 0, iclass 25, count 2 2006.197.07:54:18.65#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.197.07:54:18.65#ibcon#[25=AT04-07\r\n] 2006.197.07:54:18.65#ibcon#*before write, iclass 25, count 2 2006.197.07:54:18.65#ibcon#enter sib2, iclass 25, count 2 2006.197.07:54:18.65#ibcon#flushed, iclass 25, count 2 2006.197.07:54:18.65#ibcon#about to write, iclass 25, count 2 2006.197.07:54:18.65#ibcon#wrote, iclass 25, count 2 2006.197.07:54:18.65#ibcon#about to read 3, iclass 25, count 2 2006.197.07:54:18.68#ibcon#read 3, iclass 25, count 2 2006.197.07:54:18.68#ibcon#about to read 4, iclass 25, count 2 2006.197.07:54:18.68#ibcon#read 4, iclass 25, count 2 2006.197.07:54:18.68#ibcon#about to read 5, iclass 25, count 2 2006.197.07:54:18.68#ibcon#read 5, iclass 25, count 2 2006.197.07:54:18.68#ibcon#about to read 6, iclass 25, count 2 2006.197.07:54:18.68#ibcon#read 6, iclass 25, count 2 2006.197.07:54:18.68#ibcon#end of sib2, iclass 25, count 2 2006.197.07:54:18.68#ibcon#*after write, iclass 25, count 2 2006.197.07:54:18.68#ibcon#*before return 0, iclass 25, count 2 2006.197.07:54:18.68#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.197.07:54:18.68#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.197.07:54:18.68#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.197.07:54:18.68#ibcon#ireg 7 cls_cnt 0 2006.197.07:54:18.68#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.197.07:54:18.80#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.197.07:54:18.80#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.197.07:54:18.80#ibcon#enter wrdev, iclass 25, count 0 2006.197.07:54:18.80#ibcon#first serial, iclass 25, count 0 2006.197.07:54:18.80#ibcon#enter sib2, iclass 25, count 0 2006.197.07:54:18.80#ibcon#flushed, iclass 25, count 0 2006.197.07:54:18.80#ibcon#about to write, iclass 25, count 0 2006.197.07:54:18.80#ibcon#wrote, iclass 25, count 0 2006.197.07:54:18.80#ibcon#about to read 3, iclass 25, count 0 2006.197.07:54:18.82#ibcon#read 3, iclass 25, count 0 2006.197.07:54:18.82#ibcon#about to read 4, iclass 25, count 0 2006.197.07:54:18.82#ibcon#read 4, iclass 25, count 0 2006.197.07:54:18.82#ibcon#about to read 5, iclass 25, count 0 2006.197.07:54:18.82#ibcon#read 5, iclass 25, count 0 2006.197.07:54:18.82#ibcon#about to read 6, iclass 25, count 0 2006.197.07:54:18.82#ibcon#read 6, iclass 25, count 0 2006.197.07:54:18.82#ibcon#end of sib2, iclass 25, count 0 2006.197.07:54:18.82#ibcon#*mode == 0, iclass 25, count 0 2006.197.07:54:18.82#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.197.07:54:18.82#ibcon#[25=USB\r\n] 2006.197.07:54:18.82#ibcon#*before write, iclass 25, count 0 2006.197.07:54:18.82#ibcon#enter sib2, iclass 25, count 0 2006.197.07:54:18.82#ibcon#flushed, iclass 25, count 0 2006.197.07:54:18.82#ibcon#about to write, iclass 25, count 0 2006.197.07:54:18.82#ibcon#wrote, iclass 25, count 0 2006.197.07:54:18.82#ibcon#about to read 3, iclass 25, count 0 2006.197.07:54:18.85#ibcon#read 3, iclass 25, count 0 2006.197.07:54:18.85#ibcon#about to read 4, iclass 25, count 0 2006.197.07:54:18.85#ibcon#read 4, iclass 25, count 0 2006.197.07:54:18.85#ibcon#about to read 5, iclass 25, count 0 2006.197.07:54:18.85#ibcon#read 5, iclass 25, count 0 2006.197.07:54:18.85#ibcon#about to read 6, iclass 25, count 0 2006.197.07:54:18.85#ibcon#read 6, iclass 25, count 0 2006.197.07:54:18.85#ibcon#end of sib2, iclass 25, count 0 2006.197.07:54:18.85#ibcon#*after write, iclass 25, count 0 2006.197.07:54:18.85#ibcon#*before return 0, iclass 25, count 0 2006.197.07:54:18.85#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.197.07:54:18.85#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.197.07:54:18.85#ibcon#about to clear, iclass 25 cls_cnt 0 2006.197.07:54:18.85#ibcon#cleared, iclass 25 cls_cnt 0 2006.197.07:54:18.85$vc4f8/valo=5,652.99 2006.197.07:54:18.85#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.197.07:54:18.85#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.197.07:54:18.85#ibcon#ireg 17 cls_cnt 0 2006.197.07:54:18.85#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.197.07:54:18.85#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.197.07:54:18.85#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.197.07:54:18.85#ibcon#enter wrdev, iclass 27, count 0 2006.197.07:54:18.85#ibcon#first serial, iclass 27, count 0 2006.197.07:54:18.85#ibcon#enter sib2, iclass 27, count 0 2006.197.07:54:18.85#ibcon#flushed, iclass 27, count 0 2006.197.07:54:18.85#ibcon#about to write, iclass 27, count 0 2006.197.07:54:18.85#ibcon#wrote, iclass 27, count 0 2006.197.07:54:18.85#ibcon#about to read 3, iclass 27, count 0 2006.197.07:54:18.87#ibcon#read 3, iclass 27, count 0 2006.197.07:54:18.87#ibcon#about to read 4, iclass 27, count 0 2006.197.07:54:18.87#ibcon#read 4, iclass 27, count 0 2006.197.07:54:18.87#ibcon#about to read 5, iclass 27, count 0 2006.197.07:54:18.87#ibcon#read 5, iclass 27, count 0 2006.197.07:54:18.87#ibcon#about to read 6, iclass 27, count 0 2006.197.07:54:18.87#ibcon#read 6, iclass 27, count 0 2006.197.07:54:18.87#ibcon#end of sib2, iclass 27, count 0 2006.197.07:54:18.87#ibcon#*mode == 0, iclass 27, count 0 2006.197.07:54:18.87#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.197.07:54:18.87#ibcon#[26=FRQ=05,652.99\r\n] 2006.197.07:54:18.87#ibcon#*before write, iclass 27, count 0 2006.197.07:54:18.87#ibcon#enter sib2, iclass 27, count 0 2006.197.07:54:18.87#ibcon#flushed, iclass 27, count 0 2006.197.07:54:18.87#ibcon#about to write, iclass 27, count 0 2006.197.07:54:18.87#ibcon#wrote, iclass 27, count 0 2006.197.07:54:18.87#ibcon#about to read 3, iclass 27, count 0 2006.197.07:54:18.91#ibcon#read 3, iclass 27, count 0 2006.197.07:54:18.91#ibcon#about to read 4, iclass 27, count 0 2006.197.07:54:18.91#ibcon#read 4, iclass 27, count 0 2006.197.07:54:18.91#ibcon#about to read 5, iclass 27, count 0 2006.197.07:54:18.91#ibcon#read 5, iclass 27, count 0 2006.197.07:54:18.91#ibcon#about to read 6, iclass 27, count 0 2006.197.07:54:18.91#ibcon#read 6, iclass 27, count 0 2006.197.07:54:18.91#ibcon#end of sib2, iclass 27, count 0 2006.197.07:54:18.91#ibcon#*after write, iclass 27, count 0 2006.197.07:54:18.91#ibcon#*before return 0, iclass 27, count 0 2006.197.07:54:18.91#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.197.07:54:18.91#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.197.07:54:18.91#ibcon#about to clear, iclass 27 cls_cnt 0 2006.197.07:54:18.91#ibcon#cleared, iclass 27 cls_cnt 0 2006.197.07:54:18.91$vc4f8/va=5,7 2006.197.07:54:18.91#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.197.07:54:18.91#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.197.07:54:18.91#ibcon#ireg 11 cls_cnt 2 2006.197.07:54:18.91#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.197.07:54:18.97#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.197.07:54:18.97#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.197.07:54:18.97#ibcon#enter wrdev, iclass 29, count 2 2006.197.07:54:18.97#ibcon#first serial, iclass 29, count 2 2006.197.07:54:18.97#ibcon#enter sib2, iclass 29, count 2 2006.197.07:54:18.97#ibcon#flushed, iclass 29, count 2 2006.197.07:54:18.97#ibcon#about to write, iclass 29, count 2 2006.197.07:54:18.97#ibcon#wrote, iclass 29, count 2 2006.197.07:54:18.97#ibcon#about to read 3, iclass 29, count 2 2006.197.07:54:18.99#ibcon#read 3, iclass 29, count 2 2006.197.07:54:18.99#ibcon#about to read 4, iclass 29, count 2 2006.197.07:54:18.99#ibcon#read 4, iclass 29, count 2 2006.197.07:54:18.99#ibcon#about to read 5, iclass 29, count 2 2006.197.07:54:18.99#ibcon#read 5, iclass 29, count 2 2006.197.07:54:18.99#ibcon#about to read 6, iclass 29, count 2 2006.197.07:54:18.99#ibcon#read 6, iclass 29, count 2 2006.197.07:54:18.99#ibcon#end of sib2, iclass 29, count 2 2006.197.07:54:18.99#ibcon#*mode == 0, iclass 29, count 2 2006.197.07:54:18.99#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.197.07:54:18.99#ibcon#[25=AT05-07\r\n] 2006.197.07:54:18.99#ibcon#*before write, iclass 29, count 2 2006.197.07:54:18.99#ibcon#enter sib2, iclass 29, count 2 2006.197.07:54:18.99#ibcon#flushed, iclass 29, count 2 2006.197.07:54:18.99#ibcon#about to write, iclass 29, count 2 2006.197.07:54:18.99#ibcon#wrote, iclass 29, count 2 2006.197.07:54:18.99#ibcon#about to read 3, iclass 29, count 2 2006.197.07:54:19.02#ibcon#read 3, iclass 29, count 2 2006.197.07:54:19.02#ibcon#about to read 4, iclass 29, count 2 2006.197.07:54:19.02#ibcon#read 4, iclass 29, count 2 2006.197.07:54:19.02#ibcon#about to read 5, iclass 29, count 2 2006.197.07:54:19.02#ibcon#read 5, iclass 29, count 2 2006.197.07:54:19.02#ibcon#about to read 6, iclass 29, count 2 2006.197.07:54:19.02#ibcon#read 6, iclass 29, count 2 2006.197.07:54:19.02#ibcon#end of sib2, iclass 29, count 2 2006.197.07:54:19.02#ibcon#*after write, iclass 29, count 2 2006.197.07:54:19.02#ibcon#*before return 0, iclass 29, count 2 2006.197.07:54:19.02#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.197.07:54:19.02#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.197.07:54:19.02#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.197.07:54:19.02#ibcon#ireg 7 cls_cnt 0 2006.197.07:54:19.02#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.197.07:54:19.14#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.197.07:54:19.14#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.197.07:54:19.14#ibcon#enter wrdev, iclass 29, count 0 2006.197.07:54:19.14#ibcon#first serial, iclass 29, count 0 2006.197.07:54:19.14#ibcon#enter sib2, iclass 29, count 0 2006.197.07:54:19.14#ibcon#flushed, iclass 29, count 0 2006.197.07:54:19.14#ibcon#about to write, iclass 29, count 0 2006.197.07:54:19.14#ibcon#wrote, iclass 29, count 0 2006.197.07:54:19.14#ibcon#about to read 3, iclass 29, count 0 2006.197.07:54:19.16#ibcon#read 3, iclass 29, count 0 2006.197.07:54:19.16#ibcon#about to read 4, iclass 29, count 0 2006.197.07:54:19.16#ibcon#read 4, iclass 29, count 0 2006.197.07:54:19.16#ibcon#about to read 5, iclass 29, count 0 2006.197.07:54:19.16#ibcon#read 5, iclass 29, count 0 2006.197.07:54:19.16#ibcon#about to read 6, iclass 29, count 0 2006.197.07:54:19.16#ibcon#read 6, iclass 29, count 0 2006.197.07:54:19.16#ibcon#end of sib2, iclass 29, count 0 2006.197.07:54:19.16#ibcon#*mode == 0, iclass 29, count 0 2006.197.07:54:19.16#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.197.07:54:19.16#ibcon#[25=USB\r\n] 2006.197.07:54:19.16#ibcon#*before write, iclass 29, count 0 2006.197.07:54:19.16#ibcon#enter sib2, iclass 29, count 0 2006.197.07:54:19.16#ibcon#flushed, iclass 29, count 0 2006.197.07:54:19.16#ibcon#about to write, iclass 29, count 0 2006.197.07:54:19.16#ibcon#wrote, iclass 29, count 0 2006.197.07:54:19.16#ibcon#about to read 3, iclass 29, count 0 2006.197.07:54:19.19#ibcon#read 3, iclass 29, count 0 2006.197.07:54:19.19#ibcon#about to read 4, iclass 29, count 0 2006.197.07:54:19.19#ibcon#read 4, iclass 29, count 0 2006.197.07:54:19.19#ibcon#about to read 5, iclass 29, count 0 2006.197.07:54:19.19#ibcon#read 5, iclass 29, count 0 2006.197.07:54:19.19#ibcon#about to read 6, iclass 29, count 0 2006.197.07:54:19.19#ibcon#read 6, iclass 29, count 0 2006.197.07:54:19.19#ibcon#end of sib2, iclass 29, count 0 2006.197.07:54:19.19#ibcon#*after write, iclass 29, count 0 2006.197.07:54:19.19#ibcon#*before return 0, iclass 29, count 0 2006.197.07:54:19.19#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.197.07:54:19.19#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.197.07:54:19.19#ibcon#about to clear, iclass 29 cls_cnt 0 2006.197.07:54:19.19#ibcon#cleared, iclass 29 cls_cnt 0 2006.197.07:54:19.19$vc4f8/valo=6,772.99 2006.197.07:54:19.19#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.197.07:54:19.19#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.197.07:54:19.19#ibcon#ireg 17 cls_cnt 0 2006.197.07:54:19.19#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.197.07:54:19.19#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.197.07:54:19.19#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.197.07:54:19.19#ibcon#enter wrdev, iclass 31, count 0 2006.197.07:54:19.19#ibcon#first serial, iclass 31, count 0 2006.197.07:54:19.19#ibcon#enter sib2, iclass 31, count 0 2006.197.07:54:19.19#ibcon#flushed, iclass 31, count 0 2006.197.07:54:19.19#ibcon#about to write, iclass 31, count 0 2006.197.07:54:19.19#ibcon#wrote, iclass 31, count 0 2006.197.07:54:19.19#ibcon#about to read 3, iclass 31, count 0 2006.197.07:54:19.21#ibcon#read 3, iclass 31, count 0 2006.197.07:54:19.21#ibcon#about to read 4, iclass 31, count 0 2006.197.07:54:19.21#ibcon#read 4, iclass 31, count 0 2006.197.07:54:19.21#ibcon#about to read 5, iclass 31, count 0 2006.197.07:54:19.21#ibcon#read 5, iclass 31, count 0 2006.197.07:54:19.21#ibcon#about to read 6, iclass 31, count 0 2006.197.07:54:19.21#ibcon#read 6, iclass 31, count 0 2006.197.07:54:19.21#ibcon#end of sib2, iclass 31, count 0 2006.197.07:54:19.21#ibcon#*mode == 0, iclass 31, count 0 2006.197.07:54:19.21#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.197.07:54:19.21#ibcon#[26=FRQ=06,772.99\r\n] 2006.197.07:54:19.21#ibcon#*before write, iclass 31, count 0 2006.197.07:54:19.21#ibcon#enter sib2, iclass 31, count 0 2006.197.07:54:19.21#ibcon#flushed, iclass 31, count 0 2006.197.07:54:19.21#ibcon#about to write, iclass 31, count 0 2006.197.07:54:19.21#ibcon#wrote, iclass 31, count 0 2006.197.07:54:19.21#ibcon#about to read 3, iclass 31, count 0 2006.197.07:54:19.25#ibcon#read 3, iclass 31, count 0 2006.197.07:54:19.25#ibcon#about to read 4, iclass 31, count 0 2006.197.07:54:19.25#ibcon#read 4, iclass 31, count 0 2006.197.07:54:19.25#ibcon#about to read 5, iclass 31, count 0 2006.197.07:54:19.25#ibcon#read 5, iclass 31, count 0 2006.197.07:54:19.25#ibcon#about to read 6, iclass 31, count 0 2006.197.07:54:19.25#ibcon#read 6, iclass 31, count 0 2006.197.07:54:19.25#ibcon#end of sib2, iclass 31, count 0 2006.197.07:54:19.25#ibcon#*after write, iclass 31, count 0 2006.197.07:54:19.25#ibcon#*before return 0, iclass 31, count 0 2006.197.07:54:19.25#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.197.07:54:19.25#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.197.07:54:19.25#ibcon#about to clear, iclass 31 cls_cnt 0 2006.197.07:54:19.25#ibcon#cleared, iclass 31 cls_cnt 0 2006.197.07:54:19.25$vc4f8/va=6,6 2006.197.07:54:19.25#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.197.07:54:19.25#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.197.07:54:19.25#ibcon#ireg 11 cls_cnt 2 2006.197.07:54:19.25#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.197.07:54:19.31#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.197.07:54:19.31#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.197.07:54:19.31#ibcon#enter wrdev, iclass 33, count 2 2006.197.07:54:19.31#ibcon#first serial, iclass 33, count 2 2006.197.07:54:19.31#ibcon#enter sib2, iclass 33, count 2 2006.197.07:54:19.31#ibcon#flushed, iclass 33, count 2 2006.197.07:54:19.31#ibcon#about to write, iclass 33, count 2 2006.197.07:54:19.31#ibcon#wrote, iclass 33, count 2 2006.197.07:54:19.31#ibcon#about to read 3, iclass 33, count 2 2006.197.07:54:19.33#ibcon#read 3, iclass 33, count 2 2006.197.07:54:19.33#ibcon#about to read 4, iclass 33, count 2 2006.197.07:54:19.33#ibcon#read 4, iclass 33, count 2 2006.197.07:54:19.33#ibcon#about to read 5, iclass 33, count 2 2006.197.07:54:19.33#ibcon#read 5, iclass 33, count 2 2006.197.07:54:19.33#ibcon#about to read 6, iclass 33, count 2 2006.197.07:54:19.33#ibcon#read 6, iclass 33, count 2 2006.197.07:54:19.33#ibcon#end of sib2, iclass 33, count 2 2006.197.07:54:19.33#ibcon#*mode == 0, iclass 33, count 2 2006.197.07:54:19.33#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.197.07:54:19.33#ibcon#[25=AT06-06\r\n] 2006.197.07:54:19.33#ibcon#*before write, iclass 33, count 2 2006.197.07:54:19.33#ibcon#enter sib2, iclass 33, count 2 2006.197.07:54:19.33#ibcon#flushed, iclass 33, count 2 2006.197.07:54:19.33#ibcon#about to write, iclass 33, count 2 2006.197.07:54:19.33#ibcon#wrote, iclass 33, count 2 2006.197.07:54:19.33#ibcon#about to read 3, iclass 33, count 2 2006.197.07:54:19.36#ibcon#read 3, iclass 33, count 2 2006.197.07:54:19.36#ibcon#about to read 4, iclass 33, count 2 2006.197.07:54:19.36#ibcon#read 4, iclass 33, count 2 2006.197.07:54:19.36#ibcon#about to read 5, iclass 33, count 2 2006.197.07:54:19.36#ibcon#read 5, iclass 33, count 2 2006.197.07:54:19.36#ibcon#about to read 6, iclass 33, count 2 2006.197.07:54:19.36#ibcon#read 6, iclass 33, count 2 2006.197.07:54:19.36#ibcon#end of sib2, iclass 33, count 2 2006.197.07:54:19.36#ibcon#*after write, iclass 33, count 2 2006.197.07:54:19.36#ibcon#*before return 0, iclass 33, count 2 2006.197.07:54:19.36#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.197.07:54:19.36#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.197.07:54:19.36#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.197.07:54:19.36#ibcon#ireg 7 cls_cnt 0 2006.197.07:54:19.36#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.197.07:54:19.48#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.197.07:54:19.48#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.197.07:54:19.48#ibcon#enter wrdev, iclass 33, count 0 2006.197.07:54:19.48#ibcon#first serial, iclass 33, count 0 2006.197.07:54:19.48#ibcon#enter sib2, iclass 33, count 0 2006.197.07:54:19.48#ibcon#flushed, iclass 33, count 0 2006.197.07:54:19.48#ibcon#about to write, iclass 33, count 0 2006.197.07:54:19.48#ibcon#wrote, iclass 33, count 0 2006.197.07:54:19.48#ibcon#about to read 3, iclass 33, count 0 2006.197.07:54:19.50#ibcon#read 3, iclass 33, count 0 2006.197.07:54:19.50#ibcon#about to read 4, iclass 33, count 0 2006.197.07:54:19.50#ibcon#read 4, iclass 33, count 0 2006.197.07:54:19.50#ibcon#about to read 5, iclass 33, count 0 2006.197.07:54:19.50#ibcon#read 5, iclass 33, count 0 2006.197.07:54:19.50#ibcon#about to read 6, iclass 33, count 0 2006.197.07:54:19.50#ibcon#read 6, iclass 33, count 0 2006.197.07:54:19.50#ibcon#end of sib2, iclass 33, count 0 2006.197.07:54:19.50#ibcon#*mode == 0, iclass 33, count 0 2006.197.07:54:19.50#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.197.07:54:19.50#ibcon#[25=USB\r\n] 2006.197.07:54:19.50#ibcon#*before write, iclass 33, count 0 2006.197.07:54:19.50#ibcon#enter sib2, iclass 33, count 0 2006.197.07:54:19.50#ibcon#flushed, iclass 33, count 0 2006.197.07:54:19.50#ibcon#about to write, iclass 33, count 0 2006.197.07:54:19.50#ibcon#wrote, iclass 33, count 0 2006.197.07:54:19.50#ibcon#about to read 3, iclass 33, count 0 2006.197.07:54:19.53#ibcon#read 3, iclass 33, count 0 2006.197.07:54:19.53#ibcon#about to read 4, iclass 33, count 0 2006.197.07:54:19.53#ibcon#read 4, iclass 33, count 0 2006.197.07:54:19.53#ibcon#about to read 5, iclass 33, count 0 2006.197.07:54:19.53#ibcon#read 5, iclass 33, count 0 2006.197.07:54:19.53#ibcon#about to read 6, iclass 33, count 0 2006.197.07:54:19.53#ibcon#read 6, iclass 33, count 0 2006.197.07:54:19.53#ibcon#end of sib2, iclass 33, count 0 2006.197.07:54:19.53#ibcon#*after write, iclass 33, count 0 2006.197.07:54:19.53#ibcon#*before return 0, iclass 33, count 0 2006.197.07:54:19.53#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.197.07:54:19.53#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.197.07:54:19.53#ibcon#about to clear, iclass 33 cls_cnt 0 2006.197.07:54:19.53#ibcon#cleared, iclass 33 cls_cnt 0 2006.197.07:54:19.53$vc4f8/valo=7,832.99 2006.197.07:54:19.53#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.197.07:54:19.53#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.197.07:54:19.53#ibcon#ireg 17 cls_cnt 0 2006.197.07:54:19.53#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.197.07:54:19.53#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.197.07:54:19.53#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.197.07:54:19.53#ibcon#enter wrdev, iclass 35, count 0 2006.197.07:54:19.53#ibcon#first serial, iclass 35, count 0 2006.197.07:54:19.53#ibcon#enter sib2, iclass 35, count 0 2006.197.07:54:19.53#ibcon#flushed, iclass 35, count 0 2006.197.07:54:19.53#ibcon#about to write, iclass 35, count 0 2006.197.07:54:19.53#ibcon#wrote, iclass 35, count 0 2006.197.07:54:19.53#ibcon#about to read 3, iclass 35, count 0 2006.197.07:54:19.55#ibcon#read 3, iclass 35, count 0 2006.197.07:54:19.55#ibcon#about to read 4, iclass 35, count 0 2006.197.07:54:19.55#ibcon#read 4, iclass 35, count 0 2006.197.07:54:19.55#ibcon#about to read 5, iclass 35, count 0 2006.197.07:54:19.55#ibcon#read 5, iclass 35, count 0 2006.197.07:54:19.55#ibcon#about to read 6, iclass 35, count 0 2006.197.07:54:19.55#ibcon#read 6, iclass 35, count 0 2006.197.07:54:19.55#ibcon#end of sib2, iclass 35, count 0 2006.197.07:54:19.55#ibcon#*mode == 0, iclass 35, count 0 2006.197.07:54:19.55#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.197.07:54:19.55#ibcon#[26=FRQ=07,832.99\r\n] 2006.197.07:54:19.55#ibcon#*before write, iclass 35, count 0 2006.197.07:54:19.55#ibcon#enter sib2, iclass 35, count 0 2006.197.07:54:19.55#ibcon#flushed, iclass 35, count 0 2006.197.07:54:19.55#ibcon#about to write, iclass 35, count 0 2006.197.07:54:19.55#ibcon#wrote, iclass 35, count 0 2006.197.07:54:19.55#ibcon#about to read 3, iclass 35, count 0 2006.197.07:54:19.59#ibcon#read 3, iclass 35, count 0 2006.197.07:54:19.59#ibcon#about to read 4, iclass 35, count 0 2006.197.07:54:19.59#ibcon#read 4, iclass 35, count 0 2006.197.07:54:19.59#ibcon#about to read 5, iclass 35, count 0 2006.197.07:54:19.59#ibcon#read 5, iclass 35, count 0 2006.197.07:54:19.59#ibcon#about to read 6, iclass 35, count 0 2006.197.07:54:19.59#ibcon#read 6, iclass 35, count 0 2006.197.07:54:19.59#ibcon#end of sib2, iclass 35, count 0 2006.197.07:54:19.59#ibcon#*after write, iclass 35, count 0 2006.197.07:54:19.59#ibcon#*before return 0, iclass 35, count 0 2006.197.07:54:19.59#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.197.07:54:19.59#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.197.07:54:19.59#ibcon#about to clear, iclass 35 cls_cnt 0 2006.197.07:54:19.59#ibcon#cleared, iclass 35 cls_cnt 0 2006.197.07:54:19.59$vc4f8/va=7,6 2006.197.07:54:19.59#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.197.07:54:19.59#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.197.07:54:19.59#ibcon#ireg 11 cls_cnt 2 2006.197.07:54:19.59#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.197.07:54:19.65#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.197.07:54:19.65#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.197.07:54:19.65#ibcon#enter wrdev, iclass 37, count 2 2006.197.07:54:19.65#ibcon#first serial, iclass 37, count 2 2006.197.07:54:19.65#ibcon#enter sib2, iclass 37, count 2 2006.197.07:54:19.65#ibcon#flushed, iclass 37, count 2 2006.197.07:54:19.65#ibcon#about to write, iclass 37, count 2 2006.197.07:54:19.65#ibcon#wrote, iclass 37, count 2 2006.197.07:54:19.65#ibcon#about to read 3, iclass 37, count 2 2006.197.07:54:19.67#ibcon#read 3, iclass 37, count 2 2006.197.07:54:19.67#ibcon#about to read 4, iclass 37, count 2 2006.197.07:54:19.67#ibcon#read 4, iclass 37, count 2 2006.197.07:54:19.67#ibcon#about to read 5, iclass 37, count 2 2006.197.07:54:19.67#ibcon#read 5, iclass 37, count 2 2006.197.07:54:19.67#ibcon#about to read 6, iclass 37, count 2 2006.197.07:54:19.67#ibcon#read 6, iclass 37, count 2 2006.197.07:54:19.67#ibcon#end of sib2, iclass 37, count 2 2006.197.07:54:19.67#ibcon#*mode == 0, iclass 37, count 2 2006.197.07:54:19.67#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.197.07:54:19.67#ibcon#[25=AT07-06\r\n] 2006.197.07:54:19.67#ibcon#*before write, iclass 37, count 2 2006.197.07:54:19.67#ibcon#enter sib2, iclass 37, count 2 2006.197.07:54:19.67#ibcon#flushed, iclass 37, count 2 2006.197.07:54:19.67#ibcon#about to write, iclass 37, count 2 2006.197.07:54:19.67#ibcon#wrote, iclass 37, count 2 2006.197.07:54:19.67#ibcon#about to read 3, iclass 37, count 2 2006.197.07:54:19.70#ibcon#read 3, iclass 37, count 2 2006.197.07:54:19.70#ibcon#about to read 4, iclass 37, count 2 2006.197.07:54:19.70#ibcon#read 4, iclass 37, count 2 2006.197.07:54:19.70#ibcon#about to read 5, iclass 37, count 2 2006.197.07:54:19.70#ibcon#read 5, iclass 37, count 2 2006.197.07:54:19.70#ibcon#about to read 6, iclass 37, count 2 2006.197.07:54:19.70#ibcon#read 6, iclass 37, count 2 2006.197.07:54:19.70#ibcon#end of sib2, iclass 37, count 2 2006.197.07:54:19.70#ibcon#*after write, iclass 37, count 2 2006.197.07:54:19.70#ibcon#*before return 0, iclass 37, count 2 2006.197.07:54:19.70#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.197.07:54:19.70#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.197.07:54:19.70#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.197.07:54:19.70#ibcon#ireg 7 cls_cnt 0 2006.197.07:54:19.70#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.197.07:54:19.82#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.197.07:54:19.82#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.197.07:54:19.82#ibcon#enter wrdev, iclass 37, count 0 2006.197.07:54:19.82#ibcon#first serial, iclass 37, count 0 2006.197.07:54:19.82#ibcon#enter sib2, iclass 37, count 0 2006.197.07:54:19.82#ibcon#flushed, iclass 37, count 0 2006.197.07:54:19.82#ibcon#about to write, iclass 37, count 0 2006.197.07:54:19.82#ibcon#wrote, iclass 37, count 0 2006.197.07:54:19.82#ibcon#about to read 3, iclass 37, count 0 2006.197.07:54:19.84#ibcon#read 3, iclass 37, count 0 2006.197.07:54:19.84#ibcon#about to read 4, iclass 37, count 0 2006.197.07:54:19.84#ibcon#read 4, iclass 37, count 0 2006.197.07:54:19.84#ibcon#about to read 5, iclass 37, count 0 2006.197.07:54:19.84#ibcon#read 5, iclass 37, count 0 2006.197.07:54:19.84#ibcon#about to read 6, iclass 37, count 0 2006.197.07:54:19.84#ibcon#read 6, iclass 37, count 0 2006.197.07:54:19.84#ibcon#end of sib2, iclass 37, count 0 2006.197.07:54:19.84#ibcon#*mode == 0, iclass 37, count 0 2006.197.07:54:19.84#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.197.07:54:19.84#ibcon#[25=USB\r\n] 2006.197.07:54:19.84#ibcon#*before write, iclass 37, count 0 2006.197.07:54:19.84#ibcon#enter sib2, iclass 37, count 0 2006.197.07:54:19.84#ibcon#flushed, iclass 37, count 0 2006.197.07:54:19.84#ibcon#about to write, iclass 37, count 0 2006.197.07:54:19.84#ibcon#wrote, iclass 37, count 0 2006.197.07:54:19.84#ibcon#about to read 3, iclass 37, count 0 2006.197.07:54:19.87#ibcon#read 3, iclass 37, count 0 2006.197.07:54:19.87#ibcon#about to read 4, iclass 37, count 0 2006.197.07:54:19.87#ibcon#read 4, iclass 37, count 0 2006.197.07:54:19.87#ibcon#about to read 5, iclass 37, count 0 2006.197.07:54:19.87#ibcon#read 5, iclass 37, count 0 2006.197.07:54:19.87#ibcon#about to read 6, iclass 37, count 0 2006.197.07:54:19.87#ibcon#read 6, iclass 37, count 0 2006.197.07:54:19.87#ibcon#end of sib2, iclass 37, count 0 2006.197.07:54:19.87#ibcon#*after write, iclass 37, count 0 2006.197.07:54:19.87#ibcon#*before return 0, iclass 37, count 0 2006.197.07:54:19.87#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.197.07:54:19.87#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.197.07:54:19.87#ibcon#about to clear, iclass 37 cls_cnt 0 2006.197.07:54:19.87#ibcon#cleared, iclass 37 cls_cnt 0 2006.197.07:54:19.87$vc4f8/valo=8,852.99 2006.197.07:54:19.87#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.197.07:54:19.87#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.197.07:54:19.87#ibcon#ireg 17 cls_cnt 0 2006.197.07:54:19.87#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.197.07:54:19.87#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.197.07:54:19.87#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.197.07:54:19.87#ibcon#enter wrdev, iclass 39, count 0 2006.197.07:54:19.87#ibcon#first serial, iclass 39, count 0 2006.197.07:54:19.87#ibcon#enter sib2, iclass 39, count 0 2006.197.07:54:19.87#ibcon#flushed, iclass 39, count 0 2006.197.07:54:19.87#ibcon#about to write, iclass 39, count 0 2006.197.07:54:19.87#ibcon#wrote, iclass 39, count 0 2006.197.07:54:19.87#ibcon#about to read 3, iclass 39, count 0 2006.197.07:54:19.89#ibcon#read 3, iclass 39, count 0 2006.197.07:54:19.89#ibcon#about to read 4, iclass 39, count 0 2006.197.07:54:19.89#ibcon#read 4, iclass 39, count 0 2006.197.07:54:19.89#ibcon#about to read 5, iclass 39, count 0 2006.197.07:54:19.89#ibcon#read 5, iclass 39, count 0 2006.197.07:54:19.89#ibcon#about to read 6, iclass 39, count 0 2006.197.07:54:19.89#ibcon#read 6, iclass 39, count 0 2006.197.07:54:19.89#ibcon#end of sib2, iclass 39, count 0 2006.197.07:54:19.89#ibcon#*mode == 0, iclass 39, count 0 2006.197.07:54:19.89#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.197.07:54:19.89#ibcon#[26=FRQ=08,852.99\r\n] 2006.197.07:54:19.89#ibcon#*before write, iclass 39, count 0 2006.197.07:54:19.89#ibcon#enter sib2, iclass 39, count 0 2006.197.07:54:19.89#ibcon#flushed, iclass 39, count 0 2006.197.07:54:19.89#ibcon#about to write, iclass 39, count 0 2006.197.07:54:19.89#ibcon#wrote, iclass 39, count 0 2006.197.07:54:19.89#ibcon#about to read 3, iclass 39, count 0 2006.197.07:54:19.93#ibcon#read 3, iclass 39, count 0 2006.197.07:54:19.93#ibcon#about to read 4, iclass 39, count 0 2006.197.07:54:19.93#ibcon#read 4, iclass 39, count 0 2006.197.07:54:19.93#ibcon#about to read 5, iclass 39, count 0 2006.197.07:54:19.93#ibcon#read 5, iclass 39, count 0 2006.197.07:54:19.93#ibcon#about to read 6, iclass 39, count 0 2006.197.07:54:19.93#ibcon#read 6, iclass 39, count 0 2006.197.07:54:19.93#ibcon#end of sib2, iclass 39, count 0 2006.197.07:54:19.93#ibcon#*after write, iclass 39, count 0 2006.197.07:54:19.93#ibcon#*before return 0, iclass 39, count 0 2006.197.07:54:19.93#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.197.07:54:19.93#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.197.07:54:19.93#ibcon#about to clear, iclass 39 cls_cnt 0 2006.197.07:54:19.93#ibcon#cleared, iclass 39 cls_cnt 0 2006.197.07:54:19.93$vc4f8/va=8,7 2006.197.07:54:19.93#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.197.07:54:19.93#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.197.07:54:19.93#ibcon#ireg 11 cls_cnt 2 2006.197.07:54:19.93#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.197.07:54:19.99#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.197.07:54:19.99#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.197.07:54:19.99#ibcon#enter wrdev, iclass 3, count 2 2006.197.07:54:19.99#ibcon#first serial, iclass 3, count 2 2006.197.07:54:19.99#ibcon#enter sib2, iclass 3, count 2 2006.197.07:54:19.99#ibcon#flushed, iclass 3, count 2 2006.197.07:54:19.99#ibcon#about to write, iclass 3, count 2 2006.197.07:54:19.99#ibcon#wrote, iclass 3, count 2 2006.197.07:54:19.99#ibcon#about to read 3, iclass 3, count 2 2006.197.07:54:20.01#ibcon#read 3, iclass 3, count 2 2006.197.07:54:20.01#ibcon#about to read 4, iclass 3, count 2 2006.197.07:54:20.01#ibcon#read 4, iclass 3, count 2 2006.197.07:54:20.01#ibcon#about to read 5, iclass 3, count 2 2006.197.07:54:20.01#ibcon#read 5, iclass 3, count 2 2006.197.07:54:20.01#ibcon#about to read 6, iclass 3, count 2 2006.197.07:54:20.01#ibcon#read 6, iclass 3, count 2 2006.197.07:54:20.01#ibcon#end of sib2, iclass 3, count 2 2006.197.07:54:20.01#ibcon#*mode == 0, iclass 3, count 2 2006.197.07:54:20.01#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.197.07:54:20.01#ibcon#[25=AT08-07\r\n] 2006.197.07:54:20.01#ibcon#*before write, iclass 3, count 2 2006.197.07:54:20.01#ibcon#enter sib2, iclass 3, count 2 2006.197.07:54:20.01#ibcon#flushed, iclass 3, count 2 2006.197.07:54:20.01#ibcon#about to write, iclass 3, count 2 2006.197.07:54:20.01#ibcon#wrote, iclass 3, count 2 2006.197.07:54:20.01#ibcon#about to read 3, iclass 3, count 2 2006.197.07:54:20.04#ibcon#read 3, iclass 3, count 2 2006.197.07:54:20.04#ibcon#about to read 4, iclass 3, count 2 2006.197.07:54:20.04#ibcon#read 4, iclass 3, count 2 2006.197.07:54:20.04#ibcon#about to read 5, iclass 3, count 2 2006.197.07:54:20.04#ibcon#read 5, iclass 3, count 2 2006.197.07:54:20.04#ibcon#about to read 6, iclass 3, count 2 2006.197.07:54:20.04#ibcon#read 6, iclass 3, count 2 2006.197.07:54:20.04#ibcon#end of sib2, iclass 3, count 2 2006.197.07:54:20.04#ibcon#*after write, iclass 3, count 2 2006.197.07:54:20.04#ibcon#*before return 0, iclass 3, count 2 2006.197.07:54:20.04#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.197.07:54:20.04#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.197.07:54:20.04#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.197.07:54:20.04#ibcon#ireg 7 cls_cnt 0 2006.197.07:54:20.04#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.197.07:54:20.16#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.197.07:54:20.16#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.197.07:54:20.16#ibcon#enter wrdev, iclass 3, count 0 2006.197.07:54:20.16#ibcon#first serial, iclass 3, count 0 2006.197.07:54:20.16#ibcon#enter sib2, iclass 3, count 0 2006.197.07:54:20.16#ibcon#flushed, iclass 3, count 0 2006.197.07:54:20.16#ibcon#about to write, iclass 3, count 0 2006.197.07:54:20.16#ibcon#wrote, iclass 3, count 0 2006.197.07:54:20.16#ibcon#about to read 3, iclass 3, count 0 2006.197.07:54:20.18#ibcon#read 3, iclass 3, count 0 2006.197.07:54:20.18#ibcon#about to read 4, iclass 3, count 0 2006.197.07:54:20.18#ibcon#read 4, iclass 3, count 0 2006.197.07:54:20.18#ibcon#about to read 5, iclass 3, count 0 2006.197.07:54:20.18#ibcon#read 5, iclass 3, count 0 2006.197.07:54:20.18#ibcon#about to read 6, iclass 3, count 0 2006.197.07:54:20.18#ibcon#read 6, iclass 3, count 0 2006.197.07:54:20.18#ibcon#end of sib2, iclass 3, count 0 2006.197.07:54:20.18#ibcon#*mode == 0, iclass 3, count 0 2006.197.07:54:20.18#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.197.07:54:20.18#ibcon#[25=USB\r\n] 2006.197.07:54:20.18#ibcon#*before write, iclass 3, count 0 2006.197.07:54:20.18#ibcon#enter sib2, iclass 3, count 0 2006.197.07:54:20.18#ibcon#flushed, iclass 3, count 0 2006.197.07:54:20.18#ibcon#about to write, iclass 3, count 0 2006.197.07:54:20.18#ibcon#wrote, iclass 3, count 0 2006.197.07:54:20.18#ibcon#about to read 3, iclass 3, count 0 2006.197.07:54:20.21#ibcon#read 3, iclass 3, count 0 2006.197.07:54:20.21#ibcon#about to read 4, iclass 3, count 0 2006.197.07:54:20.21#ibcon#read 4, iclass 3, count 0 2006.197.07:54:20.21#ibcon#about to read 5, iclass 3, count 0 2006.197.07:54:20.21#ibcon#read 5, iclass 3, count 0 2006.197.07:54:20.21#ibcon#about to read 6, iclass 3, count 0 2006.197.07:54:20.21#ibcon#read 6, iclass 3, count 0 2006.197.07:54:20.21#ibcon#end of sib2, iclass 3, count 0 2006.197.07:54:20.21#ibcon#*after write, iclass 3, count 0 2006.197.07:54:20.21#ibcon#*before return 0, iclass 3, count 0 2006.197.07:54:20.21#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.197.07:54:20.21#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.197.07:54:20.21#ibcon#about to clear, iclass 3 cls_cnt 0 2006.197.07:54:20.21#ibcon#cleared, iclass 3 cls_cnt 0 2006.197.07:54:20.21$vc4f8/vblo=1,632.99 2006.197.07:54:20.21#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.197.07:54:20.21#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.197.07:54:20.21#ibcon#ireg 17 cls_cnt 0 2006.197.07:54:20.21#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.197.07:54:20.21#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.197.07:54:20.21#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.197.07:54:20.21#ibcon#enter wrdev, iclass 5, count 0 2006.197.07:54:20.21#ibcon#first serial, iclass 5, count 0 2006.197.07:54:20.21#ibcon#enter sib2, iclass 5, count 0 2006.197.07:54:20.21#ibcon#flushed, iclass 5, count 0 2006.197.07:54:20.21#ibcon#about to write, iclass 5, count 0 2006.197.07:54:20.21#ibcon#wrote, iclass 5, count 0 2006.197.07:54:20.21#ibcon#about to read 3, iclass 5, count 0 2006.197.07:54:20.23#ibcon#read 3, iclass 5, count 0 2006.197.07:54:20.23#ibcon#about to read 4, iclass 5, count 0 2006.197.07:54:20.23#ibcon#read 4, iclass 5, count 0 2006.197.07:54:20.23#ibcon#about to read 5, iclass 5, count 0 2006.197.07:54:20.23#ibcon#read 5, iclass 5, count 0 2006.197.07:54:20.23#ibcon#about to read 6, iclass 5, count 0 2006.197.07:54:20.23#ibcon#read 6, iclass 5, count 0 2006.197.07:54:20.23#ibcon#end of sib2, iclass 5, count 0 2006.197.07:54:20.23#ibcon#*mode == 0, iclass 5, count 0 2006.197.07:54:20.23#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.197.07:54:20.23#ibcon#[28=FRQ=01,632.99\r\n] 2006.197.07:54:20.23#ibcon#*before write, iclass 5, count 0 2006.197.07:54:20.23#ibcon#enter sib2, iclass 5, count 0 2006.197.07:54:20.23#ibcon#flushed, iclass 5, count 0 2006.197.07:54:20.23#ibcon#about to write, iclass 5, count 0 2006.197.07:54:20.23#ibcon#wrote, iclass 5, count 0 2006.197.07:54:20.23#ibcon#about to read 3, iclass 5, count 0 2006.197.07:54:20.27#ibcon#read 3, iclass 5, count 0 2006.197.07:54:20.27#ibcon#about to read 4, iclass 5, count 0 2006.197.07:54:20.27#ibcon#read 4, iclass 5, count 0 2006.197.07:54:20.27#ibcon#about to read 5, iclass 5, count 0 2006.197.07:54:20.27#ibcon#read 5, iclass 5, count 0 2006.197.07:54:20.27#ibcon#about to read 6, iclass 5, count 0 2006.197.07:54:20.27#ibcon#read 6, iclass 5, count 0 2006.197.07:54:20.27#ibcon#end of sib2, iclass 5, count 0 2006.197.07:54:20.27#ibcon#*after write, iclass 5, count 0 2006.197.07:54:20.27#ibcon#*before return 0, iclass 5, count 0 2006.197.07:54:20.27#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.197.07:54:20.27#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.197.07:54:20.27#ibcon#about to clear, iclass 5 cls_cnt 0 2006.197.07:54:20.27#ibcon#cleared, iclass 5 cls_cnt 0 2006.197.07:54:20.27$vc4f8/vb=1,4 2006.197.07:54:20.27#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.197.07:54:20.27#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.197.07:54:20.27#ibcon#ireg 11 cls_cnt 2 2006.197.07:54:20.27#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.197.07:54:20.27#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.197.07:54:20.27#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.197.07:54:20.27#ibcon#enter wrdev, iclass 7, count 2 2006.197.07:54:20.27#ibcon#first serial, iclass 7, count 2 2006.197.07:54:20.27#ibcon#enter sib2, iclass 7, count 2 2006.197.07:54:20.27#ibcon#flushed, iclass 7, count 2 2006.197.07:54:20.27#ibcon#about to write, iclass 7, count 2 2006.197.07:54:20.27#ibcon#wrote, iclass 7, count 2 2006.197.07:54:20.27#ibcon#about to read 3, iclass 7, count 2 2006.197.07:54:20.29#ibcon#read 3, iclass 7, count 2 2006.197.07:54:20.29#ibcon#about to read 4, iclass 7, count 2 2006.197.07:54:20.29#ibcon#read 4, iclass 7, count 2 2006.197.07:54:20.29#ibcon#about to read 5, iclass 7, count 2 2006.197.07:54:20.29#ibcon#read 5, iclass 7, count 2 2006.197.07:54:20.29#ibcon#about to read 6, iclass 7, count 2 2006.197.07:54:20.29#ibcon#read 6, iclass 7, count 2 2006.197.07:54:20.29#ibcon#end of sib2, iclass 7, count 2 2006.197.07:54:20.29#ibcon#*mode == 0, iclass 7, count 2 2006.197.07:54:20.29#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.197.07:54:20.29#ibcon#[27=AT01-04\r\n] 2006.197.07:54:20.29#ibcon#*before write, iclass 7, count 2 2006.197.07:54:20.29#ibcon#enter sib2, iclass 7, count 2 2006.197.07:54:20.29#ibcon#flushed, iclass 7, count 2 2006.197.07:54:20.29#ibcon#about to write, iclass 7, count 2 2006.197.07:54:20.29#ibcon#wrote, iclass 7, count 2 2006.197.07:54:20.29#ibcon#about to read 3, iclass 7, count 2 2006.197.07:54:20.32#ibcon#read 3, iclass 7, count 2 2006.197.07:54:20.32#ibcon#about to read 4, iclass 7, count 2 2006.197.07:54:20.32#ibcon#read 4, iclass 7, count 2 2006.197.07:54:20.32#ibcon#about to read 5, iclass 7, count 2 2006.197.07:54:20.32#ibcon#read 5, iclass 7, count 2 2006.197.07:54:20.32#ibcon#about to read 6, iclass 7, count 2 2006.197.07:54:20.32#ibcon#read 6, iclass 7, count 2 2006.197.07:54:20.32#ibcon#end of sib2, iclass 7, count 2 2006.197.07:54:20.32#ibcon#*after write, iclass 7, count 2 2006.197.07:54:20.32#ibcon#*before return 0, iclass 7, count 2 2006.197.07:54:20.32#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.197.07:54:20.32#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.197.07:54:20.32#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.197.07:54:20.32#ibcon#ireg 7 cls_cnt 0 2006.197.07:54:20.32#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.197.07:54:20.44#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.197.07:54:20.44#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.197.07:54:20.44#ibcon#enter wrdev, iclass 7, count 0 2006.197.07:54:20.44#ibcon#first serial, iclass 7, count 0 2006.197.07:54:20.44#ibcon#enter sib2, iclass 7, count 0 2006.197.07:54:20.44#ibcon#flushed, iclass 7, count 0 2006.197.07:54:20.44#ibcon#about to write, iclass 7, count 0 2006.197.07:54:20.44#ibcon#wrote, iclass 7, count 0 2006.197.07:54:20.44#ibcon#about to read 3, iclass 7, count 0 2006.197.07:54:20.46#ibcon#read 3, iclass 7, count 0 2006.197.07:54:20.46#ibcon#about to read 4, iclass 7, count 0 2006.197.07:54:20.46#ibcon#read 4, iclass 7, count 0 2006.197.07:54:20.46#ibcon#about to read 5, iclass 7, count 0 2006.197.07:54:20.46#ibcon#read 5, iclass 7, count 0 2006.197.07:54:20.46#ibcon#about to read 6, iclass 7, count 0 2006.197.07:54:20.46#ibcon#read 6, iclass 7, count 0 2006.197.07:54:20.46#ibcon#end of sib2, iclass 7, count 0 2006.197.07:54:20.46#ibcon#*mode == 0, iclass 7, count 0 2006.197.07:54:20.46#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.197.07:54:20.46#ibcon#[27=USB\r\n] 2006.197.07:54:20.46#ibcon#*before write, iclass 7, count 0 2006.197.07:54:20.46#ibcon#enter sib2, iclass 7, count 0 2006.197.07:54:20.46#ibcon#flushed, iclass 7, count 0 2006.197.07:54:20.46#ibcon#about to write, iclass 7, count 0 2006.197.07:54:20.46#ibcon#wrote, iclass 7, count 0 2006.197.07:54:20.46#ibcon#about to read 3, iclass 7, count 0 2006.197.07:54:20.49#ibcon#read 3, iclass 7, count 0 2006.197.07:54:20.49#ibcon#about to read 4, iclass 7, count 0 2006.197.07:54:20.49#ibcon#read 4, iclass 7, count 0 2006.197.07:54:20.49#ibcon#about to read 5, iclass 7, count 0 2006.197.07:54:20.49#ibcon#read 5, iclass 7, count 0 2006.197.07:54:20.49#ibcon#about to read 6, iclass 7, count 0 2006.197.07:54:20.49#ibcon#read 6, iclass 7, count 0 2006.197.07:54:20.49#ibcon#end of sib2, iclass 7, count 0 2006.197.07:54:20.49#ibcon#*after write, iclass 7, count 0 2006.197.07:54:20.49#ibcon#*before return 0, iclass 7, count 0 2006.197.07:54:20.49#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.197.07:54:20.49#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.197.07:54:20.49#ibcon#about to clear, iclass 7 cls_cnt 0 2006.197.07:54:20.49#ibcon#cleared, iclass 7 cls_cnt 0 2006.197.07:54:20.49$vc4f8/vblo=2,640.99 2006.197.07:54:20.49#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.197.07:54:20.49#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.197.07:54:20.49#ibcon#ireg 17 cls_cnt 0 2006.197.07:54:20.49#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.197.07:54:20.49#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.197.07:54:20.49#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.197.07:54:20.49#ibcon#enter wrdev, iclass 11, count 0 2006.197.07:54:20.49#ibcon#first serial, iclass 11, count 0 2006.197.07:54:20.49#ibcon#enter sib2, iclass 11, count 0 2006.197.07:54:20.49#ibcon#flushed, iclass 11, count 0 2006.197.07:54:20.49#ibcon#about to write, iclass 11, count 0 2006.197.07:54:20.49#ibcon#wrote, iclass 11, count 0 2006.197.07:54:20.49#ibcon#about to read 3, iclass 11, count 0 2006.197.07:54:20.51#ibcon#read 3, iclass 11, count 0 2006.197.07:54:20.51#ibcon#about to read 4, iclass 11, count 0 2006.197.07:54:20.51#ibcon#read 4, iclass 11, count 0 2006.197.07:54:20.51#ibcon#about to read 5, iclass 11, count 0 2006.197.07:54:20.51#ibcon#read 5, iclass 11, count 0 2006.197.07:54:20.51#ibcon#about to read 6, iclass 11, count 0 2006.197.07:54:20.51#ibcon#read 6, iclass 11, count 0 2006.197.07:54:20.51#ibcon#end of sib2, iclass 11, count 0 2006.197.07:54:20.51#ibcon#*mode == 0, iclass 11, count 0 2006.197.07:54:20.51#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.197.07:54:20.51#ibcon#[28=FRQ=02,640.99\r\n] 2006.197.07:54:20.51#ibcon#*before write, iclass 11, count 0 2006.197.07:54:20.51#ibcon#enter sib2, iclass 11, count 0 2006.197.07:54:20.51#ibcon#flushed, iclass 11, count 0 2006.197.07:54:20.51#ibcon#about to write, iclass 11, count 0 2006.197.07:54:20.51#ibcon#wrote, iclass 11, count 0 2006.197.07:54:20.51#ibcon#about to read 3, iclass 11, count 0 2006.197.07:54:20.55#ibcon#read 3, iclass 11, count 0 2006.197.07:54:20.55#ibcon#about to read 4, iclass 11, count 0 2006.197.07:54:20.55#ibcon#read 4, iclass 11, count 0 2006.197.07:54:20.55#ibcon#about to read 5, iclass 11, count 0 2006.197.07:54:20.55#ibcon#read 5, iclass 11, count 0 2006.197.07:54:20.55#ibcon#about to read 6, iclass 11, count 0 2006.197.07:54:20.55#ibcon#read 6, iclass 11, count 0 2006.197.07:54:20.55#ibcon#end of sib2, iclass 11, count 0 2006.197.07:54:20.55#ibcon#*after write, iclass 11, count 0 2006.197.07:54:20.55#ibcon#*before return 0, iclass 11, count 0 2006.197.07:54:20.55#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.197.07:54:20.55#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.197.07:54:20.55#ibcon#about to clear, iclass 11 cls_cnt 0 2006.197.07:54:20.55#ibcon#cleared, iclass 11 cls_cnt 0 2006.197.07:54:20.55$vc4f8/vb=2,4 2006.197.07:54:20.55#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.197.07:54:20.55#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.197.07:54:20.55#ibcon#ireg 11 cls_cnt 2 2006.197.07:54:20.55#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.197.07:54:20.61#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.197.07:54:20.61#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.197.07:54:20.61#ibcon#enter wrdev, iclass 13, count 2 2006.197.07:54:20.61#ibcon#first serial, iclass 13, count 2 2006.197.07:54:20.61#ibcon#enter sib2, iclass 13, count 2 2006.197.07:54:20.61#ibcon#flushed, iclass 13, count 2 2006.197.07:54:20.61#ibcon#about to write, iclass 13, count 2 2006.197.07:54:20.61#ibcon#wrote, iclass 13, count 2 2006.197.07:54:20.61#ibcon#about to read 3, iclass 13, count 2 2006.197.07:54:20.63#ibcon#read 3, iclass 13, count 2 2006.197.07:54:20.63#ibcon#about to read 4, iclass 13, count 2 2006.197.07:54:20.63#ibcon#read 4, iclass 13, count 2 2006.197.07:54:20.63#ibcon#about to read 5, iclass 13, count 2 2006.197.07:54:20.63#ibcon#read 5, iclass 13, count 2 2006.197.07:54:20.63#ibcon#about to read 6, iclass 13, count 2 2006.197.07:54:20.63#ibcon#read 6, iclass 13, count 2 2006.197.07:54:20.63#ibcon#end of sib2, iclass 13, count 2 2006.197.07:54:20.63#ibcon#*mode == 0, iclass 13, count 2 2006.197.07:54:20.63#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.197.07:54:20.63#ibcon#[27=AT02-04\r\n] 2006.197.07:54:20.63#ibcon#*before write, iclass 13, count 2 2006.197.07:54:20.63#ibcon#enter sib2, iclass 13, count 2 2006.197.07:54:20.63#ibcon#flushed, iclass 13, count 2 2006.197.07:54:20.63#ibcon#about to write, iclass 13, count 2 2006.197.07:54:20.63#ibcon#wrote, iclass 13, count 2 2006.197.07:54:20.63#ibcon#about to read 3, iclass 13, count 2 2006.197.07:54:20.66#ibcon#read 3, iclass 13, count 2 2006.197.07:54:20.66#ibcon#about to read 4, iclass 13, count 2 2006.197.07:54:20.66#ibcon#read 4, iclass 13, count 2 2006.197.07:54:20.66#ibcon#about to read 5, iclass 13, count 2 2006.197.07:54:20.66#ibcon#read 5, iclass 13, count 2 2006.197.07:54:20.66#ibcon#about to read 6, iclass 13, count 2 2006.197.07:54:20.66#ibcon#read 6, iclass 13, count 2 2006.197.07:54:20.66#ibcon#end of sib2, iclass 13, count 2 2006.197.07:54:20.66#ibcon#*after write, iclass 13, count 2 2006.197.07:54:20.66#ibcon#*before return 0, iclass 13, count 2 2006.197.07:54:20.66#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.197.07:54:20.66#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.197.07:54:20.66#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.197.07:54:20.66#ibcon#ireg 7 cls_cnt 0 2006.197.07:54:20.66#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.197.07:54:20.78#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.197.07:54:20.78#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.197.07:54:20.78#ibcon#enter wrdev, iclass 13, count 0 2006.197.07:54:20.78#ibcon#first serial, iclass 13, count 0 2006.197.07:54:20.78#ibcon#enter sib2, iclass 13, count 0 2006.197.07:54:20.78#ibcon#flushed, iclass 13, count 0 2006.197.07:54:20.78#ibcon#about to write, iclass 13, count 0 2006.197.07:54:20.78#ibcon#wrote, iclass 13, count 0 2006.197.07:54:20.78#ibcon#about to read 3, iclass 13, count 0 2006.197.07:54:20.80#ibcon#read 3, iclass 13, count 0 2006.197.07:54:20.80#ibcon#about to read 4, iclass 13, count 0 2006.197.07:54:20.80#ibcon#read 4, iclass 13, count 0 2006.197.07:54:20.80#ibcon#about to read 5, iclass 13, count 0 2006.197.07:54:20.80#ibcon#read 5, iclass 13, count 0 2006.197.07:54:20.80#ibcon#about to read 6, iclass 13, count 0 2006.197.07:54:20.80#ibcon#read 6, iclass 13, count 0 2006.197.07:54:20.80#ibcon#end of sib2, iclass 13, count 0 2006.197.07:54:20.80#ibcon#*mode == 0, iclass 13, count 0 2006.197.07:54:20.80#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.197.07:54:20.80#ibcon#[27=USB\r\n] 2006.197.07:54:20.80#ibcon#*before write, iclass 13, count 0 2006.197.07:54:20.80#ibcon#enter sib2, iclass 13, count 0 2006.197.07:54:20.80#ibcon#flushed, iclass 13, count 0 2006.197.07:54:20.80#ibcon#about to write, iclass 13, count 0 2006.197.07:54:20.80#ibcon#wrote, iclass 13, count 0 2006.197.07:54:20.80#ibcon#about to read 3, iclass 13, count 0 2006.197.07:54:20.83#ibcon#read 3, iclass 13, count 0 2006.197.07:54:20.83#ibcon#about to read 4, iclass 13, count 0 2006.197.07:54:20.83#ibcon#read 4, iclass 13, count 0 2006.197.07:54:20.83#ibcon#about to read 5, iclass 13, count 0 2006.197.07:54:20.83#ibcon#read 5, iclass 13, count 0 2006.197.07:54:20.83#ibcon#about to read 6, iclass 13, count 0 2006.197.07:54:20.83#ibcon#read 6, iclass 13, count 0 2006.197.07:54:20.83#ibcon#end of sib2, iclass 13, count 0 2006.197.07:54:20.83#ibcon#*after write, iclass 13, count 0 2006.197.07:54:20.83#ibcon#*before return 0, iclass 13, count 0 2006.197.07:54:20.83#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.197.07:54:20.83#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.197.07:54:20.83#ibcon#about to clear, iclass 13 cls_cnt 0 2006.197.07:54:20.83#ibcon#cleared, iclass 13 cls_cnt 0 2006.197.07:54:20.83$vc4f8/vblo=3,656.99 2006.197.07:54:20.83#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.197.07:54:20.83#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.197.07:54:20.83#ibcon#ireg 17 cls_cnt 0 2006.197.07:54:20.83#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.197.07:54:20.83#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.197.07:54:20.83#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.197.07:54:20.83#ibcon#enter wrdev, iclass 15, count 0 2006.197.07:54:20.83#ibcon#first serial, iclass 15, count 0 2006.197.07:54:20.83#ibcon#enter sib2, iclass 15, count 0 2006.197.07:54:20.83#ibcon#flushed, iclass 15, count 0 2006.197.07:54:20.83#ibcon#about to write, iclass 15, count 0 2006.197.07:54:20.83#ibcon#wrote, iclass 15, count 0 2006.197.07:54:20.83#ibcon#about to read 3, iclass 15, count 0 2006.197.07:54:20.85#ibcon#read 3, iclass 15, count 0 2006.197.07:54:20.85#ibcon#about to read 4, iclass 15, count 0 2006.197.07:54:20.85#ibcon#read 4, iclass 15, count 0 2006.197.07:54:20.85#ibcon#about to read 5, iclass 15, count 0 2006.197.07:54:20.85#ibcon#read 5, iclass 15, count 0 2006.197.07:54:20.85#ibcon#about to read 6, iclass 15, count 0 2006.197.07:54:20.85#ibcon#read 6, iclass 15, count 0 2006.197.07:54:20.85#ibcon#end of sib2, iclass 15, count 0 2006.197.07:54:20.85#ibcon#*mode == 0, iclass 15, count 0 2006.197.07:54:20.85#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.197.07:54:20.85#ibcon#[28=FRQ=03,656.99\r\n] 2006.197.07:54:20.85#ibcon#*before write, iclass 15, count 0 2006.197.07:54:20.85#ibcon#enter sib2, iclass 15, count 0 2006.197.07:54:20.85#ibcon#flushed, iclass 15, count 0 2006.197.07:54:20.85#ibcon#about to write, iclass 15, count 0 2006.197.07:54:20.85#ibcon#wrote, iclass 15, count 0 2006.197.07:54:20.85#ibcon#about to read 3, iclass 15, count 0 2006.197.07:54:20.89#ibcon#read 3, iclass 15, count 0 2006.197.07:54:20.89#ibcon#about to read 4, iclass 15, count 0 2006.197.07:54:20.89#ibcon#read 4, iclass 15, count 0 2006.197.07:54:20.89#ibcon#about to read 5, iclass 15, count 0 2006.197.07:54:20.89#ibcon#read 5, iclass 15, count 0 2006.197.07:54:20.89#ibcon#about to read 6, iclass 15, count 0 2006.197.07:54:20.89#ibcon#read 6, iclass 15, count 0 2006.197.07:54:20.89#ibcon#end of sib2, iclass 15, count 0 2006.197.07:54:20.89#ibcon#*after write, iclass 15, count 0 2006.197.07:54:20.89#ibcon#*before return 0, iclass 15, count 0 2006.197.07:54:20.89#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.197.07:54:20.89#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.197.07:54:20.89#ibcon#about to clear, iclass 15 cls_cnt 0 2006.197.07:54:20.89#ibcon#cleared, iclass 15 cls_cnt 0 2006.197.07:54:20.89$vc4f8/vb=3,4 2006.197.07:54:20.89#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.197.07:54:20.89#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.197.07:54:20.89#ibcon#ireg 11 cls_cnt 2 2006.197.07:54:20.89#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.197.07:54:20.95#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.197.07:54:20.95#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.197.07:54:20.95#ibcon#enter wrdev, iclass 17, count 2 2006.197.07:54:20.95#ibcon#first serial, iclass 17, count 2 2006.197.07:54:20.95#ibcon#enter sib2, iclass 17, count 2 2006.197.07:54:20.95#ibcon#flushed, iclass 17, count 2 2006.197.07:54:20.95#ibcon#about to write, iclass 17, count 2 2006.197.07:54:20.95#ibcon#wrote, iclass 17, count 2 2006.197.07:54:20.95#ibcon#about to read 3, iclass 17, count 2 2006.197.07:54:20.97#ibcon#read 3, iclass 17, count 2 2006.197.07:54:20.97#ibcon#about to read 4, iclass 17, count 2 2006.197.07:54:20.97#ibcon#read 4, iclass 17, count 2 2006.197.07:54:20.97#ibcon#about to read 5, iclass 17, count 2 2006.197.07:54:20.97#ibcon#read 5, iclass 17, count 2 2006.197.07:54:20.97#ibcon#about to read 6, iclass 17, count 2 2006.197.07:54:20.97#ibcon#read 6, iclass 17, count 2 2006.197.07:54:20.97#ibcon#end of sib2, iclass 17, count 2 2006.197.07:54:20.97#ibcon#*mode == 0, iclass 17, count 2 2006.197.07:54:20.97#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.197.07:54:20.97#ibcon#[27=AT03-04\r\n] 2006.197.07:54:20.97#ibcon#*before write, iclass 17, count 2 2006.197.07:54:20.97#ibcon#enter sib2, iclass 17, count 2 2006.197.07:54:20.97#ibcon#flushed, iclass 17, count 2 2006.197.07:54:20.97#ibcon#about to write, iclass 17, count 2 2006.197.07:54:20.97#ibcon#wrote, iclass 17, count 2 2006.197.07:54:20.97#ibcon#about to read 3, iclass 17, count 2 2006.197.07:54:21.00#ibcon#read 3, iclass 17, count 2 2006.197.07:54:21.00#ibcon#about to read 4, iclass 17, count 2 2006.197.07:54:21.00#ibcon#read 4, iclass 17, count 2 2006.197.07:54:21.00#ibcon#about to read 5, iclass 17, count 2 2006.197.07:54:21.00#ibcon#read 5, iclass 17, count 2 2006.197.07:54:21.00#ibcon#about to read 6, iclass 17, count 2 2006.197.07:54:21.00#ibcon#read 6, iclass 17, count 2 2006.197.07:54:21.00#ibcon#end of sib2, iclass 17, count 2 2006.197.07:54:21.00#ibcon#*after write, iclass 17, count 2 2006.197.07:54:21.00#ibcon#*before return 0, iclass 17, count 2 2006.197.07:54:21.00#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.197.07:54:21.00#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.197.07:54:21.00#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.197.07:54:21.00#ibcon#ireg 7 cls_cnt 0 2006.197.07:54:21.00#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.197.07:54:21.12#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.197.07:54:21.12#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.197.07:54:21.12#ibcon#enter wrdev, iclass 17, count 0 2006.197.07:54:21.12#ibcon#first serial, iclass 17, count 0 2006.197.07:54:21.12#ibcon#enter sib2, iclass 17, count 0 2006.197.07:54:21.12#ibcon#flushed, iclass 17, count 0 2006.197.07:54:21.12#ibcon#about to write, iclass 17, count 0 2006.197.07:54:21.12#ibcon#wrote, iclass 17, count 0 2006.197.07:54:21.12#ibcon#about to read 3, iclass 17, count 0 2006.197.07:54:21.14#ibcon#read 3, iclass 17, count 0 2006.197.07:54:21.14#ibcon#about to read 4, iclass 17, count 0 2006.197.07:54:21.14#ibcon#read 4, iclass 17, count 0 2006.197.07:54:21.14#ibcon#about to read 5, iclass 17, count 0 2006.197.07:54:21.14#ibcon#read 5, iclass 17, count 0 2006.197.07:54:21.14#ibcon#about to read 6, iclass 17, count 0 2006.197.07:54:21.14#ibcon#read 6, iclass 17, count 0 2006.197.07:54:21.14#ibcon#end of sib2, iclass 17, count 0 2006.197.07:54:21.14#ibcon#*mode == 0, iclass 17, count 0 2006.197.07:54:21.14#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.197.07:54:21.14#ibcon#[27=USB\r\n] 2006.197.07:54:21.14#ibcon#*before write, iclass 17, count 0 2006.197.07:54:21.14#ibcon#enter sib2, iclass 17, count 0 2006.197.07:54:21.14#ibcon#flushed, iclass 17, count 0 2006.197.07:54:21.14#ibcon#about to write, iclass 17, count 0 2006.197.07:54:21.14#ibcon#wrote, iclass 17, count 0 2006.197.07:54:21.14#ibcon#about to read 3, iclass 17, count 0 2006.197.07:54:21.17#ibcon#read 3, iclass 17, count 0 2006.197.07:54:21.17#ibcon#about to read 4, iclass 17, count 0 2006.197.07:54:21.17#ibcon#read 4, iclass 17, count 0 2006.197.07:54:21.17#ibcon#about to read 5, iclass 17, count 0 2006.197.07:54:21.17#ibcon#read 5, iclass 17, count 0 2006.197.07:54:21.17#ibcon#about to read 6, iclass 17, count 0 2006.197.07:54:21.17#ibcon#read 6, iclass 17, count 0 2006.197.07:54:21.17#ibcon#end of sib2, iclass 17, count 0 2006.197.07:54:21.17#ibcon#*after write, iclass 17, count 0 2006.197.07:54:21.17#ibcon#*before return 0, iclass 17, count 0 2006.197.07:54:21.17#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.197.07:54:21.17#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.197.07:54:21.17#ibcon#about to clear, iclass 17 cls_cnt 0 2006.197.07:54:21.17#ibcon#cleared, iclass 17 cls_cnt 0 2006.197.07:54:21.17$vc4f8/vblo=4,712.99 2006.197.07:54:21.17#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.197.07:54:21.17#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.197.07:54:21.17#ibcon#ireg 17 cls_cnt 0 2006.197.07:54:21.17#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.197.07:54:21.17#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.197.07:54:21.17#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.197.07:54:21.17#ibcon#enter wrdev, iclass 19, count 0 2006.197.07:54:21.17#ibcon#first serial, iclass 19, count 0 2006.197.07:54:21.17#ibcon#enter sib2, iclass 19, count 0 2006.197.07:54:21.17#ibcon#flushed, iclass 19, count 0 2006.197.07:54:21.17#ibcon#about to write, iclass 19, count 0 2006.197.07:54:21.17#ibcon#wrote, iclass 19, count 0 2006.197.07:54:21.17#ibcon#about to read 3, iclass 19, count 0 2006.197.07:54:21.19#ibcon#read 3, iclass 19, count 0 2006.197.07:54:21.19#ibcon#about to read 4, iclass 19, count 0 2006.197.07:54:21.19#ibcon#read 4, iclass 19, count 0 2006.197.07:54:21.19#ibcon#about to read 5, iclass 19, count 0 2006.197.07:54:21.19#ibcon#read 5, iclass 19, count 0 2006.197.07:54:21.19#ibcon#about to read 6, iclass 19, count 0 2006.197.07:54:21.19#ibcon#read 6, iclass 19, count 0 2006.197.07:54:21.19#ibcon#end of sib2, iclass 19, count 0 2006.197.07:54:21.19#ibcon#*mode == 0, iclass 19, count 0 2006.197.07:54:21.19#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.197.07:54:21.19#ibcon#[28=FRQ=04,712.99\r\n] 2006.197.07:54:21.19#ibcon#*before write, iclass 19, count 0 2006.197.07:54:21.19#ibcon#enter sib2, iclass 19, count 0 2006.197.07:54:21.19#ibcon#flushed, iclass 19, count 0 2006.197.07:54:21.19#ibcon#about to write, iclass 19, count 0 2006.197.07:54:21.19#ibcon#wrote, iclass 19, count 0 2006.197.07:54:21.19#ibcon#about to read 3, iclass 19, count 0 2006.197.07:54:21.23#ibcon#read 3, iclass 19, count 0 2006.197.07:54:21.23#ibcon#about to read 4, iclass 19, count 0 2006.197.07:54:21.23#ibcon#read 4, iclass 19, count 0 2006.197.07:54:21.23#ibcon#about to read 5, iclass 19, count 0 2006.197.07:54:21.23#ibcon#read 5, iclass 19, count 0 2006.197.07:54:21.23#ibcon#about to read 6, iclass 19, count 0 2006.197.07:54:21.23#ibcon#read 6, iclass 19, count 0 2006.197.07:54:21.23#ibcon#end of sib2, iclass 19, count 0 2006.197.07:54:21.23#ibcon#*after write, iclass 19, count 0 2006.197.07:54:21.23#ibcon#*before return 0, iclass 19, count 0 2006.197.07:54:21.23#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.197.07:54:21.23#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.197.07:54:21.23#ibcon#about to clear, iclass 19 cls_cnt 0 2006.197.07:54:21.23#ibcon#cleared, iclass 19 cls_cnt 0 2006.197.07:54:21.23$vc4f8/vb=4,4 2006.197.07:54:21.23#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.197.07:54:21.23#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.197.07:54:21.23#ibcon#ireg 11 cls_cnt 2 2006.197.07:54:21.23#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.197.07:54:21.29#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.197.07:54:21.29#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.197.07:54:21.29#ibcon#enter wrdev, iclass 21, count 2 2006.197.07:54:21.29#ibcon#first serial, iclass 21, count 2 2006.197.07:54:21.29#ibcon#enter sib2, iclass 21, count 2 2006.197.07:54:21.29#ibcon#flushed, iclass 21, count 2 2006.197.07:54:21.29#ibcon#about to write, iclass 21, count 2 2006.197.07:54:21.29#ibcon#wrote, iclass 21, count 2 2006.197.07:54:21.29#ibcon#about to read 3, iclass 21, count 2 2006.197.07:54:21.31#ibcon#read 3, iclass 21, count 2 2006.197.07:54:21.31#ibcon#about to read 4, iclass 21, count 2 2006.197.07:54:21.31#ibcon#read 4, iclass 21, count 2 2006.197.07:54:21.31#ibcon#about to read 5, iclass 21, count 2 2006.197.07:54:21.31#ibcon#read 5, iclass 21, count 2 2006.197.07:54:21.31#ibcon#about to read 6, iclass 21, count 2 2006.197.07:54:21.31#ibcon#read 6, iclass 21, count 2 2006.197.07:54:21.31#ibcon#end of sib2, iclass 21, count 2 2006.197.07:54:21.31#ibcon#*mode == 0, iclass 21, count 2 2006.197.07:54:21.31#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.197.07:54:21.31#ibcon#[27=AT04-04\r\n] 2006.197.07:54:21.31#ibcon#*before write, iclass 21, count 2 2006.197.07:54:21.31#ibcon#enter sib2, iclass 21, count 2 2006.197.07:54:21.31#ibcon#flushed, iclass 21, count 2 2006.197.07:54:21.31#ibcon#about to write, iclass 21, count 2 2006.197.07:54:21.31#ibcon#wrote, iclass 21, count 2 2006.197.07:54:21.31#ibcon#about to read 3, iclass 21, count 2 2006.197.07:54:21.34#ibcon#read 3, iclass 21, count 2 2006.197.07:54:21.34#ibcon#about to read 4, iclass 21, count 2 2006.197.07:54:21.34#ibcon#read 4, iclass 21, count 2 2006.197.07:54:21.34#ibcon#about to read 5, iclass 21, count 2 2006.197.07:54:21.34#ibcon#read 5, iclass 21, count 2 2006.197.07:54:21.34#ibcon#about to read 6, iclass 21, count 2 2006.197.07:54:21.34#ibcon#read 6, iclass 21, count 2 2006.197.07:54:21.34#ibcon#end of sib2, iclass 21, count 2 2006.197.07:54:21.34#ibcon#*after write, iclass 21, count 2 2006.197.07:54:21.34#ibcon#*before return 0, iclass 21, count 2 2006.197.07:54:21.34#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.197.07:54:21.34#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.197.07:54:21.34#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.197.07:54:21.34#ibcon#ireg 7 cls_cnt 0 2006.197.07:54:21.34#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.197.07:54:21.46#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.197.07:54:21.46#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.197.07:54:21.46#ibcon#enter wrdev, iclass 21, count 0 2006.197.07:54:21.46#ibcon#first serial, iclass 21, count 0 2006.197.07:54:21.46#ibcon#enter sib2, iclass 21, count 0 2006.197.07:54:21.46#ibcon#flushed, iclass 21, count 0 2006.197.07:54:21.46#ibcon#about to write, iclass 21, count 0 2006.197.07:54:21.46#ibcon#wrote, iclass 21, count 0 2006.197.07:54:21.46#ibcon#about to read 3, iclass 21, count 0 2006.197.07:54:21.48#ibcon#read 3, iclass 21, count 0 2006.197.07:54:21.48#ibcon#about to read 4, iclass 21, count 0 2006.197.07:54:21.48#ibcon#read 4, iclass 21, count 0 2006.197.07:54:21.48#ibcon#about to read 5, iclass 21, count 0 2006.197.07:54:21.48#ibcon#read 5, iclass 21, count 0 2006.197.07:54:21.48#ibcon#about to read 6, iclass 21, count 0 2006.197.07:54:21.48#ibcon#read 6, iclass 21, count 0 2006.197.07:54:21.48#ibcon#end of sib2, iclass 21, count 0 2006.197.07:54:21.48#ibcon#*mode == 0, iclass 21, count 0 2006.197.07:54:21.48#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.197.07:54:21.48#ibcon#[27=USB\r\n] 2006.197.07:54:21.48#ibcon#*before write, iclass 21, count 0 2006.197.07:54:21.48#ibcon#enter sib2, iclass 21, count 0 2006.197.07:54:21.48#ibcon#flushed, iclass 21, count 0 2006.197.07:54:21.48#ibcon#about to write, iclass 21, count 0 2006.197.07:54:21.48#ibcon#wrote, iclass 21, count 0 2006.197.07:54:21.48#ibcon#about to read 3, iclass 21, count 0 2006.197.07:54:21.51#ibcon#read 3, iclass 21, count 0 2006.197.07:54:21.51#ibcon#about to read 4, iclass 21, count 0 2006.197.07:54:21.51#ibcon#read 4, iclass 21, count 0 2006.197.07:54:21.51#ibcon#about to read 5, iclass 21, count 0 2006.197.07:54:21.51#ibcon#read 5, iclass 21, count 0 2006.197.07:54:21.51#ibcon#about to read 6, iclass 21, count 0 2006.197.07:54:21.51#ibcon#read 6, iclass 21, count 0 2006.197.07:54:21.51#ibcon#end of sib2, iclass 21, count 0 2006.197.07:54:21.51#ibcon#*after write, iclass 21, count 0 2006.197.07:54:21.51#ibcon#*before return 0, iclass 21, count 0 2006.197.07:54:21.51#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.197.07:54:21.51#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.197.07:54:21.51#ibcon#about to clear, iclass 21 cls_cnt 0 2006.197.07:54:21.51#ibcon#cleared, iclass 21 cls_cnt 0 2006.197.07:54:21.51$vc4f8/vblo=5,744.99 2006.197.07:54:21.51#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.197.07:54:21.51#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.197.07:54:21.51#ibcon#ireg 17 cls_cnt 0 2006.197.07:54:21.51#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.197.07:54:21.51#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.197.07:54:21.51#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.197.07:54:21.51#ibcon#enter wrdev, iclass 23, count 0 2006.197.07:54:21.51#ibcon#first serial, iclass 23, count 0 2006.197.07:54:21.51#ibcon#enter sib2, iclass 23, count 0 2006.197.07:54:21.51#ibcon#flushed, iclass 23, count 0 2006.197.07:54:21.51#ibcon#about to write, iclass 23, count 0 2006.197.07:54:21.51#ibcon#wrote, iclass 23, count 0 2006.197.07:54:21.51#ibcon#about to read 3, iclass 23, count 0 2006.197.07:54:21.53#ibcon#read 3, iclass 23, count 0 2006.197.07:54:21.53#ibcon#about to read 4, iclass 23, count 0 2006.197.07:54:21.53#ibcon#read 4, iclass 23, count 0 2006.197.07:54:21.53#ibcon#about to read 5, iclass 23, count 0 2006.197.07:54:21.53#ibcon#read 5, iclass 23, count 0 2006.197.07:54:21.53#ibcon#about to read 6, iclass 23, count 0 2006.197.07:54:21.53#ibcon#read 6, iclass 23, count 0 2006.197.07:54:21.53#ibcon#end of sib2, iclass 23, count 0 2006.197.07:54:21.53#ibcon#*mode == 0, iclass 23, count 0 2006.197.07:54:21.53#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.197.07:54:21.53#ibcon#[28=FRQ=05,744.99\r\n] 2006.197.07:54:21.53#ibcon#*before write, iclass 23, count 0 2006.197.07:54:21.53#ibcon#enter sib2, iclass 23, count 0 2006.197.07:54:21.53#ibcon#flushed, iclass 23, count 0 2006.197.07:54:21.53#ibcon#about to write, iclass 23, count 0 2006.197.07:54:21.53#ibcon#wrote, iclass 23, count 0 2006.197.07:54:21.53#ibcon#about to read 3, iclass 23, count 0 2006.197.07:54:21.57#ibcon#read 3, iclass 23, count 0 2006.197.07:54:21.57#ibcon#about to read 4, iclass 23, count 0 2006.197.07:54:21.57#ibcon#read 4, iclass 23, count 0 2006.197.07:54:21.57#ibcon#about to read 5, iclass 23, count 0 2006.197.07:54:21.57#ibcon#read 5, iclass 23, count 0 2006.197.07:54:21.57#ibcon#about to read 6, iclass 23, count 0 2006.197.07:54:21.57#ibcon#read 6, iclass 23, count 0 2006.197.07:54:21.57#ibcon#end of sib2, iclass 23, count 0 2006.197.07:54:21.57#ibcon#*after write, iclass 23, count 0 2006.197.07:54:21.57#ibcon#*before return 0, iclass 23, count 0 2006.197.07:54:21.57#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.197.07:54:21.57#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.197.07:54:21.57#ibcon#about to clear, iclass 23 cls_cnt 0 2006.197.07:54:21.57#ibcon#cleared, iclass 23 cls_cnt 0 2006.197.07:54:21.57$vc4f8/vb=5,4 2006.197.07:54:21.57#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.197.07:54:21.57#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.197.07:54:21.57#ibcon#ireg 11 cls_cnt 2 2006.197.07:54:21.57#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.197.07:54:21.63#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.197.07:54:21.63#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.197.07:54:21.63#ibcon#enter wrdev, iclass 25, count 2 2006.197.07:54:21.63#ibcon#first serial, iclass 25, count 2 2006.197.07:54:21.63#ibcon#enter sib2, iclass 25, count 2 2006.197.07:54:21.63#ibcon#flushed, iclass 25, count 2 2006.197.07:54:21.63#ibcon#about to write, iclass 25, count 2 2006.197.07:54:21.63#ibcon#wrote, iclass 25, count 2 2006.197.07:54:21.63#ibcon#about to read 3, iclass 25, count 2 2006.197.07:54:21.65#ibcon#read 3, iclass 25, count 2 2006.197.07:54:21.65#ibcon#about to read 4, iclass 25, count 2 2006.197.07:54:21.65#ibcon#read 4, iclass 25, count 2 2006.197.07:54:21.65#ibcon#about to read 5, iclass 25, count 2 2006.197.07:54:21.65#ibcon#read 5, iclass 25, count 2 2006.197.07:54:21.65#ibcon#about to read 6, iclass 25, count 2 2006.197.07:54:21.65#ibcon#read 6, iclass 25, count 2 2006.197.07:54:21.65#ibcon#end of sib2, iclass 25, count 2 2006.197.07:54:21.65#ibcon#*mode == 0, iclass 25, count 2 2006.197.07:54:21.65#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.197.07:54:21.65#ibcon#[27=AT05-04\r\n] 2006.197.07:54:21.65#ibcon#*before write, iclass 25, count 2 2006.197.07:54:21.65#ibcon#enter sib2, iclass 25, count 2 2006.197.07:54:21.65#ibcon#flushed, iclass 25, count 2 2006.197.07:54:21.65#ibcon#about to write, iclass 25, count 2 2006.197.07:54:21.65#ibcon#wrote, iclass 25, count 2 2006.197.07:54:21.65#ibcon#about to read 3, iclass 25, count 2 2006.197.07:54:21.68#ibcon#read 3, iclass 25, count 2 2006.197.07:54:21.68#ibcon#about to read 4, iclass 25, count 2 2006.197.07:54:21.68#ibcon#read 4, iclass 25, count 2 2006.197.07:54:21.68#ibcon#about to read 5, iclass 25, count 2 2006.197.07:54:21.68#ibcon#read 5, iclass 25, count 2 2006.197.07:54:21.68#ibcon#about to read 6, iclass 25, count 2 2006.197.07:54:21.68#ibcon#read 6, iclass 25, count 2 2006.197.07:54:21.68#ibcon#end of sib2, iclass 25, count 2 2006.197.07:54:21.68#ibcon#*after write, iclass 25, count 2 2006.197.07:54:21.68#ibcon#*before return 0, iclass 25, count 2 2006.197.07:54:21.68#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.197.07:54:21.68#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.197.07:54:21.68#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.197.07:54:21.68#ibcon#ireg 7 cls_cnt 0 2006.197.07:54:21.68#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.197.07:54:21.74#abcon#<5=/05 3.0 5.2 25.77 971003.1\r\n> 2006.197.07:54:21.76#abcon#{5=INTERFACE CLEAR} 2006.197.07:54:21.80#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.197.07:54:21.80#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.197.07:54:21.80#ibcon#enter wrdev, iclass 25, count 0 2006.197.07:54:21.80#ibcon#first serial, iclass 25, count 0 2006.197.07:54:21.80#ibcon#enter sib2, iclass 25, count 0 2006.197.07:54:21.80#ibcon#flushed, iclass 25, count 0 2006.197.07:54:21.80#ibcon#about to write, iclass 25, count 0 2006.197.07:54:21.80#ibcon#wrote, iclass 25, count 0 2006.197.07:54:21.80#ibcon#about to read 3, iclass 25, count 0 2006.197.07:54:21.82#ibcon#read 3, iclass 25, count 0 2006.197.07:54:21.82#ibcon#about to read 4, iclass 25, count 0 2006.197.07:54:21.82#ibcon#read 4, iclass 25, count 0 2006.197.07:54:21.82#ibcon#about to read 5, iclass 25, count 0 2006.197.07:54:21.82#ibcon#read 5, iclass 25, count 0 2006.197.07:54:21.82#ibcon#about to read 6, iclass 25, count 0 2006.197.07:54:21.82#ibcon#read 6, iclass 25, count 0 2006.197.07:54:21.82#ibcon#end of sib2, iclass 25, count 0 2006.197.07:54:21.82#ibcon#*mode == 0, iclass 25, count 0 2006.197.07:54:21.82#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.197.07:54:21.82#ibcon#[27=USB\r\n] 2006.197.07:54:21.82#ibcon#*before write, iclass 25, count 0 2006.197.07:54:21.82#ibcon#enter sib2, iclass 25, count 0 2006.197.07:54:21.82#ibcon#flushed, iclass 25, count 0 2006.197.07:54:21.82#ibcon#about to write, iclass 25, count 0 2006.197.07:54:21.82#ibcon#wrote, iclass 25, count 0 2006.197.07:54:21.82#ibcon#about to read 3, iclass 25, count 0 2006.197.07:54:21.82#abcon#[5=S1D000X0/0*\r\n] 2006.197.07:54:21.85#ibcon#read 3, iclass 25, count 0 2006.197.07:54:21.85#ibcon#about to read 4, iclass 25, count 0 2006.197.07:54:21.85#ibcon#read 4, iclass 25, count 0 2006.197.07:54:21.85#ibcon#about to read 5, iclass 25, count 0 2006.197.07:54:21.85#ibcon#read 5, iclass 25, count 0 2006.197.07:54:21.85#ibcon#about to read 6, iclass 25, count 0 2006.197.07:54:21.85#ibcon#read 6, iclass 25, count 0 2006.197.07:54:21.85#ibcon#end of sib2, iclass 25, count 0 2006.197.07:54:21.85#ibcon#*after write, iclass 25, count 0 2006.197.07:54:21.85#ibcon#*before return 0, iclass 25, count 0 2006.197.07:54:21.85#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.197.07:54:21.85#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.197.07:54:21.85#ibcon#about to clear, iclass 25 cls_cnt 0 2006.197.07:54:21.85#ibcon#cleared, iclass 25 cls_cnt 0 2006.197.07:54:21.85$vc4f8/vblo=6,752.99 2006.197.07:54:21.85#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.197.07:54:21.85#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.197.07:54:21.85#ibcon#ireg 17 cls_cnt 0 2006.197.07:54:21.85#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.197.07:54:21.85#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.197.07:54:21.85#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.197.07:54:21.85#ibcon#enter wrdev, iclass 31, count 0 2006.197.07:54:21.85#ibcon#first serial, iclass 31, count 0 2006.197.07:54:21.85#ibcon#enter sib2, iclass 31, count 0 2006.197.07:54:21.85#ibcon#flushed, iclass 31, count 0 2006.197.07:54:21.85#ibcon#about to write, iclass 31, count 0 2006.197.07:54:21.85#ibcon#wrote, iclass 31, count 0 2006.197.07:54:21.85#ibcon#about to read 3, iclass 31, count 0 2006.197.07:54:21.87#ibcon#read 3, iclass 31, count 0 2006.197.07:54:21.87#ibcon#about to read 4, iclass 31, count 0 2006.197.07:54:21.87#ibcon#read 4, iclass 31, count 0 2006.197.07:54:21.87#ibcon#about to read 5, iclass 31, count 0 2006.197.07:54:21.87#ibcon#read 5, iclass 31, count 0 2006.197.07:54:21.87#ibcon#about to read 6, iclass 31, count 0 2006.197.07:54:21.87#ibcon#read 6, iclass 31, count 0 2006.197.07:54:21.87#ibcon#end of sib2, iclass 31, count 0 2006.197.07:54:21.87#ibcon#*mode == 0, iclass 31, count 0 2006.197.07:54:21.87#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.197.07:54:21.87#ibcon#[28=FRQ=06,752.99\r\n] 2006.197.07:54:21.87#ibcon#*before write, iclass 31, count 0 2006.197.07:54:21.87#ibcon#enter sib2, iclass 31, count 0 2006.197.07:54:21.87#ibcon#flushed, iclass 31, count 0 2006.197.07:54:21.87#ibcon#about to write, iclass 31, count 0 2006.197.07:54:21.87#ibcon#wrote, iclass 31, count 0 2006.197.07:54:21.87#ibcon#about to read 3, iclass 31, count 0 2006.197.07:54:21.91#ibcon#read 3, iclass 31, count 0 2006.197.07:54:21.91#ibcon#about to read 4, iclass 31, count 0 2006.197.07:54:21.91#ibcon#read 4, iclass 31, count 0 2006.197.07:54:21.91#ibcon#about to read 5, iclass 31, count 0 2006.197.07:54:21.91#ibcon#read 5, iclass 31, count 0 2006.197.07:54:21.91#ibcon#about to read 6, iclass 31, count 0 2006.197.07:54:21.91#ibcon#read 6, iclass 31, count 0 2006.197.07:54:21.91#ibcon#end of sib2, iclass 31, count 0 2006.197.07:54:21.91#ibcon#*after write, iclass 31, count 0 2006.197.07:54:21.91#ibcon#*before return 0, iclass 31, count 0 2006.197.07:54:21.91#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.197.07:54:21.91#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.197.07:54:21.91#ibcon#about to clear, iclass 31 cls_cnt 0 2006.197.07:54:21.91#ibcon#cleared, iclass 31 cls_cnt 0 2006.197.07:54:21.91$vc4f8/vb=6,4 2006.197.07:54:21.91#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.197.07:54:21.91#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.197.07:54:21.91#ibcon#ireg 11 cls_cnt 2 2006.197.07:54:21.91#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.197.07:54:21.97#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.197.07:54:21.97#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.197.07:54:21.97#ibcon#enter wrdev, iclass 33, count 2 2006.197.07:54:21.97#ibcon#first serial, iclass 33, count 2 2006.197.07:54:21.97#ibcon#enter sib2, iclass 33, count 2 2006.197.07:54:21.97#ibcon#flushed, iclass 33, count 2 2006.197.07:54:21.97#ibcon#about to write, iclass 33, count 2 2006.197.07:54:21.97#ibcon#wrote, iclass 33, count 2 2006.197.07:54:21.97#ibcon#about to read 3, iclass 33, count 2 2006.197.07:54:21.99#ibcon#read 3, iclass 33, count 2 2006.197.07:54:21.99#ibcon#about to read 4, iclass 33, count 2 2006.197.07:54:21.99#ibcon#read 4, iclass 33, count 2 2006.197.07:54:21.99#ibcon#about to read 5, iclass 33, count 2 2006.197.07:54:21.99#ibcon#read 5, iclass 33, count 2 2006.197.07:54:21.99#ibcon#about to read 6, iclass 33, count 2 2006.197.07:54:21.99#ibcon#read 6, iclass 33, count 2 2006.197.07:54:21.99#ibcon#end of sib2, iclass 33, count 2 2006.197.07:54:21.99#ibcon#*mode == 0, iclass 33, count 2 2006.197.07:54:21.99#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.197.07:54:21.99#ibcon#[27=AT06-04\r\n] 2006.197.07:54:21.99#ibcon#*before write, iclass 33, count 2 2006.197.07:54:21.99#ibcon#enter sib2, iclass 33, count 2 2006.197.07:54:21.99#ibcon#flushed, iclass 33, count 2 2006.197.07:54:21.99#ibcon#about to write, iclass 33, count 2 2006.197.07:54:21.99#ibcon#wrote, iclass 33, count 2 2006.197.07:54:21.99#ibcon#about to read 3, iclass 33, count 2 2006.197.07:54:22.02#ibcon#read 3, iclass 33, count 2 2006.197.07:54:22.02#ibcon#about to read 4, iclass 33, count 2 2006.197.07:54:22.02#ibcon#read 4, iclass 33, count 2 2006.197.07:54:22.02#ibcon#about to read 5, iclass 33, count 2 2006.197.07:54:22.02#ibcon#read 5, iclass 33, count 2 2006.197.07:54:22.02#ibcon#about to read 6, iclass 33, count 2 2006.197.07:54:22.02#ibcon#read 6, iclass 33, count 2 2006.197.07:54:22.02#ibcon#end of sib2, iclass 33, count 2 2006.197.07:54:22.02#ibcon#*after write, iclass 33, count 2 2006.197.07:54:22.02#ibcon#*before return 0, iclass 33, count 2 2006.197.07:54:22.02#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.197.07:54:22.02#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.197.07:54:22.02#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.197.07:54:22.02#ibcon#ireg 7 cls_cnt 0 2006.197.07:54:22.02#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.197.07:54:22.14#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.197.07:54:22.14#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.197.07:54:22.14#ibcon#enter wrdev, iclass 33, count 0 2006.197.07:54:22.14#ibcon#first serial, iclass 33, count 0 2006.197.07:54:22.14#ibcon#enter sib2, iclass 33, count 0 2006.197.07:54:22.14#ibcon#flushed, iclass 33, count 0 2006.197.07:54:22.14#ibcon#about to write, iclass 33, count 0 2006.197.07:54:22.14#ibcon#wrote, iclass 33, count 0 2006.197.07:54:22.14#ibcon#about to read 3, iclass 33, count 0 2006.197.07:54:22.16#ibcon#read 3, iclass 33, count 0 2006.197.07:54:22.16#ibcon#about to read 4, iclass 33, count 0 2006.197.07:54:22.16#ibcon#read 4, iclass 33, count 0 2006.197.07:54:22.16#ibcon#about to read 5, iclass 33, count 0 2006.197.07:54:22.16#ibcon#read 5, iclass 33, count 0 2006.197.07:54:22.16#ibcon#about to read 6, iclass 33, count 0 2006.197.07:54:22.16#ibcon#read 6, iclass 33, count 0 2006.197.07:54:22.16#ibcon#end of sib2, iclass 33, count 0 2006.197.07:54:22.16#ibcon#*mode == 0, iclass 33, count 0 2006.197.07:54:22.16#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.197.07:54:22.16#ibcon#[27=USB\r\n] 2006.197.07:54:22.16#ibcon#*before write, iclass 33, count 0 2006.197.07:54:22.16#ibcon#enter sib2, iclass 33, count 0 2006.197.07:54:22.16#ibcon#flushed, iclass 33, count 0 2006.197.07:54:22.16#ibcon#about to write, iclass 33, count 0 2006.197.07:54:22.16#ibcon#wrote, iclass 33, count 0 2006.197.07:54:22.16#ibcon#about to read 3, iclass 33, count 0 2006.197.07:54:22.19#ibcon#read 3, iclass 33, count 0 2006.197.07:54:22.19#ibcon#about to read 4, iclass 33, count 0 2006.197.07:54:22.19#ibcon#read 4, iclass 33, count 0 2006.197.07:54:22.19#ibcon#about to read 5, iclass 33, count 0 2006.197.07:54:22.19#ibcon#read 5, iclass 33, count 0 2006.197.07:54:22.19#ibcon#about to read 6, iclass 33, count 0 2006.197.07:54:22.19#ibcon#read 6, iclass 33, count 0 2006.197.07:54:22.19#ibcon#end of sib2, iclass 33, count 0 2006.197.07:54:22.19#ibcon#*after write, iclass 33, count 0 2006.197.07:54:22.19#ibcon#*before return 0, iclass 33, count 0 2006.197.07:54:22.19#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.197.07:54:22.19#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.197.07:54:22.19#ibcon#about to clear, iclass 33 cls_cnt 0 2006.197.07:54:22.19#ibcon#cleared, iclass 33 cls_cnt 0 2006.197.07:54:22.19$vc4f8/vabw=wide 2006.197.07:54:22.19#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.197.07:54:22.19#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.197.07:54:22.19#ibcon#ireg 8 cls_cnt 0 2006.197.07:54:22.19#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.197.07:54:22.19#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.197.07:54:22.19#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.197.07:54:22.19#ibcon#enter wrdev, iclass 35, count 0 2006.197.07:54:22.19#ibcon#first serial, iclass 35, count 0 2006.197.07:54:22.19#ibcon#enter sib2, iclass 35, count 0 2006.197.07:54:22.19#ibcon#flushed, iclass 35, count 0 2006.197.07:54:22.19#ibcon#about to write, iclass 35, count 0 2006.197.07:54:22.19#ibcon#wrote, iclass 35, count 0 2006.197.07:54:22.19#ibcon#about to read 3, iclass 35, count 0 2006.197.07:54:22.21#ibcon#read 3, iclass 35, count 0 2006.197.07:54:22.21#ibcon#about to read 4, iclass 35, count 0 2006.197.07:54:22.21#ibcon#read 4, iclass 35, count 0 2006.197.07:54:22.21#ibcon#about to read 5, iclass 35, count 0 2006.197.07:54:22.21#ibcon#read 5, iclass 35, count 0 2006.197.07:54:22.21#ibcon#about to read 6, iclass 35, count 0 2006.197.07:54:22.21#ibcon#read 6, iclass 35, count 0 2006.197.07:54:22.21#ibcon#end of sib2, iclass 35, count 0 2006.197.07:54:22.21#ibcon#*mode == 0, iclass 35, count 0 2006.197.07:54:22.21#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.197.07:54:22.21#ibcon#[25=BW32\r\n] 2006.197.07:54:22.21#ibcon#*before write, iclass 35, count 0 2006.197.07:54:22.21#ibcon#enter sib2, iclass 35, count 0 2006.197.07:54:22.21#ibcon#flushed, iclass 35, count 0 2006.197.07:54:22.21#ibcon#about to write, iclass 35, count 0 2006.197.07:54:22.21#ibcon#wrote, iclass 35, count 0 2006.197.07:54:22.21#ibcon#about to read 3, iclass 35, count 0 2006.197.07:54:22.24#ibcon#read 3, iclass 35, count 0 2006.197.07:54:22.24#ibcon#about to read 4, iclass 35, count 0 2006.197.07:54:22.24#ibcon#read 4, iclass 35, count 0 2006.197.07:54:22.24#ibcon#about to read 5, iclass 35, count 0 2006.197.07:54:22.24#ibcon#read 5, iclass 35, count 0 2006.197.07:54:22.24#ibcon#about to read 6, iclass 35, count 0 2006.197.07:54:22.24#ibcon#read 6, iclass 35, count 0 2006.197.07:54:22.24#ibcon#end of sib2, iclass 35, count 0 2006.197.07:54:22.24#ibcon#*after write, iclass 35, count 0 2006.197.07:54:22.24#ibcon#*before return 0, iclass 35, count 0 2006.197.07:54:22.24#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.197.07:54:22.24#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.197.07:54:22.24#ibcon#about to clear, iclass 35 cls_cnt 0 2006.197.07:54:22.24#ibcon#cleared, iclass 35 cls_cnt 0 2006.197.07:54:22.24$vc4f8/vbbw=wide 2006.197.07:54:22.24#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.197.07:54:22.24#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.197.07:54:22.24#ibcon#ireg 8 cls_cnt 0 2006.197.07:54:22.24#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.197.07:54:22.31#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.197.07:54:22.31#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.197.07:54:22.31#ibcon#enter wrdev, iclass 37, count 0 2006.197.07:54:22.31#ibcon#first serial, iclass 37, count 0 2006.197.07:54:22.31#ibcon#enter sib2, iclass 37, count 0 2006.197.07:54:22.31#ibcon#flushed, iclass 37, count 0 2006.197.07:54:22.31#ibcon#about to write, iclass 37, count 0 2006.197.07:54:22.31#ibcon#wrote, iclass 37, count 0 2006.197.07:54:22.31#ibcon#about to read 3, iclass 37, count 0 2006.197.07:54:22.33#ibcon#read 3, iclass 37, count 0 2006.197.07:54:22.33#ibcon#about to read 4, iclass 37, count 0 2006.197.07:54:22.33#ibcon#read 4, iclass 37, count 0 2006.197.07:54:22.33#ibcon#about to read 5, iclass 37, count 0 2006.197.07:54:22.33#ibcon#read 5, iclass 37, count 0 2006.197.07:54:22.33#ibcon#about to read 6, iclass 37, count 0 2006.197.07:54:22.33#ibcon#read 6, iclass 37, count 0 2006.197.07:54:22.33#ibcon#end of sib2, iclass 37, count 0 2006.197.07:54:22.33#ibcon#*mode == 0, iclass 37, count 0 2006.197.07:54:22.33#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.197.07:54:22.33#ibcon#[27=BW32\r\n] 2006.197.07:54:22.33#ibcon#*before write, iclass 37, count 0 2006.197.07:54:22.33#ibcon#enter sib2, iclass 37, count 0 2006.197.07:54:22.33#ibcon#flushed, iclass 37, count 0 2006.197.07:54:22.33#ibcon#about to write, iclass 37, count 0 2006.197.07:54:22.33#ibcon#wrote, iclass 37, count 0 2006.197.07:54:22.33#ibcon#about to read 3, iclass 37, count 0 2006.197.07:54:22.36#ibcon#read 3, iclass 37, count 0 2006.197.07:54:22.36#ibcon#about to read 4, iclass 37, count 0 2006.197.07:54:22.36#ibcon#read 4, iclass 37, count 0 2006.197.07:54:22.36#ibcon#about to read 5, iclass 37, count 0 2006.197.07:54:22.36#ibcon#read 5, iclass 37, count 0 2006.197.07:54:22.36#ibcon#about to read 6, iclass 37, count 0 2006.197.07:54:22.36#ibcon#read 6, iclass 37, count 0 2006.197.07:54:22.36#ibcon#end of sib2, iclass 37, count 0 2006.197.07:54:22.36#ibcon#*after write, iclass 37, count 0 2006.197.07:54:22.36#ibcon#*before return 0, iclass 37, count 0 2006.197.07:54:22.36#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.197.07:54:22.36#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.197.07:54:22.36#ibcon#about to clear, iclass 37 cls_cnt 0 2006.197.07:54:22.36#ibcon#cleared, iclass 37 cls_cnt 0 2006.197.07:54:22.36$4f8m12a/ifd4f 2006.197.07:54:22.36$ifd4f/lo= 2006.197.07:54:22.36$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.197.07:54:22.36$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.197.07:54:22.36$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.197.07:54:22.36$ifd4f/patch= 2006.197.07:54:22.36$ifd4f/patch=lo1,a1,a2,a3,a4 2006.197.07:54:22.36$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.197.07:54:22.36$ifd4f/patch=lo3,a5,a6,a7,a8 2006.197.07:54:22.36$4f8m12a/"form=m,16.000,1:2 2006.197.07:54:22.36$4f8m12a/"tpicd 2006.197.07:54:22.36$4f8m12a/echo=off 2006.197.07:54:22.36$4f8m12a/xlog=off 2006.197.07:54:22.36:!2006.197.07:55:10 2006.197.07:54:43.13#trakl#Source acquired 2006.197.07:54:44.13#flagr#flagr/antenna,acquired 2006.197.07:55:10.00:preob 2006.197.07:55:10.13/onsource/TRACKING 2006.197.07:55:10.13:!2006.197.07:55:20 2006.197.07:55:20.00:data_valid=on 2006.197.07:55:20.00:midob 2006.197.07:55:20.13/onsource/TRACKING 2006.197.07:55:20.13/wx/25.77,1003.1,97 2006.197.07:55:20.31/cable/+6.3698E-03 2006.197.07:55:21.40/va/01,08,usb,yes,30,31 2006.197.07:55:21.40/va/02,07,usb,yes,30,31 2006.197.07:55:21.40/va/03,06,usb,yes,32,32 2006.197.07:55:21.40/va/04,07,usb,yes,31,33 2006.197.07:55:21.40/va/05,07,usb,yes,35,36 2006.197.07:55:21.40/va/06,06,usb,yes,34,33 2006.197.07:55:21.40/va/07,06,usb,yes,34,34 2006.197.07:55:21.40/va/08,07,usb,yes,32,32 2006.197.07:55:21.63/valo/01,532.99,yes,locked 2006.197.07:55:21.63/valo/02,572.99,yes,locked 2006.197.07:55:21.63/valo/03,672.99,yes,locked 2006.197.07:55:21.63/valo/04,832.99,yes,locked 2006.197.07:55:21.63/valo/05,652.99,yes,locked 2006.197.07:55:21.63/valo/06,772.99,yes,locked 2006.197.07:55:21.63/valo/07,832.99,yes,locked 2006.197.07:55:21.63/valo/08,852.99,yes,locked 2006.197.07:55:22.72/vb/01,04,usb,yes,29,28 2006.197.07:55:22.72/vb/02,04,usb,yes,31,32 2006.197.07:55:22.72/vb/03,04,usb,yes,27,31 2006.197.07:55:22.72/vb/04,04,usb,yes,28,28 2006.197.07:55:22.72/vb/05,04,usb,yes,27,31 2006.197.07:55:22.72/vb/06,04,usb,yes,28,30 2006.197.07:55:22.72/vb/07,04,usb,yes,30,30 2006.197.07:55:22.72/vb/08,04,usb,yes,27,31 2006.197.07:55:22.95/vblo/01,632.99,yes,locked 2006.197.07:55:22.95/vblo/02,640.99,yes,locked 2006.197.07:55:22.95/vblo/03,656.99,yes,locked 2006.197.07:55:22.95/vblo/04,712.99,yes,locked 2006.197.07:55:22.95/vblo/05,744.99,yes,locked 2006.197.07:55:22.95/vblo/06,752.99,yes,locked 2006.197.07:55:22.95/vblo/07,734.99,yes,locked 2006.197.07:55:22.95/vblo/08,744.99,yes,locked 2006.197.07:55:23.10/vabw/8 2006.197.07:55:23.25/vbbw/8 2006.197.07:55:23.34/xfe/off,on,15.2 2006.197.07:55:23.71/ifatt/23,28,28,28 2006.197.07:55:24.10/fmout-gps/S +2.99E-07 2006.197.07:55:24.14:!2006.197.07:56:20 2006.197.07:56:20.00:data_valid=off 2006.197.07:56:20.00:postob 2006.197.07:56:20.15/cable/+6.3721E-03 2006.197.07:56:20.15/wx/25.76,1003.0,96 2006.197.07:56:21.11/fmout-gps/S +3.01E-07 2006.197.07:56:21.11:scan_name=197-0758,k06197,60 2006.197.07:56:21.11:source=0823+033,082550.34,030924.5,2000.0,ccw 2006.197.07:56:21.13#flagr#flagr/antenna,new-source 2006.197.07:56:22.13:checkk5 2006.197.07:56:22.47/chk_autoobs//k5ts1/ autoobs is running! 2006.197.07:56:22.81/chk_autoobs//k5ts2/ autoobs is running! 2006.197.07:56:23.16/chk_autoobs//k5ts3/ autoobs is running! 2006.197.07:56:23.50/chk_autoobs//k5ts4/ autoobs is running! 2006.197.07:56:23.84/chk_obsdata//k5ts1/T1970755??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.07:56:24.18/chk_obsdata//k5ts2/T1970755??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.07:56:24.51/chk_obsdata//k5ts3/T1970755??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.07:56:24.85/chk_obsdata//k5ts4/T1970755??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.07:56:25.52/k5log//k5ts1_log_newline 2006.197.07:56:26.18/k5log//k5ts2_log_newline 2006.197.07:56:26.84/k5log//k5ts3_log_newline 2006.197.07:56:27.50/k5log//k5ts4_log_newline 2006.197.07:56:27.53/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.197.07:56:27.53:4f8m12a=2 2006.197.07:56:27.53$4f8m12a/echo=on 2006.197.07:56:27.53$4f8m12a/pcalon 2006.197.07:56:27.53$pcalon/"no phase cal control is implemented here 2006.197.07:56:27.53$4f8m12a/"tpicd=stop 2006.197.07:56:27.53$4f8m12a/vc4f8 2006.197.07:56:27.53$vc4f8/valo=1,532.99 2006.197.07:56:27.53#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.197.07:56:27.53#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.197.07:56:27.53#ibcon#ireg 17 cls_cnt 0 2006.197.07:56:27.53#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.197.07:56:27.53#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.197.07:56:27.53#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.197.07:56:27.53#ibcon#enter wrdev, iclass 16, count 0 2006.197.07:56:27.53#ibcon#first serial, iclass 16, count 0 2006.197.07:56:27.53#ibcon#enter sib2, iclass 16, count 0 2006.197.07:56:27.53#ibcon#flushed, iclass 16, count 0 2006.197.07:56:27.53#ibcon#about to write, iclass 16, count 0 2006.197.07:56:27.53#ibcon#wrote, iclass 16, count 0 2006.197.07:56:27.53#ibcon#about to read 3, iclass 16, count 0 2006.197.07:56:27.55#ibcon#read 3, iclass 16, count 0 2006.197.07:56:27.55#ibcon#about to read 4, iclass 16, count 0 2006.197.07:56:27.55#ibcon#read 4, iclass 16, count 0 2006.197.07:56:27.55#ibcon#about to read 5, iclass 16, count 0 2006.197.07:56:27.55#ibcon#read 5, iclass 16, count 0 2006.197.07:56:27.55#ibcon#about to read 6, iclass 16, count 0 2006.197.07:56:27.55#ibcon#read 6, iclass 16, count 0 2006.197.07:56:27.55#ibcon#end of sib2, iclass 16, count 0 2006.197.07:56:27.55#ibcon#*mode == 0, iclass 16, count 0 2006.197.07:56:27.55#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.197.07:56:27.55#ibcon#[26=FRQ=01,532.99\r\n] 2006.197.07:56:27.55#ibcon#*before write, iclass 16, count 0 2006.197.07:56:27.55#ibcon#enter sib2, iclass 16, count 0 2006.197.07:56:27.55#ibcon#flushed, iclass 16, count 0 2006.197.07:56:27.55#ibcon#about to write, iclass 16, count 0 2006.197.07:56:27.55#ibcon#wrote, iclass 16, count 0 2006.197.07:56:27.55#ibcon#about to read 3, iclass 16, count 0 2006.197.07:56:27.60#ibcon#read 3, iclass 16, count 0 2006.197.07:56:27.60#ibcon#about to read 4, iclass 16, count 0 2006.197.07:56:27.60#ibcon#read 4, iclass 16, count 0 2006.197.07:56:27.60#ibcon#about to read 5, iclass 16, count 0 2006.197.07:56:27.60#ibcon#read 5, iclass 16, count 0 2006.197.07:56:27.60#ibcon#about to read 6, iclass 16, count 0 2006.197.07:56:27.60#ibcon#read 6, iclass 16, count 0 2006.197.07:56:27.60#ibcon#end of sib2, iclass 16, count 0 2006.197.07:56:27.60#ibcon#*after write, iclass 16, count 0 2006.197.07:56:27.60#ibcon#*before return 0, iclass 16, count 0 2006.197.07:56:27.60#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.197.07:56:27.60#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.197.07:56:27.60#ibcon#about to clear, iclass 16 cls_cnt 0 2006.197.07:56:27.60#ibcon#cleared, iclass 16 cls_cnt 0 2006.197.07:56:27.60$vc4f8/va=1,8 2006.197.07:56:27.60#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.197.07:56:27.60#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.197.07:56:27.60#ibcon#ireg 11 cls_cnt 2 2006.197.07:56:27.60#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.197.07:56:27.60#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.197.07:56:27.60#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.197.07:56:27.60#ibcon#enter wrdev, iclass 18, count 2 2006.197.07:56:27.60#ibcon#first serial, iclass 18, count 2 2006.197.07:56:27.60#ibcon#enter sib2, iclass 18, count 2 2006.197.07:56:27.60#ibcon#flushed, iclass 18, count 2 2006.197.07:56:27.60#ibcon#about to write, iclass 18, count 2 2006.197.07:56:27.60#ibcon#wrote, iclass 18, count 2 2006.197.07:56:27.60#ibcon#about to read 3, iclass 18, count 2 2006.197.07:56:27.62#ibcon#read 3, iclass 18, count 2 2006.197.07:56:27.62#ibcon#about to read 4, iclass 18, count 2 2006.197.07:56:27.62#ibcon#read 4, iclass 18, count 2 2006.197.07:56:27.62#ibcon#about to read 5, iclass 18, count 2 2006.197.07:56:27.62#ibcon#read 5, iclass 18, count 2 2006.197.07:56:27.62#ibcon#about to read 6, iclass 18, count 2 2006.197.07:56:27.62#ibcon#read 6, iclass 18, count 2 2006.197.07:56:27.62#ibcon#end of sib2, iclass 18, count 2 2006.197.07:56:27.62#ibcon#*mode == 0, iclass 18, count 2 2006.197.07:56:27.62#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.197.07:56:27.62#ibcon#[25=AT01-08\r\n] 2006.197.07:56:27.62#ibcon#*before write, iclass 18, count 2 2006.197.07:56:27.62#ibcon#enter sib2, iclass 18, count 2 2006.197.07:56:27.62#ibcon#flushed, iclass 18, count 2 2006.197.07:56:27.62#ibcon#about to write, iclass 18, count 2 2006.197.07:56:27.62#ibcon#wrote, iclass 18, count 2 2006.197.07:56:27.62#ibcon#about to read 3, iclass 18, count 2 2006.197.07:56:27.65#ibcon#read 3, iclass 18, count 2 2006.197.07:56:27.65#ibcon#about to read 4, iclass 18, count 2 2006.197.07:56:27.65#ibcon#read 4, iclass 18, count 2 2006.197.07:56:27.65#ibcon#about to read 5, iclass 18, count 2 2006.197.07:56:27.65#ibcon#read 5, iclass 18, count 2 2006.197.07:56:27.65#ibcon#about to read 6, iclass 18, count 2 2006.197.07:56:27.65#ibcon#read 6, iclass 18, count 2 2006.197.07:56:27.65#ibcon#end of sib2, iclass 18, count 2 2006.197.07:56:27.65#ibcon#*after write, iclass 18, count 2 2006.197.07:56:27.65#ibcon#*before return 0, iclass 18, count 2 2006.197.07:56:27.65#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.197.07:56:27.65#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.197.07:56:27.65#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.197.07:56:27.65#ibcon#ireg 7 cls_cnt 0 2006.197.07:56:27.65#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.197.07:56:27.77#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.197.07:56:27.77#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.197.07:56:27.77#ibcon#enter wrdev, iclass 18, count 0 2006.197.07:56:27.77#ibcon#first serial, iclass 18, count 0 2006.197.07:56:27.77#ibcon#enter sib2, iclass 18, count 0 2006.197.07:56:27.77#ibcon#flushed, iclass 18, count 0 2006.197.07:56:27.77#ibcon#about to write, iclass 18, count 0 2006.197.07:56:27.77#ibcon#wrote, iclass 18, count 0 2006.197.07:56:27.77#ibcon#about to read 3, iclass 18, count 0 2006.197.07:56:27.79#ibcon#read 3, iclass 18, count 0 2006.197.07:56:27.79#ibcon#about to read 4, iclass 18, count 0 2006.197.07:56:27.79#ibcon#read 4, iclass 18, count 0 2006.197.07:56:27.79#ibcon#about to read 5, iclass 18, count 0 2006.197.07:56:27.79#ibcon#read 5, iclass 18, count 0 2006.197.07:56:27.79#ibcon#about to read 6, iclass 18, count 0 2006.197.07:56:27.79#ibcon#read 6, iclass 18, count 0 2006.197.07:56:27.79#ibcon#end of sib2, iclass 18, count 0 2006.197.07:56:27.79#ibcon#*mode == 0, iclass 18, count 0 2006.197.07:56:27.79#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.197.07:56:27.79#ibcon#[25=USB\r\n] 2006.197.07:56:27.79#ibcon#*before write, iclass 18, count 0 2006.197.07:56:27.79#ibcon#enter sib2, iclass 18, count 0 2006.197.07:56:27.79#ibcon#flushed, iclass 18, count 0 2006.197.07:56:27.79#ibcon#about to write, iclass 18, count 0 2006.197.07:56:27.79#ibcon#wrote, iclass 18, count 0 2006.197.07:56:27.79#ibcon#about to read 3, iclass 18, count 0 2006.197.07:56:27.82#ibcon#read 3, iclass 18, count 0 2006.197.07:56:27.82#ibcon#about to read 4, iclass 18, count 0 2006.197.07:56:27.82#ibcon#read 4, iclass 18, count 0 2006.197.07:56:27.82#ibcon#about to read 5, iclass 18, count 0 2006.197.07:56:27.82#ibcon#read 5, iclass 18, count 0 2006.197.07:56:27.82#ibcon#about to read 6, iclass 18, count 0 2006.197.07:56:27.82#ibcon#read 6, iclass 18, count 0 2006.197.07:56:27.82#ibcon#end of sib2, iclass 18, count 0 2006.197.07:56:27.82#ibcon#*after write, iclass 18, count 0 2006.197.07:56:27.82#ibcon#*before return 0, iclass 18, count 0 2006.197.07:56:27.82#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.197.07:56:27.82#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.197.07:56:27.82#ibcon#about to clear, iclass 18 cls_cnt 0 2006.197.07:56:27.82#ibcon#cleared, iclass 18 cls_cnt 0 2006.197.07:56:27.82$vc4f8/valo=2,572.99 2006.197.07:56:27.82#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.197.07:56:27.82#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.197.07:56:27.82#ibcon#ireg 17 cls_cnt 0 2006.197.07:56:27.82#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.197.07:56:27.82#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.197.07:56:27.82#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.197.07:56:27.82#ibcon#enter wrdev, iclass 20, count 0 2006.197.07:56:27.82#ibcon#first serial, iclass 20, count 0 2006.197.07:56:27.82#ibcon#enter sib2, iclass 20, count 0 2006.197.07:56:27.82#ibcon#flushed, iclass 20, count 0 2006.197.07:56:27.82#ibcon#about to write, iclass 20, count 0 2006.197.07:56:27.82#ibcon#wrote, iclass 20, count 0 2006.197.07:56:27.82#ibcon#about to read 3, iclass 20, count 0 2006.197.07:56:27.84#ibcon#read 3, iclass 20, count 0 2006.197.07:56:27.84#ibcon#about to read 4, iclass 20, count 0 2006.197.07:56:27.84#ibcon#read 4, iclass 20, count 0 2006.197.07:56:27.84#ibcon#about to read 5, iclass 20, count 0 2006.197.07:56:27.84#ibcon#read 5, iclass 20, count 0 2006.197.07:56:27.84#ibcon#about to read 6, iclass 20, count 0 2006.197.07:56:27.84#ibcon#read 6, iclass 20, count 0 2006.197.07:56:27.84#ibcon#end of sib2, iclass 20, count 0 2006.197.07:56:27.84#ibcon#*mode == 0, iclass 20, count 0 2006.197.07:56:27.84#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.197.07:56:27.84#ibcon#[26=FRQ=02,572.99\r\n] 2006.197.07:56:27.84#ibcon#*before write, iclass 20, count 0 2006.197.07:56:27.84#ibcon#enter sib2, iclass 20, count 0 2006.197.07:56:27.84#ibcon#flushed, iclass 20, count 0 2006.197.07:56:27.84#ibcon#about to write, iclass 20, count 0 2006.197.07:56:27.84#ibcon#wrote, iclass 20, count 0 2006.197.07:56:27.84#ibcon#about to read 3, iclass 20, count 0 2006.197.07:56:27.88#ibcon#read 3, iclass 20, count 0 2006.197.07:56:27.88#ibcon#about to read 4, iclass 20, count 0 2006.197.07:56:27.88#ibcon#read 4, iclass 20, count 0 2006.197.07:56:27.88#ibcon#about to read 5, iclass 20, count 0 2006.197.07:56:27.88#ibcon#read 5, iclass 20, count 0 2006.197.07:56:27.88#ibcon#about to read 6, iclass 20, count 0 2006.197.07:56:27.88#ibcon#read 6, iclass 20, count 0 2006.197.07:56:27.88#ibcon#end of sib2, iclass 20, count 0 2006.197.07:56:27.88#ibcon#*after write, iclass 20, count 0 2006.197.07:56:27.88#ibcon#*before return 0, iclass 20, count 0 2006.197.07:56:27.88#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.197.07:56:27.88#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.197.07:56:27.88#ibcon#about to clear, iclass 20 cls_cnt 0 2006.197.07:56:27.88#ibcon#cleared, iclass 20 cls_cnt 0 2006.197.07:56:27.88$vc4f8/va=2,7 2006.197.07:56:27.88#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.197.07:56:27.88#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.197.07:56:27.88#ibcon#ireg 11 cls_cnt 2 2006.197.07:56:27.88#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.197.07:56:27.94#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.197.07:56:27.94#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.197.07:56:27.94#ibcon#enter wrdev, iclass 22, count 2 2006.197.07:56:27.94#ibcon#first serial, iclass 22, count 2 2006.197.07:56:27.94#ibcon#enter sib2, iclass 22, count 2 2006.197.07:56:27.94#ibcon#flushed, iclass 22, count 2 2006.197.07:56:27.94#ibcon#about to write, iclass 22, count 2 2006.197.07:56:27.94#ibcon#wrote, iclass 22, count 2 2006.197.07:56:27.94#ibcon#about to read 3, iclass 22, count 2 2006.197.07:56:27.96#ibcon#read 3, iclass 22, count 2 2006.197.07:56:27.96#ibcon#about to read 4, iclass 22, count 2 2006.197.07:56:27.96#ibcon#read 4, iclass 22, count 2 2006.197.07:56:27.96#ibcon#about to read 5, iclass 22, count 2 2006.197.07:56:27.96#ibcon#read 5, iclass 22, count 2 2006.197.07:56:27.96#ibcon#about to read 6, iclass 22, count 2 2006.197.07:56:27.96#ibcon#read 6, iclass 22, count 2 2006.197.07:56:27.96#ibcon#end of sib2, iclass 22, count 2 2006.197.07:56:27.96#ibcon#*mode == 0, iclass 22, count 2 2006.197.07:56:27.96#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.197.07:56:27.96#ibcon#[25=AT02-07\r\n] 2006.197.07:56:27.96#ibcon#*before write, iclass 22, count 2 2006.197.07:56:27.96#ibcon#enter sib2, iclass 22, count 2 2006.197.07:56:27.96#ibcon#flushed, iclass 22, count 2 2006.197.07:56:27.96#ibcon#about to write, iclass 22, count 2 2006.197.07:56:27.96#ibcon#wrote, iclass 22, count 2 2006.197.07:56:27.96#ibcon#about to read 3, iclass 22, count 2 2006.197.07:56:27.99#ibcon#read 3, iclass 22, count 2 2006.197.07:56:27.99#ibcon#about to read 4, iclass 22, count 2 2006.197.07:56:27.99#ibcon#read 4, iclass 22, count 2 2006.197.07:56:27.99#ibcon#about to read 5, iclass 22, count 2 2006.197.07:56:27.99#ibcon#read 5, iclass 22, count 2 2006.197.07:56:27.99#ibcon#about to read 6, iclass 22, count 2 2006.197.07:56:27.99#ibcon#read 6, iclass 22, count 2 2006.197.07:56:27.99#ibcon#end of sib2, iclass 22, count 2 2006.197.07:56:27.99#ibcon#*after write, iclass 22, count 2 2006.197.07:56:27.99#ibcon#*before return 0, iclass 22, count 2 2006.197.07:56:27.99#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.197.07:56:27.99#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.197.07:56:27.99#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.197.07:56:27.99#ibcon#ireg 7 cls_cnt 0 2006.197.07:56:27.99#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.197.07:56:28.11#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.197.07:56:28.11#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.197.07:56:28.11#ibcon#enter wrdev, iclass 22, count 0 2006.197.07:56:28.11#ibcon#first serial, iclass 22, count 0 2006.197.07:56:28.11#ibcon#enter sib2, iclass 22, count 0 2006.197.07:56:28.11#ibcon#flushed, iclass 22, count 0 2006.197.07:56:28.11#ibcon#about to write, iclass 22, count 0 2006.197.07:56:28.11#ibcon#wrote, iclass 22, count 0 2006.197.07:56:28.11#ibcon#about to read 3, iclass 22, count 0 2006.197.07:56:28.13#ibcon#read 3, iclass 22, count 0 2006.197.07:56:28.13#ibcon#about to read 4, iclass 22, count 0 2006.197.07:56:28.13#ibcon#read 4, iclass 22, count 0 2006.197.07:56:28.13#ibcon#about to read 5, iclass 22, count 0 2006.197.07:56:28.13#ibcon#read 5, iclass 22, count 0 2006.197.07:56:28.13#ibcon#about to read 6, iclass 22, count 0 2006.197.07:56:28.13#ibcon#read 6, iclass 22, count 0 2006.197.07:56:28.13#ibcon#end of sib2, iclass 22, count 0 2006.197.07:56:28.13#ibcon#*mode == 0, iclass 22, count 0 2006.197.07:56:28.13#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.197.07:56:28.13#ibcon#[25=USB\r\n] 2006.197.07:56:28.13#ibcon#*before write, iclass 22, count 0 2006.197.07:56:28.13#ibcon#enter sib2, iclass 22, count 0 2006.197.07:56:28.13#ibcon#flushed, iclass 22, count 0 2006.197.07:56:28.13#ibcon#about to write, iclass 22, count 0 2006.197.07:56:28.13#ibcon#wrote, iclass 22, count 0 2006.197.07:56:28.13#ibcon#about to read 3, iclass 22, count 0 2006.197.07:56:28.16#ibcon#read 3, iclass 22, count 0 2006.197.07:56:28.16#ibcon#about to read 4, iclass 22, count 0 2006.197.07:56:28.16#ibcon#read 4, iclass 22, count 0 2006.197.07:56:28.16#ibcon#about to read 5, iclass 22, count 0 2006.197.07:56:28.16#ibcon#read 5, iclass 22, count 0 2006.197.07:56:28.16#ibcon#about to read 6, iclass 22, count 0 2006.197.07:56:28.16#ibcon#read 6, iclass 22, count 0 2006.197.07:56:28.16#ibcon#end of sib2, iclass 22, count 0 2006.197.07:56:28.16#ibcon#*after write, iclass 22, count 0 2006.197.07:56:28.16#ibcon#*before return 0, iclass 22, count 0 2006.197.07:56:28.16#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.197.07:56:28.16#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.197.07:56:28.16#ibcon#about to clear, iclass 22 cls_cnt 0 2006.197.07:56:28.16#ibcon#cleared, iclass 22 cls_cnt 0 2006.197.07:56:28.16$vc4f8/valo=3,672.99 2006.197.07:56:28.16#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.197.07:56:28.16#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.197.07:56:28.16#ibcon#ireg 17 cls_cnt 0 2006.197.07:56:28.16#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.197.07:56:28.16#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.197.07:56:28.16#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.197.07:56:28.16#ibcon#enter wrdev, iclass 24, count 0 2006.197.07:56:28.16#ibcon#first serial, iclass 24, count 0 2006.197.07:56:28.16#ibcon#enter sib2, iclass 24, count 0 2006.197.07:56:28.16#ibcon#flushed, iclass 24, count 0 2006.197.07:56:28.16#ibcon#about to write, iclass 24, count 0 2006.197.07:56:28.16#ibcon#wrote, iclass 24, count 0 2006.197.07:56:28.16#ibcon#about to read 3, iclass 24, count 0 2006.197.07:56:28.18#ibcon#read 3, iclass 24, count 0 2006.197.07:56:28.18#ibcon#about to read 4, iclass 24, count 0 2006.197.07:56:28.18#ibcon#read 4, iclass 24, count 0 2006.197.07:56:28.18#ibcon#about to read 5, iclass 24, count 0 2006.197.07:56:28.18#ibcon#read 5, iclass 24, count 0 2006.197.07:56:28.18#ibcon#about to read 6, iclass 24, count 0 2006.197.07:56:28.18#ibcon#read 6, iclass 24, count 0 2006.197.07:56:28.18#ibcon#end of sib2, iclass 24, count 0 2006.197.07:56:28.18#ibcon#*mode == 0, iclass 24, count 0 2006.197.07:56:28.18#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.197.07:56:28.18#ibcon#[26=FRQ=03,672.99\r\n] 2006.197.07:56:28.18#ibcon#*before write, iclass 24, count 0 2006.197.07:56:28.18#ibcon#enter sib2, iclass 24, count 0 2006.197.07:56:28.18#ibcon#flushed, iclass 24, count 0 2006.197.07:56:28.18#ibcon#about to write, iclass 24, count 0 2006.197.07:56:28.18#ibcon#wrote, iclass 24, count 0 2006.197.07:56:28.18#ibcon#about to read 3, iclass 24, count 0 2006.197.07:56:28.22#ibcon#read 3, iclass 24, count 0 2006.197.07:56:28.22#ibcon#about to read 4, iclass 24, count 0 2006.197.07:56:28.22#ibcon#read 4, iclass 24, count 0 2006.197.07:56:28.22#ibcon#about to read 5, iclass 24, count 0 2006.197.07:56:28.22#ibcon#read 5, iclass 24, count 0 2006.197.07:56:28.22#ibcon#about to read 6, iclass 24, count 0 2006.197.07:56:28.22#ibcon#read 6, iclass 24, count 0 2006.197.07:56:28.22#ibcon#end of sib2, iclass 24, count 0 2006.197.07:56:28.22#ibcon#*after write, iclass 24, count 0 2006.197.07:56:28.22#ibcon#*before return 0, iclass 24, count 0 2006.197.07:56:28.22#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.197.07:56:28.22#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.197.07:56:28.22#ibcon#about to clear, iclass 24 cls_cnt 0 2006.197.07:56:28.22#ibcon#cleared, iclass 24 cls_cnt 0 2006.197.07:56:28.22$vc4f8/va=3,6 2006.197.07:56:28.22#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.197.07:56:28.22#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.197.07:56:28.22#ibcon#ireg 11 cls_cnt 2 2006.197.07:56:28.22#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.197.07:56:28.28#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.197.07:56:28.28#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.197.07:56:28.28#ibcon#enter wrdev, iclass 26, count 2 2006.197.07:56:28.28#ibcon#first serial, iclass 26, count 2 2006.197.07:56:28.28#ibcon#enter sib2, iclass 26, count 2 2006.197.07:56:28.28#ibcon#flushed, iclass 26, count 2 2006.197.07:56:28.28#ibcon#about to write, iclass 26, count 2 2006.197.07:56:28.28#ibcon#wrote, iclass 26, count 2 2006.197.07:56:28.28#ibcon#about to read 3, iclass 26, count 2 2006.197.07:56:28.30#ibcon#read 3, iclass 26, count 2 2006.197.07:56:28.30#ibcon#about to read 4, iclass 26, count 2 2006.197.07:56:28.30#ibcon#read 4, iclass 26, count 2 2006.197.07:56:28.30#ibcon#about to read 5, iclass 26, count 2 2006.197.07:56:28.30#ibcon#read 5, iclass 26, count 2 2006.197.07:56:28.30#ibcon#about to read 6, iclass 26, count 2 2006.197.07:56:28.30#ibcon#read 6, iclass 26, count 2 2006.197.07:56:28.30#ibcon#end of sib2, iclass 26, count 2 2006.197.07:56:28.30#ibcon#*mode == 0, iclass 26, count 2 2006.197.07:56:28.30#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.197.07:56:28.30#ibcon#[25=AT03-06\r\n] 2006.197.07:56:28.30#ibcon#*before write, iclass 26, count 2 2006.197.07:56:28.30#ibcon#enter sib2, iclass 26, count 2 2006.197.07:56:28.30#ibcon#flushed, iclass 26, count 2 2006.197.07:56:28.30#ibcon#about to write, iclass 26, count 2 2006.197.07:56:28.30#ibcon#wrote, iclass 26, count 2 2006.197.07:56:28.30#ibcon#about to read 3, iclass 26, count 2 2006.197.07:56:28.33#ibcon#read 3, iclass 26, count 2 2006.197.07:56:28.33#ibcon#about to read 4, iclass 26, count 2 2006.197.07:56:28.33#ibcon#read 4, iclass 26, count 2 2006.197.07:56:28.33#ibcon#about to read 5, iclass 26, count 2 2006.197.07:56:28.33#ibcon#read 5, iclass 26, count 2 2006.197.07:56:28.33#ibcon#about to read 6, iclass 26, count 2 2006.197.07:56:28.33#ibcon#read 6, iclass 26, count 2 2006.197.07:56:28.33#ibcon#end of sib2, iclass 26, count 2 2006.197.07:56:28.33#ibcon#*after write, iclass 26, count 2 2006.197.07:56:28.33#ibcon#*before return 0, iclass 26, count 2 2006.197.07:56:28.33#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.197.07:56:28.33#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.197.07:56:28.33#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.197.07:56:28.33#ibcon#ireg 7 cls_cnt 0 2006.197.07:56:28.33#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.197.07:56:28.45#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.197.07:56:28.45#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.197.07:56:28.45#ibcon#enter wrdev, iclass 26, count 0 2006.197.07:56:28.45#ibcon#first serial, iclass 26, count 0 2006.197.07:56:28.45#ibcon#enter sib2, iclass 26, count 0 2006.197.07:56:28.45#ibcon#flushed, iclass 26, count 0 2006.197.07:56:28.45#ibcon#about to write, iclass 26, count 0 2006.197.07:56:28.45#ibcon#wrote, iclass 26, count 0 2006.197.07:56:28.45#ibcon#about to read 3, iclass 26, count 0 2006.197.07:56:28.47#ibcon#read 3, iclass 26, count 0 2006.197.07:56:28.47#ibcon#about to read 4, iclass 26, count 0 2006.197.07:56:28.47#ibcon#read 4, iclass 26, count 0 2006.197.07:56:28.47#ibcon#about to read 5, iclass 26, count 0 2006.197.07:56:28.47#ibcon#read 5, iclass 26, count 0 2006.197.07:56:28.47#ibcon#about to read 6, iclass 26, count 0 2006.197.07:56:28.47#ibcon#read 6, iclass 26, count 0 2006.197.07:56:28.47#ibcon#end of sib2, iclass 26, count 0 2006.197.07:56:28.47#ibcon#*mode == 0, iclass 26, count 0 2006.197.07:56:28.47#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.197.07:56:28.47#ibcon#[25=USB\r\n] 2006.197.07:56:28.47#ibcon#*before write, iclass 26, count 0 2006.197.07:56:28.47#ibcon#enter sib2, iclass 26, count 0 2006.197.07:56:28.47#ibcon#flushed, iclass 26, count 0 2006.197.07:56:28.47#ibcon#about to write, iclass 26, count 0 2006.197.07:56:28.47#ibcon#wrote, iclass 26, count 0 2006.197.07:56:28.47#ibcon#about to read 3, iclass 26, count 0 2006.197.07:56:28.50#ibcon#read 3, iclass 26, count 0 2006.197.07:56:28.50#ibcon#about to read 4, iclass 26, count 0 2006.197.07:56:28.50#ibcon#read 4, iclass 26, count 0 2006.197.07:56:28.50#ibcon#about to read 5, iclass 26, count 0 2006.197.07:56:28.50#ibcon#read 5, iclass 26, count 0 2006.197.07:56:28.50#ibcon#about to read 6, iclass 26, count 0 2006.197.07:56:28.50#ibcon#read 6, iclass 26, count 0 2006.197.07:56:28.50#ibcon#end of sib2, iclass 26, count 0 2006.197.07:56:28.50#ibcon#*after write, iclass 26, count 0 2006.197.07:56:28.50#ibcon#*before return 0, iclass 26, count 0 2006.197.07:56:28.50#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.197.07:56:28.50#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.197.07:56:28.50#ibcon#about to clear, iclass 26 cls_cnt 0 2006.197.07:56:28.50#ibcon#cleared, iclass 26 cls_cnt 0 2006.197.07:56:28.50$vc4f8/valo=4,832.99 2006.197.07:56:28.50#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.197.07:56:28.50#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.197.07:56:28.50#ibcon#ireg 17 cls_cnt 0 2006.197.07:56:28.50#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.197.07:56:28.50#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.197.07:56:28.50#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.197.07:56:28.50#ibcon#enter wrdev, iclass 28, count 0 2006.197.07:56:28.50#ibcon#first serial, iclass 28, count 0 2006.197.07:56:28.50#ibcon#enter sib2, iclass 28, count 0 2006.197.07:56:28.50#ibcon#flushed, iclass 28, count 0 2006.197.07:56:28.50#ibcon#about to write, iclass 28, count 0 2006.197.07:56:28.50#ibcon#wrote, iclass 28, count 0 2006.197.07:56:28.50#ibcon#about to read 3, iclass 28, count 0 2006.197.07:56:28.52#ibcon#read 3, iclass 28, count 0 2006.197.07:56:28.52#ibcon#about to read 4, iclass 28, count 0 2006.197.07:56:28.52#ibcon#read 4, iclass 28, count 0 2006.197.07:56:28.52#ibcon#about to read 5, iclass 28, count 0 2006.197.07:56:28.52#ibcon#read 5, iclass 28, count 0 2006.197.07:56:28.52#ibcon#about to read 6, iclass 28, count 0 2006.197.07:56:28.52#ibcon#read 6, iclass 28, count 0 2006.197.07:56:28.52#ibcon#end of sib2, iclass 28, count 0 2006.197.07:56:28.52#ibcon#*mode == 0, iclass 28, count 0 2006.197.07:56:28.52#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.197.07:56:28.52#ibcon#[26=FRQ=04,832.99\r\n] 2006.197.07:56:28.52#ibcon#*before write, iclass 28, count 0 2006.197.07:56:28.52#ibcon#enter sib2, iclass 28, count 0 2006.197.07:56:28.52#ibcon#flushed, iclass 28, count 0 2006.197.07:56:28.52#ibcon#about to write, iclass 28, count 0 2006.197.07:56:28.52#ibcon#wrote, iclass 28, count 0 2006.197.07:56:28.52#ibcon#about to read 3, iclass 28, count 0 2006.197.07:56:28.56#ibcon#read 3, iclass 28, count 0 2006.197.07:56:28.56#ibcon#about to read 4, iclass 28, count 0 2006.197.07:56:28.56#ibcon#read 4, iclass 28, count 0 2006.197.07:56:28.56#ibcon#about to read 5, iclass 28, count 0 2006.197.07:56:28.56#ibcon#read 5, iclass 28, count 0 2006.197.07:56:28.56#ibcon#about to read 6, iclass 28, count 0 2006.197.07:56:28.56#ibcon#read 6, iclass 28, count 0 2006.197.07:56:28.56#ibcon#end of sib2, iclass 28, count 0 2006.197.07:56:28.56#ibcon#*after write, iclass 28, count 0 2006.197.07:56:28.56#ibcon#*before return 0, iclass 28, count 0 2006.197.07:56:28.56#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.197.07:56:28.56#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.197.07:56:28.56#ibcon#about to clear, iclass 28 cls_cnt 0 2006.197.07:56:28.56#ibcon#cleared, iclass 28 cls_cnt 0 2006.197.07:56:28.56$vc4f8/va=4,7 2006.197.07:56:28.56#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.197.07:56:28.56#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.197.07:56:28.56#ibcon#ireg 11 cls_cnt 2 2006.197.07:56:28.56#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.197.07:56:28.62#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.197.07:56:28.62#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.197.07:56:28.62#ibcon#enter wrdev, iclass 30, count 2 2006.197.07:56:28.62#ibcon#first serial, iclass 30, count 2 2006.197.07:56:28.62#ibcon#enter sib2, iclass 30, count 2 2006.197.07:56:28.62#ibcon#flushed, iclass 30, count 2 2006.197.07:56:28.62#ibcon#about to write, iclass 30, count 2 2006.197.07:56:28.62#ibcon#wrote, iclass 30, count 2 2006.197.07:56:28.62#ibcon#about to read 3, iclass 30, count 2 2006.197.07:56:28.64#ibcon#read 3, iclass 30, count 2 2006.197.07:56:28.64#ibcon#about to read 4, iclass 30, count 2 2006.197.07:56:28.64#ibcon#read 4, iclass 30, count 2 2006.197.07:56:28.64#ibcon#about to read 5, iclass 30, count 2 2006.197.07:56:28.64#ibcon#read 5, iclass 30, count 2 2006.197.07:56:28.64#ibcon#about to read 6, iclass 30, count 2 2006.197.07:56:28.64#ibcon#read 6, iclass 30, count 2 2006.197.07:56:28.64#ibcon#end of sib2, iclass 30, count 2 2006.197.07:56:28.64#ibcon#*mode == 0, iclass 30, count 2 2006.197.07:56:28.64#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.197.07:56:28.64#ibcon#[25=AT04-07\r\n] 2006.197.07:56:28.64#ibcon#*before write, iclass 30, count 2 2006.197.07:56:28.64#ibcon#enter sib2, iclass 30, count 2 2006.197.07:56:28.64#ibcon#flushed, iclass 30, count 2 2006.197.07:56:28.64#ibcon#about to write, iclass 30, count 2 2006.197.07:56:28.64#ibcon#wrote, iclass 30, count 2 2006.197.07:56:28.64#ibcon#about to read 3, iclass 30, count 2 2006.197.07:56:28.67#ibcon#read 3, iclass 30, count 2 2006.197.07:56:28.67#ibcon#about to read 4, iclass 30, count 2 2006.197.07:56:28.67#ibcon#read 4, iclass 30, count 2 2006.197.07:56:28.67#ibcon#about to read 5, iclass 30, count 2 2006.197.07:56:28.67#ibcon#read 5, iclass 30, count 2 2006.197.07:56:28.67#ibcon#about to read 6, iclass 30, count 2 2006.197.07:56:28.67#ibcon#read 6, iclass 30, count 2 2006.197.07:56:28.67#ibcon#end of sib2, iclass 30, count 2 2006.197.07:56:28.67#ibcon#*after write, iclass 30, count 2 2006.197.07:56:28.67#ibcon#*before return 0, iclass 30, count 2 2006.197.07:56:28.67#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.197.07:56:28.67#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.197.07:56:28.67#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.197.07:56:28.67#ibcon#ireg 7 cls_cnt 0 2006.197.07:56:28.67#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.197.07:56:28.79#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.197.07:56:28.79#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.197.07:56:28.79#ibcon#enter wrdev, iclass 30, count 0 2006.197.07:56:28.79#ibcon#first serial, iclass 30, count 0 2006.197.07:56:28.79#ibcon#enter sib2, iclass 30, count 0 2006.197.07:56:28.79#ibcon#flushed, iclass 30, count 0 2006.197.07:56:28.79#ibcon#about to write, iclass 30, count 0 2006.197.07:56:28.79#ibcon#wrote, iclass 30, count 0 2006.197.07:56:28.79#ibcon#about to read 3, iclass 30, count 0 2006.197.07:56:28.81#ibcon#read 3, iclass 30, count 0 2006.197.07:56:28.81#ibcon#about to read 4, iclass 30, count 0 2006.197.07:56:28.81#ibcon#read 4, iclass 30, count 0 2006.197.07:56:28.81#ibcon#about to read 5, iclass 30, count 0 2006.197.07:56:28.81#ibcon#read 5, iclass 30, count 0 2006.197.07:56:28.81#ibcon#about to read 6, iclass 30, count 0 2006.197.07:56:28.81#ibcon#read 6, iclass 30, count 0 2006.197.07:56:28.81#ibcon#end of sib2, iclass 30, count 0 2006.197.07:56:28.81#ibcon#*mode == 0, iclass 30, count 0 2006.197.07:56:28.81#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.197.07:56:28.81#ibcon#[25=USB\r\n] 2006.197.07:56:28.81#ibcon#*before write, iclass 30, count 0 2006.197.07:56:28.81#ibcon#enter sib2, iclass 30, count 0 2006.197.07:56:28.81#ibcon#flushed, iclass 30, count 0 2006.197.07:56:28.81#ibcon#about to write, iclass 30, count 0 2006.197.07:56:28.81#ibcon#wrote, iclass 30, count 0 2006.197.07:56:28.81#ibcon#about to read 3, iclass 30, count 0 2006.197.07:56:28.84#ibcon#read 3, iclass 30, count 0 2006.197.07:56:28.84#ibcon#about to read 4, iclass 30, count 0 2006.197.07:56:28.84#ibcon#read 4, iclass 30, count 0 2006.197.07:56:28.84#ibcon#about to read 5, iclass 30, count 0 2006.197.07:56:28.84#ibcon#read 5, iclass 30, count 0 2006.197.07:56:28.84#ibcon#about to read 6, iclass 30, count 0 2006.197.07:56:28.84#ibcon#read 6, iclass 30, count 0 2006.197.07:56:28.84#ibcon#end of sib2, iclass 30, count 0 2006.197.07:56:28.84#ibcon#*after write, iclass 30, count 0 2006.197.07:56:28.84#ibcon#*before return 0, iclass 30, count 0 2006.197.07:56:28.84#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.197.07:56:28.84#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.197.07:56:28.84#ibcon#about to clear, iclass 30 cls_cnt 0 2006.197.07:56:28.84#ibcon#cleared, iclass 30 cls_cnt 0 2006.197.07:56:28.84$vc4f8/valo=5,652.99 2006.197.07:56:28.84#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.197.07:56:28.84#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.197.07:56:28.84#ibcon#ireg 17 cls_cnt 0 2006.197.07:56:28.84#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.197.07:56:28.84#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.197.07:56:28.84#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.197.07:56:28.84#ibcon#enter wrdev, iclass 32, count 0 2006.197.07:56:28.84#ibcon#first serial, iclass 32, count 0 2006.197.07:56:28.84#ibcon#enter sib2, iclass 32, count 0 2006.197.07:56:28.84#ibcon#flushed, iclass 32, count 0 2006.197.07:56:28.84#ibcon#about to write, iclass 32, count 0 2006.197.07:56:28.84#ibcon#wrote, iclass 32, count 0 2006.197.07:56:28.84#ibcon#about to read 3, iclass 32, count 0 2006.197.07:56:28.86#ibcon#read 3, iclass 32, count 0 2006.197.07:56:28.86#ibcon#about to read 4, iclass 32, count 0 2006.197.07:56:28.86#ibcon#read 4, iclass 32, count 0 2006.197.07:56:28.86#ibcon#about to read 5, iclass 32, count 0 2006.197.07:56:28.86#ibcon#read 5, iclass 32, count 0 2006.197.07:56:28.86#ibcon#about to read 6, iclass 32, count 0 2006.197.07:56:28.86#ibcon#read 6, iclass 32, count 0 2006.197.07:56:28.86#ibcon#end of sib2, iclass 32, count 0 2006.197.07:56:28.86#ibcon#*mode == 0, iclass 32, count 0 2006.197.07:56:28.86#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.197.07:56:28.86#ibcon#[26=FRQ=05,652.99\r\n] 2006.197.07:56:28.86#ibcon#*before write, iclass 32, count 0 2006.197.07:56:28.86#ibcon#enter sib2, iclass 32, count 0 2006.197.07:56:28.86#ibcon#flushed, iclass 32, count 0 2006.197.07:56:28.86#ibcon#about to write, iclass 32, count 0 2006.197.07:56:28.86#ibcon#wrote, iclass 32, count 0 2006.197.07:56:28.86#ibcon#about to read 3, iclass 32, count 0 2006.197.07:56:28.90#ibcon#read 3, iclass 32, count 0 2006.197.07:56:28.90#ibcon#about to read 4, iclass 32, count 0 2006.197.07:56:28.90#ibcon#read 4, iclass 32, count 0 2006.197.07:56:28.90#ibcon#about to read 5, iclass 32, count 0 2006.197.07:56:28.90#ibcon#read 5, iclass 32, count 0 2006.197.07:56:28.90#ibcon#about to read 6, iclass 32, count 0 2006.197.07:56:28.90#ibcon#read 6, iclass 32, count 0 2006.197.07:56:28.90#ibcon#end of sib2, iclass 32, count 0 2006.197.07:56:28.90#ibcon#*after write, iclass 32, count 0 2006.197.07:56:28.90#ibcon#*before return 0, iclass 32, count 0 2006.197.07:56:28.90#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.197.07:56:28.90#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.197.07:56:28.90#ibcon#about to clear, iclass 32 cls_cnt 0 2006.197.07:56:28.90#ibcon#cleared, iclass 32 cls_cnt 0 2006.197.07:56:28.90$vc4f8/va=5,7 2006.197.07:56:28.90#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.197.07:56:28.90#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.197.07:56:28.90#ibcon#ireg 11 cls_cnt 2 2006.197.07:56:28.90#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.197.07:56:28.96#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.197.07:56:28.96#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.197.07:56:28.96#ibcon#enter wrdev, iclass 34, count 2 2006.197.07:56:28.96#ibcon#first serial, iclass 34, count 2 2006.197.07:56:28.96#ibcon#enter sib2, iclass 34, count 2 2006.197.07:56:28.96#ibcon#flushed, iclass 34, count 2 2006.197.07:56:28.96#ibcon#about to write, iclass 34, count 2 2006.197.07:56:28.96#ibcon#wrote, iclass 34, count 2 2006.197.07:56:28.96#ibcon#about to read 3, iclass 34, count 2 2006.197.07:56:28.98#ibcon#read 3, iclass 34, count 2 2006.197.07:56:28.98#ibcon#about to read 4, iclass 34, count 2 2006.197.07:56:28.98#ibcon#read 4, iclass 34, count 2 2006.197.07:56:28.98#ibcon#about to read 5, iclass 34, count 2 2006.197.07:56:28.98#ibcon#read 5, iclass 34, count 2 2006.197.07:56:28.98#ibcon#about to read 6, iclass 34, count 2 2006.197.07:56:28.98#ibcon#read 6, iclass 34, count 2 2006.197.07:56:28.98#ibcon#end of sib2, iclass 34, count 2 2006.197.07:56:28.98#ibcon#*mode == 0, iclass 34, count 2 2006.197.07:56:28.98#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.197.07:56:28.98#ibcon#[25=AT05-07\r\n] 2006.197.07:56:28.98#ibcon#*before write, iclass 34, count 2 2006.197.07:56:28.98#ibcon#enter sib2, iclass 34, count 2 2006.197.07:56:28.98#ibcon#flushed, iclass 34, count 2 2006.197.07:56:28.98#ibcon#about to write, iclass 34, count 2 2006.197.07:56:28.98#ibcon#wrote, iclass 34, count 2 2006.197.07:56:28.98#ibcon#about to read 3, iclass 34, count 2 2006.197.07:56:29.01#ibcon#read 3, iclass 34, count 2 2006.197.07:56:29.01#ibcon#about to read 4, iclass 34, count 2 2006.197.07:56:29.01#ibcon#read 4, iclass 34, count 2 2006.197.07:56:29.01#ibcon#about to read 5, iclass 34, count 2 2006.197.07:56:29.01#ibcon#read 5, iclass 34, count 2 2006.197.07:56:29.01#ibcon#about to read 6, iclass 34, count 2 2006.197.07:56:29.01#ibcon#read 6, iclass 34, count 2 2006.197.07:56:29.01#ibcon#end of sib2, iclass 34, count 2 2006.197.07:56:29.01#ibcon#*after write, iclass 34, count 2 2006.197.07:56:29.01#ibcon#*before return 0, iclass 34, count 2 2006.197.07:56:29.01#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.197.07:56:29.01#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.197.07:56:29.01#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.197.07:56:29.01#ibcon#ireg 7 cls_cnt 0 2006.197.07:56:29.01#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.197.07:56:29.13#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.197.07:56:29.13#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.197.07:56:29.13#ibcon#enter wrdev, iclass 34, count 0 2006.197.07:56:29.13#ibcon#first serial, iclass 34, count 0 2006.197.07:56:29.13#ibcon#enter sib2, iclass 34, count 0 2006.197.07:56:29.13#ibcon#flushed, iclass 34, count 0 2006.197.07:56:29.13#ibcon#about to write, iclass 34, count 0 2006.197.07:56:29.13#ibcon#wrote, iclass 34, count 0 2006.197.07:56:29.13#ibcon#about to read 3, iclass 34, count 0 2006.197.07:56:29.15#ibcon#read 3, iclass 34, count 0 2006.197.07:56:29.15#ibcon#about to read 4, iclass 34, count 0 2006.197.07:56:29.15#ibcon#read 4, iclass 34, count 0 2006.197.07:56:29.15#ibcon#about to read 5, iclass 34, count 0 2006.197.07:56:29.15#ibcon#read 5, iclass 34, count 0 2006.197.07:56:29.15#ibcon#about to read 6, iclass 34, count 0 2006.197.07:56:29.15#ibcon#read 6, iclass 34, count 0 2006.197.07:56:29.15#ibcon#end of sib2, iclass 34, count 0 2006.197.07:56:29.15#ibcon#*mode == 0, iclass 34, count 0 2006.197.07:56:29.15#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.197.07:56:29.15#ibcon#[25=USB\r\n] 2006.197.07:56:29.15#ibcon#*before write, iclass 34, count 0 2006.197.07:56:29.15#ibcon#enter sib2, iclass 34, count 0 2006.197.07:56:29.15#ibcon#flushed, iclass 34, count 0 2006.197.07:56:29.15#ibcon#about to write, iclass 34, count 0 2006.197.07:56:29.15#ibcon#wrote, iclass 34, count 0 2006.197.07:56:29.15#ibcon#about to read 3, iclass 34, count 0 2006.197.07:56:29.18#ibcon#read 3, iclass 34, count 0 2006.197.07:56:29.18#ibcon#about to read 4, iclass 34, count 0 2006.197.07:56:29.18#ibcon#read 4, iclass 34, count 0 2006.197.07:56:29.18#ibcon#about to read 5, iclass 34, count 0 2006.197.07:56:29.18#ibcon#read 5, iclass 34, count 0 2006.197.07:56:29.18#ibcon#about to read 6, iclass 34, count 0 2006.197.07:56:29.18#ibcon#read 6, iclass 34, count 0 2006.197.07:56:29.18#ibcon#end of sib2, iclass 34, count 0 2006.197.07:56:29.18#ibcon#*after write, iclass 34, count 0 2006.197.07:56:29.18#ibcon#*before return 0, iclass 34, count 0 2006.197.07:56:29.18#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.197.07:56:29.18#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.197.07:56:29.18#ibcon#about to clear, iclass 34 cls_cnt 0 2006.197.07:56:29.18#ibcon#cleared, iclass 34 cls_cnt 0 2006.197.07:56:29.18$vc4f8/valo=6,772.99 2006.197.07:56:29.18#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.197.07:56:29.18#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.197.07:56:29.18#ibcon#ireg 17 cls_cnt 0 2006.197.07:56:29.18#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.197.07:56:29.18#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.197.07:56:29.18#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.197.07:56:29.18#ibcon#enter wrdev, iclass 36, count 0 2006.197.07:56:29.18#ibcon#first serial, iclass 36, count 0 2006.197.07:56:29.18#ibcon#enter sib2, iclass 36, count 0 2006.197.07:56:29.18#ibcon#flushed, iclass 36, count 0 2006.197.07:56:29.18#ibcon#about to write, iclass 36, count 0 2006.197.07:56:29.18#ibcon#wrote, iclass 36, count 0 2006.197.07:56:29.18#ibcon#about to read 3, iclass 36, count 0 2006.197.07:56:29.20#ibcon#read 3, iclass 36, count 0 2006.197.07:56:29.20#ibcon#about to read 4, iclass 36, count 0 2006.197.07:56:29.20#ibcon#read 4, iclass 36, count 0 2006.197.07:56:29.20#ibcon#about to read 5, iclass 36, count 0 2006.197.07:56:29.20#ibcon#read 5, iclass 36, count 0 2006.197.07:56:29.20#ibcon#about to read 6, iclass 36, count 0 2006.197.07:56:29.20#ibcon#read 6, iclass 36, count 0 2006.197.07:56:29.20#ibcon#end of sib2, iclass 36, count 0 2006.197.07:56:29.20#ibcon#*mode == 0, iclass 36, count 0 2006.197.07:56:29.20#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.197.07:56:29.20#ibcon#[26=FRQ=06,772.99\r\n] 2006.197.07:56:29.20#ibcon#*before write, iclass 36, count 0 2006.197.07:56:29.20#ibcon#enter sib2, iclass 36, count 0 2006.197.07:56:29.20#ibcon#flushed, iclass 36, count 0 2006.197.07:56:29.20#ibcon#about to write, iclass 36, count 0 2006.197.07:56:29.20#ibcon#wrote, iclass 36, count 0 2006.197.07:56:29.20#ibcon#about to read 3, iclass 36, count 0 2006.197.07:56:29.24#ibcon#read 3, iclass 36, count 0 2006.197.07:56:29.24#ibcon#about to read 4, iclass 36, count 0 2006.197.07:56:29.24#ibcon#read 4, iclass 36, count 0 2006.197.07:56:29.24#ibcon#about to read 5, iclass 36, count 0 2006.197.07:56:29.24#ibcon#read 5, iclass 36, count 0 2006.197.07:56:29.24#ibcon#about to read 6, iclass 36, count 0 2006.197.07:56:29.24#ibcon#read 6, iclass 36, count 0 2006.197.07:56:29.24#ibcon#end of sib2, iclass 36, count 0 2006.197.07:56:29.24#ibcon#*after write, iclass 36, count 0 2006.197.07:56:29.24#ibcon#*before return 0, iclass 36, count 0 2006.197.07:56:29.24#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.197.07:56:29.24#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.197.07:56:29.24#ibcon#about to clear, iclass 36 cls_cnt 0 2006.197.07:56:29.24#ibcon#cleared, iclass 36 cls_cnt 0 2006.197.07:56:29.24$vc4f8/va=6,6 2006.197.07:56:29.24#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.197.07:56:29.24#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.197.07:56:29.24#ibcon#ireg 11 cls_cnt 2 2006.197.07:56:29.24#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.197.07:56:29.30#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.197.07:56:29.30#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.197.07:56:29.30#ibcon#enter wrdev, iclass 38, count 2 2006.197.07:56:29.30#ibcon#first serial, iclass 38, count 2 2006.197.07:56:29.30#ibcon#enter sib2, iclass 38, count 2 2006.197.07:56:29.30#ibcon#flushed, iclass 38, count 2 2006.197.07:56:29.30#ibcon#about to write, iclass 38, count 2 2006.197.07:56:29.30#ibcon#wrote, iclass 38, count 2 2006.197.07:56:29.30#ibcon#about to read 3, iclass 38, count 2 2006.197.07:56:29.32#ibcon#read 3, iclass 38, count 2 2006.197.07:56:29.32#ibcon#about to read 4, iclass 38, count 2 2006.197.07:56:29.32#ibcon#read 4, iclass 38, count 2 2006.197.07:56:29.32#ibcon#about to read 5, iclass 38, count 2 2006.197.07:56:29.32#ibcon#read 5, iclass 38, count 2 2006.197.07:56:29.32#ibcon#about to read 6, iclass 38, count 2 2006.197.07:56:29.32#ibcon#read 6, iclass 38, count 2 2006.197.07:56:29.32#ibcon#end of sib2, iclass 38, count 2 2006.197.07:56:29.32#ibcon#*mode == 0, iclass 38, count 2 2006.197.07:56:29.32#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.197.07:56:29.32#ibcon#[25=AT06-06\r\n] 2006.197.07:56:29.32#ibcon#*before write, iclass 38, count 2 2006.197.07:56:29.32#ibcon#enter sib2, iclass 38, count 2 2006.197.07:56:29.32#ibcon#flushed, iclass 38, count 2 2006.197.07:56:29.32#ibcon#about to write, iclass 38, count 2 2006.197.07:56:29.32#ibcon#wrote, iclass 38, count 2 2006.197.07:56:29.32#ibcon#about to read 3, iclass 38, count 2 2006.197.07:56:29.35#ibcon#read 3, iclass 38, count 2 2006.197.07:56:29.35#ibcon#about to read 4, iclass 38, count 2 2006.197.07:56:29.35#ibcon#read 4, iclass 38, count 2 2006.197.07:56:29.35#ibcon#about to read 5, iclass 38, count 2 2006.197.07:56:29.35#ibcon#read 5, iclass 38, count 2 2006.197.07:56:29.35#ibcon#about to read 6, iclass 38, count 2 2006.197.07:56:29.35#ibcon#read 6, iclass 38, count 2 2006.197.07:56:29.35#ibcon#end of sib2, iclass 38, count 2 2006.197.07:56:29.35#ibcon#*after write, iclass 38, count 2 2006.197.07:56:29.35#ibcon#*before return 0, iclass 38, count 2 2006.197.07:56:29.35#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.197.07:56:29.35#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.197.07:56:29.35#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.197.07:56:29.35#ibcon#ireg 7 cls_cnt 0 2006.197.07:56:29.35#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.197.07:56:29.47#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.197.07:56:29.47#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.197.07:56:29.47#ibcon#enter wrdev, iclass 38, count 0 2006.197.07:56:29.47#ibcon#first serial, iclass 38, count 0 2006.197.07:56:29.47#ibcon#enter sib2, iclass 38, count 0 2006.197.07:56:29.47#ibcon#flushed, iclass 38, count 0 2006.197.07:56:29.47#ibcon#about to write, iclass 38, count 0 2006.197.07:56:29.47#ibcon#wrote, iclass 38, count 0 2006.197.07:56:29.47#ibcon#about to read 3, iclass 38, count 0 2006.197.07:56:29.49#ibcon#read 3, iclass 38, count 0 2006.197.07:56:29.49#ibcon#about to read 4, iclass 38, count 0 2006.197.07:56:29.49#ibcon#read 4, iclass 38, count 0 2006.197.07:56:29.49#ibcon#about to read 5, iclass 38, count 0 2006.197.07:56:29.49#ibcon#read 5, iclass 38, count 0 2006.197.07:56:29.49#ibcon#about to read 6, iclass 38, count 0 2006.197.07:56:29.49#ibcon#read 6, iclass 38, count 0 2006.197.07:56:29.49#ibcon#end of sib2, iclass 38, count 0 2006.197.07:56:29.49#ibcon#*mode == 0, iclass 38, count 0 2006.197.07:56:29.49#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.197.07:56:29.49#ibcon#[25=USB\r\n] 2006.197.07:56:29.49#ibcon#*before write, iclass 38, count 0 2006.197.07:56:29.49#ibcon#enter sib2, iclass 38, count 0 2006.197.07:56:29.49#ibcon#flushed, iclass 38, count 0 2006.197.07:56:29.49#ibcon#about to write, iclass 38, count 0 2006.197.07:56:29.49#ibcon#wrote, iclass 38, count 0 2006.197.07:56:29.49#ibcon#about to read 3, iclass 38, count 0 2006.197.07:56:29.52#ibcon#read 3, iclass 38, count 0 2006.197.07:56:29.52#ibcon#about to read 4, iclass 38, count 0 2006.197.07:56:29.52#ibcon#read 4, iclass 38, count 0 2006.197.07:56:29.52#ibcon#about to read 5, iclass 38, count 0 2006.197.07:56:29.52#ibcon#read 5, iclass 38, count 0 2006.197.07:56:29.52#ibcon#about to read 6, iclass 38, count 0 2006.197.07:56:29.52#ibcon#read 6, iclass 38, count 0 2006.197.07:56:29.52#ibcon#end of sib2, iclass 38, count 0 2006.197.07:56:29.52#ibcon#*after write, iclass 38, count 0 2006.197.07:56:29.52#ibcon#*before return 0, iclass 38, count 0 2006.197.07:56:29.52#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.197.07:56:29.52#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.197.07:56:29.52#ibcon#about to clear, iclass 38 cls_cnt 0 2006.197.07:56:29.52#ibcon#cleared, iclass 38 cls_cnt 0 2006.197.07:56:29.52$vc4f8/valo=7,832.99 2006.197.07:56:29.52#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.197.07:56:29.52#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.197.07:56:29.52#ibcon#ireg 17 cls_cnt 0 2006.197.07:56:29.52#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.197.07:56:29.52#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.197.07:56:29.52#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.197.07:56:29.52#ibcon#enter wrdev, iclass 40, count 0 2006.197.07:56:29.52#ibcon#first serial, iclass 40, count 0 2006.197.07:56:29.52#ibcon#enter sib2, iclass 40, count 0 2006.197.07:56:29.52#ibcon#flushed, iclass 40, count 0 2006.197.07:56:29.52#ibcon#about to write, iclass 40, count 0 2006.197.07:56:29.52#ibcon#wrote, iclass 40, count 0 2006.197.07:56:29.52#ibcon#about to read 3, iclass 40, count 0 2006.197.07:56:29.54#ibcon#read 3, iclass 40, count 0 2006.197.07:56:29.54#ibcon#about to read 4, iclass 40, count 0 2006.197.07:56:29.54#ibcon#read 4, iclass 40, count 0 2006.197.07:56:29.54#ibcon#about to read 5, iclass 40, count 0 2006.197.07:56:29.54#ibcon#read 5, iclass 40, count 0 2006.197.07:56:29.54#ibcon#about to read 6, iclass 40, count 0 2006.197.07:56:29.54#ibcon#read 6, iclass 40, count 0 2006.197.07:56:29.54#ibcon#end of sib2, iclass 40, count 0 2006.197.07:56:29.54#ibcon#*mode == 0, iclass 40, count 0 2006.197.07:56:29.54#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.197.07:56:29.54#ibcon#[26=FRQ=07,832.99\r\n] 2006.197.07:56:29.54#ibcon#*before write, iclass 40, count 0 2006.197.07:56:29.54#ibcon#enter sib2, iclass 40, count 0 2006.197.07:56:29.54#ibcon#flushed, iclass 40, count 0 2006.197.07:56:29.54#ibcon#about to write, iclass 40, count 0 2006.197.07:56:29.54#ibcon#wrote, iclass 40, count 0 2006.197.07:56:29.54#ibcon#about to read 3, iclass 40, count 0 2006.197.07:56:29.58#ibcon#read 3, iclass 40, count 0 2006.197.07:56:29.58#ibcon#about to read 4, iclass 40, count 0 2006.197.07:56:29.58#ibcon#read 4, iclass 40, count 0 2006.197.07:56:29.58#ibcon#about to read 5, iclass 40, count 0 2006.197.07:56:29.58#ibcon#read 5, iclass 40, count 0 2006.197.07:56:29.58#ibcon#about to read 6, iclass 40, count 0 2006.197.07:56:29.58#ibcon#read 6, iclass 40, count 0 2006.197.07:56:29.58#ibcon#end of sib2, iclass 40, count 0 2006.197.07:56:29.58#ibcon#*after write, iclass 40, count 0 2006.197.07:56:29.58#ibcon#*before return 0, iclass 40, count 0 2006.197.07:56:29.58#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.197.07:56:29.58#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.197.07:56:29.58#ibcon#about to clear, iclass 40 cls_cnt 0 2006.197.07:56:29.58#ibcon#cleared, iclass 40 cls_cnt 0 2006.197.07:56:29.58$vc4f8/va=7,6 2006.197.07:56:29.58#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.197.07:56:29.58#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.197.07:56:29.58#ibcon#ireg 11 cls_cnt 2 2006.197.07:56:29.58#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.197.07:56:29.64#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.197.07:56:29.64#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.197.07:56:29.64#ibcon#enter wrdev, iclass 4, count 2 2006.197.07:56:29.64#ibcon#first serial, iclass 4, count 2 2006.197.07:56:29.64#ibcon#enter sib2, iclass 4, count 2 2006.197.07:56:29.64#ibcon#flushed, iclass 4, count 2 2006.197.07:56:29.64#ibcon#about to write, iclass 4, count 2 2006.197.07:56:29.64#ibcon#wrote, iclass 4, count 2 2006.197.07:56:29.64#ibcon#about to read 3, iclass 4, count 2 2006.197.07:56:29.66#ibcon#read 3, iclass 4, count 2 2006.197.07:56:29.66#ibcon#about to read 4, iclass 4, count 2 2006.197.07:56:29.66#ibcon#read 4, iclass 4, count 2 2006.197.07:56:29.66#ibcon#about to read 5, iclass 4, count 2 2006.197.07:56:29.66#ibcon#read 5, iclass 4, count 2 2006.197.07:56:29.66#ibcon#about to read 6, iclass 4, count 2 2006.197.07:56:29.66#ibcon#read 6, iclass 4, count 2 2006.197.07:56:29.66#ibcon#end of sib2, iclass 4, count 2 2006.197.07:56:29.66#ibcon#*mode == 0, iclass 4, count 2 2006.197.07:56:29.66#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.197.07:56:29.66#ibcon#[25=AT07-06\r\n] 2006.197.07:56:29.66#ibcon#*before write, iclass 4, count 2 2006.197.07:56:29.66#ibcon#enter sib2, iclass 4, count 2 2006.197.07:56:29.66#ibcon#flushed, iclass 4, count 2 2006.197.07:56:29.66#ibcon#about to write, iclass 4, count 2 2006.197.07:56:29.66#ibcon#wrote, iclass 4, count 2 2006.197.07:56:29.66#ibcon#about to read 3, iclass 4, count 2 2006.197.07:56:29.69#ibcon#read 3, iclass 4, count 2 2006.197.07:56:29.69#ibcon#about to read 4, iclass 4, count 2 2006.197.07:56:29.69#ibcon#read 4, iclass 4, count 2 2006.197.07:56:29.69#ibcon#about to read 5, iclass 4, count 2 2006.197.07:56:29.69#ibcon#read 5, iclass 4, count 2 2006.197.07:56:29.69#ibcon#about to read 6, iclass 4, count 2 2006.197.07:56:29.69#ibcon#read 6, iclass 4, count 2 2006.197.07:56:29.69#ibcon#end of sib2, iclass 4, count 2 2006.197.07:56:29.69#ibcon#*after write, iclass 4, count 2 2006.197.07:56:29.69#ibcon#*before return 0, iclass 4, count 2 2006.197.07:56:29.69#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.197.07:56:29.69#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.197.07:56:29.69#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.197.07:56:29.69#ibcon#ireg 7 cls_cnt 0 2006.197.07:56:29.69#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.197.07:56:29.81#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.197.07:56:29.81#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.197.07:56:29.81#ibcon#enter wrdev, iclass 4, count 0 2006.197.07:56:29.81#ibcon#first serial, iclass 4, count 0 2006.197.07:56:29.81#ibcon#enter sib2, iclass 4, count 0 2006.197.07:56:29.81#ibcon#flushed, iclass 4, count 0 2006.197.07:56:29.81#ibcon#about to write, iclass 4, count 0 2006.197.07:56:29.81#ibcon#wrote, iclass 4, count 0 2006.197.07:56:29.81#ibcon#about to read 3, iclass 4, count 0 2006.197.07:56:29.83#ibcon#read 3, iclass 4, count 0 2006.197.07:56:29.83#ibcon#about to read 4, iclass 4, count 0 2006.197.07:56:29.83#ibcon#read 4, iclass 4, count 0 2006.197.07:56:29.83#ibcon#about to read 5, iclass 4, count 0 2006.197.07:56:29.83#ibcon#read 5, iclass 4, count 0 2006.197.07:56:29.83#ibcon#about to read 6, iclass 4, count 0 2006.197.07:56:29.83#ibcon#read 6, iclass 4, count 0 2006.197.07:56:29.83#ibcon#end of sib2, iclass 4, count 0 2006.197.07:56:29.83#ibcon#*mode == 0, iclass 4, count 0 2006.197.07:56:29.83#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.197.07:56:29.83#ibcon#[25=USB\r\n] 2006.197.07:56:29.83#ibcon#*before write, iclass 4, count 0 2006.197.07:56:29.83#ibcon#enter sib2, iclass 4, count 0 2006.197.07:56:29.83#ibcon#flushed, iclass 4, count 0 2006.197.07:56:29.83#ibcon#about to write, iclass 4, count 0 2006.197.07:56:29.83#ibcon#wrote, iclass 4, count 0 2006.197.07:56:29.83#ibcon#about to read 3, iclass 4, count 0 2006.197.07:56:29.86#ibcon#read 3, iclass 4, count 0 2006.197.07:56:29.86#ibcon#about to read 4, iclass 4, count 0 2006.197.07:56:29.86#ibcon#read 4, iclass 4, count 0 2006.197.07:56:29.86#ibcon#about to read 5, iclass 4, count 0 2006.197.07:56:29.86#ibcon#read 5, iclass 4, count 0 2006.197.07:56:29.86#ibcon#about to read 6, iclass 4, count 0 2006.197.07:56:29.86#ibcon#read 6, iclass 4, count 0 2006.197.07:56:29.86#ibcon#end of sib2, iclass 4, count 0 2006.197.07:56:29.86#ibcon#*after write, iclass 4, count 0 2006.197.07:56:29.86#ibcon#*before return 0, iclass 4, count 0 2006.197.07:56:29.86#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.197.07:56:29.86#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.197.07:56:29.86#ibcon#about to clear, iclass 4 cls_cnt 0 2006.197.07:56:29.86#ibcon#cleared, iclass 4 cls_cnt 0 2006.197.07:56:29.86$vc4f8/valo=8,852.99 2006.197.07:56:29.86#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.197.07:56:29.86#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.197.07:56:29.86#ibcon#ireg 17 cls_cnt 0 2006.197.07:56:29.86#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.197.07:56:29.86#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.197.07:56:29.86#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.197.07:56:29.86#ibcon#enter wrdev, iclass 6, count 0 2006.197.07:56:29.86#ibcon#first serial, iclass 6, count 0 2006.197.07:56:29.86#ibcon#enter sib2, iclass 6, count 0 2006.197.07:56:29.86#ibcon#flushed, iclass 6, count 0 2006.197.07:56:29.86#ibcon#about to write, iclass 6, count 0 2006.197.07:56:29.86#ibcon#wrote, iclass 6, count 0 2006.197.07:56:29.86#ibcon#about to read 3, iclass 6, count 0 2006.197.07:56:29.88#ibcon#read 3, iclass 6, count 0 2006.197.07:56:29.88#ibcon#about to read 4, iclass 6, count 0 2006.197.07:56:29.88#ibcon#read 4, iclass 6, count 0 2006.197.07:56:29.88#ibcon#about to read 5, iclass 6, count 0 2006.197.07:56:29.88#ibcon#read 5, iclass 6, count 0 2006.197.07:56:29.88#ibcon#about to read 6, iclass 6, count 0 2006.197.07:56:29.88#ibcon#read 6, iclass 6, count 0 2006.197.07:56:29.88#ibcon#end of sib2, iclass 6, count 0 2006.197.07:56:29.88#ibcon#*mode == 0, iclass 6, count 0 2006.197.07:56:29.88#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.197.07:56:29.88#ibcon#[26=FRQ=08,852.99\r\n] 2006.197.07:56:29.88#ibcon#*before write, iclass 6, count 0 2006.197.07:56:29.88#ibcon#enter sib2, iclass 6, count 0 2006.197.07:56:29.88#ibcon#flushed, iclass 6, count 0 2006.197.07:56:29.88#ibcon#about to write, iclass 6, count 0 2006.197.07:56:29.88#ibcon#wrote, iclass 6, count 0 2006.197.07:56:29.88#ibcon#about to read 3, iclass 6, count 0 2006.197.07:56:29.92#ibcon#read 3, iclass 6, count 0 2006.197.07:56:29.92#ibcon#about to read 4, iclass 6, count 0 2006.197.07:56:29.92#ibcon#read 4, iclass 6, count 0 2006.197.07:56:29.92#ibcon#about to read 5, iclass 6, count 0 2006.197.07:56:29.92#ibcon#read 5, iclass 6, count 0 2006.197.07:56:29.92#ibcon#about to read 6, iclass 6, count 0 2006.197.07:56:29.92#ibcon#read 6, iclass 6, count 0 2006.197.07:56:29.92#ibcon#end of sib2, iclass 6, count 0 2006.197.07:56:29.92#ibcon#*after write, iclass 6, count 0 2006.197.07:56:29.92#ibcon#*before return 0, iclass 6, count 0 2006.197.07:56:29.92#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.197.07:56:29.92#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.197.07:56:29.92#ibcon#about to clear, iclass 6 cls_cnt 0 2006.197.07:56:29.92#ibcon#cleared, iclass 6 cls_cnt 0 2006.197.07:56:29.92$vc4f8/va=8,7 2006.197.07:56:29.92#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.197.07:56:29.92#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.197.07:56:29.92#ibcon#ireg 11 cls_cnt 2 2006.197.07:56:29.92#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.197.07:56:29.98#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.197.07:56:29.98#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.197.07:56:29.98#ibcon#enter wrdev, iclass 10, count 2 2006.197.07:56:29.98#ibcon#first serial, iclass 10, count 2 2006.197.07:56:29.98#ibcon#enter sib2, iclass 10, count 2 2006.197.07:56:29.98#ibcon#flushed, iclass 10, count 2 2006.197.07:56:29.98#ibcon#about to write, iclass 10, count 2 2006.197.07:56:29.98#ibcon#wrote, iclass 10, count 2 2006.197.07:56:29.98#ibcon#about to read 3, iclass 10, count 2 2006.197.07:56:30.00#ibcon#read 3, iclass 10, count 2 2006.197.07:56:30.00#ibcon#about to read 4, iclass 10, count 2 2006.197.07:56:30.00#ibcon#read 4, iclass 10, count 2 2006.197.07:56:30.00#ibcon#about to read 5, iclass 10, count 2 2006.197.07:56:30.00#ibcon#read 5, iclass 10, count 2 2006.197.07:56:30.00#ibcon#about to read 6, iclass 10, count 2 2006.197.07:56:30.00#ibcon#read 6, iclass 10, count 2 2006.197.07:56:30.00#ibcon#end of sib2, iclass 10, count 2 2006.197.07:56:30.00#ibcon#*mode == 0, iclass 10, count 2 2006.197.07:56:30.00#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.197.07:56:30.00#ibcon#[25=AT08-07\r\n] 2006.197.07:56:30.00#ibcon#*before write, iclass 10, count 2 2006.197.07:56:30.00#ibcon#enter sib2, iclass 10, count 2 2006.197.07:56:30.00#ibcon#flushed, iclass 10, count 2 2006.197.07:56:30.00#ibcon#about to write, iclass 10, count 2 2006.197.07:56:30.00#ibcon#wrote, iclass 10, count 2 2006.197.07:56:30.00#ibcon#about to read 3, iclass 10, count 2 2006.197.07:56:30.03#ibcon#read 3, iclass 10, count 2 2006.197.07:56:30.03#ibcon#about to read 4, iclass 10, count 2 2006.197.07:56:30.03#ibcon#read 4, iclass 10, count 2 2006.197.07:56:30.03#ibcon#about to read 5, iclass 10, count 2 2006.197.07:56:30.03#ibcon#read 5, iclass 10, count 2 2006.197.07:56:30.03#ibcon#about to read 6, iclass 10, count 2 2006.197.07:56:30.03#ibcon#read 6, iclass 10, count 2 2006.197.07:56:30.03#ibcon#end of sib2, iclass 10, count 2 2006.197.07:56:30.03#ibcon#*after write, iclass 10, count 2 2006.197.07:56:30.03#ibcon#*before return 0, iclass 10, count 2 2006.197.07:56:30.03#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.197.07:56:30.03#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.197.07:56:30.03#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.197.07:56:30.03#ibcon#ireg 7 cls_cnt 0 2006.197.07:56:30.03#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.197.07:56:30.15#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.197.07:56:30.15#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.197.07:56:30.15#ibcon#enter wrdev, iclass 10, count 0 2006.197.07:56:30.15#ibcon#first serial, iclass 10, count 0 2006.197.07:56:30.15#ibcon#enter sib2, iclass 10, count 0 2006.197.07:56:30.15#ibcon#flushed, iclass 10, count 0 2006.197.07:56:30.15#ibcon#about to write, iclass 10, count 0 2006.197.07:56:30.15#ibcon#wrote, iclass 10, count 0 2006.197.07:56:30.15#ibcon#about to read 3, iclass 10, count 0 2006.197.07:56:30.17#ibcon#read 3, iclass 10, count 0 2006.197.07:56:30.17#ibcon#about to read 4, iclass 10, count 0 2006.197.07:56:30.17#ibcon#read 4, iclass 10, count 0 2006.197.07:56:30.17#ibcon#about to read 5, iclass 10, count 0 2006.197.07:56:30.17#ibcon#read 5, iclass 10, count 0 2006.197.07:56:30.17#ibcon#about to read 6, iclass 10, count 0 2006.197.07:56:30.17#ibcon#read 6, iclass 10, count 0 2006.197.07:56:30.17#ibcon#end of sib2, iclass 10, count 0 2006.197.07:56:30.17#ibcon#*mode == 0, iclass 10, count 0 2006.197.07:56:30.17#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.197.07:56:30.17#ibcon#[25=USB\r\n] 2006.197.07:56:30.17#ibcon#*before write, iclass 10, count 0 2006.197.07:56:30.17#ibcon#enter sib2, iclass 10, count 0 2006.197.07:56:30.17#ibcon#flushed, iclass 10, count 0 2006.197.07:56:30.17#ibcon#about to write, iclass 10, count 0 2006.197.07:56:30.17#ibcon#wrote, iclass 10, count 0 2006.197.07:56:30.17#ibcon#about to read 3, iclass 10, count 0 2006.197.07:56:30.20#ibcon#read 3, iclass 10, count 0 2006.197.07:56:30.20#ibcon#about to read 4, iclass 10, count 0 2006.197.07:56:30.20#ibcon#read 4, iclass 10, count 0 2006.197.07:56:30.20#ibcon#about to read 5, iclass 10, count 0 2006.197.07:56:30.20#ibcon#read 5, iclass 10, count 0 2006.197.07:56:30.20#ibcon#about to read 6, iclass 10, count 0 2006.197.07:56:30.20#ibcon#read 6, iclass 10, count 0 2006.197.07:56:30.20#ibcon#end of sib2, iclass 10, count 0 2006.197.07:56:30.20#ibcon#*after write, iclass 10, count 0 2006.197.07:56:30.20#ibcon#*before return 0, iclass 10, count 0 2006.197.07:56:30.20#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.197.07:56:30.20#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.197.07:56:30.20#ibcon#about to clear, iclass 10 cls_cnt 0 2006.197.07:56:30.20#ibcon#cleared, iclass 10 cls_cnt 0 2006.197.07:56:30.20$vc4f8/vblo=1,632.99 2006.197.07:56:30.20#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.197.07:56:30.20#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.197.07:56:30.20#ibcon#ireg 17 cls_cnt 0 2006.197.07:56:30.20#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.197.07:56:30.20#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.197.07:56:30.20#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.197.07:56:30.20#ibcon#enter wrdev, iclass 12, count 0 2006.197.07:56:30.20#ibcon#first serial, iclass 12, count 0 2006.197.07:56:30.20#ibcon#enter sib2, iclass 12, count 0 2006.197.07:56:30.20#ibcon#flushed, iclass 12, count 0 2006.197.07:56:30.20#ibcon#about to write, iclass 12, count 0 2006.197.07:56:30.20#ibcon#wrote, iclass 12, count 0 2006.197.07:56:30.20#ibcon#about to read 3, iclass 12, count 0 2006.197.07:56:30.22#ibcon#read 3, iclass 12, count 0 2006.197.07:56:30.22#ibcon#about to read 4, iclass 12, count 0 2006.197.07:56:30.22#ibcon#read 4, iclass 12, count 0 2006.197.07:56:30.22#ibcon#about to read 5, iclass 12, count 0 2006.197.07:56:30.22#ibcon#read 5, iclass 12, count 0 2006.197.07:56:30.22#ibcon#about to read 6, iclass 12, count 0 2006.197.07:56:30.22#ibcon#read 6, iclass 12, count 0 2006.197.07:56:30.22#ibcon#end of sib2, iclass 12, count 0 2006.197.07:56:30.22#ibcon#*mode == 0, iclass 12, count 0 2006.197.07:56:30.22#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.197.07:56:30.22#ibcon#[28=FRQ=01,632.99\r\n] 2006.197.07:56:30.22#ibcon#*before write, iclass 12, count 0 2006.197.07:56:30.22#ibcon#enter sib2, iclass 12, count 0 2006.197.07:56:30.22#ibcon#flushed, iclass 12, count 0 2006.197.07:56:30.22#ibcon#about to write, iclass 12, count 0 2006.197.07:56:30.22#ibcon#wrote, iclass 12, count 0 2006.197.07:56:30.22#ibcon#about to read 3, iclass 12, count 0 2006.197.07:56:30.26#ibcon#read 3, iclass 12, count 0 2006.197.07:56:30.26#ibcon#about to read 4, iclass 12, count 0 2006.197.07:56:30.26#ibcon#read 4, iclass 12, count 0 2006.197.07:56:30.26#ibcon#about to read 5, iclass 12, count 0 2006.197.07:56:30.26#ibcon#read 5, iclass 12, count 0 2006.197.07:56:30.26#ibcon#about to read 6, iclass 12, count 0 2006.197.07:56:30.26#ibcon#read 6, iclass 12, count 0 2006.197.07:56:30.26#ibcon#end of sib2, iclass 12, count 0 2006.197.07:56:30.26#ibcon#*after write, iclass 12, count 0 2006.197.07:56:30.26#ibcon#*before return 0, iclass 12, count 0 2006.197.07:56:30.26#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.197.07:56:30.26#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.197.07:56:30.26#ibcon#about to clear, iclass 12 cls_cnt 0 2006.197.07:56:30.26#ibcon#cleared, iclass 12 cls_cnt 0 2006.197.07:56:30.26$vc4f8/vb=1,4 2006.197.07:56:30.26#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.197.07:56:30.26#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.197.07:56:30.26#ibcon#ireg 11 cls_cnt 2 2006.197.07:56:30.26#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.197.07:56:30.26#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.197.07:56:30.26#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.197.07:56:30.26#ibcon#enter wrdev, iclass 14, count 2 2006.197.07:56:30.26#ibcon#first serial, iclass 14, count 2 2006.197.07:56:30.26#ibcon#enter sib2, iclass 14, count 2 2006.197.07:56:30.26#ibcon#flushed, iclass 14, count 2 2006.197.07:56:30.26#ibcon#about to write, iclass 14, count 2 2006.197.07:56:30.26#ibcon#wrote, iclass 14, count 2 2006.197.07:56:30.26#ibcon#about to read 3, iclass 14, count 2 2006.197.07:56:30.28#ibcon#read 3, iclass 14, count 2 2006.197.07:56:30.28#ibcon#about to read 4, iclass 14, count 2 2006.197.07:56:30.28#ibcon#read 4, iclass 14, count 2 2006.197.07:56:30.28#ibcon#about to read 5, iclass 14, count 2 2006.197.07:56:30.28#ibcon#read 5, iclass 14, count 2 2006.197.07:56:30.28#ibcon#about to read 6, iclass 14, count 2 2006.197.07:56:30.28#ibcon#read 6, iclass 14, count 2 2006.197.07:56:30.28#ibcon#end of sib2, iclass 14, count 2 2006.197.07:56:30.28#ibcon#*mode == 0, iclass 14, count 2 2006.197.07:56:30.28#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.197.07:56:30.28#ibcon#[27=AT01-04\r\n] 2006.197.07:56:30.28#ibcon#*before write, iclass 14, count 2 2006.197.07:56:30.28#ibcon#enter sib2, iclass 14, count 2 2006.197.07:56:30.28#ibcon#flushed, iclass 14, count 2 2006.197.07:56:30.28#ibcon#about to write, iclass 14, count 2 2006.197.07:56:30.28#ibcon#wrote, iclass 14, count 2 2006.197.07:56:30.28#ibcon#about to read 3, iclass 14, count 2 2006.197.07:56:30.31#ibcon#read 3, iclass 14, count 2 2006.197.07:56:30.31#ibcon#about to read 4, iclass 14, count 2 2006.197.07:56:30.31#ibcon#read 4, iclass 14, count 2 2006.197.07:56:30.31#ibcon#about to read 5, iclass 14, count 2 2006.197.07:56:30.31#ibcon#read 5, iclass 14, count 2 2006.197.07:56:30.31#ibcon#about to read 6, iclass 14, count 2 2006.197.07:56:30.31#ibcon#read 6, iclass 14, count 2 2006.197.07:56:30.31#ibcon#end of sib2, iclass 14, count 2 2006.197.07:56:30.31#ibcon#*after write, iclass 14, count 2 2006.197.07:56:30.31#ibcon#*before return 0, iclass 14, count 2 2006.197.07:56:30.31#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.197.07:56:30.31#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.197.07:56:30.31#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.197.07:56:30.31#ibcon#ireg 7 cls_cnt 0 2006.197.07:56:30.31#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.197.07:56:30.43#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.197.07:56:30.43#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.197.07:56:30.43#ibcon#enter wrdev, iclass 14, count 0 2006.197.07:56:30.43#ibcon#first serial, iclass 14, count 0 2006.197.07:56:30.43#ibcon#enter sib2, iclass 14, count 0 2006.197.07:56:30.43#ibcon#flushed, iclass 14, count 0 2006.197.07:56:30.43#ibcon#about to write, iclass 14, count 0 2006.197.07:56:30.43#ibcon#wrote, iclass 14, count 0 2006.197.07:56:30.43#ibcon#about to read 3, iclass 14, count 0 2006.197.07:56:30.45#ibcon#read 3, iclass 14, count 0 2006.197.07:56:30.45#ibcon#about to read 4, iclass 14, count 0 2006.197.07:56:30.45#ibcon#read 4, iclass 14, count 0 2006.197.07:56:30.45#ibcon#about to read 5, iclass 14, count 0 2006.197.07:56:30.45#ibcon#read 5, iclass 14, count 0 2006.197.07:56:30.45#ibcon#about to read 6, iclass 14, count 0 2006.197.07:56:30.45#ibcon#read 6, iclass 14, count 0 2006.197.07:56:30.45#ibcon#end of sib2, iclass 14, count 0 2006.197.07:56:30.45#ibcon#*mode == 0, iclass 14, count 0 2006.197.07:56:30.45#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.197.07:56:30.45#ibcon#[27=USB\r\n] 2006.197.07:56:30.45#ibcon#*before write, iclass 14, count 0 2006.197.07:56:30.45#ibcon#enter sib2, iclass 14, count 0 2006.197.07:56:30.45#ibcon#flushed, iclass 14, count 0 2006.197.07:56:30.45#ibcon#about to write, iclass 14, count 0 2006.197.07:56:30.45#ibcon#wrote, iclass 14, count 0 2006.197.07:56:30.45#ibcon#about to read 3, iclass 14, count 0 2006.197.07:56:30.48#ibcon#read 3, iclass 14, count 0 2006.197.07:56:30.48#ibcon#about to read 4, iclass 14, count 0 2006.197.07:56:30.48#ibcon#read 4, iclass 14, count 0 2006.197.07:56:30.48#ibcon#about to read 5, iclass 14, count 0 2006.197.07:56:30.48#ibcon#read 5, iclass 14, count 0 2006.197.07:56:30.48#ibcon#about to read 6, iclass 14, count 0 2006.197.07:56:30.48#ibcon#read 6, iclass 14, count 0 2006.197.07:56:30.48#ibcon#end of sib2, iclass 14, count 0 2006.197.07:56:30.48#ibcon#*after write, iclass 14, count 0 2006.197.07:56:30.48#ibcon#*before return 0, iclass 14, count 0 2006.197.07:56:30.48#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.197.07:56:30.48#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.197.07:56:30.48#ibcon#about to clear, iclass 14 cls_cnt 0 2006.197.07:56:30.48#ibcon#cleared, iclass 14 cls_cnt 0 2006.197.07:56:30.48$vc4f8/vblo=2,640.99 2006.197.07:56:30.48#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.197.07:56:30.48#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.197.07:56:30.48#ibcon#ireg 17 cls_cnt 0 2006.197.07:56:30.48#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.197.07:56:30.48#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.197.07:56:30.48#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.197.07:56:30.48#ibcon#enter wrdev, iclass 16, count 0 2006.197.07:56:30.48#ibcon#first serial, iclass 16, count 0 2006.197.07:56:30.48#ibcon#enter sib2, iclass 16, count 0 2006.197.07:56:30.48#ibcon#flushed, iclass 16, count 0 2006.197.07:56:30.48#ibcon#about to write, iclass 16, count 0 2006.197.07:56:30.48#ibcon#wrote, iclass 16, count 0 2006.197.07:56:30.48#ibcon#about to read 3, iclass 16, count 0 2006.197.07:56:30.50#ibcon#read 3, iclass 16, count 0 2006.197.07:56:30.50#ibcon#about to read 4, iclass 16, count 0 2006.197.07:56:30.50#ibcon#read 4, iclass 16, count 0 2006.197.07:56:30.50#ibcon#about to read 5, iclass 16, count 0 2006.197.07:56:30.50#ibcon#read 5, iclass 16, count 0 2006.197.07:56:30.50#ibcon#about to read 6, iclass 16, count 0 2006.197.07:56:30.50#ibcon#read 6, iclass 16, count 0 2006.197.07:56:30.50#ibcon#end of sib2, iclass 16, count 0 2006.197.07:56:30.50#ibcon#*mode == 0, iclass 16, count 0 2006.197.07:56:30.50#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.197.07:56:30.50#ibcon#[28=FRQ=02,640.99\r\n] 2006.197.07:56:30.50#ibcon#*before write, iclass 16, count 0 2006.197.07:56:30.50#ibcon#enter sib2, iclass 16, count 0 2006.197.07:56:30.50#ibcon#flushed, iclass 16, count 0 2006.197.07:56:30.50#ibcon#about to write, iclass 16, count 0 2006.197.07:56:30.50#ibcon#wrote, iclass 16, count 0 2006.197.07:56:30.50#ibcon#about to read 3, iclass 16, count 0 2006.197.07:56:30.54#ibcon#read 3, iclass 16, count 0 2006.197.07:56:30.54#ibcon#about to read 4, iclass 16, count 0 2006.197.07:56:30.54#ibcon#read 4, iclass 16, count 0 2006.197.07:56:30.54#ibcon#about to read 5, iclass 16, count 0 2006.197.07:56:30.54#ibcon#read 5, iclass 16, count 0 2006.197.07:56:30.54#ibcon#about to read 6, iclass 16, count 0 2006.197.07:56:30.54#ibcon#read 6, iclass 16, count 0 2006.197.07:56:30.54#ibcon#end of sib2, iclass 16, count 0 2006.197.07:56:30.54#ibcon#*after write, iclass 16, count 0 2006.197.07:56:30.54#ibcon#*before return 0, iclass 16, count 0 2006.197.07:56:30.54#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.197.07:56:30.54#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.197.07:56:30.54#ibcon#about to clear, iclass 16 cls_cnt 0 2006.197.07:56:30.54#ibcon#cleared, iclass 16 cls_cnt 0 2006.197.07:56:30.54$vc4f8/vb=2,4 2006.197.07:56:30.54#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.197.07:56:30.54#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.197.07:56:30.54#ibcon#ireg 11 cls_cnt 2 2006.197.07:56:30.54#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.197.07:56:30.60#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.197.07:56:30.60#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.197.07:56:30.60#ibcon#enter wrdev, iclass 18, count 2 2006.197.07:56:30.60#ibcon#first serial, iclass 18, count 2 2006.197.07:56:30.60#ibcon#enter sib2, iclass 18, count 2 2006.197.07:56:30.60#ibcon#flushed, iclass 18, count 2 2006.197.07:56:30.60#ibcon#about to write, iclass 18, count 2 2006.197.07:56:30.60#ibcon#wrote, iclass 18, count 2 2006.197.07:56:30.60#ibcon#about to read 3, iclass 18, count 2 2006.197.07:56:30.62#ibcon#read 3, iclass 18, count 2 2006.197.07:56:30.62#ibcon#about to read 4, iclass 18, count 2 2006.197.07:56:30.62#ibcon#read 4, iclass 18, count 2 2006.197.07:56:30.62#ibcon#about to read 5, iclass 18, count 2 2006.197.07:56:30.62#ibcon#read 5, iclass 18, count 2 2006.197.07:56:30.62#ibcon#about to read 6, iclass 18, count 2 2006.197.07:56:30.62#ibcon#read 6, iclass 18, count 2 2006.197.07:56:30.62#ibcon#end of sib2, iclass 18, count 2 2006.197.07:56:30.62#ibcon#*mode == 0, iclass 18, count 2 2006.197.07:56:30.62#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.197.07:56:30.62#ibcon#[27=AT02-04\r\n] 2006.197.07:56:30.62#ibcon#*before write, iclass 18, count 2 2006.197.07:56:30.62#ibcon#enter sib2, iclass 18, count 2 2006.197.07:56:30.62#ibcon#flushed, iclass 18, count 2 2006.197.07:56:30.62#ibcon#about to write, iclass 18, count 2 2006.197.07:56:30.62#ibcon#wrote, iclass 18, count 2 2006.197.07:56:30.62#ibcon#about to read 3, iclass 18, count 2 2006.197.07:56:30.65#ibcon#read 3, iclass 18, count 2 2006.197.07:56:30.65#ibcon#about to read 4, iclass 18, count 2 2006.197.07:56:30.65#ibcon#read 4, iclass 18, count 2 2006.197.07:56:30.65#ibcon#about to read 5, iclass 18, count 2 2006.197.07:56:30.65#ibcon#read 5, iclass 18, count 2 2006.197.07:56:30.65#ibcon#about to read 6, iclass 18, count 2 2006.197.07:56:30.65#ibcon#read 6, iclass 18, count 2 2006.197.07:56:30.65#ibcon#end of sib2, iclass 18, count 2 2006.197.07:56:30.65#ibcon#*after write, iclass 18, count 2 2006.197.07:56:30.65#ibcon#*before return 0, iclass 18, count 2 2006.197.07:56:30.65#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.197.07:56:30.65#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.197.07:56:30.65#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.197.07:56:30.65#ibcon#ireg 7 cls_cnt 0 2006.197.07:56:30.65#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.197.07:56:30.77#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.197.07:56:30.77#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.197.07:56:30.77#ibcon#enter wrdev, iclass 18, count 0 2006.197.07:56:30.77#ibcon#first serial, iclass 18, count 0 2006.197.07:56:30.77#ibcon#enter sib2, iclass 18, count 0 2006.197.07:56:30.77#ibcon#flushed, iclass 18, count 0 2006.197.07:56:30.77#ibcon#about to write, iclass 18, count 0 2006.197.07:56:30.77#ibcon#wrote, iclass 18, count 0 2006.197.07:56:30.77#ibcon#about to read 3, iclass 18, count 0 2006.197.07:56:30.79#ibcon#read 3, iclass 18, count 0 2006.197.07:56:30.79#ibcon#about to read 4, iclass 18, count 0 2006.197.07:56:30.79#ibcon#read 4, iclass 18, count 0 2006.197.07:56:30.79#ibcon#about to read 5, iclass 18, count 0 2006.197.07:56:30.79#ibcon#read 5, iclass 18, count 0 2006.197.07:56:30.79#ibcon#about to read 6, iclass 18, count 0 2006.197.07:56:30.79#ibcon#read 6, iclass 18, count 0 2006.197.07:56:30.79#ibcon#end of sib2, iclass 18, count 0 2006.197.07:56:30.79#ibcon#*mode == 0, iclass 18, count 0 2006.197.07:56:30.79#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.197.07:56:30.79#ibcon#[27=USB\r\n] 2006.197.07:56:30.79#ibcon#*before write, iclass 18, count 0 2006.197.07:56:30.79#ibcon#enter sib2, iclass 18, count 0 2006.197.07:56:30.79#ibcon#flushed, iclass 18, count 0 2006.197.07:56:30.79#ibcon#about to write, iclass 18, count 0 2006.197.07:56:30.79#ibcon#wrote, iclass 18, count 0 2006.197.07:56:30.79#ibcon#about to read 3, iclass 18, count 0 2006.197.07:56:30.82#ibcon#read 3, iclass 18, count 0 2006.197.07:56:30.82#ibcon#about to read 4, iclass 18, count 0 2006.197.07:56:30.82#ibcon#read 4, iclass 18, count 0 2006.197.07:56:30.82#ibcon#about to read 5, iclass 18, count 0 2006.197.07:56:30.82#ibcon#read 5, iclass 18, count 0 2006.197.07:56:30.82#ibcon#about to read 6, iclass 18, count 0 2006.197.07:56:30.82#ibcon#read 6, iclass 18, count 0 2006.197.07:56:30.82#ibcon#end of sib2, iclass 18, count 0 2006.197.07:56:30.82#ibcon#*after write, iclass 18, count 0 2006.197.07:56:30.82#ibcon#*before return 0, iclass 18, count 0 2006.197.07:56:30.82#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.197.07:56:30.82#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.197.07:56:30.82#ibcon#about to clear, iclass 18 cls_cnt 0 2006.197.07:56:30.82#ibcon#cleared, iclass 18 cls_cnt 0 2006.197.07:56:30.82$vc4f8/vblo=3,656.99 2006.197.07:56:30.82#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.197.07:56:30.82#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.197.07:56:30.82#ibcon#ireg 17 cls_cnt 0 2006.197.07:56:30.82#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.197.07:56:30.82#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.197.07:56:30.82#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.197.07:56:30.82#ibcon#enter wrdev, iclass 20, count 0 2006.197.07:56:30.82#ibcon#first serial, iclass 20, count 0 2006.197.07:56:30.82#ibcon#enter sib2, iclass 20, count 0 2006.197.07:56:30.82#ibcon#flushed, iclass 20, count 0 2006.197.07:56:30.82#ibcon#about to write, iclass 20, count 0 2006.197.07:56:30.82#ibcon#wrote, iclass 20, count 0 2006.197.07:56:30.82#ibcon#about to read 3, iclass 20, count 0 2006.197.07:56:30.84#ibcon#read 3, iclass 20, count 0 2006.197.07:56:30.84#ibcon#about to read 4, iclass 20, count 0 2006.197.07:56:30.84#ibcon#read 4, iclass 20, count 0 2006.197.07:56:30.84#ibcon#about to read 5, iclass 20, count 0 2006.197.07:56:30.84#ibcon#read 5, iclass 20, count 0 2006.197.07:56:30.84#ibcon#about to read 6, iclass 20, count 0 2006.197.07:56:30.84#ibcon#read 6, iclass 20, count 0 2006.197.07:56:30.84#ibcon#end of sib2, iclass 20, count 0 2006.197.07:56:30.84#ibcon#*mode == 0, iclass 20, count 0 2006.197.07:56:30.84#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.197.07:56:30.84#ibcon#[28=FRQ=03,656.99\r\n] 2006.197.07:56:30.84#ibcon#*before write, iclass 20, count 0 2006.197.07:56:30.84#ibcon#enter sib2, iclass 20, count 0 2006.197.07:56:30.84#ibcon#flushed, iclass 20, count 0 2006.197.07:56:30.84#ibcon#about to write, iclass 20, count 0 2006.197.07:56:30.84#ibcon#wrote, iclass 20, count 0 2006.197.07:56:30.84#ibcon#about to read 3, iclass 20, count 0 2006.197.07:56:30.88#ibcon#read 3, iclass 20, count 0 2006.197.07:56:30.88#ibcon#about to read 4, iclass 20, count 0 2006.197.07:56:30.88#ibcon#read 4, iclass 20, count 0 2006.197.07:56:30.88#ibcon#about to read 5, iclass 20, count 0 2006.197.07:56:30.88#ibcon#read 5, iclass 20, count 0 2006.197.07:56:30.88#ibcon#about to read 6, iclass 20, count 0 2006.197.07:56:30.88#ibcon#read 6, iclass 20, count 0 2006.197.07:56:30.88#ibcon#end of sib2, iclass 20, count 0 2006.197.07:56:30.88#ibcon#*after write, iclass 20, count 0 2006.197.07:56:30.88#ibcon#*before return 0, iclass 20, count 0 2006.197.07:56:30.88#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.197.07:56:30.88#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.197.07:56:30.88#ibcon#about to clear, iclass 20 cls_cnt 0 2006.197.07:56:30.88#ibcon#cleared, iclass 20 cls_cnt 0 2006.197.07:56:30.88$vc4f8/vb=3,4 2006.197.07:56:30.88#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.197.07:56:30.88#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.197.07:56:30.88#ibcon#ireg 11 cls_cnt 2 2006.197.07:56:30.88#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.197.07:56:30.94#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.197.07:56:30.94#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.197.07:56:30.94#ibcon#enter wrdev, iclass 22, count 2 2006.197.07:56:30.94#ibcon#first serial, iclass 22, count 2 2006.197.07:56:30.94#ibcon#enter sib2, iclass 22, count 2 2006.197.07:56:30.94#ibcon#flushed, iclass 22, count 2 2006.197.07:56:30.94#ibcon#about to write, iclass 22, count 2 2006.197.07:56:30.94#ibcon#wrote, iclass 22, count 2 2006.197.07:56:30.94#ibcon#about to read 3, iclass 22, count 2 2006.197.07:56:30.96#ibcon#read 3, iclass 22, count 2 2006.197.07:56:30.96#ibcon#about to read 4, iclass 22, count 2 2006.197.07:56:30.96#ibcon#read 4, iclass 22, count 2 2006.197.07:56:30.96#ibcon#about to read 5, iclass 22, count 2 2006.197.07:56:30.96#ibcon#read 5, iclass 22, count 2 2006.197.07:56:30.96#ibcon#about to read 6, iclass 22, count 2 2006.197.07:56:30.96#ibcon#read 6, iclass 22, count 2 2006.197.07:56:30.96#ibcon#end of sib2, iclass 22, count 2 2006.197.07:56:30.96#ibcon#*mode == 0, iclass 22, count 2 2006.197.07:56:30.96#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.197.07:56:30.96#ibcon#[27=AT03-04\r\n] 2006.197.07:56:30.96#ibcon#*before write, iclass 22, count 2 2006.197.07:56:30.96#ibcon#enter sib2, iclass 22, count 2 2006.197.07:56:30.96#ibcon#flushed, iclass 22, count 2 2006.197.07:56:30.96#ibcon#about to write, iclass 22, count 2 2006.197.07:56:30.96#ibcon#wrote, iclass 22, count 2 2006.197.07:56:30.96#ibcon#about to read 3, iclass 22, count 2 2006.197.07:56:30.99#ibcon#read 3, iclass 22, count 2 2006.197.07:56:30.99#ibcon#about to read 4, iclass 22, count 2 2006.197.07:56:30.99#ibcon#read 4, iclass 22, count 2 2006.197.07:56:30.99#ibcon#about to read 5, iclass 22, count 2 2006.197.07:56:30.99#ibcon#read 5, iclass 22, count 2 2006.197.07:56:30.99#ibcon#about to read 6, iclass 22, count 2 2006.197.07:56:30.99#ibcon#read 6, iclass 22, count 2 2006.197.07:56:30.99#ibcon#end of sib2, iclass 22, count 2 2006.197.07:56:30.99#ibcon#*after write, iclass 22, count 2 2006.197.07:56:30.99#ibcon#*before return 0, iclass 22, count 2 2006.197.07:56:30.99#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.197.07:56:30.99#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.197.07:56:30.99#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.197.07:56:30.99#ibcon#ireg 7 cls_cnt 0 2006.197.07:56:30.99#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.197.07:56:31.11#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.197.07:56:31.11#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.197.07:56:31.11#ibcon#enter wrdev, iclass 22, count 0 2006.197.07:56:31.11#ibcon#first serial, iclass 22, count 0 2006.197.07:56:31.11#ibcon#enter sib2, iclass 22, count 0 2006.197.07:56:31.11#ibcon#flushed, iclass 22, count 0 2006.197.07:56:31.11#ibcon#about to write, iclass 22, count 0 2006.197.07:56:31.11#ibcon#wrote, iclass 22, count 0 2006.197.07:56:31.11#ibcon#about to read 3, iclass 22, count 0 2006.197.07:56:31.13#ibcon#read 3, iclass 22, count 0 2006.197.07:56:31.13#ibcon#about to read 4, iclass 22, count 0 2006.197.07:56:31.13#ibcon#read 4, iclass 22, count 0 2006.197.07:56:31.13#ibcon#about to read 5, iclass 22, count 0 2006.197.07:56:31.13#ibcon#read 5, iclass 22, count 0 2006.197.07:56:31.13#ibcon#about to read 6, iclass 22, count 0 2006.197.07:56:31.13#ibcon#read 6, iclass 22, count 0 2006.197.07:56:31.13#ibcon#end of sib2, iclass 22, count 0 2006.197.07:56:31.13#ibcon#*mode == 0, iclass 22, count 0 2006.197.07:56:31.13#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.197.07:56:31.13#ibcon#[27=USB\r\n] 2006.197.07:56:31.13#ibcon#*before write, iclass 22, count 0 2006.197.07:56:31.13#ibcon#enter sib2, iclass 22, count 0 2006.197.07:56:31.13#ibcon#flushed, iclass 22, count 0 2006.197.07:56:31.13#ibcon#about to write, iclass 22, count 0 2006.197.07:56:31.13#ibcon#wrote, iclass 22, count 0 2006.197.07:56:31.13#ibcon#about to read 3, iclass 22, count 0 2006.197.07:56:31.16#ibcon#read 3, iclass 22, count 0 2006.197.07:56:31.16#ibcon#about to read 4, iclass 22, count 0 2006.197.07:56:31.16#ibcon#read 4, iclass 22, count 0 2006.197.07:56:31.16#ibcon#about to read 5, iclass 22, count 0 2006.197.07:56:31.16#ibcon#read 5, iclass 22, count 0 2006.197.07:56:31.16#ibcon#about to read 6, iclass 22, count 0 2006.197.07:56:31.16#ibcon#read 6, iclass 22, count 0 2006.197.07:56:31.16#ibcon#end of sib2, iclass 22, count 0 2006.197.07:56:31.16#ibcon#*after write, iclass 22, count 0 2006.197.07:56:31.16#ibcon#*before return 0, iclass 22, count 0 2006.197.07:56:31.16#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.197.07:56:31.16#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.197.07:56:31.16#ibcon#about to clear, iclass 22 cls_cnt 0 2006.197.07:56:31.16#ibcon#cleared, iclass 22 cls_cnt 0 2006.197.07:56:31.16$vc4f8/vblo=4,712.99 2006.197.07:56:31.16#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.197.07:56:31.16#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.197.07:56:31.16#ibcon#ireg 17 cls_cnt 0 2006.197.07:56:31.16#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.197.07:56:31.16#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.197.07:56:31.16#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.197.07:56:31.16#ibcon#enter wrdev, iclass 24, count 0 2006.197.07:56:31.16#ibcon#first serial, iclass 24, count 0 2006.197.07:56:31.16#ibcon#enter sib2, iclass 24, count 0 2006.197.07:56:31.16#ibcon#flushed, iclass 24, count 0 2006.197.07:56:31.16#ibcon#about to write, iclass 24, count 0 2006.197.07:56:31.16#ibcon#wrote, iclass 24, count 0 2006.197.07:56:31.16#ibcon#about to read 3, iclass 24, count 0 2006.197.07:56:31.18#ibcon#read 3, iclass 24, count 0 2006.197.07:56:31.18#ibcon#about to read 4, iclass 24, count 0 2006.197.07:56:31.18#ibcon#read 4, iclass 24, count 0 2006.197.07:56:31.18#ibcon#about to read 5, iclass 24, count 0 2006.197.07:56:31.18#ibcon#read 5, iclass 24, count 0 2006.197.07:56:31.18#ibcon#about to read 6, iclass 24, count 0 2006.197.07:56:31.18#ibcon#read 6, iclass 24, count 0 2006.197.07:56:31.18#ibcon#end of sib2, iclass 24, count 0 2006.197.07:56:31.18#ibcon#*mode == 0, iclass 24, count 0 2006.197.07:56:31.18#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.197.07:56:31.18#ibcon#[28=FRQ=04,712.99\r\n] 2006.197.07:56:31.18#ibcon#*before write, iclass 24, count 0 2006.197.07:56:31.18#ibcon#enter sib2, iclass 24, count 0 2006.197.07:56:31.18#ibcon#flushed, iclass 24, count 0 2006.197.07:56:31.18#ibcon#about to write, iclass 24, count 0 2006.197.07:56:31.18#ibcon#wrote, iclass 24, count 0 2006.197.07:56:31.18#ibcon#about to read 3, iclass 24, count 0 2006.197.07:56:31.22#ibcon#read 3, iclass 24, count 0 2006.197.07:56:31.22#ibcon#about to read 4, iclass 24, count 0 2006.197.07:56:31.22#ibcon#read 4, iclass 24, count 0 2006.197.07:56:31.22#ibcon#about to read 5, iclass 24, count 0 2006.197.07:56:31.22#ibcon#read 5, iclass 24, count 0 2006.197.07:56:31.22#ibcon#about to read 6, iclass 24, count 0 2006.197.07:56:31.22#ibcon#read 6, iclass 24, count 0 2006.197.07:56:31.22#ibcon#end of sib2, iclass 24, count 0 2006.197.07:56:31.22#ibcon#*after write, iclass 24, count 0 2006.197.07:56:31.22#ibcon#*before return 0, iclass 24, count 0 2006.197.07:56:31.22#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.197.07:56:31.22#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.197.07:56:31.22#ibcon#about to clear, iclass 24 cls_cnt 0 2006.197.07:56:31.22#ibcon#cleared, iclass 24 cls_cnt 0 2006.197.07:56:31.22$vc4f8/vb=4,4 2006.197.07:56:31.22#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.197.07:56:31.22#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.197.07:56:31.22#ibcon#ireg 11 cls_cnt 2 2006.197.07:56:31.22#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.197.07:56:31.28#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.197.07:56:31.28#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.197.07:56:31.28#ibcon#enter wrdev, iclass 26, count 2 2006.197.07:56:31.28#ibcon#first serial, iclass 26, count 2 2006.197.07:56:31.28#ibcon#enter sib2, iclass 26, count 2 2006.197.07:56:31.28#ibcon#flushed, iclass 26, count 2 2006.197.07:56:31.28#ibcon#about to write, iclass 26, count 2 2006.197.07:56:31.28#ibcon#wrote, iclass 26, count 2 2006.197.07:56:31.28#ibcon#about to read 3, iclass 26, count 2 2006.197.07:56:31.30#ibcon#read 3, iclass 26, count 2 2006.197.07:56:31.30#ibcon#about to read 4, iclass 26, count 2 2006.197.07:56:31.30#ibcon#read 4, iclass 26, count 2 2006.197.07:56:31.30#ibcon#about to read 5, iclass 26, count 2 2006.197.07:56:31.30#ibcon#read 5, iclass 26, count 2 2006.197.07:56:31.30#ibcon#about to read 6, iclass 26, count 2 2006.197.07:56:31.30#ibcon#read 6, iclass 26, count 2 2006.197.07:56:31.30#ibcon#end of sib2, iclass 26, count 2 2006.197.07:56:31.30#ibcon#*mode == 0, iclass 26, count 2 2006.197.07:56:31.30#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.197.07:56:31.30#ibcon#[27=AT04-04\r\n] 2006.197.07:56:31.30#ibcon#*before write, iclass 26, count 2 2006.197.07:56:31.30#ibcon#enter sib2, iclass 26, count 2 2006.197.07:56:31.30#ibcon#flushed, iclass 26, count 2 2006.197.07:56:31.30#ibcon#about to write, iclass 26, count 2 2006.197.07:56:31.30#ibcon#wrote, iclass 26, count 2 2006.197.07:56:31.30#ibcon#about to read 3, iclass 26, count 2 2006.197.07:56:31.33#ibcon#read 3, iclass 26, count 2 2006.197.07:56:31.33#ibcon#about to read 4, iclass 26, count 2 2006.197.07:56:31.33#ibcon#read 4, iclass 26, count 2 2006.197.07:56:31.33#ibcon#about to read 5, iclass 26, count 2 2006.197.07:56:31.33#ibcon#read 5, iclass 26, count 2 2006.197.07:56:31.33#ibcon#about to read 6, iclass 26, count 2 2006.197.07:56:31.33#ibcon#read 6, iclass 26, count 2 2006.197.07:56:31.33#ibcon#end of sib2, iclass 26, count 2 2006.197.07:56:31.33#ibcon#*after write, iclass 26, count 2 2006.197.07:56:31.33#ibcon#*before return 0, iclass 26, count 2 2006.197.07:56:31.33#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.197.07:56:31.33#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.197.07:56:31.33#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.197.07:56:31.33#ibcon#ireg 7 cls_cnt 0 2006.197.07:56:31.33#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.197.07:56:31.45#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.197.07:56:31.45#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.197.07:56:31.45#ibcon#enter wrdev, iclass 26, count 0 2006.197.07:56:31.45#ibcon#first serial, iclass 26, count 0 2006.197.07:56:31.45#ibcon#enter sib2, iclass 26, count 0 2006.197.07:56:31.45#ibcon#flushed, iclass 26, count 0 2006.197.07:56:31.45#ibcon#about to write, iclass 26, count 0 2006.197.07:56:31.45#ibcon#wrote, iclass 26, count 0 2006.197.07:56:31.45#ibcon#about to read 3, iclass 26, count 0 2006.197.07:56:31.47#ibcon#read 3, iclass 26, count 0 2006.197.07:56:31.47#ibcon#about to read 4, iclass 26, count 0 2006.197.07:56:31.47#ibcon#read 4, iclass 26, count 0 2006.197.07:56:31.47#ibcon#about to read 5, iclass 26, count 0 2006.197.07:56:31.47#ibcon#read 5, iclass 26, count 0 2006.197.07:56:31.47#ibcon#about to read 6, iclass 26, count 0 2006.197.07:56:31.47#ibcon#read 6, iclass 26, count 0 2006.197.07:56:31.47#ibcon#end of sib2, iclass 26, count 0 2006.197.07:56:31.47#ibcon#*mode == 0, iclass 26, count 0 2006.197.07:56:31.47#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.197.07:56:31.47#ibcon#[27=USB\r\n] 2006.197.07:56:31.47#ibcon#*before write, iclass 26, count 0 2006.197.07:56:31.47#ibcon#enter sib2, iclass 26, count 0 2006.197.07:56:31.47#ibcon#flushed, iclass 26, count 0 2006.197.07:56:31.47#ibcon#about to write, iclass 26, count 0 2006.197.07:56:31.47#ibcon#wrote, iclass 26, count 0 2006.197.07:56:31.47#ibcon#about to read 3, iclass 26, count 0 2006.197.07:56:31.50#ibcon#read 3, iclass 26, count 0 2006.197.07:56:31.50#ibcon#about to read 4, iclass 26, count 0 2006.197.07:56:31.50#ibcon#read 4, iclass 26, count 0 2006.197.07:56:31.50#ibcon#about to read 5, iclass 26, count 0 2006.197.07:56:31.50#ibcon#read 5, iclass 26, count 0 2006.197.07:56:31.50#ibcon#about to read 6, iclass 26, count 0 2006.197.07:56:31.50#ibcon#read 6, iclass 26, count 0 2006.197.07:56:31.50#ibcon#end of sib2, iclass 26, count 0 2006.197.07:56:31.50#ibcon#*after write, iclass 26, count 0 2006.197.07:56:31.50#ibcon#*before return 0, iclass 26, count 0 2006.197.07:56:31.50#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.197.07:56:31.50#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.197.07:56:31.50#ibcon#about to clear, iclass 26 cls_cnt 0 2006.197.07:56:31.50#ibcon#cleared, iclass 26 cls_cnt 0 2006.197.07:56:31.50$vc4f8/vblo=5,744.99 2006.197.07:56:31.50#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.197.07:56:31.50#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.197.07:56:31.50#ibcon#ireg 17 cls_cnt 0 2006.197.07:56:31.50#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.197.07:56:31.50#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.197.07:56:31.50#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.197.07:56:31.50#ibcon#enter wrdev, iclass 28, count 0 2006.197.07:56:31.50#ibcon#first serial, iclass 28, count 0 2006.197.07:56:31.50#ibcon#enter sib2, iclass 28, count 0 2006.197.07:56:31.50#ibcon#flushed, iclass 28, count 0 2006.197.07:56:31.50#ibcon#about to write, iclass 28, count 0 2006.197.07:56:31.50#ibcon#wrote, iclass 28, count 0 2006.197.07:56:31.50#ibcon#about to read 3, iclass 28, count 0 2006.197.07:56:31.52#ibcon#read 3, iclass 28, count 0 2006.197.07:56:31.52#ibcon#about to read 4, iclass 28, count 0 2006.197.07:56:31.52#ibcon#read 4, iclass 28, count 0 2006.197.07:56:31.52#ibcon#about to read 5, iclass 28, count 0 2006.197.07:56:31.52#ibcon#read 5, iclass 28, count 0 2006.197.07:56:31.52#ibcon#about to read 6, iclass 28, count 0 2006.197.07:56:31.52#ibcon#read 6, iclass 28, count 0 2006.197.07:56:31.52#ibcon#end of sib2, iclass 28, count 0 2006.197.07:56:31.52#ibcon#*mode == 0, iclass 28, count 0 2006.197.07:56:31.52#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.197.07:56:31.52#ibcon#[28=FRQ=05,744.99\r\n] 2006.197.07:56:31.52#ibcon#*before write, iclass 28, count 0 2006.197.07:56:31.52#ibcon#enter sib2, iclass 28, count 0 2006.197.07:56:31.52#ibcon#flushed, iclass 28, count 0 2006.197.07:56:31.52#ibcon#about to write, iclass 28, count 0 2006.197.07:56:31.52#ibcon#wrote, iclass 28, count 0 2006.197.07:56:31.52#ibcon#about to read 3, iclass 28, count 0 2006.197.07:56:31.56#ibcon#read 3, iclass 28, count 0 2006.197.07:56:31.56#ibcon#about to read 4, iclass 28, count 0 2006.197.07:56:31.56#ibcon#read 4, iclass 28, count 0 2006.197.07:56:31.56#ibcon#about to read 5, iclass 28, count 0 2006.197.07:56:31.56#ibcon#read 5, iclass 28, count 0 2006.197.07:56:31.56#ibcon#about to read 6, iclass 28, count 0 2006.197.07:56:31.56#ibcon#read 6, iclass 28, count 0 2006.197.07:56:31.56#ibcon#end of sib2, iclass 28, count 0 2006.197.07:56:31.56#ibcon#*after write, iclass 28, count 0 2006.197.07:56:31.56#ibcon#*before return 0, iclass 28, count 0 2006.197.07:56:31.56#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.197.07:56:31.56#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.197.07:56:31.56#ibcon#about to clear, iclass 28 cls_cnt 0 2006.197.07:56:31.56#ibcon#cleared, iclass 28 cls_cnt 0 2006.197.07:56:31.56$vc4f8/vb=5,4 2006.197.07:56:31.56#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.197.07:56:31.56#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.197.07:56:31.56#ibcon#ireg 11 cls_cnt 2 2006.197.07:56:31.56#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.197.07:56:31.62#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.197.07:56:31.62#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.197.07:56:31.62#ibcon#enter wrdev, iclass 30, count 2 2006.197.07:56:31.62#ibcon#first serial, iclass 30, count 2 2006.197.07:56:31.62#ibcon#enter sib2, iclass 30, count 2 2006.197.07:56:31.62#ibcon#flushed, iclass 30, count 2 2006.197.07:56:31.62#ibcon#about to write, iclass 30, count 2 2006.197.07:56:31.62#ibcon#wrote, iclass 30, count 2 2006.197.07:56:31.62#ibcon#about to read 3, iclass 30, count 2 2006.197.07:56:31.64#ibcon#read 3, iclass 30, count 2 2006.197.07:56:31.64#ibcon#about to read 4, iclass 30, count 2 2006.197.07:56:31.64#ibcon#read 4, iclass 30, count 2 2006.197.07:56:31.64#ibcon#about to read 5, iclass 30, count 2 2006.197.07:56:31.64#ibcon#read 5, iclass 30, count 2 2006.197.07:56:31.64#ibcon#about to read 6, iclass 30, count 2 2006.197.07:56:31.64#ibcon#read 6, iclass 30, count 2 2006.197.07:56:31.64#ibcon#end of sib2, iclass 30, count 2 2006.197.07:56:31.64#ibcon#*mode == 0, iclass 30, count 2 2006.197.07:56:31.64#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.197.07:56:31.64#ibcon#[27=AT05-04\r\n] 2006.197.07:56:31.64#ibcon#*before write, iclass 30, count 2 2006.197.07:56:31.64#ibcon#enter sib2, iclass 30, count 2 2006.197.07:56:31.64#ibcon#flushed, iclass 30, count 2 2006.197.07:56:31.64#ibcon#about to write, iclass 30, count 2 2006.197.07:56:31.64#ibcon#wrote, iclass 30, count 2 2006.197.07:56:31.64#ibcon#about to read 3, iclass 30, count 2 2006.197.07:56:31.67#ibcon#read 3, iclass 30, count 2 2006.197.07:56:31.67#ibcon#about to read 4, iclass 30, count 2 2006.197.07:56:31.67#ibcon#read 4, iclass 30, count 2 2006.197.07:56:31.67#ibcon#about to read 5, iclass 30, count 2 2006.197.07:56:31.67#ibcon#read 5, iclass 30, count 2 2006.197.07:56:31.67#ibcon#about to read 6, iclass 30, count 2 2006.197.07:56:31.67#ibcon#read 6, iclass 30, count 2 2006.197.07:56:31.67#ibcon#end of sib2, iclass 30, count 2 2006.197.07:56:31.67#ibcon#*after write, iclass 30, count 2 2006.197.07:56:31.67#ibcon#*before return 0, iclass 30, count 2 2006.197.07:56:31.67#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.197.07:56:31.67#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.197.07:56:31.67#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.197.07:56:31.67#ibcon#ireg 7 cls_cnt 0 2006.197.07:56:31.67#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.197.07:56:31.79#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.197.07:56:31.79#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.197.07:56:31.79#ibcon#enter wrdev, iclass 30, count 0 2006.197.07:56:31.79#ibcon#first serial, iclass 30, count 0 2006.197.07:56:31.79#ibcon#enter sib2, iclass 30, count 0 2006.197.07:56:31.79#ibcon#flushed, iclass 30, count 0 2006.197.07:56:31.79#ibcon#about to write, iclass 30, count 0 2006.197.07:56:31.79#ibcon#wrote, iclass 30, count 0 2006.197.07:56:31.79#ibcon#about to read 3, iclass 30, count 0 2006.197.07:56:31.81#ibcon#read 3, iclass 30, count 0 2006.197.07:56:31.81#ibcon#about to read 4, iclass 30, count 0 2006.197.07:56:31.81#ibcon#read 4, iclass 30, count 0 2006.197.07:56:31.81#ibcon#about to read 5, iclass 30, count 0 2006.197.07:56:31.81#ibcon#read 5, iclass 30, count 0 2006.197.07:56:31.81#ibcon#about to read 6, iclass 30, count 0 2006.197.07:56:31.81#ibcon#read 6, iclass 30, count 0 2006.197.07:56:31.81#ibcon#end of sib2, iclass 30, count 0 2006.197.07:56:31.81#ibcon#*mode == 0, iclass 30, count 0 2006.197.07:56:31.81#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.197.07:56:31.81#ibcon#[27=USB\r\n] 2006.197.07:56:31.81#ibcon#*before write, iclass 30, count 0 2006.197.07:56:31.81#ibcon#enter sib2, iclass 30, count 0 2006.197.07:56:31.81#ibcon#flushed, iclass 30, count 0 2006.197.07:56:31.81#ibcon#about to write, iclass 30, count 0 2006.197.07:56:31.81#ibcon#wrote, iclass 30, count 0 2006.197.07:56:31.81#ibcon#about to read 3, iclass 30, count 0 2006.197.07:56:31.84#ibcon#read 3, iclass 30, count 0 2006.197.07:56:31.84#ibcon#about to read 4, iclass 30, count 0 2006.197.07:56:31.84#ibcon#read 4, iclass 30, count 0 2006.197.07:56:31.84#ibcon#about to read 5, iclass 30, count 0 2006.197.07:56:31.84#ibcon#read 5, iclass 30, count 0 2006.197.07:56:31.84#ibcon#about to read 6, iclass 30, count 0 2006.197.07:56:31.84#ibcon#read 6, iclass 30, count 0 2006.197.07:56:31.84#ibcon#end of sib2, iclass 30, count 0 2006.197.07:56:31.84#ibcon#*after write, iclass 30, count 0 2006.197.07:56:31.84#ibcon#*before return 0, iclass 30, count 0 2006.197.07:56:31.84#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.197.07:56:31.84#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.197.07:56:31.84#ibcon#about to clear, iclass 30 cls_cnt 0 2006.197.07:56:31.84#ibcon#cleared, iclass 30 cls_cnt 0 2006.197.07:56:31.84$vc4f8/vblo=6,752.99 2006.197.07:56:31.84#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.197.07:56:31.84#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.197.07:56:31.84#ibcon#ireg 17 cls_cnt 0 2006.197.07:56:31.84#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.197.07:56:31.84#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.197.07:56:31.84#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.197.07:56:31.84#ibcon#enter wrdev, iclass 32, count 0 2006.197.07:56:31.84#ibcon#first serial, iclass 32, count 0 2006.197.07:56:31.84#ibcon#enter sib2, iclass 32, count 0 2006.197.07:56:31.84#ibcon#flushed, iclass 32, count 0 2006.197.07:56:31.84#ibcon#about to write, iclass 32, count 0 2006.197.07:56:31.84#ibcon#wrote, iclass 32, count 0 2006.197.07:56:31.84#ibcon#about to read 3, iclass 32, count 0 2006.197.07:56:31.86#ibcon#read 3, iclass 32, count 0 2006.197.07:56:31.86#ibcon#about to read 4, iclass 32, count 0 2006.197.07:56:31.86#ibcon#read 4, iclass 32, count 0 2006.197.07:56:31.86#ibcon#about to read 5, iclass 32, count 0 2006.197.07:56:31.86#ibcon#read 5, iclass 32, count 0 2006.197.07:56:31.86#ibcon#about to read 6, iclass 32, count 0 2006.197.07:56:31.86#ibcon#read 6, iclass 32, count 0 2006.197.07:56:31.86#ibcon#end of sib2, iclass 32, count 0 2006.197.07:56:31.86#ibcon#*mode == 0, iclass 32, count 0 2006.197.07:56:31.86#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.197.07:56:31.86#ibcon#[28=FRQ=06,752.99\r\n] 2006.197.07:56:31.86#ibcon#*before write, iclass 32, count 0 2006.197.07:56:31.86#ibcon#enter sib2, iclass 32, count 0 2006.197.07:56:31.86#ibcon#flushed, iclass 32, count 0 2006.197.07:56:31.86#ibcon#about to write, iclass 32, count 0 2006.197.07:56:31.86#ibcon#wrote, iclass 32, count 0 2006.197.07:56:31.86#ibcon#about to read 3, iclass 32, count 0 2006.197.07:56:31.90#ibcon#read 3, iclass 32, count 0 2006.197.07:56:31.90#ibcon#about to read 4, iclass 32, count 0 2006.197.07:56:31.90#ibcon#read 4, iclass 32, count 0 2006.197.07:56:31.90#ibcon#about to read 5, iclass 32, count 0 2006.197.07:56:31.90#ibcon#read 5, iclass 32, count 0 2006.197.07:56:31.90#ibcon#about to read 6, iclass 32, count 0 2006.197.07:56:31.90#ibcon#read 6, iclass 32, count 0 2006.197.07:56:31.90#ibcon#end of sib2, iclass 32, count 0 2006.197.07:56:31.90#ibcon#*after write, iclass 32, count 0 2006.197.07:56:31.90#ibcon#*before return 0, iclass 32, count 0 2006.197.07:56:31.90#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.197.07:56:31.90#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.197.07:56:31.90#ibcon#about to clear, iclass 32 cls_cnt 0 2006.197.07:56:31.90#ibcon#cleared, iclass 32 cls_cnt 0 2006.197.07:56:31.90$vc4f8/vb=6,4 2006.197.07:56:31.90#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.197.07:56:31.90#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.197.07:56:31.90#ibcon#ireg 11 cls_cnt 2 2006.197.07:56:31.90#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.197.07:56:31.96#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.197.07:56:31.96#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.197.07:56:31.96#ibcon#enter wrdev, iclass 34, count 2 2006.197.07:56:31.96#ibcon#first serial, iclass 34, count 2 2006.197.07:56:31.96#ibcon#enter sib2, iclass 34, count 2 2006.197.07:56:31.96#ibcon#flushed, iclass 34, count 2 2006.197.07:56:31.96#ibcon#about to write, iclass 34, count 2 2006.197.07:56:31.96#ibcon#wrote, iclass 34, count 2 2006.197.07:56:31.96#ibcon#about to read 3, iclass 34, count 2 2006.197.07:56:31.98#ibcon#read 3, iclass 34, count 2 2006.197.07:56:31.98#ibcon#about to read 4, iclass 34, count 2 2006.197.07:56:31.98#ibcon#read 4, iclass 34, count 2 2006.197.07:56:31.98#ibcon#about to read 5, iclass 34, count 2 2006.197.07:56:31.98#ibcon#read 5, iclass 34, count 2 2006.197.07:56:31.98#ibcon#about to read 6, iclass 34, count 2 2006.197.07:56:31.98#ibcon#read 6, iclass 34, count 2 2006.197.07:56:31.98#ibcon#end of sib2, iclass 34, count 2 2006.197.07:56:31.98#ibcon#*mode == 0, iclass 34, count 2 2006.197.07:56:31.98#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.197.07:56:31.98#ibcon#[27=AT06-04\r\n] 2006.197.07:56:31.98#ibcon#*before write, iclass 34, count 2 2006.197.07:56:31.98#ibcon#enter sib2, iclass 34, count 2 2006.197.07:56:31.98#ibcon#flushed, iclass 34, count 2 2006.197.07:56:31.98#ibcon#about to write, iclass 34, count 2 2006.197.07:56:31.98#ibcon#wrote, iclass 34, count 2 2006.197.07:56:31.98#ibcon#about to read 3, iclass 34, count 2 2006.197.07:56:32.01#ibcon#read 3, iclass 34, count 2 2006.197.07:56:32.01#ibcon#about to read 4, iclass 34, count 2 2006.197.07:56:32.01#ibcon#read 4, iclass 34, count 2 2006.197.07:56:32.01#ibcon#about to read 5, iclass 34, count 2 2006.197.07:56:32.01#ibcon#read 5, iclass 34, count 2 2006.197.07:56:32.01#ibcon#about to read 6, iclass 34, count 2 2006.197.07:56:32.01#ibcon#read 6, iclass 34, count 2 2006.197.07:56:32.01#ibcon#end of sib2, iclass 34, count 2 2006.197.07:56:32.01#ibcon#*after write, iclass 34, count 2 2006.197.07:56:32.01#ibcon#*before return 0, iclass 34, count 2 2006.197.07:56:32.01#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.197.07:56:32.01#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.197.07:56:32.01#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.197.07:56:32.01#ibcon#ireg 7 cls_cnt 0 2006.197.07:56:32.01#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.197.07:56:32.13#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.197.07:56:32.13#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.197.07:56:32.13#ibcon#enter wrdev, iclass 34, count 0 2006.197.07:56:32.13#ibcon#first serial, iclass 34, count 0 2006.197.07:56:32.13#ibcon#enter sib2, iclass 34, count 0 2006.197.07:56:32.13#ibcon#flushed, iclass 34, count 0 2006.197.07:56:32.13#ibcon#about to write, iclass 34, count 0 2006.197.07:56:32.13#ibcon#wrote, iclass 34, count 0 2006.197.07:56:32.13#ibcon#about to read 3, iclass 34, count 0 2006.197.07:56:32.15#ibcon#read 3, iclass 34, count 0 2006.197.07:56:32.15#ibcon#about to read 4, iclass 34, count 0 2006.197.07:56:32.15#ibcon#read 4, iclass 34, count 0 2006.197.07:56:32.15#ibcon#about to read 5, iclass 34, count 0 2006.197.07:56:32.15#ibcon#read 5, iclass 34, count 0 2006.197.07:56:32.15#ibcon#about to read 6, iclass 34, count 0 2006.197.07:56:32.15#ibcon#read 6, iclass 34, count 0 2006.197.07:56:32.15#ibcon#end of sib2, iclass 34, count 0 2006.197.07:56:32.15#ibcon#*mode == 0, iclass 34, count 0 2006.197.07:56:32.15#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.197.07:56:32.15#ibcon#[27=USB\r\n] 2006.197.07:56:32.15#ibcon#*before write, iclass 34, count 0 2006.197.07:56:32.15#ibcon#enter sib2, iclass 34, count 0 2006.197.07:56:32.15#ibcon#flushed, iclass 34, count 0 2006.197.07:56:32.15#ibcon#about to write, iclass 34, count 0 2006.197.07:56:32.15#ibcon#wrote, iclass 34, count 0 2006.197.07:56:32.15#ibcon#about to read 3, iclass 34, count 0 2006.197.07:56:32.18#ibcon#read 3, iclass 34, count 0 2006.197.07:56:32.18#ibcon#about to read 4, iclass 34, count 0 2006.197.07:56:32.18#ibcon#read 4, iclass 34, count 0 2006.197.07:56:32.18#ibcon#about to read 5, iclass 34, count 0 2006.197.07:56:32.18#ibcon#read 5, iclass 34, count 0 2006.197.07:56:32.18#ibcon#about to read 6, iclass 34, count 0 2006.197.07:56:32.18#ibcon#read 6, iclass 34, count 0 2006.197.07:56:32.18#ibcon#end of sib2, iclass 34, count 0 2006.197.07:56:32.18#ibcon#*after write, iclass 34, count 0 2006.197.07:56:32.18#ibcon#*before return 0, iclass 34, count 0 2006.197.07:56:32.18#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.197.07:56:32.18#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.197.07:56:32.18#ibcon#about to clear, iclass 34 cls_cnt 0 2006.197.07:56:32.18#ibcon#cleared, iclass 34 cls_cnt 0 2006.197.07:56:32.18$vc4f8/vabw=wide 2006.197.07:56:32.18#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.197.07:56:32.18#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.197.07:56:32.18#ibcon#ireg 8 cls_cnt 0 2006.197.07:56:32.18#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.197.07:56:32.18#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.197.07:56:32.18#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.197.07:56:32.18#ibcon#enter wrdev, iclass 36, count 0 2006.197.07:56:32.18#ibcon#first serial, iclass 36, count 0 2006.197.07:56:32.18#ibcon#enter sib2, iclass 36, count 0 2006.197.07:56:32.18#ibcon#flushed, iclass 36, count 0 2006.197.07:56:32.18#ibcon#about to write, iclass 36, count 0 2006.197.07:56:32.18#ibcon#wrote, iclass 36, count 0 2006.197.07:56:32.18#ibcon#about to read 3, iclass 36, count 0 2006.197.07:56:32.20#ibcon#read 3, iclass 36, count 0 2006.197.07:56:32.20#ibcon#about to read 4, iclass 36, count 0 2006.197.07:56:32.20#ibcon#read 4, iclass 36, count 0 2006.197.07:56:32.20#ibcon#about to read 5, iclass 36, count 0 2006.197.07:56:32.20#ibcon#read 5, iclass 36, count 0 2006.197.07:56:32.20#ibcon#about to read 6, iclass 36, count 0 2006.197.07:56:32.20#ibcon#read 6, iclass 36, count 0 2006.197.07:56:32.20#ibcon#end of sib2, iclass 36, count 0 2006.197.07:56:32.20#ibcon#*mode == 0, iclass 36, count 0 2006.197.07:56:32.20#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.197.07:56:32.20#ibcon#[25=BW32\r\n] 2006.197.07:56:32.20#ibcon#*before write, iclass 36, count 0 2006.197.07:56:32.20#ibcon#enter sib2, iclass 36, count 0 2006.197.07:56:32.20#ibcon#flushed, iclass 36, count 0 2006.197.07:56:32.20#ibcon#about to write, iclass 36, count 0 2006.197.07:56:32.20#ibcon#wrote, iclass 36, count 0 2006.197.07:56:32.20#ibcon#about to read 3, iclass 36, count 0 2006.197.07:56:32.23#ibcon#read 3, iclass 36, count 0 2006.197.07:56:32.23#ibcon#about to read 4, iclass 36, count 0 2006.197.07:56:32.23#ibcon#read 4, iclass 36, count 0 2006.197.07:56:32.23#ibcon#about to read 5, iclass 36, count 0 2006.197.07:56:32.23#ibcon#read 5, iclass 36, count 0 2006.197.07:56:32.23#ibcon#about to read 6, iclass 36, count 0 2006.197.07:56:32.23#ibcon#read 6, iclass 36, count 0 2006.197.07:56:32.23#ibcon#end of sib2, iclass 36, count 0 2006.197.07:56:32.23#ibcon#*after write, iclass 36, count 0 2006.197.07:56:32.23#ibcon#*before return 0, iclass 36, count 0 2006.197.07:56:32.23#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.197.07:56:32.23#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.197.07:56:32.23#ibcon#about to clear, iclass 36 cls_cnt 0 2006.197.07:56:32.23#ibcon#cleared, iclass 36 cls_cnt 0 2006.197.07:56:32.23$vc4f8/vbbw=wide 2006.197.07:56:32.23#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.197.07:56:32.23#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.197.07:56:32.23#ibcon#ireg 8 cls_cnt 0 2006.197.07:56:32.23#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.197.07:56:32.30#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.197.07:56:32.30#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.197.07:56:32.30#ibcon#enter wrdev, iclass 38, count 0 2006.197.07:56:32.30#ibcon#first serial, iclass 38, count 0 2006.197.07:56:32.30#ibcon#enter sib2, iclass 38, count 0 2006.197.07:56:32.30#ibcon#flushed, iclass 38, count 0 2006.197.07:56:32.30#ibcon#about to write, iclass 38, count 0 2006.197.07:56:32.30#ibcon#wrote, iclass 38, count 0 2006.197.07:56:32.30#ibcon#about to read 3, iclass 38, count 0 2006.197.07:56:32.32#ibcon#read 3, iclass 38, count 0 2006.197.07:56:32.32#ibcon#about to read 4, iclass 38, count 0 2006.197.07:56:32.32#ibcon#read 4, iclass 38, count 0 2006.197.07:56:32.32#ibcon#about to read 5, iclass 38, count 0 2006.197.07:56:32.32#ibcon#read 5, iclass 38, count 0 2006.197.07:56:32.32#ibcon#about to read 6, iclass 38, count 0 2006.197.07:56:32.32#ibcon#read 6, iclass 38, count 0 2006.197.07:56:32.32#ibcon#end of sib2, iclass 38, count 0 2006.197.07:56:32.32#ibcon#*mode == 0, iclass 38, count 0 2006.197.07:56:32.32#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.197.07:56:32.32#ibcon#[27=BW32\r\n] 2006.197.07:56:32.32#ibcon#*before write, iclass 38, count 0 2006.197.07:56:32.32#ibcon#enter sib2, iclass 38, count 0 2006.197.07:56:32.32#ibcon#flushed, iclass 38, count 0 2006.197.07:56:32.32#ibcon#about to write, iclass 38, count 0 2006.197.07:56:32.32#ibcon#wrote, iclass 38, count 0 2006.197.07:56:32.32#ibcon#about to read 3, iclass 38, count 0 2006.197.07:56:32.35#ibcon#read 3, iclass 38, count 0 2006.197.07:56:32.35#ibcon#about to read 4, iclass 38, count 0 2006.197.07:56:32.35#ibcon#read 4, iclass 38, count 0 2006.197.07:56:32.35#ibcon#about to read 5, iclass 38, count 0 2006.197.07:56:32.35#ibcon#read 5, iclass 38, count 0 2006.197.07:56:32.35#ibcon#about to read 6, iclass 38, count 0 2006.197.07:56:32.35#ibcon#read 6, iclass 38, count 0 2006.197.07:56:32.35#ibcon#end of sib2, iclass 38, count 0 2006.197.07:56:32.35#ibcon#*after write, iclass 38, count 0 2006.197.07:56:32.35#ibcon#*before return 0, iclass 38, count 0 2006.197.07:56:32.35#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.197.07:56:32.35#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.197.07:56:32.35#ibcon#about to clear, iclass 38 cls_cnt 0 2006.197.07:56:32.35#ibcon#cleared, iclass 38 cls_cnt 0 2006.197.07:56:32.35$4f8m12a/ifd4f 2006.197.07:56:32.35$ifd4f/lo= 2006.197.07:56:32.35$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.197.07:56:32.35$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.197.07:56:32.35$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.197.07:56:32.35$ifd4f/patch= 2006.197.07:56:32.35$ifd4f/patch=lo1,a1,a2,a3,a4 2006.197.07:56:32.35$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.197.07:56:32.35$ifd4f/patch=lo3,a5,a6,a7,a8 2006.197.07:56:32.35$4f8m12a/"form=m,16.000,1:2 2006.197.07:56:32.35$4f8m12a/"tpicd 2006.197.07:56:32.35$4f8m12a/echo=off 2006.197.07:56:32.35$4f8m12a/xlog=off 2006.197.07:56:32.35:!2006.197.07:58:40 2006.197.07:56:56.14#trakl#Source acquired 2006.197.07:56:57.14#flagr#flagr/antenna,acquired 2006.197.07:58:40.00:preob 2006.197.07:58:40.14/onsource/TRACKING 2006.197.07:58:40.14:!2006.197.07:58:50 2006.197.07:58:50.00:data_valid=on 2006.197.07:58:50.00:midob 2006.197.07:58:51.14/onsource/TRACKING 2006.197.07:58:51.14/wx/25.73,1002.9,96 2006.197.07:58:51.27/cable/+6.3713E-03 2006.197.07:58:52.36/va/01,08,usb,yes,30,32 2006.197.07:58:52.36/va/02,07,usb,yes,31,32 2006.197.07:58:52.36/va/03,06,usb,yes,33,33 2006.197.07:58:52.36/va/04,07,usb,yes,32,34 2006.197.07:58:52.36/va/05,07,usb,yes,36,38 2006.197.07:58:52.36/va/06,06,usb,yes,35,35 2006.197.07:58:52.36/va/07,06,usb,yes,35,35 2006.197.07:58:52.36/va/08,07,usb,yes,33,33 2006.197.07:58:52.59/valo/01,532.99,yes,locked 2006.197.07:58:52.59/valo/02,572.99,yes,locked 2006.197.07:58:52.59/valo/03,672.99,yes,locked 2006.197.07:58:52.59/valo/04,832.99,yes,locked 2006.197.07:58:52.59/valo/05,652.99,yes,locked 2006.197.07:58:52.59/valo/06,772.99,yes,locked 2006.197.07:58:52.59/valo/07,832.99,yes,locked 2006.197.07:58:52.59/valo/08,852.99,yes,locked 2006.197.07:58:53.68/vb/01,04,usb,yes,29,28 2006.197.07:58:53.68/vb/02,04,usb,yes,31,32 2006.197.07:58:53.68/vb/03,04,usb,yes,27,31 2006.197.07:58:53.68/vb/04,04,usb,yes,28,28 2006.197.07:58:53.68/vb/05,04,usb,yes,27,31 2006.197.07:58:53.68/vb/06,04,usb,yes,28,30 2006.197.07:58:53.68/vb/07,04,usb,yes,30,30 2006.197.07:58:53.68/vb/08,04,usb,yes,27,31 2006.197.07:58:53.91/vblo/01,632.99,yes,locked 2006.197.07:58:53.91/vblo/02,640.99,yes,locked 2006.197.07:58:53.91/vblo/03,656.99,yes,locked 2006.197.07:58:53.91/vblo/04,712.99,yes,locked 2006.197.07:58:53.91/vblo/05,744.99,yes,locked 2006.197.07:58:53.91/vblo/06,752.99,yes,locked 2006.197.07:58:53.91/vblo/07,734.99,yes,locked 2006.197.07:58:53.91/vblo/08,744.99,yes,locked 2006.197.07:58:54.06/vabw/8 2006.197.07:58:54.21/vbbw/8 2006.197.07:58:54.34/xfe/off,on,15.5 2006.197.07:58:54.72/ifatt/23,28,28,28 2006.197.07:58:55.11/fmout-gps/S +3.02E-07 2006.197.07:58:55.15:!2006.197.07:59:50 2006.197.07:59:50.00:data_valid=off 2006.197.07:59:50.00:postob 2006.197.07:59:50.09/cable/+6.3725E-03 2006.197.07:59:50.09/wx/25.72,1002.9,96 2006.197.07:59:51.09/fmout-gps/S +3.01E-07 2006.197.07:59:51.09:scan_name=197-0801,k06197,60 2006.197.07:59:51.09:source=3c371,180650.68,694928.1,2000.0,cw 2006.197.07:59:51.14#flagr#flagr/antenna,new-source 2006.197.07:59:52.14:checkk5 2006.197.07:59:52.48/chk_autoobs//k5ts1/ autoobs is running! 2006.197.07:59:52.83/chk_autoobs//k5ts2/ autoobs is running! 2006.197.07:59:53.18/chk_autoobs//k5ts3/ autoobs is running! 2006.197.07:59:53.53/chk_autoobs//k5ts4/ autoobs is running! 2006.197.07:59:53.86/chk_obsdata//k5ts1/T1970758??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.07:59:54.20/chk_obsdata//k5ts2/T1970758??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.07:59:54.53/chk_obsdata//k5ts3/T1970758??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.07:59:54.87/chk_obsdata//k5ts4/T1970758??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.07:59:55.53/k5log//k5ts1_log_newline 2006.197.07:59:56.18/k5log//k5ts2_log_newline 2006.197.07:59:56.84/k5log//k5ts3_log_newline 2006.197.07:59:57.50/k5log//k5ts4_log_newline 2006.197.07:59:57.52/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.197.07:59:57.52:4f8m12a=2 2006.197.07:59:57.52$4f8m12a/echo=on 2006.197.07:59:57.52$4f8m12a/pcalon 2006.197.07:59:57.52$pcalon/"no phase cal control is implemented here 2006.197.07:59:57.52$4f8m12a/"tpicd=stop 2006.197.07:59:57.52$4f8m12a/vc4f8 2006.197.07:59:57.52$vc4f8/valo=1,532.99 2006.197.07:59:57.53#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.197.07:59:57.53#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.197.07:59:57.53#ibcon#ireg 17 cls_cnt 0 2006.197.07:59:57.53#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.197.07:59:57.53#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.197.07:59:57.53#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.197.07:59:57.53#ibcon#enter wrdev, iclass 13, count 0 2006.197.07:59:57.53#ibcon#first serial, iclass 13, count 0 2006.197.07:59:57.53#ibcon#enter sib2, iclass 13, count 0 2006.197.07:59:57.53#ibcon#flushed, iclass 13, count 0 2006.197.07:59:57.53#ibcon#about to write, iclass 13, count 0 2006.197.07:59:57.53#ibcon#wrote, iclass 13, count 0 2006.197.07:59:57.53#ibcon#about to read 3, iclass 13, count 0 2006.197.07:59:57.55#ibcon#read 3, iclass 13, count 0 2006.197.07:59:57.55#ibcon#about to read 4, iclass 13, count 0 2006.197.07:59:57.55#ibcon#read 4, iclass 13, count 0 2006.197.07:59:57.55#ibcon#about to read 5, iclass 13, count 0 2006.197.07:59:57.55#ibcon#read 5, iclass 13, count 0 2006.197.07:59:57.55#ibcon#about to read 6, iclass 13, count 0 2006.197.07:59:57.55#ibcon#read 6, iclass 13, count 0 2006.197.07:59:57.55#ibcon#end of sib2, iclass 13, count 0 2006.197.07:59:57.55#ibcon#*mode == 0, iclass 13, count 0 2006.197.07:59:57.55#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.197.07:59:57.55#ibcon#[26=FRQ=01,532.99\r\n] 2006.197.07:59:57.55#ibcon#*before write, iclass 13, count 0 2006.197.07:59:57.55#ibcon#enter sib2, iclass 13, count 0 2006.197.07:59:57.55#ibcon#flushed, iclass 13, count 0 2006.197.07:59:57.55#ibcon#about to write, iclass 13, count 0 2006.197.07:59:57.55#ibcon#wrote, iclass 13, count 0 2006.197.07:59:57.55#ibcon#about to read 3, iclass 13, count 0 2006.197.07:59:57.60#ibcon#read 3, iclass 13, count 0 2006.197.07:59:57.60#ibcon#about to read 4, iclass 13, count 0 2006.197.07:59:57.60#ibcon#read 4, iclass 13, count 0 2006.197.07:59:57.60#ibcon#about to read 5, iclass 13, count 0 2006.197.07:59:57.60#ibcon#read 5, iclass 13, count 0 2006.197.07:59:57.60#ibcon#about to read 6, iclass 13, count 0 2006.197.07:59:57.60#ibcon#read 6, iclass 13, count 0 2006.197.07:59:57.60#ibcon#end of sib2, iclass 13, count 0 2006.197.07:59:57.60#ibcon#*after write, iclass 13, count 0 2006.197.07:59:57.60#ibcon#*before return 0, iclass 13, count 0 2006.197.07:59:57.60#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.197.07:59:57.60#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.197.07:59:57.60#ibcon#about to clear, iclass 13 cls_cnt 0 2006.197.07:59:57.60#ibcon#cleared, iclass 13 cls_cnt 0 2006.197.07:59:57.60$vc4f8/va=1,8 2006.197.07:59:57.60#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.197.07:59:57.60#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.197.07:59:57.60#ibcon#ireg 11 cls_cnt 2 2006.197.07:59:57.60#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.197.07:59:57.60#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.197.07:59:57.60#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.197.07:59:57.60#ibcon#enter wrdev, iclass 15, count 2 2006.197.07:59:57.60#ibcon#first serial, iclass 15, count 2 2006.197.07:59:57.60#ibcon#enter sib2, iclass 15, count 2 2006.197.07:59:57.60#ibcon#flushed, iclass 15, count 2 2006.197.07:59:57.60#ibcon#about to write, iclass 15, count 2 2006.197.07:59:57.60#ibcon#wrote, iclass 15, count 2 2006.197.07:59:57.60#ibcon#about to read 3, iclass 15, count 2 2006.197.07:59:57.62#ibcon#read 3, iclass 15, count 2 2006.197.07:59:57.62#ibcon#about to read 4, iclass 15, count 2 2006.197.07:59:57.62#ibcon#read 4, iclass 15, count 2 2006.197.07:59:57.62#ibcon#about to read 5, iclass 15, count 2 2006.197.07:59:57.62#ibcon#read 5, iclass 15, count 2 2006.197.07:59:57.62#ibcon#about to read 6, iclass 15, count 2 2006.197.07:59:57.62#ibcon#read 6, iclass 15, count 2 2006.197.07:59:57.62#ibcon#end of sib2, iclass 15, count 2 2006.197.07:59:57.62#ibcon#*mode == 0, iclass 15, count 2 2006.197.07:59:57.62#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.197.07:59:57.62#ibcon#[25=AT01-08\r\n] 2006.197.07:59:57.62#ibcon#*before write, iclass 15, count 2 2006.197.07:59:57.62#ibcon#enter sib2, iclass 15, count 2 2006.197.07:59:57.62#ibcon#flushed, iclass 15, count 2 2006.197.07:59:57.62#ibcon#about to write, iclass 15, count 2 2006.197.07:59:57.62#ibcon#wrote, iclass 15, count 2 2006.197.07:59:57.62#ibcon#about to read 3, iclass 15, count 2 2006.197.07:59:57.65#abcon#<5=/04 3.3 6.6 25.72 961002.9\r\n> 2006.197.07:59:57.65#ibcon#read 3, iclass 15, count 2 2006.197.07:59:57.65#ibcon#about to read 4, iclass 15, count 2 2006.197.07:59:57.65#ibcon#read 4, iclass 15, count 2 2006.197.07:59:57.65#ibcon#about to read 5, iclass 15, count 2 2006.197.07:59:57.65#ibcon#read 5, iclass 15, count 2 2006.197.07:59:57.65#ibcon#about to read 6, iclass 15, count 2 2006.197.07:59:57.65#ibcon#read 6, iclass 15, count 2 2006.197.07:59:57.65#ibcon#end of sib2, iclass 15, count 2 2006.197.07:59:57.65#ibcon#*after write, iclass 15, count 2 2006.197.07:59:57.65#ibcon#*before return 0, iclass 15, count 2 2006.197.07:59:57.65#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.197.07:59:57.65#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.197.07:59:57.65#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.197.07:59:57.65#ibcon#ireg 7 cls_cnt 0 2006.197.07:59:57.65#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.197.07:59:57.67#abcon#{5=INTERFACE CLEAR} 2006.197.07:59:57.73#abcon#[5=S1D000X0/0*\r\n] 2006.197.07:59:57.77#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.197.07:59:57.77#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.197.07:59:57.77#ibcon#enter wrdev, iclass 15, count 0 2006.197.07:59:57.77#ibcon#first serial, iclass 15, count 0 2006.197.07:59:57.77#ibcon#enter sib2, iclass 15, count 0 2006.197.07:59:57.77#ibcon#flushed, iclass 15, count 0 2006.197.07:59:57.77#ibcon#about to write, iclass 15, count 0 2006.197.07:59:57.77#ibcon#wrote, iclass 15, count 0 2006.197.07:59:57.77#ibcon#about to read 3, iclass 15, count 0 2006.197.07:59:57.79#ibcon#read 3, iclass 15, count 0 2006.197.07:59:57.79#ibcon#about to read 4, iclass 15, count 0 2006.197.07:59:57.79#ibcon#read 4, iclass 15, count 0 2006.197.07:59:57.79#ibcon#about to read 5, iclass 15, count 0 2006.197.07:59:57.79#ibcon#read 5, iclass 15, count 0 2006.197.07:59:57.79#ibcon#about to read 6, iclass 15, count 0 2006.197.07:59:57.79#ibcon#read 6, iclass 15, count 0 2006.197.07:59:57.79#ibcon#end of sib2, iclass 15, count 0 2006.197.07:59:57.79#ibcon#*mode == 0, iclass 15, count 0 2006.197.07:59:57.79#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.197.07:59:57.79#ibcon#[25=USB\r\n] 2006.197.07:59:57.79#ibcon#*before write, iclass 15, count 0 2006.197.07:59:57.79#ibcon#enter sib2, iclass 15, count 0 2006.197.07:59:57.79#ibcon#flushed, iclass 15, count 0 2006.197.07:59:57.79#ibcon#about to write, iclass 15, count 0 2006.197.07:59:57.79#ibcon#wrote, iclass 15, count 0 2006.197.07:59:57.79#ibcon#about to read 3, iclass 15, count 0 2006.197.07:59:57.82#ibcon#read 3, iclass 15, count 0 2006.197.07:59:57.82#ibcon#about to read 4, iclass 15, count 0 2006.197.07:59:57.82#ibcon#read 4, iclass 15, count 0 2006.197.07:59:57.82#ibcon#about to read 5, iclass 15, count 0 2006.197.07:59:57.82#ibcon#read 5, iclass 15, count 0 2006.197.07:59:57.82#ibcon#about to read 6, iclass 15, count 0 2006.197.07:59:57.82#ibcon#read 6, iclass 15, count 0 2006.197.07:59:57.82#ibcon#end of sib2, iclass 15, count 0 2006.197.07:59:57.82#ibcon#*after write, iclass 15, count 0 2006.197.07:59:57.82#ibcon#*before return 0, iclass 15, count 0 2006.197.07:59:57.82#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.197.07:59:57.82#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.197.07:59:57.82#ibcon#about to clear, iclass 15 cls_cnt 0 2006.197.07:59:57.82#ibcon#cleared, iclass 15 cls_cnt 0 2006.197.07:59:57.82$vc4f8/valo=2,572.99 2006.197.07:59:57.82#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.197.07:59:57.82#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.197.07:59:57.82#ibcon#ireg 17 cls_cnt 0 2006.197.07:59:57.82#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.197.07:59:57.82#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.197.07:59:57.82#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.197.07:59:57.82#ibcon#enter wrdev, iclass 21, count 0 2006.197.07:59:57.82#ibcon#first serial, iclass 21, count 0 2006.197.07:59:57.82#ibcon#enter sib2, iclass 21, count 0 2006.197.07:59:57.82#ibcon#flushed, iclass 21, count 0 2006.197.07:59:57.82#ibcon#about to write, iclass 21, count 0 2006.197.07:59:57.82#ibcon#wrote, iclass 21, count 0 2006.197.07:59:57.82#ibcon#about to read 3, iclass 21, count 0 2006.197.07:59:57.84#ibcon#read 3, iclass 21, count 0 2006.197.07:59:57.84#ibcon#about to read 4, iclass 21, count 0 2006.197.07:59:57.84#ibcon#read 4, iclass 21, count 0 2006.197.07:59:57.84#ibcon#about to read 5, iclass 21, count 0 2006.197.07:59:57.84#ibcon#read 5, iclass 21, count 0 2006.197.07:59:57.84#ibcon#about to read 6, iclass 21, count 0 2006.197.07:59:57.84#ibcon#read 6, iclass 21, count 0 2006.197.07:59:57.84#ibcon#end of sib2, iclass 21, count 0 2006.197.07:59:57.84#ibcon#*mode == 0, iclass 21, count 0 2006.197.07:59:57.84#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.197.07:59:57.84#ibcon#[26=FRQ=02,572.99\r\n] 2006.197.07:59:57.84#ibcon#*before write, iclass 21, count 0 2006.197.07:59:57.84#ibcon#enter sib2, iclass 21, count 0 2006.197.07:59:57.84#ibcon#flushed, iclass 21, count 0 2006.197.07:59:57.84#ibcon#about to write, iclass 21, count 0 2006.197.07:59:57.84#ibcon#wrote, iclass 21, count 0 2006.197.07:59:57.84#ibcon#about to read 3, iclass 21, count 0 2006.197.07:59:57.88#ibcon#read 3, iclass 21, count 0 2006.197.07:59:57.88#ibcon#about to read 4, iclass 21, count 0 2006.197.07:59:57.88#ibcon#read 4, iclass 21, count 0 2006.197.07:59:57.88#ibcon#about to read 5, iclass 21, count 0 2006.197.07:59:57.88#ibcon#read 5, iclass 21, count 0 2006.197.07:59:57.88#ibcon#about to read 6, iclass 21, count 0 2006.197.07:59:57.88#ibcon#read 6, iclass 21, count 0 2006.197.07:59:57.88#ibcon#end of sib2, iclass 21, count 0 2006.197.07:59:57.88#ibcon#*after write, iclass 21, count 0 2006.197.07:59:57.88#ibcon#*before return 0, iclass 21, count 0 2006.197.07:59:57.88#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.197.07:59:57.88#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.197.07:59:57.88#ibcon#about to clear, iclass 21 cls_cnt 0 2006.197.07:59:57.88#ibcon#cleared, iclass 21 cls_cnt 0 2006.197.07:59:57.88$vc4f8/va=2,7 2006.197.07:59:57.88#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.197.07:59:57.88#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.197.07:59:57.88#ibcon#ireg 11 cls_cnt 2 2006.197.07:59:57.88#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.197.07:59:57.94#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.197.07:59:57.94#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.197.07:59:57.94#ibcon#enter wrdev, iclass 23, count 2 2006.197.07:59:57.94#ibcon#first serial, iclass 23, count 2 2006.197.07:59:57.94#ibcon#enter sib2, iclass 23, count 2 2006.197.07:59:57.94#ibcon#flushed, iclass 23, count 2 2006.197.07:59:57.94#ibcon#about to write, iclass 23, count 2 2006.197.07:59:57.94#ibcon#wrote, iclass 23, count 2 2006.197.07:59:57.94#ibcon#about to read 3, iclass 23, count 2 2006.197.07:59:57.96#ibcon#read 3, iclass 23, count 2 2006.197.07:59:57.96#ibcon#about to read 4, iclass 23, count 2 2006.197.07:59:57.96#ibcon#read 4, iclass 23, count 2 2006.197.07:59:57.96#ibcon#about to read 5, iclass 23, count 2 2006.197.07:59:57.96#ibcon#read 5, iclass 23, count 2 2006.197.07:59:57.96#ibcon#about to read 6, iclass 23, count 2 2006.197.07:59:57.96#ibcon#read 6, iclass 23, count 2 2006.197.07:59:57.96#ibcon#end of sib2, iclass 23, count 2 2006.197.07:59:57.96#ibcon#*mode == 0, iclass 23, count 2 2006.197.07:59:57.96#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.197.07:59:57.96#ibcon#[25=AT02-07\r\n] 2006.197.07:59:57.96#ibcon#*before write, iclass 23, count 2 2006.197.07:59:57.96#ibcon#enter sib2, iclass 23, count 2 2006.197.07:59:57.96#ibcon#flushed, iclass 23, count 2 2006.197.07:59:57.96#ibcon#about to write, iclass 23, count 2 2006.197.07:59:57.96#ibcon#wrote, iclass 23, count 2 2006.197.07:59:57.96#ibcon#about to read 3, iclass 23, count 2 2006.197.07:59:57.99#ibcon#read 3, iclass 23, count 2 2006.197.07:59:57.99#ibcon#about to read 4, iclass 23, count 2 2006.197.07:59:57.99#ibcon#read 4, iclass 23, count 2 2006.197.07:59:57.99#ibcon#about to read 5, iclass 23, count 2 2006.197.07:59:57.99#ibcon#read 5, iclass 23, count 2 2006.197.07:59:57.99#ibcon#about to read 6, iclass 23, count 2 2006.197.07:59:57.99#ibcon#read 6, iclass 23, count 2 2006.197.07:59:57.99#ibcon#end of sib2, iclass 23, count 2 2006.197.07:59:57.99#ibcon#*after write, iclass 23, count 2 2006.197.07:59:57.99#ibcon#*before return 0, iclass 23, count 2 2006.197.07:59:57.99#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.197.07:59:57.99#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.197.07:59:57.99#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.197.07:59:57.99#ibcon#ireg 7 cls_cnt 0 2006.197.07:59:57.99#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.197.07:59:58.11#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.197.07:59:58.11#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.197.07:59:58.11#ibcon#enter wrdev, iclass 23, count 0 2006.197.07:59:58.11#ibcon#first serial, iclass 23, count 0 2006.197.07:59:58.11#ibcon#enter sib2, iclass 23, count 0 2006.197.07:59:58.11#ibcon#flushed, iclass 23, count 0 2006.197.07:59:58.11#ibcon#about to write, iclass 23, count 0 2006.197.07:59:58.11#ibcon#wrote, iclass 23, count 0 2006.197.07:59:58.11#ibcon#about to read 3, iclass 23, count 0 2006.197.07:59:58.13#ibcon#read 3, iclass 23, count 0 2006.197.07:59:58.13#ibcon#about to read 4, iclass 23, count 0 2006.197.07:59:58.13#ibcon#read 4, iclass 23, count 0 2006.197.07:59:58.13#ibcon#about to read 5, iclass 23, count 0 2006.197.07:59:58.13#ibcon#read 5, iclass 23, count 0 2006.197.07:59:58.13#ibcon#about to read 6, iclass 23, count 0 2006.197.07:59:58.13#ibcon#read 6, iclass 23, count 0 2006.197.07:59:58.13#ibcon#end of sib2, iclass 23, count 0 2006.197.07:59:58.13#ibcon#*mode == 0, iclass 23, count 0 2006.197.07:59:58.13#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.197.07:59:58.13#ibcon#[25=USB\r\n] 2006.197.07:59:58.13#ibcon#*before write, iclass 23, count 0 2006.197.07:59:58.13#ibcon#enter sib2, iclass 23, count 0 2006.197.07:59:58.13#ibcon#flushed, iclass 23, count 0 2006.197.07:59:58.13#ibcon#about to write, iclass 23, count 0 2006.197.07:59:58.13#ibcon#wrote, iclass 23, count 0 2006.197.07:59:58.13#ibcon#about to read 3, iclass 23, count 0 2006.197.07:59:58.16#ibcon#read 3, iclass 23, count 0 2006.197.07:59:58.16#ibcon#about to read 4, iclass 23, count 0 2006.197.07:59:58.16#ibcon#read 4, iclass 23, count 0 2006.197.07:59:58.16#ibcon#about to read 5, iclass 23, count 0 2006.197.07:59:58.16#ibcon#read 5, iclass 23, count 0 2006.197.07:59:58.16#ibcon#about to read 6, iclass 23, count 0 2006.197.07:59:58.16#ibcon#read 6, iclass 23, count 0 2006.197.07:59:58.16#ibcon#end of sib2, iclass 23, count 0 2006.197.07:59:58.16#ibcon#*after write, iclass 23, count 0 2006.197.07:59:58.16#ibcon#*before return 0, iclass 23, count 0 2006.197.07:59:58.16#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.197.07:59:58.16#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.197.07:59:58.16#ibcon#about to clear, iclass 23 cls_cnt 0 2006.197.07:59:58.16#ibcon#cleared, iclass 23 cls_cnt 0 2006.197.07:59:58.16$vc4f8/valo=3,672.99 2006.197.07:59:58.16#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.197.07:59:58.16#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.197.07:59:58.16#ibcon#ireg 17 cls_cnt 0 2006.197.07:59:58.16#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.197.07:59:58.16#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.197.07:59:58.16#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.197.07:59:58.16#ibcon#enter wrdev, iclass 25, count 0 2006.197.07:59:58.16#ibcon#first serial, iclass 25, count 0 2006.197.07:59:58.16#ibcon#enter sib2, iclass 25, count 0 2006.197.07:59:58.16#ibcon#flushed, iclass 25, count 0 2006.197.07:59:58.16#ibcon#about to write, iclass 25, count 0 2006.197.07:59:58.16#ibcon#wrote, iclass 25, count 0 2006.197.07:59:58.16#ibcon#about to read 3, iclass 25, count 0 2006.197.07:59:58.18#ibcon#read 3, iclass 25, count 0 2006.197.07:59:58.18#ibcon#about to read 4, iclass 25, count 0 2006.197.07:59:58.18#ibcon#read 4, iclass 25, count 0 2006.197.07:59:58.18#ibcon#about to read 5, iclass 25, count 0 2006.197.07:59:58.18#ibcon#read 5, iclass 25, count 0 2006.197.07:59:58.18#ibcon#about to read 6, iclass 25, count 0 2006.197.07:59:58.18#ibcon#read 6, iclass 25, count 0 2006.197.07:59:58.18#ibcon#end of sib2, iclass 25, count 0 2006.197.07:59:58.18#ibcon#*mode == 0, iclass 25, count 0 2006.197.07:59:58.18#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.197.07:59:58.18#ibcon#[26=FRQ=03,672.99\r\n] 2006.197.07:59:58.18#ibcon#*before write, iclass 25, count 0 2006.197.07:59:58.18#ibcon#enter sib2, iclass 25, count 0 2006.197.07:59:58.18#ibcon#flushed, iclass 25, count 0 2006.197.07:59:58.18#ibcon#about to write, iclass 25, count 0 2006.197.07:59:58.18#ibcon#wrote, iclass 25, count 0 2006.197.07:59:58.18#ibcon#about to read 3, iclass 25, count 0 2006.197.07:59:58.22#ibcon#read 3, iclass 25, count 0 2006.197.07:59:58.22#ibcon#about to read 4, iclass 25, count 0 2006.197.07:59:58.22#ibcon#read 4, iclass 25, count 0 2006.197.07:59:58.22#ibcon#about to read 5, iclass 25, count 0 2006.197.07:59:58.22#ibcon#read 5, iclass 25, count 0 2006.197.07:59:58.22#ibcon#about to read 6, iclass 25, count 0 2006.197.07:59:58.22#ibcon#read 6, iclass 25, count 0 2006.197.07:59:58.22#ibcon#end of sib2, iclass 25, count 0 2006.197.07:59:58.22#ibcon#*after write, iclass 25, count 0 2006.197.07:59:58.22#ibcon#*before return 0, iclass 25, count 0 2006.197.07:59:58.22#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.197.07:59:58.22#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.197.07:59:58.22#ibcon#about to clear, iclass 25 cls_cnt 0 2006.197.07:59:58.22#ibcon#cleared, iclass 25 cls_cnt 0 2006.197.07:59:58.22$vc4f8/va=3,6 2006.197.07:59:58.22#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.197.07:59:58.22#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.197.07:59:58.22#ibcon#ireg 11 cls_cnt 2 2006.197.07:59:58.22#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.197.07:59:58.28#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.197.07:59:58.28#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.197.07:59:58.28#ibcon#enter wrdev, iclass 27, count 2 2006.197.07:59:58.28#ibcon#first serial, iclass 27, count 2 2006.197.07:59:58.28#ibcon#enter sib2, iclass 27, count 2 2006.197.07:59:58.28#ibcon#flushed, iclass 27, count 2 2006.197.07:59:58.28#ibcon#about to write, iclass 27, count 2 2006.197.07:59:58.28#ibcon#wrote, iclass 27, count 2 2006.197.07:59:58.28#ibcon#about to read 3, iclass 27, count 2 2006.197.07:59:58.30#ibcon#read 3, iclass 27, count 2 2006.197.07:59:58.30#ibcon#about to read 4, iclass 27, count 2 2006.197.07:59:58.30#ibcon#read 4, iclass 27, count 2 2006.197.07:59:58.30#ibcon#about to read 5, iclass 27, count 2 2006.197.07:59:58.30#ibcon#read 5, iclass 27, count 2 2006.197.07:59:58.30#ibcon#about to read 6, iclass 27, count 2 2006.197.07:59:58.30#ibcon#read 6, iclass 27, count 2 2006.197.07:59:58.30#ibcon#end of sib2, iclass 27, count 2 2006.197.07:59:58.30#ibcon#*mode == 0, iclass 27, count 2 2006.197.07:59:58.30#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.197.07:59:58.30#ibcon#[25=AT03-06\r\n] 2006.197.07:59:58.30#ibcon#*before write, iclass 27, count 2 2006.197.07:59:58.30#ibcon#enter sib2, iclass 27, count 2 2006.197.07:59:58.30#ibcon#flushed, iclass 27, count 2 2006.197.07:59:58.30#ibcon#about to write, iclass 27, count 2 2006.197.07:59:58.30#ibcon#wrote, iclass 27, count 2 2006.197.07:59:58.30#ibcon#about to read 3, iclass 27, count 2 2006.197.07:59:58.33#ibcon#read 3, iclass 27, count 2 2006.197.07:59:58.33#ibcon#about to read 4, iclass 27, count 2 2006.197.07:59:58.33#ibcon#read 4, iclass 27, count 2 2006.197.07:59:58.33#ibcon#about to read 5, iclass 27, count 2 2006.197.07:59:58.33#ibcon#read 5, iclass 27, count 2 2006.197.07:59:58.33#ibcon#about to read 6, iclass 27, count 2 2006.197.07:59:58.33#ibcon#read 6, iclass 27, count 2 2006.197.07:59:58.33#ibcon#end of sib2, iclass 27, count 2 2006.197.07:59:58.33#ibcon#*after write, iclass 27, count 2 2006.197.07:59:58.33#ibcon#*before return 0, iclass 27, count 2 2006.197.07:59:58.33#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.197.07:59:58.33#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.197.07:59:58.33#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.197.07:59:58.33#ibcon#ireg 7 cls_cnt 0 2006.197.07:59:58.33#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.197.07:59:58.45#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.197.07:59:58.45#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.197.07:59:58.45#ibcon#enter wrdev, iclass 27, count 0 2006.197.07:59:58.45#ibcon#first serial, iclass 27, count 0 2006.197.07:59:58.45#ibcon#enter sib2, iclass 27, count 0 2006.197.07:59:58.45#ibcon#flushed, iclass 27, count 0 2006.197.07:59:58.45#ibcon#about to write, iclass 27, count 0 2006.197.07:59:58.45#ibcon#wrote, iclass 27, count 0 2006.197.07:59:58.45#ibcon#about to read 3, iclass 27, count 0 2006.197.07:59:58.47#ibcon#read 3, iclass 27, count 0 2006.197.07:59:58.47#ibcon#about to read 4, iclass 27, count 0 2006.197.07:59:58.47#ibcon#read 4, iclass 27, count 0 2006.197.07:59:58.47#ibcon#about to read 5, iclass 27, count 0 2006.197.07:59:58.47#ibcon#read 5, iclass 27, count 0 2006.197.07:59:58.47#ibcon#about to read 6, iclass 27, count 0 2006.197.07:59:58.47#ibcon#read 6, iclass 27, count 0 2006.197.07:59:58.47#ibcon#end of sib2, iclass 27, count 0 2006.197.07:59:58.47#ibcon#*mode == 0, iclass 27, count 0 2006.197.07:59:58.47#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.197.07:59:58.47#ibcon#[25=USB\r\n] 2006.197.07:59:58.47#ibcon#*before write, iclass 27, count 0 2006.197.07:59:58.47#ibcon#enter sib2, iclass 27, count 0 2006.197.07:59:58.47#ibcon#flushed, iclass 27, count 0 2006.197.07:59:58.47#ibcon#about to write, iclass 27, count 0 2006.197.07:59:58.47#ibcon#wrote, iclass 27, count 0 2006.197.07:59:58.47#ibcon#about to read 3, iclass 27, count 0 2006.197.07:59:58.50#ibcon#read 3, iclass 27, count 0 2006.197.07:59:58.50#ibcon#about to read 4, iclass 27, count 0 2006.197.07:59:58.50#ibcon#read 4, iclass 27, count 0 2006.197.07:59:58.50#ibcon#about to read 5, iclass 27, count 0 2006.197.07:59:58.50#ibcon#read 5, iclass 27, count 0 2006.197.07:59:58.50#ibcon#about to read 6, iclass 27, count 0 2006.197.07:59:58.50#ibcon#read 6, iclass 27, count 0 2006.197.07:59:58.50#ibcon#end of sib2, iclass 27, count 0 2006.197.07:59:58.50#ibcon#*after write, iclass 27, count 0 2006.197.07:59:58.50#ibcon#*before return 0, iclass 27, count 0 2006.197.07:59:58.50#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.197.07:59:58.50#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.197.07:59:58.50#ibcon#about to clear, iclass 27 cls_cnt 0 2006.197.07:59:58.50#ibcon#cleared, iclass 27 cls_cnt 0 2006.197.07:59:58.50$vc4f8/valo=4,832.99 2006.197.07:59:58.50#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.197.07:59:58.50#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.197.07:59:58.50#ibcon#ireg 17 cls_cnt 0 2006.197.07:59:58.50#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.197.07:59:58.50#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.197.07:59:58.50#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.197.07:59:58.50#ibcon#enter wrdev, iclass 29, count 0 2006.197.07:59:58.50#ibcon#first serial, iclass 29, count 0 2006.197.07:59:58.50#ibcon#enter sib2, iclass 29, count 0 2006.197.07:59:58.50#ibcon#flushed, iclass 29, count 0 2006.197.07:59:58.50#ibcon#about to write, iclass 29, count 0 2006.197.07:59:58.50#ibcon#wrote, iclass 29, count 0 2006.197.07:59:58.50#ibcon#about to read 3, iclass 29, count 0 2006.197.07:59:58.52#ibcon#read 3, iclass 29, count 0 2006.197.07:59:58.52#ibcon#about to read 4, iclass 29, count 0 2006.197.07:59:58.52#ibcon#read 4, iclass 29, count 0 2006.197.07:59:58.52#ibcon#about to read 5, iclass 29, count 0 2006.197.07:59:58.52#ibcon#read 5, iclass 29, count 0 2006.197.07:59:58.52#ibcon#about to read 6, iclass 29, count 0 2006.197.07:59:58.52#ibcon#read 6, iclass 29, count 0 2006.197.07:59:58.52#ibcon#end of sib2, iclass 29, count 0 2006.197.07:59:58.52#ibcon#*mode == 0, iclass 29, count 0 2006.197.07:59:58.52#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.197.07:59:58.52#ibcon#[26=FRQ=04,832.99\r\n] 2006.197.07:59:58.52#ibcon#*before write, iclass 29, count 0 2006.197.07:59:58.52#ibcon#enter sib2, iclass 29, count 0 2006.197.07:59:58.52#ibcon#flushed, iclass 29, count 0 2006.197.07:59:58.52#ibcon#about to write, iclass 29, count 0 2006.197.07:59:58.52#ibcon#wrote, iclass 29, count 0 2006.197.07:59:58.52#ibcon#about to read 3, iclass 29, count 0 2006.197.07:59:58.56#ibcon#read 3, iclass 29, count 0 2006.197.07:59:58.56#ibcon#about to read 4, iclass 29, count 0 2006.197.07:59:58.56#ibcon#read 4, iclass 29, count 0 2006.197.07:59:58.56#ibcon#about to read 5, iclass 29, count 0 2006.197.07:59:58.56#ibcon#read 5, iclass 29, count 0 2006.197.07:59:58.56#ibcon#about to read 6, iclass 29, count 0 2006.197.07:59:58.56#ibcon#read 6, iclass 29, count 0 2006.197.07:59:58.56#ibcon#end of sib2, iclass 29, count 0 2006.197.07:59:58.56#ibcon#*after write, iclass 29, count 0 2006.197.07:59:58.56#ibcon#*before return 0, iclass 29, count 0 2006.197.07:59:58.56#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.197.07:59:58.56#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.197.07:59:58.56#ibcon#about to clear, iclass 29 cls_cnt 0 2006.197.07:59:58.56#ibcon#cleared, iclass 29 cls_cnt 0 2006.197.07:59:58.56$vc4f8/va=4,7 2006.197.07:59:58.56#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.197.07:59:58.56#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.197.07:59:58.56#ibcon#ireg 11 cls_cnt 2 2006.197.07:59:58.56#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.197.07:59:58.62#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.197.07:59:58.62#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.197.07:59:58.62#ibcon#enter wrdev, iclass 31, count 2 2006.197.07:59:58.62#ibcon#first serial, iclass 31, count 2 2006.197.07:59:58.62#ibcon#enter sib2, iclass 31, count 2 2006.197.07:59:58.62#ibcon#flushed, iclass 31, count 2 2006.197.07:59:58.62#ibcon#about to write, iclass 31, count 2 2006.197.07:59:58.62#ibcon#wrote, iclass 31, count 2 2006.197.07:59:58.62#ibcon#about to read 3, iclass 31, count 2 2006.197.07:59:58.64#ibcon#read 3, iclass 31, count 2 2006.197.07:59:58.64#ibcon#about to read 4, iclass 31, count 2 2006.197.07:59:58.64#ibcon#read 4, iclass 31, count 2 2006.197.07:59:58.64#ibcon#about to read 5, iclass 31, count 2 2006.197.07:59:58.64#ibcon#read 5, iclass 31, count 2 2006.197.07:59:58.64#ibcon#about to read 6, iclass 31, count 2 2006.197.07:59:58.64#ibcon#read 6, iclass 31, count 2 2006.197.07:59:58.64#ibcon#end of sib2, iclass 31, count 2 2006.197.07:59:58.64#ibcon#*mode == 0, iclass 31, count 2 2006.197.07:59:58.64#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.197.07:59:58.64#ibcon#[25=AT04-07\r\n] 2006.197.07:59:58.64#ibcon#*before write, iclass 31, count 2 2006.197.07:59:58.64#ibcon#enter sib2, iclass 31, count 2 2006.197.07:59:58.64#ibcon#flushed, iclass 31, count 2 2006.197.07:59:58.64#ibcon#about to write, iclass 31, count 2 2006.197.07:59:58.64#ibcon#wrote, iclass 31, count 2 2006.197.07:59:58.64#ibcon#about to read 3, iclass 31, count 2 2006.197.07:59:58.67#ibcon#read 3, iclass 31, count 2 2006.197.07:59:58.67#ibcon#about to read 4, iclass 31, count 2 2006.197.07:59:58.67#ibcon#read 4, iclass 31, count 2 2006.197.07:59:58.67#ibcon#about to read 5, iclass 31, count 2 2006.197.07:59:58.67#ibcon#read 5, iclass 31, count 2 2006.197.07:59:58.67#ibcon#about to read 6, iclass 31, count 2 2006.197.07:59:58.67#ibcon#read 6, iclass 31, count 2 2006.197.07:59:58.67#ibcon#end of sib2, iclass 31, count 2 2006.197.07:59:58.67#ibcon#*after write, iclass 31, count 2 2006.197.07:59:58.67#ibcon#*before return 0, iclass 31, count 2 2006.197.07:59:58.67#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.197.07:59:58.67#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.197.07:59:58.67#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.197.07:59:58.67#ibcon#ireg 7 cls_cnt 0 2006.197.07:59:58.67#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.197.07:59:58.79#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.197.07:59:58.79#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.197.07:59:58.79#ibcon#enter wrdev, iclass 31, count 0 2006.197.07:59:58.79#ibcon#first serial, iclass 31, count 0 2006.197.07:59:58.79#ibcon#enter sib2, iclass 31, count 0 2006.197.07:59:58.79#ibcon#flushed, iclass 31, count 0 2006.197.07:59:58.79#ibcon#about to write, iclass 31, count 0 2006.197.07:59:58.79#ibcon#wrote, iclass 31, count 0 2006.197.07:59:58.79#ibcon#about to read 3, iclass 31, count 0 2006.197.07:59:58.81#ibcon#read 3, iclass 31, count 0 2006.197.07:59:58.81#ibcon#about to read 4, iclass 31, count 0 2006.197.07:59:58.81#ibcon#read 4, iclass 31, count 0 2006.197.07:59:58.81#ibcon#about to read 5, iclass 31, count 0 2006.197.07:59:58.81#ibcon#read 5, iclass 31, count 0 2006.197.07:59:58.81#ibcon#about to read 6, iclass 31, count 0 2006.197.07:59:58.81#ibcon#read 6, iclass 31, count 0 2006.197.07:59:58.81#ibcon#end of sib2, iclass 31, count 0 2006.197.07:59:58.81#ibcon#*mode == 0, iclass 31, count 0 2006.197.07:59:58.81#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.197.07:59:58.81#ibcon#[25=USB\r\n] 2006.197.07:59:58.81#ibcon#*before write, iclass 31, count 0 2006.197.07:59:58.81#ibcon#enter sib2, iclass 31, count 0 2006.197.07:59:58.81#ibcon#flushed, iclass 31, count 0 2006.197.07:59:58.81#ibcon#about to write, iclass 31, count 0 2006.197.07:59:58.81#ibcon#wrote, iclass 31, count 0 2006.197.07:59:58.81#ibcon#about to read 3, iclass 31, count 0 2006.197.07:59:58.84#ibcon#read 3, iclass 31, count 0 2006.197.07:59:58.84#ibcon#about to read 4, iclass 31, count 0 2006.197.07:59:58.84#ibcon#read 4, iclass 31, count 0 2006.197.07:59:58.84#ibcon#about to read 5, iclass 31, count 0 2006.197.07:59:58.84#ibcon#read 5, iclass 31, count 0 2006.197.07:59:58.84#ibcon#about to read 6, iclass 31, count 0 2006.197.07:59:58.84#ibcon#read 6, iclass 31, count 0 2006.197.07:59:58.84#ibcon#end of sib2, iclass 31, count 0 2006.197.07:59:58.84#ibcon#*after write, iclass 31, count 0 2006.197.07:59:58.84#ibcon#*before return 0, iclass 31, count 0 2006.197.07:59:58.84#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.197.07:59:58.84#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.197.07:59:58.84#ibcon#about to clear, iclass 31 cls_cnt 0 2006.197.07:59:58.84#ibcon#cleared, iclass 31 cls_cnt 0 2006.197.07:59:58.84$vc4f8/valo=5,652.99 2006.197.07:59:58.84#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.197.07:59:58.84#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.197.07:59:58.84#ibcon#ireg 17 cls_cnt 0 2006.197.07:59:58.84#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.197.07:59:58.84#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.197.07:59:58.84#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.197.07:59:58.84#ibcon#enter wrdev, iclass 33, count 0 2006.197.07:59:58.84#ibcon#first serial, iclass 33, count 0 2006.197.07:59:58.84#ibcon#enter sib2, iclass 33, count 0 2006.197.07:59:58.84#ibcon#flushed, iclass 33, count 0 2006.197.07:59:58.84#ibcon#about to write, iclass 33, count 0 2006.197.07:59:58.84#ibcon#wrote, iclass 33, count 0 2006.197.07:59:58.84#ibcon#about to read 3, iclass 33, count 0 2006.197.07:59:58.86#ibcon#read 3, iclass 33, count 0 2006.197.07:59:58.86#ibcon#about to read 4, iclass 33, count 0 2006.197.07:59:58.86#ibcon#read 4, iclass 33, count 0 2006.197.07:59:58.86#ibcon#about to read 5, iclass 33, count 0 2006.197.07:59:58.86#ibcon#read 5, iclass 33, count 0 2006.197.07:59:58.86#ibcon#about to read 6, iclass 33, count 0 2006.197.07:59:58.86#ibcon#read 6, iclass 33, count 0 2006.197.07:59:58.86#ibcon#end of sib2, iclass 33, count 0 2006.197.07:59:58.86#ibcon#*mode == 0, iclass 33, count 0 2006.197.07:59:58.86#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.197.07:59:58.86#ibcon#[26=FRQ=05,652.99\r\n] 2006.197.07:59:58.86#ibcon#*before write, iclass 33, count 0 2006.197.07:59:58.86#ibcon#enter sib2, iclass 33, count 0 2006.197.07:59:58.86#ibcon#flushed, iclass 33, count 0 2006.197.07:59:58.86#ibcon#about to write, iclass 33, count 0 2006.197.07:59:58.86#ibcon#wrote, iclass 33, count 0 2006.197.07:59:58.86#ibcon#about to read 3, iclass 33, count 0 2006.197.07:59:58.90#ibcon#read 3, iclass 33, count 0 2006.197.07:59:58.90#ibcon#about to read 4, iclass 33, count 0 2006.197.07:59:58.90#ibcon#read 4, iclass 33, count 0 2006.197.07:59:58.90#ibcon#about to read 5, iclass 33, count 0 2006.197.07:59:58.90#ibcon#read 5, iclass 33, count 0 2006.197.07:59:58.90#ibcon#about to read 6, iclass 33, count 0 2006.197.07:59:58.90#ibcon#read 6, iclass 33, count 0 2006.197.07:59:58.90#ibcon#end of sib2, iclass 33, count 0 2006.197.07:59:58.90#ibcon#*after write, iclass 33, count 0 2006.197.07:59:58.90#ibcon#*before return 0, iclass 33, count 0 2006.197.07:59:58.90#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.197.07:59:58.90#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.197.07:59:58.90#ibcon#about to clear, iclass 33 cls_cnt 0 2006.197.07:59:58.90#ibcon#cleared, iclass 33 cls_cnt 0 2006.197.07:59:58.90$vc4f8/va=5,7 2006.197.07:59:58.90#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.197.07:59:58.90#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.197.07:59:58.90#ibcon#ireg 11 cls_cnt 2 2006.197.07:59:58.90#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.197.07:59:58.96#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.197.07:59:58.96#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.197.07:59:58.96#ibcon#enter wrdev, iclass 35, count 2 2006.197.07:59:58.96#ibcon#first serial, iclass 35, count 2 2006.197.07:59:58.96#ibcon#enter sib2, iclass 35, count 2 2006.197.07:59:58.96#ibcon#flushed, iclass 35, count 2 2006.197.07:59:58.96#ibcon#about to write, iclass 35, count 2 2006.197.07:59:58.96#ibcon#wrote, iclass 35, count 2 2006.197.07:59:58.96#ibcon#about to read 3, iclass 35, count 2 2006.197.07:59:58.98#ibcon#read 3, iclass 35, count 2 2006.197.07:59:58.98#ibcon#about to read 4, iclass 35, count 2 2006.197.07:59:58.98#ibcon#read 4, iclass 35, count 2 2006.197.07:59:58.98#ibcon#about to read 5, iclass 35, count 2 2006.197.07:59:58.98#ibcon#read 5, iclass 35, count 2 2006.197.07:59:58.98#ibcon#about to read 6, iclass 35, count 2 2006.197.07:59:58.98#ibcon#read 6, iclass 35, count 2 2006.197.07:59:58.98#ibcon#end of sib2, iclass 35, count 2 2006.197.07:59:58.98#ibcon#*mode == 0, iclass 35, count 2 2006.197.07:59:58.98#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.197.07:59:58.98#ibcon#[25=AT05-07\r\n] 2006.197.07:59:58.98#ibcon#*before write, iclass 35, count 2 2006.197.07:59:58.98#ibcon#enter sib2, iclass 35, count 2 2006.197.07:59:58.98#ibcon#flushed, iclass 35, count 2 2006.197.07:59:58.98#ibcon#about to write, iclass 35, count 2 2006.197.07:59:58.98#ibcon#wrote, iclass 35, count 2 2006.197.07:59:58.98#ibcon#about to read 3, iclass 35, count 2 2006.197.07:59:59.01#ibcon#read 3, iclass 35, count 2 2006.197.07:59:59.01#ibcon#about to read 4, iclass 35, count 2 2006.197.07:59:59.01#ibcon#read 4, iclass 35, count 2 2006.197.07:59:59.01#ibcon#about to read 5, iclass 35, count 2 2006.197.07:59:59.01#ibcon#read 5, iclass 35, count 2 2006.197.07:59:59.01#ibcon#about to read 6, iclass 35, count 2 2006.197.07:59:59.01#ibcon#read 6, iclass 35, count 2 2006.197.07:59:59.01#ibcon#end of sib2, iclass 35, count 2 2006.197.07:59:59.01#ibcon#*after write, iclass 35, count 2 2006.197.07:59:59.01#ibcon#*before return 0, iclass 35, count 2 2006.197.07:59:59.01#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.197.07:59:59.01#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.197.07:59:59.01#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.197.07:59:59.01#ibcon#ireg 7 cls_cnt 0 2006.197.07:59:59.01#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.197.07:59:59.13#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.197.07:59:59.13#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.197.07:59:59.13#ibcon#enter wrdev, iclass 35, count 0 2006.197.07:59:59.13#ibcon#first serial, iclass 35, count 0 2006.197.07:59:59.13#ibcon#enter sib2, iclass 35, count 0 2006.197.07:59:59.13#ibcon#flushed, iclass 35, count 0 2006.197.07:59:59.13#ibcon#about to write, iclass 35, count 0 2006.197.07:59:59.13#ibcon#wrote, iclass 35, count 0 2006.197.07:59:59.13#ibcon#about to read 3, iclass 35, count 0 2006.197.07:59:59.15#ibcon#read 3, iclass 35, count 0 2006.197.07:59:59.15#ibcon#about to read 4, iclass 35, count 0 2006.197.07:59:59.15#ibcon#read 4, iclass 35, count 0 2006.197.07:59:59.15#ibcon#about to read 5, iclass 35, count 0 2006.197.07:59:59.15#ibcon#read 5, iclass 35, count 0 2006.197.07:59:59.15#ibcon#about to read 6, iclass 35, count 0 2006.197.07:59:59.15#ibcon#read 6, iclass 35, count 0 2006.197.07:59:59.15#ibcon#end of sib2, iclass 35, count 0 2006.197.07:59:59.15#ibcon#*mode == 0, iclass 35, count 0 2006.197.07:59:59.15#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.197.07:59:59.15#ibcon#[25=USB\r\n] 2006.197.07:59:59.15#ibcon#*before write, iclass 35, count 0 2006.197.07:59:59.15#ibcon#enter sib2, iclass 35, count 0 2006.197.07:59:59.15#ibcon#flushed, iclass 35, count 0 2006.197.07:59:59.15#ibcon#about to write, iclass 35, count 0 2006.197.07:59:59.15#ibcon#wrote, iclass 35, count 0 2006.197.07:59:59.15#ibcon#about to read 3, iclass 35, count 0 2006.197.07:59:59.18#ibcon#read 3, iclass 35, count 0 2006.197.07:59:59.18#ibcon#about to read 4, iclass 35, count 0 2006.197.07:59:59.18#ibcon#read 4, iclass 35, count 0 2006.197.07:59:59.18#ibcon#about to read 5, iclass 35, count 0 2006.197.07:59:59.18#ibcon#read 5, iclass 35, count 0 2006.197.07:59:59.18#ibcon#about to read 6, iclass 35, count 0 2006.197.07:59:59.18#ibcon#read 6, iclass 35, count 0 2006.197.07:59:59.18#ibcon#end of sib2, iclass 35, count 0 2006.197.07:59:59.18#ibcon#*after write, iclass 35, count 0 2006.197.07:59:59.18#ibcon#*before return 0, iclass 35, count 0 2006.197.07:59:59.18#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.197.07:59:59.18#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.197.07:59:59.18#ibcon#about to clear, iclass 35 cls_cnt 0 2006.197.07:59:59.18#ibcon#cleared, iclass 35 cls_cnt 0 2006.197.07:59:59.18$vc4f8/valo=6,772.99 2006.197.07:59:59.18#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.197.07:59:59.18#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.197.07:59:59.18#ibcon#ireg 17 cls_cnt 0 2006.197.07:59:59.18#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.197.07:59:59.18#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.197.07:59:59.18#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.197.07:59:59.18#ibcon#enter wrdev, iclass 37, count 0 2006.197.07:59:59.18#ibcon#first serial, iclass 37, count 0 2006.197.07:59:59.18#ibcon#enter sib2, iclass 37, count 0 2006.197.07:59:59.18#ibcon#flushed, iclass 37, count 0 2006.197.07:59:59.18#ibcon#about to write, iclass 37, count 0 2006.197.07:59:59.18#ibcon#wrote, iclass 37, count 0 2006.197.07:59:59.18#ibcon#about to read 3, iclass 37, count 0 2006.197.07:59:59.20#ibcon#read 3, iclass 37, count 0 2006.197.07:59:59.20#ibcon#about to read 4, iclass 37, count 0 2006.197.07:59:59.20#ibcon#read 4, iclass 37, count 0 2006.197.07:59:59.20#ibcon#about to read 5, iclass 37, count 0 2006.197.07:59:59.20#ibcon#read 5, iclass 37, count 0 2006.197.07:59:59.20#ibcon#about to read 6, iclass 37, count 0 2006.197.07:59:59.20#ibcon#read 6, iclass 37, count 0 2006.197.07:59:59.20#ibcon#end of sib2, iclass 37, count 0 2006.197.07:59:59.20#ibcon#*mode == 0, iclass 37, count 0 2006.197.07:59:59.20#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.197.07:59:59.20#ibcon#[26=FRQ=06,772.99\r\n] 2006.197.07:59:59.20#ibcon#*before write, iclass 37, count 0 2006.197.07:59:59.20#ibcon#enter sib2, iclass 37, count 0 2006.197.07:59:59.20#ibcon#flushed, iclass 37, count 0 2006.197.07:59:59.20#ibcon#about to write, iclass 37, count 0 2006.197.07:59:59.20#ibcon#wrote, iclass 37, count 0 2006.197.07:59:59.20#ibcon#about to read 3, iclass 37, count 0 2006.197.07:59:59.24#ibcon#read 3, iclass 37, count 0 2006.197.07:59:59.24#ibcon#about to read 4, iclass 37, count 0 2006.197.07:59:59.24#ibcon#read 4, iclass 37, count 0 2006.197.07:59:59.24#ibcon#about to read 5, iclass 37, count 0 2006.197.07:59:59.24#ibcon#read 5, iclass 37, count 0 2006.197.07:59:59.24#ibcon#about to read 6, iclass 37, count 0 2006.197.07:59:59.24#ibcon#read 6, iclass 37, count 0 2006.197.07:59:59.24#ibcon#end of sib2, iclass 37, count 0 2006.197.07:59:59.24#ibcon#*after write, iclass 37, count 0 2006.197.07:59:59.24#ibcon#*before return 0, iclass 37, count 0 2006.197.07:59:59.24#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.197.07:59:59.24#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.197.07:59:59.24#ibcon#about to clear, iclass 37 cls_cnt 0 2006.197.07:59:59.24#ibcon#cleared, iclass 37 cls_cnt 0 2006.197.07:59:59.24$vc4f8/va=6,6 2006.197.07:59:59.24#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.197.07:59:59.24#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.197.07:59:59.24#ibcon#ireg 11 cls_cnt 2 2006.197.07:59:59.24#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.197.07:59:59.30#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.197.07:59:59.30#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.197.07:59:59.30#ibcon#enter wrdev, iclass 39, count 2 2006.197.07:59:59.30#ibcon#first serial, iclass 39, count 2 2006.197.07:59:59.30#ibcon#enter sib2, iclass 39, count 2 2006.197.07:59:59.30#ibcon#flushed, iclass 39, count 2 2006.197.07:59:59.30#ibcon#about to write, iclass 39, count 2 2006.197.07:59:59.30#ibcon#wrote, iclass 39, count 2 2006.197.07:59:59.30#ibcon#about to read 3, iclass 39, count 2 2006.197.07:59:59.32#ibcon#read 3, iclass 39, count 2 2006.197.07:59:59.32#ibcon#about to read 4, iclass 39, count 2 2006.197.07:59:59.32#ibcon#read 4, iclass 39, count 2 2006.197.07:59:59.32#ibcon#about to read 5, iclass 39, count 2 2006.197.07:59:59.32#ibcon#read 5, iclass 39, count 2 2006.197.07:59:59.32#ibcon#about to read 6, iclass 39, count 2 2006.197.07:59:59.32#ibcon#read 6, iclass 39, count 2 2006.197.07:59:59.32#ibcon#end of sib2, iclass 39, count 2 2006.197.07:59:59.32#ibcon#*mode == 0, iclass 39, count 2 2006.197.07:59:59.32#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.197.07:59:59.32#ibcon#[25=AT06-06\r\n] 2006.197.07:59:59.32#ibcon#*before write, iclass 39, count 2 2006.197.07:59:59.32#ibcon#enter sib2, iclass 39, count 2 2006.197.07:59:59.32#ibcon#flushed, iclass 39, count 2 2006.197.07:59:59.32#ibcon#about to write, iclass 39, count 2 2006.197.07:59:59.32#ibcon#wrote, iclass 39, count 2 2006.197.07:59:59.32#ibcon#about to read 3, iclass 39, count 2 2006.197.07:59:59.35#ibcon#read 3, iclass 39, count 2 2006.197.07:59:59.35#ibcon#about to read 4, iclass 39, count 2 2006.197.07:59:59.35#ibcon#read 4, iclass 39, count 2 2006.197.07:59:59.35#ibcon#about to read 5, iclass 39, count 2 2006.197.07:59:59.35#ibcon#read 5, iclass 39, count 2 2006.197.07:59:59.35#ibcon#about to read 6, iclass 39, count 2 2006.197.07:59:59.35#ibcon#read 6, iclass 39, count 2 2006.197.07:59:59.35#ibcon#end of sib2, iclass 39, count 2 2006.197.07:59:59.35#ibcon#*after write, iclass 39, count 2 2006.197.07:59:59.35#ibcon#*before return 0, iclass 39, count 2 2006.197.07:59:59.35#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.197.07:59:59.35#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.197.07:59:59.35#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.197.07:59:59.35#ibcon#ireg 7 cls_cnt 0 2006.197.07:59:59.35#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.197.07:59:59.47#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.197.07:59:59.47#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.197.07:59:59.47#ibcon#enter wrdev, iclass 39, count 0 2006.197.07:59:59.47#ibcon#first serial, iclass 39, count 0 2006.197.07:59:59.47#ibcon#enter sib2, iclass 39, count 0 2006.197.07:59:59.47#ibcon#flushed, iclass 39, count 0 2006.197.07:59:59.47#ibcon#about to write, iclass 39, count 0 2006.197.07:59:59.47#ibcon#wrote, iclass 39, count 0 2006.197.07:59:59.47#ibcon#about to read 3, iclass 39, count 0 2006.197.07:59:59.49#ibcon#read 3, iclass 39, count 0 2006.197.07:59:59.49#ibcon#about to read 4, iclass 39, count 0 2006.197.07:59:59.49#ibcon#read 4, iclass 39, count 0 2006.197.07:59:59.49#ibcon#about to read 5, iclass 39, count 0 2006.197.07:59:59.49#ibcon#read 5, iclass 39, count 0 2006.197.07:59:59.49#ibcon#about to read 6, iclass 39, count 0 2006.197.07:59:59.49#ibcon#read 6, iclass 39, count 0 2006.197.07:59:59.49#ibcon#end of sib2, iclass 39, count 0 2006.197.07:59:59.49#ibcon#*mode == 0, iclass 39, count 0 2006.197.07:59:59.49#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.197.07:59:59.49#ibcon#[25=USB\r\n] 2006.197.07:59:59.49#ibcon#*before write, iclass 39, count 0 2006.197.07:59:59.49#ibcon#enter sib2, iclass 39, count 0 2006.197.07:59:59.49#ibcon#flushed, iclass 39, count 0 2006.197.07:59:59.49#ibcon#about to write, iclass 39, count 0 2006.197.07:59:59.49#ibcon#wrote, iclass 39, count 0 2006.197.07:59:59.49#ibcon#about to read 3, iclass 39, count 0 2006.197.07:59:59.52#ibcon#read 3, iclass 39, count 0 2006.197.07:59:59.52#ibcon#about to read 4, iclass 39, count 0 2006.197.07:59:59.52#ibcon#read 4, iclass 39, count 0 2006.197.07:59:59.52#ibcon#about to read 5, iclass 39, count 0 2006.197.07:59:59.52#ibcon#read 5, iclass 39, count 0 2006.197.07:59:59.52#ibcon#about to read 6, iclass 39, count 0 2006.197.07:59:59.52#ibcon#read 6, iclass 39, count 0 2006.197.07:59:59.52#ibcon#end of sib2, iclass 39, count 0 2006.197.07:59:59.52#ibcon#*after write, iclass 39, count 0 2006.197.07:59:59.52#ibcon#*before return 0, iclass 39, count 0 2006.197.07:59:59.52#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.197.07:59:59.52#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.197.07:59:59.52#ibcon#about to clear, iclass 39 cls_cnt 0 2006.197.07:59:59.52#ibcon#cleared, iclass 39 cls_cnt 0 2006.197.07:59:59.52$vc4f8/valo=7,832.99 2006.197.07:59:59.52#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.197.07:59:59.52#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.197.07:59:59.52#ibcon#ireg 17 cls_cnt 0 2006.197.07:59:59.52#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.197.07:59:59.52#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.197.07:59:59.52#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.197.07:59:59.52#ibcon#enter wrdev, iclass 3, count 0 2006.197.07:59:59.52#ibcon#first serial, iclass 3, count 0 2006.197.07:59:59.52#ibcon#enter sib2, iclass 3, count 0 2006.197.07:59:59.52#ibcon#flushed, iclass 3, count 0 2006.197.07:59:59.52#ibcon#about to write, iclass 3, count 0 2006.197.07:59:59.52#ibcon#wrote, iclass 3, count 0 2006.197.07:59:59.52#ibcon#about to read 3, iclass 3, count 0 2006.197.07:59:59.54#ibcon#read 3, iclass 3, count 0 2006.197.07:59:59.54#ibcon#about to read 4, iclass 3, count 0 2006.197.07:59:59.54#ibcon#read 4, iclass 3, count 0 2006.197.07:59:59.54#ibcon#about to read 5, iclass 3, count 0 2006.197.07:59:59.54#ibcon#read 5, iclass 3, count 0 2006.197.07:59:59.54#ibcon#about to read 6, iclass 3, count 0 2006.197.07:59:59.54#ibcon#read 6, iclass 3, count 0 2006.197.07:59:59.54#ibcon#end of sib2, iclass 3, count 0 2006.197.07:59:59.54#ibcon#*mode == 0, iclass 3, count 0 2006.197.07:59:59.54#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.197.07:59:59.54#ibcon#[26=FRQ=07,832.99\r\n] 2006.197.07:59:59.54#ibcon#*before write, iclass 3, count 0 2006.197.07:59:59.54#ibcon#enter sib2, iclass 3, count 0 2006.197.07:59:59.54#ibcon#flushed, iclass 3, count 0 2006.197.07:59:59.54#ibcon#about to write, iclass 3, count 0 2006.197.07:59:59.54#ibcon#wrote, iclass 3, count 0 2006.197.07:59:59.54#ibcon#about to read 3, iclass 3, count 0 2006.197.07:59:59.58#ibcon#read 3, iclass 3, count 0 2006.197.07:59:59.58#ibcon#about to read 4, iclass 3, count 0 2006.197.07:59:59.58#ibcon#read 4, iclass 3, count 0 2006.197.07:59:59.58#ibcon#about to read 5, iclass 3, count 0 2006.197.07:59:59.58#ibcon#read 5, iclass 3, count 0 2006.197.07:59:59.58#ibcon#about to read 6, iclass 3, count 0 2006.197.07:59:59.58#ibcon#read 6, iclass 3, count 0 2006.197.07:59:59.58#ibcon#end of sib2, iclass 3, count 0 2006.197.07:59:59.58#ibcon#*after write, iclass 3, count 0 2006.197.07:59:59.58#ibcon#*before return 0, iclass 3, count 0 2006.197.07:59:59.58#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.197.07:59:59.58#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.197.07:59:59.58#ibcon#about to clear, iclass 3 cls_cnt 0 2006.197.07:59:59.58#ibcon#cleared, iclass 3 cls_cnt 0 2006.197.07:59:59.58$vc4f8/va=7,6 2006.197.07:59:59.58#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.197.07:59:59.58#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.197.07:59:59.58#ibcon#ireg 11 cls_cnt 2 2006.197.07:59:59.58#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.197.07:59:59.64#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.197.07:59:59.64#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.197.07:59:59.64#ibcon#enter wrdev, iclass 5, count 2 2006.197.07:59:59.64#ibcon#first serial, iclass 5, count 2 2006.197.07:59:59.64#ibcon#enter sib2, iclass 5, count 2 2006.197.07:59:59.64#ibcon#flushed, iclass 5, count 2 2006.197.07:59:59.64#ibcon#about to write, iclass 5, count 2 2006.197.07:59:59.64#ibcon#wrote, iclass 5, count 2 2006.197.07:59:59.64#ibcon#about to read 3, iclass 5, count 2 2006.197.07:59:59.66#ibcon#read 3, iclass 5, count 2 2006.197.07:59:59.66#ibcon#about to read 4, iclass 5, count 2 2006.197.07:59:59.66#ibcon#read 4, iclass 5, count 2 2006.197.07:59:59.66#ibcon#about to read 5, iclass 5, count 2 2006.197.07:59:59.66#ibcon#read 5, iclass 5, count 2 2006.197.07:59:59.66#ibcon#about to read 6, iclass 5, count 2 2006.197.07:59:59.66#ibcon#read 6, iclass 5, count 2 2006.197.07:59:59.66#ibcon#end of sib2, iclass 5, count 2 2006.197.07:59:59.66#ibcon#*mode == 0, iclass 5, count 2 2006.197.07:59:59.66#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.197.07:59:59.66#ibcon#[25=AT07-06\r\n] 2006.197.07:59:59.66#ibcon#*before write, iclass 5, count 2 2006.197.07:59:59.66#ibcon#enter sib2, iclass 5, count 2 2006.197.07:59:59.66#ibcon#flushed, iclass 5, count 2 2006.197.07:59:59.66#ibcon#about to write, iclass 5, count 2 2006.197.07:59:59.66#ibcon#wrote, iclass 5, count 2 2006.197.07:59:59.66#ibcon#about to read 3, iclass 5, count 2 2006.197.07:59:59.69#ibcon#read 3, iclass 5, count 2 2006.197.07:59:59.69#ibcon#about to read 4, iclass 5, count 2 2006.197.07:59:59.69#ibcon#read 4, iclass 5, count 2 2006.197.07:59:59.69#ibcon#about to read 5, iclass 5, count 2 2006.197.07:59:59.69#ibcon#read 5, iclass 5, count 2 2006.197.07:59:59.69#ibcon#about to read 6, iclass 5, count 2 2006.197.07:59:59.69#ibcon#read 6, iclass 5, count 2 2006.197.07:59:59.69#ibcon#end of sib2, iclass 5, count 2 2006.197.07:59:59.69#ibcon#*after write, iclass 5, count 2 2006.197.07:59:59.69#ibcon#*before return 0, iclass 5, count 2 2006.197.07:59:59.69#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.197.07:59:59.69#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.197.07:59:59.69#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.197.07:59:59.69#ibcon#ireg 7 cls_cnt 0 2006.197.07:59:59.69#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.197.07:59:59.81#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.197.07:59:59.81#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.197.07:59:59.81#ibcon#enter wrdev, iclass 5, count 0 2006.197.07:59:59.81#ibcon#first serial, iclass 5, count 0 2006.197.07:59:59.81#ibcon#enter sib2, iclass 5, count 0 2006.197.07:59:59.81#ibcon#flushed, iclass 5, count 0 2006.197.07:59:59.81#ibcon#about to write, iclass 5, count 0 2006.197.07:59:59.81#ibcon#wrote, iclass 5, count 0 2006.197.07:59:59.81#ibcon#about to read 3, iclass 5, count 0 2006.197.07:59:59.83#ibcon#read 3, iclass 5, count 0 2006.197.07:59:59.83#ibcon#about to read 4, iclass 5, count 0 2006.197.07:59:59.83#ibcon#read 4, iclass 5, count 0 2006.197.07:59:59.83#ibcon#about to read 5, iclass 5, count 0 2006.197.07:59:59.83#ibcon#read 5, iclass 5, count 0 2006.197.07:59:59.83#ibcon#about to read 6, iclass 5, count 0 2006.197.07:59:59.83#ibcon#read 6, iclass 5, count 0 2006.197.07:59:59.83#ibcon#end of sib2, iclass 5, count 0 2006.197.07:59:59.83#ibcon#*mode == 0, iclass 5, count 0 2006.197.07:59:59.83#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.197.07:59:59.83#ibcon#[25=USB\r\n] 2006.197.07:59:59.83#ibcon#*before write, iclass 5, count 0 2006.197.07:59:59.83#ibcon#enter sib2, iclass 5, count 0 2006.197.07:59:59.83#ibcon#flushed, iclass 5, count 0 2006.197.07:59:59.83#ibcon#about to write, iclass 5, count 0 2006.197.07:59:59.83#ibcon#wrote, iclass 5, count 0 2006.197.07:59:59.83#ibcon#about to read 3, iclass 5, count 0 2006.197.07:59:59.86#ibcon#read 3, iclass 5, count 0 2006.197.07:59:59.86#ibcon#about to read 4, iclass 5, count 0 2006.197.07:59:59.86#ibcon#read 4, iclass 5, count 0 2006.197.07:59:59.86#ibcon#about to read 5, iclass 5, count 0 2006.197.07:59:59.86#ibcon#read 5, iclass 5, count 0 2006.197.07:59:59.86#ibcon#about to read 6, iclass 5, count 0 2006.197.07:59:59.86#ibcon#read 6, iclass 5, count 0 2006.197.07:59:59.86#ibcon#end of sib2, iclass 5, count 0 2006.197.07:59:59.86#ibcon#*after write, iclass 5, count 0 2006.197.07:59:59.86#ibcon#*before return 0, iclass 5, count 0 2006.197.07:59:59.86#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.197.07:59:59.86#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.197.07:59:59.86#ibcon#about to clear, iclass 5 cls_cnt 0 2006.197.07:59:59.86#ibcon#cleared, iclass 5 cls_cnt 0 2006.197.07:59:59.86$vc4f8/valo=8,852.99 2006.197.07:59:59.86#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.197.07:59:59.86#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.197.07:59:59.86#ibcon#ireg 17 cls_cnt 0 2006.197.07:59:59.86#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.197.07:59:59.86#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.197.07:59:59.86#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.197.07:59:59.86#ibcon#enter wrdev, iclass 7, count 0 2006.197.07:59:59.86#ibcon#first serial, iclass 7, count 0 2006.197.07:59:59.86#ibcon#enter sib2, iclass 7, count 0 2006.197.07:59:59.86#ibcon#flushed, iclass 7, count 0 2006.197.07:59:59.86#ibcon#about to write, iclass 7, count 0 2006.197.07:59:59.86#ibcon#wrote, iclass 7, count 0 2006.197.07:59:59.86#ibcon#about to read 3, iclass 7, count 0 2006.197.07:59:59.88#ibcon#read 3, iclass 7, count 0 2006.197.07:59:59.88#ibcon#about to read 4, iclass 7, count 0 2006.197.07:59:59.88#ibcon#read 4, iclass 7, count 0 2006.197.07:59:59.88#ibcon#about to read 5, iclass 7, count 0 2006.197.07:59:59.88#ibcon#read 5, iclass 7, count 0 2006.197.07:59:59.88#ibcon#about to read 6, iclass 7, count 0 2006.197.07:59:59.88#ibcon#read 6, iclass 7, count 0 2006.197.07:59:59.88#ibcon#end of sib2, iclass 7, count 0 2006.197.07:59:59.88#ibcon#*mode == 0, iclass 7, count 0 2006.197.07:59:59.88#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.197.07:59:59.88#ibcon#[26=FRQ=08,852.99\r\n] 2006.197.07:59:59.88#ibcon#*before write, iclass 7, count 0 2006.197.07:59:59.88#ibcon#enter sib2, iclass 7, count 0 2006.197.07:59:59.88#ibcon#flushed, iclass 7, count 0 2006.197.07:59:59.88#ibcon#about to write, iclass 7, count 0 2006.197.07:59:59.88#ibcon#wrote, iclass 7, count 0 2006.197.07:59:59.88#ibcon#about to read 3, iclass 7, count 0 2006.197.07:59:59.92#ibcon#read 3, iclass 7, count 0 2006.197.07:59:59.92#ibcon#about to read 4, iclass 7, count 0 2006.197.07:59:59.92#ibcon#read 4, iclass 7, count 0 2006.197.07:59:59.92#ibcon#about to read 5, iclass 7, count 0 2006.197.07:59:59.92#ibcon#read 5, iclass 7, count 0 2006.197.07:59:59.92#ibcon#about to read 6, iclass 7, count 0 2006.197.07:59:59.92#ibcon#read 6, iclass 7, count 0 2006.197.07:59:59.92#ibcon#end of sib2, iclass 7, count 0 2006.197.07:59:59.92#ibcon#*after write, iclass 7, count 0 2006.197.07:59:59.92#ibcon#*before return 0, iclass 7, count 0 2006.197.07:59:59.92#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.197.07:59:59.92#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.197.07:59:59.92#ibcon#about to clear, iclass 7 cls_cnt 0 2006.197.07:59:59.92#ibcon#cleared, iclass 7 cls_cnt 0 2006.197.07:59:59.92$vc4f8/va=8,7 2006.197.07:59:59.92#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.197.07:59:59.92#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.197.07:59:59.92#ibcon#ireg 11 cls_cnt 2 2006.197.07:59:59.92#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.197.07:59:59.98#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.197.07:59:59.98#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.197.07:59:59.98#ibcon#enter wrdev, iclass 11, count 2 2006.197.07:59:59.98#ibcon#first serial, iclass 11, count 2 2006.197.07:59:59.98#ibcon#enter sib2, iclass 11, count 2 2006.197.07:59:59.98#ibcon#flushed, iclass 11, count 2 2006.197.07:59:59.98#ibcon#about to write, iclass 11, count 2 2006.197.07:59:59.98#ibcon#wrote, iclass 11, count 2 2006.197.07:59:59.98#ibcon#about to read 3, iclass 11, count 2 2006.197.08:00:00.00#ibcon#read 3, iclass 11, count 2 2006.197.08:00:00.00#ibcon#about to read 4, iclass 11, count 2 2006.197.08:00:00.00#ibcon#read 4, iclass 11, count 2 2006.197.08:00:00.00#ibcon#about to read 5, iclass 11, count 2 2006.197.08:00:00.00#ibcon#read 5, iclass 11, count 2 2006.197.08:00:00.00#ibcon#about to read 6, iclass 11, count 2 2006.197.08:00:00.00#ibcon#read 6, iclass 11, count 2 2006.197.08:00:00.00#ibcon#end of sib2, iclass 11, count 2 2006.197.08:00:00.00#ibcon#*mode == 0, iclass 11, count 2 2006.197.08:00:00.00#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.197.08:00:00.00#ibcon#[25=AT08-07\r\n] 2006.197.08:00:00.00#ibcon#*before write, iclass 11, count 2 2006.197.08:00:00.00#ibcon#enter sib2, iclass 11, count 2 2006.197.08:00:00.00#ibcon#flushed, iclass 11, count 2 2006.197.08:00:00.00#ibcon#about to write, iclass 11, count 2 2006.197.08:00:00.00#ibcon#wrote, iclass 11, count 2 2006.197.08:00:00.00#ibcon#about to read 3, iclass 11, count 2 2006.197.08:00:00.03#ibcon#read 3, iclass 11, count 2 2006.197.08:00:00.03#ibcon#about to read 4, iclass 11, count 2 2006.197.08:00:00.03#ibcon#read 4, iclass 11, count 2 2006.197.08:00:00.03#ibcon#about to read 5, iclass 11, count 2 2006.197.08:00:00.03#ibcon#read 5, iclass 11, count 2 2006.197.08:00:00.03#ibcon#about to read 6, iclass 11, count 2 2006.197.08:00:00.03#ibcon#read 6, iclass 11, count 2 2006.197.08:00:00.03#ibcon#end of sib2, iclass 11, count 2 2006.197.08:00:00.03#ibcon#*after write, iclass 11, count 2 2006.197.08:00:00.03#ibcon#*before return 0, iclass 11, count 2 2006.197.08:00:00.03#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.197.08:00:00.03#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.197.08:00:00.03#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.197.08:00:00.03#ibcon#ireg 7 cls_cnt 0 2006.197.08:00:00.03#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.197.08:00:00.15#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.197.08:00:00.15#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.197.08:00:00.15#ibcon#enter wrdev, iclass 11, count 0 2006.197.08:00:00.15#ibcon#first serial, iclass 11, count 0 2006.197.08:00:00.15#ibcon#enter sib2, iclass 11, count 0 2006.197.08:00:00.15#ibcon#flushed, iclass 11, count 0 2006.197.08:00:00.15#ibcon#about to write, iclass 11, count 0 2006.197.08:00:00.15#ibcon#wrote, iclass 11, count 0 2006.197.08:00:00.15#ibcon#about to read 3, iclass 11, count 0 2006.197.08:00:00.17#ibcon#read 3, iclass 11, count 0 2006.197.08:00:00.17#ibcon#about to read 4, iclass 11, count 0 2006.197.08:00:00.17#ibcon#read 4, iclass 11, count 0 2006.197.08:00:00.17#ibcon#about to read 5, iclass 11, count 0 2006.197.08:00:00.17#ibcon#read 5, iclass 11, count 0 2006.197.08:00:00.17#ibcon#about to read 6, iclass 11, count 0 2006.197.08:00:00.17#ibcon#read 6, iclass 11, count 0 2006.197.08:00:00.17#ibcon#end of sib2, iclass 11, count 0 2006.197.08:00:00.17#ibcon#*mode == 0, iclass 11, count 0 2006.197.08:00:00.17#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.197.08:00:00.17#ibcon#[25=USB\r\n] 2006.197.08:00:00.17#ibcon#*before write, iclass 11, count 0 2006.197.08:00:00.17#ibcon#enter sib2, iclass 11, count 0 2006.197.08:00:00.17#ibcon#flushed, iclass 11, count 0 2006.197.08:00:00.17#ibcon#about to write, iclass 11, count 0 2006.197.08:00:00.17#ibcon#wrote, iclass 11, count 0 2006.197.08:00:00.17#ibcon#about to read 3, iclass 11, count 0 2006.197.08:00:00.20#ibcon#read 3, iclass 11, count 0 2006.197.08:00:00.20#ibcon#about to read 4, iclass 11, count 0 2006.197.08:00:00.20#ibcon#read 4, iclass 11, count 0 2006.197.08:00:00.20#ibcon#about to read 5, iclass 11, count 0 2006.197.08:00:00.20#ibcon#read 5, iclass 11, count 0 2006.197.08:00:00.20#ibcon#about to read 6, iclass 11, count 0 2006.197.08:00:00.20#ibcon#read 6, iclass 11, count 0 2006.197.08:00:00.20#ibcon#end of sib2, iclass 11, count 0 2006.197.08:00:00.20#ibcon#*after write, iclass 11, count 0 2006.197.08:00:00.20#ibcon#*before return 0, iclass 11, count 0 2006.197.08:00:00.20#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.197.08:00:00.20#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.197.08:00:00.20#ibcon#about to clear, iclass 11 cls_cnt 0 2006.197.08:00:00.20#ibcon#cleared, iclass 11 cls_cnt 0 2006.197.08:00:00.20$vc4f8/vblo=1,632.99 2006.197.08:00:00.20#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.197.08:00:00.20#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.197.08:00:00.20#ibcon#ireg 17 cls_cnt 0 2006.197.08:00:00.20#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.197.08:00:00.20#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.197.08:00:00.20#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.197.08:00:00.20#ibcon#enter wrdev, iclass 13, count 0 2006.197.08:00:00.20#ibcon#first serial, iclass 13, count 0 2006.197.08:00:00.20#ibcon#enter sib2, iclass 13, count 0 2006.197.08:00:00.20#ibcon#flushed, iclass 13, count 0 2006.197.08:00:00.20#ibcon#about to write, iclass 13, count 0 2006.197.08:00:00.20#ibcon#wrote, iclass 13, count 0 2006.197.08:00:00.20#ibcon#about to read 3, iclass 13, count 0 2006.197.08:00:00.22#ibcon#read 3, iclass 13, count 0 2006.197.08:00:00.22#ibcon#about to read 4, iclass 13, count 0 2006.197.08:00:00.22#ibcon#read 4, iclass 13, count 0 2006.197.08:00:00.22#ibcon#about to read 5, iclass 13, count 0 2006.197.08:00:00.22#ibcon#read 5, iclass 13, count 0 2006.197.08:00:00.22#ibcon#about to read 6, iclass 13, count 0 2006.197.08:00:00.22#ibcon#read 6, iclass 13, count 0 2006.197.08:00:00.22#ibcon#end of sib2, iclass 13, count 0 2006.197.08:00:00.22#ibcon#*mode == 0, iclass 13, count 0 2006.197.08:00:00.22#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.197.08:00:00.22#ibcon#[28=FRQ=01,632.99\r\n] 2006.197.08:00:00.22#ibcon#*before write, iclass 13, count 0 2006.197.08:00:00.22#ibcon#enter sib2, iclass 13, count 0 2006.197.08:00:00.22#ibcon#flushed, iclass 13, count 0 2006.197.08:00:00.22#ibcon#about to write, iclass 13, count 0 2006.197.08:00:00.22#ibcon#wrote, iclass 13, count 0 2006.197.08:00:00.22#ibcon#about to read 3, iclass 13, count 0 2006.197.08:00:00.26#ibcon#read 3, iclass 13, count 0 2006.197.08:00:00.26#ibcon#about to read 4, iclass 13, count 0 2006.197.08:00:00.26#ibcon#read 4, iclass 13, count 0 2006.197.08:00:00.26#ibcon#about to read 5, iclass 13, count 0 2006.197.08:00:00.26#ibcon#read 5, iclass 13, count 0 2006.197.08:00:00.26#ibcon#about to read 6, iclass 13, count 0 2006.197.08:00:00.26#ibcon#read 6, iclass 13, count 0 2006.197.08:00:00.26#ibcon#end of sib2, iclass 13, count 0 2006.197.08:00:00.26#ibcon#*after write, iclass 13, count 0 2006.197.08:00:00.26#ibcon#*before return 0, iclass 13, count 0 2006.197.08:00:00.26#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.197.08:00:00.26#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.197.08:00:00.26#ibcon#about to clear, iclass 13 cls_cnt 0 2006.197.08:00:00.26#ibcon#cleared, iclass 13 cls_cnt 0 2006.197.08:00:00.26$vc4f8/vb=1,4 2006.197.08:00:00.26#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.197.08:00:00.26#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.197.08:00:00.26#ibcon#ireg 11 cls_cnt 2 2006.197.08:00:00.26#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.197.08:00:00.26#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.197.08:00:00.26#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.197.08:00:00.26#ibcon#enter wrdev, iclass 15, count 2 2006.197.08:00:00.26#ibcon#first serial, iclass 15, count 2 2006.197.08:00:00.26#ibcon#enter sib2, iclass 15, count 2 2006.197.08:00:00.26#ibcon#flushed, iclass 15, count 2 2006.197.08:00:00.26#ibcon#about to write, iclass 15, count 2 2006.197.08:00:00.26#ibcon#wrote, iclass 15, count 2 2006.197.08:00:00.26#ibcon#about to read 3, iclass 15, count 2 2006.197.08:00:00.28#ibcon#read 3, iclass 15, count 2 2006.197.08:00:00.28#ibcon#about to read 4, iclass 15, count 2 2006.197.08:00:00.28#ibcon#read 4, iclass 15, count 2 2006.197.08:00:00.28#ibcon#about to read 5, iclass 15, count 2 2006.197.08:00:00.28#ibcon#read 5, iclass 15, count 2 2006.197.08:00:00.28#ibcon#about to read 6, iclass 15, count 2 2006.197.08:00:00.28#ibcon#read 6, iclass 15, count 2 2006.197.08:00:00.28#ibcon#end of sib2, iclass 15, count 2 2006.197.08:00:00.28#ibcon#*mode == 0, iclass 15, count 2 2006.197.08:00:00.28#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.197.08:00:00.28#ibcon#[27=AT01-04\r\n] 2006.197.08:00:00.28#ibcon#*before write, iclass 15, count 2 2006.197.08:00:00.28#ibcon#enter sib2, iclass 15, count 2 2006.197.08:00:00.28#ibcon#flushed, iclass 15, count 2 2006.197.08:00:00.28#ibcon#about to write, iclass 15, count 2 2006.197.08:00:00.28#ibcon#wrote, iclass 15, count 2 2006.197.08:00:00.28#ibcon#about to read 3, iclass 15, count 2 2006.197.08:00:00.31#ibcon#read 3, iclass 15, count 2 2006.197.08:00:00.31#ibcon#about to read 4, iclass 15, count 2 2006.197.08:00:00.31#ibcon#read 4, iclass 15, count 2 2006.197.08:00:00.31#ibcon#about to read 5, iclass 15, count 2 2006.197.08:00:00.31#ibcon#read 5, iclass 15, count 2 2006.197.08:00:00.31#ibcon#about to read 6, iclass 15, count 2 2006.197.08:00:00.31#ibcon#read 6, iclass 15, count 2 2006.197.08:00:00.31#ibcon#end of sib2, iclass 15, count 2 2006.197.08:00:00.31#ibcon#*after write, iclass 15, count 2 2006.197.08:00:00.31#ibcon#*before return 0, iclass 15, count 2 2006.197.08:00:00.31#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.197.08:00:00.31#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.197.08:00:00.31#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.197.08:00:00.31#ibcon#ireg 7 cls_cnt 0 2006.197.08:00:00.31#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.197.08:00:00.43#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.197.08:00:00.43#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.197.08:00:00.43#ibcon#enter wrdev, iclass 15, count 0 2006.197.08:00:00.43#ibcon#first serial, iclass 15, count 0 2006.197.08:00:00.43#ibcon#enter sib2, iclass 15, count 0 2006.197.08:00:00.43#ibcon#flushed, iclass 15, count 0 2006.197.08:00:00.43#ibcon#about to write, iclass 15, count 0 2006.197.08:00:00.43#ibcon#wrote, iclass 15, count 0 2006.197.08:00:00.43#ibcon#about to read 3, iclass 15, count 0 2006.197.08:00:00.45#ibcon#read 3, iclass 15, count 0 2006.197.08:00:00.45#ibcon#about to read 4, iclass 15, count 0 2006.197.08:00:00.45#ibcon#read 4, iclass 15, count 0 2006.197.08:00:00.45#ibcon#about to read 5, iclass 15, count 0 2006.197.08:00:00.45#ibcon#read 5, iclass 15, count 0 2006.197.08:00:00.45#ibcon#about to read 6, iclass 15, count 0 2006.197.08:00:00.45#ibcon#read 6, iclass 15, count 0 2006.197.08:00:00.45#ibcon#end of sib2, iclass 15, count 0 2006.197.08:00:00.45#ibcon#*mode == 0, iclass 15, count 0 2006.197.08:00:00.45#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.197.08:00:00.45#ibcon#[27=USB\r\n] 2006.197.08:00:00.45#ibcon#*before write, iclass 15, count 0 2006.197.08:00:00.45#ibcon#enter sib2, iclass 15, count 0 2006.197.08:00:00.45#ibcon#flushed, iclass 15, count 0 2006.197.08:00:00.45#ibcon#about to write, iclass 15, count 0 2006.197.08:00:00.45#ibcon#wrote, iclass 15, count 0 2006.197.08:00:00.45#ibcon#about to read 3, iclass 15, count 0 2006.197.08:00:00.48#ibcon#read 3, iclass 15, count 0 2006.197.08:00:00.48#ibcon#about to read 4, iclass 15, count 0 2006.197.08:00:00.48#ibcon#read 4, iclass 15, count 0 2006.197.08:00:00.48#ibcon#about to read 5, iclass 15, count 0 2006.197.08:00:00.48#ibcon#read 5, iclass 15, count 0 2006.197.08:00:00.48#ibcon#about to read 6, iclass 15, count 0 2006.197.08:00:00.48#ibcon#read 6, iclass 15, count 0 2006.197.08:00:00.48#ibcon#end of sib2, iclass 15, count 0 2006.197.08:00:00.48#ibcon#*after write, iclass 15, count 0 2006.197.08:00:00.48#ibcon#*before return 0, iclass 15, count 0 2006.197.08:00:00.48#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.197.08:00:00.48#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.197.08:00:00.48#ibcon#about to clear, iclass 15 cls_cnt 0 2006.197.08:00:00.48#ibcon#cleared, iclass 15 cls_cnt 0 2006.197.08:00:00.48$vc4f8/vblo=2,640.99 2006.197.08:00:00.48#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.197.08:00:00.48#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.197.08:00:00.48#ibcon#ireg 17 cls_cnt 0 2006.197.08:00:00.48#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.197.08:00:00.48#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.197.08:00:00.48#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.197.08:00:00.48#ibcon#enter wrdev, iclass 17, count 0 2006.197.08:00:00.48#ibcon#first serial, iclass 17, count 0 2006.197.08:00:00.48#ibcon#enter sib2, iclass 17, count 0 2006.197.08:00:00.48#ibcon#flushed, iclass 17, count 0 2006.197.08:00:00.48#ibcon#about to write, iclass 17, count 0 2006.197.08:00:00.48#ibcon#wrote, iclass 17, count 0 2006.197.08:00:00.48#ibcon#about to read 3, iclass 17, count 0 2006.197.08:00:00.50#ibcon#read 3, iclass 17, count 0 2006.197.08:00:00.50#ibcon#about to read 4, iclass 17, count 0 2006.197.08:00:00.50#ibcon#read 4, iclass 17, count 0 2006.197.08:00:00.50#ibcon#about to read 5, iclass 17, count 0 2006.197.08:00:00.50#ibcon#read 5, iclass 17, count 0 2006.197.08:00:00.50#ibcon#about to read 6, iclass 17, count 0 2006.197.08:00:00.50#ibcon#read 6, iclass 17, count 0 2006.197.08:00:00.50#ibcon#end of sib2, iclass 17, count 0 2006.197.08:00:00.50#ibcon#*mode == 0, iclass 17, count 0 2006.197.08:00:00.50#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.197.08:00:00.50#ibcon#[28=FRQ=02,640.99\r\n] 2006.197.08:00:00.50#ibcon#*before write, iclass 17, count 0 2006.197.08:00:00.50#ibcon#enter sib2, iclass 17, count 0 2006.197.08:00:00.50#ibcon#flushed, iclass 17, count 0 2006.197.08:00:00.50#ibcon#about to write, iclass 17, count 0 2006.197.08:00:00.50#ibcon#wrote, iclass 17, count 0 2006.197.08:00:00.50#ibcon#about to read 3, iclass 17, count 0 2006.197.08:00:00.54#ibcon#read 3, iclass 17, count 0 2006.197.08:00:00.54#ibcon#about to read 4, iclass 17, count 0 2006.197.08:00:00.54#ibcon#read 4, iclass 17, count 0 2006.197.08:00:00.54#ibcon#about to read 5, iclass 17, count 0 2006.197.08:00:00.54#ibcon#read 5, iclass 17, count 0 2006.197.08:00:00.54#ibcon#about to read 6, iclass 17, count 0 2006.197.08:00:00.54#ibcon#read 6, iclass 17, count 0 2006.197.08:00:00.54#ibcon#end of sib2, iclass 17, count 0 2006.197.08:00:00.54#ibcon#*after write, iclass 17, count 0 2006.197.08:00:00.54#ibcon#*before return 0, iclass 17, count 0 2006.197.08:00:00.54#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.197.08:00:00.54#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.197.08:00:00.54#ibcon#about to clear, iclass 17 cls_cnt 0 2006.197.08:00:00.54#ibcon#cleared, iclass 17 cls_cnt 0 2006.197.08:00:00.54$vc4f8/vb=2,4 2006.197.08:00:00.54#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.197.08:00:00.54#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.197.08:00:00.54#ibcon#ireg 11 cls_cnt 2 2006.197.08:00:00.54#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.197.08:00:00.60#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.197.08:00:00.60#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.197.08:00:00.60#ibcon#enter wrdev, iclass 19, count 2 2006.197.08:00:00.60#ibcon#first serial, iclass 19, count 2 2006.197.08:00:00.60#ibcon#enter sib2, iclass 19, count 2 2006.197.08:00:00.60#ibcon#flushed, iclass 19, count 2 2006.197.08:00:00.60#ibcon#about to write, iclass 19, count 2 2006.197.08:00:00.60#ibcon#wrote, iclass 19, count 2 2006.197.08:00:00.60#ibcon#about to read 3, iclass 19, count 2 2006.197.08:00:00.62#ibcon#read 3, iclass 19, count 2 2006.197.08:00:00.62#ibcon#about to read 4, iclass 19, count 2 2006.197.08:00:00.62#ibcon#read 4, iclass 19, count 2 2006.197.08:00:00.62#ibcon#about to read 5, iclass 19, count 2 2006.197.08:00:00.62#ibcon#read 5, iclass 19, count 2 2006.197.08:00:00.62#ibcon#about to read 6, iclass 19, count 2 2006.197.08:00:00.62#ibcon#read 6, iclass 19, count 2 2006.197.08:00:00.62#ibcon#end of sib2, iclass 19, count 2 2006.197.08:00:00.62#ibcon#*mode == 0, iclass 19, count 2 2006.197.08:00:00.62#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.197.08:00:00.62#ibcon#[27=AT02-04\r\n] 2006.197.08:00:00.62#ibcon#*before write, iclass 19, count 2 2006.197.08:00:00.62#ibcon#enter sib2, iclass 19, count 2 2006.197.08:00:00.62#ibcon#flushed, iclass 19, count 2 2006.197.08:00:00.62#ibcon#about to write, iclass 19, count 2 2006.197.08:00:00.62#ibcon#wrote, iclass 19, count 2 2006.197.08:00:00.62#ibcon#about to read 3, iclass 19, count 2 2006.197.08:00:00.65#ibcon#read 3, iclass 19, count 2 2006.197.08:00:00.65#ibcon#about to read 4, iclass 19, count 2 2006.197.08:00:00.65#ibcon#read 4, iclass 19, count 2 2006.197.08:00:00.65#ibcon#about to read 5, iclass 19, count 2 2006.197.08:00:00.65#ibcon#read 5, iclass 19, count 2 2006.197.08:00:00.65#ibcon#about to read 6, iclass 19, count 2 2006.197.08:00:00.65#ibcon#read 6, iclass 19, count 2 2006.197.08:00:00.65#ibcon#end of sib2, iclass 19, count 2 2006.197.08:00:00.65#ibcon#*after write, iclass 19, count 2 2006.197.08:00:00.65#ibcon#*before return 0, iclass 19, count 2 2006.197.08:00:00.65#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.197.08:00:00.65#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.197.08:00:00.65#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.197.08:00:00.65#ibcon#ireg 7 cls_cnt 0 2006.197.08:00:00.65#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.197.08:00:00.77#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.197.08:00:00.77#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.197.08:00:00.77#ibcon#enter wrdev, iclass 19, count 0 2006.197.08:00:00.77#ibcon#first serial, iclass 19, count 0 2006.197.08:00:00.77#ibcon#enter sib2, iclass 19, count 0 2006.197.08:00:00.77#ibcon#flushed, iclass 19, count 0 2006.197.08:00:00.77#ibcon#about to write, iclass 19, count 0 2006.197.08:00:00.77#ibcon#wrote, iclass 19, count 0 2006.197.08:00:00.77#ibcon#about to read 3, iclass 19, count 0 2006.197.08:00:00.79#ibcon#read 3, iclass 19, count 0 2006.197.08:00:00.79#ibcon#about to read 4, iclass 19, count 0 2006.197.08:00:00.79#ibcon#read 4, iclass 19, count 0 2006.197.08:00:00.79#ibcon#about to read 5, iclass 19, count 0 2006.197.08:00:00.79#ibcon#read 5, iclass 19, count 0 2006.197.08:00:00.79#ibcon#about to read 6, iclass 19, count 0 2006.197.08:00:00.79#ibcon#read 6, iclass 19, count 0 2006.197.08:00:00.79#ibcon#end of sib2, iclass 19, count 0 2006.197.08:00:00.79#ibcon#*mode == 0, iclass 19, count 0 2006.197.08:00:00.79#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.197.08:00:00.79#ibcon#[27=USB\r\n] 2006.197.08:00:00.79#ibcon#*before write, iclass 19, count 0 2006.197.08:00:00.79#ibcon#enter sib2, iclass 19, count 0 2006.197.08:00:00.79#ibcon#flushed, iclass 19, count 0 2006.197.08:00:00.79#ibcon#about to write, iclass 19, count 0 2006.197.08:00:00.79#ibcon#wrote, iclass 19, count 0 2006.197.08:00:00.79#ibcon#about to read 3, iclass 19, count 0 2006.197.08:00:00.82#ibcon#read 3, iclass 19, count 0 2006.197.08:00:00.82#ibcon#about to read 4, iclass 19, count 0 2006.197.08:00:00.82#ibcon#read 4, iclass 19, count 0 2006.197.08:00:00.82#ibcon#about to read 5, iclass 19, count 0 2006.197.08:00:00.82#ibcon#read 5, iclass 19, count 0 2006.197.08:00:00.82#ibcon#about to read 6, iclass 19, count 0 2006.197.08:00:00.82#ibcon#read 6, iclass 19, count 0 2006.197.08:00:00.82#ibcon#end of sib2, iclass 19, count 0 2006.197.08:00:00.82#ibcon#*after write, iclass 19, count 0 2006.197.08:00:00.82#ibcon#*before return 0, iclass 19, count 0 2006.197.08:00:00.82#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.197.08:00:00.82#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.197.08:00:00.82#ibcon#about to clear, iclass 19 cls_cnt 0 2006.197.08:00:00.82#ibcon#cleared, iclass 19 cls_cnt 0 2006.197.08:00:00.82$vc4f8/vblo=3,656.99 2006.197.08:00:00.82#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.197.08:00:00.82#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.197.08:00:00.82#ibcon#ireg 17 cls_cnt 0 2006.197.08:00:00.82#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.197.08:00:00.82#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.197.08:00:00.82#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.197.08:00:00.82#ibcon#enter wrdev, iclass 21, count 0 2006.197.08:00:00.82#ibcon#first serial, iclass 21, count 0 2006.197.08:00:00.82#ibcon#enter sib2, iclass 21, count 0 2006.197.08:00:00.82#ibcon#flushed, iclass 21, count 0 2006.197.08:00:00.82#ibcon#about to write, iclass 21, count 0 2006.197.08:00:00.82#ibcon#wrote, iclass 21, count 0 2006.197.08:00:00.82#ibcon#about to read 3, iclass 21, count 0 2006.197.08:00:00.84#ibcon#read 3, iclass 21, count 0 2006.197.08:00:00.84#ibcon#about to read 4, iclass 21, count 0 2006.197.08:00:00.84#ibcon#read 4, iclass 21, count 0 2006.197.08:00:00.84#ibcon#about to read 5, iclass 21, count 0 2006.197.08:00:00.84#ibcon#read 5, iclass 21, count 0 2006.197.08:00:00.84#ibcon#about to read 6, iclass 21, count 0 2006.197.08:00:00.84#ibcon#read 6, iclass 21, count 0 2006.197.08:00:00.84#ibcon#end of sib2, iclass 21, count 0 2006.197.08:00:00.84#ibcon#*mode == 0, iclass 21, count 0 2006.197.08:00:00.84#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.197.08:00:00.84#ibcon#[28=FRQ=03,656.99\r\n] 2006.197.08:00:00.84#ibcon#*before write, iclass 21, count 0 2006.197.08:00:00.84#ibcon#enter sib2, iclass 21, count 0 2006.197.08:00:00.84#ibcon#flushed, iclass 21, count 0 2006.197.08:00:00.84#ibcon#about to write, iclass 21, count 0 2006.197.08:00:00.84#ibcon#wrote, iclass 21, count 0 2006.197.08:00:00.84#ibcon#about to read 3, iclass 21, count 0 2006.197.08:00:00.88#ibcon#read 3, iclass 21, count 0 2006.197.08:00:00.88#ibcon#about to read 4, iclass 21, count 0 2006.197.08:00:00.88#ibcon#read 4, iclass 21, count 0 2006.197.08:00:00.88#ibcon#about to read 5, iclass 21, count 0 2006.197.08:00:00.88#ibcon#read 5, iclass 21, count 0 2006.197.08:00:00.88#ibcon#about to read 6, iclass 21, count 0 2006.197.08:00:00.88#ibcon#read 6, iclass 21, count 0 2006.197.08:00:00.88#ibcon#end of sib2, iclass 21, count 0 2006.197.08:00:00.88#ibcon#*after write, iclass 21, count 0 2006.197.08:00:00.88#ibcon#*before return 0, iclass 21, count 0 2006.197.08:00:00.88#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.197.08:00:00.88#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.197.08:00:00.88#ibcon#about to clear, iclass 21 cls_cnt 0 2006.197.08:00:00.88#ibcon#cleared, iclass 21 cls_cnt 0 2006.197.08:00:00.88$vc4f8/vb=3,4 2006.197.08:00:00.88#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.197.08:00:00.88#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.197.08:00:00.88#ibcon#ireg 11 cls_cnt 2 2006.197.08:00:00.88#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.197.08:00:00.94#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.197.08:00:00.94#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.197.08:00:00.94#ibcon#enter wrdev, iclass 23, count 2 2006.197.08:00:00.94#ibcon#first serial, iclass 23, count 2 2006.197.08:00:00.94#ibcon#enter sib2, iclass 23, count 2 2006.197.08:00:00.94#ibcon#flushed, iclass 23, count 2 2006.197.08:00:00.94#ibcon#about to write, iclass 23, count 2 2006.197.08:00:00.94#ibcon#wrote, iclass 23, count 2 2006.197.08:00:00.94#ibcon#about to read 3, iclass 23, count 2 2006.197.08:00:00.96#ibcon#read 3, iclass 23, count 2 2006.197.08:00:00.96#ibcon#about to read 4, iclass 23, count 2 2006.197.08:00:00.96#ibcon#read 4, iclass 23, count 2 2006.197.08:00:00.96#ibcon#about to read 5, iclass 23, count 2 2006.197.08:00:00.96#ibcon#read 5, iclass 23, count 2 2006.197.08:00:00.96#ibcon#about to read 6, iclass 23, count 2 2006.197.08:00:00.96#ibcon#read 6, iclass 23, count 2 2006.197.08:00:00.96#ibcon#end of sib2, iclass 23, count 2 2006.197.08:00:00.96#ibcon#*mode == 0, iclass 23, count 2 2006.197.08:00:00.96#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.197.08:00:00.96#ibcon#[27=AT03-04\r\n] 2006.197.08:00:00.96#ibcon#*before write, iclass 23, count 2 2006.197.08:00:00.96#ibcon#enter sib2, iclass 23, count 2 2006.197.08:00:00.96#ibcon#flushed, iclass 23, count 2 2006.197.08:00:00.96#ibcon#about to write, iclass 23, count 2 2006.197.08:00:00.96#ibcon#wrote, iclass 23, count 2 2006.197.08:00:00.96#ibcon#about to read 3, iclass 23, count 2 2006.197.08:00:00.99#ibcon#read 3, iclass 23, count 2 2006.197.08:00:00.99#ibcon#about to read 4, iclass 23, count 2 2006.197.08:00:00.99#ibcon#read 4, iclass 23, count 2 2006.197.08:00:00.99#ibcon#about to read 5, iclass 23, count 2 2006.197.08:00:00.99#ibcon#read 5, iclass 23, count 2 2006.197.08:00:00.99#ibcon#about to read 6, iclass 23, count 2 2006.197.08:00:00.99#ibcon#read 6, iclass 23, count 2 2006.197.08:00:00.99#ibcon#end of sib2, iclass 23, count 2 2006.197.08:00:00.99#ibcon#*after write, iclass 23, count 2 2006.197.08:00:00.99#ibcon#*before return 0, iclass 23, count 2 2006.197.08:00:00.99#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.197.08:00:00.99#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.197.08:00:00.99#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.197.08:00:00.99#ibcon#ireg 7 cls_cnt 0 2006.197.08:00:00.99#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.197.08:00:01.11#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.197.08:00:01.11#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.197.08:00:01.11#ibcon#enter wrdev, iclass 23, count 0 2006.197.08:00:01.11#ibcon#first serial, iclass 23, count 0 2006.197.08:00:01.11#ibcon#enter sib2, iclass 23, count 0 2006.197.08:00:01.11#ibcon#flushed, iclass 23, count 0 2006.197.08:00:01.11#ibcon#about to write, iclass 23, count 0 2006.197.08:00:01.11#ibcon#wrote, iclass 23, count 0 2006.197.08:00:01.11#ibcon#about to read 3, iclass 23, count 0 2006.197.08:00:01.13#ibcon#read 3, iclass 23, count 0 2006.197.08:00:01.13#ibcon#about to read 4, iclass 23, count 0 2006.197.08:00:01.13#ibcon#read 4, iclass 23, count 0 2006.197.08:00:01.13#ibcon#about to read 5, iclass 23, count 0 2006.197.08:00:01.13#ibcon#read 5, iclass 23, count 0 2006.197.08:00:01.13#ibcon#about to read 6, iclass 23, count 0 2006.197.08:00:01.13#ibcon#read 6, iclass 23, count 0 2006.197.08:00:01.13#ibcon#end of sib2, iclass 23, count 0 2006.197.08:00:01.13#ibcon#*mode == 0, iclass 23, count 0 2006.197.08:00:01.13#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.197.08:00:01.13#ibcon#[27=USB\r\n] 2006.197.08:00:01.13#ibcon#*before write, iclass 23, count 0 2006.197.08:00:01.13#ibcon#enter sib2, iclass 23, count 0 2006.197.08:00:01.13#ibcon#flushed, iclass 23, count 0 2006.197.08:00:01.13#ibcon#about to write, iclass 23, count 0 2006.197.08:00:01.13#ibcon#wrote, iclass 23, count 0 2006.197.08:00:01.13#ibcon#about to read 3, iclass 23, count 0 2006.197.08:00:01.16#ibcon#read 3, iclass 23, count 0 2006.197.08:00:01.16#ibcon#about to read 4, iclass 23, count 0 2006.197.08:00:01.16#ibcon#read 4, iclass 23, count 0 2006.197.08:00:01.16#ibcon#about to read 5, iclass 23, count 0 2006.197.08:00:01.16#ibcon#read 5, iclass 23, count 0 2006.197.08:00:01.16#ibcon#about to read 6, iclass 23, count 0 2006.197.08:00:01.16#ibcon#read 6, iclass 23, count 0 2006.197.08:00:01.16#ibcon#end of sib2, iclass 23, count 0 2006.197.08:00:01.16#ibcon#*after write, iclass 23, count 0 2006.197.08:00:01.16#ibcon#*before return 0, iclass 23, count 0 2006.197.08:00:01.16#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.197.08:00:01.16#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.197.08:00:01.16#ibcon#about to clear, iclass 23 cls_cnt 0 2006.197.08:00:01.16#ibcon#cleared, iclass 23 cls_cnt 0 2006.197.08:00:01.16$vc4f8/vblo=4,712.99 2006.197.08:00:01.16#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.197.08:00:01.16#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.197.08:00:01.16#ibcon#ireg 17 cls_cnt 0 2006.197.08:00:01.16#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.197.08:00:01.16#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.197.08:00:01.16#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.197.08:00:01.16#ibcon#enter wrdev, iclass 25, count 0 2006.197.08:00:01.16#ibcon#first serial, iclass 25, count 0 2006.197.08:00:01.16#ibcon#enter sib2, iclass 25, count 0 2006.197.08:00:01.16#ibcon#flushed, iclass 25, count 0 2006.197.08:00:01.16#ibcon#about to write, iclass 25, count 0 2006.197.08:00:01.16#ibcon#wrote, iclass 25, count 0 2006.197.08:00:01.16#ibcon#about to read 3, iclass 25, count 0 2006.197.08:00:01.18#ibcon#read 3, iclass 25, count 0 2006.197.08:00:01.18#ibcon#about to read 4, iclass 25, count 0 2006.197.08:00:01.18#ibcon#read 4, iclass 25, count 0 2006.197.08:00:01.18#ibcon#about to read 5, iclass 25, count 0 2006.197.08:00:01.18#ibcon#read 5, iclass 25, count 0 2006.197.08:00:01.18#ibcon#about to read 6, iclass 25, count 0 2006.197.08:00:01.18#ibcon#read 6, iclass 25, count 0 2006.197.08:00:01.18#ibcon#end of sib2, iclass 25, count 0 2006.197.08:00:01.18#ibcon#*mode == 0, iclass 25, count 0 2006.197.08:00:01.18#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.197.08:00:01.18#ibcon#[28=FRQ=04,712.99\r\n] 2006.197.08:00:01.18#ibcon#*before write, iclass 25, count 0 2006.197.08:00:01.18#ibcon#enter sib2, iclass 25, count 0 2006.197.08:00:01.18#ibcon#flushed, iclass 25, count 0 2006.197.08:00:01.18#ibcon#about to write, iclass 25, count 0 2006.197.08:00:01.18#ibcon#wrote, iclass 25, count 0 2006.197.08:00:01.18#ibcon#about to read 3, iclass 25, count 0 2006.197.08:00:01.22#ibcon#read 3, iclass 25, count 0 2006.197.08:00:01.22#ibcon#about to read 4, iclass 25, count 0 2006.197.08:00:01.22#ibcon#read 4, iclass 25, count 0 2006.197.08:00:01.22#ibcon#about to read 5, iclass 25, count 0 2006.197.08:00:01.22#ibcon#read 5, iclass 25, count 0 2006.197.08:00:01.22#ibcon#about to read 6, iclass 25, count 0 2006.197.08:00:01.22#ibcon#read 6, iclass 25, count 0 2006.197.08:00:01.22#ibcon#end of sib2, iclass 25, count 0 2006.197.08:00:01.22#ibcon#*after write, iclass 25, count 0 2006.197.08:00:01.22#ibcon#*before return 0, iclass 25, count 0 2006.197.08:00:01.22#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.197.08:00:01.22#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.197.08:00:01.22#ibcon#about to clear, iclass 25 cls_cnt 0 2006.197.08:00:01.22#ibcon#cleared, iclass 25 cls_cnt 0 2006.197.08:00:01.22$vc4f8/vb=4,4 2006.197.08:00:01.22#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.197.08:00:01.22#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.197.08:00:01.22#ibcon#ireg 11 cls_cnt 2 2006.197.08:00:01.22#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.197.08:00:01.28#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.197.08:00:01.28#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.197.08:00:01.28#ibcon#enter wrdev, iclass 27, count 2 2006.197.08:00:01.28#ibcon#first serial, iclass 27, count 2 2006.197.08:00:01.28#ibcon#enter sib2, iclass 27, count 2 2006.197.08:00:01.28#ibcon#flushed, iclass 27, count 2 2006.197.08:00:01.28#ibcon#about to write, iclass 27, count 2 2006.197.08:00:01.28#ibcon#wrote, iclass 27, count 2 2006.197.08:00:01.28#ibcon#about to read 3, iclass 27, count 2 2006.197.08:00:01.30#ibcon#read 3, iclass 27, count 2 2006.197.08:00:01.30#ibcon#about to read 4, iclass 27, count 2 2006.197.08:00:01.30#ibcon#read 4, iclass 27, count 2 2006.197.08:00:01.30#ibcon#about to read 5, iclass 27, count 2 2006.197.08:00:01.30#ibcon#read 5, iclass 27, count 2 2006.197.08:00:01.30#ibcon#about to read 6, iclass 27, count 2 2006.197.08:00:01.30#ibcon#read 6, iclass 27, count 2 2006.197.08:00:01.30#ibcon#end of sib2, iclass 27, count 2 2006.197.08:00:01.30#ibcon#*mode == 0, iclass 27, count 2 2006.197.08:00:01.30#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.197.08:00:01.30#ibcon#[27=AT04-04\r\n] 2006.197.08:00:01.30#ibcon#*before write, iclass 27, count 2 2006.197.08:00:01.30#ibcon#enter sib2, iclass 27, count 2 2006.197.08:00:01.30#ibcon#flushed, iclass 27, count 2 2006.197.08:00:01.30#ibcon#about to write, iclass 27, count 2 2006.197.08:00:01.30#ibcon#wrote, iclass 27, count 2 2006.197.08:00:01.30#ibcon#about to read 3, iclass 27, count 2 2006.197.08:00:01.33#ibcon#read 3, iclass 27, count 2 2006.197.08:00:01.33#ibcon#about to read 4, iclass 27, count 2 2006.197.08:00:01.33#ibcon#read 4, iclass 27, count 2 2006.197.08:00:01.33#ibcon#about to read 5, iclass 27, count 2 2006.197.08:00:01.33#ibcon#read 5, iclass 27, count 2 2006.197.08:00:01.33#ibcon#about to read 6, iclass 27, count 2 2006.197.08:00:01.33#ibcon#read 6, iclass 27, count 2 2006.197.08:00:01.33#ibcon#end of sib2, iclass 27, count 2 2006.197.08:00:01.33#ibcon#*after write, iclass 27, count 2 2006.197.08:00:01.33#ibcon#*before return 0, iclass 27, count 2 2006.197.08:00:01.33#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.197.08:00:01.33#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.197.08:00:01.33#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.197.08:00:01.33#ibcon#ireg 7 cls_cnt 0 2006.197.08:00:01.33#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.197.08:00:01.45#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.197.08:00:01.45#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.197.08:00:01.45#ibcon#enter wrdev, iclass 27, count 0 2006.197.08:00:01.45#ibcon#first serial, iclass 27, count 0 2006.197.08:00:01.45#ibcon#enter sib2, iclass 27, count 0 2006.197.08:00:01.45#ibcon#flushed, iclass 27, count 0 2006.197.08:00:01.45#ibcon#about to write, iclass 27, count 0 2006.197.08:00:01.45#ibcon#wrote, iclass 27, count 0 2006.197.08:00:01.45#ibcon#about to read 3, iclass 27, count 0 2006.197.08:00:01.47#ibcon#read 3, iclass 27, count 0 2006.197.08:00:01.47#ibcon#about to read 4, iclass 27, count 0 2006.197.08:00:01.47#ibcon#read 4, iclass 27, count 0 2006.197.08:00:01.47#ibcon#about to read 5, iclass 27, count 0 2006.197.08:00:01.47#ibcon#read 5, iclass 27, count 0 2006.197.08:00:01.47#ibcon#about to read 6, iclass 27, count 0 2006.197.08:00:01.47#ibcon#read 6, iclass 27, count 0 2006.197.08:00:01.47#ibcon#end of sib2, iclass 27, count 0 2006.197.08:00:01.47#ibcon#*mode == 0, iclass 27, count 0 2006.197.08:00:01.47#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.197.08:00:01.47#ibcon#[27=USB\r\n] 2006.197.08:00:01.47#ibcon#*before write, iclass 27, count 0 2006.197.08:00:01.47#ibcon#enter sib2, iclass 27, count 0 2006.197.08:00:01.47#ibcon#flushed, iclass 27, count 0 2006.197.08:00:01.47#ibcon#about to write, iclass 27, count 0 2006.197.08:00:01.47#ibcon#wrote, iclass 27, count 0 2006.197.08:00:01.47#ibcon#about to read 3, iclass 27, count 0 2006.197.08:00:01.50#ibcon#read 3, iclass 27, count 0 2006.197.08:00:01.50#ibcon#about to read 4, iclass 27, count 0 2006.197.08:00:01.50#ibcon#read 4, iclass 27, count 0 2006.197.08:00:01.50#ibcon#about to read 5, iclass 27, count 0 2006.197.08:00:01.50#ibcon#read 5, iclass 27, count 0 2006.197.08:00:01.50#ibcon#about to read 6, iclass 27, count 0 2006.197.08:00:01.50#ibcon#read 6, iclass 27, count 0 2006.197.08:00:01.50#ibcon#end of sib2, iclass 27, count 0 2006.197.08:00:01.50#ibcon#*after write, iclass 27, count 0 2006.197.08:00:01.50#ibcon#*before return 0, iclass 27, count 0 2006.197.08:00:01.50#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.197.08:00:01.50#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.197.08:00:01.50#ibcon#about to clear, iclass 27 cls_cnt 0 2006.197.08:00:01.50#ibcon#cleared, iclass 27 cls_cnt 0 2006.197.08:00:01.50$vc4f8/vblo=5,744.99 2006.197.08:00:01.50#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.197.08:00:01.50#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.197.08:00:01.50#ibcon#ireg 17 cls_cnt 0 2006.197.08:00:01.50#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.197.08:00:01.50#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.197.08:00:01.50#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.197.08:00:01.50#ibcon#enter wrdev, iclass 29, count 0 2006.197.08:00:01.50#ibcon#first serial, iclass 29, count 0 2006.197.08:00:01.50#ibcon#enter sib2, iclass 29, count 0 2006.197.08:00:01.50#ibcon#flushed, iclass 29, count 0 2006.197.08:00:01.50#ibcon#about to write, iclass 29, count 0 2006.197.08:00:01.50#ibcon#wrote, iclass 29, count 0 2006.197.08:00:01.50#ibcon#about to read 3, iclass 29, count 0 2006.197.08:00:01.52#ibcon#read 3, iclass 29, count 0 2006.197.08:00:01.52#ibcon#about to read 4, iclass 29, count 0 2006.197.08:00:01.52#ibcon#read 4, iclass 29, count 0 2006.197.08:00:01.52#ibcon#about to read 5, iclass 29, count 0 2006.197.08:00:01.52#ibcon#read 5, iclass 29, count 0 2006.197.08:00:01.52#ibcon#about to read 6, iclass 29, count 0 2006.197.08:00:01.52#ibcon#read 6, iclass 29, count 0 2006.197.08:00:01.52#ibcon#end of sib2, iclass 29, count 0 2006.197.08:00:01.52#ibcon#*mode == 0, iclass 29, count 0 2006.197.08:00:01.52#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.197.08:00:01.52#ibcon#[28=FRQ=05,744.99\r\n] 2006.197.08:00:01.52#ibcon#*before write, iclass 29, count 0 2006.197.08:00:01.52#ibcon#enter sib2, iclass 29, count 0 2006.197.08:00:01.52#ibcon#flushed, iclass 29, count 0 2006.197.08:00:01.52#ibcon#about to write, iclass 29, count 0 2006.197.08:00:01.52#ibcon#wrote, iclass 29, count 0 2006.197.08:00:01.52#ibcon#about to read 3, iclass 29, count 0 2006.197.08:00:01.56#ibcon#read 3, iclass 29, count 0 2006.197.08:00:01.56#ibcon#about to read 4, iclass 29, count 0 2006.197.08:00:01.56#ibcon#read 4, iclass 29, count 0 2006.197.08:00:01.56#ibcon#about to read 5, iclass 29, count 0 2006.197.08:00:01.56#ibcon#read 5, iclass 29, count 0 2006.197.08:00:01.56#ibcon#about to read 6, iclass 29, count 0 2006.197.08:00:01.56#ibcon#read 6, iclass 29, count 0 2006.197.08:00:01.56#ibcon#end of sib2, iclass 29, count 0 2006.197.08:00:01.56#ibcon#*after write, iclass 29, count 0 2006.197.08:00:01.56#ibcon#*before return 0, iclass 29, count 0 2006.197.08:00:01.56#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.197.08:00:01.56#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.197.08:00:01.56#ibcon#about to clear, iclass 29 cls_cnt 0 2006.197.08:00:01.56#ibcon#cleared, iclass 29 cls_cnt 0 2006.197.08:00:01.56$vc4f8/vb=5,4 2006.197.08:00:01.56#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.197.08:00:01.56#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.197.08:00:01.56#ibcon#ireg 11 cls_cnt 2 2006.197.08:00:01.56#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.197.08:00:01.62#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.197.08:00:01.62#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.197.08:00:01.62#ibcon#enter wrdev, iclass 31, count 2 2006.197.08:00:01.62#ibcon#first serial, iclass 31, count 2 2006.197.08:00:01.62#ibcon#enter sib2, iclass 31, count 2 2006.197.08:00:01.62#ibcon#flushed, iclass 31, count 2 2006.197.08:00:01.62#ibcon#about to write, iclass 31, count 2 2006.197.08:00:01.62#ibcon#wrote, iclass 31, count 2 2006.197.08:00:01.62#ibcon#about to read 3, iclass 31, count 2 2006.197.08:00:01.64#ibcon#read 3, iclass 31, count 2 2006.197.08:00:01.64#ibcon#about to read 4, iclass 31, count 2 2006.197.08:00:01.64#ibcon#read 4, iclass 31, count 2 2006.197.08:00:01.64#ibcon#about to read 5, iclass 31, count 2 2006.197.08:00:01.64#ibcon#read 5, iclass 31, count 2 2006.197.08:00:01.64#ibcon#about to read 6, iclass 31, count 2 2006.197.08:00:01.64#ibcon#read 6, iclass 31, count 2 2006.197.08:00:01.64#ibcon#end of sib2, iclass 31, count 2 2006.197.08:00:01.64#ibcon#*mode == 0, iclass 31, count 2 2006.197.08:00:01.64#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.197.08:00:01.64#ibcon#[27=AT05-04\r\n] 2006.197.08:00:01.64#ibcon#*before write, iclass 31, count 2 2006.197.08:00:01.64#ibcon#enter sib2, iclass 31, count 2 2006.197.08:00:01.64#ibcon#flushed, iclass 31, count 2 2006.197.08:00:01.64#ibcon#about to write, iclass 31, count 2 2006.197.08:00:01.64#ibcon#wrote, iclass 31, count 2 2006.197.08:00:01.64#ibcon#about to read 3, iclass 31, count 2 2006.197.08:00:01.67#ibcon#read 3, iclass 31, count 2 2006.197.08:00:01.67#ibcon#about to read 4, iclass 31, count 2 2006.197.08:00:01.67#ibcon#read 4, iclass 31, count 2 2006.197.08:00:01.67#ibcon#about to read 5, iclass 31, count 2 2006.197.08:00:01.67#ibcon#read 5, iclass 31, count 2 2006.197.08:00:01.67#ibcon#about to read 6, iclass 31, count 2 2006.197.08:00:01.67#ibcon#read 6, iclass 31, count 2 2006.197.08:00:01.67#ibcon#end of sib2, iclass 31, count 2 2006.197.08:00:01.67#ibcon#*after write, iclass 31, count 2 2006.197.08:00:01.67#ibcon#*before return 0, iclass 31, count 2 2006.197.08:00:01.67#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.197.08:00:01.67#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.197.08:00:01.67#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.197.08:00:01.67#ibcon#ireg 7 cls_cnt 0 2006.197.08:00:01.67#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.197.08:00:01.79#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.197.08:00:01.79#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.197.08:00:01.79#ibcon#enter wrdev, iclass 31, count 0 2006.197.08:00:01.79#ibcon#first serial, iclass 31, count 0 2006.197.08:00:01.79#ibcon#enter sib2, iclass 31, count 0 2006.197.08:00:01.79#ibcon#flushed, iclass 31, count 0 2006.197.08:00:01.79#ibcon#about to write, iclass 31, count 0 2006.197.08:00:01.79#ibcon#wrote, iclass 31, count 0 2006.197.08:00:01.79#ibcon#about to read 3, iclass 31, count 0 2006.197.08:00:01.81#ibcon#read 3, iclass 31, count 0 2006.197.08:00:01.81#ibcon#about to read 4, iclass 31, count 0 2006.197.08:00:01.81#ibcon#read 4, iclass 31, count 0 2006.197.08:00:01.81#ibcon#about to read 5, iclass 31, count 0 2006.197.08:00:01.81#ibcon#read 5, iclass 31, count 0 2006.197.08:00:01.81#ibcon#about to read 6, iclass 31, count 0 2006.197.08:00:01.81#ibcon#read 6, iclass 31, count 0 2006.197.08:00:01.81#ibcon#end of sib2, iclass 31, count 0 2006.197.08:00:01.81#ibcon#*mode == 0, iclass 31, count 0 2006.197.08:00:01.81#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.197.08:00:01.81#ibcon#[27=USB\r\n] 2006.197.08:00:01.81#ibcon#*before write, iclass 31, count 0 2006.197.08:00:01.81#ibcon#enter sib2, iclass 31, count 0 2006.197.08:00:01.81#ibcon#flushed, iclass 31, count 0 2006.197.08:00:01.81#ibcon#about to write, iclass 31, count 0 2006.197.08:00:01.81#ibcon#wrote, iclass 31, count 0 2006.197.08:00:01.81#ibcon#about to read 3, iclass 31, count 0 2006.197.08:00:01.84#ibcon#read 3, iclass 31, count 0 2006.197.08:00:01.84#ibcon#about to read 4, iclass 31, count 0 2006.197.08:00:01.84#ibcon#read 4, iclass 31, count 0 2006.197.08:00:01.84#ibcon#about to read 5, iclass 31, count 0 2006.197.08:00:01.84#ibcon#read 5, iclass 31, count 0 2006.197.08:00:01.84#ibcon#about to read 6, iclass 31, count 0 2006.197.08:00:01.84#ibcon#read 6, iclass 31, count 0 2006.197.08:00:01.84#ibcon#end of sib2, iclass 31, count 0 2006.197.08:00:01.84#ibcon#*after write, iclass 31, count 0 2006.197.08:00:01.84#ibcon#*before return 0, iclass 31, count 0 2006.197.08:00:01.84#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.197.08:00:01.84#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.197.08:00:01.84#ibcon#about to clear, iclass 31 cls_cnt 0 2006.197.08:00:01.84#ibcon#cleared, iclass 31 cls_cnt 0 2006.197.08:00:01.84$vc4f8/vblo=6,752.99 2006.197.08:00:01.84#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.197.08:00:01.84#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.197.08:00:01.84#ibcon#ireg 17 cls_cnt 0 2006.197.08:00:01.84#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.197.08:00:01.84#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.197.08:00:01.84#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.197.08:00:01.84#ibcon#enter wrdev, iclass 33, count 0 2006.197.08:00:01.84#ibcon#first serial, iclass 33, count 0 2006.197.08:00:01.84#ibcon#enter sib2, iclass 33, count 0 2006.197.08:00:01.84#ibcon#flushed, iclass 33, count 0 2006.197.08:00:01.84#ibcon#about to write, iclass 33, count 0 2006.197.08:00:01.84#ibcon#wrote, iclass 33, count 0 2006.197.08:00:01.84#ibcon#about to read 3, iclass 33, count 0 2006.197.08:00:01.86#ibcon#read 3, iclass 33, count 0 2006.197.08:00:01.86#ibcon#about to read 4, iclass 33, count 0 2006.197.08:00:01.86#ibcon#read 4, iclass 33, count 0 2006.197.08:00:01.86#ibcon#about to read 5, iclass 33, count 0 2006.197.08:00:01.86#ibcon#read 5, iclass 33, count 0 2006.197.08:00:01.86#ibcon#about to read 6, iclass 33, count 0 2006.197.08:00:01.86#ibcon#read 6, iclass 33, count 0 2006.197.08:00:01.86#ibcon#end of sib2, iclass 33, count 0 2006.197.08:00:01.86#ibcon#*mode == 0, iclass 33, count 0 2006.197.08:00:01.86#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.197.08:00:01.86#ibcon#[28=FRQ=06,752.99\r\n] 2006.197.08:00:01.86#ibcon#*before write, iclass 33, count 0 2006.197.08:00:01.86#ibcon#enter sib2, iclass 33, count 0 2006.197.08:00:01.86#ibcon#flushed, iclass 33, count 0 2006.197.08:00:01.86#ibcon#about to write, iclass 33, count 0 2006.197.08:00:01.86#ibcon#wrote, iclass 33, count 0 2006.197.08:00:01.86#ibcon#about to read 3, iclass 33, count 0 2006.197.08:00:01.90#ibcon#read 3, iclass 33, count 0 2006.197.08:00:01.90#ibcon#about to read 4, iclass 33, count 0 2006.197.08:00:01.90#ibcon#read 4, iclass 33, count 0 2006.197.08:00:01.90#ibcon#about to read 5, iclass 33, count 0 2006.197.08:00:01.90#ibcon#read 5, iclass 33, count 0 2006.197.08:00:01.90#ibcon#about to read 6, iclass 33, count 0 2006.197.08:00:01.90#ibcon#read 6, iclass 33, count 0 2006.197.08:00:01.90#ibcon#end of sib2, iclass 33, count 0 2006.197.08:00:01.90#ibcon#*after write, iclass 33, count 0 2006.197.08:00:01.90#ibcon#*before return 0, iclass 33, count 0 2006.197.08:00:01.90#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.197.08:00:01.90#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.197.08:00:01.90#ibcon#about to clear, iclass 33 cls_cnt 0 2006.197.08:00:01.90#ibcon#cleared, iclass 33 cls_cnt 0 2006.197.08:00:01.90$vc4f8/vb=6,4 2006.197.08:00:01.90#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.197.08:00:01.90#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.197.08:00:01.90#ibcon#ireg 11 cls_cnt 2 2006.197.08:00:01.90#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.197.08:00:01.96#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.197.08:00:01.96#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.197.08:00:01.96#ibcon#enter wrdev, iclass 35, count 2 2006.197.08:00:01.96#ibcon#first serial, iclass 35, count 2 2006.197.08:00:01.96#ibcon#enter sib2, iclass 35, count 2 2006.197.08:00:01.96#ibcon#flushed, iclass 35, count 2 2006.197.08:00:01.96#ibcon#about to write, iclass 35, count 2 2006.197.08:00:01.96#ibcon#wrote, iclass 35, count 2 2006.197.08:00:01.96#ibcon#about to read 3, iclass 35, count 2 2006.197.08:00:01.98#ibcon#read 3, iclass 35, count 2 2006.197.08:00:01.98#ibcon#about to read 4, iclass 35, count 2 2006.197.08:00:01.98#ibcon#read 4, iclass 35, count 2 2006.197.08:00:01.98#ibcon#about to read 5, iclass 35, count 2 2006.197.08:00:01.98#ibcon#read 5, iclass 35, count 2 2006.197.08:00:01.98#ibcon#about to read 6, iclass 35, count 2 2006.197.08:00:01.98#ibcon#read 6, iclass 35, count 2 2006.197.08:00:01.98#ibcon#end of sib2, iclass 35, count 2 2006.197.08:00:01.98#ibcon#*mode == 0, iclass 35, count 2 2006.197.08:00:01.98#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.197.08:00:01.98#ibcon#[27=AT06-04\r\n] 2006.197.08:00:01.98#ibcon#*before write, iclass 35, count 2 2006.197.08:00:01.98#ibcon#enter sib2, iclass 35, count 2 2006.197.08:00:01.98#ibcon#flushed, iclass 35, count 2 2006.197.08:00:01.98#ibcon#about to write, iclass 35, count 2 2006.197.08:00:01.98#ibcon#wrote, iclass 35, count 2 2006.197.08:00:01.98#ibcon#about to read 3, iclass 35, count 2 2006.197.08:00:02.01#ibcon#read 3, iclass 35, count 2 2006.197.08:00:02.01#ibcon#about to read 4, iclass 35, count 2 2006.197.08:00:02.01#ibcon#read 4, iclass 35, count 2 2006.197.08:00:02.01#ibcon#about to read 5, iclass 35, count 2 2006.197.08:00:02.01#ibcon#read 5, iclass 35, count 2 2006.197.08:00:02.01#ibcon#about to read 6, iclass 35, count 2 2006.197.08:00:02.01#ibcon#read 6, iclass 35, count 2 2006.197.08:00:02.01#ibcon#end of sib2, iclass 35, count 2 2006.197.08:00:02.01#ibcon#*after write, iclass 35, count 2 2006.197.08:00:02.01#ibcon#*before return 0, iclass 35, count 2 2006.197.08:00:02.01#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.197.08:00:02.01#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.197.08:00:02.01#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.197.08:00:02.01#ibcon#ireg 7 cls_cnt 0 2006.197.08:00:02.01#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.197.08:00:02.13#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.197.08:00:02.13#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.197.08:00:02.13#ibcon#enter wrdev, iclass 35, count 0 2006.197.08:00:02.13#ibcon#first serial, iclass 35, count 0 2006.197.08:00:02.13#ibcon#enter sib2, iclass 35, count 0 2006.197.08:00:02.13#ibcon#flushed, iclass 35, count 0 2006.197.08:00:02.13#ibcon#about to write, iclass 35, count 0 2006.197.08:00:02.13#ibcon#wrote, iclass 35, count 0 2006.197.08:00:02.13#ibcon#about to read 3, iclass 35, count 0 2006.197.08:00:02.15#ibcon#read 3, iclass 35, count 0 2006.197.08:00:02.15#ibcon#about to read 4, iclass 35, count 0 2006.197.08:00:02.15#ibcon#read 4, iclass 35, count 0 2006.197.08:00:02.15#ibcon#about to read 5, iclass 35, count 0 2006.197.08:00:02.15#ibcon#read 5, iclass 35, count 0 2006.197.08:00:02.15#ibcon#about to read 6, iclass 35, count 0 2006.197.08:00:02.15#ibcon#read 6, iclass 35, count 0 2006.197.08:00:02.15#ibcon#end of sib2, iclass 35, count 0 2006.197.08:00:02.15#ibcon#*mode == 0, iclass 35, count 0 2006.197.08:00:02.15#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.197.08:00:02.15#ibcon#[27=USB\r\n] 2006.197.08:00:02.15#ibcon#*before write, iclass 35, count 0 2006.197.08:00:02.15#ibcon#enter sib2, iclass 35, count 0 2006.197.08:00:02.15#ibcon#flushed, iclass 35, count 0 2006.197.08:00:02.15#ibcon#about to write, iclass 35, count 0 2006.197.08:00:02.15#ibcon#wrote, iclass 35, count 0 2006.197.08:00:02.15#ibcon#about to read 3, iclass 35, count 0 2006.197.08:00:02.18#ibcon#read 3, iclass 35, count 0 2006.197.08:00:02.18#ibcon#about to read 4, iclass 35, count 0 2006.197.08:00:02.18#ibcon#read 4, iclass 35, count 0 2006.197.08:00:02.18#ibcon#about to read 5, iclass 35, count 0 2006.197.08:00:02.18#ibcon#read 5, iclass 35, count 0 2006.197.08:00:02.18#ibcon#about to read 6, iclass 35, count 0 2006.197.08:00:02.18#ibcon#read 6, iclass 35, count 0 2006.197.08:00:02.18#ibcon#end of sib2, iclass 35, count 0 2006.197.08:00:02.18#ibcon#*after write, iclass 35, count 0 2006.197.08:00:02.18#ibcon#*before return 0, iclass 35, count 0 2006.197.08:00:02.18#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.197.08:00:02.18#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.197.08:00:02.18#ibcon#about to clear, iclass 35 cls_cnt 0 2006.197.08:00:02.18#ibcon#cleared, iclass 35 cls_cnt 0 2006.197.08:00:02.18$vc4f8/vabw=wide 2006.197.08:00:02.18#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.197.08:00:02.18#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.197.08:00:02.18#ibcon#ireg 8 cls_cnt 0 2006.197.08:00:02.18#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.197.08:00:02.18#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.197.08:00:02.18#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.197.08:00:02.18#ibcon#enter wrdev, iclass 37, count 0 2006.197.08:00:02.18#ibcon#first serial, iclass 37, count 0 2006.197.08:00:02.18#ibcon#enter sib2, iclass 37, count 0 2006.197.08:00:02.18#ibcon#flushed, iclass 37, count 0 2006.197.08:00:02.18#ibcon#about to write, iclass 37, count 0 2006.197.08:00:02.18#ibcon#wrote, iclass 37, count 0 2006.197.08:00:02.18#ibcon#about to read 3, iclass 37, count 0 2006.197.08:00:02.20#ibcon#read 3, iclass 37, count 0 2006.197.08:00:02.20#ibcon#about to read 4, iclass 37, count 0 2006.197.08:00:02.20#ibcon#read 4, iclass 37, count 0 2006.197.08:00:02.20#ibcon#about to read 5, iclass 37, count 0 2006.197.08:00:02.20#ibcon#read 5, iclass 37, count 0 2006.197.08:00:02.20#ibcon#about to read 6, iclass 37, count 0 2006.197.08:00:02.20#ibcon#read 6, iclass 37, count 0 2006.197.08:00:02.20#ibcon#end of sib2, iclass 37, count 0 2006.197.08:00:02.20#ibcon#*mode == 0, iclass 37, count 0 2006.197.08:00:02.20#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.197.08:00:02.20#ibcon#[25=BW32\r\n] 2006.197.08:00:02.20#ibcon#*before write, iclass 37, count 0 2006.197.08:00:02.20#ibcon#enter sib2, iclass 37, count 0 2006.197.08:00:02.20#ibcon#flushed, iclass 37, count 0 2006.197.08:00:02.20#ibcon#about to write, iclass 37, count 0 2006.197.08:00:02.20#ibcon#wrote, iclass 37, count 0 2006.197.08:00:02.20#ibcon#about to read 3, iclass 37, count 0 2006.197.08:00:02.23#ibcon#read 3, iclass 37, count 0 2006.197.08:00:02.23#ibcon#about to read 4, iclass 37, count 0 2006.197.08:00:02.23#ibcon#read 4, iclass 37, count 0 2006.197.08:00:02.23#ibcon#about to read 5, iclass 37, count 0 2006.197.08:00:02.23#ibcon#read 5, iclass 37, count 0 2006.197.08:00:02.23#ibcon#about to read 6, iclass 37, count 0 2006.197.08:00:02.23#ibcon#read 6, iclass 37, count 0 2006.197.08:00:02.23#ibcon#end of sib2, iclass 37, count 0 2006.197.08:00:02.23#ibcon#*after write, iclass 37, count 0 2006.197.08:00:02.23#ibcon#*before return 0, iclass 37, count 0 2006.197.08:00:02.23#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.197.08:00:02.23#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.197.08:00:02.23#ibcon#about to clear, iclass 37 cls_cnt 0 2006.197.08:00:02.23#ibcon#cleared, iclass 37 cls_cnt 0 2006.197.08:00:02.23$vc4f8/vbbw=wide 2006.197.08:00:02.23#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.197.08:00:02.23#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.197.08:00:02.23#ibcon#ireg 8 cls_cnt 0 2006.197.08:00:02.23#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.197.08:00:02.30#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.197.08:00:02.30#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.197.08:00:02.30#ibcon#enter wrdev, iclass 39, count 0 2006.197.08:00:02.30#ibcon#first serial, iclass 39, count 0 2006.197.08:00:02.30#ibcon#enter sib2, iclass 39, count 0 2006.197.08:00:02.30#ibcon#flushed, iclass 39, count 0 2006.197.08:00:02.30#ibcon#about to write, iclass 39, count 0 2006.197.08:00:02.30#ibcon#wrote, iclass 39, count 0 2006.197.08:00:02.30#ibcon#about to read 3, iclass 39, count 0 2006.197.08:00:02.32#ibcon#read 3, iclass 39, count 0 2006.197.08:00:02.32#ibcon#about to read 4, iclass 39, count 0 2006.197.08:00:02.32#ibcon#read 4, iclass 39, count 0 2006.197.08:00:02.32#ibcon#about to read 5, iclass 39, count 0 2006.197.08:00:02.32#ibcon#read 5, iclass 39, count 0 2006.197.08:00:02.32#ibcon#about to read 6, iclass 39, count 0 2006.197.08:00:02.32#ibcon#read 6, iclass 39, count 0 2006.197.08:00:02.32#ibcon#end of sib2, iclass 39, count 0 2006.197.08:00:02.32#ibcon#*mode == 0, iclass 39, count 0 2006.197.08:00:02.32#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.197.08:00:02.32#ibcon#[27=BW32\r\n] 2006.197.08:00:02.32#ibcon#*before write, iclass 39, count 0 2006.197.08:00:02.32#ibcon#enter sib2, iclass 39, count 0 2006.197.08:00:02.32#ibcon#flushed, iclass 39, count 0 2006.197.08:00:02.32#ibcon#about to write, iclass 39, count 0 2006.197.08:00:02.32#ibcon#wrote, iclass 39, count 0 2006.197.08:00:02.32#ibcon#about to read 3, iclass 39, count 0 2006.197.08:00:02.35#ibcon#read 3, iclass 39, count 0 2006.197.08:00:02.35#ibcon#about to read 4, iclass 39, count 0 2006.197.08:00:02.35#ibcon#read 4, iclass 39, count 0 2006.197.08:00:02.35#ibcon#about to read 5, iclass 39, count 0 2006.197.08:00:02.35#ibcon#read 5, iclass 39, count 0 2006.197.08:00:02.35#ibcon#about to read 6, iclass 39, count 0 2006.197.08:00:02.35#ibcon#read 6, iclass 39, count 0 2006.197.08:00:02.35#ibcon#end of sib2, iclass 39, count 0 2006.197.08:00:02.35#ibcon#*after write, iclass 39, count 0 2006.197.08:00:02.35#ibcon#*before return 0, iclass 39, count 0 2006.197.08:00:02.35#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.197.08:00:02.35#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.197.08:00:02.35#ibcon#about to clear, iclass 39 cls_cnt 0 2006.197.08:00:02.35#ibcon#cleared, iclass 39 cls_cnt 0 2006.197.08:00:02.35$4f8m12a/ifd4f 2006.197.08:00:02.35$ifd4f/lo= 2006.197.08:00:02.35$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.197.08:00:02.35$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.197.08:00:02.35$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.197.08:00:02.35$ifd4f/patch= 2006.197.08:00:02.35$ifd4f/patch=lo1,a1,a2,a3,a4 2006.197.08:00:02.35$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.197.08:00:02.35$ifd4f/patch=lo3,a5,a6,a7,a8 2006.197.08:00:02.35$4f8m12a/"form=m,16.000,1:2 2006.197.08:00:02.35$4f8m12a/"tpicd 2006.197.08:00:02.35$4f8m12a/echo=off 2006.197.08:00:02.35$4f8m12a/xlog=off 2006.197.08:00:02.35:!2006.197.08:01:00 2006.197.08:00:42.14#trakl#Source acquired 2006.197.08:00:42.14#flagr#flagr/antenna,acquired 2006.197.08:01:00.00:preob 2006.197.08:01:01.14/onsource/TRACKING 2006.197.08:01:01.14:!2006.197.08:01:10 2006.197.08:01:10.00:data_valid=on 2006.197.08:01:10.00:midob 2006.197.08:01:10.14/onsource/TRACKING 2006.197.08:01:10.14/wx/25.70,1002.8,96 2006.197.08:01:10.21/cable/+6.3706E-03 2006.197.08:01:11.30/va/01,08,usb,yes,29,31 2006.197.08:01:11.30/va/02,07,usb,yes,29,31 2006.197.08:01:11.30/va/03,06,usb,yes,31,31 2006.197.08:01:11.30/va/04,07,usb,yes,30,32 2006.197.08:01:11.30/va/05,07,usb,yes,34,36 2006.197.08:01:11.30/va/06,06,usb,yes,33,33 2006.197.08:01:11.30/va/07,06,usb,yes,33,33 2006.197.08:01:11.30/va/08,07,usb,yes,32,31 2006.197.08:01:11.53/valo/01,532.99,yes,locked 2006.197.08:01:11.53/valo/02,572.99,yes,locked 2006.197.08:01:11.53/valo/03,672.99,yes,locked 2006.197.08:01:11.53/valo/04,832.99,yes,locked 2006.197.08:01:11.53/valo/05,652.99,yes,locked 2006.197.08:01:11.53/valo/06,772.99,yes,locked 2006.197.08:01:11.53/valo/07,832.99,yes,locked 2006.197.08:01:11.53/valo/08,852.99,yes,locked 2006.197.08:01:12.62/vb/01,04,usb,yes,29,27 2006.197.08:01:12.62/vb/02,04,usb,yes,30,32 2006.197.08:01:12.62/vb/03,04,usb,yes,27,31 2006.197.08:01:12.62/vb/04,04,usb,yes,28,28 2006.197.08:01:12.62/vb/05,04,usb,yes,26,30 2006.197.08:01:12.62/vb/06,04,usb,yes,27,30 2006.197.08:01:12.62/vb/07,04,usb,yes,29,29 2006.197.08:01:12.62/vb/08,04,usb,yes,27,30 2006.197.08:01:12.86/vblo/01,632.99,yes,locked 2006.197.08:01:12.86/vblo/02,640.99,yes,locked 2006.197.08:01:12.86/vblo/03,656.99,yes,locked 2006.197.08:01:12.86/vblo/04,712.99,yes,locked 2006.197.08:01:12.86/vblo/05,744.99,yes,locked 2006.197.08:01:12.86/vblo/06,752.99,yes,locked 2006.197.08:01:12.86/vblo/07,734.99,yes,locked 2006.197.08:01:12.86/vblo/08,744.99,yes,locked 2006.197.08:01:13.01/vabw/8 2006.197.08:01:13.16/vbbw/8 2006.197.08:01:13.25/xfe/off,on,15.7 2006.197.08:01:13.62/ifatt/23,28,28,28 2006.197.08:01:14.09/fmout-gps/S +3.01E-07 2006.197.08:01:14.13:!2006.197.08:02:10 2006.197.08:02:10.00:data_valid=off 2006.197.08:02:10.00:postob 2006.197.08:02:10.16/cable/+6.3706E-03 2006.197.08:02:10.16/wx/25.70,1002.8,96 2006.197.08:02:11.09/fmout-gps/S +3.02E-07 2006.197.08:02:11.09:scan_name=197-0803,k06197,60 2006.197.08:02:11.09:source=1803+784,180045.68,782804.0,2000.0,cw 2006.197.08:02:11.14#flagr#flagr/antenna,new-source 2006.197.08:02:12.14:checkk5 2006.197.08:02:12.47/chk_autoobs//k5ts1/ autoobs is running! 2006.197.08:02:12.82/chk_autoobs//k5ts2/ autoobs is running! 2006.197.08:02:13.16/chk_autoobs//k5ts3/ autoobs is running! 2006.197.08:02:13.50/chk_autoobs//k5ts4/ autoobs is running! 2006.197.08:02:13.86/chk_obsdata//k5ts1/T1970801??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.08:02:14.20/chk_obsdata//k5ts2/T1970801??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.08:02:14.54/chk_obsdata//k5ts3/T1970801??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.08:02:14.88/chk_obsdata//k5ts4/T1970801??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.08:02:15.55/k5log//k5ts1_log_newline 2006.197.08:02:16.21/k5log//k5ts2_log_newline 2006.197.08:02:16.86/k5log//k5ts3_log_newline 2006.197.08:02:17.52/k5log//k5ts4_log_newline 2006.197.08:02:17.54/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.197.08:02:17.54:4f8m12a=2 2006.197.08:02:17.54$4f8m12a/echo=on 2006.197.08:02:17.54$4f8m12a/pcalon 2006.197.08:02:17.54$pcalon/"no phase cal control is implemented here 2006.197.08:02:17.54$4f8m12a/"tpicd=stop 2006.197.08:02:17.54$4f8m12a/vc4f8 2006.197.08:02:17.54$vc4f8/valo=1,532.99 2006.197.08:02:17.55#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.197.08:02:17.55#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.197.08:02:17.55#ibcon#ireg 17 cls_cnt 0 2006.197.08:02:17.55#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.197.08:02:17.55#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.197.08:02:17.55#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.197.08:02:17.55#ibcon#enter wrdev, iclass 22, count 0 2006.197.08:02:17.55#ibcon#first serial, iclass 22, count 0 2006.197.08:02:17.55#ibcon#enter sib2, iclass 22, count 0 2006.197.08:02:17.55#ibcon#flushed, iclass 22, count 0 2006.197.08:02:17.55#ibcon#about to write, iclass 22, count 0 2006.197.08:02:17.55#ibcon#wrote, iclass 22, count 0 2006.197.08:02:17.55#ibcon#about to read 3, iclass 22, count 0 2006.197.08:02:17.57#ibcon#read 3, iclass 22, count 0 2006.197.08:02:17.57#ibcon#about to read 4, iclass 22, count 0 2006.197.08:02:17.57#ibcon#read 4, iclass 22, count 0 2006.197.08:02:17.57#ibcon#about to read 5, iclass 22, count 0 2006.197.08:02:17.57#ibcon#read 5, iclass 22, count 0 2006.197.08:02:17.57#ibcon#about to read 6, iclass 22, count 0 2006.197.08:02:17.57#ibcon#read 6, iclass 22, count 0 2006.197.08:02:17.57#ibcon#end of sib2, iclass 22, count 0 2006.197.08:02:17.57#ibcon#*mode == 0, iclass 22, count 0 2006.197.08:02:17.57#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.197.08:02:17.57#ibcon#[26=FRQ=01,532.99\r\n] 2006.197.08:02:17.57#ibcon#*before write, iclass 22, count 0 2006.197.08:02:17.57#ibcon#enter sib2, iclass 22, count 0 2006.197.08:02:17.57#ibcon#flushed, iclass 22, count 0 2006.197.08:02:17.57#ibcon#about to write, iclass 22, count 0 2006.197.08:02:17.57#ibcon#wrote, iclass 22, count 0 2006.197.08:02:17.57#ibcon#about to read 3, iclass 22, count 0 2006.197.08:02:17.62#ibcon#read 3, iclass 22, count 0 2006.197.08:02:17.62#ibcon#about to read 4, iclass 22, count 0 2006.197.08:02:17.62#ibcon#read 4, iclass 22, count 0 2006.197.08:02:17.62#ibcon#about to read 5, iclass 22, count 0 2006.197.08:02:17.62#ibcon#read 5, iclass 22, count 0 2006.197.08:02:17.62#ibcon#about to read 6, iclass 22, count 0 2006.197.08:02:17.62#ibcon#read 6, iclass 22, count 0 2006.197.08:02:17.62#ibcon#end of sib2, iclass 22, count 0 2006.197.08:02:17.62#ibcon#*after write, iclass 22, count 0 2006.197.08:02:17.62#ibcon#*before return 0, iclass 22, count 0 2006.197.08:02:17.62#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.197.08:02:17.62#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.197.08:02:17.62#ibcon#about to clear, iclass 22 cls_cnt 0 2006.197.08:02:17.62#ibcon#cleared, iclass 22 cls_cnt 0 2006.197.08:02:17.62$vc4f8/va=1,8 2006.197.08:02:17.62#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.197.08:02:17.62#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.197.08:02:17.62#ibcon#ireg 11 cls_cnt 2 2006.197.08:02:17.62#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.197.08:02:17.62#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.197.08:02:17.62#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.197.08:02:17.62#ibcon#enter wrdev, iclass 24, count 2 2006.197.08:02:17.62#ibcon#first serial, iclass 24, count 2 2006.197.08:02:17.62#ibcon#enter sib2, iclass 24, count 2 2006.197.08:02:17.62#ibcon#flushed, iclass 24, count 2 2006.197.08:02:17.62#ibcon#about to write, iclass 24, count 2 2006.197.08:02:17.62#ibcon#wrote, iclass 24, count 2 2006.197.08:02:17.62#ibcon#about to read 3, iclass 24, count 2 2006.197.08:02:17.64#ibcon#read 3, iclass 24, count 2 2006.197.08:02:17.64#ibcon#about to read 4, iclass 24, count 2 2006.197.08:02:17.64#ibcon#read 4, iclass 24, count 2 2006.197.08:02:17.64#ibcon#about to read 5, iclass 24, count 2 2006.197.08:02:17.64#ibcon#read 5, iclass 24, count 2 2006.197.08:02:17.64#ibcon#about to read 6, iclass 24, count 2 2006.197.08:02:17.64#ibcon#read 6, iclass 24, count 2 2006.197.08:02:17.64#ibcon#end of sib2, iclass 24, count 2 2006.197.08:02:17.64#ibcon#*mode == 0, iclass 24, count 2 2006.197.08:02:17.64#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.197.08:02:17.64#ibcon#[25=AT01-08\r\n] 2006.197.08:02:17.64#ibcon#*before write, iclass 24, count 2 2006.197.08:02:17.64#ibcon#enter sib2, iclass 24, count 2 2006.197.08:02:17.64#ibcon#flushed, iclass 24, count 2 2006.197.08:02:17.64#ibcon#about to write, iclass 24, count 2 2006.197.08:02:17.64#ibcon#wrote, iclass 24, count 2 2006.197.08:02:17.64#ibcon#about to read 3, iclass 24, count 2 2006.197.08:02:17.67#ibcon#read 3, iclass 24, count 2 2006.197.08:02:17.67#ibcon#about to read 4, iclass 24, count 2 2006.197.08:02:17.67#ibcon#read 4, iclass 24, count 2 2006.197.08:02:17.67#ibcon#about to read 5, iclass 24, count 2 2006.197.08:02:17.67#ibcon#read 5, iclass 24, count 2 2006.197.08:02:17.67#ibcon#about to read 6, iclass 24, count 2 2006.197.08:02:17.67#ibcon#read 6, iclass 24, count 2 2006.197.08:02:17.67#ibcon#end of sib2, iclass 24, count 2 2006.197.08:02:17.67#ibcon#*after write, iclass 24, count 2 2006.197.08:02:17.67#ibcon#*before return 0, iclass 24, count 2 2006.197.08:02:17.67#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.197.08:02:17.67#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.197.08:02:17.67#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.197.08:02:17.67#ibcon#ireg 7 cls_cnt 0 2006.197.08:02:17.67#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.197.08:02:17.79#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.197.08:02:17.79#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.197.08:02:17.79#ibcon#enter wrdev, iclass 24, count 0 2006.197.08:02:17.79#ibcon#first serial, iclass 24, count 0 2006.197.08:02:17.79#ibcon#enter sib2, iclass 24, count 0 2006.197.08:02:17.79#ibcon#flushed, iclass 24, count 0 2006.197.08:02:17.79#ibcon#about to write, iclass 24, count 0 2006.197.08:02:17.79#ibcon#wrote, iclass 24, count 0 2006.197.08:02:17.79#ibcon#about to read 3, iclass 24, count 0 2006.197.08:02:17.81#ibcon#read 3, iclass 24, count 0 2006.197.08:02:17.81#ibcon#about to read 4, iclass 24, count 0 2006.197.08:02:17.81#ibcon#read 4, iclass 24, count 0 2006.197.08:02:17.81#ibcon#about to read 5, iclass 24, count 0 2006.197.08:02:17.81#ibcon#read 5, iclass 24, count 0 2006.197.08:02:17.81#ibcon#about to read 6, iclass 24, count 0 2006.197.08:02:17.81#ibcon#read 6, iclass 24, count 0 2006.197.08:02:17.81#ibcon#end of sib2, iclass 24, count 0 2006.197.08:02:17.81#ibcon#*mode == 0, iclass 24, count 0 2006.197.08:02:17.81#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.197.08:02:17.81#ibcon#[25=USB\r\n] 2006.197.08:02:17.81#ibcon#*before write, iclass 24, count 0 2006.197.08:02:17.81#ibcon#enter sib2, iclass 24, count 0 2006.197.08:02:17.81#ibcon#flushed, iclass 24, count 0 2006.197.08:02:17.81#ibcon#about to write, iclass 24, count 0 2006.197.08:02:17.81#ibcon#wrote, iclass 24, count 0 2006.197.08:02:17.81#ibcon#about to read 3, iclass 24, count 0 2006.197.08:02:17.84#ibcon#read 3, iclass 24, count 0 2006.197.08:02:17.84#ibcon#about to read 4, iclass 24, count 0 2006.197.08:02:17.84#ibcon#read 4, iclass 24, count 0 2006.197.08:02:17.84#ibcon#about to read 5, iclass 24, count 0 2006.197.08:02:17.84#ibcon#read 5, iclass 24, count 0 2006.197.08:02:17.84#ibcon#about to read 6, iclass 24, count 0 2006.197.08:02:17.84#ibcon#read 6, iclass 24, count 0 2006.197.08:02:17.84#ibcon#end of sib2, iclass 24, count 0 2006.197.08:02:17.84#ibcon#*after write, iclass 24, count 0 2006.197.08:02:17.84#ibcon#*before return 0, iclass 24, count 0 2006.197.08:02:17.84#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.197.08:02:17.84#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.197.08:02:17.84#ibcon#about to clear, iclass 24 cls_cnt 0 2006.197.08:02:17.84#ibcon#cleared, iclass 24 cls_cnt 0 2006.197.08:02:17.84$vc4f8/valo=2,572.99 2006.197.08:02:17.84#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.197.08:02:17.84#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.197.08:02:17.84#ibcon#ireg 17 cls_cnt 0 2006.197.08:02:17.84#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.197.08:02:17.84#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.197.08:02:17.84#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.197.08:02:17.84#ibcon#enter wrdev, iclass 26, count 0 2006.197.08:02:17.84#ibcon#first serial, iclass 26, count 0 2006.197.08:02:17.84#ibcon#enter sib2, iclass 26, count 0 2006.197.08:02:17.84#ibcon#flushed, iclass 26, count 0 2006.197.08:02:17.84#ibcon#about to write, iclass 26, count 0 2006.197.08:02:17.84#ibcon#wrote, iclass 26, count 0 2006.197.08:02:17.84#ibcon#about to read 3, iclass 26, count 0 2006.197.08:02:17.86#ibcon#read 3, iclass 26, count 0 2006.197.08:02:17.86#ibcon#about to read 4, iclass 26, count 0 2006.197.08:02:17.86#ibcon#read 4, iclass 26, count 0 2006.197.08:02:17.86#ibcon#about to read 5, iclass 26, count 0 2006.197.08:02:17.86#ibcon#read 5, iclass 26, count 0 2006.197.08:02:17.86#ibcon#about to read 6, iclass 26, count 0 2006.197.08:02:17.86#ibcon#read 6, iclass 26, count 0 2006.197.08:02:17.86#ibcon#end of sib2, iclass 26, count 0 2006.197.08:02:17.86#ibcon#*mode == 0, iclass 26, count 0 2006.197.08:02:17.86#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.197.08:02:17.86#ibcon#[26=FRQ=02,572.99\r\n] 2006.197.08:02:17.86#ibcon#*before write, iclass 26, count 0 2006.197.08:02:17.86#ibcon#enter sib2, iclass 26, count 0 2006.197.08:02:17.86#ibcon#flushed, iclass 26, count 0 2006.197.08:02:17.86#ibcon#about to write, iclass 26, count 0 2006.197.08:02:17.86#ibcon#wrote, iclass 26, count 0 2006.197.08:02:17.86#ibcon#about to read 3, iclass 26, count 0 2006.197.08:02:17.90#ibcon#read 3, iclass 26, count 0 2006.197.08:02:17.90#ibcon#about to read 4, iclass 26, count 0 2006.197.08:02:17.90#ibcon#read 4, iclass 26, count 0 2006.197.08:02:17.90#ibcon#about to read 5, iclass 26, count 0 2006.197.08:02:17.90#ibcon#read 5, iclass 26, count 0 2006.197.08:02:17.90#ibcon#about to read 6, iclass 26, count 0 2006.197.08:02:17.90#ibcon#read 6, iclass 26, count 0 2006.197.08:02:17.90#ibcon#end of sib2, iclass 26, count 0 2006.197.08:02:17.90#ibcon#*after write, iclass 26, count 0 2006.197.08:02:17.90#ibcon#*before return 0, iclass 26, count 0 2006.197.08:02:17.90#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.197.08:02:17.90#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.197.08:02:17.90#ibcon#about to clear, iclass 26 cls_cnt 0 2006.197.08:02:17.90#ibcon#cleared, iclass 26 cls_cnt 0 2006.197.08:02:17.90$vc4f8/va=2,7 2006.197.08:02:17.90#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.197.08:02:17.90#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.197.08:02:17.90#ibcon#ireg 11 cls_cnt 2 2006.197.08:02:17.90#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.197.08:02:17.96#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.197.08:02:17.96#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.197.08:02:17.96#ibcon#enter wrdev, iclass 28, count 2 2006.197.08:02:17.96#ibcon#first serial, iclass 28, count 2 2006.197.08:02:17.96#ibcon#enter sib2, iclass 28, count 2 2006.197.08:02:17.96#ibcon#flushed, iclass 28, count 2 2006.197.08:02:17.96#ibcon#about to write, iclass 28, count 2 2006.197.08:02:17.96#ibcon#wrote, iclass 28, count 2 2006.197.08:02:17.96#ibcon#about to read 3, iclass 28, count 2 2006.197.08:02:17.98#ibcon#read 3, iclass 28, count 2 2006.197.08:02:17.98#ibcon#about to read 4, iclass 28, count 2 2006.197.08:02:17.98#ibcon#read 4, iclass 28, count 2 2006.197.08:02:17.98#ibcon#about to read 5, iclass 28, count 2 2006.197.08:02:17.98#ibcon#read 5, iclass 28, count 2 2006.197.08:02:17.98#ibcon#about to read 6, iclass 28, count 2 2006.197.08:02:17.98#ibcon#read 6, iclass 28, count 2 2006.197.08:02:17.98#ibcon#end of sib2, iclass 28, count 2 2006.197.08:02:17.98#ibcon#*mode == 0, iclass 28, count 2 2006.197.08:02:17.98#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.197.08:02:17.98#ibcon#[25=AT02-07\r\n] 2006.197.08:02:17.98#ibcon#*before write, iclass 28, count 2 2006.197.08:02:17.98#ibcon#enter sib2, iclass 28, count 2 2006.197.08:02:17.98#ibcon#flushed, iclass 28, count 2 2006.197.08:02:17.98#ibcon#about to write, iclass 28, count 2 2006.197.08:02:17.98#ibcon#wrote, iclass 28, count 2 2006.197.08:02:17.98#ibcon#about to read 3, iclass 28, count 2 2006.197.08:02:18.01#ibcon#read 3, iclass 28, count 2 2006.197.08:02:18.01#ibcon#about to read 4, iclass 28, count 2 2006.197.08:02:18.01#ibcon#read 4, iclass 28, count 2 2006.197.08:02:18.01#ibcon#about to read 5, iclass 28, count 2 2006.197.08:02:18.01#ibcon#read 5, iclass 28, count 2 2006.197.08:02:18.01#ibcon#about to read 6, iclass 28, count 2 2006.197.08:02:18.01#ibcon#read 6, iclass 28, count 2 2006.197.08:02:18.01#ibcon#end of sib2, iclass 28, count 2 2006.197.08:02:18.01#ibcon#*after write, iclass 28, count 2 2006.197.08:02:18.01#ibcon#*before return 0, iclass 28, count 2 2006.197.08:02:18.01#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.197.08:02:18.01#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.197.08:02:18.01#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.197.08:02:18.01#ibcon#ireg 7 cls_cnt 0 2006.197.08:02:18.01#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.197.08:02:18.13#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.197.08:02:18.13#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.197.08:02:18.13#ibcon#enter wrdev, iclass 28, count 0 2006.197.08:02:18.13#ibcon#first serial, iclass 28, count 0 2006.197.08:02:18.13#ibcon#enter sib2, iclass 28, count 0 2006.197.08:02:18.13#ibcon#flushed, iclass 28, count 0 2006.197.08:02:18.13#ibcon#about to write, iclass 28, count 0 2006.197.08:02:18.13#ibcon#wrote, iclass 28, count 0 2006.197.08:02:18.13#ibcon#about to read 3, iclass 28, count 0 2006.197.08:02:18.15#ibcon#read 3, iclass 28, count 0 2006.197.08:02:18.15#ibcon#about to read 4, iclass 28, count 0 2006.197.08:02:18.15#ibcon#read 4, iclass 28, count 0 2006.197.08:02:18.15#ibcon#about to read 5, iclass 28, count 0 2006.197.08:02:18.15#ibcon#read 5, iclass 28, count 0 2006.197.08:02:18.15#ibcon#about to read 6, iclass 28, count 0 2006.197.08:02:18.15#ibcon#read 6, iclass 28, count 0 2006.197.08:02:18.15#ibcon#end of sib2, iclass 28, count 0 2006.197.08:02:18.15#ibcon#*mode == 0, iclass 28, count 0 2006.197.08:02:18.15#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.197.08:02:18.15#ibcon#[25=USB\r\n] 2006.197.08:02:18.15#ibcon#*before write, iclass 28, count 0 2006.197.08:02:18.15#ibcon#enter sib2, iclass 28, count 0 2006.197.08:02:18.15#ibcon#flushed, iclass 28, count 0 2006.197.08:02:18.15#ibcon#about to write, iclass 28, count 0 2006.197.08:02:18.15#ibcon#wrote, iclass 28, count 0 2006.197.08:02:18.15#ibcon#about to read 3, iclass 28, count 0 2006.197.08:02:18.18#ibcon#read 3, iclass 28, count 0 2006.197.08:02:18.18#ibcon#about to read 4, iclass 28, count 0 2006.197.08:02:18.18#ibcon#read 4, iclass 28, count 0 2006.197.08:02:18.18#ibcon#about to read 5, iclass 28, count 0 2006.197.08:02:18.18#ibcon#read 5, iclass 28, count 0 2006.197.08:02:18.18#ibcon#about to read 6, iclass 28, count 0 2006.197.08:02:18.18#ibcon#read 6, iclass 28, count 0 2006.197.08:02:18.18#ibcon#end of sib2, iclass 28, count 0 2006.197.08:02:18.18#ibcon#*after write, iclass 28, count 0 2006.197.08:02:18.18#ibcon#*before return 0, iclass 28, count 0 2006.197.08:02:18.18#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.197.08:02:18.18#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.197.08:02:18.18#ibcon#about to clear, iclass 28 cls_cnt 0 2006.197.08:02:18.18#ibcon#cleared, iclass 28 cls_cnt 0 2006.197.08:02:18.18$vc4f8/valo=3,672.99 2006.197.08:02:18.18#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.197.08:02:18.18#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.197.08:02:18.18#ibcon#ireg 17 cls_cnt 0 2006.197.08:02:18.18#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.197.08:02:18.18#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.197.08:02:18.18#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.197.08:02:18.18#ibcon#enter wrdev, iclass 30, count 0 2006.197.08:02:18.18#ibcon#first serial, iclass 30, count 0 2006.197.08:02:18.18#ibcon#enter sib2, iclass 30, count 0 2006.197.08:02:18.18#ibcon#flushed, iclass 30, count 0 2006.197.08:02:18.18#ibcon#about to write, iclass 30, count 0 2006.197.08:02:18.18#ibcon#wrote, iclass 30, count 0 2006.197.08:02:18.18#ibcon#about to read 3, iclass 30, count 0 2006.197.08:02:18.20#ibcon#read 3, iclass 30, count 0 2006.197.08:02:18.20#ibcon#about to read 4, iclass 30, count 0 2006.197.08:02:18.20#ibcon#read 4, iclass 30, count 0 2006.197.08:02:18.20#ibcon#about to read 5, iclass 30, count 0 2006.197.08:02:18.20#ibcon#read 5, iclass 30, count 0 2006.197.08:02:18.20#ibcon#about to read 6, iclass 30, count 0 2006.197.08:02:18.20#ibcon#read 6, iclass 30, count 0 2006.197.08:02:18.20#ibcon#end of sib2, iclass 30, count 0 2006.197.08:02:18.20#ibcon#*mode == 0, iclass 30, count 0 2006.197.08:02:18.20#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.197.08:02:18.20#ibcon#[26=FRQ=03,672.99\r\n] 2006.197.08:02:18.20#ibcon#*before write, iclass 30, count 0 2006.197.08:02:18.20#ibcon#enter sib2, iclass 30, count 0 2006.197.08:02:18.20#ibcon#flushed, iclass 30, count 0 2006.197.08:02:18.20#ibcon#about to write, iclass 30, count 0 2006.197.08:02:18.20#ibcon#wrote, iclass 30, count 0 2006.197.08:02:18.20#ibcon#about to read 3, iclass 30, count 0 2006.197.08:02:18.24#ibcon#read 3, iclass 30, count 0 2006.197.08:02:18.24#ibcon#about to read 4, iclass 30, count 0 2006.197.08:02:18.24#ibcon#read 4, iclass 30, count 0 2006.197.08:02:18.24#ibcon#about to read 5, iclass 30, count 0 2006.197.08:02:18.24#ibcon#read 5, iclass 30, count 0 2006.197.08:02:18.24#ibcon#about to read 6, iclass 30, count 0 2006.197.08:02:18.24#ibcon#read 6, iclass 30, count 0 2006.197.08:02:18.24#ibcon#end of sib2, iclass 30, count 0 2006.197.08:02:18.24#ibcon#*after write, iclass 30, count 0 2006.197.08:02:18.24#ibcon#*before return 0, iclass 30, count 0 2006.197.08:02:18.24#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.197.08:02:18.24#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.197.08:02:18.24#ibcon#about to clear, iclass 30 cls_cnt 0 2006.197.08:02:18.24#ibcon#cleared, iclass 30 cls_cnt 0 2006.197.08:02:18.24$vc4f8/va=3,6 2006.197.08:02:18.24#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.197.08:02:18.24#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.197.08:02:18.24#ibcon#ireg 11 cls_cnt 2 2006.197.08:02:18.24#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.197.08:02:18.30#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.197.08:02:18.30#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.197.08:02:18.30#ibcon#enter wrdev, iclass 32, count 2 2006.197.08:02:18.30#ibcon#first serial, iclass 32, count 2 2006.197.08:02:18.30#ibcon#enter sib2, iclass 32, count 2 2006.197.08:02:18.30#ibcon#flushed, iclass 32, count 2 2006.197.08:02:18.30#ibcon#about to write, iclass 32, count 2 2006.197.08:02:18.30#ibcon#wrote, iclass 32, count 2 2006.197.08:02:18.30#ibcon#about to read 3, iclass 32, count 2 2006.197.08:02:18.32#ibcon#read 3, iclass 32, count 2 2006.197.08:02:18.32#ibcon#about to read 4, iclass 32, count 2 2006.197.08:02:18.32#ibcon#read 4, iclass 32, count 2 2006.197.08:02:18.32#ibcon#about to read 5, iclass 32, count 2 2006.197.08:02:18.32#ibcon#read 5, iclass 32, count 2 2006.197.08:02:18.32#ibcon#about to read 6, iclass 32, count 2 2006.197.08:02:18.32#ibcon#read 6, iclass 32, count 2 2006.197.08:02:18.32#ibcon#end of sib2, iclass 32, count 2 2006.197.08:02:18.32#ibcon#*mode == 0, iclass 32, count 2 2006.197.08:02:18.32#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.197.08:02:18.32#ibcon#[25=AT03-06\r\n] 2006.197.08:02:18.32#ibcon#*before write, iclass 32, count 2 2006.197.08:02:18.32#ibcon#enter sib2, iclass 32, count 2 2006.197.08:02:18.32#ibcon#flushed, iclass 32, count 2 2006.197.08:02:18.32#ibcon#about to write, iclass 32, count 2 2006.197.08:02:18.32#ibcon#wrote, iclass 32, count 2 2006.197.08:02:18.32#ibcon#about to read 3, iclass 32, count 2 2006.197.08:02:18.35#ibcon#read 3, iclass 32, count 2 2006.197.08:02:18.35#ibcon#about to read 4, iclass 32, count 2 2006.197.08:02:18.35#ibcon#read 4, iclass 32, count 2 2006.197.08:02:18.35#ibcon#about to read 5, iclass 32, count 2 2006.197.08:02:18.35#ibcon#read 5, iclass 32, count 2 2006.197.08:02:18.35#ibcon#about to read 6, iclass 32, count 2 2006.197.08:02:18.35#ibcon#read 6, iclass 32, count 2 2006.197.08:02:18.35#ibcon#end of sib2, iclass 32, count 2 2006.197.08:02:18.35#ibcon#*after write, iclass 32, count 2 2006.197.08:02:18.35#ibcon#*before return 0, iclass 32, count 2 2006.197.08:02:18.35#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.197.08:02:18.35#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.197.08:02:18.35#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.197.08:02:18.35#ibcon#ireg 7 cls_cnt 0 2006.197.08:02:18.35#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.197.08:02:18.47#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.197.08:02:18.47#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.197.08:02:18.47#ibcon#enter wrdev, iclass 32, count 0 2006.197.08:02:18.47#ibcon#first serial, iclass 32, count 0 2006.197.08:02:18.47#ibcon#enter sib2, iclass 32, count 0 2006.197.08:02:18.47#ibcon#flushed, iclass 32, count 0 2006.197.08:02:18.47#ibcon#about to write, iclass 32, count 0 2006.197.08:02:18.47#ibcon#wrote, iclass 32, count 0 2006.197.08:02:18.47#ibcon#about to read 3, iclass 32, count 0 2006.197.08:02:18.49#ibcon#read 3, iclass 32, count 0 2006.197.08:02:18.49#ibcon#about to read 4, iclass 32, count 0 2006.197.08:02:18.49#ibcon#read 4, iclass 32, count 0 2006.197.08:02:18.49#ibcon#about to read 5, iclass 32, count 0 2006.197.08:02:18.49#ibcon#read 5, iclass 32, count 0 2006.197.08:02:18.49#ibcon#about to read 6, iclass 32, count 0 2006.197.08:02:18.49#ibcon#read 6, iclass 32, count 0 2006.197.08:02:18.49#ibcon#end of sib2, iclass 32, count 0 2006.197.08:02:18.49#ibcon#*mode == 0, iclass 32, count 0 2006.197.08:02:18.49#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.197.08:02:18.49#ibcon#[25=USB\r\n] 2006.197.08:02:18.49#ibcon#*before write, iclass 32, count 0 2006.197.08:02:18.49#ibcon#enter sib2, iclass 32, count 0 2006.197.08:02:18.49#ibcon#flushed, iclass 32, count 0 2006.197.08:02:18.49#ibcon#about to write, iclass 32, count 0 2006.197.08:02:18.49#ibcon#wrote, iclass 32, count 0 2006.197.08:02:18.49#ibcon#about to read 3, iclass 32, count 0 2006.197.08:02:18.52#ibcon#read 3, iclass 32, count 0 2006.197.08:02:18.52#ibcon#about to read 4, iclass 32, count 0 2006.197.08:02:18.52#ibcon#read 4, iclass 32, count 0 2006.197.08:02:18.52#ibcon#about to read 5, iclass 32, count 0 2006.197.08:02:18.52#ibcon#read 5, iclass 32, count 0 2006.197.08:02:18.52#ibcon#about to read 6, iclass 32, count 0 2006.197.08:02:18.52#ibcon#read 6, iclass 32, count 0 2006.197.08:02:18.52#ibcon#end of sib2, iclass 32, count 0 2006.197.08:02:18.52#ibcon#*after write, iclass 32, count 0 2006.197.08:02:18.52#ibcon#*before return 0, iclass 32, count 0 2006.197.08:02:18.52#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.197.08:02:18.52#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.197.08:02:18.52#ibcon#about to clear, iclass 32 cls_cnt 0 2006.197.08:02:18.52#ibcon#cleared, iclass 32 cls_cnt 0 2006.197.08:02:18.52$vc4f8/valo=4,832.99 2006.197.08:02:18.52#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.197.08:02:18.52#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.197.08:02:18.52#ibcon#ireg 17 cls_cnt 0 2006.197.08:02:18.52#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.197.08:02:18.52#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.197.08:02:18.52#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.197.08:02:18.52#ibcon#enter wrdev, iclass 34, count 0 2006.197.08:02:18.52#ibcon#first serial, iclass 34, count 0 2006.197.08:02:18.52#ibcon#enter sib2, iclass 34, count 0 2006.197.08:02:18.52#ibcon#flushed, iclass 34, count 0 2006.197.08:02:18.52#ibcon#about to write, iclass 34, count 0 2006.197.08:02:18.52#ibcon#wrote, iclass 34, count 0 2006.197.08:02:18.52#ibcon#about to read 3, iclass 34, count 0 2006.197.08:02:18.54#ibcon#read 3, iclass 34, count 0 2006.197.08:02:18.54#ibcon#about to read 4, iclass 34, count 0 2006.197.08:02:18.54#ibcon#read 4, iclass 34, count 0 2006.197.08:02:18.54#ibcon#about to read 5, iclass 34, count 0 2006.197.08:02:18.54#ibcon#read 5, iclass 34, count 0 2006.197.08:02:18.54#ibcon#about to read 6, iclass 34, count 0 2006.197.08:02:18.54#ibcon#read 6, iclass 34, count 0 2006.197.08:02:18.54#ibcon#end of sib2, iclass 34, count 0 2006.197.08:02:18.54#ibcon#*mode == 0, iclass 34, count 0 2006.197.08:02:18.54#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.197.08:02:18.54#ibcon#[26=FRQ=04,832.99\r\n] 2006.197.08:02:18.54#ibcon#*before write, iclass 34, count 0 2006.197.08:02:18.54#ibcon#enter sib2, iclass 34, count 0 2006.197.08:02:18.54#ibcon#flushed, iclass 34, count 0 2006.197.08:02:18.54#ibcon#about to write, iclass 34, count 0 2006.197.08:02:18.54#ibcon#wrote, iclass 34, count 0 2006.197.08:02:18.54#ibcon#about to read 3, iclass 34, count 0 2006.197.08:02:18.58#ibcon#read 3, iclass 34, count 0 2006.197.08:02:18.58#ibcon#about to read 4, iclass 34, count 0 2006.197.08:02:18.58#ibcon#read 4, iclass 34, count 0 2006.197.08:02:18.58#ibcon#about to read 5, iclass 34, count 0 2006.197.08:02:18.58#ibcon#read 5, iclass 34, count 0 2006.197.08:02:18.58#ibcon#about to read 6, iclass 34, count 0 2006.197.08:02:18.58#ibcon#read 6, iclass 34, count 0 2006.197.08:02:18.58#ibcon#end of sib2, iclass 34, count 0 2006.197.08:02:18.58#ibcon#*after write, iclass 34, count 0 2006.197.08:02:18.58#ibcon#*before return 0, iclass 34, count 0 2006.197.08:02:18.58#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.197.08:02:18.58#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.197.08:02:18.58#ibcon#about to clear, iclass 34 cls_cnt 0 2006.197.08:02:18.58#ibcon#cleared, iclass 34 cls_cnt 0 2006.197.08:02:18.58$vc4f8/va=4,7 2006.197.08:02:18.58#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.197.08:02:18.58#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.197.08:02:18.58#ibcon#ireg 11 cls_cnt 2 2006.197.08:02:18.58#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.197.08:02:18.64#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.197.08:02:18.64#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.197.08:02:18.64#ibcon#enter wrdev, iclass 36, count 2 2006.197.08:02:18.64#ibcon#first serial, iclass 36, count 2 2006.197.08:02:18.64#ibcon#enter sib2, iclass 36, count 2 2006.197.08:02:18.64#ibcon#flushed, iclass 36, count 2 2006.197.08:02:18.64#ibcon#about to write, iclass 36, count 2 2006.197.08:02:18.64#ibcon#wrote, iclass 36, count 2 2006.197.08:02:18.64#ibcon#about to read 3, iclass 36, count 2 2006.197.08:02:18.66#ibcon#read 3, iclass 36, count 2 2006.197.08:02:18.66#ibcon#about to read 4, iclass 36, count 2 2006.197.08:02:18.66#ibcon#read 4, iclass 36, count 2 2006.197.08:02:18.66#ibcon#about to read 5, iclass 36, count 2 2006.197.08:02:18.66#ibcon#read 5, iclass 36, count 2 2006.197.08:02:18.66#ibcon#about to read 6, iclass 36, count 2 2006.197.08:02:18.66#ibcon#read 6, iclass 36, count 2 2006.197.08:02:18.66#ibcon#end of sib2, iclass 36, count 2 2006.197.08:02:18.66#ibcon#*mode == 0, iclass 36, count 2 2006.197.08:02:18.66#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.197.08:02:18.66#ibcon#[25=AT04-07\r\n] 2006.197.08:02:18.66#ibcon#*before write, iclass 36, count 2 2006.197.08:02:18.66#ibcon#enter sib2, iclass 36, count 2 2006.197.08:02:18.66#ibcon#flushed, iclass 36, count 2 2006.197.08:02:18.66#ibcon#about to write, iclass 36, count 2 2006.197.08:02:18.66#ibcon#wrote, iclass 36, count 2 2006.197.08:02:18.66#ibcon#about to read 3, iclass 36, count 2 2006.197.08:02:18.69#ibcon#read 3, iclass 36, count 2 2006.197.08:02:18.69#ibcon#about to read 4, iclass 36, count 2 2006.197.08:02:18.69#ibcon#read 4, iclass 36, count 2 2006.197.08:02:18.69#ibcon#about to read 5, iclass 36, count 2 2006.197.08:02:18.69#ibcon#read 5, iclass 36, count 2 2006.197.08:02:18.69#ibcon#about to read 6, iclass 36, count 2 2006.197.08:02:18.69#ibcon#read 6, iclass 36, count 2 2006.197.08:02:18.69#ibcon#end of sib2, iclass 36, count 2 2006.197.08:02:18.69#ibcon#*after write, iclass 36, count 2 2006.197.08:02:18.69#ibcon#*before return 0, iclass 36, count 2 2006.197.08:02:18.69#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.197.08:02:18.69#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.197.08:02:18.69#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.197.08:02:18.69#ibcon#ireg 7 cls_cnt 0 2006.197.08:02:18.69#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.197.08:02:18.81#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.197.08:02:18.81#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.197.08:02:18.81#ibcon#enter wrdev, iclass 36, count 0 2006.197.08:02:18.81#ibcon#first serial, iclass 36, count 0 2006.197.08:02:18.81#ibcon#enter sib2, iclass 36, count 0 2006.197.08:02:18.81#ibcon#flushed, iclass 36, count 0 2006.197.08:02:18.81#ibcon#about to write, iclass 36, count 0 2006.197.08:02:18.81#ibcon#wrote, iclass 36, count 0 2006.197.08:02:18.81#ibcon#about to read 3, iclass 36, count 0 2006.197.08:02:18.83#ibcon#read 3, iclass 36, count 0 2006.197.08:02:18.83#ibcon#about to read 4, iclass 36, count 0 2006.197.08:02:18.83#ibcon#read 4, iclass 36, count 0 2006.197.08:02:18.83#ibcon#about to read 5, iclass 36, count 0 2006.197.08:02:18.83#ibcon#read 5, iclass 36, count 0 2006.197.08:02:18.83#ibcon#about to read 6, iclass 36, count 0 2006.197.08:02:18.83#ibcon#read 6, iclass 36, count 0 2006.197.08:02:18.83#ibcon#end of sib2, iclass 36, count 0 2006.197.08:02:18.83#ibcon#*mode == 0, iclass 36, count 0 2006.197.08:02:18.83#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.197.08:02:18.83#ibcon#[25=USB\r\n] 2006.197.08:02:18.83#ibcon#*before write, iclass 36, count 0 2006.197.08:02:18.83#ibcon#enter sib2, iclass 36, count 0 2006.197.08:02:18.83#ibcon#flushed, iclass 36, count 0 2006.197.08:02:18.83#ibcon#about to write, iclass 36, count 0 2006.197.08:02:18.83#ibcon#wrote, iclass 36, count 0 2006.197.08:02:18.83#ibcon#about to read 3, iclass 36, count 0 2006.197.08:02:18.86#ibcon#read 3, iclass 36, count 0 2006.197.08:02:18.86#ibcon#about to read 4, iclass 36, count 0 2006.197.08:02:18.86#ibcon#read 4, iclass 36, count 0 2006.197.08:02:18.86#ibcon#about to read 5, iclass 36, count 0 2006.197.08:02:18.86#ibcon#read 5, iclass 36, count 0 2006.197.08:02:18.86#ibcon#about to read 6, iclass 36, count 0 2006.197.08:02:18.86#ibcon#read 6, iclass 36, count 0 2006.197.08:02:18.86#ibcon#end of sib2, iclass 36, count 0 2006.197.08:02:18.86#ibcon#*after write, iclass 36, count 0 2006.197.08:02:18.86#ibcon#*before return 0, iclass 36, count 0 2006.197.08:02:18.86#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.197.08:02:18.86#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.197.08:02:18.86#ibcon#about to clear, iclass 36 cls_cnt 0 2006.197.08:02:18.86#ibcon#cleared, iclass 36 cls_cnt 0 2006.197.08:02:18.86$vc4f8/valo=5,652.99 2006.197.08:02:18.86#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.197.08:02:18.86#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.197.08:02:18.86#ibcon#ireg 17 cls_cnt 0 2006.197.08:02:18.86#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.197.08:02:18.86#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.197.08:02:18.86#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.197.08:02:18.86#ibcon#enter wrdev, iclass 38, count 0 2006.197.08:02:18.86#ibcon#first serial, iclass 38, count 0 2006.197.08:02:18.86#ibcon#enter sib2, iclass 38, count 0 2006.197.08:02:18.86#ibcon#flushed, iclass 38, count 0 2006.197.08:02:18.86#ibcon#about to write, iclass 38, count 0 2006.197.08:02:18.86#ibcon#wrote, iclass 38, count 0 2006.197.08:02:18.86#ibcon#about to read 3, iclass 38, count 0 2006.197.08:02:18.88#ibcon#read 3, iclass 38, count 0 2006.197.08:02:18.88#ibcon#about to read 4, iclass 38, count 0 2006.197.08:02:18.88#ibcon#read 4, iclass 38, count 0 2006.197.08:02:18.88#ibcon#about to read 5, iclass 38, count 0 2006.197.08:02:18.88#ibcon#read 5, iclass 38, count 0 2006.197.08:02:18.88#ibcon#about to read 6, iclass 38, count 0 2006.197.08:02:18.88#ibcon#read 6, iclass 38, count 0 2006.197.08:02:18.88#ibcon#end of sib2, iclass 38, count 0 2006.197.08:02:18.88#ibcon#*mode == 0, iclass 38, count 0 2006.197.08:02:18.88#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.197.08:02:18.88#ibcon#[26=FRQ=05,652.99\r\n] 2006.197.08:02:18.88#ibcon#*before write, iclass 38, count 0 2006.197.08:02:18.88#ibcon#enter sib2, iclass 38, count 0 2006.197.08:02:18.88#ibcon#flushed, iclass 38, count 0 2006.197.08:02:18.88#ibcon#about to write, iclass 38, count 0 2006.197.08:02:18.88#ibcon#wrote, iclass 38, count 0 2006.197.08:02:18.88#ibcon#about to read 3, iclass 38, count 0 2006.197.08:02:18.92#ibcon#read 3, iclass 38, count 0 2006.197.08:02:18.92#ibcon#about to read 4, iclass 38, count 0 2006.197.08:02:18.92#ibcon#read 4, iclass 38, count 0 2006.197.08:02:18.92#ibcon#about to read 5, iclass 38, count 0 2006.197.08:02:18.92#ibcon#read 5, iclass 38, count 0 2006.197.08:02:18.92#ibcon#about to read 6, iclass 38, count 0 2006.197.08:02:18.92#ibcon#read 6, iclass 38, count 0 2006.197.08:02:18.92#ibcon#end of sib2, iclass 38, count 0 2006.197.08:02:18.92#ibcon#*after write, iclass 38, count 0 2006.197.08:02:18.92#ibcon#*before return 0, iclass 38, count 0 2006.197.08:02:18.92#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.197.08:02:18.92#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.197.08:02:18.92#ibcon#about to clear, iclass 38 cls_cnt 0 2006.197.08:02:18.92#ibcon#cleared, iclass 38 cls_cnt 0 2006.197.08:02:18.92$vc4f8/va=5,7 2006.197.08:02:18.92#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.197.08:02:18.92#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.197.08:02:18.92#ibcon#ireg 11 cls_cnt 2 2006.197.08:02:18.92#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.197.08:02:18.98#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.197.08:02:18.98#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.197.08:02:18.98#ibcon#enter wrdev, iclass 40, count 2 2006.197.08:02:18.98#ibcon#first serial, iclass 40, count 2 2006.197.08:02:18.98#ibcon#enter sib2, iclass 40, count 2 2006.197.08:02:18.98#ibcon#flushed, iclass 40, count 2 2006.197.08:02:18.98#ibcon#about to write, iclass 40, count 2 2006.197.08:02:18.98#ibcon#wrote, iclass 40, count 2 2006.197.08:02:18.98#ibcon#about to read 3, iclass 40, count 2 2006.197.08:02:19.00#ibcon#read 3, iclass 40, count 2 2006.197.08:02:19.00#ibcon#about to read 4, iclass 40, count 2 2006.197.08:02:19.00#ibcon#read 4, iclass 40, count 2 2006.197.08:02:19.00#ibcon#about to read 5, iclass 40, count 2 2006.197.08:02:19.00#ibcon#read 5, iclass 40, count 2 2006.197.08:02:19.00#ibcon#about to read 6, iclass 40, count 2 2006.197.08:02:19.00#ibcon#read 6, iclass 40, count 2 2006.197.08:02:19.00#ibcon#end of sib2, iclass 40, count 2 2006.197.08:02:19.00#ibcon#*mode == 0, iclass 40, count 2 2006.197.08:02:19.00#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.197.08:02:19.00#ibcon#[25=AT05-07\r\n] 2006.197.08:02:19.00#ibcon#*before write, iclass 40, count 2 2006.197.08:02:19.00#ibcon#enter sib2, iclass 40, count 2 2006.197.08:02:19.00#ibcon#flushed, iclass 40, count 2 2006.197.08:02:19.00#ibcon#about to write, iclass 40, count 2 2006.197.08:02:19.00#ibcon#wrote, iclass 40, count 2 2006.197.08:02:19.00#ibcon#about to read 3, iclass 40, count 2 2006.197.08:02:19.03#ibcon#read 3, iclass 40, count 2 2006.197.08:02:19.03#ibcon#about to read 4, iclass 40, count 2 2006.197.08:02:19.03#ibcon#read 4, iclass 40, count 2 2006.197.08:02:19.03#ibcon#about to read 5, iclass 40, count 2 2006.197.08:02:19.03#ibcon#read 5, iclass 40, count 2 2006.197.08:02:19.03#ibcon#about to read 6, iclass 40, count 2 2006.197.08:02:19.03#ibcon#read 6, iclass 40, count 2 2006.197.08:02:19.03#ibcon#end of sib2, iclass 40, count 2 2006.197.08:02:19.03#ibcon#*after write, iclass 40, count 2 2006.197.08:02:19.03#ibcon#*before return 0, iclass 40, count 2 2006.197.08:02:19.03#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.197.08:02:19.03#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.197.08:02:19.03#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.197.08:02:19.03#ibcon#ireg 7 cls_cnt 0 2006.197.08:02:19.03#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.197.08:02:19.15#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.197.08:02:19.15#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.197.08:02:19.15#ibcon#enter wrdev, iclass 40, count 0 2006.197.08:02:19.15#ibcon#first serial, iclass 40, count 0 2006.197.08:02:19.15#ibcon#enter sib2, iclass 40, count 0 2006.197.08:02:19.15#ibcon#flushed, iclass 40, count 0 2006.197.08:02:19.15#ibcon#about to write, iclass 40, count 0 2006.197.08:02:19.15#ibcon#wrote, iclass 40, count 0 2006.197.08:02:19.15#ibcon#about to read 3, iclass 40, count 0 2006.197.08:02:19.17#ibcon#read 3, iclass 40, count 0 2006.197.08:02:19.17#ibcon#about to read 4, iclass 40, count 0 2006.197.08:02:19.17#ibcon#read 4, iclass 40, count 0 2006.197.08:02:19.17#ibcon#about to read 5, iclass 40, count 0 2006.197.08:02:19.17#ibcon#read 5, iclass 40, count 0 2006.197.08:02:19.17#ibcon#about to read 6, iclass 40, count 0 2006.197.08:02:19.17#ibcon#read 6, iclass 40, count 0 2006.197.08:02:19.17#ibcon#end of sib2, iclass 40, count 0 2006.197.08:02:19.17#ibcon#*mode == 0, iclass 40, count 0 2006.197.08:02:19.17#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.197.08:02:19.17#ibcon#[25=USB\r\n] 2006.197.08:02:19.17#ibcon#*before write, iclass 40, count 0 2006.197.08:02:19.17#ibcon#enter sib2, iclass 40, count 0 2006.197.08:02:19.17#ibcon#flushed, iclass 40, count 0 2006.197.08:02:19.17#ibcon#about to write, iclass 40, count 0 2006.197.08:02:19.17#ibcon#wrote, iclass 40, count 0 2006.197.08:02:19.17#ibcon#about to read 3, iclass 40, count 0 2006.197.08:02:19.20#ibcon#read 3, iclass 40, count 0 2006.197.08:02:19.20#ibcon#about to read 4, iclass 40, count 0 2006.197.08:02:19.20#ibcon#read 4, iclass 40, count 0 2006.197.08:02:19.20#ibcon#about to read 5, iclass 40, count 0 2006.197.08:02:19.20#ibcon#read 5, iclass 40, count 0 2006.197.08:02:19.20#ibcon#about to read 6, iclass 40, count 0 2006.197.08:02:19.20#ibcon#read 6, iclass 40, count 0 2006.197.08:02:19.20#ibcon#end of sib2, iclass 40, count 0 2006.197.08:02:19.20#ibcon#*after write, iclass 40, count 0 2006.197.08:02:19.20#ibcon#*before return 0, iclass 40, count 0 2006.197.08:02:19.20#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.197.08:02:19.20#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.197.08:02:19.20#ibcon#about to clear, iclass 40 cls_cnt 0 2006.197.08:02:19.20#ibcon#cleared, iclass 40 cls_cnt 0 2006.197.08:02:19.20$vc4f8/valo=6,772.99 2006.197.08:02:19.20#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.197.08:02:19.20#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.197.08:02:19.20#ibcon#ireg 17 cls_cnt 0 2006.197.08:02:19.20#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.197.08:02:19.20#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.197.08:02:19.20#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.197.08:02:19.20#ibcon#enter wrdev, iclass 4, count 0 2006.197.08:02:19.20#ibcon#first serial, iclass 4, count 0 2006.197.08:02:19.20#ibcon#enter sib2, iclass 4, count 0 2006.197.08:02:19.20#ibcon#flushed, iclass 4, count 0 2006.197.08:02:19.20#ibcon#about to write, iclass 4, count 0 2006.197.08:02:19.20#ibcon#wrote, iclass 4, count 0 2006.197.08:02:19.20#ibcon#about to read 3, iclass 4, count 0 2006.197.08:02:19.22#ibcon#read 3, iclass 4, count 0 2006.197.08:02:19.22#ibcon#about to read 4, iclass 4, count 0 2006.197.08:02:19.22#ibcon#read 4, iclass 4, count 0 2006.197.08:02:19.22#ibcon#about to read 5, iclass 4, count 0 2006.197.08:02:19.22#ibcon#read 5, iclass 4, count 0 2006.197.08:02:19.22#ibcon#about to read 6, iclass 4, count 0 2006.197.08:02:19.22#ibcon#read 6, iclass 4, count 0 2006.197.08:02:19.22#ibcon#end of sib2, iclass 4, count 0 2006.197.08:02:19.22#ibcon#*mode == 0, iclass 4, count 0 2006.197.08:02:19.22#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.197.08:02:19.22#ibcon#[26=FRQ=06,772.99\r\n] 2006.197.08:02:19.22#ibcon#*before write, iclass 4, count 0 2006.197.08:02:19.22#ibcon#enter sib2, iclass 4, count 0 2006.197.08:02:19.22#ibcon#flushed, iclass 4, count 0 2006.197.08:02:19.22#ibcon#about to write, iclass 4, count 0 2006.197.08:02:19.22#ibcon#wrote, iclass 4, count 0 2006.197.08:02:19.22#ibcon#about to read 3, iclass 4, count 0 2006.197.08:02:19.26#ibcon#read 3, iclass 4, count 0 2006.197.08:02:19.26#ibcon#about to read 4, iclass 4, count 0 2006.197.08:02:19.26#ibcon#read 4, iclass 4, count 0 2006.197.08:02:19.26#ibcon#about to read 5, iclass 4, count 0 2006.197.08:02:19.26#ibcon#read 5, iclass 4, count 0 2006.197.08:02:19.26#ibcon#about to read 6, iclass 4, count 0 2006.197.08:02:19.26#ibcon#read 6, iclass 4, count 0 2006.197.08:02:19.26#ibcon#end of sib2, iclass 4, count 0 2006.197.08:02:19.26#ibcon#*after write, iclass 4, count 0 2006.197.08:02:19.26#ibcon#*before return 0, iclass 4, count 0 2006.197.08:02:19.26#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.197.08:02:19.26#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.197.08:02:19.26#ibcon#about to clear, iclass 4 cls_cnt 0 2006.197.08:02:19.26#ibcon#cleared, iclass 4 cls_cnt 0 2006.197.08:02:19.26$vc4f8/va=6,6 2006.197.08:02:19.26#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.197.08:02:19.26#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.197.08:02:19.26#ibcon#ireg 11 cls_cnt 2 2006.197.08:02:19.26#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.197.08:02:19.32#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.197.08:02:19.32#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.197.08:02:19.32#ibcon#enter wrdev, iclass 6, count 2 2006.197.08:02:19.32#ibcon#first serial, iclass 6, count 2 2006.197.08:02:19.32#ibcon#enter sib2, iclass 6, count 2 2006.197.08:02:19.32#ibcon#flushed, iclass 6, count 2 2006.197.08:02:19.32#ibcon#about to write, iclass 6, count 2 2006.197.08:02:19.32#ibcon#wrote, iclass 6, count 2 2006.197.08:02:19.32#ibcon#about to read 3, iclass 6, count 2 2006.197.08:02:19.34#ibcon#read 3, iclass 6, count 2 2006.197.08:02:19.34#ibcon#about to read 4, iclass 6, count 2 2006.197.08:02:19.34#ibcon#read 4, iclass 6, count 2 2006.197.08:02:19.34#ibcon#about to read 5, iclass 6, count 2 2006.197.08:02:19.34#ibcon#read 5, iclass 6, count 2 2006.197.08:02:19.34#ibcon#about to read 6, iclass 6, count 2 2006.197.08:02:19.34#ibcon#read 6, iclass 6, count 2 2006.197.08:02:19.34#ibcon#end of sib2, iclass 6, count 2 2006.197.08:02:19.34#ibcon#*mode == 0, iclass 6, count 2 2006.197.08:02:19.34#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.197.08:02:19.34#ibcon#[25=AT06-06\r\n] 2006.197.08:02:19.34#ibcon#*before write, iclass 6, count 2 2006.197.08:02:19.34#ibcon#enter sib2, iclass 6, count 2 2006.197.08:02:19.34#ibcon#flushed, iclass 6, count 2 2006.197.08:02:19.34#ibcon#about to write, iclass 6, count 2 2006.197.08:02:19.34#ibcon#wrote, iclass 6, count 2 2006.197.08:02:19.34#ibcon#about to read 3, iclass 6, count 2 2006.197.08:02:19.37#ibcon#read 3, iclass 6, count 2 2006.197.08:02:19.37#ibcon#about to read 4, iclass 6, count 2 2006.197.08:02:19.37#ibcon#read 4, iclass 6, count 2 2006.197.08:02:19.37#ibcon#about to read 5, iclass 6, count 2 2006.197.08:02:19.37#ibcon#read 5, iclass 6, count 2 2006.197.08:02:19.37#ibcon#about to read 6, iclass 6, count 2 2006.197.08:02:19.37#ibcon#read 6, iclass 6, count 2 2006.197.08:02:19.37#ibcon#end of sib2, iclass 6, count 2 2006.197.08:02:19.37#ibcon#*after write, iclass 6, count 2 2006.197.08:02:19.37#ibcon#*before return 0, iclass 6, count 2 2006.197.08:02:19.37#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.197.08:02:19.37#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.197.08:02:19.37#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.197.08:02:19.37#ibcon#ireg 7 cls_cnt 0 2006.197.08:02:19.37#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.197.08:02:19.49#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.197.08:02:19.49#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.197.08:02:19.49#ibcon#enter wrdev, iclass 6, count 0 2006.197.08:02:19.49#ibcon#first serial, iclass 6, count 0 2006.197.08:02:19.49#ibcon#enter sib2, iclass 6, count 0 2006.197.08:02:19.49#ibcon#flushed, iclass 6, count 0 2006.197.08:02:19.49#ibcon#about to write, iclass 6, count 0 2006.197.08:02:19.49#ibcon#wrote, iclass 6, count 0 2006.197.08:02:19.49#ibcon#about to read 3, iclass 6, count 0 2006.197.08:02:19.51#ibcon#read 3, iclass 6, count 0 2006.197.08:02:19.51#ibcon#about to read 4, iclass 6, count 0 2006.197.08:02:19.51#ibcon#read 4, iclass 6, count 0 2006.197.08:02:19.51#ibcon#about to read 5, iclass 6, count 0 2006.197.08:02:19.51#ibcon#read 5, iclass 6, count 0 2006.197.08:02:19.51#ibcon#about to read 6, iclass 6, count 0 2006.197.08:02:19.51#ibcon#read 6, iclass 6, count 0 2006.197.08:02:19.51#ibcon#end of sib2, iclass 6, count 0 2006.197.08:02:19.51#ibcon#*mode == 0, iclass 6, count 0 2006.197.08:02:19.51#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.197.08:02:19.51#ibcon#[25=USB\r\n] 2006.197.08:02:19.51#ibcon#*before write, iclass 6, count 0 2006.197.08:02:19.51#ibcon#enter sib2, iclass 6, count 0 2006.197.08:02:19.51#ibcon#flushed, iclass 6, count 0 2006.197.08:02:19.51#ibcon#about to write, iclass 6, count 0 2006.197.08:02:19.51#ibcon#wrote, iclass 6, count 0 2006.197.08:02:19.51#ibcon#about to read 3, iclass 6, count 0 2006.197.08:02:19.54#ibcon#read 3, iclass 6, count 0 2006.197.08:02:19.54#ibcon#about to read 4, iclass 6, count 0 2006.197.08:02:19.54#ibcon#read 4, iclass 6, count 0 2006.197.08:02:19.54#ibcon#about to read 5, iclass 6, count 0 2006.197.08:02:19.54#ibcon#read 5, iclass 6, count 0 2006.197.08:02:19.54#ibcon#about to read 6, iclass 6, count 0 2006.197.08:02:19.54#ibcon#read 6, iclass 6, count 0 2006.197.08:02:19.54#ibcon#end of sib2, iclass 6, count 0 2006.197.08:02:19.54#ibcon#*after write, iclass 6, count 0 2006.197.08:02:19.54#ibcon#*before return 0, iclass 6, count 0 2006.197.08:02:19.54#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.197.08:02:19.54#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.197.08:02:19.54#ibcon#about to clear, iclass 6 cls_cnt 0 2006.197.08:02:19.54#ibcon#cleared, iclass 6 cls_cnt 0 2006.197.08:02:19.54$vc4f8/valo=7,832.99 2006.197.08:02:19.54#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.197.08:02:19.54#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.197.08:02:19.54#ibcon#ireg 17 cls_cnt 0 2006.197.08:02:19.54#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.197.08:02:19.54#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.197.08:02:19.54#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.197.08:02:19.54#ibcon#enter wrdev, iclass 10, count 0 2006.197.08:02:19.54#ibcon#first serial, iclass 10, count 0 2006.197.08:02:19.54#ibcon#enter sib2, iclass 10, count 0 2006.197.08:02:19.54#ibcon#flushed, iclass 10, count 0 2006.197.08:02:19.54#ibcon#about to write, iclass 10, count 0 2006.197.08:02:19.54#ibcon#wrote, iclass 10, count 0 2006.197.08:02:19.54#ibcon#about to read 3, iclass 10, count 0 2006.197.08:02:19.56#ibcon#read 3, iclass 10, count 0 2006.197.08:02:19.56#ibcon#about to read 4, iclass 10, count 0 2006.197.08:02:19.56#ibcon#read 4, iclass 10, count 0 2006.197.08:02:19.56#ibcon#about to read 5, iclass 10, count 0 2006.197.08:02:19.56#ibcon#read 5, iclass 10, count 0 2006.197.08:02:19.56#ibcon#about to read 6, iclass 10, count 0 2006.197.08:02:19.56#ibcon#read 6, iclass 10, count 0 2006.197.08:02:19.56#ibcon#end of sib2, iclass 10, count 0 2006.197.08:02:19.56#ibcon#*mode == 0, iclass 10, count 0 2006.197.08:02:19.56#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.197.08:02:19.56#ibcon#[26=FRQ=07,832.99\r\n] 2006.197.08:02:19.56#ibcon#*before write, iclass 10, count 0 2006.197.08:02:19.56#ibcon#enter sib2, iclass 10, count 0 2006.197.08:02:19.56#ibcon#flushed, iclass 10, count 0 2006.197.08:02:19.56#ibcon#about to write, iclass 10, count 0 2006.197.08:02:19.56#ibcon#wrote, iclass 10, count 0 2006.197.08:02:19.56#ibcon#about to read 3, iclass 10, count 0 2006.197.08:02:19.60#ibcon#read 3, iclass 10, count 0 2006.197.08:02:19.60#ibcon#about to read 4, iclass 10, count 0 2006.197.08:02:19.60#ibcon#read 4, iclass 10, count 0 2006.197.08:02:19.60#ibcon#about to read 5, iclass 10, count 0 2006.197.08:02:19.60#ibcon#read 5, iclass 10, count 0 2006.197.08:02:19.60#ibcon#about to read 6, iclass 10, count 0 2006.197.08:02:19.60#ibcon#read 6, iclass 10, count 0 2006.197.08:02:19.60#ibcon#end of sib2, iclass 10, count 0 2006.197.08:02:19.60#ibcon#*after write, iclass 10, count 0 2006.197.08:02:19.60#ibcon#*before return 0, iclass 10, count 0 2006.197.08:02:19.60#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.197.08:02:19.60#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.197.08:02:19.60#ibcon#about to clear, iclass 10 cls_cnt 0 2006.197.08:02:19.60#ibcon#cleared, iclass 10 cls_cnt 0 2006.197.08:02:19.60$vc4f8/va=7,6 2006.197.08:02:19.60#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.197.08:02:19.60#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.197.08:02:19.60#ibcon#ireg 11 cls_cnt 2 2006.197.08:02:19.60#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.197.08:02:19.66#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.197.08:02:19.66#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.197.08:02:19.66#ibcon#enter wrdev, iclass 12, count 2 2006.197.08:02:19.66#ibcon#first serial, iclass 12, count 2 2006.197.08:02:19.66#ibcon#enter sib2, iclass 12, count 2 2006.197.08:02:19.66#ibcon#flushed, iclass 12, count 2 2006.197.08:02:19.66#ibcon#about to write, iclass 12, count 2 2006.197.08:02:19.66#ibcon#wrote, iclass 12, count 2 2006.197.08:02:19.66#ibcon#about to read 3, iclass 12, count 2 2006.197.08:02:19.68#ibcon#read 3, iclass 12, count 2 2006.197.08:02:19.68#ibcon#about to read 4, iclass 12, count 2 2006.197.08:02:19.68#ibcon#read 4, iclass 12, count 2 2006.197.08:02:19.68#ibcon#about to read 5, iclass 12, count 2 2006.197.08:02:19.68#ibcon#read 5, iclass 12, count 2 2006.197.08:02:19.68#ibcon#about to read 6, iclass 12, count 2 2006.197.08:02:19.68#ibcon#read 6, iclass 12, count 2 2006.197.08:02:19.68#ibcon#end of sib2, iclass 12, count 2 2006.197.08:02:19.68#ibcon#*mode == 0, iclass 12, count 2 2006.197.08:02:19.68#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.197.08:02:19.68#ibcon#[25=AT07-06\r\n] 2006.197.08:02:19.68#ibcon#*before write, iclass 12, count 2 2006.197.08:02:19.68#ibcon#enter sib2, iclass 12, count 2 2006.197.08:02:19.68#ibcon#flushed, iclass 12, count 2 2006.197.08:02:19.68#ibcon#about to write, iclass 12, count 2 2006.197.08:02:19.68#ibcon#wrote, iclass 12, count 2 2006.197.08:02:19.68#ibcon#about to read 3, iclass 12, count 2 2006.197.08:02:19.71#ibcon#read 3, iclass 12, count 2 2006.197.08:02:19.71#ibcon#about to read 4, iclass 12, count 2 2006.197.08:02:19.71#ibcon#read 4, iclass 12, count 2 2006.197.08:02:19.71#ibcon#about to read 5, iclass 12, count 2 2006.197.08:02:19.71#ibcon#read 5, iclass 12, count 2 2006.197.08:02:19.71#ibcon#about to read 6, iclass 12, count 2 2006.197.08:02:19.71#ibcon#read 6, iclass 12, count 2 2006.197.08:02:19.71#ibcon#end of sib2, iclass 12, count 2 2006.197.08:02:19.71#ibcon#*after write, iclass 12, count 2 2006.197.08:02:19.71#ibcon#*before return 0, iclass 12, count 2 2006.197.08:02:19.71#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.197.08:02:19.71#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.197.08:02:19.71#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.197.08:02:19.71#ibcon#ireg 7 cls_cnt 0 2006.197.08:02:19.71#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.197.08:02:19.83#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.197.08:02:19.83#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.197.08:02:19.83#ibcon#enter wrdev, iclass 12, count 0 2006.197.08:02:19.83#ibcon#first serial, iclass 12, count 0 2006.197.08:02:19.83#ibcon#enter sib2, iclass 12, count 0 2006.197.08:02:19.83#ibcon#flushed, iclass 12, count 0 2006.197.08:02:19.83#ibcon#about to write, iclass 12, count 0 2006.197.08:02:19.83#ibcon#wrote, iclass 12, count 0 2006.197.08:02:19.83#ibcon#about to read 3, iclass 12, count 0 2006.197.08:02:19.85#ibcon#read 3, iclass 12, count 0 2006.197.08:02:19.85#ibcon#about to read 4, iclass 12, count 0 2006.197.08:02:19.85#ibcon#read 4, iclass 12, count 0 2006.197.08:02:19.85#ibcon#about to read 5, iclass 12, count 0 2006.197.08:02:19.85#ibcon#read 5, iclass 12, count 0 2006.197.08:02:19.85#ibcon#about to read 6, iclass 12, count 0 2006.197.08:02:19.85#ibcon#read 6, iclass 12, count 0 2006.197.08:02:19.85#ibcon#end of sib2, iclass 12, count 0 2006.197.08:02:19.85#ibcon#*mode == 0, iclass 12, count 0 2006.197.08:02:19.85#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.197.08:02:19.85#ibcon#[25=USB\r\n] 2006.197.08:02:19.85#ibcon#*before write, iclass 12, count 0 2006.197.08:02:19.85#ibcon#enter sib2, iclass 12, count 0 2006.197.08:02:19.85#ibcon#flushed, iclass 12, count 0 2006.197.08:02:19.85#ibcon#about to write, iclass 12, count 0 2006.197.08:02:19.85#ibcon#wrote, iclass 12, count 0 2006.197.08:02:19.85#ibcon#about to read 3, iclass 12, count 0 2006.197.08:02:19.88#ibcon#read 3, iclass 12, count 0 2006.197.08:02:19.88#ibcon#about to read 4, iclass 12, count 0 2006.197.08:02:19.88#ibcon#read 4, iclass 12, count 0 2006.197.08:02:19.88#ibcon#about to read 5, iclass 12, count 0 2006.197.08:02:19.88#ibcon#read 5, iclass 12, count 0 2006.197.08:02:19.88#ibcon#about to read 6, iclass 12, count 0 2006.197.08:02:19.88#ibcon#read 6, iclass 12, count 0 2006.197.08:02:19.88#ibcon#end of sib2, iclass 12, count 0 2006.197.08:02:19.88#ibcon#*after write, iclass 12, count 0 2006.197.08:02:19.88#ibcon#*before return 0, iclass 12, count 0 2006.197.08:02:19.88#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.197.08:02:19.88#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.197.08:02:19.88#ibcon#about to clear, iclass 12 cls_cnt 0 2006.197.08:02:19.88#ibcon#cleared, iclass 12 cls_cnt 0 2006.197.08:02:19.88$vc4f8/valo=8,852.99 2006.197.08:02:19.88#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.197.08:02:19.88#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.197.08:02:19.88#ibcon#ireg 17 cls_cnt 0 2006.197.08:02:19.88#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.197.08:02:19.88#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.197.08:02:19.88#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.197.08:02:19.88#ibcon#enter wrdev, iclass 14, count 0 2006.197.08:02:19.88#ibcon#first serial, iclass 14, count 0 2006.197.08:02:19.88#ibcon#enter sib2, iclass 14, count 0 2006.197.08:02:19.88#ibcon#flushed, iclass 14, count 0 2006.197.08:02:19.88#ibcon#about to write, iclass 14, count 0 2006.197.08:02:19.88#ibcon#wrote, iclass 14, count 0 2006.197.08:02:19.88#ibcon#about to read 3, iclass 14, count 0 2006.197.08:02:19.90#ibcon#read 3, iclass 14, count 0 2006.197.08:02:19.90#ibcon#about to read 4, iclass 14, count 0 2006.197.08:02:19.90#ibcon#read 4, iclass 14, count 0 2006.197.08:02:19.90#ibcon#about to read 5, iclass 14, count 0 2006.197.08:02:19.90#ibcon#read 5, iclass 14, count 0 2006.197.08:02:19.90#ibcon#about to read 6, iclass 14, count 0 2006.197.08:02:19.90#ibcon#read 6, iclass 14, count 0 2006.197.08:02:19.90#ibcon#end of sib2, iclass 14, count 0 2006.197.08:02:19.90#ibcon#*mode == 0, iclass 14, count 0 2006.197.08:02:19.90#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.197.08:02:19.90#ibcon#[26=FRQ=08,852.99\r\n] 2006.197.08:02:19.90#ibcon#*before write, iclass 14, count 0 2006.197.08:02:19.90#ibcon#enter sib2, iclass 14, count 0 2006.197.08:02:19.90#ibcon#flushed, iclass 14, count 0 2006.197.08:02:19.90#ibcon#about to write, iclass 14, count 0 2006.197.08:02:19.90#ibcon#wrote, iclass 14, count 0 2006.197.08:02:19.90#ibcon#about to read 3, iclass 14, count 0 2006.197.08:02:19.94#ibcon#read 3, iclass 14, count 0 2006.197.08:02:19.94#ibcon#about to read 4, iclass 14, count 0 2006.197.08:02:19.94#ibcon#read 4, iclass 14, count 0 2006.197.08:02:19.94#ibcon#about to read 5, iclass 14, count 0 2006.197.08:02:19.94#ibcon#read 5, iclass 14, count 0 2006.197.08:02:19.94#ibcon#about to read 6, iclass 14, count 0 2006.197.08:02:19.94#ibcon#read 6, iclass 14, count 0 2006.197.08:02:19.94#ibcon#end of sib2, iclass 14, count 0 2006.197.08:02:19.94#ibcon#*after write, iclass 14, count 0 2006.197.08:02:19.94#ibcon#*before return 0, iclass 14, count 0 2006.197.08:02:19.94#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.197.08:02:19.94#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.197.08:02:19.94#ibcon#about to clear, iclass 14 cls_cnt 0 2006.197.08:02:19.94#ibcon#cleared, iclass 14 cls_cnt 0 2006.197.08:02:19.94$vc4f8/va=8,7 2006.197.08:02:19.94#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.197.08:02:19.94#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.197.08:02:19.94#ibcon#ireg 11 cls_cnt 2 2006.197.08:02:19.94#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.197.08:02:20.00#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.197.08:02:20.00#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.197.08:02:20.00#ibcon#enter wrdev, iclass 16, count 2 2006.197.08:02:20.00#ibcon#first serial, iclass 16, count 2 2006.197.08:02:20.00#ibcon#enter sib2, iclass 16, count 2 2006.197.08:02:20.00#ibcon#flushed, iclass 16, count 2 2006.197.08:02:20.00#ibcon#about to write, iclass 16, count 2 2006.197.08:02:20.00#ibcon#wrote, iclass 16, count 2 2006.197.08:02:20.00#ibcon#about to read 3, iclass 16, count 2 2006.197.08:02:20.02#ibcon#read 3, iclass 16, count 2 2006.197.08:02:20.02#ibcon#about to read 4, iclass 16, count 2 2006.197.08:02:20.02#ibcon#read 4, iclass 16, count 2 2006.197.08:02:20.02#ibcon#about to read 5, iclass 16, count 2 2006.197.08:02:20.02#ibcon#read 5, iclass 16, count 2 2006.197.08:02:20.02#ibcon#about to read 6, iclass 16, count 2 2006.197.08:02:20.02#ibcon#read 6, iclass 16, count 2 2006.197.08:02:20.02#ibcon#end of sib2, iclass 16, count 2 2006.197.08:02:20.02#ibcon#*mode == 0, iclass 16, count 2 2006.197.08:02:20.02#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.197.08:02:20.02#ibcon#[25=AT08-07\r\n] 2006.197.08:02:20.02#ibcon#*before write, iclass 16, count 2 2006.197.08:02:20.02#ibcon#enter sib2, iclass 16, count 2 2006.197.08:02:20.02#ibcon#flushed, iclass 16, count 2 2006.197.08:02:20.02#ibcon#about to write, iclass 16, count 2 2006.197.08:02:20.02#ibcon#wrote, iclass 16, count 2 2006.197.08:02:20.02#ibcon#about to read 3, iclass 16, count 2 2006.197.08:02:20.03#abcon#<5=/04 3.4 6.6 25.69 961002.8\r\n> 2006.197.08:02:20.05#abcon#{5=INTERFACE CLEAR} 2006.197.08:02:20.05#ibcon#read 3, iclass 16, count 2 2006.197.08:02:20.05#ibcon#about to read 4, iclass 16, count 2 2006.197.08:02:20.05#ibcon#read 4, iclass 16, count 2 2006.197.08:02:20.05#ibcon#about to read 5, iclass 16, count 2 2006.197.08:02:20.05#ibcon#read 5, iclass 16, count 2 2006.197.08:02:20.05#ibcon#about to read 6, iclass 16, count 2 2006.197.08:02:20.05#ibcon#read 6, iclass 16, count 2 2006.197.08:02:20.05#ibcon#end of sib2, iclass 16, count 2 2006.197.08:02:20.05#ibcon#*after write, iclass 16, count 2 2006.197.08:02:20.05#ibcon#*before return 0, iclass 16, count 2 2006.197.08:02:20.05#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.197.08:02:20.05#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.197.08:02:20.05#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.197.08:02:20.05#ibcon#ireg 7 cls_cnt 0 2006.197.08:02:20.05#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.197.08:02:20.11#abcon#[5=S1D000X0/0*\r\n] 2006.197.08:02:20.17#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.197.08:02:20.17#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.197.08:02:20.17#ibcon#enter wrdev, iclass 16, count 0 2006.197.08:02:20.17#ibcon#first serial, iclass 16, count 0 2006.197.08:02:20.17#ibcon#enter sib2, iclass 16, count 0 2006.197.08:02:20.17#ibcon#flushed, iclass 16, count 0 2006.197.08:02:20.17#ibcon#about to write, iclass 16, count 0 2006.197.08:02:20.17#ibcon#wrote, iclass 16, count 0 2006.197.08:02:20.17#ibcon#about to read 3, iclass 16, count 0 2006.197.08:02:20.19#ibcon#read 3, iclass 16, count 0 2006.197.08:02:20.19#ibcon#about to read 4, iclass 16, count 0 2006.197.08:02:20.19#ibcon#read 4, iclass 16, count 0 2006.197.08:02:20.19#ibcon#about to read 5, iclass 16, count 0 2006.197.08:02:20.19#ibcon#read 5, iclass 16, count 0 2006.197.08:02:20.19#ibcon#about to read 6, iclass 16, count 0 2006.197.08:02:20.19#ibcon#read 6, iclass 16, count 0 2006.197.08:02:20.19#ibcon#end of sib2, iclass 16, count 0 2006.197.08:02:20.19#ibcon#*mode == 0, iclass 16, count 0 2006.197.08:02:20.19#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.197.08:02:20.19#ibcon#[25=USB\r\n] 2006.197.08:02:20.19#ibcon#*before write, iclass 16, count 0 2006.197.08:02:20.19#ibcon#enter sib2, iclass 16, count 0 2006.197.08:02:20.19#ibcon#flushed, iclass 16, count 0 2006.197.08:02:20.19#ibcon#about to write, iclass 16, count 0 2006.197.08:02:20.19#ibcon#wrote, iclass 16, count 0 2006.197.08:02:20.19#ibcon#about to read 3, iclass 16, count 0 2006.197.08:02:20.22#ibcon#read 3, iclass 16, count 0 2006.197.08:02:20.22#ibcon#about to read 4, iclass 16, count 0 2006.197.08:02:20.22#ibcon#read 4, iclass 16, count 0 2006.197.08:02:20.22#ibcon#about to read 5, iclass 16, count 0 2006.197.08:02:20.22#ibcon#read 5, iclass 16, count 0 2006.197.08:02:20.22#ibcon#about to read 6, iclass 16, count 0 2006.197.08:02:20.22#ibcon#read 6, iclass 16, count 0 2006.197.08:02:20.22#ibcon#end of sib2, iclass 16, count 0 2006.197.08:02:20.22#ibcon#*after write, iclass 16, count 0 2006.197.08:02:20.22#ibcon#*before return 0, iclass 16, count 0 2006.197.08:02:20.22#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.197.08:02:20.22#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.197.08:02:20.22#ibcon#about to clear, iclass 16 cls_cnt 0 2006.197.08:02:20.22#ibcon#cleared, iclass 16 cls_cnt 0 2006.197.08:02:20.22$vc4f8/vblo=1,632.99 2006.197.08:02:20.22#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.197.08:02:20.22#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.197.08:02:20.22#ibcon#ireg 17 cls_cnt 0 2006.197.08:02:20.22#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.197.08:02:20.22#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.197.08:02:20.22#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.197.08:02:20.22#ibcon#enter wrdev, iclass 22, count 0 2006.197.08:02:20.22#ibcon#first serial, iclass 22, count 0 2006.197.08:02:20.22#ibcon#enter sib2, iclass 22, count 0 2006.197.08:02:20.22#ibcon#flushed, iclass 22, count 0 2006.197.08:02:20.22#ibcon#about to write, iclass 22, count 0 2006.197.08:02:20.22#ibcon#wrote, iclass 22, count 0 2006.197.08:02:20.22#ibcon#about to read 3, iclass 22, count 0 2006.197.08:02:20.24#ibcon#read 3, iclass 22, count 0 2006.197.08:02:20.24#ibcon#about to read 4, iclass 22, count 0 2006.197.08:02:20.24#ibcon#read 4, iclass 22, count 0 2006.197.08:02:20.24#ibcon#about to read 5, iclass 22, count 0 2006.197.08:02:20.24#ibcon#read 5, iclass 22, count 0 2006.197.08:02:20.24#ibcon#about to read 6, iclass 22, count 0 2006.197.08:02:20.24#ibcon#read 6, iclass 22, count 0 2006.197.08:02:20.24#ibcon#end of sib2, iclass 22, count 0 2006.197.08:02:20.24#ibcon#*mode == 0, iclass 22, count 0 2006.197.08:02:20.24#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.197.08:02:20.24#ibcon#[28=FRQ=01,632.99\r\n] 2006.197.08:02:20.24#ibcon#*before write, iclass 22, count 0 2006.197.08:02:20.24#ibcon#enter sib2, iclass 22, count 0 2006.197.08:02:20.24#ibcon#flushed, iclass 22, count 0 2006.197.08:02:20.24#ibcon#about to write, iclass 22, count 0 2006.197.08:02:20.24#ibcon#wrote, iclass 22, count 0 2006.197.08:02:20.24#ibcon#about to read 3, iclass 22, count 0 2006.197.08:02:20.28#ibcon#read 3, iclass 22, count 0 2006.197.08:02:20.28#ibcon#about to read 4, iclass 22, count 0 2006.197.08:02:20.28#ibcon#read 4, iclass 22, count 0 2006.197.08:02:20.28#ibcon#about to read 5, iclass 22, count 0 2006.197.08:02:20.28#ibcon#read 5, iclass 22, count 0 2006.197.08:02:20.28#ibcon#about to read 6, iclass 22, count 0 2006.197.08:02:20.28#ibcon#read 6, iclass 22, count 0 2006.197.08:02:20.28#ibcon#end of sib2, iclass 22, count 0 2006.197.08:02:20.28#ibcon#*after write, iclass 22, count 0 2006.197.08:02:20.28#ibcon#*before return 0, iclass 22, count 0 2006.197.08:02:20.28#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.197.08:02:20.28#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.197.08:02:20.28#ibcon#about to clear, iclass 22 cls_cnt 0 2006.197.08:02:20.28#ibcon#cleared, iclass 22 cls_cnt 0 2006.197.08:02:20.28$vc4f8/vb=1,4 2006.197.08:02:20.28#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.197.08:02:20.28#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.197.08:02:20.28#ibcon#ireg 11 cls_cnt 2 2006.197.08:02:20.28#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.197.08:02:20.28#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.197.08:02:20.28#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.197.08:02:20.28#ibcon#enter wrdev, iclass 24, count 2 2006.197.08:02:20.28#ibcon#first serial, iclass 24, count 2 2006.197.08:02:20.28#ibcon#enter sib2, iclass 24, count 2 2006.197.08:02:20.28#ibcon#flushed, iclass 24, count 2 2006.197.08:02:20.28#ibcon#about to write, iclass 24, count 2 2006.197.08:02:20.28#ibcon#wrote, iclass 24, count 2 2006.197.08:02:20.28#ibcon#about to read 3, iclass 24, count 2 2006.197.08:02:20.30#ibcon#read 3, iclass 24, count 2 2006.197.08:02:20.30#ibcon#about to read 4, iclass 24, count 2 2006.197.08:02:20.30#ibcon#read 4, iclass 24, count 2 2006.197.08:02:20.30#ibcon#about to read 5, iclass 24, count 2 2006.197.08:02:20.30#ibcon#read 5, iclass 24, count 2 2006.197.08:02:20.30#ibcon#about to read 6, iclass 24, count 2 2006.197.08:02:20.30#ibcon#read 6, iclass 24, count 2 2006.197.08:02:20.30#ibcon#end of sib2, iclass 24, count 2 2006.197.08:02:20.30#ibcon#*mode == 0, iclass 24, count 2 2006.197.08:02:20.30#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.197.08:02:20.30#ibcon#[27=AT01-04\r\n] 2006.197.08:02:20.30#ibcon#*before write, iclass 24, count 2 2006.197.08:02:20.30#ibcon#enter sib2, iclass 24, count 2 2006.197.08:02:20.30#ibcon#flushed, iclass 24, count 2 2006.197.08:02:20.30#ibcon#about to write, iclass 24, count 2 2006.197.08:02:20.30#ibcon#wrote, iclass 24, count 2 2006.197.08:02:20.30#ibcon#about to read 3, iclass 24, count 2 2006.197.08:02:20.33#ibcon#read 3, iclass 24, count 2 2006.197.08:02:20.33#ibcon#about to read 4, iclass 24, count 2 2006.197.08:02:20.33#ibcon#read 4, iclass 24, count 2 2006.197.08:02:20.33#ibcon#about to read 5, iclass 24, count 2 2006.197.08:02:20.33#ibcon#read 5, iclass 24, count 2 2006.197.08:02:20.33#ibcon#about to read 6, iclass 24, count 2 2006.197.08:02:20.33#ibcon#read 6, iclass 24, count 2 2006.197.08:02:20.33#ibcon#end of sib2, iclass 24, count 2 2006.197.08:02:20.33#ibcon#*after write, iclass 24, count 2 2006.197.08:02:20.33#ibcon#*before return 0, iclass 24, count 2 2006.197.08:02:20.33#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.197.08:02:20.33#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.197.08:02:20.33#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.197.08:02:20.33#ibcon#ireg 7 cls_cnt 0 2006.197.08:02:20.33#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.197.08:02:20.45#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.197.08:02:20.45#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.197.08:02:20.45#ibcon#enter wrdev, iclass 24, count 0 2006.197.08:02:20.45#ibcon#first serial, iclass 24, count 0 2006.197.08:02:20.45#ibcon#enter sib2, iclass 24, count 0 2006.197.08:02:20.45#ibcon#flushed, iclass 24, count 0 2006.197.08:02:20.45#ibcon#about to write, iclass 24, count 0 2006.197.08:02:20.45#ibcon#wrote, iclass 24, count 0 2006.197.08:02:20.45#ibcon#about to read 3, iclass 24, count 0 2006.197.08:02:20.47#ibcon#read 3, iclass 24, count 0 2006.197.08:02:20.47#ibcon#about to read 4, iclass 24, count 0 2006.197.08:02:20.47#ibcon#read 4, iclass 24, count 0 2006.197.08:02:20.47#ibcon#about to read 5, iclass 24, count 0 2006.197.08:02:20.47#ibcon#read 5, iclass 24, count 0 2006.197.08:02:20.47#ibcon#about to read 6, iclass 24, count 0 2006.197.08:02:20.47#ibcon#read 6, iclass 24, count 0 2006.197.08:02:20.47#ibcon#end of sib2, iclass 24, count 0 2006.197.08:02:20.47#ibcon#*mode == 0, iclass 24, count 0 2006.197.08:02:20.47#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.197.08:02:20.47#ibcon#[27=USB\r\n] 2006.197.08:02:20.47#ibcon#*before write, iclass 24, count 0 2006.197.08:02:20.47#ibcon#enter sib2, iclass 24, count 0 2006.197.08:02:20.47#ibcon#flushed, iclass 24, count 0 2006.197.08:02:20.47#ibcon#about to write, iclass 24, count 0 2006.197.08:02:20.47#ibcon#wrote, iclass 24, count 0 2006.197.08:02:20.47#ibcon#about to read 3, iclass 24, count 0 2006.197.08:02:20.50#ibcon#read 3, iclass 24, count 0 2006.197.08:02:20.50#ibcon#about to read 4, iclass 24, count 0 2006.197.08:02:20.50#ibcon#read 4, iclass 24, count 0 2006.197.08:02:20.50#ibcon#about to read 5, iclass 24, count 0 2006.197.08:02:20.50#ibcon#read 5, iclass 24, count 0 2006.197.08:02:20.50#ibcon#about to read 6, iclass 24, count 0 2006.197.08:02:20.50#ibcon#read 6, iclass 24, count 0 2006.197.08:02:20.50#ibcon#end of sib2, iclass 24, count 0 2006.197.08:02:20.50#ibcon#*after write, iclass 24, count 0 2006.197.08:02:20.50#ibcon#*before return 0, iclass 24, count 0 2006.197.08:02:20.50#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.197.08:02:20.50#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.197.08:02:20.50#ibcon#about to clear, iclass 24 cls_cnt 0 2006.197.08:02:20.50#ibcon#cleared, iclass 24 cls_cnt 0 2006.197.08:02:20.50$vc4f8/vblo=2,640.99 2006.197.08:02:20.50#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.197.08:02:20.50#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.197.08:02:20.50#ibcon#ireg 17 cls_cnt 0 2006.197.08:02:20.50#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.197.08:02:20.50#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.197.08:02:20.50#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.197.08:02:20.50#ibcon#enter wrdev, iclass 26, count 0 2006.197.08:02:20.50#ibcon#first serial, iclass 26, count 0 2006.197.08:02:20.50#ibcon#enter sib2, iclass 26, count 0 2006.197.08:02:20.50#ibcon#flushed, iclass 26, count 0 2006.197.08:02:20.50#ibcon#about to write, iclass 26, count 0 2006.197.08:02:20.50#ibcon#wrote, iclass 26, count 0 2006.197.08:02:20.50#ibcon#about to read 3, iclass 26, count 0 2006.197.08:02:20.52#ibcon#read 3, iclass 26, count 0 2006.197.08:02:20.52#ibcon#about to read 4, iclass 26, count 0 2006.197.08:02:20.52#ibcon#read 4, iclass 26, count 0 2006.197.08:02:20.52#ibcon#about to read 5, iclass 26, count 0 2006.197.08:02:20.52#ibcon#read 5, iclass 26, count 0 2006.197.08:02:20.52#ibcon#about to read 6, iclass 26, count 0 2006.197.08:02:20.52#ibcon#read 6, iclass 26, count 0 2006.197.08:02:20.52#ibcon#end of sib2, iclass 26, count 0 2006.197.08:02:20.52#ibcon#*mode == 0, iclass 26, count 0 2006.197.08:02:20.52#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.197.08:02:20.52#ibcon#[28=FRQ=02,640.99\r\n] 2006.197.08:02:20.52#ibcon#*before write, iclass 26, count 0 2006.197.08:02:20.52#ibcon#enter sib2, iclass 26, count 0 2006.197.08:02:20.52#ibcon#flushed, iclass 26, count 0 2006.197.08:02:20.52#ibcon#about to write, iclass 26, count 0 2006.197.08:02:20.52#ibcon#wrote, iclass 26, count 0 2006.197.08:02:20.52#ibcon#about to read 3, iclass 26, count 0 2006.197.08:02:20.56#ibcon#read 3, iclass 26, count 0 2006.197.08:02:20.56#ibcon#about to read 4, iclass 26, count 0 2006.197.08:02:20.56#ibcon#read 4, iclass 26, count 0 2006.197.08:02:20.56#ibcon#about to read 5, iclass 26, count 0 2006.197.08:02:20.56#ibcon#read 5, iclass 26, count 0 2006.197.08:02:20.56#ibcon#about to read 6, iclass 26, count 0 2006.197.08:02:20.56#ibcon#read 6, iclass 26, count 0 2006.197.08:02:20.56#ibcon#end of sib2, iclass 26, count 0 2006.197.08:02:20.56#ibcon#*after write, iclass 26, count 0 2006.197.08:02:20.56#ibcon#*before return 0, iclass 26, count 0 2006.197.08:02:20.56#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.197.08:02:20.56#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.197.08:02:20.56#ibcon#about to clear, iclass 26 cls_cnt 0 2006.197.08:02:20.56#ibcon#cleared, iclass 26 cls_cnt 0 2006.197.08:02:20.56$vc4f8/vb=2,4 2006.197.08:02:20.56#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.197.08:02:20.56#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.197.08:02:20.56#ibcon#ireg 11 cls_cnt 2 2006.197.08:02:20.56#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.197.08:02:20.62#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.197.08:02:20.62#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.197.08:02:20.62#ibcon#enter wrdev, iclass 28, count 2 2006.197.08:02:20.62#ibcon#first serial, iclass 28, count 2 2006.197.08:02:20.62#ibcon#enter sib2, iclass 28, count 2 2006.197.08:02:20.62#ibcon#flushed, iclass 28, count 2 2006.197.08:02:20.62#ibcon#about to write, iclass 28, count 2 2006.197.08:02:20.62#ibcon#wrote, iclass 28, count 2 2006.197.08:02:20.62#ibcon#about to read 3, iclass 28, count 2 2006.197.08:02:20.64#ibcon#read 3, iclass 28, count 2 2006.197.08:02:20.64#ibcon#about to read 4, iclass 28, count 2 2006.197.08:02:20.64#ibcon#read 4, iclass 28, count 2 2006.197.08:02:20.64#ibcon#about to read 5, iclass 28, count 2 2006.197.08:02:20.64#ibcon#read 5, iclass 28, count 2 2006.197.08:02:20.64#ibcon#about to read 6, iclass 28, count 2 2006.197.08:02:20.64#ibcon#read 6, iclass 28, count 2 2006.197.08:02:20.64#ibcon#end of sib2, iclass 28, count 2 2006.197.08:02:20.64#ibcon#*mode == 0, iclass 28, count 2 2006.197.08:02:20.64#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.197.08:02:20.64#ibcon#[27=AT02-04\r\n] 2006.197.08:02:20.64#ibcon#*before write, iclass 28, count 2 2006.197.08:02:20.64#ibcon#enter sib2, iclass 28, count 2 2006.197.08:02:20.64#ibcon#flushed, iclass 28, count 2 2006.197.08:02:20.64#ibcon#about to write, iclass 28, count 2 2006.197.08:02:20.64#ibcon#wrote, iclass 28, count 2 2006.197.08:02:20.64#ibcon#about to read 3, iclass 28, count 2 2006.197.08:02:20.67#ibcon#read 3, iclass 28, count 2 2006.197.08:02:20.67#ibcon#about to read 4, iclass 28, count 2 2006.197.08:02:20.67#ibcon#read 4, iclass 28, count 2 2006.197.08:02:20.67#ibcon#about to read 5, iclass 28, count 2 2006.197.08:02:20.67#ibcon#read 5, iclass 28, count 2 2006.197.08:02:20.67#ibcon#about to read 6, iclass 28, count 2 2006.197.08:02:20.67#ibcon#read 6, iclass 28, count 2 2006.197.08:02:20.67#ibcon#end of sib2, iclass 28, count 2 2006.197.08:02:20.67#ibcon#*after write, iclass 28, count 2 2006.197.08:02:20.67#ibcon#*before return 0, iclass 28, count 2 2006.197.08:02:20.67#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.197.08:02:20.67#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.197.08:02:20.67#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.197.08:02:20.67#ibcon#ireg 7 cls_cnt 0 2006.197.08:02:20.67#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.197.08:02:20.79#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.197.08:02:20.79#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.197.08:02:20.79#ibcon#enter wrdev, iclass 28, count 0 2006.197.08:02:20.79#ibcon#first serial, iclass 28, count 0 2006.197.08:02:20.79#ibcon#enter sib2, iclass 28, count 0 2006.197.08:02:20.79#ibcon#flushed, iclass 28, count 0 2006.197.08:02:20.79#ibcon#about to write, iclass 28, count 0 2006.197.08:02:20.79#ibcon#wrote, iclass 28, count 0 2006.197.08:02:20.79#ibcon#about to read 3, iclass 28, count 0 2006.197.08:02:20.81#ibcon#read 3, iclass 28, count 0 2006.197.08:02:20.81#ibcon#about to read 4, iclass 28, count 0 2006.197.08:02:20.81#ibcon#read 4, iclass 28, count 0 2006.197.08:02:20.81#ibcon#about to read 5, iclass 28, count 0 2006.197.08:02:20.81#ibcon#read 5, iclass 28, count 0 2006.197.08:02:20.81#ibcon#about to read 6, iclass 28, count 0 2006.197.08:02:20.81#ibcon#read 6, iclass 28, count 0 2006.197.08:02:20.81#ibcon#end of sib2, iclass 28, count 0 2006.197.08:02:20.81#ibcon#*mode == 0, iclass 28, count 0 2006.197.08:02:20.81#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.197.08:02:20.81#ibcon#[27=USB\r\n] 2006.197.08:02:20.81#ibcon#*before write, iclass 28, count 0 2006.197.08:02:20.81#ibcon#enter sib2, iclass 28, count 0 2006.197.08:02:20.81#ibcon#flushed, iclass 28, count 0 2006.197.08:02:20.81#ibcon#about to write, iclass 28, count 0 2006.197.08:02:20.81#ibcon#wrote, iclass 28, count 0 2006.197.08:02:20.81#ibcon#about to read 3, iclass 28, count 0 2006.197.08:02:20.84#ibcon#read 3, iclass 28, count 0 2006.197.08:02:20.84#ibcon#about to read 4, iclass 28, count 0 2006.197.08:02:20.84#ibcon#read 4, iclass 28, count 0 2006.197.08:02:20.84#ibcon#about to read 5, iclass 28, count 0 2006.197.08:02:20.84#ibcon#read 5, iclass 28, count 0 2006.197.08:02:20.84#ibcon#about to read 6, iclass 28, count 0 2006.197.08:02:20.84#ibcon#read 6, iclass 28, count 0 2006.197.08:02:20.84#ibcon#end of sib2, iclass 28, count 0 2006.197.08:02:20.84#ibcon#*after write, iclass 28, count 0 2006.197.08:02:20.84#ibcon#*before return 0, iclass 28, count 0 2006.197.08:02:20.84#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.197.08:02:20.84#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.197.08:02:20.84#ibcon#about to clear, iclass 28 cls_cnt 0 2006.197.08:02:20.84#ibcon#cleared, iclass 28 cls_cnt 0 2006.197.08:02:20.84$vc4f8/vblo=3,656.99 2006.197.08:02:20.84#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.197.08:02:20.84#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.197.08:02:20.84#ibcon#ireg 17 cls_cnt 0 2006.197.08:02:20.84#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.197.08:02:20.84#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.197.08:02:20.84#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.197.08:02:20.84#ibcon#enter wrdev, iclass 30, count 0 2006.197.08:02:20.84#ibcon#first serial, iclass 30, count 0 2006.197.08:02:20.84#ibcon#enter sib2, iclass 30, count 0 2006.197.08:02:20.84#ibcon#flushed, iclass 30, count 0 2006.197.08:02:20.84#ibcon#about to write, iclass 30, count 0 2006.197.08:02:20.84#ibcon#wrote, iclass 30, count 0 2006.197.08:02:20.84#ibcon#about to read 3, iclass 30, count 0 2006.197.08:02:20.86#ibcon#read 3, iclass 30, count 0 2006.197.08:02:20.86#ibcon#about to read 4, iclass 30, count 0 2006.197.08:02:20.86#ibcon#read 4, iclass 30, count 0 2006.197.08:02:20.86#ibcon#about to read 5, iclass 30, count 0 2006.197.08:02:20.86#ibcon#read 5, iclass 30, count 0 2006.197.08:02:20.86#ibcon#about to read 6, iclass 30, count 0 2006.197.08:02:20.86#ibcon#read 6, iclass 30, count 0 2006.197.08:02:20.86#ibcon#end of sib2, iclass 30, count 0 2006.197.08:02:20.86#ibcon#*mode == 0, iclass 30, count 0 2006.197.08:02:20.86#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.197.08:02:20.86#ibcon#[28=FRQ=03,656.99\r\n] 2006.197.08:02:20.86#ibcon#*before write, iclass 30, count 0 2006.197.08:02:20.86#ibcon#enter sib2, iclass 30, count 0 2006.197.08:02:20.86#ibcon#flushed, iclass 30, count 0 2006.197.08:02:20.86#ibcon#about to write, iclass 30, count 0 2006.197.08:02:20.86#ibcon#wrote, iclass 30, count 0 2006.197.08:02:20.86#ibcon#about to read 3, iclass 30, count 0 2006.197.08:02:20.90#ibcon#read 3, iclass 30, count 0 2006.197.08:02:20.90#ibcon#about to read 4, iclass 30, count 0 2006.197.08:02:20.90#ibcon#read 4, iclass 30, count 0 2006.197.08:02:20.90#ibcon#about to read 5, iclass 30, count 0 2006.197.08:02:20.90#ibcon#read 5, iclass 30, count 0 2006.197.08:02:20.90#ibcon#about to read 6, iclass 30, count 0 2006.197.08:02:20.90#ibcon#read 6, iclass 30, count 0 2006.197.08:02:20.90#ibcon#end of sib2, iclass 30, count 0 2006.197.08:02:20.90#ibcon#*after write, iclass 30, count 0 2006.197.08:02:20.90#ibcon#*before return 0, iclass 30, count 0 2006.197.08:02:20.90#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.197.08:02:20.90#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.197.08:02:20.90#ibcon#about to clear, iclass 30 cls_cnt 0 2006.197.08:02:20.90#ibcon#cleared, iclass 30 cls_cnt 0 2006.197.08:02:20.90$vc4f8/vb=3,4 2006.197.08:02:20.90#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.197.08:02:20.90#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.197.08:02:20.90#ibcon#ireg 11 cls_cnt 2 2006.197.08:02:20.90#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.197.08:02:20.96#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.197.08:02:20.96#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.197.08:02:20.96#ibcon#enter wrdev, iclass 32, count 2 2006.197.08:02:20.96#ibcon#first serial, iclass 32, count 2 2006.197.08:02:20.96#ibcon#enter sib2, iclass 32, count 2 2006.197.08:02:20.96#ibcon#flushed, iclass 32, count 2 2006.197.08:02:20.96#ibcon#about to write, iclass 32, count 2 2006.197.08:02:20.96#ibcon#wrote, iclass 32, count 2 2006.197.08:02:20.96#ibcon#about to read 3, iclass 32, count 2 2006.197.08:02:20.98#ibcon#read 3, iclass 32, count 2 2006.197.08:02:20.98#ibcon#about to read 4, iclass 32, count 2 2006.197.08:02:20.98#ibcon#read 4, iclass 32, count 2 2006.197.08:02:20.98#ibcon#about to read 5, iclass 32, count 2 2006.197.08:02:20.98#ibcon#read 5, iclass 32, count 2 2006.197.08:02:20.98#ibcon#about to read 6, iclass 32, count 2 2006.197.08:02:20.98#ibcon#read 6, iclass 32, count 2 2006.197.08:02:20.98#ibcon#end of sib2, iclass 32, count 2 2006.197.08:02:20.98#ibcon#*mode == 0, iclass 32, count 2 2006.197.08:02:20.98#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.197.08:02:20.98#ibcon#[27=AT03-04\r\n] 2006.197.08:02:20.98#ibcon#*before write, iclass 32, count 2 2006.197.08:02:20.98#ibcon#enter sib2, iclass 32, count 2 2006.197.08:02:20.98#ibcon#flushed, iclass 32, count 2 2006.197.08:02:20.98#ibcon#about to write, iclass 32, count 2 2006.197.08:02:20.98#ibcon#wrote, iclass 32, count 2 2006.197.08:02:20.98#ibcon#about to read 3, iclass 32, count 2 2006.197.08:02:21.01#ibcon#read 3, iclass 32, count 2 2006.197.08:02:21.01#ibcon#about to read 4, iclass 32, count 2 2006.197.08:02:21.01#ibcon#read 4, iclass 32, count 2 2006.197.08:02:21.01#ibcon#about to read 5, iclass 32, count 2 2006.197.08:02:21.01#ibcon#read 5, iclass 32, count 2 2006.197.08:02:21.01#ibcon#about to read 6, iclass 32, count 2 2006.197.08:02:21.01#ibcon#read 6, iclass 32, count 2 2006.197.08:02:21.01#ibcon#end of sib2, iclass 32, count 2 2006.197.08:02:21.01#ibcon#*after write, iclass 32, count 2 2006.197.08:02:21.01#ibcon#*before return 0, iclass 32, count 2 2006.197.08:02:21.01#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.197.08:02:21.01#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.197.08:02:21.01#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.197.08:02:21.01#ibcon#ireg 7 cls_cnt 0 2006.197.08:02:21.01#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.197.08:02:21.13#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.197.08:02:21.13#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.197.08:02:21.13#ibcon#enter wrdev, iclass 32, count 0 2006.197.08:02:21.13#ibcon#first serial, iclass 32, count 0 2006.197.08:02:21.13#ibcon#enter sib2, iclass 32, count 0 2006.197.08:02:21.13#ibcon#flushed, iclass 32, count 0 2006.197.08:02:21.13#ibcon#about to write, iclass 32, count 0 2006.197.08:02:21.13#ibcon#wrote, iclass 32, count 0 2006.197.08:02:21.13#ibcon#about to read 3, iclass 32, count 0 2006.197.08:02:21.15#ibcon#read 3, iclass 32, count 0 2006.197.08:02:21.15#ibcon#about to read 4, iclass 32, count 0 2006.197.08:02:21.15#ibcon#read 4, iclass 32, count 0 2006.197.08:02:21.15#ibcon#about to read 5, iclass 32, count 0 2006.197.08:02:21.15#ibcon#read 5, iclass 32, count 0 2006.197.08:02:21.15#ibcon#about to read 6, iclass 32, count 0 2006.197.08:02:21.15#ibcon#read 6, iclass 32, count 0 2006.197.08:02:21.15#ibcon#end of sib2, iclass 32, count 0 2006.197.08:02:21.15#ibcon#*mode == 0, iclass 32, count 0 2006.197.08:02:21.15#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.197.08:02:21.15#ibcon#[27=USB\r\n] 2006.197.08:02:21.15#ibcon#*before write, iclass 32, count 0 2006.197.08:02:21.15#ibcon#enter sib2, iclass 32, count 0 2006.197.08:02:21.15#ibcon#flushed, iclass 32, count 0 2006.197.08:02:21.15#ibcon#about to write, iclass 32, count 0 2006.197.08:02:21.15#ibcon#wrote, iclass 32, count 0 2006.197.08:02:21.15#ibcon#about to read 3, iclass 32, count 0 2006.197.08:02:21.18#ibcon#read 3, iclass 32, count 0 2006.197.08:02:21.18#ibcon#about to read 4, iclass 32, count 0 2006.197.08:02:21.18#ibcon#read 4, iclass 32, count 0 2006.197.08:02:21.18#ibcon#about to read 5, iclass 32, count 0 2006.197.08:02:21.18#ibcon#read 5, iclass 32, count 0 2006.197.08:02:21.18#ibcon#about to read 6, iclass 32, count 0 2006.197.08:02:21.18#ibcon#read 6, iclass 32, count 0 2006.197.08:02:21.18#ibcon#end of sib2, iclass 32, count 0 2006.197.08:02:21.18#ibcon#*after write, iclass 32, count 0 2006.197.08:02:21.18#ibcon#*before return 0, iclass 32, count 0 2006.197.08:02:21.18#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.197.08:02:21.18#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.197.08:02:21.18#ibcon#about to clear, iclass 32 cls_cnt 0 2006.197.08:02:21.18#ibcon#cleared, iclass 32 cls_cnt 0 2006.197.08:02:21.18$vc4f8/vblo=4,712.99 2006.197.08:02:21.18#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.197.08:02:21.18#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.197.08:02:21.18#ibcon#ireg 17 cls_cnt 0 2006.197.08:02:21.18#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.197.08:02:21.18#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.197.08:02:21.18#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.197.08:02:21.18#ibcon#enter wrdev, iclass 34, count 0 2006.197.08:02:21.18#ibcon#first serial, iclass 34, count 0 2006.197.08:02:21.18#ibcon#enter sib2, iclass 34, count 0 2006.197.08:02:21.18#ibcon#flushed, iclass 34, count 0 2006.197.08:02:21.18#ibcon#about to write, iclass 34, count 0 2006.197.08:02:21.18#ibcon#wrote, iclass 34, count 0 2006.197.08:02:21.18#ibcon#about to read 3, iclass 34, count 0 2006.197.08:02:21.20#ibcon#read 3, iclass 34, count 0 2006.197.08:02:21.20#ibcon#about to read 4, iclass 34, count 0 2006.197.08:02:21.20#ibcon#read 4, iclass 34, count 0 2006.197.08:02:21.20#ibcon#about to read 5, iclass 34, count 0 2006.197.08:02:21.20#ibcon#read 5, iclass 34, count 0 2006.197.08:02:21.20#ibcon#about to read 6, iclass 34, count 0 2006.197.08:02:21.20#ibcon#read 6, iclass 34, count 0 2006.197.08:02:21.20#ibcon#end of sib2, iclass 34, count 0 2006.197.08:02:21.20#ibcon#*mode == 0, iclass 34, count 0 2006.197.08:02:21.20#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.197.08:02:21.20#ibcon#[28=FRQ=04,712.99\r\n] 2006.197.08:02:21.20#ibcon#*before write, iclass 34, count 0 2006.197.08:02:21.20#ibcon#enter sib2, iclass 34, count 0 2006.197.08:02:21.20#ibcon#flushed, iclass 34, count 0 2006.197.08:02:21.20#ibcon#about to write, iclass 34, count 0 2006.197.08:02:21.20#ibcon#wrote, iclass 34, count 0 2006.197.08:02:21.20#ibcon#about to read 3, iclass 34, count 0 2006.197.08:02:21.24#ibcon#read 3, iclass 34, count 0 2006.197.08:02:21.24#ibcon#about to read 4, iclass 34, count 0 2006.197.08:02:21.24#ibcon#read 4, iclass 34, count 0 2006.197.08:02:21.24#ibcon#about to read 5, iclass 34, count 0 2006.197.08:02:21.24#ibcon#read 5, iclass 34, count 0 2006.197.08:02:21.24#ibcon#about to read 6, iclass 34, count 0 2006.197.08:02:21.24#ibcon#read 6, iclass 34, count 0 2006.197.08:02:21.24#ibcon#end of sib2, iclass 34, count 0 2006.197.08:02:21.24#ibcon#*after write, iclass 34, count 0 2006.197.08:02:21.24#ibcon#*before return 0, iclass 34, count 0 2006.197.08:02:21.24#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.197.08:02:21.24#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.197.08:02:21.24#ibcon#about to clear, iclass 34 cls_cnt 0 2006.197.08:02:21.24#ibcon#cleared, iclass 34 cls_cnt 0 2006.197.08:02:21.24$vc4f8/vb=4,4 2006.197.08:02:21.24#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.197.08:02:21.24#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.197.08:02:21.24#ibcon#ireg 11 cls_cnt 2 2006.197.08:02:21.24#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.197.08:02:21.30#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.197.08:02:21.30#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.197.08:02:21.30#ibcon#enter wrdev, iclass 36, count 2 2006.197.08:02:21.30#ibcon#first serial, iclass 36, count 2 2006.197.08:02:21.30#ibcon#enter sib2, iclass 36, count 2 2006.197.08:02:21.30#ibcon#flushed, iclass 36, count 2 2006.197.08:02:21.30#ibcon#about to write, iclass 36, count 2 2006.197.08:02:21.30#ibcon#wrote, iclass 36, count 2 2006.197.08:02:21.30#ibcon#about to read 3, iclass 36, count 2 2006.197.08:02:21.32#ibcon#read 3, iclass 36, count 2 2006.197.08:02:21.32#ibcon#about to read 4, iclass 36, count 2 2006.197.08:02:21.32#ibcon#read 4, iclass 36, count 2 2006.197.08:02:21.32#ibcon#about to read 5, iclass 36, count 2 2006.197.08:02:21.32#ibcon#read 5, iclass 36, count 2 2006.197.08:02:21.32#ibcon#about to read 6, iclass 36, count 2 2006.197.08:02:21.32#ibcon#read 6, iclass 36, count 2 2006.197.08:02:21.32#ibcon#end of sib2, iclass 36, count 2 2006.197.08:02:21.32#ibcon#*mode == 0, iclass 36, count 2 2006.197.08:02:21.32#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.197.08:02:21.32#ibcon#[27=AT04-04\r\n] 2006.197.08:02:21.32#ibcon#*before write, iclass 36, count 2 2006.197.08:02:21.32#ibcon#enter sib2, iclass 36, count 2 2006.197.08:02:21.32#ibcon#flushed, iclass 36, count 2 2006.197.08:02:21.32#ibcon#about to write, iclass 36, count 2 2006.197.08:02:21.32#ibcon#wrote, iclass 36, count 2 2006.197.08:02:21.32#ibcon#about to read 3, iclass 36, count 2 2006.197.08:02:21.35#ibcon#read 3, iclass 36, count 2 2006.197.08:02:21.35#ibcon#about to read 4, iclass 36, count 2 2006.197.08:02:21.35#ibcon#read 4, iclass 36, count 2 2006.197.08:02:21.35#ibcon#about to read 5, iclass 36, count 2 2006.197.08:02:21.35#ibcon#read 5, iclass 36, count 2 2006.197.08:02:21.35#ibcon#about to read 6, iclass 36, count 2 2006.197.08:02:21.35#ibcon#read 6, iclass 36, count 2 2006.197.08:02:21.35#ibcon#end of sib2, iclass 36, count 2 2006.197.08:02:21.35#ibcon#*after write, iclass 36, count 2 2006.197.08:02:21.35#ibcon#*before return 0, iclass 36, count 2 2006.197.08:02:21.35#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.197.08:02:21.35#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.197.08:02:21.35#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.197.08:02:21.35#ibcon#ireg 7 cls_cnt 0 2006.197.08:02:21.35#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.197.08:02:21.47#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.197.08:02:21.47#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.197.08:02:21.47#ibcon#enter wrdev, iclass 36, count 0 2006.197.08:02:21.47#ibcon#first serial, iclass 36, count 0 2006.197.08:02:21.47#ibcon#enter sib2, iclass 36, count 0 2006.197.08:02:21.47#ibcon#flushed, iclass 36, count 0 2006.197.08:02:21.47#ibcon#about to write, iclass 36, count 0 2006.197.08:02:21.47#ibcon#wrote, iclass 36, count 0 2006.197.08:02:21.47#ibcon#about to read 3, iclass 36, count 0 2006.197.08:02:21.49#ibcon#read 3, iclass 36, count 0 2006.197.08:02:21.49#ibcon#about to read 4, iclass 36, count 0 2006.197.08:02:21.49#ibcon#read 4, iclass 36, count 0 2006.197.08:02:21.49#ibcon#about to read 5, iclass 36, count 0 2006.197.08:02:21.49#ibcon#read 5, iclass 36, count 0 2006.197.08:02:21.49#ibcon#about to read 6, iclass 36, count 0 2006.197.08:02:21.49#ibcon#read 6, iclass 36, count 0 2006.197.08:02:21.49#ibcon#end of sib2, iclass 36, count 0 2006.197.08:02:21.49#ibcon#*mode == 0, iclass 36, count 0 2006.197.08:02:21.49#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.197.08:02:21.49#ibcon#[27=USB\r\n] 2006.197.08:02:21.49#ibcon#*before write, iclass 36, count 0 2006.197.08:02:21.49#ibcon#enter sib2, iclass 36, count 0 2006.197.08:02:21.49#ibcon#flushed, iclass 36, count 0 2006.197.08:02:21.49#ibcon#about to write, iclass 36, count 0 2006.197.08:02:21.49#ibcon#wrote, iclass 36, count 0 2006.197.08:02:21.49#ibcon#about to read 3, iclass 36, count 0 2006.197.08:02:21.52#ibcon#read 3, iclass 36, count 0 2006.197.08:02:21.52#ibcon#about to read 4, iclass 36, count 0 2006.197.08:02:21.52#ibcon#read 4, iclass 36, count 0 2006.197.08:02:21.52#ibcon#about to read 5, iclass 36, count 0 2006.197.08:02:21.52#ibcon#read 5, iclass 36, count 0 2006.197.08:02:21.52#ibcon#about to read 6, iclass 36, count 0 2006.197.08:02:21.52#ibcon#read 6, iclass 36, count 0 2006.197.08:02:21.52#ibcon#end of sib2, iclass 36, count 0 2006.197.08:02:21.52#ibcon#*after write, iclass 36, count 0 2006.197.08:02:21.52#ibcon#*before return 0, iclass 36, count 0 2006.197.08:02:21.52#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.197.08:02:21.52#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.197.08:02:21.52#ibcon#about to clear, iclass 36 cls_cnt 0 2006.197.08:02:21.52#ibcon#cleared, iclass 36 cls_cnt 0 2006.197.08:02:21.52$vc4f8/vblo=5,744.99 2006.197.08:02:21.52#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.197.08:02:21.52#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.197.08:02:21.52#ibcon#ireg 17 cls_cnt 0 2006.197.08:02:21.52#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.197.08:02:21.52#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.197.08:02:21.52#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.197.08:02:21.52#ibcon#enter wrdev, iclass 38, count 0 2006.197.08:02:21.52#ibcon#first serial, iclass 38, count 0 2006.197.08:02:21.52#ibcon#enter sib2, iclass 38, count 0 2006.197.08:02:21.52#ibcon#flushed, iclass 38, count 0 2006.197.08:02:21.52#ibcon#about to write, iclass 38, count 0 2006.197.08:02:21.52#ibcon#wrote, iclass 38, count 0 2006.197.08:02:21.52#ibcon#about to read 3, iclass 38, count 0 2006.197.08:02:21.54#ibcon#read 3, iclass 38, count 0 2006.197.08:02:21.54#ibcon#about to read 4, iclass 38, count 0 2006.197.08:02:21.54#ibcon#read 4, iclass 38, count 0 2006.197.08:02:21.54#ibcon#about to read 5, iclass 38, count 0 2006.197.08:02:21.54#ibcon#read 5, iclass 38, count 0 2006.197.08:02:21.54#ibcon#about to read 6, iclass 38, count 0 2006.197.08:02:21.54#ibcon#read 6, iclass 38, count 0 2006.197.08:02:21.54#ibcon#end of sib2, iclass 38, count 0 2006.197.08:02:21.54#ibcon#*mode == 0, iclass 38, count 0 2006.197.08:02:21.54#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.197.08:02:21.54#ibcon#[28=FRQ=05,744.99\r\n] 2006.197.08:02:21.54#ibcon#*before write, iclass 38, count 0 2006.197.08:02:21.54#ibcon#enter sib2, iclass 38, count 0 2006.197.08:02:21.54#ibcon#flushed, iclass 38, count 0 2006.197.08:02:21.54#ibcon#about to write, iclass 38, count 0 2006.197.08:02:21.54#ibcon#wrote, iclass 38, count 0 2006.197.08:02:21.54#ibcon#about to read 3, iclass 38, count 0 2006.197.08:02:21.58#ibcon#read 3, iclass 38, count 0 2006.197.08:02:21.58#ibcon#about to read 4, iclass 38, count 0 2006.197.08:02:21.58#ibcon#read 4, iclass 38, count 0 2006.197.08:02:21.58#ibcon#about to read 5, iclass 38, count 0 2006.197.08:02:21.58#ibcon#read 5, iclass 38, count 0 2006.197.08:02:21.58#ibcon#about to read 6, iclass 38, count 0 2006.197.08:02:21.58#ibcon#read 6, iclass 38, count 0 2006.197.08:02:21.58#ibcon#end of sib2, iclass 38, count 0 2006.197.08:02:21.58#ibcon#*after write, iclass 38, count 0 2006.197.08:02:21.58#ibcon#*before return 0, iclass 38, count 0 2006.197.08:02:21.58#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.197.08:02:21.58#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.197.08:02:21.58#ibcon#about to clear, iclass 38 cls_cnt 0 2006.197.08:02:21.58#ibcon#cleared, iclass 38 cls_cnt 0 2006.197.08:02:21.58$vc4f8/vb=5,4 2006.197.08:02:21.58#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.197.08:02:21.58#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.197.08:02:21.58#ibcon#ireg 11 cls_cnt 2 2006.197.08:02:21.58#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.197.08:02:21.64#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.197.08:02:21.64#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.197.08:02:21.64#ibcon#enter wrdev, iclass 40, count 2 2006.197.08:02:21.64#ibcon#first serial, iclass 40, count 2 2006.197.08:02:21.64#ibcon#enter sib2, iclass 40, count 2 2006.197.08:02:21.64#ibcon#flushed, iclass 40, count 2 2006.197.08:02:21.64#ibcon#about to write, iclass 40, count 2 2006.197.08:02:21.64#ibcon#wrote, iclass 40, count 2 2006.197.08:02:21.64#ibcon#about to read 3, iclass 40, count 2 2006.197.08:02:21.66#ibcon#read 3, iclass 40, count 2 2006.197.08:02:21.66#ibcon#about to read 4, iclass 40, count 2 2006.197.08:02:21.66#ibcon#read 4, iclass 40, count 2 2006.197.08:02:21.66#ibcon#about to read 5, iclass 40, count 2 2006.197.08:02:21.66#ibcon#read 5, iclass 40, count 2 2006.197.08:02:21.66#ibcon#about to read 6, iclass 40, count 2 2006.197.08:02:21.66#ibcon#read 6, iclass 40, count 2 2006.197.08:02:21.66#ibcon#end of sib2, iclass 40, count 2 2006.197.08:02:21.66#ibcon#*mode == 0, iclass 40, count 2 2006.197.08:02:21.66#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.197.08:02:21.66#ibcon#[27=AT05-04\r\n] 2006.197.08:02:21.66#ibcon#*before write, iclass 40, count 2 2006.197.08:02:21.66#ibcon#enter sib2, iclass 40, count 2 2006.197.08:02:21.66#ibcon#flushed, iclass 40, count 2 2006.197.08:02:21.66#ibcon#about to write, iclass 40, count 2 2006.197.08:02:21.66#ibcon#wrote, iclass 40, count 2 2006.197.08:02:21.66#ibcon#about to read 3, iclass 40, count 2 2006.197.08:02:21.69#ibcon#read 3, iclass 40, count 2 2006.197.08:02:21.69#ibcon#about to read 4, iclass 40, count 2 2006.197.08:02:21.69#ibcon#read 4, iclass 40, count 2 2006.197.08:02:21.69#ibcon#about to read 5, iclass 40, count 2 2006.197.08:02:21.69#ibcon#read 5, iclass 40, count 2 2006.197.08:02:21.69#ibcon#about to read 6, iclass 40, count 2 2006.197.08:02:21.69#ibcon#read 6, iclass 40, count 2 2006.197.08:02:21.69#ibcon#end of sib2, iclass 40, count 2 2006.197.08:02:21.69#ibcon#*after write, iclass 40, count 2 2006.197.08:02:21.69#ibcon#*before return 0, iclass 40, count 2 2006.197.08:02:21.69#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.197.08:02:21.69#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.197.08:02:21.69#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.197.08:02:21.69#ibcon#ireg 7 cls_cnt 0 2006.197.08:02:21.69#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.197.08:02:21.81#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.197.08:02:21.81#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.197.08:02:21.81#ibcon#enter wrdev, iclass 40, count 0 2006.197.08:02:21.81#ibcon#first serial, iclass 40, count 0 2006.197.08:02:21.81#ibcon#enter sib2, iclass 40, count 0 2006.197.08:02:21.81#ibcon#flushed, iclass 40, count 0 2006.197.08:02:21.81#ibcon#about to write, iclass 40, count 0 2006.197.08:02:21.81#ibcon#wrote, iclass 40, count 0 2006.197.08:02:21.81#ibcon#about to read 3, iclass 40, count 0 2006.197.08:02:21.83#ibcon#read 3, iclass 40, count 0 2006.197.08:02:21.83#ibcon#about to read 4, iclass 40, count 0 2006.197.08:02:21.83#ibcon#read 4, iclass 40, count 0 2006.197.08:02:21.83#ibcon#about to read 5, iclass 40, count 0 2006.197.08:02:21.83#ibcon#read 5, iclass 40, count 0 2006.197.08:02:21.83#ibcon#about to read 6, iclass 40, count 0 2006.197.08:02:21.83#ibcon#read 6, iclass 40, count 0 2006.197.08:02:21.83#ibcon#end of sib2, iclass 40, count 0 2006.197.08:02:21.83#ibcon#*mode == 0, iclass 40, count 0 2006.197.08:02:21.83#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.197.08:02:21.83#ibcon#[27=USB\r\n] 2006.197.08:02:21.83#ibcon#*before write, iclass 40, count 0 2006.197.08:02:21.83#ibcon#enter sib2, iclass 40, count 0 2006.197.08:02:21.83#ibcon#flushed, iclass 40, count 0 2006.197.08:02:21.83#ibcon#about to write, iclass 40, count 0 2006.197.08:02:21.83#ibcon#wrote, iclass 40, count 0 2006.197.08:02:21.83#ibcon#about to read 3, iclass 40, count 0 2006.197.08:02:21.86#ibcon#read 3, iclass 40, count 0 2006.197.08:02:21.86#ibcon#about to read 4, iclass 40, count 0 2006.197.08:02:21.86#ibcon#read 4, iclass 40, count 0 2006.197.08:02:21.86#ibcon#about to read 5, iclass 40, count 0 2006.197.08:02:21.86#ibcon#read 5, iclass 40, count 0 2006.197.08:02:21.86#ibcon#about to read 6, iclass 40, count 0 2006.197.08:02:21.86#ibcon#read 6, iclass 40, count 0 2006.197.08:02:21.86#ibcon#end of sib2, iclass 40, count 0 2006.197.08:02:21.86#ibcon#*after write, iclass 40, count 0 2006.197.08:02:21.86#ibcon#*before return 0, iclass 40, count 0 2006.197.08:02:21.86#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.197.08:02:21.86#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.197.08:02:21.86#ibcon#about to clear, iclass 40 cls_cnt 0 2006.197.08:02:21.86#ibcon#cleared, iclass 40 cls_cnt 0 2006.197.08:02:21.86$vc4f8/vblo=6,752.99 2006.197.08:02:21.86#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.197.08:02:21.86#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.197.08:02:21.86#ibcon#ireg 17 cls_cnt 0 2006.197.08:02:21.86#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.197.08:02:21.86#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.197.08:02:21.86#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.197.08:02:21.86#ibcon#enter wrdev, iclass 4, count 0 2006.197.08:02:21.86#ibcon#first serial, iclass 4, count 0 2006.197.08:02:21.86#ibcon#enter sib2, iclass 4, count 0 2006.197.08:02:21.86#ibcon#flushed, iclass 4, count 0 2006.197.08:02:21.86#ibcon#about to write, iclass 4, count 0 2006.197.08:02:21.86#ibcon#wrote, iclass 4, count 0 2006.197.08:02:21.86#ibcon#about to read 3, iclass 4, count 0 2006.197.08:02:21.88#ibcon#read 3, iclass 4, count 0 2006.197.08:02:21.88#ibcon#about to read 4, iclass 4, count 0 2006.197.08:02:21.88#ibcon#read 4, iclass 4, count 0 2006.197.08:02:21.88#ibcon#about to read 5, iclass 4, count 0 2006.197.08:02:21.88#ibcon#read 5, iclass 4, count 0 2006.197.08:02:21.88#ibcon#about to read 6, iclass 4, count 0 2006.197.08:02:21.88#ibcon#read 6, iclass 4, count 0 2006.197.08:02:21.88#ibcon#end of sib2, iclass 4, count 0 2006.197.08:02:21.88#ibcon#*mode == 0, iclass 4, count 0 2006.197.08:02:21.88#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.197.08:02:21.88#ibcon#[28=FRQ=06,752.99\r\n] 2006.197.08:02:21.88#ibcon#*before write, iclass 4, count 0 2006.197.08:02:21.88#ibcon#enter sib2, iclass 4, count 0 2006.197.08:02:21.88#ibcon#flushed, iclass 4, count 0 2006.197.08:02:21.88#ibcon#about to write, iclass 4, count 0 2006.197.08:02:21.88#ibcon#wrote, iclass 4, count 0 2006.197.08:02:21.88#ibcon#about to read 3, iclass 4, count 0 2006.197.08:02:21.92#ibcon#read 3, iclass 4, count 0 2006.197.08:02:21.92#ibcon#about to read 4, iclass 4, count 0 2006.197.08:02:21.92#ibcon#read 4, iclass 4, count 0 2006.197.08:02:21.92#ibcon#about to read 5, iclass 4, count 0 2006.197.08:02:21.92#ibcon#read 5, iclass 4, count 0 2006.197.08:02:21.92#ibcon#about to read 6, iclass 4, count 0 2006.197.08:02:21.92#ibcon#read 6, iclass 4, count 0 2006.197.08:02:21.92#ibcon#end of sib2, iclass 4, count 0 2006.197.08:02:21.92#ibcon#*after write, iclass 4, count 0 2006.197.08:02:21.92#ibcon#*before return 0, iclass 4, count 0 2006.197.08:02:21.92#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.197.08:02:21.92#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.197.08:02:21.92#ibcon#about to clear, iclass 4 cls_cnt 0 2006.197.08:02:21.92#ibcon#cleared, iclass 4 cls_cnt 0 2006.197.08:02:21.92$vc4f8/vb=6,4 2006.197.08:02:21.92#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.197.08:02:21.92#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.197.08:02:21.92#ibcon#ireg 11 cls_cnt 2 2006.197.08:02:21.92#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.197.08:02:21.98#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.197.08:02:21.98#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.197.08:02:21.98#ibcon#enter wrdev, iclass 6, count 2 2006.197.08:02:21.98#ibcon#first serial, iclass 6, count 2 2006.197.08:02:21.98#ibcon#enter sib2, iclass 6, count 2 2006.197.08:02:21.98#ibcon#flushed, iclass 6, count 2 2006.197.08:02:21.98#ibcon#about to write, iclass 6, count 2 2006.197.08:02:21.98#ibcon#wrote, iclass 6, count 2 2006.197.08:02:21.98#ibcon#about to read 3, iclass 6, count 2 2006.197.08:02:22.00#ibcon#read 3, iclass 6, count 2 2006.197.08:02:22.00#ibcon#about to read 4, iclass 6, count 2 2006.197.08:02:22.00#ibcon#read 4, iclass 6, count 2 2006.197.08:02:22.00#ibcon#about to read 5, iclass 6, count 2 2006.197.08:02:22.00#ibcon#read 5, iclass 6, count 2 2006.197.08:02:22.00#ibcon#about to read 6, iclass 6, count 2 2006.197.08:02:22.00#ibcon#read 6, iclass 6, count 2 2006.197.08:02:22.00#ibcon#end of sib2, iclass 6, count 2 2006.197.08:02:22.00#ibcon#*mode == 0, iclass 6, count 2 2006.197.08:02:22.00#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.197.08:02:22.00#ibcon#[27=AT06-04\r\n] 2006.197.08:02:22.00#ibcon#*before write, iclass 6, count 2 2006.197.08:02:22.00#ibcon#enter sib2, iclass 6, count 2 2006.197.08:02:22.00#ibcon#flushed, iclass 6, count 2 2006.197.08:02:22.00#ibcon#about to write, iclass 6, count 2 2006.197.08:02:22.00#ibcon#wrote, iclass 6, count 2 2006.197.08:02:22.00#ibcon#about to read 3, iclass 6, count 2 2006.197.08:02:22.03#ibcon#read 3, iclass 6, count 2 2006.197.08:02:22.03#ibcon#about to read 4, iclass 6, count 2 2006.197.08:02:22.03#ibcon#read 4, iclass 6, count 2 2006.197.08:02:22.03#ibcon#about to read 5, iclass 6, count 2 2006.197.08:02:22.03#ibcon#read 5, iclass 6, count 2 2006.197.08:02:22.03#ibcon#about to read 6, iclass 6, count 2 2006.197.08:02:22.03#ibcon#read 6, iclass 6, count 2 2006.197.08:02:22.03#ibcon#end of sib2, iclass 6, count 2 2006.197.08:02:22.03#ibcon#*after write, iclass 6, count 2 2006.197.08:02:22.03#ibcon#*before return 0, iclass 6, count 2 2006.197.08:02:22.03#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.197.08:02:22.03#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.197.08:02:22.03#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.197.08:02:22.03#ibcon#ireg 7 cls_cnt 0 2006.197.08:02:22.03#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.197.08:02:22.15#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.197.08:02:22.15#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.197.08:02:22.15#ibcon#enter wrdev, iclass 6, count 0 2006.197.08:02:22.15#ibcon#first serial, iclass 6, count 0 2006.197.08:02:22.15#ibcon#enter sib2, iclass 6, count 0 2006.197.08:02:22.15#ibcon#flushed, iclass 6, count 0 2006.197.08:02:22.15#ibcon#about to write, iclass 6, count 0 2006.197.08:02:22.15#ibcon#wrote, iclass 6, count 0 2006.197.08:02:22.15#ibcon#about to read 3, iclass 6, count 0 2006.197.08:02:22.17#ibcon#read 3, iclass 6, count 0 2006.197.08:02:22.17#ibcon#about to read 4, iclass 6, count 0 2006.197.08:02:22.17#ibcon#read 4, iclass 6, count 0 2006.197.08:02:22.17#ibcon#about to read 5, iclass 6, count 0 2006.197.08:02:22.17#ibcon#read 5, iclass 6, count 0 2006.197.08:02:22.17#ibcon#about to read 6, iclass 6, count 0 2006.197.08:02:22.17#ibcon#read 6, iclass 6, count 0 2006.197.08:02:22.17#ibcon#end of sib2, iclass 6, count 0 2006.197.08:02:22.17#ibcon#*mode == 0, iclass 6, count 0 2006.197.08:02:22.17#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.197.08:02:22.17#ibcon#[27=USB\r\n] 2006.197.08:02:22.17#ibcon#*before write, iclass 6, count 0 2006.197.08:02:22.17#ibcon#enter sib2, iclass 6, count 0 2006.197.08:02:22.17#ibcon#flushed, iclass 6, count 0 2006.197.08:02:22.17#ibcon#about to write, iclass 6, count 0 2006.197.08:02:22.17#ibcon#wrote, iclass 6, count 0 2006.197.08:02:22.17#ibcon#about to read 3, iclass 6, count 0 2006.197.08:02:22.20#ibcon#read 3, iclass 6, count 0 2006.197.08:02:22.20#ibcon#about to read 4, iclass 6, count 0 2006.197.08:02:22.20#ibcon#read 4, iclass 6, count 0 2006.197.08:02:22.20#ibcon#about to read 5, iclass 6, count 0 2006.197.08:02:22.20#ibcon#read 5, iclass 6, count 0 2006.197.08:02:22.20#ibcon#about to read 6, iclass 6, count 0 2006.197.08:02:22.20#ibcon#read 6, iclass 6, count 0 2006.197.08:02:22.20#ibcon#end of sib2, iclass 6, count 0 2006.197.08:02:22.20#ibcon#*after write, iclass 6, count 0 2006.197.08:02:22.20#ibcon#*before return 0, iclass 6, count 0 2006.197.08:02:22.20#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.197.08:02:22.20#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.197.08:02:22.20#ibcon#about to clear, iclass 6 cls_cnt 0 2006.197.08:02:22.20#ibcon#cleared, iclass 6 cls_cnt 0 2006.197.08:02:22.20$vc4f8/vabw=wide 2006.197.08:02:22.20#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.197.08:02:22.20#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.197.08:02:22.20#ibcon#ireg 8 cls_cnt 0 2006.197.08:02:22.20#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.197.08:02:22.20#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.197.08:02:22.20#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.197.08:02:22.20#ibcon#enter wrdev, iclass 10, count 0 2006.197.08:02:22.20#ibcon#first serial, iclass 10, count 0 2006.197.08:02:22.20#ibcon#enter sib2, iclass 10, count 0 2006.197.08:02:22.20#ibcon#flushed, iclass 10, count 0 2006.197.08:02:22.20#ibcon#about to write, iclass 10, count 0 2006.197.08:02:22.20#ibcon#wrote, iclass 10, count 0 2006.197.08:02:22.20#ibcon#about to read 3, iclass 10, count 0 2006.197.08:02:22.22#ibcon#read 3, iclass 10, count 0 2006.197.08:02:22.22#ibcon#about to read 4, iclass 10, count 0 2006.197.08:02:22.22#ibcon#read 4, iclass 10, count 0 2006.197.08:02:22.22#ibcon#about to read 5, iclass 10, count 0 2006.197.08:02:22.22#ibcon#read 5, iclass 10, count 0 2006.197.08:02:22.22#ibcon#about to read 6, iclass 10, count 0 2006.197.08:02:22.22#ibcon#read 6, iclass 10, count 0 2006.197.08:02:22.22#ibcon#end of sib2, iclass 10, count 0 2006.197.08:02:22.22#ibcon#*mode == 0, iclass 10, count 0 2006.197.08:02:22.22#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.197.08:02:22.22#ibcon#[25=BW32\r\n] 2006.197.08:02:22.22#ibcon#*before write, iclass 10, count 0 2006.197.08:02:22.22#ibcon#enter sib2, iclass 10, count 0 2006.197.08:02:22.22#ibcon#flushed, iclass 10, count 0 2006.197.08:02:22.22#ibcon#about to write, iclass 10, count 0 2006.197.08:02:22.22#ibcon#wrote, iclass 10, count 0 2006.197.08:02:22.22#ibcon#about to read 3, iclass 10, count 0 2006.197.08:02:22.25#ibcon#read 3, iclass 10, count 0 2006.197.08:02:22.25#ibcon#about to read 4, iclass 10, count 0 2006.197.08:02:22.25#ibcon#read 4, iclass 10, count 0 2006.197.08:02:22.25#ibcon#about to read 5, iclass 10, count 0 2006.197.08:02:22.25#ibcon#read 5, iclass 10, count 0 2006.197.08:02:22.25#ibcon#about to read 6, iclass 10, count 0 2006.197.08:02:22.25#ibcon#read 6, iclass 10, count 0 2006.197.08:02:22.25#ibcon#end of sib2, iclass 10, count 0 2006.197.08:02:22.25#ibcon#*after write, iclass 10, count 0 2006.197.08:02:22.25#ibcon#*before return 0, iclass 10, count 0 2006.197.08:02:22.25#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.197.08:02:22.25#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.197.08:02:22.25#ibcon#about to clear, iclass 10 cls_cnt 0 2006.197.08:02:22.25#ibcon#cleared, iclass 10 cls_cnt 0 2006.197.08:02:22.25$vc4f8/vbbw=wide 2006.197.08:02:22.25#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.197.08:02:22.25#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.197.08:02:22.25#ibcon#ireg 8 cls_cnt 0 2006.197.08:02:22.25#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.197.08:02:22.32#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.197.08:02:22.32#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.197.08:02:22.32#ibcon#enter wrdev, iclass 12, count 0 2006.197.08:02:22.32#ibcon#first serial, iclass 12, count 0 2006.197.08:02:22.32#ibcon#enter sib2, iclass 12, count 0 2006.197.08:02:22.32#ibcon#flushed, iclass 12, count 0 2006.197.08:02:22.32#ibcon#about to write, iclass 12, count 0 2006.197.08:02:22.32#ibcon#wrote, iclass 12, count 0 2006.197.08:02:22.32#ibcon#about to read 3, iclass 12, count 0 2006.197.08:02:22.34#ibcon#read 3, iclass 12, count 0 2006.197.08:02:22.34#ibcon#about to read 4, iclass 12, count 0 2006.197.08:02:22.34#ibcon#read 4, iclass 12, count 0 2006.197.08:02:22.34#ibcon#about to read 5, iclass 12, count 0 2006.197.08:02:22.34#ibcon#read 5, iclass 12, count 0 2006.197.08:02:22.34#ibcon#about to read 6, iclass 12, count 0 2006.197.08:02:22.34#ibcon#read 6, iclass 12, count 0 2006.197.08:02:22.34#ibcon#end of sib2, iclass 12, count 0 2006.197.08:02:22.34#ibcon#*mode == 0, iclass 12, count 0 2006.197.08:02:22.34#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.197.08:02:22.34#ibcon#[27=BW32\r\n] 2006.197.08:02:22.34#ibcon#*before write, iclass 12, count 0 2006.197.08:02:22.34#ibcon#enter sib2, iclass 12, count 0 2006.197.08:02:22.34#ibcon#flushed, iclass 12, count 0 2006.197.08:02:22.34#ibcon#about to write, iclass 12, count 0 2006.197.08:02:22.34#ibcon#wrote, iclass 12, count 0 2006.197.08:02:22.34#ibcon#about to read 3, iclass 12, count 0 2006.197.08:02:22.37#ibcon#read 3, iclass 12, count 0 2006.197.08:02:22.37#ibcon#about to read 4, iclass 12, count 0 2006.197.08:02:22.37#ibcon#read 4, iclass 12, count 0 2006.197.08:02:22.37#ibcon#about to read 5, iclass 12, count 0 2006.197.08:02:22.37#ibcon#read 5, iclass 12, count 0 2006.197.08:02:22.37#ibcon#about to read 6, iclass 12, count 0 2006.197.08:02:22.37#ibcon#read 6, iclass 12, count 0 2006.197.08:02:22.37#ibcon#end of sib2, iclass 12, count 0 2006.197.08:02:22.37#ibcon#*after write, iclass 12, count 0 2006.197.08:02:22.37#ibcon#*before return 0, iclass 12, count 0 2006.197.08:02:22.37#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.197.08:02:22.37#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.197.08:02:22.37#ibcon#about to clear, iclass 12 cls_cnt 0 2006.197.08:02:22.37#ibcon#cleared, iclass 12 cls_cnt 0 2006.197.08:02:22.37$4f8m12a/ifd4f 2006.197.08:02:22.37$ifd4f/lo= 2006.197.08:02:22.37$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.197.08:02:22.37$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.197.08:02:22.37$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.197.08:02:22.37$ifd4f/patch= 2006.197.08:02:22.37$ifd4f/patch=lo1,a1,a2,a3,a4 2006.197.08:02:22.37$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.197.08:02:22.37$ifd4f/patch=lo3,a5,a6,a7,a8 2006.197.08:02:22.37$4f8m12a/"form=m,16.000,1:2 2006.197.08:02:22.37$4f8m12a/"tpicd 2006.197.08:02:22.37$4f8m12a/echo=off 2006.197.08:02:22.37$4f8m12a/xlog=off 2006.197.08:02:22.37:!2006.197.08:02:50 2006.197.08:02:26.14#trakl#Source acquired 2006.197.08:02:26.14#flagr#flagr/antenna,acquired 2006.197.08:02:50.00:preob 2006.197.08:02:51.14/onsource/TRACKING 2006.197.08:02:51.14:!2006.197.08:03:00 2006.197.08:03:00.00:data_valid=on 2006.197.08:03:00.00:midob 2006.197.08:03:00.13/onsource/TRACKING 2006.197.08:03:00.13/wx/25.69,1002.8,96 2006.197.08:03:00.28/cable/+6.3717E-03 2006.197.08:03:01.37/va/01,08,usb,yes,29,31 2006.197.08:03:01.37/va/02,07,usb,yes,29,31 2006.197.08:03:01.37/va/03,06,usb,yes,31,31 2006.197.08:03:01.37/va/04,07,usb,yes,30,32 2006.197.08:03:01.37/va/05,07,usb,yes,34,36 2006.197.08:03:01.37/va/06,06,usb,yes,33,33 2006.197.08:03:01.37/va/07,06,usb,yes,33,33 2006.197.08:03:01.37/va/08,07,usb,yes,31,31 2006.197.08:03:01.60/valo/01,532.99,yes,locked 2006.197.08:03:01.60/valo/02,572.99,yes,locked 2006.197.08:03:01.60/valo/03,672.99,yes,locked 2006.197.08:03:01.60/valo/04,832.99,yes,locked 2006.197.08:03:01.60/valo/05,652.99,yes,locked 2006.197.08:03:01.60/valo/06,772.99,yes,locked 2006.197.08:03:01.60/valo/07,832.99,yes,locked 2006.197.08:03:01.60/valo/08,852.99,yes,locked 2006.197.08:03:02.69/vb/01,04,usb,yes,28,27 2006.197.08:03:02.69/vb/02,04,usb,yes,30,32 2006.197.08:03:02.69/vb/03,04,usb,yes,27,30 2006.197.08:03:02.69/vb/04,04,usb,yes,28,28 2006.197.08:03:02.69/vb/05,04,usb,yes,26,30 2006.197.08:03:02.69/vb/06,04,usb,yes,27,30 2006.197.08:03:02.69/vb/07,04,usb,yes,29,29 2006.197.08:03:02.69/vb/08,04,usb,yes,27,30 2006.197.08:03:02.92/vblo/01,632.99,yes,locked 2006.197.08:03:02.92/vblo/02,640.99,yes,locked 2006.197.08:03:02.92/vblo/03,656.99,yes,locked 2006.197.08:03:02.92/vblo/04,712.99,yes,locked 2006.197.08:03:02.92/vblo/05,744.99,yes,locked 2006.197.08:03:02.92/vblo/06,752.99,yes,locked 2006.197.08:03:02.92/vblo/07,734.99,yes,locked 2006.197.08:03:02.92/vblo/08,744.99,yes,locked 2006.197.08:03:03.07/vabw/8 2006.197.08:03:03.22/vbbw/8 2006.197.08:03:03.31/xfe/off,on,15.5 2006.197.08:03:03.70/ifatt/23,28,28,28 2006.197.08:03:04.09/fmout-gps/S +3.02E-07 2006.197.08:03:04.13:!2006.197.08:04:00 2006.197.08:04:00.00:data_valid=off 2006.197.08:04:00.00:postob 2006.197.08:04:00.09/cable/+6.3705E-03 2006.197.08:04:00.09/wx/25.69,1002.8,96 2006.197.08:04:01.09/fmout-gps/S +3.02E-07 2006.197.08:04:01.09:scan_name=197-0804,k06197,60 2006.197.08:04:01.09:source=3c418,203837.03,511912.7,2000.0,cw 2006.197.08:04:02.13#flagr#flagr/antenna,new-source 2006.197.08:04:02.13:checkk5 2006.197.08:04:02.47/chk_autoobs//k5ts1/ autoobs is running! 2006.197.08:04:02.81/chk_autoobs//k5ts2/ autoobs is running! 2006.197.08:04:03.15/chk_autoobs//k5ts3/ autoobs is running! 2006.197.08:04:03.50/chk_autoobs//k5ts4/ autoobs is running! 2006.197.08:04:03.83/chk_obsdata//k5ts1/T1970803??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.08:04:04.16/chk_obsdata//k5ts2/T1970803??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.08:04:04.49/chk_obsdata//k5ts3/T1970803??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.08:04:04.83/chk_obsdata//k5ts4/T1970803??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.08:04:05.48/k5log//k5ts1_log_newline 2006.197.08:04:06.14/k5log//k5ts2_log_newline 2006.197.08:04:06.79/k5log//k5ts3_log_newline 2006.197.08:04:07.46/k5log//k5ts4_log_newline 2006.197.08:04:07.48/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.197.08:04:07.48:4f8m12a=2 2006.197.08:04:07.48$4f8m12a/echo=on 2006.197.08:04:07.48$4f8m12a/pcalon 2006.197.08:04:07.48$pcalon/"no phase cal control is implemented here 2006.197.08:04:07.48$4f8m12a/"tpicd=stop 2006.197.08:04:07.48$4f8m12a/vc4f8 2006.197.08:04:07.48$vc4f8/valo=1,532.99 2006.197.08:04:07.49#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.197.08:04:07.49#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.197.08:04:07.49#ibcon#ireg 17 cls_cnt 0 2006.197.08:04:07.49#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.197.08:04:07.49#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.197.08:04:07.49#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.197.08:04:07.49#ibcon#enter wrdev, iclass 19, count 0 2006.197.08:04:07.49#ibcon#first serial, iclass 19, count 0 2006.197.08:04:07.49#ibcon#enter sib2, iclass 19, count 0 2006.197.08:04:07.49#ibcon#flushed, iclass 19, count 0 2006.197.08:04:07.49#ibcon#about to write, iclass 19, count 0 2006.197.08:04:07.49#ibcon#wrote, iclass 19, count 0 2006.197.08:04:07.49#ibcon#about to read 3, iclass 19, count 0 2006.197.08:04:07.51#ibcon#read 3, iclass 19, count 0 2006.197.08:04:07.51#ibcon#about to read 4, iclass 19, count 0 2006.197.08:04:07.51#ibcon#read 4, iclass 19, count 0 2006.197.08:04:07.51#ibcon#about to read 5, iclass 19, count 0 2006.197.08:04:07.51#ibcon#read 5, iclass 19, count 0 2006.197.08:04:07.51#ibcon#about to read 6, iclass 19, count 0 2006.197.08:04:07.51#ibcon#read 6, iclass 19, count 0 2006.197.08:04:07.51#ibcon#end of sib2, iclass 19, count 0 2006.197.08:04:07.51#ibcon#*mode == 0, iclass 19, count 0 2006.197.08:04:07.51#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.197.08:04:07.51#ibcon#[26=FRQ=01,532.99\r\n] 2006.197.08:04:07.51#ibcon#*before write, iclass 19, count 0 2006.197.08:04:07.51#ibcon#enter sib2, iclass 19, count 0 2006.197.08:04:07.51#ibcon#flushed, iclass 19, count 0 2006.197.08:04:07.51#ibcon#about to write, iclass 19, count 0 2006.197.08:04:07.51#ibcon#wrote, iclass 19, count 0 2006.197.08:04:07.51#ibcon#about to read 3, iclass 19, count 0 2006.197.08:04:07.56#ibcon#read 3, iclass 19, count 0 2006.197.08:04:07.56#ibcon#about to read 4, iclass 19, count 0 2006.197.08:04:07.56#ibcon#read 4, iclass 19, count 0 2006.197.08:04:07.56#ibcon#about to read 5, iclass 19, count 0 2006.197.08:04:07.56#ibcon#read 5, iclass 19, count 0 2006.197.08:04:07.56#ibcon#about to read 6, iclass 19, count 0 2006.197.08:04:07.56#ibcon#read 6, iclass 19, count 0 2006.197.08:04:07.56#ibcon#end of sib2, iclass 19, count 0 2006.197.08:04:07.56#ibcon#*after write, iclass 19, count 0 2006.197.08:04:07.56#ibcon#*before return 0, iclass 19, count 0 2006.197.08:04:07.56#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.197.08:04:07.56#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.197.08:04:07.56#ibcon#about to clear, iclass 19 cls_cnt 0 2006.197.08:04:07.56#ibcon#cleared, iclass 19 cls_cnt 0 2006.197.08:04:07.56$vc4f8/va=1,8 2006.197.08:04:07.56#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.197.08:04:07.56#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.197.08:04:07.56#ibcon#ireg 11 cls_cnt 2 2006.197.08:04:07.56#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.197.08:04:07.56#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.197.08:04:07.56#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.197.08:04:07.56#ibcon#enter wrdev, iclass 21, count 2 2006.197.08:04:07.56#ibcon#first serial, iclass 21, count 2 2006.197.08:04:07.56#ibcon#enter sib2, iclass 21, count 2 2006.197.08:04:07.56#ibcon#flushed, iclass 21, count 2 2006.197.08:04:07.56#ibcon#about to write, iclass 21, count 2 2006.197.08:04:07.56#ibcon#wrote, iclass 21, count 2 2006.197.08:04:07.56#ibcon#about to read 3, iclass 21, count 2 2006.197.08:04:07.58#ibcon#read 3, iclass 21, count 2 2006.197.08:04:07.58#ibcon#about to read 4, iclass 21, count 2 2006.197.08:04:07.58#ibcon#read 4, iclass 21, count 2 2006.197.08:04:07.58#ibcon#about to read 5, iclass 21, count 2 2006.197.08:04:07.58#ibcon#read 5, iclass 21, count 2 2006.197.08:04:07.58#ibcon#about to read 6, iclass 21, count 2 2006.197.08:04:07.58#ibcon#read 6, iclass 21, count 2 2006.197.08:04:07.58#ibcon#end of sib2, iclass 21, count 2 2006.197.08:04:07.58#ibcon#*mode == 0, iclass 21, count 2 2006.197.08:04:07.58#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.197.08:04:07.58#ibcon#[25=AT01-08\r\n] 2006.197.08:04:07.58#ibcon#*before write, iclass 21, count 2 2006.197.08:04:07.58#ibcon#enter sib2, iclass 21, count 2 2006.197.08:04:07.58#ibcon#flushed, iclass 21, count 2 2006.197.08:04:07.58#ibcon#about to write, iclass 21, count 2 2006.197.08:04:07.58#ibcon#wrote, iclass 21, count 2 2006.197.08:04:07.58#ibcon#about to read 3, iclass 21, count 2 2006.197.08:04:07.61#ibcon#read 3, iclass 21, count 2 2006.197.08:04:07.61#ibcon#about to read 4, iclass 21, count 2 2006.197.08:04:07.61#ibcon#read 4, iclass 21, count 2 2006.197.08:04:07.61#ibcon#about to read 5, iclass 21, count 2 2006.197.08:04:07.61#ibcon#read 5, iclass 21, count 2 2006.197.08:04:07.61#ibcon#about to read 6, iclass 21, count 2 2006.197.08:04:07.61#ibcon#read 6, iclass 21, count 2 2006.197.08:04:07.61#ibcon#end of sib2, iclass 21, count 2 2006.197.08:04:07.61#ibcon#*after write, iclass 21, count 2 2006.197.08:04:07.61#ibcon#*before return 0, iclass 21, count 2 2006.197.08:04:07.61#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.197.08:04:07.61#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.197.08:04:07.61#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.197.08:04:07.61#ibcon#ireg 7 cls_cnt 0 2006.197.08:04:07.61#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.197.08:04:07.73#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.197.08:04:07.73#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.197.08:04:07.73#ibcon#enter wrdev, iclass 21, count 0 2006.197.08:04:07.73#ibcon#first serial, iclass 21, count 0 2006.197.08:04:07.73#ibcon#enter sib2, iclass 21, count 0 2006.197.08:04:07.73#ibcon#flushed, iclass 21, count 0 2006.197.08:04:07.73#ibcon#about to write, iclass 21, count 0 2006.197.08:04:07.73#ibcon#wrote, iclass 21, count 0 2006.197.08:04:07.73#ibcon#about to read 3, iclass 21, count 0 2006.197.08:04:07.75#ibcon#read 3, iclass 21, count 0 2006.197.08:04:07.75#ibcon#about to read 4, iclass 21, count 0 2006.197.08:04:07.75#ibcon#read 4, iclass 21, count 0 2006.197.08:04:07.75#ibcon#about to read 5, iclass 21, count 0 2006.197.08:04:07.75#ibcon#read 5, iclass 21, count 0 2006.197.08:04:07.75#ibcon#about to read 6, iclass 21, count 0 2006.197.08:04:07.75#ibcon#read 6, iclass 21, count 0 2006.197.08:04:07.75#ibcon#end of sib2, iclass 21, count 0 2006.197.08:04:07.75#ibcon#*mode == 0, iclass 21, count 0 2006.197.08:04:07.75#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.197.08:04:07.75#ibcon#[25=USB\r\n] 2006.197.08:04:07.75#ibcon#*before write, iclass 21, count 0 2006.197.08:04:07.75#ibcon#enter sib2, iclass 21, count 0 2006.197.08:04:07.75#ibcon#flushed, iclass 21, count 0 2006.197.08:04:07.75#ibcon#about to write, iclass 21, count 0 2006.197.08:04:07.75#ibcon#wrote, iclass 21, count 0 2006.197.08:04:07.75#ibcon#about to read 3, iclass 21, count 0 2006.197.08:04:07.78#ibcon#read 3, iclass 21, count 0 2006.197.08:04:07.78#ibcon#about to read 4, iclass 21, count 0 2006.197.08:04:07.78#ibcon#read 4, iclass 21, count 0 2006.197.08:04:07.78#ibcon#about to read 5, iclass 21, count 0 2006.197.08:04:07.78#ibcon#read 5, iclass 21, count 0 2006.197.08:04:07.78#ibcon#about to read 6, iclass 21, count 0 2006.197.08:04:07.78#ibcon#read 6, iclass 21, count 0 2006.197.08:04:07.78#ibcon#end of sib2, iclass 21, count 0 2006.197.08:04:07.78#ibcon#*after write, iclass 21, count 0 2006.197.08:04:07.78#ibcon#*before return 0, iclass 21, count 0 2006.197.08:04:07.78#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.197.08:04:07.78#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.197.08:04:07.78#ibcon#about to clear, iclass 21 cls_cnt 0 2006.197.08:04:07.78#ibcon#cleared, iclass 21 cls_cnt 0 2006.197.08:04:07.78$vc4f8/valo=2,572.99 2006.197.08:04:07.78#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.197.08:04:07.78#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.197.08:04:07.78#ibcon#ireg 17 cls_cnt 0 2006.197.08:04:07.78#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.197.08:04:07.78#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.197.08:04:07.78#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.197.08:04:07.78#ibcon#enter wrdev, iclass 23, count 0 2006.197.08:04:07.78#ibcon#first serial, iclass 23, count 0 2006.197.08:04:07.78#ibcon#enter sib2, iclass 23, count 0 2006.197.08:04:07.78#ibcon#flushed, iclass 23, count 0 2006.197.08:04:07.78#ibcon#about to write, iclass 23, count 0 2006.197.08:04:07.78#ibcon#wrote, iclass 23, count 0 2006.197.08:04:07.78#ibcon#about to read 3, iclass 23, count 0 2006.197.08:04:07.80#ibcon#read 3, iclass 23, count 0 2006.197.08:04:07.80#ibcon#about to read 4, iclass 23, count 0 2006.197.08:04:07.80#ibcon#read 4, iclass 23, count 0 2006.197.08:04:07.80#ibcon#about to read 5, iclass 23, count 0 2006.197.08:04:07.80#ibcon#read 5, iclass 23, count 0 2006.197.08:04:07.80#ibcon#about to read 6, iclass 23, count 0 2006.197.08:04:07.80#ibcon#read 6, iclass 23, count 0 2006.197.08:04:07.80#ibcon#end of sib2, iclass 23, count 0 2006.197.08:04:07.80#ibcon#*mode == 0, iclass 23, count 0 2006.197.08:04:07.80#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.197.08:04:07.80#ibcon#[26=FRQ=02,572.99\r\n] 2006.197.08:04:07.80#ibcon#*before write, iclass 23, count 0 2006.197.08:04:07.80#ibcon#enter sib2, iclass 23, count 0 2006.197.08:04:07.80#ibcon#flushed, iclass 23, count 0 2006.197.08:04:07.80#ibcon#about to write, iclass 23, count 0 2006.197.08:04:07.80#ibcon#wrote, iclass 23, count 0 2006.197.08:04:07.80#ibcon#about to read 3, iclass 23, count 0 2006.197.08:04:07.84#ibcon#read 3, iclass 23, count 0 2006.197.08:04:07.84#ibcon#about to read 4, iclass 23, count 0 2006.197.08:04:07.84#ibcon#read 4, iclass 23, count 0 2006.197.08:04:07.84#ibcon#about to read 5, iclass 23, count 0 2006.197.08:04:07.84#ibcon#read 5, iclass 23, count 0 2006.197.08:04:07.84#ibcon#about to read 6, iclass 23, count 0 2006.197.08:04:07.84#ibcon#read 6, iclass 23, count 0 2006.197.08:04:07.84#ibcon#end of sib2, iclass 23, count 0 2006.197.08:04:07.84#ibcon#*after write, iclass 23, count 0 2006.197.08:04:07.84#ibcon#*before return 0, iclass 23, count 0 2006.197.08:04:07.84#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.197.08:04:07.84#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.197.08:04:07.84#ibcon#about to clear, iclass 23 cls_cnt 0 2006.197.08:04:07.84#ibcon#cleared, iclass 23 cls_cnt 0 2006.197.08:04:07.84$vc4f8/va=2,7 2006.197.08:04:07.84#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.197.08:04:07.84#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.197.08:04:07.84#ibcon#ireg 11 cls_cnt 2 2006.197.08:04:07.84#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.197.08:04:07.90#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.197.08:04:07.90#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.197.08:04:07.90#ibcon#enter wrdev, iclass 25, count 2 2006.197.08:04:07.90#ibcon#first serial, iclass 25, count 2 2006.197.08:04:07.90#ibcon#enter sib2, iclass 25, count 2 2006.197.08:04:07.90#ibcon#flushed, iclass 25, count 2 2006.197.08:04:07.90#ibcon#about to write, iclass 25, count 2 2006.197.08:04:07.90#ibcon#wrote, iclass 25, count 2 2006.197.08:04:07.90#ibcon#about to read 3, iclass 25, count 2 2006.197.08:04:07.92#ibcon#read 3, iclass 25, count 2 2006.197.08:04:07.92#ibcon#about to read 4, iclass 25, count 2 2006.197.08:04:07.92#ibcon#read 4, iclass 25, count 2 2006.197.08:04:07.92#ibcon#about to read 5, iclass 25, count 2 2006.197.08:04:07.92#ibcon#read 5, iclass 25, count 2 2006.197.08:04:07.92#ibcon#about to read 6, iclass 25, count 2 2006.197.08:04:07.92#ibcon#read 6, iclass 25, count 2 2006.197.08:04:07.92#ibcon#end of sib2, iclass 25, count 2 2006.197.08:04:07.92#ibcon#*mode == 0, iclass 25, count 2 2006.197.08:04:07.92#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.197.08:04:07.92#ibcon#[25=AT02-07\r\n] 2006.197.08:04:07.92#ibcon#*before write, iclass 25, count 2 2006.197.08:04:07.92#ibcon#enter sib2, iclass 25, count 2 2006.197.08:04:07.92#ibcon#flushed, iclass 25, count 2 2006.197.08:04:07.92#ibcon#about to write, iclass 25, count 2 2006.197.08:04:07.92#ibcon#wrote, iclass 25, count 2 2006.197.08:04:07.92#ibcon#about to read 3, iclass 25, count 2 2006.197.08:04:07.95#ibcon#read 3, iclass 25, count 2 2006.197.08:04:07.95#ibcon#about to read 4, iclass 25, count 2 2006.197.08:04:07.95#ibcon#read 4, iclass 25, count 2 2006.197.08:04:07.95#ibcon#about to read 5, iclass 25, count 2 2006.197.08:04:07.95#ibcon#read 5, iclass 25, count 2 2006.197.08:04:07.95#ibcon#about to read 6, iclass 25, count 2 2006.197.08:04:07.95#ibcon#read 6, iclass 25, count 2 2006.197.08:04:07.95#ibcon#end of sib2, iclass 25, count 2 2006.197.08:04:07.95#ibcon#*after write, iclass 25, count 2 2006.197.08:04:07.95#ibcon#*before return 0, iclass 25, count 2 2006.197.08:04:07.95#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.197.08:04:07.95#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.197.08:04:07.95#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.197.08:04:07.95#ibcon#ireg 7 cls_cnt 0 2006.197.08:04:07.95#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.197.08:04:08.07#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.197.08:04:08.07#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.197.08:04:08.07#ibcon#enter wrdev, iclass 25, count 0 2006.197.08:04:08.07#ibcon#first serial, iclass 25, count 0 2006.197.08:04:08.07#ibcon#enter sib2, iclass 25, count 0 2006.197.08:04:08.07#ibcon#flushed, iclass 25, count 0 2006.197.08:04:08.07#ibcon#about to write, iclass 25, count 0 2006.197.08:04:08.07#ibcon#wrote, iclass 25, count 0 2006.197.08:04:08.07#ibcon#about to read 3, iclass 25, count 0 2006.197.08:04:08.09#ibcon#read 3, iclass 25, count 0 2006.197.08:04:08.09#ibcon#about to read 4, iclass 25, count 0 2006.197.08:04:08.09#ibcon#read 4, iclass 25, count 0 2006.197.08:04:08.09#ibcon#about to read 5, iclass 25, count 0 2006.197.08:04:08.09#ibcon#read 5, iclass 25, count 0 2006.197.08:04:08.09#ibcon#about to read 6, iclass 25, count 0 2006.197.08:04:08.09#ibcon#read 6, iclass 25, count 0 2006.197.08:04:08.09#ibcon#end of sib2, iclass 25, count 0 2006.197.08:04:08.09#ibcon#*mode == 0, iclass 25, count 0 2006.197.08:04:08.09#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.197.08:04:08.09#ibcon#[25=USB\r\n] 2006.197.08:04:08.09#ibcon#*before write, iclass 25, count 0 2006.197.08:04:08.09#ibcon#enter sib2, iclass 25, count 0 2006.197.08:04:08.09#ibcon#flushed, iclass 25, count 0 2006.197.08:04:08.09#ibcon#about to write, iclass 25, count 0 2006.197.08:04:08.09#ibcon#wrote, iclass 25, count 0 2006.197.08:04:08.09#ibcon#about to read 3, iclass 25, count 0 2006.197.08:04:08.12#ibcon#read 3, iclass 25, count 0 2006.197.08:04:08.12#ibcon#about to read 4, iclass 25, count 0 2006.197.08:04:08.12#ibcon#read 4, iclass 25, count 0 2006.197.08:04:08.12#ibcon#about to read 5, iclass 25, count 0 2006.197.08:04:08.12#ibcon#read 5, iclass 25, count 0 2006.197.08:04:08.12#ibcon#about to read 6, iclass 25, count 0 2006.197.08:04:08.12#ibcon#read 6, iclass 25, count 0 2006.197.08:04:08.12#ibcon#end of sib2, iclass 25, count 0 2006.197.08:04:08.12#ibcon#*after write, iclass 25, count 0 2006.197.08:04:08.12#ibcon#*before return 0, iclass 25, count 0 2006.197.08:04:08.12#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.197.08:04:08.12#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.197.08:04:08.12#ibcon#about to clear, iclass 25 cls_cnt 0 2006.197.08:04:08.12#ibcon#cleared, iclass 25 cls_cnt 0 2006.197.08:04:08.12$vc4f8/valo=3,672.99 2006.197.08:04:08.12#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.197.08:04:08.12#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.197.08:04:08.12#ibcon#ireg 17 cls_cnt 0 2006.197.08:04:08.12#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.197.08:04:08.12#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.197.08:04:08.12#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.197.08:04:08.12#ibcon#enter wrdev, iclass 27, count 0 2006.197.08:04:08.12#ibcon#first serial, iclass 27, count 0 2006.197.08:04:08.12#ibcon#enter sib2, iclass 27, count 0 2006.197.08:04:08.12#ibcon#flushed, iclass 27, count 0 2006.197.08:04:08.12#ibcon#about to write, iclass 27, count 0 2006.197.08:04:08.12#ibcon#wrote, iclass 27, count 0 2006.197.08:04:08.12#ibcon#about to read 3, iclass 27, count 0 2006.197.08:04:08.14#ibcon#read 3, iclass 27, count 0 2006.197.08:04:08.14#ibcon#about to read 4, iclass 27, count 0 2006.197.08:04:08.14#ibcon#read 4, iclass 27, count 0 2006.197.08:04:08.14#ibcon#about to read 5, iclass 27, count 0 2006.197.08:04:08.14#ibcon#read 5, iclass 27, count 0 2006.197.08:04:08.14#ibcon#about to read 6, iclass 27, count 0 2006.197.08:04:08.14#ibcon#read 6, iclass 27, count 0 2006.197.08:04:08.14#ibcon#end of sib2, iclass 27, count 0 2006.197.08:04:08.14#ibcon#*mode == 0, iclass 27, count 0 2006.197.08:04:08.14#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.197.08:04:08.14#ibcon#[26=FRQ=03,672.99\r\n] 2006.197.08:04:08.14#ibcon#*before write, iclass 27, count 0 2006.197.08:04:08.14#ibcon#enter sib2, iclass 27, count 0 2006.197.08:04:08.14#ibcon#flushed, iclass 27, count 0 2006.197.08:04:08.14#ibcon#about to write, iclass 27, count 0 2006.197.08:04:08.14#ibcon#wrote, iclass 27, count 0 2006.197.08:04:08.14#ibcon#about to read 3, iclass 27, count 0 2006.197.08:04:08.18#ibcon#read 3, iclass 27, count 0 2006.197.08:04:08.18#ibcon#about to read 4, iclass 27, count 0 2006.197.08:04:08.18#ibcon#read 4, iclass 27, count 0 2006.197.08:04:08.18#ibcon#about to read 5, iclass 27, count 0 2006.197.08:04:08.18#ibcon#read 5, iclass 27, count 0 2006.197.08:04:08.18#ibcon#about to read 6, iclass 27, count 0 2006.197.08:04:08.18#ibcon#read 6, iclass 27, count 0 2006.197.08:04:08.18#ibcon#end of sib2, iclass 27, count 0 2006.197.08:04:08.18#ibcon#*after write, iclass 27, count 0 2006.197.08:04:08.18#ibcon#*before return 0, iclass 27, count 0 2006.197.08:04:08.18#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.197.08:04:08.18#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.197.08:04:08.18#ibcon#about to clear, iclass 27 cls_cnt 0 2006.197.08:04:08.18#ibcon#cleared, iclass 27 cls_cnt 0 2006.197.08:04:08.18$vc4f8/va=3,6 2006.197.08:04:08.18#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.197.08:04:08.18#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.197.08:04:08.18#ibcon#ireg 11 cls_cnt 2 2006.197.08:04:08.18#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.197.08:04:08.24#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.197.08:04:08.24#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.197.08:04:08.24#ibcon#enter wrdev, iclass 29, count 2 2006.197.08:04:08.24#ibcon#first serial, iclass 29, count 2 2006.197.08:04:08.24#ibcon#enter sib2, iclass 29, count 2 2006.197.08:04:08.24#ibcon#flushed, iclass 29, count 2 2006.197.08:04:08.24#ibcon#about to write, iclass 29, count 2 2006.197.08:04:08.24#ibcon#wrote, iclass 29, count 2 2006.197.08:04:08.24#ibcon#about to read 3, iclass 29, count 2 2006.197.08:04:08.26#ibcon#read 3, iclass 29, count 2 2006.197.08:04:08.26#ibcon#about to read 4, iclass 29, count 2 2006.197.08:04:08.26#ibcon#read 4, iclass 29, count 2 2006.197.08:04:08.26#ibcon#about to read 5, iclass 29, count 2 2006.197.08:04:08.26#ibcon#read 5, iclass 29, count 2 2006.197.08:04:08.26#ibcon#about to read 6, iclass 29, count 2 2006.197.08:04:08.26#ibcon#read 6, iclass 29, count 2 2006.197.08:04:08.26#ibcon#end of sib2, iclass 29, count 2 2006.197.08:04:08.26#ibcon#*mode == 0, iclass 29, count 2 2006.197.08:04:08.26#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.197.08:04:08.26#ibcon#[25=AT03-06\r\n] 2006.197.08:04:08.26#ibcon#*before write, iclass 29, count 2 2006.197.08:04:08.26#ibcon#enter sib2, iclass 29, count 2 2006.197.08:04:08.26#ibcon#flushed, iclass 29, count 2 2006.197.08:04:08.26#ibcon#about to write, iclass 29, count 2 2006.197.08:04:08.26#ibcon#wrote, iclass 29, count 2 2006.197.08:04:08.26#ibcon#about to read 3, iclass 29, count 2 2006.197.08:04:08.29#ibcon#read 3, iclass 29, count 2 2006.197.08:04:08.29#ibcon#about to read 4, iclass 29, count 2 2006.197.08:04:08.29#ibcon#read 4, iclass 29, count 2 2006.197.08:04:08.29#ibcon#about to read 5, iclass 29, count 2 2006.197.08:04:08.29#ibcon#read 5, iclass 29, count 2 2006.197.08:04:08.29#ibcon#about to read 6, iclass 29, count 2 2006.197.08:04:08.29#ibcon#read 6, iclass 29, count 2 2006.197.08:04:08.29#ibcon#end of sib2, iclass 29, count 2 2006.197.08:04:08.29#ibcon#*after write, iclass 29, count 2 2006.197.08:04:08.29#ibcon#*before return 0, iclass 29, count 2 2006.197.08:04:08.29#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.197.08:04:08.29#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.197.08:04:08.29#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.197.08:04:08.29#ibcon#ireg 7 cls_cnt 0 2006.197.08:04:08.29#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.197.08:04:08.41#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.197.08:04:08.41#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.197.08:04:08.41#ibcon#enter wrdev, iclass 29, count 0 2006.197.08:04:08.41#ibcon#first serial, iclass 29, count 0 2006.197.08:04:08.41#ibcon#enter sib2, iclass 29, count 0 2006.197.08:04:08.41#ibcon#flushed, iclass 29, count 0 2006.197.08:04:08.41#ibcon#about to write, iclass 29, count 0 2006.197.08:04:08.41#ibcon#wrote, iclass 29, count 0 2006.197.08:04:08.41#ibcon#about to read 3, iclass 29, count 0 2006.197.08:04:08.43#ibcon#read 3, iclass 29, count 0 2006.197.08:04:08.43#ibcon#about to read 4, iclass 29, count 0 2006.197.08:04:08.43#ibcon#read 4, iclass 29, count 0 2006.197.08:04:08.43#ibcon#about to read 5, iclass 29, count 0 2006.197.08:04:08.43#ibcon#read 5, iclass 29, count 0 2006.197.08:04:08.43#ibcon#about to read 6, iclass 29, count 0 2006.197.08:04:08.43#ibcon#read 6, iclass 29, count 0 2006.197.08:04:08.43#ibcon#end of sib2, iclass 29, count 0 2006.197.08:04:08.43#ibcon#*mode == 0, iclass 29, count 0 2006.197.08:04:08.43#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.197.08:04:08.43#ibcon#[25=USB\r\n] 2006.197.08:04:08.43#ibcon#*before write, iclass 29, count 0 2006.197.08:04:08.43#ibcon#enter sib2, iclass 29, count 0 2006.197.08:04:08.43#ibcon#flushed, iclass 29, count 0 2006.197.08:04:08.43#ibcon#about to write, iclass 29, count 0 2006.197.08:04:08.43#ibcon#wrote, iclass 29, count 0 2006.197.08:04:08.43#ibcon#about to read 3, iclass 29, count 0 2006.197.08:04:08.46#ibcon#read 3, iclass 29, count 0 2006.197.08:04:08.46#ibcon#about to read 4, iclass 29, count 0 2006.197.08:04:08.46#ibcon#read 4, iclass 29, count 0 2006.197.08:04:08.46#ibcon#about to read 5, iclass 29, count 0 2006.197.08:04:08.46#ibcon#read 5, iclass 29, count 0 2006.197.08:04:08.46#ibcon#about to read 6, iclass 29, count 0 2006.197.08:04:08.46#ibcon#read 6, iclass 29, count 0 2006.197.08:04:08.46#ibcon#end of sib2, iclass 29, count 0 2006.197.08:04:08.46#ibcon#*after write, iclass 29, count 0 2006.197.08:04:08.46#ibcon#*before return 0, iclass 29, count 0 2006.197.08:04:08.46#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.197.08:04:08.46#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.197.08:04:08.46#ibcon#about to clear, iclass 29 cls_cnt 0 2006.197.08:04:08.46#ibcon#cleared, iclass 29 cls_cnt 0 2006.197.08:04:08.46$vc4f8/valo=4,832.99 2006.197.08:04:08.46#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.197.08:04:08.46#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.197.08:04:08.46#ibcon#ireg 17 cls_cnt 0 2006.197.08:04:08.46#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.197.08:04:08.46#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.197.08:04:08.46#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.197.08:04:08.46#ibcon#enter wrdev, iclass 31, count 0 2006.197.08:04:08.46#ibcon#first serial, iclass 31, count 0 2006.197.08:04:08.46#ibcon#enter sib2, iclass 31, count 0 2006.197.08:04:08.46#ibcon#flushed, iclass 31, count 0 2006.197.08:04:08.46#ibcon#about to write, iclass 31, count 0 2006.197.08:04:08.46#ibcon#wrote, iclass 31, count 0 2006.197.08:04:08.46#ibcon#about to read 3, iclass 31, count 0 2006.197.08:04:08.48#ibcon#read 3, iclass 31, count 0 2006.197.08:04:08.48#ibcon#about to read 4, iclass 31, count 0 2006.197.08:04:08.48#ibcon#read 4, iclass 31, count 0 2006.197.08:04:08.48#ibcon#about to read 5, iclass 31, count 0 2006.197.08:04:08.48#ibcon#read 5, iclass 31, count 0 2006.197.08:04:08.48#ibcon#about to read 6, iclass 31, count 0 2006.197.08:04:08.48#ibcon#read 6, iclass 31, count 0 2006.197.08:04:08.48#ibcon#end of sib2, iclass 31, count 0 2006.197.08:04:08.48#ibcon#*mode == 0, iclass 31, count 0 2006.197.08:04:08.48#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.197.08:04:08.48#ibcon#[26=FRQ=04,832.99\r\n] 2006.197.08:04:08.48#ibcon#*before write, iclass 31, count 0 2006.197.08:04:08.48#ibcon#enter sib2, iclass 31, count 0 2006.197.08:04:08.48#ibcon#flushed, iclass 31, count 0 2006.197.08:04:08.48#ibcon#about to write, iclass 31, count 0 2006.197.08:04:08.48#ibcon#wrote, iclass 31, count 0 2006.197.08:04:08.48#ibcon#about to read 3, iclass 31, count 0 2006.197.08:04:08.52#ibcon#read 3, iclass 31, count 0 2006.197.08:04:08.52#ibcon#about to read 4, iclass 31, count 0 2006.197.08:04:08.52#ibcon#read 4, iclass 31, count 0 2006.197.08:04:08.52#ibcon#about to read 5, iclass 31, count 0 2006.197.08:04:08.52#ibcon#read 5, iclass 31, count 0 2006.197.08:04:08.52#ibcon#about to read 6, iclass 31, count 0 2006.197.08:04:08.52#ibcon#read 6, iclass 31, count 0 2006.197.08:04:08.52#ibcon#end of sib2, iclass 31, count 0 2006.197.08:04:08.52#ibcon#*after write, iclass 31, count 0 2006.197.08:04:08.52#ibcon#*before return 0, iclass 31, count 0 2006.197.08:04:08.52#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.197.08:04:08.52#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.197.08:04:08.52#ibcon#about to clear, iclass 31 cls_cnt 0 2006.197.08:04:08.52#ibcon#cleared, iclass 31 cls_cnt 0 2006.197.08:04:08.52$vc4f8/va=4,7 2006.197.08:04:08.52#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.197.08:04:08.52#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.197.08:04:08.52#ibcon#ireg 11 cls_cnt 2 2006.197.08:04:08.52#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.197.08:04:08.58#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.197.08:04:08.58#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.197.08:04:08.58#ibcon#enter wrdev, iclass 33, count 2 2006.197.08:04:08.58#ibcon#first serial, iclass 33, count 2 2006.197.08:04:08.58#ibcon#enter sib2, iclass 33, count 2 2006.197.08:04:08.58#ibcon#flushed, iclass 33, count 2 2006.197.08:04:08.58#ibcon#about to write, iclass 33, count 2 2006.197.08:04:08.58#ibcon#wrote, iclass 33, count 2 2006.197.08:04:08.58#ibcon#about to read 3, iclass 33, count 2 2006.197.08:04:08.60#ibcon#read 3, iclass 33, count 2 2006.197.08:04:08.60#ibcon#about to read 4, iclass 33, count 2 2006.197.08:04:08.60#ibcon#read 4, iclass 33, count 2 2006.197.08:04:08.60#ibcon#about to read 5, iclass 33, count 2 2006.197.08:04:08.60#ibcon#read 5, iclass 33, count 2 2006.197.08:04:08.60#ibcon#about to read 6, iclass 33, count 2 2006.197.08:04:08.60#ibcon#read 6, iclass 33, count 2 2006.197.08:04:08.60#ibcon#end of sib2, iclass 33, count 2 2006.197.08:04:08.60#ibcon#*mode == 0, iclass 33, count 2 2006.197.08:04:08.60#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.197.08:04:08.60#ibcon#[25=AT04-07\r\n] 2006.197.08:04:08.60#ibcon#*before write, iclass 33, count 2 2006.197.08:04:08.60#ibcon#enter sib2, iclass 33, count 2 2006.197.08:04:08.60#ibcon#flushed, iclass 33, count 2 2006.197.08:04:08.60#ibcon#about to write, iclass 33, count 2 2006.197.08:04:08.60#ibcon#wrote, iclass 33, count 2 2006.197.08:04:08.60#ibcon#about to read 3, iclass 33, count 2 2006.197.08:04:08.63#ibcon#read 3, iclass 33, count 2 2006.197.08:04:08.63#ibcon#about to read 4, iclass 33, count 2 2006.197.08:04:08.63#ibcon#read 4, iclass 33, count 2 2006.197.08:04:08.63#ibcon#about to read 5, iclass 33, count 2 2006.197.08:04:08.63#ibcon#read 5, iclass 33, count 2 2006.197.08:04:08.63#ibcon#about to read 6, iclass 33, count 2 2006.197.08:04:08.63#ibcon#read 6, iclass 33, count 2 2006.197.08:04:08.63#ibcon#end of sib2, iclass 33, count 2 2006.197.08:04:08.63#ibcon#*after write, iclass 33, count 2 2006.197.08:04:08.63#ibcon#*before return 0, iclass 33, count 2 2006.197.08:04:08.63#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.197.08:04:08.63#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.197.08:04:08.63#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.197.08:04:08.63#ibcon#ireg 7 cls_cnt 0 2006.197.08:04:08.63#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.197.08:04:08.75#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.197.08:04:08.75#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.197.08:04:08.75#ibcon#enter wrdev, iclass 33, count 0 2006.197.08:04:08.75#ibcon#first serial, iclass 33, count 0 2006.197.08:04:08.75#ibcon#enter sib2, iclass 33, count 0 2006.197.08:04:08.75#ibcon#flushed, iclass 33, count 0 2006.197.08:04:08.75#ibcon#about to write, iclass 33, count 0 2006.197.08:04:08.75#ibcon#wrote, iclass 33, count 0 2006.197.08:04:08.75#ibcon#about to read 3, iclass 33, count 0 2006.197.08:04:08.77#ibcon#read 3, iclass 33, count 0 2006.197.08:04:08.77#ibcon#about to read 4, iclass 33, count 0 2006.197.08:04:08.77#ibcon#read 4, iclass 33, count 0 2006.197.08:04:08.77#ibcon#about to read 5, iclass 33, count 0 2006.197.08:04:08.77#ibcon#read 5, iclass 33, count 0 2006.197.08:04:08.77#ibcon#about to read 6, iclass 33, count 0 2006.197.08:04:08.77#ibcon#read 6, iclass 33, count 0 2006.197.08:04:08.77#ibcon#end of sib2, iclass 33, count 0 2006.197.08:04:08.77#ibcon#*mode == 0, iclass 33, count 0 2006.197.08:04:08.77#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.197.08:04:08.77#ibcon#[25=USB\r\n] 2006.197.08:04:08.77#ibcon#*before write, iclass 33, count 0 2006.197.08:04:08.77#ibcon#enter sib2, iclass 33, count 0 2006.197.08:04:08.77#ibcon#flushed, iclass 33, count 0 2006.197.08:04:08.77#ibcon#about to write, iclass 33, count 0 2006.197.08:04:08.77#ibcon#wrote, iclass 33, count 0 2006.197.08:04:08.77#ibcon#about to read 3, iclass 33, count 0 2006.197.08:04:08.80#ibcon#read 3, iclass 33, count 0 2006.197.08:04:08.80#ibcon#about to read 4, iclass 33, count 0 2006.197.08:04:08.80#ibcon#read 4, iclass 33, count 0 2006.197.08:04:08.80#ibcon#about to read 5, iclass 33, count 0 2006.197.08:04:08.80#ibcon#read 5, iclass 33, count 0 2006.197.08:04:08.80#ibcon#about to read 6, iclass 33, count 0 2006.197.08:04:08.80#ibcon#read 6, iclass 33, count 0 2006.197.08:04:08.80#ibcon#end of sib2, iclass 33, count 0 2006.197.08:04:08.80#ibcon#*after write, iclass 33, count 0 2006.197.08:04:08.80#ibcon#*before return 0, iclass 33, count 0 2006.197.08:04:08.80#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.197.08:04:08.80#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.197.08:04:08.80#ibcon#about to clear, iclass 33 cls_cnt 0 2006.197.08:04:08.80#ibcon#cleared, iclass 33 cls_cnt 0 2006.197.08:04:08.80$vc4f8/valo=5,652.99 2006.197.08:04:08.80#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.197.08:04:08.80#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.197.08:04:08.80#ibcon#ireg 17 cls_cnt 0 2006.197.08:04:08.80#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.197.08:04:08.80#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.197.08:04:08.80#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.197.08:04:08.80#ibcon#enter wrdev, iclass 35, count 0 2006.197.08:04:08.80#ibcon#first serial, iclass 35, count 0 2006.197.08:04:08.80#ibcon#enter sib2, iclass 35, count 0 2006.197.08:04:08.80#ibcon#flushed, iclass 35, count 0 2006.197.08:04:08.80#ibcon#about to write, iclass 35, count 0 2006.197.08:04:08.80#ibcon#wrote, iclass 35, count 0 2006.197.08:04:08.80#ibcon#about to read 3, iclass 35, count 0 2006.197.08:04:08.82#ibcon#read 3, iclass 35, count 0 2006.197.08:04:08.82#ibcon#about to read 4, iclass 35, count 0 2006.197.08:04:08.82#ibcon#read 4, iclass 35, count 0 2006.197.08:04:08.82#ibcon#about to read 5, iclass 35, count 0 2006.197.08:04:08.82#ibcon#read 5, iclass 35, count 0 2006.197.08:04:08.82#ibcon#about to read 6, iclass 35, count 0 2006.197.08:04:08.82#ibcon#read 6, iclass 35, count 0 2006.197.08:04:08.82#ibcon#end of sib2, iclass 35, count 0 2006.197.08:04:08.82#ibcon#*mode == 0, iclass 35, count 0 2006.197.08:04:08.82#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.197.08:04:08.82#ibcon#[26=FRQ=05,652.99\r\n] 2006.197.08:04:08.82#ibcon#*before write, iclass 35, count 0 2006.197.08:04:08.82#ibcon#enter sib2, iclass 35, count 0 2006.197.08:04:08.82#ibcon#flushed, iclass 35, count 0 2006.197.08:04:08.82#ibcon#about to write, iclass 35, count 0 2006.197.08:04:08.82#ibcon#wrote, iclass 35, count 0 2006.197.08:04:08.82#ibcon#about to read 3, iclass 35, count 0 2006.197.08:04:08.86#ibcon#read 3, iclass 35, count 0 2006.197.08:04:08.86#ibcon#about to read 4, iclass 35, count 0 2006.197.08:04:08.86#ibcon#read 4, iclass 35, count 0 2006.197.08:04:08.86#ibcon#about to read 5, iclass 35, count 0 2006.197.08:04:08.86#ibcon#read 5, iclass 35, count 0 2006.197.08:04:08.86#ibcon#about to read 6, iclass 35, count 0 2006.197.08:04:08.86#ibcon#read 6, iclass 35, count 0 2006.197.08:04:08.86#ibcon#end of sib2, iclass 35, count 0 2006.197.08:04:08.86#ibcon#*after write, iclass 35, count 0 2006.197.08:04:08.86#ibcon#*before return 0, iclass 35, count 0 2006.197.08:04:08.86#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.197.08:04:08.86#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.197.08:04:08.86#ibcon#about to clear, iclass 35 cls_cnt 0 2006.197.08:04:08.86#ibcon#cleared, iclass 35 cls_cnt 0 2006.197.08:04:08.86$vc4f8/va=5,7 2006.197.08:04:08.86#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.197.08:04:08.86#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.197.08:04:08.86#ibcon#ireg 11 cls_cnt 2 2006.197.08:04:08.86#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.197.08:04:08.92#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.197.08:04:08.92#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.197.08:04:08.92#ibcon#enter wrdev, iclass 37, count 2 2006.197.08:04:08.92#ibcon#first serial, iclass 37, count 2 2006.197.08:04:08.92#ibcon#enter sib2, iclass 37, count 2 2006.197.08:04:08.92#ibcon#flushed, iclass 37, count 2 2006.197.08:04:08.92#ibcon#about to write, iclass 37, count 2 2006.197.08:04:08.92#ibcon#wrote, iclass 37, count 2 2006.197.08:04:08.92#ibcon#about to read 3, iclass 37, count 2 2006.197.08:04:08.94#ibcon#read 3, iclass 37, count 2 2006.197.08:04:08.94#ibcon#about to read 4, iclass 37, count 2 2006.197.08:04:08.94#ibcon#read 4, iclass 37, count 2 2006.197.08:04:08.94#ibcon#about to read 5, iclass 37, count 2 2006.197.08:04:08.94#ibcon#read 5, iclass 37, count 2 2006.197.08:04:08.94#ibcon#about to read 6, iclass 37, count 2 2006.197.08:04:08.94#ibcon#read 6, iclass 37, count 2 2006.197.08:04:08.94#ibcon#end of sib2, iclass 37, count 2 2006.197.08:04:08.94#ibcon#*mode == 0, iclass 37, count 2 2006.197.08:04:08.94#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.197.08:04:08.94#ibcon#[25=AT05-07\r\n] 2006.197.08:04:08.94#ibcon#*before write, iclass 37, count 2 2006.197.08:04:08.94#ibcon#enter sib2, iclass 37, count 2 2006.197.08:04:08.94#ibcon#flushed, iclass 37, count 2 2006.197.08:04:08.94#ibcon#about to write, iclass 37, count 2 2006.197.08:04:08.94#ibcon#wrote, iclass 37, count 2 2006.197.08:04:08.94#ibcon#about to read 3, iclass 37, count 2 2006.197.08:04:08.97#ibcon#read 3, iclass 37, count 2 2006.197.08:04:08.97#ibcon#about to read 4, iclass 37, count 2 2006.197.08:04:08.97#ibcon#read 4, iclass 37, count 2 2006.197.08:04:08.97#ibcon#about to read 5, iclass 37, count 2 2006.197.08:04:08.97#ibcon#read 5, iclass 37, count 2 2006.197.08:04:08.97#ibcon#about to read 6, iclass 37, count 2 2006.197.08:04:08.97#ibcon#read 6, iclass 37, count 2 2006.197.08:04:08.97#ibcon#end of sib2, iclass 37, count 2 2006.197.08:04:08.97#ibcon#*after write, iclass 37, count 2 2006.197.08:04:08.97#ibcon#*before return 0, iclass 37, count 2 2006.197.08:04:08.97#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.197.08:04:08.97#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.197.08:04:08.97#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.197.08:04:08.97#ibcon#ireg 7 cls_cnt 0 2006.197.08:04:08.97#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.197.08:04:09.09#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.197.08:04:09.09#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.197.08:04:09.09#ibcon#enter wrdev, iclass 37, count 0 2006.197.08:04:09.09#ibcon#first serial, iclass 37, count 0 2006.197.08:04:09.09#ibcon#enter sib2, iclass 37, count 0 2006.197.08:04:09.09#ibcon#flushed, iclass 37, count 0 2006.197.08:04:09.09#ibcon#about to write, iclass 37, count 0 2006.197.08:04:09.09#ibcon#wrote, iclass 37, count 0 2006.197.08:04:09.09#ibcon#about to read 3, iclass 37, count 0 2006.197.08:04:09.11#ibcon#read 3, iclass 37, count 0 2006.197.08:04:09.11#ibcon#about to read 4, iclass 37, count 0 2006.197.08:04:09.11#ibcon#read 4, iclass 37, count 0 2006.197.08:04:09.11#ibcon#about to read 5, iclass 37, count 0 2006.197.08:04:09.11#ibcon#read 5, iclass 37, count 0 2006.197.08:04:09.11#ibcon#about to read 6, iclass 37, count 0 2006.197.08:04:09.11#ibcon#read 6, iclass 37, count 0 2006.197.08:04:09.11#ibcon#end of sib2, iclass 37, count 0 2006.197.08:04:09.11#ibcon#*mode == 0, iclass 37, count 0 2006.197.08:04:09.11#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.197.08:04:09.11#ibcon#[25=USB\r\n] 2006.197.08:04:09.11#ibcon#*before write, iclass 37, count 0 2006.197.08:04:09.11#ibcon#enter sib2, iclass 37, count 0 2006.197.08:04:09.11#ibcon#flushed, iclass 37, count 0 2006.197.08:04:09.11#ibcon#about to write, iclass 37, count 0 2006.197.08:04:09.11#ibcon#wrote, iclass 37, count 0 2006.197.08:04:09.11#ibcon#about to read 3, iclass 37, count 0 2006.197.08:04:09.14#ibcon#read 3, iclass 37, count 0 2006.197.08:04:09.14#ibcon#about to read 4, iclass 37, count 0 2006.197.08:04:09.14#ibcon#read 4, iclass 37, count 0 2006.197.08:04:09.14#ibcon#about to read 5, iclass 37, count 0 2006.197.08:04:09.14#ibcon#read 5, iclass 37, count 0 2006.197.08:04:09.14#ibcon#about to read 6, iclass 37, count 0 2006.197.08:04:09.14#ibcon#read 6, iclass 37, count 0 2006.197.08:04:09.14#ibcon#end of sib2, iclass 37, count 0 2006.197.08:04:09.14#ibcon#*after write, iclass 37, count 0 2006.197.08:04:09.14#ibcon#*before return 0, iclass 37, count 0 2006.197.08:04:09.14#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.197.08:04:09.14#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.197.08:04:09.14#ibcon#about to clear, iclass 37 cls_cnt 0 2006.197.08:04:09.14#ibcon#cleared, iclass 37 cls_cnt 0 2006.197.08:04:09.14$vc4f8/valo=6,772.99 2006.197.08:04:09.14#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.197.08:04:09.14#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.197.08:04:09.14#ibcon#ireg 17 cls_cnt 0 2006.197.08:04:09.14#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.197.08:04:09.14#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.197.08:04:09.14#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.197.08:04:09.14#ibcon#enter wrdev, iclass 39, count 0 2006.197.08:04:09.14#ibcon#first serial, iclass 39, count 0 2006.197.08:04:09.14#ibcon#enter sib2, iclass 39, count 0 2006.197.08:04:09.14#ibcon#flushed, iclass 39, count 0 2006.197.08:04:09.14#ibcon#about to write, iclass 39, count 0 2006.197.08:04:09.14#ibcon#wrote, iclass 39, count 0 2006.197.08:04:09.14#ibcon#about to read 3, iclass 39, count 0 2006.197.08:04:09.16#ibcon#read 3, iclass 39, count 0 2006.197.08:04:09.16#ibcon#about to read 4, iclass 39, count 0 2006.197.08:04:09.16#ibcon#read 4, iclass 39, count 0 2006.197.08:04:09.16#ibcon#about to read 5, iclass 39, count 0 2006.197.08:04:09.16#ibcon#read 5, iclass 39, count 0 2006.197.08:04:09.16#ibcon#about to read 6, iclass 39, count 0 2006.197.08:04:09.16#ibcon#read 6, iclass 39, count 0 2006.197.08:04:09.16#ibcon#end of sib2, iclass 39, count 0 2006.197.08:04:09.16#ibcon#*mode == 0, iclass 39, count 0 2006.197.08:04:09.16#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.197.08:04:09.16#ibcon#[26=FRQ=06,772.99\r\n] 2006.197.08:04:09.16#ibcon#*before write, iclass 39, count 0 2006.197.08:04:09.16#ibcon#enter sib2, iclass 39, count 0 2006.197.08:04:09.16#ibcon#flushed, iclass 39, count 0 2006.197.08:04:09.16#ibcon#about to write, iclass 39, count 0 2006.197.08:04:09.16#ibcon#wrote, iclass 39, count 0 2006.197.08:04:09.16#ibcon#about to read 3, iclass 39, count 0 2006.197.08:04:09.20#ibcon#read 3, iclass 39, count 0 2006.197.08:04:09.20#ibcon#about to read 4, iclass 39, count 0 2006.197.08:04:09.20#ibcon#read 4, iclass 39, count 0 2006.197.08:04:09.20#ibcon#about to read 5, iclass 39, count 0 2006.197.08:04:09.20#ibcon#read 5, iclass 39, count 0 2006.197.08:04:09.20#ibcon#about to read 6, iclass 39, count 0 2006.197.08:04:09.20#ibcon#read 6, iclass 39, count 0 2006.197.08:04:09.20#ibcon#end of sib2, iclass 39, count 0 2006.197.08:04:09.20#ibcon#*after write, iclass 39, count 0 2006.197.08:04:09.20#ibcon#*before return 0, iclass 39, count 0 2006.197.08:04:09.20#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.197.08:04:09.20#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.197.08:04:09.20#ibcon#about to clear, iclass 39 cls_cnt 0 2006.197.08:04:09.20#ibcon#cleared, iclass 39 cls_cnt 0 2006.197.08:04:09.20$vc4f8/va=6,6 2006.197.08:04:09.20#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.197.08:04:09.20#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.197.08:04:09.20#ibcon#ireg 11 cls_cnt 2 2006.197.08:04:09.20#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.197.08:04:09.26#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.197.08:04:09.26#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.197.08:04:09.26#ibcon#enter wrdev, iclass 3, count 2 2006.197.08:04:09.26#ibcon#first serial, iclass 3, count 2 2006.197.08:04:09.26#ibcon#enter sib2, iclass 3, count 2 2006.197.08:04:09.26#ibcon#flushed, iclass 3, count 2 2006.197.08:04:09.26#ibcon#about to write, iclass 3, count 2 2006.197.08:04:09.26#ibcon#wrote, iclass 3, count 2 2006.197.08:04:09.26#ibcon#about to read 3, iclass 3, count 2 2006.197.08:04:09.28#ibcon#read 3, iclass 3, count 2 2006.197.08:04:09.28#ibcon#about to read 4, iclass 3, count 2 2006.197.08:04:09.28#ibcon#read 4, iclass 3, count 2 2006.197.08:04:09.28#ibcon#about to read 5, iclass 3, count 2 2006.197.08:04:09.28#ibcon#read 5, iclass 3, count 2 2006.197.08:04:09.28#ibcon#about to read 6, iclass 3, count 2 2006.197.08:04:09.28#ibcon#read 6, iclass 3, count 2 2006.197.08:04:09.28#ibcon#end of sib2, iclass 3, count 2 2006.197.08:04:09.28#ibcon#*mode == 0, iclass 3, count 2 2006.197.08:04:09.28#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.197.08:04:09.28#ibcon#[25=AT06-06\r\n] 2006.197.08:04:09.28#ibcon#*before write, iclass 3, count 2 2006.197.08:04:09.28#ibcon#enter sib2, iclass 3, count 2 2006.197.08:04:09.28#ibcon#flushed, iclass 3, count 2 2006.197.08:04:09.28#ibcon#about to write, iclass 3, count 2 2006.197.08:04:09.28#ibcon#wrote, iclass 3, count 2 2006.197.08:04:09.28#ibcon#about to read 3, iclass 3, count 2 2006.197.08:04:09.31#ibcon#read 3, iclass 3, count 2 2006.197.08:04:09.31#ibcon#about to read 4, iclass 3, count 2 2006.197.08:04:09.31#ibcon#read 4, iclass 3, count 2 2006.197.08:04:09.31#ibcon#about to read 5, iclass 3, count 2 2006.197.08:04:09.31#ibcon#read 5, iclass 3, count 2 2006.197.08:04:09.31#ibcon#about to read 6, iclass 3, count 2 2006.197.08:04:09.31#ibcon#read 6, iclass 3, count 2 2006.197.08:04:09.31#ibcon#end of sib2, iclass 3, count 2 2006.197.08:04:09.31#ibcon#*after write, iclass 3, count 2 2006.197.08:04:09.31#ibcon#*before return 0, iclass 3, count 2 2006.197.08:04:09.31#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.197.08:04:09.31#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.197.08:04:09.31#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.197.08:04:09.31#ibcon#ireg 7 cls_cnt 0 2006.197.08:04:09.31#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.197.08:04:09.43#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.197.08:04:09.43#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.197.08:04:09.43#ibcon#enter wrdev, iclass 3, count 0 2006.197.08:04:09.43#ibcon#first serial, iclass 3, count 0 2006.197.08:04:09.43#ibcon#enter sib2, iclass 3, count 0 2006.197.08:04:09.43#ibcon#flushed, iclass 3, count 0 2006.197.08:04:09.43#ibcon#about to write, iclass 3, count 0 2006.197.08:04:09.43#ibcon#wrote, iclass 3, count 0 2006.197.08:04:09.43#ibcon#about to read 3, iclass 3, count 0 2006.197.08:04:09.45#ibcon#read 3, iclass 3, count 0 2006.197.08:04:09.45#ibcon#about to read 4, iclass 3, count 0 2006.197.08:04:09.45#ibcon#read 4, iclass 3, count 0 2006.197.08:04:09.45#ibcon#about to read 5, iclass 3, count 0 2006.197.08:04:09.45#ibcon#read 5, iclass 3, count 0 2006.197.08:04:09.45#ibcon#about to read 6, iclass 3, count 0 2006.197.08:04:09.45#ibcon#read 6, iclass 3, count 0 2006.197.08:04:09.45#ibcon#end of sib2, iclass 3, count 0 2006.197.08:04:09.45#ibcon#*mode == 0, iclass 3, count 0 2006.197.08:04:09.45#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.197.08:04:09.45#ibcon#[25=USB\r\n] 2006.197.08:04:09.45#ibcon#*before write, iclass 3, count 0 2006.197.08:04:09.45#ibcon#enter sib2, iclass 3, count 0 2006.197.08:04:09.45#ibcon#flushed, iclass 3, count 0 2006.197.08:04:09.45#ibcon#about to write, iclass 3, count 0 2006.197.08:04:09.45#ibcon#wrote, iclass 3, count 0 2006.197.08:04:09.45#ibcon#about to read 3, iclass 3, count 0 2006.197.08:04:09.48#ibcon#read 3, iclass 3, count 0 2006.197.08:04:09.48#ibcon#about to read 4, iclass 3, count 0 2006.197.08:04:09.48#ibcon#read 4, iclass 3, count 0 2006.197.08:04:09.48#ibcon#about to read 5, iclass 3, count 0 2006.197.08:04:09.48#ibcon#read 5, iclass 3, count 0 2006.197.08:04:09.48#ibcon#about to read 6, iclass 3, count 0 2006.197.08:04:09.48#ibcon#read 6, iclass 3, count 0 2006.197.08:04:09.48#ibcon#end of sib2, iclass 3, count 0 2006.197.08:04:09.48#ibcon#*after write, iclass 3, count 0 2006.197.08:04:09.48#ibcon#*before return 0, iclass 3, count 0 2006.197.08:04:09.48#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.197.08:04:09.48#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.197.08:04:09.48#ibcon#about to clear, iclass 3 cls_cnt 0 2006.197.08:04:09.48#ibcon#cleared, iclass 3 cls_cnt 0 2006.197.08:04:09.48$vc4f8/valo=7,832.99 2006.197.08:04:09.48#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.197.08:04:09.48#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.197.08:04:09.48#ibcon#ireg 17 cls_cnt 0 2006.197.08:04:09.48#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.197.08:04:09.48#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.197.08:04:09.48#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.197.08:04:09.48#ibcon#enter wrdev, iclass 5, count 0 2006.197.08:04:09.48#ibcon#first serial, iclass 5, count 0 2006.197.08:04:09.48#ibcon#enter sib2, iclass 5, count 0 2006.197.08:04:09.48#ibcon#flushed, iclass 5, count 0 2006.197.08:04:09.48#ibcon#about to write, iclass 5, count 0 2006.197.08:04:09.48#ibcon#wrote, iclass 5, count 0 2006.197.08:04:09.48#ibcon#about to read 3, iclass 5, count 0 2006.197.08:04:09.50#ibcon#read 3, iclass 5, count 0 2006.197.08:04:09.50#ibcon#about to read 4, iclass 5, count 0 2006.197.08:04:09.50#ibcon#read 4, iclass 5, count 0 2006.197.08:04:09.50#ibcon#about to read 5, iclass 5, count 0 2006.197.08:04:09.50#ibcon#read 5, iclass 5, count 0 2006.197.08:04:09.50#ibcon#about to read 6, iclass 5, count 0 2006.197.08:04:09.50#ibcon#read 6, iclass 5, count 0 2006.197.08:04:09.50#ibcon#end of sib2, iclass 5, count 0 2006.197.08:04:09.50#ibcon#*mode == 0, iclass 5, count 0 2006.197.08:04:09.50#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.197.08:04:09.50#ibcon#[26=FRQ=07,832.99\r\n] 2006.197.08:04:09.50#ibcon#*before write, iclass 5, count 0 2006.197.08:04:09.50#ibcon#enter sib2, iclass 5, count 0 2006.197.08:04:09.50#ibcon#flushed, iclass 5, count 0 2006.197.08:04:09.50#ibcon#about to write, iclass 5, count 0 2006.197.08:04:09.50#ibcon#wrote, iclass 5, count 0 2006.197.08:04:09.50#ibcon#about to read 3, iclass 5, count 0 2006.197.08:04:09.54#ibcon#read 3, iclass 5, count 0 2006.197.08:04:09.54#ibcon#about to read 4, iclass 5, count 0 2006.197.08:04:09.54#ibcon#read 4, iclass 5, count 0 2006.197.08:04:09.54#ibcon#about to read 5, iclass 5, count 0 2006.197.08:04:09.54#ibcon#read 5, iclass 5, count 0 2006.197.08:04:09.54#ibcon#about to read 6, iclass 5, count 0 2006.197.08:04:09.54#ibcon#read 6, iclass 5, count 0 2006.197.08:04:09.54#ibcon#end of sib2, iclass 5, count 0 2006.197.08:04:09.54#ibcon#*after write, iclass 5, count 0 2006.197.08:04:09.54#ibcon#*before return 0, iclass 5, count 0 2006.197.08:04:09.54#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.197.08:04:09.54#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.197.08:04:09.54#ibcon#about to clear, iclass 5 cls_cnt 0 2006.197.08:04:09.54#ibcon#cleared, iclass 5 cls_cnt 0 2006.197.08:04:09.54$vc4f8/va=7,6 2006.197.08:04:09.54#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.197.08:04:09.54#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.197.08:04:09.54#ibcon#ireg 11 cls_cnt 2 2006.197.08:04:09.54#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.197.08:04:09.60#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.197.08:04:09.60#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.197.08:04:09.60#ibcon#enter wrdev, iclass 7, count 2 2006.197.08:04:09.60#ibcon#first serial, iclass 7, count 2 2006.197.08:04:09.60#ibcon#enter sib2, iclass 7, count 2 2006.197.08:04:09.60#ibcon#flushed, iclass 7, count 2 2006.197.08:04:09.60#ibcon#about to write, iclass 7, count 2 2006.197.08:04:09.60#ibcon#wrote, iclass 7, count 2 2006.197.08:04:09.60#ibcon#about to read 3, iclass 7, count 2 2006.197.08:04:09.62#ibcon#read 3, iclass 7, count 2 2006.197.08:04:09.62#ibcon#about to read 4, iclass 7, count 2 2006.197.08:04:09.62#ibcon#read 4, iclass 7, count 2 2006.197.08:04:09.62#ibcon#about to read 5, iclass 7, count 2 2006.197.08:04:09.62#ibcon#read 5, iclass 7, count 2 2006.197.08:04:09.62#ibcon#about to read 6, iclass 7, count 2 2006.197.08:04:09.62#ibcon#read 6, iclass 7, count 2 2006.197.08:04:09.62#ibcon#end of sib2, iclass 7, count 2 2006.197.08:04:09.62#ibcon#*mode == 0, iclass 7, count 2 2006.197.08:04:09.62#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.197.08:04:09.62#ibcon#[25=AT07-06\r\n] 2006.197.08:04:09.62#ibcon#*before write, iclass 7, count 2 2006.197.08:04:09.62#ibcon#enter sib2, iclass 7, count 2 2006.197.08:04:09.62#ibcon#flushed, iclass 7, count 2 2006.197.08:04:09.62#ibcon#about to write, iclass 7, count 2 2006.197.08:04:09.62#ibcon#wrote, iclass 7, count 2 2006.197.08:04:09.62#ibcon#about to read 3, iclass 7, count 2 2006.197.08:04:09.65#ibcon#read 3, iclass 7, count 2 2006.197.08:04:09.65#ibcon#about to read 4, iclass 7, count 2 2006.197.08:04:09.65#ibcon#read 4, iclass 7, count 2 2006.197.08:04:09.65#ibcon#about to read 5, iclass 7, count 2 2006.197.08:04:09.65#ibcon#read 5, iclass 7, count 2 2006.197.08:04:09.65#ibcon#about to read 6, iclass 7, count 2 2006.197.08:04:09.65#ibcon#read 6, iclass 7, count 2 2006.197.08:04:09.65#ibcon#end of sib2, iclass 7, count 2 2006.197.08:04:09.65#ibcon#*after write, iclass 7, count 2 2006.197.08:04:09.65#ibcon#*before return 0, iclass 7, count 2 2006.197.08:04:09.65#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.197.08:04:09.65#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.197.08:04:09.65#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.197.08:04:09.65#ibcon#ireg 7 cls_cnt 0 2006.197.08:04:09.65#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.197.08:04:09.77#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.197.08:04:09.77#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.197.08:04:09.77#ibcon#enter wrdev, iclass 7, count 0 2006.197.08:04:09.77#ibcon#first serial, iclass 7, count 0 2006.197.08:04:09.77#ibcon#enter sib2, iclass 7, count 0 2006.197.08:04:09.77#ibcon#flushed, iclass 7, count 0 2006.197.08:04:09.77#ibcon#about to write, iclass 7, count 0 2006.197.08:04:09.77#ibcon#wrote, iclass 7, count 0 2006.197.08:04:09.77#ibcon#about to read 3, iclass 7, count 0 2006.197.08:04:09.79#ibcon#read 3, iclass 7, count 0 2006.197.08:04:09.79#ibcon#about to read 4, iclass 7, count 0 2006.197.08:04:09.79#ibcon#read 4, iclass 7, count 0 2006.197.08:04:09.79#ibcon#about to read 5, iclass 7, count 0 2006.197.08:04:09.79#ibcon#read 5, iclass 7, count 0 2006.197.08:04:09.79#ibcon#about to read 6, iclass 7, count 0 2006.197.08:04:09.79#ibcon#read 6, iclass 7, count 0 2006.197.08:04:09.79#ibcon#end of sib2, iclass 7, count 0 2006.197.08:04:09.79#ibcon#*mode == 0, iclass 7, count 0 2006.197.08:04:09.79#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.197.08:04:09.79#ibcon#[25=USB\r\n] 2006.197.08:04:09.79#ibcon#*before write, iclass 7, count 0 2006.197.08:04:09.79#ibcon#enter sib2, iclass 7, count 0 2006.197.08:04:09.79#ibcon#flushed, iclass 7, count 0 2006.197.08:04:09.79#ibcon#about to write, iclass 7, count 0 2006.197.08:04:09.79#ibcon#wrote, iclass 7, count 0 2006.197.08:04:09.79#ibcon#about to read 3, iclass 7, count 0 2006.197.08:04:09.82#ibcon#read 3, iclass 7, count 0 2006.197.08:04:09.82#ibcon#about to read 4, iclass 7, count 0 2006.197.08:04:09.82#ibcon#read 4, iclass 7, count 0 2006.197.08:04:09.82#ibcon#about to read 5, iclass 7, count 0 2006.197.08:04:09.82#ibcon#read 5, iclass 7, count 0 2006.197.08:04:09.82#ibcon#about to read 6, iclass 7, count 0 2006.197.08:04:09.82#ibcon#read 6, iclass 7, count 0 2006.197.08:04:09.82#ibcon#end of sib2, iclass 7, count 0 2006.197.08:04:09.82#ibcon#*after write, iclass 7, count 0 2006.197.08:04:09.82#ibcon#*before return 0, iclass 7, count 0 2006.197.08:04:09.82#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.197.08:04:09.82#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.197.08:04:09.82#ibcon#about to clear, iclass 7 cls_cnt 0 2006.197.08:04:09.82#ibcon#cleared, iclass 7 cls_cnt 0 2006.197.08:04:09.82$vc4f8/valo=8,852.99 2006.197.08:04:09.82#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.197.08:04:09.82#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.197.08:04:09.82#ibcon#ireg 17 cls_cnt 0 2006.197.08:04:09.82#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.197.08:04:09.82#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.197.08:04:09.82#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.197.08:04:09.82#ibcon#enter wrdev, iclass 11, count 0 2006.197.08:04:09.82#ibcon#first serial, iclass 11, count 0 2006.197.08:04:09.82#ibcon#enter sib2, iclass 11, count 0 2006.197.08:04:09.82#ibcon#flushed, iclass 11, count 0 2006.197.08:04:09.82#ibcon#about to write, iclass 11, count 0 2006.197.08:04:09.82#ibcon#wrote, iclass 11, count 0 2006.197.08:04:09.82#ibcon#about to read 3, iclass 11, count 0 2006.197.08:04:09.84#ibcon#read 3, iclass 11, count 0 2006.197.08:04:09.84#ibcon#about to read 4, iclass 11, count 0 2006.197.08:04:09.84#ibcon#read 4, iclass 11, count 0 2006.197.08:04:09.84#ibcon#about to read 5, iclass 11, count 0 2006.197.08:04:09.84#ibcon#read 5, iclass 11, count 0 2006.197.08:04:09.84#ibcon#about to read 6, iclass 11, count 0 2006.197.08:04:09.84#ibcon#read 6, iclass 11, count 0 2006.197.08:04:09.84#ibcon#end of sib2, iclass 11, count 0 2006.197.08:04:09.84#ibcon#*mode == 0, iclass 11, count 0 2006.197.08:04:09.84#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.197.08:04:09.84#ibcon#[26=FRQ=08,852.99\r\n] 2006.197.08:04:09.84#ibcon#*before write, iclass 11, count 0 2006.197.08:04:09.84#ibcon#enter sib2, iclass 11, count 0 2006.197.08:04:09.84#ibcon#flushed, iclass 11, count 0 2006.197.08:04:09.84#ibcon#about to write, iclass 11, count 0 2006.197.08:04:09.84#ibcon#wrote, iclass 11, count 0 2006.197.08:04:09.84#ibcon#about to read 3, iclass 11, count 0 2006.197.08:04:09.88#ibcon#read 3, iclass 11, count 0 2006.197.08:04:09.88#ibcon#about to read 4, iclass 11, count 0 2006.197.08:04:09.88#ibcon#read 4, iclass 11, count 0 2006.197.08:04:09.88#ibcon#about to read 5, iclass 11, count 0 2006.197.08:04:09.88#ibcon#read 5, iclass 11, count 0 2006.197.08:04:09.88#ibcon#about to read 6, iclass 11, count 0 2006.197.08:04:09.88#ibcon#read 6, iclass 11, count 0 2006.197.08:04:09.88#ibcon#end of sib2, iclass 11, count 0 2006.197.08:04:09.88#ibcon#*after write, iclass 11, count 0 2006.197.08:04:09.88#ibcon#*before return 0, iclass 11, count 0 2006.197.08:04:09.88#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.197.08:04:09.88#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.197.08:04:09.88#ibcon#about to clear, iclass 11 cls_cnt 0 2006.197.08:04:09.88#ibcon#cleared, iclass 11 cls_cnt 0 2006.197.08:04:09.88$vc4f8/va=8,7 2006.197.08:04:09.88#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.197.08:04:09.88#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.197.08:04:09.88#ibcon#ireg 11 cls_cnt 2 2006.197.08:04:09.88#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.197.08:04:09.94#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.197.08:04:09.94#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.197.08:04:09.94#ibcon#enter wrdev, iclass 13, count 2 2006.197.08:04:09.94#ibcon#first serial, iclass 13, count 2 2006.197.08:04:09.94#ibcon#enter sib2, iclass 13, count 2 2006.197.08:04:09.94#ibcon#flushed, iclass 13, count 2 2006.197.08:04:09.94#ibcon#about to write, iclass 13, count 2 2006.197.08:04:09.94#ibcon#wrote, iclass 13, count 2 2006.197.08:04:09.94#ibcon#about to read 3, iclass 13, count 2 2006.197.08:04:09.96#ibcon#read 3, iclass 13, count 2 2006.197.08:04:09.96#ibcon#about to read 4, iclass 13, count 2 2006.197.08:04:09.96#ibcon#read 4, iclass 13, count 2 2006.197.08:04:09.96#ibcon#about to read 5, iclass 13, count 2 2006.197.08:04:09.96#ibcon#read 5, iclass 13, count 2 2006.197.08:04:09.96#ibcon#about to read 6, iclass 13, count 2 2006.197.08:04:09.96#ibcon#read 6, iclass 13, count 2 2006.197.08:04:09.96#ibcon#end of sib2, iclass 13, count 2 2006.197.08:04:09.96#ibcon#*mode == 0, iclass 13, count 2 2006.197.08:04:09.96#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.197.08:04:09.96#ibcon#[25=AT08-07\r\n] 2006.197.08:04:09.96#ibcon#*before write, iclass 13, count 2 2006.197.08:04:09.96#ibcon#enter sib2, iclass 13, count 2 2006.197.08:04:09.96#ibcon#flushed, iclass 13, count 2 2006.197.08:04:09.96#ibcon#about to write, iclass 13, count 2 2006.197.08:04:09.96#ibcon#wrote, iclass 13, count 2 2006.197.08:04:09.96#ibcon#about to read 3, iclass 13, count 2 2006.197.08:04:09.99#ibcon#read 3, iclass 13, count 2 2006.197.08:04:09.99#ibcon#about to read 4, iclass 13, count 2 2006.197.08:04:09.99#ibcon#read 4, iclass 13, count 2 2006.197.08:04:09.99#ibcon#about to read 5, iclass 13, count 2 2006.197.08:04:09.99#ibcon#read 5, iclass 13, count 2 2006.197.08:04:09.99#ibcon#about to read 6, iclass 13, count 2 2006.197.08:04:09.99#ibcon#read 6, iclass 13, count 2 2006.197.08:04:09.99#ibcon#end of sib2, iclass 13, count 2 2006.197.08:04:09.99#ibcon#*after write, iclass 13, count 2 2006.197.08:04:09.99#ibcon#*before return 0, iclass 13, count 2 2006.197.08:04:09.99#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.197.08:04:09.99#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.197.08:04:09.99#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.197.08:04:09.99#ibcon#ireg 7 cls_cnt 0 2006.197.08:04:09.99#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.197.08:04:10.11#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.197.08:04:10.11#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.197.08:04:10.11#ibcon#enter wrdev, iclass 13, count 0 2006.197.08:04:10.11#ibcon#first serial, iclass 13, count 0 2006.197.08:04:10.11#ibcon#enter sib2, iclass 13, count 0 2006.197.08:04:10.11#ibcon#flushed, iclass 13, count 0 2006.197.08:04:10.11#ibcon#about to write, iclass 13, count 0 2006.197.08:04:10.11#ibcon#wrote, iclass 13, count 0 2006.197.08:04:10.11#ibcon#about to read 3, iclass 13, count 0 2006.197.08:04:10.13#ibcon#read 3, iclass 13, count 0 2006.197.08:04:10.13#ibcon#about to read 4, iclass 13, count 0 2006.197.08:04:10.13#ibcon#read 4, iclass 13, count 0 2006.197.08:04:10.13#ibcon#about to read 5, iclass 13, count 0 2006.197.08:04:10.13#ibcon#read 5, iclass 13, count 0 2006.197.08:04:10.13#ibcon#about to read 6, iclass 13, count 0 2006.197.08:04:10.13#ibcon#read 6, iclass 13, count 0 2006.197.08:04:10.13#ibcon#end of sib2, iclass 13, count 0 2006.197.08:04:10.13#ibcon#*mode == 0, iclass 13, count 0 2006.197.08:04:10.13#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.197.08:04:10.13#ibcon#[25=USB\r\n] 2006.197.08:04:10.13#ibcon#*before write, iclass 13, count 0 2006.197.08:04:10.13#ibcon#enter sib2, iclass 13, count 0 2006.197.08:04:10.13#ibcon#flushed, iclass 13, count 0 2006.197.08:04:10.13#ibcon#about to write, iclass 13, count 0 2006.197.08:04:10.13#ibcon#wrote, iclass 13, count 0 2006.197.08:04:10.13#ibcon#about to read 3, iclass 13, count 0 2006.197.08:04:10.16#ibcon#read 3, iclass 13, count 0 2006.197.08:04:10.16#ibcon#about to read 4, iclass 13, count 0 2006.197.08:04:10.16#ibcon#read 4, iclass 13, count 0 2006.197.08:04:10.16#ibcon#about to read 5, iclass 13, count 0 2006.197.08:04:10.16#ibcon#read 5, iclass 13, count 0 2006.197.08:04:10.16#ibcon#about to read 6, iclass 13, count 0 2006.197.08:04:10.16#ibcon#read 6, iclass 13, count 0 2006.197.08:04:10.16#ibcon#end of sib2, iclass 13, count 0 2006.197.08:04:10.16#ibcon#*after write, iclass 13, count 0 2006.197.08:04:10.16#ibcon#*before return 0, iclass 13, count 0 2006.197.08:04:10.16#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.197.08:04:10.16#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.197.08:04:10.16#ibcon#about to clear, iclass 13 cls_cnt 0 2006.197.08:04:10.16#ibcon#cleared, iclass 13 cls_cnt 0 2006.197.08:04:10.16$vc4f8/vblo=1,632.99 2006.197.08:04:10.16#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.197.08:04:10.16#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.197.08:04:10.16#ibcon#ireg 17 cls_cnt 0 2006.197.08:04:10.16#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.197.08:04:10.16#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.197.08:04:10.16#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.197.08:04:10.16#ibcon#enter wrdev, iclass 15, count 0 2006.197.08:04:10.16#ibcon#first serial, iclass 15, count 0 2006.197.08:04:10.16#ibcon#enter sib2, iclass 15, count 0 2006.197.08:04:10.16#ibcon#flushed, iclass 15, count 0 2006.197.08:04:10.16#ibcon#about to write, iclass 15, count 0 2006.197.08:04:10.16#ibcon#wrote, iclass 15, count 0 2006.197.08:04:10.16#ibcon#about to read 3, iclass 15, count 0 2006.197.08:04:10.18#ibcon#read 3, iclass 15, count 0 2006.197.08:04:10.18#ibcon#about to read 4, iclass 15, count 0 2006.197.08:04:10.18#ibcon#read 4, iclass 15, count 0 2006.197.08:04:10.18#ibcon#about to read 5, iclass 15, count 0 2006.197.08:04:10.18#ibcon#read 5, iclass 15, count 0 2006.197.08:04:10.18#ibcon#about to read 6, iclass 15, count 0 2006.197.08:04:10.18#ibcon#read 6, iclass 15, count 0 2006.197.08:04:10.18#ibcon#end of sib2, iclass 15, count 0 2006.197.08:04:10.18#ibcon#*mode == 0, iclass 15, count 0 2006.197.08:04:10.18#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.197.08:04:10.18#ibcon#[28=FRQ=01,632.99\r\n] 2006.197.08:04:10.18#ibcon#*before write, iclass 15, count 0 2006.197.08:04:10.18#ibcon#enter sib2, iclass 15, count 0 2006.197.08:04:10.18#ibcon#flushed, iclass 15, count 0 2006.197.08:04:10.18#ibcon#about to write, iclass 15, count 0 2006.197.08:04:10.18#ibcon#wrote, iclass 15, count 0 2006.197.08:04:10.18#ibcon#about to read 3, iclass 15, count 0 2006.197.08:04:10.22#ibcon#read 3, iclass 15, count 0 2006.197.08:04:10.22#ibcon#about to read 4, iclass 15, count 0 2006.197.08:04:10.22#ibcon#read 4, iclass 15, count 0 2006.197.08:04:10.22#ibcon#about to read 5, iclass 15, count 0 2006.197.08:04:10.22#ibcon#read 5, iclass 15, count 0 2006.197.08:04:10.22#ibcon#about to read 6, iclass 15, count 0 2006.197.08:04:10.22#ibcon#read 6, iclass 15, count 0 2006.197.08:04:10.22#ibcon#end of sib2, iclass 15, count 0 2006.197.08:04:10.22#ibcon#*after write, iclass 15, count 0 2006.197.08:04:10.22#ibcon#*before return 0, iclass 15, count 0 2006.197.08:04:10.22#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.197.08:04:10.22#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.197.08:04:10.22#ibcon#about to clear, iclass 15 cls_cnt 0 2006.197.08:04:10.22#ibcon#cleared, iclass 15 cls_cnt 0 2006.197.08:04:10.22$vc4f8/vb=1,4 2006.197.08:04:10.22#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.197.08:04:10.22#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.197.08:04:10.22#ibcon#ireg 11 cls_cnt 2 2006.197.08:04:10.22#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.197.08:04:10.22#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.197.08:04:10.22#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.197.08:04:10.22#ibcon#enter wrdev, iclass 17, count 2 2006.197.08:04:10.22#ibcon#first serial, iclass 17, count 2 2006.197.08:04:10.22#ibcon#enter sib2, iclass 17, count 2 2006.197.08:04:10.22#ibcon#flushed, iclass 17, count 2 2006.197.08:04:10.22#ibcon#about to write, iclass 17, count 2 2006.197.08:04:10.22#ibcon#wrote, iclass 17, count 2 2006.197.08:04:10.22#ibcon#about to read 3, iclass 17, count 2 2006.197.08:04:10.24#ibcon#read 3, iclass 17, count 2 2006.197.08:04:10.24#ibcon#about to read 4, iclass 17, count 2 2006.197.08:04:10.24#ibcon#read 4, iclass 17, count 2 2006.197.08:04:10.24#ibcon#about to read 5, iclass 17, count 2 2006.197.08:04:10.24#ibcon#read 5, iclass 17, count 2 2006.197.08:04:10.24#ibcon#about to read 6, iclass 17, count 2 2006.197.08:04:10.24#ibcon#read 6, iclass 17, count 2 2006.197.08:04:10.24#ibcon#end of sib2, iclass 17, count 2 2006.197.08:04:10.24#ibcon#*mode == 0, iclass 17, count 2 2006.197.08:04:10.24#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.197.08:04:10.24#ibcon#[27=AT01-04\r\n] 2006.197.08:04:10.24#ibcon#*before write, iclass 17, count 2 2006.197.08:04:10.24#ibcon#enter sib2, iclass 17, count 2 2006.197.08:04:10.24#ibcon#flushed, iclass 17, count 2 2006.197.08:04:10.24#ibcon#about to write, iclass 17, count 2 2006.197.08:04:10.24#ibcon#wrote, iclass 17, count 2 2006.197.08:04:10.24#ibcon#about to read 3, iclass 17, count 2 2006.197.08:04:10.27#ibcon#read 3, iclass 17, count 2 2006.197.08:04:10.27#ibcon#about to read 4, iclass 17, count 2 2006.197.08:04:10.27#ibcon#read 4, iclass 17, count 2 2006.197.08:04:10.27#ibcon#about to read 5, iclass 17, count 2 2006.197.08:04:10.27#ibcon#read 5, iclass 17, count 2 2006.197.08:04:10.27#ibcon#about to read 6, iclass 17, count 2 2006.197.08:04:10.27#ibcon#read 6, iclass 17, count 2 2006.197.08:04:10.27#ibcon#end of sib2, iclass 17, count 2 2006.197.08:04:10.27#ibcon#*after write, iclass 17, count 2 2006.197.08:04:10.27#ibcon#*before return 0, iclass 17, count 2 2006.197.08:04:10.27#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.197.08:04:10.27#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.197.08:04:10.27#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.197.08:04:10.27#ibcon#ireg 7 cls_cnt 0 2006.197.08:04:10.27#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.197.08:04:10.39#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.197.08:04:10.39#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.197.08:04:10.39#ibcon#enter wrdev, iclass 17, count 0 2006.197.08:04:10.39#ibcon#first serial, iclass 17, count 0 2006.197.08:04:10.39#ibcon#enter sib2, iclass 17, count 0 2006.197.08:04:10.39#ibcon#flushed, iclass 17, count 0 2006.197.08:04:10.39#ibcon#about to write, iclass 17, count 0 2006.197.08:04:10.39#ibcon#wrote, iclass 17, count 0 2006.197.08:04:10.39#ibcon#about to read 3, iclass 17, count 0 2006.197.08:04:10.41#ibcon#read 3, iclass 17, count 0 2006.197.08:04:10.41#ibcon#about to read 4, iclass 17, count 0 2006.197.08:04:10.41#ibcon#read 4, iclass 17, count 0 2006.197.08:04:10.41#ibcon#about to read 5, iclass 17, count 0 2006.197.08:04:10.41#ibcon#read 5, iclass 17, count 0 2006.197.08:04:10.41#ibcon#about to read 6, iclass 17, count 0 2006.197.08:04:10.41#ibcon#read 6, iclass 17, count 0 2006.197.08:04:10.41#ibcon#end of sib2, iclass 17, count 0 2006.197.08:04:10.41#ibcon#*mode == 0, iclass 17, count 0 2006.197.08:04:10.41#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.197.08:04:10.41#ibcon#[27=USB\r\n] 2006.197.08:04:10.41#ibcon#*before write, iclass 17, count 0 2006.197.08:04:10.41#ibcon#enter sib2, iclass 17, count 0 2006.197.08:04:10.41#ibcon#flushed, iclass 17, count 0 2006.197.08:04:10.41#ibcon#about to write, iclass 17, count 0 2006.197.08:04:10.41#ibcon#wrote, iclass 17, count 0 2006.197.08:04:10.41#ibcon#about to read 3, iclass 17, count 0 2006.197.08:04:10.44#ibcon#read 3, iclass 17, count 0 2006.197.08:04:10.44#ibcon#about to read 4, iclass 17, count 0 2006.197.08:04:10.44#ibcon#read 4, iclass 17, count 0 2006.197.08:04:10.44#ibcon#about to read 5, iclass 17, count 0 2006.197.08:04:10.44#ibcon#read 5, iclass 17, count 0 2006.197.08:04:10.44#ibcon#about to read 6, iclass 17, count 0 2006.197.08:04:10.44#ibcon#read 6, iclass 17, count 0 2006.197.08:04:10.44#ibcon#end of sib2, iclass 17, count 0 2006.197.08:04:10.44#ibcon#*after write, iclass 17, count 0 2006.197.08:04:10.44#ibcon#*before return 0, iclass 17, count 0 2006.197.08:04:10.44#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.197.08:04:10.44#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.197.08:04:10.44#ibcon#about to clear, iclass 17 cls_cnt 0 2006.197.08:04:10.44#ibcon#cleared, iclass 17 cls_cnt 0 2006.197.08:04:10.44$vc4f8/vblo=2,640.99 2006.197.08:04:10.44#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.197.08:04:10.44#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.197.08:04:10.44#ibcon#ireg 17 cls_cnt 0 2006.197.08:04:10.44#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.197.08:04:10.44#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.197.08:04:10.44#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.197.08:04:10.44#ibcon#enter wrdev, iclass 19, count 0 2006.197.08:04:10.44#ibcon#first serial, iclass 19, count 0 2006.197.08:04:10.44#ibcon#enter sib2, iclass 19, count 0 2006.197.08:04:10.44#ibcon#flushed, iclass 19, count 0 2006.197.08:04:10.44#ibcon#about to write, iclass 19, count 0 2006.197.08:04:10.44#ibcon#wrote, iclass 19, count 0 2006.197.08:04:10.44#ibcon#about to read 3, iclass 19, count 0 2006.197.08:04:10.46#ibcon#read 3, iclass 19, count 0 2006.197.08:04:10.46#ibcon#about to read 4, iclass 19, count 0 2006.197.08:04:10.46#ibcon#read 4, iclass 19, count 0 2006.197.08:04:10.46#ibcon#about to read 5, iclass 19, count 0 2006.197.08:04:10.46#ibcon#read 5, iclass 19, count 0 2006.197.08:04:10.46#ibcon#about to read 6, iclass 19, count 0 2006.197.08:04:10.46#ibcon#read 6, iclass 19, count 0 2006.197.08:04:10.46#ibcon#end of sib2, iclass 19, count 0 2006.197.08:04:10.46#ibcon#*mode == 0, iclass 19, count 0 2006.197.08:04:10.46#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.197.08:04:10.46#ibcon#[28=FRQ=02,640.99\r\n] 2006.197.08:04:10.46#ibcon#*before write, iclass 19, count 0 2006.197.08:04:10.46#ibcon#enter sib2, iclass 19, count 0 2006.197.08:04:10.46#ibcon#flushed, iclass 19, count 0 2006.197.08:04:10.46#ibcon#about to write, iclass 19, count 0 2006.197.08:04:10.46#ibcon#wrote, iclass 19, count 0 2006.197.08:04:10.46#ibcon#about to read 3, iclass 19, count 0 2006.197.08:04:10.50#ibcon#read 3, iclass 19, count 0 2006.197.08:04:10.50#ibcon#about to read 4, iclass 19, count 0 2006.197.08:04:10.50#ibcon#read 4, iclass 19, count 0 2006.197.08:04:10.50#ibcon#about to read 5, iclass 19, count 0 2006.197.08:04:10.50#ibcon#read 5, iclass 19, count 0 2006.197.08:04:10.50#ibcon#about to read 6, iclass 19, count 0 2006.197.08:04:10.50#ibcon#read 6, iclass 19, count 0 2006.197.08:04:10.50#ibcon#end of sib2, iclass 19, count 0 2006.197.08:04:10.50#ibcon#*after write, iclass 19, count 0 2006.197.08:04:10.50#ibcon#*before return 0, iclass 19, count 0 2006.197.08:04:10.50#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.197.08:04:10.50#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.197.08:04:10.50#ibcon#about to clear, iclass 19 cls_cnt 0 2006.197.08:04:10.50#ibcon#cleared, iclass 19 cls_cnt 0 2006.197.08:04:10.50$vc4f8/vb=2,4 2006.197.08:04:10.50#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.197.08:04:10.50#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.197.08:04:10.50#ibcon#ireg 11 cls_cnt 2 2006.197.08:04:10.50#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.197.08:04:10.56#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.197.08:04:10.56#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.197.08:04:10.56#ibcon#enter wrdev, iclass 21, count 2 2006.197.08:04:10.56#ibcon#first serial, iclass 21, count 2 2006.197.08:04:10.56#ibcon#enter sib2, iclass 21, count 2 2006.197.08:04:10.56#ibcon#flushed, iclass 21, count 2 2006.197.08:04:10.56#ibcon#about to write, iclass 21, count 2 2006.197.08:04:10.56#ibcon#wrote, iclass 21, count 2 2006.197.08:04:10.56#ibcon#about to read 3, iclass 21, count 2 2006.197.08:04:10.58#ibcon#read 3, iclass 21, count 2 2006.197.08:04:10.58#ibcon#about to read 4, iclass 21, count 2 2006.197.08:04:10.58#ibcon#read 4, iclass 21, count 2 2006.197.08:04:10.58#ibcon#about to read 5, iclass 21, count 2 2006.197.08:04:10.58#ibcon#read 5, iclass 21, count 2 2006.197.08:04:10.58#ibcon#about to read 6, iclass 21, count 2 2006.197.08:04:10.58#ibcon#read 6, iclass 21, count 2 2006.197.08:04:10.58#ibcon#end of sib2, iclass 21, count 2 2006.197.08:04:10.58#ibcon#*mode == 0, iclass 21, count 2 2006.197.08:04:10.58#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.197.08:04:10.58#ibcon#[27=AT02-04\r\n] 2006.197.08:04:10.58#ibcon#*before write, iclass 21, count 2 2006.197.08:04:10.58#ibcon#enter sib2, iclass 21, count 2 2006.197.08:04:10.58#ibcon#flushed, iclass 21, count 2 2006.197.08:04:10.58#ibcon#about to write, iclass 21, count 2 2006.197.08:04:10.58#ibcon#wrote, iclass 21, count 2 2006.197.08:04:10.58#ibcon#about to read 3, iclass 21, count 2 2006.197.08:04:10.61#ibcon#read 3, iclass 21, count 2 2006.197.08:04:10.61#ibcon#about to read 4, iclass 21, count 2 2006.197.08:04:10.61#ibcon#read 4, iclass 21, count 2 2006.197.08:04:10.61#ibcon#about to read 5, iclass 21, count 2 2006.197.08:04:10.61#ibcon#read 5, iclass 21, count 2 2006.197.08:04:10.61#ibcon#about to read 6, iclass 21, count 2 2006.197.08:04:10.61#ibcon#read 6, iclass 21, count 2 2006.197.08:04:10.61#ibcon#end of sib2, iclass 21, count 2 2006.197.08:04:10.61#ibcon#*after write, iclass 21, count 2 2006.197.08:04:10.61#ibcon#*before return 0, iclass 21, count 2 2006.197.08:04:10.61#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.197.08:04:10.61#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.197.08:04:10.61#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.197.08:04:10.61#ibcon#ireg 7 cls_cnt 0 2006.197.08:04:10.61#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.197.08:04:10.73#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.197.08:04:10.73#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.197.08:04:10.73#ibcon#enter wrdev, iclass 21, count 0 2006.197.08:04:10.73#ibcon#first serial, iclass 21, count 0 2006.197.08:04:10.73#ibcon#enter sib2, iclass 21, count 0 2006.197.08:04:10.73#ibcon#flushed, iclass 21, count 0 2006.197.08:04:10.73#ibcon#about to write, iclass 21, count 0 2006.197.08:04:10.73#ibcon#wrote, iclass 21, count 0 2006.197.08:04:10.73#ibcon#about to read 3, iclass 21, count 0 2006.197.08:04:10.75#ibcon#read 3, iclass 21, count 0 2006.197.08:04:10.75#ibcon#about to read 4, iclass 21, count 0 2006.197.08:04:10.75#ibcon#read 4, iclass 21, count 0 2006.197.08:04:10.75#ibcon#about to read 5, iclass 21, count 0 2006.197.08:04:10.75#ibcon#read 5, iclass 21, count 0 2006.197.08:04:10.75#ibcon#about to read 6, iclass 21, count 0 2006.197.08:04:10.75#ibcon#read 6, iclass 21, count 0 2006.197.08:04:10.75#ibcon#end of sib2, iclass 21, count 0 2006.197.08:04:10.75#ibcon#*mode == 0, iclass 21, count 0 2006.197.08:04:10.75#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.197.08:04:10.75#ibcon#[27=USB\r\n] 2006.197.08:04:10.75#ibcon#*before write, iclass 21, count 0 2006.197.08:04:10.75#ibcon#enter sib2, iclass 21, count 0 2006.197.08:04:10.75#ibcon#flushed, iclass 21, count 0 2006.197.08:04:10.75#ibcon#about to write, iclass 21, count 0 2006.197.08:04:10.75#ibcon#wrote, iclass 21, count 0 2006.197.08:04:10.75#ibcon#about to read 3, iclass 21, count 0 2006.197.08:04:10.78#ibcon#read 3, iclass 21, count 0 2006.197.08:04:10.78#ibcon#about to read 4, iclass 21, count 0 2006.197.08:04:10.78#ibcon#read 4, iclass 21, count 0 2006.197.08:04:10.78#ibcon#about to read 5, iclass 21, count 0 2006.197.08:04:10.78#ibcon#read 5, iclass 21, count 0 2006.197.08:04:10.78#ibcon#about to read 6, iclass 21, count 0 2006.197.08:04:10.78#ibcon#read 6, iclass 21, count 0 2006.197.08:04:10.78#ibcon#end of sib2, iclass 21, count 0 2006.197.08:04:10.78#ibcon#*after write, iclass 21, count 0 2006.197.08:04:10.78#ibcon#*before return 0, iclass 21, count 0 2006.197.08:04:10.78#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.197.08:04:10.78#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.197.08:04:10.78#ibcon#about to clear, iclass 21 cls_cnt 0 2006.197.08:04:10.78#ibcon#cleared, iclass 21 cls_cnt 0 2006.197.08:04:10.78$vc4f8/vblo=3,656.99 2006.197.08:04:10.78#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.197.08:04:10.78#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.197.08:04:10.78#ibcon#ireg 17 cls_cnt 0 2006.197.08:04:10.78#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.197.08:04:10.78#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.197.08:04:10.78#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.197.08:04:10.78#ibcon#enter wrdev, iclass 23, count 0 2006.197.08:04:10.78#ibcon#first serial, iclass 23, count 0 2006.197.08:04:10.78#ibcon#enter sib2, iclass 23, count 0 2006.197.08:04:10.78#ibcon#flushed, iclass 23, count 0 2006.197.08:04:10.78#ibcon#about to write, iclass 23, count 0 2006.197.08:04:10.78#ibcon#wrote, iclass 23, count 0 2006.197.08:04:10.78#ibcon#about to read 3, iclass 23, count 0 2006.197.08:04:10.80#ibcon#read 3, iclass 23, count 0 2006.197.08:04:10.80#ibcon#about to read 4, iclass 23, count 0 2006.197.08:04:10.80#ibcon#read 4, iclass 23, count 0 2006.197.08:04:10.80#ibcon#about to read 5, iclass 23, count 0 2006.197.08:04:10.80#ibcon#read 5, iclass 23, count 0 2006.197.08:04:10.80#ibcon#about to read 6, iclass 23, count 0 2006.197.08:04:10.80#ibcon#read 6, iclass 23, count 0 2006.197.08:04:10.80#ibcon#end of sib2, iclass 23, count 0 2006.197.08:04:10.80#ibcon#*mode == 0, iclass 23, count 0 2006.197.08:04:10.80#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.197.08:04:10.80#ibcon#[28=FRQ=03,656.99\r\n] 2006.197.08:04:10.80#ibcon#*before write, iclass 23, count 0 2006.197.08:04:10.80#ibcon#enter sib2, iclass 23, count 0 2006.197.08:04:10.80#ibcon#flushed, iclass 23, count 0 2006.197.08:04:10.80#ibcon#about to write, iclass 23, count 0 2006.197.08:04:10.80#ibcon#wrote, iclass 23, count 0 2006.197.08:04:10.80#ibcon#about to read 3, iclass 23, count 0 2006.197.08:04:10.84#ibcon#read 3, iclass 23, count 0 2006.197.08:04:10.84#ibcon#about to read 4, iclass 23, count 0 2006.197.08:04:10.84#ibcon#read 4, iclass 23, count 0 2006.197.08:04:10.84#ibcon#about to read 5, iclass 23, count 0 2006.197.08:04:10.84#ibcon#read 5, iclass 23, count 0 2006.197.08:04:10.84#ibcon#about to read 6, iclass 23, count 0 2006.197.08:04:10.84#ibcon#read 6, iclass 23, count 0 2006.197.08:04:10.84#ibcon#end of sib2, iclass 23, count 0 2006.197.08:04:10.84#ibcon#*after write, iclass 23, count 0 2006.197.08:04:10.84#ibcon#*before return 0, iclass 23, count 0 2006.197.08:04:10.84#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.197.08:04:10.84#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.197.08:04:10.84#ibcon#about to clear, iclass 23 cls_cnt 0 2006.197.08:04:10.84#ibcon#cleared, iclass 23 cls_cnt 0 2006.197.08:04:10.84$vc4f8/vb=3,4 2006.197.08:04:10.84#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.197.08:04:10.84#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.197.08:04:10.84#ibcon#ireg 11 cls_cnt 2 2006.197.08:04:10.84#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.197.08:04:10.90#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.197.08:04:10.90#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.197.08:04:10.90#ibcon#enter wrdev, iclass 25, count 2 2006.197.08:04:10.90#ibcon#first serial, iclass 25, count 2 2006.197.08:04:10.90#ibcon#enter sib2, iclass 25, count 2 2006.197.08:04:10.90#ibcon#flushed, iclass 25, count 2 2006.197.08:04:10.90#ibcon#about to write, iclass 25, count 2 2006.197.08:04:10.90#ibcon#wrote, iclass 25, count 2 2006.197.08:04:10.90#ibcon#about to read 3, iclass 25, count 2 2006.197.08:04:10.92#ibcon#read 3, iclass 25, count 2 2006.197.08:04:10.92#ibcon#about to read 4, iclass 25, count 2 2006.197.08:04:10.92#ibcon#read 4, iclass 25, count 2 2006.197.08:04:10.92#ibcon#about to read 5, iclass 25, count 2 2006.197.08:04:10.92#ibcon#read 5, iclass 25, count 2 2006.197.08:04:10.92#ibcon#about to read 6, iclass 25, count 2 2006.197.08:04:10.92#ibcon#read 6, iclass 25, count 2 2006.197.08:04:10.92#ibcon#end of sib2, iclass 25, count 2 2006.197.08:04:10.92#ibcon#*mode == 0, iclass 25, count 2 2006.197.08:04:10.92#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.197.08:04:10.92#ibcon#[27=AT03-04\r\n] 2006.197.08:04:10.92#ibcon#*before write, iclass 25, count 2 2006.197.08:04:10.92#ibcon#enter sib2, iclass 25, count 2 2006.197.08:04:10.92#ibcon#flushed, iclass 25, count 2 2006.197.08:04:10.92#ibcon#about to write, iclass 25, count 2 2006.197.08:04:10.92#ibcon#wrote, iclass 25, count 2 2006.197.08:04:10.92#ibcon#about to read 3, iclass 25, count 2 2006.197.08:04:10.95#ibcon#read 3, iclass 25, count 2 2006.197.08:04:10.95#ibcon#about to read 4, iclass 25, count 2 2006.197.08:04:10.95#ibcon#read 4, iclass 25, count 2 2006.197.08:04:10.95#ibcon#about to read 5, iclass 25, count 2 2006.197.08:04:10.95#ibcon#read 5, iclass 25, count 2 2006.197.08:04:10.95#ibcon#about to read 6, iclass 25, count 2 2006.197.08:04:10.95#ibcon#read 6, iclass 25, count 2 2006.197.08:04:10.95#ibcon#end of sib2, iclass 25, count 2 2006.197.08:04:10.95#ibcon#*after write, iclass 25, count 2 2006.197.08:04:10.95#ibcon#*before return 0, iclass 25, count 2 2006.197.08:04:10.95#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.197.08:04:10.95#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.197.08:04:10.95#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.197.08:04:10.95#ibcon#ireg 7 cls_cnt 0 2006.197.08:04:10.95#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.197.08:04:11.07#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.197.08:04:11.07#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.197.08:04:11.07#ibcon#enter wrdev, iclass 25, count 0 2006.197.08:04:11.07#ibcon#first serial, iclass 25, count 0 2006.197.08:04:11.07#ibcon#enter sib2, iclass 25, count 0 2006.197.08:04:11.07#ibcon#flushed, iclass 25, count 0 2006.197.08:04:11.07#ibcon#about to write, iclass 25, count 0 2006.197.08:04:11.07#ibcon#wrote, iclass 25, count 0 2006.197.08:04:11.07#ibcon#about to read 3, iclass 25, count 0 2006.197.08:04:11.09#ibcon#read 3, iclass 25, count 0 2006.197.08:04:11.09#ibcon#about to read 4, iclass 25, count 0 2006.197.08:04:11.09#ibcon#read 4, iclass 25, count 0 2006.197.08:04:11.09#ibcon#about to read 5, iclass 25, count 0 2006.197.08:04:11.09#ibcon#read 5, iclass 25, count 0 2006.197.08:04:11.09#ibcon#about to read 6, iclass 25, count 0 2006.197.08:04:11.09#ibcon#read 6, iclass 25, count 0 2006.197.08:04:11.09#ibcon#end of sib2, iclass 25, count 0 2006.197.08:04:11.09#ibcon#*mode == 0, iclass 25, count 0 2006.197.08:04:11.09#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.197.08:04:11.09#ibcon#[27=USB\r\n] 2006.197.08:04:11.09#ibcon#*before write, iclass 25, count 0 2006.197.08:04:11.09#ibcon#enter sib2, iclass 25, count 0 2006.197.08:04:11.09#ibcon#flushed, iclass 25, count 0 2006.197.08:04:11.09#ibcon#about to write, iclass 25, count 0 2006.197.08:04:11.09#ibcon#wrote, iclass 25, count 0 2006.197.08:04:11.09#ibcon#about to read 3, iclass 25, count 0 2006.197.08:04:11.12#ibcon#read 3, iclass 25, count 0 2006.197.08:04:11.12#ibcon#about to read 4, iclass 25, count 0 2006.197.08:04:11.12#ibcon#read 4, iclass 25, count 0 2006.197.08:04:11.12#ibcon#about to read 5, iclass 25, count 0 2006.197.08:04:11.12#ibcon#read 5, iclass 25, count 0 2006.197.08:04:11.12#ibcon#about to read 6, iclass 25, count 0 2006.197.08:04:11.12#ibcon#read 6, iclass 25, count 0 2006.197.08:04:11.12#ibcon#end of sib2, iclass 25, count 0 2006.197.08:04:11.12#ibcon#*after write, iclass 25, count 0 2006.197.08:04:11.12#ibcon#*before return 0, iclass 25, count 0 2006.197.08:04:11.12#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.197.08:04:11.12#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.197.08:04:11.12#ibcon#about to clear, iclass 25 cls_cnt 0 2006.197.08:04:11.12#ibcon#cleared, iclass 25 cls_cnt 0 2006.197.08:04:11.12$vc4f8/vblo=4,712.99 2006.197.08:04:11.12#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.197.08:04:11.12#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.197.08:04:11.12#ibcon#ireg 17 cls_cnt 0 2006.197.08:04:11.12#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.197.08:04:11.12#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.197.08:04:11.12#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.197.08:04:11.12#ibcon#enter wrdev, iclass 27, count 0 2006.197.08:04:11.12#ibcon#first serial, iclass 27, count 0 2006.197.08:04:11.12#ibcon#enter sib2, iclass 27, count 0 2006.197.08:04:11.12#ibcon#flushed, iclass 27, count 0 2006.197.08:04:11.12#ibcon#about to write, iclass 27, count 0 2006.197.08:04:11.12#ibcon#wrote, iclass 27, count 0 2006.197.08:04:11.12#ibcon#about to read 3, iclass 27, count 0 2006.197.08:04:11.14#ibcon#read 3, iclass 27, count 0 2006.197.08:04:11.14#ibcon#about to read 4, iclass 27, count 0 2006.197.08:04:11.14#ibcon#read 4, iclass 27, count 0 2006.197.08:04:11.14#ibcon#about to read 5, iclass 27, count 0 2006.197.08:04:11.14#ibcon#read 5, iclass 27, count 0 2006.197.08:04:11.14#ibcon#about to read 6, iclass 27, count 0 2006.197.08:04:11.14#ibcon#read 6, iclass 27, count 0 2006.197.08:04:11.14#ibcon#end of sib2, iclass 27, count 0 2006.197.08:04:11.14#ibcon#*mode == 0, iclass 27, count 0 2006.197.08:04:11.14#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.197.08:04:11.14#ibcon#[28=FRQ=04,712.99\r\n] 2006.197.08:04:11.14#ibcon#*before write, iclass 27, count 0 2006.197.08:04:11.14#ibcon#enter sib2, iclass 27, count 0 2006.197.08:04:11.14#ibcon#flushed, iclass 27, count 0 2006.197.08:04:11.14#ibcon#about to write, iclass 27, count 0 2006.197.08:04:11.14#ibcon#wrote, iclass 27, count 0 2006.197.08:04:11.14#ibcon#about to read 3, iclass 27, count 0 2006.197.08:04:11.18#ibcon#read 3, iclass 27, count 0 2006.197.08:04:11.18#ibcon#about to read 4, iclass 27, count 0 2006.197.08:04:11.18#ibcon#read 4, iclass 27, count 0 2006.197.08:04:11.18#ibcon#about to read 5, iclass 27, count 0 2006.197.08:04:11.18#ibcon#read 5, iclass 27, count 0 2006.197.08:04:11.18#ibcon#about to read 6, iclass 27, count 0 2006.197.08:04:11.18#ibcon#read 6, iclass 27, count 0 2006.197.08:04:11.18#ibcon#end of sib2, iclass 27, count 0 2006.197.08:04:11.18#ibcon#*after write, iclass 27, count 0 2006.197.08:04:11.18#ibcon#*before return 0, iclass 27, count 0 2006.197.08:04:11.18#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.197.08:04:11.18#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.197.08:04:11.18#ibcon#about to clear, iclass 27 cls_cnt 0 2006.197.08:04:11.18#ibcon#cleared, iclass 27 cls_cnt 0 2006.197.08:04:11.18$vc4f8/vb=4,4 2006.197.08:04:11.18#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.197.08:04:11.18#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.197.08:04:11.18#ibcon#ireg 11 cls_cnt 2 2006.197.08:04:11.18#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.197.08:04:11.24#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.197.08:04:11.24#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.197.08:04:11.24#ibcon#enter wrdev, iclass 29, count 2 2006.197.08:04:11.24#ibcon#first serial, iclass 29, count 2 2006.197.08:04:11.24#ibcon#enter sib2, iclass 29, count 2 2006.197.08:04:11.24#ibcon#flushed, iclass 29, count 2 2006.197.08:04:11.24#ibcon#about to write, iclass 29, count 2 2006.197.08:04:11.24#ibcon#wrote, iclass 29, count 2 2006.197.08:04:11.24#ibcon#about to read 3, iclass 29, count 2 2006.197.08:04:11.26#ibcon#read 3, iclass 29, count 2 2006.197.08:04:11.26#ibcon#about to read 4, iclass 29, count 2 2006.197.08:04:11.26#ibcon#read 4, iclass 29, count 2 2006.197.08:04:11.26#ibcon#about to read 5, iclass 29, count 2 2006.197.08:04:11.26#ibcon#read 5, iclass 29, count 2 2006.197.08:04:11.26#ibcon#about to read 6, iclass 29, count 2 2006.197.08:04:11.26#ibcon#read 6, iclass 29, count 2 2006.197.08:04:11.26#ibcon#end of sib2, iclass 29, count 2 2006.197.08:04:11.26#ibcon#*mode == 0, iclass 29, count 2 2006.197.08:04:11.26#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.197.08:04:11.26#ibcon#[27=AT04-04\r\n] 2006.197.08:04:11.26#ibcon#*before write, iclass 29, count 2 2006.197.08:04:11.26#ibcon#enter sib2, iclass 29, count 2 2006.197.08:04:11.26#ibcon#flushed, iclass 29, count 2 2006.197.08:04:11.26#ibcon#about to write, iclass 29, count 2 2006.197.08:04:11.26#ibcon#wrote, iclass 29, count 2 2006.197.08:04:11.26#ibcon#about to read 3, iclass 29, count 2 2006.197.08:04:11.29#ibcon#read 3, iclass 29, count 2 2006.197.08:04:11.29#ibcon#about to read 4, iclass 29, count 2 2006.197.08:04:11.29#ibcon#read 4, iclass 29, count 2 2006.197.08:04:11.29#ibcon#about to read 5, iclass 29, count 2 2006.197.08:04:11.29#ibcon#read 5, iclass 29, count 2 2006.197.08:04:11.29#ibcon#about to read 6, iclass 29, count 2 2006.197.08:04:11.29#ibcon#read 6, iclass 29, count 2 2006.197.08:04:11.29#ibcon#end of sib2, iclass 29, count 2 2006.197.08:04:11.29#ibcon#*after write, iclass 29, count 2 2006.197.08:04:11.29#ibcon#*before return 0, iclass 29, count 2 2006.197.08:04:11.29#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.197.08:04:11.29#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.197.08:04:11.29#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.197.08:04:11.29#ibcon#ireg 7 cls_cnt 0 2006.197.08:04:11.29#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.197.08:04:11.41#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.197.08:04:11.41#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.197.08:04:11.41#ibcon#enter wrdev, iclass 29, count 0 2006.197.08:04:11.41#ibcon#first serial, iclass 29, count 0 2006.197.08:04:11.41#ibcon#enter sib2, iclass 29, count 0 2006.197.08:04:11.41#ibcon#flushed, iclass 29, count 0 2006.197.08:04:11.41#ibcon#about to write, iclass 29, count 0 2006.197.08:04:11.41#ibcon#wrote, iclass 29, count 0 2006.197.08:04:11.41#ibcon#about to read 3, iclass 29, count 0 2006.197.08:04:11.43#ibcon#read 3, iclass 29, count 0 2006.197.08:04:11.43#ibcon#about to read 4, iclass 29, count 0 2006.197.08:04:11.43#ibcon#read 4, iclass 29, count 0 2006.197.08:04:11.43#ibcon#about to read 5, iclass 29, count 0 2006.197.08:04:11.43#ibcon#read 5, iclass 29, count 0 2006.197.08:04:11.43#ibcon#about to read 6, iclass 29, count 0 2006.197.08:04:11.43#ibcon#read 6, iclass 29, count 0 2006.197.08:04:11.43#ibcon#end of sib2, iclass 29, count 0 2006.197.08:04:11.43#ibcon#*mode == 0, iclass 29, count 0 2006.197.08:04:11.43#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.197.08:04:11.43#ibcon#[27=USB\r\n] 2006.197.08:04:11.43#ibcon#*before write, iclass 29, count 0 2006.197.08:04:11.43#ibcon#enter sib2, iclass 29, count 0 2006.197.08:04:11.43#ibcon#flushed, iclass 29, count 0 2006.197.08:04:11.43#ibcon#about to write, iclass 29, count 0 2006.197.08:04:11.43#ibcon#wrote, iclass 29, count 0 2006.197.08:04:11.43#ibcon#about to read 3, iclass 29, count 0 2006.197.08:04:11.46#ibcon#read 3, iclass 29, count 0 2006.197.08:04:11.46#ibcon#about to read 4, iclass 29, count 0 2006.197.08:04:11.46#ibcon#read 4, iclass 29, count 0 2006.197.08:04:11.46#ibcon#about to read 5, iclass 29, count 0 2006.197.08:04:11.46#ibcon#read 5, iclass 29, count 0 2006.197.08:04:11.46#ibcon#about to read 6, iclass 29, count 0 2006.197.08:04:11.46#ibcon#read 6, iclass 29, count 0 2006.197.08:04:11.46#ibcon#end of sib2, iclass 29, count 0 2006.197.08:04:11.46#ibcon#*after write, iclass 29, count 0 2006.197.08:04:11.46#ibcon#*before return 0, iclass 29, count 0 2006.197.08:04:11.46#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.197.08:04:11.46#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.197.08:04:11.46#ibcon#about to clear, iclass 29 cls_cnt 0 2006.197.08:04:11.46#ibcon#cleared, iclass 29 cls_cnt 0 2006.197.08:04:11.46$vc4f8/vblo=5,744.99 2006.197.08:04:11.46#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.197.08:04:11.46#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.197.08:04:11.46#ibcon#ireg 17 cls_cnt 0 2006.197.08:04:11.46#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.197.08:04:11.46#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.197.08:04:11.46#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.197.08:04:11.46#ibcon#enter wrdev, iclass 31, count 0 2006.197.08:04:11.46#ibcon#first serial, iclass 31, count 0 2006.197.08:04:11.46#ibcon#enter sib2, iclass 31, count 0 2006.197.08:04:11.46#ibcon#flushed, iclass 31, count 0 2006.197.08:04:11.46#ibcon#about to write, iclass 31, count 0 2006.197.08:04:11.46#ibcon#wrote, iclass 31, count 0 2006.197.08:04:11.46#ibcon#about to read 3, iclass 31, count 0 2006.197.08:04:11.48#ibcon#read 3, iclass 31, count 0 2006.197.08:04:11.48#ibcon#about to read 4, iclass 31, count 0 2006.197.08:04:11.48#ibcon#read 4, iclass 31, count 0 2006.197.08:04:11.48#ibcon#about to read 5, iclass 31, count 0 2006.197.08:04:11.48#ibcon#read 5, iclass 31, count 0 2006.197.08:04:11.48#ibcon#about to read 6, iclass 31, count 0 2006.197.08:04:11.48#ibcon#read 6, iclass 31, count 0 2006.197.08:04:11.48#ibcon#end of sib2, iclass 31, count 0 2006.197.08:04:11.48#ibcon#*mode == 0, iclass 31, count 0 2006.197.08:04:11.48#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.197.08:04:11.48#ibcon#[28=FRQ=05,744.99\r\n] 2006.197.08:04:11.48#ibcon#*before write, iclass 31, count 0 2006.197.08:04:11.48#ibcon#enter sib2, iclass 31, count 0 2006.197.08:04:11.48#ibcon#flushed, iclass 31, count 0 2006.197.08:04:11.48#ibcon#about to write, iclass 31, count 0 2006.197.08:04:11.48#ibcon#wrote, iclass 31, count 0 2006.197.08:04:11.48#ibcon#about to read 3, iclass 31, count 0 2006.197.08:04:11.52#ibcon#read 3, iclass 31, count 0 2006.197.08:04:11.52#ibcon#about to read 4, iclass 31, count 0 2006.197.08:04:11.52#ibcon#read 4, iclass 31, count 0 2006.197.08:04:11.52#ibcon#about to read 5, iclass 31, count 0 2006.197.08:04:11.52#ibcon#read 5, iclass 31, count 0 2006.197.08:04:11.52#ibcon#about to read 6, iclass 31, count 0 2006.197.08:04:11.52#ibcon#read 6, iclass 31, count 0 2006.197.08:04:11.52#ibcon#end of sib2, iclass 31, count 0 2006.197.08:04:11.52#ibcon#*after write, iclass 31, count 0 2006.197.08:04:11.52#ibcon#*before return 0, iclass 31, count 0 2006.197.08:04:11.52#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.197.08:04:11.52#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.197.08:04:11.52#ibcon#about to clear, iclass 31 cls_cnt 0 2006.197.08:04:11.52#ibcon#cleared, iclass 31 cls_cnt 0 2006.197.08:04:11.52$vc4f8/vb=5,4 2006.197.08:04:11.52#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.197.08:04:11.52#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.197.08:04:11.52#ibcon#ireg 11 cls_cnt 2 2006.197.08:04:11.52#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.197.08:04:11.58#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.197.08:04:11.58#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.197.08:04:11.58#ibcon#enter wrdev, iclass 33, count 2 2006.197.08:04:11.58#ibcon#first serial, iclass 33, count 2 2006.197.08:04:11.58#ibcon#enter sib2, iclass 33, count 2 2006.197.08:04:11.58#ibcon#flushed, iclass 33, count 2 2006.197.08:04:11.58#ibcon#about to write, iclass 33, count 2 2006.197.08:04:11.58#ibcon#wrote, iclass 33, count 2 2006.197.08:04:11.58#ibcon#about to read 3, iclass 33, count 2 2006.197.08:04:11.60#ibcon#read 3, iclass 33, count 2 2006.197.08:04:11.60#ibcon#about to read 4, iclass 33, count 2 2006.197.08:04:11.60#ibcon#read 4, iclass 33, count 2 2006.197.08:04:11.60#ibcon#about to read 5, iclass 33, count 2 2006.197.08:04:11.60#ibcon#read 5, iclass 33, count 2 2006.197.08:04:11.60#ibcon#about to read 6, iclass 33, count 2 2006.197.08:04:11.60#ibcon#read 6, iclass 33, count 2 2006.197.08:04:11.60#ibcon#end of sib2, iclass 33, count 2 2006.197.08:04:11.60#ibcon#*mode == 0, iclass 33, count 2 2006.197.08:04:11.60#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.197.08:04:11.60#ibcon#[27=AT05-04\r\n] 2006.197.08:04:11.60#ibcon#*before write, iclass 33, count 2 2006.197.08:04:11.60#ibcon#enter sib2, iclass 33, count 2 2006.197.08:04:11.60#ibcon#flushed, iclass 33, count 2 2006.197.08:04:11.60#ibcon#about to write, iclass 33, count 2 2006.197.08:04:11.60#ibcon#wrote, iclass 33, count 2 2006.197.08:04:11.60#ibcon#about to read 3, iclass 33, count 2 2006.197.08:04:11.63#ibcon#read 3, iclass 33, count 2 2006.197.08:04:11.63#ibcon#about to read 4, iclass 33, count 2 2006.197.08:04:11.63#ibcon#read 4, iclass 33, count 2 2006.197.08:04:11.63#ibcon#about to read 5, iclass 33, count 2 2006.197.08:04:11.63#ibcon#read 5, iclass 33, count 2 2006.197.08:04:11.63#ibcon#about to read 6, iclass 33, count 2 2006.197.08:04:11.63#ibcon#read 6, iclass 33, count 2 2006.197.08:04:11.63#ibcon#end of sib2, iclass 33, count 2 2006.197.08:04:11.63#ibcon#*after write, iclass 33, count 2 2006.197.08:04:11.63#ibcon#*before return 0, iclass 33, count 2 2006.197.08:04:11.63#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.197.08:04:11.63#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.197.08:04:11.63#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.197.08:04:11.63#ibcon#ireg 7 cls_cnt 0 2006.197.08:04:11.63#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.197.08:04:11.75#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.197.08:04:11.75#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.197.08:04:11.75#ibcon#enter wrdev, iclass 33, count 0 2006.197.08:04:11.75#ibcon#first serial, iclass 33, count 0 2006.197.08:04:11.75#ibcon#enter sib2, iclass 33, count 0 2006.197.08:04:11.75#ibcon#flushed, iclass 33, count 0 2006.197.08:04:11.75#ibcon#about to write, iclass 33, count 0 2006.197.08:04:11.75#ibcon#wrote, iclass 33, count 0 2006.197.08:04:11.75#ibcon#about to read 3, iclass 33, count 0 2006.197.08:04:11.77#ibcon#read 3, iclass 33, count 0 2006.197.08:04:11.77#ibcon#about to read 4, iclass 33, count 0 2006.197.08:04:11.77#ibcon#read 4, iclass 33, count 0 2006.197.08:04:11.77#ibcon#about to read 5, iclass 33, count 0 2006.197.08:04:11.77#ibcon#read 5, iclass 33, count 0 2006.197.08:04:11.77#ibcon#about to read 6, iclass 33, count 0 2006.197.08:04:11.77#ibcon#read 6, iclass 33, count 0 2006.197.08:04:11.77#ibcon#end of sib2, iclass 33, count 0 2006.197.08:04:11.77#ibcon#*mode == 0, iclass 33, count 0 2006.197.08:04:11.77#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.197.08:04:11.77#ibcon#[27=USB\r\n] 2006.197.08:04:11.77#ibcon#*before write, iclass 33, count 0 2006.197.08:04:11.77#ibcon#enter sib2, iclass 33, count 0 2006.197.08:04:11.77#ibcon#flushed, iclass 33, count 0 2006.197.08:04:11.77#ibcon#about to write, iclass 33, count 0 2006.197.08:04:11.77#ibcon#wrote, iclass 33, count 0 2006.197.08:04:11.77#ibcon#about to read 3, iclass 33, count 0 2006.197.08:04:11.80#ibcon#read 3, iclass 33, count 0 2006.197.08:04:11.80#ibcon#about to read 4, iclass 33, count 0 2006.197.08:04:11.80#ibcon#read 4, iclass 33, count 0 2006.197.08:04:11.80#ibcon#about to read 5, iclass 33, count 0 2006.197.08:04:11.80#ibcon#read 5, iclass 33, count 0 2006.197.08:04:11.80#ibcon#about to read 6, iclass 33, count 0 2006.197.08:04:11.80#ibcon#read 6, iclass 33, count 0 2006.197.08:04:11.80#ibcon#end of sib2, iclass 33, count 0 2006.197.08:04:11.80#ibcon#*after write, iclass 33, count 0 2006.197.08:04:11.80#ibcon#*before return 0, iclass 33, count 0 2006.197.08:04:11.80#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.197.08:04:11.80#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.197.08:04:11.80#ibcon#about to clear, iclass 33 cls_cnt 0 2006.197.08:04:11.80#ibcon#cleared, iclass 33 cls_cnt 0 2006.197.08:04:11.80$vc4f8/vblo=6,752.99 2006.197.08:04:11.80#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.197.08:04:11.80#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.197.08:04:11.80#ibcon#ireg 17 cls_cnt 0 2006.197.08:04:11.80#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.197.08:04:11.80#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.197.08:04:11.80#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.197.08:04:11.80#ibcon#enter wrdev, iclass 35, count 0 2006.197.08:04:11.80#ibcon#first serial, iclass 35, count 0 2006.197.08:04:11.80#ibcon#enter sib2, iclass 35, count 0 2006.197.08:04:11.80#ibcon#flushed, iclass 35, count 0 2006.197.08:04:11.80#ibcon#about to write, iclass 35, count 0 2006.197.08:04:11.80#ibcon#wrote, iclass 35, count 0 2006.197.08:04:11.80#ibcon#about to read 3, iclass 35, count 0 2006.197.08:04:11.82#ibcon#read 3, iclass 35, count 0 2006.197.08:04:11.82#ibcon#about to read 4, iclass 35, count 0 2006.197.08:04:11.82#ibcon#read 4, iclass 35, count 0 2006.197.08:04:11.82#ibcon#about to read 5, iclass 35, count 0 2006.197.08:04:11.82#ibcon#read 5, iclass 35, count 0 2006.197.08:04:11.82#ibcon#about to read 6, iclass 35, count 0 2006.197.08:04:11.82#ibcon#read 6, iclass 35, count 0 2006.197.08:04:11.82#ibcon#end of sib2, iclass 35, count 0 2006.197.08:04:11.82#ibcon#*mode == 0, iclass 35, count 0 2006.197.08:04:11.82#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.197.08:04:11.82#ibcon#[28=FRQ=06,752.99\r\n] 2006.197.08:04:11.82#ibcon#*before write, iclass 35, count 0 2006.197.08:04:11.82#ibcon#enter sib2, iclass 35, count 0 2006.197.08:04:11.82#ibcon#flushed, iclass 35, count 0 2006.197.08:04:11.82#ibcon#about to write, iclass 35, count 0 2006.197.08:04:11.82#ibcon#wrote, iclass 35, count 0 2006.197.08:04:11.82#ibcon#about to read 3, iclass 35, count 0 2006.197.08:04:11.86#ibcon#read 3, iclass 35, count 0 2006.197.08:04:11.86#ibcon#about to read 4, iclass 35, count 0 2006.197.08:04:11.86#ibcon#read 4, iclass 35, count 0 2006.197.08:04:11.86#ibcon#about to read 5, iclass 35, count 0 2006.197.08:04:11.86#ibcon#read 5, iclass 35, count 0 2006.197.08:04:11.86#ibcon#about to read 6, iclass 35, count 0 2006.197.08:04:11.86#ibcon#read 6, iclass 35, count 0 2006.197.08:04:11.86#ibcon#end of sib2, iclass 35, count 0 2006.197.08:04:11.86#ibcon#*after write, iclass 35, count 0 2006.197.08:04:11.86#ibcon#*before return 0, iclass 35, count 0 2006.197.08:04:11.86#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.197.08:04:11.86#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.197.08:04:11.86#ibcon#about to clear, iclass 35 cls_cnt 0 2006.197.08:04:11.86#ibcon#cleared, iclass 35 cls_cnt 0 2006.197.08:04:11.86$vc4f8/vb=6,4 2006.197.08:04:11.86#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.197.08:04:11.86#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.197.08:04:11.86#ibcon#ireg 11 cls_cnt 2 2006.197.08:04:11.86#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.197.08:04:11.90#abcon#<5=/04 3.5 6.6 25.68 961002.8\r\n> 2006.197.08:04:11.92#abcon#{5=INTERFACE CLEAR} 2006.197.08:04:11.92#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.197.08:04:11.92#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.197.08:04:11.92#ibcon#enter wrdev, iclass 38, count 2 2006.197.08:04:11.92#ibcon#first serial, iclass 38, count 2 2006.197.08:04:11.92#ibcon#enter sib2, iclass 38, count 2 2006.197.08:04:11.92#ibcon#flushed, iclass 38, count 2 2006.197.08:04:11.92#ibcon#about to write, iclass 38, count 2 2006.197.08:04:11.92#ibcon#wrote, iclass 38, count 2 2006.197.08:04:11.92#ibcon#about to read 3, iclass 38, count 2 2006.197.08:04:11.94#ibcon#read 3, iclass 38, count 2 2006.197.08:04:11.94#ibcon#about to read 4, iclass 38, count 2 2006.197.08:04:11.94#ibcon#read 4, iclass 38, count 2 2006.197.08:04:11.94#ibcon#about to read 5, iclass 38, count 2 2006.197.08:04:11.94#ibcon#read 5, iclass 38, count 2 2006.197.08:04:11.94#ibcon#about to read 6, iclass 38, count 2 2006.197.08:04:11.94#ibcon#read 6, iclass 38, count 2 2006.197.08:04:11.94#ibcon#end of sib2, iclass 38, count 2 2006.197.08:04:11.94#ibcon#*mode == 0, iclass 38, count 2 2006.197.08:04:11.94#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.197.08:04:11.94#ibcon#[27=AT06-04\r\n] 2006.197.08:04:11.94#ibcon#*before write, iclass 38, count 2 2006.197.08:04:11.94#ibcon#enter sib2, iclass 38, count 2 2006.197.08:04:11.94#ibcon#flushed, iclass 38, count 2 2006.197.08:04:11.94#ibcon#about to write, iclass 38, count 2 2006.197.08:04:11.94#ibcon#wrote, iclass 38, count 2 2006.197.08:04:11.94#ibcon#about to read 3, iclass 38, count 2 2006.197.08:04:11.97#ibcon#read 3, iclass 38, count 2 2006.197.08:04:11.97#ibcon#about to read 4, iclass 38, count 2 2006.197.08:04:11.97#ibcon#read 4, iclass 38, count 2 2006.197.08:04:11.97#ibcon#about to read 5, iclass 38, count 2 2006.197.08:04:11.97#ibcon#read 5, iclass 38, count 2 2006.197.08:04:11.97#ibcon#about to read 6, iclass 38, count 2 2006.197.08:04:11.97#ibcon#read 6, iclass 38, count 2 2006.197.08:04:11.97#ibcon#end of sib2, iclass 38, count 2 2006.197.08:04:11.97#ibcon#*after write, iclass 38, count 2 2006.197.08:04:11.97#ibcon#*before return 0, iclass 38, count 2 2006.197.08:04:11.97#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.197.08:04:11.97#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.197.08:04:11.97#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.197.08:04:11.97#ibcon#ireg 7 cls_cnt 0 2006.197.08:04:11.97#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.197.08:04:11.98#abcon#[5=S1D000X0/0*\r\n] 2006.197.08:04:12.09#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.197.08:04:12.09#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.197.08:04:12.09#ibcon#enter wrdev, iclass 38, count 0 2006.197.08:04:12.09#ibcon#first serial, iclass 38, count 0 2006.197.08:04:12.09#ibcon#enter sib2, iclass 38, count 0 2006.197.08:04:12.09#ibcon#flushed, iclass 38, count 0 2006.197.08:04:12.09#ibcon#about to write, iclass 38, count 0 2006.197.08:04:12.09#ibcon#wrote, iclass 38, count 0 2006.197.08:04:12.09#ibcon#about to read 3, iclass 38, count 0 2006.197.08:04:12.11#ibcon#read 3, iclass 38, count 0 2006.197.08:04:12.11#ibcon#about to read 4, iclass 38, count 0 2006.197.08:04:12.11#ibcon#read 4, iclass 38, count 0 2006.197.08:04:12.11#ibcon#about to read 5, iclass 38, count 0 2006.197.08:04:12.11#ibcon#read 5, iclass 38, count 0 2006.197.08:04:12.11#ibcon#about to read 6, iclass 38, count 0 2006.197.08:04:12.11#ibcon#read 6, iclass 38, count 0 2006.197.08:04:12.11#ibcon#end of sib2, iclass 38, count 0 2006.197.08:04:12.11#ibcon#*mode == 0, iclass 38, count 0 2006.197.08:04:12.11#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.197.08:04:12.11#ibcon#[27=USB\r\n] 2006.197.08:04:12.11#ibcon#*before write, iclass 38, count 0 2006.197.08:04:12.11#ibcon#enter sib2, iclass 38, count 0 2006.197.08:04:12.11#ibcon#flushed, iclass 38, count 0 2006.197.08:04:12.11#ibcon#about to write, iclass 38, count 0 2006.197.08:04:12.11#ibcon#wrote, iclass 38, count 0 2006.197.08:04:12.11#ibcon#about to read 3, iclass 38, count 0 2006.197.08:04:12.14#ibcon#read 3, iclass 38, count 0 2006.197.08:04:12.14#ibcon#about to read 4, iclass 38, count 0 2006.197.08:04:12.14#ibcon#read 4, iclass 38, count 0 2006.197.08:04:12.14#ibcon#about to read 5, iclass 38, count 0 2006.197.08:04:12.14#ibcon#read 5, iclass 38, count 0 2006.197.08:04:12.14#ibcon#about to read 6, iclass 38, count 0 2006.197.08:04:12.14#ibcon#read 6, iclass 38, count 0 2006.197.08:04:12.14#ibcon#end of sib2, iclass 38, count 0 2006.197.08:04:12.14#ibcon#*after write, iclass 38, count 0 2006.197.08:04:12.14#ibcon#*before return 0, iclass 38, count 0 2006.197.08:04:12.14#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.197.08:04:12.14#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.197.08:04:12.14#ibcon#about to clear, iclass 38 cls_cnt 0 2006.197.08:04:12.14#ibcon#cleared, iclass 38 cls_cnt 0 2006.197.08:04:12.14$vc4f8/vabw=wide 2006.197.08:04:12.14#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.197.08:04:12.14#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.197.08:04:12.14#ibcon#ireg 8 cls_cnt 0 2006.197.08:04:12.14#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.197.08:04:12.14#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.197.08:04:12.14#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.197.08:04:12.14#ibcon#enter wrdev, iclass 5, count 0 2006.197.08:04:12.14#ibcon#first serial, iclass 5, count 0 2006.197.08:04:12.14#ibcon#enter sib2, iclass 5, count 0 2006.197.08:04:12.14#ibcon#flushed, iclass 5, count 0 2006.197.08:04:12.14#ibcon#about to write, iclass 5, count 0 2006.197.08:04:12.14#ibcon#wrote, iclass 5, count 0 2006.197.08:04:12.14#ibcon#about to read 3, iclass 5, count 0 2006.197.08:04:12.16#ibcon#read 3, iclass 5, count 0 2006.197.08:04:12.16#ibcon#about to read 4, iclass 5, count 0 2006.197.08:04:12.16#ibcon#read 4, iclass 5, count 0 2006.197.08:04:12.16#ibcon#about to read 5, iclass 5, count 0 2006.197.08:04:12.16#ibcon#read 5, iclass 5, count 0 2006.197.08:04:12.16#ibcon#about to read 6, iclass 5, count 0 2006.197.08:04:12.16#ibcon#read 6, iclass 5, count 0 2006.197.08:04:12.16#ibcon#end of sib2, iclass 5, count 0 2006.197.08:04:12.16#ibcon#*mode == 0, iclass 5, count 0 2006.197.08:04:12.16#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.197.08:04:12.16#ibcon#[25=BW32\r\n] 2006.197.08:04:12.16#ibcon#*before write, iclass 5, count 0 2006.197.08:04:12.16#ibcon#enter sib2, iclass 5, count 0 2006.197.08:04:12.16#ibcon#flushed, iclass 5, count 0 2006.197.08:04:12.16#ibcon#about to write, iclass 5, count 0 2006.197.08:04:12.16#ibcon#wrote, iclass 5, count 0 2006.197.08:04:12.16#ibcon#about to read 3, iclass 5, count 0 2006.197.08:04:12.19#ibcon#read 3, iclass 5, count 0 2006.197.08:04:12.19#ibcon#about to read 4, iclass 5, count 0 2006.197.08:04:12.19#ibcon#read 4, iclass 5, count 0 2006.197.08:04:12.19#ibcon#about to read 5, iclass 5, count 0 2006.197.08:04:12.19#ibcon#read 5, iclass 5, count 0 2006.197.08:04:12.19#ibcon#about to read 6, iclass 5, count 0 2006.197.08:04:12.19#ibcon#read 6, iclass 5, count 0 2006.197.08:04:12.19#ibcon#end of sib2, iclass 5, count 0 2006.197.08:04:12.19#ibcon#*after write, iclass 5, count 0 2006.197.08:04:12.19#ibcon#*before return 0, iclass 5, count 0 2006.197.08:04:12.19#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.197.08:04:12.19#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.197.08:04:12.19#ibcon#about to clear, iclass 5 cls_cnt 0 2006.197.08:04:12.19#ibcon#cleared, iclass 5 cls_cnt 0 2006.197.08:04:12.19$vc4f8/vbbw=wide 2006.197.08:04:12.19#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.197.08:04:12.19#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.197.08:04:12.19#ibcon#ireg 8 cls_cnt 0 2006.197.08:04:12.19#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.197.08:04:12.26#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.197.08:04:12.26#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.197.08:04:12.26#ibcon#enter wrdev, iclass 7, count 0 2006.197.08:04:12.26#ibcon#first serial, iclass 7, count 0 2006.197.08:04:12.26#ibcon#enter sib2, iclass 7, count 0 2006.197.08:04:12.26#ibcon#flushed, iclass 7, count 0 2006.197.08:04:12.26#ibcon#about to write, iclass 7, count 0 2006.197.08:04:12.26#ibcon#wrote, iclass 7, count 0 2006.197.08:04:12.26#ibcon#about to read 3, iclass 7, count 0 2006.197.08:04:12.28#ibcon#read 3, iclass 7, count 0 2006.197.08:04:12.28#ibcon#about to read 4, iclass 7, count 0 2006.197.08:04:12.28#ibcon#read 4, iclass 7, count 0 2006.197.08:04:12.28#ibcon#about to read 5, iclass 7, count 0 2006.197.08:04:12.28#ibcon#read 5, iclass 7, count 0 2006.197.08:04:12.28#ibcon#about to read 6, iclass 7, count 0 2006.197.08:04:12.28#ibcon#read 6, iclass 7, count 0 2006.197.08:04:12.28#ibcon#end of sib2, iclass 7, count 0 2006.197.08:04:12.28#ibcon#*mode == 0, iclass 7, count 0 2006.197.08:04:12.28#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.197.08:04:12.28#ibcon#[27=BW32\r\n] 2006.197.08:04:12.28#ibcon#*before write, iclass 7, count 0 2006.197.08:04:12.28#ibcon#enter sib2, iclass 7, count 0 2006.197.08:04:12.28#ibcon#flushed, iclass 7, count 0 2006.197.08:04:12.28#ibcon#about to write, iclass 7, count 0 2006.197.08:04:12.28#ibcon#wrote, iclass 7, count 0 2006.197.08:04:12.28#ibcon#about to read 3, iclass 7, count 0 2006.197.08:04:12.31#ibcon#read 3, iclass 7, count 0 2006.197.08:04:12.31#ibcon#about to read 4, iclass 7, count 0 2006.197.08:04:12.31#ibcon#read 4, iclass 7, count 0 2006.197.08:04:12.31#ibcon#about to read 5, iclass 7, count 0 2006.197.08:04:12.31#ibcon#read 5, iclass 7, count 0 2006.197.08:04:12.31#ibcon#about to read 6, iclass 7, count 0 2006.197.08:04:12.31#ibcon#read 6, iclass 7, count 0 2006.197.08:04:12.31#ibcon#end of sib2, iclass 7, count 0 2006.197.08:04:12.31#ibcon#*after write, iclass 7, count 0 2006.197.08:04:12.31#ibcon#*before return 0, iclass 7, count 0 2006.197.08:04:12.31#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.197.08:04:12.31#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.197.08:04:12.31#ibcon#about to clear, iclass 7 cls_cnt 0 2006.197.08:04:12.31#ibcon#cleared, iclass 7 cls_cnt 0 2006.197.08:04:12.31$4f8m12a/ifd4f 2006.197.08:04:12.31$ifd4f/lo= 2006.197.08:04:12.31$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.197.08:04:12.31$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.197.08:04:12.31$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.197.08:04:12.31$ifd4f/patch= 2006.197.08:04:12.31$ifd4f/patch=lo1,a1,a2,a3,a4 2006.197.08:04:12.31$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.197.08:04:12.31$ifd4f/patch=lo3,a5,a6,a7,a8 2006.197.08:04:12.31$4f8m12a/"form=m,16.000,1:2 2006.197.08:04:12.31$4f8m12a/"tpicd 2006.197.08:04:12.31$4f8m12a/echo=off 2006.197.08:04:12.31$4f8m12a/xlog=off 2006.197.08:04:12.31:!2006.197.08:04:40 2006.197.08:04:23.13#trakl#Source acquired 2006.197.08:04:24.13#flagr#flagr/antenna,acquired 2006.197.08:04:40.00:preob 2006.197.08:04:40.13/onsource/TRACKING 2006.197.08:04:40.13:!2006.197.08:04:50 2006.197.08:04:50.00:data_valid=on 2006.197.08:04:50.00:midob 2006.197.08:04:51.13/onsource/TRACKING 2006.197.08:04:51.13/wx/25.68,1002.7,96 2006.197.08:04:51.29/cable/+6.3701E-03 2006.197.08:04:52.38/va/01,08,usb,yes,32,34 2006.197.08:04:52.38/va/02,07,usb,yes,33,34 2006.197.08:04:52.38/va/03,06,usb,yes,35,35 2006.197.08:04:52.38/va/04,07,usb,yes,34,36 2006.197.08:04:52.38/va/05,07,usb,yes,38,40 2006.197.08:04:52.38/va/06,06,usb,yes,38,37 2006.197.08:04:52.38/va/07,06,usb,yes,38,38 2006.197.08:04:52.38/va/08,07,usb,yes,36,35 2006.197.08:04:52.61/valo/01,532.99,yes,locked 2006.197.08:04:52.61/valo/02,572.99,yes,locked 2006.197.08:04:52.61/valo/03,672.99,yes,locked 2006.197.08:04:52.61/valo/04,832.99,yes,locked 2006.197.08:04:52.61/valo/05,652.99,yes,locked 2006.197.08:04:52.61/valo/06,772.99,yes,locked 2006.197.08:04:52.61/valo/07,832.99,yes,locked 2006.197.08:04:52.61/valo/08,852.99,yes,locked 2006.197.08:04:53.70/vb/01,04,usb,yes,31,29 2006.197.08:04:53.70/vb/02,04,usb,yes,33,34 2006.197.08:04:53.70/vb/03,04,usb,yes,29,33 2006.197.08:04:53.70/vb/04,04,usb,yes,30,30 2006.197.08:04:53.70/vb/05,04,usb,yes,28,32 2006.197.08:04:53.70/vb/06,04,usb,yes,29,32 2006.197.08:04:53.70/vb/07,04,usb,yes,32,32 2006.197.08:04:53.70/vb/08,04,usb,yes,29,32 2006.197.08:04:53.93/vblo/01,632.99,yes,locked 2006.197.08:04:53.93/vblo/02,640.99,yes,locked 2006.197.08:04:53.93/vblo/03,656.99,yes,locked 2006.197.08:04:53.93/vblo/04,712.99,yes,locked 2006.197.08:04:53.93/vblo/05,744.99,yes,locked 2006.197.08:04:53.93/vblo/06,752.99,yes,locked 2006.197.08:04:53.93/vblo/07,734.99,yes,locked 2006.197.08:04:53.93/vblo/08,744.99,yes,locked 2006.197.08:04:54.08/vabw/8 2006.197.08:04:54.23/vbbw/8 2006.197.08:04:54.42/xfe/off,on,15.5 2006.197.08:04:54.80/ifatt/23,28,28,28 2006.197.08:04:55.09/fmout-gps/S +3.01E-07 2006.197.08:04:55.12:!2006.197.08:05:50 2006.197.08:05:50.00:data_valid=off 2006.197.08:05:50.00:postob 2006.197.08:05:50.08/cable/+6.3705E-03 2006.197.08:05:50.08/wx/25.67,1002.7,96 2006.197.08:05:51.09/fmout-gps/S +3.01E-07 2006.197.08:05:51.09:scan_name=197-0806,k06197,60 2006.197.08:05:51.09:source=0602+673,060752.67,672055.4,2000.0,ccw 2006.197.08:05:51.14#flagr#flagr/antenna,new-source 2006.197.08:05:52.14:checkk5 2006.197.08:05:52.48/chk_autoobs//k5ts1/ autoobs is running! 2006.197.08:05:52.82/chk_autoobs//k5ts2/ autoobs is running! 2006.197.08:05:53.34/chk_autoobs//k5ts3/ autoobs is running! 2006.197.08:05:53.68/chk_autoobs//k5ts4/ autoobs is running! 2006.197.08:05:54.02/chk_obsdata//k5ts1/T1970804??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.197.08:05:54.35/chk_obsdata//k5ts2/T1970804??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.197.08:05:54.69/chk_obsdata//k5ts3/T1970804??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.197.08:05:55.03/chk_obsdata//k5ts4/T1970804??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.197.08:05:55.68/k5log//k5ts1_log_newline 2006.197.08:05:56.35/k5log//k5ts2_log_newline 2006.197.08:05:57.01/k5log//k5ts3_log_newline 2006.197.08:05:57.66/k5log//k5ts4_log_newline 2006.197.08:05:57.68/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.197.08:05:57.68:4f8m12a=2 2006.197.08:05:57.68$4f8m12a/echo=on 2006.197.08:05:57.69$4f8m12a/pcalon 2006.197.08:05:57.69$pcalon/"no phase cal control is implemented here 2006.197.08:05:57.69$4f8m12a/"tpicd=stop 2006.197.08:05:57.69$4f8m12a/vc4f8 2006.197.08:05:57.69$vc4f8/valo=1,532.99 2006.197.08:05:57.69#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.197.08:05:57.69#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.197.08:05:57.69#ibcon#ireg 17 cls_cnt 0 2006.197.08:05:57.69#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.197.08:05:57.69#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.197.08:05:57.69#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.197.08:05:57.69#ibcon#enter wrdev, iclass 16, count 0 2006.197.08:05:57.69#ibcon#first serial, iclass 16, count 0 2006.197.08:05:57.69#ibcon#enter sib2, iclass 16, count 0 2006.197.08:05:57.69#ibcon#flushed, iclass 16, count 0 2006.197.08:05:57.69#ibcon#about to write, iclass 16, count 0 2006.197.08:05:57.69#ibcon#wrote, iclass 16, count 0 2006.197.08:05:57.69#ibcon#about to read 3, iclass 16, count 0 2006.197.08:05:57.71#ibcon#read 3, iclass 16, count 0 2006.197.08:05:57.71#ibcon#about to read 4, iclass 16, count 0 2006.197.08:05:57.71#ibcon#read 4, iclass 16, count 0 2006.197.08:05:57.71#ibcon#about to read 5, iclass 16, count 0 2006.197.08:05:57.71#ibcon#read 5, iclass 16, count 0 2006.197.08:05:57.71#ibcon#about to read 6, iclass 16, count 0 2006.197.08:05:57.71#ibcon#read 6, iclass 16, count 0 2006.197.08:05:57.71#ibcon#end of sib2, iclass 16, count 0 2006.197.08:05:57.71#ibcon#*mode == 0, iclass 16, count 0 2006.197.08:05:57.71#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.197.08:05:57.71#ibcon#[26=FRQ=01,532.99\r\n] 2006.197.08:05:57.71#ibcon#*before write, iclass 16, count 0 2006.197.08:05:57.71#ibcon#enter sib2, iclass 16, count 0 2006.197.08:05:57.71#ibcon#flushed, iclass 16, count 0 2006.197.08:05:57.71#ibcon#about to write, iclass 16, count 0 2006.197.08:05:57.71#ibcon#wrote, iclass 16, count 0 2006.197.08:05:57.71#ibcon#about to read 3, iclass 16, count 0 2006.197.08:05:57.76#ibcon#read 3, iclass 16, count 0 2006.197.08:05:57.76#ibcon#about to read 4, iclass 16, count 0 2006.197.08:05:57.76#ibcon#read 4, iclass 16, count 0 2006.197.08:05:57.76#ibcon#about to read 5, iclass 16, count 0 2006.197.08:05:57.76#ibcon#read 5, iclass 16, count 0 2006.197.08:05:57.76#ibcon#about to read 6, iclass 16, count 0 2006.197.08:05:57.76#ibcon#read 6, iclass 16, count 0 2006.197.08:05:57.76#ibcon#end of sib2, iclass 16, count 0 2006.197.08:05:57.76#ibcon#*after write, iclass 16, count 0 2006.197.08:05:57.76#ibcon#*before return 0, iclass 16, count 0 2006.197.08:05:57.76#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.197.08:05:57.76#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.197.08:05:57.76#ibcon#about to clear, iclass 16 cls_cnt 0 2006.197.08:05:57.76#ibcon#cleared, iclass 16 cls_cnt 0 2006.197.08:05:57.76$vc4f8/va=1,8 2006.197.08:05:57.76#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.197.08:05:57.76#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.197.08:05:57.76#ibcon#ireg 11 cls_cnt 2 2006.197.08:05:57.76#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.197.08:05:57.76#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.197.08:05:57.76#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.197.08:05:57.76#ibcon#enter wrdev, iclass 18, count 2 2006.197.08:05:57.76#ibcon#first serial, iclass 18, count 2 2006.197.08:05:57.76#ibcon#enter sib2, iclass 18, count 2 2006.197.08:05:57.76#ibcon#flushed, iclass 18, count 2 2006.197.08:05:57.76#ibcon#about to write, iclass 18, count 2 2006.197.08:05:57.76#ibcon#wrote, iclass 18, count 2 2006.197.08:05:57.76#ibcon#about to read 3, iclass 18, count 2 2006.197.08:05:57.78#ibcon#read 3, iclass 18, count 2 2006.197.08:05:57.78#ibcon#about to read 4, iclass 18, count 2 2006.197.08:05:57.78#ibcon#read 4, iclass 18, count 2 2006.197.08:05:57.78#ibcon#about to read 5, iclass 18, count 2 2006.197.08:05:57.78#ibcon#read 5, iclass 18, count 2 2006.197.08:05:57.78#ibcon#about to read 6, iclass 18, count 2 2006.197.08:05:57.78#ibcon#read 6, iclass 18, count 2 2006.197.08:05:57.78#ibcon#end of sib2, iclass 18, count 2 2006.197.08:05:57.78#ibcon#*mode == 0, iclass 18, count 2 2006.197.08:05:57.78#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.197.08:05:57.78#ibcon#[25=AT01-08\r\n] 2006.197.08:05:57.78#ibcon#*before write, iclass 18, count 2 2006.197.08:05:57.78#ibcon#enter sib2, iclass 18, count 2 2006.197.08:05:57.78#ibcon#flushed, iclass 18, count 2 2006.197.08:05:57.78#ibcon#about to write, iclass 18, count 2 2006.197.08:05:57.78#ibcon#wrote, iclass 18, count 2 2006.197.08:05:57.78#ibcon#about to read 3, iclass 18, count 2 2006.197.08:05:57.81#ibcon#read 3, iclass 18, count 2 2006.197.08:05:57.81#ibcon#about to read 4, iclass 18, count 2 2006.197.08:05:57.81#ibcon#read 4, iclass 18, count 2 2006.197.08:05:57.81#ibcon#about to read 5, iclass 18, count 2 2006.197.08:05:57.81#ibcon#read 5, iclass 18, count 2 2006.197.08:05:57.81#ibcon#about to read 6, iclass 18, count 2 2006.197.08:05:57.81#ibcon#read 6, iclass 18, count 2 2006.197.08:05:57.81#ibcon#end of sib2, iclass 18, count 2 2006.197.08:05:57.81#ibcon#*after write, iclass 18, count 2 2006.197.08:05:57.81#ibcon#*before return 0, iclass 18, count 2 2006.197.08:05:57.81#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.197.08:05:57.81#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.197.08:05:57.81#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.197.08:05:57.81#ibcon#ireg 7 cls_cnt 0 2006.197.08:05:57.81#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.197.08:05:57.93#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.197.08:05:57.93#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.197.08:05:57.93#ibcon#enter wrdev, iclass 18, count 0 2006.197.08:05:57.93#ibcon#first serial, iclass 18, count 0 2006.197.08:05:57.93#ibcon#enter sib2, iclass 18, count 0 2006.197.08:05:57.93#ibcon#flushed, iclass 18, count 0 2006.197.08:05:57.93#ibcon#about to write, iclass 18, count 0 2006.197.08:05:57.93#ibcon#wrote, iclass 18, count 0 2006.197.08:05:57.93#ibcon#about to read 3, iclass 18, count 0 2006.197.08:05:57.95#ibcon#read 3, iclass 18, count 0 2006.197.08:05:57.95#ibcon#about to read 4, iclass 18, count 0 2006.197.08:05:57.95#ibcon#read 4, iclass 18, count 0 2006.197.08:05:57.95#ibcon#about to read 5, iclass 18, count 0 2006.197.08:05:57.95#ibcon#read 5, iclass 18, count 0 2006.197.08:05:57.95#ibcon#about to read 6, iclass 18, count 0 2006.197.08:05:57.95#ibcon#read 6, iclass 18, count 0 2006.197.08:05:57.95#ibcon#end of sib2, iclass 18, count 0 2006.197.08:05:57.95#ibcon#*mode == 0, iclass 18, count 0 2006.197.08:05:57.95#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.197.08:05:57.95#ibcon#[25=USB\r\n] 2006.197.08:05:57.95#ibcon#*before write, iclass 18, count 0 2006.197.08:05:57.95#ibcon#enter sib2, iclass 18, count 0 2006.197.08:05:57.95#ibcon#flushed, iclass 18, count 0 2006.197.08:05:57.95#ibcon#about to write, iclass 18, count 0 2006.197.08:05:57.95#ibcon#wrote, iclass 18, count 0 2006.197.08:05:57.95#ibcon#about to read 3, iclass 18, count 0 2006.197.08:05:57.98#ibcon#read 3, iclass 18, count 0 2006.197.08:05:57.98#ibcon#about to read 4, iclass 18, count 0 2006.197.08:05:57.98#ibcon#read 4, iclass 18, count 0 2006.197.08:05:57.98#ibcon#about to read 5, iclass 18, count 0 2006.197.08:05:57.98#ibcon#read 5, iclass 18, count 0 2006.197.08:05:57.98#ibcon#about to read 6, iclass 18, count 0 2006.197.08:05:57.98#ibcon#read 6, iclass 18, count 0 2006.197.08:05:57.98#ibcon#end of sib2, iclass 18, count 0 2006.197.08:05:57.98#ibcon#*after write, iclass 18, count 0 2006.197.08:05:57.98#ibcon#*before return 0, iclass 18, count 0 2006.197.08:05:57.98#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.197.08:05:57.98#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.197.08:05:57.98#ibcon#about to clear, iclass 18 cls_cnt 0 2006.197.08:05:57.98#ibcon#cleared, iclass 18 cls_cnt 0 2006.197.08:05:57.98$vc4f8/valo=2,572.99 2006.197.08:05:57.98#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.197.08:05:57.98#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.197.08:05:57.98#ibcon#ireg 17 cls_cnt 0 2006.197.08:05:57.98#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.197.08:05:57.98#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.197.08:05:57.98#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.197.08:05:57.98#ibcon#enter wrdev, iclass 20, count 0 2006.197.08:05:57.98#ibcon#first serial, iclass 20, count 0 2006.197.08:05:57.98#ibcon#enter sib2, iclass 20, count 0 2006.197.08:05:57.98#ibcon#flushed, iclass 20, count 0 2006.197.08:05:57.98#ibcon#about to write, iclass 20, count 0 2006.197.08:05:57.98#ibcon#wrote, iclass 20, count 0 2006.197.08:05:57.98#ibcon#about to read 3, iclass 20, count 0 2006.197.08:05:58.00#ibcon#read 3, iclass 20, count 0 2006.197.08:05:58.00#ibcon#about to read 4, iclass 20, count 0 2006.197.08:05:58.00#ibcon#read 4, iclass 20, count 0 2006.197.08:05:58.00#ibcon#about to read 5, iclass 20, count 0 2006.197.08:05:58.00#ibcon#read 5, iclass 20, count 0 2006.197.08:05:58.00#ibcon#about to read 6, iclass 20, count 0 2006.197.08:05:58.00#ibcon#read 6, iclass 20, count 0 2006.197.08:05:58.00#ibcon#end of sib2, iclass 20, count 0 2006.197.08:05:58.00#ibcon#*mode == 0, iclass 20, count 0 2006.197.08:05:58.00#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.197.08:05:58.00#ibcon#[26=FRQ=02,572.99\r\n] 2006.197.08:05:58.00#ibcon#*before write, iclass 20, count 0 2006.197.08:05:58.00#ibcon#enter sib2, iclass 20, count 0 2006.197.08:05:58.00#ibcon#flushed, iclass 20, count 0 2006.197.08:05:58.00#ibcon#about to write, iclass 20, count 0 2006.197.08:05:58.00#ibcon#wrote, iclass 20, count 0 2006.197.08:05:58.00#ibcon#about to read 3, iclass 20, count 0 2006.197.08:05:58.04#ibcon#read 3, iclass 20, count 0 2006.197.08:05:58.04#ibcon#about to read 4, iclass 20, count 0 2006.197.08:05:58.04#ibcon#read 4, iclass 20, count 0 2006.197.08:05:58.04#ibcon#about to read 5, iclass 20, count 0 2006.197.08:05:58.04#ibcon#read 5, iclass 20, count 0 2006.197.08:05:58.04#ibcon#about to read 6, iclass 20, count 0 2006.197.08:05:58.04#ibcon#read 6, iclass 20, count 0 2006.197.08:05:58.04#ibcon#end of sib2, iclass 20, count 0 2006.197.08:05:58.04#ibcon#*after write, iclass 20, count 0 2006.197.08:05:58.04#ibcon#*before return 0, iclass 20, count 0 2006.197.08:05:58.04#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.197.08:05:58.04#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.197.08:05:58.04#ibcon#about to clear, iclass 20 cls_cnt 0 2006.197.08:05:58.04#ibcon#cleared, iclass 20 cls_cnt 0 2006.197.08:05:58.04$vc4f8/va=2,7 2006.197.08:05:58.04#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.197.08:05:58.04#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.197.08:05:58.04#ibcon#ireg 11 cls_cnt 2 2006.197.08:05:58.04#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.197.08:05:58.10#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.197.08:05:58.10#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.197.08:05:58.10#ibcon#enter wrdev, iclass 22, count 2 2006.197.08:05:58.10#ibcon#first serial, iclass 22, count 2 2006.197.08:05:58.10#ibcon#enter sib2, iclass 22, count 2 2006.197.08:05:58.10#ibcon#flushed, iclass 22, count 2 2006.197.08:05:58.10#ibcon#about to write, iclass 22, count 2 2006.197.08:05:58.10#ibcon#wrote, iclass 22, count 2 2006.197.08:05:58.10#ibcon#about to read 3, iclass 22, count 2 2006.197.08:05:58.12#ibcon#read 3, iclass 22, count 2 2006.197.08:05:58.12#ibcon#about to read 4, iclass 22, count 2 2006.197.08:05:58.12#ibcon#read 4, iclass 22, count 2 2006.197.08:05:58.12#ibcon#about to read 5, iclass 22, count 2 2006.197.08:05:58.12#ibcon#read 5, iclass 22, count 2 2006.197.08:05:58.12#ibcon#about to read 6, iclass 22, count 2 2006.197.08:05:58.12#ibcon#read 6, iclass 22, count 2 2006.197.08:05:58.12#ibcon#end of sib2, iclass 22, count 2 2006.197.08:05:58.12#ibcon#*mode == 0, iclass 22, count 2 2006.197.08:05:58.12#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.197.08:05:58.12#ibcon#[25=AT02-07\r\n] 2006.197.08:05:58.12#ibcon#*before write, iclass 22, count 2 2006.197.08:05:58.12#ibcon#enter sib2, iclass 22, count 2 2006.197.08:05:58.12#ibcon#flushed, iclass 22, count 2 2006.197.08:05:58.12#ibcon#about to write, iclass 22, count 2 2006.197.08:05:58.12#ibcon#wrote, iclass 22, count 2 2006.197.08:05:58.12#ibcon#about to read 3, iclass 22, count 2 2006.197.08:05:58.15#ibcon#read 3, iclass 22, count 2 2006.197.08:05:58.15#ibcon#about to read 4, iclass 22, count 2 2006.197.08:05:58.15#ibcon#read 4, iclass 22, count 2 2006.197.08:05:58.15#ibcon#about to read 5, iclass 22, count 2 2006.197.08:05:58.15#ibcon#read 5, iclass 22, count 2 2006.197.08:05:58.15#ibcon#about to read 6, iclass 22, count 2 2006.197.08:05:58.15#ibcon#read 6, iclass 22, count 2 2006.197.08:05:58.15#ibcon#end of sib2, iclass 22, count 2 2006.197.08:05:58.15#ibcon#*after write, iclass 22, count 2 2006.197.08:05:58.15#ibcon#*before return 0, iclass 22, count 2 2006.197.08:05:58.15#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.197.08:05:58.15#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.197.08:05:58.15#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.197.08:05:58.15#ibcon#ireg 7 cls_cnt 0 2006.197.08:05:58.15#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.197.08:05:58.27#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.197.08:05:58.27#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.197.08:05:58.27#ibcon#enter wrdev, iclass 22, count 0 2006.197.08:05:58.27#ibcon#first serial, iclass 22, count 0 2006.197.08:05:58.27#ibcon#enter sib2, iclass 22, count 0 2006.197.08:05:58.27#ibcon#flushed, iclass 22, count 0 2006.197.08:05:58.27#ibcon#about to write, iclass 22, count 0 2006.197.08:05:58.27#ibcon#wrote, iclass 22, count 0 2006.197.08:05:58.27#ibcon#about to read 3, iclass 22, count 0 2006.197.08:05:58.29#ibcon#read 3, iclass 22, count 0 2006.197.08:05:58.29#ibcon#about to read 4, iclass 22, count 0 2006.197.08:05:58.29#ibcon#read 4, iclass 22, count 0 2006.197.08:05:58.29#ibcon#about to read 5, iclass 22, count 0 2006.197.08:05:58.29#ibcon#read 5, iclass 22, count 0 2006.197.08:05:58.29#ibcon#about to read 6, iclass 22, count 0 2006.197.08:05:58.29#ibcon#read 6, iclass 22, count 0 2006.197.08:05:58.29#ibcon#end of sib2, iclass 22, count 0 2006.197.08:05:58.29#ibcon#*mode == 0, iclass 22, count 0 2006.197.08:05:58.29#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.197.08:05:58.29#ibcon#[25=USB\r\n] 2006.197.08:05:58.29#ibcon#*before write, iclass 22, count 0 2006.197.08:05:58.29#ibcon#enter sib2, iclass 22, count 0 2006.197.08:05:58.29#ibcon#flushed, iclass 22, count 0 2006.197.08:05:58.29#ibcon#about to write, iclass 22, count 0 2006.197.08:05:58.29#ibcon#wrote, iclass 22, count 0 2006.197.08:05:58.29#ibcon#about to read 3, iclass 22, count 0 2006.197.08:05:58.32#ibcon#read 3, iclass 22, count 0 2006.197.08:05:58.32#ibcon#about to read 4, iclass 22, count 0 2006.197.08:05:58.32#ibcon#read 4, iclass 22, count 0 2006.197.08:05:58.32#ibcon#about to read 5, iclass 22, count 0 2006.197.08:05:58.32#ibcon#read 5, iclass 22, count 0 2006.197.08:05:58.32#ibcon#about to read 6, iclass 22, count 0 2006.197.08:05:58.32#ibcon#read 6, iclass 22, count 0 2006.197.08:05:58.32#ibcon#end of sib2, iclass 22, count 0 2006.197.08:05:58.32#ibcon#*after write, iclass 22, count 0 2006.197.08:05:58.32#ibcon#*before return 0, iclass 22, count 0 2006.197.08:05:58.32#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.197.08:05:58.32#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.197.08:05:58.32#ibcon#about to clear, iclass 22 cls_cnt 0 2006.197.08:05:58.32#ibcon#cleared, iclass 22 cls_cnt 0 2006.197.08:05:58.32$vc4f8/valo=3,672.99 2006.197.08:05:58.32#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.197.08:05:58.32#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.197.08:05:58.32#ibcon#ireg 17 cls_cnt 0 2006.197.08:05:58.32#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.197.08:05:58.32#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.197.08:05:58.32#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.197.08:05:58.32#ibcon#enter wrdev, iclass 24, count 0 2006.197.08:05:58.32#ibcon#first serial, iclass 24, count 0 2006.197.08:05:58.32#ibcon#enter sib2, iclass 24, count 0 2006.197.08:05:58.32#ibcon#flushed, iclass 24, count 0 2006.197.08:05:58.32#ibcon#about to write, iclass 24, count 0 2006.197.08:05:58.32#ibcon#wrote, iclass 24, count 0 2006.197.08:05:58.32#ibcon#about to read 3, iclass 24, count 0 2006.197.08:05:58.34#ibcon#read 3, iclass 24, count 0 2006.197.08:05:58.34#ibcon#about to read 4, iclass 24, count 0 2006.197.08:05:58.34#ibcon#read 4, iclass 24, count 0 2006.197.08:05:58.34#ibcon#about to read 5, iclass 24, count 0 2006.197.08:05:58.34#ibcon#read 5, iclass 24, count 0 2006.197.08:05:58.34#ibcon#about to read 6, iclass 24, count 0 2006.197.08:05:58.34#ibcon#read 6, iclass 24, count 0 2006.197.08:05:58.34#ibcon#end of sib2, iclass 24, count 0 2006.197.08:05:58.34#ibcon#*mode == 0, iclass 24, count 0 2006.197.08:05:58.34#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.197.08:05:58.34#ibcon#[26=FRQ=03,672.99\r\n] 2006.197.08:05:58.34#ibcon#*before write, iclass 24, count 0 2006.197.08:05:58.34#ibcon#enter sib2, iclass 24, count 0 2006.197.08:05:58.34#ibcon#flushed, iclass 24, count 0 2006.197.08:05:58.34#ibcon#about to write, iclass 24, count 0 2006.197.08:05:58.34#ibcon#wrote, iclass 24, count 0 2006.197.08:05:58.34#ibcon#about to read 3, iclass 24, count 0 2006.197.08:05:58.38#ibcon#read 3, iclass 24, count 0 2006.197.08:05:58.38#ibcon#about to read 4, iclass 24, count 0 2006.197.08:05:58.38#ibcon#read 4, iclass 24, count 0 2006.197.08:05:58.38#ibcon#about to read 5, iclass 24, count 0 2006.197.08:05:58.38#ibcon#read 5, iclass 24, count 0 2006.197.08:05:58.38#ibcon#about to read 6, iclass 24, count 0 2006.197.08:05:58.38#ibcon#read 6, iclass 24, count 0 2006.197.08:05:58.38#ibcon#end of sib2, iclass 24, count 0 2006.197.08:05:58.38#ibcon#*after write, iclass 24, count 0 2006.197.08:05:58.38#ibcon#*before return 0, iclass 24, count 0 2006.197.08:05:58.38#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.197.08:05:58.38#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.197.08:05:58.38#ibcon#about to clear, iclass 24 cls_cnt 0 2006.197.08:05:58.38#ibcon#cleared, iclass 24 cls_cnt 0 2006.197.08:05:58.38$vc4f8/va=3,6 2006.197.08:05:58.38#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.197.08:05:58.38#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.197.08:05:58.38#ibcon#ireg 11 cls_cnt 2 2006.197.08:05:58.38#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.197.08:05:58.44#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.197.08:05:58.44#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.197.08:05:58.44#ibcon#enter wrdev, iclass 26, count 2 2006.197.08:05:58.44#ibcon#first serial, iclass 26, count 2 2006.197.08:05:58.44#ibcon#enter sib2, iclass 26, count 2 2006.197.08:05:58.44#ibcon#flushed, iclass 26, count 2 2006.197.08:05:58.44#ibcon#about to write, iclass 26, count 2 2006.197.08:05:58.44#ibcon#wrote, iclass 26, count 2 2006.197.08:05:58.44#ibcon#about to read 3, iclass 26, count 2 2006.197.08:05:58.46#ibcon#read 3, iclass 26, count 2 2006.197.08:05:58.46#ibcon#about to read 4, iclass 26, count 2 2006.197.08:05:58.46#ibcon#read 4, iclass 26, count 2 2006.197.08:05:58.46#ibcon#about to read 5, iclass 26, count 2 2006.197.08:05:58.46#ibcon#read 5, iclass 26, count 2 2006.197.08:05:58.46#ibcon#about to read 6, iclass 26, count 2 2006.197.08:05:58.46#ibcon#read 6, iclass 26, count 2 2006.197.08:05:58.46#ibcon#end of sib2, iclass 26, count 2 2006.197.08:05:58.46#ibcon#*mode == 0, iclass 26, count 2 2006.197.08:05:58.46#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.197.08:05:58.46#ibcon#[25=AT03-06\r\n] 2006.197.08:05:58.46#ibcon#*before write, iclass 26, count 2 2006.197.08:05:58.46#ibcon#enter sib2, iclass 26, count 2 2006.197.08:05:58.46#ibcon#flushed, iclass 26, count 2 2006.197.08:05:58.46#ibcon#about to write, iclass 26, count 2 2006.197.08:05:58.46#ibcon#wrote, iclass 26, count 2 2006.197.08:05:58.46#ibcon#about to read 3, iclass 26, count 2 2006.197.08:05:58.49#ibcon#read 3, iclass 26, count 2 2006.197.08:05:58.49#ibcon#about to read 4, iclass 26, count 2 2006.197.08:05:58.49#ibcon#read 4, iclass 26, count 2 2006.197.08:05:58.49#ibcon#about to read 5, iclass 26, count 2 2006.197.08:05:58.49#ibcon#read 5, iclass 26, count 2 2006.197.08:05:58.49#ibcon#about to read 6, iclass 26, count 2 2006.197.08:05:58.49#ibcon#read 6, iclass 26, count 2 2006.197.08:05:58.49#ibcon#end of sib2, iclass 26, count 2 2006.197.08:05:58.49#ibcon#*after write, iclass 26, count 2 2006.197.08:05:58.49#ibcon#*before return 0, iclass 26, count 2 2006.197.08:05:58.49#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.197.08:05:58.49#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.197.08:05:58.49#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.197.08:05:58.49#ibcon#ireg 7 cls_cnt 0 2006.197.08:05:58.49#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.197.08:05:58.61#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.197.08:05:58.61#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.197.08:05:58.61#ibcon#enter wrdev, iclass 26, count 0 2006.197.08:05:58.61#ibcon#first serial, iclass 26, count 0 2006.197.08:05:58.61#ibcon#enter sib2, iclass 26, count 0 2006.197.08:05:58.61#ibcon#flushed, iclass 26, count 0 2006.197.08:05:58.61#ibcon#about to write, iclass 26, count 0 2006.197.08:05:58.61#ibcon#wrote, iclass 26, count 0 2006.197.08:05:58.61#ibcon#about to read 3, iclass 26, count 0 2006.197.08:05:58.63#ibcon#read 3, iclass 26, count 0 2006.197.08:05:58.63#ibcon#about to read 4, iclass 26, count 0 2006.197.08:05:58.63#ibcon#read 4, iclass 26, count 0 2006.197.08:05:58.63#ibcon#about to read 5, iclass 26, count 0 2006.197.08:05:58.63#ibcon#read 5, iclass 26, count 0 2006.197.08:05:58.63#ibcon#about to read 6, iclass 26, count 0 2006.197.08:05:58.63#ibcon#read 6, iclass 26, count 0 2006.197.08:05:58.63#ibcon#end of sib2, iclass 26, count 0 2006.197.08:05:58.63#ibcon#*mode == 0, iclass 26, count 0 2006.197.08:05:58.63#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.197.08:05:58.63#ibcon#[25=USB\r\n] 2006.197.08:05:58.63#ibcon#*before write, iclass 26, count 0 2006.197.08:05:58.63#ibcon#enter sib2, iclass 26, count 0 2006.197.08:05:58.63#ibcon#flushed, iclass 26, count 0 2006.197.08:05:58.63#ibcon#about to write, iclass 26, count 0 2006.197.08:05:58.63#ibcon#wrote, iclass 26, count 0 2006.197.08:05:58.63#ibcon#about to read 3, iclass 26, count 0 2006.197.08:05:58.66#ibcon#read 3, iclass 26, count 0 2006.197.08:05:58.66#ibcon#about to read 4, iclass 26, count 0 2006.197.08:05:58.66#ibcon#read 4, iclass 26, count 0 2006.197.08:05:58.66#ibcon#about to read 5, iclass 26, count 0 2006.197.08:05:58.66#ibcon#read 5, iclass 26, count 0 2006.197.08:05:58.66#ibcon#about to read 6, iclass 26, count 0 2006.197.08:05:58.66#ibcon#read 6, iclass 26, count 0 2006.197.08:05:58.66#ibcon#end of sib2, iclass 26, count 0 2006.197.08:05:58.66#ibcon#*after write, iclass 26, count 0 2006.197.08:05:58.66#ibcon#*before return 0, iclass 26, count 0 2006.197.08:05:58.66#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.197.08:05:58.66#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.197.08:05:58.66#ibcon#about to clear, iclass 26 cls_cnt 0 2006.197.08:05:58.66#ibcon#cleared, iclass 26 cls_cnt 0 2006.197.08:05:58.66$vc4f8/valo=4,832.99 2006.197.08:05:58.66#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.197.08:05:58.66#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.197.08:05:58.66#ibcon#ireg 17 cls_cnt 0 2006.197.08:05:58.66#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.197.08:05:58.66#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.197.08:05:58.66#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.197.08:05:58.66#ibcon#enter wrdev, iclass 28, count 0 2006.197.08:05:58.66#ibcon#first serial, iclass 28, count 0 2006.197.08:05:58.66#ibcon#enter sib2, iclass 28, count 0 2006.197.08:05:58.66#ibcon#flushed, iclass 28, count 0 2006.197.08:05:58.66#ibcon#about to write, iclass 28, count 0 2006.197.08:05:58.66#ibcon#wrote, iclass 28, count 0 2006.197.08:05:58.66#ibcon#about to read 3, iclass 28, count 0 2006.197.08:05:58.68#ibcon#read 3, iclass 28, count 0 2006.197.08:05:58.68#ibcon#about to read 4, iclass 28, count 0 2006.197.08:05:58.68#ibcon#read 4, iclass 28, count 0 2006.197.08:05:58.68#ibcon#about to read 5, iclass 28, count 0 2006.197.08:05:58.68#ibcon#read 5, iclass 28, count 0 2006.197.08:05:58.68#ibcon#about to read 6, iclass 28, count 0 2006.197.08:05:58.68#ibcon#read 6, iclass 28, count 0 2006.197.08:05:58.68#ibcon#end of sib2, iclass 28, count 0 2006.197.08:05:58.68#ibcon#*mode == 0, iclass 28, count 0 2006.197.08:05:58.68#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.197.08:05:58.68#ibcon#[26=FRQ=04,832.99\r\n] 2006.197.08:05:58.68#ibcon#*before write, iclass 28, count 0 2006.197.08:05:58.68#ibcon#enter sib2, iclass 28, count 0 2006.197.08:05:58.68#ibcon#flushed, iclass 28, count 0 2006.197.08:05:58.68#ibcon#about to write, iclass 28, count 0 2006.197.08:05:58.68#ibcon#wrote, iclass 28, count 0 2006.197.08:05:58.68#ibcon#about to read 3, iclass 28, count 0 2006.197.08:05:58.72#ibcon#read 3, iclass 28, count 0 2006.197.08:05:58.72#ibcon#about to read 4, iclass 28, count 0 2006.197.08:05:58.72#ibcon#read 4, iclass 28, count 0 2006.197.08:05:58.72#ibcon#about to read 5, iclass 28, count 0 2006.197.08:05:58.72#ibcon#read 5, iclass 28, count 0 2006.197.08:05:58.72#ibcon#about to read 6, iclass 28, count 0 2006.197.08:05:58.72#ibcon#read 6, iclass 28, count 0 2006.197.08:05:58.72#ibcon#end of sib2, iclass 28, count 0 2006.197.08:05:58.72#ibcon#*after write, iclass 28, count 0 2006.197.08:05:58.72#ibcon#*before return 0, iclass 28, count 0 2006.197.08:05:58.72#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.197.08:05:58.72#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.197.08:05:58.72#ibcon#about to clear, iclass 28 cls_cnt 0 2006.197.08:05:58.72#ibcon#cleared, iclass 28 cls_cnt 0 2006.197.08:05:58.72$vc4f8/va=4,7 2006.197.08:05:58.72#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.197.08:05:58.72#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.197.08:05:58.72#ibcon#ireg 11 cls_cnt 2 2006.197.08:05:58.72#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.197.08:05:58.78#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.197.08:05:58.78#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.197.08:05:58.78#ibcon#enter wrdev, iclass 30, count 2 2006.197.08:05:58.78#ibcon#first serial, iclass 30, count 2 2006.197.08:05:58.78#ibcon#enter sib2, iclass 30, count 2 2006.197.08:05:58.78#ibcon#flushed, iclass 30, count 2 2006.197.08:05:58.78#ibcon#about to write, iclass 30, count 2 2006.197.08:05:58.78#ibcon#wrote, iclass 30, count 2 2006.197.08:05:58.78#ibcon#about to read 3, iclass 30, count 2 2006.197.08:05:58.80#ibcon#read 3, iclass 30, count 2 2006.197.08:05:58.80#ibcon#about to read 4, iclass 30, count 2 2006.197.08:05:58.80#ibcon#read 4, iclass 30, count 2 2006.197.08:05:58.80#ibcon#about to read 5, iclass 30, count 2 2006.197.08:05:58.80#ibcon#read 5, iclass 30, count 2 2006.197.08:05:58.80#ibcon#about to read 6, iclass 30, count 2 2006.197.08:05:58.80#ibcon#read 6, iclass 30, count 2 2006.197.08:05:58.80#ibcon#end of sib2, iclass 30, count 2 2006.197.08:05:58.80#ibcon#*mode == 0, iclass 30, count 2 2006.197.08:05:58.80#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.197.08:05:58.80#ibcon#[25=AT04-07\r\n] 2006.197.08:05:58.80#ibcon#*before write, iclass 30, count 2 2006.197.08:05:58.80#ibcon#enter sib2, iclass 30, count 2 2006.197.08:05:58.80#ibcon#flushed, iclass 30, count 2 2006.197.08:05:58.80#ibcon#about to write, iclass 30, count 2 2006.197.08:05:58.80#ibcon#wrote, iclass 30, count 2 2006.197.08:05:58.80#ibcon#about to read 3, iclass 30, count 2 2006.197.08:05:58.83#ibcon#read 3, iclass 30, count 2 2006.197.08:05:58.83#ibcon#about to read 4, iclass 30, count 2 2006.197.08:05:58.83#ibcon#read 4, iclass 30, count 2 2006.197.08:05:58.83#ibcon#about to read 5, iclass 30, count 2 2006.197.08:05:58.83#ibcon#read 5, iclass 30, count 2 2006.197.08:05:58.83#ibcon#about to read 6, iclass 30, count 2 2006.197.08:05:58.83#ibcon#read 6, iclass 30, count 2 2006.197.08:05:58.83#ibcon#end of sib2, iclass 30, count 2 2006.197.08:05:58.83#ibcon#*after write, iclass 30, count 2 2006.197.08:05:58.83#ibcon#*before return 0, iclass 30, count 2 2006.197.08:05:58.83#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.197.08:05:58.83#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.197.08:05:58.83#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.197.08:05:58.83#ibcon#ireg 7 cls_cnt 0 2006.197.08:05:58.83#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.197.08:05:58.95#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.197.08:05:58.95#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.197.08:05:58.95#ibcon#enter wrdev, iclass 30, count 0 2006.197.08:05:58.95#ibcon#first serial, iclass 30, count 0 2006.197.08:05:58.95#ibcon#enter sib2, iclass 30, count 0 2006.197.08:05:58.95#ibcon#flushed, iclass 30, count 0 2006.197.08:05:58.95#ibcon#about to write, iclass 30, count 0 2006.197.08:05:58.95#ibcon#wrote, iclass 30, count 0 2006.197.08:05:58.95#ibcon#about to read 3, iclass 30, count 0 2006.197.08:05:58.97#ibcon#read 3, iclass 30, count 0 2006.197.08:05:58.97#ibcon#about to read 4, iclass 30, count 0 2006.197.08:05:58.97#ibcon#read 4, iclass 30, count 0 2006.197.08:05:58.97#ibcon#about to read 5, iclass 30, count 0 2006.197.08:05:58.97#ibcon#read 5, iclass 30, count 0 2006.197.08:05:58.97#ibcon#about to read 6, iclass 30, count 0 2006.197.08:05:58.97#ibcon#read 6, iclass 30, count 0 2006.197.08:05:58.97#ibcon#end of sib2, iclass 30, count 0 2006.197.08:05:58.97#ibcon#*mode == 0, iclass 30, count 0 2006.197.08:05:58.97#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.197.08:05:58.97#ibcon#[25=USB\r\n] 2006.197.08:05:58.97#ibcon#*before write, iclass 30, count 0 2006.197.08:05:58.97#ibcon#enter sib2, iclass 30, count 0 2006.197.08:05:58.97#ibcon#flushed, iclass 30, count 0 2006.197.08:05:58.97#ibcon#about to write, iclass 30, count 0 2006.197.08:05:58.97#ibcon#wrote, iclass 30, count 0 2006.197.08:05:58.97#ibcon#about to read 3, iclass 30, count 0 2006.197.08:05:59.00#ibcon#read 3, iclass 30, count 0 2006.197.08:05:59.00#ibcon#about to read 4, iclass 30, count 0 2006.197.08:05:59.00#ibcon#read 4, iclass 30, count 0 2006.197.08:05:59.00#ibcon#about to read 5, iclass 30, count 0 2006.197.08:05:59.00#ibcon#read 5, iclass 30, count 0 2006.197.08:05:59.00#ibcon#about to read 6, iclass 30, count 0 2006.197.08:05:59.00#ibcon#read 6, iclass 30, count 0 2006.197.08:05:59.00#ibcon#end of sib2, iclass 30, count 0 2006.197.08:05:59.00#ibcon#*after write, iclass 30, count 0 2006.197.08:05:59.00#ibcon#*before return 0, iclass 30, count 0 2006.197.08:05:59.00#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.197.08:05:59.00#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.197.08:05:59.00#ibcon#about to clear, iclass 30 cls_cnt 0 2006.197.08:05:59.00#ibcon#cleared, iclass 30 cls_cnt 0 2006.197.08:05:59.00$vc4f8/valo=5,652.99 2006.197.08:05:59.00#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.197.08:05:59.00#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.197.08:05:59.00#ibcon#ireg 17 cls_cnt 0 2006.197.08:05:59.00#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.197.08:05:59.00#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.197.08:05:59.00#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.197.08:05:59.00#ibcon#enter wrdev, iclass 32, count 0 2006.197.08:05:59.00#ibcon#first serial, iclass 32, count 0 2006.197.08:05:59.00#ibcon#enter sib2, iclass 32, count 0 2006.197.08:05:59.00#ibcon#flushed, iclass 32, count 0 2006.197.08:05:59.00#ibcon#about to write, iclass 32, count 0 2006.197.08:05:59.00#ibcon#wrote, iclass 32, count 0 2006.197.08:05:59.00#ibcon#about to read 3, iclass 32, count 0 2006.197.08:05:59.02#ibcon#read 3, iclass 32, count 0 2006.197.08:05:59.02#ibcon#about to read 4, iclass 32, count 0 2006.197.08:05:59.02#ibcon#read 4, iclass 32, count 0 2006.197.08:05:59.02#ibcon#about to read 5, iclass 32, count 0 2006.197.08:05:59.02#ibcon#read 5, iclass 32, count 0 2006.197.08:05:59.02#ibcon#about to read 6, iclass 32, count 0 2006.197.08:05:59.02#ibcon#read 6, iclass 32, count 0 2006.197.08:05:59.02#ibcon#end of sib2, iclass 32, count 0 2006.197.08:05:59.02#ibcon#*mode == 0, iclass 32, count 0 2006.197.08:05:59.02#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.197.08:05:59.02#ibcon#[26=FRQ=05,652.99\r\n] 2006.197.08:05:59.02#ibcon#*before write, iclass 32, count 0 2006.197.08:05:59.02#ibcon#enter sib2, iclass 32, count 0 2006.197.08:05:59.02#ibcon#flushed, iclass 32, count 0 2006.197.08:05:59.02#ibcon#about to write, iclass 32, count 0 2006.197.08:05:59.02#ibcon#wrote, iclass 32, count 0 2006.197.08:05:59.02#ibcon#about to read 3, iclass 32, count 0 2006.197.08:05:59.06#ibcon#read 3, iclass 32, count 0 2006.197.08:05:59.06#ibcon#about to read 4, iclass 32, count 0 2006.197.08:05:59.06#ibcon#read 4, iclass 32, count 0 2006.197.08:05:59.06#ibcon#about to read 5, iclass 32, count 0 2006.197.08:05:59.06#ibcon#read 5, iclass 32, count 0 2006.197.08:05:59.06#ibcon#about to read 6, iclass 32, count 0 2006.197.08:05:59.06#ibcon#read 6, iclass 32, count 0 2006.197.08:05:59.06#ibcon#end of sib2, iclass 32, count 0 2006.197.08:05:59.06#ibcon#*after write, iclass 32, count 0 2006.197.08:05:59.06#ibcon#*before return 0, iclass 32, count 0 2006.197.08:05:59.06#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.197.08:05:59.06#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.197.08:05:59.06#ibcon#about to clear, iclass 32 cls_cnt 0 2006.197.08:05:59.06#ibcon#cleared, iclass 32 cls_cnt 0 2006.197.08:05:59.06$vc4f8/va=5,7 2006.197.08:05:59.06#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.197.08:05:59.06#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.197.08:05:59.06#ibcon#ireg 11 cls_cnt 2 2006.197.08:05:59.06#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.197.08:05:59.12#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.197.08:05:59.12#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.197.08:05:59.12#ibcon#enter wrdev, iclass 34, count 2 2006.197.08:05:59.12#ibcon#first serial, iclass 34, count 2 2006.197.08:05:59.12#ibcon#enter sib2, iclass 34, count 2 2006.197.08:05:59.12#ibcon#flushed, iclass 34, count 2 2006.197.08:05:59.12#ibcon#about to write, iclass 34, count 2 2006.197.08:05:59.12#ibcon#wrote, iclass 34, count 2 2006.197.08:05:59.12#ibcon#about to read 3, iclass 34, count 2 2006.197.08:05:59.14#ibcon#read 3, iclass 34, count 2 2006.197.08:05:59.14#ibcon#about to read 4, iclass 34, count 2 2006.197.08:05:59.14#ibcon#read 4, iclass 34, count 2 2006.197.08:05:59.14#ibcon#about to read 5, iclass 34, count 2 2006.197.08:05:59.14#ibcon#read 5, iclass 34, count 2 2006.197.08:05:59.14#ibcon#about to read 6, iclass 34, count 2 2006.197.08:05:59.14#ibcon#read 6, iclass 34, count 2 2006.197.08:05:59.14#ibcon#end of sib2, iclass 34, count 2 2006.197.08:05:59.14#ibcon#*mode == 0, iclass 34, count 2 2006.197.08:05:59.14#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.197.08:05:59.14#ibcon#[25=AT05-07\r\n] 2006.197.08:05:59.14#ibcon#*before write, iclass 34, count 2 2006.197.08:05:59.14#ibcon#enter sib2, iclass 34, count 2 2006.197.08:05:59.14#ibcon#flushed, iclass 34, count 2 2006.197.08:05:59.14#ibcon#about to write, iclass 34, count 2 2006.197.08:05:59.14#ibcon#wrote, iclass 34, count 2 2006.197.08:05:59.14#ibcon#about to read 3, iclass 34, count 2 2006.197.08:05:59.17#ibcon#read 3, iclass 34, count 2 2006.197.08:05:59.17#ibcon#about to read 4, iclass 34, count 2 2006.197.08:05:59.17#ibcon#read 4, iclass 34, count 2 2006.197.08:05:59.17#ibcon#about to read 5, iclass 34, count 2 2006.197.08:05:59.17#ibcon#read 5, iclass 34, count 2 2006.197.08:05:59.17#ibcon#about to read 6, iclass 34, count 2 2006.197.08:05:59.17#ibcon#read 6, iclass 34, count 2 2006.197.08:05:59.17#ibcon#end of sib2, iclass 34, count 2 2006.197.08:05:59.17#ibcon#*after write, iclass 34, count 2 2006.197.08:05:59.17#ibcon#*before return 0, iclass 34, count 2 2006.197.08:05:59.17#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.197.08:05:59.17#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.197.08:05:59.17#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.197.08:05:59.17#ibcon#ireg 7 cls_cnt 0 2006.197.08:05:59.17#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.197.08:05:59.29#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.197.08:05:59.29#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.197.08:05:59.29#ibcon#enter wrdev, iclass 34, count 0 2006.197.08:05:59.29#ibcon#first serial, iclass 34, count 0 2006.197.08:05:59.29#ibcon#enter sib2, iclass 34, count 0 2006.197.08:05:59.29#ibcon#flushed, iclass 34, count 0 2006.197.08:05:59.29#ibcon#about to write, iclass 34, count 0 2006.197.08:05:59.29#ibcon#wrote, iclass 34, count 0 2006.197.08:05:59.29#ibcon#about to read 3, iclass 34, count 0 2006.197.08:05:59.31#ibcon#read 3, iclass 34, count 0 2006.197.08:05:59.31#ibcon#about to read 4, iclass 34, count 0 2006.197.08:05:59.31#ibcon#read 4, iclass 34, count 0 2006.197.08:05:59.31#ibcon#about to read 5, iclass 34, count 0 2006.197.08:05:59.31#ibcon#read 5, iclass 34, count 0 2006.197.08:05:59.31#ibcon#about to read 6, iclass 34, count 0 2006.197.08:05:59.31#ibcon#read 6, iclass 34, count 0 2006.197.08:05:59.31#ibcon#end of sib2, iclass 34, count 0 2006.197.08:05:59.31#ibcon#*mode == 0, iclass 34, count 0 2006.197.08:05:59.31#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.197.08:05:59.31#ibcon#[25=USB\r\n] 2006.197.08:05:59.31#ibcon#*before write, iclass 34, count 0 2006.197.08:05:59.31#ibcon#enter sib2, iclass 34, count 0 2006.197.08:05:59.31#ibcon#flushed, iclass 34, count 0 2006.197.08:05:59.31#ibcon#about to write, iclass 34, count 0 2006.197.08:05:59.31#ibcon#wrote, iclass 34, count 0 2006.197.08:05:59.31#ibcon#about to read 3, iclass 34, count 0 2006.197.08:05:59.34#ibcon#read 3, iclass 34, count 0 2006.197.08:05:59.34#ibcon#about to read 4, iclass 34, count 0 2006.197.08:05:59.34#ibcon#read 4, iclass 34, count 0 2006.197.08:05:59.34#ibcon#about to read 5, iclass 34, count 0 2006.197.08:05:59.34#ibcon#read 5, iclass 34, count 0 2006.197.08:05:59.34#ibcon#about to read 6, iclass 34, count 0 2006.197.08:05:59.34#ibcon#read 6, iclass 34, count 0 2006.197.08:05:59.34#ibcon#end of sib2, iclass 34, count 0 2006.197.08:05:59.34#ibcon#*after write, iclass 34, count 0 2006.197.08:05:59.34#ibcon#*before return 0, iclass 34, count 0 2006.197.08:05:59.34#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.197.08:05:59.34#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.197.08:05:59.34#ibcon#about to clear, iclass 34 cls_cnt 0 2006.197.08:05:59.34#ibcon#cleared, iclass 34 cls_cnt 0 2006.197.08:05:59.34$vc4f8/valo=6,772.99 2006.197.08:05:59.34#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.197.08:05:59.34#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.197.08:05:59.34#ibcon#ireg 17 cls_cnt 0 2006.197.08:05:59.34#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.197.08:05:59.34#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.197.08:05:59.34#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.197.08:05:59.34#ibcon#enter wrdev, iclass 36, count 0 2006.197.08:05:59.34#ibcon#first serial, iclass 36, count 0 2006.197.08:05:59.34#ibcon#enter sib2, iclass 36, count 0 2006.197.08:05:59.34#ibcon#flushed, iclass 36, count 0 2006.197.08:05:59.34#ibcon#about to write, iclass 36, count 0 2006.197.08:05:59.34#ibcon#wrote, iclass 36, count 0 2006.197.08:05:59.34#ibcon#about to read 3, iclass 36, count 0 2006.197.08:05:59.36#ibcon#read 3, iclass 36, count 0 2006.197.08:05:59.36#ibcon#about to read 4, iclass 36, count 0 2006.197.08:05:59.36#ibcon#read 4, iclass 36, count 0 2006.197.08:05:59.36#ibcon#about to read 5, iclass 36, count 0 2006.197.08:05:59.36#ibcon#read 5, iclass 36, count 0 2006.197.08:05:59.36#ibcon#about to read 6, iclass 36, count 0 2006.197.08:05:59.36#ibcon#read 6, iclass 36, count 0 2006.197.08:05:59.36#ibcon#end of sib2, iclass 36, count 0 2006.197.08:05:59.36#ibcon#*mode == 0, iclass 36, count 0 2006.197.08:05:59.36#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.197.08:05:59.36#ibcon#[26=FRQ=06,772.99\r\n] 2006.197.08:05:59.36#ibcon#*before write, iclass 36, count 0 2006.197.08:05:59.36#ibcon#enter sib2, iclass 36, count 0 2006.197.08:05:59.36#ibcon#flushed, iclass 36, count 0 2006.197.08:05:59.36#ibcon#about to write, iclass 36, count 0 2006.197.08:05:59.36#ibcon#wrote, iclass 36, count 0 2006.197.08:05:59.36#ibcon#about to read 3, iclass 36, count 0 2006.197.08:05:59.40#ibcon#read 3, iclass 36, count 0 2006.197.08:05:59.40#ibcon#about to read 4, iclass 36, count 0 2006.197.08:05:59.40#ibcon#read 4, iclass 36, count 0 2006.197.08:05:59.40#ibcon#about to read 5, iclass 36, count 0 2006.197.08:05:59.40#ibcon#read 5, iclass 36, count 0 2006.197.08:05:59.40#ibcon#about to read 6, iclass 36, count 0 2006.197.08:05:59.40#ibcon#read 6, iclass 36, count 0 2006.197.08:05:59.40#ibcon#end of sib2, iclass 36, count 0 2006.197.08:05:59.40#ibcon#*after write, iclass 36, count 0 2006.197.08:05:59.40#ibcon#*before return 0, iclass 36, count 0 2006.197.08:05:59.40#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.197.08:05:59.40#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.197.08:05:59.40#ibcon#about to clear, iclass 36 cls_cnt 0 2006.197.08:05:59.40#ibcon#cleared, iclass 36 cls_cnt 0 2006.197.08:05:59.40$vc4f8/va=6,6 2006.197.08:05:59.40#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.197.08:05:59.40#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.197.08:05:59.40#ibcon#ireg 11 cls_cnt 2 2006.197.08:05:59.40#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.197.08:05:59.46#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.197.08:05:59.46#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.197.08:05:59.46#ibcon#enter wrdev, iclass 38, count 2 2006.197.08:05:59.46#ibcon#first serial, iclass 38, count 2 2006.197.08:05:59.46#ibcon#enter sib2, iclass 38, count 2 2006.197.08:05:59.46#ibcon#flushed, iclass 38, count 2 2006.197.08:05:59.46#ibcon#about to write, iclass 38, count 2 2006.197.08:05:59.46#ibcon#wrote, iclass 38, count 2 2006.197.08:05:59.46#ibcon#about to read 3, iclass 38, count 2 2006.197.08:05:59.48#ibcon#read 3, iclass 38, count 2 2006.197.08:05:59.48#ibcon#about to read 4, iclass 38, count 2 2006.197.08:05:59.48#ibcon#read 4, iclass 38, count 2 2006.197.08:05:59.48#ibcon#about to read 5, iclass 38, count 2 2006.197.08:05:59.48#ibcon#read 5, iclass 38, count 2 2006.197.08:05:59.48#ibcon#about to read 6, iclass 38, count 2 2006.197.08:05:59.48#ibcon#read 6, iclass 38, count 2 2006.197.08:05:59.48#ibcon#end of sib2, iclass 38, count 2 2006.197.08:05:59.48#ibcon#*mode == 0, iclass 38, count 2 2006.197.08:05:59.48#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.197.08:05:59.48#ibcon#[25=AT06-06\r\n] 2006.197.08:05:59.48#ibcon#*before write, iclass 38, count 2 2006.197.08:05:59.48#ibcon#enter sib2, iclass 38, count 2 2006.197.08:05:59.48#ibcon#flushed, iclass 38, count 2 2006.197.08:05:59.48#ibcon#about to write, iclass 38, count 2 2006.197.08:05:59.48#ibcon#wrote, iclass 38, count 2 2006.197.08:05:59.48#ibcon#about to read 3, iclass 38, count 2 2006.197.08:05:59.51#ibcon#read 3, iclass 38, count 2 2006.197.08:05:59.51#ibcon#about to read 4, iclass 38, count 2 2006.197.08:05:59.51#ibcon#read 4, iclass 38, count 2 2006.197.08:05:59.51#ibcon#about to read 5, iclass 38, count 2 2006.197.08:05:59.51#ibcon#read 5, iclass 38, count 2 2006.197.08:05:59.51#ibcon#about to read 6, iclass 38, count 2 2006.197.08:05:59.51#ibcon#read 6, iclass 38, count 2 2006.197.08:05:59.51#ibcon#end of sib2, iclass 38, count 2 2006.197.08:05:59.51#ibcon#*after write, iclass 38, count 2 2006.197.08:05:59.51#ibcon#*before return 0, iclass 38, count 2 2006.197.08:05:59.51#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.197.08:05:59.51#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.197.08:05:59.51#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.197.08:05:59.51#ibcon#ireg 7 cls_cnt 0 2006.197.08:05:59.51#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.197.08:05:59.63#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.197.08:05:59.63#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.197.08:05:59.63#ibcon#enter wrdev, iclass 38, count 0 2006.197.08:05:59.63#ibcon#first serial, iclass 38, count 0 2006.197.08:05:59.63#ibcon#enter sib2, iclass 38, count 0 2006.197.08:05:59.63#ibcon#flushed, iclass 38, count 0 2006.197.08:05:59.63#ibcon#about to write, iclass 38, count 0 2006.197.08:05:59.63#ibcon#wrote, iclass 38, count 0 2006.197.08:05:59.63#ibcon#about to read 3, iclass 38, count 0 2006.197.08:05:59.65#ibcon#read 3, iclass 38, count 0 2006.197.08:05:59.65#ibcon#about to read 4, iclass 38, count 0 2006.197.08:05:59.65#ibcon#read 4, iclass 38, count 0 2006.197.08:05:59.65#ibcon#about to read 5, iclass 38, count 0 2006.197.08:05:59.65#ibcon#read 5, iclass 38, count 0 2006.197.08:05:59.65#ibcon#about to read 6, iclass 38, count 0 2006.197.08:05:59.65#ibcon#read 6, iclass 38, count 0 2006.197.08:05:59.65#ibcon#end of sib2, iclass 38, count 0 2006.197.08:05:59.65#ibcon#*mode == 0, iclass 38, count 0 2006.197.08:05:59.65#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.197.08:05:59.65#ibcon#[25=USB\r\n] 2006.197.08:05:59.65#ibcon#*before write, iclass 38, count 0 2006.197.08:05:59.65#ibcon#enter sib2, iclass 38, count 0 2006.197.08:05:59.65#ibcon#flushed, iclass 38, count 0 2006.197.08:05:59.65#ibcon#about to write, iclass 38, count 0 2006.197.08:05:59.65#ibcon#wrote, iclass 38, count 0 2006.197.08:05:59.65#ibcon#about to read 3, iclass 38, count 0 2006.197.08:05:59.68#ibcon#read 3, iclass 38, count 0 2006.197.08:05:59.68#ibcon#about to read 4, iclass 38, count 0 2006.197.08:05:59.68#ibcon#read 4, iclass 38, count 0 2006.197.08:05:59.68#ibcon#about to read 5, iclass 38, count 0 2006.197.08:05:59.68#ibcon#read 5, iclass 38, count 0 2006.197.08:05:59.68#ibcon#about to read 6, iclass 38, count 0 2006.197.08:05:59.68#ibcon#read 6, iclass 38, count 0 2006.197.08:05:59.68#ibcon#end of sib2, iclass 38, count 0 2006.197.08:05:59.68#ibcon#*after write, iclass 38, count 0 2006.197.08:05:59.68#ibcon#*before return 0, iclass 38, count 0 2006.197.08:05:59.68#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.197.08:05:59.68#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.197.08:05:59.68#ibcon#about to clear, iclass 38 cls_cnt 0 2006.197.08:05:59.68#ibcon#cleared, iclass 38 cls_cnt 0 2006.197.08:05:59.68$vc4f8/valo=7,832.99 2006.197.08:05:59.68#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.197.08:05:59.68#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.197.08:05:59.68#ibcon#ireg 17 cls_cnt 0 2006.197.08:05:59.68#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.197.08:05:59.68#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.197.08:05:59.68#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.197.08:05:59.68#ibcon#enter wrdev, iclass 40, count 0 2006.197.08:05:59.68#ibcon#first serial, iclass 40, count 0 2006.197.08:05:59.68#ibcon#enter sib2, iclass 40, count 0 2006.197.08:05:59.68#ibcon#flushed, iclass 40, count 0 2006.197.08:05:59.68#ibcon#about to write, iclass 40, count 0 2006.197.08:05:59.68#ibcon#wrote, iclass 40, count 0 2006.197.08:05:59.68#ibcon#about to read 3, iclass 40, count 0 2006.197.08:05:59.70#ibcon#read 3, iclass 40, count 0 2006.197.08:05:59.70#ibcon#about to read 4, iclass 40, count 0 2006.197.08:05:59.70#ibcon#read 4, iclass 40, count 0 2006.197.08:05:59.70#ibcon#about to read 5, iclass 40, count 0 2006.197.08:05:59.70#ibcon#read 5, iclass 40, count 0 2006.197.08:05:59.70#ibcon#about to read 6, iclass 40, count 0 2006.197.08:05:59.70#ibcon#read 6, iclass 40, count 0 2006.197.08:05:59.70#ibcon#end of sib2, iclass 40, count 0 2006.197.08:05:59.70#ibcon#*mode == 0, iclass 40, count 0 2006.197.08:05:59.70#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.197.08:05:59.70#ibcon#[26=FRQ=07,832.99\r\n] 2006.197.08:05:59.70#ibcon#*before write, iclass 40, count 0 2006.197.08:05:59.70#ibcon#enter sib2, iclass 40, count 0 2006.197.08:05:59.70#ibcon#flushed, iclass 40, count 0 2006.197.08:05:59.70#ibcon#about to write, iclass 40, count 0 2006.197.08:05:59.70#ibcon#wrote, iclass 40, count 0 2006.197.08:05:59.70#ibcon#about to read 3, iclass 40, count 0 2006.197.08:05:59.74#ibcon#read 3, iclass 40, count 0 2006.197.08:05:59.74#ibcon#about to read 4, iclass 40, count 0 2006.197.08:05:59.74#ibcon#read 4, iclass 40, count 0 2006.197.08:05:59.74#ibcon#about to read 5, iclass 40, count 0 2006.197.08:05:59.74#ibcon#read 5, iclass 40, count 0 2006.197.08:05:59.74#ibcon#about to read 6, iclass 40, count 0 2006.197.08:05:59.74#ibcon#read 6, iclass 40, count 0 2006.197.08:05:59.74#ibcon#end of sib2, iclass 40, count 0 2006.197.08:05:59.74#ibcon#*after write, iclass 40, count 0 2006.197.08:05:59.74#ibcon#*before return 0, iclass 40, count 0 2006.197.08:05:59.74#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.197.08:05:59.74#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.197.08:05:59.74#ibcon#about to clear, iclass 40 cls_cnt 0 2006.197.08:05:59.74#ibcon#cleared, iclass 40 cls_cnt 0 2006.197.08:05:59.74$vc4f8/va=7,6 2006.197.08:05:59.74#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.197.08:05:59.74#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.197.08:05:59.74#ibcon#ireg 11 cls_cnt 2 2006.197.08:05:59.74#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.197.08:05:59.80#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.197.08:05:59.80#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.197.08:05:59.80#ibcon#enter wrdev, iclass 4, count 2 2006.197.08:05:59.80#ibcon#first serial, iclass 4, count 2 2006.197.08:05:59.80#ibcon#enter sib2, iclass 4, count 2 2006.197.08:05:59.80#ibcon#flushed, iclass 4, count 2 2006.197.08:05:59.80#ibcon#about to write, iclass 4, count 2 2006.197.08:05:59.80#ibcon#wrote, iclass 4, count 2 2006.197.08:05:59.80#ibcon#about to read 3, iclass 4, count 2 2006.197.08:05:59.82#ibcon#read 3, iclass 4, count 2 2006.197.08:05:59.82#ibcon#about to read 4, iclass 4, count 2 2006.197.08:05:59.82#ibcon#read 4, iclass 4, count 2 2006.197.08:05:59.82#ibcon#about to read 5, iclass 4, count 2 2006.197.08:05:59.82#ibcon#read 5, iclass 4, count 2 2006.197.08:05:59.82#ibcon#about to read 6, iclass 4, count 2 2006.197.08:05:59.82#ibcon#read 6, iclass 4, count 2 2006.197.08:05:59.82#ibcon#end of sib2, iclass 4, count 2 2006.197.08:05:59.82#ibcon#*mode == 0, iclass 4, count 2 2006.197.08:05:59.82#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.197.08:05:59.82#ibcon#[25=AT07-06\r\n] 2006.197.08:05:59.82#ibcon#*before write, iclass 4, count 2 2006.197.08:05:59.82#ibcon#enter sib2, iclass 4, count 2 2006.197.08:05:59.82#ibcon#flushed, iclass 4, count 2 2006.197.08:05:59.82#ibcon#about to write, iclass 4, count 2 2006.197.08:05:59.82#ibcon#wrote, iclass 4, count 2 2006.197.08:05:59.82#ibcon#about to read 3, iclass 4, count 2 2006.197.08:05:59.85#ibcon#read 3, iclass 4, count 2 2006.197.08:05:59.85#ibcon#about to read 4, iclass 4, count 2 2006.197.08:05:59.85#ibcon#read 4, iclass 4, count 2 2006.197.08:05:59.85#ibcon#about to read 5, iclass 4, count 2 2006.197.08:05:59.85#ibcon#read 5, iclass 4, count 2 2006.197.08:05:59.85#ibcon#about to read 6, iclass 4, count 2 2006.197.08:05:59.85#ibcon#read 6, iclass 4, count 2 2006.197.08:05:59.85#ibcon#end of sib2, iclass 4, count 2 2006.197.08:05:59.85#ibcon#*after write, iclass 4, count 2 2006.197.08:05:59.85#ibcon#*before return 0, iclass 4, count 2 2006.197.08:05:59.85#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.197.08:05:59.85#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.197.08:05:59.85#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.197.08:05:59.85#ibcon#ireg 7 cls_cnt 0 2006.197.08:05:59.85#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.197.08:05:59.97#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.197.08:05:59.97#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.197.08:05:59.97#ibcon#enter wrdev, iclass 4, count 0 2006.197.08:05:59.97#ibcon#first serial, iclass 4, count 0 2006.197.08:05:59.97#ibcon#enter sib2, iclass 4, count 0 2006.197.08:05:59.97#ibcon#flushed, iclass 4, count 0 2006.197.08:05:59.97#ibcon#about to write, iclass 4, count 0 2006.197.08:05:59.97#ibcon#wrote, iclass 4, count 0 2006.197.08:05:59.97#ibcon#about to read 3, iclass 4, count 0 2006.197.08:05:59.99#ibcon#read 3, iclass 4, count 0 2006.197.08:05:59.99#ibcon#about to read 4, iclass 4, count 0 2006.197.08:05:59.99#ibcon#read 4, iclass 4, count 0 2006.197.08:05:59.99#ibcon#about to read 5, iclass 4, count 0 2006.197.08:05:59.99#ibcon#read 5, iclass 4, count 0 2006.197.08:05:59.99#ibcon#about to read 6, iclass 4, count 0 2006.197.08:05:59.99#ibcon#read 6, iclass 4, count 0 2006.197.08:05:59.99#ibcon#end of sib2, iclass 4, count 0 2006.197.08:05:59.99#ibcon#*mode == 0, iclass 4, count 0 2006.197.08:05:59.99#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.197.08:05:59.99#ibcon#[25=USB\r\n] 2006.197.08:05:59.99#ibcon#*before write, iclass 4, count 0 2006.197.08:05:59.99#ibcon#enter sib2, iclass 4, count 0 2006.197.08:05:59.99#ibcon#flushed, iclass 4, count 0 2006.197.08:05:59.99#ibcon#about to write, iclass 4, count 0 2006.197.08:05:59.99#ibcon#wrote, iclass 4, count 0 2006.197.08:05:59.99#ibcon#about to read 3, iclass 4, count 0 2006.197.08:06:00.02#ibcon#read 3, iclass 4, count 0 2006.197.08:06:00.02#ibcon#about to read 4, iclass 4, count 0 2006.197.08:06:00.02#ibcon#read 4, iclass 4, count 0 2006.197.08:06:00.02#ibcon#about to read 5, iclass 4, count 0 2006.197.08:06:00.02#ibcon#read 5, iclass 4, count 0 2006.197.08:06:00.02#ibcon#about to read 6, iclass 4, count 0 2006.197.08:06:00.02#ibcon#read 6, iclass 4, count 0 2006.197.08:06:00.02#ibcon#end of sib2, iclass 4, count 0 2006.197.08:06:00.02#ibcon#*after write, iclass 4, count 0 2006.197.08:06:00.02#ibcon#*before return 0, iclass 4, count 0 2006.197.08:06:00.02#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.197.08:06:00.02#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.197.08:06:00.02#ibcon#about to clear, iclass 4 cls_cnt 0 2006.197.08:06:00.02#ibcon#cleared, iclass 4 cls_cnt 0 2006.197.08:06:00.02$vc4f8/valo=8,852.99 2006.197.08:06:00.02#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.197.08:06:00.02#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.197.08:06:00.02#ibcon#ireg 17 cls_cnt 0 2006.197.08:06:00.02#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.197.08:06:00.02#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.197.08:06:00.02#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.197.08:06:00.02#ibcon#enter wrdev, iclass 6, count 0 2006.197.08:06:00.02#ibcon#first serial, iclass 6, count 0 2006.197.08:06:00.02#ibcon#enter sib2, iclass 6, count 0 2006.197.08:06:00.02#ibcon#flushed, iclass 6, count 0 2006.197.08:06:00.02#ibcon#about to write, iclass 6, count 0 2006.197.08:06:00.02#ibcon#wrote, iclass 6, count 0 2006.197.08:06:00.02#ibcon#about to read 3, iclass 6, count 0 2006.197.08:06:00.04#ibcon#read 3, iclass 6, count 0 2006.197.08:06:00.04#ibcon#about to read 4, iclass 6, count 0 2006.197.08:06:00.04#ibcon#read 4, iclass 6, count 0 2006.197.08:06:00.04#ibcon#about to read 5, iclass 6, count 0 2006.197.08:06:00.04#ibcon#read 5, iclass 6, count 0 2006.197.08:06:00.04#ibcon#about to read 6, iclass 6, count 0 2006.197.08:06:00.04#ibcon#read 6, iclass 6, count 0 2006.197.08:06:00.04#ibcon#end of sib2, iclass 6, count 0 2006.197.08:06:00.04#ibcon#*mode == 0, iclass 6, count 0 2006.197.08:06:00.04#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.197.08:06:00.04#ibcon#[26=FRQ=08,852.99\r\n] 2006.197.08:06:00.04#ibcon#*before write, iclass 6, count 0 2006.197.08:06:00.04#ibcon#enter sib2, iclass 6, count 0 2006.197.08:06:00.04#ibcon#flushed, iclass 6, count 0 2006.197.08:06:00.04#ibcon#about to write, iclass 6, count 0 2006.197.08:06:00.04#ibcon#wrote, iclass 6, count 0 2006.197.08:06:00.04#ibcon#about to read 3, iclass 6, count 0 2006.197.08:06:00.08#ibcon#read 3, iclass 6, count 0 2006.197.08:06:00.08#ibcon#about to read 4, iclass 6, count 0 2006.197.08:06:00.08#ibcon#read 4, iclass 6, count 0 2006.197.08:06:00.08#ibcon#about to read 5, iclass 6, count 0 2006.197.08:06:00.08#ibcon#read 5, iclass 6, count 0 2006.197.08:06:00.08#ibcon#about to read 6, iclass 6, count 0 2006.197.08:06:00.08#ibcon#read 6, iclass 6, count 0 2006.197.08:06:00.08#ibcon#end of sib2, iclass 6, count 0 2006.197.08:06:00.08#ibcon#*after write, iclass 6, count 0 2006.197.08:06:00.08#ibcon#*before return 0, iclass 6, count 0 2006.197.08:06:00.08#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.197.08:06:00.08#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.197.08:06:00.08#ibcon#about to clear, iclass 6 cls_cnt 0 2006.197.08:06:00.08#ibcon#cleared, iclass 6 cls_cnt 0 2006.197.08:06:00.08$vc4f8/va=8,7 2006.197.08:06:00.08#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.197.08:06:00.08#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.197.08:06:00.08#ibcon#ireg 11 cls_cnt 2 2006.197.08:06:00.08#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.197.08:06:00.14#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.197.08:06:00.14#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.197.08:06:00.14#ibcon#enter wrdev, iclass 10, count 2 2006.197.08:06:00.14#ibcon#first serial, iclass 10, count 2 2006.197.08:06:00.14#ibcon#enter sib2, iclass 10, count 2 2006.197.08:06:00.14#ibcon#flushed, iclass 10, count 2 2006.197.08:06:00.14#ibcon#about to write, iclass 10, count 2 2006.197.08:06:00.14#ibcon#wrote, iclass 10, count 2 2006.197.08:06:00.14#ibcon#about to read 3, iclass 10, count 2 2006.197.08:06:00.16#ibcon#read 3, iclass 10, count 2 2006.197.08:06:00.16#ibcon#about to read 4, iclass 10, count 2 2006.197.08:06:00.16#ibcon#read 4, iclass 10, count 2 2006.197.08:06:00.16#ibcon#about to read 5, iclass 10, count 2 2006.197.08:06:00.16#ibcon#read 5, iclass 10, count 2 2006.197.08:06:00.16#ibcon#about to read 6, iclass 10, count 2 2006.197.08:06:00.16#ibcon#read 6, iclass 10, count 2 2006.197.08:06:00.16#ibcon#end of sib2, iclass 10, count 2 2006.197.08:06:00.16#ibcon#*mode == 0, iclass 10, count 2 2006.197.08:06:00.16#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.197.08:06:00.16#ibcon#[25=AT08-07\r\n] 2006.197.08:06:00.16#ibcon#*before write, iclass 10, count 2 2006.197.08:06:00.16#ibcon#enter sib2, iclass 10, count 2 2006.197.08:06:00.16#ibcon#flushed, iclass 10, count 2 2006.197.08:06:00.16#ibcon#about to write, iclass 10, count 2 2006.197.08:06:00.16#ibcon#wrote, iclass 10, count 2 2006.197.08:06:00.16#ibcon#about to read 3, iclass 10, count 2 2006.197.08:06:00.19#ibcon#read 3, iclass 10, count 2 2006.197.08:06:00.19#ibcon#about to read 4, iclass 10, count 2 2006.197.08:06:00.19#ibcon#read 4, iclass 10, count 2 2006.197.08:06:00.19#ibcon#about to read 5, iclass 10, count 2 2006.197.08:06:00.19#ibcon#read 5, iclass 10, count 2 2006.197.08:06:00.19#ibcon#about to read 6, iclass 10, count 2 2006.197.08:06:00.19#ibcon#read 6, iclass 10, count 2 2006.197.08:06:00.19#ibcon#end of sib2, iclass 10, count 2 2006.197.08:06:00.19#ibcon#*after write, iclass 10, count 2 2006.197.08:06:00.19#ibcon#*before return 0, iclass 10, count 2 2006.197.08:06:00.19#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.197.08:06:00.19#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.197.08:06:00.19#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.197.08:06:00.19#ibcon#ireg 7 cls_cnt 0 2006.197.08:06:00.19#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.197.08:06:00.31#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.197.08:06:00.31#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.197.08:06:00.31#ibcon#enter wrdev, iclass 10, count 0 2006.197.08:06:00.31#ibcon#first serial, iclass 10, count 0 2006.197.08:06:00.31#ibcon#enter sib2, iclass 10, count 0 2006.197.08:06:00.31#ibcon#flushed, iclass 10, count 0 2006.197.08:06:00.31#ibcon#about to write, iclass 10, count 0 2006.197.08:06:00.31#ibcon#wrote, iclass 10, count 0 2006.197.08:06:00.31#ibcon#about to read 3, iclass 10, count 0 2006.197.08:06:00.33#ibcon#read 3, iclass 10, count 0 2006.197.08:06:00.33#ibcon#about to read 4, iclass 10, count 0 2006.197.08:06:00.33#ibcon#read 4, iclass 10, count 0 2006.197.08:06:00.33#ibcon#about to read 5, iclass 10, count 0 2006.197.08:06:00.33#ibcon#read 5, iclass 10, count 0 2006.197.08:06:00.33#ibcon#about to read 6, iclass 10, count 0 2006.197.08:06:00.33#ibcon#read 6, iclass 10, count 0 2006.197.08:06:00.33#ibcon#end of sib2, iclass 10, count 0 2006.197.08:06:00.33#ibcon#*mode == 0, iclass 10, count 0 2006.197.08:06:00.33#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.197.08:06:00.33#ibcon#[25=USB\r\n] 2006.197.08:06:00.33#ibcon#*before write, iclass 10, count 0 2006.197.08:06:00.33#ibcon#enter sib2, iclass 10, count 0 2006.197.08:06:00.33#ibcon#flushed, iclass 10, count 0 2006.197.08:06:00.33#ibcon#about to write, iclass 10, count 0 2006.197.08:06:00.33#ibcon#wrote, iclass 10, count 0 2006.197.08:06:00.33#ibcon#about to read 3, iclass 10, count 0 2006.197.08:06:00.36#ibcon#read 3, iclass 10, count 0 2006.197.08:06:00.36#ibcon#about to read 4, iclass 10, count 0 2006.197.08:06:00.36#ibcon#read 4, iclass 10, count 0 2006.197.08:06:00.36#ibcon#about to read 5, iclass 10, count 0 2006.197.08:06:00.36#ibcon#read 5, iclass 10, count 0 2006.197.08:06:00.36#ibcon#about to read 6, iclass 10, count 0 2006.197.08:06:00.36#ibcon#read 6, iclass 10, count 0 2006.197.08:06:00.36#ibcon#end of sib2, iclass 10, count 0 2006.197.08:06:00.36#ibcon#*after write, iclass 10, count 0 2006.197.08:06:00.36#ibcon#*before return 0, iclass 10, count 0 2006.197.08:06:00.36#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.197.08:06:00.36#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.197.08:06:00.36#ibcon#about to clear, iclass 10 cls_cnt 0 2006.197.08:06:00.36#ibcon#cleared, iclass 10 cls_cnt 0 2006.197.08:06:00.36$vc4f8/vblo=1,632.99 2006.197.08:06:00.36#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.197.08:06:00.36#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.197.08:06:00.36#ibcon#ireg 17 cls_cnt 0 2006.197.08:06:00.36#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.197.08:06:00.36#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.197.08:06:00.36#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.197.08:06:00.36#ibcon#enter wrdev, iclass 12, count 0 2006.197.08:06:00.36#ibcon#first serial, iclass 12, count 0 2006.197.08:06:00.36#ibcon#enter sib2, iclass 12, count 0 2006.197.08:06:00.36#ibcon#flushed, iclass 12, count 0 2006.197.08:06:00.36#ibcon#about to write, iclass 12, count 0 2006.197.08:06:00.36#ibcon#wrote, iclass 12, count 0 2006.197.08:06:00.36#ibcon#about to read 3, iclass 12, count 0 2006.197.08:06:00.38#ibcon#read 3, iclass 12, count 0 2006.197.08:06:00.38#ibcon#about to read 4, iclass 12, count 0 2006.197.08:06:00.38#ibcon#read 4, iclass 12, count 0 2006.197.08:06:00.38#ibcon#about to read 5, iclass 12, count 0 2006.197.08:06:00.38#ibcon#read 5, iclass 12, count 0 2006.197.08:06:00.38#ibcon#about to read 6, iclass 12, count 0 2006.197.08:06:00.38#ibcon#read 6, iclass 12, count 0 2006.197.08:06:00.38#ibcon#end of sib2, iclass 12, count 0 2006.197.08:06:00.38#ibcon#*mode == 0, iclass 12, count 0 2006.197.08:06:00.38#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.197.08:06:00.38#ibcon#[28=FRQ=01,632.99\r\n] 2006.197.08:06:00.38#ibcon#*before write, iclass 12, count 0 2006.197.08:06:00.38#ibcon#enter sib2, iclass 12, count 0 2006.197.08:06:00.38#ibcon#flushed, iclass 12, count 0 2006.197.08:06:00.38#ibcon#about to write, iclass 12, count 0 2006.197.08:06:00.38#ibcon#wrote, iclass 12, count 0 2006.197.08:06:00.38#ibcon#about to read 3, iclass 12, count 0 2006.197.08:06:00.42#ibcon#read 3, iclass 12, count 0 2006.197.08:06:00.42#ibcon#about to read 4, iclass 12, count 0 2006.197.08:06:00.42#ibcon#read 4, iclass 12, count 0 2006.197.08:06:00.42#ibcon#about to read 5, iclass 12, count 0 2006.197.08:06:00.42#ibcon#read 5, iclass 12, count 0 2006.197.08:06:00.42#ibcon#about to read 6, iclass 12, count 0 2006.197.08:06:00.42#ibcon#read 6, iclass 12, count 0 2006.197.08:06:00.42#ibcon#end of sib2, iclass 12, count 0 2006.197.08:06:00.42#ibcon#*after write, iclass 12, count 0 2006.197.08:06:00.42#ibcon#*before return 0, iclass 12, count 0 2006.197.08:06:00.42#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.197.08:06:00.42#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.197.08:06:00.42#ibcon#about to clear, iclass 12 cls_cnt 0 2006.197.08:06:00.42#ibcon#cleared, iclass 12 cls_cnt 0 2006.197.08:06:00.42$vc4f8/vb=1,4 2006.197.08:06:00.42#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.197.08:06:00.42#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.197.08:06:00.42#ibcon#ireg 11 cls_cnt 2 2006.197.08:06:00.42#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.197.08:06:00.42#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.197.08:06:00.42#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.197.08:06:00.42#ibcon#enter wrdev, iclass 14, count 2 2006.197.08:06:00.42#ibcon#first serial, iclass 14, count 2 2006.197.08:06:00.42#ibcon#enter sib2, iclass 14, count 2 2006.197.08:06:00.42#ibcon#flushed, iclass 14, count 2 2006.197.08:06:00.42#ibcon#about to write, iclass 14, count 2 2006.197.08:06:00.42#ibcon#wrote, iclass 14, count 2 2006.197.08:06:00.42#ibcon#about to read 3, iclass 14, count 2 2006.197.08:06:00.44#ibcon#read 3, iclass 14, count 2 2006.197.08:06:00.44#ibcon#about to read 4, iclass 14, count 2 2006.197.08:06:00.44#ibcon#read 4, iclass 14, count 2 2006.197.08:06:00.44#ibcon#about to read 5, iclass 14, count 2 2006.197.08:06:00.44#ibcon#read 5, iclass 14, count 2 2006.197.08:06:00.44#ibcon#about to read 6, iclass 14, count 2 2006.197.08:06:00.44#ibcon#read 6, iclass 14, count 2 2006.197.08:06:00.44#ibcon#end of sib2, iclass 14, count 2 2006.197.08:06:00.44#ibcon#*mode == 0, iclass 14, count 2 2006.197.08:06:00.44#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.197.08:06:00.44#ibcon#[27=AT01-04\r\n] 2006.197.08:06:00.44#ibcon#*before write, iclass 14, count 2 2006.197.08:06:00.44#ibcon#enter sib2, iclass 14, count 2 2006.197.08:06:00.44#ibcon#flushed, iclass 14, count 2 2006.197.08:06:00.44#ibcon#about to write, iclass 14, count 2 2006.197.08:06:00.44#ibcon#wrote, iclass 14, count 2 2006.197.08:06:00.44#ibcon#about to read 3, iclass 14, count 2 2006.197.08:06:00.47#ibcon#read 3, iclass 14, count 2 2006.197.08:06:00.47#ibcon#about to read 4, iclass 14, count 2 2006.197.08:06:00.47#ibcon#read 4, iclass 14, count 2 2006.197.08:06:00.47#ibcon#about to read 5, iclass 14, count 2 2006.197.08:06:00.47#ibcon#read 5, iclass 14, count 2 2006.197.08:06:00.47#ibcon#about to read 6, iclass 14, count 2 2006.197.08:06:00.47#ibcon#read 6, iclass 14, count 2 2006.197.08:06:00.47#ibcon#end of sib2, iclass 14, count 2 2006.197.08:06:00.47#ibcon#*after write, iclass 14, count 2 2006.197.08:06:00.47#ibcon#*before return 0, iclass 14, count 2 2006.197.08:06:00.47#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.197.08:06:00.47#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.197.08:06:00.47#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.197.08:06:00.47#ibcon#ireg 7 cls_cnt 0 2006.197.08:06:00.47#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.197.08:06:00.59#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.197.08:06:00.59#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.197.08:06:00.59#ibcon#enter wrdev, iclass 14, count 0 2006.197.08:06:00.59#ibcon#first serial, iclass 14, count 0 2006.197.08:06:00.59#ibcon#enter sib2, iclass 14, count 0 2006.197.08:06:00.59#ibcon#flushed, iclass 14, count 0 2006.197.08:06:00.59#ibcon#about to write, iclass 14, count 0 2006.197.08:06:00.59#ibcon#wrote, iclass 14, count 0 2006.197.08:06:00.59#ibcon#about to read 3, iclass 14, count 0 2006.197.08:06:00.61#ibcon#read 3, iclass 14, count 0 2006.197.08:06:00.61#ibcon#about to read 4, iclass 14, count 0 2006.197.08:06:00.61#ibcon#read 4, iclass 14, count 0 2006.197.08:06:00.61#ibcon#about to read 5, iclass 14, count 0 2006.197.08:06:00.61#ibcon#read 5, iclass 14, count 0 2006.197.08:06:00.61#ibcon#about to read 6, iclass 14, count 0 2006.197.08:06:00.61#ibcon#read 6, iclass 14, count 0 2006.197.08:06:00.61#ibcon#end of sib2, iclass 14, count 0 2006.197.08:06:00.61#ibcon#*mode == 0, iclass 14, count 0 2006.197.08:06:00.61#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.197.08:06:00.61#ibcon#[27=USB\r\n] 2006.197.08:06:00.61#ibcon#*before write, iclass 14, count 0 2006.197.08:06:00.61#ibcon#enter sib2, iclass 14, count 0 2006.197.08:06:00.61#ibcon#flushed, iclass 14, count 0 2006.197.08:06:00.61#ibcon#about to write, iclass 14, count 0 2006.197.08:06:00.61#ibcon#wrote, iclass 14, count 0 2006.197.08:06:00.61#ibcon#about to read 3, iclass 14, count 0 2006.197.08:06:00.64#ibcon#read 3, iclass 14, count 0 2006.197.08:06:00.64#ibcon#about to read 4, iclass 14, count 0 2006.197.08:06:00.64#ibcon#read 4, iclass 14, count 0 2006.197.08:06:00.64#ibcon#about to read 5, iclass 14, count 0 2006.197.08:06:00.64#ibcon#read 5, iclass 14, count 0 2006.197.08:06:00.64#ibcon#about to read 6, iclass 14, count 0 2006.197.08:06:00.64#ibcon#read 6, iclass 14, count 0 2006.197.08:06:00.64#ibcon#end of sib2, iclass 14, count 0 2006.197.08:06:00.64#ibcon#*after write, iclass 14, count 0 2006.197.08:06:00.64#ibcon#*before return 0, iclass 14, count 0 2006.197.08:06:00.64#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.197.08:06:00.64#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.197.08:06:00.64#ibcon#about to clear, iclass 14 cls_cnt 0 2006.197.08:06:00.64#ibcon#cleared, iclass 14 cls_cnt 0 2006.197.08:06:00.64$vc4f8/vblo=2,640.99 2006.197.08:06:00.64#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.197.08:06:00.64#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.197.08:06:00.64#ibcon#ireg 17 cls_cnt 0 2006.197.08:06:00.64#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.197.08:06:00.64#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.197.08:06:00.64#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.197.08:06:00.64#ibcon#enter wrdev, iclass 16, count 0 2006.197.08:06:00.64#ibcon#first serial, iclass 16, count 0 2006.197.08:06:00.64#ibcon#enter sib2, iclass 16, count 0 2006.197.08:06:00.64#ibcon#flushed, iclass 16, count 0 2006.197.08:06:00.64#ibcon#about to write, iclass 16, count 0 2006.197.08:06:00.64#ibcon#wrote, iclass 16, count 0 2006.197.08:06:00.64#ibcon#about to read 3, iclass 16, count 0 2006.197.08:06:00.66#ibcon#read 3, iclass 16, count 0 2006.197.08:06:00.66#ibcon#about to read 4, iclass 16, count 0 2006.197.08:06:00.66#ibcon#read 4, iclass 16, count 0 2006.197.08:06:00.66#ibcon#about to read 5, iclass 16, count 0 2006.197.08:06:00.66#ibcon#read 5, iclass 16, count 0 2006.197.08:06:00.66#ibcon#about to read 6, iclass 16, count 0 2006.197.08:06:00.66#ibcon#read 6, iclass 16, count 0 2006.197.08:06:00.66#ibcon#end of sib2, iclass 16, count 0 2006.197.08:06:00.66#ibcon#*mode == 0, iclass 16, count 0 2006.197.08:06:00.66#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.197.08:06:00.66#ibcon#[28=FRQ=02,640.99\r\n] 2006.197.08:06:00.66#ibcon#*before write, iclass 16, count 0 2006.197.08:06:00.66#ibcon#enter sib2, iclass 16, count 0 2006.197.08:06:00.66#ibcon#flushed, iclass 16, count 0 2006.197.08:06:00.66#ibcon#about to write, iclass 16, count 0 2006.197.08:06:00.66#ibcon#wrote, iclass 16, count 0 2006.197.08:06:00.66#ibcon#about to read 3, iclass 16, count 0 2006.197.08:06:00.70#ibcon#read 3, iclass 16, count 0 2006.197.08:06:00.70#ibcon#about to read 4, iclass 16, count 0 2006.197.08:06:00.70#ibcon#read 4, iclass 16, count 0 2006.197.08:06:00.70#ibcon#about to read 5, iclass 16, count 0 2006.197.08:06:00.70#ibcon#read 5, iclass 16, count 0 2006.197.08:06:00.70#ibcon#about to read 6, iclass 16, count 0 2006.197.08:06:00.70#ibcon#read 6, iclass 16, count 0 2006.197.08:06:00.70#ibcon#end of sib2, iclass 16, count 0 2006.197.08:06:00.70#ibcon#*after write, iclass 16, count 0 2006.197.08:06:00.70#ibcon#*before return 0, iclass 16, count 0 2006.197.08:06:00.70#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.197.08:06:00.70#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.197.08:06:00.70#ibcon#about to clear, iclass 16 cls_cnt 0 2006.197.08:06:00.70#ibcon#cleared, iclass 16 cls_cnt 0 2006.197.08:06:00.70$vc4f8/vb=2,4 2006.197.08:06:00.70#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.197.08:06:00.70#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.197.08:06:00.70#ibcon#ireg 11 cls_cnt 2 2006.197.08:06:00.70#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.197.08:06:00.76#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.197.08:06:00.76#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.197.08:06:00.76#ibcon#enter wrdev, iclass 18, count 2 2006.197.08:06:00.76#ibcon#first serial, iclass 18, count 2 2006.197.08:06:00.76#ibcon#enter sib2, iclass 18, count 2 2006.197.08:06:00.76#ibcon#flushed, iclass 18, count 2 2006.197.08:06:00.76#ibcon#about to write, iclass 18, count 2 2006.197.08:06:00.76#ibcon#wrote, iclass 18, count 2 2006.197.08:06:00.76#ibcon#about to read 3, iclass 18, count 2 2006.197.08:06:00.78#ibcon#read 3, iclass 18, count 2 2006.197.08:06:00.78#ibcon#about to read 4, iclass 18, count 2 2006.197.08:06:00.78#ibcon#read 4, iclass 18, count 2 2006.197.08:06:00.78#ibcon#about to read 5, iclass 18, count 2 2006.197.08:06:00.78#ibcon#read 5, iclass 18, count 2 2006.197.08:06:00.78#ibcon#about to read 6, iclass 18, count 2 2006.197.08:06:00.78#ibcon#read 6, iclass 18, count 2 2006.197.08:06:00.78#ibcon#end of sib2, iclass 18, count 2 2006.197.08:06:00.78#ibcon#*mode == 0, iclass 18, count 2 2006.197.08:06:00.78#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.197.08:06:00.78#ibcon#[27=AT02-04\r\n] 2006.197.08:06:00.78#ibcon#*before write, iclass 18, count 2 2006.197.08:06:00.78#ibcon#enter sib2, iclass 18, count 2 2006.197.08:06:00.78#ibcon#flushed, iclass 18, count 2 2006.197.08:06:00.78#ibcon#about to write, iclass 18, count 2 2006.197.08:06:00.78#ibcon#wrote, iclass 18, count 2 2006.197.08:06:00.78#ibcon#about to read 3, iclass 18, count 2 2006.197.08:06:00.81#ibcon#read 3, iclass 18, count 2 2006.197.08:06:00.81#ibcon#about to read 4, iclass 18, count 2 2006.197.08:06:00.81#ibcon#read 4, iclass 18, count 2 2006.197.08:06:00.81#ibcon#about to read 5, iclass 18, count 2 2006.197.08:06:00.81#ibcon#read 5, iclass 18, count 2 2006.197.08:06:00.81#ibcon#about to read 6, iclass 18, count 2 2006.197.08:06:00.81#ibcon#read 6, iclass 18, count 2 2006.197.08:06:00.81#ibcon#end of sib2, iclass 18, count 2 2006.197.08:06:00.81#ibcon#*after write, iclass 18, count 2 2006.197.08:06:00.81#ibcon#*before return 0, iclass 18, count 2 2006.197.08:06:00.81#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.197.08:06:00.81#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.197.08:06:00.81#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.197.08:06:00.81#ibcon#ireg 7 cls_cnt 0 2006.197.08:06:00.81#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.197.08:06:00.93#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.197.08:06:00.93#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.197.08:06:00.93#ibcon#enter wrdev, iclass 18, count 0 2006.197.08:06:00.93#ibcon#first serial, iclass 18, count 0 2006.197.08:06:00.93#ibcon#enter sib2, iclass 18, count 0 2006.197.08:06:00.93#ibcon#flushed, iclass 18, count 0 2006.197.08:06:00.93#ibcon#about to write, iclass 18, count 0 2006.197.08:06:00.93#ibcon#wrote, iclass 18, count 0 2006.197.08:06:00.93#ibcon#about to read 3, iclass 18, count 0 2006.197.08:06:00.95#ibcon#read 3, iclass 18, count 0 2006.197.08:06:00.95#ibcon#about to read 4, iclass 18, count 0 2006.197.08:06:00.95#ibcon#read 4, iclass 18, count 0 2006.197.08:06:00.95#ibcon#about to read 5, iclass 18, count 0 2006.197.08:06:00.95#ibcon#read 5, iclass 18, count 0 2006.197.08:06:00.95#ibcon#about to read 6, iclass 18, count 0 2006.197.08:06:00.95#ibcon#read 6, iclass 18, count 0 2006.197.08:06:00.95#ibcon#end of sib2, iclass 18, count 0 2006.197.08:06:00.95#ibcon#*mode == 0, iclass 18, count 0 2006.197.08:06:00.95#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.197.08:06:00.95#ibcon#[27=USB\r\n] 2006.197.08:06:00.95#ibcon#*before write, iclass 18, count 0 2006.197.08:06:00.95#ibcon#enter sib2, iclass 18, count 0 2006.197.08:06:00.95#ibcon#flushed, iclass 18, count 0 2006.197.08:06:00.95#ibcon#about to write, iclass 18, count 0 2006.197.08:06:00.95#ibcon#wrote, iclass 18, count 0 2006.197.08:06:00.95#ibcon#about to read 3, iclass 18, count 0 2006.197.08:06:00.98#ibcon#read 3, iclass 18, count 0 2006.197.08:06:00.98#ibcon#about to read 4, iclass 18, count 0 2006.197.08:06:00.98#ibcon#read 4, iclass 18, count 0 2006.197.08:06:00.98#ibcon#about to read 5, iclass 18, count 0 2006.197.08:06:00.98#ibcon#read 5, iclass 18, count 0 2006.197.08:06:00.98#ibcon#about to read 6, iclass 18, count 0 2006.197.08:06:00.98#ibcon#read 6, iclass 18, count 0 2006.197.08:06:00.98#ibcon#end of sib2, iclass 18, count 0 2006.197.08:06:00.98#ibcon#*after write, iclass 18, count 0 2006.197.08:06:00.98#ibcon#*before return 0, iclass 18, count 0 2006.197.08:06:00.98#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.197.08:06:00.98#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.197.08:06:00.98#ibcon#about to clear, iclass 18 cls_cnt 0 2006.197.08:06:00.98#ibcon#cleared, iclass 18 cls_cnt 0 2006.197.08:06:00.98$vc4f8/vblo=3,656.99 2006.197.08:06:00.98#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.197.08:06:00.98#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.197.08:06:00.98#ibcon#ireg 17 cls_cnt 0 2006.197.08:06:00.98#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.197.08:06:00.98#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.197.08:06:00.98#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.197.08:06:00.98#ibcon#enter wrdev, iclass 20, count 0 2006.197.08:06:00.98#ibcon#first serial, iclass 20, count 0 2006.197.08:06:00.98#ibcon#enter sib2, iclass 20, count 0 2006.197.08:06:00.98#ibcon#flushed, iclass 20, count 0 2006.197.08:06:00.98#ibcon#about to write, iclass 20, count 0 2006.197.08:06:00.98#ibcon#wrote, iclass 20, count 0 2006.197.08:06:00.98#ibcon#about to read 3, iclass 20, count 0 2006.197.08:06:01.00#ibcon#read 3, iclass 20, count 0 2006.197.08:06:01.00#ibcon#about to read 4, iclass 20, count 0 2006.197.08:06:01.00#ibcon#read 4, iclass 20, count 0 2006.197.08:06:01.00#ibcon#about to read 5, iclass 20, count 0 2006.197.08:06:01.00#ibcon#read 5, iclass 20, count 0 2006.197.08:06:01.00#ibcon#about to read 6, iclass 20, count 0 2006.197.08:06:01.00#ibcon#read 6, iclass 20, count 0 2006.197.08:06:01.00#ibcon#end of sib2, iclass 20, count 0 2006.197.08:06:01.00#ibcon#*mode == 0, iclass 20, count 0 2006.197.08:06:01.00#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.197.08:06:01.00#ibcon#[28=FRQ=03,656.99\r\n] 2006.197.08:06:01.00#ibcon#*before write, iclass 20, count 0 2006.197.08:06:01.00#ibcon#enter sib2, iclass 20, count 0 2006.197.08:06:01.00#ibcon#flushed, iclass 20, count 0 2006.197.08:06:01.00#ibcon#about to write, iclass 20, count 0 2006.197.08:06:01.00#ibcon#wrote, iclass 20, count 0 2006.197.08:06:01.00#ibcon#about to read 3, iclass 20, count 0 2006.197.08:06:01.04#ibcon#read 3, iclass 20, count 0 2006.197.08:06:01.04#ibcon#about to read 4, iclass 20, count 0 2006.197.08:06:01.04#ibcon#read 4, iclass 20, count 0 2006.197.08:06:01.04#ibcon#about to read 5, iclass 20, count 0 2006.197.08:06:01.04#ibcon#read 5, iclass 20, count 0 2006.197.08:06:01.04#ibcon#about to read 6, iclass 20, count 0 2006.197.08:06:01.04#ibcon#read 6, iclass 20, count 0 2006.197.08:06:01.04#ibcon#end of sib2, iclass 20, count 0 2006.197.08:06:01.04#ibcon#*after write, iclass 20, count 0 2006.197.08:06:01.04#ibcon#*before return 0, iclass 20, count 0 2006.197.08:06:01.04#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.197.08:06:01.04#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.197.08:06:01.04#ibcon#about to clear, iclass 20 cls_cnt 0 2006.197.08:06:01.04#ibcon#cleared, iclass 20 cls_cnt 0 2006.197.08:06:01.04$vc4f8/vb=3,4 2006.197.08:06:01.04#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.197.08:06:01.04#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.197.08:06:01.04#ibcon#ireg 11 cls_cnt 2 2006.197.08:06:01.04#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.197.08:06:01.10#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.197.08:06:01.10#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.197.08:06:01.10#ibcon#enter wrdev, iclass 22, count 2 2006.197.08:06:01.10#ibcon#first serial, iclass 22, count 2 2006.197.08:06:01.10#ibcon#enter sib2, iclass 22, count 2 2006.197.08:06:01.10#ibcon#flushed, iclass 22, count 2 2006.197.08:06:01.10#ibcon#about to write, iclass 22, count 2 2006.197.08:06:01.10#ibcon#wrote, iclass 22, count 2 2006.197.08:06:01.10#ibcon#about to read 3, iclass 22, count 2 2006.197.08:06:01.12#ibcon#read 3, iclass 22, count 2 2006.197.08:06:01.12#ibcon#about to read 4, iclass 22, count 2 2006.197.08:06:01.12#ibcon#read 4, iclass 22, count 2 2006.197.08:06:01.12#ibcon#about to read 5, iclass 22, count 2 2006.197.08:06:01.12#ibcon#read 5, iclass 22, count 2 2006.197.08:06:01.12#ibcon#about to read 6, iclass 22, count 2 2006.197.08:06:01.12#ibcon#read 6, iclass 22, count 2 2006.197.08:06:01.12#ibcon#end of sib2, iclass 22, count 2 2006.197.08:06:01.12#ibcon#*mode == 0, iclass 22, count 2 2006.197.08:06:01.12#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.197.08:06:01.12#ibcon#[27=AT03-04\r\n] 2006.197.08:06:01.12#ibcon#*before write, iclass 22, count 2 2006.197.08:06:01.12#ibcon#enter sib2, iclass 22, count 2 2006.197.08:06:01.12#ibcon#flushed, iclass 22, count 2 2006.197.08:06:01.12#ibcon#about to write, iclass 22, count 2 2006.197.08:06:01.12#ibcon#wrote, iclass 22, count 2 2006.197.08:06:01.12#ibcon#about to read 3, iclass 22, count 2 2006.197.08:06:01.15#ibcon#read 3, iclass 22, count 2 2006.197.08:06:01.15#ibcon#about to read 4, iclass 22, count 2 2006.197.08:06:01.15#ibcon#read 4, iclass 22, count 2 2006.197.08:06:01.15#ibcon#about to read 5, iclass 22, count 2 2006.197.08:06:01.15#ibcon#read 5, iclass 22, count 2 2006.197.08:06:01.15#ibcon#about to read 6, iclass 22, count 2 2006.197.08:06:01.15#ibcon#read 6, iclass 22, count 2 2006.197.08:06:01.15#ibcon#end of sib2, iclass 22, count 2 2006.197.08:06:01.15#ibcon#*after write, iclass 22, count 2 2006.197.08:06:01.15#ibcon#*before return 0, iclass 22, count 2 2006.197.08:06:01.15#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.197.08:06:01.15#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.197.08:06:01.15#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.197.08:06:01.15#ibcon#ireg 7 cls_cnt 0 2006.197.08:06:01.15#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.197.08:06:01.27#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.197.08:06:01.27#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.197.08:06:01.27#ibcon#enter wrdev, iclass 22, count 0 2006.197.08:06:01.27#ibcon#first serial, iclass 22, count 0 2006.197.08:06:01.27#ibcon#enter sib2, iclass 22, count 0 2006.197.08:06:01.27#ibcon#flushed, iclass 22, count 0 2006.197.08:06:01.27#ibcon#about to write, iclass 22, count 0 2006.197.08:06:01.27#ibcon#wrote, iclass 22, count 0 2006.197.08:06:01.27#ibcon#about to read 3, iclass 22, count 0 2006.197.08:06:01.29#ibcon#read 3, iclass 22, count 0 2006.197.08:06:01.29#ibcon#about to read 4, iclass 22, count 0 2006.197.08:06:01.29#ibcon#read 4, iclass 22, count 0 2006.197.08:06:01.29#ibcon#about to read 5, iclass 22, count 0 2006.197.08:06:01.29#ibcon#read 5, iclass 22, count 0 2006.197.08:06:01.29#ibcon#about to read 6, iclass 22, count 0 2006.197.08:06:01.29#ibcon#read 6, iclass 22, count 0 2006.197.08:06:01.29#ibcon#end of sib2, iclass 22, count 0 2006.197.08:06:01.29#ibcon#*mode == 0, iclass 22, count 0 2006.197.08:06:01.29#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.197.08:06:01.29#ibcon#[27=USB\r\n] 2006.197.08:06:01.29#ibcon#*before write, iclass 22, count 0 2006.197.08:06:01.29#ibcon#enter sib2, iclass 22, count 0 2006.197.08:06:01.29#ibcon#flushed, iclass 22, count 0 2006.197.08:06:01.29#ibcon#about to write, iclass 22, count 0 2006.197.08:06:01.29#ibcon#wrote, iclass 22, count 0 2006.197.08:06:01.29#ibcon#about to read 3, iclass 22, count 0 2006.197.08:06:01.32#ibcon#read 3, iclass 22, count 0 2006.197.08:06:01.32#ibcon#about to read 4, iclass 22, count 0 2006.197.08:06:01.32#ibcon#read 4, iclass 22, count 0 2006.197.08:06:01.32#ibcon#about to read 5, iclass 22, count 0 2006.197.08:06:01.32#ibcon#read 5, iclass 22, count 0 2006.197.08:06:01.32#ibcon#about to read 6, iclass 22, count 0 2006.197.08:06:01.32#ibcon#read 6, iclass 22, count 0 2006.197.08:06:01.32#ibcon#end of sib2, iclass 22, count 0 2006.197.08:06:01.32#ibcon#*after write, iclass 22, count 0 2006.197.08:06:01.32#ibcon#*before return 0, iclass 22, count 0 2006.197.08:06:01.32#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.197.08:06:01.32#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.197.08:06:01.32#ibcon#about to clear, iclass 22 cls_cnt 0 2006.197.08:06:01.32#ibcon#cleared, iclass 22 cls_cnt 0 2006.197.08:06:01.32$vc4f8/vblo=4,712.99 2006.197.08:06:01.32#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.197.08:06:01.32#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.197.08:06:01.32#ibcon#ireg 17 cls_cnt 0 2006.197.08:06:01.32#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.197.08:06:01.32#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.197.08:06:01.32#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.197.08:06:01.32#ibcon#enter wrdev, iclass 24, count 0 2006.197.08:06:01.32#ibcon#first serial, iclass 24, count 0 2006.197.08:06:01.32#ibcon#enter sib2, iclass 24, count 0 2006.197.08:06:01.32#ibcon#flushed, iclass 24, count 0 2006.197.08:06:01.32#ibcon#about to write, iclass 24, count 0 2006.197.08:06:01.32#ibcon#wrote, iclass 24, count 0 2006.197.08:06:01.32#ibcon#about to read 3, iclass 24, count 0 2006.197.08:06:01.34#ibcon#read 3, iclass 24, count 0 2006.197.08:06:01.34#ibcon#about to read 4, iclass 24, count 0 2006.197.08:06:01.34#ibcon#read 4, iclass 24, count 0 2006.197.08:06:01.34#ibcon#about to read 5, iclass 24, count 0 2006.197.08:06:01.34#ibcon#read 5, iclass 24, count 0 2006.197.08:06:01.34#ibcon#about to read 6, iclass 24, count 0 2006.197.08:06:01.34#ibcon#read 6, iclass 24, count 0 2006.197.08:06:01.34#ibcon#end of sib2, iclass 24, count 0 2006.197.08:06:01.34#ibcon#*mode == 0, iclass 24, count 0 2006.197.08:06:01.34#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.197.08:06:01.34#ibcon#[28=FRQ=04,712.99\r\n] 2006.197.08:06:01.34#ibcon#*before write, iclass 24, count 0 2006.197.08:06:01.34#ibcon#enter sib2, iclass 24, count 0 2006.197.08:06:01.34#ibcon#flushed, iclass 24, count 0 2006.197.08:06:01.34#ibcon#about to write, iclass 24, count 0 2006.197.08:06:01.34#ibcon#wrote, iclass 24, count 0 2006.197.08:06:01.34#ibcon#about to read 3, iclass 24, count 0 2006.197.08:06:01.38#ibcon#read 3, iclass 24, count 0 2006.197.08:06:01.38#ibcon#about to read 4, iclass 24, count 0 2006.197.08:06:01.38#ibcon#read 4, iclass 24, count 0 2006.197.08:06:01.38#ibcon#about to read 5, iclass 24, count 0 2006.197.08:06:01.38#ibcon#read 5, iclass 24, count 0 2006.197.08:06:01.38#ibcon#about to read 6, iclass 24, count 0 2006.197.08:06:01.38#ibcon#read 6, iclass 24, count 0 2006.197.08:06:01.38#ibcon#end of sib2, iclass 24, count 0 2006.197.08:06:01.38#ibcon#*after write, iclass 24, count 0 2006.197.08:06:01.38#ibcon#*before return 0, iclass 24, count 0 2006.197.08:06:01.38#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.197.08:06:01.38#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.197.08:06:01.38#ibcon#about to clear, iclass 24 cls_cnt 0 2006.197.08:06:01.38#ibcon#cleared, iclass 24 cls_cnt 0 2006.197.08:06:01.38$vc4f8/vb=4,4 2006.197.08:06:01.38#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.197.08:06:01.38#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.197.08:06:01.38#ibcon#ireg 11 cls_cnt 2 2006.197.08:06:01.38#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.197.08:06:01.44#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.197.08:06:01.44#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.197.08:06:01.44#ibcon#enter wrdev, iclass 26, count 2 2006.197.08:06:01.44#ibcon#first serial, iclass 26, count 2 2006.197.08:06:01.44#ibcon#enter sib2, iclass 26, count 2 2006.197.08:06:01.44#ibcon#flushed, iclass 26, count 2 2006.197.08:06:01.44#ibcon#about to write, iclass 26, count 2 2006.197.08:06:01.44#ibcon#wrote, iclass 26, count 2 2006.197.08:06:01.44#ibcon#about to read 3, iclass 26, count 2 2006.197.08:06:01.46#ibcon#read 3, iclass 26, count 2 2006.197.08:06:01.46#ibcon#about to read 4, iclass 26, count 2 2006.197.08:06:01.46#ibcon#read 4, iclass 26, count 2 2006.197.08:06:01.46#ibcon#about to read 5, iclass 26, count 2 2006.197.08:06:01.46#ibcon#read 5, iclass 26, count 2 2006.197.08:06:01.46#ibcon#about to read 6, iclass 26, count 2 2006.197.08:06:01.46#ibcon#read 6, iclass 26, count 2 2006.197.08:06:01.46#ibcon#end of sib2, iclass 26, count 2 2006.197.08:06:01.46#ibcon#*mode == 0, iclass 26, count 2 2006.197.08:06:01.46#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.197.08:06:01.46#ibcon#[27=AT04-04\r\n] 2006.197.08:06:01.46#ibcon#*before write, iclass 26, count 2 2006.197.08:06:01.46#ibcon#enter sib2, iclass 26, count 2 2006.197.08:06:01.46#ibcon#flushed, iclass 26, count 2 2006.197.08:06:01.46#ibcon#about to write, iclass 26, count 2 2006.197.08:06:01.46#ibcon#wrote, iclass 26, count 2 2006.197.08:06:01.46#ibcon#about to read 3, iclass 26, count 2 2006.197.08:06:01.49#ibcon#read 3, iclass 26, count 2 2006.197.08:06:01.49#ibcon#about to read 4, iclass 26, count 2 2006.197.08:06:01.49#ibcon#read 4, iclass 26, count 2 2006.197.08:06:01.49#ibcon#about to read 5, iclass 26, count 2 2006.197.08:06:01.49#ibcon#read 5, iclass 26, count 2 2006.197.08:06:01.49#ibcon#about to read 6, iclass 26, count 2 2006.197.08:06:01.49#ibcon#read 6, iclass 26, count 2 2006.197.08:06:01.49#ibcon#end of sib2, iclass 26, count 2 2006.197.08:06:01.49#ibcon#*after write, iclass 26, count 2 2006.197.08:06:01.49#ibcon#*before return 0, iclass 26, count 2 2006.197.08:06:01.49#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.197.08:06:01.49#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.197.08:06:01.49#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.197.08:06:01.49#ibcon#ireg 7 cls_cnt 0 2006.197.08:06:01.49#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.197.08:06:01.61#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.197.08:06:01.61#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.197.08:06:01.61#ibcon#enter wrdev, iclass 26, count 0 2006.197.08:06:01.61#ibcon#first serial, iclass 26, count 0 2006.197.08:06:01.61#ibcon#enter sib2, iclass 26, count 0 2006.197.08:06:01.61#ibcon#flushed, iclass 26, count 0 2006.197.08:06:01.61#ibcon#about to write, iclass 26, count 0 2006.197.08:06:01.61#ibcon#wrote, iclass 26, count 0 2006.197.08:06:01.61#ibcon#about to read 3, iclass 26, count 0 2006.197.08:06:01.63#ibcon#read 3, iclass 26, count 0 2006.197.08:06:01.63#ibcon#about to read 4, iclass 26, count 0 2006.197.08:06:01.63#ibcon#read 4, iclass 26, count 0 2006.197.08:06:01.63#ibcon#about to read 5, iclass 26, count 0 2006.197.08:06:01.63#ibcon#read 5, iclass 26, count 0 2006.197.08:06:01.63#ibcon#about to read 6, iclass 26, count 0 2006.197.08:06:01.63#ibcon#read 6, iclass 26, count 0 2006.197.08:06:01.63#ibcon#end of sib2, iclass 26, count 0 2006.197.08:06:01.63#ibcon#*mode == 0, iclass 26, count 0 2006.197.08:06:01.63#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.197.08:06:01.63#ibcon#[27=USB\r\n] 2006.197.08:06:01.63#ibcon#*before write, iclass 26, count 0 2006.197.08:06:01.63#ibcon#enter sib2, iclass 26, count 0 2006.197.08:06:01.63#ibcon#flushed, iclass 26, count 0 2006.197.08:06:01.63#ibcon#about to write, iclass 26, count 0 2006.197.08:06:01.63#ibcon#wrote, iclass 26, count 0 2006.197.08:06:01.63#ibcon#about to read 3, iclass 26, count 0 2006.197.08:06:01.66#ibcon#read 3, iclass 26, count 0 2006.197.08:06:01.66#ibcon#about to read 4, iclass 26, count 0 2006.197.08:06:01.66#ibcon#read 4, iclass 26, count 0 2006.197.08:06:01.66#ibcon#about to read 5, iclass 26, count 0 2006.197.08:06:01.66#ibcon#read 5, iclass 26, count 0 2006.197.08:06:01.66#ibcon#about to read 6, iclass 26, count 0 2006.197.08:06:01.66#ibcon#read 6, iclass 26, count 0 2006.197.08:06:01.66#ibcon#end of sib2, iclass 26, count 0 2006.197.08:06:01.66#ibcon#*after write, iclass 26, count 0 2006.197.08:06:01.66#ibcon#*before return 0, iclass 26, count 0 2006.197.08:06:01.66#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.197.08:06:01.66#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.197.08:06:01.66#ibcon#about to clear, iclass 26 cls_cnt 0 2006.197.08:06:01.66#ibcon#cleared, iclass 26 cls_cnt 0 2006.197.08:06:01.66$vc4f8/vblo=5,744.99 2006.197.08:06:01.66#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.197.08:06:01.66#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.197.08:06:01.66#ibcon#ireg 17 cls_cnt 0 2006.197.08:06:01.66#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.197.08:06:01.66#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.197.08:06:01.66#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.197.08:06:01.66#ibcon#enter wrdev, iclass 28, count 0 2006.197.08:06:01.66#ibcon#first serial, iclass 28, count 0 2006.197.08:06:01.66#ibcon#enter sib2, iclass 28, count 0 2006.197.08:06:01.66#ibcon#flushed, iclass 28, count 0 2006.197.08:06:01.66#ibcon#about to write, iclass 28, count 0 2006.197.08:06:01.66#ibcon#wrote, iclass 28, count 0 2006.197.08:06:01.66#ibcon#about to read 3, iclass 28, count 0 2006.197.08:06:01.68#ibcon#read 3, iclass 28, count 0 2006.197.08:06:01.68#ibcon#about to read 4, iclass 28, count 0 2006.197.08:06:01.68#ibcon#read 4, iclass 28, count 0 2006.197.08:06:01.68#ibcon#about to read 5, iclass 28, count 0 2006.197.08:06:01.68#ibcon#read 5, iclass 28, count 0 2006.197.08:06:01.68#ibcon#about to read 6, iclass 28, count 0 2006.197.08:06:01.68#ibcon#read 6, iclass 28, count 0 2006.197.08:06:01.68#ibcon#end of sib2, iclass 28, count 0 2006.197.08:06:01.68#ibcon#*mode == 0, iclass 28, count 0 2006.197.08:06:01.68#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.197.08:06:01.68#ibcon#[28=FRQ=05,744.99\r\n] 2006.197.08:06:01.68#ibcon#*before write, iclass 28, count 0 2006.197.08:06:01.68#ibcon#enter sib2, iclass 28, count 0 2006.197.08:06:01.68#ibcon#flushed, iclass 28, count 0 2006.197.08:06:01.68#ibcon#about to write, iclass 28, count 0 2006.197.08:06:01.68#ibcon#wrote, iclass 28, count 0 2006.197.08:06:01.68#ibcon#about to read 3, iclass 28, count 0 2006.197.08:06:01.72#ibcon#read 3, iclass 28, count 0 2006.197.08:06:01.72#ibcon#about to read 4, iclass 28, count 0 2006.197.08:06:01.72#ibcon#read 4, iclass 28, count 0 2006.197.08:06:01.72#ibcon#about to read 5, iclass 28, count 0 2006.197.08:06:01.72#ibcon#read 5, iclass 28, count 0 2006.197.08:06:01.72#ibcon#about to read 6, iclass 28, count 0 2006.197.08:06:01.72#ibcon#read 6, iclass 28, count 0 2006.197.08:06:01.72#ibcon#end of sib2, iclass 28, count 0 2006.197.08:06:01.72#ibcon#*after write, iclass 28, count 0 2006.197.08:06:01.72#ibcon#*before return 0, iclass 28, count 0 2006.197.08:06:01.72#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.197.08:06:01.72#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.197.08:06:01.72#ibcon#about to clear, iclass 28 cls_cnt 0 2006.197.08:06:01.72#ibcon#cleared, iclass 28 cls_cnt 0 2006.197.08:06:01.72$vc4f8/vb=5,4 2006.197.08:06:01.72#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.197.08:06:01.72#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.197.08:06:01.72#ibcon#ireg 11 cls_cnt 2 2006.197.08:06:01.72#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.197.08:06:01.78#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.197.08:06:01.78#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.197.08:06:01.78#ibcon#enter wrdev, iclass 30, count 2 2006.197.08:06:01.78#ibcon#first serial, iclass 30, count 2 2006.197.08:06:01.78#ibcon#enter sib2, iclass 30, count 2 2006.197.08:06:01.78#ibcon#flushed, iclass 30, count 2 2006.197.08:06:01.78#ibcon#about to write, iclass 30, count 2 2006.197.08:06:01.78#ibcon#wrote, iclass 30, count 2 2006.197.08:06:01.78#ibcon#about to read 3, iclass 30, count 2 2006.197.08:06:01.80#ibcon#read 3, iclass 30, count 2 2006.197.08:06:01.80#ibcon#about to read 4, iclass 30, count 2 2006.197.08:06:01.80#ibcon#read 4, iclass 30, count 2 2006.197.08:06:01.80#ibcon#about to read 5, iclass 30, count 2 2006.197.08:06:01.80#ibcon#read 5, iclass 30, count 2 2006.197.08:06:01.80#ibcon#about to read 6, iclass 30, count 2 2006.197.08:06:01.80#ibcon#read 6, iclass 30, count 2 2006.197.08:06:01.80#ibcon#end of sib2, iclass 30, count 2 2006.197.08:06:01.80#ibcon#*mode == 0, iclass 30, count 2 2006.197.08:06:01.80#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.197.08:06:01.80#ibcon#[27=AT05-04\r\n] 2006.197.08:06:01.80#ibcon#*before write, iclass 30, count 2 2006.197.08:06:01.80#ibcon#enter sib2, iclass 30, count 2 2006.197.08:06:01.80#ibcon#flushed, iclass 30, count 2 2006.197.08:06:01.80#ibcon#about to write, iclass 30, count 2 2006.197.08:06:01.80#ibcon#wrote, iclass 30, count 2 2006.197.08:06:01.80#ibcon#about to read 3, iclass 30, count 2 2006.197.08:06:01.83#ibcon#read 3, iclass 30, count 2 2006.197.08:06:01.83#ibcon#about to read 4, iclass 30, count 2 2006.197.08:06:01.83#ibcon#read 4, iclass 30, count 2 2006.197.08:06:01.83#ibcon#about to read 5, iclass 30, count 2 2006.197.08:06:01.83#ibcon#read 5, iclass 30, count 2 2006.197.08:06:01.83#ibcon#about to read 6, iclass 30, count 2 2006.197.08:06:01.83#ibcon#read 6, iclass 30, count 2 2006.197.08:06:01.83#ibcon#end of sib2, iclass 30, count 2 2006.197.08:06:01.83#ibcon#*after write, iclass 30, count 2 2006.197.08:06:01.83#ibcon#*before return 0, iclass 30, count 2 2006.197.08:06:01.83#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.197.08:06:01.83#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.197.08:06:01.83#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.197.08:06:01.83#ibcon#ireg 7 cls_cnt 0 2006.197.08:06:01.83#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.197.08:06:01.95#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.197.08:06:01.95#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.197.08:06:01.95#ibcon#enter wrdev, iclass 30, count 0 2006.197.08:06:01.95#ibcon#first serial, iclass 30, count 0 2006.197.08:06:01.95#ibcon#enter sib2, iclass 30, count 0 2006.197.08:06:01.95#ibcon#flushed, iclass 30, count 0 2006.197.08:06:01.95#ibcon#about to write, iclass 30, count 0 2006.197.08:06:01.95#ibcon#wrote, iclass 30, count 0 2006.197.08:06:01.95#ibcon#about to read 3, iclass 30, count 0 2006.197.08:06:01.97#ibcon#read 3, iclass 30, count 0 2006.197.08:06:01.97#ibcon#about to read 4, iclass 30, count 0 2006.197.08:06:01.97#ibcon#read 4, iclass 30, count 0 2006.197.08:06:01.97#ibcon#about to read 5, iclass 30, count 0 2006.197.08:06:01.97#ibcon#read 5, iclass 30, count 0 2006.197.08:06:01.97#ibcon#about to read 6, iclass 30, count 0 2006.197.08:06:01.97#ibcon#read 6, iclass 30, count 0 2006.197.08:06:01.97#ibcon#end of sib2, iclass 30, count 0 2006.197.08:06:01.97#ibcon#*mode == 0, iclass 30, count 0 2006.197.08:06:01.97#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.197.08:06:01.97#ibcon#[27=USB\r\n] 2006.197.08:06:01.97#ibcon#*before write, iclass 30, count 0 2006.197.08:06:01.97#ibcon#enter sib2, iclass 30, count 0 2006.197.08:06:01.97#ibcon#flushed, iclass 30, count 0 2006.197.08:06:01.97#ibcon#about to write, iclass 30, count 0 2006.197.08:06:01.97#ibcon#wrote, iclass 30, count 0 2006.197.08:06:01.97#ibcon#about to read 3, iclass 30, count 0 2006.197.08:06:02.00#ibcon#read 3, iclass 30, count 0 2006.197.08:06:02.00#ibcon#about to read 4, iclass 30, count 0 2006.197.08:06:02.00#ibcon#read 4, iclass 30, count 0 2006.197.08:06:02.00#ibcon#about to read 5, iclass 30, count 0 2006.197.08:06:02.00#ibcon#read 5, iclass 30, count 0 2006.197.08:06:02.00#ibcon#about to read 6, iclass 30, count 0 2006.197.08:06:02.00#ibcon#read 6, iclass 30, count 0 2006.197.08:06:02.00#ibcon#end of sib2, iclass 30, count 0 2006.197.08:06:02.00#ibcon#*after write, iclass 30, count 0 2006.197.08:06:02.00#ibcon#*before return 0, iclass 30, count 0 2006.197.08:06:02.00#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.197.08:06:02.00#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.197.08:06:02.00#ibcon#about to clear, iclass 30 cls_cnt 0 2006.197.08:06:02.00#ibcon#cleared, iclass 30 cls_cnt 0 2006.197.08:06:02.00$vc4f8/vblo=6,752.99 2006.197.08:06:02.00#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.197.08:06:02.00#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.197.08:06:02.00#ibcon#ireg 17 cls_cnt 0 2006.197.08:06:02.00#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.197.08:06:02.00#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.197.08:06:02.00#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.197.08:06:02.00#ibcon#enter wrdev, iclass 32, count 0 2006.197.08:06:02.00#ibcon#first serial, iclass 32, count 0 2006.197.08:06:02.00#ibcon#enter sib2, iclass 32, count 0 2006.197.08:06:02.00#ibcon#flushed, iclass 32, count 0 2006.197.08:06:02.00#ibcon#about to write, iclass 32, count 0 2006.197.08:06:02.00#ibcon#wrote, iclass 32, count 0 2006.197.08:06:02.00#ibcon#about to read 3, iclass 32, count 0 2006.197.08:06:02.02#ibcon#read 3, iclass 32, count 0 2006.197.08:06:02.02#ibcon#about to read 4, iclass 32, count 0 2006.197.08:06:02.02#ibcon#read 4, iclass 32, count 0 2006.197.08:06:02.02#ibcon#about to read 5, iclass 32, count 0 2006.197.08:06:02.02#ibcon#read 5, iclass 32, count 0 2006.197.08:06:02.02#ibcon#about to read 6, iclass 32, count 0 2006.197.08:06:02.02#ibcon#read 6, iclass 32, count 0 2006.197.08:06:02.02#ibcon#end of sib2, iclass 32, count 0 2006.197.08:06:02.02#ibcon#*mode == 0, iclass 32, count 0 2006.197.08:06:02.02#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.197.08:06:02.02#ibcon#[28=FRQ=06,752.99\r\n] 2006.197.08:06:02.02#ibcon#*before write, iclass 32, count 0 2006.197.08:06:02.02#ibcon#enter sib2, iclass 32, count 0 2006.197.08:06:02.02#ibcon#flushed, iclass 32, count 0 2006.197.08:06:02.02#ibcon#about to write, iclass 32, count 0 2006.197.08:06:02.02#ibcon#wrote, iclass 32, count 0 2006.197.08:06:02.02#ibcon#about to read 3, iclass 32, count 0 2006.197.08:06:02.06#ibcon#read 3, iclass 32, count 0 2006.197.08:06:02.06#ibcon#about to read 4, iclass 32, count 0 2006.197.08:06:02.06#ibcon#read 4, iclass 32, count 0 2006.197.08:06:02.06#ibcon#about to read 5, iclass 32, count 0 2006.197.08:06:02.06#ibcon#read 5, iclass 32, count 0 2006.197.08:06:02.06#ibcon#about to read 6, iclass 32, count 0 2006.197.08:06:02.06#ibcon#read 6, iclass 32, count 0 2006.197.08:06:02.06#ibcon#end of sib2, iclass 32, count 0 2006.197.08:06:02.06#ibcon#*after write, iclass 32, count 0 2006.197.08:06:02.06#ibcon#*before return 0, iclass 32, count 0 2006.197.08:06:02.06#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.197.08:06:02.06#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.197.08:06:02.06#ibcon#about to clear, iclass 32 cls_cnt 0 2006.197.08:06:02.06#ibcon#cleared, iclass 32 cls_cnt 0 2006.197.08:06:02.06$vc4f8/vb=6,4 2006.197.08:06:02.06#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.197.08:06:02.06#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.197.08:06:02.06#ibcon#ireg 11 cls_cnt 2 2006.197.08:06:02.06#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.197.08:06:02.12#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.197.08:06:02.12#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.197.08:06:02.12#ibcon#enter wrdev, iclass 34, count 2 2006.197.08:06:02.12#ibcon#first serial, iclass 34, count 2 2006.197.08:06:02.12#ibcon#enter sib2, iclass 34, count 2 2006.197.08:06:02.12#ibcon#flushed, iclass 34, count 2 2006.197.08:06:02.12#ibcon#about to write, iclass 34, count 2 2006.197.08:06:02.12#ibcon#wrote, iclass 34, count 2 2006.197.08:06:02.12#ibcon#about to read 3, iclass 34, count 2 2006.197.08:06:02.14#ibcon#read 3, iclass 34, count 2 2006.197.08:06:02.14#ibcon#about to read 4, iclass 34, count 2 2006.197.08:06:02.14#ibcon#read 4, iclass 34, count 2 2006.197.08:06:02.14#ibcon#about to read 5, iclass 34, count 2 2006.197.08:06:02.14#ibcon#read 5, iclass 34, count 2 2006.197.08:06:02.14#ibcon#about to read 6, iclass 34, count 2 2006.197.08:06:02.14#ibcon#read 6, iclass 34, count 2 2006.197.08:06:02.14#ibcon#end of sib2, iclass 34, count 2 2006.197.08:06:02.14#ibcon#*mode == 0, iclass 34, count 2 2006.197.08:06:02.14#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.197.08:06:02.14#ibcon#[27=AT06-04\r\n] 2006.197.08:06:02.14#ibcon#*before write, iclass 34, count 2 2006.197.08:06:02.14#ibcon#enter sib2, iclass 34, count 2 2006.197.08:06:02.14#ibcon#flushed, iclass 34, count 2 2006.197.08:06:02.14#ibcon#about to write, iclass 34, count 2 2006.197.08:06:02.14#ibcon#wrote, iclass 34, count 2 2006.197.08:06:02.14#ibcon#about to read 3, iclass 34, count 2 2006.197.08:06:02.17#ibcon#read 3, iclass 34, count 2 2006.197.08:06:02.17#ibcon#about to read 4, iclass 34, count 2 2006.197.08:06:02.17#ibcon#read 4, iclass 34, count 2 2006.197.08:06:02.17#ibcon#about to read 5, iclass 34, count 2 2006.197.08:06:02.17#ibcon#read 5, iclass 34, count 2 2006.197.08:06:02.17#ibcon#about to read 6, iclass 34, count 2 2006.197.08:06:02.17#ibcon#read 6, iclass 34, count 2 2006.197.08:06:02.17#ibcon#end of sib2, iclass 34, count 2 2006.197.08:06:02.17#ibcon#*after write, iclass 34, count 2 2006.197.08:06:02.17#ibcon#*before return 0, iclass 34, count 2 2006.197.08:06:02.17#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.197.08:06:02.17#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.197.08:06:02.17#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.197.08:06:02.17#ibcon#ireg 7 cls_cnt 0 2006.197.08:06:02.17#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.197.08:06:02.29#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.197.08:06:02.29#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.197.08:06:02.29#ibcon#enter wrdev, iclass 34, count 0 2006.197.08:06:02.29#ibcon#first serial, iclass 34, count 0 2006.197.08:06:02.29#ibcon#enter sib2, iclass 34, count 0 2006.197.08:06:02.29#ibcon#flushed, iclass 34, count 0 2006.197.08:06:02.29#ibcon#about to write, iclass 34, count 0 2006.197.08:06:02.29#ibcon#wrote, iclass 34, count 0 2006.197.08:06:02.29#ibcon#about to read 3, iclass 34, count 0 2006.197.08:06:02.31#ibcon#read 3, iclass 34, count 0 2006.197.08:06:02.31#ibcon#about to read 4, iclass 34, count 0 2006.197.08:06:02.31#ibcon#read 4, iclass 34, count 0 2006.197.08:06:02.31#ibcon#about to read 5, iclass 34, count 0 2006.197.08:06:02.31#ibcon#read 5, iclass 34, count 0 2006.197.08:06:02.31#ibcon#about to read 6, iclass 34, count 0 2006.197.08:06:02.31#ibcon#read 6, iclass 34, count 0 2006.197.08:06:02.31#ibcon#end of sib2, iclass 34, count 0 2006.197.08:06:02.31#ibcon#*mode == 0, iclass 34, count 0 2006.197.08:06:02.31#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.197.08:06:02.31#ibcon#[27=USB\r\n] 2006.197.08:06:02.31#ibcon#*before write, iclass 34, count 0 2006.197.08:06:02.31#ibcon#enter sib2, iclass 34, count 0 2006.197.08:06:02.31#ibcon#flushed, iclass 34, count 0 2006.197.08:06:02.31#ibcon#about to write, iclass 34, count 0 2006.197.08:06:02.31#ibcon#wrote, iclass 34, count 0 2006.197.08:06:02.31#ibcon#about to read 3, iclass 34, count 0 2006.197.08:06:02.34#ibcon#read 3, iclass 34, count 0 2006.197.08:06:02.34#ibcon#about to read 4, iclass 34, count 0 2006.197.08:06:02.34#ibcon#read 4, iclass 34, count 0 2006.197.08:06:02.34#ibcon#about to read 5, iclass 34, count 0 2006.197.08:06:02.34#ibcon#read 5, iclass 34, count 0 2006.197.08:06:02.34#ibcon#about to read 6, iclass 34, count 0 2006.197.08:06:02.34#ibcon#read 6, iclass 34, count 0 2006.197.08:06:02.34#ibcon#end of sib2, iclass 34, count 0 2006.197.08:06:02.34#ibcon#*after write, iclass 34, count 0 2006.197.08:06:02.34#ibcon#*before return 0, iclass 34, count 0 2006.197.08:06:02.34#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.197.08:06:02.34#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.197.08:06:02.34#ibcon#about to clear, iclass 34 cls_cnt 0 2006.197.08:06:02.34#ibcon#cleared, iclass 34 cls_cnt 0 2006.197.08:06:02.34$vc4f8/vabw=wide 2006.197.08:06:02.34#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.197.08:06:02.34#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.197.08:06:02.34#ibcon#ireg 8 cls_cnt 0 2006.197.08:06:02.34#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.197.08:06:02.34#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.197.08:06:02.34#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.197.08:06:02.34#ibcon#enter wrdev, iclass 36, count 0 2006.197.08:06:02.34#ibcon#first serial, iclass 36, count 0 2006.197.08:06:02.34#ibcon#enter sib2, iclass 36, count 0 2006.197.08:06:02.34#ibcon#flushed, iclass 36, count 0 2006.197.08:06:02.34#ibcon#about to write, iclass 36, count 0 2006.197.08:06:02.34#ibcon#wrote, iclass 36, count 0 2006.197.08:06:02.34#ibcon#about to read 3, iclass 36, count 0 2006.197.08:06:02.36#ibcon#read 3, iclass 36, count 0 2006.197.08:06:02.36#ibcon#about to read 4, iclass 36, count 0 2006.197.08:06:02.36#ibcon#read 4, iclass 36, count 0 2006.197.08:06:02.36#ibcon#about to read 5, iclass 36, count 0 2006.197.08:06:02.36#ibcon#read 5, iclass 36, count 0 2006.197.08:06:02.36#ibcon#about to read 6, iclass 36, count 0 2006.197.08:06:02.36#ibcon#read 6, iclass 36, count 0 2006.197.08:06:02.36#ibcon#end of sib2, iclass 36, count 0 2006.197.08:06:02.36#ibcon#*mode == 0, iclass 36, count 0 2006.197.08:06:02.36#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.197.08:06:02.36#ibcon#[25=BW32\r\n] 2006.197.08:06:02.36#ibcon#*before write, iclass 36, count 0 2006.197.08:06:02.36#ibcon#enter sib2, iclass 36, count 0 2006.197.08:06:02.36#ibcon#flushed, iclass 36, count 0 2006.197.08:06:02.36#ibcon#about to write, iclass 36, count 0 2006.197.08:06:02.36#ibcon#wrote, iclass 36, count 0 2006.197.08:06:02.36#ibcon#about to read 3, iclass 36, count 0 2006.197.08:06:02.39#ibcon#read 3, iclass 36, count 0 2006.197.08:06:02.39#ibcon#about to read 4, iclass 36, count 0 2006.197.08:06:02.39#ibcon#read 4, iclass 36, count 0 2006.197.08:06:02.39#ibcon#about to read 5, iclass 36, count 0 2006.197.08:06:02.39#ibcon#read 5, iclass 36, count 0 2006.197.08:06:02.39#ibcon#about to read 6, iclass 36, count 0 2006.197.08:06:02.39#ibcon#read 6, iclass 36, count 0 2006.197.08:06:02.39#ibcon#end of sib2, iclass 36, count 0 2006.197.08:06:02.39#ibcon#*after write, iclass 36, count 0 2006.197.08:06:02.39#ibcon#*before return 0, iclass 36, count 0 2006.197.08:06:02.39#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.197.08:06:02.39#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.197.08:06:02.39#ibcon#about to clear, iclass 36 cls_cnt 0 2006.197.08:06:02.39#ibcon#cleared, iclass 36 cls_cnt 0 2006.197.08:06:02.39$vc4f8/vbbw=wide 2006.197.08:06:02.39#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.197.08:06:02.39#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.197.08:06:02.39#ibcon#ireg 8 cls_cnt 0 2006.197.08:06:02.39#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.197.08:06:02.46#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.197.08:06:02.46#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.197.08:06:02.46#ibcon#enter wrdev, iclass 38, count 0 2006.197.08:06:02.46#ibcon#first serial, iclass 38, count 0 2006.197.08:06:02.46#ibcon#enter sib2, iclass 38, count 0 2006.197.08:06:02.46#ibcon#flushed, iclass 38, count 0 2006.197.08:06:02.46#ibcon#about to write, iclass 38, count 0 2006.197.08:06:02.46#ibcon#wrote, iclass 38, count 0 2006.197.08:06:02.46#ibcon#about to read 3, iclass 38, count 0 2006.197.08:06:02.48#ibcon#read 3, iclass 38, count 0 2006.197.08:06:02.48#ibcon#about to read 4, iclass 38, count 0 2006.197.08:06:02.48#ibcon#read 4, iclass 38, count 0 2006.197.08:06:02.48#ibcon#about to read 5, iclass 38, count 0 2006.197.08:06:02.48#ibcon#read 5, iclass 38, count 0 2006.197.08:06:02.48#ibcon#about to read 6, iclass 38, count 0 2006.197.08:06:02.48#ibcon#read 6, iclass 38, count 0 2006.197.08:06:02.48#ibcon#end of sib2, iclass 38, count 0 2006.197.08:06:02.48#ibcon#*mode == 0, iclass 38, count 0 2006.197.08:06:02.48#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.197.08:06:02.48#ibcon#[27=BW32\r\n] 2006.197.08:06:02.48#ibcon#*before write, iclass 38, count 0 2006.197.08:06:02.48#ibcon#enter sib2, iclass 38, count 0 2006.197.08:06:02.48#ibcon#flushed, iclass 38, count 0 2006.197.08:06:02.48#ibcon#about to write, iclass 38, count 0 2006.197.08:06:02.48#ibcon#wrote, iclass 38, count 0 2006.197.08:06:02.48#ibcon#about to read 3, iclass 38, count 0 2006.197.08:06:02.51#ibcon#read 3, iclass 38, count 0 2006.197.08:06:02.51#ibcon#about to read 4, iclass 38, count 0 2006.197.08:06:02.51#ibcon#read 4, iclass 38, count 0 2006.197.08:06:02.51#ibcon#about to read 5, iclass 38, count 0 2006.197.08:06:02.51#ibcon#read 5, iclass 38, count 0 2006.197.08:06:02.51#ibcon#about to read 6, iclass 38, count 0 2006.197.08:06:02.51#ibcon#read 6, iclass 38, count 0 2006.197.08:06:02.51#ibcon#end of sib2, iclass 38, count 0 2006.197.08:06:02.51#ibcon#*after write, iclass 38, count 0 2006.197.08:06:02.51#ibcon#*before return 0, iclass 38, count 0 2006.197.08:06:02.51#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.197.08:06:02.51#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.197.08:06:02.51#ibcon#about to clear, iclass 38 cls_cnt 0 2006.197.08:06:02.51#ibcon#cleared, iclass 38 cls_cnt 0 2006.197.08:06:02.51$4f8m12a/ifd4f 2006.197.08:06:02.51$ifd4f/lo= 2006.197.08:06:02.51$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.197.08:06:02.51$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.197.08:06:02.51$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.197.08:06:02.51$ifd4f/patch= 2006.197.08:06:02.51$ifd4f/patch=lo1,a1,a2,a3,a4 2006.197.08:06:02.51$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.197.08:06:02.51$ifd4f/patch=lo3,a5,a6,a7,a8 2006.197.08:06:02.51$4f8m12a/"form=m,16.000,1:2 2006.197.08:06:02.51$4f8m12a/"tpicd 2006.197.08:06:02.51$4f8m12a/echo=off 2006.197.08:06:02.51$4f8m12a/xlog=off 2006.197.08:06:02.51:!2006.197.08:06:40 2006.197.08:06:24.14#trakl#Source acquired 2006.197.08:06:24.14#flagr#flagr/antenna,acquired 2006.197.08:06:40.00:preob 2006.197.08:06:40.14/onsource/TRACKING 2006.197.08:06:40.14:!2006.197.08:06:50 2006.197.08:06:50.00:data_valid=on 2006.197.08:06:50.00:midob 2006.197.08:06:51.14/onsource/TRACKING 2006.197.08:06:51.14/wx/25.66,1002.7,96 2006.197.08:06:51.21/cable/+6.3709E-03 2006.197.08:06:52.30/va/01,08,usb,yes,30,32 2006.197.08:06:52.30/va/02,07,usb,yes,30,31 2006.197.08:06:52.30/va/03,06,usb,yes,32,32 2006.197.08:06:52.30/va/04,07,usb,yes,31,33 2006.197.08:06:52.30/va/05,07,usb,yes,35,37 2006.197.08:06:52.30/va/06,06,usb,yes,34,34 2006.197.08:06:52.30/va/07,06,usb,yes,34,34 2006.197.08:06:52.30/va/08,07,usb,yes,33,32 2006.197.08:06:52.53/valo/01,532.99,yes,locked 2006.197.08:06:52.53/valo/02,572.99,yes,locked 2006.197.08:06:52.53/valo/03,672.99,yes,locked 2006.197.08:06:52.53/valo/04,832.99,yes,locked 2006.197.08:06:52.53/valo/05,652.99,yes,locked 2006.197.08:06:52.53/valo/06,772.99,yes,locked 2006.197.08:06:52.53/valo/07,832.99,yes,locked 2006.197.08:06:52.53/valo/08,852.99,yes,locked 2006.197.08:06:53.62/vb/01,04,usb,yes,29,28 2006.197.08:06:53.62/vb/02,04,usb,yes,31,32 2006.197.08:06:53.62/vb/03,04,usb,yes,27,31 2006.197.08:06:53.62/vb/04,04,usb,yes,28,28 2006.197.08:06:53.62/vb/05,04,usb,yes,27,31 2006.197.08:06:53.62/vb/06,04,usb,yes,28,30 2006.197.08:06:53.62/vb/07,04,usb,yes,30,30 2006.197.08:06:53.62/vb/08,04,usb,yes,27,31 2006.197.08:06:53.85/vblo/01,632.99,yes,locked 2006.197.08:06:53.85/vblo/02,640.99,yes,locked 2006.197.08:06:53.85/vblo/03,656.99,yes,locked 2006.197.08:06:53.85/vblo/04,712.99,yes,locked 2006.197.08:06:53.85/vblo/05,744.99,yes,locked 2006.197.08:06:53.85/vblo/06,752.99,yes,locked 2006.197.08:06:53.85/vblo/07,734.99,yes,locked 2006.197.08:06:53.85/vblo/08,744.99,yes,locked 2006.197.08:06:54.00/vabw/8 2006.197.08:06:54.15/vbbw/8 2006.197.08:06:54.24/xfe/off,on,15.7 2006.197.08:06:54.63/ifatt/23,28,28,28 2006.197.08:06:55.09/fmout-gps/S +3.01E-07 2006.197.08:06:55.13:!2006.197.08:07:50 2006.197.08:07:50.00:data_valid=off 2006.197.08:07:50.00:postob 2006.197.08:07:50.06/cable/+6.3713E-03 2006.197.08:07:50.06/wx/25.65,1002.8,96 2006.197.08:07:51.09/fmout-gps/S +3.01E-07 2006.197.08:07:51.09:scan_name=197-0808,k06197,60 2006.197.08:07:51.09:source=0642+449,064632.03,445116.6,2000.0,ccw 2006.197.08:07:51.14#flagr#flagr/antenna,new-source 2006.197.08:07:52.14:checkk5 2006.197.08:07:52.48/chk_autoobs//k5ts1/ autoobs is running! 2006.197.08:07:52.82/chk_autoobs//k5ts2/ autoobs is running! 2006.197.08:07:53.60/chk_autoobs//k5ts3/ autoobs is running! 2006.197.08:07:53.94/chk_autoobs//k5ts4/ autoobs is running! 2006.197.08:07:54.28/chk_obsdata//k5ts1/T1970806??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.08:07:54.61/chk_obsdata//k5ts2/T1970806??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.08:07:54.95/chk_obsdata//k5ts3/T1970806??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.08:07:55.28/chk_obsdata//k5ts4/T1970806??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.08:07:55.94/k5log//k5ts1_log_newline 2006.197.08:07:56.60/k5log//k5ts2_log_newline 2006.197.08:07:57.26/k5log//k5ts3_log_newline 2006.197.08:07:57.91/k5log//k5ts4_log_newline 2006.197.08:07:57.94/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.197.08:07:57.94:4f8m12a=2 2006.197.08:07:57.94$4f8m12a/echo=on 2006.197.08:07:57.94$4f8m12a/pcalon 2006.197.08:07:57.94$pcalon/"no phase cal control is implemented here 2006.197.08:07:57.94$4f8m12a/"tpicd=stop 2006.197.08:07:57.94$4f8m12a/vc4f8 2006.197.08:07:57.94$vc4f8/valo=1,532.99 2006.197.08:07:57.94#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.197.08:07:57.94#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.197.08:07:57.94#ibcon#ireg 17 cls_cnt 0 2006.197.08:07:57.94#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.197.08:07:57.94#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.197.08:07:57.94#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.197.08:07:57.94#ibcon#enter wrdev, iclass 10, count 0 2006.197.08:07:57.94#ibcon#first serial, iclass 10, count 0 2006.197.08:07:57.94#ibcon#enter sib2, iclass 10, count 0 2006.197.08:07:57.94#ibcon#flushed, iclass 10, count 0 2006.197.08:07:57.94#ibcon#about to write, iclass 10, count 0 2006.197.08:07:57.94#ibcon#wrote, iclass 10, count 0 2006.197.08:07:57.94#ibcon#about to read 3, iclass 10, count 0 2006.197.08:07:57.96#ibcon#read 3, iclass 10, count 0 2006.197.08:07:57.96#ibcon#about to read 4, iclass 10, count 0 2006.197.08:07:57.96#ibcon#read 4, iclass 10, count 0 2006.197.08:07:57.96#ibcon#about to read 5, iclass 10, count 0 2006.197.08:07:57.96#ibcon#read 5, iclass 10, count 0 2006.197.08:07:57.96#ibcon#about to read 6, iclass 10, count 0 2006.197.08:07:57.96#ibcon#read 6, iclass 10, count 0 2006.197.08:07:57.96#ibcon#end of sib2, iclass 10, count 0 2006.197.08:07:57.96#ibcon#*mode == 0, iclass 10, count 0 2006.197.08:07:57.96#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.197.08:07:57.96#ibcon#[26=FRQ=01,532.99\r\n] 2006.197.08:07:57.96#ibcon#*before write, iclass 10, count 0 2006.197.08:07:57.96#ibcon#enter sib2, iclass 10, count 0 2006.197.08:07:57.96#ibcon#flushed, iclass 10, count 0 2006.197.08:07:57.96#ibcon#about to write, iclass 10, count 0 2006.197.08:07:57.96#ibcon#wrote, iclass 10, count 0 2006.197.08:07:57.96#ibcon#about to read 3, iclass 10, count 0 2006.197.08:07:58.01#ibcon#read 3, iclass 10, count 0 2006.197.08:07:58.01#ibcon#about to read 4, iclass 10, count 0 2006.197.08:07:58.01#ibcon#read 4, iclass 10, count 0 2006.197.08:07:58.01#ibcon#about to read 5, iclass 10, count 0 2006.197.08:07:58.01#ibcon#read 5, iclass 10, count 0 2006.197.08:07:58.01#ibcon#about to read 6, iclass 10, count 0 2006.197.08:07:58.01#ibcon#read 6, iclass 10, count 0 2006.197.08:07:58.01#ibcon#end of sib2, iclass 10, count 0 2006.197.08:07:58.01#ibcon#*after write, iclass 10, count 0 2006.197.08:07:58.01#ibcon#*before return 0, iclass 10, count 0 2006.197.08:07:58.01#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.197.08:07:58.01#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.197.08:07:58.01#ibcon#about to clear, iclass 10 cls_cnt 0 2006.197.08:07:58.01#ibcon#cleared, iclass 10 cls_cnt 0 2006.197.08:07:58.01$vc4f8/va=1,8 2006.197.08:07:58.01#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.197.08:07:58.01#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.197.08:07:58.01#ibcon#ireg 11 cls_cnt 2 2006.197.08:07:58.01#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.197.08:07:58.01#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.197.08:07:58.01#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.197.08:07:58.01#ibcon#enter wrdev, iclass 12, count 2 2006.197.08:07:58.01#ibcon#first serial, iclass 12, count 2 2006.197.08:07:58.01#ibcon#enter sib2, iclass 12, count 2 2006.197.08:07:58.01#ibcon#flushed, iclass 12, count 2 2006.197.08:07:58.01#ibcon#about to write, iclass 12, count 2 2006.197.08:07:58.01#ibcon#wrote, iclass 12, count 2 2006.197.08:07:58.01#ibcon#about to read 3, iclass 12, count 2 2006.197.08:07:58.03#ibcon#read 3, iclass 12, count 2 2006.197.08:07:58.03#ibcon#about to read 4, iclass 12, count 2 2006.197.08:07:58.03#ibcon#read 4, iclass 12, count 2 2006.197.08:07:58.03#ibcon#about to read 5, iclass 12, count 2 2006.197.08:07:58.03#ibcon#read 5, iclass 12, count 2 2006.197.08:07:58.03#ibcon#about to read 6, iclass 12, count 2 2006.197.08:07:58.03#ibcon#read 6, iclass 12, count 2 2006.197.08:07:58.03#ibcon#end of sib2, iclass 12, count 2 2006.197.08:07:58.03#ibcon#*mode == 0, iclass 12, count 2 2006.197.08:07:58.03#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.197.08:07:58.03#ibcon#[25=AT01-08\r\n] 2006.197.08:07:58.03#ibcon#*before write, iclass 12, count 2 2006.197.08:07:58.03#ibcon#enter sib2, iclass 12, count 2 2006.197.08:07:58.03#ibcon#flushed, iclass 12, count 2 2006.197.08:07:58.03#ibcon#about to write, iclass 12, count 2 2006.197.08:07:58.03#ibcon#wrote, iclass 12, count 2 2006.197.08:07:58.03#ibcon#about to read 3, iclass 12, count 2 2006.197.08:07:58.06#ibcon#read 3, iclass 12, count 2 2006.197.08:07:58.06#ibcon#about to read 4, iclass 12, count 2 2006.197.08:07:58.06#ibcon#read 4, iclass 12, count 2 2006.197.08:07:58.06#ibcon#about to read 5, iclass 12, count 2 2006.197.08:07:58.06#ibcon#read 5, iclass 12, count 2 2006.197.08:07:58.06#ibcon#about to read 6, iclass 12, count 2 2006.197.08:07:58.06#ibcon#read 6, iclass 12, count 2 2006.197.08:07:58.06#ibcon#end of sib2, iclass 12, count 2 2006.197.08:07:58.06#ibcon#*after write, iclass 12, count 2 2006.197.08:07:58.06#ibcon#*before return 0, iclass 12, count 2 2006.197.08:07:58.06#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.197.08:07:58.06#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.197.08:07:58.06#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.197.08:07:58.06#ibcon#ireg 7 cls_cnt 0 2006.197.08:07:58.06#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.197.08:07:58.18#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.197.08:07:58.18#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.197.08:07:58.18#ibcon#enter wrdev, iclass 12, count 0 2006.197.08:07:58.18#ibcon#first serial, iclass 12, count 0 2006.197.08:07:58.18#ibcon#enter sib2, iclass 12, count 0 2006.197.08:07:58.18#ibcon#flushed, iclass 12, count 0 2006.197.08:07:58.18#ibcon#about to write, iclass 12, count 0 2006.197.08:07:58.18#ibcon#wrote, iclass 12, count 0 2006.197.08:07:58.18#ibcon#about to read 3, iclass 12, count 0 2006.197.08:07:58.20#ibcon#read 3, iclass 12, count 0 2006.197.08:07:58.20#ibcon#about to read 4, iclass 12, count 0 2006.197.08:07:58.20#ibcon#read 4, iclass 12, count 0 2006.197.08:07:58.20#ibcon#about to read 5, iclass 12, count 0 2006.197.08:07:58.20#ibcon#read 5, iclass 12, count 0 2006.197.08:07:58.20#ibcon#about to read 6, iclass 12, count 0 2006.197.08:07:58.20#ibcon#read 6, iclass 12, count 0 2006.197.08:07:58.20#ibcon#end of sib2, iclass 12, count 0 2006.197.08:07:58.20#ibcon#*mode == 0, iclass 12, count 0 2006.197.08:07:58.20#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.197.08:07:58.20#ibcon#[25=USB\r\n] 2006.197.08:07:58.20#ibcon#*before write, iclass 12, count 0 2006.197.08:07:58.20#ibcon#enter sib2, iclass 12, count 0 2006.197.08:07:58.20#ibcon#flushed, iclass 12, count 0 2006.197.08:07:58.20#ibcon#about to write, iclass 12, count 0 2006.197.08:07:58.20#ibcon#wrote, iclass 12, count 0 2006.197.08:07:58.20#ibcon#about to read 3, iclass 12, count 0 2006.197.08:07:58.23#ibcon#read 3, iclass 12, count 0 2006.197.08:07:58.23#ibcon#about to read 4, iclass 12, count 0 2006.197.08:07:58.23#ibcon#read 4, iclass 12, count 0 2006.197.08:07:58.23#ibcon#about to read 5, iclass 12, count 0 2006.197.08:07:58.23#ibcon#read 5, iclass 12, count 0 2006.197.08:07:58.23#ibcon#about to read 6, iclass 12, count 0 2006.197.08:07:58.23#ibcon#read 6, iclass 12, count 0 2006.197.08:07:58.23#ibcon#end of sib2, iclass 12, count 0 2006.197.08:07:58.23#ibcon#*after write, iclass 12, count 0 2006.197.08:07:58.23#ibcon#*before return 0, iclass 12, count 0 2006.197.08:07:58.23#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.197.08:07:58.23#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.197.08:07:58.23#ibcon#about to clear, iclass 12 cls_cnt 0 2006.197.08:07:58.23#ibcon#cleared, iclass 12 cls_cnt 0 2006.197.08:07:58.23$vc4f8/valo=2,572.99 2006.197.08:07:58.23#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.197.08:07:58.23#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.197.08:07:58.23#ibcon#ireg 17 cls_cnt 0 2006.197.08:07:58.23#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.197.08:07:58.23#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.197.08:07:58.23#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.197.08:07:58.23#ibcon#enter wrdev, iclass 14, count 0 2006.197.08:07:58.23#ibcon#first serial, iclass 14, count 0 2006.197.08:07:58.23#ibcon#enter sib2, iclass 14, count 0 2006.197.08:07:58.23#ibcon#flushed, iclass 14, count 0 2006.197.08:07:58.23#ibcon#about to write, iclass 14, count 0 2006.197.08:07:58.23#ibcon#wrote, iclass 14, count 0 2006.197.08:07:58.23#ibcon#about to read 3, iclass 14, count 0 2006.197.08:07:58.25#ibcon#read 3, iclass 14, count 0 2006.197.08:07:58.25#ibcon#about to read 4, iclass 14, count 0 2006.197.08:07:58.25#ibcon#read 4, iclass 14, count 0 2006.197.08:07:58.25#ibcon#about to read 5, iclass 14, count 0 2006.197.08:07:58.25#ibcon#read 5, iclass 14, count 0 2006.197.08:07:58.25#ibcon#about to read 6, iclass 14, count 0 2006.197.08:07:58.25#ibcon#read 6, iclass 14, count 0 2006.197.08:07:58.25#ibcon#end of sib2, iclass 14, count 0 2006.197.08:07:58.25#ibcon#*mode == 0, iclass 14, count 0 2006.197.08:07:58.25#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.197.08:07:58.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.197.08:07:58.25#ibcon#*before write, iclass 14, count 0 2006.197.08:07:58.25#ibcon#enter sib2, iclass 14, count 0 2006.197.08:07:58.25#ibcon#flushed, iclass 14, count 0 2006.197.08:07:58.25#ibcon#about to write, iclass 14, count 0 2006.197.08:07:58.25#ibcon#wrote, iclass 14, count 0 2006.197.08:07:58.25#ibcon#about to read 3, iclass 14, count 0 2006.197.08:07:58.29#ibcon#read 3, iclass 14, count 0 2006.197.08:07:58.29#ibcon#about to read 4, iclass 14, count 0 2006.197.08:07:58.29#ibcon#read 4, iclass 14, count 0 2006.197.08:07:58.29#ibcon#about to read 5, iclass 14, count 0 2006.197.08:07:58.29#ibcon#read 5, iclass 14, count 0 2006.197.08:07:58.29#ibcon#about to read 6, iclass 14, count 0 2006.197.08:07:58.29#ibcon#read 6, iclass 14, count 0 2006.197.08:07:58.29#ibcon#end of sib2, iclass 14, count 0 2006.197.08:07:58.29#ibcon#*after write, iclass 14, count 0 2006.197.08:07:58.29#ibcon#*before return 0, iclass 14, count 0 2006.197.08:07:58.29#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.197.08:07:58.29#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.197.08:07:58.29#ibcon#about to clear, iclass 14 cls_cnt 0 2006.197.08:07:58.29#ibcon#cleared, iclass 14 cls_cnt 0 2006.197.08:07:58.29$vc4f8/va=2,7 2006.197.08:07:58.29#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.197.08:07:58.29#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.197.08:07:58.29#ibcon#ireg 11 cls_cnt 2 2006.197.08:07:58.29#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.197.08:07:58.35#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.197.08:07:58.35#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.197.08:07:58.35#ibcon#enter wrdev, iclass 16, count 2 2006.197.08:07:58.35#ibcon#first serial, iclass 16, count 2 2006.197.08:07:58.35#ibcon#enter sib2, iclass 16, count 2 2006.197.08:07:58.35#ibcon#flushed, iclass 16, count 2 2006.197.08:07:58.35#ibcon#about to write, iclass 16, count 2 2006.197.08:07:58.35#ibcon#wrote, iclass 16, count 2 2006.197.08:07:58.35#ibcon#about to read 3, iclass 16, count 2 2006.197.08:07:58.37#ibcon#read 3, iclass 16, count 2 2006.197.08:07:58.37#ibcon#about to read 4, iclass 16, count 2 2006.197.08:07:58.37#ibcon#read 4, iclass 16, count 2 2006.197.08:07:58.37#ibcon#about to read 5, iclass 16, count 2 2006.197.08:07:58.37#ibcon#read 5, iclass 16, count 2 2006.197.08:07:58.37#ibcon#about to read 6, iclass 16, count 2 2006.197.08:07:58.37#ibcon#read 6, iclass 16, count 2 2006.197.08:07:58.37#ibcon#end of sib2, iclass 16, count 2 2006.197.08:07:58.37#ibcon#*mode == 0, iclass 16, count 2 2006.197.08:07:58.37#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.197.08:07:58.37#ibcon#[25=AT02-07\r\n] 2006.197.08:07:58.37#ibcon#*before write, iclass 16, count 2 2006.197.08:07:58.37#ibcon#enter sib2, iclass 16, count 2 2006.197.08:07:58.37#ibcon#flushed, iclass 16, count 2 2006.197.08:07:58.37#ibcon#about to write, iclass 16, count 2 2006.197.08:07:58.37#ibcon#wrote, iclass 16, count 2 2006.197.08:07:58.37#ibcon#about to read 3, iclass 16, count 2 2006.197.08:07:58.40#ibcon#read 3, iclass 16, count 2 2006.197.08:07:58.40#ibcon#about to read 4, iclass 16, count 2 2006.197.08:07:58.40#ibcon#read 4, iclass 16, count 2 2006.197.08:07:58.40#ibcon#about to read 5, iclass 16, count 2 2006.197.08:07:58.40#ibcon#read 5, iclass 16, count 2 2006.197.08:07:58.40#ibcon#about to read 6, iclass 16, count 2 2006.197.08:07:58.40#ibcon#read 6, iclass 16, count 2 2006.197.08:07:58.40#ibcon#end of sib2, iclass 16, count 2 2006.197.08:07:58.40#ibcon#*after write, iclass 16, count 2 2006.197.08:07:58.40#ibcon#*before return 0, iclass 16, count 2 2006.197.08:07:58.40#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.197.08:07:58.40#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.197.08:07:58.40#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.197.08:07:58.40#ibcon#ireg 7 cls_cnt 0 2006.197.08:07:58.40#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.197.08:07:58.52#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.197.08:07:58.52#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.197.08:07:58.52#ibcon#enter wrdev, iclass 16, count 0 2006.197.08:07:58.52#ibcon#first serial, iclass 16, count 0 2006.197.08:07:58.52#ibcon#enter sib2, iclass 16, count 0 2006.197.08:07:58.52#ibcon#flushed, iclass 16, count 0 2006.197.08:07:58.52#ibcon#about to write, iclass 16, count 0 2006.197.08:07:58.52#ibcon#wrote, iclass 16, count 0 2006.197.08:07:58.52#ibcon#about to read 3, iclass 16, count 0 2006.197.08:07:58.54#ibcon#read 3, iclass 16, count 0 2006.197.08:07:58.54#ibcon#about to read 4, iclass 16, count 0 2006.197.08:07:58.54#ibcon#read 4, iclass 16, count 0 2006.197.08:07:58.54#ibcon#about to read 5, iclass 16, count 0 2006.197.08:07:58.54#ibcon#read 5, iclass 16, count 0 2006.197.08:07:58.54#ibcon#about to read 6, iclass 16, count 0 2006.197.08:07:58.54#ibcon#read 6, iclass 16, count 0 2006.197.08:07:58.54#ibcon#end of sib2, iclass 16, count 0 2006.197.08:07:58.54#ibcon#*mode == 0, iclass 16, count 0 2006.197.08:07:58.54#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.197.08:07:58.54#ibcon#[25=USB\r\n] 2006.197.08:07:58.54#ibcon#*before write, iclass 16, count 0 2006.197.08:07:58.54#ibcon#enter sib2, iclass 16, count 0 2006.197.08:07:58.54#ibcon#flushed, iclass 16, count 0 2006.197.08:07:58.54#ibcon#about to write, iclass 16, count 0 2006.197.08:07:58.54#ibcon#wrote, iclass 16, count 0 2006.197.08:07:58.54#ibcon#about to read 3, iclass 16, count 0 2006.197.08:07:58.55#abcon#{5=INTERFACE CLEAR} 2006.197.08:07:58.57#ibcon#read 3, iclass 16, count 0 2006.197.08:07:58.57#ibcon#about to read 4, iclass 16, count 0 2006.197.08:07:58.57#ibcon#read 4, iclass 16, count 0 2006.197.08:07:58.57#ibcon#about to read 5, iclass 16, count 0 2006.197.08:07:58.57#ibcon#read 5, iclass 16, count 0 2006.197.08:07:58.57#ibcon#about to read 6, iclass 16, count 0 2006.197.08:07:58.57#ibcon#read 6, iclass 16, count 0 2006.197.08:07:58.57#ibcon#end of sib2, iclass 16, count 0 2006.197.08:07:58.57#ibcon#*after write, iclass 16, count 0 2006.197.08:07:58.57#ibcon#*before return 0, iclass 16, count 0 2006.197.08:07:58.57#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.197.08:07:58.57#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.197.08:07:58.57#ibcon#about to clear, iclass 16 cls_cnt 0 2006.197.08:07:58.57#ibcon#cleared, iclass 16 cls_cnt 0 2006.197.08:07:58.57$vc4f8/valo=3,672.99 2006.197.08:07:58.57#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.197.08:07:58.57#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.197.08:07:58.57#ibcon#ireg 17 cls_cnt 0 2006.197.08:07:58.57#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.197.08:07:58.57#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.197.08:07:58.57#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.197.08:07:58.57#ibcon#enter wrdev, iclass 19, count 0 2006.197.08:07:58.57#ibcon#first serial, iclass 19, count 0 2006.197.08:07:58.57#ibcon#enter sib2, iclass 19, count 0 2006.197.08:07:58.57#ibcon#flushed, iclass 19, count 0 2006.197.08:07:58.57#ibcon#about to write, iclass 19, count 0 2006.197.08:07:58.57#ibcon#wrote, iclass 19, count 0 2006.197.08:07:58.57#ibcon#about to read 3, iclass 19, count 0 2006.197.08:07:58.59#ibcon#read 3, iclass 19, count 0 2006.197.08:07:58.59#ibcon#about to read 4, iclass 19, count 0 2006.197.08:07:58.59#ibcon#read 4, iclass 19, count 0 2006.197.08:07:58.59#ibcon#about to read 5, iclass 19, count 0 2006.197.08:07:58.59#ibcon#read 5, iclass 19, count 0 2006.197.08:07:58.59#ibcon#about to read 6, iclass 19, count 0 2006.197.08:07:58.59#ibcon#read 6, iclass 19, count 0 2006.197.08:07:58.59#ibcon#end of sib2, iclass 19, count 0 2006.197.08:07:58.59#ibcon#*mode == 0, iclass 19, count 0 2006.197.08:07:58.59#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.197.08:07:58.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.197.08:07:58.59#ibcon#*before write, iclass 19, count 0 2006.197.08:07:58.59#ibcon#enter sib2, iclass 19, count 0 2006.197.08:07:58.59#ibcon#flushed, iclass 19, count 0 2006.197.08:07:58.59#ibcon#about to write, iclass 19, count 0 2006.197.08:07:58.59#ibcon#wrote, iclass 19, count 0 2006.197.08:07:58.59#ibcon#about to read 3, iclass 19, count 0 2006.197.08:07:58.61#abcon#[5=S1D000X0/0*\r\n] 2006.197.08:07:58.63#ibcon#read 3, iclass 19, count 0 2006.197.08:07:58.63#ibcon#about to read 4, iclass 19, count 0 2006.197.08:07:58.63#ibcon#read 4, iclass 19, count 0 2006.197.08:07:58.63#ibcon#about to read 5, iclass 19, count 0 2006.197.08:07:58.63#ibcon#read 5, iclass 19, count 0 2006.197.08:07:58.63#ibcon#about to read 6, iclass 19, count 0 2006.197.08:07:58.63#ibcon#read 6, iclass 19, count 0 2006.197.08:07:58.63#ibcon#end of sib2, iclass 19, count 0 2006.197.08:07:58.63#ibcon#*after write, iclass 19, count 0 2006.197.08:07:58.63#ibcon#*before return 0, iclass 19, count 0 2006.197.08:07:58.63#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.197.08:07:58.63#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.197.08:07:58.63#ibcon#about to clear, iclass 19 cls_cnt 0 2006.197.08:07:58.63#ibcon#cleared, iclass 19 cls_cnt 0 2006.197.08:07:58.63$vc4f8/va=3,6 2006.197.08:07:58.63#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.197.08:07:58.63#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.197.08:07:58.63#ibcon#ireg 11 cls_cnt 2 2006.197.08:07:58.63#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.197.08:07:58.69#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.197.08:07:58.69#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.197.08:07:58.69#ibcon#enter wrdev, iclass 22, count 2 2006.197.08:07:58.69#ibcon#first serial, iclass 22, count 2 2006.197.08:07:58.69#ibcon#enter sib2, iclass 22, count 2 2006.197.08:07:58.69#ibcon#flushed, iclass 22, count 2 2006.197.08:07:58.69#ibcon#about to write, iclass 22, count 2 2006.197.08:07:58.69#ibcon#wrote, iclass 22, count 2 2006.197.08:07:58.69#ibcon#about to read 3, iclass 22, count 2 2006.197.08:07:58.71#ibcon#read 3, iclass 22, count 2 2006.197.08:07:58.71#ibcon#about to read 4, iclass 22, count 2 2006.197.08:07:58.71#ibcon#read 4, iclass 22, count 2 2006.197.08:07:58.71#ibcon#about to read 5, iclass 22, count 2 2006.197.08:07:58.71#ibcon#read 5, iclass 22, count 2 2006.197.08:07:58.71#ibcon#about to read 6, iclass 22, count 2 2006.197.08:07:58.71#ibcon#read 6, iclass 22, count 2 2006.197.08:07:58.71#ibcon#end of sib2, iclass 22, count 2 2006.197.08:07:58.71#ibcon#*mode == 0, iclass 22, count 2 2006.197.08:07:58.71#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.197.08:07:58.71#ibcon#[25=AT03-06\r\n] 2006.197.08:07:58.71#ibcon#*before write, iclass 22, count 2 2006.197.08:07:58.71#ibcon#enter sib2, iclass 22, count 2 2006.197.08:07:58.71#ibcon#flushed, iclass 22, count 2 2006.197.08:07:58.71#ibcon#about to write, iclass 22, count 2 2006.197.08:07:58.71#ibcon#wrote, iclass 22, count 2 2006.197.08:07:58.71#ibcon#about to read 3, iclass 22, count 2 2006.197.08:07:58.74#ibcon#read 3, iclass 22, count 2 2006.197.08:07:58.74#ibcon#about to read 4, iclass 22, count 2 2006.197.08:07:58.74#ibcon#read 4, iclass 22, count 2 2006.197.08:07:58.74#ibcon#about to read 5, iclass 22, count 2 2006.197.08:07:58.74#ibcon#read 5, iclass 22, count 2 2006.197.08:07:58.74#ibcon#about to read 6, iclass 22, count 2 2006.197.08:07:58.74#ibcon#read 6, iclass 22, count 2 2006.197.08:07:58.74#ibcon#end of sib2, iclass 22, count 2 2006.197.08:07:58.74#ibcon#*after write, iclass 22, count 2 2006.197.08:07:58.74#ibcon#*before return 0, iclass 22, count 2 2006.197.08:07:58.74#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.197.08:07:58.74#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.197.08:07:58.74#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.197.08:07:58.74#ibcon#ireg 7 cls_cnt 0 2006.197.08:07:58.74#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.197.08:07:58.86#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.197.08:07:58.86#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.197.08:07:58.86#ibcon#enter wrdev, iclass 22, count 0 2006.197.08:07:58.86#ibcon#first serial, iclass 22, count 0 2006.197.08:07:58.86#ibcon#enter sib2, iclass 22, count 0 2006.197.08:07:58.86#ibcon#flushed, iclass 22, count 0 2006.197.08:07:58.86#ibcon#about to write, iclass 22, count 0 2006.197.08:07:58.86#ibcon#wrote, iclass 22, count 0 2006.197.08:07:58.86#ibcon#about to read 3, iclass 22, count 0 2006.197.08:07:58.88#ibcon#read 3, iclass 22, count 0 2006.197.08:07:58.88#ibcon#about to read 4, iclass 22, count 0 2006.197.08:07:58.88#ibcon#read 4, iclass 22, count 0 2006.197.08:07:58.88#ibcon#about to read 5, iclass 22, count 0 2006.197.08:07:58.88#ibcon#read 5, iclass 22, count 0 2006.197.08:07:58.88#ibcon#about to read 6, iclass 22, count 0 2006.197.08:07:58.88#ibcon#read 6, iclass 22, count 0 2006.197.08:07:58.88#ibcon#end of sib2, iclass 22, count 0 2006.197.08:07:58.88#ibcon#*mode == 0, iclass 22, count 0 2006.197.08:07:58.88#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.197.08:07:58.88#ibcon#[25=USB\r\n] 2006.197.08:07:58.88#ibcon#*before write, iclass 22, count 0 2006.197.08:07:58.88#ibcon#enter sib2, iclass 22, count 0 2006.197.08:07:58.88#ibcon#flushed, iclass 22, count 0 2006.197.08:07:58.88#ibcon#about to write, iclass 22, count 0 2006.197.08:07:58.88#ibcon#wrote, iclass 22, count 0 2006.197.08:07:58.88#ibcon#about to read 3, iclass 22, count 0 2006.197.08:07:58.91#ibcon#read 3, iclass 22, count 0 2006.197.08:07:58.91#ibcon#about to read 4, iclass 22, count 0 2006.197.08:07:58.91#ibcon#read 4, iclass 22, count 0 2006.197.08:07:58.91#ibcon#about to read 5, iclass 22, count 0 2006.197.08:07:58.91#ibcon#read 5, iclass 22, count 0 2006.197.08:07:58.91#ibcon#about to read 6, iclass 22, count 0 2006.197.08:07:58.91#ibcon#read 6, iclass 22, count 0 2006.197.08:07:58.91#ibcon#end of sib2, iclass 22, count 0 2006.197.08:07:58.91#ibcon#*after write, iclass 22, count 0 2006.197.08:07:58.91#ibcon#*before return 0, iclass 22, count 0 2006.197.08:07:58.91#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.197.08:07:58.91#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.197.08:07:58.91#ibcon#about to clear, iclass 22 cls_cnt 0 2006.197.08:07:58.91#ibcon#cleared, iclass 22 cls_cnt 0 2006.197.08:07:58.91$vc4f8/valo=4,832.99 2006.197.08:07:58.91#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.197.08:07:58.91#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.197.08:07:58.91#ibcon#ireg 17 cls_cnt 0 2006.197.08:07:58.91#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.197.08:07:58.91#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.197.08:07:58.91#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.197.08:07:58.91#ibcon#enter wrdev, iclass 24, count 0 2006.197.08:07:58.91#ibcon#first serial, iclass 24, count 0 2006.197.08:07:58.91#ibcon#enter sib2, iclass 24, count 0 2006.197.08:07:58.91#ibcon#flushed, iclass 24, count 0 2006.197.08:07:58.91#ibcon#about to write, iclass 24, count 0 2006.197.08:07:58.91#ibcon#wrote, iclass 24, count 0 2006.197.08:07:58.91#ibcon#about to read 3, iclass 24, count 0 2006.197.08:07:58.93#ibcon#read 3, iclass 24, count 0 2006.197.08:07:58.93#ibcon#about to read 4, iclass 24, count 0 2006.197.08:07:58.93#ibcon#read 4, iclass 24, count 0 2006.197.08:07:58.93#ibcon#about to read 5, iclass 24, count 0 2006.197.08:07:58.93#ibcon#read 5, iclass 24, count 0 2006.197.08:07:58.93#ibcon#about to read 6, iclass 24, count 0 2006.197.08:07:58.93#ibcon#read 6, iclass 24, count 0 2006.197.08:07:58.93#ibcon#end of sib2, iclass 24, count 0 2006.197.08:07:58.93#ibcon#*mode == 0, iclass 24, count 0 2006.197.08:07:58.93#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.197.08:07:58.93#ibcon#[26=FRQ=04,832.99\r\n] 2006.197.08:07:58.93#ibcon#*before write, iclass 24, count 0 2006.197.08:07:58.93#ibcon#enter sib2, iclass 24, count 0 2006.197.08:07:58.93#ibcon#flushed, iclass 24, count 0 2006.197.08:07:58.93#ibcon#about to write, iclass 24, count 0 2006.197.08:07:58.93#ibcon#wrote, iclass 24, count 0 2006.197.08:07:58.93#ibcon#about to read 3, iclass 24, count 0 2006.197.08:07:58.97#ibcon#read 3, iclass 24, count 0 2006.197.08:07:58.97#ibcon#about to read 4, iclass 24, count 0 2006.197.08:07:58.97#ibcon#read 4, iclass 24, count 0 2006.197.08:07:58.97#ibcon#about to read 5, iclass 24, count 0 2006.197.08:07:58.97#ibcon#read 5, iclass 24, count 0 2006.197.08:07:58.97#ibcon#about to read 6, iclass 24, count 0 2006.197.08:07:58.97#ibcon#read 6, iclass 24, count 0 2006.197.08:07:58.97#ibcon#end of sib2, iclass 24, count 0 2006.197.08:07:58.97#ibcon#*after write, iclass 24, count 0 2006.197.08:07:58.97#ibcon#*before return 0, iclass 24, count 0 2006.197.08:07:58.97#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.197.08:07:58.97#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.197.08:07:58.97#ibcon#about to clear, iclass 24 cls_cnt 0 2006.197.08:07:58.97#ibcon#cleared, iclass 24 cls_cnt 0 2006.197.08:07:58.97$vc4f8/va=4,7 2006.197.08:07:58.97#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.197.08:07:58.97#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.197.08:07:58.97#ibcon#ireg 11 cls_cnt 2 2006.197.08:07:58.97#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.197.08:07:59.03#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.197.08:07:59.03#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.197.08:07:59.03#ibcon#enter wrdev, iclass 26, count 2 2006.197.08:07:59.03#ibcon#first serial, iclass 26, count 2 2006.197.08:07:59.03#ibcon#enter sib2, iclass 26, count 2 2006.197.08:07:59.03#ibcon#flushed, iclass 26, count 2 2006.197.08:07:59.03#ibcon#about to write, iclass 26, count 2 2006.197.08:07:59.03#ibcon#wrote, iclass 26, count 2 2006.197.08:07:59.03#ibcon#about to read 3, iclass 26, count 2 2006.197.08:07:59.05#ibcon#read 3, iclass 26, count 2 2006.197.08:07:59.05#ibcon#about to read 4, iclass 26, count 2 2006.197.08:07:59.05#ibcon#read 4, iclass 26, count 2 2006.197.08:07:59.05#ibcon#about to read 5, iclass 26, count 2 2006.197.08:07:59.05#ibcon#read 5, iclass 26, count 2 2006.197.08:07:59.05#ibcon#about to read 6, iclass 26, count 2 2006.197.08:07:59.05#ibcon#read 6, iclass 26, count 2 2006.197.08:07:59.05#ibcon#end of sib2, iclass 26, count 2 2006.197.08:07:59.05#ibcon#*mode == 0, iclass 26, count 2 2006.197.08:07:59.05#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.197.08:07:59.05#ibcon#[25=AT04-07\r\n] 2006.197.08:07:59.05#ibcon#*before write, iclass 26, count 2 2006.197.08:07:59.05#ibcon#enter sib2, iclass 26, count 2 2006.197.08:07:59.05#ibcon#flushed, iclass 26, count 2 2006.197.08:07:59.05#ibcon#about to write, iclass 26, count 2 2006.197.08:07:59.05#ibcon#wrote, iclass 26, count 2 2006.197.08:07:59.05#ibcon#about to read 3, iclass 26, count 2 2006.197.08:07:59.08#ibcon#read 3, iclass 26, count 2 2006.197.08:07:59.08#ibcon#about to read 4, iclass 26, count 2 2006.197.08:07:59.08#ibcon#read 4, iclass 26, count 2 2006.197.08:07:59.08#ibcon#about to read 5, iclass 26, count 2 2006.197.08:07:59.08#ibcon#read 5, iclass 26, count 2 2006.197.08:07:59.08#ibcon#about to read 6, iclass 26, count 2 2006.197.08:07:59.08#ibcon#read 6, iclass 26, count 2 2006.197.08:07:59.08#ibcon#end of sib2, iclass 26, count 2 2006.197.08:07:59.08#ibcon#*after write, iclass 26, count 2 2006.197.08:07:59.08#ibcon#*before return 0, iclass 26, count 2 2006.197.08:07:59.08#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.197.08:07:59.08#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.197.08:07:59.08#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.197.08:07:59.08#ibcon#ireg 7 cls_cnt 0 2006.197.08:07:59.08#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.197.08:07:59.20#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.197.08:07:59.20#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.197.08:07:59.20#ibcon#enter wrdev, iclass 26, count 0 2006.197.08:07:59.20#ibcon#first serial, iclass 26, count 0 2006.197.08:07:59.20#ibcon#enter sib2, iclass 26, count 0 2006.197.08:07:59.20#ibcon#flushed, iclass 26, count 0 2006.197.08:07:59.20#ibcon#about to write, iclass 26, count 0 2006.197.08:07:59.20#ibcon#wrote, iclass 26, count 0 2006.197.08:07:59.20#ibcon#about to read 3, iclass 26, count 0 2006.197.08:07:59.22#ibcon#read 3, iclass 26, count 0 2006.197.08:07:59.22#ibcon#about to read 4, iclass 26, count 0 2006.197.08:07:59.22#ibcon#read 4, iclass 26, count 0 2006.197.08:07:59.22#ibcon#about to read 5, iclass 26, count 0 2006.197.08:07:59.22#ibcon#read 5, iclass 26, count 0 2006.197.08:07:59.22#ibcon#about to read 6, iclass 26, count 0 2006.197.08:07:59.22#ibcon#read 6, iclass 26, count 0 2006.197.08:07:59.22#ibcon#end of sib2, iclass 26, count 0 2006.197.08:07:59.22#ibcon#*mode == 0, iclass 26, count 0 2006.197.08:07:59.22#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.197.08:07:59.22#ibcon#[25=USB\r\n] 2006.197.08:07:59.22#ibcon#*before write, iclass 26, count 0 2006.197.08:07:59.22#ibcon#enter sib2, iclass 26, count 0 2006.197.08:07:59.22#ibcon#flushed, iclass 26, count 0 2006.197.08:07:59.22#ibcon#about to write, iclass 26, count 0 2006.197.08:07:59.22#ibcon#wrote, iclass 26, count 0 2006.197.08:07:59.22#ibcon#about to read 3, iclass 26, count 0 2006.197.08:07:59.25#ibcon#read 3, iclass 26, count 0 2006.197.08:07:59.25#ibcon#about to read 4, iclass 26, count 0 2006.197.08:07:59.25#ibcon#read 4, iclass 26, count 0 2006.197.08:07:59.25#ibcon#about to read 5, iclass 26, count 0 2006.197.08:07:59.25#ibcon#read 5, iclass 26, count 0 2006.197.08:07:59.25#ibcon#about to read 6, iclass 26, count 0 2006.197.08:07:59.25#ibcon#read 6, iclass 26, count 0 2006.197.08:07:59.25#ibcon#end of sib2, iclass 26, count 0 2006.197.08:07:59.25#ibcon#*after write, iclass 26, count 0 2006.197.08:07:59.25#ibcon#*before return 0, iclass 26, count 0 2006.197.08:07:59.25#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.197.08:07:59.25#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.197.08:07:59.25#ibcon#about to clear, iclass 26 cls_cnt 0 2006.197.08:07:59.25#ibcon#cleared, iclass 26 cls_cnt 0 2006.197.08:07:59.25$vc4f8/valo=5,652.99 2006.197.08:07:59.25#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.197.08:07:59.25#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.197.08:07:59.25#ibcon#ireg 17 cls_cnt 0 2006.197.08:07:59.25#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.197.08:07:59.25#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.197.08:07:59.25#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.197.08:07:59.25#ibcon#enter wrdev, iclass 28, count 0 2006.197.08:07:59.25#ibcon#first serial, iclass 28, count 0 2006.197.08:07:59.25#ibcon#enter sib2, iclass 28, count 0 2006.197.08:07:59.25#ibcon#flushed, iclass 28, count 0 2006.197.08:07:59.25#ibcon#about to write, iclass 28, count 0 2006.197.08:07:59.25#ibcon#wrote, iclass 28, count 0 2006.197.08:07:59.25#ibcon#about to read 3, iclass 28, count 0 2006.197.08:07:59.27#ibcon#read 3, iclass 28, count 0 2006.197.08:07:59.27#ibcon#about to read 4, iclass 28, count 0 2006.197.08:07:59.27#ibcon#read 4, iclass 28, count 0 2006.197.08:07:59.27#ibcon#about to read 5, iclass 28, count 0 2006.197.08:07:59.27#ibcon#read 5, iclass 28, count 0 2006.197.08:07:59.27#ibcon#about to read 6, iclass 28, count 0 2006.197.08:07:59.27#ibcon#read 6, iclass 28, count 0 2006.197.08:07:59.27#ibcon#end of sib2, iclass 28, count 0 2006.197.08:07:59.27#ibcon#*mode == 0, iclass 28, count 0 2006.197.08:07:59.27#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.197.08:07:59.27#ibcon#[26=FRQ=05,652.99\r\n] 2006.197.08:07:59.27#ibcon#*before write, iclass 28, count 0 2006.197.08:07:59.27#ibcon#enter sib2, iclass 28, count 0 2006.197.08:07:59.27#ibcon#flushed, iclass 28, count 0 2006.197.08:07:59.27#ibcon#about to write, iclass 28, count 0 2006.197.08:07:59.27#ibcon#wrote, iclass 28, count 0 2006.197.08:07:59.27#ibcon#about to read 3, iclass 28, count 0 2006.197.08:07:59.31#ibcon#read 3, iclass 28, count 0 2006.197.08:07:59.31#ibcon#about to read 4, iclass 28, count 0 2006.197.08:07:59.31#ibcon#read 4, iclass 28, count 0 2006.197.08:07:59.31#ibcon#about to read 5, iclass 28, count 0 2006.197.08:07:59.31#ibcon#read 5, iclass 28, count 0 2006.197.08:07:59.31#ibcon#about to read 6, iclass 28, count 0 2006.197.08:07:59.31#ibcon#read 6, iclass 28, count 0 2006.197.08:07:59.31#ibcon#end of sib2, iclass 28, count 0 2006.197.08:07:59.31#ibcon#*after write, iclass 28, count 0 2006.197.08:07:59.31#ibcon#*before return 0, iclass 28, count 0 2006.197.08:07:59.31#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.197.08:07:59.31#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.197.08:07:59.31#ibcon#about to clear, iclass 28 cls_cnt 0 2006.197.08:07:59.31#ibcon#cleared, iclass 28 cls_cnt 0 2006.197.08:07:59.31$vc4f8/va=5,7 2006.197.08:07:59.31#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.197.08:07:59.31#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.197.08:07:59.31#ibcon#ireg 11 cls_cnt 2 2006.197.08:07:59.31#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.197.08:07:59.37#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.197.08:07:59.37#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.197.08:07:59.37#ibcon#enter wrdev, iclass 30, count 2 2006.197.08:07:59.37#ibcon#first serial, iclass 30, count 2 2006.197.08:07:59.37#ibcon#enter sib2, iclass 30, count 2 2006.197.08:07:59.37#ibcon#flushed, iclass 30, count 2 2006.197.08:07:59.37#ibcon#about to write, iclass 30, count 2 2006.197.08:07:59.37#ibcon#wrote, iclass 30, count 2 2006.197.08:07:59.37#ibcon#about to read 3, iclass 30, count 2 2006.197.08:07:59.39#ibcon#read 3, iclass 30, count 2 2006.197.08:07:59.39#ibcon#about to read 4, iclass 30, count 2 2006.197.08:07:59.39#ibcon#read 4, iclass 30, count 2 2006.197.08:07:59.39#ibcon#about to read 5, iclass 30, count 2 2006.197.08:07:59.39#ibcon#read 5, iclass 30, count 2 2006.197.08:07:59.39#ibcon#about to read 6, iclass 30, count 2 2006.197.08:07:59.39#ibcon#read 6, iclass 30, count 2 2006.197.08:07:59.39#ibcon#end of sib2, iclass 30, count 2 2006.197.08:07:59.39#ibcon#*mode == 0, iclass 30, count 2 2006.197.08:07:59.39#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.197.08:07:59.39#ibcon#[25=AT05-07\r\n] 2006.197.08:07:59.39#ibcon#*before write, iclass 30, count 2 2006.197.08:07:59.39#ibcon#enter sib2, iclass 30, count 2 2006.197.08:07:59.39#ibcon#flushed, iclass 30, count 2 2006.197.08:07:59.39#ibcon#about to write, iclass 30, count 2 2006.197.08:07:59.39#ibcon#wrote, iclass 30, count 2 2006.197.08:07:59.39#ibcon#about to read 3, iclass 30, count 2 2006.197.08:07:59.42#ibcon#read 3, iclass 30, count 2 2006.197.08:07:59.42#ibcon#about to read 4, iclass 30, count 2 2006.197.08:07:59.42#ibcon#read 4, iclass 30, count 2 2006.197.08:07:59.42#ibcon#about to read 5, iclass 30, count 2 2006.197.08:07:59.42#ibcon#read 5, iclass 30, count 2 2006.197.08:07:59.42#ibcon#about to read 6, iclass 30, count 2 2006.197.08:07:59.42#ibcon#read 6, iclass 30, count 2 2006.197.08:07:59.42#ibcon#end of sib2, iclass 30, count 2 2006.197.08:07:59.42#ibcon#*after write, iclass 30, count 2 2006.197.08:07:59.42#ibcon#*before return 0, iclass 30, count 2 2006.197.08:07:59.42#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.197.08:07:59.42#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.197.08:07:59.42#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.197.08:07:59.42#ibcon#ireg 7 cls_cnt 0 2006.197.08:07:59.42#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.197.08:07:59.54#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.197.08:07:59.54#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.197.08:07:59.54#ibcon#enter wrdev, iclass 30, count 0 2006.197.08:07:59.54#ibcon#first serial, iclass 30, count 0 2006.197.08:07:59.54#ibcon#enter sib2, iclass 30, count 0 2006.197.08:07:59.54#ibcon#flushed, iclass 30, count 0 2006.197.08:07:59.54#ibcon#about to write, iclass 30, count 0 2006.197.08:07:59.54#ibcon#wrote, iclass 30, count 0 2006.197.08:07:59.54#ibcon#about to read 3, iclass 30, count 0 2006.197.08:07:59.56#ibcon#read 3, iclass 30, count 0 2006.197.08:07:59.56#ibcon#about to read 4, iclass 30, count 0 2006.197.08:07:59.56#ibcon#read 4, iclass 30, count 0 2006.197.08:07:59.56#ibcon#about to read 5, iclass 30, count 0 2006.197.08:07:59.56#ibcon#read 5, iclass 30, count 0 2006.197.08:07:59.56#ibcon#about to read 6, iclass 30, count 0 2006.197.08:07:59.56#ibcon#read 6, iclass 30, count 0 2006.197.08:07:59.56#ibcon#end of sib2, iclass 30, count 0 2006.197.08:07:59.56#ibcon#*mode == 0, iclass 30, count 0 2006.197.08:07:59.56#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.197.08:07:59.56#ibcon#[25=USB\r\n] 2006.197.08:07:59.56#ibcon#*before write, iclass 30, count 0 2006.197.08:07:59.56#ibcon#enter sib2, iclass 30, count 0 2006.197.08:07:59.56#ibcon#flushed, iclass 30, count 0 2006.197.08:07:59.56#ibcon#about to write, iclass 30, count 0 2006.197.08:07:59.56#ibcon#wrote, iclass 30, count 0 2006.197.08:07:59.56#ibcon#about to read 3, iclass 30, count 0 2006.197.08:07:59.59#ibcon#read 3, iclass 30, count 0 2006.197.08:07:59.59#ibcon#about to read 4, iclass 30, count 0 2006.197.08:07:59.59#ibcon#read 4, iclass 30, count 0 2006.197.08:07:59.59#ibcon#about to read 5, iclass 30, count 0 2006.197.08:07:59.59#ibcon#read 5, iclass 30, count 0 2006.197.08:07:59.59#ibcon#about to read 6, iclass 30, count 0 2006.197.08:07:59.59#ibcon#read 6, iclass 30, count 0 2006.197.08:07:59.59#ibcon#end of sib2, iclass 30, count 0 2006.197.08:07:59.59#ibcon#*after write, iclass 30, count 0 2006.197.08:07:59.59#ibcon#*before return 0, iclass 30, count 0 2006.197.08:07:59.59#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.197.08:07:59.59#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.197.08:07:59.59#ibcon#about to clear, iclass 30 cls_cnt 0 2006.197.08:07:59.59#ibcon#cleared, iclass 30 cls_cnt 0 2006.197.08:07:59.59$vc4f8/valo=6,772.99 2006.197.08:07:59.59#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.197.08:07:59.59#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.197.08:07:59.59#ibcon#ireg 17 cls_cnt 0 2006.197.08:07:59.59#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.197.08:07:59.59#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.197.08:07:59.59#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.197.08:07:59.59#ibcon#enter wrdev, iclass 32, count 0 2006.197.08:07:59.59#ibcon#first serial, iclass 32, count 0 2006.197.08:07:59.59#ibcon#enter sib2, iclass 32, count 0 2006.197.08:07:59.59#ibcon#flushed, iclass 32, count 0 2006.197.08:07:59.59#ibcon#about to write, iclass 32, count 0 2006.197.08:07:59.59#ibcon#wrote, iclass 32, count 0 2006.197.08:07:59.59#ibcon#about to read 3, iclass 32, count 0 2006.197.08:07:59.61#ibcon#read 3, iclass 32, count 0 2006.197.08:07:59.61#ibcon#about to read 4, iclass 32, count 0 2006.197.08:07:59.61#ibcon#read 4, iclass 32, count 0 2006.197.08:07:59.61#ibcon#about to read 5, iclass 32, count 0 2006.197.08:07:59.61#ibcon#read 5, iclass 32, count 0 2006.197.08:07:59.61#ibcon#about to read 6, iclass 32, count 0 2006.197.08:07:59.61#ibcon#read 6, iclass 32, count 0 2006.197.08:07:59.61#ibcon#end of sib2, iclass 32, count 0 2006.197.08:07:59.61#ibcon#*mode == 0, iclass 32, count 0 2006.197.08:07:59.61#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.197.08:07:59.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.197.08:07:59.61#ibcon#*before write, iclass 32, count 0 2006.197.08:07:59.61#ibcon#enter sib2, iclass 32, count 0 2006.197.08:07:59.61#ibcon#flushed, iclass 32, count 0 2006.197.08:07:59.61#ibcon#about to write, iclass 32, count 0 2006.197.08:07:59.61#ibcon#wrote, iclass 32, count 0 2006.197.08:07:59.61#ibcon#about to read 3, iclass 32, count 0 2006.197.08:07:59.65#ibcon#read 3, iclass 32, count 0 2006.197.08:07:59.65#ibcon#about to read 4, iclass 32, count 0 2006.197.08:07:59.65#ibcon#read 4, iclass 32, count 0 2006.197.08:07:59.65#ibcon#about to read 5, iclass 32, count 0 2006.197.08:07:59.65#ibcon#read 5, iclass 32, count 0 2006.197.08:07:59.65#ibcon#about to read 6, iclass 32, count 0 2006.197.08:07:59.65#ibcon#read 6, iclass 32, count 0 2006.197.08:07:59.65#ibcon#end of sib2, iclass 32, count 0 2006.197.08:07:59.65#ibcon#*after write, iclass 32, count 0 2006.197.08:07:59.65#ibcon#*before return 0, iclass 32, count 0 2006.197.08:07:59.65#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.197.08:07:59.65#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.197.08:07:59.65#ibcon#about to clear, iclass 32 cls_cnt 0 2006.197.08:07:59.65#ibcon#cleared, iclass 32 cls_cnt 0 2006.197.08:07:59.65$vc4f8/va=6,6 2006.197.08:07:59.65#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.197.08:07:59.65#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.197.08:07:59.65#ibcon#ireg 11 cls_cnt 2 2006.197.08:07:59.65#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.197.08:07:59.71#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.197.08:07:59.71#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.197.08:07:59.71#ibcon#enter wrdev, iclass 34, count 2 2006.197.08:07:59.71#ibcon#first serial, iclass 34, count 2 2006.197.08:07:59.71#ibcon#enter sib2, iclass 34, count 2 2006.197.08:07:59.71#ibcon#flushed, iclass 34, count 2 2006.197.08:07:59.71#ibcon#about to write, iclass 34, count 2 2006.197.08:07:59.71#ibcon#wrote, iclass 34, count 2 2006.197.08:07:59.71#ibcon#about to read 3, iclass 34, count 2 2006.197.08:07:59.73#ibcon#read 3, iclass 34, count 2 2006.197.08:07:59.73#ibcon#about to read 4, iclass 34, count 2 2006.197.08:07:59.73#ibcon#read 4, iclass 34, count 2 2006.197.08:07:59.73#ibcon#about to read 5, iclass 34, count 2 2006.197.08:07:59.73#ibcon#read 5, iclass 34, count 2 2006.197.08:07:59.73#ibcon#about to read 6, iclass 34, count 2 2006.197.08:07:59.73#ibcon#read 6, iclass 34, count 2 2006.197.08:07:59.73#ibcon#end of sib2, iclass 34, count 2 2006.197.08:07:59.73#ibcon#*mode == 0, iclass 34, count 2 2006.197.08:07:59.73#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.197.08:07:59.73#ibcon#[25=AT06-06\r\n] 2006.197.08:07:59.73#ibcon#*before write, iclass 34, count 2 2006.197.08:07:59.73#ibcon#enter sib2, iclass 34, count 2 2006.197.08:07:59.73#ibcon#flushed, iclass 34, count 2 2006.197.08:07:59.73#ibcon#about to write, iclass 34, count 2 2006.197.08:07:59.73#ibcon#wrote, iclass 34, count 2 2006.197.08:07:59.73#ibcon#about to read 3, iclass 34, count 2 2006.197.08:07:59.76#ibcon#read 3, iclass 34, count 2 2006.197.08:07:59.76#ibcon#about to read 4, iclass 34, count 2 2006.197.08:07:59.76#ibcon#read 4, iclass 34, count 2 2006.197.08:07:59.76#ibcon#about to read 5, iclass 34, count 2 2006.197.08:07:59.76#ibcon#read 5, iclass 34, count 2 2006.197.08:07:59.76#ibcon#about to read 6, iclass 34, count 2 2006.197.08:07:59.76#ibcon#read 6, iclass 34, count 2 2006.197.08:07:59.76#ibcon#end of sib2, iclass 34, count 2 2006.197.08:07:59.76#ibcon#*after write, iclass 34, count 2 2006.197.08:07:59.76#ibcon#*before return 0, iclass 34, count 2 2006.197.08:07:59.76#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.197.08:07:59.76#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.197.08:07:59.76#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.197.08:07:59.76#ibcon#ireg 7 cls_cnt 0 2006.197.08:07:59.76#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.197.08:07:59.88#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.197.08:07:59.88#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.197.08:07:59.88#ibcon#enter wrdev, iclass 34, count 0 2006.197.08:07:59.88#ibcon#first serial, iclass 34, count 0 2006.197.08:07:59.88#ibcon#enter sib2, iclass 34, count 0 2006.197.08:07:59.88#ibcon#flushed, iclass 34, count 0 2006.197.08:07:59.88#ibcon#about to write, iclass 34, count 0 2006.197.08:07:59.88#ibcon#wrote, iclass 34, count 0 2006.197.08:07:59.88#ibcon#about to read 3, iclass 34, count 0 2006.197.08:07:59.90#ibcon#read 3, iclass 34, count 0 2006.197.08:07:59.90#ibcon#about to read 4, iclass 34, count 0 2006.197.08:07:59.90#ibcon#read 4, iclass 34, count 0 2006.197.08:07:59.90#ibcon#about to read 5, iclass 34, count 0 2006.197.08:07:59.90#ibcon#read 5, iclass 34, count 0 2006.197.08:07:59.90#ibcon#about to read 6, iclass 34, count 0 2006.197.08:07:59.90#ibcon#read 6, iclass 34, count 0 2006.197.08:07:59.90#ibcon#end of sib2, iclass 34, count 0 2006.197.08:07:59.90#ibcon#*mode == 0, iclass 34, count 0 2006.197.08:07:59.90#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.197.08:07:59.90#ibcon#[25=USB\r\n] 2006.197.08:07:59.90#ibcon#*before write, iclass 34, count 0 2006.197.08:07:59.90#ibcon#enter sib2, iclass 34, count 0 2006.197.08:07:59.90#ibcon#flushed, iclass 34, count 0 2006.197.08:07:59.90#ibcon#about to write, iclass 34, count 0 2006.197.08:07:59.90#ibcon#wrote, iclass 34, count 0 2006.197.08:07:59.90#ibcon#about to read 3, iclass 34, count 0 2006.197.08:07:59.93#ibcon#read 3, iclass 34, count 0 2006.197.08:07:59.93#ibcon#about to read 4, iclass 34, count 0 2006.197.08:07:59.93#ibcon#read 4, iclass 34, count 0 2006.197.08:07:59.93#ibcon#about to read 5, iclass 34, count 0 2006.197.08:07:59.93#ibcon#read 5, iclass 34, count 0 2006.197.08:07:59.93#ibcon#about to read 6, iclass 34, count 0 2006.197.08:07:59.93#ibcon#read 6, iclass 34, count 0 2006.197.08:07:59.93#ibcon#end of sib2, iclass 34, count 0 2006.197.08:07:59.93#ibcon#*after write, iclass 34, count 0 2006.197.08:07:59.93#ibcon#*before return 0, iclass 34, count 0 2006.197.08:07:59.93#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.197.08:07:59.93#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.197.08:07:59.93#ibcon#about to clear, iclass 34 cls_cnt 0 2006.197.08:07:59.93#ibcon#cleared, iclass 34 cls_cnt 0 2006.197.08:07:59.93$vc4f8/valo=7,832.99 2006.197.08:07:59.93#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.197.08:07:59.93#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.197.08:07:59.93#ibcon#ireg 17 cls_cnt 0 2006.197.08:07:59.93#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.197.08:07:59.93#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.197.08:07:59.93#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.197.08:07:59.93#ibcon#enter wrdev, iclass 36, count 0 2006.197.08:07:59.93#ibcon#first serial, iclass 36, count 0 2006.197.08:07:59.93#ibcon#enter sib2, iclass 36, count 0 2006.197.08:07:59.93#ibcon#flushed, iclass 36, count 0 2006.197.08:07:59.93#ibcon#about to write, iclass 36, count 0 2006.197.08:07:59.93#ibcon#wrote, iclass 36, count 0 2006.197.08:07:59.93#ibcon#about to read 3, iclass 36, count 0 2006.197.08:07:59.95#ibcon#read 3, iclass 36, count 0 2006.197.08:07:59.95#ibcon#about to read 4, iclass 36, count 0 2006.197.08:07:59.95#ibcon#read 4, iclass 36, count 0 2006.197.08:07:59.95#ibcon#about to read 5, iclass 36, count 0 2006.197.08:07:59.95#ibcon#read 5, iclass 36, count 0 2006.197.08:07:59.95#ibcon#about to read 6, iclass 36, count 0 2006.197.08:07:59.95#ibcon#read 6, iclass 36, count 0 2006.197.08:07:59.95#ibcon#end of sib2, iclass 36, count 0 2006.197.08:07:59.95#ibcon#*mode == 0, iclass 36, count 0 2006.197.08:07:59.95#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.197.08:07:59.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.197.08:07:59.95#ibcon#*before write, iclass 36, count 0 2006.197.08:07:59.95#ibcon#enter sib2, iclass 36, count 0 2006.197.08:07:59.95#ibcon#flushed, iclass 36, count 0 2006.197.08:07:59.95#ibcon#about to write, iclass 36, count 0 2006.197.08:07:59.95#ibcon#wrote, iclass 36, count 0 2006.197.08:07:59.95#ibcon#about to read 3, iclass 36, count 0 2006.197.08:07:59.99#ibcon#read 3, iclass 36, count 0 2006.197.08:07:59.99#ibcon#about to read 4, iclass 36, count 0 2006.197.08:07:59.99#ibcon#read 4, iclass 36, count 0 2006.197.08:07:59.99#ibcon#about to read 5, iclass 36, count 0 2006.197.08:07:59.99#ibcon#read 5, iclass 36, count 0 2006.197.08:07:59.99#ibcon#about to read 6, iclass 36, count 0 2006.197.08:07:59.99#ibcon#read 6, iclass 36, count 0 2006.197.08:07:59.99#ibcon#end of sib2, iclass 36, count 0 2006.197.08:07:59.99#ibcon#*after write, iclass 36, count 0 2006.197.08:07:59.99#ibcon#*before return 0, iclass 36, count 0 2006.197.08:07:59.99#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.197.08:07:59.99#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.197.08:07:59.99#ibcon#about to clear, iclass 36 cls_cnt 0 2006.197.08:07:59.99#ibcon#cleared, iclass 36 cls_cnt 0 2006.197.08:07:59.99$vc4f8/va=7,6 2006.197.08:07:59.99#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.197.08:07:59.99#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.197.08:07:59.99#ibcon#ireg 11 cls_cnt 2 2006.197.08:07:59.99#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.197.08:08:00.05#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.197.08:08:00.05#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.197.08:08:00.05#ibcon#enter wrdev, iclass 38, count 2 2006.197.08:08:00.05#ibcon#first serial, iclass 38, count 2 2006.197.08:08:00.05#ibcon#enter sib2, iclass 38, count 2 2006.197.08:08:00.05#ibcon#flushed, iclass 38, count 2 2006.197.08:08:00.05#ibcon#about to write, iclass 38, count 2 2006.197.08:08:00.05#ibcon#wrote, iclass 38, count 2 2006.197.08:08:00.05#ibcon#about to read 3, iclass 38, count 2 2006.197.08:08:00.07#ibcon#read 3, iclass 38, count 2 2006.197.08:08:00.07#ibcon#about to read 4, iclass 38, count 2 2006.197.08:08:00.07#ibcon#read 4, iclass 38, count 2 2006.197.08:08:00.07#ibcon#about to read 5, iclass 38, count 2 2006.197.08:08:00.07#ibcon#read 5, iclass 38, count 2 2006.197.08:08:00.07#ibcon#about to read 6, iclass 38, count 2 2006.197.08:08:00.07#ibcon#read 6, iclass 38, count 2 2006.197.08:08:00.07#ibcon#end of sib2, iclass 38, count 2 2006.197.08:08:00.07#ibcon#*mode == 0, iclass 38, count 2 2006.197.08:08:00.07#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.197.08:08:00.07#ibcon#[25=AT07-06\r\n] 2006.197.08:08:00.07#ibcon#*before write, iclass 38, count 2 2006.197.08:08:00.07#ibcon#enter sib2, iclass 38, count 2 2006.197.08:08:00.07#ibcon#flushed, iclass 38, count 2 2006.197.08:08:00.07#ibcon#about to write, iclass 38, count 2 2006.197.08:08:00.07#ibcon#wrote, iclass 38, count 2 2006.197.08:08:00.07#ibcon#about to read 3, iclass 38, count 2 2006.197.08:08:00.10#ibcon#read 3, iclass 38, count 2 2006.197.08:08:00.10#ibcon#about to read 4, iclass 38, count 2 2006.197.08:08:00.10#ibcon#read 4, iclass 38, count 2 2006.197.08:08:00.10#ibcon#about to read 5, iclass 38, count 2 2006.197.08:08:00.10#ibcon#read 5, iclass 38, count 2 2006.197.08:08:00.10#ibcon#about to read 6, iclass 38, count 2 2006.197.08:08:00.10#ibcon#read 6, iclass 38, count 2 2006.197.08:08:00.10#ibcon#end of sib2, iclass 38, count 2 2006.197.08:08:00.10#ibcon#*after write, iclass 38, count 2 2006.197.08:08:00.10#ibcon#*before return 0, iclass 38, count 2 2006.197.08:08:00.10#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.197.08:08:00.10#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.197.08:08:00.10#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.197.08:08:00.10#ibcon#ireg 7 cls_cnt 0 2006.197.08:08:00.10#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.197.08:08:00.22#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.197.08:08:00.22#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.197.08:08:00.22#ibcon#enter wrdev, iclass 38, count 0 2006.197.08:08:00.22#ibcon#first serial, iclass 38, count 0 2006.197.08:08:00.22#ibcon#enter sib2, iclass 38, count 0 2006.197.08:08:00.22#ibcon#flushed, iclass 38, count 0 2006.197.08:08:00.22#ibcon#about to write, iclass 38, count 0 2006.197.08:08:00.22#ibcon#wrote, iclass 38, count 0 2006.197.08:08:00.22#ibcon#about to read 3, iclass 38, count 0 2006.197.08:08:00.24#ibcon#read 3, iclass 38, count 0 2006.197.08:08:00.24#ibcon#about to read 4, iclass 38, count 0 2006.197.08:08:00.24#ibcon#read 4, iclass 38, count 0 2006.197.08:08:00.24#ibcon#about to read 5, iclass 38, count 0 2006.197.08:08:00.24#ibcon#read 5, iclass 38, count 0 2006.197.08:08:00.24#ibcon#about to read 6, iclass 38, count 0 2006.197.08:08:00.24#ibcon#read 6, iclass 38, count 0 2006.197.08:08:00.24#ibcon#end of sib2, iclass 38, count 0 2006.197.08:08:00.24#ibcon#*mode == 0, iclass 38, count 0 2006.197.08:08:00.24#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.197.08:08:00.24#ibcon#[25=USB\r\n] 2006.197.08:08:00.24#ibcon#*before write, iclass 38, count 0 2006.197.08:08:00.24#ibcon#enter sib2, iclass 38, count 0 2006.197.08:08:00.24#ibcon#flushed, iclass 38, count 0 2006.197.08:08:00.24#ibcon#about to write, iclass 38, count 0 2006.197.08:08:00.24#ibcon#wrote, iclass 38, count 0 2006.197.08:08:00.24#ibcon#about to read 3, iclass 38, count 0 2006.197.08:08:00.27#ibcon#read 3, iclass 38, count 0 2006.197.08:08:00.27#ibcon#about to read 4, iclass 38, count 0 2006.197.08:08:00.27#ibcon#read 4, iclass 38, count 0 2006.197.08:08:00.27#ibcon#about to read 5, iclass 38, count 0 2006.197.08:08:00.27#ibcon#read 5, iclass 38, count 0 2006.197.08:08:00.27#ibcon#about to read 6, iclass 38, count 0 2006.197.08:08:00.27#ibcon#read 6, iclass 38, count 0 2006.197.08:08:00.27#ibcon#end of sib2, iclass 38, count 0 2006.197.08:08:00.27#ibcon#*after write, iclass 38, count 0 2006.197.08:08:00.27#ibcon#*before return 0, iclass 38, count 0 2006.197.08:08:00.27#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.197.08:08:00.27#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.197.08:08:00.27#ibcon#about to clear, iclass 38 cls_cnt 0 2006.197.08:08:00.27#ibcon#cleared, iclass 38 cls_cnt 0 2006.197.08:08:00.27$vc4f8/valo=8,852.99 2006.197.08:08:00.27#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.197.08:08:00.27#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.197.08:08:00.27#ibcon#ireg 17 cls_cnt 0 2006.197.08:08:00.27#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.197.08:08:00.27#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.197.08:08:00.27#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.197.08:08:00.27#ibcon#enter wrdev, iclass 40, count 0 2006.197.08:08:00.27#ibcon#first serial, iclass 40, count 0 2006.197.08:08:00.27#ibcon#enter sib2, iclass 40, count 0 2006.197.08:08:00.27#ibcon#flushed, iclass 40, count 0 2006.197.08:08:00.27#ibcon#about to write, iclass 40, count 0 2006.197.08:08:00.27#ibcon#wrote, iclass 40, count 0 2006.197.08:08:00.27#ibcon#about to read 3, iclass 40, count 0 2006.197.08:08:00.29#ibcon#read 3, iclass 40, count 0 2006.197.08:08:00.29#ibcon#about to read 4, iclass 40, count 0 2006.197.08:08:00.29#ibcon#read 4, iclass 40, count 0 2006.197.08:08:00.29#ibcon#about to read 5, iclass 40, count 0 2006.197.08:08:00.29#ibcon#read 5, iclass 40, count 0 2006.197.08:08:00.29#ibcon#about to read 6, iclass 40, count 0 2006.197.08:08:00.29#ibcon#read 6, iclass 40, count 0 2006.197.08:08:00.29#ibcon#end of sib2, iclass 40, count 0 2006.197.08:08:00.29#ibcon#*mode == 0, iclass 40, count 0 2006.197.08:08:00.29#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.197.08:08:00.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.197.08:08:00.29#ibcon#*before write, iclass 40, count 0 2006.197.08:08:00.29#ibcon#enter sib2, iclass 40, count 0 2006.197.08:08:00.29#ibcon#flushed, iclass 40, count 0 2006.197.08:08:00.29#ibcon#about to write, iclass 40, count 0 2006.197.08:08:00.29#ibcon#wrote, iclass 40, count 0 2006.197.08:08:00.29#ibcon#about to read 3, iclass 40, count 0 2006.197.08:08:00.33#ibcon#read 3, iclass 40, count 0 2006.197.08:08:00.33#ibcon#about to read 4, iclass 40, count 0 2006.197.08:08:00.33#ibcon#read 4, iclass 40, count 0 2006.197.08:08:00.33#ibcon#about to read 5, iclass 40, count 0 2006.197.08:08:00.33#ibcon#read 5, iclass 40, count 0 2006.197.08:08:00.33#ibcon#about to read 6, iclass 40, count 0 2006.197.08:08:00.33#ibcon#read 6, iclass 40, count 0 2006.197.08:08:00.33#ibcon#end of sib2, iclass 40, count 0 2006.197.08:08:00.33#ibcon#*after write, iclass 40, count 0 2006.197.08:08:00.33#ibcon#*before return 0, iclass 40, count 0 2006.197.08:08:00.33#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.197.08:08:00.33#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.197.08:08:00.33#ibcon#about to clear, iclass 40 cls_cnt 0 2006.197.08:08:00.33#ibcon#cleared, iclass 40 cls_cnt 0 2006.197.08:08:00.33$vc4f8/va=8,7 2006.197.08:08:00.33#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.197.08:08:00.33#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.197.08:08:00.33#ibcon#ireg 11 cls_cnt 2 2006.197.08:08:00.33#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.197.08:08:00.39#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.197.08:08:00.39#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.197.08:08:00.39#ibcon#enter wrdev, iclass 4, count 2 2006.197.08:08:00.39#ibcon#first serial, iclass 4, count 2 2006.197.08:08:00.39#ibcon#enter sib2, iclass 4, count 2 2006.197.08:08:00.39#ibcon#flushed, iclass 4, count 2 2006.197.08:08:00.39#ibcon#about to write, iclass 4, count 2 2006.197.08:08:00.39#ibcon#wrote, iclass 4, count 2 2006.197.08:08:00.39#ibcon#about to read 3, iclass 4, count 2 2006.197.08:08:00.41#ibcon#read 3, iclass 4, count 2 2006.197.08:08:00.41#ibcon#about to read 4, iclass 4, count 2 2006.197.08:08:00.41#ibcon#read 4, iclass 4, count 2 2006.197.08:08:00.41#ibcon#about to read 5, iclass 4, count 2 2006.197.08:08:00.41#ibcon#read 5, iclass 4, count 2 2006.197.08:08:00.41#ibcon#about to read 6, iclass 4, count 2 2006.197.08:08:00.41#ibcon#read 6, iclass 4, count 2 2006.197.08:08:00.41#ibcon#end of sib2, iclass 4, count 2 2006.197.08:08:00.41#ibcon#*mode == 0, iclass 4, count 2 2006.197.08:08:00.41#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.197.08:08:00.41#ibcon#[25=AT08-07\r\n] 2006.197.08:08:00.41#ibcon#*before write, iclass 4, count 2 2006.197.08:08:00.41#ibcon#enter sib2, iclass 4, count 2 2006.197.08:08:00.41#ibcon#flushed, iclass 4, count 2 2006.197.08:08:00.41#ibcon#about to write, iclass 4, count 2 2006.197.08:08:00.41#ibcon#wrote, iclass 4, count 2 2006.197.08:08:00.41#ibcon#about to read 3, iclass 4, count 2 2006.197.08:08:00.44#ibcon#read 3, iclass 4, count 2 2006.197.08:08:00.44#ibcon#about to read 4, iclass 4, count 2 2006.197.08:08:00.44#ibcon#read 4, iclass 4, count 2 2006.197.08:08:00.44#ibcon#about to read 5, iclass 4, count 2 2006.197.08:08:00.44#ibcon#read 5, iclass 4, count 2 2006.197.08:08:00.44#ibcon#about to read 6, iclass 4, count 2 2006.197.08:08:00.44#ibcon#read 6, iclass 4, count 2 2006.197.08:08:00.44#ibcon#end of sib2, iclass 4, count 2 2006.197.08:08:00.44#ibcon#*after write, iclass 4, count 2 2006.197.08:08:00.44#ibcon#*before return 0, iclass 4, count 2 2006.197.08:08:00.44#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.197.08:08:00.44#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.197.08:08:00.44#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.197.08:08:00.44#ibcon#ireg 7 cls_cnt 0 2006.197.08:08:00.44#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.197.08:08:00.56#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.197.08:08:00.56#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.197.08:08:00.56#ibcon#enter wrdev, iclass 4, count 0 2006.197.08:08:00.56#ibcon#first serial, iclass 4, count 0 2006.197.08:08:00.56#ibcon#enter sib2, iclass 4, count 0 2006.197.08:08:00.56#ibcon#flushed, iclass 4, count 0 2006.197.08:08:00.56#ibcon#about to write, iclass 4, count 0 2006.197.08:08:00.56#ibcon#wrote, iclass 4, count 0 2006.197.08:08:00.56#ibcon#about to read 3, iclass 4, count 0 2006.197.08:08:00.58#ibcon#read 3, iclass 4, count 0 2006.197.08:08:00.58#ibcon#about to read 4, iclass 4, count 0 2006.197.08:08:00.58#ibcon#read 4, iclass 4, count 0 2006.197.08:08:00.58#ibcon#about to read 5, iclass 4, count 0 2006.197.08:08:00.58#ibcon#read 5, iclass 4, count 0 2006.197.08:08:00.58#ibcon#about to read 6, iclass 4, count 0 2006.197.08:08:00.58#ibcon#read 6, iclass 4, count 0 2006.197.08:08:00.58#ibcon#end of sib2, iclass 4, count 0 2006.197.08:08:00.58#ibcon#*mode == 0, iclass 4, count 0 2006.197.08:08:00.58#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.197.08:08:00.58#ibcon#[25=USB\r\n] 2006.197.08:08:00.58#ibcon#*before write, iclass 4, count 0 2006.197.08:08:00.58#ibcon#enter sib2, iclass 4, count 0 2006.197.08:08:00.58#ibcon#flushed, iclass 4, count 0 2006.197.08:08:00.58#ibcon#about to write, iclass 4, count 0 2006.197.08:08:00.58#ibcon#wrote, iclass 4, count 0 2006.197.08:08:00.58#ibcon#about to read 3, iclass 4, count 0 2006.197.08:08:00.61#ibcon#read 3, iclass 4, count 0 2006.197.08:08:00.61#ibcon#about to read 4, iclass 4, count 0 2006.197.08:08:00.61#ibcon#read 4, iclass 4, count 0 2006.197.08:08:00.61#ibcon#about to read 5, iclass 4, count 0 2006.197.08:08:00.61#ibcon#read 5, iclass 4, count 0 2006.197.08:08:00.61#ibcon#about to read 6, iclass 4, count 0 2006.197.08:08:00.61#ibcon#read 6, iclass 4, count 0 2006.197.08:08:00.61#ibcon#end of sib2, iclass 4, count 0 2006.197.08:08:00.61#ibcon#*after write, iclass 4, count 0 2006.197.08:08:00.61#ibcon#*before return 0, iclass 4, count 0 2006.197.08:08:00.61#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.197.08:08:00.61#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.197.08:08:00.61#ibcon#about to clear, iclass 4 cls_cnt 0 2006.197.08:08:00.61#ibcon#cleared, iclass 4 cls_cnt 0 2006.197.08:08:00.61$vc4f8/vblo=1,632.99 2006.197.08:08:00.61#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.197.08:08:00.61#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.197.08:08:00.61#ibcon#ireg 17 cls_cnt 0 2006.197.08:08:00.61#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.197.08:08:00.61#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.197.08:08:00.61#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.197.08:08:00.61#ibcon#enter wrdev, iclass 6, count 0 2006.197.08:08:00.61#ibcon#first serial, iclass 6, count 0 2006.197.08:08:00.61#ibcon#enter sib2, iclass 6, count 0 2006.197.08:08:00.61#ibcon#flushed, iclass 6, count 0 2006.197.08:08:00.61#ibcon#about to write, iclass 6, count 0 2006.197.08:08:00.61#ibcon#wrote, iclass 6, count 0 2006.197.08:08:00.61#ibcon#about to read 3, iclass 6, count 0 2006.197.08:08:00.63#ibcon#read 3, iclass 6, count 0 2006.197.08:08:00.63#ibcon#about to read 4, iclass 6, count 0 2006.197.08:08:00.63#ibcon#read 4, iclass 6, count 0 2006.197.08:08:00.63#ibcon#about to read 5, iclass 6, count 0 2006.197.08:08:00.63#ibcon#read 5, iclass 6, count 0 2006.197.08:08:00.63#ibcon#about to read 6, iclass 6, count 0 2006.197.08:08:00.63#ibcon#read 6, iclass 6, count 0 2006.197.08:08:00.63#ibcon#end of sib2, iclass 6, count 0 2006.197.08:08:00.63#ibcon#*mode == 0, iclass 6, count 0 2006.197.08:08:00.63#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.197.08:08:00.63#ibcon#[28=FRQ=01,632.99\r\n] 2006.197.08:08:00.63#ibcon#*before write, iclass 6, count 0 2006.197.08:08:00.63#ibcon#enter sib2, iclass 6, count 0 2006.197.08:08:00.63#ibcon#flushed, iclass 6, count 0 2006.197.08:08:00.63#ibcon#about to write, iclass 6, count 0 2006.197.08:08:00.63#ibcon#wrote, iclass 6, count 0 2006.197.08:08:00.63#ibcon#about to read 3, iclass 6, count 0 2006.197.08:08:00.67#ibcon#read 3, iclass 6, count 0 2006.197.08:08:00.67#ibcon#about to read 4, iclass 6, count 0 2006.197.08:08:00.67#ibcon#read 4, iclass 6, count 0 2006.197.08:08:00.67#ibcon#about to read 5, iclass 6, count 0 2006.197.08:08:00.67#ibcon#read 5, iclass 6, count 0 2006.197.08:08:00.67#ibcon#about to read 6, iclass 6, count 0 2006.197.08:08:00.67#ibcon#read 6, iclass 6, count 0 2006.197.08:08:00.67#ibcon#end of sib2, iclass 6, count 0 2006.197.08:08:00.67#ibcon#*after write, iclass 6, count 0 2006.197.08:08:00.67#ibcon#*before return 0, iclass 6, count 0 2006.197.08:08:00.67#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.197.08:08:00.67#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.197.08:08:00.67#ibcon#about to clear, iclass 6 cls_cnt 0 2006.197.08:08:00.67#ibcon#cleared, iclass 6 cls_cnt 0 2006.197.08:08:00.67$vc4f8/vb=1,4 2006.197.08:08:00.67#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.197.08:08:00.67#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.197.08:08:00.67#ibcon#ireg 11 cls_cnt 2 2006.197.08:08:00.67#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.197.08:08:00.67#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.197.08:08:00.67#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.197.08:08:00.67#ibcon#enter wrdev, iclass 10, count 2 2006.197.08:08:00.67#ibcon#first serial, iclass 10, count 2 2006.197.08:08:00.67#ibcon#enter sib2, iclass 10, count 2 2006.197.08:08:00.67#ibcon#flushed, iclass 10, count 2 2006.197.08:08:00.67#ibcon#about to write, iclass 10, count 2 2006.197.08:08:00.67#ibcon#wrote, iclass 10, count 2 2006.197.08:08:00.67#ibcon#about to read 3, iclass 10, count 2 2006.197.08:08:00.69#ibcon#read 3, iclass 10, count 2 2006.197.08:08:00.69#ibcon#about to read 4, iclass 10, count 2 2006.197.08:08:00.69#ibcon#read 4, iclass 10, count 2 2006.197.08:08:00.69#ibcon#about to read 5, iclass 10, count 2 2006.197.08:08:00.69#ibcon#read 5, iclass 10, count 2 2006.197.08:08:00.69#ibcon#about to read 6, iclass 10, count 2 2006.197.08:08:00.69#ibcon#read 6, iclass 10, count 2 2006.197.08:08:00.69#ibcon#end of sib2, iclass 10, count 2 2006.197.08:08:00.69#ibcon#*mode == 0, iclass 10, count 2 2006.197.08:08:00.69#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.197.08:08:00.69#ibcon#[27=AT01-04\r\n] 2006.197.08:08:00.69#ibcon#*before write, iclass 10, count 2 2006.197.08:08:00.69#ibcon#enter sib2, iclass 10, count 2 2006.197.08:08:00.69#ibcon#flushed, iclass 10, count 2 2006.197.08:08:00.69#ibcon#about to write, iclass 10, count 2 2006.197.08:08:00.69#ibcon#wrote, iclass 10, count 2 2006.197.08:08:00.69#ibcon#about to read 3, iclass 10, count 2 2006.197.08:08:00.72#ibcon#read 3, iclass 10, count 2 2006.197.08:08:00.72#ibcon#about to read 4, iclass 10, count 2 2006.197.08:08:00.72#ibcon#read 4, iclass 10, count 2 2006.197.08:08:00.72#ibcon#about to read 5, iclass 10, count 2 2006.197.08:08:00.72#ibcon#read 5, iclass 10, count 2 2006.197.08:08:00.72#ibcon#about to read 6, iclass 10, count 2 2006.197.08:08:00.72#ibcon#read 6, iclass 10, count 2 2006.197.08:08:00.72#ibcon#end of sib2, iclass 10, count 2 2006.197.08:08:00.72#ibcon#*after write, iclass 10, count 2 2006.197.08:08:00.72#ibcon#*before return 0, iclass 10, count 2 2006.197.08:08:00.72#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.197.08:08:00.72#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.197.08:08:00.72#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.197.08:08:00.72#ibcon#ireg 7 cls_cnt 0 2006.197.08:08:00.72#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.197.08:08:00.84#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.197.08:08:00.84#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.197.08:08:00.84#ibcon#enter wrdev, iclass 10, count 0 2006.197.08:08:00.84#ibcon#first serial, iclass 10, count 0 2006.197.08:08:00.84#ibcon#enter sib2, iclass 10, count 0 2006.197.08:08:00.84#ibcon#flushed, iclass 10, count 0 2006.197.08:08:00.84#ibcon#about to write, iclass 10, count 0 2006.197.08:08:00.84#ibcon#wrote, iclass 10, count 0 2006.197.08:08:00.84#ibcon#about to read 3, iclass 10, count 0 2006.197.08:08:00.86#ibcon#read 3, iclass 10, count 0 2006.197.08:08:00.86#ibcon#about to read 4, iclass 10, count 0 2006.197.08:08:00.86#ibcon#read 4, iclass 10, count 0 2006.197.08:08:00.86#ibcon#about to read 5, iclass 10, count 0 2006.197.08:08:00.86#ibcon#read 5, iclass 10, count 0 2006.197.08:08:00.86#ibcon#about to read 6, iclass 10, count 0 2006.197.08:08:00.86#ibcon#read 6, iclass 10, count 0 2006.197.08:08:00.86#ibcon#end of sib2, iclass 10, count 0 2006.197.08:08:00.86#ibcon#*mode == 0, iclass 10, count 0 2006.197.08:08:00.86#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.197.08:08:00.86#ibcon#[27=USB\r\n] 2006.197.08:08:00.86#ibcon#*before write, iclass 10, count 0 2006.197.08:08:00.86#ibcon#enter sib2, iclass 10, count 0 2006.197.08:08:00.86#ibcon#flushed, iclass 10, count 0 2006.197.08:08:00.86#ibcon#about to write, iclass 10, count 0 2006.197.08:08:00.86#ibcon#wrote, iclass 10, count 0 2006.197.08:08:00.86#ibcon#about to read 3, iclass 10, count 0 2006.197.08:08:00.89#ibcon#read 3, iclass 10, count 0 2006.197.08:08:00.89#ibcon#about to read 4, iclass 10, count 0 2006.197.08:08:00.89#ibcon#read 4, iclass 10, count 0 2006.197.08:08:00.89#ibcon#about to read 5, iclass 10, count 0 2006.197.08:08:00.89#ibcon#read 5, iclass 10, count 0 2006.197.08:08:00.89#ibcon#about to read 6, iclass 10, count 0 2006.197.08:08:00.89#ibcon#read 6, iclass 10, count 0 2006.197.08:08:00.89#ibcon#end of sib2, iclass 10, count 0 2006.197.08:08:00.89#ibcon#*after write, iclass 10, count 0 2006.197.08:08:00.89#ibcon#*before return 0, iclass 10, count 0 2006.197.08:08:00.89#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.197.08:08:00.89#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.197.08:08:00.89#ibcon#about to clear, iclass 10 cls_cnt 0 2006.197.08:08:00.89#ibcon#cleared, iclass 10 cls_cnt 0 2006.197.08:08:00.89$vc4f8/vblo=2,640.99 2006.197.08:08:00.89#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.197.08:08:00.89#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.197.08:08:00.89#ibcon#ireg 17 cls_cnt 0 2006.197.08:08:00.89#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.197.08:08:00.89#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.197.08:08:00.89#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.197.08:08:00.89#ibcon#enter wrdev, iclass 12, count 0 2006.197.08:08:00.89#ibcon#first serial, iclass 12, count 0 2006.197.08:08:00.89#ibcon#enter sib2, iclass 12, count 0 2006.197.08:08:00.89#ibcon#flushed, iclass 12, count 0 2006.197.08:08:00.89#ibcon#about to write, iclass 12, count 0 2006.197.08:08:00.89#ibcon#wrote, iclass 12, count 0 2006.197.08:08:00.89#ibcon#about to read 3, iclass 12, count 0 2006.197.08:08:00.91#ibcon#read 3, iclass 12, count 0 2006.197.08:08:00.91#ibcon#about to read 4, iclass 12, count 0 2006.197.08:08:00.91#ibcon#read 4, iclass 12, count 0 2006.197.08:08:00.91#ibcon#about to read 5, iclass 12, count 0 2006.197.08:08:00.91#ibcon#read 5, iclass 12, count 0 2006.197.08:08:00.91#ibcon#about to read 6, iclass 12, count 0 2006.197.08:08:00.91#ibcon#read 6, iclass 12, count 0 2006.197.08:08:00.91#ibcon#end of sib2, iclass 12, count 0 2006.197.08:08:00.91#ibcon#*mode == 0, iclass 12, count 0 2006.197.08:08:00.91#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.197.08:08:00.91#ibcon#[28=FRQ=02,640.99\r\n] 2006.197.08:08:00.91#ibcon#*before write, iclass 12, count 0 2006.197.08:08:00.91#ibcon#enter sib2, iclass 12, count 0 2006.197.08:08:00.91#ibcon#flushed, iclass 12, count 0 2006.197.08:08:00.91#ibcon#about to write, iclass 12, count 0 2006.197.08:08:00.91#ibcon#wrote, iclass 12, count 0 2006.197.08:08:00.91#ibcon#about to read 3, iclass 12, count 0 2006.197.08:08:00.95#ibcon#read 3, iclass 12, count 0 2006.197.08:08:00.95#ibcon#about to read 4, iclass 12, count 0 2006.197.08:08:00.95#ibcon#read 4, iclass 12, count 0 2006.197.08:08:00.95#ibcon#about to read 5, iclass 12, count 0 2006.197.08:08:00.95#ibcon#read 5, iclass 12, count 0 2006.197.08:08:00.95#ibcon#about to read 6, iclass 12, count 0 2006.197.08:08:00.95#ibcon#read 6, iclass 12, count 0 2006.197.08:08:00.95#ibcon#end of sib2, iclass 12, count 0 2006.197.08:08:00.95#ibcon#*after write, iclass 12, count 0 2006.197.08:08:00.95#ibcon#*before return 0, iclass 12, count 0 2006.197.08:08:00.95#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.197.08:08:00.95#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.197.08:08:00.95#ibcon#about to clear, iclass 12 cls_cnt 0 2006.197.08:08:00.95#ibcon#cleared, iclass 12 cls_cnt 0 2006.197.08:08:00.95$vc4f8/vb=2,4 2006.197.08:08:00.95#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.197.08:08:00.95#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.197.08:08:00.95#ibcon#ireg 11 cls_cnt 2 2006.197.08:08:00.95#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.197.08:08:01.01#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.197.08:08:01.01#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.197.08:08:01.01#ibcon#enter wrdev, iclass 14, count 2 2006.197.08:08:01.01#ibcon#first serial, iclass 14, count 2 2006.197.08:08:01.01#ibcon#enter sib2, iclass 14, count 2 2006.197.08:08:01.01#ibcon#flushed, iclass 14, count 2 2006.197.08:08:01.01#ibcon#about to write, iclass 14, count 2 2006.197.08:08:01.01#ibcon#wrote, iclass 14, count 2 2006.197.08:08:01.01#ibcon#about to read 3, iclass 14, count 2 2006.197.08:08:01.03#ibcon#read 3, iclass 14, count 2 2006.197.08:08:01.03#ibcon#about to read 4, iclass 14, count 2 2006.197.08:08:01.03#ibcon#read 4, iclass 14, count 2 2006.197.08:08:01.03#ibcon#about to read 5, iclass 14, count 2 2006.197.08:08:01.03#ibcon#read 5, iclass 14, count 2 2006.197.08:08:01.03#ibcon#about to read 6, iclass 14, count 2 2006.197.08:08:01.03#ibcon#read 6, iclass 14, count 2 2006.197.08:08:01.03#ibcon#end of sib2, iclass 14, count 2 2006.197.08:08:01.03#ibcon#*mode == 0, iclass 14, count 2 2006.197.08:08:01.03#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.197.08:08:01.03#ibcon#[27=AT02-04\r\n] 2006.197.08:08:01.03#ibcon#*before write, iclass 14, count 2 2006.197.08:08:01.03#ibcon#enter sib2, iclass 14, count 2 2006.197.08:08:01.03#ibcon#flushed, iclass 14, count 2 2006.197.08:08:01.03#ibcon#about to write, iclass 14, count 2 2006.197.08:08:01.03#ibcon#wrote, iclass 14, count 2 2006.197.08:08:01.03#ibcon#about to read 3, iclass 14, count 2 2006.197.08:08:01.06#ibcon#read 3, iclass 14, count 2 2006.197.08:08:01.06#ibcon#about to read 4, iclass 14, count 2 2006.197.08:08:01.06#ibcon#read 4, iclass 14, count 2 2006.197.08:08:01.06#ibcon#about to read 5, iclass 14, count 2 2006.197.08:08:01.06#ibcon#read 5, iclass 14, count 2 2006.197.08:08:01.06#ibcon#about to read 6, iclass 14, count 2 2006.197.08:08:01.06#ibcon#read 6, iclass 14, count 2 2006.197.08:08:01.06#ibcon#end of sib2, iclass 14, count 2 2006.197.08:08:01.06#ibcon#*after write, iclass 14, count 2 2006.197.08:08:01.06#ibcon#*before return 0, iclass 14, count 2 2006.197.08:08:01.06#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.197.08:08:01.06#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.197.08:08:01.06#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.197.08:08:01.06#ibcon#ireg 7 cls_cnt 0 2006.197.08:08:01.06#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.197.08:08:01.18#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.197.08:08:01.18#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.197.08:08:01.18#ibcon#enter wrdev, iclass 14, count 0 2006.197.08:08:01.18#ibcon#first serial, iclass 14, count 0 2006.197.08:08:01.18#ibcon#enter sib2, iclass 14, count 0 2006.197.08:08:01.18#ibcon#flushed, iclass 14, count 0 2006.197.08:08:01.18#ibcon#about to write, iclass 14, count 0 2006.197.08:08:01.18#ibcon#wrote, iclass 14, count 0 2006.197.08:08:01.18#ibcon#about to read 3, iclass 14, count 0 2006.197.08:08:01.20#ibcon#read 3, iclass 14, count 0 2006.197.08:08:01.20#ibcon#about to read 4, iclass 14, count 0 2006.197.08:08:01.20#ibcon#read 4, iclass 14, count 0 2006.197.08:08:01.20#ibcon#about to read 5, iclass 14, count 0 2006.197.08:08:01.20#ibcon#read 5, iclass 14, count 0 2006.197.08:08:01.20#ibcon#about to read 6, iclass 14, count 0 2006.197.08:08:01.20#ibcon#read 6, iclass 14, count 0 2006.197.08:08:01.20#ibcon#end of sib2, iclass 14, count 0 2006.197.08:08:01.20#ibcon#*mode == 0, iclass 14, count 0 2006.197.08:08:01.20#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.197.08:08:01.20#ibcon#[27=USB\r\n] 2006.197.08:08:01.20#ibcon#*before write, iclass 14, count 0 2006.197.08:08:01.20#ibcon#enter sib2, iclass 14, count 0 2006.197.08:08:01.20#ibcon#flushed, iclass 14, count 0 2006.197.08:08:01.20#ibcon#about to write, iclass 14, count 0 2006.197.08:08:01.20#ibcon#wrote, iclass 14, count 0 2006.197.08:08:01.20#ibcon#about to read 3, iclass 14, count 0 2006.197.08:08:01.23#ibcon#read 3, iclass 14, count 0 2006.197.08:08:01.23#ibcon#about to read 4, iclass 14, count 0 2006.197.08:08:01.23#ibcon#read 4, iclass 14, count 0 2006.197.08:08:01.23#ibcon#about to read 5, iclass 14, count 0 2006.197.08:08:01.23#ibcon#read 5, iclass 14, count 0 2006.197.08:08:01.23#ibcon#about to read 6, iclass 14, count 0 2006.197.08:08:01.23#ibcon#read 6, iclass 14, count 0 2006.197.08:08:01.23#ibcon#end of sib2, iclass 14, count 0 2006.197.08:08:01.23#ibcon#*after write, iclass 14, count 0 2006.197.08:08:01.23#ibcon#*before return 0, iclass 14, count 0 2006.197.08:08:01.23#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.197.08:08:01.23#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.197.08:08:01.23#ibcon#about to clear, iclass 14 cls_cnt 0 2006.197.08:08:01.23#ibcon#cleared, iclass 14 cls_cnt 0 2006.197.08:08:01.23$vc4f8/vblo=3,656.99 2006.197.08:08:01.23#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.197.08:08:01.23#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.197.08:08:01.23#ibcon#ireg 17 cls_cnt 0 2006.197.08:08:01.23#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.197.08:08:01.23#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.197.08:08:01.23#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.197.08:08:01.23#ibcon#enter wrdev, iclass 16, count 0 2006.197.08:08:01.23#ibcon#first serial, iclass 16, count 0 2006.197.08:08:01.23#ibcon#enter sib2, iclass 16, count 0 2006.197.08:08:01.23#ibcon#flushed, iclass 16, count 0 2006.197.08:08:01.23#ibcon#about to write, iclass 16, count 0 2006.197.08:08:01.23#ibcon#wrote, iclass 16, count 0 2006.197.08:08:01.23#ibcon#about to read 3, iclass 16, count 0 2006.197.08:08:01.25#ibcon#read 3, iclass 16, count 0 2006.197.08:08:01.25#ibcon#about to read 4, iclass 16, count 0 2006.197.08:08:01.25#ibcon#read 4, iclass 16, count 0 2006.197.08:08:01.25#ibcon#about to read 5, iclass 16, count 0 2006.197.08:08:01.25#ibcon#read 5, iclass 16, count 0 2006.197.08:08:01.25#ibcon#about to read 6, iclass 16, count 0 2006.197.08:08:01.25#ibcon#read 6, iclass 16, count 0 2006.197.08:08:01.25#ibcon#end of sib2, iclass 16, count 0 2006.197.08:08:01.25#ibcon#*mode == 0, iclass 16, count 0 2006.197.08:08:01.25#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.197.08:08:01.25#ibcon#[28=FRQ=03,656.99\r\n] 2006.197.08:08:01.25#ibcon#*before write, iclass 16, count 0 2006.197.08:08:01.25#ibcon#enter sib2, iclass 16, count 0 2006.197.08:08:01.25#ibcon#flushed, iclass 16, count 0 2006.197.08:08:01.25#ibcon#about to write, iclass 16, count 0 2006.197.08:08:01.25#ibcon#wrote, iclass 16, count 0 2006.197.08:08:01.25#ibcon#about to read 3, iclass 16, count 0 2006.197.08:08:01.29#ibcon#read 3, iclass 16, count 0 2006.197.08:08:01.29#ibcon#about to read 4, iclass 16, count 0 2006.197.08:08:01.29#ibcon#read 4, iclass 16, count 0 2006.197.08:08:01.29#ibcon#about to read 5, iclass 16, count 0 2006.197.08:08:01.29#ibcon#read 5, iclass 16, count 0 2006.197.08:08:01.29#ibcon#about to read 6, iclass 16, count 0 2006.197.08:08:01.29#ibcon#read 6, iclass 16, count 0 2006.197.08:08:01.29#ibcon#end of sib2, iclass 16, count 0 2006.197.08:08:01.29#ibcon#*after write, iclass 16, count 0 2006.197.08:08:01.29#ibcon#*before return 0, iclass 16, count 0 2006.197.08:08:01.29#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.197.08:08:01.29#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.197.08:08:01.29#ibcon#about to clear, iclass 16 cls_cnt 0 2006.197.08:08:01.29#ibcon#cleared, iclass 16 cls_cnt 0 2006.197.08:08:01.29$vc4f8/vb=3,4 2006.197.08:08:01.29#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.197.08:08:01.29#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.197.08:08:01.29#ibcon#ireg 11 cls_cnt 2 2006.197.08:08:01.29#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.197.08:08:01.35#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.197.08:08:01.35#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.197.08:08:01.35#ibcon#enter wrdev, iclass 18, count 2 2006.197.08:08:01.35#ibcon#first serial, iclass 18, count 2 2006.197.08:08:01.35#ibcon#enter sib2, iclass 18, count 2 2006.197.08:08:01.35#ibcon#flushed, iclass 18, count 2 2006.197.08:08:01.35#ibcon#about to write, iclass 18, count 2 2006.197.08:08:01.35#ibcon#wrote, iclass 18, count 2 2006.197.08:08:01.35#ibcon#about to read 3, iclass 18, count 2 2006.197.08:08:01.37#ibcon#read 3, iclass 18, count 2 2006.197.08:08:01.37#ibcon#about to read 4, iclass 18, count 2 2006.197.08:08:01.37#ibcon#read 4, iclass 18, count 2 2006.197.08:08:01.37#ibcon#about to read 5, iclass 18, count 2 2006.197.08:08:01.37#ibcon#read 5, iclass 18, count 2 2006.197.08:08:01.37#ibcon#about to read 6, iclass 18, count 2 2006.197.08:08:01.37#ibcon#read 6, iclass 18, count 2 2006.197.08:08:01.37#ibcon#end of sib2, iclass 18, count 2 2006.197.08:08:01.37#ibcon#*mode == 0, iclass 18, count 2 2006.197.08:08:01.37#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.197.08:08:01.37#ibcon#[27=AT03-04\r\n] 2006.197.08:08:01.37#ibcon#*before write, iclass 18, count 2 2006.197.08:08:01.37#ibcon#enter sib2, iclass 18, count 2 2006.197.08:08:01.37#ibcon#flushed, iclass 18, count 2 2006.197.08:08:01.37#ibcon#about to write, iclass 18, count 2 2006.197.08:08:01.37#ibcon#wrote, iclass 18, count 2 2006.197.08:08:01.37#ibcon#about to read 3, iclass 18, count 2 2006.197.08:08:01.40#ibcon#read 3, iclass 18, count 2 2006.197.08:08:01.40#ibcon#about to read 4, iclass 18, count 2 2006.197.08:08:01.40#ibcon#read 4, iclass 18, count 2 2006.197.08:08:01.40#ibcon#about to read 5, iclass 18, count 2 2006.197.08:08:01.40#ibcon#read 5, iclass 18, count 2 2006.197.08:08:01.40#ibcon#about to read 6, iclass 18, count 2 2006.197.08:08:01.40#ibcon#read 6, iclass 18, count 2 2006.197.08:08:01.40#ibcon#end of sib2, iclass 18, count 2 2006.197.08:08:01.40#ibcon#*after write, iclass 18, count 2 2006.197.08:08:01.40#ibcon#*before return 0, iclass 18, count 2 2006.197.08:08:01.40#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.197.08:08:01.40#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.197.08:08:01.40#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.197.08:08:01.40#ibcon#ireg 7 cls_cnt 0 2006.197.08:08:01.40#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.197.08:08:01.52#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.197.08:08:01.52#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.197.08:08:01.52#ibcon#enter wrdev, iclass 18, count 0 2006.197.08:08:01.52#ibcon#first serial, iclass 18, count 0 2006.197.08:08:01.52#ibcon#enter sib2, iclass 18, count 0 2006.197.08:08:01.52#ibcon#flushed, iclass 18, count 0 2006.197.08:08:01.52#ibcon#about to write, iclass 18, count 0 2006.197.08:08:01.52#ibcon#wrote, iclass 18, count 0 2006.197.08:08:01.52#ibcon#about to read 3, iclass 18, count 0 2006.197.08:08:01.54#ibcon#read 3, iclass 18, count 0 2006.197.08:08:01.54#ibcon#about to read 4, iclass 18, count 0 2006.197.08:08:01.54#ibcon#read 4, iclass 18, count 0 2006.197.08:08:01.54#ibcon#about to read 5, iclass 18, count 0 2006.197.08:08:01.54#ibcon#read 5, iclass 18, count 0 2006.197.08:08:01.54#ibcon#about to read 6, iclass 18, count 0 2006.197.08:08:01.54#ibcon#read 6, iclass 18, count 0 2006.197.08:08:01.54#ibcon#end of sib2, iclass 18, count 0 2006.197.08:08:01.54#ibcon#*mode == 0, iclass 18, count 0 2006.197.08:08:01.54#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.197.08:08:01.54#ibcon#[27=USB\r\n] 2006.197.08:08:01.54#ibcon#*before write, iclass 18, count 0 2006.197.08:08:01.54#ibcon#enter sib2, iclass 18, count 0 2006.197.08:08:01.54#ibcon#flushed, iclass 18, count 0 2006.197.08:08:01.54#ibcon#about to write, iclass 18, count 0 2006.197.08:08:01.54#ibcon#wrote, iclass 18, count 0 2006.197.08:08:01.54#ibcon#about to read 3, iclass 18, count 0 2006.197.08:08:01.57#ibcon#read 3, iclass 18, count 0 2006.197.08:08:01.57#ibcon#about to read 4, iclass 18, count 0 2006.197.08:08:01.57#ibcon#read 4, iclass 18, count 0 2006.197.08:08:01.57#ibcon#about to read 5, iclass 18, count 0 2006.197.08:08:01.57#ibcon#read 5, iclass 18, count 0 2006.197.08:08:01.57#ibcon#about to read 6, iclass 18, count 0 2006.197.08:08:01.57#ibcon#read 6, iclass 18, count 0 2006.197.08:08:01.57#ibcon#end of sib2, iclass 18, count 0 2006.197.08:08:01.57#ibcon#*after write, iclass 18, count 0 2006.197.08:08:01.57#ibcon#*before return 0, iclass 18, count 0 2006.197.08:08:01.57#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.197.08:08:01.57#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.197.08:08:01.57#ibcon#about to clear, iclass 18 cls_cnt 0 2006.197.08:08:01.57#ibcon#cleared, iclass 18 cls_cnt 0 2006.197.08:08:01.57$vc4f8/vblo=4,712.99 2006.197.08:08:01.57#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.197.08:08:01.57#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.197.08:08:01.57#ibcon#ireg 17 cls_cnt 0 2006.197.08:08:01.57#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.197.08:08:01.57#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.197.08:08:01.57#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.197.08:08:01.57#ibcon#enter wrdev, iclass 20, count 0 2006.197.08:08:01.57#ibcon#first serial, iclass 20, count 0 2006.197.08:08:01.57#ibcon#enter sib2, iclass 20, count 0 2006.197.08:08:01.57#ibcon#flushed, iclass 20, count 0 2006.197.08:08:01.57#ibcon#about to write, iclass 20, count 0 2006.197.08:08:01.57#ibcon#wrote, iclass 20, count 0 2006.197.08:08:01.57#ibcon#about to read 3, iclass 20, count 0 2006.197.08:08:01.59#ibcon#read 3, iclass 20, count 0 2006.197.08:08:01.59#ibcon#about to read 4, iclass 20, count 0 2006.197.08:08:01.59#ibcon#read 4, iclass 20, count 0 2006.197.08:08:01.59#ibcon#about to read 5, iclass 20, count 0 2006.197.08:08:01.59#ibcon#read 5, iclass 20, count 0 2006.197.08:08:01.59#ibcon#about to read 6, iclass 20, count 0 2006.197.08:08:01.59#ibcon#read 6, iclass 20, count 0 2006.197.08:08:01.59#ibcon#end of sib2, iclass 20, count 0 2006.197.08:08:01.59#ibcon#*mode == 0, iclass 20, count 0 2006.197.08:08:01.59#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.197.08:08:01.59#ibcon#[28=FRQ=04,712.99\r\n] 2006.197.08:08:01.59#ibcon#*before write, iclass 20, count 0 2006.197.08:08:01.59#ibcon#enter sib2, iclass 20, count 0 2006.197.08:08:01.59#ibcon#flushed, iclass 20, count 0 2006.197.08:08:01.59#ibcon#about to write, iclass 20, count 0 2006.197.08:08:01.59#ibcon#wrote, iclass 20, count 0 2006.197.08:08:01.59#ibcon#about to read 3, iclass 20, count 0 2006.197.08:08:01.63#ibcon#read 3, iclass 20, count 0 2006.197.08:08:01.63#ibcon#about to read 4, iclass 20, count 0 2006.197.08:08:01.63#ibcon#read 4, iclass 20, count 0 2006.197.08:08:01.63#ibcon#about to read 5, iclass 20, count 0 2006.197.08:08:01.63#ibcon#read 5, iclass 20, count 0 2006.197.08:08:01.63#ibcon#about to read 6, iclass 20, count 0 2006.197.08:08:01.63#ibcon#read 6, iclass 20, count 0 2006.197.08:08:01.63#ibcon#end of sib2, iclass 20, count 0 2006.197.08:08:01.63#ibcon#*after write, iclass 20, count 0 2006.197.08:08:01.63#ibcon#*before return 0, iclass 20, count 0 2006.197.08:08:01.63#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.197.08:08:01.63#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.197.08:08:01.63#ibcon#about to clear, iclass 20 cls_cnt 0 2006.197.08:08:01.63#ibcon#cleared, iclass 20 cls_cnt 0 2006.197.08:08:01.63$vc4f8/vb=4,4 2006.197.08:08:01.63#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.197.08:08:01.63#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.197.08:08:01.63#ibcon#ireg 11 cls_cnt 2 2006.197.08:08:01.63#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.197.08:08:01.69#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.197.08:08:01.69#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.197.08:08:01.69#ibcon#enter wrdev, iclass 22, count 2 2006.197.08:08:01.69#ibcon#first serial, iclass 22, count 2 2006.197.08:08:01.69#ibcon#enter sib2, iclass 22, count 2 2006.197.08:08:01.69#ibcon#flushed, iclass 22, count 2 2006.197.08:08:01.69#ibcon#about to write, iclass 22, count 2 2006.197.08:08:01.69#ibcon#wrote, iclass 22, count 2 2006.197.08:08:01.69#ibcon#about to read 3, iclass 22, count 2 2006.197.08:08:01.71#ibcon#read 3, iclass 22, count 2 2006.197.08:08:01.71#ibcon#about to read 4, iclass 22, count 2 2006.197.08:08:01.71#ibcon#read 4, iclass 22, count 2 2006.197.08:08:01.71#ibcon#about to read 5, iclass 22, count 2 2006.197.08:08:01.71#ibcon#read 5, iclass 22, count 2 2006.197.08:08:01.71#ibcon#about to read 6, iclass 22, count 2 2006.197.08:08:01.71#ibcon#read 6, iclass 22, count 2 2006.197.08:08:01.71#ibcon#end of sib2, iclass 22, count 2 2006.197.08:08:01.71#ibcon#*mode == 0, iclass 22, count 2 2006.197.08:08:01.71#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.197.08:08:01.71#ibcon#[27=AT04-04\r\n] 2006.197.08:08:01.71#ibcon#*before write, iclass 22, count 2 2006.197.08:08:01.71#ibcon#enter sib2, iclass 22, count 2 2006.197.08:08:01.71#ibcon#flushed, iclass 22, count 2 2006.197.08:08:01.71#ibcon#about to write, iclass 22, count 2 2006.197.08:08:01.71#ibcon#wrote, iclass 22, count 2 2006.197.08:08:01.71#ibcon#about to read 3, iclass 22, count 2 2006.197.08:08:01.74#ibcon#read 3, iclass 22, count 2 2006.197.08:08:01.74#ibcon#about to read 4, iclass 22, count 2 2006.197.08:08:01.74#ibcon#read 4, iclass 22, count 2 2006.197.08:08:01.74#ibcon#about to read 5, iclass 22, count 2 2006.197.08:08:01.74#ibcon#read 5, iclass 22, count 2 2006.197.08:08:01.74#ibcon#about to read 6, iclass 22, count 2 2006.197.08:08:01.74#ibcon#read 6, iclass 22, count 2 2006.197.08:08:01.74#ibcon#end of sib2, iclass 22, count 2 2006.197.08:08:01.74#ibcon#*after write, iclass 22, count 2 2006.197.08:08:01.74#ibcon#*before return 0, iclass 22, count 2 2006.197.08:08:01.74#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.197.08:08:01.74#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.197.08:08:01.74#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.197.08:08:01.74#ibcon#ireg 7 cls_cnt 0 2006.197.08:08:01.74#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.197.08:08:01.86#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.197.08:08:01.86#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.197.08:08:01.86#ibcon#enter wrdev, iclass 22, count 0 2006.197.08:08:01.86#ibcon#first serial, iclass 22, count 0 2006.197.08:08:01.86#ibcon#enter sib2, iclass 22, count 0 2006.197.08:08:01.86#ibcon#flushed, iclass 22, count 0 2006.197.08:08:01.86#ibcon#about to write, iclass 22, count 0 2006.197.08:08:01.86#ibcon#wrote, iclass 22, count 0 2006.197.08:08:01.86#ibcon#about to read 3, iclass 22, count 0 2006.197.08:08:01.88#ibcon#read 3, iclass 22, count 0 2006.197.08:08:01.88#ibcon#about to read 4, iclass 22, count 0 2006.197.08:08:01.88#ibcon#read 4, iclass 22, count 0 2006.197.08:08:01.88#ibcon#about to read 5, iclass 22, count 0 2006.197.08:08:01.88#ibcon#read 5, iclass 22, count 0 2006.197.08:08:01.88#ibcon#about to read 6, iclass 22, count 0 2006.197.08:08:01.88#ibcon#read 6, iclass 22, count 0 2006.197.08:08:01.88#ibcon#end of sib2, iclass 22, count 0 2006.197.08:08:01.88#ibcon#*mode == 0, iclass 22, count 0 2006.197.08:08:01.88#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.197.08:08:01.88#ibcon#[27=USB\r\n] 2006.197.08:08:01.88#ibcon#*before write, iclass 22, count 0 2006.197.08:08:01.88#ibcon#enter sib2, iclass 22, count 0 2006.197.08:08:01.88#ibcon#flushed, iclass 22, count 0 2006.197.08:08:01.88#ibcon#about to write, iclass 22, count 0 2006.197.08:08:01.88#ibcon#wrote, iclass 22, count 0 2006.197.08:08:01.88#ibcon#about to read 3, iclass 22, count 0 2006.197.08:08:01.91#ibcon#read 3, iclass 22, count 0 2006.197.08:08:01.91#ibcon#about to read 4, iclass 22, count 0 2006.197.08:08:01.91#ibcon#read 4, iclass 22, count 0 2006.197.08:08:01.91#ibcon#about to read 5, iclass 22, count 0 2006.197.08:08:01.91#ibcon#read 5, iclass 22, count 0 2006.197.08:08:01.91#ibcon#about to read 6, iclass 22, count 0 2006.197.08:08:01.91#ibcon#read 6, iclass 22, count 0 2006.197.08:08:01.91#ibcon#end of sib2, iclass 22, count 0 2006.197.08:08:01.91#ibcon#*after write, iclass 22, count 0 2006.197.08:08:01.91#ibcon#*before return 0, iclass 22, count 0 2006.197.08:08:01.91#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.197.08:08:01.91#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.197.08:08:01.91#ibcon#about to clear, iclass 22 cls_cnt 0 2006.197.08:08:01.91#ibcon#cleared, iclass 22 cls_cnt 0 2006.197.08:08:01.91$vc4f8/vblo=5,744.99 2006.197.08:08:01.91#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.197.08:08:01.91#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.197.08:08:01.91#ibcon#ireg 17 cls_cnt 0 2006.197.08:08:01.91#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.197.08:08:01.91#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.197.08:08:01.91#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.197.08:08:01.91#ibcon#enter wrdev, iclass 24, count 0 2006.197.08:08:01.91#ibcon#first serial, iclass 24, count 0 2006.197.08:08:01.91#ibcon#enter sib2, iclass 24, count 0 2006.197.08:08:01.91#ibcon#flushed, iclass 24, count 0 2006.197.08:08:01.91#ibcon#about to write, iclass 24, count 0 2006.197.08:08:01.91#ibcon#wrote, iclass 24, count 0 2006.197.08:08:01.91#ibcon#about to read 3, iclass 24, count 0 2006.197.08:08:01.93#ibcon#read 3, iclass 24, count 0 2006.197.08:08:01.93#ibcon#about to read 4, iclass 24, count 0 2006.197.08:08:01.93#ibcon#read 4, iclass 24, count 0 2006.197.08:08:01.93#ibcon#about to read 5, iclass 24, count 0 2006.197.08:08:01.93#ibcon#read 5, iclass 24, count 0 2006.197.08:08:01.93#ibcon#about to read 6, iclass 24, count 0 2006.197.08:08:01.93#ibcon#read 6, iclass 24, count 0 2006.197.08:08:01.93#ibcon#end of sib2, iclass 24, count 0 2006.197.08:08:01.93#ibcon#*mode == 0, iclass 24, count 0 2006.197.08:08:01.93#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.197.08:08:01.93#ibcon#[28=FRQ=05,744.99\r\n] 2006.197.08:08:01.93#ibcon#*before write, iclass 24, count 0 2006.197.08:08:01.93#ibcon#enter sib2, iclass 24, count 0 2006.197.08:08:01.93#ibcon#flushed, iclass 24, count 0 2006.197.08:08:01.93#ibcon#about to write, iclass 24, count 0 2006.197.08:08:01.93#ibcon#wrote, iclass 24, count 0 2006.197.08:08:01.93#ibcon#about to read 3, iclass 24, count 0 2006.197.08:08:01.97#ibcon#read 3, iclass 24, count 0 2006.197.08:08:01.97#ibcon#about to read 4, iclass 24, count 0 2006.197.08:08:01.97#ibcon#read 4, iclass 24, count 0 2006.197.08:08:01.97#ibcon#about to read 5, iclass 24, count 0 2006.197.08:08:01.97#ibcon#read 5, iclass 24, count 0 2006.197.08:08:01.97#ibcon#about to read 6, iclass 24, count 0 2006.197.08:08:01.97#ibcon#read 6, iclass 24, count 0 2006.197.08:08:01.97#ibcon#end of sib2, iclass 24, count 0 2006.197.08:08:01.97#ibcon#*after write, iclass 24, count 0 2006.197.08:08:01.97#ibcon#*before return 0, iclass 24, count 0 2006.197.08:08:01.97#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.197.08:08:01.97#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.197.08:08:01.97#ibcon#about to clear, iclass 24 cls_cnt 0 2006.197.08:08:01.97#ibcon#cleared, iclass 24 cls_cnt 0 2006.197.08:08:01.97$vc4f8/vb=5,4 2006.197.08:08:01.97#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.197.08:08:01.97#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.197.08:08:01.97#ibcon#ireg 11 cls_cnt 2 2006.197.08:08:01.97#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.197.08:08:02.03#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.197.08:08:02.03#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.197.08:08:02.03#ibcon#enter wrdev, iclass 26, count 2 2006.197.08:08:02.03#ibcon#first serial, iclass 26, count 2 2006.197.08:08:02.03#ibcon#enter sib2, iclass 26, count 2 2006.197.08:08:02.03#ibcon#flushed, iclass 26, count 2 2006.197.08:08:02.03#ibcon#about to write, iclass 26, count 2 2006.197.08:08:02.03#ibcon#wrote, iclass 26, count 2 2006.197.08:08:02.03#ibcon#about to read 3, iclass 26, count 2 2006.197.08:08:02.05#ibcon#read 3, iclass 26, count 2 2006.197.08:08:02.05#ibcon#about to read 4, iclass 26, count 2 2006.197.08:08:02.05#ibcon#read 4, iclass 26, count 2 2006.197.08:08:02.05#ibcon#about to read 5, iclass 26, count 2 2006.197.08:08:02.05#ibcon#read 5, iclass 26, count 2 2006.197.08:08:02.05#ibcon#about to read 6, iclass 26, count 2 2006.197.08:08:02.05#ibcon#read 6, iclass 26, count 2 2006.197.08:08:02.05#ibcon#end of sib2, iclass 26, count 2 2006.197.08:08:02.05#ibcon#*mode == 0, iclass 26, count 2 2006.197.08:08:02.05#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.197.08:08:02.05#ibcon#[27=AT05-04\r\n] 2006.197.08:08:02.05#ibcon#*before write, iclass 26, count 2 2006.197.08:08:02.05#ibcon#enter sib2, iclass 26, count 2 2006.197.08:08:02.05#ibcon#flushed, iclass 26, count 2 2006.197.08:08:02.05#ibcon#about to write, iclass 26, count 2 2006.197.08:08:02.05#ibcon#wrote, iclass 26, count 2 2006.197.08:08:02.05#ibcon#about to read 3, iclass 26, count 2 2006.197.08:08:02.08#ibcon#read 3, iclass 26, count 2 2006.197.08:08:02.08#ibcon#about to read 4, iclass 26, count 2 2006.197.08:08:02.08#ibcon#read 4, iclass 26, count 2 2006.197.08:08:02.08#ibcon#about to read 5, iclass 26, count 2 2006.197.08:08:02.08#ibcon#read 5, iclass 26, count 2 2006.197.08:08:02.08#ibcon#about to read 6, iclass 26, count 2 2006.197.08:08:02.08#ibcon#read 6, iclass 26, count 2 2006.197.08:08:02.08#ibcon#end of sib2, iclass 26, count 2 2006.197.08:08:02.08#ibcon#*after write, iclass 26, count 2 2006.197.08:08:02.08#ibcon#*before return 0, iclass 26, count 2 2006.197.08:08:02.08#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.197.08:08:02.08#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.197.08:08:02.08#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.197.08:08:02.08#ibcon#ireg 7 cls_cnt 0 2006.197.08:08:02.08#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.197.08:08:02.20#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.197.08:08:02.20#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.197.08:08:02.20#ibcon#enter wrdev, iclass 26, count 0 2006.197.08:08:02.20#ibcon#first serial, iclass 26, count 0 2006.197.08:08:02.20#ibcon#enter sib2, iclass 26, count 0 2006.197.08:08:02.20#ibcon#flushed, iclass 26, count 0 2006.197.08:08:02.20#ibcon#about to write, iclass 26, count 0 2006.197.08:08:02.20#ibcon#wrote, iclass 26, count 0 2006.197.08:08:02.20#ibcon#about to read 3, iclass 26, count 0 2006.197.08:08:02.22#ibcon#read 3, iclass 26, count 0 2006.197.08:08:02.22#ibcon#about to read 4, iclass 26, count 0 2006.197.08:08:02.22#ibcon#read 4, iclass 26, count 0 2006.197.08:08:02.22#ibcon#about to read 5, iclass 26, count 0 2006.197.08:08:02.22#ibcon#read 5, iclass 26, count 0 2006.197.08:08:02.22#ibcon#about to read 6, iclass 26, count 0 2006.197.08:08:02.22#ibcon#read 6, iclass 26, count 0 2006.197.08:08:02.22#ibcon#end of sib2, iclass 26, count 0 2006.197.08:08:02.22#ibcon#*mode == 0, iclass 26, count 0 2006.197.08:08:02.22#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.197.08:08:02.22#ibcon#[27=USB\r\n] 2006.197.08:08:02.22#ibcon#*before write, iclass 26, count 0 2006.197.08:08:02.22#ibcon#enter sib2, iclass 26, count 0 2006.197.08:08:02.22#ibcon#flushed, iclass 26, count 0 2006.197.08:08:02.22#ibcon#about to write, iclass 26, count 0 2006.197.08:08:02.22#ibcon#wrote, iclass 26, count 0 2006.197.08:08:02.22#ibcon#about to read 3, iclass 26, count 0 2006.197.08:08:02.25#ibcon#read 3, iclass 26, count 0 2006.197.08:08:02.25#ibcon#about to read 4, iclass 26, count 0 2006.197.08:08:02.25#ibcon#read 4, iclass 26, count 0 2006.197.08:08:02.25#ibcon#about to read 5, iclass 26, count 0 2006.197.08:08:02.25#ibcon#read 5, iclass 26, count 0 2006.197.08:08:02.25#ibcon#about to read 6, iclass 26, count 0 2006.197.08:08:02.25#ibcon#read 6, iclass 26, count 0 2006.197.08:08:02.25#ibcon#end of sib2, iclass 26, count 0 2006.197.08:08:02.25#ibcon#*after write, iclass 26, count 0 2006.197.08:08:02.25#ibcon#*before return 0, iclass 26, count 0 2006.197.08:08:02.25#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.197.08:08:02.25#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.197.08:08:02.25#ibcon#about to clear, iclass 26 cls_cnt 0 2006.197.08:08:02.25#ibcon#cleared, iclass 26 cls_cnt 0 2006.197.08:08:02.25$vc4f8/vblo=6,752.99 2006.197.08:08:02.25#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.197.08:08:02.25#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.197.08:08:02.25#ibcon#ireg 17 cls_cnt 0 2006.197.08:08:02.25#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.197.08:08:02.25#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.197.08:08:02.25#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.197.08:08:02.25#ibcon#enter wrdev, iclass 28, count 0 2006.197.08:08:02.25#ibcon#first serial, iclass 28, count 0 2006.197.08:08:02.25#ibcon#enter sib2, iclass 28, count 0 2006.197.08:08:02.25#ibcon#flushed, iclass 28, count 0 2006.197.08:08:02.25#ibcon#about to write, iclass 28, count 0 2006.197.08:08:02.25#ibcon#wrote, iclass 28, count 0 2006.197.08:08:02.25#ibcon#about to read 3, iclass 28, count 0 2006.197.08:08:02.27#ibcon#read 3, iclass 28, count 0 2006.197.08:08:02.27#ibcon#about to read 4, iclass 28, count 0 2006.197.08:08:02.27#ibcon#read 4, iclass 28, count 0 2006.197.08:08:02.27#ibcon#about to read 5, iclass 28, count 0 2006.197.08:08:02.27#ibcon#read 5, iclass 28, count 0 2006.197.08:08:02.27#ibcon#about to read 6, iclass 28, count 0 2006.197.08:08:02.27#ibcon#read 6, iclass 28, count 0 2006.197.08:08:02.27#ibcon#end of sib2, iclass 28, count 0 2006.197.08:08:02.27#ibcon#*mode == 0, iclass 28, count 0 2006.197.08:08:02.27#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.197.08:08:02.27#ibcon#[28=FRQ=06,752.99\r\n] 2006.197.08:08:02.27#ibcon#*before write, iclass 28, count 0 2006.197.08:08:02.27#ibcon#enter sib2, iclass 28, count 0 2006.197.08:08:02.27#ibcon#flushed, iclass 28, count 0 2006.197.08:08:02.27#ibcon#about to write, iclass 28, count 0 2006.197.08:08:02.27#ibcon#wrote, iclass 28, count 0 2006.197.08:08:02.27#ibcon#about to read 3, iclass 28, count 0 2006.197.08:08:02.31#ibcon#read 3, iclass 28, count 0 2006.197.08:08:02.31#ibcon#about to read 4, iclass 28, count 0 2006.197.08:08:02.31#ibcon#read 4, iclass 28, count 0 2006.197.08:08:02.31#ibcon#about to read 5, iclass 28, count 0 2006.197.08:08:02.31#ibcon#read 5, iclass 28, count 0 2006.197.08:08:02.31#ibcon#about to read 6, iclass 28, count 0 2006.197.08:08:02.31#ibcon#read 6, iclass 28, count 0 2006.197.08:08:02.31#ibcon#end of sib2, iclass 28, count 0 2006.197.08:08:02.31#ibcon#*after write, iclass 28, count 0 2006.197.08:08:02.31#ibcon#*before return 0, iclass 28, count 0 2006.197.08:08:02.31#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.197.08:08:02.31#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.197.08:08:02.31#ibcon#about to clear, iclass 28 cls_cnt 0 2006.197.08:08:02.31#ibcon#cleared, iclass 28 cls_cnt 0 2006.197.08:08:02.31$vc4f8/vb=6,4 2006.197.08:08:02.31#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.197.08:08:02.31#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.197.08:08:02.31#ibcon#ireg 11 cls_cnt 2 2006.197.08:08:02.31#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.197.08:08:02.37#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.197.08:08:02.37#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.197.08:08:02.37#ibcon#enter wrdev, iclass 30, count 2 2006.197.08:08:02.37#ibcon#first serial, iclass 30, count 2 2006.197.08:08:02.37#ibcon#enter sib2, iclass 30, count 2 2006.197.08:08:02.37#ibcon#flushed, iclass 30, count 2 2006.197.08:08:02.37#ibcon#about to write, iclass 30, count 2 2006.197.08:08:02.37#ibcon#wrote, iclass 30, count 2 2006.197.08:08:02.37#ibcon#about to read 3, iclass 30, count 2 2006.197.08:08:02.39#ibcon#read 3, iclass 30, count 2 2006.197.08:08:02.39#ibcon#about to read 4, iclass 30, count 2 2006.197.08:08:02.39#ibcon#read 4, iclass 30, count 2 2006.197.08:08:02.39#ibcon#about to read 5, iclass 30, count 2 2006.197.08:08:02.39#ibcon#read 5, iclass 30, count 2 2006.197.08:08:02.39#ibcon#about to read 6, iclass 30, count 2 2006.197.08:08:02.39#ibcon#read 6, iclass 30, count 2 2006.197.08:08:02.39#ibcon#end of sib2, iclass 30, count 2 2006.197.08:08:02.39#ibcon#*mode == 0, iclass 30, count 2 2006.197.08:08:02.39#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.197.08:08:02.39#ibcon#[27=AT06-04\r\n] 2006.197.08:08:02.39#ibcon#*before write, iclass 30, count 2 2006.197.08:08:02.39#ibcon#enter sib2, iclass 30, count 2 2006.197.08:08:02.39#ibcon#flushed, iclass 30, count 2 2006.197.08:08:02.39#ibcon#about to write, iclass 30, count 2 2006.197.08:08:02.39#ibcon#wrote, iclass 30, count 2 2006.197.08:08:02.39#ibcon#about to read 3, iclass 30, count 2 2006.197.08:08:02.42#ibcon#read 3, iclass 30, count 2 2006.197.08:08:02.42#ibcon#about to read 4, iclass 30, count 2 2006.197.08:08:02.42#ibcon#read 4, iclass 30, count 2 2006.197.08:08:02.42#ibcon#about to read 5, iclass 30, count 2 2006.197.08:08:02.42#ibcon#read 5, iclass 30, count 2 2006.197.08:08:02.42#ibcon#about to read 6, iclass 30, count 2 2006.197.08:08:02.42#ibcon#read 6, iclass 30, count 2 2006.197.08:08:02.42#ibcon#end of sib2, iclass 30, count 2 2006.197.08:08:02.42#ibcon#*after write, iclass 30, count 2 2006.197.08:08:02.42#ibcon#*before return 0, iclass 30, count 2 2006.197.08:08:02.42#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.197.08:08:02.42#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.197.08:08:02.42#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.197.08:08:02.42#ibcon#ireg 7 cls_cnt 0 2006.197.08:08:02.42#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.197.08:08:02.54#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.197.08:08:02.54#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.197.08:08:02.54#ibcon#enter wrdev, iclass 30, count 0 2006.197.08:08:02.54#ibcon#first serial, iclass 30, count 0 2006.197.08:08:02.54#ibcon#enter sib2, iclass 30, count 0 2006.197.08:08:02.54#ibcon#flushed, iclass 30, count 0 2006.197.08:08:02.54#ibcon#about to write, iclass 30, count 0 2006.197.08:08:02.54#ibcon#wrote, iclass 30, count 0 2006.197.08:08:02.54#ibcon#about to read 3, iclass 30, count 0 2006.197.08:08:02.56#ibcon#read 3, iclass 30, count 0 2006.197.08:08:02.56#ibcon#about to read 4, iclass 30, count 0 2006.197.08:08:02.56#ibcon#read 4, iclass 30, count 0 2006.197.08:08:02.56#ibcon#about to read 5, iclass 30, count 0 2006.197.08:08:02.56#ibcon#read 5, iclass 30, count 0 2006.197.08:08:02.56#ibcon#about to read 6, iclass 30, count 0 2006.197.08:08:02.56#ibcon#read 6, iclass 30, count 0 2006.197.08:08:02.56#ibcon#end of sib2, iclass 30, count 0 2006.197.08:08:02.56#ibcon#*mode == 0, iclass 30, count 0 2006.197.08:08:02.56#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.197.08:08:02.56#ibcon#[27=USB\r\n] 2006.197.08:08:02.56#ibcon#*before write, iclass 30, count 0 2006.197.08:08:02.56#ibcon#enter sib2, iclass 30, count 0 2006.197.08:08:02.56#ibcon#flushed, iclass 30, count 0 2006.197.08:08:02.56#ibcon#about to write, iclass 30, count 0 2006.197.08:08:02.56#ibcon#wrote, iclass 30, count 0 2006.197.08:08:02.56#ibcon#about to read 3, iclass 30, count 0 2006.197.08:08:02.59#ibcon#read 3, iclass 30, count 0 2006.197.08:08:02.59#ibcon#about to read 4, iclass 30, count 0 2006.197.08:08:02.59#ibcon#read 4, iclass 30, count 0 2006.197.08:08:02.59#ibcon#about to read 5, iclass 30, count 0 2006.197.08:08:02.59#ibcon#read 5, iclass 30, count 0 2006.197.08:08:02.59#ibcon#about to read 6, iclass 30, count 0 2006.197.08:08:02.59#ibcon#read 6, iclass 30, count 0 2006.197.08:08:02.59#ibcon#end of sib2, iclass 30, count 0 2006.197.08:08:02.59#ibcon#*after write, iclass 30, count 0 2006.197.08:08:02.59#ibcon#*before return 0, iclass 30, count 0 2006.197.08:08:02.59#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.197.08:08:02.59#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.197.08:08:02.59#ibcon#about to clear, iclass 30 cls_cnt 0 2006.197.08:08:02.59#ibcon#cleared, iclass 30 cls_cnt 0 2006.197.08:08:02.59$vc4f8/vabw=wide 2006.197.08:08:02.59#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.197.08:08:02.59#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.197.08:08:02.59#ibcon#ireg 8 cls_cnt 0 2006.197.08:08:02.59#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.197.08:08:02.59#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.197.08:08:02.59#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.197.08:08:02.59#ibcon#enter wrdev, iclass 32, count 0 2006.197.08:08:02.59#ibcon#first serial, iclass 32, count 0 2006.197.08:08:02.59#ibcon#enter sib2, iclass 32, count 0 2006.197.08:08:02.59#ibcon#flushed, iclass 32, count 0 2006.197.08:08:02.59#ibcon#about to write, iclass 32, count 0 2006.197.08:08:02.59#ibcon#wrote, iclass 32, count 0 2006.197.08:08:02.59#ibcon#about to read 3, iclass 32, count 0 2006.197.08:08:02.61#ibcon#read 3, iclass 32, count 0 2006.197.08:08:02.61#ibcon#about to read 4, iclass 32, count 0 2006.197.08:08:02.61#ibcon#read 4, iclass 32, count 0 2006.197.08:08:02.61#ibcon#about to read 5, iclass 32, count 0 2006.197.08:08:02.61#ibcon#read 5, iclass 32, count 0 2006.197.08:08:02.61#ibcon#about to read 6, iclass 32, count 0 2006.197.08:08:02.61#ibcon#read 6, iclass 32, count 0 2006.197.08:08:02.61#ibcon#end of sib2, iclass 32, count 0 2006.197.08:08:02.61#ibcon#*mode == 0, iclass 32, count 0 2006.197.08:08:02.61#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.197.08:08:02.61#ibcon#[25=BW32\r\n] 2006.197.08:08:02.61#ibcon#*before write, iclass 32, count 0 2006.197.08:08:02.61#ibcon#enter sib2, iclass 32, count 0 2006.197.08:08:02.61#ibcon#flushed, iclass 32, count 0 2006.197.08:08:02.61#ibcon#about to write, iclass 32, count 0 2006.197.08:08:02.61#ibcon#wrote, iclass 32, count 0 2006.197.08:08:02.61#ibcon#about to read 3, iclass 32, count 0 2006.197.08:08:02.64#ibcon#read 3, iclass 32, count 0 2006.197.08:08:02.64#ibcon#about to read 4, iclass 32, count 0 2006.197.08:08:02.64#ibcon#read 4, iclass 32, count 0 2006.197.08:08:02.64#ibcon#about to read 5, iclass 32, count 0 2006.197.08:08:02.64#ibcon#read 5, iclass 32, count 0 2006.197.08:08:02.64#ibcon#about to read 6, iclass 32, count 0 2006.197.08:08:02.64#ibcon#read 6, iclass 32, count 0 2006.197.08:08:02.64#ibcon#end of sib2, iclass 32, count 0 2006.197.08:08:02.64#ibcon#*after write, iclass 32, count 0 2006.197.08:08:02.64#ibcon#*before return 0, iclass 32, count 0 2006.197.08:08:02.64#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.197.08:08:02.64#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.197.08:08:02.64#ibcon#about to clear, iclass 32 cls_cnt 0 2006.197.08:08:02.64#ibcon#cleared, iclass 32 cls_cnt 0 2006.197.08:08:02.64$vc4f8/vbbw=wide 2006.197.08:08:02.64#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.197.08:08:02.64#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.197.08:08:02.64#ibcon#ireg 8 cls_cnt 0 2006.197.08:08:02.64#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.197.08:08:02.71#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.197.08:08:02.71#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.197.08:08:02.71#ibcon#enter wrdev, iclass 34, count 0 2006.197.08:08:02.71#ibcon#first serial, iclass 34, count 0 2006.197.08:08:02.71#ibcon#enter sib2, iclass 34, count 0 2006.197.08:08:02.71#ibcon#flushed, iclass 34, count 0 2006.197.08:08:02.71#ibcon#about to write, iclass 34, count 0 2006.197.08:08:02.71#ibcon#wrote, iclass 34, count 0 2006.197.08:08:02.71#ibcon#about to read 3, iclass 34, count 0 2006.197.08:08:02.73#ibcon#read 3, iclass 34, count 0 2006.197.08:08:02.73#ibcon#about to read 4, iclass 34, count 0 2006.197.08:08:02.73#ibcon#read 4, iclass 34, count 0 2006.197.08:08:02.73#ibcon#about to read 5, iclass 34, count 0 2006.197.08:08:02.73#ibcon#read 5, iclass 34, count 0 2006.197.08:08:02.73#ibcon#about to read 6, iclass 34, count 0 2006.197.08:08:02.73#ibcon#read 6, iclass 34, count 0 2006.197.08:08:02.73#ibcon#end of sib2, iclass 34, count 0 2006.197.08:08:02.73#ibcon#*mode == 0, iclass 34, count 0 2006.197.08:08:02.73#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.197.08:08:02.73#ibcon#[27=BW32\r\n] 2006.197.08:08:02.73#ibcon#*before write, iclass 34, count 0 2006.197.08:08:02.73#ibcon#enter sib2, iclass 34, count 0 2006.197.08:08:02.73#ibcon#flushed, iclass 34, count 0 2006.197.08:08:02.73#ibcon#about to write, iclass 34, count 0 2006.197.08:08:02.73#ibcon#wrote, iclass 34, count 0 2006.197.08:08:02.73#ibcon#about to read 3, iclass 34, count 0 2006.197.08:08:02.76#ibcon#read 3, iclass 34, count 0 2006.197.08:08:02.76#ibcon#about to read 4, iclass 34, count 0 2006.197.08:08:02.76#ibcon#read 4, iclass 34, count 0 2006.197.08:08:02.76#ibcon#about to read 5, iclass 34, count 0 2006.197.08:08:02.76#ibcon#read 5, iclass 34, count 0 2006.197.08:08:02.76#ibcon#about to read 6, iclass 34, count 0 2006.197.08:08:02.76#ibcon#read 6, iclass 34, count 0 2006.197.08:08:02.76#ibcon#end of sib2, iclass 34, count 0 2006.197.08:08:02.76#ibcon#*after write, iclass 34, count 0 2006.197.08:08:02.76#ibcon#*before return 0, iclass 34, count 0 2006.197.08:08:02.76#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.197.08:08:02.76#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.197.08:08:02.76#ibcon#about to clear, iclass 34 cls_cnt 0 2006.197.08:08:02.76#ibcon#cleared, iclass 34 cls_cnt 0 2006.197.08:08:02.76$4f8m12a/ifd4f 2006.197.08:08:02.76$ifd4f/lo= 2006.197.08:08:02.76$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.197.08:08:02.76$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.197.08:08:02.76$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.197.08:08:02.76$ifd4f/patch= 2006.197.08:08:02.76$ifd4f/patch=lo1,a1,a2,a3,a4 2006.197.08:08:02.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.197.08:08:02.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.197.08:08:02.76$4f8m12a/"form=m,16.000,1:2 2006.197.08:08:02.76$4f8m12a/"tpicd 2006.197.08:08:02.76$4f8m12a/echo=off 2006.197.08:08:02.76$4f8m12a/xlog=off 2006.197.08:08:02.76:!2006.197.08:08:30 2006.197.08:08:12.14#trakl#Source acquired 2006.197.08:08:12.14#flagr#flagr/antenna,acquired 2006.197.08:08:30.00:preob 2006.197.08:08:31.14/onsource/TRACKING 2006.197.08:08:31.14:!2006.197.08:08:40 2006.197.08:08:40.00:data_valid=on 2006.197.08:08:40.00:midob 2006.197.08:08:40.14/onsource/TRACKING 2006.197.08:08:40.14/wx/25.65,1002.8,96 2006.197.08:08:40.34/cable/+6.3712E-03 2006.197.08:08:41.43/va/01,08,usb,yes,31,32 2006.197.08:08:41.43/va/02,07,usb,yes,31,32 2006.197.08:08:41.43/va/03,06,usb,yes,33,33 2006.197.08:08:41.43/va/04,07,usb,yes,32,34 2006.197.08:08:41.43/va/05,07,usb,yes,36,38 2006.197.08:08:41.43/va/06,06,usb,yes,35,35 2006.197.08:08:41.43/va/07,06,usb,yes,36,36 2006.197.08:08:41.43/va/08,07,usb,yes,34,33 2006.197.08:08:41.66/valo/01,532.99,yes,locked 2006.197.08:08:41.66/valo/02,572.99,yes,locked 2006.197.08:08:41.66/valo/03,672.99,yes,locked 2006.197.08:08:41.66/valo/04,832.99,yes,locked 2006.197.08:08:41.66/valo/05,652.99,yes,locked 2006.197.08:08:41.66/valo/06,772.99,yes,locked 2006.197.08:08:41.66/valo/07,832.99,yes,locked 2006.197.08:08:41.66/valo/08,852.99,yes,locked 2006.197.08:08:42.75/vb/01,04,usb,yes,30,28 2006.197.08:08:42.75/vb/02,04,usb,yes,32,33 2006.197.08:08:42.75/vb/03,04,usb,yes,28,32 2006.197.08:08:42.75/vb/04,04,usb,yes,29,29 2006.197.08:08:42.75/vb/05,04,usb,yes,27,31 2006.197.08:08:42.75/vb/06,04,usb,yes,28,31 2006.197.08:08:42.75/vb/07,04,usb,yes,30,30 2006.197.08:08:42.75/vb/08,04,usb,yes,28,31 2006.197.08:08:42.98/vblo/01,632.99,yes,locked 2006.197.08:08:42.98/vblo/02,640.99,yes,locked 2006.197.08:08:42.98/vblo/03,656.99,yes,locked 2006.197.08:08:42.98/vblo/04,712.99,yes,locked 2006.197.08:08:42.98/vblo/05,744.99,yes,locked 2006.197.08:08:42.98/vblo/06,752.99,yes,locked 2006.197.08:08:42.98/vblo/07,734.99,yes,locked 2006.197.08:08:42.98/vblo/08,744.99,yes,locked 2006.197.08:08:43.13/vabw/8 2006.197.08:08:43.28/vbbw/8 2006.197.08:08:43.37/xfe/off,on,15.5 2006.197.08:08:43.75/ifatt/23,28,28,28 2006.197.08:08:44.09/fmout-gps/S +3.01E-07 2006.197.08:08:44.13:!2006.197.08:09:40 2006.197.08:09:40.00:data_valid=off 2006.197.08:09:40.00:postob 2006.197.08:09:40.06/cable/+6.3714E-03 2006.197.08:09:40.06/wx/25.64,1002.8,96 2006.197.08:09:41.10/fmout-gps/S +3.01E-07 2006.197.08:09:41.10:scan_name=197-0810,k06197,60 2006.197.08:09:41.10:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.197.08:09:41.14#flagr#flagr/antenna,new-source 2006.197.08:09:42.14:checkk5 2006.197.08:09:42.48/chk_autoobs//k5ts1/ autoobs is running! 2006.197.08:09:42.82/chk_autoobs//k5ts2/ autoobs is running! 2006.197.08:09:43.49/chk_autoobs//k5ts3/ autoobs is running! 2006.197.08:09:43.83/chk_autoobs//k5ts4/ autoobs is running! 2006.197.08:09:44.16/chk_obsdata//k5ts1/T1970808??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.08:09:44.50/chk_obsdata//k5ts2/T1970808??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.08:09:44.84/chk_obsdata//k5ts3/T1970808??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.08:09:45.18/chk_obsdata//k5ts4/T1970808??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.08:09:45.84/k5log//k5ts1_log_newline 2006.197.08:09:46.49/k5log//k5ts2_log_newline 2006.197.08:09:47.15/k5log//k5ts3_log_newline 2006.197.08:09:47.81/k5log//k5ts4_log_newline 2006.197.08:09:47.83/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.197.08:09:47.83:4f8m12a=2 2006.197.08:09:47.84$4f8m12a/echo=on 2006.197.08:09:47.84$4f8m12a/pcalon 2006.197.08:09:47.84$pcalon/"no phase cal control is implemented here 2006.197.08:09:47.84$4f8m12a/"tpicd=stop 2006.197.08:09:47.84$4f8m12a/vc4f8 2006.197.08:09:47.84$vc4f8/valo=1,532.99 2006.197.08:09:47.84#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.197.08:09:47.84#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.197.08:09:47.84#ibcon#ireg 17 cls_cnt 0 2006.197.08:09:47.84#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.197.08:09:47.84#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.197.08:09:47.84#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.197.08:09:47.84#ibcon#enter wrdev, iclass 3, count 0 2006.197.08:09:47.84#ibcon#first serial, iclass 3, count 0 2006.197.08:09:47.84#ibcon#enter sib2, iclass 3, count 0 2006.197.08:09:47.84#ibcon#flushed, iclass 3, count 0 2006.197.08:09:47.84#ibcon#about to write, iclass 3, count 0 2006.197.08:09:47.84#ibcon#wrote, iclass 3, count 0 2006.197.08:09:47.84#ibcon#about to read 3, iclass 3, count 0 2006.197.08:09:47.86#ibcon#read 3, iclass 3, count 0 2006.197.08:09:47.86#ibcon#about to read 4, iclass 3, count 0 2006.197.08:09:47.86#ibcon#read 4, iclass 3, count 0 2006.197.08:09:47.86#ibcon#about to read 5, iclass 3, count 0 2006.197.08:09:47.86#ibcon#read 5, iclass 3, count 0 2006.197.08:09:47.86#ibcon#about to read 6, iclass 3, count 0 2006.197.08:09:47.86#ibcon#read 6, iclass 3, count 0 2006.197.08:09:47.86#ibcon#end of sib2, iclass 3, count 0 2006.197.08:09:47.86#ibcon#*mode == 0, iclass 3, count 0 2006.197.08:09:47.86#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.197.08:09:47.86#ibcon#[26=FRQ=01,532.99\r\n] 2006.197.08:09:47.86#ibcon#*before write, iclass 3, count 0 2006.197.08:09:47.86#ibcon#enter sib2, iclass 3, count 0 2006.197.08:09:47.86#ibcon#flushed, iclass 3, count 0 2006.197.08:09:47.86#ibcon#about to write, iclass 3, count 0 2006.197.08:09:47.86#ibcon#wrote, iclass 3, count 0 2006.197.08:09:47.86#ibcon#about to read 3, iclass 3, count 0 2006.197.08:09:47.91#ibcon#read 3, iclass 3, count 0 2006.197.08:09:47.91#ibcon#about to read 4, iclass 3, count 0 2006.197.08:09:47.91#ibcon#read 4, iclass 3, count 0 2006.197.08:09:47.91#ibcon#about to read 5, iclass 3, count 0 2006.197.08:09:47.91#ibcon#read 5, iclass 3, count 0 2006.197.08:09:47.91#ibcon#about to read 6, iclass 3, count 0 2006.197.08:09:47.91#ibcon#read 6, iclass 3, count 0 2006.197.08:09:47.91#ibcon#end of sib2, iclass 3, count 0 2006.197.08:09:47.91#ibcon#*after write, iclass 3, count 0 2006.197.08:09:47.91#ibcon#*before return 0, iclass 3, count 0 2006.197.08:09:47.91#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.197.08:09:47.91#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.197.08:09:47.91#ibcon#about to clear, iclass 3 cls_cnt 0 2006.197.08:09:47.91#ibcon#cleared, iclass 3 cls_cnt 0 2006.197.08:09:47.91$vc4f8/va=1,8 2006.197.08:09:47.91#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.197.08:09:47.91#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.197.08:09:47.91#ibcon#ireg 11 cls_cnt 2 2006.197.08:09:47.91#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.197.08:09:47.91#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.197.08:09:47.91#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.197.08:09:47.91#ibcon#enter wrdev, iclass 5, count 2 2006.197.08:09:47.91#ibcon#first serial, iclass 5, count 2 2006.197.08:09:47.91#ibcon#enter sib2, iclass 5, count 2 2006.197.08:09:47.91#ibcon#flushed, iclass 5, count 2 2006.197.08:09:47.91#ibcon#about to write, iclass 5, count 2 2006.197.08:09:47.91#ibcon#wrote, iclass 5, count 2 2006.197.08:09:47.91#ibcon#about to read 3, iclass 5, count 2 2006.197.08:09:47.93#ibcon#read 3, iclass 5, count 2 2006.197.08:09:47.93#ibcon#about to read 4, iclass 5, count 2 2006.197.08:09:47.93#ibcon#read 4, iclass 5, count 2 2006.197.08:09:47.93#ibcon#about to read 5, iclass 5, count 2 2006.197.08:09:47.93#ibcon#read 5, iclass 5, count 2 2006.197.08:09:47.93#ibcon#about to read 6, iclass 5, count 2 2006.197.08:09:47.93#ibcon#read 6, iclass 5, count 2 2006.197.08:09:47.93#ibcon#end of sib2, iclass 5, count 2 2006.197.08:09:47.93#ibcon#*mode == 0, iclass 5, count 2 2006.197.08:09:47.93#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.197.08:09:47.93#ibcon#[25=AT01-08\r\n] 2006.197.08:09:47.93#ibcon#*before write, iclass 5, count 2 2006.197.08:09:47.93#ibcon#enter sib2, iclass 5, count 2 2006.197.08:09:47.93#ibcon#flushed, iclass 5, count 2 2006.197.08:09:47.93#ibcon#about to write, iclass 5, count 2 2006.197.08:09:47.93#ibcon#wrote, iclass 5, count 2 2006.197.08:09:47.93#ibcon#about to read 3, iclass 5, count 2 2006.197.08:09:47.96#ibcon#read 3, iclass 5, count 2 2006.197.08:09:47.96#ibcon#about to read 4, iclass 5, count 2 2006.197.08:09:47.96#ibcon#read 4, iclass 5, count 2 2006.197.08:09:47.96#ibcon#about to read 5, iclass 5, count 2 2006.197.08:09:47.96#ibcon#read 5, iclass 5, count 2 2006.197.08:09:47.96#ibcon#about to read 6, iclass 5, count 2 2006.197.08:09:47.96#ibcon#read 6, iclass 5, count 2 2006.197.08:09:47.96#ibcon#end of sib2, iclass 5, count 2 2006.197.08:09:47.96#ibcon#*after write, iclass 5, count 2 2006.197.08:09:47.96#ibcon#*before return 0, iclass 5, count 2 2006.197.08:09:47.96#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.197.08:09:47.96#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.197.08:09:47.96#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.197.08:09:47.96#ibcon#ireg 7 cls_cnt 0 2006.197.08:09:47.96#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.197.08:09:48.08#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.197.08:09:48.08#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.197.08:09:48.08#ibcon#enter wrdev, iclass 5, count 0 2006.197.08:09:48.08#ibcon#first serial, iclass 5, count 0 2006.197.08:09:48.08#ibcon#enter sib2, iclass 5, count 0 2006.197.08:09:48.08#ibcon#flushed, iclass 5, count 0 2006.197.08:09:48.08#ibcon#about to write, iclass 5, count 0 2006.197.08:09:48.08#ibcon#wrote, iclass 5, count 0 2006.197.08:09:48.08#ibcon#about to read 3, iclass 5, count 0 2006.197.08:09:48.10#ibcon#read 3, iclass 5, count 0 2006.197.08:09:48.10#ibcon#about to read 4, iclass 5, count 0 2006.197.08:09:48.10#ibcon#read 4, iclass 5, count 0 2006.197.08:09:48.10#ibcon#about to read 5, iclass 5, count 0 2006.197.08:09:48.10#ibcon#read 5, iclass 5, count 0 2006.197.08:09:48.10#ibcon#about to read 6, iclass 5, count 0 2006.197.08:09:48.10#ibcon#read 6, iclass 5, count 0 2006.197.08:09:48.10#ibcon#end of sib2, iclass 5, count 0 2006.197.08:09:48.10#ibcon#*mode == 0, iclass 5, count 0 2006.197.08:09:48.10#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.197.08:09:48.10#ibcon#[25=USB\r\n] 2006.197.08:09:48.10#ibcon#*before write, iclass 5, count 0 2006.197.08:09:48.10#ibcon#enter sib2, iclass 5, count 0 2006.197.08:09:48.10#ibcon#flushed, iclass 5, count 0 2006.197.08:09:48.10#ibcon#about to write, iclass 5, count 0 2006.197.08:09:48.10#ibcon#wrote, iclass 5, count 0 2006.197.08:09:48.10#ibcon#about to read 3, iclass 5, count 0 2006.197.08:09:48.13#ibcon#read 3, iclass 5, count 0 2006.197.08:09:48.13#ibcon#about to read 4, iclass 5, count 0 2006.197.08:09:48.13#ibcon#read 4, iclass 5, count 0 2006.197.08:09:48.13#ibcon#about to read 5, iclass 5, count 0 2006.197.08:09:48.13#ibcon#read 5, iclass 5, count 0 2006.197.08:09:48.13#ibcon#about to read 6, iclass 5, count 0 2006.197.08:09:48.13#ibcon#read 6, iclass 5, count 0 2006.197.08:09:48.13#ibcon#end of sib2, iclass 5, count 0 2006.197.08:09:48.13#ibcon#*after write, iclass 5, count 0 2006.197.08:09:48.13#ibcon#*before return 0, iclass 5, count 0 2006.197.08:09:48.13#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.197.08:09:48.13#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.197.08:09:48.13#ibcon#about to clear, iclass 5 cls_cnt 0 2006.197.08:09:48.13#ibcon#cleared, iclass 5 cls_cnt 0 2006.197.08:09:48.13$vc4f8/valo=2,572.99 2006.197.08:09:48.13#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.197.08:09:48.13#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.197.08:09:48.13#ibcon#ireg 17 cls_cnt 0 2006.197.08:09:48.13#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.197.08:09:48.13#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.197.08:09:48.13#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.197.08:09:48.13#ibcon#enter wrdev, iclass 7, count 0 2006.197.08:09:48.13#ibcon#first serial, iclass 7, count 0 2006.197.08:09:48.13#ibcon#enter sib2, iclass 7, count 0 2006.197.08:09:48.13#ibcon#flushed, iclass 7, count 0 2006.197.08:09:48.13#ibcon#about to write, iclass 7, count 0 2006.197.08:09:48.13#ibcon#wrote, iclass 7, count 0 2006.197.08:09:48.13#ibcon#about to read 3, iclass 7, count 0 2006.197.08:09:48.15#ibcon#read 3, iclass 7, count 0 2006.197.08:09:48.15#ibcon#about to read 4, iclass 7, count 0 2006.197.08:09:48.15#ibcon#read 4, iclass 7, count 0 2006.197.08:09:48.15#ibcon#about to read 5, iclass 7, count 0 2006.197.08:09:48.15#ibcon#read 5, iclass 7, count 0 2006.197.08:09:48.15#ibcon#about to read 6, iclass 7, count 0 2006.197.08:09:48.15#ibcon#read 6, iclass 7, count 0 2006.197.08:09:48.15#ibcon#end of sib2, iclass 7, count 0 2006.197.08:09:48.15#ibcon#*mode == 0, iclass 7, count 0 2006.197.08:09:48.15#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.197.08:09:48.15#ibcon#[26=FRQ=02,572.99\r\n] 2006.197.08:09:48.15#ibcon#*before write, iclass 7, count 0 2006.197.08:09:48.15#ibcon#enter sib2, iclass 7, count 0 2006.197.08:09:48.15#ibcon#flushed, iclass 7, count 0 2006.197.08:09:48.15#ibcon#about to write, iclass 7, count 0 2006.197.08:09:48.15#ibcon#wrote, iclass 7, count 0 2006.197.08:09:48.15#ibcon#about to read 3, iclass 7, count 0 2006.197.08:09:48.19#ibcon#read 3, iclass 7, count 0 2006.197.08:09:48.19#ibcon#about to read 4, iclass 7, count 0 2006.197.08:09:48.19#ibcon#read 4, iclass 7, count 0 2006.197.08:09:48.19#ibcon#about to read 5, iclass 7, count 0 2006.197.08:09:48.19#ibcon#read 5, iclass 7, count 0 2006.197.08:09:48.19#ibcon#about to read 6, iclass 7, count 0 2006.197.08:09:48.19#ibcon#read 6, iclass 7, count 0 2006.197.08:09:48.19#ibcon#end of sib2, iclass 7, count 0 2006.197.08:09:48.19#ibcon#*after write, iclass 7, count 0 2006.197.08:09:48.19#ibcon#*before return 0, iclass 7, count 0 2006.197.08:09:48.19#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.197.08:09:48.19#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.197.08:09:48.19#ibcon#about to clear, iclass 7 cls_cnt 0 2006.197.08:09:48.19#ibcon#cleared, iclass 7 cls_cnt 0 2006.197.08:09:48.19$vc4f8/va=2,7 2006.197.08:09:48.19#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.197.08:09:48.19#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.197.08:09:48.19#ibcon#ireg 11 cls_cnt 2 2006.197.08:09:48.19#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.197.08:09:48.25#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.197.08:09:48.25#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.197.08:09:48.25#ibcon#enter wrdev, iclass 11, count 2 2006.197.08:09:48.25#ibcon#first serial, iclass 11, count 2 2006.197.08:09:48.25#ibcon#enter sib2, iclass 11, count 2 2006.197.08:09:48.25#ibcon#flushed, iclass 11, count 2 2006.197.08:09:48.25#ibcon#about to write, iclass 11, count 2 2006.197.08:09:48.25#ibcon#wrote, iclass 11, count 2 2006.197.08:09:48.25#ibcon#about to read 3, iclass 11, count 2 2006.197.08:09:48.27#ibcon#read 3, iclass 11, count 2 2006.197.08:09:48.27#ibcon#about to read 4, iclass 11, count 2 2006.197.08:09:48.27#ibcon#read 4, iclass 11, count 2 2006.197.08:09:48.27#ibcon#about to read 5, iclass 11, count 2 2006.197.08:09:48.27#ibcon#read 5, iclass 11, count 2 2006.197.08:09:48.27#ibcon#about to read 6, iclass 11, count 2 2006.197.08:09:48.27#ibcon#read 6, iclass 11, count 2 2006.197.08:09:48.27#ibcon#end of sib2, iclass 11, count 2 2006.197.08:09:48.27#ibcon#*mode == 0, iclass 11, count 2 2006.197.08:09:48.27#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.197.08:09:48.27#ibcon#[25=AT02-07\r\n] 2006.197.08:09:48.27#ibcon#*before write, iclass 11, count 2 2006.197.08:09:48.27#ibcon#enter sib2, iclass 11, count 2 2006.197.08:09:48.27#ibcon#flushed, iclass 11, count 2 2006.197.08:09:48.27#ibcon#about to write, iclass 11, count 2 2006.197.08:09:48.27#ibcon#wrote, iclass 11, count 2 2006.197.08:09:48.27#ibcon#about to read 3, iclass 11, count 2 2006.197.08:09:48.30#ibcon#read 3, iclass 11, count 2 2006.197.08:09:48.30#ibcon#about to read 4, iclass 11, count 2 2006.197.08:09:48.30#ibcon#read 4, iclass 11, count 2 2006.197.08:09:48.30#ibcon#about to read 5, iclass 11, count 2 2006.197.08:09:48.30#ibcon#read 5, iclass 11, count 2 2006.197.08:09:48.30#ibcon#about to read 6, iclass 11, count 2 2006.197.08:09:48.30#ibcon#read 6, iclass 11, count 2 2006.197.08:09:48.30#ibcon#end of sib2, iclass 11, count 2 2006.197.08:09:48.30#ibcon#*after write, iclass 11, count 2 2006.197.08:09:48.30#ibcon#*before return 0, iclass 11, count 2 2006.197.08:09:48.30#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.197.08:09:48.30#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.197.08:09:48.30#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.197.08:09:48.30#ibcon#ireg 7 cls_cnt 0 2006.197.08:09:48.30#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.197.08:09:48.42#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.197.08:09:48.42#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.197.08:09:48.42#ibcon#enter wrdev, iclass 11, count 0 2006.197.08:09:48.42#ibcon#first serial, iclass 11, count 0 2006.197.08:09:48.42#ibcon#enter sib2, iclass 11, count 0 2006.197.08:09:48.42#ibcon#flushed, iclass 11, count 0 2006.197.08:09:48.42#ibcon#about to write, iclass 11, count 0 2006.197.08:09:48.42#ibcon#wrote, iclass 11, count 0 2006.197.08:09:48.42#ibcon#about to read 3, iclass 11, count 0 2006.197.08:09:48.44#ibcon#read 3, iclass 11, count 0 2006.197.08:09:48.44#ibcon#about to read 4, iclass 11, count 0 2006.197.08:09:48.44#ibcon#read 4, iclass 11, count 0 2006.197.08:09:48.44#ibcon#about to read 5, iclass 11, count 0 2006.197.08:09:48.44#ibcon#read 5, iclass 11, count 0 2006.197.08:09:48.44#ibcon#about to read 6, iclass 11, count 0 2006.197.08:09:48.44#ibcon#read 6, iclass 11, count 0 2006.197.08:09:48.44#ibcon#end of sib2, iclass 11, count 0 2006.197.08:09:48.44#ibcon#*mode == 0, iclass 11, count 0 2006.197.08:09:48.44#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.197.08:09:48.44#ibcon#[25=USB\r\n] 2006.197.08:09:48.44#ibcon#*before write, iclass 11, count 0 2006.197.08:09:48.44#ibcon#enter sib2, iclass 11, count 0 2006.197.08:09:48.44#ibcon#flushed, iclass 11, count 0 2006.197.08:09:48.44#ibcon#about to write, iclass 11, count 0 2006.197.08:09:48.44#ibcon#wrote, iclass 11, count 0 2006.197.08:09:48.44#ibcon#about to read 3, iclass 11, count 0 2006.197.08:09:48.47#ibcon#read 3, iclass 11, count 0 2006.197.08:09:48.47#ibcon#about to read 4, iclass 11, count 0 2006.197.08:09:48.47#ibcon#read 4, iclass 11, count 0 2006.197.08:09:48.47#ibcon#about to read 5, iclass 11, count 0 2006.197.08:09:48.47#ibcon#read 5, iclass 11, count 0 2006.197.08:09:48.47#ibcon#about to read 6, iclass 11, count 0 2006.197.08:09:48.47#ibcon#read 6, iclass 11, count 0 2006.197.08:09:48.47#ibcon#end of sib2, iclass 11, count 0 2006.197.08:09:48.47#ibcon#*after write, iclass 11, count 0 2006.197.08:09:48.47#ibcon#*before return 0, iclass 11, count 0 2006.197.08:09:48.47#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.197.08:09:48.47#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.197.08:09:48.47#ibcon#about to clear, iclass 11 cls_cnt 0 2006.197.08:09:48.47#ibcon#cleared, iclass 11 cls_cnt 0 2006.197.08:09:48.47$vc4f8/valo=3,672.99 2006.197.08:09:48.47#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.197.08:09:48.47#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.197.08:09:48.47#ibcon#ireg 17 cls_cnt 0 2006.197.08:09:48.47#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.197.08:09:48.47#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.197.08:09:48.47#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.197.08:09:48.47#ibcon#enter wrdev, iclass 13, count 0 2006.197.08:09:48.47#ibcon#first serial, iclass 13, count 0 2006.197.08:09:48.47#ibcon#enter sib2, iclass 13, count 0 2006.197.08:09:48.47#ibcon#flushed, iclass 13, count 0 2006.197.08:09:48.47#ibcon#about to write, iclass 13, count 0 2006.197.08:09:48.47#ibcon#wrote, iclass 13, count 0 2006.197.08:09:48.47#ibcon#about to read 3, iclass 13, count 0 2006.197.08:09:48.49#ibcon#read 3, iclass 13, count 0 2006.197.08:09:48.49#ibcon#about to read 4, iclass 13, count 0 2006.197.08:09:48.49#ibcon#read 4, iclass 13, count 0 2006.197.08:09:48.49#ibcon#about to read 5, iclass 13, count 0 2006.197.08:09:48.49#ibcon#read 5, iclass 13, count 0 2006.197.08:09:48.49#ibcon#about to read 6, iclass 13, count 0 2006.197.08:09:48.49#ibcon#read 6, iclass 13, count 0 2006.197.08:09:48.49#ibcon#end of sib2, iclass 13, count 0 2006.197.08:09:48.49#ibcon#*mode == 0, iclass 13, count 0 2006.197.08:09:48.49#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.197.08:09:48.49#ibcon#[26=FRQ=03,672.99\r\n] 2006.197.08:09:48.49#ibcon#*before write, iclass 13, count 0 2006.197.08:09:48.49#ibcon#enter sib2, iclass 13, count 0 2006.197.08:09:48.49#ibcon#flushed, iclass 13, count 0 2006.197.08:09:48.49#ibcon#about to write, iclass 13, count 0 2006.197.08:09:48.49#ibcon#wrote, iclass 13, count 0 2006.197.08:09:48.49#ibcon#about to read 3, iclass 13, count 0 2006.197.08:09:48.53#ibcon#read 3, iclass 13, count 0 2006.197.08:09:48.53#ibcon#about to read 4, iclass 13, count 0 2006.197.08:09:48.53#ibcon#read 4, iclass 13, count 0 2006.197.08:09:48.53#ibcon#about to read 5, iclass 13, count 0 2006.197.08:09:48.53#ibcon#read 5, iclass 13, count 0 2006.197.08:09:48.53#ibcon#about to read 6, iclass 13, count 0 2006.197.08:09:48.53#ibcon#read 6, iclass 13, count 0 2006.197.08:09:48.53#ibcon#end of sib2, iclass 13, count 0 2006.197.08:09:48.53#ibcon#*after write, iclass 13, count 0 2006.197.08:09:48.53#ibcon#*before return 0, iclass 13, count 0 2006.197.08:09:48.53#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.197.08:09:48.53#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.197.08:09:48.53#ibcon#about to clear, iclass 13 cls_cnt 0 2006.197.08:09:48.53#ibcon#cleared, iclass 13 cls_cnt 0 2006.197.08:09:48.53$vc4f8/va=3,6 2006.197.08:09:48.53#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.197.08:09:48.53#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.197.08:09:48.53#ibcon#ireg 11 cls_cnt 2 2006.197.08:09:48.53#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.197.08:09:48.59#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.197.08:09:48.59#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.197.08:09:48.59#ibcon#enter wrdev, iclass 15, count 2 2006.197.08:09:48.59#ibcon#first serial, iclass 15, count 2 2006.197.08:09:48.59#ibcon#enter sib2, iclass 15, count 2 2006.197.08:09:48.59#ibcon#flushed, iclass 15, count 2 2006.197.08:09:48.59#ibcon#about to write, iclass 15, count 2 2006.197.08:09:48.59#ibcon#wrote, iclass 15, count 2 2006.197.08:09:48.59#ibcon#about to read 3, iclass 15, count 2 2006.197.08:09:48.61#ibcon#read 3, iclass 15, count 2 2006.197.08:09:48.61#ibcon#about to read 4, iclass 15, count 2 2006.197.08:09:48.61#ibcon#read 4, iclass 15, count 2 2006.197.08:09:48.61#ibcon#about to read 5, iclass 15, count 2 2006.197.08:09:48.61#ibcon#read 5, iclass 15, count 2 2006.197.08:09:48.61#ibcon#about to read 6, iclass 15, count 2 2006.197.08:09:48.61#ibcon#read 6, iclass 15, count 2 2006.197.08:09:48.61#ibcon#end of sib2, iclass 15, count 2 2006.197.08:09:48.61#ibcon#*mode == 0, iclass 15, count 2 2006.197.08:09:48.61#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.197.08:09:48.61#ibcon#[25=AT03-06\r\n] 2006.197.08:09:48.61#ibcon#*before write, iclass 15, count 2 2006.197.08:09:48.61#ibcon#enter sib2, iclass 15, count 2 2006.197.08:09:48.61#ibcon#flushed, iclass 15, count 2 2006.197.08:09:48.61#ibcon#about to write, iclass 15, count 2 2006.197.08:09:48.61#ibcon#wrote, iclass 15, count 2 2006.197.08:09:48.61#ibcon#about to read 3, iclass 15, count 2 2006.197.08:09:48.64#ibcon#read 3, iclass 15, count 2 2006.197.08:09:48.64#ibcon#about to read 4, iclass 15, count 2 2006.197.08:09:48.64#ibcon#read 4, iclass 15, count 2 2006.197.08:09:48.64#ibcon#about to read 5, iclass 15, count 2 2006.197.08:09:48.64#ibcon#read 5, iclass 15, count 2 2006.197.08:09:48.64#ibcon#about to read 6, iclass 15, count 2 2006.197.08:09:48.64#ibcon#read 6, iclass 15, count 2 2006.197.08:09:48.64#ibcon#end of sib2, iclass 15, count 2 2006.197.08:09:48.64#ibcon#*after write, iclass 15, count 2 2006.197.08:09:48.64#ibcon#*before return 0, iclass 15, count 2 2006.197.08:09:48.64#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.197.08:09:48.64#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.197.08:09:48.64#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.197.08:09:48.64#ibcon#ireg 7 cls_cnt 0 2006.197.08:09:48.64#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.197.08:09:48.76#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.197.08:09:48.76#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.197.08:09:48.76#ibcon#enter wrdev, iclass 15, count 0 2006.197.08:09:48.76#ibcon#first serial, iclass 15, count 0 2006.197.08:09:48.76#ibcon#enter sib2, iclass 15, count 0 2006.197.08:09:48.76#ibcon#flushed, iclass 15, count 0 2006.197.08:09:48.76#ibcon#about to write, iclass 15, count 0 2006.197.08:09:48.76#ibcon#wrote, iclass 15, count 0 2006.197.08:09:48.76#ibcon#about to read 3, iclass 15, count 0 2006.197.08:09:48.78#ibcon#read 3, iclass 15, count 0 2006.197.08:09:48.78#ibcon#about to read 4, iclass 15, count 0 2006.197.08:09:48.78#ibcon#read 4, iclass 15, count 0 2006.197.08:09:48.78#ibcon#about to read 5, iclass 15, count 0 2006.197.08:09:48.78#ibcon#read 5, iclass 15, count 0 2006.197.08:09:48.78#ibcon#about to read 6, iclass 15, count 0 2006.197.08:09:48.78#ibcon#read 6, iclass 15, count 0 2006.197.08:09:48.78#ibcon#end of sib2, iclass 15, count 0 2006.197.08:09:48.78#ibcon#*mode == 0, iclass 15, count 0 2006.197.08:09:48.78#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.197.08:09:48.78#ibcon#[25=USB\r\n] 2006.197.08:09:48.78#ibcon#*before write, iclass 15, count 0 2006.197.08:09:48.78#ibcon#enter sib2, iclass 15, count 0 2006.197.08:09:48.78#ibcon#flushed, iclass 15, count 0 2006.197.08:09:48.78#ibcon#about to write, iclass 15, count 0 2006.197.08:09:48.78#ibcon#wrote, iclass 15, count 0 2006.197.08:09:48.78#ibcon#about to read 3, iclass 15, count 0 2006.197.08:09:48.81#ibcon#read 3, iclass 15, count 0 2006.197.08:09:48.81#ibcon#about to read 4, iclass 15, count 0 2006.197.08:09:48.81#ibcon#read 4, iclass 15, count 0 2006.197.08:09:48.81#ibcon#about to read 5, iclass 15, count 0 2006.197.08:09:48.81#ibcon#read 5, iclass 15, count 0 2006.197.08:09:48.81#ibcon#about to read 6, iclass 15, count 0 2006.197.08:09:48.81#ibcon#read 6, iclass 15, count 0 2006.197.08:09:48.81#ibcon#end of sib2, iclass 15, count 0 2006.197.08:09:48.81#ibcon#*after write, iclass 15, count 0 2006.197.08:09:48.81#ibcon#*before return 0, iclass 15, count 0 2006.197.08:09:48.81#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.197.08:09:48.81#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.197.08:09:48.81#ibcon#about to clear, iclass 15 cls_cnt 0 2006.197.08:09:48.81#ibcon#cleared, iclass 15 cls_cnt 0 2006.197.08:09:48.81$vc4f8/valo=4,832.99 2006.197.08:09:48.81#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.197.08:09:48.81#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.197.08:09:48.81#ibcon#ireg 17 cls_cnt 0 2006.197.08:09:48.81#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.197.08:09:48.81#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.197.08:09:48.81#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.197.08:09:48.81#ibcon#enter wrdev, iclass 17, count 0 2006.197.08:09:48.81#ibcon#first serial, iclass 17, count 0 2006.197.08:09:48.81#ibcon#enter sib2, iclass 17, count 0 2006.197.08:09:48.81#ibcon#flushed, iclass 17, count 0 2006.197.08:09:48.81#ibcon#about to write, iclass 17, count 0 2006.197.08:09:48.81#ibcon#wrote, iclass 17, count 0 2006.197.08:09:48.81#ibcon#about to read 3, iclass 17, count 0 2006.197.08:09:48.83#ibcon#read 3, iclass 17, count 0 2006.197.08:09:48.83#ibcon#about to read 4, iclass 17, count 0 2006.197.08:09:48.83#ibcon#read 4, iclass 17, count 0 2006.197.08:09:48.83#ibcon#about to read 5, iclass 17, count 0 2006.197.08:09:48.83#ibcon#read 5, iclass 17, count 0 2006.197.08:09:48.83#ibcon#about to read 6, iclass 17, count 0 2006.197.08:09:48.83#ibcon#read 6, iclass 17, count 0 2006.197.08:09:48.83#ibcon#end of sib2, iclass 17, count 0 2006.197.08:09:48.83#ibcon#*mode == 0, iclass 17, count 0 2006.197.08:09:48.83#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.197.08:09:48.83#ibcon#[26=FRQ=04,832.99\r\n] 2006.197.08:09:48.83#ibcon#*before write, iclass 17, count 0 2006.197.08:09:48.83#ibcon#enter sib2, iclass 17, count 0 2006.197.08:09:48.83#ibcon#flushed, iclass 17, count 0 2006.197.08:09:48.83#ibcon#about to write, iclass 17, count 0 2006.197.08:09:48.83#ibcon#wrote, iclass 17, count 0 2006.197.08:09:48.83#ibcon#about to read 3, iclass 17, count 0 2006.197.08:09:48.87#ibcon#read 3, iclass 17, count 0 2006.197.08:09:48.87#ibcon#about to read 4, iclass 17, count 0 2006.197.08:09:48.87#ibcon#read 4, iclass 17, count 0 2006.197.08:09:48.87#ibcon#about to read 5, iclass 17, count 0 2006.197.08:09:48.87#ibcon#read 5, iclass 17, count 0 2006.197.08:09:48.87#ibcon#about to read 6, iclass 17, count 0 2006.197.08:09:48.87#ibcon#read 6, iclass 17, count 0 2006.197.08:09:48.87#ibcon#end of sib2, iclass 17, count 0 2006.197.08:09:48.87#ibcon#*after write, iclass 17, count 0 2006.197.08:09:48.87#ibcon#*before return 0, iclass 17, count 0 2006.197.08:09:48.87#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.197.08:09:48.87#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.197.08:09:48.87#ibcon#about to clear, iclass 17 cls_cnt 0 2006.197.08:09:48.87#ibcon#cleared, iclass 17 cls_cnt 0 2006.197.08:09:48.87$vc4f8/va=4,7 2006.197.08:09:48.87#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.197.08:09:48.87#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.197.08:09:48.87#ibcon#ireg 11 cls_cnt 2 2006.197.08:09:48.87#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.197.08:09:48.93#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.197.08:09:48.93#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.197.08:09:48.93#ibcon#enter wrdev, iclass 19, count 2 2006.197.08:09:48.93#ibcon#first serial, iclass 19, count 2 2006.197.08:09:48.93#ibcon#enter sib2, iclass 19, count 2 2006.197.08:09:48.93#ibcon#flushed, iclass 19, count 2 2006.197.08:09:48.93#ibcon#about to write, iclass 19, count 2 2006.197.08:09:48.93#ibcon#wrote, iclass 19, count 2 2006.197.08:09:48.93#ibcon#about to read 3, iclass 19, count 2 2006.197.08:09:48.95#ibcon#read 3, iclass 19, count 2 2006.197.08:09:48.95#ibcon#about to read 4, iclass 19, count 2 2006.197.08:09:48.95#ibcon#read 4, iclass 19, count 2 2006.197.08:09:48.95#ibcon#about to read 5, iclass 19, count 2 2006.197.08:09:48.95#ibcon#read 5, iclass 19, count 2 2006.197.08:09:48.95#ibcon#about to read 6, iclass 19, count 2 2006.197.08:09:48.95#ibcon#read 6, iclass 19, count 2 2006.197.08:09:48.95#ibcon#end of sib2, iclass 19, count 2 2006.197.08:09:48.95#ibcon#*mode == 0, iclass 19, count 2 2006.197.08:09:48.95#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.197.08:09:48.95#ibcon#[25=AT04-07\r\n] 2006.197.08:09:48.95#ibcon#*before write, iclass 19, count 2 2006.197.08:09:48.95#ibcon#enter sib2, iclass 19, count 2 2006.197.08:09:48.95#ibcon#flushed, iclass 19, count 2 2006.197.08:09:48.95#ibcon#about to write, iclass 19, count 2 2006.197.08:09:48.95#ibcon#wrote, iclass 19, count 2 2006.197.08:09:48.95#ibcon#about to read 3, iclass 19, count 2 2006.197.08:09:48.98#ibcon#read 3, iclass 19, count 2 2006.197.08:09:48.98#ibcon#about to read 4, iclass 19, count 2 2006.197.08:09:48.98#ibcon#read 4, iclass 19, count 2 2006.197.08:09:48.98#ibcon#about to read 5, iclass 19, count 2 2006.197.08:09:48.98#ibcon#read 5, iclass 19, count 2 2006.197.08:09:48.98#ibcon#about to read 6, iclass 19, count 2 2006.197.08:09:48.98#ibcon#read 6, iclass 19, count 2 2006.197.08:09:48.98#ibcon#end of sib2, iclass 19, count 2 2006.197.08:09:48.98#ibcon#*after write, iclass 19, count 2 2006.197.08:09:48.98#ibcon#*before return 0, iclass 19, count 2 2006.197.08:09:48.98#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.197.08:09:48.98#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.197.08:09:48.98#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.197.08:09:48.98#ibcon#ireg 7 cls_cnt 0 2006.197.08:09:48.98#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.197.08:09:49.10#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.197.08:09:49.10#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.197.08:09:49.10#ibcon#enter wrdev, iclass 19, count 0 2006.197.08:09:49.10#ibcon#first serial, iclass 19, count 0 2006.197.08:09:49.10#ibcon#enter sib2, iclass 19, count 0 2006.197.08:09:49.10#ibcon#flushed, iclass 19, count 0 2006.197.08:09:49.10#ibcon#about to write, iclass 19, count 0 2006.197.08:09:49.10#ibcon#wrote, iclass 19, count 0 2006.197.08:09:49.10#ibcon#about to read 3, iclass 19, count 0 2006.197.08:09:49.12#ibcon#read 3, iclass 19, count 0 2006.197.08:09:49.12#ibcon#about to read 4, iclass 19, count 0 2006.197.08:09:49.12#ibcon#read 4, iclass 19, count 0 2006.197.08:09:49.12#ibcon#about to read 5, iclass 19, count 0 2006.197.08:09:49.12#ibcon#read 5, iclass 19, count 0 2006.197.08:09:49.12#ibcon#about to read 6, iclass 19, count 0 2006.197.08:09:49.12#ibcon#read 6, iclass 19, count 0 2006.197.08:09:49.12#ibcon#end of sib2, iclass 19, count 0 2006.197.08:09:49.12#ibcon#*mode == 0, iclass 19, count 0 2006.197.08:09:49.12#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.197.08:09:49.12#ibcon#[25=USB\r\n] 2006.197.08:09:49.12#ibcon#*before write, iclass 19, count 0 2006.197.08:09:49.12#ibcon#enter sib2, iclass 19, count 0 2006.197.08:09:49.12#ibcon#flushed, iclass 19, count 0 2006.197.08:09:49.12#ibcon#about to write, iclass 19, count 0 2006.197.08:09:49.12#ibcon#wrote, iclass 19, count 0 2006.197.08:09:49.12#ibcon#about to read 3, iclass 19, count 0 2006.197.08:09:49.15#ibcon#read 3, iclass 19, count 0 2006.197.08:09:49.15#ibcon#about to read 4, iclass 19, count 0 2006.197.08:09:49.15#ibcon#read 4, iclass 19, count 0 2006.197.08:09:49.15#ibcon#about to read 5, iclass 19, count 0 2006.197.08:09:49.15#ibcon#read 5, iclass 19, count 0 2006.197.08:09:49.15#ibcon#about to read 6, iclass 19, count 0 2006.197.08:09:49.15#ibcon#read 6, iclass 19, count 0 2006.197.08:09:49.15#ibcon#end of sib2, iclass 19, count 0 2006.197.08:09:49.15#ibcon#*after write, iclass 19, count 0 2006.197.08:09:49.15#ibcon#*before return 0, iclass 19, count 0 2006.197.08:09:49.15#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.197.08:09:49.15#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.197.08:09:49.15#ibcon#about to clear, iclass 19 cls_cnt 0 2006.197.08:09:49.15#ibcon#cleared, iclass 19 cls_cnt 0 2006.197.08:09:49.15$vc4f8/valo=5,652.99 2006.197.08:09:49.15#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.197.08:09:49.15#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.197.08:09:49.15#ibcon#ireg 17 cls_cnt 0 2006.197.08:09:49.15#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.197.08:09:49.15#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.197.08:09:49.15#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.197.08:09:49.15#ibcon#enter wrdev, iclass 21, count 0 2006.197.08:09:49.15#ibcon#first serial, iclass 21, count 0 2006.197.08:09:49.15#ibcon#enter sib2, iclass 21, count 0 2006.197.08:09:49.15#ibcon#flushed, iclass 21, count 0 2006.197.08:09:49.15#ibcon#about to write, iclass 21, count 0 2006.197.08:09:49.15#ibcon#wrote, iclass 21, count 0 2006.197.08:09:49.15#ibcon#about to read 3, iclass 21, count 0 2006.197.08:09:49.17#ibcon#read 3, iclass 21, count 0 2006.197.08:09:49.17#ibcon#about to read 4, iclass 21, count 0 2006.197.08:09:49.17#ibcon#read 4, iclass 21, count 0 2006.197.08:09:49.17#ibcon#about to read 5, iclass 21, count 0 2006.197.08:09:49.17#ibcon#read 5, iclass 21, count 0 2006.197.08:09:49.17#ibcon#about to read 6, iclass 21, count 0 2006.197.08:09:49.17#ibcon#read 6, iclass 21, count 0 2006.197.08:09:49.17#ibcon#end of sib2, iclass 21, count 0 2006.197.08:09:49.17#ibcon#*mode == 0, iclass 21, count 0 2006.197.08:09:49.17#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.197.08:09:49.17#ibcon#[26=FRQ=05,652.99\r\n] 2006.197.08:09:49.17#ibcon#*before write, iclass 21, count 0 2006.197.08:09:49.17#ibcon#enter sib2, iclass 21, count 0 2006.197.08:09:49.17#ibcon#flushed, iclass 21, count 0 2006.197.08:09:49.17#ibcon#about to write, iclass 21, count 0 2006.197.08:09:49.17#ibcon#wrote, iclass 21, count 0 2006.197.08:09:49.17#ibcon#about to read 3, iclass 21, count 0 2006.197.08:09:49.21#ibcon#read 3, iclass 21, count 0 2006.197.08:09:49.21#ibcon#about to read 4, iclass 21, count 0 2006.197.08:09:49.21#ibcon#read 4, iclass 21, count 0 2006.197.08:09:49.21#ibcon#about to read 5, iclass 21, count 0 2006.197.08:09:49.21#ibcon#read 5, iclass 21, count 0 2006.197.08:09:49.21#ibcon#about to read 6, iclass 21, count 0 2006.197.08:09:49.21#ibcon#read 6, iclass 21, count 0 2006.197.08:09:49.21#ibcon#end of sib2, iclass 21, count 0 2006.197.08:09:49.21#ibcon#*after write, iclass 21, count 0 2006.197.08:09:49.21#ibcon#*before return 0, iclass 21, count 0 2006.197.08:09:49.21#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.197.08:09:49.21#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.197.08:09:49.21#ibcon#about to clear, iclass 21 cls_cnt 0 2006.197.08:09:49.21#ibcon#cleared, iclass 21 cls_cnt 0 2006.197.08:09:49.21$vc4f8/va=5,7 2006.197.08:09:49.21#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.197.08:09:49.21#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.197.08:09:49.21#ibcon#ireg 11 cls_cnt 2 2006.197.08:09:49.21#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.197.08:09:49.27#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.197.08:09:49.27#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.197.08:09:49.27#ibcon#enter wrdev, iclass 23, count 2 2006.197.08:09:49.27#ibcon#first serial, iclass 23, count 2 2006.197.08:09:49.27#ibcon#enter sib2, iclass 23, count 2 2006.197.08:09:49.27#ibcon#flushed, iclass 23, count 2 2006.197.08:09:49.27#ibcon#about to write, iclass 23, count 2 2006.197.08:09:49.27#ibcon#wrote, iclass 23, count 2 2006.197.08:09:49.27#ibcon#about to read 3, iclass 23, count 2 2006.197.08:09:49.29#ibcon#read 3, iclass 23, count 2 2006.197.08:09:49.29#ibcon#about to read 4, iclass 23, count 2 2006.197.08:09:49.29#ibcon#read 4, iclass 23, count 2 2006.197.08:09:49.29#ibcon#about to read 5, iclass 23, count 2 2006.197.08:09:49.29#ibcon#read 5, iclass 23, count 2 2006.197.08:09:49.29#ibcon#about to read 6, iclass 23, count 2 2006.197.08:09:49.29#ibcon#read 6, iclass 23, count 2 2006.197.08:09:49.29#ibcon#end of sib2, iclass 23, count 2 2006.197.08:09:49.29#ibcon#*mode == 0, iclass 23, count 2 2006.197.08:09:49.29#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.197.08:09:49.29#ibcon#[25=AT05-07\r\n] 2006.197.08:09:49.29#ibcon#*before write, iclass 23, count 2 2006.197.08:09:49.29#ibcon#enter sib2, iclass 23, count 2 2006.197.08:09:49.29#ibcon#flushed, iclass 23, count 2 2006.197.08:09:49.29#ibcon#about to write, iclass 23, count 2 2006.197.08:09:49.29#ibcon#wrote, iclass 23, count 2 2006.197.08:09:49.29#ibcon#about to read 3, iclass 23, count 2 2006.197.08:09:49.32#ibcon#read 3, iclass 23, count 2 2006.197.08:09:49.32#ibcon#about to read 4, iclass 23, count 2 2006.197.08:09:49.32#ibcon#read 4, iclass 23, count 2 2006.197.08:09:49.32#ibcon#about to read 5, iclass 23, count 2 2006.197.08:09:49.32#ibcon#read 5, iclass 23, count 2 2006.197.08:09:49.32#ibcon#about to read 6, iclass 23, count 2 2006.197.08:09:49.32#ibcon#read 6, iclass 23, count 2 2006.197.08:09:49.32#ibcon#end of sib2, iclass 23, count 2 2006.197.08:09:49.32#ibcon#*after write, iclass 23, count 2 2006.197.08:09:49.32#ibcon#*before return 0, iclass 23, count 2 2006.197.08:09:49.32#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.197.08:09:49.32#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.197.08:09:49.32#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.197.08:09:49.32#ibcon#ireg 7 cls_cnt 0 2006.197.08:09:49.32#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.197.08:09:49.44#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.197.08:09:49.44#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.197.08:09:49.44#ibcon#enter wrdev, iclass 23, count 0 2006.197.08:09:49.44#ibcon#first serial, iclass 23, count 0 2006.197.08:09:49.44#ibcon#enter sib2, iclass 23, count 0 2006.197.08:09:49.44#ibcon#flushed, iclass 23, count 0 2006.197.08:09:49.44#ibcon#about to write, iclass 23, count 0 2006.197.08:09:49.44#ibcon#wrote, iclass 23, count 0 2006.197.08:09:49.44#ibcon#about to read 3, iclass 23, count 0 2006.197.08:09:49.46#ibcon#read 3, iclass 23, count 0 2006.197.08:09:49.46#ibcon#about to read 4, iclass 23, count 0 2006.197.08:09:49.46#ibcon#read 4, iclass 23, count 0 2006.197.08:09:49.46#ibcon#about to read 5, iclass 23, count 0 2006.197.08:09:49.46#ibcon#read 5, iclass 23, count 0 2006.197.08:09:49.46#ibcon#about to read 6, iclass 23, count 0 2006.197.08:09:49.46#ibcon#read 6, iclass 23, count 0 2006.197.08:09:49.46#ibcon#end of sib2, iclass 23, count 0 2006.197.08:09:49.46#ibcon#*mode == 0, iclass 23, count 0 2006.197.08:09:49.46#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.197.08:09:49.46#ibcon#[25=USB\r\n] 2006.197.08:09:49.46#ibcon#*before write, iclass 23, count 0 2006.197.08:09:49.46#ibcon#enter sib2, iclass 23, count 0 2006.197.08:09:49.46#ibcon#flushed, iclass 23, count 0 2006.197.08:09:49.46#ibcon#about to write, iclass 23, count 0 2006.197.08:09:49.46#ibcon#wrote, iclass 23, count 0 2006.197.08:09:49.46#ibcon#about to read 3, iclass 23, count 0 2006.197.08:09:49.49#ibcon#read 3, iclass 23, count 0 2006.197.08:09:49.49#ibcon#about to read 4, iclass 23, count 0 2006.197.08:09:49.49#ibcon#read 4, iclass 23, count 0 2006.197.08:09:49.49#ibcon#about to read 5, iclass 23, count 0 2006.197.08:09:49.49#ibcon#read 5, iclass 23, count 0 2006.197.08:09:49.49#ibcon#about to read 6, iclass 23, count 0 2006.197.08:09:49.49#ibcon#read 6, iclass 23, count 0 2006.197.08:09:49.49#ibcon#end of sib2, iclass 23, count 0 2006.197.08:09:49.49#ibcon#*after write, iclass 23, count 0 2006.197.08:09:49.49#ibcon#*before return 0, iclass 23, count 0 2006.197.08:09:49.49#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.197.08:09:49.49#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.197.08:09:49.49#ibcon#about to clear, iclass 23 cls_cnt 0 2006.197.08:09:49.49#ibcon#cleared, iclass 23 cls_cnt 0 2006.197.08:09:49.49$vc4f8/valo=6,772.99 2006.197.08:09:49.49#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.197.08:09:49.49#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.197.08:09:49.49#ibcon#ireg 17 cls_cnt 0 2006.197.08:09:49.49#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.197.08:09:49.49#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.197.08:09:49.49#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.197.08:09:49.49#ibcon#enter wrdev, iclass 25, count 0 2006.197.08:09:49.49#ibcon#first serial, iclass 25, count 0 2006.197.08:09:49.49#ibcon#enter sib2, iclass 25, count 0 2006.197.08:09:49.49#ibcon#flushed, iclass 25, count 0 2006.197.08:09:49.49#ibcon#about to write, iclass 25, count 0 2006.197.08:09:49.49#ibcon#wrote, iclass 25, count 0 2006.197.08:09:49.49#ibcon#about to read 3, iclass 25, count 0 2006.197.08:09:49.51#ibcon#read 3, iclass 25, count 0 2006.197.08:09:49.51#ibcon#about to read 4, iclass 25, count 0 2006.197.08:09:49.51#ibcon#read 4, iclass 25, count 0 2006.197.08:09:49.51#ibcon#about to read 5, iclass 25, count 0 2006.197.08:09:49.51#ibcon#read 5, iclass 25, count 0 2006.197.08:09:49.51#ibcon#about to read 6, iclass 25, count 0 2006.197.08:09:49.51#ibcon#read 6, iclass 25, count 0 2006.197.08:09:49.51#ibcon#end of sib2, iclass 25, count 0 2006.197.08:09:49.51#ibcon#*mode == 0, iclass 25, count 0 2006.197.08:09:49.51#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.197.08:09:49.51#ibcon#[26=FRQ=06,772.99\r\n] 2006.197.08:09:49.51#ibcon#*before write, iclass 25, count 0 2006.197.08:09:49.51#ibcon#enter sib2, iclass 25, count 0 2006.197.08:09:49.51#ibcon#flushed, iclass 25, count 0 2006.197.08:09:49.51#ibcon#about to write, iclass 25, count 0 2006.197.08:09:49.51#ibcon#wrote, iclass 25, count 0 2006.197.08:09:49.51#ibcon#about to read 3, iclass 25, count 0 2006.197.08:09:49.55#ibcon#read 3, iclass 25, count 0 2006.197.08:09:49.55#ibcon#about to read 4, iclass 25, count 0 2006.197.08:09:49.55#ibcon#read 4, iclass 25, count 0 2006.197.08:09:49.55#ibcon#about to read 5, iclass 25, count 0 2006.197.08:09:49.55#ibcon#read 5, iclass 25, count 0 2006.197.08:09:49.55#ibcon#about to read 6, iclass 25, count 0 2006.197.08:09:49.55#ibcon#read 6, iclass 25, count 0 2006.197.08:09:49.55#ibcon#end of sib2, iclass 25, count 0 2006.197.08:09:49.55#ibcon#*after write, iclass 25, count 0 2006.197.08:09:49.55#ibcon#*before return 0, iclass 25, count 0 2006.197.08:09:49.55#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.197.08:09:49.55#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.197.08:09:49.55#ibcon#about to clear, iclass 25 cls_cnt 0 2006.197.08:09:49.55#ibcon#cleared, iclass 25 cls_cnt 0 2006.197.08:09:49.55$vc4f8/va=6,6 2006.197.08:09:49.55#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.197.08:09:49.55#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.197.08:09:49.55#ibcon#ireg 11 cls_cnt 2 2006.197.08:09:49.55#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.197.08:09:49.61#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.197.08:09:49.61#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.197.08:09:49.61#ibcon#enter wrdev, iclass 27, count 2 2006.197.08:09:49.61#ibcon#first serial, iclass 27, count 2 2006.197.08:09:49.61#ibcon#enter sib2, iclass 27, count 2 2006.197.08:09:49.61#ibcon#flushed, iclass 27, count 2 2006.197.08:09:49.61#ibcon#about to write, iclass 27, count 2 2006.197.08:09:49.61#ibcon#wrote, iclass 27, count 2 2006.197.08:09:49.61#ibcon#about to read 3, iclass 27, count 2 2006.197.08:09:49.63#ibcon#read 3, iclass 27, count 2 2006.197.08:09:49.63#ibcon#about to read 4, iclass 27, count 2 2006.197.08:09:49.63#ibcon#read 4, iclass 27, count 2 2006.197.08:09:49.63#ibcon#about to read 5, iclass 27, count 2 2006.197.08:09:49.63#ibcon#read 5, iclass 27, count 2 2006.197.08:09:49.63#ibcon#about to read 6, iclass 27, count 2 2006.197.08:09:49.63#ibcon#read 6, iclass 27, count 2 2006.197.08:09:49.63#ibcon#end of sib2, iclass 27, count 2 2006.197.08:09:49.63#ibcon#*mode == 0, iclass 27, count 2 2006.197.08:09:49.63#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.197.08:09:49.63#ibcon#[25=AT06-06\r\n] 2006.197.08:09:49.63#ibcon#*before write, iclass 27, count 2 2006.197.08:09:49.63#ibcon#enter sib2, iclass 27, count 2 2006.197.08:09:49.63#ibcon#flushed, iclass 27, count 2 2006.197.08:09:49.63#ibcon#about to write, iclass 27, count 2 2006.197.08:09:49.63#ibcon#wrote, iclass 27, count 2 2006.197.08:09:49.63#ibcon#about to read 3, iclass 27, count 2 2006.197.08:09:49.66#ibcon#read 3, iclass 27, count 2 2006.197.08:09:49.66#ibcon#about to read 4, iclass 27, count 2 2006.197.08:09:49.66#ibcon#read 4, iclass 27, count 2 2006.197.08:09:49.66#ibcon#about to read 5, iclass 27, count 2 2006.197.08:09:49.66#ibcon#read 5, iclass 27, count 2 2006.197.08:09:49.66#ibcon#about to read 6, iclass 27, count 2 2006.197.08:09:49.66#ibcon#read 6, iclass 27, count 2 2006.197.08:09:49.66#ibcon#end of sib2, iclass 27, count 2 2006.197.08:09:49.66#ibcon#*after write, iclass 27, count 2 2006.197.08:09:49.66#ibcon#*before return 0, iclass 27, count 2 2006.197.08:09:49.66#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.197.08:09:49.66#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.197.08:09:49.66#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.197.08:09:49.66#ibcon#ireg 7 cls_cnt 0 2006.197.08:09:49.66#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.197.08:09:49.78#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.197.08:09:49.78#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.197.08:09:49.78#ibcon#enter wrdev, iclass 27, count 0 2006.197.08:09:49.78#ibcon#first serial, iclass 27, count 0 2006.197.08:09:49.78#ibcon#enter sib2, iclass 27, count 0 2006.197.08:09:49.78#ibcon#flushed, iclass 27, count 0 2006.197.08:09:49.78#ibcon#about to write, iclass 27, count 0 2006.197.08:09:49.78#ibcon#wrote, iclass 27, count 0 2006.197.08:09:49.78#ibcon#about to read 3, iclass 27, count 0 2006.197.08:09:49.80#ibcon#read 3, iclass 27, count 0 2006.197.08:09:49.80#ibcon#about to read 4, iclass 27, count 0 2006.197.08:09:49.80#ibcon#read 4, iclass 27, count 0 2006.197.08:09:49.80#ibcon#about to read 5, iclass 27, count 0 2006.197.08:09:49.80#ibcon#read 5, iclass 27, count 0 2006.197.08:09:49.80#ibcon#about to read 6, iclass 27, count 0 2006.197.08:09:49.80#ibcon#read 6, iclass 27, count 0 2006.197.08:09:49.80#ibcon#end of sib2, iclass 27, count 0 2006.197.08:09:49.80#ibcon#*mode == 0, iclass 27, count 0 2006.197.08:09:49.80#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.197.08:09:49.80#ibcon#[25=USB\r\n] 2006.197.08:09:49.80#ibcon#*before write, iclass 27, count 0 2006.197.08:09:49.80#ibcon#enter sib2, iclass 27, count 0 2006.197.08:09:49.80#ibcon#flushed, iclass 27, count 0 2006.197.08:09:49.80#ibcon#about to write, iclass 27, count 0 2006.197.08:09:49.80#ibcon#wrote, iclass 27, count 0 2006.197.08:09:49.80#ibcon#about to read 3, iclass 27, count 0 2006.197.08:09:49.83#ibcon#read 3, iclass 27, count 0 2006.197.08:09:49.83#ibcon#about to read 4, iclass 27, count 0 2006.197.08:09:49.83#ibcon#read 4, iclass 27, count 0 2006.197.08:09:49.83#ibcon#about to read 5, iclass 27, count 0 2006.197.08:09:49.83#ibcon#read 5, iclass 27, count 0 2006.197.08:09:49.83#ibcon#about to read 6, iclass 27, count 0 2006.197.08:09:49.83#ibcon#read 6, iclass 27, count 0 2006.197.08:09:49.83#ibcon#end of sib2, iclass 27, count 0 2006.197.08:09:49.83#ibcon#*after write, iclass 27, count 0 2006.197.08:09:49.83#ibcon#*before return 0, iclass 27, count 0 2006.197.08:09:49.83#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.197.08:09:49.83#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.197.08:09:49.83#ibcon#about to clear, iclass 27 cls_cnt 0 2006.197.08:09:49.83#ibcon#cleared, iclass 27 cls_cnt 0 2006.197.08:09:49.83$vc4f8/valo=7,832.99 2006.197.08:09:49.83#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.197.08:09:49.83#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.197.08:09:49.83#ibcon#ireg 17 cls_cnt 0 2006.197.08:09:49.83#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.197.08:09:49.83#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.197.08:09:49.83#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.197.08:09:49.83#ibcon#enter wrdev, iclass 29, count 0 2006.197.08:09:49.83#ibcon#first serial, iclass 29, count 0 2006.197.08:09:49.83#ibcon#enter sib2, iclass 29, count 0 2006.197.08:09:49.83#ibcon#flushed, iclass 29, count 0 2006.197.08:09:49.83#ibcon#about to write, iclass 29, count 0 2006.197.08:09:49.83#ibcon#wrote, iclass 29, count 0 2006.197.08:09:49.83#ibcon#about to read 3, iclass 29, count 0 2006.197.08:09:49.85#ibcon#read 3, iclass 29, count 0 2006.197.08:09:49.85#ibcon#about to read 4, iclass 29, count 0 2006.197.08:09:49.85#ibcon#read 4, iclass 29, count 0 2006.197.08:09:49.85#ibcon#about to read 5, iclass 29, count 0 2006.197.08:09:49.85#ibcon#read 5, iclass 29, count 0 2006.197.08:09:49.85#ibcon#about to read 6, iclass 29, count 0 2006.197.08:09:49.85#ibcon#read 6, iclass 29, count 0 2006.197.08:09:49.85#ibcon#end of sib2, iclass 29, count 0 2006.197.08:09:49.85#ibcon#*mode == 0, iclass 29, count 0 2006.197.08:09:49.85#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.197.08:09:49.85#ibcon#[26=FRQ=07,832.99\r\n] 2006.197.08:09:49.85#ibcon#*before write, iclass 29, count 0 2006.197.08:09:49.85#ibcon#enter sib2, iclass 29, count 0 2006.197.08:09:49.85#ibcon#flushed, iclass 29, count 0 2006.197.08:09:49.85#ibcon#about to write, iclass 29, count 0 2006.197.08:09:49.85#ibcon#wrote, iclass 29, count 0 2006.197.08:09:49.85#ibcon#about to read 3, iclass 29, count 0 2006.197.08:09:49.89#ibcon#read 3, iclass 29, count 0 2006.197.08:09:49.89#ibcon#about to read 4, iclass 29, count 0 2006.197.08:09:49.89#ibcon#read 4, iclass 29, count 0 2006.197.08:09:49.89#ibcon#about to read 5, iclass 29, count 0 2006.197.08:09:49.89#ibcon#read 5, iclass 29, count 0 2006.197.08:09:49.89#ibcon#about to read 6, iclass 29, count 0 2006.197.08:09:49.89#ibcon#read 6, iclass 29, count 0 2006.197.08:09:49.89#ibcon#end of sib2, iclass 29, count 0 2006.197.08:09:49.89#ibcon#*after write, iclass 29, count 0 2006.197.08:09:49.89#ibcon#*before return 0, iclass 29, count 0 2006.197.08:09:49.89#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.197.08:09:49.89#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.197.08:09:49.89#ibcon#about to clear, iclass 29 cls_cnt 0 2006.197.08:09:49.89#ibcon#cleared, iclass 29 cls_cnt 0 2006.197.08:09:49.89$vc4f8/va=7,6 2006.197.08:09:49.89#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.197.08:09:49.89#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.197.08:09:49.89#ibcon#ireg 11 cls_cnt 2 2006.197.08:09:49.89#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.197.08:09:49.95#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.197.08:09:49.95#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.197.08:09:49.95#ibcon#enter wrdev, iclass 31, count 2 2006.197.08:09:49.95#ibcon#first serial, iclass 31, count 2 2006.197.08:09:49.95#ibcon#enter sib2, iclass 31, count 2 2006.197.08:09:49.95#ibcon#flushed, iclass 31, count 2 2006.197.08:09:49.95#ibcon#about to write, iclass 31, count 2 2006.197.08:09:49.95#ibcon#wrote, iclass 31, count 2 2006.197.08:09:49.95#ibcon#about to read 3, iclass 31, count 2 2006.197.08:09:49.97#ibcon#read 3, iclass 31, count 2 2006.197.08:09:49.97#ibcon#about to read 4, iclass 31, count 2 2006.197.08:09:49.97#ibcon#read 4, iclass 31, count 2 2006.197.08:09:49.97#ibcon#about to read 5, iclass 31, count 2 2006.197.08:09:49.97#ibcon#read 5, iclass 31, count 2 2006.197.08:09:49.97#ibcon#about to read 6, iclass 31, count 2 2006.197.08:09:49.97#ibcon#read 6, iclass 31, count 2 2006.197.08:09:49.97#ibcon#end of sib2, iclass 31, count 2 2006.197.08:09:49.97#ibcon#*mode == 0, iclass 31, count 2 2006.197.08:09:49.97#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.197.08:09:49.97#ibcon#[25=AT07-06\r\n] 2006.197.08:09:49.97#ibcon#*before write, iclass 31, count 2 2006.197.08:09:49.97#ibcon#enter sib2, iclass 31, count 2 2006.197.08:09:49.97#ibcon#flushed, iclass 31, count 2 2006.197.08:09:49.97#ibcon#about to write, iclass 31, count 2 2006.197.08:09:49.97#ibcon#wrote, iclass 31, count 2 2006.197.08:09:49.97#ibcon#about to read 3, iclass 31, count 2 2006.197.08:09:50.00#ibcon#read 3, iclass 31, count 2 2006.197.08:09:50.00#ibcon#about to read 4, iclass 31, count 2 2006.197.08:09:50.00#ibcon#read 4, iclass 31, count 2 2006.197.08:09:50.00#ibcon#about to read 5, iclass 31, count 2 2006.197.08:09:50.00#ibcon#read 5, iclass 31, count 2 2006.197.08:09:50.00#ibcon#about to read 6, iclass 31, count 2 2006.197.08:09:50.00#ibcon#read 6, iclass 31, count 2 2006.197.08:09:50.00#ibcon#end of sib2, iclass 31, count 2 2006.197.08:09:50.00#ibcon#*after write, iclass 31, count 2 2006.197.08:09:50.00#ibcon#*before return 0, iclass 31, count 2 2006.197.08:09:50.00#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.197.08:09:50.00#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.197.08:09:50.00#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.197.08:09:50.00#ibcon#ireg 7 cls_cnt 0 2006.197.08:09:50.00#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.197.08:09:50.12#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.197.08:09:50.12#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.197.08:09:50.12#ibcon#enter wrdev, iclass 31, count 0 2006.197.08:09:50.12#ibcon#first serial, iclass 31, count 0 2006.197.08:09:50.12#ibcon#enter sib2, iclass 31, count 0 2006.197.08:09:50.12#ibcon#flushed, iclass 31, count 0 2006.197.08:09:50.12#ibcon#about to write, iclass 31, count 0 2006.197.08:09:50.12#ibcon#wrote, iclass 31, count 0 2006.197.08:09:50.12#ibcon#about to read 3, iclass 31, count 0 2006.197.08:09:50.14#ibcon#read 3, iclass 31, count 0 2006.197.08:09:50.14#ibcon#about to read 4, iclass 31, count 0 2006.197.08:09:50.14#ibcon#read 4, iclass 31, count 0 2006.197.08:09:50.14#ibcon#about to read 5, iclass 31, count 0 2006.197.08:09:50.14#ibcon#read 5, iclass 31, count 0 2006.197.08:09:50.14#ibcon#about to read 6, iclass 31, count 0 2006.197.08:09:50.14#ibcon#read 6, iclass 31, count 0 2006.197.08:09:50.14#ibcon#end of sib2, iclass 31, count 0 2006.197.08:09:50.14#ibcon#*mode == 0, iclass 31, count 0 2006.197.08:09:50.14#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.197.08:09:50.14#ibcon#[25=USB\r\n] 2006.197.08:09:50.14#ibcon#*before write, iclass 31, count 0 2006.197.08:09:50.14#ibcon#enter sib2, iclass 31, count 0 2006.197.08:09:50.14#ibcon#flushed, iclass 31, count 0 2006.197.08:09:50.14#ibcon#about to write, iclass 31, count 0 2006.197.08:09:50.14#ibcon#wrote, iclass 31, count 0 2006.197.08:09:50.14#ibcon#about to read 3, iclass 31, count 0 2006.197.08:09:50.17#ibcon#read 3, iclass 31, count 0 2006.197.08:09:50.17#ibcon#about to read 4, iclass 31, count 0 2006.197.08:09:50.17#ibcon#read 4, iclass 31, count 0 2006.197.08:09:50.17#ibcon#about to read 5, iclass 31, count 0 2006.197.08:09:50.17#ibcon#read 5, iclass 31, count 0 2006.197.08:09:50.17#ibcon#about to read 6, iclass 31, count 0 2006.197.08:09:50.17#ibcon#read 6, iclass 31, count 0 2006.197.08:09:50.17#ibcon#end of sib2, iclass 31, count 0 2006.197.08:09:50.17#ibcon#*after write, iclass 31, count 0 2006.197.08:09:50.17#ibcon#*before return 0, iclass 31, count 0 2006.197.08:09:50.17#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.197.08:09:50.17#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.197.08:09:50.17#ibcon#about to clear, iclass 31 cls_cnt 0 2006.197.08:09:50.17#ibcon#cleared, iclass 31 cls_cnt 0 2006.197.08:09:50.17$vc4f8/valo=8,852.99 2006.197.08:09:50.17#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.197.08:09:50.17#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.197.08:09:50.17#ibcon#ireg 17 cls_cnt 0 2006.197.08:09:50.17#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.197.08:09:50.17#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.197.08:09:50.17#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.197.08:09:50.17#ibcon#enter wrdev, iclass 33, count 0 2006.197.08:09:50.17#ibcon#first serial, iclass 33, count 0 2006.197.08:09:50.17#ibcon#enter sib2, iclass 33, count 0 2006.197.08:09:50.17#ibcon#flushed, iclass 33, count 0 2006.197.08:09:50.17#ibcon#about to write, iclass 33, count 0 2006.197.08:09:50.17#ibcon#wrote, iclass 33, count 0 2006.197.08:09:50.17#ibcon#about to read 3, iclass 33, count 0 2006.197.08:09:50.19#ibcon#read 3, iclass 33, count 0 2006.197.08:09:50.19#ibcon#about to read 4, iclass 33, count 0 2006.197.08:09:50.19#ibcon#read 4, iclass 33, count 0 2006.197.08:09:50.19#ibcon#about to read 5, iclass 33, count 0 2006.197.08:09:50.19#ibcon#read 5, iclass 33, count 0 2006.197.08:09:50.19#ibcon#about to read 6, iclass 33, count 0 2006.197.08:09:50.19#ibcon#read 6, iclass 33, count 0 2006.197.08:09:50.19#ibcon#end of sib2, iclass 33, count 0 2006.197.08:09:50.19#ibcon#*mode == 0, iclass 33, count 0 2006.197.08:09:50.19#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.197.08:09:50.19#ibcon#[26=FRQ=08,852.99\r\n] 2006.197.08:09:50.19#ibcon#*before write, iclass 33, count 0 2006.197.08:09:50.19#ibcon#enter sib2, iclass 33, count 0 2006.197.08:09:50.19#ibcon#flushed, iclass 33, count 0 2006.197.08:09:50.19#ibcon#about to write, iclass 33, count 0 2006.197.08:09:50.19#ibcon#wrote, iclass 33, count 0 2006.197.08:09:50.19#ibcon#about to read 3, iclass 33, count 0 2006.197.08:09:50.23#ibcon#read 3, iclass 33, count 0 2006.197.08:09:50.23#ibcon#about to read 4, iclass 33, count 0 2006.197.08:09:50.23#ibcon#read 4, iclass 33, count 0 2006.197.08:09:50.23#ibcon#about to read 5, iclass 33, count 0 2006.197.08:09:50.23#ibcon#read 5, iclass 33, count 0 2006.197.08:09:50.23#ibcon#about to read 6, iclass 33, count 0 2006.197.08:09:50.23#ibcon#read 6, iclass 33, count 0 2006.197.08:09:50.23#ibcon#end of sib2, iclass 33, count 0 2006.197.08:09:50.23#ibcon#*after write, iclass 33, count 0 2006.197.08:09:50.23#ibcon#*before return 0, iclass 33, count 0 2006.197.08:09:50.23#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.197.08:09:50.23#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.197.08:09:50.23#ibcon#about to clear, iclass 33 cls_cnt 0 2006.197.08:09:50.23#ibcon#cleared, iclass 33 cls_cnt 0 2006.197.08:09:50.23$vc4f8/va=8,7 2006.197.08:09:50.23#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.197.08:09:50.23#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.197.08:09:50.23#ibcon#ireg 11 cls_cnt 2 2006.197.08:09:50.23#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.197.08:09:50.29#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.197.08:09:50.29#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.197.08:09:50.29#ibcon#enter wrdev, iclass 35, count 2 2006.197.08:09:50.29#ibcon#first serial, iclass 35, count 2 2006.197.08:09:50.29#ibcon#enter sib2, iclass 35, count 2 2006.197.08:09:50.29#ibcon#flushed, iclass 35, count 2 2006.197.08:09:50.29#ibcon#about to write, iclass 35, count 2 2006.197.08:09:50.29#ibcon#wrote, iclass 35, count 2 2006.197.08:09:50.29#ibcon#about to read 3, iclass 35, count 2 2006.197.08:09:50.31#ibcon#read 3, iclass 35, count 2 2006.197.08:09:50.31#ibcon#about to read 4, iclass 35, count 2 2006.197.08:09:50.31#ibcon#read 4, iclass 35, count 2 2006.197.08:09:50.31#ibcon#about to read 5, iclass 35, count 2 2006.197.08:09:50.31#ibcon#read 5, iclass 35, count 2 2006.197.08:09:50.31#ibcon#about to read 6, iclass 35, count 2 2006.197.08:09:50.31#ibcon#read 6, iclass 35, count 2 2006.197.08:09:50.31#ibcon#end of sib2, iclass 35, count 2 2006.197.08:09:50.31#ibcon#*mode == 0, iclass 35, count 2 2006.197.08:09:50.31#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.197.08:09:50.31#ibcon#[25=AT08-07\r\n] 2006.197.08:09:50.31#ibcon#*before write, iclass 35, count 2 2006.197.08:09:50.31#ibcon#enter sib2, iclass 35, count 2 2006.197.08:09:50.31#ibcon#flushed, iclass 35, count 2 2006.197.08:09:50.31#ibcon#about to write, iclass 35, count 2 2006.197.08:09:50.31#ibcon#wrote, iclass 35, count 2 2006.197.08:09:50.31#ibcon#about to read 3, iclass 35, count 2 2006.197.08:09:50.34#ibcon#read 3, iclass 35, count 2 2006.197.08:09:50.34#ibcon#about to read 4, iclass 35, count 2 2006.197.08:09:50.34#ibcon#read 4, iclass 35, count 2 2006.197.08:09:50.34#ibcon#about to read 5, iclass 35, count 2 2006.197.08:09:50.34#ibcon#read 5, iclass 35, count 2 2006.197.08:09:50.34#ibcon#about to read 6, iclass 35, count 2 2006.197.08:09:50.34#ibcon#read 6, iclass 35, count 2 2006.197.08:09:50.34#ibcon#end of sib2, iclass 35, count 2 2006.197.08:09:50.34#ibcon#*after write, iclass 35, count 2 2006.197.08:09:50.34#ibcon#*before return 0, iclass 35, count 2 2006.197.08:09:50.34#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.197.08:09:50.34#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.197.08:09:50.34#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.197.08:09:50.34#ibcon#ireg 7 cls_cnt 0 2006.197.08:09:50.34#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.197.08:09:50.40#abcon#<5=/05 3.2 6.2 25.64 961002.8\r\n> 2006.197.08:09:50.42#abcon#{5=INTERFACE CLEAR} 2006.197.08:09:50.46#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.197.08:09:50.46#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.197.08:09:50.46#ibcon#enter wrdev, iclass 35, count 0 2006.197.08:09:50.46#ibcon#first serial, iclass 35, count 0 2006.197.08:09:50.46#ibcon#enter sib2, iclass 35, count 0 2006.197.08:09:50.46#ibcon#flushed, iclass 35, count 0 2006.197.08:09:50.46#ibcon#about to write, iclass 35, count 0 2006.197.08:09:50.46#ibcon#wrote, iclass 35, count 0 2006.197.08:09:50.46#ibcon#about to read 3, iclass 35, count 0 2006.197.08:09:50.48#ibcon#read 3, iclass 35, count 0 2006.197.08:09:50.48#ibcon#about to read 4, iclass 35, count 0 2006.197.08:09:50.48#ibcon#read 4, iclass 35, count 0 2006.197.08:09:50.48#ibcon#about to read 5, iclass 35, count 0 2006.197.08:09:50.48#ibcon#read 5, iclass 35, count 0 2006.197.08:09:50.48#ibcon#about to read 6, iclass 35, count 0 2006.197.08:09:50.48#ibcon#read 6, iclass 35, count 0 2006.197.08:09:50.48#ibcon#end of sib2, iclass 35, count 0 2006.197.08:09:50.48#ibcon#*mode == 0, iclass 35, count 0 2006.197.08:09:50.48#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.197.08:09:50.48#ibcon#[25=USB\r\n] 2006.197.08:09:50.48#ibcon#*before write, iclass 35, count 0 2006.197.08:09:50.48#ibcon#enter sib2, iclass 35, count 0 2006.197.08:09:50.48#ibcon#flushed, iclass 35, count 0 2006.197.08:09:50.48#ibcon#about to write, iclass 35, count 0 2006.197.08:09:50.48#ibcon#wrote, iclass 35, count 0 2006.197.08:09:50.48#ibcon#about to read 3, iclass 35, count 0 2006.197.08:09:50.48#abcon#[5=S1D000X0/0*\r\n] 2006.197.08:09:50.51#ibcon#read 3, iclass 35, count 0 2006.197.08:09:50.51#ibcon#about to read 4, iclass 35, count 0 2006.197.08:09:50.51#ibcon#read 4, iclass 35, count 0 2006.197.08:09:50.51#ibcon#about to read 5, iclass 35, count 0 2006.197.08:09:50.51#ibcon#read 5, iclass 35, count 0 2006.197.08:09:50.51#ibcon#about to read 6, iclass 35, count 0 2006.197.08:09:50.51#ibcon#read 6, iclass 35, count 0 2006.197.08:09:50.51#ibcon#end of sib2, iclass 35, count 0 2006.197.08:09:50.51#ibcon#*after write, iclass 35, count 0 2006.197.08:09:50.51#ibcon#*before return 0, iclass 35, count 0 2006.197.08:09:50.51#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.197.08:09:50.51#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.197.08:09:50.51#ibcon#about to clear, iclass 35 cls_cnt 0 2006.197.08:09:50.51#ibcon#cleared, iclass 35 cls_cnt 0 2006.197.08:09:50.51$vc4f8/vblo=1,632.99 2006.197.08:09:50.51#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.197.08:09:50.51#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.197.08:09:50.51#ibcon#ireg 17 cls_cnt 0 2006.197.08:09:50.51#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.197.08:09:50.51#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.197.08:09:50.51#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.197.08:09:50.51#ibcon#enter wrdev, iclass 3, count 0 2006.197.08:09:50.51#ibcon#first serial, iclass 3, count 0 2006.197.08:09:50.51#ibcon#enter sib2, iclass 3, count 0 2006.197.08:09:50.51#ibcon#flushed, iclass 3, count 0 2006.197.08:09:50.51#ibcon#about to write, iclass 3, count 0 2006.197.08:09:50.51#ibcon#wrote, iclass 3, count 0 2006.197.08:09:50.51#ibcon#about to read 3, iclass 3, count 0 2006.197.08:09:50.53#ibcon#read 3, iclass 3, count 0 2006.197.08:09:50.53#ibcon#about to read 4, iclass 3, count 0 2006.197.08:09:50.53#ibcon#read 4, iclass 3, count 0 2006.197.08:09:50.53#ibcon#about to read 5, iclass 3, count 0 2006.197.08:09:50.53#ibcon#read 5, iclass 3, count 0 2006.197.08:09:50.53#ibcon#about to read 6, iclass 3, count 0 2006.197.08:09:50.53#ibcon#read 6, iclass 3, count 0 2006.197.08:09:50.53#ibcon#end of sib2, iclass 3, count 0 2006.197.08:09:50.53#ibcon#*mode == 0, iclass 3, count 0 2006.197.08:09:50.53#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.197.08:09:50.53#ibcon#[28=FRQ=01,632.99\r\n] 2006.197.08:09:50.53#ibcon#*before write, iclass 3, count 0 2006.197.08:09:50.53#ibcon#enter sib2, iclass 3, count 0 2006.197.08:09:50.53#ibcon#flushed, iclass 3, count 0 2006.197.08:09:50.53#ibcon#about to write, iclass 3, count 0 2006.197.08:09:50.53#ibcon#wrote, iclass 3, count 0 2006.197.08:09:50.53#ibcon#about to read 3, iclass 3, count 0 2006.197.08:09:50.57#ibcon#read 3, iclass 3, count 0 2006.197.08:09:50.57#ibcon#about to read 4, iclass 3, count 0 2006.197.08:09:50.57#ibcon#read 4, iclass 3, count 0 2006.197.08:09:50.57#ibcon#about to read 5, iclass 3, count 0 2006.197.08:09:50.57#ibcon#read 5, iclass 3, count 0 2006.197.08:09:50.57#ibcon#about to read 6, iclass 3, count 0 2006.197.08:09:50.57#ibcon#read 6, iclass 3, count 0 2006.197.08:09:50.57#ibcon#end of sib2, iclass 3, count 0 2006.197.08:09:50.57#ibcon#*after write, iclass 3, count 0 2006.197.08:09:50.57#ibcon#*before return 0, iclass 3, count 0 2006.197.08:09:50.57#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.197.08:09:50.57#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.197.08:09:50.57#ibcon#about to clear, iclass 3 cls_cnt 0 2006.197.08:09:50.57#ibcon#cleared, iclass 3 cls_cnt 0 2006.197.08:09:50.57$vc4f8/vb=1,4 2006.197.08:09:50.57#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.197.08:09:50.57#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.197.08:09:50.57#ibcon#ireg 11 cls_cnt 2 2006.197.08:09:50.57#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.197.08:09:50.57#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.197.08:09:50.57#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.197.08:09:50.57#ibcon#enter wrdev, iclass 5, count 2 2006.197.08:09:50.57#ibcon#first serial, iclass 5, count 2 2006.197.08:09:50.57#ibcon#enter sib2, iclass 5, count 2 2006.197.08:09:50.57#ibcon#flushed, iclass 5, count 2 2006.197.08:09:50.57#ibcon#about to write, iclass 5, count 2 2006.197.08:09:50.57#ibcon#wrote, iclass 5, count 2 2006.197.08:09:50.57#ibcon#about to read 3, iclass 5, count 2 2006.197.08:09:50.59#ibcon#read 3, iclass 5, count 2 2006.197.08:09:50.59#ibcon#about to read 4, iclass 5, count 2 2006.197.08:09:50.59#ibcon#read 4, iclass 5, count 2 2006.197.08:09:50.59#ibcon#about to read 5, iclass 5, count 2 2006.197.08:09:50.59#ibcon#read 5, iclass 5, count 2 2006.197.08:09:50.59#ibcon#about to read 6, iclass 5, count 2 2006.197.08:09:50.59#ibcon#read 6, iclass 5, count 2 2006.197.08:09:50.59#ibcon#end of sib2, iclass 5, count 2 2006.197.08:09:50.59#ibcon#*mode == 0, iclass 5, count 2 2006.197.08:09:50.59#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.197.08:09:50.59#ibcon#[27=AT01-04\r\n] 2006.197.08:09:50.59#ibcon#*before write, iclass 5, count 2 2006.197.08:09:50.59#ibcon#enter sib2, iclass 5, count 2 2006.197.08:09:50.59#ibcon#flushed, iclass 5, count 2 2006.197.08:09:50.59#ibcon#about to write, iclass 5, count 2 2006.197.08:09:50.59#ibcon#wrote, iclass 5, count 2 2006.197.08:09:50.59#ibcon#about to read 3, iclass 5, count 2 2006.197.08:09:50.62#ibcon#read 3, iclass 5, count 2 2006.197.08:09:50.62#ibcon#about to read 4, iclass 5, count 2 2006.197.08:09:50.62#ibcon#read 4, iclass 5, count 2 2006.197.08:09:50.62#ibcon#about to read 5, iclass 5, count 2 2006.197.08:09:50.62#ibcon#read 5, iclass 5, count 2 2006.197.08:09:50.62#ibcon#about to read 6, iclass 5, count 2 2006.197.08:09:50.62#ibcon#read 6, iclass 5, count 2 2006.197.08:09:50.62#ibcon#end of sib2, iclass 5, count 2 2006.197.08:09:50.62#ibcon#*after write, iclass 5, count 2 2006.197.08:09:50.62#ibcon#*before return 0, iclass 5, count 2 2006.197.08:09:50.62#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.197.08:09:50.62#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.197.08:09:50.62#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.197.08:09:50.62#ibcon#ireg 7 cls_cnt 0 2006.197.08:09:50.62#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.197.08:09:50.74#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.197.08:09:50.74#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.197.08:09:50.74#ibcon#enter wrdev, iclass 5, count 0 2006.197.08:09:50.74#ibcon#first serial, iclass 5, count 0 2006.197.08:09:50.74#ibcon#enter sib2, iclass 5, count 0 2006.197.08:09:50.74#ibcon#flushed, iclass 5, count 0 2006.197.08:09:50.74#ibcon#about to write, iclass 5, count 0 2006.197.08:09:50.74#ibcon#wrote, iclass 5, count 0 2006.197.08:09:50.74#ibcon#about to read 3, iclass 5, count 0 2006.197.08:09:50.76#ibcon#read 3, iclass 5, count 0 2006.197.08:09:50.76#ibcon#about to read 4, iclass 5, count 0 2006.197.08:09:50.76#ibcon#read 4, iclass 5, count 0 2006.197.08:09:50.76#ibcon#about to read 5, iclass 5, count 0 2006.197.08:09:50.76#ibcon#read 5, iclass 5, count 0 2006.197.08:09:50.76#ibcon#about to read 6, iclass 5, count 0 2006.197.08:09:50.76#ibcon#read 6, iclass 5, count 0 2006.197.08:09:50.76#ibcon#end of sib2, iclass 5, count 0 2006.197.08:09:50.76#ibcon#*mode == 0, iclass 5, count 0 2006.197.08:09:50.76#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.197.08:09:50.76#ibcon#[27=USB\r\n] 2006.197.08:09:50.76#ibcon#*before write, iclass 5, count 0 2006.197.08:09:50.76#ibcon#enter sib2, iclass 5, count 0 2006.197.08:09:50.76#ibcon#flushed, iclass 5, count 0 2006.197.08:09:50.76#ibcon#about to write, iclass 5, count 0 2006.197.08:09:50.76#ibcon#wrote, iclass 5, count 0 2006.197.08:09:50.76#ibcon#about to read 3, iclass 5, count 0 2006.197.08:09:50.79#ibcon#read 3, iclass 5, count 0 2006.197.08:09:50.79#ibcon#about to read 4, iclass 5, count 0 2006.197.08:09:50.79#ibcon#read 4, iclass 5, count 0 2006.197.08:09:50.79#ibcon#about to read 5, iclass 5, count 0 2006.197.08:09:50.79#ibcon#read 5, iclass 5, count 0 2006.197.08:09:50.79#ibcon#about to read 6, iclass 5, count 0 2006.197.08:09:50.79#ibcon#read 6, iclass 5, count 0 2006.197.08:09:50.79#ibcon#end of sib2, iclass 5, count 0 2006.197.08:09:50.79#ibcon#*after write, iclass 5, count 0 2006.197.08:09:50.79#ibcon#*before return 0, iclass 5, count 0 2006.197.08:09:50.79#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.197.08:09:50.79#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.197.08:09:50.79#ibcon#about to clear, iclass 5 cls_cnt 0 2006.197.08:09:50.79#ibcon#cleared, iclass 5 cls_cnt 0 2006.197.08:09:50.79$vc4f8/vblo=2,640.99 2006.197.08:09:50.79#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.197.08:09:50.79#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.197.08:09:50.79#ibcon#ireg 17 cls_cnt 0 2006.197.08:09:50.79#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.197.08:09:50.79#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.197.08:09:50.79#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.197.08:09:50.79#ibcon#enter wrdev, iclass 7, count 0 2006.197.08:09:50.79#ibcon#first serial, iclass 7, count 0 2006.197.08:09:50.79#ibcon#enter sib2, iclass 7, count 0 2006.197.08:09:50.79#ibcon#flushed, iclass 7, count 0 2006.197.08:09:50.79#ibcon#about to write, iclass 7, count 0 2006.197.08:09:50.79#ibcon#wrote, iclass 7, count 0 2006.197.08:09:50.79#ibcon#about to read 3, iclass 7, count 0 2006.197.08:09:50.81#ibcon#read 3, iclass 7, count 0 2006.197.08:09:50.81#ibcon#about to read 4, iclass 7, count 0 2006.197.08:09:50.81#ibcon#read 4, iclass 7, count 0 2006.197.08:09:50.81#ibcon#about to read 5, iclass 7, count 0 2006.197.08:09:50.81#ibcon#read 5, iclass 7, count 0 2006.197.08:09:50.81#ibcon#about to read 6, iclass 7, count 0 2006.197.08:09:50.81#ibcon#read 6, iclass 7, count 0 2006.197.08:09:50.81#ibcon#end of sib2, iclass 7, count 0 2006.197.08:09:50.81#ibcon#*mode == 0, iclass 7, count 0 2006.197.08:09:50.81#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.197.08:09:50.81#ibcon#[28=FRQ=02,640.99\r\n] 2006.197.08:09:50.81#ibcon#*before write, iclass 7, count 0 2006.197.08:09:50.81#ibcon#enter sib2, iclass 7, count 0 2006.197.08:09:50.81#ibcon#flushed, iclass 7, count 0 2006.197.08:09:50.81#ibcon#about to write, iclass 7, count 0 2006.197.08:09:50.81#ibcon#wrote, iclass 7, count 0 2006.197.08:09:50.81#ibcon#about to read 3, iclass 7, count 0 2006.197.08:09:50.85#ibcon#read 3, iclass 7, count 0 2006.197.08:09:50.85#ibcon#about to read 4, iclass 7, count 0 2006.197.08:09:50.85#ibcon#read 4, iclass 7, count 0 2006.197.08:09:50.85#ibcon#about to read 5, iclass 7, count 0 2006.197.08:09:50.85#ibcon#read 5, iclass 7, count 0 2006.197.08:09:50.85#ibcon#about to read 6, iclass 7, count 0 2006.197.08:09:50.85#ibcon#read 6, iclass 7, count 0 2006.197.08:09:50.85#ibcon#end of sib2, iclass 7, count 0 2006.197.08:09:50.85#ibcon#*after write, iclass 7, count 0 2006.197.08:09:50.85#ibcon#*before return 0, iclass 7, count 0 2006.197.08:09:50.85#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.197.08:09:50.85#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.197.08:09:50.85#ibcon#about to clear, iclass 7 cls_cnt 0 2006.197.08:09:50.85#ibcon#cleared, iclass 7 cls_cnt 0 2006.197.08:09:50.85$vc4f8/vb=2,4 2006.197.08:09:50.85#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.197.08:09:50.85#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.197.08:09:50.85#ibcon#ireg 11 cls_cnt 2 2006.197.08:09:50.85#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.197.08:09:50.91#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.197.08:09:50.91#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.197.08:09:50.91#ibcon#enter wrdev, iclass 11, count 2 2006.197.08:09:50.91#ibcon#first serial, iclass 11, count 2 2006.197.08:09:50.91#ibcon#enter sib2, iclass 11, count 2 2006.197.08:09:50.91#ibcon#flushed, iclass 11, count 2 2006.197.08:09:50.91#ibcon#about to write, iclass 11, count 2 2006.197.08:09:50.91#ibcon#wrote, iclass 11, count 2 2006.197.08:09:50.91#ibcon#about to read 3, iclass 11, count 2 2006.197.08:09:50.93#ibcon#read 3, iclass 11, count 2 2006.197.08:09:50.93#ibcon#about to read 4, iclass 11, count 2 2006.197.08:09:50.93#ibcon#read 4, iclass 11, count 2 2006.197.08:09:50.93#ibcon#about to read 5, iclass 11, count 2 2006.197.08:09:50.93#ibcon#read 5, iclass 11, count 2 2006.197.08:09:50.93#ibcon#about to read 6, iclass 11, count 2 2006.197.08:09:50.93#ibcon#read 6, iclass 11, count 2 2006.197.08:09:50.93#ibcon#end of sib2, iclass 11, count 2 2006.197.08:09:50.93#ibcon#*mode == 0, iclass 11, count 2 2006.197.08:09:50.93#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.197.08:09:50.93#ibcon#[27=AT02-04\r\n] 2006.197.08:09:50.93#ibcon#*before write, iclass 11, count 2 2006.197.08:09:50.93#ibcon#enter sib2, iclass 11, count 2 2006.197.08:09:50.93#ibcon#flushed, iclass 11, count 2 2006.197.08:09:50.93#ibcon#about to write, iclass 11, count 2 2006.197.08:09:50.93#ibcon#wrote, iclass 11, count 2 2006.197.08:09:50.93#ibcon#about to read 3, iclass 11, count 2 2006.197.08:09:50.96#ibcon#read 3, iclass 11, count 2 2006.197.08:09:50.96#ibcon#about to read 4, iclass 11, count 2 2006.197.08:09:50.96#ibcon#read 4, iclass 11, count 2 2006.197.08:09:50.96#ibcon#about to read 5, iclass 11, count 2 2006.197.08:09:50.96#ibcon#read 5, iclass 11, count 2 2006.197.08:09:50.96#ibcon#about to read 6, iclass 11, count 2 2006.197.08:09:50.96#ibcon#read 6, iclass 11, count 2 2006.197.08:09:50.96#ibcon#end of sib2, iclass 11, count 2 2006.197.08:09:50.96#ibcon#*after write, iclass 11, count 2 2006.197.08:09:50.96#ibcon#*before return 0, iclass 11, count 2 2006.197.08:09:50.96#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.197.08:09:50.96#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.197.08:09:50.96#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.197.08:09:50.96#ibcon#ireg 7 cls_cnt 0 2006.197.08:09:50.96#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.197.08:09:51.08#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.197.08:09:51.08#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.197.08:09:51.08#ibcon#enter wrdev, iclass 11, count 0 2006.197.08:09:51.08#ibcon#first serial, iclass 11, count 0 2006.197.08:09:51.08#ibcon#enter sib2, iclass 11, count 0 2006.197.08:09:51.08#ibcon#flushed, iclass 11, count 0 2006.197.08:09:51.08#ibcon#about to write, iclass 11, count 0 2006.197.08:09:51.08#ibcon#wrote, iclass 11, count 0 2006.197.08:09:51.08#ibcon#about to read 3, iclass 11, count 0 2006.197.08:09:51.10#ibcon#read 3, iclass 11, count 0 2006.197.08:09:51.10#ibcon#about to read 4, iclass 11, count 0 2006.197.08:09:51.10#ibcon#read 4, iclass 11, count 0 2006.197.08:09:51.10#ibcon#about to read 5, iclass 11, count 0 2006.197.08:09:51.10#ibcon#read 5, iclass 11, count 0 2006.197.08:09:51.10#ibcon#about to read 6, iclass 11, count 0 2006.197.08:09:51.10#ibcon#read 6, iclass 11, count 0 2006.197.08:09:51.10#ibcon#end of sib2, iclass 11, count 0 2006.197.08:09:51.10#ibcon#*mode == 0, iclass 11, count 0 2006.197.08:09:51.10#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.197.08:09:51.10#ibcon#[27=USB\r\n] 2006.197.08:09:51.10#ibcon#*before write, iclass 11, count 0 2006.197.08:09:51.10#ibcon#enter sib2, iclass 11, count 0 2006.197.08:09:51.10#ibcon#flushed, iclass 11, count 0 2006.197.08:09:51.10#ibcon#about to write, iclass 11, count 0 2006.197.08:09:51.10#ibcon#wrote, iclass 11, count 0 2006.197.08:09:51.10#ibcon#about to read 3, iclass 11, count 0 2006.197.08:09:51.13#ibcon#read 3, iclass 11, count 0 2006.197.08:09:51.13#ibcon#about to read 4, iclass 11, count 0 2006.197.08:09:51.13#ibcon#read 4, iclass 11, count 0 2006.197.08:09:51.13#ibcon#about to read 5, iclass 11, count 0 2006.197.08:09:51.13#ibcon#read 5, iclass 11, count 0 2006.197.08:09:51.13#ibcon#about to read 6, iclass 11, count 0 2006.197.08:09:51.13#ibcon#read 6, iclass 11, count 0 2006.197.08:09:51.13#ibcon#end of sib2, iclass 11, count 0 2006.197.08:09:51.13#ibcon#*after write, iclass 11, count 0 2006.197.08:09:51.13#ibcon#*before return 0, iclass 11, count 0 2006.197.08:09:51.13#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.197.08:09:51.13#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.197.08:09:51.13#ibcon#about to clear, iclass 11 cls_cnt 0 2006.197.08:09:51.13#ibcon#cleared, iclass 11 cls_cnt 0 2006.197.08:09:51.13$vc4f8/vblo=3,656.99 2006.197.08:09:51.13#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.197.08:09:51.13#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.197.08:09:51.13#ibcon#ireg 17 cls_cnt 0 2006.197.08:09:51.13#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.197.08:09:51.13#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.197.08:09:51.13#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.197.08:09:51.13#ibcon#enter wrdev, iclass 13, count 0 2006.197.08:09:51.13#ibcon#first serial, iclass 13, count 0 2006.197.08:09:51.13#ibcon#enter sib2, iclass 13, count 0 2006.197.08:09:51.13#ibcon#flushed, iclass 13, count 0 2006.197.08:09:51.13#ibcon#about to write, iclass 13, count 0 2006.197.08:09:51.13#ibcon#wrote, iclass 13, count 0 2006.197.08:09:51.13#ibcon#about to read 3, iclass 13, count 0 2006.197.08:09:51.15#ibcon#read 3, iclass 13, count 0 2006.197.08:09:51.15#ibcon#about to read 4, iclass 13, count 0 2006.197.08:09:51.15#ibcon#read 4, iclass 13, count 0 2006.197.08:09:51.15#ibcon#about to read 5, iclass 13, count 0 2006.197.08:09:51.15#ibcon#read 5, iclass 13, count 0 2006.197.08:09:51.15#ibcon#about to read 6, iclass 13, count 0 2006.197.08:09:51.15#ibcon#read 6, iclass 13, count 0 2006.197.08:09:51.15#ibcon#end of sib2, iclass 13, count 0 2006.197.08:09:51.15#ibcon#*mode == 0, iclass 13, count 0 2006.197.08:09:51.15#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.197.08:09:51.15#ibcon#[28=FRQ=03,656.99\r\n] 2006.197.08:09:51.15#ibcon#*before write, iclass 13, count 0 2006.197.08:09:51.15#ibcon#enter sib2, iclass 13, count 0 2006.197.08:09:51.15#ibcon#flushed, iclass 13, count 0 2006.197.08:09:51.15#ibcon#about to write, iclass 13, count 0 2006.197.08:09:51.15#ibcon#wrote, iclass 13, count 0 2006.197.08:09:51.15#ibcon#about to read 3, iclass 13, count 0 2006.197.08:09:51.19#ibcon#read 3, iclass 13, count 0 2006.197.08:09:51.19#ibcon#about to read 4, iclass 13, count 0 2006.197.08:09:51.19#ibcon#read 4, iclass 13, count 0 2006.197.08:09:51.19#ibcon#about to read 5, iclass 13, count 0 2006.197.08:09:51.19#ibcon#read 5, iclass 13, count 0 2006.197.08:09:51.19#ibcon#about to read 6, iclass 13, count 0 2006.197.08:09:51.19#ibcon#read 6, iclass 13, count 0 2006.197.08:09:51.19#ibcon#end of sib2, iclass 13, count 0 2006.197.08:09:51.19#ibcon#*after write, iclass 13, count 0 2006.197.08:09:51.19#ibcon#*before return 0, iclass 13, count 0 2006.197.08:09:51.19#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.197.08:09:51.19#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.197.08:09:51.19#ibcon#about to clear, iclass 13 cls_cnt 0 2006.197.08:09:51.19#ibcon#cleared, iclass 13 cls_cnt 0 2006.197.08:09:51.19$vc4f8/vb=3,4 2006.197.08:09:51.19#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.197.08:09:51.19#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.197.08:09:51.19#ibcon#ireg 11 cls_cnt 2 2006.197.08:09:51.19#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.197.08:09:51.25#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.197.08:09:51.25#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.197.08:09:51.25#ibcon#enter wrdev, iclass 15, count 2 2006.197.08:09:51.25#ibcon#first serial, iclass 15, count 2 2006.197.08:09:51.25#ibcon#enter sib2, iclass 15, count 2 2006.197.08:09:51.25#ibcon#flushed, iclass 15, count 2 2006.197.08:09:51.25#ibcon#about to write, iclass 15, count 2 2006.197.08:09:51.25#ibcon#wrote, iclass 15, count 2 2006.197.08:09:51.25#ibcon#about to read 3, iclass 15, count 2 2006.197.08:09:51.27#ibcon#read 3, iclass 15, count 2 2006.197.08:09:51.27#ibcon#about to read 4, iclass 15, count 2 2006.197.08:09:51.27#ibcon#read 4, iclass 15, count 2 2006.197.08:09:51.27#ibcon#about to read 5, iclass 15, count 2 2006.197.08:09:51.27#ibcon#read 5, iclass 15, count 2 2006.197.08:09:51.27#ibcon#about to read 6, iclass 15, count 2 2006.197.08:09:51.27#ibcon#read 6, iclass 15, count 2 2006.197.08:09:51.27#ibcon#end of sib2, iclass 15, count 2 2006.197.08:09:51.27#ibcon#*mode == 0, iclass 15, count 2 2006.197.08:09:51.27#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.197.08:09:51.27#ibcon#[27=AT03-04\r\n] 2006.197.08:09:51.27#ibcon#*before write, iclass 15, count 2 2006.197.08:09:51.27#ibcon#enter sib2, iclass 15, count 2 2006.197.08:09:51.27#ibcon#flushed, iclass 15, count 2 2006.197.08:09:51.27#ibcon#about to write, iclass 15, count 2 2006.197.08:09:51.27#ibcon#wrote, iclass 15, count 2 2006.197.08:09:51.27#ibcon#about to read 3, iclass 15, count 2 2006.197.08:09:51.30#ibcon#read 3, iclass 15, count 2 2006.197.08:09:51.30#ibcon#about to read 4, iclass 15, count 2 2006.197.08:09:51.30#ibcon#read 4, iclass 15, count 2 2006.197.08:09:51.30#ibcon#about to read 5, iclass 15, count 2 2006.197.08:09:51.30#ibcon#read 5, iclass 15, count 2 2006.197.08:09:51.30#ibcon#about to read 6, iclass 15, count 2 2006.197.08:09:51.30#ibcon#read 6, iclass 15, count 2 2006.197.08:09:51.30#ibcon#end of sib2, iclass 15, count 2 2006.197.08:09:51.30#ibcon#*after write, iclass 15, count 2 2006.197.08:09:51.30#ibcon#*before return 0, iclass 15, count 2 2006.197.08:09:51.30#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.197.08:09:51.30#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.197.08:09:51.30#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.197.08:09:51.30#ibcon#ireg 7 cls_cnt 0 2006.197.08:09:51.30#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.197.08:09:51.42#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.197.08:09:51.42#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.197.08:09:51.42#ibcon#enter wrdev, iclass 15, count 0 2006.197.08:09:51.42#ibcon#first serial, iclass 15, count 0 2006.197.08:09:51.42#ibcon#enter sib2, iclass 15, count 0 2006.197.08:09:51.42#ibcon#flushed, iclass 15, count 0 2006.197.08:09:51.42#ibcon#about to write, iclass 15, count 0 2006.197.08:09:51.42#ibcon#wrote, iclass 15, count 0 2006.197.08:09:51.42#ibcon#about to read 3, iclass 15, count 0 2006.197.08:09:51.44#ibcon#read 3, iclass 15, count 0 2006.197.08:09:51.44#ibcon#about to read 4, iclass 15, count 0 2006.197.08:09:51.44#ibcon#read 4, iclass 15, count 0 2006.197.08:09:51.44#ibcon#about to read 5, iclass 15, count 0 2006.197.08:09:51.44#ibcon#read 5, iclass 15, count 0 2006.197.08:09:51.44#ibcon#about to read 6, iclass 15, count 0 2006.197.08:09:51.44#ibcon#read 6, iclass 15, count 0 2006.197.08:09:51.44#ibcon#end of sib2, iclass 15, count 0 2006.197.08:09:51.44#ibcon#*mode == 0, iclass 15, count 0 2006.197.08:09:51.44#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.197.08:09:51.44#ibcon#[27=USB\r\n] 2006.197.08:09:51.44#ibcon#*before write, iclass 15, count 0 2006.197.08:09:51.44#ibcon#enter sib2, iclass 15, count 0 2006.197.08:09:51.44#ibcon#flushed, iclass 15, count 0 2006.197.08:09:51.44#ibcon#about to write, iclass 15, count 0 2006.197.08:09:51.44#ibcon#wrote, iclass 15, count 0 2006.197.08:09:51.44#ibcon#about to read 3, iclass 15, count 0 2006.197.08:09:51.47#ibcon#read 3, iclass 15, count 0 2006.197.08:09:51.47#ibcon#about to read 4, iclass 15, count 0 2006.197.08:09:51.47#ibcon#read 4, iclass 15, count 0 2006.197.08:09:51.47#ibcon#about to read 5, iclass 15, count 0 2006.197.08:09:51.47#ibcon#read 5, iclass 15, count 0 2006.197.08:09:51.47#ibcon#about to read 6, iclass 15, count 0 2006.197.08:09:51.47#ibcon#read 6, iclass 15, count 0 2006.197.08:09:51.47#ibcon#end of sib2, iclass 15, count 0 2006.197.08:09:51.47#ibcon#*after write, iclass 15, count 0 2006.197.08:09:51.47#ibcon#*before return 0, iclass 15, count 0 2006.197.08:09:51.47#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.197.08:09:51.47#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.197.08:09:51.47#ibcon#about to clear, iclass 15 cls_cnt 0 2006.197.08:09:51.47#ibcon#cleared, iclass 15 cls_cnt 0 2006.197.08:09:51.47$vc4f8/vblo=4,712.99 2006.197.08:09:51.47#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.197.08:09:51.47#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.197.08:09:51.47#ibcon#ireg 17 cls_cnt 0 2006.197.08:09:51.47#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.197.08:09:51.47#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.197.08:09:51.47#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.197.08:09:51.47#ibcon#enter wrdev, iclass 17, count 0 2006.197.08:09:51.47#ibcon#first serial, iclass 17, count 0 2006.197.08:09:51.47#ibcon#enter sib2, iclass 17, count 0 2006.197.08:09:51.47#ibcon#flushed, iclass 17, count 0 2006.197.08:09:51.47#ibcon#about to write, iclass 17, count 0 2006.197.08:09:51.47#ibcon#wrote, iclass 17, count 0 2006.197.08:09:51.47#ibcon#about to read 3, iclass 17, count 0 2006.197.08:09:51.49#ibcon#read 3, iclass 17, count 0 2006.197.08:09:51.49#ibcon#about to read 4, iclass 17, count 0 2006.197.08:09:51.49#ibcon#read 4, iclass 17, count 0 2006.197.08:09:51.49#ibcon#about to read 5, iclass 17, count 0 2006.197.08:09:51.49#ibcon#read 5, iclass 17, count 0 2006.197.08:09:51.49#ibcon#about to read 6, iclass 17, count 0 2006.197.08:09:51.49#ibcon#read 6, iclass 17, count 0 2006.197.08:09:51.49#ibcon#end of sib2, iclass 17, count 0 2006.197.08:09:51.49#ibcon#*mode == 0, iclass 17, count 0 2006.197.08:09:51.49#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.197.08:09:51.49#ibcon#[28=FRQ=04,712.99\r\n] 2006.197.08:09:51.49#ibcon#*before write, iclass 17, count 0 2006.197.08:09:51.49#ibcon#enter sib2, iclass 17, count 0 2006.197.08:09:51.49#ibcon#flushed, iclass 17, count 0 2006.197.08:09:51.49#ibcon#about to write, iclass 17, count 0 2006.197.08:09:51.49#ibcon#wrote, iclass 17, count 0 2006.197.08:09:51.49#ibcon#about to read 3, iclass 17, count 0 2006.197.08:09:51.53#ibcon#read 3, iclass 17, count 0 2006.197.08:09:51.53#ibcon#about to read 4, iclass 17, count 0 2006.197.08:09:51.53#ibcon#read 4, iclass 17, count 0 2006.197.08:09:51.53#ibcon#about to read 5, iclass 17, count 0 2006.197.08:09:51.53#ibcon#read 5, iclass 17, count 0 2006.197.08:09:51.53#ibcon#about to read 6, iclass 17, count 0 2006.197.08:09:51.53#ibcon#read 6, iclass 17, count 0 2006.197.08:09:51.53#ibcon#end of sib2, iclass 17, count 0 2006.197.08:09:51.53#ibcon#*after write, iclass 17, count 0 2006.197.08:09:51.53#ibcon#*before return 0, iclass 17, count 0 2006.197.08:09:51.53#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.197.08:09:51.53#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.197.08:09:51.53#ibcon#about to clear, iclass 17 cls_cnt 0 2006.197.08:09:51.53#ibcon#cleared, iclass 17 cls_cnt 0 2006.197.08:09:51.53$vc4f8/vb=4,4 2006.197.08:09:51.53#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.197.08:09:51.53#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.197.08:09:51.53#ibcon#ireg 11 cls_cnt 2 2006.197.08:09:51.53#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.197.08:09:51.59#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.197.08:09:51.59#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.197.08:09:51.59#ibcon#enter wrdev, iclass 19, count 2 2006.197.08:09:51.59#ibcon#first serial, iclass 19, count 2 2006.197.08:09:51.59#ibcon#enter sib2, iclass 19, count 2 2006.197.08:09:51.59#ibcon#flushed, iclass 19, count 2 2006.197.08:09:51.59#ibcon#about to write, iclass 19, count 2 2006.197.08:09:51.59#ibcon#wrote, iclass 19, count 2 2006.197.08:09:51.59#ibcon#about to read 3, iclass 19, count 2 2006.197.08:09:51.61#ibcon#read 3, iclass 19, count 2 2006.197.08:09:51.61#ibcon#about to read 4, iclass 19, count 2 2006.197.08:09:51.61#ibcon#read 4, iclass 19, count 2 2006.197.08:09:51.61#ibcon#about to read 5, iclass 19, count 2 2006.197.08:09:51.61#ibcon#read 5, iclass 19, count 2 2006.197.08:09:51.61#ibcon#about to read 6, iclass 19, count 2 2006.197.08:09:51.61#ibcon#read 6, iclass 19, count 2 2006.197.08:09:51.61#ibcon#end of sib2, iclass 19, count 2 2006.197.08:09:51.61#ibcon#*mode == 0, iclass 19, count 2 2006.197.08:09:51.61#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.197.08:09:51.61#ibcon#[27=AT04-04\r\n] 2006.197.08:09:51.61#ibcon#*before write, iclass 19, count 2 2006.197.08:09:51.61#ibcon#enter sib2, iclass 19, count 2 2006.197.08:09:51.61#ibcon#flushed, iclass 19, count 2 2006.197.08:09:51.61#ibcon#about to write, iclass 19, count 2 2006.197.08:09:51.61#ibcon#wrote, iclass 19, count 2 2006.197.08:09:51.61#ibcon#about to read 3, iclass 19, count 2 2006.197.08:09:51.64#ibcon#read 3, iclass 19, count 2 2006.197.08:09:51.64#ibcon#about to read 4, iclass 19, count 2 2006.197.08:09:51.64#ibcon#read 4, iclass 19, count 2 2006.197.08:09:51.64#ibcon#about to read 5, iclass 19, count 2 2006.197.08:09:51.64#ibcon#read 5, iclass 19, count 2 2006.197.08:09:51.64#ibcon#about to read 6, iclass 19, count 2 2006.197.08:09:51.64#ibcon#read 6, iclass 19, count 2 2006.197.08:09:51.64#ibcon#end of sib2, iclass 19, count 2 2006.197.08:09:51.64#ibcon#*after write, iclass 19, count 2 2006.197.08:09:51.64#ibcon#*before return 0, iclass 19, count 2 2006.197.08:09:51.64#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.197.08:09:51.64#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.197.08:09:51.64#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.197.08:09:51.64#ibcon#ireg 7 cls_cnt 0 2006.197.08:09:51.64#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.197.08:09:51.76#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.197.08:09:51.76#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.197.08:09:51.76#ibcon#enter wrdev, iclass 19, count 0 2006.197.08:09:51.76#ibcon#first serial, iclass 19, count 0 2006.197.08:09:51.76#ibcon#enter sib2, iclass 19, count 0 2006.197.08:09:51.76#ibcon#flushed, iclass 19, count 0 2006.197.08:09:51.76#ibcon#about to write, iclass 19, count 0 2006.197.08:09:51.76#ibcon#wrote, iclass 19, count 0 2006.197.08:09:51.76#ibcon#about to read 3, iclass 19, count 0 2006.197.08:09:51.78#ibcon#read 3, iclass 19, count 0 2006.197.08:09:51.78#ibcon#about to read 4, iclass 19, count 0 2006.197.08:09:51.78#ibcon#read 4, iclass 19, count 0 2006.197.08:09:51.78#ibcon#about to read 5, iclass 19, count 0 2006.197.08:09:51.78#ibcon#read 5, iclass 19, count 0 2006.197.08:09:51.78#ibcon#about to read 6, iclass 19, count 0 2006.197.08:09:51.78#ibcon#read 6, iclass 19, count 0 2006.197.08:09:51.78#ibcon#end of sib2, iclass 19, count 0 2006.197.08:09:51.78#ibcon#*mode == 0, iclass 19, count 0 2006.197.08:09:51.78#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.197.08:09:51.78#ibcon#[27=USB\r\n] 2006.197.08:09:51.78#ibcon#*before write, iclass 19, count 0 2006.197.08:09:51.78#ibcon#enter sib2, iclass 19, count 0 2006.197.08:09:51.78#ibcon#flushed, iclass 19, count 0 2006.197.08:09:51.78#ibcon#about to write, iclass 19, count 0 2006.197.08:09:51.78#ibcon#wrote, iclass 19, count 0 2006.197.08:09:51.78#ibcon#about to read 3, iclass 19, count 0 2006.197.08:09:51.81#ibcon#read 3, iclass 19, count 0 2006.197.08:09:51.81#ibcon#about to read 4, iclass 19, count 0 2006.197.08:09:51.81#ibcon#read 4, iclass 19, count 0 2006.197.08:09:51.81#ibcon#about to read 5, iclass 19, count 0 2006.197.08:09:51.81#ibcon#read 5, iclass 19, count 0 2006.197.08:09:51.81#ibcon#about to read 6, iclass 19, count 0 2006.197.08:09:51.81#ibcon#read 6, iclass 19, count 0 2006.197.08:09:51.81#ibcon#end of sib2, iclass 19, count 0 2006.197.08:09:51.81#ibcon#*after write, iclass 19, count 0 2006.197.08:09:51.81#ibcon#*before return 0, iclass 19, count 0 2006.197.08:09:51.81#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.197.08:09:51.81#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.197.08:09:51.81#ibcon#about to clear, iclass 19 cls_cnt 0 2006.197.08:09:51.81#ibcon#cleared, iclass 19 cls_cnt 0 2006.197.08:09:51.81$vc4f8/vblo=5,744.99 2006.197.08:09:51.81#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.197.08:09:51.81#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.197.08:09:51.81#ibcon#ireg 17 cls_cnt 0 2006.197.08:09:51.81#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.197.08:09:51.81#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.197.08:09:51.81#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.197.08:09:51.81#ibcon#enter wrdev, iclass 21, count 0 2006.197.08:09:51.81#ibcon#first serial, iclass 21, count 0 2006.197.08:09:51.81#ibcon#enter sib2, iclass 21, count 0 2006.197.08:09:51.81#ibcon#flushed, iclass 21, count 0 2006.197.08:09:51.81#ibcon#about to write, iclass 21, count 0 2006.197.08:09:51.81#ibcon#wrote, iclass 21, count 0 2006.197.08:09:51.81#ibcon#about to read 3, iclass 21, count 0 2006.197.08:09:51.83#ibcon#read 3, iclass 21, count 0 2006.197.08:09:51.83#ibcon#about to read 4, iclass 21, count 0 2006.197.08:09:51.83#ibcon#read 4, iclass 21, count 0 2006.197.08:09:51.83#ibcon#about to read 5, iclass 21, count 0 2006.197.08:09:51.83#ibcon#read 5, iclass 21, count 0 2006.197.08:09:51.83#ibcon#about to read 6, iclass 21, count 0 2006.197.08:09:51.83#ibcon#read 6, iclass 21, count 0 2006.197.08:09:51.83#ibcon#end of sib2, iclass 21, count 0 2006.197.08:09:51.83#ibcon#*mode == 0, iclass 21, count 0 2006.197.08:09:51.83#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.197.08:09:51.83#ibcon#[28=FRQ=05,744.99\r\n] 2006.197.08:09:51.83#ibcon#*before write, iclass 21, count 0 2006.197.08:09:51.83#ibcon#enter sib2, iclass 21, count 0 2006.197.08:09:51.83#ibcon#flushed, iclass 21, count 0 2006.197.08:09:51.83#ibcon#about to write, iclass 21, count 0 2006.197.08:09:51.83#ibcon#wrote, iclass 21, count 0 2006.197.08:09:51.83#ibcon#about to read 3, iclass 21, count 0 2006.197.08:09:51.87#ibcon#read 3, iclass 21, count 0 2006.197.08:09:51.87#ibcon#about to read 4, iclass 21, count 0 2006.197.08:09:51.87#ibcon#read 4, iclass 21, count 0 2006.197.08:09:51.87#ibcon#about to read 5, iclass 21, count 0 2006.197.08:09:51.87#ibcon#read 5, iclass 21, count 0 2006.197.08:09:51.87#ibcon#about to read 6, iclass 21, count 0 2006.197.08:09:51.87#ibcon#read 6, iclass 21, count 0 2006.197.08:09:51.87#ibcon#end of sib2, iclass 21, count 0 2006.197.08:09:51.87#ibcon#*after write, iclass 21, count 0 2006.197.08:09:51.87#ibcon#*before return 0, iclass 21, count 0 2006.197.08:09:51.87#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.197.08:09:51.87#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.197.08:09:51.87#ibcon#about to clear, iclass 21 cls_cnt 0 2006.197.08:09:51.87#ibcon#cleared, iclass 21 cls_cnt 0 2006.197.08:09:51.87$vc4f8/vb=5,4 2006.197.08:09:51.87#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.197.08:09:51.87#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.197.08:09:51.87#ibcon#ireg 11 cls_cnt 2 2006.197.08:09:51.87#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.197.08:09:51.93#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.197.08:09:51.93#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.197.08:09:51.93#ibcon#enter wrdev, iclass 23, count 2 2006.197.08:09:51.93#ibcon#first serial, iclass 23, count 2 2006.197.08:09:51.93#ibcon#enter sib2, iclass 23, count 2 2006.197.08:09:51.93#ibcon#flushed, iclass 23, count 2 2006.197.08:09:51.93#ibcon#about to write, iclass 23, count 2 2006.197.08:09:51.93#ibcon#wrote, iclass 23, count 2 2006.197.08:09:51.93#ibcon#about to read 3, iclass 23, count 2 2006.197.08:09:51.95#ibcon#read 3, iclass 23, count 2 2006.197.08:09:51.95#ibcon#about to read 4, iclass 23, count 2 2006.197.08:09:51.95#ibcon#read 4, iclass 23, count 2 2006.197.08:09:51.95#ibcon#about to read 5, iclass 23, count 2 2006.197.08:09:51.95#ibcon#read 5, iclass 23, count 2 2006.197.08:09:51.95#ibcon#about to read 6, iclass 23, count 2 2006.197.08:09:51.95#ibcon#read 6, iclass 23, count 2 2006.197.08:09:51.95#ibcon#end of sib2, iclass 23, count 2 2006.197.08:09:51.95#ibcon#*mode == 0, iclass 23, count 2 2006.197.08:09:51.95#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.197.08:09:51.95#ibcon#[27=AT05-04\r\n] 2006.197.08:09:51.95#ibcon#*before write, iclass 23, count 2 2006.197.08:09:51.95#ibcon#enter sib2, iclass 23, count 2 2006.197.08:09:51.95#ibcon#flushed, iclass 23, count 2 2006.197.08:09:51.95#ibcon#about to write, iclass 23, count 2 2006.197.08:09:51.95#ibcon#wrote, iclass 23, count 2 2006.197.08:09:51.95#ibcon#about to read 3, iclass 23, count 2 2006.197.08:09:51.98#ibcon#read 3, iclass 23, count 2 2006.197.08:09:51.98#ibcon#about to read 4, iclass 23, count 2 2006.197.08:09:51.98#ibcon#read 4, iclass 23, count 2 2006.197.08:09:51.98#ibcon#about to read 5, iclass 23, count 2 2006.197.08:09:51.98#ibcon#read 5, iclass 23, count 2 2006.197.08:09:51.98#ibcon#about to read 6, iclass 23, count 2 2006.197.08:09:51.98#ibcon#read 6, iclass 23, count 2 2006.197.08:09:51.98#ibcon#end of sib2, iclass 23, count 2 2006.197.08:09:51.98#ibcon#*after write, iclass 23, count 2 2006.197.08:09:51.98#ibcon#*before return 0, iclass 23, count 2 2006.197.08:09:51.98#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.197.08:09:51.98#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.197.08:09:51.98#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.197.08:09:51.98#ibcon#ireg 7 cls_cnt 0 2006.197.08:09:51.98#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.197.08:09:52.10#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.197.08:09:52.10#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.197.08:09:52.10#ibcon#enter wrdev, iclass 23, count 0 2006.197.08:09:52.10#ibcon#first serial, iclass 23, count 0 2006.197.08:09:52.10#ibcon#enter sib2, iclass 23, count 0 2006.197.08:09:52.10#ibcon#flushed, iclass 23, count 0 2006.197.08:09:52.10#ibcon#about to write, iclass 23, count 0 2006.197.08:09:52.10#ibcon#wrote, iclass 23, count 0 2006.197.08:09:52.10#ibcon#about to read 3, iclass 23, count 0 2006.197.08:09:52.12#ibcon#read 3, iclass 23, count 0 2006.197.08:09:52.12#ibcon#about to read 4, iclass 23, count 0 2006.197.08:09:52.12#ibcon#read 4, iclass 23, count 0 2006.197.08:09:52.12#ibcon#about to read 5, iclass 23, count 0 2006.197.08:09:52.12#ibcon#read 5, iclass 23, count 0 2006.197.08:09:52.12#ibcon#about to read 6, iclass 23, count 0 2006.197.08:09:52.12#ibcon#read 6, iclass 23, count 0 2006.197.08:09:52.12#ibcon#end of sib2, iclass 23, count 0 2006.197.08:09:52.12#ibcon#*mode == 0, iclass 23, count 0 2006.197.08:09:52.12#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.197.08:09:52.12#ibcon#[27=USB\r\n] 2006.197.08:09:52.12#ibcon#*before write, iclass 23, count 0 2006.197.08:09:52.12#ibcon#enter sib2, iclass 23, count 0 2006.197.08:09:52.12#ibcon#flushed, iclass 23, count 0 2006.197.08:09:52.12#ibcon#about to write, iclass 23, count 0 2006.197.08:09:52.12#ibcon#wrote, iclass 23, count 0 2006.197.08:09:52.12#ibcon#about to read 3, iclass 23, count 0 2006.197.08:09:52.15#ibcon#read 3, iclass 23, count 0 2006.197.08:09:52.15#ibcon#about to read 4, iclass 23, count 0 2006.197.08:09:52.15#ibcon#read 4, iclass 23, count 0 2006.197.08:09:52.15#ibcon#about to read 5, iclass 23, count 0 2006.197.08:09:52.15#ibcon#read 5, iclass 23, count 0 2006.197.08:09:52.15#ibcon#about to read 6, iclass 23, count 0 2006.197.08:09:52.15#ibcon#read 6, iclass 23, count 0 2006.197.08:09:52.15#ibcon#end of sib2, iclass 23, count 0 2006.197.08:09:52.15#ibcon#*after write, iclass 23, count 0 2006.197.08:09:52.15#ibcon#*before return 0, iclass 23, count 0 2006.197.08:09:52.15#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.197.08:09:52.15#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.197.08:09:52.15#ibcon#about to clear, iclass 23 cls_cnt 0 2006.197.08:09:52.15#ibcon#cleared, iclass 23 cls_cnt 0 2006.197.08:09:52.15$vc4f8/vblo=6,752.99 2006.197.08:09:52.15#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.197.08:09:52.15#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.197.08:09:52.15#ibcon#ireg 17 cls_cnt 0 2006.197.08:09:52.15#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.197.08:09:52.15#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.197.08:09:52.15#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.197.08:09:52.15#ibcon#enter wrdev, iclass 25, count 0 2006.197.08:09:52.15#ibcon#first serial, iclass 25, count 0 2006.197.08:09:52.15#ibcon#enter sib2, iclass 25, count 0 2006.197.08:09:52.15#ibcon#flushed, iclass 25, count 0 2006.197.08:09:52.15#ibcon#about to write, iclass 25, count 0 2006.197.08:09:52.15#ibcon#wrote, iclass 25, count 0 2006.197.08:09:52.15#ibcon#about to read 3, iclass 25, count 0 2006.197.08:09:52.17#ibcon#read 3, iclass 25, count 0 2006.197.08:09:52.17#ibcon#about to read 4, iclass 25, count 0 2006.197.08:09:52.17#ibcon#read 4, iclass 25, count 0 2006.197.08:09:52.17#ibcon#about to read 5, iclass 25, count 0 2006.197.08:09:52.17#ibcon#read 5, iclass 25, count 0 2006.197.08:09:52.17#ibcon#about to read 6, iclass 25, count 0 2006.197.08:09:52.17#ibcon#read 6, iclass 25, count 0 2006.197.08:09:52.17#ibcon#end of sib2, iclass 25, count 0 2006.197.08:09:52.17#ibcon#*mode == 0, iclass 25, count 0 2006.197.08:09:52.17#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.197.08:09:52.17#ibcon#[28=FRQ=06,752.99\r\n] 2006.197.08:09:52.17#ibcon#*before write, iclass 25, count 0 2006.197.08:09:52.17#ibcon#enter sib2, iclass 25, count 0 2006.197.08:09:52.17#ibcon#flushed, iclass 25, count 0 2006.197.08:09:52.17#ibcon#about to write, iclass 25, count 0 2006.197.08:09:52.17#ibcon#wrote, iclass 25, count 0 2006.197.08:09:52.17#ibcon#about to read 3, iclass 25, count 0 2006.197.08:09:52.21#ibcon#read 3, iclass 25, count 0 2006.197.08:09:52.21#ibcon#about to read 4, iclass 25, count 0 2006.197.08:09:52.21#ibcon#read 4, iclass 25, count 0 2006.197.08:09:52.21#ibcon#about to read 5, iclass 25, count 0 2006.197.08:09:52.21#ibcon#read 5, iclass 25, count 0 2006.197.08:09:52.21#ibcon#about to read 6, iclass 25, count 0 2006.197.08:09:52.21#ibcon#read 6, iclass 25, count 0 2006.197.08:09:52.21#ibcon#end of sib2, iclass 25, count 0 2006.197.08:09:52.21#ibcon#*after write, iclass 25, count 0 2006.197.08:09:52.21#ibcon#*before return 0, iclass 25, count 0 2006.197.08:09:52.21#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.197.08:09:52.21#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.197.08:09:52.21#ibcon#about to clear, iclass 25 cls_cnt 0 2006.197.08:09:52.21#ibcon#cleared, iclass 25 cls_cnt 0 2006.197.08:09:52.21$vc4f8/vb=6,4 2006.197.08:09:52.21#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.197.08:09:52.21#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.197.08:09:52.21#ibcon#ireg 11 cls_cnt 2 2006.197.08:09:52.21#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.197.08:09:52.27#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.197.08:09:52.27#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.197.08:09:52.27#ibcon#enter wrdev, iclass 27, count 2 2006.197.08:09:52.27#ibcon#first serial, iclass 27, count 2 2006.197.08:09:52.27#ibcon#enter sib2, iclass 27, count 2 2006.197.08:09:52.27#ibcon#flushed, iclass 27, count 2 2006.197.08:09:52.27#ibcon#about to write, iclass 27, count 2 2006.197.08:09:52.27#ibcon#wrote, iclass 27, count 2 2006.197.08:09:52.27#ibcon#about to read 3, iclass 27, count 2 2006.197.08:09:52.29#ibcon#read 3, iclass 27, count 2 2006.197.08:09:52.29#ibcon#about to read 4, iclass 27, count 2 2006.197.08:09:52.29#ibcon#read 4, iclass 27, count 2 2006.197.08:09:52.29#ibcon#about to read 5, iclass 27, count 2 2006.197.08:09:52.29#ibcon#read 5, iclass 27, count 2 2006.197.08:09:52.29#ibcon#about to read 6, iclass 27, count 2 2006.197.08:09:52.29#ibcon#read 6, iclass 27, count 2 2006.197.08:09:52.29#ibcon#end of sib2, iclass 27, count 2 2006.197.08:09:52.29#ibcon#*mode == 0, iclass 27, count 2 2006.197.08:09:52.29#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.197.08:09:52.29#ibcon#[27=AT06-04\r\n] 2006.197.08:09:52.29#ibcon#*before write, iclass 27, count 2 2006.197.08:09:52.29#ibcon#enter sib2, iclass 27, count 2 2006.197.08:09:52.29#ibcon#flushed, iclass 27, count 2 2006.197.08:09:52.29#ibcon#about to write, iclass 27, count 2 2006.197.08:09:52.29#ibcon#wrote, iclass 27, count 2 2006.197.08:09:52.29#ibcon#about to read 3, iclass 27, count 2 2006.197.08:09:52.32#ibcon#read 3, iclass 27, count 2 2006.197.08:09:52.32#ibcon#about to read 4, iclass 27, count 2 2006.197.08:09:52.32#ibcon#read 4, iclass 27, count 2 2006.197.08:09:52.32#ibcon#about to read 5, iclass 27, count 2 2006.197.08:09:52.32#ibcon#read 5, iclass 27, count 2 2006.197.08:09:52.32#ibcon#about to read 6, iclass 27, count 2 2006.197.08:09:52.32#ibcon#read 6, iclass 27, count 2 2006.197.08:09:52.32#ibcon#end of sib2, iclass 27, count 2 2006.197.08:09:52.32#ibcon#*after write, iclass 27, count 2 2006.197.08:09:52.32#ibcon#*before return 0, iclass 27, count 2 2006.197.08:09:52.32#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.197.08:09:52.32#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.197.08:09:52.32#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.197.08:09:52.32#ibcon#ireg 7 cls_cnt 0 2006.197.08:09:52.32#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.197.08:09:52.44#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.197.08:09:52.44#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.197.08:09:52.44#ibcon#enter wrdev, iclass 27, count 0 2006.197.08:09:52.44#ibcon#first serial, iclass 27, count 0 2006.197.08:09:52.44#ibcon#enter sib2, iclass 27, count 0 2006.197.08:09:52.44#ibcon#flushed, iclass 27, count 0 2006.197.08:09:52.44#ibcon#about to write, iclass 27, count 0 2006.197.08:09:52.44#ibcon#wrote, iclass 27, count 0 2006.197.08:09:52.44#ibcon#about to read 3, iclass 27, count 0 2006.197.08:09:52.46#ibcon#read 3, iclass 27, count 0 2006.197.08:09:52.46#ibcon#about to read 4, iclass 27, count 0 2006.197.08:09:52.46#ibcon#read 4, iclass 27, count 0 2006.197.08:09:52.46#ibcon#about to read 5, iclass 27, count 0 2006.197.08:09:52.46#ibcon#read 5, iclass 27, count 0 2006.197.08:09:52.46#ibcon#about to read 6, iclass 27, count 0 2006.197.08:09:52.46#ibcon#read 6, iclass 27, count 0 2006.197.08:09:52.46#ibcon#end of sib2, iclass 27, count 0 2006.197.08:09:52.46#ibcon#*mode == 0, iclass 27, count 0 2006.197.08:09:52.46#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.197.08:09:52.46#ibcon#[27=USB\r\n] 2006.197.08:09:52.46#ibcon#*before write, iclass 27, count 0 2006.197.08:09:52.46#ibcon#enter sib2, iclass 27, count 0 2006.197.08:09:52.46#ibcon#flushed, iclass 27, count 0 2006.197.08:09:52.46#ibcon#about to write, iclass 27, count 0 2006.197.08:09:52.46#ibcon#wrote, iclass 27, count 0 2006.197.08:09:52.46#ibcon#about to read 3, iclass 27, count 0 2006.197.08:09:52.49#ibcon#read 3, iclass 27, count 0 2006.197.08:09:52.49#ibcon#about to read 4, iclass 27, count 0 2006.197.08:09:52.49#ibcon#read 4, iclass 27, count 0 2006.197.08:09:52.49#ibcon#about to read 5, iclass 27, count 0 2006.197.08:09:52.49#ibcon#read 5, iclass 27, count 0 2006.197.08:09:52.49#ibcon#about to read 6, iclass 27, count 0 2006.197.08:09:52.49#ibcon#read 6, iclass 27, count 0 2006.197.08:09:52.49#ibcon#end of sib2, iclass 27, count 0 2006.197.08:09:52.49#ibcon#*after write, iclass 27, count 0 2006.197.08:09:52.49#ibcon#*before return 0, iclass 27, count 0 2006.197.08:09:52.49#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.197.08:09:52.49#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.197.08:09:52.49#ibcon#about to clear, iclass 27 cls_cnt 0 2006.197.08:09:52.49#ibcon#cleared, iclass 27 cls_cnt 0 2006.197.08:09:52.49$vc4f8/vabw=wide 2006.197.08:09:52.49#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.197.08:09:52.49#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.197.08:09:52.49#ibcon#ireg 8 cls_cnt 0 2006.197.08:09:52.49#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.197.08:09:52.49#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.197.08:09:52.49#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.197.08:09:52.49#ibcon#enter wrdev, iclass 29, count 0 2006.197.08:09:52.49#ibcon#first serial, iclass 29, count 0 2006.197.08:09:52.49#ibcon#enter sib2, iclass 29, count 0 2006.197.08:09:52.49#ibcon#flushed, iclass 29, count 0 2006.197.08:09:52.49#ibcon#about to write, iclass 29, count 0 2006.197.08:09:52.49#ibcon#wrote, iclass 29, count 0 2006.197.08:09:52.49#ibcon#about to read 3, iclass 29, count 0 2006.197.08:09:52.51#ibcon#read 3, iclass 29, count 0 2006.197.08:09:52.51#ibcon#about to read 4, iclass 29, count 0 2006.197.08:09:52.51#ibcon#read 4, iclass 29, count 0 2006.197.08:09:52.51#ibcon#about to read 5, iclass 29, count 0 2006.197.08:09:52.51#ibcon#read 5, iclass 29, count 0 2006.197.08:09:52.51#ibcon#about to read 6, iclass 29, count 0 2006.197.08:09:52.51#ibcon#read 6, iclass 29, count 0 2006.197.08:09:52.51#ibcon#end of sib2, iclass 29, count 0 2006.197.08:09:52.51#ibcon#*mode == 0, iclass 29, count 0 2006.197.08:09:52.51#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.197.08:09:52.51#ibcon#[25=BW32\r\n] 2006.197.08:09:52.51#ibcon#*before write, iclass 29, count 0 2006.197.08:09:52.51#ibcon#enter sib2, iclass 29, count 0 2006.197.08:09:52.51#ibcon#flushed, iclass 29, count 0 2006.197.08:09:52.51#ibcon#about to write, iclass 29, count 0 2006.197.08:09:52.51#ibcon#wrote, iclass 29, count 0 2006.197.08:09:52.51#ibcon#about to read 3, iclass 29, count 0 2006.197.08:09:52.54#ibcon#read 3, iclass 29, count 0 2006.197.08:09:52.54#ibcon#about to read 4, iclass 29, count 0 2006.197.08:09:52.54#ibcon#read 4, iclass 29, count 0 2006.197.08:09:52.54#ibcon#about to read 5, iclass 29, count 0 2006.197.08:09:52.54#ibcon#read 5, iclass 29, count 0 2006.197.08:09:52.54#ibcon#about to read 6, iclass 29, count 0 2006.197.08:09:52.54#ibcon#read 6, iclass 29, count 0 2006.197.08:09:52.54#ibcon#end of sib2, iclass 29, count 0 2006.197.08:09:52.54#ibcon#*after write, iclass 29, count 0 2006.197.08:09:52.54#ibcon#*before return 0, iclass 29, count 0 2006.197.08:09:52.54#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.197.08:09:52.54#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.197.08:09:52.54#ibcon#about to clear, iclass 29 cls_cnt 0 2006.197.08:09:52.54#ibcon#cleared, iclass 29 cls_cnt 0 2006.197.08:09:52.54$vc4f8/vbbw=wide 2006.197.08:09:52.54#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.197.08:09:52.54#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.197.08:09:52.54#ibcon#ireg 8 cls_cnt 0 2006.197.08:09:52.54#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.197.08:09:52.61#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.197.08:09:52.61#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.197.08:09:52.61#ibcon#enter wrdev, iclass 31, count 0 2006.197.08:09:52.61#ibcon#first serial, iclass 31, count 0 2006.197.08:09:52.61#ibcon#enter sib2, iclass 31, count 0 2006.197.08:09:52.61#ibcon#flushed, iclass 31, count 0 2006.197.08:09:52.61#ibcon#about to write, iclass 31, count 0 2006.197.08:09:52.61#ibcon#wrote, iclass 31, count 0 2006.197.08:09:52.61#ibcon#about to read 3, iclass 31, count 0 2006.197.08:09:52.63#ibcon#read 3, iclass 31, count 0 2006.197.08:09:52.63#ibcon#about to read 4, iclass 31, count 0 2006.197.08:09:52.63#ibcon#read 4, iclass 31, count 0 2006.197.08:09:52.63#ibcon#about to read 5, iclass 31, count 0 2006.197.08:09:52.63#ibcon#read 5, iclass 31, count 0 2006.197.08:09:52.63#ibcon#about to read 6, iclass 31, count 0 2006.197.08:09:52.63#ibcon#read 6, iclass 31, count 0 2006.197.08:09:52.63#ibcon#end of sib2, iclass 31, count 0 2006.197.08:09:52.63#ibcon#*mode == 0, iclass 31, count 0 2006.197.08:09:52.63#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.197.08:09:52.63#ibcon#[27=BW32\r\n] 2006.197.08:09:52.63#ibcon#*before write, iclass 31, count 0 2006.197.08:09:52.63#ibcon#enter sib2, iclass 31, count 0 2006.197.08:09:52.63#ibcon#flushed, iclass 31, count 0 2006.197.08:09:52.63#ibcon#about to write, iclass 31, count 0 2006.197.08:09:52.63#ibcon#wrote, iclass 31, count 0 2006.197.08:09:52.63#ibcon#about to read 3, iclass 31, count 0 2006.197.08:09:52.66#ibcon#read 3, iclass 31, count 0 2006.197.08:09:52.66#ibcon#about to read 4, iclass 31, count 0 2006.197.08:09:52.66#ibcon#read 4, iclass 31, count 0 2006.197.08:09:52.66#ibcon#about to read 5, iclass 31, count 0 2006.197.08:09:52.66#ibcon#read 5, iclass 31, count 0 2006.197.08:09:52.66#ibcon#about to read 6, iclass 31, count 0 2006.197.08:09:52.66#ibcon#read 6, iclass 31, count 0 2006.197.08:09:52.66#ibcon#end of sib2, iclass 31, count 0 2006.197.08:09:52.66#ibcon#*after write, iclass 31, count 0 2006.197.08:09:52.66#ibcon#*before return 0, iclass 31, count 0 2006.197.08:09:52.66#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.197.08:09:52.66#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.197.08:09:52.66#ibcon#about to clear, iclass 31 cls_cnt 0 2006.197.08:09:52.66#ibcon#cleared, iclass 31 cls_cnt 0 2006.197.08:09:52.66$4f8m12a/ifd4f 2006.197.08:09:52.66$ifd4f/lo= 2006.197.08:09:52.66$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.197.08:09:52.66$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.197.08:09:52.66$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.197.08:09:52.66$ifd4f/patch= 2006.197.08:09:52.66$ifd4f/patch=lo1,a1,a2,a3,a4 2006.197.08:09:52.66$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.197.08:09:52.66$ifd4f/patch=lo3,a5,a6,a7,a8 2006.197.08:09:52.66$4f8m12a/"form=m,16.000,1:2 2006.197.08:09:52.66$4f8m12a/"tpicd 2006.197.08:09:52.66$4f8m12a/echo=off 2006.197.08:09:52.66$4f8m12a/xlog=off 2006.197.08:09:52.66:!2006.197.08:10:20 2006.197.08:09:58.14#trakl#Source acquired 2006.197.08:09:59.14#flagr#flagr/antenna,acquired 2006.197.08:10:20.00:preob 2006.197.08:10:21.14/onsource/TRACKING 2006.197.08:10:21.14:!2006.197.08:10:30 2006.197.08:10:30.00:data_valid=on 2006.197.08:10:30.00:midob 2006.197.08:10:30.14/onsource/TRACKING 2006.197.08:10:30.14/wx/25.64,1002.8,96 2006.197.08:10:30.30/cable/+6.3725E-03 2006.197.08:10:31.39/va/01,08,usb,yes,45,47 2006.197.08:10:31.39/va/02,07,usb,yes,46,47 2006.197.08:10:31.39/va/03,06,usb,yes,48,48 2006.197.08:10:31.39/va/04,07,usb,yes,46,50 2006.197.08:10:31.39/va/05,07,usb,yes,52,55 2006.197.08:10:31.39/va/06,06,usb,yes,51,51 2006.197.08:10:31.39/va/07,06,usb,yes,52,52 2006.197.08:10:31.39/va/08,07,usb,yes,49,49 2006.197.08:10:31.62/valo/01,532.99,yes,locked 2006.197.08:10:31.62/valo/02,572.99,yes,locked 2006.197.08:10:31.62/valo/03,672.99,yes,locked 2006.197.08:10:31.62/valo/04,832.99,yes,locked 2006.197.08:10:31.62/valo/05,652.99,yes,locked 2006.197.08:10:31.62/valo/06,772.99,yes,locked 2006.197.08:10:31.62/valo/07,832.99,yes,locked 2006.197.08:10:31.62/valo/08,852.99,yes,locked 2006.197.08:10:32.71/vb/01,04,usb,yes,40,37 2006.197.08:10:32.71/vb/02,04,usb,yes,42,43 2006.197.08:10:32.71/vb/03,04,usb,yes,37,42 2006.197.08:10:32.71/vb/04,04,usb,yes,38,39 2006.197.08:10:32.71/vb/05,04,usb,yes,36,41 2006.197.08:10:32.71/vb/06,04,usb,yes,37,41 2006.197.08:10:32.71/vb/07,04,usb,yes,40,40 2006.197.08:10:32.71/vb/08,04,usb,yes,37,41 2006.197.08:10:32.94/vblo/01,632.99,yes,locked 2006.197.08:10:32.94/vblo/02,640.99,yes,locked 2006.197.08:10:32.94/vblo/03,656.99,yes,locked 2006.197.08:10:32.94/vblo/04,712.99,yes,locked 2006.197.08:10:32.94/vblo/05,744.99,yes,locked 2006.197.08:10:32.94/vblo/06,752.99,yes,locked 2006.197.08:10:32.94/vblo/07,734.99,yes,locked 2006.197.08:10:32.94/vblo/08,744.99,yes,locked 2006.197.08:10:33.09/vabw/8 2006.197.08:10:33.24/vbbw/8 2006.197.08:10:33.33/xfe/off,on,15.5 2006.197.08:10:33.72/ifatt/23,28,28,28 2006.197.08:10:34.09/fmout-gps/S +3.00E-07 2006.197.08:10:34.12:!2006.197.08:11:30 2006.197.08:11:30.00:data_valid=off 2006.197.08:11:30.00:postob 2006.197.08:11:30.06/cable/+6.3713E-03 2006.197.08:11:30.06/wx/25.63,1002.8,96 2006.197.08:11:31.10/fmout-gps/S +3.00E-07 2006.197.08:11:31.10:scan_name=197-0812,k06197,60 2006.197.08:11:31.10:source=0749+540,075301.38,535300.0,2000.0,ccw 2006.197.08:11:31.13#flagr#flagr/antenna,new-source 2006.197.08:11:32.13:checkk5 2006.197.08:11:32.47/chk_autoobs//k5ts1/ autoobs is running! 2006.197.08:11:32.81/chk_autoobs//k5ts2/ autoobs is running! 2006.197.08:11:33.68/chk_autoobs//k5ts3/ autoobs is running! 2006.197.08:11:34.02/chk_autoobs//k5ts4/ autoobs is running! 2006.197.08:11:34.35/chk_obsdata//k5ts1/T1970810??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.197.08:11:34.69/chk_obsdata//k5ts2/T1970810??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.197.08:11:35.02/chk_obsdata//k5ts3/T1970810??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.197.08:11:35.36/chk_obsdata//k5ts4/T1970810??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.197.08:11:36.02/k5log//k5ts1_log_newline 2006.197.08:11:36.67/k5log//k5ts2_log_newline 2006.197.08:11:37.33/k5log//k5ts3_log_newline 2006.197.08:11:37.99/k5log//k5ts4_log_newline 2006.197.08:11:38.02/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.197.08:11:38.02:4f8m12a=2 2006.197.08:11:38.02$4f8m12a/echo=on 2006.197.08:11:38.02$4f8m12a/pcalon 2006.197.08:11:38.02$pcalon/"no phase cal control is implemented here 2006.197.08:11:38.02$4f8m12a/"tpicd=stop 2006.197.08:11:38.02$4f8m12a/vc4f8 2006.197.08:11:38.02$vc4f8/valo=1,532.99 2006.197.08:11:38.02#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.197.08:11:38.02#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.197.08:11:38.02#ibcon#ireg 17 cls_cnt 0 2006.197.08:11:38.02#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.197.08:11:38.02#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.197.08:11:38.02#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.197.08:11:38.02#ibcon#enter wrdev, iclass 38, count 0 2006.197.08:11:38.02#ibcon#first serial, iclass 38, count 0 2006.197.08:11:38.02#ibcon#enter sib2, iclass 38, count 0 2006.197.08:11:38.02#ibcon#flushed, iclass 38, count 0 2006.197.08:11:38.02#ibcon#about to write, iclass 38, count 0 2006.197.08:11:38.02#ibcon#wrote, iclass 38, count 0 2006.197.08:11:38.03#ibcon#about to read 3, iclass 38, count 0 2006.197.08:11:38.05#ibcon#read 3, iclass 38, count 0 2006.197.08:11:38.05#ibcon#about to read 4, iclass 38, count 0 2006.197.08:11:38.05#ibcon#read 4, iclass 38, count 0 2006.197.08:11:38.05#ibcon#about to read 5, iclass 38, count 0 2006.197.08:11:38.05#ibcon#read 5, iclass 38, count 0 2006.197.08:11:38.05#ibcon#about to read 6, iclass 38, count 0 2006.197.08:11:38.05#ibcon#read 6, iclass 38, count 0 2006.197.08:11:38.05#ibcon#end of sib2, iclass 38, count 0 2006.197.08:11:38.05#ibcon#*mode == 0, iclass 38, count 0 2006.197.08:11:38.05#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.197.08:11:38.05#ibcon#[26=FRQ=01,532.99\r\n] 2006.197.08:11:38.05#ibcon#*before write, iclass 38, count 0 2006.197.08:11:38.05#ibcon#enter sib2, iclass 38, count 0 2006.197.08:11:38.05#ibcon#flushed, iclass 38, count 0 2006.197.08:11:38.05#ibcon#about to write, iclass 38, count 0 2006.197.08:11:38.05#ibcon#wrote, iclass 38, count 0 2006.197.08:11:38.05#ibcon#about to read 3, iclass 38, count 0 2006.197.08:11:38.10#ibcon#read 3, iclass 38, count 0 2006.197.08:11:38.10#ibcon#about to read 4, iclass 38, count 0 2006.197.08:11:38.10#ibcon#read 4, iclass 38, count 0 2006.197.08:11:38.10#ibcon#about to read 5, iclass 38, count 0 2006.197.08:11:38.10#ibcon#read 5, iclass 38, count 0 2006.197.08:11:38.10#ibcon#about to read 6, iclass 38, count 0 2006.197.08:11:38.10#ibcon#read 6, iclass 38, count 0 2006.197.08:11:38.10#ibcon#end of sib2, iclass 38, count 0 2006.197.08:11:38.10#ibcon#*after write, iclass 38, count 0 2006.197.08:11:38.10#ibcon#*before return 0, iclass 38, count 0 2006.197.08:11:38.10#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.197.08:11:38.10#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.197.08:11:38.10#ibcon#about to clear, iclass 38 cls_cnt 0 2006.197.08:11:38.10#ibcon#cleared, iclass 38 cls_cnt 0 2006.197.08:11:38.10$vc4f8/va=1,8 2006.197.08:11:38.10#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.197.08:11:38.10#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.197.08:11:38.10#ibcon#ireg 11 cls_cnt 2 2006.197.08:11:38.10#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.197.08:11:38.10#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.197.08:11:38.10#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.197.08:11:38.10#ibcon#enter wrdev, iclass 40, count 2 2006.197.08:11:38.10#ibcon#first serial, iclass 40, count 2 2006.197.08:11:38.10#ibcon#enter sib2, iclass 40, count 2 2006.197.08:11:38.10#ibcon#flushed, iclass 40, count 2 2006.197.08:11:38.10#ibcon#about to write, iclass 40, count 2 2006.197.08:11:38.10#ibcon#wrote, iclass 40, count 2 2006.197.08:11:38.10#ibcon#about to read 3, iclass 40, count 2 2006.197.08:11:38.12#ibcon#read 3, iclass 40, count 2 2006.197.08:11:38.12#ibcon#about to read 4, iclass 40, count 2 2006.197.08:11:38.12#ibcon#read 4, iclass 40, count 2 2006.197.08:11:38.12#ibcon#about to read 5, iclass 40, count 2 2006.197.08:11:38.12#ibcon#read 5, iclass 40, count 2 2006.197.08:11:38.12#ibcon#about to read 6, iclass 40, count 2 2006.197.08:11:38.12#ibcon#read 6, iclass 40, count 2 2006.197.08:11:38.12#ibcon#end of sib2, iclass 40, count 2 2006.197.08:11:38.12#ibcon#*mode == 0, iclass 40, count 2 2006.197.08:11:38.12#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.197.08:11:38.12#ibcon#[25=AT01-08\r\n] 2006.197.08:11:38.12#ibcon#*before write, iclass 40, count 2 2006.197.08:11:38.12#ibcon#enter sib2, iclass 40, count 2 2006.197.08:11:38.12#ibcon#flushed, iclass 40, count 2 2006.197.08:11:38.12#ibcon#about to write, iclass 40, count 2 2006.197.08:11:38.12#ibcon#wrote, iclass 40, count 2 2006.197.08:11:38.12#ibcon#about to read 3, iclass 40, count 2 2006.197.08:11:38.15#ibcon#read 3, iclass 40, count 2 2006.197.08:11:38.15#ibcon#about to read 4, iclass 40, count 2 2006.197.08:11:38.15#ibcon#read 4, iclass 40, count 2 2006.197.08:11:38.15#ibcon#about to read 5, iclass 40, count 2 2006.197.08:11:38.15#ibcon#read 5, iclass 40, count 2 2006.197.08:11:38.15#ibcon#about to read 6, iclass 40, count 2 2006.197.08:11:38.15#ibcon#read 6, iclass 40, count 2 2006.197.08:11:38.15#ibcon#end of sib2, iclass 40, count 2 2006.197.08:11:38.15#ibcon#*after write, iclass 40, count 2 2006.197.08:11:38.15#ibcon#*before return 0, iclass 40, count 2 2006.197.08:11:38.15#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.197.08:11:38.15#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.197.08:11:38.15#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.197.08:11:38.15#ibcon#ireg 7 cls_cnt 0 2006.197.08:11:38.15#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.197.08:11:38.27#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.197.08:11:38.27#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.197.08:11:38.27#ibcon#enter wrdev, iclass 40, count 0 2006.197.08:11:38.27#ibcon#first serial, iclass 40, count 0 2006.197.08:11:38.27#ibcon#enter sib2, iclass 40, count 0 2006.197.08:11:38.27#ibcon#flushed, iclass 40, count 0 2006.197.08:11:38.27#ibcon#about to write, iclass 40, count 0 2006.197.08:11:38.27#ibcon#wrote, iclass 40, count 0 2006.197.08:11:38.27#ibcon#about to read 3, iclass 40, count 0 2006.197.08:11:38.29#ibcon#read 3, iclass 40, count 0 2006.197.08:11:38.29#ibcon#about to read 4, iclass 40, count 0 2006.197.08:11:38.29#ibcon#read 4, iclass 40, count 0 2006.197.08:11:38.29#ibcon#about to read 5, iclass 40, count 0 2006.197.08:11:38.29#ibcon#read 5, iclass 40, count 0 2006.197.08:11:38.29#ibcon#about to read 6, iclass 40, count 0 2006.197.08:11:38.29#ibcon#read 6, iclass 40, count 0 2006.197.08:11:38.29#ibcon#end of sib2, iclass 40, count 0 2006.197.08:11:38.29#ibcon#*mode == 0, iclass 40, count 0 2006.197.08:11:38.29#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.197.08:11:38.29#ibcon#[25=USB\r\n] 2006.197.08:11:38.29#ibcon#*before write, iclass 40, count 0 2006.197.08:11:38.29#ibcon#enter sib2, iclass 40, count 0 2006.197.08:11:38.29#ibcon#flushed, iclass 40, count 0 2006.197.08:11:38.29#ibcon#about to write, iclass 40, count 0 2006.197.08:11:38.29#ibcon#wrote, iclass 40, count 0 2006.197.08:11:38.29#ibcon#about to read 3, iclass 40, count 0 2006.197.08:11:38.32#ibcon#read 3, iclass 40, count 0 2006.197.08:11:38.32#ibcon#about to read 4, iclass 40, count 0 2006.197.08:11:38.32#ibcon#read 4, iclass 40, count 0 2006.197.08:11:38.32#ibcon#about to read 5, iclass 40, count 0 2006.197.08:11:38.32#ibcon#read 5, iclass 40, count 0 2006.197.08:11:38.32#ibcon#about to read 6, iclass 40, count 0 2006.197.08:11:38.32#ibcon#read 6, iclass 40, count 0 2006.197.08:11:38.32#ibcon#end of sib2, iclass 40, count 0 2006.197.08:11:38.32#ibcon#*after write, iclass 40, count 0 2006.197.08:11:38.32#ibcon#*before return 0, iclass 40, count 0 2006.197.08:11:38.32#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.197.08:11:38.32#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.197.08:11:38.32#ibcon#about to clear, iclass 40 cls_cnt 0 2006.197.08:11:38.32#ibcon#cleared, iclass 40 cls_cnt 0 2006.197.08:11:38.32$vc4f8/valo=2,572.99 2006.197.08:11:38.32#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.197.08:11:38.32#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.197.08:11:38.32#ibcon#ireg 17 cls_cnt 0 2006.197.08:11:38.32#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.197.08:11:38.32#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.197.08:11:38.32#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.197.08:11:38.32#ibcon#enter wrdev, iclass 4, count 0 2006.197.08:11:38.32#ibcon#first serial, iclass 4, count 0 2006.197.08:11:38.32#ibcon#enter sib2, iclass 4, count 0 2006.197.08:11:38.32#ibcon#flushed, iclass 4, count 0 2006.197.08:11:38.32#ibcon#about to write, iclass 4, count 0 2006.197.08:11:38.32#ibcon#wrote, iclass 4, count 0 2006.197.08:11:38.32#ibcon#about to read 3, iclass 4, count 0 2006.197.08:11:38.34#ibcon#read 3, iclass 4, count 0 2006.197.08:11:38.34#ibcon#about to read 4, iclass 4, count 0 2006.197.08:11:38.34#ibcon#read 4, iclass 4, count 0 2006.197.08:11:38.34#ibcon#about to read 5, iclass 4, count 0 2006.197.08:11:38.34#ibcon#read 5, iclass 4, count 0 2006.197.08:11:38.34#ibcon#about to read 6, iclass 4, count 0 2006.197.08:11:38.34#ibcon#read 6, iclass 4, count 0 2006.197.08:11:38.34#ibcon#end of sib2, iclass 4, count 0 2006.197.08:11:38.34#ibcon#*mode == 0, iclass 4, count 0 2006.197.08:11:38.34#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.197.08:11:38.34#ibcon#[26=FRQ=02,572.99\r\n] 2006.197.08:11:38.34#ibcon#*before write, iclass 4, count 0 2006.197.08:11:38.34#ibcon#enter sib2, iclass 4, count 0 2006.197.08:11:38.34#ibcon#flushed, iclass 4, count 0 2006.197.08:11:38.34#ibcon#about to write, iclass 4, count 0 2006.197.08:11:38.34#ibcon#wrote, iclass 4, count 0 2006.197.08:11:38.34#ibcon#about to read 3, iclass 4, count 0 2006.197.08:11:38.38#ibcon#read 3, iclass 4, count 0 2006.197.08:11:38.38#ibcon#about to read 4, iclass 4, count 0 2006.197.08:11:38.38#ibcon#read 4, iclass 4, count 0 2006.197.08:11:38.38#ibcon#about to read 5, iclass 4, count 0 2006.197.08:11:38.38#ibcon#read 5, iclass 4, count 0 2006.197.08:11:38.38#ibcon#about to read 6, iclass 4, count 0 2006.197.08:11:38.38#ibcon#read 6, iclass 4, count 0 2006.197.08:11:38.38#ibcon#end of sib2, iclass 4, count 0 2006.197.08:11:38.38#ibcon#*after write, iclass 4, count 0 2006.197.08:11:38.38#ibcon#*before return 0, iclass 4, count 0 2006.197.08:11:38.38#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.197.08:11:38.38#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.197.08:11:38.38#ibcon#about to clear, iclass 4 cls_cnt 0 2006.197.08:11:38.38#ibcon#cleared, iclass 4 cls_cnt 0 2006.197.08:11:38.38$vc4f8/va=2,7 2006.197.08:11:38.38#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.197.08:11:38.38#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.197.08:11:38.38#ibcon#ireg 11 cls_cnt 2 2006.197.08:11:38.38#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.197.08:11:38.44#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.197.08:11:38.44#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.197.08:11:38.44#ibcon#enter wrdev, iclass 6, count 2 2006.197.08:11:38.44#ibcon#first serial, iclass 6, count 2 2006.197.08:11:38.44#ibcon#enter sib2, iclass 6, count 2 2006.197.08:11:38.44#ibcon#flushed, iclass 6, count 2 2006.197.08:11:38.44#ibcon#about to write, iclass 6, count 2 2006.197.08:11:38.44#ibcon#wrote, iclass 6, count 2 2006.197.08:11:38.44#ibcon#about to read 3, iclass 6, count 2 2006.197.08:11:38.46#ibcon#read 3, iclass 6, count 2 2006.197.08:11:38.46#ibcon#about to read 4, iclass 6, count 2 2006.197.08:11:38.46#ibcon#read 4, iclass 6, count 2 2006.197.08:11:38.46#ibcon#about to read 5, iclass 6, count 2 2006.197.08:11:38.46#ibcon#read 5, iclass 6, count 2 2006.197.08:11:38.46#ibcon#about to read 6, iclass 6, count 2 2006.197.08:11:38.46#ibcon#read 6, iclass 6, count 2 2006.197.08:11:38.46#ibcon#end of sib2, iclass 6, count 2 2006.197.08:11:38.46#ibcon#*mode == 0, iclass 6, count 2 2006.197.08:11:38.46#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.197.08:11:38.46#ibcon#[25=AT02-07\r\n] 2006.197.08:11:38.46#ibcon#*before write, iclass 6, count 2 2006.197.08:11:38.46#ibcon#enter sib2, iclass 6, count 2 2006.197.08:11:38.46#ibcon#flushed, iclass 6, count 2 2006.197.08:11:38.46#ibcon#about to write, iclass 6, count 2 2006.197.08:11:38.46#ibcon#wrote, iclass 6, count 2 2006.197.08:11:38.46#ibcon#about to read 3, iclass 6, count 2 2006.197.08:11:38.49#ibcon#read 3, iclass 6, count 2 2006.197.08:11:38.49#ibcon#about to read 4, iclass 6, count 2 2006.197.08:11:38.49#ibcon#read 4, iclass 6, count 2 2006.197.08:11:38.49#ibcon#about to read 5, iclass 6, count 2 2006.197.08:11:38.49#ibcon#read 5, iclass 6, count 2 2006.197.08:11:38.49#ibcon#about to read 6, iclass 6, count 2 2006.197.08:11:38.49#ibcon#read 6, iclass 6, count 2 2006.197.08:11:38.49#ibcon#end of sib2, iclass 6, count 2 2006.197.08:11:38.49#ibcon#*after write, iclass 6, count 2 2006.197.08:11:38.49#ibcon#*before return 0, iclass 6, count 2 2006.197.08:11:38.49#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.197.08:11:38.49#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.197.08:11:38.49#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.197.08:11:38.49#ibcon#ireg 7 cls_cnt 0 2006.197.08:11:38.49#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.197.08:11:38.61#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.197.08:11:38.61#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.197.08:11:38.61#ibcon#enter wrdev, iclass 6, count 0 2006.197.08:11:38.61#ibcon#first serial, iclass 6, count 0 2006.197.08:11:38.61#ibcon#enter sib2, iclass 6, count 0 2006.197.08:11:38.61#ibcon#flushed, iclass 6, count 0 2006.197.08:11:38.61#ibcon#about to write, iclass 6, count 0 2006.197.08:11:38.61#ibcon#wrote, iclass 6, count 0 2006.197.08:11:38.61#ibcon#about to read 3, iclass 6, count 0 2006.197.08:11:38.63#ibcon#read 3, iclass 6, count 0 2006.197.08:11:38.63#ibcon#about to read 4, iclass 6, count 0 2006.197.08:11:38.63#ibcon#read 4, iclass 6, count 0 2006.197.08:11:38.63#ibcon#about to read 5, iclass 6, count 0 2006.197.08:11:38.63#ibcon#read 5, iclass 6, count 0 2006.197.08:11:38.63#ibcon#about to read 6, iclass 6, count 0 2006.197.08:11:38.63#ibcon#read 6, iclass 6, count 0 2006.197.08:11:38.63#ibcon#end of sib2, iclass 6, count 0 2006.197.08:11:38.63#ibcon#*mode == 0, iclass 6, count 0 2006.197.08:11:38.63#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.197.08:11:38.63#ibcon#[25=USB\r\n] 2006.197.08:11:38.63#ibcon#*before write, iclass 6, count 0 2006.197.08:11:38.63#ibcon#enter sib2, iclass 6, count 0 2006.197.08:11:38.63#ibcon#flushed, iclass 6, count 0 2006.197.08:11:38.63#ibcon#about to write, iclass 6, count 0 2006.197.08:11:38.63#ibcon#wrote, iclass 6, count 0 2006.197.08:11:38.63#ibcon#about to read 3, iclass 6, count 0 2006.197.08:11:38.66#ibcon#read 3, iclass 6, count 0 2006.197.08:11:38.66#ibcon#about to read 4, iclass 6, count 0 2006.197.08:11:38.66#ibcon#read 4, iclass 6, count 0 2006.197.08:11:38.66#ibcon#about to read 5, iclass 6, count 0 2006.197.08:11:38.66#ibcon#read 5, iclass 6, count 0 2006.197.08:11:38.66#ibcon#about to read 6, iclass 6, count 0 2006.197.08:11:38.66#ibcon#read 6, iclass 6, count 0 2006.197.08:11:38.66#ibcon#end of sib2, iclass 6, count 0 2006.197.08:11:38.66#ibcon#*after write, iclass 6, count 0 2006.197.08:11:38.66#ibcon#*before return 0, iclass 6, count 0 2006.197.08:11:38.66#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.197.08:11:38.66#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.197.08:11:38.66#ibcon#about to clear, iclass 6 cls_cnt 0 2006.197.08:11:38.66#ibcon#cleared, iclass 6 cls_cnt 0 2006.197.08:11:38.66$vc4f8/valo=3,672.99 2006.197.08:11:38.66#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.197.08:11:38.66#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.197.08:11:38.66#ibcon#ireg 17 cls_cnt 0 2006.197.08:11:38.66#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.197.08:11:38.66#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.197.08:11:38.66#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.197.08:11:38.66#ibcon#enter wrdev, iclass 10, count 0 2006.197.08:11:38.66#ibcon#first serial, iclass 10, count 0 2006.197.08:11:38.66#ibcon#enter sib2, iclass 10, count 0 2006.197.08:11:38.66#ibcon#flushed, iclass 10, count 0 2006.197.08:11:38.66#ibcon#about to write, iclass 10, count 0 2006.197.08:11:38.66#ibcon#wrote, iclass 10, count 0 2006.197.08:11:38.66#ibcon#about to read 3, iclass 10, count 0 2006.197.08:11:38.68#ibcon#read 3, iclass 10, count 0 2006.197.08:11:38.68#ibcon#about to read 4, iclass 10, count 0 2006.197.08:11:38.68#ibcon#read 4, iclass 10, count 0 2006.197.08:11:38.68#ibcon#about to read 5, iclass 10, count 0 2006.197.08:11:38.68#ibcon#read 5, iclass 10, count 0 2006.197.08:11:38.68#ibcon#about to read 6, iclass 10, count 0 2006.197.08:11:38.68#ibcon#read 6, iclass 10, count 0 2006.197.08:11:38.68#ibcon#end of sib2, iclass 10, count 0 2006.197.08:11:38.68#ibcon#*mode == 0, iclass 10, count 0 2006.197.08:11:38.68#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.197.08:11:38.68#ibcon#[26=FRQ=03,672.99\r\n] 2006.197.08:11:38.68#ibcon#*before write, iclass 10, count 0 2006.197.08:11:38.68#ibcon#enter sib2, iclass 10, count 0 2006.197.08:11:38.68#ibcon#flushed, iclass 10, count 0 2006.197.08:11:38.68#ibcon#about to write, iclass 10, count 0 2006.197.08:11:38.68#ibcon#wrote, iclass 10, count 0 2006.197.08:11:38.68#ibcon#about to read 3, iclass 10, count 0 2006.197.08:11:38.72#ibcon#read 3, iclass 10, count 0 2006.197.08:11:38.72#ibcon#about to read 4, iclass 10, count 0 2006.197.08:11:38.72#ibcon#read 4, iclass 10, count 0 2006.197.08:11:38.72#ibcon#about to read 5, iclass 10, count 0 2006.197.08:11:38.72#ibcon#read 5, iclass 10, count 0 2006.197.08:11:38.72#ibcon#about to read 6, iclass 10, count 0 2006.197.08:11:38.72#ibcon#read 6, iclass 10, count 0 2006.197.08:11:38.72#ibcon#end of sib2, iclass 10, count 0 2006.197.08:11:38.72#ibcon#*after write, iclass 10, count 0 2006.197.08:11:38.72#ibcon#*before return 0, iclass 10, count 0 2006.197.08:11:38.72#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.197.08:11:38.72#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.197.08:11:38.72#ibcon#about to clear, iclass 10 cls_cnt 0 2006.197.08:11:38.72#ibcon#cleared, iclass 10 cls_cnt 0 2006.197.08:11:38.72$vc4f8/va=3,6 2006.197.08:11:38.72#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.197.08:11:38.72#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.197.08:11:38.72#ibcon#ireg 11 cls_cnt 2 2006.197.08:11:38.72#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.197.08:11:38.78#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.197.08:11:38.78#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.197.08:11:38.78#ibcon#enter wrdev, iclass 12, count 2 2006.197.08:11:38.78#ibcon#first serial, iclass 12, count 2 2006.197.08:11:38.78#ibcon#enter sib2, iclass 12, count 2 2006.197.08:11:38.78#ibcon#flushed, iclass 12, count 2 2006.197.08:11:38.78#ibcon#about to write, iclass 12, count 2 2006.197.08:11:38.78#ibcon#wrote, iclass 12, count 2 2006.197.08:11:38.78#ibcon#about to read 3, iclass 12, count 2 2006.197.08:11:38.80#ibcon#read 3, iclass 12, count 2 2006.197.08:11:38.80#ibcon#about to read 4, iclass 12, count 2 2006.197.08:11:38.80#ibcon#read 4, iclass 12, count 2 2006.197.08:11:38.80#ibcon#about to read 5, iclass 12, count 2 2006.197.08:11:38.80#ibcon#read 5, iclass 12, count 2 2006.197.08:11:38.80#ibcon#about to read 6, iclass 12, count 2 2006.197.08:11:38.80#ibcon#read 6, iclass 12, count 2 2006.197.08:11:38.80#ibcon#end of sib2, iclass 12, count 2 2006.197.08:11:38.80#ibcon#*mode == 0, iclass 12, count 2 2006.197.08:11:38.80#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.197.08:11:38.80#ibcon#[25=AT03-06\r\n] 2006.197.08:11:38.80#ibcon#*before write, iclass 12, count 2 2006.197.08:11:38.80#ibcon#enter sib2, iclass 12, count 2 2006.197.08:11:38.80#ibcon#flushed, iclass 12, count 2 2006.197.08:11:38.80#ibcon#about to write, iclass 12, count 2 2006.197.08:11:38.80#ibcon#wrote, iclass 12, count 2 2006.197.08:11:38.80#ibcon#about to read 3, iclass 12, count 2 2006.197.08:11:38.83#ibcon#read 3, iclass 12, count 2 2006.197.08:11:38.83#ibcon#about to read 4, iclass 12, count 2 2006.197.08:11:38.83#ibcon#read 4, iclass 12, count 2 2006.197.08:11:38.83#ibcon#about to read 5, iclass 12, count 2 2006.197.08:11:38.83#ibcon#read 5, iclass 12, count 2 2006.197.08:11:38.83#ibcon#about to read 6, iclass 12, count 2 2006.197.08:11:38.83#ibcon#read 6, iclass 12, count 2 2006.197.08:11:38.83#ibcon#end of sib2, iclass 12, count 2 2006.197.08:11:38.83#ibcon#*after write, iclass 12, count 2 2006.197.08:11:38.83#ibcon#*before return 0, iclass 12, count 2 2006.197.08:11:38.83#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.197.08:11:38.83#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.197.08:11:38.83#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.197.08:11:38.83#ibcon#ireg 7 cls_cnt 0 2006.197.08:11:38.83#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.197.08:11:38.95#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.197.08:11:38.95#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.197.08:11:38.95#ibcon#enter wrdev, iclass 12, count 0 2006.197.08:11:38.95#ibcon#first serial, iclass 12, count 0 2006.197.08:11:38.95#ibcon#enter sib2, iclass 12, count 0 2006.197.08:11:38.95#ibcon#flushed, iclass 12, count 0 2006.197.08:11:38.95#ibcon#about to write, iclass 12, count 0 2006.197.08:11:38.95#ibcon#wrote, iclass 12, count 0 2006.197.08:11:38.95#ibcon#about to read 3, iclass 12, count 0 2006.197.08:11:38.97#ibcon#read 3, iclass 12, count 0 2006.197.08:11:38.97#ibcon#about to read 4, iclass 12, count 0 2006.197.08:11:38.97#ibcon#read 4, iclass 12, count 0 2006.197.08:11:38.97#ibcon#about to read 5, iclass 12, count 0 2006.197.08:11:38.97#ibcon#read 5, iclass 12, count 0 2006.197.08:11:38.97#ibcon#about to read 6, iclass 12, count 0 2006.197.08:11:38.97#ibcon#read 6, iclass 12, count 0 2006.197.08:11:38.97#ibcon#end of sib2, iclass 12, count 0 2006.197.08:11:38.97#ibcon#*mode == 0, iclass 12, count 0 2006.197.08:11:38.97#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.197.08:11:38.97#ibcon#[25=USB\r\n] 2006.197.08:11:38.97#ibcon#*before write, iclass 12, count 0 2006.197.08:11:38.97#ibcon#enter sib2, iclass 12, count 0 2006.197.08:11:38.97#ibcon#flushed, iclass 12, count 0 2006.197.08:11:38.97#ibcon#about to write, iclass 12, count 0 2006.197.08:11:38.97#ibcon#wrote, iclass 12, count 0 2006.197.08:11:38.97#ibcon#about to read 3, iclass 12, count 0 2006.197.08:11:39.00#ibcon#read 3, iclass 12, count 0 2006.197.08:11:39.00#ibcon#about to read 4, iclass 12, count 0 2006.197.08:11:39.00#ibcon#read 4, iclass 12, count 0 2006.197.08:11:39.00#ibcon#about to read 5, iclass 12, count 0 2006.197.08:11:39.00#ibcon#read 5, iclass 12, count 0 2006.197.08:11:39.00#ibcon#about to read 6, iclass 12, count 0 2006.197.08:11:39.00#ibcon#read 6, iclass 12, count 0 2006.197.08:11:39.00#ibcon#end of sib2, iclass 12, count 0 2006.197.08:11:39.00#ibcon#*after write, iclass 12, count 0 2006.197.08:11:39.00#ibcon#*before return 0, iclass 12, count 0 2006.197.08:11:39.00#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.197.08:11:39.00#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.197.08:11:39.00#ibcon#about to clear, iclass 12 cls_cnt 0 2006.197.08:11:39.00#ibcon#cleared, iclass 12 cls_cnt 0 2006.197.08:11:39.00$vc4f8/valo=4,832.99 2006.197.08:11:39.00#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.197.08:11:39.00#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.197.08:11:39.00#ibcon#ireg 17 cls_cnt 0 2006.197.08:11:39.00#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.197.08:11:39.00#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.197.08:11:39.00#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.197.08:11:39.00#ibcon#enter wrdev, iclass 14, count 0 2006.197.08:11:39.00#ibcon#first serial, iclass 14, count 0 2006.197.08:11:39.00#ibcon#enter sib2, iclass 14, count 0 2006.197.08:11:39.00#ibcon#flushed, iclass 14, count 0 2006.197.08:11:39.00#ibcon#about to write, iclass 14, count 0 2006.197.08:11:39.00#ibcon#wrote, iclass 14, count 0 2006.197.08:11:39.00#ibcon#about to read 3, iclass 14, count 0 2006.197.08:11:39.02#ibcon#read 3, iclass 14, count 0 2006.197.08:11:39.02#ibcon#about to read 4, iclass 14, count 0 2006.197.08:11:39.02#ibcon#read 4, iclass 14, count 0 2006.197.08:11:39.02#ibcon#about to read 5, iclass 14, count 0 2006.197.08:11:39.02#ibcon#read 5, iclass 14, count 0 2006.197.08:11:39.02#ibcon#about to read 6, iclass 14, count 0 2006.197.08:11:39.02#ibcon#read 6, iclass 14, count 0 2006.197.08:11:39.02#ibcon#end of sib2, iclass 14, count 0 2006.197.08:11:39.02#ibcon#*mode == 0, iclass 14, count 0 2006.197.08:11:39.02#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.197.08:11:39.02#ibcon#[26=FRQ=04,832.99\r\n] 2006.197.08:11:39.02#ibcon#*before write, iclass 14, count 0 2006.197.08:11:39.02#ibcon#enter sib2, iclass 14, count 0 2006.197.08:11:39.02#ibcon#flushed, iclass 14, count 0 2006.197.08:11:39.02#ibcon#about to write, iclass 14, count 0 2006.197.08:11:39.02#ibcon#wrote, iclass 14, count 0 2006.197.08:11:39.02#ibcon#about to read 3, iclass 14, count 0 2006.197.08:11:39.06#ibcon#read 3, iclass 14, count 0 2006.197.08:11:39.06#ibcon#about to read 4, iclass 14, count 0 2006.197.08:11:39.06#ibcon#read 4, iclass 14, count 0 2006.197.08:11:39.06#ibcon#about to read 5, iclass 14, count 0 2006.197.08:11:39.06#ibcon#read 5, iclass 14, count 0 2006.197.08:11:39.06#ibcon#about to read 6, iclass 14, count 0 2006.197.08:11:39.06#ibcon#read 6, iclass 14, count 0 2006.197.08:11:39.06#ibcon#end of sib2, iclass 14, count 0 2006.197.08:11:39.06#ibcon#*after write, iclass 14, count 0 2006.197.08:11:39.06#ibcon#*before return 0, iclass 14, count 0 2006.197.08:11:39.06#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.197.08:11:39.06#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.197.08:11:39.06#ibcon#about to clear, iclass 14 cls_cnt 0 2006.197.08:11:39.06#ibcon#cleared, iclass 14 cls_cnt 0 2006.197.08:11:39.06$vc4f8/va=4,7 2006.197.08:11:39.06#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.197.08:11:39.06#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.197.08:11:39.06#ibcon#ireg 11 cls_cnt 2 2006.197.08:11:39.06#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.197.08:11:39.12#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.197.08:11:39.12#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.197.08:11:39.12#ibcon#enter wrdev, iclass 16, count 2 2006.197.08:11:39.12#ibcon#first serial, iclass 16, count 2 2006.197.08:11:39.12#ibcon#enter sib2, iclass 16, count 2 2006.197.08:11:39.12#ibcon#flushed, iclass 16, count 2 2006.197.08:11:39.12#ibcon#about to write, iclass 16, count 2 2006.197.08:11:39.12#ibcon#wrote, iclass 16, count 2 2006.197.08:11:39.12#ibcon#about to read 3, iclass 16, count 2 2006.197.08:11:39.14#ibcon#read 3, iclass 16, count 2 2006.197.08:11:39.14#ibcon#about to read 4, iclass 16, count 2 2006.197.08:11:39.14#ibcon#read 4, iclass 16, count 2 2006.197.08:11:39.14#ibcon#about to read 5, iclass 16, count 2 2006.197.08:11:39.14#ibcon#read 5, iclass 16, count 2 2006.197.08:11:39.14#ibcon#about to read 6, iclass 16, count 2 2006.197.08:11:39.14#ibcon#read 6, iclass 16, count 2 2006.197.08:11:39.14#ibcon#end of sib2, iclass 16, count 2 2006.197.08:11:39.14#ibcon#*mode == 0, iclass 16, count 2 2006.197.08:11:39.14#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.197.08:11:39.14#ibcon#[25=AT04-07\r\n] 2006.197.08:11:39.14#ibcon#*before write, iclass 16, count 2 2006.197.08:11:39.14#ibcon#enter sib2, iclass 16, count 2 2006.197.08:11:39.14#ibcon#flushed, iclass 16, count 2 2006.197.08:11:39.14#ibcon#about to write, iclass 16, count 2 2006.197.08:11:39.14#ibcon#wrote, iclass 16, count 2 2006.197.08:11:39.14#ibcon#about to read 3, iclass 16, count 2 2006.197.08:11:39.17#ibcon#read 3, iclass 16, count 2 2006.197.08:11:39.17#ibcon#about to read 4, iclass 16, count 2 2006.197.08:11:39.17#ibcon#read 4, iclass 16, count 2 2006.197.08:11:39.17#ibcon#about to read 5, iclass 16, count 2 2006.197.08:11:39.17#ibcon#read 5, iclass 16, count 2 2006.197.08:11:39.17#ibcon#about to read 6, iclass 16, count 2 2006.197.08:11:39.17#ibcon#read 6, iclass 16, count 2 2006.197.08:11:39.17#ibcon#end of sib2, iclass 16, count 2 2006.197.08:11:39.17#ibcon#*after write, iclass 16, count 2 2006.197.08:11:39.17#ibcon#*before return 0, iclass 16, count 2 2006.197.08:11:39.17#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.197.08:11:39.17#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.197.08:11:39.17#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.197.08:11:39.17#ibcon#ireg 7 cls_cnt 0 2006.197.08:11:39.17#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.197.08:11:39.29#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.197.08:11:39.29#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.197.08:11:39.29#ibcon#enter wrdev, iclass 16, count 0 2006.197.08:11:39.29#ibcon#first serial, iclass 16, count 0 2006.197.08:11:39.29#ibcon#enter sib2, iclass 16, count 0 2006.197.08:11:39.29#ibcon#flushed, iclass 16, count 0 2006.197.08:11:39.29#ibcon#about to write, iclass 16, count 0 2006.197.08:11:39.29#ibcon#wrote, iclass 16, count 0 2006.197.08:11:39.29#ibcon#about to read 3, iclass 16, count 0 2006.197.08:11:39.31#ibcon#read 3, iclass 16, count 0 2006.197.08:11:39.31#ibcon#about to read 4, iclass 16, count 0 2006.197.08:11:39.31#ibcon#read 4, iclass 16, count 0 2006.197.08:11:39.31#ibcon#about to read 5, iclass 16, count 0 2006.197.08:11:39.31#ibcon#read 5, iclass 16, count 0 2006.197.08:11:39.31#ibcon#about to read 6, iclass 16, count 0 2006.197.08:11:39.31#ibcon#read 6, iclass 16, count 0 2006.197.08:11:39.31#ibcon#end of sib2, iclass 16, count 0 2006.197.08:11:39.31#ibcon#*mode == 0, iclass 16, count 0 2006.197.08:11:39.31#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.197.08:11:39.31#ibcon#[25=USB\r\n] 2006.197.08:11:39.31#ibcon#*before write, iclass 16, count 0 2006.197.08:11:39.31#ibcon#enter sib2, iclass 16, count 0 2006.197.08:11:39.31#ibcon#flushed, iclass 16, count 0 2006.197.08:11:39.31#ibcon#about to write, iclass 16, count 0 2006.197.08:11:39.31#ibcon#wrote, iclass 16, count 0 2006.197.08:11:39.31#ibcon#about to read 3, iclass 16, count 0 2006.197.08:11:39.34#ibcon#read 3, iclass 16, count 0 2006.197.08:11:39.34#ibcon#about to read 4, iclass 16, count 0 2006.197.08:11:39.34#ibcon#read 4, iclass 16, count 0 2006.197.08:11:39.34#ibcon#about to read 5, iclass 16, count 0 2006.197.08:11:39.34#ibcon#read 5, iclass 16, count 0 2006.197.08:11:39.34#ibcon#about to read 6, iclass 16, count 0 2006.197.08:11:39.34#ibcon#read 6, iclass 16, count 0 2006.197.08:11:39.34#ibcon#end of sib2, iclass 16, count 0 2006.197.08:11:39.34#ibcon#*after write, iclass 16, count 0 2006.197.08:11:39.34#ibcon#*before return 0, iclass 16, count 0 2006.197.08:11:39.34#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.197.08:11:39.34#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.197.08:11:39.34#ibcon#about to clear, iclass 16 cls_cnt 0 2006.197.08:11:39.34#ibcon#cleared, iclass 16 cls_cnt 0 2006.197.08:11:39.34$vc4f8/valo=5,652.99 2006.197.08:11:39.34#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.197.08:11:39.34#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.197.08:11:39.34#ibcon#ireg 17 cls_cnt 0 2006.197.08:11:39.34#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.197.08:11:39.34#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.197.08:11:39.34#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.197.08:11:39.34#ibcon#enter wrdev, iclass 18, count 0 2006.197.08:11:39.34#ibcon#first serial, iclass 18, count 0 2006.197.08:11:39.34#ibcon#enter sib2, iclass 18, count 0 2006.197.08:11:39.34#ibcon#flushed, iclass 18, count 0 2006.197.08:11:39.34#ibcon#about to write, iclass 18, count 0 2006.197.08:11:39.34#ibcon#wrote, iclass 18, count 0 2006.197.08:11:39.34#ibcon#about to read 3, iclass 18, count 0 2006.197.08:11:39.36#ibcon#read 3, iclass 18, count 0 2006.197.08:11:39.36#ibcon#about to read 4, iclass 18, count 0 2006.197.08:11:39.36#ibcon#read 4, iclass 18, count 0 2006.197.08:11:39.36#ibcon#about to read 5, iclass 18, count 0 2006.197.08:11:39.36#ibcon#read 5, iclass 18, count 0 2006.197.08:11:39.36#ibcon#about to read 6, iclass 18, count 0 2006.197.08:11:39.36#ibcon#read 6, iclass 18, count 0 2006.197.08:11:39.36#ibcon#end of sib2, iclass 18, count 0 2006.197.08:11:39.36#ibcon#*mode == 0, iclass 18, count 0 2006.197.08:11:39.36#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.197.08:11:39.36#ibcon#[26=FRQ=05,652.99\r\n] 2006.197.08:11:39.36#ibcon#*before write, iclass 18, count 0 2006.197.08:11:39.36#ibcon#enter sib2, iclass 18, count 0 2006.197.08:11:39.36#ibcon#flushed, iclass 18, count 0 2006.197.08:11:39.36#ibcon#about to write, iclass 18, count 0 2006.197.08:11:39.36#ibcon#wrote, iclass 18, count 0 2006.197.08:11:39.36#ibcon#about to read 3, iclass 18, count 0 2006.197.08:11:39.40#ibcon#read 3, iclass 18, count 0 2006.197.08:11:39.40#ibcon#about to read 4, iclass 18, count 0 2006.197.08:11:39.40#ibcon#read 4, iclass 18, count 0 2006.197.08:11:39.40#ibcon#about to read 5, iclass 18, count 0 2006.197.08:11:39.40#ibcon#read 5, iclass 18, count 0 2006.197.08:11:39.40#ibcon#about to read 6, iclass 18, count 0 2006.197.08:11:39.40#ibcon#read 6, iclass 18, count 0 2006.197.08:11:39.40#ibcon#end of sib2, iclass 18, count 0 2006.197.08:11:39.40#ibcon#*after write, iclass 18, count 0 2006.197.08:11:39.40#ibcon#*before return 0, iclass 18, count 0 2006.197.08:11:39.40#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.197.08:11:39.40#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.197.08:11:39.40#ibcon#about to clear, iclass 18 cls_cnt 0 2006.197.08:11:39.40#ibcon#cleared, iclass 18 cls_cnt 0 2006.197.08:11:39.40$vc4f8/va=5,7 2006.197.08:11:39.40#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.197.08:11:39.40#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.197.08:11:39.40#ibcon#ireg 11 cls_cnt 2 2006.197.08:11:39.40#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.197.08:11:39.46#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.197.08:11:39.46#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.197.08:11:39.46#ibcon#enter wrdev, iclass 20, count 2 2006.197.08:11:39.46#ibcon#first serial, iclass 20, count 2 2006.197.08:11:39.46#ibcon#enter sib2, iclass 20, count 2 2006.197.08:11:39.46#ibcon#flushed, iclass 20, count 2 2006.197.08:11:39.46#ibcon#about to write, iclass 20, count 2 2006.197.08:11:39.46#ibcon#wrote, iclass 20, count 2 2006.197.08:11:39.46#ibcon#about to read 3, iclass 20, count 2 2006.197.08:11:39.48#ibcon#read 3, iclass 20, count 2 2006.197.08:11:39.48#ibcon#about to read 4, iclass 20, count 2 2006.197.08:11:39.48#ibcon#read 4, iclass 20, count 2 2006.197.08:11:39.48#ibcon#about to read 5, iclass 20, count 2 2006.197.08:11:39.48#ibcon#read 5, iclass 20, count 2 2006.197.08:11:39.48#ibcon#about to read 6, iclass 20, count 2 2006.197.08:11:39.48#ibcon#read 6, iclass 20, count 2 2006.197.08:11:39.48#ibcon#end of sib2, iclass 20, count 2 2006.197.08:11:39.48#ibcon#*mode == 0, iclass 20, count 2 2006.197.08:11:39.48#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.197.08:11:39.48#ibcon#[25=AT05-07\r\n] 2006.197.08:11:39.48#ibcon#*before write, iclass 20, count 2 2006.197.08:11:39.48#ibcon#enter sib2, iclass 20, count 2 2006.197.08:11:39.48#ibcon#flushed, iclass 20, count 2 2006.197.08:11:39.48#ibcon#about to write, iclass 20, count 2 2006.197.08:11:39.48#ibcon#wrote, iclass 20, count 2 2006.197.08:11:39.48#ibcon#about to read 3, iclass 20, count 2 2006.197.08:11:39.51#ibcon#read 3, iclass 20, count 2 2006.197.08:11:39.51#ibcon#about to read 4, iclass 20, count 2 2006.197.08:11:39.51#ibcon#read 4, iclass 20, count 2 2006.197.08:11:39.51#ibcon#about to read 5, iclass 20, count 2 2006.197.08:11:39.51#ibcon#read 5, iclass 20, count 2 2006.197.08:11:39.51#ibcon#about to read 6, iclass 20, count 2 2006.197.08:11:39.51#ibcon#read 6, iclass 20, count 2 2006.197.08:11:39.51#ibcon#end of sib2, iclass 20, count 2 2006.197.08:11:39.51#ibcon#*after write, iclass 20, count 2 2006.197.08:11:39.51#ibcon#*before return 0, iclass 20, count 2 2006.197.08:11:39.51#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.197.08:11:39.51#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.197.08:11:39.51#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.197.08:11:39.51#ibcon#ireg 7 cls_cnt 0 2006.197.08:11:39.51#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.197.08:11:39.63#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.197.08:11:39.63#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.197.08:11:39.63#ibcon#enter wrdev, iclass 20, count 0 2006.197.08:11:39.63#ibcon#first serial, iclass 20, count 0 2006.197.08:11:39.63#ibcon#enter sib2, iclass 20, count 0 2006.197.08:11:39.63#ibcon#flushed, iclass 20, count 0 2006.197.08:11:39.63#ibcon#about to write, iclass 20, count 0 2006.197.08:11:39.63#ibcon#wrote, iclass 20, count 0 2006.197.08:11:39.63#ibcon#about to read 3, iclass 20, count 0 2006.197.08:11:39.65#ibcon#read 3, iclass 20, count 0 2006.197.08:11:39.65#ibcon#about to read 4, iclass 20, count 0 2006.197.08:11:39.65#ibcon#read 4, iclass 20, count 0 2006.197.08:11:39.65#ibcon#about to read 5, iclass 20, count 0 2006.197.08:11:39.65#ibcon#read 5, iclass 20, count 0 2006.197.08:11:39.65#ibcon#about to read 6, iclass 20, count 0 2006.197.08:11:39.65#ibcon#read 6, iclass 20, count 0 2006.197.08:11:39.65#ibcon#end of sib2, iclass 20, count 0 2006.197.08:11:39.65#ibcon#*mode == 0, iclass 20, count 0 2006.197.08:11:39.65#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.197.08:11:39.65#ibcon#[25=USB\r\n] 2006.197.08:11:39.65#ibcon#*before write, iclass 20, count 0 2006.197.08:11:39.65#ibcon#enter sib2, iclass 20, count 0 2006.197.08:11:39.65#ibcon#flushed, iclass 20, count 0 2006.197.08:11:39.65#ibcon#about to write, iclass 20, count 0 2006.197.08:11:39.65#ibcon#wrote, iclass 20, count 0 2006.197.08:11:39.65#ibcon#about to read 3, iclass 20, count 0 2006.197.08:11:39.68#ibcon#read 3, iclass 20, count 0 2006.197.08:11:39.68#ibcon#about to read 4, iclass 20, count 0 2006.197.08:11:39.68#ibcon#read 4, iclass 20, count 0 2006.197.08:11:39.68#ibcon#about to read 5, iclass 20, count 0 2006.197.08:11:39.68#ibcon#read 5, iclass 20, count 0 2006.197.08:11:39.68#ibcon#about to read 6, iclass 20, count 0 2006.197.08:11:39.68#ibcon#read 6, iclass 20, count 0 2006.197.08:11:39.68#ibcon#end of sib2, iclass 20, count 0 2006.197.08:11:39.68#ibcon#*after write, iclass 20, count 0 2006.197.08:11:39.68#ibcon#*before return 0, iclass 20, count 0 2006.197.08:11:39.68#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.197.08:11:39.68#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.197.08:11:39.68#ibcon#about to clear, iclass 20 cls_cnt 0 2006.197.08:11:39.68#ibcon#cleared, iclass 20 cls_cnt 0 2006.197.08:11:39.68$vc4f8/valo=6,772.99 2006.197.08:11:39.68#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.197.08:11:39.68#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.197.08:11:39.68#ibcon#ireg 17 cls_cnt 0 2006.197.08:11:39.68#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.197.08:11:39.68#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.197.08:11:39.68#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.197.08:11:39.68#ibcon#enter wrdev, iclass 22, count 0 2006.197.08:11:39.68#ibcon#first serial, iclass 22, count 0 2006.197.08:11:39.68#ibcon#enter sib2, iclass 22, count 0 2006.197.08:11:39.68#ibcon#flushed, iclass 22, count 0 2006.197.08:11:39.68#ibcon#about to write, iclass 22, count 0 2006.197.08:11:39.68#ibcon#wrote, iclass 22, count 0 2006.197.08:11:39.68#ibcon#about to read 3, iclass 22, count 0 2006.197.08:11:39.70#ibcon#read 3, iclass 22, count 0 2006.197.08:11:39.70#ibcon#about to read 4, iclass 22, count 0 2006.197.08:11:39.70#ibcon#read 4, iclass 22, count 0 2006.197.08:11:39.70#ibcon#about to read 5, iclass 22, count 0 2006.197.08:11:39.70#ibcon#read 5, iclass 22, count 0 2006.197.08:11:39.70#ibcon#about to read 6, iclass 22, count 0 2006.197.08:11:39.70#ibcon#read 6, iclass 22, count 0 2006.197.08:11:39.70#ibcon#end of sib2, iclass 22, count 0 2006.197.08:11:39.70#ibcon#*mode == 0, iclass 22, count 0 2006.197.08:11:39.70#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.197.08:11:39.70#ibcon#[26=FRQ=06,772.99\r\n] 2006.197.08:11:39.70#ibcon#*before write, iclass 22, count 0 2006.197.08:11:39.70#ibcon#enter sib2, iclass 22, count 0 2006.197.08:11:39.70#ibcon#flushed, iclass 22, count 0 2006.197.08:11:39.70#ibcon#about to write, iclass 22, count 0 2006.197.08:11:39.70#ibcon#wrote, iclass 22, count 0 2006.197.08:11:39.70#ibcon#about to read 3, iclass 22, count 0 2006.197.08:11:39.74#ibcon#read 3, iclass 22, count 0 2006.197.08:11:39.74#ibcon#about to read 4, iclass 22, count 0 2006.197.08:11:39.74#ibcon#read 4, iclass 22, count 0 2006.197.08:11:39.74#ibcon#about to read 5, iclass 22, count 0 2006.197.08:11:39.74#ibcon#read 5, iclass 22, count 0 2006.197.08:11:39.74#ibcon#about to read 6, iclass 22, count 0 2006.197.08:11:39.74#ibcon#read 6, iclass 22, count 0 2006.197.08:11:39.74#ibcon#end of sib2, iclass 22, count 0 2006.197.08:11:39.74#ibcon#*after write, iclass 22, count 0 2006.197.08:11:39.74#ibcon#*before return 0, iclass 22, count 0 2006.197.08:11:39.74#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.197.08:11:39.74#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.197.08:11:39.74#ibcon#about to clear, iclass 22 cls_cnt 0 2006.197.08:11:39.74#ibcon#cleared, iclass 22 cls_cnt 0 2006.197.08:11:39.74$vc4f8/va=6,6 2006.197.08:11:39.74#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.197.08:11:39.74#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.197.08:11:39.74#ibcon#ireg 11 cls_cnt 2 2006.197.08:11:39.74#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.197.08:11:39.80#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.197.08:11:39.80#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.197.08:11:39.80#ibcon#enter wrdev, iclass 24, count 2 2006.197.08:11:39.80#ibcon#first serial, iclass 24, count 2 2006.197.08:11:39.80#ibcon#enter sib2, iclass 24, count 2 2006.197.08:11:39.80#ibcon#flushed, iclass 24, count 2 2006.197.08:11:39.80#ibcon#about to write, iclass 24, count 2 2006.197.08:11:39.80#ibcon#wrote, iclass 24, count 2 2006.197.08:11:39.80#ibcon#about to read 3, iclass 24, count 2 2006.197.08:11:39.82#ibcon#read 3, iclass 24, count 2 2006.197.08:11:39.82#ibcon#about to read 4, iclass 24, count 2 2006.197.08:11:39.82#ibcon#read 4, iclass 24, count 2 2006.197.08:11:39.82#ibcon#about to read 5, iclass 24, count 2 2006.197.08:11:39.82#ibcon#read 5, iclass 24, count 2 2006.197.08:11:39.82#ibcon#about to read 6, iclass 24, count 2 2006.197.08:11:39.82#ibcon#read 6, iclass 24, count 2 2006.197.08:11:39.82#ibcon#end of sib2, iclass 24, count 2 2006.197.08:11:39.82#ibcon#*mode == 0, iclass 24, count 2 2006.197.08:11:39.82#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.197.08:11:39.82#ibcon#[25=AT06-06\r\n] 2006.197.08:11:39.82#ibcon#*before write, iclass 24, count 2 2006.197.08:11:39.82#ibcon#enter sib2, iclass 24, count 2 2006.197.08:11:39.82#ibcon#flushed, iclass 24, count 2 2006.197.08:11:39.82#ibcon#about to write, iclass 24, count 2 2006.197.08:11:39.82#ibcon#wrote, iclass 24, count 2 2006.197.08:11:39.82#ibcon#about to read 3, iclass 24, count 2 2006.197.08:11:39.85#ibcon#read 3, iclass 24, count 2 2006.197.08:11:39.85#ibcon#about to read 4, iclass 24, count 2 2006.197.08:11:39.85#ibcon#read 4, iclass 24, count 2 2006.197.08:11:39.85#ibcon#about to read 5, iclass 24, count 2 2006.197.08:11:39.85#ibcon#read 5, iclass 24, count 2 2006.197.08:11:39.85#ibcon#about to read 6, iclass 24, count 2 2006.197.08:11:39.85#ibcon#read 6, iclass 24, count 2 2006.197.08:11:39.85#ibcon#end of sib2, iclass 24, count 2 2006.197.08:11:39.85#ibcon#*after write, iclass 24, count 2 2006.197.08:11:39.85#ibcon#*before return 0, iclass 24, count 2 2006.197.08:11:39.85#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.197.08:11:39.85#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.197.08:11:39.85#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.197.08:11:39.85#ibcon#ireg 7 cls_cnt 0 2006.197.08:11:39.85#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.197.08:11:39.97#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.197.08:11:39.97#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.197.08:11:39.97#ibcon#enter wrdev, iclass 24, count 0 2006.197.08:11:39.97#ibcon#first serial, iclass 24, count 0 2006.197.08:11:39.97#ibcon#enter sib2, iclass 24, count 0 2006.197.08:11:39.97#ibcon#flushed, iclass 24, count 0 2006.197.08:11:39.97#ibcon#about to write, iclass 24, count 0 2006.197.08:11:39.97#ibcon#wrote, iclass 24, count 0 2006.197.08:11:39.97#ibcon#about to read 3, iclass 24, count 0 2006.197.08:11:39.99#ibcon#read 3, iclass 24, count 0 2006.197.08:11:39.99#ibcon#about to read 4, iclass 24, count 0 2006.197.08:11:39.99#ibcon#read 4, iclass 24, count 0 2006.197.08:11:39.99#ibcon#about to read 5, iclass 24, count 0 2006.197.08:11:39.99#ibcon#read 5, iclass 24, count 0 2006.197.08:11:39.99#ibcon#about to read 6, iclass 24, count 0 2006.197.08:11:39.99#ibcon#read 6, iclass 24, count 0 2006.197.08:11:39.99#ibcon#end of sib2, iclass 24, count 0 2006.197.08:11:39.99#ibcon#*mode == 0, iclass 24, count 0 2006.197.08:11:39.99#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.197.08:11:39.99#ibcon#[25=USB\r\n] 2006.197.08:11:39.99#ibcon#*before write, iclass 24, count 0 2006.197.08:11:39.99#ibcon#enter sib2, iclass 24, count 0 2006.197.08:11:39.99#ibcon#flushed, iclass 24, count 0 2006.197.08:11:39.99#ibcon#about to write, iclass 24, count 0 2006.197.08:11:39.99#ibcon#wrote, iclass 24, count 0 2006.197.08:11:39.99#ibcon#about to read 3, iclass 24, count 0 2006.197.08:11:40.02#ibcon#read 3, iclass 24, count 0 2006.197.08:11:40.02#ibcon#about to read 4, iclass 24, count 0 2006.197.08:11:40.02#ibcon#read 4, iclass 24, count 0 2006.197.08:11:40.02#ibcon#about to read 5, iclass 24, count 0 2006.197.08:11:40.02#ibcon#read 5, iclass 24, count 0 2006.197.08:11:40.02#ibcon#about to read 6, iclass 24, count 0 2006.197.08:11:40.02#ibcon#read 6, iclass 24, count 0 2006.197.08:11:40.02#ibcon#end of sib2, iclass 24, count 0 2006.197.08:11:40.02#ibcon#*after write, iclass 24, count 0 2006.197.08:11:40.02#ibcon#*before return 0, iclass 24, count 0 2006.197.08:11:40.02#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.197.08:11:40.02#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.197.08:11:40.02#ibcon#about to clear, iclass 24 cls_cnt 0 2006.197.08:11:40.02#ibcon#cleared, iclass 24 cls_cnt 0 2006.197.08:11:40.02$vc4f8/valo=7,832.99 2006.197.08:11:40.02#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.197.08:11:40.02#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.197.08:11:40.02#ibcon#ireg 17 cls_cnt 0 2006.197.08:11:40.02#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.197.08:11:40.02#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.197.08:11:40.02#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.197.08:11:40.02#ibcon#enter wrdev, iclass 26, count 0 2006.197.08:11:40.02#ibcon#first serial, iclass 26, count 0 2006.197.08:11:40.02#ibcon#enter sib2, iclass 26, count 0 2006.197.08:11:40.02#ibcon#flushed, iclass 26, count 0 2006.197.08:11:40.02#ibcon#about to write, iclass 26, count 0 2006.197.08:11:40.02#ibcon#wrote, iclass 26, count 0 2006.197.08:11:40.02#ibcon#about to read 3, iclass 26, count 0 2006.197.08:11:40.04#ibcon#read 3, iclass 26, count 0 2006.197.08:11:40.04#ibcon#about to read 4, iclass 26, count 0 2006.197.08:11:40.04#ibcon#read 4, iclass 26, count 0 2006.197.08:11:40.04#ibcon#about to read 5, iclass 26, count 0 2006.197.08:11:40.04#ibcon#read 5, iclass 26, count 0 2006.197.08:11:40.04#ibcon#about to read 6, iclass 26, count 0 2006.197.08:11:40.04#ibcon#read 6, iclass 26, count 0 2006.197.08:11:40.04#ibcon#end of sib2, iclass 26, count 0 2006.197.08:11:40.04#ibcon#*mode == 0, iclass 26, count 0 2006.197.08:11:40.04#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.197.08:11:40.04#ibcon#[26=FRQ=07,832.99\r\n] 2006.197.08:11:40.04#ibcon#*before write, iclass 26, count 0 2006.197.08:11:40.04#ibcon#enter sib2, iclass 26, count 0 2006.197.08:11:40.04#ibcon#flushed, iclass 26, count 0 2006.197.08:11:40.04#ibcon#about to write, iclass 26, count 0 2006.197.08:11:40.04#ibcon#wrote, iclass 26, count 0 2006.197.08:11:40.04#ibcon#about to read 3, iclass 26, count 0 2006.197.08:11:40.08#ibcon#read 3, iclass 26, count 0 2006.197.08:11:40.08#ibcon#about to read 4, iclass 26, count 0 2006.197.08:11:40.08#ibcon#read 4, iclass 26, count 0 2006.197.08:11:40.08#ibcon#about to read 5, iclass 26, count 0 2006.197.08:11:40.08#ibcon#read 5, iclass 26, count 0 2006.197.08:11:40.08#ibcon#about to read 6, iclass 26, count 0 2006.197.08:11:40.08#ibcon#read 6, iclass 26, count 0 2006.197.08:11:40.08#ibcon#end of sib2, iclass 26, count 0 2006.197.08:11:40.08#ibcon#*after write, iclass 26, count 0 2006.197.08:11:40.08#ibcon#*before return 0, iclass 26, count 0 2006.197.08:11:40.08#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.197.08:11:40.08#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.197.08:11:40.08#ibcon#about to clear, iclass 26 cls_cnt 0 2006.197.08:11:40.08#ibcon#cleared, iclass 26 cls_cnt 0 2006.197.08:11:40.08$vc4f8/va=7,6 2006.197.08:11:40.08#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.197.08:11:40.08#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.197.08:11:40.08#ibcon#ireg 11 cls_cnt 2 2006.197.08:11:40.08#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.197.08:11:40.14#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.197.08:11:40.14#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.197.08:11:40.14#ibcon#enter wrdev, iclass 28, count 2 2006.197.08:11:40.14#ibcon#first serial, iclass 28, count 2 2006.197.08:11:40.14#ibcon#enter sib2, iclass 28, count 2 2006.197.08:11:40.14#ibcon#flushed, iclass 28, count 2 2006.197.08:11:40.14#ibcon#about to write, iclass 28, count 2 2006.197.08:11:40.14#ibcon#wrote, iclass 28, count 2 2006.197.08:11:40.14#ibcon#about to read 3, iclass 28, count 2 2006.197.08:11:40.16#ibcon#read 3, iclass 28, count 2 2006.197.08:11:40.16#ibcon#about to read 4, iclass 28, count 2 2006.197.08:11:40.16#ibcon#read 4, iclass 28, count 2 2006.197.08:11:40.16#ibcon#about to read 5, iclass 28, count 2 2006.197.08:11:40.16#ibcon#read 5, iclass 28, count 2 2006.197.08:11:40.16#ibcon#about to read 6, iclass 28, count 2 2006.197.08:11:40.16#ibcon#read 6, iclass 28, count 2 2006.197.08:11:40.16#ibcon#end of sib2, iclass 28, count 2 2006.197.08:11:40.16#ibcon#*mode == 0, iclass 28, count 2 2006.197.08:11:40.16#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.197.08:11:40.16#ibcon#[25=AT07-06\r\n] 2006.197.08:11:40.16#ibcon#*before write, iclass 28, count 2 2006.197.08:11:40.16#ibcon#enter sib2, iclass 28, count 2 2006.197.08:11:40.16#ibcon#flushed, iclass 28, count 2 2006.197.08:11:40.16#ibcon#about to write, iclass 28, count 2 2006.197.08:11:40.16#ibcon#wrote, iclass 28, count 2 2006.197.08:11:40.16#ibcon#about to read 3, iclass 28, count 2 2006.197.08:11:40.19#ibcon#read 3, iclass 28, count 2 2006.197.08:11:40.19#ibcon#about to read 4, iclass 28, count 2 2006.197.08:11:40.19#ibcon#read 4, iclass 28, count 2 2006.197.08:11:40.19#ibcon#about to read 5, iclass 28, count 2 2006.197.08:11:40.19#ibcon#read 5, iclass 28, count 2 2006.197.08:11:40.19#ibcon#about to read 6, iclass 28, count 2 2006.197.08:11:40.19#ibcon#read 6, iclass 28, count 2 2006.197.08:11:40.19#ibcon#end of sib2, iclass 28, count 2 2006.197.08:11:40.19#ibcon#*after write, iclass 28, count 2 2006.197.08:11:40.19#ibcon#*before return 0, iclass 28, count 2 2006.197.08:11:40.19#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.197.08:11:40.19#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.197.08:11:40.19#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.197.08:11:40.19#ibcon#ireg 7 cls_cnt 0 2006.197.08:11:40.19#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.197.08:11:40.31#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.197.08:11:40.31#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.197.08:11:40.31#ibcon#enter wrdev, iclass 28, count 0 2006.197.08:11:40.31#ibcon#first serial, iclass 28, count 0 2006.197.08:11:40.31#ibcon#enter sib2, iclass 28, count 0 2006.197.08:11:40.31#ibcon#flushed, iclass 28, count 0 2006.197.08:11:40.31#ibcon#about to write, iclass 28, count 0 2006.197.08:11:40.31#ibcon#wrote, iclass 28, count 0 2006.197.08:11:40.31#ibcon#about to read 3, iclass 28, count 0 2006.197.08:11:40.33#ibcon#read 3, iclass 28, count 0 2006.197.08:11:40.33#ibcon#about to read 4, iclass 28, count 0 2006.197.08:11:40.33#ibcon#read 4, iclass 28, count 0 2006.197.08:11:40.33#ibcon#about to read 5, iclass 28, count 0 2006.197.08:11:40.33#ibcon#read 5, iclass 28, count 0 2006.197.08:11:40.33#ibcon#about to read 6, iclass 28, count 0 2006.197.08:11:40.33#ibcon#read 6, iclass 28, count 0 2006.197.08:11:40.33#ibcon#end of sib2, iclass 28, count 0 2006.197.08:11:40.33#ibcon#*mode == 0, iclass 28, count 0 2006.197.08:11:40.33#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.197.08:11:40.33#ibcon#[25=USB\r\n] 2006.197.08:11:40.33#ibcon#*before write, iclass 28, count 0 2006.197.08:11:40.33#ibcon#enter sib2, iclass 28, count 0 2006.197.08:11:40.33#ibcon#flushed, iclass 28, count 0 2006.197.08:11:40.33#ibcon#about to write, iclass 28, count 0 2006.197.08:11:40.33#ibcon#wrote, iclass 28, count 0 2006.197.08:11:40.33#ibcon#about to read 3, iclass 28, count 0 2006.197.08:11:40.36#ibcon#read 3, iclass 28, count 0 2006.197.08:11:40.36#ibcon#about to read 4, iclass 28, count 0 2006.197.08:11:40.36#ibcon#read 4, iclass 28, count 0 2006.197.08:11:40.36#ibcon#about to read 5, iclass 28, count 0 2006.197.08:11:40.36#ibcon#read 5, iclass 28, count 0 2006.197.08:11:40.36#ibcon#about to read 6, iclass 28, count 0 2006.197.08:11:40.36#ibcon#read 6, iclass 28, count 0 2006.197.08:11:40.36#ibcon#end of sib2, iclass 28, count 0 2006.197.08:11:40.36#ibcon#*after write, iclass 28, count 0 2006.197.08:11:40.36#ibcon#*before return 0, iclass 28, count 0 2006.197.08:11:40.36#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.197.08:11:40.36#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.197.08:11:40.36#ibcon#about to clear, iclass 28 cls_cnt 0 2006.197.08:11:40.36#ibcon#cleared, iclass 28 cls_cnt 0 2006.197.08:11:40.36$vc4f8/valo=8,852.99 2006.197.08:11:40.36#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.197.08:11:40.36#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.197.08:11:40.36#ibcon#ireg 17 cls_cnt 0 2006.197.08:11:40.36#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.197.08:11:40.36#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.197.08:11:40.36#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.197.08:11:40.36#ibcon#enter wrdev, iclass 30, count 0 2006.197.08:11:40.36#ibcon#first serial, iclass 30, count 0 2006.197.08:11:40.36#ibcon#enter sib2, iclass 30, count 0 2006.197.08:11:40.36#ibcon#flushed, iclass 30, count 0 2006.197.08:11:40.36#ibcon#about to write, iclass 30, count 0 2006.197.08:11:40.36#ibcon#wrote, iclass 30, count 0 2006.197.08:11:40.36#ibcon#about to read 3, iclass 30, count 0 2006.197.08:11:40.38#ibcon#read 3, iclass 30, count 0 2006.197.08:11:40.38#ibcon#about to read 4, iclass 30, count 0 2006.197.08:11:40.38#ibcon#read 4, iclass 30, count 0 2006.197.08:11:40.38#ibcon#about to read 5, iclass 30, count 0 2006.197.08:11:40.38#ibcon#read 5, iclass 30, count 0 2006.197.08:11:40.38#ibcon#about to read 6, iclass 30, count 0 2006.197.08:11:40.38#ibcon#read 6, iclass 30, count 0 2006.197.08:11:40.38#ibcon#end of sib2, iclass 30, count 0 2006.197.08:11:40.38#ibcon#*mode == 0, iclass 30, count 0 2006.197.08:11:40.38#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.197.08:11:40.38#ibcon#[26=FRQ=08,852.99\r\n] 2006.197.08:11:40.38#ibcon#*before write, iclass 30, count 0 2006.197.08:11:40.38#ibcon#enter sib2, iclass 30, count 0 2006.197.08:11:40.38#ibcon#flushed, iclass 30, count 0 2006.197.08:11:40.38#ibcon#about to write, iclass 30, count 0 2006.197.08:11:40.38#ibcon#wrote, iclass 30, count 0 2006.197.08:11:40.38#ibcon#about to read 3, iclass 30, count 0 2006.197.08:11:40.42#ibcon#read 3, iclass 30, count 0 2006.197.08:11:40.42#ibcon#about to read 4, iclass 30, count 0 2006.197.08:11:40.42#ibcon#read 4, iclass 30, count 0 2006.197.08:11:40.42#ibcon#about to read 5, iclass 30, count 0 2006.197.08:11:40.42#ibcon#read 5, iclass 30, count 0 2006.197.08:11:40.42#ibcon#about to read 6, iclass 30, count 0 2006.197.08:11:40.42#ibcon#read 6, iclass 30, count 0 2006.197.08:11:40.42#ibcon#end of sib2, iclass 30, count 0 2006.197.08:11:40.42#ibcon#*after write, iclass 30, count 0 2006.197.08:11:40.42#ibcon#*before return 0, iclass 30, count 0 2006.197.08:11:40.42#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.197.08:11:40.42#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.197.08:11:40.42#ibcon#about to clear, iclass 30 cls_cnt 0 2006.197.08:11:40.42#ibcon#cleared, iclass 30 cls_cnt 0 2006.197.08:11:40.42$vc4f8/va=8,7 2006.197.08:11:40.42#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.197.08:11:40.42#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.197.08:11:40.42#ibcon#ireg 11 cls_cnt 2 2006.197.08:11:40.42#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.197.08:11:40.48#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.197.08:11:40.48#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.197.08:11:40.48#ibcon#enter wrdev, iclass 32, count 2 2006.197.08:11:40.48#ibcon#first serial, iclass 32, count 2 2006.197.08:11:40.48#ibcon#enter sib2, iclass 32, count 2 2006.197.08:11:40.48#ibcon#flushed, iclass 32, count 2 2006.197.08:11:40.48#ibcon#about to write, iclass 32, count 2 2006.197.08:11:40.48#ibcon#wrote, iclass 32, count 2 2006.197.08:11:40.48#ibcon#about to read 3, iclass 32, count 2 2006.197.08:11:40.50#ibcon#read 3, iclass 32, count 2 2006.197.08:11:40.50#ibcon#about to read 4, iclass 32, count 2 2006.197.08:11:40.50#ibcon#read 4, iclass 32, count 2 2006.197.08:11:40.50#ibcon#about to read 5, iclass 32, count 2 2006.197.08:11:40.50#ibcon#read 5, iclass 32, count 2 2006.197.08:11:40.50#ibcon#about to read 6, iclass 32, count 2 2006.197.08:11:40.50#ibcon#read 6, iclass 32, count 2 2006.197.08:11:40.50#ibcon#end of sib2, iclass 32, count 2 2006.197.08:11:40.50#ibcon#*mode == 0, iclass 32, count 2 2006.197.08:11:40.50#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.197.08:11:40.50#ibcon#[25=AT08-07\r\n] 2006.197.08:11:40.50#ibcon#*before write, iclass 32, count 2 2006.197.08:11:40.50#ibcon#enter sib2, iclass 32, count 2 2006.197.08:11:40.50#ibcon#flushed, iclass 32, count 2 2006.197.08:11:40.50#ibcon#about to write, iclass 32, count 2 2006.197.08:11:40.50#ibcon#wrote, iclass 32, count 2 2006.197.08:11:40.50#ibcon#about to read 3, iclass 32, count 2 2006.197.08:11:40.53#ibcon#read 3, iclass 32, count 2 2006.197.08:11:40.53#ibcon#about to read 4, iclass 32, count 2 2006.197.08:11:40.53#ibcon#read 4, iclass 32, count 2 2006.197.08:11:40.53#ibcon#about to read 5, iclass 32, count 2 2006.197.08:11:40.53#ibcon#read 5, iclass 32, count 2 2006.197.08:11:40.53#ibcon#about to read 6, iclass 32, count 2 2006.197.08:11:40.53#ibcon#read 6, iclass 32, count 2 2006.197.08:11:40.53#ibcon#end of sib2, iclass 32, count 2 2006.197.08:11:40.53#ibcon#*after write, iclass 32, count 2 2006.197.08:11:40.53#ibcon#*before return 0, iclass 32, count 2 2006.197.08:11:40.53#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.197.08:11:40.53#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.197.08:11:40.53#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.197.08:11:40.53#ibcon#ireg 7 cls_cnt 0 2006.197.08:11:40.53#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.197.08:11:40.65#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.197.08:11:40.65#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.197.08:11:40.65#ibcon#enter wrdev, iclass 32, count 0 2006.197.08:11:40.65#ibcon#first serial, iclass 32, count 0 2006.197.08:11:40.65#ibcon#enter sib2, iclass 32, count 0 2006.197.08:11:40.65#ibcon#flushed, iclass 32, count 0 2006.197.08:11:40.65#ibcon#about to write, iclass 32, count 0 2006.197.08:11:40.65#ibcon#wrote, iclass 32, count 0 2006.197.08:11:40.65#ibcon#about to read 3, iclass 32, count 0 2006.197.08:11:40.67#ibcon#read 3, iclass 32, count 0 2006.197.08:11:40.67#ibcon#about to read 4, iclass 32, count 0 2006.197.08:11:40.67#ibcon#read 4, iclass 32, count 0 2006.197.08:11:40.67#ibcon#about to read 5, iclass 32, count 0 2006.197.08:11:40.67#ibcon#read 5, iclass 32, count 0 2006.197.08:11:40.67#ibcon#about to read 6, iclass 32, count 0 2006.197.08:11:40.67#ibcon#read 6, iclass 32, count 0 2006.197.08:11:40.67#ibcon#end of sib2, iclass 32, count 0 2006.197.08:11:40.67#ibcon#*mode == 0, iclass 32, count 0 2006.197.08:11:40.67#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.197.08:11:40.67#ibcon#[25=USB\r\n] 2006.197.08:11:40.67#ibcon#*before write, iclass 32, count 0 2006.197.08:11:40.67#ibcon#enter sib2, iclass 32, count 0 2006.197.08:11:40.67#ibcon#flushed, iclass 32, count 0 2006.197.08:11:40.67#ibcon#about to write, iclass 32, count 0 2006.197.08:11:40.67#ibcon#wrote, iclass 32, count 0 2006.197.08:11:40.67#ibcon#about to read 3, iclass 32, count 0 2006.197.08:11:40.70#ibcon#read 3, iclass 32, count 0 2006.197.08:11:40.70#ibcon#about to read 4, iclass 32, count 0 2006.197.08:11:40.70#ibcon#read 4, iclass 32, count 0 2006.197.08:11:40.70#ibcon#about to read 5, iclass 32, count 0 2006.197.08:11:40.70#ibcon#read 5, iclass 32, count 0 2006.197.08:11:40.70#ibcon#about to read 6, iclass 32, count 0 2006.197.08:11:40.70#ibcon#read 6, iclass 32, count 0 2006.197.08:11:40.70#ibcon#end of sib2, iclass 32, count 0 2006.197.08:11:40.70#ibcon#*after write, iclass 32, count 0 2006.197.08:11:40.70#ibcon#*before return 0, iclass 32, count 0 2006.197.08:11:40.70#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.197.08:11:40.70#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.197.08:11:40.70#ibcon#about to clear, iclass 32 cls_cnt 0 2006.197.08:11:40.70#ibcon#cleared, iclass 32 cls_cnt 0 2006.197.08:11:40.70$vc4f8/vblo=1,632.99 2006.197.08:11:40.70#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.197.08:11:40.70#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.197.08:11:40.70#ibcon#ireg 17 cls_cnt 0 2006.197.08:11:40.70#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.197.08:11:40.70#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.197.08:11:40.70#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.197.08:11:40.70#ibcon#enter wrdev, iclass 34, count 0 2006.197.08:11:40.70#ibcon#first serial, iclass 34, count 0 2006.197.08:11:40.70#ibcon#enter sib2, iclass 34, count 0 2006.197.08:11:40.70#ibcon#flushed, iclass 34, count 0 2006.197.08:11:40.70#ibcon#about to write, iclass 34, count 0 2006.197.08:11:40.70#ibcon#wrote, iclass 34, count 0 2006.197.08:11:40.70#ibcon#about to read 3, iclass 34, count 0 2006.197.08:11:40.72#ibcon#read 3, iclass 34, count 0 2006.197.08:11:40.72#ibcon#about to read 4, iclass 34, count 0 2006.197.08:11:40.72#ibcon#read 4, iclass 34, count 0 2006.197.08:11:40.72#ibcon#about to read 5, iclass 34, count 0 2006.197.08:11:40.72#ibcon#read 5, iclass 34, count 0 2006.197.08:11:40.72#ibcon#about to read 6, iclass 34, count 0 2006.197.08:11:40.72#ibcon#read 6, iclass 34, count 0 2006.197.08:11:40.72#ibcon#end of sib2, iclass 34, count 0 2006.197.08:11:40.72#ibcon#*mode == 0, iclass 34, count 0 2006.197.08:11:40.72#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.197.08:11:40.72#ibcon#[28=FRQ=01,632.99\r\n] 2006.197.08:11:40.72#ibcon#*before write, iclass 34, count 0 2006.197.08:11:40.72#ibcon#enter sib2, iclass 34, count 0 2006.197.08:11:40.72#ibcon#flushed, iclass 34, count 0 2006.197.08:11:40.72#ibcon#about to write, iclass 34, count 0 2006.197.08:11:40.72#ibcon#wrote, iclass 34, count 0 2006.197.08:11:40.72#ibcon#about to read 3, iclass 34, count 0 2006.197.08:11:40.76#ibcon#read 3, iclass 34, count 0 2006.197.08:11:40.76#ibcon#about to read 4, iclass 34, count 0 2006.197.08:11:40.76#ibcon#read 4, iclass 34, count 0 2006.197.08:11:40.76#ibcon#about to read 5, iclass 34, count 0 2006.197.08:11:40.76#ibcon#read 5, iclass 34, count 0 2006.197.08:11:40.76#ibcon#about to read 6, iclass 34, count 0 2006.197.08:11:40.76#ibcon#read 6, iclass 34, count 0 2006.197.08:11:40.76#ibcon#end of sib2, iclass 34, count 0 2006.197.08:11:40.76#ibcon#*after write, iclass 34, count 0 2006.197.08:11:40.76#ibcon#*before return 0, iclass 34, count 0 2006.197.08:11:40.76#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.197.08:11:40.76#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.197.08:11:40.76#ibcon#about to clear, iclass 34 cls_cnt 0 2006.197.08:11:40.76#ibcon#cleared, iclass 34 cls_cnt 0 2006.197.08:11:40.76$vc4f8/vb=1,4 2006.197.08:11:40.76#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.197.08:11:40.76#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.197.08:11:40.76#ibcon#ireg 11 cls_cnt 2 2006.197.08:11:40.76#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.197.08:11:40.76#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.197.08:11:40.76#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.197.08:11:40.76#ibcon#enter wrdev, iclass 36, count 2 2006.197.08:11:40.76#ibcon#first serial, iclass 36, count 2 2006.197.08:11:40.76#ibcon#enter sib2, iclass 36, count 2 2006.197.08:11:40.76#ibcon#flushed, iclass 36, count 2 2006.197.08:11:40.76#ibcon#about to write, iclass 36, count 2 2006.197.08:11:40.76#ibcon#wrote, iclass 36, count 2 2006.197.08:11:40.76#ibcon#about to read 3, iclass 36, count 2 2006.197.08:11:40.78#ibcon#read 3, iclass 36, count 2 2006.197.08:11:40.78#ibcon#about to read 4, iclass 36, count 2 2006.197.08:11:40.78#ibcon#read 4, iclass 36, count 2 2006.197.08:11:40.78#ibcon#about to read 5, iclass 36, count 2 2006.197.08:11:40.78#ibcon#read 5, iclass 36, count 2 2006.197.08:11:40.78#ibcon#about to read 6, iclass 36, count 2 2006.197.08:11:40.78#ibcon#read 6, iclass 36, count 2 2006.197.08:11:40.78#ibcon#end of sib2, iclass 36, count 2 2006.197.08:11:40.78#ibcon#*mode == 0, iclass 36, count 2 2006.197.08:11:40.78#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.197.08:11:40.78#ibcon#[27=AT01-04\r\n] 2006.197.08:11:40.78#ibcon#*before write, iclass 36, count 2 2006.197.08:11:40.78#ibcon#enter sib2, iclass 36, count 2 2006.197.08:11:40.78#ibcon#flushed, iclass 36, count 2 2006.197.08:11:40.78#ibcon#about to write, iclass 36, count 2 2006.197.08:11:40.78#ibcon#wrote, iclass 36, count 2 2006.197.08:11:40.78#ibcon#about to read 3, iclass 36, count 2 2006.197.08:11:40.81#ibcon#read 3, iclass 36, count 2 2006.197.08:11:40.81#ibcon#about to read 4, iclass 36, count 2 2006.197.08:11:40.81#ibcon#read 4, iclass 36, count 2 2006.197.08:11:40.81#ibcon#about to read 5, iclass 36, count 2 2006.197.08:11:40.81#ibcon#read 5, iclass 36, count 2 2006.197.08:11:40.81#ibcon#about to read 6, iclass 36, count 2 2006.197.08:11:40.81#ibcon#read 6, iclass 36, count 2 2006.197.08:11:40.81#ibcon#end of sib2, iclass 36, count 2 2006.197.08:11:40.81#ibcon#*after write, iclass 36, count 2 2006.197.08:11:40.81#ibcon#*before return 0, iclass 36, count 2 2006.197.08:11:40.81#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.197.08:11:40.81#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.197.08:11:40.81#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.197.08:11:40.81#ibcon#ireg 7 cls_cnt 0 2006.197.08:11:40.81#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.197.08:11:40.93#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.197.08:11:40.93#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.197.08:11:40.93#ibcon#enter wrdev, iclass 36, count 0 2006.197.08:11:40.93#ibcon#first serial, iclass 36, count 0 2006.197.08:11:40.93#ibcon#enter sib2, iclass 36, count 0 2006.197.08:11:40.93#ibcon#flushed, iclass 36, count 0 2006.197.08:11:40.93#ibcon#about to write, iclass 36, count 0 2006.197.08:11:40.93#ibcon#wrote, iclass 36, count 0 2006.197.08:11:40.93#ibcon#about to read 3, iclass 36, count 0 2006.197.08:11:40.95#ibcon#read 3, iclass 36, count 0 2006.197.08:11:40.95#ibcon#about to read 4, iclass 36, count 0 2006.197.08:11:40.95#ibcon#read 4, iclass 36, count 0 2006.197.08:11:40.95#ibcon#about to read 5, iclass 36, count 0 2006.197.08:11:40.95#ibcon#read 5, iclass 36, count 0 2006.197.08:11:40.95#ibcon#about to read 6, iclass 36, count 0 2006.197.08:11:40.95#ibcon#read 6, iclass 36, count 0 2006.197.08:11:40.95#ibcon#end of sib2, iclass 36, count 0 2006.197.08:11:40.95#ibcon#*mode == 0, iclass 36, count 0 2006.197.08:11:40.95#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.197.08:11:40.95#ibcon#[27=USB\r\n] 2006.197.08:11:40.95#ibcon#*before write, iclass 36, count 0 2006.197.08:11:40.95#ibcon#enter sib2, iclass 36, count 0 2006.197.08:11:40.95#ibcon#flushed, iclass 36, count 0 2006.197.08:11:40.95#ibcon#about to write, iclass 36, count 0 2006.197.08:11:40.95#ibcon#wrote, iclass 36, count 0 2006.197.08:11:40.95#ibcon#about to read 3, iclass 36, count 0 2006.197.08:11:40.98#ibcon#read 3, iclass 36, count 0 2006.197.08:11:40.98#ibcon#about to read 4, iclass 36, count 0 2006.197.08:11:40.98#ibcon#read 4, iclass 36, count 0 2006.197.08:11:40.98#ibcon#about to read 5, iclass 36, count 0 2006.197.08:11:40.98#ibcon#read 5, iclass 36, count 0 2006.197.08:11:40.98#ibcon#about to read 6, iclass 36, count 0 2006.197.08:11:40.98#ibcon#read 6, iclass 36, count 0 2006.197.08:11:40.98#ibcon#end of sib2, iclass 36, count 0 2006.197.08:11:40.98#ibcon#*after write, iclass 36, count 0 2006.197.08:11:40.98#ibcon#*before return 0, iclass 36, count 0 2006.197.08:11:40.98#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.197.08:11:40.98#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.197.08:11:40.98#ibcon#about to clear, iclass 36 cls_cnt 0 2006.197.08:11:40.98#ibcon#cleared, iclass 36 cls_cnt 0 2006.197.08:11:40.98$vc4f8/vblo=2,640.99 2006.197.08:11:40.98#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.197.08:11:40.98#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.197.08:11:40.98#ibcon#ireg 17 cls_cnt 0 2006.197.08:11:40.98#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.197.08:11:40.98#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.197.08:11:40.98#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.197.08:11:40.98#ibcon#enter wrdev, iclass 38, count 0 2006.197.08:11:40.98#ibcon#first serial, iclass 38, count 0 2006.197.08:11:40.98#ibcon#enter sib2, iclass 38, count 0 2006.197.08:11:40.98#ibcon#flushed, iclass 38, count 0 2006.197.08:11:40.98#ibcon#about to write, iclass 38, count 0 2006.197.08:11:40.98#ibcon#wrote, iclass 38, count 0 2006.197.08:11:40.98#ibcon#about to read 3, iclass 38, count 0 2006.197.08:11:41.00#ibcon#read 3, iclass 38, count 0 2006.197.08:11:41.00#ibcon#about to read 4, iclass 38, count 0 2006.197.08:11:41.00#ibcon#read 4, iclass 38, count 0 2006.197.08:11:41.00#ibcon#about to read 5, iclass 38, count 0 2006.197.08:11:41.00#ibcon#read 5, iclass 38, count 0 2006.197.08:11:41.00#ibcon#about to read 6, iclass 38, count 0 2006.197.08:11:41.00#ibcon#read 6, iclass 38, count 0 2006.197.08:11:41.00#ibcon#end of sib2, iclass 38, count 0 2006.197.08:11:41.00#ibcon#*mode == 0, iclass 38, count 0 2006.197.08:11:41.00#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.197.08:11:41.00#ibcon#[28=FRQ=02,640.99\r\n] 2006.197.08:11:41.00#ibcon#*before write, iclass 38, count 0 2006.197.08:11:41.00#ibcon#enter sib2, iclass 38, count 0 2006.197.08:11:41.00#ibcon#flushed, iclass 38, count 0 2006.197.08:11:41.00#ibcon#about to write, iclass 38, count 0 2006.197.08:11:41.00#ibcon#wrote, iclass 38, count 0 2006.197.08:11:41.00#ibcon#about to read 3, iclass 38, count 0 2006.197.08:11:41.04#ibcon#read 3, iclass 38, count 0 2006.197.08:11:41.04#ibcon#about to read 4, iclass 38, count 0 2006.197.08:11:41.04#ibcon#read 4, iclass 38, count 0 2006.197.08:11:41.04#ibcon#about to read 5, iclass 38, count 0 2006.197.08:11:41.04#ibcon#read 5, iclass 38, count 0 2006.197.08:11:41.04#ibcon#about to read 6, iclass 38, count 0 2006.197.08:11:41.04#ibcon#read 6, iclass 38, count 0 2006.197.08:11:41.04#ibcon#end of sib2, iclass 38, count 0 2006.197.08:11:41.04#ibcon#*after write, iclass 38, count 0 2006.197.08:11:41.04#ibcon#*before return 0, iclass 38, count 0 2006.197.08:11:41.04#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.197.08:11:41.04#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.197.08:11:41.04#ibcon#about to clear, iclass 38 cls_cnt 0 2006.197.08:11:41.04#ibcon#cleared, iclass 38 cls_cnt 0 2006.197.08:11:41.04$vc4f8/vb=2,4 2006.197.08:11:41.04#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.197.08:11:41.04#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.197.08:11:41.04#ibcon#ireg 11 cls_cnt 2 2006.197.08:11:41.04#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.197.08:11:41.10#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.197.08:11:41.10#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.197.08:11:41.10#ibcon#enter wrdev, iclass 40, count 2 2006.197.08:11:41.10#ibcon#first serial, iclass 40, count 2 2006.197.08:11:41.10#ibcon#enter sib2, iclass 40, count 2 2006.197.08:11:41.10#ibcon#flushed, iclass 40, count 2 2006.197.08:11:41.10#ibcon#about to write, iclass 40, count 2 2006.197.08:11:41.10#ibcon#wrote, iclass 40, count 2 2006.197.08:11:41.10#ibcon#about to read 3, iclass 40, count 2 2006.197.08:11:41.12#ibcon#read 3, iclass 40, count 2 2006.197.08:11:41.12#ibcon#about to read 4, iclass 40, count 2 2006.197.08:11:41.12#ibcon#read 4, iclass 40, count 2 2006.197.08:11:41.12#ibcon#about to read 5, iclass 40, count 2 2006.197.08:11:41.12#ibcon#read 5, iclass 40, count 2 2006.197.08:11:41.12#ibcon#about to read 6, iclass 40, count 2 2006.197.08:11:41.12#ibcon#read 6, iclass 40, count 2 2006.197.08:11:41.12#ibcon#end of sib2, iclass 40, count 2 2006.197.08:11:41.12#ibcon#*mode == 0, iclass 40, count 2 2006.197.08:11:41.12#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.197.08:11:41.12#ibcon#[27=AT02-04\r\n] 2006.197.08:11:41.12#ibcon#*before write, iclass 40, count 2 2006.197.08:11:41.12#ibcon#enter sib2, iclass 40, count 2 2006.197.08:11:41.12#ibcon#flushed, iclass 40, count 2 2006.197.08:11:41.12#ibcon#about to write, iclass 40, count 2 2006.197.08:11:41.12#ibcon#wrote, iclass 40, count 2 2006.197.08:11:41.12#ibcon#about to read 3, iclass 40, count 2 2006.197.08:11:41.15#ibcon#read 3, iclass 40, count 2 2006.197.08:11:41.15#ibcon#about to read 4, iclass 40, count 2 2006.197.08:11:41.15#ibcon#read 4, iclass 40, count 2 2006.197.08:11:41.15#ibcon#about to read 5, iclass 40, count 2 2006.197.08:11:41.15#ibcon#read 5, iclass 40, count 2 2006.197.08:11:41.15#ibcon#about to read 6, iclass 40, count 2 2006.197.08:11:41.15#ibcon#read 6, iclass 40, count 2 2006.197.08:11:41.15#ibcon#end of sib2, iclass 40, count 2 2006.197.08:11:41.15#ibcon#*after write, iclass 40, count 2 2006.197.08:11:41.15#ibcon#*before return 0, iclass 40, count 2 2006.197.08:11:41.15#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.197.08:11:41.15#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.197.08:11:41.15#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.197.08:11:41.15#ibcon#ireg 7 cls_cnt 0 2006.197.08:11:41.15#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.197.08:11:41.27#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.197.08:11:41.27#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.197.08:11:41.27#ibcon#enter wrdev, iclass 40, count 0 2006.197.08:11:41.27#ibcon#first serial, iclass 40, count 0 2006.197.08:11:41.27#ibcon#enter sib2, iclass 40, count 0 2006.197.08:11:41.27#ibcon#flushed, iclass 40, count 0 2006.197.08:11:41.27#ibcon#about to write, iclass 40, count 0 2006.197.08:11:41.27#ibcon#wrote, iclass 40, count 0 2006.197.08:11:41.27#ibcon#about to read 3, iclass 40, count 0 2006.197.08:11:41.29#ibcon#read 3, iclass 40, count 0 2006.197.08:11:41.29#ibcon#about to read 4, iclass 40, count 0 2006.197.08:11:41.29#ibcon#read 4, iclass 40, count 0 2006.197.08:11:41.29#ibcon#about to read 5, iclass 40, count 0 2006.197.08:11:41.29#ibcon#read 5, iclass 40, count 0 2006.197.08:11:41.29#ibcon#about to read 6, iclass 40, count 0 2006.197.08:11:41.29#ibcon#read 6, iclass 40, count 0 2006.197.08:11:41.29#ibcon#end of sib2, iclass 40, count 0 2006.197.08:11:41.29#ibcon#*mode == 0, iclass 40, count 0 2006.197.08:11:41.29#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.197.08:11:41.29#ibcon#[27=USB\r\n] 2006.197.08:11:41.29#ibcon#*before write, iclass 40, count 0 2006.197.08:11:41.29#ibcon#enter sib2, iclass 40, count 0 2006.197.08:11:41.29#ibcon#flushed, iclass 40, count 0 2006.197.08:11:41.29#ibcon#about to write, iclass 40, count 0 2006.197.08:11:41.29#ibcon#wrote, iclass 40, count 0 2006.197.08:11:41.29#ibcon#about to read 3, iclass 40, count 0 2006.197.08:11:41.32#ibcon#read 3, iclass 40, count 0 2006.197.08:11:41.32#ibcon#about to read 4, iclass 40, count 0 2006.197.08:11:41.32#ibcon#read 4, iclass 40, count 0 2006.197.08:11:41.32#ibcon#about to read 5, iclass 40, count 0 2006.197.08:11:41.32#ibcon#read 5, iclass 40, count 0 2006.197.08:11:41.32#ibcon#about to read 6, iclass 40, count 0 2006.197.08:11:41.32#ibcon#read 6, iclass 40, count 0 2006.197.08:11:41.32#ibcon#end of sib2, iclass 40, count 0 2006.197.08:11:41.32#ibcon#*after write, iclass 40, count 0 2006.197.08:11:41.32#ibcon#*before return 0, iclass 40, count 0 2006.197.08:11:41.32#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.197.08:11:41.32#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.197.08:11:41.32#ibcon#about to clear, iclass 40 cls_cnt 0 2006.197.08:11:41.32#ibcon#cleared, iclass 40 cls_cnt 0 2006.197.08:11:41.32$vc4f8/vblo=3,656.99 2006.197.08:11:41.32#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.197.08:11:41.32#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.197.08:11:41.32#ibcon#ireg 17 cls_cnt 0 2006.197.08:11:41.32#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.197.08:11:41.32#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.197.08:11:41.32#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.197.08:11:41.32#ibcon#enter wrdev, iclass 4, count 0 2006.197.08:11:41.32#ibcon#first serial, iclass 4, count 0 2006.197.08:11:41.32#ibcon#enter sib2, iclass 4, count 0 2006.197.08:11:41.32#ibcon#flushed, iclass 4, count 0 2006.197.08:11:41.32#ibcon#about to write, iclass 4, count 0 2006.197.08:11:41.32#ibcon#wrote, iclass 4, count 0 2006.197.08:11:41.32#ibcon#about to read 3, iclass 4, count 0 2006.197.08:11:41.34#ibcon#read 3, iclass 4, count 0 2006.197.08:11:41.34#ibcon#about to read 4, iclass 4, count 0 2006.197.08:11:41.34#ibcon#read 4, iclass 4, count 0 2006.197.08:11:41.34#ibcon#about to read 5, iclass 4, count 0 2006.197.08:11:41.34#ibcon#read 5, iclass 4, count 0 2006.197.08:11:41.34#ibcon#about to read 6, iclass 4, count 0 2006.197.08:11:41.34#ibcon#read 6, iclass 4, count 0 2006.197.08:11:41.34#ibcon#end of sib2, iclass 4, count 0 2006.197.08:11:41.34#ibcon#*mode == 0, iclass 4, count 0 2006.197.08:11:41.34#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.197.08:11:41.34#ibcon#[28=FRQ=03,656.99\r\n] 2006.197.08:11:41.34#ibcon#*before write, iclass 4, count 0 2006.197.08:11:41.34#ibcon#enter sib2, iclass 4, count 0 2006.197.08:11:41.34#ibcon#flushed, iclass 4, count 0 2006.197.08:11:41.34#ibcon#about to write, iclass 4, count 0 2006.197.08:11:41.34#ibcon#wrote, iclass 4, count 0 2006.197.08:11:41.34#ibcon#about to read 3, iclass 4, count 0 2006.197.08:11:41.38#ibcon#read 3, iclass 4, count 0 2006.197.08:11:41.38#ibcon#about to read 4, iclass 4, count 0 2006.197.08:11:41.38#ibcon#read 4, iclass 4, count 0 2006.197.08:11:41.38#ibcon#about to read 5, iclass 4, count 0 2006.197.08:11:41.38#ibcon#read 5, iclass 4, count 0 2006.197.08:11:41.38#ibcon#about to read 6, iclass 4, count 0 2006.197.08:11:41.38#ibcon#read 6, iclass 4, count 0 2006.197.08:11:41.38#ibcon#end of sib2, iclass 4, count 0 2006.197.08:11:41.38#ibcon#*after write, iclass 4, count 0 2006.197.08:11:41.38#ibcon#*before return 0, iclass 4, count 0 2006.197.08:11:41.38#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.197.08:11:41.38#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.197.08:11:41.38#ibcon#about to clear, iclass 4 cls_cnt 0 2006.197.08:11:41.38#ibcon#cleared, iclass 4 cls_cnt 0 2006.197.08:11:41.38$vc4f8/vb=3,4 2006.197.08:11:41.38#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.197.08:11:41.38#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.197.08:11:41.38#ibcon#ireg 11 cls_cnt 2 2006.197.08:11:41.38#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.197.08:11:41.44#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.197.08:11:41.44#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.197.08:11:41.44#ibcon#enter wrdev, iclass 6, count 2 2006.197.08:11:41.44#ibcon#first serial, iclass 6, count 2 2006.197.08:11:41.44#ibcon#enter sib2, iclass 6, count 2 2006.197.08:11:41.44#ibcon#flushed, iclass 6, count 2 2006.197.08:11:41.44#ibcon#about to write, iclass 6, count 2 2006.197.08:11:41.44#ibcon#wrote, iclass 6, count 2 2006.197.08:11:41.44#ibcon#about to read 3, iclass 6, count 2 2006.197.08:11:41.46#ibcon#read 3, iclass 6, count 2 2006.197.08:11:41.46#ibcon#about to read 4, iclass 6, count 2 2006.197.08:11:41.46#ibcon#read 4, iclass 6, count 2 2006.197.08:11:41.46#ibcon#about to read 5, iclass 6, count 2 2006.197.08:11:41.46#ibcon#read 5, iclass 6, count 2 2006.197.08:11:41.46#ibcon#about to read 6, iclass 6, count 2 2006.197.08:11:41.46#ibcon#read 6, iclass 6, count 2 2006.197.08:11:41.46#ibcon#end of sib2, iclass 6, count 2 2006.197.08:11:41.46#ibcon#*mode == 0, iclass 6, count 2 2006.197.08:11:41.46#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.197.08:11:41.46#ibcon#[27=AT03-04\r\n] 2006.197.08:11:41.46#ibcon#*before write, iclass 6, count 2 2006.197.08:11:41.46#ibcon#enter sib2, iclass 6, count 2 2006.197.08:11:41.46#ibcon#flushed, iclass 6, count 2 2006.197.08:11:41.46#ibcon#about to write, iclass 6, count 2 2006.197.08:11:41.46#ibcon#wrote, iclass 6, count 2 2006.197.08:11:41.46#ibcon#about to read 3, iclass 6, count 2 2006.197.08:11:41.49#ibcon#read 3, iclass 6, count 2 2006.197.08:11:41.49#ibcon#about to read 4, iclass 6, count 2 2006.197.08:11:41.49#ibcon#read 4, iclass 6, count 2 2006.197.08:11:41.49#ibcon#about to read 5, iclass 6, count 2 2006.197.08:11:41.49#ibcon#read 5, iclass 6, count 2 2006.197.08:11:41.49#ibcon#about to read 6, iclass 6, count 2 2006.197.08:11:41.49#ibcon#read 6, iclass 6, count 2 2006.197.08:11:41.49#ibcon#end of sib2, iclass 6, count 2 2006.197.08:11:41.49#ibcon#*after write, iclass 6, count 2 2006.197.08:11:41.49#ibcon#*before return 0, iclass 6, count 2 2006.197.08:11:41.49#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.197.08:11:41.49#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.197.08:11:41.49#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.197.08:11:41.49#ibcon#ireg 7 cls_cnt 0 2006.197.08:11:41.49#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.197.08:11:41.61#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.197.08:11:41.61#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.197.08:11:41.61#ibcon#enter wrdev, iclass 6, count 0 2006.197.08:11:41.61#ibcon#first serial, iclass 6, count 0 2006.197.08:11:41.61#ibcon#enter sib2, iclass 6, count 0 2006.197.08:11:41.61#ibcon#flushed, iclass 6, count 0 2006.197.08:11:41.61#ibcon#about to write, iclass 6, count 0 2006.197.08:11:41.61#ibcon#wrote, iclass 6, count 0 2006.197.08:11:41.61#ibcon#about to read 3, iclass 6, count 0 2006.197.08:11:41.63#ibcon#read 3, iclass 6, count 0 2006.197.08:11:41.63#ibcon#about to read 4, iclass 6, count 0 2006.197.08:11:41.63#ibcon#read 4, iclass 6, count 0 2006.197.08:11:41.63#ibcon#about to read 5, iclass 6, count 0 2006.197.08:11:41.63#ibcon#read 5, iclass 6, count 0 2006.197.08:11:41.63#ibcon#about to read 6, iclass 6, count 0 2006.197.08:11:41.63#ibcon#read 6, iclass 6, count 0 2006.197.08:11:41.63#ibcon#end of sib2, iclass 6, count 0 2006.197.08:11:41.63#ibcon#*mode == 0, iclass 6, count 0 2006.197.08:11:41.63#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.197.08:11:41.63#ibcon#[27=USB\r\n] 2006.197.08:11:41.63#ibcon#*before write, iclass 6, count 0 2006.197.08:11:41.63#ibcon#enter sib2, iclass 6, count 0 2006.197.08:11:41.63#ibcon#flushed, iclass 6, count 0 2006.197.08:11:41.63#ibcon#about to write, iclass 6, count 0 2006.197.08:11:41.63#ibcon#wrote, iclass 6, count 0 2006.197.08:11:41.63#ibcon#about to read 3, iclass 6, count 0 2006.197.08:11:41.66#ibcon#read 3, iclass 6, count 0 2006.197.08:11:41.66#ibcon#about to read 4, iclass 6, count 0 2006.197.08:11:41.66#ibcon#read 4, iclass 6, count 0 2006.197.08:11:41.66#ibcon#about to read 5, iclass 6, count 0 2006.197.08:11:41.66#ibcon#read 5, iclass 6, count 0 2006.197.08:11:41.66#ibcon#about to read 6, iclass 6, count 0 2006.197.08:11:41.66#ibcon#read 6, iclass 6, count 0 2006.197.08:11:41.66#ibcon#end of sib2, iclass 6, count 0 2006.197.08:11:41.66#ibcon#*after write, iclass 6, count 0 2006.197.08:11:41.66#ibcon#*before return 0, iclass 6, count 0 2006.197.08:11:41.66#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.197.08:11:41.66#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.197.08:11:41.66#ibcon#about to clear, iclass 6 cls_cnt 0 2006.197.08:11:41.66#ibcon#cleared, iclass 6 cls_cnt 0 2006.197.08:11:41.66$vc4f8/vblo=4,712.99 2006.197.08:11:41.66#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.197.08:11:41.66#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.197.08:11:41.66#ibcon#ireg 17 cls_cnt 0 2006.197.08:11:41.66#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.197.08:11:41.66#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.197.08:11:41.66#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.197.08:11:41.66#ibcon#enter wrdev, iclass 10, count 0 2006.197.08:11:41.66#ibcon#first serial, iclass 10, count 0 2006.197.08:11:41.66#ibcon#enter sib2, iclass 10, count 0 2006.197.08:11:41.66#ibcon#flushed, iclass 10, count 0 2006.197.08:11:41.66#ibcon#about to write, iclass 10, count 0 2006.197.08:11:41.66#ibcon#wrote, iclass 10, count 0 2006.197.08:11:41.66#ibcon#about to read 3, iclass 10, count 0 2006.197.08:11:41.68#ibcon#read 3, iclass 10, count 0 2006.197.08:11:41.68#ibcon#about to read 4, iclass 10, count 0 2006.197.08:11:41.68#ibcon#read 4, iclass 10, count 0 2006.197.08:11:41.68#ibcon#about to read 5, iclass 10, count 0 2006.197.08:11:41.68#ibcon#read 5, iclass 10, count 0 2006.197.08:11:41.68#ibcon#about to read 6, iclass 10, count 0 2006.197.08:11:41.68#ibcon#read 6, iclass 10, count 0 2006.197.08:11:41.68#ibcon#end of sib2, iclass 10, count 0 2006.197.08:11:41.68#ibcon#*mode == 0, iclass 10, count 0 2006.197.08:11:41.68#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.197.08:11:41.68#ibcon#[28=FRQ=04,712.99\r\n] 2006.197.08:11:41.68#ibcon#*before write, iclass 10, count 0 2006.197.08:11:41.68#ibcon#enter sib2, iclass 10, count 0 2006.197.08:11:41.68#ibcon#flushed, iclass 10, count 0 2006.197.08:11:41.68#ibcon#about to write, iclass 10, count 0 2006.197.08:11:41.68#ibcon#wrote, iclass 10, count 0 2006.197.08:11:41.68#ibcon#about to read 3, iclass 10, count 0 2006.197.08:11:41.72#ibcon#read 3, iclass 10, count 0 2006.197.08:11:41.72#ibcon#about to read 4, iclass 10, count 0 2006.197.08:11:41.72#ibcon#read 4, iclass 10, count 0 2006.197.08:11:41.72#ibcon#about to read 5, iclass 10, count 0 2006.197.08:11:41.72#ibcon#read 5, iclass 10, count 0 2006.197.08:11:41.72#ibcon#about to read 6, iclass 10, count 0 2006.197.08:11:41.72#ibcon#read 6, iclass 10, count 0 2006.197.08:11:41.72#ibcon#end of sib2, iclass 10, count 0 2006.197.08:11:41.72#ibcon#*after write, iclass 10, count 0 2006.197.08:11:41.72#ibcon#*before return 0, iclass 10, count 0 2006.197.08:11:41.72#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.197.08:11:41.72#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.197.08:11:41.72#ibcon#about to clear, iclass 10 cls_cnt 0 2006.197.08:11:41.72#ibcon#cleared, iclass 10 cls_cnt 0 2006.197.08:11:41.72$vc4f8/vb=4,4 2006.197.08:11:41.72#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.197.08:11:41.72#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.197.08:11:41.72#ibcon#ireg 11 cls_cnt 2 2006.197.08:11:41.72#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.197.08:11:41.78#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.197.08:11:41.78#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.197.08:11:41.78#ibcon#enter wrdev, iclass 12, count 2 2006.197.08:11:41.78#ibcon#first serial, iclass 12, count 2 2006.197.08:11:41.78#ibcon#enter sib2, iclass 12, count 2 2006.197.08:11:41.78#ibcon#flushed, iclass 12, count 2 2006.197.08:11:41.78#ibcon#about to write, iclass 12, count 2 2006.197.08:11:41.78#ibcon#wrote, iclass 12, count 2 2006.197.08:11:41.78#ibcon#about to read 3, iclass 12, count 2 2006.197.08:11:41.80#ibcon#read 3, iclass 12, count 2 2006.197.08:11:41.80#ibcon#about to read 4, iclass 12, count 2 2006.197.08:11:41.80#ibcon#read 4, iclass 12, count 2 2006.197.08:11:41.80#ibcon#about to read 5, iclass 12, count 2 2006.197.08:11:41.80#ibcon#read 5, iclass 12, count 2 2006.197.08:11:41.80#ibcon#about to read 6, iclass 12, count 2 2006.197.08:11:41.80#ibcon#read 6, iclass 12, count 2 2006.197.08:11:41.80#ibcon#end of sib2, iclass 12, count 2 2006.197.08:11:41.80#ibcon#*mode == 0, iclass 12, count 2 2006.197.08:11:41.80#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.197.08:11:41.80#ibcon#[27=AT04-04\r\n] 2006.197.08:11:41.80#ibcon#*before write, iclass 12, count 2 2006.197.08:11:41.80#ibcon#enter sib2, iclass 12, count 2 2006.197.08:11:41.80#ibcon#flushed, iclass 12, count 2 2006.197.08:11:41.80#ibcon#about to write, iclass 12, count 2 2006.197.08:11:41.80#ibcon#wrote, iclass 12, count 2 2006.197.08:11:41.80#ibcon#about to read 3, iclass 12, count 2 2006.197.08:11:41.83#ibcon#read 3, iclass 12, count 2 2006.197.08:11:41.83#ibcon#about to read 4, iclass 12, count 2 2006.197.08:11:41.83#ibcon#read 4, iclass 12, count 2 2006.197.08:11:41.83#ibcon#about to read 5, iclass 12, count 2 2006.197.08:11:41.83#ibcon#read 5, iclass 12, count 2 2006.197.08:11:41.83#ibcon#about to read 6, iclass 12, count 2 2006.197.08:11:41.83#ibcon#read 6, iclass 12, count 2 2006.197.08:11:41.83#ibcon#end of sib2, iclass 12, count 2 2006.197.08:11:41.83#ibcon#*after write, iclass 12, count 2 2006.197.08:11:41.83#ibcon#*before return 0, iclass 12, count 2 2006.197.08:11:41.83#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.197.08:11:41.83#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.197.08:11:41.83#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.197.08:11:41.83#ibcon#ireg 7 cls_cnt 0 2006.197.08:11:41.83#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.197.08:11:41.95#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.197.08:11:41.95#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.197.08:11:41.95#ibcon#enter wrdev, iclass 12, count 0 2006.197.08:11:41.95#ibcon#first serial, iclass 12, count 0 2006.197.08:11:41.95#ibcon#enter sib2, iclass 12, count 0 2006.197.08:11:41.95#ibcon#flushed, iclass 12, count 0 2006.197.08:11:41.95#ibcon#about to write, iclass 12, count 0 2006.197.08:11:41.95#ibcon#wrote, iclass 12, count 0 2006.197.08:11:41.95#ibcon#about to read 3, iclass 12, count 0 2006.197.08:11:41.97#ibcon#read 3, iclass 12, count 0 2006.197.08:11:41.97#ibcon#about to read 4, iclass 12, count 0 2006.197.08:11:41.97#ibcon#read 4, iclass 12, count 0 2006.197.08:11:41.97#ibcon#about to read 5, iclass 12, count 0 2006.197.08:11:41.97#ibcon#read 5, iclass 12, count 0 2006.197.08:11:41.97#ibcon#about to read 6, iclass 12, count 0 2006.197.08:11:41.97#ibcon#read 6, iclass 12, count 0 2006.197.08:11:41.97#ibcon#end of sib2, iclass 12, count 0 2006.197.08:11:41.97#ibcon#*mode == 0, iclass 12, count 0 2006.197.08:11:41.97#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.197.08:11:41.97#ibcon#[27=USB\r\n] 2006.197.08:11:41.97#ibcon#*before write, iclass 12, count 0 2006.197.08:11:41.97#ibcon#enter sib2, iclass 12, count 0 2006.197.08:11:41.97#ibcon#flushed, iclass 12, count 0 2006.197.08:11:41.97#ibcon#about to write, iclass 12, count 0 2006.197.08:11:41.97#ibcon#wrote, iclass 12, count 0 2006.197.08:11:41.97#ibcon#about to read 3, iclass 12, count 0 2006.197.08:11:42.00#ibcon#read 3, iclass 12, count 0 2006.197.08:11:42.00#ibcon#about to read 4, iclass 12, count 0 2006.197.08:11:42.00#ibcon#read 4, iclass 12, count 0 2006.197.08:11:42.00#ibcon#about to read 5, iclass 12, count 0 2006.197.08:11:42.00#ibcon#read 5, iclass 12, count 0 2006.197.08:11:42.00#ibcon#about to read 6, iclass 12, count 0 2006.197.08:11:42.00#ibcon#read 6, iclass 12, count 0 2006.197.08:11:42.00#ibcon#end of sib2, iclass 12, count 0 2006.197.08:11:42.00#ibcon#*after write, iclass 12, count 0 2006.197.08:11:42.00#ibcon#*before return 0, iclass 12, count 0 2006.197.08:11:42.00#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.197.08:11:42.00#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.197.08:11:42.00#ibcon#about to clear, iclass 12 cls_cnt 0 2006.197.08:11:42.00#ibcon#cleared, iclass 12 cls_cnt 0 2006.197.08:11:42.00$vc4f8/vblo=5,744.99 2006.197.08:11:42.00#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.197.08:11:42.00#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.197.08:11:42.00#ibcon#ireg 17 cls_cnt 0 2006.197.08:11:42.00#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.197.08:11:42.00#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.197.08:11:42.00#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.197.08:11:42.00#ibcon#enter wrdev, iclass 14, count 0 2006.197.08:11:42.00#ibcon#first serial, iclass 14, count 0 2006.197.08:11:42.00#ibcon#enter sib2, iclass 14, count 0 2006.197.08:11:42.00#ibcon#flushed, iclass 14, count 0 2006.197.08:11:42.00#ibcon#about to write, iclass 14, count 0 2006.197.08:11:42.00#ibcon#wrote, iclass 14, count 0 2006.197.08:11:42.00#ibcon#about to read 3, iclass 14, count 0 2006.197.08:11:42.02#ibcon#read 3, iclass 14, count 0 2006.197.08:11:42.02#ibcon#about to read 4, iclass 14, count 0 2006.197.08:11:42.02#ibcon#read 4, iclass 14, count 0 2006.197.08:11:42.02#ibcon#about to read 5, iclass 14, count 0 2006.197.08:11:42.02#ibcon#read 5, iclass 14, count 0 2006.197.08:11:42.02#ibcon#about to read 6, iclass 14, count 0 2006.197.08:11:42.02#ibcon#read 6, iclass 14, count 0 2006.197.08:11:42.02#ibcon#end of sib2, iclass 14, count 0 2006.197.08:11:42.02#ibcon#*mode == 0, iclass 14, count 0 2006.197.08:11:42.02#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.197.08:11:42.02#ibcon#[28=FRQ=05,744.99\r\n] 2006.197.08:11:42.02#ibcon#*before write, iclass 14, count 0 2006.197.08:11:42.02#ibcon#enter sib2, iclass 14, count 0 2006.197.08:11:42.02#ibcon#flushed, iclass 14, count 0 2006.197.08:11:42.02#ibcon#about to write, iclass 14, count 0 2006.197.08:11:42.02#ibcon#wrote, iclass 14, count 0 2006.197.08:11:42.02#ibcon#about to read 3, iclass 14, count 0 2006.197.08:11:42.06#ibcon#read 3, iclass 14, count 0 2006.197.08:11:42.06#ibcon#about to read 4, iclass 14, count 0 2006.197.08:11:42.06#ibcon#read 4, iclass 14, count 0 2006.197.08:11:42.06#ibcon#about to read 5, iclass 14, count 0 2006.197.08:11:42.06#ibcon#read 5, iclass 14, count 0 2006.197.08:11:42.06#ibcon#about to read 6, iclass 14, count 0 2006.197.08:11:42.06#ibcon#read 6, iclass 14, count 0 2006.197.08:11:42.06#ibcon#end of sib2, iclass 14, count 0 2006.197.08:11:42.06#ibcon#*after write, iclass 14, count 0 2006.197.08:11:42.06#ibcon#*before return 0, iclass 14, count 0 2006.197.08:11:42.06#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.197.08:11:42.06#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.197.08:11:42.06#ibcon#about to clear, iclass 14 cls_cnt 0 2006.197.08:11:42.06#ibcon#cleared, iclass 14 cls_cnt 0 2006.197.08:11:42.06$vc4f8/vb=5,4 2006.197.08:11:42.06#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.197.08:11:42.06#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.197.08:11:42.06#ibcon#ireg 11 cls_cnt 2 2006.197.08:11:42.06#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.197.08:11:42.12#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.197.08:11:42.12#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.197.08:11:42.12#ibcon#enter wrdev, iclass 16, count 2 2006.197.08:11:42.12#ibcon#first serial, iclass 16, count 2 2006.197.08:11:42.12#ibcon#enter sib2, iclass 16, count 2 2006.197.08:11:42.12#ibcon#flushed, iclass 16, count 2 2006.197.08:11:42.12#ibcon#about to write, iclass 16, count 2 2006.197.08:11:42.12#ibcon#wrote, iclass 16, count 2 2006.197.08:11:42.12#ibcon#about to read 3, iclass 16, count 2 2006.197.08:11:42.14#ibcon#read 3, iclass 16, count 2 2006.197.08:11:42.14#ibcon#about to read 4, iclass 16, count 2 2006.197.08:11:42.14#ibcon#read 4, iclass 16, count 2 2006.197.08:11:42.14#ibcon#about to read 5, iclass 16, count 2 2006.197.08:11:42.14#ibcon#read 5, iclass 16, count 2 2006.197.08:11:42.14#ibcon#about to read 6, iclass 16, count 2 2006.197.08:11:42.14#ibcon#read 6, iclass 16, count 2 2006.197.08:11:42.14#ibcon#end of sib2, iclass 16, count 2 2006.197.08:11:42.14#ibcon#*mode == 0, iclass 16, count 2 2006.197.08:11:42.14#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.197.08:11:42.14#ibcon#[27=AT05-04\r\n] 2006.197.08:11:42.14#ibcon#*before write, iclass 16, count 2 2006.197.08:11:42.14#ibcon#enter sib2, iclass 16, count 2 2006.197.08:11:42.14#ibcon#flushed, iclass 16, count 2 2006.197.08:11:42.14#ibcon#about to write, iclass 16, count 2 2006.197.08:11:42.14#ibcon#wrote, iclass 16, count 2 2006.197.08:11:42.14#ibcon#about to read 3, iclass 16, count 2 2006.197.08:11:42.17#ibcon#read 3, iclass 16, count 2 2006.197.08:11:42.17#ibcon#about to read 4, iclass 16, count 2 2006.197.08:11:42.17#ibcon#read 4, iclass 16, count 2 2006.197.08:11:42.17#ibcon#about to read 5, iclass 16, count 2 2006.197.08:11:42.17#ibcon#read 5, iclass 16, count 2 2006.197.08:11:42.17#ibcon#about to read 6, iclass 16, count 2 2006.197.08:11:42.17#ibcon#read 6, iclass 16, count 2 2006.197.08:11:42.17#ibcon#end of sib2, iclass 16, count 2 2006.197.08:11:42.17#ibcon#*after write, iclass 16, count 2 2006.197.08:11:42.17#ibcon#*before return 0, iclass 16, count 2 2006.197.08:11:42.17#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.197.08:11:42.17#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.197.08:11:42.17#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.197.08:11:42.17#ibcon#ireg 7 cls_cnt 0 2006.197.08:11:42.17#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.197.08:11:42.28#abcon#<5=/05 3.2 6.2 25.63 961002.8\r\n> 2006.197.08:11:42.29#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.197.08:11:42.29#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.197.08:11:42.29#ibcon#enter wrdev, iclass 16, count 0 2006.197.08:11:42.29#ibcon#first serial, iclass 16, count 0 2006.197.08:11:42.29#ibcon#enter sib2, iclass 16, count 0 2006.197.08:11:42.29#ibcon#flushed, iclass 16, count 0 2006.197.08:11:42.29#ibcon#about to write, iclass 16, count 0 2006.197.08:11:42.29#ibcon#wrote, iclass 16, count 0 2006.197.08:11:42.29#ibcon#about to read 3, iclass 16, count 0 2006.197.08:11:42.30#abcon#{5=INTERFACE CLEAR} 2006.197.08:11:42.31#ibcon#read 3, iclass 16, count 0 2006.197.08:11:42.31#ibcon#about to read 4, iclass 16, count 0 2006.197.08:11:42.31#ibcon#read 4, iclass 16, count 0 2006.197.08:11:42.31#ibcon#about to read 5, iclass 16, count 0 2006.197.08:11:42.31#ibcon#read 5, iclass 16, count 0 2006.197.08:11:42.31#ibcon#about to read 6, iclass 16, count 0 2006.197.08:11:42.31#ibcon#read 6, iclass 16, count 0 2006.197.08:11:42.31#ibcon#end of sib2, iclass 16, count 0 2006.197.08:11:42.31#ibcon#*mode == 0, iclass 16, count 0 2006.197.08:11:42.31#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.197.08:11:42.31#ibcon#[27=USB\r\n] 2006.197.08:11:42.31#ibcon#*before write, iclass 16, count 0 2006.197.08:11:42.31#ibcon#enter sib2, iclass 16, count 0 2006.197.08:11:42.31#ibcon#flushed, iclass 16, count 0 2006.197.08:11:42.31#ibcon#about to write, iclass 16, count 0 2006.197.08:11:42.31#ibcon#wrote, iclass 16, count 0 2006.197.08:11:42.31#ibcon#about to read 3, iclass 16, count 0 2006.197.08:11:42.34#ibcon#read 3, iclass 16, count 0 2006.197.08:11:42.34#ibcon#about to read 4, iclass 16, count 0 2006.197.08:11:42.34#ibcon#read 4, iclass 16, count 0 2006.197.08:11:42.34#ibcon#about to read 5, iclass 16, count 0 2006.197.08:11:42.34#ibcon#read 5, iclass 16, count 0 2006.197.08:11:42.34#ibcon#about to read 6, iclass 16, count 0 2006.197.08:11:42.34#ibcon#read 6, iclass 16, count 0 2006.197.08:11:42.34#ibcon#end of sib2, iclass 16, count 0 2006.197.08:11:42.34#ibcon#*after write, iclass 16, count 0 2006.197.08:11:42.34#ibcon#*before return 0, iclass 16, count 0 2006.197.08:11:42.34#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.197.08:11:42.34#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.197.08:11:42.34#ibcon#about to clear, iclass 16 cls_cnt 0 2006.197.08:11:42.34#ibcon#cleared, iclass 16 cls_cnt 0 2006.197.08:11:42.34$vc4f8/vblo=6,752.99 2006.197.08:11:42.34#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.197.08:11:42.34#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.197.08:11:42.34#ibcon#ireg 17 cls_cnt 0 2006.197.08:11:42.34#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.197.08:11:42.34#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.197.08:11:42.34#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.197.08:11:42.34#ibcon#enter wrdev, iclass 21, count 0 2006.197.08:11:42.34#ibcon#first serial, iclass 21, count 0 2006.197.08:11:42.34#ibcon#enter sib2, iclass 21, count 0 2006.197.08:11:42.34#ibcon#flushed, iclass 21, count 0 2006.197.08:11:42.34#ibcon#about to write, iclass 21, count 0 2006.197.08:11:42.34#ibcon#wrote, iclass 21, count 0 2006.197.08:11:42.34#ibcon#about to read 3, iclass 21, count 0 2006.197.08:11:42.36#ibcon#read 3, iclass 21, count 0 2006.197.08:11:42.36#ibcon#about to read 4, iclass 21, count 0 2006.197.08:11:42.36#ibcon#read 4, iclass 21, count 0 2006.197.08:11:42.36#ibcon#about to read 5, iclass 21, count 0 2006.197.08:11:42.36#ibcon#read 5, iclass 21, count 0 2006.197.08:11:42.36#ibcon#about to read 6, iclass 21, count 0 2006.197.08:11:42.36#ibcon#read 6, iclass 21, count 0 2006.197.08:11:42.36#ibcon#end of sib2, iclass 21, count 0 2006.197.08:11:42.36#ibcon#*mode == 0, iclass 21, count 0 2006.197.08:11:42.36#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.197.08:11:42.36#ibcon#[28=FRQ=06,752.99\r\n] 2006.197.08:11:42.36#ibcon#*before write, iclass 21, count 0 2006.197.08:11:42.36#ibcon#enter sib2, iclass 21, count 0 2006.197.08:11:42.36#ibcon#flushed, iclass 21, count 0 2006.197.08:11:42.36#ibcon#about to write, iclass 21, count 0 2006.197.08:11:42.36#ibcon#wrote, iclass 21, count 0 2006.197.08:11:42.36#ibcon#about to read 3, iclass 21, count 0 2006.197.08:11:42.36#abcon#[5=S1D000X0/0*\r\n] 2006.197.08:11:42.40#ibcon#read 3, iclass 21, count 0 2006.197.08:11:42.40#ibcon#about to read 4, iclass 21, count 0 2006.197.08:11:42.40#ibcon#read 4, iclass 21, count 0 2006.197.08:11:42.40#ibcon#about to read 5, iclass 21, count 0 2006.197.08:11:42.40#ibcon#read 5, iclass 21, count 0 2006.197.08:11:42.40#ibcon#about to read 6, iclass 21, count 0 2006.197.08:11:42.40#ibcon#read 6, iclass 21, count 0 2006.197.08:11:42.40#ibcon#end of sib2, iclass 21, count 0 2006.197.08:11:42.40#ibcon#*after write, iclass 21, count 0 2006.197.08:11:42.40#ibcon#*before return 0, iclass 21, count 0 2006.197.08:11:42.40#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.197.08:11:42.40#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.197.08:11:42.40#ibcon#about to clear, iclass 21 cls_cnt 0 2006.197.08:11:42.40#ibcon#cleared, iclass 21 cls_cnt 0 2006.197.08:11:42.40$vc4f8/vb=6,4 2006.197.08:11:42.40#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.197.08:11:42.40#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.197.08:11:42.40#ibcon#ireg 11 cls_cnt 2 2006.197.08:11:42.40#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.197.08:11:42.46#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.197.08:11:42.46#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.197.08:11:42.46#ibcon#enter wrdev, iclass 24, count 2 2006.197.08:11:42.46#ibcon#first serial, iclass 24, count 2 2006.197.08:11:42.46#ibcon#enter sib2, iclass 24, count 2 2006.197.08:11:42.46#ibcon#flushed, iclass 24, count 2 2006.197.08:11:42.46#ibcon#about to write, iclass 24, count 2 2006.197.08:11:42.46#ibcon#wrote, iclass 24, count 2 2006.197.08:11:42.46#ibcon#about to read 3, iclass 24, count 2 2006.197.08:11:42.48#ibcon#read 3, iclass 24, count 2 2006.197.08:11:42.48#ibcon#about to read 4, iclass 24, count 2 2006.197.08:11:42.48#ibcon#read 4, iclass 24, count 2 2006.197.08:11:42.48#ibcon#about to read 5, iclass 24, count 2 2006.197.08:11:42.48#ibcon#read 5, iclass 24, count 2 2006.197.08:11:42.48#ibcon#about to read 6, iclass 24, count 2 2006.197.08:11:42.48#ibcon#read 6, iclass 24, count 2 2006.197.08:11:42.48#ibcon#end of sib2, iclass 24, count 2 2006.197.08:11:42.48#ibcon#*mode == 0, iclass 24, count 2 2006.197.08:11:42.48#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.197.08:11:42.48#ibcon#[27=AT06-04\r\n] 2006.197.08:11:42.48#ibcon#*before write, iclass 24, count 2 2006.197.08:11:42.48#ibcon#enter sib2, iclass 24, count 2 2006.197.08:11:42.48#ibcon#flushed, iclass 24, count 2 2006.197.08:11:42.48#ibcon#about to write, iclass 24, count 2 2006.197.08:11:42.48#ibcon#wrote, iclass 24, count 2 2006.197.08:11:42.48#ibcon#about to read 3, iclass 24, count 2 2006.197.08:11:42.51#ibcon#read 3, iclass 24, count 2 2006.197.08:11:42.51#ibcon#about to read 4, iclass 24, count 2 2006.197.08:11:42.51#ibcon#read 4, iclass 24, count 2 2006.197.08:11:42.51#ibcon#about to read 5, iclass 24, count 2 2006.197.08:11:42.51#ibcon#read 5, iclass 24, count 2 2006.197.08:11:42.51#ibcon#about to read 6, iclass 24, count 2 2006.197.08:11:42.51#ibcon#read 6, iclass 24, count 2 2006.197.08:11:42.51#ibcon#end of sib2, iclass 24, count 2 2006.197.08:11:42.51#ibcon#*after write, iclass 24, count 2 2006.197.08:11:42.51#ibcon#*before return 0, iclass 24, count 2 2006.197.08:11:42.51#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.197.08:11:42.51#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.197.08:11:42.51#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.197.08:11:42.51#ibcon#ireg 7 cls_cnt 0 2006.197.08:11:42.51#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.197.08:11:42.63#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.197.08:11:42.63#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.197.08:11:42.63#ibcon#enter wrdev, iclass 24, count 0 2006.197.08:11:42.63#ibcon#first serial, iclass 24, count 0 2006.197.08:11:42.63#ibcon#enter sib2, iclass 24, count 0 2006.197.08:11:42.63#ibcon#flushed, iclass 24, count 0 2006.197.08:11:42.63#ibcon#about to write, iclass 24, count 0 2006.197.08:11:42.63#ibcon#wrote, iclass 24, count 0 2006.197.08:11:42.63#ibcon#about to read 3, iclass 24, count 0 2006.197.08:11:42.65#ibcon#read 3, iclass 24, count 0 2006.197.08:11:42.65#ibcon#about to read 4, iclass 24, count 0 2006.197.08:11:42.65#ibcon#read 4, iclass 24, count 0 2006.197.08:11:42.65#ibcon#about to read 5, iclass 24, count 0 2006.197.08:11:42.65#ibcon#read 5, iclass 24, count 0 2006.197.08:11:42.65#ibcon#about to read 6, iclass 24, count 0 2006.197.08:11:42.65#ibcon#read 6, iclass 24, count 0 2006.197.08:11:42.65#ibcon#end of sib2, iclass 24, count 0 2006.197.08:11:42.65#ibcon#*mode == 0, iclass 24, count 0 2006.197.08:11:42.65#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.197.08:11:42.65#ibcon#[27=USB\r\n] 2006.197.08:11:42.65#ibcon#*before write, iclass 24, count 0 2006.197.08:11:42.65#ibcon#enter sib2, iclass 24, count 0 2006.197.08:11:42.65#ibcon#flushed, iclass 24, count 0 2006.197.08:11:42.65#ibcon#about to write, iclass 24, count 0 2006.197.08:11:42.65#ibcon#wrote, iclass 24, count 0 2006.197.08:11:42.65#ibcon#about to read 3, iclass 24, count 0 2006.197.08:11:42.68#ibcon#read 3, iclass 24, count 0 2006.197.08:11:42.68#ibcon#about to read 4, iclass 24, count 0 2006.197.08:11:42.68#ibcon#read 4, iclass 24, count 0 2006.197.08:11:42.68#ibcon#about to read 5, iclass 24, count 0 2006.197.08:11:42.68#ibcon#read 5, iclass 24, count 0 2006.197.08:11:42.68#ibcon#about to read 6, iclass 24, count 0 2006.197.08:11:42.68#ibcon#read 6, iclass 24, count 0 2006.197.08:11:42.68#ibcon#end of sib2, iclass 24, count 0 2006.197.08:11:42.68#ibcon#*after write, iclass 24, count 0 2006.197.08:11:42.68#ibcon#*before return 0, iclass 24, count 0 2006.197.08:11:42.68#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.197.08:11:42.68#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.197.08:11:42.68#ibcon#about to clear, iclass 24 cls_cnt 0 2006.197.08:11:42.68#ibcon#cleared, iclass 24 cls_cnt 0 2006.197.08:11:42.68$vc4f8/vabw=wide 2006.197.08:11:42.68#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.197.08:11:42.68#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.197.08:11:42.68#ibcon#ireg 8 cls_cnt 0 2006.197.08:11:42.68#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.197.08:11:42.68#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.197.08:11:42.68#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.197.08:11:42.68#ibcon#enter wrdev, iclass 26, count 0 2006.197.08:11:42.68#ibcon#first serial, iclass 26, count 0 2006.197.08:11:42.68#ibcon#enter sib2, iclass 26, count 0 2006.197.08:11:42.68#ibcon#flushed, iclass 26, count 0 2006.197.08:11:42.68#ibcon#about to write, iclass 26, count 0 2006.197.08:11:42.68#ibcon#wrote, iclass 26, count 0 2006.197.08:11:42.68#ibcon#about to read 3, iclass 26, count 0 2006.197.08:11:42.70#ibcon#read 3, iclass 26, count 0 2006.197.08:11:42.70#ibcon#about to read 4, iclass 26, count 0 2006.197.08:11:42.70#ibcon#read 4, iclass 26, count 0 2006.197.08:11:42.70#ibcon#about to read 5, iclass 26, count 0 2006.197.08:11:42.70#ibcon#read 5, iclass 26, count 0 2006.197.08:11:42.70#ibcon#about to read 6, iclass 26, count 0 2006.197.08:11:42.70#ibcon#read 6, iclass 26, count 0 2006.197.08:11:42.70#ibcon#end of sib2, iclass 26, count 0 2006.197.08:11:42.70#ibcon#*mode == 0, iclass 26, count 0 2006.197.08:11:42.70#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.197.08:11:42.70#ibcon#[25=BW32\r\n] 2006.197.08:11:42.70#ibcon#*before write, iclass 26, count 0 2006.197.08:11:42.70#ibcon#enter sib2, iclass 26, count 0 2006.197.08:11:42.70#ibcon#flushed, iclass 26, count 0 2006.197.08:11:42.70#ibcon#about to write, iclass 26, count 0 2006.197.08:11:42.70#ibcon#wrote, iclass 26, count 0 2006.197.08:11:42.70#ibcon#about to read 3, iclass 26, count 0 2006.197.08:11:42.73#ibcon#read 3, iclass 26, count 0 2006.197.08:11:42.73#ibcon#about to read 4, iclass 26, count 0 2006.197.08:11:42.73#ibcon#read 4, iclass 26, count 0 2006.197.08:11:42.73#ibcon#about to read 5, iclass 26, count 0 2006.197.08:11:42.73#ibcon#read 5, iclass 26, count 0 2006.197.08:11:42.73#ibcon#about to read 6, iclass 26, count 0 2006.197.08:11:42.73#ibcon#read 6, iclass 26, count 0 2006.197.08:11:42.73#ibcon#end of sib2, iclass 26, count 0 2006.197.08:11:42.73#ibcon#*after write, iclass 26, count 0 2006.197.08:11:42.73#ibcon#*before return 0, iclass 26, count 0 2006.197.08:11:42.73#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.197.08:11:42.73#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.197.08:11:42.73#ibcon#about to clear, iclass 26 cls_cnt 0 2006.197.08:11:42.73#ibcon#cleared, iclass 26 cls_cnt 0 2006.197.08:11:42.73$vc4f8/vbbw=wide 2006.197.08:11:42.73#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.197.08:11:42.73#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.197.08:11:42.73#ibcon#ireg 8 cls_cnt 0 2006.197.08:11:42.73#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.197.08:11:42.80#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.197.08:11:42.80#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.197.08:11:42.80#ibcon#enter wrdev, iclass 28, count 0 2006.197.08:11:42.80#ibcon#first serial, iclass 28, count 0 2006.197.08:11:42.80#ibcon#enter sib2, iclass 28, count 0 2006.197.08:11:42.80#ibcon#flushed, iclass 28, count 0 2006.197.08:11:42.80#ibcon#about to write, iclass 28, count 0 2006.197.08:11:42.80#ibcon#wrote, iclass 28, count 0 2006.197.08:11:42.80#ibcon#about to read 3, iclass 28, count 0 2006.197.08:11:42.82#ibcon#read 3, iclass 28, count 0 2006.197.08:11:42.82#ibcon#about to read 4, iclass 28, count 0 2006.197.08:11:42.82#ibcon#read 4, iclass 28, count 0 2006.197.08:11:42.82#ibcon#about to read 5, iclass 28, count 0 2006.197.08:11:42.82#ibcon#read 5, iclass 28, count 0 2006.197.08:11:42.82#ibcon#about to read 6, iclass 28, count 0 2006.197.08:11:42.82#ibcon#read 6, iclass 28, count 0 2006.197.08:11:42.82#ibcon#end of sib2, iclass 28, count 0 2006.197.08:11:42.82#ibcon#*mode == 0, iclass 28, count 0 2006.197.08:11:42.82#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.197.08:11:42.82#ibcon#[27=BW32\r\n] 2006.197.08:11:42.82#ibcon#*before write, iclass 28, count 0 2006.197.08:11:42.82#ibcon#enter sib2, iclass 28, count 0 2006.197.08:11:42.82#ibcon#flushed, iclass 28, count 0 2006.197.08:11:42.82#ibcon#about to write, iclass 28, count 0 2006.197.08:11:42.82#ibcon#wrote, iclass 28, count 0 2006.197.08:11:42.82#ibcon#about to read 3, iclass 28, count 0 2006.197.08:11:42.85#ibcon#read 3, iclass 28, count 0 2006.197.08:11:42.85#ibcon#about to read 4, iclass 28, count 0 2006.197.08:11:42.85#ibcon#read 4, iclass 28, count 0 2006.197.08:11:42.85#ibcon#about to read 5, iclass 28, count 0 2006.197.08:11:42.85#ibcon#read 5, iclass 28, count 0 2006.197.08:11:42.85#ibcon#about to read 6, iclass 28, count 0 2006.197.08:11:42.85#ibcon#read 6, iclass 28, count 0 2006.197.08:11:42.85#ibcon#end of sib2, iclass 28, count 0 2006.197.08:11:42.85#ibcon#*after write, iclass 28, count 0 2006.197.08:11:42.85#ibcon#*before return 0, iclass 28, count 0 2006.197.08:11:42.85#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.197.08:11:42.85#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.197.08:11:42.85#ibcon#about to clear, iclass 28 cls_cnt 0 2006.197.08:11:42.85#ibcon#cleared, iclass 28 cls_cnt 0 2006.197.08:11:42.85$4f8m12a/ifd4f 2006.197.08:11:42.85$ifd4f/lo= 2006.197.08:11:42.85$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.197.08:11:42.85$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.197.08:11:42.85$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.197.08:11:42.85$ifd4f/patch= 2006.197.08:11:42.85$ifd4f/patch=lo1,a1,a2,a3,a4 2006.197.08:11:42.85$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.197.08:11:42.85$ifd4f/patch=lo3,a5,a6,a7,a8 2006.197.08:11:42.85$4f8m12a/"form=m,16.000,1:2 2006.197.08:11:42.85$4f8m12a/"tpicd 2006.197.08:11:42.85$4f8m12a/echo=off 2006.197.08:11:42.85$4f8m12a/xlog=off 2006.197.08:11:42.85:!2006.197.08:12:10 2006.197.08:11:51.13#trakl#Source acquired 2006.197.08:11:52.13#flagr#flagr/antenna,acquired 2006.197.08:12:10.00:preob 2006.197.08:12:11.13/onsource/TRACKING 2006.197.08:12:11.13:!2006.197.08:12:20 2006.197.08:12:20.00:data_valid=on 2006.197.08:12:20.00:midob 2006.197.08:12:20.13/onsource/TRACKING 2006.197.08:12:20.13/wx/25.62,1002.8,96 2006.197.08:12:20.18/cable/+6.3735E-03 2006.197.08:12:21.27/va/01,08,usb,yes,29,31 2006.197.08:12:21.27/va/02,07,usb,yes,29,31 2006.197.08:12:21.27/va/03,06,usb,yes,31,31 2006.197.08:12:21.27/va/04,07,usb,yes,30,32 2006.197.08:12:21.27/va/05,07,usb,yes,34,36 2006.197.08:12:21.27/va/06,06,usb,yes,33,33 2006.197.08:12:21.27/va/07,06,usb,yes,34,34 2006.197.08:12:21.27/va/08,07,usb,yes,32,31 2006.197.08:12:21.50/valo/01,532.99,yes,locked 2006.197.08:12:21.50/valo/02,572.99,yes,locked 2006.197.08:12:21.50/valo/03,672.99,yes,locked 2006.197.08:12:21.50/valo/04,832.99,yes,locked 2006.197.08:12:21.50/valo/05,652.99,yes,locked 2006.197.08:12:21.50/valo/06,772.99,yes,locked 2006.197.08:12:21.50/valo/07,832.99,yes,locked 2006.197.08:12:21.50/valo/08,852.99,yes,locked 2006.197.08:12:22.59/vb/01,04,usb,yes,29,28 2006.197.08:12:22.59/vb/02,04,usb,yes,31,32 2006.197.08:12:22.59/vb/03,04,usb,yes,27,31 2006.197.08:12:22.59/vb/04,04,usb,yes,28,28 2006.197.08:12:22.59/vb/05,04,usb,yes,26,30 2006.197.08:12:22.59/vb/06,04,usb,yes,27,30 2006.197.08:12:22.59/vb/07,04,usb,yes,29,29 2006.197.08:12:22.59/vb/08,04,usb,yes,27,30 2006.197.08:12:22.83/vblo/01,632.99,yes,locked 2006.197.08:12:22.83/vblo/02,640.99,yes,locked 2006.197.08:12:22.83/vblo/03,656.99,yes,locked 2006.197.08:12:22.83/vblo/04,712.99,yes,locked 2006.197.08:12:22.83/vblo/05,744.99,yes,locked 2006.197.08:12:22.83/vblo/06,752.99,yes,locked 2006.197.08:12:22.83/vblo/07,734.99,yes,locked 2006.197.08:12:22.83/vblo/08,744.99,yes,locked 2006.197.08:12:22.98/vabw/8 2006.197.08:12:23.13/vbbw/8 2006.197.08:12:23.22/xfe/off,on,15.5 2006.197.08:12:23.61/ifatt/23,28,28,28 2006.197.08:12:24.09/fmout-gps/S +2.99E-07 2006.197.08:12:24.13:!2006.197.08:13:20 2006.197.08:13:20.00:data_valid=off 2006.197.08:13:20.00:postob 2006.197.08:13:20.13/cable/+6.3717E-03 2006.197.08:13:20.13/wx/25.61,1002.8,96 2006.197.08:13:21.10/fmout-gps/S +2.99E-07 2006.197.08:13:21.10:scan_name=197-0814,k06197,60 2006.197.08:13:21.10:source=0955+476,095819.67,472507.8,2000.0,ccw 2006.197.08:13:21.13#flagr#flagr/antenna,new-source 2006.197.08:13:22.13:checkk5 2006.197.08:13:22.47/chk_autoobs//k5ts1/ autoobs is running! 2006.197.08:13:22.81/chk_autoobs//k5ts2/ autoobs is running! 2006.197.08:13:23.12/chk_autoobs//k5ts3/ autoobs is running! 2006.197.08:13:23.47/chk_autoobs//k5ts4/ autoobs is running! 2006.197.08:13:23.81/chk_obsdata//k5ts1/T1970812??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.08:13:24.17/chk_obsdata//k5ts2/T1970812??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.08:13:24.50/chk_obsdata//k5ts3/T1970812??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.08:13:24.83/chk_obsdata//k5ts4/T1970812??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.08:13:25.49/k5log//k5ts1_log_newline 2006.197.08:13:26.15/k5log//k5ts2_log_newline 2006.197.08:13:26.80/k5log//k5ts3_log_newline 2006.197.08:13:27.46/k5log//k5ts4_log_newline 2006.197.08:13:27.49/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.197.08:13:27.49:4f8m12a=2 2006.197.08:13:27.49$4f8m12a/echo=on 2006.197.08:13:27.49$4f8m12a/pcalon 2006.197.08:13:27.49$pcalon/"no phase cal control is implemented here 2006.197.08:13:27.49$4f8m12a/"tpicd=stop 2006.197.08:13:27.49$4f8m12a/vc4f8 2006.197.08:13:27.49$vc4f8/valo=1,532.99 2006.197.08:13:27.49#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.197.08:13:27.49#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.197.08:13:27.49#ibcon#ireg 17 cls_cnt 0 2006.197.08:13:27.49#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.197.08:13:27.49#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.197.08:13:27.49#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.197.08:13:27.49#ibcon#enter wrdev, iclass 35, count 0 2006.197.08:13:27.49#ibcon#first serial, iclass 35, count 0 2006.197.08:13:27.49#ibcon#enter sib2, iclass 35, count 0 2006.197.08:13:27.49#ibcon#flushed, iclass 35, count 0 2006.197.08:13:27.49#ibcon#about to write, iclass 35, count 0 2006.197.08:13:27.49#ibcon#wrote, iclass 35, count 0 2006.197.08:13:27.49#ibcon#about to read 3, iclass 35, count 0 2006.197.08:13:27.51#ibcon#read 3, iclass 35, count 0 2006.197.08:13:27.51#ibcon#about to read 4, iclass 35, count 0 2006.197.08:13:27.51#ibcon#read 4, iclass 35, count 0 2006.197.08:13:27.51#ibcon#about to read 5, iclass 35, count 0 2006.197.08:13:27.51#ibcon#read 5, iclass 35, count 0 2006.197.08:13:27.51#ibcon#about to read 6, iclass 35, count 0 2006.197.08:13:27.51#ibcon#read 6, iclass 35, count 0 2006.197.08:13:27.51#ibcon#end of sib2, iclass 35, count 0 2006.197.08:13:27.51#ibcon#*mode == 0, iclass 35, count 0 2006.197.08:13:27.51#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.197.08:13:27.51#ibcon#[26=FRQ=01,532.99\r\n] 2006.197.08:13:27.51#ibcon#*before write, iclass 35, count 0 2006.197.08:13:27.51#ibcon#enter sib2, iclass 35, count 0 2006.197.08:13:27.51#ibcon#flushed, iclass 35, count 0 2006.197.08:13:27.51#ibcon#about to write, iclass 35, count 0 2006.197.08:13:27.51#ibcon#wrote, iclass 35, count 0 2006.197.08:13:27.51#ibcon#about to read 3, iclass 35, count 0 2006.197.08:13:27.56#ibcon#read 3, iclass 35, count 0 2006.197.08:13:27.56#ibcon#about to read 4, iclass 35, count 0 2006.197.08:13:27.56#ibcon#read 4, iclass 35, count 0 2006.197.08:13:27.56#ibcon#about to read 5, iclass 35, count 0 2006.197.08:13:27.56#ibcon#read 5, iclass 35, count 0 2006.197.08:13:27.56#ibcon#about to read 6, iclass 35, count 0 2006.197.08:13:27.56#ibcon#read 6, iclass 35, count 0 2006.197.08:13:27.56#ibcon#end of sib2, iclass 35, count 0 2006.197.08:13:27.56#ibcon#*after write, iclass 35, count 0 2006.197.08:13:27.56#ibcon#*before return 0, iclass 35, count 0 2006.197.08:13:27.56#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.197.08:13:27.56#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.197.08:13:27.56#ibcon#about to clear, iclass 35 cls_cnt 0 2006.197.08:13:27.56#ibcon#cleared, iclass 35 cls_cnt 0 2006.197.08:13:27.56$vc4f8/va=1,8 2006.197.08:13:27.56#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.197.08:13:27.56#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.197.08:13:27.56#ibcon#ireg 11 cls_cnt 2 2006.197.08:13:27.56#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.197.08:13:27.56#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.197.08:13:27.56#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.197.08:13:27.56#ibcon#enter wrdev, iclass 37, count 2 2006.197.08:13:27.56#ibcon#first serial, iclass 37, count 2 2006.197.08:13:27.56#ibcon#enter sib2, iclass 37, count 2 2006.197.08:13:27.56#ibcon#flushed, iclass 37, count 2 2006.197.08:13:27.56#ibcon#about to write, iclass 37, count 2 2006.197.08:13:27.56#ibcon#wrote, iclass 37, count 2 2006.197.08:13:27.56#ibcon#about to read 3, iclass 37, count 2 2006.197.08:13:27.58#ibcon#read 3, iclass 37, count 2 2006.197.08:13:27.58#ibcon#about to read 4, iclass 37, count 2 2006.197.08:13:27.58#ibcon#read 4, iclass 37, count 2 2006.197.08:13:27.58#ibcon#about to read 5, iclass 37, count 2 2006.197.08:13:27.58#ibcon#read 5, iclass 37, count 2 2006.197.08:13:27.58#ibcon#about to read 6, iclass 37, count 2 2006.197.08:13:27.58#ibcon#read 6, iclass 37, count 2 2006.197.08:13:27.58#ibcon#end of sib2, iclass 37, count 2 2006.197.08:13:27.58#ibcon#*mode == 0, iclass 37, count 2 2006.197.08:13:27.58#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.197.08:13:27.58#ibcon#[25=AT01-08\r\n] 2006.197.08:13:27.58#ibcon#*before write, iclass 37, count 2 2006.197.08:13:27.58#ibcon#enter sib2, iclass 37, count 2 2006.197.08:13:27.58#ibcon#flushed, iclass 37, count 2 2006.197.08:13:27.58#ibcon#about to write, iclass 37, count 2 2006.197.08:13:27.58#ibcon#wrote, iclass 37, count 2 2006.197.08:13:27.58#ibcon#about to read 3, iclass 37, count 2 2006.197.08:13:27.61#ibcon#read 3, iclass 37, count 2 2006.197.08:13:27.61#ibcon#about to read 4, iclass 37, count 2 2006.197.08:13:27.61#ibcon#read 4, iclass 37, count 2 2006.197.08:13:27.61#ibcon#about to read 5, iclass 37, count 2 2006.197.08:13:27.61#ibcon#read 5, iclass 37, count 2 2006.197.08:13:27.61#ibcon#about to read 6, iclass 37, count 2 2006.197.08:13:27.61#ibcon#read 6, iclass 37, count 2 2006.197.08:13:27.61#ibcon#end of sib2, iclass 37, count 2 2006.197.08:13:27.61#ibcon#*after write, iclass 37, count 2 2006.197.08:13:27.61#ibcon#*before return 0, iclass 37, count 2 2006.197.08:13:27.61#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.197.08:13:27.61#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.197.08:13:27.61#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.197.08:13:27.61#ibcon#ireg 7 cls_cnt 0 2006.197.08:13:27.61#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.197.08:13:27.73#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.197.08:13:27.73#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.197.08:13:27.73#ibcon#enter wrdev, iclass 37, count 0 2006.197.08:13:27.73#ibcon#first serial, iclass 37, count 0 2006.197.08:13:27.73#ibcon#enter sib2, iclass 37, count 0 2006.197.08:13:27.73#ibcon#flushed, iclass 37, count 0 2006.197.08:13:27.73#ibcon#about to write, iclass 37, count 0 2006.197.08:13:27.73#ibcon#wrote, iclass 37, count 0 2006.197.08:13:27.73#ibcon#about to read 3, iclass 37, count 0 2006.197.08:13:27.75#ibcon#read 3, iclass 37, count 0 2006.197.08:13:27.75#ibcon#about to read 4, iclass 37, count 0 2006.197.08:13:27.75#ibcon#read 4, iclass 37, count 0 2006.197.08:13:27.75#ibcon#about to read 5, iclass 37, count 0 2006.197.08:13:27.75#ibcon#read 5, iclass 37, count 0 2006.197.08:13:27.75#ibcon#about to read 6, iclass 37, count 0 2006.197.08:13:27.75#ibcon#read 6, iclass 37, count 0 2006.197.08:13:27.75#ibcon#end of sib2, iclass 37, count 0 2006.197.08:13:27.75#ibcon#*mode == 0, iclass 37, count 0 2006.197.08:13:27.75#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.197.08:13:27.75#ibcon#[25=USB\r\n] 2006.197.08:13:27.75#ibcon#*before write, iclass 37, count 0 2006.197.08:13:27.75#ibcon#enter sib2, iclass 37, count 0 2006.197.08:13:27.75#ibcon#flushed, iclass 37, count 0 2006.197.08:13:27.75#ibcon#about to write, iclass 37, count 0 2006.197.08:13:27.75#ibcon#wrote, iclass 37, count 0 2006.197.08:13:27.75#ibcon#about to read 3, iclass 37, count 0 2006.197.08:13:27.78#ibcon#read 3, iclass 37, count 0 2006.197.08:13:27.78#ibcon#about to read 4, iclass 37, count 0 2006.197.08:13:27.78#ibcon#read 4, iclass 37, count 0 2006.197.08:13:27.78#ibcon#about to read 5, iclass 37, count 0 2006.197.08:13:27.78#ibcon#read 5, iclass 37, count 0 2006.197.08:13:27.78#ibcon#about to read 6, iclass 37, count 0 2006.197.08:13:27.78#ibcon#read 6, iclass 37, count 0 2006.197.08:13:27.78#ibcon#end of sib2, iclass 37, count 0 2006.197.08:13:27.78#ibcon#*after write, iclass 37, count 0 2006.197.08:13:27.78#ibcon#*before return 0, iclass 37, count 0 2006.197.08:13:27.78#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.197.08:13:27.78#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.197.08:13:27.78#ibcon#about to clear, iclass 37 cls_cnt 0 2006.197.08:13:27.78#ibcon#cleared, iclass 37 cls_cnt 0 2006.197.08:13:27.78$vc4f8/valo=2,572.99 2006.197.08:13:27.78#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.197.08:13:27.78#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.197.08:13:27.78#ibcon#ireg 17 cls_cnt 0 2006.197.08:13:27.78#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.197.08:13:27.78#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.197.08:13:27.78#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.197.08:13:27.78#ibcon#enter wrdev, iclass 39, count 0 2006.197.08:13:27.78#ibcon#first serial, iclass 39, count 0 2006.197.08:13:27.78#ibcon#enter sib2, iclass 39, count 0 2006.197.08:13:27.78#ibcon#flushed, iclass 39, count 0 2006.197.08:13:27.78#ibcon#about to write, iclass 39, count 0 2006.197.08:13:27.78#ibcon#wrote, iclass 39, count 0 2006.197.08:13:27.78#ibcon#about to read 3, iclass 39, count 0 2006.197.08:13:27.80#ibcon#read 3, iclass 39, count 0 2006.197.08:13:27.80#ibcon#about to read 4, iclass 39, count 0 2006.197.08:13:27.80#ibcon#read 4, iclass 39, count 0 2006.197.08:13:27.80#ibcon#about to read 5, iclass 39, count 0 2006.197.08:13:27.80#ibcon#read 5, iclass 39, count 0 2006.197.08:13:27.80#ibcon#about to read 6, iclass 39, count 0 2006.197.08:13:27.80#ibcon#read 6, iclass 39, count 0 2006.197.08:13:27.80#ibcon#end of sib2, iclass 39, count 0 2006.197.08:13:27.80#ibcon#*mode == 0, iclass 39, count 0 2006.197.08:13:27.80#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.197.08:13:27.80#ibcon#[26=FRQ=02,572.99\r\n] 2006.197.08:13:27.80#ibcon#*before write, iclass 39, count 0 2006.197.08:13:27.80#ibcon#enter sib2, iclass 39, count 0 2006.197.08:13:27.80#ibcon#flushed, iclass 39, count 0 2006.197.08:13:27.80#ibcon#about to write, iclass 39, count 0 2006.197.08:13:27.80#ibcon#wrote, iclass 39, count 0 2006.197.08:13:27.80#ibcon#about to read 3, iclass 39, count 0 2006.197.08:13:27.84#ibcon#read 3, iclass 39, count 0 2006.197.08:13:27.84#ibcon#about to read 4, iclass 39, count 0 2006.197.08:13:27.84#ibcon#read 4, iclass 39, count 0 2006.197.08:13:27.84#ibcon#about to read 5, iclass 39, count 0 2006.197.08:13:27.84#ibcon#read 5, iclass 39, count 0 2006.197.08:13:27.84#ibcon#about to read 6, iclass 39, count 0 2006.197.08:13:27.84#ibcon#read 6, iclass 39, count 0 2006.197.08:13:27.84#ibcon#end of sib2, iclass 39, count 0 2006.197.08:13:27.84#ibcon#*after write, iclass 39, count 0 2006.197.08:13:27.84#ibcon#*before return 0, iclass 39, count 0 2006.197.08:13:27.84#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.197.08:13:27.84#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.197.08:13:27.84#ibcon#about to clear, iclass 39 cls_cnt 0 2006.197.08:13:27.84#ibcon#cleared, iclass 39 cls_cnt 0 2006.197.08:13:27.84$vc4f8/va=2,7 2006.197.08:13:27.84#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.197.08:13:27.84#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.197.08:13:27.84#ibcon#ireg 11 cls_cnt 2 2006.197.08:13:27.84#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.197.08:13:27.90#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.197.08:13:27.90#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.197.08:13:27.90#ibcon#enter wrdev, iclass 3, count 2 2006.197.08:13:27.90#ibcon#first serial, iclass 3, count 2 2006.197.08:13:27.90#ibcon#enter sib2, iclass 3, count 2 2006.197.08:13:27.90#ibcon#flushed, iclass 3, count 2 2006.197.08:13:27.90#ibcon#about to write, iclass 3, count 2 2006.197.08:13:27.90#ibcon#wrote, iclass 3, count 2 2006.197.08:13:27.90#ibcon#about to read 3, iclass 3, count 2 2006.197.08:13:27.92#ibcon#read 3, iclass 3, count 2 2006.197.08:13:27.92#ibcon#about to read 4, iclass 3, count 2 2006.197.08:13:27.92#ibcon#read 4, iclass 3, count 2 2006.197.08:13:27.92#ibcon#about to read 5, iclass 3, count 2 2006.197.08:13:27.92#ibcon#read 5, iclass 3, count 2 2006.197.08:13:27.92#ibcon#about to read 6, iclass 3, count 2 2006.197.08:13:27.92#ibcon#read 6, iclass 3, count 2 2006.197.08:13:27.92#ibcon#end of sib2, iclass 3, count 2 2006.197.08:13:27.92#ibcon#*mode == 0, iclass 3, count 2 2006.197.08:13:27.92#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.197.08:13:27.92#ibcon#[25=AT02-07\r\n] 2006.197.08:13:27.92#ibcon#*before write, iclass 3, count 2 2006.197.08:13:27.92#ibcon#enter sib2, iclass 3, count 2 2006.197.08:13:27.92#ibcon#flushed, iclass 3, count 2 2006.197.08:13:27.92#ibcon#about to write, iclass 3, count 2 2006.197.08:13:27.92#ibcon#wrote, iclass 3, count 2 2006.197.08:13:27.92#ibcon#about to read 3, iclass 3, count 2 2006.197.08:13:27.95#ibcon#read 3, iclass 3, count 2 2006.197.08:13:27.95#ibcon#about to read 4, iclass 3, count 2 2006.197.08:13:27.95#ibcon#read 4, iclass 3, count 2 2006.197.08:13:27.95#ibcon#about to read 5, iclass 3, count 2 2006.197.08:13:27.95#ibcon#read 5, iclass 3, count 2 2006.197.08:13:27.95#ibcon#about to read 6, iclass 3, count 2 2006.197.08:13:27.95#ibcon#read 6, iclass 3, count 2 2006.197.08:13:27.95#ibcon#end of sib2, iclass 3, count 2 2006.197.08:13:27.95#ibcon#*after write, iclass 3, count 2 2006.197.08:13:27.95#ibcon#*before return 0, iclass 3, count 2 2006.197.08:13:27.95#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.197.08:13:27.95#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.197.08:13:27.95#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.197.08:13:27.95#ibcon#ireg 7 cls_cnt 0 2006.197.08:13:27.95#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.197.08:13:28.07#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.197.08:13:28.07#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.197.08:13:28.07#ibcon#enter wrdev, iclass 3, count 0 2006.197.08:13:28.07#ibcon#first serial, iclass 3, count 0 2006.197.08:13:28.07#ibcon#enter sib2, iclass 3, count 0 2006.197.08:13:28.07#ibcon#flushed, iclass 3, count 0 2006.197.08:13:28.07#ibcon#about to write, iclass 3, count 0 2006.197.08:13:28.07#ibcon#wrote, iclass 3, count 0 2006.197.08:13:28.07#ibcon#about to read 3, iclass 3, count 0 2006.197.08:13:28.09#ibcon#read 3, iclass 3, count 0 2006.197.08:13:28.09#ibcon#about to read 4, iclass 3, count 0 2006.197.08:13:28.09#ibcon#read 4, iclass 3, count 0 2006.197.08:13:28.09#ibcon#about to read 5, iclass 3, count 0 2006.197.08:13:28.09#ibcon#read 5, iclass 3, count 0 2006.197.08:13:28.09#ibcon#about to read 6, iclass 3, count 0 2006.197.08:13:28.09#ibcon#read 6, iclass 3, count 0 2006.197.08:13:28.09#ibcon#end of sib2, iclass 3, count 0 2006.197.08:13:28.09#ibcon#*mode == 0, iclass 3, count 0 2006.197.08:13:28.09#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.197.08:13:28.09#ibcon#[25=USB\r\n] 2006.197.08:13:28.09#ibcon#*before write, iclass 3, count 0 2006.197.08:13:28.09#ibcon#enter sib2, iclass 3, count 0 2006.197.08:13:28.09#ibcon#flushed, iclass 3, count 0 2006.197.08:13:28.09#ibcon#about to write, iclass 3, count 0 2006.197.08:13:28.09#ibcon#wrote, iclass 3, count 0 2006.197.08:13:28.09#ibcon#about to read 3, iclass 3, count 0 2006.197.08:13:28.12#ibcon#read 3, iclass 3, count 0 2006.197.08:13:28.12#ibcon#about to read 4, iclass 3, count 0 2006.197.08:13:28.12#ibcon#read 4, iclass 3, count 0 2006.197.08:13:28.12#ibcon#about to read 5, iclass 3, count 0 2006.197.08:13:28.12#ibcon#read 5, iclass 3, count 0 2006.197.08:13:28.12#ibcon#about to read 6, iclass 3, count 0 2006.197.08:13:28.12#ibcon#read 6, iclass 3, count 0 2006.197.08:13:28.12#ibcon#end of sib2, iclass 3, count 0 2006.197.08:13:28.12#ibcon#*after write, iclass 3, count 0 2006.197.08:13:28.12#ibcon#*before return 0, iclass 3, count 0 2006.197.08:13:28.12#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.197.08:13:28.12#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.197.08:13:28.12#ibcon#about to clear, iclass 3 cls_cnt 0 2006.197.08:13:28.12#ibcon#cleared, iclass 3 cls_cnt 0 2006.197.08:13:28.12$vc4f8/valo=3,672.99 2006.197.08:13:28.12#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.197.08:13:28.12#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.197.08:13:28.12#ibcon#ireg 17 cls_cnt 0 2006.197.08:13:28.12#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.197.08:13:28.12#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.197.08:13:28.12#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.197.08:13:28.12#ibcon#enter wrdev, iclass 5, count 0 2006.197.08:13:28.12#ibcon#first serial, iclass 5, count 0 2006.197.08:13:28.12#ibcon#enter sib2, iclass 5, count 0 2006.197.08:13:28.12#ibcon#flushed, iclass 5, count 0 2006.197.08:13:28.12#ibcon#about to write, iclass 5, count 0 2006.197.08:13:28.12#ibcon#wrote, iclass 5, count 0 2006.197.08:13:28.12#ibcon#about to read 3, iclass 5, count 0 2006.197.08:13:28.14#ibcon#read 3, iclass 5, count 0 2006.197.08:13:28.14#ibcon#about to read 4, iclass 5, count 0 2006.197.08:13:28.14#ibcon#read 4, iclass 5, count 0 2006.197.08:13:28.14#ibcon#about to read 5, iclass 5, count 0 2006.197.08:13:28.14#ibcon#read 5, iclass 5, count 0 2006.197.08:13:28.14#ibcon#about to read 6, iclass 5, count 0 2006.197.08:13:28.14#ibcon#read 6, iclass 5, count 0 2006.197.08:13:28.14#ibcon#end of sib2, iclass 5, count 0 2006.197.08:13:28.14#ibcon#*mode == 0, iclass 5, count 0 2006.197.08:13:28.14#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.197.08:13:28.14#ibcon#[26=FRQ=03,672.99\r\n] 2006.197.08:13:28.14#ibcon#*before write, iclass 5, count 0 2006.197.08:13:28.14#ibcon#enter sib2, iclass 5, count 0 2006.197.08:13:28.14#ibcon#flushed, iclass 5, count 0 2006.197.08:13:28.14#ibcon#about to write, iclass 5, count 0 2006.197.08:13:28.14#ibcon#wrote, iclass 5, count 0 2006.197.08:13:28.14#ibcon#about to read 3, iclass 5, count 0 2006.197.08:13:28.18#ibcon#read 3, iclass 5, count 0 2006.197.08:13:28.18#ibcon#about to read 4, iclass 5, count 0 2006.197.08:13:28.18#ibcon#read 4, iclass 5, count 0 2006.197.08:13:28.18#ibcon#about to read 5, iclass 5, count 0 2006.197.08:13:28.18#ibcon#read 5, iclass 5, count 0 2006.197.08:13:28.18#ibcon#about to read 6, iclass 5, count 0 2006.197.08:13:28.18#ibcon#read 6, iclass 5, count 0 2006.197.08:13:28.18#ibcon#end of sib2, iclass 5, count 0 2006.197.08:13:28.18#ibcon#*after write, iclass 5, count 0 2006.197.08:13:28.18#ibcon#*before return 0, iclass 5, count 0 2006.197.08:13:28.18#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.197.08:13:28.18#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.197.08:13:28.18#ibcon#about to clear, iclass 5 cls_cnt 0 2006.197.08:13:28.18#ibcon#cleared, iclass 5 cls_cnt 0 2006.197.08:13:28.18$vc4f8/va=3,6 2006.197.08:13:28.18#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.197.08:13:28.18#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.197.08:13:28.18#ibcon#ireg 11 cls_cnt 2 2006.197.08:13:28.18#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.197.08:13:28.24#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.197.08:13:28.24#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.197.08:13:28.24#ibcon#enter wrdev, iclass 7, count 2 2006.197.08:13:28.24#ibcon#first serial, iclass 7, count 2 2006.197.08:13:28.24#ibcon#enter sib2, iclass 7, count 2 2006.197.08:13:28.24#ibcon#flushed, iclass 7, count 2 2006.197.08:13:28.24#ibcon#about to write, iclass 7, count 2 2006.197.08:13:28.24#ibcon#wrote, iclass 7, count 2 2006.197.08:13:28.24#ibcon#about to read 3, iclass 7, count 2 2006.197.08:13:28.26#ibcon#read 3, iclass 7, count 2 2006.197.08:13:28.26#ibcon#about to read 4, iclass 7, count 2 2006.197.08:13:28.26#ibcon#read 4, iclass 7, count 2 2006.197.08:13:28.26#ibcon#about to read 5, iclass 7, count 2 2006.197.08:13:28.26#ibcon#read 5, iclass 7, count 2 2006.197.08:13:28.26#ibcon#about to read 6, iclass 7, count 2 2006.197.08:13:28.26#ibcon#read 6, iclass 7, count 2 2006.197.08:13:28.26#ibcon#end of sib2, iclass 7, count 2 2006.197.08:13:28.26#ibcon#*mode == 0, iclass 7, count 2 2006.197.08:13:28.26#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.197.08:13:28.26#ibcon#[25=AT03-06\r\n] 2006.197.08:13:28.26#ibcon#*before write, iclass 7, count 2 2006.197.08:13:28.26#ibcon#enter sib2, iclass 7, count 2 2006.197.08:13:28.26#ibcon#flushed, iclass 7, count 2 2006.197.08:13:28.26#ibcon#about to write, iclass 7, count 2 2006.197.08:13:28.26#ibcon#wrote, iclass 7, count 2 2006.197.08:13:28.26#ibcon#about to read 3, iclass 7, count 2 2006.197.08:13:28.29#ibcon#read 3, iclass 7, count 2 2006.197.08:13:28.29#ibcon#about to read 4, iclass 7, count 2 2006.197.08:13:28.29#ibcon#read 4, iclass 7, count 2 2006.197.08:13:28.29#ibcon#about to read 5, iclass 7, count 2 2006.197.08:13:28.29#ibcon#read 5, iclass 7, count 2 2006.197.08:13:28.29#ibcon#about to read 6, iclass 7, count 2 2006.197.08:13:28.29#ibcon#read 6, iclass 7, count 2 2006.197.08:13:28.29#ibcon#end of sib2, iclass 7, count 2 2006.197.08:13:28.29#ibcon#*after write, iclass 7, count 2 2006.197.08:13:28.29#ibcon#*before return 0, iclass 7, count 2 2006.197.08:13:28.29#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.197.08:13:28.29#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.197.08:13:28.29#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.197.08:13:28.29#ibcon#ireg 7 cls_cnt 0 2006.197.08:13:28.29#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.197.08:13:28.41#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.197.08:13:28.41#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.197.08:13:28.41#ibcon#enter wrdev, iclass 7, count 0 2006.197.08:13:28.41#ibcon#first serial, iclass 7, count 0 2006.197.08:13:28.41#ibcon#enter sib2, iclass 7, count 0 2006.197.08:13:28.41#ibcon#flushed, iclass 7, count 0 2006.197.08:13:28.41#ibcon#about to write, iclass 7, count 0 2006.197.08:13:28.41#ibcon#wrote, iclass 7, count 0 2006.197.08:13:28.41#ibcon#about to read 3, iclass 7, count 0 2006.197.08:13:28.43#ibcon#read 3, iclass 7, count 0 2006.197.08:13:28.43#ibcon#about to read 4, iclass 7, count 0 2006.197.08:13:28.43#ibcon#read 4, iclass 7, count 0 2006.197.08:13:28.43#ibcon#about to read 5, iclass 7, count 0 2006.197.08:13:28.43#ibcon#read 5, iclass 7, count 0 2006.197.08:13:28.43#ibcon#about to read 6, iclass 7, count 0 2006.197.08:13:28.43#ibcon#read 6, iclass 7, count 0 2006.197.08:13:28.43#ibcon#end of sib2, iclass 7, count 0 2006.197.08:13:28.43#ibcon#*mode == 0, iclass 7, count 0 2006.197.08:13:28.43#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.197.08:13:28.43#ibcon#[25=USB\r\n] 2006.197.08:13:28.43#ibcon#*before write, iclass 7, count 0 2006.197.08:13:28.43#ibcon#enter sib2, iclass 7, count 0 2006.197.08:13:28.43#ibcon#flushed, iclass 7, count 0 2006.197.08:13:28.43#ibcon#about to write, iclass 7, count 0 2006.197.08:13:28.43#ibcon#wrote, iclass 7, count 0 2006.197.08:13:28.43#ibcon#about to read 3, iclass 7, count 0 2006.197.08:13:28.46#ibcon#read 3, iclass 7, count 0 2006.197.08:13:28.46#ibcon#about to read 4, iclass 7, count 0 2006.197.08:13:28.46#ibcon#read 4, iclass 7, count 0 2006.197.08:13:28.46#ibcon#about to read 5, iclass 7, count 0 2006.197.08:13:28.46#ibcon#read 5, iclass 7, count 0 2006.197.08:13:28.46#ibcon#about to read 6, iclass 7, count 0 2006.197.08:13:28.46#ibcon#read 6, iclass 7, count 0 2006.197.08:13:28.46#ibcon#end of sib2, iclass 7, count 0 2006.197.08:13:28.46#ibcon#*after write, iclass 7, count 0 2006.197.08:13:28.46#ibcon#*before return 0, iclass 7, count 0 2006.197.08:13:28.46#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.197.08:13:28.46#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.197.08:13:28.46#ibcon#about to clear, iclass 7 cls_cnt 0 2006.197.08:13:28.46#ibcon#cleared, iclass 7 cls_cnt 0 2006.197.08:13:28.46$vc4f8/valo=4,832.99 2006.197.08:13:28.46#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.197.08:13:28.46#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.197.08:13:28.46#ibcon#ireg 17 cls_cnt 0 2006.197.08:13:28.46#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.197.08:13:28.46#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.197.08:13:28.46#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.197.08:13:28.46#ibcon#enter wrdev, iclass 11, count 0 2006.197.08:13:28.46#ibcon#first serial, iclass 11, count 0 2006.197.08:13:28.46#ibcon#enter sib2, iclass 11, count 0 2006.197.08:13:28.46#ibcon#flushed, iclass 11, count 0 2006.197.08:13:28.46#ibcon#about to write, iclass 11, count 0 2006.197.08:13:28.46#ibcon#wrote, iclass 11, count 0 2006.197.08:13:28.46#ibcon#about to read 3, iclass 11, count 0 2006.197.08:13:28.48#ibcon#read 3, iclass 11, count 0 2006.197.08:13:28.48#ibcon#about to read 4, iclass 11, count 0 2006.197.08:13:28.48#ibcon#read 4, iclass 11, count 0 2006.197.08:13:28.48#ibcon#about to read 5, iclass 11, count 0 2006.197.08:13:28.48#ibcon#read 5, iclass 11, count 0 2006.197.08:13:28.48#ibcon#about to read 6, iclass 11, count 0 2006.197.08:13:28.48#ibcon#read 6, iclass 11, count 0 2006.197.08:13:28.48#ibcon#end of sib2, iclass 11, count 0 2006.197.08:13:28.48#ibcon#*mode == 0, iclass 11, count 0 2006.197.08:13:28.48#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.197.08:13:28.48#ibcon#[26=FRQ=04,832.99\r\n] 2006.197.08:13:28.48#ibcon#*before write, iclass 11, count 0 2006.197.08:13:28.48#ibcon#enter sib2, iclass 11, count 0 2006.197.08:13:28.48#ibcon#flushed, iclass 11, count 0 2006.197.08:13:28.48#ibcon#about to write, iclass 11, count 0 2006.197.08:13:28.48#ibcon#wrote, iclass 11, count 0 2006.197.08:13:28.48#ibcon#about to read 3, iclass 11, count 0 2006.197.08:13:28.52#ibcon#read 3, iclass 11, count 0 2006.197.08:13:28.52#ibcon#about to read 4, iclass 11, count 0 2006.197.08:13:28.52#ibcon#read 4, iclass 11, count 0 2006.197.08:13:28.52#ibcon#about to read 5, iclass 11, count 0 2006.197.08:13:28.52#ibcon#read 5, iclass 11, count 0 2006.197.08:13:28.52#ibcon#about to read 6, iclass 11, count 0 2006.197.08:13:28.52#ibcon#read 6, iclass 11, count 0 2006.197.08:13:28.52#ibcon#end of sib2, iclass 11, count 0 2006.197.08:13:28.52#ibcon#*after write, iclass 11, count 0 2006.197.08:13:28.52#ibcon#*before return 0, iclass 11, count 0 2006.197.08:13:28.52#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.197.08:13:28.52#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.197.08:13:28.52#ibcon#about to clear, iclass 11 cls_cnt 0 2006.197.08:13:28.52#ibcon#cleared, iclass 11 cls_cnt 0 2006.197.08:13:28.52$vc4f8/va=4,7 2006.197.08:13:28.52#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.197.08:13:28.52#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.197.08:13:28.52#ibcon#ireg 11 cls_cnt 2 2006.197.08:13:28.52#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.197.08:13:28.58#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.197.08:13:28.58#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.197.08:13:28.58#ibcon#enter wrdev, iclass 13, count 2 2006.197.08:13:28.58#ibcon#first serial, iclass 13, count 2 2006.197.08:13:28.58#ibcon#enter sib2, iclass 13, count 2 2006.197.08:13:28.58#ibcon#flushed, iclass 13, count 2 2006.197.08:13:28.58#ibcon#about to write, iclass 13, count 2 2006.197.08:13:28.58#ibcon#wrote, iclass 13, count 2 2006.197.08:13:28.58#ibcon#about to read 3, iclass 13, count 2 2006.197.08:13:28.60#ibcon#read 3, iclass 13, count 2 2006.197.08:13:28.60#ibcon#about to read 4, iclass 13, count 2 2006.197.08:13:28.60#ibcon#read 4, iclass 13, count 2 2006.197.08:13:28.60#ibcon#about to read 5, iclass 13, count 2 2006.197.08:13:28.60#ibcon#read 5, iclass 13, count 2 2006.197.08:13:28.60#ibcon#about to read 6, iclass 13, count 2 2006.197.08:13:28.60#ibcon#read 6, iclass 13, count 2 2006.197.08:13:28.60#ibcon#end of sib2, iclass 13, count 2 2006.197.08:13:28.60#ibcon#*mode == 0, iclass 13, count 2 2006.197.08:13:28.60#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.197.08:13:28.60#ibcon#[25=AT04-07\r\n] 2006.197.08:13:28.60#ibcon#*before write, iclass 13, count 2 2006.197.08:13:28.60#ibcon#enter sib2, iclass 13, count 2 2006.197.08:13:28.60#ibcon#flushed, iclass 13, count 2 2006.197.08:13:28.60#ibcon#about to write, iclass 13, count 2 2006.197.08:13:28.60#ibcon#wrote, iclass 13, count 2 2006.197.08:13:28.60#ibcon#about to read 3, iclass 13, count 2 2006.197.08:13:28.63#ibcon#read 3, iclass 13, count 2 2006.197.08:13:28.63#ibcon#about to read 4, iclass 13, count 2 2006.197.08:13:28.63#ibcon#read 4, iclass 13, count 2 2006.197.08:13:28.63#ibcon#about to read 5, iclass 13, count 2 2006.197.08:13:28.63#ibcon#read 5, iclass 13, count 2 2006.197.08:13:28.63#ibcon#about to read 6, iclass 13, count 2 2006.197.08:13:28.63#ibcon#read 6, iclass 13, count 2 2006.197.08:13:28.63#ibcon#end of sib2, iclass 13, count 2 2006.197.08:13:28.63#ibcon#*after write, iclass 13, count 2 2006.197.08:13:28.63#ibcon#*before return 0, iclass 13, count 2 2006.197.08:13:28.63#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.197.08:13:28.63#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.197.08:13:28.63#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.197.08:13:28.63#ibcon#ireg 7 cls_cnt 0 2006.197.08:13:28.63#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.197.08:13:28.75#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.197.08:13:28.75#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.197.08:13:28.75#ibcon#enter wrdev, iclass 13, count 0 2006.197.08:13:28.75#ibcon#first serial, iclass 13, count 0 2006.197.08:13:28.75#ibcon#enter sib2, iclass 13, count 0 2006.197.08:13:28.75#ibcon#flushed, iclass 13, count 0 2006.197.08:13:28.75#ibcon#about to write, iclass 13, count 0 2006.197.08:13:28.75#ibcon#wrote, iclass 13, count 0 2006.197.08:13:28.75#ibcon#about to read 3, iclass 13, count 0 2006.197.08:13:28.77#ibcon#read 3, iclass 13, count 0 2006.197.08:13:28.77#ibcon#about to read 4, iclass 13, count 0 2006.197.08:13:28.77#ibcon#read 4, iclass 13, count 0 2006.197.08:13:28.77#ibcon#about to read 5, iclass 13, count 0 2006.197.08:13:28.77#ibcon#read 5, iclass 13, count 0 2006.197.08:13:28.77#ibcon#about to read 6, iclass 13, count 0 2006.197.08:13:28.77#ibcon#read 6, iclass 13, count 0 2006.197.08:13:28.77#ibcon#end of sib2, iclass 13, count 0 2006.197.08:13:28.77#ibcon#*mode == 0, iclass 13, count 0 2006.197.08:13:28.77#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.197.08:13:28.77#ibcon#[25=USB\r\n] 2006.197.08:13:28.77#ibcon#*before write, iclass 13, count 0 2006.197.08:13:28.77#ibcon#enter sib2, iclass 13, count 0 2006.197.08:13:28.77#ibcon#flushed, iclass 13, count 0 2006.197.08:13:28.77#ibcon#about to write, iclass 13, count 0 2006.197.08:13:28.77#ibcon#wrote, iclass 13, count 0 2006.197.08:13:28.77#ibcon#about to read 3, iclass 13, count 0 2006.197.08:13:28.80#ibcon#read 3, iclass 13, count 0 2006.197.08:13:28.80#ibcon#about to read 4, iclass 13, count 0 2006.197.08:13:28.80#ibcon#read 4, iclass 13, count 0 2006.197.08:13:28.80#ibcon#about to read 5, iclass 13, count 0 2006.197.08:13:28.80#ibcon#read 5, iclass 13, count 0 2006.197.08:13:28.80#ibcon#about to read 6, iclass 13, count 0 2006.197.08:13:28.80#ibcon#read 6, iclass 13, count 0 2006.197.08:13:28.80#ibcon#end of sib2, iclass 13, count 0 2006.197.08:13:28.80#ibcon#*after write, iclass 13, count 0 2006.197.08:13:28.80#ibcon#*before return 0, iclass 13, count 0 2006.197.08:13:28.80#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.197.08:13:28.80#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.197.08:13:28.80#ibcon#about to clear, iclass 13 cls_cnt 0 2006.197.08:13:28.80#ibcon#cleared, iclass 13 cls_cnt 0 2006.197.08:13:28.80$vc4f8/valo=5,652.99 2006.197.08:13:28.80#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.197.08:13:28.80#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.197.08:13:28.80#ibcon#ireg 17 cls_cnt 0 2006.197.08:13:28.80#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.197.08:13:28.80#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.197.08:13:28.80#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.197.08:13:28.80#ibcon#enter wrdev, iclass 15, count 0 2006.197.08:13:28.80#ibcon#first serial, iclass 15, count 0 2006.197.08:13:28.80#ibcon#enter sib2, iclass 15, count 0 2006.197.08:13:28.80#ibcon#flushed, iclass 15, count 0 2006.197.08:13:28.80#ibcon#about to write, iclass 15, count 0 2006.197.08:13:28.80#ibcon#wrote, iclass 15, count 0 2006.197.08:13:28.80#ibcon#about to read 3, iclass 15, count 0 2006.197.08:13:28.82#ibcon#read 3, iclass 15, count 0 2006.197.08:13:28.82#ibcon#about to read 4, iclass 15, count 0 2006.197.08:13:28.82#ibcon#read 4, iclass 15, count 0 2006.197.08:13:28.82#ibcon#about to read 5, iclass 15, count 0 2006.197.08:13:28.82#ibcon#read 5, iclass 15, count 0 2006.197.08:13:28.82#ibcon#about to read 6, iclass 15, count 0 2006.197.08:13:28.82#ibcon#read 6, iclass 15, count 0 2006.197.08:13:28.82#ibcon#end of sib2, iclass 15, count 0 2006.197.08:13:28.82#ibcon#*mode == 0, iclass 15, count 0 2006.197.08:13:28.82#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.197.08:13:28.82#ibcon#[26=FRQ=05,652.99\r\n] 2006.197.08:13:28.82#ibcon#*before write, iclass 15, count 0 2006.197.08:13:28.82#ibcon#enter sib2, iclass 15, count 0 2006.197.08:13:28.82#ibcon#flushed, iclass 15, count 0 2006.197.08:13:28.82#ibcon#about to write, iclass 15, count 0 2006.197.08:13:28.82#ibcon#wrote, iclass 15, count 0 2006.197.08:13:28.82#ibcon#about to read 3, iclass 15, count 0 2006.197.08:13:28.86#ibcon#read 3, iclass 15, count 0 2006.197.08:13:28.86#ibcon#about to read 4, iclass 15, count 0 2006.197.08:13:28.86#ibcon#read 4, iclass 15, count 0 2006.197.08:13:28.86#ibcon#about to read 5, iclass 15, count 0 2006.197.08:13:28.86#ibcon#read 5, iclass 15, count 0 2006.197.08:13:28.86#ibcon#about to read 6, iclass 15, count 0 2006.197.08:13:28.86#ibcon#read 6, iclass 15, count 0 2006.197.08:13:28.86#ibcon#end of sib2, iclass 15, count 0 2006.197.08:13:28.86#ibcon#*after write, iclass 15, count 0 2006.197.08:13:28.86#ibcon#*before return 0, iclass 15, count 0 2006.197.08:13:28.86#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.197.08:13:28.86#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.197.08:13:28.86#ibcon#about to clear, iclass 15 cls_cnt 0 2006.197.08:13:28.86#ibcon#cleared, iclass 15 cls_cnt 0 2006.197.08:13:28.86$vc4f8/va=5,7 2006.197.08:13:28.86#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.197.08:13:28.86#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.197.08:13:28.86#ibcon#ireg 11 cls_cnt 2 2006.197.08:13:28.86#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.197.08:13:28.92#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.197.08:13:28.92#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.197.08:13:28.92#ibcon#enter wrdev, iclass 17, count 2 2006.197.08:13:28.92#ibcon#first serial, iclass 17, count 2 2006.197.08:13:28.92#ibcon#enter sib2, iclass 17, count 2 2006.197.08:13:28.92#ibcon#flushed, iclass 17, count 2 2006.197.08:13:28.92#ibcon#about to write, iclass 17, count 2 2006.197.08:13:28.92#ibcon#wrote, iclass 17, count 2 2006.197.08:13:28.92#ibcon#about to read 3, iclass 17, count 2 2006.197.08:13:28.94#ibcon#read 3, iclass 17, count 2 2006.197.08:13:28.94#ibcon#about to read 4, iclass 17, count 2 2006.197.08:13:28.94#ibcon#read 4, iclass 17, count 2 2006.197.08:13:28.94#ibcon#about to read 5, iclass 17, count 2 2006.197.08:13:28.94#ibcon#read 5, iclass 17, count 2 2006.197.08:13:28.94#ibcon#about to read 6, iclass 17, count 2 2006.197.08:13:28.94#ibcon#read 6, iclass 17, count 2 2006.197.08:13:28.94#ibcon#end of sib2, iclass 17, count 2 2006.197.08:13:28.94#ibcon#*mode == 0, iclass 17, count 2 2006.197.08:13:28.94#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.197.08:13:28.94#ibcon#[25=AT05-07\r\n] 2006.197.08:13:28.94#ibcon#*before write, iclass 17, count 2 2006.197.08:13:28.94#ibcon#enter sib2, iclass 17, count 2 2006.197.08:13:28.94#ibcon#flushed, iclass 17, count 2 2006.197.08:13:28.94#ibcon#about to write, iclass 17, count 2 2006.197.08:13:28.94#ibcon#wrote, iclass 17, count 2 2006.197.08:13:28.94#ibcon#about to read 3, iclass 17, count 2 2006.197.08:13:28.97#ibcon#read 3, iclass 17, count 2 2006.197.08:13:28.97#ibcon#about to read 4, iclass 17, count 2 2006.197.08:13:28.97#ibcon#read 4, iclass 17, count 2 2006.197.08:13:28.97#ibcon#about to read 5, iclass 17, count 2 2006.197.08:13:28.97#ibcon#read 5, iclass 17, count 2 2006.197.08:13:28.97#ibcon#about to read 6, iclass 17, count 2 2006.197.08:13:28.97#ibcon#read 6, iclass 17, count 2 2006.197.08:13:28.97#ibcon#end of sib2, iclass 17, count 2 2006.197.08:13:28.97#ibcon#*after write, iclass 17, count 2 2006.197.08:13:28.97#ibcon#*before return 0, iclass 17, count 2 2006.197.08:13:28.97#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.197.08:13:28.97#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.197.08:13:28.97#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.197.08:13:28.97#ibcon#ireg 7 cls_cnt 0 2006.197.08:13:28.97#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.197.08:13:29.09#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.197.08:13:29.09#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.197.08:13:29.09#ibcon#enter wrdev, iclass 17, count 0 2006.197.08:13:29.09#ibcon#first serial, iclass 17, count 0 2006.197.08:13:29.09#ibcon#enter sib2, iclass 17, count 0 2006.197.08:13:29.09#ibcon#flushed, iclass 17, count 0 2006.197.08:13:29.09#ibcon#about to write, iclass 17, count 0 2006.197.08:13:29.09#ibcon#wrote, iclass 17, count 0 2006.197.08:13:29.09#ibcon#about to read 3, iclass 17, count 0 2006.197.08:13:29.11#ibcon#read 3, iclass 17, count 0 2006.197.08:13:29.11#ibcon#about to read 4, iclass 17, count 0 2006.197.08:13:29.11#ibcon#read 4, iclass 17, count 0 2006.197.08:13:29.11#ibcon#about to read 5, iclass 17, count 0 2006.197.08:13:29.11#ibcon#read 5, iclass 17, count 0 2006.197.08:13:29.11#ibcon#about to read 6, iclass 17, count 0 2006.197.08:13:29.11#ibcon#read 6, iclass 17, count 0 2006.197.08:13:29.11#ibcon#end of sib2, iclass 17, count 0 2006.197.08:13:29.11#ibcon#*mode == 0, iclass 17, count 0 2006.197.08:13:29.11#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.197.08:13:29.11#ibcon#[25=USB\r\n] 2006.197.08:13:29.11#ibcon#*before write, iclass 17, count 0 2006.197.08:13:29.11#ibcon#enter sib2, iclass 17, count 0 2006.197.08:13:29.11#ibcon#flushed, iclass 17, count 0 2006.197.08:13:29.11#ibcon#about to write, iclass 17, count 0 2006.197.08:13:29.11#ibcon#wrote, iclass 17, count 0 2006.197.08:13:29.11#ibcon#about to read 3, iclass 17, count 0 2006.197.08:13:29.14#ibcon#read 3, iclass 17, count 0 2006.197.08:13:29.14#ibcon#about to read 4, iclass 17, count 0 2006.197.08:13:29.14#ibcon#read 4, iclass 17, count 0 2006.197.08:13:29.14#ibcon#about to read 5, iclass 17, count 0 2006.197.08:13:29.14#ibcon#read 5, iclass 17, count 0 2006.197.08:13:29.14#ibcon#about to read 6, iclass 17, count 0 2006.197.08:13:29.14#ibcon#read 6, iclass 17, count 0 2006.197.08:13:29.14#ibcon#end of sib2, iclass 17, count 0 2006.197.08:13:29.14#ibcon#*after write, iclass 17, count 0 2006.197.08:13:29.14#ibcon#*before return 0, iclass 17, count 0 2006.197.08:13:29.14#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.197.08:13:29.14#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.197.08:13:29.14#ibcon#about to clear, iclass 17 cls_cnt 0 2006.197.08:13:29.14#ibcon#cleared, iclass 17 cls_cnt 0 2006.197.08:13:29.14$vc4f8/valo=6,772.99 2006.197.08:13:29.14#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.197.08:13:29.14#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.197.08:13:29.14#ibcon#ireg 17 cls_cnt 0 2006.197.08:13:29.14#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.197.08:13:29.14#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.197.08:13:29.14#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.197.08:13:29.14#ibcon#enter wrdev, iclass 19, count 0 2006.197.08:13:29.14#ibcon#first serial, iclass 19, count 0 2006.197.08:13:29.14#ibcon#enter sib2, iclass 19, count 0 2006.197.08:13:29.14#ibcon#flushed, iclass 19, count 0 2006.197.08:13:29.14#ibcon#about to write, iclass 19, count 0 2006.197.08:13:29.14#ibcon#wrote, iclass 19, count 0 2006.197.08:13:29.14#ibcon#about to read 3, iclass 19, count 0 2006.197.08:13:29.16#ibcon#read 3, iclass 19, count 0 2006.197.08:13:29.16#ibcon#about to read 4, iclass 19, count 0 2006.197.08:13:29.16#ibcon#read 4, iclass 19, count 0 2006.197.08:13:29.16#ibcon#about to read 5, iclass 19, count 0 2006.197.08:13:29.16#ibcon#read 5, iclass 19, count 0 2006.197.08:13:29.16#ibcon#about to read 6, iclass 19, count 0 2006.197.08:13:29.16#ibcon#read 6, iclass 19, count 0 2006.197.08:13:29.16#ibcon#end of sib2, iclass 19, count 0 2006.197.08:13:29.16#ibcon#*mode == 0, iclass 19, count 0 2006.197.08:13:29.16#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.197.08:13:29.16#ibcon#[26=FRQ=06,772.99\r\n] 2006.197.08:13:29.16#ibcon#*before write, iclass 19, count 0 2006.197.08:13:29.16#ibcon#enter sib2, iclass 19, count 0 2006.197.08:13:29.16#ibcon#flushed, iclass 19, count 0 2006.197.08:13:29.16#ibcon#about to write, iclass 19, count 0 2006.197.08:13:29.16#ibcon#wrote, iclass 19, count 0 2006.197.08:13:29.16#ibcon#about to read 3, iclass 19, count 0 2006.197.08:13:29.20#ibcon#read 3, iclass 19, count 0 2006.197.08:13:29.20#ibcon#about to read 4, iclass 19, count 0 2006.197.08:13:29.20#ibcon#read 4, iclass 19, count 0 2006.197.08:13:29.20#ibcon#about to read 5, iclass 19, count 0 2006.197.08:13:29.20#ibcon#read 5, iclass 19, count 0 2006.197.08:13:29.20#ibcon#about to read 6, iclass 19, count 0 2006.197.08:13:29.20#ibcon#read 6, iclass 19, count 0 2006.197.08:13:29.20#ibcon#end of sib2, iclass 19, count 0 2006.197.08:13:29.20#ibcon#*after write, iclass 19, count 0 2006.197.08:13:29.20#ibcon#*before return 0, iclass 19, count 0 2006.197.08:13:29.20#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.197.08:13:29.20#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.197.08:13:29.20#ibcon#about to clear, iclass 19 cls_cnt 0 2006.197.08:13:29.20#ibcon#cleared, iclass 19 cls_cnt 0 2006.197.08:13:29.20$vc4f8/va=6,6 2006.197.08:13:29.20#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.197.08:13:29.20#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.197.08:13:29.20#ibcon#ireg 11 cls_cnt 2 2006.197.08:13:29.20#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.197.08:13:29.26#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.197.08:13:29.26#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.197.08:13:29.26#ibcon#enter wrdev, iclass 21, count 2 2006.197.08:13:29.26#ibcon#first serial, iclass 21, count 2 2006.197.08:13:29.26#ibcon#enter sib2, iclass 21, count 2 2006.197.08:13:29.26#ibcon#flushed, iclass 21, count 2 2006.197.08:13:29.26#ibcon#about to write, iclass 21, count 2 2006.197.08:13:29.26#ibcon#wrote, iclass 21, count 2 2006.197.08:13:29.26#ibcon#about to read 3, iclass 21, count 2 2006.197.08:13:29.28#ibcon#read 3, iclass 21, count 2 2006.197.08:13:29.28#ibcon#about to read 4, iclass 21, count 2 2006.197.08:13:29.28#ibcon#read 4, iclass 21, count 2 2006.197.08:13:29.28#ibcon#about to read 5, iclass 21, count 2 2006.197.08:13:29.28#ibcon#read 5, iclass 21, count 2 2006.197.08:13:29.28#ibcon#about to read 6, iclass 21, count 2 2006.197.08:13:29.28#ibcon#read 6, iclass 21, count 2 2006.197.08:13:29.28#ibcon#end of sib2, iclass 21, count 2 2006.197.08:13:29.28#ibcon#*mode == 0, iclass 21, count 2 2006.197.08:13:29.28#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.197.08:13:29.28#ibcon#[25=AT06-06\r\n] 2006.197.08:13:29.28#ibcon#*before write, iclass 21, count 2 2006.197.08:13:29.28#ibcon#enter sib2, iclass 21, count 2 2006.197.08:13:29.28#ibcon#flushed, iclass 21, count 2 2006.197.08:13:29.28#ibcon#about to write, iclass 21, count 2 2006.197.08:13:29.28#ibcon#wrote, iclass 21, count 2 2006.197.08:13:29.28#ibcon#about to read 3, iclass 21, count 2 2006.197.08:13:29.31#ibcon#read 3, iclass 21, count 2 2006.197.08:13:29.31#ibcon#about to read 4, iclass 21, count 2 2006.197.08:13:29.31#ibcon#read 4, iclass 21, count 2 2006.197.08:13:29.31#ibcon#about to read 5, iclass 21, count 2 2006.197.08:13:29.31#ibcon#read 5, iclass 21, count 2 2006.197.08:13:29.31#ibcon#about to read 6, iclass 21, count 2 2006.197.08:13:29.31#ibcon#read 6, iclass 21, count 2 2006.197.08:13:29.31#ibcon#end of sib2, iclass 21, count 2 2006.197.08:13:29.31#ibcon#*after write, iclass 21, count 2 2006.197.08:13:29.31#ibcon#*before return 0, iclass 21, count 2 2006.197.08:13:29.31#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.197.08:13:29.31#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.197.08:13:29.31#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.197.08:13:29.31#ibcon#ireg 7 cls_cnt 0 2006.197.08:13:29.31#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.197.08:13:29.43#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.197.08:13:29.43#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.197.08:13:29.43#ibcon#enter wrdev, iclass 21, count 0 2006.197.08:13:29.43#ibcon#first serial, iclass 21, count 0 2006.197.08:13:29.43#ibcon#enter sib2, iclass 21, count 0 2006.197.08:13:29.43#ibcon#flushed, iclass 21, count 0 2006.197.08:13:29.43#ibcon#about to write, iclass 21, count 0 2006.197.08:13:29.43#ibcon#wrote, iclass 21, count 0 2006.197.08:13:29.43#ibcon#about to read 3, iclass 21, count 0 2006.197.08:13:29.45#ibcon#read 3, iclass 21, count 0 2006.197.08:13:29.45#ibcon#about to read 4, iclass 21, count 0 2006.197.08:13:29.45#ibcon#read 4, iclass 21, count 0 2006.197.08:13:29.45#ibcon#about to read 5, iclass 21, count 0 2006.197.08:13:29.45#ibcon#read 5, iclass 21, count 0 2006.197.08:13:29.45#ibcon#about to read 6, iclass 21, count 0 2006.197.08:13:29.45#ibcon#read 6, iclass 21, count 0 2006.197.08:13:29.45#ibcon#end of sib2, iclass 21, count 0 2006.197.08:13:29.45#ibcon#*mode == 0, iclass 21, count 0 2006.197.08:13:29.45#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.197.08:13:29.45#ibcon#[25=USB\r\n] 2006.197.08:13:29.45#ibcon#*before write, iclass 21, count 0 2006.197.08:13:29.45#ibcon#enter sib2, iclass 21, count 0 2006.197.08:13:29.45#ibcon#flushed, iclass 21, count 0 2006.197.08:13:29.45#ibcon#about to write, iclass 21, count 0 2006.197.08:13:29.45#ibcon#wrote, iclass 21, count 0 2006.197.08:13:29.45#ibcon#about to read 3, iclass 21, count 0 2006.197.08:13:29.48#ibcon#read 3, iclass 21, count 0 2006.197.08:13:29.48#ibcon#about to read 4, iclass 21, count 0 2006.197.08:13:29.48#ibcon#read 4, iclass 21, count 0 2006.197.08:13:29.48#ibcon#about to read 5, iclass 21, count 0 2006.197.08:13:29.48#ibcon#read 5, iclass 21, count 0 2006.197.08:13:29.48#ibcon#about to read 6, iclass 21, count 0 2006.197.08:13:29.48#ibcon#read 6, iclass 21, count 0 2006.197.08:13:29.48#ibcon#end of sib2, iclass 21, count 0 2006.197.08:13:29.48#ibcon#*after write, iclass 21, count 0 2006.197.08:13:29.48#ibcon#*before return 0, iclass 21, count 0 2006.197.08:13:29.48#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.197.08:13:29.48#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.197.08:13:29.48#ibcon#about to clear, iclass 21 cls_cnt 0 2006.197.08:13:29.48#ibcon#cleared, iclass 21 cls_cnt 0 2006.197.08:13:29.48$vc4f8/valo=7,832.99 2006.197.08:13:29.48#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.197.08:13:29.48#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.197.08:13:29.48#ibcon#ireg 17 cls_cnt 0 2006.197.08:13:29.48#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.197.08:13:29.48#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.197.08:13:29.48#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.197.08:13:29.48#ibcon#enter wrdev, iclass 23, count 0 2006.197.08:13:29.48#ibcon#first serial, iclass 23, count 0 2006.197.08:13:29.48#ibcon#enter sib2, iclass 23, count 0 2006.197.08:13:29.48#ibcon#flushed, iclass 23, count 0 2006.197.08:13:29.48#ibcon#about to write, iclass 23, count 0 2006.197.08:13:29.48#ibcon#wrote, iclass 23, count 0 2006.197.08:13:29.48#ibcon#about to read 3, iclass 23, count 0 2006.197.08:13:29.50#ibcon#read 3, iclass 23, count 0 2006.197.08:13:29.50#ibcon#about to read 4, iclass 23, count 0 2006.197.08:13:29.50#ibcon#read 4, iclass 23, count 0 2006.197.08:13:29.50#ibcon#about to read 5, iclass 23, count 0 2006.197.08:13:29.50#ibcon#read 5, iclass 23, count 0 2006.197.08:13:29.50#ibcon#about to read 6, iclass 23, count 0 2006.197.08:13:29.50#ibcon#read 6, iclass 23, count 0 2006.197.08:13:29.50#ibcon#end of sib2, iclass 23, count 0 2006.197.08:13:29.50#ibcon#*mode == 0, iclass 23, count 0 2006.197.08:13:29.50#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.197.08:13:29.50#ibcon#[26=FRQ=07,832.99\r\n] 2006.197.08:13:29.50#ibcon#*before write, iclass 23, count 0 2006.197.08:13:29.50#ibcon#enter sib2, iclass 23, count 0 2006.197.08:13:29.50#ibcon#flushed, iclass 23, count 0 2006.197.08:13:29.50#ibcon#about to write, iclass 23, count 0 2006.197.08:13:29.50#ibcon#wrote, iclass 23, count 0 2006.197.08:13:29.50#ibcon#about to read 3, iclass 23, count 0 2006.197.08:13:29.54#ibcon#read 3, iclass 23, count 0 2006.197.08:13:29.54#ibcon#about to read 4, iclass 23, count 0 2006.197.08:13:29.54#ibcon#read 4, iclass 23, count 0 2006.197.08:13:29.54#ibcon#about to read 5, iclass 23, count 0 2006.197.08:13:29.54#ibcon#read 5, iclass 23, count 0 2006.197.08:13:29.54#ibcon#about to read 6, iclass 23, count 0 2006.197.08:13:29.54#ibcon#read 6, iclass 23, count 0 2006.197.08:13:29.54#ibcon#end of sib2, iclass 23, count 0 2006.197.08:13:29.54#ibcon#*after write, iclass 23, count 0 2006.197.08:13:29.54#ibcon#*before return 0, iclass 23, count 0 2006.197.08:13:29.54#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.197.08:13:29.54#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.197.08:13:29.54#ibcon#about to clear, iclass 23 cls_cnt 0 2006.197.08:13:29.54#ibcon#cleared, iclass 23 cls_cnt 0 2006.197.08:13:29.54$vc4f8/va=7,6 2006.197.08:13:29.54#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.197.08:13:29.54#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.197.08:13:29.54#ibcon#ireg 11 cls_cnt 2 2006.197.08:13:29.54#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.197.08:13:29.60#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.197.08:13:29.60#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.197.08:13:29.60#ibcon#enter wrdev, iclass 25, count 2 2006.197.08:13:29.60#ibcon#first serial, iclass 25, count 2 2006.197.08:13:29.60#ibcon#enter sib2, iclass 25, count 2 2006.197.08:13:29.60#ibcon#flushed, iclass 25, count 2 2006.197.08:13:29.60#ibcon#about to write, iclass 25, count 2 2006.197.08:13:29.60#ibcon#wrote, iclass 25, count 2 2006.197.08:13:29.60#ibcon#about to read 3, iclass 25, count 2 2006.197.08:13:29.62#ibcon#read 3, iclass 25, count 2 2006.197.08:13:29.62#ibcon#about to read 4, iclass 25, count 2 2006.197.08:13:29.62#ibcon#read 4, iclass 25, count 2 2006.197.08:13:29.62#ibcon#about to read 5, iclass 25, count 2 2006.197.08:13:29.62#ibcon#read 5, iclass 25, count 2 2006.197.08:13:29.62#ibcon#about to read 6, iclass 25, count 2 2006.197.08:13:29.62#ibcon#read 6, iclass 25, count 2 2006.197.08:13:29.62#ibcon#end of sib2, iclass 25, count 2 2006.197.08:13:29.62#ibcon#*mode == 0, iclass 25, count 2 2006.197.08:13:29.62#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.197.08:13:29.62#ibcon#[25=AT07-06\r\n] 2006.197.08:13:29.62#ibcon#*before write, iclass 25, count 2 2006.197.08:13:29.62#ibcon#enter sib2, iclass 25, count 2 2006.197.08:13:29.62#ibcon#flushed, iclass 25, count 2 2006.197.08:13:29.62#ibcon#about to write, iclass 25, count 2 2006.197.08:13:29.62#ibcon#wrote, iclass 25, count 2 2006.197.08:13:29.62#ibcon#about to read 3, iclass 25, count 2 2006.197.08:13:29.65#ibcon#read 3, iclass 25, count 2 2006.197.08:13:29.65#ibcon#about to read 4, iclass 25, count 2 2006.197.08:13:29.65#ibcon#read 4, iclass 25, count 2 2006.197.08:13:29.65#ibcon#about to read 5, iclass 25, count 2 2006.197.08:13:29.65#ibcon#read 5, iclass 25, count 2 2006.197.08:13:29.65#ibcon#about to read 6, iclass 25, count 2 2006.197.08:13:29.65#ibcon#read 6, iclass 25, count 2 2006.197.08:13:29.65#ibcon#end of sib2, iclass 25, count 2 2006.197.08:13:29.65#ibcon#*after write, iclass 25, count 2 2006.197.08:13:29.65#ibcon#*before return 0, iclass 25, count 2 2006.197.08:13:29.65#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.197.08:13:29.65#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.197.08:13:29.65#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.197.08:13:29.65#ibcon#ireg 7 cls_cnt 0 2006.197.08:13:29.65#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.197.08:13:29.77#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.197.08:13:29.77#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.197.08:13:29.77#ibcon#enter wrdev, iclass 25, count 0 2006.197.08:13:29.77#ibcon#first serial, iclass 25, count 0 2006.197.08:13:29.77#ibcon#enter sib2, iclass 25, count 0 2006.197.08:13:29.77#ibcon#flushed, iclass 25, count 0 2006.197.08:13:29.77#ibcon#about to write, iclass 25, count 0 2006.197.08:13:29.77#ibcon#wrote, iclass 25, count 0 2006.197.08:13:29.77#ibcon#about to read 3, iclass 25, count 0 2006.197.08:13:29.79#ibcon#read 3, iclass 25, count 0 2006.197.08:13:29.79#ibcon#about to read 4, iclass 25, count 0 2006.197.08:13:29.79#ibcon#read 4, iclass 25, count 0 2006.197.08:13:29.79#ibcon#about to read 5, iclass 25, count 0 2006.197.08:13:29.79#ibcon#read 5, iclass 25, count 0 2006.197.08:13:29.79#ibcon#about to read 6, iclass 25, count 0 2006.197.08:13:29.79#ibcon#read 6, iclass 25, count 0 2006.197.08:13:29.79#ibcon#end of sib2, iclass 25, count 0 2006.197.08:13:29.79#ibcon#*mode == 0, iclass 25, count 0 2006.197.08:13:29.79#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.197.08:13:29.79#ibcon#[25=USB\r\n] 2006.197.08:13:29.79#ibcon#*before write, iclass 25, count 0 2006.197.08:13:29.79#ibcon#enter sib2, iclass 25, count 0 2006.197.08:13:29.79#ibcon#flushed, iclass 25, count 0 2006.197.08:13:29.79#ibcon#about to write, iclass 25, count 0 2006.197.08:13:29.79#ibcon#wrote, iclass 25, count 0 2006.197.08:13:29.79#ibcon#about to read 3, iclass 25, count 0 2006.197.08:13:29.82#ibcon#read 3, iclass 25, count 0 2006.197.08:13:29.82#ibcon#about to read 4, iclass 25, count 0 2006.197.08:13:29.82#ibcon#read 4, iclass 25, count 0 2006.197.08:13:29.82#ibcon#about to read 5, iclass 25, count 0 2006.197.08:13:29.82#ibcon#read 5, iclass 25, count 0 2006.197.08:13:29.82#ibcon#about to read 6, iclass 25, count 0 2006.197.08:13:29.82#ibcon#read 6, iclass 25, count 0 2006.197.08:13:29.82#ibcon#end of sib2, iclass 25, count 0 2006.197.08:13:29.82#ibcon#*after write, iclass 25, count 0 2006.197.08:13:29.82#ibcon#*before return 0, iclass 25, count 0 2006.197.08:13:29.82#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.197.08:13:29.82#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.197.08:13:29.82#ibcon#about to clear, iclass 25 cls_cnt 0 2006.197.08:13:29.82#ibcon#cleared, iclass 25 cls_cnt 0 2006.197.08:13:29.82$vc4f8/valo=8,852.99 2006.197.08:13:29.82#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.197.08:13:29.82#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.197.08:13:29.82#ibcon#ireg 17 cls_cnt 0 2006.197.08:13:29.82#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.197.08:13:29.82#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.197.08:13:29.82#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.197.08:13:29.82#ibcon#enter wrdev, iclass 27, count 0 2006.197.08:13:29.82#ibcon#first serial, iclass 27, count 0 2006.197.08:13:29.82#ibcon#enter sib2, iclass 27, count 0 2006.197.08:13:29.82#ibcon#flushed, iclass 27, count 0 2006.197.08:13:29.82#ibcon#about to write, iclass 27, count 0 2006.197.08:13:29.82#ibcon#wrote, iclass 27, count 0 2006.197.08:13:29.82#ibcon#about to read 3, iclass 27, count 0 2006.197.08:13:29.84#ibcon#read 3, iclass 27, count 0 2006.197.08:13:29.84#ibcon#about to read 4, iclass 27, count 0 2006.197.08:13:29.84#ibcon#read 4, iclass 27, count 0 2006.197.08:13:29.84#ibcon#about to read 5, iclass 27, count 0 2006.197.08:13:29.84#ibcon#read 5, iclass 27, count 0 2006.197.08:13:29.84#ibcon#about to read 6, iclass 27, count 0 2006.197.08:13:29.84#ibcon#read 6, iclass 27, count 0 2006.197.08:13:29.84#ibcon#end of sib2, iclass 27, count 0 2006.197.08:13:29.84#ibcon#*mode == 0, iclass 27, count 0 2006.197.08:13:29.84#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.197.08:13:29.84#ibcon#[26=FRQ=08,852.99\r\n] 2006.197.08:13:29.84#ibcon#*before write, iclass 27, count 0 2006.197.08:13:29.84#ibcon#enter sib2, iclass 27, count 0 2006.197.08:13:29.84#ibcon#flushed, iclass 27, count 0 2006.197.08:13:29.84#ibcon#about to write, iclass 27, count 0 2006.197.08:13:29.84#ibcon#wrote, iclass 27, count 0 2006.197.08:13:29.84#ibcon#about to read 3, iclass 27, count 0 2006.197.08:13:29.88#ibcon#read 3, iclass 27, count 0 2006.197.08:13:29.88#ibcon#about to read 4, iclass 27, count 0 2006.197.08:13:29.88#ibcon#read 4, iclass 27, count 0 2006.197.08:13:29.88#ibcon#about to read 5, iclass 27, count 0 2006.197.08:13:29.88#ibcon#read 5, iclass 27, count 0 2006.197.08:13:29.88#ibcon#about to read 6, iclass 27, count 0 2006.197.08:13:29.88#ibcon#read 6, iclass 27, count 0 2006.197.08:13:29.88#ibcon#end of sib2, iclass 27, count 0 2006.197.08:13:29.88#ibcon#*after write, iclass 27, count 0 2006.197.08:13:29.88#ibcon#*before return 0, iclass 27, count 0 2006.197.08:13:29.88#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.197.08:13:29.88#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.197.08:13:29.88#ibcon#about to clear, iclass 27 cls_cnt 0 2006.197.08:13:29.88#ibcon#cleared, iclass 27 cls_cnt 0 2006.197.08:13:29.88$vc4f8/va=8,7 2006.197.08:13:29.88#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.197.08:13:29.88#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.197.08:13:29.88#ibcon#ireg 11 cls_cnt 2 2006.197.08:13:29.88#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.197.08:13:29.94#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.197.08:13:29.94#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.197.08:13:29.94#ibcon#enter wrdev, iclass 29, count 2 2006.197.08:13:29.94#ibcon#first serial, iclass 29, count 2 2006.197.08:13:29.94#ibcon#enter sib2, iclass 29, count 2 2006.197.08:13:29.94#ibcon#flushed, iclass 29, count 2 2006.197.08:13:29.94#ibcon#about to write, iclass 29, count 2 2006.197.08:13:29.94#ibcon#wrote, iclass 29, count 2 2006.197.08:13:29.94#ibcon#about to read 3, iclass 29, count 2 2006.197.08:13:29.96#ibcon#read 3, iclass 29, count 2 2006.197.08:13:29.96#ibcon#about to read 4, iclass 29, count 2 2006.197.08:13:29.96#ibcon#read 4, iclass 29, count 2 2006.197.08:13:29.96#ibcon#about to read 5, iclass 29, count 2 2006.197.08:13:29.96#ibcon#read 5, iclass 29, count 2 2006.197.08:13:29.96#ibcon#about to read 6, iclass 29, count 2 2006.197.08:13:29.96#ibcon#read 6, iclass 29, count 2 2006.197.08:13:29.96#ibcon#end of sib2, iclass 29, count 2 2006.197.08:13:29.96#ibcon#*mode == 0, iclass 29, count 2 2006.197.08:13:29.96#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.197.08:13:29.96#ibcon#[25=AT08-07\r\n] 2006.197.08:13:29.96#ibcon#*before write, iclass 29, count 2 2006.197.08:13:29.96#ibcon#enter sib2, iclass 29, count 2 2006.197.08:13:29.96#ibcon#flushed, iclass 29, count 2 2006.197.08:13:29.96#ibcon#about to write, iclass 29, count 2 2006.197.08:13:29.96#ibcon#wrote, iclass 29, count 2 2006.197.08:13:29.96#ibcon#about to read 3, iclass 29, count 2 2006.197.08:13:29.99#ibcon#read 3, iclass 29, count 2 2006.197.08:13:29.99#ibcon#about to read 4, iclass 29, count 2 2006.197.08:13:29.99#ibcon#read 4, iclass 29, count 2 2006.197.08:13:29.99#ibcon#about to read 5, iclass 29, count 2 2006.197.08:13:29.99#ibcon#read 5, iclass 29, count 2 2006.197.08:13:29.99#ibcon#about to read 6, iclass 29, count 2 2006.197.08:13:29.99#ibcon#read 6, iclass 29, count 2 2006.197.08:13:29.99#ibcon#end of sib2, iclass 29, count 2 2006.197.08:13:29.99#ibcon#*after write, iclass 29, count 2 2006.197.08:13:29.99#ibcon#*before return 0, iclass 29, count 2 2006.197.08:13:29.99#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.197.08:13:29.99#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.197.08:13:29.99#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.197.08:13:29.99#ibcon#ireg 7 cls_cnt 0 2006.197.08:13:29.99#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.197.08:13:30.11#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.197.08:13:30.11#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.197.08:13:30.11#ibcon#enter wrdev, iclass 29, count 0 2006.197.08:13:30.11#ibcon#first serial, iclass 29, count 0 2006.197.08:13:30.11#ibcon#enter sib2, iclass 29, count 0 2006.197.08:13:30.11#ibcon#flushed, iclass 29, count 0 2006.197.08:13:30.11#ibcon#about to write, iclass 29, count 0 2006.197.08:13:30.11#ibcon#wrote, iclass 29, count 0 2006.197.08:13:30.11#ibcon#about to read 3, iclass 29, count 0 2006.197.08:13:30.13#ibcon#read 3, iclass 29, count 0 2006.197.08:13:30.13#ibcon#about to read 4, iclass 29, count 0 2006.197.08:13:30.13#ibcon#read 4, iclass 29, count 0 2006.197.08:13:30.13#ibcon#about to read 5, iclass 29, count 0 2006.197.08:13:30.13#ibcon#read 5, iclass 29, count 0 2006.197.08:13:30.13#ibcon#about to read 6, iclass 29, count 0 2006.197.08:13:30.13#ibcon#read 6, iclass 29, count 0 2006.197.08:13:30.13#ibcon#end of sib2, iclass 29, count 0 2006.197.08:13:30.13#ibcon#*mode == 0, iclass 29, count 0 2006.197.08:13:30.13#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.197.08:13:30.13#ibcon#[25=USB\r\n] 2006.197.08:13:30.13#ibcon#*before write, iclass 29, count 0 2006.197.08:13:30.13#ibcon#enter sib2, iclass 29, count 0 2006.197.08:13:30.13#ibcon#flushed, iclass 29, count 0 2006.197.08:13:30.13#ibcon#about to write, iclass 29, count 0 2006.197.08:13:30.13#ibcon#wrote, iclass 29, count 0 2006.197.08:13:30.13#ibcon#about to read 3, iclass 29, count 0 2006.197.08:13:30.16#ibcon#read 3, iclass 29, count 0 2006.197.08:13:30.16#ibcon#about to read 4, iclass 29, count 0 2006.197.08:13:30.16#ibcon#read 4, iclass 29, count 0 2006.197.08:13:30.16#ibcon#about to read 5, iclass 29, count 0 2006.197.08:13:30.16#ibcon#read 5, iclass 29, count 0 2006.197.08:13:30.16#ibcon#about to read 6, iclass 29, count 0 2006.197.08:13:30.16#ibcon#read 6, iclass 29, count 0 2006.197.08:13:30.16#ibcon#end of sib2, iclass 29, count 0 2006.197.08:13:30.16#ibcon#*after write, iclass 29, count 0 2006.197.08:13:30.16#ibcon#*before return 0, iclass 29, count 0 2006.197.08:13:30.16#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.197.08:13:30.16#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.197.08:13:30.16#ibcon#about to clear, iclass 29 cls_cnt 0 2006.197.08:13:30.16#ibcon#cleared, iclass 29 cls_cnt 0 2006.197.08:13:30.16$vc4f8/vblo=1,632.99 2006.197.08:13:30.16#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.197.08:13:30.16#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.197.08:13:30.16#ibcon#ireg 17 cls_cnt 0 2006.197.08:13:30.16#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.197.08:13:30.16#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.197.08:13:30.16#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.197.08:13:30.16#ibcon#enter wrdev, iclass 31, count 0 2006.197.08:13:30.16#ibcon#first serial, iclass 31, count 0 2006.197.08:13:30.16#ibcon#enter sib2, iclass 31, count 0 2006.197.08:13:30.16#ibcon#flushed, iclass 31, count 0 2006.197.08:13:30.16#ibcon#about to write, iclass 31, count 0 2006.197.08:13:30.16#ibcon#wrote, iclass 31, count 0 2006.197.08:13:30.16#ibcon#about to read 3, iclass 31, count 0 2006.197.08:13:30.18#ibcon#read 3, iclass 31, count 0 2006.197.08:13:30.18#ibcon#about to read 4, iclass 31, count 0 2006.197.08:13:30.18#ibcon#read 4, iclass 31, count 0 2006.197.08:13:30.18#ibcon#about to read 5, iclass 31, count 0 2006.197.08:13:30.18#ibcon#read 5, iclass 31, count 0 2006.197.08:13:30.18#ibcon#about to read 6, iclass 31, count 0 2006.197.08:13:30.18#ibcon#read 6, iclass 31, count 0 2006.197.08:13:30.18#ibcon#end of sib2, iclass 31, count 0 2006.197.08:13:30.18#ibcon#*mode == 0, iclass 31, count 0 2006.197.08:13:30.18#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.197.08:13:30.18#ibcon#[28=FRQ=01,632.99\r\n] 2006.197.08:13:30.18#ibcon#*before write, iclass 31, count 0 2006.197.08:13:30.18#ibcon#enter sib2, iclass 31, count 0 2006.197.08:13:30.18#ibcon#flushed, iclass 31, count 0 2006.197.08:13:30.18#ibcon#about to write, iclass 31, count 0 2006.197.08:13:30.18#ibcon#wrote, iclass 31, count 0 2006.197.08:13:30.18#ibcon#about to read 3, iclass 31, count 0 2006.197.08:13:30.22#ibcon#read 3, iclass 31, count 0 2006.197.08:13:30.22#ibcon#about to read 4, iclass 31, count 0 2006.197.08:13:30.22#ibcon#read 4, iclass 31, count 0 2006.197.08:13:30.22#ibcon#about to read 5, iclass 31, count 0 2006.197.08:13:30.22#ibcon#read 5, iclass 31, count 0 2006.197.08:13:30.22#ibcon#about to read 6, iclass 31, count 0 2006.197.08:13:30.22#ibcon#read 6, iclass 31, count 0 2006.197.08:13:30.22#ibcon#end of sib2, iclass 31, count 0 2006.197.08:13:30.22#ibcon#*after write, iclass 31, count 0 2006.197.08:13:30.22#ibcon#*before return 0, iclass 31, count 0 2006.197.08:13:30.22#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.197.08:13:30.22#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.197.08:13:30.22#ibcon#about to clear, iclass 31 cls_cnt 0 2006.197.08:13:30.22#ibcon#cleared, iclass 31 cls_cnt 0 2006.197.08:13:30.22$vc4f8/vb=1,4 2006.197.08:13:30.22#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.197.08:13:30.22#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.197.08:13:30.22#ibcon#ireg 11 cls_cnt 2 2006.197.08:13:30.22#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.197.08:13:30.22#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.197.08:13:30.22#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.197.08:13:30.22#ibcon#enter wrdev, iclass 33, count 2 2006.197.08:13:30.22#ibcon#first serial, iclass 33, count 2 2006.197.08:13:30.22#ibcon#enter sib2, iclass 33, count 2 2006.197.08:13:30.22#ibcon#flushed, iclass 33, count 2 2006.197.08:13:30.22#ibcon#about to write, iclass 33, count 2 2006.197.08:13:30.22#ibcon#wrote, iclass 33, count 2 2006.197.08:13:30.22#ibcon#about to read 3, iclass 33, count 2 2006.197.08:13:30.24#ibcon#read 3, iclass 33, count 2 2006.197.08:13:30.24#ibcon#about to read 4, iclass 33, count 2 2006.197.08:13:30.24#ibcon#read 4, iclass 33, count 2 2006.197.08:13:30.24#ibcon#about to read 5, iclass 33, count 2 2006.197.08:13:30.24#ibcon#read 5, iclass 33, count 2 2006.197.08:13:30.24#ibcon#about to read 6, iclass 33, count 2 2006.197.08:13:30.24#ibcon#read 6, iclass 33, count 2 2006.197.08:13:30.24#ibcon#end of sib2, iclass 33, count 2 2006.197.08:13:30.24#ibcon#*mode == 0, iclass 33, count 2 2006.197.08:13:30.24#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.197.08:13:30.24#ibcon#[27=AT01-04\r\n] 2006.197.08:13:30.24#ibcon#*before write, iclass 33, count 2 2006.197.08:13:30.24#ibcon#enter sib2, iclass 33, count 2 2006.197.08:13:30.24#ibcon#flushed, iclass 33, count 2 2006.197.08:13:30.24#ibcon#about to write, iclass 33, count 2 2006.197.08:13:30.24#ibcon#wrote, iclass 33, count 2 2006.197.08:13:30.24#ibcon#about to read 3, iclass 33, count 2 2006.197.08:13:30.27#ibcon#read 3, iclass 33, count 2 2006.197.08:13:30.27#ibcon#about to read 4, iclass 33, count 2 2006.197.08:13:30.27#ibcon#read 4, iclass 33, count 2 2006.197.08:13:30.27#ibcon#about to read 5, iclass 33, count 2 2006.197.08:13:30.27#ibcon#read 5, iclass 33, count 2 2006.197.08:13:30.27#ibcon#about to read 6, iclass 33, count 2 2006.197.08:13:30.27#ibcon#read 6, iclass 33, count 2 2006.197.08:13:30.27#ibcon#end of sib2, iclass 33, count 2 2006.197.08:13:30.27#ibcon#*after write, iclass 33, count 2 2006.197.08:13:30.27#ibcon#*before return 0, iclass 33, count 2 2006.197.08:13:30.27#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.197.08:13:30.27#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.197.08:13:30.27#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.197.08:13:30.27#ibcon#ireg 7 cls_cnt 0 2006.197.08:13:30.27#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.197.08:13:30.39#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.197.08:13:30.39#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.197.08:13:30.39#ibcon#enter wrdev, iclass 33, count 0 2006.197.08:13:30.39#ibcon#first serial, iclass 33, count 0 2006.197.08:13:30.39#ibcon#enter sib2, iclass 33, count 0 2006.197.08:13:30.39#ibcon#flushed, iclass 33, count 0 2006.197.08:13:30.39#ibcon#about to write, iclass 33, count 0 2006.197.08:13:30.39#ibcon#wrote, iclass 33, count 0 2006.197.08:13:30.39#ibcon#about to read 3, iclass 33, count 0 2006.197.08:13:30.41#ibcon#read 3, iclass 33, count 0 2006.197.08:13:30.41#ibcon#about to read 4, iclass 33, count 0 2006.197.08:13:30.41#ibcon#read 4, iclass 33, count 0 2006.197.08:13:30.41#ibcon#about to read 5, iclass 33, count 0 2006.197.08:13:30.41#ibcon#read 5, iclass 33, count 0 2006.197.08:13:30.41#ibcon#about to read 6, iclass 33, count 0 2006.197.08:13:30.41#ibcon#read 6, iclass 33, count 0 2006.197.08:13:30.41#ibcon#end of sib2, iclass 33, count 0 2006.197.08:13:30.41#ibcon#*mode == 0, iclass 33, count 0 2006.197.08:13:30.41#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.197.08:13:30.41#ibcon#[27=USB\r\n] 2006.197.08:13:30.41#ibcon#*before write, iclass 33, count 0 2006.197.08:13:30.41#ibcon#enter sib2, iclass 33, count 0 2006.197.08:13:30.41#ibcon#flushed, iclass 33, count 0 2006.197.08:13:30.41#ibcon#about to write, iclass 33, count 0 2006.197.08:13:30.41#ibcon#wrote, iclass 33, count 0 2006.197.08:13:30.41#ibcon#about to read 3, iclass 33, count 0 2006.197.08:13:30.44#ibcon#read 3, iclass 33, count 0 2006.197.08:13:30.44#ibcon#about to read 4, iclass 33, count 0 2006.197.08:13:30.44#ibcon#read 4, iclass 33, count 0 2006.197.08:13:30.44#ibcon#about to read 5, iclass 33, count 0 2006.197.08:13:30.44#ibcon#read 5, iclass 33, count 0 2006.197.08:13:30.44#ibcon#about to read 6, iclass 33, count 0 2006.197.08:13:30.44#ibcon#read 6, iclass 33, count 0 2006.197.08:13:30.44#ibcon#end of sib2, iclass 33, count 0 2006.197.08:13:30.44#ibcon#*after write, iclass 33, count 0 2006.197.08:13:30.44#ibcon#*before return 0, iclass 33, count 0 2006.197.08:13:30.44#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.197.08:13:30.44#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.197.08:13:30.44#ibcon#about to clear, iclass 33 cls_cnt 0 2006.197.08:13:30.44#ibcon#cleared, iclass 33 cls_cnt 0 2006.197.08:13:30.44$vc4f8/vblo=2,640.99 2006.197.08:13:30.44#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.197.08:13:30.44#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.197.08:13:30.44#ibcon#ireg 17 cls_cnt 0 2006.197.08:13:30.44#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.197.08:13:30.44#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.197.08:13:30.44#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.197.08:13:30.44#ibcon#enter wrdev, iclass 35, count 0 2006.197.08:13:30.44#ibcon#first serial, iclass 35, count 0 2006.197.08:13:30.44#ibcon#enter sib2, iclass 35, count 0 2006.197.08:13:30.44#ibcon#flushed, iclass 35, count 0 2006.197.08:13:30.44#ibcon#about to write, iclass 35, count 0 2006.197.08:13:30.44#ibcon#wrote, iclass 35, count 0 2006.197.08:13:30.44#ibcon#about to read 3, iclass 35, count 0 2006.197.08:13:30.46#ibcon#read 3, iclass 35, count 0 2006.197.08:13:30.46#ibcon#about to read 4, iclass 35, count 0 2006.197.08:13:30.46#ibcon#read 4, iclass 35, count 0 2006.197.08:13:30.46#ibcon#about to read 5, iclass 35, count 0 2006.197.08:13:30.46#ibcon#read 5, iclass 35, count 0 2006.197.08:13:30.46#ibcon#about to read 6, iclass 35, count 0 2006.197.08:13:30.46#ibcon#read 6, iclass 35, count 0 2006.197.08:13:30.46#ibcon#end of sib2, iclass 35, count 0 2006.197.08:13:30.46#ibcon#*mode == 0, iclass 35, count 0 2006.197.08:13:30.46#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.197.08:13:30.46#ibcon#[28=FRQ=02,640.99\r\n] 2006.197.08:13:30.46#ibcon#*before write, iclass 35, count 0 2006.197.08:13:30.46#ibcon#enter sib2, iclass 35, count 0 2006.197.08:13:30.46#ibcon#flushed, iclass 35, count 0 2006.197.08:13:30.46#ibcon#about to write, iclass 35, count 0 2006.197.08:13:30.46#ibcon#wrote, iclass 35, count 0 2006.197.08:13:30.46#ibcon#about to read 3, iclass 35, count 0 2006.197.08:13:30.50#ibcon#read 3, iclass 35, count 0 2006.197.08:13:30.50#ibcon#about to read 4, iclass 35, count 0 2006.197.08:13:30.50#ibcon#read 4, iclass 35, count 0 2006.197.08:13:30.50#ibcon#about to read 5, iclass 35, count 0 2006.197.08:13:30.50#ibcon#read 5, iclass 35, count 0 2006.197.08:13:30.50#ibcon#about to read 6, iclass 35, count 0 2006.197.08:13:30.50#ibcon#read 6, iclass 35, count 0 2006.197.08:13:30.50#ibcon#end of sib2, iclass 35, count 0 2006.197.08:13:30.50#ibcon#*after write, iclass 35, count 0 2006.197.08:13:30.50#ibcon#*before return 0, iclass 35, count 0 2006.197.08:13:30.50#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.197.08:13:30.50#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.197.08:13:30.50#ibcon#about to clear, iclass 35 cls_cnt 0 2006.197.08:13:30.50#ibcon#cleared, iclass 35 cls_cnt 0 2006.197.08:13:30.50$vc4f8/vb=2,4 2006.197.08:13:30.50#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.197.08:13:30.50#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.197.08:13:30.50#ibcon#ireg 11 cls_cnt 2 2006.197.08:13:30.50#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.197.08:13:30.56#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.197.08:13:30.56#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.197.08:13:30.56#ibcon#enter wrdev, iclass 37, count 2 2006.197.08:13:30.56#ibcon#first serial, iclass 37, count 2 2006.197.08:13:30.56#ibcon#enter sib2, iclass 37, count 2 2006.197.08:13:30.56#ibcon#flushed, iclass 37, count 2 2006.197.08:13:30.56#ibcon#about to write, iclass 37, count 2 2006.197.08:13:30.56#ibcon#wrote, iclass 37, count 2 2006.197.08:13:30.56#ibcon#about to read 3, iclass 37, count 2 2006.197.08:13:30.58#ibcon#read 3, iclass 37, count 2 2006.197.08:13:30.58#ibcon#about to read 4, iclass 37, count 2 2006.197.08:13:30.58#ibcon#read 4, iclass 37, count 2 2006.197.08:13:30.58#ibcon#about to read 5, iclass 37, count 2 2006.197.08:13:30.58#ibcon#read 5, iclass 37, count 2 2006.197.08:13:30.58#ibcon#about to read 6, iclass 37, count 2 2006.197.08:13:30.58#ibcon#read 6, iclass 37, count 2 2006.197.08:13:30.58#ibcon#end of sib2, iclass 37, count 2 2006.197.08:13:30.58#ibcon#*mode == 0, iclass 37, count 2 2006.197.08:13:30.58#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.197.08:13:30.58#ibcon#[27=AT02-04\r\n] 2006.197.08:13:30.58#ibcon#*before write, iclass 37, count 2 2006.197.08:13:30.58#ibcon#enter sib2, iclass 37, count 2 2006.197.08:13:30.58#ibcon#flushed, iclass 37, count 2 2006.197.08:13:30.58#ibcon#about to write, iclass 37, count 2 2006.197.08:13:30.58#ibcon#wrote, iclass 37, count 2 2006.197.08:13:30.58#ibcon#about to read 3, iclass 37, count 2 2006.197.08:13:30.61#ibcon#read 3, iclass 37, count 2 2006.197.08:13:30.61#ibcon#about to read 4, iclass 37, count 2 2006.197.08:13:30.61#ibcon#read 4, iclass 37, count 2 2006.197.08:13:30.61#ibcon#about to read 5, iclass 37, count 2 2006.197.08:13:30.61#ibcon#read 5, iclass 37, count 2 2006.197.08:13:30.61#ibcon#about to read 6, iclass 37, count 2 2006.197.08:13:30.61#ibcon#read 6, iclass 37, count 2 2006.197.08:13:30.61#ibcon#end of sib2, iclass 37, count 2 2006.197.08:13:30.61#ibcon#*after write, iclass 37, count 2 2006.197.08:13:30.61#ibcon#*before return 0, iclass 37, count 2 2006.197.08:13:30.61#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.197.08:13:30.61#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.197.08:13:30.61#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.197.08:13:30.61#ibcon#ireg 7 cls_cnt 0 2006.197.08:13:30.61#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.197.08:13:30.73#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.197.08:13:30.73#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.197.08:13:30.73#ibcon#enter wrdev, iclass 37, count 0 2006.197.08:13:30.73#ibcon#first serial, iclass 37, count 0 2006.197.08:13:30.73#ibcon#enter sib2, iclass 37, count 0 2006.197.08:13:30.73#ibcon#flushed, iclass 37, count 0 2006.197.08:13:30.73#ibcon#about to write, iclass 37, count 0 2006.197.08:13:30.73#ibcon#wrote, iclass 37, count 0 2006.197.08:13:30.73#ibcon#about to read 3, iclass 37, count 0 2006.197.08:13:30.75#ibcon#read 3, iclass 37, count 0 2006.197.08:13:30.75#ibcon#about to read 4, iclass 37, count 0 2006.197.08:13:30.75#ibcon#read 4, iclass 37, count 0 2006.197.08:13:30.75#ibcon#about to read 5, iclass 37, count 0 2006.197.08:13:30.75#ibcon#read 5, iclass 37, count 0 2006.197.08:13:30.75#ibcon#about to read 6, iclass 37, count 0 2006.197.08:13:30.75#ibcon#read 6, iclass 37, count 0 2006.197.08:13:30.75#ibcon#end of sib2, iclass 37, count 0 2006.197.08:13:30.75#ibcon#*mode == 0, iclass 37, count 0 2006.197.08:13:30.75#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.197.08:13:30.75#ibcon#[27=USB\r\n] 2006.197.08:13:30.75#ibcon#*before write, iclass 37, count 0 2006.197.08:13:30.75#ibcon#enter sib2, iclass 37, count 0 2006.197.08:13:30.75#ibcon#flushed, iclass 37, count 0 2006.197.08:13:30.75#ibcon#about to write, iclass 37, count 0 2006.197.08:13:30.75#ibcon#wrote, iclass 37, count 0 2006.197.08:13:30.75#ibcon#about to read 3, iclass 37, count 0 2006.197.08:13:30.78#ibcon#read 3, iclass 37, count 0 2006.197.08:13:30.78#ibcon#about to read 4, iclass 37, count 0 2006.197.08:13:30.78#ibcon#read 4, iclass 37, count 0 2006.197.08:13:30.78#ibcon#about to read 5, iclass 37, count 0 2006.197.08:13:30.78#ibcon#read 5, iclass 37, count 0 2006.197.08:13:30.78#ibcon#about to read 6, iclass 37, count 0 2006.197.08:13:30.78#ibcon#read 6, iclass 37, count 0 2006.197.08:13:30.78#ibcon#end of sib2, iclass 37, count 0 2006.197.08:13:30.78#ibcon#*after write, iclass 37, count 0 2006.197.08:13:30.78#ibcon#*before return 0, iclass 37, count 0 2006.197.08:13:30.78#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.197.08:13:30.78#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.197.08:13:30.78#ibcon#about to clear, iclass 37 cls_cnt 0 2006.197.08:13:30.78#ibcon#cleared, iclass 37 cls_cnt 0 2006.197.08:13:30.78$vc4f8/vblo=3,656.99 2006.197.08:13:30.78#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.197.08:13:30.78#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.197.08:13:30.78#ibcon#ireg 17 cls_cnt 0 2006.197.08:13:30.78#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.197.08:13:30.78#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.197.08:13:30.78#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.197.08:13:30.78#ibcon#enter wrdev, iclass 39, count 0 2006.197.08:13:30.78#ibcon#first serial, iclass 39, count 0 2006.197.08:13:30.78#ibcon#enter sib2, iclass 39, count 0 2006.197.08:13:30.78#ibcon#flushed, iclass 39, count 0 2006.197.08:13:30.78#ibcon#about to write, iclass 39, count 0 2006.197.08:13:30.78#ibcon#wrote, iclass 39, count 0 2006.197.08:13:30.78#ibcon#about to read 3, iclass 39, count 0 2006.197.08:13:30.80#ibcon#read 3, iclass 39, count 0 2006.197.08:13:30.80#ibcon#about to read 4, iclass 39, count 0 2006.197.08:13:30.80#ibcon#read 4, iclass 39, count 0 2006.197.08:13:30.80#ibcon#about to read 5, iclass 39, count 0 2006.197.08:13:30.80#ibcon#read 5, iclass 39, count 0 2006.197.08:13:30.80#ibcon#about to read 6, iclass 39, count 0 2006.197.08:13:30.80#ibcon#read 6, iclass 39, count 0 2006.197.08:13:30.80#ibcon#end of sib2, iclass 39, count 0 2006.197.08:13:30.80#ibcon#*mode == 0, iclass 39, count 0 2006.197.08:13:30.80#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.197.08:13:30.80#ibcon#[28=FRQ=03,656.99\r\n] 2006.197.08:13:30.80#ibcon#*before write, iclass 39, count 0 2006.197.08:13:30.80#ibcon#enter sib2, iclass 39, count 0 2006.197.08:13:30.80#ibcon#flushed, iclass 39, count 0 2006.197.08:13:30.80#ibcon#about to write, iclass 39, count 0 2006.197.08:13:30.80#ibcon#wrote, iclass 39, count 0 2006.197.08:13:30.80#ibcon#about to read 3, iclass 39, count 0 2006.197.08:13:30.84#ibcon#read 3, iclass 39, count 0 2006.197.08:13:30.84#ibcon#about to read 4, iclass 39, count 0 2006.197.08:13:30.84#ibcon#read 4, iclass 39, count 0 2006.197.08:13:30.84#ibcon#about to read 5, iclass 39, count 0 2006.197.08:13:30.84#ibcon#read 5, iclass 39, count 0 2006.197.08:13:30.84#ibcon#about to read 6, iclass 39, count 0 2006.197.08:13:30.84#ibcon#read 6, iclass 39, count 0 2006.197.08:13:30.84#ibcon#end of sib2, iclass 39, count 0 2006.197.08:13:30.84#ibcon#*after write, iclass 39, count 0 2006.197.08:13:30.84#ibcon#*before return 0, iclass 39, count 0 2006.197.08:13:30.84#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.197.08:13:30.84#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.197.08:13:30.84#ibcon#about to clear, iclass 39 cls_cnt 0 2006.197.08:13:30.84#ibcon#cleared, iclass 39 cls_cnt 0 2006.197.08:13:30.84$vc4f8/vb=3,4 2006.197.08:13:30.84#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.197.08:13:30.84#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.197.08:13:30.84#ibcon#ireg 11 cls_cnt 2 2006.197.08:13:30.84#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.197.08:13:30.90#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.197.08:13:30.90#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.197.08:13:30.90#ibcon#enter wrdev, iclass 3, count 2 2006.197.08:13:30.90#ibcon#first serial, iclass 3, count 2 2006.197.08:13:30.90#ibcon#enter sib2, iclass 3, count 2 2006.197.08:13:30.90#ibcon#flushed, iclass 3, count 2 2006.197.08:13:30.90#ibcon#about to write, iclass 3, count 2 2006.197.08:13:30.90#ibcon#wrote, iclass 3, count 2 2006.197.08:13:30.90#ibcon#about to read 3, iclass 3, count 2 2006.197.08:13:30.92#ibcon#read 3, iclass 3, count 2 2006.197.08:13:30.92#ibcon#about to read 4, iclass 3, count 2 2006.197.08:13:30.92#ibcon#read 4, iclass 3, count 2 2006.197.08:13:30.92#ibcon#about to read 5, iclass 3, count 2 2006.197.08:13:30.92#ibcon#read 5, iclass 3, count 2 2006.197.08:13:30.92#ibcon#about to read 6, iclass 3, count 2 2006.197.08:13:30.92#ibcon#read 6, iclass 3, count 2 2006.197.08:13:30.92#ibcon#end of sib2, iclass 3, count 2 2006.197.08:13:30.92#ibcon#*mode == 0, iclass 3, count 2 2006.197.08:13:30.92#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.197.08:13:30.92#ibcon#[27=AT03-04\r\n] 2006.197.08:13:30.92#ibcon#*before write, iclass 3, count 2 2006.197.08:13:30.92#ibcon#enter sib2, iclass 3, count 2 2006.197.08:13:30.92#ibcon#flushed, iclass 3, count 2 2006.197.08:13:30.92#ibcon#about to write, iclass 3, count 2 2006.197.08:13:30.92#ibcon#wrote, iclass 3, count 2 2006.197.08:13:30.92#ibcon#about to read 3, iclass 3, count 2 2006.197.08:13:30.95#ibcon#read 3, iclass 3, count 2 2006.197.08:13:30.95#ibcon#about to read 4, iclass 3, count 2 2006.197.08:13:30.95#ibcon#read 4, iclass 3, count 2 2006.197.08:13:30.95#ibcon#about to read 5, iclass 3, count 2 2006.197.08:13:30.95#ibcon#read 5, iclass 3, count 2 2006.197.08:13:30.95#ibcon#about to read 6, iclass 3, count 2 2006.197.08:13:30.95#ibcon#read 6, iclass 3, count 2 2006.197.08:13:30.95#ibcon#end of sib2, iclass 3, count 2 2006.197.08:13:30.95#ibcon#*after write, iclass 3, count 2 2006.197.08:13:30.95#ibcon#*before return 0, iclass 3, count 2 2006.197.08:13:30.95#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.197.08:13:30.95#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.197.08:13:30.95#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.197.08:13:30.95#ibcon#ireg 7 cls_cnt 0 2006.197.08:13:30.95#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.197.08:13:31.07#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.197.08:13:31.07#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.197.08:13:31.07#ibcon#enter wrdev, iclass 3, count 0 2006.197.08:13:31.07#ibcon#first serial, iclass 3, count 0 2006.197.08:13:31.07#ibcon#enter sib2, iclass 3, count 0 2006.197.08:13:31.07#ibcon#flushed, iclass 3, count 0 2006.197.08:13:31.07#ibcon#about to write, iclass 3, count 0 2006.197.08:13:31.07#ibcon#wrote, iclass 3, count 0 2006.197.08:13:31.07#ibcon#about to read 3, iclass 3, count 0 2006.197.08:13:31.09#ibcon#read 3, iclass 3, count 0 2006.197.08:13:31.09#ibcon#about to read 4, iclass 3, count 0 2006.197.08:13:31.09#ibcon#read 4, iclass 3, count 0 2006.197.08:13:31.09#ibcon#about to read 5, iclass 3, count 0 2006.197.08:13:31.09#ibcon#read 5, iclass 3, count 0 2006.197.08:13:31.09#ibcon#about to read 6, iclass 3, count 0 2006.197.08:13:31.09#ibcon#read 6, iclass 3, count 0 2006.197.08:13:31.09#ibcon#end of sib2, iclass 3, count 0 2006.197.08:13:31.09#ibcon#*mode == 0, iclass 3, count 0 2006.197.08:13:31.09#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.197.08:13:31.09#ibcon#[27=USB\r\n] 2006.197.08:13:31.09#ibcon#*before write, iclass 3, count 0 2006.197.08:13:31.09#ibcon#enter sib2, iclass 3, count 0 2006.197.08:13:31.09#ibcon#flushed, iclass 3, count 0 2006.197.08:13:31.09#ibcon#about to write, iclass 3, count 0 2006.197.08:13:31.09#ibcon#wrote, iclass 3, count 0 2006.197.08:13:31.09#ibcon#about to read 3, iclass 3, count 0 2006.197.08:13:31.12#ibcon#read 3, iclass 3, count 0 2006.197.08:13:31.12#ibcon#about to read 4, iclass 3, count 0 2006.197.08:13:31.12#ibcon#read 4, iclass 3, count 0 2006.197.08:13:31.12#ibcon#about to read 5, iclass 3, count 0 2006.197.08:13:31.12#ibcon#read 5, iclass 3, count 0 2006.197.08:13:31.12#ibcon#about to read 6, iclass 3, count 0 2006.197.08:13:31.12#ibcon#read 6, iclass 3, count 0 2006.197.08:13:31.12#ibcon#end of sib2, iclass 3, count 0 2006.197.08:13:31.12#ibcon#*after write, iclass 3, count 0 2006.197.08:13:31.12#ibcon#*before return 0, iclass 3, count 0 2006.197.08:13:31.12#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.197.08:13:31.12#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.197.08:13:31.12#ibcon#about to clear, iclass 3 cls_cnt 0 2006.197.08:13:31.12#ibcon#cleared, iclass 3 cls_cnt 0 2006.197.08:13:31.12$vc4f8/vblo=4,712.99 2006.197.08:13:31.12#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.197.08:13:31.12#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.197.08:13:31.12#ibcon#ireg 17 cls_cnt 0 2006.197.08:13:31.12#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.197.08:13:31.12#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.197.08:13:31.12#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.197.08:13:31.12#ibcon#enter wrdev, iclass 5, count 0 2006.197.08:13:31.12#ibcon#first serial, iclass 5, count 0 2006.197.08:13:31.12#ibcon#enter sib2, iclass 5, count 0 2006.197.08:13:31.12#ibcon#flushed, iclass 5, count 0 2006.197.08:13:31.12#ibcon#about to write, iclass 5, count 0 2006.197.08:13:31.12#ibcon#wrote, iclass 5, count 0 2006.197.08:13:31.12#ibcon#about to read 3, iclass 5, count 0 2006.197.08:13:31.14#ibcon#read 3, iclass 5, count 0 2006.197.08:13:31.14#ibcon#about to read 4, iclass 5, count 0 2006.197.08:13:31.14#ibcon#read 4, iclass 5, count 0 2006.197.08:13:31.14#ibcon#about to read 5, iclass 5, count 0 2006.197.08:13:31.14#ibcon#read 5, iclass 5, count 0 2006.197.08:13:31.14#ibcon#about to read 6, iclass 5, count 0 2006.197.08:13:31.14#ibcon#read 6, iclass 5, count 0 2006.197.08:13:31.14#ibcon#end of sib2, iclass 5, count 0 2006.197.08:13:31.14#ibcon#*mode == 0, iclass 5, count 0 2006.197.08:13:31.14#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.197.08:13:31.14#ibcon#[28=FRQ=04,712.99\r\n] 2006.197.08:13:31.14#ibcon#*before write, iclass 5, count 0 2006.197.08:13:31.14#ibcon#enter sib2, iclass 5, count 0 2006.197.08:13:31.14#ibcon#flushed, iclass 5, count 0 2006.197.08:13:31.14#ibcon#about to write, iclass 5, count 0 2006.197.08:13:31.14#ibcon#wrote, iclass 5, count 0 2006.197.08:13:31.14#ibcon#about to read 3, iclass 5, count 0 2006.197.08:13:31.18#ibcon#read 3, iclass 5, count 0 2006.197.08:13:31.18#ibcon#about to read 4, iclass 5, count 0 2006.197.08:13:31.18#ibcon#read 4, iclass 5, count 0 2006.197.08:13:31.18#ibcon#about to read 5, iclass 5, count 0 2006.197.08:13:31.18#ibcon#read 5, iclass 5, count 0 2006.197.08:13:31.18#ibcon#about to read 6, iclass 5, count 0 2006.197.08:13:31.18#ibcon#read 6, iclass 5, count 0 2006.197.08:13:31.18#ibcon#end of sib2, iclass 5, count 0 2006.197.08:13:31.18#ibcon#*after write, iclass 5, count 0 2006.197.08:13:31.18#ibcon#*before return 0, iclass 5, count 0 2006.197.08:13:31.18#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.197.08:13:31.18#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.197.08:13:31.18#ibcon#about to clear, iclass 5 cls_cnt 0 2006.197.08:13:31.18#ibcon#cleared, iclass 5 cls_cnt 0 2006.197.08:13:31.18$vc4f8/vb=4,4 2006.197.08:13:31.18#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.197.08:13:31.18#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.197.08:13:31.18#ibcon#ireg 11 cls_cnt 2 2006.197.08:13:31.18#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.197.08:13:31.24#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.197.08:13:31.24#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.197.08:13:31.24#ibcon#enter wrdev, iclass 7, count 2 2006.197.08:13:31.24#ibcon#first serial, iclass 7, count 2 2006.197.08:13:31.24#ibcon#enter sib2, iclass 7, count 2 2006.197.08:13:31.24#ibcon#flushed, iclass 7, count 2 2006.197.08:13:31.24#ibcon#about to write, iclass 7, count 2 2006.197.08:13:31.24#ibcon#wrote, iclass 7, count 2 2006.197.08:13:31.24#ibcon#about to read 3, iclass 7, count 2 2006.197.08:13:31.26#ibcon#read 3, iclass 7, count 2 2006.197.08:13:31.26#ibcon#about to read 4, iclass 7, count 2 2006.197.08:13:31.26#ibcon#read 4, iclass 7, count 2 2006.197.08:13:31.26#ibcon#about to read 5, iclass 7, count 2 2006.197.08:13:31.26#ibcon#read 5, iclass 7, count 2 2006.197.08:13:31.26#ibcon#about to read 6, iclass 7, count 2 2006.197.08:13:31.26#ibcon#read 6, iclass 7, count 2 2006.197.08:13:31.26#ibcon#end of sib2, iclass 7, count 2 2006.197.08:13:31.26#ibcon#*mode == 0, iclass 7, count 2 2006.197.08:13:31.26#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.197.08:13:31.26#ibcon#[27=AT04-04\r\n] 2006.197.08:13:31.26#ibcon#*before write, iclass 7, count 2 2006.197.08:13:31.26#ibcon#enter sib2, iclass 7, count 2 2006.197.08:13:31.26#ibcon#flushed, iclass 7, count 2 2006.197.08:13:31.26#ibcon#about to write, iclass 7, count 2 2006.197.08:13:31.26#ibcon#wrote, iclass 7, count 2 2006.197.08:13:31.26#ibcon#about to read 3, iclass 7, count 2 2006.197.08:13:31.29#ibcon#read 3, iclass 7, count 2 2006.197.08:13:31.29#ibcon#about to read 4, iclass 7, count 2 2006.197.08:13:31.29#ibcon#read 4, iclass 7, count 2 2006.197.08:13:31.29#ibcon#about to read 5, iclass 7, count 2 2006.197.08:13:31.29#ibcon#read 5, iclass 7, count 2 2006.197.08:13:31.29#ibcon#about to read 6, iclass 7, count 2 2006.197.08:13:31.29#ibcon#read 6, iclass 7, count 2 2006.197.08:13:31.29#ibcon#end of sib2, iclass 7, count 2 2006.197.08:13:31.29#ibcon#*after write, iclass 7, count 2 2006.197.08:13:31.29#ibcon#*before return 0, iclass 7, count 2 2006.197.08:13:31.29#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.197.08:13:31.29#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.197.08:13:31.29#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.197.08:13:31.29#ibcon#ireg 7 cls_cnt 0 2006.197.08:13:31.29#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.197.08:13:31.41#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.197.08:13:31.41#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.197.08:13:31.41#ibcon#enter wrdev, iclass 7, count 0 2006.197.08:13:31.41#ibcon#first serial, iclass 7, count 0 2006.197.08:13:31.41#ibcon#enter sib2, iclass 7, count 0 2006.197.08:13:31.41#ibcon#flushed, iclass 7, count 0 2006.197.08:13:31.41#ibcon#about to write, iclass 7, count 0 2006.197.08:13:31.41#ibcon#wrote, iclass 7, count 0 2006.197.08:13:31.41#ibcon#about to read 3, iclass 7, count 0 2006.197.08:13:31.43#ibcon#read 3, iclass 7, count 0 2006.197.08:13:31.43#ibcon#about to read 4, iclass 7, count 0 2006.197.08:13:31.43#ibcon#read 4, iclass 7, count 0 2006.197.08:13:31.43#ibcon#about to read 5, iclass 7, count 0 2006.197.08:13:31.43#ibcon#read 5, iclass 7, count 0 2006.197.08:13:31.43#ibcon#about to read 6, iclass 7, count 0 2006.197.08:13:31.43#ibcon#read 6, iclass 7, count 0 2006.197.08:13:31.43#ibcon#end of sib2, iclass 7, count 0 2006.197.08:13:31.43#ibcon#*mode == 0, iclass 7, count 0 2006.197.08:13:31.43#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.197.08:13:31.43#ibcon#[27=USB\r\n] 2006.197.08:13:31.43#ibcon#*before write, iclass 7, count 0 2006.197.08:13:31.43#ibcon#enter sib2, iclass 7, count 0 2006.197.08:13:31.43#ibcon#flushed, iclass 7, count 0 2006.197.08:13:31.43#ibcon#about to write, iclass 7, count 0 2006.197.08:13:31.43#ibcon#wrote, iclass 7, count 0 2006.197.08:13:31.43#ibcon#about to read 3, iclass 7, count 0 2006.197.08:13:31.46#ibcon#read 3, iclass 7, count 0 2006.197.08:13:31.46#ibcon#about to read 4, iclass 7, count 0 2006.197.08:13:31.46#ibcon#read 4, iclass 7, count 0 2006.197.08:13:31.46#ibcon#about to read 5, iclass 7, count 0 2006.197.08:13:31.46#ibcon#read 5, iclass 7, count 0 2006.197.08:13:31.46#ibcon#about to read 6, iclass 7, count 0 2006.197.08:13:31.46#ibcon#read 6, iclass 7, count 0 2006.197.08:13:31.46#ibcon#end of sib2, iclass 7, count 0 2006.197.08:13:31.46#ibcon#*after write, iclass 7, count 0 2006.197.08:13:31.46#ibcon#*before return 0, iclass 7, count 0 2006.197.08:13:31.46#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.197.08:13:31.46#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.197.08:13:31.46#ibcon#about to clear, iclass 7 cls_cnt 0 2006.197.08:13:31.46#ibcon#cleared, iclass 7 cls_cnt 0 2006.197.08:13:31.46$vc4f8/vblo=5,744.99 2006.197.08:13:31.46#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.197.08:13:31.46#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.197.08:13:31.46#ibcon#ireg 17 cls_cnt 0 2006.197.08:13:31.46#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.197.08:13:31.46#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.197.08:13:31.46#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.197.08:13:31.46#ibcon#enter wrdev, iclass 11, count 0 2006.197.08:13:31.46#ibcon#first serial, iclass 11, count 0 2006.197.08:13:31.46#ibcon#enter sib2, iclass 11, count 0 2006.197.08:13:31.46#ibcon#flushed, iclass 11, count 0 2006.197.08:13:31.46#ibcon#about to write, iclass 11, count 0 2006.197.08:13:31.46#ibcon#wrote, iclass 11, count 0 2006.197.08:13:31.46#ibcon#about to read 3, iclass 11, count 0 2006.197.08:13:31.48#ibcon#read 3, iclass 11, count 0 2006.197.08:13:31.48#ibcon#about to read 4, iclass 11, count 0 2006.197.08:13:31.48#ibcon#read 4, iclass 11, count 0 2006.197.08:13:31.48#ibcon#about to read 5, iclass 11, count 0 2006.197.08:13:31.48#ibcon#read 5, iclass 11, count 0 2006.197.08:13:31.48#ibcon#about to read 6, iclass 11, count 0 2006.197.08:13:31.48#ibcon#read 6, iclass 11, count 0 2006.197.08:13:31.48#ibcon#end of sib2, iclass 11, count 0 2006.197.08:13:31.48#ibcon#*mode == 0, iclass 11, count 0 2006.197.08:13:31.48#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.197.08:13:31.48#ibcon#[28=FRQ=05,744.99\r\n] 2006.197.08:13:31.48#ibcon#*before write, iclass 11, count 0 2006.197.08:13:31.48#ibcon#enter sib2, iclass 11, count 0 2006.197.08:13:31.48#ibcon#flushed, iclass 11, count 0 2006.197.08:13:31.48#ibcon#about to write, iclass 11, count 0 2006.197.08:13:31.48#ibcon#wrote, iclass 11, count 0 2006.197.08:13:31.48#ibcon#about to read 3, iclass 11, count 0 2006.197.08:13:31.52#ibcon#read 3, iclass 11, count 0 2006.197.08:13:31.52#ibcon#about to read 4, iclass 11, count 0 2006.197.08:13:31.52#ibcon#read 4, iclass 11, count 0 2006.197.08:13:31.52#ibcon#about to read 5, iclass 11, count 0 2006.197.08:13:31.52#ibcon#read 5, iclass 11, count 0 2006.197.08:13:31.52#ibcon#about to read 6, iclass 11, count 0 2006.197.08:13:31.52#ibcon#read 6, iclass 11, count 0 2006.197.08:13:31.52#ibcon#end of sib2, iclass 11, count 0 2006.197.08:13:31.52#ibcon#*after write, iclass 11, count 0 2006.197.08:13:31.52#ibcon#*before return 0, iclass 11, count 0 2006.197.08:13:31.52#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.197.08:13:31.52#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.197.08:13:31.52#ibcon#about to clear, iclass 11 cls_cnt 0 2006.197.08:13:31.52#ibcon#cleared, iclass 11 cls_cnt 0 2006.197.08:13:31.52$vc4f8/vb=5,4 2006.197.08:13:31.52#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.197.08:13:31.52#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.197.08:13:31.52#ibcon#ireg 11 cls_cnt 2 2006.197.08:13:31.52#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.197.08:13:31.58#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.197.08:13:31.58#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.197.08:13:31.58#ibcon#enter wrdev, iclass 13, count 2 2006.197.08:13:31.58#ibcon#first serial, iclass 13, count 2 2006.197.08:13:31.58#ibcon#enter sib2, iclass 13, count 2 2006.197.08:13:31.58#ibcon#flushed, iclass 13, count 2 2006.197.08:13:31.58#ibcon#about to write, iclass 13, count 2 2006.197.08:13:31.58#ibcon#wrote, iclass 13, count 2 2006.197.08:13:31.58#ibcon#about to read 3, iclass 13, count 2 2006.197.08:13:31.60#ibcon#read 3, iclass 13, count 2 2006.197.08:13:31.60#ibcon#about to read 4, iclass 13, count 2 2006.197.08:13:31.60#ibcon#read 4, iclass 13, count 2 2006.197.08:13:31.60#ibcon#about to read 5, iclass 13, count 2 2006.197.08:13:31.60#ibcon#read 5, iclass 13, count 2 2006.197.08:13:31.60#ibcon#about to read 6, iclass 13, count 2 2006.197.08:13:31.60#ibcon#read 6, iclass 13, count 2 2006.197.08:13:31.60#ibcon#end of sib2, iclass 13, count 2 2006.197.08:13:31.60#ibcon#*mode == 0, iclass 13, count 2 2006.197.08:13:31.60#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.197.08:13:31.60#ibcon#[27=AT05-04\r\n] 2006.197.08:13:31.60#ibcon#*before write, iclass 13, count 2 2006.197.08:13:31.60#ibcon#enter sib2, iclass 13, count 2 2006.197.08:13:31.60#ibcon#flushed, iclass 13, count 2 2006.197.08:13:31.60#ibcon#about to write, iclass 13, count 2 2006.197.08:13:31.60#ibcon#wrote, iclass 13, count 2 2006.197.08:13:31.60#ibcon#about to read 3, iclass 13, count 2 2006.197.08:13:31.63#ibcon#read 3, iclass 13, count 2 2006.197.08:13:31.63#ibcon#about to read 4, iclass 13, count 2 2006.197.08:13:31.63#ibcon#read 4, iclass 13, count 2 2006.197.08:13:31.63#ibcon#about to read 5, iclass 13, count 2 2006.197.08:13:31.63#ibcon#read 5, iclass 13, count 2 2006.197.08:13:31.63#ibcon#about to read 6, iclass 13, count 2 2006.197.08:13:31.63#ibcon#read 6, iclass 13, count 2 2006.197.08:13:31.63#ibcon#end of sib2, iclass 13, count 2 2006.197.08:13:31.63#ibcon#*after write, iclass 13, count 2 2006.197.08:13:31.63#ibcon#*before return 0, iclass 13, count 2 2006.197.08:13:31.63#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.197.08:13:31.63#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.197.08:13:31.63#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.197.08:13:31.63#ibcon#ireg 7 cls_cnt 0 2006.197.08:13:31.63#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.197.08:13:31.75#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.197.08:13:31.75#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.197.08:13:31.75#ibcon#enter wrdev, iclass 13, count 0 2006.197.08:13:31.75#ibcon#first serial, iclass 13, count 0 2006.197.08:13:31.75#ibcon#enter sib2, iclass 13, count 0 2006.197.08:13:31.75#ibcon#flushed, iclass 13, count 0 2006.197.08:13:31.75#ibcon#about to write, iclass 13, count 0 2006.197.08:13:31.75#ibcon#wrote, iclass 13, count 0 2006.197.08:13:31.75#ibcon#about to read 3, iclass 13, count 0 2006.197.08:13:31.77#ibcon#read 3, iclass 13, count 0 2006.197.08:13:31.77#ibcon#about to read 4, iclass 13, count 0 2006.197.08:13:31.77#ibcon#read 4, iclass 13, count 0 2006.197.08:13:31.77#ibcon#about to read 5, iclass 13, count 0 2006.197.08:13:31.77#ibcon#read 5, iclass 13, count 0 2006.197.08:13:31.77#ibcon#about to read 6, iclass 13, count 0 2006.197.08:13:31.77#ibcon#read 6, iclass 13, count 0 2006.197.08:13:31.77#ibcon#end of sib2, iclass 13, count 0 2006.197.08:13:31.77#ibcon#*mode == 0, iclass 13, count 0 2006.197.08:13:31.77#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.197.08:13:31.77#ibcon#[27=USB\r\n] 2006.197.08:13:31.77#ibcon#*before write, iclass 13, count 0 2006.197.08:13:31.77#ibcon#enter sib2, iclass 13, count 0 2006.197.08:13:31.77#ibcon#flushed, iclass 13, count 0 2006.197.08:13:31.77#ibcon#about to write, iclass 13, count 0 2006.197.08:13:31.77#ibcon#wrote, iclass 13, count 0 2006.197.08:13:31.77#ibcon#about to read 3, iclass 13, count 0 2006.197.08:13:31.80#ibcon#read 3, iclass 13, count 0 2006.197.08:13:31.80#ibcon#about to read 4, iclass 13, count 0 2006.197.08:13:31.80#ibcon#read 4, iclass 13, count 0 2006.197.08:13:31.80#ibcon#about to read 5, iclass 13, count 0 2006.197.08:13:31.80#ibcon#read 5, iclass 13, count 0 2006.197.08:13:31.80#ibcon#about to read 6, iclass 13, count 0 2006.197.08:13:31.80#ibcon#read 6, iclass 13, count 0 2006.197.08:13:31.80#ibcon#end of sib2, iclass 13, count 0 2006.197.08:13:31.80#ibcon#*after write, iclass 13, count 0 2006.197.08:13:31.80#ibcon#*before return 0, iclass 13, count 0 2006.197.08:13:31.80#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.197.08:13:31.80#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.197.08:13:31.80#ibcon#about to clear, iclass 13 cls_cnt 0 2006.197.08:13:31.80#ibcon#cleared, iclass 13 cls_cnt 0 2006.197.08:13:31.80$vc4f8/vblo=6,752.99 2006.197.08:13:31.80#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.197.08:13:31.80#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.197.08:13:31.80#ibcon#ireg 17 cls_cnt 0 2006.197.08:13:31.80#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.197.08:13:31.80#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.197.08:13:31.80#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.197.08:13:31.80#ibcon#enter wrdev, iclass 15, count 0 2006.197.08:13:31.80#ibcon#first serial, iclass 15, count 0 2006.197.08:13:31.80#ibcon#enter sib2, iclass 15, count 0 2006.197.08:13:31.80#ibcon#flushed, iclass 15, count 0 2006.197.08:13:31.80#ibcon#about to write, iclass 15, count 0 2006.197.08:13:31.80#ibcon#wrote, iclass 15, count 0 2006.197.08:13:31.80#ibcon#about to read 3, iclass 15, count 0 2006.197.08:13:31.82#ibcon#read 3, iclass 15, count 0 2006.197.08:13:31.82#ibcon#about to read 4, iclass 15, count 0 2006.197.08:13:31.82#ibcon#read 4, iclass 15, count 0 2006.197.08:13:31.82#ibcon#about to read 5, iclass 15, count 0 2006.197.08:13:31.82#ibcon#read 5, iclass 15, count 0 2006.197.08:13:31.82#ibcon#about to read 6, iclass 15, count 0 2006.197.08:13:31.82#ibcon#read 6, iclass 15, count 0 2006.197.08:13:31.82#ibcon#end of sib2, iclass 15, count 0 2006.197.08:13:31.82#ibcon#*mode == 0, iclass 15, count 0 2006.197.08:13:31.82#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.197.08:13:31.82#ibcon#[28=FRQ=06,752.99\r\n] 2006.197.08:13:31.82#ibcon#*before write, iclass 15, count 0 2006.197.08:13:31.82#ibcon#enter sib2, iclass 15, count 0 2006.197.08:13:31.82#ibcon#flushed, iclass 15, count 0 2006.197.08:13:31.82#ibcon#about to write, iclass 15, count 0 2006.197.08:13:31.82#ibcon#wrote, iclass 15, count 0 2006.197.08:13:31.82#ibcon#about to read 3, iclass 15, count 0 2006.197.08:13:31.86#ibcon#read 3, iclass 15, count 0 2006.197.08:13:31.86#ibcon#about to read 4, iclass 15, count 0 2006.197.08:13:31.86#ibcon#read 4, iclass 15, count 0 2006.197.08:13:31.86#ibcon#about to read 5, iclass 15, count 0 2006.197.08:13:31.86#ibcon#read 5, iclass 15, count 0 2006.197.08:13:31.86#ibcon#about to read 6, iclass 15, count 0 2006.197.08:13:31.86#ibcon#read 6, iclass 15, count 0 2006.197.08:13:31.86#ibcon#end of sib2, iclass 15, count 0 2006.197.08:13:31.86#ibcon#*after write, iclass 15, count 0 2006.197.08:13:31.86#ibcon#*before return 0, iclass 15, count 0 2006.197.08:13:31.86#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.197.08:13:31.86#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.197.08:13:31.86#ibcon#about to clear, iclass 15 cls_cnt 0 2006.197.08:13:31.86#ibcon#cleared, iclass 15 cls_cnt 0 2006.197.08:13:31.86$vc4f8/vb=6,4 2006.197.08:13:31.86#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.197.08:13:31.86#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.197.08:13:31.86#ibcon#ireg 11 cls_cnt 2 2006.197.08:13:31.86#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.197.08:13:31.92#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.197.08:13:31.92#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.197.08:13:31.92#ibcon#enter wrdev, iclass 17, count 2 2006.197.08:13:31.92#ibcon#first serial, iclass 17, count 2 2006.197.08:13:31.92#ibcon#enter sib2, iclass 17, count 2 2006.197.08:13:31.92#ibcon#flushed, iclass 17, count 2 2006.197.08:13:31.92#ibcon#about to write, iclass 17, count 2 2006.197.08:13:31.92#ibcon#wrote, iclass 17, count 2 2006.197.08:13:31.92#ibcon#about to read 3, iclass 17, count 2 2006.197.08:13:31.94#ibcon#read 3, iclass 17, count 2 2006.197.08:13:31.94#ibcon#about to read 4, iclass 17, count 2 2006.197.08:13:31.94#ibcon#read 4, iclass 17, count 2 2006.197.08:13:31.94#ibcon#about to read 5, iclass 17, count 2 2006.197.08:13:31.94#ibcon#read 5, iclass 17, count 2 2006.197.08:13:31.94#ibcon#about to read 6, iclass 17, count 2 2006.197.08:13:31.94#ibcon#read 6, iclass 17, count 2 2006.197.08:13:31.94#ibcon#end of sib2, iclass 17, count 2 2006.197.08:13:31.94#ibcon#*mode == 0, iclass 17, count 2 2006.197.08:13:31.94#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.197.08:13:31.94#ibcon#[27=AT06-04\r\n] 2006.197.08:13:31.94#ibcon#*before write, iclass 17, count 2 2006.197.08:13:31.94#ibcon#enter sib2, iclass 17, count 2 2006.197.08:13:31.94#ibcon#flushed, iclass 17, count 2 2006.197.08:13:31.94#ibcon#about to write, iclass 17, count 2 2006.197.08:13:31.94#ibcon#wrote, iclass 17, count 2 2006.197.08:13:31.94#ibcon#about to read 3, iclass 17, count 2 2006.197.08:13:31.97#ibcon#read 3, iclass 17, count 2 2006.197.08:13:31.97#ibcon#about to read 4, iclass 17, count 2 2006.197.08:13:31.97#ibcon#read 4, iclass 17, count 2 2006.197.08:13:31.97#ibcon#about to read 5, iclass 17, count 2 2006.197.08:13:31.97#ibcon#read 5, iclass 17, count 2 2006.197.08:13:31.97#ibcon#about to read 6, iclass 17, count 2 2006.197.08:13:31.97#ibcon#read 6, iclass 17, count 2 2006.197.08:13:31.97#ibcon#end of sib2, iclass 17, count 2 2006.197.08:13:31.97#ibcon#*after write, iclass 17, count 2 2006.197.08:13:31.97#ibcon#*before return 0, iclass 17, count 2 2006.197.08:13:31.97#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.197.08:13:31.97#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.197.08:13:31.97#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.197.08:13:31.97#ibcon#ireg 7 cls_cnt 0 2006.197.08:13:31.97#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.197.08:13:32.09#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.197.08:13:32.09#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.197.08:13:32.09#ibcon#enter wrdev, iclass 17, count 0 2006.197.08:13:32.09#ibcon#first serial, iclass 17, count 0 2006.197.08:13:32.09#ibcon#enter sib2, iclass 17, count 0 2006.197.08:13:32.09#ibcon#flushed, iclass 17, count 0 2006.197.08:13:32.09#ibcon#about to write, iclass 17, count 0 2006.197.08:13:32.09#ibcon#wrote, iclass 17, count 0 2006.197.08:13:32.09#ibcon#about to read 3, iclass 17, count 0 2006.197.08:13:32.11#ibcon#read 3, iclass 17, count 0 2006.197.08:13:32.11#ibcon#about to read 4, iclass 17, count 0 2006.197.08:13:32.11#ibcon#read 4, iclass 17, count 0 2006.197.08:13:32.11#ibcon#about to read 5, iclass 17, count 0 2006.197.08:13:32.11#ibcon#read 5, iclass 17, count 0 2006.197.08:13:32.11#ibcon#about to read 6, iclass 17, count 0 2006.197.08:13:32.11#ibcon#read 6, iclass 17, count 0 2006.197.08:13:32.11#ibcon#end of sib2, iclass 17, count 0 2006.197.08:13:32.11#ibcon#*mode == 0, iclass 17, count 0 2006.197.08:13:32.11#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.197.08:13:32.11#ibcon#[27=USB\r\n] 2006.197.08:13:32.11#ibcon#*before write, iclass 17, count 0 2006.197.08:13:32.11#ibcon#enter sib2, iclass 17, count 0 2006.197.08:13:32.11#ibcon#flushed, iclass 17, count 0 2006.197.08:13:32.11#ibcon#about to write, iclass 17, count 0 2006.197.08:13:32.11#ibcon#wrote, iclass 17, count 0 2006.197.08:13:32.11#ibcon#about to read 3, iclass 17, count 0 2006.197.08:13:32.14#ibcon#read 3, iclass 17, count 0 2006.197.08:13:32.14#ibcon#about to read 4, iclass 17, count 0 2006.197.08:13:32.14#ibcon#read 4, iclass 17, count 0 2006.197.08:13:32.14#ibcon#about to read 5, iclass 17, count 0 2006.197.08:13:32.14#ibcon#read 5, iclass 17, count 0 2006.197.08:13:32.14#ibcon#about to read 6, iclass 17, count 0 2006.197.08:13:32.14#ibcon#read 6, iclass 17, count 0 2006.197.08:13:32.14#ibcon#end of sib2, iclass 17, count 0 2006.197.08:13:32.14#ibcon#*after write, iclass 17, count 0 2006.197.08:13:32.14#ibcon#*before return 0, iclass 17, count 0 2006.197.08:13:32.14#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.197.08:13:32.14#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.197.08:13:32.14#ibcon#about to clear, iclass 17 cls_cnt 0 2006.197.08:13:32.14#ibcon#cleared, iclass 17 cls_cnt 0 2006.197.08:13:32.14$vc4f8/vabw=wide 2006.197.08:13:32.14#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.197.08:13:32.14#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.197.08:13:32.14#ibcon#ireg 8 cls_cnt 0 2006.197.08:13:32.14#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.197.08:13:32.14#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.197.08:13:32.14#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.197.08:13:32.14#ibcon#enter wrdev, iclass 19, count 0 2006.197.08:13:32.14#ibcon#first serial, iclass 19, count 0 2006.197.08:13:32.14#ibcon#enter sib2, iclass 19, count 0 2006.197.08:13:32.14#ibcon#flushed, iclass 19, count 0 2006.197.08:13:32.14#ibcon#about to write, iclass 19, count 0 2006.197.08:13:32.14#ibcon#wrote, iclass 19, count 0 2006.197.08:13:32.14#ibcon#about to read 3, iclass 19, count 0 2006.197.08:13:32.16#ibcon#read 3, iclass 19, count 0 2006.197.08:13:32.16#ibcon#about to read 4, iclass 19, count 0 2006.197.08:13:32.16#ibcon#read 4, iclass 19, count 0 2006.197.08:13:32.16#ibcon#about to read 5, iclass 19, count 0 2006.197.08:13:32.16#ibcon#read 5, iclass 19, count 0 2006.197.08:13:32.16#ibcon#about to read 6, iclass 19, count 0 2006.197.08:13:32.16#ibcon#read 6, iclass 19, count 0 2006.197.08:13:32.16#ibcon#end of sib2, iclass 19, count 0 2006.197.08:13:32.16#ibcon#*mode == 0, iclass 19, count 0 2006.197.08:13:32.16#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.197.08:13:32.16#ibcon#[25=BW32\r\n] 2006.197.08:13:32.16#ibcon#*before write, iclass 19, count 0 2006.197.08:13:32.16#ibcon#enter sib2, iclass 19, count 0 2006.197.08:13:32.16#ibcon#flushed, iclass 19, count 0 2006.197.08:13:32.16#ibcon#about to write, iclass 19, count 0 2006.197.08:13:32.16#ibcon#wrote, iclass 19, count 0 2006.197.08:13:32.16#ibcon#about to read 3, iclass 19, count 0 2006.197.08:13:32.19#ibcon#read 3, iclass 19, count 0 2006.197.08:13:32.19#ibcon#about to read 4, iclass 19, count 0 2006.197.08:13:32.19#ibcon#read 4, iclass 19, count 0 2006.197.08:13:32.19#ibcon#about to read 5, iclass 19, count 0 2006.197.08:13:32.19#ibcon#read 5, iclass 19, count 0 2006.197.08:13:32.19#ibcon#about to read 6, iclass 19, count 0 2006.197.08:13:32.19#ibcon#read 6, iclass 19, count 0 2006.197.08:13:32.19#ibcon#end of sib2, iclass 19, count 0 2006.197.08:13:32.19#ibcon#*after write, iclass 19, count 0 2006.197.08:13:32.19#ibcon#*before return 0, iclass 19, count 0 2006.197.08:13:32.19#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.197.08:13:32.19#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.197.08:13:32.19#ibcon#about to clear, iclass 19 cls_cnt 0 2006.197.08:13:32.19#ibcon#cleared, iclass 19 cls_cnt 0 2006.197.08:13:32.19$vc4f8/vbbw=wide 2006.197.08:13:32.19#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.197.08:13:32.19#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.197.08:13:32.19#ibcon#ireg 8 cls_cnt 0 2006.197.08:13:32.19#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.197.08:13:32.26#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.197.08:13:32.26#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.197.08:13:32.26#ibcon#enter wrdev, iclass 21, count 0 2006.197.08:13:32.26#ibcon#first serial, iclass 21, count 0 2006.197.08:13:32.26#ibcon#enter sib2, iclass 21, count 0 2006.197.08:13:32.26#ibcon#flushed, iclass 21, count 0 2006.197.08:13:32.26#ibcon#about to write, iclass 21, count 0 2006.197.08:13:32.26#ibcon#wrote, iclass 21, count 0 2006.197.08:13:32.26#ibcon#about to read 3, iclass 21, count 0 2006.197.08:13:32.28#ibcon#read 3, iclass 21, count 0 2006.197.08:13:32.28#ibcon#about to read 4, iclass 21, count 0 2006.197.08:13:32.28#ibcon#read 4, iclass 21, count 0 2006.197.08:13:32.28#ibcon#about to read 5, iclass 21, count 0 2006.197.08:13:32.28#ibcon#read 5, iclass 21, count 0 2006.197.08:13:32.28#ibcon#about to read 6, iclass 21, count 0 2006.197.08:13:32.28#ibcon#read 6, iclass 21, count 0 2006.197.08:13:32.28#ibcon#end of sib2, iclass 21, count 0 2006.197.08:13:32.28#ibcon#*mode == 0, iclass 21, count 0 2006.197.08:13:32.28#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.197.08:13:32.28#ibcon#[27=BW32\r\n] 2006.197.08:13:32.28#ibcon#*before write, iclass 21, count 0 2006.197.08:13:32.28#ibcon#enter sib2, iclass 21, count 0 2006.197.08:13:32.28#ibcon#flushed, iclass 21, count 0 2006.197.08:13:32.28#ibcon#about to write, iclass 21, count 0 2006.197.08:13:32.28#ibcon#wrote, iclass 21, count 0 2006.197.08:13:32.28#ibcon#about to read 3, iclass 21, count 0 2006.197.08:13:32.31#ibcon#read 3, iclass 21, count 0 2006.197.08:13:32.31#ibcon#about to read 4, iclass 21, count 0 2006.197.08:13:32.31#ibcon#read 4, iclass 21, count 0 2006.197.08:13:32.31#ibcon#about to read 5, iclass 21, count 0 2006.197.08:13:32.31#ibcon#read 5, iclass 21, count 0 2006.197.08:13:32.31#ibcon#about to read 6, iclass 21, count 0 2006.197.08:13:32.31#ibcon#read 6, iclass 21, count 0 2006.197.08:13:32.31#ibcon#end of sib2, iclass 21, count 0 2006.197.08:13:32.31#ibcon#*after write, iclass 21, count 0 2006.197.08:13:32.31#ibcon#*before return 0, iclass 21, count 0 2006.197.08:13:32.31#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.197.08:13:32.31#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.197.08:13:32.31#ibcon#about to clear, iclass 21 cls_cnt 0 2006.197.08:13:32.31#ibcon#cleared, iclass 21 cls_cnt 0 2006.197.08:13:32.31$4f8m12a/ifd4f 2006.197.08:13:32.31$ifd4f/lo= 2006.197.08:13:32.31$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.197.08:13:32.31$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.197.08:13:32.31$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.197.08:13:32.31$ifd4f/patch= 2006.197.08:13:32.31$ifd4f/patch=lo1,a1,a2,a3,a4 2006.197.08:13:32.31$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.197.08:13:32.31$ifd4f/patch=lo3,a5,a6,a7,a8 2006.197.08:13:32.31$4f8m12a/"form=m,16.000,1:2 2006.197.08:13:32.31$4f8m12a/"tpicd 2006.197.08:13:32.31$4f8m12a/echo=off 2006.197.08:13:32.31$4f8m12a/xlog=off 2006.197.08:13:32.31:!2006.197.08:14:00 2006.197.08:13:40.14#trakl#Source acquired 2006.197.08:13:42.14#flagr#flagr/antenna,acquired 2006.197.08:14:00.00:preob 2006.197.08:14:01.14/onsource/TRACKING 2006.197.08:14:01.14:!2006.197.08:14:10 2006.197.08:14:10.00:data_valid=on 2006.197.08:14:10.00:midob 2006.197.08:14:10.14/onsource/TRACKING 2006.197.08:14:10.14/wx/25.60,1002.8,96 2006.197.08:14:10.30/cable/+6.3743E-03 2006.197.08:14:11.39/va/01,08,usb,yes,28,30 2006.197.08:14:11.39/va/02,07,usb,yes,29,30 2006.197.08:14:11.39/va/03,06,usb,yes,30,30 2006.197.08:14:11.39/va/04,07,usb,yes,29,32 2006.197.08:14:11.39/va/05,07,usb,yes,33,35 2006.197.08:14:11.39/va/06,06,usb,yes,32,32 2006.197.08:14:11.39/va/07,06,usb,yes,33,33 2006.197.08:14:11.39/va/08,07,usb,yes,31,30 2006.197.08:14:11.62/valo/01,532.99,yes,locked 2006.197.08:14:11.62/valo/02,572.99,yes,locked 2006.197.08:14:11.62/valo/03,672.99,yes,locked 2006.197.08:14:11.62/valo/04,832.99,yes,locked 2006.197.08:14:11.62/valo/05,652.99,yes,locked 2006.197.08:14:11.62/valo/06,772.99,yes,locked 2006.197.08:14:11.62/valo/07,832.99,yes,locked 2006.197.08:14:11.62/valo/08,852.99,yes,locked 2006.197.08:14:12.71/vb/01,04,usb,yes,28,27 2006.197.08:14:12.71/vb/02,04,usb,yes,30,32 2006.197.08:14:12.71/vb/03,04,usb,yes,27,30 2006.197.08:14:12.71/vb/04,04,usb,yes,27,28 2006.197.08:14:12.71/vb/05,04,usb,yes,26,30 2006.197.08:14:12.71/vb/06,04,usb,yes,27,30 2006.197.08:14:12.71/vb/07,04,usb,yes,29,29 2006.197.08:14:12.71/vb/08,04,usb,yes,27,30 2006.197.08:14:12.94/vblo/01,632.99,yes,locked 2006.197.08:14:12.94/vblo/02,640.99,yes,locked 2006.197.08:14:12.94/vblo/03,656.99,yes,locked 2006.197.08:14:12.94/vblo/04,712.99,yes,locked 2006.197.08:14:12.94/vblo/05,744.99,yes,locked 2006.197.08:14:12.94/vblo/06,752.99,yes,locked 2006.197.08:14:12.94/vblo/07,734.99,yes,locked 2006.197.08:14:12.94/vblo/08,744.99,yes,locked 2006.197.08:14:13.09/vabw/8 2006.197.08:14:13.24/vbbw/8 2006.197.08:14:13.33/xfe/off,on,15.5 2006.197.08:14:13.71/ifatt/23,28,28,28 2006.197.08:14:14.10/fmout-gps/S +2.99E-07 2006.197.08:14:14.14:!2006.197.08:15:10 2006.197.08:15:10.00:data_valid=off 2006.197.08:15:10.00:postob 2006.197.08:15:10.21/cable/+6.3719E-03 2006.197.08:15:10.21/wx/25.59,1002.8,96 2006.197.08:15:11.10/fmout-gps/S +2.99E-07 2006.197.08:15:11.10:scan_name=197-0816,k06197,60 2006.197.08:15:11.10:source=oj287,085448.87,200630.6,2000.0,ccw 2006.197.08:15:11.14#flagr#flagr/antenna,new-source 2006.197.08:15:12.14:checkk5 2006.197.08:15:12.48/chk_autoobs//k5ts1/ autoobs is running! 2006.197.08:15:12.82/chk_autoobs//k5ts2/ autoobs is running! 2006.197.08:15:13.16/chk_autoobs//k5ts3/ autoobs is running! 2006.197.08:15:13.50/chk_autoobs//k5ts4/ autoobs is running! 2006.197.08:15:13.84/chk_obsdata//k5ts1/T1970814??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.08:15:14.18/chk_obsdata//k5ts2/T1970814??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.08:15:14.52/chk_obsdata//k5ts3/T1970814??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.08:15:14.85/chk_obsdata//k5ts4/T1970814??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.08:15:15.51/k5log//k5ts1_log_newline 2006.197.08:15:16.16/k5log//k5ts2_log_newline 2006.197.08:15:16.81/k5log//k5ts3_log_newline 2006.197.08:15:17.47/k5log//k5ts4_log_newline 2006.197.08:15:17.50/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.197.08:15:17.50:4f8m12a=2 2006.197.08:15:17.50$4f8m12a/echo=on 2006.197.08:15:17.50$4f8m12a/pcalon 2006.197.08:15:17.50$pcalon/"no phase cal control is implemented here 2006.197.08:15:17.50$4f8m12a/"tpicd=stop 2006.197.08:15:17.50$4f8m12a/vc4f8 2006.197.08:15:17.50$vc4f8/valo=1,532.99 2006.197.08:15:17.50#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.197.08:15:17.50#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.197.08:15:17.50#ibcon#ireg 17 cls_cnt 0 2006.197.08:15:17.50#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.197.08:15:17.50#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.197.08:15:17.50#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.197.08:15:17.50#ibcon#enter wrdev, iclass 32, count 0 2006.197.08:15:17.50#ibcon#first serial, iclass 32, count 0 2006.197.08:15:17.50#ibcon#enter sib2, iclass 32, count 0 2006.197.08:15:17.50#ibcon#flushed, iclass 32, count 0 2006.197.08:15:17.50#ibcon#about to write, iclass 32, count 0 2006.197.08:15:17.50#ibcon#wrote, iclass 32, count 0 2006.197.08:15:17.50#ibcon#about to read 3, iclass 32, count 0 2006.197.08:15:17.52#ibcon#read 3, iclass 32, count 0 2006.197.08:15:17.52#ibcon#about to read 4, iclass 32, count 0 2006.197.08:15:17.52#ibcon#read 4, iclass 32, count 0 2006.197.08:15:17.52#ibcon#about to read 5, iclass 32, count 0 2006.197.08:15:17.52#ibcon#read 5, iclass 32, count 0 2006.197.08:15:17.52#ibcon#about to read 6, iclass 32, count 0 2006.197.08:15:17.52#ibcon#read 6, iclass 32, count 0 2006.197.08:15:17.52#ibcon#end of sib2, iclass 32, count 0 2006.197.08:15:17.52#ibcon#*mode == 0, iclass 32, count 0 2006.197.08:15:17.52#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.197.08:15:17.52#ibcon#[26=FRQ=01,532.99\r\n] 2006.197.08:15:17.52#ibcon#*before write, iclass 32, count 0 2006.197.08:15:17.52#ibcon#enter sib2, iclass 32, count 0 2006.197.08:15:17.52#ibcon#flushed, iclass 32, count 0 2006.197.08:15:17.52#ibcon#about to write, iclass 32, count 0 2006.197.08:15:17.52#ibcon#wrote, iclass 32, count 0 2006.197.08:15:17.52#ibcon#about to read 3, iclass 32, count 0 2006.197.08:15:17.57#ibcon#read 3, iclass 32, count 0 2006.197.08:15:17.57#ibcon#about to read 4, iclass 32, count 0 2006.197.08:15:17.57#ibcon#read 4, iclass 32, count 0 2006.197.08:15:17.57#ibcon#about to read 5, iclass 32, count 0 2006.197.08:15:17.57#ibcon#read 5, iclass 32, count 0 2006.197.08:15:17.57#ibcon#about to read 6, iclass 32, count 0 2006.197.08:15:17.57#ibcon#read 6, iclass 32, count 0 2006.197.08:15:17.57#ibcon#end of sib2, iclass 32, count 0 2006.197.08:15:17.57#ibcon#*after write, iclass 32, count 0 2006.197.08:15:17.57#ibcon#*before return 0, iclass 32, count 0 2006.197.08:15:17.57#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.197.08:15:17.57#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.197.08:15:17.57#ibcon#about to clear, iclass 32 cls_cnt 0 2006.197.08:15:17.57#ibcon#cleared, iclass 32 cls_cnt 0 2006.197.08:15:17.57$vc4f8/va=1,8 2006.197.08:15:17.57#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.197.08:15:17.57#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.197.08:15:17.57#ibcon#ireg 11 cls_cnt 2 2006.197.08:15:17.57#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.197.08:15:17.57#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.197.08:15:17.57#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.197.08:15:17.57#ibcon#enter wrdev, iclass 34, count 2 2006.197.08:15:17.57#ibcon#first serial, iclass 34, count 2 2006.197.08:15:17.57#ibcon#enter sib2, iclass 34, count 2 2006.197.08:15:17.57#ibcon#flushed, iclass 34, count 2 2006.197.08:15:17.57#ibcon#about to write, iclass 34, count 2 2006.197.08:15:17.57#ibcon#wrote, iclass 34, count 2 2006.197.08:15:17.57#ibcon#about to read 3, iclass 34, count 2 2006.197.08:15:17.59#ibcon#read 3, iclass 34, count 2 2006.197.08:15:17.59#ibcon#about to read 4, iclass 34, count 2 2006.197.08:15:17.59#ibcon#read 4, iclass 34, count 2 2006.197.08:15:17.59#ibcon#about to read 5, iclass 34, count 2 2006.197.08:15:17.59#ibcon#read 5, iclass 34, count 2 2006.197.08:15:17.59#ibcon#about to read 6, iclass 34, count 2 2006.197.08:15:17.59#ibcon#read 6, iclass 34, count 2 2006.197.08:15:17.59#ibcon#end of sib2, iclass 34, count 2 2006.197.08:15:17.59#ibcon#*mode == 0, iclass 34, count 2 2006.197.08:15:17.59#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.197.08:15:17.59#ibcon#[25=AT01-08\r\n] 2006.197.08:15:17.59#ibcon#*before write, iclass 34, count 2 2006.197.08:15:17.59#ibcon#enter sib2, iclass 34, count 2 2006.197.08:15:17.59#ibcon#flushed, iclass 34, count 2 2006.197.08:15:17.59#ibcon#about to write, iclass 34, count 2 2006.197.08:15:17.59#ibcon#wrote, iclass 34, count 2 2006.197.08:15:17.59#ibcon#about to read 3, iclass 34, count 2 2006.197.08:15:17.62#ibcon#read 3, iclass 34, count 2 2006.197.08:15:17.62#ibcon#about to read 4, iclass 34, count 2 2006.197.08:15:17.62#ibcon#read 4, iclass 34, count 2 2006.197.08:15:17.62#ibcon#about to read 5, iclass 34, count 2 2006.197.08:15:17.62#ibcon#read 5, iclass 34, count 2 2006.197.08:15:17.62#ibcon#about to read 6, iclass 34, count 2 2006.197.08:15:17.62#ibcon#read 6, iclass 34, count 2 2006.197.08:15:17.62#ibcon#end of sib2, iclass 34, count 2 2006.197.08:15:17.62#ibcon#*after write, iclass 34, count 2 2006.197.08:15:17.62#ibcon#*before return 0, iclass 34, count 2 2006.197.08:15:17.62#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.197.08:15:17.62#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.197.08:15:17.62#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.197.08:15:17.62#ibcon#ireg 7 cls_cnt 0 2006.197.08:15:17.62#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.197.08:15:17.74#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.197.08:15:17.74#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.197.08:15:17.74#ibcon#enter wrdev, iclass 34, count 0 2006.197.08:15:17.74#ibcon#first serial, iclass 34, count 0 2006.197.08:15:17.74#ibcon#enter sib2, iclass 34, count 0 2006.197.08:15:17.74#ibcon#flushed, iclass 34, count 0 2006.197.08:15:17.74#ibcon#about to write, iclass 34, count 0 2006.197.08:15:17.74#ibcon#wrote, iclass 34, count 0 2006.197.08:15:17.74#ibcon#about to read 3, iclass 34, count 0 2006.197.08:15:17.76#ibcon#read 3, iclass 34, count 0 2006.197.08:15:17.76#ibcon#about to read 4, iclass 34, count 0 2006.197.08:15:17.76#ibcon#read 4, iclass 34, count 0 2006.197.08:15:17.76#ibcon#about to read 5, iclass 34, count 0 2006.197.08:15:17.76#ibcon#read 5, iclass 34, count 0 2006.197.08:15:17.76#ibcon#about to read 6, iclass 34, count 0 2006.197.08:15:17.76#ibcon#read 6, iclass 34, count 0 2006.197.08:15:17.76#ibcon#end of sib2, iclass 34, count 0 2006.197.08:15:17.76#ibcon#*mode == 0, iclass 34, count 0 2006.197.08:15:17.76#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.197.08:15:17.76#ibcon#[25=USB\r\n] 2006.197.08:15:17.76#ibcon#*before write, iclass 34, count 0 2006.197.08:15:17.76#ibcon#enter sib2, iclass 34, count 0 2006.197.08:15:17.76#ibcon#flushed, iclass 34, count 0 2006.197.08:15:17.76#ibcon#about to write, iclass 34, count 0 2006.197.08:15:17.76#ibcon#wrote, iclass 34, count 0 2006.197.08:15:17.76#ibcon#about to read 3, iclass 34, count 0 2006.197.08:15:17.79#ibcon#read 3, iclass 34, count 0 2006.197.08:15:17.79#ibcon#about to read 4, iclass 34, count 0 2006.197.08:15:17.79#ibcon#read 4, iclass 34, count 0 2006.197.08:15:17.79#ibcon#about to read 5, iclass 34, count 0 2006.197.08:15:17.79#ibcon#read 5, iclass 34, count 0 2006.197.08:15:17.79#ibcon#about to read 6, iclass 34, count 0 2006.197.08:15:17.79#ibcon#read 6, iclass 34, count 0 2006.197.08:15:17.79#ibcon#end of sib2, iclass 34, count 0 2006.197.08:15:17.79#ibcon#*after write, iclass 34, count 0 2006.197.08:15:17.79#ibcon#*before return 0, iclass 34, count 0 2006.197.08:15:17.79#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.197.08:15:17.79#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.197.08:15:17.79#ibcon#about to clear, iclass 34 cls_cnt 0 2006.197.08:15:17.79#ibcon#cleared, iclass 34 cls_cnt 0 2006.197.08:15:17.79$vc4f8/valo=2,572.99 2006.197.08:15:17.79#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.197.08:15:17.79#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.197.08:15:17.79#ibcon#ireg 17 cls_cnt 0 2006.197.08:15:17.79#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.197.08:15:17.79#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.197.08:15:17.79#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.197.08:15:17.79#ibcon#enter wrdev, iclass 36, count 0 2006.197.08:15:17.79#ibcon#first serial, iclass 36, count 0 2006.197.08:15:17.79#ibcon#enter sib2, iclass 36, count 0 2006.197.08:15:17.79#ibcon#flushed, iclass 36, count 0 2006.197.08:15:17.79#ibcon#about to write, iclass 36, count 0 2006.197.08:15:17.79#ibcon#wrote, iclass 36, count 0 2006.197.08:15:17.79#ibcon#about to read 3, iclass 36, count 0 2006.197.08:15:17.81#ibcon#read 3, iclass 36, count 0 2006.197.08:15:17.81#ibcon#about to read 4, iclass 36, count 0 2006.197.08:15:17.81#ibcon#read 4, iclass 36, count 0 2006.197.08:15:17.81#ibcon#about to read 5, iclass 36, count 0 2006.197.08:15:17.81#ibcon#read 5, iclass 36, count 0 2006.197.08:15:17.81#ibcon#about to read 6, iclass 36, count 0 2006.197.08:15:17.81#ibcon#read 6, iclass 36, count 0 2006.197.08:15:17.81#ibcon#end of sib2, iclass 36, count 0 2006.197.08:15:17.81#ibcon#*mode == 0, iclass 36, count 0 2006.197.08:15:17.81#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.197.08:15:17.81#ibcon#[26=FRQ=02,572.99\r\n] 2006.197.08:15:17.81#ibcon#*before write, iclass 36, count 0 2006.197.08:15:17.81#ibcon#enter sib2, iclass 36, count 0 2006.197.08:15:17.81#ibcon#flushed, iclass 36, count 0 2006.197.08:15:17.81#ibcon#about to write, iclass 36, count 0 2006.197.08:15:17.81#ibcon#wrote, iclass 36, count 0 2006.197.08:15:17.81#ibcon#about to read 3, iclass 36, count 0 2006.197.08:15:17.85#ibcon#read 3, iclass 36, count 0 2006.197.08:15:17.85#ibcon#about to read 4, iclass 36, count 0 2006.197.08:15:17.85#ibcon#read 4, iclass 36, count 0 2006.197.08:15:17.85#ibcon#about to read 5, iclass 36, count 0 2006.197.08:15:17.85#ibcon#read 5, iclass 36, count 0 2006.197.08:15:17.85#ibcon#about to read 6, iclass 36, count 0 2006.197.08:15:17.85#ibcon#read 6, iclass 36, count 0 2006.197.08:15:17.85#ibcon#end of sib2, iclass 36, count 0 2006.197.08:15:17.85#ibcon#*after write, iclass 36, count 0 2006.197.08:15:17.85#ibcon#*before return 0, iclass 36, count 0 2006.197.08:15:17.85#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.197.08:15:17.85#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.197.08:15:17.85#ibcon#about to clear, iclass 36 cls_cnt 0 2006.197.08:15:17.85#ibcon#cleared, iclass 36 cls_cnt 0 2006.197.08:15:17.85$vc4f8/va=2,7 2006.197.08:15:17.85#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.197.08:15:17.85#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.197.08:15:17.85#ibcon#ireg 11 cls_cnt 2 2006.197.08:15:17.85#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.197.08:15:17.91#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.197.08:15:17.91#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.197.08:15:17.91#ibcon#enter wrdev, iclass 38, count 2 2006.197.08:15:17.91#ibcon#first serial, iclass 38, count 2 2006.197.08:15:17.91#ibcon#enter sib2, iclass 38, count 2 2006.197.08:15:17.91#ibcon#flushed, iclass 38, count 2 2006.197.08:15:17.91#ibcon#about to write, iclass 38, count 2 2006.197.08:15:17.91#ibcon#wrote, iclass 38, count 2 2006.197.08:15:17.91#ibcon#about to read 3, iclass 38, count 2 2006.197.08:15:17.93#ibcon#read 3, iclass 38, count 2 2006.197.08:15:17.93#ibcon#about to read 4, iclass 38, count 2 2006.197.08:15:17.93#ibcon#read 4, iclass 38, count 2 2006.197.08:15:17.93#ibcon#about to read 5, iclass 38, count 2 2006.197.08:15:17.93#ibcon#read 5, iclass 38, count 2 2006.197.08:15:17.93#ibcon#about to read 6, iclass 38, count 2 2006.197.08:15:17.93#ibcon#read 6, iclass 38, count 2 2006.197.08:15:17.93#ibcon#end of sib2, iclass 38, count 2 2006.197.08:15:17.93#ibcon#*mode == 0, iclass 38, count 2 2006.197.08:15:17.93#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.197.08:15:17.93#ibcon#[25=AT02-07\r\n] 2006.197.08:15:17.93#ibcon#*before write, iclass 38, count 2 2006.197.08:15:17.93#ibcon#enter sib2, iclass 38, count 2 2006.197.08:15:17.93#ibcon#flushed, iclass 38, count 2 2006.197.08:15:17.93#ibcon#about to write, iclass 38, count 2 2006.197.08:15:17.93#ibcon#wrote, iclass 38, count 2 2006.197.08:15:17.93#ibcon#about to read 3, iclass 38, count 2 2006.197.08:15:17.96#ibcon#read 3, iclass 38, count 2 2006.197.08:15:17.96#ibcon#about to read 4, iclass 38, count 2 2006.197.08:15:17.96#ibcon#read 4, iclass 38, count 2 2006.197.08:15:17.96#ibcon#about to read 5, iclass 38, count 2 2006.197.08:15:17.96#ibcon#read 5, iclass 38, count 2 2006.197.08:15:17.96#ibcon#about to read 6, iclass 38, count 2 2006.197.08:15:17.96#ibcon#read 6, iclass 38, count 2 2006.197.08:15:17.96#ibcon#end of sib2, iclass 38, count 2 2006.197.08:15:17.96#ibcon#*after write, iclass 38, count 2 2006.197.08:15:17.96#ibcon#*before return 0, iclass 38, count 2 2006.197.08:15:17.96#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.197.08:15:17.96#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.197.08:15:17.96#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.197.08:15:17.96#ibcon#ireg 7 cls_cnt 0 2006.197.08:15:17.96#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.197.08:15:18.08#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.197.08:15:18.08#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.197.08:15:18.08#ibcon#enter wrdev, iclass 38, count 0 2006.197.08:15:18.08#ibcon#first serial, iclass 38, count 0 2006.197.08:15:18.08#ibcon#enter sib2, iclass 38, count 0 2006.197.08:15:18.08#ibcon#flushed, iclass 38, count 0 2006.197.08:15:18.08#ibcon#about to write, iclass 38, count 0 2006.197.08:15:18.08#ibcon#wrote, iclass 38, count 0 2006.197.08:15:18.08#ibcon#about to read 3, iclass 38, count 0 2006.197.08:15:18.10#ibcon#read 3, iclass 38, count 0 2006.197.08:15:18.10#ibcon#about to read 4, iclass 38, count 0 2006.197.08:15:18.10#ibcon#read 4, iclass 38, count 0 2006.197.08:15:18.10#ibcon#about to read 5, iclass 38, count 0 2006.197.08:15:18.10#ibcon#read 5, iclass 38, count 0 2006.197.08:15:18.10#ibcon#about to read 6, iclass 38, count 0 2006.197.08:15:18.10#ibcon#read 6, iclass 38, count 0 2006.197.08:15:18.10#ibcon#end of sib2, iclass 38, count 0 2006.197.08:15:18.10#ibcon#*mode == 0, iclass 38, count 0 2006.197.08:15:18.10#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.197.08:15:18.10#ibcon#[25=USB\r\n] 2006.197.08:15:18.10#ibcon#*before write, iclass 38, count 0 2006.197.08:15:18.10#ibcon#enter sib2, iclass 38, count 0 2006.197.08:15:18.10#ibcon#flushed, iclass 38, count 0 2006.197.08:15:18.10#ibcon#about to write, iclass 38, count 0 2006.197.08:15:18.10#ibcon#wrote, iclass 38, count 0 2006.197.08:15:18.10#ibcon#about to read 3, iclass 38, count 0 2006.197.08:15:18.13#ibcon#read 3, iclass 38, count 0 2006.197.08:15:18.13#ibcon#about to read 4, iclass 38, count 0 2006.197.08:15:18.13#ibcon#read 4, iclass 38, count 0 2006.197.08:15:18.13#ibcon#about to read 5, iclass 38, count 0 2006.197.08:15:18.13#ibcon#read 5, iclass 38, count 0 2006.197.08:15:18.13#ibcon#about to read 6, iclass 38, count 0 2006.197.08:15:18.13#ibcon#read 6, iclass 38, count 0 2006.197.08:15:18.13#ibcon#end of sib2, iclass 38, count 0 2006.197.08:15:18.13#ibcon#*after write, iclass 38, count 0 2006.197.08:15:18.13#ibcon#*before return 0, iclass 38, count 0 2006.197.08:15:18.13#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.197.08:15:18.13#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.197.08:15:18.13#ibcon#about to clear, iclass 38 cls_cnt 0 2006.197.08:15:18.13#ibcon#cleared, iclass 38 cls_cnt 0 2006.197.08:15:18.13$vc4f8/valo=3,672.99 2006.197.08:15:18.13#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.197.08:15:18.13#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.197.08:15:18.13#ibcon#ireg 17 cls_cnt 0 2006.197.08:15:18.13#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.197.08:15:18.13#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.197.08:15:18.13#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.197.08:15:18.13#ibcon#enter wrdev, iclass 40, count 0 2006.197.08:15:18.13#ibcon#first serial, iclass 40, count 0 2006.197.08:15:18.13#ibcon#enter sib2, iclass 40, count 0 2006.197.08:15:18.13#ibcon#flushed, iclass 40, count 0 2006.197.08:15:18.13#ibcon#about to write, iclass 40, count 0 2006.197.08:15:18.13#ibcon#wrote, iclass 40, count 0 2006.197.08:15:18.13#ibcon#about to read 3, iclass 40, count 0 2006.197.08:15:18.15#ibcon#read 3, iclass 40, count 0 2006.197.08:15:18.15#ibcon#about to read 4, iclass 40, count 0 2006.197.08:15:18.15#ibcon#read 4, iclass 40, count 0 2006.197.08:15:18.15#ibcon#about to read 5, iclass 40, count 0 2006.197.08:15:18.15#ibcon#read 5, iclass 40, count 0 2006.197.08:15:18.15#ibcon#about to read 6, iclass 40, count 0 2006.197.08:15:18.15#ibcon#read 6, iclass 40, count 0 2006.197.08:15:18.15#ibcon#end of sib2, iclass 40, count 0 2006.197.08:15:18.15#ibcon#*mode == 0, iclass 40, count 0 2006.197.08:15:18.15#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.197.08:15:18.15#ibcon#[26=FRQ=03,672.99\r\n] 2006.197.08:15:18.15#ibcon#*before write, iclass 40, count 0 2006.197.08:15:18.15#ibcon#enter sib2, iclass 40, count 0 2006.197.08:15:18.15#ibcon#flushed, iclass 40, count 0 2006.197.08:15:18.15#ibcon#about to write, iclass 40, count 0 2006.197.08:15:18.15#ibcon#wrote, iclass 40, count 0 2006.197.08:15:18.15#ibcon#about to read 3, iclass 40, count 0 2006.197.08:15:18.19#ibcon#read 3, iclass 40, count 0 2006.197.08:15:18.19#ibcon#about to read 4, iclass 40, count 0 2006.197.08:15:18.19#ibcon#read 4, iclass 40, count 0 2006.197.08:15:18.19#ibcon#about to read 5, iclass 40, count 0 2006.197.08:15:18.19#ibcon#read 5, iclass 40, count 0 2006.197.08:15:18.19#ibcon#about to read 6, iclass 40, count 0 2006.197.08:15:18.19#ibcon#read 6, iclass 40, count 0 2006.197.08:15:18.19#ibcon#end of sib2, iclass 40, count 0 2006.197.08:15:18.19#ibcon#*after write, iclass 40, count 0 2006.197.08:15:18.19#ibcon#*before return 0, iclass 40, count 0 2006.197.08:15:18.19#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.197.08:15:18.19#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.197.08:15:18.19#ibcon#about to clear, iclass 40 cls_cnt 0 2006.197.08:15:18.19#ibcon#cleared, iclass 40 cls_cnt 0 2006.197.08:15:18.19$vc4f8/va=3,6 2006.197.08:15:18.19#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.197.08:15:18.19#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.197.08:15:18.19#ibcon#ireg 11 cls_cnt 2 2006.197.08:15:18.19#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.197.08:15:18.25#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.197.08:15:18.25#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.197.08:15:18.25#ibcon#enter wrdev, iclass 4, count 2 2006.197.08:15:18.25#ibcon#first serial, iclass 4, count 2 2006.197.08:15:18.25#ibcon#enter sib2, iclass 4, count 2 2006.197.08:15:18.25#ibcon#flushed, iclass 4, count 2 2006.197.08:15:18.25#ibcon#about to write, iclass 4, count 2 2006.197.08:15:18.25#ibcon#wrote, iclass 4, count 2 2006.197.08:15:18.25#ibcon#about to read 3, iclass 4, count 2 2006.197.08:15:18.27#ibcon#read 3, iclass 4, count 2 2006.197.08:15:18.27#ibcon#about to read 4, iclass 4, count 2 2006.197.08:15:18.27#ibcon#read 4, iclass 4, count 2 2006.197.08:15:18.27#ibcon#about to read 5, iclass 4, count 2 2006.197.08:15:18.27#ibcon#read 5, iclass 4, count 2 2006.197.08:15:18.27#ibcon#about to read 6, iclass 4, count 2 2006.197.08:15:18.27#ibcon#read 6, iclass 4, count 2 2006.197.08:15:18.27#ibcon#end of sib2, iclass 4, count 2 2006.197.08:15:18.27#ibcon#*mode == 0, iclass 4, count 2 2006.197.08:15:18.27#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.197.08:15:18.27#ibcon#[25=AT03-06\r\n] 2006.197.08:15:18.27#ibcon#*before write, iclass 4, count 2 2006.197.08:15:18.27#ibcon#enter sib2, iclass 4, count 2 2006.197.08:15:18.27#ibcon#flushed, iclass 4, count 2 2006.197.08:15:18.27#ibcon#about to write, iclass 4, count 2 2006.197.08:15:18.27#ibcon#wrote, iclass 4, count 2 2006.197.08:15:18.27#ibcon#about to read 3, iclass 4, count 2 2006.197.08:15:18.30#ibcon#read 3, iclass 4, count 2 2006.197.08:15:18.30#ibcon#about to read 4, iclass 4, count 2 2006.197.08:15:18.30#ibcon#read 4, iclass 4, count 2 2006.197.08:15:18.30#ibcon#about to read 5, iclass 4, count 2 2006.197.08:15:18.30#ibcon#read 5, iclass 4, count 2 2006.197.08:15:18.30#ibcon#about to read 6, iclass 4, count 2 2006.197.08:15:18.30#ibcon#read 6, iclass 4, count 2 2006.197.08:15:18.30#ibcon#end of sib2, iclass 4, count 2 2006.197.08:15:18.30#ibcon#*after write, iclass 4, count 2 2006.197.08:15:18.30#ibcon#*before return 0, iclass 4, count 2 2006.197.08:15:18.30#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.197.08:15:18.30#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.197.08:15:18.30#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.197.08:15:18.30#ibcon#ireg 7 cls_cnt 0 2006.197.08:15:18.30#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.197.08:15:18.42#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.197.08:15:18.42#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.197.08:15:18.42#ibcon#enter wrdev, iclass 4, count 0 2006.197.08:15:18.42#ibcon#first serial, iclass 4, count 0 2006.197.08:15:18.42#ibcon#enter sib2, iclass 4, count 0 2006.197.08:15:18.42#ibcon#flushed, iclass 4, count 0 2006.197.08:15:18.42#ibcon#about to write, iclass 4, count 0 2006.197.08:15:18.42#ibcon#wrote, iclass 4, count 0 2006.197.08:15:18.42#ibcon#about to read 3, iclass 4, count 0 2006.197.08:15:18.44#ibcon#read 3, iclass 4, count 0 2006.197.08:15:18.44#ibcon#about to read 4, iclass 4, count 0 2006.197.08:15:18.44#ibcon#read 4, iclass 4, count 0 2006.197.08:15:18.44#ibcon#about to read 5, iclass 4, count 0 2006.197.08:15:18.44#ibcon#read 5, iclass 4, count 0 2006.197.08:15:18.44#ibcon#about to read 6, iclass 4, count 0 2006.197.08:15:18.44#ibcon#read 6, iclass 4, count 0 2006.197.08:15:18.44#ibcon#end of sib2, iclass 4, count 0 2006.197.08:15:18.44#ibcon#*mode == 0, iclass 4, count 0 2006.197.08:15:18.44#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.197.08:15:18.44#ibcon#[25=USB\r\n] 2006.197.08:15:18.44#ibcon#*before write, iclass 4, count 0 2006.197.08:15:18.44#ibcon#enter sib2, iclass 4, count 0 2006.197.08:15:18.44#ibcon#flushed, iclass 4, count 0 2006.197.08:15:18.44#ibcon#about to write, iclass 4, count 0 2006.197.08:15:18.44#ibcon#wrote, iclass 4, count 0 2006.197.08:15:18.44#ibcon#about to read 3, iclass 4, count 0 2006.197.08:15:18.47#ibcon#read 3, iclass 4, count 0 2006.197.08:15:18.47#ibcon#about to read 4, iclass 4, count 0 2006.197.08:15:18.47#ibcon#read 4, iclass 4, count 0 2006.197.08:15:18.47#ibcon#about to read 5, iclass 4, count 0 2006.197.08:15:18.47#ibcon#read 5, iclass 4, count 0 2006.197.08:15:18.47#ibcon#about to read 6, iclass 4, count 0 2006.197.08:15:18.47#ibcon#read 6, iclass 4, count 0 2006.197.08:15:18.47#ibcon#end of sib2, iclass 4, count 0 2006.197.08:15:18.47#ibcon#*after write, iclass 4, count 0 2006.197.08:15:18.47#ibcon#*before return 0, iclass 4, count 0 2006.197.08:15:18.47#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.197.08:15:18.47#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.197.08:15:18.47#ibcon#about to clear, iclass 4 cls_cnt 0 2006.197.08:15:18.47#ibcon#cleared, iclass 4 cls_cnt 0 2006.197.08:15:18.47$vc4f8/valo=4,832.99 2006.197.08:15:18.47#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.197.08:15:18.47#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.197.08:15:18.47#ibcon#ireg 17 cls_cnt 0 2006.197.08:15:18.47#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.197.08:15:18.47#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.197.08:15:18.47#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.197.08:15:18.47#ibcon#enter wrdev, iclass 6, count 0 2006.197.08:15:18.47#ibcon#first serial, iclass 6, count 0 2006.197.08:15:18.47#ibcon#enter sib2, iclass 6, count 0 2006.197.08:15:18.47#ibcon#flushed, iclass 6, count 0 2006.197.08:15:18.47#ibcon#about to write, iclass 6, count 0 2006.197.08:15:18.47#ibcon#wrote, iclass 6, count 0 2006.197.08:15:18.47#ibcon#about to read 3, iclass 6, count 0 2006.197.08:15:18.49#ibcon#read 3, iclass 6, count 0 2006.197.08:15:18.49#ibcon#about to read 4, iclass 6, count 0 2006.197.08:15:18.49#ibcon#read 4, iclass 6, count 0 2006.197.08:15:18.49#ibcon#about to read 5, iclass 6, count 0 2006.197.08:15:18.49#ibcon#read 5, iclass 6, count 0 2006.197.08:15:18.49#ibcon#about to read 6, iclass 6, count 0 2006.197.08:15:18.49#ibcon#read 6, iclass 6, count 0 2006.197.08:15:18.49#ibcon#end of sib2, iclass 6, count 0 2006.197.08:15:18.49#ibcon#*mode == 0, iclass 6, count 0 2006.197.08:15:18.49#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.197.08:15:18.49#ibcon#[26=FRQ=04,832.99\r\n] 2006.197.08:15:18.49#ibcon#*before write, iclass 6, count 0 2006.197.08:15:18.49#ibcon#enter sib2, iclass 6, count 0 2006.197.08:15:18.49#ibcon#flushed, iclass 6, count 0 2006.197.08:15:18.49#ibcon#about to write, iclass 6, count 0 2006.197.08:15:18.49#ibcon#wrote, iclass 6, count 0 2006.197.08:15:18.49#ibcon#about to read 3, iclass 6, count 0 2006.197.08:15:18.53#ibcon#read 3, iclass 6, count 0 2006.197.08:15:18.53#ibcon#about to read 4, iclass 6, count 0 2006.197.08:15:18.53#ibcon#read 4, iclass 6, count 0 2006.197.08:15:18.53#ibcon#about to read 5, iclass 6, count 0 2006.197.08:15:18.53#ibcon#read 5, iclass 6, count 0 2006.197.08:15:18.53#ibcon#about to read 6, iclass 6, count 0 2006.197.08:15:18.53#ibcon#read 6, iclass 6, count 0 2006.197.08:15:18.53#ibcon#end of sib2, iclass 6, count 0 2006.197.08:15:18.53#ibcon#*after write, iclass 6, count 0 2006.197.08:15:18.53#ibcon#*before return 0, iclass 6, count 0 2006.197.08:15:18.53#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.197.08:15:18.53#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.197.08:15:18.53#ibcon#about to clear, iclass 6 cls_cnt 0 2006.197.08:15:18.53#ibcon#cleared, iclass 6 cls_cnt 0 2006.197.08:15:18.53$vc4f8/va=4,7 2006.197.08:15:18.53#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.197.08:15:18.53#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.197.08:15:18.53#ibcon#ireg 11 cls_cnt 2 2006.197.08:15:18.53#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.197.08:15:18.59#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.197.08:15:18.59#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.197.08:15:18.59#ibcon#enter wrdev, iclass 10, count 2 2006.197.08:15:18.59#ibcon#first serial, iclass 10, count 2 2006.197.08:15:18.59#ibcon#enter sib2, iclass 10, count 2 2006.197.08:15:18.59#ibcon#flushed, iclass 10, count 2 2006.197.08:15:18.59#ibcon#about to write, iclass 10, count 2 2006.197.08:15:18.59#ibcon#wrote, iclass 10, count 2 2006.197.08:15:18.59#ibcon#about to read 3, iclass 10, count 2 2006.197.08:15:18.61#ibcon#read 3, iclass 10, count 2 2006.197.08:15:18.61#ibcon#about to read 4, iclass 10, count 2 2006.197.08:15:18.61#ibcon#read 4, iclass 10, count 2 2006.197.08:15:18.61#ibcon#about to read 5, iclass 10, count 2 2006.197.08:15:18.61#ibcon#read 5, iclass 10, count 2 2006.197.08:15:18.61#ibcon#about to read 6, iclass 10, count 2 2006.197.08:15:18.61#ibcon#read 6, iclass 10, count 2 2006.197.08:15:18.61#ibcon#end of sib2, iclass 10, count 2 2006.197.08:15:18.61#ibcon#*mode == 0, iclass 10, count 2 2006.197.08:15:18.61#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.197.08:15:18.61#ibcon#[25=AT04-07\r\n] 2006.197.08:15:18.61#ibcon#*before write, iclass 10, count 2 2006.197.08:15:18.61#ibcon#enter sib2, iclass 10, count 2 2006.197.08:15:18.61#ibcon#flushed, iclass 10, count 2 2006.197.08:15:18.61#ibcon#about to write, iclass 10, count 2 2006.197.08:15:18.61#ibcon#wrote, iclass 10, count 2 2006.197.08:15:18.61#ibcon#about to read 3, iclass 10, count 2 2006.197.08:15:18.64#ibcon#read 3, iclass 10, count 2 2006.197.08:15:18.64#ibcon#about to read 4, iclass 10, count 2 2006.197.08:15:18.64#ibcon#read 4, iclass 10, count 2 2006.197.08:15:18.64#ibcon#about to read 5, iclass 10, count 2 2006.197.08:15:18.64#ibcon#read 5, iclass 10, count 2 2006.197.08:15:18.64#ibcon#about to read 6, iclass 10, count 2 2006.197.08:15:18.64#ibcon#read 6, iclass 10, count 2 2006.197.08:15:18.64#ibcon#end of sib2, iclass 10, count 2 2006.197.08:15:18.64#ibcon#*after write, iclass 10, count 2 2006.197.08:15:18.64#ibcon#*before return 0, iclass 10, count 2 2006.197.08:15:18.64#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.197.08:15:18.64#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.197.08:15:18.64#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.197.08:15:18.64#ibcon#ireg 7 cls_cnt 0 2006.197.08:15:18.64#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.197.08:15:18.76#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.197.08:15:18.76#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.197.08:15:18.76#ibcon#enter wrdev, iclass 10, count 0 2006.197.08:15:18.76#ibcon#first serial, iclass 10, count 0 2006.197.08:15:18.76#ibcon#enter sib2, iclass 10, count 0 2006.197.08:15:18.76#ibcon#flushed, iclass 10, count 0 2006.197.08:15:18.76#ibcon#about to write, iclass 10, count 0 2006.197.08:15:18.76#ibcon#wrote, iclass 10, count 0 2006.197.08:15:18.76#ibcon#about to read 3, iclass 10, count 0 2006.197.08:15:18.78#ibcon#read 3, iclass 10, count 0 2006.197.08:15:18.78#ibcon#about to read 4, iclass 10, count 0 2006.197.08:15:18.78#ibcon#read 4, iclass 10, count 0 2006.197.08:15:18.78#ibcon#about to read 5, iclass 10, count 0 2006.197.08:15:18.78#ibcon#read 5, iclass 10, count 0 2006.197.08:15:18.78#ibcon#about to read 6, iclass 10, count 0 2006.197.08:15:18.78#ibcon#read 6, iclass 10, count 0 2006.197.08:15:18.78#ibcon#end of sib2, iclass 10, count 0 2006.197.08:15:18.78#ibcon#*mode == 0, iclass 10, count 0 2006.197.08:15:18.78#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.197.08:15:18.78#ibcon#[25=USB\r\n] 2006.197.08:15:18.78#ibcon#*before write, iclass 10, count 0 2006.197.08:15:18.78#ibcon#enter sib2, iclass 10, count 0 2006.197.08:15:18.78#ibcon#flushed, iclass 10, count 0 2006.197.08:15:18.78#ibcon#about to write, iclass 10, count 0 2006.197.08:15:18.78#ibcon#wrote, iclass 10, count 0 2006.197.08:15:18.78#ibcon#about to read 3, iclass 10, count 0 2006.197.08:15:18.81#ibcon#read 3, iclass 10, count 0 2006.197.08:15:18.81#ibcon#about to read 4, iclass 10, count 0 2006.197.08:15:18.81#ibcon#read 4, iclass 10, count 0 2006.197.08:15:18.81#ibcon#about to read 5, iclass 10, count 0 2006.197.08:15:18.81#ibcon#read 5, iclass 10, count 0 2006.197.08:15:18.81#ibcon#about to read 6, iclass 10, count 0 2006.197.08:15:18.81#ibcon#read 6, iclass 10, count 0 2006.197.08:15:18.81#ibcon#end of sib2, iclass 10, count 0 2006.197.08:15:18.81#ibcon#*after write, iclass 10, count 0 2006.197.08:15:18.81#ibcon#*before return 0, iclass 10, count 0 2006.197.08:15:18.81#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.197.08:15:18.81#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.197.08:15:18.81#ibcon#about to clear, iclass 10 cls_cnt 0 2006.197.08:15:18.81#ibcon#cleared, iclass 10 cls_cnt 0 2006.197.08:15:18.81$vc4f8/valo=5,652.99 2006.197.08:15:18.81#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.197.08:15:18.81#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.197.08:15:18.81#ibcon#ireg 17 cls_cnt 0 2006.197.08:15:18.81#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.197.08:15:18.81#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.197.08:15:18.81#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.197.08:15:18.81#ibcon#enter wrdev, iclass 12, count 0 2006.197.08:15:18.81#ibcon#first serial, iclass 12, count 0 2006.197.08:15:18.81#ibcon#enter sib2, iclass 12, count 0 2006.197.08:15:18.81#ibcon#flushed, iclass 12, count 0 2006.197.08:15:18.81#ibcon#about to write, iclass 12, count 0 2006.197.08:15:18.81#ibcon#wrote, iclass 12, count 0 2006.197.08:15:18.81#ibcon#about to read 3, iclass 12, count 0 2006.197.08:15:18.83#ibcon#read 3, iclass 12, count 0 2006.197.08:15:18.83#ibcon#about to read 4, iclass 12, count 0 2006.197.08:15:18.83#ibcon#read 4, iclass 12, count 0 2006.197.08:15:18.83#ibcon#about to read 5, iclass 12, count 0 2006.197.08:15:18.83#ibcon#read 5, iclass 12, count 0 2006.197.08:15:18.83#ibcon#about to read 6, iclass 12, count 0 2006.197.08:15:18.83#ibcon#read 6, iclass 12, count 0 2006.197.08:15:18.83#ibcon#end of sib2, iclass 12, count 0 2006.197.08:15:18.83#ibcon#*mode == 0, iclass 12, count 0 2006.197.08:15:18.83#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.197.08:15:18.83#ibcon#[26=FRQ=05,652.99\r\n] 2006.197.08:15:18.83#ibcon#*before write, iclass 12, count 0 2006.197.08:15:18.83#ibcon#enter sib2, iclass 12, count 0 2006.197.08:15:18.83#ibcon#flushed, iclass 12, count 0 2006.197.08:15:18.83#ibcon#about to write, iclass 12, count 0 2006.197.08:15:18.83#ibcon#wrote, iclass 12, count 0 2006.197.08:15:18.83#ibcon#about to read 3, iclass 12, count 0 2006.197.08:15:18.87#ibcon#read 3, iclass 12, count 0 2006.197.08:15:18.87#ibcon#about to read 4, iclass 12, count 0 2006.197.08:15:18.87#ibcon#read 4, iclass 12, count 0 2006.197.08:15:18.87#ibcon#about to read 5, iclass 12, count 0 2006.197.08:15:18.87#ibcon#read 5, iclass 12, count 0 2006.197.08:15:18.87#ibcon#about to read 6, iclass 12, count 0 2006.197.08:15:18.87#ibcon#read 6, iclass 12, count 0 2006.197.08:15:18.87#ibcon#end of sib2, iclass 12, count 0 2006.197.08:15:18.87#ibcon#*after write, iclass 12, count 0 2006.197.08:15:18.87#ibcon#*before return 0, iclass 12, count 0 2006.197.08:15:18.87#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.197.08:15:18.87#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.197.08:15:18.87#ibcon#about to clear, iclass 12 cls_cnt 0 2006.197.08:15:18.87#ibcon#cleared, iclass 12 cls_cnt 0 2006.197.08:15:18.87$vc4f8/va=5,7 2006.197.08:15:18.87#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.197.08:15:18.87#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.197.08:15:18.87#ibcon#ireg 11 cls_cnt 2 2006.197.08:15:18.87#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.197.08:15:18.93#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.197.08:15:18.93#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.197.08:15:18.93#ibcon#enter wrdev, iclass 14, count 2 2006.197.08:15:18.93#ibcon#first serial, iclass 14, count 2 2006.197.08:15:18.93#ibcon#enter sib2, iclass 14, count 2 2006.197.08:15:18.93#ibcon#flushed, iclass 14, count 2 2006.197.08:15:18.93#ibcon#about to write, iclass 14, count 2 2006.197.08:15:18.93#ibcon#wrote, iclass 14, count 2 2006.197.08:15:18.93#ibcon#about to read 3, iclass 14, count 2 2006.197.08:15:18.95#ibcon#read 3, iclass 14, count 2 2006.197.08:15:18.95#ibcon#about to read 4, iclass 14, count 2 2006.197.08:15:18.95#ibcon#read 4, iclass 14, count 2 2006.197.08:15:18.95#ibcon#about to read 5, iclass 14, count 2 2006.197.08:15:18.95#ibcon#read 5, iclass 14, count 2 2006.197.08:15:18.95#ibcon#about to read 6, iclass 14, count 2 2006.197.08:15:18.95#ibcon#read 6, iclass 14, count 2 2006.197.08:15:18.95#ibcon#end of sib2, iclass 14, count 2 2006.197.08:15:18.95#ibcon#*mode == 0, iclass 14, count 2 2006.197.08:15:18.95#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.197.08:15:18.95#ibcon#[25=AT05-07\r\n] 2006.197.08:15:18.95#ibcon#*before write, iclass 14, count 2 2006.197.08:15:18.95#ibcon#enter sib2, iclass 14, count 2 2006.197.08:15:18.95#ibcon#flushed, iclass 14, count 2 2006.197.08:15:18.95#ibcon#about to write, iclass 14, count 2 2006.197.08:15:18.95#ibcon#wrote, iclass 14, count 2 2006.197.08:15:18.95#ibcon#about to read 3, iclass 14, count 2 2006.197.08:15:18.98#ibcon#read 3, iclass 14, count 2 2006.197.08:15:18.98#ibcon#about to read 4, iclass 14, count 2 2006.197.08:15:18.98#ibcon#read 4, iclass 14, count 2 2006.197.08:15:18.98#ibcon#about to read 5, iclass 14, count 2 2006.197.08:15:18.98#ibcon#read 5, iclass 14, count 2 2006.197.08:15:18.98#ibcon#about to read 6, iclass 14, count 2 2006.197.08:15:18.98#ibcon#read 6, iclass 14, count 2 2006.197.08:15:18.98#ibcon#end of sib2, iclass 14, count 2 2006.197.08:15:18.98#ibcon#*after write, iclass 14, count 2 2006.197.08:15:18.98#ibcon#*before return 0, iclass 14, count 2 2006.197.08:15:18.98#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.197.08:15:18.98#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.197.08:15:18.98#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.197.08:15:18.98#ibcon#ireg 7 cls_cnt 0 2006.197.08:15:18.98#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.197.08:15:19.10#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.197.08:15:19.10#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.197.08:15:19.10#ibcon#enter wrdev, iclass 14, count 0 2006.197.08:15:19.10#ibcon#first serial, iclass 14, count 0 2006.197.08:15:19.10#ibcon#enter sib2, iclass 14, count 0 2006.197.08:15:19.10#ibcon#flushed, iclass 14, count 0 2006.197.08:15:19.10#ibcon#about to write, iclass 14, count 0 2006.197.08:15:19.10#ibcon#wrote, iclass 14, count 0 2006.197.08:15:19.10#ibcon#about to read 3, iclass 14, count 0 2006.197.08:15:19.12#ibcon#read 3, iclass 14, count 0 2006.197.08:15:19.12#ibcon#about to read 4, iclass 14, count 0 2006.197.08:15:19.12#ibcon#read 4, iclass 14, count 0 2006.197.08:15:19.12#ibcon#about to read 5, iclass 14, count 0 2006.197.08:15:19.12#ibcon#read 5, iclass 14, count 0 2006.197.08:15:19.12#ibcon#about to read 6, iclass 14, count 0 2006.197.08:15:19.12#ibcon#read 6, iclass 14, count 0 2006.197.08:15:19.12#ibcon#end of sib2, iclass 14, count 0 2006.197.08:15:19.12#ibcon#*mode == 0, iclass 14, count 0 2006.197.08:15:19.12#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.197.08:15:19.12#ibcon#[25=USB\r\n] 2006.197.08:15:19.12#ibcon#*before write, iclass 14, count 0 2006.197.08:15:19.12#ibcon#enter sib2, iclass 14, count 0 2006.197.08:15:19.12#ibcon#flushed, iclass 14, count 0 2006.197.08:15:19.12#ibcon#about to write, iclass 14, count 0 2006.197.08:15:19.12#ibcon#wrote, iclass 14, count 0 2006.197.08:15:19.12#ibcon#about to read 3, iclass 14, count 0 2006.197.08:15:19.15#ibcon#read 3, iclass 14, count 0 2006.197.08:15:19.15#ibcon#about to read 4, iclass 14, count 0 2006.197.08:15:19.15#ibcon#read 4, iclass 14, count 0 2006.197.08:15:19.15#ibcon#about to read 5, iclass 14, count 0 2006.197.08:15:19.15#ibcon#read 5, iclass 14, count 0 2006.197.08:15:19.15#ibcon#about to read 6, iclass 14, count 0 2006.197.08:15:19.15#ibcon#read 6, iclass 14, count 0 2006.197.08:15:19.15#ibcon#end of sib2, iclass 14, count 0 2006.197.08:15:19.15#ibcon#*after write, iclass 14, count 0 2006.197.08:15:19.15#ibcon#*before return 0, iclass 14, count 0 2006.197.08:15:19.15#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.197.08:15:19.15#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.197.08:15:19.15#ibcon#about to clear, iclass 14 cls_cnt 0 2006.197.08:15:19.15#ibcon#cleared, iclass 14 cls_cnt 0 2006.197.08:15:19.15$vc4f8/valo=6,772.99 2006.197.08:15:19.15#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.197.08:15:19.15#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.197.08:15:19.15#ibcon#ireg 17 cls_cnt 0 2006.197.08:15:19.15#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.197.08:15:19.15#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.197.08:15:19.15#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.197.08:15:19.15#ibcon#enter wrdev, iclass 16, count 0 2006.197.08:15:19.15#ibcon#first serial, iclass 16, count 0 2006.197.08:15:19.15#ibcon#enter sib2, iclass 16, count 0 2006.197.08:15:19.15#ibcon#flushed, iclass 16, count 0 2006.197.08:15:19.15#ibcon#about to write, iclass 16, count 0 2006.197.08:15:19.15#ibcon#wrote, iclass 16, count 0 2006.197.08:15:19.15#ibcon#about to read 3, iclass 16, count 0 2006.197.08:15:19.17#ibcon#read 3, iclass 16, count 0 2006.197.08:15:19.17#ibcon#about to read 4, iclass 16, count 0 2006.197.08:15:19.17#ibcon#read 4, iclass 16, count 0 2006.197.08:15:19.17#ibcon#about to read 5, iclass 16, count 0 2006.197.08:15:19.17#ibcon#read 5, iclass 16, count 0 2006.197.08:15:19.17#ibcon#about to read 6, iclass 16, count 0 2006.197.08:15:19.17#ibcon#read 6, iclass 16, count 0 2006.197.08:15:19.17#ibcon#end of sib2, iclass 16, count 0 2006.197.08:15:19.17#ibcon#*mode == 0, iclass 16, count 0 2006.197.08:15:19.17#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.197.08:15:19.17#ibcon#[26=FRQ=06,772.99\r\n] 2006.197.08:15:19.17#ibcon#*before write, iclass 16, count 0 2006.197.08:15:19.17#ibcon#enter sib2, iclass 16, count 0 2006.197.08:15:19.17#ibcon#flushed, iclass 16, count 0 2006.197.08:15:19.17#ibcon#about to write, iclass 16, count 0 2006.197.08:15:19.17#ibcon#wrote, iclass 16, count 0 2006.197.08:15:19.17#ibcon#about to read 3, iclass 16, count 0 2006.197.08:15:19.21#ibcon#read 3, iclass 16, count 0 2006.197.08:15:19.21#ibcon#about to read 4, iclass 16, count 0 2006.197.08:15:19.21#ibcon#read 4, iclass 16, count 0 2006.197.08:15:19.21#ibcon#about to read 5, iclass 16, count 0 2006.197.08:15:19.21#ibcon#read 5, iclass 16, count 0 2006.197.08:15:19.21#ibcon#about to read 6, iclass 16, count 0 2006.197.08:15:19.21#ibcon#read 6, iclass 16, count 0 2006.197.08:15:19.21#ibcon#end of sib2, iclass 16, count 0 2006.197.08:15:19.21#ibcon#*after write, iclass 16, count 0 2006.197.08:15:19.21#ibcon#*before return 0, iclass 16, count 0 2006.197.08:15:19.21#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.197.08:15:19.21#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.197.08:15:19.21#ibcon#about to clear, iclass 16 cls_cnt 0 2006.197.08:15:19.21#ibcon#cleared, iclass 16 cls_cnt 0 2006.197.08:15:19.21$vc4f8/va=6,6 2006.197.08:15:19.21#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.197.08:15:19.21#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.197.08:15:19.21#ibcon#ireg 11 cls_cnt 2 2006.197.08:15:19.21#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.197.08:15:19.27#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.197.08:15:19.27#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.197.08:15:19.27#ibcon#enter wrdev, iclass 18, count 2 2006.197.08:15:19.27#ibcon#first serial, iclass 18, count 2 2006.197.08:15:19.27#ibcon#enter sib2, iclass 18, count 2 2006.197.08:15:19.27#ibcon#flushed, iclass 18, count 2 2006.197.08:15:19.27#ibcon#about to write, iclass 18, count 2 2006.197.08:15:19.27#ibcon#wrote, iclass 18, count 2 2006.197.08:15:19.27#ibcon#about to read 3, iclass 18, count 2 2006.197.08:15:19.29#ibcon#read 3, iclass 18, count 2 2006.197.08:15:19.29#ibcon#about to read 4, iclass 18, count 2 2006.197.08:15:19.29#ibcon#read 4, iclass 18, count 2 2006.197.08:15:19.29#ibcon#about to read 5, iclass 18, count 2 2006.197.08:15:19.29#ibcon#read 5, iclass 18, count 2 2006.197.08:15:19.29#ibcon#about to read 6, iclass 18, count 2 2006.197.08:15:19.29#ibcon#read 6, iclass 18, count 2 2006.197.08:15:19.29#ibcon#end of sib2, iclass 18, count 2 2006.197.08:15:19.29#ibcon#*mode == 0, iclass 18, count 2 2006.197.08:15:19.29#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.197.08:15:19.29#ibcon#[25=AT06-06\r\n] 2006.197.08:15:19.29#ibcon#*before write, iclass 18, count 2 2006.197.08:15:19.29#ibcon#enter sib2, iclass 18, count 2 2006.197.08:15:19.29#ibcon#flushed, iclass 18, count 2 2006.197.08:15:19.29#ibcon#about to write, iclass 18, count 2 2006.197.08:15:19.29#ibcon#wrote, iclass 18, count 2 2006.197.08:15:19.29#ibcon#about to read 3, iclass 18, count 2 2006.197.08:15:19.32#ibcon#read 3, iclass 18, count 2 2006.197.08:15:19.32#ibcon#about to read 4, iclass 18, count 2 2006.197.08:15:19.32#ibcon#read 4, iclass 18, count 2 2006.197.08:15:19.32#ibcon#about to read 5, iclass 18, count 2 2006.197.08:15:19.32#ibcon#read 5, iclass 18, count 2 2006.197.08:15:19.32#ibcon#about to read 6, iclass 18, count 2 2006.197.08:15:19.32#ibcon#read 6, iclass 18, count 2 2006.197.08:15:19.32#ibcon#end of sib2, iclass 18, count 2 2006.197.08:15:19.32#ibcon#*after write, iclass 18, count 2 2006.197.08:15:19.32#ibcon#*before return 0, iclass 18, count 2 2006.197.08:15:19.32#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.197.08:15:19.32#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.197.08:15:19.32#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.197.08:15:19.32#ibcon#ireg 7 cls_cnt 0 2006.197.08:15:19.32#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.197.08:15:19.44#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.197.08:15:19.44#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.197.08:15:19.44#ibcon#enter wrdev, iclass 18, count 0 2006.197.08:15:19.44#ibcon#first serial, iclass 18, count 0 2006.197.08:15:19.44#ibcon#enter sib2, iclass 18, count 0 2006.197.08:15:19.44#ibcon#flushed, iclass 18, count 0 2006.197.08:15:19.44#ibcon#about to write, iclass 18, count 0 2006.197.08:15:19.44#ibcon#wrote, iclass 18, count 0 2006.197.08:15:19.44#ibcon#about to read 3, iclass 18, count 0 2006.197.08:15:19.46#ibcon#read 3, iclass 18, count 0 2006.197.08:15:19.46#ibcon#about to read 4, iclass 18, count 0 2006.197.08:15:19.46#ibcon#read 4, iclass 18, count 0 2006.197.08:15:19.46#ibcon#about to read 5, iclass 18, count 0 2006.197.08:15:19.46#ibcon#read 5, iclass 18, count 0 2006.197.08:15:19.46#ibcon#about to read 6, iclass 18, count 0 2006.197.08:15:19.46#ibcon#read 6, iclass 18, count 0 2006.197.08:15:19.46#ibcon#end of sib2, iclass 18, count 0 2006.197.08:15:19.46#ibcon#*mode == 0, iclass 18, count 0 2006.197.08:15:19.46#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.197.08:15:19.46#ibcon#[25=USB\r\n] 2006.197.08:15:19.46#ibcon#*before write, iclass 18, count 0 2006.197.08:15:19.46#ibcon#enter sib2, iclass 18, count 0 2006.197.08:15:19.46#ibcon#flushed, iclass 18, count 0 2006.197.08:15:19.46#ibcon#about to write, iclass 18, count 0 2006.197.08:15:19.46#ibcon#wrote, iclass 18, count 0 2006.197.08:15:19.46#ibcon#about to read 3, iclass 18, count 0 2006.197.08:15:19.49#ibcon#read 3, iclass 18, count 0 2006.197.08:15:19.49#ibcon#about to read 4, iclass 18, count 0 2006.197.08:15:19.49#ibcon#read 4, iclass 18, count 0 2006.197.08:15:19.49#ibcon#about to read 5, iclass 18, count 0 2006.197.08:15:19.49#ibcon#read 5, iclass 18, count 0 2006.197.08:15:19.49#ibcon#about to read 6, iclass 18, count 0 2006.197.08:15:19.49#ibcon#read 6, iclass 18, count 0 2006.197.08:15:19.49#ibcon#end of sib2, iclass 18, count 0 2006.197.08:15:19.49#ibcon#*after write, iclass 18, count 0 2006.197.08:15:19.49#ibcon#*before return 0, iclass 18, count 0 2006.197.08:15:19.49#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.197.08:15:19.49#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.197.08:15:19.49#ibcon#about to clear, iclass 18 cls_cnt 0 2006.197.08:15:19.49#ibcon#cleared, iclass 18 cls_cnt 0 2006.197.08:15:19.49$vc4f8/valo=7,832.99 2006.197.08:15:19.49#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.197.08:15:19.49#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.197.08:15:19.49#ibcon#ireg 17 cls_cnt 0 2006.197.08:15:19.49#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.197.08:15:19.49#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.197.08:15:19.49#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.197.08:15:19.49#ibcon#enter wrdev, iclass 20, count 0 2006.197.08:15:19.49#ibcon#first serial, iclass 20, count 0 2006.197.08:15:19.49#ibcon#enter sib2, iclass 20, count 0 2006.197.08:15:19.49#ibcon#flushed, iclass 20, count 0 2006.197.08:15:19.49#ibcon#about to write, iclass 20, count 0 2006.197.08:15:19.49#ibcon#wrote, iclass 20, count 0 2006.197.08:15:19.49#ibcon#about to read 3, iclass 20, count 0 2006.197.08:15:19.51#ibcon#read 3, iclass 20, count 0 2006.197.08:15:19.51#ibcon#about to read 4, iclass 20, count 0 2006.197.08:15:19.51#ibcon#read 4, iclass 20, count 0 2006.197.08:15:19.51#ibcon#about to read 5, iclass 20, count 0 2006.197.08:15:19.51#ibcon#read 5, iclass 20, count 0 2006.197.08:15:19.51#ibcon#about to read 6, iclass 20, count 0 2006.197.08:15:19.51#ibcon#read 6, iclass 20, count 0 2006.197.08:15:19.51#ibcon#end of sib2, iclass 20, count 0 2006.197.08:15:19.51#ibcon#*mode == 0, iclass 20, count 0 2006.197.08:15:19.51#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.197.08:15:19.51#ibcon#[26=FRQ=07,832.99\r\n] 2006.197.08:15:19.51#ibcon#*before write, iclass 20, count 0 2006.197.08:15:19.51#ibcon#enter sib2, iclass 20, count 0 2006.197.08:15:19.51#ibcon#flushed, iclass 20, count 0 2006.197.08:15:19.51#ibcon#about to write, iclass 20, count 0 2006.197.08:15:19.51#ibcon#wrote, iclass 20, count 0 2006.197.08:15:19.51#ibcon#about to read 3, iclass 20, count 0 2006.197.08:15:19.55#ibcon#read 3, iclass 20, count 0 2006.197.08:15:19.55#ibcon#about to read 4, iclass 20, count 0 2006.197.08:15:19.55#ibcon#read 4, iclass 20, count 0 2006.197.08:15:19.55#ibcon#about to read 5, iclass 20, count 0 2006.197.08:15:19.55#ibcon#read 5, iclass 20, count 0 2006.197.08:15:19.55#ibcon#about to read 6, iclass 20, count 0 2006.197.08:15:19.55#ibcon#read 6, iclass 20, count 0 2006.197.08:15:19.55#ibcon#end of sib2, iclass 20, count 0 2006.197.08:15:19.55#ibcon#*after write, iclass 20, count 0 2006.197.08:15:19.55#ibcon#*before return 0, iclass 20, count 0 2006.197.08:15:19.55#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.197.08:15:19.55#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.197.08:15:19.55#ibcon#about to clear, iclass 20 cls_cnt 0 2006.197.08:15:19.55#ibcon#cleared, iclass 20 cls_cnt 0 2006.197.08:15:19.55$vc4f8/va=7,6 2006.197.08:15:19.55#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.197.08:15:19.55#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.197.08:15:19.55#ibcon#ireg 11 cls_cnt 2 2006.197.08:15:19.55#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.197.08:15:19.61#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.197.08:15:19.61#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.197.08:15:19.61#ibcon#enter wrdev, iclass 22, count 2 2006.197.08:15:19.61#ibcon#first serial, iclass 22, count 2 2006.197.08:15:19.61#ibcon#enter sib2, iclass 22, count 2 2006.197.08:15:19.61#ibcon#flushed, iclass 22, count 2 2006.197.08:15:19.61#ibcon#about to write, iclass 22, count 2 2006.197.08:15:19.61#ibcon#wrote, iclass 22, count 2 2006.197.08:15:19.61#ibcon#about to read 3, iclass 22, count 2 2006.197.08:15:19.63#ibcon#read 3, iclass 22, count 2 2006.197.08:15:19.63#ibcon#about to read 4, iclass 22, count 2 2006.197.08:15:19.63#ibcon#read 4, iclass 22, count 2 2006.197.08:15:19.63#ibcon#about to read 5, iclass 22, count 2 2006.197.08:15:19.63#ibcon#read 5, iclass 22, count 2 2006.197.08:15:19.63#ibcon#about to read 6, iclass 22, count 2 2006.197.08:15:19.63#ibcon#read 6, iclass 22, count 2 2006.197.08:15:19.63#ibcon#end of sib2, iclass 22, count 2 2006.197.08:15:19.63#ibcon#*mode == 0, iclass 22, count 2 2006.197.08:15:19.63#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.197.08:15:19.63#ibcon#[25=AT07-06\r\n] 2006.197.08:15:19.63#ibcon#*before write, iclass 22, count 2 2006.197.08:15:19.63#ibcon#enter sib2, iclass 22, count 2 2006.197.08:15:19.63#ibcon#flushed, iclass 22, count 2 2006.197.08:15:19.63#ibcon#about to write, iclass 22, count 2 2006.197.08:15:19.63#ibcon#wrote, iclass 22, count 2 2006.197.08:15:19.63#ibcon#about to read 3, iclass 22, count 2 2006.197.08:15:19.66#ibcon#read 3, iclass 22, count 2 2006.197.08:15:19.66#ibcon#about to read 4, iclass 22, count 2 2006.197.08:15:19.66#ibcon#read 4, iclass 22, count 2 2006.197.08:15:19.66#ibcon#about to read 5, iclass 22, count 2 2006.197.08:15:19.66#ibcon#read 5, iclass 22, count 2 2006.197.08:15:19.66#ibcon#about to read 6, iclass 22, count 2 2006.197.08:15:19.66#ibcon#read 6, iclass 22, count 2 2006.197.08:15:19.66#ibcon#end of sib2, iclass 22, count 2 2006.197.08:15:19.66#ibcon#*after write, iclass 22, count 2 2006.197.08:15:19.66#ibcon#*before return 0, iclass 22, count 2 2006.197.08:15:19.66#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.197.08:15:19.66#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.197.08:15:19.66#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.197.08:15:19.66#ibcon#ireg 7 cls_cnt 0 2006.197.08:15:19.66#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.197.08:15:19.78#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.197.08:15:19.78#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.197.08:15:19.78#ibcon#enter wrdev, iclass 22, count 0 2006.197.08:15:19.78#ibcon#first serial, iclass 22, count 0 2006.197.08:15:19.78#ibcon#enter sib2, iclass 22, count 0 2006.197.08:15:19.78#ibcon#flushed, iclass 22, count 0 2006.197.08:15:19.78#ibcon#about to write, iclass 22, count 0 2006.197.08:15:19.78#ibcon#wrote, iclass 22, count 0 2006.197.08:15:19.78#ibcon#about to read 3, iclass 22, count 0 2006.197.08:15:19.80#ibcon#read 3, iclass 22, count 0 2006.197.08:15:19.80#ibcon#about to read 4, iclass 22, count 0 2006.197.08:15:19.80#ibcon#read 4, iclass 22, count 0 2006.197.08:15:19.80#ibcon#about to read 5, iclass 22, count 0 2006.197.08:15:19.80#ibcon#read 5, iclass 22, count 0 2006.197.08:15:19.80#ibcon#about to read 6, iclass 22, count 0 2006.197.08:15:19.80#ibcon#read 6, iclass 22, count 0 2006.197.08:15:19.80#ibcon#end of sib2, iclass 22, count 0 2006.197.08:15:19.80#ibcon#*mode == 0, iclass 22, count 0 2006.197.08:15:19.80#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.197.08:15:19.80#ibcon#[25=USB\r\n] 2006.197.08:15:19.80#ibcon#*before write, iclass 22, count 0 2006.197.08:15:19.80#ibcon#enter sib2, iclass 22, count 0 2006.197.08:15:19.80#ibcon#flushed, iclass 22, count 0 2006.197.08:15:19.80#ibcon#about to write, iclass 22, count 0 2006.197.08:15:19.80#ibcon#wrote, iclass 22, count 0 2006.197.08:15:19.80#ibcon#about to read 3, iclass 22, count 0 2006.197.08:15:19.83#ibcon#read 3, iclass 22, count 0 2006.197.08:15:19.83#ibcon#about to read 4, iclass 22, count 0 2006.197.08:15:19.83#ibcon#read 4, iclass 22, count 0 2006.197.08:15:19.83#ibcon#about to read 5, iclass 22, count 0 2006.197.08:15:19.83#ibcon#read 5, iclass 22, count 0 2006.197.08:15:19.83#ibcon#about to read 6, iclass 22, count 0 2006.197.08:15:19.83#ibcon#read 6, iclass 22, count 0 2006.197.08:15:19.83#ibcon#end of sib2, iclass 22, count 0 2006.197.08:15:19.83#ibcon#*after write, iclass 22, count 0 2006.197.08:15:19.83#ibcon#*before return 0, iclass 22, count 0 2006.197.08:15:19.83#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.197.08:15:19.83#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.197.08:15:19.83#ibcon#about to clear, iclass 22 cls_cnt 0 2006.197.08:15:19.83#ibcon#cleared, iclass 22 cls_cnt 0 2006.197.08:15:19.83$vc4f8/valo=8,852.99 2006.197.08:15:19.83#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.197.08:15:19.83#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.197.08:15:19.83#ibcon#ireg 17 cls_cnt 0 2006.197.08:15:19.83#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.197.08:15:19.83#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.197.08:15:19.83#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.197.08:15:19.83#ibcon#enter wrdev, iclass 24, count 0 2006.197.08:15:19.83#ibcon#first serial, iclass 24, count 0 2006.197.08:15:19.83#ibcon#enter sib2, iclass 24, count 0 2006.197.08:15:19.83#ibcon#flushed, iclass 24, count 0 2006.197.08:15:19.83#ibcon#about to write, iclass 24, count 0 2006.197.08:15:19.83#ibcon#wrote, iclass 24, count 0 2006.197.08:15:19.83#ibcon#about to read 3, iclass 24, count 0 2006.197.08:15:19.85#ibcon#read 3, iclass 24, count 0 2006.197.08:15:19.85#ibcon#about to read 4, iclass 24, count 0 2006.197.08:15:19.85#ibcon#read 4, iclass 24, count 0 2006.197.08:15:19.85#ibcon#about to read 5, iclass 24, count 0 2006.197.08:15:19.85#ibcon#read 5, iclass 24, count 0 2006.197.08:15:19.85#ibcon#about to read 6, iclass 24, count 0 2006.197.08:15:19.85#ibcon#read 6, iclass 24, count 0 2006.197.08:15:19.85#ibcon#end of sib2, iclass 24, count 0 2006.197.08:15:19.85#ibcon#*mode == 0, iclass 24, count 0 2006.197.08:15:19.85#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.197.08:15:19.85#ibcon#[26=FRQ=08,852.99\r\n] 2006.197.08:15:19.85#ibcon#*before write, iclass 24, count 0 2006.197.08:15:19.85#ibcon#enter sib2, iclass 24, count 0 2006.197.08:15:19.85#ibcon#flushed, iclass 24, count 0 2006.197.08:15:19.85#ibcon#about to write, iclass 24, count 0 2006.197.08:15:19.85#ibcon#wrote, iclass 24, count 0 2006.197.08:15:19.85#ibcon#about to read 3, iclass 24, count 0 2006.197.08:15:19.89#ibcon#read 3, iclass 24, count 0 2006.197.08:15:19.89#ibcon#about to read 4, iclass 24, count 0 2006.197.08:15:19.89#ibcon#read 4, iclass 24, count 0 2006.197.08:15:19.89#ibcon#about to read 5, iclass 24, count 0 2006.197.08:15:19.89#ibcon#read 5, iclass 24, count 0 2006.197.08:15:19.89#ibcon#about to read 6, iclass 24, count 0 2006.197.08:15:19.89#ibcon#read 6, iclass 24, count 0 2006.197.08:15:19.89#ibcon#end of sib2, iclass 24, count 0 2006.197.08:15:19.89#ibcon#*after write, iclass 24, count 0 2006.197.08:15:19.89#ibcon#*before return 0, iclass 24, count 0 2006.197.08:15:19.89#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.197.08:15:19.89#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.197.08:15:19.89#ibcon#about to clear, iclass 24 cls_cnt 0 2006.197.08:15:19.89#ibcon#cleared, iclass 24 cls_cnt 0 2006.197.08:15:19.89$vc4f8/va=8,7 2006.197.08:15:19.89#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.197.08:15:19.89#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.197.08:15:19.89#ibcon#ireg 11 cls_cnt 2 2006.197.08:15:19.89#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.197.08:15:19.95#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.197.08:15:19.95#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.197.08:15:19.95#ibcon#enter wrdev, iclass 26, count 2 2006.197.08:15:19.95#ibcon#first serial, iclass 26, count 2 2006.197.08:15:19.95#ibcon#enter sib2, iclass 26, count 2 2006.197.08:15:19.95#ibcon#flushed, iclass 26, count 2 2006.197.08:15:19.95#ibcon#about to write, iclass 26, count 2 2006.197.08:15:19.95#ibcon#wrote, iclass 26, count 2 2006.197.08:15:19.95#ibcon#about to read 3, iclass 26, count 2 2006.197.08:15:19.97#ibcon#read 3, iclass 26, count 2 2006.197.08:15:19.97#ibcon#about to read 4, iclass 26, count 2 2006.197.08:15:19.97#ibcon#read 4, iclass 26, count 2 2006.197.08:15:19.97#ibcon#about to read 5, iclass 26, count 2 2006.197.08:15:19.97#ibcon#read 5, iclass 26, count 2 2006.197.08:15:19.97#ibcon#about to read 6, iclass 26, count 2 2006.197.08:15:19.97#ibcon#read 6, iclass 26, count 2 2006.197.08:15:19.97#ibcon#end of sib2, iclass 26, count 2 2006.197.08:15:19.97#ibcon#*mode == 0, iclass 26, count 2 2006.197.08:15:19.97#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.197.08:15:19.97#ibcon#[25=AT08-07\r\n] 2006.197.08:15:19.97#ibcon#*before write, iclass 26, count 2 2006.197.08:15:19.97#ibcon#enter sib2, iclass 26, count 2 2006.197.08:15:19.97#ibcon#flushed, iclass 26, count 2 2006.197.08:15:19.97#ibcon#about to write, iclass 26, count 2 2006.197.08:15:19.97#ibcon#wrote, iclass 26, count 2 2006.197.08:15:19.97#ibcon#about to read 3, iclass 26, count 2 2006.197.08:15:20.00#ibcon#read 3, iclass 26, count 2 2006.197.08:15:20.00#ibcon#about to read 4, iclass 26, count 2 2006.197.08:15:20.00#ibcon#read 4, iclass 26, count 2 2006.197.08:15:20.00#ibcon#about to read 5, iclass 26, count 2 2006.197.08:15:20.00#ibcon#read 5, iclass 26, count 2 2006.197.08:15:20.00#ibcon#about to read 6, iclass 26, count 2 2006.197.08:15:20.00#ibcon#read 6, iclass 26, count 2 2006.197.08:15:20.00#ibcon#end of sib2, iclass 26, count 2 2006.197.08:15:20.00#ibcon#*after write, iclass 26, count 2 2006.197.08:15:20.00#ibcon#*before return 0, iclass 26, count 2 2006.197.08:15:20.00#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.197.08:15:20.00#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.197.08:15:20.00#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.197.08:15:20.00#ibcon#ireg 7 cls_cnt 0 2006.197.08:15:20.00#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.197.08:15:20.12#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.197.08:15:20.12#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.197.08:15:20.12#ibcon#enter wrdev, iclass 26, count 0 2006.197.08:15:20.12#ibcon#first serial, iclass 26, count 0 2006.197.08:15:20.12#ibcon#enter sib2, iclass 26, count 0 2006.197.08:15:20.12#ibcon#flushed, iclass 26, count 0 2006.197.08:15:20.12#ibcon#about to write, iclass 26, count 0 2006.197.08:15:20.12#ibcon#wrote, iclass 26, count 0 2006.197.08:15:20.12#ibcon#about to read 3, iclass 26, count 0 2006.197.08:15:20.14#ibcon#read 3, iclass 26, count 0 2006.197.08:15:20.14#ibcon#about to read 4, iclass 26, count 0 2006.197.08:15:20.14#ibcon#read 4, iclass 26, count 0 2006.197.08:15:20.14#ibcon#about to read 5, iclass 26, count 0 2006.197.08:15:20.14#ibcon#read 5, iclass 26, count 0 2006.197.08:15:20.14#ibcon#about to read 6, iclass 26, count 0 2006.197.08:15:20.14#ibcon#read 6, iclass 26, count 0 2006.197.08:15:20.14#ibcon#end of sib2, iclass 26, count 0 2006.197.08:15:20.14#ibcon#*mode == 0, iclass 26, count 0 2006.197.08:15:20.14#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.197.08:15:20.14#ibcon#[25=USB\r\n] 2006.197.08:15:20.14#ibcon#*before write, iclass 26, count 0 2006.197.08:15:20.14#ibcon#enter sib2, iclass 26, count 0 2006.197.08:15:20.14#ibcon#flushed, iclass 26, count 0 2006.197.08:15:20.14#ibcon#about to write, iclass 26, count 0 2006.197.08:15:20.14#ibcon#wrote, iclass 26, count 0 2006.197.08:15:20.14#ibcon#about to read 3, iclass 26, count 0 2006.197.08:15:20.17#ibcon#read 3, iclass 26, count 0 2006.197.08:15:20.17#ibcon#about to read 4, iclass 26, count 0 2006.197.08:15:20.17#ibcon#read 4, iclass 26, count 0 2006.197.08:15:20.17#ibcon#about to read 5, iclass 26, count 0 2006.197.08:15:20.17#ibcon#read 5, iclass 26, count 0 2006.197.08:15:20.17#ibcon#about to read 6, iclass 26, count 0 2006.197.08:15:20.17#ibcon#read 6, iclass 26, count 0 2006.197.08:15:20.17#ibcon#end of sib2, iclass 26, count 0 2006.197.08:15:20.17#ibcon#*after write, iclass 26, count 0 2006.197.08:15:20.17#ibcon#*before return 0, iclass 26, count 0 2006.197.08:15:20.17#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.197.08:15:20.17#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.197.08:15:20.17#ibcon#about to clear, iclass 26 cls_cnt 0 2006.197.08:15:20.17#ibcon#cleared, iclass 26 cls_cnt 0 2006.197.08:15:20.17$vc4f8/vblo=1,632.99 2006.197.08:15:20.17#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.197.08:15:20.17#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.197.08:15:20.17#ibcon#ireg 17 cls_cnt 0 2006.197.08:15:20.17#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.197.08:15:20.17#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.197.08:15:20.17#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.197.08:15:20.17#ibcon#enter wrdev, iclass 28, count 0 2006.197.08:15:20.17#ibcon#first serial, iclass 28, count 0 2006.197.08:15:20.17#ibcon#enter sib2, iclass 28, count 0 2006.197.08:15:20.17#ibcon#flushed, iclass 28, count 0 2006.197.08:15:20.17#ibcon#about to write, iclass 28, count 0 2006.197.08:15:20.17#ibcon#wrote, iclass 28, count 0 2006.197.08:15:20.17#ibcon#about to read 3, iclass 28, count 0 2006.197.08:15:20.19#ibcon#read 3, iclass 28, count 0 2006.197.08:15:20.19#ibcon#about to read 4, iclass 28, count 0 2006.197.08:15:20.19#ibcon#read 4, iclass 28, count 0 2006.197.08:15:20.19#ibcon#about to read 5, iclass 28, count 0 2006.197.08:15:20.19#ibcon#read 5, iclass 28, count 0 2006.197.08:15:20.19#ibcon#about to read 6, iclass 28, count 0 2006.197.08:15:20.19#ibcon#read 6, iclass 28, count 0 2006.197.08:15:20.19#ibcon#end of sib2, iclass 28, count 0 2006.197.08:15:20.19#ibcon#*mode == 0, iclass 28, count 0 2006.197.08:15:20.19#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.197.08:15:20.19#ibcon#[28=FRQ=01,632.99\r\n] 2006.197.08:15:20.19#ibcon#*before write, iclass 28, count 0 2006.197.08:15:20.19#ibcon#enter sib2, iclass 28, count 0 2006.197.08:15:20.19#ibcon#flushed, iclass 28, count 0 2006.197.08:15:20.19#ibcon#about to write, iclass 28, count 0 2006.197.08:15:20.19#ibcon#wrote, iclass 28, count 0 2006.197.08:15:20.19#ibcon#about to read 3, iclass 28, count 0 2006.197.08:15:20.23#ibcon#read 3, iclass 28, count 0 2006.197.08:15:20.23#ibcon#about to read 4, iclass 28, count 0 2006.197.08:15:20.23#ibcon#read 4, iclass 28, count 0 2006.197.08:15:20.23#ibcon#about to read 5, iclass 28, count 0 2006.197.08:15:20.23#ibcon#read 5, iclass 28, count 0 2006.197.08:15:20.23#ibcon#about to read 6, iclass 28, count 0 2006.197.08:15:20.23#ibcon#read 6, iclass 28, count 0 2006.197.08:15:20.23#ibcon#end of sib2, iclass 28, count 0 2006.197.08:15:20.23#ibcon#*after write, iclass 28, count 0 2006.197.08:15:20.23#ibcon#*before return 0, iclass 28, count 0 2006.197.08:15:20.23#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.197.08:15:20.23#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.197.08:15:20.23#ibcon#about to clear, iclass 28 cls_cnt 0 2006.197.08:15:20.23#ibcon#cleared, iclass 28 cls_cnt 0 2006.197.08:15:20.23$vc4f8/vb=1,4 2006.197.08:15:20.23#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.197.08:15:20.23#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.197.08:15:20.23#ibcon#ireg 11 cls_cnt 2 2006.197.08:15:20.23#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.197.08:15:20.23#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.197.08:15:20.23#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.197.08:15:20.23#ibcon#enter wrdev, iclass 30, count 2 2006.197.08:15:20.23#ibcon#first serial, iclass 30, count 2 2006.197.08:15:20.23#ibcon#enter sib2, iclass 30, count 2 2006.197.08:15:20.23#ibcon#flushed, iclass 30, count 2 2006.197.08:15:20.23#ibcon#about to write, iclass 30, count 2 2006.197.08:15:20.23#ibcon#wrote, iclass 30, count 2 2006.197.08:15:20.23#ibcon#about to read 3, iclass 30, count 2 2006.197.08:15:20.25#ibcon#read 3, iclass 30, count 2 2006.197.08:15:20.25#ibcon#about to read 4, iclass 30, count 2 2006.197.08:15:20.25#ibcon#read 4, iclass 30, count 2 2006.197.08:15:20.25#ibcon#about to read 5, iclass 30, count 2 2006.197.08:15:20.25#ibcon#read 5, iclass 30, count 2 2006.197.08:15:20.25#ibcon#about to read 6, iclass 30, count 2 2006.197.08:15:20.25#ibcon#read 6, iclass 30, count 2 2006.197.08:15:20.25#ibcon#end of sib2, iclass 30, count 2 2006.197.08:15:20.25#ibcon#*mode == 0, iclass 30, count 2 2006.197.08:15:20.25#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.197.08:15:20.25#ibcon#[27=AT01-04\r\n] 2006.197.08:15:20.25#ibcon#*before write, iclass 30, count 2 2006.197.08:15:20.25#ibcon#enter sib2, iclass 30, count 2 2006.197.08:15:20.25#ibcon#flushed, iclass 30, count 2 2006.197.08:15:20.25#ibcon#about to write, iclass 30, count 2 2006.197.08:15:20.25#ibcon#wrote, iclass 30, count 2 2006.197.08:15:20.25#ibcon#about to read 3, iclass 30, count 2 2006.197.08:15:20.28#ibcon#read 3, iclass 30, count 2 2006.197.08:15:20.28#ibcon#about to read 4, iclass 30, count 2 2006.197.08:15:20.28#ibcon#read 4, iclass 30, count 2 2006.197.08:15:20.28#ibcon#about to read 5, iclass 30, count 2 2006.197.08:15:20.28#ibcon#read 5, iclass 30, count 2 2006.197.08:15:20.28#ibcon#about to read 6, iclass 30, count 2 2006.197.08:15:20.28#ibcon#read 6, iclass 30, count 2 2006.197.08:15:20.28#ibcon#end of sib2, iclass 30, count 2 2006.197.08:15:20.28#ibcon#*after write, iclass 30, count 2 2006.197.08:15:20.28#ibcon#*before return 0, iclass 30, count 2 2006.197.08:15:20.28#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.197.08:15:20.28#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.197.08:15:20.28#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.197.08:15:20.28#ibcon#ireg 7 cls_cnt 0 2006.197.08:15:20.28#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.197.08:15:20.40#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.197.08:15:20.40#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.197.08:15:20.40#ibcon#enter wrdev, iclass 30, count 0 2006.197.08:15:20.40#ibcon#first serial, iclass 30, count 0 2006.197.08:15:20.40#ibcon#enter sib2, iclass 30, count 0 2006.197.08:15:20.40#ibcon#flushed, iclass 30, count 0 2006.197.08:15:20.40#ibcon#about to write, iclass 30, count 0 2006.197.08:15:20.40#ibcon#wrote, iclass 30, count 0 2006.197.08:15:20.40#ibcon#about to read 3, iclass 30, count 0 2006.197.08:15:20.42#ibcon#read 3, iclass 30, count 0 2006.197.08:15:20.42#ibcon#about to read 4, iclass 30, count 0 2006.197.08:15:20.42#ibcon#read 4, iclass 30, count 0 2006.197.08:15:20.42#ibcon#about to read 5, iclass 30, count 0 2006.197.08:15:20.42#ibcon#read 5, iclass 30, count 0 2006.197.08:15:20.42#ibcon#about to read 6, iclass 30, count 0 2006.197.08:15:20.42#ibcon#read 6, iclass 30, count 0 2006.197.08:15:20.42#ibcon#end of sib2, iclass 30, count 0 2006.197.08:15:20.42#ibcon#*mode == 0, iclass 30, count 0 2006.197.08:15:20.42#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.197.08:15:20.42#ibcon#[27=USB\r\n] 2006.197.08:15:20.42#ibcon#*before write, iclass 30, count 0 2006.197.08:15:20.42#ibcon#enter sib2, iclass 30, count 0 2006.197.08:15:20.42#ibcon#flushed, iclass 30, count 0 2006.197.08:15:20.42#ibcon#about to write, iclass 30, count 0 2006.197.08:15:20.42#ibcon#wrote, iclass 30, count 0 2006.197.08:15:20.42#ibcon#about to read 3, iclass 30, count 0 2006.197.08:15:20.45#ibcon#read 3, iclass 30, count 0 2006.197.08:15:20.45#ibcon#about to read 4, iclass 30, count 0 2006.197.08:15:20.45#ibcon#read 4, iclass 30, count 0 2006.197.08:15:20.45#ibcon#about to read 5, iclass 30, count 0 2006.197.08:15:20.45#ibcon#read 5, iclass 30, count 0 2006.197.08:15:20.45#ibcon#about to read 6, iclass 30, count 0 2006.197.08:15:20.45#ibcon#read 6, iclass 30, count 0 2006.197.08:15:20.45#ibcon#end of sib2, iclass 30, count 0 2006.197.08:15:20.45#ibcon#*after write, iclass 30, count 0 2006.197.08:15:20.45#ibcon#*before return 0, iclass 30, count 0 2006.197.08:15:20.45#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.197.08:15:20.45#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.197.08:15:20.45#ibcon#about to clear, iclass 30 cls_cnt 0 2006.197.08:15:20.45#ibcon#cleared, iclass 30 cls_cnt 0 2006.197.08:15:20.45$vc4f8/vblo=2,640.99 2006.197.08:15:20.45#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.197.08:15:20.45#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.197.08:15:20.45#ibcon#ireg 17 cls_cnt 0 2006.197.08:15:20.45#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.197.08:15:20.45#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.197.08:15:20.45#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.197.08:15:20.45#ibcon#enter wrdev, iclass 32, count 0 2006.197.08:15:20.45#ibcon#first serial, iclass 32, count 0 2006.197.08:15:20.45#ibcon#enter sib2, iclass 32, count 0 2006.197.08:15:20.45#ibcon#flushed, iclass 32, count 0 2006.197.08:15:20.45#ibcon#about to write, iclass 32, count 0 2006.197.08:15:20.45#ibcon#wrote, iclass 32, count 0 2006.197.08:15:20.45#ibcon#about to read 3, iclass 32, count 0 2006.197.08:15:20.47#ibcon#read 3, iclass 32, count 0 2006.197.08:15:20.47#ibcon#about to read 4, iclass 32, count 0 2006.197.08:15:20.47#ibcon#read 4, iclass 32, count 0 2006.197.08:15:20.47#ibcon#about to read 5, iclass 32, count 0 2006.197.08:15:20.47#ibcon#read 5, iclass 32, count 0 2006.197.08:15:20.47#ibcon#about to read 6, iclass 32, count 0 2006.197.08:15:20.47#ibcon#read 6, iclass 32, count 0 2006.197.08:15:20.47#ibcon#end of sib2, iclass 32, count 0 2006.197.08:15:20.47#ibcon#*mode == 0, iclass 32, count 0 2006.197.08:15:20.47#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.197.08:15:20.47#ibcon#[28=FRQ=02,640.99\r\n] 2006.197.08:15:20.47#ibcon#*before write, iclass 32, count 0 2006.197.08:15:20.47#ibcon#enter sib2, iclass 32, count 0 2006.197.08:15:20.47#ibcon#flushed, iclass 32, count 0 2006.197.08:15:20.47#ibcon#about to write, iclass 32, count 0 2006.197.08:15:20.47#ibcon#wrote, iclass 32, count 0 2006.197.08:15:20.47#ibcon#about to read 3, iclass 32, count 0 2006.197.08:15:20.51#ibcon#read 3, iclass 32, count 0 2006.197.08:15:20.51#ibcon#about to read 4, iclass 32, count 0 2006.197.08:15:20.51#ibcon#read 4, iclass 32, count 0 2006.197.08:15:20.51#ibcon#about to read 5, iclass 32, count 0 2006.197.08:15:20.51#ibcon#read 5, iclass 32, count 0 2006.197.08:15:20.51#ibcon#about to read 6, iclass 32, count 0 2006.197.08:15:20.51#ibcon#read 6, iclass 32, count 0 2006.197.08:15:20.51#ibcon#end of sib2, iclass 32, count 0 2006.197.08:15:20.51#ibcon#*after write, iclass 32, count 0 2006.197.08:15:20.51#ibcon#*before return 0, iclass 32, count 0 2006.197.08:15:20.51#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.197.08:15:20.51#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.197.08:15:20.51#ibcon#about to clear, iclass 32 cls_cnt 0 2006.197.08:15:20.51#ibcon#cleared, iclass 32 cls_cnt 0 2006.197.08:15:20.51$vc4f8/vb=2,4 2006.197.08:15:20.51#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.197.08:15:20.51#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.197.08:15:20.51#ibcon#ireg 11 cls_cnt 2 2006.197.08:15:20.51#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.197.08:15:20.57#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.197.08:15:20.57#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.197.08:15:20.57#ibcon#enter wrdev, iclass 34, count 2 2006.197.08:15:20.57#ibcon#first serial, iclass 34, count 2 2006.197.08:15:20.57#ibcon#enter sib2, iclass 34, count 2 2006.197.08:15:20.57#ibcon#flushed, iclass 34, count 2 2006.197.08:15:20.57#ibcon#about to write, iclass 34, count 2 2006.197.08:15:20.57#ibcon#wrote, iclass 34, count 2 2006.197.08:15:20.57#ibcon#about to read 3, iclass 34, count 2 2006.197.08:15:20.59#ibcon#read 3, iclass 34, count 2 2006.197.08:15:20.59#ibcon#about to read 4, iclass 34, count 2 2006.197.08:15:20.59#ibcon#read 4, iclass 34, count 2 2006.197.08:15:20.59#ibcon#about to read 5, iclass 34, count 2 2006.197.08:15:20.59#ibcon#read 5, iclass 34, count 2 2006.197.08:15:20.59#ibcon#about to read 6, iclass 34, count 2 2006.197.08:15:20.59#ibcon#read 6, iclass 34, count 2 2006.197.08:15:20.59#ibcon#end of sib2, iclass 34, count 2 2006.197.08:15:20.59#ibcon#*mode == 0, iclass 34, count 2 2006.197.08:15:20.59#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.197.08:15:20.59#ibcon#[27=AT02-04\r\n] 2006.197.08:15:20.59#ibcon#*before write, iclass 34, count 2 2006.197.08:15:20.59#ibcon#enter sib2, iclass 34, count 2 2006.197.08:15:20.59#ibcon#flushed, iclass 34, count 2 2006.197.08:15:20.59#ibcon#about to write, iclass 34, count 2 2006.197.08:15:20.59#ibcon#wrote, iclass 34, count 2 2006.197.08:15:20.59#ibcon#about to read 3, iclass 34, count 2 2006.197.08:15:20.62#ibcon#read 3, iclass 34, count 2 2006.197.08:15:20.62#ibcon#about to read 4, iclass 34, count 2 2006.197.08:15:20.62#ibcon#read 4, iclass 34, count 2 2006.197.08:15:20.62#ibcon#about to read 5, iclass 34, count 2 2006.197.08:15:20.62#ibcon#read 5, iclass 34, count 2 2006.197.08:15:20.62#ibcon#about to read 6, iclass 34, count 2 2006.197.08:15:20.62#ibcon#read 6, iclass 34, count 2 2006.197.08:15:20.62#ibcon#end of sib2, iclass 34, count 2 2006.197.08:15:20.62#ibcon#*after write, iclass 34, count 2 2006.197.08:15:20.62#ibcon#*before return 0, iclass 34, count 2 2006.197.08:15:20.62#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.197.08:15:20.62#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.197.08:15:20.62#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.197.08:15:20.62#ibcon#ireg 7 cls_cnt 0 2006.197.08:15:20.62#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.197.08:15:20.74#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.197.08:15:20.74#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.197.08:15:20.74#ibcon#enter wrdev, iclass 34, count 0 2006.197.08:15:20.74#ibcon#first serial, iclass 34, count 0 2006.197.08:15:20.74#ibcon#enter sib2, iclass 34, count 0 2006.197.08:15:20.74#ibcon#flushed, iclass 34, count 0 2006.197.08:15:20.74#ibcon#about to write, iclass 34, count 0 2006.197.08:15:20.74#ibcon#wrote, iclass 34, count 0 2006.197.08:15:20.74#ibcon#about to read 3, iclass 34, count 0 2006.197.08:15:20.76#ibcon#read 3, iclass 34, count 0 2006.197.08:15:20.76#ibcon#about to read 4, iclass 34, count 0 2006.197.08:15:20.76#ibcon#read 4, iclass 34, count 0 2006.197.08:15:20.76#ibcon#about to read 5, iclass 34, count 0 2006.197.08:15:20.76#ibcon#read 5, iclass 34, count 0 2006.197.08:15:20.76#ibcon#about to read 6, iclass 34, count 0 2006.197.08:15:20.76#ibcon#read 6, iclass 34, count 0 2006.197.08:15:20.76#ibcon#end of sib2, iclass 34, count 0 2006.197.08:15:20.76#ibcon#*mode == 0, iclass 34, count 0 2006.197.08:15:20.76#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.197.08:15:20.76#ibcon#[27=USB\r\n] 2006.197.08:15:20.76#ibcon#*before write, iclass 34, count 0 2006.197.08:15:20.76#ibcon#enter sib2, iclass 34, count 0 2006.197.08:15:20.76#ibcon#flushed, iclass 34, count 0 2006.197.08:15:20.76#ibcon#about to write, iclass 34, count 0 2006.197.08:15:20.76#ibcon#wrote, iclass 34, count 0 2006.197.08:15:20.76#ibcon#about to read 3, iclass 34, count 0 2006.197.08:15:20.79#ibcon#read 3, iclass 34, count 0 2006.197.08:15:20.79#ibcon#about to read 4, iclass 34, count 0 2006.197.08:15:20.79#ibcon#read 4, iclass 34, count 0 2006.197.08:15:20.79#ibcon#about to read 5, iclass 34, count 0 2006.197.08:15:20.79#ibcon#read 5, iclass 34, count 0 2006.197.08:15:20.79#ibcon#about to read 6, iclass 34, count 0 2006.197.08:15:20.79#ibcon#read 6, iclass 34, count 0 2006.197.08:15:20.79#ibcon#end of sib2, iclass 34, count 0 2006.197.08:15:20.79#ibcon#*after write, iclass 34, count 0 2006.197.08:15:20.79#ibcon#*before return 0, iclass 34, count 0 2006.197.08:15:20.79#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.197.08:15:20.79#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.197.08:15:20.79#ibcon#about to clear, iclass 34 cls_cnt 0 2006.197.08:15:20.79#ibcon#cleared, iclass 34 cls_cnt 0 2006.197.08:15:20.79$vc4f8/vblo=3,656.99 2006.197.08:15:20.79#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.197.08:15:20.79#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.197.08:15:20.79#ibcon#ireg 17 cls_cnt 0 2006.197.08:15:20.79#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.197.08:15:20.79#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.197.08:15:20.79#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.197.08:15:20.79#ibcon#enter wrdev, iclass 36, count 0 2006.197.08:15:20.79#ibcon#first serial, iclass 36, count 0 2006.197.08:15:20.79#ibcon#enter sib2, iclass 36, count 0 2006.197.08:15:20.79#ibcon#flushed, iclass 36, count 0 2006.197.08:15:20.79#ibcon#about to write, iclass 36, count 0 2006.197.08:15:20.79#ibcon#wrote, iclass 36, count 0 2006.197.08:15:20.79#ibcon#about to read 3, iclass 36, count 0 2006.197.08:15:20.81#ibcon#read 3, iclass 36, count 0 2006.197.08:15:20.81#ibcon#about to read 4, iclass 36, count 0 2006.197.08:15:20.81#ibcon#read 4, iclass 36, count 0 2006.197.08:15:20.81#ibcon#about to read 5, iclass 36, count 0 2006.197.08:15:20.81#ibcon#read 5, iclass 36, count 0 2006.197.08:15:20.81#ibcon#about to read 6, iclass 36, count 0 2006.197.08:15:20.81#ibcon#read 6, iclass 36, count 0 2006.197.08:15:20.81#ibcon#end of sib2, iclass 36, count 0 2006.197.08:15:20.81#ibcon#*mode == 0, iclass 36, count 0 2006.197.08:15:20.81#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.197.08:15:20.81#ibcon#[28=FRQ=03,656.99\r\n] 2006.197.08:15:20.81#ibcon#*before write, iclass 36, count 0 2006.197.08:15:20.81#ibcon#enter sib2, iclass 36, count 0 2006.197.08:15:20.81#ibcon#flushed, iclass 36, count 0 2006.197.08:15:20.81#ibcon#about to write, iclass 36, count 0 2006.197.08:15:20.81#ibcon#wrote, iclass 36, count 0 2006.197.08:15:20.81#ibcon#about to read 3, iclass 36, count 0 2006.197.08:15:20.85#ibcon#read 3, iclass 36, count 0 2006.197.08:15:20.85#ibcon#about to read 4, iclass 36, count 0 2006.197.08:15:20.85#ibcon#read 4, iclass 36, count 0 2006.197.08:15:20.85#ibcon#about to read 5, iclass 36, count 0 2006.197.08:15:20.85#ibcon#read 5, iclass 36, count 0 2006.197.08:15:20.85#ibcon#about to read 6, iclass 36, count 0 2006.197.08:15:20.85#ibcon#read 6, iclass 36, count 0 2006.197.08:15:20.85#ibcon#end of sib2, iclass 36, count 0 2006.197.08:15:20.85#ibcon#*after write, iclass 36, count 0 2006.197.08:15:20.85#ibcon#*before return 0, iclass 36, count 0 2006.197.08:15:20.85#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.197.08:15:20.85#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.197.08:15:20.85#ibcon#about to clear, iclass 36 cls_cnt 0 2006.197.08:15:20.85#ibcon#cleared, iclass 36 cls_cnt 0 2006.197.08:15:20.85$vc4f8/vb=3,4 2006.197.08:15:20.85#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.197.08:15:20.85#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.197.08:15:20.85#ibcon#ireg 11 cls_cnt 2 2006.197.08:15:20.85#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.197.08:15:20.91#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.197.08:15:20.91#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.197.08:15:20.91#ibcon#enter wrdev, iclass 38, count 2 2006.197.08:15:20.91#ibcon#first serial, iclass 38, count 2 2006.197.08:15:20.91#ibcon#enter sib2, iclass 38, count 2 2006.197.08:15:20.91#ibcon#flushed, iclass 38, count 2 2006.197.08:15:20.91#ibcon#about to write, iclass 38, count 2 2006.197.08:15:20.91#ibcon#wrote, iclass 38, count 2 2006.197.08:15:20.91#ibcon#about to read 3, iclass 38, count 2 2006.197.08:15:20.93#ibcon#read 3, iclass 38, count 2 2006.197.08:15:20.93#ibcon#about to read 4, iclass 38, count 2 2006.197.08:15:20.93#ibcon#read 4, iclass 38, count 2 2006.197.08:15:20.93#ibcon#about to read 5, iclass 38, count 2 2006.197.08:15:20.93#ibcon#read 5, iclass 38, count 2 2006.197.08:15:20.93#ibcon#about to read 6, iclass 38, count 2 2006.197.08:15:20.93#ibcon#read 6, iclass 38, count 2 2006.197.08:15:20.93#ibcon#end of sib2, iclass 38, count 2 2006.197.08:15:20.93#ibcon#*mode == 0, iclass 38, count 2 2006.197.08:15:20.93#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.197.08:15:20.93#ibcon#[27=AT03-04\r\n] 2006.197.08:15:20.93#ibcon#*before write, iclass 38, count 2 2006.197.08:15:20.93#ibcon#enter sib2, iclass 38, count 2 2006.197.08:15:20.93#ibcon#flushed, iclass 38, count 2 2006.197.08:15:20.93#ibcon#about to write, iclass 38, count 2 2006.197.08:15:20.93#ibcon#wrote, iclass 38, count 2 2006.197.08:15:20.93#ibcon#about to read 3, iclass 38, count 2 2006.197.08:15:20.96#ibcon#read 3, iclass 38, count 2 2006.197.08:15:20.96#ibcon#about to read 4, iclass 38, count 2 2006.197.08:15:20.96#ibcon#read 4, iclass 38, count 2 2006.197.08:15:20.96#ibcon#about to read 5, iclass 38, count 2 2006.197.08:15:20.96#ibcon#read 5, iclass 38, count 2 2006.197.08:15:20.96#ibcon#about to read 6, iclass 38, count 2 2006.197.08:15:20.96#ibcon#read 6, iclass 38, count 2 2006.197.08:15:20.96#ibcon#end of sib2, iclass 38, count 2 2006.197.08:15:20.96#ibcon#*after write, iclass 38, count 2 2006.197.08:15:20.96#ibcon#*before return 0, iclass 38, count 2 2006.197.08:15:20.96#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.197.08:15:20.96#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.197.08:15:20.96#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.197.08:15:20.96#ibcon#ireg 7 cls_cnt 0 2006.197.08:15:20.96#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.197.08:15:21.08#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.197.08:15:21.08#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.197.08:15:21.08#ibcon#enter wrdev, iclass 38, count 0 2006.197.08:15:21.08#ibcon#first serial, iclass 38, count 0 2006.197.08:15:21.08#ibcon#enter sib2, iclass 38, count 0 2006.197.08:15:21.08#ibcon#flushed, iclass 38, count 0 2006.197.08:15:21.08#ibcon#about to write, iclass 38, count 0 2006.197.08:15:21.08#ibcon#wrote, iclass 38, count 0 2006.197.08:15:21.08#ibcon#about to read 3, iclass 38, count 0 2006.197.08:15:21.10#ibcon#read 3, iclass 38, count 0 2006.197.08:15:21.10#ibcon#about to read 4, iclass 38, count 0 2006.197.08:15:21.10#ibcon#read 4, iclass 38, count 0 2006.197.08:15:21.10#ibcon#about to read 5, iclass 38, count 0 2006.197.08:15:21.10#ibcon#read 5, iclass 38, count 0 2006.197.08:15:21.10#ibcon#about to read 6, iclass 38, count 0 2006.197.08:15:21.10#ibcon#read 6, iclass 38, count 0 2006.197.08:15:21.10#ibcon#end of sib2, iclass 38, count 0 2006.197.08:15:21.10#ibcon#*mode == 0, iclass 38, count 0 2006.197.08:15:21.10#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.197.08:15:21.10#ibcon#[27=USB\r\n] 2006.197.08:15:21.10#ibcon#*before write, iclass 38, count 0 2006.197.08:15:21.10#ibcon#enter sib2, iclass 38, count 0 2006.197.08:15:21.10#ibcon#flushed, iclass 38, count 0 2006.197.08:15:21.10#ibcon#about to write, iclass 38, count 0 2006.197.08:15:21.10#ibcon#wrote, iclass 38, count 0 2006.197.08:15:21.10#ibcon#about to read 3, iclass 38, count 0 2006.197.08:15:21.13#ibcon#read 3, iclass 38, count 0 2006.197.08:15:21.13#ibcon#about to read 4, iclass 38, count 0 2006.197.08:15:21.13#ibcon#read 4, iclass 38, count 0 2006.197.08:15:21.13#ibcon#about to read 5, iclass 38, count 0 2006.197.08:15:21.13#ibcon#read 5, iclass 38, count 0 2006.197.08:15:21.13#ibcon#about to read 6, iclass 38, count 0 2006.197.08:15:21.13#ibcon#read 6, iclass 38, count 0 2006.197.08:15:21.13#ibcon#end of sib2, iclass 38, count 0 2006.197.08:15:21.13#ibcon#*after write, iclass 38, count 0 2006.197.08:15:21.13#ibcon#*before return 0, iclass 38, count 0 2006.197.08:15:21.13#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.197.08:15:21.13#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.197.08:15:21.13#ibcon#about to clear, iclass 38 cls_cnt 0 2006.197.08:15:21.13#ibcon#cleared, iclass 38 cls_cnt 0 2006.197.08:15:21.13$vc4f8/vblo=4,712.99 2006.197.08:15:21.13#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.197.08:15:21.13#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.197.08:15:21.13#ibcon#ireg 17 cls_cnt 0 2006.197.08:15:21.13#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.197.08:15:21.13#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.197.08:15:21.13#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.197.08:15:21.13#ibcon#enter wrdev, iclass 40, count 0 2006.197.08:15:21.13#ibcon#first serial, iclass 40, count 0 2006.197.08:15:21.13#ibcon#enter sib2, iclass 40, count 0 2006.197.08:15:21.13#ibcon#flushed, iclass 40, count 0 2006.197.08:15:21.13#ibcon#about to write, iclass 40, count 0 2006.197.08:15:21.13#ibcon#wrote, iclass 40, count 0 2006.197.08:15:21.13#ibcon#about to read 3, iclass 40, count 0 2006.197.08:15:21.15#ibcon#read 3, iclass 40, count 0 2006.197.08:15:21.15#ibcon#about to read 4, iclass 40, count 0 2006.197.08:15:21.15#ibcon#read 4, iclass 40, count 0 2006.197.08:15:21.15#ibcon#about to read 5, iclass 40, count 0 2006.197.08:15:21.15#ibcon#read 5, iclass 40, count 0 2006.197.08:15:21.15#ibcon#about to read 6, iclass 40, count 0 2006.197.08:15:21.15#ibcon#read 6, iclass 40, count 0 2006.197.08:15:21.15#ibcon#end of sib2, iclass 40, count 0 2006.197.08:15:21.15#ibcon#*mode == 0, iclass 40, count 0 2006.197.08:15:21.15#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.197.08:15:21.15#ibcon#[28=FRQ=04,712.99\r\n] 2006.197.08:15:21.15#ibcon#*before write, iclass 40, count 0 2006.197.08:15:21.15#ibcon#enter sib2, iclass 40, count 0 2006.197.08:15:21.15#ibcon#flushed, iclass 40, count 0 2006.197.08:15:21.15#ibcon#about to write, iclass 40, count 0 2006.197.08:15:21.15#ibcon#wrote, iclass 40, count 0 2006.197.08:15:21.15#ibcon#about to read 3, iclass 40, count 0 2006.197.08:15:21.19#ibcon#read 3, iclass 40, count 0 2006.197.08:15:21.19#ibcon#about to read 4, iclass 40, count 0 2006.197.08:15:21.19#ibcon#read 4, iclass 40, count 0 2006.197.08:15:21.19#ibcon#about to read 5, iclass 40, count 0 2006.197.08:15:21.19#ibcon#read 5, iclass 40, count 0 2006.197.08:15:21.19#ibcon#about to read 6, iclass 40, count 0 2006.197.08:15:21.19#ibcon#read 6, iclass 40, count 0 2006.197.08:15:21.19#ibcon#end of sib2, iclass 40, count 0 2006.197.08:15:21.19#ibcon#*after write, iclass 40, count 0 2006.197.08:15:21.19#ibcon#*before return 0, iclass 40, count 0 2006.197.08:15:21.19#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.197.08:15:21.19#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.197.08:15:21.19#ibcon#about to clear, iclass 40 cls_cnt 0 2006.197.08:15:21.19#ibcon#cleared, iclass 40 cls_cnt 0 2006.197.08:15:21.19$vc4f8/vb=4,4 2006.197.08:15:21.19#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.197.08:15:21.19#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.197.08:15:21.19#ibcon#ireg 11 cls_cnt 2 2006.197.08:15:21.19#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.197.08:15:21.25#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.197.08:15:21.25#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.197.08:15:21.25#ibcon#enter wrdev, iclass 4, count 2 2006.197.08:15:21.25#ibcon#first serial, iclass 4, count 2 2006.197.08:15:21.25#ibcon#enter sib2, iclass 4, count 2 2006.197.08:15:21.25#ibcon#flushed, iclass 4, count 2 2006.197.08:15:21.25#ibcon#about to write, iclass 4, count 2 2006.197.08:15:21.25#ibcon#wrote, iclass 4, count 2 2006.197.08:15:21.25#ibcon#about to read 3, iclass 4, count 2 2006.197.08:15:21.27#ibcon#read 3, iclass 4, count 2 2006.197.08:15:21.27#ibcon#about to read 4, iclass 4, count 2 2006.197.08:15:21.27#ibcon#read 4, iclass 4, count 2 2006.197.08:15:21.27#ibcon#about to read 5, iclass 4, count 2 2006.197.08:15:21.27#ibcon#read 5, iclass 4, count 2 2006.197.08:15:21.27#ibcon#about to read 6, iclass 4, count 2 2006.197.08:15:21.27#ibcon#read 6, iclass 4, count 2 2006.197.08:15:21.27#ibcon#end of sib2, iclass 4, count 2 2006.197.08:15:21.27#ibcon#*mode == 0, iclass 4, count 2 2006.197.08:15:21.27#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.197.08:15:21.27#ibcon#[27=AT04-04\r\n] 2006.197.08:15:21.27#ibcon#*before write, iclass 4, count 2 2006.197.08:15:21.27#ibcon#enter sib2, iclass 4, count 2 2006.197.08:15:21.27#ibcon#flushed, iclass 4, count 2 2006.197.08:15:21.27#ibcon#about to write, iclass 4, count 2 2006.197.08:15:21.27#ibcon#wrote, iclass 4, count 2 2006.197.08:15:21.27#ibcon#about to read 3, iclass 4, count 2 2006.197.08:15:21.30#ibcon#read 3, iclass 4, count 2 2006.197.08:15:21.30#ibcon#about to read 4, iclass 4, count 2 2006.197.08:15:21.30#ibcon#read 4, iclass 4, count 2 2006.197.08:15:21.30#ibcon#about to read 5, iclass 4, count 2 2006.197.08:15:21.30#ibcon#read 5, iclass 4, count 2 2006.197.08:15:21.30#ibcon#about to read 6, iclass 4, count 2 2006.197.08:15:21.30#ibcon#read 6, iclass 4, count 2 2006.197.08:15:21.30#ibcon#end of sib2, iclass 4, count 2 2006.197.08:15:21.30#ibcon#*after write, iclass 4, count 2 2006.197.08:15:21.30#ibcon#*before return 0, iclass 4, count 2 2006.197.08:15:21.30#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.197.08:15:21.30#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.197.08:15:21.30#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.197.08:15:21.30#ibcon#ireg 7 cls_cnt 0 2006.197.08:15:21.30#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.197.08:15:21.42#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.197.08:15:21.42#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.197.08:15:21.42#ibcon#enter wrdev, iclass 4, count 0 2006.197.08:15:21.42#ibcon#first serial, iclass 4, count 0 2006.197.08:15:21.42#ibcon#enter sib2, iclass 4, count 0 2006.197.08:15:21.42#ibcon#flushed, iclass 4, count 0 2006.197.08:15:21.42#ibcon#about to write, iclass 4, count 0 2006.197.08:15:21.42#ibcon#wrote, iclass 4, count 0 2006.197.08:15:21.42#ibcon#about to read 3, iclass 4, count 0 2006.197.08:15:21.44#ibcon#read 3, iclass 4, count 0 2006.197.08:15:21.44#ibcon#about to read 4, iclass 4, count 0 2006.197.08:15:21.44#ibcon#read 4, iclass 4, count 0 2006.197.08:15:21.44#ibcon#about to read 5, iclass 4, count 0 2006.197.08:15:21.44#ibcon#read 5, iclass 4, count 0 2006.197.08:15:21.44#ibcon#about to read 6, iclass 4, count 0 2006.197.08:15:21.44#ibcon#read 6, iclass 4, count 0 2006.197.08:15:21.44#ibcon#end of sib2, iclass 4, count 0 2006.197.08:15:21.44#ibcon#*mode == 0, iclass 4, count 0 2006.197.08:15:21.44#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.197.08:15:21.44#ibcon#[27=USB\r\n] 2006.197.08:15:21.44#ibcon#*before write, iclass 4, count 0 2006.197.08:15:21.44#ibcon#enter sib2, iclass 4, count 0 2006.197.08:15:21.44#ibcon#flushed, iclass 4, count 0 2006.197.08:15:21.44#ibcon#about to write, iclass 4, count 0 2006.197.08:15:21.44#ibcon#wrote, iclass 4, count 0 2006.197.08:15:21.44#ibcon#about to read 3, iclass 4, count 0 2006.197.08:15:21.47#ibcon#read 3, iclass 4, count 0 2006.197.08:15:21.47#ibcon#about to read 4, iclass 4, count 0 2006.197.08:15:21.47#ibcon#read 4, iclass 4, count 0 2006.197.08:15:21.47#ibcon#about to read 5, iclass 4, count 0 2006.197.08:15:21.47#ibcon#read 5, iclass 4, count 0 2006.197.08:15:21.47#ibcon#about to read 6, iclass 4, count 0 2006.197.08:15:21.47#ibcon#read 6, iclass 4, count 0 2006.197.08:15:21.47#ibcon#end of sib2, iclass 4, count 0 2006.197.08:15:21.47#ibcon#*after write, iclass 4, count 0 2006.197.08:15:21.47#ibcon#*before return 0, iclass 4, count 0 2006.197.08:15:21.47#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.197.08:15:21.47#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.197.08:15:21.47#ibcon#about to clear, iclass 4 cls_cnt 0 2006.197.08:15:21.47#ibcon#cleared, iclass 4 cls_cnt 0 2006.197.08:15:21.47$vc4f8/vblo=5,744.99 2006.197.08:15:21.47#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.197.08:15:21.47#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.197.08:15:21.47#ibcon#ireg 17 cls_cnt 0 2006.197.08:15:21.47#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.197.08:15:21.47#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.197.08:15:21.47#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.197.08:15:21.47#ibcon#enter wrdev, iclass 6, count 0 2006.197.08:15:21.47#ibcon#first serial, iclass 6, count 0 2006.197.08:15:21.47#ibcon#enter sib2, iclass 6, count 0 2006.197.08:15:21.47#ibcon#flushed, iclass 6, count 0 2006.197.08:15:21.47#ibcon#about to write, iclass 6, count 0 2006.197.08:15:21.47#ibcon#wrote, iclass 6, count 0 2006.197.08:15:21.47#ibcon#about to read 3, iclass 6, count 0 2006.197.08:15:21.49#ibcon#read 3, iclass 6, count 0 2006.197.08:15:21.49#ibcon#about to read 4, iclass 6, count 0 2006.197.08:15:21.49#ibcon#read 4, iclass 6, count 0 2006.197.08:15:21.49#ibcon#about to read 5, iclass 6, count 0 2006.197.08:15:21.49#ibcon#read 5, iclass 6, count 0 2006.197.08:15:21.49#ibcon#about to read 6, iclass 6, count 0 2006.197.08:15:21.49#ibcon#read 6, iclass 6, count 0 2006.197.08:15:21.49#ibcon#end of sib2, iclass 6, count 0 2006.197.08:15:21.49#ibcon#*mode == 0, iclass 6, count 0 2006.197.08:15:21.49#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.197.08:15:21.49#ibcon#[28=FRQ=05,744.99\r\n] 2006.197.08:15:21.49#ibcon#*before write, iclass 6, count 0 2006.197.08:15:21.49#ibcon#enter sib2, iclass 6, count 0 2006.197.08:15:21.49#ibcon#flushed, iclass 6, count 0 2006.197.08:15:21.49#ibcon#about to write, iclass 6, count 0 2006.197.08:15:21.49#ibcon#wrote, iclass 6, count 0 2006.197.08:15:21.49#ibcon#about to read 3, iclass 6, count 0 2006.197.08:15:21.53#ibcon#read 3, iclass 6, count 0 2006.197.08:15:21.53#ibcon#about to read 4, iclass 6, count 0 2006.197.08:15:21.53#ibcon#read 4, iclass 6, count 0 2006.197.08:15:21.53#ibcon#about to read 5, iclass 6, count 0 2006.197.08:15:21.53#ibcon#read 5, iclass 6, count 0 2006.197.08:15:21.53#ibcon#about to read 6, iclass 6, count 0 2006.197.08:15:21.53#ibcon#read 6, iclass 6, count 0 2006.197.08:15:21.53#ibcon#end of sib2, iclass 6, count 0 2006.197.08:15:21.53#ibcon#*after write, iclass 6, count 0 2006.197.08:15:21.53#ibcon#*before return 0, iclass 6, count 0 2006.197.08:15:21.53#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.197.08:15:21.53#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.197.08:15:21.53#ibcon#about to clear, iclass 6 cls_cnt 0 2006.197.08:15:21.53#ibcon#cleared, iclass 6 cls_cnt 0 2006.197.08:15:21.53$vc4f8/vb=5,4 2006.197.08:15:21.53#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.197.08:15:21.53#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.197.08:15:21.53#ibcon#ireg 11 cls_cnt 2 2006.197.08:15:21.53#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.197.08:15:21.59#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.197.08:15:21.59#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.197.08:15:21.59#ibcon#enter wrdev, iclass 10, count 2 2006.197.08:15:21.59#ibcon#first serial, iclass 10, count 2 2006.197.08:15:21.59#ibcon#enter sib2, iclass 10, count 2 2006.197.08:15:21.59#ibcon#flushed, iclass 10, count 2 2006.197.08:15:21.59#ibcon#about to write, iclass 10, count 2 2006.197.08:15:21.59#ibcon#wrote, iclass 10, count 2 2006.197.08:15:21.59#ibcon#about to read 3, iclass 10, count 2 2006.197.08:15:21.61#ibcon#read 3, iclass 10, count 2 2006.197.08:15:21.61#ibcon#about to read 4, iclass 10, count 2 2006.197.08:15:21.61#ibcon#read 4, iclass 10, count 2 2006.197.08:15:21.61#ibcon#about to read 5, iclass 10, count 2 2006.197.08:15:21.61#ibcon#read 5, iclass 10, count 2 2006.197.08:15:21.61#ibcon#about to read 6, iclass 10, count 2 2006.197.08:15:21.61#ibcon#read 6, iclass 10, count 2 2006.197.08:15:21.61#ibcon#end of sib2, iclass 10, count 2 2006.197.08:15:21.61#ibcon#*mode == 0, iclass 10, count 2 2006.197.08:15:21.61#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.197.08:15:21.61#ibcon#[27=AT05-04\r\n] 2006.197.08:15:21.61#ibcon#*before write, iclass 10, count 2 2006.197.08:15:21.61#ibcon#enter sib2, iclass 10, count 2 2006.197.08:15:21.61#ibcon#flushed, iclass 10, count 2 2006.197.08:15:21.61#ibcon#about to write, iclass 10, count 2 2006.197.08:15:21.61#ibcon#wrote, iclass 10, count 2 2006.197.08:15:21.61#ibcon#about to read 3, iclass 10, count 2 2006.197.08:15:21.64#ibcon#read 3, iclass 10, count 2 2006.197.08:15:21.64#ibcon#about to read 4, iclass 10, count 2 2006.197.08:15:21.64#ibcon#read 4, iclass 10, count 2 2006.197.08:15:21.64#ibcon#about to read 5, iclass 10, count 2 2006.197.08:15:21.64#ibcon#read 5, iclass 10, count 2 2006.197.08:15:21.64#ibcon#about to read 6, iclass 10, count 2 2006.197.08:15:21.64#ibcon#read 6, iclass 10, count 2 2006.197.08:15:21.64#ibcon#end of sib2, iclass 10, count 2 2006.197.08:15:21.64#ibcon#*after write, iclass 10, count 2 2006.197.08:15:21.64#ibcon#*before return 0, iclass 10, count 2 2006.197.08:15:21.64#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.197.08:15:21.64#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.197.08:15:21.64#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.197.08:15:21.64#ibcon#ireg 7 cls_cnt 0 2006.197.08:15:21.64#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.197.08:15:21.76#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.197.08:15:21.76#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.197.08:15:21.76#ibcon#enter wrdev, iclass 10, count 0 2006.197.08:15:21.76#ibcon#first serial, iclass 10, count 0 2006.197.08:15:21.76#ibcon#enter sib2, iclass 10, count 0 2006.197.08:15:21.76#ibcon#flushed, iclass 10, count 0 2006.197.08:15:21.76#ibcon#about to write, iclass 10, count 0 2006.197.08:15:21.76#ibcon#wrote, iclass 10, count 0 2006.197.08:15:21.76#ibcon#about to read 3, iclass 10, count 0 2006.197.08:15:21.78#ibcon#read 3, iclass 10, count 0 2006.197.08:15:21.78#ibcon#about to read 4, iclass 10, count 0 2006.197.08:15:21.78#ibcon#read 4, iclass 10, count 0 2006.197.08:15:21.78#ibcon#about to read 5, iclass 10, count 0 2006.197.08:15:21.78#ibcon#read 5, iclass 10, count 0 2006.197.08:15:21.78#ibcon#about to read 6, iclass 10, count 0 2006.197.08:15:21.78#ibcon#read 6, iclass 10, count 0 2006.197.08:15:21.78#ibcon#end of sib2, iclass 10, count 0 2006.197.08:15:21.78#ibcon#*mode == 0, iclass 10, count 0 2006.197.08:15:21.78#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.197.08:15:21.78#ibcon#[27=USB\r\n] 2006.197.08:15:21.78#ibcon#*before write, iclass 10, count 0 2006.197.08:15:21.78#ibcon#enter sib2, iclass 10, count 0 2006.197.08:15:21.78#ibcon#flushed, iclass 10, count 0 2006.197.08:15:21.78#ibcon#about to write, iclass 10, count 0 2006.197.08:15:21.78#ibcon#wrote, iclass 10, count 0 2006.197.08:15:21.78#ibcon#about to read 3, iclass 10, count 0 2006.197.08:15:21.81#ibcon#read 3, iclass 10, count 0 2006.197.08:15:21.81#ibcon#about to read 4, iclass 10, count 0 2006.197.08:15:21.81#ibcon#read 4, iclass 10, count 0 2006.197.08:15:21.81#ibcon#about to read 5, iclass 10, count 0 2006.197.08:15:21.81#ibcon#read 5, iclass 10, count 0 2006.197.08:15:21.81#ibcon#about to read 6, iclass 10, count 0 2006.197.08:15:21.81#ibcon#read 6, iclass 10, count 0 2006.197.08:15:21.81#ibcon#end of sib2, iclass 10, count 0 2006.197.08:15:21.81#ibcon#*after write, iclass 10, count 0 2006.197.08:15:21.81#ibcon#*before return 0, iclass 10, count 0 2006.197.08:15:21.81#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.197.08:15:21.81#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.197.08:15:21.81#ibcon#about to clear, iclass 10 cls_cnt 0 2006.197.08:15:21.81#ibcon#cleared, iclass 10 cls_cnt 0 2006.197.08:15:21.81$vc4f8/vblo=6,752.99 2006.197.08:15:21.81#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.197.08:15:21.81#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.197.08:15:21.81#ibcon#ireg 17 cls_cnt 0 2006.197.08:15:21.81#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.197.08:15:21.81#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.197.08:15:21.81#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.197.08:15:21.81#ibcon#enter wrdev, iclass 12, count 0 2006.197.08:15:21.81#ibcon#first serial, iclass 12, count 0 2006.197.08:15:21.81#ibcon#enter sib2, iclass 12, count 0 2006.197.08:15:21.81#ibcon#flushed, iclass 12, count 0 2006.197.08:15:21.81#ibcon#about to write, iclass 12, count 0 2006.197.08:15:21.81#ibcon#wrote, iclass 12, count 0 2006.197.08:15:21.81#ibcon#about to read 3, iclass 12, count 0 2006.197.08:15:21.83#ibcon#read 3, iclass 12, count 0 2006.197.08:15:21.83#ibcon#about to read 4, iclass 12, count 0 2006.197.08:15:21.83#ibcon#read 4, iclass 12, count 0 2006.197.08:15:21.83#ibcon#about to read 5, iclass 12, count 0 2006.197.08:15:21.83#ibcon#read 5, iclass 12, count 0 2006.197.08:15:21.83#ibcon#about to read 6, iclass 12, count 0 2006.197.08:15:21.83#ibcon#read 6, iclass 12, count 0 2006.197.08:15:21.83#ibcon#end of sib2, iclass 12, count 0 2006.197.08:15:21.83#ibcon#*mode == 0, iclass 12, count 0 2006.197.08:15:21.83#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.197.08:15:21.83#ibcon#[28=FRQ=06,752.99\r\n] 2006.197.08:15:21.83#ibcon#*before write, iclass 12, count 0 2006.197.08:15:21.83#ibcon#enter sib2, iclass 12, count 0 2006.197.08:15:21.83#ibcon#flushed, iclass 12, count 0 2006.197.08:15:21.83#ibcon#about to write, iclass 12, count 0 2006.197.08:15:21.83#ibcon#wrote, iclass 12, count 0 2006.197.08:15:21.83#ibcon#about to read 3, iclass 12, count 0 2006.197.08:15:21.87#ibcon#read 3, iclass 12, count 0 2006.197.08:15:21.87#ibcon#about to read 4, iclass 12, count 0 2006.197.08:15:21.87#ibcon#read 4, iclass 12, count 0 2006.197.08:15:21.87#ibcon#about to read 5, iclass 12, count 0 2006.197.08:15:21.87#ibcon#read 5, iclass 12, count 0 2006.197.08:15:21.87#ibcon#about to read 6, iclass 12, count 0 2006.197.08:15:21.87#ibcon#read 6, iclass 12, count 0 2006.197.08:15:21.87#ibcon#end of sib2, iclass 12, count 0 2006.197.08:15:21.87#ibcon#*after write, iclass 12, count 0 2006.197.08:15:21.87#ibcon#*before return 0, iclass 12, count 0 2006.197.08:15:21.87#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.197.08:15:21.87#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.197.08:15:21.87#ibcon#about to clear, iclass 12 cls_cnt 0 2006.197.08:15:21.87#ibcon#cleared, iclass 12 cls_cnt 0 2006.197.08:15:21.87$vc4f8/vb=6,4 2006.197.08:15:21.87#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.197.08:15:21.87#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.197.08:15:21.87#ibcon#ireg 11 cls_cnt 2 2006.197.08:15:21.87#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.197.08:15:21.93#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.197.08:15:21.93#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.197.08:15:21.93#ibcon#enter wrdev, iclass 14, count 2 2006.197.08:15:21.93#ibcon#first serial, iclass 14, count 2 2006.197.08:15:21.93#ibcon#enter sib2, iclass 14, count 2 2006.197.08:15:21.93#ibcon#flushed, iclass 14, count 2 2006.197.08:15:21.93#ibcon#about to write, iclass 14, count 2 2006.197.08:15:21.93#ibcon#wrote, iclass 14, count 2 2006.197.08:15:21.93#ibcon#about to read 3, iclass 14, count 2 2006.197.08:15:21.95#ibcon#read 3, iclass 14, count 2 2006.197.08:15:21.95#ibcon#about to read 4, iclass 14, count 2 2006.197.08:15:21.95#ibcon#read 4, iclass 14, count 2 2006.197.08:15:21.95#ibcon#about to read 5, iclass 14, count 2 2006.197.08:15:21.95#ibcon#read 5, iclass 14, count 2 2006.197.08:15:21.95#ibcon#about to read 6, iclass 14, count 2 2006.197.08:15:21.95#ibcon#read 6, iclass 14, count 2 2006.197.08:15:21.95#ibcon#end of sib2, iclass 14, count 2 2006.197.08:15:21.95#ibcon#*mode == 0, iclass 14, count 2 2006.197.08:15:21.95#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.197.08:15:21.95#ibcon#[27=AT06-04\r\n] 2006.197.08:15:21.95#ibcon#*before write, iclass 14, count 2 2006.197.08:15:21.95#ibcon#enter sib2, iclass 14, count 2 2006.197.08:15:21.95#ibcon#flushed, iclass 14, count 2 2006.197.08:15:21.95#ibcon#about to write, iclass 14, count 2 2006.197.08:15:21.95#ibcon#wrote, iclass 14, count 2 2006.197.08:15:21.95#ibcon#about to read 3, iclass 14, count 2 2006.197.08:15:21.98#ibcon#read 3, iclass 14, count 2 2006.197.08:15:21.98#ibcon#about to read 4, iclass 14, count 2 2006.197.08:15:21.98#ibcon#read 4, iclass 14, count 2 2006.197.08:15:21.98#ibcon#about to read 5, iclass 14, count 2 2006.197.08:15:21.98#ibcon#read 5, iclass 14, count 2 2006.197.08:15:21.98#ibcon#about to read 6, iclass 14, count 2 2006.197.08:15:21.98#ibcon#read 6, iclass 14, count 2 2006.197.08:15:21.98#ibcon#end of sib2, iclass 14, count 2 2006.197.08:15:21.98#ibcon#*after write, iclass 14, count 2 2006.197.08:15:21.98#ibcon#*before return 0, iclass 14, count 2 2006.197.08:15:21.98#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.197.08:15:21.98#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.197.08:15:21.98#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.197.08:15:21.98#ibcon#ireg 7 cls_cnt 0 2006.197.08:15:21.98#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.197.08:15:22.10#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.197.08:15:22.10#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.197.08:15:22.10#ibcon#enter wrdev, iclass 14, count 0 2006.197.08:15:22.10#ibcon#first serial, iclass 14, count 0 2006.197.08:15:22.10#ibcon#enter sib2, iclass 14, count 0 2006.197.08:15:22.10#ibcon#flushed, iclass 14, count 0 2006.197.08:15:22.10#ibcon#about to write, iclass 14, count 0 2006.197.08:15:22.10#ibcon#wrote, iclass 14, count 0 2006.197.08:15:22.10#ibcon#about to read 3, iclass 14, count 0 2006.197.08:15:22.12#ibcon#read 3, iclass 14, count 0 2006.197.08:15:22.12#ibcon#about to read 4, iclass 14, count 0 2006.197.08:15:22.12#ibcon#read 4, iclass 14, count 0 2006.197.08:15:22.12#ibcon#about to read 5, iclass 14, count 0 2006.197.08:15:22.12#ibcon#read 5, iclass 14, count 0 2006.197.08:15:22.12#ibcon#about to read 6, iclass 14, count 0 2006.197.08:15:22.12#ibcon#read 6, iclass 14, count 0 2006.197.08:15:22.12#ibcon#end of sib2, iclass 14, count 0 2006.197.08:15:22.12#ibcon#*mode == 0, iclass 14, count 0 2006.197.08:15:22.12#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.197.08:15:22.12#ibcon#[27=USB\r\n] 2006.197.08:15:22.12#ibcon#*before write, iclass 14, count 0 2006.197.08:15:22.12#ibcon#enter sib2, iclass 14, count 0 2006.197.08:15:22.12#ibcon#flushed, iclass 14, count 0 2006.197.08:15:22.12#ibcon#about to write, iclass 14, count 0 2006.197.08:15:22.12#ibcon#wrote, iclass 14, count 0 2006.197.08:15:22.12#ibcon#about to read 3, iclass 14, count 0 2006.197.08:15:22.15#ibcon#read 3, iclass 14, count 0 2006.197.08:15:22.15#ibcon#about to read 4, iclass 14, count 0 2006.197.08:15:22.15#ibcon#read 4, iclass 14, count 0 2006.197.08:15:22.15#ibcon#about to read 5, iclass 14, count 0 2006.197.08:15:22.15#ibcon#read 5, iclass 14, count 0 2006.197.08:15:22.15#ibcon#about to read 6, iclass 14, count 0 2006.197.08:15:22.15#ibcon#read 6, iclass 14, count 0 2006.197.08:15:22.15#ibcon#end of sib2, iclass 14, count 0 2006.197.08:15:22.15#ibcon#*after write, iclass 14, count 0 2006.197.08:15:22.15#ibcon#*before return 0, iclass 14, count 0 2006.197.08:15:22.15#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.197.08:15:22.15#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.197.08:15:22.15#ibcon#about to clear, iclass 14 cls_cnt 0 2006.197.08:15:22.15#ibcon#cleared, iclass 14 cls_cnt 0 2006.197.08:15:22.15$vc4f8/vabw=wide 2006.197.08:15:22.15#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.197.08:15:22.15#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.197.08:15:22.15#ibcon#ireg 8 cls_cnt 0 2006.197.08:15:22.15#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.197.08:15:22.15#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.197.08:15:22.15#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.197.08:15:22.15#ibcon#enter wrdev, iclass 16, count 0 2006.197.08:15:22.15#ibcon#first serial, iclass 16, count 0 2006.197.08:15:22.15#ibcon#enter sib2, iclass 16, count 0 2006.197.08:15:22.15#ibcon#flushed, iclass 16, count 0 2006.197.08:15:22.15#ibcon#about to write, iclass 16, count 0 2006.197.08:15:22.15#ibcon#wrote, iclass 16, count 0 2006.197.08:15:22.15#ibcon#about to read 3, iclass 16, count 0 2006.197.08:15:22.17#ibcon#read 3, iclass 16, count 0 2006.197.08:15:22.17#ibcon#about to read 4, iclass 16, count 0 2006.197.08:15:22.17#ibcon#read 4, iclass 16, count 0 2006.197.08:15:22.17#ibcon#about to read 5, iclass 16, count 0 2006.197.08:15:22.17#ibcon#read 5, iclass 16, count 0 2006.197.08:15:22.17#ibcon#about to read 6, iclass 16, count 0 2006.197.08:15:22.17#ibcon#read 6, iclass 16, count 0 2006.197.08:15:22.17#ibcon#end of sib2, iclass 16, count 0 2006.197.08:15:22.17#ibcon#*mode == 0, iclass 16, count 0 2006.197.08:15:22.17#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.197.08:15:22.17#ibcon#[25=BW32\r\n] 2006.197.08:15:22.17#ibcon#*before write, iclass 16, count 0 2006.197.08:15:22.17#ibcon#enter sib2, iclass 16, count 0 2006.197.08:15:22.17#ibcon#flushed, iclass 16, count 0 2006.197.08:15:22.17#ibcon#about to write, iclass 16, count 0 2006.197.08:15:22.17#ibcon#wrote, iclass 16, count 0 2006.197.08:15:22.17#ibcon#about to read 3, iclass 16, count 0 2006.197.08:15:22.20#ibcon#read 3, iclass 16, count 0 2006.197.08:15:22.20#ibcon#about to read 4, iclass 16, count 0 2006.197.08:15:22.20#ibcon#read 4, iclass 16, count 0 2006.197.08:15:22.20#ibcon#about to read 5, iclass 16, count 0 2006.197.08:15:22.20#ibcon#read 5, iclass 16, count 0 2006.197.08:15:22.20#ibcon#about to read 6, iclass 16, count 0 2006.197.08:15:22.20#ibcon#read 6, iclass 16, count 0 2006.197.08:15:22.20#ibcon#end of sib2, iclass 16, count 0 2006.197.08:15:22.20#ibcon#*after write, iclass 16, count 0 2006.197.08:15:22.20#ibcon#*before return 0, iclass 16, count 0 2006.197.08:15:22.20#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.197.08:15:22.20#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.197.08:15:22.20#ibcon#about to clear, iclass 16 cls_cnt 0 2006.197.08:15:22.20#ibcon#cleared, iclass 16 cls_cnt 0 2006.197.08:15:22.20$vc4f8/vbbw=wide 2006.197.08:15:22.20#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.197.08:15:22.20#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.197.08:15:22.20#ibcon#ireg 8 cls_cnt 0 2006.197.08:15:22.20#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.197.08:15:22.27#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.197.08:15:22.27#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.197.08:15:22.27#ibcon#enter wrdev, iclass 18, count 0 2006.197.08:15:22.27#ibcon#first serial, iclass 18, count 0 2006.197.08:15:22.27#ibcon#enter sib2, iclass 18, count 0 2006.197.08:15:22.27#ibcon#flushed, iclass 18, count 0 2006.197.08:15:22.27#ibcon#about to write, iclass 18, count 0 2006.197.08:15:22.27#ibcon#wrote, iclass 18, count 0 2006.197.08:15:22.27#ibcon#about to read 3, iclass 18, count 0 2006.197.08:15:22.29#ibcon#read 3, iclass 18, count 0 2006.197.08:15:22.29#ibcon#about to read 4, iclass 18, count 0 2006.197.08:15:22.29#ibcon#read 4, iclass 18, count 0 2006.197.08:15:22.29#ibcon#about to read 5, iclass 18, count 0 2006.197.08:15:22.29#ibcon#read 5, iclass 18, count 0 2006.197.08:15:22.29#ibcon#about to read 6, iclass 18, count 0 2006.197.08:15:22.29#ibcon#read 6, iclass 18, count 0 2006.197.08:15:22.29#ibcon#end of sib2, iclass 18, count 0 2006.197.08:15:22.29#ibcon#*mode == 0, iclass 18, count 0 2006.197.08:15:22.29#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.197.08:15:22.29#ibcon#[27=BW32\r\n] 2006.197.08:15:22.29#ibcon#*before write, iclass 18, count 0 2006.197.08:15:22.29#ibcon#enter sib2, iclass 18, count 0 2006.197.08:15:22.29#ibcon#flushed, iclass 18, count 0 2006.197.08:15:22.29#ibcon#about to write, iclass 18, count 0 2006.197.08:15:22.29#ibcon#wrote, iclass 18, count 0 2006.197.08:15:22.29#ibcon#about to read 3, iclass 18, count 0 2006.197.08:15:22.32#ibcon#read 3, iclass 18, count 0 2006.197.08:15:22.32#ibcon#about to read 4, iclass 18, count 0 2006.197.08:15:22.32#ibcon#read 4, iclass 18, count 0 2006.197.08:15:22.32#ibcon#about to read 5, iclass 18, count 0 2006.197.08:15:22.32#ibcon#read 5, iclass 18, count 0 2006.197.08:15:22.32#ibcon#about to read 6, iclass 18, count 0 2006.197.08:15:22.32#ibcon#read 6, iclass 18, count 0 2006.197.08:15:22.32#ibcon#end of sib2, iclass 18, count 0 2006.197.08:15:22.32#ibcon#*after write, iclass 18, count 0 2006.197.08:15:22.32#ibcon#*before return 0, iclass 18, count 0 2006.197.08:15:22.32#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.197.08:15:22.32#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.197.08:15:22.32#ibcon#about to clear, iclass 18 cls_cnt 0 2006.197.08:15:22.32#ibcon#cleared, iclass 18 cls_cnt 0 2006.197.08:15:22.32$4f8m12a/ifd4f 2006.197.08:15:22.32$ifd4f/lo= 2006.197.08:15:22.32$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.197.08:15:22.32$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.197.08:15:22.32$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.197.08:15:22.32$ifd4f/patch= 2006.197.08:15:22.32$ifd4f/patch=lo1,a1,a2,a3,a4 2006.197.08:15:22.32$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.197.08:15:22.32$ifd4f/patch=lo3,a5,a6,a7,a8 2006.197.08:15:22.32$4f8m12a/"form=m,16.000,1:2 2006.197.08:15:22.32$4f8m12a/"tpicd 2006.197.08:15:22.32$4f8m12a/echo=off 2006.197.08:15:22.32$4f8m12a/xlog=off 2006.197.08:15:22.32:!2006.197.08:15:50 2006.197.08:15:32.14#trakl#Source acquired 2006.197.08:15:32.14#flagr#flagr/antenna,acquired 2006.197.08:15:50.00:preob 2006.197.08:15:51.14/onsource/TRACKING 2006.197.08:15:51.14:!2006.197.08:16:00 2006.197.08:16:00.00:data_valid=on 2006.197.08:16:00.00:midob 2006.197.08:16:00.14/onsource/TRACKING 2006.197.08:16:00.14/wx/25.58,1002.7,96 2006.197.08:16:00.23/cable/+6.3728E-03 2006.197.08:16:01.32/va/01,08,usb,yes,29,31 2006.197.08:16:01.32/va/02,07,usb,yes,30,31 2006.197.08:16:01.32/va/03,06,usb,yes,31,31 2006.197.08:16:01.32/va/04,07,usb,yes,30,33 2006.197.08:16:01.32/va/05,07,usb,yes,34,36 2006.197.08:16:01.32/va/06,06,usb,yes,33,33 2006.197.08:16:01.32/va/07,06,usb,yes,34,34 2006.197.08:16:01.32/va/08,07,usb,yes,32,31 2006.197.08:16:01.55/valo/01,532.99,yes,locked 2006.197.08:16:01.55/valo/02,572.99,yes,locked 2006.197.08:16:01.55/valo/03,672.99,yes,locked 2006.197.08:16:01.55/valo/04,832.99,yes,locked 2006.197.08:16:01.55/valo/05,652.99,yes,locked 2006.197.08:16:01.55/valo/06,772.99,yes,locked 2006.197.08:16:01.55/valo/07,832.99,yes,locked 2006.197.08:16:01.55/valo/08,852.99,yes,locked 2006.197.08:16:02.64/vb/01,04,usb,yes,29,28 2006.197.08:16:02.64/vb/02,04,usb,yes,31,32 2006.197.08:16:02.64/vb/03,04,usb,yes,27,31 2006.197.08:16:02.64/vb/04,04,usb,yes,28,28 2006.197.08:16:02.64/vb/05,04,usb,yes,26,30 2006.197.08:16:02.64/vb/06,04,usb,yes,27,30 2006.197.08:16:02.64/vb/07,04,usb,yes,29,29 2006.197.08:16:02.64/vb/08,04,usb,yes,27,30 2006.197.08:16:02.88/vblo/01,632.99,yes,locked 2006.197.08:16:02.88/vblo/02,640.99,yes,locked 2006.197.08:16:02.88/vblo/03,656.99,yes,locked 2006.197.08:16:02.88/vblo/04,712.99,yes,locked 2006.197.08:16:02.88/vblo/05,744.99,yes,locked 2006.197.08:16:02.88/vblo/06,752.99,yes,locked 2006.197.08:16:02.88/vblo/07,734.99,yes,locked 2006.197.08:16:02.88/vblo/08,744.99,yes,locked 2006.197.08:16:03.03/vabw/8 2006.197.08:16:03.18/vbbw/8 2006.197.08:16:03.27/xfe/off,on,15.5 2006.197.08:16:03.64/ifatt/23,28,28,28 2006.197.08:16:04.10/fmout-gps/S +2.99E-07 2006.197.08:16:04.14:!2006.197.08:17:00 2006.197.08:17:00.00:data_valid=off 2006.197.08:17:00.00:postob 2006.197.08:17:00.10/cable/+6.3737E-03 2006.197.08:17:00.10/wx/25.57,1002.7,96 2006.197.08:17:01.10/fmout-gps/S +3.00E-07 2006.197.08:17:01.10:scan_name=197-0817,k06197,60 2006.197.08:17:01.10:source=0804+499,080839.67,495036.5,2000.0,ccw 2006.197.08:17:01.14#flagr#flagr/antenna,new-source 2006.197.08:17:02.14:checkk5 2006.197.08:17:02.47/chk_autoobs//k5ts1/ autoobs is running! 2006.197.08:17:02.81/chk_autoobs//k5ts2/ autoobs is running! 2006.197.08:17:03.15/chk_autoobs//k5ts3/ autoobs is running! 2006.197.08:17:03.49/chk_autoobs//k5ts4/ autoobs is running! 2006.197.08:17:03.84/chk_obsdata//k5ts1/T1970816??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.197.08:17:04.17/chk_obsdata//k5ts2/T1970816??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.197.08:17:04.51/chk_obsdata//k5ts3/T1970816??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.197.08:17:04.85/chk_obsdata//k5ts4/T1970816??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.197.08:17:05.52/k5log//k5ts1_log_newline 2006.197.08:17:06.18/k5log//k5ts2_log_newline 2006.197.08:17:06.86/k5log//k5ts3_log_newline 2006.197.08:17:07.53/k5log//k5ts4_log_newline 2006.197.08:17:07.55/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.197.08:17:07.55:4f8m12a=2 2006.197.08:17:07.55$4f8m12a/echo=on 2006.197.08:17:07.55$4f8m12a/pcalon 2006.197.08:17:07.55$pcalon/"no phase cal control is implemented here 2006.197.08:17:07.55$4f8m12a/"tpicd=stop 2006.197.08:17:07.55$4f8m12a/vc4f8 2006.197.08:17:07.55$vc4f8/valo=1,532.99 2006.197.08:17:07.56#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.197.08:17:07.56#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.197.08:17:07.56#ibcon#ireg 17 cls_cnt 0 2006.197.08:17:07.56#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.197.08:17:07.56#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.197.08:17:07.56#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.197.08:17:07.56#ibcon#enter wrdev, iclass 25, count 0 2006.197.08:17:07.56#ibcon#first serial, iclass 25, count 0 2006.197.08:17:07.56#ibcon#enter sib2, iclass 25, count 0 2006.197.08:17:07.56#ibcon#flushed, iclass 25, count 0 2006.197.08:17:07.56#ibcon#about to write, iclass 25, count 0 2006.197.08:17:07.56#ibcon#wrote, iclass 25, count 0 2006.197.08:17:07.56#ibcon#about to read 3, iclass 25, count 0 2006.197.08:17:07.58#ibcon#read 3, iclass 25, count 0 2006.197.08:17:07.58#ibcon#about to read 4, iclass 25, count 0 2006.197.08:17:07.58#ibcon#read 4, iclass 25, count 0 2006.197.08:17:07.58#ibcon#about to read 5, iclass 25, count 0 2006.197.08:17:07.58#ibcon#read 5, iclass 25, count 0 2006.197.08:17:07.58#ibcon#about to read 6, iclass 25, count 0 2006.197.08:17:07.58#ibcon#read 6, iclass 25, count 0 2006.197.08:17:07.58#ibcon#end of sib2, iclass 25, count 0 2006.197.08:17:07.58#ibcon#*mode == 0, iclass 25, count 0 2006.197.08:17:07.58#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.197.08:17:07.58#ibcon#[26=FRQ=01,532.99\r\n] 2006.197.08:17:07.58#ibcon#*before write, iclass 25, count 0 2006.197.08:17:07.58#ibcon#enter sib2, iclass 25, count 0 2006.197.08:17:07.58#ibcon#flushed, iclass 25, count 0 2006.197.08:17:07.58#ibcon#about to write, iclass 25, count 0 2006.197.08:17:07.58#ibcon#wrote, iclass 25, count 0 2006.197.08:17:07.58#ibcon#about to read 3, iclass 25, count 0 2006.197.08:17:07.63#ibcon#read 3, iclass 25, count 0 2006.197.08:17:07.63#ibcon#about to read 4, iclass 25, count 0 2006.197.08:17:07.63#ibcon#read 4, iclass 25, count 0 2006.197.08:17:07.63#ibcon#about to read 5, iclass 25, count 0 2006.197.08:17:07.63#ibcon#read 5, iclass 25, count 0 2006.197.08:17:07.63#ibcon#about to read 6, iclass 25, count 0 2006.197.08:17:07.63#ibcon#read 6, iclass 25, count 0 2006.197.08:17:07.63#ibcon#end of sib2, iclass 25, count 0 2006.197.08:17:07.63#ibcon#*after write, iclass 25, count 0 2006.197.08:17:07.63#ibcon#*before return 0, iclass 25, count 0 2006.197.08:17:07.63#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.197.08:17:07.63#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.197.08:17:07.63#ibcon#about to clear, iclass 25 cls_cnt 0 2006.197.08:17:07.63#ibcon#cleared, iclass 25 cls_cnt 0 2006.197.08:17:07.63$vc4f8/va=1,8 2006.197.08:17:07.63#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.197.08:17:07.63#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.197.08:17:07.63#ibcon#ireg 11 cls_cnt 2 2006.197.08:17:07.63#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.197.08:17:07.63#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.197.08:17:07.63#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.197.08:17:07.63#ibcon#enter wrdev, iclass 27, count 2 2006.197.08:17:07.63#ibcon#first serial, iclass 27, count 2 2006.197.08:17:07.63#ibcon#enter sib2, iclass 27, count 2 2006.197.08:17:07.63#ibcon#flushed, iclass 27, count 2 2006.197.08:17:07.63#ibcon#about to write, iclass 27, count 2 2006.197.08:17:07.63#ibcon#wrote, iclass 27, count 2 2006.197.08:17:07.63#ibcon#about to read 3, iclass 27, count 2 2006.197.08:17:07.65#ibcon#read 3, iclass 27, count 2 2006.197.08:17:07.65#ibcon#about to read 4, iclass 27, count 2 2006.197.08:17:07.65#ibcon#read 4, iclass 27, count 2 2006.197.08:17:07.65#ibcon#about to read 5, iclass 27, count 2 2006.197.08:17:07.65#ibcon#read 5, iclass 27, count 2 2006.197.08:17:07.65#ibcon#about to read 6, iclass 27, count 2 2006.197.08:17:07.65#ibcon#read 6, iclass 27, count 2 2006.197.08:17:07.65#ibcon#end of sib2, iclass 27, count 2 2006.197.08:17:07.65#ibcon#*mode == 0, iclass 27, count 2 2006.197.08:17:07.65#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.197.08:17:07.65#ibcon#[25=AT01-08\r\n] 2006.197.08:17:07.65#ibcon#*before write, iclass 27, count 2 2006.197.08:17:07.65#ibcon#enter sib2, iclass 27, count 2 2006.197.08:17:07.65#ibcon#flushed, iclass 27, count 2 2006.197.08:17:07.65#ibcon#about to write, iclass 27, count 2 2006.197.08:17:07.65#ibcon#wrote, iclass 27, count 2 2006.197.08:17:07.65#ibcon#about to read 3, iclass 27, count 2 2006.197.08:17:07.68#ibcon#read 3, iclass 27, count 2 2006.197.08:17:07.68#ibcon#about to read 4, iclass 27, count 2 2006.197.08:17:07.68#ibcon#read 4, iclass 27, count 2 2006.197.08:17:07.68#ibcon#about to read 5, iclass 27, count 2 2006.197.08:17:07.68#ibcon#read 5, iclass 27, count 2 2006.197.08:17:07.68#ibcon#about to read 6, iclass 27, count 2 2006.197.08:17:07.68#ibcon#read 6, iclass 27, count 2 2006.197.08:17:07.68#ibcon#end of sib2, iclass 27, count 2 2006.197.08:17:07.68#ibcon#*after write, iclass 27, count 2 2006.197.08:17:07.68#ibcon#*before return 0, iclass 27, count 2 2006.197.08:17:07.68#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.197.08:17:07.68#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.197.08:17:07.68#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.197.08:17:07.68#ibcon#ireg 7 cls_cnt 0 2006.197.08:17:07.68#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.197.08:17:07.80#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.197.08:17:07.80#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.197.08:17:07.80#ibcon#enter wrdev, iclass 27, count 0 2006.197.08:17:07.80#ibcon#first serial, iclass 27, count 0 2006.197.08:17:07.80#ibcon#enter sib2, iclass 27, count 0 2006.197.08:17:07.80#ibcon#flushed, iclass 27, count 0 2006.197.08:17:07.80#ibcon#about to write, iclass 27, count 0 2006.197.08:17:07.80#ibcon#wrote, iclass 27, count 0 2006.197.08:17:07.80#ibcon#about to read 3, iclass 27, count 0 2006.197.08:17:07.82#ibcon#read 3, iclass 27, count 0 2006.197.08:17:07.82#ibcon#about to read 4, iclass 27, count 0 2006.197.08:17:07.82#ibcon#read 4, iclass 27, count 0 2006.197.08:17:07.82#ibcon#about to read 5, iclass 27, count 0 2006.197.08:17:07.82#ibcon#read 5, iclass 27, count 0 2006.197.08:17:07.82#ibcon#about to read 6, iclass 27, count 0 2006.197.08:17:07.82#ibcon#read 6, iclass 27, count 0 2006.197.08:17:07.82#ibcon#end of sib2, iclass 27, count 0 2006.197.08:17:07.82#ibcon#*mode == 0, iclass 27, count 0 2006.197.08:17:07.82#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.197.08:17:07.82#ibcon#[25=USB\r\n] 2006.197.08:17:07.82#ibcon#*before write, iclass 27, count 0 2006.197.08:17:07.82#ibcon#enter sib2, iclass 27, count 0 2006.197.08:17:07.82#ibcon#flushed, iclass 27, count 0 2006.197.08:17:07.82#ibcon#about to write, iclass 27, count 0 2006.197.08:17:07.82#ibcon#wrote, iclass 27, count 0 2006.197.08:17:07.82#ibcon#about to read 3, iclass 27, count 0 2006.197.08:17:07.82#abcon#<5=/05 3.6 7.2 25.57 961002.7\r\n> 2006.197.08:17:07.84#abcon#{5=INTERFACE CLEAR} 2006.197.08:17:07.85#ibcon#read 3, iclass 27, count 0 2006.197.08:17:07.85#ibcon#about to read 4, iclass 27, count 0 2006.197.08:17:07.85#ibcon#read 4, iclass 27, count 0 2006.197.08:17:07.85#ibcon#about to read 5, iclass 27, count 0 2006.197.08:17:07.85#ibcon#read 5, iclass 27, count 0 2006.197.08:17:07.85#ibcon#about to read 6, iclass 27, count 0 2006.197.08:17:07.85#ibcon#read 6, iclass 27, count 0 2006.197.08:17:07.85#ibcon#end of sib2, iclass 27, count 0 2006.197.08:17:07.85#ibcon#*after write, iclass 27, count 0 2006.197.08:17:07.85#ibcon#*before return 0, iclass 27, count 0 2006.197.08:17:07.85#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.197.08:17:07.85#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.197.08:17:07.85#ibcon#about to clear, iclass 27 cls_cnt 0 2006.197.08:17:07.85#ibcon#cleared, iclass 27 cls_cnt 0 2006.197.08:17:07.85$vc4f8/valo=2,572.99 2006.197.08:17:07.85#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.197.08:17:07.85#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.197.08:17:07.85#ibcon#ireg 17 cls_cnt 0 2006.197.08:17:07.85#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.197.08:17:07.85#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.197.08:17:07.85#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.197.08:17:07.85#ibcon#enter wrdev, iclass 32, count 0 2006.197.08:17:07.85#ibcon#first serial, iclass 32, count 0 2006.197.08:17:07.85#ibcon#enter sib2, iclass 32, count 0 2006.197.08:17:07.85#ibcon#flushed, iclass 32, count 0 2006.197.08:17:07.85#ibcon#about to write, iclass 32, count 0 2006.197.08:17:07.85#ibcon#wrote, iclass 32, count 0 2006.197.08:17:07.85#ibcon#about to read 3, iclass 32, count 0 2006.197.08:17:07.87#ibcon#read 3, iclass 32, count 0 2006.197.08:17:07.87#ibcon#about to read 4, iclass 32, count 0 2006.197.08:17:07.87#ibcon#read 4, iclass 32, count 0 2006.197.08:17:07.87#ibcon#about to read 5, iclass 32, count 0 2006.197.08:17:07.87#ibcon#read 5, iclass 32, count 0 2006.197.08:17:07.87#ibcon#about to read 6, iclass 32, count 0 2006.197.08:17:07.87#ibcon#read 6, iclass 32, count 0 2006.197.08:17:07.87#ibcon#end of sib2, iclass 32, count 0 2006.197.08:17:07.87#ibcon#*mode == 0, iclass 32, count 0 2006.197.08:17:07.87#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.197.08:17:07.87#ibcon#[26=FRQ=02,572.99\r\n] 2006.197.08:17:07.87#ibcon#*before write, iclass 32, count 0 2006.197.08:17:07.87#ibcon#enter sib2, iclass 32, count 0 2006.197.08:17:07.87#ibcon#flushed, iclass 32, count 0 2006.197.08:17:07.87#ibcon#about to write, iclass 32, count 0 2006.197.08:17:07.87#ibcon#wrote, iclass 32, count 0 2006.197.08:17:07.87#ibcon#about to read 3, iclass 32, count 0 2006.197.08:17:07.90#abcon#[5=S1D000X0/0*\r\n] 2006.197.08:17:07.91#ibcon#read 3, iclass 32, count 0 2006.197.08:17:07.91#ibcon#about to read 4, iclass 32, count 0 2006.197.08:17:07.91#ibcon#read 4, iclass 32, count 0 2006.197.08:17:07.91#ibcon#about to read 5, iclass 32, count 0 2006.197.08:17:07.91#ibcon#read 5, iclass 32, count 0 2006.197.08:17:07.91#ibcon#about to read 6, iclass 32, count 0 2006.197.08:17:07.91#ibcon#read 6, iclass 32, count 0 2006.197.08:17:07.91#ibcon#end of sib2, iclass 32, count 0 2006.197.08:17:07.91#ibcon#*after write, iclass 32, count 0 2006.197.08:17:07.91#ibcon#*before return 0, iclass 32, count 0 2006.197.08:17:07.91#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.197.08:17:07.91#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.197.08:17:07.91#ibcon#about to clear, iclass 32 cls_cnt 0 2006.197.08:17:07.91#ibcon#cleared, iclass 32 cls_cnt 0 2006.197.08:17:07.91$vc4f8/va=2,7 2006.197.08:17:07.91#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.197.08:17:07.91#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.197.08:17:07.91#ibcon#ireg 11 cls_cnt 2 2006.197.08:17:07.91#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.197.08:17:07.97#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.197.08:17:07.97#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.197.08:17:07.97#ibcon#enter wrdev, iclass 35, count 2 2006.197.08:17:07.97#ibcon#first serial, iclass 35, count 2 2006.197.08:17:07.97#ibcon#enter sib2, iclass 35, count 2 2006.197.08:17:07.97#ibcon#flushed, iclass 35, count 2 2006.197.08:17:07.97#ibcon#about to write, iclass 35, count 2 2006.197.08:17:07.97#ibcon#wrote, iclass 35, count 2 2006.197.08:17:07.97#ibcon#about to read 3, iclass 35, count 2 2006.197.08:17:07.99#ibcon#read 3, iclass 35, count 2 2006.197.08:17:07.99#ibcon#about to read 4, iclass 35, count 2 2006.197.08:17:07.99#ibcon#read 4, iclass 35, count 2 2006.197.08:17:07.99#ibcon#about to read 5, iclass 35, count 2 2006.197.08:17:07.99#ibcon#read 5, iclass 35, count 2 2006.197.08:17:07.99#ibcon#about to read 6, iclass 35, count 2 2006.197.08:17:07.99#ibcon#read 6, iclass 35, count 2 2006.197.08:17:07.99#ibcon#end of sib2, iclass 35, count 2 2006.197.08:17:07.99#ibcon#*mode == 0, iclass 35, count 2 2006.197.08:17:07.99#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.197.08:17:07.99#ibcon#[25=AT02-07\r\n] 2006.197.08:17:07.99#ibcon#*before write, iclass 35, count 2 2006.197.08:17:07.99#ibcon#enter sib2, iclass 35, count 2 2006.197.08:17:07.99#ibcon#flushed, iclass 35, count 2 2006.197.08:17:07.99#ibcon#about to write, iclass 35, count 2 2006.197.08:17:07.99#ibcon#wrote, iclass 35, count 2 2006.197.08:17:07.99#ibcon#about to read 3, iclass 35, count 2 2006.197.08:17:08.02#ibcon#read 3, iclass 35, count 2 2006.197.08:17:08.02#ibcon#about to read 4, iclass 35, count 2 2006.197.08:17:08.02#ibcon#read 4, iclass 35, count 2 2006.197.08:17:08.02#ibcon#about to read 5, iclass 35, count 2 2006.197.08:17:08.02#ibcon#read 5, iclass 35, count 2 2006.197.08:17:08.02#ibcon#about to read 6, iclass 35, count 2 2006.197.08:17:08.02#ibcon#read 6, iclass 35, count 2 2006.197.08:17:08.02#ibcon#end of sib2, iclass 35, count 2 2006.197.08:17:08.02#ibcon#*after write, iclass 35, count 2 2006.197.08:17:08.02#ibcon#*before return 0, iclass 35, count 2 2006.197.08:17:08.02#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.197.08:17:08.02#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.197.08:17:08.02#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.197.08:17:08.02#ibcon#ireg 7 cls_cnt 0 2006.197.08:17:08.02#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.197.08:17:08.14#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.197.08:17:08.14#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.197.08:17:08.14#ibcon#enter wrdev, iclass 35, count 0 2006.197.08:17:08.14#ibcon#first serial, iclass 35, count 0 2006.197.08:17:08.14#ibcon#enter sib2, iclass 35, count 0 2006.197.08:17:08.14#ibcon#flushed, iclass 35, count 0 2006.197.08:17:08.14#ibcon#about to write, iclass 35, count 0 2006.197.08:17:08.14#ibcon#wrote, iclass 35, count 0 2006.197.08:17:08.14#ibcon#about to read 3, iclass 35, count 0 2006.197.08:17:08.16#ibcon#read 3, iclass 35, count 0 2006.197.08:17:08.16#ibcon#about to read 4, iclass 35, count 0 2006.197.08:17:08.16#ibcon#read 4, iclass 35, count 0 2006.197.08:17:08.16#ibcon#about to read 5, iclass 35, count 0 2006.197.08:17:08.16#ibcon#read 5, iclass 35, count 0 2006.197.08:17:08.16#ibcon#about to read 6, iclass 35, count 0 2006.197.08:17:08.16#ibcon#read 6, iclass 35, count 0 2006.197.08:17:08.16#ibcon#end of sib2, iclass 35, count 0 2006.197.08:17:08.16#ibcon#*mode == 0, iclass 35, count 0 2006.197.08:17:08.16#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.197.08:17:08.16#ibcon#[25=USB\r\n] 2006.197.08:17:08.16#ibcon#*before write, iclass 35, count 0 2006.197.08:17:08.16#ibcon#enter sib2, iclass 35, count 0 2006.197.08:17:08.16#ibcon#flushed, iclass 35, count 0 2006.197.08:17:08.16#ibcon#about to write, iclass 35, count 0 2006.197.08:17:08.16#ibcon#wrote, iclass 35, count 0 2006.197.08:17:08.16#ibcon#about to read 3, iclass 35, count 0 2006.197.08:17:08.19#ibcon#read 3, iclass 35, count 0 2006.197.08:17:08.19#ibcon#about to read 4, iclass 35, count 0 2006.197.08:17:08.19#ibcon#read 4, iclass 35, count 0 2006.197.08:17:08.19#ibcon#about to read 5, iclass 35, count 0 2006.197.08:17:08.19#ibcon#read 5, iclass 35, count 0 2006.197.08:17:08.19#ibcon#about to read 6, iclass 35, count 0 2006.197.08:17:08.19#ibcon#read 6, iclass 35, count 0 2006.197.08:17:08.19#ibcon#end of sib2, iclass 35, count 0 2006.197.08:17:08.19#ibcon#*after write, iclass 35, count 0 2006.197.08:17:08.19#ibcon#*before return 0, iclass 35, count 0 2006.197.08:17:08.19#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.197.08:17:08.19#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.197.08:17:08.19#ibcon#about to clear, iclass 35 cls_cnt 0 2006.197.08:17:08.19#ibcon#cleared, iclass 35 cls_cnt 0 2006.197.08:17:08.19$vc4f8/valo=3,672.99 2006.197.08:17:08.19#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.197.08:17:08.19#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.197.08:17:08.19#ibcon#ireg 17 cls_cnt 0 2006.197.08:17:08.19#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.197.08:17:08.19#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.197.08:17:08.19#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.197.08:17:08.19#ibcon#enter wrdev, iclass 37, count 0 2006.197.08:17:08.19#ibcon#first serial, iclass 37, count 0 2006.197.08:17:08.19#ibcon#enter sib2, iclass 37, count 0 2006.197.08:17:08.19#ibcon#flushed, iclass 37, count 0 2006.197.08:17:08.19#ibcon#about to write, iclass 37, count 0 2006.197.08:17:08.19#ibcon#wrote, iclass 37, count 0 2006.197.08:17:08.19#ibcon#about to read 3, iclass 37, count 0 2006.197.08:17:08.21#ibcon#read 3, iclass 37, count 0 2006.197.08:17:08.21#ibcon#about to read 4, iclass 37, count 0 2006.197.08:17:08.21#ibcon#read 4, iclass 37, count 0 2006.197.08:17:08.21#ibcon#about to read 5, iclass 37, count 0 2006.197.08:17:08.21#ibcon#read 5, iclass 37, count 0 2006.197.08:17:08.21#ibcon#about to read 6, iclass 37, count 0 2006.197.08:17:08.21#ibcon#read 6, iclass 37, count 0 2006.197.08:17:08.21#ibcon#end of sib2, iclass 37, count 0 2006.197.08:17:08.21#ibcon#*mode == 0, iclass 37, count 0 2006.197.08:17:08.21#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.197.08:17:08.21#ibcon#[26=FRQ=03,672.99\r\n] 2006.197.08:17:08.21#ibcon#*before write, iclass 37, count 0 2006.197.08:17:08.21#ibcon#enter sib2, iclass 37, count 0 2006.197.08:17:08.21#ibcon#flushed, iclass 37, count 0 2006.197.08:17:08.21#ibcon#about to write, iclass 37, count 0 2006.197.08:17:08.21#ibcon#wrote, iclass 37, count 0 2006.197.08:17:08.21#ibcon#about to read 3, iclass 37, count 0 2006.197.08:17:08.25#ibcon#read 3, iclass 37, count 0 2006.197.08:17:08.25#ibcon#about to read 4, iclass 37, count 0 2006.197.08:17:08.25#ibcon#read 4, iclass 37, count 0 2006.197.08:17:08.25#ibcon#about to read 5, iclass 37, count 0 2006.197.08:17:08.25#ibcon#read 5, iclass 37, count 0 2006.197.08:17:08.25#ibcon#about to read 6, iclass 37, count 0 2006.197.08:17:08.25#ibcon#read 6, iclass 37, count 0 2006.197.08:17:08.25#ibcon#end of sib2, iclass 37, count 0 2006.197.08:17:08.25#ibcon#*after write, iclass 37, count 0 2006.197.08:17:08.25#ibcon#*before return 0, iclass 37, count 0 2006.197.08:17:08.25#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.197.08:17:08.25#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.197.08:17:08.25#ibcon#about to clear, iclass 37 cls_cnt 0 2006.197.08:17:08.25#ibcon#cleared, iclass 37 cls_cnt 0 2006.197.08:17:08.25$vc4f8/va=3,6 2006.197.08:17:08.25#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.197.08:17:08.25#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.197.08:17:08.25#ibcon#ireg 11 cls_cnt 2 2006.197.08:17:08.25#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.197.08:17:08.31#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.197.08:17:08.31#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.197.08:17:08.31#ibcon#enter wrdev, iclass 39, count 2 2006.197.08:17:08.31#ibcon#first serial, iclass 39, count 2 2006.197.08:17:08.31#ibcon#enter sib2, iclass 39, count 2 2006.197.08:17:08.31#ibcon#flushed, iclass 39, count 2 2006.197.08:17:08.31#ibcon#about to write, iclass 39, count 2 2006.197.08:17:08.31#ibcon#wrote, iclass 39, count 2 2006.197.08:17:08.31#ibcon#about to read 3, iclass 39, count 2 2006.197.08:17:08.33#ibcon#read 3, iclass 39, count 2 2006.197.08:17:08.33#ibcon#about to read 4, iclass 39, count 2 2006.197.08:17:08.33#ibcon#read 4, iclass 39, count 2 2006.197.08:17:08.33#ibcon#about to read 5, iclass 39, count 2 2006.197.08:17:08.33#ibcon#read 5, iclass 39, count 2 2006.197.08:17:08.33#ibcon#about to read 6, iclass 39, count 2 2006.197.08:17:08.33#ibcon#read 6, iclass 39, count 2 2006.197.08:17:08.33#ibcon#end of sib2, iclass 39, count 2 2006.197.08:17:08.33#ibcon#*mode == 0, iclass 39, count 2 2006.197.08:17:08.33#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.197.08:17:08.33#ibcon#[25=AT03-06\r\n] 2006.197.08:17:08.33#ibcon#*before write, iclass 39, count 2 2006.197.08:17:08.33#ibcon#enter sib2, iclass 39, count 2 2006.197.08:17:08.33#ibcon#flushed, iclass 39, count 2 2006.197.08:17:08.33#ibcon#about to write, iclass 39, count 2 2006.197.08:17:08.33#ibcon#wrote, iclass 39, count 2 2006.197.08:17:08.33#ibcon#about to read 3, iclass 39, count 2 2006.197.08:17:08.36#ibcon#read 3, iclass 39, count 2 2006.197.08:17:08.36#ibcon#about to read 4, iclass 39, count 2 2006.197.08:17:08.36#ibcon#read 4, iclass 39, count 2 2006.197.08:17:08.36#ibcon#about to read 5, iclass 39, count 2 2006.197.08:17:08.36#ibcon#read 5, iclass 39, count 2 2006.197.08:17:08.36#ibcon#about to read 6, iclass 39, count 2 2006.197.08:17:08.36#ibcon#read 6, iclass 39, count 2 2006.197.08:17:08.36#ibcon#end of sib2, iclass 39, count 2 2006.197.08:17:08.36#ibcon#*after write, iclass 39, count 2 2006.197.08:17:08.36#ibcon#*before return 0, iclass 39, count 2 2006.197.08:17:08.36#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.197.08:17:08.36#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.197.08:17:08.36#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.197.08:17:08.36#ibcon#ireg 7 cls_cnt 0 2006.197.08:17:08.36#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.197.08:17:08.48#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.197.08:17:08.48#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.197.08:17:08.48#ibcon#enter wrdev, iclass 39, count 0 2006.197.08:17:08.48#ibcon#first serial, iclass 39, count 0 2006.197.08:17:08.48#ibcon#enter sib2, iclass 39, count 0 2006.197.08:17:08.48#ibcon#flushed, iclass 39, count 0 2006.197.08:17:08.48#ibcon#about to write, iclass 39, count 0 2006.197.08:17:08.48#ibcon#wrote, iclass 39, count 0 2006.197.08:17:08.48#ibcon#about to read 3, iclass 39, count 0 2006.197.08:17:08.50#ibcon#read 3, iclass 39, count 0 2006.197.08:17:08.50#ibcon#about to read 4, iclass 39, count 0 2006.197.08:17:08.50#ibcon#read 4, iclass 39, count 0 2006.197.08:17:08.50#ibcon#about to read 5, iclass 39, count 0 2006.197.08:17:08.50#ibcon#read 5, iclass 39, count 0 2006.197.08:17:08.50#ibcon#about to read 6, iclass 39, count 0 2006.197.08:17:08.50#ibcon#read 6, iclass 39, count 0 2006.197.08:17:08.50#ibcon#end of sib2, iclass 39, count 0 2006.197.08:17:08.50#ibcon#*mode == 0, iclass 39, count 0 2006.197.08:17:08.50#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.197.08:17:08.50#ibcon#[25=USB\r\n] 2006.197.08:17:08.50#ibcon#*before write, iclass 39, count 0 2006.197.08:17:08.50#ibcon#enter sib2, iclass 39, count 0 2006.197.08:17:08.50#ibcon#flushed, iclass 39, count 0 2006.197.08:17:08.50#ibcon#about to write, iclass 39, count 0 2006.197.08:17:08.50#ibcon#wrote, iclass 39, count 0 2006.197.08:17:08.50#ibcon#about to read 3, iclass 39, count 0 2006.197.08:17:08.53#ibcon#read 3, iclass 39, count 0 2006.197.08:17:08.53#ibcon#about to read 4, iclass 39, count 0 2006.197.08:17:08.53#ibcon#read 4, iclass 39, count 0 2006.197.08:17:08.53#ibcon#about to read 5, iclass 39, count 0 2006.197.08:17:08.53#ibcon#read 5, iclass 39, count 0 2006.197.08:17:08.53#ibcon#about to read 6, iclass 39, count 0 2006.197.08:17:08.53#ibcon#read 6, iclass 39, count 0 2006.197.08:17:08.53#ibcon#end of sib2, iclass 39, count 0 2006.197.08:17:08.53#ibcon#*after write, iclass 39, count 0 2006.197.08:17:08.53#ibcon#*before return 0, iclass 39, count 0 2006.197.08:17:08.53#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.197.08:17:08.53#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.197.08:17:08.53#ibcon#about to clear, iclass 39 cls_cnt 0 2006.197.08:17:08.53#ibcon#cleared, iclass 39 cls_cnt 0 2006.197.08:17:08.53$vc4f8/valo=4,832.99 2006.197.08:17:08.53#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.197.08:17:08.53#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.197.08:17:08.53#ibcon#ireg 17 cls_cnt 0 2006.197.08:17:08.53#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.197.08:17:08.53#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.197.08:17:08.53#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.197.08:17:08.53#ibcon#enter wrdev, iclass 3, count 0 2006.197.08:17:08.53#ibcon#first serial, iclass 3, count 0 2006.197.08:17:08.53#ibcon#enter sib2, iclass 3, count 0 2006.197.08:17:08.53#ibcon#flushed, iclass 3, count 0 2006.197.08:17:08.53#ibcon#about to write, iclass 3, count 0 2006.197.08:17:08.53#ibcon#wrote, iclass 3, count 0 2006.197.08:17:08.53#ibcon#about to read 3, iclass 3, count 0 2006.197.08:17:08.55#ibcon#read 3, iclass 3, count 0 2006.197.08:17:08.55#ibcon#about to read 4, iclass 3, count 0 2006.197.08:17:08.55#ibcon#read 4, iclass 3, count 0 2006.197.08:17:08.55#ibcon#about to read 5, iclass 3, count 0 2006.197.08:17:08.55#ibcon#read 5, iclass 3, count 0 2006.197.08:17:08.55#ibcon#about to read 6, iclass 3, count 0 2006.197.08:17:08.55#ibcon#read 6, iclass 3, count 0 2006.197.08:17:08.55#ibcon#end of sib2, iclass 3, count 0 2006.197.08:17:08.55#ibcon#*mode == 0, iclass 3, count 0 2006.197.08:17:08.55#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.197.08:17:08.55#ibcon#[26=FRQ=04,832.99\r\n] 2006.197.08:17:08.55#ibcon#*before write, iclass 3, count 0 2006.197.08:17:08.55#ibcon#enter sib2, iclass 3, count 0 2006.197.08:17:08.55#ibcon#flushed, iclass 3, count 0 2006.197.08:17:08.55#ibcon#about to write, iclass 3, count 0 2006.197.08:17:08.55#ibcon#wrote, iclass 3, count 0 2006.197.08:17:08.55#ibcon#about to read 3, iclass 3, count 0 2006.197.08:17:08.59#ibcon#read 3, iclass 3, count 0 2006.197.08:17:08.59#ibcon#about to read 4, iclass 3, count 0 2006.197.08:17:08.59#ibcon#read 4, iclass 3, count 0 2006.197.08:17:08.59#ibcon#about to read 5, iclass 3, count 0 2006.197.08:17:08.59#ibcon#read 5, iclass 3, count 0 2006.197.08:17:08.59#ibcon#about to read 6, iclass 3, count 0 2006.197.08:17:08.59#ibcon#read 6, iclass 3, count 0 2006.197.08:17:08.59#ibcon#end of sib2, iclass 3, count 0 2006.197.08:17:08.59#ibcon#*after write, iclass 3, count 0 2006.197.08:17:08.59#ibcon#*before return 0, iclass 3, count 0 2006.197.08:17:08.59#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.197.08:17:08.59#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.197.08:17:08.59#ibcon#about to clear, iclass 3 cls_cnt 0 2006.197.08:17:08.59#ibcon#cleared, iclass 3 cls_cnt 0 2006.197.08:17:08.59$vc4f8/va=4,7 2006.197.08:17:08.59#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.197.08:17:08.59#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.197.08:17:08.59#ibcon#ireg 11 cls_cnt 2 2006.197.08:17:08.59#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.197.08:17:08.65#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.197.08:17:08.65#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.197.08:17:08.65#ibcon#enter wrdev, iclass 5, count 2 2006.197.08:17:08.65#ibcon#first serial, iclass 5, count 2 2006.197.08:17:08.65#ibcon#enter sib2, iclass 5, count 2 2006.197.08:17:08.65#ibcon#flushed, iclass 5, count 2 2006.197.08:17:08.65#ibcon#about to write, iclass 5, count 2 2006.197.08:17:08.65#ibcon#wrote, iclass 5, count 2 2006.197.08:17:08.65#ibcon#about to read 3, iclass 5, count 2 2006.197.08:17:08.67#ibcon#read 3, iclass 5, count 2 2006.197.08:17:08.67#ibcon#about to read 4, iclass 5, count 2 2006.197.08:17:08.67#ibcon#read 4, iclass 5, count 2 2006.197.08:17:08.67#ibcon#about to read 5, iclass 5, count 2 2006.197.08:17:08.67#ibcon#read 5, iclass 5, count 2 2006.197.08:17:08.67#ibcon#about to read 6, iclass 5, count 2 2006.197.08:17:08.67#ibcon#read 6, iclass 5, count 2 2006.197.08:17:08.67#ibcon#end of sib2, iclass 5, count 2 2006.197.08:17:08.67#ibcon#*mode == 0, iclass 5, count 2 2006.197.08:17:08.67#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.197.08:17:08.67#ibcon#[25=AT04-07\r\n] 2006.197.08:17:08.67#ibcon#*before write, iclass 5, count 2 2006.197.08:17:08.67#ibcon#enter sib2, iclass 5, count 2 2006.197.08:17:08.67#ibcon#flushed, iclass 5, count 2 2006.197.08:17:08.67#ibcon#about to write, iclass 5, count 2 2006.197.08:17:08.67#ibcon#wrote, iclass 5, count 2 2006.197.08:17:08.67#ibcon#about to read 3, iclass 5, count 2 2006.197.08:17:08.70#ibcon#read 3, iclass 5, count 2 2006.197.08:17:08.70#ibcon#about to read 4, iclass 5, count 2 2006.197.08:17:08.70#ibcon#read 4, iclass 5, count 2 2006.197.08:17:08.70#ibcon#about to read 5, iclass 5, count 2 2006.197.08:17:08.70#ibcon#read 5, iclass 5, count 2 2006.197.08:17:08.70#ibcon#about to read 6, iclass 5, count 2 2006.197.08:17:08.70#ibcon#read 6, iclass 5, count 2 2006.197.08:17:08.70#ibcon#end of sib2, iclass 5, count 2 2006.197.08:17:08.70#ibcon#*after write, iclass 5, count 2 2006.197.08:17:08.70#ibcon#*before return 0, iclass 5, count 2 2006.197.08:17:08.70#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.197.08:17:08.70#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.197.08:17:08.70#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.197.08:17:08.70#ibcon#ireg 7 cls_cnt 0 2006.197.08:17:08.70#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.197.08:17:08.82#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.197.08:17:08.82#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.197.08:17:08.82#ibcon#enter wrdev, iclass 5, count 0 2006.197.08:17:08.82#ibcon#first serial, iclass 5, count 0 2006.197.08:17:08.82#ibcon#enter sib2, iclass 5, count 0 2006.197.08:17:08.82#ibcon#flushed, iclass 5, count 0 2006.197.08:17:08.82#ibcon#about to write, iclass 5, count 0 2006.197.08:17:08.82#ibcon#wrote, iclass 5, count 0 2006.197.08:17:08.82#ibcon#about to read 3, iclass 5, count 0 2006.197.08:17:08.84#ibcon#read 3, iclass 5, count 0 2006.197.08:17:08.84#ibcon#about to read 4, iclass 5, count 0 2006.197.08:17:08.84#ibcon#read 4, iclass 5, count 0 2006.197.08:17:08.84#ibcon#about to read 5, iclass 5, count 0 2006.197.08:17:08.84#ibcon#read 5, iclass 5, count 0 2006.197.08:17:08.84#ibcon#about to read 6, iclass 5, count 0 2006.197.08:17:08.84#ibcon#read 6, iclass 5, count 0 2006.197.08:17:08.84#ibcon#end of sib2, iclass 5, count 0 2006.197.08:17:08.84#ibcon#*mode == 0, iclass 5, count 0 2006.197.08:17:08.84#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.197.08:17:08.84#ibcon#[25=USB\r\n] 2006.197.08:17:08.84#ibcon#*before write, iclass 5, count 0 2006.197.08:17:08.84#ibcon#enter sib2, iclass 5, count 0 2006.197.08:17:08.84#ibcon#flushed, iclass 5, count 0 2006.197.08:17:08.84#ibcon#about to write, iclass 5, count 0 2006.197.08:17:08.84#ibcon#wrote, iclass 5, count 0 2006.197.08:17:08.84#ibcon#about to read 3, iclass 5, count 0 2006.197.08:17:08.87#ibcon#read 3, iclass 5, count 0 2006.197.08:17:08.87#ibcon#about to read 4, iclass 5, count 0 2006.197.08:17:08.87#ibcon#read 4, iclass 5, count 0 2006.197.08:17:08.87#ibcon#about to read 5, iclass 5, count 0 2006.197.08:17:08.87#ibcon#read 5, iclass 5, count 0 2006.197.08:17:08.87#ibcon#about to read 6, iclass 5, count 0 2006.197.08:17:08.87#ibcon#read 6, iclass 5, count 0 2006.197.08:17:08.87#ibcon#end of sib2, iclass 5, count 0 2006.197.08:17:08.87#ibcon#*after write, iclass 5, count 0 2006.197.08:17:08.87#ibcon#*before return 0, iclass 5, count 0 2006.197.08:17:08.87#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.197.08:17:08.87#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.197.08:17:08.87#ibcon#about to clear, iclass 5 cls_cnt 0 2006.197.08:17:08.87#ibcon#cleared, iclass 5 cls_cnt 0 2006.197.08:17:08.87$vc4f8/valo=5,652.99 2006.197.08:17:08.87#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.197.08:17:08.87#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.197.08:17:08.87#ibcon#ireg 17 cls_cnt 0 2006.197.08:17:08.87#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.197.08:17:08.87#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.197.08:17:08.87#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.197.08:17:08.87#ibcon#enter wrdev, iclass 7, count 0 2006.197.08:17:08.87#ibcon#first serial, iclass 7, count 0 2006.197.08:17:08.87#ibcon#enter sib2, iclass 7, count 0 2006.197.08:17:08.87#ibcon#flushed, iclass 7, count 0 2006.197.08:17:08.87#ibcon#about to write, iclass 7, count 0 2006.197.08:17:08.87#ibcon#wrote, iclass 7, count 0 2006.197.08:17:08.87#ibcon#about to read 3, iclass 7, count 0 2006.197.08:17:08.89#ibcon#read 3, iclass 7, count 0 2006.197.08:17:08.89#ibcon#about to read 4, iclass 7, count 0 2006.197.08:17:08.89#ibcon#read 4, iclass 7, count 0 2006.197.08:17:08.89#ibcon#about to read 5, iclass 7, count 0 2006.197.08:17:08.89#ibcon#read 5, iclass 7, count 0 2006.197.08:17:08.89#ibcon#about to read 6, iclass 7, count 0 2006.197.08:17:08.89#ibcon#read 6, iclass 7, count 0 2006.197.08:17:08.89#ibcon#end of sib2, iclass 7, count 0 2006.197.08:17:08.89#ibcon#*mode == 0, iclass 7, count 0 2006.197.08:17:08.89#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.197.08:17:08.89#ibcon#[26=FRQ=05,652.99\r\n] 2006.197.08:17:08.89#ibcon#*before write, iclass 7, count 0 2006.197.08:17:08.89#ibcon#enter sib2, iclass 7, count 0 2006.197.08:17:08.89#ibcon#flushed, iclass 7, count 0 2006.197.08:17:08.89#ibcon#about to write, iclass 7, count 0 2006.197.08:17:08.89#ibcon#wrote, iclass 7, count 0 2006.197.08:17:08.89#ibcon#about to read 3, iclass 7, count 0 2006.197.08:17:08.93#ibcon#read 3, iclass 7, count 0 2006.197.08:17:08.93#ibcon#about to read 4, iclass 7, count 0 2006.197.08:17:08.93#ibcon#read 4, iclass 7, count 0 2006.197.08:17:08.93#ibcon#about to read 5, iclass 7, count 0 2006.197.08:17:08.93#ibcon#read 5, iclass 7, count 0 2006.197.08:17:08.93#ibcon#about to read 6, iclass 7, count 0 2006.197.08:17:08.93#ibcon#read 6, iclass 7, count 0 2006.197.08:17:08.93#ibcon#end of sib2, iclass 7, count 0 2006.197.08:17:08.93#ibcon#*after write, iclass 7, count 0 2006.197.08:17:08.93#ibcon#*before return 0, iclass 7, count 0 2006.197.08:17:08.93#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.197.08:17:08.93#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.197.08:17:08.93#ibcon#about to clear, iclass 7 cls_cnt 0 2006.197.08:17:08.93#ibcon#cleared, iclass 7 cls_cnt 0 2006.197.08:17:08.93$vc4f8/va=5,7 2006.197.08:17:08.93#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.197.08:17:08.93#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.197.08:17:08.93#ibcon#ireg 11 cls_cnt 2 2006.197.08:17:08.93#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.197.08:17:08.99#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.197.08:17:08.99#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.197.08:17:08.99#ibcon#enter wrdev, iclass 11, count 2 2006.197.08:17:08.99#ibcon#first serial, iclass 11, count 2 2006.197.08:17:08.99#ibcon#enter sib2, iclass 11, count 2 2006.197.08:17:08.99#ibcon#flushed, iclass 11, count 2 2006.197.08:17:08.99#ibcon#about to write, iclass 11, count 2 2006.197.08:17:08.99#ibcon#wrote, iclass 11, count 2 2006.197.08:17:08.99#ibcon#about to read 3, iclass 11, count 2 2006.197.08:17:09.01#ibcon#read 3, iclass 11, count 2 2006.197.08:17:09.01#ibcon#about to read 4, iclass 11, count 2 2006.197.08:17:09.01#ibcon#read 4, iclass 11, count 2 2006.197.08:17:09.01#ibcon#about to read 5, iclass 11, count 2 2006.197.08:17:09.01#ibcon#read 5, iclass 11, count 2 2006.197.08:17:09.01#ibcon#about to read 6, iclass 11, count 2 2006.197.08:17:09.01#ibcon#read 6, iclass 11, count 2 2006.197.08:17:09.01#ibcon#end of sib2, iclass 11, count 2 2006.197.08:17:09.01#ibcon#*mode == 0, iclass 11, count 2 2006.197.08:17:09.01#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.197.08:17:09.01#ibcon#[25=AT05-07\r\n] 2006.197.08:17:09.01#ibcon#*before write, iclass 11, count 2 2006.197.08:17:09.01#ibcon#enter sib2, iclass 11, count 2 2006.197.08:17:09.01#ibcon#flushed, iclass 11, count 2 2006.197.08:17:09.01#ibcon#about to write, iclass 11, count 2 2006.197.08:17:09.01#ibcon#wrote, iclass 11, count 2 2006.197.08:17:09.01#ibcon#about to read 3, iclass 11, count 2 2006.197.08:17:09.04#ibcon#read 3, iclass 11, count 2 2006.197.08:17:09.04#ibcon#about to read 4, iclass 11, count 2 2006.197.08:17:09.04#ibcon#read 4, iclass 11, count 2 2006.197.08:17:09.04#ibcon#about to read 5, iclass 11, count 2 2006.197.08:17:09.04#ibcon#read 5, iclass 11, count 2 2006.197.08:17:09.04#ibcon#about to read 6, iclass 11, count 2 2006.197.08:17:09.04#ibcon#read 6, iclass 11, count 2 2006.197.08:17:09.04#ibcon#end of sib2, iclass 11, count 2 2006.197.08:17:09.04#ibcon#*after write, iclass 11, count 2 2006.197.08:17:09.04#ibcon#*before return 0, iclass 11, count 2 2006.197.08:17:09.04#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.197.08:17:09.04#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.197.08:17:09.04#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.197.08:17:09.04#ibcon#ireg 7 cls_cnt 0 2006.197.08:17:09.04#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.197.08:17:09.16#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.197.08:17:09.16#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.197.08:17:09.16#ibcon#enter wrdev, iclass 11, count 0 2006.197.08:17:09.16#ibcon#first serial, iclass 11, count 0 2006.197.08:17:09.16#ibcon#enter sib2, iclass 11, count 0 2006.197.08:17:09.16#ibcon#flushed, iclass 11, count 0 2006.197.08:17:09.16#ibcon#about to write, iclass 11, count 0 2006.197.08:17:09.16#ibcon#wrote, iclass 11, count 0 2006.197.08:17:09.16#ibcon#about to read 3, iclass 11, count 0 2006.197.08:17:09.18#ibcon#read 3, iclass 11, count 0 2006.197.08:17:09.18#ibcon#about to read 4, iclass 11, count 0 2006.197.08:17:09.18#ibcon#read 4, iclass 11, count 0 2006.197.08:17:09.18#ibcon#about to read 5, iclass 11, count 0 2006.197.08:17:09.18#ibcon#read 5, iclass 11, count 0 2006.197.08:17:09.18#ibcon#about to read 6, iclass 11, count 0 2006.197.08:17:09.18#ibcon#read 6, iclass 11, count 0 2006.197.08:17:09.18#ibcon#end of sib2, iclass 11, count 0 2006.197.08:17:09.18#ibcon#*mode == 0, iclass 11, count 0 2006.197.08:17:09.18#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.197.08:17:09.18#ibcon#[25=USB\r\n] 2006.197.08:17:09.18#ibcon#*before write, iclass 11, count 0 2006.197.08:17:09.18#ibcon#enter sib2, iclass 11, count 0 2006.197.08:17:09.18#ibcon#flushed, iclass 11, count 0 2006.197.08:17:09.18#ibcon#about to write, iclass 11, count 0 2006.197.08:17:09.18#ibcon#wrote, iclass 11, count 0 2006.197.08:17:09.18#ibcon#about to read 3, iclass 11, count 0 2006.197.08:17:09.21#ibcon#read 3, iclass 11, count 0 2006.197.08:17:09.21#ibcon#about to read 4, iclass 11, count 0 2006.197.08:17:09.21#ibcon#read 4, iclass 11, count 0 2006.197.08:17:09.21#ibcon#about to read 5, iclass 11, count 0 2006.197.08:17:09.21#ibcon#read 5, iclass 11, count 0 2006.197.08:17:09.21#ibcon#about to read 6, iclass 11, count 0 2006.197.08:17:09.21#ibcon#read 6, iclass 11, count 0 2006.197.08:17:09.21#ibcon#end of sib2, iclass 11, count 0 2006.197.08:17:09.21#ibcon#*after write, iclass 11, count 0 2006.197.08:17:09.21#ibcon#*before return 0, iclass 11, count 0 2006.197.08:17:09.21#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.197.08:17:09.21#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.197.08:17:09.21#ibcon#about to clear, iclass 11 cls_cnt 0 2006.197.08:17:09.21#ibcon#cleared, iclass 11 cls_cnt 0 2006.197.08:17:09.21$vc4f8/valo=6,772.99 2006.197.08:17:09.21#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.197.08:17:09.21#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.197.08:17:09.21#ibcon#ireg 17 cls_cnt 0 2006.197.08:17:09.21#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.197.08:17:09.21#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.197.08:17:09.21#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.197.08:17:09.21#ibcon#enter wrdev, iclass 13, count 0 2006.197.08:17:09.21#ibcon#first serial, iclass 13, count 0 2006.197.08:17:09.21#ibcon#enter sib2, iclass 13, count 0 2006.197.08:17:09.21#ibcon#flushed, iclass 13, count 0 2006.197.08:17:09.21#ibcon#about to write, iclass 13, count 0 2006.197.08:17:09.21#ibcon#wrote, iclass 13, count 0 2006.197.08:17:09.21#ibcon#about to read 3, iclass 13, count 0 2006.197.08:17:09.23#ibcon#read 3, iclass 13, count 0 2006.197.08:17:09.23#ibcon#about to read 4, iclass 13, count 0 2006.197.08:17:09.23#ibcon#read 4, iclass 13, count 0 2006.197.08:17:09.23#ibcon#about to read 5, iclass 13, count 0 2006.197.08:17:09.23#ibcon#read 5, iclass 13, count 0 2006.197.08:17:09.23#ibcon#about to read 6, iclass 13, count 0 2006.197.08:17:09.23#ibcon#read 6, iclass 13, count 0 2006.197.08:17:09.23#ibcon#end of sib2, iclass 13, count 0 2006.197.08:17:09.23#ibcon#*mode == 0, iclass 13, count 0 2006.197.08:17:09.23#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.197.08:17:09.23#ibcon#[26=FRQ=06,772.99\r\n] 2006.197.08:17:09.23#ibcon#*before write, iclass 13, count 0 2006.197.08:17:09.23#ibcon#enter sib2, iclass 13, count 0 2006.197.08:17:09.23#ibcon#flushed, iclass 13, count 0 2006.197.08:17:09.23#ibcon#about to write, iclass 13, count 0 2006.197.08:17:09.23#ibcon#wrote, iclass 13, count 0 2006.197.08:17:09.23#ibcon#about to read 3, iclass 13, count 0 2006.197.08:17:09.27#ibcon#read 3, iclass 13, count 0 2006.197.08:17:09.27#ibcon#about to read 4, iclass 13, count 0 2006.197.08:17:09.27#ibcon#read 4, iclass 13, count 0 2006.197.08:17:09.27#ibcon#about to read 5, iclass 13, count 0 2006.197.08:17:09.27#ibcon#read 5, iclass 13, count 0 2006.197.08:17:09.27#ibcon#about to read 6, iclass 13, count 0 2006.197.08:17:09.27#ibcon#read 6, iclass 13, count 0 2006.197.08:17:09.27#ibcon#end of sib2, iclass 13, count 0 2006.197.08:17:09.27#ibcon#*after write, iclass 13, count 0 2006.197.08:17:09.27#ibcon#*before return 0, iclass 13, count 0 2006.197.08:17:09.27#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.197.08:17:09.27#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.197.08:17:09.27#ibcon#about to clear, iclass 13 cls_cnt 0 2006.197.08:17:09.27#ibcon#cleared, iclass 13 cls_cnt 0 2006.197.08:17:09.27$vc4f8/va=6,6 2006.197.08:17:09.27#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.197.08:17:09.27#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.197.08:17:09.27#ibcon#ireg 11 cls_cnt 2 2006.197.08:17:09.27#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.197.08:17:09.33#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.197.08:17:09.33#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.197.08:17:09.33#ibcon#enter wrdev, iclass 15, count 2 2006.197.08:17:09.33#ibcon#first serial, iclass 15, count 2 2006.197.08:17:09.33#ibcon#enter sib2, iclass 15, count 2 2006.197.08:17:09.33#ibcon#flushed, iclass 15, count 2 2006.197.08:17:09.33#ibcon#about to write, iclass 15, count 2 2006.197.08:17:09.33#ibcon#wrote, iclass 15, count 2 2006.197.08:17:09.33#ibcon#about to read 3, iclass 15, count 2 2006.197.08:17:09.35#ibcon#read 3, iclass 15, count 2 2006.197.08:17:09.35#ibcon#about to read 4, iclass 15, count 2 2006.197.08:17:09.35#ibcon#read 4, iclass 15, count 2 2006.197.08:17:09.35#ibcon#about to read 5, iclass 15, count 2 2006.197.08:17:09.35#ibcon#read 5, iclass 15, count 2 2006.197.08:17:09.35#ibcon#about to read 6, iclass 15, count 2 2006.197.08:17:09.35#ibcon#read 6, iclass 15, count 2 2006.197.08:17:09.35#ibcon#end of sib2, iclass 15, count 2 2006.197.08:17:09.35#ibcon#*mode == 0, iclass 15, count 2 2006.197.08:17:09.35#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.197.08:17:09.35#ibcon#[25=AT06-06\r\n] 2006.197.08:17:09.35#ibcon#*before write, iclass 15, count 2 2006.197.08:17:09.35#ibcon#enter sib2, iclass 15, count 2 2006.197.08:17:09.35#ibcon#flushed, iclass 15, count 2 2006.197.08:17:09.35#ibcon#about to write, iclass 15, count 2 2006.197.08:17:09.35#ibcon#wrote, iclass 15, count 2 2006.197.08:17:09.35#ibcon#about to read 3, iclass 15, count 2 2006.197.08:17:09.38#ibcon#read 3, iclass 15, count 2 2006.197.08:17:09.38#ibcon#about to read 4, iclass 15, count 2 2006.197.08:17:09.38#ibcon#read 4, iclass 15, count 2 2006.197.08:17:09.38#ibcon#about to read 5, iclass 15, count 2 2006.197.08:17:09.38#ibcon#read 5, iclass 15, count 2 2006.197.08:17:09.38#ibcon#about to read 6, iclass 15, count 2 2006.197.08:17:09.38#ibcon#read 6, iclass 15, count 2 2006.197.08:17:09.38#ibcon#end of sib2, iclass 15, count 2 2006.197.08:17:09.38#ibcon#*after write, iclass 15, count 2 2006.197.08:17:09.38#ibcon#*before return 0, iclass 15, count 2 2006.197.08:17:09.38#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.197.08:17:09.38#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.197.08:17:09.38#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.197.08:17:09.38#ibcon#ireg 7 cls_cnt 0 2006.197.08:17:09.38#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.197.08:17:09.50#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.197.08:17:09.50#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.197.08:17:09.50#ibcon#enter wrdev, iclass 15, count 0 2006.197.08:17:09.50#ibcon#first serial, iclass 15, count 0 2006.197.08:17:09.50#ibcon#enter sib2, iclass 15, count 0 2006.197.08:17:09.50#ibcon#flushed, iclass 15, count 0 2006.197.08:17:09.50#ibcon#about to write, iclass 15, count 0 2006.197.08:17:09.50#ibcon#wrote, iclass 15, count 0 2006.197.08:17:09.50#ibcon#about to read 3, iclass 15, count 0 2006.197.08:17:09.52#ibcon#read 3, iclass 15, count 0 2006.197.08:17:09.52#ibcon#about to read 4, iclass 15, count 0 2006.197.08:17:09.52#ibcon#read 4, iclass 15, count 0 2006.197.08:17:09.52#ibcon#about to read 5, iclass 15, count 0 2006.197.08:17:09.52#ibcon#read 5, iclass 15, count 0 2006.197.08:17:09.52#ibcon#about to read 6, iclass 15, count 0 2006.197.08:17:09.52#ibcon#read 6, iclass 15, count 0 2006.197.08:17:09.52#ibcon#end of sib2, iclass 15, count 0 2006.197.08:17:09.52#ibcon#*mode == 0, iclass 15, count 0 2006.197.08:17:09.52#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.197.08:17:09.52#ibcon#[25=USB\r\n] 2006.197.08:17:09.52#ibcon#*before write, iclass 15, count 0 2006.197.08:17:09.52#ibcon#enter sib2, iclass 15, count 0 2006.197.08:17:09.52#ibcon#flushed, iclass 15, count 0 2006.197.08:17:09.52#ibcon#about to write, iclass 15, count 0 2006.197.08:17:09.52#ibcon#wrote, iclass 15, count 0 2006.197.08:17:09.52#ibcon#about to read 3, iclass 15, count 0 2006.197.08:17:09.55#ibcon#read 3, iclass 15, count 0 2006.197.08:17:09.55#ibcon#about to read 4, iclass 15, count 0 2006.197.08:17:09.55#ibcon#read 4, iclass 15, count 0 2006.197.08:17:09.55#ibcon#about to read 5, iclass 15, count 0 2006.197.08:17:09.55#ibcon#read 5, iclass 15, count 0 2006.197.08:17:09.55#ibcon#about to read 6, iclass 15, count 0 2006.197.08:17:09.55#ibcon#read 6, iclass 15, count 0 2006.197.08:17:09.55#ibcon#end of sib2, iclass 15, count 0 2006.197.08:17:09.55#ibcon#*after write, iclass 15, count 0 2006.197.08:17:09.55#ibcon#*before return 0, iclass 15, count 0 2006.197.08:17:09.55#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.197.08:17:09.55#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.197.08:17:09.55#ibcon#about to clear, iclass 15 cls_cnt 0 2006.197.08:17:09.55#ibcon#cleared, iclass 15 cls_cnt 0 2006.197.08:17:09.55$vc4f8/valo=7,832.99 2006.197.08:17:09.55#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.197.08:17:09.55#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.197.08:17:09.55#ibcon#ireg 17 cls_cnt 0 2006.197.08:17:09.55#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.197.08:17:09.55#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.197.08:17:09.55#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.197.08:17:09.55#ibcon#enter wrdev, iclass 17, count 0 2006.197.08:17:09.55#ibcon#first serial, iclass 17, count 0 2006.197.08:17:09.55#ibcon#enter sib2, iclass 17, count 0 2006.197.08:17:09.55#ibcon#flushed, iclass 17, count 0 2006.197.08:17:09.55#ibcon#about to write, iclass 17, count 0 2006.197.08:17:09.55#ibcon#wrote, iclass 17, count 0 2006.197.08:17:09.55#ibcon#about to read 3, iclass 17, count 0 2006.197.08:17:09.57#ibcon#read 3, iclass 17, count 0 2006.197.08:17:09.57#ibcon#about to read 4, iclass 17, count 0 2006.197.08:17:09.57#ibcon#read 4, iclass 17, count 0 2006.197.08:17:09.57#ibcon#about to read 5, iclass 17, count 0 2006.197.08:17:09.57#ibcon#read 5, iclass 17, count 0 2006.197.08:17:09.57#ibcon#about to read 6, iclass 17, count 0 2006.197.08:17:09.57#ibcon#read 6, iclass 17, count 0 2006.197.08:17:09.57#ibcon#end of sib2, iclass 17, count 0 2006.197.08:17:09.57#ibcon#*mode == 0, iclass 17, count 0 2006.197.08:17:09.57#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.197.08:17:09.57#ibcon#[26=FRQ=07,832.99\r\n] 2006.197.08:17:09.57#ibcon#*before write, iclass 17, count 0 2006.197.08:17:09.57#ibcon#enter sib2, iclass 17, count 0 2006.197.08:17:09.57#ibcon#flushed, iclass 17, count 0 2006.197.08:17:09.57#ibcon#about to write, iclass 17, count 0 2006.197.08:17:09.57#ibcon#wrote, iclass 17, count 0 2006.197.08:17:09.57#ibcon#about to read 3, iclass 17, count 0 2006.197.08:17:09.61#ibcon#read 3, iclass 17, count 0 2006.197.08:17:09.61#ibcon#about to read 4, iclass 17, count 0 2006.197.08:17:09.61#ibcon#read 4, iclass 17, count 0 2006.197.08:17:09.61#ibcon#about to read 5, iclass 17, count 0 2006.197.08:17:09.61#ibcon#read 5, iclass 17, count 0 2006.197.08:17:09.61#ibcon#about to read 6, iclass 17, count 0 2006.197.08:17:09.61#ibcon#read 6, iclass 17, count 0 2006.197.08:17:09.61#ibcon#end of sib2, iclass 17, count 0 2006.197.08:17:09.61#ibcon#*after write, iclass 17, count 0 2006.197.08:17:09.61#ibcon#*before return 0, iclass 17, count 0 2006.197.08:17:09.61#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.197.08:17:09.61#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.197.08:17:09.61#ibcon#about to clear, iclass 17 cls_cnt 0 2006.197.08:17:09.61#ibcon#cleared, iclass 17 cls_cnt 0 2006.197.08:17:09.61$vc4f8/va=7,6 2006.197.08:17:09.61#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.197.08:17:09.61#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.197.08:17:09.61#ibcon#ireg 11 cls_cnt 2 2006.197.08:17:09.61#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.197.08:17:09.67#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.197.08:17:09.67#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.197.08:17:09.67#ibcon#enter wrdev, iclass 19, count 2 2006.197.08:17:09.67#ibcon#first serial, iclass 19, count 2 2006.197.08:17:09.67#ibcon#enter sib2, iclass 19, count 2 2006.197.08:17:09.67#ibcon#flushed, iclass 19, count 2 2006.197.08:17:09.67#ibcon#about to write, iclass 19, count 2 2006.197.08:17:09.67#ibcon#wrote, iclass 19, count 2 2006.197.08:17:09.67#ibcon#about to read 3, iclass 19, count 2 2006.197.08:17:09.69#ibcon#read 3, iclass 19, count 2 2006.197.08:17:09.69#ibcon#about to read 4, iclass 19, count 2 2006.197.08:17:09.69#ibcon#read 4, iclass 19, count 2 2006.197.08:17:09.69#ibcon#about to read 5, iclass 19, count 2 2006.197.08:17:09.69#ibcon#read 5, iclass 19, count 2 2006.197.08:17:09.69#ibcon#about to read 6, iclass 19, count 2 2006.197.08:17:09.69#ibcon#read 6, iclass 19, count 2 2006.197.08:17:09.69#ibcon#end of sib2, iclass 19, count 2 2006.197.08:17:09.69#ibcon#*mode == 0, iclass 19, count 2 2006.197.08:17:09.69#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.197.08:17:09.69#ibcon#[25=AT07-06\r\n] 2006.197.08:17:09.69#ibcon#*before write, iclass 19, count 2 2006.197.08:17:09.69#ibcon#enter sib2, iclass 19, count 2 2006.197.08:17:09.69#ibcon#flushed, iclass 19, count 2 2006.197.08:17:09.69#ibcon#about to write, iclass 19, count 2 2006.197.08:17:09.69#ibcon#wrote, iclass 19, count 2 2006.197.08:17:09.69#ibcon#about to read 3, iclass 19, count 2 2006.197.08:17:09.72#ibcon#read 3, iclass 19, count 2 2006.197.08:17:09.72#ibcon#about to read 4, iclass 19, count 2 2006.197.08:17:09.72#ibcon#read 4, iclass 19, count 2 2006.197.08:17:09.72#ibcon#about to read 5, iclass 19, count 2 2006.197.08:17:09.72#ibcon#read 5, iclass 19, count 2 2006.197.08:17:09.72#ibcon#about to read 6, iclass 19, count 2 2006.197.08:17:09.72#ibcon#read 6, iclass 19, count 2 2006.197.08:17:09.72#ibcon#end of sib2, iclass 19, count 2 2006.197.08:17:09.72#ibcon#*after write, iclass 19, count 2 2006.197.08:17:09.72#ibcon#*before return 0, iclass 19, count 2 2006.197.08:17:09.72#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.197.08:17:09.72#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.197.08:17:09.72#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.197.08:17:09.72#ibcon#ireg 7 cls_cnt 0 2006.197.08:17:09.72#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.197.08:17:09.84#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.197.08:17:09.84#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.197.08:17:09.84#ibcon#enter wrdev, iclass 19, count 0 2006.197.08:17:09.84#ibcon#first serial, iclass 19, count 0 2006.197.08:17:09.84#ibcon#enter sib2, iclass 19, count 0 2006.197.08:17:09.84#ibcon#flushed, iclass 19, count 0 2006.197.08:17:09.84#ibcon#about to write, iclass 19, count 0 2006.197.08:17:09.84#ibcon#wrote, iclass 19, count 0 2006.197.08:17:09.84#ibcon#about to read 3, iclass 19, count 0 2006.197.08:17:09.86#ibcon#read 3, iclass 19, count 0 2006.197.08:17:09.86#ibcon#about to read 4, iclass 19, count 0 2006.197.08:17:09.86#ibcon#read 4, iclass 19, count 0 2006.197.08:17:09.86#ibcon#about to read 5, iclass 19, count 0 2006.197.08:17:09.86#ibcon#read 5, iclass 19, count 0 2006.197.08:17:09.86#ibcon#about to read 6, iclass 19, count 0 2006.197.08:17:09.86#ibcon#read 6, iclass 19, count 0 2006.197.08:17:09.86#ibcon#end of sib2, iclass 19, count 0 2006.197.08:17:09.86#ibcon#*mode == 0, iclass 19, count 0 2006.197.08:17:09.86#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.197.08:17:09.86#ibcon#[25=USB\r\n] 2006.197.08:17:09.86#ibcon#*before write, iclass 19, count 0 2006.197.08:17:09.86#ibcon#enter sib2, iclass 19, count 0 2006.197.08:17:09.86#ibcon#flushed, iclass 19, count 0 2006.197.08:17:09.86#ibcon#about to write, iclass 19, count 0 2006.197.08:17:09.86#ibcon#wrote, iclass 19, count 0 2006.197.08:17:09.86#ibcon#about to read 3, iclass 19, count 0 2006.197.08:17:09.89#ibcon#read 3, iclass 19, count 0 2006.197.08:17:09.89#ibcon#about to read 4, iclass 19, count 0 2006.197.08:17:09.89#ibcon#read 4, iclass 19, count 0 2006.197.08:17:09.89#ibcon#about to read 5, iclass 19, count 0 2006.197.08:17:09.89#ibcon#read 5, iclass 19, count 0 2006.197.08:17:09.89#ibcon#about to read 6, iclass 19, count 0 2006.197.08:17:09.89#ibcon#read 6, iclass 19, count 0 2006.197.08:17:09.89#ibcon#end of sib2, iclass 19, count 0 2006.197.08:17:09.89#ibcon#*after write, iclass 19, count 0 2006.197.08:17:09.89#ibcon#*before return 0, iclass 19, count 0 2006.197.08:17:09.89#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.197.08:17:09.89#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.197.08:17:09.89#ibcon#about to clear, iclass 19 cls_cnt 0 2006.197.08:17:09.89#ibcon#cleared, iclass 19 cls_cnt 0 2006.197.08:17:09.89$vc4f8/valo=8,852.99 2006.197.08:17:09.89#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.197.08:17:09.89#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.197.08:17:09.89#ibcon#ireg 17 cls_cnt 0 2006.197.08:17:09.89#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.197.08:17:09.89#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.197.08:17:09.89#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.197.08:17:09.89#ibcon#enter wrdev, iclass 21, count 0 2006.197.08:17:09.89#ibcon#first serial, iclass 21, count 0 2006.197.08:17:09.89#ibcon#enter sib2, iclass 21, count 0 2006.197.08:17:09.89#ibcon#flushed, iclass 21, count 0 2006.197.08:17:09.89#ibcon#about to write, iclass 21, count 0 2006.197.08:17:09.89#ibcon#wrote, iclass 21, count 0 2006.197.08:17:09.89#ibcon#about to read 3, iclass 21, count 0 2006.197.08:17:09.91#ibcon#read 3, iclass 21, count 0 2006.197.08:17:09.91#ibcon#about to read 4, iclass 21, count 0 2006.197.08:17:09.91#ibcon#read 4, iclass 21, count 0 2006.197.08:17:09.91#ibcon#about to read 5, iclass 21, count 0 2006.197.08:17:09.91#ibcon#read 5, iclass 21, count 0 2006.197.08:17:09.91#ibcon#about to read 6, iclass 21, count 0 2006.197.08:17:09.91#ibcon#read 6, iclass 21, count 0 2006.197.08:17:09.91#ibcon#end of sib2, iclass 21, count 0 2006.197.08:17:09.91#ibcon#*mode == 0, iclass 21, count 0 2006.197.08:17:09.91#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.197.08:17:09.91#ibcon#[26=FRQ=08,852.99\r\n] 2006.197.08:17:09.91#ibcon#*before write, iclass 21, count 0 2006.197.08:17:09.91#ibcon#enter sib2, iclass 21, count 0 2006.197.08:17:09.91#ibcon#flushed, iclass 21, count 0 2006.197.08:17:09.91#ibcon#about to write, iclass 21, count 0 2006.197.08:17:09.91#ibcon#wrote, iclass 21, count 0 2006.197.08:17:09.91#ibcon#about to read 3, iclass 21, count 0 2006.197.08:17:09.95#ibcon#read 3, iclass 21, count 0 2006.197.08:17:09.95#ibcon#about to read 4, iclass 21, count 0 2006.197.08:17:09.95#ibcon#read 4, iclass 21, count 0 2006.197.08:17:09.95#ibcon#about to read 5, iclass 21, count 0 2006.197.08:17:09.95#ibcon#read 5, iclass 21, count 0 2006.197.08:17:09.95#ibcon#about to read 6, iclass 21, count 0 2006.197.08:17:09.95#ibcon#read 6, iclass 21, count 0 2006.197.08:17:09.95#ibcon#end of sib2, iclass 21, count 0 2006.197.08:17:09.95#ibcon#*after write, iclass 21, count 0 2006.197.08:17:09.95#ibcon#*before return 0, iclass 21, count 0 2006.197.08:17:09.95#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.197.08:17:09.95#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.197.08:17:09.95#ibcon#about to clear, iclass 21 cls_cnt 0 2006.197.08:17:09.95#ibcon#cleared, iclass 21 cls_cnt 0 2006.197.08:17:09.95$vc4f8/va=8,7 2006.197.08:17:09.95#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.197.08:17:09.95#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.197.08:17:09.95#ibcon#ireg 11 cls_cnt 2 2006.197.08:17:09.95#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.197.08:17:10.01#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.197.08:17:10.01#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.197.08:17:10.01#ibcon#enter wrdev, iclass 23, count 2 2006.197.08:17:10.01#ibcon#first serial, iclass 23, count 2 2006.197.08:17:10.01#ibcon#enter sib2, iclass 23, count 2 2006.197.08:17:10.01#ibcon#flushed, iclass 23, count 2 2006.197.08:17:10.01#ibcon#about to write, iclass 23, count 2 2006.197.08:17:10.01#ibcon#wrote, iclass 23, count 2 2006.197.08:17:10.01#ibcon#about to read 3, iclass 23, count 2 2006.197.08:17:10.03#ibcon#read 3, iclass 23, count 2 2006.197.08:17:10.03#ibcon#about to read 4, iclass 23, count 2 2006.197.08:17:10.03#ibcon#read 4, iclass 23, count 2 2006.197.08:17:10.03#ibcon#about to read 5, iclass 23, count 2 2006.197.08:17:10.03#ibcon#read 5, iclass 23, count 2 2006.197.08:17:10.03#ibcon#about to read 6, iclass 23, count 2 2006.197.08:17:10.03#ibcon#read 6, iclass 23, count 2 2006.197.08:17:10.03#ibcon#end of sib2, iclass 23, count 2 2006.197.08:17:10.03#ibcon#*mode == 0, iclass 23, count 2 2006.197.08:17:10.03#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.197.08:17:10.03#ibcon#[25=AT08-07\r\n] 2006.197.08:17:10.03#ibcon#*before write, iclass 23, count 2 2006.197.08:17:10.03#ibcon#enter sib2, iclass 23, count 2 2006.197.08:17:10.03#ibcon#flushed, iclass 23, count 2 2006.197.08:17:10.03#ibcon#about to write, iclass 23, count 2 2006.197.08:17:10.03#ibcon#wrote, iclass 23, count 2 2006.197.08:17:10.03#ibcon#about to read 3, iclass 23, count 2 2006.197.08:17:10.06#ibcon#read 3, iclass 23, count 2 2006.197.08:17:10.06#ibcon#about to read 4, iclass 23, count 2 2006.197.08:17:10.06#ibcon#read 4, iclass 23, count 2 2006.197.08:17:10.06#ibcon#about to read 5, iclass 23, count 2 2006.197.08:17:10.06#ibcon#read 5, iclass 23, count 2 2006.197.08:17:10.06#ibcon#about to read 6, iclass 23, count 2 2006.197.08:17:10.06#ibcon#read 6, iclass 23, count 2 2006.197.08:17:10.06#ibcon#end of sib2, iclass 23, count 2 2006.197.08:17:10.06#ibcon#*after write, iclass 23, count 2 2006.197.08:17:10.06#ibcon#*before return 0, iclass 23, count 2 2006.197.08:17:10.06#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.197.08:17:10.06#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.197.08:17:10.06#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.197.08:17:10.06#ibcon#ireg 7 cls_cnt 0 2006.197.08:17:10.06#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.197.08:17:10.18#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.197.08:17:10.18#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.197.08:17:10.18#ibcon#enter wrdev, iclass 23, count 0 2006.197.08:17:10.18#ibcon#first serial, iclass 23, count 0 2006.197.08:17:10.18#ibcon#enter sib2, iclass 23, count 0 2006.197.08:17:10.18#ibcon#flushed, iclass 23, count 0 2006.197.08:17:10.18#ibcon#about to write, iclass 23, count 0 2006.197.08:17:10.18#ibcon#wrote, iclass 23, count 0 2006.197.08:17:10.18#ibcon#about to read 3, iclass 23, count 0 2006.197.08:17:10.20#ibcon#read 3, iclass 23, count 0 2006.197.08:17:10.20#ibcon#about to read 4, iclass 23, count 0 2006.197.08:17:10.20#ibcon#read 4, iclass 23, count 0 2006.197.08:17:10.20#ibcon#about to read 5, iclass 23, count 0 2006.197.08:17:10.20#ibcon#read 5, iclass 23, count 0 2006.197.08:17:10.20#ibcon#about to read 6, iclass 23, count 0 2006.197.08:17:10.20#ibcon#read 6, iclass 23, count 0 2006.197.08:17:10.20#ibcon#end of sib2, iclass 23, count 0 2006.197.08:17:10.20#ibcon#*mode == 0, iclass 23, count 0 2006.197.08:17:10.20#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.197.08:17:10.20#ibcon#[25=USB\r\n] 2006.197.08:17:10.20#ibcon#*before write, iclass 23, count 0 2006.197.08:17:10.20#ibcon#enter sib2, iclass 23, count 0 2006.197.08:17:10.20#ibcon#flushed, iclass 23, count 0 2006.197.08:17:10.20#ibcon#about to write, iclass 23, count 0 2006.197.08:17:10.20#ibcon#wrote, iclass 23, count 0 2006.197.08:17:10.20#ibcon#about to read 3, iclass 23, count 0 2006.197.08:17:10.23#ibcon#read 3, iclass 23, count 0 2006.197.08:17:10.23#ibcon#about to read 4, iclass 23, count 0 2006.197.08:17:10.23#ibcon#read 4, iclass 23, count 0 2006.197.08:17:10.23#ibcon#about to read 5, iclass 23, count 0 2006.197.08:17:10.23#ibcon#read 5, iclass 23, count 0 2006.197.08:17:10.23#ibcon#about to read 6, iclass 23, count 0 2006.197.08:17:10.23#ibcon#read 6, iclass 23, count 0 2006.197.08:17:10.23#ibcon#end of sib2, iclass 23, count 0 2006.197.08:17:10.23#ibcon#*after write, iclass 23, count 0 2006.197.08:17:10.23#ibcon#*before return 0, iclass 23, count 0 2006.197.08:17:10.23#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.197.08:17:10.23#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.197.08:17:10.23#ibcon#about to clear, iclass 23 cls_cnt 0 2006.197.08:17:10.23#ibcon#cleared, iclass 23 cls_cnt 0 2006.197.08:17:10.23$vc4f8/vblo=1,632.99 2006.197.08:17:10.23#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.197.08:17:10.23#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.197.08:17:10.23#ibcon#ireg 17 cls_cnt 0 2006.197.08:17:10.23#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.197.08:17:10.23#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.197.08:17:10.23#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.197.08:17:10.23#ibcon#enter wrdev, iclass 25, count 0 2006.197.08:17:10.23#ibcon#first serial, iclass 25, count 0 2006.197.08:17:10.23#ibcon#enter sib2, iclass 25, count 0 2006.197.08:17:10.23#ibcon#flushed, iclass 25, count 0 2006.197.08:17:10.23#ibcon#about to write, iclass 25, count 0 2006.197.08:17:10.23#ibcon#wrote, iclass 25, count 0 2006.197.08:17:10.23#ibcon#about to read 3, iclass 25, count 0 2006.197.08:17:10.25#ibcon#read 3, iclass 25, count 0 2006.197.08:17:10.25#ibcon#about to read 4, iclass 25, count 0 2006.197.08:17:10.25#ibcon#read 4, iclass 25, count 0 2006.197.08:17:10.25#ibcon#about to read 5, iclass 25, count 0 2006.197.08:17:10.25#ibcon#read 5, iclass 25, count 0 2006.197.08:17:10.25#ibcon#about to read 6, iclass 25, count 0 2006.197.08:17:10.25#ibcon#read 6, iclass 25, count 0 2006.197.08:17:10.25#ibcon#end of sib2, iclass 25, count 0 2006.197.08:17:10.25#ibcon#*mode == 0, iclass 25, count 0 2006.197.08:17:10.25#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.197.08:17:10.25#ibcon#[28=FRQ=01,632.99\r\n] 2006.197.08:17:10.25#ibcon#*before write, iclass 25, count 0 2006.197.08:17:10.25#ibcon#enter sib2, iclass 25, count 0 2006.197.08:17:10.25#ibcon#flushed, iclass 25, count 0 2006.197.08:17:10.25#ibcon#about to write, iclass 25, count 0 2006.197.08:17:10.25#ibcon#wrote, iclass 25, count 0 2006.197.08:17:10.25#ibcon#about to read 3, iclass 25, count 0 2006.197.08:17:10.29#ibcon#read 3, iclass 25, count 0 2006.197.08:17:10.29#ibcon#about to read 4, iclass 25, count 0 2006.197.08:17:10.29#ibcon#read 4, iclass 25, count 0 2006.197.08:17:10.29#ibcon#about to read 5, iclass 25, count 0 2006.197.08:17:10.29#ibcon#read 5, iclass 25, count 0 2006.197.08:17:10.29#ibcon#about to read 6, iclass 25, count 0 2006.197.08:17:10.29#ibcon#read 6, iclass 25, count 0 2006.197.08:17:10.29#ibcon#end of sib2, iclass 25, count 0 2006.197.08:17:10.29#ibcon#*after write, iclass 25, count 0 2006.197.08:17:10.29#ibcon#*before return 0, iclass 25, count 0 2006.197.08:17:10.29#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.197.08:17:10.29#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.197.08:17:10.29#ibcon#about to clear, iclass 25 cls_cnt 0 2006.197.08:17:10.29#ibcon#cleared, iclass 25 cls_cnt 0 2006.197.08:17:10.29$vc4f8/vb=1,4 2006.197.08:17:10.29#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.197.08:17:10.29#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.197.08:17:10.29#ibcon#ireg 11 cls_cnt 2 2006.197.08:17:10.29#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.197.08:17:10.29#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.197.08:17:10.29#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.197.08:17:10.29#ibcon#enter wrdev, iclass 27, count 2 2006.197.08:17:10.29#ibcon#first serial, iclass 27, count 2 2006.197.08:17:10.29#ibcon#enter sib2, iclass 27, count 2 2006.197.08:17:10.29#ibcon#flushed, iclass 27, count 2 2006.197.08:17:10.29#ibcon#about to write, iclass 27, count 2 2006.197.08:17:10.29#ibcon#wrote, iclass 27, count 2 2006.197.08:17:10.29#ibcon#about to read 3, iclass 27, count 2 2006.197.08:17:10.31#ibcon#read 3, iclass 27, count 2 2006.197.08:17:10.31#ibcon#about to read 4, iclass 27, count 2 2006.197.08:17:10.31#ibcon#read 4, iclass 27, count 2 2006.197.08:17:10.31#ibcon#about to read 5, iclass 27, count 2 2006.197.08:17:10.31#ibcon#read 5, iclass 27, count 2 2006.197.08:17:10.31#ibcon#about to read 6, iclass 27, count 2 2006.197.08:17:10.31#ibcon#read 6, iclass 27, count 2 2006.197.08:17:10.31#ibcon#end of sib2, iclass 27, count 2 2006.197.08:17:10.31#ibcon#*mode == 0, iclass 27, count 2 2006.197.08:17:10.31#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.197.08:17:10.31#ibcon#[27=AT01-04\r\n] 2006.197.08:17:10.31#ibcon#*before write, iclass 27, count 2 2006.197.08:17:10.31#ibcon#enter sib2, iclass 27, count 2 2006.197.08:17:10.31#ibcon#flushed, iclass 27, count 2 2006.197.08:17:10.31#ibcon#about to write, iclass 27, count 2 2006.197.08:17:10.31#ibcon#wrote, iclass 27, count 2 2006.197.08:17:10.31#ibcon#about to read 3, iclass 27, count 2 2006.197.08:17:10.34#ibcon#read 3, iclass 27, count 2 2006.197.08:17:10.34#ibcon#about to read 4, iclass 27, count 2 2006.197.08:17:10.34#ibcon#read 4, iclass 27, count 2 2006.197.08:17:10.34#ibcon#about to read 5, iclass 27, count 2 2006.197.08:17:10.34#ibcon#read 5, iclass 27, count 2 2006.197.08:17:10.34#ibcon#about to read 6, iclass 27, count 2 2006.197.08:17:10.34#ibcon#read 6, iclass 27, count 2 2006.197.08:17:10.34#ibcon#end of sib2, iclass 27, count 2 2006.197.08:17:10.34#ibcon#*after write, iclass 27, count 2 2006.197.08:17:10.34#ibcon#*before return 0, iclass 27, count 2 2006.197.08:17:10.34#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.197.08:17:10.34#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.197.08:17:10.34#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.197.08:17:10.34#ibcon#ireg 7 cls_cnt 0 2006.197.08:17:10.34#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.197.08:17:10.46#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.197.08:17:10.46#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.197.08:17:10.46#ibcon#enter wrdev, iclass 27, count 0 2006.197.08:17:10.46#ibcon#first serial, iclass 27, count 0 2006.197.08:17:10.46#ibcon#enter sib2, iclass 27, count 0 2006.197.08:17:10.46#ibcon#flushed, iclass 27, count 0 2006.197.08:17:10.46#ibcon#about to write, iclass 27, count 0 2006.197.08:17:10.46#ibcon#wrote, iclass 27, count 0 2006.197.08:17:10.46#ibcon#about to read 3, iclass 27, count 0 2006.197.08:17:10.48#ibcon#read 3, iclass 27, count 0 2006.197.08:17:10.48#ibcon#about to read 4, iclass 27, count 0 2006.197.08:17:10.48#ibcon#read 4, iclass 27, count 0 2006.197.08:17:10.48#ibcon#about to read 5, iclass 27, count 0 2006.197.08:17:10.48#ibcon#read 5, iclass 27, count 0 2006.197.08:17:10.48#ibcon#about to read 6, iclass 27, count 0 2006.197.08:17:10.48#ibcon#read 6, iclass 27, count 0 2006.197.08:17:10.48#ibcon#end of sib2, iclass 27, count 0 2006.197.08:17:10.48#ibcon#*mode == 0, iclass 27, count 0 2006.197.08:17:10.48#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.197.08:17:10.48#ibcon#[27=USB\r\n] 2006.197.08:17:10.48#ibcon#*before write, iclass 27, count 0 2006.197.08:17:10.48#ibcon#enter sib2, iclass 27, count 0 2006.197.08:17:10.48#ibcon#flushed, iclass 27, count 0 2006.197.08:17:10.48#ibcon#about to write, iclass 27, count 0 2006.197.08:17:10.48#ibcon#wrote, iclass 27, count 0 2006.197.08:17:10.48#ibcon#about to read 3, iclass 27, count 0 2006.197.08:17:10.51#ibcon#read 3, iclass 27, count 0 2006.197.08:17:10.51#ibcon#about to read 4, iclass 27, count 0 2006.197.08:17:10.51#ibcon#read 4, iclass 27, count 0 2006.197.08:17:10.51#ibcon#about to read 5, iclass 27, count 0 2006.197.08:17:10.51#ibcon#read 5, iclass 27, count 0 2006.197.08:17:10.51#ibcon#about to read 6, iclass 27, count 0 2006.197.08:17:10.51#ibcon#read 6, iclass 27, count 0 2006.197.08:17:10.51#ibcon#end of sib2, iclass 27, count 0 2006.197.08:17:10.51#ibcon#*after write, iclass 27, count 0 2006.197.08:17:10.51#ibcon#*before return 0, iclass 27, count 0 2006.197.08:17:10.51#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.197.08:17:10.51#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.197.08:17:10.51#ibcon#about to clear, iclass 27 cls_cnt 0 2006.197.08:17:10.51#ibcon#cleared, iclass 27 cls_cnt 0 2006.197.08:17:10.51$vc4f8/vblo=2,640.99 2006.197.08:17:10.51#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.197.08:17:10.51#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.197.08:17:10.51#ibcon#ireg 17 cls_cnt 0 2006.197.08:17:10.51#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.197.08:17:10.51#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.197.08:17:10.51#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.197.08:17:10.51#ibcon#enter wrdev, iclass 29, count 0 2006.197.08:17:10.51#ibcon#first serial, iclass 29, count 0 2006.197.08:17:10.51#ibcon#enter sib2, iclass 29, count 0 2006.197.08:17:10.51#ibcon#flushed, iclass 29, count 0 2006.197.08:17:10.51#ibcon#about to write, iclass 29, count 0 2006.197.08:17:10.51#ibcon#wrote, iclass 29, count 0 2006.197.08:17:10.51#ibcon#about to read 3, iclass 29, count 0 2006.197.08:17:10.53#ibcon#read 3, iclass 29, count 0 2006.197.08:17:10.53#ibcon#about to read 4, iclass 29, count 0 2006.197.08:17:10.53#ibcon#read 4, iclass 29, count 0 2006.197.08:17:10.53#ibcon#about to read 5, iclass 29, count 0 2006.197.08:17:10.53#ibcon#read 5, iclass 29, count 0 2006.197.08:17:10.53#ibcon#about to read 6, iclass 29, count 0 2006.197.08:17:10.53#ibcon#read 6, iclass 29, count 0 2006.197.08:17:10.53#ibcon#end of sib2, iclass 29, count 0 2006.197.08:17:10.53#ibcon#*mode == 0, iclass 29, count 0 2006.197.08:17:10.53#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.197.08:17:10.53#ibcon#[28=FRQ=02,640.99\r\n] 2006.197.08:17:10.53#ibcon#*before write, iclass 29, count 0 2006.197.08:17:10.53#ibcon#enter sib2, iclass 29, count 0 2006.197.08:17:10.53#ibcon#flushed, iclass 29, count 0 2006.197.08:17:10.53#ibcon#about to write, iclass 29, count 0 2006.197.08:17:10.53#ibcon#wrote, iclass 29, count 0 2006.197.08:17:10.53#ibcon#about to read 3, iclass 29, count 0 2006.197.08:17:10.57#ibcon#read 3, iclass 29, count 0 2006.197.08:17:10.57#ibcon#about to read 4, iclass 29, count 0 2006.197.08:17:10.57#ibcon#read 4, iclass 29, count 0 2006.197.08:17:10.57#ibcon#about to read 5, iclass 29, count 0 2006.197.08:17:10.57#ibcon#read 5, iclass 29, count 0 2006.197.08:17:10.57#ibcon#about to read 6, iclass 29, count 0 2006.197.08:17:10.57#ibcon#read 6, iclass 29, count 0 2006.197.08:17:10.57#ibcon#end of sib2, iclass 29, count 0 2006.197.08:17:10.57#ibcon#*after write, iclass 29, count 0 2006.197.08:17:10.57#ibcon#*before return 0, iclass 29, count 0 2006.197.08:17:10.57#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.197.08:17:10.57#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.197.08:17:10.57#ibcon#about to clear, iclass 29 cls_cnt 0 2006.197.08:17:10.57#ibcon#cleared, iclass 29 cls_cnt 0 2006.197.08:17:10.57$vc4f8/vb=2,4 2006.197.08:17:10.57#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.197.08:17:10.57#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.197.08:17:10.57#ibcon#ireg 11 cls_cnt 2 2006.197.08:17:10.57#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.197.08:17:10.63#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.197.08:17:10.63#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.197.08:17:10.63#ibcon#enter wrdev, iclass 31, count 2 2006.197.08:17:10.63#ibcon#first serial, iclass 31, count 2 2006.197.08:17:10.63#ibcon#enter sib2, iclass 31, count 2 2006.197.08:17:10.63#ibcon#flushed, iclass 31, count 2 2006.197.08:17:10.63#ibcon#about to write, iclass 31, count 2 2006.197.08:17:10.63#ibcon#wrote, iclass 31, count 2 2006.197.08:17:10.63#ibcon#about to read 3, iclass 31, count 2 2006.197.08:17:10.65#ibcon#read 3, iclass 31, count 2 2006.197.08:17:10.65#ibcon#about to read 4, iclass 31, count 2 2006.197.08:17:10.65#ibcon#read 4, iclass 31, count 2 2006.197.08:17:10.65#ibcon#about to read 5, iclass 31, count 2 2006.197.08:17:10.65#ibcon#read 5, iclass 31, count 2 2006.197.08:17:10.65#ibcon#about to read 6, iclass 31, count 2 2006.197.08:17:10.65#ibcon#read 6, iclass 31, count 2 2006.197.08:17:10.65#ibcon#end of sib2, iclass 31, count 2 2006.197.08:17:10.65#ibcon#*mode == 0, iclass 31, count 2 2006.197.08:17:10.65#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.197.08:17:10.65#ibcon#[27=AT02-04\r\n] 2006.197.08:17:10.65#ibcon#*before write, iclass 31, count 2 2006.197.08:17:10.65#ibcon#enter sib2, iclass 31, count 2 2006.197.08:17:10.65#ibcon#flushed, iclass 31, count 2 2006.197.08:17:10.65#ibcon#about to write, iclass 31, count 2 2006.197.08:17:10.65#ibcon#wrote, iclass 31, count 2 2006.197.08:17:10.65#ibcon#about to read 3, iclass 31, count 2 2006.197.08:17:10.68#ibcon#read 3, iclass 31, count 2 2006.197.08:17:10.68#ibcon#about to read 4, iclass 31, count 2 2006.197.08:17:10.68#ibcon#read 4, iclass 31, count 2 2006.197.08:17:10.68#ibcon#about to read 5, iclass 31, count 2 2006.197.08:17:10.68#ibcon#read 5, iclass 31, count 2 2006.197.08:17:10.68#ibcon#about to read 6, iclass 31, count 2 2006.197.08:17:10.68#ibcon#read 6, iclass 31, count 2 2006.197.08:17:10.68#ibcon#end of sib2, iclass 31, count 2 2006.197.08:17:10.68#ibcon#*after write, iclass 31, count 2 2006.197.08:17:10.68#ibcon#*before return 0, iclass 31, count 2 2006.197.08:17:10.68#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.197.08:17:10.68#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.197.08:17:10.68#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.197.08:17:10.68#ibcon#ireg 7 cls_cnt 0 2006.197.08:17:10.68#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.197.08:17:10.80#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.197.08:17:10.80#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.197.08:17:10.80#ibcon#enter wrdev, iclass 31, count 0 2006.197.08:17:10.80#ibcon#first serial, iclass 31, count 0 2006.197.08:17:10.80#ibcon#enter sib2, iclass 31, count 0 2006.197.08:17:10.80#ibcon#flushed, iclass 31, count 0 2006.197.08:17:10.80#ibcon#about to write, iclass 31, count 0 2006.197.08:17:10.80#ibcon#wrote, iclass 31, count 0 2006.197.08:17:10.80#ibcon#about to read 3, iclass 31, count 0 2006.197.08:17:10.82#ibcon#read 3, iclass 31, count 0 2006.197.08:17:10.82#ibcon#about to read 4, iclass 31, count 0 2006.197.08:17:10.82#ibcon#read 4, iclass 31, count 0 2006.197.08:17:10.82#ibcon#about to read 5, iclass 31, count 0 2006.197.08:17:10.82#ibcon#read 5, iclass 31, count 0 2006.197.08:17:10.82#ibcon#about to read 6, iclass 31, count 0 2006.197.08:17:10.82#ibcon#read 6, iclass 31, count 0 2006.197.08:17:10.82#ibcon#end of sib2, iclass 31, count 0 2006.197.08:17:10.82#ibcon#*mode == 0, iclass 31, count 0 2006.197.08:17:10.82#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.197.08:17:10.82#ibcon#[27=USB\r\n] 2006.197.08:17:10.82#ibcon#*before write, iclass 31, count 0 2006.197.08:17:10.82#ibcon#enter sib2, iclass 31, count 0 2006.197.08:17:10.82#ibcon#flushed, iclass 31, count 0 2006.197.08:17:10.82#ibcon#about to write, iclass 31, count 0 2006.197.08:17:10.82#ibcon#wrote, iclass 31, count 0 2006.197.08:17:10.82#ibcon#about to read 3, iclass 31, count 0 2006.197.08:17:10.85#ibcon#read 3, iclass 31, count 0 2006.197.08:17:10.85#ibcon#about to read 4, iclass 31, count 0 2006.197.08:17:10.85#ibcon#read 4, iclass 31, count 0 2006.197.08:17:10.85#ibcon#about to read 5, iclass 31, count 0 2006.197.08:17:10.85#ibcon#read 5, iclass 31, count 0 2006.197.08:17:10.85#ibcon#about to read 6, iclass 31, count 0 2006.197.08:17:10.85#ibcon#read 6, iclass 31, count 0 2006.197.08:17:10.85#ibcon#end of sib2, iclass 31, count 0 2006.197.08:17:10.85#ibcon#*after write, iclass 31, count 0 2006.197.08:17:10.85#ibcon#*before return 0, iclass 31, count 0 2006.197.08:17:10.85#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.197.08:17:10.85#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.197.08:17:10.85#ibcon#about to clear, iclass 31 cls_cnt 0 2006.197.08:17:10.85#ibcon#cleared, iclass 31 cls_cnt 0 2006.197.08:17:10.85$vc4f8/vblo=3,656.99 2006.197.08:17:10.85#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.197.08:17:10.85#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.197.08:17:10.85#ibcon#ireg 17 cls_cnt 0 2006.197.08:17:10.85#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.197.08:17:10.85#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.197.08:17:10.85#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.197.08:17:10.85#ibcon#enter wrdev, iclass 33, count 0 2006.197.08:17:10.85#ibcon#first serial, iclass 33, count 0 2006.197.08:17:10.85#ibcon#enter sib2, iclass 33, count 0 2006.197.08:17:10.85#ibcon#flushed, iclass 33, count 0 2006.197.08:17:10.85#ibcon#about to write, iclass 33, count 0 2006.197.08:17:10.85#ibcon#wrote, iclass 33, count 0 2006.197.08:17:10.85#ibcon#about to read 3, iclass 33, count 0 2006.197.08:17:10.87#ibcon#read 3, iclass 33, count 0 2006.197.08:17:10.87#ibcon#about to read 4, iclass 33, count 0 2006.197.08:17:10.87#ibcon#read 4, iclass 33, count 0 2006.197.08:17:10.87#ibcon#about to read 5, iclass 33, count 0 2006.197.08:17:10.87#ibcon#read 5, iclass 33, count 0 2006.197.08:17:10.87#ibcon#about to read 6, iclass 33, count 0 2006.197.08:17:10.87#ibcon#read 6, iclass 33, count 0 2006.197.08:17:10.87#ibcon#end of sib2, iclass 33, count 0 2006.197.08:17:10.87#ibcon#*mode == 0, iclass 33, count 0 2006.197.08:17:10.87#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.197.08:17:10.87#ibcon#[28=FRQ=03,656.99\r\n] 2006.197.08:17:10.87#ibcon#*before write, iclass 33, count 0 2006.197.08:17:10.87#ibcon#enter sib2, iclass 33, count 0 2006.197.08:17:10.87#ibcon#flushed, iclass 33, count 0 2006.197.08:17:10.87#ibcon#about to write, iclass 33, count 0 2006.197.08:17:10.87#ibcon#wrote, iclass 33, count 0 2006.197.08:17:10.87#ibcon#about to read 3, iclass 33, count 0 2006.197.08:17:10.91#ibcon#read 3, iclass 33, count 0 2006.197.08:17:10.91#ibcon#about to read 4, iclass 33, count 0 2006.197.08:17:10.91#ibcon#read 4, iclass 33, count 0 2006.197.08:17:10.91#ibcon#about to read 5, iclass 33, count 0 2006.197.08:17:10.91#ibcon#read 5, iclass 33, count 0 2006.197.08:17:10.91#ibcon#about to read 6, iclass 33, count 0 2006.197.08:17:10.91#ibcon#read 6, iclass 33, count 0 2006.197.08:17:10.91#ibcon#end of sib2, iclass 33, count 0 2006.197.08:17:10.91#ibcon#*after write, iclass 33, count 0 2006.197.08:17:10.91#ibcon#*before return 0, iclass 33, count 0 2006.197.08:17:10.91#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.197.08:17:10.91#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.197.08:17:10.91#ibcon#about to clear, iclass 33 cls_cnt 0 2006.197.08:17:10.91#ibcon#cleared, iclass 33 cls_cnt 0 2006.197.08:17:10.91$vc4f8/vb=3,4 2006.197.08:17:10.91#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.197.08:17:10.91#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.197.08:17:10.91#ibcon#ireg 11 cls_cnt 2 2006.197.08:17:10.91#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.197.08:17:10.97#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.197.08:17:10.97#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.197.08:17:10.97#ibcon#enter wrdev, iclass 35, count 2 2006.197.08:17:10.97#ibcon#first serial, iclass 35, count 2 2006.197.08:17:10.97#ibcon#enter sib2, iclass 35, count 2 2006.197.08:17:10.97#ibcon#flushed, iclass 35, count 2 2006.197.08:17:10.97#ibcon#about to write, iclass 35, count 2 2006.197.08:17:10.97#ibcon#wrote, iclass 35, count 2 2006.197.08:17:10.97#ibcon#about to read 3, iclass 35, count 2 2006.197.08:17:10.99#ibcon#read 3, iclass 35, count 2 2006.197.08:17:10.99#ibcon#about to read 4, iclass 35, count 2 2006.197.08:17:10.99#ibcon#read 4, iclass 35, count 2 2006.197.08:17:10.99#ibcon#about to read 5, iclass 35, count 2 2006.197.08:17:10.99#ibcon#read 5, iclass 35, count 2 2006.197.08:17:10.99#ibcon#about to read 6, iclass 35, count 2 2006.197.08:17:10.99#ibcon#read 6, iclass 35, count 2 2006.197.08:17:10.99#ibcon#end of sib2, iclass 35, count 2 2006.197.08:17:10.99#ibcon#*mode == 0, iclass 35, count 2 2006.197.08:17:10.99#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.197.08:17:10.99#ibcon#[27=AT03-04\r\n] 2006.197.08:17:10.99#ibcon#*before write, iclass 35, count 2 2006.197.08:17:10.99#ibcon#enter sib2, iclass 35, count 2 2006.197.08:17:10.99#ibcon#flushed, iclass 35, count 2 2006.197.08:17:10.99#ibcon#about to write, iclass 35, count 2 2006.197.08:17:10.99#ibcon#wrote, iclass 35, count 2 2006.197.08:17:10.99#ibcon#about to read 3, iclass 35, count 2 2006.197.08:17:11.02#ibcon#read 3, iclass 35, count 2 2006.197.08:17:11.02#ibcon#about to read 4, iclass 35, count 2 2006.197.08:17:11.02#ibcon#read 4, iclass 35, count 2 2006.197.08:17:11.02#ibcon#about to read 5, iclass 35, count 2 2006.197.08:17:11.02#ibcon#read 5, iclass 35, count 2 2006.197.08:17:11.02#ibcon#about to read 6, iclass 35, count 2 2006.197.08:17:11.02#ibcon#read 6, iclass 35, count 2 2006.197.08:17:11.02#ibcon#end of sib2, iclass 35, count 2 2006.197.08:17:11.02#ibcon#*after write, iclass 35, count 2 2006.197.08:17:11.02#ibcon#*before return 0, iclass 35, count 2 2006.197.08:17:11.02#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.197.08:17:11.02#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.197.08:17:11.02#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.197.08:17:11.02#ibcon#ireg 7 cls_cnt 0 2006.197.08:17:11.02#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.197.08:17:11.14#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.197.08:17:11.14#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.197.08:17:11.14#ibcon#enter wrdev, iclass 35, count 0 2006.197.08:17:11.14#ibcon#first serial, iclass 35, count 0 2006.197.08:17:11.14#ibcon#enter sib2, iclass 35, count 0 2006.197.08:17:11.14#ibcon#flushed, iclass 35, count 0 2006.197.08:17:11.14#ibcon#about to write, iclass 35, count 0 2006.197.08:17:11.14#ibcon#wrote, iclass 35, count 0 2006.197.08:17:11.14#ibcon#about to read 3, iclass 35, count 0 2006.197.08:17:11.16#ibcon#read 3, iclass 35, count 0 2006.197.08:17:11.16#ibcon#about to read 4, iclass 35, count 0 2006.197.08:17:11.16#ibcon#read 4, iclass 35, count 0 2006.197.08:17:11.16#ibcon#about to read 5, iclass 35, count 0 2006.197.08:17:11.16#ibcon#read 5, iclass 35, count 0 2006.197.08:17:11.16#ibcon#about to read 6, iclass 35, count 0 2006.197.08:17:11.16#ibcon#read 6, iclass 35, count 0 2006.197.08:17:11.16#ibcon#end of sib2, iclass 35, count 0 2006.197.08:17:11.16#ibcon#*mode == 0, iclass 35, count 0 2006.197.08:17:11.16#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.197.08:17:11.16#ibcon#[27=USB\r\n] 2006.197.08:17:11.16#ibcon#*before write, iclass 35, count 0 2006.197.08:17:11.16#ibcon#enter sib2, iclass 35, count 0 2006.197.08:17:11.16#ibcon#flushed, iclass 35, count 0 2006.197.08:17:11.16#ibcon#about to write, iclass 35, count 0 2006.197.08:17:11.16#ibcon#wrote, iclass 35, count 0 2006.197.08:17:11.16#ibcon#about to read 3, iclass 35, count 0 2006.197.08:17:11.19#ibcon#read 3, iclass 35, count 0 2006.197.08:17:11.19#ibcon#about to read 4, iclass 35, count 0 2006.197.08:17:11.19#ibcon#read 4, iclass 35, count 0 2006.197.08:17:11.19#ibcon#about to read 5, iclass 35, count 0 2006.197.08:17:11.19#ibcon#read 5, iclass 35, count 0 2006.197.08:17:11.19#ibcon#about to read 6, iclass 35, count 0 2006.197.08:17:11.19#ibcon#read 6, iclass 35, count 0 2006.197.08:17:11.19#ibcon#end of sib2, iclass 35, count 0 2006.197.08:17:11.19#ibcon#*after write, iclass 35, count 0 2006.197.08:17:11.19#ibcon#*before return 0, iclass 35, count 0 2006.197.08:17:11.19#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.197.08:17:11.19#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.197.08:17:11.19#ibcon#about to clear, iclass 35 cls_cnt 0 2006.197.08:17:11.19#ibcon#cleared, iclass 35 cls_cnt 0 2006.197.08:17:11.19$vc4f8/vblo=4,712.99 2006.197.08:17:11.19#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.197.08:17:11.19#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.197.08:17:11.19#ibcon#ireg 17 cls_cnt 0 2006.197.08:17:11.19#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.197.08:17:11.19#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.197.08:17:11.19#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.197.08:17:11.19#ibcon#enter wrdev, iclass 37, count 0 2006.197.08:17:11.19#ibcon#first serial, iclass 37, count 0 2006.197.08:17:11.19#ibcon#enter sib2, iclass 37, count 0 2006.197.08:17:11.19#ibcon#flushed, iclass 37, count 0 2006.197.08:17:11.19#ibcon#about to write, iclass 37, count 0 2006.197.08:17:11.19#ibcon#wrote, iclass 37, count 0 2006.197.08:17:11.19#ibcon#about to read 3, iclass 37, count 0 2006.197.08:17:11.21#ibcon#read 3, iclass 37, count 0 2006.197.08:17:11.21#ibcon#about to read 4, iclass 37, count 0 2006.197.08:17:11.21#ibcon#read 4, iclass 37, count 0 2006.197.08:17:11.21#ibcon#about to read 5, iclass 37, count 0 2006.197.08:17:11.21#ibcon#read 5, iclass 37, count 0 2006.197.08:17:11.21#ibcon#about to read 6, iclass 37, count 0 2006.197.08:17:11.21#ibcon#read 6, iclass 37, count 0 2006.197.08:17:11.21#ibcon#end of sib2, iclass 37, count 0 2006.197.08:17:11.21#ibcon#*mode == 0, iclass 37, count 0 2006.197.08:17:11.21#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.197.08:17:11.21#ibcon#[28=FRQ=04,712.99\r\n] 2006.197.08:17:11.21#ibcon#*before write, iclass 37, count 0 2006.197.08:17:11.21#ibcon#enter sib2, iclass 37, count 0 2006.197.08:17:11.21#ibcon#flushed, iclass 37, count 0 2006.197.08:17:11.21#ibcon#about to write, iclass 37, count 0 2006.197.08:17:11.21#ibcon#wrote, iclass 37, count 0 2006.197.08:17:11.21#ibcon#about to read 3, iclass 37, count 0 2006.197.08:17:11.25#ibcon#read 3, iclass 37, count 0 2006.197.08:17:11.25#ibcon#about to read 4, iclass 37, count 0 2006.197.08:17:11.25#ibcon#read 4, iclass 37, count 0 2006.197.08:17:11.25#ibcon#about to read 5, iclass 37, count 0 2006.197.08:17:11.25#ibcon#read 5, iclass 37, count 0 2006.197.08:17:11.25#ibcon#about to read 6, iclass 37, count 0 2006.197.08:17:11.25#ibcon#read 6, iclass 37, count 0 2006.197.08:17:11.25#ibcon#end of sib2, iclass 37, count 0 2006.197.08:17:11.25#ibcon#*after write, iclass 37, count 0 2006.197.08:17:11.25#ibcon#*before return 0, iclass 37, count 0 2006.197.08:17:11.25#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.197.08:17:11.25#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.197.08:17:11.25#ibcon#about to clear, iclass 37 cls_cnt 0 2006.197.08:17:11.25#ibcon#cleared, iclass 37 cls_cnt 0 2006.197.08:17:11.25$vc4f8/vb=4,4 2006.197.08:17:11.25#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.197.08:17:11.25#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.197.08:17:11.25#ibcon#ireg 11 cls_cnt 2 2006.197.08:17:11.25#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.197.08:17:11.31#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.197.08:17:11.31#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.197.08:17:11.31#ibcon#enter wrdev, iclass 39, count 2 2006.197.08:17:11.31#ibcon#first serial, iclass 39, count 2 2006.197.08:17:11.31#ibcon#enter sib2, iclass 39, count 2 2006.197.08:17:11.31#ibcon#flushed, iclass 39, count 2 2006.197.08:17:11.31#ibcon#about to write, iclass 39, count 2 2006.197.08:17:11.31#ibcon#wrote, iclass 39, count 2 2006.197.08:17:11.31#ibcon#about to read 3, iclass 39, count 2 2006.197.08:17:11.33#ibcon#read 3, iclass 39, count 2 2006.197.08:17:11.33#ibcon#about to read 4, iclass 39, count 2 2006.197.08:17:11.33#ibcon#read 4, iclass 39, count 2 2006.197.08:17:11.33#ibcon#about to read 5, iclass 39, count 2 2006.197.08:17:11.33#ibcon#read 5, iclass 39, count 2 2006.197.08:17:11.33#ibcon#about to read 6, iclass 39, count 2 2006.197.08:17:11.33#ibcon#read 6, iclass 39, count 2 2006.197.08:17:11.33#ibcon#end of sib2, iclass 39, count 2 2006.197.08:17:11.33#ibcon#*mode == 0, iclass 39, count 2 2006.197.08:17:11.33#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.197.08:17:11.33#ibcon#[27=AT04-04\r\n] 2006.197.08:17:11.33#ibcon#*before write, iclass 39, count 2 2006.197.08:17:11.33#ibcon#enter sib2, iclass 39, count 2 2006.197.08:17:11.33#ibcon#flushed, iclass 39, count 2 2006.197.08:17:11.33#ibcon#about to write, iclass 39, count 2 2006.197.08:17:11.33#ibcon#wrote, iclass 39, count 2 2006.197.08:17:11.33#ibcon#about to read 3, iclass 39, count 2 2006.197.08:17:11.36#ibcon#read 3, iclass 39, count 2 2006.197.08:17:11.36#ibcon#about to read 4, iclass 39, count 2 2006.197.08:17:11.36#ibcon#read 4, iclass 39, count 2 2006.197.08:17:11.36#ibcon#about to read 5, iclass 39, count 2 2006.197.08:17:11.36#ibcon#read 5, iclass 39, count 2 2006.197.08:17:11.36#ibcon#about to read 6, iclass 39, count 2 2006.197.08:17:11.36#ibcon#read 6, iclass 39, count 2 2006.197.08:17:11.36#ibcon#end of sib2, iclass 39, count 2 2006.197.08:17:11.36#ibcon#*after write, iclass 39, count 2 2006.197.08:17:11.36#ibcon#*before return 0, iclass 39, count 2 2006.197.08:17:11.36#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.197.08:17:11.36#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.197.08:17:11.36#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.197.08:17:11.36#ibcon#ireg 7 cls_cnt 0 2006.197.08:17:11.36#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.197.08:17:11.48#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.197.08:17:11.48#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.197.08:17:11.48#ibcon#enter wrdev, iclass 39, count 0 2006.197.08:17:11.48#ibcon#first serial, iclass 39, count 0 2006.197.08:17:11.48#ibcon#enter sib2, iclass 39, count 0 2006.197.08:17:11.48#ibcon#flushed, iclass 39, count 0 2006.197.08:17:11.48#ibcon#about to write, iclass 39, count 0 2006.197.08:17:11.48#ibcon#wrote, iclass 39, count 0 2006.197.08:17:11.48#ibcon#about to read 3, iclass 39, count 0 2006.197.08:17:11.50#ibcon#read 3, iclass 39, count 0 2006.197.08:17:11.50#ibcon#about to read 4, iclass 39, count 0 2006.197.08:17:11.50#ibcon#read 4, iclass 39, count 0 2006.197.08:17:11.50#ibcon#about to read 5, iclass 39, count 0 2006.197.08:17:11.50#ibcon#read 5, iclass 39, count 0 2006.197.08:17:11.50#ibcon#about to read 6, iclass 39, count 0 2006.197.08:17:11.50#ibcon#read 6, iclass 39, count 0 2006.197.08:17:11.50#ibcon#end of sib2, iclass 39, count 0 2006.197.08:17:11.50#ibcon#*mode == 0, iclass 39, count 0 2006.197.08:17:11.50#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.197.08:17:11.50#ibcon#[27=USB\r\n] 2006.197.08:17:11.50#ibcon#*before write, iclass 39, count 0 2006.197.08:17:11.50#ibcon#enter sib2, iclass 39, count 0 2006.197.08:17:11.50#ibcon#flushed, iclass 39, count 0 2006.197.08:17:11.50#ibcon#about to write, iclass 39, count 0 2006.197.08:17:11.50#ibcon#wrote, iclass 39, count 0 2006.197.08:17:11.50#ibcon#about to read 3, iclass 39, count 0 2006.197.08:17:11.53#ibcon#read 3, iclass 39, count 0 2006.197.08:17:11.53#ibcon#about to read 4, iclass 39, count 0 2006.197.08:17:11.53#ibcon#read 4, iclass 39, count 0 2006.197.08:17:11.53#ibcon#about to read 5, iclass 39, count 0 2006.197.08:17:11.53#ibcon#read 5, iclass 39, count 0 2006.197.08:17:11.53#ibcon#about to read 6, iclass 39, count 0 2006.197.08:17:11.53#ibcon#read 6, iclass 39, count 0 2006.197.08:17:11.53#ibcon#end of sib2, iclass 39, count 0 2006.197.08:17:11.53#ibcon#*after write, iclass 39, count 0 2006.197.08:17:11.53#ibcon#*before return 0, iclass 39, count 0 2006.197.08:17:11.53#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.197.08:17:11.53#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.197.08:17:11.53#ibcon#about to clear, iclass 39 cls_cnt 0 2006.197.08:17:11.53#ibcon#cleared, iclass 39 cls_cnt 0 2006.197.08:17:11.53$vc4f8/vblo=5,744.99 2006.197.08:17:11.53#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.197.08:17:11.53#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.197.08:17:11.53#ibcon#ireg 17 cls_cnt 0 2006.197.08:17:11.53#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.197.08:17:11.53#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.197.08:17:11.53#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.197.08:17:11.53#ibcon#enter wrdev, iclass 3, count 0 2006.197.08:17:11.53#ibcon#first serial, iclass 3, count 0 2006.197.08:17:11.53#ibcon#enter sib2, iclass 3, count 0 2006.197.08:17:11.53#ibcon#flushed, iclass 3, count 0 2006.197.08:17:11.53#ibcon#about to write, iclass 3, count 0 2006.197.08:17:11.53#ibcon#wrote, iclass 3, count 0 2006.197.08:17:11.53#ibcon#about to read 3, iclass 3, count 0 2006.197.08:17:11.55#ibcon#read 3, iclass 3, count 0 2006.197.08:17:11.55#ibcon#about to read 4, iclass 3, count 0 2006.197.08:17:11.55#ibcon#read 4, iclass 3, count 0 2006.197.08:17:11.55#ibcon#about to read 5, iclass 3, count 0 2006.197.08:17:11.55#ibcon#read 5, iclass 3, count 0 2006.197.08:17:11.55#ibcon#about to read 6, iclass 3, count 0 2006.197.08:17:11.55#ibcon#read 6, iclass 3, count 0 2006.197.08:17:11.55#ibcon#end of sib2, iclass 3, count 0 2006.197.08:17:11.55#ibcon#*mode == 0, iclass 3, count 0 2006.197.08:17:11.55#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.197.08:17:11.55#ibcon#[28=FRQ=05,744.99\r\n] 2006.197.08:17:11.55#ibcon#*before write, iclass 3, count 0 2006.197.08:17:11.55#ibcon#enter sib2, iclass 3, count 0 2006.197.08:17:11.55#ibcon#flushed, iclass 3, count 0 2006.197.08:17:11.55#ibcon#about to write, iclass 3, count 0 2006.197.08:17:11.55#ibcon#wrote, iclass 3, count 0 2006.197.08:17:11.55#ibcon#about to read 3, iclass 3, count 0 2006.197.08:17:11.59#ibcon#read 3, iclass 3, count 0 2006.197.08:17:11.59#ibcon#about to read 4, iclass 3, count 0 2006.197.08:17:11.59#ibcon#read 4, iclass 3, count 0 2006.197.08:17:11.59#ibcon#about to read 5, iclass 3, count 0 2006.197.08:17:11.59#ibcon#read 5, iclass 3, count 0 2006.197.08:17:11.59#ibcon#about to read 6, iclass 3, count 0 2006.197.08:17:11.59#ibcon#read 6, iclass 3, count 0 2006.197.08:17:11.59#ibcon#end of sib2, iclass 3, count 0 2006.197.08:17:11.59#ibcon#*after write, iclass 3, count 0 2006.197.08:17:11.59#ibcon#*before return 0, iclass 3, count 0 2006.197.08:17:11.59#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.197.08:17:11.59#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.197.08:17:11.59#ibcon#about to clear, iclass 3 cls_cnt 0 2006.197.08:17:11.59#ibcon#cleared, iclass 3 cls_cnt 0 2006.197.08:17:11.59$vc4f8/vb=5,4 2006.197.08:17:11.59#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.197.08:17:11.59#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.197.08:17:11.59#ibcon#ireg 11 cls_cnt 2 2006.197.08:17:11.59#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.197.08:17:11.65#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.197.08:17:11.65#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.197.08:17:11.65#ibcon#enter wrdev, iclass 5, count 2 2006.197.08:17:11.65#ibcon#first serial, iclass 5, count 2 2006.197.08:17:11.65#ibcon#enter sib2, iclass 5, count 2 2006.197.08:17:11.65#ibcon#flushed, iclass 5, count 2 2006.197.08:17:11.65#ibcon#about to write, iclass 5, count 2 2006.197.08:17:11.65#ibcon#wrote, iclass 5, count 2 2006.197.08:17:11.65#ibcon#about to read 3, iclass 5, count 2 2006.197.08:17:11.67#ibcon#read 3, iclass 5, count 2 2006.197.08:17:11.67#ibcon#about to read 4, iclass 5, count 2 2006.197.08:17:11.67#ibcon#read 4, iclass 5, count 2 2006.197.08:17:11.67#ibcon#about to read 5, iclass 5, count 2 2006.197.08:17:11.67#ibcon#read 5, iclass 5, count 2 2006.197.08:17:11.67#ibcon#about to read 6, iclass 5, count 2 2006.197.08:17:11.67#ibcon#read 6, iclass 5, count 2 2006.197.08:17:11.67#ibcon#end of sib2, iclass 5, count 2 2006.197.08:17:11.67#ibcon#*mode == 0, iclass 5, count 2 2006.197.08:17:11.67#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.197.08:17:11.67#ibcon#[27=AT05-04\r\n] 2006.197.08:17:11.67#ibcon#*before write, iclass 5, count 2 2006.197.08:17:11.67#ibcon#enter sib2, iclass 5, count 2 2006.197.08:17:11.67#ibcon#flushed, iclass 5, count 2 2006.197.08:17:11.67#ibcon#about to write, iclass 5, count 2 2006.197.08:17:11.67#ibcon#wrote, iclass 5, count 2 2006.197.08:17:11.67#ibcon#about to read 3, iclass 5, count 2 2006.197.08:17:11.70#ibcon#read 3, iclass 5, count 2 2006.197.08:17:11.70#ibcon#about to read 4, iclass 5, count 2 2006.197.08:17:11.70#ibcon#read 4, iclass 5, count 2 2006.197.08:17:11.70#ibcon#about to read 5, iclass 5, count 2 2006.197.08:17:11.70#ibcon#read 5, iclass 5, count 2 2006.197.08:17:11.70#ibcon#about to read 6, iclass 5, count 2 2006.197.08:17:11.70#ibcon#read 6, iclass 5, count 2 2006.197.08:17:11.70#ibcon#end of sib2, iclass 5, count 2 2006.197.08:17:11.70#ibcon#*after write, iclass 5, count 2 2006.197.08:17:11.70#ibcon#*before return 0, iclass 5, count 2 2006.197.08:17:11.70#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.197.08:17:11.70#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.197.08:17:11.70#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.197.08:17:11.70#ibcon#ireg 7 cls_cnt 0 2006.197.08:17:11.70#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.197.08:17:11.82#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.197.08:17:11.82#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.197.08:17:11.82#ibcon#enter wrdev, iclass 5, count 0 2006.197.08:17:11.82#ibcon#first serial, iclass 5, count 0 2006.197.08:17:11.82#ibcon#enter sib2, iclass 5, count 0 2006.197.08:17:11.82#ibcon#flushed, iclass 5, count 0 2006.197.08:17:11.82#ibcon#about to write, iclass 5, count 0 2006.197.08:17:11.82#ibcon#wrote, iclass 5, count 0 2006.197.08:17:11.82#ibcon#about to read 3, iclass 5, count 0 2006.197.08:17:11.84#ibcon#read 3, iclass 5, count 0 2006.197.08:17:11.84#ibcon#about to read 4, iclass 5, count 0 2006.197.08:17:11.84#ibcon#read 4, iclass 5, count 0 2006.197.08:17:11.84#ibcon#about to read 5, iclass 5, count 0 2006.197.08:17:11.84#ibcon#read 5, iclass 5, count 0 2006.197.08:17:11.84#ibcon#about to read 6, iclass 5, count 0 2006.197.08:17:11.84#ibcon#read 6, iclass 5, count 0 2006.197.08:17:11.84#ibcon#end of sib2, iclass 5, count 0 2006.197.08:17:11.84#ibcon#*mode == 0, iclass 5, count 0 2006.197.08:17:11.84#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.197.08:17:11.84#ibcon#[27=USB\r\n] 2006.197.08:17:11.84#ibcon#*before write, iclass 5, count 0 2006.197.08:17:11.84#ibcon#enter sib2, iclass 5, count 0 2006.197.08:17:11.84#ibcon#flushed, iclass 5, count 0 2006.197.08:17:11.84#ibcon#about to write, iclass 5, count 0 2006.197.08:17:11.84#ibcon#wrote, iclass 5, count 0 2006.197.08:17:11.84#ibcon#about to read 3, iclass 5, count 0 2006.197.08:17:11.87#ibcon#read 3, iclass 5, count 0 2006.197.08:17:11.87#ibcon#about to read 4, iclass 5, count 0 2006.197.08:17:11.87#ibcon#read 4, iclass 5, count 0 2006.197.08:17:11.87#ibcon#about to read 5, iclass 5, count 0 2006.197.08:17:11.87#ibcon#read 5, iclass 5, count 0 2006.197.08:17:11.87#ibcon#about to read 6, iclass 5, count 0 2006.197.08:17:11.87#ibcon#read 6, iclass 5, count 0 2006.197.08:17:11.87#ibcon#end of sib2, iclass 5, count 0 2006.197.08:17:11.87#ibcon#*after write, iclass 5, count 0 2006.197.08:17:11.87#ibcon#*before return 0, iclass 5, count 0 2006.197.08:17:11.87#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.197.08:17:11.87#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.197.08:17:11.87#ibcon#about to clear, iclass 5 cls_cnt 0 2006.197.08:17:11.87#ibcon#cleared, iclass 5 cls_cnt 0 2006.197.08:17:11.87$vc4f8/vblo=6,752.99 2006.197.08:17:11.87#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.197.08:17:11.87#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.197.08:17:11.87#ibcon#ireg 17 cls_cnt 0 2006.197.08:17:11.87#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.197.08:17:11.87#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.197.08:17:11.87#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.197.08:17:11.87#ibcon#enter wrdev, iclass 7, count 0 2006.197.08:17:11.87#ibcon#first serial, iclass 7, count 0 2006.197.08:17:11.87#ibcon#enter sib2, iclass 7, count 0 2006.197.08:17:11.87#ibcon#flushed, iclass 7, count 0 2006.197.08:17:11.87#ibcon#about to write, iclass 7, count 0 2006.197.08:17:11.87#ibcon#wrote, iclass 7, count 0 2006.197.08:17:11.87#ibcon#about to read 3, iclass 7, count 0 2006.197.08:17:11.89#ibcon#read 3, iclass 7, count 0 2006.197.08:17:11.89#ibcon#about to read 4, iclass 7, count 0 2006.197.08:17:11.89#ibcon#read 4, iclass 7, count 0 2006.197.08:17:11.89#ibcon#about to read 5, iclass 7, count 0 2006.197.08:17:11.89#ibcon#read 5, iclass 7, count 0 2006.197.08:17:11.89#ibcon#about to read 6, iclass 7, count 0 2006.197.08:17:11.89#ibcon#read 6, iclass 7, count 0 2006.197.08:17:11.89#ibcon#end of sib2, iclass 7, count 0 2006.197.08:17:11.89#ibcon#*mode == 0, iclass 7, count 0 2006.197.08:17:11.89#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.197.08:17:11.89#ibcon#[28=FRQ=06,752.99\r\n] 2006.197.08:17:11.89#ibcon#*before write, iclass 7, count 0 2006.197.08:17:11.89#ibcon#enter sib2, iclass 7, count 0 2006.197.08:17:11.89#ibcon#flushed, iclass 7, count 0 2006.197.08:17:11.89#ibcon#about to write, iclass 7, count 0 2006.197.08:17:11.89#ibcon#wrote, iclass 7, count 0 2006.197.08:17:11.89#ibcon#about to read 3, iclass 7, count 0 2006.197.08:17:11.93#ibcon#read 3, iclass 7, count 0 2006.197.08:17:11.93#ibcon#about to read 4, iclass 7, count 0 2006.197.08:17:11.93#ibcon#read 4, iclass 7, count 0 2006.197.08:17:11.93#ibcon#about to read 5, iclass 7, count 0 2006.197.08:17:11.93#ibcon#read 5, iclass 7, count 0 2006.197.08:17:11.93#ibcon#about to read 6, iclass 7, count 0 2006.197.08:17:11.93#ibcon#read 6, iclass 7, count 0 2006.197.08:17:11.93#ibcon#end of sib2, iclass 7, count 0 2006.197.08:17:11.93#ibcon#*after write, iclass 7, count 0 2006.197.08:17:11.93#ibcon#*before return 0, iclass 7, count 0 2006.197.08:17:11.93#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.197.08:17:11.93#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.197.08:17:11.93#ibcon#about to clear, iclass 7 cls_cnt 0 2006.197.08:17:11.93#ibcon#cleared, iclass 7 cls_cnt 0 2006.197.08:17:11.93$vc4f8/vb=6,4 2006.197.08:17:11.93#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.197.08:17:11.93#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.197.08:17:11.93#ibcon#ireg 11 cls_cnt 2 2006.197.08:17:11.93#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.197.08:17:11.99#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.197.08:17:11.99#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.197.08:17:11.99#ibcon#enter wrdev, iclass 11, count 2 2006.197.08:17:11.99#ibcon#first serial, iclass 11, count 2 2006.197.08:17:11.99#ibcon#enter sib2, iclass 11, count 2 2006.197.08:17:11.99#ibcon#flushed, iclass 11, count 2 2006.197.08:17:11.99#ibcon#about to write, iclass 11, count 2 2006.197.08:17:11.99#ibcon#wrote, iclass 11, count 2 2006.197.08:17:11.99#ibcon#about to read 3, iclass 11, count 2 2006.197.08:17:12.01#ibcon#read 3, iclass 11, count 2 2006.197.08:17:12.01#ibcon#about to read 4, iclass 11, count 2 2006.197.08:17:12.01#ibcon#read 4, iclass 11, count 2 2006.197.08:17:12.01#ibcon#about to read 5, iclass 11, count 2 2006.197.08:17:12.01#ibcon#read 5, iclass 11, count 2 2006.197.08:17:12.01#ibcon#about to read 6, iclass 11, count 2 2006.197.08:17:12.01#ibcon#read 6, iclass 11, count 2 2006.197.08:17:12.01#ibcon#end of sib2, iclass 11, count 2 2006.197.08:17:12.01#ibcon#*mode == 0, iclass 11, count 2 2006.197.08:17:12.01#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.197.08:17:12.01#ibcon#[27=AT06-04\r\n] 2006.197.08:17:12.01#ibcon#*before write, iclass 11, count 2 2006.197.08:17:12.01#ibcon#enter sib2, iclass 11, count 2 2006.197.08:17:12.01#ibcon#flushed, iclass 11, count 2 2006.197.08:17:12.01#ibcon#about to write, iclass 11, count 2 2006.197.08:17:12.01#ibcon#wrote, iclass 11, count 2 2006.197.08:17:12.01#ibcon#about to read 3, iclass 11, count 2 2006.197.08:17:12.04#ibcon#read 3, iclass 11, count 2 2006.197.08:17:12.04#ibcon#about to read 4, iclass 11, count 2 2006.197.08:17:12.04#ibcon#read 4, iclass 11, count 2 2006.197.08:17:12.04#ibcon#about to read 5, iclass 11, count 2 2006.197.08:17:12.04#ibcon#read 5, iclass 11, count 2 2006.197.08:17:12.04#ibcon#about to read 6, iclass 11, count 2 2006.197.08:17:12.04#ibcon#read 6, iclass 11, count 2 2006.197.08:17:12.04#ibcon#end of sib2, iclass 11, count 2 2006.197.08:17:12.04#ibcon#*after write, iclass 11, count 2 2006.197.08:17:12.04#ibcon#*before return 0, iclass 11, count 2 2006.197.08:17:12.04#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.197.08:17:12.04#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.197.08:17:12.04#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.197.08:17:12.04#ibcon#ireg 7 cls_cnt 0 2006.197.08:17:12.04#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.197.08:17:12.16#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.197.08:17:12.16#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.197.08:17:12.16#ibcon#enter wrdev, iclass 11, count 0 2006.197.08:17:12.16#ibcon#first serial, iclass 11, count 0 2006.197.08:17:12.16#ibcon#enter sib2, iclass 11, count 0 2006.197.08:17:12.16#ibcon#flushed, iclass 11, count 0 2006.197.08:17:12.16#ibcon#about to write, iclass 11, count 0 2006.197.08:17:12.16#ibcon#wrote, iclass 11, count 0 2006.197.08:17:12.16#ibcon#about to read 3, iclass 11, count 0 2006.197.08:17:12.18#ibcon#read 3, iclass 11, count 0 2006.197.08:17:12.18#ibcon#about to read 4, iclass 11, count 0 2006.197.08:17:12.18#ibcon#read 4, iclass 11, count 0 2006.197.08:17:12.18#ibcon#about to read 5, iclass 11, count 0 2006.197.08:17:12.18#ibcon#read 5, iclass 11, count 0 2006.197.08:17:12.18#ibcon#about to read 6, iclass 11, count 0 2006.197.08:17:12.18#ibcon#read 6, iclass 11, count 0 2006.197.08:17:12.18#ibcon#end of sib2, iclass 11, count 0 2006.197.08:17:12.18#ibcon#*mode == 0, iclass 11, count 0 2006.197.08:17:12.18#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.197.08:17:12.18#ibcon#[27=USB\r\n] 2006.197.08:17:12.18#ibcon#*before write, iclass 11, count 0 2006.197.08:17:12.18#ibcon#enter sib2, iclass 11, count 0 2006.197.08:17:12.18#ibcon#flushed, iclass 11, count 0 2006.197.08:17:12.18#ibcon#about to write, iclass 11, count 0 2006.197.08:17:12.18#ibcon#wrote, iclass 11, count 0 2006.197.08:17:12.18#ibcon#about to read 3, iclass 11, count 0 2006.197.08:17:12.21#ibcon#read 3, iclass 11, count 0 2006.197.08:17:12.21#ibcon#about to read 4, iclass 11, count 0 2006.197.08:17:12.21#ibcon#read 4, iclass 11, count 0 2006.197.08:17:12.21#ibcon#about to read 5, iclass 11, count 0 2006.197.08:17:12.21#ibcon#read 5, iclass 11, count 0 2006.197.08:17:12.21#ibcon#about to read 6, iclass 11, count 0 2006.197.08:17:12.21#ibcon#read 6, iclass 11, count 0 2006.197.08:17:12.21#ibcon#end of sib2, iclass 11, count 0 2006.197.08:17:12.21#ibcon#*after write, iclass 11, count 0 2006.197.08:17:12.21#ibcon#*before return 0, iclass 11, count 0 2006.197.08:17:12.21#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.197.08:17:12.21#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.197.08:17:12.21#ibcon#about to clear, iclass 11 cls_cnt 0 2006.197.08:17:12.21#ibcon#cleared, iclass 11 cls_cnt 0 2006.197.08:17:12.21$vc4f8/vabw=wide 2006.197.08:17:12.21#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.197.08:17:12.21#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.197.08:17:12.21#ibcon#ireg 8 cls_cnt 0 2006.197.08:17:12.21#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.197.08:17:12.21#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.197.08:17:12.21#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.197.08:17:12.21#ibcon#enter wrdev, iclass 13, count 0 2006.197.08:17:12.21#ibcon#first serial, iclass 13, count 0 2006.197.08:17:12.21#ibcon#enter sib2, iclass 13, count 0 2006.197.08:17:12.21#ibcon#flushed, iclass 13, count 0 2006.197.08:17:12.21#ibcon#about to write, iclass 13, count 0 2006.197.08:17:12.21#ibcon#wrote, iclass 13, count 0 2006.197.08:17:12.21#ibcon#about to read 3, iclass 13, count 0 2006.197.08:17:12.23#ibcon#read 3, iclass 13, count 0 2006.197.08:17:12.23#ibcon#about to read 4, iclass 13, count 0 2006.197.08:17:12.23#ibcon#read 4, iclass 13, count 0 2006.197.08:17:12.23#ibcon#about to read 5, iclass 13, count 0 2006.197.08:17:12.23#ibcon#read 5, iclass 13, count 0 2006.197.08:17:12.23#ibcon#about to read 6, iclass 13, count 0 2006.197.08:17:12.23#ibcon#read 6, iclass 13, count 0 2006.197.08:17:12.23#ibcon#end of sib2, iclass 13, count 0 2006.197.08:17:12.23#ibcon#*mode == 0, iclass 13, count 0 2006.197.08:17:12.23#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.197.08:17:12.23#ibcon#[25=BW32\r\n] 2006.197.08:17:12.23#ibcon#*before write, iclass 13, count 0 2006.197.08:17:12.23#ibcon#enter sib2, iclass 13, count 0 2006.197.08:17:12.23#ibcon#flushed, iclass 13, count 0 2006.197.08:17:12.23#ibcon#about to write, iclass 13, count 0 2006.197.08:17:12.23#ibcon#wrote, iclass 13, count 0 2006.197.08:17:12.23#ibcon#about to read 3, iclass 13, count 0 2006.197.08:17:12.26#ibcon#read 3, iclass 13, count 0 2006.197.08:17:12.26#ibcon#about to read 4, iclass 13, count 0 2006.197.08:17:12.26#ibcon#read 4, iclass 13, count 0 2006.197.08:17:12.26#ibcon#about to read 5, iclass 13, count 0 2006.197.08:17:12.26#ibcon#read 5, iclass 13, count 0 2006.197.08:17:12.26#ibcon#about to read 6, iclass 13, count 0 2006.197.08:17:12.26#ibcon#read 6, iclass 13, count 0 2006.197.08:17:12.26#ibcon#end of sib2, iclass 13, count 0 2006.197.08:17:12.26#ibcon#*after write, iclass 13, count 0 2006.197.08:17:12.26#ibcon#*before return 0, iclass 13, count 0 2006.197.08:17:12.26#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.197.08:17:12.26#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.197.08:17:12.26#ibcon#about to clear, iclass 13 cls_cnt 0 2006.197.08:17:12.26#ibcon#cleared, iclass 13 cls_cnt 0 2006.197.08:17:12.26$vc4f8/vbbw=wide 2006.197.08:17:12.26#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.197.08:17:12.26#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.197.08:17:12.26#ibcon#ireg 8 cls_cnt 0 2006.197.08:17:12.26#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.197.08:17:12.33#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.197.08:17:12.33#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.197.08:17:12.33#ibcon#enter wrdev, iclass 15, count 0 2006.197.08:17:12.33#ibcon#first serial, iclass 15, count 0 2006.197.08:17:12.33#ibcon#enter sib2, iclass 15, count 0 2006.197.08:17:12.33#ibcon#flushed, iclass 15, count 0 2006.197.08:17:12.33#ibcon#about to write, iclass 15, count 0 2006.197.08:17:12.33#ibcon#wrote, iclass 15, count 0 2006.197.08:17:12.33#ibcon#about to read 3, iclass 15, count 0 2006.197.08:17:12.35#ibcon#read 3, iclass 15, count 0 2006.197.08:17:12.35#ibcon#about to read 4, iclass 15, count 0 2006.197.08:17:12.35#ibcon#read 4, iclass 15, count 0 2006.197.08:17:12.35#ibcon#about to read 5, iclass 15, count 0 2006.197.08:17:12.35#ibcon#read 5, iclass 15, count 0 2006.197.08:17:12.35#ibcon#about to read 6, iclass 15, count 0 2006.197.08:17:12.35#ibcon#read 6, iclass 15, count 0 2006.197.08:17:12.35#ibcon#end of sib2, iclass 15, count 0 2006.197.08:17:12.35#ibcon#*mode == 0, iclass 15, count 0 2006.197.08:17:12.35#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.197.08:17:12.35#ibcon#[27=BW32\r\n] 2006.197.08:17:12.35#ibcon#*before write, iclass 15, count 0 2006.197.08:17:12.35#ibcon#enter sib2, iclass 15, count 0 2006.197.08:17:12.35#ibcon#flushed, iclass 15, count 0 2006.197.08:17:12.35#ibcon#about to write, iclass 15, count 0 2006.197.08:17:12.35#ibcon#wrote, iclass 15, count 0 2006.197.08:17:12.35#ibcon#about to read 3, iclass 15, count 0 2006.197.08:17:12.38#ibcon#read 3, iclass 15, count 0 2006.197.08:17:12.38#ibcon#about to read 4, iclass 15, count 0 2006.197.08:17:12.38#ibcon#read 4, iclass 15, count 0 2006.197.08:17:12.38#ibcon#about to read 5, iclass 15, count 0 2006.197.08:17:12.38#ibcon#read 5, iclass 15, count 0 2006.197.08:17:12.38#ibcon#about to read 6, iclass 15, count 0 2006.197.08:17:12.38#ibcon#read 6, iclass 15, count 0 2006.197.08:17:12.38#ibcon#end of sib2, iclass 15, count 0 2006.197.08:17:12.38#ibcon#*after write, iclass 15, count 0 2006.197.08:17:12.38#ibcon#*before return 0, iclass 15, count 0 2006.197.08:17:12.38#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.197.08:17:12.38#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.197.08:17:12.38#ibcon#about to clear, iclass 15 cls_cnt 0 2006.197.08:17:12.38#ibcon#cleared, iclass 15 cls_cnt 0 2006.197.08:17:12.38$4f8m12a/ifd4f 2006.197.08:17:12.38$ifd4f/lo= 2006.197.08:17:12.38$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.197.08:17:12.38$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.197.08:17:12.38$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.197.08:17:12.38$ifd4f/patch= 2006.197.08:17:12.38$ifd4f/patch=lo1,a1,a2,a3,a4 2006.197.08:17:12.38$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.197.08:17:12.38$ifd4f/patch=lo3,a5,a6,a7,a8 2006.197.08:17:12.38$4f8m12a/"form=m,16.000,1:2 2006.197.08:17:12.38$4f8m12a/"tpicd 2006.197.08:17:12.38$4f8m12a/echo=off 2006.197.08:17:12.38$4f8m12a/xlog=off 2006.197.08:17:12.38:!2006.197.08:17:40 2006.197.08:17:24.14#trakl#Source acquired 2006.197.08:17:25.14#flagr#flagr/antenna,acquired 2006.197.08:17:40.00:preob 2006.197.08:17:41.14/onsource/TRACKING 2006.197.08:17:41.14:!2006.197.08:17:50 2006.197.08:17:50.00:data_valid=on 2006.197.08:17:50.00:midob 2006.197.08:17:50.14/onsource/TRACKING 2006.197.08:17:50.14/wx/25.57,1002.7,96 2006.197.08:17:50.33/cable/+6.3715E-03 2006.197.08:17:51.42/va/01,08,usb,yes,29,31 2006.197.08:17:51.42/va/02,07,usb,yes,29,31 2006.197.08:17:51.42/va/03,06,usb,yes,31,31 2006.197.08:17:51.42/va/04,07,usb,yes,30,32 2006.197.08:17:51.42/va/05,07,usb,yes,34,36 2006.197.08:17:51.42/va/06,06,usb,yes,33,33 2006.197.08:17:51.42/va/07,06,usb,yes,34,33 2006.197.08:17:51.42/va/08,07,usb,yes,32,31 2006.197.08:17:51.65/valo/01,532.99,yes,locked 2006.197.08:17:51.65/valo/02,572.99,yes,locked 2006.197.08:17:51.65/valo/03,672.99,yes,locked 2006.197.08:17:51.65/valo/04,832.99,yes,locked 2006.197.08:17:51.65/valo/05,652.99,yes,locked 2006.197.08:17:51.65/valo/06,772.99,yes,locked 2006.197.08:17:51.65/valo/07,832.99,yes,locked 2006.197.08:17:51.65/valo/08,852.99,yes,locked 2006.197.08:17:52.74/vb/01,04,usb,yes,29,28 2006.197.08:17:52.74/vb/02,04,usb,yes,31,32 2006.197.08:17:52.74/vb/03,04,usb,yes,27,31 2006.197.08:17:52.74/vb/04,04,usb,yes,28,28 2006.197.08:17:52.74/vb/05,04,usb,yes,26,30 2006.197.08:17:52.74/vb/06,04,usb,yes,27,30 2006.197.08:17:52.74/vb/07,04,usb,yes,29,29 2006.197.08:17:52.74/vb/08,04,usb,yes,27,30 2006.197.08:17:52.97/vblo/01,632.99,yes,locked 2006.197.08:17:52.97/vblo/02,640.99,yes,locked 2006.197.08:17:52.97/vblo/03,656.99,yes,locked 2006.197.08:17:52.97/vblo/04,712.99,yes,locked 2006.197.08:17:52.97/vblo/05,744.99,yes,locked 2006.197.08:17:52.97/vblo/06,752.99,yes,locked 2006.197.08:17:52.97/vblo/07,734.99,yes,locked 2006.197.08:17:52.97/vblo/08,744.99,yes,locked 2006.197.08:17:53.12/vabw/8 2006.197.08:17:53.27/vbbw/8 2006.197.08:17:53.36/xfe/off,on,15.5 2006.197.08:17:53.74/ifatt/23,28,28,28 2006.197.08:17:54.10/fmout-gps/S +3.00E-07 2006.197.08:17:54.13:!2006.197.08:18:50 2006.197.08:18:50.00:data_valid=off 2006.197.08:18:50.00:postob 2006.197.08:18:50.21/cable/+6.3741E-03 2006.197.08:18:50.21/wx/25.56,1002.7,96 2006.197.08:18:51.10/fmout-gps/S +3.00E-07 2006.197.08:18:51.10:scan_name=197-0820,k06197,60 2006.197.08:18:51.10:source=0602+673,060752.67,672055.4,2000.0,ccw 2006.197.08:18:51.14#flagr#flagr/antenna,new-source 2006.197.08:18:52.14:checkk5 2006.197.08:18:52.47/chk_autoobs//k5ts1/ autoobs is running! 2006.197.08:18:52.82/chk_autoobs//k5ts2/ autoobs is running! 2006.197.08:18:53.17/chk_autoobs//k5ts3/ autoobs is running! 2006.197.08:18:53.50/chk_autoobs//k5ts4/ autoobs is running! 2006.197.08:18:53.84/chk_obsdata//k5ts1/T1970817??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.08:18:54.17/chk_obsdata//k5ts2/T1970817??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.08:18:54.51/chk_obsdata//k5ts3/T1970817??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.08:18:54.85/chk_obsdata//k5ts4/T1970817??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.08:18:55.51/k5log//k5ts1_log_newline 2006.197.08:18:56.19/k5log//k5ts2_log_newline 2006.197.08:18:56.87/k5log//k5ts3_log_newline 2006.197.08:18:57.53/k5log//k5ts4_log_newline 2006.197.08:18:57.55/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.197.08:18:57.55:4f8m12a=3 2006.197.08:18:57.55$4f8m12a/echo=on 2006.197.08:18:57.55$4f8m12a/pcalon 2006.197.08:18:57.56$pcalon/"no phase cal control is implemented here 2006.197.08:18:57.56$4f8m12a/"tpicd=stop 2006.197.08:18:57.56$4f8m12a/vc4f8 2006.197.08:18:57.56$vc4f8/valo=1,532.99 2006.197.08:18:57.56#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.197.08:18:57.56#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.197.08:18:57.56#ibcon#ireg 17 cls_cnt 0 2006.197.08:18:57.56#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.197.08:18:57.56#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.197.08:18:57.56#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.197.08:18:57.56#ibcon#enter wrdev, iclass 22, count 0 2006.197.08:18:57.56#ibcon#first serial, iclass 22, count 0 2006.197.08:18:57.56#ibcon#enter sib2, iclass 22, count 0 2006.197.08:18:57.56#ibcon#flushed, iclass 22, count 0 2006.197.08:18:57.56#ibcon#about to write, iclass 22, count 0 2006.197.08:18:57.56#ibcon#wrote, iclass 22, count 0 2006.197.08:18:57.56#ibcon#about to read 3, iclass 22, count 0 2006.197.08:18:57.58#ibcon#read 3, iclass 22, count 0 2006.197.08:18:57.58#ibcon#about to read 4, iclass 22, count 0 2006.197.08:18:57.58#ibcon#read 4, iclass 22, count 0 2006.197.08:18:57.58#ibcon#about to read 5, iclass 22, count 0 2006.197.08:18:57.58#ibcon#read 5, iclass 22, count 0 2006.197.08:18:57.58#ibcon#about to read 6, iclass 22, count 0 2006.197.08:18:57.58#ibcon#read 6, iclass 22, count 0 2006.197.08:18:57.58#ibcon#end of sib2, iclass 22, count 0 2006.197.08:18:57.58#ibcon#*mode == 0, iclass 22, count 0 2006.197.08:18:57.58#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.197.08:18:57.58#ibcon#[26=FRQ=01,532.99\r\n] 2006.197.08:18:57.58#ibcon#*before write, iclass 22, count 0 2006.197.08:18:57.58#ibcon#enter sib2, iclass 22, count 0 2006.197.08:18:57.58#ibcon#flushed, iclass 22, count 0 2006.197.08:18:57.58#ibcon#about to write, iclass 22, count 0 2006.197.08:18:57.58#ibcon#wrote, iclass 22, count 0 2006.197.08:18:57.58#ibcon#about to read 3, iclass 22, count 0 2006.197.08:18:57.63#ibcon#read 3, iclass 22, count 0 2006.197.08:18:57.63#ibcon#about to read 4, iclass 22, count 0 2006.197.08:18:57.63#ibcon#read 4, iclass 22, count 0 2006.197.08:18:57.63#ibcon#about to read 5, iclass 22, count 0 2006.197.08:18:57.63#ibcon#read 5, iclass 22, count 0 2006.197.08:18:57.63#ibcon#about to read 6, iclass 22, count 0 2006.197.08:18:57.63#ibcon#read 6, iclass 22, count 0 2006.197.08:18:57.63#ibcon#end of sib2, iclass 22, count 0 2006.197.08:18:57.63#ibcon#*after write, iclass 22, count 0 2006.197.08:18:57.63#ibcon#*before return 0, iclass 22, count 0 2006.197.08:18:57.63#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.197.08:18:57.63#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.197.08:18:57.63#ibcon#about to clear, iclass 22 cls_cnt 0 2006.197.08:18:57.63#ibcon#cleared, iclass 22 cls_cnt 0 2006.197.08:18:57.63$vc4f8/va=1,8 2006.197.08:18:57.63#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.197.08:18:57.63#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.197.08:18:57.63#ibcon#ireg 11 cls_cnt 2 2006.197.08:18:57.63#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.197.08:18:57.63#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.197.08:18:57.63#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.197.08:18:57.63#ibcon#enter wrdev, iclass 24, count 2 2006.197.08:18:57.63#ibcon#first serial, iclass 24, count 2 2006.197.08:18:57.63#ibcon#enter sib2, iclass 24, count 2 2006.197.08:18:57.63#ibcon#flushed, iclass 24, count 2 2006.197.08:18:57.63#ibcon#about to write, iclass 24, count 2 2006.197.08:18:57.63#ibcon#wrote, iclass 24, count 2 2006.197.08:18:57.63#ibcon#about to read 3, iclass 24, count 2 2006.197.08:18:57.65#ibcon#read 3, iclass 24, count 2 2006.197.08:18:57.65#ibcon#about to read 4, iclass 24, count 2 2006.197.08:18:57.65#ibcon#read 4, iclass 24, count 2 2006.197.08:18:57.65#ibcon#about to read 5, iclass 24, count 2 2006.197.08:18:57.65#ibcon#read 5, iclass 24, count 2 2006.197.08:18:57.65#ibcon#about to read 6, iclass 24, count 2 2006.197.08:18:57.65#ibcon#read 6, iclass 24, count 2 2006.197.08:18:57.65#ibcon#end of sib2, iclass 24, count 2 2006.197.08:18:57.65#ibcon#*mode == 0, iclass 24, count 2 2006.197.08:18:57.65#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.197.08:18:57.65#ibcon#[25=AT01-08\r\n] 2006.197.08:18:57.65#ibcon#*before write, iclass 24, count 2 2006.197.08:18:57.65#ibcon#enter sib2, iclass 24, count 2 2006.197.08:18:57.65#ibcon#flushed, iclass 24, count 2 2006.197.08:18:57.65#ibcon#about to write, iclass 24, count 2 2006.197.08:18:57.65#ibcon#wrote, iclass 24, count 2 2006.197.08:18:57.65#ibcon#about to read 3, iclass 24, count 2 2006.197.08:18:57.68#ibcon#read 3, iclass 24, count 2 2006.197.08:18:57.68#ibcon#about to read 4, iclass 24, count 2 2006.197.08:18:57.68#ibcon#read 4, iclass 24, count 2 2006.197.08:18:57.68#ibcon#about to read 5, iclass 24, count 2 2006.197.08:18:57.68#ibcon#read 5, iclass 24, count 2 2006.197.08:18:57.68#ibcon#about to read 6, iclass 24, count 2 2006.197.08:18:57.68#ibcon#read 6, iclass 24, count 2 2006.197.08:18:57.68#ibcon#end of sib2, iclass 24, count 2 2006.197.08:18:57.68#ibcon#*after write, iclass 24, count 2 2006.197.08:18:57.68#ibcon#*before return 0, iclass 24, count 2 2006.197.08:18:57.68#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.197.08:18:57.68#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.197.08:18:57.68#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.197.08:18:57.68#ibcon#ireg 7 cls_cnt 0 2006.197.08:18:57.68#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.197.08:18:57.80#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.197.08:18:57.80#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.197.08:18:57.80#ibcon#enter wrdev, iclass 24, count 0 2006.197.08:18:57.80#ibcon#first serial, iclass 24, count 0 2006.197.08:18:57.80#ibcon#enter sib2, iclass 24, count 0 2006.197.08:18:57.80#ibcon#flushed, iclass 24, count 0 2006.197.08:18:57.80#ibcon#about to write, iclass 24, count 0 2006.197.08:18:57.80#ibcon#wrote, iclass 24, count 0 2006.197.08:18:57.80#ibcon#about to read 3, iclass 24, count 0 2006.197.08:18:57.82#ibcon#read 3, iclass 24, count 0 2006.197.08:18:57.82#ibcon#about to read 4, iclass 24, count 0 2006.197.08:18:57.82#ibcon#read 4, iclass 24, count 0 2006.197.08:18:57.82#ibcon#about to read 5, iclass 24, count 0 2006.197.08:18:57.82#ibcon#read 5, iclass 24, count 0 2006.197.08:18:57.82#ibcon#about to read 6, iclass 24, count 0 2006.197.08:18:57.82#ibcon#read 6, iclass 24, count 0 2006.197.08:18:57.82#ibcon#end of sib2, iclass 24, count 0 2006.197.08:18:57.82#ibcon#*mode == 0, iclass 24, count 0 2006.197.08:18:57.82#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.197.08:18:57.82#ibcon#[25=USB\r\n] 2006.197.08:18:57.82#ibcon#*before write, iclass 24, count 0 2006.197.08:18:57.82#ibcon#enter sib2, iclass 24, count 0 2006.197.08:18:57.82#ibcon#flushed, iclass 24, count 0 2006.197.08:18:57.82#ibcon#about to write, iclass 24, count 0 2006.197.08:18:57.82#ibcon#wrote, iclass 24, count 0 2006.197.08:18:57.82#ibcon#about to read 3, iclass 24, count 0 2006.197.08:18:57.85#ibcon#read 3, iclass 24, count 0 2006.197.08:18:57.85#ibcon#about to read 4, iclass 24, count 0 2006.197.08:18:57.85#ibcon#read 4, iclass 24, count 0 2006.197.08:18:57.85#ibcon#about to read 5, iclass 24, count 0 2006.197.08:18:57.85#ibcon#read 5, iclass 24, count 0 2006.197.08:18:57.85#ibcon#about to read 6, iclass 24, count 0 2006.197.08:18:57.85#ibcon#read 6, iclass 24, count 0 2006.197.08:18:57.85#ibcon#end of sib2, iclass 24, count 0 2006.197.08:18:57.85#ibcon#*after write, iclass 24, count 0 2006.197.08:18:57.85#ibcon#*before return 0, iclass 24, count 0 2006.197.08:18:57.85#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.197.08:18:57.85#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.197.08:18:57.85#ibcon#about to clear, iclass 24 cls_cnt 0 2006.197.08:18:57.85#ibcon#cleared, iclass 24 cls_cnt 0 2006.197.08:18:57.85$vc4f8/valo=2,572.99 2006.197.08:18:57.85#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.197.08:18:57.85#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.197.08:18:57.85#ibcon#ireg 17 cls_cnt 0 2006.197.08:18:57.85#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.197.08:18:57.85#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.197.08:18:57.85#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.197.08:18:57.85#ibcon#enter wrdev, iclass 26, count 0 2006.197.08:18:57.85#ibcon#first serial, iclass 26, count 0 2006.197.08:18:57.85#ibcon#enter sib2, iclass 26, count 0 2006.197.08:18:57.85#ibcon#flushed, iclass 26, count 0 2006.197.08:18:57.85#ibcon#about to write, iclass 26, count 0 2006.197.08:18:57.85#ibcon#wrote, iclass 26, count 0 2006.197.08:18:57.85#ibcon#about to read 3, iclass 26, count 0 2006.197.08:18:57.87#ibcon#read 3, iclass 26, count 0 2006.197.08:18:57.87#ibcon#about to read 4, iclass 26, count 0 2006.197.08:18:57.87#ibcon#read 4, iclass 26, count 0 2006.197.08:18:57.87#ibcon#about to read 5, iclass 26, count 0 2006.197.08:18:57.87#ibcon#read 5, iclass 26, count 0 2006.197.08:18:57.87#ibcon#about to read 6, iclass 26, count 0 2006.197.08:18:57.87#ibcon#read 6, iclass 26, count 0 2006.197.08:18:57.87#ibcon#end of sib2, iclass 26, count 0 2006.197.08:18:57.87#ibcon#*mode == 0, iclass 26, count 0 2006.197.08:18:57.87#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.197.08:18:57.87#ibcon#[26=FRQ=02,572.99\r\n] 2006.197.08:18:57.87#ibcon#*before write, iclass 26, count 0 2006.197.08:18:57.87#ibcon#enter sib2, iclass 26, count 0 2006.197.08:18:57.87#ibcon#flushed, iclass 26, count 0 2006.197.08:18:57.87#ibcon#about to write, iclass 26, count 0 2006.197.08:18:57.87#ibcon#wrote, iclass 26, count 0 2006.197.08:18:57.87#ibcon#about to read 3, iclass 26, count 0 2006.197.08:18:57.91#ibcon#read 3, iclass 26, count 0 2006.197.08:18:57.91#ibcon#about to read 4, iclass 26, count 0 2006.197.08:18:57.91#ibcon#read 4, iclass 26, count 0 2006.197.08:18:57.91#ibcon#about to read 5, iclass 26, count 0 2006.197.08:18:57.91#ibcon#read 5, iclass 26, count 0 2006.197.08:18:57.91#ibcon#about to read 6, iclass 26, count 0 2006.197.08:18:57.91#ibcon#read 6, iclass 26, count 0 2006.197.08:18:57.91#ibcon#end of sib2, iclass 26, count 0 2006.197.08:18:57.91#ibcon#*after write, iclass 26, count 0 2006.197.08:18:57.91#ibcon#*before return 0, iclass 26, count 0 2006.197.08:18:57.91#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.197.08:18:57.91#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.197.08:18:57.91#ibcon#about to clear, iclass 26 cls_cnt 0 2006.197.08:18:57.91#ibcon#cleared, iclass 26 cls_cnt 0 2006.197.08:18:57.91$vc4f8/va=2,7 2006.197.08:18:57.91#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.197.08:18:57.91#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.197.08:18:57.91#ibcon#ireg 11 cls_cnt 2 2006.197.08:18:57.91#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.197.08:18:57.97#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.197.08:18:57.97#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.197.08:18:57.97#ibcon#enter wrdev, iclass 28, count 2 2006.197.08:18:57.97#ibcon#first serial, iclass 28, count 2 2006.197.08:18:57.97#ibcon#enter sib2, iclass 28, count 2 2006.197.08:18:57.97#ibcon#flushed, iclass 28, count 2 2006.197.08:18:57.97#ibcon#about to write, iclass 28, count 2 2006.197.08:18:57.97#ibcon#wrote, iclass 28, count 2 2006.197.08:18:57.97#ibcon#about to read 3, iclass 28, count 2 2006.197.08:18:57.99#ibcon#read 3, iclass 28, count 2 2006.197.08:18:57.99#ibcon#about to read 4, iclass 28, count 2 2006.197.08:18:57.99#ibcon#read 4, iclass 28, count 2 2006.197.08:18:57.99#ibcon#about to read 5, iclass 28, count 2 2006.197.08:18:57.99#ibcon#read 5, iclass 28, count 2 2006.197.08:18:57.99#ibcon#about to read 6, iclass 28, count 2 2006.197.08:18:57.99#ibcon#read 6, iclass 28, count 2 2006.197.08:18:57.99#ibcon#end of sib2, iclass 28, count 2 2006.197.08:18:57.99#ibcon#*mode == 0, iclass 28, count 2 2006.197.08:18:57.99#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.197.08:18:57.99#ibcon#[25=AT02-07\r\n] 2006.197.08:18:57.99#ibcon#*before write, iclass 28, count 2 2006.197.08:18:57.99#ibcon#enter sib2, iclass 28, count 2 2006.197.08:18:57.99#ibcon#flushed, iclass 28, count 2 2006.197.08:18:57.99#ibcon#about to write, iclass 28, count 2 2006.197.08:18:57.99#ibcon#wrote, iclass 28, count 2 2006.197.08:18:57.99#ibcon#about to read 3, iclass 28, count 2 2006.197.08:18:58.02#ibcon#read 3, iclass 28, count 2 2006.197.08:18:58.02#ibcon#about to read 4, iclass 28, count 2 2006.197.08:18:58.02#ibcon#read 4, iclass 28, count 2 2006.197.08:18:58.02#ibcon#about to read 5, iclass 28, count 2 2006.197.08:18:58.02#ibcon#read 5, iclass 28, count 2 2006.197.08:18:58.02#ibcon#about to read 6, iclass 28, count 2 2006.197.08:18:58.02#ibcon#read 6, iclass 28, count 2 2006.197.08:18:58.02#ibcon#end of sib2, iclass 28, count 2 2006.197.08:18:58.02#ibcon#*after write, iclass 28, count 2 2006.197.08:18:58.02#ibcon#*before return 0, iclass 28, count 2 2006.197.08:18:58.02#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.197.08:18:58.02#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.197.08:18:58.02#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.197.08:18:58.02#ibcon#ireg 7 cls_cnt 0 2006.197.08:18:58.02#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.197.08:18:58.14#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.197.08:18:58.14#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.197.08:18:58.14#ibcon#enter wrdev, iclass 28, count 0 2006.197.08:18:58.14#ibcon#first serial, iclass 28, count 0 2006.197.08:18:58.14#ibcon#enter sib2, iclass 28, count 0 2006.197.08:18:58.14#ibcon#flushed, iclass 28, count 0 2006.197.08:18:58.14#ibcon#about to write, iclass 28, count 0 2006.197.08:18:58.14#ibcon#wrote, iclass 28, count 0 2006.197.08:18:58.14#ibcon#about to read 3, iclass 28, count 0 2006.197.08:18:58.16#ibcon#read 3, iclass 28, count 0 2006.197.08:18:58.16#ibcon#about to read 4, iclass 28, count 0 2006.197.08:18:58.16#ibcon#read 4, iclass 28, count 0 2006.197.08:18:58.16#ibcon#about to read 5, iclass 28, count 0 2006.197.08:18:58.16#ibcon#read 5, iclass 28, count 0 2006.197.08:18:58.16#ibcon#about to read 6, iclass 28, count 0 2006.197.08:18:58.16#ibcon#read 6, iclass 28, count 0 2006.197.08:18:58.16#ibcon#end of sib2, iclass 28, count 0 2006.197.08:18:58.16#ibcon#*mode == 0, iclass 28, count 0 2006.197.08:18:58.16#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.197.08:18:58.16#ibcon#[25=USB\r\n] 2006.197.08:18:58.16#ibcon#*before write, iclass 28, count 0 2006.197.08:18:58.16#ibcon#enter sib2, iclass 28, count 0 2006.197.08:18:58.16#ibcon#flushed, iclass 28, count 0 2006.197.08:18:58.16#ibcon#about to write, iclass 28, count 0 2006.197.08:18:58.16#ibcon#wrote, iclass 28, count 0 2006.197.08:18:58.16#ibcon#about to read 3, iclass 28, count 0 2006.197.08:18:58.19#ibcon#read 3, iclass 28, count 0 2006.197.08:18:58.19#ibcon#about to read 4, iclass 28, count 0 2006.197.08:18:58.19#ibcon#read 4, iclass 28, count 0 2006.197.08:18:58.19#ibcon#about to read 5, iclass 28, count 0 2006.197.08:18:58.19#ibcon#read 5, iclass 28, count 0 2006.197.08:18:58.19#ibcon#about to read 6, iclass 28, count 0 2006.197.08:18:58.19#ibcon#read 6, iclass 28, count 0 2006.197.08:18:58.19#ibcon#end of sib2, iclass 28, count 0 2006.197.08:18:58.19#ibcon#*after write, iclass 28, count 0 2006.197.08:18:58.19#ibcon#*before return 0, iclass 28, count 0 2006.197.08:18:58.19#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.197.08:18:58.19#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.197.08:18:58.19#ibcon#about to clear, iclass 28 cls_cnt 0 2006.197.08:18:58.19#ibcon#cleared, iclass 28 cls_cnt 0 2006.197.08:18:58.19$vc4f8/valo=3,672.99 2006.197.08:18:58.19#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.197.08:18:58.19#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.197.08:18:58.19#ibcon#ireg 17 cls_cnt 0 2006.197.08:18:58.19#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.197.08:18:58.19#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.197.08:18:58.19#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.197.08:18:58.19#ibcon#enter wrdev, iclass 30, count 0 2006.197.08:18:58.19#ibcon#first serial, iclass 30, count 0 2006.197.08:18:58.19#ibcon#enter sib2, iclass 30, count 0 2006.197.08:18:58.19#ibcon#flushed, iclass 30, count 0 2006.197.08:18:58.19#ibcon#about to write, iclass 30, count 0 2006.197.08:18:58.19#ibcon#wrote, iclass 30, count 0 2006.197.08:18:58.19#ibcon#about to read 3, iclass 30, count 0 2006.197.08:18:58.21#ibcon#read 3, iclass 30, count 0 2006.197.08:18:58.21#ibcon#about to read 4, iclass 30, count 0 2006.197.08:18:58.21#ibcon#read 4, iclass 30, count 0 2006.197.08:18:58.21#ibcon#about to read 5, iclass 30, count 0 2006.197.08:18:58.21#ibcon#read 5, iclass 30, count 0 2006.197.08:18:58.21#ibcon#about to read 6, iclass 30, count 0 2006.197.08:18:58.21#ibcon#read 6, iclass 30, count 0 2006.197.08:18:58.21#ibcon#end of sib2, iclass 30, count 0 2006.197.08:18:58.21#ibcon#*mode == 0, iclass 30, count 0 2006.197.08:18:58.21#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.197.08:18:58.21#ibcon#[26=FRQ=03,672.99\r\n] 2006.197.08:18:58.21#ibcon#*before write, iclass 30, count 0 2006.197.08:18:58.21#ibcon#enter sib2, iclass 30, count 0 2006.197.08:18:58.21#ibcon#flushed, iclass 30, count 0 2006.197.08:18:58.21#ibcon#about to write, iclass 30, count 0 2006.197.08:18:58.21#ibcon#wrote, iclass 30, count 0 2006.197.08:18:58.21#ibcon#about to read 3, iclass 30, count 0 2006.197.08:18:58.25#ibcon#read 3, iclass 30, count 0 2006.197.08:18:58.25#ibcon#about to read 4, iclass 30, count 0 2006.197.08:18:58.25#ibcon#read 4, iclass 30, count 0 2006.197.08:18:58.25#ibcon#about to read 5, iclass 30, count 0 2006.197.08:18:58.25#ibcon#read 5, iclass 30, count 0 2006.197.08:18:58.25#ibcon#about to read 6, iclass 30, count 0 2006.197.08:18:58.25#ibcon#read 6, iclass 30, count 0 2006.197.08:18:58.25#ibcon#end of sib2, iclass 30, count 0 2006.197.08:18:58.25#ibcon#*after write, iclass 30, count 0 2006.197.08:18:58.25#ibcon#*before return 0, iclass 30, count 0 2006.197.08:18:58.25#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.197.08:18:58.25#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.197.08:18:58.25#ibcon#about to clear, iclass 30 cls_cnt 0 2006.197.08:18:58.25#ibcon#cleared, iclass 30 cls_cnt 0 2006.197.08:18:58.25$vc4f8/va=3,6 2006.197.08:18:58.25#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.197.08:18:58.25#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.197.08:18:58.25#ibcon#ireg 11 cls_cnt 2 2006.197.08:18:58.25#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.197.08:18:58.31#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.197.08:18:58.31#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.197.08:18:58.31#ibcon#enter wrdev, iclass 32, count 2 2006.197.08:18:58.31#ibcon#first serial, iclass 32, count 2 2006.197.08:18:58.31#ibcon#enter sib2, iclass 32, count 2 2006.197.08:18:58.31#ibcon#flushed, iclass 32, count 2 2006.197.08:18:58.31#ibcon#about to write, iclass 32, count 2 2006.197.08:18:58.31#ibcon#wrote, iclass 32, count 2 2006.197.08:18:58.31#ibcon#about to read 3, iclass 32, count 2 2006.197.08:18:58.33#ibcon#read 3, iclass 32, count 2 2006.197.08:18:58.33#ibcon#about to read 4, iclass 32, count 2 2006.197.08:18:58.33#ibcon#read 4, iclass 32, count 2 2006.197.08:18:58.33#ibcon#about to read 5, iclass 32, count 2 2006.197.08:18:58.33#ibcon#read 5, iclass 32, count 2 2006.197.08:18:58.33#ibcon#about to read 6, iclass 32, count 2 2006.197.08:18:58.33#ibcon#read 6, iclass 32, count 2 2006.197.08:18:58.33#ibcon#end of sib2, iclass 32, count 2 2006.197.08:18:58.33#ibcon#*mode == 0, iclass 32, count 2 2006.197.08:18:58.33#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.197.08:18:58.33#ibcon#[25=AT03-06\r\n] 2006.197.08:18:58.33#ibcon#*before write, iclass 32, count 2 2006.197.08:18:58.33#ibcon#enter sib2, iclass 32, count 2 2006.197.08:18:58.33#ibcon#flushed, iclass 32, count 2 2006.197.08:18:58.33#ibcon#about to write, iclass 32, count 2 2006.197.08:18:58.33#ibcon#wrote, iclass 32, count 2 2006.197.08:18:58.33#ibcon#about to read 3, iclass 32, count 2 2006.197.08:18:58.36#ibcon#read 3, iclass 32, count 2 2006.197.08:18:58.36#ibcon#about to read 4, iclass 32, count 2 2006.197.08:18:58.36#ibcon#read 4, iclass 32, count 2 2006.197.08:18:58.36#ibcon#about to read 5, iclass 32, count 2 2006.197.08:18:58.36#ibcon#read 5, iclass 32, count 2 2006.197.08:18:58.36#ibcon#about to read 6, iclass 32, count 2 2006.197.08:18:58.36#ibcon#read 6, iclass 32, count 2 2006.197.08:18:58.36#ibcon#end of sib2, iclass 32, count 2 2006.197.08:18:58.36#ibcon#*after write, iclass 32, count 2 2006.197.08:18:58.36#ibcon#*before return 0, iclass 32, count 2 2006.197.08:18:58.36#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.197.08:18:58.36#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.197.08:18:58.36#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.197.08:18:58.36#ibcon#ireg 7 cls_cnt 0 2006.197.08:18:58.36#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.197.08:18:58.48#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.197.08:18:58.48#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.197.08:18:58.48#ibcon#enter wrdev, iclass 32, count 0 2006.197.08:18:58.48#ibcon#first serial, iclass 32, count 0 2006.197.08:18:58.48#ibcon#enter sib2, iclass 32, count 0 2006.197.08:18:58.48#ibcon#flushed, iclass 32, count 0 2006.197.08:18:58.48#ibcon#about to write, iclass 32, count 0 2006.197.08:18:58.48#ibcon#wrote, iclass 32, count 0 2006.197.08:18:58.48#ibcon#about to read 3, iclass 32, count 0 2006.197.08:18:58.50#ibcon#read 3, iclass 32, count 0 2006.197.08:18:58.50#ibcon#about to read 4, iclass 32, count 0 2006.197.08:18:58.50#ibcon#read 4, iclass 32, count 0 2006.197.08:18:58.50#ibcon#about to read 5, iclass 32, count 0 2006.197.08:18:58.50#ibcon#read 5, iclass 32, count 0 2006.197.08:18:58.50#ibcon#about to read 6, iclass 32, count 0 2006.197.08:18:58.50#ibcon#read 6, iclass 32, count 0 2006.197.08:18:58.50#ibcon#end of sib2, iclass 32, count 0 2006.197.08:18:58.50#ibcon#*mode == 0, iclass 32, count 0 2006.197.08:18:58.50#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.197.08:18:58.50#ibcon#[25=USB\r\n] 2006.197.08:18:58.50#ibcon#*before write, iclass 32, count 0 2006.197.08:18:58.50#ibcon#enter sib2, iclass 32, count 0 2006.197.08:18:58.50#ibcon#flushed, iclass 32, count 0 2006.197.08:18:58.50#ibcon#about to write, iclass 32, count 0 2006.197.08:18:58.50#ibcon#wrote, iclass 32, count 0 2006.197.08:18:58.50#ibcon#about to read 3, iclass 32, count 0 2006.197.08:18:58.53#ibcon#read 3, iclass 32, count 0 2006.197.08:18:58.53#ibcon#about to read 4, iclass 32, count 0 2006.197.08:18:58.53#ibcon#read 4, iclass 32, count 0 2006.197.08:18:58.53#ibcon#about to read 5, iclass 32, count 0 2006.197.08:18:58.53#ibcon#read 5, iclass 32, count 0 2006.197.08:18:58.53#ibcon#about to read 6, iclass 32, count 0 2006.197.08:18:58.53#ibcon#read 6, iclass 32, count 0 2006.197.08:18:58.53#ibcon#end of sib2, iclass 32, count 0 2006.197.08:18:58.53#ibcon#*after write, iclass 32, count 0 2006.197.08:18:58.53#ibcon#*before return 0, iclass 32, count 0 2006.197.08:18:58.53#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.197.08:18:58.53#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.197.08:18:58.53#ibcon#about to clear, iclass 32 cls_cnt 0 2006.197.08:18:58.53#ibcon#cleared, iclass 32 cls_cnt 0 2006.197.08:18:58.53$vc4f8/valo=4,832.99 2006.197.08:18:58.53#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.197.08:18:58.53#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.197.08:18:58.53#ibcon#ireg 17 cls_cnt 0 2006.197.08:18:58.53#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.197.08:18:58.53#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.197.08:18:58.53#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.197.08:18:58.53#ibcon#enter wrdev, iclass 34, count 0 2006.197.08:18:58.53#ibcon#first serial, iclass 34, count 0 2006.197.08:18:58.53#ibcon#enter sib2, iclass 34, count 0 2006.197.08:18:58.53#ibcon#flushed, iclass 34, count 0 2006.197.08:18:58.53#ibcon#about to write, iclass 34, count 0 2006.197.08:18:58.53#ibcon#wrote, iclass 34, count 0 2006.197.08:18:58.53#ibcon#about to read 3, iclass 34, count 0 2006.197.08:18:58.55#ibcon#read 3, iclass 34, count 0 2006.197.08:18:58.55#ibcon#about to read 4, iclass 34, count 0 2006.197.08:18:58.55#ibcon#read 4, iclass 34, count 0 2006.197.08:18:58.55#ibcon#about to read 5, iclass 34, count 0 2006.197.08:18:58.55#ibcon#read 5, iclass 34, count 0 2006.197.08:18:58.55#ibcon#about to read 6, iclass 34, count 0 2006.197.08:18:58.55#ibcon#read 6, iclass 34, count 0 2006.197.08:18:58.55#ibcon#end of sib2, iclass 34, count 0 2006.197.08:18:58.55#ibcon#*mode == 0, iclass 34, count 0 2006.197.08:18:58.55#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.197.08:18:58.55#ibcon#[26=FRQ=04,832.99\r\n] 2006.197.08:18:58.55#ibcon#*before write, iclass 34, count 0 2006.197.08:18:58.55#ibcon#enter sib2, iclass 34, count 0 2006.197.08:18:58.55#ibcon#flushed, iclass 34, count 0 2006.197.08:18:58.55#ibcon#about to write, iclass 34, count 0 2006.197.08:18:58.55#ibcon#wrote, iclass 34, count 0 2006.197.08:18:58.55#ibcon#about to read 3, iclass 34, count 0 2006.197.08:18:58.59#ibcon#read 3, iclass 34, count 0 2006.197.08:18:58.59#ibcon#about to read 4, iclass 34, count 0 2006.197.08:18:58.59#ibcon#read 4, iclass 34, count 0 2006.197.08:18:58.59#ibcon#about to read 5, iclass 34, count 0 2006.197.08:18:58.59#ibcon#read 5, iclass 34, count 0 2006.197.08:18:58.59#ibcon#about to read 6, iclass 34, count 0 2006.197.08:18:58.59#ibcon#read 6, iclass 34, count 0 2006.197.08:18:58.59#ibcon#end of sib2, iclass 34, count 0 2006.197.08:18:58.59#ibcon#*after write, iclass 34, count 0 2006.197.08:18:58.59#ibcon#*before return 0, iclass 34, count 0 2006.197.08:18:58.59#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.197.08:18:58.59#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.197.08:18:58.59#ibcon#about to clear, iclass 34 cls_cnt 0 2006.197.08:18:58.59#ibcon#cleared, iclass 34 cls_cnt 0 2006.197.08:18:58.59$vc4f8/va=4,7 2006.197.08:18:58.59#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.197.08:18:58.59#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.197.08:18:58.59#ibcon#ireg 11 cls_cnt 2 2006.197.08:18:58.59#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.197.08:18:58.65#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.197.08:18:58.65#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.197.08:18:58.65#ibcon#enter wrdev, iclass 36, count 2 2006.197.08:18:58.65#ibcon#first serial, iclass 36, count 2 2006.197.08:18:58.65#ibcon#enter sib2, iclass 36, count 2 2006.197.08:18:58.65#ibcon#flushed, iclass 36, count 2 2006.197.08:18:58.65#ibcon#about to write, iclass 36, count 2 2006.197.08:18:58.65#ibcon#wrote, iclass 36, count 2 2006.197.08:18:58.65#ibcon#about to read 3, iclass 36, count 2 2006.197.08:18:58.67#ibcon#read 3, iclass 36, count 2 2006.197.08:18:58.67#ibcon#about to read 4, iclass 36, count 2 2006.197.08:18:58.67#ibcon#read 4, iclass 36, count 2 2006.197.08:18:58.67#ibcon#about to read 5, iclass 36, count 2 2006.197.08:18:58.67#ibcon#read 5, iclass 36, count 2 2006.197.08:18:58.67#ibcon#about to read 6, iclass 36, count 2 2006.197.08:18:58.67#ibcon#read 6, iclass 36, count 2 2006.197.08:18:58.67#ibcon#end of sib2, iclass 36, count 2 2006.197.08:18:58.67#ibcon#*mode == 0, iclass 36, count 2 2006.197.08:18:58.67#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.197.08:18:58.67#ibcon#[25=AT04-07\r\n] 2006.197.08:18:58.67#ibcon#*before write, iclass 36, count 2 2006.197.08:18:58.67#ibcon#enter sib2, iclass 36, count 2 2006.197.08:18:58.67#ibcon#flushed, iclass 36, count 2 2006.197.08:18:58.67#ibcon#about to write, iclass 36, count 2 2006.197.08:18:58.67#ibcon#wrote, iclass 36, count 2 2006.197.08:18:58.67#ibcon#about to read 3, iclass 36, count 2 2006.197.08:18:58.70#ibcon#read 3, iclass 36, count 2 2006.197.08:18:58.70#ibcon#about to read 4, iclass 36, count 2 2006.197.08:18:58.70#ibcon#read 4, iclass 36, count 2 2006.197.08:18:58.70#ibcon#about to read 5, iclass 36, count 2 2006.197.08:18:58.70#ibcon#read 5, iclass 36, count 2 2006.197.08:18:58.70#ibcon#about to read 6, iclass 36, count 2 2006.197.08:18:58.70#ibcon#read 6, iclass 36, count 2 2006.197.08:18:58.70#ibcon#end of sib2, iclass 36, count 2 2006.197.08:18:58.70#ibcon#*after write, iclass 36, count 2 2006.197.08:18:58.70#ibcon#*before return 0, iclass 36, count 2 2006.197.08:18:58.70#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.197.08:18:58.70#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.197.08:18:58.70#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.197.08:18:58.70#ibcon#ireg 7 cls_cnt 0 2006.197.08:18:58.70#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.197.08:18:58.82#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.197.08:18:58.82#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.197.08:18:58.82#ibcon#enter wrdev, iclass 36, count 0 2006.197.08:18:58.82#ibcon#first serial, iclass 36, count 0 2006.197.08:18:58.82#ibcon#enter sib2, iclass 36, count 0 2006.197.08:18:58.82#ibcon#flushed, iclass 36, count 0 2006.197.08:18:58.82#ibcon#about to write, iclass 36, count 0 2006.197.08:18:58.82#ibcon#wrote, iclass 36, count 0 2006.197.08:18:58.82#ibcon#about to read 3, iclass 36, count 0 2006.197.08:18:58.84#ibcon#read 3, iclass 36, count 0 2006.197.08:18:58.84#ibcon#about to read 4, iclass 36, count 0 2006.197.08:18:58.84#ibcon#read 4, iclass 36, count 0 2006.197.08:18:58.84#ibcon#about to read 5, iclass 36, count 0 2006.197.08:18:58.84#ibcon#read 5, iclass 36, count 0 2006.197.08:18:58.84#ibcon#about to read 6, iclass 36, count 0 2006.197.08:18:58.84#ibcon#read 6, iclass 36, count 0 2006.197.08:18:58.84#ibcon#end of sib2, iclass 36, count 0 2006.197.08:18:58.84#ibcon#*mode == 0, iclass 36, count 0 2006.197.08:18:58.84#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.197.08:18:58.84#ibcon#[25=USB\r\n] 2006.197.08:18:58.84#ibcon#*before write, iclass 36, count 0 2006.197.08:18:58.84#ibcon#enter sib2, iclass 36, count 0 2006.197.08:18:58.84#ibcon#flushed, iclass 36, count 0 2006.197.08:18:58.84#ibcon#about to write, iclass 36, count 0 2006.197.08:18:58.84#ibcon#wrote, iclass 36, count 0 2006.197.08:18:58.84#ibcon#about to read 3, iclass 36, count 0 2006.197.08:18:58.87#ibcon#read 3, iclass 36, count 0 2006.197.08:18:58.87#ibcon#about to read 4, iclass 36, count 0 2006.197.08:18:58.87#ibcon#read 4, iclass 36, count 0 2006.197.08:18:58.87#ibcon#about to read 5, iclass 36, count 0 2006.197.08:18:58.87#ibcon#read 5, iclass 36, count 0 2006.197.08:18:58.87#ibcon#about to read 6, iclass 36, count 0 2006.197.08:18:58.87#ibcon#read 6, iclass 36, count 0 2006.197.08:18:58.87#ibcon#end of sib2, iclass 36, count 0 2006.197.08:18:58.87#ibcon#*after write, iclass 36, count 0 2006.197.08:18:58.87#ibcon#*before return 0, iclass 36, count 0 2006.197.08:18:58.87#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.197.08:18:58.87#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.197.08:18:58.87#ibcon#about to clear, iclass 36 cls_cnt 0 2006.197.08:18:58.87#ibcon#cleared, iclass 36 cls_cnt 0 2006.197.08:18:58.87$vc4f8/valo=5,652.99 2006.197.08:18:58.87#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.197.08:18:58.87#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.197.08:18:58.87#ibcon#ireg 17 cls_cnt 0 2006.197.08:18:58.87#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.197.08:18:58.87#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.197.08:18:58.87#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.197.08:18:58.87#ibcon#enter wrdev, iclass 38, count 0 2006.197.08:18:58.87#ibcon#first serial, iclass 38, count 0 2006.197.08:18:58.87#ibcon#enter sib2, iclass 38, count 0 2006.197.08:18:58.87#ibcon#flushed, iclass 38, count 0 2006.197.08:18:58.87#ibcon#about to write, iclass 38, count 0 2006.197.08:18:58.87#ibcon#wrote, iclass 38, count 0 2006.197.08:18:58.87#ibcon#about to read 3, iclass 38, count 0 2006.197.08:18:58.89#ibcon#read 3, iclass 38, count 0 2006.197.08:18:58.89#ibcon#about to read 4, iclass 38, count 0 2006.197.08:18:58.89#ibcon#read 4, iclass 38, count 0 2006.197.08:18:58.89#ibcon#about to read 5, iclass 38, count 0 2006.197.08:18:58.89#ibcon#read 5, iclass 38, count 0 2006.197.08:18:58.89#ibcon#about to read 6, iclass 38, count 0 2006.197.08:18:58.89#ibcon#read 6, iclass 38, count 0 2006.197.08:18:58.89#ibcon#end of sib2, iclass 38, count 0 2006.197.08:18:58.89#ibcon#*mode == 0, iclass 38, count 0 2006.197.08:18:58.89#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.197.08:18:58.89#ibcon#[26=FRQ=05,652.99\r\n] 2006.197.08:18:58.89#ibcon#*before write, iclass 38, count 0 2006.197.08:18:58.89#ibcon#enter sib2, iclass 38, count 0 2006.197.08:18:58.89#ibcon#flushed, iclass 38, count 0 2006.197.08:18:58.89#ibcon#about to write, iclass 38, count 0 2006.197.08:18:58.89#ibcon#wrote, iclass 38, count 0 2006.197.08:18:58.89#ibcon#about to read 3, iclass 38, count 0 2006.197.08:18:58.93#ibcon#read 3, iclass 38, count 0 2006.197.08:18:58.93#ibcon#about to read 4, iclass 38, count 0 2006.197.08:18:58.93#ibcon#read 4, iclass 38, count 0 2006.197.08:18:58.93#ibcon#about to read 5, iclass 38, count 0 2006.197.08:18:58.93#ibcon#read 5, iclass 38, count 0 2006.197.08:18:58.93#ibcon#about to read 6, iclass 38, count 0 2006.197.08:18:58.93#ibcon#read 6, iclass 38, count 0 2006.197.08:18:58.93#ibcon#end of sib2, iclass 38, count 0 2006.197.08:18:58.93#ibcon#*after write, iclass 38, count 0 2006.197.08:18:58.93#ibcon#*before return 0, iclass 38, count 0 2006.197.08:18:58.93#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.197.08:18:58.93#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.197.08:18:58.93#ibcon#about to clear, iclass 38 cls_cnt 0 2006.197.08:18:58.93#ibcon#cleared, iclass 38 cls_cnt 0 2006.197.08:18:58.93$vc4f8/va=5,7 2006.197.08:18:58.93#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.197.08:18:58.93#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.197.08:18:58.93#ibcon#ireg 11 cls_cnt 2 2006.197.08:18:58.93#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.197.08:18:58.99#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.197.08:18:58.99#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.197.08:18:58.99#ibcon#enter wrdev, iclass 40, count 2 2006.197.08:18:58.99#ibcon#first serial, iclass 40, count 2 2006.197.08:18:58.99#ibcon#enter sib2, iclass 40, count 2 2006.197.08:18:58.99#ibcon#flushed, iclass 40, count 2 2006.197.08:18:58.99#ibcon#about to write, iclass 40, count 2 2006.197.08:18:58.99#ibcon#wrote, iclass 40, count 2 2006.197.08:18:58.99#ibcon#about to read 3, iclass 40, count 2 2006.197.08:18:59.01#ibcon#read 3, iclass 40, count 2 2006.197.08:18:59.01#ibcon#about to read 4, iclass 40, count 2 2006.197.08:18:59.01#ibcon#read 4, iclass 40, count 2 2006.197.08:18:59.01#ibcon#about to read 5, iclass 40, count 2 2006.197.08:18:59.01#ibcon#read 5, iclass 40, count 2 2006.197.08:18:59.01#ibcon#about to read 6, iclass 40, count 2 2006.197.08:18:59.01#ibcon#read 6, iclass 40, count 2 2006.197.08:18:59.01#ibcon#end of sib2, iclass 40, count 2 2006.197.08:18:59.01#ibcon#*mode == 0, iclass 40, count 2 2006.197.08:18:59.01#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.197.08:18:59.01#ibcon#[25=AT05-07\r\n] 2006.197.08:18:59.01#ibcon#*before write, iclass 40, count 2 2006.197.08:18:59.01#ibcon#enter sib2, iclass 40, count 2 2006.197.08:18:59.01#ibcon#flushed, iclass 40, count 2 2006.197.08:18:59.01#ibcon#about to write, iclass 40, count 2 2006.197.08:18:59.01#ibcon#wrote, iclass 40, count 2 2006.197.08:18:59.01#ibcon#about to read 3, iclass 40, count 2 2006.197.08:18:59.04#ibcon#read 3, iclass 40, count 2 2006.197.08:18:59.04#ibcon#about to read 4, iclass 40, count 2 2006.197.08:18:59.04#ibcon#read 4, iclass 40, count 2 2006.197.08:18:59.04#ibcon#about to read 5, iclass 40, count 2 2006.197.08:18:59.04#ibcon#read 5, iclass 40, count 2 2006.197.08:18:59.04#ibcon#about to read 6, iclass 40, count 2 2006.197.08:18:59.04#ibcon#read 6, iclass 40, count 2 2006.197.08:18:59.04#ibcon#end of sib2, iclass 40, count 2 2006.197.08:18:59.04#ibcon#*after write, iclass 40, count 2 2006.197.08:18:59.04#ibcon#*before return 0, iclass 40, count 2 2006.197.08:18:59.04#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.197.08:18:59.04#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.197.08:18:59.04#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.197.08:18:59.04#ibcon#ireg 7 cls_cnt 0 2006.197.08:18:59.04#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.197.08:18:59.16#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.197.08:18:59.16#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.197.08:18:59.16#ibcon#enter wrdev, iclass 40, count 0 2006.197.08:18:59.16#ibcon#first serial, iclass 40, count 0 2006.197.08:18:59.16#ibcon#enter sib2, iclass 40, count 0 2006.197.08:18:59.16#ibcon#flushed, iclass 40, count 0 2006.197.08:18:59.16#ibcon#about to write, iclass 40, count 0 2006.197.08:18:59.16#ibcon#wrote, iclass 40, count 0 2006.197.08:18:59.16#ibcon#about to read 3, iclass 40, count 0 2006.197.08:18:59.18#ibcon#read 3, iclass 40, count 0 2006.197.08:18:59.18#ibcon#about to read 4, iclass 40, count 0 2006.197.08:18:59.18#ibcon#read 4, iclass 40, count 0 2006.197.08:18:59.18#ibcon#about to read 5, iclass 40, count 0 2006.197.08:18:59.18#ibcon#read 5, iclass 40, count 0 2006.197.08:18:59.18#ibcon#about to read 6, iclass 40, count 0 2006.197.08:18:59.18#ibcon#read 6, iclass 40, count 0 2006.197.08:18:59.18#ibcon#end of sib2, iclass 40, count 0 2006.197.08:18:59.18#ibcon#*mode == 0, iclass 40, count 0 2006.197.08:18:59.18#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.197.08:18:59.18#ibcon#[25=USB\r\n] 2006.197.08:18:59.18#ibcon#*before write, iclass 40, count 0 2006.197.08:18:59.18#ibcon#enter sib2, iclass 40, count 0 2006.197.08:18:59.18#ibcon#flushed, iclass 40, count 0 2006.197.08:18:59.18#ibcon#about to write, iclass 40, count 0 2006.197.08:18:59.18#ibcon#wrote, iclass 40, count 0 2006.197.08:18:59.18#ibcon#about to read 3, iclass 40, count 0 2006.197.08:18:59.21#ibcon#read 3, iclass 40, count 0 2006.197.08:18:59.21#ibcon#about to read 4, iclass 40, count 0 2006.197.08:18:59.21#ibcon#read 4, iclass 40, count 0 2006.197.08:18:59.21#ibcon#about to read 5, iclass 40, count 0 2006.197.08:18:59.21#ibcon#read 5, iclass 40, count 0 2006.197.08:18:59.21#ibcon#about to read 6, iclass 40, count 0 2006.197.08:18:59.21#ibcon#read 6, iclass 40, count 0 2006.197.08:18:59.21#ibcon#end of sib2, iclass 40, count 0 2006.197.08:18:59.21#ibcon#*after write, iclass 40, count 0 2006.197.08:18:59.21#ibcon#*before return 0, iclass 40, count 0 2006.197.08:18:59.21#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.197.08:18:59.21#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.197.08:18:59.21#ibcon#about to clear, iclass 40 cls_cnt 0 2006.197.08:18:59.21#ibcon#cleared, iclass 40 cls_cnt 0 2006.197.08:18:59.21$vc4f8/valo=6,772.99 2006.197.08:18:59.21#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.197.08:18:59.21#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.197.08:18:59.21#ibcon#ireg 17 cls_cnt 0 2006.197.08:18:59.21#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.197.08:18:59.21#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.197.08:18:59.21#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.197.08:18:59.21#ibcon#enter wrdev, iclass 4, count 0 2006.197.08:18:59.21#ibcon#first serial, iclass 4, count 0 2006.197.08:18:59.21#ibcon#enter sib2, iclass 4, count 0 2006.197.08:18:59.21#ibcon#flushed, iclass 4, count 0 2006.197.08:18:59.21#ibcon#about to write, iclass 4, count 0 2006.197.08:18:59.21#ibcon#wrote, iclass 4, count 0 2006.197.08:18:59.21#ibcon#about to read 3, iclass 4, count 0 2006.197.08:18:59.23#ibcon#read 3, iclass 4, count 0 2006.197.08:18:59.23#ibcon#about to read 4, iclass 4, count 0 2006.197.08:18:59.23#ibcon#read 4, iclass 4, count 0 2006.197.08:18:59.23#ibcon#about to read 5, iclass 4, count 0 2006.197.08:18:59.23#ibcon#read 5, iclass 4, count 0 2006.197.08:18:59.23#ibcon#about to read 6, iclass 4, count 0 2006.197.08:18:59.23#ibcon#read 6, iclass 4, count 0 2006.197.08:18:59.23#ibcon#end of sib2, iclass 4, count 0 2006.197.08:18:59.23#ibcon#*mode == 0, iclass 4, count 0 2006.197.08:18:59.23#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.197.08:18:59.23#ibcon#[26=FRQ=06,772.99\r\n] 2006.197.08:18:59.23#ibcon#*before write, iclass 4, count 0 2006.197.08:18:59.23#ibcon#enter sib2, iclass 4, count 0 2006.197.08:18:59.23#ibcon#flushed, iclass 4, count 0 2006.197.08:18:59.23#ibcon#about to write, iclass 4, count 0 2006.197.08:18:59.23#ibcon#wrote, iclass 4, count 0 2006.197.08:18:59.23#ibcon#about to read 3, iclass 4, count 0 2006.197.08:18:59.27#ibcon#read 3, iclass 4, count 0 2006.197.08:18:59.27#ibcon#about to read 4, iclass 4, count 0 2006.197.08:18:59.27#ibcon#read 4, iclass 4, count 0 2006.197.08:18:59.27#ibcon#about to read 5, iclass 4, count 0 2006.197.08:18:59.27#ibcon#read 5, iclass 4, count 0 2006.197.08:18:59.27#ibcon#about to read 6, iclass 4, count 0 2006.197.08:18:59.27#ibcon#read 6, iclass 4, count 0 2006.197.08:18:59.27#ibcon#end of sib2, iclass 4, count 0 2006.197.08:18:59.27#ibcon#*after write, iclass 4, count 0 2006.197.08:18:59.27#ibcon#*before return 0, iclass 4, count 0 2006.197.08:18:59.27#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.197.08:18:59.27#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.197.08:18:59.27#ibcon#about to clear, iclass 4 cls_cnt 0 2006.197.08:18:59.27#ibcon#cleared, iclass 4 cls_cnt 0 2006.197.08:18:59.27$vc4f8/va=6,6 2006.197.08:18:59.27#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.197.08:18:59.27#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.197.08:18:59.27#ibcon#ireg 11 cls_cnt 2 2006.197.08:18:59.27#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.197.08:18:59.33#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.197.08:18:59.33#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.197.08:18:59.33#ibcon#enter wrdev, iclass 6, count 2 2006.197.08:18:59.33#ibcon#first serial, iclass 6, count 2 2006.197.08:18:59.33#ibcon#enter sib2, iclass 6, count 2 2006.197.08:18:59.33#ibcon#flushed, iclass 6, count 2 2006.197.08:18:59.33#ibcon#about to write, iclass 6, count 2 2006.197.08:18:59.33#ibcon#wrote, iclass 6, count 2 2006.197.08:18:59.33#ibcon#about to read 3, iclass 6, count 2 2006.197.08:18:59.35#ibcon#read 3, iclass 6, count 2 2006.197.08:18:59.35#ibcon#about to read 4, iclass 6, count 2 2006.197.08:18:59.35#ibcon#read 4, iclass 6, count 2 2006.197.08:18:59.35#ibcon#about to read 5, iclass 6, count 2 2006.197.08:18:59.35#ibcon#read 5, iclass 6, count 2 2006.197.08:18:59.35#ibcon#about to read 6, iclass 6, count 2 2006.197.08:18:59.35#ibcon#read 6, iclass 6, count 2 2006.197.08:18:59.35#ibcon#end of sib2, iclass 6, count 2 2006.197.08:18:59.35#ibcon#*mode == 0, iclass 6, count 2 2006.197.08:18:59.35#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.197.08:18:59.35#ibcon#[25=AT06-06\r\n] 2006.197.08:18:59.35#ibcon#*before write, iclass 6, count 2 2006.197.08:18:59.35#ibcon#enter sib2, iclass 6, count 2 2006.197.08:18:59.35#ibcon#flushed, iclass 6, count 2 2006.197.08:18:59.35#ibcon#about to write, iclass 6, count 2 2006.197.08:18:59.35#ibcon#wrote, iclass 6, count 2 2006.197.08:18:59.35#ibcon#about to read 3, iclass 6, count 2 2006.197.08:18:59.38#ibcon#read 3, iclass 6, count 2 2006.197.08:18:59.38#ibcon#about to read 4, iclass 6, count 2 2006.197.08:18:59.38#ibcon#read 4, iclass 6, count 2 2006.197.08:18:59.38#ibcon#about to read 5, iclass 6, count 2 2006.197.08:18:59.38#ibcon#read 5, iclass 6, count 2 2006.197.08:18:59.38#ibcon#about to read 6, iclass 6, count 2 2006.197.08:18:59.38#ibcon#read 6, iclass 6, count 2 2006.197.08:18:59.38#ibcon#end of sib2, iclass 6, count 2 2006.197.08:18:59.38#ibcon#*after write, iclass 6, count 2 2006.197.08:18:59.38#ibcon#*before return 0, iclass 6, count 2 2006.197.08:18:59.38#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.197.08:18:59.38#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.197.08:18:59.38#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.197.08:18:59.38#ibcon#ireg 7 cls_cnt 0 2006.197.08:18:59.38#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.197.08:18:59.50#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.197.08:18:59.50#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.197.08:18:59.50#ibcon#enter wrdev, iclass 6, count 0 2006.197.08:18:59.50#ibcon#first serial, iclass 6, count 0 2006.197.08:18:59.50#ibcon#enter sib2, iclass 6, count 0 2006.197.08:18:59.50#ibcon#flushed, iclass 6, count 0 2006.197.08:18:59.50#ibcon#about to write, iclass 6, count 0 2006.197.08:18:59.50#ibcon#wrote, iclass 6, count 0 2006.197.08:18:59.50#ibcon#about to read 3, iclass 6, count 0 2006.197.08:18:59.52#ibcon#read 3, iclass 6, count 0 2006.197.08:18:59.52#ibcon#about to read 4, iclass 6, count 0 2006.197.08:18:59.52#ibcon#read 4, iclass 6, count 0 2006.197.08:18:59.52#ibcon#about to read 5, iclass 6, count 0 2006.197.08:18:59.52#ibcon#read 5, iclass 6, count 0 2006.197.08:18:59.52#ibcon#about to read 6, iclass 6, count 0 2006.197.08:18:59.52#ibcon#read 6, iclass 6, count 0 2006.197.08:18:59.52#ibcon#end of sib2, iclass 6, count 0 2006.197.08:18:59.52#ibcon#*mode == 0, iclass 6, count 0 2006.197.08:18:59.52#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.197.08:18:59.52#ibcon#[25=USB\r\n] 2006.197.08:18:59.52#ibcon#*before write, iclass 6, count 0 2006.197.08:18:59.52#ibcon#enter sib2, iclass 6, count 0 2006.197.08:18:59.52#ibcon#flushed, iclass 6, count 0 2006.197.08:18:59.52#ibcon#about to write, iclass 6, count 0 2006.197.08:18:59.52#ibcon#wrote, iclass 6, count 0 2006.197.08:18:59.52#ibcon#about to read 3, iclass 6, count 0 2006.197.08:18:59.55#ibcon#read 3, iclass 6, count 0 2006.197.08:18:59.55#ibcon#about to read 4, iclass 6, count 0 2006.197.08:18:59.55#ibcon#read 4, iclass 6, count 0 2006.197.08:18:59.55#ibcon#about to read 5, iclass 6, count 0 2006.197.08:18:59.55#ibcon#read 5, iclass 6, count 0 2006.197.08:18:59.55#ibcon#about to read 6, iclass 6, count 0 2006.197.08:18:59.55#ibcon#read 6, iclass 6, count 0 2006.197.08:18:59.55#ibcon#end of sib2, iclass 6, count 0 2006.197.08:18:59.55#ibcon#*after write, iclass 6, count 0 2006.197.08:18:59.55#ibcon#*before return 0, iclass 6, count 0 2006.197.08:18:59.55#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.197.08:18:59.55#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.197.08:18:59.55#ibcon#about to clear, iclass 6 cls_cnt 0 2006.197.08:18:59.55#ibcon#cleared, iclass 6 cls_cnt 0 2006.197.08:18:59.55$vc4f8/valo=7,832.99 2006.197.08:18:59.55#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.197.08:18:59.55#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.197.08:18:59.55#ibcon#ireg 17 cls_cnt 0 2006.197.08:18:59.55#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.197.08:18:59.55#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.197.08:18:59.55#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.197.08:18:59.55#ibcon#enter wrdev, iclass 10, count 0 2006.197.08:18:59.55#ibcon#first serial, iclass 10, count 0 2006.197.08:18:59.55#ibcon#enter sib2, iclass 10, count 0 2006.197.08:18:59.55#ibcon#flushed, iclass 10, count 0 2006.197.08:18:59.55#ibcon#about to write, iclass 10, count 0 2006.197.08:18:59.55#ibcon#wrote, iclass 10, count 0 2006.197.08:18:59.55#ibcon#about to read 3, iclass 10, count 0 2006.197.08:18:59.57#ibcon#read 3, iclass 10, count 0 2006.197.08:18:59.57#ibcon#about to read 4, iclass 10, count 0 2006.197.08:18:59.57#ibcon#read 4, iclass 10, count 0 2006.197.08:18:59.57#ibcon#about to read 5, iclass 10, count 0 2006.197.08:18:59.57#ibcon#read 5, iclass 10, count 0 2006.197.08:18:59.57#ibcon#about to read 6, iclass 10, count 0 2006.197.08:18:59.57#ibcon#read 6, iclass 10, count 0 2006.197.08:18:59.57#ibcon#end of sib2, iclass 10, count 0 2006.197.08:18:59.57#ibcon#*mode == 0, iclass 10, count 0 2006.197.08:18:59.57#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.197.08:18:59.57#ibcon#[26=FRQ=07,832.99\r\n] 2006.197.08:18:59.57#ibcon#*before write, iclass 10, count 0 2006.197.08:18:59.57#ibcon#enter sib2, iclass 10, count 0 2006.197.08:18:59.57#ibcon#flushed, iclass 10, count 0 2006.197.08:18:59.57#ibcon#about to write, iclass 10, count 0 2006.197.08:18:59.57#ibcon#wrote, iclass 10, count 0 2006.197.08:18:59.57#ibcon#about to read 3, iclass 10, count 0 2006.197.08:18:59.61#ibcon#read 3, iclass 10, count 0 2006.197.08:18:59.61#ibcon#about to read 4, iclass 10, count 0 2006.197.08:18:59.61#ibcon#read 4, iclass 10, count 0 2006.197.08:18:59.61#ibcon#about to read 5, iclass 10, count 0 2006.197.08:18:59.61#ibcon#read 5, iclass 10, count 0 2006.197.08:18:59.61#ibcon#about to read 6, iclass 10, count 0 2006.197.08:18:59.61#ibcon#read 6, iclass 10, count 0 2006.197.08:18:59.61#ibcon#end of sib2, iclass 10, count 0 2006.197.08:18:59.61#ibcon#*after write, iclass 10, count 0 2006.197.08:18:59.61#ibcon#*before return 0, iclass 10, count 0 2006.197.08:18:59.61#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.197.08:18:59.61#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.197.08:18:59.61#ibcon#about to clear, iclass 10 cls_cnt 0 2006.197.08:18:59.61#ibcon#cleared, iclass 10 cls_cnt 0 2006.197.08:18:59.61$vc4f8/va=7,6 2006.197.08:18:59.61#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.197.08:18:59.61#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.197.08:18:59.61#ibcon#ireg 11 cls_cnt 2 2006.197.08:18:59.61#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.197.08:18:59.67#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.197.08:18:59.67#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.197.08:18:59.67#ibcon#enter wrdev, iclass 12, count 2 2006.197.08:18:59.67#ibcon#first serial, iclass 12, count 2 2006.197.08:18:59.67#ibcon#enter sib2, iclass 12, count 2 2006.197.08:18:59.67#ibcon#flushed, iclass 12, count 2 2006.197.08:18:59.67#ibcon#about to write, iclass 12, count 2 2006.197.08:18:59.67#ibcon#wrote, iclass 12, count 2 2006.197.08:18:59.67#ibcon#about to read 3, iclass 12, count 2 2006.197.08:18:59.69#ibcon#read 3, iclass 12, count 2 2006.197.08:18:59.69#ibcon#about to read 4, iclass 12, count 2 2006.197.08:18:59.69#ibcon#read 4, iclass 12, count 2 2006.197.08:18:59.69#ibcon#about to read 5, iclass 12, count 2 2006.197.08:18:59.69#ibcon#read 5, iclass 12, count 2 2006.197.08:18:59.69#ibcon#about to read 6, iclass 12, count 2 2006.197.08:18:59.69#ibcon#read 6, iclass 12, count 2 2006.197.08:18:59.69#ibcon#end of sib2, iclass 12, count 2 2006.197.08:18:59.69#ibcon#*mode == 0, iclass 12, count 2 2006.197.08:18:59.69#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.197.08:18:59.69#ibcon#[25=AT07-06\r\n] 2006.197.08:18:59.69#ibcon#*before write, iclass 12, count 2 2006.197.08:18:59.69#ibcon#enter sib2, iclass 12, count 2 2006.197.08:18:59.69#ibcon#flushed, iclass 12, count 2 2006.197.08:18:59.69#ibcon#about to write, iclass 12, count 2 2006.197.08:18:59.69#ibcon#wrote, iclass 12, count 2 2006.197.08:18:59.69#ibcon#about to read 3, iclass 12, count 2 2006.197.08:18:59.69#abcon#<5=/05 3.7 7.2 25.56 961002.7\r\n> 2006.197.08:18:59.71#abcon#{5=INTERFACE CLEAR} 2006.197.08:18:59.72#ibcon#read 3, iclass 12, count 2 2006.197.08:18:59.72#ibcon#about to read 4, iclass 12, count 2 2006.197.08:18:59.72#ibcon#read 4, iclass 12, count 2 2006.197.08:18:59.72#ibcon#about to read 5, iclass 12, count 2 2006.197.08:18:59.72#ibcon#read 5, iclass 12, count 2 2006.197.08:18:59.72#ibcon#about to read 6, iclass 12, count 2 2006.197.08:18:59.72#ibcon#read 6, iclass 12, count 2 2006.197.08:18:59.72#ibcon#end of sib2, iclass 12, count 2 2006.197.08:18:59.72#ibcon#*after write, iclass 12, count 2 2006.197.08:18:59.72#ibcon#*before return 0, iclass 12, count 2 2006.197.08:18:59.72#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.197.08:18:59.72#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.197.08:18:59.72#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.197.08:18:59.72#ibcon#ireg 7 cls_cnt 0 2006.197.08:18:59.72#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.197.08:18:59.77#abcon#[5=S1D000X0/0*\r\n] 2006.197.08:18:59.84#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.197.08:18:59.84#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.197.08:18:59.84#ibcon#enter wrdev, iclass 12, count 0 2006.197.08:18:59.84#ibcon#first serial, iclass 12, count 0 2006.197.08:18:59.84#ibcon#enter sib2, iclass 12, count 0 2006.197.08:18:59.84#ibcon#flushed, iclass 12, count 0 2006.197.08:18:59.84#ibcon#about to write, iclass 12, count 0 2006.197.08:18:59.84#ibcon#wrote, iclass 12, count 0 2006.197.08:18:59.84#ibcon#about to read 3, iclass 12, count 0 2006.197.08:18:59.86#ibcon#read 3, iclass 12, count 0 2006.197.08:18:59.86#ibcon#about to read 4, iclass 12, count 0 2006.197.08:18:59.86#ibcon#read 4, iclass 12, count 0 2006.197.08:18:59.86#ibcon#about to read 5, iclass 12, count 0 2006.197.08:18:59.86#ibcon#read 5, iclass 12, count 0 2006.197.08:18:59.86#ibcon#about to read 6, iclass 12, count 0 2006.197.08:18:59.86#ibcon#read 6, iclass 12, count 0 2006.197.08:18:59.86#ibcon#end of sib2, iclass 12, count 0 2006.197.08:18:59.86#ibcon#*mode == 0, iclass 12, count 0 2006.197.08:18:59.86#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.197.08:18:59.86#ibcon#[25=USB\r\n] 2006.197.08:18:59.86#ibcon#*before write, iclass 12, count 0 2006.197.08:18:59.86#ibcon#enter sib2, iclass 12, count 0 2006.197.08:18:59.86#ibcon#flushed, iclass 12, count 0 2006.197.08:18:59.86#ibcon#about to write, iclass 12, count 0 2006.197.08:18:59.86#ibcon#wrote, iclass 12, count 0 2006.197.08:18:59.86#ibcon#about to read 3, iclass 12, count 0 2006.197.08:18:59.89#ibcon#read 3, iclass 12, count 0 2006.197.08:18:59.89#ibcon#about to read 4, iclass 12, count 0 2006.197.08:18:59.89#ibcon#read 4, iclass 12, count 0 2006.197.08:18:59.89#ibcon#about to read 5, iclass 12, count 0 2006.197.08:18:59.89#ibcon#read 5, iclass 12, count 0 2006.197.08:18:59.89#ibcon#about to read 6, iclass 12, count 0 2006.197.08:18:59.89#ibcon#read 6, iclass 12, count 0 2006.197.08:18:59.89#ibcon#end of sib2, iclass 12, count 0 2006.197.08:18:59.89#ibcon#*after write, iclass 12, count 0 2006.197.08:18:59.89#ibcon#*before return 0, iclass 12, count 0 2006.197.08:18:59.89#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.197.08:18:59.89#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.197.08:18:59.89#ibcon#about to clear, iclass 12 cls_cnt 0 2006.197.08:18:59.89#ibcon#cleared, iclass 12 cls_cnt 0 2006.197.08:18:59.89$vc4f8/valo=8,852.99 2006.197.08:18:59.89#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.197.08:18:59.89#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.197.08:18:59.89#ibcon#ireg 17 cls_cnt 0 2006.197.08:18:59.89#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.197.08:18:59.89#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.197.08:18:59.89#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.197.08:18:59.89#ibcon#enter wrdev, iclass 18, count 0 2006.197.08:18:59.89#ibcon#first serial, iclass 18, count 0 2006.197.08:18:59.89#ibcon#enter sib2, iclass 18, count 0 2006.197.08:18:59.89#ibcon#flushed, iclass 18, count 0 2006.197.08:18:59.89#ibcon#about to write, iclass 18, count 0 2006.197.08:18:59.89#ibcon#wrote, iclass 18, count 0 2006.197.08:18:59.89#ibcon#about to read 3, iclass 18, count 0 2006.197.08:18:59.91#ibcon#read 3, iclass 18, count 0 2006.197.08:18:59.91#ibcon#about to read 4, iclass 18, count 0 2006.197.08:18:59.91#ibcon#read 4, iclass 18, count 0 2006.197.08:18:59.91#ibcon#about to read 5, iclass 18, count 0 2006.197.08:18:59.91#ibcon#read 5, iclass 18, count 0 2006.197.08:18:59.91#ibcon#about to read 6, iclass 18, count 0 2006.197.08:18:59.91#ibcon#read 6, iclass 18, count 0 2006.197.08:18:59.91#ibcon#end of sib2, iclass 18, count 0 2006.197.08:18:59.91#ibcon#*mode == 0, iclass 18, count 0 2006.197.08:18:59.91#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.197.08:18:59.91#ibcon#[26=FRQ=08,852.99\r\n] 2006.197.08:18:59.91#ibcon#*before write, iclass 18, count 0 2006.197.08:18:59.91#ibcon#enter sib2, iclass 18, count 0 2006.197.08:18:59.91#ibcon#flushed, iclass 18, count 0 2006.197.08:18:59.91#ibcon#about to write, iclass 18, count 0 2006.197.08:18:59.91#ibcon#wrote, iclass 18, count 0 2006.197.08:18:59.91#ibcon#about to read 3, iclass 18, count 0 2006.197.08:18:59.95#ibcon#read 3, iclass 18, count 0 2006.197.08:18:59.95#ibcon#about to read 4, iclass 18, count 0 2006.197.08:18:59.95#ibcon#read 4, iclass 18, count 0 2006.197.08:18:59.95#ibcon#about to read 5, iclass 18, count 0 2006.197.08:18:59.95#ibcon#read 5, iclass 18, count 0 2006.197.08:18:59.95#ibcon#about to read 6, iclass 18, count 0 2006.197.08:18:59.95#ibcon#read 6, iclass 18, count 0 2006.197.08:18:59.95#ibcon#end of sib2, iclass 18, count 0 2006.197.08:18:59.95#ibcon#*after write, iclass 18, count 0 2006.197.08:18:59.95#ibcon#*before return 0, iclass 18, count 0 2006.197.08:18:59.95#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.197.08:18:59.95#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.197.08:18:59.95#ibcon#about to clear, iclass 18 cls_cnt 0 2006.197.08:18:59.95#ibcon#cleared, iclass 18 cls_cnt 0 2006.197.08:18:59.95$vc4f8/va=8,7 2006.197.08:18:59.95#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.197.08:18:59.95#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.197.08:18:59.95#ibcon#ireg 11 cls_cnt 2 2006.197.08:18:59.95#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.197.08:19:00.01#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.197.08:19:00.01#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.197.08:19:00.01#ibcon#enter wrdev, iclass 20, count 2 2006.197.08:19:00.01#ibcon#first serial, iclass 20, count 2 2006.197.08:19:00.01#ibcon#enter sib2, iclass 20, count 2 2006.197.08:19:00.01#ibcon#flushed, iclass 20, count 2 2006.197.08:19:00.01#ibcon#about to write, iclass 20, count 2 2006.197.08:19:00.01#ibcon#wrote, iclass 20, count 2 2006.197.08:19:00.01#ibcon#about to read 3, iclass 20, count 2 2006.197.08:19:00.03#ibcon#read 3, iclass 20, count 2 2006.197.08:19:00.03#ibcon#about to read 4, iclass 20, count 2 2006.197.08:19:00.03#ibcon#read 4, iclass 20, count 2 2006.197.08:19:00.03#ibcon#about to read 5, iclass 20, count 2 2006.197.08:19:00.03#ibcon#read 5, iclass 20, count 2 2006.197.08:19:00.03#ibcon#about to read 6, iclass 20, count 2 2006.197.08:19:00.03#ibcon#read 6, iclass 20, count 2 2006.197.08:19:00.03#ibcon#end of sib2, iclass 20, count 2 2006.197.08:19:00.03#ibcon#*mode == 0, iclass 20, count 2 2006.197.08:19:00.03#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.197.08:19:00.03#ibcon#[25=AT08-07\r\n] 2006.197.08:19:00.03#ibcon#*before write, iclass 20, count 2 2006.197.08:19:00.03#ibcon#enter sib2, iclass 20, count 2 2006.197.08:19:00.03#ibcon#flushed, iclass 20, count 2 2006.197.08:19:00.03#ibcon#about to write, iclass 20, count 2 2006.197.08:19:00.03#ibcon#wrote, iclass 20, count 2 2006.197.08:19:00.03#ibcon#about to read 3, iclass 20, count 2 2006.197.08:19:00.06#ibcon#read 3, iclass 20, count 2 2006.197.08:19:00.06#ibcon#about to read 4, iclass 20, count 2 2006.197.08:19:00.06#ibcon#read 4, iclass 20, count 2 2006.197.08:19:00.06#ibcon#about to read 5, iclass 20, count 2 2006.197.08:19:00.06#ibcon#read 5, iclass 20, count 2 2006.197.08:19:00.06#ibcon#about to read 6, iclass 20, count 2 2006.197.08:19:00.06#ibcon#read 6, iclass 20, count 2 2006.197.08:19:00.06#ibcon#end of sib2, iclass 20, count 2 2006.197.08:19:00.06#ibcon#*after write, iclass 20, count 2 2006.197.08:19:00.06#ibcon#*before return 0, iclass 20, count 2 2006.197.08:19:00.06#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.197.08:19:00.06#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.197.08:19:00.06#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.197.08:19:00.06#ibcon#ireg 7 cls_cnt 0 2006.197.08:19:00.06#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.197.08:19:00.18#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.197.08:19:00.18#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.197.08:19:00.18#ibcon#enter wrdev, iclass 20, count 0 2006.197.08:19:00.18#ibcon#first serial, iclass 20, count 0 2006.197.08:19:00.18#ibcon#enter sib2, iclass 20, count 0 2006.197.08:19:00.18#ibcon#flushed, iclass 20, count 0 2006.197.08:19:00.18#ibcon#about to write, iclass 20, count 0 2006.197.08:19:00.18#ibcon#wrote, iclass 20, count 0 2006.197.08:19:00.18#ibcon#about to read 3, iclass 20, count 0 2006.197.08:19:00.20#ibcon#read 3, iclass 20, count 0 2006.197.08:19:00.20#ibcon#about to read 4, iclass 20, count 0 2006.197.08:19:00.20#ibcon#read 4, iclass 20, count 0 2006.197.08:19:00.20#ibcon#about to read 5, iclass 20, count 0 2006.197.08:19:00.20#ibcon#read 5, iclass 20, count 0 2006.197.08:19:00.20#ibcon#about to read 6, iclass 20, count 0 2006.197.08:19:00.20#ibcon#read 6, iclass 20, count 0 2006.197.08:19:00.20#ibcon#end of sib2, iclass 20, count 0 2006.197.08:19:00.20#ibcon#*mode == 0, iclass 20, count 0 2006.197.08:19:00.20#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.197.08:19:00.20#ibcon#[25=USB\r\n] 2006.197.08:19:00.20#ibcon#*before write, iclass 20, count 0 2006.197.08:19:00.20#ibcon#enter sib2, iclass 20, count 0 2006.197.08:19:00.20#ibcon#flushed, iclass 20, count 0 2006.197.08:19:00.20#ibcon#about to write, iclass 20, count 0 2006.197.08:19:00.20#ibcon#wrote, iclass 20, count 0 2006.197.08:19:00.20#ibcon#about to read 3, iclass 20, count 0 2006.197.08:19:00.23#ibcon#read 3, iclass 20, count 0 2006.197.08:19:00.23#ibcon#about to read 4, iclass 20, count 0 2006.197.08:19:00.23#ibcon#read 4, iclass 20, count 0 2006.197.08:19:00.23#ibcon#about to read 5, iclass 20, count 0 2006.197.08:19:00.23#ibcon#read 5, iclass 20, count 0 2006.197.08:19:00.23#ibcon#about to read 6, iclass 20, count 0 2006.197.08:19:00.23#ibcon#read 6, iclass 20, count 0 2006.197.08:19:00.23#ibcon#end of sib2, iclass 20, count 0 2006.197.08:19:00.23#ibcon#*after write, iclass 20, count 0 2006.197.08:19:00.23#ibcon#*before return 0, iclass 20, count 0 2006.197.08:19:00.23#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.197.08:19:00.23#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.197.08:19:00.23#ibcon#about to clear, iclass 20 cls_cnt 0 2006.197.08:19:00.23#ibcon#cleared, iclass 20 cls_cnt 0 2006.197.08:19:00.23$vc4f8/vblo=1,632.99 2006.197.08:19:00.23#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.197.08:19:00.23#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.197.08:19:00.23#ibcon#ireg 17 cls_cnt 0 2006.197.08:19:00.23#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.197.08:19:00.23#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.197.08:19:00.23#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.197.08:19:00.23#ibcon#enter wrdev, iclass 22, count 0 2006.197.08:19:00.23#ibcon#first serial, iclass 22, count 0 2006.197.08:19:00.23#ibcon#enter sib2, iclass 22, count 0 2006.197.08:19:00.23#ibcon#flushed, iclass 22, count 0 2006.197.08:19:00.23#ibcon#about to write, iclass 22, count 0 2006.197.08:19:00.23#ibcon#wrote, iclass 22, count 0 2006.197.08:19:00.23#ibcon#about to read 3, iclass 22, count 0 2006.197.08:19:00.25#ibcon#read 3, iclass 22, count 0 2006.197.08:19:00.25#ibcon#about to read 4, iclass 22, count 0 2006.197.08:19:00.25#ibcon#read 4, iclass 22, count 0 2006.197.08:19:00.25#ibcon#about to read 5, iclass 22, count 0 2006.197.08:19:00.25#ibcon#read 5, iclass 22, count 0 2006.197.08:19:00.25#ibcon#about to read 6, iclass 22, count 0 2006.197.08:19:00.25#ibcon#read 6, iclass 22, count 0 2006.197.08:19:00.25#ibcon#end of sib2, iclass 22, count 0 2006.197.08:19:00.25#ibcon#*mode == 0, iclass 22, count 0 2006.197.08:19:00.25#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.197.08:19:00.25#ibcon#[28=FRQ=01,632.99\r\n] 2006.197.08:19:00.25#ibcon#*before write, iclass 22, count 0 2006.197.08:19:00.25#ibcon#enter sib2, iclass 22, count 0 2006.197.08:19:00.25#ibcon#flushed, iclass 22, count 0 2006.197.08:19:00.25#ibcon#about to write, iclass 22, count 0 2006.197.08:19:00.25#ibcon#wrote, iclass 22, count 0 2006.197.08:19:00.25#ibcon#about to read 3, iclass 22, count 0 2006.197.08:19:00.29#ibcon#read 3, iclass 22, count 0 2006.197.08:19:00.29#ibcon#about to read 4, iclass 22, count 0 2006.197.08:19:00.29#ibcon#read 4, iclass 22, count 0 2006.197.08:19:00.29#ibcon#about to read 5, iclass 22, count 0 2006.197.08:19:00.29#ibcon#read 5, iclass 22, count 0 2006.197.08:19:00.29#ibcon#about to read 6, iclass 22, count 0 2006.197.08:19:00.29#ibcon#read 6, iclass 22, count 0 2006.197.08:19:00.29#ibcon#end of sib2, iclass 22, count 0 2006.197.08:19:00.29#ibcon#*after write, iclass 22, count 0 2006.197.08:19:00.29#ibcon#*before return 0, iclass 22, count 0 2006.197.08:19:00.29#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.197.08:19:00.29#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.197.08:19:00.29#ibcon#about to clear, iclass 22 cls_cnt 0 2006.197.08:19:00.29#ibcon#cleared, iclass 22 cls_cnt 0 2006.197.08:19:00.29$vc4f8/vb=1,4 2006.197.08:19:00.29#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.197.08:19:00.29#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.197.08:19:00.29#ibcon#ireg 11 cls_cnt 2 2006.197.08:19:00.29#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.197.08:19:00.29#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.197.08:19:00.29#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.197.08:19:00.29#ibcon#enter wrdev, iclass 24, count 2 2006.197.08:19:00.29#ibcon#first serial, iclass 24, count 2 2006.197.08:19:00.29#ibcon#enter sib2, iclass 24, count 2 2006.197.08:19:00.29#ibcon#flushed, iclass 24, count 2 2006.197.08:19:00.29#ibcon#about to write, iclass 24, count 2 2006.197.08:19:00.29#ibcon#wrote, iclass 24, count 2 2006.197.08:19:00.29#ibcon#about to read 3, iclass 24, count 2 2006.197.08:19:00.31#ibcon#read 3, iclass 24, count 2 2006.197.08:19:00.31#ibcon#about to read 4, iclass 24, count 2 2006.197.08:19:00.31#ibcon#read 4, iclass 24, count 2 2006.197.08:19:00.31#ibcon#about to read 5, iclass 24, count 2 2006.197.08:19:00.31#ibcon#read 5, iclass 24, count 2 2006.197.08:19:00.31#ibcon#about to read 6, iclass 24, count 2 2006.197.08:19:00.31#ibcon#read 6, iclass 24, count 2 2006.197.08:19:00.31#ibcon#end of sib2, iclass 24, count 2 2006.197.08:19:00.31#ibcon#*mode == 0, iclass 24, count 2 2006.197.08:19:00.31#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.197.08:19:00.31#ibcon#[27=AT01-04\r\n] 2006.197.08:19:00.31#ibcon#*before write, iclass 24, count 2 2006.197.08:19:00.31#ibcon#enter sib2, iclass 24, count 2 2006.197.08:19:00.31#ibcon#flushed, iclass 24, count 2 2006.197.08:19:00.31#ibcon#about to write, iclass 24, count 2 2006.197.08:19:00.31#ibcon#wrote, iclass 24, count 2 2006.197.08:19:00.31#ibcon#about to read 3, iclass 24, count 2 2006.197.08:19:00.34#ibcon#read 3, iclass 24, count 2 2006.197.08:19:00.34#ibcon#about to read 4, iclass 24, count 2 2006.197.08:19:00.34#ibcon#read 4, iclass 24, count 2 2006.197.08:19:00.34#ibcon#about to read 5, iclass 24, count 2 2006.197.08:19:00.34#ibcon#read 5, iclass 24, count 2 2006.197.08:19:00.34#ibcon#about to read 6, iclass 24, count 2 2006.197.08:19:00.34#ibcon#read 6, iclass 24, count 2 2006.197.08:19:00.34#ibcon#end of sib2, iclass 24, count 2 2006.197.08:19:00.34#ibcon#*after write, iclass 24, count 2 2006.197.08:19:00.34#ibcon#*before return 0, iclass 24, count 2 2006.197.08:19:00.34#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.197.08:19:00.34#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.197.08:19:00.34#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.197.08:19:00.34#ibcon#ireg 7 cls_cnt 0 2006.197.08:19:00.34#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.197.08:19:00.46#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.197.08:19:00.46#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.197.08:19:00.46#ibcon#enter wrdev, iclass 24, count 0 2006.197.08:19:00.46#ibcon#first serial, iclass 24, count 0 2006.197.08:19:00.46#ibcon#enter sib2, iclass 24, count 0 2006.197.08:19:00.46#ibcon#flushed, iclass 24, count 0 2006.197.08:19:00.46#ibcon#about to write, iclass 24, count 0 2006.197.08:19:00.46#ibcon#wrote, iclass 24, count 0 2006.197.08:19:00.46#ibcon#about to read 3, iclass 24, count 0 2006.197.08:19:00.48#ibcon#read 3, iclass 24, count 0 2006.197.08:19:00.48#ibcon#about to read 4, iclass 24, count 0 2006.197.08:19:00.48#ibcon#read 4, iclass 24, count 0 2006.197.08:19:00.48#ibcon#about to read 5, iclass 24, count 0 2006.197.08:19:00.48#ibcon#read 5, iclass 24, count 0 2006.197.08:19:00.48#ibcon#about to read 6, iclass 24, count 0 2006.197.08:19:00.48#ibcon#read 6, iclass 24, count 0 2006.197.08:19:00.48#ibcon#end of sib2, iclass 24, count 0 2006.197.08:19:00.48#ibcon#*mode == 0, iclass 24, count 0 2006.197.08:19:00.48#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.197.08:19:00.48#ibcon#[27=USB\r\n] 2006.197.08:19:00.48#ibcon#*before write, iclass 24, count 0 2006.197.08:19:00.48#ibcon#enter sib2, iclass 24, count 0 2006.197.08:19:00.48#ibcon#flushed, iclass 24, count 0 2006.197.08:19:00.48#ibcon#about to write, iclass 24, count 0 2006.197.08:19:00.48#ibcon#wrote, iclass 24, count 0 2006.197.08:19:00.48#ibcon#about to read 3, iclass 24, count 0 2006.197.08:19:00.51#ibcon#read 3, iclass 24, count 0 2006.197.08:19:00.51#ibcon#about to read 4, iclass 24, count 0 2006.197.08:19:00.51#ibcon#read 4, iclass 24, count 0 2006.197.08:19:00.51#ibcon#about to read 5, iclass 24, count 0 2006.197.08:19:00.51#ibcon#read 5, iclass 24, count 0 2006.197.08:19:00.51#ibcon#about to read 6, iclass 24, count 0 2006.197.08:19:00.51#ibcon#read 6, iclass 24, count 0 2006.197.08:19:00.51#ibcon#end of sib2, iclass 24, count 0 2006.197.08:19:00.51#ibcon#*after write, iclass 24, count 0 2006.197.08:19:00.51#ibcon#*before return 0, iclass 24, count 0 2006.197.08:19:00.51#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.197.08:19:00.51#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.197.08:19:00.51#ibcon#about to clear, iclass 24 cls_cnt 0 2006.197.08:19:00.51#ibcon#cleared, iclass 24 cls_cnt 0 2006.197.08:19:00.51$vc4f8/vblo=2,640.99 2006.197.08:19:00.51#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.197.08:19:00.51#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.197.08:19:00.51#ibcon#ireg 17 cls_cnt 0 2006.197.08:19:00.51#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.197.08:19:00.51#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.197.08:19:00.51#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.197.08:19:00.51#ibcon#enter wrdev, iclass 26, count 0 2006.197.08:19:00.51#ibcon#first serial, iclass 26, count 0 2006.197.08:19:00.51#ibcon#enter sib2, iclass 26, count 0 2006.197.08:19:00.51#ibcon#flushed, iclass 26, count 0 2006.197.08:19:00.51#ibcon#about to write, iclass 26, count 0 2006.197.08:19:00.51#ibcon#wrote, iclass 26, count 0 2006.197.08:19:00.51#ibcon#about to read 3, iclass 26, count 0 2006.197.08:19:00.53#ibcon#read 3, iclass 26, count 0 2006.197.08:19:00.53#ibcon#about to read 4, iclass 26, count 0 2006.197.08:19:00.53#ibcon#read 4, iclass 26, count 0 2006.197.08:19:00.53#ibcon#about to read 5, iclass 26, count 0 2006.197.08:19:00.53#ibcon#read 5, iclass 26, count 0 2006.197.08:19:00.53#ibcon#about to read 6, iclass 26, count 0 2006.197.08:19:00.53#ibcon#read 6, iclass 26, count 0 2006.197.08:19:00.53#ibcon#end of sib2, iclass 26, count 0 2006.197.08:19:00.53#ibcon#*mode == 0, iclass 26, count 0 2006.197.08:19:00.53#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.197.08:19:00.53#ibcon#[28=FRQ=02,640.99\r\n] 2006.197.08:19:00.53#ibcon#*before write, iclass 26, count 0 2006.197.08:19:00.53#ibcon#enter sib2, iclass 26, count 0 2006.197.08:19:00.53#ibcon#flushed, iclass 26, count 0 2006.197.08:19:00.53#ibcon#about to write, iclass 26, count 0 2006.197.08:19:00.53#ibcon#wrote, iclass 26, count 0 2006.197.08:19:00.53#ibcon#about to read 3, iclass 26, count 0 2006.197.08:19:00.57#ibcon#read 3, iclass 26, count 0 2006.197.08:19:00.57#ibcon#about to read 4, iclass 26, count 0 2006.197.08:19:00.57#ibcon#read 4, iclass 26, count 0 2006.197.08:19:00.57#ibcon#about to read 5, iclass 26, count 0 2006.197.08:19:00.57#ibcon#read 5, iclass 26, count 0 2006.197.08:19:00.57#ibcon#about to read 6, iclass 26, count 0 2006.197.08:19:00.57#ibcon#read 6, iclass 26, count 0 2006.197.08:19:00.57#ibcon#end of sib2, iclass 26, count 0 2006.197.08:19:00.57#ibcon#*after write, iclass 26, count 0 2006.197.08:19:00.57#ibcon#*before return 0, iclass 26, count 0 2006.197.08:19:00.57#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.197.08:19:00.57#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.197.08:19:00.57#ibcon#about to clear, iclass 26 cls_cnt 0 2006.197.08:19:00.57#ibcon#cleared, iclass 26 cls_cnt 0 2006.197.08:19:00.57$vc4f8/vb=2,4 2006.197.08:19:00.57#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.197.08:19:00.57#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.197.08:19:00.57#ibcon#ireg 11 cls_cnt 2 2006.197.08:19:00.57#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.197.08:19:00.63#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.197.08:19:00.63#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.197.08:19:00.63#ibcon#enter wrdev, iclass 28, count 2 2006.197.08:19:00.63#ibcon#first serial, iclass 28, count 2 2006.197.08:19:00.63#ibcon#enter sib2, iclass 28, count 2 2006.197.08:19:00.63#ibcon#flushed, iclass 28, count 2 2006.197.08:19:00.63#ibcon#about to write, iclass 28, count 2 2006.197.08:19:00.63#ibcon#wrote, iclass 28, count 2 2006.197.08:19:00.63#ibcon#about to read 3, iclass 28, count 2 2006.197.08:19:00.65#ibcon#read 3, iclass 28, count 2 2006.197.08:19:00.65#ibcon#about to read 4, iclass 28, count 2 2006.197.08:19:00.65#ibcon#read 4, iclass 28, count 2 2006.197.08:19:00.65#ibcon#about to read 5, iclass 28, count 2 2006.197.08:19:00.65#ibcon#read 5, iclass 28, count 2 2006.197.08:19:00.65#ibcon#about to read 6, iclass 28, count 2 2006.197.08:19:00.65#ibcon#read 6, iclass 28, count 2 2006.197.08:19:00.65#ibcon#end of sib2, iclass 28, count 2 2006.197.08:19:00.65#ibcon#*mode == 0, iclass 28, count 2 2006.197.08:19:00.65#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.197.08:19:00.65#ibcon#[27=AT02-04\r\n] 2006.197.08:19:00.65#ibcon#*before write, iclass 28, count 2 2006.197.08:19:00.65#ibcon#enter sib2, iclass 28, count 2 2006.197.08:19:00.65#ibcon#flushed, iclass 28, count 2 2006.197.08:19:00.65#ibcon#about to write, iclass 28, count 2 2006.197.08:19:00.65#ibcon#wrote, iclass 28, count 2 2006.197.08:19:00.65#ibcon#about to read 3, iclass 28, count 2 2006.197.08:19:00.68#ibcon#read 3, iclass 28, count 2 2006.197.08:19:00.68#ibcon#about to read 4, iclass 28, count 2 2006.197.08:19:00.68#ibcon#read 4, iclass 28, count 2 2006.197.08:19:00.68#ibcon#about to read 5, iclass 28, count 2 2006.197.08:19:00.68#ibcon#read 5, iclass 28, count 2 2006.197.08:19:00.68#ibcon#about to read 6, iclass 28, count 2 2006.197.08:19:00.68#ibcon#read 6, iclass 28, count 2 2006.197.08:19:00.68#ibcon#end of sib2, iclass 28, count 2 2006.197.08:19:00.68#ibcon#*after write, iclass 28, count 2 2006.197.08:19:00.68#ibcon#*before return 0, iclass 28, count 2 2006.197.08:19:00.68#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.197.08:19:00.68#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.197.08:19:00.68#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.197.08:19:00.68#ibcon#ireg 7 cls_cnt 0 2006.197.08:19:00.68#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.197.08:19:00.80#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.197.08:19:00.80#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.197.08:19:00.80#ibcon#enter wrdev, iclass 28, count 0 2006.197.08:19:00.80#ibcon#first serial, iclass 28, count 0 2006.197.08:19:00.80#ibcon#enter sib2, iclass 28, count 0 2006.197.08:19:00.80#ibcon#flushed, iclass 28, count 0 2006.197.08:19:00.80#ibcon#about to write, iclass 28, count 0 2006.197.08:19:00.80#ibcon#wrote, iclass 28, count 0 2006.197.08:19:00.80#ibcon#about to read 3, iclass 28, count 0 2006.197.08:19:00.82#ibcon#read 3, iclass 28, count 0 2006.197.08:19:00.82#ibcon#about to read 4, iclass 28, count 0 2006.197.08:19:00.82#ibcon#read 4, iclass 28, count 0 2006.197.08:19:00.82#ibcon#about to read 5, iclass 28, count 0 2006.197.08:19:00.82#ibcon#read 5, iclass 28, count 0 2006.197.08:19:00.82#ibcon#about to read 6, iclass 28, count 0 2006.197.08:19:00.82#ibcon#read 6, iclass 28, count 0 2006.197.08:19:00.82#ibcon#end of sib2, iclass 28, count 0 2006.197.08:19:00.82#ibcon#*mode == 0, iclass 28, count 0 2006.197.08:19:00.82#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.197.08:19:00.82#ibcon#[27=USB\r\n] 2006.197.08:19:00.82#ibcon#*before write, iclass 28, count 0 2006.197.08:19:00.82#ibcon#enter sib2, iclass 28, count 0 2006.197.08:19:00.82#ibcon#flushed, iclass 28, count 0 2006.197.08:19:00.82#ibcon#about to write, iclass 28, count 0 2006.197.08:19:00.82#ibcon#wrote, iclass 28, count 0 2006.197.08:19:00.82#ibcon#about to read 3, iclass 28, count 0 2006.197.08:19:00.85#ibcon#read 3, iclass 28, count 0 2006.197.08:19:00.85#ibcon#about to read 4, iclass 28, count 0 2006.197.08:19:00.85#ibcon#read 4, iclass 28, count 0 2006.197.08:19:00.85#ibcon#about to read 5, iclass 28, count 0 2006.197.08:19:00.85#ibcon#read 5, iclass 28, count 0 2006.197.08:19:00.85#ibcon#about to read 6, iclass 28, count 0 2006.197.08:19:00.85#ibcon#read 6, iclass 28, count 0 2006.197.08:19:00.85#ibcon#end of sib2, iclass 28, count 0 2006.197.08:19:00.85#ibcon#*after write, iclass 28, count 0 2006.197.08:19:00.85#ibcon#*before return 0, iclass 28, count 0 2006.197.08:19:00.85#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.197.08:19:00.85#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.197.08:19:00.85#ibcon#about to clear, iclass 28 cls_cnt 0 2006.197.08:19:00.85#ibcon#cleared, iclass 28 cls_cnt 0 2006.197.08:19:00.85$vc4f8/vblo=3,656.99 2006.197.08:19:00.85#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.197.08:19:00.85#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.197.08:19:00.85#ibcon#ireg 17 cls_cnt 0 2006.197.08:19:00.85#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.197.08:19:00.85#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.197.08:19:00.85#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.197.08:19:00.85#ibcon#enter wrdev, iclass 30, count 0 2006.197.08:19:00.85#ibcon#first serial, iclass 30, count 0 2006.197.08:19:00.85#ibcon#enter sib2, iclass 30, count 0 2006.197.08:19:00.85#ibcon#flushed, iclass 30, count 0 2006.197.08:19:00.85#ibcon#about to write, iclass 30, count 0 2006.197.08:19:00.85#ibcon#wrote, iclass 30, count 0 2006.197.08:19:00.85#ibcon#about to read 3, iclass 30, count 0 2006.197.08:19:00.87#ibcon#read 3, iclass 30, count 0 2006.197.08:19:00.87#ibcon#about to read 4, iclass 30, count 0 2006.197.08:19:00.87#ibcon#read 4, iclass 30, count 0 2006.197.08:19:00.87#ibcon#about to read 5, iclass 30, count 0 2006.197.08:19:00.87#ibcon#read 5, iclass 30, count 0 2006.197.08:19:00.87#ibcon#about to read 6, iclass 30, count 0 2006.197.08:19:00.87#ibcon#read 6, iclass 30, count 0 2006.197.08:19:00.87#ibcon#end of sib2, iclass 30, count 0 2006.197.08:19:00.87#ibcon#*mode == 0, iclass 30, count 0 2006.197.08:19:00.87#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.197.08:19:00.87#ibcon#[28=FRQ=03,656.99\r\n] 2006.197.08:19:00.87#ibcon#*before write, iclass 30, count 0 2006.197.08:19:00.87#ibcon#enter sib2, iclass 30, count 0 2006.197.08:19:00.87#ibcon#flushed, iclass 30, count 0 2006.197.08:19:00.87#ibcon#about to write, iclass 30, count 0 2006.197.08:19:00.87#ibcon#wrote, iclass 30, count 0 2006.197.08:19:00.87#ibcon#about to read 3, iclass 30, count 0 2006.197.08:19:00.91#ibcon#read 3, iclass 30, count 0 2006.197.08:19:00.91#ibcon#about to read 4, iclass 30, count 0 2006.197.08:19:00.91#ibcon#read 4, iclass 30, count 0 2006.197.08:19:00.91#ibcon#about to read 5, iclass 30, count 0 2006.197.08:19:00.91#ibcon#read 5, iclass 30, count 0 2006.197.08:19:00.91#ibcon#about to read 6, iclass 30, count 0 2006.197.08:19:00.91#ibcon#read 6, iclass 30, count 0 2006.197.08:19:00.91#ibcon#end of sib2, iclass 30, count 0 2006.197.08:19:00.91#ibcon#*after write, iclass 30, count 0 2006.197.08:19:00.91#ibcon#*before return 0, iclass 30, count 0 2006.197.08:19:00.91#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.197.08:19:00.91#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.197.08:19:00.91#ibcon#about to clear, iclass 30 cls_cnt 0 2006.197.08:19:00.91#ibcon#cleared, iclass 30 cls_cnt 0 2006.197.08:19:00.91$vc4f8/vb=3,4 2006.197.08:19:00.91#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.197.08:19:00.91#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.197.08:19:00.91#ibcon#ireg 11 cls_cnt 2 2006.197.08:19:00.91#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.197.08:19:00.97#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.197.08:19:00.97#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.197.08:19:00.97#ibcon#enter wrdev, iclass 32, count 2 2006.197.08:19:00.97#ibcon#first serial, iclass 32, count 2 2006.197.08:19:00.97#ibcon#enter sib2, iclass 32, count 2 2006.197.08:19:00.97#ibcon#flushed, iclass 32, count 2 2006.197.08:19:00.97#ibcon#about to write, iclass 32, count 2 2006.197.08:19:00.97#ibcon#wrote, iclass 32, count 2 2006.197.08:19:00.97#ibcon#about to read 3, iclass 32, count 2 2006.197.08:19:00.99#ibcon#read 3, iclass 32, count 2 2006.197.08:19:00.99#ibcon#about to read 4, iclass 32, count 2 2006.197.08:19:00.99#ibcon#read 4, iclass 32, count 2 2006.197.08:19:00.99#ibcon#about to read 5, iclass 32, count 2 2006.197.08:19:00.99#ibcon#read 5, iclass 32, count 2 2006.197.08:19:00.99#ibcon#about to read 6, iclass 32, count 2 2006.197.08:19:00.99#ibcon#read 6, iclass 32, count 2 2006.197.08:19:00.99#ibcon#end of sib2, iclass 32, count 2 2006.197.08:19:00.99#ibcon#*mode == 0, iclass 32, count 2 2006.197.08:19:00.99#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.197.08:19:00.99#ibcon#[27=AT03-04\r\n] 2006.197.08:19:00.99#ibcon#*before write, iclass 32, count 2 2006.197.08:19:00.99#ibcon#enter sib2, iclass 32, count 2 2006.197.08:19:00.99#ibcon#flushed, iclass 32, count 2 2006.197.08:19:00.99#ibcon#about to write, iclass 32, count 2 2006.197.08:19:00.99#ibcon#wrote, iclass 32, count 2 2006.197.08:19:00.99#ibcon#about to read 3, iclass 32, count 2 2006.197.08:19:01.02#ibcon#read 3, iclass 32, count 2 2006.197.08:19:01.02#ibcon#about to read 4, iclass 32, count 2 2006.197.08:19:01.02#ibcon#read 4, iclass 32, count 2 2006.197.08:19:01.02#ibcon#about to read 5, iclass 32, count 2 2006.197.08:19:01.02#ibcon#read 5, iclass 32, count 2 2006.197.08:19:01.02#ibcon#about to read 6, iclass 32, count 2 2006.197.08:19:01.02#ibcon#read 6, iclass 32, count 2 2006.197.08:19:01.02#ibcon#end of sib2, iclass 32, count 2 2006.197.08:19:01.02#ibcon#*after write, iclass 32, count 2 2006.197.08:19:01.02#ibcon#*before return 0, iclass 32, count 2 2006.197.08:19:01.02#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.197.08:19:01.02#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.197.08:19:01.02#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.197.08:19:01.02#ibcon#ireg 7 cls_cnt 0 2006.197.08:19:01.02#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.197.08:19:01.14#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.197.08:19:01.14#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.197.08:19:01.14#ibcon#enter wrdev, iclass 32, count 0 2006.197.08:19:01.14#ibcon#first serial, iclass 32, count 0 2006.197.08:19:01.14#ibcon#enter sib2, iclass 32, count 0 2006.197.08:19:01.14#ibcon#flushed, iclass 32, count 0 2006.197.08:19:01.14#ibcon#about to write, iclass 32, count 0 2006.197.08:19:01.14#ibcon#wrote, iclass 32, count 0 2006.197.08:19:01.14#ibcon#about to read 3, iclass 32, count 0 2006.197.08:19:01.16#ibcon#read 3, iclass 32, count 0 2006.197.08:19:01.16#ibcon#about to read 4, iclass 32, count 0 2006.197.08:19:01.16#ibcon#read 4, iclass 32, count 0 2006.197.08:19:01.16#ibcon#about to read 5, iclass 32, count 0 2006.197.08:19:01.16#ibcon#read 5, iclass 32, count 0 2006.197.08:19:01.16#ibcon#about to read 6, iclass 32, count 0 2006.197.08:19:01.16#ibcon#read 6, iclass 32, count 0 2006.197.08:19:01.16#ibcon#end of sib2, iclass 32, count 0 2006.197.08:19:01.16#ibcon#*mode == 0, iclass 32, count 0 2006.197.08:19:01.16#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.197.08:19:01.16#ibcon#[27=USB\r\n] 2006.197.08:19:01.16#ibcon#*before write, iclass 32, count 0 2006.197.08:19:01.16#ibcon#enter sib2, iclass 32, count 0 2006.197.08:19:01.16#ibcon#flushed, iclass 32, count 0 2006.197.08:19:01.16#ibcon#about to write, iclass 32, count 0 2006.197.08:19:01.16#ibcon#wrote, iclass 32, count 0 2006.197.08:19:01.16#ibcon#about to read 3, iclass 32, count 0 2006.197.08:19:01.19#ibcon#read 3, iclass 32, count 0 2006.197.08:19:01.19#ibcon#about to read 4, iclass 32, count 0 2006.197.08:19:01.19#ibcon#read 4, iclass 32, count 0 2006.197.08:19:01.19#ibcon#about to read 5, iclass 32, count 0 2006.197.08:19:01.19#ibcon#read 5, iclass 32, count 0 2006.197.08:19:01.19#ibcon#about to read 6, iclass 32, count 0 2006.197.08:19:01.19#ibcon#read 6, iclass 32, count 0 2006.197.08:19:01.19#ibcon#end of sib2, iclass 32, count 0 2006.197.08:19:01.19#ibcon#*after write, iclass 32, count 0 2006.197.08:19:01.19#ibcon#*before return 0, iclass 32, count 0 2006.197.08:19:01.19#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.197.08:19:01.19#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.197.08:19:01.19#ibcon#about to clear, iclass 32 cls_cnt 0 2006.197.08:19:01.19#ibcon#cleared, iclass 32 cls_cnt 0 2006.197.08:19:01.19$vc4f8/vblo=4,712.99 2006.197.08:19:01.19#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.197.08:19:01.19#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.197.08:19:01.19#ibcon#ireg 17 cls_cnt 0 2006.197.08:19:01.19#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.197.08:19:01.19#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.197.08:19:01.19#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.197.08:19:01.19#ibcon#enter wrdev, iclass 34, count 0 2006.197.08:19:01.19#ibcon#first serial, iclass 34, count 0 2006.197.08:19:01.19#ibcon#enter sib2, iclass 34, count 0 2006.197.08:19:01.19#ibcon#flushed, iclass 34, count 0 2006.197.08:19:01.19#ibcon#about to write, iclass 34, count 0 2006.197.08:19:01.19#ibcon#wrote, iclass 34, count 0 2006.197.08:19:01.19#ibcon#about to read 3, iclass 34, count 0 2006.197.08:19:01.21#ibcon#read 3, iclass 34, count 0 2006.197.08:19:01.21#ibcon#about to read 4, iclass 34, count 0 2006.197.08:19:01.21#ibcon#read 4, iclass 34, count 0 2006.197.08:19:01.21#ibcon#about to read 5, iclass 34, count 0 2006.197.08:19:01.21#ibcon#read 5, iclass 34, count 0 2006.197.08:19:01.21#ibcon#about to read 6, iclass 34, count 0 2006.197.08:19:01.21#ibcon#read 6, iclass 34, count 0 2006.197.08:19:01.21#ibcon#end of sib2, iclass 34, count 0 2006.197.08:19:01.21#ibcon#*mode == 0, iclass 34, count 0 2006.197.08:19:01.21#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.197.08:19:01.21#ibcon#[28=FRQ=04,712.99\r\n] 2006.197.08:19:01.21#ibcon#*before write, iclass 34, count 0 2006.197.08:19:01.21#ibcon#enter sib2, iclass 34, count 0 2006.197.08:19:01.21#ibcon#flushed, iclass 34, count 0 2006.197.08:19:01.21#ibcon#about to write, iclass 34, count 0 2006.197.08:19:01.21#ibcon#wrote, iclass 34, count 0 2006.197.08:19:01.21#ibcon#about to read 3, iclass 34, count 0 2006.197.08:19:01.25#ibcon#read 3, iclass 34, count 0 2006.197.08:19:01.25#ibcon#about to read 4, iclass 34, count 0 2006.197.08:19:01.25#ibcon#read 4, iclass 34, count 0 2006.197.08:19:01.25#ibcon#about to read 5, iclass 34, count 0 2006.197.08:19:01.25#ibcon#read 5, iclass 34, count 0 2006.197.08:19:01.25#ibcon#about to read 6, iclass 34, count 0 2006.197.08:19:01.25#ibcon#read 6, iclass 34, count 0 2006.197.08:19:01.25#ibcon#end of sib2, iclass 34, count 0 2006.197.08:19:01.25#ibcon#*after write, iclass 34, count 0 2006.197.08:19:01.25#ibcon#*before return 0, iclass 34, count 0 2006.197.08:19:01.25#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.197.08:19:01.25#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.197.08:19:01.25#ibcon#about to clear, iclass 34 cls_cnt 0 2006.197.08:19:01.25#ibcon#cleared, iclass 34 cls_cnt 0 2006.197.08:19:01.25$vc4f8/vb=4,4 2006.197.08:19:01.25#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.197.08:19:01.25#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.197.08:19:01.25#ibcon#ireg 11 cls_cnt 2 2006.197.08:19:01.25#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.197.08:19:01.31#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.197.08:19:01.31#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.197.08:19:01.31#ibcon#enter wrdev, iclass 36, count 2 2006.197.08:19:01.31#ibcon#first serial, iclass 36, count 2 2006.197.08:19:01.31#ibcon#enter sib2, iclass 36, count 2 2006.197.08:19:01.31#ibcon#flushed, iclass 36, count 2 2006.197.08:19:01.31#ibcon#about to write, iclass 36, count 2 2006.197.08:19:01.31#ibcon#wrote, iclass 36, count 2 2006.197.08:19:01.31#ibcon#about to read 3, iclass 36, count 2 2006.197.08:19:01.33#ibcon#read 3, iclass 36, count 2 2006.197.08:19:01.33#ibcon#about to read 4, iclass 36, count 2 2006.197.08:19:01.33#ibcon#read 4, iclass 36, count 2 2006.197.08:19:01.33#ibcon#about to read 5, iclass 36, count 2 2006.197.08:19:01.33#ibcon#read 5, iclass 36, count 2 2006.197.08:19:01.33#ibcon#about to read 6, iclass 36, count 2 2006.197.08:19:01.33#ibcon#read 6, iclass 36, count 2 2006.197.08:19:01.33#ibcon#end of sib2, iclass 36, count 2 2006.197.08:19:01.33#ibcon#*mode == 0, iclass 36, count 2 2006.197.08:19:01.33#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.197.08:19:01.33#ibcon#[27=AT04-04\r\n] 2006.197.08:19:01.33#ibcon#*before write, iclass 36, count 2 2006.197.08:19:01.33#ibcon#enter sib2, iclass 36, count 2 2006.197.08:19:01.33#ibcon#flushed, iclass 36, count 2 2006.197.08:19:01.33#ibcon#about to write, iclass 36, count 2 2006.197.08:19:01.33#ibcon#wrote, iclass 36, count 2 2006.197.08:19:01.33#ibcon#about to read 3, iclass 36, count 2 2006.197.08:19:01.36#ibcon#read 3, iclass 36, count 2 2006.197.08:19:01.36#ibcon#about to read 4, iclass 36, count 2 2006.197.08:19:01.36#ibcon#read 4, iclass 36, count 2 2006.197.08:19:01.36#ibcon#about to read 5, iclass 36, count 2 2006.197.08:19:01.36#ibcon#read 5, iclass 36, count 2 2006.197.08:19:01.36#ibcon#about to read 6, iclass 36, count 2 2006.197.08:19:01.36#ibcon#read 6, iclass 36, count 2 2006.197.08:19:01.36#ibcon#end of sib2, iclass 36, count 2 2006.197.08:19:01.36#ibcon#*after write, iclass 36, count 2 2006.197.08:19:01.36#ibcon#*before return 0, iclass 36, count 2 2006.197.08:19:01.36#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.197.08:19:01.36#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.197.08:19:01.36#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.197.08:19:01.36#ibcon#ireg 7 cls_cnt 0 2006.197.08:19:01.36#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.197.08:19:01.48#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.197.08:19:01.48#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.197.08:19:01.48#ibcon#enter wrdev, iclass 36, count 0 2006.197.08:19:01.48#ibcon#first serial, iclass 36, count 0 2006.197.08:19:01.48#ibcon#enter sib2, iclass 36, count 0 2006.197.08:19:01.48#ibcon#flushed, iclass 36, count 0 2006.197.08:19:01.48#ibcon#about to write, iclass 36, count 0 2006.197.08:19:01.48#ibcon#wrote, iclass 36, count 0 2006.197.08:19:01.48#ibcon#about to read 3, iclass 36, count 0 2006.197.08:19:01.50#ibcon#read 3, iclass 36, count 0 2006.197.08:19:01.50#ibcon#about to read 4, iclass 36, count 0 2006.197.08:19:01.50#ibcon#read 4, iclass 36, count 0 2006.197.08:19:01.50#ibcon#about to read 5, iclass 36, count 0 2006.197.08:19:01.50#ibcon#read 5, iclass 36, count 0 2006.197.08:19:01.50#ibcon#about to read 6, iclass 36, count 0 2006.197.08:19:01.50#ibcon#read 6, iclass 36, count 0 2006.197.08:19:01.50#ibcon#end of sib2, iclass 36, count 0 2006.197.08:19:01.50#ibcon#*mode == 0, iclass 36, count 0 2006.197.08:19:01.50#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.197.08:19:01.50#ibcon#[27=USB\r\n] 2006.197.08:19:01.50#ibcon#*before write, iclass 36, count 0 2006.197.08:19:01.50#ibcon#enter sib2, iclass 36, count 0 2006.197.08:19:01.50#ibcon#flushed, iclass 36, count 0 2006.197.08:19:01.50#ibcon#about to write, iclass 36, count 0 2006.197.08:19:01.50#ibcon#wrote, iclass 36, count 0 2006.197.08:19:01.50#ibcon#about to read 3, iclass 36, count 0 2006.197.08:19:01.53#ibcon#read 3, iclass 36, count 0 2006.197.08:19:01.53#ibcon#about to read 4, iclass 36, count 0 2006.197.08:19:01.53#ibcon#read 4, iclass 36, count 0 2006.197.08:19:01.53#ibcon#about to read 5, iclass 36, count 0 2006.197.08:19:01.53#ibcon#read 5, iclass 36, count 0 2006.197.08:19:01.53#ibcon#about to read 6, iclass 36, count 0 2006.197.08:19:01.53#ibcon#read 6, iclass 36, count 0 2006.197.08:19:01.53#ibcon#end of sib2, iclass 36, count 0 2006.197.08:19:01.53#ibcon#*after write, iclass 36, count 0 2006.197.08:19:01.53#ibcon#*before return 0, iclass 36, count 0 2006.197.08:19:01.53#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.197.08:19:01.53#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.197.08:19:01.53#ibcon#about to clear, iclass 36 cls_cnt 0 2006.197.08:19:01.53#ibcon#cleared, iclass 36 cls_cnt 0 2006.197.08:19:01.53$vc4f8/vblo=5,744.99 2006.197.08:19:01.53#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.197.08:19:01.53#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.197.08:19:01.53#ibcon#ireg 17 cls_cnt 0 2006.197.08:19:01.53#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.197.08:19:01.53#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.197.08:19:01.53#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.197.08:19:01.53#ibcon#enter wrdev, iclass 38, count 0 2006.197.08:19:01.53#ibcon#first serial, iclass 38, count 0 2006.197.08:19:01.53#ibcon#enter sib2, iclass 38, count 0 2006.197.08:19:01.53#ibcon#flushed, iclass 38, count 0 2006.197.08:19:01.53#ibcon#about to write, iclass 38, count 0 2006.197.08:19:01.53#ibcon#wrote, iclass 38, count 0 2006.197.08:19:01.53#ibcon#about to read 3, iclass 38, count 0 2006.197.08:19:01.55#ibcon#read 3, iclass 38, count 0 2006.197.08:19:01.55#ibcon#about to read 4, iclass 38, count 0 2006.197.08:19:01.55#ibcon#read 4, iclass 38, count 0 2006.197.08:19:01.55#ibcon#about to read 5, iclass 38, count 0 2006.197.08:19:01.55#ibcon#read 5, iclass 38, count 0 2006.197.08:19:01.55#ibcon#about to read 6, iclass 38, count 0 2006.197.08:19:01.55#ibcon#read 6, iclass 38, count 0 2006.197.08:19:01.55#ibcon#end of sib2, iclass 38, count 0 2006.197.08:19:01.55#ibcon#*mode == 0, iclass 38, count 0 2006.197.08:19:01.55#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.197.08:19:01.55#ibcon#[28=FRQ=05,744.99\r\n] 2006.197.08:19:01.55#ibcon#*before write, iclass 38, count 0 2006.197.08:19:01.55#ibcon#enter sib2, iclass 38, count 0 2006.197.08:19:01.55#ibcon#flushed, iclass 38, count 0 2006.197.08:19:01.55#ibcon#about to write, iclass 38, count 0 2006.197.08:19:01.55#ibcon#wrote, iclass 38, count 0 2006.197.08:19:01.55#ibcon#about to read 3, iclass 38, count 0 2006.197.08:19:01.59#ibcon#read 3, iclass 38, count 0 2006.197.08:19:01.59#ibcon#about to read 4, iclass 38, count 0 2006.197.08:19:01.59#ibcon#read 4, iclass 38, count 0 2006.197.08:19:01.59#ibcon#about to read 5, iclass 38, count 0 2006.197.08:19:01.59#ibcon#read 5, iclass 38, count 0 2006.197.08:19:01.59#ibcon#about to read 6, iclass 38, count 0 2006.197.08:19:01.59#ibcon#read 6, iclass 38, count 0 2006.197.08:19:01.59#ibcon#end of sib2, iclass 38, count 0 2006.197.08:19:01.59#ibcon#*after write, iclass 38, count 0 2006.197.08:19:01.59#ibcon#*before return 0, iclass 38, count 0 2006.197.08:19:01.59#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.197.08:19:01.59#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.197.08:19:01.59#ibcon#about to clear, iclass 38 cls_cnt 0 2006.197.08:19:01.59#ibcon#cleared, iclass 38 cls_cnt 0 2006.197.08:19:01.59$vc4f8/vb=5,4 2006.197.08:19:01.59#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.197.08:19:01.59#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.197.08:19:01.59#ibcon#ireg 11 cls_cnt 2 2006.197.08:19:01.59#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.197.08:19:01.65#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.197.08:19:01.65#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.197.08:19:01.65#ibcon#enter wrdev, iclass 40, count 2 2006.197.08:19:01.65#ibcon#first serial, iclass 40, count 2 2006.197.08:19:01.65#ibcon#enter sib2, iclass 40, count 2 2006.197.08:19:01.65#ibcon#flushed, iclass 40, count 2 2006.197.08:19:01.65#ibcon#about to write, iclass 40, count 2 2006.197.08:19:01.65#ibcon#wrote, iclass 40, count 2 2006.197.08:19:01.65#ibcon#about to read 3, iclass 40, count 2 2006.197.08:19:01.67#ibcon#read 3, iclass 40, count 2 2006.197.08:19:01.67#ibcon#about to read 4, iclass 40, count 2 2006.197.08:19:01.67#ibcon#read 4, iclass 40, count 2 2006.197.08:19:01.67#ibcon#about to read 5, iclass 40, count 2 2006.197.08:19:01.67#ibcon#read 5, iclass 40, count 2 2006.197.08:19:01.67#ibcon#about to read 6, iclass 40, count 2 2006.197.08:19:01.67#ibcon#read 6, iclass 40, count 2 2006.197.08:19:01.67#ibcon#end of sib2, iclass 40, count 2 2006.197.08:19:01.67#ibcon#*mode == 0, iclass 40, count 2 2006.197.08:19:01.67#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.197.08:19:01.67#ibcon#[27=AT05-04\r\n] 2006.197.08:19:01.67#ibcon#*before write, iclass 40, count 2 2006.197.08:19:01.67#ibcon#enter sib2, iclass 40, count 2 2006.197.08:19:01.67#ibcon#flushed, iclass 40, count 2 2006.197.08:19:01.67#ibcon#about to write, iclass 40, count 2 2006.197.08:19:01.67#ibcon#wrote, iclass 40, count 2 2006.197.08:19:01.67#ibcon#about to read 3, iclass 40, count 2 2006.197.08:19:01.70#ibcon#read 3, iclass 40, count 2 2006.197.08:19:01.70#ibcon#about to read 4, iclass 40, count 2 2006.197.08:19:01.70#ibcon#read 4, iclass 40, count 2 2006.197.08:19:01.70#ibcon#about to read 5, iclass 40, count 2 2006.197.08:19:01.70#ibcon#read 5, iclass 40, count 2 2006.197.08:19:01.70#ibcon#about to read 6, iclass 40, count 2 2006.197.08:19:01.70#ibcon#read 6, iclass 40, count 2 2006.197.08:19:01.70#ibcon#end of sib2, iclass 40, count 2 2006.197.08:19:01.70#ibcon#*after write, iclass 40, count 2 2006.197.08:19:01.70#ibcon#*before return 0, iclass 40, count 2 2006.197.08:19:01.70#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.197.08:19:01.70#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.197.08:19:01.70#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.197.08:19:01.70#ibcon#ireg 7 cls_cnt 0 2006.197.08:19:01.70#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.197.08:19:01.82#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.197.08:19:01.82#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.197.08:19:01.82#ibcon#enter wrdev, iclass 40, count 0 2006.197.08:19:01.82#ibcon#first serial, iclass 40, count 0 2006.197.08:19:01.82#ibcon#enter sib2, iclass 40, count 0 2006.197.08:19:01.82#ibcon#flushed, iclass 40, count 0 2006.197.08:19:01.82#ibcon#about to write, iclass 40, count 0 2006.197.08:19:01.82#ibcon#wrote, iclass 40, count 0 2006.197.08:19:01.82#ibcon#about to read 3, iclass 40, count 0 2006.197.08:19:01.84#ibcon#read 3, iclass 40, count 0 2006.197.08:19:01.84#ibcon#about to read 4, iclass 40, count 0 2006.197.08:19:01.84#ibcon#read 4, iclass 40, count 0 2006.197.08:19:01.84#ibcon#about to read 5, iclass 40, count 0 2006.197.08:19:01.84#ibcon#read 5, iclass 40, count 0 2006.197.08:19:01.84#ibcon#about to read 6, iclass 40, count 0 2006.197.08:19:01.84#ibcon#read 6, iclass 40, count 0 2006.197.08:19:01.84#ibcon#end of sib2, iclass 40, count 0 2006.197.08:19:01.84#ibcon#*mode == 0, iclass 40, count 0 2006.197.08:19:01.84#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.197.08:19:01.84#ibcon#[27=USB\r\n] 2006.197.08:19:01.84#ibcon#*before write, iclass 40, count 0 2006.197.08:19:01.84#ibcon#enter sib2, iclass 40, count 0 2006.197.08:19:01.84#ibcon#flushed, iclass 40, count 0 2006.197.08:19:01.84#ibcon#about to write, iclass 40, count 0 2006.197.08:19:01.84#ibcon#wrote, iclass 40, count 0 2006.197.08:19:01.84#ibcon#about to read 3, iclass 40, count 0 2006.197.08:19:01.87#ibcon#read 3, iclass 40, count 0 2006.197.08:19:01.87#ibcon#about to read 4, iclass 40, count 0 2006.197.08:19:01.87#ibcon#read 4, iclass 40, count 0 2006.197.08:19:01.87#ibcon#about to read 5, iclass 40, count 0 2006.197.08:19:01.87#ibcon#read 5, iclass 40, count 0 2006.197.08:19:01.87#ibcon#about to read 6, iclass 40, count 0 2006.197.08:19:01.87#ibcon#read 6, iclass 40, count 0 2006.197.08:19:01.87#ibcon#end of sib2, iclass 40, count 0 2006.197.08:19:01.87#ibcon#*after write, iclass 40, count 0 2006.197.08:19:01.87#ibcon#*before return 0, iclass 40, count 0 2006.197.08:19:01.87#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.197.08:19:01.87#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.197.08:19:01.87#ibcon#about to clear, iclass 40 cls_cnt 0 2006.197.08:19:01.87#ibcon#cleared, iclass 40 cls_cnt 0 2006.197.08:19:01.87$vc4f8/vblo=6,752.99 2006.197.08:19:01.87#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.197.08:19:01.87#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.197.08:19:01.87#ibcon#ireg 17 cls_cnt 0 2006.197.08:19:01.87#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.197.08:19:01.87#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.197.08:19:01.87#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.197.08:19:01.87#ibcon#enter wrdev, iclass 4, count 0 2006.197.08:19:01.87#ibcon#first serial, iclass 4, count 0 2006.197.08:19:01.87#ibcon#enter sib2, iclass 4, count 0 2006.197.08:19:01.87#ibcon#flushed, iclass 4, count 0 2006.197.08:19:01.87#ibcon#about to write, iclass 4, count 0 2006.197.08:19:01.87#ibcon#wrote, iclass 4, count 0 2006.197.08:19:01.87#ibcon#about to read 3, iclass 4, count 0 2006.197.08:19:01.89#ibcon#read 3, iclass 4, count 0 2006.197.08:19:01.89#ibcon#about to read 4, iclass 4, count 0 2006.197.08:19:01.89#ibcon#read 4, iclass 4, count 0 2006.197.08:19:01.89#ibcon#about to read 5, iclass 4, count 0 2006.197.08:19:01.89#ibcon#read 5, iclass 4, count 0 2006.197.08:19:01.89#ibcon#about to read 6, iclass 4, count 0 2006.197.08:19:01.89#ibcon#read 6, iclass 4, count 0 2006.197.08:19:01.89#ibcon#end of sib2, iclass 4, count 0 2006.197.08:19:01.89#ibcon#*mode == 0, iclass 4, count 0 2006.197.08:19:01.89#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.197.08:19:01.89#ibcon#[28=FRQ=06,752.99\r\n] 2006.197.08:19:01.89#ibcon#*before write, iclass 4, count 0 2006.197.08:19:01.89#ibcon#enter sib2, iclass 4, count 0 2006.197.08:19:01.89#ibcon#flushed, iclass 4, count 0 2006.197.08:19:01.89#ibcon#about to write, iclass 4, count 0 2006.197.08:19:01.89#ibcon#wrote, iclass 4, count 0 2006.197.08:19:01.89#ibcon#about to read 3, iclass 4, count 0 2006.197.08:19:01.93#ibcon#read 3, iclass 4, count 0 2006.197.08:19:01.93#ibcon#about to read 4, iclass 4, count 0 2006.197.08:19:01.93#ibcon#read 4, iclass 4, count 0 2006.197.08:19:01.93#ibcon#about to read 5, iclass 4, count 0 2006.197.08:19:01.93#ibcon#read 5, iclass 4, count 0 2006.197.08:19:01.93#ibcon#about to read 6, iclass 4, count 0 2006.197.08:19:01.93#ibcon#read 6, iclass 4, count 0 2006.197.08:19:01.93#ibcon#end of sib2, iclass 4, count 0 2006.197.08:19:01.93#ibcon#*after write, iclass 4, count 0 2006.197.08:19:01.93#ibcon#*before return 0, iclass 4, count 0 2006.197.08:19:01.93#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.197.08:19:01.93#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.197.08:19:01.93#ibcon#about to clear, iclass 4 cls_cnt 0 2006.197.08:19:01.93#ibcon#cleared, iclass 4 cls_cnt 0 2006.197.08:19:01.93$vc4f8/vb=6,4 2006.197.08:19:01.93#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.197.08:19:01.93#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.197.08:19:01.93#ibcon#ireg 11 cls_cnt 2 2006.197.08:19:01.93#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.197.08:19:01.99#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.197.08:19:01.99#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.197.08:19:01.99#ibcon#enter wrdev, iclass 6, count 2 2006.197.08:19:01.99#ibcon#first serial, iclass 6, count 2 2006.197.08:19:01.99#ibcon#enter sib2, iclass 6, count 2 2006.197.08:19:01.99#ibcon#flushed, iclass 6, count 2 2006.197.08:19:01.99#ibcon#about to write, iclass 6, count 2 2006.197.08:19:01.99#ibcon#wrote, iclass 6, count 2 2006.197.08:19:01.99#ibcon#about to read 3, iclass 6, count 2 2006.197.08:19:02.01#ibcon#read 3, iclass 6, count 2 2006.197.08:19:02.01#ibcon#about to read 4, iclass 6, count 2 2006.197.08:19:02.01#ibcon#read 4, iclass 6, count 2 2006.197.08:19:02.01#ibcon#about to read 5, iclass 6, count 2 2006.197.08:19:02.01#ibcon#read 5, iclass 6, count 2 2006.197.08:19:02.01#ibcon#about to read 6, iclass 6, count 2 2006.197.08:19:02.01#ibcon#read 6, iclass 6, count 2 2006.197.08:19:02.01#ibcon#end of sib2, iclass 6, count 2 2006.197.08:19:02.01#ibcon#*mode == 0, iclass 6, count 2 2006.197.08:19:02.01#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.197.08:19:02.01#ibcon#[27=AT06-04\r\n] 2006.197.08:19:02.01#ibcon#*before write, iclass 6, count 2 2006.197.08:19:02.01#ibcon#enter sib2, iclass 6, count 2 2006.197.08:19:02.01#ibcon#flushed, iclass 6, count 2 2006.197.08:19:02.01#ibcon#about to write, iclass 6, count 2 2006.197.08:19:02.01#ibcon#wrote, iclass 6, count 2 2006.197.08:19:02.01#ibcon#about to read 3, iclass 6, count 2 2006.197.08:19:02.04#ibcon#read 3, iclass 6, count 2 2006.197.08:19:02.04#ibcon#about to read 4, iclass 6, count 2 2006.197.08:19:02.04#ibcon#read 4, iclass 6, count 2 2006.197.08:19:02.04#ibcon#about to read 5, iclass 6, count 2 2006.197.08:19:02.04#ibcon#read 5, iclass 6, count 2 2006.197.08:19:02.04#ibcon#about to read 6, iclass 6, count 2 2006.197.08:19:02.04#ibcon#read 6, iclass 6, count 2 2006.197.08:19:02.04#ibcon#end of sib2, iclass 6, count 2 2006.197.08:19:02.04#ibcon#*after write, iclass 6, count 2 2006.197.08:19:02.04#ibcon#*before return 0, iclass 6, count 2 2006.197.08:19:02.04#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.197.08:19:02.04#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.197.08:19:02.04#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.197.08:19:02.04#ibcon#ireg 7 cls_cnt 0 2006.197.08:19:02.04#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.197.08:19:02.16#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.197.08:19:02.16#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.197.08:19:02.16#ibcon#enter wrdev, iclass 6, count 0 2006.197.08:19:02.16#ibcon#first serial, iclass 6, count 0 2006.197.08:19:02.16#ibcon#enter sib2, iclass 6, count 0 2006.197.08:19:02.16#ibcon#flushed, iclass 6, count 0 2006.197.08:19:02.16#ibcon#about to write, iclass 6, count 0 2006.197.08:19:02.16#ibcon#wrote, iclass 6, count 0 2006.197.08:19:02.16#ibcon#about to read 3, iclass 6, count 0 2006.197.08:19:02.18#ibcon#read 3, iclass 6, count 0 2006.197.08:19:02.18#ibcon#about to read 4, iclass 6, count 0 2006.197.08:19:02.18#ibcon#read 4, iclass 6, count 0 2006.197.08:19:02.18#ibcon#about to read 5, iclass 6, count 0 2006.197.08:19:02.18#ibcon#read 5, iclass 6, count 0 2006.197.08:19:02.18#ibcon#about to read 6, iclass 6, count 0 2006.197.08:19:02.18#ibcon#read 6, iclass 6, count 0 2006.197.08:19:02.18#ibcon#end of sib2, iclass 6, count 0 2006.197.08:19:02.18#ibcon#*mode == 0, iclass 6, count 0 2006.197.08:19:02.18#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.197.08:19:02.18#ibcon#[27=USB\r\n] 2006.197.08:19:02.18#ibcon#*before write, iclass 6, count 0 2006.197.08:19:02.18#ibcon#enter sib2, iclass 6, count 0 2006.197.08:19:02.18#ibcon#flushed, iclass 6, count 0 2006.197.08:19:02.18#ibcon#about to write, iclass 6, count 0 2006.197.08:19:02.18#ibcon#wrote, iclass 6, count 0 2006.197.08:19:02.18#ibcon#about to read 3, iclass 6, count 0 2006.197.08:19:02.21#ibcon#read 3, iclass 6, count 0 2006.197.08:19:02.21#ibcon#about to read 4, iclass 6, count 0 2006.197.08:19:02.21#ibcon#read 4, iclass 6, count 0 2006.197.08:19:02.21#ibcon#about to read 5, iclass 6, count 0 2006.197.08:19:02.21#ibcon#read 5, iclass 6, count 0 2006.197.08:19:02.21#ibcon#about to read 6, iclass 6, count 0 2006.197.08:19:02.21#ibcon#read 6, iclass 6, count 0 2006.197.08:19:02.21#ibcon#end of sib2, iclass 6, count 0 2006.197.08:19:02.21#ibcon#*after write, iclass 6, count 0 2006.197.08:19:02.21#ibcon#*before return 0, iclass 6, count 0 2006.197.08:19:02.21#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.197.08:19:02.21#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.197.08:19:02.21#ibcon#about to clear, iclass 6 cls_cnt 0 2006.197.08:19:02.21#ibcon#cleared, iclass 6 cls_cnt 0 2006.197.08:19:02.21$vc4f8/vabw=wide 2006.197.08:19:02.21#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.197.08:19:02.21#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.197.08:19:02.21#ibcon#ireg 8 cls_cnt 0 2006.197.08:19:02.21#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.197.08:19:02.21#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.197.08:19:02.21#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.197.08:19:02.21#ibcon#enter wrdev, iclass 10, count 0 2006.197.08:19:02.21#ibcon#first serial, iclass 10, count 0 2006.197.08:19:02.21#ibcon#enter sib2, iclass 10, count 0 2006.197.08:19:02.21#ibcon#flushed, iclass 10, count 0 2006.197.08:19:02.21#ibcon#about to write, iclass 10, count 0 2006.197.08:19:02.21#ibcon#wrote, iclass 10, count 0 2006.197.08:19:02.21#ibcon#about to read 3, iclass 10, count 0 2006.197.08:19:02.23#ibcon#read 3, iclass 10, count 0 2006.197.08:19:02.23#ibcon#about to read 4, iclass 10, count 0 2006.197.08:19:02.23#ibcon#read 4, iclass 10, count 0 2006.197.08:19:02.23#ibcon#about to read 5, iclass 10, count 0 2006.197.08:19:02.23#ibcon#read 5, iclass 10, count 0 2006.197.08:19:02.23#ibcon#about to read 6, iclass 10, count 0 2006.197.08:19:02.23#ibcon#read 6, iclass 10, count 0 2006.197.08:19:02.23#ibcon#end of sib2, iclass 10, count 0 2006.197.08:19:02.23#ibcon#*mode == 0, iclass 10, count 0 2006.197.08:19:02.23#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.197.08:19:02.23#ibcon#[25=BW32\r\n] 2006.197.08:19:02.23#ibcon#*before write, iclass 10, count 0 2006.197.08:19:02.23#ibcon#enter sib2, iclass 10, count 0 2006.197.08:19:02.23#ibcon#flushed, iclass 10, count 0 2006.197.08:19:02.23#ibcon#about to write, iclass 10, count 0 2006.197.08:19:02.23#ibcon#wrote, iclass 10, count 0 2006.197.08:19:02.23#ibcon#about to read 3, iclass 10, count 0 2006.197.08:19:02.26#ibcon#read 3, iclass 10, count 0 2006.197.08:19:02.26#ibcon#about to read 4, iclass 10, count 0 2006.197.08:19:02.26#ibcon#read 4, iclass 10, count 0 2006.197.08:19:02.26#ibcon#about to read 5, iclass 10, count 0 2006.197.08:19:02.26#ibcon#read 5, iclass 10, count 0 2006.197.08:19:02.26#ibcon#about to read 6, iclass 10, count 0 2006.197.08:19:02.26#ibcon#read 6, iclass 10, count 0 2006.197.08:19:02.26#ibcon#end of sib2, iclass 10, count 0 2006.197.08:19:02.26#ibcon#*after write, iclass 10, count 0 2006.197.08:19:02.26#ibcon#*before return 0, iclass 10, count 0 2006.197.08:19:02.26#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.197.08:19:02.26#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.197.08:19:02.26#ibcon#about to clear, iclass 10 cls_cnt 0 2006.197.08:19:02.26#ibcon#cleared, iclass 10 cls_cnt 0 2006.197.08:19:02.26$vc4f8/vbbw=wide 2006.197.08:19:02.26#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.197.08:19:02.26#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.197.08:19:02.26#ibcon#ireg 8 cls_cnt 0 2006.197.08:19:02.26#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.197.08:19:02.33#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.197.08:19:02.33#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.197.08:19:02.33#ibcon#enter wrdev, iclass 12, count 0 2006.197.08:19:02.33#ibcon#first serial, iclass 12, count 0 2006.197.08:19:02.33#ibcon#enter sib2, iclass 12, count 0 2006.197.08:19:02.33#ibcon#flushed, iclass 12, count 0 2006.197.08:19:02.33#ibcon#about to write, iclass 12, count 0 2006.197.08:19:02.33#ibcon#wrote, iclass 12, count 0 2006.197.08:19:02.33#ibcon#about to read 3, iclass 12, count 0 2006.197.08:19:02.35#ibcon#read 3, iclass 12, count 0 2006.197.08:19:02.35#ibcon#about to read 4, iclass 12, count 0 2006.197.08:19:02.35#ibcon#read 4, iclass 12, count 0 2006.197.08:19:02.35#ibcon#about to read 5, iclass 12, count 0 2006.197.08:19:02.35#ibcon#read 5, iclass 12, count 0 2006.197.08:19:02.35#ibcon#about to read 6, iclass 12, count 0 2006.197.08:19:02.35#ibcon#read 6, iclass 12, count 0 2006.197.08:19:02.35#ibcon#end of sib2, iclass 12, count 0 2006.197.08:19:02.35#ibcon#*mode == 0, iclass 12, count 0 2006.197.08:19:02.35#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.197.08:19:02.35#ibcon#[27=BW32\r\n] 2006.197.08:19:02.35#ibcon#*before write, iclass 12, count 0 2006.197.08:19:02.35#ibcon#enter sib2, iclass 12, count 0 2006.197.08:19:02.35#ibcon#flushed, iclass 12, count 0 2006.197.08:19:02.35#ibcon#about to write, iclass 12, count 0 2006.197.08:19:02.35#ibcon#wrote, iclass 12, count 0 2006.197.08:19:02.35#ibcon#about to read 3, iclass 12, count 0 2006.197.08:19:02.38#ibcon#read 3, iclass 12, count 0 2006.197.08:19:02.38#ibcon#about to read 4, iclass 12, count 0 2006.197.08:19:02.38#ibcon#read 4, iclass 12, count 0 2006.197.08:19:02.38#ibcon#about to read 5, iclass 12, count 0 2006.197.08:19:02.38#ibcon#read 5, iclass 12, count 0 2006.197.08:19:02.38#ibcon#about to read 6, iclass 12, count 0 2006.197.08:19:02.38#ibcon#read 6, iclass 12, count 0 2006.197.08:19:02.38#ibcon#end of sib2, iclass 12, count 0 2006.197.08:19:02.38#ibcon#*after write, iclass 12, count 0 2006.197.08:19:02.38#ibcon#*before return 0, iclass 12, count 0 2006.197.08:19:02.38#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.197.08:19:02.38#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.197.08:19:02.38#ibcon#about to clear, iclass 12 cls_cnt 0 2006.197.08:19:02.38#ibcon#cleared, iclass 12 cls_cnt 0 2006.197.08:19:02.38$4f8m12a/ifd4f 2006.197.08:19:02.38$ifd4f/lo= 2006.197.08:19:02.38$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.197.08:19:02.38$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.197.08:19:02.38$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.197.08:19:02.38$ifd4f/patch= 2006.197.08:19:02.38$ifd4f/patch=lo1,a1,a2,a3,a4 2006.197.08:19:02.38$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.197.08:19:02.38$ifd4f/patch=lo3,a5,a6,a7,a8 2006.197.08:19:02.38$4f8m12a/"form=m,16.000,1:2 2006.197.08:19:02.38$4f8m12a/"tpicd 2006.197.08:19:02.38$4f8m12a/echo=off 2006.197.08:19:02.38$4f8m12a/xlog=off 2006.197.08:19:02.38:!2006.197.08:20:40 2006.197.08:19:11.14#trakl#Source acquired 2006.197.08:19:12.14#flagr#flagr/antenna,acquired 2006.197.08:20:40.00:preob 2006.197.08:20:40.13/onsource/TRACKING 2006.197.08:20:40.13:!2006.197.08:20:50 2006.197.08:20:50.00:data_valid=on 2006.197.08:20:50.00:midob 2006.197.08:20:51.13/onsource/TRACKING 2006.197.08:20:51.13/wx/25.54,1002.8,96 2006.197.08:20:51.26/cable/+6.3717E-03 2006.197.08:20:52.35/va/01,08,usb,yes,30,32 2006.197.08:20:52.35/va/02,07,usb,yes,30,31 2006.197.08:20:52.35/va/03,06,usb,yes,32,32 2006.197.08:20:52.35/va/04,07,usb,yes,31,33 2006.197.08:20:52.35/va/05,07,usb,yes,35,37 2006.197.08:20:52.35/va/06,06,usb,yes,34,34 2006.197.08:20:52.35/va/07,06,usb,yes,34,34 2006.197.08:20:52.35/va/08,07,usb,yes,33,32 2006.197.08:20:52.58/valo/01,532.99,yes,locked 2006.197.08:20:52.58/valo/02,572.99,yes,locked 2006.197.08:20:52.58/valo/03,672.99,yes,locked 2006.197.08:20:52.58/valo/04,832.99,yes,locked 2006.197.08:20:52.58/valo/05,652.99,yes,locked 2006.197.08:20:52.58/valo/06,772.99,yes,locked 2006.197.08:20:52.58/valo/07,832.99,yes,locked 2006.197.08:20:52.58/valo/08,852.99,yes,locked 2006.197.08:20:53.67/vb/01,04,usb,yes,29,28 2006.197.08:20:53.67/vb/02,04,usb,yes,31,32 2006.197.08:20:53.67/vb/03,04,usb,yes,28,31 2006.197.08:20:53.67/vb/04,04,usb,yes,28,28 2006.197.08:20:53.67/vb/05,04,usb,yes,27,31 2006.197.08:20:53.67/vb/06,04,usb,yes,28,30 2006.197.08:20:53.67/vb/07,04,usb,yes,30,30 2006.197.08:20:53.67/vb/08,04,usb,yes,27,31 2006.197.08:20:53.91/vblo/01,632.99,yes,locked 2006.197.08:20:53.91/vblo/02,640.99,yes,locked 2006.197.08:20:53.91/vblo/03,656.99,yes,locked 2006.197.08:20:53.91/vblo/04,712.99,yes,locked 2006.197.08:20:53.91/vblo/05,744.99,yes,locked 2006.197.08:20:53.91/vblo/06,752.99,yes,locked 2006.197.08:20:53.91/vblo/07,734.99,yes,locked 2006.197.08:20:53.91/vblo/08,744.99,yes,locked 2006.197.08:20:54.06/vabw/8 2006.197.08:20:54.21/vbbw/8 2006.197.08:20:54.30/xfe/off,on,15.5 2006.197.08:20:54.69/ifatt/23,28,28,28 2006.197.08:20:55.10/fmout-gps/S +3.00E-07 2006.197.08:20:55.13:!2006.197.08:21:50 2006.197.08:21:50.00:data_valid=off 2006.197.08:21:50.00:postob 2006.197.08:21:50.19/cable/+6.3707E-03 2006.197.08:21:50.19/wx/25.53,1002.8,96 2006.197.08:21:51.10/fmout-gps/S +3.00E-07 2006.197.08:21:51.10:scan_name=197-0824,k06197,60 2006.197.08:21:51.10:source=3c418,203837.03,511912.7,2000.0,cw 2006.197.08:21:51.13#flagr#flagr/antenna,new-source 2006.197.08:21:52.13:checkk5 2006.197.08:21:52.46/chk_autoobs//k5ts1/ autoobs is running! 2006.197.08:21:52.80/chk_autoobs//k5ts2/ autoobs is running! 2006.197.08:21:53.15/chk_autoobs//k5ts3/ autoobs is running! 2006.197.08:21:53.50/chk_autoobs//k5ts4/ autoobs is running! 2006.197.08:21:53.83/chk_obsdata//k5ts1/T1970820??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.08:21:54.16/chk_obsdata//k5ts2/T1970820??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.08:21:54.50/chk_obsdata//k5ts3/T1970820??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.08:21:54.84/chk_obsdata//k5ts4/T1970820??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.08:21:55.49/k5log//k5ts1_log_newline 2006.197.08:21:56.16/k5log//k5ts2_log_newline 2006.197.08:21:56.82/k5log//k5ts3_log_newline 2006.197.08:21:57.48/k5log//k5ts4_log_newline 2006.197.08:21:57.50/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.197.08:21:57.50:4f8m12a=3 2006.197.08:21:57.50$4f8m12a/echo=on 2006.197.08:21:57.50$4f8m12a/pcalon 2006.197.08:21:57.50$pcalon/"no phase cal control is implemented here 2006.197.08:21:57.50$4f8m12a/"tpicd=stop 2006.197.08:21:57.50$4f8m12a/vc4f8 2006.197.08:21:57.50$vc4f8/valo=1,532.99 2006.197.08:21:57.51#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.197.08:21:57.51#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.197.08:21:57.51#ibcon#ireg 17 cls_cnt 0 2006.197.08:21:57.51#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.197.08:21:57.51#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.197.08:21:57.51#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.197.08:21:57.51#ibcon#enter wrdev, iclass 11, count 0 2006.197.08:21:57.51#ibcon#first serial, iclass 11, count 0 2006.197.08:21:57.51#ibcon#enter sib2, iclass 11, count 0 2006.197.08:21:57.51#ibcon#flushed, iclass 11, count 0 2006.197.08:21:57.51#ibcon#about to write, iclass 11, count 0 2006.197.08:21:57.51#ibcon#wrote, iclass 11, count 0 2006.197.08:21:57.51#ibcon#about to read 3, iclass 11, count 0 2006.197.08:21:57.53#ibcon#read 3, iclass 11, count 0 2006.197.08:21:57.53#ibcon#about to read 4, iclass 11, count 0 2006.197.08:21:57.53#ibcon#read 4, iclass 11, count 0 2006.197.08:21:57.53#ibcon#about to read 5, iclass 11, count 0 2006.197.08:21:57.53#ibcon#read 5, iclass 11, count 0 2006.197.08:21:57.53#ibcon#about to read 6, iclass 11, count 0 2006.197.08:21:57.53#ibcon#read 6, iclass 11, count 0 2006.197.08:21:57.53#ibcon#end of sib2, iclass 11, count 0 2006.197.08:21:57.53#ibcon#*mode == 0, iclass 11, count 0 2006.197.08:21:57.53#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.197.08:21:57.53#ibcon#[26=FRQ=01,532.99\r\n] 2006.197.08:21:57.53#ibcon#*before write, iclass 11, count 0 2006.197.08:21:57.53#ibcon#enter sib2, iclass 11, count 0 2006.197.08:21:57.53#ibcon#flushed, iclass 11, count 0 2006.197.08:21:57.53#ibcon#about to write, iclass 11, count 0 2006.197.08:21:57.53#ibcon#wrote, iclass 11, count 0 2006.197.08:21:57.53#ibcon#about to read 3, iclass 11, count 0 2006.197.08:21:57.58#ibcon#read 3, iclass 11, count 0 2006.197.08:21:57.58#ibcon#about to read 4, iclass 11, count 0 2006.197.08:21:57.58#ibcon#read 4, iclass 11, count 0 2006.197.08:21:57.58#ibcon#about to read 5, iclass 11, count 0 2006.197.08:21:57.58#ibcon#read 5, iclass 11, count 0 2006.197.08:21:57.58#ibcon#about to read 6, iclass 11, count 0 2006.197.08:21:57.58#ibcon#read 6, iclass 11, count 0 2006.197.08:21:57.58#ibcon#end of sib2, iclass 11, count 0 2006.197.08:21:57.58#ibcon#*after write, iclass 11, count 0 2006.197.08:21:57.58#ibcon#*before return 0, iclass 11, count 0 2006.197.08:21:57.58#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.197.08:21:57.58#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.197.08:21:57.58#ibcon#about to clear, iclass 11 cls_cnt 0 2006.197.08:21:57.58#ibcon#cleared, iclass 11 cls_cnt 0 2006.197.08:21:57.58$vc4f8/va=1,8 2006.197.08:21:57.58#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.197.08:21:57.58#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.197.08:21:57.58#ibcon#ireg 11 cls_cnt 2 2006.197.08:21:57.58#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.197.08:21:57.58#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.197.08:21:57.58#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.197.08:21:57.58#ibcon#enter wrdev, iclass 13, count 2 2006.197.08:21:57.58#ibcon#first serial, iclass 13, count 2 2006.197.08:21:57.58#ibcon#enter sib2, iclass 13, count 2 2006.197.08:21:57.58#ibcon#flushed, iclass 13, count 2 2006.197.08:21:57.58#ibcon#about to write, iclass 13, count 2 2006.197.08:21:57.58#ibcon#wrote, iclass 13, count 2 2006.197.08:21:57.58#ibcon#about to read 3, iclass 13, count 2 2006.197.08:21:57.60#ibcon#read 3, iclass 13, count 2 2006.197.08:21:57.60#ibcon#about to read 4, iclass 13, count 2 2006.197.08:21:57.60#ibcon#read 4, iclass 13, count 2 2006.197.08:21:57.60#ibcon#about to read 5, iclass 13, count 2 2006.197.08:21:57.60#ibcon#read 5, iclass 13, count 2 2006.197.08:21:57.60#ibcon#about to read 6, iclass 13, count 2 2006.197.08:21:57.60#ibcon#read 6, iclass 13, count 2 2006.197.08:21:57.60#ibcon#end of sib2, iclass 13, count 2 2006.197.08:21:57.60#ibcon#*mode == 0, iclass 13, count 2 2006.197.08:21:57.60#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.197.08:21:57.60#ibcon#[25=AT01-08\r\n] 2006.197.08:21:57.60#ibcon#*before write, iclass 13, count 2 2006.197.08:21:57.60#ibcon#enter sib2, iclass 13, count 2 2006.197.08:21:57.60#ibcon#flushed, iclass 13, count 2 2006.197.08:21:57.60#ibcon#about to write, iclass 13, count 2 2006.197.08:21:57.60#ibcon#wrote, iclass 13, count 2 2006.197.08:21:57.60#ibcon#about to read 3, iclass 13, count 2 2006.197.08:21:57.63#ibcon#read 3, iclass 13, count 2 2006.197.08:21:57.63#ibcon#about to read 4, iclass 13, count 2 2006.197.08:21:57.63#ibcon#read 4, iclass 13, count 2 2006.197.08:21:57.63#ibcon#about to read 5, iclass 13, count 2 2006.197.08:21:57.63#ibcon#read 5, iclass 13, count 2 2006.197.08:21:57.63#ibcon#about to read 6, iclass 13, count 2 2006.197.08:21:57.63#ibcon#read 6, iclass 13, count 2 2006.197.08:21:57.63#ibcon#end of sib2, iclass 13, count 2 2006.197.08:21:57.63#ibcon#*after write, iclass 13, count 2 2006.197.08:21:57.63#ibcon#*before return 0, iclass 13, count 2 2006.197.08:21:57.63#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.197.08:21:57.63#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.197.08:21:57.63#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.197.08:21:57.63#ibcon#ireg 7 cls_cnt 0 2006.197.08:21:57.63#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.197.08:21:57.75#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.197.08:21:57.75#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.197.08:21:57.75#ibcon#enter wrdev, iclass 13, count 0 2006.197.08:21:57.75#ibcon#first serial, iclass 13, count 0 2006.197.08:21:57.75#ibcon#enter sib2, iclass 13, count 0 2006.197.08:21:57.75#ibcon#flushed, iclass 13, count 0 2006.197.08:21:57.75#ibcon#about to write, iclass 13, count 0 2006.197.08:21:57.75#ibcon#wrote, iclass 13, count 0 2006.197.08:21:57.75#ibcon#about to read 3, iclass 13, count 0 2006.197.08:21:57.77#ibcon#read 3, iclass 13, count 0 2006.197.08:21:57.77#ibcon#about to read 4, iclass 13, count 0 2006.197.08:21:57.77#ibcon#read 4, iclass 13, count 0 2006.197.08:21:57.77#ibcon#about to read 5, iclass 13, count 0 2006.197.08:21:57.77#ibcon#read 5, iclass 13, count 0 2006.197.08:21:57.77#ibcon#about to read 6, iclass 13, count 0 2006.197.08:21:57.77#ibcon#read 6, iclass 13, count 0 2006.197.08:21:57.77#ibcon#end of sib2, iclass 13, count 0 2006.197.08:21:57.77#ibcon#*mode == 0, iclass 13, count 0 2006.197.08:21:57.77#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.197.08:21:57.77#ibcon#[25=USB\r\n] 2006.197.08:21:57.77#ibcon#*before write, iclass 13, count 0 2006.197.08:21:57.77#ibcon#enter sib2, iclass 13, count 0 2006.197.08:21:57.77#ibcon#flushed, iclass 13, count 0 2006.197.08:21:57.77#ibcon#about to write, iclass 13, count 0 2006.197.08:21:57.77#ibcon#wrote, iclass 13, count 0 2006.197.08:21:57.77#ibcon#about to read 3, iclass 13, count 0 2006.197.08:21:57.80#ibcon#read 3, iclass 13, count 0 2006.197.08:21:57.80#ibcon#about to read 4, iclass 13, count 0 2006.197.08:21:57.80#ibcon#read 4, iclass 13, count 0 2006.197.08:21:57.80#ibcon#about to read 5, iclass 13, count 0 2006.197.08:21:57.80#ibcon#read 5, iclass 13, count 0 2006.197.08:21:57.80#ibcon#about to read 6, iclass 13, count 0 2006.197.08:21:57.80#ibcon#read 6, iclass 13, count 0 2006.197.08:21:57.80#ibcon#end of sib2, iclass 13, count 0 2006.197.08:21:57.80#ibcon#*after write, iclass 13, count 0 2006.197.08:21:57.80#ibcon#*before return 0, iclass 13, count 0 2006.197.08:21:57.80#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.197.08:21:57.80#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.197.08:21:57.80#ibcon#about to clear, iclass 13 cls_cnt 0 2006.197.08:21:57.80#ibcon#cleared, iclass 13 cls_cnt 0 2006.197.08:21:57.80$vc4f8/valo=2,572.99 2006.197.08:21:57.80#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.197.08:21:57.80#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.197.08:21:57.80#ibcon#ireg 17 cls_cnt 0 2006.197.08:21:57.80#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.197.08:21:57.80#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.197.08:21:57.80#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.197.08:21:57.80#ibcon#enter wrdev, iclass 15, count 0 2006.197.08:21:57.80#ibcon#first serial, iclass 15, count 0 2006.197.08:21:57.80#ibcon#enter sib2, iclass 15, count 0 2006.197.08:21:57.80#ibcon#flushed, iclass 15, count 0 2006.197.08:21:57.80#ibcon#about to write, iclass 15, count 0 2006.197.08:21:57.80#ibcon#wrote, iclass 15, count 0 2006.197.08:21:57.80#ibcon#about to read 3, iclass 15, count 0 2006.197.08:21:57.82#ibcon#read 3, iclass 15, count 0 2006.197.08:21:57.82#ibcon#about to read 4, iclass 15, count 0 2006.197.08:21:57.82#ibcon#read 4, iclass 15, count 0 2006.197.08:21:57.82#ibcon#about to read 5, iclass 15, count 0 2006.197.08:21:57.82#ibcon#read 5, iclass 15, count 0 2006.197.08:21:57.82#ibcon#about to read 6, iclass 15, count 0 2006.197.08:21:57.82#ibcon#read 6, iclass 15, count 0 2006.197.08:21:57.82#ibcon#end of sib2, iclass 15, count 0 2006.197.08:21:57.82#ibcon#*mode == 0, iclass 15, count 0 2006.197.08:21:57.82#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.197.08:21:57.82#ibcon#[26=FRQ=02,572.99\r\n] 2006.197.08:21:57.82#ibcon#*before write, iclass 15, count 0 2006.197.08:21:57.82#ibcon#enter sib2, iclass 15, count 0 2006.197.08:21:57.82#ibcon#flushed, iclass 15, count 0 2006.197.08:21:57.82#ibcon#about to write, iclass 15, count 0 2006.197.08:21:57.82#ibcon#wrote, iclass 15, count 0 2006.197.08:21:57.82#ibcon#about to read 3, iclass 15, count 0 2006.197.08:21:57.86#ibcon#read 3, iclass 15, count 0 2006.197.08:21:57.86#ibcon#about to read 4, iclass 15, count 0 2006.197.08:21:57.86#ibcon#read 4, iclass 15, count 0 2006.197.08:21:57.86#ibcon#about to read 5, iclass 15, count 0 2006.197.08:21:57.86#ibcon#read 5, iclass 15, count 0 2006.197.08:21:57.86#ibcon#about to read 6, iclass 15, count 0 2006.197.08:21:57.86#ibcon#read 6, iclass 15, count 0 2006.197.08:21:57.86#ibcon#end of sib2, iclass 15, count 0 2006.197.08:21:57.86#ibcon#*after write, iclass 15, count 0 2006.197.08:21:57.86#ibcon#*before return 0, iclass 15, count 0 2006.197.08:21:57.86#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.197.08:21:57.86#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.197.08:21:57.86#ibcon#about to clear, iclass 15 cls_cnt 0 2006.197.08:21:57.86#ibcon#cleared, iclass 15 cls_cnt 0 2006.197.08:21:57.86$vc4f8/va=2,7 2006.197.08:21:57.86#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.197.08:21:57.86#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.197.08:21:57.86#ibcon#ireg 11 cls_cnt 2 2006.197.08:21:57.86#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.197.08:21:57.92#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.197.08:21:57.92#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.197.08:21:57.92#ibcon#enter wrdev, iclass 17, count 2 2006.197.08:21:57.92#ibcon#first serial, iclass 17, count 2 2006.197.08:21:57.92#ibcon#enter sib2, iclass 17, count 2 2006.197.08:21:57.92#ibcon#flushed, iclass 17, count 2 2006.197.08:21:57.92#ibcon#about to write, iclass 17, count 2 2006.197.08:21:57.92#ibcon#wrote, iclass 17, count 2 2006.197.08:21:57.92#ibcon#about to read 3, iclass 17, count 2 2006.197.08:21:57.94#ibcon#read 3, iclass 17, count 2 2006.197.08:21:57.94#ibcon#about to read 4, iclass 17, count 2 2006.197.08:21:57.94#ibcon#read 4, iclass 17, count 2 2006.197.08:21:57.94#ibcon#about to read 5, iclass 17, count 2 2006.197.08:21:57.94#ibcon#read 5, iclass 17, count 2 2006.197.08:21:57.94#ibcon#about to read 6, iclass 17, count 2 2006.197.08:21:57.94#ibcon#read 6, iclass 17, count 2 2006.197.08:21:57.94#ibcon#end of sib2, iclass 17, count 2 2006.197.08:21:57.94#ibcon#*mode == 0, iclass 17, count 2 2006.197.08:21:57.94#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.197.08:21:57.94#ibcon#[25=AT02-07\r\n] 2006.197.08:21:57.94#ibcon#*before write, iclass 17, count 2 2006.197.08:21:57.94#ibcon#enter sib2, iclass 17, count 2 2006.197.08:21:57.94#ibcon#flushed, iclass 17, count 2 2006.197.08:21:57.94#ibcon#about to write, iclass 17, count 2 2006.197.08:21:57.94#ibcon#wrote, iclass 17, count 2 2006.197.08:21:57.94#ibcon#about to read 3, iclass 17, count 2 2006.197.08:21:57.97#ibcon#read 3, iclass 17, count 2 2006.197.08:21:57.97#ibcon#about to read 4, iclass 17, count 2 2006.197.08:21:57.97#ibcon#read 4, iclass 17, count 2 2006.197.08:21:57.97#ibcon#about to read 5, iclass 17, count 2 2006.197.08:21:57.97#ibcon#read 5, iclass 17, count 2 2006.197.08:21:57.97#ibcon#about to read 6, iclass 17, count 2 2006.197.08:21:57.97#ibcon#read 6, iclass 17, count 2 2006.197.08:21:57.97#ibcon#end of sib2, iclass 17, count 2 2006.197.08:21:57.97#ibcon#*after write, iclass 17, count 2 2006.197.08:21:57.97#ibcon#*before return 0, iclass 17, count 2 2006.197.08:21:57.97#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.197.08:21:57.97#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.197.08:21:57.97#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.197.08:21:57.97#ibcon#ireg 7 cls_cnt 0 2006.197.08:21:57.97#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.197.08:21:58.09#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.197.08:21:58.09#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.197.08:21:58.09#ibcon#enter wrdev, iclass 17, count 0 2006.197.08:21:58.09#ibcon#first serial, iclass 17, count 0 2006.197.08:21:58.09#ibcon#enter sib2, iclass 17, count 0 2006.197.08:21:58.09#ibcon#flushed, iclass 17, count 0 2006.197.08:21:58.09#ibcon#about to write, iclass 17, count 0 2006.197.08:21:58.09#ibcon#wrote, iclass 17, count 0 2006.197.08:21:58.09#ibcon#about to read 3, iclass 17, count 0 2006.197.08:21:58.11#ibcon#read 3, iclass 17, count 0 2006.197.08:21:58.11#ibcon#about to read 4, iclass 17, count 0 2006.197.08:21:58.11#ibcon#read 4, iclass 17, count 0 2006.197.08:21:58.11#ibcon#about to read 5, iclass 17, count 0 2006.197.08:21:58.11#ibcon#read 5, iclass 17, count 0 2006.197.08:21:58.11#ibcon#about to read 6, iclass 17, count 0 2006.197.08:21:58.11#ibcon#read 6, iclass 17, count 0 2006.197.08:21:58.11#ibcon#end of sib2, iclass 17, count 0 2006.197.08:21:58.11#ibcon#*mode == 0, iclass 17, count 0 2006.197.08:21:58.11#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.197.08:21:58.11#ibcon#[25=USB\r\n] 2006.197.08:21:58.11#ibcon#*before write, iclass 17, count 0 2006.197.08:21:58.11#ibcon#enter sib2, iclass 17, count 0 2006.197.08:21:58.11#ibcon#flushed, iclass 17, count 0 2006.197.08:21:58.11#ibcon#about to write, iclass 17, count 0 2006.197.08:21:58.11#ibcon#wrote, iclass 17, count 0 2006.197.08:21:58.11#ibcon#about to read 3, iclass 17, count 0 2006.197.08:21:58.14#ibcon#read 3, iclass 17, count 0 2006.197.08:21:58.14#ibcon#about to read 4, iclass 17, count 0 2006.197.08:21:58.14#ibcon#read 4, iclass 17, count 0 2006.197.08:21:58.14#ibcon#about to read 5, iclass 17, count 0 2006.197.08:21:58.14#ibcon#read 5, iclass 17, count 0 2006.197.08:21:58.14#ibcon#about to read 6, iclass 17, count 0 2006.197.08:21:58.14#ibcon#read 6, iclass 17, count 0 2006.197.08:21:58.14#ibcon#end of sib2, iclass 17, count 0 2006.197.08:21:58.14#ibcon#*after write, iclass 17, count 0 2006.197.08:21:58.14#ibcon#*before return 0, iclass 17, count 0 2006.197.08:21:58.14#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.197.08:21:58.14#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.197.08:21:58.14#ibcon#about to clear, iclass 17 cls_cnt 0 2006.197.08:21:58.14#ibcon#cleared, iclass 17 cls_cnt 0 2006.197.08:21:58.14$vc4f8/valo=3,672.99 2006.197.08:21:58.14#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.197.08:21:58.14#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.197.08:21:58.14#ibcon#ireg 17 cls_cnt 0 2006.197.08:21:58.14#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.197.08:21:58.14#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.197.08:21:58.14#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.197.08:21:58.14#ibcon#enter wrdev, iclass 19, count 0 2006.197.08:21:58.14#ibcon#first serial, iclass 19, count 0 2006.197.08:21:58.14#ibcon#enter sib2, iclass 19, count 0 2006.197.08:21:58.14#ibcon#flushed, iclass 19, count 0 2006.197.08:21:58.14#ibcon#about to write, iclass 19, count 0 2006.197.08:21:58.14#ibcon#wrote, iclass 19, count 0 2006.197.08:21:58.14#ibcon#about to read 3, iclass 19, count 0 2006.197.08:21:58.16#ibcon#read 3, iclass 19, count 0 2006.197.08:21:58.16#ibcon#about to read 4, iclass 19, count 0 2006.197.08:21:58.16#ibcon#read 4, iclass 19, count 0 2006.197.08:21:58.16#ibcon#about to read 5, iclass 19, count 0 2006.197.08:21:58.16#ibcon#read 5, iclass 19, count 0 2006.197.08:21:58.16#ibcon#about to read 6, iclass 19, count 0 2006.197.08:21:58.16#ibcon#read 6, iclass 19, count 0 2006.197.08:21:58.16#ibcon#end of sib2, iclass 19, count 0 2006.197.08:21:58.16#ibcon#*mode == 0, iclass 19, count 0 2006.197.08:21:58.16#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.197.08:21:58.16#ibcon#[26=FRQ=03,672.99\r\n] 2006.197.08:21:58.16#ibcon#*before write, iclass 19, count 0 2006.197.08:21:58.16#ibcon#enter sib2, iclass 19, count 0 2006.197.08:21:58.16#ibcon#flushed, iclass 19, count 0 2006.197.08:21:58.16#ibcon#about to write, iclass 19, count 0 2006.197.08:21:58.16#ibcon#wrote, iclass 19, count 0 2006.197.08:21:58.16#ibcon#about to read 3, iclass 19, count 0 2006.197.08:21:58.20#ibcon#read 3, iclass 19, count 0 2006.197.08:21:58.20#ibcon#about to read 4, iclass 19, count 0 2006.197.08:21:58.20#ibcon#read 4, iclass 19, count 0 2006.197.08:21:58.20#ibcon#about to read 5, iclass 19, count 0 2006.197.08:21:58.20#ibcon#read 5, iclass 19, count 0 2006.197.08:21:58.20#ibcon#about to read 6, iclass 19, count 0 2006.197.08:21:58.20#ibcon#read 6, iclass 19, count 0 2006.197.08:21:58.20#ibcon#end of sib2, iclass 19, count 0 2006.197.08:21:58.20#ibcon#*after write, iclass 19, count 0 2006.197.08:21:58.20#ibcon#*before return 0, iclass 19, count 0 2006.197.08:21:58.20#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.197.08:21:58.20#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.197.08:21:58.20#ibcon#about to clear, iclass 19 cls_cnt 0 2006.197.08:21:58.20#ibcon#cleared, iclass 19 cls_cnt 0 2006.197.08:21:58.20$vc4f8/va=3,6 2006.197.08:21:58.20#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.197.08:21:58.20#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.197.08:21:58.20#ibcon#ireg 11 cls_cnt 2 2006.197.08:21:58.20#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.197.08:21:58.26#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.197.08:21:58.26#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.197.08:21:58.26#ibcon#enter wrdev, iclass 21, count 2 2006.197.08:21:58.26#ibcon#first serial, iclass 21, count 2 2006.197.08:21:58.26#ibcon#enter sib2, iclass 21, count 2 2006.197.08:21:58.26#ibcon#flushed, iclass 21, count 2 2006.197.08:21:58.26#ibcon#about to write, iclass 21, count 2 2006.197.08:21:58.26#ibcon#wrote, iclass 21, count 2 2006.197.08:21:58.26#ibcon#about to read 3, iclass 21, count 2 2006.197.08:21:58.28#ibcon#read 3, iclass 21, count 2 2006.197.08:21:58.28#ibcon#about to read 4, iclass 21, count 2 2006.197.08:21:58.28#ibcon#read 4, iclass 21, count 2 2006.197.08:21:58.28#ibcon#about to read 5, iclass 21, count 2 2006.197.08:21:58.28#ibcon#read 5, iclass 21, count 2 2006.197.08:21:58.28#ibcon#about to read 6, iclass 21, count 2 2006.197.08:21:58.28#ibcon#read 6, iclass 21, count 2 2006.197.08:21:58.28#ibcon#end of sib2, iclass 21, count 2 2006.197.08:21:58.28#ibcon#*mode == 0, iclass 21, count 2 2006.197.08:21:58.28#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.197.08:21:58.28#ibcon#[25=AT03-06\r\n] 2006.197.08:21:58.28#ibcon#*before write, iclass 21, count 2 2006.197.08:21:58.28#ibcon#enter sib2, iclass 21, count 2 2006.197.08:21:58.28#ibcon#flushed, iclass 21, count 2 2006.197.08:21:58.28#ibcon#about to write, iclass 21, count 2 2006.197.08:21:58.28#ibcon#wrote, iclass 21, count 2 2006.197.08:21:58.28#ibcon#about to read 3, iclass 21, count 2 2006.197.08:21:58.31#ibcon#read 3, iclass 21, count 2 2006.197.08:21:58.31#ibcon#about to read 4, iclass 21, count 2 2006.197.08:21:58.31#ibcon#read 4, iclass 21, count 2 2006.197.08:21:58.31#ibcon#about to read 5, iclass 21, count 2 2006.197.08:21:58.31#ibcon#read 5, iclass 21, count 2 2006.197.08:21:58.31#ibcon#about to read 6, iclass 21, count 2 2006.197.08:21:58.31#ibcon#read 6, iclass 21, count 2 2006.197.08:21:58.31#ibcon#end of sib2, iclass 21, count 2 2006.197.08:21:58.31#ibcon#*after write, iclass 21, count 2 2006.197.08:21:58.31#ibcon#*before return 0, iclass 21, count 2 2006.197.08:21:58.31#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.197.08:21:58.31#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.197.08:21:58.31#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.197.08:21:58.31#ibcon#ireg 7 cls_cnt 0 2006.197.08:21:58.31#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.197.08:21:58.43#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.197.08:21:58.43#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.197.08:21:58.43#ibcon#enter wrdev, iclass 21, count 0 2006.197.08:21:58.43#ibcon#first serial, iclass 21, count 0 2006.197.08:21:58.43#ibcon#enter sib2, iclass 21, count 0 2006.197.08:21:58.43#ibcon#flushed, iclass 21, count 0 2006.197.08:21:58.43#ibcon#about to write, iclass 21, count 0 2006.197.08:21:58.43#ibcon#wrote, iclass 21, count 0 2006.197.08:21:58.43#ibcon#about to read 3, iclass 21, count 0 2006.197.08:21:58.45#ibcon#read 3, iclass 21, count 0 2006.197.08:21:58.45#ibcon#about to read 4, iclass 21, count 0 2006.197.08:21:58.45#ibcon#read 4, iclass 21, count 0 2006.197.08:21:58.45#ibcon#about to read 5, iclass 21, count 0 2006.197.08:21:58.45#ibcon#read 5, iclass 21, count 0 2006.197.08:21:58.45#ibcon#about to read 6, iclass 21, count 0 2006.197.08:21:58.45#ibcon#read 6, iclass 21, count 0 2006.197.08:21:58.45#ibcon#end of sib2, iclass 21, count 0 2006.197.08:21:58.45#ibcon#*mode == 0, iclass 21, count 0 2006.197.08:21:58.45#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.197.08:21:58.45#ibcon#[25=USB\r\n] 2006.197.08:21:58.45#ibcon#*before write, iclass 21, count 0 2006.197.08:21:58.45#ibcon#enter sib2, iclass 21, count 0 2006.197.08:21:58.45#ibcon#flushed, iclass 21, count 0 2006.197.08:21:58.45#ibcon#about to write, iclass 21, count 0 2006.197.08:21:58.45#ibcon#wrote, iclass 21, count 0 2006.197.08:21:58.45#ibcon#about to read 3, iclass 21, count 0 2006.197.08:21:58.48#ibcon#read 3, iclass 21, count 0 2006.197.08:21:58.48#ibcon#about to read 4, iclass 21, count 0 2006.197.08:21:58.48#ibcon#read 4, iclass 21, count 0 2006.197.08:21:58.48#ibcon#about to read 5, iclass 21, count 0 2006.197.08:21:58.48#ibcon#read 5, iclass 21, count 0 2006.197.08:21:58.48#ibcon#about to read 6, iclass 21, count 0 2006.197.08:21:58.48#ibcon#read 6, iclass 21, count 0 2006.197.08:21:58.48#ibcon#end of sib2, iclass 21, count 0 2006.197.08:21:58.48#ibcon#*after write, iclass 21, count 0 2006.197.08:21:58.48#ibcon#*before return 0, iclass 21, count 0 2006.197.08:21:58.48#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.197.08:21:58.48#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.197.08:21:58.48#ibcon#about to clear, iclass 21 cls_cnt 0 2006.197.08:21:58.48#ibcon#cleared, iclass 21 cls_cnt 0 2006.197.08:21:58.48$vc4f8/valo=4,832.99 2006.197.08:21:58.48#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.197.08:21:58.48#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.197.08:21:58.48#ibcon#ireg 17 cls_cnt 0 2006.197.08:21:58.48#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.197.08:21:58.48#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.197.08:21:58.48#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.197.08:21:58.48#ibcon#enter wrdev, iclass 23, count 0 2006.197.08:21:58.48#ibcon#first serial, iclass 23, count 0 2006.197.08:21:58.48#ibcon#enter sib2, iclass 23, count 0 2006.197.08:21:58.48#ibcon#flushed, iclass 23, count 0 2006.197.08:21:58.48#ibcon#about to write, iclass 23, count 0 2006.197.08:21:58.48#ibcon#wrote, iclass 23, count 0 2006.197.08:21:58.48#ibcon#about to read 3, iclass 23, count 0 2006.197.08:21:58.50#ibcon#read 3, iclass 23, count 0 2006.197.08:21:58.50#ibcon#about to read 4, iclass 23, count 0 2006.197.08:21:58.50#ibcon#read 4, iclass 23, count 0 2006.197.08:21:58.50#ibcon#about to read 5, iclass 23, count 0 2006.197.08:21:58.50#ibcon#read 5, iclass 23, count 0 2006.197.08:21:58.50#ibcon#about to read 6, iclass 23, count 0 2006.197.08:21:58.50#ibcon#read 6, iclass 23, count 0 2006.197.08:21:58.50#ibcon#end of sib2, iclass 23, count 0 2006.197.08:21:58.50#ibcon#*mode == 0, iclass 23, count 0 2006.197.08:21:58.50#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.197.08:21:58.50#ibcon#[26=FRQ=04,832.99\r\n] 2006.197.08:21:58.50#ibcon#*before write, iclass 23, count 0 2006.197.08:21:58.50#ibcon#enter sib2, iclass 23, count 0 2006.197.08:21:58.50#ibcon#flushed, iclass 23, count 0 2006.197.08:21:58.50#ibcon#about to write, iclass 23, count 0 2006.197.08:21:58.50#ibcon#wrote, iclass 23, count 0 2006.197.08:21:58.50#ibcon#about to read 3, iclass 23, count 0 2006.197.08:21:58.54#ibcon#read 3, iclass 23, count 0 2006.197.08:21:58.54#ibcon#about to read 4, iclass 23, count 0 2006.197.08:21:58.54#ibcon#read 4, iclass 23, count 0 2006.197.08:21:58.54#ibcon#about to read 5, iclass 23, count 0 2006.197.08:21:58.54#ibcon#read 5, iclass 23, count 0 2006.197.08:21:58.54#ibcon#about to read 6, iclass 23, count 0 2006.197.08:21:58.54#ibcon#read 6, iclass 23, count 0 2006.197.08:21:58.54#ibcon#end of sib2, iclass 23, count 0 2006.197.08:21:58.54#ibcon#*after write, iclass 23, count 0 2006.197.08:21:58.54#ibcon#*before return 0, iclass 23, count 0 2006.197.08:21:58.54#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.197.08:21:58.54#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.197.08:21:58.54#ibcon#about to clear, iclass 23 cls_cnt 0 2006.197.08:21:58.54#ibcon#cleared, iclass 23 cls_cnt 0 2006.197.08:21:58.54$vc4f8/va=4,7 2006.197.08:21:58.54#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.197.08:21:58.54#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.197.08:21:58.54#ibcon#ireg 11 cls_cnt 2 2006.197.08:21:58.54#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.197.08:21:58.60#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.197.08:21:58.60#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.197.08:21:58.60#ibcon#enter wrdev, iclass 25, count 2 2006.197.08:21:58.60#ibcon#first serial, iclass 25, count 2 2006.197.08:21:58.60#ibcon#enter sib2, iclass 25, count 2 2006.197.08:21:58.60#ibcon#flushed, iclass 25, count 2 2006.197.08:21:58.60#ibcon#about to write, iclass 25, count 2 2006.197.08:21:58.60#ibcon#wrote, iclass 25, count 2 2006.197.08:21:58.60#ibcon#about to read 3, iclass 25, count 2 2006.197.08:21:58.62#ibcon#read 3, iclass 25, count 2 2006.197.08:21:58.62#ibcon#about to read 4, iclass 25, count 2 2006.197.08:21:58.62#ibcon#read 4, iclass 25, count 2 2006.197.08:21:58.62#ibcon#about to read 5, iclass 25, count 2 2006.197.08:21:58.62#ibcon#read 5, iclass 25, count 2 2006.197.08:21:58.62#ibcon#about to read 6, iclass 25, count 2 2006.197.08:21:58.62#ibcon#read 6, iclass 25, count 2 2006.197.08:21:58.62#ibcon#end of sib2, iclass 25, count 2 2006.197.08:21:58.62#ibcon#*mode == 0, iclass 25, count 2 2006.197.08:21:58.62#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.197.08:21:58.62#ibcon#[25=AT04-07\r\n] 2006.197.08:21:58.62#ibcon#*before write, iclass 25, count 2 2006.197.08:21:58.62#ibcon#enter sib2, iclass 25, count 2 2006.197.08:21:58.62#ibcon#flushed, iclass 25, count 2 2006.197.08:21:58.62#ibcon#about to write, iclass 25, count 2 2006.197.08:21:58.62#ibcon#wrote, iclass 25, count 2 2006.197.08:21:58.62#ibcon#about to read 3, iclass 25, count 2 2006.197.08:21:58.65#ibcon#read 3, iclass 25, count 2 2006.197.08:21:58.65#ibcon#about to read 4, iclass 25, count 2 2006.197.08:21:58.65#ibcon#read 4, iclass 25, count 2 2006.197.08:21:58.65#ibcon#about to read 5, iclass 25, count 2 2006.197.08:21:58.65#ibcon#read 5, iclass 25, count 2 2006.197.08:21:58.65#ibcon#about to read 6, iclass 25, count 2 2006.197.08:21:58.65#ibcon#read 6, iclass 25, count 2 2006.197.08:21:58.65#ibcon#end of sib2, iclass 25, count 2 2006.197.08:21:58.65#ibcon#*after write, iclass 25, count 2 2006.197.08:21:58.65#ibcon#*before return 0, iclass 25, count 2 2006.197.08:21:58.65#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.197.08:21:58.65#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.197.08:21:58.65#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.197.08:21:58.65#ibcon#ireg 7 cls_cnt 0 2006.197.08:21:58.65#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.197.08:21:58.77#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.197.08:21:58.77#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.197.08:21:58.77#ibcon#enter wrdev, iclass 25, count 0 2006.197.08:21:58.77#ibcon#first serial, iclass 25, count 0 2006.197.08:21:58.77#ibcon#enter sib2, iclass 25, count 0 2006.197.08:21:58.77#ibcon#flushed, iclass 25, count 0 2006.197.08:21:58.77#ibcon#about to write, iclass 25, count 0 2006.197.08:21:58.77#ibcon#wrote, iclass 25, count 0 2006.197.08:21:58.77#ibcon#about to read 3, iclass 25, count 0 2006.197.08:21:58.79#ibcon#read 3, iclass 25, count 0 2006.197.08:21:58.79#ibcon#about to read 4, iclass 25, count 0 2006.197.08:21:58.79#ibcon#read 4, iclass 25, count 0 2006.197.08:21:58.79#ibcon#about to read 5, iclass 25, count 0 2006.197.08:21:58.79#ibcon#read 5, iclass 25, count 0 2006.197.08:21:58.79#ibcon#about to read 6, iclass 25, count 0 2006.197.08:21:58.79#ibcon#read 6, iclass 25, count 0 2006.197.08:21:58.79#ibcon#end of sib2, iclass 25, count 0 2006.197.08:21:58.79#ibcon#*mode == 0, iclass 25, count 0 2006.197.08:21:58.79#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.197.08:21:58.79#ibcon#[25=USB\r\n] 2006.197.08:21:58.79#ibcon#*before write, iclass 25, count 0 2006.197.08:21:58.79#ibcon#enter sib2, iclass 25, count 0 2006.197.08:21:58.79#ibcon#flushed, iclass 25, count 0 2006.197.08:21:58.79#ibcon#about to write, iclass 25, count 0 2006.197.08:21:58.79#ibcon#wrote, iclass 25, count 0 2006.197.08:21:58.79#ibcon#about to read 3, iclass 25, count 0 2006.197.08:21:58.82#ibcon#read 3, iclass 25, count 0 2006.197.08:21:58.82#ibcon#about to read 4, iclass 25, count 0 2006.197.08:21:58.82#ibcon#read 4, iclass 25, count 0 2006.197.08:21:58.82#ibcon#about to read 5, iclass 25, count 0 2006.197.08:21:58.82#ibcon#read 5, iclass 25, count 0 2006.197.08:21:58.82#ibcon#about to read 6, iclass 25, count 0 2006.197.08:21:58.82#ibcon#read 6, iclass 25, count 0 2006.197.08:21:58.82#ibcon#end of sib2, iclass 25, count 0 2006.197.08:21:58.82#ibcon#*after write, iclass 25, count 0 2006.197.08:21:58.82#ibcon#*before return 0, iclass 25, count 0 2006.197.08:21:58.82#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.197.08:21:58.82#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.197.08:21:58.82#ibcon#about to clear, iclass 25 cls_cnt 0 2006.197.08:21:58.82#ibcon#cleared, iclass 25 cls_cnt 0 2006.197.08:21:58.82$vc4f8/valo=5,652.99 2006.197.08:21:58.82#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.197.08:21:58.82#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.197.08:21:58.82#ibcon#ireg 17 cls_cnt 0 2006.197.08:21:58.82#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.197.08:21:58.82#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.197.08:21:58.82#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.197.08:21:58.82#ibcon#enter wrdev, iclass 27, count 0 2006.197.08:21:58.82#ibcon#first serial, iclass 27, count 0 2006.197.08:21:58.82#ibcon#enter sib2, iclass 27, count 0 2006.197.08:21:58.82#ibcon#flushed, iclass 27, count 0 2006.197.08:21:58.82#ibcon#about to write, iclass 27, count 0 2006.197.08:21:58.82#ibcon#wrote, iclass 27, count 0 2006.197.08:21:58.82#ibcon#about to read 3, iclass 27, count 0 2006.197.08:21:58.84#ibcon#read 3, iclass 27, count 0 2006.197.08:21:58.84#ibcon#about to read 4, iclass 27, count 0 2006.197.08:21:58.84#ibcon#read 4, iclass 27, count 0 2006.197.08:21:58.84#ibcon#about to read 5, iclass 27, count 0 2006.197.08:21:58.84#ibcon#read 5, iclass 27, count 0 2006.197.08:21:58.84#ibcon#about to read 6, iclass 27, count 0 2006.197.08:21:58.84#ibcon#read 6, iclass 27, count 0 2006.197.08:21:58.84#ibcon#end of sib2, iclass 27, count 0 2006.197.08:21:58.84#ibcon#*mode == 0, iclass 27, count 0 2006.197.08:21:58.84#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.197.08:21:58.84#ibcon#[26=FRQ=05,652.99\r\n] 2006.197.08:21:58.84#ibcon#*before write, iclass 27, count 0 2006.197.08:21:58.84#ibcon#enter sib2, iclass 27, count 0 2006.197.08:21:58.84#ibcon#flushed, iclass 27, count 0 2006.197.08:21:58.84#ibcon#about to write, iclass 27, count 0 2006.197.08:21:58.84#ibcon#wrote, iclass 27, count 0 2006.197.08:21:58.84#ibcon#about to read 3, iclass 27, count 0 2006.197.08:21:58.88#ibcon#read 3, iclass 27, count 0 2006.197.08:21:58.88#ibcon#about to read 4, iclass 27, count 0 2006.197.08:21:58.88#ibcon#read 4, iclass 27, count 0 2006.197.08:21:58.88#ibcon#about to read 5, iclass 27, count 0 2006.197.08:21:58.88#ibcon#read 5, iclass 27, count 0 2006.197.08:21:58.88#ibcon#about to read 6, iclass 27, count 0 2006.197.08:21:58.88#ibcon#read 6, iclass 27, count 0 2006.197.08:21:58.88#ibcon#end of sib2, iclass 27, count 0 2006.197.08:21:58.88#ibcon#*after write, iclass 27, count 0 2006.197.08:21:58.88#ibcon#*before return 0, iclass 27, count 0 2006.197.08:21:58.88#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.197.08:21:58.88#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.197.08:21:58.88#ibcon#about to clear, iclass 27 cls_cnt 0 2006.197.08:21:58.88#ibcon#cleared, iclass 27 cls_cnt 0 2006.197.08:21:58.88$vc4f8/va=5,7 2006.197.08:21:58.88#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.197.08:21:58.88#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.197.08:21:58.88#ibcon#ireg 11 cls_cnt 2 2006.197.08:21:58.88#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.197.08:21:58.94#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.197.08:21:58.94#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.197.08:21:58.94#ibcon#enter wrdev, iclass 29, count 2 2006.197.08:21:58.94#ibcon#first serial, iclass 29, count 2 2006.197.08:21:58.94#ibcon#enter sib2, iclass 29, count 2 2006.197.08:21:58.94#ibcon#flushed, iclass 29, count 2 2006.197.08:21:58.94#ibcon#about to write, iclass 29, count 2 2006.197.08:21:58.94#ibcon#wrote, iclass 29, count 2 2006.197.08:21:58.94#ibcon#about to read 3, iclass 29, count 2 2006.197.08:21:58.96#ibcon#read 3, iclass 29, count 2 2006.197.08:21:58.96#ibcon#about to read 4, iclass 29, count 2 2006.197.08:21:58.96#ibcon#read 4, iclass 29, count 2 2006.197.08:21:58.96#ibcon#about to read 5, iclass 29, count 2 2006.197.08:21:58.96#ibcon#read 5, iclass 29, count 2 2006.197.08:21:58.96#ibcon#about to read 6, iclass 29, count 2 2006.197.08:21:58.96#ibcon#read 6, iclass 29, count 2 2006.197.08:21:58.96#ibcon#end of sib2, iclass 29, count 2 2006.197.08:21:58.96#ibcon#*mode == 0, iclass 29, count 2 2006.197.08:21:58.96#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.197.08:21:58.96#ibcon#[25=AT05-07\r\n] 2006.197.08:21:58.96#ibcon#*before write, iclass 29, count 2 2006.197.08:21:58.96#ibcon#enter sib2, iclass 29, count 2 2006.197.08:21:58.96#ibcon#flushed, iclass 29, count 2 2006.197.08:21:58.96#ibcon#about to write, iclass 29, count 2 2006.197.08:21:58.96#ibcon#wrote, iclass 29, count 2 2006.197.08:21:58.96#ibcon#about to read 3, iclass 29, count 2 2006.197.08:21:58.99#ibcon#read 3, iclass 29, count 2 2006.197.08:21:58.99#ibcon#about to read 4, iclass 29, count 2 2006.197.08:21:58.99#ibcon#read 4, iclass 29, count 2 2006.197.08:21:58.99#ibcon#about to read 5, iclass 29, count 2 2006.197.08:21:58.99#ibcon#read 5, iclass 29, count 2 2006.197.08:21:58.99#ibcon#about to read 6, iclass 29, count 2 2006.197.08:21:58.99#ibcon#read 6, iclass 29, count 2 2006.197.08:21:58.99#ibcon#end of sib2, iclass 29, count 2 2006.197.08:21:58.99#ibcon#*after write, iclass 29, count 2 2006.197.08:21:58.99#ibcon#*before return 0, iclass 29, count 2 2006.197.08:21:58.99#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.197.08:21:58.99#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.197.08:21:58.99#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.197.08:21:58.99#ibcon#ireg 7 cls_cnt 0 2006.197.08:21:58.99#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.197.08:21:59.11#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.197.08:21:59.11#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.197.08:21:59.11#ibcon#enter wrdev, iclass 29, count 0 2006.197.08:21:59.11#ibcon#first serial, iclass 29, count 0 2006.197.08:21:59.11#ibcon#enter sib2, iclass 29, count 0 2006.197.08:21:59.11#ibcon#flushed, iclass 29, count 0 2006.197.08:21:59.11#ibcon#about to write, iclass 29, count 0 2006.197.08:21:59.11#ibcon#wrote, iclass 29, count 0 2006.197.08:21:59.11#ibcon#about to read 3, iclass 29, count 0 2006.197.08:21:59.13#ibcon#read 3, iclass 29, count 0 2006.197.08:21:59.13#ibcon#about to read 4, iclass 29, count 0 2006.197.08:21:59.13#ibcon#read 4, iclass 29, count 0 2006.197.08:21:59.13#ibcon#about to read 5, iclass 29, count 0 2006.197.08:21:59.13#ibcon#read 5, iclass 29, count 0 2006.197.08:21:59.13#ibcon#about to read 6, iclass 29, count 0 2006.197.08:21:59.13#ibcon#read 6, iclass 29, count 0 2006.197.08:21:59.13#ibcon#end of sib2, iclass 29, count 0 2006.197.08:21:59.13#ibcon#*mode == 0, iclass 29, count 0 2006.197.08:21:59.13#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.197.08:21:59.13#ibcon#[25=USB\r\n] 2006.197.08:21:59.13#ibcon#*before write, iclass 29, count 0 2006.197.08:21:59.13#ibcon#enter sib2, iclass 29, count 0 2006.197.08:21:59.13#ibcon#flushed, iclass 29, count 0 2006.197.08:21:59.13#ibcon#about to write, iclass 29, count 0 2006.197.08:21:59.13#ibcon#wrote, iclass 29, count 0 2006.197.08:21:59.13#ibcon#about to read 3, iclass 29, count 0 2006.197.08:21:59.16#ibcon#read 3, iclass 29, count 0 2006.197.08:21:59.16#ibcon#about to read 4, iclass 29, count 0 2006.197.08:21:59.16#ibcon#read 4, iclass 29, count 0 2006.197.08:21:59.16#ibcon#about to read 5, iclass 29, count 0 2006.197.08:21:59.16#ibcon#read 5, iclass 29, count 0 2006.197.08:21:59.16#ibcon#about to read 6, iclass 29, count 0 2006.197.08:21:59.16#ibcon#read 6, iclass 29, count 0 2006.197.08:21:59.16#ibcon#end of sib2, iclass 29, count 0 2006.197.08:21:59.16#ibcon#*after write, iclass 29, count 0 2006.197.08:21:59.16#ibcon#*before return 0, iclass 29, count 0 2006.197.08:21:59.16#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.197.08:21:59.16#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.197.08:21:59.16#ibcon#about to clear, iclass 29 cls_cnt 0 2006.197.08:21:59.16#ibcon#cleared, iclass 29 cls_cnt 0 2006.197.08:21:59.16$vc4f8/valo=6,772.99 2006.197.08:21:59.16#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.197.08:21:59.16#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.197.08:21:59.16#ibcon#ireg 17 cls_cnt 0 2006.197.08:21:59.16#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.197.08:21:59.16#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.197.08:21:59.16#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.197.08:21:59.16#ibcon#enter wrdev, iclass 31, count 0 2006.197.08:21:59.16#ibcon#first serial, iclass 31, count 0 2006.197.08:21:59.16#ibcon#enter sib2, iclass 31, count 0 2006.197.08:21:59.16#ibcon#flushed, iclass 31, count 0 2006.197.08:21:59.16#ibcon#about to write, iclass 31, count 0 2006.197.08:21:59.16#ibcon#wrote, iclass 31, count 0 2006.197.08:21:59.16#ibcon#about to read 3, iclass 31, count 0 2006.197.08:21:59.18#ibcon#read 3, iclass 31, count 0 2006.197.08:21:59.18#ibcon#about to read 4, iclass 31, count 0 2006.197.08:21:59.18#ibcon#read 4, iclass 31, count 0 2006.197.08:21:59.18#ibcon#about to read 5, iclass 31, count 0 2006.197.08:21:59.18#ibcon#read 5, iclass 31, count 0 2006.197.08:21:59.18#ibcon#about to read 6, iclass 31, count 0 2006.197.08:21:59.18#ibcon#read 6, iclass 31, count 0 2006.197.08:21:59.18#ibcon#end of sib2, iclass 31, count 0 2006.197.08:21:59.18#ibcon#*mode == 0, iclass 31, count 0 2006.197.08:21:59.18#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.197.08:21:59.18#ibcon#[26=FRQ=06,772.99\r\n] 2006.197.08:21:59.18#ibcon#*before write, iclass 31, count 0 2006.197.08:21:59.18#ibcon#enter sib2, iclass 31, count 0 2006.197.08:21:59.18#ibcon#flushed, iclass 31, count 0 2006.197.08:21:59.18#ibcon#about to write, iclass 31, count 0 2006.197.08:21:59.18#ibcon#wrote, iclass 31, count 0 2006.197.08:21:59.18#ibcon#about to read 3, iclass 31, count 0 2006.197.08:21:59.22#ibcon#read 3, iclass 31, count 0 2006.197.08:21:59.22#ibcon#about to read 4, iclass 31, count 0 2006.197.08:21:59.22#ibcon#read 4, iclass 31, count 0 2006.197.08:21:59.22#ibcon#about to read 5, iclass 31, count 0 2006.197.08:21:59.22#ibcon#read 5, iclass 31, count 0 2006.197.08:21:59.22#ibcon#about to read 6, iclass 31, count 0 2006.197.08:21:59.22#ibcon#read 6, iclass 31, count 0 2006.197.08:21:59.22#ibcon#end of sib2, iclass 31, count 0 2006.197.08:21:59.22#ibcon#*after write, iclass 31, count 0 2006.197.08:21:59.22#ibcon#*before return 0, iclass 31, count 0 2006.197.08:21:59.22#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.197.08:21:59.22#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.197.08:21:59.22#ibcon#about to clear, iclass 31 cls_cnt 0 2006.197.08:21:59.22#ibcon#cleared, iclass 31 cls_cnt 0 2006.197.08:21:59.22$vc4f8/va=6,6 2006.197.08:21:59.22#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.197.08:21:59.22#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.197.08:21:59.22#ibcon#ireg 11 cls_cnt 2 2006.197.08:21:59.22#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.197.08:21:59.28#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.197.08:21:59.28#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.197.08:21:59.28#ibcon#enter wrdev, iclass 33, count 2 2006.197.08:21:59.28#ibcon#first serial, iclass 33, count 2 2006.197.08:21:59.28#ibcon#enter sib2, iclass 33, count 2 2006.197.08:21:59.28#ibcon#flushed, iclass 33, count 2 2006.197.08:21:59.28#ibcon#about to write, iclass 33, count 2 2006.197.08:21:59.28#ibcon#wrote, iclass 33, count 2 2006.197.08:21:59.28#ibcon#about to read 3, iclass 33, count 2 2006.197.08:21:59.30#ibcon#read 3, iclass 33, count 2 2006.197.08:21:59.30#ibcon#about to read 4, iclass 33, count 2 2006.197.08:21:59.30#ibcon#read 4, iclass 33, count 2 2006.197.08:21:59.30#ibcon#about to read 5, iclass 33, count 2 2006.197.08:21:59.30#ibcon#read 5, iclass 33, count 2 2006.197.08:21:59.30#ibcon#about to read 6, iclass 33, count 2 2006.197.08:21:59.30#ibcon#read 6, iclass 33, count 2 2006.197.08:21:59.30#ibcon#end of sib2, iclass 33, count 2 2006.197.08:21:59.30#ibcon#*mode == 0, iclass 33, count 2 2006.197.08:21:59.30#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.197.08:21:59.30#ibcon#[25=AT06-06\r\n] 2006.197.08:21:59.30#ibcon#*before write, iclass 33, count 2 2006.197.08:21:59.30#ibcon#enter sib2, iclass 33, count 2 2006.197.08:21:59.30#ibcon#flushed, iclass 33, count 2 2006.197.08:21:59.30#ibcon#about to write, iclass 33, count 2 2006.197.08:21:59.30#ibcon#wrote, iclass 33, count 2 2006.197.08:21:59.30#ibcon#about to read 3, iclass 33, count 2 2006.197.08:21:59.33#ibcon#read 3, iclass 33, count 2 2006.197.08:21:59.33#ibcon#about to read 4, iclass 33, count 2 2006.197.08:21:59.33#ibcon#read 4, iclass 33, count 2 2006.197.08:21:59.33#ibcon#about to read 5, iclass 33, count 2 2006.197.08:21:59.33#ibcon#read 5, iclass 33, count 2 2006.197.08:21:59.33#ibcon#about to read 6, iclass 33, count 2 2006.197.08:21:59.33#ibcon#read 6, iclass 33, count 2 2006.197.08:21:59.33#ibcon#end of sib2, iclass 33, count 2 2006.197.08:21:59.33#ibcon#*after write, iclass 33, count 2 2006.197.08:21:59.33#ibcon#*before return 0, iclass 33, count 2 2006.197.08:21:59.33#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.197.08:21:59.33#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.197.08:21:59.33#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.197.08:21:59.33#ibcon#ireg 7 cls_cnt 0 2006.197.08:21:59.33#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.197.08:21:59.45#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.197.08:21:59.45#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.197.08:21:59.45#ibcon#enter wrdev, iclass 33, count 0 2006.197.08:21:59.45#ibcon#first serial, iclass 33, count 0 2006.197.08:21:59.45#ibcon#enter sib2, iclass 33, count 0 2006.197.08:21:59.45#ibcon#flushed, iclass 33, count 0 2006.197.08:21:59.45#ibcon#about to write, iclass 33, count 0 2006.197.08:21:59.45#ibcon#wrote, iclass 33, count 0 2006.197.08:21:59.45#ibcon#about to read 3, iclass 33, count 0 2006.197.08:21:59.47#ibcon#read 3, iclass 33, count 0 2006.197.08:21:59.47#ibcon#about to read 4, iclass 33, count 0 2006.197.08:21:59.47#ibcon#read 4, iclass 33, count 0 2006.197.08:21:59.47#ibcon#about to read 5, iclass 33, count 0 2006.197.08:21:59.47#ibcon#read 5, iclass 33, count 0 2006.197.08:21:59.47#ibcon#about to read 6, iclass 33, count 0 2006.197.08:21:59.47#ibcon#read 6, iclass 33, count 0 2006.197.08:21:59.47#ibcon#end of sib2, iclass 33, count 0 2006.197.08:21:59.47#ibcon#*mode == 0, iclass 33, count 0 2006.197.08:21:59.47#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.197.08:21:59.47#ibcon#[25=USB\r\n] 2006.197.08:21:59.47#ibcon#*before write, iclass 33, count 0 2006.197.08:21:59.47#ibcon#enter sib2, iclass 33, count 0 2006.197.08:21:59.47#ibcon#flushed, iclass 33, count 0 2006.197.08:21:59.47#ibcon#about to write, iclass 33, count 0 2006.197.08:21:59.47#ibcon#wrote, iclass 33, count 0 2006.197.08:21:59.47#ibcon#about to read 3, iclass 33, count 0 2006.197.08:21:59.50#ibcon#read 3, iclass 33, count 0 2006.197.08:21:59.50#ibcon#about to read 4, iclass 33, count 0 2006.197.08:21:59.50#ibcon#read 4, iclass 33, count 0 2006.197.08:21:59.50#ibcon#about to read 5, iclass 33, count 0 2006.197.08:21:59.50#ibcon#read 5, iclass 33, count 0 2006.197.08:21:59.50#ibcon#about to read 6, iclass 33, count 0 2006.197.08:21:59.50#ibcon#read 6, iclass 33, count 0 2006.197.08:21:59.50#ibcon#end of sib2, iclass 33, count 0 2006.197.08:21:59.50#ibcon#*after write, iclass 33, count 0 2006.197.08:21:59.50#ibcon#*before return 0, iclass 33, count 0 2006.197.08:21:59.50#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.197.08:21:59.50#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.197.08:21:59.50#ibcon#about to clear, iclass 33 cls_cnt 0 2006.197.08:21:59.50#ibcon#cleared, iclass 33 cls_cnt 0 2006.197.08:21:59.50$vc4f8/valo=7,832.99 2006.197.08:21:59.50#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.197.08:21:59.50#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.197.08:21:59.50#ibcon#ireg 17 cls_cnt 0 2006.197.08:21:59.50#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.197.08:21:59.50#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.197.08:21:59.50#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.197.08:21:59.50#ibcon#enter wrdev, iclass 35, count 0 2006.197.08:21:59.50#ibcon#first serial, iclass 35, count 0 2006.197.08:21:59.50#ibcon#enter sib2, iclass 35, count 0 2006.197.08:21:59.50#ibcon#flushed, iclass 35, count 0 2006.197.08:21:59.50#ibcon#about to write, iclass 35, count 0 2006.197.08:21:59.50#ibcon#wrote, iclass 35, count 0 2006.197.08:21:59.50#ibcon#about to read 3, iclass 35, count 0 2006.197.08:21:59.52#ibcon#read 3, iclass 35, count 0 2006.197.08:21:59.52#ibcon#about to read 4, iclass 35, count 0 2006.197.08:21:59.52#ibcon#read 4, iclass 35, count 0 2006.197.08:21:59.52#ibcon#about to read 5, iclass 35, count 0 2006.197.08:21:59.52#ibcon#read 5, iclass 35, count 0 2006.197.08:21:59.52#ibcon#about to read 6, iclass 35, count 0 2006.197.08:21:59.52#ibcon#read 6, iclass 35, count 0 2006.197.08:21:59.52#ibcon#end of sib2, iclass 35, count 0 2006.197.08:21:59.52#ibcon#*mode == 0, iclass 35, count 0 2006.197.08:21:59.52#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.197.08:21:59.52#ibcon#[26=FRQ=07,832.99\r\n] 2006.197.08:21:59.52#ibcon#*before write, iclass 35, count 0 2006.197.08:21:59.52#ibcon#enter sib2, iclass 35, count 0 2006.197.08:21:59.52#ibcon#flushed, iclass 35, count 0 2006.197.08:21:59.52#ibcon#about to write, iclass 35, count 0 2006.197.08:21:59.52#ibcon#wrote, iclass 35, count 0 2006.197.08:21:59.52#ibcon#about to read 3, iclass 35, count 0 2006.197.08:21:59.56#ibcon#read 3, iclass 35, count 0 2006.197.08:21:59.56#ibcon#about to read 4, iclass 35, count 0 2006.197.08:21:59.56#ibcon#read 4, iclass 35, count 0 2006.197.08:21:59.56#ibcon#about to read 5, iclass 35, count 0 2006.197.08:21:59.56#ibcon#read 5, iclass 35, count 0 2006.197.08:21:59.56#ibcon#about to read 6, iclass 35, count 0 2006.197.08:21:59.56#ibcon#read 6, iclass 35, count 0 2006.197.08:21:59.56#ibcon#end of sib2, iclass 35, count 0 2006.197.08:21:59.56#ibcon#*after write, iclass 35, count 0 2006.197.08:21:59.56#ibcon#*before return 0, iclass 35, count 0 2006.197.08:21:59.56#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.197.08:21:59.56#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.197.08:21:59.56#ibcon#about to clear, iclass 35 cls_cnt 0 2006.197.08:21:59.56#ibcon#cleared, iclass 35 cls_cnt 0 2006.197.08:21:59.56$vc4f8/va=7,6 2006.197.08:21:59.56#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.197.08:21:59.56#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.197.08:21:59.56#ibcon#ireg 11 cls_cnt 2 2006.197.08:21:59.56#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.197.08:21:59.62#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.197.08:21:59.62#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.197.08:21:59.62#ibcon#enter wrdev, iclass 37, count 2 2006.197.08:21:59.62#ibcon#first serial, iclass 37, count 2 2006.197.08:21:59.62#ibcon#enter sib2, iclass 37, count 2 2006.197.08:21:59.62#ibcon#flushed, iclass 37, count 2 2006.197.08:21:59.62#ibcon#about to write, iclass 37, count 2 2006.197.08:21:59.62#ibcon#wrote, iclass 37, count 2 2006.197.08:21:59.62#ibcon#about to read 3, iclass 37, count 2 2006.197.08:21:59.64#ibcon#read 3, iclass 37, count 2 2006.197.08:21:59.64#ibcon#about to read 4, iclass 37, count 2 2006.197.08:21:59.64#ibcon#read 4, iclass 37, count 2 2006.197.08:21:59.64#ibcon#about to read 5, iclass 37, count 2 2006.197.08:21:59.64#ibcon#read 5, iclass 37, count 2 2006.197.08:21:59.64#ibcon#about to read 6, iclass 37, count 2 2006.197.08:21:59.64#ibcon#read 6, iclass 37, count 2 2006.197.08:21:59.64#ibcon#end of sib2, iclass 37, count 2 2006.197.08:21:59.64#ibcon#*mode == 0, iclass 37, count 2 2006.197.08:21:59.64#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.197.08:21:59.64#ibcon#[25=AT07-06\r\n] 2006.197.08:21:59.64#ibcon#*before write, iclass 37, count 2 2006.197.08:21:59.64#ibcon#enter sib2, iclass 37, count 2 2006.197.08:21:59.64#ibcon#flushed, iclass 37, count 2 2006.197.08:21:59.64#ibcon#about to write, iclass 37, count 2 2006.197.08:21:59.64#ibcon#wrote, iclass 37, count 2 2006.197.08:21:59.64#ibcon#about to read 3, iclass 37, count 2 2006.197.08:21:59.67#ibcon#read 3, iclass 37, count 2 2006.197.08:21:59.67#ibcon#about to read 4, iclass 37, count 2 2006.197.08:21:59.67#ibcon#read 4, iclass 37, count 2 2006.197.08:21:59.67#ibcon#about to read 5, iclass 37, count 2 2006.197.08:21:59.67#ibcon#read 5, iclass 37, count 2 2006.197.08:21:59.67#ibcon#about to read 6, iclass 37, count 2 2006.197.08:21:59.67#ibcon#read 6, iclass 37, count 2 2006.197.08:21:59.67#ibcon#end of sib2, iclass 37, count 2 2006.197.08:21:59.67#ibcon#*after write, iclass 37, count 2 2006.197.08:21:59.67#ibcon#*before return 0, iclass 37, count 2 2006.197.08:21:59.67#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.197.08:21:59.67#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.197.08:21:59.67#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.197.08:21:59.67#ibcon#ireg 7 cls_cnt 0 2006.197.08:21:59.67#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.197.08:21:59.79#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.197.08:21:59.79#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.197.08:21:59.79#ibcon#enter wrdev, iclass 37, count 0 2006.197.08:21:59.79#ibcon#first serial, iclass 37, count 0 2006.197.08:21:59.79#ibcon#enter sib2, iclass 37, count 0 2006.197.08:21:59.79#ibcon#flushed, iclass 37, count 0 2006.197.08:21:59.79#ibcon#about to write, iclass 37, count 0 2006.197.08:21:59.79#ibcon#wrote, iclass 37, count 0 2006.197.08:21:59.79#ibcon#about to read 3, iclass 37, count 0 2006.197.08:21:59.81#ibcon#read 3, iclass 37, count 0 2006.197.08:21:59.81#ibcon#about to read 4, iclass 37, count 0 2006.197.08:21:59.81#ibcon#read 4, iclass 37, count 0 2006.197.08:21:59.81#ibcon#about to read 5, iclass 37, count 0 2006.197.08:21:59.81#ibcon#read 5, iclass 37, count 0 2006.197.08:21:59.81#ibcon#about to read 6, iclass 37, count 0 2006.197.08:21:59.81#ibcon#read 6, iclass 37, count 0 2006.197.08:21:59.81#ibcon#end of sib2, iclass 37, count 0 2006.197.08:21:59.81#ibcon#*mode == 0, iclass 37, count 0 2006.197.08:21:59.81#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.197.08:21:59.81#ibcon#[25=USB\r\n] 2006.197.08:21:59.81#ibcon#*before write, iclass 37, count 0 2006.197.08:21:59.81#ibcon#enter sib2, iclass 37, count 0 2006.197.08:21:59.81#ibcon#flushed, iclass 37, count 0 2006.197.08:21:59.81#ibcon#about to write, iclass 37, count 0 2006.197.08:21:59.81#ibcon#wrote, iclass 37, count 0 2006.197.08:21:59.81#ibcon#about to read 3, iclass 37, count 0 2006.197.08:21:59.84#ibcon#read 3, iclass 37, count 0 2006.197.08:21:59.84#ibcon#about to read 4, iclass 37, count 0 2006.197.08:21:59.84#ibcon#read 4, iclass 37, count 0 2006.197.08:21:59.84#ibcon#about to read 5, iclass 37, count 0 2006.197.08:21:59.84#ibcon#read 5, iclass 37, count 0 2006.197.08:21:59.84#ibcon#about to read 6, iclass 37, count 0 2006.197.08:21:59.84#ibcon#read 6, iclass 37, count 0 2006.197.08:21:59.84#ibcon#end of sib2, iclass 37, count 0 2006.197.08:21:59.84#ibcon#*after write, iclass 37, count 0 2006.197.08:21:59.84#ibcon#*before return 0, iclass 37, count 0 2006.197.08:21:59.84#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.197.08:21:59.84#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.197.08:21:59.84#ibcon#about to clear, iclass 37 cls_cnt 0 2006.197.08:21:59.84#ibcon#cleared, iclass 37 cls_cnt 0 2006.197.08:21:59.84$vc4f8/valo=8,852.99 2006.197.08:21:59.84#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.197.08:21:59.84#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.197.08:21:59.84#ibcon#ireg 17 cls_cnt 0 2006.197.08:21:59.84#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.197.08:21:59.84#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.197.08:21:59.84#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.197.08:21:59.84#ibcon#enter wrdev, iclass 39, count 0 2006.197.08:21:59.84#ibcon#first serial, iclass 39, count 0 2006.197.08:21:59.84#ibcon#enter sib2, iclass 39, count 0 2006.197.08:21:59.84#ibcon#flushed, iclass 39, count 0 2006.197.08:21:59.84#ibcon#about to write, iclass 39, count 0 2006.197.08:21:59.84#ibcon#wrote, iclass 39, count 0 2006.197.08:21:59.84#ibcon#about to read 3, iclass 39, count 0 2006.197.08:21:59.86#ibcon#read 3, iclass 39, count 0 2006.197.08:21:59.86#ibcon#about to read 4, iclass 39, count 0 2006.197.08:21:59.86#ibcon#read 4, iclass 39, count 0 2006.197.08:21:59.86#ibcon#about to read 5, iclass 39, count 0 2006.197.08:21:59.86#ibcon#read 5, iclass 39, count 0 2006.197.08:21:59.86#ibcon#about to read 6, iclass 39, count 0 2006.197.08:21:59.86#ibcon#read 6, iclass 39, count 0 2006.197.08:21:59.86#ibcon#end of sib2, iclass 39, count 0 2006.197.08:21:59.86#ibcon#*mode == 0, iclass 39, count 0 2006.197.08:21:59.86#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.197.08:21:59.86#ibcon#[26=FRQ=08,852.99\r\n] 2006.197.08:21:59.86#ibcon#*before write, iclass 39, count 0 2006.197.08:21:59.86#ibcon#enter sib2, iclass 39, count 0 2006.197.08:21:59.86#ibcon#flushed, iclass 39, count 0 2006.197.08:21:59.86#ibcon#about to write, iclass 39, count 0 2006.197.08:21:59.86#ibcon#wrote, iclass 39, count 0 2006.197.08:21:59.86#ibcon#about to read 3, iclass 39, count 0 2006.197.08:21:59.90#ibcon#read 3, iclass 39, count 0 2006.197.08:21:59.90#ibcon#about to read 4, iclass 39, count 0 2006.197.08:21:59.90#ibcon#read 4, iclass 39, count 0 2006.197.08:21:59.90#ibcon#about to read 5, iclass 39, count 0 2006.197.08:21:59.90#ibcon#read 5, iclass 39, count 0 2006.197.08:21:59.90#ibcon#about to read 6, iclass 39, count 0 2006.197.08:21:59.90#ibcon#read 6, iclass 39, count 0 2006.197.08:21:59.90#ibcon#end of sib2, iclass 39, count 0 2006.197.08:21:59.90#ibcon#*after write, iclass 39, count 0 2006.197.08:21:59.90#ibcon#*before return 0, iclass 39, count 0 2006.197.08:21:59.90#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.197.08:21:59.90#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.197.08:21:59.90#ibcon#about to clear, iclass 39 cls_cnt 0 2006.197.08:21:59.90#ibcon#cleared, iclass 39 cls_cnt 0 2006.197.08:21:59.90$vc4f8/va=8,7 2006.197.08:21:59.90#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.197.08:21:59.90#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.197.08:21:59.90#ibcon#ireg 11 cls_cnt 2 2006.197.08:21:59.90#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.197.08:21:59.96#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.197.08:21:59.96#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.197.08:21:59.96#ibcon#enter wrdev, iclass 3, count 2 2006.197.08:21:59.96#ibcon#first serial, iclass 3, count 2 2006.197.08:21:59.96#ibcon#enter sib2, iclass 3, count 2 2006.197.08:21:59.96#ibcon#flushed, iclass 3, count 2 2006.197.08:21:59.96#ibcon#about to write, iclass 3, count 2 2006.197.08:21:59.96#ibcon#wrote, iclass 3, count 2 2006.197.08:21:59.96#ibcon#about to read 3, iclass 3, count 2 2006.197.08:21:59.98#ibcon#read 3, iclass 3, count 2 2006.197.08:21:59.98#ibcon#about to read 4, iclass 3, count 2 2006.197.08:21:59.98#ibcon#read 4, iclass 3, count 2 2006.197.08:21:59.98#ibcon#about to read 5, iclass 3, count 2 2006.197.08:21:59.98#ibcon#read 5, iclass 3, count 2 2006.197.08:21:59.98#ibcon#about to read 6, iclass 3, count 2 2006.197.08:21:59.98#ibcon#read 6, iclass 3, count 2 2006.197.08:21:59.98#ibcon#end of sib2, iclass 3, count 2 2006.197.08:21:59.98#ibcon#*mode == 0, iclass 3, count 2 2006.197.08:21:59.98#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.197.08:21:59.98#ibcon#[25=AT08-07\r\n] 2006.197.08:21:59.98#ibcon#*before write, iclass 3, count 2 2006.197.08:21:59.98#ibcon#enter sib2, iclass 3, count 2 2006.197.08:21:59.98#ibcon#flushed, iclass 3, count 2 2006.197.08:21:59.98#ibcon#about to write, iclass 3, count 2 2006.197.08:21:59.98#ibcon#wrote, iclass 3, count 2 2006.197.08:21:59.98#ibcon#about to read 3, iclass 3, count 2 2006.197.08:22:00.01#ibcon#read 3, iclass 3, count 2 2006.197.08:22:00.01#ibcon#about to read 4, iclass 3, count 2 2006.197.08:22:00.01#ibcon#read 4, iclass 3, count 2 2006.197.08:22:00.01#ibcon#about to read 5, iclass 3, count 2 2006.197.08:22:00.01#ibcon#read 5, iclass 3, count 2 2006.197.08:22:00.01#ibcon#about to read 6, iclass 3, count 2 2006.197.08:22:00.01#ibcon#read 6, iclass 3, count 2 2006.197.08:22:00.01#ibcon#end of sib2, iclass 3, count 2 2006.197.08:22:00.01#ibcon#*after write, iclass 3, count 2 2006.197.08:22:00.01#ibcon#*before return 0, iclass 3, count 2 2006.197.08:22:00.01#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.197.08:22:00.01#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.197.08:22:00.01#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.197.08:22:00.01#ibcon#ireg 7 cls_cnt 0 2006.197.08:22:00.01#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.197.08:22:00.13#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.197.08:22:00.13#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.197.08:22:00.13#ibcon#enter wrdev, iclass 3, count 0 2006.197.08:22:00.13#ibcon#first serial, iclass 3, count 0 2006.197.08:22:00.13#ibcon#enter sib2, iclass 3, count 0 2006.197.08:22:00.13#ibcon#flushed, iclass 3, count 0 2006.197.08:22:00.13#ibcon#about to write, iclass 3, count 0 2006.197.08:22:00.13#ibcon#wrote, iclass 3, count 0 2006.197.08:22:00.13#ibcon#about to read 3, iclass 3, count 0 2006.197.08:22:00.15#ibcon#read 3, iclass 3, count 0 2006.197.08:22:00.15#ibcon#about to read 4, iclass 3, count 0 2006.197.08:22:00.15#ibcon#read 4, iclass 3, count 0 2006.197.08:22:00.15#ibcon#about to read 5, iclass 3, count 0 2006.197.08:22:00.15#ibcon#read 5, iclass 3, count 0 2006.197.08:22:00.15#ibcon#about to read 6, iclass 3, count 0 2006.197.08:22:00.15#ibcon#read 6, iclass 3, count 0 2006.197.08:22:00.15#ibcon#end of sib2, iclass 3, count 0 2006.197.08:22:00.15#ibcon#*mode == 0, iclass 3, count 0 2006.197.08:22:00.15#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.197.08:22:00.15#ibcon#[25=USB\r\n] 2006.197.08:22:00.15#ibcon#*before write, iclass 3, count 0 2006.197.08:22:00.15#ibcon#enter sib2, iclass 3, count 0 2006.197.08:22:00.15#ibcon#flushed, iclass 3, count 0 2006.197.08:22:00.15#ibcon#about to write, iclass 3, count 0 2006.197.08:22:00.15#ibcon#wrote, iclass 3, count 0 2006.197.08:22:00.15#ibcon#about to read 3, iclass 3, count 0 2006.197.08:22:00.18#ibcon#read 3, iclass 3, count 0 2006.197.08:22:00.18#ibcon#about to read 4, iclass 3, count 0 2006.197.08:22:00.18#ibcon#read 4, iclass 3, count 0 2006.197.08:22:00.18#ibcon#about to read 5, iclass 3, count 0 2006.197.08:22:00.18#ibcon#read 5, iclass 3, count 0 2006.197.08:22:00.18#ibcon#about to read 6, iclass 3, count 0 2006.197.08:22:00.18#ibcon#read 6, iclass 3, count 0 2006.197.08:22:00.18#ibcon#end of sib2, iclass 3, count 0 2006.197.08:22:00.18#ibcon#*after write, iclass 3, count 0 2006.197.08:22:00.18#ibcon#*before return 0, iclass 3, count 0 2006.197.08:22:00.18#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.197.08:22:00.18#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.197.08:22:00.18#ibcon#about to clear, iclass 3 cls_cnt 0 2006.197.08:22:00.18#ibcon#cleared, iclass 3 cls_cnt 0 2006.197.08:22:00.18$vc4f8/vblo=1,632.99 2006.197.08:22:00.18#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.197.08:22:00.18#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.197.08:22:00.18#ibcon#ireg 17 cls_cnt 0 2006.197.08:22:00.18#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.197.08:22:00.18#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.197.08:22:00.18#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.197.08:22:00.18#ibcon#enter wrdev, iclass 5, count 0 2006.197.08:22:00.18#ibcon#first serial, iclass 5, count 0 2006.197.08:22:00.18#ibcon#enter sib2, iclass 5, count 0 2006.197.08:22:00.18#ibcon#flushed, iclass 5, count 0 2006.197.08:22:00.18#ibcon#about to write, iclass 5, count 0 2006.197.08:22:00.18#ibcon#wrote, iclass 5, count 0 2006.197.08:22:00.18#ibcon#about to read 3, iclass 5, count 0 2006.197.08:22:00.20#ibcon#read 3, iclass 5, count 0 2006.197.08:22:00.20#ibcon#about to read 4, iclass 5, count 0 2006.197.08:22:00.20#ibcon#read 4, iclass 5, count 0 2006.197.08:22:00.20#ibcon#about to read 5, iclass 5, count 0 2006.197.08:22:00.20#ibcon#read 5, iclass 5, count 0 2006.197.08:22:00.20#ibcon#about to read 6, iclass 5, count 0 2006.197.08:22:00.20#ibcon#read 6, iclass 5, count 0 2006.197.08:22:00.20#ibcon#end of sib2, iclass 5, count 0 2006.197.08:22:00.20#ibcon#*mode == 0, iclass 5, count 0 2006.197.08:22:00.20#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.197.08:22:00.20#ibcon#[28=FRQ=01,632.99\r\n] 2006.197.08:22:00.20#ibcon#*before write, iclass 5, count 0 2006.197.08:22:00.20#ibcon#enter sib2, iclass 5, count 0 2006.197.08:22:00.20#ibcon#flushed, iclass 5, count 0 2006.197.08:22:00.20#ibcon#about to write, iclass 5, count 0 2006.197.08:22:00.20#ibcon#wrote, iclass 5, count 0 2006.197.08:22:00.20#ibcon#about to read 3, iclass 5, count 0 2006.197.08:22:00.24#ibcon#read 3, iclass 5, count 0 2006.197.08:22:00.24#ibcon#about to read 4, iclass 5, count 0 2006.197.08:22:00.24#ibcon#read 4, iclass 5, count 0 2006.197.08:22:00.24#ibcon#about to read 5, iclass 5, count 0 2006.197.08:22:00.24#ibcon#read 5, iclass 5, count 0 2006.197.08:22:00.24#ibcon#about to read 6, iclass 5, count 0 2006.197.08:22:00.24#ibcon#read 6, iclass 5, count 0 2006.197.08:22:00.24#ibcon#end of sib2, iclass 5, count 0 2006.197.08:22:00.24#ibcon#*after write, iclass 5, count 0 2006.197.08:22:00.24#ibcon#*before return 0, iclass 5, count 0 2006.197.08:22:00.24#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.197.08:22:00.24#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.197.08:22:00.24#ibcon#about to clear, iclass 5 cls_cnt 0 2006.197.08:22:00.24#ibcon#cleared, iclass 5 cls_cnt 0 2006.197.08:22:00.24$vc4f8/vb=1,4 2006.197.08:22:00.24#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.197.08:22:00.24#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.197.08:22:00.24#ibcon#ireg 11 cls_cnt 2 2006.197.08:22:00.24#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.197.08:22:00.24#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.197.08:22:00.24#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.197.08:22:00.24#ibcon#enter wrdev, iclass 7, count 2 2006.197.08:22:00.24#ibcon#first serial, iclass 7, count 2 2006.197.08:22:00.24#ibcon#enter sib2, iclass 7, count 2 2006.197.08:22:00.24#ibcon#flushed, iclass 7, count 2 2006.197.08:22:00.24#ibcon#about to write, iclass 7, count 2 2006.197.08:22:00.24#ibcon#wrote, iclass 7, count 2 2006.197.08:22:00.24#ibcon#about to read 3, iclass 7, count 2 2006.197.08:22:00.26#ibcon#read 3, iclass 7, count 2 2006.197.08:22:00.26#ibcon#about to read 4, iclass 7, count 2 2006.197.08:22:00.26#ibcon#read 4, iclass 7, count 2 2006.197.08:22:00.26#ibcon#about to read 5, iclass 7, count 2 2006.197.08:22:00.26#ibcon#read 5, iclass 7, count 2 2006.197.08:22:00.26#ibcon#about to read 6, iclass 7, count 2 2006.197.08:22:00.26#ibcon#read 6, iclass 7, count 2 2006.197.08:22:00.26#ibcon#end of sib2, iclass 7, count 2 2006.197.08:22:00.26#ibcon#*mode == 0, iclass 7, count 2 2006.197.08:22:00.26#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.197.08:22:00.26#ibcon#[27=AT01-04\r\n] 2006.197.08:22:00.26#ibcon#*before write, iclass 7, count 2 2006.197.08:22:00.26#ibcon#enter sib2, iclass 7, count 2 2006.197.08:22:00.26#ibcon#flushed, iclass 7, count 2 2006.197.08:22:00.26#ibcon#about to write, iclass 7, count 2 2006.197.08:22:00.26#ibcon#wrote, iclass 7, count 2 2006.197.08:22:00.26#ibcon#about to read 3, iclass 7, count 2 2006.197.08:22:00.29#ibcon#read 3, iclass 7, count 2 2006.197.08:22:00.29#ibcon#about to read 4, iclass 7, count 2 2006.197.08:22:00.29#ibcon#read 4, iclass 7, count 2 2006.197.08:22:00.29#ibcon#about to read 5, iclass 7, count 2 2006.197.08:22:00.29#ibcon#read 5, iclass 7, count 2 2006.197.08:22:00.29#ibcon#about to read 6, iclass 7, count 2 2006.197.08:22:00.29#ibcon#read 6, iclass 7, count 2 2006.197.08:22:00.29#ibcon#end of sib2, iclass 7, count 2 2006.197.08:22:00.29#ibcon#*after write, iclass 7, count 2 2006.197.08:22:00.29#ibcon#*before return 0, iclass 7, count 2 2006.197.08:22:00.29#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.197.08:22:00.29#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.197.08:22:00.29#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.197.08:22:00.29#ibcon#ireg 7 cls_cnt 0 2006.197.08:22:00.29#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.197.08:22:00.41#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.197.08:22:00.41#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.197.08:22:00.41#ibcon#enter wrdev, iclass 7, count 0 2006.197.08:22:00.41#ibcon#first serial, iclass 7, count 0 2006.197.08:22:00.41#ibcon#enter sib2, iclass 7, count 0 2006.197.08:22:00.41#ibcon#flushed, iclass 7, count 0 2006.197.08:22:00.41#ibcon#about to write, iclass 7, count 0 2006.197.08:22:00.41#ibcon#wrote, iclass 7, count 0 2006.197.08:22:00.41#ibcon#about to read 3, iclass 7, count 0 2006.197.08:22:00.43#ibcon#read 3, iclass 7, count 0 2006.197.08:22:00.43#ibcon#about to read 4, iclass 7, count 0 2006.197.08:22:00.43#ibcon#read 4, iclass 7, count 0 2006.197.08:22:00.43#ibcon#about to read 5, iclass 7, count 0 2006.197.08:22:00.43#ibcon#read 5, iclass 7, count 0 2006.197.08:22:00.43#ibcon#about to read 6, iclass 7, count 0 2006.197.08:22:00.43#ibcon#read 6, iclass 7, count 0 2006.197.08:22:00.43#ibcon#end of sib2, iclass 7, count 0 2006.197.08:22:00.43#ibcon#*mode == 0, iclass 7, count 0 2006.197.08:22:00.43#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.197.08:22:00.43#ibcon#[27=USB\r\n] 2006.197.08:22:00.43#ibcon#*before write, iclass 7, count 0 2006.197.08:22:00.43#ibcon#enter sib2, iclass 7, count 0 2006.197.08:22:00.43#ibcon#flushed, iclass 7, count 0 2006.197.08:22:00.43#ibcon#about to write, iclass 7, count 0 2006.197.08:22:00.43#ibcon#wrote, iclass 7, count 0 2006.197.08:22:00.43#ibcon#about to read 3, iclass 7, count 0 2006.197.08:22:00.46#ibcon#read 3, iclass 7, count 0 2006.197.08:22:00.46#ibcon#about to read 4, iclass 7, count 0 2006.197.08:22:00.46#ibcon#read 4, iclass 7, count 0 2006.197.08:22:00.46#ibcon#about to read 5, iclass 7, count 0 2006.197.08:22:00.46#ibcon#read 5, iclass 7, count 0 2006.197.08:22:00.46#ibcon#about to read 6, iclass 7, count 0 2006.197.08:22:00.46#ibcon#read 6, iclass 7, count 0 2006.197.08:22:00.46#ibcon#end of sib2, iclass 7, count 0 2006.197.08:22:00.46#ibcon#*after write, iclass 7, count 0 2006.197.08:22:00.46#ibcon#*before return 0, iclass 7, count 0 2006.197.08:22:00.46#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.197.08:22:00.46#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.197.08:22:00.46#ibcon#about to clear, iclass 7 cls_cnt 0 2006.197.08:22:00.46#ibcon#cleared, iclass 7 cls_cnt 0 2006.197.08:22:00.46$vc4f8/vblo=2,640.99 2006.197.08:22:00.46#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.197.08:22:00.46#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.197.08:22:00.46#ibcon#ireg 17 cls_cnt 0 2006.197.08:22:00.46#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.197.08:22:00.46#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.197.08:22:00.46#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.197.08:22:00.46#ibcon#enter wrdev, iclass 11, count 0 2006.197.08:22:00.46#ibcon#first serial, iclass 11, count 0 2006.197.08:22:00.46#ibcon#enter sib2, iclass 11, count 0 2006.197.08:22:00.46#ibcon#flushed, iclass 11, count 0 2006.197.08:22:00.46#ibcon#about to write, iclass 11, count 0 2006.197.08:22:00.46#ibcon#wrote, iclass 11, count 0 2006.197.08:22:00.46#ibcon#about to read 3, iclass 11, count 0 2006.197.08:22:00.48#ibcon#read 3, iclass 11, count 0 2006.197.08:22:00.48#ibcon#about to read 4, iclass 11, count 0 2006.197.08:22:00.48#ibcon#read 4, iclass 11, count 0 2006.197.08:22:00.48#ibcon#about to read 5, iclass 11, count 0 2006.197.08:22:00.48#ibcon#read 5, iclass 11, count 0 2006.197.08:22:00.48#ibcon#about to read 6, iclass 11, count 0 2006.197.08:22:00.48#ibcon#read 6, iclass 11, count 0 2006.197.08:22:00.48#ibcon#end of sib2, iclass 11, count 0 2006.197.08:22:00.48#ibcon#*mode == 0, iclass 11, count 0 2006.197.08:22:00.48#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.197.08:22:00.48#ibcon#[28=FRQ=02,640.99\r\n] 2006.197.08:22:00.48#ibcon#*before write, iclass 11, count 0 2006.197.08:22:00.48#ibcon#enter sib2, iclass 11, count 0 2006.197.08:22:00.48#ibcon#flushed, iclass 11, count 0 2006.197.08:22:00.48#ibcon#about to write, iclass 11, count 0 2006.197.08:22:00.48#ibcon#wrote, iclass 11, count 0 2006.197.08:22:00.48#ibcon#about to read 3, iclass 11, count 0 2006.197.08:22:00.52#ibcon#read 3, iclass 11, count 0 2006.197.08:22:00.52#ibcon#about to read 4, iclass 11, count 0 2006.197.08:22:00.52#ibcon#read 4, iclass 11, count 0 2006.197.08:22:00.52#ibcon#about to read 5, iclass 11, count 0 2006.197.08:22:00.52#ibcon#read 5, iclass 11, count 0 2006.197.08:22:00.52#ibcon#about to read 6, iclass 11, count 0 2006.197.08:22:00.52#ibcon#read 6, iclass 11, count 0 2006.197.08:22:00.52#ibcon#end of sib2, iclass 11, count 0 2006.197.08:22:00.52#ibcon#*after write, iclass 11, count 0 2006.197.08:22:00.52#ibcon#*before return 0, iclass 11, count 0 2006.197.08:22:00.52#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.197.08:22:00.52#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.197.08:22:00.52#ibcon#about to clear, iclass 11 cls_cnt 0 2006.197.08:22:00.52#ibcon#cleared, iclass 11 cls_cnt 0 2006.197.08:22:00.52$vc4f8/vb=2,4 2006.197.08:22:00.52#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.197.08:22:00.52#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.197.08:22:00.52#ibcon#ireg 11 cls_cnt 2 2006.197.08:22:00.52#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.197.08:22:00.58#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.197.08:22:00.58#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.197.08:22:00.58#ibcon#enter wrdev, iclass 13, count 2 2006.197.08:22:00.58#ibcon#first serial, iclass 13, count 2 2006.197.08:22:00.58#ibcon#enter sib2, iclass 13, count 2 2006.197.08:22:00.58#ibcon#flushed, iclass 13, count 2 2006.197.08:22:00.58#ibcon#about to write, iclass 13, count 2 2006.197.08:22:00.58#ibcon#wrote, iclass 13, count 2 2006.197.08:22:00.58#ibcon#about to read 3, iclass 13, count 2 2006.197.08:22:00.60#ibcon#read 3, iclass 13, count 2 2006.197.08:22:00.60#ibcon#about to read 4, iclass 13, count 2 2006.197.08:22:00.60#ibcon#read 4, iclass 13, count 2 2006.197.08:22:00.60#ibcon#about to read 5, iclass 13, count 2 2006.197.08:22:00.60#ibcon#read 5, iclass 13, count 2 2006.197.08:22:00.60#ibcon#about to read 6, iclass 13, count 2 2006.197.08:22:00.60#ibcon#read 6, iclass 13, count 2 2006.197.08:22:00.60#ibcon#end of sib2, iclass 13, count 2 2006.197.08:22:00.60#ibcon#*mode == 0, iclass 13, count 2 2006.197.08:22:00.60#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.197.08:22:00.60#ibcon#[27=AT02-04\r\n] 2006.197.08:22:00.60#ibcon#*before write, iclass 13, count 2 2006.197.08:22:00.60#ibcon#enter sib2, iclass 13, count 2 2006.197.08:22:00.60#ibcon#flushed, iclass 13, count 2 2006.197.08:22:00.60#ibcon#about to write, iclass 13, count 2 2006.197.08:22:00.60#ibcon#wrote, iclass 13, count 2 2006.197.08:22:00.60#ibcon#about to read 3, iclass 13, count 2 2006.197.08:22:00.63#ibcon#read 3, iclass 13, count 2 2006.197.08:22:00.63#ibcon#about to read 4, iclass 13, count 2 2006.197.08:22:00.63#ibcon#read 4, iclass 13, count 2 2006.197.08:22:00.63#ibcon#about to read 5, iclass 13, count 2 2006.197.08:22:00.63#ibcon#read 5, iclass 13, count 2 2006.197.08:22:00.63#ibcon#about to read 6, iclass 13, count 2 2006.197.08:22:00.63#ibcon#read 6, iclass 13, count 2 2006.197.08:22:00.63#ibcon#end of sib2, iclass 13, count 2 2006.197.08:22:00.63#ibcon#*after write, iclass 13, count 2 2006.197.08:22:00.63#ibcon#*before return 0, iclass 13, count 2 2006.197.08:22:00.63#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.197.08:22:00.63#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.197.08:22:00.63#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.197.08:22:00.63#ibcon#ireg 7 cls_cnt 0 2006.197.08:22:00.63#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.197.08:22:00.75#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.197.08:22:00.75#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.197.08:22:00.75#ibcon#enter wrdev, iclass 13, count 0 2006.197.08:22:00.75#ibcon#first serial, iclass 13, count 0 2006.197.08:22:00.75#ibcon#enter sib2, iclass 13, count 0 2006.197.08:22:00.75#ibcon#flushed, iclass 13, count 0 2006.197.08:22:00.75#ibcon#about to write, iclass 13, count 0 2006.197.08:22:00.75#ibcon#wrote, iclass 13, count 0 2006.197.08:22:00.75#ibcon#about to read 3, iclass 13, count 0 2006.197.08:22:00.77#ibcon#read 3, iclass 13, count 0 2006.197.08:22:00.77#ibcon#about to read 4, iclass 13, count 0 2006.197.08:22:00.77#ibcon#read 4, iclass 13, count 0 2006.197.08:22:00.77#ibcon#about to read 5, iclass 13, count 0 2006.197.08:22:00.77#ibcon#read 5, iclass 13, count 0 2006.197.08:22:00.77#ibcon#about to read 6, iclass 13, count 0 2006.197.08:22:00.77#ibcon#read 6, iclass 13, count 0 2006.197.08:22:00.77#ibcon#end of sib2, iclass 13, count 0 2006.197.08:22:00.77#ibcon#*mode == 0, iclass 13, count 0 2006.197.08:22:00.77#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.197.08:22:00.77#ibcon#[27=USB\r\n] 2006.197.08:22:00.77#ibcon#*before write, iclass 13, count 0 2006.197.08:22:00.77#ibcon#enter sib2, iclass 13, count 0 2006.197.08:22:00.77#ibcon#flushed, iclass 13, count 0 2006.197.08:22:00.77#ibcon#about to write, iclass 13, count 0 2006.197.08:22:00.77#ibcon#wrote, iclass 13, count 0 2006.197.08:22:00.77#ibcon#about to read 3, iclass 13, count 0 2006.197.08:22:00.80#ibcon#read 3, iclass 13, count 0 2006.197.08:22:00.80#ibcon#about to read 4, iclass 13, count 0 2006.197.08:22:00.80#ibcon#read 4, iclass 13, count 0 2006.197.08:22:00.80#ibcon#about to read 5, iclass 13, count 0 2006.197.08:22:00.80#ibcon#read 5, iclass 13, count 0 2006.197.08:22:00.80#ibcon#about to read 6, iclass 13, count 0 2006.197.08:22:00.80#ibcon#read 6, iclass 13, count 0 2006.197.08:22:00.80#ibcon#end of sib2, iclass 13, count 0 2006.197.08:22:00.80#ibcon#*after write, iclass 13, count 0 2006.197.08:22:00.80#ibcon#*before return 0, iclass 13, count 0 2006.197.08:22:00.80#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.197.08:22:00.80#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.197.08:22:00.80#ibcon#about to clear, iclass 13 cls_cnt 0 2006.197.08:22:00.80#ibcon#cleared, iclass 13 cls_cnt 0 2006.197.08:22:00.80$vc4f8/vblo=3,656.99 2006.197.08:22:00.80#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.197.08:22:00.80#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.197.08:22:00.80#ibcon#ireg 17 cls_cnt 0 2006.197.08:22:00.80#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.197.08:22:00.80#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.197.08:22:00.80#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.197.08:22:00.80#ibcon#enter wrdev, iclass 15, count 0 2006.197.08:22:00.80#ibcon#first serial, iclass 15, count 0 2006.197.08:22:00.80#ibcon#enter sib2, iclass 15, count 0 2006.197.08:22:00.80#ibcon#flushed, iclass 15, count 0 2006.197.08:22:00.80#ibcon#about to write, iclass 15, count 0 2006.197.08:22:00.80#ibcon#wrote, iclass 15, count 0 2006.197.08:22:00.80#ibcon#about to read 3, iclass 15, count 0 2006.197.08:22:00.82#ibcon#read 3, iclass 15, count 0 2006.197.08:22:00.82#ibcon#about to read 4, iclass 15, count 0 2006.197.08:22:00.82#ibcon#read 4, iclass 15, count 0 2006.197.08:22:00.82#ibcon#about to read 5, iclass 15, count 0 2006.197.08:22:00.82#ibcon#read 5, iclass 15, count 0 2006.197.08:22:00.82#ibcon#about to read 6, iclass 15, count 0 2006.197.08:22:00.82#ibcon#read 6, iclass 15, count 0 2006.197.08:22:00.82#ibcon#end of sib2, iclass 15, count 0 2006.197.08:22:00.82#ibcon#*mode == 0, iclass 15, count 0 2006.197.08:22:00.82#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.197.08:22:00.82#ibcon#[28=FRQ=03,656.99\r\n] 2006.197.08:22:00.82#ibcon#*before write, iclass 15, count 0 2006.197.08:22:00.82#ibcon#enter sib2, iclass 15, count 0 2006.197.08:22:00.82#ibcon#flushed, iclass 15, count 0 2006.197.08:22:00.82#ibcon#about to write, iclass 15, count 0 2006.197.08:22:00.82#ibcon#wrote, iclass 15, count 0 2006.197.08:22:00.82#ibcon#about to read 3, iclass 15, count 0 2006.197.08:22:00.86#ibcon#read 3, iclass 15, count 0 2006.197.08:22:00.86#ibcon#about to read 4, iclass 15, count 0 2006.197.08:22:00.86#ibcon#read 4, iclass 15, count 0 2006.197.08:22:00.86#ibcon#about to read 5, iclass 15, count 0 2006.197.08:22:00.86#ibcon#read 5, iclass 15, count 0 2006.197.08:22:00.86#ibcon#about to read 6, iclass 15, count 0 2006.197.08:22:00.86#ibcon#read 6, iclass 15, count 0 2006.197.08:22:00.86#ibcon#end of sib2, iclass 15, count 0 2006.197.08:22:00.86#ibcon#*after write, iclass 15, count 0 2006.197.08:22:00.86#ibcon#*before return 0, iclass 15, count 0 2006.197.08:22:00.86#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.197.08:22:00.86#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.197.08:22:00.86#ibcon#about to clear, iclass 15 cls_cnt 0 2006.197.08:22:00.86#ibcon#cleared, iclass 15 cls_cnt 0 2006.197.08:22:00.86$vc4f8/vb=3,4 2006.197.08:22:00.86#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.197.08:22:00.86#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.197.08:22:00.86#ibcon#ireg 11 cls_cnt 2 2006.197.08:22:00.86#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.197.08:22:00.92#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.197.08:22:00.92#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.197.08:22:00.92#ibcon#enter wrdev, iclass 17, count 2 2006.197.08:22:00.92#ibcon#first serial, iclass 17, count 2 2006.197.08:22:00.92#ibcon#enter sib2, iclass 17, count 2 2006.197.08:22:00.92#ibcon#flushed, iclass 17, count 2 2006.197.08:22:00.92#ibcon#about to write, iclass 17, count 2 2006.197.08:22:00.92#ibcon#wrote, iclass 17, count 2 2006.197.08:22:00.92#ibcon#about to read 3, iclass 17, count 2 2006.197.08:22:00.94#ibcon#read 3, iclass 17, count 2 2006.197.08:22:00.94#ibcon#about to read 4, iclass 17, count 2 2006.197.08:22:00.94#ibcon#read 4, iclass 17, count 2 2006.197.08:22:00.94#ibcon#about to read 5, iclass 17, count 2 2006.197.08:22:00.94#ibcon#read 5, iclass 17, count 2 2006.197.08:22:00.94#ibcon#about to read 6, iclass 17, count 2 2006.197.08:22:00.94#ibcon#read 6, iclass 17, count 2 2006.197.08:22:00.94#ibcon#end of sib2, iclass 17, count 2 2006.197.08:22:00.94#ibcon#*mode == 0, iclass 17, count 2 2006.197.08:22:00.94#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.197.08:22:00.94#ibcon#[27=AT03-04\r\n] 2006.197.08:22:00.94#ibcon#*before write, iclass 17, count 2 2006.197.08:22:00.94#ibcon#enter sib2, iclass 17, count 2 2006.197.08:22:00.94#ibcon#flushed, iclass 17, count 2 2006.197.08:22:00.94#ibcon#about to write, iclass 17, count 2 2006.197.08:22:00.94#ibcon#wrote, iclass 17, count 2 2006.197.08:22:00.94#ibcon#about to read 3, iclass 17, count 2 2006.197.08:22:00.97#ibcon#read 3, iclass 17, count 2 2006.197.08:22:00.97#ibcon#about to read 4, iclass 17, count 2 2006.197.08:22:00.97#ibcon#read 4, iclass 17, count 2 2006.197.08:22:00.97#ibcon#about to read 5, iclass 17, count 2 2006.197.08:22:00.97#ibcon#read 5, iclass 17, count 2 2006.197.08:22:00.97#ibcon#about to read 6, iclass 17, count 2 2006.197.08:22:00.97#ibcon#read 6, iclass 17, count 2 2006.197.08:22:00.97#ibcon#end of sib2, iclass 17, count 2 2006.197.08:22:00.97#ibcon#*after write, iclass 17, count 2 2006.197.08:22:00.97#ibcon#*before return 0, iclass 17, count 2 2006.197.08:22:00.97#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.197.08:22:00.97#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.197.08:22:00.97#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.197.08:22:00.97#ibcon#ireg 7 cls_cnt 0 2006.197.08:22:00.97#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.197.08:22:01.09#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.197.08:22:01.09#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.197.08:22:01.09#ibcon#enter wrdev, iclass 17, count 0 2006.197.08:22:01.09#ibcon#first serial, iclass 17, count 0 2006.197.08:22:01.09#ibcon#enter sib2, iclass 17, count 0 2006.197.08:22:01.09#ibcon#flushed, iclass 17, count 0 2006.197.08:22:01.09#ibcon#about to write, iclass 17, count 0 2006.197.08:22:01.09#ibcon#wrote, iclass 17, count 0 2006.197.08:22:01.09#ibcon#about to read 3, iclass 17, count 0 2006.197.08:22:01.11#ibcon#read 3, iclass 17, count 0 2006.197.08:22:01.11#ibcon#about to read 4, iclass 17, count 0 2006.197.08:22:01.11#ibcon#read 4, iclass 17, count 0 2006.197.08:22:01.11#ibcon#about to read 5, iclass 17, count 0 2006.197.08:22:01.11#ibcon#read 5, iclass 17, count 0 2006.197.08:22:01.11#ibcon#about to read 6, iclass 17, count 0 2006.197.08:22:01.11#ibcon#read 6, iclass 17, count 0 2006.197.08:22:01.11#ibcon#end of sib2, iclass 17, count 0 2006.197.08:22:01.11#ibcon#*mode == 0, iclass 17, count 0 2006.197.08:22:01.11#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.197.08:22:01.11#ibcon#[27=USB\r\n] 2006.197.08:22:01.11#ibcon#*before write, iclass 17, count 0 2006.197.08:22:01.11#ibcon#enter sib2, iclass 17, count 0 2006.197.08:22:01.11#ibcon#flushed, iclass 17, count 0 2006.197.08:22:01.11#ibcon#about to write, iclass 17, count 0 2006.197.08:22:01.11#ibcon#wrote, iclass 17, count 0 2006.197.08:22:01.11#ibcon#about to read 3, iclass 17, count 0 2006.197.08:22:01.14#ibcon#read 3, iclass 17, count 0 2006.197.08:22:01.14#ibcon#about to read 4, iclass 17, count 0 2006.197.08:22:01.14#ibcon#read 4, iclass 17, count 0 2006.197.08:22:01.14#ibcon#about to read 5, iclass 17, count 0 2006.197.08:22:01.14#ibcon#read 5, iclass 17, count 0 2006.197.08:22:01.14#ibcon#about to read 6, iclass 17, count 0 2006.197.08:22:01.14#ibcon#read 6, iclass 17, count 0 2006.197.08:22:01.14#ibcon#end of sib2, iclass 17, count 0 2006.197.08:22:01.14#ibcon#*after write, iclass 17, count 0 2006.197.08:22:01.14#ibcon#*before return 0, iclass 17, count 0 2006.197.08:22:01.14#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.197.08:22:01.14#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.197.08:22:01.14#ibcon#about to clear, iclass 17 cls_cnt 0 2006.197.08:22:01.14#ibcon#cleared, iclass 17 cls_cnt 0 2006.197.08:22:01.14$vc4f8/vblo=4,712.99 2006.197.08:22:01.14#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.197.08:22:01.14#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.197.08:22:01.14#ibcon#ireg 17 cls_cnt 0 2006.197.08:22:01.14#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.197.08:22:01.14#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.197.08:22:01.14#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.197.08:22:01.14#ibcon#enter wrdev, iclass 19, count 0 2006.197.08:22:01.14#ibcon#first serial, iclass 19, count 0 2006.197.08:22:01.14#ibcon#enter sib2, iclass 19, count 0 2006.197.08:22:01.14#ibcon#flushed, iclass 19, count 0 2006.197.08:22:01.14#ibcon#about to write, iclass 19, count 0 2006.197.08:22:01.14#ibcon#wrote, iclass 19, count 0 2006.197.08:22:01.14#ibcon#about to read 3, iclass 19, count 0 2006.197.08:22:01.16#ibcon#read 3, iclass 19, count 0 2006.197.08:22:01.16#ibcon#about to read 4, iclass 19, count 0 2006.197.08:22:01.16#ibcon#read 4, iclass 19, count 0 2006.197.08:22:01.16#ibcon#about to read 5, iclass 19, count 0 2006.197.08:22:01.16#ibcon#read 5, iclass 19, count 0 2006.197.08:22:01.16#ibcon#about to read 6, iclass 19, count 0 2006.197.08:22:01.16#ibcon#read 6, iclass 19, count 0 2006.197.08:22:01.16#ibcon#end of sib2, iclass 19, count 0 2006.197.08:22:01.16#ibcon#*mode == 0, iclass 19, count 0 2006.197.08:22:01.16#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.197.08:22:01.16#ibcon#[28=FRQ=04,712.99\r\n] 2006.197.08:22:01.16#ibcon#*before write, iclass 19, count 0 2006.197.08:22:01.16#ibcon#enter sib2, iclass 19, count 0 2006.197.08:22:01.16#ibcon#flushed, iclass 19, count 0 2006.197.08:22:01.16#ibcon#about to write, iclass 19, count 0 2006.197.08:22:01.16#ibcon#wrote, iclass 19, count 0 2006.197.08:22:01.16#ibcon#about to read 3, iclass 19, count 0 2006.197.08:22:01.20#ibcon#read 3, iclass 19, count 0 2006.197.08:22:01.20#ibcon#about to read 4, iclass 19, count 0 2006.197.08:22:01.20#ibcon#read 4, iclass 19, count 0 2006.197.08:22:01.20#ibcon#about to read 5, iclass 19, count 0 2006.197.08:22:01.20#ibcon#read 5, iclass 19, count 0 2006.197.08:22:01.20#ibcon#about to read 6, iclass 19, count 0 2006.197.08:22:01.20#ibcon#read 6, iclass 19, count 0 2006.197.08:22:01.20#ibcon#end of sib2, iclass 19, count 0 2006.197.08:22:01.20#ibcon#*after write, iclass 19, count 0 2006.197.08:22:01.20#ibcon#*before return 0, iclass 19, count 0 2006.197.08:22:01.20#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.197.08:22:01.20#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.197.08:22:01.20#ibcon#about to clear, iclass 19 cls_cnt 0 2006.197.08:22:01.20#ibcon#cleared, iclass 19 cls_cnt 0 2006.197.08:22:01.20$vc4f8/vb=4,4 2006.197.08:22:01.20#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.197.08:22:01.20#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.197.08:22:01.20#ibcon#ireg 11 cls_cnt 2 2006.197.08:22:01.20#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.197.08:22:01.26#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.197.08:22:01.26#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.197.08:22:01.26#ibcon#enter wrdev, iclass 21, count 2 2006.197.08:22:01.26#ibcon#first serial, iclass 21, count 2 2006.197.08:22:01.26#ibcon#enter sib2, iclass 21, count 2 2006.197.08:22:01.26#ibcon#flushed, iclass 21, count 2 2006.197.08:22:01.26#ibcon#about to write, iclass 21, count 2 2006.197.08:22:01.26#ibcon#wrote, iclass 21, count 2 2006.197.08:22:01.26#ibcon#about to read 3, iclass 21, count 2 2006.197.08:22:01.28#ibcon#read 3, iclass 21, count 2 2006.197.08:22:01.28#ibcon#about to read 4, iclass 21, count 2 2006.197.08:22:01.28#ibcon#read 4, iclass 21, count 2 2006.197.08:22:01.28#ibcon#about to read 5, iclass 21, count 2 2006.197.08:22:01.28#ibcon#read 5, iclass 21, count 2 2006.197.08:22:01.28#ibcon#about to read 6, iclass 21, count 2 2006.197.08:22:01.28#ibcon#read 6, iclass 21, count 2 2006.197.08:22:01.28#ibcon#end of sib2, iclass 21, count 2 2006.197.08:22:01.28#ibcon#*mode == 0, iclass 21, count 2 2006.197.08:22:01.28#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.197.08:22:01.28#ibcon#[27=AT04-04\r\n] 2006.197.08:22:01.28#ibcon#*before write, iclass 21, count 2 2006.197.08:22:01.28#ibcon#enter sib2, iclass 21, count 2 2006.197.08:22:01.28#ibcon#flushed, iclass 21, count 2 2006.197.08:22:01.28#ibcon#about to write, iclass 21, count 2 2006.197.08:22:01.28#ibcon#wrote, iclass 21, count 2 2006.197.08:22:01.28#ibcon#about to read 3, iclass 21, count 2 2006.197.08:22:01.31#ibcon#read 3, iclass 21, count 2 2006.197.08:22:01.31#ibcon#about to read 4, iclass 21, count 2 2006.197.08:22:01.31#ibcon#read 4, iclass 21, count 2 2006.197.08:22:01.31#ibcon#about to read 5, iclass 21, count 2 2006.197.08:22:01.31#ibcon#read 5, iclass 21, count 2 2006.197.08:22:01.31#ibcon#about to read 6, iclass 21, count 2 2006.197.08:22:01.31#ibcon#read 6, iclass 21, count 2 2006.197.08:22:01.31#ibcon#end of sib2, iclass 21, count 2 2006.197.08:22:01.31#ibcon#*after write, iclass 21, count 2 2006.197.08:22:01.31#ibcon#*before return 0, iclass 21, count 2 2006.197.08:22:01.31#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.197.08:22:01.31#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.197.08:22:01.31#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.197.08:22:01.31#ibcon#ireg 7 cls_cnt 0 2006.197.08:22:01.31#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.197.08:22:01.43#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.197.08:22:01.43#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.197.08:22:01.43#ibcon#enter wrdev, iclass 21, count 0 2006.197.08:22:01.43#ibcon#first serial, iclass 21, count 0 2006.197.08:22:01.43#ibcon#enter sib2, iclass 21, count 0 2006.197.08:22:01.43#ibcon#flushed, iclass 21, count 0 2006.197.08:22:01.43#ibcon#about to write, iclass 21, count 0 2006.197.08:22:01.43#ibcon#wrote, iclass 21, count 0 2006.197.08:22:01.43#ibcon#about to read 3, iclass 21, count 0 2006.197.08:22:01.45#ibcon#read 3, iclass 21, count 0 2006.197.08:22:01.45#ibcon#about to read 4, iclass 21, count 0 2006.197.08:22:01.45#ibcon#read 4, iclass 21, count 0 2006.197.08:22:01.45#ibcon#about to read 5, iclass 21, count 0 2006.197.08:22:01.45#ibcon#read 5, iclass 21, count 0 2006.197.08:22:01.45#ibcon#about to read 6, iclass 21, count 0 2006.197.08:22:01.45#ibcon#read 6, iclass 21, count 0 2006.197.08:22:01.45#ibcon#end of sib2, iclass 21, count 0 2006.197.08:22:01.45#ibcon#*mode == 0, iclass 21, count 0 2006.197.08:22:01.45#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.197.08:22:01.45#ibcon#[27=USB\r\n] 2006.197.08:22:01.45#ibcon#*before write, iclass 21, count 0 2006.197.08:22:01.45#ibcon#enter sib2, iclass 21, count 0 2006.197.08:22:01.45#ibcon#flushed, iclass 21, count 0 2006.197.08:22:01.45#ibcon#about to write, iclass 21, count 0 2006.197.08:22:01.45#ibcon#wrote, iclass 21, count 0 2006.197.08:22:01.45#ibcon#about to read 3, iclass 21, count 0 2006.197.08:22:01.48#ibcon#read 3, iclass 21, count 0 2006.197.08:22:01.48#ibcon#about to read 4, iclass 21, count 0 2006.197.08:22:01.48#ibcon#read 4, iclass 21, count 0 2006.197.08:22:01.48#ibcon#about to read 5, iclass 21, count 0 2006.197.08:22:01.48#ibcon#read 5, iclass 21, count 0 2006.197.08:22:01.48#ibcon#about to read 6, iclass 21, count 0 2006.197.08:22:01.48#ibcon#read 6, iclass 21, count 0 2006.197.08:22:01.48#ibcon#end of sib2, iclass 21, count 0 2006.197.08:22:01.48#ibcon#*after write, iclass 21, count 0 2006.197.08:22:01.48#ibcon#*before return 0, iclass 21, count 0 2006.197.08:22:01.48#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.197.08:22:01.48#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.197.08:22:01.48#ibcon#about to clear, iclass 21 cls_cnt 0 2006.197.08:22:01.48#ibcon#cleared, iclass 21 cls_cnt 0 2006.197.08:22:01.48$vc4f8/vblo=5,744.99 2006.197.08:22:01.48#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.197.08:22:01.48#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.197.08:22:01.48#ibcon#ireg 17 cls_cnt 0 2006.197.08:22:01.48#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.197.08:22:01.48#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.197.08:22:01.48#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.197.08:22:01.48#ibcon#enter wrdev, iclass 23, count 0 2006.197.08:22:01.48#ibcon#first serial, iclass 23, count 0 2006.197.08:22:01.48#ibcon#enter sib2, iclass 23, count 0 2006.197.08:22:01.48#ibcon#flushed, iclass 23, count 0 2006.197.08:22:01.48#ibcon#about to write, iclass 23, count 0 2006.197.08:22:01.48#ibcon#wrote, iclass 23, count 0 2006.197.08:22:01.48#ibcon#about to read 3, iclass 23, count 0 2006.197.08:22:01.50#ibcon#read 3, iclass 23, count 0 2006.197.08:22:01.50#ibcon#about to read 4, iclass 23, count 0 2006.197.08:22:01.50#ibcon#read 4, iclass 23, count 0 2006.197.08:22:01.50#ibcon#about to read 5, iclass 23, count 0 2006.197.08:22:01.50#ibcon#read 5, iclass 23, count 0 2006.197.08:22:01.50#ibcon#about to read 6, iclass 23, count 0 2006.197.08:22:01.50#ibcon#read 6, iclass 23, count 0 2006.197.08:22:01.50#ibcon#end of sib2, iclass 23, count 0 2006.197.08:22:01.50#ibcon#*mode == 0, iclass 23, count 0 2006.197.08:22:01.50#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.197.08:22:01.50#ibcon#[28=FRQ=05,744.99\r\n] 2006.197.08:22:01.50#ibcon#*before write, iclass 23, count 0 2006.197.08:22:01.50#ibcon#enter sib2, iclass 23, count 0 2006.197.08:22:01.50#ibcon#flushed, iclass 23, count 0 2006.197.08:22:01.50#ibcon#about to write, iclass 23, count 0 2006.197.08:22:01.50#ibcon#wrote, iclass 23, count 0 2006.197.08:22:01.50#ibcon#about to read 3, iclass 23, count 0 2006.197.08:22:01.54#ibcon#read 3, iclass 23, count 0 2006.197.08:22:01.54#ibcon#about to read 4, iclass 23, count 0 2006.197.08:22:01.54#ibcon#read 4, iclass 23, count 0 2006.197.08:22:01.54#ibcon#about to read 5, iclass 23, count 0 2006.197.08:22:01.54#ibcon#read 5, iclass 23, count 0 2006.197.08:22:01.54#ibcon#about to read 6, iclass 23, count 0 2006.197.08:22:01.54#ibcon#read 6, iclass 23, count 0 2006.197.08:22:01.54#ibcon#end of sib2, iclass 23, count 0 2006.197.08:22:01.54#ibcon#*after write, iclass 23, count 0 2006.197.08:22:01.54#ibcon#*before return 0, iclass 23, count 0 2006.197.08:22:01.54#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.197.08:22:01.54#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.197.08:22:01.54#ibcon#about to clear, iclass 23 cls_cnt 0 2006.197.08:22:01.54#ibcon#cleared, iclass 23 cls_cnt 0 2006.197.08:22:01.54$vc4f8/vb=5,4 2006.197.08:22:01.54#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.197.08:22:01.54#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.197.08:22:01.54#ibcon#ireg 11 cls_cnt 2 2006.197.08:22:01.54#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.197.08:22:01.60#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.197.08:22:01.60#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.197.08:22:01.60#ibcon#enter wrdev, iclass 25, count 2 2006.197.08:22:01.60#ibcon#first serial, iclass 25, count 2 2006.197.08:22:01.60#ibcon#enter sib2, iclass 25, count 2 2006.197.08:22:01.60#ibcon#flushed, iclass 25, count 2 2006.197.08:22:01.60#ibcon#about to write, iclass 25, count 2 2006.197.08:22:01.60#ibcon#wrote, iclass 25, count 2 2006.197.08:22:01.60#ibcon#about to read 3, iclass 25, count 2 2006.197.08:22:01.62#ibcon#read 3, iclass 25, count 2 2006.197.08:22:01.62#ibcon#about to read 4, iclass 25, count 2 2006.197.08:22:01.62#ibcon#read 4, iclass 25, count 2 2006.197.08:22:01.62#ibcon#about to read 5, iclass 25, count 2 2006.197.08:22:01.62#ibcon#read 5, iclass 25, count 2 2006.197.08:22:01.62#ibcon#about to read 6, iclass 25, count 2 2006.197.08:22:01.62#ibcon#read 6, iclass 25, count 2 2006.197.08:22:01.62#ibcon#end of sib2, iclass 25, count 2 2006.197.08:22:01.62#ibcon#*mode == 0, iclass 25, count 2 2006.197.08:22:01.62#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.197.08:22:01.62#ibcon#[27=AT05-04\r\n] 2006.197.08:22:01.62#ibcon#*before write, iclass 25, count 2 2006.197.08:22:01.62#ibcon#enter sib2, iclass 25, count 2 2006.197.08:22:01.62#ibcon#flushed, iclass 25, count 2 2006.197.08:22:01.62#ibcon#about to write, iclass 25, count 2 2006.197.08:22:01.62#ibcon#wrote, iclass 25, count 2 2006.197.08:22:01.62#ibcon#about to read 3, iclass 25, count 2 2006.197.08:22:01.65#ibcon#read 3, iclass 25, count 2 2006.197.08:22:01.65#ibcon#about to read 4, iclass 25, count 2 2006.197.08:22:01.65#ibcon#read 4, iclass 25, count 2 2006.197.08:22:01.65#ibcon#about to read 5, iclass 25, count 2 2006.197.08:22:01.65#ibcon#read 5, iclass 25, count 2 2006.197.08:22:01.65#ibcon#about to read 6, iclass 25, count 2 2006.197.08:22:01.65#ibcon#read 6, iclass 25, count 2 2006.197.08:22:01.65#ibcon#end of sib2, iclass 25, count 2 2006.197.08:22:01.65#ibcon#*after write, iclass 25, count 2 2006.197.08:22:01.65#ibcon#*before return 0, iclass 25, count 2 2006.197.08:22:01.65#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.197.08:22:01.65#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.197.08:22:01.65#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.197.08:22:01.65#ibcon#ireg 7 cls_cnt 0 2006.197.08:22:01.65#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.197.08:22:01.77#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.197.08:22:01.77#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.197.08:22:01.77#ibcon#enter wrdev, iclass 25, count 0 2006.197.08:22:01.77#ibcon#first serial, iclass 25, count 0 2006.197.08:22:01.77#ibcon#enter sib2, iclass 25, count 0 2006.197.08:22:01.77#ibcon#flushed, iclass 25, count 0 2006.197.08:22:01.77#ibcon#about to write, iclass 25, count 0 2006.197.08:22:01.77#ibcon#wrote, iclass 25, count 0 2006.197.08:22:01.77#ibcon#about to read 3, iclass 25, count 0 2006.197.08:22:01.79#ibcon#read 3, iclass 25, count 0 2006.197.08:22:01.79#ibcon#about to read 4, iclass 25, count 0 2006.197.08:22:01.79#ibcon#read 4, iclass 25, count 0 2006.197.08:22:01.79#ibcon#about to read 5, iclass 25, count 0 2006.197.08:22:01.79#ibcon#read 5, iclass 25, count 0 2006.197.08:22:01.79#ibcon#about to read 6, iclass 25, count 0 2006.197.08:22:01.79#ibcon#read 6, iclass 25, count 0 2006.197.08:22:01.79#ibcon#end of sib2, iclass 25, count 0 2006.197.08:22:01.79#ibcon#*mode == 0, iclass 25, count 0 2006.197.08:22:01.79#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.197.08:22:01.79#ibcon#[27=USB\r\n] 2006.197.08:22:01.79#ibcon#*before write, iclass 25, count 0 2006.197.08:22:01.79#ibcon#enter sib2, iclass 25, count 0 2006.197.08:22:01.79#ibcon#flushed, iclass 25, count 0 2006.197.08:22:01.79#ibcon#about to write, iclass 25, count 0 2006.197.08:22:01.79#ibcon#wrote, iclass 25, count 0 2006.197.08:22:01.79#ibcon#about to read 3, iclass 25, count 0 2006.197.08:22:01.82#ibcon#read 3, iclass 25, count 0 2006.197.08:22:01.82#ibcon#about to read 4, iclass 25, count 0 2006.197.08:22:01.82#ibcon#read 4, iclass 25, count 0 2006.197.08:22:01.82#ibcon#about to read 5, iclass 25, count 0 2006.197.08:22:01.82#ibcon#read 5, iclass 25, count 0 2006.197.08:22:01.82#ibcon#about to read 6, iclass 25, count 0 2006.197.08:22:01.82#ibcon#read 6, iclass 25, count 0 2006.197.08:22:01.82#ibcon#end of sib2, iclass 25, count 0 2006.197.08:22:01.82#ibcon#*after write, iclass 25, count 0 2006.197.08:22:01.82#ibcon#*before return 0, iclass 25, count 0 2006.197.08:22:01.82#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.197.08:22:01.82#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.197.08:22:01.82#ibcon#about to clear, iclass 25 cls_cnt 0 2006.197.08:22:01.82#ibcon#cleared, iclass 25 cls_cnt 0 2006.197.08:22:01.82$vc4f8/vblo=6,752.99 2006.197.08:22:01.82#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.197.08:22:01.82#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.197.08:22:01.82#ibcon#ireg 17 cls_cnt 0 2006.197.08:22:01.82#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.197.08:22:01.82#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.197.08:22:01.82#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.197.08:22:01.82#ibcon#enter wrdev, iclass 27, count 0 2006.197.08:22:01.82#ibcon#first serial, iclass 27, count 0 2006.197.08:22:01.82#ibcon#enter sib2, iclass 27, count 0 2006.197.08:22:01.82#ibcon#flushed, iclass 27, count 0 2006.197.08:22:01.82#ibcon#about to write, iclass 27, count 0 2006.197.08:22:01.82#ibcon#wrote, iclass 27, count 0 2006.197.08:22:01.82#ibcon#about to read 3, iclass 27, count 0 2006.197.08:22:01.84#ibcon#read 3, iclass 27, count 0 2006.197.08:22:01.84#ibcon#about to read 4, iclass 27, count 0 2006.197.08:22:01.84#ibcon#read 4, iclass 27, count 0 2006.197.08:22:01.84#ibcon#about to read 5, iclass 27, count 0 2006.197.08:22:01.84#ibcon#read 5, iclass 27, count 0 2006.197.08:22:01.84#ibcon#about to read 6, iclass 27, count 0 2006.197.08:22:01.84#ibcon#read 6, iclass 27, count 0 2006.197.08:22:01.84#ibcon#end of sib2, iclass 27, count 0 2006.197.08:22:01.84#ibcon#*mode == 0, iclass 27, count 0 2006.197.08:22:01.84#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.197.08:22:01.84#ibcon#[28=FRQ=06,752.99\r\n] 2006.197.08:22:01.84#ibcon#*before write, iclass 27, count 0 2006.197.08:22:01.84#ibcon#enter sib2, iclass 27, count 0 2006.197.08:22:01.84#ibcon#flushed, iclass 27, count 0 2006.197.08:22:01.84#ibcon#about to write, iclass 27, count 0 2006.197.08:22:01.84#ibcon#wrote, iclass 27, count 0 2006.197.08:22:01.84#ibcon#about to read 3, iclass 27, count 0 2006.197.08:22:01.88#ibcon#read 3, iclass 27, count 0 2006.197.08:22:01.88#ibcon#about to read 4, iclass 27, count 0 2006.197.08:22:01.88#ibcon#read 4, iclass 27, count 0 2006.197.08:22:01.88#ibcon#about to read 5, iclass 27, count 0 2006.197.08:22:01.88#ibcon#read 5, iclass 27, count 0 2006.197.08:22:01.88#ibcon#about to read 6, iclass 27, count 0 2006.197.08:22:01.88#ibcon#read 6, iclass 27, count 0 2006.197.08:22:01.88#ibcon#end of sib2, iclass 27, count 0 2006.197.08:22:01.88#ibcon#*after write, iclass 27, count 0 2006.197.08:22:01.88#ibcon#*before return 0, iclass 27, count 0 2006.197.08:22:01.88#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.197.08:22:01.88#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.197.08:22:01.88#ibcon#about to clear, iclass 27 cls_cnt 0 2006.197.08:22:01.88#ibcon#cleared, iclass 27 cls_cnt 0 2006.197.08:22:01.88$vc4f8/vb=6,4 2006.197.08:22:01.88#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.197.08:22:01.88#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.197.08:22:01.88#ibcon#ireg 11 cls_cnt 2 2006.197.08:22:01.88#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.197.08:22:01.94#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.197.08:22:01.94#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.197.08:22:01.94#ibcon#enter wrdev, iclass 29, count 2 2006.197.08:22:01.94#ibcon#first serial, iclass 29, count 2 2006.197.08:22:01.94#ibcon#enter sib2, iclass 29, count 2 2006.197.08:22:01.94#ibcon#flushed, iclass 29, count 2 2006.197.08:22:01.94#ibcon#about to write, iclass 29, count 2 2006.197.08:22:01.94#ibcon#wrote, iclass 29, count 2 2006.197.08:22:01.94#ibcon#about to read 3, iclass 29, count 2 2006.197.08:22:01.96#ibcon#read 3, iclass 29, count 2 2006.197.08:22:01.96#ibcon#about to read 4, iclass 29, count 2 2006.197.08:22:01.96#ibcon#read 4, iclass 29, count 2 2006.197.08:22:01.96#ibcon#about to read 5, iclass 29, count 2 2006.197.08:22:01.96#ibcon#read 5, iclass 29, count 2 2006.197.08:22:01.96#ibcon#about to read 6, iclass 29, count 2 2006.197.08:22:01.96#ibcon#read 6, iclass 29, count 2 2006.197.08:22:01.96#ibcon#end of sib2, iclass 29, count 2 2006.197.08:22:01.96#ibcon#*mode == 0, iclass 29, count 2 2006.197.08:22:01.96#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.197.08:22:01.96#ibcon#[27=AT06-04\r\n] 2006.197.08:22:01.96#ibcon#*before write, iclass 29, count 2 2006.197.08:22:01.96#ibcon#enter sib2, iclass 29, count 2 2006.197.08:22:01.96#ibcon#flushed, iclass 29, count 2 2006.197.08:22:01.96#ibcon#about to write, iclass 29, count 2 2006.197.08:22:01.96#ibcon#wrote, iclass 29, count 2 2006.197.08:22:01.96#ibcon#about to read 3, iclass 29, count 2 2006.197.08:22:01.99#ibcon#read 3, iclass 29, count 2 2006.197.08:22:01.99#ibcon#about to read 4, iclass 29, count 2 2006.197.08:22:01.99#ibcon#read 4, iclass 29, count 2 2006.197.08:22:01.99#ibcon#about to read 5, iclass 29, count 2 2006.197.08:22:01.99#ibcon#read 5, iclass 29, count 2 2006.197.08:22:01.99#ibcon#about to read 6, iclass 29, count 2 2006.197.08:22:01.99#ibcon#read 6, iclass 29, count 2 2006.197.08:22:01.99#ibcon#end of sib2, iclass 29, count 2 2006.197.08:22:01.99#ibcon#*after write, iclass 29, count 2 2006.197.08:22:01.99#ibcon#*before return 0, iclass 29, count 2 2006.197.08:22:01.99#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.197.08:22:01.99#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.197.08:22:01.99#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.197.08:22:01.99#ibcon#ireg 7 cls_cnt 0 2006.197.08:22:01.99#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.197.08:22:02.11#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.197.08:22:02.11#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.197.08:22:02.11#ibcon#enter wrdev, iclass 29, count 0 2006.197.08:22:02.11#ibcon#first serial, iclass 29, count 0 2006.197.08:22:02.11#ibcon#enter sib2, iclass 29, count 0 2006.197.08:22:02.11#ibcon#flushed, iclass 29, count 0 2006.197.08:22:02.11#ibcon#about to write, iclass 29, count 0 2006.197.08:22:02.11#ibcon#wrote, iclass 29, count 0 2006.197.08:22:02.11#ibcon#about to read 3, iclass 29, count 0 2006.197.08:22:02.13#ibcon#read 3, iclass 29, count 0 2006.197.08:22:02.13#ibcon#about to read 4, iclass 29, count 0 2006.197.08:22:02.13#ibcon#read 4, iclass 29, count 0 2006.197.08:22:02.13#ibcon#about to read 5, iclass 29, count 0 2006.197.08:22:02.13#ibcon#read 5, iclass 29, count 0 2006.197.08:22:02.13#ibcon#about to read 6, iclass 29, count 0 2006.197.08:22:02.13#ibcon#read 6, iclass 29, count 0 2006.197.08:22:02.13#ibcon#end of sib2, iclass 29, count 0 2006.197.08:22:02.13#ibcon#*mode == 0, iclass 29, count 0 2006.197.08:22:02.13#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.197.08:22:02.13#ibcon#[27=USB\r\n] 2006.197.08:22:02.13#ibcon#*before write, iclass 29, count 0 2006.197.08:22:02.13#ibcon#enter sib2, iclass 29, count 0 2006.197.08:22:02.13#ibcon#flushed, iclass 29, count 0 2006.197.08:22:02.13#ibcon#about to write, iclass 29, count 0 2006.197.08:22:02.13#ibcon#wrote, iclass 29, count 0 2006.197.08:22:02.13#ibcon#about to read 3, iclass 29, count 0 2006.197.08:22:02.16#ibcon#read 3, iclass 29, count 0 2006.197.08:22:02.16#ibcon#about to read 4, iclass 29, count 0 2006.197.08:22:02.16#ibcon#read 4, iclass 29, count 0 2006.197.08:22:02.16#ibcon#about to read 5, iclass 29, count 0 2006.197.08:22:02.16#ibcon#read 5, iclass 29, count 0 2006.197.08:22:02.16#ibcon#about to read 6, iclass 29, count 0 2006.197.08:22:02.16#ibcon#read 6, iclass 29, count 0 2006.197.08:22:02.16#ibcon#end of sib2, iclass 29, count 0 2006.197.08:22:02.16#ibcon#*after write, iclass 29, count 0 2006.197.08:22:02.16#ibcon#*before return 0, iclass 29, count 0 2006.197.08:22:02.16#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.197.08:22:02.16#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.197.08:22:02.16#ibcon#about to clear, iclass 29 cls_cnt 0 2006.197.08:22:02.16#ibcon#cleared, iclass 29 cls_cnt 0 2006.197.08:22:02.16$vc4f8/vabw=wide 2006.197.08:22:02.16#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.197.08:22:02.16#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.197.08:22:02.16#ibcon#ireg 8 cls_cnt 0 2006.197.08:22:02.16#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.197.08:22:02.16#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.197.08:22:02.16#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.197.08:22:02.16#ibcon#enter wrdev, iclass 31, count 0 2006.197.08:22:02.16#ibcon#first serial, iclass 31, count 0 2006.197.08:22:02.16#ibcon#enter sib2, iclass 31, count 0 2006.197.08:22:02.16#ibcon#flushed, iclass 31, count 0 2006.197.08:22:02.16#ibcon#about to write, iclass 31, count 0 2006.197.08:22:02.16#ibcon#wrote, iclass 31, count 0 2006.197.08:22:02.16#ibcon#about to read 3, iclass 31, count 0 2006.197.08:22:02.18#ibcon#read 3, iclass 31, count 0 2006.197.08:22:02.18#ibcon#about to read 4, iclass 31, count 0 2006.197.08:22:02.18#ibcon#read 4, iclass 31, count 0 2006.197.08:22:02.18#ibcon#about to read 5, iclass 31, count 0 2006.197.08:22:02.18#ibcon#read 5, iclass 31, count 0 2006.197.08:22:02.18#ibcon#about to read 6, iclass 31, count 0 2006.197.08:22:02.18#ibcon#read 6, iclass 31, count 0 2006.197.08:22:02.18#ibcon#end of sib2, iclass 31, count 0 2006.197.08:22:02.18#ibcon#*mode == 0, iclass 31, count 0 2006.197.08:22:02.18#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.197.08:22:02.18#ibcon#[25=BW32\r\n] 2006.197.08:22:02.18#ibcon#*before write, iclass 31, count 0 2006.197.08:22:02.18#ibcon#enter sib2, iclass 31, count 0 2006.197.08:22:02.18#ibcon#flushed, iclass 31, count 0 2006.197.08:22:02.18#ibcon#about to write, iclass 31, count 0 2006.197.08:22:02.18#ibcon#wrote, iclass 31, count 0 2006.197.08:22:02.18#ibcon#about to read 3, iclass 31, count 0 2006.197.08:22:02.21#ibcon#read 3, iclass 31, count 0 2006.197.08:22:02.21#ibcon#about to read 4, iclass 31, count 0 2006.197.08:22:02.21#ibcon#read 4, iclass 31, count 0 2006.197.08:22:02.21#ibcon#about to read 5, iclass 31, count 0 2006.197.08:22:02.21#ibcon#read 5, iclass 31, count 0 2006.197.08:22:02.21#ibcon#about to read 6, iclass 31, count 0 2006.197.08:22:02.21#ibcon#read 6, iclass 31, count 0 2006.197.08:22:02.21#ibcon#end of sib2, iclass 31, count 0 2006.197.08:22:02.21#ibcon#*after write, iclass 31, count 0 2006.197.08:22:02.21#ibcon#*before return 0, iclass 31, count 0 2006.197.08:22:02.21#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.197.08:22:02.21#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.197.08:22:02.21#ibcon#about to clear, iclass 31 cls_cnt 0 2006.197.08:22:02.21#ibcon#cleared, iclass 31 cls_cnt 0 2006.197.08:22:02.21$vc4f8/vbbw=wide 2006.197.08:22:02.21#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.197.08:22:02.21#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.197.08:22:02.21#ibcon#ireg 8 cls_cnt 0 2006.197.08:22:02.21#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.197.08:22:02.28#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.197.08:22:02.28#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.197.08:22:02.28#ibcon#enter wrdev, iclass 33, count 0 2006.197.08:22:02.28#ibcon#first serial, iclass 33, count 0 2006.197.08:22:02.28#ibcon#enter sib2, iclass 33, count 0 2006.197.08:22:02.28#ibcon#flushed, iclass 33, count 0 2006.197.08:22:02.28#ibcon#about to write, iclass 33, count 0 2006.197.08:22:02.28#ibcon#wrote, iclass 33, count 0 2006.197.08:22:02.28#ibcon#about to read 3, iclass 33, count 0 2006.197.08:22:02.30#ibcon#read 3, iclass 33, count 0 2006.197.08:22:02.30#ibcon#about to read 4, iclass 33, count 0 2006.197.08:22:02.30#ibcon#read 4, iclass 33, count 0 2006.197.08:22:02.30#ibcon#about to read 5, iclass 33, count 0 2006.197.08:22:02.30#ibcon#read 5, iclass 33, count 0 2006.197.08:22:02.30#ibcon#about to read 6, iclass 33, count 0 2006.197.08:22:02.30#ibcon#read 6, iclass 33, count 0 2006.197.08:22:02.30#ibcon#end of sib2, iclass 33, count 0 2006.197.08:22:02.30#ibcon#*mode == 0, iclass 33, count 0 2006.197.08:22:02.30#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.197.08:22:02.30#ibcon#[27=BW32\r\n] 2006.197.08:22:02.30#ibcon#*before write, iclass 33, count 0 2006.197.08:22:02.30#ibcon#enter sib2, iclass 33, count 0 2006.197.08:22:02.30#ibcon#flushed, iclass 33, count 0 2006.197.08:22:02.30#ibcon#about to write, iclass 33, count 0 2006.197.08:22:02.30#ibcon#wrote, iclass 33, count 0 2006.197.08:22:02.30#ibcon#about to read 3, iclass 33, count 0 2006.197.08:22:02.33#ibcon#read 3, iclass 33, count 0 2006.197.08:22:02.33#ibcon#about to read 4, iclass 33, count 0 2006.197.08:22:02.33#ibcon#read 4, iclass 33, count 0 2006.197.08:22:02.33#ibcon#about to read 5, iclass 33, count 0 2006.197.08:22:02.33#ibcon#read 5, iclass 33, count 0 2006.197.08:22:02.33#ibcon#about to read 6, iclass 33, count 0 2006.197.08:22:02.33#ibcon#read 6, iclass 33, count 0 2006.197.08:22:02.33#ibcon#end of sib2, iclass 33, count 0 2006.197.08:22:02.33#ibcon#*after write, iclass 33, count 0 2006.197.08:22:02.33#ibcon#*before return 0, iclass 33, count 0 2006.197.08:22:02.33#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.197.08:22:02.33#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.197.08:22:02.33#ibcon#about to clear, iclass 33 cls_cnt 0 2006.197.08:22:02.33#ibcon#cleared, iclass 33 cls_cnt 0 2006.197.08:22:02.33$4f8m12a/ifd4f 2006.197.08:22:02.33$ifd4f/lo= 2006.197.08:22:02.33$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.197.08:22:02.33$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.197.08:22:02.33$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.197.08:22:02.33$ifd4f/patch= 2006.197.08:22:02.33$ifd4f/patch=lo1,a1,a2,a3,a4 2006.197.08:22:02.33$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.197.08:22:02.33$ifd4f/patch=lo3,a5,a6,a7,a8 2006.197.08:22:02.33$4f8m12a/"form=m,16.000,1:2 2006.197.08:22:02.33$4f8m12a/"tpicd 2006.197.08:22:02.33$4f8m12a/echo=off 2006.197.08:22:02.33$4f8m12a/xlog=off 2006.197.08:22:02.33:!2006.197.08:24:10 2006.197.08:22:22.14#trakl#Source acquired 2006.197.08:22:24.14#flagr#flagr/antenna,acquired 2006.197.08:24:10.00:preob 2006.197.08:24:10.14/onsource/TRACKING 2006.197.08:24:10.14:!2006.197.08:24:20 2006.197.08:24:20.00:data_valid=on 2006.197.08:24:20.00:midob 2006.197.08:24:21.14/onsource/TRACKING 2006.197.08:24:21.14/wx/25.52,1002.9,96 2006.197.08:24:21.22/cable/+6.3726E-03 2006.197.08:24:22.31/va/01,08,usb,yes,31,33 2006.197.08:24:22.31/va/02,07,usb,yes,32,33 2006.197.08:24:22.31/va/03,06,usb,yes,34,34 2006.197.08:24:22.31/va/04,07,usb,yes,33,35 2006.197.08:24:22.31/va/05,07,usb,yes,37,39 2006.197.08:24:22.31/va/06,06,usb,yes,37,36 2006.197.08:24:22.31/va/07,06,usb,yes,37,37 2006.197.08:24:22.31/va/08,07,usb,yes,35,35 2006.197.08:24:22.54/valo/01,532.99,yes,locked 2006.197.08:24:22.54/valo/02,572.99,yes,locked 2006.197.08:24:22.54/valo/03,672.99,yes,locked 2006.197.08:24:22.54/valo/04,832.99,yes,locked 2006.197.08:24:22.54/valo/05,652.99,yes,locked 2006.197.08:24:22.54/valo/06,772.99,yes,locked 2006.197.08:24:22.54/valo/07,832.99,yes,locked 2006.197.08:24:22.54/valo/08,852.99,yes,locked 2006.197.08:24:23.63/vb/01,04,usb,yes,30,29 2006.197.08:24:23.63/vb/02,04,usb,yes,32,34 2006.197.08:24:23.63/vb/03,04,usb,yes,28,32 2006.197.08:24:23.63/vb/04,04,usb,yes,30,30 2006.197.08:24:23.63/vb/05,04,usb,yes,28,32 2006.197.08:24:23.63/vb/06,04,usb,yes,29,32 2006.197.08:24:23.63/vb/07,04,usb,yes,31,31 2006.197.08:24:23.63/vb/08,04,usb,yes,29,32 2006.197.08:24:23.86/vblo/01,632.99,yes,locked 2006.197.08:24:23.86/vblo/02,640.99,yes,locked 2006.197.08:24:23.86/vblo/03,656.99,yes,locked 2006.197.08:24:23.86/vblo/04,712.99,yes,locked 2006.197.08:24:23.86/vblo/05,744.99,yes,locked 2006.197.08:24:23.86/vblo/06,752.99,yes,locked 2006.197.08:24:23.86/vblo/07,734.99,yes,locked 2006.197.08:24:23.86/vblo/08,744.99,yes,locked 2006.197.08:24:24.01/vabw/8 2006.197.08:24:24.16/vbbw/8 2006.197.08:24:24.25/xfe/off,on,15.2 2006.197.08:24:24.64/ifatt/23,28,28,28 2006.197.08:24:25.09/fmout-gps/S +3.00E-07 2006.197.08:24:25.13:!2006.197.08:25:20 2006.197.08:25:20.00:data_valid=off 2006.197.08:25:20.00:postob 2006.197.08:25:20.18/cable/+6.3695E-03 2006.197.08:25:20.18/wx/25.51,1002.9,96 2006.197.08:25:21.10/fmout-gps/S +3.00E-07 2006.197.08:25:21.10:scan_name=197-0826,k06197,60 2006.197.08:25:21.10:source=0823+033,082550.34,030924.5,2000.0,ccw 2006.197.08:25:21.14#flagr#flagr/antenna,new-source 2006.197.08:25:22.14:checkk5 2006.197.08:25:22.48/chk_autoobs//k5ts1/ autoobs is running! 2006.197.08:25:22.82/chk_autoobs//k5ts2/ autoobs is running! 2006.197.08:25:23.16/chk_autoobs//k5ts3/ autoobs is running! 2006.197.08:25:23.50/chk_autoobs//k5ts4/ autoobs is running! 2006.197.08:25:23.84/chk_obsdata//k5ts1/T1970824??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.197.08:25:24.18/chk_obsdata//k5ts2/T1970824??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.197.08:25:24.52/chk_obsdata//k5ts3/T1970824??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.197.08:25:24.85/chk_obsdata//k5ts4/T1970824??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.197.08:25:25.50/k5log//k5ts1_log_newline 2006.197.08:25:26.16/k5log//k5ts2_log_newline 2006.197.08:25:26.81/k5log//k5ts3_log_newline 2006.197.08:25:27.47/k5log//k5ts4_log_newline 2006.197.08:25:27.49/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.197.08:25:27.49:4f8m12a=3 2006.197.08:25:27.49$4f8m12a/echo=on 2006.197.08:25:27.49$4f8m12a/pcalon 2006.197.08:25:27.49$pcalon/"no phase cal control is implemented here 2006.197.08:25:27.49$4f8m12a/"tpicd=stop 2006.197.08:25:27.49$4f8m12a/vc4f8 2006.197.08:25:27.49$vc4f8/valo=1,532.99 2006.197.08:25:27.50#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.197.08:25:27.50#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.197.08:25:27.50#ibcon#ireg 17 cls_cnt 0 2006.197.08:25:27.50#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.197.08:25:27.50#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.197.08:25:27.50#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.197.08:25:27.50#ibcon#enter wrdev, iclass 12, count 0 2006.197.08:25:27.50#ibcon#first serial, iclass 12, count 0 2006.197.08:25:27.50#ibcon#enter sib2, iclass 12, count 0 2006.197.08:25:27.50#ibcon#flushed, iclass 12, count 0 2006.197.08:25:27.50#ibcon#about to write, iclass 12, count 0 2006.197.08:25:27.50#ibcon#wrote, iclass 12, count 0 2006.197.08:25:27.50#ibcon#about to read 3, iclass 12, count 0 2006.197.08:25:27.52#ibcon#read 3, iclass 12, count 0 2006.197.08:25:27.52#ibcon#about to read 4, iclass 12, count 0 2006.197.08:25:27.52#ibcon#read 4, iclass 12, count 0 2006.197.08:25:27.52#ibcon#about to read 5, iclass 12, count 0 2006.197.08:25:27.52#ibcon#read 5, iclass 12, count 0 2006.197.08:25:27.52#ibcon#about to read 6, iclass 12, count 0 2006.197.08:25:27.52#ibcon#read 6, iclass 12, count 0 2006.197.08:25:27.52#ibcon#end of sib2, iclass 12, count 0 2006.197.08:25:27.52#ibcon#*mode == 0, iclass 12, count 0 2006.197.08:25:27.52#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.197.08:25:27.52#ibcon#[26=FRQ=01,532.99\r\n] 2006.197.08:25:27.52#ibcon#*before write, iclass 12, count 0 2006.197.08:25:27.52#ibcon#enter sib2, iclass 12, count 0 2006.197.08:25:27.52#ibcon#flushed, iclass 12, count 0 2006.197.08:25:27.52#ibcon#about to write, iclass 12, count 0 2006.197.08:25:27.52#ibcon#wrote, iclass 12, count 0 2006.197.08:25:27.52#ibcon#about to read 3, iclass 12, count 0 2006.197.08:25:27.57#ibcon#read 3, iclass 12, count 0 2006.197.08:25:27.57#ibcon#about to read 4, iclass 12, count 0 2006.197.08:25:27.57#ibcon#read 4, iclass 12, count 0 2006.197.08:25:27.57#ibcon#about to read 5, iclass 12, count 0 2006.197.08:25:27.57#ibcon#read 5, iclass 12, count 0 2006.197.08:25:27.57#ibcon#about to read 6, iclass 12, count 0 2006.197.08:25:27.57#ibcon#read 6, iclass 12, count 0 2006.197.08:25:27.57#ibcon#end of sib2, iclass 12, count 0 2006.197.08:25:27.57#ibcon#*after write, iclass 12, count 0 2006.197.08:25:27.57#ibcon#*before return 0, iclass 12, count 0 2006.197.08:25:27.57#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.197.08:25:27.57#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.197.08:25:27.57#ibcon#about to clear, iclass 12 cls_cnt 0 2006.197.08:25:27.57#ibcon#cleared, iclass 12 cls_cnt 0 2006.197.08:25:27.57$vc4f8/va=1,8 2006.197.08:25:27.57#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.197.08:25:27.57#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.197.08:25:27.57#ibcon#ireg 11 cls_cnt 2 2006.197.08:25:27.57#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.197.08:25:27.57#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.197.08:25:27.57#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.197.08:25:27.57#ibcon#enter wrdev, iclass 14, count 2 2006.197.08:25:27.57#ibcon#first serial, iclass 14, count 2 2006.197.08:25:27.57#ibcon#enter sib2, iclass 14, count 2 2006.197.08:25:27.57#ibcon#flushed, iclass 14, count 2 2006.197.08:25:27.57#ibcon#about to write, iclass 14, count 2 2006.197.08:25:27.57#ibcon#wrote, iclass 14, count 2 2006.197.08:25:27.57#ibcon#about to read 3, iclass 14, count 2 2006.197.08:25:27.59#ibcon#read 3, iclass 14, count 2 2006.197.08:25:27.59#ibcon#about to read 4, iclass 14, count 2 2006.197.08:25:27.59#ibcon#read 4, iclass 14, count 2 2006.197.08:25:27.59#ibcon#about to read 5, iclass 14, count 2 2006.197.08:25:27.59#ibcon#read 5, iclass 14, count 2 2006.197.08:25:27.59#ibcon#about to read 6, iclass 14, count 2 2006.197.08:25:27.59#ibcon#read 6, iclass 14, count 2 2006.197.08:25:27.59#ibcon#end of sib2, iclass 14, count 2 2006.197.08:25:27.59#ibcon#*mode == 0, iclass 14, count 2 2006.197.08:25:27.59#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.197.08:25:27.59#ibcon#[25=AT01-08\r\n] 2006.197.08:25:27.59#ibcon#*before write, iclass 14, count 2 2006.197.08:25:27.59#ibcon#enter sib2, iclass 14, count 2 2006.197.08:25:27.59#ibcon#flushed, iclass 14, count 2 2006.197.08:25:27.59#ibcon#about to write, iclass 14, count 2 2006.197.08:25:27.59#ibcon#wrote, iclass 14, count 2 2006.197.08:25:27.59#ibcon#about to read 3, iclass 14, count 2 2006.197.08:25:27.62#ibcon#read 3, iclass 14, count 2 2006.197.08:25:27.62#ibcon#about to read 4, iclass 14, count 2 2006.197.08:25:27.62#ibcon#read 4, iclass 14, count 2 2006.197.08:25:27.62#ibcon#about to read 5, iclass 14, count 2 2006.197.08:25:27.62#ibcon#read 5, iclass 14, count 2 2006.197.08:25:27.62#ibcon#about to read 6, iclass 14, count 2 2006.197.08:25:27.62#ibcon#read 6, iclass 14, count 2 2006.197.08:25:27.62#ibcon#end of sib2, iclass 14, count 2 2006.197.08:25:27.62#ibcon#*after write, iclass 14, count 2 2006.197.08:25:27.62#ibcon#*before return 0, iclass 14, count 2 2006.197.08:25:27.62#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.197.08:25:27.62#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.197.08:25:27.62#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.197.08:25:27.62#ibcon#ireg 7 cls_cnt 0 2006.197.08:25:27.62#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.197.08:25:27.74#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.197.08:25:27.74#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.197.08:25:27.74#ibcon#enter wrdev, iclass 14, count 0 2006.197.08:25:27.74#ibcon#first serial, iclass 14, count 0 2006.197.08:25:27.74#ibcon#enter sib2, iclass 14, count 0 2006.197.08:25:27.74#ibcon#flushed, iclass 14, count 0 2006.197.08:25:27.74#ibcon#about to write, iclass 14, count 0 2006.197.08:25:27.74#ibcon#wrote, iclass 14, count 0 2006.197.08:25:27.74#ibcon#about to read 3, iclass 14, count 0 2006.197.08:25:27.76#ibcon#read 3, iclass 14, count 0 2006.197.08:25:27.76#ibcon#about to read 4, iclass 14, count 0 2006.197.08:25:27.76#ibcon#read 4, iclass 14, count 0 2006.197.08:25:27.76#ibcon#about to read 5, iclass 14, count 0 2006.197.08:25:27.76#ibcon#read 5, iclass 14, count 0 2006.197.08:25:27.76#ibcon#about to read 6, iclass 14, count 0 2006.197.08:25:27.76#ibcon#read 6, iclass 14, count 0 2006.197.08:25:27.76#ibcon#end of sib2, iclass 14, count 0 2006.197.08:25:27.76#ibcon#*mode == 0, iclass 14, count 0 2006.197.08:25:27.76#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.197.08:25:27.76#ibcon#[25=USB\r\n] 2006.197.08:25:27.76#ibcon#*before write, iclass 14, count 0 2006.197.08:25:27.76#ibcon#enter sib2, iclass 14, count 0 2006.197.08:25:27.76#ibcon#flushed, iclass 14, count 0 2006.197.08:25:27.76#ibcon#about to write, iclass 14, count 0 2006.197.08:25:27.76#ibcon#wrote, iclass 14, count 0 2006.197.08:25:27.76#ibcon#about to read 3, iclass 14, count 0 2006.197.08:25:27.79#ibcon#read 3, iclass 14, count 0 2006.197.08:25:27.79#ibcon#about to read 4, iclass 14, count 0 2006.197.08:25:27.79#ibcon#read 4, iclass 14, count 0 2006.197.08:25:27.79#ibcon#about to read 5, iclass 14, count 0 2006.197.08:25:27.79#ibcon#read 5, iclass 14, count 0 2006.197.08:25:27.79#ibcon#about to read 6, iclass 14, count 0 2006.197.08:25:27.79#ibcon#read 6, iclass 14, count 0 2006.197.08:25:27.79#ibcon#end of sib2, iclass 14, count 0 2006.197.08:25:27.79#ibcon#*after write, iclass 14, count 0 2006.197.08:25:27.79#ibcon#*before return 0, iclass 14, count 0 2006.197.08:25:27.79#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.197.08:25:27.79#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.197.08:25:27.79#ibcon#about to clear, iclass 14 cls_cnt 0 2006.197.08:25:27.79#ibcon#cleared, iclass 14 cls_cnt 0 2006.197.08:25:27.79$vc4f8/valo=2,572.99 2006.197.08:25:27.79#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.197.08:25:27.79#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.197.08:25:27.79#ibcon#ireg 17 cls_cnt 0 2006.197.08:25:27.79#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.197.08:25:27.79#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.197.08:25:27.79#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.197.08:25:27.79#ibcon#enter wrdev, iclass 16, count 0 2006.197.08:25:27.79#ibcon#first serial, iclass 16, count 0 2006.197.08:25:27.79#ibcon#enter sib2, iclass 16, count 0 2006.197.08:25:27.79#ibcon#flushed, iclass 16, count 0 2006.197.08:25:27.79#ibcon#about to write, iclass 16, count 0 2006.197.08:25:27.79#ibcon#wrote, iclass 16, count 0 2006.197.08:25:27.79#ibcon#about to read 3, iclass 16, count 0 2006.197.08:25:27.81#ibcon#read 3, iclass 16, count 0 2006.197.08:25:27.81#ibcon#about to read 4, iclass 16, count 0 2006.197.08:25:27.81#ibcon#read 4, iclass 16, count 0 2006.197.08:25:27.81#ibcon#about to read 5, iclass 16, count 0 2006.197.08:25:27.81#ibcon#read 5, iclass 16, count 0 2006.197.08:25:27.81#ibcon#about to read 6, iclass 16, count 0 2006.197.08:25:27.81#ibcon#read 6, iclass 16, count 0 2006.197.08:25:27.81#ibcon#end of sib2, iclass 16, count 0 2006.197.08:25:27.81#ibcon#*mode == 0, iclass 16, count 0 2006.197.08:25:27.81#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.197.08:25:27.81#ibcon#[26=FRQ=02,572.99\r\n] 2006.197.08:25:27.81#ibcon#*before write, iclass 16, count 0 2006.197.08:25:27.81#ibcon#enter sib2, iclass 16, count 0 2006.197.08:25:27.81#ibcon#flushed, iclass 16, count 0 2006.197.08:25:27.81#ibcon#about to write, iclass 16, count 0 2006.197.08:25:27.81#ibcon#wrote, iclass 16, count 0 2006.197.08:25:27.81#ibcon#about to read 3, iclass 16, count 0 2006.197.08:25:27.85#ibcon#read 3, iclass 16, count 0 2006.197.08:25:27.85#ibcon#about to read 4, iclass 16, count 0 2006.197.08:25:27.85#ibcon#read 4, iclass 16, count 0 2006.197.08:25:27.85#ibcon#about to read 5, iclass 16, count 0 2006.197.08:25:27.85#ibcon#read 5, iclass 16, count 0 2006.197.08:25:27.85#ibcon#about to read 6, iclass 16, count 0 2006.197.08:25:27.85#ibcon#read 6, iclass 16, count 0 2006.197.08:25:27.85#ibcon#end of sib2, iclass 16, count 0 2006.197.08:25:27.85#ibcon#*after write, iclass 16, count 0 2006.197.08:25:27.85#ibcon#*before return 0, iclass 16, count 0 2006.197.08:25:27.85#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.197.08:25:27.85#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.197.08:25:27.85#ibcon#about to clear, iclass 16 cls_cnt 0 2006.197.08:25:27.85#ibcon#cleared, iclass 16 cls_cnt 0 2006.197.08:25:27.85$vc4f8/va=2,7 2006.197.08:25:27.85#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.197.08:25:27.85#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.197.08:25:27.85#ibcon#ireg 11 cls_cnt 2 2006.197.08:25:27.85#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.197.08:25:27.91#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.197.08:25:27.91#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.197.08:25:27.91#ibcon#enter wrdev, iclass 18, count 2 2006.197.08:25:27.91#ibcon#first serial, iclass 18, count 2 2006.197.08:25:27.91#ibcon#enter sib2, iclass 18, count 2 2006.197.08:25:27.91#ibcon#flushed, iclass 18, count 2 2006.197.08:25:27.91#ibcon#about to write, iclass 18, count 2 2006.197.08:25:27.91#ibcon#wrote, iclass 18, count 2 2006.197.08:25:27.91#ibcon#about to read 3, iclass 18, count 2 2006.197.08:25:27.93#ibcon#read 3, iclass 18, count 2 2006.197.08:25:27.93#ibcon#about to read 4, iclass 18, count 2 2006.197.08:25:27.93#ibcon#read 4, iclass 18, count 2 2006.197.08:25:27.93#ibcon#about to read 5, iclass 18, count 2 2006.197.08:25:27.93#ibcon#read 5, iclass 18, count 2 2006.197.08:25:27.93#ibcon#about to read 6, iclass 18, count 2 2006.197.08:25:27.93#ibcon#read 6, iclass 18, count 2 2006.197.08:25:27.93#ibcon#end of sib2, iclass 18, count 2 2006.197.08:25:27.93#ibcon#*mode == 0, iclass 18, count 2 2006.197.08:25:27.93#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.197.08:25:27.93#ibcon#[25=AT02-07\r\n] 2006.197.08:25:27.93#ibcon#*before write, iclass 18, count 2 2006.197.08:25:27.93#ibcon#enter sib2, iclass 18, count 2 2006.197.08:25:27.93#ibcon#flushed, iclass 18, count 2 2006.197.08:25:27.93#ibcon#about to write, iclass 18, count 2 2006.197.08:25:27.93#ibcon#wrote, iclass 18, count 2 2006.197.08:25:27.93#ibcon#about to read 3, iclass 18, count 2 2006.197.08:25:27.96#ibcon#read 3, iclass 18, count 2 2006.197.08:25:27.96#ibcon#about to read 4, iclass 18, count 2 2006.197.08:25:27.96#ibcon#read 4, iclass 18, count 2 2006.197.08:25:27.96#ibcon#about to read 5, iclass 18, count 2 2006.197.08:25:27.96#ibcon#read 5, iclass 18, count 2 2006.197.08:25:27.96#ibcon#about to read 6, iclass 18, count 2 2006.197.08:25:27.96#ibcon#read 6, iclass 18, count 2 2006.197.08:25:27.96#ibcon#end of sib2, iclass 18, count 2 2006.197.08:25:27.96#ibcon#*after write, iclass 18, count 2 2006.197.08:25:27.96#ibcon#*before return 0, iclass 18, count 2 2006.197.08:25:27.96#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.197.08:25:27.96#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.197.08:25:27.96#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.197.08:25:27.96#ibcon#ireg 7 cls_cnt 0 2006.197.08:25:27.96#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.197.08:25:28.08#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.197.08:25:28.08#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.197.08:25:28.08#ibcon#enter wrdev, iclass 18, count 0 2006.197.08:25:28.08#ibcon#first serial, iclass 18, count 0 2006.197.08:25:28.08#ibcon#enter sib2, iclass 18, count 0 2006.197.08:25:28.08#ibcon#flushed, iclass 18, count 0 2006.197.08:25:28.08#ibcon#about to write, iclass 18, count 0 2006.197.08:25:28.08#ibcon#wrote, iclass 18, count 0 2006.197.08:25:28.08#ibcon#about to read 3, iclass 18, count 0 2006.197.08:25:28.10#ibcon#read 3, iclass 18, count 0 2006.197.08:25:28.10#ibcon#about to read 4, iclass 18, count 0 2006.197.08:25:28.10#ibcon#read 4, iclass 18, count 0 2006.197.08:25:28.10#ibcon#about to read 5, iclass 18, count 0 2006.197.08:25:28.10#ibcon#read 5, iclass 18, count 0 2006.197.08:25:28.10#ibcon#about to read 6, iclass 18, count 0 2006.197.08:25:28.10#ibcon#read 6, iclass 18, count 0 2006.197.08:25:28.10#ibcon#end of sib2, iclass 18, count 0 2006.197.08:25:28.10#ibcon#*mode == 0, iclass 18, count 0 2006.197.08:25:28.10#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.197.08:25:28.10#ibcon#[25=USB\r\n] 2006.197.08:25:28.10#ibcon#*before write, iclass 18, count 0 2006.197.08:25:28.10#ibcon#enter sib2, iclass 18, count 0 2006.197.08:25:28.10#ibcon#flushed, iclass 18, count 0 2006.197.08:25:28.10#ibcon#about to write, iclass 18, count 0 2006.197.08:25:28.10#ibcon#wrote, iclass 18, count 0 2006.197.08:25:28.10#ibcon#about to read 3, iclass 18, count 0 2006.197.08:25:28.13#ibcon#read 3, iclass 18, count 0 2006.197.08:25:28.13#ibcon#about to read 4, iclass 18, count 0 2006.197.08:25:28.13#ibcon#read 4, iclass 18, count 0 2006.197.08:25:28.13#ibcon#about to read 5, iclass 18, count 0 2006.197.08:25:28.13#ibcon#read 5, iclass 18, count 0 2006.197.08:25:28.13#ibcon#about to read 6, iclass 18, count 0 2006.197.08:25:28.13#ibcon#read 6, iclass 18, count 0 2006.197.08:25:28.13#ibcon#end of sib2, iclass 18, count 0 2006.197.08:25:28.13#ibcon#*after write, iclass 18, count 0 2006.197.08:25:28.13#ibcon#*before return 0, iclass 18, count 0 2006.197.08:25:28.13#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.197.08:25:28.13#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.197.08:25:28.13#ibcon#about to clear, iclass 18 cls_cnt 0 2006.197.08:25:28.13#ibcon#cleared, iclass 18 cls_cnt 0 2006.197.08:25:28.13$vc4f8/valo=3,672.99 2006.197.08:25:28.13#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.197.08:25:28.13#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.197.08:25:28.13#ibcon#ireg 17 cls_cnt 0 2006.197.08:25:28.13#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.197.08:25:28.13#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.197.08:25:28.13#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.197.08:25:28.13#ibcon#enter wrdev, iclass 20, count 0 2006.197.08:25:28.13#ibcon#first serial, iclass 20, count 0 2006.197.08:25:28.13#ibcon#enter sib2, iclass 20, count 0 2006.197.08:25:28.13#ibcon#flushed, iclass 20, count 0 2006.197.08:25:28.13#ibcon#about to write, iclass 20, count 0 2006.197.08:25:28.13#ibcon#wrote, iclass 20, count 0 2006.197.08:25:28.13#ibcon#about to read 3, iclass 20, count 0 2006.197.08:25:28.15#ibcon#read 3, iclass 20, count 0 2006.197.08:25:28.15#ibcon#about to read 4, iclass 20, count 0 2006.197.08:25:28.15#ibcon#read 4, iclass 20, count 0 2006.197.08:25:28.15#ibcon#about to read 5, iclass 20, count 0 2006.197.08:25:28.15#ibcon#read 5, iclass 20, count 0 2006.197.08:25:28.15#ibcon#about to read 6, iclass 20, count 0 2006.197.08:25:28.15#ibcon#read 6, iclass 20, count 0 2006.197.08:25:28.15#ibcon#end of sib2, iclass 20, count 0 2006.197.08:25:28.15#ibcon#*mode == 0, iclass 20, count 0 2006.197.08:25:28.15#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.197.08:25:28.15#ibcon#[26=FRQ=03,672.99\r\n] 2006.197.08:25:28.15#ibcon#*before write, iclass 20, count 0 2006.197.08:25:28.15#ibcon#enter sib2, iclass 20, count 0 2006.197.08:25:28.15#ibcon#flushed, iclass 20, count 0 2006.197.08:25:28.15#ibcon#about to write, iclass 20, count 0 2006.197.08:25:28.15#ibcon#wrote, iclass 20, count 0 2006.197.08:25:28.15#ibcon#about to read 3, iclass 20, count 0 2006.197.08:25:28.19#ibcon#read 3, iclass 20, count 0 2006.197.08:25:28.19#ibcon#about to read 4, iclass 20, count 0 2006.197.08:25:28.19#ibcon#read 4, iclass 20, count 0 2006.197.08:25:28.19#ibcon#about to read 5, iclass 20, count 0 2006.197.08:25:28.19#ibcon#read 5, iclass 20, count 0 2006.197.08:25:28.19#ibcon#about to read 6, iclass 20, count 0 2006.197.08:25:28.19#ibcon#read 6, iclass 20, count 0 2006.197.08:25:28.19#ibcon#end of sib2, iclass 20, count 0 2006.197.08:25:28.19#ibcon#*after write, iclass 20, count 0 2006.197.08:25:28.19#ibcon#*before return 0, iclass 20, count 0 2006.197.08:25:28.19#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.197.08:25:28.19#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.197.08:25:28.19#ibcon#about to clear, iclass 20 cls_cnt 0 2006.197.08:25:28.19#ibcon#cleared, iclass 20 cls_cnt 0 2006.197.08:25:28.19$vc4f8/va=3,6 2006.197.08:25:28.19#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.197.08:25:28.19#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.197.08:25:28.19#ibcon#ireg 11 cls_cnt 2 2006.197.08:25:28.19#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.197.08:25:28.25#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.197.08:25:28.25#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.197.08:25:28.25#ibcon#enter wrdev, iclass 22, count 2 2006.197.08:25:28.25#ibcon#first serial, iclass 22, count 2 2006.197.08:25:28.25#ibcon#enter sib2, iclass 22, count 2 2006.197.08:25:28.25#ibcon#flushed, iclass 22, count 2 2006.197.08:25:28.25#ibcon#about to write, iclass 22, count 2 2006.197.08:25:28.25#ibcon#wrote, iclass 22, count 2 2006.197.08:25:28.25#ibcon#about to read 3, iclass 22, count 2 2006.197.08:25:28.27#ibcon#read 3, iclass 22, count 2 2006.197.08:25:28.27#ibcon#about to read 4, iclass 22, count 2 2006.197.08:25:28.27#ibcon#read 4, iclass 22, count 2 2006.197.08:25:28.27#ibcon#about to read 5, iclass 22, count 2 2006.197.08:25:28.27#ibcon#read 5, iclass 22, count 2 2006.197.08:25:28.27#ibcon#about to read 6, iclass 22, count 2 2006.197.08:25:28.27#ibcon#read 6, iclass 22, count 2 2006.197.08:25:28.27#ibcon#end of sib2, iclass 22, count 2 2006.197.08:25:28.27#ibcon#*mode == 0, iclass 22, count 2 2006.197.08:25:28.27#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.197.08:25:28.27#ibcon#[25=AT03-06\r\n] 2006.197.08:25:28.27#ibcon#*before write, iclass 22, count 2 2006.197.08:25:28.27#ibcon#enter sib2, iclass 22, count 2 2006.197.08:25:28.27#ibcon#flushed, iclass 22, count 2 2006.197.08:25:28.27#ibcon#about to write, iclass 22, count 2 2006.197.08:25:28.27#ibcon#wrote, iclass 22, count 2 2006.197.08:25:28.27#ibcon#about to read 3, iclass 22, count 2 2006.197.08:25:28.30#ibcon#read 3, iclass 22, count 2 2006.197.08:25:28.30#ibcon#about to read 4, iclass 22, count 2 2006.197.08:25:28.30#ibcon#read 4, iclass 22, count 2 2006.197.08:25:28.30#ibcon#about to read 5, iclass 22, count 2 2006.197.08:25:28.30#ibcon#read 5, iclass 22, count 2 2006.197.08:25:28.30#ibcon#about to read 6, iclass 22, count 2 2006.197.08:25:28.30#ibcon#read 6, iclass 22, count 2 2006.197.08:25:28.30#ibcon#end of sib2, iclass 22, count 2 2006.197.08:25:28.30#ibcon#*after write, iclass 22, count 2 2006.197.08:25:28.30#ibcon#*before return 0, iclass 22, count 2 2006.197.08:25:28.30#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.197.08:25:28.30#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.197.08:25:28.30#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.197.08:25:28.30#ibcon#ireg 7 cls_cnt 0 2006.197.08:25:28.30#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.197.08:25:28.42#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.197.08:25:28.42#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.197.08:25:28.42#ibcon#enter wrdev, iclass 22, count 0 2006.197.08:25:28.42#ibcon#first serial, iclass 22, count 0 2006.197.08:25:28.42#ibcon#enter sib2, iclass 22, count 0 2006.197.08:25:28.42#ibcon#flushed, iclass 22, count 0 2006.197.08:25:28.42#ibcon#about to write, iclass 22, count 0 2006.197.08:25:28.42#ibcon#wrote, iclass 22, count 0 2006.197.08:25:28.42#ibcon#about to read 3, iclass 22, count 0 2006.197.08:25:28.44#ibcon#read 3, iclass 22, count 0 2006.197.08:25:28.44#ibcon#about to read 4, iclass 22, count 0 2006.197.08:25:28.44#ibcon#read 4, iclass 22, count 0 2006.197.08:25:28.44#ibcon#about to read 5, iclass 22, count 0 2006.197.08:25:28.44#ibcon#read 5, iclass 22, count 0 2006.197.08:25:28.44#ibcon#about to read 6, iclass 22, count 0 2006.197.08:25:28.44#ibcon#read 6, iclass 22, count 0 2006.197.08:25:28.44#ibcon#end of sib2, iclass 22, count 0 2006.197.08:25:28.44#ibcon#*mode == 0, iclass 22, count 0 2006.197.08:25:28.44#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.197.08:25:28.44#ibcon#[25=USB\r\n] 2006.197.08:25:28.44#ibcon#*before write, iclass 22, count 0 2006.197.08:25:28.44#ibcon#enter sib2, iclass 22, count 0 2006.197.08:25:28.44#ibcon#flushed, iclass 22, count 0 2006.197.08:25:28.44#ibcon#about to write, iclass 22, count 0 2006.197.08:25:28.44#ibcon#wrote, iclass 22, count 0 2006.197.08:25:28.44#ibcon#about to read 3, iclass 22, count 0 2006.197.08:25:28.47#ibcon#read 3, iclass 22, count 0 2006.197.08:25:28.47#ibcon#about to read 4, iclass 22, count 0 2006.197.08:25:28.47#ibcon#read 4, iclass 22, count 0 2006.197.08:25:28.47#ibcon#about to read 5, iclass 22, count 0 2006.197.08:25:28.47#ibcon#read 5, iclass 22, count 0 2006.197.08:25:28.47#ibcon#about to read 6, iclass 22, count 0 2006.197.08:25:28.47#ibcon#read 6, iclass 22, count 0 2006.197.08:25:28.47#ibcon#end of sib2, iclass 22, count 0 2006.197.08:25:28.47#ibcon#*after write, iclass 22, count 0 2006.197.08:25:28.47#ibcon#*before return 0, iclass 22, count 0 2006.197.08:25:28.47#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.197.08:25:28.47#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.197.08:25:28.47#ibcon#about to clear, iclass 22 cls_cnt 0 2006.197.08:25:28.47#ibcon#cleared, iclass 22 cls_cnt 0 2006.197.08:25:28.47$vc4f8/valo=4,832.99 2006.197.08:25:28.47#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.197.08:25:28.47#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.197.08:25:28.47#ibcon#ireg 17 cls_cnt 0 2006.197.08:25:28.47#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.197.08:25:28.47#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.197.08:25:28.47#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.197.08:25:28.47#ibcon#enter wrdev, iclass 24, count 0 2006.197.08:25:28.47#ibcon#first serial, iclass 24, count 0 2006.197.08:25:28.47#ibcon#enter sib2, iclass 24, count 0 2006.197.08:25:28.47#ibcon#flushed, iclass 24, count 0 2006.197.08:25:28.47#ibcon#about to write, iclass 24, count 0 2006.197.08:25:28.47#ibcon#wrote, iclass 24, count 0 2006.197.08:25:28.47#ibcon#about to read 3, iclass 24, count 0 2006.197.08:25:28.49#ibcon#read 3, iclass 24, count 0 2006.197.08:25:28.49#ibcon#about to read 4, iclass 24, count 0 2006.197.08:25:28.49#ibcon#read 4, iclass 24, count 0 2006.197.08:25:28.49#ibcon#about to read 5, iclass 24, count 0 2006.197.08:25:28.49#ibcon#read 5, iclass 24, count 0 2006.197.08:25:28.49#ibcon#about to read 6, iclass 24, count 0 2006.197.08:25:28.49#ibcon#read 6, iclass 24, count 0 2006.197.08:25:28.49#ibcon#end of sib2, iclass 24, count 0 2006.197.08:25:28.49#ibcon#*mode == 0, iclass 24, count 0 2006.197.08:25:28.49#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.197.08:25:28.49#ibcon#[26=FRQ=04,832.99\r\n] 2006.197.08:25:28.49#ibcon#*before write, iclass 24, count 0 2006.197.08:25:28.49#ibcon#enter sib2, iclass 24, count 0 2006.197.08:25:28.49#ibcon#flushed, iclass 24, count 0 2006.197.08:25:28.49#ibcon#about to write, iclass 24, count 0 2006.197.08:25:28.49#ibcon#wrote, iclass 24, count 0 2006.197.08:25:28.49#ibcon#about to read 3, iclass 24, count 0 2006.197.08:25:28.53#ibcon#read 3, iclass 24, count 0 2006.197.08:25:28.53#ibcon#about to read 4, iclass 24, count 0 2006.197.08:25:28.53#ibcon#read 4, iclass 24, count 0 2006.197.08:25:28.53#ibcon#about to read 5, iclass 24, count 0 2006.197.08:25:28.53#ibcon#read 5, iclass 24, count 0 2006.197.08:25:28.53#ibcon#about to read 6, iclass 24, count 0 2006.197.08:25:28.53#ibcon#read 6, iclass 24, count 0 2006.197.08:25:28.53#ibcon#end of sib2, iclass 24, count 0 2006.197.08:25:28.53#ibcon#*after write, iclass 24, count 0 2006.197.08:25:28.53#ibcon#*before return 0, iclass 24, count 0 2006.197.08:25:28.53#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.197.08:25:28.53#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.197.08:25:28.53#ibcon#about to clear, iclass 24 cls_cnt 0 2006.197.08:25:28.53#ibcon#cleared, iclass 24 cls_cnt 0 2006.197.08:25:28.53$vc4f8/va=4,7 2006.197.08:25:28.53#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.197.08:25:28.53#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.197.08:25:28.53#ibcon#ireg 11 cls_cnt 2 2006.197.08:25:28.53#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.197.08:25:28.59#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.197.08:25:28.59#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.197.08:25:28.59#ibcon#enter wrdev, iclass 26, count 2 2006.197.08:25:28.59#ibcon#first serial, iclass 26, count 2 2006.197.08:25:28.59#ibcon#enter sib2, iclass 26, count 2 2006.197.08:25:28.59#ibcon#flushed, iclass 26, count 2 2006.197.08:25:28.59#ibcon#about to write, iclass 26, count 2 2006.197.08:25:28.59#ibcon#wrote, iclass 26, count 2 2006.197.08:25:28.59#ibcon#about to read 3, iclass 26, count 2 2006.197.08:25:28.61#ibcon#read 3, iclass 26, count 2 2006.197.08:25:28.61#ibcon#about to read 4, iclass 26, count 2 2006.197.08:25:28.61#ibcon#read 4, iclass 26, count 2 2006.197.08:25:28.61#ibcon#about to read 5, iclass 26, count 2 2006.197.08:25:28.61#ibcon#read 5, iclass 26, count 2 2006.197.08:25:28.61#ibcon#about to read 6, iclass 26, count 2 2006.197.08:25:28.61#ibcon#read 6, iclass 26, count 2 2006.197.08:25:28.61#ibcon#end of sib2, iclass 26, count 2 2006.197.08:25:28.61#ibcon#*mode == 0, iclass 26, count 2 2006.197.08:25:28.61#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.197.08:25:28.61#ibcon#[25=AT04-07\r\n] 2006.197.08:25:28.61#ibcon#*before write, iclass 26, count 2 2006.197.08:25:28.61#ibcon#enter sib2, iclass 26, count 2 2006.197.08:25:28.61#ibcon#flushed, iclass 26, count 2 2006.197.08:25:28.61#ibcon#about to write, iclass 26, count 2 2006.197.08:25:28.61#ibcon#wrote, iclass 26, count 2 2006.197.08:25:28.61#ibcon#about to read 3, iclass 26, count 2 2006.197.08:25:28.64#ibcon#read 3, iclass 26, count 2 2006.197.08:25:28.64#ibcon#about to read 4, iclass 26, count 2 2006.197.08:25:28.64#ibcon#read 4, iclass 26, count 2 2006.197.08:25:28.64#ibcon#about to read 5, iclass 26, count 2 2006.197.08:25:28.64#ibcon#read 5, iclass 26, count 2 2006.197.08:25:28.64#ibcon#about to read 6, iclass 26, count 2 2006.197.08:25:28.64#ibcon#read 6, iclass 26, count 2 2006.197.08:25:28.64#ibcon#end of sib2, iclass 26, count 2 2006.197.08:25:28.64#ibcon#*after write, iclass 26, count 2 2006.197.08:25:28.64#ibcon#*before return 0, iclass 26, count 2 2006.197.08:25:28.64#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.197.08:25:28.64#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.197.08:25:28.64#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.197.08:25:28.64#ibcon#ireg 7 cls_cnt 0 2006.197.08:25:28.64#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.197.08:25:28.76#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.197.08:25:28.76#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.197.08:25:28.76#ibcon#enter wrdev, iclass 26, count 0 2006.197.08:25:28.76#ibcon#first serial, iclass 26, count 0 2006.197.08:25:28.76#ibcon#enter sib2, iclass 26, count 0 2006.197.08:25:28.76#ibcon#flushed, iclass 26, count 0 2006.197.08:25:28.76#ibcon#about to write, iclass 26, count 0 2006.197.08:25:28.76#ibcon#wrote, iclass 26, count 0 2006.197.08:25:28.76#ibcon#about to read 3, iclass 26, count 0 2006.197.08:25:28.78#ibcon#read 3, iclass 26, count 0 2006.197.08:25:28.78#ibcon#about to read 4, iclass 26, count 0 2006.197.08:25:28.78#ibcon#read 4, iclass 26, count 0 2006.197.08:25:28.78#ibcon#about to read 5, iclass 26, count 0 2006.197.08:25:28.78#ibcon#read 5, iclass 26, count 0 2006.197.08:25:28.78#ibcon#about to read 6, iclass 26, count 0 2006.197.08:25:28.78#ibcon#read 6, iclass 26, count 0 2006.197.08:25:28.78#ibcon#end of sib2, iclass 26, count 0 2006.197.08:25:28.78#ibcon#*mode == 0, iclass 26, count 0 2006.197.08:25:28.78#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.197.08:25:28.78#ibcon#[25=USB\r\n] 2006.197.08:25:28.78#ibcon#*before write, iclass 26, count 0 2006.197.08:25:28.78#ibcon#enter sib2, iclass 26, count 0 2006.197.08:25:28.78#ibcon#flushed, iclass 26, count 0 2006.197.08:25:28.78#ibcon#about to write, iclass 26, count 0 2006.197.08:25:28.78#ibcon#wrote, iclass 26, count 0 2006.197.08:25:28.78#ibcon#about to read 3, iclass 26, count 0 2006.197.08:25:28.81#ibcon#read 3, iclass 26, count 0 2006.197.08:25:28.81#ibcon#about to read 4, iclass 26, count 0 2006.197.08:25:28.81#ibcon#read 4, iclass 26, count 0 2006.197.08:25:28.81#ibcon#about to read 5, iclass 26, count 0 2006.197.08:25:28.81#ibcon#read 5, iclass 26, count 0 2006.197.08:25:28.81#ibcon#about to read 6, iclass 26, count 0 2006.197.08:25:28.81#ibcon#read 6, iclass 26, count 0 2006.197.08:25:28.81#ibcon#end of sib2, iclass 26, count 0 2006.197.08:25:28.81#ibcon#*after write, iclass 26, count 0 2006.197.08:25:28.81#ibcon#*before return 0, iclass 26, count 0 2006.197.08:25:28.81#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.197.08:25:28.81#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.197.08:25:28.81#ibcon#about to clear, iclass 26 cls_cnt 0 2006.197.08:25:28.81#ibcon#cleared, iclass 26 cls_cnt 0 2006.197.08:25:28.81$vc4f8/valo=5,652.99 2006.197.08:25:28.81#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.197.08:25:28.81#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.197.08:25:28.81#ibcon#ireg 17 cls_cnt 0 2006.197.08:25:28.81#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.197.08:25:28.81#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.197.08:25:28.81#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.197.08:25:28.81#ibcon#enter wrdev, iclass 28, count 0 2006.197.08:25:28.81#ibcon#first serial, iclass 28, count 0 2006.197.08:25:28.81#ibcon#enter sib2, iclass 28, count 0 2006.197.08:25:28.81#ibcon#flushed, iclass 28, count 0 2006.197.08:25:28.81#ibcon#about to write, iclass 28, count 0 2006.197.08:25:28.81#ibcon#wrote, iclass 28, count 0 2006.197.08:25:28.81#ibcon#about to read 3, iclass 28, count 0 2006.197.08:25:28.83#ibcon#read 3, iclass 28, count 0 2006.197.08:25:28.83#ibcon#about to read 4, iclass 28, count 0 2006.197.08:25:28.83#ibcon#read 4, iclass 28, count 0 2006.197.08:25:28.83#ibcon#about to read 5, iclass 28, count 0 2006.197.08:25:28.83#ibcon#read 5, iclass 28, count 0 2006.197.08:25:28.83#ibcon#about to read 6, iclass 28, count 0 2006.197.08:25:28.83#ibcon#read 6, iclass 28, count 0 2006.197.08:25:28.83#ibcon#end of sib2, iclass 28, count 0 2006.197.08:25:28.83#ibcon#*mode == 0, iclass 28, count 0 2006.197.08:25:28.83#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.197.08:25:28.83#ibcon#[26=FRQ=05,652.99\r\n] 2006.197.08:25:28.83#ibcon#*before write, iclass 28, count 0 2006.197.08:25:28.83#ibcon#enter sib2, iclass 28, count 0 2006.197.08:25:28.83#ibcon#flushed, iclass 28, count 0 2006.197.08:25:28.83#ibcon#about to write, iclass 28, count 0 2006.197.08:25:28.83#ibcon#wrote, iclass 28, count 0 2006.197.08:25:28.83#ibcon#about to read 3, iclass 28, count 0 2006.197.08:25:28.87#ibcon#read 3, iclass 28, count 0 2006.197.08:25:28.87#ibcon#about to read 4, iclass 28, count 0 2006.197.08:25:28.87#ibcon#read 4, iclass 28, count 0 2006.197.08:25:28.87#ibcon#about to read 5, iclass 28, count 0 2006.197.08:25:28.87#ibcon#read 5, iclass 28, count 0 2006.197.08:25:28.87#ibcon#about to read 6, iclass 28, count 0 2006.197.08:25:28.87#ibcon#read 6, iclass 28, count 0 2006.197.08:25:28.87#ibcon#end of sib2, iclass 28, count 0 2006.197.08:25:28.87#ibcon#*after write, iclass 28, count 0 2006.197.08:25:28.87#ibcon#*before return 0, iclass 28, count 0 2006.197.08:25:28.87#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.197.08:25:28.87#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.197.08:25:28.87#ibcon#about to clear, iclass 28 cls_cnt 0 2006.197.08:25:28.87#ibcon#cleared, iclass 28 cls_cnt 0 2006.197.08:25:28.87$vc4f8/va=5,7 2006.197.08:25:28.87#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.197.08:25:28.87#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.197.08:25:28.87#ibcon#ireg 11 cls_cnt 2 2006.197.08:25:28.87#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.197.08:25:28.93#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.197.08:25:28.93#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.197.08:25:28.93#ibcon#enter wrdev, iclass 30, count 2 2006.197.08:25:28.93#ibcon#first serial, iclass 30, count 2 2006.197.08:25:28.93#ibcon#enter sib2, iclass 30, count 2 2006.197.08:25:28.93#ibcon#flushed, iclass 30, count 2 2006.197.08:25:28.93#ibcon#about to write, iclass 30, count 2 2006.197.08:25:28.93#ibcon#wrote, iclass 30, count 2 2006.197.08:25:28.93#ibcon#about to read 3, iclass 30, count 2 2006.197.08:25:28.95#ibcon#read 3, iclass 30, count 2 2006.197.08:25:28.95#ibcon#about to read 4, iclass 30, count 2 2006.197.08:25:28.95#ibcon#read 4, iclass 30, count 2 2006.197.08:25:28.95#ibcon#about to read 5, iclass 30, count 2 2006.197.08:25:28.95#ibcon#read 5, iclass 30, count 2 2006.197.08:25:28.95#ibcon#about to read 6, iclass 30, count 2 2006.197.08:25:28.95#ibcon#read 6, iclass 30, count 2 2006.197.08:25:28.95#ibcon#end of sib2, iclass 30, count 2 2006.197.08:25:28.95#ibcon#*mode == 0, iclass 30, count 2 2006.197.08:25:28.95#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.197.08:25:28.95#ibcon#[25=AT05-07\r\n] 2006.197.08:25:28.95#ibcon#*before write, iclass 30, count 2 2006.197.08:25:28.95#ibcon#enter sib2, iclass 30, count 2 2006.197.08:25:28.95#ibcon#flushed, iclass 30, count 2 2006.197.08:25:28.95#ibcon#about to write, iclass 30, count 2 2006.197.08:25:28.95#ibcon#wrote, iclass 30, count 2 2006.197.08:25:28.95#ibcon#about to read 3, iclass 30, count 2 2006.197.08:25:28.98#ibcon#read 3, iclass 30, count 2 2006.197.08:25:28.98#ibcon#about to read 4, iclass 30, count 2 2006.197.08:25:28.98#ibcon#read 4, iclass 30, count 2 2006.197.08:25:28.98#ibcon#about to read 5, iclass 30, count 2 2006.197.08:25:28.98#ibcon#read 5, iclass 30, count 2 2006.197.08:25:28.98#ibcon#about to read 6, iclass 30, count 2 2006.197.08:25:28.98#ibcon#read 6, iclass 30, count 2 2006.197.08:25:28.98#ibcon#end of sib2, iclass 30, count 2 2006.197.08:25:28.98#ibcon#*after write, iclass 30, count 2 2006.197.08:25:28.98#ibcon#*before return 0, iclass 30, count 2 2006.197.08:25:28.98#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.197.08:25:28.98#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.197.08:25:28.98#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.197.08:25:28.98#ibcon#ireg 7 cls_cnt 0 2006.197.08:25:28.98#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.197.08:25:29.10#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.197.08:25:29.10#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.197.08:25:29.10#ibcon#enter wrdev, iclass 30, count 0 2006.197.08:25:29.10#ibcon#first serial, iclass 30, count 0 2006.197.08:25:29.10#ibcon#enter sib2, iclass 30, count 0 2006.197.08:25:29.10#ibcon#flushed, iclass 30, count 0 2006.197.08:25:29.10#ibcon#about to write, iclass 30, count 0 2006.197.08:25:29.10#ibcon#wrote, iclass 30, count 0 2006.197.08:25:29.10#ibcon#about to read 3, iclass 30, count 0 2006.197.08:25:29.12#ibcon#read 3, iclass 30, count 0 2006.197.08:25:29.12#ibcon#about to read 4, iclass 30, count 0 2006.197.08:25:29.12#ibcon#read 4, iclass 30, count 0 2006.197.08:25:29.12#ibcon#about to read 5, iclass 30, count 0 2006.197.08:25:29.12#ibcon#read 5, iclass 30, count 0 2006.197.08:25:29.12#ibcon#about to read 6, iclass 30, count 0 2006.197.08:25:29.12#ibcon#read 6, iclass 30, count 0 2006.197.08:25:29.12#ibcon#end of sib2, iclass 30, count 0 2006.197.08:25:29.12#ibcon#*mode == 0, iclass 30, count 0 2006.197.08:25:29.12#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.197.08:25:29.12#ibcon#[25=USB\r\n] 2006.197.08:25:29.12#ibcon#*before write, iclass 30, count 0 2006.197.08:25:29.12#ibcon#enter sib2, iclass 30, count 0 2006.197.08:25:29.12#ibcon#flushed, iclass 30, count 0 2006.197.08:25:29.12#ibcon#about to write, iclass 30, count 0 2006.197.08:25:29.12#ibcon#wrote, iclass 30, count 0 2006.197.08:25:29.12#ibcon#about to read 3, iclass 30, count 0 2006.197.08:25:29.15#ibcon#read 3, iclass 30, count 0 2006.197.08:25:29.15#ibcon#about to read 4, iclass 30, count 0 2006.197.08:25:29.15#ibcon#read 4, iclass 30, count 0 2006.197.08:25:29.15#ibcon#about to read 5, iclass 30, count 0 2006.197.08:25:29.15#ibcon#read 5, iclass 30, count 0 2006.197.08:25:29.15#ibcon#about to read 6, iclass 30, count 0 2006.197.08:25:29.15#ibcon#read 6, iclass 30, count 0 2006.197.08:25:29.15#ibcon#end of sib2, iclass 30, count 0 2006.197.08:25:29.15#ibcon#*after write, iclass 30, count 0 2006.197.08:25:29.15#ibcon#*before return 0, iclass 30, count 0 2006.197.08:25:29.15#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.197.08:25:29.15#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.197.08:25:29.15#ibcon#about to clear, iclass 30 cls_cnt 0 2006.197.08:25:29.15#ibcon#cleared, iclass 30 cls_cnt 0 2006.197.08:25:29.15$vc4f8/valo=6,772.99 2006.197.08:25:29.15#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.197.08:25:29.15#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.197.08:25:29.15#ibcon#ireg 17 cls_cnt 0 2006.197.08:25:29.15#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.197.08:25:29.15#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.197.08:25:29.15#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.197.08:25:29.15#ibcon#enter wrdev, iclass 32, count 0 2006.197.08:25:29.15#ibcon#first serial, iclass 32, count 0 2006.197.08:25:29.15#ibcon#enter sib2, iclass 32, count 0 2006.197.08:25:29.15#ibcon#flushed, iclass 32, count 0 2006.197.08:25:29.15#ibcon#about to write, iclass 32, count 0 2006.197.08:25:29.15#ibcon#wrote, iclass 32, count 0 2006.197.08:25:29.15#ibcon#about to read 3, iclass 32, count 0 2006.197.08:25:29.17#ibcon#read 3, iclass 32, count 0 2006.197.08:25:29.17#ibcon#about to read 4, iclass 32, count 0 2006.197.08:25:29.17#ibcon#read 4, iclass 32, count 0 2006.197.08:25:29.17#ibcon#about to read 5, iclass 32, count 0 2006.197.08:25:29.17#ibcon#read 5, iclass 32, count 0 2006.197.08:25:29.17#ibcon#about to read 6, iclass 32, count 0 2006.197.08:25:29.17#ibcon#read 6, iclass 32, count 0 2006.197.08:25:29.17#ibcon#end of sib2, iclass 32, count 0 2006.197.08:25:29.17#ibcon#*mode == 0, iclass 32, count 0 2006.197.08:25:29.17#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.197.08:25:29.17#ibcon#[26=FRQ=06,772.99\r\n] 2006.197.08:25:29.17#ibcon#*before write, iclass 32, count 0 2006.197.08:25:29.17#ibcon#enter sib2, iclass 32, count 0 2006.197.08:25:29.17#ibcon#flushed, iclass 32, count 0 2006.197.08:25:29.17#ibcon#about to write, iclass 32, count 0 2006.197.08:25:29.17#ibcon#wrote, iclass 32, count 0 2006.197.08:25:29.17#ibcon#about to read 3, iclass 32, count 0 2006.197.08:25:29.21#ibcon#read 3, iclass 32, count 0 2006.197.08:25:29.21#ibcon#about to read 4, iclass 32, count 0 2006.197.08:25:29.21#ibcon#read 4, iclass 32, count 0 2006.197.08:25:29.21#ibcon#about to read 5, iclass 32, count 0 2006.197.08:25:29.21#ibcon#read 5, iclass 32, count 0 2006.197.08:25:29.21#ibcon#about to read 6, iclass 32, count 0 2006.197.08:25:29.21#ibcon#read 6, iclass 32, count 0 2006.197.08:25:29.21#ibcon#end of sib2, iclass 32, count 0 2006.197.08:25:29.21#ibcon#*after write, iclass 32, count 0 2006.197.08:25:29.21#ibcon#*before return 0, iclass 32, count 0 2006.197.08:25:29.21#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.197.08:25:29.21#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.197.08:25:29.21#ibcon#about to clear, iclass 32 cls_cnt 0 2006.197.08:25:29.21#ibcon#cleared, iclass 32 cls_cnt 0 2006.197.08:25:29.21$vc4f8/va=6,6 2006.197.08:25:29.21#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.197.08:25:29.21#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.197.08:25:29.21#ibcon#ireg 11 cls_cnt 2 2006.197.08:25:29.21#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.197.08:25:29.27#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.197.08:25:29.27#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.197.08:25:29.27#ibcon#enter wrdev, iclass 34, count 2 2006.197.08:25:29.27#ibcon#first serial, iclass 34, count 2 2006.197.08:25:29.27#ibcon#enter sib2, iclass 34, count 2 2006.197.08:25:29.27#ibcon#flushed, iclass 34, count 2 2006.197.08:25:29.27#ibcon#about to write, iclass 34, count 2 2006.197.08:25:29.27#ibcon#wrote, iclass 34, count 2 2006.197.08:25:29.27#ibcon#about to read 3, iclass 34, count 2 2006.197.08:25:29.29#ibcon#read 3, iclass 34, count 2 2006.197.08:25:29.29#ibcon#about to read 4, iclass 34, count 2 2006.197.08:25:29.29#ibcon#read 4, iclass 34, count 2 2006.197.08:25:29.29#ibcon#about to read 5, iclass 34, count 2 2006.197.08:25:29.29#ibcon#read 5, iclass 34, count 2 2006.197.08:25:29.29#ibcon#about to read 6, iclass 34, count 2 2006.197.08:25:29.29#ibcon#read 6, iclass 34, count 2 2006.197.08:25:29.29#ibcon#end of sib2, iclass 34, count 2 2006.197.08:25:29.29#ibcon#*mode == 0, iclass 34, count 2 2006.197.08:25:29.29#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.197.08:25:29.29#ibcon#[25=AT06-06\r\n] 2006.197.08:25:29.29#ibcon#*before write, iclass 34, count 2 2006.197.08:25:29.29#ibcon#enter sib2, iclass 34, count 2 2006.197.08:25:29.29#ibcon#flushed, iclass 34, count 2 2006.197.08:25:29.29#ibcon#about to write, iclass 34, count 2 2006.197.08:25:29.29#ibcon#wrote, iclass 34, count 2 2006.197.08:25:29.29#ibcon#about to read 3, iclass 34, count 2 2006.197.08:25:29.32#ibcon#read 3, iclass 34, count 2 2006.197.08:25:29.32#ibcon#about to read 4, iclass 34, count 2 2006.197.08:25:29.32#ibcon#read 4, iclass 34, count 2 2006.197.08:25:29.32#ibcon#about to read 5, iclass 34, count 2 2006.197.08:25:29.32#ibcon#read 5, iclass 34, count 2 2006.197.08:25:29.32#ibcon#about to read 6, iclass 34, count 2 2006.197.08:25:29.32#ibcon#read 6, iclass 34, count 2 2006.197.08:25:29.32#ibcon#end of sib2, iclass 34, count 2 2006.197.08:25:29.32#ibcon#*after write, iclass 34, count 2 2006.197.08:25:29.32#ibcon#*before return 0, iclass 34, count 2 2006.197.08:25:29.32#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.197.08:25:29.32#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.197.08:25:29.32#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.197.08:25:29.32#ibcon#ireg 7 cls_cnt 0 2006.197.08:25:29.32#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.197.08:25:29.44#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.197.08:25:29.44#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.197.08:25:29.44#ibcon#enter wrdev, iclass 34, count 0 2006.197.08:25:29.44#ibcon#first serial, iclass 34, count 0 2006.197.08:25:29.44#ibcon#enter sib2, iclass 34, count 0 2006.197.08:25:29.44#ibcon#flushed, iclass 34, count 0 2006.197.08:25:29.44#ibcon#about to write, iclass 34, count 0 2006.197.08:25:29.44#ibcon#wrote, iclass 34, count 0 2006.197.08:25:29.44#ibcon#about to read 3, iclass 34, count 0 2006.197.08:25:29.46#ibcon#read 3, iclass 34, count 0 2006.197.08:25:29.46#ibcon#about to read 4, iclass 34, count 0 2006.197.08:25:29.46#ibcon#read 4, iclass 34, count 0 2006.197.08:25:29.46#ibcon#about to read 5, iclass 34, count 0 2006.197.08:25:29.46#ibcon#read 5, iclass 34, count 0 2006.197.08:25:29.46#ibcon#about to read 6, iclass 34, count 0 2006.197.08:25:29.46#ibcon#read 6, iclass 34, count 0 2006.197.08:25:29.46#ibcon#end of sib2, iclass 34, count 0 2006.197.08:25:29.46#ibcon#*mode == 0, iclass 34, count 0 2006.197.08:25:29.46#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.197.08:25:29.46#ibcon#[25=USB\r\n] 2006.197.08:25:29.46#ibcon#*before write, iclass 34, count 0 2006.197.08:25:29.46#ibcon#enter sib2, iclass 34, count 0 2006.197.08:25:29.46#ibcon#flushed, iclass 34, count 0 2006.197.08:25:29.46#ibcon#about to write, iclass 34, count 0 2006.197.08:25:29.46#ibcon#wrote, iclass 34, count 0 2006.197.08:25:29.46#ibcon#about to read 3, iclass 34, count 0 2006.197.08:25:29.49#ibcon#read 3, iclass 34, count 0 2006.197.08:25:29.49#ibcon#about to read 4, iclass 34, count 0 2006.197.08:25:29.49#ibcon#read 4, iclass 34, count 0 2006.197.08:25:29.49#ibcon#about to read 5, iclass 34, count 0 2006.197.08:25:29.49#ibcon#read 5, iclass 34, count 0 2006.197.08:25:29.49#ibcon#about to read 6, iclass 34, count 0 2006.197.08:25:29.49#ibcon#read 6, iclass 34, count 0 2006.197.08:25:29.49#ibcon#end of sib2, iclass 34, count 0 2006.197.08:25:29.49#ibcon#*after write, iclass 34, count 0 2006.197.08:25:29.49#ibcon#*before return 0, iclass 34, count 0 2006.197.08:25:29.49#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.197.08:25:29.49#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.197.08:25:29.49#ibcon#about to clear, iclass 34 cls_cnt 0 2006.197.08:25:29.49#ibcon#cleared, iclass 34 cls_cnt 0 2006.197.08:25:29.49$vc4f8/valo=7,832.99 2006.197.08:25:29.49#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.197.08:25:29.49#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.197.08:25:29.49#ibcon#ireg 17 cls_cnt 0 2006.197.08:25:29.49#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.197.08:25:29.49#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.197.08:25:29.49#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.197.08:25:29.49#ibcon#enter wrdev, iclass 36, count 0 2006.197.08:25:29.49#ibcon#first serial, iclass 36, count 0 2006.197.08:25:29.49#ibcon#enter sib2, iclass 36, count 0 2006.197.08:25:29.49#ibcon#flushed, iclass 36, count 0 2006.197.08:25:29.49#ibcon#about to write, iclass 36, count 0 2006.197.08:25:29.49#ibcon#wrote, iclass 36, count 0 2006.197.08:25:29.49#ibcon#about to read 3, iclass 36, count 0 2006.197.08:25:29.51#ibcon#read 3, iclass 36, count 0 2006.197.08:25:29.51#ibcon#about to read 4, iclass 36, count 0 2006.197.08:25:29.51#ibcon#read 4, iclass 36, count 0 2006.197.08:25:29.51#ibcon#about to read 5, iclass 36, count 0 2006.197.08:25:29.51#ibcon#read 5, iclass 36, count 0 2006.197.08:25:29.51#ibcon#about to read 6, iclass 36, count 0 2006.197.08:25:29.51#ibcon#read 6, iclass 36, count 0 2006.197.08:25:29.51#ibcon#end of sib2, iclass 36, count 0 2006.197.08:25:29.51#ibcon#*mode == 0, iclass 36, count 0 2006.197.08:25:29.51#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.197.08:25:29.51#ibcon#[26=FRQ=07,832.99\r\n] 2006.197.08:25:29.51#ibcon#*before write, iclass 36, count 0 2006.197.08:25:29.51#ibcon#enter sib2, iclass 36, count 0 2006.197.08:25:29.51#ibcon#flushed, iclass 36, count 0 2006.197.08:25:29.51#ibcon#about to write, iclass 36, count 0 2006.197.08:25:29.51#ibcon#wrote, iclass 36, count 0 2006.197.08:25:29.51#ibcon#about to read 3, iclass 36, count 0 2006.197.08:25:29.55#ibcon#read 3, iclass 36, count 0 2006.197.08:25:29.55#ibcon#about to read 4, iclass 36, count 0 2006.197.08:25:29.55#ibcon#read 4, iclass 36, count 0 2006.197.08:25:29.55#ibcon#about to read 5, iclass 36, count 0 2006.197.08:25:29.55#ibcon#read 5, iclass 36, count 0 2006.197.08:25:29.55#ibcon#about to read 6, iclass 36, count 0 2006.197.08:25:29.55#ibcon#read 6, iclass 36, count 0 2006.197.08:25:29.55#ibcon#end of sib2, iclass 36, count 0 2006.197.08:25:29.55#ibcon#*after write, iclass 36, count 0 2006.197.08:25:29.55#ibcon#*before return 0, iclass 36, count 0 2006.197.08:25:29.55#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.197.08:25:29.55#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.197.08:25:29.55#ibcon#about to clear, iclass 36 cls_cnt 0 2006.197.08:25:29.55#ibcon#cleared, iclass 36 cls_cnt 0 2006.197.08:25:29.55$vc4f8/va=7,6 2006.197.08:25:29.55#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.197.08:25:29.55#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.197.08:25:29.55#ibcon#ireg 11 cls_cnt 2 2006.197.08:25:29.55#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.197.08:25:29.61#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.197.08:25:29.61#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.197.08:25:29.61#ibcon#enter wrdev, iclass 38, count 2 2006.197.08:25:29.61#ibcon#first serial, iclass 38, count 2 2006.197.08:25:29.61#ibcon#enter sib2, iclass 38, count 2 2006.197.08:25:29.61#ibcon#flushed, iclass 38, count 2 2006.197.08:25:29.61#ibcon#about to write, iclass 38, count 2 2006.197.08:25:29.61#ibcon#wrote, iclass 38, count 2 2006.197.08:25:29.61#ibcon#about to read 3, iclass 38, count 2 2006.197.08:25:29.63#ibcon#read 3, iclass 38, count 2 2006.197.08:25:29.63#ibcon#about to read 4, iclass 38, count 2 2006.197.08:25:29.63#ibcon#read 4, iclass 38, count 2 2006.197.08:25:29.63#ibcon#about to read 5, iclass 38, count 2 2006.197.08:25:29.63#ibcon#read 5, iclass 38, count 2 2006.197.08:25:29.63#ibcon#about to read 6, iclass 38, count 2 2006.197.08:25:29.63#ibcon#read 6, iclass 38, count 2 2006.197.08:25:29.63#ibcon#end of sib2, iclass 38, count 2 2006.197.08:25:29.63#ibcon#*mode == 0, iclass 38, count 2 2006.197.08:25:29.63#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.197.08:25:29.63#ibcon#[25=AT07-06\r\n] 2006.197.08:25:29.63#ibcon#*before write, iclass 38, count 2 2006.197.08:25:29.63#ibcon#enter sib2, iclass 38, count 2 2006.197.08:25:29.63#ibcon#flushed, iclass 38, count 2 2006.197.08:25:29.63#ibcon#about to write, iclass 38, count 2 2006.197.08:25:29.63#ibcon#wrote, iclass 38, count 2 2006.197.08:25:29.63#ibcon#about to read 3, iclass 38, count 2 2006.197.08:25:29.66#ibcon#read 3, iclass 38, count 2 2006.197.08:25:29.66#ibcon#about to read 4, iclass 38, count 2 2006.197.08:25:29.66#ibcon#read 4, iclass 38, count 2 2006.197.08:25:29.66#ibcon#about to read 5, iclass 38, count 2 2006.197.08:25:29.66#ibcon#read 5, iclass 38, count 2 2006.197.08:25:29.66#ibcon#about to read 6, iclass 38, count 2 2006.197.08:25:29.66#ibcon#read 6, iclass 38, count 2 2006.197.08:25:29.66#ibcon#end of sib2, iclass 38, count 2 2006.197.08:25:29.66#ibcon#*after write, iclass 38, count 2 2006.197.08:25:29.66#ibcon#*before return 0, iclass 38, count 2 2006.197.08:25:29.66#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.197.08:25:29.66#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.197.08:25:29.66#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.197.08:25:29.66#ibcon#ireg 7 cls_cnt 0 2006.197.08:25:29.66#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.197.08:25:29.78#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.197.08:25:29.78#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.197.08:25:29.78#ibcon#enter wrdev, iclass 38, count 0 2006.197.08:25:29.78#ibcon#first serial, iclass 38, count 0 2006.197.08:25:29.78#ibcon#enter sib2, iclass 38, count 0 2006.197.08:25:29.78#ibcon#flushed, iclass 38, count 0 2006.197.08:25:29.78#ibcon#about to write, iclass 38, count 0 2006.197.08:25:29.78#ibcon#wrote, iclass 38, count 0 2006.197.08:25:29.78#ibcon#about to read 3, iclass 38, count 0 2006.197.08:25:29.80#ibcon#read 3, iclass 38, count 0 2006.197.08:25:29.80#ibcon#about to read 4, iclass 38, count 0 2006.197.08:25:29.80#ibcon#read 4, iclass 38, count 0 2006.197.08:25:29.80#ibcon#about to read 5, iclass 38, count 0 2006.197.08:25:29.80#ibcon#read 5, iclass 38, count 0 2006.197.08:25:29.80#ibcon#about to read 6, iclass 38, count 0 2006.197.08:25:29.80#ibcon#read 6, iclass 38, count 0 2006.197.08:25:29.80#ibcon#end of sib2, iclass 38, count 0 2006.197.08:25:29.80#ibcon#*mode == 0, iclass 38, count 0 2006.197.08:25:29.80#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.197.08:25:29.80#ibcon#[25=USB\r\n] 2006.197.08:25:29.80#ibcon#*before write, iclass 38, count 0 2006.197.08:25:29.80#ibcon#enter sib2, iclass 38, count 0 2006.197.08:25:29.80#ibcon#flushed, iclass 38, count 0 2006.197.08:25:29.80#ibcon#about to write, iclass 38, count 0 2006.197.08:25:29.80#ibcon#wrote, iclass 38, count 0 2006.197.08:25:29.80#ibcon#about to read 3, iclass 38, count 0 2006.197.08:25:29.83#ibcon#read 3, iclass 38, count 0 2006.197.08:25:29.83#ibcon#about to read 4, iclass 38, count 0 2006.197.08:25:29.83#ibcon#read 4, iclass 38, count 0 2006.197.08:25:29.83#ibcon#about to read 5, iclass 38, count 0 2006.197.08:25:29.83#ibcon#read 5, iclass 38, count 0 2006.197.08:25:29.83#ibcon#about to read 6, iclass 38, count 0 2006.197.08:25:29.83#ibcon#read 6, iclass 38, count 0 2006.197.08:25:29.83#ibcon#end of sib2, iclass 38, count 0 2006.197.08:25:29.83#ibcon#*after write, iclass 38, count 0 2006.197.08:25:29.83#ibcon#*before return 0, iclass 38, count 0 2006.197.08:25:29.83#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.197.08:25:29.83#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.197.08:25:29.83#ibcon#about to clear, iclass 38 cls_cnt 0 2006.197.08:25:29.83#ibcon#cleared, iclass 38 cls_cnt 0 2006.197.08:25:29.83$vc4f8/valo=8,852.99 2006.197.08:25:29.83#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.197.08:25:29.83#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.197.08:25:29.83#ibcon#ireg 17 cls_cnt 0 2006.197.08:25:29.83#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.197.08:25:29.83#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.197.08:25:29.83#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.197.08:25:29.83#ibcon#enter wrdev, iclass 40, count 0 2006.197.08:25:29.83#ibcon#first serial, iclass 40, count 0 2006.197.08:25:29.83#ibcon#enter sib2, iclass 40, count 0 2006.197.08:25:29.83#ibcon#flushed, iclass 40, count 0 2006.197.08:25:29.83#ibcon#about to write, iclass 40, count 0 2006.197.08:25:29.83#ibcon#wrote, iclass 40, count 0 2006.197.08:25:29.83#ibcon#about to read 3, iclass 40, count 0 2006.197.08:25:29.85#ibcon#read 3, iclass 40, count 0 2006.197.08:25:29.85#ibcon#about to read 4, iclass 40, count 0 2006.197.08:25:29.85#ibcon#read 4, iclass 40, count 0 2006.197.08:25:29.85#ibcon#about to read 5, iclass 40, count 0 2006.197.08:25:29.85#ibcon#read 5, iclass 40, count 0 2006.197.08:25:29.85#ibcon#about to read 6, iclass 40, count 0 2006.197.08:25:29.85#ibcon#read 6, iclass 40, count 0 2006.197.08:25:29.85#ibcon#end of sib2, iclass 40, count 0 2006.197.08:25:29.85#ibcon#*mode == 0, iclass 40, count 0 2006.197.08:25:29.85#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.197.08:25:29.85#ibcon#[26=FRQ=08,852.99\r\n] 2006.197.08:25:29.85#ibcon#*before write, iclass 40, count 0 2006.197.08:25:29.85#ibcon#enter sib2, iclass 40, count 0 2006.197.08:25:29.85#ibcon#flushed, iclass 40, count 0 2006.197.08:25:29.85#ibcon#about to write, iclass 40, count 0 2006.197.08:25:29.85#ibcon#wrote, iclass 40, count 0 2006.197.08:25:29.85#ibcon#about to read 3, iclass 40, count 0 2006.197.08:25:29.89#ibcon#read 3, iclass 40, count 0 2006.197.08:25:29.89#ibcon#about to read 4, iclass 40, count 0 2006.197.08:25:29.89#ibcon#read 4, iclass 40, count 0 2006.197.08:25:29.89#ibcon#about to read 5, iclass 40, count 0 2006.197.08:25:29.89#ibcon#read 5, iclass 40, count 0 2006.197.08:25:29.89#ibcon#about to read 6, iclass 40, count 0 2006.197.08:25:29.89#ibcon#read 6, iclass 40, count 0 2006.197.08:25:29.89#ibcon#end of sib2, iclass 40, count 0 2006.197.08:25:29.89#ibcon#*after write, iclass 40, count 0 2006.197.08:25:29.89#ibcon#*before return 0, iclass 40, count 0 2006.197.08:25:29.89#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.197.08:25:29.89#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.197.08:25:29.89#ibcon#about to clear, iclass 40 cls_cnt 0 2006.197.08:25:29.89#ibcon#cleared, iclass 40 cls_cnt 0 2006.197.08:25:29.89$vc4f8/va=8,7 2006.197.08:25:29.89#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.197.08:25:29.89#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.197.08:25:29.89#ibcon#ireg 11 cls_cnt 2 2006.197.08:25:29.89#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.197.08:25:29.95#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.197.08:25:29.95#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.197.08:25:29.95#ibcon#enter wrdev, iclass 4, count 2 2006.197.08:25:29.95#ibcon#first serial, iclass 4, count 2 2006.197.08:25:29.95#ibcon#enter sib2, iclass 4, count 2 2006.197.08:25:29.95#ibcon#flushed, iclass 4, count 2 2006.197.08:25:29.95#ibcon#about to write, iclass 4, count 2 2006.197.08:25:29.95#ibcon#wrote, iclass 4, count 2 2006.197.08:25:29.95#ibcon#about to read 3, iclass 4, count 2 2006.197.08:25:29.97#ibcon#read 3, iclass 4, count 2 2006.197.08:25:29.97#ibcon#about to read 4, iclass 4, count 2 2006.197.08:25:29.97#ibcon#read 4, iclass 4, count 2 2006.197.08:25:29.97#ibcon#about to read 5, iclass 4, count 2 2006.197.08:25:29.97#ibcon#read 5, iclass 4, count 2 2006.197.08:25:29.97#ibcon#about to read 6, iclass 4, count 2 2006.197.08:25:29.97#ibcon#read 6, iclass 4, count 2 2006.197.08:25:29.97#ibcon#end of sib2, iclass 4, count 2 2006.197.08:25:29.97#ibcon#*mode == 0, iclass 4, count 2 2006.197.08:25:29.97#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.197.08:25:29.97#ibcon#[25=AT08-07\r\n] 2006.197.08:25:29.97#ibcon#*before write, iclass 4, count 2 2006.197.08:25:29.97#ibcon#enter sib2, iclass 4, count 2 2006.197.08:25:29.97#ibcon#flushed, iclass 4, count 2 2006.197.08:25:29.97#ibcon#about to write, iclass 4, count 2 2006.197.08:25:29.97#ibcon#wrote, iclass 4, count 2 2006.197.08:25:29.97#ibcon#about to read 3, iclass 4, count 2 2006.197.08:25:30.00#ibcon#read 3, iclass 4, count 2 2006.197.08:25:30.00#ibcon#about to read 4, iclass 4, count 2 2006.197.08:25:30.00#ibcon#read 4, iclass 4, count 2 2006.197.08:25:30.00#ibcon#about to read 5, iclass 4, count 2 2006.197.08:25:30.00#ibcon#read 5, iclass 4, count 2 2006.197.08:25:30.00#ibcon#about to read 6, iclass 4, count 2 2006.197.08:25:30.00#ibcon#read 6, iclass 4, count 2 2006.197.08:25:30.00#ibcon#end of sib2, iclass 4, count 2 2006.197.08:25:30.00#ibcon#*after write, iclass 4, count 2 2006.197.08:25:30.00#ibcon#*before return 0, iclass 4, count 2 2006.197.08:25:30.00#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.197.08:25:30.00#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.197.08:25:30.00#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.197.08:25:30.00#ibcon#ireg 7 cls_cnt 0 2006.197.08:25:30.00#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.197.08:25:30.12#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.197.08:25:30.12#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.197.08:25:30.12#ibcon#enter wrdev, iclass 4, count 0 2006.197.08:25:30.12#ibcon#first serial, iclass 4, count 0 2006.197.08:25:30.12#ibcon#enter sib2, iclass 4, count 0 2006.197.08:25:30.12#ibcon#flushed, iclass 4, count 0 2006.197.08:25:30.12#ibcon#about to write, iclass 4, count 0 2006.197.08:25:30.12#ibcon#wrote, iclass 4, count 0 2006.197.08:25:30.12#ibcon#about to read 3, iclass 4, count 0 2006.197.08:25:30.14#ibcon#read 3, iclass 4, count 0 2006.197.08:25:30.14#ibcon#about to read 4, iclass 4, count 0 2006.197.08:25:30.14#ibcon#read 4, iclass 4, count 0 2006.197.08:25:30.14#ibcon#about to read 5, iclass 4, count 0 2006.197.08:25:30.14#ibcon#read 5, iclass 4, count 0 2006.197.08:25:30.14#ibcon#about to read 6, iclass 4, count 0 2006.197.08:25:30.14#ibcon#read 6, iclass 4, count 0 2006.197.08:25:30.14#ibcon#end of sib2, iclass 4, count 0 2006.197.08:25:30.14#ibcon#*mode == 0, iclass 4, count 0 2006.197.08:25:30.14#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.197.08:25:30.14#ibcon#[25=USB\r\n] 2006.197.08:25:30.14#ibcon#*before write, iclass 4, count 0 2006.197.08:25:30.14#ibcon#enter sib2, iclass 4, count 0 2006.197.08:25:30.14#ibcon#flushed, iclass 4, count 0 2006.197.08:25:30.14#ibcon#about to write, iclass 4, count 0 2006.197.08:25:30.14#ibcon#wrote, iclass 4, count 0 2006.197.08:25:30.14#ibcon#about to read 3, iclass 4, count 0 2006.197.08:25:30.17#ibcon#read 3, iclass 4, count 0 2006.197.08:25:30.17#ibcon#about to read 4, iclass 4, count 0 2006.197.08:25:30.17#ibcon#read 4, iclass 4, count 0 2006.197.08:25:30.17#ibcon#about to read 5, iclass 4, count 0 2006.197.08:25:30.17#ibcon#read 5, iclass 4, count 0 2006.197.08:25:30.17#ibcon#about to read 6, iclass 4, count 0 2006.197.08:25:30.17#ibcon#read 6, iclass 4, count 0 2006.197.08:25:30.17#ibcon#end of sib2, iclass 4, count 0 2006.197.08:25:30.17#ibcon#*after write, iclass 4, count 0 2006.197.08:25:30.17#ibcon#*before return 0, iclass 4, count 0 2006.197.08:25:30.17#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.197.08:25:30.17#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.197.08:25:30.17#ibcon#about to clear, iclass 4 cls_cnt 0 2006.197.08:25:30.17#ibcon#cleared, iclass 4 cls_cnt 0 2006.197.08:25:30.17$vc4f8/vblo=1,632.99 2006.197.08:25:30.17#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.197.08:25:30.17#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.197.08:25:30.17#ibcon#ireg 17 cls_cnt 0 2006.197.08:25:30.17#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.197.08:25:30.17#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.197.08:25:30.17#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.197.08:25:30.17#ibcon#enter wrdev, iclass 6, count 0 2006.197.08:25:30.17#ibcon#first serial, iclass 6, count 0 2006.197.08:25:30.17#ibcon#enter sib2, iclass 6, count 0 2006.197.08:25:30.17#ibcon#flushed, iclass 6, count 0 2006.197.08:25:30.17#ibcon#about to write, iclass 6, count 0 2006.197.08:25:30.17#ibcon#wrote, iclass 6, count 0 2006.197.08:25:30.17#ibcon#about to read 3, iclass 6, count 0 2006.197.08:25:30.19#ibcon#read 3, iclass 6, count 0 2006.197.08:25:30.19#ibcon#about to read 4, iclass 6, count 0 2006.197.08:25:30.19#ibcon#read 4, iclass 6, count 0 2006.197.08:25:30.19#ibcon#about to read 5, iclass 6, count 0 2006.197.08:25:30.19#ibcon#read 5, iclass 6, count 0 2006.197.08:25:30.19#ibcon#about to read 6, iclass 6, count 0 2006.197.08:25:30.19#ibcon#read 6, iclass 6, count 0 2006.197.08:25:30.19#ibcon#end of sib2, iclass 6, count 0 2006.197.08:25:30.19#ibcon#*mode == 0, iclass 6, count 0 2006.197.08:25:30.19#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.197.08:25:30.19#ibcon#[28=FRQ=01,632.99\r\n] 2006.197.08:25:30.19#ibcon#*before write, iclass 6, count 0 2006.197.08:25:30.19#ibcon#enter sib2, iclass 6, count 0 2006.197.08:25:30.19#ibcon#flushed, iclass 6, count 0 2006.197.08:25:30.19#ibcon#about to write, iclass 6, count 0 2006.197.08:25:30.19#ibcon#wrote, iclass 6, count 0 2006.197.08:25:30.19#ibcon#about to read 3, iclass 6, count 0 2006.197.08:25:30.23#ibcon#read 3, iclass 6, count 0 2006.197.08:25:30.23#ibcon#about to read 4, iclass 6, count 0 2006.197.08:25:30.23#ibcon#read 4, iclass 6, count 0 2006.197.08:25:30.23#ibcon#about to read 5, iclass 6, count 0 2006.197.08:25:30.23#ibcon#read 5, iclass 6, count 0 2006.197.08:25:30.23#ibcon#about to read 6, iclass 6, count 0 2006.197.08:25:30.23#ibcon#read 6, iclass 6, count 0 2006.197.08:25:30.23#ibcon#end of sib2, iclass 6, count 0 2006.197.08:25:30.23#ibcon#*after write, iclass 6, count 0 2006.197.08:25:30.23#ibcon#*before return 0, iclass 6, count 0 2006.197.08:25:30.23#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.197.08:25:30.23#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.197.08:25:30.23#ibcon#about to clear, iclass 6 cls_cnt 0 2006.197.08:25:30.23#ibcon#cleared, iclass 6 cls_cnt 0 2006.197.08:25:30.23$vc4f8/vb=1,4 2006.197.08:25:30.23#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.197.08:25:30.23#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.197.08:25:30.23#ibcon#ireg 11 cls_cnt 2 2006.197.08:25:30.23#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.197.08:25:30.23#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.197.08:25:30.23#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.197.08:25:30.23#ibcon#enter wrdev, iclass 10, count 2 2006.197.08:25:30.23#ibcon#first serial, iclass 10, count 2 2006.197.08:25:30.23#ibcon#enter sib2, iclass 10, count 2 2006.197.08:25:30.23#ibcon#flushed, iclass 10, count 2 2006.197.08:25:30.23#ibcon#about to write, iclass 10, count 2 2006.197.08:25:30.23#ibcon#wrote, iclass 10, count 2 2006.197.08:25:30.23#ibcon#about to read 3, iclass 10, count 2 2006.197.08:25:30.25#ibcon#read 3, iclass 10, count 2 2006.197.08:25:30.25#ibcon#about to read 4, iclass 10, count 2 2006.197.08:25:30.25#ibcon#read 4, iclass 10, count 2 2006.197.08:25:30.25#ibcon#about to read 5, iclass 10, count 2 2006.197.08:25:30.25#ibcon#read 5, iclass 10, count 2 2006.197.08:25:30.25#ibcon#about to read 6, iclass 10, count 2 2006.197.08:25:30.25#ibcon#read 6, iclass 10, count 2 2006.197.08:25:30.25#ibcon#end of sib2, iclass 10, count 2 2006.197.08:25:30.25#ibcon#*mode == 0, iclass 10, count 2 2006.197.08:25:30.25#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.197.08:25:30.25#ibcon#[27=AT01-04\r\n] 2006.197.08:25:30.25#ibcon#*before write, iclass 10, count 2 2006.197.08:25:30.25#ibcon#enter sib2, iclass 10, count 2 2006.197.08:25:30.25#ibcon#flushed, iclass 10, count 2 2006.197.08:25:30.25#ibcon#about to write, iclass 10, count 2 2006.197.08:25:30.25#ibcon#wrote, iclass 10, count 2 2006.197.08:25:30.25#ibcon#about to read 3, iclass 10, count 2 2006.197.08:25:30.28#ibcon#read 3, iclass 10, count 2 2006.197.08:25:30.28#ibcon#about to read 4, iclass 10, count 2 2006.197.08:25:30.28#ibcon#read 4, iclass 10, count 2 2006.197.08:25:30.28#ibcon#about to read 5, iclass 10, count 2 2006.197.08:25:30.28#ibcon#read 5, iclass 10, count 2 2006.197.08:25:30.28#ibcon#about to read 6, iclass 10, count 2 2006.197.08:25:30.28#ibcon#read 6, iclass 10, count 2 2006.197.08:25:30.28#ibcon#end of sib2, iclass 10, count 2 2006.197.08:25:30.28#ibcon#*after write, iclass 10, count 2 2006.197.08:25:30.28#ibcon#*before return 0, iclass 10, count 2 2006.197.08:25:30.28#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.197.08:25:30.28#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.197.08:25:30.28#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.197.08:25:30.28#ibcon#ireg 7 cls_cnt 0 2006.197.08:25:30.28#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.197.08:25:30.40#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.197.08:25:30.40#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.197.08:25:30.40#ibcon#enter wrdev, iclass 10, count 0 2006.197.08:25:30.40#ibcon#first serial, iclass 10, count 0 2006.197.08:25:30.40#ibcon#enter sib2, iclass 10, count 0 2006.197.08:25:30.40#ibcon#flushed, iclass 10, count 0 2006.197.08:25:30.40#ibcon#about to write, iclass 10, count 0 2006.197.08:25:30.40#ibcon#wrote, iclass 10, count 0 2006.197.08:25:30.40#ibcon#about to read 3, iclass 10, count 0 2006.197.08:25:30.42#ibcon#read 3, iclass 10, count 0 2006.197.08:25:30.42#ibcon#about to read 4, iclass 10, count 0 2006.197.08:25:30.42#ibcon#read 4, iclass 10, count 0 2006.197.08:25:30.42#ibcon#about to read 5, iclass 10, count 0 2006.197.08:25:30.42#ibcon#read 5, iclass 10, count 0 2006.197.08:25:30.42#ibcon#about to read 6, iclass 10, count 0 2006.197.08:25:30.42#ibcon#read 6, iclass 10, count 0 2006.197.08:25:30.42#ibcon#end of sib2, iclass 10, count 0 2006.197.08:25:30.42#ibcon#*mode == 0, iclass 10, count 0 2006.197.08:25:30.42#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.197.08:25:30.42#ibcon#[27=USB\r\n] 2006.197.08:25:30.42#ibcon#*before write, iclass 10, count 0 2006.197.08:25:30.42#ibcon#enter sib2, iclass 10, count 0 2006.197.08:25:30.42#ibcon#flushed, iclass 10, count 0 2006.197.08:25:30.42#ibcon#about to write, iclass 10, count 0 2006.197.08:25:30.42#ibcon#wrote, iclass 10, count 0 2006.197.08:25:30.42#ibcon#about to read 3, iclass 10, count 0 2006.197.08:25:30.45#ibcon#read 3, iclass 10, count 0 2006.197.08:25:30.45#ibcon#about to read 4, iclass 10, count 0 2006.197.08:25:30.45#ibcon#read 4, iclass 10, count 0 2006.197.08:25:30.45#ibcon#about to read 5, iclass 10, count 0 2006.197.08:25:30.45#ibcon#read 5, iclass 10, count 0 2006.197.08:25:30.45#ibcon#about to read 6, iclass 10, count 0 2006.197.08:25:30.45#ibcon#read 6, iclass 10, count 0 2006.197.08:25:30.45#ibcon#end of sib2, iclass 10, count 0 2006.197.08:25:30.45#ibcon#*after write, iclass 10, count 0 2006.197.08:25:30.45#ibcon#*before return 0, iclass 10, count 0 2006.197.08:25:30.45#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.197.08:25:30.45#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.197.08:25:30.45#ibcon#about to clear, iclass 10 cls_cnt 0 2006.197.08:25:30.45#ibcon#cleared, iclass 10 cls_cnt 0 2006.197.08:25:30.45$vc4f8/vblo=2,640.99 2006.197.08:25:30.45#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.197.08:25:30.45#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.197.08:25:30.45#ibcon#ireg 17 cls_cnt 0 2006.197.08:25:30.45#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.197.08:25:30.45#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.197.08:25:30.45#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.197.08:25:30.45#ibcon#enter wrdev, iclass 12, count 0 2006.197.08:25:30.45#ibcon#first serial, iclass 12, count 0 2006.197.08:25:30.45#ibcon#enter sib2, iclass 12, count 0 2006.197.08:25:30.45#ibcon#flushed, iclass 12, count 0 2006.197.08:25:30.45#ibcon#about to write, iclass 12, count 0 2006.197.08:25:30.45#ibcon#wrote, iclass 12, count 0 2006.197.08:25:30.45#ibcon#about to read 3, iclass 12, count 0 2006.197.08:25:30.47#ibcon#read 3, iclass 12, count 0 2006.197.08:25:30.47#ibcon#about to read 4, iclass 12, count 0 2006.197.08:25:30.47#ibcon#read 4, iclass 12, count 0 2006.197.08:25:30.47#ibcon#about to read 5, iclass 12, count 0 2006.197.08:25:30.47#ibcon#read 5, iclass 12, count 0 2006.197.08:25:30.47#ibcon#about to read 6, iclass 12, count 0 2006.197.08:25:30.47#ibcon#read 6, iclass 12, count 0 2006.197.08:25:30.47#ibcon#end of sib2, iclass 12, count 0 2006.197.08:25:30.47#ibcon#*mode == 0, iclass 12, count 0 2006.197.08:25:30.47#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.197.08:25:30.47#ibcon#[28=FRQ=02,640.99\r\n] 2006.197.08:25:30.47#ibcon#*before write, iclass 12, count 0 2006.197.08:25:30.47#ibcon#enter sib2, iclass 12, count 0 2006.197.08:25:30.47#ibcon#flushed, iclass 12, count 0 2006.197.08:25:30.47#ibcon#about to write, iclass 12, count 0 2006.197.08:25:30.47#ibcon#wrote, iclass 12, count 0 2006.197.08:25:30.47#ibcon#about to read 3, iclass 12, count 0 2006.197.08:25:30.51#ibcon#read 3, iclass 12, count 0 2006.197.08:25:30.51#ibcon#about to read 4, iclass 12, count 0 2006.197.08:25:30.51#ibcon#read 4, iclass 12, count 0 2006.197.08:25:30.51#ibcon#about to read 5, iclass 12, count 0 2006.197.08:25:30.51#ibcon#read 5, iclass 12, count 0 2006.197.08:25:30.51#ibcon#about to read 6, iclass 12, count 0 2006.197.08:25:30.51#ibcon#read 6, iclass 12, count 0 2006.197.08:25:30.51#ibcon#end of sib2, iclass 12, count 0 2006.197.08:25:30.51#ibcon#*after write, iclass 12, count 0 2006.197.08:25:30.51#ibcon#*before return 0, iclass 12, count 0 2006.197.08:25:30.51#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.197.08:25:30.51#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.197.08:25:30.51#ibcon#about to clear, iclass 12 cls_cnt 0 2006.197.08:25:30.51#ibcon#cleared, iclass 12 cls_cnt 0 2006.197.08:25:30.51$vc4f8/vb=2,4 2006.197.08:25:30.51#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.197.08:25:30.51#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.197.08:25:30.51#ibcon#ireg 11 cls_cnt 2 2006.197.08:25:30.51#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.197.08:25:30.57#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.197.08:25:30.57#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.197.08:25:30.57#ibcon#enter wrdev, iclass 14, count 2 2006.197.08:25:30.57#ibcon#first serial, iclass 14, count 2 2006.197.08:25:30.57#ibcon#enter sib2, iclass 14, count 2 2006.197.08:25:30.57#ibcon#flushed, iclass 14, count 2 2006.197.08:25:30.57#ibcon#about to write, iclass 14, count 2 2006.197.08:25:30.57#ibcon#wrote, iclass 14, count 2 2006.197.08:25:30.57#ibcon#about to read 3, iclass 14, count 2 2006.197.08:25:30.59#ibcon#read 3, iclass 14, count 2 2006.197.08:25:30.59#ibcon#about to read 4, iclass 14, count 2 2006.197.08:25:30.59#ibcon#read 4, iclass 14, count 2 2006.197.08:25:30.59#ibcon#about to read 5, iclass 14, count 2 2006.197.08:25:30.59#ibcon#read 5, iclass 14, count 2 2006.197.08:25:30.59#ibcon#about to read 6, iclass 14, count 2 2006.197.08:25:30.59#ibcon#read 6, iclass 14, count 2 2006.197.08:25:30.59#ibcon#end of sib2, iclass 14, count 2 2006.197.08:25:30.59#ibcon#*mode == 0, iclass 14, count 2 2006.197.08:25:30.59#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.197.08:25:30.59#ibcon#[27=AT02-04\r\n] 2006.197.08:25:30.59#ibcon#*before write, iclass 14, count 2 2006.197.08:25:30.59#ibcon#enter sib2, iclass 14, count 2 2006.197.08:25:30.59#ibcon#flushed, iclass 14, count 2 2006.197.08:25:30.59#ibcon#about to write, iclass 14, count 2 2006.197.08:25:30.59#ibcon#wrote, iclass 14, count 2 2006.197.08:25:30.59#ibcon#about to read 3, iclass 14, count 2 2006.197.08:25:30.62#ibcon#read 3, iclass 14, count 2 2006.197.08:25:30.62#ibcon#about to read 4, iclass 14, count 2 2006.197.08:25:30.62#ibcon#read 4, iclass 14, count 2 2006.197.08:25:30.62#ibcon#about to read 5, iclass 14, count 2 2006.197.08:25:30.62#ibcon#read 5, iclass 14, count 2 2006.197.08:25:30.62#ibcon#about to read 6, iclass 14, count 2 2006.197.08:25:30.62#ibcon#read 6, iclass 14, count 2 2006.197.08:25:30.62#ibcon#end of sib2, iclass 14, count 2 2006.197.08:25:30.62#ibcon#*after write, iclass 14, count 2 2006.197.08:25:30.62#ibcon#*before return 0, iclass 14, count 2 2006.197.08:25:30.62#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.197.08:25:30.62#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.197.08:25:30.62#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.197.08:25:30.62#ibcon#ireg 7 cls_cnt 0 2006.197.08:25:30.62#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.197.08:25:30.74#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.197.08:25:30.74#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.197.08:25:30.74#ibcon#enter wrdev, iclass 14, count 0 2006.197.08:25:30.74#ibcon#first serial, iclass 14, count 0 2006.197.08:25:30.74#ibcon#enter sib2, iclass 14, count 0 2006.197.08:25:30.74#ibcon#flushed, iclass 14, count 0 2006.197.08:25:30.74#ibcon#about to write, iclass 14, count 0 2006.197.08:25:30.74#ibcon#wrote, iclass 14, count 0 2006.197.08:25:30.74#ibcon#about to read 3, iclass 14, count 0 2006.197.08:25:30.76#ibcon#read 3, iclass 14, count 0 2006.197.08:25:30.76#ibcon#about to read 4, iclass 14, count 0 2006.197.08:25:30.76#ibcon#read 4, iclass 14, count 0 2006.197.08:25:30.76#ibcon#about to read 5, iclass 14, count 0 2006.197.08:25:30.76#ibcon#read 5, iclass 14, count 0 2006.197.08:25:30.76#ibcon#about to read 6, iclass 14, count 0 2006.197.08:25:30.76#ibcon#read 6, iclass 14, count 0 2006.197.08:25:30.76#ibcon#end of sib2, iclass 14, count 0 2006.197.08:25:30.76#ibcon#*mode == 0, iclass 14, count 0 2006.197.08:25:30.76#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.197.08:25:30.76#ibcon#[27=USB\r\n] 2006.197.08:25:30.76#ibcon#*before write, iclass 14, count 0 2006.197.08:25:30.76#ibcon#enter sib2, iclass 14, count 0 2006.197.08:25:30.76#ibcon#flushed, iclass 14, count 0 2006.197.08:25:30.76#ibcon#about to write, iclass 14, count 0 2006.197.08:25:30.76#ibcon#wrote, iclass 14, count 0 2006.197.08:25:30.76#ibcon#about to read 3, iclass 14, count 0 2006.197.08:25:30.79#ibcon#read 3, iclass 14, count 0 2006.197.08:25:30.79#ibcon#about to read 4, iclass 14, count 0 2006.197.08:25:30.79#ibcon#read 4, iclass 14, count 0 2006.197.08:25:30.79#ibcon#about to read 5, iclass 14, count 0 2006.197.08:25:30.79#ibcon#read 5, iclass 14, count 0 2006.197.08:25:30.79#ibcon#about to read 6, iclass 14, count 0 2006.197.08:25:30.79#ibcon#read 6, iclass 14, count 0 2006.197.08:25:30.79#ibcon#end of sib2, iclass 14, count 0 2006.197.08:25:30.79#ibcon#*after write, iclass 14, count 0 2006.197.08:25:30.79#ibcon#*before return 0, iclass 14, count 0 2006.197.08:25:30.79#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.197.08:25:30.79#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.197.08:25:30.79#ibcon#about to clear, iclass 14 cls_cnt 0 2006.197.08:25:30.79#ibcon#cleared, iclass 14 cls_cnt 0 2006.197.08:25:30.79$vc4f8/vblo=3,656.99 2006.197.08:25:30.79#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.197.08:25:30.79#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.197.08:25:30.79#ibcon#ireg 17 cls_cnt 0 2006.197.08:25:30.79#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.197.08:25:30.79#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.197.08:25:30.79#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.197.08:25:30.79#ibcon#enter wrdev, iclass 16, count 0 2006.197.08:25:30.79#ibcon#first serial, iclass 16, count 0 2006.197.08:25:30.79#ibcon#enter sib2, iclass 16, count 0 2006.197.08:25:30.79#ibcon#flushed, iclass 16, count 0 2006.197.08:25:30.79#ibcon#about to write, iclass 16, count 0 2006.197.08:25:30.79#ibcon#wrote, iclass 16, count 0 2006.197.08:25:30.79#ibcon#about to read 3, iclass 16, count 0 2006.197.08:25:30.81#ibcon#read 3, iclass 16, count 0 2006.197.08:25:30.81#ibcon#about to read 4, iclass 16, count 0 2006.197.08:25:30.81#ibcon#read 4, iclass 16, count 0 2006.197.08:25:30.81#ibcon#about to read 5, iclass 16, count 0 2006.197.08:25:30.81#ibcon#read 5, iclass 16, count 0 2006.197.08:25:30.81#ibcon#about to read 6, iclass 16, count 0 2006.197.08:25:30.81#ibcon#read 6, iclass 16, count 0 2006.197.08:25:30.81#ibcon#end of sib2, iclass 16, count 0 2006.197.08:25:30.81#ibcon#*mode == 0, iclass 16, count 0 2006.197.08:25:30.81#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.197.08:25:30.81#ibcon#[28=FRQ=03,656.99\r\n] 2006.197.08:25:30.81#ibcon#*before write, iclass 16, count 0 2006.197.08:25:30.81#ibcon#enter sib2, iclass 16, count 0 2006.197.08:25:30.81#ibcon#flushed, iclass 16, count 0 2006.197.08:25:30.81#ibcon#about to write, iclass 16, count 0 2006.197.08:25:30.81#ibcon#wrote, iclass 16, count 0 2006.197.08:25:30.81#ibcon#about to read 3, iclass 16, count 0 2006.197.08:25:30.85#ibcon#read 3, iclass 16, count 0 2006.197.08:25:30.85#ibcon#about to read 4, iclass 16, count 0 2006.197.08:25:30.85#ibcon#read 4, iclass 16, count 0 2006.197.08:25:30.85#ibcon#about to read 5, iclass 16, count 0 2006.197.08:25:30.85#ibcon#read 5, iclass 16, count 0 2006.197.08:25:30.85#ibcon#about to read 6, iclass 16, count 0 2006.197.08:25:30.85#ibcon#read 6, iclass 16, count 0 2006.197.08:25:30.85#ibcon#end of sib2, iclass 16, count 0 2006.197.08:25:30.85#ibcon#*after write, iclass 16, count 0 2006.197.08:25:30.85#ibcon#*before return 0, iclass 16, count 0 2006.197.08:25:30.85#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.197.08:25:30.85#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.197.08:25:30.85#ibcon#about to clear, iclass 16 cls_cnt 0 2006.197.08:25:30.85#ibcon#cleared, iclass 16 cls_cnt 0 2006.197.08:25:30.85$vc4f8/vb=3,4 2006.197.08:25:30.85#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.197.08:25:30.85#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.197.08:25:30.85#ibcon#ireg 11 cls_cnt 2 2006.197.08:25:30.85#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.197.08:25:30.91#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.197.08:25:30.91#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.197.08:25:30.91#ibcon#enter wrdev, iclass 18, count 2 2006.197.08:25:30.91#ibcon#first serial, iclass 18, count 2 2006.197.08:25:30.91#ibcon#enter sib2, iclass 18, count 2 2006.197.08:25:30.91#ibcon#flushed, iclass 18, count 2 2006.197.08:25:30.91#ibcon#about to write, iclass 18, count 2 2006.197.08:25:30.91#ibcon#wrote, iclass 18, count 2 2006.197.08:25:30.91#ibcon#about to read 3, iclass 18, count 2 2006.197.08:25:30.93#ibcon#read 3, iclass 18, count 2 2006.197.08:25:30.93#ibcon#about to read 4, iclass 18, count 2 2006.197.08:25:30.93#ibcon#read 4, iclass 18, count 2 2006.197.08:25:30.93#ibcon#about to read 5, iclass 18, count 2 2006.197.08:25:30.93#ibcon#read 5, iclass 18, count 2 2006.197.08:25:30.93#ibcon#about to read 6, iclass 18, count 2 2006.197.08:25:30.93#ibcon#read 6, iclass 18, count 2 2006.197.08:25:30.93#ibcon#end of sib2, iclass 18, count 2 2006.197.08:25:30.93#ibcon#*mode == 0, iclass 18, count 2 2006.197.08:25:30.93#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.197.08:25:30.93#ibcon#[27=AT03-04\r\n] 2006.197.08:25:30.93#ibcon#*before write, iclass 18, count 2 2006.197.08:25:30.93#ibcon#enter sib2, iclass 18, count 2 2006.197.08:25:30.93#ibcon#flushed, iclass 18, count 2 2006.197.08:25:30.93#ibcon#about to write, iclass 18, count 2 2006.197.08:25:30.93#ibcon#wrote, iclass 18, count 2 2006.197.08:25:30.93#ibcon#about to read 3, iclass 18, count 2 2006.197.08:25:30.96#ibcon#read 3, iclass 18, count 2 2006.197.08:25:30.96#ibcon#about to read 4, iclass 18, count 2 2006.197.08:25:30.96#ibcon#read 4, iclass 18, count 2 2006.197.08:25:30.96#ibcon#about to read 5, iclass 18, count 2 2006.197.08:25:30.96#ibcon#read 5, iclass 18, count 2 2006.197.08:25:30.96#ibcon#about to read 6, iclass 18, count 2 2006.197.08:25:30.96#ibcon#read 6, iclass 18, count 2 2006.197.08:25:30.96#ibcon#end of sib2, iclass 18, count 2 2006.197.08:25:30.96#ibcon#*after write, iclass 18, count 2 2006.197.08:25:30.96#ibcon#*before return 0, iclass 18, count 2 2006.197.08:25:30.96#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.197.08:25:30.96#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.197.08:25:30.96#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.197.08:25:30.96#ibcon#ireg 7 cls_cnt 0 2006.197.08:25:30.96#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.197.08:25:31.08#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.197.08:25:31.08#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.197.08:25:31.08#ibcon#enter wrdev, iclass 18, count 0 2006.197.08:25:31.08#ibcon#first serial, iclass 18, count 0 2006.197.08:25:31.08#ibcon#enter sib2, iclass 18, count 0 2006.197.08:25:31.08#ibcon#flushed, iclass 18, count 0 2006.197.08:25:31.08#ibcon#about to write, iclass 18, count 0 2006.197.08:25:31.08#ibcon#wrote, iclass 18, count 0 2006.197.08:25:31.08#ibcon#about to read 3, iclass 18, count 0 2006.197.08:25:31.10#ibcon#read 3, iclass 18, count 0 2006.197.08:25:31.10#ibcon#about to read 4, iclass 18, count 0 2006.197.08:25:31.10#ibcon#read 4, iclass 18, count 0 2006.197.08:25:31.10#ibcon#about to read 5, iclass 18, count 0 2006.197.08:25:31.10#ibcon#read 5, iclass 18, count 0 2006.197.08:25:31.10#ibcon#about to read 6, iclass 18, count 0 2006.197.08:25:31.10#ibcon#read 6, iclass 18, count 0 2006.197.08:25:31.10#ibcon#end of sib2, iclass 18, count 0 2006.197.08:25:31.10#ibcon#*mode == 0, iclass 18, count 0 2006.197.08:25:31.10#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.197.08:25:31.10#ibcon#[27=USB\r\n] 2006.197.08:25:31.10#ibcon#*before write, iclass 18, count 0 2006.197.08:25:31.10#ibcon#enter sib2, iclass 18, count 0 2006.197.08:25:31.10#ibcon#flushed, iclass 18, count 0 2006.197.08:25:31.10#ibcon#about to write, iclass 18, count 0 2006.197.08:25:31.10#ibcon#wrote, iclass 18, count 0 2006.197.08:25:31.10#ibcon#about to read 3, iclass 18, count 0 2006.197.08:25:31.13#ibcon#read 3, iclass 18, count 0 2006.197.08:25:31.13#ibcon#about to read 4, iclass 18, count 0 2006.197.08:25:31.13#ibcon#read 4, iclass 18, count 0 2006.197.08:25:31.13#ibcon#about to read 5, iclass 18, count 0 2006.197.08:25:31.13#ibcon#read 5, iclass 18, count 0 2006.197.08:25:31.13#ibcon#about to read 6, iclass 18, count 0 2006.197.08:25:31.13#ibcon#read 6, iclass 18, count 0 2006.197.08:25:31.13#ibcon#end of sib2, iclass 18, count 0 2006.197.08:25:31.13#ibcon#*after write, iclass 18, count 0 2006.197.08:25:31.13#ibcon#*before return 0, iclass 18, count 0 2006.197.08:25:31.13#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.197.08:25:31.13#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.197.08:25:31.13#ibcon#about to clear, iclass 18 cls_cnt 0 2006.197.08:25:31.13#ibcon#cleared, iclass 18 cls_cnt 0 2006.197.08:25:31.13$vc4f8/vblo=4,712.99 2006.197.08:25:31.13#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.197.08:25:31.13#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.197.08:25:31.13#ibcon#ireg 17 cls_cnt 0 2006.197.08:25:31.13#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.197.08:25:31.13#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.197.08:25:31.13#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.197.08:25:31.13#ibcon#enter wrdev, iclass 20, count 0 2006.197.08:25:31.13#ibcon#first serial, iclass 20, count 0 2006.197.08:25:31.13#ibcon#enter sib2, iclass 20, count 0 2006.197.08:25:31.13#ibcon#flushed, iclass 20, count 0 2006.197.08:25:31.13#ibcon#about to write, iclass 20, count 0 2006.197.08:25:31.13#ibcon#wrote, iclass 20, count 0 2006.197.08:25:31.13#ibcon#about to read 3, iclass 20, count 0 2006.197.08:25:31.15#ibcon#read 3, iclass 20, count 0 2006.197.08:25:31.15#ibcon#about to read 4, iclass 20, count 0 2006.197.08:25:31.15#ibcon#read 4, iclass 20, count 0 2006.197.08:25:31.15#ibcon#about to read 5, iclass 20, count 0 2006.197.08:25:31.15#ibcon#read 5, iclass 20, count 0 2006.197.08:25:31.15#ibcon#about to read 6, iclass 20, count 0 2006.197.08:25:31.15#ibcon#read 6, iclass 20, count 0 2006.197.08:25:31.15#ibcon#end of sib2, iclass 20, count 0 2006.197.08:25:31.15#ibcon#*mode == 0, iclass 20, count 0 2006.197.08:25:31.15#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.197.08:25:31.15#ibcon#[28=FRQ=04,712.99\r\n] 2006.197.08:25:31.15#ibcon#*before write, iclass 20, count 0 2006.197.08:25:31.15#ibcon#enter sib2, iclass 20, count 0 2006.197.08:25:31.15#ibcon#flushed, iclass 20, count 0 2006.197.08:25:31.15#ibcon#about to write, iclass 20, count 0 2006.197.08:25:31.15#ibcon#wrote, iclass 20, count 0 2006.197.08:25:31.15#ibcon#about to read 3, iclass 20, count 0 2006.197.08:25:31.19#ibcon#read 3, iclass 20, count 0 2006.197.08:25:31.19#ibcon#about to read 4, iclass 20, count 0 2006.197.08:25:31.19#ibcon#read 4, iclass 20, count 0 2006.197.08:25:31.19#ibcon#about to read 5, iclass 20, count 0 2006.197.08:25:31.19#ibcon#read 5, iclass 20, count 0 2006.197.08:25:31.19#ibcon#about to read 6, iclass 20, count 0 2006.197.08:25:31.19#ibcon#read 6, iclass 20, count 0 2006.197.08:25:31.19#ibcon#end of sib2, iclass 20, count 0 2006.197.08:25:31.19#ibcon#*after write, iclass 20, count 0 2006.197.08:25:31.19#ibcon#*before return 0, iclass 20, count 0 2006.197.08:25:31.19#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.197.08:25:31.19#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.197.08:25:31.19#ibcon#about to clear, iclass 20 cls_cnt 0 2006.197.08:25:31.19#ibcon#cleared, iclass 20 cls_cnt 0 2006.197.08:25:31.19$vc4f8/vb=4,4 2006.197.08:25:31.19#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.197.08:25:31.19#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.197.08:25:31.19#ibcon#ireg 11 cls_cnt 2 2006.197.08:25:31.19#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.197.08:25:31.25#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.197.08:25:31.25#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.197.08:25:31.25#ibcon#enter wrdev, iclass 22, count 2 2006.197.08:25:31.25#ibcon#first serial, iclass 22, count 2 2006.197.08:25:31.25#ibcon#enter sib2, iclass 22, count 2 2006.197.08:25:31.25#ibcon#flushed, iclass 22, count 2 2006.197.08:25:31.25#ibcon#about to write, iclass 22, count 2 2006.197.08:25:31.25#ibcon#wrote, iclass 22, count 2 2006.197.08:25:31.25#ibcon#about to read 3, iclass 22, count 2 2006.197.08:25:31.27#ibcon#read 3, iclass 22, count 2 2006.197.08:25:31.27#ibcon#about to read 4, iclass 22, count 2 2006.197.08:25:31.27#ibcon#read 4, iclass 22, count 2 2006.197.08:25:31.27#ibcon#about to read 5, iclass 22, count 2 2006.197.08:25:31.27#ibcon#read 5, iclass 22, count 2 2006.197.08:25:31.27#ibcon#about to read 6, iclass 22, count 2 2006.197.08:25:31.27#ibcon#read 6, iclass 22, count 2 2006.197.08:25:31.27#ibcon#end of sib2, iclass 22, count 2 2006.197.08:25:31.27#ibcon#*mode == 0, iclass 22, count 2 2006.197.08:25:31.27#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.197.08:25:31.27#ibcon#[27=AT04-04\r\n] 2006.197.08:25:31.27#ibcon#*before write, iclass 22, count 2 2006.197.08:25:31.27#ibcon#enter sib2, iclass 22, count 2 2006.197.08:25:31.27#ibcon#flushed, iclass 22, count 2 2006.197.08:25:31.27#ibcon#about to write, iclass 22, count 2 2006.197.08:25:31.27#ibcon#wrote, iclass 22, count 2 2006.197.08:25:31.27#ibcon#about to read 3, iclass 22, count 2 2006.197.08:25:31.30#ibcon#read 3, iclass 22, count 2 2006.197.08:25:31.30#ibcon#about to read 4, iclass 22, count 2 2006.197.08:25:31.30#ibcon#read 4, iclass 22, count 2 2006.197.08:25:31.30#ibcon#about to read 5, iclass 22, count 2 2006.197.08:25:31.30#ibcon#read 5, iclass 22, count 2 2006.197.08:25:31.30#ibcon#about to read 6, iclass 22, count 2 2006.197.08:25:31.30#ibcon#read 6, iclass 22, count 2 2006.197.08:25:31.30#ibcon#end of sib2, iclass 22, count 2 2006.197.08:25:31.30#ibcon#*after write, iclass 22, count 2 2006.197.08:25:31.30#ibcon#*before return 0, iclass 22, count 2 2006.197.08:25:31.30#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.197.08:25:31.30#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.197.08:25:31.30#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.197.08:25:31.30#ibcon#ireg 7 cls_cnt 0 2006.197.08:25:31.30#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.197.08:25:31.42#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.197.08:25:31.42#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.197.08:25:31.42#ibcon#enter wrdev, iclass 22, count 0 2006.197.08:25:31.42#ibcon#first serial, iclass 22, count 0 2006.197.08:25:31.42#ibcon#enter sib2, iclass 22, count 0 2006.197.08:25:31.42#ibcon#flushed, iclass 22, count 0 2006.197.08:25:31.42#ibcon#about to write, iclass 22, count 0 2006.197.08:25:31.42#ibcon#wrote, iclass 22, count 0 2006.197.08:25:31.42#ibcon#about to read 3, iclass 22, count 0 2006.197.08:25:31.44#ibcon#read 3, iclass 22, count 0 2006.197.08:25:31.44#ibcon#about to read 4, iclass 22, count 0 2006.197.08:25:31.44#ibcon#read 4, iclass 22, count 0 2006.197.08:25:31.44#ibcon#about to read 5, iclass 22, count 0 2006.197.08:25:31.44#ibcon#read 5, iclass 22, count 0 2006.197.08:25:31.44#ibcon#about to read 6, iclass 22, count 0 2006.197.08:25:31.44#ibcon#read 6, iclass 22, count 0 2006.197.08:25:31.44#ibcon#end of sib2, iclass 22, count 0 2006.197.08:25:31.44#ibcon#*mode == 0, iclass 22, count 0 2006.197.08:25:31.44#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.197.08:25:31.44#ibcon#[27=USB\r\n] 2006.197.08:25:31.44#ibcon#*before write, iclass 22, count 0 2006.197.08:25:31.44#ibcon#enter sib2, iclass 22, count 0 2006.197.08:25:31.44#ibcon#flushed, iclass 22, count 0 2006.197.08:25:31.44#ibcon#about to write, iclass 22, count 0 2006.197.08:25:31.44#ibcon#wrote, iclass 22, count 0 2006.197.08:25:31.44#ibcon#about to read 3, iclass 22, count 0 2006.197.08:25:31.47#ibcon#read 3, iclass 22, count 0 2006.197.08:25:31.47#ibcon#about to read 4, iclass 22, count 0 2006.197.08:25:31.47#ibcon#read 4, iclass 22, count 0 2006.197.08:25:31.47#ibcon#about to read 5, iclass 22, count 0 2006.197.08:25:31.47#ibcon#read 5, iclass 22, count 0 2006.197.08:25:31.47#ibcon#about to read 6, iclass 22, count 0 2006.197.08:25:31.47#ibcon#read 6, iclass 22, count 0 2006.197.08:25:31.47#ibcon#end of sib2, iclass 22, count 0 2006.197.08:25:31.47#ibcon#*after write, iclass 22, count 0 2006.197.08:25:31.47#ibcon#*before return 0, iclass 22, count 0 2006.197.08:25:31.47#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.197.08:25:31.47#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.197.08:25:31.47#ibcon#about to clear, iclass 22 cls_cnt 0 2006.197.08:25:31.47#ibcon#cleared, iclass 22 cls_cnt 0 2006.197.08:25:31.47$vc4f8/vblo=5,744.99 2006.197.08:25:31.47#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.197.08:25:31.47#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.197.08:25:31.47#ibcon#ireg 17 cls_cnt 0 2006.197.08:25:31.47#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.197.08:25:31.47#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.197.08:25:31.47#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.197.08:25:31.47#ibcon#enter wrdev, iclass 24, count 0 2006.197.08:25:31.47#ibcon#first serial, iclass 24, count 0 2006.197.08:25:31.47#ibcon#enter sib2, iclass 24, count 0 2006.197.08:25:31.47#ibcon#flushed, iclass 24, count 0 2006.197.08:25:31.47#ibcon#about to write, iclass 24, count 0 2006.197.08:25:31.47#ibcon#wrote, iclass 24, count 0 2006.197.08:25:31.47#ibcon#about to read 3, iclass 24, count 0 2006.197.08:25:31.49#ibcon#read 3, iclass 24, count 0 2006.197.08:25:31.49#ibcon#about to read 4, iclass 24, count 0 2006.197.08:25:31.49#ibcon#read 4, iclass 24, count 0 2006.197.08:25:31.49#ibcon#about to read 5, iclass 24, count 0 2006.197.08:25:31.49#ibcon#read 5, iclass 24, count 0 2006.197.08:25:31.49#ibcon#about to read 6, iclass 24, count 0 2006.197.08:25:31.49#ibcon#read 6, iclass 24, count 0 2006.197.08:25:31.49#ibcon#end of sib2, iclass 24, count 0 2006.197.08:25:31.49#ibcon#*mode == 0, iclass 24, count 0 2006.197.08:25:31.49#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.197.08:25:31.49#ibcon#[28=FRQ=05,744.99\r\n] 2006.197.08:25:31.49#ibcon#*before write, iclass 24, count 0 2006.197.08:25:31.49#ibcon#enter sib2, iclass 24, count 0 2006.197.08:25:31.49#ibcon#flushed, iclass 24, count 0 2006.197.08:25:31.49#ibcon#about to write, iclass 24, count 0 2006.197.08:25:31.49#ibcon#wrote, iclass 24, count 0 2006.197.08:25:31.49#ibcon#about to read 3, iclass 24, count 0 2006.197.08:25:31.53#ibcon#read 3, iclass 24, count 0 2006.197.08:25:31.53#ibcon#about to read 4, iclass 24, count 0 2006.197.08:25:31.53#ibcon#read 4, iclass 24, count 0 2006.197.08:25:31.53#ibcon#about to read 5, iclass 24, count 0 2006.197.08:25:31.53#ibcon#read 5, iclass 24, count 0 2006.197.08:25:31.53#ibcon#about to read 6, iclass 24, count 0 2006.197.08:25:31.53#ibcon#read 6, iclass 24, count 0 2006.197.08:25:31.53#ibcon#end of sib2, iclass 24, count 0 2006.197.08:25:31.53#ibcon#*after write, iclass 24, count 0 2006.197.08:25:31.53#ibcon#*before return 0, iclass 24, count 0 2006.197.08:25:31.53#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.197.08:25:31.53#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.197.08:25:31.53#ibcon#about to clear, iclass 24 cls_cnt 0 2006.197.08:25:31.53#ibcon#cleared, iclass 24 cls_cnt 0 2006.197.08:25:31.53$vc4f8/vb=5,4 2006.197.08:25:31.53#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.197.08:25:31.53#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.197.08:25:31.53#ibcon#ireg 11 cls_cnt 2 2006.197.08:25:31.53#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.197.08:25:31.59#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.197.08:25:31.59#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.197.08:25:31.59#ibcon#enter wrdev, iclass 26, count 2 2006.197.08:25:31.59#ibcon#first serial, iclass 26, count 2 2006.197.08:25:31.59#ibcon#enter sib2, iclass 26, count 2 2006.197.08:25:31.59#ibcon#flushed, iclass 26, count 2 2006.197.08:25:31.59#ibcon#about to write, iclass 26, count 2 2006.197.08:25:31.59#ibcon#wrote, iclass 26, count 2 2006.197.08:25:31.59#ibcon#about to read 3, iclass 26, count 2 2006.197.08:25:31.61#ibcon#read 3, iclass 26, count 2 2006.197.08:25:31.61#ibcon#about to read 4, iclass 26, count 2 2006.197.08:25:31.61#ibcon#read 4, iclass 26, count 2 2006.197.08:25:31.61#ibcon#about to read 5, iclass 26, count 2 2006.197.08:25:31.61#ibcon#read 5, iclass 26, count 2 2006.197.08:25:31.61#ibcon#about to read 6, iclass 26, count 2 2006.197.08:25:31.61#ibcon#read 6, iclass 26, count 2 2006.197.08:25:31.61#ibcon#end of sib2, iclass 26, count 2 2006.197.08:25:31.61#ibcon#*mode == 0, iclass 26, count 2 2006.197.08:25:31.61#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.197.08:25:31.61#ibcon#[27=AT05-04\r\n] 2006.197.08:25:31.61#ibcon#*before write, iclass 26, count 2 2006.197.08:25:31.61#ibcon#enter sib2, iclass 26, count 2 2006.197.08:25:31.61#ibcon#flushed, iclass 26, count 2 2006.197.08:25:31.61#ibcon#about to write, iclass 26, count 2 2006.197.08:25:31.61#ibcon#wrote, iclass 26, count 2 2006.197.08:25:31.61#ibcon#about to read 3, iclass 26, count 2 2006.197.08:25:31.64#ibcon#read 3, iclass 26, count 2 2006.197.08:25:31.64#ibcon#about to read 4, iclass 26, count 2 2006.197.08:25:31.64#ibcon#read 4, iclass 26, count 2 2006.197.08:25:31.64#ibcon#about to read 5, iclass 26, count 2 2006.197.08:25:31.64#ibcon#read 5, iclass 26, count 2 2006.197.08:25:31.64#ibcon#about to read 6, iclass 26, count 2 2006.197.08:25:31.64#ibcon#read 6, iclass 26, count 2 2006.197.08:25:31.64#ibcon#end of sib2, iclass 26, count 2 2006.197.08:25:31.64#ibcon#*after write, iclass 26, count 2 2006.197.08:25:31.64#ibcon#*before return 0, iclass 26, count 2 2006.197.08:25:31.64#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.197.08:25:31.64#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.197.08:25:31.64#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.197.08:25:31.64#ibcon#ireg 7 cls_cnt 0 2006.197.08:25:31.64#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.197.08:25:31.76#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.197.08:25:31.76#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.197.08:25:31.76#ibcon#enter wrdev, iclass 26, count 0 2006.197.08:25:31.76#ibcon#first serial, iclass 26, count 0 2006.197.08:25:31.76#ibcon#enter sib2, iclass 26, count 0 2006.197.08:25:31.76#ibcon#flushed, iclass 26, count 0 2006.197.08:25:31.76#ibcon#about to write, iclass 26, count 0 2006.197.08:25:31.76#ibcon#wrote, iclass 26, count 0 2006.197.08:25:31.76#ibcon#about to read 3, iclass 26, count 0 2006.197.08:25:31.78#ibcon#read 3, iclass 26, count 0 2006.197.08:25:31.78#ibcon#about to read 4, iclass 26, count 0 2006.197.08:25:31.78#ibcon#read 4, iclass 26, count 0 2006.197.08:25:31.78#ibcon#about to read 5, iclass 26, count 0 2006.197.08:25:31.78#ibcon#read 5, iclass 26, count 0 2006.197.08:25:31.78#ibcon#about to read 6, iclass 26, count 0 2006.197.08:25:31.78#ibcon#read 6, iclass 26, count 0 2006.197.08:25:31.78#ibcon#end of sib2, iclass 26, count 0 2006.197.08:25:31.78#ibcon#*mode == 0, iclass 26, count 0 2006.197.08:25:31.78#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.197.08:25:31.78#ibcon#[27=USB\r\n] 2006.197.08:25:31.78#ibcon#*before write, iclass 26, count 0 2006.197.08:25:31.78#ibcon#enter sib2, iclass 26, count 0 2006.197.08:25:31.78#ibcon#flushed, iclass 26, count 0 2006.197.08:25:31.78#ibcon#about to write, iclass 26, count 0 2006.197.08:25:31.78#ibcon#wrote, iclass 26, count 0 2006.197.08:25:31.78#ibcon#about to read 3, iclass 26, count 0 2006.197.08:25:31.81#ibcon#read 3, iclass 26, count 0 2006.197.08:25:31.81#ibcon#about to read 4, iclass 26, count 0 2006.197.08:25:31.81#ibcon#read 4, iclass 26, count 0 2006.197.08:25:31.81#ibcon#about to read 5, iclass 26, count 0 2006.197.08:25:31.81#ibcon#read 5, iclass 26, count 0 2006.197.08:25:31.81#ibcon#about to read 6, iclass 26, count 0 2006.197.08:25:31.81#ibcon#read 6, iclass 26, count 0 2006.197.08:25:31.81#ibcon#end of sib2, iclass 26, count 0 2006.197.08:25:31.81#ibcon#*after write, iclass 26, count 0 2006.197.08:25:31.81#ibcon#*before return 0, iclass 26, count 0 2006.197.08:25:31.81#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.197.08:25:31.81#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.197.08:25:31.81#ibcon#about to clear, iclass 26 cls_cnt 0 2006.197.08:25:31.81#ibcon#cleared, iclass 26 cls_cnt 0 2006.197.08:25:31.81$vc4f8/vblo=6,752.99 2006.197.08:25:31.81#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.197.08:25:31.81#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.197.08:25:31.81#ibcon#ireg 17 cls_cnt 0 2006.197.08:25:31.81#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.197.08:25:31.81#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.197.08:25:31.81#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.197.08:25:31.81#ibcon#enter wrdev, iclass 28, count 0 2006.197.08:25:31.81#ibcon#first serial, iclass 28, count 0 2006.197.08:25:31.81#ibcon#enter sib2, iclass 28, count 0 2006.197.08:25:31.81#ibcon#flushed, iclass 28, count 0 2006.197.08:25:31.81#ibcon#about to write, iclass 28, count 0 2006.197.08:25:31.81#ibcon#wrote, iclass 28, count 0 2006.197.08:25:31.81#ibcon#about to read 3, iclass 28, count 0 2006.197.08:25:31.83#ibcon#read 3, iclass 28, count 0 2006.197.08:25:31.83#ibcon#about to read 4, iclass 28, count 0 2006.197.08:25:31.83#ibcon#read 4, iclass 28, count 0 2006.197.08:25:31.83#ibcon#about to read 5, iclass 28, count 0 2006.197.08:25:31.83#ibcon#read 5, iclass 28, count 0 2006.197.08:25:31.83#ibcon#about to read 6, iclass 28, count 0 2006.197.08:25:31.83#ibcon#read 6, iclass 28, count 0 2006.197.08:25:31.83#ibcon#end of sib2, iclass 28, count 0 2006.197.08:25:31.83#ibcon#*mode == 0, iclass 28, count 0 2006.197.08:25:31.83#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.197.08:25:31.83#ibcon#[28=FRQ=06,752.99\r\n] 2006.197.08:25:31.83#ibcon#*before write, iclass 28, count 0 2006.197.08:25:31.83#ibcon#enter sib2, iclass 28, count 0 2006.197.08:25:31.83#ibcon#flushed, iclass 28, count 0 2006.197.08:25:31.83#ibcon#about to write, iclass 28, count 0 2006.197.08:25:31.83#ibcon#wrote, iclass 28, count 0 2006.197.08:25:31.83#ibcon#about to read 3, iclass 28, count 0 2006.197.08:25:31.87#ibcon#read 3, iclass 28, count 0 2006.197.08:25:31.87#ibcon#about to read 4, iclass 28, count 0 2006.197.08:25:31.87#ibcon#read 4, iclass 28, count 0 2006.197.08:25:31.87#ibcon#about to read 5, iclass 28, count 0 2006.197.08:25:31.87#ibcon#read 5, iclass 28, count 0 2006.197.08:25:31.87#ibcon#about to read 6, iclass 28, count 0 2006.197.08:25:31.87#ibcon#read 6, iclass 28, count 0 2006.197.08:25:31.87#ibcon#end of sib2, iclass 28, count 0 2006.197.08:25:31.87#ibcon#*after write, iclass 28, count 0 2006.197.08:25:31.87#ibcon#*before return 0, iclass 28, count 0 2006.197.08:25:31.87#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.197.08:25:31.87#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.197.08:25:31.87#ibcon#about to clear, iclass 28 cls_cnt 0 2006.197.08:25:31.87#ibcon#cleared, iclass 28 cls_cnt 0 2006.197.08:25:31.87$vc4f8/vb=6,4 2006.197.08:25:31.87#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.197.08:25:31.87#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.197.08:25:31.87#ibcon#ireg 11 cls_cnt 2 2006.197.08:25:31.87#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.197.08:25:31.93#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.197.08:25:31.93#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.197.08:25:31.93#ibcon#enter wrdev, iclass 30, count 2 2006.197.08:25:31.93#ibcon#first serial, iclass 30, count 2 2006.197.08:25:31.93#ibcon#enter sib2, iclass 30, count 2 2006.197.08:25:31.93#ibcon#flushed, iclass 30, count 2 2006.197.08:25:31.93#ibcon#about to write, iclass 30, count 2 2006.197.08:25:31.93#ibcon#wrote, iclass 30, count 2 2006.197.08:25:31.93#ibcon#about to read 3, iclass 30, count 2 2006.197.08:25:31.95#ibcon#read 3, iclass 30, count 2 2006.197.08:25:31.95#ibcon#about to read 4, iclass 30, count 2 2006.197.08:25:31.95#ibcon#read 4, iclass 30, count 2 2006.197.08:25:31.95#ibcon#about to read 5, iclass 30, count 2 2006.197.08:25:31.95#ibcon#read 5, iclass 30, count 2 2006.197.08:25:31.95#ibcon#about to read 6, iclass 30, count 2 2006.197.08:25:31.95#ibcon#read 6, iclass 30, count 2 2006.197.08:25:31.95#ibcon#end of sib2, iclass 30, count 2 2006.197.08:25:31.95#ibcon#*mode == 0, iclass 30, count 2 2006.197.08:25:31.95#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.197.08:25:31.95#ibcon#[27=AT06-04\r\n] 2006.197.08:25:31.95#ibcon#*before write, iclass 30, count 2 2006.197.08:25:31.95#ibcon#enter sib2, iclass 30, count 2 2006.197.08:25:31.95#ibcon#flushed, iclass 30, count 2 2006.197.08:25:31.95#ibcon#about to write, iclass 30, count 2 2006.197.08:25:31.95#ibcon#wrote, iclass 30, count 2 2006.197.08:25:31.95#ibcon#about to read 3, iclass 30, count 2 2006.197.08:25:31.98#ibcon#read 3, iclass 30, count 2 2006.197.08:25:31.98#ibcon#about to read 4, iclass 30, count 2 2006.197.08:25:31.98#ibcon#read 4, iclass 30, count 2 2006.197.08:25:31.98#ibcon#about to read 5, iclass 30, count 2 2006.197.08:25:31.98#ibcon#read 5, iclass 30, count 2 2006.197.08:25:31.98#ibcon#about to read 6, iclass 30, count 2 2006.197.08:25:31.98#ibcon#read 6, iclass 30, count 2 2006.197.08:25:31.98#ibcon#end of sib2, iclass 30, count 2 2006.197.08:25:31.98#ibcon#*after write, iclass 30, count 2 2006.197.08:25:31.98#ibcon#*before return 0, iclass 30, count 2 2006.197.08:25:31.98#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.197.08:25:31.98#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.197.08:25:31.98#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.197.08:25:31.98#ibcon#ireg 7 cls_cnt 0 2006.197.08:25:31.98#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.197.08:25:32.10#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.197.08:25:32.10#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.197.08:25:32.10#ibcon#enter wrdev, iclass 30, count 0 2006.197.08:25:32.10#ibcon#first serial, iclass 30, count 0 2006.197.08:25:32.10#ibcon#enter sib2, iclass 30, count 0 2006.197.08:25:32.10#ibcon#flushed, iclass 30, count 0 2006.197.08:25:32.10#ibcon#about to write, iclass 30, count 0 2006.197.08:25:32.10#ibcon#wrote, iclass 30, count 0 2006.197.08:25:32.10#ibcon#about to read 3, iclass 30, count 0 2006.197.08:25:32.12#ibcon#read 3, iclass 30, count 0 2006.197.08:25:32.12#ibcon#about to read 4, iclass 30, count 0 2006.197.08:25:32.12#ibcon#read 4, iclass 30, count 0 2006.197.08:25:32.12#ibcon#about to read 5, iclass 30, count 0 2006.197.08:25:32.12#ibcon#read 5, iclass 30, count 0 2006.197.08:25:32.12#ibcon#about to read 6, iclass 30, count 0 2006.197.08:25:32.12#ibcon#read 6, iclass 30, count 0 2006.197.08:25:32.12#ibcon#end of sib2, iclass 30, count 0 2006.197.08:25:32.12#ibcon#*mode == 0, iclass 30, count 0 2006.197.08:25:32.12#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.197.08:25:32.12#ibcon#[27=USB\r\n] 2006.197.08:25:32.12#ibcon#*before write, iclass 30, count 0 2006.197.08:25:32.12#ibcon#enter sib2, iclass 30, count 0 2006.197.08:25:32.12#ibcon#flushed, iclass 30, count 0 2006.197.08:25:32.12#ibcon#about to write, iclass 30, count 0 2006.197.08:25:32.12#ibcon#wrote, iclass 30, count 0 2006.197.08:25:32.12#ibcon#about to read 3, iclass 30, count 0 2006.197.08:25:32.15#ibcon#read 3, iclass 30, count 0 2006.197.08:25:32.15#ibcon#about to read 4, iclass 30, count 0 2006.197.08:25:32.15#ibcon#read 4, iclass 30, count 0 2006.197.08:25:32.15#ibcon#about to read 5, iclass 30, count 0 2006.197.08:25:32.15#ibcon#read 5, iclass 30, count 0 2006.197.08:25:32.15#ibcon#about to read 6, iclass 30, count 0 2006.197.08:25:32.15#ibcon#read 6, iclass 30, count 0 2006.197.08:25:32.15#ibcon#end of sib2, iclass 30, count 0 2006.197.08:25:32.15#ibcon#*after write, iclass 30, count 0 2006.197.08:25:32.15#ibcon#*before return 0, iclass 30, count 0 2006.197.08:25:32.15#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.197.08:25:32.15#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.197.08:25:32.15#ibcon#about to clear, iclass 30 cls_cnt 0 2006.197.08:25:32.15#ibcon#cleared, iclass 30 cls_cnt 0 2006.197.08:25:32.15$vc4f8/vabw=wide 2006.197.08:25:32.15#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.197.08:25:32.15#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.197.08:25:32.15#ibcon#ireg 8 cls_cnt 0 2006.197.08:25:32.15#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.197.08:25:32.15#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.197.08:25:32.15#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.197.08:25:32.15#ibcon#enter wrdev, iclass 32, count 0 2006.197.08:25:32.15#ibcon#first serial, iclass 32, count 0 2006.197.08:25:32.15#ibcon#enter sib2, iclass 32, count 0 2006.197.08:25:32.15#ibcon#flushed, iclass 32, count 0 2006.197.08:25:32.15#ibcon#about to write, iclass 32, count 0 2006.197.08:25:32.15#ibcon#wrote, iclass 32, count 0 2006.197.08:25:32.15#ibcon#about to read 3, iclass 32, count 0 2006.197.08:25:32.17#ibcon#read 3, iclass 32, count 0 2006.197.08:25:32.17#ibcon#about to read 4, iclass 32, count 0 2006.197.08:25:32.17#ibcon#read 4, iclass 32, count 0 2006.197.08:25:32.17#ibcon#about to read 5, iclass 32, count 0 2006.197.08:25:32.17#ibcon#read 5, iclass 32, count 0 2006.197.08:25:32.17#ibcon#about to read 6, iclass 32, count 0 2006.197.08:25:32.17#ibcon#read 6, iclass 32, count 0 2006.197.08:25:32.17#ibcon#end of sib2, iclass 32, count 0 2006.197.08:25:32.17#ibcon#*mode == 0, iclass 32, count 0 2006.197.08:25:32.17#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.197.08:25:32.17#ibcon#[25=BW32\r\n] 2006.197.08:25:32.17#ibcon#*before write, iclass 32, count 0 2006.197.08:25:32.17#ibcon#enter sib2, iclass 32, count 0 2006.197.08:25:32.17#ibcon#flushed, iclass 32, count 0 2006.197.08:25:32.17#ibcon#about to write, iclass 32, count 0 2006.197.08:25:32.17#ibcon#wrote, iclass 32, count 0 2006.197.08:25:32.17#ibcon#about to read 3, iclass 32, count 0 2006.197.08:25:32.20#ibcon#read 3, iclass 32, count 0 2006.197.08:25:32.20#ibcon#about to read 4, iclass 32, count 0 2006.197.08:25:32.20#ibcon#read 4, iclass 32, count 0 2006.197.08:25:32.20#ibcon#about to read 5, iclass 32, count 0 2006.197.08:25:32.20#ibcon#read 5, iclass 32, count 0 2006.197.08:25:32.20#ibcon#about to read 6, iclass 32, count 0 2006.197.08:25:32.20#ibcon#read 6, iclass 32, count 0 2006.197.08:25:32.20#ibcon#end of sib2, iclass 32, count 0 2006.197.08:25:32.20#ibcon#*after write, iclass 32, count 0 2006.197.08:25:32.20#ibcon#*before return 0, iclass 32, count 0 2006.197.08:25:32.20#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.197.08:25:32.20#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.197.08:25:32.20#ibcon#about to clear, iclass 32 cls_cnt 0 2006.197.08:25:32.20#ibcon#cleared, iclass 32 cls_cnt 0 2006.197.08:25:32.20$vc4f8/vbbw=wide 2006.197.08:25:32.20#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.197.08:25:32.20#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.197.08:25:32.20#ibcon#ireg 8 cls_cnt 0 2006.197.08:25:32.20#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.197.08:25:32.27#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.197.08:25:32.27#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.197.08:25:32.27#ibcon#enter wrdev, iclass 34, count 0 2006.197.08:25:32.27#ibcon#first serial, iclass 34, count 0 2006.197.08:25:32.27#ibcon#enter sib2, iclass 34, count 0 2006.197.08:25:32.27#ibcon#flushed, iclass 34, count 0 2006.197.08:25:32.27#ibcon#about to write, iclass 34, count 0 2006.197.08:25:32.27#ibcon#wrote, iclass 34, count 0 2006.197.08:25:32.27#ibcon#about to read 3, iclass 34, count 0 2006.197.08:25:32.29#ibcon#read 3, iclass 34, count 0 2006.197.08:25:32.29#ibcon#about to read 4, iclass 34, count 0 2006.197.08:25:32.29#ibcon#read 4, iclass 34, count 0 2006.197.08:25:32.29#ibcon#about to read 5, iclass 34, count 0 2006.197.08:25:32.29#ibcon#read 5, iclass 34, count 0 2006.197.08:25:32.29#ibcon#about to read 6, iclass 34, count 0 2006.197.08:25:32.29#ibcon#read 6, iclass 34, count 0 2006.197.08:25:32.29#ibcon#end of sib2, iclass 34, count 0 2006.197.08:25:32.29#ibcon#*mode == 0, iclass 34, count 0 2006.197.08:25:32.29#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.197.08:25:32.29#ibcon#[27=BW32\r\n] 2006.197.08:25:32.29#ibcon#*before write, iclass 34, count 0 2006.197.08:25:32.29#ibcon#enter sib2, iclass 34, count 0 2006.197.08:25:32.29#ibcon#flushed, iclass 34, count 0 2006.197.08:25:32.29#ibcon#about to write, iclass 34, count 0 2006.197.08:25:32.29#ibcon#wrote, iclass 34, count 0 2006.197.08:25:32.29#ibcon#about to read 3, iclass 34, count 0 2006.197.08:25:32.32#ibcon#read 3, iclass 34, count 0 2006.197.08:25:32.32#ibcon#about to read 4, iclass 34, count 0 2006.197.08:25:32.32#ibcon#read 4, iclass 34, count 0 2006.197.08:25:32.32#ibcon#about to read 5, iclass 34, count 0 2006.197.08:25:32.32#ibcon#read 5, iclass 34, count 0 2006.197.08:25:32.32#ibcon#about to read 6, iclass 34, count 0 2006.197.08:25:32.32#ibcon#read 6, iclass 34, count 0 2006.197.08:25:32.32#ibcon#end of sib2, iclass 34, count 0 2006.197.08:25:32.32#ibcon#*after write, iclass 34, count 0 2006.197.08:25:32.32#ibcon#*before return 0, iclass 34, count 0 2006.197.08:25:32.32#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.197.08:25:32.32#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.197.08:25:32.32#ibcon#about to clear, iclass 34 cls_cnt 0 2006.197.08:25:32.32#ibcon#cleared, iclass 34 cls_cnt 0 2006.197.08:25:32.32$4f8m12a/ifd4f 2006.197.08:25:32.32$ifd4f/lo= 2006.197.08:25:32.32$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.197.08:25:32.32$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.197.08:25:32.32$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.197.08:25:32.32$ifd4f/patch= 2006.197.08:25:32.32$ifd4f/patch=lo1,a1,a2,a3,a4 2006.197.08:25:32.32$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.197.08:25:32.32$ifd4f/patch=lo3,a5,a6,a7,a8 2006.197.08:25:32.32$4f8m12a/"form=m,16.000,1:2 2006.197.08:25:32.32$4f8m12a/"tpicd 2006.197.08:25:32.32$4f8m12a/echo=off 2006.197.08:25:32.32$4f8m12a/xlog=off 2006.197.08:25:32.32:!2006.197.08:26:40 2006.197.08:26:16.14#trakl#Source acquired 2006.197.08:26:18.14#flagr#flagr/antenna,acquired 2006.197.08:26:40.00:preob 2006.197.08:26:40.14/onsource/TRACKING 2006.197.08:26:40.14:!2006.197.08:26:50 2006.197.08:26:50.00:data_valid=on 2006.197.08:26:50.00:midob 2006.197.08:26:51.14/onsource/TRACKING 2006.197.08:26:51.14/wx/25.50,1003.0,96 2006.197.08:26:51.34/cable/+6.3720E-03 2006.197.08:26:52.43/va/01,08,usb,yes,32,34 2006.197.08:26:52.43/va/02,07,usb,yes,33,34 2006.197.08:26:52.43/va/03,06,usb,yes,34,34 2006.197.08:26:52.43/va/04,07,usb,yes,34,36 2006.197.08:26:52.43/va/05,07,usb,yes,38,40 2006.197.08:26:52.43/va/06,06,usb,yes,37,37 2006.197.08:26:52.43/va/07,06,usb,yes,37,37 2006.197.08:26:52.43/va/08,07,usb,yes,35,35 2006.197.08:26:52.66/valo/01,532.99,yes,locked 2006.197.08:26:52.66/valo/02,572.99,yes,locked 2006.197.08:26:52.66/valo/03,672.99,yes,locked 2006.197.08:26:52.66/valo/04,832.99,yes,locked 2006.197.08:26:52.66/valo/05,652.99,yes,locked 2006.197.08:26:52.66/valo/06,772.99,yes,locked 2006.197.08:26:52.66/valo/07,832.99,yes,locked 2006.197.08:26:52.66/valo/08,852.99,yes,locked 2006.197.08:26:53.75/vb/01,04,usb,yes,25,24 2006.197.08:26:53.75/vb/02,04,usb,yes,27,29 2006.197.08:26:53.75/vb/03,04,usb,yes,23,27 2006.197.08:26:53.75/vb/04,04,usb,yes,24,24 2006.197.08:26:53.75/vb/05,04,usb,yes,23,27 2006.197.08:26:53.75/vb/06,04,usb,yes,24,26 2006.197.08:26:53.75/vb/07,04,usb,yes,26,26 2006.197.08:26:53.75/vb/08,04,usb,yes,24,27 2006.197.08:26:53.99/vblo/01,632.99,yes,locked 2006.197.08:26:53.99/vblo/02,640.99,yes,locked 2006.197.08:26:53.99/vblo/03,656.99,yes,locked 2006.197.08:26:53.99/vblo/04,712.99,yes,locked 2006.197.08:26:53.99/vblo/05,744.99,yes,locked 2006.197.08:26:53.99/vblo/06,752.99,yes,locked 2006.197.08:26:53.99/vblo/07,734.99,yes,locked 2006.197.08:26:53.99/vblo/08,744.99,yes,locked 2006.197.08:26:54.14/vabw/8 2006.197.08:26:54.29/vbbw/8 2006.197.08:26:54.38/xfe/off,on,15.2 2006.197.08:26:54.77/ifatt/23,28,28,28 2006.197.08:26:55.10/fmout-gps/S +3.00E-07 2006.197.08:26:55.13:!2006.197.08:27:50 2006.197.08:27:50.00:data_valid=off 2006.197.08:27:50.00:postob 2006.197.08:27:50.10/cable/+6.3730E-03 2006.197.08:27:50.10/wx/25.50,1003.0,96 2006.197.08:27:51.10/fmout-gps/S +2.99E-07 2006.197.08:27:51.10:scan_name=197-0828,k06197,60 2006.197.08:27:51.10:source=0955+476,095819.67,472507.8,2000.0,ccw 2006.197.08:27:51.14#flagr#flagr/antenna,new-source 2006.197.08:27:52.14:checkk5 2006.197.08:27:52.48/chk_autoobs//k5ts1/ autoobs is running! 2006.197.08:27:52.82/chk_autoobs//k5ts2/ autoobs is running! 2006.197.08:27:53.17/chk_autoobs//k5ts3/ autoobs is running! 2006.197.08:27:53.51/chk_autoobs//k5ts4/ autoobs is running! 2006.197.08:27:53.84/chk_obsdata//k5ts1/T1970826??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.08:27:54.18/chk_obsdata//k5ts2/T1970826??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.08:27:54.51/chk_obsdata//k5ts3/T1970826??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.08:27:54.84/chk_obsdata//k5ts4/T1970826??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.08:27:55.50/k5log//k5ts1_log_newline 2006.197.08:27:56.16/k5log//k5ts2_log_newline 2006.197.08:27:56.82/k5log//k5ts3_log_newline 2006.197.08:27:57.47/k5log//k5ts4_log_newline 2006.197.08:27:57.49/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.197.08:27:57.49:4f8m12a=3 2006.197.08:27:57.49$4f8m12a/echo=on 2006.197.08:27:57.49$4f8m12a/pcalon 2006.197.08:27:57.49$pcalon/"no phase cal control is implemented here 2006.197.08:27:57.49$4f8m12a/"tpicd=stop 2006.197.08:27:57.49$4f8m12a/vc4f8 2006.197.08:27:57.49$vc4f8/valo=1,532.99 2006.197.08:27:57.50#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.197.08:27:57.50#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.197.08:27:57.50#ibcon#ireg 17 cls_cnt 0 2006.197.08:27:57.50#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.197.08:27:57.50#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.197.08:27:57.50#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.197.08:27:57.50#ibcon#enter wrdev, iclass 21, count 0 2006.197.08:27:57.50#ibcon#first serial, iclass 21, count 0 2006.197.08:27:57.50#ibcon#enter sib2, iclass 21, count 0 2006.197.08:27:57.50#ibcon#flushed, iclass 21, count 0 2006.197.08:27:57.50#ibcon#about to write, iclass 21, count 0 2006.197.08:27:57.50#ibcon#wrote, iclass 21, count 0 2006.197.08:27:57.50#ibcon#about to read 3, iclass 21, count 0 2006.197.08:27:57.52#ibcon#read 3, iclass 21, count 0 2006.197.08:27:57.52#ibcon#about to read 4, iclass 21, count 0 2006.197.08:27:57.52#ibcon#read 4, iclass 21, count 0 2006.197.08:27:57.52#ibcon#about to read 5, iclass 21, count 0 2006.197.08:27:57.52#ibcon#read 5, iclass 21, count 0 2006.197.08:27:57.52#ibcon#about to read 6, iclass 21, count 0 2006.197.08:27:57.52#ibcon#read 6, iclass 21, count 0 2006.197.08:27:57.52#ibcon#end of sib2, iclass 21, count 0 2006.197.08:27:57.52#ibcon#*mode == 0, iclass 21, count 0 2006.197.08:27:57.52#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.197.08:27:57.52#ibcon#[26=FRQ=01,532.99\r\n] 2006.197.08:27:57.52#ibcon#*before write, iclass 21, count 0 2006.197.08:27:57.52#ibcon#enter sib2, iclass 21, count 0 2006.197.08:27:57.52#ibcon#flushed, iclass 21, count 0 2006.197.08:27:57.52#ibcon#about to write, iclass 21, count 0 2006.197.08:27:57.52#ibcon#wrote, iclass 21, count 0 2006.197.08:27:57.52#ibcon#about to read 3, iclass 21, count 0 2006.197.08:27:57.57#ibcon#read 3, iclass 21, count 0 2006.197.08:27:57.57#ibcon#about to read 4, iclass 21, count 0 2006.197.08:27:57.57#ibcon#read 4, iclass 21, count 0 2006.197.08:27:57.57#ibcon#about to read 5, iclass 21, count 0 2006.197.08:27:57.57#ibcon#read 5, iclass 21, count 0 2006.197.08:27:57.57#ibcon#about to read 6, iclass 21, count 0 2006.197.08:27:57.57#ibcon#read 6, iclass 21, count 0 2006.197.08:27:57.57#ibcon#end of sib2, iclass 21, count 0 2006.197.08:27:57.57#ibcon#*after write, iclass 21, count 0 2006.197.08:27:57.57#ibcon#*before return 0, iclass 21, count 0 2006.197.08:27:57.57#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.197.08:27:57.57#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.197.08:27:57.57#ibcon#about to clear, iclass 21 cls_cnt 0 2006.197.08:27:57.57#ibcon#cleared, iclass 21 cls_cnt 0 2006.197.08:27:57.57$vc4f8/va=1,8 2006.197.08:27:57.57#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.197.08:27:57.57#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.197.08:27:57.57#ibcon#ireg 11 cls_cnt 2 2006.197.08:27:57.57#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.197.08:27:57.57#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.197.08:27:57.57#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.197.08:27:57.57#ibcon#enter wrdev, iclass 23, count 2 2006.197.08:27:57.57#ibcon#first serial, iclass 23, count 2 2006.197.08:27:57.57#ibcon#enter sib2, iclass 23, count 2 2006.197.08:27:57.57#ibcon#flushed, iclass 23, count 2 2006.197.08:27:57.57#ibcon#about to write, iclass 23, count 2 2006.197.08:27:57.57#ibcon#wrote, iclass 23, count 2 2006.197.08:27:57.57#ibcon#about to read 3, iclass 23, count 2 2006.197.08:27:57.59#ibcon#read 3, iclass 23, count 2 2006.197.08:27:57.59#ibcon#about to read 4, iclass 23, count 2 2006.197.08:27:57.59#ibcon#read 4, iclass 23, count 2 2006.197.08:27:57.59#ibcon#about to read 5, iclass 23, count 2 2006.197.08:27:57.59#ibcon#read 5, iclass 23, count 2 2006.197.08:27:57.59#ibcon#about to read 6, iclass 23, count 2 2006.197.08:27:57.59#ibcon#read 6, iclass 23, count 2 2006.197.08:27:57.59#ibcon#end of sib2, iclass 23, count 2 2006.197.08:27:57.59#ibcon#*mode == 0, iclass 23, count 2 2006.197.08:27:57.59#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.197.08:27:57.59#ibcon#[25=AT01-08\r\n] 2006.197.08:27:57.59#ibcon#*before write, iclass 23, count 2 2006.197.08:27:57.59#ibcon#enter sib2, iclass 23, count 2 2006.197.08:27:57.59#ibcon#flushed, iclass 23, count 2 2006.197.08:27:57.59#ibcon#about to write, iclass 23, count 2 2006.197.08:27:57.59#ibcon#wrote, iclass 23, count 2 2006.197.08:27:57.59#ibcon#about to read 3, iclass 23, count 2 2006.197.08:27:57.62#ibcon#read 3, iclass 23, count 2 2006.197.08:27:57.62#ibcon#about to read 4, iclass 23, count 2 2006.197.08:27:57.62#ibcon#read 4, iclass 23, count 2 2006.197.08:27:57.62#ibcon#about to read 5, iclass 23, count 2 2006.197.08:27:57.62#ibcon#read 5, iclass 23, count 2 2006.197.08:27:57.62#ibcon#about to read 6, iclass 23, count 2 2006.197.08:27:57.62#ibcon#read 6, iclass 23, count 2 2006.197.08:27:57.62#ibcon#end of sib2, iclass 23, count 2 2006.197.08:27:57.62#ibcon#*after write, iclass 23, count 2 2006.197.08:27:57.62#ibcon#*before return 0, iclass 23, count 2 2006.197.08:27:57.62#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.197.08:27:57.62#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.197.08:27:57.62#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.197.08:27:57.62#ibcon#ireg 7 cls_cnt 0 2006.197.08:27:57.62#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.197.08:27:57.74#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.197.08:27:57.74#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.197.08:27:57.74#ibcon#enter wrdev, iclass 23, count 0 2006.197.08:27:57.74#ibcon#first serial, iclass 23, count 0 2006.197.08:27:57.74#ibcon#enter sib2, iclass 23, count 0 2006.197.08:27:57.74#ibcon#flushed, iclass 23, count 0 2006.197.08:27:57.74#ibcon#about to write, iclass 23, count 0 2006.197.08:27:57.74#ibcon#wrote, iclass 23, count 0 2006.197.08:27:57.74#ibcon#about to read 3, iclass 23, count 0 2006.197.08:27:57.76#ibcon#read 3, iclass 23, count 0 2006.197.08:27:57.76#ibcon#about to read 4, iclass 23, count 0 2006.197.08:27:57.76#ibcon#read 4, iclass 23, count 0 2006.197.08:27:57.76#ibcon#about to read 5, iclass 23, count 0 2006.197.08:27:57.76#ibcon#read 5, iclass 23, count 0 2006.197.08:27:57.76#ibcon#about to read 6, iclass 23, count 0 2006.197.08:27:57.76#ibcon#read 6, iclass 23, count 0 2006.197.08:27:57.76#ibcon#end of sib2, iclass 23, count 0 2006.197.08:27:57.76#ibcon#*mode == 0, iclass 23, count 0 2006.197.08:27:57.76#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.197.08:27:57.76#ibcon#[25=USB\r\n] 2006.197.08:27:57.76#ibcon#*before write, iclass 23, count 0 2006.197.08:27:57.76#ibcon#enter sib2, iclass 23, count 0 2006.197.08:27:57.76#ibcon#flushed, iclass 23, count 0 2006.197.08:27:57.76#ibcon#about to write, iclass 23, count 0 2006.197.08:27:57.76#ibcon#wrote, iclass 23, count 0 2006.197.08:27:57.76#ibcon#about to read 3, iclass 23, count 0 2006.197.08:27:57.79#ibcon#read 3, iclass 23, count 0 2006.197.08:27:57.79#ibcon#about to read 4, iclass 23, count 0 2006.197.08:27:57.79#ibcon#read 4, iclass 23, count 0 2006.197.08:27:57.79#ibcon#about to read 5, iclass 23, count 0 2006.197.08:27:57.79#ibcon#read 5, iclass 23, count 0 2006.197.08:27:57.79#ibcon#about to read 6, iclass 23, count 0 2006.197.08:27:57.79#ibcon#read 6, iclass 23, count 0 2006.197.08:27:57.79#ibcon#end of sib2, iclass 23, count 0 2006.197.08:27:57.79#ibcon#*after write, iclass 23, count 0 2006.197.08:27:57.79#ibcon#*before return 0, iclass 23, count 0 2006.197.08:27:57.79#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.197.08:27:57.79#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.197.08:27:57.79#ibcon#about to clear, iclass 23 cls_cnt 0 2006.197.08:27:57.79#ibcon#cleared, iclass 23 cls_cnt 0 2006.197.08:27:57.79$vc4f8/valo=2,572.99 2006.197.08:27:57.79#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.197.08:27:57.79#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.197.08:27:57.79#ibcon#ireg 17 cls_cnt 0 2006.197.08:27:57.79#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.197.08:27:57.79#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.197.08:27:57.79#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.197.08:27:57.79#ibcon#enter wrdev, iclass 25, count 0 2006.197.08:27:57.79#ibcon#first serial, iclass 25, count 0 2006.197.08:27:57.79#ibcon#enter sib2, iclass 25, count 0 2006.197.08:27:57.79#ibcon#flushed, iclass 25, count 0 2006.197.08:27:57.79#ibcon#about to write, iclass 25, count 0 2006.197.08:27:57.79#ibcon#wrote, iclass 25, count 0 2006.197.08:27:57.79#ibcon#about to read 3, iclass 25, count 0 2006.197.08:27:57.81#ibcon#read 3, iclass 25, count 0 2006.197.08:27:57.81#ibcon#about to read 4, iclass 25, count 0 2006.197.08:27:57.81#ibcon#read 4, iclass 25, count 0 2006.197.08:27:57.81#ibcon#about to read 5, iclass 25, count 0 2006.197.08:27:57.81#ibcon#read 5, iclass 25, count 0 2006.197.08:27:57.81#ibcon#about to read 6, iclass 25, count 0 2006.197.08:27:57.81#ibcon#read 6, iclass 25, count 0 2006.197.08:27:57.81#ibcon#end of sib2, iclass 25, count 0 2006.197.08:27:57.81#ibcon#*mode == 0, iclass 25, count 0 2006.197.08:27:57.81#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.197.08:27:57.81#ibcon#[26=FRQ=02,572.99\r\n] 2006.197.08:27:57.81#ibcon#*before write, iclass 25, count 0 2006.197.08:27:57.81#ibcon#enter sib2, iclass 25, count 0 2006.197.08:27:57.81#ibcon#flushed, iclass 25, count 0 2006.197.08:27:57.81#ibcon#about to write, iclass 25, count 0 2006.197.08:27:57.81#ibcon#wrote, iclass 25, count 0 2006.197.08:27:57.81#ibcon#about to read 3, iclass 25, count 0 2006.197.08:27:57.85#ibcon#read 3, iclass 25, count 0 2006.197.08:27:57.85#ibcon#about to read 4, iclass 25, count 0 2006.197.08:27:57.85#ibcon#read 4, iclass 25, count 0 2006.197.08:27:57.85#ibcon#about to read 5, iclass 25, count 0 2006.197.08:27:57.85#ibcon#read 5, iclass 25, count 0 2006.197.08:27:57.85#ibcon#about to read 6, iclass 25, count 0 2006.197.08:27:57.85#ibcon#read 6, iclass 25, count 0 2006.197.08:27:57.85#ibcon#end of sib2, iclass 25, count 0 2006.197.08:27:57.85#ibcon#*after write, iclass 25, count 0 2006.197.08:27:57.85#ibcon#*before return 0, iclass 25, count 0 2006.197.08:27:57.85#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.197.08:27:57.85#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.197.08:27:57.85#ibcon#about to clear, iclass 25 cls_cnt 0 2006.197.08:27:57.85#ibcon#cleared, iclass 25 cls_cnt 0 2006.197.08:27:57.85$vc4f8/va=2,7 2006.197.08:27:57.85#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.197.08:27:57.85#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.197.08:27:57.85#ibcon#ireg 11 cls_cnt 2 2006.197.08:27:57.85#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.197.08:27:57.91#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.197.08:27:57.91#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.197.08:27:57.91#ibcon#enter wrdev, iclass 27, count 2 2006.197.08:27:57.91#ibcon#first serial, iclass 27, count 2 2006.197.08:27:57.91#ibcon#enter sib2, iclass 27, count 2 2006.197.08:27:57.91#ibcon#flushed, iclass 27, count 2 2006.197.08:27:57.91#ibcon#about to write, iclass 27, count 2 2006.197.08:27:57.91#ibcon#wrote, iclass 27, count 2 2006.197.08:27:57.91#ibcon#about to read 3, iclass 27, count 2 2006.197.08:27:57.93#ibcon#read 3, iclass 27, count 2 2006.197.08:27:57.93#ibcon#about to read 4, iclass 27, count 2 2006.197.08:27:57.93#ibcon#read 4, iclass 27, count 2 2006.197.08:27:57.93#ibcon#about to read 5, iclass 27, count 2 2006.197.08:27:57.93#ibcon#read 5, iclass 27, count 2 2006.197.08:27:57.93#ibcon#about to read 6, iclass 27, count 2 2006.197.08:27:57.93#ibcon#read 6, iclass 27, count 2 2006.197.08:27:57.93#ibcon#end of sib2, iclass 27, count 2 2006.197.08:27:57.93#ibcon#*mode == 0, iclass 27, count 2 2006.197.08:27:57.93#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.197.08:27:57.93#ibcon#[25=AT02-07\r\n] 2006.197.08:27:57.93#ibcon#*before write, iclass 27, count 2 2006.197.08:27:57.93#ibcon#enter sib2, iclass 27, count 2 2006.197.08:27:57.93#ibcon#flushed, iclass 27, count 2 2006.197.08:27:57.93#ibcon#about to write, iclass 27, count 2 2006.197.08:27:57.93#ibcon#wrote, iclass 27, count 2 2006.197.08:27:57.93#ibcon#about to read 3, iclass 27, count 2 2006.197.08:27:57.96#ibcon#read 3, iclass 27, count 2 2006.197.08:27:57.96#ibcon#about to read 4, iclass 27, count 2 2006.197.08:27:57.96#ibcon#read 4, iclass 27, count 2 2006.197.08:27:57.96#ibcon#about to read 5, iclass 27, count 2 2006.197.08:27:57.96#ibcon#read 5, iclass 27, count 2 2006.197.08:27:57.96#ibcon#about to read 6, iclass 27, count 2 2006.197.08:27:57.96#ibcon#read 6, iclass 27, count 2 2006.197.08:27:57.96#ibcon#end of sib2, iclass 27, count 2 2006.197.08:27:57.96#ibcon#*after write, iclass 27, count 2 2006.197.08:27:57.96#ibcon#*before return 0, iclass 27, count 2 2006.197.08:27:57.96#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.197.08:27:57.96#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.197.08:27:57.96#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.197.08:27:57.96#ibcon#ireg 7 cls_cnt 0 2006.197.08:27:57.96#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.197.08:27:58.08#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.197.08:27:58.08#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.197.08:27:58.08#ibcon#enter wrdev, iclass 27, count 0 2006.197.08:27:58.08#ibcon#first serial, iclass 27, count 0 2006.197.08:27:58.08#ibcon#enter sib2, iclass 27, count 0 2006.197.08:27:58.08#ibcon#flushed, iclass 27, count 0 2006.197.08:27:58.08#ibcon#about to write, iclass 27, count 0 2006.197.08:27:58.08#ibcon#wrote, iclass 27, count 0 2006.197.08:27:58.08#ibcon#about to read 3, iclass 27, count 0 2006.197.08:27:58.10#ibcon#read 3, iclass 27, count 0 2006.197.08:27:58.10#ibcon#about to read 4, iclass 27, count 0 2006.197.08:27:58.10#ibcon#read 4, iclass 27, count 0 2006.197.08:27:58.10#ibcon#about to read 5, iclass 27, count 0 2006.197.08:27:58.10#ibcon#read 5, iclass 27, count 0 2006.197.08:27:58.10#ibcon#about to read 6, iclass 27, count 0 2006.197.08:27:58.10#ibcon#read 6, iclass 27, count 0 2006.197.08:27:58.10#ibcon#end of sib2, iclass 27, count 0 2006.197.08:27:58.10#ibcon#*mode == 0, iclass 27, count 0 2006.197.08:27:58.10#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.197.08:27:58.10#ibcon#[25=USB\r\n] 2006.197.08:27:58.10#ibcon#*before write, iclass 27, count 0 2006.197.08:27:58.10#ibcon#enter sib2, iclass 27, count 0 2006.197.08:27:58.10#ibcon#flushed, iclass 27, count 0 2006.197.08:27:58.10#ibcon#about to write, iclass 27, count 0 2006.197.08:27:58.10#ibcon#wrote, iclass 27, count 0 2006.197.08:27:58.10#ibcon#about to read 3, iclass 27, count 0 2006.197.08:27:58.13#ibcon#read 3, iclass 27, count 0 2006.197.08:27:58.13#ibcon#about to read 4, iclass 27, count 0 2006.197.08:27:58.13#ibcon#read 4, iclass 27, count 0 2006.197.08:27:58.13#ibcon#about to read 5, iclass 27, count 0 2006.197.08:27:58.13#ibcon#read 5, iclass 27, count 0 2006.197.08:27:58.13#ibcon#about to read 6, iclass 27, count 0 2006.197.08:27:58.13#ibcon#read 6, iclass 27, count 0 2006.197.08:27:58.13#ibcon#end of sib2, iclass 27, count 0 2006.197.08:27:58.13#ibcon#*after write, iclass 27, count 0 2006.197.08:27:58.13#ibcon#*before return 0, iclass 27, count 0 2006.197.08:27:58.13#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.197.08:27:58.13#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.197.08:27:58.13#ibcon#about to clear, iclass 27 cls_cnt 0 2006.197.08:27:58.13#ibcon#cleared, iclass 27 cls_cnt 0 2006.197.08:27:58.13$vc4f8/valo=3,672.99 2006.197.08:27:58.13#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.197.08:27:58.13#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.197.08:27:58.13#ibcon#ireg 17 cls_cnt 0 2006.197.08:27:58.13#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.197.08:27:58.13#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.197.08:27:58.13#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.197.08:27:58.13#ibcon#enter wrdev, iclass 29, count 0 2006.197.08:27:58.13#ibcon#first serial, iclass 29, count 0 2006.197.08:27:58.13#ibcon#enter sib2, iclass 29, count 0 2006.197.08:27:58.13#ibcon#flushed, iclass 29, count 0 2006.197.08:27:58.13#ibcon#about to write, iclass 29, count 0 2006.197.08:27:58.13#ibcon#wrote, iclass 29, count 0 2006.197.08:27:58.13#ibcon#about to read 3, iclass 29, count 0 2006.197.08:27:58.15#ibcon#read 3, iclass 29, count 0 2006.197.08:27:58.15#ibcon#about to read 4, iclass 29, count 0 2006.197.08:27:58.15#ibcon#read 4, iclass 29, count 0 2006.197.08:27:58.15#ibcon#about to read 5, iclass 29, count 0 2006.197.08:27:58.15#ibcon#read 5, iclass 29, count 0 2006.197.08:27:58.15#ibcon#about to read 6, iclass 29, count 0 2006.197.08:27:58.15#ibcon#read 6, iclass 29, count 0 2006.197.08:27:58.15#ibcon#end of sib2, iclass 29, count 0 2006.197.08:27:58.15#ibcon#*mode == 0, iclass 29, count 0 2006.197.08:27:58.15#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.197.08:27:58.15#ibcon#[26=FRQ=03,672.99\r\n] 2006.197.08:27:58.15#ibcon#*before write, iclass 29, count 0 2006.197.08:27:58.15#ibcon#enter sib2, iclass 29, count 0 2006.197.08:27:58.15#ibcon#flushed, iclass 29, count 0 2006.197.08:27:58.15#ibcon#about to write, iclass 29, count 0 2006.197.08:27:58.15#ibcon#wrote, iclass 29, count 0 2006.197.08:27:58.15#ibcon#about to read 3, iclass 29, count 0 2006.197.08:27:58.19#ibcon#read 3, iclass 29, count 0 2006.197.08:27:58.19#ibcon#about to read 4, iclass 29, count 0 2006.197.08:27:58.19#ibcon#read 4, iclass 29, count 0 2006.197.08:27:58.19#ibcon#about to read 5, iclass 29, count 0 2006.197.08:27:58.19#ibcon#read 5, iclass 29, count 0 2006.197.08:27:58.19#ibcon#about to read 6, iclass 29, count 0 2006.197.08:27:58.19#ibcon#read 6, iclass 29, count 0 2006.197.08:27:58.19#ibcon#end of sib2, iclass 29, count 0 2006.197.08:27:58.19#ibcon#*after write, iclass 29, count 0 2006.197.08:27:58.19#ibcon#*before return 0, iclass 29, count 0 2006.197.08:27:58.19#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.197.08:27:58.19#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.197.08:27:58.19#ibcon#about to clear, iclass 29 cls_cnt 0 2006.197.08:27:58.19#ibcon#cleared, iclass 29 cls_cnt 0 2006.197.08:27:58.19$vc4f8/va=3,6 2006.197.08:27:58.19#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.197.08:27:58.19#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.197.08:27:58.19#ibcon#ireg 11 cls_cnt 2 2006.197.08:27:58.19#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.197.08:27:58.25#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.197.08:27:58.25#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.197.08:27:58.25#ibcon#enter wrdev, iclass 31, count 2 2006.197.08:27:58.25#ibcon#first serial, iclass 31, count 2 2006.197.08:27:58.25#ibcon#enter sib2, iclass 31, count 2 2006.197.08:27:58.25#ibcon#flushed, iclass 31, count 2 2006.197.08:27:58.25#ibcon#about to write, iclass 31, count 2 2006.197.08:27:58.25#ibcon#wrote, iclass 31, count 2 2006.197.08:27:58.25#ibcon#about to read 3, iclass 31, count 2 2006.197.08:27:58.27#ibcon#read 3, iclass 31, count 2 2006.197.08:27:58.27#ibcon#about to read 4, iclass 31, count 2 2006.197.08:27:58.27#ibcon#read 4, iclass 31, count 2 2006.197.08:27:58.27#ibcon#about to read 5, iclass 31, count 2 2006.197.08:27:58.27#ibcon#read 5, iclass 31, count 2 2006.197.08:27:58.27#ibcon#about to read 6, iclass 31, count 2 2006.197.08:27:58.27#ibcon#read 6, iclass 31, count 2 2006.197.08:27:58.27#ibcon#end of sib2, iclass 31, count 2 2006.197.08:27:58.27#ibcon#*mode == 0, iclass 31, count 2 2006.197.08:27:58.27#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.197.08:27:58.27#ibcon#[25=AT03-06\r\n] 2006.197.08:27:58.27#ibcon#*before write, iclass 31, count 2 2006.197.08:27:58.27#ibcon#enter sib2, iclass 31, count 2 2006.197.08:27:58.27#ibcon#flushed, iclass 31, count 2 2006.197.08:27:58.27#ibcon#about to write, iclass 31, count 2 2006.197.08:27:58.27#ibcon#wrote, iclass 31, count 2 2006.197.08:27:58.27#ibcon#about to read 3, iclass 31, count 2 2006.197.08:27:58.30#ibcon#read 3, iclass 31, count 2 2006.197.08:27:58.30#ibcon#about to read 4, iclass 31, count 2 2006.197.08:27:58.30#ibcon#read 4, iclass 31, count 2 2006.197.08:27:58.30#ibcon#about to read 5, iclass 31, count 2 2006.197.08:27:58.30#ibcon#read 5, iclass 31, count 2 2006.197.08:27:58.30#ibcon#about to read 6, iclass 31, count 2 2006.197.08:27:58.30#ibcon#read 6, iclass 31, count 2 2006.197.08:27:58.30#ibcon#end of sib2, iclass 31, count 2 2006.197.08:27:58.30#ibcon#*after write, iclass 31, count 2 2006.197.08:27:58.30#ibcon#*before return 0, iclass 31, count 2 2006.197.08:27:58.30#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.197.08:27:58.30#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.197.08:27:58.30#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.197.08:27:58.30#ibcon#ireg 7 cls_cnt 0 2006.197.08:27:58.30#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.197.08:27:58.42#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.197.08:27:58.42#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.197.08:27:58.42#ibcon#enter wrdev, iclass 31, count 0 2006.197.08:27:58.42#ibcon#first serial, iclass 31, count 0 2006.197.08:27:58.42#ibcon#enter sib2, iclass 31, count 0 2006.197.08:27:58.42#ibcon#flushed, iclass 31, count 0 2006.197.08:27:58.42#ibcon#about to write, iclass 31, count 0 2006.197.08:27:58.42#ibcon#wrote, iclass 31, count 0 2006.197.08:27:58.42#ibcon#about to read 3, iclass 31, count 0 2006.197.08:27:58.44#ibcon#read 3, iclass 31, count 0 2006.197.08:27:58.44#ibcon#about to read 4, iclass 31, count 0 2006.197.08:27:58.44#ibcon#read 4, iclass 31, count 0 2006.197.08:27:58.44#ibcon#about to read 5, iclass 31, count 0 2006.197.08:27:58.44#ibcon#read 5, iclass 31, count 0 2006.197.08:27:58.44#ibcon#about to read 6, iclass 31, count 0 2006.197.08:27:58.44#ibcon#read 6, iclass 31, count 0 2006.197.08:27:58.44#ibcon#end of sib2, iclass 31, count 0 2006.197.08:27:58.44#ibcon#*mode == 0, iclass 31, count 0 2006.197.08:27:58.44#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.197.08:27:58.44#ibcon#[25=USB\r\n] 2006.197.08:27:58.44#ibcon#*before write, iclass 31, count 0 2006.197.08:27:58.44#ibcon#enter sib2, iclass 31, count 0 2006.197.08:27:58.44#ibcon#flushed, iclass 31, count 0 2006.197.08:27:58.44#ibcon#about to write, iclass 31, count 0 2006.197.08:27:58.44#ibcon#wrote, iclass 31, count 0 2006.197.08:27:58.44#ibcon#about to read 3, iclass 31, count 0 2006.197.08:27:58.47#ibcon#read 3, iclass 31, count 0 2006.197.08:27:58.47#ibcon#about to read 4, iclass 31, count 0 2006.197.08:27:58.47#ibcon#read 4, iclass 31, count 0 2006.197.08:27:58.47#ibcon#about to read 5, iclass 31, count 0 2006.197.08:27:58.47#ibcon#read 5, iclass 31, count 0 2006.197.08:27:58.47#ibcon#about to read 6, iclass 31, count 0 2006.197.08:27:58.47#ibcon#read 6, iclass 31, count 0 2006.197.08:27:58.47#ibcon#end of sib2, iclass 31, count 0 2006.197.08:27:58.47#ibcon#*after write, iclass 31, count 0 2006.197.08:27:58.47#ibcon#*before return 0, iclass 31, count 0 2006.197.08:27:58.47#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.197.08:27:58.47#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.197.08:27:58.47#ibcon#about to clear, iclass 31 cls_cnt 0 2006.197.08:27:58.47#ibcon#cleared, iclass 31 cls_cnt 0 2006.197.08:27:58.47$vc4f8/valo=4,832.99 2006.197.08:27:58.47#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.197.08:27:58.47#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.197.08:27:58.47#ibcon#ireg 17 cls_cnt 0 2006.197.08:27:58.47#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.197.08:27:58.47#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.197.08:27:58.47#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.197.08:27:58.47#ibcon#enter wrdev, iclass 33, count 0 2006.197.08:27:58.47#ibcon#first serial, iclass 33, count 0 2006.197.08:27:58.47#ibcon#enter sib2, iclass 33, count 0 2006.197.08:27:58.47#ibcon#flushed, iclass 33, count 0 2006.197.08:27:58.47#ibcon#about to write, iclass 33, count 0 2006.197.08:27:58.47#ibcon#wrote, iclass 33, count 0 2006.197.08:27:58.47#ibcon#about to read 3, iclass 33, count 0 2006.197.08:27:58.49#ibcon#read 3, iclass 33, count 0 2006.197.08:27:58.49#ibcon#about to read 4, iclass 33, count 0 2006.197.08:27:58.49#ibcon#read 4, iclass 33, count 0 2006.197.08:27:58.49#ibcon#about to read 5, iclass 33, count 0 2006.197.08:27:58.49#ibcon#read 5, iclass 33, count 0 2006.197.08:27:58.49#ibcon#about to read 6, iclass 33, count 0 2006.197.08:27:58.49#ibcon#read 6, iclass 33, count 0 2006.197.08:27:58.49#ibcon#end of sib2, iclass 33, count 0 2006.197.08:27:58.49#ibcon#*mode == 0, iclass 33, count 0 2006.197.08:27:58.49#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.197.08:27:58.49#ibcon#[26=FRQ=04,832.99\r\n] 2006.197.08:27:58.49#ibcon#*before write, iclass 33, count 0 2006.197.08:27:58.49#ibcon#enter sib2, iclass 33, count 0 2006.197.08:27:58.49#ibcon#flushed, iclass 33, count 0 2006.197.08:27:58.49#ibcon#about to write, iclass 33, count 0 2006.197.08:27:58.49#ibcon#wrote, iclass 33, count 0 2006.197.08:27:58.49#ibcon#about to read 3, iclass 33, count 0 2006.197.08:27:58.53#ibcon#read 3, iclass 33, count 0 2006.197.08:27:58.53#ibcon#about to read 4, iclass 33, count 0 2006.197.08:27:58.53#ibcon#read 4, iclass 33, count 0 2006.197.08:27:58.53#ibcon#about to read 5, iclass 33, count 0 2006.197.08:27:58.53#ibcon#read 5, iclass 33, count 0 2006.197.08:27:58.53#ibcon#about to read 6, iclass 33, count 0 2006.197.08:27:58.53#ibcon#read 6, iclass 33, count 0 2006.197.08:27:58.53#ibcon#end of sib2, iclass 33, count 0 2006.197.08:27:58.53#ibcon#*after write, iclass 33, count 0 2006.197.08:27:58.53#ibcon#*before return 0, iclass 33, count 0 2006.197.08:27:58.53#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.197.08:27:58.53#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.197.08:27:58.53#ibcon#about to clear, iclass 33 cls_cnt 0 2006.197.08:27:58.53#ibcon#cleared, iclass 33 cls_cnt 0 2006.197.08:27:58.53$vc4f8/va=4,7 2006.197.08:27:58.53#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.197.08:27:58.53#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.197.08:27:58.53#ibcon#ireg 11 cls_cnt 2 2006.197.08:27:58.53#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.197.08:27:58.59#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.197.08:27:58.59#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.197.08:27:58.59#ibcon#enter wrdev, iclass 35, count 2 2006.197.08:27:58.59#ibcon#first serial, iclass 35, count 2 2006.197.08:27:58.59#ibcon#enter sib2, iclass 35, count 2 2006.197.08:27:58.59#ibcon#flushed, iclass 35, count 2 2006.197.08:27:58.59#ibcon#about to write, iclass 35, count 2 2006.197.08:27:58.59#ibcon#wrote, iclass 35, count 2 2006.197.08:27:58.59#ibcon#about to read 3, iclass 35, count 2 2006.197.08:27:58.61#ibcon#read 3, iclass 35, count 2 2006.197.08:27:58.61#ibcon#about to read 4, iclass 35, count 2 2006.197.08:27:58.61#ibcon#read 4, iclass 35, count 2 2006.197.08:27:58.61#ibcon#about to read 5, iclass 35, count 2 2006.197.08:27:58.61#ibcon#read 5, iclass 35, count 2 2006.197.08:27:58.61#ibcon#about to read 6, iclass 35, count 2 2006.197.08:27:58.61#ibcon#read 6, iclass 35, count 2 2006.197.08:27:58.61#ibcon#end of sib2, iclass 35, count 2 2006.197.08:27:58.61#ibcon#*mode == 0, iclass 35, count 2 2006.197.08:27:58.61#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.197.08:27:58.61#ibcon#[25=AT04-07\r\n] 2006.197.08:27:58.61#ibcon#*before write, iclass 35, count 2 2006.197.08:27:58.61#ibcon#enter sib2, iclass 35, count 2 2006.197.08:27:58.61#ibcon#flushed, iclass 35, count 2 2006.197.08:27:58.61#ibcon#about to write, iclass 35, count 2 2006.197.08:27:58.61#ibcon#wrote, iclass 35, count 2 2006.197.08:27:58.61#ibcon#about to read 3, iclass 35, count 2 2006.197.08:27:58.64#ibcon#read 3, iclass 35, count 2 2006.197.08:27:58.64#ibcon#about to read 4, iclass 35, count 2 2006.197.08:27:58.64#ibcon#read 4, iclass 35, count 2 2006.197.08:27:58.64#ibcon#about to read 5, iclass 35, count 2 2006.197.08:27:58.64#ibcon#read 5, iclass 35, count 2 2006.197.08:27:58.64#ibcon#about to read 6, iclass 35, count 2 2006.197.08:27:58.64#ibcon#read 6, iclass 35, count 2 2006.197.08:27:58.64#ibcon#end of sib2, iclass 35, count 2 2006.197.08:27:58.64#ibcon#*after write, iclass 35, count 2 2006.197.08:27:58.64#ibcon#*before return 0, iclass 35, count 2 2006.197.08:27:58.64#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.197.08:27:58.64#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.197.08:27:58.64#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.197.08:27:58.64#ibcon#ireg 7 cls_cnt 0 2006.197.08:27:58.64#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.197.08:27:58.76#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.197.08:27:58.76#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.197.08:27:58.76#ibcon#enter wrdev, iclass 35, count 0 2006.197.08:27:58.76#ibcon#first serial, iclass 35, count 0 2006.197.08:27:58.76#ibcon#enter sib2, iclass 35, count 0 2006.197.08:27:58.76#ibcon#flushed, iclass 35, count 0 2006.197.08:27:58.76#ibcon#about to write, iclass 35, count 0 2006.197.08:27:58.76#ibcon#wrote, iclass 35, count 0 2006.197.08:27:58.76#ibcon#about to read 3, iclass 35, count 0 2006.197.08:27:58.78#ibcon#read 3, iclass 35, count 0 2006.197.08:27:58.78#ibcon#about to read 4, iclass 35, count 0 2006.197.08:27:58.78#ibcon#read 4, iclass 35, count 0 2006.197.08:27:58.78#ibcon#about to read 5, iclass 35, count 0 2006.197.08:27:58.78#ibcon#read 5, iclass 35, count 0 2006.197.08:27:58.78#ibcon#about to read 6, iclass 35, count 0 2006.197.08:27:58.78#ibcon#read 6, iclass 35, count 0 2006.197.08:27:58.78#ibcon#end of sib2, iclass 35, count 0 2006.197.08:27:58.78#ibcon#*mode == 0, iclass 35, count 0 2006.197.08:27:58.78#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.197.08:27:58.78#ibcon#[25=USB\r\n] 2006.197.08:27:58.78#ibcon#*before write, iclass 35, count 0 2006.197.08:27:58.78#ibcon#enter sib2, iclass 35, count 0 2006.197.08:27:58.78#ibcon#flushed, iclass 35, count 0 2006.197.08:27:58.78#ibcon#about to write, iclass 35, count 0 2006.197.08:27:58.78#ibcon#wrote, iclass 35, count 0 2006.197.08:27:58.78#ibcon#about to read 3, iclass 35, count 0 2006.197.08:27:58.81#ibcon#read 3, iclass 35, count 0 2006.197.08:27:58.81#ibcon#about to read 4, iclass 35, count 0 2006.197.08:27:58.81#ibcon#read 4, iclass 35, count 0 2006.197.08:27:58.81#ibcon#about to read 5, iclass 35, count 0 2006.197.08:27:58.81#ibcon#read 5, iclass 35, count 0 2006.197.08:27:58.81#ibcon#about to read 6, iclass 35, count 0 2006.197.08:27:58.81#ibcon#read 6, iclass 35, count 0 2006.197.08:27:58.81#ibcon#end of sib2, iclass 35, count 0 2006.197.08:27:58.81#ibcon#*after write, iclass 35, count 0 2006.197.08:27:58.81#ibcon#*before return 0, iclass 35, count 0 2006.197.08:27:58.81#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.197.08:27:58.81#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.197.08:27:58.81#ibcon#about to clear, iclass 35 cls_cnt 0 2006.197.08:27:58.81#ibcon#cleared, iclass 35 cls_cnt 0 2006.197.08:27:58.81$vc4f8/valo=5,652.99 2006.197.08:27:58.81#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.197.08:27:58.81#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.197.08:27:58.81#ibcon#ireg 17 cls_cnt 0 2006.197.08:27:58.81#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.197.08:27:58.81#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.197.08:27:58.81#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.197.08:27:58.81#ibcon#enter wrdev, iclass 38, count 0 2006.197.08:27:58.81#ibcon#first serial, iclass 38, count 0 2006.197.08:27:58.81#ibcon#enter sib2, iclass 38, count 0 2006.197.08:27:58.81#ibcon#flushed, iclass 38, count 0 2006.197.08:27:58.81#ibcon#about to write, iclass 38, count 0 2006.197.08:27:58.81#ibcon#wrote, iclass 38, count 0 2006.197.08:27:58.81#ibcon#about to read 3, iclass 38, count 0 2006.197.08:27:58.83#ibcon#read 3, iclass 38, count 0 2006.197.08:27:58.83#ibcon#about to read 4, iclass 38, count 0 2006.197.08:27:58.83#ibcon#read 4, iclass 38, count 0 2006.197.08:27:58.83#ibcon#about to read 5, iclass 38, count 0 2006.197.08:27:58.83#ibcon#read 5, iclass 38, count 0 2006.197.08:27:58.83#ibcon#about to read 6, iclass 38, count 0 2006.197.08:27:58.83#ibcon#read 6, iclass 38, count 0 2006.197.08:27:58.83#ibcon#end of sib2, iclass 38, count 0 2006.197.08:27:58.83#ibcon#*mode == 0, iclass 38, count 0 2006.197.08:27:58.83#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.197.08:27:58.83#ibcon#[26=FRQ=05,652.99\r\n] 2006.197.08:27:58.83#ibcon#*before write, iclass 38, count 0 2006.197.08:27:58.83#ibcon#enter sib2, iclass 38, count 0 2006.197.08:27:58.83#ibcon#flushed, iclass 38, count 0 2006.197.08:27:58.83#ibcon#about to write, iclass 38, count 0 2006.197.08:27:58.83#ibcon#wrote, iclass 38, count 0 2006.197.08:27:58.83#ibcon#about to read 3, iclass 38, count 0 2006.197.08:27:58.84#abcon#<5=/04 3.0 6.1 25.50 961003.0\r\n> 2006.197.08:27:58.86#abcon#{5=INTERFACE CLEAR} 2006.197.08:27:58.87#ibcon#read 3, iclass 38, count 0 2006.197.08:27:58.87#ibcon#about to read 4, iclass 38, count 0 2006.197.08:27:58.87#ibcon#read 4, iclass 38, count 0 2006.197.08:27:58.87#ibcon#about to read 5, iclass 38, count 0 2006.197.08:27:58.87#ibcon#read 5, iclass 38, count 0 2006.197.08:27:58.87#ibcon#about to read 6, iclass 38, count 0 2006.197.08:27:58.87#ibcon#read 6, iclass 38, count 0 2006.197.08:27:58.87#ibcon#end of sib2, iclass 38, count 0 2006.197.08:27:58.87#ibcon#*after write, iclass 38, count 0 2006.197.08:27:58.87#ibcon#*before return 0, iclass 38, count 0 2006.197.08:27:58.87#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.197.08:27:58.87#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.197.08:27:58.87#ibcon#about to clear, iclass 38 cls_cnt 0 2006.197.08:27:58.87#ibcon#cleared, iclass 38 cls_cnt 0 2006.197.08:27:58.87$vc4f8/va=5,7 2006.197.08:27:58.87#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.197.08:27:58.87#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.197.08:27:58.87#ibcon#ireg 11 cls_cnt 2 2006.197.08:27:58.87#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.197.08:27:58.92#abcon#[5=S1D000X0/0*\r\n] 2006.197.08:27:58.93#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.197.08:27:58.93#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.197.08:27:58.93#ibcon#enter wrdev, iclass 4, count 2 2006.197.08:27:58.93#ibcon#first serial, iclass 4, count 2 2006.197.08:27:58.93#ibcon#enter sib2, iclass 4, count 2 2006.197.08:27:58.93#ibcon#flushed, iclass 4, count 2 2006.197.08:27:58.93#ibcon#about to write, iclass 4, count 2 2006.197.08:27:58.93#ibcon#wrote, iclass 4, count 2 2006.197.08:27:58.93#ibcon#about to read 3, iclass 4, count 2 2006.197.08:27:58.95#ibcon#read 3, iclass 4, count 2 2006.197.08:27:58.95#ibcon#about to read 4, iclass 4, count 2 2006.197.08:27:58.95#ibcon#read 4, iclass 4, count 2 2006.197.08:27:58.95#ibcon#about to read 5, iclass 4, count 2 2006.197.08:27:58.95#ibcon#read 5, iclass 4, count 2 2006.197.08:27:58.95#ibcon#about to read 6, iclass 4, count 2 2006.197.08:27:58.95#ibcon#read 6, iclass 4, count 2 2006.197.08:27:58.95#ibcon#end of sib2, iclass 4, count 2 2006.197.08:27:58.95#ibcon#*mode == 0, iclass 4, count 2 2006.197.08:27:58.95#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.197.08:27:58.95#ibcon#[25=AT05-07\r\n] 2006.197.08:27:58.95#ibcon#*before write, iclass 4, count 2 2006.197.08:27:58.95#ibcon#enter sib2, iclass 4, count 2 2006.197.08:27:58.95#ibcon#flushed, iclass 4, count 2 2006.197.08:27:58.95#ibcon#about to write, iclass 4, count 2 2006.197.08:27:58.95#ibcon#wrote, iclass 4, count 2 2006.197.08:27:58.95#ibcon#about to read 3, iclass 4, count 2 2006.197.08:27:58.98#ibcon#read 3, iclass 4, count 2 2006.197.08:27:58.98#ibcon#about to read 4, iclass 4, count 2 2006.197.08:27:58.98#ibcon#read 4, iclass 4, count 2 2006.197.08:27:58.98#ibcon#about to read 5, iclass 4, count 2 2006.197.08:27:58.98#ibcon#read 5, iclass 4, count 2 2006.197.08:27:58.98#ibcon#about to read 6, iclass 4, count 2 2006.197.08:27:58.98#ibcon#read 6, iclass 4, count 2 2006.197.08:27:58.98#ibcon#end of sib2, iclass 4, count 2 2006.197.08:27:58.98#ibcon#*after write, iclass 4, count 2 2006.197.08:27:58.98#ibcon#*before return 0, iclass 4, count 2 2006.197.08:27:58.98#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.197.08:27:58.98#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.197.08:27:58.98#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.197.08:27:58.98#ibcon#ireg 7 cls_cnt 0 2006.197.08:27:58.98#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.197.08:27:59.10#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.197.08:27:59.10#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.197.08:27:59.10#ibcon#enter wrdev, iclass 4, count 0 2006.197.08:27:59.10#ibcon#first serial, iclass 4, count 0 2006.197.08:27:59.10#ibcon#enter sib2, iclass 4, count 0 2006.197.08:27:59.10#ibcon#flushed, iclass 4, count 0 2006.197.08:27:59.10#ibcon#about to write, iclass 4, count 0 2006.197.08:27:59.10#ibcon#wrote, iclass 4, count 0 2006.197.08:27:59.10#ibcon#about to read 3, iclass 4, count 0 2006.197.08:27:59.12#ibcon#read 3, iclass 4, count 0 2006.197.08:27:59.12#ibcon#about to read 4, iclass 4, count 0 2006.197.08:27:59.12#ibcon#read 4, iclass 4, count 0 2006.197.08:27:59.12#ibcon#about to read 5, iclass 4, count 0 2006.197.08:27:59.12#ibcon#read 5, iclass 4, count 0 2006.197.08:27:59.12#ibcon#about to read 6, iclass 4, count 0 2006.197.08:27:59.12#ibcon#read 6, iclass 4, count 0 2006.197.08:27:59.12#ibcon#end of sib2, iclass 4, count 0 2006.197.08:27:59.12#ibcon#*mode == 0, iclass 4, count 0 2006.197.08:27:59.12#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.197.08:27:59.12#ibcon#[25=USB\r\n] 2006.197.08:27:59.12#ibcon#*before write, iclass 4, count 0 2006.197.08:27:59.12#ibcon#enter sib2, iclass 4, count 0 2006.197.08:27:59.12#ibcon#flushed, iclass 4, count 0 2006.197.08:27:59.12#ibcon#about to write, iclass 4, count 0 2006.197.08:27:59.12#ibcon#wrote, iclass 4, count 0 2006.197.08:27:59.12#ibcon#about to read 3, iclass 4, count 0 2006.197.08:27:59.15#ibcon#read 3, iclass 4, count 0 2006.197.08:27:59.15#ibcon#about to read 4, iclass 4, count 0 2006.197.08:27:59.15#ibcon#read 4, iclass 4, count 0 2006.197.08:27:59.15#ibcon#about to read 5, iclass 4, count 0 2006.197.08:27:59.15#ibcon#read 5, iclass 4, count 0 2006.197.08:27:59.15#ibcon#about to read 6, iclass 4, count 0 2006.197.08:27:59.15#ibcon#read 6, iclass 4, count 0 2006.197.08:27:59.15#ibcon#end of sib2, iclass 4, count 0 2006.197.08:27:59.15#ibcon#*after write, iclass 4, count 0 2006.197.08:27:59.15#ibcon#*before return 0, iclass 4, count 0 2006.197.08:27:59.15#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.197.08:27:59.15#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.197.08:27:59.15#ibcon#about to clear, iclass 4 cls_cnt 0 2006.197.08:27:59.15#ibcon#cleared, iclass 4 cls_cnt 0 2006.197.08:27:59.15$vc4f8/valo=6,772.99 2006.197.08:27:59.15#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.197.08:27:59.15#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.197.08:27:59.15#ibcon#ireg 17 cls_cnt 0 2006.197.08:27:59.15#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.197.08:27:59.15#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.197.08:27:59.15#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.197.08:27:59.15#ibcon#enter wrdev, iclass 7, count 0 2006.197.08:27:59.15#ibcon#first serial, iclass 7, count 0 2006.197.08:27:59.15#ibcon#enter sib2, iclass 7, count 0 2006.197.08:27:59.15#ibcon#flushed, iclass 7, count 0 2006.197.08:27:59.15#ibcon#about to write, iclass 7, count 0 2006.197.08:27:59.15#ibcon#wrote, iclass 7, count 0 2006.197.08:27:59.15#ibcon#about to read 3, iclass 7, count 0 2006.197.08:27:59.17#ibcon#read 3, iclass 7, count 0 2006.197.08:27:59.17#ibcon#about to read 4, iclass 7, count 0 2006.197.08:27:59.17#ibcon#read 4, iclass 7, count 0 2006.197.08:27:59.17#ibcon#about to read 5, iclass 7, count 0 2006.197.08:27:59.17#ibcon#read 5, iclass 7, count 0 2006.197.08:27:59.17#ibcon#about to read 6, iclass 7, count 0 2006.197.08:27:59.17#ibcon#read 6, iclass 7, count 0 2006.197.08:27:59.17#ibcon#end of sib2, iclass 7, count 0 2006.197.08:27:59.17#ibcon#*mode == 0, iclass 7, count 0 2006.197.08:27:59.17#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.197.08:27:59.17#ibcon#[26=FRQ=06,772.99\r\n] 2006.197.08:27:59.17#ibcon#*before write, iclass 7, count 0 2006.197.08:27:59.17#ibcon#enter sib2, iclass 7, count 0 2006.197.08:27:59.17#ibcon#flushed, iclass 7, count 0 2006.197.08:27:59.17#ibcon#about to write, iclass 7, count 0 2006.197.08:27:59.17#ibcon#wrote, iclass 7, count 0 2006.197.08:27:59.17#ibcon#about to read 3, iclass 7, count 0 2006.197.08:27:59.21#ibcon#read 3, iclass 7, count 0 2006.197.08:27:59.21#ibcon#about to read 4, iclass 7, count 0 2006.197.08:27:59.21#ibcon#read 4, iclass 7, count 0 2006.197.08:27:59.21#ibcon#about to read 5, iclass 7, count 0 2006.197.08:27:59.21#ibcon#read 5, iclass 7, count 0 2006.197.08:27:59.21#ibcon#about to read 6, iclass 7, count 0 2006.197.08:27:59.21#ibcon#read 6, iclass 7, count 0 2006.197.08:27:59.21#ibcon#end of sib2, iclass 7, count 0 2006.197.08:27:59.21#ibcon#*after write, iclass 7, count 0 2006.197.08:27:59.21#ibcon#*before return 0, iclass 7, count 0 2006.197.08:27:59.21#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.197.08:27:59.21#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.197.08:27:59.21#ibcon#about to clear, iclass 7 cls_cnt 0 2006.197.08:27:59.21#ibcon#cleared, iclass 7 cls_cnt 0 2006.197.08:27:59.21$vc4f8/va=6,6 2006.197.08:27:59.21#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.197.08:27:59.21#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.197.08:27:59.21#ibcon#ireg 11 cls_cnt 2 2006.197.08:27:59.21#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.197.08:27:59.27#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.197.08:27:59.27#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.197.08:27:59.27#ibcon#enter wrdev, iclass 11, count 2 2006.197.08:27:59.27#ibcon#first serial, iclass 11, count 2 2006.197.08:27:59.27#ibcon#enter sib2, iclass 11, count 2 2006.197.08:27:59.27#ibcon#flushed, iclass 11, count 2 2006.197.08:27:59.27#ibcon#about to write, iclass 11, count 2 2006.197.08:27:59.27#ibcon#wrote, iclass 11, count 2 2006.197.08:27:59.27#ibcon#about to read 3, iclass 11, count 2 2006.197.08:27:59.29#ibcon#read 3, iclass 11, count 2 2006.197.08:27:59.29#ibcon#about to read 4, iclass 11, count 2 2006.197.08:27:59.29#ibcon#read 4, iclass 11, count 2 2006.197.08:27:59.29#ibcon#about to read 5, iclass 11, count 2 2006.197.08:27:59.29#ibcon#read 5, iclass 11, count 2 2006.197.08:27:59.29#ibcon#about to read 6, iclass 11, count 2 2006.197.08:27:59.29#ibcon#read 6, iclass 11, count 2 2006.197.08:27:59.29#ibcon#end of sib2, iclass 11, count 2 2006.197.08:27:59.29#ibcon#*mode == 0, iclass 11, count 2 2006.197.08:27:59.29#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.197.08:27:59.29#ibcon#[25=AT06-06\r\n] 2006.197.08:27:59.29#ibcon#*before write, iclass 11, count 2 2006.197.08:27:59.29#ibcon#enter sib2, iclass 11, count 2 2006.197.08:27:59.29#ibcon#flushed, iclass 11, count 2 2006.197.08:27:59.29#ibcon#about to write, iclass 11, count 2 2006.197.08:27:59.29#ibcon#wrote, iclass 11, count 2 2006.197.08:27:59.29#ibcon#about to read 3, iclass 11, count 2 2006.197.08:27:59.32#ibcon#read 3, iclass 11, count 2 2006.197.08:27:59.32#ibcon#about to read 4, iclass 11, count 2 2006.197.08:27:59.32#ibcon#read 4, iclass 11, count 2 2006.197.08:27:59.32#ibcon#about to read 5, iclass 11, count 2 2006.197.08:27:59.32#ibcon#read 5, iclass 11, count 2 2006.197.08:27:59.32#ibcon#about to read 6, iclass 11, count 2 2006.197.08:27:59.32#ibcon#read 6, iclass 11, count 2 2006.197.08:27:59.32#ibcon#end of sib2, iclass 11, count 2 2006.197.08:27:59.32#ibcon#*after write, iclass 11, count 2 2006.197.08:27:59.32#ibcon#*before return 0, iclass 11, count 2 2006.197.08:27:59.32#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.197.08:27:59.32#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.197.08:27:59.32#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.197.08:27:59.32#ibcon#ireg 7 cls_cnt 0 2006.197.08:27:59.32#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.197.08:27:59.44#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.197.08:27:59.44#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.197.08:27:59.44#ibcon#enter wrdev, iclass 11, count 0 2006.197.08:27:59.44#ibcon#first serial, iclass 11, count 0 2006.197.08:27:59.44#ibcon#enter sib2, iclass 11, count 0 2006.197.08:27:59.44#ibcon#flushed, iclass 11, count 0 2006.197.08:27:59.44#ibcon#about to write, iclass 11, count 0 2006.197.08:27:59.44#ibcon#wrote, iclass 11, count 0 2006.197.08:27:59.44#ibcon#about to read 3, iclass 11, count 0 2006.197.08:27:59.46#ibcon#read 3, iclass 11, count 0 2006.197.08:27:59.46#ibcon#about to read 4, iclass 11, count 0 2006.197.08:27:59.46#ibcon#read 4, iclass 11, count 0 2006.197.08:27:59.46#ibcon#about to read 5, iclass 11, count 0 2006.197.08:27:59.46#ibcon#read 5, iclass 11, count 0 2006.197.08:27:59.46#ibcon#about to read 6, iclass 11, count 0 2006.197.08:27:59.46#ibcon#read 6, iclass 11, count 0 2006.197.08:27:59.46#ibcon#end of sib2, iclass 11, count 0 2006.197.08:27:59.46#ibcon#*mode == 0, iclass 11, count 0 2006.197.08:27:59.46#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.197.08:27:59.46#ibcon#[25=USB\r\n] 2006.197.08:27:59.46#ibcon#*before write, iclass 11, count 0 2006.197.08:27:59.46#ibcon#enter sib2, iclass 11, count 0 2006.197.08:27:59.46#ibcon#flushed, iclass 11, count 0 2006.197.08:27:59.46#ibcon#about to write, iclass 11, count 0 2006.197.08:27:59.46#ibcon#wrote, iclass 11, count 0 2006.197.08:27:59.46#ibcon#about to read 3, iclass 11, count 0 2006.197.08:27:59.49#ibcon#read 3, iclass 11, count 0 2006.197.08:27:59.49#ibcon#about to read 4, iclass 11, count 0 2006.197.08:27:59.49#ibcon#read 4, iclass 11, count 0 2006.197.08:27:59.49#ibcon#about to read 5, iclass 11, count 0 2006.197.08:27:59.49#ibcon#read 5, iclass 11, count 0 2006.197.08:27:59.49#ibcon#about to read 6, iclass 11, count 0 2006.197.08:27:59.49#ibcon#read 6, iclass 11, count 0 2006.197.08:27:59.49#ibcon#end of sib2, iclass 11, count 0 2006.197.08:27:59.49#ibcon#*after write, iclass 11, count 0 2006.197.08:27:59.49#ibcon#*before return 0, iclass 11, count 0 2006.197.08:27:59.49#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.197.08:27:59.49#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.197.08:27:59.49#ibcon#about to clear, iclass 11 cls_cnt 0 2006.197.08:27:59.49#ibcon#cleared, iclass 11 cls_cnt 0 2006.197.08:27:59.49$vc4f8/valo=7,832.99 2006.197.08:27:59.49#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.197.08:27:59.49#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.197.08:27:59.49#ibcon#ireg 17 cls_cnt 0 2006.197.08:27:59.49#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.197.08:27:59.49#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.197.08:27:59.49#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.197.08:27:59.49#ibcon#enter wrdev, iclass 13, count 0 2006.197.08:27:59.49#ibcon#first serial, iclass 13, count 0 2006.197.08:27:59.49#ibcon#enter sib2, iclass 13, count 0 2006.197.08:27:59.49#ibcon#flushed, iclass 13, count 0 2006.197.08:27:59.49#ibcon#about to write, iclass 13, count 0 2006.197.08:27:59.49#ibcon#wrote, iclass 13, count 0 2006.197.08:27:59.49#ibcon#about to read 3, iclass 13, count 0 2006.197.08:27:59.51#ibcon#read 3, iclass 13, count 0 2006.197.08:27:59.51#ibcon#about to read 4, iclass 13, count 0 2006.197.08:27:59.51#ibcon#read 4, iclass 13, count 0 2006.197.08:27:59.51#ibcon#about to read 5, iclass 13, count 0 2006.197.08:27:59.51#ibcon#read 5, iclass 13, count 0 2006.197.08:27:59.51#ibcon#about to read 6, iclass 13, count 0 2006.197.08:27:59.51#ibcon#read 6, iclass 13, count 0 2006.197.08:27:59.51#ibcon#end of sib2, iclass 13, count 0 2006.197.08:27:59.51#ibcon#*mode == 0, iclass 13, count 0 2006.197.08:27:59.51#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.197.08:27:59.51#ibcon#[26=FRQ=07,832.99\r\n] 2006.197.08:27:59.51#ibcon#*before write, iclass 13, count 0 2006.197.08:27:59.51#ibcon#enter sib2, iclass 13, count 0 2006.197.08:27:59.51#ibcon#flushed, iclass 13, count 0 2006.197.08:27:59.51#ibcon#about to write, iclass 13, count 0 2006.197.08:27:59.51#ibcon#wrote, iclass 13, count 0 2006.197.08:27:59.51#ibcon#about to read 3, iclass 13, count 0 2006.197.08:27:59.55#ibcon#read 3, iclass 13, count 0 2006.197.08:27:59.55#ibcon#about to read 4, iclass 13, count 0 2006.197.08:27:59.55#ibcon#read 4, iclass 13, count 0 2006.197.08:27:59.55#ibcon#about to read 5, iclass 13, count 0 2006.197.08:27:59.55#ibcon#read 5, iclass 13, count 0 2006.197.08:27:59.55#ibcon#about to read 6, iclass 13, count 0 2006.197.08:27:59.55#ibcon#read 6, iclass 13, count 0 2006.197.08:27:59.55#ibcon#end of sib2, iclass 13, count 0 2006.197.08:27:59.55#ibcon#*after write, iclass 13, count 0 2006.197.08:27:59.55#ibcon#*before return 0, iclass 13, count 0 2006.197.08:27:59.55#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.197.08:27:59.55#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.197.08:27:59.55#ibcon#about to clear, iclass 13 cls_cnt 0 2006.197.08:27:59.55#ibcon#cleared, iclass 13 cls_cnt 0 2006.197.08:27:59.55$vc4f8/va=7,6 2006.197.08:27:59.55#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.197.08:27:59.55#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.197.08:27:59.55#ibcon#ireg 11 cls_cnt 2 2006.197.08:27:59.55#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.197.08:27:59.61#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.197.08:27:59.61#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.197.08:27:59.61#ibcon#enter wrdev, iclass 15, count 2 2006.197.08:27:59.61#ibcon#first serial, iclass 15, count 2 2006.197.08:27:59.61#ibcon#enter sib2, iclass 15, count 2 2006.197.08:27:59.61#ibcon#flushed, iclass 15, count 2 2006.197.08:27:59.61#ibcon#about to write, iclass 15, count 2 2006.197.08:27:59.61#ibcon#wrote, iclass 15, count 2 2006.197.08:27:59.61#ibcon#about to read 3, iclass 15, count 2 2006.197.08:27:59.63#ibcon#read 3, iclass 15, count 2 2006.197.08:27:59.63#ibcon#about to read 4, iclass 15, count 2 2006.197.08:27:59.63#ibcon#read 4, iclass 15, count 2 2006.197.08:27:59.63#ibcon#about to read 5, iclass 15, count 2 2006.197.08:27:59.63#ibcon#read 5, iclass 15, count 2 2006.197.08:27:59.63#ibcon#about to read 6, iclass 15, count 2 2006.197.08:27:59.63#ibcon#read 6, iclass 15, count 2 2006.197.08:27:59.63#ibcon#end of sib2, iclass 15, count 2 2006.197.08:27:59.63#ibcon#*mode == 0, iclass 15, count 2 2006.197.08:27:59.63#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.197.08:27:59.63#ibcon#[25=AT07-06\r\n] 2006.197.08:27:59.63#ibcon#*before write, iclass 15, count 2 2006.197.08:27:59.63#ibcon#enter sib2, iclass 15, count 2 2006.197.08:27:59.63#ibcon#flushed, iclass 15, count 2 2006.197.08:27:59.63#ibcon#about to write, iclass 15, count 2 2006.197.08:27:59.63#ibcon#wrote, iclass 15, count 2 2006.197.08:27:59.63#ibcon#about to read 3, iclass 15, count 2 2006.197.08:27:59.66#ibcon#read 3, iclass 15, count 2 2006.197.08:27:59.66#ibcon#about to read 4, iclass 15, count 2 2006.197.08:27:59.66#ibcon#read 4, iclass 15, count 2 2006.197.08:27:59.66#ibcon#about to read 5, iclass 15, count 2 2006.197.08:27:59.66#ibcon#read 5, iclass 15, count 2 2006.197.08:27:59.66#ibcon#about to read 6, iclass 15, count 2 2006.197.08:27:59.66#ibcon#read 6, iclass 15, count 2 2006.197.08:27:59.66#ibcon#end of sib2, iclass 15, count 2 2006.197.08:27:59.66#ibcon#*after write, iclass 15, count 2 2006.197.08:27:59.66#ibcon#*before return 0, iclass 15, count 2 2006.197.08:27:59.66#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.197.08:27:59.66#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.197.08:27:59.66#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.197.08:27:59.66#ibcon#ireg 7 cls_cnt 0 2006.197.08:27:59.66#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.197.08:27:59.78#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.197.08:27:59.78#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.197.08:27:59.78#ibcon#enter wrdev, iclass 15, count 0 2006.197.08:27:59.78#ibcon#first serial, iclass 15, count 0 2006.197.08:27:59.78#ibcon#enter sib2, iclass 15, count 0 2006.197.08:27:59.78#ibcon#flushed, iclass 15, count 0 2006.197.08:27:59.78#ibcon#about to write, iclass 15, count 0 2006.197.08:27:59.78#ibcon#wrote, iclass 15, count 0 2006.197.08:27:59.78#ibcon#about to read 3, iclass 15, count 0 2006.197.08:27:59.80#ibcon#read 3, iclass 15, count 0 2006.197.08:27:59.80#ibcon#about to read 4, iclass 15, count 0 2006.197.08:27:59.80#ibcon#read 4, iclass 15, count 0 2006.197.08:27:59.80#ibcon#about to read 5, iclass 15, count 0 2006.197.08:27:59.80#ibcon#read 5, iclass 15, count 0 2006.197.08:27:59.80#ibcon#about to read 6, iclass 15, count 0 2006.197.08:27:59.80#ibcon#read 6, iclass 15, count 0 2006.197.08:27:59.80#ibcon#end of sib2, iclass 15, count 0 2006.197.08:27:59.80#ibcon#*mode == 0, iclass 15, count 0 2006.197.08:27:59.80#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.197.08:27:59.80#ibcon#[25=USB\r\n] 2006.197.08:27:59.80#ibcon#*before write, iclass 15, count 0 2006.197.08:27:59.80#ibcon#enter sib2, iclass 15, count 0 2006.197.08:27:59.80#ibcon#flushed, iclass 15, count 0 2006.197.08:27:59.80#ibcon#about to write, iclass 15, count 0 2006.197.08:27:59.80#ibcon#wrote, iclass 15, count 0 2006.197.08:27:59.80#ibcon#about to read 3, iclass 15, count 0 2006.197.08:27:59.83#ibcon#read 3, iclass 15, count 0 2006.197.08:27:59.83#ibcon#about to read 4, iclass 15, count 0 2006.197.08:27:59.83#ibcon#read 4, iclass 15, count 0 2006.197.08:27:59.83#ibcon#about to read 5, iclass 15, count 0 2006.197.08:27:59.83#ibcon#read 5, iclass 15, count 0 2006.197.08:27:59.83#ibcon#about to read 6, iclass 15, count 0 2006.197.08:27:59.83#ibcon#read 6, iclass 15, count 0 2006.197.08:27:59.83#ibcon#end of sib2, iclass 15, count 0 2006.197.08:27:59.83#ibcon#*after write, iclass 15, count 0 2006.197.08:27:59.83#ibcon#*before return 0, iclass 15, count 0 2006.197.08:27:59.83#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.197.08:27:59.83#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.197.08:27:59.83#ibcon#about to clear, iclass 15 cls_cnt 0 2006.197.08:27:59.83#ibcon#cleared, iclass 15 cls_cnt 0 2006.197.08:27:59.83$vc4f8/valo=8,852.99 2006.197.08:27:59.83#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.197.08:27:59.83#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.197.08:27:59.83#ibcon#ireg 17 cls_cnt 0 2006.197.08:27:59.83#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.197.08:27:59.83#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.197.08:27:59.83#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.197.08:27:59.83#ibcon#enter wrdev, iclass 17, count 0 2006.197.08:27:59.83#ibcon#first serial, iclass 17, count 0 2006.197.08:27:59.83#ibcon#enter sib2, iclass 17, count 0 2006.197.08:27:59.83#ibcon#flushed, iclass 17, count 0 2006.197.08:27:59.83#ibcon#about to write, iclass 17, count 0 2006.197.08:27:59.83#ibcon#wrote, iclass 17, count 0 2006.197.08:27:59.83#ibcon#about to read 3, iclass 17, count 0 2006.197.08:27:59.85#ibcon#read 3, iclass 17, count 0 2006.197.08:27:59.85#ibcon#about to read 4, iclass 17, count 0 2006.197.08:27:59.85#ibcon#read 4, iclass 17, count 0 2006.197.08:27:59.85#ibcon#about to read 5, iclass 17, count 0 2006.197.08:27:59.85#ibcon#read 5, iclass 17, count 0 2006.197.08:27:59.85#ibcon#about to read 6, iclass 17, count 0 2006.197.08:27:59.85#ibcon#read 6, iclass 17, count 0 2006.197.08:27:59.85#ibcon#end of sib2, iclass 17, count 0 2006.197.08:27:59.85#ibcon#*mode == 0, iclass 17, count 0 2006.197.08:27:59.85#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.197.08:27:59.85#ibcon#[26=FRQ=08,852.99\r\n] 2006.197.08:27:59.85#ibcon#*before write, iclass 17, count 0 2006.197.08:27:59.85#ibcon#enter sib2, iclass 17, count 0 2006.197.08:27:59.85#ibcon#flushed, iclass 17, count 0 2006.197.08:27:59.85#ibcon#about to write, iclass 17, count 0 2006.197.08:27:59.85#ibcon#wrote, iclass 17, count 0 2006.197.08:27:59.85#ibcon#about to read 3, iclass 17, count 0 2006.197.08:27:59.89#ibcon#read 3, iclass 17, count 0 2006.197.08:27:59.89#ibcon#about to read 4, iclass 17, count 0 2006.197.08:27:59.89#ibcon#read 4, iclass 17, count 0 2006.197.08:27:59.89#ibcon#about to read 5, iclass 17, count 0 2006.197.08:27:59.89#ibcon#read 5, iclass 17, count 0 2006.197.08:27:59.89#ibcon#about to read 6, iclass 17, count 0 2006.197.08:27:59.89#ibcon#read 6, iclass 17, count 0 2006.197.08:27:59.89#ibcon#end of sib2, iclass 17, count 0 2006.197.08:27:59.89#ibcon#*after write, iclass 17, count 0 2006.197.08:27:59.89#ibcon#*before return 0, iclass 17, count 0 2006.197.08:27:59.89#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.197.08:27:59.89#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.197.08:27:59.89#ibcon#about to clear, iclass 17 cls_cnt 0 2006.197.08:27:59.89#ibcon#cleared, iclass 17 cls_cnt 0 2006.197.08:27:59.89$vc4f8/va=8,7 2006.197.08:27:59.89#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.197.08:27:59.89#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.197.08:27:59.89#ibcon#ireg 11 cls_cnt 2 2006.197.08:27:59.89#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.197.08:27:59.95#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.197.08:27:59.95#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.197.08:27:59.95#ibcon#enter wrdev, iclass 19, count 2 2006.197.08:27:59.95#ibcon#first serial, iclass 19, count 2 2006.197.08:27:59.95#ibcon#enter sib2, iclass 19, count 2 2006.197.08:27:59.95#ibcon#flushed, iclass 19, count 2 2006.197.08:27:59.95#ibcon#about to write, iclass 19, count 2 2006.197.08:27:59.95#ibcon#wrote, iclass 19, count 2 2006.197.08:27:59.95#ibcon#about to read 3, iclass 19, count 2 2006.197.08:27:59.97#ibcon#read 3, iclass 19, count 2 2006.197.08:27:59.97#ibcon#about to read 4, iclass 19, count 2 2006.197.08:27:59.97#ibcon#read 4, iclass 19, count 2 2006.197.08:27:59.97#ibcon#about to read 5, iclass 19, count 2 2006.197.08:27:59.97#ibcon#read 5, iclass 19, count 2 2006.197.08:27:59.97#ibcon#about to read 6, iclass 19, count 2 2006.197.08:27:59.97#ibcon#read 6, iclass 19, count 2 2006.197.08:27:59.97#ibcon#end of sib2, iclass 19, count 2 2006.197.08:27:59.97#ibcon#*mode == 0, iclass 19, count 2 2006.197.08:27:59.97#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.197.08:27:59.97#ibcon#[25=AT08-07\r\n] 2006.197.08:27:59.97#ibcon#*before write, iclass 19, count 2 2006.197.08:27:59.97#ibcon#enter sib2, iclass 19, count 2 2006.197.08:27:59.97#ibcon#flushed, iclass 19, count 2 2006.197.08:27:59.97#ibcon#about to write, iclass 19, count 2 2006.197.08:27:59.97#ibcon#wrote, iclass 19, count 2 2006.197.08:27:59.97#ibcon#about to read 3, iclass 19, count 2 2006.197.08:28:00.00#ibcon#read 3, iclass 19, count 2 2006.197.08:28:00.00#ibcon#about to read 4, iclass 19, count 2 2006.197.08:28:00.00#ibcon#read 4, iclass 19, count 2 2006.197.08:28:00.00#ibcon#about to read 5, iclass 19, count 2 2006.197.08:28:00.00#ibcon#read 5, iclass 19, count 2 2006.197.08:28:00.00#ibcon#about to read 6, iclass 19, count 2 2006.197.08:28:00.00#ibcon#read 6, iclass 19, count 2 2006.197.08:28:00.00#ibcon#end of sib2, iclass 19, count 2 2006.197.08:28:00.00#ibcon#*after write, iclass 19, count 2 2006.197.08:28:00.00#ibcon#*before return 0, iclass 19, count 2 2006.197.08:28:00.00#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.197.08:28:00.00#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.197.08:28:00.00#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.197.08:28:00.00#ibcon#ireg 7 cls_cnt 0 2006.197.08:28:00.00#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.197.08:28:00.12#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.197.08:28:00.12#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.197.08:28:00.12#ibcon#enter wrdev, iclass 19, count 0 2006.197.08:28:00.12#ibcon#first serial, iclass 19, count 0 2006.197.08:28:00.12#ibcon#enter sib2, iclass 19, count 0 2006.197.08:28:00.12#ibcon#flushed, iclass 19, count 0 2006.197.08:28:00.12#ibcon#about to write, iclass 19, count 0 2006.197.08:28:00.12#ibcon#wrote, iclass 19, count 0 2006.197.08:28:00.12#ibcon#about to read 3, iclass 19, count 0 2006.197.08:28:00.14#ibcon#read 3, iclass 19, count 0 2006.197.08:28:00.14#ibcon#about to read 4, iclass 19, count 0 2006.197.08:28:00.14#ibcon#read 4, iclass 19, count 0 2006.197.08:28:00.14#ibcon#about to read 5, iclass 19, count 0 2006.197.08:28:00.14#ibcon#read 5, iclass 19, count 0 2006.197.08:28:00.14#ibcon#about to read 6, iclass 19, count 0 2006.197.08:28:00.14#ibcon#read 6, iclass 19, count 0 2006.197.08:28:00.14#ibcon#end of sib2, iclass 19, count 0 2006.197.08:28:00.14#ibcon#*mode == 0, iclass 19, count 0 2006.197.08:28:00.14#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.197.08:28:00.14#ibcon#[25=USB\r\n] 2006.197.08:28:00.14#ibcon#*before write, iclass 19, count 0 2006.197.08:28:00.14#ibcon#enter sib2, iclass 19, count 0 2006.197.08:28:00.14#ibcon#flushed, iclass 19, count 0 2006.197.08:28:00.14#ibcon#about to write, iclass 19, count 0 2006.197.08:28:00.14#ibcon#wrote, iclass 19, count 0 2006.197.08:28:00.14#ibcon#about to read 3, iclass 19, count 0 2006.197.08:28:00.17#ibcon#read 3, iclass 19, count 0 2006.197.08:28:00.17#ibcon#about to read 4, iclass 19, count 0 2006.197.08:28:00.17#ibcon#read 4, iclass 19, count 0 2006.197.08:28:00.17#ibcon#about to read 5, iclass 19, count 0 2006.197.08:28:00.17#ibcon#read 5, iclass 19, count 0 2006.197.08:28:00.17#ibcon#about to read 6, iclass 19, count 0 2006.197.08:28:00.17#ibcon#read 6, iclass 19, count 0 2006.197.08:28:00.17#ibcon#end of sib2, iclass 19, count 0 2006.197.08:28:00.17#ibcon#*after write, iclass 19, count 0 2006.197.08:28:00.17#ibcon#*before return 0, iclass 19, count 0 2006.197.08:28:00.17#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.197.08:28:00.17#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.197.08:28:00.17#ibcon#about to clear, iclass 19 cls_cnt 0 2006.197.08:28:00.17#ibcon#cleared, iclass 19 cls_cnt 0 2006.197.08:28:00.17$vc4f8/vblo=1,632.99 2006.197.08:28:00.17#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.197.08:28:00.17#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.197.08:28:00.17#ibcon#ireg 17 cls_cnt 0 2006.197.08:28:00.17#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.197.08:28:00.17#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.197.08:28:00.17#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.197.08:28:00.17#ibcon#enter wrdev, iclass 21, count 0 2006.197.08:28:00.17#ibcon#first serial, iclass 21, count 0 2006.197.08:28:00.17#ibcon#enter sib2, iclass 21, count 0 2006.197.08:28:00.17#ibcon#flushed, iclass 21, count 0 2006.197.08:28:00.17#ibcon#about to write, iclass 21, count 0 2006.197.08:28:00.17#ibcon#wrote, iclass 21, count 0 2006.197.08:28:00.17#ibcon#about to read 3, iclass 21, count 0 2006.197.08:28:00.19#ibcon#read 3, iclass 21, count 0 2006.197.08:28:00.19#ibcon#about to read 4, iclass 21, count 0 2006.197.08:28:00.19#ibcon#read 4, iclass 21, count 0 2006.197.08:28:00.19#ibcon#about to read 5, iclass 21, count 0 2006.197.08:28:00.19#ibcon#read 5, iclass 21, count 0 2006.197.08:28:00.19#ibcon#about to read 6, iclass 21, count 0 2006.197.08:28:00.19#ibcon#read 6, iclass 21, count 0 2006.197.08:28:00.19#ibcon#end of sib2, iclass 21, count 0 2006.197.08:28:00.19#ibcon#*mode == 0, iclass 21, count 0 2006.197.08:28:00.19#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.197.08:28:00.19#ibcon#[28=FRQ=01,632.99\r\n] 2006.197.08:28:00.19#ibcon#*before write, iclass 21, count 0 2006.197.08:28:00.19#ibcon#enter sib2, iclass 21, count 0 2006.197.08:28:00.19#ibcon#flushed, iclass 21, count 0 2006.197.08:28:00.19#ibcon#about to write, iclass 21, count 0 2006.197.08:28:00.19#ibcon#wrote, iclass 21, count 0 2006.197.08:28:00.19#ibcon#about to read 3, iclass 21, count 0 2006.197.08:28:00.23#ibcon#read 3, iclass 21, count 0 2006.197.08:28:00.23#ibcon#about to read 4, iclass 21, count 0 2006.197.08:28:00.23#ibcon#read 4, iclass 21, count 0 2006.197.08:28:00.23#ibcon#about to read 5, iclass 21, count 0 2006.197.08:28:00.23#ibcon#read 5, iclass 21, count 0 2006.197.08:28:00.23#ibcon#about to read 6, iclass 21, count 0 2006.197.08:28:00.23#ibcon#read 6, iclass 21, count 0 2006.197.08:28:00.23#ibcon#end of sib2, iclass 21, count 0 2006.197.08:28:00.23#ibcon#*after write, iclass 21, count 0 2006.197.08:28:00.23#ibcon#*before return 0, iclass 21, count 0 2006.197.08:28:00.23#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.197.08:28:00.23#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.197.08:28:00.23#ibcon#about to clear, iclass 21 cls_cnt 0 2006.197.08:28:00.23#ibcon#cleared, iclass 21 cls_cnt 0 2006.197.08:28:00.23$vc4f8/vb=1,4 2006.197.08:28:00.23#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.197.08:28:00.23#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.197.08:28:00.23#ibcon#ireg 11 cls_cnt 2 2006.197.08:28:00.23#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.197.08:28:00.23#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.197.08:28:00.23#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.197.08:28:00.23#ibcon#enter wrdev, iclass 23, count 2 2006.197.08:28:00.23#ibcon#first serial, iclass 23, count 2 2006.197.08:28:00.23#ibcon#enter sib2, iclass 23, count 2 2006.197.08:28:00.23#ibcon#flushed, iclass 23, count 2 2006.197.08:28:00.23#ibcon#about to write, iclass 23, count 2 2006.197.08:28:00.23#ibcon#wrote, iclass 23, count 2 2006.197.08:28:00.23#ibcon#about to read 3, iclass 23, count 2 2006.197.08:28:00.25#ibcon#read 3, iclass 23, count 2 2006.197.08:28:00.25#ibcon#about to read 4, iclass 23, count 2 2006.197.08:28:00.25#ibcon#read 4, iclass 23, count 2 2006.197.08:28:00.25#ibcon#about to read 5, iclass 23, count 2 2006.197.08:28:00.25#ibcon#read 5, iclass 23, count 2 2006.197.08:28:00.25#ibcon#about to read 6, iclass 23, count 2 2006.197.08:28:00.25#ibcon#read 6, iclass 23, count 2 2006.197.08:28:00.25#ibcon#end of sib2, iclass 23, count 2 2006.197.08:28:00.25#ibcon#*mode == 0, iclass 23, count 2 2006.197.08:28:00.25#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.197.08:28:00.25#ibcon#[27=AT01-04\r\n] 2006.197.08:28:00.25#ibcon#*before write, iclass 23, count 2 2006.197.08:28:00.25#ibcon#enter sib2, iclass 23, count 2 2006.197.08:28:00.25#ibcon#flushed, iclass 23, count 2 2006.197.08:28:00.25#ibcon#about to write, iclass 23, count 2 2006.197.08:28:00.25#ibcon#wrote, iclass 23, count 2 2006.197.08:28:00.25#ibcon#about to read 3, iclass 23, count 2 2006.197.08:28:00.28#ibcon#read 3, iclass 23, count 2 2006.197.08:28:00.28#ibcon#about to read 4, iclass 23, count 2 2006.197.08:28:00.28#ibcon#read 4, iclass 23, count 2 2006.197.08:28:00.28#ibcon#about to read 5, iclass 23, count 2 2006.197.08:28:00.28#ibcon#read 5, iclass 23, count 2 2006.197.08:28:00.28#ibcon#about to read 6, iclass 23, count 2 2006.197.08:28:00.28#ibcon#read 6, iclass 23, count 2 2006.197.08:28:00.28#ibcon#end of sib2, iclass 23, count 2 2006.197.08:28:00.28#ibcon#*after write, iclass 23, count 2 2006.197.08:28:00.28#ibcon#*before return 0, iclass 23, count 2 2006.197.08:28:00.28#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.197.08:28:00.28#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.197.08:28:00.28#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.197.08:28:00.28#ibcon#ireg 7 cls_cnt 0 2006.197.08:28:00.28#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.197.08:28:00.40#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.197.08:28:00.40#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.197.08:28:00.40#ibcon#enter wrdev, iclass 23, count 0 2006.197.08:28:00.40#ibcon#first serial, iclass 23, count 0 2006.197.08:28:00.40#ibcon#enter sib2, iclass 23, count 0 2006.197.08:28:00.40#ibcon#flushed, iclass 23, count 0 2006.197.08:28:00.40#ibcon#about to write, iclass 23, count 0 2006.197.08:28:00.40#ibcon#wrote, iclass 23, count 0 2006.197.08:28:00.40#ibcon#about to read 3, iclass 23, count 0 2006.197.08:28:00.42#ibcon#read 3, iclass 23, count 0 2006.197.08:28:00.42#ibcon#about to read 4, iclass 23, count 0 2006.197.08:28:00.42#ibcon#read 4, iclass 23, count 0 2006.197.08:28:00.42#ibcon#about to read 5, iclass 23, count 0 2006.197.08:28:00.42#ibcon#read 5, iclass 23, count 0 2006.197.08:28:00.42#ibcon#about to read 6, iclass 23, count 0 2006.197.08:28:00.42#ibcon#read 6, iclass 23, count 0 2006.197.08:28:00.42#ibcon#end of sib2, iclass 23, count 0 2006.197.08:28:00.42#ibcon#*mode == 0, iclass 23, count 0 2006.197.08:28:00.42#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.197.08:28:00.42#ibcon#[27=USB\r\n] 2006.197.08:28:00.42#ibcon#*before write, iclass 23, count 0 2006.197.08:28:00.42#ibcon#enter sib2, iclass 23, count 0 2006.197.08:28:00.42#ibcon#flushed, iclass 23, count 0 2006.197.08:28:00.42#ibcon#about to write, iclass 23, count 0 2006.197.08:28:00.42#ibcon#wrote, iclass 23, count 0 2006.197.08:28:00.42#ibcon#about to read 3, iclass 23, count 0 2006.197.08:28:00.45#ibcon#read 3, iclass 23, count 0 2006.197.08:28:00.45#ibcon#about to read 4, iclass 23, count 0 2006.197.08:28:00.45#ibcon#read 4, iclass 23, count 0 2006.197.08:28:00.45#ibcon#about to read 5, iclass 23, count 0 2006.197.08:28:00.45#ibcon#read 5, iclass 23, count 0 2006.197.08:28:00.45#ibcon#about to read 6, iclass 23, count 0 2006.197.08:28:00.45#ibcon#read 6, iclass 23, count 0 2006.197.08:28:00.45#ibcon#end of sib2, iclass 23, count 0 2006.197.08:28:00.45#ibcon#*after write, iclass 23, count 0 2006.197.08:28:00.45#ibcon#*before return 0, iclass 23, count 0 2006.197.08:28:00.45#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.197.08:28:00.45#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.197.08:28:00.45#ibcon#about to clear, iclass 23 cls_cnt 0 2006.197.08:28:00.45#ibcon#cleared, iclass 23 cls_cnt 0 2006.197.08:28:00.45$vc4f8/vblo=2,640.99 2006.197.08:28:00.45#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.197.08:28:00.45#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.197.08:28:00.45#ibcon#ireg 17 cls_cnt 0 2006.197.08:28:00.45#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.197.08:28:00.45#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.197.08:28:00.45#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.197.08:28:00.45#ibcon#enter wrdev, iclass 25, count 0 2006.197.08:28:00.45#ibcon#first serial, iclass 25, count 0 2006.197.08:28:00.45#ibcon#enter sib2, iclass 25, count 0 2006.197.08:28:00.45#ibcon#flushed, iclass 25, count 0 2006.197.08:28:00.45#ibcon#about to write, iclass 25, count 0 2006.197.08:28:00.45#ibcon#wrote, iclass 25, count 0 2006.197.08:28:00.45#ibcon#about to read 3, iclass 25, count 0 2006.197.08:28:00.47#ibcon#read 3, iclass 25, count 0 2006.197.08:28:00.47#ibcon#about to read 4, iclass 25, count 0 2006.197.08:28:00.47#ibcon#read 4, iclass 25, count 0 2006.197.08:28:00.47#ibcon#about to read 5, iclass 25, count 0 2006.197.08:28:00.47#ibcon#read 5, iclass 25, count 0 2006.197.08:28:00.47#ibcon#about to read 6, iclass 25, count 0 2006.197.08:28:00.47#ibcon#read 6, iclass 25, count 0 2006.197.08:28:00.47#ibcon#end of sib2, iclass 25, count 0 2006.197.08:28:00.47#ibcon#*mode == 0, iclass 25, count 0 2006.197.08:28:00.47#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.197.08:28:00.47#ibcon#[28=FRQ=02,640.99\r\n] 2006.197.08:28:00.47#ibcon#*before write, iclass 25, count 0 2006.197.08:28:00.47#ibcon#enter sib2, iclass 25, count 0 2006.197.08:28:00.47#ibcon#flushed, iclass 25, count 0 2006.197.08:28:00.47#ibcon#about to write, iclass 25, count 0 2006.197.08:28:00.47#ibcon#wrote, iclass 25, count 0 2006.197.08:28:00.47#ibcon#about to read 3, iclass 25, count 0 2006.197.08:28:00.51#ibcon#read 3, iclass 25, count 0 2006.197.08:28:00.51#ibcon#about to read 4, iclass 25, count 0 2006.197.08:28:00.51#ibcon#read 4, iclass 25, count 0 2006.197.08:28:00.51#ibcon#about to read 5, iclass 25, count 0 2006.197.08:28:00.51#ibcon#read 5, iclass 25, count 0 2006.197.08:28:00.51#ibcon#about to read 6, iclass 25, count 0 2006.197.08:28:00.51#ibcon#read 6, iclass 25, count 0 2006.197.08:28:00.51#ibcon#end of sib2, iclass 25, count 0 2006.197.08:28:00.51#ibcon#*after write, iclass 25, count 0 2006.197.08:28:00.51#ibcon#*before return 0, iclass 25, count 0 2006.197.08:28:00.51#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.197.08:28:00.51#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.197.08:28:00.51#ibcon#about to clear, iclass 25 cls_cnt 0 2006.197.08:28:00.51#ibcon#cleared, iclass 25 cls_cnt 0 2006.197.08:28:00.51$vc4f8/vb=2,4 2006.197.08:28:00.51#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.197.08:28:00.51#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.197.08:28:00.51#ibcon#ireg 11 cls_cnt 2 2006.197.08:28:00.51#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.197.08:28:00.57#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.197.08:28:00.57#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.197.08:28:00.57#ibcon#enter wrdev, iclass 27, count 2 2006.197.08:28:00.57#ibcon#first serial, iclass 27, count 2 2006.197.08:28:00.57#ibcon#enter sib2, iclass 27, count 2 2006.197.08:28:00.57#ibcon#flushed, iclass 27, count 2 2006.197.08:28:00.57#ibcon#about to write, iclass 27, count 2 2006.197.08:28:00.57#ibcon#wrote, iclass 27, count 2 2006.197.08:28:00.57#ibcon#about to read 3, iclass 27, count 2 2006.197.08:28:00.59#ibcon#read 3, iclass 27, count 2 2006.197.08:28:00.59#ibcon#about to read 4, iclass 27, count 2 2006.197.08:28:00.59#ibcon#read 4, iclass 27, count 2 2006.197.08:28:00.59#ibcon#about to read 5, iclass 27, count 2 2006.197.08:28:00.59#ibcon#read 5, iclass 27, count 2 2006.197.08:28:00.59#ibcon#about to read 6, iclass 27, count 2 2006.197.08:28:00.59#ibcon#read 6, iclass 27, count 2 2006.197.08:28:00.59#ibcon#end of sib2, iclass 27, count 2 2006.197.08:28:00.59#ibcon#*mode == 0, iclass 27, count 2 2006.197.08:28:00.59#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.197.08:28:00.59#ibcon#[27=AT02-04\r\n] 2006.197.08:28:00.59#ibcon#*before write, iclass 27, count 2 2006.197.08:28:00.59#ibcon#enter sib2, iclass 27, count 2 2006.197.08:28:00.59#ibcon#flushed, iclass 27, count 2 2006.197.08:28:00.59#ibcon#about to write, iclass 27, count 2 2006.197.08:28:00.59#ibcon#wrote, iclass 27, count 2 2006.197.08:28:00.59#ibcon#about to read 3, iclass 27, count 2 2006.197.08:28:00.62#ibcon#read 3, iclass 27, count 2 2006.197.08:28:00.62#ibcon#about to read 4, iclass 27, count 2 2006.197.08:28:00.62#ibcon#read 4, iclass 27, count 2 2006.197.08:28:00.62#ibcon#about to read 5, iclass 27, count 2 2006.197.08:28:00.62#ibcon#read 5, iclass 27, count 2 2006.197.08:28:00.62#ibcon#about to read 6, iclass 27, count 2 2006.197.08:28:00.62#ibcon#read 6, iclass 27, count 2 2006.197.08:28:00.62#ibcon#end of sib2, iclass 27, count 2 2006.197.08:28:00.62#ibcon#*after write, iclass 27, count 2 2006.197.08:28:00.62#ibcon#*before return 0, iclass 27, count 2 2006.197.08:28:00.62#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.197.08:28:00.62#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.197.08:28:00.62#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.197.08:28:00.62#ibcon#ireg 7 cls_cnt 0 2006.197.08:28:00.62#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.197.08:28:00.74#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.197.08:28:00.74#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.197.08:28:00.74#ibcon#enter wrdev, iclass 27, count 0 2006.197.08:28:00.74#ibcon#first serial, iclass 27, count 0 2006.197.08:28:00.74#ibcon#enter sib2, iclass 27, count 0 2006.197.08:28:00.74#ibcon#flushed, iclass 27, count 0 2006.197.08:28:00.74#ibcon#about to write, iclass 27, count 0 2006.197.08:28:00.74#ibcon#wrote, iclass 27, count 0 2006.197.08:28:00.74#ibcon#about to read 3, iclass 27, count 0 2006.197.08:28:00.76#ibcon#read 3, iclass 27, count 0 2006.197.08:28:00.76#ibcon#about to read 4, iclass 27, count 0 2006.197.08:28:00.76#ibcon#read 4, iclass 27, count 0 2006.197.08:28:00.76#ibcon#about to read 5, iclass 27, count 0 2006.197.08:28:00.76#ibcon#read 5, iclass 27, count 0 2006.197.08:28:00.76#ibcon#about to read 6, iclass 27, count 0 2006.197.08:28:00.76#ibcon#read 6, iclass 27, count 0 2006.197.08:28:00.76#ibcon#end of sib2, iclass 27, count 0 2006.197.08:28:00.76#ibcon#*mode == 0, iclass 27, count 0 2006.197.08:28:00.76#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.197.08:28:00.76#ibcon#[27=USB\r\n] 2006.197.08:28:00.76#ibcon#*before write, iclass 27, count 0 2006.197.08:28:00.76#ibcon#enter sib2, iclass 27, count 0 2006.197.08:28:00.76#ibcon#flushed, iclass 27, count 0 2006.197.08:28:00.76#ibcon#about to write, iclass 27, count 0 2006.197.08:28:00.76#ibcon#wrote, iclass 27, count 0 2006.197.08:28:00.76#ibcon#about to read 3, iclass 27, count 0 2006.197.08:28:00.79#ibcon#read 3, iclass 27, count 0 2006.197.08:28:00.79#ibcon#about to read 4, iclass 27, count 0 2006.197.08:28:00.79#ibcon#read 4, iclass 27, count 0 2006.197.08:28:00.79#ibcon#about to read 5, iclass 27, count 0 2006.197.08:28:00.79#ibcon#read 5, iclass 27, count 0 2006.197.08:28:00.79#ibcon#about to read 6, iclass 27, count 0 2006.197.08:28:00.79#ibcon#read 6, iclass 27, count 0 2006.197.08:28:00.79#ibcon#end of sib2, iclass 27, count 0 2006.197.08:28:00.79#ibcon#*after write, iclass 27, count 0 2006.197.08:28:00.79#ibcon#*before return 0, iclass 27, count 0 2006.197.08:28:00.79#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.197.08:28:00.79#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.197.08:28:00.79#ibcon#about to clear, iclass 27 cls_cnt 0 2006.197.08:28:00.79#ibcon#cleared, iclass 27 cls_cnt 0 2006.197.08:28:00.79$vc4f8/vblo=3,656.99 2006.197.08:28:00.79#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.197.08:28:00.79#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.197.08:28:00.79#ibcon#ireg 17 cls_cnt 0 2006.197.08:28:00.79#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.197.08:28:00.79#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.197.08:28:00.79#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.197.08:28:00.79#ibcon#enter wrdev, iclass 29, count 0 2006.197.08:28:00.79#ibcon#first serial, iclass 29, count 0 2006.197.08:28:00.79#ibcon#enter sib2, iclass 29, count 0 2006.197.08:28:00.79#ibcon#flushed, iclass 29, count 0 2006.197.08:28:00.79#ibcon#about to write, iclass 29, count 0 2006.197.08:28:00.79#ibcon#wrote, iclass 29, count 0 2006.197.08:28:00.79#ibcon#about to read 3, iclass 29, count 0 2006.197.08:28:00.81#ibcon#read 3, iclass 29, count 0 2006.197.08:28:00.81#ibcon#about to read 4, iclass 29, count 0 2006.197.08:28:00.81#ibcon#read 4, iclass 29, count 0 2006.197.08:28:00.81#ibcon#about to read 5, iclass 29, count 0 2006.197.08:28:00.81#ibcon#read 5, iclass 29, count 0 2006.197.08:28:00.81#ibcon#about to read 6, iclass 29, count 0 2006.197.08:28:00.81#ibcon#read 6, iclass 29, count 0 2006.197.08:28:00.81#ibcon#end of sib2, iclass 29, count 0 2006.197.08:28:00.81#ibcon#*mode == 0, iclass 29, count 0 2006.197.08:28:00.81#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.197.08:28:00.81#ibcon#[28=FRQ=03,656.99\r\n] 2006.197.08:28:00.81#ibcon#*before write, iclass 29, count 0 2006.197.08:28:00.81#ibcon#enter sib2, iclass 29, count 0 2006.197.08:28:00.81#ibcon#flushed, iclass 29, count 0 2006.197.08:28:00.81#ibcon#about to write, iclass 29, count 0 2006.197.08:28:00.81#ibcon#wrote, iclass 29, count 0 2006.197.08:28:00.81#ibcon#about to read 3, iclass 29, count 0 2006.197.08:28:00.85#ibcon#read 3, iclass 29, count 0 2006.197.08:28:00.85#ibcon#about to read 4, iclass 29, count 0 2006.197.08:28:00.85#ibcon#read 4, iclass 29, count 0 2006.197.08:28:00.85#ibcon#about to read 5, iclass 29, count 0 2006.197.08:28:00.85#ibcon#read 5, iclass 29, count 0 2006.197.08:28:00.85#ibcon#about to read 6, iclass 29, count 0 2006.197.08:28:00.85#ibcon#read 6, iclass 29, count 0 2006.197.08:28:00.85#ibcon#end of sib2, iclass 29, count 0 2006.197.08:28:00.85#ibcon#*after write, iclass 29, count 0 2006.197.08:28:00.85#ibcon#*before return 0, iclass 29, count 0 2006.197.08:28:00.85#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.197.08:28:00.85#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.197.08:28:00.85#ibcon#about to clear, iclass 29 cls_cnt 0 2006.197.08:28:00.85#ibcon#cleared, iclass 29 cls_cnt 0 2006.197.08:28:00.85$vc4f8/vb=3,4 2006.197.08:28:00.85#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.197.08:28:00.85#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.197.08:28:00.85#ibcon#ireg 11 cls_cnt 2 2006.197.08:28:00.85#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.197.08:28:00.91#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.197.08:28:00.91#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.197.08:28:00.91#ibcon#enter wrdev, iclass 31, count 2 2006.197.08:28:00.91#ibcon#first serial, iclass 31, count 2 2006.197.08:28:00.91#ibcon#enter sib2, iclass 31, count 2 2006.197.08:28:00.91#ibcon#flushed, iclass 31, count 2 2006.197.08:28:00.91#ibcon#about to write, iclass 31, count 2 2006.197.08:28:00.91#ibcon#wrote, iclass 31, count 2 2006.197.08:28:00.91#ibcon#about to read 3, iclass 31, count 2 2006.197.08:28:00.93#ibcon#read 3, iclass 31, count 2 2006.197.08:28:00.93#ibcon#about to read 4, iclass 31, count 2 2006.197.08:28:00.93#ibcon#read 4, iclass 31, count 2 2006.197.08:28:00.93#ibcon#about to read 5, iclass 31, count 2 2006.197.08:28:00.93#ibcon#read 5, iclass 31, count 2 2006.197.08:28:00.93#ibcon#about to read 6, iclass 31, count 2 2006.197.08:28:00.93#ibcon#read 6, iclass 31, count 2 2006.197.08:28:00.93#ibcon#end of sib2, iclass 31, count 2 2006.197.08:28:00.93#ibcon#*mode == 0, iclass 31, count 2 2006.197.08:28:00.93#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.197.08:28:00.93#ibcon#[27=AT03-04\r\n] 2006.197.08:28:00.93#ibcon#*before write, iclass 31, count 2 2006.197.08:28:00.93#ibcon#enter sib2, iclass 31, count 2 2006.197.08:28:00.93#ibcon#flushed, iclass 31, count 2 2006.197.08:28:00.93#ibcon#about to write, iclass 31, count 2 2006.197.08:28:00.93#ibcon#wrote, iclass 31, count 2 2006.197.08:28:00.93#ibcon#about to read 3, iclass 31, count 2 2006.197.08:28:00.96#ibcon#read 3, iclass 31, count 2 2006.197.08:28:00.96#ibcon#about to read 4, iclass 31, count 2 2006.197.08:28:00.96#ibcon#read 4, iclass 31, count 2 2006.197.08:28:00.96#ibcon#about to read 5, iclass 31, count 2 2006.197.08:28:00.96#ibcon#read 5, iclass 31, count 2 2006.197.08:28:00.96#ibcon#about to read 6, iclass 31, count 2 2006.197.08:28:00.96#ibcon#read 6, iclass 31, count 2 2006.197.08:28:00.96#ibcon#end of sib2, iclass 31, count 2 2006.197.08:28:00.96#ibcon#*after write, iclass 31, count 2 2006.197.08:28:00.96#ibcon#*before return 0, iclass 31, count 2 2006.197.08:28:00.96#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.197.08:28:00.96#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.197.08:28:00.96#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.197.08:28:00.96#ibcon#ireg 7 cls_cnt 0 2006.197.08:28:00.96#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.197.08:28:01.08#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.197.08:28:01.08#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.197.08:28:01.08#ibcon#enter wrdev, iclass 31, count 0 2006.197.08:28:01.08#ibcon#first serial, iclass 31, count 0 2006.197.08:28:01.08#ibcon#enter sib2, iclass 31, count 0 2006.197.08:28:01.08#ibcon#flushed, iclass 31, count 0 2006.197.08:28:01.08#ibcon#about to write, iclass 31, count 0 2006.197.08:28:01.08#ibcon#wrote, iclass 31, count 0 2006.197.08:28:01.08#ibcon#about to read 3, iclass 31, count 0 2006.197.08:28:01.10#ibcon#read 3, iclass 31, count 0 2006.197.08:28:01.10#ibcon#about to read 4, iclass 31, count 0 2006.197.08:28:01.10#ibcon#read 4, iclass 31, count 0 2006.197.08:28:01.10#ibcon#about to read 5, iclass 31, count 0 2006.197.08:28:01.10#ibcon#read 5, iclass 31, count 0 2006.197.08:28:01.10#ibcon#about to read 6, iclass 31, count 0 2006.197.08:28:01.10#ibcon#read 6, iclass 31, count 0 2006.197.08:28:01.10#ibcon#end of sib2, iclass 31, count 0 2006.197.08:28:01.10#ibcon#*mode == 0, iclass 31, count 0 2006.197.08:28:01.10#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.197.08:28:01.10#ibcon#[27=USB\r\n] 2006.197.08:28:01.10#ibcon#*before write, iclass 31, count 0 2006.197.08:28:01.10#ibcon#enter sib2, iclass 31, count 0 2006.197.08:28:01.10#ibcon#flushed, iclass 31, count 0 2006.197.08:28:01.10#ibcon#about to write, iclass 31, count 0 2006.197.08:28:01.10#ibcon#wrote, iclass 31, count 0 2006.197.08:28:01.10#ibcon#about to read 3, iclass 31, count 0 2006.197.08:28:01.13#ibcon#read 3, iclass 31, count 0 2006.197.08:28:01.13#ibcon#about to read 4, iclass 31, count 0 2006.197.08:28:01.13#ibcon#read 4, iclass 31, count 0 2006.197.08:28:01.13#ibcon#about to read 5, iclass 31, count 0 2006.197.08:28:01.13#ibcon#read 5, iclass 31, count 0 2006.197.08:28:01.13#ibcon#about to read 6, iclass 31, count 0 2006.197.08:28:01.13#ibcon#read 6, iclass 31, count 0 2006.197.08:28:01.13#ibcon#end of sib2, iclass 31, count 0 2006.197.08:28:01.13#ibcon#*after write, iclass 31, count 0 2006.197.08:28:01.13#ibcon#*before return 0, iclass 31, count 0 2006.197.08:28:01.13#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.197.08:28:01.13#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.197.08:28:01.13#ibcon#about to clear, iclass 31 cls_cnt 0 2006.197.08:28:01.13#ibcon#cleared, iclass 31 cls_cnt 0 2006.197.08:28:01.13$vc4f8/vblo=4,712.99 2006.197.08:28:01.13#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.197.08:28:01.13#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.197.08:28:01.13#ibcon#ireg 17 cls_cnt 0 2006.197.08:28:01.13#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.197.08:28:01.13#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.197.08:28:01.13#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.197.08:28:01.13#ibcon#enter wrdev, iclass 33, count 0 2006.197.08:28:01.13#ibcon#first serial, iclass 33, count 0 2006.197.08:28:01.13#ibcon#enter sib2, iclass 33, count 0 2006.197.08:28:01.13#ibcon#flushed, iclass 33, count 0 2006.197.08:28:01.13#ibcon#about to write, iclass 33, count 0 2006.197.08:28:01.13#ibcon#wrote, iclass 33, count 0 2006.197.08:28:01.13#ibcon#about to read 3, iclass 33, count 0 2006.197.08:28:01.15#ibcon#read 3, iclass 33, count 0 2006.197.08:28:01.15#ibcon#about to read 4, iclass 33, count 0 2006.197.08:28:01.15#ibcon#read 4, iclass 33, count 0 2006.197.08:28:01.15#ibcon#about to read 5, iclass 33, count 0 2006.197.08:28:01.15#ibcon#read 5, iclass 33, count 0 2006.197.08:28:01.15#ibcon#about to read 6, iclass 33, count 0 2006.197.08:28:01.15#ibcon#read 6, iclass 33, count 0 2006.197.08:28:01.15#ibcon#end of sib2, iclass 33, count 0 2006.197.08:28:01.15#ibcon#*mode == 0, iclass 33, count 0 2006.197.08:28:01.15#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.197.08:28:01.15#ibcon#[28=FRQ=04,712.99\r\n] 2006.197.08:28:01.15#ibcon#*before write, iclass 33, count 0 2006.197.08:28:01.15#ibcon#enter sib2, iclass 33, count 0 2006.197.08:28:01.15#ibcon#flushed, iclass 33, count 0 2006.197.08:28:01.15#ibcon#about to write, iclass 33, count 0 2006.197.08:28:01.15#ibcon#wrote, iclass 33, count 0 2006.197.08:28:01.15#ibcon#about to read 3, iclass 33, count 0 2006.197.08:28:01.19#ibcon#read 3, iclass 33, count 0 2006.197.08:28:01.19#ibcon#about to read 4, iclass 33, count 0 2006.197.08:28:01.19#ibcon#read 4, iclass 33, count 0 2006.197.08:28:01.19#ibcon#about to read 5, iclass 33, count 0 2006.197.08:28:01.19#ibcon#read 5, iclass 33, count 0 2006.197.08:28:01.19#ibcon#about to read 6, iclass 33, count 0 2006.197.08:28:01.19#ibcon#read 6, iclass 33, count 0 2006.197.08:28:01.19#ibcon#end of sib2, iclass 33, count 0 2006.197.08:28:01.19#ibcon#*after write, iclass 33, count 0 2006.197.08:28:01.19#ibcon#*before return 0, iclass 33, count 0 2006.197.08:28:01.19#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.197.08:28:01.19#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.197.08:28:01.19#ibcon#about to clear, iclass 33 cls_cnt 0 2006.197.08:28:01.19#ibcon#cleared, iclass 33 cls_cnt 0 2006.197.08:28:01.19$vc4f8/vb=4,4 2006.197.08:28:01.19#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.197.08:28:01.19#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.197.08:28:01.19#ibcon#ireg 11 cls_cnt 2 2006.197.08:28:01.19#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.197.08:28:01.25#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.197.08:28:01.25#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.197.08:28:01.25#ibcon#enter wrdev, iclass 35, count 2 2006.197.08:28:01.25#ibcon#first serial, iclass 35, count 2 2006.197.08:28:01.25#ibcon#enter sib2, iclass 35, count 2 2006.197.08:28:01.25#ibcon#flushed, iclass 35, count 2 2006.197.08:28:01.25#ibcon#about to write, iclass 35, count 2 2006.197.08:28:01.25#ibcon#wrote, iclass 35, count 2 2006.197.08:28:01.25#ibcon#about to read 3, iclass 35, count 2 2006.197.08:28:01.27#ibcon#read 3, iclass 35, count 2 2006.197.08:28:01.27#ibcon#about to read 4, iclass 35, count 2 2006.197.08:28:01.27#ibcon#read 4, iclass 35, count 2 2006.197.08:28:01.27#ibcon#about to read 5, iclass 35, count 2 2006.197.08:28:01.27#ibcon#read 5, iclass 35, count 2 2006.197.08:28:01.27#ibcon#about to read 6, iclass 35, count 2 2006.197.08:28:01.27#ibcon#read 6, iclass 35, count 2 2006.197.08:28:01.27#ibcon#end of sib2, iclass 35, count 2 2006.197.08:28:01.27#ibcon#*mode == 0, iclass 35, count 2 2006.197.08:28:01.27#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.197.08:28:01.27#ibcon#[27=AT04-04\r\n] 2006.197.08:28:01.27#ibcon#*before write, iclass 35, count 2 2006.197.08:28:01.27#ibcon#enter sib2, iclass 35, count 2 2006.197.08:28:01.27#ibcon#flushed, iclass 35, count 2 2006.197.08:28:01.27#ibcon#about to write, iclass 35, count 2 2006.197.08:28:01.27#ibcon#wrote, iclass 35, count 2 2006.197.08:28:01.27#ibcon#about to read 3, iclass 35, count 2 2006.197.08:28:01.30#ibcon#read 3, iclass 35, count 2 2006.197.08:28:01.30#ibcon#about to read 4, iclass 35, count 2 2006.197.08:28:01.30#ibcon#read 4, iclass 35, count 2 2006.197.08:28:01.30#ibcon#about to read 5, iclass 35, count 2 2006.197.08:28:01.30#ibcon#read 5, iclass 35, count 2 2006.197.08:28:01.30#ibcon#about to read 6, iclass 35, count 2 2006.197.08:28:01.30#ibcon#read 6, iclass 35, count 2 2006.197.08:28:01.30#ibcon#end of sib2, iclass 35, count 2 2006.197.08:28:01.30#ibcon#*after write, iclass 35, count 2 2006.197.08:28:01.30#ibcon#*before return 0, iclass 35, count 2 2006.197.08:28:01.30#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.197.08:28:01.30#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.197.08:28:01.30#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.197.08:28:01.30#ibcon#ireg 7 cls_cnt 0 2006.197.08:28:01.30#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.197.08:28:01.42#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.197.08:28:01.42#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.197.08:28:01.42#ibcon#enter wrdev, iclass 35, count 0 2006.197.08:28:01.42#ibcon#first serial, iclass 35, count 0 2006.197.08:28:01.42#ibcon#enter sib2, iclass 35, count 0 2006.197.08:28:01.42#ibcon#flushed, iclass 35, count 0 2006.197.08:28:01.42#ibcon#about to write, iclass 35, count 0 2006.197.08:28:01.42#ibcon#wrote, iclass 35, count 0 2006.197.08:28:01.42#ibcon#about to read 3, iclass 35, count 0 2006.197.08:28:01.44#ibcon#read 3, iclass 35, count 0 2006.197.08:28:01.44#ibcon#about to read 4, iclass 35, count 0 2006.197.08:28:01.44#ibcon#read 4, iclass 35, count 0 2006.197.08:28:01.44#ibcon#about to read 5, iclass 35, count 0 2006.197.08:28:01.44#ibcon#read 5, iclass 35, count 0 2006.197.08:28:01.44#ibcon#about to read 6, iclass 35, count 0 2006.197.08:28:01.44#ibcon#read 6, iclass 35, count 0 2006.197.08:28:01.44#ibcon#end of sib2, iclass 35, count 0 2006.197.08:28:01.44#ibcon#*mode == 0, iclass 35, count 0 2006.197.08:28:01.44#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.197.08:28:01.44#ibcon#[27=USB\r\n] 2006.197.08:28:01.44#ibcon#*before write, iclass 35, count 0 2006.197.08:28:01.44#ibcon#enter sib2, iclass 35, count 0 2006.197.08:28:01.44#ibcon#flushed, iclass 35, count 0 2006.197.08:28:01.44#ibcon#about to write, iclass 35, count 0 2006.197.08:28:01.44#ibcon#wrote, iclass 35, count 0 2006.197.08:28:01.44#ibcon#about to read 3, iclass 35, count 0 2006.197.08:28:01.47#ibcon#read 3, iclass 35, count 0 2006.197.08:28:01.47#ibcon#about to read 4, iclass 35, count 0 2006.197.08:28:01.47#ibcon#read 4, iclass 35, count 0 2006.197.08:28:01.47#ibcon#about to read 5, iclass 35, count 0 2006.197.08:28:01.47#ibcon#read 5, iclass 35, count 0 2006.197.08:28:01.47#ibcon#about to read 6, iclass 35, count 0 2006.197.08:28:01.47#ibcon#read 6, iclass 35, count 0 2006.197.08:28:01.47#ibcon#end of sib2, iclass 35, count 0 2006.197.08:28:01.47#ibcon#*after write, iclass 35, count 0 2006.197.08:28:01.47#ibcon#*before return 0, iclass 35, count 0 2006.197.08:28:01.47#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.197.08:28:01.47#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.197.08:28:01.47#ibcon#about to clear, iclass 35 cls_cnt 0 2006.197.08:28:01.47#ibcon#cleared, iclass 35 cls_cnt 0 2006.197.08:28:01.47$vc4f8/vblo=5,744.99 2006.197.08:28:01.47#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.197.08:28:01.47#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.197.08:28:01.47#ibcon#ireg 17 cls_cnt 0 2006.197.08:28:01.47#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.197.08:28:01.47#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.197.08:28:01.47#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.197.08:28:01.47#ibcon#enter wrdev, iclass 37, count 0 2006.197.08:28:01.47#ibcon#first serial, iclass 37, count 0 2006.197.08:28:01.47#ibcon#enter sib2, iclass 37, count 0 2006.197.08:28:01.47#ibcon#flushed, iclass 37, count 0 2006.197.08:28:01.47#ibcon#about to write, iclass 37, count 0 2006.197.08:28:01.47#ibcon#wrote, iclass 37, count 0 2006.197.08:28:01.47#ibcon#about to read 3, iclass 37, count 0 2006.197.08:28:01.49#ibcon#read 3, iclass 37, count 0 2006.197.08:28:01.49#ibcon#about to read 4, iclass 37, count 0 2006.197.08:28:01.49#ibcon#read 4, iclass 37, count 0 2006.197.08:28:01.49#ibcon#about to read 5, iclass 37, count 0 2006.197.08:28:01.49#ibcon#read 5, iclass 37, count 0 2006.197.08:28:01.49#ibcon#about to read 6, iclass 37, count 0 2006.197.08:28:01.49#ibcon#read 6, iclass 37, count 0 2006.197.08:28:01.49#ibcon#end of sib2, iclass 37, count 0 2006.197.08:28:01.49#ibcon#*mode == 0, iclass 37, count 0 2006.197.08:28:01.49#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.197.08:28:01.49#ibcon#[28=FRQ=05,744.99\r\n] 2006.197.08:28:01.49#ibcon#*before write, iclass 37, count 0 2006.197.08:28:01.49#ibcon#enter sib2, iclass 37, count 0 2006.197.08:28:01.49#ibcon#flushed, iclass 37, count 0 2006.197.08:28:01.49#ibcon#about to write, iclass 37, count 0 2006.197.08:28:01.49#ibcon#wrote, iclass 37, count 0 2006.197.08:28:01.49#ibcon#about to read 3, iclass 37, count 0 2006.197.08:28:01.53#ibcon#read 3, iclass 37, count 0 2006.197.08:28:01.53#ibcon#about to read 4, iclass 37, count 0 2006.197.08:28:01.53#ibcon#read 4, iclass 37, count 0 2006.197.08:28:01.53#ibcon#about to read 5, iclass 37, count 0 2006.197.08:28:01.53#ibcon#read 5, iclass 37, count 0 2006.197.08:28:01.53#ibcon#about to read 6, iclass 37, count 0 2006.197.08:28:01.53#ibcon#read 6, iclass 37, count 0 2006.197.08:28:01.53#ibcon#end of sib2, iclass 37, count 0 2006.197.08:28:01.53#ibcon#*after write, iclass 37, count 0 2006.197.08:28:01.53#ibcon#*before return 0, iclass 37, count 0 2006.197.08:28:01.53#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.197.08:28:01.53#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.197.08:28:01.53#ibcon#about to clear, iclass 37 cls_cnt 0 2006.197.08:28:01.53#ibcon#cleared, iclass 37 cls_cnt 0 2006.197.08:28:01.53$vc4f8/vb=5,4 2006.197.08:28:01.53#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.197.08:28:01.53#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.197.08:28:01.53#ibcon#ireg 11 cls_cnt 2 2006.197.08:28:01.53#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.197.08:28:01.59#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.197.08:28:01.59#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.197.08:28:01.59#ibcon#enter wrdev, iclass 39, count 2 2006.197.08:28:01.59#ibcon#first serial, iclass 39, count 2 2006.197.08:28:01.59#ibcon#enter sib2, iclass 39, count 2 2006.197.08:28:01.59#ibcon#flushed, iclass 39, count 2 2006.197.08:28:01.59#ibcon#about to write, iclass 39, count 2 2006.197.08:28:01.59#ibcon#wrote, iclass 39, count 2 2006.197.08:28:01.59#ibcon#about to read 3, iclass 39, count 2 2006.197.08:28:01.61#ibcon#read 3, iclass 39, count 2 2006.197.08:28:01.61#ibcon#about to read 4, iclass 39, count 2 2006.197.08:28:01.61#ibcon#read 4, iclass 39, count 2 2006.197.08:28:01.61#ibcon#about to read 5, iclass 39, count 2 2006.197.08:28:01.61#ibcon#read 5, iclass 39, count 2 2006.197.08:28:01.61#ibcon#about to read 6, iclass 39, count 2 2006.197.08:28:01.61#ibcon#read 6, iclass 39, count 2 2006.197.08:28:01.61#ibcon#end of sib2, iclass 39, count 2 2006.197.08:28:01.61#ibcon#*mode == 0, iclass 39, count 2 2006.197.08:28:01.61#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.197.08:28:01.61#ibcon#[27=AT05-04\r\n] 2006.197.08:28:01.61#ibcon#*before write, iclass 39, count 2 2006.197.08:28:01.61#ibcon#enter sib2, iclass 39, count 2 2006.197.08:28:01.61#ibcon#flushed, iclass 39, count 2 2006.197.08:28:01.61#ibcon#about to write, iclass 39, count 2 2006.197.08:28:01.61#ibcon#wrote, iclass 39, count 2 2006.197.08:28:01.61#ibcon#about to read 3, iclass 39, count 2 2006.197.08:28:01.64#ibcon#read 3, iclass 39, count 2 2006.197.08:28:01.64#ibcon#about to read 4, iclass 39, count 2 2006.197.08:28:01.64#ibcon#read 4, iclass 39, count 2 2006.197.08:28:01.64#ibcon#about to read 5, iclass 39, count 2 2006.197.08:28:01.64#ibcon#read 5, iclass 39, count 2 2006.197.08:28:01.64#ibcon#about to read 6, iclass 39, count 2 2006.197.08:28:01.64#ibcon#read 6, iclass 39, count 2 2006.197.08:28:01.64#ibcon#end of sib2, iclass 39, count 2 2006.197.08:28:01.64#ibcon#*after write, iclass 39, count 2 2006.197.08:28:01.64#ibcon#*before return 0, iclass 39, count 2 2006.197.08:28:01.64#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.197.08:28:01.64#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.197.08:28:01.64#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.197.08:28:01.64#ibcon#ireg 7 cls_cnt 0 2006.197.08:28:01.64#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.197.08:28:01.76#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.197.08:28:01.76#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.197.08:28:01.76#ibcon#enter wrdev, iclass 39, count 0 2006.197.08:28:01.76#ibcon#first serial, iclass 39, count 0 2006.197.08:28:01.76#ibcon#enter sib2, iclass 39, count 0 2006.197.08:28:01.76#ibcon#flushed, iclass 39, count 0 2006.197.08:28:01.76#ibcon#about to write, iclass 39, count 0 2006.197.08:28:01.76#ibcon#wrote, iclass 39, count 0 2006.197.08:28:01.76#ibcon#about to read 3, iclass 39, count 0 2006.197.08:28:01.78#ibcon#read 3, iclass 39, count 0 2006.197.08:28:01.78#ibcon#about to read 4, iclass 39, count 0 2006.197.08:28:01.78#ibcon#read 4, iclass 39, count 0 2006.197.08:28:01.78#ibcon#about to read 5, iclass 39, count 0 2006.197.08:28:01.78#ibcon#read 5, iclass 39, count 0 2006.197.08:28:01.78#ibcon#about to read 6, iclass 39, count 0 2006.197.08:28:01.78#ibcon#read 6, iclass 39, count 0 2006.197.08:28:01.78#ibcon#end of sib2, iclass 39, count 0 2006.197.08:28:01.78#ibcon#*mode == 0, iclass 39, count 0 2006.197.08:28:01.78#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.197.08:28:01.78#ibcon#[27=USB\r\n] 2006.197.08:28:01.78#ibcon#*before write, iclass 39, count 0 2006.197.08:28:01.78#ibcon#enter sib2, iclass 39, count 0 2006.197.08:28:01.78#ibcon#flushed, iclass 39, count 0 2006.197.08:28:01.78#ibcon#about to write, iclass 39, count 0 2006.197.08:28:01.78#ibcon#wrote, iclass 39, count 0 2006.197.08:28:01.78#ibcon#about to read 3, iclass 39, count 0 2006.197.08:28:01.81#ibcon#read 3, iclass 39, count 0 2006.197.08:28:01.81#ibcon#about to read 4, iclass 39, count 0 2006.197.08:28:01.81#ibcon#read 4, iclass 39, count 0 2006.197.08:28:01.81#ibcon#about to read 5, iclass 39, count 0 2006.197.08:28:01.81#ibcon#read 5, iclass 39, count 0 2006.197.08:28:01.81#ibcon#about to read 6, iclass 39, count 0 2006.197.08:28:01.81#ibcon#read 6, iclass 39, count 0 2006.197.08:28:01.81#ibcon#end of sib2, iclass 39, count 0 2006.197.08:28:01.81#ibcon#*after write, iclass 39, count 0 2006.197.08:28:01.81#ibcon#*before return 0, iclass 39, count 0 2006.197.08:28:01.81#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.197.08:28:01.81#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.197.08:28:01.81#ibcon#about to clear, iclass 39 cls_cnt 0 2006.197.08:28:01.81#ibcon#cleared, iclass 39 cls_cnt 0 2006.197.08:28:01.81$vc4f8/vblo=6,752.99 2006.197.08:28:01.81#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.197.08:28:01.81#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.197.08:28:01.81#ibcon#ireg 17 cls_cnt 0 2006.197.08:28:01.81#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.197.08:28:01.81#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.197.08:28:01.81#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.197.08:28:01.81#ibcon#enter wrdev, iclass 3, count 0 2006.197.08:28:01.81#ibcon#first serial, iclass 3, count 0 2006.197.08:28:01.81#ibcon#enter sib2, iclass 3, count 0 2006.197.08:28:01.81#ibcon#flushed, iclass 3, count 0 2006.197.08:28:01.81#ibcon#about to write, iclass 3, count 0 2006.197.08:28:01.81#ibcon#wrote, iclass 3, count 0 2006.197.08:28:01.81#ibcon#about to read 3, iclass 3, count 0 2006.197.08:28:01.83#ibcon#read 3, iclass 3, count 0 2006.197.08:28:01.83#ibcon#about to read 4, iclass 3, count 0 2006.197.08:28:01.83#ibcon#read 4, iclass 3, count 0 2006.197.08:28:01.83#ibcon#about to read 5, iclass 3, count 0 2006.197.08:28:01.83#ibcon#read 5, iclass 3, count 0 2006.197.08:28:01.83#ibcon#about to read 6, iclass 3, count 0 2006.197.08:28:01.83#ibcon#read 6, iclass 3, count 0 2006.197.08:28:01.83#ibcon#end of sib2, iclass 3, count 0 2006.197.08:28:01.83#ibcon#*mode == 0, iclass 3, count 0 2006.197.08:28:01.83#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.197.08:28:01.83#ibcon#[28=FRQ=06,752.99\r\n] 2006.197.08:28:01.83#ibcon#*before write, iclass 3, count 0 2006.197.08:28:01.83#ibcon#enter sib2, iclass 3, count 0 2006.197.08:28:01.83#ibcon#flushed, iclass 3, count 0 2006.197.08:28:01.83#ibcon#about to write, iclass 3, count 0 2006.197.08:28:01.83#ibcon#wrote, iclass 3, count 0 2006.197.08:28:01.83#ibcon#about to read 3, iclass 3, count 0 2006.197.08:28:01.87#ibcon#read 3, iclass 3, count 0 2006.197.08:28:01.87#ibcon#about to read 4, iclass 3, count 0 2006.197.08:28:01.87#ibcon#read 4, iclass 3, count 0 2006.197.08:28:01.87#ibcon#about to read 5, iclass 3, count 0 2006.197.08:28:01.87#ibcon#read 5, iclass 3, count 0 2006.197.08:28:01.87#ibcon#about to read 6, iclass 3, count 0 2006.197.08:28:01.87#ibcon#read 6, iclass 3, count 0 2006.197.08:28:01.87#ibcon#end of sib2, iclass 3, count 0 2006.197.08:28:01.87#ibcon#*after write, iclass 3, count 0 2006.197.08:28:01.87#ibcon#*before return 0, iclass 3, count 0 2006.197.08:28:01.87#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.197.08:28:01.87#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.197.08:28:01.87#ibcon#about to clear, iclass 3 cls_cnt 0 2006.197.08:28:01.87#ibcon#cleared, iclass 3 cls_cnt 0 2006.197.08:28:01.87$vc4f8/vb=6,4 2006.197.08:28:01.87#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.197.08:28:01.87#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.197.08:28:01.87#ibcon#ireg 11 cls_cnt 2 2006.197.08:28:01.87#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.197.08:28:01.93#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.197.08:28:01.93#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.197.08:28:01.93#ibcon#enter wrdev, iclass 5, count 2 2006.197.08:28:01.93#ibcon#first serial, iclass 5, count 2 2006.197.08:28:01.93#ibcon#enter sib2, iclass 5, count 2 2006.197.08:28:01.93#ibcon#flushed, iclass 5, count 2 2006.197.08:28:01.93#ibcon#about to write, iclass 5, count 2 2006.197.08:28:01.93#ibcon#wrote, iclass 5, count 2 2006.197.08:28:01.93#ibcon#about to read 3, iclass 5, count 2 2006.197.08:28:01.95#ibcon#read 3, iclass 5, count 2 2006.197.08:28:01.95#ibcon#about to read 4, iclass 5, count 2 2006.197.08:28:01.95#ibcon#read 4, iclass 5, count 2 2006.197.08:28:01.95#ibcon#about to read 5, iclass 5, count 2 2006.197.08:28:01.95#ibcon#read 5, iclass 5, count 2 2006.197.08:28:01.95#ibcon#about to read 6, iclass 5, count 2 2006.197.08:28:01.95#ibcon#read 6, iclass 5, count 2 2006.197.08:28:01.95#ibcon#end of sib2, iclass 5, count 2 2006.197.08:28:01.95#ibcon#*mode == 0, iclass 5, count 2 2006.197.08:28:01.95#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.197.08:28:01.95#ibcon#[27=AT06-04\r\n] 2006.197.08:28:01.95#ibcon#*before write, iclass 5, count 2 2006.197.08:28:01.95#ibcon#enter sib2, iclass 5, count 2 2006.197.08:28:01.95#ibcon#flushed, iclass 5, count 2 2006.197.08:28:01.95#ibcon#about to write, iclass 5, count 2 2006.197.08:28:01.95#ibcon#wrote, iclass 5, count 2 2006.197.08:28:01.95#ibcon#about to read 3, iclass 5, count 2 2006.197.08:28:01.98#ibcon#read 3, iclass 5, count 2 2006.197.08:28:01.98#ibcon#about to read 4, iclass 5, count 2 2006.197.08:28:01.98#ibcon#read 4, iclass 5, count 2 2006.197.08:28:01.98#ibcon#about to read 5, iclass 5, count 2 2006.197.08:28:01.98#ibcon#read 5, iclass 5, count 2 2006.197.08:28:01.98#ibcon#about to read 6, iclass 5, count 2 2006.197.08:28:01.98#ibcon#read 6, iclass 5, count 2 2006.197.08:28:01.98#ibcon#end of sib2, iclass 5, count 2 2006.197.08:28:01.98#ibcon#*after write, iclass 5, count 2 2006.197.08:28:01.98#ibcon#*before return 0, iclass 5, count 2 2006.197.08:28:01.98#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.197.08:28:01.98#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.197.08:28:01.98#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.197.08:28:01.98#ibcon#ireg 7 cls_cnt 0 2006.197.08:28:01.98#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.197.08:28:02.10#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.197.08:28:02.10#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.197.08:28:02.10#ibcon#enter wrdev, iclass 5, count 0 2006.197.08:28:02.10#ibcon#first serial, iclass 5, count 0 2006.197.08:28:02.10#ibcon#enter sib2, iclass 5, count 0 2006.197.08:28:02.10#ibcon#flushed, iclass 5, count 0 2006.197.08:28:02.10#ibcon#about to write, iclass 5, count 0 2006.197.08:28:02.10#ibcon#wrote, iclass 5, count 0 2006.197.08:28:02.10#ibcon#about to read 3, iclass 5, count 0 2006.197.08:28:02.12#ibcon#read 3, iclass 5, count 0 2006.197.08:28:02.12#ibcon#about to read 4, iclass 5, count 0 2006.197.08:28:02.12#ibcon#read 4, iclass 5, count 0 2006.197.08:28:02.12#ibcon#about to read 5, iclass 5, count 0 2006.197.08:28:02.12#ibcon#read 5, iclass 5, count 0 2006.197.08:28:02.12#ibcon#about to read 6, iclass 5, count 0 2006.197.08:28:02.12#ibcon#read 6, iclass 5, count 0 2006.197.08:28:02.12#ibcon#end of sib2, iclass 5, count 0 2006.197.08:28:02.12#ibcon#*mode == 0, iclass 5, count 0 2006.197.08:28:02.12#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.197.08:28:02.12#ibcon#[27=USB\r\n] 2006.197.08:28:02.12#ibcon#*before write, iclass 5, count 0 2006.197.08:28:02.12#ibcon#enter sib2, iclass 5, count 0 2006.197.08:28:02.12#ibcon#flushed, iclass 5, count 0 2006.197.08:28:02.12#ibcon#about to write, iclass 5, count 0 2006.197.08:28:02.12#ibcon#wrote, iclass 5, count 0 2006.197.08:28:02.12#ibcon#about to read 3, iclass 5, count 0 2006.197.08:28:02.15#ibcon#read 3, iclass 5, count 0 2006.197.08:28:02.15#ibcon#about to read 4, iclass 5, count 0 2006.197.08:28:02.15#ibcon#read 4, iclass 5, count 0 2006.197.08:28:02.15#ibcon#about to read 5, iclass 5, count 0 2006.197.08:28:02.15#ibcon#read 5, iclass 5, count 0 2006.197.08:28:02.15#ibcon#about to read 6, iclass 5, count 0 2006.197.08:28:02.15#ibcon#read 6, iclass 5, count 0 2006.197.08:28:02.15#ibcon#end of sib2, iclass 5, count 0 2006.197.08:28:02.15#ibcon#*after write, iclass 5, count 0 2006.197.08:28:02.15#ibcon#*before return 0, iclass 5, count 0 2006.197.08:28:02.15#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.197.08:28:02.15#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.197.08:28:02.15#ibcon#about to clear, iclass 5 cls_cnt 0 2006.197.08:28:02.15#ibcon#cleared, iclass 5 cls_cnt 0 2006.197.08:28:02.15$vc4f8/vabw=wide 2006.197.08:28:02.15#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.197.08:28:02.15#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.197.08:28:02.15#ibcon#ireg 8 cls_cnt 0 2006.197.08:28:02.15#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.197.08:28:02.15#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.197.08:28:02.15#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.197.08:28:02.15#ibcon#enter wrdev, iclass 7, count 0 2006.197.08:28:02.15#ibcon#first serial, iclass 7, count 0 2006.197.08:28:02.15#ibcon#enter sib2, iclass 7, count 0 2006.197.08:28:02.15#ibcon#flushed, iclass 7, count 0 2006.197.08:28:02.15#ibcon#about to write, iclass 7, count 0 2006.197.08:28:02.15#ibcon#wrote, iclass 7, count 0 2006.197.08:28:02.15#ibcon#about to read 3, iclass 7, count 0 2006.197.08:28:02.17#ibcon#read 3, iclass 7, count 0 2006.197.08:28:02.17#ibcon#about to read 4, iclass 7, count 0 2006.197.08:28:02.17#ibcon#read 4, iclass 7, count 0 2006.197.08:28:02.17#ibcon#about to read 5, iclass 7, count 0 2006.197.08:28:02.17#ibcon#read 5, iclass 7, count 0 2006.197.08:28:02.17#ibcon#about to read 6, iclass 7, count 0 2006.197.08:28:02.17#ibcon#read 6, iclass 7, count 0 2006.197.08:28:02.17#ibcon#end of sib2, iclass 7, count 0 2006.197.08:28:02.17#ibcon#*mode == 0, iclass 7, count 0 2006.197.08:28:02.17#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.197.08:28:02.17#ibcon#[25=BW32\r\n] 2006.197.08:28:02.17#ibcon#*before write, iclass 7, count 0 2006.197.08:28:02.17#ibcon#enter sib2, iclass 7, count 0 2006.197.08:28:02.17#ibcon#flushed, iclass 7, count 0 2006.197.08:28:02.17#ibcon#about to write, iclass 7, count 0 2006.197.08:28:02.17#ibcon#wrote, iclass 7, count 0 2006.197.08:28:02.17#ibcon#about to read 3, iclass 7, count 0 2006.197.08:28:02.20#ibcon#read 3, iclass 7, count 0 2006.197.08:28:02.20#ibcon#about to read 4, iclass 7, count 0 2006.197.08:28:02.20#ibcon#read 4, iclass 7, count 0 2006.197.08:28:02.20#ibcon#about to read 5, iclass 7, count 0 2006.197.08:28:02.20#ibcon#read 5, iclass 7, count 0 2006.197.08:28:02.20#ibcon#about to read 6, iclass 7, count 0 2006.197.08:28:02.20#ibcon#read 6, iclass 7, count 0 2006.197.08:28:02.20#ibcon#end of sib2, iclass 7, count 0 2006.197.08:28:02.20#ibcon#*after write, iclass 7, count 0 2006.197.08:28:02.20#ibcon#*before return 0, iclass 7, count 0 2006.197.08:28:02.20#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.197.08:28:02.20#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.197.08:28:02.20#ibcon#about to clear, iclass 7 cls_cnt 0 2006.197.08:28:02.20#ibcon#cleared, iclass 7 cls_cnt 0 2006.197.08:28:02.20$vc4f8/vbbw=wide 2006.197.08:28:02.20#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.197.08:28:02.20#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.197.08:28:02.20#ibcon#ireg 8 cls_cnt 0 2006.197.08:28:02.20#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.197.08:28:02.27#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.197.08:28:02.27#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.197.08:28:02.27#ibcon#enter wrdev, iclass 11, count 0 2006.197.08:28:02.27#ibcon#first serial, iclass 11, count 0 2006.197.08:28:02.27#ibcon#enter sib2, iclass 11, count 0 2006.197.08:28:02.27#ibcon#flushed, iclass 11, count 0 2006.197.08:28:02.27#ibcon#about to write, iclass 11, count 0 2006.197.08:28:02.27#ibcon#wrote, iclass 11, count 0 2006.197.08:28:02.27#ibcon#about to read 3, iclass 11, count 0 2006.197.08:28:02.29#ibcon#read 3, iclass 11, count 0 2006.197.08:28:02.29#ibcon#about to read 4, iclass 11, count 0 2006.197.08:28:02.29#ibcon#read 4, iclass 11, count 0 2006.197.08:28:02.29#ibcon#about to read 5, iclass 11, count 0 2006.197.08:28:02.29#ibcon#read 5, iclass 11, count 0 2006.197.08:28:02.29#ibcon#about to read 6, iclass 11, count 0 2006.197.08:28:02.29#ibcon#read 6, iclass 11, count 0 2006.197.08:28:02.29#ibcon#end of sib2, iclass 11, count 0 2006.197.08:28:02.29#ibcon#*mode == 0, iclass 11, count 0 2006.197.08:28:02.29#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.197.08:28:02.29#ibcon#[27=BW32\r\n] 2006.197.08:28:02.29#ibcon#*before write, iclass 11, count 0 2006.197.08:28:02.29#ibcon#enter sib2, iclass 11, count 0 2006.197.08:28:02.29#ibcon#flushed, iclass 11, count 0 2006.197.08:28:02.29#ibcon#about to write, iclass 11, count 0 2006.197.08:28:02.29#ibcon#wrote, iclass 11, count 0 2006.197.08:28:02.29#ibcon#about to read 3, iclass 11, count 0 2006.197.08:28:02.32#ibcon#read 3, iclass 11, count 0 2006.197.08:28:02.32#ibcon#about to read 4, iclass 11, count 0 2006.197.08:28:02.32#ibcon#read 4, iclass 11, count 0 2006.197.08:28:02.32#ibcon#about to read 5, iclass 11, count 0 2006.197.08:28:02.32#ibcon#read 5, iclass 11, count 0 2006.197.08:28:02.32#ibcon#about to read 6, iclass 11, count 0 2006.197.08:28:02.32#ibcon#read 6, iclass 11, count 0 2006.197.08:28:02.32#ibcon#end of sib2, iclass 11, count 0 2006.197.08:28:02.32#ibcon#*after write, iclass 11, count 0 2006.197.08:28:02.32#ibcon#*before return 0, iclass 11, count 0 2006.197.08:28:02.32#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.197.08:28:02.32#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.197.08:28:02.32#ibcon#about to clear, iclass 11 cls_cnt 0 2006.197.08:28:02.32#ibcon#cleared, iclass 11 cls_cnt 0 2006.197.08:28:02.32$4f8m12a/ifd4f 2006.197.08:28:02.32$ifd4f/lo= 2006.197.08:28:02.32$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.197.08:28:02.32$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.197.08:28:02.32$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.197.08:28:02.32$ifd4f/patch= 2006.197.08:28:02.32$ifd4f/patch=lo1,a1,a2,a3,a4 2006.197.08:28:02.32$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.197.08:28:02.32$ifd4f/patch=lo3,a5,a6,a7,a8 2006.197.08:28:02.32$4f8m12a/"form=m,16.000,1:2 2006.197.08:28:02.32$4f8m12a/"tpicd 2006.197.08:28:02.32$4f8m12a/echo=off 2006.197.08:28:02.32$4f8m12a/xlog=off 2006.197.08:28:02.32:!2006.197.08:28:30 2006.197.08:28:15.14#trakl#Source acquired 2006.197.08:28:15.14#flagr#flagr/antenna,acquired 2006.197.08:28:30.00:preob 2006.197.08:28:31.13/onsource/TRACKING 2006.197.08:28:31.13:!2006.197.08:28:40 2006.197.08:28:40.00:data_valid=on 2006.197.08:28:40.00:midob 2006.197.08:28:40.13/onsource/TRACKING 2006.197.08:28:40.13/wx/25.50,1003.0,96 2006.197.08:28:40.18/cable/+6.3732E-03 2006.197.08:28:41.27/va/01,08,usb,yes,28,30 2006.197.08:28:41.27/va/02,07,usb,yes,29,30 2006.197.08:28:41.27/va/03,06,usb,yes,30,30 2006.197.08:28:41.27/va/04,07,usb,yes,29,32 2006.197.08:28:41.27/va/05,07,usb,yes,33,35 2006.197.08:28:41.27/va/06,06,usb,yes,32,32 2006.197.08:28:41.27/va/07,06,usb,yes,33,33 2006.197.08:28:41.27/va/08,07,usb,yes,31,30 2006.197.08:28:41.50/valo/01,532.99,yes,locked 2006.197.08:28:41.50/valo/02,572.99,yes,locked 2006.197.08:28:41.50/valo/03,672.99,yes,locked 2006.197.08:28:41.50/valo/04,832.99,yes,locked 2006.197.08:28:41.50/valo/05,652.99,yes,locked 2006.197.08:28:41.50/valo/06,772.99,yes,locked 2006.197.08:28:41.50/valo/07,832.99,yes,locked 2006.197.08:28:41.50/valo/08,852.99,yes,locked 2006.197.08:28:42.59/vb/01,04,usb,yes,28,27 2006.197.08:28:42.59/vb/02,04,usb,yes,30,31 2006.197.08:28:42.59/vb/03,04,usb,yes,27,30 2006.197.08:28:42.59/vb/04,04,usb,yes,27,28 2006.197.08:28:42.59/vb/05,04,usb,yes,26,30 2006.197.08:28:42.59/vb/06,04,usb,yes,27,29 2006.197.08:28:42.59/vb/07,04,usb,yes,29,29 2006.197.08:28:42.59/vb/08,04,usb,yes,27,30 2006.197.08:28:42.83/vblo/01,632.99,yes,locked 2006.197.08:28:42.83/vblo/02,640.99,yes,locked 2006.197.08:28:42.83/vblo/03,656.99,yes,locked 2006.197.08:28:42.83/vblo/04,712.99,yes,locked 2006.197.08:28:42.83/vblo/05,744.99,yes,locked 2006.197.08:28:42.83/vblo/06,752.99,yes,locked 2006.197.08:28:42.83/vblo/07,734.99,yes,locked 2006.197.08:28:42.83/vblo/08,744.99,yes,locked 2006.197.08:28:42.98/vabw/8 2006.197.08:28:43.13/vbbw/8 2006.197.08:28:43.22/xfe/off,on,15.2 2006.197.08:28:43.60/ifatt/23,28,28,28 2006.197.08:28:44.11/fmout-gps/S +2.98E-07 2006.197.08:28:44.15:!2006.197.08:29:40 2006.197.08:29:40.00:data_valid=off 2006.197.08:29:40.00:postob 2006.197.08:29:40.13/cable/+6.3724E-03 2006.197.08:29:40.13/wx/25.49,1003.0,96 2006.197.08:29:41.10/fmout-gps/S +2.99E-07 2006.197.08:29:41.10:checkk5last 2006.197.08:29:41.10&checkk5last/chk_obsdata=1 2006.197.08:29:41.10&checkk5last/chk_obsdata=2 2006.197.08:29:41.10&checkk5last/chk_obsdata=3 2006.197.08:29:41.10&checkk5last/chk_obsdata=4 2006.197.08:29:41.10&checkk5last/k5log=1 2006.197.08:29:41.10&checkk5last/k5log=2 2006.197.08:29:41.10&checkk5last/k5log=3 2006.197.08:29:41.10&checkk5last/k5log=4 2006.197.08:29:41.10&checkk5last/obsinfo 2006.197.08:29:41.43/chk_obsdata//k5ts1/T1970828??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.08:29:41.78/chk_obsdata//k5ts2/T1970828??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.08:29:42.15/chk_obsdata//k5ts3/T1970828??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.08:29:42.50/chk_obsdata//k5ts4/T1970828??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.197.08:29:43.15/k5log//k5ts1_log_newline 2006.197.08:29:43.81/k5log//k5ts2_log_newline 2006.197.08:29:44.46/k5log//k5ts3_log_newline 2006.197.08:29:45.12/k5log//k5ts4_log_newline 2006.197.08:29:45.15/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.197.08:29:45.15:sched_end 2006.197.08:29:45.15&sched_end/stopcheck 2006.197.08:29:45.15&stopcheck/sy=killall check_fsrun.pl 2006.197.08:29:45.15&stopcheck/" sy=killall chmem.sh 2006.197.08:29:45.20:source=idle 2006.197.08:29:46.13#flagr#flagr/antenna,new-source 2006.197.08:29:46.13:stow 2006.197.08:29:46.13&stow/source=idle 2006.197.08:29:46.14&stow/"this is stow command. 2006.197.08:29:46.14&stow/antenna=m3 2006.197.08:29:50.01:!+10m 2006.197.08:39:50.02:standby 2006.197.08:39:50.02&standby/"this is standby command. 2006.197.08:39:50.02&standby/antenna=m0 2006.197.08:39:51.01:sy=cp /usr2/log/k06197ts.log /usr2/log_backup/ 2006.197.08:39:51.06:*end of schedule