2006.195.08:12:47.28;Log Opened: Mark IV Field System Version 9.7.7 2006.195.08:12:47.28;location,TSUKUB32,-140.09,36.10,61.0 2006.195.08:12:47.28;horizon1,0.,5.,360. 2006.195.08:12:47.28;antenna,32.0,180.0,180.0,10.0,710.0,5.0,88.0,azel 2006.195.08:12:47.28;equip,k42c/mk4,vlbab,vlbab,mk4,500.10,3,a/d,101,60,20,none,41,1,in,8bit,cdp,3 2006.195.08:12:47.28;drivev11,330,270,no 2006.195.08:12:47.28;drivev12,mvme117,0,11.400,2548.000,152.780,-6.655,0.014,152,10.000,54500 2006.195.08:12:47.28;drivev13,15.000,268,10.000,10.000,10.000 2006.195.08:12:47.28;drivev21,330,270,no 2006.195.08:12:47.28;drivev22,mvme117,0,11.500,2821.000,127.500,-8.640,0.015,152,14.000,54500 2006.195.08:12:47.28;drivev23,15.000,268,10.000,10.000,10.000 2006.195.08:12:47.28;head10,all,all,all,odd,adaptive,no,5.0000,1 2006.195.08:12:47.28;head11,131.5,16.4,-291.0,131.5,16.4,0.8,168.30,168.30 2006.195.08:12:47.28;head12,122.8,13.9,-150.8,122.8,14.7,2.5,167.61,167.61 2006.195.08:12:47.28;head20,all,all,all,odd,adaptive,no,5.0000,1 2006.195.08:12:47.28;head21,145.3,16.1,-209.3,137.2,16.1,58.9,165.28,165.28 2006.195.08:12:47.28;head22,157.5,17.4,-203.7,149.2,16.6,56.5,169.73,169.73 2006.195.08:12:47.28;time,-0.364,101.533,rate 2006.195.08:12:47.28;flagr,200 2006.195.08:12:47.28:" K06196 2006 TSUKUB32 T Ts 2006.195.08:12:47.28:" T TSUKUB32 AZEL .0000 180.0 14 10.0 710.0 180.0 14 5.0 88.0 32.0 Ts 108 2006.195.08:12:47.28:" Ts TSUKUB32 -3957408.75120 3310229.34660 3737494.83600 73452301 2006.195.08:12:47.28:" 108 TSUKUB32 14 17400 2006.195.08:12:47.28:" drudg version 050216 compiled under FS 9.7.07 2006.195.08:12:47.28:" Rack=K4-2/M4 Recorder 1=K5 Recorder 2=none 2006.195.08:12:47.28:exper_initi 2006.195.08:12:47.28&exper_initi/proc_library 2006.195.08:12:47.28&exper_initi/sched_initi 2006.195.08:12:47.28:!2006.196.06:29:50 2006.195.08:12:47.28&proc_library/" k06196 tsukub32 ts 2006.195.08:12:47.28&proc_library/" drudg version 050216 compiled under fs 9.7.7 2006.195.08:12:47.28&proc_library/"< k4-2/m4 rack >< k5 recorder 1> 2006.195.08:12:47.28&sched_initi/startcheck 2006.195.08:12:47.28&startcheck/sy=check_fsrun.pl & 2006.195.08:12:47.28&startcheck/" sy=/usr2/oper/temp/chmem.sh >& /dev/null & 2006.195.08:12:59.30;cable 2006.195.08:12:59.40/cable/+6.3561E-03 2006.195.08:13:51.50;cablelng 2006.195.08:13:51.50?ERROR sp -4 Unrecognized name (not a function or procedure). 2006.195.08:13:54.28;cablelong 2006.195.08:13:54.35/cablelong/+6.9206E-03 2006.195.08:13:58.87;cablediff 2006.195.08:13:58.87/cablediff/564.5e-6,+ 2006.195.08:15:22.73;cable 2006.195.08:15:22.95/cable/+6.3559E-03 2006.195.08:15:30.01;standby 2006.195.08:15:30.01&standby/"this is standby command. 2006.195.08:15:30.01&standby/antenna=m0 2006.195.08:15:34.33;wx 2006.195.08:15:34.33/wx/25.55,1007.5,100 2006.195.08:15:43.04;"Sky is rainy. 2006.195.08:15:45.65;xfe 2006.195.08:15:45.74/xfe/off,on,15.2 2006.195.08:15:49.55;clockoff 2006.195.08:15:49.55&clockoff/"gps-fmout=1p 2006.195.08:15:49.55&clockoff/fmout-gps=1p 2006.195.08:15:50.03/fmout-gps/S +3.58E-07 2006.196.06:29:50.00:sy=/usr2/oper/k5/bin/freeze_chk.pl & 2006.196.06:29:50.02:!2006.196.07:19:50 2006.196.07:19:50.00:unstow 2006.196.07:19:50.00&unstow/antenna=e 2006.196.07:19:50.00&unstow/!+10s 2006.196.07:19:50.00&unstow/antenna=m2 2006.196.07:20:02.01:scan_name=196-0730,k06196,60 2006.196.07:20:02.01:source=3c418,203837.03,511912.7,2000.0,ccw 2006.196.07:20:03.14#antcn#PM 1 00019 2005 228 00 22 31 00 2006.196.07:20:03.14#antcn#PM 2 90.0000 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 2006.196.07:20:03.14#antcn#PM 2 -0.0279715 0.0000000 -0.0282214 -0.0241630 -0.0014011 2006.196.07:20:03.14#antcn#PM 3 -0.0059899 0.0042895 -0.0643783 0.0000000 0.0000000 2006.196.07:20:03.14#antcn#PM 4 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.196.07:20:03.14#antcn#PM 5 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.196.07:20:04.14:ready_k5 2006.196.07:20:04.14&ready_k5/obsinfo=st 2006.196.07:20:04.14&ready_k5/autoobs=1 2006.196.07:20:04.14&ready_k5/autoobs=2 2006.196.07:20:04.14&ready_k5/autoobs=3 2006.196.07:20:04.14&ready_k5/autoobs=4 2006.196.07:20:04.14&ready_k5/obsinfo 2006.196.07:20:04.14#flagr#flagr/antenna,new-source 2006.196.07:20:04.14/obsinfo=st/error_log.tmp was not found (or not removed). 2006.196.07:20:07.37/autoobs//k5ts1/ autoobs started! 2006.196.07:20:10.50/autoobs//k5ts2/ autoobs started! 2006.196.07:20:13.62/autoobs//k5ts3/ autoobs started! 2006.196.07:20:16.75/autoobs//k5ts4/ autoobs started! 2006.196.07:20:16.77/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.196.07:20:16.77:4f8m12a=1 2006.196.07:20:16.77&4f8m12a/xlog=on 2006.196.07:20:16.77&4f8m12a/echo=on 2006.196.07:20:16.77&4f8m12a/pcalon 2006.196.07:20:16.77&4f8m12a/"tpicd=stop 2006.196.07:20:16.77&4f8m12a/vc4f8 2006.196.07:20:16.77&4f8m12a/ifd4f 2006.196.07:20:16.77&4f8m12a/"form=m,16.000,1:2 2006.196.07:20:16.77&4f8m12a/"tpicd 2006.196.07:20:16.77&4f8m12a/echo=off 2006.196.07:20:16.77&4f8m12a/xlog=off 2006.196.07:20:16.77$4f8m12a/echo=on 2006.196.07:20:16.77$4f8m12a/pcalon 2006.196.07:20:16.77&pcalon/"no phase cal control is implemented here 2006.196.07:20:16.77$pcalon/"no phase cal control is implemented here 2006.196.07:20:16.77$4f8m12a/"tpicd=stop 2006.196.07:20:16.77$4f8m12a/vc4f8 2006.196.07:20:16.77&vc4f8/valo=1,532.99 2006.196.07:20:16.77&vc4f8/va=1,8 2006.196.07:20:16.77&vc4f8/valo=2,572.99 2006.196.07:20:16.77&vc4f8/va=2,7 2006.196.07:20:16.77&vc4f8/valo=3,672.99 2006.196.07:20:16.77&vc4f8/va=3,6 2006.196.07:20:16.77&vc4f8/valo=4,832.99 2006.196.07:20:16.77&vc4f8/va=4,7 2006.196.07:20:16.77&vc4f8/valo=5,652.99 2006.196.07:20:16.77&vc4f8/va=5,7 2006.196.07:20:16.77&vc4f8/valo=6,772.99 2006.196.07:20:16.77&vc4f8/va=6,6 2006.196.07:20:16.77&vc4f8/valo=7,832.99 2006.196.07:20:16.77&vc4f8/va=7,6 2006.196.07:20:16.77&vc4f8/valo=8,852.99 2006.196.07:20:16.77&vc4f8/va=8,7 2006.196.07:20:16.77&vc4f8/vblo=1,632.99 2006.196.07:20:16.77&vc4f8/vb=1,4 2006.196.07:20:16.77&vc4f8/vblo=2,640.99 2006.196.07:20:16.77&vc4f8/vb=2,4 2006.196.07:20:16.77&vc4f8/vblo=3,656.99 2006.196.07:20:16.77&vc4f8/vb=3,4 2006.196.07:20:16.77&vc4f8/vblo=4,712.99 2006.196.07:20:16.77&vc4f8/vb=4,4 2006.196.07:20:16.77&vc4f8/vblo=5,744.99 2006.196.07:20:16.78&vc4f8/vb=5,4 2006.196.07:20:16.78&vc4f8/vblo=6,752.99 2006.196.07:20:16.78&vc4f8/vb=6,4 2006.196.07:20:16.78&vc4f8/vabw=wide 2006.196.07:20:16.78&vc4f8/vbbw=wide 2006.196.07:20:16.78$vc4f8/valo=1,532.99 2006.196.07:20:16.82#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.196.07:20:16.82#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.196.07:20:16.82#ibcon#ireg 17 cls_cnt 0 2006.196.07:20:16.82#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.196.07:20:16.82#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.196.07:20:16.82#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.196.07:20:16.82#ibcon#enter wrdev, iclass 34, count 0 2006.196.07:20:16.82#ibcon#first serial, iclass 34, count 0 2006.196.07:20:16.82#ibcon#enter sib2, iclass 34, count 0 2006.196.07:20:16.82#ibcon#flushed, iclass 34, count 0 2006.196.07:20:16.82#ibcon#about to write, iclass 34, count 0 2006.196.07:20:16.82#ibcon#wrote, iclass 34, count 0 2006.196.07:20:16.82#ibcon#about to read 3, iclass 34, count 0 2006.196.07:20:16.84#ibcon#read 3, iclass 34, count 0 2006.196.07:20:16.84#ibcon#about to read 4, iclass 34, count 0 2006.196.07:20:16.84#ibcon#read 4, iclass 34, count 0 2006.196.07:20:16.84#ibcon#about to read 5, iclass 34, count 0 2006.196.07:20:16.84#ibcon#read 5, iclass 34, count 0 2006.196.07:20:16.84#ibcon#about to read 6, iclass 34, count 0 2006.196.07:20:16.84#ibcon#read 6, iclass 34, count 0 2006.196.07:20:16.84#ibcon#end of sib2, iclass 34, count 0 2006.196.07:20:16.84#ibcon#*mode == 0, iclass 34, count 0 2006.196.07:20:16.84#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.196.07:20:16.84#ibcon#[26=FRQ=01,532.99\r\n] 2006.196.07:20:16.84#ibcon#*before write, iclass 34, count 0 2006.196.07:20:16.84#ibcon#enter sib2, iclass 34, count 0 2006.196.07:20:16.84#ibcon#flushed, iclass 34, count 0 2006.196.07:20:16.84#ibcon#about to write, iclass 34, count 0 2006.196.07:20:16.84#ibcon#wrote, iclass 34, count 0 2006.196.07:20:16.84#ibcon#about to read 3, iclass 34, count 0 2006.196.07:20:16.90#ibcon#read 3, iclass 34, count 0 2006.196.07:20:16.90#ibcon#about to read 4, iclass 34, count 0 2006.196.07:20:16.90#ibcon#read 4, iclass 34, count 0 2006.196.07:20:16.90#ibcon#about to read 5, iclass 34, count 0 2006.196.07:20:16.90#ibcon#read 5, iclass 34, count 0 2006.196.07:20:16.90#ibcon#about to read 6, iclass 34, count 0 2006.196.07:20:16.90#ibcon#read 6, iclass 34, count 0 2006.196.07:20:16.90#ibcon#end of sib2, iclass 34, count 0 2006.196.07:20:16.90#ibcon#*after write, iclass 34, count 0 2006.196.07:20:16.90#ibcon#*before return 0, iclass 34, count 0 2006.196.07:20:16.90#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.196.07:20:16.90#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.196.07:20:16.90#ibcon#about to clear, iclass 34 cls_cnt 0 2006.196.07:20:16.90#ibcon#cleared, iclass 34 cls_cnt 0 2006.196.07:20:16.90$vc4f8/va=1,8 2006.196.07:20:16.90#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.196.07:20:16.90#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.196.07:20:16.90#ibcon#ireg 11 cls_cnt 2 2006.196.07:20:16.90#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.196.07:20:16.90#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.196.07:20:16.90#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.196.07:20:16.90#ibcon#enter wrdev, iclass 36, count 2 2006.196.07:20:16.90#ibcon#first serial, iclass 36, count 2 2006.196.07:20:16.90#ibcon#enter sib2, iclass 36, count 2 2006.196.07:20:16.90#ibcon#flushed, iclass 36, count 2 2006.196.07:20:16.90#ibcon#about to write, iclass 36, count 2 2006.196.07:20:16.90#ibcon#wrote, iclass 36, count 2 2006.196.07:20:16.90#ibcon#about to read 3, iclass 36, count 2 2006.196.07:20:16.92#ibcon#read 3, iclass 36, count 2 2006.196.07:20:16.92#ibcon#about to read 4, iclass 36, count 2 2006.196.07:20:16.92#ibcon#read 4, iclass 36, count 2 2006.196.07:20:16.92#ibcon#about to read 5, iclass 36, count 2 2006.196.07:20:16.92#ibcon#read 5, iclass 36, count 2 2006.196.07:20:16.92#ibcon#about to read 6, iclass 36, count 2 2006.196.07:20:16.92#ibcon#read 6, iclass 36, count 2 2006.196.07:20:16.92#ibcon#end of sib2, iclass 36, count 2 2006.196.07:20:16.92#ibcon#*mode == 0, iclass 36, count 2 2006.196.07:20:16.92#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.196.07:20:16.92#ibcon#[25=AT01-08\r\n] 2006.196.07:20:16.92#ibcon#*before write, iclass 36, count 2 2006.196.07:20:16.92#ibcon#enter sib2, iclass 36, count 2 2006.196.07:20:16.92#ibcon#flushed, iclass 36, count 2 2006.196.07:20:16.92#ibcon#about to write, iclass 36, count 2 2006.196.07:20:16.92#ibcon#wrote, iclass 36, count 2 2006.196.07:20:16.92#ibcon#about to read 3, iclass 36, count 2 2006.196.07:20:16.95#ibcon#read 3, iclass 36, count 2 2006.196.07:20:16.95#ibcon#about to read 4, iclass 36, count 2 2006.196.07:20:16.95#ibcon#read 4, iclass 36, count 2 2006.196.07:20:16.95#ibcon#about to read 5, iclass 36, count 2 2006.196.07:20:16.95#ibcon#read 5, iclass 36, count 2 2006.196.07:20:16.95#ibcon#about to read 6, iclass 36, count 2 2006.196.07:20:16.95#ibcon#read 6, iclass 36, count 2 2006.196.07:20:16.95#ibcon#end of sib2, iclass 36, count 2 2006.196.07:20:16.95#ibcon#*after write, iclass 36, count 2 2006.196.07:20:16.95#ibcon#*before return 0, iclass 36, count 2 2006.196.07:20:16.95#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.196.07:20:16.95#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.196.07:20:16.95#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.196.07:20:16.95#ibcon#ireg 7 cls_cnt 0 2006.196.07:20:16.95#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.196.07:20:17.07#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.196.07:20:17.07#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.196.07:20:17.07#ibcon#enter wrdev, iclass 36, count 0 2006.196.07:20:17.07#ibcon#first serial, iclass 36, count 0 2006.196.07:20:17.07#ibcon#enter sib2, iclass 36, count 0 2006.196.07:20:17.07#ibcon#flushed, iclass 36, count 0 2006.196.07:20:17.07#ibcon#about to write, iclass 36, count 0 2006.196.07:20:17.07#ibcon#wrote, iclass 36, count 0 2006.196.07:20:17.07#ibcon#about to read 3, iclass 36, count 0 2006.196.07:20:17.10#ibcon#read 3, iclass 36, count 0 2006.196.07:20:17.10#ibcon#about to read 4, iclass 36, count 0 2006.196.07:20:17.10#ibcon#read 4, iclass 36, count 0 2006.196.07:20:17.10#ibcon#about to read 5, iclass 36, count 0 2006.196.07:20:17.10#ibcon#read 5, iclass 36, count 0 2006.196.07:20:17.10#ibcon#about to read 6, iclass 36, count 0 2006.196.07:20:17.10#ibcon#read 6, iclass 36, count 0 2006.196.07:20:17.10#ibcon#end of sib2, iclass 36, count 0 2006.196.07:20:17.10#ibcon#*mode == 0, iclass 36, count 0 2006.196.07:20:17.10#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.196.07:20:17.10#ibcon#[25=USB\r\n] 2006.196.07:20:17.10#ibcon#*before write, iclass 36, count 0 2006.196.07:20:17.10#ibcon#enter sib2, iclass 36, count 0 2006.196.07:20:17.10#ibcon#flushed, iclass 36, count 0 2006.196.07:20:17.10#ibcon#about to write, iclass 36, count 0 2006.196.07:20:17.10#ibcon#wrote, iclass 36, count 0 2006.196.07:20:17.10#ibcon#about to read 3, iclass 36, count 0 2006.196.07:20:17.13#ibcon#read 3, iclass 36, count 0 2006.196.07:20:17.13#ibcon#about to read 4, iclass 36, count 0 2006.196.07:20:17.13#ibcon#read 4, iclass 36, count 0 2006.196.07:20:17.13#ibcon#about to read 5, iclass 36, count 0 2006.196.07:20:17.13#ibcon#read 5, iclass 36, count 0 2006.196.07:20:17.13#ibcon#about to read 6, iclass 36, count 0 2006.196.07:20:17.13#ibcon#read 6, iclass 36, count 0 2006.196.07:20:17.13#ibcon#end of sib2, iclass 36, count 0 2006.196.07:20:17.13#ibcon#*after write, iclass 36, count 0 2006.196.07:20:17.13#ibcon#*before return 0, iclass 36, count 0 2006.196.07:20:17.13#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.196.07:20:17.13#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.196.07:20:17.13#ibcon#about to clear, iclass 36 cls_cnt 0 2006.196.07:20:17.13#ibcon#cleared, iclass 36 cls_cnt 0 2006.196.07:20:17.13$vc4f8/valo=2,572.99 2006.196.07:20:17.13#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.196.07:20:17.13#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.196.07:20:17.13#ibcon#ireg 17 cls_cnt 0 2006.196.07:20:17.13#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.196.07:20:17.13#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.196.07:20:17.13#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.196.07:20:17.13#ibcon#enter wrdev, iclass 38, count 0 2006.196.07:20:17.13#ibcon#first serial, iclass 38, count 0 2006.196.07:20:17.13#ibcon#enter sib2, iclass 38, count 0 2006.196.07:20:17.13#ibcon#flushed, iclass 38, count 0 2006.196.07:20:17.13#ibcon#about to write, iclass 38, count 0 2006.196.07:20:17.13#ibcon#wrote, iclass 38, count 0 2006.196.07:20:17.13#ibcon#about to read 3, iclass 38, count 0 2006.196.07:20:17.15#ibcon#read 3, iclass 38, count 0 2006.196.07:20:17.15#ibcon#about to read 4, iclass 38, count 0 2006.196.07:20:17.15#ibcon#read 4, iclass 38, count 0 2006.196.07:20:17.15#ibcon#about to read 5, iclass 38, count 0 2006.196.07:20:17.15#ibcon#read 5, iclass 38, count 0 2006.196.07:20:17.15#ibcon#about to read 6, iclass 38, count 0 2006.196.07:20:17.15#ibcon#read 6, iclass 38, count 0 2006.196.07:20:17.15#ibcon#end of sib2, iclass 38, count 0 2006.196.07:20:17.15#ibcon#*mode == 0, iclass 38, count 0 2006.196.07:20:17.15#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.196.07:20:17.15#ibcon#[26=FRQ=02,572.99\r\n] 2006.196.07:20:17.15#ibcon#*before write, iclass 38, count 0 2006.196.07:20:17.15#ibcon#enter sib2, iclass 38, count 0 2006.196.07:20:17.15#ibcon#flushed, iclass 38, count 0 2006.196.07:20:17.15#ibcon#about to write, iclass 38, count 0 2006.196.07:20:17.15#ibcon#wrote, iclass 38, count 0 2006.196.07:20:17.15#ibcon#about to read 3, iclass 38, count 0 2006.196.07:20:17.19#ibcon#read 3, iclass 38, count 0 2006.196.07:20:17.19#ibcon#about to read 4, iclass 38, count 0 2006.196.07:20:17.19#ibcon#read 4, iclass 38, count 0 2006.196.07:20:17.19#ibcon#about to read 5, iclass 38, count 0 2006.196.07:20:17.19#ibcon#read 5, iclass 38, count 0 2006.196.07:20:17.19#ibcon#about to read 6, iclass 38, count 0 2006.196.07:20:17.19#ibcon#read 6, iclass 38, count 0 2006.196.07:20:17.19#ibcon#end of sib2, iclass 38, count 0 2006.196.07:20:17.19#ibcon#*after write, iclass 38, count 0 2006.196.07:20:17.19#ibcon#*before return 0, iclass 38, count 0 2006.196.07:20:17.19#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.196.07:20:17.19#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.196.07:20:17.19#ibcon#about to clear, iclass 38 cls_cnt 0 2006.196.07:20:17.19#ibcon#cleared, iclass 38 cls_cnt 0 2006.196.07:20:17.19$vc4f8/va=2,7 2006.196.07:20:17.19#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.196.07:20:17.19#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.196.07:20:17.19#ibcon#ireg 11 cls_cnt 2 2006.196.07:20:17.19#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.196.07:20:17.25#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.196.07:20:17.25#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.196.07:20:17.25#ibcon#enter wrdev, iclass 40, count 2 2006.196.07:20:17.25#ibcon#first serial, iclass 40, count 2 2006.196.07:20:17.25#ibcon#enter sib2, iclass 40, count 2 2006.196.07:20:17.25#ibcon#flushed, iclass 40, count 2 2006.196.07:20:17.25#ibcon#about to write, iclass 40, count 2 2006.196.07:20:17.25#ibcon#wrote, iclass 40, count 2 2006.196.07:20:17.25#ibcon#about to read 3, iclass 40, count 2 2006.196.07:20:17.27#ibcon#read 3, iclass 40, count 2 2006.196.07:20:17.27#ibcon#about to read 4, iclass 40, count 2 2006.196.07:20:17.27#ibcon#read 4, iclass 40, count 2 2006.196.07:20:17.27#ibcon#about to read 5, iclass 40, count 2 2006.196.07:20:17.27#ibcon#read 5, iclass 40, count 2 2006.196.07:20:17.27#ibcon#about to read 6, iclass 40, count 2 2006.196.07:20:17.27#ibcon#read 6, iclass 40, count 2 2006.196.07:20:17.27#ibcon#end of sib2, iclass 40, count 2 2006.196.07:20:17.27#ibcon#*mode == 0, iclass 40, count 2 2006.196.07:20:17.27#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.196.07:20:17.27#ibcon#[25=AT02-07\r\n] 2006.196.07:20:17.27#ibcon#*before write, iclass 40, count 2 2006.196.07:20:17.27#ibcon#enter sib2, iclass 40, count 2 2006.196.07:20:17.27#ibcon#flushed, iclass 40, count 2 2006.196.07:20:17.27#ibcon#about to write, iclass 40, count 2 2006.196.07:20:17.27#ibcon#wrote, iclass 40, count 2 2006.196.07:20:17.27#ibcon#about to read 3, iclass 40, count 2 2006.196.07:20:17.31#ibcon#read 3, iclass 40, count 2 2006.196.07:20:17.31#ibcon#about to read 4, iclass 40, count 2 2006.196.07:20:17.31#ibcon#read 4, iclass 40, count 2 2006.196.07:20:17.31#ibcon#about to read 5, iclass 40, count 2 2006.196.07:20:17.31#ibcon#read 5, iclass 40, count 2 2006.196.07:20:17.31#ibcon#about to read 6, iclass 40, count 2 2006.196.07:20:17.31#ibcon#read 6, iclass 40, count 2 2006.196.07:20:17.31#ibcon#end of sib2, iclass 40, count 2 2006.196.07:20:17.31#ibcon#*after write, iclass 40, count 2 2006.196.07:20:17.31#ibcon#*before return 0, iclass 40, count 2 2006.196.07:20:17.31#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.196.07:20:17.31#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.196.07:20:17.31#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.196.07:20:17.31#ibcon#ireg 7 cls_cnt 0 2006.196.07:20:17.31#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.196.07:20:17.43#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.196.07:20:17.43#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.196.07:20:17.43#ibcon#enter wrdev, iclass 40, count 0 2006.196.07:20:17.43#ibcon#first serial, iclass 40, count 0 2006.196.07:20:17.43#ibcon#enter sib2, iclass 40, count 0 2006.196.07:20:17.43#ibcon#flushed, iclass 40, count 0 2006.196.07:20:17.43#ibcon#about to write, iclass 40, count 0 2006.196.07:20:17.43#ibcon#wrote, iclass 40, count 0 2006.196.07:20:17.43#ibcon#about to read 3, iclass 40, count 0 2006.196.07:20:17.45#ibcon#read 3, iclass 40, count 0 2006.196.07:20:17.45#ibcon#about to read 4, iclass 40, count 0 2006.196.07:20:17.45#ibcon#read 4, iclass 40, count 0 2006.196.07:20:17.45#ibcon#about to read 5, iclass 40, count 0 2006.196.07:20:17.45#ibcon#read 5, iclass 40, count 0 2006.196.07:20:17.45#ibcon#about to read 6, iclass 40, count 0 2006.196.07:20:17.45#ibcon#read 6, iclass 40, count 0 2006.196.07:20:17.45#ibcon#end of sib2, iclass 40, count 0 2006.196.07:20:17.45#ibcon#*mode == 0, iclass 40, count 0 2006.196.07:20:17.45#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.196.07:20:17.45#ibcon#[25=USB\r\n] 2006.196.07:20:17.45#ibcon#*before write, iclass 40, count 0 2006.196.07:20:17.45#ibcon#enter sib2, iclass 40, count 0 2006.196.07:20:17.45#ibcon#flushed, iclass 40, count 0 2006.196.07:20:17.45#ibcon#about to write, iclass 40, count 0 2006.196.07:20:17.45#ibcon#wrote, iclass 40, count 0 2006.196.07:20:17.45#ibcon#about to read 3, iclass 40, count 0 2006.196.07:20:17.48#ibcon#read 3, iclass 40, count 0 2006.196.07:20:17.48#ibcon#about to read 4, iclass 40, count 0 2006.196.07:20:17.48#ibcon#read 4, iclass 40, count 0 2006.196.07:20:17.48#ibcon#about to read 5, iclass 40, count 0 2006.196.07:20:17.48#ibcon#read 5, iclass 40, count 0 2006.196.07:20:17.48#ibcon#about to read 6, iclass 40, count 0 2006.196.07:20:17.48#ibcon#read 6, iclass 40, count 0 2006.196.07:20:17.48#ibcon#end of sib2, iclass 40, count 0 2006.196.07:20:17.48#ibcon#*after write, iclass 40, count 0 2006.196.07:20:17.48#ibcon#*before return 0, iclass 40, count 0 2006.196.07:20:17.48#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.196.07:20:17.48#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.196.07:20:17.48#ibcon#about to clear, iclass 40 cls_cnt 0 2006.196.07:20:17.48#ibcon#cleared, iclass 40 cls_cnt 0 2006.196.07:20:17.48$vc4f8/valo=3,672.99 2006.196.07:20:17.48#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.196.07:20:17.48#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.196.07:20:17.48#ibcon#ireg 17 cls_cnt 0 2006.196.07:20:17.48#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.196.07:20:17.48#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.196.07:20:17.48#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.196.07:20:17.48#ibcon#enter wrdev, iclass 4, count 0 2006.196.07:20:17.48#ibcon#first serial, iclass 4, count 0 2006.196.07:20:17.48#ibcon#enter sib2, iclass 4, count 0 2006.196.07:20:17.48#ibcon#flushed, iclass 4, count 0 2006.196.07:20:17.48#ibcon#about to write, iclass 4, count 0 2006.196.07:20:17.48#ibcon#wrote, iclass 4, count 0 2006.196.07:20:17.48#ibcon#about to read 3, iclass 4, count 0 2006.196.07:20:17.50#ibcon#read 3, iclass 4, count 0 2006.196.07:20:17.50#ibcon#about to read 4, iclass 4, count 0 2006.196.07:20:17.50#ibcon#read 4, iclass 4, count 0 2006.196.07:20:17.50#ibcon#about to read 5, iclass 4, count 0 2006.196.07:20:17.50#ibcon#read 5, iclass 4, count 0 2006.196.07:20:17.50#ibcon#about to read 6, iclass 4, count 0 2006.196.07:20:17.50#ibcon#read 6, iclass 4, count 0 2006.196.07:20:17.50#ibcon#end of sib2, iclass 4, count 0 2006.196.07:20:17.50#ibcon#*mode == 0, iclass 4, count 0 2006.196.07:20:17.50#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.196.07:20:17.50#ibcon#[26=FRQ=03,672.99\r\n] 2006.196.07:20:17.50#ibcon#*before write, iclass 4, count 0 2006.196.07:20:17.50#ibcon#enter sib2, iclass 4, count 0 2006.196.07:20:17.50#ibcon#flushed, iclass 4, count 0 2006.196.07:20:17.50#ibcon#about to write, iclass 4, count 0 2006.196.07:20:17.50#ibcon#wrote, iclass 4, count 0 2006.196.07:20:17.50#ibcon#about to read 3, iclass 4, count 0 2006.196.07:20:17.54#ibcon#read 3, iclass 4, count 0 2006.196.07:20:17.54#ibcon#about to read 4, iclass 4, count 0 2006.196.07:20:17.54#ibcon#read 4, iclass 4, count 0 2006.196.07:20:17.54#ibcon#about to read 5, iclass 4, count 0 2006.196.07:20:17.54#ibcon#read 5, iclass 4, count 0 2006.196.07:20:17.54#ibcon#about to read 6, iclass 4, count 0 2006.196.07:20:17.54#ibcon#read 6, iclass 4, count 0 2006.196.07:20:17.54#ibcon#end of sib2, iclass 4, count 0 2006.196.07:20:17.54#ibcon#*after write, iclass 4, count 0 2006.196.07:20:17.54#ibcon#*before return 0, iclass 4, count 0 2006.196.07:20:17.54#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.196.07:20:17.54#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.196.07:20:17.54#ibcon#about to clear, iclass 4 cls_cnt 0 2006.196.07:20:17.54#ibcon#cleared, iclass 4 cls_cnt 0 2006.196.07:20:17.54$vc4f8/va=3,6 2006.196.07:20:17.54#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.196.07:20:17.54#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.196.07:20:17.54#ibcon#ireg 11 cls_cnt 2 2006.196.07:20:17.54#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.196.07:20:17.60#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.196.07:20:17.60#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.196.07:20:17.60#ibcon#enter wrdev, iclass 6, count 2 2006.196.07:20:17.60#ibcon#first serial, iclass 6, count 2 2006.196.07:20:17.60#ibcon#enter sib2, iclass 6, count 2 2006.196.07:20:17.60#ibcon#flushed, iclass 6, count 2 2006.196.07:20:17.60#ibcon#about to write, iclass 6, count 2 2006.196.07:20:17.60#ibcon#wrote, iclass 6, count 2 2006.196.07:20:17.60#ibcon#about to read 3, iclass 6, count 2 2006.196.07:20:17.62#ibcon#read 3, iclass 6, count 2 2006.196.07:20:17.62#ibcon#about to read 4, iclass 6, count 2 2006.196.07:20:17.62#ibcon#read 4, iclass 6, count 2 2006.196.07:20:17.62#ibcon#about to read 5, iclass 6, count 2 2006.196.07:20:17.62#ibcon#read 5, iclass 6, count 2 2006.196.07:20:17.62#ibcon#about to read 6, iclass 6, count 2 2006.196.07:20:17.62#ibcon#read 6, iclass 6, count 2 2006.196.07:20:17.62#ibcon#end of sib2, iclass 6, count 2 2006.196.07:20:17.62#ibcon#*mode == 0, iclass 6, count 2 2006.196.07:20:17.62#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.196.07:20:17.62#ibcon#[25=AT03-06\r\n] 2006.196.07:20:17.62#ibcon#*before write, iclass 6, count 2 2006.196.07:20:17.62#ibcon#enter sib2, iclass 6, count 2 2006.196.07:20:17.62#ibcon#flushed, iclass 6, count 2 2006.196.07:20:17.62#ibcon#about to write, iclass 6, count 2 2006.196.07:20:17.62#ibcon#wrote, iclass 6, count 2 2006.196.07:20:17.62#ibcon#about to read 3, iclass 6, count 2 2006.196.07:20:17.65#ibcon#read 3, iclass 6, count 2 2006.196.07:20:17.65#ibcon#about to read 4, iclass 6, count 2 2006.196.07:20:17.65#ibcon#read 4, iclass 6, count 2 2006.196.07:20:17.65#ibcon#about to read 5, iclass 6, count 2 2006.196.07:20:17.65#ibcon#read 5, iclass 6, count 2 2006.196.07:20:17.65#ibcon#about to read 6, iclass 6, count 2 2006.196.07:20:17.65#ibcon#read 6, iclass 6, count 2 2006.196.07:20:17.65#ibcon#end of sib2, iclass 6, count 2 2006.196.07:20:17.65#ibcon#*after write, iclass 6, count 2 2006.196.07:20:17.65#ibcon#*before return 0, iclass 6, count 2 2006.196.07:20:17.65#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.196.07:20:17.65#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.196.07:20:17.65#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.196.07:20:17.65#ibcon#ireg 7 cls_cnt 0 2006.196.07:20:17.65#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.196.07:20:17.77#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.196.07:20:17.77#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.196.07:20:17.77#ibcon#enter wrdev, iclass 6, count 0 2006.196.07:20:17.77#ibcon#first serial, iclass 6, count 0 2006.196.07:20:17.77#ibcon#enter sib2, iclass 6, count 0 2006.196.07:20:17.77#ibcon#flushed, iclass 6, count 0 2006.196.07:20:17.77#ibcon#about to write, iclass 6, count 0 2006.196.07:20:17.77#ibcon#wrote, iclass 6, count 0 2006.196.07:20:17.77#ibcon#about to read 3, iclass 6, count 0 2006.196.07:20:17.79#ibcon#read 3, iclass 6, count 0 2006.196.07:20:17.79#ibcon#about to read 4, iclass 6, count 0 2006.196.07:20:17.79#ibcon#read 4, iclass 6, count 0 2006.196.07:20:17.79#ibcon#about to read 5, iclass 6, count 0 2006.196.07:20:17.79#ibcon#read 5, iclass 6, count 0 2006.196.07:20:17.79#ibcon#about to read 6, iclass 6, count 0 2006.196.07:20:17.79#ibcon#read 6, iclass 6, count 0 2006.196.07:20:17.79#ibcon#end of sib2, iclass 6, count 0 2006.196.07:20:17.79#ibcon#*mode == 0, iclass 6, count 0 2006.196.07:20:17.79#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.196.07:20:17.79#ibcon#[25=USB\r\n] 2006.196.07:20:17.79#ibcon#*before write, iclass 6, count 0 2006.196.07:20:17.79#ibcon#enter sib2, iclass 6, count 0 2006.196.07:20:17.79#ibcon#flushed, iclass 6, count 0 2006.196.07:20:17.79#ibcon#about to write, iclass 6, count 0 2006.196.07:20:17.79#ibcon#wrote, iclass 6, count 0 2006.196.07:20:17.79#ibcon#about to read 3, iclass 6, count 0 2006.196.07:20:17.82#ibcon#read 3, iclass 6, count 0 2006.196.07:20:17.82#ibcon#about to read 4, iclass 6, count 0 2006.196.07:20:17.82#ibcon#read 4, iclass 6, count 0 2006.196.07:20:17.82#ibcon#about to read 5, iclass 6, count 0 2006.196.07:20:17.82#ibcon#read 5, iclass 6, count 0 2006.196.07:20:17.82#ibcon#about to read 6, iclass 6, count 0 2006.196.07:20:17.82#ibcon#read 6, iclass 6, count 0 2006.196.07:20:17.82#ibcon#end of sib2, iclass 6, count 0 2006.196.07:20:17.82#ibcon#*after write, iclass 6, count 0 2006.196.07:20:17.82#ibcon#*before return 0, iclass 6, count 0 2006.196.07:20:17.82#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.196.07:20:17.82#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.196.07:20:17.82#ibcon#about to clear, iclass 6 cls_cnt 0 2006.196.07:20:17.82#ibcon#cleared, iclass 6 cls_cnt 0 2006.196.07:20:17.82$vc4f8/valo=4,832.99 2006.196.07:20:17.82#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.196.07:20:17.82#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.196.07:20:17.82#ibcon#ireg 17 cls_cnt 0 2006.196.07:20:17.82#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.196.07:20:17.82#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.196.07:20:17.82#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.196.07:20:17.82#ibcon#enter wrdev, iclass 10, count 0 2006.196.07:20:17.82#ibcon#first serial, iclass 10, count 0 2006.196.07:20:17.82#ibcon#enter sib2, iclass 10, count 0 2006.196.07:20:17.82#ibcon#flushed, iclass 10, count 0 2006.196.07:20:17.82#ibcon#about to write, iclass 10, count 0 2006.196.07:20:17.82#ibcon#wrote, iclass 10, count 0 2006.196.07:20:17.82#ibcon#about to read 3, iclass 10, count 0 2006.196.07:20:17.84#ibcon#read 3, iclass 10, count 0 2006.196.07:20:17.84#ibcon#about to read 4, iclass 10, count 0 2006.196.07:20:17.84#ibcon#read 4, iclass 10, count 0 2006.196.07:20:17.84#ibcon#about to read 5, iclass 10, count 0 2006.196.07:20:17.84#ibcon#read 5, iclass 10, count 0 2006.196.07:20:17.84#ibcon#about to read 6, iclass 10, count 0 2006.196.07:20:17.84#ibcon#read 6, iclass 10, count 0 2006.196.07:20:17.84#ibcon#end of sib2, iclass 10, count 0 2006.196.07:20:17.84#ibcon#*mode == 0, iclass 10, count 0 2006.196.07:20:17.84#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.196.07:20:17.84#ibcon#[26=FRQ=04,832.99\r\n] 2006.196.07:20:17.84#ibcon#*before write, iclass 10, count 0 2006.196.07:20:17.84#ibcon#enter sib2, iclass 10, count 0 2006.196.07:20:17.84#ibcon#flushed, iclass 10, count 0 2006.196.07:20:17.84#ibcon#about to write, iclass 10, count 0 2006.196.07:20:17.84#ibcon#wrote, iclass 10, count 0 2006.196.07:20:17.84#ibcon#about to read 3, iclass 10, count 0 2006.196.07:20:17.88#ibcon#read 3, iclass 10, count 0 2006.196.07:20:17.88#ibcon#about to read 4, iclass 10, count 0 2006.196.07:20:17.88#ibcon#read 4, iclass 10, count 0 2006.196.07:20:17.88#ibcon#about to read 5, iclass 10, count 0 2006.196.07:20:17.88#ibcon#read 5, iclass 10, count 0 2006.196.07:20:17.88#ibcon#about to read 6, iclass 10, count 0 2006.196.07:20:17.88#ibcon#read 6, iclass 10, count 0 2006.196.07:20:17.88#ibcon#end of sib2, iclass 10, count 0 2006.196.07:20:17.88#ibcon#*after write, iclass 10, count 0 2006.196.07:20:17.88#ibcon#*before return 0, iclass 10, count 0 2006.196.07:20:17.88#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.196.07:20:17.88#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.196.07:20:17.88#ibcon#about to clear, iclass 10 cls_cnt 0 2006.196.07:20:17.88#ibcon#cleared, iclass 10 cls_cnt 0 2006.196.07:20:17.88$vc4f8/va=4,7 2006.196.07:20:17.88#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.196.07:20:17.88#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.196.07:20:17.88#ibcon#ireg 11 cls_cnt 2 2006.196.07:20:17.88#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.196.07:20:17.94#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.196.07:20:17.94#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.196.07:20:17.94#ibcon#enter wrdev, iclass 12, count 2 2006.196.07:20:17.94#ibcon#first serial, iclass 12, count 2 2006.196.07:20:17.94#ibcon#enter sib2, iclass 12, count 2 2006.196.07:20:17.94#ibcon#flushed, iclass 12, count 2 2006.196.07:20:17.94#ibcon#about to write, iclass 12, count 2 2006.196.07:20:17.94#ibcon#wrote, iclass 12, count 2 2006.196.07:20:17.94#ibcon#about to read 3, iclass 12, count 2 2006.196.07:20:17.96#ibcon#read 3, iclass 12, count 2 2006.196.07:20:17.96#ibcon#about to read 4, iclass 12, count 2 2006.196.07:20:17.96#ibcon#read 4, iclass 12, count 2 2006.196.07:20:17.96#ibcon#about to read 5, iclass 12, count 2 2006.196.07:20:17.96#ibcon#read 5, iclass 12, count 2 2006.196.07:20:17.96#ibcon#about to read 6, iclass 12, count 2 2006.196.07:20:17.96#ibcon#read 6, iclass 12, count 2 2006.196.07:20:17.96#ibcon#end of sib2, iclass 12, count 2 2006.196.07:20:17.96#ibcon#*mode == 0, iclass 12, count 2 2006.196.07:20:17.96#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.196.07:20:17.96#ibcon#[25=AT04-07\r\n] 2006.196.07:20:17.96#ibcon#*before write, iclass 12, count 2 2006.196.07:20:17.96#ibcon#enter sib2, iclass 12, count 2 2006.196.07:20:17.96#ibcon#flushed, iclass 12, count 2 2006.196.07:20:17.96#ibcon#about to write, iclass 12, count 2 2006.196.07:20:17.96#ibcon#wrote, iclass 12, count 2 2006.196.07:20:17.96#ibcon#about to read 3, iclass 12, count 2 2006.196.07:20:17.99#ibcon#read 3, iclass 12, count 2 2006.196.07:20:17.99#ibcon#about to read 4, iclass 12, count 2 2006.196.07:20:17.99#ibcon#read 4, iclass 12, count 2 2006.196.07:20:17.99#ibcon#about to read 5, iclass 12, count 2 2006.196.07:20:17.99#ibcon#read 5, iclass 12, count 2 2006.196.07:20:17.99#ibcon#about to read 6, iclass 12, count 2 2006.196.07:20:17.99#ibcon#read 6, iclass 12, count 2 2006.196.07:20:17.99#ibcon#end of sib2, iclass 12, count 2 2006.196.07:20:17.99#ibcon#*after write, iclass 12, count 2 2006.196.07:20:17.99#ibcon#*before return 0, iclass 12, count 2 2006.196.07:20:17.99#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.196.07:20:17.99#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.196.07:20:17.99#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.196.07:20:17.99#ibcon#ireg 7 cls_cnt 0 2006.196.07:20:17.99#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.196.07:20:18.11#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.196.07:20:18.11#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.196.07:20:18.11#ibcon#enter wrdev, iclass 12, count 0 2006.196.07:20:18.11#ibcon#first serial, iclass 12, count 0 2006.196.07:20:18.11#ibcon#enter sib2, iclass 12, count 0 2006.196.07:20:18.11#ibcon#flushed, iclass 12, count 0 2006.196.07:20:18.11#ibcon#about to write, iclass 12, count 0 2006.196.07:20:18.11#ibcon#wrote, iclass 12, count 0 2006.196.07:20:18.11#ibcon#about to read 3, iclass 12, count 0 2006.196.07:20:18.13#ibcon#read 3, iclass 12, count 0 2006.196.07:20:18.13#ibcon#about to read 4, iclass 12, count 0 2006.196.07:20:18.13#ibcon#read 4, iclass 12, count 0 2006.196.07:20:18.13#ibcon#about to read 5, iclass 12, count 0 2006.196.07:20:18.13#ibcon#read 5, iclass 12, count 0 2006.196.07:20:18.13#ibcon#about to read 6, iclass 12, count 0 2006.196.07:20:18.13#ibcon#read 6, iclass 12, count 0 2006.196.07:20:18.13#ibcon#end of sib2, iclass 12, count 0 2006.196.07:20:18.13#ibcon#*mode == 0, iclass 12, count 0 2006.196.07:20:18.13#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.196.07:20:18.13#ibcon#[25=USB\r\n] 2006.196.07:20:18.13#ibcon#*before write, iclass 12, count 0 2006.196.07:20:18.13#ibcon#enter sib2, iclass 12, count 0 2006.196.07:20:18.13#ibcon#flushed, iclass 12, count 0 2006.196.07:20:18.13#ibcon#about to write, iclass 12, count 0 2006.196.07:20:18.13#ibcon#wrote, iclass 12, count 0 2006.196.07:20:18.13#ibcon#about to read 3, iclass 12, count 0 2006.196.07:20:18.16#ibcon#read 3, iclass 12, count 0 2006.196.07:20:18.16#ibcon#about to read 4, iclass 12, count 0 2006.196.07:20:18.16#ibcon#read 4, iclass 12, count 0 2006.196.07:20:18.16#ibcon#about to read 5, iclass 12, count 0 2006.196.07:20:18.16#ibcon#read 5, iclass 12, count 0 2006.196.07:20:18.16#ibcon#about to read 6, iclass 12, count 0 2006.196.07:20:18.16#ibcon#read 6, iclass 12, count 0 2006.196.07:20:18.16#ibcon#end of sib2, iclass 12, count 0 2006.196.07:20:18.16#ibcon#*after write, iclass 12, count 0 2006.196.07:20:18.16#ibcon#*before return 0, iclass 12, count 0 2006.196.07:20:18.16#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.196.07:20:18.16#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.196.07:20:18.16#ibcon#about to clear, iclass 12 cls_cnt 0 2006.196.07:20:18.16#ibcon#cleared, iclass 12 cls_cnt 0 2006.196.07:20:18.16$vc4f8/valo=5,652.99 2006.196.07:20:18.16#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.196.07:20:18.16#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.196.07:20:18.16#ibcon#ireg 17 cls_cnt 0 2006.196.07:20:18.16#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.196.07:20:18.16#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.196.07:20:18.16#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.196.07:20:18.16#ibcon#enter wrdev, iclass 14, count 0 2006.196.07:20:18.16#ibcon#first serial, iclass 14, count 0 2006.196.07:20:18.16#ibcon#enter sib2, iclass 14, count 0 2006.196.07:20:18.16#ibcon#flushed, iclass 14, count 0 2006.196.07:20:18.16#ibcon#about to write, iclass 14, count 0 2006.196.07:20:18.16#ibcon#wrote, iclass 14, count 0 2006.196.07:20:18.16#ibcon#about to read 3, iclass 14, count 0 2006.196.07:20:18.18#ibcon#read 3, iclass 14, count 0 2006.196.07:20:18.18#ibcon#about to read 4, iclass 14, count 0 2006.196.07:20:18.18#ibcon#read 4, iclass 14, count 0 2006.196.07:20:18.18#ibcon#about to read 5, iclass 14, count 0 2006.196.07:20:18.18#ibcon#read 5, iclass 14, count 0 2006.196.07:20:18.18#ibcon#about to read 6, iclass 14, count 0 2006.196.07:20:18.18#ibcon#read 6, iclass 14, count 0 2006.196.07:20:18.18#ibcon#end of sib2, iclass 14, count 0 2006.196.07:20:18.18#ibcon#*mode == 0, iclass 14, count 0 2006.196.07:20:18.18#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.196.07:20:18.18#ibcon#[26=FRQ=05,652.99\r\n] 2006.196.07:20:18.18#ibcon#*before write, iclass 14, count 0 2006.196.07:20:18.18#ibcon#enter sib2, iclass 14, count 0 2006.196.07:20:18.18#ibcon#flushed, iclass 14, count 0 2006.196.07:20:18.18#ibcon#about to write, iclass 14, count 0 2006.196.07:20:18.18#ibcon#wrote, iclass 14, count 0 2006.196.07:20:18.18#ibcon#about to read 3, iclass 14, count 0 2006.196.07:20:18.22#ibcon#read 3, iclass 14, count 0 2006.196.07:20:18.22#ibcon#about to read 4, iclass 14, count 0 2006.196.07:20:18.22#ibcon#read 4, iclass 14, count 0 2006.196.07:20:18.22#ibcon#about to read 5, iclass 14, count 0 2006.196.07:20:18.22#ibcon#read 5, iclass 14, count 0 2006.196.07:20:18.22#ibcon#about to read 6, iclass 14, count 0 2006.196.07:20:18.22#ibcon#read 6, iclass 14, count 0 2006.196.07:20:18.22#ibcon#end of sib2, iclass 14, count 0 2006.196.07:20:18.22#ibcon#*after write, iclass 14, count 0 2006.196.07:20:18.22#ibcon#*before return 0, iclass 14, count 0 2006.196.07:20:18.22#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.196.07:20:18.22#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.196.07:20:18.22#ibcon#about to clear, iclass 14 cls_cnt 0 2006.196.07:20:18.22#ibcon#cleared, iclass 14 cls_cnt 0 2006.196.07:20:18.22$vc4f8/va=5,7 2006.196.07:20:18.22#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.196.07:20:18.22#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.196.07:20:18.22#ibcon#ireg 11 cls_cnt 2 2006.196.07:20:18.22#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.196.07:20:18.28#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.196.07:20:18.28#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.196.07:20:18.28#ibcon#enter wrdev, iclass 16, count 2 2006.196.07:20:18.28#ibcon#first serial, iclass 16, count 2 2006.196.07:20:18.28#ibcon#enter sib2, iclass 16, count 2 2006.196.07:20:18.28#ibcon#flushed, iclass 16, count 2 2006.196.07:20:18.28#ibcon#about to write, iclass 16, count 2 2006.196.07:20:18.28#ibcon#wrote, iclass 16, count 2 2006.196.07:20:18.28#ibcon#about to read 3, iclass 16, count 2 2006.196.07:20:18.30#ibcon#read 3, iclass 16, count 2 2006.196.07:20:18.30#ibcon#about to read 4, iclass 16, count 2 2006.196.07:20:18.30#ibcon#read 4, iclass 16, count 2 2006.196.07:20:18.30#ibcon#about to read 5, iclass 16, count 2 2006.196.07:20:18.30#ibcon#read 5, iclass 16, count 2 2006.196.07:20:18.30#ibcon#about to read 6, iclass 16, count 2 2006.196.07:20:18.30#ibcon#read 6, iclass 16, count 2 2006.196.07:20:18.30#ibcon#end of sib2, iclass 16, count 2 2006.196.07:20:18.30#ibcon#*mode == 0, iclass 16, count 2 2006.196.07:20:18.30#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.196.07:20:18.30#ibcon#[25=AT05-07\r\n] 2006.196.07:20:18.30#ibcon#*before write, iclass 16, count 2 2006.196.07:20:18.30#ibcon#enter sib2, iclass 16, count 2 2006.196.07:20:18.30#ibcon#flushed, iclass 16, count 2 2006.196.07:20:18.30#ibcon#about to write, iclass 16, count 2 2006.196.07:20:18.30#ibcon#wrote, iclass 16, count 2 2006.196.07:20:18.30#ibcon#about to read 3, iclass 16, count 2 2006.196.07:20:18.33#ibcon#read 3, iclass 16, count 2 2006.196.07:20:18.33#ibcon#about to read 4, iclass 16, count 2 2006.196.07:20:18.33#ibcon#read 4, iclass 16, count 2 2006.196.07:20:18.33#ibcon#about to read 5, iclass 16, count 2 2006.196.07:20:18.33#ibcon#read 5, iclass 16, count 2 2006.196.07:20:18.33#ibcon#about to read 6, iclass 16, count 2 2006.196.07:20:18.33#ibcon#read 6, iclass 16, count 2 2006.196.07:20:18.33#ibcon#end of sib2, iclass 16, count 2 2006.196.07:20:18.33#ibcon#*after write, iclass 16, count 2 2006.196.07:20:18.33#ibcon#*before return 0, iclass 16, count 2 2006.196.07:20:18.33#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.196.07:20:18.33#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.196.07:20:18.33#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.196.07:20:18.33#ibcon#ireg 7 cls_cnt 0 2006.196.07:20:18.33#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.196.07:20:18.45#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.196.07:20:18.45#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.196.07:20:18.45#ibcon#enter wrdev, iclass 16, count 0 2006.196.07:20:18.45#ibcon#first serial, iclass 16, count 0 2006.196.07:20:18.45#ibcon#enter sib2, iclass 16, count 0 2006.196.07:20:18.45#ibcon#flushed, iclass 16, count 0 2006.196.07:20:18.45#ibcon#about to write, iclass 16, count 0 2006.196.07:20:18.45#ibcon#wrote, iclass 16, count 0 2006.196.07:20:18.45#ibcon#about to read 3, iclass 16, count 0 2006.196.07:20:18.47#ibcon#read 3, iclass 16, count 0 2006.196.07:20:18.47#ibcon#about to read 4, iclass 16, count 0 2006.196.07:20:18.47#ibcon#read 4, iclass 16, count 0 2006.196.07:20:18.47#ibcon#about to read 5, iclass 16, count 0 2006.196.07:20:18.47#ibcon#read 5, iclass 16, count 0 2006.196.07:20:18.47#ibcon#about to read 6, iclass 16, count 0 2006.196.07:20:18.47#ibcon#read 6, iclass 16, count 0 2006.196.07:20:18.47#ibcon#end of sib2, iclass 16, count 0 2006.196.07:20:18.47#ibcon#*mode == 0, iclass 16, count 0 2006.196.07:20:18.47#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.196.07:20:18.47#ibcon#[25=USB\r\n] 2006.196.07:20:18.47#ibcon#*before write, iclass 16, count 0 2006.196.07:20:18.47#ibcon#enter sib2, iclass 16, count 0 2006.196.07:20:18.47#ibcon#flushed, iclass 16, count 0 2006.196.07:20:18.47#ibcon#about to write, iclass 16, count 0 2006.196.07:20:18.47#ibcon#wrote, iclass 16, count 0 2006.196.07:20:18.47#ibcon#about to read 3, iclass 16, count 0 2006.196.07:20:18.50#ibcon#read 3, iclass 16, count 0 2006.196.07:20:18.50#ibcon#about to read 4, iclass 16, count 0 2006.196.07:20:18.50#ibcon#read 4, iclass 16, count 0 2006.196.07:20:18.50#ibcon#about to read 5, iclass 16, count 0 2006.196.07:20:18.50#ibcon#read 5, iclass 16, count 0 2006.196.07:20:18.50#ibcon#about to read 6, iclass 16, count 0 2006.196.07:20:18.50#ibcon#read 6, iclass 16, count 0 2006.196.07:20:18.50#ibcon#end of sib2, iclass 16, count 0 2006.196.07:20:18.50#ibcon#*after write, iclass 16, count 0 2006.196.07:20:18.50#ibcon#*before return 0, iclass 16, count 0 2006.196.07:20:18.50#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.196.07:20:18.50#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.196.07:20:18.50#ibcon#about to clear, iclass 16 cls_cnt 0 2006.196.07:20:18.50#ibcon#cleared, iclass 16 cls_cnt 0 2006.196.07:20:18.50$vc4f8/valo=6,772.99 2006.196.07:20:18.50#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.196.07:20:18.50#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.196.07:20:18.50#ibcon#ireg 17 cls_cnt 0 2006.196.07:20:18.50#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.196.07:20:18.50#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.196.07:20:18.50#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.196.07:20:18.50#ibcon#enter wrdev, iclass 18, count 0 2006.196.07:20:18.50#ibcon#first serial, iclass 18, count 0 2006.196.07:20:18.50#ibcon#enter sib2, iclass 18, count 0 2006.196.07:20:18.50#ibcon#flushed, iclass 18, count 0 2006.196.07:20:18.50#ibcon#about to write, iclass 18, count 0 2006.196.07:20:18.50#ibcon#wrote, iclass 18, count 0 2006.196.07:20:18.50#ibcon#about to read 3, iclass 18, count 0 2006.196.07:20:18.52#ibcon#read 3, iclass 18, count 0 2006.196.07:20:18.52#ibcon#about to read 4, iclass 18, count 0 2006.196.07:20:18.52#ibcon#read 4, iclass 18, count 0 2006.196.07:20:18.52#ibcon#about to read 5, iclass 18, count 0 2006.196.07:20:18.52#ibcon#read 5, iclass 18, count 0 2006.196.07:20:18.52#ibcon#about to read 6, iclass 18, count 0 2006.196.07:20:18.52#ibcon#read 6, iclass 18, count 0 2006.196.07:20:18.52#ibcon#end of sib2, iclass 18, count 0 2006.196.07:20:18.52#ibcon#*mode == 0, iclass 18, count 0 2006.196.07:20:18.52#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.196.07:20:18.52#ibcon#[26=FRQ=06,772.99\r\n] 2006.196.07:20:18.52#ibcon#*before write, iclass 18, count 0 2006.196.07:20:18.52#ibcon#enter sib2, iclass 18, count 0 2006.196.07:20:18.52#ibcon#flushed, iclass 18, count 0 2006.196.07:20:18.52#ibcon#about to write, iclass 18, count 0 2006.196.07:20:18.52#ibcon#wrote, iclass 18, count 0 2006.196.07:20:18.52#ibcon#about to read 3, iclass 18, count 0 2006.196.07:20:18.56#ibcon#read 3, iclass 18, count 0 2006.196.07:20:18.56#ibcon#about to read 4, iclass 18, count 0 2006.196.07:20:18.56#ibcon#read 4, iclass 18, count 0 2006.196.07:20:18.56#ibcon#about to read 5, iclass 18, count 0 2006.196.07:20:18.56#ibcon#read 5, iclass 18, count 0 2006.196.07:20:18.56#ibcon#about to read 6, iclass 18, count 0 2006.196.07:20:18.56#ibcon#read 6, iclass 18, count 0 2006.196.07:20:18.56#ibcon#end of sib2, iclass 18, count 0 2006.196.07:20:18.56#ibcon#*after write, iclass 18, count 0 2006.196.07:20:18.56#ibcon#*before return 0, iclass 18, count 0 2006.196.07:20:18.56#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.196.07:20:18.56#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.196.07:20:18.56#ibcon#about to clear, iclass 18 cls_cnt 0 2006.196.07:20:18.56#ibcon#cleared, iclass 18 cls_cnt 0 2006.196.07:20:18.56$vc4f8/va=6,6 2006.196.07:20:18.56#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.196.07:20:18.56#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.196.07:20:18.56#ibcon#ireg 11 cls_cnt 2 2006.196.07:20:18.56#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.196.07:20:18.62#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.196.07:20:18.62#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.196.07:20:18.62#ibcon#enter wrdev, iclass 20, count 2 2006.196.07:20:18.62#ibcon#first serial, iclass 20, count 2 2006.196.07:20:18.62#ibcon#enter sib2, iclass 20, count 2 2006.196.07:20:18.62#ibcon#flushed, iclass 20, count 2 2006.196.07:20:18.62#ibcon#about to write, iclass 20, count 2 2006.196.07:20:18.62#ibcon#wrote, iclass 20, count 2 2006.196.07:20:18.62#ibcon#about to read 3, iclass 20, count 2 2006.196.07:20:18.64#ibcon#read 3, iclass 20, count 2 2006.196.07:20:18.64#ibcon#about to read 4, iclass 20, count 2 2006.196.07:20:18.64#ibcon#read 4, iclass 20, count 2 2006.196.07:20:18.64#ibcon#about to read 5, iclass 20, count 2 2006.196.07:20:18.64#ibcon#read 5, iclass 20, count 2 2006.196.07:20:18.64#ibcon#about to read 6, iclass 20, count 2 2006.196.07:20:18.64#ibcon#read 6, iclass 20, count 2 2006.196.07:20:18.64#ibcon#end of sib2, iclass 20, count 2 2006.196.07:20:18.64#ibcon#*mode == 0, iclass 20, count 2 2006.196.07:20:18.64#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.196.07:20:18.64#ibcon#[25=AT06-06\r\n] 2006.196.07:20:18.64#ibcon#*before write, iclass 20, count 2 2006.196.07:20:18.64#ibcon#enter sib2, iclass 20, count 2 2006.196.07:20:18.64#ibcon#flushed, iclass 20, count 2 2006.196.07:20:18.64#ibcon#about to write, iclass 20, count 2 2006.196.07:20:18.64#ibcon#wrote, iclass 20, count 2 2006.196.07:20:18.64#ibcon#about to read 3, iclass 20, count 2 2006.196.07:20:18.67#ibcon#read 3, iclass 20, count 2 2006.196.07:20:18.67#ibcon#about to read 4, iclass 20, count 2 2006.196.07:20:18.67#ibcon#read 4, iclass 20, count 2 2006.196.07:20:18.67#ibcon#about to read 5, iclass 20, count 2 2006.196.07:20:18.67#ibcon#read 5, iclass 20, count 2 2006.196.07:20:18.67#ibcon#about to read 6, iclass 20, count 2 2006.196.07:20:18.67#ibcon#read 6, iclass 20, count 2 2006.196.07:20:18.67#ibcon#end of sib2, iclass 20, count 2 2006.196.07:20:18.67#ibcon#*after write, iclass 20, count 2 2006.196.07:20:18.67#ibcon#*before return 0, iclass 20, count 2 2006.196.07:20:18.67#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.196.07:20:18.67#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.196.07:20:18.67#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.196.07:20:18.67#ibcon#ireg 7 cls_cnt 0 2006.196.07:20:18.67#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.196.07:20:18.79#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.196.07:20:18.79#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.196.07:20:18.79#ibcon#enter wrdev, iclass 20, count 0 2006.196.07:20:18.79#ibcon#first serial, iclass 20, count 0 2006.196.07:20:18.79#ibcon#enter sib2, iclass 20, count 0 2006.196.07:20:18.79#ibcon#flushed, iclass 20, count 0 2006.196.07:20:18.79#ibcon#about to write, iclass 20, count 0 2006.196.07:20:18.79#ibcon#wrote, iclass 20, count 0 2006.196.07:20:18.79#ibcon#about to read 3, iclass 20, count 0 2006.196.07:20:18.81#ibcon#read 3, iclass 20, count 0 2006.196.07:20:18.81#ibcon#about to read 4, iclass 20, count 0 2006.196.07:20:18.81#ibcon#read 4, iclass 20, count 0 2006.196.07:20:18.81#ibcon#about to read 5, iclass 20, count 0 2006.196.07:20:18.81#ibcon#read 5, iclass 20, count 0 2006.196.07:20:18.81#ibcon#about to read 6, iclass 20, count 0 2006.196.07:20:18.81#ibcon#read 6, iclass 20, count 0 2006.196.07:20:18.81#ibcon#end of sib2, iclass 20, count 0 2006.196.07:20:18.81#ibcon#*mode == 0, iclass 20, count 0 2006.196.07:20:18.81#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.196.07:20:18.81#ibcon#[25=USB\r\n] 2006.196.07:20:18.81#ibcon#*before write, iclass 20, count 0 2006.196.07:20:18.81#ibcon#enter sib2, iclass 20, count 0 2006.196.07:20:18.81#ibcon#flushed, iclass 20, count 0 2006.196.07:20:18.81#ibcon#about to write, iclass 20, count 0 2006.196.07:20:18.81#ibcon#wrote, iclass 20, count 0 2006.196.07:20:18.81#ibcon#about to read 3, iclass 20, count 0 2006.196.07:20:18.84#ibcon#read 3, iclass 20, count 0 2006.196.07:20:18.84#ibcon#about to read 4, iclass 20, count 0 2006.196.07:20:18.84#ibcon#read 4, iclass 20, count 0 2006.196.07:20:18.84#ibcon#about to read 5, iclass 20, count 0 2006.196.07:20:18.84#ibcon#read 5, iclass 20, count 0 2006.196.07:20:18.84#ibcon#about to read 6, iclass 20, count 0 2006.196.07:20:18.84#ibcon#read 6, iclass 20, count 0 2006.196.07:20:18.84#ibcon#end of sib2, iclass 20, count 0 2006.196.07:20:18.84#ibcon#*after write, iclass 20, count 0 2006.196.07:20:18.84#ibcon#*before return 0, iclass 20, count 0 2006.196.07:20:18.84#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.196.07:20:18.84#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.196.07:20:18.84#ibcon#about to clear, iclass 20 cls_cnt 0 2006.196.07:20:18.84#ibcon#cleared, iclass 20 cls_cnt 0 2006.196.07:20:18.84$vc4f8/valo=7,832.99 2006.196.07:20:18.84#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.196.07:20:18.84#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.196.07:20:18.84#ibcon#ireg 17 cls_cnt 0 2006.196.07:20:18.84#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.196.07:20:18.84#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.196.07:20:18.84#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.196.07:20:18.84#ibcon#enter wrdev, iclass 22, count 0 2006.196.07:20:18.84#ibcon#first serial, iclass 22, count 0 2006.196.07:20:18.84#ibcon#enter sib2, iclass 22, count 0 2006.196.07:20:18.84#ibcon#flushed, iclass 22, count 0 2006.196.07:20:18.84#ibcon#about to write, iclass 22, count 0 2006.196.07:20:18.84#ibcon#wrote, iclass 22, count 0 2006.196.07:20:18.84#ibcon#about to read 3, iclass 22, count 0 2006.196.07:20:18.86#ibcon#read 3, iclass 22, count 0 2006.196.07:20:18.86#ibcon#about to read 4, iclass 22, count 0 2006.196.07:20:18.86#ibcon#read 4, iclass 22, count 0 2006.196.07:20:18.86#ibcon#about to read 5, iclass 22, count 0 2006.196.07:20:18.86#ibcon#read 5, iclass 22, count 0 2006.196.07:20:18.86#ibcon#about to read 6, iclass 22, count 0 2006.196.07:20:18.86#ibcon#read 6, iclass 22, count 0 2006.196.07:20:18.86#ibcon#end of sib2, iclass 22, count 0 2006.196.07:20:18.86#ibcon#*mode == 0, iclass 22, count 0 2006.196.07:20:18.86#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.196.07:20:18.86#ibcon#[26=FRQ=07,832.99\r\n] 2006.196.07:20:18.86#ibcon#*before write, iclass 22, count 0 2006.196.07:20:18.86#ibcon#enter sib2, iclass 22, count 0 2006.196.07:20:18.86#ibcon#flushed, iclass 22, count 0 2006.196.07:20:18.86#ibcon#about to write, iclass 22, count 0 2006.196.07:20:18.86#ibcon#wrote, iclass 22, count 0 2006.196.07:20:18.86#ibcon#about to read 3, iclass 22, count 0 2006.196.07:20:18.90#ibcon#read 3, iclass 22, count 0 2006.196.07:20:18.90#ibcon#about to read 4, iclass 22, count 0 2006.196.07:20:18.90#ibcon#read 4, iclass 22, count 0 2006.196.07:20:18.90#ibcon#about to read 5, iclass 22, count 0 2006.196.07:20:18.90#ibcon#read 5, iclass 22, count 0 2006.196.07:20:18.90#ibcon#about to read 6, iclass 22, count 0 2006.196.07:20:18.90#ibcon#read 6, iclass 22, count 0 2006.196.07:20:18.90#ibcon#end of sib2, iclass 22, count 0 2006.196.07:20:18.90#ibcon#*after write, iclass 22, count 0 2006.196.07:20:18.90#ibcon#*before return 0, iclass 22, count 0 2006.196.07:20:18.90#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.196.07:20:18.90#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.196.07:20:18.90#ibcon#about to clear, iclass 22 cls_cnt 0 2006.196.07:20:18.90#ibcon#cleared, iclass 22 cls_cnt 0 2006.196.07:20:18.90$vc4f8/va=7,6 2006.196.07:20:18.90#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.196.07:20:18.90#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.196.07:20:18.90#ibcon#ireg 11 cls_cnt 2 2006.196.07:20:18.90#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.196.07:20:18.96#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.196.07:20:18.96#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.196.07:20:18.96#ibcon#enter wrdev, iclass 24, count 2 2006.196.07:20:18.96#ibcon#first serial, iclass 24, count 2 2006.196.07:20:18.96#ibcon#enter sib2, iclass 24, count 2 2006.196.07:20:18.96#ibcon#flushed, iclass 24, count 2 2006.196.07:20:18.96#ibcon#about to write, iclass 24, count 2 2006.196.07:20:18.96#ibcon#wrote, iclass 24, count 2 2006.196.07:20:18.96#ibcon#about to read 3, iclass 24, count 2 2006.196.07:20:18.98#ibcon#read 3, iclass 24, count 2 2006.196.07:20:18.98#ibcon#about to read 4, iclass 24, count 2 2006.196.07:20:18.98#ibcon#read 4, iclass 24, count 2 2006.196.07:20:18.98#ibcon#about to read 5, iclass 24, count 2 2006.196.07:20:18.98#ibcon#read 5, iclass 24, count 2 2006.196.07:20:18.98#ibcon#about to read 6, iclass 24, count 2 2006.196.07:20:18.98#ibcon#read 6, iclass 24, count 2 2006.196.07:20:18.98#ibcon#end of sib2, iclass 24, count 2 2006.196.07:20:18.98#ibcon#*mode == 0, iclass 24, count 2 2006.196.07:20:18.98#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.196.07:20:18.98#ibcon#[25=AT07-06\r\n] 2006.196.07:20:18.98#ibcon#*before write, iclass 24, count 2 2006.196.07:20:18.98#ibcon#enter sib2, iclass 24, count 2 2006.196.07:20:18.98#ibcon#flushed, iclass 24, count 2 2006.196.07:20:18.98#ibcon#about to write, iclass 24, count 2 2006.196.07:20:18.98#ibcon#wrote, iclass 24, count 2 2006.196.07:20:18.98#ibcon#about to read 3, iclass 24, count 2 2006.196.07:20:19.01#ibcon#read 3, iclass 24, count 2 2006.196.07:20:19.01#ibcon#about to read 4, iclass 24, count 2 2006.196.07:20:19.01#ibcon#read 4, iclass 24, count 2 2006.196.07:20:19.01#ibcon#about to read 5, iclass 24, count 2 2006.196.07:20:19.01#ibcon#read 5, iclass 24, count 2 2006.196.07:20:19.01#ibcon#about to read 6, iclass 24, count 2 2006.196.07:20:19.01#ibcon#read 6, iclass 24, count 2 2006.196.07:20:19.01#ibcon#end of sib2, iclass 24, count 2 2006.196.07:20:19.01#ibcon#*after write, iclass 24, count 2 2006.196.07:20:19.01#ibcon#*before return 0, iclass 24, count 2 2006.196.07:20:19.01#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.196.07:20:19.01#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.196.07:20:19.01#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.196.07:20:19.01#ibcon#ireg 7 cls_cnt 0 2006.196.07:20:19.01#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.196.07:20:19.13#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.196.07:20:19.13#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.196.07:20:19.13#ibcon#enter wrdev, iclass 24, count 0 2006.196.07:20:19.13#ibcon#first serial, iclass 24, count 0 2006.196.07:20:19.13#ibcon#enter sib2, iclass 24, count 0 2006.196.07:20:19.13#ibcon#flushed, iclass 24, count 0 2006.196.07:20:19.13#ibcon#about to write, iclass 24, count 0 2006.196.07:20:19.13#ibcon#wrote, iclass 24, count 0 2006.196.07:20:19.13#ibcon#about to read 3, iclass 24, count 0 2006.196.07:20:19.15#ibcon#read 3, iclass 24, count 0 2006.196.07:20:19.15#ibcon#about to read 4, iclass 24, count 0 2006.196.07:20:19.15#ibcon#read 4, iclass 24, count 0 2006.196.07:20:19.15#ibcon#about to read 5, iclass 24, count 0 2006.196.07:20:19.15#ibcon#read 5, iclass 24, count 0 2006.196.07:20:19.15#ibcon#about to read 6, iclass 24, count 0 2006.196.07:20:19.15#ibcon#read 6, iclass 24, count 0 2006.196.07:20:19.15#ibcon#end of sib2, iclass 24, count 0 2006.196.07:20:19.15#ibcon#*mode == 0, iclass 24, count 0 2006.196.07:20:19.15#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.196.07:20:19.15#ibcon#[25=USB\r\n] 2006.196.07:20:19.15#ibcon#*before write, iclass 24, count 0 2006.196.07:20:19.15#ibcon#enter sib2, iclass 24, count 0 2006.196.07:20:19.15#ibcon#flushed, iclass 24, count 0 2006.196.07:20:19.15#ibcon#about to write, iclass 24, count 0 2006.196.07:20:19.15#ibcon#wrote, iclass 24, count 0 2006.196.07:20:19.15#ibcon#about to read 3, iclass 24, count 0 2006.196.07:20:19.18#ibcon#read 3, iclass 24, count 0 2006.196.07:20:19.18#ibcon#about to read 4, iclass 24, count 0 2006.196.07:20:19.18#ibcon#read 4, iclass 24, count 0 2006.196.07:20:19.18#ibcon#about to read 5, iclass 24, count 0 2006.196.07:20:19.18#ibcon#read 5, iclass 24, count 0 2006.196.07:20:19.18#ibcon#about to read 6, iclass 24, count 0 2006.196.07:20:19.18#ibcon#read 6, iclass 24, count 0 2006.196.07:20:19.18#ibcon#end of sib2, iclass 24, count 0 2006.196.07:20:19.18#ibcon#*after write, iclass 24, count 0 2006.196.07:20:19.18#ibcon#*before return 0, iclass 24, count 0 2006.196.07:20:19.18#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.196.07:20:19.18#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.196.07:20:19.18#ibcon#about to clear, iclass 24 cls_cnt 0 2006.196.07:20:19.18#ibcon#cleared, iclass 24 cls_cnt 0 2006.196.07:20:19.18$vc4f8/valo=8,852.99 2006.196.07:20:19.18#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.196.07:20:19.18#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.196.07:20:19.18#ibcon#ireg 17 cls_cnt 0 2006.196.07:20:19.18#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.196.07:20:19.18#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.196.07:20:19.18#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.196.07:20:19.18#ibcon#enter wrdev, iclass 26, count 0 2006.196.07:20:19.18#ibcon#first serial, iclass 26, count 0 2006.196.07:20:19.18#ibcon#enter sib2, iclass 26, count 0 2006.196.07:20:19.18#ibcon#flushed, iclass 26, count 0 2006.196.07:20:19.18#ibcon#about to write, iclass 26, count 0 2006.196.07:20:19.18#ibcon#wrote, iclass 26, count 0 2006.196.07:20:19.18#ibcon#about to read 3, iclass 26, count 0 2006.196.07:20:19.20#ibcon#read 3, iclass 26, count 0 2006.196.07:20:19.20#ibcon#about to read 4, iclass 26, count 0 2006.196.07:20:19.20#ibcon#read 4, iclass 26, count 0 2006.196.07:20:19.20#ibcon#about to read 5, iclass 26, count 0 2006.196.07:20:19.20#ibcon#read 5, iclass 26, count 0 2006.196.07:20:19.20#ibcon#about to read 6, iclass 26, count 0 2006.196.07:20:19.20#ibcon#read 6, iclass 26, count 0 2006.196.07:20:19.20#ibcon#end of sib2, iclass 26, count 0 2006.196.07:20:19.20#ibcon#*mode == 0, iclass 26, count 0 2006.196.07:20:19.20#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.196.07:20:19.20#ibcon#[26=FRQ=08,852.99\r\n] 2006.196.07:20:19.20#ibcon#*before write, iclass 26, count 0 2006.196.07:20:19.20#ibcon#enter sib2, iclass 26, count 0 2006.196.07:20:19.20#ibcon#flushed, iclass 26, count 0 2006.196.07:20:19.20#ibcon#about to write, iclass 26, count 0 2006.196.07:20:19.20#ibcon#wrote, iclass 26, count 0 2006.196.07:20:19.20#ibcon#about to read 3, iclass 26, count 0 2006.196.07:20:19.24#ibcon#read 3, iclass 26, count 0 2006.196.07:20:19.24#ibcon#about to read 4, iclass 26, count 0 2006.196.07:20:19.24#ibcon#read 4, iclass 26, count 0 2006.196.07:20:19.24#ibcon#about to read 5, iclass 26, count 0 2006.196.07:20:19.24#ibcon#read 5, iclass 26, count 0 2006.196.07:20:19.24#ibcon#about to read 6, iclass 26, count 0 2006.196.07:20:19.24#ibcon#read 6, iclass 26, count 0 2006.196.07:20:19.24#ibcon#end of sib2, iclass 26, count 0 2006.196.07:20:19.24#ibcon#*after write, iclass 26, count 0 2006.196.07:20:19.24#ibcon#*before return 0, iclass 26, count 0 2006.196.07:20:19.24#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.196.07:20:19.24#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.196.07:20:19.24#ibcon#about to clear, iclass 26 cls_cnt 0 2006.196.07:20:19.24#ibcon#cleared, iclass 26 cls_cnt 0 2006.196.07:20:19.24$vc4f8/va=8,7 2006.196.07:20:19.24#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.196.07:20:19.24#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.196.07:20:19.24#ibcon#ireg 11 cls_cnt 2 2006.196.07:20:19.24#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.196.07:20:19.30#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.196.07:20:19.30#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.196.07:20:19.30#ibcon#enter wrdev, iclass 28, count 2 2006.196.07:20:19.30#ibcon#first serial, iclass 28, count 2 2006.196.07:20:19.30#ibcon#enter sib2, iclass 28, count 2 2006.196.07:20:19.30#ibcon#flushed, iclass 28, count 2 2006.196.07:20:19.30#ibcon#about to write, iclass 28, count 2 2006.196.07:20:19.30#ibcon#wrote, iclass 28, count 2 2006.196.07:20:19.30#ibcon#about to read 3, iclass 28, count 2 2006.196.07:20:19.32#ibcon#read 3, iclass 28, count 2 2006.196.07:20:19.32#ibcon#about to read 4, iclass 28, count 2 2006.196.07:20:19.32#ibcon#read 4, iclass 28, count 2 2006.196.07:20:19.32#ibcon#about to read 5, iclass 28, count 2 2006.196.07:20:19.32#ibcon#read 5, iclass 28, count 2 2006.196.07:20:19.32#ibcon#about to read 6, iclass 28, count 2 2006.196.07:20:19.32#ibcon#read 6, iclass 28, count 2 2006.196.07:20:19.32#ibcon#end of sib2, iclass 28, count 2 2006.196.07:20:19.32#ibcon#*mode == 0, iclass 28, count 2 2006.196.07:20:19.32#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.196.07:20:19.32#ibcon#[25=AT08-07\r\n] 2006.196.07:20:19.32#ibcon#*before write, iclass 28, count 2 2006.196.07:20:19.32#ibcon#enter sib2, iclass 28, count 2 2006.196.07:20:19.32#ibcon#flushed, iclass 28, count 2 2006.196.07:20:19.32#ibcon#about to write, iclass 28, count 2 2006.196.07:20:19.32#ibcon#wrote, iclass 28, count 2 2006.196.07:20:19.32#ibcon#about to read 3, iclass 28, count 2 2006.196.07:20:19.35#ibcon#read 3, iclass 28, count 2 2006.196.07:20:19.35#ibcon#about to read 4, iclass 28, count 2 2006.196.07:20:19.35#ibcon#read 4, iclass 28, count 2 2006.196.07:20:19.35#ibcon#about to read 5, iclass 28, count 2 2006.196.07:20:19.35#ibcon#read 5, iclass 28, count 2 2006.196.07:20:19.35#ibcon#about to read 6, iclass 28, count 2 2006.196.07:20:19.35#ibcon#read 6, iclass 28, count 2 2006.196.07:20:19.35#ibcon#end of sib2, iclass 28, count 2 2006.196.07:20:19.35#ibcon#*after write, iclass 28, count 2 2006.196.07:20:19.35#ibcon#*before return 0, iclass 28, count 2 2006.196.07:20:19.35#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.196.07:20:19.35#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.196.07:20:19.35#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.196.07:20:19.35#ibcon#ireg 7 cls_cnt 0 2006.196.07:20:19.35#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.196.07:20:19.47#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.196.07:20:19.47#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.196.07:20:19.47#ibcon#enter wrdev, iclass 28, count 0 2006.196.07:20:19.47#ibcon#first serial, iclass 28, count 0 2006.196.07:20:19.47#ibcon#enter sib2, iclass 28, count 0 2006.196.07:20:19.47#ibcon#flushed, iclass 28, count 0 2006.196.07:20:19.47#ibcon#about to write, iclass 28, count 0 2006.196.07:20:19.47#ibcon#wrote, iclass 28, count 0 2006.196.07:20:19.47#ibcon#about to read 3, iclass 28, count 0 2006.196.07:20:19.49#ibcon#read 3, iclass 28, count 0 2006.196.07:20:19.49#ibcon#about to read 4, iclass 28, count 0 2006.196.07:20:19.49#ibcon#read 4, iclass 28, count 0 2006.196.07:20:19.49#ibcon#about to read 5, iclass 28, count 0 2006.196.07:20:19.49#ibcon#read 5, iclass 28, count 0 2006.196.07:20:19.49#ibcon#about to read 6, iclass 28, count 0 2006.196.07:20:19.49#ibcon#read 6, iclass 28, count 0 2006.196.07:20:19.49#ibcon#end of sib2, iclass 28, count 0 2006.196.07:20:19.49#ibcon#*mode == 0, iclass 28, count 0 2006.196.07:20:19.49#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.196.07:20:19.49#ibcon#[25=USB\r\n] 2006.196.07:20:19.49#ibcon#*before write, iclass 28, count 0 2006.196.07:20:19.49#ibcon#enter sib2, iclass 28, count 0 2006.196.07:20:19.49#ibcon#flushed, iclass 28, count 0 2006.196.07:20:19.49#ibcon#about to write, iclass 28, count 0 2006.196.07:20:19.49#ibcon#wrote, iclass 28, count 0 2006.196.07:20:19.49#ibcon#about to read 3, iclass 28, count 0 2006.196.07:20:19.52#ibcon#read 3, iclass 28, count 0 2006.196.07:20:19.52#ibcon#about to read 4, iclass 28, count 0 2006.196.07:20:19.52#ibcon#read 4, iclass 28, count 0 2006.196.07:20:19.52#ibcon#about to read 5, iclass 28, count 0 2006.196.07:20:19.52#ibcon#read 5, iclass 28, count 0 2006.196.07:20:19.52#ibcon#about to read 6, iclass 28, count 0 2006.196.07:20:19.52#ibcon#read 6, iclass 28, count 0 2006.196.07:20:19.52#ibcon#end of sib2, iclass 28, count 0 2006.196.07:20:19.52#ibcon#*after write, iclass 28, count 0 2006.196.07:20:19.52#ibcon#*before return 0, iclass 28, count 0 2006.196.07:20:19.52#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.196.07:20:19.52#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.196.07:20:19.52#ibcon#about to clear, iclass 28 cls_cnt 0 2006.196.07:20:19.52#ibcon#cleared, iclass 28 cls_cnt 0 2006.196.07:20:19.52$vc4f8/vblo=1,632.99 2006.196.07:20:19.52#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.196.07:20:19.52#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.196.07:20:19.52#ibcon#ireg 17 cls_cnt 0 2006.196.07:20:19.52#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.196.07:20:19.52#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.196.07:20:19.52#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.196.07:20:19.52#ibcon#enter wrdev, iclass 30, count 0 2006.196.07:20:19.52#ibcon#first serial, iclass 30, count 0 2006.196.07:20:19.52#ibcon#enter sib2, iclass 30, count 0 2006.196.07:20:19.52#ibcon#flushed, iclass 30, count 0 2006.196.07:20:19.52#ibcon#about to write, iclass 30, count 0 2006.196.07:20:19.52#ibcon#wrote, iclass 30, count 0 2006.196.07:20:19.52#ibcon#about to read 3, iclass 30, count 0 2006.196.07:20:19.54#ibcon#read 3, iclass 30, count 0 2006.196.07:20:19.54#ibcon#about to read 4, iclass 30, count 0 2006.196.07:20:19.54#ibcon#read 4, iclass 30, count 0 2006.196.07:20:19.54#ibcon#about to read 5, iclass 30, count 0 2006.196.07:20:19.54#ibcon#read 5, iclass 30, count 0 2006.196.07:20:19.54#ibcon#about to read 6, iclass 30, count 0 2006.196.07:20:19.54#ibcon#read 6, iclass 30, count 0 2006.196.07:20:19.54#ibcon#end of sib2, iclass 30, count 0 2006.196.07:20:19.54#ibcon#*mode == 0, iclass 30, count 0 2006.196.07:20:19.54#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.196.07:20:19.54#ibcon#[28=FRQ=01,632.99\r\n] 2006.196.07:20:19.54#ibcon#*before write, iclass 30, count 0 2006.196.07:20:19.54#ibcon#enter sib2, iclass 30, count 0 2006.196.07:20:19.54#ibcon#flushed, iclass 30, count 0 2006.196.07:20:19.54#ibcon#about to write, iclass 30, count 0 2006.196.07:20:19.54#ibcon#wrote, iclass 30, count 0 2006.196.07:20:19.54#ibcon#about to read 3, iclass 30, count 0 2006.196.07:20:19.60#ibcon#read 3, iclass 30, count 0 2006.196.07:20:19.60#ibcon#about to read 4, iclass 30, count 0 2006.196.07:20:19.60#ibcon#read 4, iclass 30, count 0 2006.196.07:20:19.60#ibcon#about to read 5, iclass 30, count 0 2006.196.07:20:19.60#ibcon#read 5, iclass 30, count 0 2006.196.07:20:19.60#ibcon#about to read 6, iclass 30, count 0 2006.196.07:20:19.60#ibcon#read 6, iclass 30, count 0 2006.196.07:20:19.60#ibcon#end of sib2, iclass 30, count 0 2006.196.07:20:19.60#ibcon#*after write, iclass 30, count 0 2006.196.07:20:19.60#ibcon#*before return 0, iclass 30, count 0 2006.196.07:20:19.60#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.196.07:20:19.60#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.196.07:20:19.60#ibcon#about to clear, iclass 30 cls_cnt 0 2006.196.07:20:19.60#ibcon#cleared, iclass 30 cls_cnt 0 2006.196.07:20:19.60$vc4f8/vb=1,4 2006.196.07:20:19.60#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.196.07:20:19.60#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.196.07:20:19.60#ibcon#ireg 11 cls_cnt 2 2006.196.07:20:19.60#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.196.07:20:19.60#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.196.07:20:19.60#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.196.07:20:19.60#ibcon#enter wrdev, iclass 32, count 2 2006.196.07:20:19.60#ibcon#first serial, iclass 32, count 2 2006.196.07:20:19.60#ibcon#enter sib2, iclass 32, count 2 2006.196.07:20:19.60#ibcon#flushed, iclass 32, count 2 2006.196.07:20:19.60#ibcon#about to write, iclass 32, count 2 2006.196.07:20:19.60#ibcon#wrote, iclass 32, count 2 2006.196.07:20:19.60#ibcon#about to read 3, iclass 32, count 2 2006.196.07:20:19.62#ibcon#read 3, iclass 32, count 2 2006.196.07:20:19.62#ibcon#about to read 4, iclass 32, count 2 2006.196.07:20:19.62#ibcon#read 4, iclass 32, count 2 2006.196.07:20:19.62#ibcon#about to read 5, iclass 32, count 2 2006.196.07:20:19.62#ibcon#read 5, iclass 32, count 2 2006.196.07:20:19.62#ibcon#about to read 6, iclass 32, count 2 2006.196.07:20:19.62#ibcon#read 6, iclass 32, count 2 2006.196.07:20:19.62#ibcon#end of sib2, iclass 32, count 2 2006.196.07:20:19.62#ibcon#*mode == 0, iclass 32, count 2 2006.196.07:20:19.62#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.196.07:20:19.62#ibcon#[27=AT01-04\r\n] 2006.196.07:20:19.62#ibcon#*before write, iclass 32, count 2 2006.196.07:20:19.62#ibcon#enter sib2, iclass 32, count 2 2006.196.07:20:19.62#ibcon#flushed, iclass 32, count 2 2006.196.07:20:19.62#ibcon#about to write, iclass 32, count 2 2006.196.07:20:19.62#ibcon#wrote, iclass 32, count 2 2006.196.07:20:19.62#ibcon#about to read 3, iclass 32, count 2 2006.196.07:20:19.65#ibcon#read 3, iclass 32, count 2 2006.196.07:20:19.65#ibcon#about to read 4, iclass 32, count 2 2006.196.07:20:19.65#ibcon#read 4, iclass 32, count 2 2006.196.07:20:19.65#ibcon#about to read 5, iclass 32, count 2 2006.196.07:20:19.65#ibcon#read 5, iclass 32, count 2 2006.196.07:20:19.65#ibcon#about to read 6, iclass 32, count 2 2006.196.07:20:19.65#ibcon#read 6, iclass 32, count 2 2006.196.07:20:19.65#ibcon#end of sib2, iclass 32, count 2 2006.196.07:20:19.65#ibcon#*after write, iclass 32, count 2 2006.196.07:20:19.65#ibcon#*before return 0, iclass 32, count 2 2006.196.07:20:19.65#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.196.07:20:19.65#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.196.07:20:19.65#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.196.07:20:19.65#ibcon#ireg 7 cls_cnt 0 2006.196.07:20:19.65#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.196.07:20:19.77#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.196.07:20:19.77#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.196.07:20:19.77#ibcon#enter wrdev, iclass 32, count 0 2006.196.07:20:19.77#ibcon#first serial, iclass 32, count 0 2006.196.07:20:19.77#ibcon#enter sib2, iclass 32, count 0 2006.196.07:20:19.77#ibcon#flushed, iclass 32, count 0 2006.196.07:20:19.77#ibcon#about to write, iclass 32, count 0 2006.196.07:20:19.77#ibcon#wrote, iclass 32, count 0 2006.196.07:20:19.77#ibcon#about to read 3, iclass 32, count 0 2006.196.07:20:19.79#ibcon#read 3, iclass 32, count 0 2006.196.07:20:19.79#ibcon#about to read 4, iclass 32, count 0 2006.196.07:20:19.79#ibcon#read 4, iclass 32, count 0 2006.196.07:20:19.79#ibcon#about to read 5, iclass 32, count 0 2006.196.07:20:19.79#ibcon#read 5, iclass 32, count 0 2006.196.07:20:19.79#ibcon#about to read 6, iclass 32, count 0 2006.196.07:20:19.79#ibcon#read 6, iclass 32, count 0 2006.196.07:20:19.79#ibcon#end of sib2, iclass 32, count 0 2006.196.07:20:19.79#ibcon#*mode == 0, iclass 32, count 0 2006.196.07:20:19.79#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.196.07:20:19.79#ibcon#[27=USB\r\n] 2006.196.07:20:19.79#ibcon#*before write, iclass 32, count 0 2006.196.07:20:19.79#ibcon#enter sib2, iclass 32, count 0 2006.196.07:20:19.79#ibcon#flushed, iclass 32, count 0 2006.196.07:20:19.79#ibcon#about to write, iclass 32, count 0 2006.196.07:20:19.79#ibcon#wrote, iclass 32, count 0 2006.196.07:20:19.79#ibcon#about to read 3, iclass 32, count 0 2006.196.07:20:19.82#ibcon#read 3, iclass 32, count 0 2006.196.07:20:19.82#ibcon#about to read 4, iclass 32, count 0 2006.196.07:20:19.82#ibcon#read 4, iclass 32, count 0 2006.196.07:20:19.82#ibcon#about to read 5, iclass 32, count 0 2006.196.07:20:19.82#ibcon#read 5, iclass 32, count 0 2006.196.07:20:19.82#ibcon#about to read 6, iclass 32, count 0 2006.196.07:20:19.82#ibcon#read 6, iclass 32, count 0 2006.196.07:20:19.82#ibcon#end of sib2, iclass 32, count 0 2006.196.07:20:19.82#ibcon#*after write, iclass 32, count 0 2006.196.07:20:19.82#ibcon#*before return 0, iclass 32, count 0 2006.196.07:20:19.82#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.196.07:20:19.82#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.196.07:20:19.82#ibcon#about to clear, iclass 32 cls_cnt 0 2006.196.07:20:19.82#ibcon#cleared, iclass 32 cls_cnt 0 2006.196.07:20:19.82$vc4f8/vblo=2,640.99 2006.196.07:20:19.82#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.196.07:20:19.82#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.196.07:20:19.82#ibcon#ireg 17 cls_cnt 0 2006.196.07:20:19.82#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.196.07:20:19.82#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.196.07:20:19.82#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.196.07:20:19.82#ibcon#enter wrdev, iclass 34, count 0 2006.196.07:20:19.82#ibcon#first serial, iclass 34, count 0 2006.196.07:20:19.82#ibcon#enter sib2, iclass 34, count 0 2006.196.07:20:19.82#ibcon#flushed, iclass 34, count 0 2006.196.07:20:19.82#ibcon#about to write, iclass 34, count 0 2006.196.07:20:19.82#ibcon#wrote, iclass 34, count 0 2006.196.07:20:19.82#ibcon#about to read 3, iclass 34, count 0 2006.196.07:20:19.84#ibcon#read 3, iclass 34, count 0 2006.196.07:20:19.84#ibcon#about to read 4, iclass 34, count 0 2006.196.07:20:19.84#ibcon#read 4, iclass 34, count 0 2006.196.07:20:19.84#ibcon#about to read 5, iclass 34, count 0 2006.196.07:20:19.84#ibcon#read 5, iclass 34, count 0 2006.196.07:20:19.84#ibcon#about to read 6, iclass 34, count 0 2006.196.07:20:19.84#ibcon#read 6, iclass 34, count 0 2006.196.07:20:19.84#ibcon#end of sib2, iclass 34, count 0 2006.196.07:20:19.84#ibcon#*mode == 0, iclass 34, count 0 2006.196.07:20:19.84#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.196.07:20:19.84#ibcon#[28=FRQ=02,640.99\r\n] 2006.196.07:20:19.84#ibcon#*before write, iclass 34, count 0 2006.196.07:20:19.84#ibcon#enter sib2, iclass 34, count 0 2006.196.07:20:19.84#ibcon#flushed, iclass 34, count 0 2006.196.07:20:19.84#ibcon#about to write, iclass 34, count 0 2006.196.07:20:19.84#ibcon#wrote, iclass 34, count 0 2006.196.07:20:19.84#ibcon#about to read 3, iclass 34, count 0 2006.196.07:20:19.88#ibcon#read 3, iclass 34, count 0 2006.196.07:20:19.88#ibcon#about to read 4, iclass 34, count 0 2006.196.07:20:19.88#ibcon#read 4, iclass 34, count 0 2006.196.07:20:19.88#ibcon#about to read 5, iclass 34, count 0 2006.196.07:20:19.88#ibcon#read 5, iclass 34, count 0 2006.196.07:20:19.88#ibcon#about to read 6, iclass 34, count 0 2006.196.07:20:19.88#ibcon#read 6, iclass 34, count 0 2006.196.07:20:19.88#ibcon#end of sib2, iclass 34, count 0 2006.196.07:20:19.88#ibcon#*after write, iclass 34, count 0 2006.196.07:20:19.88#ibcon#*before return 0, iclass 34, count 0 2006.196.07:20:19.88#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.196.07:20:19.88#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.196.07:20:19.88#ibcon#about to clear, iclass 34 cls_cnt 0 2006.196.07:20:19.88#ibcon#cleared, iclass 34 cls_cnt 0 2006.196.07:20:19.88$vc4f8/vb=2,4 2006.196.07:20:19.88#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.196.07:20:19.88#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.196.07:20:19.88#ibcon#ireg 11 cls_cnt 2 2006.196.07:20:19.88#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.196.07:20:19.94#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.196.07:20:19.94#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.196.07:20:19.94#ibcon#enter wrdev, iclass 36, count 2 2006.196.07:20:19.94#ibcon#first serial, iclass 36, count 2 2006.196.07:20:19.94#ibcon#enter sib2, iclass 36, count 2 2006.196.07:20:19.94#ibcon#flushed, iclass 36, count 2 2006.196.07:20:19.94#ibcon#about to write, iclass 36, count 2 2006.196.07:20:19.94#ibcon#wrote, iclass 36, count 2 2006.196.07:20:19.94#ibcon#about to read 3, iclass 36, count 2 2006.196.07:20:19.96#ibcon#read 3, iclass 36, count 2 2006.196.07:20:19.96#ibcon#about to read 4, iclass 36, count 2 2006.196.07:20:19.96#ibcon#read 4, iclass 36, count 2 2006.196.07:20:19.96#ibcon#about to read 5, iclass 36, count 2 2006.196.07:20:19.96#ibcon#read 5, iclass 36, count 2 2006.196.07:20:19.96#ibcon#about to read 6, iclass 36, count 2 2006.196.07:20:19.96#ibcon#read 6, iclass 36, count 2 2006.196.07:20:19.96#ibcon#end of sib2, iclass 36, count 2 2006.196.07:20:19.96#ibcon#*mode == 0, iclass 36, count 2 2006.196.07:20:19.96#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.196.07:20:19.96#ibcon#[27=AT02-04\r\n] 2006.196.07:20:19.96#ibcon#*before write, iclass 36, count 2 2006.196.07:20:19.96#ibcon#enter sib2, iclass 36, count 2 2006.196.07:20:19.96#ibcon#flushed, iclass 36, count 2 2006.196.07:20:19.96#ibcon#about to write, iclass 36, count 2 2006.196.07:20:19.96#ibcon#wrote, iclass 36, count 2 2006.196.07:20:19.96#ibcon#about to read 3, iclass 36, count 2 2006.196.07:20:19.99#ibcon#read 3, iclass 36, count 2 2006.196.07:20:19.99#ibcon#about to read 4, iclass 36, count 2 2006.196.07:20:19.99#ibcon#read 4, iclass 36, count 2 2006.196.07:20:19.99#ibcon#about to read 5, iclass 36, count 2 2006.196.07:20:19.99#ibcon#read 5, iclass 36, count 2 2006.196.07:20:19.99#ibcon#about to read 6, iclass 36, count 2 2006.196.07:20:19.99#ibcon#read 6, iclass 36, count 2 2006.196.07:20:19.99#ibcon#end of sib2, iclass 36, count 2 2006.196.07:20:19.99#ibcon#*after write, iclass 36, count 2 2006.196.07:20:19.99#ibcon#*before return 0, iclass 36, count 2 2006.196.07:20:19.99#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.196.07:20:19.99#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.196.07:20:19.99#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.196.07:20:19.99#ibcon#ireg 7 cls_cnt 0 2006.196.07:20:19.99#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.196.07:20:20.11#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.196.07:20:20.11#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.196.07:20:20.11#ibcon#enter wrdev, iclass 36, count 0 2006.196.07:20:20.11#ibcon#first serial, iclass 36, count 0 2006.196.07:20:20.11#ibcon#enter sib2, iclass 36, count 0 2006.196.07:20:20.11#ibcon#flushed, iclass 36, count 0 2006.196.07:20:20.11#ibcon#about to write, iclass 36, count 0 2006.196.07:20:20.11#ibcon#wrote, iclass 36, count 0 2006.196.07:20:20.11#ibcon#about to read 3, iclass 36, count 0 2006.196.07:20:20.13#ibcon#read 3, iclass 36, count 0 2006.196.07:20:20.13#ibcon#about to read 4, iclass 36, count 0 2006.196.07:20:20.13#ibcon#read 4, iclass 36, count 0 2006.196.07:20:20.13#ibcon#about to read 5, iclass 36, count 0 2006.196.07:20:20.13#ibcon#read 5, iclass 36, count 0 2006.196.07:20:20.13#ibcon#about to read 6, iclass 36, count 0 2006.196.07:20:20.13#ibcon#read 6, iclass 36, count 0 2006.196.07:20:20.13#ibcon#end of sib2, iclass 36, count 0 2006.196.07:20:20.13#ibcon#*mode == 0, iclass 36, count 0 2006.196.07:20:20.13#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.196.07:20:20.13#ibcon#[27=USB\r\n] 2006.196.07:20:20.13#ibcon#*before write, iclass 36, count 0 2006.196.07:20:20.13#ibcon#enter sib2, iclass 36, count 0 2006.196.07:20:20.13#ibcon#flushed, iclass 36, count 0 2006.196.07:20:20.13#ibcon#about to write, iclass 36, count 0 2006.196.07:20:20.13#ibcon#wrote, iclass 36, count 0 2006.196.07:20:20.13#ibcon#about to read 3, iclass 36, count 0 2006.196.07:20:20.16#ibcon#read 3, iclass 36, count 0 2006.196.07:20:20.16#ibcon#about to read 4, iclass 36, count 0 2006.196.07:20:20.16#ibcon#read 4, iclass 36, count 0 2006.196.07:20:20.16#ibcon#about to read 5, iclass 36, count 0 2006.196.07:20:20.16#ibcon#read 5, iclass 36, count 0 2006.196.07:20:20.16#ibcon#about to read 6, iclass 36, count 0 2006.196.07:20:20.16#ibcon#read 6, iclass 36, count 0 2006.196.07:20:20.16#ibcon#end of sib2, iclass 36, count 0 2006.196.07:20:20.16#ibcon#*after write, iclass 36, count 0 2006.196.07:20:20.16#ibcon#*before return 0, iclass 36, count 0 2006.196.07:20:20.16#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.196.07:20:20.16#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.196.07:20:20.16#ibcon#about to clear, iclass 36 cls_cnt 0 2006.196.07:20:20.16#ibcon#cleared, iclass 36 cls_cnt 0 2006.196.07:20:20.16$vc4f8/vblo=3,656.99 2006.196.07:20:20.16#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.196.07:20:20.16#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.196.07:20:20.16#ibcon#ireg 17 cls_cnt 0 2006.196.07:20:20.16#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.196.07:20:20.16#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.196.07:20:20.16#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.196.07:20:20.16#ibcon#enter wrdev, iclass 38, count 0 2006.196.07:20:20.16#ibcon#first serial, iclass 38, count 0 2006.196.07:20:20.16#ibcon#enter sib2, iclass 38, count 0 2006.196.07:20:20.16#ibcon#flushed, iclass 38, count 0 2006.196.07:20:20.16#ibcon#about to write, iclass 38, count 0 2006.196.07:20:20.16#ibcon#wrote, iclass 38, count 0 2006.196.07:20:20.16#ibcon#about to read 3, iclass 38, count 0 2006.196.07:20:20.18#ibcon#read 3, iclass 38, count 0 2006.196.07:20:20.18#ibcon#about to read 4, iclass 38, count 0 2006.196.07:20:20.18#ibcon#read 4, iclass 38, count 0 2006.196.07:20:20.18#ibcon#about to read 5, iclass 38, count 0 2006.196.07:20:20.18#ibcon#read 5, iclass 38, count 0 2006.196.07:20:20.18#ibcon#about to read 6, iclass 38, count 0 2006.196.07:20:20.18#ibcon#read 6, iclass 38, count 0 2006.196.07:20:20.18#ibcon#end of sib2, iclass 38, count 0 2006.196.07:20:20.18#ibcon#*mode == 0, iclass 38, count 0 2006.196.07:20:20.18#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.196.07:20:20.18#ibcon#[28=FRQ=03,656.99\r\n] 2006.196.07:20:20.18#ibcon#*before write, iclass 38, count 0 2006.196.07:20:20.18#ibcon#enter sib2, iclass 38, count 0 2006.196.07:20:20.18#ibcon#flushed, iclass 38, count 0 2006.196.07:20:20.18#ibcon#about to write, iclass 38, count 0 2006.196.07:20:20.18#ibcon#wrote, iclass 38, count 0 2006.196.07:20:20.18#ibcon#about to read 3, iclass 38, count 0 2006.196.07:20:20.22#ibcon#read 3, iclass 38, count 0 2006.196.07:20:20.22#ibcon#about to read 4, iclass 38, count 0 2006.196.07:20:20.22#ibcon#read 4, iclass 38, count 0 2006.196.07:20:20.22#ibcon#about to read 5, iclass 38, count 0 2006.196.07:20:20.22#ibcon#read 5, iclass 38, count 0 2006.196.07:20:20.22#ibcon#about to read 6, iclass 38, count 0 2006.196.07:20:20.22#ibcon#read 6, iclass 38, count 0 2006.196.07:20:20.22#ibcon#end of sib2, iclass 38, count 0 2006.196.07:20:20.22#ibcon#*after write, iclass 38, count 0 2006.196.07:20:20.22#ibcon#*before return 0, iclass 38, count 0 2006.196.07:20:20.22#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.196.07:20:20.22#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.196.07:20:20.22#ibcon#about to clear, iclass 38 cls_cnt 0 2006.196.07:20:20.22#ibcon#cleared, iclass 38 cls_cnt 0 2006.196.07:20:20.22$vc4f8/vb=3,4 2006.196.07:20:20.22#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.196.07:20:20.22#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.196.07:20:20.22#ibcon#ireg 11 cls_cnt 2 2006.196.07:20:20.22#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.196.07:20:20.28#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.196.07:20:20.28#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.196.07:20:20.28#ibcon#enter wrdev, iclass 40, count 2 2006.196.07:20:20.28#ibcon#first serial, iclass 40, count 2 2006.196.07:20:20.28#ibcon#enter sib2, iclass 40, count 2 2006.196.07:20:20.28#ibcon#flushed, iclass 40, count 2 2006.196.07:20:20.28#ibcon#about to write, iclass 40, count 2 2006.196.07:20:20.28#ibcon#wrote, iclass 40, count 2 2006.196.07:20:20.28#ibcon#about to read 3, iclass 40, count 2 2006.196.07:20:20.30#ibcon#read 3, iclass 40, count 2 2006.196.07:20:20.30#ibcon#about to read 4, iclass 40, count 2 2006.196.07:20:20.30#ibcon#read 4, iclass 40, count 2 2006.196.07:20:20.30#ibcon#about to read 5, iclass 40, count 2 2006.196.07:20:20.30#ibcon#read 5, iclass 40, count 2 2006.196.07:20:20.30#ibcon#about to read 6, iclass 40, count 2 2006.196.07:20:20.30#ibcon#read 6, iclass 40, count 2 2006.196.07:20:20.30#ibcon#end of sib2, iclass 40, count 2 2006.196.07:20:20.30#ibcon#*mode == 0, iclass 40, count 2 2006.196.07:20:20.30#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.196.07:20:20.30#ibcon#[27=AT03-04\r\n] 2006.196.07:20:20.30#ibcon#*before write, iclass 40, count 2 2006.196.07:20:20.30#ibcon#enter sib2, iclass 40, count 2 2006.196.07:20:20.30#ibcon#flushed, iclass 40, count 2 2006.196.07:20:20.30#ibcon#about to write, iclass 40, count 2 2006.196.07:20:20.30#ibcon#wrote, iclass 40, count 2 2006.196.07:20:20.30#ibcon#about to read 3, iclass 40, count 2 2006.196.07:20:20.33#ibcon#read 3, iclass 40, count 2 2006.196.07:20:20.33#ibcon#about to read 4, iclass 40, count 2 2006.196.07:20:20.33#ibcon#read 4, iclass 40, count 2 2006.196.07:20:20.33#ibcon#about to read 5, iclass 40, count 2 2006.196.07:20:20.33#ibcon#read 5, iclass 40, count 2 2006.196.07:20:20.33#ibcon#about to read 6, iclass 40, count 2 2006.196.07:20:20.33#ibcon#read 6, iclass 40, count 2 2006.196.07:20:20.33#ibcon#end of sib2, iclass 40, count 2 2006.196.07:20:20.33#ibcon#*after write, iclass 40, count 2 2006.196.07:20:20.33#ibcon#*before return 0, iclass 40, count 2 2006.196.07:20:20.33#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.196.07:20:20.33#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.196.07:20:20.33#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.196.07:20:20.33#ibcon#ireg 7 cls_cnt 0 2006.196.07:20:20.33#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.196.07:20:20.45#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.196.07:20:20.45#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.196.07:20:20.45#ibcon#enter wrdev, iclass 40, count 0 2006.196.07:20:20.45#ibcon#first serial, iclass 40, count 0 2006.196.07:20:20.45#ibcon#enter sib2, iclass 40, count 0 2006.196.07:20:20.45#ibcon#flushed, iclass 40, count 0 2006.196.07:20:20.45#ibcon#about to write, iclass 40, count 0 2006.196.07:20:20.45#ibcon#wrote, iclass 40, count 0 2006.196.07:20:20.45#ibcon#about to read 3, iclass 40, count 0 2006.196.07:20:20.47#ibcon#read 3, iclass 40, count 0 2006.196.07:20:20.47#ibcon#about to read 4, iclass 40, count 0 2006.196.07:20:20.47#ibcon#read 4, iclass 40, count 0 2006.196.07:20:20.47#ibcon#about to read 5, iclass 40, count 0 2006.196.07:20:20.47#ibcon#read 5, iclass 40, count 0 2006.196.07:20:20.47#ibcon#about to read 6, iclass 40, count 0 2006.196.07:20:20.47#ibcon#read 6, iclass 40, count 0 2006.196.07:20:20.47#ibcon#end of sib2, iclass 40, count 0 2006.196.07:20:20.47#ibcon#*mode == 0, iclass 40, count 0 2006.196.07:20:20.47#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.196.07:20:20.47#ibcon#[27=USB\r\n] 2006.196.07:20:20.47#ibcon#*before write, iclass 40, count 0 2006.196.07:20:20.47#ibcon#enter sib2, iclass 40, count 0 2006.196.07:20:20.47#ibcon#flushed, iclass 40, count 0 2006.196.07:20:20.47#ibcon#about to write, iclass 40, count 0 2006.196.07:20:20.47#ibcon#wrote, iclass 40, count 0 2006.196.07:20:20.47#ibcon#about to read 3, iclass 40, count 0 2006.196.07:20:20.50#ibcon#read 3, iclass 40, count 0 2006.196.07:20:20.50#ibcon#about to read 4, iclass 40, count 0 2006.196.07:20:20.50#ibcon#read 4, iclass 40, count 0 2006.196.07:20:20.50#ibcon#about to read 5, iclass 40, count 0 2006.196.07:20:20.50#ibcon#read 5, iclass 40, count 0 2006.196.07:20:20.50#ibcon#about to read 6, iclass 40, count 0 2006.196.07:20:20.50#ibcon#read 6, iclass 40, count 0 2006.196.07:20:20.50#ibcon#end of sib2, iclass 40, count 0 2006.196.07:20:20.50#ibcon#*after write, iclass 40, count 0 2006.196.07:20:20.50#ibcon#*before return 0, iclass 40, count 0 2006.196.07:20:20.50#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.196.07:20:20.50#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.196.07:20:20.50#ibcon#about to clear, iclass 40 cls_cnt 0 2006.196.07:20:20.50#ibcon#cleared, iclass 40 cls_cnt 0 2006.196.07:20:20.50$vc4f8/vblo=4,712.99 2006.196.07:20:20.50#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.196.07:20:20.50#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.196.07:20:20.50#ibcon#ireg 17 cls_cnt 0 2006.196.07:20:20.50#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.196.07:20:20.50#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.196.07:20:20.50#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.196.07:20:20.50#ibcon#enter wrdev, iclass 4, count 0 2006.196.07:20:20.50#ibcon#first serial, iclass 4, count 0 2006.196.07:20:20.50#ibcon#enter sib2, iclass 4, count 0 2006.196.07:20:20.50#ibcon#flushed, iclass 4, count 0 2006.196.07:20:20.50#ibcon#about to write, iclass 4, count 0 2006.196.07:20:20.50#ibcon#wrote, iclass 4, count 0 2006.196.07:20:20.50#ibcon#about to read 3, iclass 4, count 0 2006.196.07:20:20.52#ibcon#read 3, iclass 4, count 0 2006.196.07:20:20.52#ibcon#about to read 4, iclass 4, count 0 2006.196.07:20:20.52#ibcon#read 4, iclass 4, count 0 2006.196.07:20:20.52#ibcon#about to read 5, iclass 4, count 0 2006.196.07:20:20.52#ibcon#read 5, iclass 4, count 0 2006.196.07:20:20.52#ibcon#about to read 6, iclass 4, count 0 2006.196.07:20:20.52#ibcon#read 6, iclass 4, count 0 2006.196.07:20:20.52#ibcon#end of sib2, iclass 4, count 0 2006.196.07:20:20.52#ibcon#*mode == 0, iclass 4, count 0 2006.196.07:20:20.52#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.196.07:20:20.52#ibcon#[28=FRQ=04,712.99\r\n] 2006.196.07:20:20.52#ibcon#*before write, iclass 4, count 0 2006.196.07:20:20.52#ibcon#enter sib2, iclass 4, count 0 2006.196.07:20:20.52#ibcon#flushed, iclass 4, count 0 2006.196.07:20:20.52#ibcon#about to write, iclass 4, count 0 2006.196.07:20:20.52#ibcon#wrote, iclass 4, count 0 2006.196.07:20:20.52#ibcon#about to read 3, iclass 4, count 0 2006.196.07:20:20.56#ibcon#read 3, iclass 4, count 0 2006.196.07:20:20.56#ibcon#about to read 4, iclass 4, count 0 2006.196.07:20:20.56#ibcon#read 4, iclass 4, count 0 2006.196.07:20:20.56#ibcon#about to read 5, iclass 4, count 0 2006.196.07:20:20.56#ibcon#read 5, iclass 4, count 0 2006.196.07:20:20.56#ibcon#about to read 6, iclass 4, count 0 2006.196.07:20:20.56#ibcon#read 6, iclass 4, count 0 2006.196.07:20:20.56#ibcon#end of sib2, iclass 4, count 0 2006.196.07:20:20.56#ibcon#*after write, iclass 4, count 0 2006.196.07:20:20.56#ibcon#*before return 0, iclass 4, count 0 2006.196.07:20:20.56#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.196.07:20:20.56#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.196.07:20:20.56#ibcon#about to clear, iclass 4 cls_cnt 0 2006.196.07:20:20.56#ibcon#cleared, iclass 4 cls_cnt 0 2006.196.07:20:20.56$vc4f8/vb=4,4 2006.196.07:20:20.56#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.196.07:20:20.56#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.196.07:20:20.56#ibcon#ireg 11 cls_cnt 2 2006.196.07:20:20.56#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.196.07:20:20.62#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.196.07:20:20.62#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.196.07:20:20.62#ibcon#enter wrdev, iclass 6, count 2 2006.196.07:20:20.62#ibcon#first serial, iclass 6, count 2 2006.196.07:20:20.62#ibcon#enter sib2, iclass 6, count 2 2006.196.07:20:20.62#ibcon#flushed, iclass 6, count 2 2006.196.07:20:20.62#ibcon#about to write, iclass 6, count 2 2006.196.07:20:20.62#ibcon#wrote, iclass 6, count 2 2006.196.07:20:20.62#ibcon#about to read 3, iclass 6, count 2 2006.196.07:20:20.64#ibcon#read 3, iclass 6, count 2 2006.196.07:20:20.64#ibcon#about to read 4, iclass 6, count 2 2006.196.07:20:20.64#ibcon#read 4, iclass 6, count 2 2006.196.07:20:20.64#ibcon#about to read 5, iclass 6, count 2 2006.196.07:20:20.64#ibcon#read 5, iclass 6, count 2 2006.196.07:20:20.64#ibcon#about to read 6, iclass 6, count 2 2006.196.07:20:20.64#ibcon#read 6, iclass 6, count 2 2006.196.07:20:20.64#ibcon#end of sib2, iclass 6, count 2 2006.196.07:20:20.64#ibcon#*mode == 0, iclass 6, count 2 2006.196.07:20:20.64#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.196.07:20:20.64#ibcon#[27=AT04-04\r\n] 2006.196.07:20:20.64#ibcon#*before write, iclass 6, count 2 2006.196.07:20:20.64#ibcon#enter sib2, iclass 6, count 2 2006.196.07:20:20.64#ibcon#flushed, iclass 6, count 2 2006.196.07:20:20.64#ibcon#about to write, iclass 6, count 2 2006.196.07:20:20.64#ibcon#wrote, iclass 6, count 2 2006.196.07:20:20.64#ibcon#about to read 3, iclass 6, count 2 2006.196.07:20:20.67#ibcon#read 3, iclass 6, count 2 2006.196.07:20:20.67#ibcon#about to read 4, iclass 6, count 2 2006.196.07:20:20.67#ibcon#read 4, iclass 6, count 2 2006.196.07:20:20.67#ibcon#about to read 5, iclass 6, count 2 2006.196.07:20:20.67#ibcon#read 5, iclass 6, count 2 2006.196.07:20:20.67#ibcon#about to read 6, iclass 6, count 2 2006.196.07:20:20.67#ibcon#read 6, iclass 6, count 2 2006.196.07:20:20.67#ibcon#end of sib2, iclass 6, count 2 2006.196.07:20:20.67#ibcon#*after write, iclass 6, count 2 2006.196.07:20:20.67#ibcon#*before return 0, iclass 6, count 2 2006.196.07:20:20.67#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.196.07:20:20.67#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.196.07:20:20.67#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.196.07:20:20.67#ibcon#ireg 7 cls_cnt 0 2006.196.07:20:20.67#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.196.07:20:20.79#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.196.07:20:20.79#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.196.07:20:20.79#ibcon#enter wrdev, iclass 6, count 0 2006.196.07:20:20.79#ibcon#first serial, iclass 6, count 0 2006.196.07:20:20.79#ibcon#enter sib2, iclass 6, count 0 2006.196.07:20:20.79#ibcon#flushed, iclass 6, count 0 2006.196.07:20:20.79#ibcon#about to write, iclass 6, count 0 2006.196.07:20:20.79#ibcon#wrote, iclass 6, count 0 2006.196.07:20:20.79#ibcon#about to read 3, iclass 6, count 0 2006.196.07:20:20.81#ibcon#read 3, iclass 6, count 0 2006.196.07:20:20.81#ibcon#about to read 4, iclass 6, count 0 2006.196.07:20:20.81#ibcon#read 4, iclass 6, count 0 2006.196.07:20:20.81#ibcon#about to read 5, iclass 6, count 0 2006.196.07:20:20.81#ibcon#read 5, iclass 6, count 0 2006.196.07:20:20.81#ibcon#about to read 6, iclass 6, count 0 2006.196.07:20:20.81#ibcon#read 6, iclass 6, count 0 2006.196.07:20:20.81#ibcon#end of sib2, iclass 6, count 0 2006.196.07:20:20.81#ibcon#*mode == 0, iclass 6, count 0 2006.196.07:20:20.81#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.196.07:20:20.81#ibcon#[27=USB\r\n] 2006.196.07:20:20.81#ibcon#*before write, iclass 6, count 0 2006.196.07:20:20.81#ibcon#enter sib2, iclass 6, count 0 2006.196.07:20:20.81#ibcon#flushed, iclass 6, count 0 2006.196.07:20:20.81#ibcon#about to write, iclass 6, count 0 2006.196.07:20:20.81#ibcon#wrote, iclass 6, count 0 2006.196.07:20:20.81#ibcon#about to read 3, iclass 6, count 0 2006.196.07:20:20.84#ibcon#read 3, iclass 6, count 0 2006.196.07:20:20.84#ibcon#about to read 4, iclass 6, count 0 2006.196.07:20:20.84#ibcon#read 4, iclass 6, count 0 2006.196.07:20:20.84#ibcon#about to read 5, iclass 6, count 0 2006.196.07:20:20.84#ibcon#read 5, iclass 6, count 0 2006.196.07:20:20.84#ibcon#about to read 6, iclass 6, count 0 2006.196.07:20:20.84#ibcon#read 6, iclass 6, count 0 2006.196.07:20:20.84#ibcon#end of sib2, iclass 6, count 0 2006.196.07:20:20.84#ibcon#*after write, iclass 6, count 0 2006.196.07:20:20.84#ibcon#*before return 0, iclass 6, count 0 2006.196.07:20:20.84#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.196.07:20:20.84#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.196.07:20:20.84#ibcon#about to clear, iclass 6 cls_cnt 0 2006.196.07:20:20.84#ibcon#cleared, iclass 6 cls_cnt 0 2006.196.07:20:20.84$vc4f8/vblo=5,744.99 2006.196.07:20:20.84#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.196.07:20:20.84#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.196.07:20:20.84#ibcon#ireg 17 cls_cnt 0 2006.196.07:20:20.84#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.196.07:20:20.84#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.196.07:20:20.84#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.196.07:20:20.84#ibcon#enter wrdev, iclass 10, count 0 2006.196.07:20:20.84#ibcon#first serial, iclass 10, count 0 2006.196.07:20:20.84#ibcon#enter sib2, iclass 10, count 0 2006.196.07:20:20.84#ibcon#flushed, iclass 10, count 0 2006.196.07:20:20.84#ibcon#about to write, iclass 10, count 0 2006.196.07:20:20.84#ibcon#wrote, iclass 10, count 0 2006.196.07:20:20.84#ibcon#about to read 3, iclass 10, count 0 2006.196.07:20:20.86#ibcon#read 3, iclass 10, count 0 2006.196.07:20:20.86#ibcon#about to read 4, iclass 10, count 0 2006.196.07:20:20.86#ibcon#read 4, iclass 10, count 0 2006.196.07:20:20.86#ibcon#about to read 5, iclass 10, count 0 2006.196.07:20:20.86#ibcon#read 5, iclass 10, count 0 2006.196.07:20:20.86#ibcon#about to read 6, iclass 10, count 0 2006.196.07:20:20.86#ibcon#read 6, iclass 10, count 0 2006.196.07:20:20.86#ibcon#end of sib2, iclass 10, count 0 2006.196.07:20:20.86#ibcon#*mode == 0, iclass 10, count 0 2006.196.07:20:20.86#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.196.07:20:20.86#ibcon#[28=FRQ=05,744.99\r\n] 2006.196.07:20:20.86#ibcon#*before write, iclass 10, count 0 2006.196.07:20:20.86#ibcon#enter sib2, iclass 10, count 0 2006.196.07:20:20.86#ibcon#flushed, iclass 10, count 0 2006.196.07:20:20.86#ibcon#about to write, iclass 10, count 0 2006.196.07:20:20.86#ibcon#wrote, iclass 10, count 0 2006.196.07:20:20.86#ibcon#about to read 3, iclass 10, count 0 2006.196.07:20:20.90#ibcon#read 3, iclass 10, count 0 2006.196.07:20:20.90#ibcon#about to read 4, iclass 10, count 0 2006.196.07:20:20.90#ibcon#read 4, iclass 10, count 0 2006.196.07:20:20.90#ibcon#about to read 5, iclass 10, count 0 2006.196.07:20:20.90#ibcon#read 5, iclass 10, count 0 2006.196.07:20:20.90#ibcon#about to read 6, iclass 10, count 0 2006.196.07:20:20.90#ibcon#read 6, iclass 10, count 0 2006.196.07:20:20.90#ibcon#end of sib2, iclass 10, count 0 2006.196.07:20:20.90#ibcon#*after write, iclass 10, count 0 2006.196.07:20:20.90#ibcon#*before return 0, iclass 10, count 0 2006.196.07:20:20.90#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.196.07:20:20.90#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.196.07:20:20.90#ibcon#about to clear, iclass 10 cls_cnt 0 2006.196.07:20:20.90#ibcon#cleared, iclass 10 cls_cnt 0 2006.196.07:20:20.90$vc4f8/vb=5,4 2006.196.07:20:20.90#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.196.07:20:20.90#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.196.07:20:20.90#ibcon#ireg 11 cls_cnt 2 2006.196.07:20:20.90#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.196.07:20:20.96#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.196.07:20:20.96#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.196.07:20:20.96#ibcon#enter wrdev, iclass 12, count 2 2006.196.07:20:20.96#ibcon#first serial, iclass 12, count 2 2006.196.07:20:20.96#ibcon#enter sib2, iclass 12, count 2 2006.196.07:20:20.96#ibcon#flushed, iclass 12, count 2 2006.196.07:20:20.96#ibcon#about to write, iclass 12, count 2 2006.196.07:20:20.96#ibcon#wrote, iclass 12, count 2 2006.196.07:20:20.96#ibcon#about to read 3, iclass 12, count 2 2006.196.07:20:20.98#ibcon#read 3, iclass 12, count 2 2006.196.07:20:20.98#ibcon#about to read 4, iclass 12, count 2 2006.196.07:20:20.98#ibcon#read 4, iclass 12, count 2 2006.196.07:20:20.98#ibcon#about to read 5, iclass 12, count 2 2006.196.07:20:20.98#ibcon#read 5, iclass 12, count 2 2006.196.07:20:20.98#ibcon#about to read 6, iclass 12, count 2 2006.196.07:20:20.98#ibcon#read 6, iclass 12, count 2 2006.196.07:20:20.98#ibcon#end of sib2, iclass 12, count 2 2006.196.07:20:20.98#ibcon#*mode == 0, iclass 12, count 2 2006.196.07:20:20.98#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.196.07:20:20.98#ibcon#[27=AT05-04\r\n] 2006.196.07:20:20.98#ibcon#*before write, iclass 12, count 2 2006.196.07:20:20.98#ibcon#enter sib2, iclass 12, count 2 2006.196.07:20:20.98#ibcon#flushed, iclass 12, count 2 2006.196.07:20:20.98#ibcon#about to write, iclass 12, count 2 2006.196.07:20:20.98#ibcon#wrote, iclass 12, count 2 2006.196.07:20:20.98#ibcon#about to read 3, iclass 12, count 2 2006.196.07:20:21.01#ibcon#read 3, iclass 12, count 2 2006.196.07:20:21.01#ibcon#about to read 4, iclass 12, count 2 2006.196.07:20:21.01#ibcon#read 4, iclass 12, count 2 2006.196.07:20:21.01#ibcon#about to read 5, iclass 12, count 2 2006.196.07:20:21.01#ibcon#read 5, iclass 12, count 2 2006.196.07:20:21.01#ibcon#about to read 6, iclass 12, count 2 2006.196.07:20:21.01#ibcon#read 6, iclass 12, count 2 2006.196.07:20:21.01#ibcon#end of sib2, iclass 12, count 2 2006.196.07:20:21.01#ibcon#*after write, iclass 12, count 2 2006.196.07:20:21.01#ibcon#*before return 0, iclass 12, count 2 2006.196.07:20:21.01#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.196.07:20:21.01#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.196.07:20:21.01#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.196.07:20:21.01#ibcon#ireg 7 cls_cnt 0 2006.196.07:20:21.01#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.196.07:20:21.13#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.196.07:20:21.13#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.196.07:20:21.13#ibcon#enter wrdev, iclass 12, count 0 2006.196.07:20:21.13#ibcon#first serial, iclass 12, count 0 2006.196.07:20:21.13#ibcon#enter sib2, iclass 12, count 0 2006.196.07:20:21.13#ibcon#flushed, iclass 12, count 0 2006.196.07:20:21.13#ibcon#about to write, iclass 12, count 0 2006.196.07:20:21.13#ibcon#wrote, iclass 12, count 0 2006.196.07:20:21.13#ibcon#about to read 3, iclass 12, count 0 2006.196.07:20:21.15#ibcon#read 3, iclass 12, count 0 2006.196.07:20:21.15#ibcon#about to read 4, iclass 12, count 0 2006.196.07:20:21.15#ibcon#read 4, iclass 12, count 0 2006.196.07:20:21.15#ibcon#about to read 5, iclass 12, count 0 2006.196.07:20:21.15#ibcon#read 5, iclass 12, count 0 2006.196.07:20:21.15#ibcon#about to read 6, iclass 12, count 0 2006.196.07:20:21.15#ibcon#read 6, iclass 12, count 0 2006.196.07:20:21.15#ibcon#end of sib2, iclass 12, count 0 2006.196.07:20:21.15#ibcon#*mode == 0, iclass 12, count 0 2006.196.07:20:21.15#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.196.07:20:21.15#ibcon#[27=USB\r\n] 2006.196.07:20:21.15#ibcon#*before write, iclass 12, count 0 2006.196.07:20:21.15#ibcon#enter sib2, iclass 12, count 0 2006.196.07:20:21.15#ibcon#flushed, iclass 12, count 0 2006.196.07:20:21.15#ibcon#about to write, iclass 12, count 0 2006.196.07:20:21.15#ibcon#wrote, iclass 12, count 0 2006.196.07:20:21.15#ibcon#about to read 3, iclass 12, count 0 2006.196.07:20:21.18#ibcon#read 3, iclass 12, count 0 2006.196.07:20:21.18#ibcon#about to read 4, iclass 12, count 0 2006.196.07:20:21.18#ibcon#read 4, iclass 12, count 0 2006.196.07:20:21.18#ibcon#about to read 5, iclass 12, count 0 2006.196.07:20:21.18#ibcon#read 5, iclass 12, count 0 2006.196.07:20:21.18#ibcon#about to read 6, iclass 12, count 0 2006.196.07:20:21.18#ibcon#read 6, iclass 12, count 0 2006.196.07:20:21.18#ibcon#end of sib2, iclass 12, count 0 2006.196.07:20:21.18#ibcon#*after write, iclass 12, count 0 2006.196.07:20:21.18#ibcon#*before return 0, iclass 12, count 0 2006.196.07:20:21.18#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.196.07:20:21.18#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.196.07:20:21.18#ibcon#about to clear, iclass 12 cls_cnt 0 2006.196.07:20:21.18#ibcon#cleared, iclass 12 cls_cnt 0 2006.196.07:20:21.18$vc4f8/vblo=6,752.99 2006.196.07:20:21.18#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.196.07:20:21.18#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.196.07:20:21.18#ibcon#ireg 17 cls_cnt 0 2006.196.07:20:21.18#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.196.07:20:21.18#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.196.07:20:21.18#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.196.07:20:21.18#ibcon#enter wrdev, iclass 14, count 0 2006.196.07:20:21.18#ibcon#first serial, iclass 14, count 0 2006.196.07:20:21.18#ibcon#enter sib2, iclass 14, count 0 2006.196.07:20:21.18#ibcon#flushed, iclass 14, count 0 2006.196.07:20:21.18#ibcon#about to write, iclass 14, count 0 2006.196.07:20:21.18#ibcon#wrote, iclass 14, count 0 2006.196.07:20:21.18#ibcon#about to read 3, iclass 14, count 0 2006.196.07:20:21.20#ibcon#read 3, iclass 14, count 0 2006.196.07:20:21.20#ibcon#about to read 4, iclass 14, count 0 2006.196.07:20:21.20#ibcon#read 4, iclass 14, count 0 2006.196.07:20:21.20#ibcon#about to read 5, iclass 14, count 0 2006.196.07:20:21.20#ibcon#read 5, iclass 14, count 0 2006.196.07:20:21.20#ibcon#about to read 6, iclass 14, count 0 2006.196.07:20:21.20#ibcon#read 6, iclass 14, count 0 2006.196.07:20:21.20#ibcon#end of sib2, iclass 14, count 0 2006.196.07:20:21.20#ibcon#*mode == 0, iclass 14, count 0 2006.196.07:20:21.20#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.196.07:20:21.20#ibcon#[28=FRQ=06,752.99\r\n] 2006.196.07:20:21.20#ibcon#*before write, iclass 14, count 0 2006.196.07:20:21.20#ibcon#enter sib2, iclass 14, count 0 2006.196.07:20:21.20#ibcon#flushed, iclass 14, count 0 2006.196.07:20:21.20#ibcon#about to write, iclass 14, count 0 2006.196.07:20:21.20#ibcon#wrote, iclass 14, count 0 2006.196.07:20:21.20#ibcon#about to read 3, iclass 14, count 0 2006.196.07:20:21.24#ibcon#read 3, iclass 14, count 0 2006.196.07:20:21.24#ibcon#about to read 4, iclass 14, count 0 2006.196.07:20:21.24#ibcon#read 4, iclass 14, count 0 2006.196.07:20:21.24#ibcon#about to read 5, iclass 14, count 0 2006.196.07:20:21.24#ibcon#read 5, iclass 14, count 0 2006.196.07:20:21.24#ibcon#about to read 6, iclass 14, count 0 2006.196.07:20:21.24#ibcon#read 6, iclass 14, count 0 2006.196.07:20:21.24#ibcon#end of sib2, iclass 14, count 0 2006.196.07:20:21.24#ibcon#*after write, iclass 14, count 0 2006.196.07:20:21.24#ibcon#*before return 0, iclass 14, count 0 2006.196.07:20:21.24#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.196.07:20:21.24#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.196.07:20:21.24#ibcon#about to clear, iclass 14 cls_cnt 0 2006.196.07:20:21.24#ibcon#cleared, iclass 14 cls_cnt 0 2006.196.07:20:21.24$vc4f8/vb=6,4 2006.196.07:20:21.24#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.196.07:20:21.24#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.196.07:20:21.24#ibcon#ireg 11 cls_cnt 2 2006.196.07:20:21.24#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.196.07:20:21.30#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.196.07:20:21.30#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.196.07:20:21.30#ibcon#enter wrdev, iclass 16, count 2 2006.196.07:20:21.30#ibcon#first serial, iclass 16, count 2 2006.196.07:20:21.30#ibcon#enter sib2, iclass 16, count 2 2006.196.07:20:21.30#ibcon#flushed, iclass 16, count 2 2006.196.07:20:21.30#ibcon#about to write, iclass 16, count 2 2006.196.07:20:21.30#ibcon#wrote, iclass 16, count 2 2006.196.07:20:21.30#ibcon#about to read 3, iclass 16, count 2 2006.196.07:20:21.32#ibcon#read 3, iclass 16, count 2 2006.196.07:20:21.32#ibcon#about to read 4, iclass 16, count 2 2006.196.07:20:21.32#ibcon#read 4, iclass 16, count 2 2006.196.07:20:21.32#ibcon#about to read 5, iclass 16, count 2 2006.196.07:20:21.32#ibcon#read 5, iclass 16, count 2 2006.196.07:20:21.32#ibcon#about to read 6, iclass 16, count 2 2006.196.07:20:21.32#ibcon#read 6, iclass 16, count 2 2006.196.07:20:21.32#ibcon#end of sib2, iclass 16, count 2 2006.196.07:20:21.32#ibcon#*mode == 0, iclass 16, count 2 2006.196.07:20:21.32#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.196.07:20:21.32#ibcon#[27=AT06-04\r\n] 2006.196.07:20:21.32#ibcon#*before write, iclass 16, count 2 2006.196.07:20:21.32#ibcon#enter sib2, iclass 16, count 2 2006.196.07:20:21.32#ibcon#flushed, iclass 16, count 2 2006.196.07:20:21.32#ibcon#about to write, iclass 16, count 2 2006.196.07:20:21.32#ibcon#wrote, iclass 16, count 2 2006.196.07:20:21.32#ibcon#about to read 3, iclass 16, count 2 2006.196.07:20:21.35#ibcon#read 3, iclass 16, count 2 2006.196.07:20:21.35#ibcon#about to read 4, iclass 16, count 2 2006.196.07:20:21.35#ibcon#read 4, iclass 16, count 2 2006.196.07:20:21.35#ibcon#about to read 5, iclass 16, count 2 2006.196.07:20:21.35#ibcon#read 5, iclass 16, count 2 2006.196.07:20:21.35#ibcon#about to read 6, iclass 16, count 2 2006.196.07:20:21.35#ibcon#read 6, iclass 16, count 2 2006.196.07:20:21.35#ibcon#end of sib2, iclass 16, count 2 2006.196.07:20:21.35#ibcon#*after write, iclass 16, count 2 2006.196.07:20:21.35#ibcon#*before return 0, iclass 16, count 2 2006.196.07:20:21.35#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.196.07:20:21.35#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.196.07:20:21.35#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.196.07:20:21.35#ibcon#ireg 7 cls_cnt 0 2006.196.07:20:21.35#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.196.07:20:21.47#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.196.07:20:21.47#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.196.07:20:21.47#ibcon#enter wrdev, iclass 16, count 0 2006.196.07:20:21.47#ibcon#first serial, iclass 16, count 0 2006.196.07:20:21.47#ibcon#enter sib2, iclass 16, count 0 2006.196.07:20:21.47#ibcon#flushed, iclass 16, count 0 2006.196.07:20:21.47#ibcon#about to write, iclass 16, count 0 2006.196.07:20:21.47#ibcon#wrote, iclass 16, count 0 2006.196.07:20:21.47#ibcon#about to read 3, iclass 16, count 0 2006.196.07:20:21.49#ibcon#read 3, iclass 16, count 0 2006.196.07:20:21.49#ibcon#about to read 4, iclass 16, count 0 2006.196.07:20:21.49#ibcon#read 4, iclass 16, count 0 2006.196.07:20:21.49#ibcon#about to read 5, iclass 16, count 0 2006.196.07:20:21.49#ibcon#read 5, iclass 16, count 0 2006.196.07:20:21.49#ibcon#about to read 6, iclass 16, count 0 2006.196.07:20:21.49#ibcon#read 6, iclass 16, count 0 2006.196.07:20:21.49#ibcon#end of sib2, iclass 16, count 0 2006.196.07:20:21.49#ibcon#*mode == 0, iclass 16, count 0 2006.196.07:20:21.49#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.196.07:20:21.49#ibcon#[27=USB\r\n] 2006.196.07:20:21.49#ibcon#*before write, iclass 16, count 0 2006.196.07:20:21.49#ibcon#enter sib2, iclass 16, count 0 2006.196.07:20:21.49#ibcon#flushed, iclass 16, count 0 2006.196.07:20:21.49#ibcon#about to write, iclass 16, count 0 2006.196.07:20:21.49#ibcon#wrote, iclass 16, count 0 2006.196.07:20:21.49#ibcon#about to read 3, iclass 16, count 0 2006.196.07:20:21.52#ibcon#read 3, iclass 16, count 0 2006.196.07:20:21.52#ibcon#about to read 4, iclass 16, count 0 2006.196.07:20:21.52#ibcon#read 4, iclass 16, count 0 2006.196.07:20:21.52#ibcon#about to read 5, iclass 16, count 0 2006.196.07:20:21.52#ibcon#read 5, iclass 16, count 0 2006.196.07:20:21.52#ibcon#about to read 6, iclass 16, count 0 2006.196.07:20:21.52#ibcon#read 6, iclass 16, count 0 2006.196.07:20:21.52#ibcon#end of sib2, iclass 16, count 0 2006.196.07:20:21.52#ibcon#*after write, iclass 16, count 0 2006.196.07:20:21.52#ibcon#*before return 0, iclass 16, count 0 2006.196.07:20:21.52#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.196.07:20:21.52#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.196.07:20:21.52#ibcon#about to clear, iclass 16 cls_cnt 0 2006.196.07:20:21.52#ibcon#cleared, iclass 16 cls_cnt 0 2006.196.07:20:21.52$vc4f8/vabw=wide 2006.196.07:20:21.52#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.196.07:20:21.52#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.196.07:20:21.52#ibcon#ireg 8 cls_cnt 0 2006.196.07:20:21.52#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.196.07:20:21.52#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.196.07:20:21.52#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.196.07:20:21.52#ibcon#enter wrdev, iclass 18, count 0 2006.196.07:20:21.52#ibcon#first serial, iclass 18, count 0 2006.196.07:20:21.52#ibcon#enter sib2, iclass 18, count 0 2006.196.07:20:21.52#ibcon#flushed, iclass 18, count 0 2006.196.07:20:21.52#ibcon#about to write, iclass 18, count 0 2006.196.07:20:21.52#ibcon#wrote, iclass 18, count 0 2006.196.07:20:21.52#ibcon#about to read 3, iclass 18, count 0 2006.196.07:20:21.54#ibcon#read 3, iclass 18, count 0 2006.196.07:20:21.54#ibcon#about to read 4, iclass 18, count 0 2006.196.07:20:21.54#ibcon#read 4, iclass 18, count 0 2006.196.07:20:21.54#ibcon#about to read 5, iclass 18, count 0 2006.196.07:20:21.54#ibcon#read 5, iclass 18, count 0 2006.196.07:20:21.54#ibcon#about to read 6, iclass 18, count 0 2006.196.07:20:21.54#ibcon#read 6, iclass 18, count 0 2006.196.07:20:21.54#ibcon#end of sib2, iclass 18, count 0 2006.196.07:20:21.54#ibcon#*mode == 0, iclass 18, count 0 2006.196.07:20:21.54#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.196.07:20:21.54#ibcon#[25=BW32\r\n] 2006.196.07:20:21.54#ibcon#*before write, iclass 18, count 0 2006.196.07:20:21.54#ibcon#enter sib2, iclass 18, count 0 2006.196.07:20:21.54#ibcon#flushed, iclass 18, count 0 2006.196.07:20:21.54#ibcon#about to write, iclass 18, count 0 2006.196.07:20:21.54#ibcon#wrote, iclass 18, count 0 2006.196.07:20:21.54#ibcon#about to read 3, iclass 18, count 0 2006.196.07:20:21.57#ibcon#read 3, iclass 18, count 0 2006.196.07:20:21.57#ibcon#about to read 4, iclass 18, count 0 2006.196.07:20:21.57#ibcon#read 4, iclass 18, count 0 2006.196.07:20:21.57#ibcon#about to read 5, iclass 18, count 0 2006.196.07:20:21.57#ibcon#read 5, iclass 18, count 0 2006.196.07:20:21.57#ibcon#about to read 6, iclass 18, count 0 2006.196.07:20:21.57#ibcon#read 6, iclass 18, count 0 2006.196.07:20:21.57#ibcon#end of sib2, iclass 18, count 0 2006.196.07:20:21.57#ibcon#*after write, iclass 18, count 0 2006.196.07:20:21.57#ibcon#*before return 0, iclass 18, count 0 2006.196.07:20:21.57#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.196.07:20:21.57#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.196.07:20:21.57#ibcon#about to clear, iclass 18 cls_cnt 0 2006.196.07:20:21.57#ibcon#cleared, iclass 18 cls_cnt 0 2006.196.07:20:21.57$vc4f8/vbbw=wide 2006.196.07:20:21.57#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.196.07:20:21.57#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.196.07:20:21.57#ibcon#ireg 8 cls_cnt 0 2006.196.07:20:21.57#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.196.07:20:21.64#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.196.07:20:21.64#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.196.07:20:21.64#ibcon#enter wrdev, iclass 20, count 0 2006.196.07:20:21.64#ibcon#first serial, iclass 20, count 0 2006.196.07:20:21.64#ibcon#enter sib2, iclass 20, count 0 2006.196.07:20:21.64#ibcon#flushed, iclass 20, count 0 2006.196.07:20:21.64#ibcon#about to write, iclass 20, count 0 2006.196.07:20:21.64#ibcon#wrote, iclass 20, count 0 2006.196.07:20:21.64#ibcon#about to read 3, iclass 20, count 0 2006.196.07:20:21.66#ibcon#read 3, iclass 20, count 0 2006.196.07:20:21.66#ibcon#about to read 4, iclass 20, count 0 2006.196.07:20:21.66#ibcon#read 4, iclass 20, count 0 2006.196.07:20:21.66#ibcon#about to read 5, iclass 20, count 0 2006.196.07:20:21.66#ibcon#read 5, iclass 20, count 0 2006.196.07:20:21.66#ibcon#about to read 6, iclass 20, count 0 2006.196.07:20:21.66#ibcon#read 6, iclass 20, count 0 2006.196.07:20:21.66#ibcon#end of sib2, iclass 20, count 0 2006.196.07:20:21.66#ibcon#*mode == 0, iclass 20, count 0 2006.196.07:20:21.66#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.196.07:20:21.66#ibcon#[27=BW32\r\n] 2006.196.07:20:21.66#ibcon#*before write, iclass 20, count 0 2006.196.07:20:21.66#ibcon#enter sib2, iclass 20, count 0 2006.196.07:20:21.66#ibcon#flushed, iclass 20, count 0 2006.196.07:20:21.66#ibcon#about to write, iclass 20, count 0 2006.196.07:20:21.66#ibcon#wrote, iclass 20, count 0 2006.196.07:20:21.66#ibcon#about to read 3, iclass 20, count 0 2006.196.07:20:21.69#ibcon#read 3, iclass 20, count 0 2006.196.07:20:21.69#ibcon#about to read 4, iclass 20, count 0 2006.196.07:20:21.69#ibcon#read 4, iclass 20, count 0 2006.196.07:20:21.69#ibcon#about to read 5, iclass 20, count 0 2006.196.07:20:21.69#ibcon#read 5, iclass 20, count 0 2006.196.07:20:21.69#ibcon#about to read 6, iclass 20, count 0 2006.196.07:20:21.69#ibcon#read 6, iclass 20, count 0 2006.196.07:20:21.69#ibcon#end of sib2, iclass 20, count 0 2006.196.07:20:21.69#ibcon#*after write, iclass 20, count 0 2006.196.07:20:21.69#ibcon#*before return 0, iclass 20, count 0 2006.196.07:20:21.69#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.196.07:20:21.69#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.196.07:20:21.69#ibcon#about to clear, iclass 20 cls_cnt 0 2006.196.07:20:21.69#ibcon#cleared, iclass 20 cls_cnt 0 2006.196.07:20:21.69$4f8m12a/ifd4f 2006.196.07:20:21.69&ifd4f/lo= 2006.196.07:20:21.69&ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.196.07:20:21.69&ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.196.07:20:21.69&ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.196.07:20:21.69&ifd4f/patch= 2006.196.07:20:21.69&ifd4f/patch=lo1,a1,a2,a3,a4 2006.196.07:20:21.69&ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.196.07:20:21.69&ifd4f/patch=lo3,a5,a6,a7,a8 2006.196.07:20:21.69$ifd4f/lo= 2006.196.07:20:21.69$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.196.07:20:21.69$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.196.07:20:21.69$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.196.07:20:21.69$ifd4f/patch= 2006.196.07:20:21.69$ifd4f/patch=lo1,a1,a2,a3,a4 2006.196.07:20:21.69$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.196.07:20:21.69$ifd4f/patch=lo3,a5,a6,a7,a8 2006.196.07:20:21.69$4f8m12a/"form=m,16.000,1:2 2006.196.07:20:21.69$4f8m12a/"tpicd 2006.196.07:20:21.69$4f8m12a/echo=off 2006.196.07:20:21.69$4f8m12a/xlog=off 2006.196.07:20:21.69:!2006.196.07:29:50 2006.196.07:20:44.14#trakl#Source acquired 2006.196.07:20:44.14#flagr#flagr/antenna,acquired 2006.196.07:24:55.13#trakl#Off source 2006.196.07:24:55.13?ERROR st -7 Antenna off-source! 2006.196.07:24:55.13#trakl#az 31.102 el 9.712 azerr*cos(el) 0.0210 elerr -0.0004 2006.196.07:24:56.13#flagr#flagr/antenna,off-source 2006.196.07:25:01.13#trakl#Source re-acquired 2006.196.07:25:02.13#flagr#flagr/antenna,re-acquired 2006.196.07:29:50.00:preob 2006.196.07:29:50.00&preob/onsource 2006.196.07:29:51.14/onsource/TRACKING 2006.196.07:29:51.14:!2006.196.07:30:00 2006.196.07:30:00.00:data_valid=on 2006.196.07:30:00.00:midob 2006.196.07:30:00.00&midob/onsource 2006.196.07:30:00.00&midob/wx 2006.196.07:30:00.00&midob/cable 2006.196.07:30:00.00&midob/va 2006.196.07:30:00.00&midob/valo 2006.196.07:30:00.00&midob/vb 2006.196.07:30:00.00&midob/vblo 2006.196.07:30:00.00&midob/vabw 2006.196.07:30:00.00&midob/vbbw 2006.196.07:30:00.00&midob/"form 2006.196.07:30:00.00&midob/xfe 2006.196.07:30:00.00&midob/ifatt 2006.196.07:30:00.00&midob/clockoff 2006.196.07:30:00.00&midob/sy=logmail 2006.196.07:30:00.00&midob/"sy=run setcl adapt & 2006.196.07:30:00.14/onsource/TRACKING 2006.196.07:30:00.14/wx/30.35,1004.2,86 2006.196.07:30:00.35/cable/+6.3313E-03 2006.196.07:30:01.44/va/01,08,usb,yes,35,37 2006.196.07:30:01.44/va/02,07,usb,yes,35,37 2006.196.07:30:01.44/va/03,06,usb,yes,37,37 2006.196.07:30:01.44/va/04,07,usb,yes,36,39 2006.196.07:30:01.44/va/05,07,usb,yes,38,40 2006.196.07:30:01.44/va/06,06,usb,yes,37,37 2006.196.07:30:01.44/va/07,06,usb,yes,38,38 2006.196.07:30:01.44/va/08,07,usb,yes,36,35 2006.196.07:30:01.67/valo/01,532.99,yes,locked 2006.196.07:30:01.67/valo/02,572.99,yes,locked 2006.196.07:30:01.67/valo/03,672.99,yes,locked 2006.196.07:30:01.67/valo/04,832.99,yes,locked 2006.196.07:30:01.67/valo/05,652.99,yes,locked 2006.196.07:30:01.67/valo/06,772.99,yes,locked 2006.196.07:30:01.67/valo/07,832.99,yes,locked 2006.196.07:30:01.67/valo/08,852.99,yes,locked 2006.196.07:30:02.76/vb/01,04,usb,yes,32,30 2006.196.07:30:02.76/vb/02,04,usb,yes,34,35 2006.196.07:30:02.76/vb/03,04,usb,yes,30,34 2006.196.07:30:02.76/vb/04,04,usb,yes,31,31 2006.196.07:30:02.76/vb/05,04,usb,yes,30,34 2006.196.07:30:02.76/vb/06,04,usb,yes,31,34 2006.196.07:30:02.76/vb/07,04,usb,yes,33,33 2006.196.07:30:02.76/vb/08,04,usb,yes,30,34 2006.196.07:30:03.00/vblo/01,632.99,yes,locked 2006.196.07:30:03.00/vblo/02,640.99,yes,locked 2006.196.07:30:03.00/vblo/03,656.99,yes,locked 2006.196.07:30:03.00/vblo/04,712.99,yes,locked 2006.196.07:30:03.00/vblo/05,744.99,yes,locked 2006.196.07:30:03.00/vblo/06,752.99,yes,locked 2006.196.07:30:03.00/vblo/07,734.99,yes,locked 2006.196.07:30:03.00/vblo/08,744.99,yes,locked 2006.196.07:30:03.15/vabw/8 2006.196.07:30:03.30/vbbw/8 2006.196.07:30:03.41/xfe/off,on,15.0 2006.196.07:30:03.78/ifatt/23,28,28,28 2006.196.07:30:04.07/fmout-gps/S +3.37E-07 2006.196.07:30:04.15:!2006.196.07:31:00 2006.196.07:31:00.00:data_valid=off 2006.196.07:31:00.00:postob 2006.196.07:31:00.00&postob/cable 2006.196.07:31:00.01&postob/wx 2006.196.07:31:00.01&postob/clockoff 2006.196.07:31:00.19/cable/+6.3308E-03 2006.196.07:31:00.19/wx/30.32,1004.2,87 2006.196.07:31:01.07/fmout-gps/S +3.38E-07 2006.196.07:31:01.07:scan_name=196-0733,k06196,60 2006.196.07:31:01.07:source=0823+033,082550.34,030924.5,2000.0,ccw 2006.196.07:31:01.14#flagr#flagr/antenna,new-source 2006.196.07:31:02.14:checkk5 2006.196.07:31:02.14&checkk5/chk_autoobs=1 2006.196.07:31:02.14&checkk5/chk_autoobs=2 2006.196.07:31:02.15&checkk5/chk_autoobs=3 2006.196.07:31:02.15&checkk5/chk_autoobs=4 2006.196.07:31:02.15&checkk5/chk_obsdata=1 2006.196.07:31:02.16&checkk5/chk_obsdata=2 2006.196.07:31:02.16&checkk5/chk_obsdata=3 2006.196.07:31:02.16&checkk5/chk_obsdata=4 2006.196.07:31:02.17&checkk5/k5log=1 2006.196.07:31:02.17&checkk5/k5log=2 2006.196.07:31:02.17&checkk5/k5log=3 2006.196.07:31:02.18&checkk5/k5log=4 2006.196.07:31:02.18&checkk5/obsinfo 2006.196.07:31:02.61/chk_autoobs//k5ts1/ autoobs is running! 2006.196.07:31:02.98/chk_autoobs//k5ts2/ autoobs is running! 2006.196.07:31:03.53/chk_autoobs//k5ts3/ autoobs is running! 2006.196.07:31:03.92/chk_autoobs//k5ts4/ autoobs is running! 2006.196.07:31:04.29/chk_obsdata//k5ts1/T1960730??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.07:31:04.65/chk_obsdata//k5ts2/T1960730??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.07:31:05.04/chk_obsdata//k5ts3/T1960730??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.07:31:05.41/chk_obsdata//k5ts4/T1960730??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.07:31:06.12/k5log//k5ts1_log_newline 2006.196.07:31:06.80/k5log//k5ts2_log_newline 2006.196.07:31:07.50/k5log//k5ts3_log_newline 2006.196.07:31:08.18/k5log//k5ts4_log_newline 2006.196.07:31:08.21/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.196.07:31:08.21:4f8m12a=1 2006.196.07:31:08.21$4f8m12a/echo=on 2006.196.07:31:08.21$4f8m12a/pcalon 2006.196.07:31:08.21$pcalon/"no phase cal control is implemented here 2006.196.07:31:08.21$4f8m12a/"tpicd=stop 2006.196.07:31:08.21$4f8m12a/vc4f8 2006.196.07:31:08.21$vc4f8/valo=1,532.99 2006.196.07:31:08.21#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.196.07:31:08.21#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.196.07:31:08.21#ibcon#ireg 17 cls_cnt 0 2006.196.07:31:08.21#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.196.07:31:08.21#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.196.07:31:08.21#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.196.07:31:08.21#ibcon#enter wrdev, iclass 29, count 0 2006.196.07:31:08.21#ibcon#first serial, iclass 29, count 0 2006.196.07:31:08.21#ibcon#enter sib2, iclass 29, count 0 2006.196.07:31:08.21#ibcon#flushed, iclass 29, count 0 2006.196.07:31:08.21#ibcon#about to write, iclass 29, count 0 2006.196.07:31:08.21#ibcon#wrote, iclass 29, count 0 2006.196.07:31:08.21#ibcon#about to read 3, iclass 29, count 0 2006.196.07:31:08.23#ibcon#read 3, iclass 29, count 0 2006.196.07:31:08.23#ibcon#about to read 4, iclass 29, count 0 2006.196.07:31:08.23#ibcon#read 4, iclass 29, count 0 2006.196.07:31:08.23#ibcon#about to read 5, iclass 29, count 0 2006.196.07:31:08.23#ibcon#read 5, iclass 29, count 0 2006.196.07:31:08.23#ibcon#about to read 6, iclass 29, count 0 2006.196.07:31:08.23#ibcon#read 6, iclass 29, count 0 2006.196.07:31:08.23#ibcon#end of sib2, iclass 29, count 0 2006.196.07:31:08.23#ibcon#*mode == 0, iclass 29, count 0 2006.196.07:31:08.23#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.196.07:31:08.23#ibcon#[26=FRQ=01,532.99\r\n] 2006.196.07:31:08.23#ibcon#*before write, iclass 29, count 0 2006.196.07:31:08.23#ibcon#enter sib2, iclass 29, count 0 2006.196.07:31:08.23#ibcon#flushed, iclass 29, count 0 2006.196.07:31:08.23#ibcon#about to write, iclass 29, count 0 2006.196.07:31:08.23#ibcon#wrote, iclass 29, count 0 2006.196.07:31:08.23#ibcon#about to read 3, iclass 29, count 0 2006.196.07:31:08.28#ibcon#read 3, iclass 29, count 0 2006.196.07:31:08.28#ibcon#about to read 4, iclass 29, count 0 2006.196.07:31:08.28#ibcon#read 4, iclass 29, count 0 2006.196.07:31:08.28#ibcon#about to read 5, iclass 29, count 0 2006.196.07:31:08.28#ibcon#read 5, iclass 29, count 0 2006.196.07:31:08.28#ibcon#about to read 6, iclass 29, count 0 2006.196.07:31:08.28#ibcon#read 6, iclass 29, count 0 2006.196.07:31:08.28#ibcon#end of sib2, iclass 29, count 0 2006.196.07:31:08.28#ibcon#*after write, iclass 29, count 0 2006.196.07:31:08.28#ibcon#*before return 0, iclass 29, count 0 2006.196.07:31:08.28#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.196.07:31:08.28#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.196.07:31:08.28#ibcon#about to clear, iclass 29 cls_cnt 0 2006.196.07:31:08.28#ibcon#cleared, iclass 29 cls_cnt 0 2006.196.07:31:08.28$vc4f8/va=1,8 2006.196.07:31:08.28#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.196.07:31:08.28#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.196.07:31:08.28#ibcon#ireg 11 cls_cnt 2 2006.196.07:31:08.28#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.196.07:31:08.28#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.196.07:31:08.28#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.196.07:31:08.28#ibcon#enter wrdev, iclass 31, count 2 2006.196.07:31:08.28#ibcon#first serial, iclass 31, count 2 2006.196.07:31:08.28#ibcon#enter sib2, iclass 31, count 2 2006.196.07:31:08.28#ibcon#flushed, iclass 31, count 2 2006.196.07:31:08.28#ibcon#about to write, iclass 31, count 2 2006.196.07:31:08.28#ibcon#wrote, iclass 31, count 2 2006.196.07:31:08.28#ibcon#about to read 3, iclass 31, count 2 2006.196.07:31:08.30#ibcon#read 3, iclass 31, count 2 2006.196.07:31:08.30#ibcon#about to read 4, iclass 31, count 2 2006.196.07:31:08.30#ibcon#read 4, iclass 31, count 2 2006.196.07:31:08.30#ibcon#about to read 5, iclass 31, count 2 2006.196.07:31:08.30#ibcon#read 5, iclass 31, count 2 2006.196.07:31:08.30#ibcon#about to read 6, iclass 31, count 2 2006.196.07:31:08.30#ibcon#read 6, iclass 31, count 2 2006.196.07:31:08.30#ibcon#end of sib2, iclass 31, count 2 2006.196.07:31:08.30#ibcon#*mode == 0, iclass 31, count 2 2006.196.07:31:08.30#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.196.07:31:08.30#ibcon#[25=AT01-08\r\n] 2006.196.07:31:08.30#ibcon#*before write, iclass 31, count 2 2006.196.07:31:08.30#ibcon#enter sib2, iclass 31, count 2 2006.196.07:31:08.30#ibcon#flushed, iclass 31, count 2 2006.196.07:31:08.30#ibcon#about to write, iclass 31, count 2 2006.196.07:31:08.30#ibcon#wrote, iclass 31, count 2 2006.196.07:31:08.30#ibcon#about to read 3, iclass 31, count 2 2006.196.07:31:08.33#ibcon#read 3, iclass 31, count 2 2006.196.07:31:08.33#ibcon#about to read 4, iclass 31, count 2 2006.196.07:31:08.33#ibcon#read 4, iclass 31, count 2 2006.196.07:31:08.33#ibcon#about to read 5, iclass 31, count 2 2006.196.07:31:08.33#ibcon#read 5, iclass 31, count 2 2006.196.07:31:08.33#ibcon#about to read 6, iclass 31, count 2 2006.196.07:31:08.33#ibcon#read 6, iclass 31, count 2 2006.196.07:31:08.33#ibcon#end of sib2, iclass 31, count 2 2006.196.07:31:08.33#ibcon#*after write, iclass 31, count 2 2006.196.07:31:08.33#ibcon#*before return 0, iclass 31, count 2 2006.196.07:31:08.33#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.196.07:31:08.33#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.196.07:31:08.33#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.196.07:31:08.33#ibcon#ireg 7 cls_cnt 0 2006.196.07:31:08.33#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.196.07:31:08.45#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.196.07:31:08.45#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.196.07:31:08.45#ibcon#enter wrdev, iclass 31, count 0 2006.196.07:31:08.45#ibcon#first serial, iclass 31, count 0 2006.196.07:31:08.45#ibcon#enter sib2, iclass 31, count 0 2006.196.07:31:08.45#ibcon#flushed, iclass 31, count 0 2006.196.07:31:08.45#ibcon#about to write, iclass 31, count 0 2006.196.07:31:08.45#ibcon#wrote, iclass 31, count 0 2006.196.07:31:08.45#ibcon#about to read 3, iclass 31, count 0 2006.196.07:31:08.47#ibcon#read 3, iclass 31, count 0 2006.196.07:31:08.47#ibcon#about to read 4, iclass 31, count 0 2006.196.07:31:08.47#ibcon#read 4, iclass 31, count 0 2006.196.07:31:08.47#ibcon#about to read 5, iclass 31, count 0 2006.196.07:31:08.47#ibcon#read 5, iclass 31, count 0 2006.196.07:31:08.47#ibcon#about to read 6, iclass 31, count 0 2006.196.07:31:08.47#ibcon#read 6, iclass 31, count 0 2006.196.07:31:08.47#ibcon#end of sib2, iclass 31, count 0 2006.196.07:31:08.47#ibcon#*mode == 0, iclass 31, count 0 2006.196.07:31:08.47#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.196.07:31:08.47#ibcon#[25=USB\r\n] 2006.196.07:31:08.47#ibcon#*before write, iclass 31, count 0 2006.196.07:31:08.47#ibcon#enter sib2, iclass 31, count 0 2006.196.07:31:08.47#ibcon#flushed, iclass 31, count 0 2006.196.07:31:08.47#ibcon#about to write, iclass 31, count 0 2006.196.07:31:08.47#ibcon#wrote, iclass 31, count 0 2006.196.07:31:08.47#ibcon#about to read 3, iclass 31, count 0 2006.196.07:31:08.50#ibcon#read 3, iclass 31, count 0 2006.196.07:31:08.50#ibcon#about to read 4, iclass 31, count 0 2006.196.07:31:08.50#ibcon#read 4, iclass 31, count 0 2006.196.07:31:08.50#ibcon#about to read 5, iclass 31, count 0 2006.196.07:31:08.50#ibcon#read 5, iclass 31, count 0 2006.196.07:31:08.50#ibcon#about to read 6, iclass 31, count 0 2006.196.07:31:08.50#ibcon#read 6, iclass 31, count 0 2006.196.07:31:08.50#ibcon#end of sib2, iclass 31, count 0 2006.196.07:31:08.50#ibcon#*after write, iclass 31, count 0 2006.196.07:31:08.50#ibcon#*before return 0, iclass 31, count 0 2006.196.07:31:08.50#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.196.07:31:08.50#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.196.07:31:08.50#ibcon#about to clear, iclass 31 cls_cnt 0 2006.196.07:31:08.50#ibcon#cleared, iclass 31 cls_cnt 0 2006.196.07:31:08.50$vc4f8/valo=2,572.99 2006.196.07:31:08.50#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.196.07:31:08.50#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.196.07:31:08.50#ibcon#ireg 17 cls_cnt 0 2006.196.07:31:08.50#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.196.07:31:08.50#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.196.07:31:08.50#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.196.07:31:08.50#ibcon#enter wrdev, iclass 33, count 0 2006.196.07:31:08.50#ibcon#first serial, iclass 33, count 0 2006.196.07:31:08.50#ibcon#enter sib2, iclass 33, count 0 2006.196.07:31:08.50#ibcon#flushed, iclass 33, count 0 2006.196.07:31:08.50#ibcon#about to write, iclass 33, count 0 2006.196.07:31:08.50#ibcon#wrote, iclass 33, count 0 2006.196.07:31:08.50#ibcon#about to read 3, iclass 33, count 0 2006.196.07:31:08.52#ibcon#read 3, iclass 33, count 0 2006.196.07:31:08.52#ibcon#about to read 4, iclass 33, count 0 2006.196.07:31:08.52#ibcon#read 4, iclass 33, count 0 2006.196.07:31:08.52#ibcon#about to read 5, iclass 33, count 0 2006.196.07:31:08.52#ibcon#read 5, iclass 33, count 0 2006.196.07:31:08.52#ibcon#about to read 6, iclass 33, count 0 2006.196.07:31:08.52#ibcon#read 6, iclass 33, count 0 2006.196.07:31:08.52#ibcon#end of sib2, iclass 33, count 0 2006.196.07:31:08.52#ibcon#*mode == 0, iclass 33, count 0 2006.196.07:31:08.52#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.196.07:31:08.52#ibcon#[26=FRQ=02,572.99\r\n] 2006.196.07:31:08.52#ibcon#*before write, iclass 33, count 0 2006.196.07:31:08.52#ibcon#enter sib2, iclass 33, count 0 2006.196.07:31:08.52#ibcon#flushed, iclass 33, count 0 2006.196.07:31:08.52#ibcon#about to write, iclass 33, count 0 2006.196.07:31:08.52#ibcon#wrote, iclass 33, count 0 2006.196.07:31:08.52#ibcon#about to read 3, iclass 33, count 0 2006.196.07:31:08.57#ibcon#read 3, iclass 33, count 0 2006.196.07:31:08.57#ibcon#about to read 4, iclass 33, count 0 2006.196.07:31:08.57#ibcon#read 4, iclass 33, count 0 2006.196.07:31:08.57#ibcon#about to read 5, iclass 33, count 0 2006.196.07:31:08.57#ibcon#read 5, iclass 33, count 0 2006.196.07:31:08.57#ibcon#about to read 6, iclass 33, count 0 2006.196.07:31:08.57#ibcon#read 6, iclass 33, count 0 2006.196.07:31:08.57#ibcon#end of sib2, iclass 33, count 0 2006.196.07:31:08.57#ibcon#*after write, iclass 33, count 0 2006.196.07:31:08.57#ibcon#*before return 0, iclass 33, count 0 2006.196.07:31:08.57#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.196.07:31:08.57#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.196.07:31:08.57#ibcon#about to clear, iclass 33 cls_cnt 0 2006.196.07:31:08.57#ibcon#cleared, iclass 33 cls_cnt 0 2006.196.07:31:08.57$vc4f8/va=2,7 2006.196.07:31:08.57#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.196.07:31:08.57#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.196.07:31:08.57#ibcon#ireg 11 cls_cnt 2 2006.196.07:31:08.57#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.196.07:31:08.62#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.196.07:31:08.62#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.196.07:31:08.62#ibcon#enter wrdev, iclass 35, count 2 2006.196.07:31:08.62#ibcon#first serial, iclass 35, count 2 2006.196.07:31:08.62#ibcon#enter sib2, iclass 35, count 2 2006.196.07:31:08.62#ibcon#flushed, iclass 35, count 2 2006.196.07:31:08.62#ibcon#about to write, iclass 35, count 2 2006.196.07:31:08.62#ibcon#wrote, iclass 35, count 2 2006.196.07:31:08.62#ibcon#about to read 3, iclass 35, count 2 2006.196.07:31:08.64#ibcon#read 3, iclass 35, count 2 2006.196.07:31:08.64#ibcon#about to read 4, iclass 35, count 2 2006.196.07:31:08.64#ibcon#read 4, iclass 35, count 2 2006.196.07:31:08.64#ibcon#about to read 5, iclass 35, count 2 2006.196.07:31:08.64#ibcon#read 5, iclass 35, count 2 2006.196.07:31:08.64#ibcon#about to read 6, iclass 35, count 2 2006.196.07:31:08.64#ibcon#read 6, iclass 35, count 2 2006.196.07:31:08.64#ibcon#end of sib2, iclass 35, count 2 2006.196.07:31:08.64#ibcon#*mode == 0, iclass 35, count 2 2006.196.07:31:08.64#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.196.07:31:08.64#ibcon#[25=AT02-07\r\n] 2006.196.07:31:08.64#ibcon#*before write, iclass 35, count 2 2006.196.07:31:08.64#ibcon#enter sib2, iclass 35, count 2 2006.196.07:31:08.64#ibcon#flushed, iclass 35, count 2 2006.196.07:31:08.64#ibcon#about to write, iclass 35, count 2 2006.196.07:31:08.64#ibcon#wrote, iclass 35, count 2 2006.196.07:31:08.64#ibcon#about to read 3, iclass 35, count 2 2006.196.07:31:08.67#ibcon#read 3, iclass 35, count 2 2006.196.07:31:08.67#ibcon#about to read 4, iclass 35, count 2 2006.196.07:31:08.67#ibcon#read 4, iclass 35, count 2 2006.196.07:31:08.67#ibcon#about to read 5, iclass 35, count 2 2006.196.07:31:08.67#ibcon#read 5, iclass 35, count 2 2006.196.07:31:08.67#ibcon#about to read 6, iclass 35, count 2 2006.196.07:31:08.67#ibcon#read 6, iclass 35, count 2 2006.196.07:31:08.67#ibcon#end of sib2, iclass 35, count 2 2006.196.07:31:08.67#ibcon#*after write, iclass 35, count 2 2006.196.07:31:08.67#ibcon#*before return 0, iclass 35, count 2 2006.196.07:31:08.67#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.196.07:31:08.67#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.196.07:31:08.67#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.196.07:31:08.67#ibcon#ireg 7 cls_cnt 0 2006.196.07:31:08.67#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.196.07:31:08.79#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.196.07:31:08.79#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.196.07:31:08.79#ibcon#enter wrdev, iclass 35, count 0 2006.196.07:31:08.79#ibcon#first serial, iclass 35, count 0 2006.196.07:31:08.79#ibcon#enter sib2, iclass 35, count 0 2006.196.07:31:08.79#ibcon#flushed, iclass 35, count 0 2006.196.07:31:08.79#ibcon#about to write, iclass 35, count 0 2006.196.07:31:08.79#ibcon#wrote, iclass 35, count 0 2006.196.07:31:08.79#ibcon#about to read 3, iclass 35, count 0 2006.196.07:31:08.81#ibcon#read 3, iclass 35, count 0 2006.196.07:31:08.81#ibcon#about to read 4, iclass 35, count 0 2006.196.07:31:08.81#ibcon#read 4, iclass 35, count 0 2006.196.07:31:08.81#ibcon#about to read 5, iclass 35, count 0 2006.196.07:31:08.81#ibcon#read 5, iclass 35, count 0 2006.196.07:31:08.81#ibcon#about to read 6, iclass 35, count 0 2006.196.07:31:08.81#ibcon#read 6, iclass 35, count 0 2006.196.07:31:08.81#ibcon#end of sib2, iclass 35, count 0 2006.196.07:31:08.81#ibcon#*mode == 0, iclass 35, count 0 2006.196.07:31:08.81#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.196.07:31:08.81#ibcon#[25=USB\r\n] 2006.196.07:31:08.81#ibcon#*before write, iclass 35, count 0 2006.196.07:31:08.81#ibcon#enter sib2, iclass 35, count 0 2006.196.07:31:08.81#ibcon#flushed, iclass 35, count 0 2006.196.07:31:08.81#ibcon#about to write, iclass 35, count 0 2006.196.07:31:08.81#ibcon#wrote, iclass 35, count 0 2006.196.07:31:08.81#ibcon#about to read 3, iclass 35, count 0 2006.196.07:31:08.84#ibcon#read 3, iclass 35, count 0 2006.196.07:31:08.84#ibcon#about to read 4, iclass 35, count 0 2006.196.07:31:08.84#ibcon#read 4, iclass 35, count 0 2006.196.07:31:08.84#ibcon#about to read 5, iclass 35, count 0 2006.196.07:31:08.84#ibcon#read 5, iclass 35, count 0 2006.196.07:31:08.84#ibcon#about to read 6, iclass 35, count 0 2006.196.07:31:08.84#ibcon#read 6, iclass 35, count 0 2006.196.07:31:08.84#ibcon#end of sib2, iclass 35, count 0 2006.196.07:31:08.84#ibcon#*after write, iclass 35, count 0 2006.196.07:31:08.84#ibcon#*before return 0, iclass 35, count 0 2006.196.07:31:08.84#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.196.07:31:08.84#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.196.07:31:08.84#ibcon#about to clear, iclass 35 cls_cnt 0 2006.196.07:31:08.84#ibcon#cleared, iclass 35 cls_cnt 0 2006.196.07:31:08.84$vc4f8/valo=3,672.99 2006.196.07:31:08.84#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.196.07:31:08.84#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.196.07:31:08.84#ibcon#ireg 17 cls_cnt 0 2006.196.07:31:08.84#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.196.07:31:08.84#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.196.07:31:08.84#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.196.07:31:08.84#ibcon#enter wrdev, iclass 37, count 0 2006.196.07:31:08.84#ibcon#first serial, iclass 37, count 0 2006.196.07:31:08.84#ibcon#enter sib2, iclass 37, count 0 2006.196.07:31:08.84#ibcon#flushed, iclass 37, count 0 2006.196.07:31:08.84#ibcon#about to write, iclass 37, count 0 2006.196.07:31:08.84#ibcon#wrote, iclass 37, count 0 2006.196.07:31:08.84#ibcon#about to read 3, iclass 37, count 0 2006.196.07:31:08.86#ibcon#read 3, iclass 37, count 0 2006.196.07:31:08.86#ibcon#about to read 4, iclass 37, count 0 2006.196.07:31:08.86#ibcon#read 4, iclass 37, count 0 2006.196.07:31:08.86#ibcon#about to read 5, iclass 37, count 0 2006.196.07:31:08.86#ibcon#read 5, iclass 37, count 0 2006.196.07:31:08.86#ibcon#about to read 6, iclass 37, count 0 2006.196.07:31:08.86#ibcon#read 6, iclass 37, count 0 2006.196.07:31:08.86#ibcon#end of sib2, iclass 37, count 0 2006.196.07:31:08.86#ibcon#*mode == 0, iclass 37, count 0 2006.196.07:31:08.86#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.196.07:31:08.86#ibcon#[26=FRQ=03,672.99\r\n] 2006.196.07:31:08.86#ibcon#*before write, iclass 37, count 0 2006.196.07:31:08.86#ibcon#enter sib2, iclass 37, count 0 2006.196.07:31:08.86#ibcon#flushed, iclass 37, count 0 2006.196.07:31:08.86#ibcon#about to write, iclass 37, count 0 2006.196.07:31:08.86#ibcon#wrote, iclass 37, count 0 2006.196.07:31:08.86#ibcon#about to read 3, iclass 37, count 0 2006.196.07:31:08.90#ibcon#read 3, iclass 37, count 0 2006.196.07:31:08.90#ibcon#about to read 4, iclass 37, count 0 2006.196.07:31:08.90#ibcon#read 4, iclass 37, count 0 2006.196.07:31:08.90#ibcon#about to read 5, iclass 37, count 0 2006.196.07:31:08.90#ibcon#read 5, iclass 37, count 0 2006.196.07:31:08.90#ibcon#about to read 6, iclass 37, count 0 2006.196.07:31:08.90#ibcon#read 6, iclass 37, count 0 2006.196.07:31:08.90#ibcon#end of sib2, iclass 37, count 0 2006.196.07:31:08.90#ibcon#*after write, iclass 37, count 0 2006.196.07:31:08.90#ibcon#*before return 0, iclass 37, count 0 2006.196.07:31:08.90#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.196.07:31:08.90#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.196.07:31:08.90#ibcon#about to clear, iclass 37 cls_cnt 0 2006.196.07:31:08.90#ibcon#cleared, iclass 37 cls_cnt 0 2006.196.07:31:08.90$vc4f8/va=3,6 2006.196.07:31:08.90#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.196.07:31:08.90#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.196.07:31:08.90#ibcon#ireg 11 cls_cnt 2 2006.196.07:31:08.90#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.196.07:31:08.96#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.196.07:31:08.96#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.196.07:31:08.96#ibcon#enter wrdev, iclass 39, count 2 2006.196.07:31:08.96#ibcon#first serial, iclass 39, count 2 2006.196.07:31:08.96#ibcon#enter sib2, iclass 39, count 2 2006.196.07:31:08.96#ibcon#flushed, iclass 39, count 2 2006.196.07:31:08.96#ibcon#about to write, iclass 39, count 2 2006.196.07:31:08.96#ibcon#wrote, iclass 39, count 2 2006.196.07:31:08.96#ibcon#about to read 3, iclass 39, count 2 2006.196.07:31:08.98#ibcon#read 3, iclass 39, count 2 2006.196.07:31:08.98#ibcon#about to read 4, iclass 39, count 2 2006.196.07:31:08.98#ibcon#read 4, iclass 39, count 2 2006.196.07:31:08.98#ibcon#about to read 5, iclass 39, count 2 2006.196.07:31:08.98#ibcon#read 5, iclass 39, count 2 2006.196.07:31:08.98#ibcon#about to read 6, iclass 39, count 2 2006.196.07:31:08.98#ibcon#read 6, iclass 39, count 2 2006.196.07:31:08.98#ibcon#end of sib2, iclass 39, count 2 2006.196.07:31:08.98#ibcon#*mode == 0, iclass 39, count 2 2006.196.07:31:08.98#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.196.07:31:08.98#ibcon#[25=AT03-06\r\n] 2006.196.07:31:08.98#ibcon#*before write, iclass 39, count 2 2006.196.07:31:08.98#ibcon#enter sib2, iclass 39, count 2 2006.196.07:31:08.98#ibcon#flushed, iclass 39, count 2 2006.196.07:31:08.98#ibcon#about to write, iclass 39, count 2 2006.196.07:31:08.98#ibcon#wrote, iclass 39, count 2 2006.196.07:31:08.98#ibcon#about to read 3, iclass 39, count 2 2006.196.07:31:09.01#ibcon#read 3, iclass 39, count 2 2006.196.07:31:09.01#ibcon#about to read 4, iclass 39, count 2 2006.196.07:31:09.01#ibcon#read 4, iclass 39, count 2 2006.196.07:31:09.01#ibcon#about to read 5, iclass 39, count 2 2006.196.07:31:09.01#ibcon#read 5, iclass 39, count 2 2006.196.07:31:09.01#ibcon#about to read 6, iclass 39, count 2 2006.196.07:31:09.01#ibcon#read 6, iclass 39, count 2 2006.196.07:31:09.01#ibcon#end of sib2, iclass 39, count 2 2006.196.07:31:09.01#ibcon#*after write, iclass 39, count 2 2006.196.07:31:09.01#ibcon#*before return 0, iclass 39, count 2 2006.196.07:31:09.01#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.196.07:31:09.01#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.196.07:31:09.01#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.196.07:31:09.01#ibcon#ireg 7 cls_cnt 0 2006.196.07:31:09.01#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.196.07:31:09.13#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.196.07:31:09.13#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.196.07:31:09.13#ibcon#enter wrdev, iclass 39, count 0 2006.196.07:31:09.13#ibcon#first serial, iclass 39, count 0 2006.196.07:31:09.13#ibcon#enter sib2, iclass 39, count 0 2006.196.07:31:09.13#ibcon#flushed, iclass 39, count 0 2006.196.07:31:09.13#ibcon#about to write, iclass 39, count 0 2006.196.07:31:09.13#ibcon#wrote, iclass 39, count 0 2006.196.07:31:09.13#ibcon#about to read 3, iclass 39, count 0 2006.196.07:31:09.15#ibcon#read 3, iclass 39, count 0 2006.196.07:31:09.15#ibcon#about to read 4, iclass 39, count 0 2006.196.07:31:09.15#ibcon#read 4, iclass 39, count 0 2006.196.07:31:09.15#ibcon#about to read 5, iclass 39, count 0 2006.196.07:31:09.15#ibcon#read 5, iclass 39, count 0 2006.196.07:31:09.15#ibcon#about to read 6, iclass 39, count 0 2006.196.07:31:09.15#ibcon#read 6, iclass 39, count 0 2006.196.07:31:09.15#ibcon#end of sib2, iclass 39, count 0 2006.196.07:31:09.15#ibcon#*mode == 0, iclass 39, count 0 2006.196.07:31:09.15#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.196.07:31:09.15#ibcon#[25=USB\r\n] 2006.196.07:31:09.15#ibcon#*before write, iclass 39, count 0 2006.196.07:31:09.15#ibcon#enter sib2, iclass 39, count 0 2006.196.07:31:09.15#ibcon#flushed, iclass 39, count 0 2006.196.07:31:09.15#ibcon#about to write, iclass 39, count 0 2006.196.07:31:09.15#ibcon#wrote, iclass 39, count 0 2006.196.07:31:09.15#ibcon#about to read 3, iclass 39, count 0 2006.196.07:31:09.18#ibcon#read 3, iclass 39, count 0 2006.196.07:31:09.18#ibcon#about to read 4, iclass 39, count 0 2006.196.07:31:09.18#ibcon#read 4, iclass 39, count 0 2006.196.07:31:09.18#ibcon#about to read 5, iclass 39, count 0 2006.196.07:31:09.18#ibcon#read 5, iclass 39, count 0 2006.196.07:31:09.18#ibcon#about to read 6, iclass 39, count 0 2006.196.07:31:09.18#ibcon#read 6, iclass 39, count 0 2006.196.07:31:09.18#ibcon#end of sib2, iclass 39, count 0 2006.196.07:31:09.18#ibcon#*after write, iclass 39, count 0 2006.196.07:31:09.18#ibcon#*before return 0, iclass 39, count 0 2006.196.07:31:09.18#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.196.07:31:09.18#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.196.07:31:09.18#ibcon#about to clear, iclass 39 cls_cnt 0 2006.196.07:31:09.18#ibcon#cleared, iclass 39 cls_cnt 0 2006.196.07:31:09.18$vc4f8/valo=4,832.99 2006.196.07:31:09.18#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.196.07:31:09.18#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.196.07:31:09.18#ibcon#ireg 17 cls_cnt 0 2006.196.07:31:09.18#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.196.07:31:09.18#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.196.07:31:09.18#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.196.07:31:09.18#ibcon#enter wrdev, iclass 3, count 0 2006.196.07:31:09.18#ibcon#first serial, iclass 3, count 0 2006.196.07:31:09.18#ibcon#enter sib2, iclass 3, count 0 2006.196.07:31:09.18#ibcon#flushed, iclass 3, count 0 2006.196.07:31:09.18#ibcon#about to write, iclass 3, count 0 2006.196.07:31:09.18#ibcon#wrote, iclass 3, count 0 2006.196.07:31:09.18#ibcon#about to read 3, iclass 3, count 0 2006.196.07:31:09.20#ibcon#read 3, iclass 3, count 0 2006.196.07:31:09.20#ibcon#about to read 4, iclass 3, count 0 2006.196.07:31:09.20#ibcon#read 4, iclass 3, count 0 2006.196.07:31:09.20#ibcon#about to read 5, iclass 3, count 0 2006.196.07:31:09.20#ibcon#read 5, iclass 3, count 0 2006.196.07:31:09.20#ibcon#about to read 6, iclass 3, count 0 2006.196.07:31:09.20#ibcon#read 6, iclass 3, count 0 2006.196.07:31:09.20#ibcon#end of sib2, iclass 3, count 0 2006.196.07:31:09.20#ibcon#*mode == 0, iclass 3, count 0 2006.196.07:31:09.20#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.196.07:31:09.20#ibcon#[26=FRQ=04,832.99\r\n] 2006.196.07:31:09.20#ibcon#*before write, iclass 3, count 0 2006.196.07:31:09.20#ibcon#enter sib2, iclass 3, count 0 2006.196.07:31:09.20#ibcon#flushed, iclass 3, count 0 2006.196.07:31:09.20#ibcon#about to write, iclass 3, count 0 2006.196.07:31:09.20#ibcon#wrote, iclass 3, count 0 2006.196.07:31:09.20#ibcon#about to read 3, iclass 3, count 0 2006.196.07:31:09.24#ibcon#read 3, iclass 3, count 0 2006.196.07:31:09.24#ibcon#about to read 4, iclass 3, count 0 2006.196.07:31:09.24#ibcon#read 4, iclass 3, count 0 2006.196.07:31:09.24#ibcon#about to read 5, iclass 3, count 0 2006.196.07:31:09.24#ibcon#read 5, iclass 3, count 0 2006.196.07:31:09.24#ibcon#about to read 6, iclass 3, count 0 2006.196.07:31:09.24#ibcon#read 6, iclass 3, count 0 2006.196.07:31:09.24#ibcon#end of sib2, iclass 3, count 0 2006.196.07:31:09.24#ibcon#*after write, iclass 3, count 0 2006.196.07:31:09.24#ibcon#*before return 0, iclass 3, count 0 2006.196.07:31:09.24#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.196.07:31:09.24#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.196.07:31:09.24#ibcon#about to clear, iclass 3 cls_cnt 0 2006.196.07:31:09.24#ibcon#cleared, iclass 3 cls_cnt 0 2006.196.07:31:09.24$vc4f8/va=4,7 2006.196.07:31:09.24#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.196.07:31:09.24#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.196.07:31:09.24#ibcon#ireg 11 cls_cnt 2 2006.196.07:31:09.24#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.196.07:31:09.30#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.196.07:31:09.30#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.196.07:31:09.30#ibcon#enter wrdev, iclass 5, count 2 2006.196.07:31:09.30#ibcon#first serial, iclass 5, count 2 2006.196.07:31:09.30#ibcon#enter sib2, iclass 5, count 2 2006.196.07:31:09.30#ibcon#flushed, iclass 5, count 2 2006.196.07:31:09.30#ibcon#about to write, iclass 5, count 2 2006.196.07:31:09.30#ibcon#wrote, iclass 5, count 2 2006.196.07:31:09.30#ibcon#about to read 3, iclass 5, count 2 2006.196.07:31:09.32#ibcon#read 3, iclass 5, count 2 2006.196.07:31:09.32#ibcon#about to read 4, iclass 5, count 2 2006.196.07:31:09.32#ibcon#read 4, iclass 5, count 2 2006.196.07:31:09.32#ibcon#about to read 5, iclass 5, count 2 2006.196.07:31:09.32#ibcon#read 5, iclass 5, count 2 2006.196.07:31:09.32#ibcon#about to read 6, iclass 5, count 2 2006.196.07:31:09.32#ibcon#read 6, iclass 5, count 2 2006.196.07:31:09.32#ibcon#end of sib2, iclass 5, count 2 2006.196.07:31:09.32#ibcon#*mode == 0, iclass 5, count 2 2006.196.07:31:09.32#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.196.07:31:09.32#ibcon#[25=AT04-07\r\n] 2006.196.07:31:09.32#ibcon#*before write, iclass 5, count 2 2006.196.07:31:09.32#ibcon#enter sib2, iclass 5, count 2 2006.196.07:31:09.32#ibcon#flushed, iclass 5, count 2 2006.196.07:31:09.32#ibcon#about to write, iclass 5, count 2 2006.196.07:31:09.32#ibcon#wrote, iclass 5, count 2 2006.196.07:31:09.32#ibcon#about to read 3, iclass 5, count 2 2006.196.07:31:09.35#ibcon#read 3, iclass 5, count 2 2006.196.07:31:09.35#ibcon#about to read 4, iclass 5, count 2 2006.196.07:31:09.35#ibcon#read 4, iclass 5, count 2 2006.196.07:31:09.35#ibcon#about to read 5, iclass 5, count 2 2006.196.07:31:09.35#ibcon#read 5, iclass 5, count 2 2006.196.07:31:09.35#ibcon#about to read 6, iclass 5, count 2 2006.196.07:31:09.35#ibcon#read 6, iclass 5, count 2 2006.196.07:31:09.35#ibcon#end of sib2, iclass 5, count 2 2006.196.07:31:09.35#ibcon#*after write, iclass 5, count 2 2006.196.07:31:09.35#ibcon#*before return 0, iclass 5, count 2 2006.196.07:31:09.35#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.196.07:31:09.35#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.196.07:31:09.35#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.196.07:31:09.35#ibcon#ireg 7 cls_cnt 0 2006.196.07:31:09.35#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.196.07:31:09.47#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.196.07:31:09.47#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.196.07:31:09.47#ibcon#enter wrdev, iclass 5, count 0 2006.196.07:31:09.47#ibcon#first serial, iclass 5, count 0 2006.196.07:31:09.47#ibcon#enter sib2, iclass 5, count 0 2006.196.07:31:09.47#ibcon#flushed, iclass 5, count 0 2006.196.07:31:09.47#ibcon#about to write, iclass 5, count 0 2006.196.07:31:09.47#ibcon#wrote, iclass 5, count 0 2006.196.07:31:09.47#ibcon#about to read 3, iclass 5, count 0 2006.196.07:31:09.49#ibcon#read 3, iclass 5, count 0 2006.196.07:31:09.49#ibcon#about to read 4, iclass 5, count 0 2006.196.07:31:09.49#ibcon#read 4, iclass 5, count 0 2006.196.07:31:09.49#ibcon#about to read 5, iclass 5, count 0 2006.196.07:31:09.49#ibcon#read 5, iclass 5, count 0 2006.196.07:31:09.49#ibcon#about to read 6, iclass 5, count 0 2006.196.07:31:09.49#ibcon#read 6, iclass 5, count 0 2006.196.07:31:09.49#ibcon#end of sib2, iclass 5, count 0 2006.196.07:31:09.49#ibcon#*mode == 0, iclass 5, count 0 2006.196.07:31:09.49#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.196.07:31:09.49#ibcon#[25=USB\r\n] 2006.196.07:31:09.49#ibcon#*before write, iclass 5, count 0 2006.196.07:31:09.49#ibcon#enter sib2, iclass 5, count 0 2006.196.07:31:09.49#ibcon#flushed, iclass 5, count 0 2006.196.07:31:09.49#ibcon#about to write, iclass 5, count 0 2006.196.07:31:09.49#ibcon#wrote, iclass 5, count 0 2006.196.07:31:09.49#ibcon#about to read 3, iclass 5, count 0 2006.196.07:31:09.52#ibcon#read 3, iclass 5, count 0 2006.196.07:31:09.52#ibcon#about to read 4, iclass 5, count 0 2006.196.07:31:09.52#ibcon#read 4, iclass 5, count 0 2006.196.07:31:09.52#ibcon#about to read 5, iclass 5, count 0 2006.196.07:31:09.52#ibcon#read 5, iclass 5, count 0 2006.196.07:31:09.52#ibcon#about to read 6, iclass 5, count 0 2006.196.07:31:09.52#ibcon#read 6, iclass 5, count 0 2006.196.07:31:09.52#ibcon#end of sib2, iclass 5, count 0 2006.196.07:31:09.52#ibcon#*after write, iclass 5, count 0 2006.196.07:31:09.52#ibcon#*before return 0, iclass 5, count 0 2006.196.07:31:09.52#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.196.07:31:09.52#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.196.07:31:09.52#ibcon#about to clear, iclass 5 cls_cnt 0 2006.196.07:31:09.52#ibcon#cleared, iclass 5 cls_cnt 0 2006.196.07:31:09.52$vc4f8/valo=5,652.99 2006.196.07:31:09.52#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.196.07:31:09.52#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.196.07:31:09.52#ibcon#ireg 17 cls_cnt 0 2006.196.07:31:09.52#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.196.07:31:09.52#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.196.07:31:09.52#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.196.07:31:09.52#ibcon#enter wrdev, iclass 7, count 0 2006.196.07:31:09.52#ibcon#first serial, iclass 7, count 0 2006.196.07:31:09.52#ibcon#enter sib2, iclass 7, count 0 2006.196.07:31:09.52#ibcon#flushed, iclass 7, count 0 2006.196.07:31:09.52#ibcon#about to write, iclass 7, count 0 2006.196.07:31:09.52#ibcon#wrote, iclass 7, count 0 2006.196.07:31:09.52#ibcon#about to read 3, iclass 7, count 0 2006.196.07:31:09.54#ibcon#read 3, iclass 7, count 0 2006.196.07:31:09.54#ibcon#about to read 4, iclass 7, count 0 2006.196.07:31:09.54#ibcon#read 4, iclass 7, count 0 2006.196.07:31:09.54#ibcon#about to read 5, iclass 7, count 0 2006.196.07:31:09.54#ibcon#read 5, iclass 7, count 0 2006.196.07:31:09.54#ibcon#about to read 6, iclass 7, count 0 2006.196.07:31:09.54#ibcon#read 6, iclass 7, count 0 2006.196.07:31:09.54#ibcon#end of sib2, iclass 7, count 0 2006.196.07:31:09.54#ibcon#*mode == 0, iclass 7, count 0 2006.196.07:31:09.54#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.196.07:31:09.54#ibcon#[26=FRQ=05,652.99\r\n] 2006.196.07:31:09.54#ibcon#*before write, iclass 7, count 0 2006.196.07:31:09.54#ibcon#enter sib2, iclass 7, count 0 2006.196.07:31:09.54#ibcon#flushed, iclass 7, count 0 2006.196.07:31:09.54#ibcon#about to write, iclass 7, count 0 2006.196.07:31:09.54#ibcon#wrote, iclass 7, count 0 2006.196.07:31:09.54#ibcon#about to read 3, iclass 7, count 0 2006.196.07:31:09.58#ibcon#read 3, iclass 7, count 0 2006.196.07:31:09.58#ibcon#about to read 4, iclass 7, count 0 2006.196.07:31:09.58#ibcon#read 4, iclass 7, count 0 2006.196.07:31:09.58#ibcon#about to read 5, iclass 7, count 0 2006.196.07:31:09.58#ibcon#read 5, iclass 7, count 0 2006.196.07:31:09.58#ibcon#about to read 6, iclass 7, count 0 2006.196.07:31:09.58#ibcon#read 6, iclass 7, count 0 2006.196.07:31:09.58#ibcon#end of sib2, iclass 7, count 0 2006.196.07:31:09.58#ibcon#*after write, iclass 7, count 0 2006.196.07:31:09.58#ibcon#*before return 0, iclass 7, count 0 2006.196.07:31:09.58#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.196.07:31:09.58#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.196.07:31:09.58#ibcon#about to clear, iclass 7 cls_cnt 0 2006.196.07:31:09.58#ibcon#cleared, iclass 7 cls_cnt 0 2006.196.07:31:09.58$vc4f8/va=5,7 2006.196.07:31:09.58#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.196.07:31:09.58#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.196.07:31:09.58#ibcon#ireg 11 cls_cnt 2 2006.196.07:31:09.58#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.196.07:31:09.64#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.196.07:31:09.64#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.196.07:31:09.64#ibcon#enter wrdev, iclass 11, count 2 2006.196.07:31:09.64#ibcon#first serial, iclass 11, count 2 2006.196.07:31:09.64#ibcon#enter sib2, iclass 11, count 2 2006.196.07:31:09.64#ibcon#flushed, iclass 11, count 2 2006.196.07:31:09.64#ibcon#about to write, iclass 11, count 2 2006.196.07:31:09.64#ibcon#wrote, iclass 11, count 2 2006.196.07:31:09.64#ibcon#about to read 3, iclass 11, count 2 2006.196.07:31:09.66#ibcon#read 3, iclass 11, count 2 2006.196.07:31:09.66#ibcon#about to read 4, iclass 11, count 2 2006.196.07:31:09.66#ibcon#read 4, iclass 11, count 2 2006.196.07:31:09.66#ibcon#about to read 5, iclass 11, count 2 2006.196.07:31:09.66#ibcon#read 5, iclass 11, count 2 2006.196.07:31:09.66#ibcon#about to read 6, iclass 11, count 2 2006.196.07:31:09.66#ibcon#read 6, iclass 11, count 2 2006.196.07:31:09.66#ibcon#end of sib2, iclass 11, count 2 2006.196.07:31:09.66#ibcon#*mode == 0, iclass 11, count 2 2006.196.07:31:09.66#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.196.07:31:09.66#ibcon#[25=AT05-07\r\n] 2006.196.07:31:09.66#ibcon#*before write, iclass 11, count 2 2006.196.07:31:09.66#ibcon#enter sib2, iclass 11, count 2 2006.196.07:31:09.66#ibcon#flushed, iclass 11, count 2 2006.196.07:31:09.66#ibcon#about to write, iclass 11, count 2 2006.196.07:31:09.66#ibcon#wrote, iclass 11, count 2 2006.196.07:31:09.66#ibcon#about to read 3, iclass 11, count 2 2006.196.07:31:09.69#ibcon#read 3, iclass 11, count 2 2006.196.07:31:09.69#ibcon#about to read 4, iclass 11, count 2 2006.196.07:31:09.69#ibcon#read 4, iclass 11, count 2 2006.196.07:31:09.69#ibcon#about to read 5, iclass 11, count 2 2006.196.07:31:09.69#ibcon#read 5, iclass 11, count 2 2006.196.07:31:09.69#ibcon#about to read 6, iclass 11, count 2 2006.196.07:31:09.69#ibcon#read 6, iclass 11, count 2 2006.196.07:31:09.69#ibcon#end of sib2, iclass 11, count 2 2006.196.07:31:09.69#ibcon#*after write, iclass 11, count 2 2006.196.07:31:09.69#ibcon#*before return 0, iclass 11, count 2 2006.196.07:31:09.69#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.196.07:31:09.69#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.196.07:31:09.69#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.196.07:31:09.69#ibcon#ireg 7 cls_cnt 0 2006.196.07:31:09.69#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.196.07:31:09.81#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.196.07:31:09.81#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.196.07:31:09.81#ibcon#enter wrdev, iclass 11, count 0 2006.196.07:31:09.81#ibcon#first serial, iclass 11, count 0 2006.196.07:31:09.81#ibcon#enter sib2, iclass 11, count 0 2006.196.07:31:09.81#ibcon#flushed, iclass 11, count 0 2006.196.07:31:09.81#ibcon#about to write, iclass 11, count 0 2006.196.07:31:09.81#ibcon#wrote, iclass 11, count 0 2006.196.07:31:09.81#ibcon#about to read 3, iclass 11, count 0 2006.196.07:31:09.83#ibcon#read 3, iclass 11, count 0 2006.196.07:31:09.83#ibcon#about to read 4, iclass 11, count 0 2006.196.07:31:09.83#ibcon#read 4, iclass 11, count 0 2006.196.07:31:09.83#ibcon#about to read 5, iclass 11, count 0 2006.196.07:31:09.83#ibcon#read 5, iclass 11, count 0 2006.196.07:31:09.83#ibcon#about to read 6, iclass 11, count 0 2006.196.07:31:09.83#ibcon#read 6, iclass 11, count 0 2006.196.07:31:09.83#ibcon#end of sib2, iclass 11, count 0 2006.196.07:31:09.83#ibcon#*mode == 0, iclass 11, count 0 2006.196.07:31:09.83#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.196.07:31:09.83#ibcon#[25=USB\r\n] 2006.196.07:31:09.83#ibcon#*before write, iclass 11, count 0 2006.196.07:31:09.83#ibcon#enter sib2, iclass 11, count 0 2006.196.07:31:09.83#ibcon#flushed, iclass 11, count 0 2006.196.07:31:09.83#ibcon#about to write, iclass 11, count 0 2006.196.07:31:09.83#ibcon#wrote, iclass 11, count 0 2006.196.07:31:09.83#ibcon#about to read 3, iclass 11, count 0 2006.196.07:31:09.86#ibcon#read 3, iclass 11, count 0 2006.196.07:31:09.86#ibcon#about to read 4, iclass 11, count 0 2006.196.07:31:09.86#ibcon#read 4, iclass 11, count 0 2006.196.07:31:09.86#ibcon#about to read 5, iclass 11, count 0 2006.196.07:31:09.86#ibcon#read 5, iclass 11, count 0 2006.196.07:31:09.86#ibcon#about to read 6, iclass 11, count 0 2006.196.07:31:09.86#ibcon#read 6, iclass 11, count 0 2006.196.07:31:09.86#ibcon#end of sib2, iclass 11, count 0 2006.196.07:31:09.86#ibcon#*after write, iclass 11, count 0 2006.196.07:31:09.86#ibcon#*before return 0, iclass 11, count 0 2006.196.07:31:09.86#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.196.07:31:09.86#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.196.07:31:09.86#ibcon#about to clear, iclass 11 cls_cnt 0 2006.196.07:31:09.86#ibcon#cleared, iclass 11 cls_cnt 0 2006.196.07:31:09.86$vc4f8/valo=6,772.99 2006.196.07:31:09.86#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.196.07:31:09.86#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.196.07:31:09.86#ibcon#ireg 17 cls_cnt 0 2006.196.07:31:09.86#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.196.07:31:09.86#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.196.07:31:09.86#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.196.07:31:09.86#ibcon#enter wrdev, iclass 13, count 0 2006.196.07:31:09.86#ibcon#first serial, iclass 13, count 0 2006.196.07:31:09.86#ibcon#enter sib2, iclass 13, count 0 2006.196.07:31:09.86#ibcon#flushed, iclass 13, count 0 2006.196.07:31:09.86#ibcon#about to write, iclass 13, count 0 2006.196.07:31:09.86#ibcon#wrote, iclass 13, count 0 2006.196.07:31:09.86#ibcon#about to read 3, iclass 13, count 0 2006.196.07:31:09.88#ibcon#read 3, iclass 13, count 0 2006.196.07:31:09.88#ibcon#about to read 4, iclass 13, count 0 2006.196.07:31:09.88#ibcon#read 4, iclass 13, count 0 2006.196.07:31:09.88#ibcon#about to read 5, iclass 13, count 0 2006.196.07:31:09.88#ibcon#read 5, iclass 13, count 0 2006.196.07:31:09.88#ibcon#about to read 6, iclass 13, count 0 2006.196.07:31:09.88#ibcon#read 6, iclass 13, count 0 2006.196.07:31:09.88#ibcon#end of sib2, iclass 13, count 0 2006.196.07:31:09.88#ibcon#*mode == 0, iclass 13, count 0 2006.196.07:31:09.88#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.196.07:31:09.88#ibcon#[26=FRQ=06,772.99\r\n] 2006.196.07:31:09.88#ibcon#*before write, iclass 13, count 0 2006.196.07:31:09.88#ibcon#enter sib2, iclass 13, count 0 2006.196.07:31:09.88#ibcon#flushed, iclass 13, count 0 2006.196.07:31:09.88#ibcon#about to write, iclass 13, count 0 2006.196.07:31:09.88#ibcon#wrote, iclass 13, count 0 2006.196.07:31:09.88#ibcon#about to read 3, iclass 13, count 0 2006.196.07:31:09.92#ibcon#read 3, iclass 13, count 0 2006.196.07:31:09.92#ibcon#about to read 4, iclass 13, count 0 2006.196.07:31:09.92#ibcon#read 4, iclass 13, count 0 2006.196.07:31:09.92#ibcon#about to read 5, iclass 13, count 0 2006.196.07:31:09.92#ibcon#read 5, iclass 13, count 0 2006.196.07:31:09.92#ibcon#about to read 6, iclass 13, count 0 2006.196.07:31:09.92#ibcon#read 6, iclass 13, count 0 2006.196.07:31:09.92#ibcon#end of sib2, iclass 13, count 0 2006.196.07:31:09.92#ibcon#*after write, iclass 13, count 0 2006.196.07:31:09.92#ibcon#*before return 0, iclass 13, count 0 2006.196.07:31:09.92#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.196.07:31:09.92#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.196.07:31:09.92#ibcon#about to clear, iclass 13 cls_cnt 0 2006.196.07:31:09.92#ibcon#cleared, iclass 13 cls_cnt 0 2006.196.07:31:09.92$vc4f8/va=6,6 2006.196.07:31:09.92#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.196.07:31:09.92#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.196.07:31:09.92#ibcon#ireg 11 cls_cnt 2 2006.196.07:31:09.92#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.196.07:31:09.98#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.196.07:31:09.98#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.196.07:31:09.98#ibcon#enter wrdev, iclass 15, count 2 2006.196.07:31:09.98#ibcon#first serial, iclass 15, count 2 2006.196.07:31:09.98#ibcon#enter sib2, iclass 15, count 2 2006.196.07:31:09.98#ibcon#flushed, iclass 15, count 2 2006.196.07:31:09.98#ibcon#about to write, iclass 15, count 2 2006.196.07:31:09.98#ibcon#wrote, iclass 15, count 2 2006.196.07:31:09.98#ibcon#about to read 3, iclass 15, count 2 2006.196.07:31:10.00#ibcon#read 3, iclass 15, count 2 2006.196.07:31:10.00#ibcon#about to read 4, iclass 15, count 2 2006.196.07:31:10.00#ibcon#read 4, iclass 15, count 2 2006.196.07:31:10.00#ibcon#about to read 5, iclass 15, count 2 2006.196.07:31:10.00#ibcon#read 5, iclass 15, count 2 2006.196.07:31:10.00#ibcon#about to read 6, iclass 15, count 2 2006.196.07:31:10.00#ibcon#read 6, iclass 15, count 2 2006.196.07:31:10.00#ibcon#end of sib2, iclass 15, count 2 2006.196.07:31:10.00#ibcon#*mode == 0, iclass 15, count 2 2006.196.07:31:10.00#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.196.07:31:10.00#ibcon#[25=AT06-06\r\n] 2006.196.07:31:10.00#ibcon#*before write, iclass 15, count 2 2006.196.07:31:10.00#ibcon#enter sib2, iclass 15, count 2 2006.196.07:31:10.00#ibcon#flushed, iclass 15, count 2 2006.196.07:31:10.00#ibcon#about to write, iclass 15, count 2 2006.196.07:31:10.00#ibcon#wrote, iclass 15, count 2 2006.196.07:31:10.00#ibcon#about to read 3, iclass 15, count 2 2006.196.07:31:10.03#ibcon#read 3, iclass 15, count 2 2006.196.07:31:10.03#ibcon#about to read 4, iclass 15, count 2 2006.196.07:31:10.03#ibcon#read 4, iclass 15, count 2 2006.196.07:31:10.03#ibcon#about to read 5, iclass 15, count 2 2006.196.07:31:10.03#ibcon#read 5, iclass 15, count 2 2006.196.07:31:10.03#ibcon#about to read 6, iclass 15, count 2 2006.196.07:31:10.03#ibcon#read 6, iclass 15, count 2 2006.196.07:31:10.03#ibcon#end of sib2, iclass 15, count 2 2006.196.07:31:10.03#ibcon#*after write, iclass 15, count 2 2006.196.07:31:10.03#ibcon#*before return 0, iclass 15, count 2 2006.196.07:31:10.03#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.196.07:31:10.03#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.196.07:31:10.03#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.196.07:31:10.03#ibcon#ireg 7 cls_cnt 0 2006.196.07:31:10.03#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.196.07:31:10.15#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.196.07:31:10.15#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.196.07:31:10.15#ibcon#enter wrdev, iclass 15, count 0 2006.196.07:31:10.15#ibcon#first serial, iclass 15, count 0 2006.196.07:31:10.15#ibcon#enter sib2, iclass 15, count 0 2006.196.07:31:10.15#ibcon#flushed, iclass 15, count 0 2006.196.07:31:10.15#ibcon#about to write, iclass 15, count 0 2006.196.07:31:10.15#ibcon#wrote, iclass 15, count 0 2006.196.07:31:10.15#ibcon#about to read 3, iclass 15, count 0 2006.196.07:31:10.17#ibcon#read 3, iclass 15, count 0 2006.196.07:31:10.17#ibcon#about to read 4, iclass 15, count 0 2006.196.07:31:10.17#ibcon#read 4, iclass 15, count 0 2006.196.07:31:10.17#ibcon#about to read 5, iclass 15, count 0 2006.196.07:31:10.17#ibcon#read 5, iclass 15, count 0 2006.196.07:31:10.17#ibcon#about to read 6, iclass 15, count 0 2006.196.07:31:10.17#ibcon#read 6, iclass 15, count 0 2006.196.07:31:10.17#ibcon#end of sib2, iclass 15, count 0 2006.196.07:31:10.17#ibcon#*mode == 0, iclass 15, count 0 2006.196.07:31:10.17#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.196.07:31:10.17#ibcon#[25=USB\r\n] 2006.196.07:31:10.17#ibcon#*before write, iclass 15, count 0 2006.196.07:31:10.17#ibcon#enter sib2, iclass 15, count 0 2006.196.07:31:10.17#ibcon#flushed, iclass 15, count 0 2006.196.07:31:10.17#ibcon#about to write, iclass 15, count 0 2006.196.07:31:10.17#ibcon#wrote, iclass 15, count 0 2006.196.07:31:10.17#ibcon#about to read 3, iclass 15, count 0 2006.196.07:31:10.20#ibcon#read 3, iclass 15, count 0 2006.196.07:31:10.20#ibcon#about to read 4, iclass 15, count 0 2006.196.07:31:10.20#ibcon#read 4, iclass 15, count 0 2006.196.07:31:10.20#ibcon#about to read 5, iclass 15, count 0 2006.196.07:31:10.20#ibcon#read 5, iclass 15, count 0 2006.196.07:31:10.20#ibcon#about to read 6, iclass 15, count 0 2006.196.07:31:10.20#ibcon#read 6, iclass 15, count 0 2006.196.07:31:10.20#ibcon#end of sib2, iclass 15, count 0 2006.196.07:31:10.20#ibcon#*after write, iclass 15, count 0 2006.196.07:31:10.20#ibcon#*before return 0, iclass 15, count 0 2006.196.07:31:10.20#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.196.07:31:10.20#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.196.07:31:10.20#ibcon#about to clear, iclass 15 cls_cnt 0 2006.196.07:31:10.20#ibcon#cleared, iclass 15 cls_cnt 0 2006.196.07:31:10.20$vc4f8/valo=7,832.99 2006.196.07:31:10.20#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.196.07:31:10.20#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.196.07:31:10.20#ibcon#ireg 17 cls_cnt 0 2006.196.07:31:10.20#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.196.07:31:10.20#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.196.07:31:10.20#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.196.07:31:10.20#ibcon#enter wrdev, iclass 17, count 0 2006.196.07:31:10.20#ibcon#first serial, iclass 17, count 0 2006.196.07:31:10.20#ibcon#enter sib2, iclass 17, count 0 2006.196.07:31:10.20#ibcon#flushed, iclass 17, count 0 2006.196.07:31:10.20#ibcon#about to write, iclass 17, count 0 2006.196.07:31:10.20#ibcon#wrote, iclass 17, count 0 2006.196.07:31:10.20#ibcon#about to read 3, iclass 17, count 0 2006.196.07:31:10.22#ibcon#read 3, iclass 17, count 0 2006.196.07:31:10.22#ibcon#about to read 4, iclass 17, count 0 2006.196.07:31:10.22#ibcon#read 4, iclass 17, count 0 2006.196.07:31:10.22#ibcon#about to read 5, iclass 17, count 0 2006.196.07:31:10.22#ibcon#read 5, iclass 17, count 0 2006.196.07:31:10.22#ibcon#about to read 6, iclass 17, count 0 2006.196.07:31:10.22#ibcon#read 6, iclass 17, count 0 2006.196.07:31:10.22#ibcon#end of sib2, iclass 17, count 0 2006.196.07:31:10.22#ibcon#*mode == 0, iclass 17, count 0 2006.196.07:31:10.22#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.196.07:31:10.22#ibcon#[26=FRQ=07,832.99\r\n] 2006.196.07:31:10.22#ibcon#*before write, iclass 17, count 0 2006.196.07:31:10.22#ibcon#enter sib2, iclass 17, count 0 2006.196.07:31:10.22#ibcon#flushed, iclass 17, count 0 2006.196.07:31:10.22#ibcon#about to write, iclass 17, count 0 2006.196.07:31:10.22#ibcon#wrote, iclass 17, count 0 2006.196.07:31:10.22#ibcon#about to read 3, iclass 17, count 0 2006.196.07:31:10.26#ibcon#read 3, iclass 17, count 0 2006.196.07:31:10.26#ibcon#about to read 4, iclass 17, count 0 2006.196.07:31:10.26#ibcon#read 4, iclass 17, count 0 2006.196.07:31:10.26#ibcon#about to read 5, iclass 17, count 0 2006.196.07:31:10.26#ibcon#read 5, iclass 17, count 0 2006.196.07:31:10.26#ibcon#about to read 6, iclass 17, count 0 2006.196.07:31:10.26#ibcon#read 6, iclass 17, count 0 2006.196.07:31:10.26#ibcon#end of sib2, iclass 17, count 0 2006.196.07:31:10.26#ibcon#*after write, iclass 17, count 0 2006.196.07:31:10.26#ibcon#*before return 0, iclass 17, count 0 2006.196.07:31:10.26#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.196.07:31:10.26#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.196.07:31:10.26#ibcon#about to clear, iclass 17 cls_cnt 0 2006.196.07:31:10.26#ibcon#cleared, iclass 17 cls_cnt 0 2006.196.07:31:10.26$vc4f8/va=7,6 2006.196.07:31:10.26#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.196.07:31:10.26#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.196.07:31:10.26#ibcon#ireg 11 cls_cnt 2 2006.196.07:31:10.26#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.196.07:31:10.32#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.196.07:31:10.32#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.196.07:31:10.32#ibcon#enter wrdev, iclass 19, count 2 2006.196.07:31:10.32#ibcon#first serial, iclass 19, count 2 2006.196.07:31:10.32#ibcon#enter sib2, iclass 19, count 2 2006.196.07:31:10.32#ibcon#flushed, iclass 19, count 2 2006.196.07:31:10.32#ibcon#about to write, iclass 19, count 2 2006.196.07:31:10.32#ibcon#wrote, iclass 19, count 2 2006.196.07:31:10.32#ibcon#about to read 3, iclass 19, count 2 2006.196.07:31:10.34#ibcon#read 3, iclass 19, count 2 2006.196.07:31:10.34#ibcon#about to read 4, iclass 19, count 2 2006.196.07:31:10.34#ibcon#read 4, iclass 19, count 2 2006.196.07:31:10.34#ibcon#about to read 5, iclass 19, count 2 2006.196.07:31:10.34#ibcon#read 5, iclass 19, count 2 2006.196.07:31:10.34#ibcon#about to read 6, iclass 19, count 2 2006.196.07:31:10.34#ibcon#read 6, iclass 19, count 2 2006.196.07:31:10.34#ibcon#end of sib2, iclass 19, count 2 2006.196.07:31:10.34#ibcon#*mode == 0, iclass 19, count 2 2006.196.07:31:10.34#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.196.07:31:10.34#ibcon#[25=AT07-06\r\n] 2006.196.07:31:10.34#ibcon#*before write, iclass 19, count 2 2006.196.07:31:10.34#ibcon#enter sib2, iclass 19, count 2 2006.196.07:31:10.34#ibcon#flushed, iclass 19, count 2 2006.196.07:31:10.34#ibcon#about to write, iclass 19, count 2 2006.196.07:31:10.34#ibcon#wrote, iclass 19, count 2 2006.196.07:31:10.34#ibcon#about to read 3, iclass 19, count 2 2006.196.07:31:10.37#ibcon#read 3, iclass 19, count 2 2006.196.07:31:10.37#ibcon#about to read 4, iclass 19, count 2 2006.196.07:31:10.37#ibcon#read 4, iclass 19, count 2 2006.196.07:31:10.37#ibcon#about to read 5, iclass 19, count 2 2006.196.07:31:10.37#ibcon#read 5, iclass 19, count 2 2006.196.07:31:10.37#ibcon#about to read 6, iclass 19, count 2 2006.196.07:31:10.37#ibcon#read 6, iclass 19, count 2 2006.196.07:31:10.37#ibcon#end of sib2, iclass 19, count 2 2006.196.07:31:10.37#ibcon#*after write, iclass 19, count 2 2006.196.07:31:10.37#ibcon#*before return 0, iclass 19, count 2 2006.196.07:31:10.37#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.196.07:31:10.37#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.196.07:31:10.37#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.196.07:31:10.37#ibcon#ireg 7 cls_cnt 0 2006.196.07:31:10.37#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.196.07:31:10.49#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.196.07:31:10.49#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.196.07:31:10.49#ibcon#enter wrdev, iclass 19, count 0 2006.196.07:31:10.49#ibcon#first serial, iclass 19, count 0 2006.196.07:31:10.49#ibcon#enter sib2, iclass 19, count 0 2006.196.07:31:10.49#ibcon#flushed, iclass 19, count 0 2006.196.07:31:10.49#ibcon#about to write, iclass 19, count 0 2006.196.07:31:10.49#ibcon#wrote, iclass 19, count 0 2006.196.07:31:10.49#ibcon#about to read 3, iclass 19, count 0 2006.196.07:31:10.51#ibcon#read 3, iclass 19, count 0 2006.196.07:31:10.51#ibcon#about to read 4, iclass 19, count 0 2006.196.07:31:10.51#ibcon#read 4, iclass 19, count 0 2006.196.07:31:10.51#ibcon#about to read 5, iclass 19, count 0 2006.196.07:31:10.51#ibcon#read 5, iclass 19, count 0 2006.196.07:31:10.51#ibcon#about to read 6, iclass 19, count 0 2006.196.07:31:10.51#ibcon#read 6, iclass 19, count 0 2006.196.07:31:10.51#ibcon#end of sib2, iclass 19, count 0 2006.196.07:31:10.51#ibcon#*mode == 0, iclass 19, count 0 2006.196.07:31:10.51#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.196.07:31:10.51#ibcon#[25=USB\r\n] 2006.196.07:31:10.51#ibcon#*before write, iclass 19, count 0 2006.196.07:31:10.51#ibcon#enter sib2, iclass 19, count 0 2006.196.07:31:10.51#ibcon#flushed, iclass 19, count 0 2006.196.07:31:10.51#ibcon#about to write, iclass 19, count 0 2006.196.07:31:10.51#ibcon#wrote, iclass 19, count 0 2006.196.07:31:10.51#ibcon#about to read 3, iclass 19, count 0 2006.196.07:31:10.54#ibcon#read 3, iclass 19, count 0 2006.196.07:31:10.54#ibcon#about to read 4, iclass 19, count 0 2006.196.07:31:10.54#ibcon#read 4, iclass 19, count 0 2006.196.07:31:10.54#ibcon#about to read 5, iclass 19, count 0 2006.196.07:31:10.54#ibcon#read 5, iclass 19, count 0 2006.196.07:31:10.54#ibcon#about to read 6, iclass 19, count 0 2006.196.07:31:10.54#ibcon#read 6, iclass 19, count 0 2006.196.07:31:10.54#ibcon#end of sib2, iclass 19, count 0 2006.196.07:31:10.54#ibcon#*after write, iclass 19, count 0 2006.196.07:31:10.54#ibcon#*before return 0, iclass 19, count 0 2006.196.07:31:10.54#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.196.07:31:10.54#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.196.07:31:10.54#ibcon#about to clear, iclass 19 cls_cnt 0 2006.196.07:31:10.54#ibcon#cleared, iclass 19 cls_cnt 0 2006.196.07:31:10.54$vc4f8/valo=8,852.99 2006.196.07:31:10.54#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.196.07:31:10.54#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.196.07:31:10.54#ibcon#ireg 17 cls_cnt 0 2006.196.07:31:10.54#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.196.07:31:10.54#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.196.07:31:10.54#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.196.07:31:10.54#ibcon#enter wrdev, iclass 21, count 0 2006.196.07:31:10.54#ibcon#first serial, iclass 21, count 0 2006.196.07:31:10.54#ibcon#enter sib2, iclass 21, count 0 2006.196.07:31:10.54#ibcon#flushed, iclass 21, count 0 2006.196.07:31:10.54#ibcon#about to write, iclass 21, count 0 2006.196.07:31:10.54#ibcon#wrote, iclass 21, count 0 2006.196.07:31:10.54#ibcon#about to read 3, iclass 21, count 0 2006.196.07:31:10.56#ibcon#read 3, iclass 21, count 0 2006.196.07:31:10.56#ibcon#about to read 4, iclass 21, count 0 2006.196.07:31:10.56#ibcon#read 4, iclass 21, count 0 2006.196.07:31:10.56#ibcon#about to read 5, iclass 21, count 0 2006.196.07:31:10.56#ibcon#read 5, iclass 21, count 0 2006.196.07:31:10.56#ibcon#about to read 6, iclass 21, count 0 2006.196.07:31:10.56#ibcon#read 6, iclass 21, count 0 2006.196.07:31:10.56#ibcon#end of sib2, iclass 21, count 0 2006.196.07:31:10.56#ibcon#*mode == 0, iclass 21, count 0 2006.196.07:31:10.56#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.196.07:31:10.56#ibcon#[26=FRQ=08,852.99\r\n] 2006.196.07:31:10.56#ibcon#*before write, iclass 21, count 0 2006.196.07:31:10.56#ibcon#enter sib2, iclass 21, count 0 2006.196.07:31:10.56#ibcon#flushed, iclass 21, count 0 2006.196.07:31:10.56#ibcon#about to write, iclass 21, count 0 2006.196.07:31:10.56#ibcon#wrote, iclass 21, count 0 2006.196.07:31:10.56#ibcon#about to read 3, iclass 21, count 0 2006.196.07:31:10.60#ibcon#read 3, iclass 21, count 0 2006.196.07:31:10.60#ibcon#about to read 4, iclass 21, count 0 2006.196.07:31:10.60#ibcon#read 4, iclass 21, count 0 2006.196.07:31:10.60#ibcon#about to read 5, iclass 21, count 0 2006.196.07:31:10.60#ibcon#read 5, iclass 21, count 0 2006.196.07:31:10.60#ibcon#about to read 6, iclass 21, count 0 2006.196.07:31:10.60#ibcon#read 6, iclass 21, count 0 2006.196.07:31:10.60#ibcon#end of sib2, iclass 21, count 0 2006.196.07:31:10.60#ibcon#*after write, iclass 21, count 0 2006.196.07:31:10.60#ibcon#*before return 0, iclass 21, count 0 2006.196.07:31:10.60#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.196.07:31:10.60#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.196.07:31:10.60#ibcon#about to clear, iclass 21 cls_cnt 0 2006.196.07:31:10.60#ibcon#cleared, iclass 21 cls_cnt 0 2006.196.07:31:10.60$vc4f8/va=8,7 2006.196.07:31:10.60#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.196.07:31:10.60#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.196.07:31:10.60#ibcon#ireg 11 cls_cnt 2 2006.196.07:31:10.60#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.196.07:31:10.66#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.196.07:31:10.66#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.196.07:31:10.66#ibcon#enter wrdev, iclass 23, count 2 2006.196.07:31:10.66#ibcon#first serial, iclass 23, count 2 2006.196.07:31:10.66#ibcon#enter sib2, iclass 23, count 2 2006.196.07:31:10.66#ibcon#flushed, iclass 23, count 2 2006.196.07:31:10.66#ibcon#about to write, iclass 23, count 2 2006.196.07:31:10.66#ibcon#wrote, iclass 23, count 2 2006.196.07:31:10.66#ibcon#about to read 3, iclass 23, count 2 2006.196.07:31:10.68#ibcon#read 3, iclass 23, count 2 2006.196.07:31:10.68#ibcon#about to read 4, iclass 23, count 2 2006.196.07:31:10.68#ibcon#read 4, iclass 23, count 2 2006.196.07:31:10.68#ibcon#about to read 5, iclass 23, count 2 2006.196.07:31:10.68#ibcon#read 5, iclass 23, count 2 2006.196.07:31:10.68#ibcon#about to read 6, iclass 23, count 2 2006.196.07:31:10.68#ibcon#read 6, iclass 23, count 2 2006.196.07:31:10.68#ibcon#end of sib2, iclass 23, count 2 2006.196.07:31:10.68#ibcon#*mode == 0, iclass 23, count 2 2006.196.07:31:10.68#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.196.07:31:10.68#ibcon#[25=AT08-07\r\n] 2006.196.07:31:10.68#ibcon#*before write, iclass 23, count 2 2006.196.07:31:10.68#ibcon#enter sib2, iclass 23, count 2 2006.196.07:31:10.68#ibcon#flushed, iclass 23, count 2 2006.196.07:31:10.68#ibcon#about to write, iclass 23, count 2 2006.196.07:31:10.68#ibcon#wrote, iclass 23, count 2 2006.196.07:31:10.68#ibcon#about to read 3, iclass 23, count 2 2006.196.07:31:10.72#ibcon#read 3, iclass 23, count 2 2006.196.07:31:10.72#ibcon#about to read 4, iclass 23, count 2 2006.196.07:31:10.72#ibcon#read 4, iclass 23, count 2 2006.196.07:31:10.72#ibcon#about to read 5, iclass 23, count 2 2006.196.07:31:10.72#ibcon#read 5, iclass 23, count 2 2006.196.07:31:10.72#ibcon#about to read 6, iclass 23, count 2 2006.196.07:31:10.72#ibcon#read 6, iclass 23, count 2 2006.196.07:31:10.72#ibcon#end of sib2, iclass 23, count 2 2006.196.07:31:10.72#ibcon#*after write, iclass 23, count 2 2006.196.07:31:10.72#ibcon#*before return 0, iclass 23, count 2 2006.196.07:31:10.72#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.196.07:31:10.72#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.196.07:31:10.72#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.196.07:31:10.72#ibcon#ireg 7 cls_cnt 0 2006.196.07:31:10.72#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.196.07:31:10.84#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.196.07:31:10.84#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.196.07:31:10.84#ibcon#enter wrdev, iclass 23, count 0 2006.196.07:31:10.84#ibcon#first serial, iclass 23, count 0 2006.196.07:31:10.84#ibcon#enter sib2, iclass 23, count 0 2006.196.07:31:10.84#ibcon#flushed, iclass 23, count 0 2006.196.07:31:10.84#ibcon#about to write, iclass 23, count 0 2006.196.07:31:10.84#ibcon#wrote, iclass 23, count 0 2006.196.07:31:10.84#ibcon#about to read 3, iclass 23, count 0 2006.196.07:31:10.86#ibcon#read 3, iclass 23, count 0 2006.196.07:31:10.86#ibcon#about to read 4, iclass 23, count 0 2006.196.07:31:10.86#ibcon#read 4, iclass 23, count 0 2006.196.07:31:10.86#ibcon#about to read 5, iclass 23, count 0 2006.196.07:31:10.86#ibcon#read 5, iclass 23, count 0 2006.196.07:31:10.86#ibcon#about to read 6, iclass 23, count 0 2006.196.07:31:10.86#ibcon#read 6, iclass 23, count 0 2006.196.07:31:10.86#ibcon#end of sib2, iclass 23, count 0 2006.196.07:31:10.86#ibcon#*mode == 0, iclass 23, count 0 2006.196.07:31:10.86#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.196.07:31:10.86#ibcon#[25=USB\r\n] 2006.196.07:31:10.86#ibcon#*before write, iclass 23, count 0 2006.196.07:31:10.86#ibcon#enter sib2, iclass 23, count 0 2006.196.07:31:10.86#ibcon#flushed, iclass 23, count 0 2006.196.07:31:10.86#ibcon#about to write, iclass 23, count 0 2006.196.07:31:10.86#ibcon#wrote, iclass 23, count 0 2006.196.07:31:10.86#ibcon#about to read 3, iclass 23, count 0 2006.196.07:31:10.89#ibcon#read 3, iclass 23, count 0 2006.196.07:31:10.89#ibcon#about to read 4, iclass 23, count 0 2006.196.07:31:10.89#ibcon#read 4, iclass 23, count 0 2006.196.07:31:10.89#ibcon#about to read 5, iclass 23, count 0 2006.196.07:31:10.89#ibcon#read 5, iclass 23, count 0 2006.196.07:31:10.89#ibcon#about to read 6, iclass 23, count 0 2006.196.07:31:10.89#ibcon#read 6, iclass 23, count 0 2006.196.07:31:10.89#ibcon#end of sib2, iclass 23, count 0 2006.196.07:31:10.89#ibcon#*after write, iclass 23, count 0 2006.196.07:31:10.89#ibcon#*before return 0, iclass 23, count 0 2006.196.07:31:10.89#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.196.07:31:10.89#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.196.07:31:10.89#ibcon#about to clear, iclass 23 cls_cnt 0 2006.196.07:31:10.89#ibcon#cleared, iclass 23 cls_cnt 0 2006.196.07:31:10.89$vc4f8/vblo=1,632.99 2006.196.07:31:10.89#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.196.07:31:10.89#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.196.07:31:10.89#ibcon#ireg 17 cls_cnt 0 2006.196.07:31:10.89#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.196.07:31:10.89#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.196.07:31:10.89#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.196.07:31:10.89#ibcon#enter wrdev, iclass 25, count 0 2006.196.07:31:10.89#ibcon#first serial, iclass 25, count 0 2006.196.07:31:10.89#ibcon#enter sib2, iclass 25, count 0 2006.196.07:31:10.89#ibcon#flushed, iclass 25, count 0 2006.196.07:31:10.89#ibcon#about to write, iclass 25, count 0 2006.196.07:31:10.89#ibcon#wrote, iclass 25, count 0 2006.196.07:31:10.89#ibcon#about to read 3, iclass 25, count 0 2006.196.07:31:10.91#ibcon#read 3, iclass 25, count 0 2006.196.07:31:10.91#ibcon#about to read 4, iclass 25, count 0 2006.196.07:31:10.91#ibcon#read 4, iclass 25, count 0 2006.196.07:31:10.91#ibcon#about to read 5, iclass 25, count 0 2006.196.07:31:10.91#ibcon#read 5, iclass 25, count 0 2006.196.07:31:10.91#ibcon#about to read 6, iclass 25, count 0 2006.196.07:31:10.91#ibcon#read 6, iclass 25, count 0 2006.196.07:31:10.91#ibcon#end of sib2, iclass 25, count 0 2006.196.07:31:10.91#ibcon#*mode == 0, iclass 25, count 0 2006.196.07:31:10.91#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.196.07:31:10.91#ibcon#[28=FRQ=01,632.99\r\n] 2006.196.07:31:10.91#ibcon#*before write, iclass 25, count 0 2006.196.07:31:10.91#ibcon#enter sib2, iclass 25, count 0 2006.196.07:31:10.91#ibcon#flushed, iclass 25, count 0 2006.196.07:31:10.91#ibcon#about to write, iclass 25, count 0 2006.196.07:31:10.91#ibcon#wrote, iclass 25, count 0 2006.196.07:31:10.91#ibcon#about to read 3, iclass 25, count 0 2006.196.07:31:10.95#ibcon#read 3, iclass 25, count 0 2006.196.07:31:10.95#ibcon#about to read 4, iclass 25, count 0 2006.196.07:31:10.95#ibcon#read 4, iclass 25, count 0 2006.196.07:31:10.95#ibcon#about to read 5, iclass 25, count 0 2006.196.07:31:10.95#ibcon#read 5, iclass 25, count 0 2006.196.07:31:10.95#ibcon#about to read 6, iclass 25, count 0 2006.196.07:31:10.95#ibcon#read 6, iclass 25, count 0 2006.196.07:31:10.95#ibcon#end of sib2, iclass 25, count 0 2006.196.07:31:10.95#ibcon#*after write, iclass 25, count 0 2006.196.07:31:10.95#ibcon#*before return 0, iclass 25, count 0 2006.196.07:31:10.95#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.196.07:31:10.95#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.196.07:31:10.95#ibcon#about to clear, iclass 25 cls_cnt 0 2006.196.07:31:10.95#ibcon#cleared, iclass 25 cls_cnt 0 2006.196.07:31:10.95$vc4f8/vb=1,4 2006.196.07:31:10.95#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.196.07:31:10.95#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.196.07:31:10.95#ibcon#ireg 11 cls_cnt 2 2006.196.07:31:10.95#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.196.07:31:10.95#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.196.07:31:10.95#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.196.07:31:10.95#ibcon#enter wrdev, iclass 27, count 2 2006.196.07:31:10.95#ibcon#first serial, iclass 27, count 2 2006.196.07:31:10.95#ibcon#enter sib2, iclass 27, count 2 2006.196.07:31:10.95#ibcon#flushed, iclass 27, count 2 2006.196.07:31:10.95#ibcon#about to write, iclass 27, count 2 2006.196.07:31:10.95#ibcon#wrote, iclass 27, count 2 2006.196.07:31:10.95#ibcon#about to read 3, iclass 27, count 2 2006.196.07:31:10.97#ibcon#read 3, iclass 27, count 2 2006.196.07:31:10.97#ibcon#about to read 4, iclass 27, count 2 2006.196.07:31:10.97#ibcon#read 4, iclass 27, count 2 2006.196.07:31:10.97#ibcon#about to read 5, iclass 27, count 2 2006.196.07:31:10.97#ibcon#read 5, iclass 27, count 2 2006.196.07:31:10.97#ibcon#about to read 6, iclass 27, count 2 2006.196.07:31:10.97#ibcon#read 6, iclass 27, count 2 2006.196.07:31:10.97#ibcon#end of sib2, iclass 27, count 2 2006.196.07:31:10.97#ibcon#*mode == 0, iclass 27, count 2 2006.196.07:31:10.97#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.196.07:31:10.97#ibcon#[27=AT01-04\r\n] 2006.196.07:31:10.97#ibcon#*before write, iclass 27, count 2 2006.196.07:31:10.97#ibcon#enter sib2, iclass 27, count 2 2006.196.07:31:10.97#ibcon#flushed, iclass 27, count 2 2006.196.07:31:10.97#ibcon#about to write, iclass 27, count 2 2006.196.07:31:10.97#ibcon#wrote, iclass 27, count 2 2006.196.07:31:10.97#ibcon#about to read 3, iclass 27, count 2 2006.196.07:31:11.00#ibcon#read 3, iclass 27, count 2 2006.196.07:31:11.00#ibcon#about to read 4, iclass 27, count 2 2006.196.07:31:11.00#ibcon#read 4, iclass 27, count 2 2006.196.07:31:11.00#ibcon#about to read 5, iclass 27, count 2 2006.196.07:31:11.00#ibcon#read 5, iclass 27, count 2 2006.196.07:31:11.00#ibcon#about to read 6, iclass 27, count 2 2006.196.07:31:11.00#ibcon#read 6, iclass 27, count 2 2006.196.07:31:11.00#ibcon#end of sib2, iclass 27, count 2 2006.196.07:31:11.00#ibcon#*after write, iclass 27, count 2 2006.196.07:31:11.00#ibcon#*before return 0, iclass 27, count 2 2006.196.07:31:11.00#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.196.07:31:11.00#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.196.07:31:11.00#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.196.07:31:11.00#ibcon#ireg 7 cls_cnt 0 2006.196.07:31:11.00#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.196.07:31:11.12#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.196.07:31:11.12#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.196.07:31:11.12#ibcon#enter wrdev, iclass 27, count 0 2006.196.07:31:11.12#ibcon#first serial, iclass 27, count 0 2006.196.07:31:11.12#ibcon#enter sib2, iclass 27, count 0 2006.196.07:31:11.12#ibcon#flushed, iclass 27, count 0 2006.196.07:31:11.12#ibcon#about to write, iclass 27, count 0 2006.196.07:31:11.12#ibcon#wrote, iclass 27, count 0 2006.196.07:31:11.12#ibcon#about to read 3, iclass 27, count 0 2006.196.07:31:11.14#ibcon#read 3, iclass 27, count 0 2006.196.07:31:11.14#ibcon#about to read 4, iclass 27, count 0 2006.196.07:31:11.14#ibcon#read 4, iclass 27, count 0 2006.196.07:31:11.14#ibcon#about to read 5, iclass 27, count 0 2006.196.07:31:11.14#ibcon#read 5, iclass 27, count 0 2006.196.07:31:11.14#ibcon#about to read 6, iclass 27, count 0 2006.196.07:31:11.14#ibcon#read 6, iclass 27, count 0 2006.196.07:31:11.14#ibcon#end of sib2, iclass 27, count 0 2006.196.07:31:11.14#ibcon#*mode == 0, iclass 27, count 0 2006.196.07:31:11.14#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.196.07:31:11.14#ibcon#[27=USB\r\n] 2006.196.07:31:11.14#ibcon#*before write, iclass 27, count 0 2006.196.07:31:11.14#ibcon#enter sib2, iclass 27, count 0 2006.196.07:31:11.14#ibcon#flushed, iclass 27, count 0 2006.196.07:31:11.14#ibcon#about to write, iclass 27, count 0 2006.196.07:31:11.14#ibcon#wrote, iclass 27, count 0 2006.196.07:31:11.14#ibcon#about to read 3, iclass 27, count 0 2006.196.07:31:11.17#ibcon#read 3, iclass 27, count 0 2006.196.07:31:11.17#ibcon#about to read 4, iclass 27, count 0 2006.196.07:31:11.17#ibcon#read 4, iclass 27, count 0 2006.196.07:31:11.17#ibcon#about to read 5, iclass 27, count 0 2006.196.07:31:11.17#ibcon#read 5, iclass 27, count 0 2006.196.07:31:11.17#ibcon#about to read 6, iclass 27, count 0 2006.196.07:31:11.17#ibcon#read 6, iclass 27, count 0 2006.196.07:31:11.17#ibcon#end of sib2, iclass 27, count 0 2006.196.07:31:11.17#ibcon#*after write, iclass 27, count 0 2006.196.07:31:11.17#ibcon#*before return 0, iclass 27, count 0 2006.196.07:31:11.17#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.196.07:31:11.17#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.196.07:31:11.17#ibcon#about to clear, iclass 27 cls_cnt 0 2006.196.07:31:11.17#ibcon#cleared, iclass 27 cls_cnt 0 2006.196.07:31:11.17$vc4f8/vblo=2,640.99 2006.196.07:31:11.17#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.196.07:31:11.17#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.196.07:31:11.17#ibcon#ireg 17 cls_cnt 0 2006.196.07:31:11.17#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.196.07:31:11.17#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.196.07:31:11.17#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.196.07:31:11.17#ibcon#enter wrdev, iclass 29, count 0 2006.196.07:31:11.17#ibcon#first serial, iclass 29, count 0 2006.196.07:31:11.17#ibcon#enter sib2, iclass 29, count 0 2006.196.07:31:11.17#ibcon#flushed, iclass 29, count 0 2006.196.07:31:11.17#ibcon#about to write, iclass 29, count 0 2006.196.07:31:11.17#ibcon#wrote, iclass 29, count 0 2006.196.07:31:11.17#ibcon#about to read 3, iclass 29, count 0 2006.196.07:31:11.19#ibcon#read 3, iclass 29, count 0 2006.196.07:31:11.19#ibcon#about to read 4, iclass 29, count 0 2006.196.07:31:11.19#ibcon#read 4, iclass 29, count 0 2006.196.07:31:11.19#ibcon#about to read 5, iclass 29, count 0 2006.196.07:31:11.19#ibcon#read 5, iclass 29, count 0 2006.196.07:31:11.19#ibcon#about to read 6, iclass 29, count 0 2006.196.07:31:11.19#ibcon#read 6, iclass 29, count 0 2006.196.07:31:11.19#ibcon#end of sib2, iclass 29, count 0 2006.196.07:31:11.19#ibcon#*mode == 0, iclass 29, count 0 2006.196.07:31:11.19#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.196.07:31:11.19#ibcon#[28=FRQ=02,640.99\r\n] 2006.196.07:31:11.19#ibcon#*before write, iclass 29, count 0 2006.196.07:31:11.19#ibcon#enter sib2, iclass 29, count 0 2006.196.07:31:11.19#ibcon#flushed, iclass 29, count 0 2006.196.07:31:11.19#ibcon#about to write, iclass 29, count 0 2006.196.07:31:11.19#ibcon#wrote, iclass 29, count 0 2006.196.07:31:11.19#ibcon#about to read 3, iclass 29, count 0 2006.196.07:31:11.23#ibcon#read 3, iclass 29, count 0 2006.196.07:31:11.23#ibcon#about to read 4, iclass 29, count 0 2006.196.07:31:11.23#ibcon#read 4, iclass 29, count 0 2006.196.07:31:11.23#ibcon#about to read 5, iclass 29, count 0 2006.196.07:31:11.23#ibcon#read 5, iclass 29, count 0 2006.196.07:31:11.23#ibcon#about to read 6, iclass 29, count 0 2006.196.07:31:11.23#ibcon#read 6, iclass 29, count 0 2006.196.07:31:11.23#ibcon#end of sib2, iclass 29, count 0 2006.196.07:31:11.23#ibcon#*after write, iclass 29, count 0 2006.196.07:31:11.23#ibcon#*before return 0, iclass 29, count 0 2006.196.07:31:11.23#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.196.07:31:11.23#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.196.07:31:11.23#ibcon#about to clear, iclass 29 cls_cnt 0 2006.196.07:31:11.23#ibcon#cleared, iclass 29 cls_cnt 0 2006.196.07:31:11.23$vc4f8/vb=2,4 2006.196.07:31:11.23#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.196.07:31:11.23#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.196.07:31:11.23#ibcon#ireg 11 cls_cnt 2 2006.196.07:31:11.23#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.196.07:31:11.29#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.196.07:31:11.29#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.196.07:31:11.29#ibcon#enter wrdev, iclass 31, count 2 2006.196.07:31:11.29#ibcon#first serial, iclass 31, count 2 2006.196.07:31:11.29#ibcon#enter sib2, iclass 31, count 2 2006.196.07:31:11.29#ibcon#flushed, iclass 31, count 2 2006.196.07:31:11.29#ibcon#about to write, iclass 31, count 2 2006.196.07:31:11.29#ibcon#wrote, iclass 31, count 2 2006.196.07:31:11.29#ibcon#about to read 3, iclass 31, count 2 2006.196.07:31:11.31#ibcon#read 3, iclass 31, count 2 2006.196.07:31:11.31#ibcon#about to read 4, iclass 31, count 2 2006.196.07:31:11.31#ibcon#read 4, iclass 31, count 2 2006.196.07:31:11.31#ibcon#about to read 5, iclass 31, count 2 2006.196.07:31:11.31#ibcon#read 5, iclass 31, count 2 2006.196.07:31:11.31#ibcon#about to read 6, iclass 31, count 2 2006.196.07:31:11.31#ibcon#read 6, iclass 31, count 2 2006.196.07:31:11.31#ibcon#end of sib2, iclass 31, count 2 2006.196.07:31:11.31#ibcon#*mode == 0, iclass 31, count 2 2006.196.07:31:11.31#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.196.07:31:11.31#ibcon#[27=AT02-04\r\n] 2006.196.07:31:11.31#ibcon#*before write, iclass 31, count 2 2006.196.07:31:11.31#ibcon#enter sib2, iclass 31, count 2 2006.196.07:31:11.31#ibcon#flushed, iclass 31, count 2 2006.196.07:31:11.31#ibcon#about to write, iclass 31, count 2 2006.196.07:31:11.31#ibcon#wrote, iclass 31, count 2 2006.196.07:31:11.31#ibcon#about to read 3, iclass 31, count 2 2006.196.07:31:11.34#ibcon#read 3, iclass 31, count 2 2006.196.07:31:11.34#ibcon#about to read 4, iclass 31, count 2 2006.196.07:31:11.34#ibcon#read 4, iclass 31, count 2 2006.196.07:31:11.34#ibcon#about to read 5, iclass 31, count 2 2006.196.07:31:11.34#ibcon#read 5, iclass 31, count 2 2006.196.07:31:11.34#ibcon#about to read 6, iclass 31, count 2 2006.196.07:31:11.34#ibcon#read 6, iclass 31, count 2 2006.196.07:31:11.34#ibcon#end of sib2, iclass 31, count 2 2006.196.07:31:11.34#ibcon#*after write, iclass 31, count 2 2006.196.07:31:11.34#ibcon#*before return 0, iclass 31, count 2 2006.196.07:31:11.34#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.196.07:31:11.34#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.196.07:31:11.34#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.196.07:31:11.34#ibcon#ireg 7 cls_cnt 0 2006.196.07:31:11.34#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.196.07:31:11.46#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.196.07:31:11.46#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.196.07:31:11.46#ibcon#enter wrdev, iclass 31, count 0 2006.196.07:31:11.46#ibcon#first serial, iclass 31, count 0 2006.196.07:31:11.46#ibcon#enter sib2, iclass 31, count 0 2006.196.07:31:11.46#ibcon#flushed, iclass 31, count 0 2006.196.07:31:11.46#ibcon#about to write, iclass 31, count 0 2006.196.07:31:11.46#ibcon#wrote, iclass 31, count 0 2006.196.07:31:11.46#ibcon#about to read 3, iclass 31, count 0 2006.196.07:31:11.48#ibcon#read 3, iclass 31, count 0 2006.196.07:31:11.48#ibcon#about to read 4, iclass 31, count 0 2006.196.07:31:11.48#ibcon#read 4, iclass 31, count 0 2006.196.07:31:11.48#ibcon#about to read 5, iclass 31, count 0 2006.196.07:31:11.48#ibcon#read 5, iclass 31, count 0 2006.196.07:31:11.48#ibcon#about to read 6, iclass 31, count 0 2006.196.07:31:11.48#ibcon#read 6, iclass 31, count 0 2006.196.07:31:11.48#ibcon#end of sib2, iclass 31, count 0 2006.196.07:31:11.48#ibcon#*mode == 0, iclass 31, count 0 2006.196.07:31:11.48#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.196.07:31:11.48#ibcon#[27=USB\r\n] 2006.196.07:31:11.48#ibcon#*before write, iclass 31, count 0 2006.196.07:31:11.48#ibcon#enter sib2, iclass 31, count 0 2006.196.07:31:11.48#ibcon#flushed, iclass 31, count 0 2006.196.07:31:11.48#ibcon#about to write, iclass 31, count 0 2006.196.07:31:11.48#ibcon#wrote, iclass 31, count 0 2006.196.07:31:11.48#ibcon#about to read 3, iclass 31, count 0 2006.196.07:31:11.51#ibcon#read 3, iclass 31, count 0 2006.196.07:31:11.51#ibcon#about to read 4, iclass 31, count 0 2006.196.07:31:11.51#ibcon#read 4, iclass 31, count 0 2006.196.07:31:11.51#ibcon#about to read 5, iclass 31, count 0 2006.196.07:31:11.51#ibcon#read 5, iclass 31, count 0 2006.196.07:31:11.51#ibcon#about to read 6, iclass 31, count 0 2006.196.07:31:11.51#ibcon#read 6, iclass 31, count 0 2006.196.07:31:11.51#ibcon#end of sib2, iclass 31, count 0 2006.196.07:31:11.51#ibcon#*after write, iclass 31, count 0 2006.196.07:31:11.51#ibcon#*before return 0, iclass 31, count 0 2006.196.07:31:11.51#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.196.07:31:11.51#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.196.07:31:11.51#ibcon#about to clear, iclass 31 cls_cnt 0 2006.196.07:31:11.51#ibcon#cleared, iclass 31 cls_cnt 0 2006.196.07:31:11.51$vc4f8/vblo=3,656.99 2006.196.07:31:11.51#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.196.07:31:11.51#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.196.07:31:11.51#ibcon#ireg 17 cls_cnt 0 2006.196.07:31:11.51#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.196.07:31:11.51#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.196.07:31:11.51#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.196.07:31:11.51#ibcon#enter wrdev, iclass 33, count 0 2006.196.07:31:11.51#ibcon#first serial, iclass 33, count 0 2006.196.07:31:11.51#ibcon#enter sib2, iclass 33, count 0 2006.196.07:31:11.51#ibcon#flushed, iclass 33, count 0 2006.196.07:31:11.51#ibcon#about to write, iclass 33, count 0 2006.196.07:31:11.51#ibcon#wrote, iclass 33, count 0 2006.196.07:31:11.51#ibcon#about to read 3, iclass 33, count 0 2006.196.07:31:11.53#ibcon#read 3, iclass 33, count 0 2006.196.07:31:11.53#ibcon#about to read 4, iclass 33, count 0 2006.196.07:31:11.53#ibcon#read 4, iclass 33, count 0 2006.196.07:31:11.53#ibcon#about to read 5, iclass 33, count 0 2006.196.07:31:11.53#ibcon#read 5, iclass 33, count 0 2006.196.07:31:11.53#ibcon#about to read 6, iclass 33, count 0 2006.196.07:31:11.53#ibcon#read 6, iclass 33, count 0 2006.196.07:31:11.53#ibcon#end of sib2, iclass 33, count 0 2006.196.07:31:11.53#ibcon#*mode == 0, iclass 33, count 0 2006.196.07:31:11.53#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.196.07:31:11.53#ibcon#[28=FRQ=03,656.99\r\n] 2006.196.07:31:11.53#ibcon#*before write, iclass 33, count 0 2006.196.07:31:11.53#ibcon#enter sib2, iclass 33, count 0 2006.196.07:31:11.53#ibcon#flushed, iclass 33, count 0 2006.196.07:31:11.53#ibcon#about to write, iclass 33, count 0 2006.196.07:31:11.53#ibcon#wrote, iclass 33, count 0 2006.196.07:31:11.53#ibcon#about to read 3, iclass 33, count 0 2006.196.07:31:11.57#ibcon#read 3, iclass 33, count 0 2006.196.07:31:11.57#ibcon#about to read 4, iclass 33, count 0 2006.196.07:31:11.57#ibcon#read 4, iclass 33, count 0 2006.196.07:31:11.57#ibcon#about to read 5, iclass 33, count 0 2006.196.07:31:11.57#ibcon#read 5, iclass 33, count 0 2006.196.07:31:11.57#ibcon#about to read 6, iclass 33, count 0 2006.196.07:31:11.57#ibcon#read 6, iclass 33, count 0 2006.196.07:31:11.57#ibcon#end of sib2, iclass 33, count 0 2006.196.07:31:11.57#ibcon#*after write, iclass 33, count 0 2006.196.07:31:11.57#ibcon#*before return 0, iclass 33, count 0 2006.196.07:31:11.57#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.196.07:31:11.57#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.196.07:31:11.57#ibcon#about to clear, iclass 33 cls_cnt 0 2006.196.07:31:11.57#ibcon#cleared, iclass 33 cls_cnt 0 2006.196.07:31:11.57$vc4f8/vb=3,4 2006.196.07:31:11.57#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.196.07:31:11.57#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.196.07:31:11.57#ibcon#ireg 11 cls_cnt 2 2006.196.07:31:11.57#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.196.07:31:11.63#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.196.07:31:11.63#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.196.07:31:11.63#ibcon#enter wrdev, iclass 35, count 2 2006.196.07:31:11.63#ibcon#first serial, iclass 35, count 2 2006.196.07:31:11.63#ibcon#enter sib2, iclass 35, count 2 2006.196.07:31:11.63#ibcon#flushed, iclass 35, count 2 2006.196.07:31:11.63#ibcon#about to write, iclass 35, count 2 2006.196.07:31:11.63#ibcon#wrote, iclass 35, count 2 2006.196.07:31:11.63#ibcon#about to read 3, iclass 35, count 2 2006.196.07:31:11.65#ibcon#read 3, iclass 35, count 2 2006.196.07:31:11.65#ibcon#about to read 4, iclass 35, count 2 2006.196.07:31:11.65#ibcon#read 4, iclass 35, count 2 2006.196.07:31:11.65#ibcon#about to read 5, iclass 35, count 2 2006.196.07:31:11.65#ibcon#read 5, iclass 35, count 2 2006.196.07:31:11.65#ibcon#about to read 6, iclass 35, count 2 2006.196.07:31:11.65#ibcon#read 6, iclass 35, count 2 2006.196.07:31:11.65#ibcon#end of sib2, iclass 35, count 2 2006.196.07:31:11.65#ibcon#*mode == 0, iclass 35, count 2 2006.196.07:31:11.65#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.196.07:31:11.65#ibcon#[27=AT03-04\r\n] 2006.196.07:31:11.65#ibcon#*before write, iclass 35, count 2 2006.196.07:31:11.65#ibcon#enter sib2, iclass 35, count 2 2006.196.07:31:11.65#ibcon#flushed, iclass 35, count 2 2006.196.07:31:11.65#ibcon#about to write, iclass 35, count 2 2006.196.07:31:11.65#ibcon#wrote, iclass 35, count 2 2006.196.07:31:11.65#ibcon#about to read 3, iclass 35, count 2 2006.196.07:31:11.68#ibcon#read 3, iclass 35, count 2 2006.196.07:31:11.68#ibcon#about to read 4, iclass 35, count 2 2006.196.07:31:11.68#ibcon#read 4, iclass 35, count 2 2006.196.07:31:11.68#ibcon#about to read 5, iclass 35, count 2 2006.196.07:31:11.68#ibcon#read 5, iclass 35, count 2 2006.196.07:31:11.68#ibcon#about to read 6, iclass 35, count 2 2006.196.07:31:11.68#ibcon#read 6, iclass 35, count 2 2006.196.07:31:11.68#ibcon#end of sib2, iclass 35, count 2 2006.196.07:31:11.68#ibcon#*after write, iclass 35, count 2 2006.196.07:31:11.68#ibcon#*before return 0, iclass 35, count 2 2006.196.07:31:11.68#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.196.07:31:11.68#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.196.07:31:11.68#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.196.07:31:11.68#ibcon#ireg 7 cls_cnt 0 2006.196.07:31:11.68#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.196.07:31:11.80#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.196.07:31:11.80#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.196.07:31:11.80#ibcon#enter wrdev, iclass 35, count 0 2006.196.07:31:11.80#ibcon#first serial, iclass 35, count 0 2006.196.07:31:11.80#ibcon#enter sib2, iclass 35, count 0 2006.196.07:31:11.80#ibcon#flushed, iclass 35, count 0 2006.196.07:31:11.80#ibcon#about to write, iclass 35, count 0 2006.196.07:31:11.80#ibcon#wrote, iclass 35, count 0 2006.196.07:31:11.80#ibcon#about to read 3, iclass 35, count 0 2006.196.07:31:11.82#ibcon#read 3, iclass 35, count 0 2006.196.07:31:11.82#ibcon#about to read 4, iclass 35, count 0 2006.196.07:31:11.82#ibcon#read 4, iclass 35, count 0 2006.196.07:31:11.82#ibcon#about to read 5, iclass 35, count 0 2006.196.07:31:11.82#ibcon#read 5, iclass 35, count 0 2006.196.07:31:11.82#ibcon#about to read 6, iclass 35, count 0 2006.196.07:31:11.82#ibcon#read 6, iclass 35, count 0 2006.196.07:31:11.82#ibcon#end of sib2, iclass 35, count 0 2006.196.07:31:11.82#ibcon#*mode == 0, iclass 35, count 0 2006.196.07:31:11.82#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.196.07:31:11.82#ibcon#[27=USB\r\n] 2006.196.07:31:11.82#ibcon#*before write, iclass 35, count 0 2006.196.07:31:11.82#ibcon#enter sib2, iclass 35, count 0 2006.196.07:31:11.82#ibcon#flushed, iclass 35, count 0 2006.196.07:31:11.82#ibcon#about to write, iclass 35, count 0 2006.196.07:31:11.82#ibcon#wrote, iclass 35, count 0 2006.196.07:31:11.82#ibcon#about to read 3, iclass 35, count 0 2006.196.07:31:11.85#ibcon#read 3, iclass 35, count 0 2006.196.07:31:11.85#ibcon#about to read 4, iclass 35, count 0 2006.196.07:31:11.85#ibcon#read 4, iclass 35, count 0 2006.196.07:31:11.85#ibcon#about to read 5, iclass 35, count 0 2006.196.07:31:11.85#ibcon#read 5, iclass 35, count 0 2006.196.07:31:11.85#ibcon#about to read 6, iclass 35, count 0 2006.196.07:31:11.85#ibcon#read 6, iclass 35, count 0 2006.196.07:31:11.85#ibcon#end of sib2, iclass 35, count 0 2006.196.07:31:11.85#ibcon#*after write, iclass 35, count 0 2006.196.07:31:11.85#ibcon#*before return 0, iclass 35, count 0 2006.196.07:31:11.85#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.196.07:31:11.85#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.196.07:31:11.85#ibcon#about to clear, iclass 35 cls_cnt 0 2006.196.07:31:11.85#ibcon#cleared, iclass 35 cls_cnt 0 2006.196.07:31:11.85$vc4f8/vblo=4,712.99 2006.196.07:31:11.85#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.196.07:31:11.85#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.196.07:31:11.85#ibcon#ireg 17 cls_cnt 0 2006.196.07:31:11.85#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.196.07:31:11.85#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.196.07:31:11.85#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.196.07:31:11.85#ibcon#enter wrdev, iclass 37, count 0 2006.196.07:31:11.85#ibcon#first serial, iclass 37, count 0 2006.196.07:31:11.85#ibcon#enter sib2, iclass 37, count 0 2006.196.07:31:11.85#ibcon#flushed, iclass 37, count 0 2006.196.07:31:11.85#ibcon#about to write, iclass 37, count 0 2006.196.07:31:11.85#ibcon#wrote, iclass 37, count 0 2006.196.07:31:11.85#ibcon#about to read 3, iclass 37, count 0 2006.196.07:31:11.87#ibcon#read 3, iclass 37, count 0 2006.196.07:31:11.87#ibcon#about to read 4, iclass 37, count 0 2006.196.07:31:11.87#ibcon#read 4, iclass 37, count 0 2006.196.07:31:11.87#ibcon#about to read 5, iclass 37, count 0 2006.196.07:31:11.87#ibcon#read 5, iclass 37, count 0 2006.196.07:31:11.87#ibcon#about to read 6, iclass 37, count 0 2006.196.07:31:11.87#ibcon#read 6, iclass 37, count 0 2006.196.07:31:11.87#ibcon#end of sib2, iclass 37, count 0 2006.196.07:31:11.87#ibcon#*mode == 0, iclass 37, count 0 2006.196.07:31:11.87#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.196.07:31:11.87#ibcon#[28=FRQ=04,712.99\r\n] 2006.196.07:31:11.87#ibcon#*before write, iclass 37, count 0 2006.196.07:31:11.87#ibcon#enter sib2, iclass 37, count 0 2006.196.07:31:11.87#ibcon#flushed, iclass 37, count 0 2006.196.07:31:11.87#ibcon#about to write, iclass 37, count 0 2006.196.07:31:11.87#ibcon#wrote, iclass 37, count 0 2006.196.07:31:11.87#ibcon#about to read 3, iclass 37, count 0 2006.196.07:31:11.91#ibcon#read 3, iclass 37, count 0 2006.196.07:31:11.91#ibcon#about to read 4, iclass 37, count 0 2006.196.07:31:11.91#ibcon#read 4, iclass 37, count 0 2006.196.07:31:11.91#ibcon#about to read 5, iclass 37, count 0 2006.196.07:31:11.91#ibcon#read 5, iclass 37, count 0 2006.196.07:31:11.91#ibcon#about to read 6, iclass 37, count 0 2006.196.07:31:11.91#ibcon#read 6, iclass 37, count 0 2006.196.07:31:11.91#ibcon#end of sib2, iclass 37, count 0 2006.196.07:31:11.91#ibcon#*after write, iclass 37, count 0 2006.196.07:31:11.91#ibcon#*before return 0, iclass 37, count 0 2006.196.07:31:11.91#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.196.07:31:11.91#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.196.07:31:11.91#ibcon#about to clear, iclass 37 cls_cnt 0 2006.196.07:31:11.91#ibcon#cleared, iclass 37 cls_cnt 0 2006.196.07:31:11.91$vc4f8/vb=4,4 2006.196.07:31:11.91#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.196.07:31:11.91#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.196.07:31:11.91#ibcon#ireg 11 cls_cnt 2 2006.196.07:31:11.91#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.196.07:31:11.97#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.196.07:31:11.97#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.196.07:31:11.97#ibcon#enter wrdev, iclass 39, count 2 2006.196.07:31:11.97#ibcon#first serial, iclass 39, count 2 2006.196.07:31:11.97#ibcon#enter sib2, iclass 39, count 2 2006.196.07:31:11.97#ibcon#flushed, iclass 39, count 2 2006.196.07:31:11.97#ibcon#about to write, iclass 39, count 2 2006.196.07:31:11.97#ibcon#wrote, iclass 39, count 2 2006.196.07:31:11.97#ibcon#about to read 3, iclass 39, count 2 2006.196.07:31:11.99#ibcon#read 3, iclass 39, count 2 2006.196.07:31:11.99#ibcon#about to read 4, iclass 39, count 2 2006.196.07:31:11.99#ibcon#read 4, iclass 39, count 2 2006.196.07:31:11.99#ibcon#about to read 5, iclass 39, count 2 2006.196.07:31:11.99#ibcon#read 5, iclass 39, count 2 2006.196.07:31:11.99#ibcon#about to read 6, iclass 39, count 2 2006.196.07:31:11.99#ibcon#read 6, iclass 39, count 2 2006.196.07:31:11.99#ibcon#end of sib2, iclass 39, count 2 2006.196.07:31:11.99#ibcon#*mode == 0, iclass 39, count 2 2006.196.07:31:11.99#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.196.07:31:11.99#ibcon#[27=AT04-04\r\n] 2006.196.07:31:11.99#ibcon#*before write, iclass 39, count 2 2006.196.07:31:11.99#ibcon#enter sib2, iclass 39, count 2 2006.196.07:31:11.99#ibcon#flushed, iclass 39, count 2 2006.196.07:31:11.99#ibcon#about to write, iclass 39, count 2 2006.196.07:31:11.99#ibcon#wrote, iclass 39, count 2 2006.196.07:31:11.99#ibcon#about to read 3, iclass 39, count 2 2006.196.07:31:12.02#ibcon#read 3, iclass 39, count 2 2006.196.07:31:12.02#ibcon#about to read 4, iclass 39, count 2 2006.196.07:31:12.02#ibcon#read 4, iclass 39, count 2 2006.196.07:31:12.02#ibcon#about to read 5, iclass 39, count 2 2006.196.07:31:12.02#ibcon#read 5, iclass 39, count 2 2006.196.07:31:12.02#ibcon#about to read 6, iclass 39, count 2 2006.196.07:31:12.02#ibcon#read 6, iclass 39, count 2 2006.196.07:31:12.02#ibcon#end of sib2, iclass 39, count 2 2006.196.07:31:12.02#ibcon#*after write, iclass 39, count 2 2006.196.07:31:12.02#ibcon#*before return 0, iclass 39, count 2 2006.196.07:31:12.02#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.196.07:31:12.02#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.196.07:31:12.02#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.196.07:31:12.02#ibcon#ireg 7 cls_cnt 0 2006.196.07:31:12.02#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.196.07:31:12.14#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.196.07:31:12.14#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.196.07:31:12.14#ibcon#enter wrdev, iclass 39, count 0 2006.196.07:31:12.14#ibcon#first serial, iclass 39, count 0 2006.196.07:31:12.14#ibcon#enter sib2, iclass 39, count 0 2006.196.07:31:12.14#ibcon#flushed, iclass 39, count 0 2006.196.07:31:12.14#ibcon#about to write, iclass 39, count 0 2006.196.07:31:12.14#ibcon#wrote, iclass 39, count 0 2006.196.07:31:12.14#ibcon#about to read 3, iclass 39, count 0 2006.196.07:31:12.16#ibcon#read 3, iclass 39, count 0 2006.196.07:31:12.16#ibcon#about to read 4, iclass 39, count 0 2006.196.07:31:12.16#ibcon#read 4, iclass 39, count 0 2006.196.07:31:12.16#ibcon#about to read 5, iclass 39, count 0 2006.196.07:31:12.16#ibcon#read 5, iclass 39, count 0 2006.196.07:31:12.16#ibcon#about to read 6, iclass 39, count 0 2006.196.07:31:12.16#ibcon#read 6, iclass 39, count 0 2006.196.07:31:12.16#ibcon#end of sib2, iclass 39, count 0 2006.196.07:31:12.16#ibcon#*mode == 0, iclass 39, count 0 2006.196.07:31:12.16#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.196.07:31:12.16#ibcon#[27=USB\r\n] 2006.196.07:31:12.16#ibcon#*before write, iclass 39, count 0 2006.196.07:31:12.16#ibcon#enter sib2, iclass 39, count 0 2006.196.07:31:12.16#ibcon#flushed, iclass 39, count 0 2006.196.07:31:12.16#ibcon#about to write, iclass 39, count 0 2006.196.07:31:12.16#ibcon#wrote, iclass 39, count 0 2006.196.07:31:12.16#ibcon#about to read 3, iclass 39, count 0 2006.196.07:31:12.19#ibcon#read 3, iclass 39, count 0 2006.196.07:31:12.19#ibcon#about to read 4, iclass 39, count 0 2006.196.07:31:12.19#ibcon#read 4, iclass 39, count 0 2006.196.07:31:12.19#ibcon#about to read 5, iclass 39, count 0 2006.196.07:31:12.19#ibcon#read 5, iclass 39, count 0 2006.196.07:31:12.19#ibcon#about to read 6, iclass 39, count 0 2006.196.07:31:12.19#ibcon#read 6, iclass 39, count 0 2006.196.07:31:12.19#ibcon#end of sib2, iclass 39, count 0 2006.196.07:31:12.19#ibcon#*after write, iclass 39, count 0 2006.196.07:31:12.19#ibcon#*before return 0, iclass 39, count 0 2006.196.07:31:12.19#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.196.07:31:12.19#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.196.07:31:12.19#ibcon#about to clear, iclass 39 cls_cnt 0 2006.196.07:31:12.19#ibcon#cleared, iclass 39 cls_cnt 0 2006.196.07:31:12.19$vc4f8/vblo=5,744.99 2006.196.07:31:12.19#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.196.07:31:12.19#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.196.07:31:12.19#ibcon#ireg 17 cls_cnt 0 2006.196.07:31:12.19#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.196.07:31:12.19#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.196.07:31:12.19#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.196.07:31:12.19#ibcon#enter wrdev, iclass 3, count 0 2006.196.07:31:12.19#ibcon#first serial, iclass 3, count 0 2006.196.07:31:12.19#ibcon#enter sib2, iclass 3, count 0 2006.196.07:31:12.19#ibcon#flushed, iclass 3, count 0 2006.196.07:31:12.19#ibcon#about to write, iclass 3, count 0 2006.196.07:31:12.19#ibcon#wrote, iclass 3, count 0 2006.196.07:31:12.19#ibcon#about to read 3, iclass 3, count 0 2006.196.07:31:12.21#ibcon#read 3, iclass 3, count 0 2006.196.07:31:12.21#ibcon#about to read 4, iclass 3, count 0 2006.196.07:31:12.21#ibcon#read 4, iclass 3, count 0 2006.196.07:31:12.21#ibcon#about to read 5, iclass 3, count 0 2006.196.07:31:12.21#ibcon#read 5, iclass 3, count 0 2006.196.07:31:12.21#ibcon#about to read 6, iclass 3, count 0 2006.196.07:31:12.21#ibcon#read 6, iclass 3, count 0 2006.196.07:31:12.21#ibcon#end of sib2, iclass 3, count 0 2006.196.07:31:12.21#ibcon#*mode == 0, iclass 3, count 0 2006.196.07:31:12.21#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.196.07:31:12.21#ibcon#[28=FRQ=05,744.99\r\n] 2006.196.07:31:12.21#ibcon#*before write, iclass 3, count 0 2006.196.07:31:12.21#ibcon#enter sib2, iclass 3, count 0 2006.196.07:31:12.21#ibcon#flushed, iclass 3, count 0 2006.196.07:31:12.21#ibcon#about to write, iclass 3, count 0 2006.196.07:31:12.21#ibcon#wrote, iclass 3, count 0 2006.196.07:31:12.21#ibcon#about to read 3, iclass 3, count 0 2006.196.07:31:12.25#ibcon#read 3, iclass 3, count 0 2006.196.07:31:12.25#ibcon#about to read 4, iclass 3, count 0 2006.196.07:31:12.25#ibcon#read 4, iclass 3, count 0 2006.196.07:31:12.25#ibcon#about to read 5, iclass 3, count 0 2006.196.07:31:12.25#ibcon#read 5, iclass 3, count 0 2006.196.07:31:12.25#ibcon#about to read 6, iclass 3, count 0 2006.196.07:31:12.25#ibcon#read 6, iclass 3, count 0 2006.196.07:31:12.25#ibcon#end of sib2, iclass 3, count 0 2006.196.07:31:12.25#ibcon#*after write, iclass 3, count 0 2006.196.07:31:12.25#ibcon#*before return 0, iclass 3, count 0 2006.196.07:31:12.25#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.196.07:31:12.25#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.196.07:31:12.25#ibcon#about to clear, iclass 3 cls_cnt 0 2006.196.07:31:12.25#ibcon#cleared, iclass 3 cls_cnt 0 2006.196.07:31:12.25$vc4f8/vb=5,4 2006.196.07:31:12.25#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.196.07:31:12.25#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.196.07:31:12.25#ibcon#ireg 11 cls_cnt 2 2006.196.07:31:12.25#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.196.07:31:12.31#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.196.07:31:12.31#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.196.07:31:12.31#ibcon#enter wrdev, iclass 5, count 2 2006.196.07:31:12.31#ibcon#first serial, iclass 5, count 2 2006.196.07:31:12.31#ibcon#enter sib2, iclass 5, count 2 2006.196.07:31:12.31#ibcon#flushed, iclass 5, count 2 2006.196.07:31:12.31#ibcon#about to write, iclass 5, count 2 2006.196.07:31:12.31#ibcon#wrote, iclass 5, count 2 2006.196.07:31:12.31#ibcon#about to read 3, iclass 5, count 2 2006.196.07:31:12.33#ibcon#read 3, iclass 5, count 2 2006.196.07:31:12.33#ibcon#about to read 4, iclass 5, count 2 2006.196.07:31:12.33#ibcon#read 4, iclass 5, count 2 2006.196.07:31:12.33#ibcon#about to read 5, iclass 5, count 2 2006.196.07:31:12.33#ibcon#read 5, iclass 5, count 2 2006.196.07:31:12.33#ibcon#about to read 6, iclass 5, count 2 2006.196.07:31:12.33#ibcon#read 6, iclass 5, count 2 2006.196.07:31:12.33#ibcon#end of sib2, iclass 5, count 2 2006.196.07:31:12.33#ibcon#*mode == 0, iclass 5, count 2 2006.196.07:31:12.33#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.196.07:31:12.33#ibcon#[27=AT05-04\r\n] 2006.196.07:31:12.33#ibcon#*before write, iclass 5, count 2 2006.196.07:31:12.33#ibcon#enter sib2, iclass 5, count 2 2006.196.07:31:12.33#ibcon#flushed, iclass 5, count 2 2006.196.07:31:12.33#ibcon#about to write, iclass 5, count 2 2006.196.07:31:12.33#ibcon#wrote, iclass 5, count 2 2006.196.07:31:12.33#ibcon#about to read 3, iclass 5, count 2 2006.196.07:31:12.36#ibcon#read 3, iclass 5, count 2 2006.196.07:31:12.36#ibcon#about to read 4, iclass 5, count 2 2006.196.07:31:12.36#ibcon#read 4, iclass 5, count 2 2006.196.07:31:12.36#ibcon#about to read 5, iclass 5, count 2 2006.196.07:31:12.36#ibcon#read 5, iclass 5, count 2 2006.196.07:31:12.36#ibcon#about to read 6, iclass 5, count 2 2006.196.07:31:12.36#ibcon#read 6, iclass 5, count 2 2006.196.07:31:12.36#ibcon#end of sib2, iclass 5, count 2 2006.196.07:31:12.36#ibcon#*after write, iclass 5, count 2 2006.196.07:31:12.36#ibcon#*before return 0, iclass 5, count 2 2006.196.07:31:12.36#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.196.07:31:12.36#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.196.07:31:12.36#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.196.07:31:12.36#ibcon#ireg 7 cls_cnt 0 2006.196.07:31:12.36#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.196.07:31:12.48#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.196.07:31:12.48#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.196.07:31:12.48#ibcon#enter wrdev, iclass 5, count 0 2006.196.07:31:12.48#ibcon#first serial, iclass 5, count 0 2006.196.07:31:12.48#ibcon#enter sib2, iclass 5, count 0 2006.196.07:31:12.48#ibcon#flushed, iclass 5, count 0 2006.196.07:31:12.48#ibcon#about to write, iclass 5, count 0 2006.196.07:31:12.48#ibcon#wrote, iclass 5, count 0 2006.196.07:31:12.48#ibcon#about to read 3, iclass 5, count 0 2006.196.07:31:12.50#ibcon#read 3, iclass 5, count 0 2006.196.07:31:12.50#ibcon#about to read 4, iclass 5, count 0 2006.196.07:31:12.50#ibcon#read 4, iclass 5, count 0 2006.196.07:31:12.50#ibcon#about to read 5, iclass 5, count 0 2006.196.07:31:12.50#ibcon#read 5, iclass 5, count 0 2006.196.07:31:12.50#ibcon#about to read 6, iclass 5, count 0 2006.196.07:31:12.50#ibcon#read 6, iclass 5, count 0 2006.196.07:31:12.50#ibcon#end of sib2, iclass 5, count 0 2006.196.07:31:12.50#ibcon#*mode == 0, iclass 5, count 0 2006.196.07:31:12.50#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.196.07:31:12.50#ibcon#[27=USB\r\n] 2006.196.07:31:12.50#ibcon#*before write, iclass 5, count 0 2006.196.07:31:12.50#ibcon#enter sib2, iclass 5, count 0 2006.196.07:31:12.50#ibcon#flushed, iclass 5, count 0 2006.196.07:31:12.50#ibcon#about to write, iclass 5, count 0 2006.196.07:31:12.50#ibcon#wrote, iclass 5, count 0 2006.196.07:31:12.50#ibcon#about to read 3, iclass 5, count 0 2006.196.07:31:12.53#ibcon#read 3, iclass 5, count 0 2006.196.07:31:12.53#ibcon#about to read 4, iclass 5, count 0 2006.196.07:31:12.53#ibcon#read 4, iclass 5, count 0 2006.196.07:31:12.53#ibcon#about to read 5, iclass 5, count 0 2006.196.07:31:12.53#ibcon#read 5, iclass 5, count 0 2006.196.07:31:12.53#ibcon#about to read 6, iclass 5, count 0 2006.196.07:31:12.53#ibcon#read 6, iclass 5, count 0 2006.196.07:31:12.53#ibcon#end of sib2, iclass 5, count 0 2006.196.07:31:12.53#ibcon#*after write, iclass 5, count 0 2006.196.07:31:12.53#ibcon#*before return 0, iclass 5, count 0 2006.196.07:31:12.53#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.196.07:31:12.53#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.196.07:31:12.53#ibcon#about to clear, iclass 5 cls_cnt 0 2006.196.07:31:12.53#ibcon#cleared, iclass 5 cls_cnt 0 2006.196.07:31:12.53$vc4f8/vblo=6,752.99 2006.196.07:31:12.53#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.196.07:31:12.53#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.196.07:31:12.53#ibcon#ireg 17 cls_cnt 0 2006.196.07:31:12.53#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.196.07:31:12.53#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.196.07:31:12.53#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.196.07:31:12.53#ibcon#enter wrdev, iclass 7, count 0 2006.196.07:31:12.53#ibcon#first serial, iclass 7, count 0 2006.196.07:31:12.53#ibcon#enter sib2, iclass 7, count 0 2006.196.07:31:12.53#ibcon#flushed, iclass 7, count 0 2006.196.07:31:12.53#ibcon#about to write, iclass 7, count 0 2006.196.07:31:12.53#ibcon#wrote, iclass 7, count 0 2006.196.07:31:12.53#ibcon#about to read 3, iclass 7, count 0 2006.196.07:31:12.55#ibcon#read 3, iclass 7, count 0 2006.196.07:31:12.55#ibcon#about to read 4, iclass 7, count 0 2006.196.07:31:12.55#ibcon#read 4, iclass 7, count 0 2006.196.07:31:12.55#ibcon#about to read 5, iclass 7, count 0 2006.196.07:31:12.55#ibcon#read 5, iclass 7, count 0 2006.196.07:31:12.55#ibcon#about to read 6, iclass 7, count 0 2006.196.07:31:12.55#ibcon#read 6, iclass 7, count 0 2006.196.07:31:12.55#ibcon#end of sib2, iclass 7, count 0 2006.196.07:31:12.55#ibcon#*mode == 0, iclass 7, count 0 2006.196.07:31:12.55#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.196.07:31:12.55#ibcon#[28=FRQ=06,752.99\r\n] 2006.196.07:31:12.55#ibcon#*before write, iclass 7, count 0 2006.196.07:31:12.55#ibcon#enter sib2, iclass 7, count 0 2006.196.07:31:12.55#ibcon#flushed, iclass 7, count 0 2006.196.07:31:12.55#ibcon#about to write, iclass 7, count 0 2006.196.07:31:12.55#ibcon#wrote, iclass 7, count 0 2006.196.07:31:12.55#ibcon#about to read 3, iclass 7, count 0 2006.196.07:31:12.59#ibcon#read 3, iclass 7, count 0 2006.196.07:31:12.59#ibcon#about to read 4, iclass 7, count 0 2006.196.07:31:12.59#ibcon#read 4, iclass 7, count 0 2006.196.07:31:12.59#ibcon#about to read 5, iclass 7, count 0 2006.196.07:31:12.59#ibcon#read 5, iclass 7, count 0 2006.196.07:31:12.59#ibcon#about to read 6, iclass 7, count 0 2006.196.07:31:12.59#ibcon#read 6, iclass 7, count 0 2006.196.07:31:12.59#ibcon#end of sib2, iclass 7, count 0 2006.196.07:31:12.59#ibcon#*after write, iclass 7, count 0 2006.196.07:31:12.59#ibcon#*before return 0, iclass 7, count 0 2006.196.07:31:12.59#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.196.07:31:12.59#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.196.07:31:12.59#ibcon#about to clear, iclass 7 cls_cnt 0 2006.196.07:31:12.59#ibcon#cleared, iclass 7 cls_cnt 0 2006.196.07:31:12.59$vc4f8/vb=6,4 2006.196.07:31:12.59#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.196.07:31:12.59#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.196.07:31:12.59#ibcon#ireg 11 cls_cnt 2 2006.196.07:31:12.59#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.196.07:31:12.65#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.196.07:31:12.65#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.196.07:31:12.65#ibcon#enter wrdev, iclass 11, count 2 2006.196.07:31:12.65#ibcon#first serial, iclass 11, count 2 2006.196.07:31:12.65#ibcon#enter sib2, iclass 11, count 2 2006.196.07:31:12.65#ibcon#flushed, iclass 11, count 2 2006.196.07:31:12.65#ibcon#about to write, iclass 11, count 2 2006.196.07:31:12.65#ibcon#wrote, iclass 11, count 2 2006.196.07:31:12.65#ibcon#about to read 3, iclass 11, count 2 2006.196.07:31:12.67#ibcon#read 3, iclass 11, count 2 2006.196.07:31:12.67#ibcon#about to read 4, iclass 11, count 2 2006.196.07:31:12.67#ibcon#read 4, iclass 11, count 2 2006.196.07:31:12.67#ibcon#about to read 5, iclass 11, count 2 2006.196.07:31:12.67#ibcon#read 5, iclass 11, count 2 2006.196.07:31:12.67#ibcon#about to read 6, iclass 11, count 2 2006.196.07:31:12.67#ibcon#read 6, iclass 11, count 2 2006.196.07:31:12.67#ibcon#end of sib2, iclass 11, count 2 2006.196.07:31:12.67#ibcon#*mode == 0, iclass 11, count 2 2006.196.07:31:12.67#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.196.07:31:12.67#ibcon#[27=AT06-04\r\n] 2006.196.07:31:12.67#ibcon#*before write, iclass 11, count 2 2006.196.07:31:12.67#ibcon#enter sib2, iclass 11, count 2 2006.196.07:31:12.67#ibcon#flushed, iclass 11, count 2 2006.196.07:31:12.67#ibcon#about to write, iclass 11, count 2 2006.196.07:31:12.67#ibcon#wrote, iclass 11, count 2 2006.196.07:31:12.67#ibcon#about to read 3, iclass 11, count 2 2006.196.07:31:12.70#ibcon#read 3, iclass 11, count 2 2006.196.07:31:12.70#ibcon#about to read 4, iclass 11, count 2 2006.196.07:31:12.70#ibcon#read 4, iclass 11, count 2 2006.196.07:31:12.70#ibcon#about to read 5, iclass 11, count 2 2006.196.07:31:12.70#ibcon#read 5, iclass 11, count 2 2006.196.07:31:12.70#ibcon#about to read 6, iclass 11, count 2 2006.196.07:31:12.70#ibcon#read 6, iclass 11, count 2 2006.196.07:31:12.70#ibcon#end of sib2, iclass 11, count 2 2006.196.07:31:12.70#ibcon#*after write, iclass 11, count 2 2006.196.07:31:12.70#ibcon#*before return 0, iclass 11, count 2 2006.196.07:31:12.70#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.196.07:31:12.70#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.196.07:31:12.70#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.196.07:31:12.70#ibcon#ireg 7 cls_cnt 0 2006.196.07:31:12.70#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.196.07:31:12.82#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.196.07:31:12.82#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.196.07:31:12.82#ibcon#enter wrdev, iclass 11, count 0 2006.196.07:31:12.82#ibcon#first serial, iclass 11, count 0 2006.196.07:31:12.82#ibcon#enter sib2, iclass 11, count 0 2006.196.07:31:12.82#ibcon#flushed, iclass 11, count 0 2006.196.07:31:12.82#ibcon#about to write, iclass 11, count 0 2006.196.07:31:12.82#ibcon#wrote, iclass 11, count 0 2006.196.07:31:12.82#ibcon#about to read 3, iclass 11, count 0 2006.196.07:31:12.84#ibcon#read 3, iclass 11, count 0 2006.196.07:31:12.84#ibcon#about to read 4, iclass 11, count 0 2006.196.07:31:12.84#ibcon#read 4, iclass 11, count 0 2006.196.07:31:12.84#ibcon#about to read 5, iclass 11, count 0 2006.196.07:31:12.84#ibcon#read 5, iclass 11, count 0 2006.196.07:31:12.84#ibcon#about to read 6, iclass 11, count 0 2006.196.07:31:12.84#ibcon#read 6, iclass 11, count 0 2006.196.07:31:12.84#ibcon#end of sib2, iclass 11, count 0 2006.196.07:31:12.84#ibcon#*mode == 0, iclass 11, count 0 2006.196.07:31:12.84#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.196.07:31:12.84#ibcon#[27=USB\r\n] 2006.196.07:31:12.84#ibcon#*before write, iclass 11, count 0 2006.196.07:31:12.84#ibcon#enter sib2, iclass 11, count 0 2006.196.07:31:12.84#ibcon#flushed, iclass 11, count 0 2006.196.07:31:12.84#ibcon#about to write, iclass 11, count 0 2006.196.07:31:12.84#ibcon#wrote, iclass 11, count 0 2006.196.07:31:12.84#ibcon#about to read 3, iclass 11, count 0 2006.196.07:31:12.87#ibcon#read 3, iclass 11, count 0 2006.196.07:31:12.87#ibcon#about to read 4, iclass 11, count 0 2006.196.07:31:12.87#ibcon#read 4, iclass 11, count 0 2006.196.07:31:12.87#ibcon#about to read 5, iclass 11, count 0 2006.196.07:31:12.87#ibcon#read 5, iclass 11, count 0 2006.196.07:31:12.87#ibcon#about to read 6, iclass 11, count 0 2006.196.07:31:12.87#ibcon#read 6, iclass 11, count 0 2006.196.07:31:12.87#ibcon#end of sib2, iclass 11, count 0 2006.196.07:31:12.87#ibcon#*after write, iclass 11, count 0 2006.196.07:31:12.87#ibcon#*before return 0, iclass 11, count 0 2006.196.07:31:12.87#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.196.07:31:12.87#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.196.07:31:12.87#ibcon#about to clear, iclass 11 cls_cnt 0 2006.196.07:31:12.87#ibcon#cleared, iclass 11 cls_cnt 0 2006.196.07:31:12.87$vc4f8/vabw=wide 2006.196.07:31:12.87#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.196.07:31:12.87#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.196.07:31:12.87#ibcon#ireg 8 cls_cnt 0 2006.196.07:31:12.87#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.196.07:31:12.87#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.196.07:31:12.87#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.196.07:31:12.87#ibcon#enter wrdev, iclass 13, count 0 2006.196.07:31:12.87#ibcon#first serial, iclass 13, count 0 2006.196.07:31:12.87#ibcon#enter sib2, iclass 13, count 0 2006.196.07:31:12.87#ibcon#flushed, iclass 13, count 0 2006.196.07:31:12.87#ibcon#about to write, iclass 13, count 0 2006.196.07:31:12.87#ibcon#wrote, iclass 13, count 0 2006.196.07:31:12.87#ibcon#about to read 3, iclass 13, count 0 2006.196.07:31:12.89#ibcon#read 3, iclass 13, count 0 2006.196.07:31:12.89#ibcon#about to read 4, iclass 13, count 0 2006.196.07:31:12.89#ibcon#read 4, iclass 13, count 0 2006.196.07:31:12.89#ibcon#about to read 5, iclass 13, count 0 2006.196.07:31:12.89#ibcon#read 5, iclass 13, count 0 2006.196.07:31:12.89#ibcon#about to read 6, iclass 13, count 0 2006.196.07:31:12.89#ibcon#read 6, iclass 13, count 0 2006.196.07:31:12.89#ibcon#end of sib2, iclass 13, count 0 2006.196.07:31:12.89#ibcon#*mode == 0, iclass 13, count 0 2006.196.07:31:12.89#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.196.07:31:12.89#ibcon#[25=BW32\r\n] 2006.196.07:31:12.89#ibcon#*before write, iclass 13, count 0 2006.196.07:31:12.89#ibcon#enter sib2, iclass 13, count 0 2006.196.07:31:12.89#ibcon#flushed, iclass 13, count 0 2006.196.07:31:12.89#ibcon#about to write, iclass 13, count 0 2006.196.07:31:12.89#ibcon#wrote, iclass 13, count 0 2006.196.07:31:12.89#ibcon#about to read 3, iclass 13, count 0 2006.196.07:31:12.92#ibcon#read 3, iclass 13, count 0 2006.196.07:31:12.92#ibcon#about to read 4, iclass 13, count 0 2006.196.07:31:12.92#ibcon#read 4, iclass 13, count 0 2006.196.07:31:12.92#ibcon#about to read 5, iclass 13, count 0 2006.196.07:31:12.92#ibcon#read 5, iclass 13, count 0 2006.196.07:31:12.92#ibcon#about to read 6, iclass 13, count 0 2006.196.07:31:12.92#ibcon#read 6, iclass 13, count 0 2006.196.07:31:12.92#ibcon#end of sib2, iclass 13, count 0 2006.196.07:31:12.92#ibcon#*after write, iclass 13, count 0 2006.196.07:31:12.92#ibcon#*before return 0, iclass 13, count 0 2006.196.07:31:12.92#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.196.07:31:12.92#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.196.07:31:12.92#ibcon#about to clear, iclass 13 cls_cnt 0 2006.196.07:31:12.92#ibcon#cleared, iclass 13 cls_cnt 0 2006.196.07:31:12.92$vc4f8/vbbw=wide 2006.196.07:31:12.92#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.196.07:31:12.92#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.196.07:31:12.92#ibcon#ireg 8 cls_cnt 0 2006.196.07:31:12.92#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.196.07:31:12.99#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.196.07:31:12.99#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.196.07:31:12.99#ibcon#enter wrdev, iclass 15, count 0 2006.196.07:31:12.99#ibcon#first serial, iclass 15, count 0 2006.196.07:31:12.99#ibcon#enter sib2, iclass 15, count 0 2006.196.07:31:12.99#ibcon#flushed, iclass 15, count 0 2006.196.07:31:12.99#ibcon#about to write, iclass 15, count 0 2006.196.07:31:12.99#ibcon#wrote, iclass 15, count 0 2006.196.07:31:12.99#ibcon#about to read 3, iclass 15, count 0 2006.196.07:31:13.01#ibcon#read 3, iclass 15, count 0 2006.196.07:31:13.01#ibcon#about to read 4, iclass 15, count 0 2006.196.07:31:13.01#ibcon#read 4, iclass 15, count 0 2006.196.07:31:13.01#ibcon#about to read 5, iclass 15, count 0 2006.196.07:31:13.01#ibcon#read 5, iclass 15, count 0 2006.196.07:31:13.01#ibcon#about to read 6, iclass 15, count 0 2006.196.07:31:13.01#ibcon#read 6, iclass 15, count 0 2006.196.07:31:13.01#ibcon#end of sib2, iclass 15, count 0 2006.196.07:31:13.01#ibcon#*mode == 0, iclass 15, count 0 2006.196.07:31:13.01#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.196.07:31:13.01#ibcon#[27=BW32\r\n] 2006.196.07:31:13.01#ibcon#*before write, iclass 15, count 0 2006.196.07:31:13.01#ibcon#enter sib2, iclass 15, count 0 2006.196.07:31:13.01#ibcon#flushed, iclass 15, count 0 2006.196.07:31:13.01#ibcon#about to write, iclass 15, count 0 2006.196.07:31:13.01#ibcon#wrote, iclass 15, count 0 2006.196.07:31:13.01#ibcon#about to read 3, iclass 15, count 0 2006.196.07:31:13.04#ibcon#read 3, iclass 15, count 0 2006.196.07:31:13.04#ibcon#about to read 4, iclass 15, count 0 2006.196.07:31:13.04#ibcon#read 4, iclass 15, count 0 2006.196.07:31:13.04#ibcon#about to read 5, iclass 15, count 0 2006.196.07:31:13.04#ibcon#read 5, iclass 15, count 0 2006.196.07:31:13.04#ibcon#about to read 6, iclass 15, count 0 2006.196.07:31:13.04#ibcon#read 6, iclass 15, count 0 2006.196.07:31:13.04#ibcon#end of sib2, iclass 15, count 0 2006.196.07:31:13.04#ibcon#*after write, iclass 15, count 0 2006.196.07:31:13.04#ibcon#*before return 0, iclass 15, count 0 2006.196.07:31:13.04#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.196.07:31:13.04#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.196.07:31:13.04#ibcon#about to clear, iclass 15 cls_cnt 0 2006.196.07:31:13.04#ibcon#cleared, iclass 15 cls_cnt 0 2006.196.07:31:13.04$4f8m12a/ifd4f 2006.196.07:31:13.04$ifd4f/lo= 2006.196.07:31:13.04$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.196.07:31:13.04$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.196.07:31:13.04$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.196.07:31:13.04$ifd4f/patch= 2006.196.07:31:13.04$ifd4f/patch=lo1,a1,a2,a3,a4 2006.196.07:31:13.04$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.196.07:31:13.04$ifd4f/patch=lo3,a5,a6,a7,a8 2006.196.07:31:13.04$4f8m12a/"form=m,16.000,1:2 2006.196.07:31:13.04$4f8m12a/"tpicd 2006.196.07:31:13.04$4f8m12a/echo=off 2006.196.07:31:13.04$4f8m12a/xlog=off 2006.196.07:31:13.04:!2006.196.07:33:20 2006.196.07:31:56.14#trakl#Source acquired 2006.196.07:31:58.14#flagr#flagr/antenna,acquired 2006.196.07:33:20.00:preob 2006.196.07:33:20.13/onsource/TRACKING 2006.196.07:33:20.13:!2006.196.07:33:30 2006.196.07:33:30.00:data_valid=on 2006.196.07:33:30.00:midob 2006.196.07:33:31.13/onsource/TRACKING 2006.196.07:33:31.13/wx/30.25,1004.1,86 2006.196.07:33:31.22/cable/+6.3340E-03 2006.196.07:33:32.31/va/01,08,usb,yes,30,31 2006.196.07:33:32.31/va/02,07,usb,yes,30,32 2006.196.07:33:32.31/va/03,06,usb,yes,32,32 2006.196.07:33:32.31/va/04,07,usb,yes,31,33 2006.196.07:33:32.31/va/05,07,usb,yes,32,34 2006.196.07:33:32.31/va/06,06,usb,yes,31,31 2006.196.07:33:32.31/va/07,06,usb,yes,32,32 2006.196.07:33:32.31/va/08,07,usb,yes,30,30 2006.196.07:33:32.54/valo/01,532.99,yes,locked 2006.196.07:33:32.54/valo/02,572.99,yes,locked 2006.196.07:33:32.54/valo/03,672.99,yes,locked 2006.196.07:33:32.54/valo/04,832.99,yes,locked 2006.196.07:33:32.54/valo/05,652.99,yes,locked 2006.196.07:33:32.54/valo/06,772.99,yes,locked 2006.196.07:33:32.54/valo/07,832.99,yes,locked 2006.196.07:33:32.54/valo/08,852.99,yes,locked 2006.196.07:33:33.63/vb/01,04,usb,yes,29,28 2006.196.07:33:33.63/vb/02,04,usb,yes,31,32 2006.196.07:33:33.63/vb/03,04,usb,yes,27,31 2006.196.07:33:33.63/vb/04,04,usb,yes,28,28 2006.196.07:33:33.63/vb/05,04,usb,yes,27,31 2006.196.07:33:33.63/vb/06,04,usb,yes,28,30 2006.196.07:33:33.63/vb/07,04,usb,yes,30,29 2006.196.07:33:33.63/vb/08,04,usb,yes,27,31 2006.196.07:33:33.86/vblo/01,632.99,yes,locked 2006.196.07:33:33.86/vblo/02,640.99,yes,locked 2006.196.07:33:33.86/vblo/03,656.99,yes,locked 2006.196.07:33:33.86/vblo/04,712.99,yes,locked 2006.196.07:33:33.86/vblo/05,744.99,yes,locked 2006.196.07:33:33.86/vblo/06,752.99,yes,locked 2006.196.07:33:33.86/vblo/07,734.99,yes,locked 2006.196.07:33:33.86/vblo/08,744.99,yes,locked 2006.196.07:33:34.01/vabw/8 2006.196.07:33:34.16/vbbw/8 2006.196.07:33:34.25/xfe/off,on,15.0 2006.196.07:33:34.62/ifatt/23,28,28,28 2006.196.07:33:35.07/fmout-gps/S +3.37E-07 2006.196.07:33:35.11:!2006.196.07:34:30 2006.196.07:34:30.00:data_valid=off 2006.196.07:34:30.00:postob 2006.196.07:34:30.19/cable/+6.3328E-03 2006.196.07:34:30.19/wx/30.21,1004.1,85 2006.196.07:34:31.07/fmout-gps/S +3.36E-07 2006.196.07:34:31.07:scan_name=196-0735,k06196,60 2006.196.07:34:31.07:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.196.07:34:31.14#flagr#flagr/antenna,new-source 2006.196.07:34:32.14:checkk5 2006.196.07:34:32.51/chk_autoobs//k5ts1/ autoobs is running! 2006.196.07:34:32.88/chk_autoobs//k5ts2/ autoobs is running! 2006.196.07:34:33.26/chk_autoobs//k5ts3/ autoobs is running! 2006.196.07:34:33.63/chk_autoobs//k5ts4/ autoobs is running! 2006.196.07:34:33.99/chk_obsdata//k5ts1/T1960733??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.07:34:34.37/chk_obsdata//k5ts2/T1960733??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.07:34:34.74/chk_obsdata//k5ts3/T1960733??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.07:34:35.10/chk_obsdata//k5ts4/T1960733??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.07:34:35.79/k5log//k5ts1_log_newline 2006.196.07:34:36.49/k5log//k5ts2_log_newline 2006.196.07:34:37.17/k5log//k5ts3_log_newline 2006.196.07:34:37.85/k5log//k5ts4_log_newline 2006.196.07:34:37.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.196.07:34:37.88:4f8m12a=1 2006.196.07:34:37.88$4f8m12a/echo=on 2006.196.07:34:37.88$4f8m12a/pcalon 2006.196.07:34:37.88$pcalon/"no phase cal control is implemented here 2006.196.07:34:37.88$4f8m12a/"tpicd=stop 2006.196.07:34:37.88$4f8m12a/vc4f8 2006.196.07:34:37.88$vc4f8/valo=1,532.99 2006.196.07:34:37.88#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.196.07:34:37.88#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.196.07:34:37.88#ibcon#ireg 17 cls_cnt 0 2006.196.07:34:37.88#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.196.07:34:37.88#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.196.07:34:37.88#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.196.07:34:37.88#ibcon#enter wrdev, iclass 26, count 0 2006.196.07:34:37.88#ibcon#first serial, iclass 26, count 0 2006.196.07:34:37.88#ibcon#enter sib2, iclass 26, count 0 2006.196.07:34:37.88#ibcon#flushed, iclass 26, count 0 2006.196.07:34:37.88#ibcon#about to write, iclass 26, count 0 2006.196.07:34:37.88#ibcon#wrote, iclass 26, count 0 2006.196.07:34:37.88#ibcon#about to read 3, iclass 26, count 0 2006.196.07:34:37.90#ibcon#read 3, iclass 26, count 0 2006.196.07:34:37.90#ibcon#about to read 4, iclass 26, count 0 2006.196.07:34:37.90#ibcon#read 4, iclass 26, count 0 2006.196.07:34:37.90#ibcon#about to read 5, iclass 26, count 0 2006.196.07:34:37.90#ibcon#read 5, iclass 26, count 0 2006.196.07:34:37.90#ibcon#about to read 6, iclass 26, count 0 2006.196.07:34:37.90#ibcon#read 6, iclass 26, count 0 2006.196.07:34:37.90#ibcon#end of sib2, iclass 26, count 0 2006.196.07:34:37.90#ibcon#*mode == 0, iclass 26, count 0 2006.196.07:34:37.90#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.196.07:34:37.90#ibcon#[26=FRQ=01,532.99\r\n] 2006.196.07:34:37.90#ibcon#*before write, iclass 26, count 0 2006.196.07:34:37.90#ibcon#enter sib2, iclass 26, count 0 2006.196.07:34:37.90#ibcon#flushed, iclass 26, count 0 2006.196.07:34:37.90#ibcon#about to write, iclass 26, count 0 2006.196.07:34:37.90#ibcon#wrote, iclass 26, count 0 2006.196.07:34:37.90#ibcon#about to read 3, iclass 26, count 0 2006.196.07:34:37.95#ibcon#read 3, iclass 26, count 0 2006.196.07:34:37.95#ibcon#about to read 4, iclass 26, count 0 2006.196.07:34:37.95#ibcon#read 4, iclass 26, count 0 2006.196.07:34:37.95#ibcon#about to read 5, iclass 26, count 0 2006.196.07:34:37.95#ibcon#read 5, iclass 26, count 0 2006.196.07:34:37.95#ibcon#about to read 6, iclass 26, count 0 2006.196.07:34:37.95#ibcon#read 6, iclass 26, count 0 2006.196.07:34:37.95#ibcon#end of sib2, iclass 26, count 0 2006.196.07:34:37.95#ibcon#*after write, iclass 26, count 0 2006.196.07:34:37.95#ibcon#*before return 0, iclass 26, count 0 2006.196.07:34:37.95#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.196.07:34:37.95#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.196.07:34:37.95#ibcon#about to clear, iclass 26 cls_cnt 0 2006.196.07:34:37.95#ibcon#cleared, iclass 26 cls_cnt 0 2006.196.07:34:37.95$vc4f8/va=1,8 2006.196.07:34:37.95#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.196.07:34:37.95#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.196.07:34:37.95#ibcon#ireg 11 cls_cnt 2 2006.196.07:34:37.95#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.196.07:34:37.95#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.196.07:34:37.95#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.196.07:34:37.95#ibcon#enter wrdev, iclass 28, count 2 2006.196.07:34:37.95#ibcon#first serial, iclass 28, count 2 2006.196.07:34:37.95#ibcon#enter sib2, iclass 28, count 2 2006.196.07:34:37.95#ibcon#flushed, iclass 28, count 2 2006.196.07:34:37.95#ibcon#about to write, iclass 28, count 2 2006.196.07:34:37.95#ibcon#wrote, iclass 28, count 2 2006.196.07:34:37.95#ibcon#about to read 3, iclass 28, count 2 2006.196.07:34:37.97#ibcon#read 3, iclass 28, count 2 2006.196.07:34:37.97#ibcon#about to read 4, iclass 28, count 2 2006.196.07:34:37.97#ibcon#read 4, iclass 28, count 2 2006.196.07:34:37.97#ibcon#about to read 5, iclass 28, count 2 2006.196.07:34:37.97#ibcon#read 5, iclass 28, count 2 2006.196.07:34:37.97#ibcon#about to read 6, iclass 28, count 2 2006.196.07:34:37.97#ibcon#read 6, iclass 28, count 2 2006.196.07:34:37.97#ibcon#end of sib2, iclass 28, count 2 2006.196.07:34:37.97#ibcon#*mode == 0, iclass 28, count 2 2006.196.07:34:37.97#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.196.07:34:37.97#ibcon#[25=AT01-08\r\n] 2006.196.07:34:37.97#ibcon#*before write, iclass 28, count 2 2006.196.07:34:37.97#ibcon#enter sib2, iclass 28, count 2 2006.196.07:34:37.97#ibcon#flushed, iclass 28, count 2 2006.196.07:34:37.97#ibcon#about to write, iclass 28, count 2 2006.196.07:34:37.97#ibcon#wrote, iclass 28, count 2 2006.196.07:34:37.97#ibcon#about to read 3, iclass 28, count 2 2006.196.07:34:38.00#ibcon#read 3, iclass 28, count 2 2006.196.07:34:38.00#ibcon#about to read 4, iclass 28, count 2 2006.196.07:34:38.00#ibcon#read 4, iclass 28, count 2 2006.196.07:34:38.00#ibcon#about to read 5, iclass 28, count 2 2006.196.07:34:38.00#ibcon#read 5, iclass 28, count 2 2006.196.07:34:38.00#ibcon#about to read 6, iclass 28, count 2 2006.196.07:34:38.00#ibcon#read 6, iclass 28, count 2 2006.196.07:34:38.00#ibcon#end of sib2, iclass 28, count 2 2006.196.07:34:38.00#ibcon#*after write, iclass 28, count 2 2006.196.07:34:38.00#ibcon#*before return 0, iclass 28, count 2 2006.196.07:34:38.00#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.196.07:34:38.00#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.196.07:34:38.00#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.196.07:34:38.00#ibcon#ireg 7 cls_cnt 0 2006.196.07:34:38.00#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.196.07:34:38.12#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.196.07:34:38.12#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.196.07:34:38.12#ibcon#enter wrdev, iclass 28, count 0 2006.196.07:34:38.12#ibcon#first serial, iclass 28, count 0 2006.196.07:34:38.12#ibcon#enter sib2, iclass 28, count 0 2006.196.07:34:38.12#ibcon#flushed, iclass 28, count 0 2006.196.07:34:38.12#ibcon#about to write, iclass 28, count 0 2006.196.07:34:38.12#ibcon#wrote, iclass 28, count 0 2006.196.07:34:38.12#ibcon#about to read 3, iclass 28, count 0 2006.196.07:34:38.14#ibcon#read 3, iclass 28, count 0 2006.196.07:34:38.14#ibcon#about to read 4, iclass 28, count 0 2006.196.07:34:38.14#ibcon#read 4, iclass 28, count 0 2006.196.07:34:38.14#ibcon#about to read 5, iclass 28, count 0 2006.196.07:34:38.14#ibcon#read 5, iclass 28, count 0 2006.196.07:34:38.14#ibcon#about to read 6, iclass 28, count 0 2006.196.07:34:38.14#ibcon#read 6, iclass 28, count 0 2006.196.07:34:38.14#ibcon#end of sib2, iclass 28, count 0 2006.196.07:34:38.14#ibcon#*mode == 0, iclass 28, count 0 2006.196.07:34:38.14#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.196.07:34:38.14#ibcon#[25=USB\r\n] 2006.196.07:34:38.14#ibcon#*before write, iclass 28, count 0 2006.196.07:34:38.14#ibcon#enter sib2, iclass 28, count 0 2006.196.07:34:38.14#ibcon#flushed, iclass 28, count 0 2006.196.07:34:38.14#ibcon#about to write, iclass 28, count 0 2006.196.07:34:38.14#ibcon#wrote, iclass 28, count 0 2006.196.07:34:38.14#ibcon#about to read 3, iclass 28, count 0 2006.196.07:34:38.17#ibcon#read 3, iclass 28, count 0 2006.196.07:34:38.17#ibcon#about to read 4, iclass 28, count 0 2006.196.07:34:38.17#ibcon#read 4, iclass 28, count 0 2006.196.07:34:38.17#ibcon#about to read 5, iclass 28, count 0 2006.196.07:34:38.17#ibcon#read 5, iclass 28, count 0 2006.196.07:34:38.17#ibcon#about to read 6, iclass 28, count 0 2006.196.07:34:38.17#ibcon#read 6, iclass 28, count 0 2006.196.07:34:38.17#ibcon#end of sib2, iclass 28, count 0 2006.196.07:34:38.17#ibcon#*after write, iclass 28, count 0 2006.196.07:34:38.17#ibcon#*before return 0, iclass 28, count 0 2006.196.07:34:38.17#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.196.07:34:38.17#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.196.07:34:38.17#ibcon#about to clear, iclass 28 cls_cnt 0 2006.196.07:34:38.17#ibcon#cleared, iclass 28 cls_cnt 0 2006.196.07:34:38.17$vc4f8/valo=2,572.99 2006.196.07:34:38.17#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.196.07:34:38.17#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.196.07:34:38.17#ibcon#ireg 17 cls_cnt 0 2006.196.07:34:38.17#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.196.07:34:38.17#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.196.07:34:38.17#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.196.07:34:38.17#ibcon#enter wrdev, iclass 30, count 0 2006.196.07:34:38.17#ibcon#first serial, iclass 30, count 0 2006.196.07:34:38.17#ibcon#enter sib2, iclass 30, count 0 2006.196.07:34:38.17#ibcon#flushed, iclass 30, count 0 2006.196.07:34:38.17#ibcon#about to write, iclass 30, count 0 2006.196.07:34:38.17#ibcon#wrote, iclass 30, count 0 2006.196.07:34:38.17#ibcon#about to read 3, iclass 30, count 0 2006.196.07:34:38.19#ibcon#read 3, iclass 30, count 0 2006.196.07:34:38.19#ibcon#about to read 4, iclass 30, count 0 2006.196.07:34:38.19#ibcon#read 4, iclass 30, count 0 2006.196.07:34:38.19#ibcon#about to read 5, iclass 30, count 0 2006.196.07:34:38.19#ibcon#read 5, iclass 30, count 0 2006.196.07:34:38.19#ibcon#about to read 6, iclass 30, count 0 2006.196.07:34:38.19#ibcon#read 6, iclass 30, count 0 2006.196.07:34:38.19#ibcon#end of sib2, iclass 30, count 0 2006.196.07:34:38.19#ibcon#*mode == 0, iclass 30, count 0 2006.196.07:34:38.19#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.196.07:34:38.19#ibcon#[26=FRQ=02,572.99\r\n] 2006.196.07:34:38.19#ibcon#*before write, iclass 30, count 0 2006.196.07:34:38.19#ibcon#enter sib2, iclass 30, count 0 2006.196.07:34:38.19#ibcon#flushed, iclass 30, count 0 2006.196.07:34:38.19#ibcon#about to write, iclass 30, count 0 2006.196.07:34:38.19#ibcon#wrote, iclass 30, count 0 2006.196.07:34:38.19#ibcon#about to read 3, iclass 30, count 0 2006.196.07:34:38.24#ibcon#read 3, iclass 30, count 0 2006.196.07:34:38.24#ibcon#about to read 4, iclass 30, count 0 2006.196.07:34:38.24#ibcon#read 4, iclass 30, count 0 2006.196.07:34:38.24#ibcon#about to read 5, iclass 30, count 0 2006.196.07:34:38.24#ibcon#read 5, iclass 30, count 0 2006.196.07:34:38.24#ibcon#about to read 6, iclass 30, count 0 2006.196.07:34:38.24#ibcon#read 6, iclass 30, count 0 2006.196.07:34:38.24#ibcon#end of sib2, iclass 30, count 0 2006.196.07:34:38.24#ibcon#*after write, iclass 30, count 0 2006.196.07:34:38.24#ibcon#*before return 0, iclass 30, count 0 2006.196.07:34:38.24#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.196.07:34:38.24#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.196.07:34:38.24#ibcon#about to clear, iclass 30 cls_cnt 0 2006.196.07:34:38.24#ibcon#cleared, iclass 30 cls_cnt 0 2006.196.07:34:38.24$vc4f8/va=2,7 2006.196.07:34:38.24#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.196.07:34:38.24#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.196.07:34:38.24#ibcon#ireg 11 cls_cnt 2 2006.196.07:34:38.24#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.196.07:34:38.29#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.196.07:34:38.29#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.196.07:34:38.29#ibcon#enter wrdev, iclass 32, count 2 2006.196.07:34:38.29#ibcon#first serial, iclass 32, count 2 2006.196.07:34:38.29#ibcon#enter sib2, iclass 32, count 2 2006.196.07:34:38.29#ibcon#flushed, iclass 32, count 2 2006.196.07:34:38.29#ibcon#about to write, iclass 32, count 2 2006.196.07:34:38.29#ibcon#wrote, iclass 32, count 2 2006.196.07:34:38.29#ibcon#about to read 3, iclass 32, count 2 2006.196.07:34:38.31#ibcon#read 3, iclass 32, count 2 2006.196.07:34:38.31#ibcon#about to read 4, iclass 32, count 2 2006.196.07:34:38.31#ibcon#read 4, iclass 32, count 2 2006.196.07:34:38.31#ibcon#about to read 5, iclass 32, count 2 2006.196.07:34:38.31#ibcon#read 5, iclass 32, count 2 2006.196.07:34:38.31#ibcon#about to read 6, iclass 32, count 2 2006.196.07:34:38.31#ibcon#read 6, iclass 32, count 2 2006.196.07:34:38.31#ibcon#end of sib2, iclass 32, count 2 2006.196.07:34:38.31#ibcon#*mode == 0, iclass 32, count 2 2006.196.07:34:38.31#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.196.07:34:38.31#ibcon#[25=AT02-07\r\n] 2006.196.07:34:38.31#ibcon#*before write, iclass 32, count 2 2006.196.07:34:38.31#ibcon#enter sib2, iclass 32, count 2 2006.196.07:34:38.31#ibcon#flushed, iclass 32, count 2 2006.196.07:34:38.31#ibcon#about to write, iclass 32, count 2 2006.196.07:34:38.31#ibcon#wrote, iclass 32, count 2 2006.196.07:34:38.31#ibcon#about to read 3, iclass 32, count 2 2006.196.07:34:38.34#ibcon#read 3, iclass 32, count 2 2006.196.07:34:38.34#ibcon#about to read 4, iclass 32, count 2 2006.196.07:34:38.34#ibcon#read 4, iclass 32, count 2 2006.196.07:34:38.34#ibcon#about to read 5, iclass 32, count 2 2006.196.07:34:38.34#ibcon#read 5, iclass 32, count 2 2006.196.07:34:38.34#ibcon#about to read 6, iclass 32, count 2 2006.196.07:34:38.34#ibcon#read 6, iclass 32, count 2 2006.196.07:34:38.34#ibcon#end of sib2, iclass 32, count 2 2006.196.07:34:38.34#ibcon#*after write, iclass 32, count 2 2006.196.07:34:38.34#ibcon#*before return 0, iclass 32, count 2 2006.196.07:34:38.34#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.196.07:34:38.34#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.196.07:34:38.34#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.196.07:34:38.34#ibcon#ireg 7 cls_cnt 0 2006.196.07:34:38.34#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.196.07:34:38.46#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.196.07:34:38.46#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.196.07:34:38.46#ibcon#enter wrdev, iclass 32, count 0 2006.196.07:34:38.46#ibcon#first serial, iclass 32, count 0 2006.196.07:34:38.46#ibcon#enter sib2, iclass 32, count 0 2006.196.07:34:38.46#ibcon#flushed, iclass 32, count 0 2006.196.07:34:38.46#ibcon#about to write, iclass 32, count 0 2006.196.07:34:38.46#ibcon#wrote, iclass 32, count 0 2006.196.07:34:38.46#ibcon#about to read 3, iclass 32, count 0 2006.196.07:34:38.48#ibcon#read 3, iclass 32, count 0 2006.196.07:34:38.48#ibcon#about to read 4, iclass 32, count 0 2006.196.07:34:38.48#ibcon#read 4, iclass 32, count 0 2006.196.07:34:38.48#ibcon#about to read 5, iclass 32, count 0 2006.196.07:34:38.48#ibcon#read 5, iclass 32, count 0 2006.196.07:34:38.48#ibcon#about to read 6, iclass 32, count 0 2006.196.07:34:38.48#ibcon#read 6, iclass 32, count 0 2006.196.07:34:38.48#ibcon#end of sib2, iclass 32, count 0 2006.196.07:34:38.48#ibcon#*mode == 0, iclass 32, count 0 2006.196.07:34:38.48#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.196.07:34:38.48#ibcon#[25=USB\r\n] 2006.196.07:34:38.48#ibcon#*before write, iclass 32, count 0 2006.196.07:34:38.48#ibcon#enter sib2, iclass 32, count 0 2006.196.07:34:38.48#ibcon#flushed, iclass 32, count 0 2006.196.07:34:38.48#ibcon#about to write, iclass 32, count 0 2006.196.07:34:38.48#ibcon#wrote, iclass 32, count 0 2006.196.07:34:38.48#ibcon#about to read 3, iclass 32, count 0 2006.196.07:34:38.51#ibcon#read 3, iclass 32, count 0 2006.196.07:34:38.51#ibcon#about to read 4, iclass 32, count 0 2006.196.07:34:38.51#ibcon#read 4, iclass 32, count 0 2006.196.07:34:38.51#ibcon#about to read 5, iclass 32, count 0 2006.196.07:34:38.51#ibcon#read 5, iclass 32, count 0 2006.196.07:34:38.51#ibcon#about to read 6, iclass 32, count 0 2006.196.07:34:38.51#ibcon#read 6, iclass 32, count 0 2006.196.07:34:38.51#ibcon#end of sib2, iclass 32, count 0 2006.196.07:34:38.51#ibcon#*after write, iclass 32, count 0 2006.196.07:34:38.51#ibcon#*before return 0, iclass 32, count 0 2006.196.07:34:38.51#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.196.07:34:38.51#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.196.07:34:38.51#ibcon#about to clear, iclass 32 cls_cnt 0 2006.196.07:34:38.51#ibcon#cleared, iclass 32 cls_cnt 0 2006.196.07:34:38.51$vc4f8/valo=3,672.99 2006.196.07:34:38.51#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.196.07:34:38.51#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.196.07:34:38.51#ibcon#ireg 17 cls_cnt 0 2006.196.07:34:38.51#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.196.07:34:38.51#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.196.07:34:38.51#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.196.07:34:38.51#ibcon#enter wrdev, iclass 34, count 0 2006.196.07:34:38.51#ibcon#first serial, iclass 34, count 0 2006.196.07:34:38.51#ibcon#enter sib2, iclass 34, count 0 2006.196.07:34:38.51#ibcon#flushed, iclass 34, count 0 2006.196.07:34:38.51#ibcon#about to write, iclass 34, count 0 2006.196.07:34:38.51#ibcon#wrote, iclass 34, count 0 2006.196.07:34:38.51#ibcon#about to read 3, iclass 34, count 0 2006.196.07:34:38.53#ibcon#read 3, iclass 34, count 0 2006.196.07:34:38.53#ibcon#about to read 4, iclass 34, count 0 2006.196.07:34:38.53#ibcon#read 4, iclass 34, count 0 2006.196.07:34:38.53#ibcon#about to read 5, iclass 34, count 0 2006.196.07:34:38.53#ibcon#read 5, iclass 34, count 0 2006.196.07:34:38.53#ibcon#about to read 6, iclass 34, count 0 2006.196.07:34:38.53#ibcon#read 6, iclass 34, count 0 2006.196.07:34:38.53#ibcon#end of sib2, iclass 34, count 0 2006.196.07:34:38.53#ibcon#*mode == 0, iclass 34, count 0 2006.196.07:34:38.53#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.196.07:34:38.53#ibcon#[26=FRQ=03,672.99\r\n] 2006.196.07:34:38.53#ibcon#*before write, iclass 34, count 0 2006.196.07:34:38.53#ibcon#enter sib2, iclass 34, count 0 2006.196.07:34:38.53#ibcon#flushed, iclass 34, count 0 2006.196.07:34:38.53#ibcon#about to write, iclass 34, count 0 2006.196.07:34:38.53#ibcon#wrote, iclass 34, count 0 2006.196.07:34:38.53#ibcon#about to read 3, iclass 34, count 0 2006.196.07:34:38.57#ibcon#read 3, iclass 34, count 0 2006.196.07:34:38.57#ibcon#about to read 4, iclass 34, count 0 2006.196.07:34:38.57#ibcon#read 4, iclass 34, count 0 2006.196.07:34:38.57#ibcon#about to read 5, iclass 34, count 0 2006.196.07:34:38.57#ibcon#read 5, iclass 34, count 0 2006.196.07:34:38.57#ibcon#about to read 6, iclass 34, count 0 2006.196.07:34:38.57#ibcon#read 6, iclass 34, count 0 2006.196.07:34:38.57#ibcon#end of sib2, iclass 34, count 0 2006.196.07:34:38.57#ibcon#*after write, iclass 34, count 0 2006.196.07:34:38.57#ibcon#*before return 0, iclass 34, count 0 2006.196.07:34:38.57#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.196.07:34:38.57#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.196.07:34:38.57#ibcon#about to clear, iclass 34 cls_cnt 0 2006.196.07:34:38.57#ibcon#cleared, iclass 34 cls_cnt 0 2006.196.07:34:38.57$vc4f8/va=3,6 2006.196.07:34:38.57#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.196.07:34:38.57#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.196.07:34:38.57#ibcon#ireg 11 cls_cnt 2 2006.196.07:34:38.57#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.196.07:34:38.63#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.196.07:34:38.63#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.196.07:34:38.63#ibcon#enter wrdev, iclass 36, count 2 2006.196.07:34:38.63#ibcon#first serial, iclass 36, count 2 2006.196.07:34:38.63#ibcon#enter sib2, iclass 36, count 2 2006.196.07:34:38.63#ibcon#flushed, iclass 36, count 2 2006.196.07:34:38.63#ibcon#about to write, iclass 36, count 2 2006.196.07:34:38.63#ibcon#wrote, iclass 36, count 2 2006.196.07:34:38.63#ibcon#about to read 3, iclass 36, count 2 2006.196.07:34:38.65#ibcon#read 3, iclass 36, count 2 2006.196.07:34:38.65#ibcon#about to read 4, iclass 36, count 2 2006.196.07:34:38.65#ibcon#read 4, iclass 36, count 2 2006.196.07:34:38.65#ibcon#about to read 5, iclass 36, count 2 2006.196.07:34:38.65#ibcon#read 5, iclass 36, count 2 2006.196.07:34:38.65#ibcon#about to read 6, iclass 36, count 2 2006.196.07:34:38.65#ibcon#read 6, iclass 36, count 2 2006.196.07:34:38.65#ibcon#end of sib2, iclass 36, count 2 2006.196.07:34:38.65#ibcon#*mode == 0, iclass 36, count 2 2006.196.07:34:38.65#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.196.07:34:38.65#ibcon#[25=AT03-06\r\n] 2006.196.07:34:38.65#ibcon#*before write, iclass 36, count 2 2006.196.07:34:38.65#ibcon#enter sib2, iclass 36, count 2 2006.196.07:34:38.65#ibcon#flushed, iclass 36, count 2 2006.196.07:34:38.65#ibcon#about to write, iclass 36, count 2 2006.196.07:34:38.65#ibcon#wrote, iclass 36, count 2 2006.196.07:34:38.65#ibcon#about to read 3, iclass 36, count 2 2006.196.07:34:38.68#ibcon#read 3, iclass 36, count 2 2006.196.07:34:38.68#ibcon#about to read 4, iclass 36, count 2 2006.196.07:34:38.68#ibcon#read 4, iclass 36, count 2 2006.196.07:34:38.68#ibcon#about to read 5, iclass 36, count 2 2006.196.07:34:38.68#ibcon#read 5, iclass 36, count 2 2006.196.07:34:38.68#ibcon#about to read 6, iclass 36, count 2 2006.196.07:34:38.68#ibcon#read 6, iclass 36, count 2 2006.196.07:34:38.68#ibcon#end of sib2, iclass 36, count 2 2006.196.07:34:38.68#ibcon#*after write, iclass 36, count 2 2006.196.07:34:38.68#ibcon#*before return 0, iclass 36, count 2 2006.196.07:34:38.68#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.196.07:34:38.68#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.196.07:34:38.68#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.196.07:34:38.68#ibcon#ireg 7 cls_cnt 0 2006.196.07:34:38.68#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.196.07:34:38.80#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.196.07:34:38.80#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.196.07:34:38.80#ibcon#enter wrdev, iclass 36, count 0 2006.196.07:34:38.80#ibcon#first serial, iclass 36, count 0 2006.196.07:34:38.80#ibcon#enter sib2, iclass 36, count 0 2006.196.07:34:38.80#ibcon#flushed, iclass 36, count 0 2006.196.07:34:38.80#ibcon#about to write, iclass 36, count 0 2006.196.07:34:38.80#ibcon#wrote, iclass 36, count 0 2006.196.07:34:38.80#ibcon#about to read 3, iclass 36, count 0 2006.196.07:34:38.82#ibcon#read 3, iclass 36, count 0 2006.196.07:34:38.82#ibcon#about to read 4, iclass 36, count 0 2006.196.07:34:38.82#ibcon#read 4, iclass 36, count 0 2006.196.07:34:38.82#ibcon#about to read 5, iclass 36, count 0 2006.196.07:34:38.82#ibcon#read 5, iclass 36, count 0 2006.196.07:34:38.82#ibcon#about to read 6, iclass 36, count 0 2006.196.07:34:38.82#ibcon#read 6, iclass 36, count 0 2006.196.07:34:38.82#ibcon#end of sib2, iclass 36, count 0 2006.196.07:34:38.82#ibcon#*mode == 0, iclass 36, count 0 2006.196.07:34:38.82#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.196.07:34:38.82#ibcon#[25=USB\r\n] 2006.196.07:34:38.82#ibcon#*before write, iclass 36, count 0 2006.196.07:34:38.82#ibcon#enter sib2, iclass 36, count 0 2006.196.07:34:38.82#ibcon#flushed, iclass 36, count 0 2006.196.07:34:38.82#ibcon#about to write, iclass 36, count 0 2006.196.07:34:38.82#ibcon#wrote, iclass 36, count 0 2006.196.07:34:38.82#ibcon#about to read 3, iclass 36, count 0 2006.196.07:34:38.85#ibcon#read 3, iclass 36, count 0 2006.196.07:34:38.85#ibcon#about to read 4, iclass 36, count 0 2006.196.07:34:38.85#ibcon#read 4, iclass 36, count 0 2006.196.07:34:38.85#ibcon#about to read 5, iclass 36, count 0 2006.196.07:34:38.85#ibcon#read 5, iclass 36, count 0 2006.196.07:34:38.85#ibcon#about to read 6, iclass 36, count 0 2006.196.07:34:38.85#ibcon#read 6, iclass 36, count 0 2006.196.07:34:38.85#ibcon#end of sib2, iclass 36, count 0 2006.196.07:34:38.85#ibcon#*after write, iclass 36, count 0 2006.196.07:34:38.85#ibcon#*before return 0, iclass 36, count 0 2006.196.07:34:38.85#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.196.07:34:38.85#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.196.07:34:38.85#ibcon#about to clear, iclass 36 cls_cnt 0 2006.196.07:34:38.85#ibcon#cleared, iclass 36 cls_cnt 0 2006.196.07:34:38.85$vc4f8/valo=4,832.99 2006.196.07:34:38.85#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.196.07:34:38.85#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.196.07:34:38.85#ibcon#ireg 17 cls_cnt 0 2006.196.07:34:38.85#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.196.07:34:38.85#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.196.07:34:38.85#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.196.07:34:38.85#ibcon#enter wrdev, iclass 38, count 0 2006.196.07:34:38.85#ibcon#first serial, iclass 38, count 0 2006.196.07:34:38.85#ibcon#enter sib2, iclass 38, count 0 2006.196.07:34:38.85#ibcon#flushed, iclass 38, count 0 2006.196.07:34:38.85#ibcon#about to write, iclass 38, count 0 2006.196.07:34:38.85#ibcon#wrote, iclass 38, count 0 2006.196.07:34:38.85#ibcon#about to read 3, iclass 38, count 0 2006.196.07:34:38.87#ibcon#read 3, iclass 38, count 0 2006.196.07:34:38.87#ibcon#about to read 4, iclass 38, count 0 2006.196.07:34:38.87#ibcon#read 4, iclass 38, count 0 2006.196.07:34:38.87#ibcon#about to read 5, iclass 38, count 0 2006.196.07:34:38.87#ibcon#read 5, iclass 38, count 0 2006.196.07:34:38.87#ibcon#about to read 6, iclass 38, count 0 2006.196.07:34:38.87#ibcon#read 6, iclass 38, count 0 2006.196.07:34:38.87#ibcon#end of sib2, iclass 38, count 0 2006.196.07:34:38.87#ibcon#*mode == 0, iclass 38, count 0 2006.196.07:34:38.87#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.196.07:34:38.87#ibcon#[26=FRQ=04,832.99\r\n] 2006.196.07:34:38.87#ibcon#*before write, iclass 38, count 0 2006.196.07:34:38.87#ibcon#enter sib2, iclass 38, count 0 2006.196.07:34:38.87#ibcon#flushed, iclass 38, count 0 2006.196.07:34:38.87#ibcon#about to write, iclass 38, count 0 2006.196.07:34:38.87#ibcon#wrote, iclass 38, count 0 2006.196.07:34:38.87#ibcon#about to read 3, iclass 38, count 0 2006.196.07:34:38.91#ibcon#read 3, iclass 38, count 0 2006.196.07:34:38.91#ibcon#about to read 4, iclass 38, count 0 2006.196.07:34:38.91#ibcon#read 4, iclass 38, count 0 2006.196.07:34:38.91#ibcon#about to read 5, iclass 38, count 0 2006.196.07:34:38.91#ibcon#read 5, iclass 38, count 0 2006.196.07:34:38.91#ibcon#about to read 6, iclass 38, count 0 2006.196.07:34:38.91#ibcon#read 6, iclass 38, count 0 2006.196.07:34:38.91#ibcon#end of sib2, iclass 38, count 0 2006.196.07:34:38.91#ibcon#*after write, iclass 38, count 0 2006.196.07:34:38.91#ibcon#*before return 0, iclass 38, count 0 2006.196.07:34:38.91#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.196.07:34:38.91#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.196.07:34:38.91#ibcon#about to clear, iclass 38 cls_cnt 0 2006.196.07:34:38.91#ibcon#cleared, iclass 38 cls_cnt 0 2006.196.07:34:38.91$vc4f8/va=4,7 2006.196.07:34:38.91#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.196.07:34:38.91#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.196.07:34:38.91#ibcon#ireg 11 cls_cnt 2 2006.196.07:34:38.91#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.196.07:34:38.97#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.196.07:34:38.97#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.196.07:34:38.97#ibcon#enter wrdev, iclass 40, count 2 2006.196.07:34:38.97#ibcon#first serial, iclass 40, count 2 2006.196.07:34:38.97#ibcon#enter sib2, iclass 40, count 2 2006.196.07:34:38.97#ibcon#flushed, iclass 40, count 2 2006.196.07:34:38.97#ibcon#about to write, iclass 40, count 2 2006.196.07:34:38.97#ibcon#wrote, iclass 40, count 2 2006.196.07:34:38.97#ibcon#about to read 3, iclass 40, count 2 2006.196.07:34:38.99#ibcon#read 3, iclass 40, count 2 2006.196.07:34:38.99#ibcon#about to read 4, iclass 40, count 2 2006.196.07:34:38.99#ibcon#read 4, iclass 40, count 2 2006.196.07:34:38.99#ibcon#about to read 5, iclass 40, count 2 2006.196.07:34:38.99#ibcon#read 5, iclass 40, count 2 2006.196.07:34:38.99#ibcon#about to read 6, iclass 40, count 2 2006.196.07:34:38.99#ibcon#read 6, iclass 40, count 2 2006.196.07:34:38.99#ibcon#end of sib2, iclass 40, count 2 2006.196.07:34:38.99#ibcon#*mode == 0, iclass 40, count 2 2006.196.07:34:38.99#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.196.07:34:38.99#ibcon#[25=AT04-07\r\n] 2006.196.07:34:38.99#ibcon#*before write, iclass 40, count 2 2006.196.07:34:38.99#ibcon#enter sib2, iclass 40, count 2 2006.196.07:34:38.99#ibcon#flushed, iclass 40, count 2 2006.196.07:34:38.99#ibcon#about to write, iclass 40, count 2 2006.196.07:34:38.99#ibcon#wrote, iclass 40, count 2 2006.196.07:34:38.99#ibcon#about to read 3, iclass 40, count 2 2006.196.07:34:39.02#ibcon#read 3, iclass 40, count 2 2006.196.07:34:39.02#ibcon#about to read 4, iclass 40, count 2 2006.196.07:34:39.02#ibcon#read 4, iclass 40, count 2 2006.196.07:34:39.02#ibcon#about to read 5, iclass 40, count 2 2006.196.07:34:39.02#ibcon#read 5, iclass 40, count 2 2006.196.07:34:39.02#ibcon#about to read 6, iclass 40, count 2 2006.196.07:34:39.02#ibcon#read 6, iclass 40, count 2 2006.196.07:34:39.02#ibcon#end of sib2, iclass 40, count 2 2006.196.07:34:39.02#ibcon#*after write, iclass 40, count 2 2006.196.07:34:39.02#ibcon#*before return 0, iclass 40, count 2 2006.196.07:34:39.02#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.196.07:34:39.02#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.196.07:34:39.02#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.196.07:34:39.02#ibcon#ireg 7 cls_cnt 0 2006.196.07:34:39.02#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.196.07:34:39.14#abcon#<5=/04 4.0 6.7 30.21 861004.1\r\n> 2006.196.07:34:39.14#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.196.07:34:39.14#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.196.07:34:39.14#ibcon#enter wrdev, iclass 40, count 0 2006.196.07:34:39.14#ibcon#first serial, iclass 40, count 0 2006.196.07:34:39.14#ibcon#enter sib2, iclass 40, count 0 2006.196.07:34:39.14#ibcon#flushed, iclass 40, count 0 2006.196.07:34:39.14#ibcon#about to write, iclass 40, count 0 2006.196.07:34:39.14#ibcon#wrote, iclass 40, count 0 2006.196.07:34:39.14#ibcon#about to read 3, iclass 40, count 0 2006.196.07:34:39.16#abcon#{5=INTERFACE CLEAR} 2006.196.07:34:39.16#ibcon#read 3, iclass 40, count 0 2006.196.07:34:39.16#ibcon#about to read 4, iclass 40, count 0 2006.196.07:34:39.16#ibcon#read 4, iclass 40, count 0 2006.196.07:34:39.16#ibcon#about to read 5, iclass 40, count 0 2006.196.07:34:39.16#ibcon#read 5, iclass 40, count 0 2006.196.07:34:39.16#ibcon#about to read 6, iclass 40, count 0 2006.196.07:34:39.16#ibcon#read 6, iclass 40, count 0 2006.196.07:34:39.16#ibcon#end of sib2, iclass 40, count 0 2006.196.07:34:39.16#ibcon#*mode == 0, iclass 40, count 0 2006.196.07:34:39.16#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.196.07:34:39.16#ibcon#[25=USB\r\n] 2006.196.07:34:39.16#ibcon#*before write, iclass 40, count 0 2006.196.07:34:39.16#ibcon#enter sib2, iclass 40, count 0 2006.196.07:34:39.16#ibcon#flushed, iclass 40, count 0 2006.196.07:34:39.16#ibcon#about to write, iclass 40, count 0 2006.196.07:34:39.16#ibcon#wrote, iclass 40, count 0 2006.196.07:34:39.16#ibcon#about to read 3, iclass 40, count 0 2006.196.07:34:39.19#ibcon#read 3, iclass 40, count 0 2006.196.07:34:39.19#ibcon#about to read 4, iclass 40, count 0 2006.196.07:34:39.19#ibcon#read 4, iclass 40, count 0 2006.196.07:34:39.19#ibcon#about to read 5, iclass 40, count 0 2006.196.07:34:39.19#ibcon#read 5, iclass 40, count 0 2006.196.07:34:39.19#ibcon#about to read 6, iclass 40, count 0 2006.196.07:34:39.19#ibcon#read 6, iclass 40, count 0 2006.196.07:34:39.19#ibcon#end of sib2, iclass 40, count 0 2006.196.07:34:39.19#ibcon#*after write, iclass 40, count 0 2006.196.07:34:39.19#ibcon#*before return 0, iclass 40, count 0 2006.196.07:34:39.19#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.196.07:34:39.19#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.196.07:34:39.19#ibcon#about to clear, iclass 40 cls_cnt 0 2006.196.07:34:39.19#ibcon#cleared, iclass 40 cls_cnt 0 2006.196.07:34:39.19$vc4f8/valo=5,652.99 2006.196.07:34:39.19#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.196.07:34:39.19#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.196.07:34:39.19#ibcon#ireg 17 cls_cnt 0 2006.196.07:34:39.19#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.196.07:34:39.19#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.196.07:34:39.19#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.196.07:34:39.19#ibcon#enter wrdev, iclass 7, count 0 2006.196.07:34:39.19#ibcon#first serial, iclass 7, count 0 2006.196.07:34:39.19#ibcon#enter sib2, iclass 7, count 0 2006.196.07:34:39.19#ibcon#flushed, iclass 7, count 0 2006.196.07:34:39.19#ibcon#about to write, iclass 7, count 0 2006.196.07:34:39.19#ibcon#wrote, iclass 7, count 0 2006.196.07:34:39.19#ibcon#about to read 3, iclass 7, count 0 2006.196.07:34:39.21#ibcon#read 3, iclass 7, count 0 2006.196.07:34:39.21#ibcon#about to read 4, iclass 7, count 0 2006.196.07:34:39.21#ibcon#read 4, iclass 7, count 0 2006.196.07:34:39.21#ibcon#about to read 5, iclass 7, count 0 2006.196.07:34:39.21#ibcon#read 5, iclass 7, count 0 2006.196.07:34:39.21#ibcon#about to read 6, iclass 7, count 0 2006.196.07:34:39.21#ibcon#read 6, iclass 7, count 0 2006.196.07:34:39.21#ibcon#end of sib2, iclass 7, count 0 2006.196.07:34:39.21#ibcon#*mode == 0, iclass 7, count 0 2006.196.07:34:39.21#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.196.07:34:39.21#ibcon#[26=FRQ=05,652.99\r\n] 2006.196.07:34:39.21#ibcon#*before write, iclass 7, count 0 2006.196.07:34:39.21#ibcon#enter sib2, iclass 7, count 0 2006.196.07:34:39.21#ibcon#flushed, iclass 7, count 0 2006.196.07:34:39.21#ibcon#about to write, iclass 7, count 0 2006.196.07:34:39.21#ibcon#wrote, iclass 7, count 0 2006.196.07:34:39.21#ibcon#about to read 3, iclass 7, count 0 2006.196.07:34:39.22#abcon#[5=S1D000X0/0*\r\n] 2006.196.07:34:39.25#ibcon#read 3, iclass 7, count 0 2006.196.07:34:39.25#ibcon#about to read 4, iclass 7, count 0 2006.196.07:34:39.25#ibcon#read 4, iclass 7, count 0 2006.196.07:34:39.25#ibcon#about to read 5, iclass 7, count 0 2006.196.07:34:39.25#ibcon#read 5, iclass 7, count 0 2006.196.07:34:39.25#ibcon#about to read 6, iclass 7, count 0 2006.196.07:34:39.25#ibcon#read 6, iclass 7, count 0 2006.196.07:34:39.25#ibcon#end of sib2, iclass 7, count 0 2006.196.07:34:39.25#ibcon#*after write, iclass 7, count 0 2006.196.07:34:39.25#ibcon#*before return 0, iclass 7, count 0 2006.196.07:34:39.25#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.196.07:34:39.25#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.196.07:34:39.25#ibcon#about to clear, iclass 7 cls_cnt 0 2006.196.07:34:39.25#ibcon#cleared, iclass 7 cls_cnt 0 2006.196.07:34:39.25$vc4f8/va=5,7 2006.196.07:34:39.25#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.196.07:34:39.25#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.196.07:34:39.25#ibcon#ireg 11 cls_cnt 2 2006.196.07:34:39.25#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.196.07:34:39.31#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.196.07:34:39.31#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.196.07:34:39.31#ibcon#enter wrdev, iclass 12, count 2 2006.196.07:34:39.31#ibcon#first serial, iclass 12, count 2 2006.196.07:34:39.31#ibcon#enter sib2, iclass 12, count 2 2006.196.07:34:39.31#ibcon#flushed, iclass 12, count 2 2006.196.07:34:39.31#ibcon#about to write, iclass 12, count 2 2006.196.07:34:39.31#ibcon#wrote, iclass 12, count 2 2006.196.07:34:39.31#ibcon#about to read 3, iclass 12, count 2 2006.196.07:34:39.33#ibcon#read 3, iclass 12, count 2 2006.196.07:34:39.33#ibcon#about to read 4, iclass 12, count 2 2006.196.07:34:39.33#ibcon#read 4, iclass 12, count 2 2006.196.07:34:39.33#ibcon#about to read 5, iclass 12, count 2 2006.196.07:34:39.33#ibcon#read 5, iclass 12, count 2 2006.196.07:34:39.33#ibcon#about to read 6, iclass 12, count 2 2006.196.07:34:39.33#ibcon#read 6, iclass 12, count 2 2006.196.07:34:39.33#ibcon#end of sib2, iclass 12, count 2 2006.196.07:34:39.33#ibcon#*mode == 0, iclass 12, count 2 2006.196.07:34:39.33#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.196.07:34:39.33#ibcon#[25=AT05-07\r\n] 2006.196.07:34:39.33#ibcon#*before write, iclass 12, count 2 2006.196.07:34:39.33#ibcon#enter sib2, iclass 12, count 2 2006.196.07:34:39.33#ibcon#flushed, iclass 12, count 2 2006.196.07:34:39.33#ibcon#about to write, iclass 12, count 2 2006.196.07:34:39.33#ibcon#wrote, iclass 12, count 2 2006.196.07:34:39.33#ibcon#about to read 3, iclass 12, count 2 2006.196.07:34:39.36#ibcon#read 3, iclass 12, count 2 2006.196.07:34:39.36#ibcon#about to read 4, iclass 12, count 2 2006.196.07:34:39.36#ibcon#read 4, iclass 12, count 2 2006.196.07:34:39.36#ibcon#about to read 5, iclass 12, count 2 2006.196.07:34:39.36#ibcon#read 5, iclass 12, count 2 2006.196.07:34:39.36#ibcon#about to read 6, iclass 12, count 2 2006.196.07:34:39.36#ibcon#read 6, iclass 12, count 2 2006.196.07:34:39.36#ibcon#end of sib2, iclass 12, count 2 2006.196.07:34:39.36#ibcon#*after write, iclass 12, count 2 2006.196.07:34:39.36#ibcon#*before return 0, iclass 12, count 2 2006.196.07:34:39.36#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.196.07:34:39.36#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.196.07:34:39.36#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.196.07:34:39.36#ibcon#ireg 7 cls_cnt 0 2006.196.07:34:39.36#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.196.07:34:39.48#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.196.07:34:39.48#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.196.07:34:39.48#ibcon#enter wrdev, iclass 12, count 0 2006.196.07:34:39.48#ibcon#first serial, iclass 12, count 0 2006.196.07:34:39.48#ibcon#enter sib2, iclass 12, count 0 2006.196.07:34:39.48#ibcon#flushed, iclass 12, count 0 2006.196.07:34:39.48#ibcon#about to write, iclass 12, count 0 2006.196.07:34:39.48#ibcon#wrote, iclass 12, count 0 2006.196.07:34:39.48#ibcon#about to read 3, iclass 12, count 0 2006.196.07:34:39.50#ibcon#read 3, iclass 12, count 0 2006.196.07:34:39.50#ibcon#about to read 4, iclass 12, count 0 2006.196.07:34:39.50#ibcon#read 4, iclass 12, count 0 2006.196.07:34:39.50#ibcon#about to read 5, iclass 12, count 0 2006.196.07:34:39.50#ibcon#read 5, iclass 12, count 0 2006.196.07:34:39.50#ibcon#about to read 6, iclass 12, count 0 2006.196.07:34:39.50#ibcon#read 6, iclass 12, count 0 2006.196.07:34:39.50#ibcon#end of sib2, iclass 12, count 0 2006.196.07:34:39.50#ibcon#*mode == 0, iclass 12, count 0 2006.196.07:34:39.50#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.196.07:34:39.50#ibcon#[25=USB\r\n] 2006.196.07:34:39.50#ibcon#*before write, iclass 12, count 0 2006.196.07:34:39.50#ibcon#enter sib2, iclass 12, count 0 2006.196.07:34:39.50#ibcon#flushed, iclass 12, count 0 2006.196.07:34:39.50#ibcon#about to write, iclass 12, count 0 2006.196.07:34:39.50#ibcon#wrote, iclass 12, count 0 2006.196.07:34:39.50#ibcon#about to read 3, iclass 12, count 0 2006.196.07:34:39.53#ibcon#read 3, iclass 12, count 0 2006.196.07:34:39.53#ibcon#about to read 4, iclass 12, count 0 2006.196.07:34:39.53#ibcon#read 4, iclass 12, count 0 2006.196.07:34:39.53#ibcon#about to read 5, iclass 12, count 0 2006.196.07:34:39.53#ibcon#read 5, iclass 12, count 0 2006.196.07:34:39.53#ibcon#about to read 6, iclass 12, count 0 2006.196.07:34:39.53#ibcon#read 6, iclass 12, count 0 2006.196.07:34:39.53#ibcon#end of sib2, iclass 12, count 0 2006.196.07:34:39.53#ibcon#*after write, iclass 12, count 0 2006.196.07:34:39.53#ibcon#*before return 0, iclass 12, count 0 2006.196.07:34:39.53#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.196.07:34:39.53#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.196.07:34:39.53#ibcon#about to clear, iclass 12 cls_cnt 0 2006.196.07:34:39.53#ibcon#cleared, iclass 12 cls_cnt 0 2006.196.07:34:39.53$vc4f8/valo=6,772.99 2006.196.07:34:39.53#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.196.07:34:39.53#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.196.07:34:39.53#ibcon#ireg 17 cls_cnt 0 2006.196.07:34:39.53#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.196.07:34:39.53#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.196.07:34:39.53#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.196.07:34:39.53#ibcon#enter wrdev, iclass 14, count 0 2006.196.07:34:39.53#ibcon#first serial, iclass 14, count 0 2006.196.07:34:39.53#ibcon#enter sib2, iclass 14, count 0 2006.196.07:34:39.53#ibcon#flushed, iclass 14, count 0 2006.196.07:34:39.53#ibcon#about to write, iclass 14, count 0 2006.196.07:34:39.53#ibcon#wrote, iclass 14, count 0 2006.196.07:34:39.53#ibcon#about to read 3, iclass 14, count 0 2006.196.07:34:39.55#ibcon#read 3, iclass 14, count 0 2006.196.07:34:39.55#ibcon#about to read 4, iclass 14, count 0 2006.196.07:34:39.55#ibcon#read 4, iclass 14, count 0 2006.196.07:34:39.55#ibcon#about to read 5, iclass 14, count 0 2006.196.07:34:39.55#ibcon#read 5, iclass 14, count 0 2006.196.07:34:39.55#ibcon#about to read 6, iclass 14, count 0 2006.196.07:34:39.55#ibcon#read 6, iclass 14, count 0 2006.196.07:34:39.55#ibcon#end of sib2, iclass 14, count 0 2006.196.07:34:39.55#ibcon#*mode == 0, iclass 14, count 0 2006.196.07:34:39.55#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.196.07:34:39.55#ibcon#[26=FRQ=06,772.99\r\n] 2006.196.07:34:39.55#ibcon#*before write, iclass 14, count 0 2006.196.07:34:39.55#ibcon#enter sib2, iclass 14, count 0 2006.196.07:34:39.55#ibcon#flushed, iclass 14, count 0 2006.196.07:34:39.55#ibcon#about to write, iclass 14, count 0 2006.196.07:34:39.55#ibcon#wrote, iclass 14, count 0 2006.196.07:34:39.55#ibcon#about to read 3, iclass 14, count 0 2006.196.07:34:39.59#ibcon#read 3, iclass 14, count 0 2006.196.07:34:39.59#ibcon#about to read 4, iclass 14, count 0 2006.196.07:34:39.59#ibcon#read 4, iclass 14, count 0 2006.196.07:34:39.59#ibcon#about to read 5, iclass 14, count 0 2006.196.07:34:39.59#ibcon#read 5, iclass 14, count 0 2006.196.07:34:39.59#ibcon#about to read 6, iclass 14, count 0 2006.196.07:34:39.59#ibcon#read 6, iclass 14, count 0 2006.196.07:34:39.59#ibcon#end of sib2, iclass 14, count 0 2006.196.07:34:39.59#ibcon#*after write, iclass 14, count 0 2006.196.07:34:39.59#ibcon#*before return 0, iclass 14, count 0 2006.196.07:34:39.59#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.196.07:34:39.59#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.196.07:34:39.59#ibcon#about to clear, iclass 14 cls_cnt 0 2006.196.07:34:39.59#ibcon#cleared, iclass 14 cls_cnt 0 2006.196.07:34:39.59$vc4f8/va=6,6 2006.196.07:34:39.59#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.196.07:34:39.59#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.196.07:34:39.59#ibcon#ireg 11 cls_cnt 2 2006.196.07:34:39.59#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.196.07:34:39.65#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.196.07:34:39.65#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.196.07:34:39.65#ibcon#enter wrdev, iclass 16, count 2 2006.196.07:34:39.65#ibcon#first serial, iclass 16, count 2 2006.196.07:34:39.65#ibcon#enter sib2, iclass 16, count 2 2006.196.07:34:39.65#ibcon#flushed, iclass 16, count 2 2006.196.07:34:39.65#ibcon#about to write, iclass 16, count 2 2006.196.07:34:39.65#ibcon#wrote, iclass 16, count 2 2006.196.07:34:39.65#ibcon#about to read 3, iclass 16, count 2 2006.196.07:34:39.67#ibcon#read 3, iclass 16, count 2 2006.196.07:34:39.67#ibcon#about to read 4, iclass 16, count 2 2006.196.07:34:39.67#ibcon#read 4, iclass 16, count 2 2006.196.07:34:39.67#ibcon#about to read 5, iclass 16, count 2 2006.196.07:34:39.67#ibcon#read 5, iclass 16, count 2 2006.196.07:34:39.67#ibcon#about to read 6, iclass 16, count 2 2006.196.07:34:39.67#ibcon#read 6, iclass 16, count 2 2006.196.07:34:39.67#ibcon#end of sib2, iclass 16, count 2 2006.196.07:34:39.67#ibcon#*mode == 0, iclass 16, count 2 2006.196.07:34:39.67#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.196.07:34:39.67#ibcon#[25=AT06-06\r\n] 2006.196.07:34:39.67#ibcon#*before write, iclass 16, count 2 2006.196.07:34:39.67#ibcon#enter sib2, iclass 16, count 2 2006.196.07:34:39.67#ibcon#flushed, iclass 16, count 2 2006.196.07:34:39.67#ibcon#about to write, iclass 16, count 2 2006.196.07:34:39.67#ibcon#wrote, iclass 16, count 2 2006.196.07:34:39.67#ibcon#about to read 3, iclass 16, count 2 2006.196.07:34:39.70#ibcon#read 3, iclass 16, count 2 2006.196.07:34:39.70#ibcon#about to read 4, iclass 16, count 2 2006.196.07:34:39.70#ibcon#read 4, iclass 16, count 2 2006.196.07:34:39.70#ibcon#about to read 5, iclass 16, count 2 2006.196.07:34:39.70#ibcon#read 5, iclass 16, count 2 2006.196.07:34:39.70#ibcon#about to read 6, iclass 16, count 2 2006.196.07:34:39.70#ibcon#read 6, iclass 16, count 2 2006.196.07:34:39.70#ibcon#end of sib2, iclass 16, count 2 2006.196.07:34:39.70#ibcon#*after write, iclass 16, count 2 2006.196.07:34:39.70#ibcon#*before return 0, iclass 16, count 2 2006.196.07:34:39.70#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.196.07:34:39.70#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.196.07:34:39.70#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.196.07:34:39.70#ibcon#ireg 7 cls_cnt 0 2006.196.07:34:39.70#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.196.07:34:39.82#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.196.07:34:39.82#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.196.07:34:39.82#ibcon#enter wrdev, iclass 16, count 0 2006.196.07:34:39.82#ibcon#first serial, iclass 16, count 0 2006.196.07:34:39.82#ibcon#enter sib2, iclass 16, count 0 2006.196.07:34:39.82#ibcon#flushed, iclass 16, count 0 2006.196.07:34:39.82#ibcon#about to write, iclass 16, count 0 2006.196.07:34:39.82#ibcon#wrote, iclass 16, count 0 2006.196.07:34:39.82#ibcon#about to read 3, iclass 16, count 0 2006.196.07:34:39.84#ibcon#read 3, iclass 16, count 0 2006.196.07:34:39.84#ibcon#about to read 4, iclass 16, count 0 2006.196.07:34:39.84#ibcon#read 4, iclass 16, count 0 2006.196.07:34:39.84#ibcon#about to read 5, iclass 16, count 0 2006.196.07:34:39.84#ibcon#read 5, iclass 16, count 0 2006.196.07:34:39.84#ibcon#about to read 6, iclass 16, count 0 2006.196.07:34:39.84#ibcon#read 6, iclass 16, count 0 2006.196.07:34:39.84#ibcon#end of sib2, iclass 16, count 0 2006.196.07:34:39.84#ibcon#*mode == 0, iclass 16, count 0 2006.196.07:34:39.84#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.196.07:34:39.84#ibcon#[25=USB\r\n] 2006.196.07:34:39.84#ibcon#*before write, iclass 16, count 0 2006.196.07:34:39.84#ibcon#enter sib2, iclass 16, count 0 2006.196.07:34:39.84#ibcon#flushed, iclass 16, count 0 2006.196.07:34:39.84#ibcon#about to write, iclass 16, count 0 2006.196.07:34:39.84#ibcon#wrote, iclass 16, count 0 2006.196.07:34:39.84#ibcon#about to read 3, iclass 16, count 0 2006.196.07:34:39.87#ibcon#read 3, iclass 16, count 0 2006.196.07:34:39.87#ibcon#about to read 4, iclass 16, count 0 2006.196.07:34:39.87#ibcon#read 4, iclass 16, count 0 2006.196.07:34:39.87#ibcon#about to read 5, iclass 16, count 0 2006.196.07:34:39.87#ibcon#read 5, iclass 16, count 0 2006.196.07:34:39.87#ibcon#about to read 6, iclass 16, count 0 2006.196.07:34:39.87#ibcon#read 6, iclass 16, count 0 2006.196.07:34:39.87#ibcon#end of sib2, iclass 16, count 0 2006.196.07:34:39.87#ibcon#*after write, iclass 16, count 0 2006.196.07:34:39.87#ibcon#*before return 0, iclass 16, count 0 2006.196.07:34:39.87#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.196.07:34:39.87#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.196.07:34:39.87#ibcon#about to clear, iclass 16 cls_cnt 0 2006.196.07:34:39.87#ibcon#cleared, iclass 16 cls_cnt 0 2006.196.07:34:39.87$vc4f8/valo=7,832.99 2006.196.07:34:39.87#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.196.07:34:39.87#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.196.07:34:39.87#ibcon#ireg 17 cls_cnt 0 2006.196.07:34:39.87#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.196.07:34:39.87#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.196.07:34:39.87#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.196.07:34:39.87#ibcon#enter wrdev, iclass 18, count 0 2006.196.07:34:39.87#ibcon#first serial, iclass 18, count 0 2006.196.07:34:39.87#ibcon#enter sib2, iclass 18, count 0 2006.196.07:34:39.87#ibcon#flushed, iclass 18, count 0 2006.196.07:34:39.87#ibcon#about to write, iclass 18, count 0 2006.196.07:34:39.87#ibcon#wrote, iclass 18, count 0 2006.196.07:34:39.87#ibcon#about to read 3, iclass 18, count 0 2006.196.07:34:39.89#ibcon#read 3, iclass 18, count 0 2006.196.07:34:39.89#ibcon#about to read 4, iclass 18, count 0 2006.196.07:34:39.89#ibcon#read 4, iclass 18, count 0 2006.196.07:34:39.89#ibcon#about to read 5, iclass 18, count 0 2006.196.07:34:39.89#ibcon#read 5, iclass 18, count 0 2006.196.07:34:39.89#ibcon#about to read 6, iclass 18, count 0 2006.196.07:34:39.89#ibcon#read 6, iclass 18, count 0 2006.196.07:34:39.89#ibcon#end of sib2, iclass 18, count 0 2006.196.07:34:39.89#ibcon#*mode == 0, iclass 18, count 0 2006.196.07:34:39.89#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.196.07:34:39.89#ibcon#[26=FRQ=07,832.99\r\n] 2006.196.07:34:39.89#ibcon#*before write, iclass 18, count 0 2006.196.07:34:39.89#ibcon#enter sib2, iclass 18, count 0 2006.196.07:34:39.89#ibcon#flushed, iclass 18, count 0 2006.196.07:34:39.89#ibcon#about to write, iclass 18, count 0 2006.196.07:34:39.89#ibcon#wrote, iclass 18, count 0 2006.196.07:34:39.89#ibcon#about to read 3, iclass 18, count 0 2006.196.07:34:39.93#ibcon#read 3, iclass 18, count 0 2006.196.07:34:39.93#ibcon#about to read 4, iclass 18, count 0 2006.196.07:34:39.93#ibcon#read 4, iclass 18, count 0 2006.196.07:34:39.93#ibcon#about to read 5, iclass 18, count 0 2006.196.07:34:39.93#ibcon#read 5, iclass 18, count 0 2006.196.07:34:39.93#ibcon#about to read 6, iclass 18, count 0 2006.196.07:34:39.93#ibcon#read 6, iclass 18, count 0 2006.196.07:34:39.93#ibcon#end of sib2, iclass 18, count 0 2006.196.07:34:39.93#ibcon#*after write, iclass 18, count 0 2006.196.07:34:39.93#ibcon#*before return 0, iclass 18, count 0 2006.196.07:34:39.93#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.196.07:34:39.93#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.196.07:34:39.93#ibcon#about to clear, iclass 18 cls_cnt 0 2006.196.07:34:39.93#ibcon#cleared, iclass 18 cls_cnt 0 2006.196.07:34:39.93$vc4f8/va=7,6 2006.196.07:34:39.93#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.196.07:34:39.93#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.196.07:34:39.93#ibcon#ireg 11 cls_cnt 2 2006.196.07:34:39.93#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.196.07:34:39.99#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.196.07:34:39.99#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.196.07:34:39.99#ibcon#enter wrdev, iclass 20, count 2 2006.196.07:34:39.99#ibcon#first serial, iclass 20, count 2 2006.196.07:34:39.99#ibcon#enter sib2, iclass 20, count 2 2006.196.07:34:39.99#ibcon#flushed, iclass 20, count 2 2006.196.07:34:39.99#ibcon#about to write, iclass 20, count 2 2006.196.07:34:39.99#ibcon#wrote, iclass 20, count 2 2006.196.07:34:39.99#ibcon#about to read 3, iclass 20, count 2 2006.196.07:34:40.01#ibcon#read 3, iclass 20, count 2 2006.196.07:34:40.01#ibcon#about to read 4, iclass 20, count 2 2006.196.07:34:40.01#ibcon#read 4, iclass 20, count 2 2006.196.07:34:40.01#ibcon#about to read 5, iclass 20, count 2 2006.196.07:34:40.01#ibcon#read 5, iclass 20, count 2 2006.196.07:34:40.01#ibcon#about to read 6, iclass 20, count 2 2006.196.07:34:40.01#ibcon#read 6, iclass 20, count 2 2006.196.07:34:40.01#ibcon#end of sib2, iclass 20, count 2 2006.196.07:34:40.01#ibcon#*mode == 0, iclass 20, count 2 2006.196.07:34:40.01#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.196.07:34:40.01#ibcon#[25=AT07-06\r\n] 2006.196.07:34:40.01#ibcon#*before write, iclass 20, count 2 2006.196.07:34:40.01#ibcon#enter sib2, iclass 20, count 2 2006.196.07:34:40.01#ibcon#flushed, iclass 20, count 2 2006.196.07:34:40.01#ibcon#about to write, iclass 20, count 2 2006.196.07:34:40.01#ibcon#wrote, iclass 20, count 2 2006.196.07:34:40.01#ibcon#about to read 3, iclass 20, count 2 2006.196.07:34:40.04#ibcon#read 3, iclass 20, count 2 2006.196.07:34:40.04#ibcon#about to read 4, iclass 20, count 2 2006.196.07:34:40.04#ibcon#read 4, iclass 20, count 2 2006.196.07:34:40.04#ibcon#about to read 5, iclass 20, count 2 2006.196.07:34:40.04#ibcon#read 5, iclass 20, count 2 2006.196.07:34:40.04#ibcon#about to read 6, iclass 20, count 2 2006.196.07:34:40.04#ibcon#read 6, iclass 20, count 2 2006.196.07:34:40.04#ibcon#end of sib2, iclass 20, count 2 2006.196.07:34:40.04#ibcon#*after write, iclass 20, count 2 2006.196.07:34:40.04#ibcon#*before return 0, iclass 20, count 2 2006.196.07:34:40.04#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.196.07:34:40.04#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.196.07:34:40.04#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.196.07:34:40.04#ibcon#ireg 7 cls_cnt 0 2006.196.07:34:40.04#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.196.07:34:40.16#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.196.07:34:40.16#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.196.07:34:40.16#ibcon#enter wrdev, iclass 20, count 0 2006.196.07:34:40.16#ibcon#first serial, iclass 20, count 0 2006.196.07:34:40.16#ibcon#enter sib2, iclass 20, count 0 2006.196.07:34:40.16#ibcon#flushed, iclass 20, count 0 2006.196.07:34:40.16#ibcon#about to write, iclass 20, count 0 2006.196.07:34:40.16#ibcon#wrote, iclass 20, count 0 2006.196.07:34:40.16#ibcon#about to read 3, iclass 20, count 0 2006.196.07:34:40.18#ibcon#read 3, iclass 20, count 0 2006.196.07:34:40.18#ibcon#about to read 4, iclass 20, count 0 2006.196.07:34:40.18#ibcon#read 4, iclass 20, count 0 2006.196.07:34:40.18#ibcon#about to read 5, iclass 20, count 0 2006.196.07:34:40.18#ibcon#read 5, iclass 20, count 0 2006.196.07:34:40.18#ibcon#about to read 6, iclass 20, count 0 2006.196.07:34:40.18#ibcon#read 6, iclass 20, count 0 2006.196.07:34:40.18#ibcon#end of sib2, iclass 20, count 0 2006.196.07:34:40.18#ibcon#*mode == 0, iclass 20, count 0 2006.196.07:34:40.18#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.196.07:34:40.18#ibcon#[25=USB\r\n] 2006.196.07:34:40.18#ibcon#*before write, iclass 20, count 0 2006.196.07:34:40.18#ibcon#enter sib2, iclass 20, count 0 2006.196.07:34:40.18#ibcon#flushed, iclass 20, count 0 2006.196.07:34:40.18#ibcon#about to write, iclass 20, count 0 2006.196.07:34:40.18#ibcon#wrote, iclass 20, count 0 2006.196.07:34:40.18#ibcon#about to read 3, iclass 20, count 0 2006.196.07:34:40.21#ibcon#read 3, iclass 20, count 0 2006.196.07:34:40.21#ibcon#about to read 4, iclass 20, count 0 2006.196.07:34:40.21#ibcon#read 4, iclass 20, count 0 2006.196.07:34:40.21#ibcon#about to read 5, iclass 20, count 0 2006.196.07:34:40.21#ibcon#read 5, iclass 20, count 0 2006.196.07:34:40.21#ibcon#about to read 6, iclass 20, count 0 2006.196.07:34:40.21#ibcon#read 6, iclass 20, count 0 2006.196.07:34:40.21#ibcon#end of sib2, iclass 20, count 0 2006.196.07:34:40.21#ibcon#*after write, iclass 20, count 0 2006.196.07:34:40.21#ibcon#*before return 0, iclass 20, count 0 2006.196.07:34:40.21#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.196.07:34:40.21#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.196.07:34:40.21#ibcon#about to clear, iclass 20 cls_cnt 0 2006.196.07:34:40.21#ibcon#cleared, iclass 20 cls_cnt 0 2006.196.07:34:40.21$vc4f8/valo=8,852.99 2006.196.07:34:40.21#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.196.07:34:40.21#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.196.07:34:40.21#ibcon#ireg 17 cls_cnt 0 2006.196.07:34:40.21#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.196.07:34:40.21#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.196.07:34:40.21#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.196.07:34:40.21#ibcon#enter wrdev, iclass 22, count 0 2006.196.07:34:40.21#ibcon#first serial, iclass 22, count 0 2006.196.07:34:40.21#ibcon#enter sib2, iclass 22, count 0 2006.196.07:34:40.21#ibcon#flushed, iclass 22, count 0 2006.196.07:34:40.21#ibcon#about to write, iclass 22, count 0 2006.196.07:34:40.21#ibcon#wrote, iclass 22, count 0 2006.196.07:34:40.21#ibcon#about to read 3, iclass 22, count 0 2006.196.07:34:40.23#ibcon#read 3, iclass 22, count 0 2006.196.07:34:40.23#ibcon#about to read 4, iclass 22, count 0 2006.196.07:34:40.23#ibcon#read 4, iclass 22, count 0 2006.196.07:34:40.23#ibcon#about to read 5, iclass 22, count 0 2006.196.07:34:40.23#ibcon#read 5, iclass 22, count 0 2006.196.07:34:40.23#ibcon#about to read 6, iclass 22, count 0 2006.196.07:34:40.23#ibcon#read 6, iclass 22, count 0 2006.196.07:34:40.23#ibcon#end of sib2, iclass 22, count 0 2006.196.07:34:40.23#ibcon#*mode == 0, iclass 22, count 0 2006.196.07:34:40.23#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.196.07:34:40.23#ibcon#[26=FRQ=08,852.99\r\n] 2006.196.07:34:40.23#ibcon#*before write, iclass 22, count 0 2006.196.07:34:40.23#ibcon#enter sib2, iclass 22, count 0 2006.196.07:34:40.23#ibcon#flushed, iclass 22, count 0 2006.196.07:34:40.23#ibcon#about to write, iclass 22, count 0 2006.196.07:34:40.23#ibcon#wrote, iclass 22, count 0 2006.196.07:34:40.23#ibcon#about to read 3, iclass 22, count 0 2006.196.07:34:40.27#ibcon#read 3, iclass 22, count 0 2006.196.07:34:40.27#ibcon#about to read 4, iclass 22, count 0 2006.196.07:34:40.27#ibcon#read 4, iclass 22, count 0 2006.196.07:34:40.27#ibcon#about to read 5, iclass 22, count 0 2006.196.07:34:40.27#ibcon#read 5, iclass 22, count 0 2006.196.07:34:40.27#ibcon#about to read 6, iclass 22, count 0 2006.196.07:34:40.27#ibcon#read 6, iclass 22, count 0 2006.196.07:34:40.27#ibcon#end of sib2, iclass 22, count 0 2006.196.07:34:40.27#ibcon#*after write, iclass 22, count 0 2006.196.07:34:40.27#ibcon#*before return 0, iclass 22, count 0 2006.196.07:34:40.27#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.196.07:34:40.27#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.196.07:34:40.27#ibcon#about to clear, iclass 22 cls_cnt 0 2006.196.07:34:40.27#ibcon#cleared, iclass 22 cls_cnt 0 2006.196.07:34:40.27$vc4f8/va=8,7 2006.196.07:34:40.27#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.196.07:34:40.27#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.196.07:34:40.27#ibcon#ireg 11 cls_cnt 2 2006.196.07:34:40.27#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.196.07:34:40.33#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.196.07:34:40.33#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.196.07:34:40.33#ibcon#enter wrdev, iclass 24, count 2 2006.196.07:34:40.33#ibcon#first serial, iclass 24, count 2 2006.196.07:34:40.33#ibcon#enter sib2, iclass 24, count 2 2006.196.07:34:40.33#ibcon#flushed, iclass 24, count 2 2006.196.07:34:40.33#ibcon#about to write, iclass 24, count 2 2006.196.07:34:40.33#ibcon#wrote, iclass 24, count 2 2006.196.07:34:40.33#ibcon#about to read 3, iclass 24, count 2 2006.196.07:34:40.35#ibcon#read 3, iclass 24, count 2 2006.196.07:34:40.35#ibcon#about to read 4, iclass 24, count 2 2006.196.07:34:40.35#ibcon#read 4, iclass 24, count 2 2006.196.07:34:40.35#ibcon#about to read 5, iclass 24, count 2 2006.196.07:34:40.35#ibcon#read 5, iclass 24, count 2 2006.196.07:34:40.35#ibcon#about to read 6, iclass 24, count 2 2006.196.07:34:40.35#ibcon#read 6, iclass 24, count 2 2006.196.07:34:40.35#ibcon#end of sib2, iclass 24, count 2 2006.196.07:34:40.35#ibcon#*mode == 0, iclass 24, count 2 2006.196.07:34:40.35#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.196.07:34:40.35#ibcon#[25=AT08-07\r\n] 2006.196.07:34:40.35#ibcon#*before write, iclass 24, count 2 2006.196.07:34:40.35#ibcon#enter sib2, iclass 24, count 2 2006.196.07:34:40.35#ibcon#flushed, iclass 24, count 2 2006.196.07:34:40.35#ibcon#about to write, iclass 24, count 2 2006.196.07:34:40.35#ibcon#wrote, iclass 24, count 2 2006.196.07:34:40.35#ibcon#about to read 3, iclass 24, count 2 2006.196.07:34:40.38#ibcon#read 3, iclass 24, count 2 2006.196.07:34:40.38#ibcon#about to read 4, iclass 24, count 2 2006.196.07:34:40.38#ibcon#read 4, iclass 24, count 2 2006.196.07:34:40.38#ibcon#about to read 5, iclass 24, count 2 2006.196.07:34:40.38#ibcon#read 5, iclass 24, count 2 2006.196.07:34:40.38#ibcon#about to read 6, iclass 24, count 2 2006.196.07:34:40.38#ibcon#read 6, iclass 24, count 2 2006.196.07:34:40.38#ibcon#end of sib2, iclass 24, count 2 2006.196.07:34:40.38#ibcon#*after write, iclass 24, count 2 2006.196.07:34:40.38#ibcon#*before return 0, iclass 24, count 2 2006.196.07:34:40.38#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.196.07:34:40.38#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.196.07:34:40.38#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.196.07:34:40.38#ibcon#ireg 7 cls_cnt 0 2006.196.07:34:40.38#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.196.07:34:40.50#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.196.07:34:40.50#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.196.07:34:40.50#ibcon#enter wrdev, iclass 24, count 0 2006.196.07:34:40.50#ibcon#first serial, iclass 24, count 0 2006.196.07:34:40.50#ibcon#enter sib2, iclass 24, count 0 2006.196.07:34:40.50#ibcon#flushed, iclass 24, count 0 2006.196.07:34:40.50#ibcon#about to write, iclass 24, count 0 2006.196.07:34:40.50#ibcon#wrote, iclass 24, count 0 2006.196.07:34:40.50#ibcon#about to read 3, iclass 24, count 0 2006.196.07:34:40.52#ibcon#read 3, iclass 24, count 0 2006.196.07:34:40.52#ibcon#about to read 4, iclass 24, count 0 2006.196.07:34:40.52#ibcon#read 4, iclass 24, count 0 2006.196.07:34:40.52#ibcon#about to read 5, iclass 24, count 0 2006.196.07:34:40.52#ibcon#read 5, iclass 24, count 0 2006.196.07:34:40.52#ibcon#about to read 6, iclass 24, count 0 2006.196.07:34:40.52#ibcon#read 6, iclass 24, count 0 2006.196.07:34:40.52#ibcon#end of sib2, iclass 24, count 0 2006.196.07:34:40.52#ibcon#*mode == 0, iclass 24, count 0 2006.196.07:34:40.52#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.196.07:34:40.52#ibcon#[25=USB\r\n] 2006.196.07:34:40.52#ibcon#*before write, iclass 24, count 0 2006.196.07:34:40.52#ibcon#enter sib2, iclass 24, count 0 2006.196.07:34:40.52#ibcon#flushed, iclass 24, count 0 2006.196.07:34:40.52#ibcon#about to write, iclass 24, count 0 2006.196.07:34:40.52#ibcon#wrote, iclass 24, count 0 2006.196.07:34:40.52#ibcon#about to read 3, iclass 24, count 0 2006.196.07:34:40.55#ibcon#read 3, iclass 24, count 0 2006.196.07:34:40.55#ibcon#about to read 4, iclass 24, count 0 2006.196.07:34:40.55#ibcon#read 4, iclass 24, count 0 2006.196.07:34:40.55#ibcon#about to read 5, iclass 24, count 0 2006.196.07:34:40.55#ibcon#read 5, iclass 24, count 0 2006.196.07:34:40.55#ibcon#about to read 6, iclass 24, count 0 2006.196.07:34:40.55#ibcon#read 6, iclass 24, count 0 2006.196.07:34:40.55#ibcon#end of sib2, iclass 24, count 0 2006.196.07:34:40.55#ibcon#*after write, iclass 24, count 0 2006.196.07:34:40.55#ibcon#*before return 0, iclass 24, count 0 2006.196.07:34:40.55#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.196.07:34:40.55#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.196.07:34:40.55#ibcon#about to clear, iclass 24 cls_cnt 0 2006.196.07:34:40.55#ibcon#cleared, iclass 24 cls_cnt 0 2006.196.07:34:40.55$vc4f8/vblo=1,632.99 2006.196.07:34:40.55#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.196.07:34:40.55#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.196.07:34:40.55#ibcon#ireg 17 cls_cnt 0 2006.196.07:34:40.55#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.196.07:34:40.55#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.196.07:34:40.55#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.196.07:34:40.55#ibcon#enter wrdev, iclass 26, count 0 2006.196.07:34:40.55#ibcon#first serial, iclass 26, count 0 2006.196.07:34:40.55#ibcon#enter sib2, iclass 26, count 0 2006.196.07:34:40.55#ibcon#flushed, iclass 26, count 0 2006.196.07:34:40.55#ibcon#about to write, iclass 26, count 0 2006.196.07:34:40.55#ibcon#wrote, iclass 26, count 0 2006.196.07:34:40.55#ibcon#about to read 3, iclass 26, count 0 2006.196.07:34:40.57#ibcon#read 3, iclass 26, count 0 2006.196.07:34:40.57#ibcon#about to read 4, iclass 26, count 0 2006.196.07:34:40.57#ibcon#read 4, iclass 26, count 0 2006.196.07:34:40.57#ibcon#about to read 5, iclass 26, count 0 2006.196.07:34:40.57#ibcon#read 5, iclass 26, count 0 2006.196.07:34:40.57#ibcon#about to read 6, iclass 26, count 0 2006.196.07:34:40.57#ibcon#read 6, iclass 26, count 0 2006.196.07:34:40.57#ibcon#end of sib2, iclass 26, count 0 2006.196.07:34:40.57#ibcon#*mode == 0, iclass 26, count 0 2006.196.07:34:40.57#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.196.07:34:40.57#ibcon#[28=FRQ=01,632.99\r\n] 2006.196.07:34:40.57#ibcon#*before write, iclass 26, count 0 2006.196.07:34:40.57#ibcon#enter sib2, iclass 26, count 0 2006.196.07:34:40.57#ibcon#flushed, iclass 26, count 0 2006.196.07:34:40.57#ibcon#about to write, iclass 26, count 0 2006.196.07:34:40.57#ibcon#wrote, iclass 26, count 0 2006.196.07:34:40.57#ibcon#about to read 3, iclass 26, count 0 2006.196.07:34:40.62#ibcon#read 3, iclass 26, count 0 2006.196.07:34:40.62#ibcon#about to read 4, iclass 26, count 0 2006.196.07:34:40.62#ibcon#read 4, iclass 26, count 0 2006.196.07:34:40.62#ibcon#about to read 5, iclass 26, count 0 2006.196.07:34:40.62#ibcon#read 5, iclass 26, count 0 2006.196.07:34:40.62#ibcon#about to read 6, iclass 26, count 0 2006.196.07:34:40.62#ibcon#read 6, iclass 26, count 0 2006.196.07:34:40.62#ibcon#end of sib2, iclass 26, count 0 2006.196.07:34:40.62#ibcon#*after write, iclass 26, count 0 2006.196.07:34:40.62#ibcon#*before return 0, iclass 26, count 0 2006.196.07:34:40.62#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.196.07:34:40.62#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.196.07:34:40.62#ibcon#about to clear, iclass 26 cls_cnt 0 2006.196.07:34:40.62#ibcon#cleared, iclass 26 cls_cnt 0 2006.196.07:34:40.62$vc4f8/vb=1,4 2006.196.07:34:40.62#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.196.07:34:40.62#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.196.07:34:40.62#ibcon#ireg 11 cls_cnt 2 2006.196.07:34:40.62#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.196.07:34:40.62#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.196.07:34:40.62#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.196.07:34:40.62#ibcon#enter wrdev, iclass 28, count 2 2006.196.07:34:40.62#ibcon#first serial, iclass 28, count 2 2006.196.07:34:40.62#ibcon#enter sib2, iclass 28, count 2 2006.196.07:34:40.62#ibcon#flushed, iclass 28, count 2 2006.196.07:34:40.62#ibcon#about to write, iclass 28, count 2 2006.196.07:34:40.62#ibcon#wrote, iclass 28, count 2 2006.196.07:34:40.62#ibcon#about to read 3, iclass 28, count 2 2006.196.07:34:40.64#ibcon#read 3, iclass 28, count 2 2006.196.07:34:40.64#ibcon#about to read 4, iclass 28, count 2 2006.196.07:34:40.64#ibcon#read 4, iclass 28, count 2 2006.196.07:34:40.64#ibcon#about to read 5, iclass 28, count 2 2006.196.07:34:40.64#ibcon#read 5, iclass 28, count 2 2006.196.07:34:40.64#ibcon#about to read 6, iclass 28, count 2 2006.196.07:34:40.64#ibcon#read 6, iclass 28, count 2 2006.196.07:34:40.64#ibcon#end of sib2, iclass 28, count 2 2006.196.07:34:40.64#ibcon#*mode == 0, iclass 28, count 2 2006.196.07:34:40.64#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.196.07:34:40.64#ibcon#[27=AT01-04\r\n] 2006.196.07:34:40.64#ibcon#*before write, iclass 28, count 2 2006.196.07:34:40.64#ibcon#enter sib2, iclass 28, count 2 2006.196.07:34:40.64#ibcon#flushed, iclass 28, count 2 2006.196.07:34:40.64#ibcon#about to write, iclass 28, count 2 2006.196.07:34:40.64#ibcon#wrote, iclass 28, count 2 2006.196.07:34:40.64#ibcon#about to read 3, iclass 28, count 2 2006.196.07:34:40.67#ibcon#read 3, iclass 28, count 2 2006.196.07:34:40.67#ibcon#about to read 4, iclass 28, count 2 2006.196.07:34:40.67#ibcon#read 4, iclass 28, count 2 2006.196.07:34:40.67#ibcon#about to read 5, iclass 28, count 2 2006.196.07:34:40.67#ibcon#read 5, iclass 28, count 2 2006.196.07:34:40.67#ibcon#about to read 6, iclass 28, count 2 2006.196.07:34:40.67#ibcon#read 6, iclass 28, count 2 2006.196.07:34:40.67#ibcon#end of sib2, iclass 28, count 2 2006.196.07:34:40.67#ibcon#*after write, iclass 28, count 2 2006.196.07:34:40.67#ibcon#*before return 0, iclass 28, count 2 2006.196.07:34:40.67#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.196.07:34:40.67#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.196.07:34:40.67#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.196.07:34:40.67#ibcon#ireg 7 cls_cnt 0 2006.196.07:34:40.67#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.196.07:34:40.79#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.196.07:34:40.79#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.196.07:34:40.79#ibcon#enter wrdev, iclass 28, count 0 2006.196.07:34:40.79#ibcon#first serial, iclass 28, count 0 2006.196.07:34:40.79#ibcon#enter sib2, iclass 28, count 0 2006.196.07:34:40.79#ibcon#flushed, iclass 28, count 0 2006.196.07:34:40.79#ibcon#about to write, iclass 28, count 0 2006.196.07:34:40.79#ibcon#wrote, iclass 28, count 0 2006.196.07:34:40.79#ibcon#about to read 3, iclass 28, count 0 2006.196.07:34:40.81#ibcon#read 3, iclass 28, count 0 2006.196.07:34:40.81#ibcon#about to read 4, iclass 28, count 0 2006.196.07:34:40.81#ibcon#read 4, iclass 28, count 0 2006.196.07:34:40.81#ibcon#about to read 5, iclass 28, count 0 2006.196.07:34:40.81#ibcon#read 5, iclass 28, count 0 2006.196.07:34:40.81#ibcon#about to read 6, iclass 28, count 0 2006.196.07:34:40.81#ibcon#read 6, iclass 28, count 0 2006.196.07:34:40.81#ibcon#end of sib2, iclass 28, count 0 2006.196.07:34:40.81#ibcon#*mode == 0, iclass 28, count 0 2006.196.07:34:40.81#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.196.07:34:40.81#ibcon#[27=USB\r\n] 2006.196.07:34:40.81#ibcon#*before write, iclass 28, count 0 2006.196.07:34:40.81#ibcon#enter sib2, iclass 28, count 0 2006.196.07:34:40.81#ibcon#flushed, iclass 28, count 0 2006.196.07:34:40.81#ibcon#about to write, iclass 28, count 0 2006.196.07:34:40.81#ibcon#wrote, iclass 28, count 0 2006.196.07:34:40.81#ibcon#about to read 3, iclass 28, count 0 2006.196.07:34:40.84#ibcon#read 3, iclass 28, count 0 2006.196.07:34:40.84#ibcon#about to read 4, iclass 28, count 0 2006.196.07:34:40.84#ibcon#read 4, iclass 28, count 0 2006.196.07:34:40.84#ibcon#about to read 5, iclass 28, count 0 2006.196.07:34:40.84#ibcon#read 5, iclass 28, count 0 2006.196.07:34:40.84#ibcon#about to read 6, iclass 28, count 0 2006.196.07:34:40.84#ibcon#read 6, iclass 28, count 0 2006.196.07:34:40.84#ibcon#end of sib2, iclass 28, count 0 2006.196.07:34:40.84#ibcon#*after write, iclass 28, count 0 2006.196.07:34:40.84#ibcon#*before return 0, iclass 28, count 0 2006.196.07:34:40.84#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.196.07:34:40.84#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.196.07:34:40.84#ibcon#about to clear, iclass 28 cls_cnt 0 2006.196.07:34:40.84#ibcon#cleared, iclass 28 cls_cnt 0 2006.196.07:34:40.84$vc4f8/vblo=2,640.99 2006.196.07:34:40.84#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.196.07:34:40.84#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.196.07:34:40.84#ibcon#ireg 17 cls_cnt 0 2006.196.07:34:40.84#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.196.07:34:40.84#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.196.07:34:40.84#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.196.07:34:40.84#ibcon#enter wrdev, iclass 30, count 0 2006.196.07:34:40.84#ibcon#first serial, iclass 30, count 0 2006.196.07:34:40.84#ibcon#enter sib2, iclass 30, count 0 2006.196.07:34:40.84#ibcon#flushed, iclass 30, count 0 2006.196.07:34:40.84#ibcon#about to write, iclass 30, count 0 2006.196.07:34:40.84#ibcon#wrote, iclass 30, count 0 2006.196.07:34:40.84#ibcon#about to read 3, iclass 30, count 0 2006.196.07:34:40.86#ibcon#read 3, iclass 30, count 0 2006.196.07:34:40.86#ibcon#about to read 4, iclass 30, count 0 2006.196.07:34:40.86#ibcon#read 4, iclass 30, count 0 2006.196.07:34:40.86#ibcon#about to read 5, iclass 30, count 0 2006.196.07:34:40.86#ibcon#read 5, iclass 30, count 0 2006.196.07:34:40.86#ibcon#about to read 6, iclass 30, count 0 2006.196.07:34:40.86#ibcon#read 6, iclass 30, count 0 2006.196.07:34:40.86#ibcon#end of sib2, iclass 30, count 0 2006.196.07:34:40.86#ibcon#*mode == 0, iclass 30, count 0 2006.196.07:34:40.86#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.196.07:34:40.86#ibcon#[28=FRQ=02,640.99\r\n] 2006.196.07:34:40.86#ibcon#*before write, iclass 30, count 0 2006.196.07:34:40.86#ibcon#enter sib2, iclass 30, count 0 2006.196.07:34:40.86#ibcon#flushed, iclass 30, count 0 2006.196.07:34:40.86#ibcon#about to write, iclass 30, count 0 2006.196.07:34:40.86#ibcon#wrote, iclass 30, count 0 2006.196.07:34:40.86#ibcon#about to read 3, iclass 30, count 0 2006.196.07:34:40.90#ibcon#read 3, iclass 30, count 0 2006.196.07:34:40.90#ibcon#about to read 4, iclass 30, count 0 2006.196.07:34:40.90#ibcon#read 4, iclass 30, count 0 2006.196.07:34:40.90#ibcon#about to read 5, iclass 30, count 0 2006.196.07:34:40.90#ibcon#read 5, iclass 30, count 0 2006.196.07:34:40.90#ibcon#about to read 6, iclass 30, count 0 2006.196.07:34:40.90#ibcon#read 6, iclass 30, count 0 2006.196.07:34:40.90#ibcon#end of sib2, iclass 30, count 0 2006.196.07:34:40.90#ibcon#*after write, iclass 30, count 0 2006.196.07:34:40.90#ibcon#*before return 0, iclass 30, count 0 2006.196.07:34:40.90#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.196.07:34:40.90#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.196.07:34:40.90#ibcon#about to clear, iclass 30 cls_cnt 0 2006.196.07:34:40.90#ibcon#cleared, iclass 30 cls_cnt 0 2006.196.07:34:40.90$vc4f8/vb=2,4 2006.196.07:34:40.90#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.196.07:34:40.90#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.196.07:34:40.90#ibcon#ireg 11 cls_cnt 2 2006.196.07:34:40.90#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.196.07:34:40.96#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.196.07:34:40.96#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.196.07:34:40.96#ibcon#enter wrdev, iclass 32, count 2 2006.196.07:34:40.96#ibcon#first serial, iclass 32, count 2 2006.196.07:34:40.96#ibcon#enter sib2, iclass 32, count 2 2006.196.07:34:40.96#ibcon#flushed, iclass 32, count 2 2006.196.07:34:40.96#ibcon#about to write, iclass 32, count 2 2006.196.07:34:40.96#ibcon#wrote, iclass 32, count 2 2006.196.07:34:40.96#ibcon#about to read 3, iclass 32, count 2 2006.196.07:34:40.98#ibcon#read 3, iclass 32, count 2 2006.196.07:34:40.98#ibcon#about to read 4, iclass 32, count 2 2006.196.07:34:40.98#ibcon#read 4, iclass 32, count 2 2006.196.07:34:40.98#ibcon#about to read 5, iclass 32, count 2 2006.196.07:34:40.98#ibcon#read 5, iclass 32, count 2 2006.196.07:34:40.98#ibcon#about to read 6, iclass 32, count 2 2006.196.07:34:40.98#ibcon#read 6, iclass 32, count 2 2006.196.07:34:40.98#ibcon#end of sib2, iclass 32, count 2 2006.196.07:34:40.98#ibcon#*mode == 0, iclass 32, count 2 2006.196.07:34:40.98#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.196.07:34:40.98#ibcon#[27=AT02-04\r\n] 2006.196.07:34:40.98#ibcon#*before write, iclass 32, count 2 2006.196.07:34:40.98#ibcon#enter sib2, iclass 32, count 2 2006.196.07:34:40.98#ibcon#flushed, iclass 32, count 2 2006.196.07:34:40.98#ibcon#about to write, iclass 32, count 2 2006.196.07:34:40.98#ibcon#wrote, iclass 32, count 2 2006.196.07:34:40.98#ibcon#about to read 3, iclass 32, count 2 2006.196.07:34:41.01#ibcon#read 3, iclass 32, count 2 2006.196.07:34:41.01#ibcon#about to read 4, iclass 32, count 2 2006.196.07:34:41.01#ibcon#read 4, iclass 32, count 2 2006.196.07:34:41.01#ibcon#about to read 5, iclass 32, count 2 2006.196.07:34:41.01#ibcon#read 5, iclass 32, count 2 2006.196.07:34:41.01#ibcon#about to read 6, iclass 32, count 2 2006.196.07:34:41.01#ibcon#read 6, iclass 32, count 2 2006.196.07:34:41.01#ibcon#end of sib2, iclass 32, count 2 2006.196.07:34:41.01#ibcon#*after write, iclass 32, count 2 2006.196.07:34:41.01#ibcon#*before return 0, iclass 32, count 2 2006.196.07:34:41.01#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.196.07:34:41.01#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.196.07:34:41.01#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.196.07:34:41.01#ibcon#ireg 7 cls_cnt 0 2006.196.07:34:41.01#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.196.07:34:41.13#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.196.07:34:41.13#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.196.07:34:41.13#ibcon#enter wrdev, iclass 32, count 0 2006.196.07:34:41.13#ibcon#first serial, iclass 32, count 0 2006.196.07:34:41.13#ibcon#enter sib2, iclass 32, count 0 2006.196.07:34:41.13#ibcon#flushed, iclass 32, count 0 2006.196.07:34:41.13#ibcon#about to write, iclass 32, count 0 2006.196.07:34:41.13#ibcon#wrote, iclass 32, count 0 2006.196.07:34:41.13#ibcon#about to read 3, iclass 32, count 0 2006.196.07:34:41.15#ibcon#read 3, iclass 32, count 0 2006.196.07:34:41.15#ibcon#about to read 4, iclass 32, count 0 2006.196.07:34:41.15#ibcon#read 4, iclass 32, count 0 2006.196.07:34:41.15#ibcon#about to read 5, iclass 32, count 0 2006.196.07:34:41.15#ibcon#read 5, iclass 32, count 0 2006.196.07:34:41.15#ibcon#about to read 6, iclass 32, count 0 2006.196.07:34:41.15#ibcon#read 6, iclass 32, count 0 2006.196.07:34:41.15#ibcon#end of sib2, iclass 32, count 0 2006.196.07:34:41.15#ibcon#*mode == 0, iclass 32, count 0 2006.196.07:34:41.15#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.196.07:34:41.15#ibcon#[27=USB\r\n] 2006.196.07:34:41.15#ibcon#*before write, iclass 32, count 0 2006.196.07:34:41.15#ibcon#enter sib2, iclass 32, count 0 2006.196.07:34:41.15#ibcon#flushed, iclass 32, count 0 2006.196.07:34:41.15#ibcon#about to write, iclass 32, count 0 2006.196.07:34:41.15#ibcon#wrote, iclass 32, count 0 2006.196.07:34:41.15#ibcon#about to read 3, iclass 32, count 0 2006.196.07:34:41.18#ibcon#read 3, iclass 32, count 0 2006.196.07:34:41.18#ibcon#about to read 4, iclass 32, count 0 2006.196.07:34:41.18#ibcon#read 4, iclass 32, count 0 2006.196.07:34:41.18#ibcon#about to read 5, iclass 32, count 0 2006.196.07:34:41.18#ibcon#read 5, iclass 32, count 0 2006.196.07:34:41.18#ibcon#about to read 6, iclass 32, count 0 2006.196.07:34:41.18#ibcon#read 6, iclass 32, count 0 2006.196.07:34:41.18#ibcon#end of sib2, iclass 32, count 0 2006.196.07:34:41.18#ibcon#*after write, iclass 32, count 0 2006.196.07:34:41.18#ibcon#*before return 0, iclass 32, count 0 2006.196.07:34:41.18#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.196.07:34:41.18#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.196.07:34:41.18#ibcon#about to clear, iclass 32 cls_cnt 0 2006.196.07:34:41.18#ibcon#cleared, iclass 32 cls_cnt 0 2006.196.07:34:41.18$vc4f8/vblo=3,656.99 2006.196.07:34:41.18#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.196.07:34:41.18#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.196.07:34:41.18#ibcon#ireg 17 cls_cnt 0 2006.196.07:34:41.18#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.196.07:34:41.18#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.196.07:34:41.18#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.196.07:34:41.18#ibcon#enter wrdev, iclass 34, count 0 2006.196.07:34:41.18#ibcon#first serial, iclass 34, count 0 2006.196.07:34:41.18#ibcon#enter sib2, iclass 34, count 0 2006.196.07:34:41.18#ibcon#flushed, iclass 34, count 0 2006.196.07:34:41.18#ibcon#about to write, iclass 34, count 0 2006.196.07:34:41.18#ibcon#wrote, iclass 34, count 0 2006.196.07:34:41.18#ibcon#about to read 3, iclass 34, count 0 2006.196.07:34:41.20#ibcon#read 3, iclass 34, count 0 2006.196.07:34:41.20#ibcon#about to read 4, iclass 34, count 0 2006.196.07:34:41.20#ibcon#read 4, iclass 34, count 0 2006.196.07:34:41.20#ibcon#about to read 5, iclass 34, count 0 2006.196.07:34:41.20#ibcon#read 5, iclass 34, count 0 2006.196.07:34:41.20#ibcon#about to read 6, iclass 34, count 0 2006.196.07:34:41.20#ibcon#read 6, iclass 34, count 0 2006.196.07:34:41.20#ibcon#end of sib2, iclass 34, count 0 2006.196.07:34:41.20#ibcon#*mode == 0, iclass 34, count 0 2006.196.07:34:41.20#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.196.07:34:41.20#ibcon#[28=FRQ=03,656.99\r\n] 2006.196.07:34:41.20#ibcon#*before write, iclass 34, count 0 2006.196.07:34:41.20#ibcon#enter sib2, iclass 34, count 0 2006.196.07:34:41.20#ibcon#flushed, iclass 34, count 0 2006.196.07:34:41.20#ibcon#about to write, iclass 34, count 0 2006.196.07:34:41.20#ibcon#wrote, iclass 34, count 0 2006.196.07:34:41.20#ibcon#about to read 3, iclass 34, count 0 2006.196.07:34:41.24#ibcon#read 3, iclass 34, count 0 2006.196.07:34:41.24#ibcon#about to read 4, iclass 34, count 0 2006.196.07:34:41.24#ibcon#read 4, iclass 34, count 0 2006.196.07:34:41.24#ibcon#about to read 5, iclass 34, count 0 2006.196.07:34:41.24#ibcon#read 5, iclass 34, count 0 2006.196.07:34:41.24#ibcon#about to read 6, iclass 34, count 0 2006.196.07:34:41.24#ibcon#read 6, iclass 34, count 0 2006.196.07:34:41.24#ibcon#end of sib2, iclass 34, count 0 2006.196.07:34:41.24#ibcon#*after write, iclass 34, count 0 2006.196.07:34:41.24#ibcon#*before return 0, iclass 34, count 0 2006.196.07:34:41.24#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.196.07:34:41.24#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.196.07:34:41.24#ibcon#about to clear, iclass 34 cls_cnt 0 2006.196.07:34:41.24#ibcon#cleared, iclass 34 cls_cnt 0 2006.196.07:34:41.24$vc4f8/vb=3,4 2006.196.07:34:41.24#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.196.07:34:41.24#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.196.07:34:41.24#ibcon#ireg 11 cls_cnt 2 2006.196.07:34:41.24#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.196.07:34:41.30#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.196.07:34:41.30#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.196.07:34:41.30#ibcon#enter wrdev, iclass 36, count 2 2006.196.07:34:41.30#ibcon#first serial, iclass 36, count 2 2006.196.07:34:41.30#ibcon#enter sib2, iclass 36, count 2 2006.196.07:34:41.30#ibcon#flushed, iclass 36, count 2 2006.196.07:34:41.30#ibcon#about to write, iclass 36, count 2 2006.196.07:34:41.30#ibcon#wrote, iclass 36, count 2 2006.196.07:34:41.30#ibcon#about to read 3, iclass 36, count 2 2006.196.07:34:41.32#ibcon#read 3, iclass 36, count 2 2006.196.07:34:41.32#ibcon#about to read 4, iclass 36, count 2 2006.196.07:34:41.32#ibcon#read 4, iclass 36, count 2 2006.196.07:34:41.32#ibcon#about to read 5, iclass 36, count 2 2006.196.07:34:41.32#ibcon#read 5, iclass 36, count 2 2006.196.07:34:41.32#ibcon#about to read 6, iclass 36, count 2 2006.196.07:34:41.32#ibcon#read 6, iclass 36, count 2 2006.196.07:34:41.32#ibcon#end of sib2, iclass 36, count 2 2006.196.07:34:41.32#ibcon#*mode == 0, iclass 36, count 2 2006.196.07:34:41.32#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.196.07:34:41.32#ibcon#[27=AT03-04\r\n] 2006.196.07:34:41.32#ibcon#*before write, iclass 36, count 2 2006.196.07:34:41.32#ibcon#enter sib2, iclass 36, count 2 2006.196.07:34:41.32#ibcon#flushed, iclass 36, count 2 2006.196.07:34:41.32#ibcon#about to write, iclass 36, count 2 2006.196.07:34:41.32#ibcon#wrote, iclass 36, count 2 2006.196.07:34:41.32#ibcon#about to read 3, iclass 36, count 2 2006.196.07:34:41.35#ibcon#read 3, iclass 36, count 2 2006.196.07:34:41.35#ibcon#about to read 4, iclass 36, count 2 2006.196.07:34:41.35#ibcon#read 4, iclass 36, count 2 2006.196.07:34:41.35#ibcon#about to read 5, iclass 36, count 2 2006.196.07:34:41.35#ibcon#read 5, iclass 36, count 2 2006.196.07:34:41.35#ibcon#about to read 6, iclass 36, count 2 2006.196.07:34:41.35#ibcon#read 6, iclass 36, count 2 2006.196.07:34:41.35#ibcon#end of sib2, iclass 36, count 2 2006.196.07:34:41.35#ibcon#*after write, iclass 36, count 2 2006.196.07:34:41.35#ibcon#*before return 0, iclass 36, count 2 2006.196.07:34:41.35#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.196.07:34:41.35#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.196.07:34:41.35#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.196.07:34:41.35#ibcon#ireg 7 cls_cnt 0 2006.196.07:34:41.35#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.196.07:34:41.47#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.196.07:34:41.47#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.196.07:34:41.47#ibcon#enter wrdev, iclass 36, count 0 2006.196.07:34:41.47#ibcon#first serial, iclass 36, count 0 2006.196.07:34:41.47#ibcon#enter sib2, iclass 36, count 0 2006.196.07:34:41.47#ibcon#flushed, iclass 36, count 0 2006.196.07:34:41.47#ibcon#about to write, iclass 36, count 0 2006.196.07:34:41.47#ibcon#wrote, iclass 36, count 0 2006.196.07:34:41.47#ibcon#about to read 3, iclass 36, count 0 2006.196.07:34:41.49#ibcon#read 3, iclass 36, count 0 2006.196.07:34:41.49#ibcon#about to read 4, iclass 36, count 0 2006.196.07:34:41.49#ibcon#read 4, iclass 36, count 0 2006.196.07:34:41.49#ibcon#about to read 5, iclass 36, count 0 2006.196.07:34:41.49#ibcon#read 5, iclass 36, count 0 2006.196.07:34:41.49#ibcon#about to read 6, iclass 36, count 0 2006.196.07:34:41.49#ibcon#read 6, iclass 36, count 0 2006.196.07:34:41.49#ibcon#end of sib2, iclass 36, count 0 2006.196.07:34:41.49#ibcon#*mode == 0, iclass 36, count 0 2006.196.07:34:41.49#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.196.07:34:41.49#ibcon#[27=USB\r\n] 2006.196.07:34:41.49#ibcon#*before write, iclass 36, count 0 2006.196.07:34:41.49#ibcon#enter sib2, iclass 36, count 0 2006.196.07:34:41.49#ibcon#flushed, iclass 36, count 0 2006.196.07:34:41.49#ibcon#about to write, iclass 36, count 0 2006.196.07:34:41.49#ibcon#wrote, iclass 36, count 0 2006.196.07:34:41.49#ibcon#about to read 3, iclass 36, count 0 2006.196.07:34:41.52#ibcon#read 3, iclass 36, count 0 2006.196.07:34:41.52#ibcon#about to read 4, iclass 36, count 0 2006.196.07:34:41.52#ibcon#read 4, iclass 36, count 0 2006.196.07:34:41.52#ibcon#about to read 5, iclass 36, count 0 2006.196.07:34:41.52#ibcon#read 5, iclass 36, count 0 2006.196.07:34:41.52#ibcon#about to read 6, iclass 36, count 0 2006.196.07:34:41.52#ibcon#read 6, iclass 36, count 0 2006.196.07:34:41.52#ibcon#end of sib2, iclass 36, count 0 2006.196.07:34:41.52#ibcon#*after write, iclass 36, count 0 2006.196.07:34:41.52#ibcon#*before return 0, iclass 36, count 0 2006.196.07:34:41.52#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.196.07:34:41.52#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.196.07:34:41.52#ibcon#about to clear, iclass 36 cls_cnt 0 2006.196.07:34:41.52#ibcon#cleared, iclass 36 cls_cnt 0 2006.196.07:34:41.52$vc4f8/vblo=4,712.99 2006.196.07:34:41.52#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.196.07:34:41.52#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.196.07:34:41.52#ibcon#ireg 17 cls_cnt 0 2006.196.07:34:41.52#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.196.07:34:41.52#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.196.07:34:41.52#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.196.07:34:41.52#ibcon#enter wrdev, iclass 38, count 0 2006.196.07:34:41.52#ibcon#first serial, iclass 38, count 0 2006.196.07:34:41.52#ibcon#enter sib2, iclass 38, count 0 2006.196.07:34:41.52#ibcon#flushed, iclass 38, count 0 2006.196.07:34:41.52#ibcon#about to write, iclass 38, count 0 2006.196.07:34:41.52#ibcon#wrote, iclass 38, count 0 2006.196.07:34:41.52#ibcon#about to read 3, iclass 38, count 0 2006.196.07:34:41.54#ibcon#read 3, iclass 38, count 0 2006.196.07:34:41.54#ibcon#about to read 4, iclass 38, count 0 2006.196.07:34:41.54#ibcon#read 4, iclass 38, count 0 2006.196.07:34:41.54#ibcon#about to read 5, iclass 38, count 0 2006.196.07:34:41.54#ibcon#read 5, iclass 38, count 0 2006.196.07:34:41.54#ibcon#about to read 6, iclass 38, count 0 2006.196.07:34:41.54#ibcon#read 6, iclass 38, count 0 2006.196.07:34:41.54#ibcon#end of sib2, iclass 38, count 0 2006.196.07:34:41.54#ibcon#*mode == 0, iclass 38, count 0 2006.196.07:34:41.54#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.196.07:34:41.54#ibcon#[28=FRQ=04,712.99\r\n] 2006.196.07:34:41.54#ibcon#*before write, iclass 38, count 0 2006.196.07:34:41.54#ibcon#enter sib2, iclass 38, count 0 2006.196.07:34:41.54#ibcon#flushed, iclass 38, count 0 2006.196.07:34:41.54#ibcon#about to write, iclass 38, count 0 2006.196.07:34:41.54#ibcon#wrote, iclass 38, count 0 2006.196.07:34:41.54#ibcon#about to read 3, iclass 38, count 0 2006.196.07:34:41.58#ibcon#read 3, iclass 38, count 0 2006.196.07:34:41.58#ibcon#about to read 4, iclass 38, count 0 2006.196.07:34:41.58#ibcon#read 4, iclass 38, count 0 2006.196.07:34:41.58#ibcon#about to read 5, iclass 38, count 0 2006.196.07:34:41.58#ibcon#read 5, iclass 38, count 0 2006.196.07:34:41.58#ibcon#about to read 6, iclass 38, count 0 2006.196.07:34:41.58#ibcon#read 6, iclass 38, count 0 2006.196.07:34:41.58#ibcon#end of sib2, iclass 38, count 0 2006.196.07:34:41.58#ibcon#*after write, iclass 38, count 0 2006.196.07:34:41.58#ibcon#*before return 0, iclass 38, count 0 2006.196.07:34:41.58#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.196.07:34:41.58#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.196.07:34:41.58#ibcon#about to clear, iclass 38 cls_cnt 0 2006.196.07:34:41.58#ibcon#cleared, iclass 38 cls_cnt 0 2006.196.07:34:41.58$vc4f8/vb=4,4 2006.196.07:34:41.58#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.196.07:34:41.58#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.196.07:34:41.58#ibcon#ireg 11 cls_cnt 2 2006.196.07:34:41.58#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.196.07:34:41.64#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.196.07:34:41.64#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.196.07:34:41.64#ibcon#enter wrdev, iclass 40, count 2 2006.196.07:34:41.64#ibcon#first serial, iclass 40, count 2 2006.196.07:34:41.64#ibcon#enter sib2, iclass 40, count 2 2006.196.07:34:41.64#ibcon#flushed, iclass 40, count 2 2006.196.07:34:41.64#ibcon#about to write, iclass 40, count 2 2006.196.07:34:41.64#ibcon#wrote, iclass 40, count 2 2006.196.07:34:41.64#ibcon#about to read 3, iclass 40, count 2 2006.196.07:34:41.66#ibcon#read 3, iclass 40, count 2 2006.196.07:34:41.66#ibcon#about to read 4, iclass 40, count 2 2006.196.07:34:41.66#ibcon#read 4, iclass 40, count 2 2006.196.07:34:41.66#ibcon#about to read 5, iclass 40, count 2 2006.196.07:34:41.66#ibcon#read 5, iclass 40, count 2 2006.196.07:34:41.66#ibcon#about to read 6, iclass 40, count 2 2006.196.07:34:41.66#ibcon#read 6, iclass 40, count 2 2006.196.07:34:41.66#ibcon#end of sib2, iclass 40, count 2 2006.196.07:34:41.66#ibcon#*mode == 0, iclass 40, count 2 2006.196.07:34:41.66#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.196.07:34:41.66#ibcon#[27=AT04-04\r\n] 2006.196.07:34:41.66#ibcon#*before write, iclass 40, count 2 2006.196.07:34:41.66#ibcon#enter sib2, iclass 40, count 2 2006.196.07:34:41.66#ibcon#flushed, iclass 40, count 2 2006.196.07:34:41.66#ibcon#about to write, iclass 40, count 2 2006.196.07:34:41.66#ibcon#wrote, iclass 40, count 2 2006.196.07:34:41.66#ibcon#about to read 3, iclass 40, count 2 2006.196.07:34:41.69#ibcon#read 3, iclass 40, count 2 2006.196.07:34:41.69#ibcon#about to read 4, iclass 40, count 2 2006.196.07:34:41.69#ibcon#read 4, iclass 40, count 2 2006.196.07:34:41.69#ibcon#about to read 5, iclass 40, count 2 2006.196.07:34:41.69#ibcon#read 5, iclass 40, count 2 2006.196.07:34:41.69#ibcon#about to read 6, iclass 40, count 2 2006.196.07:34:41.69#ibcon#read 6, iclass 40, count 2 2006.196.07:34:41.69#ibcon#end of sib2, iclass 40, count 2 2006.196.07:34:41.69#ibcon#*after write, iclass 40, count 2 2006.196.07:34:41.69#ibcon#*before return 0, iclass 40, count 2 2006.196.07:34:41.69#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.196.07:34:41.69#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.196.07:34:41.69#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.196.07:34:41.69#ibcon#ireg 7 cls_cnt 0 2006.196.07:34:41.69#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.196.07:34:41.81#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.196.07:34:41.81#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.196.07:34:41.81#ibcon#enter wrdev, iclass 40, count 0 2006.196.07:34:41.81#ibcon#first serial, iclass 40, count 0 2006.196.07:34:41.81#ibcon#enter sib2, iclass 40, count 0 2006.196.07:34:41.81#ibcon#flushed, iclass 40, count 0 2006.196.07:34:41.81#ibcon#about to write, iclass 40, count 0 2006.196.07:34:41.81#ibcon#wrote, iclass 40, count 0 2006.196.07:34:41.81#ibcon#about to read 3, iclass 40, count 0 2006.196.07:34:41.83#ibcon#read 3, iclass 40, count 0 2006.196.07:34:41.83#ibcon#about to read 4, iclass 40, count 0 2006.196.07:34:41.83#ibcon#read 4, iclass 40, count 0 2006.196.07:34:41.83#ibcon#about to read 5, iclass 40, count 0 2006.196.07:34:41.83#ibcon#read 5, iclass 40, count 0 2006.196.07:34:41.83#ibcon#about to read 6, iclass 40, count 0 2006.196.07:34:41.83#ibcon#read 6, iclass 40, count 0 2006.196.07:34:41.83#ibcon#end of sib2, iclass 40, count 0 2006.196.07:34:41.83#ibcon#*mode == 0, iclass 40, count 0 2006.196.07:34:41.83#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.196.07:34:41.83#ibcon#[27=USB\r\n] 2006.196.07:34:41.83#ibcon#*before write, iclass 40, count 0 2006.196.07:34:41.83#ibcon#enter sib2, iclass 40, count 0 2006.196.07:34:41.83#ibcon#flushed, iclass 40, count 0 2006.196.07:34:41.83#ibcon#about to write, iclass 40, count 0 2006.196.07:34:41.83#ibcon#wrote, iclass 40, count 0 2006.196.07:34:41.83#ibcon#about to read 3, iclass 40, count 0 2006.196.07:34:41.86#ibcon#read 3, iclass 40, count 0 2006.196.07:34:41.86#ibcon#about to read 4, iclass 40, count 0 2006.196.07:34:41.86#ibcon#read 4, iclass 40, count 0 2006.196.07:34:41.86#ibcon#about to read 5, iclass 40, count 0 2006.196.07:34:41.86#ibcon#read 5, iclass 40, count 0 2006.196.07:34:41.86#ibcon#about to read 6, iclass 40, count 0 2006.196.07:34:41.86#ibcon#read 6, iclass 40, count 0 2006.196.07:34:41.86#ibcon#end of sib2, iclass 40, count 0 2006.196.07:34:41.86#ibcon#*after write, iclass 40, count 0 2006.196.07:34:41.86#ibcon#*before return 0, iclass 40, count 0 2006.196.07:34:41.86#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.196.07:34:41.86#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.196.07:34:41.86#ibcon#about to clear, iclass 40 cls_cnt 0 2006.196.07:34:41.86#ibcon#cleared, iclass 40 cls_cnt 0 2006.196.07:34:41.86$vc4f8/vblo=5,744.99 2006.196.07:34:41.86#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.196.07:34:41.86#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.196.07:34:41.86#ibcon#ireg 17 cls_cnt 0 2006.196.07:34:41.86#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.196.07:34:41.86#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.196.07:34:41.86#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.196.07:34:41.86#ibcon#enter wrdev, iclass 4, count 0 2006.196.07:34:41.86#ibcon#first serial, iclass 4, count 0 2006.196.07:34:41.86#ibcon#enter sib2, iclass 4, count 0 2006.196.07:34:41.86#ibcon#flushed, iclass 4, count 0 2006.196.07:34:41.86#ibcon#about to write, iclass 4, count 0 2006.196.07:34:41.86#ibcon#wrote, iclass 4, count 0 2006.196.07:34:41.86#ibcon#about to read 3, iclass 4, count 0 2006.196.07:34:41.88#ibcon#read 3, iclass 4, count 0 2006.196.07:34:41.88#ibcon#about to read 4, iclass 4, count 0 2006.196.07:34:41.88#ibcon#read 4, iclass 4, count 0 2006.196.07:34:41.88#ibcon#about to read 5, iclass 4, count 0 2006.196.07:34:41.88#ibcon#read 5, iclass 4, count 0 2006.196.07:34:41.88#ibcon#about to read 6, iclass 4, count 0 2006.196.07:34:41.88#ibcon#read 6, iclass 4, count 0 2006.196.07:34:41.88#ibcon#end of sib2, iclass 4, count 0 2006.196.07:34:41.88#ibcon#*mode == 0, iclass 4, count 0 2006.196.07:34:41.88#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.196.07:34:41.88#ibcon#[28=FRQ=05,744.99\r\n] 2006.196.07:34:41.88#ibcon#*before write, iclass 4, count 0 2006.196.07:34:41.88#ibcon#enter sib2, iclass 4, count 0 2006.196.07:34:41.88#ibcon#flushed, iclass 4, count 0 2006.196.07:34:41.88#ibcon#about to write, iclass 4, count 0 2006.196.07:34:41.88#ibcon#wrote, iclass 4, count 0 2006.196.07:34:41.88#ibcon#about to read 3, iclass 4, count 0 2006.196.07:34:41.92#ibcon#read 3, iclass 4, count 0 2006.196.07:34:41.92#ibcon#about to read 4, iclass 4, count 0 2006.196.07:34:41.92#ibcon#read 4, iclass 4, count 0 2006.196.07:34:41.92#ibcon#about to read 5, iclass 4, count 0 2006.196.07:34:41.92#ibcon#read 5, iclass 4, count 0 2006.196.07:34:41.92#ibcon#about to read 6, iclass 4, count 0 2006.196.07:34:41.92#ibcon#read 6, iclass 4, count 0 2006.196.07:34:41.92#ibcon#end of sib2, iclass 4, count 0 2006.196.07:34:41.92#ibcon#*after write, iclass 4, count 0 2006.196.07:34:41.92#ibcon#*before return 0, iclass 4, count 0 2006.196.07:34:41.92#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.196.07:34:41.92#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.196.07:34:41.92#ibcon#about to clear, iclass 4 cls_cnt 0 2006.196.07:34:41.92#ibcon#cleared, iclass 4 cls_cnt 0 2006.196.07:34:41.92$vc4f8/vb=5,4 2006.196.07:34:41.92#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.196.07:34:41.92#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.196.07:34:41.92#ibcon#ireg 11 cls_cnt 2 2006.196.07:34:41.92#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.196.07:34:41.98#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.196.07:34:41.98#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.196.07:34:41.98#ibcon#enter wrdev, iclass 6, count 2 2006.196.07:34:41.98#ibcon#first serial, iclass 6, count 2 2006.196.07:34:41.98#ibcon#enter sib2, iclass 6, count 2 2006.196.07:34:41.98#ibcon#flushed, iclass 6, count 2 2006.196.07:34:41.98#ibcon#about to write, iclass 6, count 2 2006.196.07:34:41.98#ibcon#wrote, iclass 6, count 2 2006.196.07:34:41.98#ibcon#about to read 3, iclass 6, count 2 2006.196.07:34:42.00#ibcon#read 3, iclass 6, count 2 2006.196.07:34:42.00#ibcon#about to read 4, iclass 6, count 2 2006.196.07:34:42.00#ibcon#read 4, iclass 6, count 2 2006.196.07:34:42.00#ibcon#about to read 5, iclass 6, count 2 2006.196.07:34:42.00#ibcon#read 5, iclass 6, count 2 2006.196.07:34:42.00#ibcon#about to read 6, iclass 6, count 2 2006.196.07:34:42.00#ibcon#read 6, iclass 6, count 2 2006.196.07:34:42.00#ibcon#end of sib2, iclass 6, count 2 2006.196.07:34:42.00#ibcon#*mode == 0, iclass 6, count 2 2006.196.07:34:42.00#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.196.07:34:42.00#ibcon#[27=AT05-04\r\n] 2006.196.07:34:42.00#ibcon#*before write, iclass 6, count 2 2006.196.07:34:42.00#ibcon#enter sib2, iclass 6, count 2 2006.196.07:34:42.00#ibcon#flushed, iclass 6, count 2 2006.196.07:34:42.00#ibcon#about to write, iclass 6, count 2 2006.196.07:34:42.00#ibcon#wrote, iclass 6, count 2 2006.196.07:34:42.00#ibcon#about to read 3, iclass 6, count 2 2006.196.07:34:42.03#ibcon#read 3, iclass 6, count 2 2006.196.07:34:42.03#ibcon#about to read 4, iclass 6, count 2 2006.196.07:34:42.03#ibcon#read 4, iclass 6, count 2 2006.196.07:34:42.03#ibcon#about to read 5, iclass 6, count 2 2006.196.07:34:42.03#ibcon#read 5, iclass 6, count 2 2006.196.07:34:42.03#ibcon#about to read 6, iclass 6, count 2 2006.196.07:34:42.03#ibcon#read 6, iclass 6, count 2 2006.196.07:34:42.03#ibcon#end of sib2, iclass 6, count 2 2006.196.07:34:42.03#ibcon#*after write, iclass 6, count 2 2006.196.07:34:42.03#ibcon#*before return 0, iclass 6, count 2 2006.196.07:34:42.03#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.196.07:34:42.03#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.196.07:34:42.03#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.196.07:34:42.03#ibcon#ireg 7 cls_cnt 0 2006.196.07:34:42.03#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.196.07:34:42.15#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.196.07:34:42.15#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.196.07:34:42.15#ibcon#enter wrdev, iclass 6, count 0 2006.196.07:34:42.15#ibcon#first serial, iclass 6, count 0 2006.196.07:34:42.15#ibcon#enter sib2, iclass 6, count 0 2006.196.07:34:42.15#ibcon#flushed, iclass 6, count 0 2006.196.07:34:42.15#ibcon#about to write, iclass 6, count 0 2006.196.07:34:42.15#ibcon#wrote, iclass 6, count 0 2006.196.07:34:42.15#ibcon#about to read 3, iclass 6, count 0 2006.196.07:34:42.17#ibcon#read 3, iclass 6, count 0 2006.196.07:34:42.17#ibcon#about to read 4, iclass 6, count 0 2006.196.07:34:42.17#ibcon#read 4, iclass 6, count 0 2006.196.07:34:42.17#ibcon#about to read 5, iclass 6, count 0 2006.196.07:34:42.17#ibcon#read 5, iclass 6, count 0 2006.196.07:34:42.17#ibcon#about to read 6, iclass 6, count 0 2006.196.07:34:42.17#ibcon#read 6, iclass 6, count 0 2006.196.07:34:42.17#ibcon#end of sib2, iclass 6, count 0 2006.196.07:34:42.17#ibcon#*mode == 0, iclass 6, count 0 2006.196.07:34:42.17#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.196.07:34:42.17#ibcon#[27=USB\r\n] 2006.196.07:34:42.17#ibcon#*before write, iclass 6, count 0 2006.196.07:34:42.17#ibcon#enter sib2, iclass 6, count 0 2006.196.07:34:42.17#ibcon#flushed, iclass 6, count 0 2006.196.07:34:42.17#ibcon#about to write, iclass 6, count 0 2006.196.07:34:42.17#ibcon#wrote, iclass 6, count 0 2006.196.07:34:42.17#ibcon#about to read 3, iclass 6, count 0 2006.196.07:34:42.20#ibcon#read 3, iclass 6, count 0 2006.196.07:34:42.20#ibcon#about to read 4, iclass 6, count 0 2006.196.07:34:42.20#ibcon#read 4, iclass 6, count 0 2006.196.07:34:42.20#ibcon#about to read 5, iclass 6, count 0 2006.196.07:34:42.20#ibcon#read 5, iclass 6, count 0 2006.196.07:34:42.20#ibcon#about to read 6, iclass 6, count 0 2006.196.07:34:42.20#ibcon#read 6, iclass 6, count 0 2006.196.07:34:42.20#ibcon#end of sib2, iclass 6, count 0 2006.196.07:34:42.20#ibcon#*after write, iclass 6, count 0 2006.196.07:34:42.20#ibcon#*before return 0, iclass 6, count 0 2006.196.07:34:42.20#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.196.07:34:42.20#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.196.07:34:42.20#ibcon#about to clear, iclass 6 cls_cnt 0 2006.196.07:34:42.20#ibcon#cleared, iclass 6 cls_cnt 0 2006.196.07:34:42.20$vc4f8/vblo=6,752.99 2006.196.07:34:42.20#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.196.07:34:42.20#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.196.07:34:42.20#ibcon#ireg 17 cls_cnt 0 2006.196.07:34:42.20#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.196.07:34:42.20#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.196.07:34:42.20#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.196.07:34:42.20#ibcon#enter wrdev, iclass 10, count 0 2006.196.07:34:42.20#ibcon#first serial, iclass 10, count 0 2006.196.07:34:42.20#ibcon#enter sib2, iclass 10, count 0 2006.196.07:34:42.20#ibcon#flushed, iclass 10, count 0 2006.196.07:34:42.20#ibcon#about to write, iclass 10, count 0 2006.196.07:34:42.20#ibcon#wrote, iclass 10, count 0 2006.196.07:34:42.20#ibcon#about to read 3, iclass 10, count 0 2006.196.07:34:42.22#ibcon#read 3, iclass 10, count 0 2006.196.07:34:42.22#ibcon#about to read 4, iclass 10, count 0 2006.196.07:34:42.22#ibcon#read 4, iclass 10, count 0 2006.196.07:34:42.22#ibcon#about to read 5, iclass 10, count 0 2006.196.07:34:42.22#ibcon#read 5, iclass 10, count 0 2006.196.07:34:42.22#ibcon#about to read 6, iclass 10, count 0 2006.196.07:34:42.22#ibcon#read 6, iclass 10, count 0 2006.196.07:34:42.22#ibcon#end of sib2, iclass 10, count 0 2006.196.07:34:42.22#ibcon#*mode == 0, iclass 10, count 0 2006.196.07:34:42.22#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.196.07:34:42.22#ibcon#[28=FRQ=06,752.99\r\n] 2006.196.07:34:42.22#ibcon#*before write, iclass 10, count 0 2006.196.07:34:42.22#ibcon#enter sib2, iclass 10, count 0 2006.196.07:34:42.22#ibcon#flushed, iclass 10, count 0 2006.196.07:34:42.22#ibcon#about to write, iclass 10, count 0 2006.196.07:34:42.22#ibcon#wrote, iclass 10, count 0 2006.196.07:34:42.22#ibcon#about to read 3, iclass 10, count 0 2006.196.07:34:42.26#ibcon#read 3, iclass 10, count 0 2006.196.07:34:42.26#ibcon#about to read 4, iclass 10, count 0 2006.196.07:34:42.26#ibcon#read 4, iclass 10, count 0 2006.196.07:34:42.26#ibcon#about to read 5, iclass 10, count 0 2006.196.07:34:42.26#ibcon#read 5, iclass 10, count 0 2006.196.07:34:42.26#ibcon#about to read 6, iclass 10, count 0 2006.196.07:34:42.26#ibcon#read 6, iclass 10, count 0 2006.196.07:34:42.26#ibcon#end of sib2, iclass 10, count 0 2006.196.07:34:42.26#ibcon#*after write, iclass 10, count 0 2006.196.07:34:42.26#ibcon#*before return 0, iclass 10, count 0 2006.196.07:34:42.26#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.196.07:34:42.26#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.196.07:34:42.26#ibcon#about to clear, iclass 10 cls_cnt 0 2006.196.07:34:42.26#ibcon#cleared, iclass 10 cls_cnt 0 2006.196.07:34:42.26$vc4f8/vb=6,4 2006.196.07:34:42.26#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.196.07:34:42.26#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.196.07:34:42.26#ibcon#ireg 11 cls_cnt 2 2006.196.07:34:42.26#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.196.07:34:42.32#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.196.07:34:42.32#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.196.07:34:42.32#ibcon#enter wrdev, iclass 12, count 2 2006.196.07:34:42.32#ibcon#first serial, iclass 12, count 2 2006.196.07:34:42.32#ibcon#enter sib2, iclass 12, count 2 2006.196.07:34:42.32#ibcon#flushed, iclass 12, count 2 2006.196.07:34:42.32#ibcon#about to write, iclass 12, count 2 2006.196.07:34:42.32#ibcon#wrote, iclass 12, count 2 2006.196.07:34:42.32#ibcon#about to read 3, iclass 12, count 2 2006.196.07:34:42.34#ibcon#read 3, iclass 12, count 2 2006.196.07:34:42.34#ibcon#about to read 4, iclass 12, count 2 2006.196.07:34:42.34#ibcon#read 4, iclass 12, count 2 2006.196.07:34:42.34#ibcon#about to read 5, iclass 12, count 2 2006.196.07:34:42.34#ibcon#read 5, iclass 12, count 2 2006.196.07:34:42.34#ibcon#about to read 6, iclass 12, count 2 2006.196.07:34:42.34#ibcon#read 6, iclass 12, count 2 2006.196.07:34:42.34#ibcon#end of sib2, iclass 12, count 2 2006.196.07:34:42.34#ibcon#*mode == 0, iclass 12, count 2 2006.196.07:34:42.34#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.196.07:34:42.34#ibcon#[27=AT06-04\r\n] 2006.196.07:34:42.34#ibcon#*before write, iclass 12, count 2 2006.196.07:34:42.34#ibcon#enter sib2, iclass 12, count 2 2006.196.07:34:42.34#ibcon#flushed, iclass 12, count 2 2006.196.07:34:42.34#ibcon#about to write, iclass 12, count 2 2006.196.07:34:42.34#ibcon#wrote, iclass 12, count 2 2006.196.07:34:42.34#ibcon#about to read 3, iclass 12, count 2 2006.196.07:34:42.37#ibcon#read 3, iclass 12, count 2 2006.196.07:34:42.37#ibcon#about to read 4, iclass 12, count 2 2006.196.07:34:42.37#ibcon#read 4, iclass 12, count 2 2006.196.07:34:42.37#ibcon#about to read 5, iclass 12, count 2 2006.196.07:34:42.37#ibcon#read 5, iclass 12, count 2 2006.196.07:34:42.37#ibcon#about to read 6, iclass 12, count 2 2006.196.07:34:42.37#ibcon#read 6, iclass 12, count 2 2006.196.07:34:42.37#ibcon#end of sib2, iclass 12, count 2 2006.196.07:34:42.37#ibcon#*after write, iclass 12, count 2 2006.196.07:34:42.37#ibcon#*before return 0, iclass 12, count 2 2006.196.07:34:42.37#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.196.07:34:42.37#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.196.07:34:42.37#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.196.07:34:42.37#ibcon#ireg 7 cls_cnt 0 2006.196.07:34:42.37#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.196.07:34:42.49#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.196.07:34:42.49#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.196.07:34:42.49#ibcon#enter wrdev, iclass 12, count 0 2006.196.07:34:42.49#ibcon#first serial, iclass 12, count 0 2006.196.07:34:42.49#ibcon#enter sib2, iclass 12, count 0 2006.196.07:34:42.49#ibcon#flushed, iclass 12, count 0 2006.196.07:34:42.49#ibcon#about to write, iclass 12, count 0 2006.196.07:34:42.49#ibcon#wrote, iclass 12, count 0 2006.196.07:34:42.49#ibcon#about to read 3, iclass 12, count 0 2006.196.07:34:42.51#ibcon#read 3, iclass 12, count 0 2006.196.07:34:42.51#ibcon#about to read 4, iclass 12, count 0 2006.196.07:34:42.51#ibcon#read 4, iclass 12, count 0 2006.196.07:34:42.51#ibcon#about to read 5, iclass 12, count 0 2006.196.07:34:42.51#ibcon#read 5, iclass 12, count 0 2006.196.07:34:42.51#ibcon#about to read 6, iclass 12, count 0 2006.196.07:34:42.51#ibcon#read 6, iclass 12, count 0 2006.196.07:34:42.51#ibcon#end of sib2, iclass 12, count 0 2006.196.07:34:42.51#ibcon#*mode == 0, iclass 12, count 0 2006.196.07:34:42.51#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.196.07:34:42.51#ibcon#[27=USB\r\n] 2006.196.07:34:42.51#ibcon#*before write, iclass 12, count 0 2006.196.07:34:42.51#ibcon#enter sib2, iclass 12, count 0 2006.196.07:34:42.51#ibcon#flushed, iclass 12, count 0 2006.196.07:34:42.51#ibcon#about to write, iclass 12, count 0 2006.196.07:34:42.51#ibcon#wrote, iclass 12, count 0 2006.196.07:34:42.51#ibcon#about to read 3, iclass 12, count 0 2006.196.07:34:42.54#ibcon#read 3, iclass 12, count 0 2006.196.07:34:42.54#ibcon#about to read 4, iclass 12, count 0 2006.196.07:34:42.54#ibcon#read 4, iclass 12, count 0 2006.196.07:34:42.54#ibcon#about to read 5, iclass 12, count 0 2006.196.07:34:42.54#ibcon#read 5, iclass 12, count 0 2006.196.07:34:42.54#ibcon#about to read 6, iclass 12, count 0 2006.196.07:34:42.54#ibcon#read 6, iclass 12, count 0 2006.196.07:34:42.54#ibcon#end of sib2, iclass 12, count 0 2006.196.07:34:42.54#ibcon#*after write, iclass 12, count 0 2006.196.07:34:42.54#ibcon#*before return 0, iclass 12, count 0 2006.196.07:34:42.54#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.196.07:34:42.54#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.196.07:34:42.54#ibcon#about to clear, iclass 12 cls_cnt 0 2006.196.07:34:42.54#ibcon#cleared, iclass 12 cls_cnt 0 2006.196.07:34:42.54$vc4f8/vabw=wide 2006.196.07:34:42.54#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.196.07:34:42.54#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.196.07:34:42.54#ibcon#ireg 8 cls_cnt 0 2006.196.07:34:42.54#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.196.07:34:42.54#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.196.07:34:42.54#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.196.07:34:42.54#ibcon#enter wrdev, iclass 14, count 0 2006.196.07:34:42.54#ibcon#first serial, iclass 14, count 0 2006.196.07:34:42.54#ibcon#enter sib2, iclass 14, count 0 2006.196.07:34:42.54#ibcon#flushed, iclass 14, count 0 2006.196.07:34:42.54#ibcon#about to write, iclass 14, count 0 2006.196.07:34:42.54#ibcon#wrote, iclass 14, count 0 2006.196.07:34:42.54#ibcon#about to read 3, iclass 14, count 0 2006.196.07:34:42.56#ibcon#read 3, iclass 14, count 0 2006.196.07:34:42.56#ibcon#about to read 4, iclass 14, count 0 2006.196.07:34:42.56#ibcon#read 4, iclass 14, count 0 2006.196.07:34:42.56#ibcon#about to read 5, iclass 14, count 0 2006.196.07:34:42.56#ibcon#read 5, iclass 14, count 0 2006.196.07:34:42.56#ibcon#about to read 6, iclass 14, count 0 2006.196.07:34:42.56#ibcon#read 6, iclass 14, count 0 2006.196.07:34:42.56#ibcon#end of sib2, iclass 14, count 0 2006.196.07:34:42.56#ibcon#*mode == 0, iclass 14, count 0 2006.196.07:34:42.56#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.196.07:34:42.56#ibcon#[25=BW32\r\n] 2006.196.07:34:42.56#ibcon#*before write, iclass 14, count 0 2006.196.07:34:42.56#ibcon#enter sib2, iclass 14, count 0 2006.196.07:34:42.56#ibcon#flushed, iclass 14, count 0 2006.196.07:34:42.56#ibcon#about to write, iclass 14, count 0 2006.196.07:34:42.56#ibcon#wrote, iclass 14, count 0 2006.196.07:34:42.56#ibcon#about to read 3, iclass 14, count 0 2006.196.07:34:42.59#ibcon#read 3, iclass 14, count 0 2006.196.07:34:42.59#ibcon#about to read 4, iclass 14, count 0 2006.196.07:34:42.59#ibcon#read 4, iclass 14, count 0 2006.196.07:34:42.59#ibcon#about to read 5, iclass 14, count 0 2006.196.07:34:42.59#ibcon#read 5, iclass 14, count 0 2006.196.07:34:42.59#ibcon#about to read 6, iclass 14, count 0 2006.196.07:34:42.59#ibcon#read 6, iclass 14, count 0 2006.196.07:34:42.59#ibcon#end of sib2, iclass 14, count 0 2006.196.07:34:42.59#ibcon#*after write, iclass 14, count 0 2006.196.07:34:42.59#ibcon#*before return 0, iclass 14, count 0 2006.196.07:34:42.59#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.196.07:34:42.59#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.196.07:34:42.59#ibcon#about to clear, iclass 14 cls_cnt 0 2006.196.07:34:42.59#ibcon#cleared, iclass 14 cls_cnt 0 2006.196.07:34:42.59$vc4f8/vbbw=wide 2006.196.07:34:42.59#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.196.07:34:42.59#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.196.07:34:42.59#ibcon#ireg 8 cls_cnt 0 2006.196.07:34:42.59#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.196.07:34:42.66#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.196.07:34:42.66#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.196.07:34:42.66#ibcon#enter wrdev, iclass 16, count 0 2006.196.07:34:42.66#ibcon#first serial, iclass 16, count 0 2006.196.07:34:42.66#ibcon#enter sib2, iclass 16, count 0 2006.196.07:34:42.66#ibcon#flushed, iclass 16, count 0 2006.196.07:34:42.66#ibcon#about to write, iclass 16, count 0 2006.196.07:34:42.66#ibcon#wrote, iclass 16, count 0 2006.196.07:34:42.66#ibcon#about to read 3, iclass 16, count 0 2006.196.07:34:42.68#ibcon#read 3, iclass 16, count 0 2006.196.07:34:42.68#ibcon#about to read 4, iclass 16, count 0 2006.196.07:34:42.68#ibcon#read 4, iclass 16, count 0 2006.196.07:34:42.68#ibcon#about to read 5, iclass 16, count 0 2006.196.07:34:42.68#ibcon#read 5, iclass 16, count 0 2006.196.07:34:42.68#ibcon#about to read 6, iclass 16, count 0 2006.196.07:34:42.68#ibcon#read 6, iclass 16, count 0 2006.196.07:34:42.68#ibcon#end of sib2, iclass 16, count 0 2006.196.07:34:42.68#ibcon#*mode == 0, iclass 16, count 0 2006.196.07:34:42.68#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.196.07:34:42.68#ibcon#[27=BW32\r\n] 2006.196.07:34:42.68#ibcon#*before write, iclass 16, count 0 2006.196.07:34:42.68#ibcon#enter sib2, iclass 16, count 0 2006.196.07:34:42.68#ibcon#flushed, iclass 16, count 0 2006.196.07:34:42.68#ibcon#about to write, iclass 16, count 0 2006.196.07:34:42.68#ibcon#wrote, iclass 16, count 0 2006.196.07:34:42.68#ibcon#about to read 3, iclass 16, count 0 2006.196.07:34:42.71#ibcon#read 3, iclass 16, count 0 2006.196.07:34:42.71#ibcon#about to read 4, iclass 16, count 0 2006.196.07:34:42.71#ibcon#read 4, iclass 16, count 0 2006.196.07:34:42.71#ibcon#about to read 5, iclass 16, count 0 2006.196.07:34:42.71#ibcon#read 5, iclass 16, count 0 2006.196.07:34:42.71#ibcon#about to read 6, iclass 16, count 0 2006.196.07:34:42.71#ibcon#read 6, iclass 16, count 0 2006.196.07:34:42.71#ibcon#end of sib2, iclass 16, count 0 2006.196.07:34:42.71#ibcon#*after write, iclass 16, count 0 2006.196.07:34:42.71#ibcon#*before return 0, iclass 16, count 0 2006.196.07:34:42.71#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.196.07:34:42.71#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.196.07:34:42.71#ibcon#about to clear, iclass 16 cls_cnt 0 2006.196.07:34:42.71#ibcon#cleared, iclass 16 cls_cnt 0 2006.196.07:34:42.71$4f8m12a/ifd4f 2006.196.07:34:42.71$ifd4f/lo= 2006.196.07:34:42.71$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.196.07:34:42.71$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.196.07:34:42.71$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.196.07:34:42.71$ifd4f/patch= 2006.196.07:34:42.71$ifd4f/patch=lo1,a1,a2,a3,a4 2006.196.07:34:42.71$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.196.07:34:42.71$ifd4f/patch=lo3,a5,a6,a7,a8 2006.196.07:34:42.71$4f8m12a/"form=m,16.000,1:2 2006.196.07:34:42.71$4f8m12a/"tpicd 2006.196.07:34:42.71$4f8m12a/echo=off 2006.196.07:34:42.71$4f8m12a/xlog=off 2006.196.07:34:42.71:!2006.196.07:35:10 2006.196.07:34:52.14#trakl#Source acquired 2006.196.07:34:52.14#flagr#flagr/antenna,acquired 2006.196.07:35:10.00:preob 2006.196.07:35:11.14/onsource/TRACKING 2006.196.07:35:11.14:!2006.196.07:35:20 2006.196.07:35:20.00:data_valid=on 2006.196.07:35:20.00:midob 2006.196.07:35:20.14/onsource/TRACKING 2006.196.07:35:20.14/wx/30.18,1004.1,85 2006.196.07:35:20.31/cable/+6.3333E-03 2006.196.07:35:21.40/va/01,08,usb,yes,29,30 2006.196.07:35:21.40/va/02,07,usb,yes,29,31 2006.196.07:35:21.40/va/03,06,usb,yes,31,31 2006.196.07:35:21.40/va/04,07,usb,yes,30,32 2006.196.07:35:21.40/va/05,07,usb,yes,31,33 2006.196.07:35:21.40/va/06,06,usb,yes,30,30 2006.196.07:35:21.40/va/07,06,usb,yes,31,31 2006.196.07:35:21.40/va/08,07,usb,yes,29,29 2006.196.07:35:21.63/valo/01,532.99,yes,locked 2006.196.07:35:21.63/valo/02,572.99,yes,locked 2006.196.07:35:21.63/valo/03,672.99,yes,locked 2006.196.07:35:21.63/valo/04,832.99,yes,locked 2006.196.07:35:21.63/valo/05,652.99,yes,locked 2006.196.07:35:21.63/valo/06,772.99,yes,locked 2006.196.07:35:21.63/valo/07,832.99,yes,locked 2006.196.07:35:21.63/valo/08,852.99,yes,locked 2006.196.07:35:22.72/vb/01,04,usb,yes,29,27 2006.196.07:35:22.72/vb/02,04,usb,yes,30,32 2006.196.07:35:22.72/vb/03,04,usb,yes,27,30 2006.196.07:35:22.72/vb/04,04,usb,yes,28,28 2006.196.07:35:22.72/vb/05,04,usb,yes,26,30 2006.196.07:35:22.72/vb/06,04,usb,yes,27,30 2006.196.07:35:22.72/vb/07,04,usb,yes,29,29 2006.196.07:35:22.72/vb/08,04,usb,yes,27,30 2006.196.07:35:22.96/vblo/01,632.99,yes,locked 2006.196.07:35:22.96/vblo/02,640.99,yes,locked 2006.196.07:35:22.96/vblo/03,656.99,yes,locked 2006.196.07:35:22.96/vblo/04,712.99,yes,locked 2006.196.07:35:22.96/vblo/05,744.99,yes,locked 2006.196.07:35:22.96/vblo/06,752.99,yes,locked 2006.196.07:35:22.96/vblo/07,734.99,yes,locked 2006.196.07:35:22.96/vblo/08,744.99,yes,locked 2006.196.07:35:23.11/vabw/8 2006.196.07:35:23.26/vbbw/8 2006.196.07:35:23.35/xfe/off,on,15.5 2006.196.07:35:23.75/ifatt/23,28,28,28 2006.196.07:35:24.07/fmout-gps/S +3.36E-07 2006.196.07:35:24.11:!2006.196.07:36:20 2006.196.07:36:20.00:data_valid=off 2006.196.07:36:20.00:postob 2006.196.07:36:20.10/cable/+6.3340E-03 2006.196.07:36:20.10/wx/30.14,1004.0,86 2006.196.07:36:21.06/fmout-gps/S +3.35E-07 2006.196.07:36:21.06:scan_name=196-0737,k06196,60 2006.196.07:36:21.06:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.196.07:36:21.14#flagr#flagr/antenna,new-source 2006.196.07:36:22.14:checkk5 2006.196.07:36:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.196.07:36:22.88/chk_autoobs//k5ts2/ autoobs is running! 2006.196.07:36:23.27/chk_autoobs//k5ts3/ autoobs is running! 2006.196.07:36:23.64/chk_autoobs//k5ts4/ autoobs is running! 2006.196.07:36:24.02/chk_obsdata//k5ts1/T1960735??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.07:36:24.39/chk_obsdata//k5ts2/T1960735??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.07:36:24.75/chk_obsdata//k5ts3/T1960735??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.07:36:25.12/chk_obsdata//k5ts4/T1960735??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.07:36:25.81/k5log//k5ts1_log_newline 2006.196.07:36:26.50/k5log//k5ts2_log_newline 2006.196.07:36:27.18/k5log//k5ts3_log_newline 2006.196.07:36:27.86/k5log//k5ts4_log_newline 2006.196.07:36:27.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.196.07:36:27.89:4f8m12a=1 2006.196.07:36:27.89$4f8m12a/echo=on 2006.196.07:36:27.89$4f8m12a/pcalon 2006.196.07:36:27.89$pcalon/"no phase cal control is implemented here 2006.196.07:36:27.89$4f8m12a/"tpicd=stop 2006.196.07:36:27.89$4f8m12a/vc4f8 2006.196.07:36:27.89$vc4f8/valo=1,532.99 2006.196.07:36:27.89#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.196.07:36:27.89#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.196.07:36:27.89#ibcon#ireg 17 cls_cnt 0 2006.196.07:36:27.89#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.196.07:36:27.89#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.196.07:36:27.89#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.196.07:36:27.89#ibcon#enter wrdev, iclass 23, count 0 2006.196.07:36:27.89#ibcon#first serial, iclass 23, count 0 2006.196.07:36:27.89#ibcon#enter sib2, iclass 23, count 0 2006.196.07:36:27.89#ibcon#flushed, iclass 23, count 0 2006.196.07:36:27.89#ibcon#about to write, iclass 23, count 0 2006.196.07:36:27.89#ibcon#wrote, iclass 23, count 0 2006.196.07:36:27.89#ibcon#about to read 3, iclass 23, count 0 2006.196.07:36:27.91#ibcon#read 3, iclass 23, count 0 2006.196.07:36:27.91#ibcon#about to read 4, iclass 23, count 0 2006.196.07:36:27.91#ibcon#read 4, iclass 23, count 0 2006.196.07:36:27.91#ibcon#about to read 5, iclass 23, count 0 2006.196.07:36:27.91#ibcon#read 5, iclass 23, count 0 2006.196.07:36:27.91#ibcon#about to read 6, iclass 23, count 0 2006.196.07:36:27.91#ibcon#read 6, iclass 23, count 0 2006.196.07:36:27.91#ibcon#end of sib2, iclass 23, count 0 2006.196.07:36:27.91#ibcon#*mode == 0, iclass 23, count 0 2006.196.07:36:27.91#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.196.07:36:27.91#ibcon#[26=FRQ=01,532.99\r\n] 2006.196.07:36:27.91#ibcon#*before write, iclass 23, count 0 2006.196.07:36:27.91#ibcon#enter sib2, iclass 23, count 0 2006.196.07:36:27.91#ibcon#flushed, iclass 23, count 0 2006.196.07:36:27.91#ibcon#about to write, iclass 23, count 0 2006.196.07:36:27.91#ibcon#wrote, iclass 23, count 0 2006.196.07:36:27.91#ibcon#about to read 3, iclass 23, count 0 2006.196.07:36:27.96#ibcon#read 3, iclass 23, count 0 2006.196.07:36:27.96#ibcon#about to read 4, iclass 23, count 0 2006.196.07:36:27.96#ibcon#read 4, iclass 23, count 0 2006.196.07:36:27.96#ibcon#about to read 5, iclass 23, count 0 2006.196.07:36:27.96#ibcon#read 5, iclass 23, count 0 2006.196.07:36:27.96#ibcon#about to read 6, iclass 23, count 0 2006.196.07:36:27.96#ibcon#read 6, iclass 23, count 0 2006.196.07:36:27.96#ibcon#end of sib2, iclass 23, count 0 2006.196.07:36:27.96#ibcon#*after write, iclass 23, count 0 2006.196.07:36:27.96#ibcon#*before return 0, iclass 23, count 0 2006.196.07:36:27.96#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.196.07:36:27.96#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.196.07:36:27.96#ibcon#about to clear, iclass 23 cls_cnt 0 2006.196.07:36:27.96#ibcon#cleared, iclass 23 cls_cnt 0 2006.196.07:36:27.96$vc4f8/va=1,8 2006.196.07:36:27.96#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.196.07:36:27.96#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.196.07:36:27.96#ibcon#ireg 11 cls_cnt 2 2006.196.07:36:27.96#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.196.07:36:27.96#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.196.07:36:27.96#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.196.07:36:27.96#ibcon#enter wrdev, iclass 25, count 2 2006.196.07:36:27.96#ibcon#first serial, iclass 25, count 2 2006.196.07:36:27.96#ibcon#enter sib2, iclass 25, count 2 2006.196.07:36:27.96#ibcon#flushed, iclass 25, count 2 2006.196.07:36:27.96#ibcon#about to write, iclass 25, count 2 2006.196.07:36:27.96#ibcon#wrote, iclass 25, count 2 2006.196.07:36:27.96#ibcon#about to read 3, iclass 25, count 2 2006.196.07:36:27.98#ibcon#read 3, iclass 25, count 2 2006.196.07:36:27.98#ibcon#about to read 4, iclass 25, count 2 2006.196.07:36:27.98#ibcon#read 4, iclass 25, count 2 2006.196.07:36:27.98#ibcon#about to read 5, iclass 25, count 2 2006.196.07:36:27.98#ibcon#read 5, iclass 25, count 2 2006.196.07:36:27.98#ibcon#about to read 6, iclass 25, count 2 2006.196.07:36:27.98#ibcon#read 6, iclass 25, count 2 2006.196.07:36:27.98#ibcon#end of sib2, iclass 25, count 2 2006.196.07:36:27.98#ibcon#*mode == 0, iclass 25, count 2 2006.196.07:36:27.98#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.196.07:36:27.98#ibcon#[25=AT01-08\r\n] 2006.196.07:36:27.98#ibcon#*before write, iclass 25, count 2 2006.196.07:36:27.98#ibcon#enter sib2, iclass 25, count 2 2006.196.07:36:27.98#ibcon#flushed, iclass 25, count 2 2006.196.07:36:27.98#ibcon#about to write, iclass 25, count 2 2006.196.07:36:27.98#ibcon#wrote, iclass 25, count 2 2006.196.07:36:27.98#ibcon#about to read 3, iclass 25, count 2 2006.196.07:36:28.01#ibcon#read 3, iclass 25, count 2 2006.196.07:36:28.01#ibcon#about to read 4, iclass 25, count 2 2006.196.07:36:28.01#ibcon#read 4, iclass 25, count 2 2006.196.07:36:28.01#ibcon#about to read 5, iclass 25, count 2 2006.196.07:36:28.01#ibcon#read 5, iclass 25, count 2 2006.196.07:36:28.01#ibcon#about to read 6, iclass 25, count 2 2006.196.07:36:28.01#ibcon#read 6, iclass 25, count 2 2006.196.07:36:28.01#ibcon#end of sib2, iclass 25, count 2 2006.196.07:36:28.01#ibcon#*after write, iclass 25, count 2 2006.196.07:36:28.01#ibcon#*before return 0, iclass 25, count 2 2006.196.07:36:28.01#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.196.07:36:28.01#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.196.07:36:28.01#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.196.07:36:28.01#ibcon#ireg 7 cls_cnt 0 2006.196.07:36:28.01#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.196.07:36:28.13#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.196.07:36:28.13#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.196.07:36:28.13#ibcon#enter wrdev, iclass 25, count 0 2006.196.07:36:28.13#ibcon#first serial, iclass 25, count 0 2006.196.07:36:28.13#ibcon#enter sib2, iclass 25, count 0 2006.196.07:36:28.13#ibcon#flushed, iclass 25, count 0 2006.196.07:36:28.13#ibcon#about to write, iclass 25, count 0 2006.196.07:36:28.13#ibcon#wrote, iclass 25, count 0 2006.196.07:36:28.13#ibcon#about to read 3, iclass 25, count 0 2006.196.07:36:28.15#ibcon#read 3, iclass 25, count 0 2006.196.07:36:28.15#ibcon#about to read 4, iclass 25, count 0 2006.196.07:36:28.15#ibcon#read 4, iclass 25, count 0 2006.196.07:36:28.15#ibcon#about to read 5, iclass 25, count 0 2006.196.07:36:28.15#ibcon#read 5, iclass 25, count 0 2006.196.07:36:28.15#ibcon#about to read 6, iclass 25, count 0 2006.196.07:36:28.15#ibcon#read 6, iclass 25, count 0 2006.196.07:36:28.15#ibcon#end of sib2, iclass 25, count 0 2006.196.07:36:28.15#ibcon#*mode == 0, iclass 25, count 0 2006.196.07:36:28.15#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.196.07:36:28.15#ibcon#[25=USB\r\n] 2006.196.07:36:28.15#ibcon#*before write, iclass 25, count 0 2006.196.07:36:28.15#ibcon#enter sib2, iclass 25, count 0 2006.196.07:36:28.15#ibcon#flushed, iclass 25, count 0 2006.196.07:36:28.15#ibcon#about to write, iclass 25, count 0 2006.196.07:36:28.15#ibcon#wrote, iclass 25, count 0 2006.196.07:36:28.15#ibcon#about to read 3, iclass 25, count 0 2006.196.07:36:28.18#ibcon#read 3, iclass 25, count 0 2006.196.07:36:28.18#ibcon#about to read 4, iclass 25, count 0 2006.196.07:36:28.18#ibcon#read 4, iclass 25, count 0 2006.196.07:36:28.18#ibcon#about to read 5, iclass 25, count 0 2006.196.07:36:28.18#ibcon#read 5, iclass 25, count 0 2006.196.07:36:28.18#ibcon#about to read 6, iclass 25, count 0 2006.196.07:36:28.18#ibcon#read 6, iclass 25, count 0 2006.196.07:36:28.18#ibcon#end of sib2, iclass 25, count 0 2006.196.07:36:28.18#ibcon#*after write, iclass 25, count 0 2006.196.07:36:28.18#ibcon#*before return 0, iclass 25, count 0 2006.196.07:36:28.18#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.196.07:36:28.18#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.196.07:36:28.18#ibcon#about to clear, iclass 25 cls_cnt 0 2006.196.07:36:28.18#ibcon#cleared, iclass 25 cls_cnt 0 2006.196.07:36:28.18$vc4f8/valo=2,572.99 2006.196.07:36:28.18#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.196.07:36:28.18#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.196.07:36:28.18#ibcon#ireg 17 cls_cnt 0 2006.196.07:36:28.18#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.196.07:36:28.18#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.196.07:36:28.18#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.196.07:36:28.18#ibcon#enter wrdev, iclass 27, count 0 2006.196.07:36:28.18#ibcon#first serial, iclass 27, count 0 2006.196.07:36:28.18#ibcon#enter sib2, iclass 27, count 0 2006.196.07:36:28.18#ibcon#flushed, iclass 27, count 0 2006.196.07:36:28.18#ibcon#about to write, iclass 27, count 0 2006.196.07:36:28.18#ibcon#wrote, iclass 27, count 0 2006.196.07:36:28.18#ibcon#about to read 3, iclass 27, count 0 2006.196.07:36:28.20#ibcon#read 3, iclass 27, count 0 2006.196.07:36:28.20#ibcon#about to read 4, iclass 27, count 0 2006.196.07:36:28.20#ibcon#read 4, iclass 27, count 0 2006.196.07:36:28.20#ibcon#about to read 5, iclass 27, count 0 2006.196.07:36:28.20#ibcon#read 5, iclass 27, count 0 2006.196.07:36:28.20#ibcon#about to read 6, iclass 27, count 0 2006.196.07:36:28.20#ibcon#read 6, iclass 27, count 0 2006.196.07:36:28.20#ibcon#end of sib2, iclass 27, count 0 2006.196.07:36:28.20#ibcon#*mode == 0, iclass 27, count 0 2006.196.07:36:28.20#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.196.07:36:28.20#ibcon#[26=FRQ=02,572.99\r\n] 2006.196.07:36:28.20#ibcon#*before write, iclass 27, count 0 2006.196.07:36:28.20#ibcon#enter sib2, iclass 27, count 0 2006.196.07:36:28.20#ibcon#flushed, iclass 27, count 0 2006.196.07:36:28.20#ibcon#about to write, iclass 27, count 0 2006.196.07:36:28.20#ibcon#wrote, iclass 27, count 0 2006.196.07:36:28.20#ibcon#about to read 3, iclass 27, count 0 2006.196.07:36:28.25#ibcon#read 3, iclass 27, count 0 2006.196.07:36:28.25#ibcon#about to read 4, iclass 27, count 0 2006.196.07:36:28.25#ibcon#read 4, iclass 27, count 0 2006.196.07:36:28.25#ibcon#about to read 5, iclass 27, count 0 2006.196.07:36:28.25#ibcon#read 5, iclass 27, count 0 2006.196.07:36:28.25#ibcon#about to read 6, iclass 27, count 0 2006.196.07:36:28.25#ibcon#read 6, iclass 27, count 0 2006.196.07:36:28.25#ibcon#end of sib2, iclass 27, count 0 2006.196.07:36:28.25#ibcon#*after write, iclass 27, count 0 2006.196.07:36:28.25#ibcon#*before return 0, iclass 27, count 0 2006.196.07:36:28.25#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.196.07:36:28.25#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.196.07:36:28.25#ibcon#about to clear, iclass 27 cls_cnt 0 2006.196.07:36:28.25#ibcon#cleared, iclass 27 cls_cnt 0 2006.196.07:36:28.25$vc4f8/va=2,7 2006.196.07:36:28.25#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.196.07:36:28.25#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.196.07:36:28.25#ibcon#ireg 11 cls_cnt 2 2006.196.07:36:28.25#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.196.07:36:28.30#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.196.07:36:28.30#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.196.07:36:28.30#ibcon#enter wrdev, iclass 29, count 2 2006.196.07:36:28.30#ibcon#first serial, iclass 29, count 2 2006.196.07:36:28.30#ibcon#enter sib2, iclass 29, count 2 2006.196.07:36:28.30#ibcon#flushed, iclass 29, count 2 2006.196.07:36:28.30#ibcon#about to write, iclass 29, count 2 2006.196.07:36:28.30#ibcon#wrote, iclass 29, count 2 2006.196.07:36:28.30#ibcon#about to read 3, iclass 29, count 2 2006.196.07:36:28.32#ibcon#read 3, iclass 29, count 2 2006.196.07:36:28.32#ibcon#about to read 4, iclass 29, count 2 2006.196.07:36:28.32#ibcon#read 4, iclass 29, count 2 2006.196.07:36:28.32#ibcon#about to read 5, iclass 29, count 2 2006.196.07:36:28.32#ibcon#read 5, iclass 29, count 2 2006.196.07:36:28.32#ibcon#about to read 6, iclass 29, count 2 2006.196.07:36:28.32#ibcon#read 6, iclass 29, count 2 2006.196.07:36:28.32#ibcon#end of sib2, iclass 29, count 2 2006.196.07:36:28.32#ibcon#*mode == 0, iclass 29, count 2 2006.196.07:36:28.32#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.196.07:36:28.32#ibcon#[25=AT02-07\r\n] 2006.196.07:36:28.32#ibcon#*before write, iclass 29, count 2 2006.196.07:36:28.32#ibcon#enter sib2, iclass 29, count 2 2006.196.07:36:28.32#ibcon#flushed, iclass 29, count 2 2006.196.07:36:28.32#ibcon#about to write, iclass 29, count 2 2006.196.07:36:28.32#ibcon#wrote, iclass 29, count 2 2006.196.07:36:28.32#ibcon#about to read 3, iclass 29, count 2 2006.196.07:36:28.35#ibcon#read 3, iclass 29, count 2 2006.196.07:36:28.35#ibcon#about to read 4, iclass 29, count 2 2006.196.07:36:28.35#ibcon#read 4, iclass 29, count 2 2006.196.07:36:28.35#ibcon#about to read 5, iclass 29, count 2 2006.196.07:36:28.35#ibcon#read 5, iclass 29, count 2 2006.196.07:36:28.35#ibcon#about to read 6, iclass 29, count 2 2006.196.07:36:28.35#ibcon#read 6, iclass 29, count 2 2006.196.07:36:28.35#ibcon#end of sib2, iclass 29, count 2 2006.196.07:36:28.35#ibcon#*after write, iclass 29, count 2 2006.196.07:36:28.35#ibcon#*before return 0, iclass 29, count 2 2006.196.07:36:28.35#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.196.07:36:28.35#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.196.07:36:28.35#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.196.07:36:28.35#ibcon#ireg 7 cls_cnt 0 2006.196.07:36:28.35#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.196.07:36:28.47#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.196.07:36:28.47#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.196.07:36:28.47#ibcon#enter wrdev, iclass 29, count 0 2006.196.07:36:28.47#ibcon#first serial, iclass 29, count 0 2006.196.07:36:28.47#ibcon#enter sib2, iclass 29, count 0 2006.196.07:36:28.47#ibcon#flushed, iclass 29, count 0 2006.196.07:36:28.47#ibcon#about to write, iclass 29, count 0 2006.196.07:36:28.47#ibcon#wrote, iclass 29, count 0 2006.196.07:36:28.47#ibcon#about to read 3, iclass 29, count 0 2006.196.07:36:28.49#ibcon#read 3, iclass 29, count 0 2006.196.07:36:28.49#ibcon#about to read 4, iclass 29, count 0 2006.196.07:36:28.49#ibcon#read 4, iclass 29, count 0 2006.196.07:36:28.49#ibcon#about to read 5, iclass 29, count 0 2006.196.07:36:28.49#ibcon#read 5, iclass 29, count 0 2006.196.07:36:28.49#ibcon#about to read 6, iclass 29, count 0 2006.196.07:36:28.49#ibcon#read 6, iclass 29, count 0 2006.196.07:36:28.49#ibcon#end of sib2, iclass 29, count 0 2006.196.07:36:28.49#ibcon#*mode == 0, iclass 29, count 0 2006.196.07:36:28.49#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.196.07:36:28.49#ibcon#[25=USB\r\n] 2006.196.07:36:28.49#ibcon#*before write, iclass 29, count 0 2006.196.07:36:28.49#ibcon#enter sib2, iclass 29, count 0 2006.196.07:36:28.49#ibcon#flushed, iclass 29, count 0 2006.196.07:36:28.49#ibcon#about to write, iclass 29, count 0 2006.196.07:36:28.49#ibcon#wrote, iclass 29, count 0 2006.196.07:36:28.49#ibcon#about to read 3, iclass 29, count 0 2006.196.07:36:28.52#ibcon#read 3, iclass 29, count 0 2006.196.07:36:28.52#ibcon#about to read 4, iclass 29, count 0 2006.196.07:36:28.52#ibcon#read 4, iclass 29, count 0 2006.196.07:36:28.52#ibcon#about to read 5, iclass 29, count 0 2006.196.07:36:28.52#ibcon#read 5, iclass 29, count 0 2006.196.07:36:28.52#ibcon#about to read 6, iclass 29, count 0 2006.196.07:36:28.52#ibcon#read 6, iclass 29, count 0 2006.196.07:36:28.52#ibcon#end of sib2, iclass 29, count 0 2006.196.07:36:28.52#ibcon#*after write, iclass 29, count 0 2006.196.07:36:28.52#ibcon#*before return 0, iclass 29, count 0 2006.196.07:36:28.52#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.196.07:36:28.52#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.196.07:36:28.52#ibcon#about to clear, iclass 29 cls_cnt 0 2006.196.07:36:28.52#ibcon#cleared, iclass 29 cls_cnt 0 2006.196.07:36:28.52$vc4f8/valo=3,672.99 2006.196.07:36:28.52#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.196.07:36:28.52#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.196.07:36:28.52#ibcon#ireg 17 cls_cnt 0 2006.196.07:36:28.52#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.196.07:36:28.52#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.196.07:36:28.52#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.196.07:36:28.52#ibcon#enter wrdev, iclass 31, count 0 2006.196.07:36:28.52#ibcon#first serial, iclass 31, count 0 2006.196.07:36:28.52#ibcon#enter sib2, iclass 31, count 0 2006.196.07:36:28.52#ibcon#flushed, iclass 31, count 0 2006.196.07:36:28.52#ibcon#about to write, iclass 31, count 0 2006.196.07:36:28.52#ibcon#wrote, iclass 31, count 0 2006.196.07:36:28.52#ibcon#about to read 3, iclass 31, count 0 2006.196.07:36:28.54#ibcon#read 3, iclass 31, count 0 2006.196.07:36:28.54#ibcon#about to read 4, iclass 31, count 0 2006.196.07:36:28.54#ibcon#read 4, iclass 31, count 0 2006.196.07:36:28.54#ibcon#about to read 5, iclass 31, count 0 2006.196.07:36:28.54#ibcon#read 5, iclass 31, count 0 2006.196.07:36:28.54#ibcon#about to read 6, iclass 31, count 0 2006.196.07:36:28.54#ibcon#read 6, iclass 31, count 0 2006.196.07:36:28.54#ibcon#end of sib2, iclass 31, count 0 2006.196.07:36:28.54#ibcon#*mode == 0, iclass 31, count 0 2006.196.07:36:28.54#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.196.07:36:28.54#ibcon#[26=FRQ=03,672.99\r\n] 2006.196.07:36:28.54#ibcon#*before write, iclass 31, count 0 2006.196.07:36:28.54#ibcon#enter sib2, iclass 31, count 0 2006.196.07:36:28.54#ibcon#flushed, iclass 31, count 0 2006.196.07:36:28.54#ibcon#about to write, iclass 31, count 0 2006.196.07:36:28.54#ibcon#wrote, iclass 31, count 0 2006.196.07:36:28.54#ibcon#about to read 3, iclass 31, count 0 2006.196.07:36:28.59#ibcon#read 3, iclass 31, count 0 2006.196.07:36:28.59#ibcon#about to read 4, iclass 31, count 0 2006.196.07:36:28.59#ibcon#read 4, iclass 31, count 0 2006.196.07:36:28.59#ibcon#about to read 5, iclass 31, count 0 2006.196.07:36:28.59#ibcon#read 5, iclass 31, count 0 2006.196.07:36:28.59#ibcon#about to read 6, iclass 31, count 0 2006.196.07:36:28.59#ibcon#read 6, iclass 31, count 0 2006.196.07:36:28.59#ibcon#end of sib2, iclass 31, count 0 2006.196.07:36:28.59#ibcon#*after write, iclass 31, count 0 2006.196.07:36:28.59#ibcon#*before return 0, iclass 31, count 0 2006.196.07:36:28.59#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.196.07:36:28.59#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.196.07:36:28.59#ibcon#about to clear, iclass 31 cls_cnt 0 2006.196.07:36:28.59#ibcon#cleared, iclass 31 cls_cnt 0 2006.196.07:36:28.59$vc4f8/va=3,6 2006.196.07:36:28.59#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.196.07:36:28.59#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.196.07:36:28.59#ibcon#ireg 11 cls_cnt 2 2006.196.07:36:28.59#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.196.07:36:28.64#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.196.07:36:28.64#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.196.07:36:28.64#ibcon#enter wrdev, iclass 33, count 2 2006.196.07:36:28.64#ibcon#first serial, iclass 33, count 2 2006.196.07:36:28.64#ibcon#enter sib2, iclass 33, count 2 2006.196.07:36:28.64#ibcon#flushed, iclass 33, count 2 2006.196.07:36:28.64#ibcon#about to write, iclass 33, count 2 2006.196.07:36:28.64#ibcon#wrote, iclass 33, count 2 2006.196.07:36:28.64#ibcon#about to read 3, iclass 33, count 2 2006.196.07:36:28.66#ibcon#read 3, iclass 33, count 2 2006.196.07:36:28.66#ibcon#about to read 4, iclass 33, count 2 2006.196.07:36:28.66#ibcon#read 4, iclass 33, count 2 2006.196.07:36:28.66#ibcon#about to read 5, iclass 33, count 2 2006.196.07:36:28.66#ibcon#read 5, iclass 33, count 2 2006.196.07:36:28.66#ibcon#about to read 6, iclass 33, count 2 2006.196.07:36:28.66#ibcon#read 6, iclass 33, count 2 2006.196.07:36:28.66#ibcon#end of sib2, iclass 33, count 2 2006.196.07:36:28.66#ibcon#*mode == 0, iclass 33, count 2 2006.196.07:36:28.66#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.196.07:36:28.66#ibcon#[25=AT03-06\r\n] 2006.196.07:36:28.66#ibcon#*before write, iclass 33, count 2 2006.196.07:36:28.66#ibcon#enter sib2, iclass 33, count 2 2006.196.07:36:28.66#ibcon#flushed, iclass 33, count 2 2006.196.07:36:28.66#ibcon#about to write, iclass 33, count 2 2006.196.07:36:28.66#ibcon#wrote, iclass 33, count 2 2006.196.07:36:28.66#ibcon#about to read 3, iclass 33, count 2 2006.196.07:36:28.69#ibcon#read 3, iclass 33, count 2 2006.196.07:36:28.69#ibcon#about to read 4, iclass 33, count 2 2006.196.07:36:28.69#ibcon#read 4, iclass 33, count 2 2006.196.07:36:28.69#ibcon#about to read 5, iclass 33, count 2 2006.196.07:36:28.69#ibcon#read 5, iclass 33, count 2 2006.196.07:36:28.69#ibcon#about to read 6, iclass 33, count 2 2006.196.07:36:28.69#ibcon#read 6, iclass 33, count 2 2006.196.07:36:28.69#ibcon#end of sib2, iclass 33, count 2 2006.196.07:36:28.69#ibcon#*after write, iclass 33, count 2 2006.196.07:36:28.69#ibcon#*before return 0, iclass 33, count 2 2006.196.07:36:28.69#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.196.07:36:28.69#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.196.07:36:28.69#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.196.07:36:28.69#ibcon#ireg 7 cls_cnt 0 2006.196.07:36:28.69#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.196.07:36:28.81#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.196.07:36:28.81#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.196.07:36:28.81#ibcon#enter wrdev, iclass 33, count 0 2006.196.07:36:28.81#ibcon#first serial, iclass 33, count 0 2006.196.07:36:28.81#ibcon#enter sib2, iclass 33, count 0 2006.196.07:36:28.81#ibcon#flushed, iclass 33, count 0 2006.196.07:36:28.81#ibcon#about to write, iclass 33, count 0 2006.196.07:36:28.81#ibcon#wrote, iclass 33, count 0 2006.196.07:36:28.81#ibcon#about to read 3, iclass 33, count 0 2006.196.07:36:28.83#ibcon#read 3, iclass 33, count 0 2006.196.07:36:28.83#ibcon#about to read 4, iclass 33, count 0 2006.196.07:36:28.83#ibcon#read 4, iclass 33, count 0 2006.196.07:36:28.83#ibcon#about to read 5, iclass 33, count 0 2006.196.07:36:28.83#ibcon#read 5, iclass 33, count 0 2006.196.07:36:28.83#ibcon#about to read 6, iclass 33, count 0 2006.196.07:36:28.83#ibcon#read 6, iclass 33, count 0 2006.196.07:36:28.83#ibcon#end of sib2, iclass 33, count 0 2006.196.07:36:28.83#ibcon#*mode == 0, iclass 33, count 0 2006.196.07:36:28.83#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.196.07:36:28.83#ibcon#[25=USB\r\n] 2006.196.07:36:28.83#ibcon#*before write, iclass 33, count 0 2006.196.07:36:28.83#ibcon#enter sib2, iclass 33, count 0 2006.196.07:36:28.83#ibcon#flushed, iclass 33, count 0 2006.196.07:36:28.83#ibcon#about to write, iclass 33, count 0 2006.196.07:36:28.83#ibcon#wrote, iclass 33, count 0 2006.196.07:36:28.83#ibcon#about to read 3, iclass 33, count 0 2006.196.07:36:28.86#ibcon#read 3, iclass 33, count 0 2006.196.07:36:28.86#ibcon#about to read 4, iclass 33, count 0 2006.196.07:36:28.86#ibcon#read 4, iclass 33, count 0 2006.196.07:36:28.86#ibcon#about to read 5, iclass 33, count 0 2006.196.07:36:28.86#ibcon#read 5, iclass 33, count 0 2006.196.07:36:28.86#ibcon#about to read 6, iclass 33, count 0 2006.196.07:36:28.86#ibcon#read 6, iclass 33, count 0 2006.196.07:36:28.86#ibcon#end of sib2, iclass 33, count 0 2006.196.07:36:28.86#ibcon#*after write, iclass 33, count 0 2006.196.07:36:28.86#ibcon#*before return 0, iclass 33, count 0 2006.196.07:36:28.86#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.196.07:36:28.86#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.196.07:36:28.86#ibcon#about to clear, iclass 33 cls_cnt 0 2006.196.07:36:28.86#ibcon#cleared, iclass 33 cls_cnt 0 2006.196.07:36:28.86$vc4f8/valo=4,832.99 2006.196.07:36:28.86#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.196.07:36:28.86#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.196.07:36:28.86#ibcon#ireg 17 cls_cnt 0 2006.196.07:36:28.86#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.196.07:36:28.86#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.196.07:36:28.86#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.196.07:36:28.86#ibcon#enter wrdev, iclass 35, count 0 2006.196.07:36:28.86#ibcon#first serial, iclass 35, count 0 2006.196.07:36:28.86#ibcon#enter sib2, iclass 35, count 0 2006.196.07:36:28.86#ibcon#flushed, iclass 35, count 0 2006.196.07:36:28.86#ibcon#about to write, iclass 35, count 0 2006.196.07:36:28.86#ibcon#wrote, iclass 35, count 0 2006.196.07:36:28.86#ibcon#about to read 3, iclass 35, count 0 2006.196.07:36:28.88#ibcon#read 3, iclass 35, count 0 2006.196.07:36:28.88#ibcon#about to read 4, iclass 35, count 0 2006.196.07:36:28.88#ibcon#read 4, iclass 35, count 0 2006.196.07:36:28.88#ibcon#about to read 5, iclass 35, count 0 2006.196.07:36:28.88#ibcon#read 5, iclass 35, count 0 2006.196.07:36:28.88#ibcon#about to read 6, iclass 35, count 0 2006.196.07:36:28.88#ibcon#read 6, iclass 35, count 0 2006.196.07:36:28.88#ibcon#end of sib2, iclass 35, count 0 2006.196.07:36:28.88#ibcon#*mode == 0, iclass 35, count 0 2006.196.07:36:28.88#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.196.07:36:28.88#ibcon#[26=FRQ=04,832.99\r\n] 2006.196.07:36:28.88#ibcon#*before write, iclass 35, count 0 2006.196.07:36:28.88#ibcon#enter sib2, iclass 35, count 0 2006.196.07:36:28.88#ibcon#flushed, iclass 35, count 0 2006.196.07:36:28.88#ibcon#about to write, iclass 35, count 0 2006.196.07:36:28.88#ibcon#wrote, iclass 35, count 0 2006.196.07:36:28.88#ibcon#about to read 3, iclass 35, count 0 2006.196.07:36:28.92#ibcon#read 3, iclass 35, count 0 2006.196.07:36:28.92#ibcon#about to read 4, iclass 35, count 0 2006.196.07:36:28.92#ibcon#read 4, iclass 35, count 0 2006.196.07:36:28.92#ibcon#about to read 5, iclass 35, count 0 2006.196.07:36:28.92#ibcon#read 5, iclass 35, count 0 2006.196.07:36:28.92#ibcon#about to read 6, iclass 35, count 0 2006.196.07:36:28.92#ibcon#read 6, iclass 35, count 0 2006.196.07:36:28.92#ibcon#end of sib2, iclass 35, count 0 2006.196.07:36:28.92#ibcon#*after write, iclass 35, count 0 2006.196.07:36:28.92#ibcon#*before return 0, iclass 35, count 0 2006.196.07:36:28.92#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.196.07:36:28.92#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.196.07:36:28.92#ibcon#about to clear, iclass 35 cls_cnt 0 2006.196.07:36:28.92#ibcon#cleared, iclass 35 cls_cnt 0 2006.196.07:36:28.92$vc4f8/va=4,7 2006.196.07:36:28.92#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.196.07:36:28.92#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.196.07:36:28.92#ibcon#ireg 11 cls_cnt 2 2006.196.07:36:28.92#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.196.07:36:28.98#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.196.07:36:28.98#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.196.07:36:28.98#ibcon#enter wrdev, iclass 37, count 2 2006.196.07:36:28.98#ibcon#first serial, iclass 37, count 2 2006.196.07:36:28.98#ibcon#enter sib2, iclass 37, count 2 2006.196.07:36:28.98#ibcon#flushed, iclass 37, count 2 2006.196.07:36:28.98#ibcon#about to write, iclass 37, count 2 2006.196.07:36:28.98#ibcon#wrote, iclass 37, count 2 2006.196.07:36:28.98#ibcon#about to read 3, iclass 37, count 2 2006.196.07:36:29.00#ibcon#read 3, iclass 37, count 2 2006.196.07:36:29.00#ibcon#about to read 4, iclass 37, count 2 2006.196.07:36:29.00#ibcon#read 4, iclass 37, count 2 2006.196.07:36:29.00#ibcon#about to read 5, iclass 37, count 2 2006.196.07:36:29.00#ibcon#read 5, iclass 37, count 2 2006.196.07:36:29.00#ibcon#about to read 6, iclass 37, count 2 2006.196.07:36:29.00#ibcon#read 6, iclass 37, count 2 2006.196.07:36:29.00#ibcon#end of sib2, iclass 37, count 2 2006.196.07:36:29.00#ibcon#*mode == 0, iclass 37, count 2 2006.196.07:36:29.00#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.196.07:36:29.00#ibcon#[25=AT04-07\r\n] 2006.196.07:36:29.00#ibcon#*before write, iclass 37, count 2 2006.196.07:36:29.00#ibcon#enter sib2, iclass 37, count 2 2006.196.07:36:29.00#ibcon#flushed, iclass 37, count 2 2006.196.07:36:29.00#ibcon#about to write, iclass 37, count 2 2006.196.07:36:29.00#ibcon#wrote, iclass 37, count 2 2006.196.07:36:29.00#ibcon#about to read 3, iclass 37, count 2 2006.196.07:36:29.03#ibcon#read 3, iclass 37, count 2 2006.196.07:36:29.03#ibcon#about to read 4, iclass 37, count 2 2006.196.07:36:29.03#ibcon#read 4, iclass 37, count 2 2006.196.07:36:29.03#ibcon#about to read 5, iclass 37, count 2 2006.196.07:36:29.03#ibcon#read 5, iclass 37, count 2 2006.196.07:36:29.03#ibcon#about to read 6, iclass 37, count 2 2006.196.07:36:29.03#ibcon#read 6, iclass 37, count 2 2006.196.07:36:29.03#ibcon#end of sib2, iclass 37, count 2 2006.196.07:36:29.03#ibcon#*after write, iclass 37, count 2 2006.196.07:36:29.03#ibcon#*before return 0, iclass 37, count 2 2006.196.07:36:29.03#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.196.07:36:29.03#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.196.07:36:29.03#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.196.07:36:29.03#ibcon#ireg 7 cls_cnt 0 2006.196.07:36:29.03#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.196.07:36:29.15#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.196.07:36:29.15#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.196.07:36:29.15#ibcon#enter wrdev, iclass 37, count 0 2006.196.07:36:29.15#ibcon#first serial, iclass 37, count 0 2006.196.07:36:29.15#ibcon#enter sib2, iclass 37, count 0 2006.196.07:36:29.15#ibcon#flushed, iclass 37, count 0 2006.196.07:36:29.15#ibcon#about to write, iclass 37, count 0 2006.196.07:36:29.15#ibcon#wrote, iclass 37, count 0 2006.196.07:36:29.15#ibcon#about to read 3, iclass 37, count 0 2006.196.07:36:29.17#ibcon#read 3, iclass 37, count 0 2006.196.07:36:29.17#ibcon#about to read 4, iclass 37, count 0 2006.196.07:36:29.17#ibcon#read 4, iclass 37, count 0 2006.196.07:36:29.17#ibcon#about to read 5, iclass 37, count 0 2006.196.07:36:29.17#ibcon#read 5, iclass 37, count 0 2006.196.07:36:29.17#ibcon#about to read 6, iclass 37, count 0 2006.196.07:36:29.17#ibcon#read 6, iclass 37, count 0 2006.196.07:36:29.17#ibcon#end of sib2, iclass 37, count 0 2006.196.07:36:29.17#ibcon#*mode == 0, iclass 37, count 0 2006.196.07:36:29.17#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.196.07:36:29.17#ibcon#[25=USB\r\n] 2006.196.07:36:29.17#ibcon#*before write, iclass 37, count 0 2006.196.07:36:29.17#ibcon#enter sib2, iclass 37, count 0 2006.196.07:36:29.17#ibcon#flushed, iclass 37, count 0 2006.196.07:36:29.17#ibcon#about to write, iclass 37, count 0 2006.196.07:36:29.17#ibcon#wrote, iclass 37, count 0 2006.196.07:36:29.17#ibcon#about to read 3, iclass 37, count 0 2006.196.07:36:29.20#ibcon#read 3, iclass 37, count 0 2006.196.07:36:29.20#ibcon#about to read 4, iclass 37, count 0 2006.196.07:36:29.20#ibcon#read 4, iclass 37, count 0 2006.196.07:36:29.20#ibcon#about to read 5, iclass 37, count 0 2006.196.07:36:29.20#ibcon#read 5, iclass 37, count 0 2006.196.07:36:29.20#ibcon#about to read 6, iclass 37, count 0 2006.196.07:36:29.20#ibcon#read 6, iclass 37, count 0 2006.196.07:36:29.20#ibcon#end of sib2, iclass 37, count 0 2006.196.07:36:29.20#ibcon#*after write, iclass 37, count 0 2006.196.07:36:29.20#ibcon#*before return 0, iclass 37, count 0 2006.196.07:36:29.20#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.196.07:36:29.20#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.196.07:36:29.20#ibcon#about to clear, iclass 37 cls_cnt 0 2006.196.07:36:29.20#ibcon#cleared, iclass 37 cls_cnt 0 2006.196.07:36:29.20$vc4f8/valo=5,652.99 2006.196.07:36:29.20#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.196.07:36:29.20#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.196.07:36:29.20#ibcon#ireg 17 cls_cnt 0 2006.196.07:36:29.20#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.196.07:36:29.20#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.196.07:36:29.20#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.196.07:36:29.20#ibcon#enter wrdev, iclass 39, count 0 2006.196.07:36:29.20#ibcon#first serial, iclass 39, count 0 2006.196.07:36:29.20#ibcon#enter sib2, iclass 39, count 0 2006.196.07:36:29.20#ibcon#flushed, iclass 39, count 0 2006.196.07:36:29.20#ibcon#about to write, iclass 39, count 0 2006.196.07:36:29.20#ibcon#wrote, iclass 39, count 0 2006.196.07:36:29.20#ibcon#about to read 3, iclass 39, count 0 2006.196.07:36:29.22#ibcon#read 3, iclass 39, count 0 2006.196.07:36:29.22#ibcon#about to read 4, iclass 39, count 0 2006.196.07:36:29.22#ibcon#read 4, iclass 39, count 0 2006.196.07:36:29.22#ibcon#about to read 5, iclass 39, count 0 2006.196.07:36:29.22#ibcon#read 5, iclass 39, count 0 2006.196.07:36:29.22#ibcon#about to read 6, iclass 39, count 0 2006.196.07:36:29.22#ibcon#read 6, iclass 39, count 0 2006.196.07:36:29.22#ibcon#end of sib2, iclass 39, count 0 2006.196.07:36:29.22#ibcon#*mode == 0, iclass 39, count 0 2006.196.07:36:29.22#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.196.07:36:29.22#ibcon#[26=FRQ=05,652.99\r\n] 2006.196.07:36:29.22#ibcon#*before write, iclass 39, count 0 2006.196.07:36:29.22#ibcon#enter sib2, iclass 39, count 0 2006.196.07:36:29.22#ibcon#flushed, iclass 39, count 0 2006.196.07:36:29.22#ibcon#about to write, iclass 39, count 0 2006.196.07:36:29.22#ibcon#wrote, iclass 39, count 0 2006.196.07:36:29.22#ibcon#about to read 3, iclass 39, count 0 2006.196.07:36:29.26#ibcon#read 3, iclass 39, count 0 2006.196.07:36:29.26#ibcon#about to read 4, iclass 39, count 0 2006.196.07:36:29.26#ibcon#read 4, iclass 39, count 0 2006.196.07:36:29.26#ibcon#about to read 5, iclass 39, count 0 2006.196.07:36:29.26#ibcon#read 5, iclass 39, count 0 2006.196.07:36:29.26#ibcon#about to read 6, iclass 39, count 0 2006.196.07:36:29.26#ibcon#read 6, iclass 39, count 0 2006.196.07:36:29.26#ibcon#end of sib2, iclass 39, count 0 2006.196.07:36:29.26#ibcon#*after write, iclass 39, count 0 2006.196.07:36:29.26#ibcon#*before return 0, iclass 39, count 0 2006.196.07:36:29.26#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.196.07:36:29.26#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.196.07:36:29.26#ibcon#about to clear, iclass 39 cls_cnt 0 2006.196.07:36:29.26#ibcon#cleared, iclass 39 cls_cnt 0 2006.196.07:36:29.26$vc4f8/va=5,7 2006.196.07:36:29.26#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.196.07:36:29.26#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.196.07:36:29.26#ibcon#ireg 11 cls_cnt 2 2006.196.07:36:29.26#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.196.07:36:29.32#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.196.07:36:29.32#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.196.07:36:29.32#ibcon#enter wrdev, iclass 3, count 2 2006.196.07:36:29.32#ibcon#first serial, iclass 3, count 2 2006.196.07:36:29.32#ibcon#enter sib2, iclass 3, count 2 2006.196.07:36:29.32#ibcon#flushed, iclass 3, count 2 2006.196.07:36:29.32#ibcon#about to write, iclass 3, count 2 2006.196.07:36:29.32#ibcon#wrote, iclass 3, count 2 2006.196.07:36:29.32#ibcon#about to read 3, iclass 3, count 2 2006.196.07:36:29.34#ibcon#read 3, iclass 3, count 2 2006.196.07:36:29.34#ibcon#about to read 4, iclass 3, count 2 2006.196.07:36:29.34#ibcon#read 4, iclass 3, count 2 2006.196.07:36:29.34#ibcon#about to read 5, iclass 3, count 2 2006.196.07:36:29.34#ibcon#read 5, iclass 3, count 2 2006.196.07:36:29.34#ibcon#about to read 6, iclass 3, count 2 2006.196.07:36:29.34#ibcon#read 6, iclass 3, count 2 2006.196.07:36:29.34#ibcon#end of sib2, iclass 3, count 2 2006.196.07:36:29.34#ibcon#*mode == 0, iclass 3, count 2 2006.196.07:36:29.34#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.196.07:36:29.34#ibcon#[25=AT05-07\r\n] 2006.196.07:36:29.34#ibcon#*before write, iclass 3, count 2 2006.196.07:36:29.34#ibcon#enter sib2, iclass 3, count 2 2006.196.07:36:29.34#ibcon#flushed, iclass 3, count 2 2006.196.07:36:29.34#ibcon#about to write, iclass 3, count 2 2006.196.07:36:29.34#ibcon#wrote, iclass 3, count 2 2006.196.07:36:29.34#ibcon#about to read 3, iclass 3, count 2 2006.196.07:36:29.37#ibcon#read 3, iclass 3, count 2 2006.196.07:36:29.37#ibcon#about to read 4, iclass 3, count 2 2006.196.07:36:29.37#ibcon#read 4, iclass 3, count 2 2006.196.07:36:29.37#ibcon#about to read 5, iclass 3, count 2 2006.196.07:36:29.37#ibcon#read 5, iclass 3, count 2 2006.196.07:36:29.37#ibcon#about to read 6, iclass 3, count 2 2006.196.07:36:29.37#ibcon#read 6, iclass 3, count 2 2006.196.07:36:29.37#ibcon#end of sib2, iclass 3, count 2 2006.196.07:36:29.37#ibcon#*after write, iclass 3, count 2 2006.196.07:36:29.37#ibcon#*before return 0, iclass 3, count 2 2006.196.07:36:29.37#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.196.07:36:29.37#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.196.07:36:29.37#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.196.07:36:29.37#ibcon#ireg 7 cls_cnt 0 2006.196.07:36:29.37#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.196.07:36:29.49#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.196.07:36:29.49#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.196.07:36:29.49#ibcon#enter wrdev, iclass 3, count 0 2006.196.07:36:29.49#ibcon#first serial, iclass 3, count 0 2006.196.07:36:29.49#ibcon#enter sib2, iclass 3, count 0 2006.196.07:36:29.49#ibcon#flushed, iclass 3, count 0 2006.196.07:36:29.49#ibcon#about to write, iclass 3, count 0 2006.196.07:36:29.49#ibcon#wrote, iclass 3, count 0 2006.196.07:36:29.49#ibcon#about to read 3, iclass 3, count 0 2006.196.07:36:29.51#ibcon#read 3, iclass 3, count 0 2006.196.07:36:29.51#ibcon#about to read 4, iclass 3, count 0 2006.196.07:36:29.51#ibcon#read 4, iclass 3, count 0 2006.196.07:36:29.51#ibcon#about to read 5, iclass 3, count 0 2006.196.07:36:29.51#ibcon#read 5, iclass 3, count 0 2006.196.07:36:29.51#ibcon#about to read 6, iclass 3, count 0 2006.196.07:36:29.51#ibcon#read 6, iclass 3, count 0 2006.196.07:36:29.51#ibcon#end of sib2, iclass 3, count 0 2006.196.07:36:29.51#ibcon#*mode == 0, iclass 3, count 0 2006.196.07:36:29.51#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.196.07:36:29.51#ibcon#[25=USB\r\n] 2006.196.07:36:29.51#ibcon#*before write, iclass 3, count 0 2006.196.07:36:29.51#ibcon#enter sib2, iclass 3, count 0 2006.196.07:36:29.51#ibcon#flushed, iclass 3, count 0 2006.196.07:36:29.51#ibcon#about to write, iclass 3, count 0 2006.196.07:36:29.51#ibcon#wrote, iclass 3, count 0 2006.196.07:36:29.51#ibcon#about to read 3, iclass 3, count 0 2006.196.07:36:29.54#ibcon#read 3, iclass 3, count 0 2006.196.07:36:29.54#ibcon#about to read 4, iclass 3, count 0 2006.196.07:36:29.54#ibcon#read 4, iclass 3, count 0 2006.196.07:36:29.54#ibcon#about to read 5, iclass 3, count 0 2006.196.07:36:29.54#ibcon#read 5, iclass 3, count 0 2006.196.07:36:29.54#ibcon#about to read 6, iclass 3, count 0 2006.196.07:36:29.54#ibcon#read 6, iclass 3, count 0 2006.196.07:36:29.54#ibcon#end of sib2, iclass 3, count 0 2006.196.07:36:29.54#ibcon#*after write, iclass 3, count 0 2006.196.07:36:29.54#ibcon#*before return 0, iclass 3, count 0 2006.196.07:36:29.54#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.196.07:36:29.54#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.196.07:36:29.54#ibcon#about to clear, iclass 3 cls_cnt 0 2006.196.07:36:29.54#ibcon#cleared, iclass 3 cls_cnt 0 2006.196.07:36:29.54$vc4f8/valo=6,772.99 2006.196.07:36:29.54#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.196.07:36:29.54#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.196.07:36:29.54#ibcon#ireg 17 cls_cnt 0 2006.196.07:36:29.54#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.196.07:36:29.54#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.196.07:36:29.54#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.196.07:36:29.54#ibcon#enter wrdev, iclass 5, count 0 2006.196.07:36:29.54#ibcon#first serial, iclass 5, count 0 2006.196.07:36:29.54#ibcon#enter sib2, iclass 5, count 0 2006.196.07:36:29.54#ibcon#flushed, iclass 5, count 0 2006.196.07:36:29.54#ibcon#about to write, iclass 5, count 0 2006.196.07:36:29.54#ibcon#wrote, iclass 5, count 0 2006.196.07:36:29.54#ibcon#about to read 3, iclass 5, count 0 2006.196.07:36:29.56#ibcon#read 3, iclass 5, count 0 2006.196.07:36:29.56#ibcon#about to read 4, iclass 5, count 0 2006.196.07:36:29.56#ibcon#read 4, iclass 5, count 0 2006.196.07:36:29.56#ibcon#about to read 5, iclass 5, count 0 2006.196.07:36:29.56#ibcon#read 5, iclass 5, count 0 2006.196.07:36:29.56#ibcon#about to read 6, iclass 5, count 0 2006.196.07:36:29.56#ibcon#read 6, iclass 5, count 0 2006.196.07:36:29.56#ibcon#end of sib2, iclass 5, count 0 2006.196.07:36:29.56#ibcon#*mode == 0, iclass 5, count 0 2006.196.07:36:29.56#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.196.07:36:29.56#ibcon#[26=FRQ=06,772.99\r\n] 2006.196.07:36:29.56#ibcon#*before write, iclass 5, count 0 2006.196.07:36:29.56#ibcon#enter sib2, iclass 5, count 0 2006.196.07:36:29.56#ibcon#flushed, iclass 5, count 0 2006.196.07:36:29.56#ibcon#about to write, iclass 5, count 0 2006.196.07:36:29.56#ibcon#wrote, iclass 5, count 0 2006.196.07:36:29.56#ibcon#about to read 3, iclass 5, count 0 2006.196.07:36:29.60#ibcon#read 3, iclass 5, count 0 2006.196.07:36:29.60#ibcon#about to read 4, iclass 5, count 0 2006.196.07:36:29.60#ibcon#read 4, iclass 5, count 0 2006.196.07:36:29.60#ibcon#about to read 5, iclass 5, count 0 2006.196.07:36:29.60#ibcon#read 5, iclass 5, count 0 2006.196.07:36:29.60#ibcon#about to read 6, iclass 5, count 0 2006.196.07:36:29.60#ibcon#read 6, iclass 5, count 0 2006.196.07:36:29.60#ibcon#end of sib2, iclass 5, count 0 2006.196.07:36:29.60#ibcon#*after write, iclass 5, count 0 2006.196.07:36:29.60#ibcon#*before return 0, iclass 5, count 0 2006.196.07:36:29.60#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.196.07:36:29.60#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.196.07:36:29.60#ibcon#about to clear, iclass 5 cls_cnt 0 2006.196.07:36:29.60#ibcon#cleared, iclass 5 cls_cnt 0 2006.196.07:36:29.60$vc4f8/va=6,6 2006.196.07:36:29.60#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.196.07:36:29.60#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.196.07:36:29.60#ibcon#ireg 11 cls_cnt 2 2006.196.07:36:29.60#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.196.07:36:29.66#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.196.07:36:29.66#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.196.07:36:29.66#ibcon#enter wrdev, iclass 7, count 2 2006.196.07:36:29.66#ibcon#first serial, iclass 7, count 2 2006.196.07:36:29.66#ibcon#enter sib2, iclass 7, count 2 2006.196.07:36:29.66#ibcon#flushed, iclass 7, count 2 2006.196.07:36:29.66#ibcon#about to write, iclass 7, count 2 2006.196.07:36:29.66#ibcon#wrote, iclass 7, count 2 2006.196.07:36:29.66#ibcon#about to read 3, iclass 7, count 2 2006.196.07:36:29.68#ibcon#read 3, iclass 7, count 2 2006.196.07:36:29.68#ibcon#about to read 4, iclass 7, count 2 2006.196.07:36:29.68#ibcon#read 4, iclass 7, count 2 2006.196.07:36:29.68#ibcon#about to read 5, iclass 7, count 2 2006.196.07:36:29.68#ibcon#read 5, iclass 7, count 2 2006.196.07:36:29.68#ibcon#about to read 6, iclass 7, count 2 2006.196.07:36:29.68#ibcon#read 6, iclass 7, count 2 2006.196.07:36:29.68#ibcon#end of sib2, iclass 7, count 2 2006.196.07:36:29.68#ibcon#*mode == 0, iclass 7, count 2 2006.196.07:36:29.68#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.196.07:36:29.68#ibcon#[25=AT06-06\r\n] 2006.196.07:36:29.68#ibcon#*before write, iclass 7, count 2 2006.196.07:36:29.68#ibcon#enter sib2, iclass 7, count 2 2006.196.07:36:29.68#ibcon#flushed, iclass 7, count 2 2006.196.07:36:29.68#ibcon#about to write, iclass 7, count 2 2006.196.07:36:29.68#ibcon#wrote, iclass 7, count 2 2006.196.07:36:29.68#ibcon#about to read 3, iclass 7, count 2 2006.196.07:36:29.71#ibcon#read 3, iclass 7, count 2 2006.196.07:36:29.71#ibcon#about to read 4, iclass 7, count 2 2006.196.07:36:29.71#ibcon#read 4, iclass 7, count 2 2006.196.07:36:29.71#ibcon#about to read 5, iclass 7, count 2 2006.196.07:36:29.71#ibcon#read 5, iclass 7, count 2 2006.196.07:36:29.71#ibcon#about to read 6, iclass 7, count 2 2006.196.07:36:29.71#ibcon#read 6, iclass 7, count 2 2006.196.07:36:29.71#ibcon#end of sib2, iclass 7, count 2 2006.196.07:36:29.71#ibcon#*after write, iclass 7, count 2 2006.196.07:36:29.71#ibcon#*before return 0, iclass 7, count 2 2006.196.07:36:29.71#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.196.07:36:29.71#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.196.07:36:29.71#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.196.07:36:29.71#ibcon#ireg 7 cls_cnt 0 2006.196.07:36:29.71#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.196.07:36:29.83#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.196.07:36:29.83#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.196.07:36:29.83#ibcon#enter wrdev, iclass 7, count 0 2006.196.07:36:29.83#ibcon#first serial, iclass 7, count 0 2006.196.07:36:29.83#ibcon#enter sib2, iclass 7, count 0 2006.196.07:36:29.83#ibcon#flushed, iclass 7, count 0 2006.196.07:36:29.83#ibcon#about to write, iclass 7, count 0 2006.196.07:36:29.83#ibcon#wrote, iclass 7, count 0 2006.196.07:36:29.83#ibcon#about to read 3, iclass 7, count 0 2006.196.07:36:29.85#ibcon#read 3, iclass 7, count 0 2006.196.07:36:29.85#ibcon#about to read 4, iclass 7, count 0 2006.196.07:36:29.85#ibcon#read 4, iclass 7, count 0 2006.196.07:36:29.85#ibcon#about to read 5, iclass 7, count 0 2006.196.07:36:29.85#ibcon#read 5, iclass 7, count 0 2006.196.07:36:29.85#ibcon#about to read 6, iclass 7, count 0 2006.196.07:36:29.85#ibcon#read 6, iclass 7, count 0 2006.196.07:36:29.85#ibcon#end of sib2, iclass 7, count 0 2006.196.07:36:29.85#ibcon#*mode == 0, iclass 7, count 0 2006.196.07:36:29.85#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.196.07:36:29.85#ibcon#[25=USB\r\n] 2006.196.07:36:29.85#ibcon#*before write, iclass 7, count 0 2006.196.07:36:29.85#ibcon#enter sib2, iclass 7, count 0 2006.196.07:36:29.85#ibcon#flushed, iclass 7, count 0 2006.196.07:36:29.85#ibcon#about to write, iclass 7, count 0 2006.196.07:36:29.85#ibcon#wrote, iclass 7, count 0 2006.196.07:36:29.85#ibcon#about to read 3, iclass 7, count 0 2006.196.07:36:29.88#ibcon#read 3, iclass 7, count 0 2006.196.07:36:29.88#ibcon#about to read 4, iclass 7, count 0 2006.196.07:36:29.88#ibcon#read 4, iclass 7, count 0 2006.196.07:36:29.88#ibcon#about to read 5, iclass 7, count 0 2006.196.07:36:29.88#ibcon#read 5, iclass 7, count 0 2006.196.07:36:29.88#ibcon#about to read 6, iclass 7, count 0 2006.196.07:36:29.88#ibcon#read 6, iclass 7, count 0 2006.196.07:36:29.88#ibcon#end of sib2, iclass 7, count 0 2006.196.07:36:29.88#ibcon#*after write, iclass 7, count 0 2006.196.07:36:29.88#ibcon#*before return 0, iclass 7, count 0 2006.196.07:36:29.88#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.196.07:36:29.88#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.196.07:36:29.88#ibcon#about to clear, iclass 7 cls_cnt 0 2006.196.07:36:29.88#ibcon#cleared, iclass 7 cls_cnt 0 2006.196.07:36:29.88$vc4f8/valo=7,832.99 2006.196.07:36:29.88#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.196.07:36:29.88#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.196.07:36:29.88#ibcon#ireg 17 cls_cnt 0 2006.196.07:36:29.88#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.196.07:36:29.88#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.196.07:36:29.88#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.196.07:36:29.88#ibcon#enter wrdev, iclass 11, count 0 2006.196.07:36:29.88#ibcon#first serial, iclass 11, count 0 2006.196.07:36:29.88#ibcon#enter sib2, iclass 11, count 0 2006.196.07:36:29.88#ibcon#flushed, iclass 11, count 0 2006.196.07:36:29.88#ibcon#about to write, iclass 11, count 0 2006.196.07:36:29.88#ibcon#wrote, iclass 11, count 0 2006.196.07:36:29.88#ibcon#about to read 3, iclass 11, count 0 2006.196.07:36:29.90#ibcon#read 3, iclass 11, count 0 2006.196.07:36:29.90#ibcon#about to read 4, iclass 11, count 0 2006.196.07:36:29.90#ibcon#read 4, iclass 11, count 0 2006.196.07:36:29.90#ibcon#about to read 5, iclass 11, count 0 2006.196.07:36:29.90#ibcon#read 5, iclass 11, count 0 2006.196.07:36:29.90#ibcon#about to read 6, iclass 11, count 0 2006.196.07:36:29.90#ibcon#read 6, iclass 11, count 0 2006.196.07:36:29.90#ibcon#end of sib2, iclass 11, count 0 2006.196.07:36:29.90#ibcon#*mode == 0, iclass 11, count 0 2006.196.07:36:29.90#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.196.07:36:29.90#ibcon#[26=FRQ=07,832.99\r\n] 2006.196.07:36:29.90#ibcon#*before write, iclass 11, count 0 2006.196.07:36:29.90#ibcon#enter sib2, iclass 11, count 0 2006.196.07:36:29.90#ibcon#flushed, iclass 11, count 0 2006.196.07:36:29.90#ibcon#about to write, iclass 11, count 0 2006.196.07:36:29.90#ibcon#wrote, iclass 11, count 0 2006.196.07:36:29.90#ibcon#about to read 3, iclass 11, count 0 2006.196.07:36:29.94#ibcon#read 3, iclass 11, count 0 2006.196.07:36:29.94#ibcon#about to read 4, iclass 11, count 0 2006.196.07:36:29.94#ibcon#read 4, iclass 11, count 0 2006.196.07:36:29.94#ibcon#about to read 5, iclass 11, count 0 2006.196.07:36:29.94#ibcon#read 5, iclass 11, count 0 2006.196.07:36:29.94#ibcon#about to read 6, iclass 11, count 0 2006.196.07:36:29.94#ibcon#read 6, iclass 11, count 0 2006.196.07:36:29.94#ibcon#end of sib2, iclass 11, count 0 2006.196.07:36:29.94#ibcon#*after write, iclass 11, count 0 2006.196.07:36:29.94#ibcon#*before return 0, iclass 11, count 0 2006.196.07:36:29.94#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.196.07:36:29.94#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.196.07:36:29.94#ibcon#about to clear, iclass 11 cls_cnt 0 2006.196.07:36:29.94#ibcon#cleared, iclass 11 cls_cnt 0 2006.196.07:36:29.94$vc4f8/va=7,6 2006.196.07:36:29.94#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.196.07:36:29.94#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.196.07:36:29.94#ibcon#ireg 11 cls_cnt 2 2006.196.07:36:29.94#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.196.07:36:30.00#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.196.07:36:30.00#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.196.07:36:30.00#ibcon#enter wrdev, iclass 13, count 2 2006.196.07:36:30.00#ibcon#first serial, iclass 13, count 2 2006.196.07:36:30.00#ibcon#enter sib2, iclass 13, count 2 2006.196.07:36:30.00#ibcon#flushed, iclass 13, count 2 2006.196.07:36:30.00#ibcon#about to write, iclass 13, count 2 2006.196.07:36:30.00#ibcon#wrote, iclass 13, count 2 2006.196.07:36:30.00#ibcon#about to read 3, iclass 13, count 2 2006.196.07:36:30.02#ibcon#read 3, iclass 13, count 2 2006.196.07:36:30.02#ibcon#about to read 4, iclass 13, count 2 2006.196.07:36:30.02#ibcon#read 4, iclass 13, count 2 2006.196.07:36:30.02#ibcon#about to read 5, iclass 13, count 2 2006.196.07:36:30.02#ibcon#read 5, iclass 13, count 2 2006.196.07:36:30.02#ibcon#about to read 6, iclass 13, count 2 2006.196.07:36:30.02#ibcon#read 6, iclass 13, count 2 2006.196.07:36:30.02#ibcon#end of sib2, iclass 13, count 2 2006.196.07:36:30.02#ibcon#*mode == 0, iclass 13, count 2 2006.196.07:36:30.02#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.196.07:36:30.02#ibcon#[25=AT07-06\r\n] 2006.196.07:36:30.02#ibcon#*before write, iclass 13, count 2 2006.196.07:36:30.02#ibcon#enter sib2, iclass 13, count 2 2006.196.07:36:30.02#ibcon#flushed, iclass 13, count 2 2006.196.07:36:30.02#ibcon#about to write, iclass 13, count 2 2006.196.07:36:30.02#ibcon#wrote, iclass 13, count 2 2006.196.07:36:30.02#ibcon#about to read 3, iclass 13, count 2 2006.196.07:36:30.05#ibcon#read 3, iclass 13, count 2 2006.196.07:36:30.05#ibcon#about to read 4, iclass 13, count 2 2006.196.07:36:30.05#ibcon#read 4, iclass 13, count 2 2006.196.07:36:30.05#ibcon#about to read 5, iclass 13, count 2 2006.196.07:36:30.05#ibcon#read 5, iclass 13, count 2 2006.196.07:36:30.05#ibcon#about to read 6, iclass 13, count 2 2006.196.07:36:30.05#ibcon#read 6, iclass 13, count 2 2006.196.07:36:30.05#ibcon#end of sib2, iclass 13, count 2 2006.196.07:36:30.05#ibcon#*after write, iclass 13, count 2 2006.196.07:36:30.05#ibcon#*before return 0, iclass 13, count 2 2006.196.07:36:30.05#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.196.07:36:30.05#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.196.07:36:30.05#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.196.07:36:30.05#ibcon#ireg 7 cls_cnt 0 2006.196.07:36:30.05#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.196.07:36:30.17#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.196.07:36:30.17#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.196.07:36:30.17#ibcon#enter wrdev, iclass 13, count 0 2006.196.07:36:30.17#ibcon#first serial, iclass 13, count 0 2006.196.07:36:30.17#ibcon#enter sib2, iclass 13, count 0 2006.196.07:36:30.17#ibcon#flushed, iclass 13, count 0 2006.196.07:36:30.17#ibcon#about to write, iclass 13, count 0 2006.196.07:36:30.17#ibcon#wrote, iclass 13, count 0 2006.196.07:36:30.17#ibcon#about to read 3, iclass 13, count 0 2006.196.07:36:30.19#ibcon#read 3, iclass 13, count 0 2006.196.07:36:30.19#ibcon#about to read 4, iclass 13, count 0 2006.196.07:36:30.19#ibcon#read 4, iclass 13, count 0 2006.196.07:36:30.19#ibcon#about to read 5, iclass 13, count 0 2006.196.07:36:30.19#ibcon#read 5, iclass 13, count 0 2006.196.07:36:30.19#ibcon#about to read 6, iclass 13, count 0 2006.196.07:36:30.19#ibcon#read 6, iclass 13, count 0 2006.196.07:36:30.19#ibcon#end of sib2, iclass 13, count 0 2006.196.07:36:30.19#ibcon#*mode == 0, iclass 13, count 0 2006.196.07:36:30.19#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.196.07:36:30.19#ibcon#[25=USB\r\n] 2006.196.07:36:30.19#ibcon#*before write, iclass 13, count 0 2006.196.07:36:30.19#ibcon#enter sib2, iclass 13, count 0 2006.196.07:36:30.19#ibcon#flushed, iclass 13, count 0 2006.196.07:36:30.19#ibcon#about to write, iclass 13, count 0 2006.196.07:36:30.19#ibcon#wrote, iclass 13, count 0 2006.196.07:36:30.19#ibcon#about to read 3, iclass 13, count 0 2006.196.07:36:30.22#ibcon#read 3, iclass 13, count 0 2006.196.07:36:30.22#ibcon#about to read 4, iclass 13, count 0 2006.196.07:36:30.22#ibcon#read 4, iclass 13, count 0 2006.196.07:36:30.22#ibcon#about to read 5, iclass 13, count 0 2006.196.07:36:30.22#ibcon#read 5, iclass 13, count 0 2006.196.07:36:30.22#ibcon#about to read 6, iclass 13, count 0 2006.196.07:36:30.22#ibcon#read 6, iclass 13, count 0 2006.196.07:36:30.22#ibcon#end of sib2, iclass 13, count 0 2006.196.07:36:30.22#ibcon#*after write, iclass 13, count 0 2006.196.07:36:30.22#ibcon#*before return 0, iclass 13, count 0 2006.196.07:36:30.22#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.196.07:36:30.22#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.196.07:36:30.22#ibcon#about to clear, iclass 13 cls_cnt 0 2006.196.07:36:30.22#ibcon#cleared, iclass 13 cls_cnt 0 2006.196.07:36:30.22$vc4f8/valo=8,852.99 2006.196.07:36:30.22#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.196.07:36:30.22#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.196.07:36:30.22#ibcon#ireg 17 cls_cnt 0 2006.196.07:36:30.22#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.196.07:36:30.22#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.196.07:36:30.22#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.196.07:36:30.22#ibcon#enter wrdev, iclass 15, count 0 2006.196.07:36:30.22#ibcon#first serial, iclass 15, count 0 2006.196.07:36:30.22#ibcon#enter sib2, iclass 15, count 0 2006.196.07:36:30.22#ibcon#flushed, iclass 15, count 0 2006.196.07:36:30.22#ibcon#about to write, iclass 15, count 0 2006.196.07:36:30.22#ibcon#wrote, iclass 15, count 0 2006.196.07:36:30.22#ibcon#about to read 3, iclass 15, count 0 2006.196.07:36:30.24#ibcon#read 3, iclass 15, count 0 2006.196.07:36:30.24#ibcon#about to read 4, iclass 15, count 0 2006.196.07:36:30.24#ibcon#read 4, iclass 15, count 0 2006.196.07:36:30.24#ibcon#about to read 5, iclass 15, count 0 2006.196.07:36:30.24#ibcon#read 5, iclass 15, count 0 2006.196.07:36:30.24#ibcon#about to read 6, iclass 15, count 0 2006.196.07:36:30.24#ibcon#read 6, iclass 15, count 0 2006.196.07:36:30.24#ibcon#end of sib2, iclass 15, count 0 2006.196.07:36:30.24#ibcon#*mode == 0, iclass 15, count 0 2006.196.07:36:30.24#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.196.07:36:30.24#ibcon#[26=FRQ=08,852.99\r\n] 2006.196.07:36:30.24#ibcon#*before write, iclass 15, count 0 2006.196.07:36:30.24#ibcon#enter sib2, iclass 15, count 0 2006.196.07:36:30.24#ibcon#flushed, iclass 15, count 0 2006.196.07:36:30.24#ibcon#about to write, iclass 15, count 0 2006.196.07:36:30.24#ibcon#wrote, iclass 15, count 0 2006.196.07:36:30.24#ibcon#about to read 3, iclass 15, count 0 2006.196.07:36:30.28#ibcon#read 3, iclass 15, count 0 2006.196.07:36:30.28#ibcon#about to read 4, iclass 15, count 0 2006.196.07:36:30.28#ibcon#read 4, iclass 15, count 0 2006.196.07:36:30.28#ibcon#about to read 5, iclass 15, count 0 2006.196.07:36:30.28#ibcon#read 5, iclass 15, count 0 2006.196.07:36:30.28#ibcon#about to read 6, iclass 15, count 0 2006.196.07:36:30.28#ibcon#read 6, iclass 15, count 0 2006.196.07:36:30.28#ibcon#end of sib2, iclass 15, count 0 2006.196.07:36:30.28#ibcon#*after write, iclass 15, count 0 2006.196.07:36:30.28#ibcon#*before return 0, iclass 15, count 0 2006.196.07:36:30.28#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.196.07:36:30.28#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.196.07:36:30.28#ibcon#about to clear, iclass 15 cls_cnt 0 2006.196.07:36:30.28#ibcon#cleared, iclass 15 cls_cnt 0 2006.196.07:36:30.28$vc4f8/va=8,7 2006.196.07:36:30.28#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.196.07:36:30.28#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.196.07:36:30.28#ibcon#ireg 11 cls_cnt 2 2006.196.07:36:30.28#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.196.07:36:30.34#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.196.07:36:30.34#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.196.07:36:30.34#ibcon#enter wrdev, iclass 17, count 2 2006.196.07:36:30.34#ibcon#first serial, iclass 17, count 2 2006.196.07:36:30.34#ibcon#enter sib2, iclass 17, count 2 2006.196.07:36:30.34#ibcon#flushed, iclass 17, count 2 2006.196.07:36:30.34#ibcon#about to write, iclass 17, count 2 2006.196.07:36:30.34#ibcon#wrote, iclass 17, count 2 2006.196.07:36:30.34#ibcon#about to read 3, iclass 17, count 2 2006.196.07:36:30.36#ibcon#read 3, iclass 17, count 2 2006.196.07:36:30.36#ibcon#about to read 4, iclass 17, count 2 2006.196.07:36:30.36#ibcon#read 4, iclass 17, count 2 2006.196.07:36:30.36#ibcon#about to read 5, iclass 17, count 2 2006.196.07:36:30.36#ibcon#read 5, iclass 17, count 2 2006.196.07:36:30.36#ibcon#about to read 6, iclass 17, count 2 2006.196.07:36:30.36#ibcon#read 6, iclass 17, count 2 2006.196.07:36:30.36#ibcon#end of sib2, iclass 17, count 2 2006.196.07:36:30.36#ibcon#*mode == 0, iclass 17, count 2 2006.196.07:36:30.36#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.196.07:36:30.36#ibcon#[25=AT08-07\r\n] 2006.196.07:36:30.36#ibcon#*before write, iclass 17, count 2 2006.196.07:36:30.36#ibcon#enter sib2, iclass 17, count 2 2006.196.07:36:30.36#ibcon#flushed, iclass 17, count 2 2006.196.07:36:30.36#ibcon#about to write, iclass 17, count 2 2006.196.07:36:30.36#ibcon#wrote, iclass 17, count 2 2006.196.07:36:30.36#ibcon#about to read 3, iclass 17, count 2 2006.196.07:36:30.39#ibcon#read 3, iclass 17, count 2 2006.196.07:36:30.39#ibcon#about to read 4, iclass 17, count 2 2006.196.07:36:30.39#ibcon#read 4, iclass 17, count 2 2006.196.07:36:30.39#ibcon#about to read 5, iclass 17, count 2 2006.196.07:36:30.39#ibcon#read 5, iclass 17, count 2 2006.196.07:36:30.39#ibcon#about to read 6, iclass 17, count 2 2006.196.07:36:30.39#ibcon#read 6, iclass 17, count 2 2006.196.07:36:30.39#ibcon#end of sib2, iclass 17, count 2 2006.196.07:36:30.39#ibcon#*after write, iclass 17, count 2 2006.196.07:36:30.39#ibcon#*before return 0, iclass 17, count 2 2006.196.07:36:30.39#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.196.07:36:30.39#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.196.07:36:30.39#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.196.07:36:30.39#ibcon#ireg 7 cls_cnt 0 2006.196.07:36:30.39#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.196.07:36:30.51#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.196.07:36:30.51#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.196.07:36:30.51#ibcon#enter wrdev, iclass 17, count 0 2006.196.07:36:30.51#ibcon#first serial, iclass 17, count 0 2006.196.07:36:30.51#ibcon#enter sib2, iclass 17, count 0 2006.196.07:36:30.51#ibcon#flushed, iclass 17, count 0 2006.196.07:36:30.51#ibcon#about to write, iclass 17, count 0 2006.196.07:36:30.51#ibcon#wrote, iclass 17, count 0 2006.196.07:36:30.51#ibcon#about to read 3, iclass 17, count 0 2006.196.07:36:30.53#ibcon#read 3, iclass 17, count 0 2006.196.07:36:30.53#ibcon#about to read 4, iclass 17, count 0 2006.196.07:36:30.53#ibcon#read 4, iclass 17, count 0 2006.196.07:36:30.53#ibcon#about to read 5, iclass 17, count 0 2006.196.07:36:30.53#ibcon#read 5, iclass 17, count 0 2006.196.07:36:30.53#ibcon#about to read 6, iclass 17, count 0 2006.196.07:36:30.53#ibcon#read 6, iclass 17, count 0 2006.196.07:36:30.53#ibcon#end of sib2, iclass 17, count 0 2006.196.07:36:30.53#ibcon#*mode == 0, iclass 17, count 0 2006.196.07:36:30.53#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.196.07:36:30.53#ibcon#[25=USB\r\n] 2006.196.07:36:30.53#ibcon#*before write, iclass 17, count 0 2006.196.07:36:30.53#ibcon#enter sib2, iclass 17, count 0 2006.196.07:36:30.53#ibcon#flushed, iclass 17, count 0 2006.196.07:36:30.53#ibcon#about to write, iclass 17, count 0 2006.196.07:36:30.53#ibcon#wrote, iclass 17, count 0 2006.196.07:36:30.53#ibcon#about to read 3, iclass 17, count 0 2006.196.07:36:30.56#ibcon#read 3, iclass 17, count 0 2006.196.07:36:30.56#ibcon#about to read 4, iclass 17, count 0 2006.196.07:36:30.56#ibcon#read 4, iclass 17, count 0 2006.196.07:36:30.56#ibcon#about to read 5, iclass 17, count 0 2006.196.07:36:30.56#ibcon#read 5, iclass 17, count 0 2006.196.07:36:30.56#ibcon#about to read 6, iclass 17, count 0 2006.196.07:36:30.56#ibcon#read 6, iclass 17, count 0 2006.196.07:36:30.56#ibcon#end of sib2, iclass 17, count 0 2006.196.07:36:30.56#ibcon#*after write, iclass 17, count 0 2006.196.07:36:30.56#ibcon#*before return 0, iclass 17, count 0 2006.196.07:36:30.56#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.196.07:36:30.56#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.196.07:36:30.56#ibcon#about to clear, iclass 17 cls_cnt 0 2006.196.07:36:30.56#ibcon#cleared, iclass 17 cls_cnt 0 2006.196.07:36:30.56$vc4f8/vblo=1,632.99 2006.196.07:36:30.56#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.196.07:36:30.56#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.196.07:36:30.56#ibcon#ireg 17 cls_cnt 0 2006.196.07:36:30.56#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.196.07:36:30.56#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.196.07:36:30.56#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.196.07:36:30.56#ibcon#enter wrdev, iclass 19, count 0 2006.196.07:36:30.56#ibcon#first serial, iclass 19, count 0 2006.196.07:36:30.56#ibcon#enter sib2, iclass 19, count 0 2006.196.07:36:30.56#ibcon#flushed, iclass 19, count 0 2006.196.07:36:30.56#ibcon#about to write, iclass 19, count 0 2006.196.07:36:30.56#ibcon#wrote, iclass 19, count 0 2006.196.07:36:30.56#ibcon#about to read 3, iclass 19, count 0 2006.196.07:36:30.58#ibcon#read 3, iclass 19, count 0 2006.196.07:36:30.58#ibcon#about to read 4, iclass 19, count 0 2006.196.07:36:30.58#ibcon#read 4, iclass 19, count 0 2006.196.07:36:30.58#ibcon#about to read 5, iclass 19, count 0 2006.196.07:36:30.58#ibcon#read 5, iclass 19, count 0 2006.196.07:36:30.58#ibcon#about to read 6, iclass 19, count 0 2006.196.07:36:30.58#ibcon#read 6, iclass 19, count 0 2006.196.07:36:30.58#ibcon#end of sib2, iclass 19, count 0 2006.196.07:36:30.58#ibcon#*mode == 0, iclass 19, count 0 2006.196.07:36:30.58#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.196.07:36:30.58#ibcon#[28=FRQ=01,632.99\r\n] 2006.196.07:36:30.58#ibcon#*before write, iclass 19, count 0 2006.196.07:36:30.58#ibcon#enter sib2, iclass 19, count 0 2006.196.07:36:30.58#ibcon#flushed, iclass 19, count 0 2006.196.07:36:30.58#ibcon#about to write, iclass 19, count 0 2006.196.07:36:30.58#ibcon#wrote, iclass 19, count 0 2006.196.07:36:30.58#ibcon#about to read 3, iclass 19, count 0 2006.196.07:36:30.62#ibcon#read 3, iclass 19, count 0 2006.196.07:36:30.62#ibcon#about to read 4, iclass 19, count 0 2006.196.07:36:30.62#ibcon#read 4, iclass 19, count 0 2006.196.07:36:30.62#ibcon#about to read 5, iclass 19, count 0 2006.196.07:36:30.62#ibcon#read 5, iclass 19, count 0 2006.196.07:36:30.62#ibcon#about to read 6, iclass 19, count 0 2006.196.07:36:30.62#ibcon#read 6, iclass 19, count 0 2006.196.07:36:30.62#ibcon#end of sib2, iclass 19, count 0 2006.196.07:36:30.62#ibcon#*after write, iclass 19, count 0 2006.196.07:36:30.62#ibcon#*before return 0, iclass 19, count 0 2006.196.07:36:30.62#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.196.07:36:30.62#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.196.07:36:30.62#ibcon#about to clear, iclass 19 cls_cnt 0 2006.196.07:36:30.62#ibcon#cleared, iclass 19 cls_cnt 0 2006.196.07:36:30.62$vc4f8/vb=1,4 2006.196.07:36:30.62#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.196.07:36:30.62#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.196.07:36:30.62#ibcon#ireg 11 cls_cnt 2 2006.196.07:36:30.62#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.196.07:36:30.62#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.196.07:36:30.62#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.196.07:36:30.62#ibcon#enter wrdev, iclass 21, count 2 2006.196.07:36:30.62#ibcon#first serial, iclass 21, count 2 2006.196.07:36:30.62#ibcon#enter sib2, iclass 21, count 2 2006.196.07:36:30.62#ibcon#flushed, iclass 21, count 2 2006.196.07:36:30.62#ibcon#about to write, iclass 21, count 2 2006.196.07:36:30.62#ibcon#wrote, iclass 21, count 2 2006.196.07:36:30.62#ibcon#about to read 3, iclass 21, count 2 2006.196.07:36:30.64#ibcon#read 3, iclass 21, count 2 2006.196.07:36:30.64#ibcon#about to read 4, iclass 21, count 2 2006.196.07:36:30.64#ibcon#read 4, iclass 21, count 2 2006.196.07:36:30.64#ibcon#about to read 5, iclass 21, count 2 2006.196.07:36:30.64#ibcon#read 5, iclass 21, count 2 2006.196.07:36:30.64#ibcon#about to read 6, iclass 21, count 2 2006.196.07:36:30.64#ibcon#read 6, iclass 21, count 2 2006.196.07:36:30.64#ibcon#end of sib2, iclass 21, count 2 2006.196.07:36:30.64#ibcon#*mode == 0, iclass 21, count 2 2006.196.07:36:30.64#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.196.07:36:30.64#ibcon#[27=AT01-04\r\n] 2006.196.07:36:30.64#ibcon#*before write, iclass 21, count 2 2006.196.07:36:30.64#ibcon#enter sib2, iclass 21, count 2 2006.196.07:36:30.64#ibcon#flushed, iclass 21, count 2 2006.196.07:36:30.64#ibcon#about to write, iclass 21, count 2 2006.196.07:36:30.64#ibcon#wrote, iclass 21, count 2 2006.196.07:36:30.64#ibcon#about to read 3, iclass 21, count 2 2006.196.07:36:30.67#ibcon#read 3, iclass 21, count 2 2006.196.07:36:30.67#ibcon#about to read 4, iclass 21, count 2 2006.196.07:36:30.67#ibcon#read 4, iclass 21, count 2 2006.196.07:36:30.67#ibcon#about to read 5, iclass 21, count 2 2006.196.07:36:30.67#ibcon#read 5, iclass 21, count 2 2006.196.07:36:30.67#ibcon#about to read 6, iclass 21, count 2 2006.196.07:36:30.67#ibcon#read 6, iclass 21, count 2 2006.196.07:36:30.67#ibcon#end of sib2, iclass 21, count 2 2006.196.07:36:30.67#ibcon#*after write, iclass 21, count 2 2006.196.07:36:30.67#ibcon#*before return 0, iclass 21, count 2 2006.196.07:36:30.67#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.196.07:36:30.67#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.196.07:36:30.67#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.196.07:36:30.67#ibcon#ireg 7 cls_cnt 0 2006.196.07:36:30.67#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.196.07:36:30.79#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.196.07:36:30.79#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.196.07:36:30.79#ibcon#enter wrdev, iclass 21, count 0 2006.196.07:36:30.79#ibcon#first serial, iclass 21, count 0 2006.196.07:36:30.79#ibcon#enter sib2, iclass 21, count 0 2006.196.07:36:30.79#ibcon#flushed, iclass 21, count 0 2006.196.07:36:30.79#ibcon#about to write, iclass 21, count 0 2006.196.07:36:30.79#ibcon#wrote, iclass 21, count 0 2006.196.07:36:30.79#ibcon#about to read 3, iclass 21, count 0 2006.196.07:36:30.81#ibcon#read 3, iclass 21, count 0 2006.196.07:36:30.81#ibcon#about to read 4, iclass 21, count 0 2006.196.07:36:30.81#ibcon#read 4, iclass 21, count 0 2006.196.07:36:30.81#ibcon#about to read 5, iclass 21, count 0 2006.196.07:36:30.81#ibcon#read 5, iclass 21, count 0 2006.196.07:36:30.81#ibcon#about to read 6, iclass 21, count 0 2006.196.07:36:30.81#ibcon#read 6, iclass 21, count 0 2006.196.07:36:30.81#ibcon#end of sib2, iclass 21, count 0 2006.196.07:36:30.81#ibcon#*mode == 0, iclass 21, count 0 2006.196.07:36:30.81#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.196.07:36:30.81#ibcon#[27=USB\r\n] 2006.196.07:36:30.81#ibcon#*before write, iclass 21, count 0 2006.196.07:36:30.81#ibcon#enter sib2, iclass 21, count 0 2006.196.07:36:30.81#ibcon#flushed, iclass 21, count 0 2006.196.07:36:30.81#ibcon#about to write, iclass 21, count 0 2006.196.07:36:30.81#ibcon#wrote, iclass 21, count 0 2006.196.07:36:30.81#ibcon#about to read 3, iclass 21, count 0 2006.196.07:36:30.84#ibcon#read 3, iclass 21, count 0 2006.196.07:36:30.84#ibcon#about to read 4, iclass 21, count 0 2006.196.07:36:30.84#ibcon#read 4, iclass 21, count 0 2006.196.07:36:30.84#ibcon#about to read 5, iclass 21, count 0 2006.196.07:36:30.84#ibcon#read 5, iclass 21, count 0 2006.196.07:36:30.84#ibcon#about to read 6, iclass 21, count 0 2006.196.07:36:30.84#ibcon#read 6, iclass 21, count 0 2006.196.07:36:30.84#ibcon#end of sib2, iclass 21, count 0 2006.196.07:36:30.84#ibcon#*after write, iclass 21, count 0 2006.196.07:36:30.84#ibcon#*before return 0, iclass 21, count 0 2006.196.07:36:30.84#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.196.07:36:30.84#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.196.07:36:30.84#ibcon#about to clear, iclass 21 cls_cnt 0 2006.196.07:36:30.84#ibcon#cleared, iclass 21 cls_cnt 0 2006.196.07:36:30.84$vc4f8/vblo=2,640.99 2006.196.07:36:30.84#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.196.07:36:30.84#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.196.07:36:30.84#ibcon#ireg 17 cls_cnt 0 2006.196.07:36:30.84#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.196.07:36:30.84#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.196.07:36:30.84#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.196.07:36:30.84#ibcon#enter wrdev, iclass 23, count 0 2006.196.07:36:30.84#ibcon#first serial, iclass 23, count 0 2006.196.07:36:30.84#ibcon#enter sib2, iclass 23, count 0 2006.196.07:36:30.84#ibcon#flushed, iclass 23, count 0 2006.196.07:36:30.84#ibcon#about to write, iclass 23, count 0 2006.196.07:36:30.84#ibcon#wrote, iclass 23, count 0 2006.196.07:36:30.84#ibcon#about to read 3, iclass 23, count 0 2006.196.07:36:30.86#ibcon#read 3, iclass 23, count 0 2006.196.07:36:30.86#ibcon#about to read 4, iclass 23, count 0 2006.196.07:36:30.86#ibcon#read 4, iclass 23, count 0 2006.196.07:36:30.86#ibcon#about to read 5, iclass 23, count 0 2006.196.07:36:30.86#ibcon#read 5, iclass 23, count 0 2006.196.07:36:30.86#ibcon#about to read 6, iclass 23, count 0 2006.196.07:36:30.86#ibcon#read 6, iclass 23, count 0 2006.196.07:36:30.86#ibcon#end of sib2, iclass 23, count 0 2006.196.07:36:30.86#ibcon#*mode == 0, iclass 23, count 0 2006.196.07:36:30.86#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.196.07:36:30.86#ibcon#[28=FRQ=02,640.99\r\n] 2006.196.07:36:30.86#ibcon#*before write, iclass 23, count 0 2006.196.07:36:30.86#ibcon#enter sib2, iclass 23, count 0 2006.196.07:36:30.86#ibcon#flushed, iclass 23, count 0 2006.196.07:36:30.86#ibcon#about to write, iclass 23, count 0 2006.196.07:36:30.86#ibcon#wrote, iclass 23, count 0 2006.196.07:36:30.86#ibcon#about to read 3, iclass 23, count 0 2006.196.07:36:30.90#ibcon#read 3, iclass 23, count 0 2006.196.07:36:30.90#ibcon#about to read 4, iclass 23, count 0 2006.196.07:36:30.90#ibcon#read 4, iclass 23, count 0 2006.196.07:36:30.90#ibcon#about to read 5, iclass 23, count 0 2006.196.07:36:30.90#ibcon#read 5, iclass 23, count 0 2006.196.07:36:30.90#ibcon#about to read 6, iclass 23, count 0 2006.196.07:36:30.90#ibcon#read 6, iclass 23, count 0 2006.196.07:36:30.90#ibcon#end of sib2, iclass 23, count 0 2006.196.07:36:30.90#ibcon#*after write, iclass 23, count 0 2006.196.07:36:30.90#ibcon#*before return 0, iclass 23, count 0 2006.196.07:36:30.90#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.196.07:36:30.90#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.196.07:36:30.90#ibcon#about to clear, iclass 23 cls_cnt 0 2006.196.07:36:30.90#ibcon#cleared, iclass 23 cls_cnt 0 2006.196.07:36:30.90$vc4f8/vb=2,4 2006.196.07:36:30.90#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.196.07:36:30.90#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.196.07:36:30.90#ibcon#ireg 11 cls_cnt 2 2006.196.07:36:30.90#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.196.07:36:30.96#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.196.07:36:30.96#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.196.07:36:30.96#ibcon#enter wrdev, iclass 25, count 2 2006.196.07:36:30.96#ibcon#first serial, iclass 25, count 2 2006.196.07:36:30.96#ibcon#enter sib2, iclass 25, count 2 2006.196.07:36:30.96#ibcon#flushed, iclass 25, count 2 2006.196.07:36:30.96#ibcon#about to write, iclass 25, count 2 2006.196.07:36:30.96#ibcon#wrote, iclass 25, count 2 2006.196.07:36:30.96#ibcon#about to read 3, iclass 25, count 2 2006.196.07:36:30.98#ibcon#read 3, iclass 25, count 2 2006.196.07:36:30.98#ibcon#about to read 4, iclass 25, count 2 2006.196.07:36:30.98#ibcon#read 4, iclass 25, count 2 2006.196.07:36:30.98#ibcon#about to read 5, iclass 25, count 2 2006.196.07:36:30.98#ibcon#read 5, iclass 25, count 2 2006.196.07:36:30.98#ibcon#about to read 6, iclass 25, count 2 2006.196.07:36:30.98#ibcon#read 6, iclass 25, count 2 2006.196.07:36:30.98#ibcon#end of sib2, iclass 25, count 2 2006.196.07:36:30.98#ibcon#*mode == 0, iclass 25, count 2 2006.196.07:36:30.98#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.196.07:36:30.98#ibcon#[27=AT02-04\r\n] 2006.196.07:36:30.98#ibcon#*before write, iclass 25, count 2 2006.196.07:36:30.98#ibcon#enter sib2, iclass 25, count 2 2006.196.07:36:30.98#ibcon#flushed, iclass 25, count 2 2006.196.07:36:30.98#ibcon#about to write, iclass 25, count 2 2006.196.07:36:30.98#ibcon#wrote, iclass 25, count 2 2006.196.07:36:30.98#ibcon#about to read 3, iclass 25, count 2 2006.196.07:36:31.01#ibcon#read 3, iclass 25, count 2 2006.196.07:36:31.01#ibcon#about to read 4, iclass 25, count 2 2006.196.07:36:31.01#ibcon#read 4, iclass 25, count 2 2006.196.07:36:31.01#ibcon#about to read 5, iclass 25, count 2 2006.196.07:36:31.01#ibcon#read 5, iclass 25, count 2 2006.196.07:36:31.01#ibcon#about to read 6, iclass 25, count 2 2006.196.07:36:31.01#ibcon#read 6, iclass 25, count 2 2006.196.07:36:31.01#ibcon#end of sib2, iclass 25, count 2 2006.196.07:36:31.01#ibcon#*after write, iclass 25, count 2 2006.196.07:36:31.01#ibcon#*before return 0, iclass 25, count 2 2006.196.07:36:31.01#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.196.07:36:31.01#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.196.07:36:31.01#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.196.07:36:31.01#ibcon#ireg 7 cls_cnt 0 2006.196.07:36:31.01#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.196.07:36:31.09#abcon#<5=/05 4.1 6.7 30.13 861004.0\r\n> 2006.196.07:36:31.11#abcon#{5=INTERFACE CLEAR} 2006.196.07:36:31.13#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.196.07:36:31.13#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.196.07:36:31.13#ibcon#enter wrdev, iclass 25, count 0 2006.196.07:36:31.13#ibcon#first serial, iclass 25, count 0 2006.196.07:36:31.13#ibcon#enter sib2, iclass 25, count 0 2006.196.07:36:31.13#ibcon#flushed, iclass 25, count 0 2006.196.07:36:31.13#ibcon#about to write, iclass 25, count 0 2006.196.07:36:31.13#ibcon#wrote, iclass 25, count 0 2006.196.07:36:31.13#ibcon#about to read 3, iclass 25, count 0 2006.196.07:36:31.15#ibcon#read 3, iclass 25, count 0 2006.196.07:36:31.15#ibcon#about to read 4, iclass 25, count 0 2006.196.07:36:31.15#ibcon#read 4, iclass 25, count 0 2006.196.07:36:31.15#ibcon#about to read 5, iclass 25, count 0 2006.196.07:36:31.15#ibcon#read 5, iclass 25, count 0 2006.196.07:36:31.15#ibcon#about to read 6, iclass 25, count 0 2006.196.07:36:31.15#ibcon#read 6, iclass 25, count 0 2006.196.07:36:31.15#ibcon#end of sib2, iclass 25, count 0 2006.196.07:36:31.15#ibcon#*mode == 0, iclass 25, count 0 2006.196.07:36:31.15#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.196.07:36:31.15#ibcon#[27=USB\r\n] 2006.196.07:36:31.15#ibcon#*before write, iclass 25, count 0 2006.196.07:36:31.15#ibcon#enter sib2, iclass 25, count 0 2006.196.07:36:31.15#ibcon#flushed, iclass 25, count 0 2006.196.07:36:31.15#ibcon#about to write, iclass 25, count 0 2006.196.07:36:31.15#ibcon#wrote, iclass 25, count 0 2006.196.07:36:31.15#ibcon#about to read 3, iclass 25, count 0 2006.196.07:36:31.17#abcon#[5=S1D000X0/0*\r\n] 2006.196.07:36:31.18#ibcon#read 3, iclass 25, count 0 2006.196.07:36:31.18#ibcon#about to read 4, iclass 25, count 0 2006.196.07:36:31.18#ibcon#read 4, iclass 25, count 0 2006.196.07:36:31.18#ibcon#about to read 5, iclass 25, count 0 2006.196.07:36:31.18#ibcon#read 5, iclass 25, count 0 2006.196.07:36:31.18#ibcon#about to read 6, iclass 25, count 0 2006.196.07:36:31.18#ibcon#read 6, iclass 25, count 0 2006.196.07:36:31.18#ibcon#end of sib2, iclass 25, count 0 2006.196.07:36:31.18#ibcon#*after write, iclass 25, count 0 2006.196.07:36:31.18#ibcon#*before return 0, iclass 25, count 0 2006.196.07:36:31.18#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.196.07:36:31.18#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.196.07:36:31.18#ibcon#about to clear, iclass 25 cls_cnt 0 2006.196.07:36:31.18#ibcon#cleared, iclass 25 cls_cnt 0 2006.196.07:36:31.18$vc4f8/vblo=3,656.99 2006.196.07:36:31.18#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.196.07:36:31.18#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.196.07:36:31.18#ibcon#ireg 17 cls_cnt 0 2006.196.07:36:31.18#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.196.07:36:31.18#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.196.07:36:31.18#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.196.07:36:31.18#ibcon#enter wrdev, iclass 31, count 0 2006.196.07:36:31.18#ibcon#first serial, iclass 31, count 0 2006.196.07:36:31.18#ibcon#enter sib2, iclass 31, count 0 2006.196.07:36:31.18#ibcon#flushed, iclass 31, count 0 2006.196.07:36:31.18#ibcon#about to write, iclass 31, count 0 2006.196.07:36:31.18#ibcon#wrote, iclass 31, count 0 2006.196.07:36:31.18#ibcon#about to read 3, iclass 31, count 0 2006.196.07:36:31.20#ibcon#read 3, iclass 31, count 0 2006.196.07:36:31.20#ibcon#about to read 4, iclass 31, count 0 2006.196.07:36:31.20#ibcon#read 4, iclass 31, count 0 2006.196.07:36:31.20#ibcon#about to read 5, iclass 31, count 0 2006.196.07:36:31.20#ibcon#read 5, iclass 31, count 0 2006.196.07:36:31.20#ibcon#about to read 6, iclass 31, count 0 2006.196.07:36:31.20#ibcon#read 6, iclass 31, count 0 2006.196.07:36:31.20#ibcon#end of sib2, iclass 31, count 0 2006.196.07:36:31.20#ibcon#*mode == 0, iclass 31, count 0 2006.196.07:36:31.20#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.196.07:36:31.20#ibcon#[28=FRQ=03,656.99\r\n] 2006.196.07:36:31.20#ibcon#*before write, iclass 31, count 0 2006.196.07:36:31.20#ibcon#enter sib2, iclass 31, count 0 2006.196.07:36:31.20#ibcon#flushed, iclass 31, count 0 2006.196.07:36:31.20#ibcon#about to write, iclass 31, count 0 2006.196.07:36:31.20#ibcon#wrote, iclass 31, count 0 2006.196.07:36:31.20#ibcon#about to read 3, iclass 31, count 0 2006.196.07:36:31.24#ibcon#read 3, iclass 31, count 0 2006.196.07:36:31.24#ibcon#about to read 4, iclass 31, count 0 2006.196.07:36:31.24#ibcon#read 4, iclass 31, count 0 2006.196.07:36:31.24#ibcon#about to read 5, iclass 31, count 0 2006.196.07:36:31.24#ibcon#read 5, iclass 31, count 0 2006.196.07:36:31.24#ibcon#about to read 6, iclass 31, count 0 2006.196.07:36:31.24#ibcon#read 6, iclass 31, count 0 2006.196.07:36:31.24#ibcon#end of sib2, iclass 31, count 0 2006.196.07:36:31.24#ibcon#*after write, iclass 31, count 0 2006.196.07:36:31.24#ibcon#*before return 0, iclass 31, count 0 2006.196.07:36:31.24#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.196.07:36:31.24#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.196.07:36:31.24#ibcon#about to clear, iclass 31 cls_cnt 0 2006.196.07:36:31.24#ibcon#cleared, iclass 31 cls_cnt 0 2006.196.07:36:31.24$vc4f8/vb=3,4 2006.196.07:36:31.24#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.196.07:36:31.24#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.196.07:36:31.24#ibcon#ireg 11 cls_cnt 2 2006.196.07:36:31.24#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.196.07:36:31.30#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.196.07:36:31.30#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.196.07:36:31.30#ibcon#enter wrdev, iclass 33, count 2 2006.196.07:36:31.30#ibcon#first serial, iclass 33, count 2 2006.196.07:36:31.30#ibcon#enter sib2, iclass 33, count 2 2006.196.07:36:31.30#ibcon#flushed, iclass 33, count 2 2006.196.07:36:31.30#ibcon#about to write, iclass 33, count 2 2006.196.07:36:31.30#ibcon#wrote, iclass 33, count 2 2006.196.07:36:31.30#ibcon#about to read 3, iclass 33, count 2 2006.196.07:36:31.32#ibcon#read 3, iclass 33, count 2 2006.196.07:36:31.32#ibcon#about to read 4, iclass 33, count 2 2006.196.07:36:31.32#ibcon#read 4, iclass 33, count 2 2006.196.07:36:31.32#ibcon#about to read 5, iclass 33, count 2 2006.196.07:36:31.32#ibcon#read 5, iclass 33, count 2 2006.196.07:36:31.32#ibcon#about to read 6, iclass 33, count 2 2006.196.07:36:31.32#ibcon#read 6, iclass 33, count 2 2006.196.07:36:31.32#ibcon#end of sib2, iclass 33, count 2 2006.196.07:36:31.32#ibcon#*mode == 0, iclass 33, count 2 2006.196.07:36:31.32#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.196.07:36:31.32#ibcon#[27=AT03-04\r\n] 2006.196.07:36:31.32#ibcon#*before write, iclass 33, count 2 2006.196.07:36:31.32#ibcon#enter sib2, iclass 33, count 2 2006.196.07:36:31.32#ibcon#flushed, iclass 33, count 2 2006.196.07:36:31.32#ibcon#about to write, iclass 33, count 2 2006.196.07:36:31.32#ibcon#wrote, iclass 33, count 2 2006.196.07:36:31.32#ibcon#about to read 3, iclass 33, count 2 2006.196.07:36:31.35#ibcon#read 3, iclass 33, count 2 2006.196.07:36:31.35#ibcon#about to read 4, iclass 33, count 2 2006.196.07:36:31.35#ibcon#read 4, iclass 33, count 2 2006.196.07:36:31.35#ibcon#about to read 5, iclass 33, count 2 2006.196.07:36:31.35#ibcon#read 5, iclass 33, count 2 2006.196.07:36:31.35#ibcon#about to read 6, iclass 33, count 2 2006.196.07:36:31.35#ibcon#read 6, iclass 33, count 2 2006.196.07:36:31.35#ibcon#end of sib2, iclass 33, count 2 2006.196.07:36:31.35#ibcon#*after write, iclass 33, count 2 2006.196.07:36:31.35#ibcon#*before return 0, iclass 33, count 2 2006.196.07:36:31.35#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.196.07:36:31.35#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.196.07:36:31.35#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.196.07:36:31.35#ibcon#ireg 7 cls_cnt 0 2006.196.07:36:31.35#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.196.07:36:31.47#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.196.07:36:31.47#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.196.07:36:31.47#ibcon#enter wrdev, iclass 33, count 0 2006.196.07:36:31.47#ibcon#first serial, iclass 33, count 0 2006.196.07:36:31.47#ibcon#enter sib2, iclass 33, count 0 2006.196.07:36:31.47#ibcon#flushed, iclass 33, count 0 2006.196.07:36:31.47#ibcon#about to write, iclass 33, count 0 2006.196.07:36:31.47#ibcon#wrote, iclass 33, count 0 2006.196.07:36:31.47#ibcon#about to read 3, iclass 33, count 0 2006.196.07:36:31.49#ibcon#read 3, iclass 33, count 0 2006.196.07:36:31.49#ibcon#about to read 4, iclass 33, count 0 2006.196.07:36:31.49#ibcon#read 4, iclass 33, count 0 2006.196.07:36:31.49#ibcon#about to read 5, iclass 33, count 0 2006.196.07:36:31.49#ibcon#read 5, iclass 33, count 0 2006.196.07:36:31.49#ibcon#about to read 6, iclass 33, count 0 2006.196.07:36:31.49#ibcon#read 6, iclass 33, count 0 2006.196.07:36:31.49#ibcon#end of sib2, iclass 33, count 0 2006.196.07:36:31.49#ibcon#*mode == 0, iclass 33, count 0 2006.196.07:36:31.49#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.196.07:36:31.49#ibcon#[27=USB\r\n] 2006.196.07:36:31.49#ibcon#*before write, iclass 33, count 0 2006.196.07:36:31.49#ibcon#enter sib2, iclass 33, count 0 2006.196.07:36:31.49#ibcon#flushed, iclass 33, count 0 2006.196.07:36:31.49#ibcon#about to write, iclass 33, count 0 2006.196.07:36:31.49#ibcon#wrote, iclass 33, count 0 2006.196.07:36:31.49#ibcon#about to read 3, iclass 33, count 0 2006.196.07:36:31.52#ibcon#read 3, iclass 33, count 0 2006.196.07:36:31.52#ibcon#about to read 4, iclass 33, count 0 2006.196.07:36:31.52#ibcon#read 4, iclass 33, count 0 2006.196.07:36:31.52#ibcon#about to read 5, iclass 33, count 0 2006.196.07:36:31.52#ibcon#read 5, iclass 33, count 0 2006.196.07:36:31.52#ibcon#about to read 6, iclass 33, count 0 2006.196.07:36:31.52#ibcon#read 6, iclass 33, count 0 2006.196.07:36:31.52#ibcon#end of sib2, iclass 33, count 0 2006.196.07:36:31.52#ibcon#*after write, iclass 33, count 0 2006.196.07:36:31.52#ibcon#*before return 0, iclass 33, count 0 2006.196.07:36:31.52#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.196.07:36:31.52#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.196.07:36:31.52#ibcon#about to clear, iclass 33 cls_cnt 0 2006.196.07:36:31.52#ibcon#cleared, iclass 33 cls_cnt 0 2006.196.07:36:31.52$vc4f8/vblo=4,712.99 2006.196.07:36:31.52#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.196.07:36:31.52#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.196.07:36:31.52#ibcon#ireg 17 cls_cnt 0 2006.196.07:36:31.52#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.196.07:36:31.52#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.196.07:36:31.52#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.196.07:36:31.52#ibcon#enter wrdev, iclass 35, count 0 2006.196.07:36:31.52#ibcon#first serial, iclass 35, count 0 2006.196.07:36:31.52#ibcon#enter sib2, iclass 35, count 0 2006.196.07:36:31.52#ibcon#flushed, iclass 35, count 0 2006.196.07:36:31.52#ibcon#about to write, iclass 35, count 0 2006.196.07:36:31.52#ibcon#wrote, iclass 35, count 0 2006.196.07:36:31.52#ibcon#about to read 3, iclass 35, count 0 2006.196.07:36:31.54#ibcon#read 3, iclass 35, count 0 2006.196.07:36:31.54#ibcon#about to read 4, iclass 35, count 0 2006.196.07:36:31.54#ibcon#read 4, iclass 35, count 0 2006.196.07:36:31.54#ibcon#about to read 5, iclass 35, count 0 2006.196.07:36:31.54#ibcon#read 5, iclass 35, count 0 2006.196.07:36:31.54#ibcon#about to read 6, iclass 35, count 0 2006.196.07:36:31.54#ibcon#read 6, iclass 35, count 0 2006.196.07:36:31.54#ibcon#end of sib2, iclass 35, count 0 2006.196.07:36:31.54#ibcon#*mode == 0, iclass 35, count 0 2006.196.07:36:31.54#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.196.07:36:31.54#ibcon#[28=FRQ=04,712.99\r\n] 2006.196.07:36:31.54#ibcon#*before write, iclass 35, count 0 2006.196.07:36:31.54#ibcon#enter sib2, iclass 35, count 0 2006.196.07:36:31.54#ibcon#flushed, iclass 35, count 0 2006.196.07:36:31.54#ibcon#about to write, iclass 35, count 0 2006.196.07:36:31.54#ibcon#wrote, iclass 35, count 0 2006.196.07:36:31.54#ibcon#about to read 3, iclass 35, count 0 2006.196.07:36:31.58#ibcon#read 3, iclass 35, count 0 2006.196.07:36:31.58#ibcon#about to read 4, iclass 35, count 0 2006.196.07:36:31.58#ibcon#read 4, iclass 35, count 0 2006.196.07:36:31.58#ibcon#about to read 5, iclass 35, count 0 2006.196.07:36:31.58#ibcon#read 5, iclass 35, count 0 2006.196.07:36:31.58#ibcon#about to read 6, iclass 35, count 0 2006.196.07:36:31.58#ibcon#read 6, iclass 35, count 0 2006.196.07:36:31.58#ibcon#end of sib2, iclass 35, count 0 2006.196.07:36:31.58#ibcon#*after write, iclass 35, count 0 2006.196.07:36:31.58#ibcon#*before return 0, iclass 35, count 0 2006.196.07:36:31.58#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.196.07:36:31.58#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.196.07:36:31.58#ibcon#about to clear, iclass 35 cls_cnt 0 2006.196.07:36:31.58#ibcon#cleared, iclass 35 cls_cnt 0 2006.196.07:36:31.58$vc4f8/vb=4,4 2006.196.07:36:31.58#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.196.07:36:31.58#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.196.07:36:31.58#ibcon#ireg 11 cls_cnt 2 2006.196.07:36:31.58#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.196.07:36:31.64#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.196.07:36:31.64#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.196.07:36:31.64#ibcon#enter wrdev, iclass 37, count 2 2006.196.07:36:31.64#ibcon#first serial, iclass 37, count 2 2006.196.07:36:31.64#ibcon#enter sib2, iclass 37, count 2 2006.196.07:36:31.64#ibcon#flushed, iclass 37, count 2 2006.196.07:36:31.64#ibcon#about to write, iclass 37, count 2 2006.196.07:36:31.64#ibcon#wrote, iclass 37, count 2 2006.196.07:36:31.64#ibcon#about to read 3, iclass 37, count 2 2006.196.07:36:31.66#ibcon#read 3, iclass 37, count 2 2006.196.07:36:31.66#ibcon#about to read 4, iclass 37, count 2 2006.196.07:36:31.66#ibcon#read 4, iclass 37, count 2 2006.196.07:36:31.66#ibcon#about to read 5, iclass 37, count 2 2006.196.07:36:31.66#ibcon#read 5, iclass 37, count 2 2006.196.07:36:31.66#ibcon#about to read 6, iclass 37, count 2 2006.196.07:36:31.66#ibcon#read 6, iclass 37, count 2 2006.196.07:36:31.66#ibcon#end of sib2, iclass 37, count 2 2006.196.07:36:31.66#ibcon#*mode == 0, iclass 37, count 2 2006.196.07:36:31.66#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.196.07:36:31.66#ibcon#[27=AT04-04\r\n] 2006.196.07:36:31.66#ibcon#*before write, iclass 37, count 2 2006.196.07:36:31.66#ibcon#enter sib2, iclass 37, count 2 2006.196.07:36:31.66#ibcon#flushed, iclass 37, count 2 2006.196.07:36:31.66#ibcon#about to write, iclass 37, count 2 2006.196.07:36:31.66#ibcon#wrote, iclass 37, count 2 2006.196.07:36:31.66#ibcon#about to read 3, iclass 37, count 2 2006.196.07:36:31.69#ibcon#read 3, iclass 37, count 2 2006.196.07:36:31.69#ibcon#about to read 4, iclass 37, count 2 2006.196.07:36:31.69#ibcon#read 4, iclass 37, count 2 2006.196.07:36:31.69#ibcon#about to read 5, iclass 37, count 2 2006.196.07:36:31.69#ibcon#read 5, iclass 37, count 2 2006.196.07:36:31.69#ibcon#about to read 6, iclass 37, count 2 2006.196.07:36:31.69#ibcon#read 6, iclass 37, count 2 2006.196.07:36:31.69#ibcon#end of sib2, iclass 37, count 2 2006.196.07:36:31.69#ibcon#*after write, iclass 37, count 2 2006.196.07:36:31.69#ibcon#*before return 0, iclass 37, count 2 2006.196.07:36:31.69#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.196.07:36:31.69#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.196.07:36:31.69#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.196.07:36:31.69#ibcon#ireg 7 cls_cnt 0 2006.196.07:36:31.69#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.196.07:36:31.81#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.196.07:36:31.81#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.196.07:36:31.81#ibcon#enter wrdev, iclass 37, count 0 2006.196.07:36:31.81#ibcon#first serial, iclass 37, count 0 2006.196.07:36:31.81#ibcon#enter sib2, iclass 37, count 0 2006.196.07:36:31.81#ibcon#flushed, iclass 37, count 0 2006.196.07:36:31.81#ibcon#about to write, iclass 37, count 0 2006.196.07:36:31.81#ibcon#wrote, iclass 37, count 0 2006.196.07:36:31.81#ibcon#about to read 3, iclass 37, count 0 2006.196.07:36:31.83#ibcon#read 3, iclass 37, count 0 2006.196.07:36:31.83#ibcon#about to read 4, iclass 37, count 0 2006.196.07:36:31.83#ibcon#read 4, iclass 37, count 0 2006.196.07:36:31.83#ibcon#about to read 5, iclass 37, count 0 2006.196.07:36:31.83#ibcon#read 5, iclass 37, count 0 2006.196.07:36:31.83#ibcon#about to read 6, iclass 37, count 0 2006.196.07:36:31.83#ibcon#read 6, iclass 37, count 0 2006.196.07:36:31.83#ibcon#end of sib2, iclass 37, count 0 2006.196.07:36:31.83#ibcon#*mode == 0, iclass 37, count 0 2006.196.07:36:31.83#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.196.07:36:31.83#ibcon#[27=USB\r\n] 2006.196.07:36:31.83#ibcon#*before write, iclass 37, count 0 2006.196.07:36:31.83#ibcon#enter sib2, iclass 37, count 0 2006.196.07:36:31.83#ibcon#flushed, iclass 37, count 0 2006.196.07:36:31.83#ibcon#about to write, iclass 37, count 0 2006.196.07:36:31.83#ibcon#wrote, iclass 37, count 0 2006.196.07:36:31.83#ibcon#about to read 3, iclass 37, count 0 2006.196.07:36:31.86#ibcon#read 3, iclass 37, count 0 2006.196.07:36:31.86#ibcon#about to read 4, iclass 37, count 0 2006.196.07:36:31.86#ibcon#read 4, iclass 37, count 0 2006.196.07:36:31.86#ibcon#about to read 5, iclass 37, count 0 2006.196.07:36:31.86#ibcon#read 5, iclass 37, count 0 2006.196.07:36:31.86#ibcon#about to read 6, iclass 37, count 0 2006.196.07:36:31.86#ibcon#read 6, iclass 37, count 0 2006.196.07:36:31.86#ibcon#end of sib2, iclass 37, count 0 2006.196.07:36:31.86#ibcon#*after write, iclass 37, count 0 2006.196.07:36:31.86#ibcon#*before return 0, iclass 37, count 0 2006.196.07:36:31.86#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.196.07:36:31.86#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.196.07:36:31.86#ibcon#about to clear, iclass 37 cls_cnt 0 2006.196.07:36:31.86#ibcon#cleared, iclass 37 cls_cnt 0 2006.196.07:36:31.86$vc4f8/vblo=5,744.99 2006.196.07:36:31.86#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.196.07:36:31.86#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.196.07:36:31.86#ibcon#ireg 17 cls_cnt 0 2006.196.07:36:31.86#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.196.07:36:31.86#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.196.07:36:31.86#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.196.07:36:31.86#ibcon#enter wrdev, iclass 39, count 0 2006.196.07:36:31.86#ibcon#first serial, iclass 39, count 0 2006.196.07:36:31.86#ibcon#enter sib2, iclass 39, count 0 2006.196.07:36:31.86#ibcon#flushed, iclass 39, count 0 2006.196.07:36:31.86#ibcon#about to write, iclass 39, count 0 2006.196.07:36:31.86#ibcon#wrote, iclass 39, count 0 2006.196.07:36:31.86#ibcon#about to read 3, iclass 39, count 0 2006.196.07:36:31.88#ibcon#read 3, iclass 39, count 0 2006.196.07:36:31.88#ibcon#about to read 4, iclass 39, count 0 2006.196.07:36:31.88#ibcon#read 4, iclass 39, count 0 2006.196.07:36:31.88#ibcon#about to read 5, iclass 39, count 0 2006.196.07:36:31.88#ibcon#read 5, iclass 39, count 0 2006.196.07:36:31.88#ibcon#about to read 6, iclass 39, count 0 2006.196.07:36:31.88#ibcon#read 6, iclass 39, count 0 2006.196.07:36:31.88#ibcon#end of sib2, iclass 39, count 0 2006.196.07:36:31.88#ibcon#*mode == 0, iclass 39, count 0 2006.196.07:36:31.88#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.196.07:36:31.88#ibcon#[28=FRQ=05,744.99\r\n] 2006.196.07:36:31.88#ibcon#*before write, iclass 39, count 0 2006.196.07:36:31.88#ibcon#enter sib2, iclass 39, count 0 2006.196.07:36:31.88#ibcon#flushed, iclass 39, count 0 2006.196.07:36:31.88#ibcon#about to write, iclass 39, count 0 2006.196.07:36:31.88#ibcon#wrote, iclass 39, count 0 2006.196.07:36:31.88#ibcon#about to read 3, iclass 39, count 0 2006.196.07:36:31.92#ibcon#read 3, iclass 39, count 0 2006.196.07:36:31.92#ibcon#about to read 4, iclass 39, count 0 2006.196.07:36:31.92#ibcon#read 4, iclass 39, count 0 2006.196.07:36:31.92#ibcon#about to read 5, iclass 39, count 0 2006.196.07:36:31.92#ibcon#read 5, iclass 39, count 0 2006.196.07:36:31.92#ibcon#about to read 6, iclass 39, count 0 2006.196.07:36:31.92#ibcon#read 6, iclass 39, count 0 2006.196.07:36:31.92#ibcon#end of sib2, iclass 39, count 0 2006.196.07:36:31.92#ibcon#*after write, iclass 39, count 0 2006.196.07:36:31.92#ibcon#*before return 0, iclass 39, count 0 2006.196.07:36:31.92#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.196.07:36:31.92#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.196.07:36:31.92#ibcon#about to clear, iclass 39 cls_cnt 0 2006.196.07:36:31.92#ibcon#cleared, iclass 39 cls_cnt 0 2006.196.07:36:31.92$vc4f8/vb=5,4 2006.196.07:36:31.92#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.196.07:36:31.92#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.196.07:36:31.92#ibcon#ireg 11 cls_cnt 2 2006.196.07:36:31.92#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.196.07:36:31.98#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.196.07:36:31.98#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.196.07:36:31.98#ibcon#enter wrdev, iclass 3, count 2 2006.196.07:36:31.98#ibcon#first serial, iclass 3, count 2 2006.196.07:36:31.98#ibcon#enter sib2, iclass 3, count 2 2006.196.07:36:31.98#ibcon#flushed, iclass 3, count 2 2006.196.07:36:31.98#ibcon#about to write, iclass 3, count 2 2006.196.07:36:31.98#ibcon#wrote, iclass 3, count 2 2006.196.07:36:31.98#ibcon#about to read 3, iclass 3, count 2 2006.196.07:36:32.00#ibcon#read 3, iclass 3, count 2 2006.196.07:36:32.00#ibcon#about to read 4, iclass 3, count 2 2006.196.07:36:32.00#ibcon#read 4, iclass 3, count 2 2006.196.07:36:32.00#ibcon#about to read 5, iclass 3, count 2 2006.196.07:36:32.00#ibcon#read 5, iclass 3, count 2 2006.196.07:36:32.00#ibcon#about to read 6, iclass 3, count 2 2006.196.07:36:32.00#ibcon#read 6, iclass 3, count 2 2006.196.07:36:32.00#ibcon#end of sib2, iclass 3, count 2 2006.196.07:36:32.00#ibcon#*mode == 0, iclass 3, count 2 2006.196.07:36:32.00#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.196.07:36:32.00#ibcon#[27=AT05-04\r\n] 2006.196.07:36:32.00#ibcon#*before write, iclass 3, count 2 2006.196.07:36:32.00#ibcon#enter sib2, iclass 3, count 2 2006.196.07:36:32.00#ibcon#flushed, iclass 3, count 2 2006.196.07:36:32.00#ibcon#about to write, iclass 3, count 2 2006.196.07:36:32.00#ibcon#wrote, iclass 3, count 2 2006.196.07:36:32.00#ibcon#about to read 3, iclass 3, count 2 2006.196.07:36:32.03#ibcon#read 3, iclass 3, count 2 2006.196.07:36:32.03#ibcon#about to read 4, iclass 3, count 2 2006.196.07:36:32.03#ibcon#read 4, iclass 3, count 2 2006.196.07:36:32.03#ibcon#about to read 5, iclass 3, count 2 2006.196.07:36:32.03#ibcon#read 5, iclass 3, count 2 2006.196.07:36:32.03#ibcon#about to read 6, iclass 3, count 2 2006.196.07:36:32.03#ibcon#read 6, iclass 3, count 2 2006.196.07:36:32.03#ibcon#end of sib2, iclass 3, count 2 2006.196.07:36:32.03#ibcon#*after write, iclass 3, count 2 2006.196.07:36:32.03#ibcon#*before return 0, iclass 3, count 2 2006.196.07:36:32.03#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.196.07:36:32.03#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.196.07:36:32.03#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.196.07:36:32.03#ibcon#ireg 7 cls_cnt 0 2006.196.07:36:32.03#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.196.07:36:32.15#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.196.07:36:32.15#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.196.07:36:32.15#ibcon#enter wrdev, iclass 3, count 0 2006.196.07:36:32.15#ibcon#first serial, iclass 3, count 0 2006.196.07:36:32.15#ibcon#enter sib2, iclass 3, count 0 2006.196.07:36:32.15#ibcon#flushed, iclass 3, count 0 2006.196.07:36:32.15#ibcon#about to write, iclass 3, count 0 2006.196.07:36:32.15#ibcon#wrote, iclass 3, count 0 2006.196.07:36:32.15#ibcon#about to read 3, iclass 3, count 0 2006.196.07:36:32.17#ibcon#read 3, iclass 3, count 0 2006.196.07:36:32.17#ibcon#about to read 4, iclass 3, count 0 2006.196.07:36:32.17#ibcon#read 4, iclass 3, count 0 2006.196.07:36:32.17#ibcon#about to read 5, iclass 3, count 0 2006.196.07:36:32.17#ibcon#read 5, iclass 3, count 0 2006.196.07:36:32.17#ibcon#about to read 6, iclass 3, count 0 2006.196.07:36:32.17#ibcon#read 6, iclass 3, count 0 2006.196.07:36:32.17#ibcon#end of sib2, iclass 3, count 0 2006.196.07:36:32.17#ibcon#*mode == 0, iclass 3, count 0 2006.196.07:36:32.17#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.196.07:36:32.17#ibcon#[27=USB\r\n] 2006.196.07:36:32.17#ibcon#*before write, iclass 3, count 0 2006.196.07:36:32.17#ibcon#enter sib2, iclass 3, count 0 2006.196.07:36:32.17#ibcon#flushed, iclass 3, count 0 2006.196.07:36:32.17#ibcon#about to write, iclass 3, count 0 2006.196.07:36:32.17#ibcon#wrote, iclass 3, count 0 2006.196.07:36:32.17#ibcon#about to read 3, iclass 3, count 0 2006.196.07:36:32.20#ibcon#read 3, iclass 3, count 0 2006.196.07:36:32.20#ibcon#about to read 4, iclass 3, count 0 2006.196.07:36:32.20#ibcon#read 4, iclass 3, count 0 2006.196.07:36:32.20#ibcon#about to read 5, iclass 3, count 0 2006.196.07:36:32.20#ibcon#read 5, iclass 3, count 0 2006.196.07:36:32.20#ibcon#about to read 6, iclass 3, count 0 2006.196.07:36:32.20#ibcon#read 6, iclass 3, count 0 2006.196.07:36:32.20#ibcon#end of sib2, iclass 3, count 0 2006.196.07:36:32.20#ibcon#*after write, iclass 3, count 0 2006.196.07:36:32.20#ibcon#*before return 0, iclass 3, count 0 2006.196.07:36:32.20#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.196.07:36:32.20#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.196.07:36:32.20#ibcon#about to clear, iclass 3 cls_cnt 0 2006.196.07:36:32.20#ibcon#cleared, iclass 3 cls_cnt 0 2006.196.07:36:32.20$vc4f8/vblo=6,752.99 2006.196.07:36:32.20#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.196.07:36:32.20#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.196.07:36:32.20#ibcon#ireg 17 cls_cnt 0 2006.196.07:36:32.20#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.196.07:36:32.20#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.196.07:36:32.20#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.196.07:36:32.20#ibcon#enter wrdev, iclass 5, count 0 2006.196.07:36:32.20#ibcon#first serial, iclass 5, count 0 2006.196.07:36:32.20#ibcon#enter sib2, iclass 5, count 0 2006.196.07:36:32.20#ibcon#flushed, iclass 5, count 0 2006.196.07:36:32.20#ibcon#about to write, iclass 5, count 0 2006.196.07:36:32.20#ibcon#wrote, iclass 5, count 0 2006.196.07:36:32.20#ibcon#about to read 3, iclass 5, count 0 2006.196.07:36:32.22#ibcon#read 3, iclass 5, count 0 2006.196.07:36:32.22#ibcon#about to read 4, iclass 5, count 0 2006.196.07:36:32.22#ibcon#read 4, iclass 5, count 0 2006.196.07:36:32.22#ibcon#about to read 5, iclass 5, count 0 2006.196.07:36:32.22#ibcon#read 5, iclass 5, count 0 2006.196.07:36:32.22#ibcon#about to read 6, iclass 5, count 0 2006.196.07:36:32.22#ibcon#read 6, iclass 5, count 0 2006.196.07:36:32.22#ibcon#end of sib2, iclass 5, count 0 2006.196.07:36:32.22#ibcon#*mode == 0, iclass 5, count 0 2006.196.07:36:32.22#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.196.07:36:32.22#ibcon#[28=FRQ=06,752.99\r\n] 2006.196.07:36:32.22#ibcon#*before write, iclass 5, count 0 2006.196.07:36:32.22#ibcon#enter sib2, iclass 5, count 0 2006.196.07:36:32.22#ibcon#flushed, iclass 5, count 0 2006.196.07:36:32.22#ibcon#about to write, iclass 5, count 0 2006.196.07:36:32.22#ibcon#wrote, iclass 5, count 0 2006.196.07:36:32.22#ibcon#about to read 3, iclass 5, count 0 2006.196.07:36:32.26#ibcon#read 3, iclass 5, count 0 2006.196.07:36:32.26#ibcon#about to read 4, iclass 5, count 0 2006.196.07:36:32.26#ibcon#read 4, iclass 5, count 0 2006.196.07:36:32.26#ibcon#about to read 5, iclass 5, count 0 2006.196.07:36:32.26#ibcon#read 5, iclass 5, count 0 2006.196.07:36:32.26#ibcon#about to read 6, iclass 5, count 0 2006.196.07:36:32.26#ibcon#read 6, iclass 5, count 0 2006.196.07:36:32.26#ibcon#end of sib2, iclass 5, count 0 2006.196.07:36:32.26#ibcon#*after write, iclass 5, count 0 2006.196.07:36:32.26#ibcon#*before return 0, iclass 5, count 0 2006.196.07:36:32.26#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.196.07:36:32.26#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.196.07:36:32.26#ibcon#about to clear, iclass 5 cls_cnt 0 2006.196.07:36:32.26#ibcon#cleared, iclass 5 cls_cnt 0 2006.196.07:36:32.26$vc4f8/vb=6,4 2006.196.07:36:32.26#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.196.07:36:32.26#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.196.07:36:32.26#ibcon#ireg 11 cls_cnt 2 2006.196.07:36:32.26#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.196.07:36:32.32#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.196.07:36:32.32#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.196.07:36:32.32#ibcon#enter wrdev, iclass 7, count 2 2006.196.07:36:32.32#ibcon#first serial, iclass 7, count 2 2006.196.07:36:32.32#ibcon#enter sib2, iclass 7, count 2 2006.196.07:36:32.32#ibcon#flushed, iclass 7, count 2 2006.196.07:36:32.32#ibcon#about to write, iclass 7, count 2 2006.196.07:36:32.32#ibcon#wrote, iclass 7, count 2 2006.196.07:36:32.32#ibcon#about to read 3, iclass 7, count 2 2006.196.07:36:32.34#ibcon#read 3, iclass 7, count 2 2006.196.07:36:32.34#ibcon#about to read 4, iclass 7, count 2 2006.196.07:36:32.34#ibcon#read 4, iclass 7, count 2 2006.196.07:36:32.34#ibcon#about to read 5, iclass 7, count 2 2006.196.07:36:32.34#ibcon#read 5, iclass 7, count 2 2006.196.07:36:32.34#ibcon#about to read 6, iclass 7, count 2 2006.196.07:36:32.34#ibcon#read 6, iclass 7, count 2 2006.196.07:36:32.34#ibcon#end of sib2, iclass 7, count 2 2006.196.07:36:32.34#ibcon#*mode == 0, iclass 7, count 2 2006.196.07:36:32.34#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.196.07:36:32.34#ibcon#[27=AT06-04\r\n] 2006.196.07:36:32.34#ibcon#*before write, iclass 7, count 2 2006.196.07:36:32.34#ibcon#enter sib2, iclass 7, count 2 2006.196.07:36:32.34#ibcon#flushed, iclass 7, count 2 2006.196.07:36:32.34#ibcon#about to write, iclass 7, count 2 2006.196.07:36:32.34#ibcon#wrote, iclass 7, count 2 2006.196.07:36:32.34#ibcon#about to read 3, iclass 7, count 2 2006.196.07:36:32.37#ibcon#read 3, iclass 7, count 2 2006.196.07:36:32.37#ibcon#about to read 4, iclass 7, count 2 2006.196.07:36:32.37#ibcon#read 4, iclass 7, count 2 2006.196.07:36:32.37#ibcon#about to read 5, iclass 7, count 2 2006.196.07:36:32.37#ibcon#read 5, iclass 7, count 2 2006.196.07:36:32.37#ibcon#about to read 6, iclass 7, count 2 2006.196.07:36:32.37#ibcon#read 6, iclass 7, count 2 2006.196.07:36:32.37#ibcon#end of sib2, iclass 7, count 2 2006.196.07:36:32.37#ibcon#*after write, iclass 7, count 2 2006.196.07:36:32.37#ibcon#*before return 0, iclass 7, count 2 2006.196.07:36:32.37#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.196.07:36:32.37#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.196.07:36:32.37#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.196.07:36:32.37#ibcon#ireg 7 cls_cnt 0 2006.196.07:36:32.37#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.196.07:36:32.49#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.196.07:36:32.49#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.196.07:36:32.49#ibcon#enter wrdev, iclass 7, count 0 2006.196.07:36:32.49#ibcon#first serial, iclass 7, count 0 2006.196.07:36:32.49#ibcon#enter sib2, iclass 7, count 0 2006.196.07:36:32.49#ibcon#flushed, iclass 7, count 0 2006.196.07:36:32.49#ibcon#about to write, iclass 7, count 0 2006.196.07:36:32.49#ibcon#wrote, iclass 7, count 0 2006.196.07:36:32.49#ibcon#about to read 3, iclass 7, count 0 2006.196.07:36:32.51#ibcon#read 3, iclass 7, count 0 2006.196.07:36:32.51#ibcon#about to read 4, iclass 7, count 0 2006.196.07:36:32.51#ibcon#read 4, iclass 7, count 0 2006.196.07:36:32.51#ibcon#about to read 5, iclass 7, count 0 2006.196.07:36:32.51#ibcon#read 5, iclass 7, count 0 2006.196.07:36:32.51#ibcon#about to read 6, iclass 7, count 0 2006.196.07:36:32.51#ibcon#read 6, iclass 7, count 0 2006.196.07:36:32.51#ibcon#end of sib2, iclass 7, count 0 2006.196.07:36:32.51#ibcon#*mode == 0, iclass 7, count 0 2006.196.07:36:32.51#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.196.07:36:32.51#ibcon#[27=USB\r\n] 2006.196.07:36:32.51#ibcon#*before write, iclass 7, count 0 2006.196.07:36:32.51#ibcon#enter sib2, iclass 7, count 0 2006.196.07:36:32.51#ibcon#flushed, iclass 7, count 0 2006.196.07:36:32.51#ibcon#about to write, iclass 7, count 0 2006.196.07:36:32.51#ibcon#wrote, iclass 7, count 0 2006.196.07:36:32.51#ibcon#about to read 3, iclass 7, count 0 2006.196.07:36:32.54#ibcon#read 3, iclass 7, count 0 2006.196.07:36:32.54#ibcon#about to read 4, iclass 7, count 0 2006.196.07:36:32.54#ibcon#read 4, iclass 7, count 0 2006.196.07:36:32.54#ibcon#about to read 5, iclass 7, count 0 2006.196.07:36:32.54#ibcon#read 5, iclass 7, count 0 2006.196.07:36:32.54#ibcon#about to read 6, iclass 7, count 0 2006.196.07:36:32.54#ibcon#read 6, iclass 7, count 0 2006.196.07:36:32.54#ibcon#end of sib2, iclass 7, count 0 2006.196.07:36:32.54#ibcon#*after write, iclass 7, count 0 2006.196.07:36:32.54#ibcon#*before return 0, iclass 7, count 0 2006.196.07:36:32.54#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.196.07:36:32.54#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.196.07:36:32.54#ibcon#about to clear, iclass 7 cls_cnt 0 2006.196.07:36:32.54#ibcon#cleared, iclass 7 cls_cnt 0 2006.196.07:36:32.54$vc4f8/vabw=wide 2006.196.07:36:32.54#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.196.07:36:32.54#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.196.07:36:32.54#ibcon#ireg 8 cls_cnt 0 2006.196.07:36:32.54#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.196.07:36:32.54#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.196.07:36:32.54#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.196.07:36:32.54#ibcon#enter wrdev, iclass 11, count 0 2006.196.07:36:32.54#ibcon#first serial, iclass 11, count 0 2006.196.07:36:32.54#ibcon#enter sib2, iclass 11, count 0 2006.196.07:36:32.54#ibcon#flushed, iclass 11, count 0 2006.196.07:36:32.54#ibcon#about to write, iclass 11, count 0 2006.196.07:36:32.54#ibcon#wrote, iclass 11, count 0 2006.196.07:36:32.54#ibcon#about to read 3, iclass 11, count 0 2006.196.07:36:32.56#ibcon#read 3, iclass 11, count 0 2006.196.07:36:32.56#ibcon#about to read 4, iclass 11, count 0 2006.196.07:36:32.56#ibcon#read 4, iclass 11, count 0 2006.196.07:36:32.56#ibcon#about to read 5, iclass 11, count 0 2006.196.07:36:32.56#ibcon#read 5, iclass 11, count 0 2006.196.07:36:32.56#ibcon#about to read 6, iclass 11, count 0 2006.196.07:36:32.56#ibcon#read 6, iclass 11, count 0 2006.196.07:36:32.56#ibcon#end of sib2, iclass 11, count 0 2006.196.07:36:32.56#ibcon#*mode == 0, iclass 11, count 0 2006.196.07:36:32.56#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.196.07:36:32.56#ibcon#[25=BW32\r\n] 2006.196.07:36:32.56#ibcon#*before write, iclass 11, count 0 2006.196.07:36:32.56#ibcon#enter sib2, iclass 11, count 0 2006.196.07:36:32.56#ibcon#flushed, iclass 11, count 0 2006.196.07:36:32.56#ibcon#about to write, iclass 11, count 0 2006.196.07:36:32.56#ibcon#wrote, iclass 11, count 0 2006.196.07:36:32.56#ibcon#about to read 3, iclass 11, count 0 2006.196.07:36:32.59#ibcon#read 3, iclass 11, count 0 2006.196.07:36:32.59#ibcon#about to read 4, iclass 11, count 0 2006.196.07:36:32.59#ibcon#read 4, iclass 11, count 0 2006.196.07:36:32.59#ibcon#about to read 5, iclass 11, count 0 2006.196.07:36:32.59#ibcon#read 5, iclass 11, count 0 2006.196.07:36:32.59#ibcon#about to read 6, iclass 11, count 0 2006.196.07:36:32.59#ibcon#read 6, iclass 11, count 0 2006.196.07:36:32.59#ibcon#end of sib2, iclass 11, count 0 2006.196.07:36:32.59#ibcon#*after write, iclass 11, count 0 2006.196.07:36:32.59#ibcon#*before return 0, iclass 11, count 0 2006.196.07:36:32.59#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.196.07:36:32.59#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.196.07:36:32.59#ibcon#about to clear, iclass 11 cls_cnt 0 2006.196.07:36:32.59#ibcon#cleared, iclass 11 cls_cnt 0 2006.196.07:36:32.59$vc4f8/vbbw=wide 2006.196.07:36:32.59#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.196.07:36:32.59#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.196.07:36:32.59#ibcon#ireg 8 cls_cnt 0 2006.196.07:36:32.59#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.196.07:36:32.66#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.196.07:36:32.66#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.196.07:36:32.66#ibcon#enter wrdev, iclass 13, count 0 2006.196.07:36:32.66#ibcon#first serial, iclass 13, count 0 2006.196.07:36:32.66#ibcon#enter sib2, iclass 13, count 0 2006.196.07:36:32.66#ibcon#flushed, iclass 13, count 0 2006.196.07:36:32.66#ibcon#about to write, iclass 13, count 0 2006.196.07:36:32.66#ibcon#wrote, iclass 13, count 0 2006.196.07:36:32.66#ibcon#about to read 3, iclass 13, count 0 2006.196.07:36:32.68#ibcon#read 3, iclass 13, count 0 2006.196.07:36:32.68#ibcon#about to read 4, iclass 13, count 0 2006.196.07:36:32.68#ibcon#read 4, iclass 13, count 0 2006.196.07:36:32.68#ibcon#about to read 5, iclass 13, count 0 2006.196.07:36:32.68#ibcon#read 5, iclass 13, count 0 2006.196.07:36:32.68#ibcon#about to read 6, iclass 13, count 0 2006.196.07:36:32.68#ibcon#read 6, iclass 13, count 0 2006.196.07:36:32.68#ibcon#end of sib2, iclass 13, count 0 2006.196.07:36:32.68#ibcon#*mode == 0, iclass 13, count 0 2006.196.07:36:32.68#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.196.07:36:32.68#ibcon#[27=BW32\r\n] 2006.196.07:36:32.68#ibcon#*before write, iclass 13, count 0 2006.196.07:36:32.68#ibcon#enter sib2, iclass 13, count 0 2006.196.07:36:32.68#ibcon#flushed, iclass 13, count 0 2006.196.07:36:32.68#ibcon#about to write, iclass 13, count 0 2006.196.07:36:32.68#ibcon#wrote, iclass 13, count 0 2006.196.07:36:32.68#ibcon#about to read 3, iclass 13, count 0 2006.196.07:36:32.71#ibcon#read 3, iclass 13, count 0 2006.196.07:36:32.71#ibcon#about to read 4, iclass 13, count 0 2006.196.07:36:32.71#ibcon#read 4, iclass 13, count 0 2006.196.07:36:32.71#ibcon#about to read 5, iclass 13, count 0 2006.196.07:36:32.71#ibcon#read 5, iclass 13, count 0 2006.196.07:36:32.71#ibcon#about to read 6, iclass 13, count 0 2006.196.07:36:32.71#ibcon#read 6, iclass 13, count 0 2006.196.07:36:32.71#ibcon#end of sib2, iclass 13, count 0 2006.196.07:36:32.71#ibcon#*after write, iclass 13, count 0 2006.196.07:36:32.71#ibcon#*before return 0, iclass 13, count 0 2006.196.07:36:32.71#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.196.07:36:32.71#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.196.07:36:32.71#ibcon#about to clear, iclass 13 cls_cnt 0 2006.196.07:36:32.71#ibcon#cleared, iclass 13 cls_cnt 0 2006.196.07:36:32.71$4f8m12a/ifd4f 2006.196.07:36:32.71$ifd4f/lo= 2006.196.07:36:32.71$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.196.07:36:32.71$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.196.07:36:32.71$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.196.07:36:32.71$ifd4f/patch= 2006.196.07:36:32.71$ifd4f/patch=lo1,a1,a2,a3,a4 2006.196.07:36:32.71$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.196.07:36:32.71$ifd4f/patch=lo3,a5,a6,a7,a8 2006.196.07:36:32.71$4f8m12a/"form=m,16.000,1:2 2006.196.07:36:32.71$4f8m12a/"tpicd 2006.196.07:36:32.71$4f8m12a/echo=off 2006.196.07:36:32.71$4f8m12a/xlog=off 2006.196.07:36:32.71:!2006.196.07:37:00 2006.196.07:36:46.14#trakl#Source acquired 2006.196.07:36:48.14#flagr#flagr/antenna,acquired 2006.196.07:37:00.00:preob 2006.196.07:37:01.14/onsource/TRACKING 2006.196.07:37:01.14:!2006.196.07:37:10 2006.196.07:37:10.00:data_valid=on 2006.196.07:37:10.00:midob 2006.196.07:37:10.14/onsource/TRACKING 2006.196.07:37:10.14/wx/30.10,1004.0,86 2006.196.07:37:10.22/cable/+6.3329E-03 2006.196.07:37:11.31/va/01,08,usb,yes,35,37 2006.196.07:37:11.31/va/02,07,usb,yes,35,36 2006.196.07:37:11.31/va/03,06,usb,yes,36,37 2006.196.07:37:11.31/va/04,07,usb,yes,36,38 2006.196.07:37:11.31/va/05,07,usb,yes,38,40 2006.196.07:37:11.31/va/06,06,usb,yes,37,37 2006.196.07:37:11.31/va/07,06,usb,yes,37,37 2006.196.07:37:11.31/va/08,07,usb,yes,35,35 2006.196.07:37:11.54/valo/01,532.99,yes,locked 2006.196.07:37:11.54/valo/02,572.99,yes,locked 2006.196.07:37:11.54/valo/03,672.99,yes,locked 2006.196.07:37:11.54/valo/04,832.99,yes,locked 2006.196.07:37:11.54/valo/05,652.99,yes,locked 2006.196.07:37:11.54/valo/06,772.99,yes,locked 2006.196.07:37:11.54/valo/07,832.99,yes,locked 2006.196.07:37:11.54/valo/08,852.99,yes,locked 2006.196.07:37:12.63/vb/01,04,usb,yes,31,30 2006.196.07:37:12.63/vb/02,04,usb,yes,33,35 2006.196.07:37:12.63/vb/03,04,usb,yes,29,33 2006.196.07:37:12.63/vb/04,04,usb,yes,30,31 2006.196.07:37:12.63/vb/05,04,usb,yes,29,33 2006.196.07:37:12.63/vb/06,04,usb,yes,30,33 2006.196.07:37:12.63/vb/07,04,usb,yes,32,32 2006.196.07:37:12.63/vb/08,04,usb,yes,29,33 2006.196.07:37:12.86/vblo/01,632.99,yes,locked 2006.196.07:37:12.86/vblo/02,640.99,yes,locked 2006.196.07:37:12.86/vblo/03,656.99,yes,locked 2006.196.07:37:12.86/vblo/04,712.99,yes,locked 2006.196.07:37:12.86/vblo/05,744.99,yes,locked 2006.196.07:37:12.86/vblo/06,752.99,yes,locked 2006.196.07:37:12.86/vblo/07,734.99,yes,locked 2006.196.07:37:12.86/vblo/08,744.99,yes,locked 2006.196.07:37:13.01/vabw/8 2006.196.07:37:13.16/vbbw/8 2006.196.07:37:13.27/xfe/off,on,14.7 2006.196.07:37:13.66/ifatt/23,28,28,28 2006.196.07:37:14.06/fmout-gps/S +3.35E-07 2006.196.07:37:14.13:!2006.196.07:38:10 2006.196.07:38:10.00:data_valid=off 2006.196.07:38:10.00:postob 2006.196.07:38:10.22/cable/+6.3323E-03 2006.196.07:38:10.22/wx/30.06,1004.0,86 2006.196.07:38:11.06/fmout-gps/S +3.36E-07 2006.196.07:38:11.06:scan_name=196-0739,k06196,60 2006.196.07:38:11.06:source=0602+673,060752.67,672055.4,2000.0,ccw 2006.196.07:38:11.14#flagr#flagr/antenna,new-source 2006.196.07:38:12.14:checkk5 2006.196.07:38:12.51/chk_autoobs//k5ts1/ autoobs is running! 2006.196.07:38:12.88/chk_autoobs//k5ts2/ autoobs is running! 2006.196.07:38:13.26/chk_autoobs//k5ts3/ autoobs is running! 2006.196.07:38:13.64/chk_autoobs//k5ts4/ autoobs is running! 2006.196.07:38:14.01/chk_obsdata//k5ts1/T1960737??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.07:38:14.39/chk_obsdata//k5ts2/T1960737??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.07:38:14.76/chk_obsdata//k5ts3/T1960737??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.07:38:15.13/chk_obsdata//k5ts4/T1960737??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.07:38:15.83/k5log//k5ts1_log_newline 2006.196.07:38:16.53/k5log//k5ts2_log_newline 2006.196.07:38:17.21/k5log//k5ts3_log_newline 2006.196.07:38:17.90/k5log//k5ts4_log_newline 2006.196.07:38:17.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.196.07:38:17.92:4f8m12a=1 2006.196.07:38:17.92$4f8m12a/echo=on 2006.196.07:38:17.92$4f8m12a/pcalon 2006.196.07:38:17.92$pcalon/"no phase cal control is implemented here 2006.196.07:38:17.92$4f8m12a/"tpicd=stop 2006.196.07:38:17.92$4f8m12a/vc4f8 2006.196.07:38:17.92$vc4f8/valo=1,532.99 2006.196.07:38:17.93#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.196.07:38:17.93#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.196.07:38:17.93#ibcon#ireg 17 cls_cnt 0 2006.196.07:38:17.93#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.196.07:38:17.93#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.196.07:38:17.93#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.196.07:38:17.93#ibcon#enter wrdev, iclass 20, count 0 2006.196.07:38:17.93#ibcon#first serial, iclass 20, count 0 2006.196.07:38:17.93#ibcon#enter sib2, iclass 20, count 0 2006.196.07:38:17.93#ibcon#flushed, iclass 20, count 0 2006.196.07:38:17.93#ibcon#about to write, iclass 20, count 0 2006.196.07:38:17.93#ibcon#wrote, iclass 20, count 0 2006.196.07:38:17.93#ibcon#about to read 3, iclass 20, count 0 2006.196.07:38:17.97#ibcon#read 3, iclass 20, count 0 2006.196.07:38:17.97#ibcon#about to read 4, iclass 20, count 0 2006.196.07:38:17.97#ibcon#read 4, iclass 20, count 0 2006.196.07:38:17.97#ibcon#about to read 5, iclass 20, count 0 2006.196.07:38:17.97#ibcon#read 5, iclass 20, count 0 2006.196.07:38:17.97#ibcon#about to read 6, iclass 20, count 0 2006.196.07:38:17.97#ibcon#read 6, iclass 20, count 0 2006.196.07:38:17.97#ibcon#end of sib2, iclass 20, count 0 2006.196.07:38:17.97#ibcon#*mode == 0, iclass 20, count 0 2006.196.07:38:17.97#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.196.07:38:17.97#ibcon#[26=FRQ=01,532.99\r\n] 2006.196.07:38:17.97#ibcon#*before write, iclass 20, count 0 2006.196.07:38:17.97#ibcon#enter sib2, iclass 20, count 0 2006.196.07:38:17.97#ibcon#flushed, iclass 20, count 0 2006.196.07:38:17.97#ibcon#about to write, iclass 20, count 0 2006.196.07:38:17.97#ibcon#wrote, iclass 20, count 0 2006.196.07:38:17.97#ibcon#about to read 3, iclass 20, count 0 2006.196.07:38:18.02#ibcon#read 3, iclass 20, count 0 2006.196.07:38:18.02#ibcon#about to read 4, iclass 20, count 0 2006.196.07:38:18.02#ibcon#read 4, iclass 20, count 0 2006.196.07:38:18.02#ibcon#about to read 5, iclass 20, count 0 2006.196.07:38:18.02#ibcon#read 5, iclass 20, count 0 2006.196.07:38:18.02#ibcon#about to read 6, iclass 20, count 0 2006.196.07:38:18.02#ibcon#read 6, iclass 20, count 0 2006.196.07:38:18.02#ibcon#end of sib2, iclass 20, count 0 2006.196.07:38:18.02#ibcon#*after write, iclass 20, count 0 2006.196.07:38:18.02#ibcon#*before return 0, iclass 20, count 0 2006.196.07:38:18.02#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.196.07:38:18.02#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.196.07:38:18.02#ibcon#about to clear, iclass 20 cls_cnt 0 2006.196.07:38:18.02#ibcon#cleared, iclass 20 cls_cnt 0 2006.196.07:38:18.02$vc4f8/va=1,8 2006.196.07:38:18.02#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.196.07:38:18.02#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.196.07:38:18.02#ibcon#ireg 11 cls_cnt 2 2006.196.07:38:18.02#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.196.07:38:18.02#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.196.07:38:18.02#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.196.07:38:18.02#ibcon#enter wrdev, iclass 22, count 2 2006.196.07:38:18.02#ibcon#first serial, iclass 22, count 2 2006.196.07:38:18.02#ibcon#enter sib2, iclass 22, count 2 2006.196.07:38:18.02#ibcon#flushed, iclass 22, count 2 2006.196.07:38:18.02#ibcon#about to write, iclass 22, count 2 2006.196.07:38:18.02#ibcon#wrote, iclass 22, count 2 2006.196.07:38:18.02#ibcon#about to read 3, iclass 22, count 2 2006.196.07:38:18.04#ibcon#read 3, iclass 22, count 2 2006.196.07:38:18.04#ibcon#about to read 4, iclass 22, count 2 2006.196.07:38:18.04#ibcon#read 4, iclass 22, count 2 2006.196.07:38:18.04#ibcon#about to read 5, iclass 22, count 2 2006.196.07:38:18.04#ibcon#read 5, iclass 22, count 2 2006.196.07:38:18.04#ibcon#about to read 6, iclass 22, count 2 2006.196.07:38:18.04#ibcon#read 6, iclass 22, count 2 2006.196.07:38:18.04#ibcon#end of sib2, iclass 22, count 2 2006.196.07:38:18.04#ibcon#*mode == 0, iclass 22, count 2 2006.196.07:38:18.04#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.196.07:38:18.04#ibcon#[25=AT01-08\r\n] 2006.196.07:38:18.04#ibcon#*before write, iclass 22, count 2 2006.196.07:38:18.04#ibcon#enter sib2, iclass 22, count 2 2006.196.07:38:18.04#ibcon#flushed, iclass 22, count 2 2006.196.07:38:18.04#ibcon#about to write, iclass 22, count 2 2006.196.07:38:18.04#ibcon#wrote, iclass 22, count 2 2006.196.07:38:18.04#ibcon#about to read 3, iclass 22, count 2 2006.196.07:38:18.07#ibcon#read 3, iclass 22, count 2 2006.196.07:38:18.07#ibcon#about to read 4, iclass 22, count 2 2006.196.07:38:18.07#ibcon#read 4, iclass 22, count 2 2006.196.07:38:18.07#ibcon#about to read 5, iclass 22, count 2 2006.196.07:38:18.07#ibcon#read 5, iclass 22, count 2 2006.196.07:38:18.07#ibcon#about to read 6, iclass 22, count 2 2006.196.07:38:18.07#ibcon#read 6, iclass 22, count 2 2006.196.07:38:18.07#ibcon#end of sib2, iclass 22, count 2 2006.196.07:38:18.07#ibcon#*after write, iclass 22, count 2 2006.196.07:38:18.07#ibcon#*before return 0, iclass 22, count 2 2006.196.07:38:18.07#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.196.07:38:18.07#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.196.07:38:18.07#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.196.07:38:18.07#ibcon#ireg 7 cls_cnt 0 2006.196.07:38:18.07#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.196.07:38:18.19#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.196.07:38:18.19#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.196.07:38:18.19#ibcon#enter wrdev, iclass 22, count 0 2006.196.07:38:18.19#ibcon#first serial, iclass 22, count 0 2006.196.07:38:18.19#ibcon#enter sib2, iclass 22, count 0 2006.196.07:38:18.19#ibcon#flushed, iclass 22, count 0 2006.196.07:38:18.19#ibcon#about to write, iclass 22, count 0 2006.196.07:38:18.19#ibcon#wrote, iclass 22, count 0 2006.196.07:38:18.19#ibcon#about to read 3, iclass 22, count 0 2006.196.07:38:18.21#ibcon#read 3, iclass 22, count 0 2006.196.07:38:18.21#ibcon#about to read 4, iclass 22, count 0 2006.196.07:38:18.21#ibcon#read 4, iclass 22, count 0 2006.196.07:38:18.21#ibcon#about to read 5, iclass 22, count 0 2006.196.07:38:18.21#ibcon#read 5, iclass 22, count 0 2006.196.07:38:18.21#ibcon#about to read 6, iclass 22, count 0 2006.196.07:38:18.21#ibcon#read 6, iclass 22, count 0 2006.196.07:38:18.21#ibcon#end of sib2, iclass 22, count 0 2006.196.07:38:18.21#ibcon#*mode == 0, iclass 22, count 0 2006.196.07:38:18.21#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.196.07:38:18.21#ibcon#[25=USB\r\n] 2006.196.07:38:18.21#ibcon#*before write, iclass 22, count 0 2006.196.07:38:18.21#ibcon#enter sib2, iclass 22, count 0 2006.196.07:38:18.21#ibcon#flushed, iclass 22, count 0 2006.196.07:38:18.21#ibcon#about to write, iclass 22, count 0 2006.196.07:38:18.21#ibcon#wrote, iclass 22, count 0 2006.196.07:38:18.21#ibcon#about to read 3, iclass 22, count 0 2006.196.07:38:18.24#ibcon#read 3, iclass 22, count 0 2006.196.07:38:18.24#ibcon#about to read 4, iclass 22, count 0 2006.196.07:38:18.24#ibcon#read 4, iclass 22, count 0 2006.196.07:38:18.24#ibcon#about to read 5, iclass 22, count 0 2006.196.07:38:18.24#ibcon#read 5, iclass 22, count 0 2006.196.07:38:18.24#ibcon#about to read 6, iclass 22, count 0 2006.196.07:38:18.24#ibcon#read 6, iclass 22, count 0 2006.196.07:38:18.24#ibcon#end of sib2, iclass 22, count 0 2006.196.07:38:18.24#ibcon#*after write, iclass 22, count 0 2006.196.07:38:18.24#ibcon#*before return 0, iclass 22, count 0 2006.196.07:38:18.24#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.196.07:38:18.24#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.196.07:38:18.24#ibcon#about to clear, iclass 22 cls_cnt 0 2006.196.07:38:18.24#ibcon#cleared, iclass 22 cls_cnt 0 2006.196.07:38:18.24$vc4f8/valo=2,572.99 2006.196.07:38:18.24#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.196.07:38:18.24#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.196.07:38:18.24#ibcon#ireg 17 cls_cnt 0 2006.196.07:38:18.24#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.196.07:38:18.24#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.196.07:38:18.24#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.196.07:38:18.24#ibcon#enter wrdev, iclass 24, count 0 2006.196.07:38:18.24#ibcon#first serial, iclass 24, count 0 2006.196.07:38:18.24#ibcon#enter sib2, iclass 24, count 0 2006.196.07:38:18.24#ibcon#flushed, iclass 24, count 0 2006.196.07:38:18.24#ibcon#about to write, iclass 24, count 0 2006.196.07:38:18.24#ibcon#wrote, iclass 24, count 0 2006.196.07:38:18.24#ibcon#about to read 3, iclass 24, count 0 2006.196.07:38:18.26#ibcon#read 3, iclass 24, count 0 2006.196.07:38:18.26#ibcon#about to read 4, iclass 24, count 0 2006.196.07:38:18.26#ibcon#read 4, iclass 24, count 0 2006.196.07:38:18.26#ibcon#about to read 5, iclass 24, count 0 2006.196.07:38:18.26#ibcon#read 5, iclass 24, count 0 2006.196.07:38:18.26#ibcon#about to read 6, iclass 24, count 0 2006.196.07:38:18.26#ibcon#read 6, iclass 24, count 0 2006.196.07:38:18.26#ibcon#end of sib2, iclass 24, count 0 2006.196.07:38:18.26#ibcon#*mode == 0, iclass 24, count 0 2006.196.07:38:18.26#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.196.07:38:18.26#ibcon#[26=FRQ=02,572.99\r\n] 2006.196.07:38:18.26#ibcon#*before write, iclass 24, count 0 2006.196.07:38:18.26#ibcon#enter sib2, iclass 24, count 0 2006.196.07:38:18.26#ibcon#flushed, iclass 24, count 0 2006.196.07:38:18.26#ibcon#about to write, iclass 24, count 0 2006.196.07:38:18.26#ibcon#wrote, iclass 24, count 0 2006.196.07:38:18.26#ibcon#about to read 3, iclass 24, count 0 2006.196.07:38:18.30#ibcon#read 3, iclass 24, count 0 2006.196.07:38:18.30#ibcon#about to read 4, iclass 24, count 0 2006.196.07:38:18.30#ibcon#read 4, iclass 24, count 0 2006.196.07:38:18.30#ibcon#about to read 5, iclass 24, count 0 2006.196.07:38:18.30#ibcon#read 5, iclass 24, count 0 2006.196.07:38:18.30#ibcon#about to read 6, iclass 24, count 0 2006.196.07:38:18.30#ibcon#read 6, iclass 24, count 0 2006.196.07:38:18.30#ibcon#end of sib2, iclass 24, count 0 2006.196.07:38:18.30#ibcon#*after write, iclass 24, count 0 2006.196.07:38:18.30#ibcon#*before return 0, iclass 24, count 0 2006.196.07:38:18.30#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.196.07:38:18.30#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.196.07:38:18.30#ibcon#about to clear, iclass 24 cls_cnt 0 2006.196.07:38:18.30#ibcon#cleared, iclass 24 cls_cnt 0 2006.196.07:38:18.30$vc4f8/va=2,7 2006.196.07:38:18.30#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.196.07:38:18.30#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.196.07:38:18.30#ibcon#ireg 11 cls_cnt 2 2006.196.07:38:18.30#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.196.07:38:18.36#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.196.07:38:18.36#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.196.07:38:18.36#ibcon#enter wrdev, iclass 26, count 2 2006.196.07:38:18.36#ibcon#first serial, iclass 26, count 2 2006.196.07:38:18.36#ibcon#enter sib2, iclass 26, count 2 2006.196.07:38:18.36#ibcon#flushed, iclass 26, count 2 2006.196.07:38:18.36#ibcon#about to write, iclass 26, count 2 2006.196.07:38:18.36#ibcon#wrote, iclass 26, count 2 2006.196.07:38:18.36#ibcon#about to read 3, iclass 26, count 2 2006.196.07:38:18.38#ibcon#read 3, iclass 26, count 2 2006.196.07:38:18.38#ibcon#about to read 4, iclass 26, count 2 2006.196.07:38:18.38#ibcon#read 4, iclass 26, count 2 2006.196.07:38:18.38#ibcon#about to read 5, iclass 26, count 2 2006.196.07:38:18.38#ibcon#read 5, iclass 26, count 2 2006.196.07:38:18.38#ibcon#about to read 6, iclass 26, count 2 2006.196.07:38:18.38#ibcon#read 6, iclass 26, count 2 2006.196.07:38:18.38#ibcon#end of sib2, iclass 26, count 2 2006.196.07:38:18.38#ibcon#*mode == 0, iclass 26, count 2 2006.196.07:38:18.38#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.196.07:38:18.38#ibcon#[25=AT02-07\r\n] 2006.196.07:38:18.38#ibcon#*before write, iclass 26, count 2 2006.196.07:38:18.38#ibcon#enter sib2, iclass 26, count 2 2006.196.07:38:18.38#ibcon#flushed, iclass 26, count 2 2006.196.07:38:18.38#ibcon#about to write, iclass 26, count 2 2006.196.07:38:18.38#ibcon#wrote, iclass 26, count 2 2006.196.07:38:18.38#ibcon#about to read 3, iclass 26, count 2 2006.196.07:38:18.41#ibcon#read 3, iclass 26, count 2 2006.196.07:38:18.41#ibcon#about to read 4, iclass 26, count 2 2006.196.07:38:18.41#ibcon#read 4, iclass 26, count 2 2006.196.07:38:18.41#ibcon#about to read 5, iclass 26, count 2 2006.196.07:38:18.41#ibcon#read 5, iclass 26, count 2 2006.196.07:38:18.41#ibcon#about to read 6, iclass 26, count 2 2006.196.07:38:18.41#ibcon#read 6, iclass 26, count 2 2006.196.07:38:18.41#ibcon#end of sib2, iclass 26, count 2 2006.196.07:38:18.41#ibcon#*after write, iclass 26, count 2 2006.196.07:38:18.41#ibcon#*before return 0, iclass 26, count 2 2006.196.07:38:18.41#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.196.07:38:18.41#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.196.07:38:18.41#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.196.07:38:18.41#ibcon#ireg 7 cls_cnt 0 2006.196.07:38:18.41#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.196.07:38:18.53#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.196.07:38:18.53#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.196.07:38:18.53#ibcon#enter wrdev, iclass 26, count 0 2006.196.07:38:18.53#ibcon#first serial, iclass 26, count 0 2006.196.07:38:18.53#ibcon#enter sib2, iclass 26, count 0 2006.196.07:38:18.53#ibcon#flushed, iclass 26, count 0 2006.196.07:38:18.53#ibcon#about to write, iclass 26, count 0 2006.196.07:38:18.53#ibcon#wrote, iclass 26, count 0 2006.196.07:38:18.53#ibcon#about to read 3, iclass 26, count 0 2006.196.07:38:18.55#ibcon#read 3, iclass 26, count 0 2006.196.07:38:18.55#ibcon#about to read 4, iclass 26, count 0 2006.196.07:38:18.55#ibcon#read 4, iclass 26, count 0 2006.196.07:38:18.55#ibcon#about to read 5, iclass 26, count 0 2006.196.07:38:18.55#ibcon#read 5, iclass 26, count 0 2006.196.07:38:18.55#ibcon#about to read 6, iclass 26, count 0 2006.196.07:38:18.55#ibcon#read 6, iclass 26, count 0 2006.196.07:38:18.55#ibcon#end of sib2, iclass 26, count 0 2006.196.07:38:18.55#ibcon#*mode == 0, iclass 26, count 0 2006.196.07:38:18.55#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.196.07:38:18.55#ibcon#[25=USB\r\n] 2006.196.07:38:18.55#ibcon#*before write, iclass 26, count 0 2006.196.07:38:18.55#ibcon#enter sib2, iclass 26, count 0 2006.196.07:38:18.55#ibcon#flushed, iclass 26, count 0 2006.196.07:38:18.55#ibcon#about to write, iclass 26, count 0 2006.196.07:38:18.55#ibcon#wrote, iclass 26, count 0 2006.196.07:38:18.55#ibcon#about to read 3, iclass 26, count 0 2006.196.07:38:18.58#ibcon#read 3, iclass 26, count 0 2006.196.07:38:18.58#ibcon#about to read 4, iclass 26, count 0 2006.196.07:38:18.58#ibcon#read 4, iclass 26, count 0 2006.196.07:38:18.58#ibcon#about to read 5, iclass 26, count 0 2006.196.07:38:18.58#ibcon#read 5, iclass 26, count 0 2006.196.07:38:18.58#ibcon#about to read 6, iclass 26, count 0 2006.196.07:38:18.58#ibcon#read 6, iclass 26, count 0 2006.196.07:38:18.58#ibcon#end of sib2, iclass 26, count 0 2006.196.07:38:18.58#ibcon#*after write, iclass 26, count 0 2006.196.07:38:18.58#ibcon#*before return 0, iclass 26, count 0 2006.196.07:38:18.58#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.196.07:38:18.58#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.196.07:38:18.58#ibcon#about to clear, iclass 26 cls_cnt 0 2006.196.07:38:18.58#ibcon#cleared, iclass 26 cls_cnt 0 2006.196.07:38:18.58$vc4f8/valo=3,672.99 2006.196.07:38:18.58#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.196.07:38:18.58#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.196.07:38:18.58#ibcon#ireg 17 cls_cnt 0 2006.196.07:38:18.58#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.196.07:38:18.58#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.196.07:38:18.58#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.196.07:38:18.58#ibcon#enter wrdev, iclass 28, count 0 2006.196.07:38:18.58#ibcon#first serial, iclass 28, count 0 2006.196.07:38:18.58#ibcon#enter sib2, iclass 28, count 0 2006.196.07:38:18.58#ibcon#flushed, iclass 28, count 0 2006.196.07:38:18.58#ibcon#about to write, iclass 28, count 0 2006.196.07:38:18.58#ibcon#wrote, iclass 28, count 0 2006.196.07:38:18.58#ibcon#about to read 3, iclass 28, count 0 2006.196.07:38:18.60#ibcon#read 3, iclass 28, count 0 2006.196.07:38:18.60#ibcon#about to read 4, iclass 28, count 0 2006.196.07:38:18.60#ibcon#read 4, iclass 28, count 0 2006.196.07:38:18.60#ibcon#about to read 5, iclass 28, count 0 2006.196.07:38:18.60#ibcon#read 5, iclass 28, count 0 2006.196.07:38:18.60#ibcon#about to read 6, iclass 28, count 0 2006.196.07:38:18.60#ibcon#read 6, iclass 28, count 0 2006.196.07:38:18.60#ibcon#end of sib2, iclass 28, count 0 2006.196.07:38:18.60#ibcon#*mode == 0, iclass 28, count 0 2006.196.07:38:18.60#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.196.07:38:18.60#ibcon#[26=FRQ=03,672.99\r\n] 2006.196.07:38:18.60#ibcon#*before write, iclass 28, count 0 2006.196.07:38:18.60#ibcon#enter sib2, iclass 28, count 0 2006.196.07:38:18.60#ibcon#flushed, iclass 28, count 0 2006.196.07:38:18.60#ibcon#about to write, iclass 28, count 0 2006.196.07:38:18.60#ibcon#wrote, iclass 28, count 0 2006.196.07:38:18.60#ibcon#about to read 3, iclass 28, count 0 2006.196.07:38:18.65#ibcon#read 3, iclass 28, count 0 2006.196.07:38:18.65#ibcon#about to read 4, iclass 28, count 0 2006.196.07:38:18.65#ibcon#read 4, iclass 28, count 0 2006.196.07:38:18.65#ibcon#about to read 5, iclass 28, count 0 2006.196.07:38:18.65#ibcon#read 5, iclass 28, count 0 2006.196.07:38:18.65#ibcon#about to read 6, iclass 28, count 0 2006.196.07:38:18.65#ibcon#read 6, iclass 28, count 0 2006.196.07:38:18.65#ibcon#end of sib2, iclass 28, count 0 2006.196.07:38:18.65#ibcon#*after write, iclass 28, count 0 2006.196.07:38:18.65#ibcon#*before return 0, iclass 28, count 0 2006.196.07:38:18.65#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.196.07:38:18.65#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.196.07:38:18.65#ibcon#about to clear, iclass 28 cls_cnt 0 2006.196.07:38:18.65#ibcon#cleared, iclass 28 cls_cnt 0 2006.196.07:38:18.65$vc4f8/va=3,6 2006.196.07:38:18.65#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.196.07:38:18.65#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.196.07:38:18.65#ibcon#ireg 11 cls_cnt 2 2006.196.07:38:18.65#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.196.07:38:18.70#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.196.07:38:18.70#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.196.07:38:18.70#ibcon#enter wrdev, iclass 30, count 2 2006.196.07:38:18.70#ibcon#first serial, iclass 30, count 2 2006.196.07:38:18.70#ibcon#enter sib2, iclass 30, count 2 2006.196.07:38:18.70#ibcon#flushed, iclass 30, count 2 2006.196.07:38:18.70#ibcon#about to write, iclass 30, count 2 2006.196.07:38:18.70#ibcon#wrote, iclass 30, count 2 2006.196.07:38:18.70#ibcon#about to read 3, iclass 30, count 2 2006.196.07:38:18.72#ibcon#read 3, iclass 30, count 2 2006.196.07:38:18.72#ibcon#about to read 4, iclass 30, count 2 2006.196.07:38:18.72#ibcon#read 4, iclass 30, count 2 2006.196.07:38:18.72#ibcon#about to read 5, iclass 30, count 2 2006.196.07:38:18.72#ibcon#read 5, iclass 30, count 2 2006.196.07:38:18.72#ibcon#about to read 6, iclass 30, count 2 2006.196.07:38:18.72#ibcon#read 6, iclass 30, count 2 2006.196.07:38:18.72#ibcon#end of sib2, iclass 30, count 2 2006.196.07:38:18.72#ibcon#*mode == 0, iclass 30, count 2 2006.196.07:38:18.72#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.196.07:38:18.72#ibcon#[25=AT03-06\r\n] 2006.196.07:38:18.72#ibcon#*before write, iclass 30, count 2 2006.196.07:38:18.72#ibcon#enter sib2, iclass 30, count 2 2006.196.07:38:18.72#ibcon#flushed, iclass 30, count 2 2006.196.07:38:18.72#ibcon#about to write, iclass 30, count 2 2006.196.07:38:18.72#ibcon#wrote, iclass 30, count 2 2006.196.07:38:18.72#ibcon#about to read 3, iclass 30, count 2 2006.196.07:38:18.75#ibcon#read 3, iclass 30, count 2 2006.196.07:38:18.75#ibcon#about to read 4, iclass 30, count 2 2006.196.07:38:18.75#ibcon#read 4, iclass 30, count 2 2006.196.07:38:18.75#ibcon#about to read 5, iclass 30, count 2 2006.196.07:38:18.75#ibcon#read 5, iclass 30, count 2 2006.196.07:38:18.75#ibcon#about to read 6, iclass 30, count 2 2006.196.07:38:18.75#ibcon#read 6, iclass 30, count 2 2006.196.07:38:18.75#ibcon#end of sib2, iclass 30, count 2 2006.196.07:38:18.75#ibcon#*after write, iclass 30, count 2 2006.196.07:38:18.75#ibcon#*before return 0, iclass 30, count 2 2006.196.07:38:18.75#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.196.07:38:18.75#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.196.07:38:18.75#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.196.07:38:18.75#ibcon#ireg 7 cls_cnt 0 2006.196.07:38:18.75#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.196.07:38:18.87#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.196.07:38:18.87#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.196.07:38:18.87#ibcon#enter wrdev, iclass 30, count 0 2006.196.07:38:18.87#ibcon#first serial, iclass 30, count 0 2006.196.07:38:18.87#ibcon#enter sib2, iclass 30, count 0 2006.196.07:38:18.87#ibcon#flushed, iclass 30, count 0 2006.196.07:38:18.87#ibcon#about to write, iclass 30, count 0 2006.196.07:38:18.87#ibcon#wrote, iclass 30, count 0 2006.196.07:38:18.87#ibcon#about to read 3, iclass 30, count 0 2006.196.07:38:18.89#ibcon#read 3, iclass 30, count 0 2006.196.07:38:18.89#ibcon#about to read 4, iclass 30, count 0 2006.196.07:38:18.89#ibcon#read 4, iclass 30, count 0 2006.196.07:38:18.89#ibcon#about to read 5, iclass 30, count 0 2006.196.07:38:18.89#ibcon#read 5, iclass 30, count 0 2006.196.07:38:18.89#ibcon#about to read 6, iclass 30, count 0 2006.196.07:38:18.89#ibcon#read 6, iclass 30, count 0 2006.196.07:38:18.89#ibcon#end of sib2, iclass 30, count 0 2006.196.07:38:18.89#ibcon#*mode == 0, iclass 30, count 0 2006.196.07:38:18.89#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.196.07:38:18.89#ibcon#[25=USB\r\n] 2006.196.07:38:18.89#ibcon#*before write, iclass 30, count 0 2006.196.07:38:18.89#ibcon#enter sib2, iclass 30, count 0 2006.196.07:38:18.89#ibcon#flushed, iclass 30, count 0 2006.196.07:38:18.89#ibcon#about to write, iclass 30, count 0 2006.196.07:38:18.89#ibcon#wrote, iclass 30, count 0 2006.196.07:38:18.89#ibcon#about to read 3, iclass 30, count 0 2006.196.07:38:18.92#ibcon#read 3, iclass 30, count 0 2006.196.07:38:18.92#ibcon#about to read 4, iclass 30, count 0 2006.196.07:38:18.92#ibcon#read 4, iclass 30, count 0 2006.196.07:38:18.92#ibcon#about to read 5, iclass 30, count 0 2006.196.07:38:18.92#ibcon#read 5, iclass 30, count 0 2006.196.07:38:18.92#ibcon#about to read 6, iclass 30, count 0 2006.196.07:38:18.92#ibcon#read 6, iclass 30, count 0 2006.196.07:38:18.92#ibcon#end of sib2, iclass 30, count 0 2006.196.07:38:18.92#ibcon#*after write, iclass 30, count 0 2006.196.07:38:18.92#ibcon#*before return 0, iclass 30, count 0 2006.196.07:38:18.92#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.196.07:38:18.92#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.196.07:38:18.92#ibcon#about to clear, iclass 30 cls_cnt 0 2006.196.07:38:18.92#ibcon#cleared, iclass 30 cls_cnt 0 2006.196.07:38:18.92$vc4f8/valo=4,832.99 2006.196.07:38:18.92#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.196.07:38:18.92#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.196.07:38:18.92#ibcon#ireg 17 cls_cnt 0 2006.196.07:38:18.92#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.196.07:38:18.92#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.196.07:38:18.92#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.196.07:38:18.92#ibcon#enter wrdev, iclass 32, count 0 2006.196.07:38:18.92#ibcon#first serial, iclass 32, count 0 2006.196.07:38:18.92#ibcon#enter sib2, iclass 32, count 0 2006.196.07:38:18.92#ibcon#flushed, iclass 32, count 0 2006.196.07:38:18.92#ibcon#about to write, iclass 32, count 0 2006.196.07:38:18.92#ibcon#wrote, iclass 32, count 0 2006.196.07:38:18.92#ibcon#about to read 3, iclass 32, count 0 2006.196.07:38:18.94#ibcon#read 3, iclass 32, count 0 2006.196.07:38:18.94#ibcon#about to read 4, iclass 32, count 0 2006.196.07:38:18.94#ibcon#read 4, iclass 32, count 0 2006.196.07:38:18.94#ibcon#about to read 5, iclass 32, count 0 2006.196.07:38:18.94#ibcon#read 5, iclass 32, count 0 2006.196.07:38:18.94#ibcon#about to read 6, iclass 32, count 0 2006.196.07:38:18.94#ibcon#read 6, iclass 32, count 0 2006.196.07:38:18.94#ibcon#end of sib2, iclass 32, count 0 2006.196.07:38:18.94#ibcon#*mode == 0, iclass 32, count 0 2006.196.07:38:18.94#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.196.07:38:18.94#ibcon#[26=FRQ=04,832.99\r\n] 2006.196.07:38:18.94#ibcon#*before write, iclass 32, count 0 2006.196.07:38:18.94#ibcon#enter sib2, iclass 32, count 0 2006.196.07:38:18.94#ibcon#flushed, iclass 32, count 0 2006.196.07:38:18.94#ibcon#about to write, iclass 32, count 0 2006.196.07:38:18.94#ibcon#wrote, iclass 32, count 0 2006.196.07:38:18.94#ibcon#about to read 3, iclass 32, count 0 2006.196.07:38:18.98#ibcon#read 3, iclass 32, count 0 2006.196.07:38:18.98#ibcon#about to read 4, iclass 32, count 0 2006.196.07:38:18.98#ibcon#read 4, iclass 32, count 0 2006.196.07:38:18.98#ibcon#about to read 5, iclass 32, count 0 2006.196.07:38:18.98#ibcon#read 5, iclass 32, count 0 2006.196.07:38:18.98#ibcon#about to read 6, iclass 32, count 0 2006.196.07:38:18.98#ibcon#read 6, iclass 32, count 0 2006.196.07:38:18.98#ibcon#end of sib2, iclass 32, count 0 2006.196.07:38:18.98#ibcon#*after write, iclass 32, count 0 2006.196.07:38:18.98#ibcon#*before return 0, iclass 32, count 0 2006.196.07:38:18.98#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.196.07:38:18.98#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.196.07:38:18.98#ibcon#about to clear, iclass 32 cls_cnt 0 2006.196.07:38:18.98#ibcon#cleared, iclass 32 cls_cnt 0 2006.196.07:38:18.98$vc4f8/va=4,7 2006.196.07:38:18.98#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.196.07:38:18.98#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.196.07:38:18.98#ibcon#ireg 11 cls_cnt 2 2006.196.07:38:18.98#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.196.07:38:19.04#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.196.07:38:19.04#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.196.07:38:19.04#ibcon#enter wrdev, iclass 34, count 2 2006.196.07:38:19.04#ibcon#first serial, iclass 34, count 2 2006.196.07:38:19.04#ibcon#enter sib2, iclass 34, count 2 2006.196.07:38:19.04#ibcon#flushed, iclass 34, count 2 2006.196.07:38:19.04#ibcon#about to write, iclass 34, count 2 2006.196.07:38:19.04#ibcon#wrote, iclass 34, count 2 2006.196.07:38:19.04#ibcon#about to read 3, iclass 34, count 2 2006.196.07:38:19.06#ibcon#read 3, iclass 34, count 2 2006.196.07:38:19.06#ibcon#about to read 4, iclass 34, count 2 2006.196.07:38:19.06#ibcon#read 4, iclass 34, count 2 2006.196.07:38:19.06#ibcon#about to read 5, iclass 34, count 2 2006.196.07:38:19.06#ibcon#read 5, iclass 34, count 2 2006.196.07:38:19.06#ibcon#about to read 6, iclass 34, count 2 2006.196.07:38:19.06#ibcon#read 6, iclass 34, count 2 2006.196.07:38:19.06#ibcon#end of sib2, iclass 34, count 2 2006.196.07:38:19.06#ibcon#*mode == 0, iclass 34, count 2 2006.196.07:38:19.06#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.196.07:38:19.06#ibcon#[25=AT04-07\r\n] 2006.196.07:38:19.06#ibcon#*before write, iclass 34, count 2 2006.196.07:38:19.06#ibcon#enter sib2, iclass 34, count 2 2006.196.07:38:19.06#ibcon#flushed, iclass 34, count 2 2006.196.07:38:19.06#ibcon#about to write, iclass 34, count 2 2006.196.07:38:19.06#ibcon#wrote, iclass 34, count 2 2006.196.07:38:19.06#ibcon#about to read 3, iclass 34, count 2 2006.196.07:38:19.09#ibcon#read 3, iclass 34, count 2 2006.196.07:38:19.09#ibcon#about to read 4, iclass 34, count 2 2006.196.07:38:19.09#ibcon#read 4, iclass 34, count 2 2006.196.07:38:19.09#ibcon#about to read 5, iclass 34, count 2 2006.196.07:38:19.09#ibcon#read 5, iclass 34, count 2 2006.196.07:38:19.09#ibcon#about to read 6, iclass 34, count 2 2006.196.07:38:19.09#ibcon#read 6, iclass 34, count 2 2006.196.07:38:19.09#ibcon#end of sib2, iclass 34, count 2 2006.196.07:38:19.09#ibcon#*after write, iclass 34, count 2 2006.196.07:38:19.09#ibcon#*before return 0, iclass 34, count 2 2006.196.07:38:19.09#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.196.07:38:19.09#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.196.07:38:19.09#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.196.07:38:19.09#ibcon#ireg 7 cls_cnt 0 2006.196.07:38:19.09#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.196.07:38:19.21#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.196.07:38:19.21#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.196.07:38:19.21#ibcon#enter wrdev, iclass 34, count 0 2006.196.07:38:19.21#ibcon#first serial, iclass 34, count 0 2006.196.07:38:19.21#ibcon#enter sib2, iclass 34, count 0 2006.196.07:38:19.21#ibcon#flushed, iclass 34, count 0 2006.196.07:38:19.21#ibcon#about to write, iclass 34, count 0 2006.196.07:38:19.21#ibcon#wrote, iclass 34, count 0 2006.196.07:38:19.21#ibcon#about to read 3, iclass 34, count 0 2006.196.07:38:19.23#ibcon#read 3, iclass 34, count 0 2006.196.07:38:19.23#ibcon#about to read 4, iclass 34, count 0 2006.196.07:38:19.23#ibcon#read 4, iclass 34, count 0 2006.196.07:38:19.23#ibcon#about to read 5, iclass 34, count 0 2006.196.07:38:19.23#ibcon#read 5, iclass 34, count 0 2006.196.07:38:19.23#ibcon#about to read 6, iclass 34, count 0 2006.196.07:38:19.23#ibcon#read 6, iclass 34, count 0 2006.196.07:38:19.23#ibcon#end of sib2, iclass 34, count 0 2006.196.07:38:19.23#ibcon#*mode == 0, iclass 34, count 0 2006.196.07:38:19.23#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.196.07:38:19.23#ibcon#[25=USB\r\n] 2006.196.07:38:19.23#ibcon#*before write, iclass 34, count 0 2006.196.07:38:19.23#ibcon#enter sib2, iclass 34, count 0 2006.196.07:38:19.23#ibcon#flushed, iclass 34, count 0 2006.196.07:38:19.23#ibcon#about to write, iclass 34, count 0 2006.196.07:38:19.23#ibcon#wrote, iclass 34, count 0 2006.196.07:38:19.23#ibcon#about to read 3, iclass 34, count 0 2006.196.07:38:19.26#ibcon#read 3, iclass 34, count 0 2006.196.07:38:19.26#ibcon#about to read 4, iclass 34, count 0 2006.196.07:38:19.26#ibcon#read 4, iclass 34, count 0 2006.196.07:38:19.26#ibcon#about to read 5, iclass 34, count 0 2006.196.07:38:19.26#ibcon#read 5, iclass 34, count 0 2006.196.07:38:19.26#ibcon#about to read 6, iclass 34, count 0 2006.196.07:38:19.26#ibcon#read 6, iclass 34, count 0 2006.196.07:38:19.26#ibcon#end of sib2, iclass 34, count 0 2006.196.07:38:19.26#ibcon#*after write, iclass 34, count 0 2006.196.07:38:19.26#ibcon#*before return 0, iclass 34, count 0 2006.196.07:38:19.26#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.196.07:38:19.26#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.196.07:38:19.26#ibcon#about to clear, iclass 34 cls_cnt 0 2006.196.07:38:19.26#ibcon#cleared, iclass 34 cls_cnt 0 2006.196.07:38:19.26$vc4f8/valo=5,652.99 2006.196.07:38:19.26#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.196.07:38:19.26#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.196.07:38:19.26#ibcon#ireg 17 cls_cnt 0 2006.196.07:38:19.26#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.196.07:38:19.26#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.196.07:38:19.26#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.196.07:38:19.26#ibcon#enter wrdev, iclass 36, count 0 2006.196.07:38:19.26#ibcon#first serial, iclass 36, count 0 2006.196.07:38:19.26#ibcon#enter sib2, iclass 36, count 0 2006.196.07:38:19.26#ibcon#flushed, iclass 36, count 0 2006.196.07:38:19.26#ibcon#about to write, iclass 36, count 0 2006.196.07:38:19.26#ibcon#wrote, iclass 36, count 0 2006.196.07:38:19.26#ibcon#about to read 3, iclass 36, count 0 2006.196.07:38:19.28#ibcon#read 3, iclass 36, count 0 2006.196.07:38:19.28#ibcon#about to read 4, iclass 36, count 0 2006.196.07:38:19.28#ibcon#read 4, iclass 36, count 0 2006.196.07:38:19.28#ibcon#about to read 5, iclass 36, count 0 2006.196.07:38:19.28#ibcon#read 5, iclass 36, count 0 2006.196.07:38:19.28#ibcon#about to read 6, iclass 36, count 0 2006.196.07:38:19.28#ibcon#read 6, iclass 36, count 0 2006.196.07:38:19.28#ibcon#end of sib2, iclass 36, count 0 2006.196.07:38:19.28#ibcon#*mode == 0, iclass 36, count 0 2006.196.07:38:19.28#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.196.07:38:19.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.196.07:38:19.28#ibcon#*before write, iclass 36, count 0 2006.196.07:38:19.28#ibcon#enter sib2, iclass 36, count 0 2006.196.07:38:19.28#ibcon#flushed, iclass 36, count 0 2006.196.07:38:19.28#ibcon#about to write, iclass 36, count 0 2006.196.07:38:19.28#ibcon#wrote, iclass 36, count 0 2006.196.07:38:19.28#ibcon#about to read 3, iclass 36, count 0 2006.196.07:38:19.32#ibcon#read 3, iclass 36, count 0 2006.196.07:38:19.32#ibcon#about to read 4, iclass 36, count 0 2006.196.07:38:19.32#ibcon#read 4, iclass 36, count 0 2006.196.07:38:19.32#ibcon#about to read 5, iclass 36, count 0 2006.196.07:38:19.32#ibcon#read 5, iclass 36, count 0 2006.196.07:38:19.32#ibcon#about to read 6, iclass 36, count 0 2006.196.07:38:19.32#ibcon#read 6, iclass 36, count 0 2006.196.07:38:19.32#ibcon#end of sib2, iclass 36, count 0 2006.196.07:38:19.32#ibcon#*after write, iclass 36, count 0 2006.196.07:38:19.32#ibcon#*before return 0, iclass 36, count 0 2006.196.07:38:19.32#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.196.07:38:19.32#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.196.07:38:19.32#ibcon#about to clear, iclass 36 cls_cnt 0 2006.196.07:38:19.32#ibcon#cleared, iclass 36 cls_cnt 0 2006.196.07:38:19.32$vc4f8/va=5,7 2006.196.07:38:19.32#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.196.07:38:19.32#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.196.07:38:19.32#ibcon#ireg 11 cls_cnt 2 2006.196.07:38:19.32#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.196.07:38:19.38#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.196.07:38:19.38#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.196.07:38:19.38#ibcon#enter wrdev, iclass 38, count 2 2006.196.07:38:19.38#ibcon#first serial, iclass 38, count 2 2006.196.07:38:19.38#ibcon#enter sib2, iclass 38, count 2 2006.196.07:38:19.38#ibcon#flushed, iclass 38, count 2 2006.196.07:38:19.38#ibcon#about to write, iclass 38, count 2 2006.196.07:38:19.38#ibcon#wrote, iclass 38, count 2 2006.196.07:38:19.38#ibcon#about to read 3, iclass 38, count 2 2006.196.07:38:19.40#ibcon#read 3, iclass 38, count 2 2006.196.07:38:19.40#ibcon#about to read 4, iclass 38, count 2 2006.196.07:38:19.40#ibcon#read 4, iclass 38, count 2 2006.196.07:38:19.40#ibcon#about to read 5, iclass 38, count 2 2006.196.07:38:19.40#ibcon#read 5, iclass 38, count 2 2006.196.07:38:19.40#ibcon#about to read 6, iclass 38, count 2 2006.196.07:38:19.40#ibcon#read 6, iclass 38, count 2 2006.196.07:38:19.40#ibcon#end of sib2, iclass 38, count 2 2006.196.07:38:19.40#ibcon#*mode == 0, iclass 38, count 2 2006.196.07:38:19.40#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.196.07:38:19.40#ibcon#[25=AT05-07\r\n] 2006.196.07:38:19.40#ibcon#*before write, iclass 38, count 2 2006.196.07:38:19.40#ibcon#enter sib2, iclass 38, count 2 2006.196.07:38:19.40#ibcon#flushed, iclass 38, count 2 2006.196.07:38:19.40#ibcon#about to write, iclass 38, count 2 2006.196.07:38:19.40#ibcon#wrote, iclass 38, count 2 2006.196.07:38:19.40#ibcon#about to read 3, iclass 38, count 2 2006.196.07:38:19.43#ibcon#read 3, iclass 38, count 2 2006.196.07:38:19.43#ibcon#about to read 4, iclass 38, count 2 2006.196.07:38:19.43#ibcon#read 4, iclass 38, count 2 2006.196.07:38:19.43#ibcon#about to read 5, iclass 38, count 2 2006.196.07:38:19.43#ibcon#read 5, iclass 38, count 2 2006.196.07:38:19.43#ibcon#about to read 6, iclass 38, count 2 2006.196.07:38:19.43#ibcon#read 6, iclass 38, count 2 2006.196.07:38:19.43#ibcon#end of sib2, iclass 38, count 2 2006.196.07:38:19.43#ibcon#*after write, iclass 38, count 2 2006.196.07:38:19.43#ibcon#*before return 0, iclass 38, count 2 2006.196.07:38:19.43#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.196.07:38:19.43#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.196.07:38:19.43#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.196.07:38:19.43#ibcon#ireg 7 cls_cnt 0 2006.196.07:38:19.43#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.196.07:38:19.55#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.196.07:38:19.55#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.196.07:38:19.55#ibcon#enter wrdev, iclass 38, count 0 2006.196.07:38:19.55#ibcon#first serial, iclass 38, count 0 2006.196.07:38:19.55#ibcon#enter sib2, iclass 38, count 0 2006.196.07:38:19.55#ibcon#flushed, iclass 38, count 0 2006.196.07:38:19.55#ibcon#about to write, iclass 38, count 0 2006.196.07:38:19.55#ibcon#wrote, iclass 38, count 0 2006.196.07:38:19.55#ibcon#about to read 3, iclass 38, count 0 2006.196.07:38:19.57#ibcon#read 3, iclass 38, count 0 2006.196.07:38:19.57#ibcon#about to read 4, iclass 38, count 0 2006.196.07:38:19.57#ibcon#read 4, iclass 38, count 0 2006.196.07:38:19.57#ibcon#about to read 5, iclass 38, count 0 2006.196.07:38:19.57#ibcon#read 5, iclass 38, count 0 2006.196.07:38:19.57#ibcon#about to read 6, iclass 38, count 0 2006.196.07:38:19.57#ibcon#read 6, iclass 38, count 0 2006.196.07:38:19.57#ibcon#end of sib2, iclass 38, count 0 2006.196.07:38:19.57#ibcon#*mode == 0, iclass 38, count 0 2006.196.07:38:19.57#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.196.07:38:19.57#ibcon#[25=USB\r\n] 2006.196.07:38:19.57#ibcon#*before write, iclass 38, count 0 2006.196.07:38:19.57#ibcon#enter sib2, iclass 38, count 0 2006.196.07:38:19.57#ibcon#flushed, iclass 38, count 0 2006.196.07:38:19.57#ibcon#about to write, iclass 38, count 0 2006.196.07:38:19.57#ibcon#wrote, iclass 38, count 0 2006.196.07:38:19.57#ibcon#about to read 3, iclass 38, count 0 2006.196.07:38:19.60#ibcon#read 3, iclass 38, count 0 2006.196.07:38:19.60#ibcon#about to read 4, iclass 38, count 0 2006.196.07:38:19.60#ibcon#read 4, iclass 38, count 0 2006.196.07:38:19.60#ibcon#about to read 5, iclass 38, count 0 2006.196.07:38:19.60#ibcon#read 5, iclass 38, count 0 2006.196.07:38:19.60#ibcon#about to read 6, iclass 38, count 0 2006.196.07:38:19.60#ibcon#read 6, iclass 38, count 0 2006.196.07:38:19.60#ibcon#end of sib2, iclass 38, count 0 2006.196.07:38:19.60#ibcon#*after write, iclass 38, count 0 2006.196.07:38:19.60#ibcon#*before return 0, iclass 38, count 0 2006.196.07:38:19.60#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.196.07:38:19.60#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.196.07:38:19.60#ibcon#about to clear, iclass 38 cls_cnt 0 2006.196.07:38:19.60#ibcon#cleared, iclass 38 cls_cnt 0 2006.196.07:38:19.60$vc4f8/valo=6,772.99 2006.196.07:38:19.60#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.196.07:38:19.60#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.196.07:38:19.60#ibcon#ireg 17 cls_cnt 0 2006.196.07:38:19.60#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.196.07:38:19.60#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.196.07:38:19.60#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.196.07:38:19.60#ibcon#enter wrdev, iclass 40, count 0 2006.196.07:38:19.60#ibcon#first serial, iclass 40, count 0 2006.196.07:38:19.60#ibcon#enter sib2, iclass 40, count 0 2006.196.07:38:19.60#ibcon#flushed, iclass 40, count 0 2006.196.07:38:19.60#ibcon#about to write, iclass 40, count 0 2006.196.07:38:19.60#ibcon#wrote, iclass 40, count 0 2006.196.07:38:19.60#ibcon#about to read 3, iclass 40, count 0 2006.196.07:38:19.62#ibcon#read 3, iclass 40, count 0 2006.196.07:38:19.62#ibcon#about to read 4, iclass 40, count 0 2006.196.07:38:19.62#ibcon#read 4, iclass 40, count 0 2006.196.07:38:19.62#ibcon#about to read 5, iclass 40, count 0 2006.196.07:38:19.62#ibcon#read 5, iclass 40, count 0 2006.196.07:38:19.62#ibcon#about to read 6, iclass 40, count 0 2006.196.07:38:19.62#ibcon#read 6, iclass 40, count 0 2006.196.07:38:19.62#ibcon#end of sib2, iclass 40, count 0 2006.196.07:38:19.62#ibcon#*mode == 0, iclass 40, count 0 2006.196.07:38:19.62#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.196.07:38:19.62#ibcon#[26=FRQ=06,772.99\r\n] 2006.196.07:38:19.62#ibcon#*before write, iclass 40, count 0 2006.196.07:38:19.62#ibcon#enter sib2, iclass 40, count 0 2006.196.07:38:19.62#ibcon#flushed, iclass 40, count 0 2006.196.07:38:19.62#ibcon#about to write, iclass 40, count 0 2006.196.07:38:19.62#ibcon#wrote, iclass 40, count 0 2006.196.07:38:19.62#ibcon#about to read 3, iclass 40, count 0 2006.196.07:38:19.66#ibcon#read 3, iclass 40, count 0 2006.196.07:38:19.66#ibcon#about to read 4, iclass 40, count 0 2006.196.07:38:19.66#ibcon#read 4, iclass 40, count 0 2006.196.07:38:19.66#ibcon#about to read 5, iclass 40, count 0 2006.196.07:38:19.66#ibcon#read 5, iclass 40, count 0 2006.196.07:38:19.66#ibcon#about to read 6, iclass 40, count 0 2006.196.07:38:19.66#ibcon#read 6, iclass 40, count 0 2006.196.07:38:19.66#ibcon#end of sib2, iclass 40, count 0 2006.196.07:38:19.66#ibcon#*after write, iclass 40, count 0 2006.196.07:38:19.66#ibcon#*before return 0, iclass 40, count 0 2006.196.07:38:19.66#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.196.07:38:19.66#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.196.07:38:19.66#ibcon#about to clear, iclass 40 cls_cnt 0 2006.196.07:38:19.66#ibcon#cleared, iclass 40 cls_cnt 0 2006.196.07:38:19.66$vc4f8/va=6,6 2006.196.07:38:19.66#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.196.07:38:19.66#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.196.07:38:19.66#ibcon#ireg 11 cls_cnt 2 2006.196.07:38:19.66#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.196.07:38:19.72#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.196.07:38:19.72#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.196.07:38:19.72#ibcon#enter wrdev, iclass 4, count 2 2006.196.07:38:19.72#ibcon#first serial, iclass 4, count 2 2006.196.07:38:19.72#ibcon#enter sib2, iclass 4, count 2 2006.196.07:38:19.72#ibcon#flushed, iclass 4, count 2 2006.196.07:38:19.72#ibcon#about to write, iclass 4, count 2 2006.196.07:38:19.72#ibcon#wrote, iclass 4, count 2 2006.196.07:38:19.72#ibcon#about to read 3, iclass 4, count 2 2006.196.07:38:19.74#ibcon#read 3, iclass 4, count 2 2006.196.07:38:19.74#ibcon#about to read 4, iclass 4, count 2 2006.196.07:38:19.74#ibcon#read 4, iclass 4, count 2 2006.196.07:38:19.74#ibcon#about to read 5, iclass 4, count 2 2006.196.07:38:19.74#ibcon#read 5, iclass 4, count 2 2006.196.07:38:19.74#ibcon#about to read 6, iclass 4, count 2 2006.196.07:38:19.74#ibcon#read 6, iclass 4, count 2 2006.196.07:38:19.74#ibcon#end of sib2, iclass 4, count 2 2006.196.07:38:19.74#ibcon#*mode == 0, iclass 4, count 2 2006.196.07:38:19.74#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.196.07:38:19.74#ibcon#[25=AT06-06\r\n] 2006.196.07:38:19.74#ibcon#*before write, iclass 4, count 2 2006.196.07:38:19.74#ibcon#enter sib2, iclass 4, count 2 2006.196.07:38:19.74#ibcon#flushed, iclass 4, count 2 2006.196.07:38:19.74#ibcon#about to write, iclass 4, count 2 2006.196.07:38:19.74#ibcon#wrote, iclass 4, count 2 2006.196.07:38:19.74#ibcon#about to read 3, iclass 4, count 2 2006.196.07:38:19.77#ibcon#read 3, iclass 4, count 2 2006.196.07:38:19.77#ibcon#about to read 4, iclass 4, count 2 2006.196.07:38:19.77#ibcon#read 4, iclass 4, count 2 2006.196.07:38:19.77#ibcon#about to read 5, iclass 4, count 2 2006.196.07:38:19.77#ibcon#read 5, iclass 4, count 2 2006.196.07:38:19.77#ibcon#about to read 6, iclass 4, count 2 2006.196.07:38:19.77#ibcon#read 6, iclass 4, count 2 2006.196.07:38:19.77#ibcon#end of sib2, iclass 4, count 2 2006.196.07:38:19.77#ibcon#*after write, iclass 4, count 2 2006.196.07:38:19.77#ibcon#*before return 0, iclass 4, count 2 2006.196.07:38:19.77#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.196.07:38:19.77#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.196.07:38:19.77#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.196.07:38:19.77#ibcon#ireg 7 cls_cnt 0 2006.196.07:38:19.77#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.196.07:38:19.89#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.196.07:38:19.89#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.196.07:38:19.89#ibcon#enter wrdev, iclass 4, count 0 2006.196.07:38:19.89#ibcon#first serial, iclass 4, count 0 2006.196.07:38:19.89#ibcon#enter sib2, iclass 4, count 0 2006.196.07:38:19.89#ibcon#flushed, iclass 4, count 0 2006.196.07:38:19.89#ibcon#about to write, iclass 4, count 0 2006.196.07:38:19.89#ibcon#wrote, iclass 4, count 0 2006.196.07:38:19.89#ibcon#about to read 3, iclass 4, count 0 2006.196.07:38:19.91#ibcon#read 3, iclass 4, count 0 2006.196.07:38:19.91#ibcon#about to read 4, iclass 4, count 0 2006.196.07:38:19.91#ibcon#read 4, iclass 4, count 0 2006.196.07:38:19.91#ibcon#about to read 5, iclass 4, count 0 2006.196.07:38:19.91#ibcon#read 5, iclass 4, count 0 2006.196.07:38:19.91#ibcon#about to read 6, iclass 4, count 0 2006.196.07:38:19.91#ibcon#read 6, iclass 4, count 0 2006.196.07:38:19.91#ibcon#end of sib2, iclass 4, count 0 2006.196.07:38:19.91#ibcon#*mode == 0, iclass 4, count 0 2006.196.07:38:19.91#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.196.07:38:19.91#ibcon#[25=USB\r\n] 2006.196.07:38:19.91#ibcon#*before write, iclass 4, count 0 2006.196.07:38:19.91#ibcon#enter sib2, iclass 4, count 0 2006.196.07:38:19.91#ibcon#flushed, iclass 4, count 0 2006.196.07:38:19.91#ibcon#about to write, iclass 4, count 0 2006.196.07:38:19.91#ibcon#wrote, iclass 4, count 0 2006.196.07:38:19.91#ibcon#about to read 3, iclass 4, count 0 2006.196.07:38:19.94#ibcon#read 3, iclass 4, count 0 2006.196.07:38:19.94#ibcon#about to read 4, iclass 4, count 0 2006.196.07:38:19.94#ibcon#read 4, iclass 4, count 0 2006.196.07:38:19.94#ibcon#about to read 5, iclass 4, count 0 2006.196.07:38:19.94#ibcon#read 5, iclass 4, count 0 2006.196.07:38:19.94#ibcon#about to read 6, iclass 4, count 0 2006.196.07:38:19.94#ibcon#read 6, iclass 4, count 0 2006.196.07:38:19.94#ibcon#end of sib2, iclass 4, count 0 2006.196.07:38:19.94#ibcon#*after write, iclass 4, count 0 2006.196.07:38:19.94#ibcon#*before return 0, iclass 4, count 0 2006.196.07:38:19.94#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.196.07:38:19.94#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.196.07:38:19.94#ibcon#about to clear, iclass 4 cls_cnt 0 2006.196.07:38:19.94#ibcon#cleared, iclass 4 cls_cnt 0 2006.196.07:38:19.94$vc4f8/valo=7,832.99 2006.196.07:38:19.94#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.196.07:38:19.94#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.196.07:38:19.94#ibcon#ireg 17 cls_cnt 0 2006.196.07:38:19.94#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.196.07:38:19.94#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.196.07:38:19.94#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.196.07:38:19.94#ibcon#enter wrdev, iclass 6, count 0 2006.196.07:38:19.94#ibcon#first serial, iclass 6, count 0 2006.196.07:38:19.94#ibcon#enter sib2, iclass 6, count 0 2006.196.07:38:19.94#ibcon#flushed, iclass 6, count 0 2006.196.07:38:19.94#ibcon#about to write, iclass 6, count 0 2006.196.07:38:19.94#ibcon#wrote, iclass 6, count 0 2006.196.07:38:19.94#ibcon#about to read 3, iclass 6, count 0 2006.196.07:38:19.96#ibcon#read 3, iclass 6, count 0 2006.196.07:38:19.96#ibcon#about to read 4, iclass 6, count 0 2006.196.07:38:19.96#ibcon#read 4, iclass 6, count 0 2006.196.07:38:19.96#ibcon#about to read 5, iclass 6, count 0 2006.196.07:38:19.96#ibcon#read 5, iclass 6, count 0 2006.196.07:38:19.96#ibcon#about to read 6, iclass 6, count 0 2006.196.07:38:19.96#ibcon#read 6, iclass 6, count 0 2006.196.07:38:19.96#ibcon#end of sib2, iclass 6, count 0 2006.196.07:38:19.96#ibcon#*mode == 0, iclass 6, count 0 2006.196.07:38:19.96#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.196.07:38:19.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.196.07:38:19.96#ibcon#*before write, iclass 6, count 0 2006.196.07:38:19.96#ibcon#enter sib2, iclass 6, count 0 2006.196.07:38:19.96#ibcon#flushed, iclass 6, count 0 2006.196.07:38:19.96#ibcon#about to write, iclass 6, count 0 2006.196.07:38:19.96#ibcon#wrote, iclass 6, count 0 2006.196.07:38:19.96#ibcon#about to read 3, iclass 6, count 0 2006.196.07:38:20.00#ibcon#read 3, iclass 6, count 0 2006.196.07:38:20.00#ibcon#about to read 4, iclass 6, count 0 2006.196.07:38:20.00#ibcon#read 4, iclass 6, count 0 2006.196.07:38:20.00#ibcon#about to read 5, iclass 6, count 0 2006.196.07:38:20.00#ibcon#read 5, iclass 6, count 0 2006.196.07:38:20.00#ibcon#about to read 6, iclass 6, count 0 2006.196.07:38:20.00#ibcon#read 6, iclass 6, count 0 2006.196.07:38:20.00#ibcon#end of sib2, iclass 6, count 0 2006.196.07:38:20.00#ibcon#*after write, iclass 6, count 0 2006.196.07:38:20.00#ibcon#*before return 0, iclass 6, count 0 2006.196.07:38:20.00#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.196.07:38:20.00#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.196.07:38:20.00#ibcon#about to clear, iclass 6 cls_cnt 0 2006.196.07:38:20.00#ibcon#cleared, iclass 6 cls_cnt 0 2006.196.07:38:20.00$vc4f8/va=7,6 2006.196.07:38:20.00#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.196.07:38:20.00#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.196.07:38:20.00#ibcon#ireg 11 cls_cnt 2 2006.196.07:38:20.00#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.196.07:38:20.06#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.196.07:38:20.06#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.196.07:38:20.06#ibcon#enter wrdev, iclass 10, count 2 2006.196.07:38:20.06#ibcon#first serial, iclass 10, count 2 2006.196.07:38:20.06#ibcon#enter sib2, iclass 10, count 2 2006.196.07:38:20.06#ibcon#flushed, iclass 10, count 2 2006.196.07:38:20.06#ibcon#about to write, iclass 10, count 2 2006.196.07:38:20.06#ibcon#wrote, iclass 10, count 2 2006.196.07:38:20.06#ibcon#about to read 3, iclass 10, count 2 2006.196.07:38:20.08#ibcon#read 3, iclass 10, count 2 2006.196.07:38:20.08#ibcon#about to read 4, iclass 10, count 2 2006.196.07:38:20.08#ibcon#read 4, iclass 10, count 2 2006.196.07:38:20.08#ibcon#about to read 5, iclass 10, count 2 2006.196.07:38:20.08#ibcon#read 5, iclass 10, count 2 2006.196.07:38:20.08#ibcon#about to read 6, iclass 10, count 2 2006.196.07:38:20.08#ibcon#read 6, iclass 10, count 2 2006.196.07:38:20.08#ibcon#end of sib2, iclass 10, count 2 2006.196.07:38:20.08#ibcon#*mode == 0, iclass 10, count 2 2006.196.07:38:20.08#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.196.07:38:20.08#ibcon#[25=AT07-06\r\n] 2006.196.07:38:20.08#ibcon#*before write, iclass 10, count 2 2006.196.07:38:20.08#ibcon#enter sib2, iclass 10, count 2 2006.196.07:38:20.08#ibcon#flushed, iclass 10, count 2 2006.196.07:38:20.08#ibcon#about to write, iclass 10, count 2 2006.196.07:38:20.08#ibcon#wrote, iclass 10, count 2 2006.196.07:38:20.08#ibcon#about to read 3, iclass 10, count 2 2006.196.07:38:20.11#ibcon#read 3, iclass 10, count 2 2006.196.07:38:20.11#ibcon#about to read 4, iclass 10, count 2 2006.196.07:38:20.11#ibcon#read 4, iclass 10, count 2 2006.196.07:38:20.11#ibcon#about to read 5, iclass 10, count 2 2006.196.07:38:20.11#ibcon#read 5, iclass 10, count 2 2006.196.07:38:20.11#ibcon#about to read 6, iclass 10, count 2 2006.196.07:38:20.11#ibcon#read 6, iclass 10, count 2 2006.196.07:38:20.11#ibcon#end of sib2, iclass 10, count 2 2006.196.07:38:20.11#ibcon#*after write, iclass 10, count 2 2006.196.07:38:20.11#ibcon#*before return 0, iclass 10, count 2 2006.196.07:38:20.11#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.196.07:38:20.11#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.196.07:38:20.11#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.196.07:38:20.11#ibcon#ireg 7 cls_cnt 0 2006.196.07:38:20.11#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.196.07:38:20.23#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.196.07:38:20.23#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.196.07:38:20.23#ibcon#enter wrdev, iclass 10, count 0 2006.196.07:38:20.23#ibcon#first serial, iclass 10, count 0 2006.196.07:38:20.23#ibcon#enter sib2, iclass 10, count 0 2006.196.07:38:20.23#ibcon#flushed, iclass 10, count 0 2006.196.07:38:20.23#ibcon#about to write, iclass 10, count 0 2006.196.07:38:20.23#ibcon#wrote, iclass 10, count 0 2006.196.07:38:20.23#ibcon#about to read 3, iclass 10, count 0 2006.196.07:38:20.26#ibcon#read 3, iclass 10, count 0 2006.196.07:38:20.26#ibcon#about to read 4, iclass 10, count 0 2006.196.07:38:20.26#ibcon#read 4, iclass 10, count 0 2006.196.07:38:20.26#ibcon#about to read 5, iclass 10, count 0 2006.196.07:38:20.26#ibcon#read 5, iclass 10, count 0 2006.196.07:38:20.26#ibcon#about to read 6, iclass 10, count 0 2006.196.07:38:20.26#ibcon#read 6, iclass 10, count 0 2006.196.07:38:20.26#ibcon#end of sib2, iclass 10, count 0 2006.196.07:38:20.26#ibcon#*mode == 0, iclass 10, count 0 2006.196.07:38:20.26#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.196.07:38:20.26#ibcon#[25=USB\r\n] 2006.196.07:38:20.26#ibcon#*before write, iclass 10, count 0 2006.196.07:38:20.26#ibcon#enter sib2, iclass 10, count 0 2006.196.07:38:20.26#ibcon#flushed, iclass 10, count 0 2006.196.07:38:20.26#ibcon#about to write, iclass 10, count 0 2006.196.07:38:20.26#ibcon#wrote, iclass 10, count 0 2006.196.07:38:20.26#ibcon#about to read 3, iclass 10, count 0 2006.196.07:38:20.29#ibcon#read 3, iclass 10, count 0 2006.196.07:38:20.29#ibcon#about to read 4, iclass 10, count 0 2006.196.07:38:20.29#ibcon#read 4, iclass 10, count 0 2006.196.07:38:20.29#ibcon#about to read 5, iclass 10, count 0 2006.196.07:38:20.29#ibcon#read 5, iclass 10, count 0 2006.196.07:38:20.29#ibcon#about to read 6, iclass 10, count 0 2006.196.07:38:20.29#ibcon#read 6, iclass 10, count 0 2006.196.07:38:20.29#ibcon#end of sib2, iclass 10, count 0 2006.196.07:38:20.29#ibcon#*after write, iclass 10, count 0 2006.196.07:38:20.29#ibcon#*before return 0, iclass 10, count 0 2006.196.07:38:20.29#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.196.07:38:20.29#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.196.07:38:20.29#ibcon#about to clear, iclass 10 cls_cnt 0 2006.196.07:38:20.29#ibcon#cleared, iclass 10 cls_cnt 0 2006.196.07:38:20.29$vc4f8/valo=8,852.99 2006.196.07:38:20.29#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.196.07:38:20.29#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.196.07:38:20.29#ibcon#ireg 17 cls_cnt 0 2006.196.07:38:20.29#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.196.07:38:20.29#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.196.07:38:20.29#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.196.07:38:20.29#ibcon#enter wrdev, iclass 12, count 0 2006.196.07:38:20.29#ibcon#first serial, iclass 12, count 0 2006.196.07:38:20.29#ibcon#enter sib2, iclass 12, count 0 2006.196.07:38:20.29#ibcon#flushed, iclass 12, count 0 2006.196.07:38:20.29#ibcon#about to write, iclass 12, count 0 2006.196.07:38:20.29#ibcon#wrote, iclass 12, count 0 2006.196.07:38:20.29#ibcon#about to read 3, iclass 12, count 0 2006.196.07:38:20.31#ibcon#read 3, iclass 12, count 0 2006.196.07:38:20.31#ibcon#about to read 4, iclass 12, count 0 2006.196.07:38:20.31#ibcon#read 4, iclass 12, count 0 2006.196.07:38:20.31#ibcon#about to read 5, iclass 12, count 0 2006.196.07:38:20.31#ibcon#read 5, iclass 12, count 0 2006.196.07:38:20.31#ibcon#about to read 6, iclass 12, count 0 2006.196.07:38:20.31#ibcon#read 6, iclass 12, count 0 2006.196.07:38:20.31#ibcon#end of sib2, iclass 12, count 0 2006.196.07:38:20.31#ibcon#*mode == 0, iclass 12, count 0 2006.196.07:38:20.31#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.196.07:38:20.31#ibcon#[26=FRQ=08,852.99\r\n] 2006.196.07:38:20.31#ibcon#*before write, iclass 12, count 0 2006.196.07:38:20.31#ibcon#enter sib2, iclass 12, count 0 2006.196.07:38:20.31#ibcon#flushed, iclass 12, count 0 2006.196.07:38:20.31#ibcon#about to write, iclass 12, count 0 2006.196.07:38:20.31#ibcon#wrote, iclass 12, count 0 2006.196.07:38:20.31#ibcon#about to read 3, iclass 12, count 0 2006.196.07:38:20.35#ibcon#read 3, iclass 12, count 0 2006.196.07:38:20.35#ibcon#about to read 4, iclass 12, count 0 2006.196.07:38:20.35#ibcon#read 4, iclass 12, count 0 2006.196.07:38:20.35#ibcon#about to read 5, iclass 12, count 0 2006.196.07:38:20.35#ibcon#read 5, iclass 12, count 0 2006.196.07:38:20.35#ibcon#about to read 6, iclass 12, count 0 2006.196.07:38:20.35#ibcon#read 6, iclass 12, count 0 2006.196.07:38:20.35#ibcon#end of sib2, iclass 12, count 0 2006.196.07:38:20.35#ibcon#*after write, iclass 12, count 0 2006.196.07:38:20.35#ibcon#*before return 0, iclass 12, count 0 2006.196.07:38:20.35#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.196.07:38:20.35#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.196.07:38:20.35#ibcon#about to clear, iclass 12 cls_cnt 0 2006.196.07:38:20.35#ibcon#cleared, iclass 12 cls_cnt 0 2006.196.07:38:20.35$vc4f8/va=8,7 2006.196.07:38:20.35#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.196.07:38:20.35#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.196.07:38:20.35#ibcon#ireg 11 cls_cnt 2 2006.196.07:38:20.35#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.196.07:38:20.41#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.196.07:38:20.41#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.196.07:38:20.41#ibcon#enter wrdev, iclass 14, count 2 2006.196.07:38:20.41#ibcon#first serial, iclass 14, count 2 2006.196.07:38:20.41#ibcon#enter sib2, iclass 14, count 2 2006.196.07:38:20.41#ibcon#flushed, iclass 14, count 2 2006.196.07:38:20.41#ibcon#about to write, iclass 14, count 2 2006.196.07:38:20.41#ibcon#wrote, iclass 14, count 2 2006.196.07:38:20.41#ibcon#about to read 3, iclass 14, count 2 2006.196.07:38:20.43#ibcon#read 3, iclass 14, count 2 2006.196.07:38:20.43#ibcon#about to read 4, iclass 14, count 2 2006.196.07:38:20.43#ibcon#read 4, iclass 14, count 2 2006.196.07:38:20.43#ibcon#about to read 5, iclass 14, count 2 2006.196.07:38:20.43#ibcon#read 5, iclass 14, count 2 2006.196.07:38:20.43#ibcon#about to read 6, iclass 14, count 2 2006.196.07:38:20.43#ibcon#read 6, iclass 14, count 2 2006.196.07:38:20.43#ibcon#end of sib2, iclass 14, count 2 2006.196.07:38:20.43#ibcon#*mode == 0, iclass 14, count 2 2006.196.07:38:20.43#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.196.07:38:20.43#ibcon#[25=AT08-07\r\n] 2006.196.07:38:20.43#ibcon#*before write, iclass 14, count 2 2006.196.07:38:20.43#ibcon#enter sib2, iclass 14, count 2 2006.196.07:38:20.43#ibcon#flushed, iclass 14, count 2 2006.196.07:38:20.43#ibcon#about to write, iclass 14, count 2 2006.196.07:38:20.43#ibcon#wrote, iclass 14, count 2 2006.196.07:38:20.43#ibcon#about to read 3, iclass 14, count 2 2006.196.07:38:20.46#ibcon#read 3, iclass 14, count 2 2006.196.07:38:20.46#ibcon#about to read 4, iclass 14, count 2 2006.196.07:38:20.46#ibcon#read 4, iclass 14, count 2 2006.196.07:38:20.46#ibcon#about to read 5, iclass 14, count 2 2006.196.07:38:20.46#ibcon#read 5, iclass 14, count 2 2006.196.07:38:20.46#ibcon#about to read 6, iclass 14, count 2 2006.196.07:38:20.46#ibcon#read 6, iclass 14, count 2 2006.196.07:38:20.46#ibcon#end of sib2, iclass 14, count 2 2006.196.07:38:20.46#ibcon#*after write, iclass 14, count 2 2006.196.07:38:20.46#ibcon#*before return 0, iclass 14, count 2 2006.196.07:38:20.46#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.196.07:38:20.46#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.196.07:38:20.46#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.196.07:38:20.46#ibcon#ireg 7 cls_cnt 0 2006.196.07:38:20.46#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.196.07:38:20.58#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.196.07:38:20.58#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.196.07:38:20.58#ibcon#enter wrdev, iclass 14, count 0 2006.196.07:38:20.58#ibcon#first serial, iclass 14, count 0 2006.196.07:38:20.58#ibcon#enter sib2, iclass 14, count 0 2006.196.07:38:20.58#ibcon#flushed, iclass 14, count 0 2006.196.07:38:20.58#ibcon#about to write, iclass 14, count 0 2006.196.07:38:20.58#ibcon#wrote, iclass 14, count 0 2006.196.07:38:20.58#ibcon#about to read 3, iclass 14, count 0 2006.196.07:38:20.60#ibcon#read 3, iclass 14, count 0 2006.196.07:38:20.60#ibcon#about to read 4, iclass 14, count 0 2006.196.07:38:20.60#ibcon#read 4, iclass 14, count 0 2006.196.07:38:20.60#ibcon#about to read 5, iclass 14, count 0 2006.196.07:38:20.60#ibcon#read 5, iclass 14, count 0 2006.196.07:38:20.60#ibcon#about to read 6, iclass 14, count 0 2006.196.07:38:20.60#ibcon#read 6, iclass 14, count 0 2006.196.07:38:20.60#ibcon#end of sib2, iclass 14, count 0 2006.196.07:38:20.60#ibcon#*mode == 0, iclass 14, count 0 2006.196.07:38:20.60#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.196.07:38:20.60#ibcon#[25=USB\r\n] 2006.196.07:38:20.60#ibcon#*before write, iclass 14, count 0 2006.196.07:38:20.60#ibcon#enter sib2, iclass 14, count 0 2006.196.07:38:20.60#ibcon#flushed, iclass 14, count 0 2006.196.07:38:20.60#ibcon#about to write, iclass 14, count 0 2006.196.07:38:20.60#ibcon#wrote, iclass 14, count 0 2006.196.07:38:20.60#ibcon#about to read 3, iclass 14, count 0 2006.196.07:38:20.63#ibcon#read 3, iclass 14, count 0 2006.196.07:38:20.63#ibcon#about to read 4, iclass 14, count 0 2006.196.07:38:20.63#ibcon#read 4, iclass 14, count 0 2006.196.07:38:20.63#ibcon#about to read 5, iclass 14, count 0 2006.196.07:38:20.63#ibcon#read 5, iclass 14, count 0 2006.196.07:38:20.63#ibcon#about to read 6, iclass 14, count 0 2006.196.07:38:20.63#ibcon#read 6, iclass 14, count 0 2006.196.07:38:20.63#ibcon#end of sib2, iclass 14, count 0 2006.196.07:38:20.63#ibcon#*after write, iclass 14, count 0 2006.196.07:38:20.63#ibcon#*before return 0, iclass 14, count 0 2006.196.07:38:20.63#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.196.07:38:20.63#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.196.07:38:20.63#ibcon#about to clear, iclass 14 cls_cnt 0 2006.196.07:38:20.63#ibcon#cleared, iclass 14 cls_cnt 0 2006.196.07:38:20.63$vc4f8/vblo=1,632.99 2006.196.07:38:20.63#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.196.07:38:20.63#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.196.07:38:20.63#ibcon#ireg 17 cls_cnt 0 2006.196.07:38:20.63#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.196.07:38:20.63#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.196.07:38:20.63#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.196.07:38:20.63#ibcon#enter wrdev, iclass 16, count 0 2006.196.07:38:20.63#ibcon#first serial, iclass 16, count 0 2006.196.07:38:20.63#ibcon#enter sib2, iclass 16, count 0 2006.196.07:38:20.63#ibcon#flushed, iclass 16, count 0 2006.196.07:38:20.63#ibcon#about to write, iclass 16, count 0 2006.196.07:38:20.63#ibcon#wrote, iclass 16, count 0 2006.196.07:38:20.63#ibcon#about to read 3, iclass 16, count 0 2006.196.07:38:20.65#ibcon#read 3, iclass 16, count 0 2006.196.07:38:20.65#ibcon#about to read 4, iclass 16, count 0 2006.196.07:38:20.65#ibcon#read 4, iclass 16, count 0 2006.196.07:38:20.65#ibcon#about to read 5, iclass 16, count 0 2006.196.07:38:20.65#ibcon#read 5, iclass 16, count 0 2006.196.07:38:20.65#ibcon#about to read 6, iclass 16, count 0 2006.196.07:38:20.65#ibcon#read 6, iclass 16, count 0 2006.196.07:38:20.65#ibcon#end of sib2, iclass 16, count 0 2006.196.07:38:20.65#ibcon#*mode == 0, iclass 16, count 0 2006.196.07:38:20.65#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.196.07:38:20.65#ibcon#[28=FRQ=01,632.99\r\n] 2006.196.07:38:20.65#ibcon#*before write, iclass 16, count 0 2006.196.07:38:20.65#ibcon#enter sib2, iclass 16, count 0 2006.196.07:38:20.65#ibcon#flushed, iclass 16, count 0 2006.196.07:38:20.65#ibcon#about to write, iclass 16, count 0 2006.196.07:38:20.65#ibcon#wrote, iclass 16, count 0 2006.196.07:38:20.65#ibcon#about to read 3, iclass 16, count 0 2006.196.07:38:20.69#ibcon#read 3, iclass 16, count 0 2006.196.07:38:20.69#ibcon#about to read 4, iclass 16, count 0 2006.196.07:38:20.69#ibcon#read 4, iclass 16, count 0 2006.196.07:38:20.69#ibcon#about to read 5, iclass 16, count 0 2006.196.07:38:20.69#ibcon#read 5, iclass 16, count 0 2006.196.07:38:20.69#ibcon#about to read 6, iclass 16, count 0 2006.196.07:38:20.69#ibcon#read 6, iclass 16, count 0 2006.196.07:38:20.69#ibcon#end of sib2, iclass 16, count 0 2006.196.07:38:20.69#ibcon#*after write, iclass 16, count 0 2006.196.07:38:20.69#ibcon#*before return 0, iclass 16, count 0 2006.196.07:38:20.69#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.196.07:38:20.69#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.196.07:38:20.69#ibcon#about to clear, iclass 16 cls_cnt 0 2006.196.07:38:20.69#ibcon#cleared, iclass 16 cls_cnt 0 2006.196.07:38:20.69$vc4f8/vb=1,4 2006.196.07:38:20.69#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.196.07:38:20.69#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.196.07:38:20.69#ibcon#ireg 11 cls_cnt 2 2006.196.07:38:20.69#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.196.07:38:20.69#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.196.07:38:20.69#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.196.07:38:20.69#ibcon#enter wrdev, iclass 18, count 2 2006.196.07:38:20.69#ibcon#first serial, iclass 18, count 2 2006.196.07:38:20.69#ibcon#enter sib2, iclass 18, count 2 2006.196.07:38:20.69#ibcon#flushed, iclass 18, count 2 2006.196.07:38:20.69#ibcon#about to write, iclass 18, count 2 2006.196.07:38:20.69#ibcon#wrote, iclass 18, count 2 2006.196.07:38:20.69#ibcon#about to read 3, iclass 18, count 2 2006.196.07:38:20.71#ibcon#read 3, iclass 18, count 2 2006.196.07:38:20.71#ibcon#about to read 4, iclass 18, count 2 2006.196.07:38:20.71#ibcon#read 4, iclass 18, count 2 2006.196.07:38:20.71#ibcon#about to read 5, iclass 18, count 2 2006.196.07:38:20.71#ibcon#read 5, iclass 18, count 2 2006.196.07:38:20.71#ibcon#about to read 6, iclass 18, count 2 2006.196.07:38:20.71#ibcon#read 6, iclass 18, count 2 2006.196.07:38:20.71#ibcon#end of sib2, iclass 18, count 2 2006.196.07:38:20.71#ibcon#*mode == 0, iclass 18, count 2 2006.196.07:38:20.71#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.196.07:38:20.71#ibcon#[27=AT01-04\r\n] 2006.196.07:38:20.71#ibcon#*before write, iclass 18, count 2 2006.196.07:38:20.71#ibcon#enter sib2, iclass 18, count 2 2006.196.07:38:20.71#ibcon#flushed, iclass 18, count 2 2006.196.07:38:20.71#ibcon#about to write, iclass 18, count 2 2006.196.07:38:20.71#ibcon#wrote, iclass 18, count 2 2006.196.07:38:20.71#ibcon#about to read 3, iclass 18, count 2 2006.196.07:38:20.74#ibcon#read 3, iclass 18, count 2 2006.196.07:38:20.74#ibcon#about to read 4, iclass 18, count 2 2006.196.07:38:20.74#ibcon#read 4, iclass 18, count 2 2006.196.07:38:20.74#ibcon#about to read 5, iclass 18, count 2 2006.196.07:38:20.74#ibcon#read 5, iclass 18, count 2 2006.196.07:38:20.74#ibcon#about to read 6, iclass 18, count 2 2006.196.07:38:20.74#ibcon#read 6, iclass 18, count 2 2006.196.07:38:20.74#ibcon#end of sib2, iclass 18, count 2 2006.196.07:38:20.74#ibcon#*after write, iclass 18, count 2 2006.196.07:38:20.74#ibcon#*before return 0, iclass 18, count 2 2006.196.07:38:20.74#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.196.07:38:20.74#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.196.07:38:20.74#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.196.07:38:20.74#ibcon#ireg 7 cls_cnt 0 2006.196.07:38:20.74#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.196.07:38:20.86#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.196.07:38:20.86#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.196.07:38:20.86#ibcon#enter wrdev, iclass 18, count 0 2006.196.07:38:20.86#ibcon#first serial, iclass 18, count 0 2006.196.07:38:20.86#ibcon#enter sib2, iclass 18, count 0 2006.196.07:38:20.86#ibcon#flushed, iclass 18, count 0 2006.196.07:38:20.86#ibcon#about to write, iclass 18, count 0 2006.196.07:38:20.86#ibcon#wrote, iclass 18, count 0 2006.196.07:38:20.86#ibcon#about to read 3, iclass 18, count 0 2006.196.07:38:20.88#ibcon#read 3, iclass 18, count 0 2006.196.07:38:20.88#ibcon#about to read 4, iclass 18, count 0 2006.196.07:38:20.88#ibcon#read 4, iclass 18, count 0 2006.196.07:38:20.88#ibcon#about to read 5, iclass 18, count 0 2006.196.07:38:20.88#ibcon#read 5, iclass 18, count 0 2006.196.07:38:20.88#ibcon#about to read 6, iclass 18, count 0 2006.196.07:38:20.88#ibcon#read 6, iclass 18, count 0 2006.196.07:38:20.88#ibcon#end of sib2, iclass 18, count 0 2006.196.07:38:20.88#ibcon#*mode == 0, iclass 18, count 0 2006.196.07:38:20.88#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.196.07:38:20.88#ibcon#[27=USB\r\n] 2006.196.07:38:20.88#ibcon#*before write, iclass 18, count 0 2006.196.07:38:20.88#ibcon#enter sib2, iclass 18, count 0 2006.196.07:38:20.88#ibcon#flushed, iclass 18, count 0 2006.196.07:38:20.88#ibcon#about to write, iclass 18, count 0 2006.196.07:38:20.88#ibcon#wrote, iclass 18, count 0 2006.196.07:38:20.88#ibcon#about to read 3, iclass 18, count 0 2006.196.07:38:20.91#ibcon#read 3, iclass 18, count 0 2006.196.07:38:20.91#ibcon#about to read 4, iclass 18, count 0 2006.196.07:38:20.91#ibcon#read 4, iclass 18, count 0 2006.196.07:38:20.91#ibcon#about to read 5, iclass 18, count 0 2006.196.07:38:20.91#ibcon#read 5, iclass 18, count 0 2006.196.07:38:20.91#ibcon#about to read 6, iclass 18, count 0 2006.196.07:38:20.91#ibcon#read 6, iclass 18, count 0 2006.196.07:38:20.91#ibcon#end of sib2, iclass 18, count 0 2006.196.07:38:20.91#ibcon#*after write, iclass 18, count 0 2006.196.07:38:20.91#ibcon#*before return 0, iclass 18, count 0 2006.196.07:38:20.91#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.196.07:38:20.91#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.196.07:38:20.91#ibcon#about to clear, iclass 18 cls_cnt 0 2006.196.07:38:20.91#ibcon#cleared, iclass 18 cls_cnt 0 2006.196.07:38:20.91$vc4f8/vblo=2,640.99 2006.196.07:38:20.91#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.196.07:38:20.91#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.196.07:38:20.91#ibcon#ireg 17 cls_cnt 0 2006.196.07:38:20.91#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.196.07:38:20.91#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.196.07:38:20.91#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.196.07:38:20.91#ibcon#enter wrdev, iclass 20, count 0 2006.196.07:38:20.91#ibcon#first serial, iclass 20, count 0 2006.196.07:38:20.91#ibcon#enter sib2, iclass 20, count 0 2006.196.07:38:20.91#ibcon#flushed, iclass 20, count 0 2006.196.07:38:20.91#ibcon#about to write, iclass 20, count 0 2006.196.07:38:20.91#ibcon#wrote, iclass 20, count 0 2006.196.07:38:20.91#ibcon#about to read 3, iclass 20, count 0 2006.196.07:38:20.93#ibcon#read 3, iclass 20, count 0 2006.196.07:38:20.93#ibcon#about to read 4, iclass 20, count 0 2006.196.07:38:20.93#ibcon#read 4, iclass 20, count 0 2006.196.07:38:20.93#ibcon#about to read 5, iclass 20, count 0 2006.196.07:38:20.93#ibcon#read 5, iclass 20, count 0 2006.196.07:38:20.93#ibcon#about to read 6, iclass 20, count 0 2006.196.07:38:20.93#ibcon#read 6, iclass 20, count 0 2006.196.07:38:20.93#ibcon#end of sib2, iclass 20, count 0 2006.196.07:38:20.93#ibcon#*mode == 0, iclass 20, count 0 2006.196.07:38:20.93#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.196.07:38:20.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.196.07:38:20.93#ibcon#*before write, iclass 20, count 0 2006.196.07:38:20.93#ibcon#enter sib2, iclass 20, count 0 2006.196.07:38:20.93#ibcon#flushed, iclass 20, count 0 2006.196.07:38:20.93#ibcon#about to write, iclass 20, count 0 2006.196.07:38:20.93#ibcon#wrote, iclass 20, count 0 2006.196.07:38:20.93#ibcon#about to read 3, iclass 20, count 0 2006.196.07:38:20.97#ibcon#read 3, iclass 20, count 0 2006.196.07:38:20.97#ibcon#about to read 4, iclass 20, count 0 2006.196.07:38:20.97#ibcon#read 4, iclass 20, count 0 2006.196.07:38:20.97#ibcon#about to read 5, iclass 20, count 0 2006.196.07:38:20.97#ibcon#read 5, iclass 20, count 0 2006.196.07:38:20.97#ibcon#about to read 6, iclass 20, count 0 2006.196.07:38:20.97#ibcon#read 6, iclass 20, count 0 2006.196.07:38:20.97#ibcon#end of sib2, iclass 20, count 0 2006.196.07:38:20.97#ibcon#*after write, iclass 20, count 0 2006.196.07:38:20.97#ibcon#*before return 0, iclass 20, count 0 2006.196.07:38:20.97#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.196.07:38:20.97#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.196.07:38:20.97#ibcon#about to clear, iclass 20 cls_cnt 0 2006.196.07:38:20.97#ibcon#cleared, iclass 20 cls_cnt 0 2006.196.07:38:20.97$vc4f8/vb=2,4 2006.196.07:38:20.97#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.196.07:38:20.97#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.196.07:38:20.97#ibcon#ireg 11 cls_cnt 2 2006.196.07:38:20.97#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.196.07:38:21.03#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.196.07:38:21.03#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.196.07:38:21.03#ibcon#enter wrdev, iclass 22, count 2 2006.196.07:38:21.03#ibcon#first serial, iclass 22, count 2 2006.196.07:38:21.03#ibcon#enter sib2, iclass 22, count 2 2006.196.07:38:21.03#ibcon#flushed, iclass 22, count 2 2006.196.07:38:21.03#ibcon#about to write, iclass 22, count 2 2006.196.07:38:21.03#ibcon#wrote, iclass 22, count 2 2006.196.07:38:21.03#ibcon#about to read 3, iclass 22, count 2 2006.196.07:38:21.05#ibcon#read 3, iclass 22, count 2 2006.196.07:38:21.05#ibcon#about to read 4, iclass 22, count 2 2006.196.07:38:21.05#ibcon#read 4, iclass 22, count 2 2006.196.07:38:21.05#ibcon#about to read 5, iclass 22, count 2 2006.196.07:38:21.05#ibcon#read 5, iclass 22, count 2 2006.196.07:38:21.05#ibcon#about to read 6, iclass 22, count 2 2006.196.07:38:21.05#ibcon#read 6, iclass 22, count 2 2006.196.07:38:21.05#ibcon#end of sib2, iclass 22, count 2 2006.196.07:38:21.05#ibcon#*mode == 0, iclass 22, count 2 2006.196.07:38:21.05#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.196.07:38:21.05#ibcon#[27=AT02-04\r\n] 2006.196.07:38:21.05#ibcon#*before write, iclass 22, count 2 2006.196.07:38:21.05#ibcon#enter sib2, iclass 22, count 2 2006.196.07:38:21.05#ibcon#flushed, iclass 22, count 2 2006.196.07:38:21.05#ibcon#about to write, iclass 22, count 2 2006.196.07:38:21.05#ibcon#wrote, iclass 22, count 2 2006.196.07:38:21.05#ibcon#about to read 3, iclass 22, count 2 2006.196.07:38:21.08#ibcon#read 3, iclass 22, count 2 2006.196.07:38:21.08#ibcon#about to read 4, iclass 22, count 2 2006.196.07:38:21.08#ibcon#read 4, iclass 22, count 2 2006.196.07:38:21.08#ibcon#about to read 5, iclass 22, count 2 2006.196.07:38:21.08#ibcon#read 5, iclass 22, count 2 2006.196.07:38:21.08#ibcon#about to read 6, iclass 22, count 2 2006.196.07:38:21.08#ibcon#read 6, iclass 22, count 2 2006.196.07:38:21.08#ibcon#end of sib2, iclass 22, count 2 2006.196.07:38:21.08#ibcon#*after write, iclass 22, count 2 2006.196.07:38:21.08#ibcon#*before return 0, iclass 22, count 2 2006.196.07:38:21.08#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.196.07:38:21.08#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.196.07:38:21.08#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.196.07:38:21.08#ibcon#ireg 7 cls_cnt 0 2006.196.07:38:21.08#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.196.07:38:21.20#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.196.07:38:21.20#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.196.07:38:21.20#ibcon#enter wrdev, iclass 22, count 0 2006.196.07:38:21.20#ibcon#first serial, iclass 22, count 0 2006.196.07:38:21.20#ibcon#enter sib2, iclass 22, count 0 2006.196.07:38:21.20#ibcon#flushed, iclass 22, count 0 2006.196.07:38:21.20#ibcon#about to write, iclass 22, count 0 2006.196.07:38:21.20#ibcon#wrote, iclass 22, count 0 2006.196.07:38:21.20#ibcon#about to read 3, iclass 22, count 0 2006.196.07:38:21.22#ibcon#read 3, iclass 22, count 0 2006.196.07:38:21.22#ibcon#about to read 4, iclass 22, count 0 2006.196.07:38:21.22#ibcon#read 4, iclass 22, count 0 2006.196.07:38:21.22#ibcon#about to read 5, iclass 22, count 0 2006.196.07:38:21.22#ibcon#read 5, iclass 22, count 0 2006.196.07:38:21.22#ibcon#about to read 6, iclass 22, count 0 2006.196.07:38:21.22#ibcon#read 6, iclass 22, count 0 2006.196.07:38:21.22#ibcon#end of sib2, iclass 22, count 0 2006.196.07:38:21.22#ibcon#*mode == 0, iclass 22, count 0 2006.196.07:38:21.22#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.196.07:38:21.22#ibcon#[27=USB\r\n] 2006.196.07:38:21.22#ibcon#*before write, iclass 22, count 0 2006.196.07:38:21.22#ibcon#enter sib2, iclass 22, count 0 2006.196.07:38:21.22#ibcon#flushed, iclass 22, count 0 2006.196.07:38:21.22#ibcon#about to write, iclass 22, count 0 2006.196.07:38:21.22#ibcon#wrote, iclass 22, count 0 2006.196.07:38:21.22#ibcon#about to read 3, iclass 22, count 0 2006.196.07:38:21.25#ibcon#read 3, iclass 22, count 0 2006.196.07:38:21.25#ibcon#about to read 4, iclass 22, count 0 2006.196.07:38:21.25#ibcon#read 4, iclass 22, count 0 2006.196.07:38:21.25#ibcon#about to read 5, iclass 22, count 0 2006.196.07:38:21.25#ibcon#read 5, iclass 22, count 0 2006.196.07:38:21.25#ibcon#about to read 6, iclass 22, count 0 2006.196.07:38:21.25#ibcon#read 6, iclass 22, count 0 2006.196.07:38:21.25#ibcon#end of sib2, iclass 22, count 0 2006.196.07:38:21.25#ibcon#*after write, iclass 22, count 0 2006.196.07:38:21.25#ibcon#*before return 0, iclass 22, count 0 2006.196.07:38:21.25#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.196.07:38:21.25#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.196.07:38:21.25#ibcon#about to clear, iclass 22 cls_cnt 0 2006.196.07:38:21.25#ibcon#cleared, iclass 22 cls_cnt 0 2006.196.07:38:21.25$vc4f8/vblo=3,656.99 2006.196.07:38:21.25#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.196.07:38:21.25#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.196.07:38:21.25#ibcon#ireg 17 cls_cnt 0 2006.196.07:38:21.25#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.196.07:38:21.25#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.196.07:38:21.25#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.196.07:38:21.25#ibcon#enter wrdev, iclass 24, count 0 2006.196.07:38:21.25#ibcon#first serial, iclass 24, count 0 2006.196.07:38:21.25#ibcon#enter sib2, iclass 24, count 0 2006.196.07:38:21.25#ibcon#flushed, iclass 24, count 0 2006.196.07:38:21.25#ibcon#about to write, iclass 24, count 0 2006.196.07:38:21.25#ibcon#wrote, iclass 24, count 0 2006.196.07:38:21.25#ibcon#about to read 3, iclass 24, count 0 2006.196.07:38:21.27#ibcon#read 3, iclass 24, count 0 2006.196.07:38:21.27#ibcon#about to read 4, iclass 24, count 0 2006.196.07:38:21.27#ibcon#read 4, iclass 24, count 0 2006.196.07:38:21.27#ibcon#about to read 5, iclass 24, count 0 2006.196.07:38:21.27#ibcon#read 5, iclass 24, count 0 2006.196.07:38:21.27#ibcon#about to read 6, iclass 24, count 0 2006.196.07:38:21.27#ibcon#read 6, iclass 24, count 0 2006.196.07:38:21.27#ibcon#end of sib2, iclass 24, count 0 2006.196.07:38:21.27#ibcon#*mode == 0, iclass 24, count 0 2006.196.07:38:21.27#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.196.07:38:21.27#ibcon#[28=FRQ=03,656.99\r\n] 2006.196.07:38:21.27#ibcon#*before write, iclass 24, count 0 2006.196.07:38:21.27#ibcon#enter sib2, iclass 24, count 0 2006.196.07:38:21.27#ibcon#flushed, iclass 24, count 0 2006.196.07:38:21.27#ibcon#about to write, iclass 24, count 0 2006.196.07:38:21.27#ibcon#wrote, iclass 24, count 0 2006.196.07:38:21.27#ibcon#about to read 3, iclass 24, count 0 2006.196.07:38:21.31#ibcon#read 3, iclass 24, count 0 2006.196.07:38:21.31#ibcon#about to read 4, iclass 24, count 0 2006.196.07:38:21.31#ibcon#read 4, iclass 24, count 0 2006.196.07:38:21.31#ibcon#about to read 5, iclass 24, count 0 2006.196.07:38:21.31#ibcon#read 5, iclass 24, count 0 2006.196.07:38:21.31#ibcon#about to read 6, iclass 24, count 0 2006.196.07:38:21.31#ibcon#read 6, iclass 24, count 0 2006.196.07:38:21.31#ibcon#end of sib2, iclass 24, count 0 2006.196.07:38:21.31#ibcon#*after write, iclass 24, count 0 2006.196.07:38:21.31#ibcon#*before return 0, iclass 24, count 0 2006.196.07:38:21.31#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.196.07:38:21.31#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.196.07:38:21.31#ibcon#about to clear, iclass 24 cls_cnt 0 2006.196.07:38:21.31#ibcon#cleared, iclass 24 cls_cnt 0 2006.196.07:38:21.31$vc4f8/vb=3,4 2006.196.07:38:21.31#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.196.07:38:21.31#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.196.07:38:21.31#ibcon#ireg 11 cls_cnt 2 2006.196.07:38:21.31#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.196.07:38:21.37#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.196.07:38:21.37#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.196.07:38:21.37#ibcon#enter wrdev, iclass 26, count 2 2006.196.07:38:21.37#ibcon#first serial, iclass 26, count 2 2006.196.07:38:21.37#ibcon#enter sib2, iclass 26, count 2 2006.196.07:38:21.37#ibcon#flushed, iclass 26, count 2 2006.196.07:38:21.37#ibcon#about to write, iclass 26, count 2 2006.196.07:38:21.37#ibcon#wrote, iclass 26, count 2 2006.196.07:38:21.37#ibcon#about to read 3, iclass 26, count 2 2006.196.07:38:21.39#ibcon#read 3, iclass 26, count 2 2006.196.07:38:21.39#ibcon#about to read 4, iclass 26, count 2 2006.196.07:38:21.39#ibcon#read 4, iclass 26, count 2 2006.196.07:38:21.39#ibcon#about to read 5, iclass 26, count 2 2006.196.07:38:21.39#ibcon#read 5, iclass 26, count 2 2006.196.07:38:21.39#ibcon#about to read 6, iclass 26, count 2 2006.196.07:38:21.39#ibcon#read 6, iclass 26, count 2 2006.196.07:38:21.39#ibcon#end of sib2, iclass 26, count 2 2006.196.07:38:21.39#ibcon#*mode == 0, iclass 26, count 2 2006.196.07:38:21.39#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.196.07:38:21.39#ibcon#[27=AT03-04\r\n] 2006.196.07:38:21.39#ibcon#*before write, iclass 26, count 2 2006.196.07:38:21.39#ibcon#enter sib2, iclass 26, count 2 2006.196.07:38:21.39#ibcon#flushed, iclass 26, count 2 2006.196.07:38:21.39#ibcon#about to write, iclass 26, count 2 2006.196.07:38:21.39#ibcon#wrote, iclass 26, count 2 2006.196.07:38:21.39#ibcon#about to read 3, iclass 26, count 2 2006.196.07:38:21.42#ibcon#read 3, iclass 26, count 2 2006.196.07:38:21.42#ibcon#about to read 4, iclass 26, count 2 2006.196.07:38:21.42#ibcon#read 4, iclass 26, count 2 2006.196.07:38:21.42#ibcon#about to read 5, iclass 26, count 2 2006.196.07:38:21.42#ibcon#read 5, iclass 26, count 2 2006.196.07:38:21.42#ibcon#about to read 6, iclass 26, count 2 2006.196.07:38:21.42#ibcon#read 6, iclass 26, count 2 2006.196.07:38:21.42#ibcon#end of sib2, iclass 26, count 2 2006.196.07:38:21.42#ibcon#*after write, iclass 26, count 2 2006.196.07:38:21.42#ibcon#*before return 0, iclass 26, count 2 2006.196.07:38:21.42#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.196.07:38:21.42#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.196.07:38:21.42#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.196.07:38:21.42#ibcon#ireg 7 cls_cnt 0 2006.196.07:38:21.42#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.196.07:38:21.54#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.196.07:38:21.54#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.196.07:38:21.54#ibcon#enter wrdev, iclass 26, count 0 2006.196.07:38:21.54#ibcon#first serial, iclass 26, count 0 2006.196.07:38:21.54#ibcon#enter sib2, iclass 26, count 0 2006.196.07:38:21.54#ibcon#flushed, iclass 26, count 0 2006.196.07:38:21.54#ibcon#about to write, iclass 26, count 0 2006.196.07:38:21.54#ibcon#wrote, iclass 26, count 0 2006.196.07:38:21.54#ibcon#about to read 3, iclass 26, count 0 2006.196.07:38:21.56#ibcon#read 3, iclass 26, count 0 2006.196.07:38:21.56#ibcon#about to read 4, iclass 26, count 0 2006.196.07:38:21.56#ibcon#read 4, iclass 26, count 0 2006.196.07:38:21.56#ibcon#about to read 5, iclass 26, count 0 2006.196.07:38:21.56#ibcon#read 5, iclass 26, count 0 2006.196.07:38:21.56#ibcon#about to read 6, iclass 26, count 0 2006.196.07:38:21.56#ibcon#read 6, iclass 26, count 0 2006.196.07:38:21.56#ibcon#end of sib2, iclass 26, count 0 2006.196.07:38:21.56#ibcon#*mode == 0, iclass 26, count 0 2006.196.07:38:21.56#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.196.07:38:21.56#ibcon#[27=USB\r\n] 2006.196.07:38:21.56#ibcon#*before write, iclass 26, count 0 2006.196.07:38:21.56#ibcon#enter sib2, iclass 26, count 0 2006.196.07:38:21.56#ibcon#flushed, iclass 26, count 0 2006.196.07:38:21.56#ibcon#about to write, iclass 26, count 0 2006.196.07:38:21.56#ibcon#wrote, iclass 26, count 0 2006.196.07:38:21.56#ibcon#about to read 3, iclass 26, count 0 2006.196.07:38:21.59#ibcon#read 3, iclass 26, count 0 2006.196.07:38:21.59#ibcon#about to read 4, iclass 26, count 0 2006.196.07:38:21.59#ibcon#read 4, iclass 26, count 0 2006.196.07:38:21.59#ibcon#about to read 5, iclass 26, count 0 2006.196.07:38:21.59#ibcon#read 5, iclass 26, count 0 2006.196.07:38:21.59#ibcon#about to read 6, iclass 26, count 0 2006.196.07:38:21.59#ibcon#read 6, iclass 26, count 0 2006.196.07:38:21.59#ibcon#end of sib2, iclass 26, count 0 2006.196.07:38:21.59#ibcon#*after write, iclass 26, count 0 2006.196.07:38:21.59#ibcon#*before return 0, iclass 26, count 0 2006.196.07:38:21.59#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.196.07:38:21.59#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.196.07:38:21.59#ibcon#about to clear, iclass 26 cls_cnt 0 2006.196.07:38:21.59#ibcon#cleared, iclass 26 cls_cnt 0 2006.196.07:38:21.59$vc4f8/vblo=4,712.99 2006.196.07:38:21.59#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.196.07:38:21.59#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.196.07:38:21.59#ibcon#ireg 17 cls_cnt 0 2006.196.07:38:21.59#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.196.07:38:21.59#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.196.07:38:21.59#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.196.07:38:21.59#ibcon#enter wrdev, iclass 28, count 0 2006.196.07:38:21.59#ibcon#first serial, iclass 28, count 0 2006.196.07:38:21.59#ibcon#enter sib2, iclass 28, count 0 2006.196.07:38:21.59#ibcon#flushed, iclass 28, count 0 2006.196.07:38:21.59#ibcon#about to write, iclass 28, count 0 2006.196.07:38:21.59#ibcon#wrote, iclass 28, count 0 2006.196.07:38:21.59#ibcon#about to read 3, iclass 28, count 0 2006.196.07:38:21.61#ibcon#read 3, iclass 28, count 0 2006.196.07:38:21.61#ibcon#about to read 4, iclass 28, count 0 2006.196.07:38:21.61#ibcon#read 4, iclass 28, count 0 2006.196.07:38:21.61#ibcon#about to read 5, iclass 28, count 0 2006.196.07:38:21.61#ibcon#read 5, iclass 28, count 0 2006.196.07:38:21.61#ibcon#about to read 6, iclass 28, count 0 2006.196.07:38:21.61#ibcon#read 6, iclass 28, count 0 2006.196.07:38:21.61#ibcon#end of sib2, iclass 28, count 0 2006.196.07:38:21.61#ibcon#*mode == 0, iclass 28, count 0 2006.196.07:38:21.61#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.196.07:38:21.61#ibcon#[28=FRQ=04,712.99\r\n] 2006.196.07:38:21.61#ibcon#*before write, iclass 28, count 0 2006.196.07:38:21.61#ibcon#enter sib2, iclass 28, count 0 2006.196.07:38:21.61#ibcon#flushed, iclass 28, count 0 2006.196.07:38:21.61#ibcon#about to write, iclass 28, count 0 2006.196.07:38:21.61#ibcon#wrote, iclass 28, count 0 2006.196.07:38:21.61#ibcon#about to read 3, iclass 28, count 0 2006.196.07:38:21.65#ibcon#read 3, iclass 28, count 0 2006.196.07:38:21.65#ibcon#about to read 4, iclass 28, count 0 2006.196.07:38:21.65#ibcon#read 4, iclass 28, count 0 2006.196.07:38:21.65#ibcon#about to read 5, iclass 28, count 0 2006.196.07:38:21.65#ibcon#read 5, iclass 28, count 0 2006.196.07:38:21.65#ibcon#about to read 6, iclass 28, count 0 2006.196.07:38:21.65#ibcon#read 6, iclass 28, count 0 2006.196.07:38:21.65#ibcon#end of sib2, iclass 28, count 0 2006.196.07:38:21.65#ibcon#*after write, iclass 28, count 0 2006.196.07:38:21.65#ibcon#*before return 0, iclass 28, count 0 2006.196.07:38:21.65#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.196.07:38:21.65#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.196.07:38:21.65#ibcon#about to clear, iclass 28 cls_cnt 0 2006.196.07:38:21.65#ibcon#cleared, iclass 28 cls_cnt 0 2006.196.07:38:21.65$vc4f8/vb=4,4 2006.196.07:38:21.65#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.196.07:38:21.65#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.196.07:38:21.65#ibcon#ireg 11 cls_cnt 2 2006.196.07:38:21.65#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.196.07:38:21.71#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.196.07:38:21.71#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.196.07:38:21.71#ibcon#enter wrdev, iclass 30, count 2 2006.196.07:38:21.71#ibcon#first serial, iclass 30, count 2 2006.196.07:38:21.71#ibcon#enter sib2, iclass 30, count 2 2006.196.07:38:21.71#ibcon#flushed, iclass 30, count 2 2006.196.07:38:21.71#ibcon#about to write, iclass 30, count 2 2006.196.07:38:21.71#ibcon#wrote, iclass 30, count 2 2006.196.07:38:21.71#ibcon#about to read 3, iclass 30, count 2 2006.196.07:38:21.73#ibcon#read 3, iclass 30, count 2 2006.196.07:38:21.73#ibcon#about to read 4, iclass 30, count 2 2006.196.07:38:21.73#ibcon#read 4, iclass 30, count 2 2006.196.07:38:21.73#ibcon#about to read 5, iclass 30, count 2 2006.196.07:38:21.73#ibcon#read 5, iclass 30, count 2 2006.196.07:38:21.73#ibcon#about to read 6, iclass 30, count 2 2006.196.07:38:21.73#ibcon#read 6, iclass 30, count 2 2006.196.07:38:21.73#ibcon#end of sib2, iclass 30, count 2 2006.196.07:38:21.73#ibcon#*mode == 0, iclass 30, count 2 2006.196.07:38:21.73#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.196.07:38:21.73#ibcon#[27=AT04-04\r\n] 2006.196.07:38:21.73#ibcon#*before write, iclass 30, count 2 2006.196.07:38:21.73#ibcon#enter sib2, iclass 30, count 2 2006.196.07:38:21.73#ibcon#flushed, iclass 30, count 2 2006.196.07:38:21.73#ibcon#about to write, iclass 30, count 2 2006.196.07:38:21.73#ibcon#wrote, iclass 30, count 2 2006.196.07:38:21.73#ibcon#about to read 3, iclass 30, count 2 2006.196.07:38:21.76#ibcon#read 3, iclass 30, count 2 2006.196.07:38:21.76#ibcon#about to read 4, iclass 30, count 2 2006.196.07:38:21.76#ibcon#read 4, iclass 30, count 2 2006.196.07:38:21.76#ibcon#about to read 5, iclass 30, count 2 2006.196.07:38:21.76#ibcon#read 5, iclass 30, count 2 2006.196.07:38:21.76#ibcon#about to read 6, iclass 30, count 2 2006.196.07:38:21.76#ibcon#read 6, iclass 30, count 2 2006.196.07:38:21.76#ibcon#end of sib2, iclass 30, count 2 2006.196.07:38:21.76#ibcon#*after write, iclass 30, count 2 2006.196.07:38:21.76#ibcon#*before return 0, iclass 30, count 2 2006.196.07:38:21.76#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.196.07:38:21.76#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.196.07:38:21.76#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.196.07:38:21.76#ibcon#ireg 7 cls_cnt 0 2006.196.07:38:21.76#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.196.07:38:21.88#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.196.07:38:21.88#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.196.07:38:21.88#ibcon#enter wrdev, iclass 30, count 0 2006.196.07:38:21.88#ibcon#first serial, iclass 30, count 0 2006.196.07:38:21.88#ibcon#enter sib2, iclass 30, count 0 2006.196.07:38:21.88#ibcon#flushed, iclass 30, count 0 2006.196.07:38:21.88#ibcon#about to write, iclass 30, count 0 2006.196.07:38:21.88#ibcon#wrote, iclass 30, count 0 2006.196.07:38:21.88#ibcon#about to read 3, iclass 30, count 0 2006.196.07:38:21.90#ibcon#read 3, iclass 30, count 0 2006.196.07:38:21.90#ibcon#about to read 4, iclass 30, count 0 2006.196.07:38:21.90#ibcon#read 4, iclass 30, count 0 2006.196.07:38:21.90#ibcon#about to read 5, iclass 30, count 0 2006.196.07:38:21.90#ibcon#read 5, iclass 30, count 0 2006.196.07:38:21.90#ibcon#about to read 6, iclass 30, count 0 2006.196.07:38:21.90#ibcon#read 6, iclass 30, count 0 2006.196.07:38:21.90#ibcon#end of sib2, iclass 30, count 0 2006.196.07:38:21.90#ibcon#*mode == 0, iclass 30, count 0 2006.196.07:38:21.90#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.196.07:38:21.90#ibcon#[27=USB\r\n] 2006.196.07:38:21.90#ibcon#*before write, iclass 30, count 0 2006.196.07:38:21.90#ibcon#enter sib2, iclass 30, count 0 2006.196.07:38:21.90#ibcon#flushed, iclass 30, count 0 2006.196.07:38:21.90#ibcon#about to write, iclass 30, count 0 2006.196.07:38:21.90#ibcon#wrote, iclass 30, count 0 2006.196.07:38:21.90#ibcon#about to read 3, iclass 30, count 0 2006.196.07:38:21.93#ibcon#read 3, iclass 30, count 0 2006.196.07:38:21.93#ibcon#about to read 4, iclass 30, count 0 2006.196.07:38:21.93#ibcon#read 4, iclass 30, count 0 2006.196.07:38:21.93#ibcon#about to read 5, iclass 30, count 0 2006.196.07:38:21.93#ibcon#read 5, iclass 30, count 0 2006.196.07:38:21.93#ibcon#about to read 6, iclass 30, count 0 2006.196.07:38:21.93#ibcon#read 6, iclass 30, count 0 2006.196.07:38:21.93#ibcon#end of sib2, iclass 30, count 0 2006.196.07:38:21.93#ibcon#*after write, iclass 30, count 0 2006.196.07:38:21.93#ibcon#*before return 0, iclass 30, count 0 2006.196.07:38:21.93#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.196.07:38:21.93#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.196.07:38:21.93#ibcon#about to clear, iclass 30 cls_cnt 0 2006.196.07:38:21.93#ibcon#cleared, iclass 30 cls_cnt 0 2006.196.07:38:21.93$vc4f8/vblo=5,744.99 2006.196.07:38:21.93#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.196.07:38:21.93#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.196.07:38:21.93#ibcon#ireg 17 cls_cnt 0 2006.196.07:38:21.93#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.196.07:38:21.93#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.196.07:38:21.93#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.196.07:38:21.93#ibcon#enter wrdev, iclass 32, count 0 2006.196.07:38:21.93#ibcon#first serial, iclass 32, count 0 2006.196.07:38:21.93#ibcon#enter sib2, iclass 32, count 0 2006.196.07:38:21.93#ibcon#flushed, iclass 32, count 0 2006.196.07:38:21.93#ibcon#about to write, iclass 32, count 0 2006.196.07:38:21.93#ibcon#wrote, iclass 32, count 0 2006.196.07:38:21.93#ibcon#about to read 3, iclass 32, count 0 2006.196.07:38:21.95#ibcon#read 3, iclass 32, count 0 2006.196.07:38:21.95#ibcon#about to read 4, iclass 32, count 0 2006.196.07:38:21.95#ibcon#read 4, iclass 32, count 0 2006.196.07:38:21.95#ibcon#about to read 5, iclass 32, count 0 2006.196.07:38:21.95#ibcon#read 5, iclass 32, count 0 2006.196.07:38:21.95#ibcon#about to read 6, iclass 32, count 0 2006.196.07:38:21.95#ibcon#read 6, iclass 32, count 0 2006.196.07:38:21.95#ibcon#end of sib2, iclass 32, count 0 2006.196.07:38:21.95#ibcon#*mode == 0, iclass 32, count 0 2006.196.07:38:21.95#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.196.07:38:21.95#ibcon#[28=FRQ=05,744.99\r\n] 2006.196.07:38:21.95#ibcon#*before write, iclass 32, count 0 2006.196.07:38:21.95#ibcon#enter sib2, iclass 32, count 0 2006.196.07:38:21.95#ibcon#flushed, iclass 32, count 0 2006.196.07:38:21.95#ibcon#about to write, iclass 32, count 0 2006.196.07:38:21.95#ibcon#wrote, iclass 32, count 0 2006.196.07:38:21.95#ibcon#about to read 3, iclass 32, count 0 2006.196.07:38:21.99#ibcon#read 3, iclass 32, count 0 2006.196.07:38:21.99#ibcon#about to read 4, iclass 32, count 0 2006.196.07:38:21.99#ibcon#read 4, iclass 32, count 0 2006.196.07:38:21.99#ibcon#about to read 5, iclass 32, count 0 2006.196.07:38:21.99#ibcon#read 5, iclass 32, count 0 2006.196.07:38:21.99#ibcon#about to read 6, iclass 32, count 0 2006.196.07:38:21.99#ibcon#read 6, iclass 32, count 0 2006.196.07:38:21.99#ibcon#end of sib2, iclass 32, count 0 2006.196.07:38:21.99#ibcon#*after write, iclass 32, count 0 2006.196.07:38:21.99#ibcon#*before return 0, iclass 32, count 0 2006.196.07:38:21.99#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.196.07:38:21.99#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.196.07:38:21.99#ibcon#about to clear, iclass 32 cls_cnt 0 2006.196.07:38:21.99#ibcon#cleared, iclass 32 cls_cnt 0 2006.196.07:38:21.99$vc4f8/vb=5,4 2006.196.07:38:21.99#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.196.07:38:21.99#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.196.07:38:21.99#ibcon#ireg 11 cls_cnt 2 2006.196.07:38:21.99#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.196.07:38:22.05#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.196.07:38:22.05#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.196.07:38:22.05#ibcon#enter wrdev, iclass 34, count 2 2006.196.07:38:22.05#ibcon#first serial, iclass 34, count 2 2006.196.07:38:22.05#ibcon#enter sib2, iclass 34, count 2 2006.196.07:38:22.05#ibcon#flushed, iclass 34, count 2 2006.196.07:38:22.05#ibcon#about to write, iclass 34, count 2 2006.196.07:38:22.05#ibcon#wrote, iclass 34, count 2 2006.196.07:38:22.05#ibcon#about to read 3, iclass 34, count 2 2006.196.07:38:22.07#ibcon#read 3, iclass 34, count 2 2006.196.07:38:22.07#ibcon#about to read 4, iclass 34, count 2 2006.196.07:38:22.07#ibcon#read 4, iclass 34, count 2 2006.196.07:38:22.07#ibcon#about to read 5, iclass 34, count 2 2006.196.07:38:22.07#ibcon#read 5, iclass 34, count 2 2006.196.07:38:22.07#ibcon#about to read 6, iclass 34, count 2 2006.196.07:38:22.07#ibcon#read 6, iclass 34, count 2 2006.196.07:38:22.07#ibcon#end of sib2, iclass 34, count 2 2006.196.07:38:22.07#ibcon#*mode == 0, iclass 34, count 2 2006.196.07:38:22.07#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.196.07:38:22.07#ibcon#[27=AT05-04\r\n] 2006.196.07:38:22.07#ibcon#*before write, iclass 34, count 2 2006.196.07:38:22.07#ibcon#enter sib2, iclass 34, count 2 2006.196.07:38:22.07#ibcon#flushed, iclass 34, count 2 2006.196.07:38:22.07#ibcon#about to write, iclass 34, count 2 2006.196.07:38:22.07#ibcon#wrote, iclass 34, count 2 2006.196.07:38:22.07#ibcon#about to read 3, iclass 34, count 2 2006.196.07:38:22.10#ibcon#read 3, iclass 34, count 2 2006.196.07:38:22.10#ibcon#about to read 4, iclass 34, count 2 2006.196.07:38:22.10#ibcon#read 4, iclass 34, count 2 2006.196.07:38:22.10#ibcon#about to read 5, iclass 34, count 2 2006.196.07:38:22.10#ibcon#read 5, iclass 34, count 2 2006.196.07:38:22.10#ibcon#about to read 6, iclass 34, count 2 2006.196.07:38:22.10#ibcon#read 6, iclass 34, count 2 2006.196.07:38:22.10#ibcon#end of sib2, iclass 34, count 2 2006.196.07:38:22.10#ibcon#*after write, iclass 34, count 2 2006.196.07:38:22.10#ibcon#*before return 0, iclass 34, count 2 2006.196.07:38:22.10#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.196.07:38:22.10#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.196.07:38:22.10#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.196.07:38:22.10#ibcon#ireg 7 cls_cnt 0 2006.196.07:38:22.10#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.196.07:38:22.22#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.196.07:38:22.22#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.196.07:38:22.22#ibcon#enter wrdev, iclass 34, count 0 2006.196.07:38:22.22#ibcon#first serial, iclass 34, count 0 2006.196.07:38:22.22#ibcon#enter sib2, iclass 34, count 0 2006.196.07:38:22.22#ibcon#flushed, iclass 34, count 0 2006.196.07:38:22.22#ibcon#about to write, iclass 34, count 0 2006.196.07:38:22.22#ibcon#wrote, iclass 34, count 0 2006.196.07:38:22.22#ibcon#about to read 3, iclass 34, count 0 2006.196.07:38:22.24#ibcon#read 3, iclass 34, count 0 2006.196.07:38:22.24#ibcon#about to read 4, iclass 34, count 0 2006.196.07:38:22.24#ibcon#read 4, iclass 34, count 0 2006.196.07:38:22.24#ibcon#about to read 5, iclass 34, count 0 2006.196.07:38:22.24#ibcon#read 5, iclass 34, count 0 2006.196.07:38:22.24#ibcon#about to read 6, iclass 34, count 0 2006.196.07:38:22.24#ibcon#read 6, iclass 34, count 0 2006.196.07:38:22.24#ibcon#end of sib2, iclass 34, count 0 2006.196.07:38:22.24#ibcon#*mode == 0, iclass 34, count 0 2006.196.07:38:22.24#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.196.07:38:22.24#ibcon#[27=USB\r\n] 2006.196.07:38:22.24#ibcon#*before write, iclass 34, count 0 2006.196.07:38:22.24#ibcon#enter sib2, iclass 34, count 0 2006.196.07:38:22.24#ibcon#flushed, iclass 34, count 0 2006.196.07:38:22.24#ibcon#about to write, iclass 34, count 0 2006.196.07:38:22.24#ibcon#wrote, iclass 34, count 0 2006.196.07:38:22.24#ibcon#about to read 3, iclass 34, count 0 2006.196.07:38:22.27#ibcon#read 3, iclass 34, count 0 2006.196.07:38:22.27#ibcon#about to read 4, iclass 34, count 0 2006.196.07:38:22.27#ibcon#read 4, iclass 34, count 0 2006.196.07:38:22.27#ibcon#about to read 5, iclass 34, count 0 2006.196.07:38:22.27#ibcon#read 5, iclass 34, count 0 2006.196.07:38:22.27#ibcon#about to read 6, iclass 34, count 0 2006.196.07:38:22.27#ibcon#read 6, iclass 34, count 0 2006.196.07:38:22.27#ibcon#end of sib2, iclass 34, count 0 2006.196.07:38:22.27#ibcon#*after write, iclass 34, count 0 2006.196.07:38:22.27#ibcon#*before return 0, iclass 34, count 0 2006.196.07:38:22.27#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.196.07:38:22.27#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.196.07:38:22.27#ibcon#about to clear, iclass 34 cls_cnt 0 2006.196.07:38:22.27#ibcon#cleared, iclass 34 cls_cnt 0 2006.196.07:38:22.27$vc4f8/vblo=6,752.99 2006.196.07:38:22.27#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.196.07:38:22.27#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.196.07:38:22.27#ibcon#ireg 17 cls_cnt 0 2006.196.07:38:22.27#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.196.07:38:22.27#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.196.07:38:22.27#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.196.07:38:22.27#ibcon#enter wrdev, iclass 36, count 0 2006.196.07:38:22.27#ibcon#first serial, iclass 36, count 0 2006.196.07:38:22.27#ibcon#enter sib2, iclass 36, count 0 2006.196.07:38:22.27#ibcon#flushed, iclass 36, count 0 2006.196.07:38:22.27#ibcon#about to write, iclass 36, count 0 2006.196.07:38:22.27#ibcon#wrote, iclass 36, count 0 2006.196.07:38:22.27#ibcon#about to read 3, iclass 36, count 0 2006.196.07:38:22.29#ibcon#read 3, iclass 36, count 0 2006.196.07:38:22.29#ibcon#about to read 4, iclass 36, count 0 2006.196.07:38:22.29#ibcon#read 4, iclass 36, count 0 2006.196.07:38:22.29#ibcon#about to read 5, iclass 36, count 0 2006.196.07:38:22.29#ibcon#read 5, iclass 36, count 0 2006.196.07:38:22.29#ibcon#about to read 6, iclass 36, count 0 2006.196.07:38:22.29#ibcon#read 6, iclass 36, count 0 2006.196.07:38:22.29#ibcon#end of sib2, iclass 36, count 0 2006.196.07:38:22.29#ibcon#*mode == 0, iclass 36, count 0 2006.196.07:38:22.29#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.196.07:38:22.29#ibcon#[28=FRQ=06,752.99\r\n] 2006.196.07:38:22.29#ibcon#*before write, iclass 36, count 0 2006.196.07:38:22.29#ibcon#enter sib2, iclass 36, count 0 2006.196.07:38:22.29#ibcon#flushed, iclass 36, count 0 2006.196.07:38:22.29#ibcon#about to write, iclass 36, count 0 2006.196.07:38:22.29#ibcon#wrote, iclass 36, count 0 2006.196.07:38:22.29#ibcon#about to read 3, iclass 36, count 0 2006.196.07:38:22.33#ibcon#read 3, iclass 36, count 0 2006.196.07:38:22.33#ibcon#about to read 4, iclass 36, count 0 2006.196.07:38:22.33#ibcon#read 4, iclass 36, count 0 2006.196.07:38:22.33#ibcon#about to read 5, iclass 36, count 0 2006.196.07:38:22.33#ibcon#read 5, iclass 36, count 0 2006.196.07:38:22.33#ibcon#about to read 6, iclass 36, count 0 2006.196.07:38:22.33#ibcon#read 6, iclass 36, count 0 2006.196.07:38:22.33#ibcon#end of sib2, iclass 36, count 0 2006.196.07:38:22.33#ibcon#*after write, iclass 36, count 0 2006.196.07:38:22.33#ibcon#*before return 0, iclass 36, count 0 2006.196.07:38:22.33#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.196.07:38:22.33#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.196.07:38:22.33#ibcon#about to clear, iclass 36 cls_cnt 0 2006.196.07:38:22.33#ibcon#cleared, iclass 36 cls_cnt 0 2006.196.07:38:22.33$vc4f8/vb=6,4 2006.196.07:38:22.33#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.196.07:38:22.33#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.196.07:38:22.33#ibcon#ireg 11 cls_cnt 2 2006.196.07:38:22.33#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.196.07:38:22.39#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.196.07:38:22.39#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.196.07:38:22.39#ibcon#enter wrdev, iclass 38, count 2 2006.196.07:38:22.39#ibcon#first serial, iclass 38, count 2 2006.196.07:38:22.39#ibcon#enter sib2, iclass 38, count 2 2006.196.07:38:22.39#ibcon#flushed, iclass 38, count 2 2006.196.07:38:22.39#ibcon#about to write, iclass 38, count 2 2006.196.07:38:22.39#ibcon#wrote, iclass 38, count 2 2006.196.07:38:22.39#ibcon#about to read 3, iclass 38, count 2 2006.196.07:38:22.41#ibcon#read 3, iclass 38, count 2 2006.196.07:38:22.41#ibcon#about to read 4, iclass 38, count 2 2006.196.07:38:22.41#ibcon#read 4, iclass 38, count 2 2006.196.07:38:22.41#ibcon#about to read 5, iclass 38, count 2 2006.196.07:38:22.41#ibcon#read 5, iclass 38, count 2 2006.196.07:38:22.41#ibcon#about to read 6, iclass 38, count 2 2006.196.07:38:22.41#ibcon#read 6, iclass 38, count 2 2006.196.07:38:22.41#ibcon#end of sib2, iclass 38, count 2 2006.196.07:38:22.41#ibcon#*mode == 0, iclass 38, count 2 2006.196.07:38:22.41#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.196.07:38:22.41#ibcon#[27=AT06-04\r\n] 2006.196.07:38:22.41#ibcon#*before write, iclass 38, count 2 2006.196.07:38:22.41#ibcon#enter sib2, iclass 38, count 2 2006.196.07:38:22.41#ibcon#flushed, iclass 38, count 2 2006.196.07:38:22.41#ibcon#about to write, iclass 38, count 2 2006.196.07:38:22.41#ibcon#wrote, iclass 38, count 2 2006.196.07:38:22.41#ibcon#about to read 3, iclass 38, count 2 2006.196.07:38:22.44#ibcon#read 3, iclass 38, count 2 2006.196.07:38:22.44#ibcon#about to read 4, iclass 38, count 2 2006.196.07:38:22.44#ibcon#read 4, iclass 38, count 2 2006.196.07:38:22.44#ibcon#about to read 5, iclass 38, count 2 2006.196.07:38:22.44#ibcon#read 5, iclass 38, count 2 2006.196.07:38:22.44#ibcon#about to read 6, iclass 38, count 2 2006.196.07:38:22.44#ibcon#read 6, iclass 38, count 2 2006.196.07:38:22.44#ibcon#end of sib2, iclass 38, count 2 2006.196.07:38:22.44#ibcon#*after write, iclass 38, count 2 2006.196.07:38:22.44#ibcon#*before return 0, iclass 38, count 2 2006.196.07:38:22.44#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.196.07:38:22.44#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.196.07:38:22.44#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.196.07:38:22.44#ibcon#ireg 7 cls_cnt 0 2006.196.07:38:22.44#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.196.07:38:22.56#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.196.07:38:22.56#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.196.07:38:22.56#ibcon#enter wrdev, iclass 38, count 0 2006.196.07:38:22.56#ibcon#first serial, iclass 38, count 0 2006.196.07:38:22.56#ibcon#enter sib2, iclass 38, count 0 2006.196.07:38:22.56#ibcon#flushed, iclass 38, count 0 2006.196.07:38:22.56#ibcon#about to write, iclass 38, count 0 2006.196.07:38:22.56#ibcon#wrote, iclass 38, count 0 2006.196.07:38:22.56#ibcon#about to read 3, iclass 38, count 0 2006.196.07:38:22.58#ibcon#read 3, iclass 38, count 0 2006.196.07:38:22.58#ibcon#about to read 4, iclass 38, count 0 2006.196.07:38:22.58#ibcon#read 4, iclass 38, count 0 2006.196.07:38:22.58#ibcon#about to read 5, iclass 38, count 0 2006.196.07:38:22.58#ibcon#read 5, iclass 38, count 0 2006.196.07:38:22.58#ibcon#about to read 6, iclass 38, count 0 2006.196.07:38:22.58#ibcon#read 6, iclass 38, count 0 2006.196.07:38:22.58#ibcon#end of sib2, iclass 38, count 0 2006.196.07:38:22.58#ibcon#*mode == 0, iclass 38, count 0 2006.196.07:38:22.58#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.196.07:38:22.58#ibcon#[27=USB\r\n] 2006.196.07:38:22.58#ibcon#*before write, iclass 38, count 0 2006.196.07:38:22.58#ibcon#enter sib2, iclass 38, count 0 2006.196.07:38:22.58#ibcon#flushed, iclass 38, count 0 2006.196.07:38:22.58#ibcon#about to write, iclass 38, count 0 2006.196.07:38:22.58#ibcon#wrote, iclass 38, count 0 2006.196.07:38:22.58#ibcon#about to read 3, iclass 38, count 0 2006.196.07:38:22.61#ibcon#read 3, iclass 38, count 0 2006.196.07:38:22.61#ibcon#about to read 4, iclass 38, count 0 2006.196.07:38:22.61#ibcon#read 4, iclass 38, count 0 2006.196.07:38:22.61#ibcon#about to read 5, iclass 38, count 0 2006.196.07:38:22.61#ibcon#read 5, iclass 38, count 0 2006.196.07:38:22.61#ibcon#about to read 6, iclass 38, count 0 2006.196.07:38:22.61#ibcon#read 6, iclass 38, count 0 2006.196.07:38:22.61#ibcon#end of sib2, iclass 38, count 0 2006.196.07:38:22.61#ibcon#*after write, iclass 38, count 0 2006.196.07:38:22.61#ibcon#*before return 0, iclass 38, count 0 2006.196.07:38:22.61#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.196.07:38:22.61#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.196.07:38:22.61#ibcon#about to clear, iclass 38 cls_cnt 0 2006.196.07:38:22.61#ibcon#cleared, iclass 38 cls_cnt 0 2006.196.07:38:22.61$vc4f8/vabw=wide 2006.196.07:38:22.61#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.196.07:38:22.61#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.196.07:38:22.61#ibcon#ireg 8 cls_cnt 0 2006.196.07:38:22.61#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.196.07:38:22.61#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.196.07:38:22.61#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.196.07:38:22.61#ibcon#enter wrdev, iclass 40, count 0 2006.196.07:38:22.61#ibcon#first serial, iclass 40, count 0 2006.196.07:38:22.61#ibcon#enter sib2, iclass 40, count 0 2006.196.07:38:22.61#ibcon#flushed, iclass 40, count 0 2006.196.07:38:22.61#ibcon#about to write, iclass 40, count 0 2006.196.07:38:22.61#ibcon#wrote, iclass 40, count 0 2006.196.07:38:22.61#ibcon#about to read 3, iclass 40, count 0 2006.196.07:38:22.63#ibcon#read 3, iclass 40, count 0 2006.196.07:38:22.63#ibcon#about to read 4, iclass 40, count 0 2006.196.07:38:22.63#ibcon#read 4, iclass 40, count 0 2006.196.07:38:22.63#ibcon#about to read 5, iclass 40, count 0 2006.196.07:38:22.63#ibcon#read 5, iclass 40, count 0 2006.196.07:38:22.63#ibcon#about to read 6, iclass 40, count 0 2006.196.07:38:22.63#ibcon#read 6, iclass 40, count 0 2006.196.07:38:22.63#ibcon#end of sib2, iclass 40, count 0 2006.196.07:38:22.63#ibcon#*mode == 0, iclass 40, count 0 2006.196.07:38:22.63#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.196.07:38:22.63#ibcon#[25=BW32\r\n] 2006.196.07:38:22.63#ibcon#*before write, iclass 40, count 0 2006.196.07:38:22.63#ibcon#enter sib2, iclass 40, count 0 2006.196.07:38:22.63#ibcon#flushed, iclass 40, count 0 2006.196.07:38:22.63#ibcon#about to write, iclass 40, count 0 2006.196.07:38:22.63#ibcon#wrote, iclass 40, count 0 2006.196.07:38:22.63#ibcon#about to read 3, iclass 40, count 0 2006.196.07:38:22.66#ibcon#read 3, iclass 40, count 0 2006.196.07:38:22.66#ibcon#about to read 4, iclass 40, count 0 2006.196.07:38:22.66#ibcon#read 4, iclass 40, count 0 2006.196.07:38:22.66#ibcon#about to read 5, iclass 40, count 0 2006.196.07:38:22.66#ibcon#read 5, iclass 40, count 0 2006.196.07:38:22.66#ibcon#about to read 6, iclass 40, count 0 2006.196.07:38:22.66#ibcon#read 6, iclass 40, count 0 2006.196.07:38:22.66#ibcon#end of sib2, iclass 40, count 0 2006.196.07:38:22.66#ibcon#*after write, iclass 40, count 0 2006.196.07:38:22.66#ibcon#*before return 0, iclass 40, count 0 2006.196.07:38:22.66#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.196.07:38:22.66#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.196.07:38:22.66#ibcon#about to clear, iclass 40 cls_cnt 0 2006.196.07:38:22.66#ibcon#cleared, iclass 40 cls_cnt 0 2006.196.07:38:22.66$vc4f8/vbbw=wide 2006.196.07:38:22.66#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.196.07:38:22.66#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.196.07:38:22.66#ibcon#ireg 8 cls_cnt 0 2006.196.07:38:22.66#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.196.07:38:22.73#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.196.07:38:22.73#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.196.07:38:22.73#ibcon#enter wrdev, iclass 4, count 0 2006.196.07:38:22.73#ibcon#first serial, iclass 4, count 0 2006.196.07:38:22.73#ibcon#enter sib2, iclass 4, count 0 2006.196.07:38:22.73#ibcon#flushed, iclass 4, count 0 2006.196.07:38:22.73#ibcon#about to write, iclass 4, count 0 2006.196.07:38:22.73#ibcon#wrote, iclass 4, count 0 2006.196.07:38:22.73#ibcon#about to read 3, iclass 4, count 0 2006.196.07:38:22.75#ibcon#read 3, iclass 4, count 0 2006.196.07:38:22.75#ibcon#about to read 4, iclass 4, count 0 2006.196.07:38:22.75#ibcon#read 4, iclass 4, count 0 2006.196.07:38:22.75#ibcon#about to read 5, iclass 4, count 0 2006.196.07:38:22.75#ibcon#read 5, iclass 4, count 0 2006.196.07:38:22.75#ibcon#about to read 6, iclass 4, count 0 2006.196.07:38:22.75#ibcon#read 6, iclass 4, count 0 2006.196.07:38:22.75#ibcon#end of sib2, iclass 4, count 0 2006.196.07:38:22.75#ibcon#*mode == 0, iclass 4, count 0 2006.196.07:38:22.75#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.196.07:38:22.75#ibcon#[27=BW32\r\n] 2006.196.07:38:22.75#ibcon#*before write, iclass 4, count 0 2006.196.07:38:22.75#ibcon#enter sib2, iclass 4, count 0 2006.196.07:38:22.75#ibcon#flushed, iclass 4, count 0 2006.196.07:38:22.75#ibcon#about to write, iclass 4, count 0 2006.196.07:38:22.75#ibcon#wrote, iclass 4, count 0 2006.196.07:38:22.75#ibcon#about to read 3, iclass 4, count 0 2006.196.07:38:22.78#ibcon#read 3, iclass 4, count 0 2006.196.07:38:22.78#ibcon#about to read 4, iclass 4, count 0 2006.196.07:38:22.78#ibcon#read 4, iclass 4, count 0 2006.196.07:38:22.78#ibcon#about to read 5, iclass 4, count 0 2006.196.07:38:22.78#ibcon#read 5, iclass 4, count 0 2006.196.07:38:22.78#ibcon#about to read 6, iclass 4, count 0 2006.196.07:38:22.78#ibcon#read 6, iclass 4, count 0 2006.196.07:38:22.78#ibcon#end of sib2, iclass 4, count 0 2006.196.07:38:22.78#ibcon#*after write, iclass 4, count 0 2006.196.07:38:22.78#ibcon#*before return 0, iclass 4, count 0 2006.196.07:38:22.78#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.196.07:38:22.78#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.196.07:38:22.78#ibcon#about to clear, iclass 4 cls_cnt 0 2006.196.07:38:22.78#ibcon#cleared, iclass 4 cls_cnt 0 2006.196.07:38:22.78$4f8m12a/ifd4f 2006.196.07:38:22.78$ifd4f/lo= 2006.196.07:38:22.78$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.196.07:38:22.78$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.196.07:38:22.78$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.196.07:38:22.78$ifd4f/patch= 2006.196.07:38:22.78$ifd4f/patch=lo1,a1,a2,a3,a4 2006.196.07:38:22.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.196.07:38:22.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.196.07:38:22.78$4f8m12a/"form=m,16.000,1:2 2006.196.07:38:22.78$4f8m12a/"tpicd 2006.196.07:38:22.78$4f8m12a/echo=off 2006.196.07:38:22.78$4f8m12a/xlog=off 2006.196.07:38:22.78:!2006.196.07:38:50 2006.196.07:38:30.14#trakl#Source acquired 2006.196.07:38:32.14#flagr#flagr/antenna,acquired 2006.196.07:38:50.00:preob 2006.196.07:38:51.14/onsource/TRACKING 2006.196.07:38:51.14:!2006.196.07:39:00 2006.196.07:39:00.00:data_valid=on 2006.196.07:39:00.00:midob 2006.196.07:39:00.14/onsource/TRACKING 2006.196.07:39:00.14/wx/30.02,1004.0,86 2006.196.07:39:00.30/cable/+6.3325E-03 2006.196.07:39:01.39/va/01,08,usb,yes,29,31 2006.196.07:39:01.39/va/02,07,usb,yes,30,31 2006.196.07:39:01.39/va/03,06,usb,yes,31,31 2006.196.07:39:01.39/va/04,07,usb,yes,31,33 2006.196.07:39:01.39/va/05,07,usb,yes,32,34 2006.196.07:39:01.39/va/06,06,usb,yes,31,31 2006.196.07:39:01.39/va/07,06,usb,yes,32,31 2006.196.07:39:01.39/va/08,07,usb,yes,30,29 2006.196.07:39:01.62/valo/01,532.99,yes,locked 2006.196.07:39:01.62/valo/02,572.99,yes,locked 2006.196.07:39:01.62/valo/03,672.99,yes,locked 2006.196.07:39:01.62/valo/04,832.99,yes,locked 2006.196.07:39:01.62/valo/05,652.99,yes,locked 2006.196.07:39:01.62/valo/06,772.99,yes,locked 2006.196.07:39:01.62/valo/07,832.99,yes,locked 2006.196.07:39:01.62/valo/08,852.99,yes,locked 2006.196.07:39:02.71/vb/01,04,usb,yes,29,28 2006.196.07:39:02.71/vb/02,04,usb,yes,31,32 2006.196.07:39:02.71/vb/03,04,usb,yes,27,31 2006.196.07:39:02.71/vb/04,04,usb,yes,28,28 2006.196.07:39:02.71/vb/05,04,usb,yes,27,31 2006.196.07:39:02.71/vb/06,04,usb,yes,28,30 2006.196.07:39:02.71/vb/07,04,usb,yes,30,30 2006.196.07:39:02.71/vb/08,04,usb,yes,27,31 2006.196.07:39:02.95/vblo/01,632.99,yes,locked 2006.196.07:39:02.95/vblo/02,640.99,yes,locked 2006.196.07:39:02.95/vblo/03,656.99,yes,locked 2006.196.07:39:02.95/vblo/04,712.99,yes,locked 2006.196.07:39:02.95/vblo/05,744.99,yes,locked 2006.196.07:39:02.95/vblo/06,752.99,yes,locked 2006.196.07:39:02.95/vblo/07,734.99,yes,locked 2006.196.07:39:02.95/vblo/08,744.99,yes,locked 2006.196.07:39:03.10/vabw/8 2006.196.07:39:03.25/vbbw/8 2006.196.07:39:03.34/xfe/off,on,15.2 2006.196.07:39:03.71/ifatt/23,28,28,28 2006.196.07:39:04.06/fmout-gps/S +3.36E-07 2006.196.07:39:04.13:!2006.196.07:40:00 2006.196.07:40:00.00:data_valid=off 2006.196.07:40:00.00:postob 2006.196.07:40:00.10/cable/+6.3336E-03 2006.196.07:40:00.10/wx/29.98,1004.0,85 2006.196.07:40:01.06/fmout-gps/S +3.35E-07 2006.196.07:40:01.06:scan_name=196-0740,k06196,60 2006.196.07:40:01.06:source=1803+784,180045.68,782804.0,2000.0,cw 2006.196.07:40:01.14#flagr#flagr/antenna,new-source 2006.196.07:40:02.14:checkk5 2006.196.07:40:02.51/chk_autoobs//k5ts1/ autoobs is running! 2006.196.07:40:02.89/chk_autoobs//k5ts2/ autoobs is running! 2006.196.07:40:03.27/chk_autoobs//k5ts3/ autoobs is running! 2006.196.07:40:03.64/chk_autoobs//k5ts4/ autoobs is running! 2006.196.07:40:04.01/chk_obsdata//k5ts1/T1960739??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.07:40:04.38/chk_obsdata//k5ts2/T1960739??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.07:40:04.74/chk_obsdata//k5ts3/T1960739??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.07:40:05.12/chk_obsdata//k5ts4/T1960739??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.07:40:05.81/k5log//k5ts1_log_newline 2006.196.07:40:06.51/k5log//k5ts2_log_newline 2006.196.07:40:07.19/k5log//k5ts3_log_newline 2006.196.07:40:07.89/k5log//k5ts4_log_newline 2006.196.07:40:07.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.196.07:40:07.91:4f8m12a=1 2006.196.07:40:07.91$4f8m12a/echo=on 2006.196.07:40:07.91$4f8m12a/pcalon 2006.196.07:40:07.91$pcalon/"no phase cal control is implemented here 2006.196.07:40:07.91$4f8m12a/"tpicd=stop 2006.196.07:40:07.91$4f8m12a/vc4f8 2006.196.07:40:07.91$vc4f8/valo=1,532.99 2006.196.07:40:07.92#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.196.07:40:07.92#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.196.07:40:07.92#ibcon#ireg 17 cls_cnt 0 2006.196.07:40:07.92#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.196.07:40:07.92#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.196.07:40:07.92#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.196.07:40:07.92#ibcon#enter wrdev, iclass 17, count 0 2006.196.07:40:07.92#ibcon#first serial, iclass 17, count 0 2006.196.07:40:07.92#ibcon#enter sib2, iclass 17, count 0 2006.196.07:40:07.92#ibcon#flushed, iclass 17, count 0 2006.196.07:40:07.92#ibcon#about to write, iclass 17, count 0 2006.196.07:40:07.92#ibcon#wrote, iclass 17, count 0 2006.196.07:40:07.92#ibcon#about to read 3, iclass 17, count 0 2006.196.07:40:07.96#ibcon#read 3, iclass 17, count 0 2006.196.07:40:07.96#ibcon#about to read 4, iclass 17, count 0 2006.196.07:40:07.96#ibcon#read 4, iclass 17, count 0 2006.196.07:40:07.96#ibcon#about to read 5, iclass 17, count 0 2006.196.07:40:07.96#ibcon#read 5, iclass 17, count 0 2006.196.07:40:07.96#ibcon#about to read 6, iclass 17, count 0 2006.196.07:40:07.96#ibcon#read 6, iclass 17, count 0 2006.196.07:40:07.96#ibcon#end of sib2, iclass 17, count 0 2006.196.07:40:07.96#ibcon#*mode == 0, iclass 17, count 0 2006.196.07:40:07.96#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.196.07:40:07.96#ibcon#[26=FRQ=01,532.99\r\n] 2006.196.07:40:07.96#ibcon#*before write, iclass 17, count 0 2006.196.07:40:07.96#ibcon#enter sib2, iclass 17, count 0 2006.196.07:40:07.96#ibcon#flushed, iclass 17, count 0 2006.196.07:40:07.96#ibcon#about to write, iclass 17, count 0 2006.196.07:40:07.96#ibcon#wrote, iclass 17, count 0 2006.196.07:40:07.96#ibcon#about to read 3, iclass 17, count 0 2006.196.07:40:08.01#ibcon#read 3, iclass 17, count 0 2006.196.07:40:08.01#ibcon#about to read 4, iclass 17, count 0 2006.196.07:40:08.01#ibcon#read 4, iclass 17, count 0 2006.196.07:40:08.01#ibcon#about to read 5, iclass 17, count 0 2006.196.07:40:08.01#ibcon#read 5, iclass 17, count 0 2006.196.07:40:08.01#ibcon#about to read 6, iclass 17, count 0 2006.196.07:40:08.01#ibcon#read 6, iclass 17, count 0 2006.196.07:40:08.01#ibcon#end of sib2, iclass 17, count 0 2006.196.07:40:08.01#ibcon#*after write, iclass 17, count 0 2006.196.07:40:08.01#ibcon#*before return 0, iclass 17, count 0 2006.196.07:40:08.01#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.196.07:40:08.01#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.196.07:40:08.01#ibcon#about to clear, iclass 17 cls_cnt 0 2006.196.07:40:08.01#ibcon#cleared, iclass 17 cls_cnt 0 2006.196.07:40:08.01$vc4f8/va=1,8 2006.196.07:40:08.01#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.196.07:40:08.01#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.196.07:40:08.01#ibcon#ireg 11 cls_cnt 2 2006.196.07:40:08.01#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.196.07:40:08.01#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.196.07:40:08.01#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.196.07:40:08.01#ibcon#enter wrdev, iclass 19, count 2 2006.196.07:40:08.01#ibcon#first serial, iclass 19, count 2 2006.196.07:40:08.01#ibcon#enter sib2, iclass 19, count 2 2006.196.07:40:08.01#ibcon#flushed, iclass 19, count 2 2006.196.07:40:08.01#ibcon#about to write, iclass 19, count 2 2006.196.07:40:08.01#ibcon#wrote, iclass 19, count 2 2006.196.07:40:08.01#ibcon#about to read 3, iclass 19, count 2 2006.196.07:40:08.03#ibcon#read 3, iclass 19, count 2 2006.196.07:40:08.03#ibcon#about to read 4, iclass 19, count 2 2006.196.07:40:08.03#ibcon#read 4, iclass 19, count 2 2006.196.07:40:08.03#ibcon#about to read 5, iclass 19, count 2 2006.196.07:40:08.03#ibcon#read 5, iclass 19, count 2 2006.196.07:40:08.03#ibcon#about to read 6, iclass 19, count 2 2006.196.07:40:08.03#ibcon#read 6, iclass 19, count 2 2006.196.07:40:08.03#ibcon#end of sib2, iclass 19, count 2 2006.196.07:40:08.03#ibcon#*mode == 0, iclass 19, count 2 2006.196.07:40:08.03#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.196.07:40:08.03#ibcon#[25=AT01-08\r\n] 2006.196.07:40:08.03#ibcon#*before write, iclass 19, count 2 2006.196.07:40:08.03#ibcon#enter sib2, iclass 19, count 2 2006.196.07:40:08.03#ibcon#flushed, iclass 19, count 2 2006.196.07:40:08.03#ibcon#about to write, iclass 19, count 2 2006.196.07:40:08.03#ibcon#wrote, iclass 19, count 2 2006.196.07:40:08.03#ibcon#about to read 3, iclass 19, count 2 2006.196.07:40:08.07#ibcon#read 3, iclass 19, count 2 2006.196.07:40:08.07#ibcon#about to read 4, iclass 19, count 2 2006.196.07:40:08.07#ibcon#read 4, iclass 19, count 2 2006.196.07:40:08.07#ibcon#about to read 5, iclass 19, count 2 2006.196.07:40:08.07#ibcon#read 5, iclass 19, count 2 2006.196.07:40:08.07#ibcon#about to read 6, iclass 19, count 2 2006.196.07:40:08.07#ibcon#read 6, iclass 19, count 2 2006.196.07:40:08.07#ibcon#end of sib2, iclass 19, count 2 2006.196.07:40:08.07#ibcon#*after write, iclass 19, count 2 2006.196.07:40:08.07#ibcon#*before return 0, iclass 19, count 2 2006.196.07:40:08.07#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.196.07:40:08.07#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.196.07:40:08.07#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.196.07:40:08.07#ibcon#ireg 7 cls_cnt 0 2006.196.07:40:08.07#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.196.07:40:08.19#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.196.07:40:08.19#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.196.07:40:08.19#ibcon#enter wrdev, iclass 19, count 0 2006.196.07:40:08.19#ibcon#first serial, iclass 19, count 0 2006.196.07:40:08.19#ibcon#enter sib2, iclass 19, count 0 2006.196.07:40:08.19#ibcon#flushed, iclass 19, count 0 2006.196.07:40:08.19#ibcon#about to write, iclass 19, count 0 2006.196.07:40:08.19#ibcon#wrote, iclass 19, count 0 2006.196.07:40:08.19#ibcon#about to read 3, iclass 19, count 0 2006.196.07:40:08.22#ibcon#read 3, iclass 19, count 0 2006.196.07:40:08.22#ibcon#about to read 4, iclass 19, count 0 2006.196.07:40:08.22#ibcon#read 4, iclass 19, count 0 2006.196.07:40:08.22#ibcon#about to read 5, iclass 19, count 0 2006.196.07:40:08.22#ibcon#read 5, iclass 19, count 0 2006.196.07:40:08.22#ibcon#about to read 6, iclass 19, count 0 2006.196.07:40:08.22#ibcon#read 6, iclass 19, count 0 2006.196.07:40:08.22#ibcon#end of sib2, iclass 19, count 0 2006.196.07:40:08.22#ibcon#*mode == 0, iclass 19, count 0 2006.196.07:40:08.22#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.196.07:40:08.22#ibcon#[25=USB\r\n] 2006.196.07:40:08.22#ibcon#*before write, iclass 19, count 0 2006.196.07:40:08.22#ibcon#enter sib2, iclass 19, count 0 2006.196.07:40:08.22#ibcon#flushed, iclass 19, count 0 2006.196.07:40:08.22#ibcon#about to write, iclass 19, count 0 2006.196.07:40:08.22#ibcon#wrote, iclass 19, count 0 2006.196.07:40:08.22#ibcon#about to read 3, iclass 19, count 0 2006.196.07:40:08.25#ibcon#read 3, iclass 19, count 0 2006.196.07:40:08.25#ibcon#about to read 4, iclass 19, count 0 2006.196.07:40:08.25#ibcon#read 4, iclass 19, count 0 2006.196.07:40:08.25#ibcon#about to read 5, iclass 19, count 0 2006.196.07:40:08.25#ibcon#read 5, iclass 19, count 0 2006.196.07:40:08.25#ibcon#about to read 6, iclass 19, count 0 2006.196.07:40:08.25#ibcon#read 6, iclass 19, count 0 2006.196.07:40:08.25#ibcon#end of sib2, iclass 19, count 0 2006.196.07:40:08.25#ibcon#*after write, iclass 19, count 0 2006.196.07:40:08.25#ibcon#*before return 0, iclass 19, count 0 2006.196.07:40:08.25#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.196.07:40:08.25#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.196.07:40:08.25#ibcon#about to clear, iclass 19 cls_cnt 0 2006.196.07:40:08.25#ibcon#cleared, iclass 19 cls_cnt 0 2006.196.07:40:08.25$vc4f8/valo=2,572.99 2006.196.07:40:08.25#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.196.07:40:08.25#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.196.07:40:08.25#ibcon#ireg 17 cls_cnt 0 2006.196.07:40:08.25#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.196.07:40:08.25#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.196.07:40:08.25#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.196.07:40:08.25#ibcon#enter wrdev, iclass 21, count 0 2006.196.07:40:08.25#ibcon#first serial, iclass 21, count 0 2006.196.07:40:08.25#ibcon#enter sib2, iclass 21, count 0 2006.196.07:40:08.25#ibcon#flushed, iclass 21, count 0 2006.196.07:40:08.25#ibcon#about to write, iclass 21, count 0 2006.196.07:40:08.25#ibcon#wrote, iclass 21, count 0 2006.196.07:40:08.25#ibcon#about to read 3, iclass 21, count 0 2006.196.07:40:08.27#ibcon#read 3, iclass 21, count 0 2006.196.07:40:08.27#ibcon#about to read 4, iclass 21, count 0 2006.196.07:40:08.27#ibcon#read 4, iclass 21, count 0 2006.196.07:40:08.27#ibcon#about to read 5, iclass 21, count 0 2006.196.07:40:08.27#ibcon#read 5, iclass 21, count 0 2006.196.07:40:08.27#ibcon#about to read 6, iclass 21, count 0 2006.196.07:40:08.27#ibcon#read 6, iclass 21, count 0 2006.196.07:40:08.27#ibcon#end of sib2, iclass 21, count 0 2006.196.07:40:08.27#ibcon#*mode == 0, iclass 21, count 0 2006.196.07:40:08.27#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.196.07:40:08.27#ibcon#[26=FRQ=02,572.99\r\n] 2006.196.07:40:08.27#ibcon#*before write, iclass 21, count 0 2006.196.07:40:08.27#ibcon#enter sib2, iclass 21, count 0 2006.196.07:40:08.27#ibcon#flushed, iclass 21, count 0 2006.196.07:40:08.27#ibcon#about to write, iclass 21, count 0 2006.196.07:40:08.27#ibcon#wrote, iclass 21, count 0 2006.196.07:40:08.27#ibcon#about to read 3, iclass 21, count 0 2006.196.07:40:08.31#ibcon#read 3, iclass 21, count 0 2006.196.07:40:08.31#ibcon#about to read 4, iclass 21, count 0 2006.196.07:40:08.31#ibcon#read 4, iclass 21, count 0 2006.196.07:40:08.31#ibcon#about to read 5, iclass 21, count 0 2006.196.07:40:08.31#ibcon#read 5, iclass 21, count 0 2006.196.07:40:08.31#ibcon#about to read 6, iclass 21, count 0 2006.196.07:40:08.31#ibcon#read 6, iclass 21, count 0 2006.196.07:40:08.31#ibcon#end of sib2, iclass 21, count 0 2006.196.07:40:08.31#ibcon#*after write, iclass 21, count 0 2006.196.07:40:08.31#ibcon#*before return 0, iclass 21, count 0 2006.196.07:40:08.31#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.196.07:40:08.31#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.196.07:40:08.31#ibcon#about to clear, iclass 21 cls_cnt 0 2006.196.07:40:08.31#ibcon#cleared, iclass 21 cls_cnt 0 2006.196.07:40:08.31$vc4f8/va=2,7 2006.196.07:40:08.31#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.196.07:40:08.31#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.196.07:40:08.31#ibcon#ireg 11 cls_cnt 2 2006.196.07:40:08.31#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.196.07:40:08.37#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.196.07:40:08.37#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.196.07:40:08.37#ibcon#enter wrdev, iclass 23, count 2 2006.196.07:40:08.37#ibcon#first serial, iclass 23, count 2 2006.196.07:40:08.37#ibcon#enter sib2, iclass 23, count 2 2006.196.07:40:08.37#ibcon#flushed, iclass 23, count 2 2006.196.07:40:08.37#ibcon#about to write, iclass 23, count 2 2006.196.07:40:08.37#ibcon#wrote, iclass 23, count 2 2006.196.07:40:08.37#ibcon#about to read 3, iclass 23, count 2 2006.196.07:40:08.39#ibcon#read 3, iclass 23, count 2 2006.196.07:40:08.39#ibcon#about to read 4, iclass 23, count 2 2006.196.07:40:08.39#ibcon#read 4, iclass 23, count 2 2006.196.07:40:08.39#ibcon#about to read 5, iclass 23, count 2 2006.196.07:40:08.39#ibcon#read 5, iclass 23, count 2 2006.196.07:40:08.39#ibcon#about to read 6, iclass 23, count 2 2006.196.07:40:08.39#ibcon#read 6, iclass 23, count 2 2006.196.07:40:08.39#ibcon#end of sib2, iclass 23, count 2 2006.196.07:40:08.39#ibcon#*mode == 0, iclass 23, count 2 2006.196.07:40:08.39#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.196.07:40:08.39#ibcon#[25=AT02-07\r\n] 2006.196.07:40:08.39#ibcon#*before write, iclass 23, count 2 2006.196.07:40:08.39#ibcon#enter sib2, iclass 23, count 2 2006.196.07:40:08.39#ibcon#flushed, iclass 23, count 2 2006.196.07:40:08.39#ibcon#about to write, iclass 23, count 2 2006.196.07:40:08.39#ibcon#wrote, iclass 23, count 2 2006.196.07:40:08.39#ibcon#about to read 3, iclass 23, count 2 2006.196.07:40:08.42#ibcon#read 3, iclass 23, count 2 2006.196.07:40:08.42#ibcon#about to read 4, iclass 23, count 2 2006.196.07:40:08.42#ibcon#read 4, iclass 23, count 2 2006.196.07:40:08.42#ibcon#about to read 5, iclass 23, count 2 2006.196.07:40:08.42#ibcon#read 5, iclass 23, count 2 2006.196.07:40:08.42#ibcon#about to read 6, iclass 23, count 2 2006.196.07:40:08.42#ibcon#read 6, iclass 23, count 2 2006.196.07:40:08.42#ibcon#end of sib2, iclass 23, count 2 2006.196.07:40:08.42#ibcon#*after write, iclass 23, count 2 2006.196.07:40:08.42#ibcon#*before return 0, iclass 23, count 2 2006.196.07:40:08.42#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.196.07:40:08.42#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.196.07:40:08.42#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.196.07:40:08.42#ibcon#ireg 7 cls_cnt 0 2006.196.07:40:08.42#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.196.07:40:08.54#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.196.07:40:08.54#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.196.07:40:08.54#ibcon#enter wrdev, iclass 23, count 0 2006.196.07:40:08.54#ibcon#first serial, iclass 23, count 0 2006.196.07:40:08.54#ibcon#enter sib2, iclass 23, count 0 2006.196.07:40:08.54#ibcon#flushed, iclass 23, count 0 2006.196.07:40:08.54#ibcon#about to write, iclass 23, count 0 2006.196.07:40:08.54#ibcon#wrote, iclass 23, count 0 2006.196.07:40:08.54#ibcon#about to read 3, iclass 23, count 0 2006.196.07:40:08.56#ibcon#read 3, iclass 23, count 0 2006.196.07:40:08.56#ibcon#about to read 4, iclass 23, count 0 2006.196.07:40:08.56#ibcon#read 4, iclass 23, count 0 2006.196.07:40:08.56#ibcon#about to read 5, iclass 23, count 0 2006.196.07:40:08.56#ibcon#read 5, iclass 23, count 0 2006.196.07:40:08.56#ibcon#about to read 6, iclass 23, count 0 2006.196.07:40:08.56#ibcon#read 6, iclass 23, count 0 2006.196.07:40:08.56#ibcon#end of sib2, iclass 23, count 0 2006.196.07:40:08.56#ibcon#*mode == 0, iclass 23, count 0 2006.196.07:40:08.56#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.196.07:40:08.56#ibcon#[25=USB\r\n] 2006.196.07:40:08.56#ibcon#*before write, iclass 23, count 0 2006.196.07:40:08.56#ibcon#enter sib2, iclass 23, count 0 2006.196.07:40:08.56#ibcon#flushed, iclass 23, count 0 2006.196.07:40:08.56#ibcon#about to write, iclass 23, count 0 2006.196.07:40:08.56#ibcon#wrote, iclass 23, count 0 2006.196.07:40:08.56#ibcon#about to read 3, iclass 23, count 0 2006.196.07:40:08.59#ibcon#read 3, iclass 23, count 0 2006.196.07:40:08.59#ibcon#about to read 4, iclass 23, count 0 2006.196.07:40:08.59#ibcon#read 4, iclass 23, count 0 2006.196.07:40:08.59#ibcon#about to read 5, iclass 23, count 0 2006.196.07:40:08.59#ibcon#read 5, iclass 23, count 0 2006.196.07:40:08.59#ibcon#about to read 6, iclass 23, count 0 2006.196.07:40:08.59#ibcon#read 6, iclass 23, count 0 2006.196.07:40:08.59#ibcon#end of sib2, iclass 23, count 0 2006.196.07:40:08.59#ibcon#*after write, iclass 23, count 0 2006.196.07:40:08.59#ibcon#*before return 0, iclass 23, count 0 2006.196.07:40:08.59#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.196.07:40:08.59#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.196.07:40:08.59#ibcon#about to clear, iclass 23 cls_cnt 0 2006.196.07:40:08.59#ibcon#cleared, iclass 23 cls_cnt 0 2006.196.07:40:08.59$vc4f8/valo=3,672.99 2006.196.07:40:08.59#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.196.07:40:08.59#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.196.07:40:08.59#ibcon#ireg 17 cls_cnt 0 2006.196.07:40:08.59#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.196.07:40:08.59#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.196.07:40:08.59#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.196.07:40:08.59#ibcon#enter wrdev, iclass 25, count 0 2006.196.07:40:08.59#ibcon#first serial, iclass 25, count 0 2006.196.07:40:08.59#ibcon#enter sib2, iclass 25, count 0 2006.196.07:40:08.59#ibcon#flushed, iclass 25, count 0 2006.196.07:40:08.59#ibcon#about to write, iclass 25, count 0 2006.196.07:40:08.59#ibcon#wrote, iclass 25, count 0 2006.196.07:40:08.59#ibcon#about to read 3, iclass 25, count 0 2006.196.07:40:08.61#ibcon#read 3, iclass 25, count 0 2006.196.07:40:08.61#ibcon#about to read 4, iclass 25, count 0 2006.196.07:40:08.61#ibcon#read 4, iclass 25, count 0 2006.196.07:40:08.61#ibcon#about to read 5, iclass 25, count 0 2006.196.07:40:08.61#ibcon#read 5, iclass 25, count 0 2006.196.07:40:08.61#ibcon#about to read 6, iclass 25, count 0 2006.196.07:40:08.61#ibcon#read 6, iclass 25, count 0 2006.196.07:40:08.61#ibcon#end of sib2, iclass 25, count 0 2006.196.07:40:08.61#ibcon#*mode == 0, iclass 25, count 0 2006.196.07:40:08.61#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.196.07:40:08.61#ibcon#[26=FRQ=03,672.99\r\n] 2006.196.07:40:08.61#ibcon#*before write, iclass 25, count 0 2006.196.07:40:08.61#ibcon#enter sib2, iclass 25, count 0 2006.196.07:40:08.61#ibcon#flushed, iclass 25, count 0 2006.196.07:40:08.61#ibcon#about to write, iclass 25, count 0 2006.196.07:40:08.61#ibcon#wrote, iclass 25, count 0 2006.196.07:40:08.61#ibcon#about to read 3, iclass 25, count 0 2006.196.07:40:08.66#ibcon#read 3, iclass 25, count 0 2006.196.07:40:08.66#ibcon#about to read 4, iclass 25, count 0 2006.196.07:40:08.66#ibcon#read 4, iclass 25, count 0 2006.196.07:40:08.66#ibcon#about to read 5, iclass 25, count 0 2006.196.07:40:08.66#ibcon#read 5, iclass 25, count 0 2006.196.07:40:08.66#ibcon#about to read 6, iclass 25, count 0 2006.196.07:40:08.66#ibcon#read 6, iclass 25, count 0 2006.196.07:40:08.66#ibcon#end of sib2, iclass 25, count 0 2006.196.07:40:08.66#ibcon#*after write, iclass 25, count 0 2006.196.07:40:08.66#ibcon#*before return 0, iclass 25, count 0 2006.196.07:40:08.66#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.196.07:40:08.66#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.196.07:40:08.66#ibcon#about to clear, iclass 25 cls_cnt 0 2006.196.07:40:08.66#ibcon#cleared, iclass 25 cls_cnt 0 2006.196.07:40:08.66$vc4f8/va=3,6 2006.196.07:40:08.66#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.196.07:40:08.66#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.196.07:40:08.66#ibcon#ireg 11 cls_cnt 2 2006.196.07:40:08.66#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.196.07:40:08.71#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.196.07:40:08.71#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.196.07:40:08.71#ibcon#enter wrdev, iclass 27, count 2 2006.196.07:40:08.71#ibcon#first serial, iclass 27, count 2 2006.196.07:40:08.71#ibcon#enter sib2, iclass 27, count 2 2006.196.07:40:08.71#ibcon#flushed, iclass 27, count 2 2006.196.07:40:08.71#ibcon#about to write, iclass 27, count 2 2006.196.07:40:08.71#ibcon#wrote, iclass 27, count 2 2006.196.07:40:08.71#ibcon#about to read 3, iclass 27, count 2 2006.196.07:40:08.73#ibcon#read 3, iclass 27, count 2 2006.196.07:40:08.73#ibcon#about to read 4, iclass 27, count 2 2006.196.07:40:08.73#ibcon#read 4, iclass 27, count 2 2006.196.07:40:08.73#ibcon#about to read 5, iclass 27, count 2 2006.196.07:40:08.73#ibcon#read 5, iclass 27, count 2 2006.196.07:40:08.73#ibcon#about to read 6, iclass 27, count 2 2006.196.07:40:08.73#ibcon#read 6, iclass 27, count 2 2006.196.07:40:08.73#ibcon#end of sib2, iclass 27, count 2 2006.196.07:40:08.73#ibcon#*mode == 0, iclass 27, count 2 2006.196.07:40:08.73#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.196.07:40:08.73#ibcon#[25=AT03-06\r\n] 2006.196.07:40:08.73#ibcon#*before write, iclass 27, count 2 2006.196.07:40:08.73#ibcon#enter sib2, iclass 27, count 2 2006.196.07:40:08.73#ibcon#flushed, iclass 27, count 2 2006.196.07:40:08.73#ibcon#about to write, iclass 27, count 2 2006.196.07:40:08.73#ibcon#wrote, iclass 27, count 2 2006.196.07:40:08.73#ibcon#about to read 3, iclass 27, count 2 2006.196.07:40:08.76#ibcon#read 3, iclass 27, count 2 2006.196.07:40:08.76#ibcon#about to read 4, iclass 27, count 2 2006.196.07:40:08.76#ibcon#read 4, iclass 27, count 2 2006.196.07:40:08.76#ibcon#about to read 5, iclass 27, count 2 2006.196.07:40:08.76#ibcon#read 5, iclass 27, count 2 2006.196.07:40:08.76#ibcon#about to read 6, iclass 27, count 2 2006.196.07:40:08.76#ibcon#read 6, iclass 27, count 2 2006.196.07:40:08.76#ibcon#end of sib2, iclass 27, count 2 2006.196.07:40:08.76#ibcon#*after write, iclass 27, count 2 2006.196.07:40:08.76#ibcon#*before return 0, iclass 27, count 2 2006.196.07:40:08.76#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.196.07:40:08.76#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.196.07:40:08.76#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.196.07:40:08.76#ibcon#ireg 7 cls_cnt 0 2006.196.07:40:08.76#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.196.07:40:08.88#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.196.07:40:08.88#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.196.07:40:08.88#ibcon#enter wrdev, iclass 27, count 0 2006.196.07:40:08.88#ibcon#first serial, iclass 27, count 0 2006.196.07:40:08.88#ibcon#enter sib2, iclass 27, count 0 2006.196.07:40:08.88#ibcon#flushed, iclass 27, count 0 2006.196.07:40:08.88#ibcon#about to write, iclass 27, count 0 2006.196.07:40:08.88#ibcon#wrote, iclass 27, count 0 2006.196.07:40:08.88#ibcon#about to read 3, iclass 27, count 0 2006.196.07:40:08.90#ibcon#read 3, iclass 27, count 0 2006.196.07:40:08.90#ibcon#about to read 4, iclass 27, count 0 2006.196.07:40:08.90#ibcon#read 4, iclass 27, count 0 2006.196.07:40:08.90#ibcon#about to read 5, iclass 27, count 0 2006.196.07:40:08.90#ibcon#read 5, iclass 27, count 0 2006.196.07:40:08.90#ibcon#about to read 6, iclass 27, count 0 2006.196.07:40:08.90#ibcon#read 6, iclass 27, count 0 2006.196.07:40:08.90#ibcon#end of sib2, iclass 27, count 0 2006.196.07:40:08.90#ibcon#*mode == 0, iclass 27, count 0 2006.196.07:40:08.90#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.196.07:40:08.90#ibcon#[25=USB\r\n] 2006.196.07:40:08.90#ibcon#*before write, iclass 27, count 0 2006.196.07:40:08.90#ibcon#enter sib2, iclass 27, count 0 2006.196.07:40:08.90#ibcon#flushed, iclass 27, count 0 2006.196.07:40:08.90#ibcon#about to write, iclass 27, count 0 2006.196.07:40:08.90#ibcon#wrote, iclass 27, count 0 2006.196.07:40:08.90#ibcon#about to read 3, iclass 27, count 0 2006.196.07:40:08.93#ibcon#read 3, iclass 27, count 0 2006.196.07:40:08.93#ibcon#about to read 4, iclass 27, count 0 2006.196.07:40:08.93#ibcon#read 4, iclass 27, count 0 2006.196.07:40:08.93#ibcon#about to read 5, iclass 27, count 0 2006.196.07:40:08.93#ibcon#read 5, iclass 27, count 0 2006.196.07:40:08.93#ibcon#about to read 6, iclass 27, count 0 2006.196.07:40:08.93#ibcon#read 6, iclass 27, count 0 2006.196.07:40:08.93#ibcon#end of sib2, iclass 27, count 0 2006.196.07:40:08.93#ibcon#*after write, iclass 27, count 0 2006.196.07:40:08.93#ibcon#*before return 0, iclass 27, count 0 2006.196.07:40:08.93#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.196.07:40:08.93#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.196.07:40:08.93#ibcon#about to clear, iclass 27 cls_cnt 0 2006.196.07:40:08.93#ibcon#cleared, iclass 27 cls_cnt 0 2006.196.07:40:08.93$vc4f8/valo=4,832.99 2006.196.07:40:08.93#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.196.07:40:08.93#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.196.07:40:08.93#ibcon#ireg 17 cls_cnt 0 2006.196.07:40:08.93#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.196.07:40:08.93#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.196.07:40:08.93#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.196.07:40:08.93#ibcon#enter wrdev, iclass 29, count 0 2006.196.07:40:08.93#ibcon#first serial, iclass 29, count 0 2006.196.07:40:08.93#ibcon#enter sib2, iclass 29, count 0 2006.196.07:40:08.93#ibcon#flushed, iclass 29, count 0 2006.196.07:40:08.93#ibcon#about to write, iclass 29, count 0 2006.196.07:40:08.93#ibcon#wrote, iclass 29, count 0 2006.196.07:40:08.93#ibcon#about to read 3, iclass 29, count 0 2006.196.07:40:08.95#ibcon#read 3, iclass 29, count 0 2006.196.07:40:08.95#ibcon#about to read 4, iclass 29, count 0 2006.196.07:40:08.95#ibcon#read 4, iclass 29, count 0 2006.196.07:40:08.95#ibcon#about to read 5, iclass 29, count 0 2006.196.07:40:08.95#ibcon#read 5, iclass 29, count 0 2006.196.07:40:08.95#ibcon#about to read 6, iclass 29, count 0 2006.196.07:40:08.95#ibcon#read 6, iclass 29, count 0 2006.196.07:40:08.95#ibcon#end of sib2, iclass 29, count 0 2006.196.07:40:08.95#ibcon#*mode == 0, iclass 29, count 0 2006.196.07:40:08.95#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.196.07:40:08.95#ibcon#[26=FRQ=04,832.99\r\n] 2006.196.07:40:08.95#ibcon#*before write, iclass 29, count 0 2006.196.07:40:08.95#ibcon#enter sib2, iclass 29, count 0 2006.196.07:40:08.95#ibcon#flushed, iclass 29, count 0 2006.196.07:40:08.95#ibcon#about to write, iclass 29, count 0 2006.196.07:40:08.95#ibcon#wrote, iclass 29, count 0 2006.196.07:40:08.95#ibcon#about to read 3, iclass 29, count 0 2006.196.07:40:08.99#ibcon#read 3, iclass 29, count 0 2006.196.07:40:08.99#ibcon#about to read 4, iclass 29, count 0 2006.196.07:40:08.99#ibcon#read 4, iclass 29, count 0 2006.196.07:40:08.99#ibcon#about to read 5, iclass 29, count 0 2006.196.07:40:08.99#ibcon#read 5, iclass 29, count 0 2006.196.07:40:08.99#ibcon#about to read 6, iclass 29, count 0 2006.196.07:40:08.99#ibcon#read 6, iclass 29, count 0 2006.196.07:40:08.99#ibcon#end of sib2, iclass 29, count 0 2006.196.07:40:08.99#ibcon#*after write, iclass 29, count 0 2006.196.07:40:08.99#ibcon#*before return 0, iclass 29, count 0 2006.196.07:40:08.99#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.196.07:40:08.99#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.196.07:40:08.99#ibcon#about to clear, iclass 29 cls_cnt 0 2006.196.07:40:08.99#ibcon#cleared, iclass 29 cls_cnt 0 2006.196.07:40:08.99$vc4f8/va=4,7 2006.196.07:40:08.99#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.196.07:40:08.99#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.196.07:40:08.99#ibcon#ireg 11 cls_cnt 2 2006.196.07:40:08.99#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.196.07:40:09.05#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.196.07:40:09.05#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.196.07:40:09.05#ibcon#enter wrdev, iclass 31, count 2 2006.196.07:40:09.05#ibcon#first serial, iclass 31, count 2 2006.196.07:40:09.05#ibcon#enter sib2, iclass 31, count 2 2006.196.07:40:09.05#ibcon#flushed, iclass 31, count 2 2006.196.07:40:09.05#ibcon#about to write, iclass 31, count 2 2006.196.07:40:09.05#ibcon#wrote, iclass 31, count 2 2006.196.07:40:09.05#ibcon#about to read 3, iclass 31, count 2 2006.196.07:40:09.07#ibcon#read 3, iclass 31, count 2 2006.196.07:40:09.07#ibcon#about to read 4, iclass 31, count 2 2006.196.07:40:09.07#ibcon#read 4, iclass 31, count 2 2006.196.07:40:09.07#ibcon#about to read 5, iclass 31, count 2 2006.196.07:40:09.07#ibcon#read 5, iclass 31, count 2 2006.196.07:40:09.07#ibcon#about to read 6, iclass 31, count 2 2006.196.07:40:09.07#ibcon#read 6, iclass 31, count 2 2006.196.07:40:09.07#ibcon#end of sib2, iclass 31, count 2 2006.196.07:40:09.07#ibcon#*mode == 0, iclass 31, count 2 2006.196.07:40:09.07#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.196.07:40:09.07#ibcon#[25=AT04-07\r\n] 2006.196.07:40:09.07#ibcon#*before write, iclass 31, count 2 2006.196.07:40:09.07#ibcon#enter sib2, iclass 31, count 2 2006.196.07:40:09.07#ibcon#flushed, iclass 31, count 2 2006.196.07:40:09.07#ibcon#about to write, iclass 31, count 2 2006.196.07:40:09.07#ibcon#wrote, iclass 31, count 2 2006.196.07:40:09.07#ibcon#about to read 3, iclass 31, count 2 2006.196.07:40:09.10#ibcon#read 3, iclass 31, count 2 2006.196.07:40:09.10#ibcon#about to read 4, iclass 31, count 2 2006.196.07:40:09.10#ibcon#read 4, iclass 31, count 2 2006.196.07:40:09.10#ibcon#about to read 5, iclass 31, count 2 2006.196.07:40:09.10#ibcon#read 5, iclass 31, count 2 2006.196.07:40:09.10#ibcon#about to read 6, iclass 31, count 2 2006.196.07:40:09.10#ibcon#read 6, iclass 31, count 2 2006.196.07:40:09.10#ibcon#end of sib2, iclass 31, count 2 2006.196.07:40:09.10#ibcon#*after write, iclass 31, count 2 2006.196.07:40:09.10#ibcon#*before return 0, iclass 31, count 2 2006.196.07:40:09.10#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.196.07:40:09.10#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.196.07:40:09.10#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.196.07:40:09.10#ibcon#ireg 7 cls_cnt 0 2006.196.07:40:09.10#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.196.07:40:09.22#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.196.07:40:09.22#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.196.07:40:09.22#ibcon#enter wrdev, iclass 31, count 0 2006.196.07:40:09.22#ibcon#first serial, iclass 31, count 0 2006.196.07:40:09.22#ibcon#enter sib2, iclass 31, count 0 2006.196.07:40:09.22#ibcon#flushed, iclass 31, count 0 2006.196.07:40:09.22#ibcon#about to write, iclass 31, count 0 2006.196.07:40:09.22#ibcon#wrote, iclass 31, count 0 2006.196.07:40:09.22#ibcon#about to read 3, iclass 31, count 0 2006.196.07:40:09.24#ibcon#read 3, iclass 31, count 0 2006.196.07:40:09.24#ibcon#about to read 4, iclass 31, count 0 2006.196.07:40:09.24#ibcon#read 4, iclass 31, count 0 2006.196.07:40:09.24#ibcon#about to read 5, iclass 31, count 0 2006.196.07:40:09.24#ibcon#read 5, iclass 31, count 0 2006.196.07:40:09.24#ibcon#about to read 6, iclass 31, count 0 2006.196.07:40:09.24#ibcon#read 6, iclass 31, count 0 2006.196.07:40:09.24#ibcon#end of sib2, iclass 31, count 0 2006.196.07:40:09.24#ibcon#*mode == 0, iclass 31, count 0 2006.196.07:40:09.24#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.196.07:40:09.24#ibcon#[25=USB\r\n] 2006.196.07:40:09.24#ibcon#*before write, iclass 31, count 0 2006.196.07:40:09.24#ibcon#enter sib2, iclass 31, count 0 2006.196.07:40:09.24#ibcon#flushed, iclass 31, count 0 2006.196.07:40:09.24#ibcon#about to write, iclass 31, count 0 2006.196.07:40:09.24#ibcon#wrote, iclass 31, count 0 2006.196.07:40:09.24#ibcon#about to read 3, iclass 31, count 0 2006.196.07:40:09.27#ibcon#read 3, iclass 31, count 0 2006.196.07:40:09.27#ibcon#about to read 4, iclass 31, count 0 2006.196.07:40:09.27#ibcon#read 4, iclass 31, count 0 2006.196.07:40:09.27#ibcon#about to read 5, iclass 31, count 0 2006.196.07:40:09.27#ibcon#read 5, iclass 31, count 0 2006.196.07:40:09.27#ibcon#about to read 6, iclass 31, count 0 2006.196.07:40:09.27#ibcon#read 6, iclass 31, count 0 2006.196.07:40:09.27#ibcon#end of sib2, iclass 31, count 0 2006.196.07:40:09.27#ibcon#*after write, iclass 31, count 0 2006.196.07:40:09.27#ibcon#*before return 0, iclass 31, count 0 2006.196.07:40:09.27#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.196.07:40:09.27#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.196.07:40:09.27#ibcon#about to clear, iclass 31 cls_cnt 0 2006.196.07:40:09.27#ibcon#cleared, iclass 31 cls_cnt 0 2006.196.07:40:09.27$vc4f8/valo=5,652.99 2006.196.07:40:09.27#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.196.07:40:09.27#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.196.07:40:09.27#ibcon#ireg 17 cls_cnt 0 2006.196.07:40:09.27#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.196.07:40:09.27#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.196.07:40:09.27#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.196.07:40:09.27#ibcon#enter wrdev, iclass 33, count 0 2006.196.07:40:09.27#ibcon#first serial, iclass 33, count 0 2006.196.07:40:09.27#ibcon#enter sib2, iclass 33, count 0 2006.196.07:40:09.27#ibcon#flushed, iclass 33, count 0 2006.196.07:40:09.27#ibcon#about to write, iclass 33, count 0 2006.196.07:40:09.27#ibcon#wrote, iclass 33, count 0 2006.196.07:40:09.27#ibcon#about to read 3, iclass 33, count 0 2006.196.07:40:09.29#ibcon#read 3, iclass 33, count 0 2006.196.07:40:09.29#ibcon#about to read 4, iclass 33, count 0 2006.196.07:40:09.29#ibcon#read 4, iclass 33, count 0 2006.196.07:40:09.29#ibcon#about to read 5, iclass 33, count 0 2006.196.07:40:09.29#ibcon#read 5, iclass 33, count 0 2006.196.07:40:09.29#ibcon#about to read 6, iclass 33, count 0 2006.196.07:40:09.29#ibcon#read 6, iclass 33, count 0 2006.196.07:40:09.29#ibcon#end of sib2, iclass 33, count 0 2006.196.07:40:09.29#ibcon#*mode == 0, iclass 33, count 0 2006.196.07:40:09.29#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.196.07:40:09.29#ibcon#[26=FRQ=05,652.99\r\n] 2006.196.07:40:09.29#ibcon#*before write, iclass 33, count 0 2006.196.07:40:09.29#ibcon#enter sib2, iclass 33, count 0 2006.196.07:40:09.29#ibcon#flushed, iclass 33, count 0 2006.196.07:40:09.29#ibcon#about to write, iclass 33, count 0 2006.196.07:40:09.29#ibcon#wrote, iclass 33, count 0 2006.196.07:40:09.29#ibcon#about to read 3, iclass 33, count 0 2006.196.07:40:09.33#ibcon#read 3, iclass 33, count 0 2006.196.07:40:09.33#ibcon#about to read 4, iclass 33, count 0 2006.196.07:40:09.33#ibcon#read 4, iclass 33, count 0 2006.196.07:40:09.33#ibcon#about to read 5, iclass 33, count 0 2006.196.07:40:09.33#ibcon#read 5, iclass 33, count 0 2006.196.07:40:09.33#ibcon#about to read 6, iclass 33, count 0 2006.196.07:40:09.33#ibcon#read 6, iclass 33, count 0 2006.196.07:40:09.33#ibcon#end of sib2, iclass 33, count 0 2006.196.07:40:09.33#ibcon#*after write, iclass 33, count 0 2006.196.07:40:09.33#ibcon#*before return 0, iclass 33, count 0 2006.196.07:40:09.33#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.196.07:40:09.33#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.196.07:40:09.33#ibcon#about to clear, iclass 33 cls_cnt 0 2006.196.07:40:09.33#ibcon#cleared, iclass 33 cls_cnt 0 2006.196.07:40:09.33$vc4f8/va=5,7 2006.196.07:40:09.33#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.196.07:40:09.33#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.196.07:40:09.33#ibcon#ireg 11 cls_cnt 2 2006.196.07:40:09.33#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.196.07:40:09.39#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.196.07:40:09.39#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.196.07:40:09.39#ibcon#enter wrdev, iclass 35, count 2 2006.196.07:40:09.39#ibcon#first serial, iclass 35, count 2 2006.196.07:40:09.39#ibcon#enter sib2, iclass 35, count 2 2006.196.07:40:09.39#ibcon#flushed, iclass 35, count 2 2006.196.07:40:09.39#ibcon#about to write, iclass 35, count 2 2006.196.07:40:09.39#ibcon#wrote, iclass 35, count 2 2006.196.07:40:09.39#ibcon#about to read 3, iclass 35, count 2 2006.196.07:40:09.41#ibcon#read 3, iclass 35, count 2 2006.196.07:40:09.41#ibcon#about to read 4, iclass 35, count 2 2006.196.07:40:09.41#ibcon#read 4, iclass 35, count 2 2006.196.07:40:09.41#ibcon#about to read 5, iclass 35, count 2 2006.196.07:40:09.41#ibcon#read 5, iclass 35, count 2 2006.196.07:40:09.41#ibcon#about to read 6, iclass 35, count 2 2006.196.07:40:09.41#ibcon#read 6, iclass 35, count 2 2006.196.07:40:09.41#ibcon#end of sib2, iclass 35, count 2 2006.196.07:40:09.41#ibcon#*mode == 0, iclass 35, count 2 2006.196.07:40:09.41#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.196.07:40:09.41#ibcon#[25=AT05-07\r\n] 2006.196.07:40:09.41#ibcon#*before write, iclass 35, count 2 2006.196.07:40:09.41#ibcon#enter sib2, iclass 35, count 2 2006.196.07:40:09.41#ibcon#flushed, iclass 35, count 2 2006.196.07:40:09.41#ibcon#about to write, iclass 35, count 2 2006.196.07:40:09.41#ibcon#wrote, iclass 35, count 2 2006.196.07:40:09.41#ibcon#about to read 3, iclass 35, count 2 2006.196.07:40:09.44#ibcon#read 3, iclass 35, count 2 2006.196.07:40:09.44#ibcon#about to read 4, iclass 35, count 2 2006.196.07:40:09.44#ibcon#read 4, iclass 35, count 2 2006.196.07:40:09.44#ibcon#about to read 5, iclass 35, count 2 2006.196.07:40:09.44#ibcon#read 5, iclass 35, count 2 2006.196.07:40:09.44#ibcon#about to read 6, iclass 35, count 2 2006.196.07:40:09.44#ibcon#read 6, iclass 35, count 2 2006.196.07:40:09.44#ibcon#end of sib2, iclass 35, count 2 2006.196.07:40:09.44#ibcon#*after write, iclass 35, count 2 2006.196.07:40:09.44#ibcon#*before return 0, iclass 35, count 2 2006.196.07:40:09.44#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.196.07:40:09.44#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.196.07:40:09.44#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.196.07:40:09.44#ibcon#ireg 7 cls_cnt 0 2006.196.07:40:09.44#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.196.07:40:09.56#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.196.07:40:09.56#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.196.07:40:09.56#ibcon#enter wrdev, iclass 35, count 0 2006.196.07:40:09.56#ibcon#first serial, iclass 35, count 0 2006.196.07:40:09.56#ibcon#enter sib2, iclass 35, count 0 2006.196.07:40:09.56#ibcon#flushed, iclass 35, count 0 2006.196.07:40:09.56#ibcon#about to write, iclass 35, count 0 2006.196.07:40:09.56#ibcon#wrote, iclass 35, count 0 2006.196.07:40:09.56#ibcon#about to read 3, iclass 35, count 0 2006.196.07:40:09.58#ibcon#read 3, iclass 35, count 0 2006.196.07:40:09.58#ibcon#about to read 4, iclass 35, count 0 2006.196.07:40:09.58#ibcon#read 4, iclass 35, count 0 2006.196.07:40:09.58#ibcon#about to read 5, iclass 35, count 0 2006.196.07:40:09.58#ibcon#read 5, iclass 35, count 0 2006.196.07:40:09.58#ibcon#about to read 6, iclass 35, count 0 2006.196.07:40:09.58#ibcon#read 6, iclass 35, count 0 2006.196.07:40:09.58#ibcon#end of sib2, iclass 35, count 0 2006.196.07:40:09.58#ibcon#*mode == 0, iclass 35, count 0 2006.196.07:40:09.58#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.196.07:40:09.58#ibcon#[25=USB\r\n] 2006.196.07:40:09.58#ibcon#*before write, iclass 35, count 0 2006.196.07:40:09.58#ibcon#enter sib2, iclass 35, count 0 2006.196.07:40:09.58#ibcon#flushed, iclass 35, count 0 2006.196.07:40:09.58#ibcon#about to write, iclass 35, count 0 2006.196.07:40:09.58#ibcon#wrote, iclass 35, count 0 2006.196.07:40:09.58#ibcon#about to read 3, iclass 35, count 0 2006.196.07:40:09.61#ibcon#read 3, iclass 35, count 0 2006.196.07:40:09.61#ibcon#about to read 4, iclass 35, count 0 2006.196.07:40:09.61#ibcon#read 4, iclass 35, count 0 2006.196.07:40:09.61#ibcon#about to read 5, iclass 35, count 0 2006.196.07:40:09.61#ibcon#read 5, iclass 35, count 0 2006.196.07:40:09.61#ibcon#about to read 6, iclass 35, count 0 2006.196.07:40:09.61#ibcon#read 6, iclass 35, count 0 2006.196.07:40:09.61#ibcon#end of sib2, iclass 35, count 0 2006.196.07:40:09.61#ibcon#*after write, iclass 35, count 0 2006.196.07:40:09.61#ibcon#*before return 0, iclass 35, count 0 2006.196.07:40:09.61#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.196.07:40:09.61#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.196.07:40:09.61#ibcon#about to clear, iclass 35 cls_cnt 0 2006.196.07:40:09.61#ibcon#cleared, iclass 35 cls_cnt 0 2006.196.07:40:09.61$vc4f8/valo=6,772.99 2006.196.07:40:09.61#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.196.07:40:09.61#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.196.07:40:09.61#ibcon#ireg 17 cls_cnt 0 2006.196.07:40:09.61#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.196.07:40:09.61#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.196.07:40:09.61#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.196.07:40:09.61#ibcon#enter wrdev, iclass 37, count 0 2006.196.07:40:09.61#ibcon#first serial, iclass 37, count 0 2006.196.07:40:09.61#ibcon#enter sib2, iclass 37, count 0 2006.196.07:40:09.61#ibcon#flushed, iclass 37, count 0 2006.196.07:40:09.61#ibcon#about to write, iclass 37, count 0 2006.196.07:40:09.61#ibcon#wrote, iclass 37, count 0 2006.196.07:40:09.61#ibcon#about to read 3, iclass 37, count 0 2006.196.07:40:09.63#ibcon#read 3, iclass 37, count 0 2006.196.07:40:09.63#ibcon#about to read 4, iclass 37, count 0 2006.196.07:40:09.63#ibcon#read 4, iclass 37, count 0 2006.196.07:40:09.63#ibcon#about to read 5, iclass 37, count 0 2006.196.07:40:09.63#ibcon#read 5, iclass 37, count 0 2006.196.07:40:09.63#ibcon#about to read 6, iclass 37, count 0 2006.196.07:40:09.63#ibcon#read 6, iclass 37, count 0 2006.196.07:40:09.63#ibcon#end of sib2, iclass 37, count 0 2006.196.07:40:09.63#ibcon#*mode == 0, iclass 37, count 0 2006.196.07:40:09.63#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.196.07:40:09.63#ibcon#[26=FRQ=06,772.99\r\n] 2006.196.07:40:09.63#ibcon#*before write, iclass 37, count 0 2006.196.07:40:09.63#ibcon#enter sib2, iclass 37, count 0 2006.196.07:40:09.63#ibcon#flushed, iclass 37, count 0 2006.196.07:40:09.63#ibcon#about to write, iclass 37, count 0 2006.196.07:40:09.63#ibcon#wrote, iclass 37, count 0 2006.196.07:40:09.63#ibcon#about to read 3, iclass 37, count 0 2006.196.07:40:09.67#ibcon#read 3, iclass 37, count 0 2006.196.07:40:09.67#ibcon#about to read 4, iclass 37, count 0 2006.196.07:40:09.67#ibcon#read 4, iclass 37, count 0 2006.196.07:40:09.67#ibcon#about to read 5, iclass 37, count 0 2006.196.07:40:09.67#ibcon#read 5, iclass 37, count 0 2006.196.07:40:09.67#ibcon#about to read 6, iclass 37, count 0 2006.196.07:40:09.67#ibcon#read 6, iclass 37, count 0 2006.196.07:40:09.67#ibcon#end of sib2, iclass 37, count 0 2006.196.07:40:09.67#ibcon#*after write, iclass 37, count 0 2006.196.07:40:09.67#ibcon#*before return 0, iclass 37, count 0 2006.196.07:40:09.67#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.196.07:40:09.67#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.196.07:40:09.67#ibcon#about to clear, iclass 37 cls_cnt 0 2006.196.07:40:09.67#ibcon#cleared, iclass 37 cls_cnt 0 2006.196.07:40:09.67$vc4f8/va=6,6 2006.196.07:40:09.67#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.196.07:40:09.67#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.196.07:40:09.67#ibcon#ireg 11 cls_cnt 2 2006.196.07:40:09.67#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.196.07:40:09.73#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.196.07:40:09.73#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.196.07:40:09.73#ibcon#enter wrdev, iclass 39, count 2 2006.196.07:40:09.73#ibcon#first serial, iclass 39, count 2 2006.196.07:40:09.73#ibcon#enter sib2, iclass 39, count 2 2006.196.07:40:09.73#ibcon#flushed, iclass 39, count 2 2006.196.07:40:09.73#ibcon#about to write, iclass 39, count 2 2006.196.07:40:09.73#ibcon#wrote, iclass 39, count 2 2006.196.07:40:09.73#ibcon#about to read 3, iclass 39, count 2 2006.196.07:40:09.75#ibcon#read 3, iclass 39, count 2 2006.196.07:40:09.75#ibcon#about to read 4, iclass 39, count 2 2006.196.07:40:09.75#ibcon#read 4, iclass 39, count 2 2006.196.07:40:09.75#ibcon#about to read 5, iclass 39, count 2 2006.196.07:40:09.75#ibcon#read 5, iclass 39, count 2 2006.196.07:40:09.75#ibcon#about to read 6, iclass 39, count 2 2006.196.07:40:09.75#ibcon#read 6, iclass 39, count 2 2006.196.07:40:09.75#ibcon#end of sib2, iclass 39, count 2 2006.196.07:40:09.75#ibcon#*mode == 0, iclass 39, count 2 2006.196.07:40:09.75#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.196.07:40:09.75#ibcon#[25=AT06-06\r\n] 2006.196.07:40:09.75#ibcon#*before write, iclass 39, count 2 2006.196.07:40:09.75#ibcon#enter sib2, iclass 39, count 2 2006.196.07:40:09.75#ibcon#flushed, iclass 39, count 2 2006.196.07:40:09.75#ibcon#about to write, iclass 39, count 2 2006.196.07:40:09.75#ibcon#wrote, iclass 39, count 2 2006.196.07:40:09.75#ibcon#about to read 3, iclass 39, count 2 2006.196.07:40:09.78#ibcon#read 3, iclass 39, count 2 2006.196.07:40:09.78#ibcon#about to read 4, iclass 39, count 2 2006.196.07:40:09.78#ibcon#read 4, iclass 39, count 2 2006.196.07:40:09.78#ibcon#about to read 5, iclass 39, count 2 2006.196.07:40:09.78#ibcon#read 5, iclass 39, count 2 2006.196.07:40:09.78#ibcon#about to read 6, iclass 39, count 2 2006.196.07:40:09.78#ibcon#read 6, iclass 39, count 2 2006.196.07:40:09.78#ibcon#end of sib2, iclass 39, count 2 2006.196.07:40:09.78#ibcon#*after write, iclass 39, count 2 2006.196.07:40:09.78#ibcon#*before return 0, iclass 39, count 2 2006.196.07:40:09.78#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.196.07:40:09.78#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.196.07:40:09.78#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.196.07:40:09.78#ibcon#ireg 7 cls_cnt 0 2006.196.07:40:09.78#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.196.07:40:09.90#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.196.07:40:09.90#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.196.07:40:09.90#ibcon#enter wrdev, iclass 39, count 0 2006.196.07:40:09.90#ibcon#first serial, iclass 39, count 0 2006.196.07:40:09.90#ibcon#enter sib2, iclass 39, count 0 2006.196.07:40:09.90#ibcon#flushed, iclass 39, count 0 2006.196.07:40:09.90#ibcon#about to write, iclass 39, count 0 2006.196.07:40:09.90#ibcon#wrote, iclass 39, count 0 2006.196.07:40:09.90#ibcon#about to read 3, iclass 39, count 0 2006.196.07:40:09.92#ibcon#read 3, iclass 39, count 0 2006.196.07:40:09.92#ibcon#about to read 4, iclass 39, count 0 2006.196.07:40:09.92#ibcon#read 4, iclass 39, count 0 2006.196.07:40:09.92#ibcon#about to read 5, iclass 39, count 0 2006.196.07:40:09.92#ibcon#read 5, iclass 39, count 0 2006.196.07:40:09.92#ibcon#about to read 6, iclass 39, count 0 2006.196.07:40:09.92#ibcon#read 6, iclass 39, count 0 2006.196.07:40:09.92#ibcon#end of sib2, iclass 39, count 0 2006.196.07:40:09.92#ibcon#*mode == 0, iclass 39, count 0 2006.196.07:40:09.92#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.196.07:40:09.92#ibcon#[25=USB\r\n] 2006.196.07:40:09.92#ibcon#*before write, iclass 39, count 0 2006.196.07:40:09.92#ibcon#enter sib2, iclass 39, count 0 2006.196.07:40:09.92#ibcon#flushed, iclass 39, count 0 2006.196.07:40:09.92#ibcon#about to write, iclass 39, count 0 2006.196.07:40:09.92#ibcon#wrote, iclass 39, count 0 2006.196.07:40:09.92#ibcon#about to read 3, iclass 39, count 0 2006.196.07:40:09.95#ibcon#read 3, iclass 39, count 0 2006.196.07:40:09.95#ibcon#about to read 4, iclass 39, count 0 2006.196.07:40:09.95#ibcon#read 4, iclass 39, count 0 2006.196.07:40:09.95#ibcon#about to read 5, iclass 39, count 0 2006.196.07:40:09.95#ibcon#read 5, iclass 39, count 0 2006.196.07:40:09.95#ibcon#about to read 6, iclass 39, count 0 2006.196.07:40:09.95#ibcon#read 6, iclass 39, count 0 2006.196.07:40:09.95#ibcon#end of sib2, iclass 39, count 0 2006.196.07:40:09.95#ibcon#*after write, iclass 39, count 0 2006.196.07:40:09.95#ibcon#*before return 0, iclass 39, count 0 2006.196.07:40:09.95#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.196.07:40:09.95#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.196.07:40:09.95#ibcon#about to clear, iclass 39 cls_cnt 0 2006.196.07:40:09.95#ibcon#cleared, iclass 39 cls_cnt 0 2006.196.07:40:09.95$vc4f8/valo=7,832.99 2006.196.07:40:09.95#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.196.07:40:09.95#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.196.07:40:09.95#ibcon#ireg 17 cls_cnt 0 2006.196.07:40:09.95#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.196.07:40:09.95#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.196.07:40:09.95#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.196.07:40:09.95#ibcon#enter wrdev, iclass 3, count 0 2006.196.07:40:09.95#ibcon#first serial, iclass 3, count 0 2006.196.07:40:09.95#ibcon#enter sib2, iclass 3, count 0 2006.196.07:40:09.95#ibcon#flushed, iclass 3, count 0 2006.196.07:40:09.95#ibcon#about to write, iclass 3, count 0 2006.196.07:40:09.95#ibcon#wrote, iclass 3, count 0 2006.196.07:40:09.95#ibcon#about to read 3, iclass 3, count 0 2006.196.07:40:09.97#ibcon#read 3, iclass 3, count 0 2006.196.07:40:09.97#ibcon#about to read 4, iclass 3, count 0 2006.196.07:40:09.97#ibcon#read 4, iclass 3, count 0 2006.196.07:40:09.97#ibcon#about to read 5, iclass 3, count 0 2006.196.07:40:09.97#ibcon#read 5, iclass 3, count 0 2006.196.07:40:09.97#ibcon#about to read 6, iclass 3, count 0 2006.196.07:40:09.97#ibcon#read 6, iclass 3, count 0 2006.196.07:40:09.97#ibcon#end of sib2, iclass 3, count 0 2006.196.07:40:09.97#ibcon#*mode == 0, iclass 3, count 0 2006.196.07:40:09.97#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.196.07:40:09.97#ibcon#[26=FRQ=07,832.99\r\n] 2006.196.07:40:09.97#ibcon#*before write, iclass 3, count 0 2006.196.07:40:09.97#ibcon#enter sib2, iclass 3, count 0 2006.196.07:40:09.97#ibcon#flushed, iclass 3, count 0 2006.196.07:40:09.97#ibcon#about to write, iclass 3, count 0 2006.196.07:40:09.97#ibcon#wrote, iclass 3, count 0 2006.196.07:40:09.97#ibcon#about to read 3, iclass 3, count 0 2006.196.07:40:10.01#ibcon#read 3, iclass 3, count 0 2006.196.07:40:10.01#ibcon#about to read 4, iclass 3, count 0 2006.196.07:40:10.01#ibcon#read 4, iclass 3, count 0 2006.196.07:40:10.01#ibcon#about to read 5, iclass 3, count 0 2006.196.07:40:10.01#ibcon#read 5, iclass 3, count 0 2006.196.07:40:10.01#ibcon#about to read 6, iclass 3, count 0 2006.196.07:40:10.01#ibcon#read 6, iclass 3, count 0 2006.196.07:40:10.01#ibcon#end of sib2, iclass 3, count 0 2006.196.07:40:10.01#ibcon#*after write, iclass 3, count 0 2006.196.07:40:10.01#ibcon#*before return 0, iclass 3, count 0 2006.196.07:40:10.01#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.196.07:40:10.01#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.196.07:40:10.01#ibcon#about to clear, iclass 3 cls_cnt 0 2006.196.07:40:10.01#ibcon#cleared, iclass 3 cls_cnt 0 2006.196.07:40:10.01$vc4f8/va=7,6 2006.196.07:40:10.01#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.196.07:40:10.01#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.196.07:40:10.01#ibcon#ireg 11 cls_cnt 2 2006.196.07:40:10.01#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.196.07:40:10.07#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.196.07:40:10.07#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.196.07:40:10.07#ibcon#enter wrdev, iclass 5, count 2 2006.196.07:40:10.07#ibcon#first serial, iclass 5, count 2 2006.196.07:40:10.07#ibcon#enter sib2, iclass 5, count 2 2006.196.07:40:10.07#ibcon#flushed, iclass 5, count 2 2006.196.07:40:10.07#ibcon#about to write, iclass 5, count 2 2006.196.07:40:10.07#ibcon#wrote, iclass 5, count 2 2006.196.07:40:10.07#ibcon#about to read 3, iclass 5, count 2 2006.196.07:40:10.09#ibcon#read 3, iclass 5, count 2 2006.196.07:40:10.09#ibcon#about to read 4, iclass 5, count 2 2006.196.07:40:10.09#ibcon#read 4, iclass 5, count 2 2006.196.07:40:10.09#ibcon#about to read 5, iclass 5, count 2 2006.196.07:40:10.09#ibcon#read 5, iclass 5, count 2 2006.196.07:40:10.09#ibcon#about to read 6, iclass 5, count 2 2006.196.07:40:10.09#ibcon#read 6, iclass 5, count 2 2006.196.07:40:10.09#ibcon#end of sib2, iclass 5, count 2 2006.196.07:40:10.09#ibcon#*mode == 0, iclass 5, count 2 2006.196.07:40:10.09#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.196.07:40:10.09#ibcon#[25=AT07-06\r\n] 2006.196.07:40:10.09#ibcon#*before write, iclass 5, count 2 2006.196.07:40:10.09#ibcon#enter sib2, iclass 5, count 2 2006.196.07:40:10.09#ibcon#flushed, iclass 5, count 2 2006.196.07:40:10.09#ibcon#about to write, iclass 5, count 2 2006.196.07:40:10.09#ibcon#wrote, iclass 5, count 2 2006.196.07:40:10.09#ibcon#about to read 3, iclass 5, count 2 2006.196.07:40:10.12#ibcon#read 3, iclass 5, count 2 2006.196.07:40:10.12#ibcon#about to read 4, iclass 5, count 2 2006.196.07:40:10.12#ibcon#read 4, iclass 5, count 2 2006.196.07:40:10.12#ibcon#about to read 5, iclass 5, count 2 2006.196.07:40:10.12#ibcon#read 5, iclass 5, count 2 2006.196.07:40:10.12#ibcon#about to read 6, iclass 5, count 2 2006.196.07:40:10.12#ibcon#read 6, iclass 5, count 2 2006.196.07:40:10.12#ibcon#end of sib2, iclass 5, count 2 2006.196.07:40:10.12#ibcon#*after write, iclass 5, count 2 2006.196.07:40:10.12#ibcon#*before return 0, iclass 5, count 2 2006.196.07:40:10.12#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.196.07:40:10.12#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.196.07:40:10.12#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.196.07:40:10.12#ibcon#ireg 7 cls_cnt 0 2006.196.07:40:10.12#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.196.07:40:10.24#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.196.07:40:10.24#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.196.07:40:10.24#ibcon#enter wrdev, iclass 5, count 0 2006.196.07:40:10.24#ibcon#first serial, iclass 5, count 0 2006.196.07:40:10.24#ibcon#enter sib2, iclass 5, count 0 2006.196.07:40:10.24#ibcon#flushed, iclass 5, count 0 2006.196.07:40:10.24#ibcon#about to write, iclass 5, count 0 2006.196.07:40:10.24#ibcon#wrote, iclass 5, count 0 2006.196.07:40:10.24#ibcon#about to read 3, iclass 5, count 0 2006.196.07:40:10.26#ibcon#read 3, iclass 5, count 0 2006.196.07:40:10.26#ibcon#about to read 4, iclass 5, count 0 2006.196.07:40:10.26#ibcon#read 4, iclass 5, count 0 2006.196.07:40:10.26#ibcon#about to read 5, iclass 5, count 0 2006.196.07:40:10.26#ibcon#read 5, iclass 5, count 0 2006.196.07:40:10.26#ibcon#about to read 6, iclass 5, count 0 2006.196.07:40:10.26#ibcon#read 6, iclass 5, count 0 2006.196.07:40:10.26#ibcon#end of sib2, iclass 5, count 0 2006.196.07:40:10.26#ibcon#*mode == 0, iclass 5, count 0 2006.196.07:40:10.26#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.196.07:40:10.26#ibcon#[25=USB\r\n] 2006.196.07:40:10.26#ibcon#*before write, iclass 5, count 0 2006.196.07:40:10.26#ibcon#enter sib2, iclass 5, count 0 2006.196.07:40:10.26#ibcon#flushed, iclass 5, count 0 2006.196.07:40:10.26#ibcon#about to write, iclass 5, count 0 2006.196.07:40:10.26#ibcon#wrote, iclass 5, count 0 2006.196.07:40:10.26#ibcon#about to read 3, iclass 5, count 0 2006.196.07:40:10.29#ibcon#read 3, iclass 5, count 0 2006.196.07:40:10.29#ibcon#about to read 4, iclass 5, count 0 2006.196.07:40:10.29#ibcon#read 4, iclass 5, count 0 2006.196.07:40:10.29#ibcon#about to read 5, iclass 5, count 0 2006.196.07:40:10.29#ibcon#read 5, iclass 5, count 0 2006.196.07:40:10.29#ibcon#about to read 6, iclass 5, count 0 2006.196.07:40:10.29#ibcon#read 6, iclass 5, count 0 2006.196.07:40:10.29#ibcon#end of sib2, iclass 5, count 0 2006.196.07:40:10.29#ibcon#*after write, iclass 5, count 0 2006.196.07:40:10.29#ibcon#*before return 0, iclass 5, count 0 2006.196.07:40:10.29#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.196.07:40:10.29#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.196.07:40:10.29#ibcon#about to clear, iclass 5 cls_cnt 0 2006.196.07:40:10.29#ibcon#cleared, iclass 5 cls_cnt 0 2006.196.07:40:10.29$vc4f8/valo=8,852.99 2006.196.07:40:10.29#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.196.07:40:10.29#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.196.07:40:10.29#ibcon#ireg 17 cls_cnt 0 2006.196.07:40:10.29#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.196.07:40:10.29#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.196.07:40:10.29#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.196.07:40:10.29#ibcon#enter wrdev, iclass 7, count 0 2006.196.07:40:10.29#ibcon#first serial, iclass 7, count 0 2006.196.07:40:10.29#ibcon#enter sib2, iclass 7, count 0 2006.196.07:40:10.29#ibcon#flushed, iclass 7, count 0 2006.196.07:40:10.29#ibcon#about to write, iclass 7, count 0 2006.196.07:40:10.29#ibcon#wrote, iclass 7, count 0 2006.196.07:40:10.29#ibcon#about to read 3, iclass 7, count 0 2006.196.07:40:10.31#ibcon#read 3, iclass 7, count 0 2006.196.07:40:10.31#ibcon#about to read 4, iclass 7, count 0 2006.196.07:40:10.31#ibcon#read 4, iclass 7, count 0 2006.196.07:40:10.31#ibcon#about to read 5, iclass 7, count 0 2006.196.07:40:10.31#ibcon#read 5, iclass 7, count 0 2006.196.07:40:10.31#ibcon#about to read 6, iclass 7, count 0 2006.196.07:40:10.31#ibcon#read 6, iclass 7, count 0 2006.196.07:40:10.31#ibcon#end of sib2, iclass 7, count 0 2006.196.07:40:10.31#ibcon#*mode == 0, iclass 7, count 0 2006.196.07:40:10.31#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.196.07:40:10.31#ibcon#[26=FRQ=08,852.99\r\n] 2006.196.07:40:10.31#ibcon#*before write, iclass 7, count 0 2006.196.07:40:10.31#ibcon#enter sib2, iclass 7, count 0 2006.196.07:40:10.31#ibcon#flushed, iclass 7, count 0 2006.196.07:40:10.31#ibcon#about to write, iclass 7, count 0 2006.196.07:40:10.31#ibcon#wrote, iclass 7, count 0 2006.196.07:40:10.31#ibcon#about to read 3, iclass 7, count 0 2006.196.07:40:10.36#ibcon#read 3, iclass 7, count 0 2006.196.07:40:10.36#ibcon#about to read 4, iclass 7, count 0 2006.196.07:40:10.36#ibcon#read 4, iclass 7, count 0 2006.196.07:40:10.36#ibcon#about to read 5, iclass 7, count 0 2006.196.07:40:10.36#ibcon#read 5, iclass 7, count 0 2006.196.07:40:10.36#ibcon#about to read 6, iclass 7, count 0 2006.196.07:40:10.36#ibcon#read 6, iclass 7, count 0 2006.196.07:40:10.36#ibcon#end of sib2, iclass 7, count 0 2006.196.07:40:10.36#ibcon#*after write, iclass 7, count 0 2006.196.07:40:10.36#ibcon#*before return 0, iclass 7, count 0 2006.196.07:40:10.36#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.196.07:40:10.36#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.196.07:40:10.36#ibcon#about to clear, iclass 7 cls_cnt 0 2006.196.07:40:10.36#ibcon#cleared, iclass 7 cls_cnt 0 2006.196.07:40:10.36$vc4f8/va=8,7 2006.196.07:40:10.36#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.196.07:40:10.36#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.196.07:40:10.36#ibcon#ireg 11 cls_cnt 2 2006.196.07:40:10.36#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.196.07:40:10.41#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.196.07:40:10.41#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.196.07:40:10.41#ibcon#enter wrdev, iclass 11, count 2 2006.196.07:40:10.41#ibcon#first serial, iclass 11, count 2 2006.196.07:40:10.41#ibcon#enter sib2, iclass 11, count 2 2006.196.07:40:10.41#ibcon#flushed, iclass 11, count 2 2006.196.07:40:10.41#ibcon#about to write, iclass 11, count 2 2006.196.07:40:10.41#ibcon#wrote, iclass 11, count 2 2006.196.07:40:10.41#ibcon#about to read 3, iclass 11, count 2 2006.196.07:40:10.43#ibcon#read 3, iclass 11, count 2 2006.196.07:40:10.43#ibcon#about to read 4, iclass 11, count 2 2006.196.07:40:10.43#ibcon#read 4, iclass 11, count 2 2006.196.07:40:10.43#ibcon#about to read 5, iclass 11, count 2 2006.196.07:40:10.43#ibcon#read 5, iclass 11, count 2 2006.196.07:40:10.43#ibcon#about to read 6, iclass 11, count 2 2006.196.07:40:10.43#ibcon#read 6, iclass 11, count 2 2006.196.07:40:10.43#ibcon#end of sib2, iclass 11, count 2 2006.196.07:40:10.43#ibcon#*mode == 0, iclass 11, count 2 2006.196.07:40:10.43#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.196.07:40:10.43#ibcon#[25=AT08-07\r\n] 2006.196.07:40:10.43#ibcon#*before write, iclass 11, count 2 2006.196.07:40:10.43#ibcon#enter sib2, iclass 11, count 2 2006.196.07:40:10.43#ibcon#flushed, iclass 11, count 2 2006.196.07:40:10.43#ibcon#about to write, iclass 11, count 2 2006.196.07:40:10.43#ibcon#wrote, iclass 11, count 2 2006.196.07:40:10.43#ibcon#about to read 3, iclass 11, count 2 2006.196.07:40:10.46#ibcon#read 3, iclass 11, count 2 2006.196.07:40:10.46#ibcon#about to read 4, iclass 11, count 2 2006.196.07:40:10.46#ibcon#read 4, iclass 11, count 2 2006.196.07:40:10.46#ibcon#about to read 5, iclass 11, count 2 2006.196.07:40:10.46#ibcon#read 5, iclass 11, count 2 2006.196.07:40:10.46#ibcon#about to read 6, iclass 11, count 2 2006.196.07:40:10.46#ibcon#read 6, iclass 11, count 2 2006.196.07:40:10.46#ibcon#end of sib2, iclass 11, count 2 2006.196.07:40:10.46#ibcon#*after write, iclass 11, count 2 2006.196.07:40:10.46#ibcon#*before return 0, iclass 11, count 2 2006.196.07:40:10.46#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.196.07:40:10.46#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.196.07:40:10.46#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.196.07:40:10.46#ibcon#ireg 7 cls_cnt 0 2006.196.07:40:10.46#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.196.07:40:10.58#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.196.07:40:10.58#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.196.07:40:10.58#ibcon#enter wrdev, iclass 11, count 0 2006.196.07:40:10.58#ibcon#first serial, iclass 11, count 0 2006.196.07:40:10.58#ibcon#enter sib2, iclass 11, count 0 2006.196.07:40:10.58#ibcon#flushed, iclass 11, count 0 2006.196.07:40:10.58#ibcon#about to write, iclass 11, count 0 2006.196.07:40:10.58#ibcon#wrote, iclass 11, count 0 2006.196.07:40:10.58#ibcon#about to read 3, iclass 11, count 0 2006.196.07:40:10.60#ibcon#read 3, iclass 11, count 0 2006.196.07:40:10.60#ibcon#about to read 4, iclass 11, count 0 2006.196.07:40:10.60#ibcon#read 4, iclass 11, count 0 2006.196.07:40:10.60#ibcon#about to read 5, iclass 11, count 0 2006.196.07:40:10.60#ibcon#read 5, iclass 11, count 0 2006.196.07:40:10.60#ibcon#about to read 6, iclass 11, count 0 2006.196.07:40:10.60#ibcon#read 6, iclass 11, count 0 2006.196.07:40:10.60#ibcon#end of sib2, iclass 11, count 0 2006.196.07:40:10.60#ibcon#*mode == 0, iclass 11, count 0 2006.196.07:40:10.60#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.196.07:40:10.60#ibcon#[25=USB\r\n] 2006.196.07:40:10.60#ibcon#*before write, iclass 11, count 0 2006.196.07:40:10.60#ibcon#enter sib2, iclass 11, count 0 2006.196.07:40:10.60#ibcon#flushed, iclass 11, count 0 2006.196.07:40:10.60#ibcon#about to write, iclass 11, count 0 2006.196.07:40:10.60#ibcon#wrote, iclass 11, count 0 2006.196.07:40:10.60#ibcon#about to read 3, iclass 11, count 0 2006.196.07:40:10.63#ibcon#read 3, iclass 11, count 0 2006.196.07:40:10.63#ibcon#about to read 4, iclass 11, count 0 2006.196.07:40:10.63#ibcon#read 4, iclass 11, count 0 2006.196.07:40:10.63#ibcon#about to read 5, iclass 11, count 0 2006.196.07:40:10.63#ibcon#read 5, iclass 11, count 0 2006.196.07:40:10.63#ibcon#about to read 6, iclass 11, count 0 2006.196.07:40:10.63#ibcon#read 6, iclass 11, count 0 2006.196.07:40:10.63#ibcon#end of sib2, iclass 11, count 0 2006.196.07:40:10.63#ibcon#*after write, iclass 11, count 0 2006.196.07:40:10.63#ibcon#*before return 0, iclass 11, count 0 2006.196.07:40:10.63#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.196.07:40:10.63#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.196.07:40:10.63#ibcon#about to clear, iclass 11 cls_cnt 0 2006.196.07:40:10.63#ibcon#cleared, iclass 11 cls_cnt 0 2006.196.07:40:10.63$vc4f8/vblo=1,632.99 2006.196.07:40:10.63#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.196.07:40:10.63#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.196.07:40:10.63#ibcon#ireg 17 cls_cnt 0 2006.196.07:40:10.63#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.196.07:40:10.63#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.196.07:40:10.63#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.196.07:40:10.63#ibcon#enter wrdev, iclass 13, count 0 2006.196.07:40:10.63#ibcon#first serial, iclass 13, count 0 2006.196.07:40:10.63#ibcon#enter sib2, iclass 13, count 0 2006.196.07:40:10.63#ibcon#flushed, iclass 13, count 0 2006.196.07:40:10.63#ibcon#about to write, iclass 13, count 0 2006.196.07:40:10.63#ibcon#wrote, iclass 13, count 0 2006.196.07:40:10.63#ibcon#about to read 3, iclass 13, count 0 2006.196.07:40:10.65#ibcon#read 3, iclass 13, count 0 2006.196.07:40:10.65#ibcon#about to read 4, iclass 13, count 0 2006.196.07:40:10.65#ibcon#read 4, iclass 13, count 0 2006.196.07:40:10.65#ibcon#about to read 5, iclass 13, count 0 2006.196.07:40:10.65#ibcon#read 5, iclass 13, count 0 2006.196.07:40:10.65#ibcon#about to read 6, iclass 13, count 0 2006.196.07:40:10.65#ibcon#read 6, iclass 13, count 0 2006.196.07:40:10.65#ibcon#end of sib2, iclass 13, count 0 2006.196.07:40:10.65#ibcon#*mode == 0, iclass 13, count 0 2006.196.07:40:10.65#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.196.07:40:10.65#ibcon#[28=FRQ=01,632.99\r\n] 2006.196.07:40:10.65#ibcon#*before write, iclass 13, count 0 2006.196.07:40:10.65#ibcon#enter sib2, iclass 13, count 0 2006.196.07:40:10.65#ibcon#flushed, iclass 13, count 0 2006.196.07:40:10.65#ibcon#about to write, iclass 13, count 0 2006.196.07:40:10.65#ibcon#wrote, iclass 13, count 0 2006.196.07:40:10.65#ibcon#about to read 3, iclass 13, count 0 2006.196.07:40:10.69#ibcon#read 3, iclass 13, count 0 2006.196.07:40:10.69#ibcon#about to read 4, iclass 13, count 0 2006.196.07:40:10.69#ibcon#read 4, iclass 13, count 0 2006.196.07:40:10.69#ibcon#about to read 5, iclass 13, count 0 2006.196.07:40:10.69#ibcon#read 5, iclass 13, count 0 2006.196.07:40:10.69#ibcon#about to read 6, iclass 13, count 0 2006.196.07:40:10.69#ibcon#read 6, iclass 13, count 0 2006.196.07:40:10.69#ibcon#end of sib2, iclass 13, count 0 2006.196.07:40:10.69#ibcon#*after write, iclass 13, count 0 2006.196.07:40:10.69#ibcon#*before return 0, iclass 13, count 0 2006.196.07:40:10.69#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.196.07:40:10.69#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.196.07:40:10.69#ibcon#about to clear, iclass 13 cls_cnt 0 2006.196.07:40:10.69#ibcon#cleared, iclass 13 cls_cnt 0 2006.196.07:40:10.69$vc4f8/vb=1,4 2006.196.07:40:10.69#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.196.07:40:10.69#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.196.07:40:10.69#ibcon#ireg 11 cls_cnt 2 2006.196.07:40:10.69#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.196.07:40:10.69#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.196.07:40:10.69#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.196.07:40:10.69#ibcon#enter wrdev, iclass 15, count 2 2006.196.07:40:10.69#ibcon#first serial, iclass 15, count 2 2006.196.07:40:10.69#ibcon#enter sib2, iclass 15, count 2 2006.196.07:40:10.69#ibcon#flushed, iclass 15, count 2 2006.196.07:40:10.69#ibcon#about to write, iclass 15, count 2 2006.196.07:40:10.69#ibcon#wrote, iclass 15, count 2 2006.196.07:40:10.69#ibcon#about to read 3, iclass 15, count 2 2006.196.07:40:10.71#ibcon#read 3, iclass 15, count 2 2006.196.07:40:10.71#ibcon#about to read 4, iclass 15, count 2 2006.196.07:40:10.71#ibcon#read 4, iclass 15, count 2 2006.196.07:40:10.71#ibcon#about to read 5, iclass 15, count 2 2006.196.07:40:10.71#ibcon#read 5, iclass 15, count 2 2006.196.07:40:10.71#ibcon#about to read 6, iclass 15, count 2 2006.196.07:40:10.71#ibcon#read 6, iclass 15, count 2 2006.196.07:40:10.71#ibcon#end of sib2, iclass 15, count 2 2006.196.07:40:10.71#ibcon#*mode == 0, iclass 15, count 2 2006.196.07:40:10.71#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.196.07:40:10.71#ibcon#[27=AT01-04\r\n] 2006.196.07:40:10.71#ibcon#*before write, iclass 15, count 2 2006.196.07:40:10.71#ibcon#enter sib2, iclass 15, count 2 2006.196.07:40:10.71#ibcon#flushed, iclass 15, count 2 2006.196.07:40:10.71#ibcon#about to write, iclass 15, count 2 2006.196.07:40:10.71#ibcon#wrote, iclass 15, count 2 2006.196.07:40:10.71#ibcon#about to read 3, iclass 15, count 2 2006.196.07:40:10.74#ibcon#read 3, iclass 15, count 2 2006.196.07:40:10.74#ibcon#about to read 4, iclass 15, count 2 2006.196.07:40:10.74#ibcon#read 4, iclass 15, count 2 2006.196.07:40:10.74#ibcon#about to read 5, iclass 15, count 2 2006.196.07:40:10.74#ibcon#read 5, iclass 15, count 2 2006.196.07:40:10.74#ibcon#about to read 6, iclass 15, count 2 2006.196.07:40:10.74#ibcon#read 6, iclass 15, count 2 2006.196.07:40:10.74#ibcon#end of sib2, iclass 15, count 2 2006.196.07:40:10.74#ibcon#*after write, iclass 15, count 2 2006.196.07:40:10.74#ibcon#*before return 0, iclass 15, count 2 2006.196.07:40:10.74#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.196.07:40:10.74#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.196.07:40:10.74#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.196.07:40:10.74#ibcon#ireg 7 cls_cnt 0 2006.196.07:40:10.74#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.196.07:40:10.86#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.196.07:40:10.86#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.196.07:40:10.86#ibcon#enter wrdev, iclass 15, count 0 2006.196.07:40:10.86#ibcon#first serial, iclass 15, count 0 2006.196.07:40:10.86#ibcon#enter sib2, iclass 15, count 0 2006.196.07:40:10.86#ibcon#flushed, iclass 15, count 0 2006.196.07:40:10.86#ibcon#about to write, iclass 15, count 0 2006.196.07:40:10.86#ibcon#wrote, iclass 15, count 0 2006.196.07:40:10.86#ibcon#about to read 3, iclass 15, count 0 2006.196.07:40:10.88#ibcon#read 3, iclass 15, count 0 2006.196.07:40:10.88#ibcon#about to read 4, iclass 15, count 0 2006.196.07:40:10.88#ibcon#read 4, iclass 15, count 0 2006.196.07:40:10.88#ibcon#about to read 5, iclass 15, count 0 2006.196.07:40:10.88#ibcon#read 5, iclass 15, count 0 2006.196.07:40:10.88#ibcon#about to read 6, iclass 15, count 0 2006.196.07:40:10.88#ibcon#read 6, iclass 15, count 0 2006.196.07:40:10.88#ibcon#end of sib2, iclass 15, count 0 2006.196.07:40:10.88#ibcon#*mode == 0, iclass 15, count 0 2006.196.07:40:10.88#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.196.07:40:10.88#ibcon#[27=USB\r\n] 2006.196.07:40:10.88#ibcon#*before write, iclass 15, count 0 2006.196.07:40:10.88#ibcon#enter sib2, iclass 15, count 0 2006.196.07:40:10.88#ibcon#flushed, iclass 15, count 0 2006.196.07:40:10.88#ibcon#about to write, iclass 15, count 0 2006.196.07:40:10.88#ibcon#wrote, iclass 15, count 0 2006.196.07:40:10.88#ibcon#about to read 3, iclass 15, count 0 2006.196.07:40:10.91#ibcon#read 3, iclass 15, count 0 2006.196.07:40:10.91#ibcon#about to read 4, iclass 15, count 0 2006.196.07:40:10.91#ibcon#read 4, iclass 15, count 0 2006.196.07:40:10.91#ibcon#about to read 5, iclass 15, count 0 2006.196.07:40:10.91#ibcon#read 5, iclass 15, count 0 2006.196.07:40:10.91#ibcon#about to read 6, iclass 15, count 0 2006.196.07:40:10.91#ibcon#read 6, iclass 15, count 0 2006.196.07:40:10.91#ibcon#end of sib2, iclass 15, count 0 2006.196.07:40:10.91#ibcon#*after write, iclass 15, count 0 2006.196.07:40:10.91#ibcon#*before return 0, iclass 15, count 0 2006.196.07:40:10.91#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.196.07:40:10.91#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.196.07:40:10.91#ibcon#about to clear, iclass 15 cls_cnt 0 2006.196.07:40:10.91#ibcon#cleared, iclass 15 cls_cnt 0 2006.196.07:40:10.91$vc4f8/vblo=2,640.99 2006.196.07:40:10.91#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.196.07:40:10.91#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.196.07:40:10.91#ibcon#ireg 17 cls_cnt 0 2006.196.07:40:10.91#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.196.07:40:10.91#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.196.07:40:10.91#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.196.07:40:10.91#ibcon#enter wrdev, iclass 17, count 0 2006.196.07:40:10.91#ibcon#first serial, iclass 17, count 0 2006.196.07:40:10.91#ibcon#enter sib2, iclass 17, count 0 2006.196.07:40:10.91#ibcon#flushed, iclass 17, count 0 2006.196.07:40:10.91#ibcon#about to write, iclass 17, count 0 2006.196.07:40:10.91#ibcon#wrote, iclass 17, count 0 2006.196.07:40:10.91#ibcon#about to read 3, iclass 17, count 0 2006.196.07:40:10.93#ibcon#read 3, iclass 17, count 0 2006.196.07:40:10.93#ibcon#about to read 4, iclass 17, count 0 2006.196.07:40:10.93#ibcon#read 4, iclass 17, count 0 2006.196.07:40:10.93#ibcon#about to read 5, iclass 17, count 0 2006.196.07:40:10.93#ibcon#read 5, iclass 17, count 0 2006.196.07:40:10.93#ibcon#about to read 6, iclass 17, count 0 2006.196.07:40:10.93#ibcon#read 6, iclass 17, count 0 2006.196.07:40:10.93#ibcon#end of sib2, iclass 17, count 0 2006.196.07:40:10.93#ibcon#*mode == 0, iclass 17, count 0 2006.196.07:40:10.93#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.196.07:40:10.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.196.07:40:10.93#ibcon#*before write, iclass 17, count 0 2006.196.07:40:10.93#ibcon#enter sib2, iclass 17, count 0 2006.196.07:40:10.93#ibcon#flushed, iclass 17, count 0 2006.196.07:40:10.93#ibcon#about to write, iclass 17, count 0 2006.196.07:40:10.93#ibcon#wrote, iclass 17, count 0 2006.196.07:40:10.93#ibcon#about to read 3, iclass 17, count 0 2006.196.07:40:10.97#ibcon#read 3, iclass 17, count 0 2006.196.07:40:10.97#ibcon#about to read 4, iclass 17, count 0 2006.196.07:40:10.97#ibcon#read 4, iclass 17, count 0 2006.196.07:40:10.97#ibcon#about to read 5, iclass 17, count 0 2006.196.07:40:10.97#ibcon#read 5, iclass 17, count 0 2006.196.07:40:10.97#ibcon#about to read 6, iclass 17, count 0 2006.196.07:40:10.97#ibcon#read 6, iclass 17, count 0 2006.196.07:40:10.97#ibcon#end of sib2, iclass 17, count 0 2006.196.07:40:10.97#ibcon#*after write, iclass 17, count 0 2006.196.07:40:10.97#ibcon#*before return 0, iclass 17, count 0 2006.196.07:40:10.97#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.196.07:40:10.97#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.196.07:40:10.97#ibcon#about to clear, iclass 17 cls_cnt 0 2006.196.07:40:10.97#ibcon#cleared, iclass 17 cls_cnt 0 2006.196.07:40:10.97$vc4f8/vb=2,4 2006.196.07:40:10.97#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.196.07:40:10.97#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.196.07:40:10.97#ibcon#ireg 11 cls_cnt 2 2006.196.07:40:10.97#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.196.07:40:11.03#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.196.07:40:11.03#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.196.07:40:11.03#ibcon#enter wrdev, iclass 19, count 2 2006.196.07:40:11.03#ibcon#first serial, iclass 19, count 2 2006.196.07:40:11.03#ibcon#enter sib2, iclass 19, count 2 2006.196.07:40:11.03#ibcon#flushed, iclass 19, count 2 2006.196.07:40:11.03#ibcon#about to write, iclass 19, count 2 2006.196.07:40:11.03#ibcon#wrote, iclass 19, count 2 2006.196.07:40:11.03#ibcon#about to read 3, iclass 19, count 2 2006.196.07:40:11.05#ibcon#read 3, iclass 19, count 2 2006.196.07:40:11.05#ibcon#about to read 4, iclass 19, count 2 2006.196.07:40:11.05#ibcon#read 4, iclass 19, count 2 2006.196.07:40:11.05#ibcon#about to read 5, iclass 19, count 2 2006.196.07:40:11.05#ibcon#read 5, iclass 19, count 2 2006.196.07:40:11.05#ibcon#about to read 6, iclass 19, count 2 2006.196.07:40:11.05#ibcon#read 6, iclass 19, count 2 2006.196.07:40:11.05#ibcon#end of sib2, iclass 19, count 2 2006.196.07:40:11.05#ibcon#*mode == 0, iclass 19, count 2 2006.196.07:40:11.05#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.196.07:40:11.05#ibcon#[27=AT02-04\r\n] 2006.196.07:40:11.05#ibcon#*before write, iclass 19, count 2 2006.196.07:40:11.05#ibcon#enter sib2, iclass 19, count 2 2006.196.07:40:11.05#ibcon#flushed, iclass 19, count 2 2006.196.07:40:11.05#ibcon#about to write, iclass 19, count 2 2006.196.07:40:11.05#ibcon#wrote, iclass 19, count 2 2006.196.07:40:11.05#ibcon#about to read 3, iclass 19, count 2 2006.196.07:40:11.08#ibcon#read 3, iclass 19, count 2 2006.196.07:40:11.08#ibcon#about to read 4, iclass 19, count 2 2006.196.07:40:11.08#ibcon#read 4, iclass 19, count 2 2006.196.07:40:11.08#ibcon#about to read 5, iclass 19, count 2 2006.196.07:40:11.08#ibcon#read 5, iclass 19, count 2 2006.196.07:40:11.08#ibcon#about to read 6, iclass 19, count 2 2006.196.07:40:11.08#ibcon#read 6, iclass 19, count 2 2006.196.07:40:11.08#ibcon#end of sib2, iclass 19, count 2 2006.196.07:40:11.08#ibcon#*after write, iclass 19, count 2 2006.196.07:40:11.08#ibcon#*before return 0, iclass 19, count 2 2006.196.07:40:11.08#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.196.07:40:11.08#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.196.07:40:11.08#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.196.07:40:11.08#ibcon#ireg 7 cls_cnt 0 2006.196.07:40:11.08#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.196.07:40:11.20#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.196.07:40:11.20#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.196.07:40:11.20#ibcon#enter wrdev, iclass 19, count 0 2006.196.07:40:11.20#ibcon#first serial, iclass 19, count 0 2006.196.07:40:11.20#ibcon#enter sib2, iclass 19, count 0 2006.196.07:40:11.20#ibcon#flushed, iclass 19, count 0 2006.196.07:40:11.20#ibcon#about to write, iclass 19, count 0 2006.196.07:40:11.20#ibcon#wrote, iclass 19, count 0 2006.196.07:40:11.20#ibcon#about to read 3, iclass 19, count 0 2006.196.07:40:11.23#ibcon#read 3, iclass 19, count 0 2006.196.07:40:11.23#ibcon#about to read 4, iclass 19, count 0 2006.196.07:40:11.23#ibcon#read 4, iclass 19, count 0 2006.196.07:40:11.23#ibcon#about to read 5, iclass 19, count 0 2006.196.07:40:11.23#ibcon#read 5, iclass 19, count 0 2006.196.07:40:11.23#ibcon#about to read 6, iclass 19, count 0 2006.196.07:40:11.23#ibcon#read 6, iclass 19, count 0 2006.196.07:40:11.23#ibcon#end of sib2, iclass 19, count 0 2006.196.07:40:11.23#ibcon#*mode == 0, iclass 19, count 0 2006.196.07:40:11.23#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.196.07:40:11.23#ibcon#[27=USB\r\n] 2006.196.07:40:11.23#ibcon#*before write, iclass 19, count 0 2006.196.07:40:11.23#ibcon#enter sib2, iclass 19, count 0 2006.196.07:40:11.23#ibcon#flushed, iclass 19, count 0 2006.196.07:40:11.23#ibcon#about to write, iclass 19, count 0 2006.196.07:40:11.23#ibcon#wrote, iclass 19, count 0 2006.196.07:40:11.23#ibcon#about to read 3, iclass 19, count 0 2006.196.07:40:11.26#ibcon#read 3, iclass 19, count 0 2006.196.07:40:11.26#ibcon#about to read 4, iclass 19, count 0 2006.196.07:40:11.26#ibcon#read 4, iclass 19, count 0 2006.196.07:40:11.26#ibcon#about to read 5, iclass 19, count 0 2006.196.07:40:11.26#ibcon#read 5, iclass 19, count 0 2006.196.07:40:11.26#ibcon#about to read 6, iclass 19, count 0 2006.196.07:40:11.26#ibcon#read 6, iclass 19, count 0 2006.196.07:40:11.26#ibcon#end of sib2, iclass 19, count 0 2006.196.07:40:11.26#ibcon#*after write, iclass 19, count 0 2006.196.07:40:11.26#ibcon#*before return 0, iclass 19, count 0 2006.196.07:40:11.26#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.196.07:40:11.26#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.196.07:40:11.26#ibcon#about to clear, iclass 19 cls_cnt 0 2006.196.07:40:11.26#ibcon#cleared, iclass 19 cls_cnt 0 2006.196.07:40:11.26$vc4f8/vblo=3,656.99 2006.196.07:40:11.26#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.196.07:40:11.26#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.196.07:40:11.26#ibcon#ireg 17 cls_cnt 0 2006.196.07:40:11.26#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.196.07:40:11.26#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.196.07:40:11.26#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.196.07:40:11.26#ibcon#enter wrdev, iclass 21, count 0 2006.196.07:40:11.26#ibcon#first serial, iclass 21, count 0 2006.196.07:40:11.26#ibcon#enter sib2, iclass 21, count 0 2006.196.07:40:11.26#ibcon#flushed, iclass 21, count 0 2006.196.07:40:11.26#ibcon#about to write, iclass 21, count 0 2006.196.07:40:11.26#ibcon#wrote, iclass 21, count 0 2006.196.07:40:11.26#ibcon#about to read 3, iclass 21, count 0 2006.196.07:40:11.28#ibcon#read 3, iclass 21, count 0 2006.196.07:40:11.28#ibcon#about to read 4, iclass 21, count 0 2006.196.07:40:11.28#ibcon#read 4, iclass 21, count 0 2006.196.07:40:11.28#ibcon#about to read 5, iclass 21, count 0 2006.196.07:40:11.28#ibcon#read 5, iclass 21, count 0 2006.196.07:40:11.28#ibcon#about to read 6, iclass 21, count 0 2006.196.07:40:11.28#ibcon#read 6, iclass 21, count 0 2006.196.07:40:11.28#ibcon#end of sib2, iclass 21, count 0 2006.196.07:40:11.28#ibcon#*mode == 0, iclass 21, count 0 2006.196.07:40:11.28#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.196.07:40:11.28#ibcon#[28=FRQ=03,656.99\r\n] 2006.196.07:40:11.28#ibcon#*before write, iclass 21, count 0 2006.196.07:40:11.28#ibcon#enter sib2, iclass 21, count 0 2006.196.07:40:11.28#ibcon#flushed, iclass 21, count 0 2006.196.07:40:11.28#ibcon#about to write, iclass 21, count 0 2006.196.07:40:11.28#ibcon#wrote, iclass 21, count 0 2006.196.07:40:11.28#ibcon#about to read 3, iclass 21, count 0 2006.196.07:40:11.32#ibcon#read 3, iclass 21, count 0 2006.196.07:40:11.32#ibcon#about to read 4, iclass 21, count 0 2006.196.07:40:11.32#ibcon#read 4, iclass 21, count 0 2006.196.07:40:11.32#ibcon#about to read 5, iclass 21, count 0 2006.196.07:40:11.32#ibcon#read 5, iclass 21, count 0 2006.196.07:40:11.32#ibcon#about to read 6, iclass 21, count 0 2006.196.07:40:11.32#ibcon#read 6, iclass 21, count 0 2006.196.07:40:11.32#ibcon#end of sib2, iclass 21, count 0 2006.196.07:40:11.32#ibcon#*after write, iclass 21, count 0 2006.196.07:40:11.32#ibcon#*before return 0, iclass 21, count 0 2006.196.07:40:11.32#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.196.07:40:11.32#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.196.07:40:11.32#ibcon#about to clear, iclass 21 cls_cnt 0 2006.196.07:40:11.32#ibcon#cleared, iclass 21 cls_cnt 0 2006.196.07:40:11.32$vc4f8/vb=3,4 2006.196.07:40:11.32#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.196.07:40:11.32#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.196.07:40:11.32#ibcon#ireg 11 cls_cnt 2 2006.196.07:40:11.32#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.196.07:40:11.38#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.196.07:40:11.38#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.196.07:40:11.38#ibcon#enter wrdev, iclass 23, count 2 2006.196.07:40:11.38#ibcon#first serial, iclass 23, count 2 2006.196.07:40:11.38#ibcon#enter sib2, iclass 23, count 2 2006.196.07:40:11.38#ibcon#flushed, iclass 23, count 2 2006.196.07:40:11.38#ibcon#about to write, iclass 23, count 2 2006.196.07:40:11.38#ibcon#wrote, iclass 23, count 2 2006.196.07:40:11.38#ibcon#about to read 3, iclass 23, count 2 2006.196.07:40:11.40#ibcon#read 3, iclass 23, count 2 2006.196.07:40:11.40#ibcon#about to read 4, iclass 23, count 2 2006.196.07:40:11.40#ibcon#read 4, iclass 23, count 2 2006.196.07:40:11.40#ibcon#about to read 5, iclass 23, count 2 2006.196.07:40:11.40#ibcon#read 5, iclass 23, count 2 2006.196.07:40:11.40#ibcon#about to read 6, iclass 23, count 2 2006.196.07:40:11.40#ibcon#read 6, iclass 23, count 2 2006.196.07:40:11.40#ibcon#end of sib2, iclass 23, count 2 2006.196.07:40:11.40#ibcon#*mode == 0, iclass 23, count 2 2006.196.07:40:11.40#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.196.07:40:11.40#ibcon#[27=AT03-04\r\n] 2006.196.07:40:11.40#ibcon#*before write, iclass 23, count 2 2006.196.07:40:11.40#ibcon#enter sib2, iclass 23, count 2 2006.196.07:40:11.40#ibcon#flushed, iclass 23, count 2 2006.196.07:40:11.40#ibcon#about to write, iclass 23, count 2 2006.196.07:40:11.40#ibcon#wrote, iclass 23, count 2 2006.196.07:40:11.40#ibcon#about to read 3, iclass 23, count 2 2006.196.07:40:11.43#ibcon#read 3, iclass 23, count 2 2006.196.07:40:11.43#ibcon#about to read 4, iclass 23, count 2 2006.196.07:40:11.43#ibcon#read 4, iclass 23, count 2 2006.196.07:40:11.43#ibcon#about to read 5, iclass 23, count 2 2006.196.07:40:11.43#ibcon#read 5, iclass 23, count 2 2006.196.07:40:11.43#ibcon#about to read 6, iclass 23, count 2 2006.196.07:40:11.43#ibcon#read 6, iclass 23, count 2 2006.196.07:40:11.43#ibcon#end of sib2, iclass 23, count 2 2006.196.07:40:11.43#ibcon#*after write, iclass 23, count 2 2006.196.07:40:11.43#ibcon#*before return 0, iclass 23, count 2 2006.196.07:40:11.43#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.196.07:40:11.43#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.196.07:40:11.43#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.196.07:40:11.43#ibcon#ireg 7 cls_cnt 0 2006.196.07:40:11.43#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.196.07:40:11.55#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.196.07:40:11.55#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.196.07:40:11.55#ibcon#enter wrdev, iclass 23, count 0 2006.196.07:40:11.55#ibcon#first serial, iclass 23, count 0 2006.196.07:40:11.55#ibcon#enter sib2, iclass 23, count 0 2006.196.07:40:11.55#ibcon#flushed, iclass 23, count 0 2006.196.07:40:11.55#ibcon#about to write, iclass 23, count 0 2006.196.07:40:11.55#ibcon#wrote, iclass 23, count 0 2006.196.07:40:11.55#ibcon#about to read 3, iclass 23, count 0 2006.196.07:40:11.57#ibcon#read 3, iclass 23, count 0 2006.196.07:40:11.57#ibcon#about to read 4, iclass 23, count 0 2006.196.07:40:11.57#ibcon#read 4, iclass 23, count 0 2006.196.07:40:11.57#ibcon#about to read 5, iclass 23, count 0 2006.196.07:40:11.57#ibcon#read 5, iclass 23, count 0 2006.196.07:40:11.57#ibcon#about to read 6, iclass 23, count 0 2006.196.07:40:11.57#ibcon#read 6, iclass 23, count 0 2006.196.07:40:11.57#ibcon#end of sib2, iclass 23, count 0 2006.196.07:40:11.57#ibcon#*mode == 0, iclass 23, count 0 2006.196.07:40:11.57#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.196.07:40:11.57#ibcon#[27=USB\r\n] 2006.196.07:40:11.57#ibcon#*before write, iclass 23, count 0 2006.196.07:40:11.57#ibcon#enter sib2, iclass 23, count 0 2006.196.07:40:11.57#ibcon#flushed, iclass 23, count 0 2006.196.07:40:11.57#ibcon#about to write, iclass 23, count 0 2006.196.07:40:11.57#ibcon#wrote, iclass 23, count 0 2006.196.07:40:11.57#ibcon#about to read 3, iclass 23, count 0 2006.196.07:40:11.60#ibcon#read 3, iclass 23, count 0 2006.196.07:40:11.60#ibcon#about to read 4, iclass 23, count 0 2006.196.07:40:11.60#ibcon#read 4, iclass 23, count 0 2006.196.07:40:11.60#ibcon#about to read 5, iclass 23, count 0 2006.196.07:40:11.60#ibcon#read 5, iclass 23, count 0 2006.196.07:40:11.60#ibcon#about to read 6, iclass 23, count 0 2006.196.07:40:11.60#ibcon#read 6, iclass 23, count 0 2006.196.07:40:11.60#ibcon#end of sib2, iclass 23, count 0 2006.196.07:40:11.60#ibcon#*after write, iclass 23, count 0 2006.196.07:40:11.60#ibcon#*before return 0, iclass 23, count 0 2006.196.07:40:11.60#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.196.07:40:11.60#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.196.07:40:11.60#ibcon#about to clear, iclass 23 cls_cnt 0 2006.196.07:40:11.60#ibcon#cleared, iclass 23 cls_cnt 0 2006.196.07:40:11.60$vc4f8/vblo=4,712.99 2006.196.07:40:11.60#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.196.07:40:11.60#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.196.07:40:11.60#ibcon#ireg 17 cls_cnt 0 2006.196.07:40:11.60#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.196.07:40:11.60#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.196.07:40:11.60#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.196.07:40:11.60#ibcon#enter wrdev, iclass 25, count 0 2006.196.07:40:11.60#ibcon#first serial, iclass 25, count 0 2006.196.07:40:11.60#ibcon#enter sib2, iclass 25, count 0 2006.196.07:40:11.60#ibcon#flushed, iclass 25, count 0 2006.196.07:40:11.60#ibcon#about to write, iclass 25, count 0 2006.196.07:40:11.60#ibcon#wrote, iclass 25, count 0 2006.196.07:40:11.60#ibcon#about to read 3, iclass 25, count 0 2006.196.07:40:11.62#ibcon#read 3, iclass 25, count 0 2006.196.07:40:11.62#ibcon#about to read 4, iclass 25, count 0 2006.196.07:40:11.62#ibcon#read 4, iclass 25, count 0 2006.196.07:40:11.62#ibcon#about to read 5, iclass 25, count 0 2006.196.07:40:11.62#ibcon#read 5, iclass 25, count 0 2006.196.07:40:11.62#ibcon#about to read 6, iclass 25, count 0 2006.196.07:40:11.62#ibcon#read 6, iclass 25, count 0 2006.196.07:40:11.62#ibcon#end of sib2, iclass 25, count 0 2006.196.07:40:11.62#ibcon#*mode == 0, iclass 25, count 0 2006.196.07:40:11.62#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.196.07:40:11.62#ibcon#[28=FRQ=04,712.99\r\n] 2006.196.07:40:11.62#ibcon#*before write, iclass 25, count 0 2006.196.07:40:11.62#ibcon#enter sib2, iclass 25, count 0 2006.196.07:40:11.62#ibcon#flushed, iclass 25, count 0 2006.196.07:40:11.62#ibcon#about to write, iclass 25, count 0 2006.196.07:40:11.62#ibcon#wrote, iclass 25, count 0 2006.196.07:40:11.62#ibcon#about to read 3, iclass 25, count 0 2006.196.07:40:11.66#ibcon#read 3, iclass 25, count 0 2006.196.07:40:11.66#ibcon#about to read 4, iclass 25, count 0 2006.196.07:40:11.66#ibcon#read 4, iclass 25, count 0 2006.196.07:40:11.66#ibcon#about to read 5, iclass 25, count 0 2006.196.07:40:11.66#ibcon#read 5, iclass 25, count 0 2006.196.07:40:11.66#ibcon#about to read 6, iclass 25, count 0 2006.196.07:40:11.66#ibcon#read 6, iclass 25, count 0 2006.196.07:40:11.66#ibcon#end of sib2, iclass 25, count 0 2006.196.07:40:11.66#ibcon#*after write, iclass 25, count 0 2006.196.07:40:11.66#ibcon#*before return 0, iclass 25, count 0 2006.196.07:40:11.66#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.196.07:40:11.66#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.196.07:40:11.66#ibcon#about to clear, iclass 25 cls_cnt 0 2006.196.07:40:11.66#ibcon#cleared, iclass 25 cls_cnt 0 2006.196.07:40:11.66$vc4f8/vb=4,4 2006.196.07:40:11.66#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.196.07:40:11.66#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.196.07:40:11.66#ibcon#ireg 11 cls_cnt 2 2006.196.07:40:11.66#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.196.07:40:11.72#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.196.07:40:11.72#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.196.07:40:11.72#ibcon#enter wrdev, iclass 27, count 2 2006.196.07:40:11.72#ibcon#first serial, iclass 27, count 2 2006.196.07:40:11.72#ibcon#enter sib2, iclass 27, count 2 2006.196.07:40:11.72#ibcon#flushed, iclass 27, count 2 2006.196.07:40:11.72#ibcon#about to write, iclass 27, count 2 2006.196.07:40:11.72#ibcon#wrote, iclass 27, count 2 2006.196.07:40:11.72#ibcon#about to read 3, iclass 27, count 2 2006.196.07:40:11.74#ibcon#read 3, iclass 27, count 2 2006.196.07:40:11.74#ibcon#about to read 4, iclass 27, count 2 2006.196.07:40:11.74#ibcon#read 4, iclass 27, count 2 2006.196.07:40:11.74#ibcon#about to read 5, iclass 27, count 2 2006.196.07:40:11.74#ibcon#read 5, iclass 27, count 2 2006.196.07:40:11.74#ibcon#about to read 6, iclass 27, count 2 2006.196.07:40:11.74#ibcon#read 6, iclass 27, count 2 2006.196.07:40:11.74#ibcon#end of sib2, iclass 27, count 2 2006.196.07:40:11.74#ibcon#*mode == 0, iclass 27, count 2 2006.196.07:40:11.74#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.196.07:40:11.74#ibcon#[27=AT04-04\r\n] 2006.196.07:40:11.74#ibcon#*before write, iclass 27, count 2 2006.196.07:40:11.74#ibcon#enter sib2, iclass 27, count 2 2006.196.07:40:11.74#ibcon#flushed, iclass 27, count 2 2006.196.07:40:11.74#ibcon#about to write, iclass 27, count 2 2006.196.07:40:11.74#ibcon#wrote, iclass 27, count 2 2006.196.07:40:11.74#ibcon#about to read 3, iclass 27, count 2 2006.196.07:40:11.77#ibcon#read 3, iclass 27, count 2 2006.196.07:40:11.77#ibcon#about to read 4, iclass 27, count 2 2006.196.07:40:11.77#ibcon#read 4, iclass 27, count 2 2006.196.07:40:11.77#ibcon#about to read 5, iclass 27, count 2 2006.196.07:40:11.77#ibcon#read 5, iclass 27, count 2 2006.196.07:40:11.77#ibcon#about to read 6, iclass 27, count 2 2006.196.07:40:11.77#ibcon#read 6, iclass 27, count 2 2006.196.07:40:11.77#ibcon#end of sib2, iclass 27, count 2 2006.196.07:40:11.77#ibcon#*after write, iclass 27, count 2 2006.196.07:40:11.77#ibcon#*before return 0, iclass 27, count 2 2006.196.07:40:11.77#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.196.07:40:11.77#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.196.07:40:11.77#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.196.07:40:11.77#ibcon#ireg 7 cls_cnt 0 2006.196.07:40:11.77#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.196.07:40:11.89#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.196.07:40:11.89#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.196.07:40:11.89#ibcon#enter wrdev, iclass 27, count 0 2006.196.07:40:11.89#ibcon#first serial, iclass 27, count 0 2006.196.07:40:11.89#ibcon#enter sib2, iclass 27, count 0 2006.196.07:40:11.89#ibcon#flushed, iclass 27, count 0 2006.196.07:40:11.89#ibcon#about to write, iclass 27, count 0 2006.196.07:40:11.89#ibcon#wrote, iclass 27, count 0 2006.196.07:40:11.89#ibcon#about to read 3, iclass 27, count 0 2006.196.07:40:11.91#ibcon#read 3, iclass 27, count 0 2006.196.07:40:11.91#ibcon#about to read 4, iclass 27, count 0 2006.196.07:40:11.91#ibcon#read 4, iclass 27, count 0 2006.196.07:40:11.91#ibcon#about to read 5, iclass 27, count 0 2006.196.07:40:11.91#ibcon#read 5, iclass 27, count 0 2006.196.07:40:11.91#ibcon#about to read 6, iclass 27, count 0 2006.196.07:40:11.91#ibcon#read 6, iclass 27, count 0 2006.196.07:40:11.91#ibcon#end of sib2, iclass 27, count 0 2006.196.07:40:11.91#ibcon#*mode == 0, iclass 27, count 0 2006.196.07:40:11.91#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.196.07:40:11.91#ibcon#[27=USB\r\n] 2006.196.07:40:11.91#ibcon#*before write, iclass 27, count 0 2006.196.07:40:11.91#ibcon#enter sib2, iclass 27, count 0 2006.196.07:40:11.91#ibcon#flushed, iclass 27, count 0 2006.196.07:40:11.91#ibcon#about to write, iclass 27, count 0 2006.196.07:40:11.91#ibcon#wrote, iclass 27, count 0 2006.196.07:40:11.91#ibcon#about to read 3, iclass 27, count 0 2006.196.07:40:11.94#ibcon#read 3, iclass 27, count 0 2006.196.07:40:11.94#ibcon#about to read 4, iclass 27, count 0 2006.196.07:40:11.94#ibcon#read 4, iclass 27, count 0 2006.196.07:40:11.94#ibcon#about to read 5, iclass 27, count 0 2006.196.07:40:11.94#ibcon#read 5, iclass 27, count 0 2006.196.07:40:11.94#ibcon#about to read 6, iclass 27, count 0 2006.196.07:40:11.94#ibcon#read 6, iclass 27, count 0 2006.196.07:40:11.94#ibcon#end of sib2, iclass 27, count 0 2006.196.07:40:11.94#ibcon#*after write, iclass 27, count 0 2006.196.07:40:11.94#ibcon#*before return 0, iclass 27, count 0 2006.196.07:40:11.94#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.196.07:40:11.94#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.196.07:40:11.94#ibcon#about to clear, iclass 27 cls_cnt 0 2006.196.07:40:11.94#ibcon#cleared, iclass 27 cls_cnt 0 2006.196.07:40:11.94$vc4f8/vblo=5,744.99 2006.196.07:40:11.94#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.196.07:40:11.94#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.196.07:40:11.94#ibcon#ireg 17 cls_cnt 0 2006.196.07:40:11.94#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.196.07:40:11.94#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.196.07:40:11.94#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.196.07:40:11.94#ibcon#enter wrdev, iclass 29, count 0 2006.196.07:40:11.94#ibcon#first serial, iclass 29, count 0 2006.196.07:40:11.94#ibcon#enter sib2, iclass 29, count 0 2006.196.07:40:11.94#ibcon#flushed, iclass 29, count 0 2006.196.07:40:11.94#ibcon#about to write, iclass 29, count 0 2006.196.07:40:11.94#ibcon#wrote, iclass 29, count 0 2006.196.07:40:11.94#ibcon#about to read 3, iclass 29, count 0 2006.196.07:40:11.96#ibcon#read 3, iclass 29, count 0 2006.196.07:40:11.96#ibcon#about to read 4, iclass 29, count 0 2006.196.07:40:11.96#ibcon#read 4, iclass 29, count 0 2006.196.07:40:11.96#ibcon#about to read 5, iclass 29, count 0 2006.196.07:40:11.96#ibcon#read 5, iclass 29, count 0 2006.196.07:40:11.96#ibcon#about to read 6, iclass 29, count 0 2006.196.07:40:11.96#ibcon#read 6, iclass 29, count 0 2006.196.07:40:11.96#ibcon#end of sib2, iclass 29, count 0 2006.196.07:40:11.96#ibcon#*mode == 0, iclass 29, count 0 2006.196.07:40:11.96#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.196.07:40:11.96#ibcon#[28=FRQ=05,744.99\r\n] 2006.196.07:40:11.96#ibcon#*before write, iclass 29, count 0 2006.196.07:40:11.96#ibcon#enter sib2, iclass 29, count 0 2006.196.07:40:11.96#ibcon#flushed, iclass 29, count 0 2006.196.07:40:11.96#ibcon#about to write, iclass 29, count 0 2006.196.07:40:11.96#ibcon#wrote, iclass 29, count 0 2006.196.07:40:11.96#ibcon#about to read 3, iclass 29, count 0 2006.196.07:40:12.01#ibcon#read 3, iclass 29, count 0 2006.196.07:40:12.01#ibcon#about to read 4, iclass 29, count 0 2006.196.07:40:12.01#ibcon#read 4, iclass 29, count 0 2006.196.07:40:12.01#ibcon#about to read 5, iclass 29, count 0 2006.196.07:40:12.01#ibcon#read 5, iclass 29, count 0 2006.196.07:40:12.01#ibcon#about to read 6, iclass 29, count 0 2006.196.07:40:12.01#ibcon#read 6, iclass 29, count 0 2006.196.07:40:12.01#ibcon#end of sib2, iclass 29, count 0 2006.196.07:40:12.01#ibcon#*after write, iclass 29, count 0 2006.196.07:40:12.01#ibcon#*before return 0, iclass 29, count 0 2006.196.07:40:12.01#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.196.07:40:12.01#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.196.07:40:12.01#ibcon#about to clear, iclass 29 cls_cnt 0 2006.196.07:40:12.01#ibcon#cleared, iclass 29 cls_cnt 0 2006.196.07:40:12.01$vc4f8/vb=5,4 2006.196.07:40:12.01#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.196.07:40:12.01#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.196.07:40:12.01#ibcon#ireg 11 cls_cnt 2 2006.196.07:40:12.01#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.196.07:40:12.06#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.196.07:40:12.06#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.196.07:40:12.06#ibcon#enter wrdev, iclass 31, count 2 2006.196.07:40:12.06#ibcon#first serial, iclass 31, count 2 2006.196.07:40:12.06#ibcon#enter sib2, iclass 31, count 2 2006.196.07:40:12.06#ibcon#flushed, iclass 31, count 2 2006.196.07:40:12.06#ibcon#about to write, iclass 31, count 2 2006.196.07:40:12.06#ibcon#wrote, iclass 31, count 2 2006.196.07:40:12.06#ibcon#about to read 3, iclass 31, count 2 2006.196.07:40:12.08#ibcon#read 3, iclass 31, count 2 2006.196.07:40:12.08#ibcon#about to read 4, iclass 31, count 2 2006.196.07:40:12.08#ibcon#read 4, iclass 31, count 2 2006.196.07:40:12.08#ibcon#about to read 5, iclass 31, count 2 2006.196.07:40:12.08#ibcon#read 5, iclass 31, count 2 2006.196.07:40:12.08#ibcon#about to read 6, iclass 31, count 2 2006.196.07:40:12.08#ibcon#read 6, iclass 31, count 2 2006.196.07:40:12.08#ibcon#end of sib2, iclass 31, count 2 2006.196.07:40:12.08#ibcon#*mode == 0, iclass 31, count 2 2006.196.07:40:12.08#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.196.07:40:12.08#ibcon#[27=AT05-04\r\n] 2006.196.07:40:12.08#ibcon#*before write, iclass 31, count 2 2006.196.07:40:12.08#ibcon#enter sib2, iclass 31, count 2 2006.196.07:40:12.08#ibcon#flushed, iclass 31, count 2 2006.196.07:40:12.08#ibcon#about to write, iclass 31, count 2 2006.196.07:40:12.08#ibcon#wrote, iclass 31, count 2 2006.196.07:40:12.08#ibcon#about to read 3, iclass 31, count 2 2006.196.07:40:12.11#ibcon#read 3, iclass 31, count 2 2006.196.07:40:12.11#ibcon#about to read 4, iclass 31, count 2 2006.196.07:40:12.11#ibcon#read 4, iclass 31, count 2 2006.196.07:40:12.11#ibcon#about to read 5, iclass 31, count 2 2006.196.07:40:12.11#ibcon#read 5, iclass 31, count 2 2006.196.07:40:12.11#ibcon#about to read 6, iclass 31, count 2 2006.196.07:40:12.11#ibcon#read 6, iclass 31, count 2 2006.196.07:40:12.11#ibcon#end of sib2, iclass 31, count 2 2006.196.07:40:12.11#ibcon#*after write, iclass 31, count 2 2006.196.07:40:12.11#ibcon#*before return 0, iclass 31, count 2 2006.196.07:40:12.11#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.196.07:40:12.11#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.196.07:40:12.11#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.196.07:40:12.11#ibcon#ireg 7 cls_cnt 0 2006.196.07:40:12.11#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.196.07:40:12.23#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.196.07:40:12.23#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.196.07:40:12.23#ibcon#enter wrdev, iclass 31, count 0 2006.196.07:40:12.23#ibcon#first serial, iclass 31, count 0 2006.196.07:40:12.23#ibcon#enter sib2, iclass 31, count 0 2006.196.07:40:12.23#ibcon#flushed, iclass 31, count 0 2006.196.07:40:12.23#ibcon#about to write, iclass 31, count 0 2006.196.07:40:12.23#ibcon#wrote, iclass 31, count 0 2006.196.07:40:12.23#ibcon#about to read 3, iclass 31, count 0 2006.196.07:40:12.25#ibcon#read 3, iclass 31, count 0 2006.196.07:40:12.25#ibcon#about to read 4, iclass 31, count 0 2006.196.07:40:12.25#ibcon#read 4, iclass 31, count 0 2006.196.07:40:12.25#ibcon#about to read 5, iclass 31, count 0 2006.196.07:40:12.25#ibcon#read 5, iclass 31, count 0 2006.196.07:40:12.25#ibcon#about to read 6, iclass 31, count 0 2006.196.07:40:12.25#ibcon#read 6, iclass 31, count 0 2006.196.07:40:12.25#ibcon#end of sib2, iclass 31, count 0 2006.196.07:40:12.25#ibcon#*mode == 0, iclass 31, count 0 2006.196.07:40:12.25#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.196.07:40:12.25#ibcon#[27=USB\r\n] 2006.196.07:40:12.25#ibcon#*before write, iclass 31, count 0 2006.196.07:40:12.25#ibcon#enter sib2, iclass 31, count 0 2006.196.07:40:12.25#ibcon#flushed, iclass 31, count 0 2006.196.07:40:12.25#ibcon#about to write, iclass 31, count 0 2006.196.07:40:12.25#ibcon#wrote, iclass 31, count 0 2006.196.07:40:12.25#ibcon#about to read 3, iclass 31, count 0 2006.196.07:40:12.28#ibcon#read 3, iclass 31, count 0 2006.196.07:40:12.28#ibcon#about to read 4, iclass 31, count 0 2006.196.07:40:12.28#ibcon#read 4, iclass 31, count 0 2006.196.07:40:12.28#ibcon#about to read 5, iclass 31, count 0 2006.196.07:40:12.28#ibcon#read 5, iclass 31, count 0 2006.196.07:40:12.28#ibcon#about to read 6, iclass 31, count 0 2006.196.07:40:12.28#ibcon#read 6, iclass 31, count 0 2006.196.07:40:12.28#ibcon#end of sib2, iclass 31, count 0 2006.196.07:40:12.28#ibcon#*after write, iclass 31, count 0 2006.196.07:40:12.28#ibcon#*before return 0, iclass 31, count 0 2006.196.07:40:12.28#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.196.07:40:12.28#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.196.07:40:12.28#ibcon#about to clear, iclass 31 cls_cnt 0 2006.196.07:40:12.28#ibcon#cleared, iclass 31 cls_cnt 0 2006.196.07:40:12.28$vc4f8/vblo=6,752.99 2006.196.07:40:12.28#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.196.07:40:12.28#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.196.07:40:12.28#ibcon#ireg 17 cls_cnt 0 2006.196.07:40:12.28#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.196.07:40:12.28#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.196.07:40:12.28#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.196.07:40:12.28#ibcon#enter wrdev, iclass 33, count 0 2006.196.07:40:12.28#ibcon#first serial, iclass 33, count 0 2006.196.07:40:12.28#ibcon#enter sib2, iclass 33, count 0 2006.196.07:40:12.28#ibcon#flushed, iclass 33, count 0 2006.196.07:40:12.28#ibcon#about to write, iclass 33, count 0 2006.196.07:40:12.28#ibcon#wrote, iclass 33, count 0 2006.196.07:40:12.28#ibcon#about to read 3, iclass 33, count 0 2006.196.07:40:12.30#ibcon#read 3, iclass 33, count 0 2006.196.07:40:12.30#ibcon#about to read 4, iclass 33, count 0 2006.196.07:40:12.30#ibcon#read 4, iclass 33, count 0 2006.196.07:40:12.30#ibcon#about to read 5, iclass 33, count 0 2006.196.07:40:12.30#ibcon#read 5, iclass 33, count 0 2006.196.07:40:12.30#ibcon#about to read 6, iclass 33, count 0 2006.196.07:40:12.30#ibcon#read 6, iclass 33, count 0 2006.196.07:40:12.30#ibcon#end of sib2, iclass 33, count 0 2006.196.07:40:12.30#ibcon#*mode == 0, iclass 33, count 0 2006.196.07:40:12.30#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.196.07:40:12.30#ibcon#[28=FRQ=06,752.99\r\n] 2006.196.07:40:12.30#ibcon#*before write, iclass 33, count 0 2006.196.07:40:12.30#ibcon#enter sib2, iclass 33, count 0 2006.196.07:40:12.30#ibcon#flushed, iclass 33, count 0 2006.196.07:40:12.30#ibcon#about to write, iclass 33, count 0 2006.196.07:40:12.30#ibcon#wrote, iclass 33, count 0 2006.196.07:40:12.30#ibcon#about to read 3, iclass 33, count 0 2006.196.07:40:12.34#ibcon#read 3, iclass 33, count 0 2006.196.07:40:12.34#ibcon#about to read 4, iclass 33, count 0 2006.196.07:40:12.34#ibcon#read 4, iclass 33, count 0 2006.196.07:40:12.34#ibcon#about to read 5, iclass 33, count 0 2006.196.07:40:12.34#ibcon#read 5, iclass 33, count 0 2006.196.07:40:12.34#ibcon#about to read 6, iclass 33, count 0 2006.196.07:40:12.34#ibcon#read 6, iclass 33, count 0 2006.196.07:40:12.34#ibcon#end of sib2, iclass 33, count 0 2006.196.07:40:12.34#ibcon#*after write, iclass 33, count 0 2006.196.07:40:12.34#ibcon#*before return 0, iclass 33, count 0 2006.196.07:40:12.34#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.196.07:40:12.34#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.196.07:40:12.34#ibcon#about to clear, iclass 33 cls_cnt 0 2006.196.07:40:12.34#ibcon#cleared, iclass 33 cls_cnt 0 2006.196.07:40:12.34$vc4f8/vb=6,4 2006.196.07:40:12.34#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.196.07:40:12.34#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.196.07:40:12.34#ibcon#ireg 11 cls_cnt 2 2006.196.07:40:12.34#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.196.07:40:12.40#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.196.07:40:12.40#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.196.07:40:12.40#ibcon#enter wrdev, iclass 35, count 2 2006.196.07:40:12.40#ibcon#first serial, iclass 35, count 2 2006.196.07:40:12.40#ibcon#enter sib2, iclass 35, count 2 2006.196.07:40:12.40#ibcon#flushed, iclass 35, count 2 2006.196.07:40:12.40#ibcon#about to write, iclass 35, count 2 2006.196.07:40:12.40#ibcon#wrote, iclass 35, count 2 2006.196.07:40:12.40#ibcon#about to read 3, iclass 35, count 2 2006.196.07:40:12.42#ibcon#read 3, iclass 35, count 2 2006.196.07:40:12.42#ibcon#about to read 4, iclass 35, count 2 2006.196.07:40:12.42#ibcon#read 4, iclass 35, count 2 2006.196.07:40:12.42#ibcon#about to read 5, iclass 35, count 2 2006.196.07:40:12.42#ibcon#read 5, iclass 35, count 2 2006.196.07:40:12.42#ibcon#about to read 6, iclass 35, count 2 2006.196.07:40:12.42#ibcon#read 6, iclass 35, count 2 2006.196.07:40:12.42#ibcon#end of sib2, iclass 35, count 2 2006.196.07:40:12.42#ibcon#*mode == 0, iclass 35, count 2 2006.196.07:40:12.42#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.196.07:40:12.42#ibcon#[27=AT06-04\r\n] 2006.196.07:40:12.42#ibcon#*before write, iclass 35, count 2 2006.196.07:40:12.42#ibcon#enter sib2, iclass 35, count 2 2006.196.07:40:12.42#ibcon#flushed, iclass 35, count 2 2006.196.07:40:12.42#ibcon#about to write, iclass 35, count 2 2006.196.07:40:12.42#ibcon#wrote, iclass 35, count 2 2006.196.07:40:12.42#ibcon#about to read 3, iclass 35, count 2 2006.196.07:40:12.45#ibcon#read 3, iclass 35, count 2 2006.196.07:40:12.45#ibcon#about to read 4, iclass 35, count 2 2006.196.07:40:12.45#ibcon#read 4, iclass 35, count 2 2006.196.07:40:12.45#ibcon#about to read 5, iclass 35, count 2 2006.196.07:40:12.45#ibcon#read 5, iclass 35, count 2 2006.196.07:40:12.45#ibcon#about to read 6, iclass 35, count 2 2006.196.07:40:12.45#ibcon#read 6, iclass 35, count 2 2006.196.07:40:12.45#ibcon#end of sib2, iclass 35, count 2 2006.196.07:40:12.45#ibcon#*after write, iclass 35, count 2 2006.196.07:40:12.45#ibcon#*before return 0, iclass 35, count 2 2006.196.07:40:12.45#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.196.07:40:12.45#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.196.07:40:12.45#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.196.07:40:12.45#ibcon#ireg 7 cls_cnt 0 2006.196.07:40:12.45#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.196.07:40:12.57#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.196.07:40:12.57#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.196.07:40:12.57#ibcon#enter wrdev, iclass 35, count 0 2006.196.07:40:12.57#ibcon#first serial, iclass 35, count 0 2006.196.07:40:12.57#ibcon#enter sib2, iclass 35, count 0 2006.196.07:40:12.57#ibcon#flushed, iclass 35, count 0 2006.196.07:40:12.57#ibcon#about to write, iclass 35, count 0 2006.196.07:40:12.57#ibcon#wrote, iclass 35, count 0 2006.196.07:40:12.57#ibcon#about to read 3, iclass 35, count 0 2006.196.07:40:12.59#ibcon#read 3, iclass 35, count 0 2006.196.07:40:12.59#ibcon#about to read 4, iclass 35, count 0 2006.196.07:40:12.59#ibcon#read 4, iclass 35, count 0 2006.196.07:40:12.59#ibcon#about to read 5, iclass 35, count 0 2006.196.07:40:12.59#ibcon#read 5, iclass 35, count 0 2006.196.07:40:12.59#ibcon#about to read 6, iclass 35, count 0 2006.196.07:40:12.59#ibcon#read 6, iclass 35, count 0 2006.196.07:40:12.59#ibcon#end of sib2, iclass 35, count 0 2006.196.07:40:12.59#ibcon#*mode == 0, iclass 35, count 0 2006.196.07:40:12.59#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.196.07:40:12.59#ibcon#[27=USB\r\n] 2006.196.07:40:12.59#ibcon#*before write, iclass 35, count 0 2006.196.07:40:12.59#ibcon#enter sib2, iclass 35, count 0 2006.196.07:40:12.59#ibcon#flushed, iclass 35, count 0 2006.196.07:40:12.59#ibcon#about to write, iclass 35, count 0 2006.196.07:40:12.59#ibcon#wrote, iclass 35, count 0 2006.196.07:40:12.59#ibcon#about to read 3, iclass 35, count 0 2006.196.07:40:12.62#ibcon#read 3, iclass 35, count 0 2006.196.07:40:12.62#ibcon#about to read 4, iclass 35, count 0 2006.196.07:40:12.62#ibcon#read 4, iclass 35, count 0 2006.196.07:40:12.62#ibcon#about to read 5, iclass 35, count 0 2006.196.07:40:12.62#ibcon#read 5, iclass 35, count 0 2006.196.07:40:12.62#ibcon#about to read 6, iclass 35, count 0 2006.196.07:40:12.62#ibcon#read 6, iclass 35, count 0 2006.196.07:40:12.62#ibcon#end of sib2, iclass 35, count 0 2006.196.07:40:12.62#ibcon#*after write, iclass 35, count 0 2006.196.07:40:12.62#ibcon#*before return 0, iclass 35, count 0 2006.196.07:40:12.62#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.196.07:40:12.62#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.196.07:40:12.62#ibcon#about to clear, iclass 35 cls_cnt 0 2006.196.07:40:12.62#ibcon#cleared, iclass 35 cls_cnt 0 2006.196.07:40:12.62$vc4f8/vabw=wide 2006.196.07:40:12.62#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.196.07:40:12.62#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.196.07:40:12.62#ibcon#ireg 8 cls_cnt 0 2006.196.07:40:12.62#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.196.07:40:12.62#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.196.07:40:12.62#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.196.07:40:12.62#ibcon#enter wrdev, iclass 37, count 0 2006.196.07:40:12.62#ibcon#first serial, iclass 37, count 0 2006.196.07:40:12.62#ibcon#enter sib2, iclass 37, count 0 2006.196.07:40:12.62#ibcon#flushed, iclass 37, count 0 2006.196.07:40:12.62#ibcon#about to write, iclass 37, count 0 2006.196.07:40:12.62#ibcon#wrote, iclass 37, count 0 2006.196.07:40:12.62#ibcon#about to read 3, iclass 37, count 0 2006.196.07:40:12.64#ibcon#read 3, iclass 37, count 0 2006.196.07:40:12.64#ibcon#about to read 4, iclass 37, count 0 2006.196.07:40:12.64#ibcon#read 4, iclass 37, count 0 2006.196.07:40:12.64#ibcon#about to read 5, iclass 37, count 0 2006.196.07:40:12.64#ibcon#read 5, iclass 37, count 0 2006.196.07:40:12.64#ibcon#about to read 6, iclass 37, count 0 2006.196.07:40:12.64#ibcon#read 6, iclass 37, count 0 2006.196.07:40:12.64#ibcon#end of sib2, iclass 37, count 0 2006.196.07:40:12.64#ibcon#*mode == 0, iclass 37, count 0 2006.196.07:40:12.64#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.196.07:40:12.64#ibcon#[25=BW32\r\n] 2006.196.07:40:12.64#ibcon#*before write, iclass 37, count 0 2006.196.07:40:12.64#ibcon#enter sib2, iclass 37, count 0 2006.196.07:40:12.64#ibcon#flushed, iclass 37, count 0 2006.196.07:40:12.64#ibcon#about to write, iclass 37, count 0 2006.196.07:40:12.64#ibcon#wrote, iclass 37, count 0 2006.196.07:40:12.64#ibcon#about to read 3, iclass 37, count 0 2006.196.07:40:12.68#ibcon#read 3, iclass 37, count 0 2006.196.07:40:12.68#ibcon#about to read 4, iclass 37, count 0 2006.196.07:40:12.68#ibcon#read 4, iclass 37, count 0 2006.196.07:40:12.68#ibcon#about to read 5, iclass 37, count 0 2006.196.07:40:12.68#ibcon#read 5, iclass 37, count 0 2006.196.07:40:12.68#ibcon#about to read 6, iclass 37, count 0 2006.196.07:40:12.68#ibcon#read 6, iclass 37, count 0 2006.196.07:40:12.68#ibcon#end of sib2, iclass 37, count 0 2006.196.07:40:12.68#ibcon#*after write, iclass 37, count 0 2006.196.07:40:12.68#ibcon#*before return 0, iclass 37, count 0 2006.196.07:40:12.68#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.196.07:40:12.68#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.196.07:40:12.68#ibcon#about to clear, iclass 37 cls_cnt 0 2006.196.07:40:12.68#ibcon#cleared, iclass 37 cls_cnt 0 2006.196.07:40:12.68$vc4f8/vbbw=wide 2006.196.07:40:12.68#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.196.07:40:12.68#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.196.07:40:12.68#ibcon#ireg 8 cls_cnt 0 2006.196.07:40:12.68#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.196.07:40:12.74#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.196.07:40:12.74#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.196.07:40:12.74#ibcon#enter wrdev, iclass 39, count 0 2006.196.07:40:12.74#ibcon#first serial, iclass 39, count 0 2006.196.07:40:12.74#ibcon#enter sib2, iclass 39, count 0 2006.196.07:40:12.74#ibcon#flushed, iclass 39, count 0 2006.196.07:40:12.74#ibcon#about to write, iclass 39, count 0 2006.196.07:40:12.74#ibcon#wrote, iclass 39, count 0 2006.196.07:40:12.74#ibcon#about to read 3, iclass 39, count 0 2006.196.07:40:12.76#ibcon#read 3, iclass 39, count 0 2006.196.07:40:12.76#ibcon#about to read 4, iclass 39, count 0 2006.196.07:40:12.76#ibcon#read 4, iclass 39, count 0 2006.196.07:40:12.76#ibcon#about to read 5, iclass 39, count 0 2006.196.07:40:12.76#ibcon#read 5, iclass 39, count 0 2006.196.07:40:12.76#ibcon#about to read 6, iclass 39, count 0 2006.196.07:40:12.76#ibcon#read 6, iclass 39, count 0 2006.196.07:40:12.76#ibcon#end of sib2, iclass 39, count 0 2006.196.07:40:12.76#ibcon#*mode == 0, iclass 39, count 0 2006.196.07:40:12.76#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.196.07:40:12.76#ibcon#[27=BW32\r\n] 2006.196.07:40:12.76#ibcon#*before write, iclass 39, count 0 2006.196.07:40:12.76#ibcon#enter sib2, iclass 39, count 0 2006.196.07:40:12.76#ibcon#flushed, iclass 39, count 0 2006.196.07:40:12.76#ibcon#about to write, iclass 39, count 0 2006.196.07:40:12.76#ibcon#wrote, iclass 39, count 0 2006.196.07:40:12.76#ibcon#about to read 3, iclass 39, count 0 2006.196.07:40:12.79#ibcon#read 3, iclass 39, count 0 2006.196.07:40:12.79#ibcon#about to read 4, iclass 39, count 0 2006.196.07:40:12.79#ibcon#read 4, iclass 39, count 0 2006.196.07:40:12.79#ibcon#about to read 5, iclass 39, count 0 2006.196.07:40:12.79#ibcon#read 5, iclass 39, count 0 2006.196.07:40:12.79#ibcon#about to read 6, iclass 39, count 0 2006.196.07:40:12.79#ibcon#read 6, iclass 39, count 0 2006.196.07:40:12.79#ibcon#end of sib2, iclass 39, count 0 2006.196.07:40:12.79#ibcon#*after write, iclass 39, count 0 2006.196.07:40:12.79#ibcon#*before return 0, iclass 39, count 0 2006.196.07:40:12.79#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.196.07:40:12.79#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.196.07:40:12.79#ibcon#about to clear, iclass 39 cls_cnt 0 2006.196.07:40:12.79#ibcon#cleared, iclass 39 cls_cnt 0 2006.196.07:40:12.79$4f8m12a/ifd4f 2006.196.07:40:12.79$ifd4f/lo= 2006.196.07:40:12.79$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.196.07:40:12.79$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.196.07:40:12.79$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.196.07:40:12.79$ifd4f/patch= 2006.196.07:40:12.79$ifd4f/patch=lo1,a1,a2,a3,a4 2006.196.07:40:12.79$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.196.07:40:12.79$ifd4f/patch=lo3,a5,a6,a7,a8 2006.196.07:40:12.79$4f8m12a/"form=m,16.000,1:2 2006.196.07:40:12.79$4f8m12a/"tpicd 2006.196.07:40:12.79$4f8m12a/echo=off 2006.196.07:40:12.79$4f8m12a/xlog=off 2006.196.07:40:12.79:!2006.196.07:40:40 2006.196.07:40:24.14#trakl#Source acquired 2006.196.07:40:25.13#flagr#flagr/antenna,acquired 2006.196.07:40:40.00:preob 2006.196.07:40:41.13/onsource/TRACKING 2006.196.07:40:41.13:!2006.196.07:40:50 2006.196.07:40:50.00:data_valid=on 2006.196.07:40:50.00:midob 2006.196.07:40:50.14/onsource/TRACKING 2006.196.07:40:50.14/wx/29.95,1004.0,86 2006.196.07:40:50.21/cable/+6.3327E-03 2006.196.07:40:51.30/va/01,08,usb,yes,29,31 2006.196.07:40:51.30/va/02,07,usb,yes,29,31 2006.196.07:40:51.30/va/03,06,usb,yes,31,31 2006.196.07:40:51.30/va/04,07,usb,yes,30,32 2006.196.07:40:51.30/va/05,07,usb,yes,31,33 2006.196.07:40:51.30/va/06,06,usb,yes,31,30 2006.196.07:40:51.30/va/07,06,usb,yes,31,31 2006.196.07:40:51.30/va/08,07,usb,yes,29,29 2006.196.07:40:51.53/valo/01,532.99,yes,locked 2006.196.07:40:51.53/valo/02,572.99,yes,locked 2006.196.07:40:51.53/valo/03,672.99,yes,locked 2006.196.07:40:51.53/valo/04,832.99,yes,locked 2006.196.07:40:51.53/valo/05,652.99,yes,locked 2006.196.07:40:51.53/valo/06,772.99,yes,locked 2006.196.07:40:51.53/valo/07,832.99,yes,locked 2006.196.07:40:51.53/valo/08,852.99,yes,locked 2006.196.07:40:52.62/vb/01,04,usb,yes,28,27 2006.196.07:40:52.62/vb/02,04,usb,yes,30,32 2006.196.07:40:52.62/vb/03,04,usb,yes,27,30 2006.196.07:40:52.62/vb/04,04,usb,yes,28,28 2006.196.07:40:52.62/vb/05,04,usb,yes,26,30 2006.196.07:40:52.62/vb/06,04,usb,yes,27,30 2006.196.07:40:52.62/vb/07,04,usb,yes,29,29 2006.196.07:40:52.62/vb/08,04,usb,yes,27,30 2006.196.07:40:52.85/vblo/01,632.99,yes,locked 2006.196.07:40:52.85/vblo/02,640.99,yes,locked 2006.196.07:40:52.85/vblo/03,656.99,yes,locked 2006.196.07:40:52.85/vblo/04,712.99,yes,locked 2006.196.07:40:52.85/vblo/05,744.99,yes,locked 2006.196.07:40:52.85/vblo/06,752.99,yes,locked 2006.196.07:40:52.85/vblo/07,734.99,yes,locked 2006.196.07:40:52.85/vblo/08,744.99,yes,locked 2006.196.07:40:53.00/vabw/8 2006.196.07:40:53.15/vbbw/8 2006.196.07:40:53.27/xfe/off,on,15.2 2006.196.07:40:53.64/ifatt/23,28,28,28 2006.196.07:40:54.06/fmout-gps/S +3.34E-07 2006.196.07:40:54.13:!2006.196.07:41:50 2006.196.07:41:50.00:data_valid=off 2006.196.07:41:50.00:postob 2006.196.07:41:50.15/cable/+6.3334E-03 2006.196.07:41:50.15/wx/29.91,1004.0,87 2006.196.07:41:51.06/fmout-gps/S +3.35E-07 2006.196.07:41:51.06:scan_name=196-0743,k06196,170 2006.196.07:41:51.06:source=0808+019,081126.71,014652.2,2000.0,ccw 2006.196.07:41:51.13#flagr#flagr/antenna,new-source 2006.196.07:41:52.13:checkk5 2006.196.07:41:52.50/chk_autoobs//k5ts1/ autoobs is running! 2006.196.07:41:52.86/chk_autoobs//k5ts2/ autoobs is running! 2006.196.07:41:53.23/chk_autoobs//k5ts3/ autoobs is running! 2006.196.07:41:53.60/chk_autoobs//k5ts4/ autoobs is running! 2006.196.07:41:53.97/chk_obsdata//k5ts1/T1960740??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.07:41:54.34/chk_obsdata//k5ts2/T1960740??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.07:41:54.71/chk_obsdata//k5ts3/T1960740??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.07:41:55.08/chk_obsdata//k5ts4/T1960740??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.07:41:55.77/k5log//k5ts1_log_newline 2006.196.07:41:56.47/k5log//k5ts2_log_newline 2006.196.07:41:57.16/k5log//k5ts3_log_newline 2006.196.07:41:57.86/k5log//k5ts4_log_newline 2006.196.07:41:57.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.196.07:41:57.88:4f8m12a=1 2006.196.07:41:57.88$4f8m12a/echo=on 2006.196.07:41:57.88$4f8m12a/pcalon 2006.196.07:41:57.88$pcalon/"no phase cal control is implemented here 2006.196.07:41:57.88$4f8m12a/"tpicd=stop 2006.196.07:41:57.88$4f8m12a/vc4f8 2006.196.07:41:57.88$vc4f8/valo=1,532.99 2006.196.07:41:57.89#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.196.07:41:57.89#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.196.07:41:57.89#ibcon#ireg 17 cls_cnt 0 2006.196.07:41:57.89#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.196.07:41:57.89#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.196.07:41:57.89#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.196.07:41:57.89#ibcon#enter wrdev, iclass 14, count 0 2006.196.07:41:57.89#ibcon#first serial, iclass 14, count 0 2006.196.07:41:57.89#ibcon#enter sib2, iclass 14, count 0 2006.196.07:41:57.89#ibcon#flushed, iclass 14, count 0 2006.196.07:41:57.89#ibcon#about to write, iclass 14, count 0 2006.196.07:41:57.89#ibcon#wrote, iclass 14, count 0 2006.196.07:41:57.89#ibcon#about to read 3, iclass 14, count 0 2006.196.07:41:57.93#ibcon#read 3, iclass 14, count 0 2006.196.07:41:57.93#ibcon#about to read 4, iclass 14, count 0 2006.196.07:41:57.93#ibcon#read 4, iclass 14, count 0 2006.196.07:41:57.93#ibcon#about to read 5, iclass 14, count 0 2006.196.07:41:57.93#ibcon#read 5, iclass 14, count 0 2006.196.07:41:57.93#ibcon#about to read 6, iclass 14, count 0 2006.196.07:41:57.93#ibcon#read 6, iclass 14, count 0 2006.196.07:41:57.93#ibcon#end of sib2, iclass 14, count 0 2006.196.07:41:57.93#ibcon#*mode == 0, iclass 14, count 0 2006.196.07:41:57.93#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.196.07:41:57.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.196.07:41:57.93#ibcon#*before write, iclass 14, count 0 2006.196.07:41:57.93#ibcon#enter sib2, iclass 14, count 0 2006.196.07:41:57.93#ibcon#flushed, iclass 14, count 0 2006.196.07:41:57.93#ibcon#about to write, iclass 14, count 0 2006.196.07:41:57.93#ibcon#wrote, iclass 14, count 0 2006.196.07:41:57.93#ibcon#about to read 3, iclass 14, count 0 2006.196.07:41:57.98#ibcon#read 3, iclass 14, count 0 2006.196.07:41:57.98#ibcon#about to read 4, iclass 14, count 0 2006.196.07:41:57.98#ibcon#read 4, iclass 14, count 0 2006.196.07:41:57.98#ibcon#about to read 5, iclass 14, count 0 2006.196.07:41:57.98#ibcon#read 5, iclass 14, count 0 2006.196.07:41:57.98#ibcon#about to read 6, iclass 14, count 0 2006.196.07:41:57.98#ibcon#read 6, iclass 14, count 0 2006.196.07:41:57.98#ibcon#end of sib2, iclass 14, count 0 2006.196.07:41:57.98#ibcon#*after write, iclass 14, count 0 2006.196.07:41:57.98#ibcon#*before return 0, iclass 14, count 0 2006.196.07:41:57.98#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.196.07:41:57.98#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.196.07:41:57.98#ibcon#about to clear, iclass 14 cls_cnt 0 2006.196.07:41:57.98#ibcon#cleared, iclass 14 cls_cnt 0 2006.196.07:41:57.98$vc4f8/va=1,8 2006.196.07:41:57.98#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.196.07:41:57.98#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.196.07:41:57.98#ibcon#ireg 11 cls_cnt 2 2006.196.07:41:57.98#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.196.07:41:57.98#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.196.07:41:57.98#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.196.07:41:57.98#ibcon#enter wrdev, iclass 16, count 2 2006.196.07:41:57.98#ibcon#first serial, iclass 16, count 2 2006.196.07:41:57.98#ibcon#enter sib2, iclass 16, count 2 2006.196.07:41:57.98#ibcon#flushed, iclass 16, count 2 2006.196.07:41:57.98#ibcon#about to write, iclass 16, count 2 2006.196.07:41:57.98#ibcon#wrote, iclass 16, count 2 2006.196.07:41:57.98#ibcon#about to read 3, iclass 16, count 2 2006.196.07:41:58.00#ibcon#read 3, iclass 16, count 2 2006.196.07:41:58.00#ibcon#about to read 4, iclass 16, count 2 2006.196.07:41:58.00#ibcon#read 4, iclass 16, count 2 2006.196.07:41:58.00#ibcon#about to read 5, iclass 16, count 2 2006.196.07:41:58.00#ibcon#read 5, iclass 16, count 2 2006.196.07:41:58.00#ibcon#about to read 6, iclass 16, count 2 2006.196.07:41:58.00#ibcon#read 6, iclass 16, count 2 2006.196.07:41:58.00#ibcon#end of sib2, iclass 16, count 2 2006.196.07:41:58.00#ibcon#*mode == 0, iclass 16, count 2 2006.196.07:41:58.00#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.196.07:41:58.00#ibcon#[25=AT01-08\r\n] 2006.196.07:41:58.00#ibcon#*before write, iclass 16, count 2 2006.196.07:41:58.00#ibcon#enter sib2, iclass 16, count 2 2006.196.07:41:58.00#ibcon#flushed, iclass 16, count 2 2006.196.07:41:58.00#ibcon#about to write, iclass 16, count 2 2006.196.07:41:58.00#ibcon#wrote, iclass 16, count 2 2006.196.07:41:58.00#ibcon#about to read 3, iclass 16, count 2 2006.196.07:41:58.03#ibcon#read 3, iclass 16, count 2 2006.196.07:41:58.03#ibcon#about to read 4, iclass 16, count 2 2006.196.07:41:58.03#ibcon#read 4, iclass 16, count 2 2006.196.07:41:58.03#ibcon#about to read 5, iclass 16, count 2 2006.196.07:41:58.03#ibcon#read 5, iclass 16, count 2 2006.196.07:41:58.03#ibcon#about to read 6, iclass 16, count 2 2006.196.07:41:58.03#ibcon#read 6, iclass 16, count 2 2006.196.07:41:58.03#ibcon#end of sib2, iclass 16, count 2 2006.196.07:41:58.03#ibcon#*after write, iclass 16, count 2 2006.196.07:41:58.03#ibcon#*before return 0, iclass 16, count 2 2006.196.07:41:58.03#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.196.07:41:58.03#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.196.07:41:58.03#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.196.07:41:58.03#ibcon#ireg 7 cls_cnt 0 2006.196.07:41:58.03#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.196.07:41:58.15#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.196.07:41:58.15#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.196.07:41:58.15#ibcon#enter wrdev, iclass 16, count 0 2006.196.07:41:58.15#ibcon#first serial, iclass 16, count 0 2006.196.07:41:58.15#ibcon#enter sib2, iclass 16, count 0 2006.196.07:41:58.15#ibcon#flushed, iclass 16, count 0 2006.196.07:41:58.15#ibcon#about to write, iclass 16, count 0 2006.196.07:41:58.15#ibcon#wrote, iclass 16, count 0 2006.196.07:41:58.15#ibcon#about to read 3, iclass 16, count 0 2006.196.07:41:58.17#ibcon#read 3, iclass 16, count 0 2006.196.07:41:58.17#ibcon#about to read 4, iclass 16, count 0 2006.196.07:41:58.17#ibcon#read 4, iclass 16, count 0 2006.196.07:41:58.17#ibcon#about to read 5, iclass 16, count 0 2006.196.07:41:58.17#ibcon#read 5, iclass 16, count 0 2006.196.07:41:58.17#ibcon#about to read 6, iclass 16, count 0 2006.196.07:41:58.17#ibcon#read 6, iclass 16, count 0 2006.196.07:41:58.17#ibcon#end of sib2, iclass 16, count 0 2006.196.07:41:58.17#ibcon#*mode == 0, iclass 16, count 0 2006.196.07:41:58.17#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.196.07:41:58.17#ibcon#[25=USB\r\n] 2006.196.07:41:58.17#ibcon#*before write, iclass 16, count 0 2006.196.07:41:58.17#ibcon#enter sib2, iclass 16, count 0 2006.196.07:41:58.17#ibcon#flushed, iclass 16, count 0 2006.196.07:41:58.17#ibcon#about to write, iclass 16, count 0 2006.196.07:41:58.17#ibcon#wrote, iclass 16, count 0 2006.196.07:41:58.17#ibcon#about to read 3, iclass 16, count 0 2006.196.07:41:58.20#ibcon#read 3, iclass 16, count 0 2006.196.07:41:58.20#ibcon#about to read 4, iclass 16, count 0 2006.196.07:41:58.20#ibcon#read 4, iclass 16, count 0 2006.196.07:41:58.20#ibcon#about to read 5, iclass 16, count 0 2006.196.07:41:58.20#ibcon#read 5, iclass 16, count 0 2006.196.07:41:58.20#ibcon#about to read 6, iclass 16, count 0 2006.196.07:41:58.20#ibcon#read 6, iclass 16, count 0 2006.196.07:41:58.20#ibcon#end of sib2, iclass 16, count 0 2006.196.07:41:58.20#ibcon#*after write, iclass 16, count 0 2006.196.07:41:58.20#ibcon#*before return 0, iclass 16, count 0 2006.196.07:41:58.20#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.196.07:41:58.20#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.196.07:41:58.20#ibcon#about to clear, iclass 16 cls_cnt 0 2006.196.07:41:58.20#ibcon#cleared, iclass 16 cls_cnt 0 2006.196.07:41:58.20$vc4f8/valo=2,572.99 2006.196.07:41:58.20#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.196.07:41:58.20#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.196.07:41:58.20#ibcon#ireg 17 cls_cnt 0 2006.196.07:41:58.20#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.196.07:41:58.20#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.196.07:41:58.20#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.196.07:41:58.20#ibcon#enter wrdev, iclass 18, count 0 2006.196.07:41:58.20#ibcon#first serial, iclass 18, count 0 2006.196.07:41:58.20#ibcon#enter sib2, iclass 18, count 0 2006.196.07:41:58.20#ibcon#flushed, iclass 18, count 0 2006.196.07:41:58.20#ibcon#about to write, iclass 18, count 0 2006.196.07:41:58.20#ibcon#wrote, iclass 18, count 0 2006.196.07:41:58.20#ibcon#about to read 3, iclass 18, count 0 2006.196.07:41:58.22#ibcon#read 3, iclass 18, count 0 2006.196.07:41:58.22#ibcon#about to read 4, iclass 18, count 0 2006.196.07:41:58.22#ibcon#read 4, iclass 18, count 0 2006.196.07:41:58.22#ibcon#about to read 5, iclass 18, count 0 2006.196.07:41:58.22#ibcon#read 5, iclass 18, count 0 2006.196.07:41:58.22#ibcon#about to read 6, iclass 18, count 0 2006.196.07:41:58.22#ibcon#read 6, iclass 18, count 0 2006.196.07:41:58.22#ibcon#end of sib2, iclass 18, count 0 2006.196.07:41:58.22#ibcon#*mode == 0, iclass 18, count 0 2006.196.07:41:58.22#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.196.07:41:58.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.196.07:41:58.22#ibcon#*before write, iclass 18, count 0 2006.196.07:41:58.22#ibcon#enter sib2, iclass 18, count 0 2006.196.07:41:58.22#ibcon#flushed, iclass 18, count 0 2006.196.07:41:58.22#ibcon#about to write, iclass 18, count 0 2006.196.07:41:58.22#ibcon#wrote, iclass 18, count 0 2006.196.07:41:58.22#ibcon#about to read 3, iclass 18, count 0 2006.196.07:41:58.26#ibcon#read 3, iclass 18, count 0 2006.196.07:41:58.26#ibcon#about to read 4, iclass 18, count 0 2006.196.07:41:58.26#ibcon#read 4, iclass 18, count 0 2006.196.07:41:58.26#ibcon#about to read 5, iclass 18, count 0 2006.196.07:41:58.26#ibcon#read 5, iclass 18, count 0 2006.196.07:41:58.26#ibcon#about to read 6, iclass 18, count 0 2006.196.07:41:58.26#ibcon#read 6, iclass 18, count 0 2006.196.07:41:58.26#ibcon#end of sib2, iclass 18, count 0 2006.196.07:41:58.26#ibcon#*after write, iclass 18, count 0 2006.196.07:41:58.26#ibcon#*before return 0, iclass 18, count 0 2006.196.07:41:58.26#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.196.07:41:58.26#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.196.07:41:58.26#ibcon#about to clear, iclass 18 cls_cnt 0 2006.196.07:41:58.26#ibcon#cleared, iclass 18 cls_cnt 0 2006.196.07:41:58.26$vc4f8/va=2,7 2006.196.07:41:58.26#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.196.07:41:58.26#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.196.07:41:58.26#ibcon#ireg 11 cls_cnt 2 2006.196.07:41:58.26#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.196.07:41:58.32#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.196.07:41:58.32#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.196.07:41:58.32#ibcon#enter wrdev, iclass 20, count 2 2006.196.07:41:58.32#ibcon#first serial, iclass 20, count 2 2006.196.07:41:58.32#ibcon#enter sib2, iclass 20, count 2 2006.196.07:41:58.32#ibcon#flushed, iclass 20, count 2 2006.196.07:41:58.32#ibcon#about to write, iclass 20, count 2 2006.196.07:41:58.32#ibcon#wrote, iclass 20, count 2 2006.196.07:41:58.32#ibcon#about to read 3, iclass 20, count 2 2006.196.07:41:58.34#ibcon#read 3, iclass 20, count 2 2006.196.07:41:58.34#ibcon#about to read 4, iclass 20, count 2 2006.196.07:41:58.34#ibcon#read 4, iclass 20, count 2 2006.196.07:41:58.34#ibcon#about to read 5, iclass 20, count 2 2006.196.07:41:58.34#ibcon#read 5, iclass 20, count 2 2006.196.07:41:58.34#ibcon#about to read 6, iclass 20, count 2 2006.196.07:41:58.34#ibcon#read 6, iclass 20, count 2 2006.196.07:41:58.34#ibcon#end of sib2, iclass 20, count 2 2006.196.07:41:58.34#ibcon#*mode == 0, iclass 20, count 2 2006.196.07:41:58.34#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.196.07:41:58.34#ibcon#[25=AT02-07\r\n] 2006.196.07:41:58.34#ibcon#*before write, iclass 20, count 2 2006.196.07:41:58.34#ibcon#enter sib2, iclass 20, count 2 2006.196.07:41:58.34#ibcon#flushed, iclass 20, count 2 2006.196.07:41:58.34#ibcon#about to write, iclass 20, count 2 2006.196.07:41:58.34#ibcon#wrote, iclass 20, count 2 2006.196.07:41:58.34#ibcon#about to read 3, iclass 20, count 2 2006.196.07:41:58.37#ibcon#read 3, iclass 20, count 2 2006.196.07:41:58.37#ibcon#about to read 4, iclass 20, count 2 2006.196.07:41:58.37#ibcon#read 4, iclass 20, count 2 2006.196.07:41:58.37#ibcon#about to read 5, iclass 20, count 2 2006.196.07:41:58.37#ibcon#read 5, iclass 20, count 2 2006.196.07:41:58.37#ibcon#about to read 6, iclass 20, count 2 2006.196.07:41:58.37#ibcon#read 6, iclass 20, count 2 2006.196.07:41:58.37#ibcon#end of sib2, iclass 20, count 2 2006.196.07:41:58.37#ibcon#*after write, iclass 20, count 2 2006.196.07:41:58.37#ibcon#*before return 0, iclass 20, count 2 2006.196.07:41:58.37#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.196.07:41:58.37#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.196.07:41:58.37#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.196.07:41:58.37#ibcon#ireg 7 cls_cnt 0 2006.196.07:41:58.37#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.196.07:41:58.49#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.196.07:41:58.49#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.196.07:41:58.49#ibcon#enter wrdev, iclass 20, count 0 2006.196.07:41:58.49#ibcon#first serial, iclass 20, count 0 2006.196.07:41:58.49#ibcon#enter sib2, iclass 20, count 0 2006.196.07:41:58.49#ibcon#flushed, iclass 20, count 0 2006.196.07:41:58.49#ibcon#about to write, iclass 20, count 0 2006.196.07:41:58.49#ibcon#wrote, iclass 20, count 0 2006.196.07:41:58.49#ibcon#about to read 3, iclass 20, count 0 2006.196.07:41:58.51#ibcon#read 3, iclass 20, count 0 2006.196.07:41:58.51#ibcon#about to read 4, iclass 20, count 0 2006.196.07:41:58.51#ibcon#read 4, iclass 20, count 0 2006.196.07:41:58.51#ibcon#about to read 5, iclass 20, count 0 2006.196.07:41:58.51#ibcon#read 5, iclass 20, count 0 2006.196.07:41:58.51#ibcon#about to read 6, iclass 20, count 0 2006.196.07:41:58.51#ibcon#read 6, iclass 20, count 0 2006.196.07:41:58.51#ibcon#end of sib2, iclass 20, count 0 2006.196.07:41:58.51#ibcon#*mode == 0, iclass 20, count 0 2006.196.07:41:58.51#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.196.07:41:58.51#ibcon#[25=USB\r\n] 2006.196.07:41:58.51#ibcon#*before write, iclass 20, count 0 2006.196.07:41:58.51#ibcon#enter sib2, iclass 20, count 0 2006.196.07:41:58.51#ibcon#flushed, iclass 20, count 0 2006.196.07:41:58.51#ibcon#about to write, iclass 20, count 0 2006.196.07:41:58.51#ibcon#wrote, iclass 20, count 0 2006.196.07:41:58.51#ibcon#about to read 3, iclass 20, count 0 2006.196.07:41:58.54#ibcon#read 3, iclass 20, count 0 2006.196.07:41:58.54#ibcon#about to read 4, iclass 20, count 0 2006.196.07:41:58.54#ibcon#read 4, iclass 20, count 0 2006.196.07:41:58.54#ibcon#about to read 5, iclass 20, count 0 2006.196.07:41:58.54#ibcon#read 5, iclass 20, count 0 2006.196.07:41:58.54#ibcon#about to read 6, iclass 20, count 0 2006.196.07:41:58.54#ibcon#read 6, iclass 20, count 0 2006.196.07:41:58.54#ibcon#end of sib2, iclass 20, count 0 2006.196.07:41:58.54#ibcon#*after write, iclass 20, count 0 2006.196.07:41:58.54#ibcon#*before return 0, iclass 20, count 0 2006.196.07:41:58.54#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.196.07:41:58.54#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.196.07:41:58.54#ibcon#about to clear, iclass 20 cls_cnt 0 2006.196.07:41:58.54#ibcon#cleared, iclass 20 cls_cnt 0 2006.196.07:41:58.54$vc4f8/valo=3,672.99 2006.196.07:41:58.54#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.196.07:41:58.54#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.196.07:41:58.54#ibcon#ireg 17 cls_cnt 0 2006.196.07:41:58.54#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.196.07:41:58.54#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.196.07:41:58.54#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.196.07:41:58.54#ibcon#enter wrdev, iclass 22, count 0 2006.196.07:41:58.54#ibcon#first serial, iclass 22, count 0 2006.196.07:41:58.54#ibcon#enter sib2, iclass 22, count 0 2006.196.07:41:58.54#ibcon#flushed, iclass 22, count 0 2006.196.07:41:58.54#ibcon#about to write, iclass 22, count 0 2006.196.07:41:58.54#ibcon#wrote, iclass 22, count 0 2006.196.07:41:58.54#ibcon#about to read 3, iclass 22, count 0 2006.196.07:41:58.56#ibcon#read 3, iclass 22, count 0 2006.196.07:41:58.56#ibcon#about to read 4, iclass 22, count 0 2006.196.07:41:58.56#ibcon#read 4, iclass 22, count 0 2006.196.07:41:58.56#ibcon#about to read 5, iclass 22, count 0 2006.196.07:41:58.56#ibcon#read 5, iclass 22, count 0 2006.196.07:41:58.56#ibcon#about to read 6, iclass 22, count 0 2006.196.07:41:58.56#ibcon#read 6, iclass 22, count 0 2006.196.07:41:58.56#ibcon#end of sib2, iclass 22, count 0 2006.196.07:41:58.56#ibcon#*mode == 0, iclass 22, count 0 2006.196.07:41:58.56#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.196.07:41:58.56#ibcon#[26=FRQ=03,672.99\r\n] 2006.196.07:41:58.56#ibcon#*before write, iclass 22, count 0 2006.196.07:41:58.56#ibcon#enter sib2, iclass 22, count 0 2006.196.07:41:58.56#ibcon#flushed, iclass 22, count 0 2006.196.07:41:58.56#ibcon#about to write, iclass 22, count 0 2006.196.07:41:58.56#ibcon#wrote, iclass 22, count 0 2006.196.07:41:58.56#ibcon#about to read 3, iclass 22, count 0 2006.196.07:41:58.60#ibcon#read 3, iclass 22, count 0 2006.196.07:41:58.60#ibcon#about to read 4, iclass 22, count 0 2006.196.07:41:58.60#ibcon#read 4, iclass 22, count 0 2006.196.07:41:58.60#ibcon#about to read 5, iclass 22, count 0 2006.196.07:41:58.60#ibcon#read 5, iclass 22, count 0 2006.196.07:41:58.60#ibcon#about to read 6, iclass 22, count 0 2006.196.07:41:58.60#ibcon#read 6, iclass 22, count 0 2006.196.07:41:58.60#ibcon#end of sib2, iclass 22, count 0 2006.196.07:41:58.60#ibcon#*after write, iclass 22, count 0 2006.196.07:41:58.60#ibcon#*before return 0, iclass 22, count 0 2006.196.07:41:58.60#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.196.07:41:58.60#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.196.07:41:58.60#ibcon#about to clear, iclass 22 cls_cnt 0 2006.196.07:41:58.60#ibcon#cleared, iclass 22 cls_cnt 0 2006.196.07:41:58.60$vc4f8/va=3,6 2006.196.07:41:58.60#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.196.07:41:58.60#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.196.07:41:58.60#ibcon#ireg 11 cls_cnt 2 2006.196.07:41:58.60#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.196.07:41:58.66#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.196.07:41:58.66#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.196.07:41:58.66#ibcon#enter wrdev, iclass 24, count 2 2006.196.07:41:58.66#ibcon#first serial, iclass 24, count 2 2006.196.07:41:58.66#ibcon#enter sib2, iclass 24, count 2 2006.196.07:41:58.66#ibcon#flushed, iclass 24, count 2 2006.196.07:41:58.66#ibcon#about to write, iclass 24, count 2 2006.196.07:41:58.66#ibcon#wrote, iclass 24, count 2 2006.196.07:41:58.66#ibcon#about to read 3, iclass 24, count 2 2006.196.07:41:58.68#ibcon#read 3, iclass 24, count 2 2006.196.07:41:58.68#ibcon#about to read 4, iclass 24, count 2 2006.196.07:41:58.68#ibcon#read 4, iclass 24, count 2 2006.196.07:41:58.68#ibcon#about to read 5, iclass 24, count 2 2006.196.07:41:58.68#ibcon#read 5, iclass 24, count 2 2006.196.07:41:58.68#ibcon#about to read 6, iclass 24, count 2 2006.196.07:41:58.68#ibcon#read 6, iclass 24, count 2 2006.196.07:41:58.68#ibcon#end of sib2, iclass 24, count 2 2006.196.07:41:58.68#ibcon#*mode == 0, iclass 24, count 2 2006.196.07:41:58.68#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.196.07:41:58.68#ibcon#[25=AT03-06\r\n] 2006.196.07:41:58.68#ibcon#*before write, iclass 24, count 2 2006.196.07:41:58.68#ibcon#enter sib2, iclass 24, count 2 2006.196.07:41:58.68#ibcon#flushed, iclass 24, count 2 2006.196.07:41:58.68#ibcon#about to write, iclass 24, count 2 2006.196.07:41:58.68#ibcon#wrote, iclass 24, count 2 2006.196.07:41:58.68#ibcon#about to read 3, iclass 24, count 2 2006.196.07:41:58.71#ibcon#read 3, iclass 24, count 2 2006.196.07:41:58.71#ibcon#about to read 4, iclass 24, count 2 2006.196.07:41:58.71#ibcon#read 4, iclass 24, count 2 2006.196.07:41:58.71#ibcon#about to read 5, iclass 24, count 2 2006.196.07:41:58.71#ibcon#read 5, iclass 24, count 2 2006.196.07:41:58.71#ibcon#about to read 6, iclass 24, count 2 2006.196.07:41:58.71#ibcon#read 6, iclass 24, count 2 2006.196.07:41:58.71#ibcon#end of sib2, iclass 24, count 2 2006.196.07:41:58.71#ibcon#*after write, iclass 24, count 2 2006.196.07:41:58.71#ibcon#*before return 0, iclass 24, count 2 2006.196.07:41:58.71#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.196.07:41:58.71#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.196.07:41:58.71#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.196.07:41:58.71#ibcon#ireg 7 cls_cnt 0 2006.196.07:41:58.71#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.196.07:41:58.83#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.196.07:41:58.83#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.196.07:41:58.83#ibcon#enter wrdev, iclass 24, count 0 2006.196.07:41:58.83#ibcon#first serial, iclass 24, count 0 2006.196.07:41:58.83#ibcon#enter sib2, iclass 24, count 0 2006.196.07:41:58.83#ibcon#flushed, iclass 24, count 0 2006.196.07:41:58.83#ibcon#about to write, iclass 24, count 0 2006.196.07:41:58.83#ibcon#wrote, iclass 24, count 0 2006.196.07:41:58.83#ibcon#about to read 3, iclass 24, count 0 2006.196.07:41:58.85#ibcon#read 3, iclass 24, count 0 2006.196.07:41:58.85#ibcon#about to read 4, iclass 24, count 0 2006.196.07:41:58.85#ibcon#read 4, iclass 24, count 0 2006.196.07:41:58.85#ibcon#about to read 5, iclass 24, count 0 2006.196.07:41:58.85#ibcon#read 5, iclass 24, count 0 2006.196.07:41:58.85#ibcon#about to read 6, iclass 24, count 0 2006.196.07:41:58.85#ibcon#read 6, iclass 24, count 0 2006.196.07:41:58.85#ibcon#end of sib2, iclass 24, count 0 2006.196.07:41:58.85#ibcon#*mode == 0, iclass 24, count 0 2006.196.07:41:58.85#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.196.07:41:58.85#ibcon#[25=USB\r\n] 2006.196.07:41:58.85#ibcon#*before write, iclass 24, count 0 2006.196.07:41:58.85#ibcon#enter sib2, iclass 24, count 0 2006.196.07:41:58.85#ibcon#flushed, iclass 24, count 0 2006.196.07:41:58.85#ibcon#about to write, iclass 24, count 0 2006.196.07:41:58.85#ibcon#wrote, iclass 24, count 0 2006.196.07:41:58.85#ibcon#about to read 3, iclass 24, count 0 2006.196.07:41:58.88#ibcon#read 3, iclass 24, count 0 2006.196.07:41:58.88#ibcon#about to read 4, iclass 24, count 0 2006.196.07:41:58.88#ibcon#read 4, iclass 24, count 0 2006.196.07:41:58.88#ibcon#about to read 5, iclass 24, count 0 2006.196.07:41:58.88#ibcon#read 5, iclass 24, count 0 2006.196.07:41:58.88#ibcon#about to read 6, iclass 24, count 0 2006.196.07:41:58.88#ibcon#read 6, iclass 24, count 0 2006.196.07:41:58.88#ibcon#end of sib2, iclass 24, count 0 2006.196.07:41:58.88#ibcon#*after write, iclass 24, count 0 2006.196.07:41:58.88#ibcon#*before return 0, iclass 24, count 0 2006.196.07:41:58.88#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.196.07:41:58.88#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.196.07:41:58.88#ibcon#about to clear, iclass 24 cls_cnt 0 2006.196.07:41:58.88#ibcon#cleared, iclass 24 cls_cnt 0 2006.196.07:41:58.88$vc4f8/valo=4,832.99 2006.196.07:41:58.88#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.196.07:41:58.88#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.196.07:41:58.88#ibcon#ireg 17 cls_cnt 0 2006.196.07:41:58.88#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.196.07:41:58.88#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.196.07:41:58.88#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.196.07:41:58.88#ibcon#enter wrdev, iclass 26, count 0 2006.196.07:41:58.88#ibcon#first serial, iclass 26, count 0 2006.196.07:41:58.88#ibcon#enter sib2, iclass 26, count 0 2006.196.07:41:58.88#ibcon#flushed, iclass 26, count 0 2006.196.07:41:58.88#ibcon#about to write, iclass 26, count 0 2006.196.07:41:58.88#ibcon#wrote, iclass 26, count 0 2006.196.07:41:58.88#ibcon#about to read 3, iclass 26, count 0 2006.196.07:41:58.90#ibcon#read 3, iclass 26, count 0 2006.196.07:41:58.90#ibcon#about to read 4, iclass 26, count 0 2006.196.07:41:58.90#ibcon#read 4, iclass 26, count 0 2006.196.07:41:58.90#ibcon#about to read 5, iclass 26, count 0 2006.196.07:41:58.90#ibcon#read 5, iclass 26, count 0 2006.196.07:41:58.90#ibcon#about to read 6, iclass 26, count 0 2006.196.07:41:58.90#ibcon#read 6, iclass 26, count 0 2006.196.07:41:58.90#ibcon#end of sib2, iclass 26, count 0 2006.196.07:41:58.90#ibcon#*mode == 0, iclass 26, count 0 2006.196.07:41:58.90#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.196.07:41:58.90#ibcon#[26=FRQ=04,832.99\r\n] 2006.196.07:41:58.90#ibcon#*before write, iclass 26, count 0 2006.196.07:41:58.90#ibcon#enter sib2, iclass 26, count 0 2006.196.07:41:58.90#ibcon#flushed, iclass 26, count 0 2006.196.07:41:58.90#ibcon#about to write, iclass 26, count 0 2006.196.07:41:58.90#ibcon#wrote, iclass 26, count 0 2006.196.07:41:58.90#ibcon#about to read 3, iclass 26, count 0 2006.196.07:41:58.94#ibcon#read 3, iclass 26, count 0 2006.196.07:41:58.94#ibcon#about to read 4, iclass 26, count 0 2006.196.07:41:58.94#ibcon#read 4, iclass 26, count 0 2006.196.07:41:58.94#ibcon#about to read 5, iclass 26, count 0 2006.196.07:41:58.94#ibcon#read 5, iclass 26, count 0 2006.196.07:41:58.94#ibcon#about to read 6, iclass 26, count 0 2006.196.07:41:58.94#ibcon#read 6, iclass 26, count 0 2006.196.07:41:58.94#ibcon#end of sib2, iclass 26, count 0 2006.196.07:41:58.94#ibcon#*after write, iclass 26, count 0 2006.196.07:41:58.94#ibcon#*before return 0, iclass 26, count 0 2006.196.07:41:58.94#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.196.07:41:58.94#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.196.07:41:58.94#ibcon#about to clear, iclass 26 cls_cnt 0 2006.196.07:41:58.94#ibcon#cleared, iclass 26 cls_cnt 0 2006.196.07:41:58.94$vc4f8/va=4,7 2006.196.07:41:58.94#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.196.07:41:58.94#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.196.07:41:58.94#ibcon#ireg 11 cls_cnt 2 2006.196.07:41:58.94#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.196.07:41:59.00#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.196.07:41:59.00#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.196.07:41:59.00#ibcon#enter wrdev, iclass 28, count 2 2006.196.07:41:59.00#ibcon#first serial, iclass 28, count 2 2006.196.07:41:59.00#ibcon#enter sib2, iclass 28, count 2 2006.196.07:41:59.00#ibcon#flushed, iclass 28, count 2 2006.196.07:41:59.00#ibcon#about to write, iclass 28, count 2 2006.196.07:41:59.00#ibcon#wrote, iclass 28, count 2 2006.196.07:41:59.00#ibcon#about to read 3, iclass 28, count 2 2006.196.07:41:59.02#ibcon#read 3, iclass 28, count 2 2006.196.07:41:59.02#ibcon#about to read 4, iclass 28, count 2 2006.196.07:41:59.02#ibcon#read 4, iclass 28, count 2 2006.196.07:41:59.02#ibcon#about to read 5, iclass 28, count 2 2006.196.07:41:59.02#ibcon#read 5, iclass 28, count 2 2006.196.07:41:59.02#ibcon#about to read 6, iclass 28, count 2 2006.196.07:41:59.02#ibcon#read 6, iclass 28, count 2 2006.196.07:41:59.02#ibcon#end of sib2, iclass 28, count 2 2006.196.07:41:59.02#ibcon#*mode == 0, iclass 28, count 2 2006.196.07:41:59.02#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.196.07:41:59.02#ibcon#[25=AT04-07\r\n] 2006.196.07:41:59.02#ibcon#*before write, iclass 28, count 2 2006.196.07:41:59.02#ibcon#enter sib2, iclass 28, count 2 2006.196.07:41:59.02#ibcon#flushed, iclass 28, count 2 2006.196.07:41:59.02#ibcon#about to write, iclass 28, count 2 2006.196.07:41:59.02#ibcon#wrote, iclass 28, count 2 2006.196.07:41:59.02#ibcon#about to read 3, iclass 28, count 2 2006.196.07:41:59.05#ibcon#read 3, iclass 28, count 2 2006.196.07:41:59.05#ibcon#about to read 4, iclass 28, count 2 2006.196.07:41:59.05#ibcon#read 4, iclass 28, count 2 2006.196.07:41:59.05#ibcon#about to read 5, iclass 28, count 2 2006.196.07:41:59.05#ibcon#read 5, iclass 28, count 2 2006.196.07:41:59.05#ibcon#about to read 6, iclass 28, count 2 2006.196.07:41:59.05#ibcon#read 6, iclass 28, count 2 2006.196.07:41:59.05#ibcon#end of sib2, iclass 28, count 2 2006.196.07:41:59.05#ibcon#*after write, iclass 28, count 2 2006.196.07:41:59.05#ibcon#*before return 0, iclass 28, count 2 2006.196.07:41:59.05#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.196.07:41:59.05#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.196.07:41:59.05#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.196.07:41:59.05#ibcon#ireg 7 cls_cnt 0 2006.196.07:41:59.05#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.196.07:41:59.17#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.196.07:41:59.17#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.196.07:41:59.17#ibcon#enter wrdev, iclass 28, count 0 2006.196.07:41:59.17#ibcon#first serial, iclass 28, count 0 2006.196.07:41:59.17#ibcon#enter sib2, iclass 28, count 0 2006.196.07:41:59.17#ibcon#flushed, iclass 28, count 0 2006.196.07:41:59.17#ibcon#about to write, iclass 28, count 0 2006.196.07:41:59.17#ibcon#wrote, iclass 28, count 0 2006.196.07:41:59.17#ibcon#about to read 3, iclass 28, count 0 2006.196.07:41:59.19#ibcon#read 3, iclass 28, count 0 2006.196.07:41:59.19#ibcon#about to read 4, iclass 28, count 0 2006.196.07:41:59.19#ibcon#read 4, iclass 28, count 0 2006.196.07:41:59.19#ibcon#about to read 5, iclass 28, count 0 2006.196.07:41:59.19#ibcon#read 5, iclass 28, count 0 2006.196.07:41:59.19#ibcon#about to read 6, iclass 28, count 0 2006.196.07:41:59.19#ibcon#read 6, iclass 28, count 0 2006.196.07:41:59.19#ibcon#end of sib2, iclass 28, count 0 2006.196.07:41:59.19#ibcon#*mode == 0, iclass 28, count 0 2006.196.07:41:59.19#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.196.07:41:59.19#ibcon#[25=USB\r\n] 2006.196.07:41:59.19#ibcon#*before write, iclass 28, count 0 2006.196.07:41:59.19#ibcon#enter sib2, iclass 28, count 0 2006.196.07:41:59.19#ibcon#flushed, iclass 28, count 0 2006.196.07:41:59.19#ibcon#about to write, iclass 28, count 0 2006.196.07:41:59.19#ibcon#wrote, iclass 28, count 0 2006.196.07:41:59.19#ibcon#about to read 3, iclass 28, count 0 2006.196.07:41:59.22#ibcon#read 3, iclass 28, count 0 2006.196.07:41:59.22#ibcon#about to read 4, iclass 28, count 0 2006.196.07:41:59.22#ibcon#read 4, iclass 28, count 0 2006.196.07:41:59.22#ibcon#about to read 5, iclass 28, count 0 2006.196.07:41:59.22#ibcon#read 5, iclass 28, count 0 2006.196.07:41:59.22#ibcon#about to read 6, iclass 28, count 0 2006.196.07:41:59.22#ibcon#read 6, iclass 28, count 0 2006.196.07:41:59.22#ibcon#end of sib2, iclass 28, count 0 2006.196.07:41:59.22#ibcon#*after write, iclass 28, count 0 2006.196.07:41:59.22#ibcon#*before return 0, iclass 28, count 0 2006.196.07:41:59.22#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.196.07:41:59.22#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.196.07:41:59.22#ibcon#about to clear, iclass 28 cls_cnt 0 2006.196.07:41:59.22#ibcon#cleared, iclass 28 cls_cnt 0 2006.196.07:41:59.22$vc4f8/valo=5,652.99 2006.196.07:41:59.22#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.196.07:41:59.22#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.196.07:41:59.22#ibcon#ireg 17 cls_cnt 0 2006.196.07:41:59.22#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.196.07:41:59.22#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.196.07:41:59.22#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.196.07:41:59.22#ibcon#enter wrdev, iclass 30, count 0 2006.196.07:41:59.22#ibcon#first serial, iclass 30, count 0 2006.196.07:41:59.22#ibcon#enter sib2, iclass 30, count 0 2006.196.07:41:59.22#ibcon#flushed, iclass 30, count 0 2006.196.07:41:59.22#ibcon#about to write, iclass 30, count 0 2006.196.07:41:59.22#ibcon#wrote, iclass 30, count 0 2006.196.07:41:59.22#ibcon#about to read 3, iclass 30, count 0 2006.196.07:41:59.24#ibcon#read 3, iclass 30, count 0 2006.196.07:41:59.24#ibcon#about to read 4, iclass 30, count 0 2006.196.07:41:59.24#ibcon#read 4, iclass 30, count 0 2006.196.07:41:59.24#ibcon#about to read 5, iclass 30, count 0 2006.196.07:41:59.24#ibcon#read 5, iclass 30, count 0 2006.196.07:41:59.24#ibcon#about to read 6, iclass 30, count 0 2006.196.07:41:59.24#ibcon#read 6, iclass 30, count 0 2006.196.07:41:59.24#ibcon#end of sib2, iclass 30, count 0 2006.196.07:41:59.24#ibcon#*mode == 0, iclass 30, count 0 2006.196.07:41:59.24#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.196.07:41:59.24#ibcon#[26=FRQ=05,652.99\r\n] 2006.196.07:41:59.24#ibcon#*before write, iclass 30, count 0 2006.196.07:41:59.24#ibcon#enter sib2, iclass 30, count 0 2006.196.07:41:59.24#ibcon#flushed, iclass 30, count 0 2006.196.07:41:59.24#ibcon#about to write, iclass 30, count 0 2006.196.07:41:59.24#ibcon#wrote, iclass 30, count 0 2006.196.07:41:59.24#ibcon#about to read 3, iclass 30, count 0 2006.196.07:41:59.28#ibcon#read 3, iclass 30, count 0 2006.196.07:41:59.28#ibcon#about to read 4, iclass 30, count 0 2006.196.07:41:59.28#ibcon#read 4, iclass 30, count 0 2006.196.07:41:59.28#ibcon#about to read 5, iclass 30, count 0 2006.196.07:41:59.28#ibcon#read 5, iclass 30, count 0 2006.196.07:41:59.28#ibcon#about to read 6, iclass 30, count 0 2006.196.07:41:59.28#ibcon#read 6, iclass 30, count 0 2006.196.07:41:59.28#ibcon#end of sib2, iclass 30, count 0 2006.196.07:41:59.28#ibcon#*after write, iclass 30, count 0 2006.196.07:41:59.28#ibcon#*before return 0, iclass 30, count 0 2006.196.07:41:59.28#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.196.07:41:59.28#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.196.07:41:59.28#ibcon#about to clear, iclass 30 cls_cnt 0 2006.196.07:41:59.28#ibcon#cleared, iclass 30 cls_cnt 0 2006.196.07:41:59.28$vc4f8/va=5,7 2006.196.07:41:59.28#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.196.07:41:59.28#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.196.07:41:59.28#ibcon#ireg 11 cls_cnt 2 2006.196.07:41:59.28#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.196.07:41:59.34#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.196.07:41:59.34#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.196.07:41:59.34#ibcon#enter wrdev, iclass 32, count 2 2006.196.07:41:59.34#ibcon#first serial, iclass 32, count 2 2006.196.07:41:59.34#ibcon#enter sib2, iclass 32, count 2 2006.196.07:41:59.34#ibcon#flushed, iclass 32, count 2 2006.196.07:41:59.34#ibcon#about to write, iclass 32, count 2 2006.196.07:41:59.34#ibcon#wrote, iclass 32, count 2 2006.196.07:41:59.34#ibcon#about to read 3, iclass 32, count 2 2006.196.07:41:59.36#ibcon#read 3, iclass 32, count 2 2006.196.07:41:59.36#ibcon#about to read 4, iclass 32, count 2 2006.196.07:41:59.36#ibcon#read 4, iclass 32, count 2 2006.196.07:41:59.36#ibcon#about to read 5, iclass 32, count 2 2006.196.07:41:59.36#ibcon#read 5, iclass 32, count 2 2006.196.07:41:59.36#ibcon#about to read 6, iclass 32, count 2 2006.196.07:41:59.36#ibcon#read 6, iclass 32, count 2 2006.196.07:41:59.36#ibcon#end of sib2, iclass 32, count 2 2006.196.07:41:59.36#ibcon#*mode == 0, iclass 32, count 2 2006.196.07:41:59.36#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.196.07:41:59.36#ibcon#[25=AT05-07\r\n] 2006.196.07:41:59.36#ibcon#*before write, iclass 32, count 2 2006.196.07:41:59.36#ibcon#enter sib2, iclass 32, count 2 2006.196.07:41:59.36#ibcon#flushed, iclass 32, count 2 2006.196.07:41:59.36#ibcon#about to write, iclass 32, count 2 2006.196.07:41:59.36#ibcon#wrote, iclass 32, count 2 2006.196.07:41:59.36#ibcon#about to read 3, iclass 32, count 2 2006.196.07:41:59.39#ibcon#read 3, iclass 32, count 2 2006.196.07:41:59.39#ibcon#about to read 4, iclass 32, count 2 2006.196.07:41:59.39#ibcon#read 4, iclass 32, count 2 2006.196.07:41:59.39#ibcon#about to read 5, iclass 32, count 2 2006.196.07:41:59.39#ibcon#read 5, iclass 32, count 2 2006.196.07:41:59.39#ibcon#about to read 6, iclass 32, count 2 2006.196.07:41:59.39#ibcon#read 6, iclass 32, count 2 2006.196.07:41:59.39#ibcon#end of sib2, iclass 32, count 2 2006.196.07:41:59.39#ibcon#*after write, iclass 32, count 2 2006.196.07:41:59.39#ibcon#*before return 0, iclass 32, count 2 2006.196.07:41:59.39#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.196.07:41:59.39#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.196.07:41:59.39#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.196.07:41:59.39#ibcon#ireg 7 cls_cnt 0 2006.196.07:41:59.39#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.196.07:41:59.51#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.196.07:41:59.51#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.196.07:41:59.51#ibcon#enter wrdev, iclass 32, count 0 2006.196.07:41:59.51#ibcon#first serial, iclass 32, count 0 2006.196.07:41:59.51#ibcon#enter sib2, iclass 32, count 0 2006.196.07:41:59.51#ibcon#flushed, iclass 32, count 0 2006.196.07:41:59.51#ibcon#about to write, iclass 32, count 0 2006.196.07:41:59.51#ibcon#wrote, iclass 32, count 0 2006.196.07:41:59.51#ibcon#about to read 3, iclass 32, count 0 2006.196.07:41:59.53#ibcon#read 3, iclass 32, count 0 2006.196.07:41:59.53#ibcon#about to read 4, iclass 32, count 0 2006.196.07:41:59.53#ibcon#read 4, iclass 32, count 0 2006.196.07:41:59.53#ibcon#about to read 5, iclass 32, count 0 2006.196.07:41:59.53#ibcon#read 5, iclass 32, count 0 2006.196.07:41:59.53#ibcon#about to read 6, iclass 32, count 0 2006.196.07:41:59.53#ibcon#read 6, iclass 32, count 0 2006.196.07:41:59.53#ibcon#end of sib2, iclass 32, count 0 2006.196.07:41:59.53#ibcon#*mode == 0, iclass 32, count 0 2006.196.07:41:59.53#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.196.07:41:59.53#ibcon#[25=USB\r\n] 2006.196.07:41:59.53#ibcon#*before write, iclass 32, count 0 2006.196.07:41:59.53#ibcon#enter sib2, iclass 32, count 0 2006.196.07:41:59.53#ibcon#flushed, iclass 32, count 0 2006.196.07:41:59.53#ibcon#about to write, iclass 32, count 0 2006.196.07:41:59.53#ibcon#wrote, iclass 32, count 0 2006.196.07:41:59.53#ibcon#about to read 3, iclass 32, count 0 2006.196.07:41:59.56#ibcon#read 3, iclass 32, count 0 2006.196.07:41:59.56#ibcon#about to read 4, iclass 32, count 0 2006.196.07:41:59.56#ibcon#read 4, iclass 32, count 0 2006.196.07:41:59.56#ibcon#about to read 5, iclass 32, count 0 2006.196.07:41:59.56#ibcon#read 5, iclass 32, count 0 2006.196.07:41:59.56#ibcon#about to read 6, iclass 32, count 0 2006.196.07:41:59.56#ibcon#read 6, iclass 32, count 0 2006.196.07:41:59.56#ibcon#end of sib2, iclass 32, count 0 2006.196.07:41:59.56#ibcon#*after write, iclass 32, count 0 2006.196.07:41:59.56#ibcon#*before return 0, iclass 32, count 0 2006.196.07:41:59.56#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.196.07:41:59.56#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.196.07:41:59.56#ibcon#about to clear, iclass 32 cls_cnt 0 2006.196.07:41:59.56#ibcon#cleared, iclass 32 cls_cnt 0 2006.196.07:41:59.56$vc4f8/valo=6,772.99 2006.196.07:41:59.56#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.196.07:41:59.56#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.196.07:41:59.56#ibcon#ireg 17 cls_cnt 0 2006.196.07:41:59.56#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.196.07:41:59.56#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.196.07:41:59.56#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.196.07:41:59.56#ibcon#enter wrdev, iclass 34, count 0 2006.196.07:41:59.56#ibcon#first serial, iclass 34, count 0 2006.196.07:41:59.56#ibcon#enter sib2, iclass 34, count 0 2006.196.07:41:59.56#ibcon#flushed, iclass 34, count 0 2006.196.07:41:59.56#ibcon#about to write, iclass 34, count 0 2006.196.07:41:59.56#ibcon#wrote, iclass 34, count 0 2006.196.07:41:59.56#ibcon#about to read 3, iclass 34, count 0 2006.196.07:41:59.58#ibcon#read 3, iclass 34, count 0 2006.196.07:41:59.58#ibcon#about to read 4, iclass 34, count 0 2006.196.07:41:59.58#ibcon#read 4, iclass 34, count 0 2006.196.07:41:59.58#ibcon#about to read 5, iclass 34, count 0 2006.196.07:41:59.58#ibcon#read 5, iclass 34, count 0 2006.196.07:41:59.58#ibcon#about to read 6, iclass 34, count 0 2006.196.07:41:59.58#ibcon#read 6, iclass 34, count 0 2006.196.07:41:59.58#ibcon#end of sib2, iclass 34, count 0 2006.196.07:41:59.58#ibcon#*mode == 0, iclass 34, count 0 2006.196.07:41:59.58#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.196.07:41:59.58#ibcon#[26=FRQ=06,772.99\r\n] 2006.196.07:41:59.58#ibcon#*before write, iclass 34, count 0 2006.196.07:41:59.58#ibcon#enter sib2, iclass 34, count 0 2006.196.07:41:59.58#ibcon#flushed, iclass 34, count 0 2006.196.07:41:59.58#ibcon#about to write, iclass 34, count 0 2006.196.07:41:59.58#ibcon#wrote, iclass 34, count 0 2006.196.07:41:59.58#ibcon#about to read 3, iclass 34, count 0 2006.196.07:41:59.62#ibcon#read 3, iclass 34, count 0 2006.196.07:41:59.62#ibcon#about to read 4, iclass 34, count 0 2006.196.07:41:59.62#ibcon#read 4, iclass 34, count 0 2006.196.07:41:59.62#ibcon#about to read 5, iclass 34, count 0 2006.196.07:41:59.62#ibcon#read 5, iclass 34, count 0 2006.196.07:41:59.62#ibcon#about to read 6, iclass 34, count 0 2006.196.07:41:59.62#ibcon#read 6, iclass 34, count 0 2006.196.07:41:59.62#ibcon#end of sib2, iclass 34, count 0 2006.196.07:41:59.62#ibcon#*after write, iclass 34, count 0 2006.196.07:41:59.62#ibcon#*before return 0, iclass 34, count 0 2006.196.07:41:59.62#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.196.07:41:59.62#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.196.07:41:59.62#ibcon#about to clear, iclass 34 cls_cnt 0 2006.196.07:41:59.62#ibcon#cleared, iclass 34 cls_cnt 0 2006.196.07:41:59.62$vc4f8/va=6,6 2006.196.07:41:59.62#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.196.07:41:59.62#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.196.07:41:59.62#ibcon#ireg 11 cls_cnt 2 2006.196.07:41:59.62#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.196.07:41:59.68#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.196.07:41:59.68#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.196.07:41:59.68#ibcon#enter wrdev, iclass 36, count 2 2006.196.07:41:59.68#ibcon#first serial, iclass 36, count 2 2006.196.07:41:59.68#ibcon#enter sib2, iclass 36, count 2 2006.196.07:41:59.68#ibcon#flushed, iclass 36, count 2 2006.196.07:41:59.68#ibcon#about to write, iclass 36, count 2 2006.196.07:41:59.68#ibcon#wrote, iclass 36, count 2 2006.196.07:41:59.68#ibcon#about to read 3, iclass 36, count 2 2006.196.07:41:59.70#ibcon#read 3, iclass 36, count 2 2006.196.07:41:59.70#ibcon#about to read 4, iclass 36, count 2 2006.196.07:41:59.70#ibcon#read 4, iclass 36, count 2 2006.196.07:41:59.70#ibcon#about to read 5, iclass 36, count 2 2006.196.07:41:59.70#ibcon#read 5, iclass 36, count 2 2006.196.07:41:59.70#ibcon#about to read 6, iclass 36, count 2 2006.196.07:41:59.70#ibcon#read 6, iclass 36, count 2 2006.196.07:41:59.70#ibcon#end of sib2, iclass 36, count 2 2006.196.07:41:59.70#ibcon#*mode == 0, iclass 36, count 2 2006.196.07:41:59.70#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.196.07:41:59.70#ibcon#[25=AT06-06\r\n] 2006.196.07:41:59.70#ibcon#*before write, iclass 36, count 2 2006.196.07:41:59.70#ibcon#enter sib2, iclass 36, count 2 2006.196.07:41:59.70#ibcon#flushed, iclass 36, count 2 2006.196.07:41:59.70#ibcon#about to write, iclass 36, count 2 2006.196.07:41:59.70#ibcon#wrote, iclass 36, count 2 2006.196.07:41:59.70#ibcon#about to read 3, iclass 36, count 2 2006.196.07:41:59.73#ibcon#read 3, iclass 36, count 2 2006.196.07:41:59.73#ibcon#about to read 4, iclass 36, count 2 2006.196.07:41:59.73#ibcon#read 4, iclass 36, count 2 2006.196.07:41:59.73#ibcon#about to read 5, iclass 36, count 2 2006.196.07:41:59.73#ibcon#read 5, iclass 36, count 2 2006.196.07:41:59.73#ibcon#about to read 6, iclass 36, count 2 2006.196.07:41:59.73#ibcon#read 6, iclass 36, count 2 2006.196.07:41:59.73#ibcon#end of sib2, iclass 36, count 2 2006.196.07:41:59.73#ibcon#*after write, iclass 36, count 2 2006.196.07:41:59.73#ibcon#*before return 0, iclass 36, count 2 2006.196.07:41:59.73#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.196.07:41:59.73#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.196.07:41:59.73#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.196.07:41:59.73#ibcon#ireg 7 cls_cnt 0 2006.196.07:41:59.73#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.196.07:41:59.85#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.196.07:41:59.85#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.196.07:41:59.85#ibcon#enter wrdev, iclass 36, count 0 2006.196.07:41:59.85#ibcon#first serial, iclass 36, count 0 2006.196.07:41:59.85#ibcon#enter sib2, iclass 36, count 0 2006.196.07:41:59.85#ibcon#flushed, iclass 36, count 0 2006.196.07:41:59.85#ibcon#about to write, iclass 36, count 0 2006.196.07:41:59.85#ibcon#wrote, iclass 36, count 0 2006.196.07:41:59.85#ibcon#about to read 3, iclass 36, count 0 2006.196.07:41:59.87#ibcon#read 3, iclass 36, count 0 2006.196.07:41:59.87#ibcon#about to read 4, iclass 36, count 0 2006.196.07:41:59.87#ibcon#read 4, iclass 36, count 0 2006.196.07:41:59.87#ibcon#about to read 5, iclass 36, count 0 2006.196.07:41:59.87#ibcon#read 5, iclass 36, count 0 2006.196.07:41:59.87#ibcon#about to read 6, iclass 36, count 0 2006.196.07:41:59.87#ibcon#read 6, iclass 36, count 0 2006.196.07:41:59.87#ibcon#end of sib2, iclass 36, count 0 2006.196.07:41:59.87#ibcon#*mode == 0, iclass 36, count 0 2006.196.07:41:59.87#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.196.07:41:59.87#ibcon#[25=USB\r\n] 2006.196.07:41:59.87#ibcon#*before write, iclass 36, count 0 2006.196.07:41:59.87#ibcon#enter sib2, iclass 36, count 0 2006.196.07:41:59.87#ibcon#flushed, iclass 36, count 0 2006.196.07:41:59.87#ibcon#about to write, iclass 36, count 0 2006.196.07:41:59.87#ibcon#wrote, iclass 36, count 0 2006.196.07:41:59.87#ibcon#about to read 3, iclass 36, count 0 2006.196.07:41:59.90#ibcon#read 3, iclass 36, count 0 2006.196.07:41:59.90#ibcon#about to read 4, iclass 36, count 0 2006.196.07:41:59.90#ibcon#read 4, iclass 36, count 0 2006.196.07:41:59.90#ibcon#about to read 5, iclass 36, count 0 2006.196.07:41:59.90#ibcon#read 5, iclass 36, count 0 2006.196.07:41:59.90#ibcon#about to read 6, iclass 36, count 0 2006.196.07:41:59.90#ibcon#read 6, iclass 36, count 0 2006.196.07:41:59.90#ibcon#end of sib2, iclass 36, count 0 2006.196.07:41:59.90#ibcon#*after write, iclass 36, count 0 2006.196.07:41:59.90#ibcon#*before return 0, iclass 36, count 0 2006.196.07:41:59.90#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.196.07:41:59.90#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.196.07:41:59.90#ibcon#about to clear, iclass 36 cls_cnt 0 2006.196.07:41:59.90#ibcon#cleared, iclass 36 cls_cnt 0 2006.196.07:41:59.90$vc4f8/valo=7,832.99 2006.196.07:41:59.90#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.196.07:41:59.90#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.196.07:41:59.90#ibcon#ireg 17 cls_cnt 0 2006.196.07:41:59.90#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.196.07:41:59.90#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.196.07:41:59.90#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.196.07:41:59.90#ibcon#enter wrdev, iclass 38, count 0 2006.196.07:41:59.90#ibcon#first serial, iclass 38, count 0 2006.196.07:41:59.90#ibcon#enter sib2, iclass 38, count 0 2006.196.07:41:59.90#ibcon#flushed, iclass 38, count 0 2006.196.07:41:59.90#ibcon#about to write, iclass 38, count 0 2006.196.07:41:59.90#ibcon#wrote, iclass 38, count 0 2006.196.07:41:59.90#ibcon#about to read 3, iclass 38, count 0 2006.196.07:41:59.92#ibcon#read 3, iclass 38, count 0 2006.196.07:41:59.92#ibcon#about to read 4, iclass 38, count 0 2006.196.07:41:59.92#ibcon#read 4, iclass 38, count 0 2006.196.07:41:59.92#ibcon#about to read 5, iclass 38, count 0 2006.196.07:41:59.92#ibcon#read 5, iclass 38, count 0 2006.196.07:41:59.92#ibcon#about to read 6, iclass 38, count 0 2006.196.07:41:59.92#ibcon#read 6, iclass 38, count 0 2006.196.07:41:59.92#ibcon#end of sib2, iclass 38, count 0 2006.196.07:41:59.92#ibcon#*mode == 0, iclass 38, count 0 2006.196.07:41:59.92#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.196.07:41:59.92#ibcon#[26=FRQ=07,832.99\r\n] 2006.196.07:41:59.92#ibcon#*before write, iclass 38, count 0 2006.196.07:41:59.92#ibcon#enter sib2, iclass 38, count 0 2006.196.07:41:59.92#ibcon#flushed, iclass 38, count 0 2006.196.07:41:59.92#ibcon#about to write, iclass 38, count 0 2006.196.07:41:59.92#ibcon#wrote, iclass 38, count 0 2006.196.07:41:59.92#ibcon#about to read 3, iclass 38, count 0 2006.196.07:41:59.96#ibcon#read 3, iclass 38, count 0 2006.196.07:41:59.96#ibcon#about to read 4, iclass 38, count 0 2006.196.07:41:59.96#ibcon#read 4, iclass 38, count 0 2006.196.07:41:59.96#ibcon#about to read 5, iclass 38, count 0 2006.196.07:41:59.96#ibcon#read 5, iclass 38, count 0 2006.196.07:41:59.96#ibcon#about to read 6, iclass 38, count 0 2006.196.07:41:59.96#ibcon#read 6, iclass 38, count 0 2006.196.07:41:59.96#ibcon#end of sib2, iclass 38, count 0 2006.196.07:41:59.96#ibcon#*after write, iclass 38, count 0 2006.196.07:41:59.96#ibcon#*before return 0, iclass 38, count 0 2006.196.07:41:59.96#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.196.07:41:59.96#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.196.07:41:59.96#ibcon#about to clear, iclass 38 cls_cnt 0 2006.196.07:41:59.96#ibcon#cleared, iclass 38 cls_cnt 0 2006.196.07:41:59.96$vc4f8/va=7,6 2006.196.07:41:59.96#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.196.07:41:59.96#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.196.07:41:59.96#ibcon#ireg 11 cls_cnt 2 2006.196.07:41:59.96#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.196.07:42:00.02#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.196.07:42:00.02#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.196.07:42:00.02#ibcon#enter wrdev, iclass 40, count 2 2006.196.07:42:00.02#ibcon#first serial, iclass 40, count 2 2006.196.07:42:00.02#ibcon#enter sib2, iclass 40, count 2 2006.196.07:42:00.02#ibcon#flushed, iclass 40, count 2 2006.196.07:42:00.02#ibcon#about to write, iclass 40, count 2 2006.196.07:42:00.02#ibcon#wrote, iclass 40, count 2 2006.196.07:42:00.02#ibcon#about to read 3, iclass 40, count 2 2006.196.07:42:00.04#ibcon#read 3, iclass 40, count 2 2006.196.07:42:00.04#ibcon#about to read 4, iclass 40, count 2 2006.196.07:42:00.04#ibcon#read 4, iclass 40, count 2 2006.196.07:42:00.04#ibcon#about to read 5, iclass 40, count 2 2006.196.07:42:00.04#ibcon#read 5, iclass 40, count 2 2006.196.07:42:00.04#ibcon#about to read 6, iclass 40, count 2 2006.196.07:42:00.04#ibcon#read 6, iclass 40, count 2 2006.196.07:42:00.04#ibcon#end of sib2, iclass 40, count 2 2006.196.07:42:00.04#ibcon#*mode == 0, iclass 40, count 2 2006.196.07:42:00.04#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.196.07:42:00.04#ibcon#[25=AT07-06\r\n] 2006.196.07:42:00.04#ibcon#*before write, iclass 40, count 2 2006.196.07:42:00.04#ibcon#enter sib2, iclass 40, count 2 2006.196.07:42:00.04#ibcon#flushed, iclass 40, count 2 2006.196.07:42:00.04#ibcon#about to write, iclass 40, count 2 2006.196.07:42:00.04#ibcon#wrote, iclass 40, count 2 2006.196.07:42:00.04#ibcon#about to read 3, iclass 40, count 2 2006.196.07:42:00.07#ibcon#read 3, iclass 40, count 2 2006.196.07:42:00.07#ibcon#about to read 4, iclass 40, count 2 2006.196.07:42:00.07#ibcon#read 4, iclass 40, count 2 2006.196.07:42:00.07#ibcon#about to read 5, iclass 40, count 2 2006.196.07:42:00.07#ibcon#read 5, iclass 40, count 2 2006.196.07:42:00.07#ibcon#about to read 6, iclass 40, count 2 2006.196.07:42:00.07#ibcon#read 6, iclass 40, count 2 2006.196.07:42:00.07#ibcon#end of sib2, iclass 40, count 2 2006.196.07:42:00.07#ibcon#*after write, iclass 40, count 2 2006.196.07:42:00.07#ibcon#*before return 0, iclass 40, count 2 2006.196.07:42:00.07#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.196.07:42:00.07#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.196.07:42:00.07#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.196.07:42:00.07#ibcon#ireg 7 cls_cnt 0 2006.196.07:42:00.07#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.196.07:42:00.19#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.196.07:42:00.19#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.196.07:42:00.19#ibcon#enter wrdev, iclass 40, count 0 2006.196.07:42:00.19#ibcon#first serial, iclass 40, count 0 2006.196.07:42:00.19#ibcon#enter sib2, iclass 40, count 0 2006.196.07:42:00.19#ibcon#flushed, iclass 40, count 0 2006.196.07:42:00.19#ibcon#about to write, iclass 40, count 0 2006.196.07:42:00.19#ibcon#wrote, iclass 40, count 0 2006.196.07:42:00.19#ibcon#about to read 3, iclass 40, count 0 2006.196.07:42:00.21#ibcon#read 3, iclass 40, count 0 2006.196.07:42:00.21#ibcon#about to read 4, iclass 40, count 0 2006.196.07:42:00.21#ibcon#read 4, iclass 40, count 0 2006.196.07:42:00.21#ibcon#about to read 5, iclass 40, count 0 2006.196.07:42:00.21#ibcon#read 5, iclass 40, count 0 2006.196.07:42:00.21#ibcon#about to read 6, iclass 40, count 0 2006.196.07:42:00.21#ibcon#read 6, iclass 40, count 0 2006.196.07:42:00.21#ibcon#end of sib2, iclass 40, count 0 2006.196.07:42:00.21#ibcon#*mode == 0, iclass 40, count 0 2006.196.07:42:00.21#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.196.07:42:00.21#ibcon#[25=USB\r\n] 2006.196.07:42:00.21#ibcon#*before write, iclass 40, count 0 2006.196.07:42:00.21#ibcon#enter sib2, iclass 40, count 0 2006.196.07:42:00.21#ibcon#flushed, iclass 40, count 0 2006.196.07:42:00.21#ibcon#about to write, iclass 40, count 0 2006.196.07:42:00.21#ibcon#wrote, iclass 40, count 0 2006.196.07:42:00.21#ibcon#about to read 3, iclass 40, count 0 2006.196.07:42:00.24#ibcon#read 3, iclass 40, count 0 2006.196.07:42:00.24#ibcon#about to read 4, iclass 40, count 0 2006.196.07:42:00.24#ibcon#read 4, iclass 40, count 0 2006.196.07:42:00.24#ibcon#about to read 5, iclass 40, count 0 2006.196.07:42:00.24#ibcon#read 5, iclass 40, count 0 2006.196.07:42:00.24#ibcon#about to read 6, iclass 40, count 0 2006.196.07:42:00.24#ibcon#read 6, iclass 40, count 0 2006.196.07:42:00.24#ibcon#end of sib2, iclass 40, count 0 2006.196.07:42:00.24#ibcon#*after write, iclass 40, count 0 2006.196.07:42:00.24#ibcon#*before return 0, iclass 40, count 0 2006.196.07:42:00.24#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.196.07:42:00.24#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.196.07:42:00.24#ibcon#about to clear, iclass 40 cls_cnt 0 2006.196.07:42:00.24#ibcon#cleared, iclass 40 cls_cnt 0 2006.196.07:42:00.24$vc4f8/valo=8,852.99 2006.196.07:42:00.24#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.196.07:42:00.24#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.196.07:42:00.24#ibcon#ireg 17 cls_cnt 0 2006.196.07:42:00.24#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.196.07:42:00.24#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.196.07:42:00.24#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.196.07:42:00.24#ibcon#enter wrdev, iclass 4, count 0 2006.196.07:42:00.24#ibcon#first serial, iclass 4, count 0 2006.196.07:42:00.24#ibcon#enter sib2, iclass 4, count 0 2006.196.07:42:00.24#ibcon#flushed, iclass 4, count 0 2006.196.07:42:00.24#ibcon#about to write, iclass 4, count 0 2006.196.07:42:00.24#ibcon#wrote, iclass 4, count 0 2006.196.07:42:00.24#ibcon#about to read 3, iclass 4, count 0 2006.196.07:42:00.26#ibcon#read 3, iclass 4, count 0 2006.196.07:42:00.26#ibcon#about to read 4, iclass 4, count 0 2006.196.07:42:00.26#ibcon#read 4, iclass 4, count 0 2006.196.07:42:00.26#ibcon#about to read 5, iclass 4, count 0 2006.196.07:42:00.26#ibcon#read 5, iclass 4, count 0 2006.196.07:42:00.26#ibcon#about to read 6, iclass 4, count 0 2006.196.07:42:00.26#ibcon#read 6, iclass 4, count 0 2006.196.07:42:00.26#ibcon#end of sib2, iclass 4, count 0 2006.196.07:42:00.26#ibcon#*mode == 0, iclass 4, count 0 2006.196.07:42:00.26#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.196.07:42:00.26#ibcon#[26=FRQ=08,852.99\r\n] 2006.196.07:42:00.26#ibcon#*before write, iclass 4, count 0 2006.196.07:42:00.26#ibcon#enter sib2, iclass 4, count 0 2006.196.07:42:00.26#ibcon#flushed, iclass 4, count 0 2006.196.07:42:00.26#ibcon#about to write, iclass 4, count 0 2006.196.07:42:00.26#ibcon#wrote, iclass 4, count 0 2006.196.07:42:00.26#ibcon#about to read 3, iclass 4, count 0 2006.196.07:42:00.30#ibcon#read 3, iclass 4, count 0 2006.196.07:42:00.30#ibcon#about to read 4, iclass 4, count 0 2006.196.07:42:00.30#ibcon#read 4, iclass 4, count 0 2006.196.07:42:00.30#ibcon#about to read 5, iclass 4, count 0 2006.196.07:42:00.30#ibcon#read 5, iclass 4, count 0 2006.196.07:42:00.30#ibcon#about to read 6, iclass 4, count 0 2006.196.07:42:00.30#ibcon#read 6, iclass 4, count 0 2006.196.07:42:00.30#ibcon#end of sib2, iclass 4, count 0 2006.196.07:42:00.30#ibcon#*after write, iclass 4, count 0 2006.196.07:42:00.30#ibcon#*before return 0, iclass 4, count 0 2006.196.07:42:00.30#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.196.07:42:00.30#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.196.07:42:00.30#ibcon#about to clear, iclass 4 cls_cnt 0 2006.196.07:42:00.30#ibcon#cleared, iclass 4 cls_cnt 0 2006.196.07:42:00.30$vc4f8/va=8,7 2006.196.07:42:00.30#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.196.07:42:00.30#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.196.07:42:00.30#ibcon#ireg 11 cls_cnt 2 2006.196.07:42:00.30#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.196.07:42:00.36#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.196.07:42:00.36#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.196.07:42:00.36#ibcon#enter wrdev, iclass 6, count 2 2006.196.07:42:00.36#ibcon#first serial, iclass 6, count 2 2006.196.07:42:00.36#ibcon#enter sib2, iclass 6, count 2 2006.196.07:42:00.36#ibcon#flushed, iclass 6, count 2 2006.196.07:42:00.36#ibcon#about to write, iclass 6, count 2 2006.196.07:42:00.36#ibcon#wrote, iclass 6, count 2 2006.196.07:42:00.36#ibcon#about to read 3, iclass 6, count 2 2006.196.07:42:00.38#ibcon#read 3, iclass 6, count 2 2006.196.07:42:00.38#ibcon#about to read 4, iclass 6, count 2 2006.196.07:42:00.38#ibcon#read 4, iclass 6, count 2 2006.196.07:42:00.38#ibcon#about to read 5, iclass 6, count 2 2006.196.07:42:00.38#ibcon#read 5, iclass 6, count 2 2006.196.07:42:00.38#ibcon#about to read 6, iclass 6, count 2 2006.196.07:42:00.38#ibcon#read 6, iclass 6, count 2 2006.196.07:42:00.38#ibcon#end of sib2, iclass 6, count 2 2006.196.07:42:00.38#ibcon#*mode == 0, iclass 6, count 2 2006.196.07:42:00.38#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.196.07:42:00.38#ibcon#[25=AT08-07\r\n] 2006.196.07:42:00.38#ibcon#*before write, iclass 6, count 2 2006.196.07:42:00.38#ibcon#enter sib2, iclass 6, count 2 2006.196.07:42:00.38#ibcon#flushed, iclass 6, count 2 2006.196.07:42:00.38#ibcon#about to write, iclass 6, count 2 2006.196.07:42:00.38#ibcon#wrote, iclass 6, count 2 2006.196.07:42:00.38#ibcon#about to read 3, iclass 6, count 2 2006.196.07:42:00.41#ibcon#read 3, iclass 6, count 2 2006.196.07:42:00.41#ibcon#about to read 4, iclass 6, count 2 2006.196.07:42:00.41#ibcon#read 4, iclass 6, count 2 2006.196.07:42:00.41#ibcon#about to read 5, iclass 6, count 2 2006.196.07:42:00.41#ibcon#read 5, iclass 6, count 2 2006.196.07:42:00.41#ibcon#about to read 6, iclass 6, count 2 2006.196.07:42:00.41#ibcon#read 6, iclass 6, count 2 2006.196.07:42:00.41#ibcon#end of sib2, iclass 6, count 2 2006.196.07:42:00.41#ibcon#*after write, iclass 6, count 2 2006.196.07:42:00.41#ibcon#*before return 0, iclass 6, count 2 2006.196.07:42:00.41#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.196.07:42:00.41#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.196.07:42:00.41#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.196.07:42:00.41#ibcon#ireg 7 cls_cnt 0 2006.196.07:42:00.41#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.196.07:42:00.53#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.196.07:42:00.53#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.196.07:42:00.53#ibcon#enter wrdev, iclass 6, count 0 2006.196.07:42:00.53#ibcon#first serial, iclass 6, count 0 2006.196.07:42:00.53#ibcon#enter sib2, iclass 6, count 0 2006.196.07:42:00.53#ibcon#flushed, iclass 6, count 0 2006.196.07:42:00.53#ibcon#about to write, iclass 6, count 0 2006.196.07:42:00.53#ibcon#wrote, iclass 6, count 0 2006.196.07:42:00.53#ibcon#about to read 3, iclass 6, count 0 2006.196.07:42:00.55#ibcon#read 3, iclass 6, count 0 2006.196.07:42:00.55#ibcon#about to read 4, iclass 6, count 0 2006.196.07:42:00.55#ibcon#read 4, iclass 6, count 0 2006.196.07:42:00.55#ibcon#about to read 5, iclass 6, count 0 2006.196.07:42:00.55#ibcon#read 5, iclass 6, count 0 2006.196.07:42:00.55#ibcon#about to read 6, iclass 6, count 0 2006.196.07:42:00.55#ibcon#read 6, iclass 6, count 0 2006.196.07:42:00.55#ibcon#end of sib2, iclass 6, count 0 2006.196.07:42:00.55#ibcon#*mode == 0, iclass 6, count 0 2006.196.07:42:00.55#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.196.07:42:00.55#ibcon#[25=USB\r\n] 2006.196.07:42:00.55#ibcon#*before write, iclass 6, count 0 2006.196.07:42:00.55#ibcon#enter sib2, iclass 6, count 0 2006.196.07:42:00.55#ibcon#flushed, iclass 6, count 0 2006.196.07:42:00.55#ibcon#about to write, iclass 6, count 0 2006.196.07:42:00.55#ibcon#wrote, iclass 6, count 0 2006.196.07:42:00.55#ibcon#about to read 3, iclass 6, count 0 2006.196.07:42:00.58#ibcon#read 3, iclass 6, count 0 2006.196.07:42:00.58#ibcon#about to read 4, iclass 6, count 0 2006.196.07:42:00.58#ibcon#read 4, iclass 6, count 0 2006.196.07:42:00.58#ibcon#about to read 5, iclass 6, count 0 2006.196.07:42:00.58#ibcon#read 5, iclass 6, count 0 2006.196.07:42:00.58#ibcon#about to read 6, iclass 6, count 0 2006.196.07:42:00.58#ibcon#read 6, iclass 6, count 0 2006.196.07:42:00.58#ibcon#end of sib2, iclass 6, count 0 2006.196.07:42:00.58#ibcon#*after write, iclass 6, count 0 2006.196.07:42:00.58#ibcon#*before return 0, iclass 6, count 0 2006.196.07:42:00.58#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.196.07:42:00.58#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.196.07:42:00.58#ibcon#about to clear, iclass 6 cls_cnt 0 2006.196.07:42:00.58#ibcon#cleared, iclass 6 cls_cnt 0 2006.196.07:42:00.58$vc4f8/vblo=1,632.99 2006.196.07:42:00.58#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.196.07:42:00.58#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.196.07:42:00.58#ibcon#ireg 17 cls_cnt 0 2006.196.07:42:00.58#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.196.07:42:00.58#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.196.07:42:00.58#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.196.07:42:00.58#ibcon#enter wrdev, iclass 10, count 0 2006.196.07:42:00.58#ibcon#first serial, iclass 10, count 0 2006.196.07:42:00.58#ibcon#enter sib2, iclass 10, count 0 2006.196.07:42:00.58#ibcon#flushed, iclass 10, count 0 2006.196.07:42:00.58#ibcon#about to write, iclass 10, count 0 2006.196.07:42:00.58#ibcon#wrote, iclass 10, count 0 2006.196.07:42:00.58#ibcon#about to read 3, iclass 10, count 0 2006.196.07:42:00.60#ibcon#read 3, iclass 10, count 0 2006.196.07:42:00.60#ibcon#about to read 4, iclass 10, count 0 2006.196.07:42:00.60#ibcon#read 4, iclass 10, count 0 2006.196.07:42:00.60#ibcon#about to read 5, iclass 10, count 0 2006.196.07:42:00.60#ibcon#read 5, iclass 10, count 0 2006.196.07:42:00.60#ibcon#about to read 6, iclass 10, count 0 2006.196.07:42:00.60#ibcon#read 6, iclass 10, count 0 2006.196.07:42:00.60#ibcon#end of sib2, iclass 10, count 0 2006.196.07:42:00.60#ibcon#*mode == 0, iclass 10, count 0 2006.196.07:42:00.60#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.196.07:42:00.60#ibcon#[28=FRQ=01,632.99\r\n] 2006.196.07:42:00.60#ibcon#*before write, iclass 10, count 0 2006.196.07:42:00.60#ibcon#enter sib2, iclass 10, count 0 2006.196.07:42:00.60#ibcon#flushed, iclass 10, count 0 2006.196.07:42:00.60#ibcon#about to write, iclass 10, count 0 2006.196.07:42:00.60#ibcon#wrote, iclass 10, count 0 2006.196.07:42:00.60#ibcon#about to read 3, iclass 10, count 0 2006.196.07:42:00.64#ibcon#read 3, iclass 10, count 0 2006.196.07:42:00.64#ibcon#about to read 4, iclass 10, count 0 2006.196.07:42:00.64#ibcon#read 4, iclass 10, count 0 2006.196.07:42:00.64#ibcon#about to read 5, iclass 10, count 0 2006.196.07:42:00.64#ibcon#read 5, iclass 10, count 0 2006.196.07:42:00.64#ibcon#about to read 6, iclass 10, count 0 2006.196.07:42:00.64#ibcon#read 6, iclass 10, count 0 2006.196.07:42:00.64#ibcon#end of sib2, iclass 10, count 0 2006.196.07:42:00.64#ibcon#*after write, iclass 10, count 0 2006.196.07:42:00.64#ibcon#*before return 0, iclass 10, count 0 2006.196.07:42:00.64#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.196.07:42:00.64#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.196.07:42:00.64#ibcon#about to clear, iclass 10 cls_cnt 0 2006.196.07:42:00.64#ibcon#cleared, iclass 10 cls_cnt 0 2006.196.07:42:00.64$vc4f8/vb=1,4 2006.196.07:42:00.64#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.196.07:42:00.64#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.196.07:42:00.64#ibcon#ireg 11 cls_cnt 2 2006.196.07:42:00.64#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.196.07:42:00.64#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.196.07:42:00.64#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.196.07:42:00.64#ibcon#enter wrdev, iclass 12, count 2 2006.196.07:42:00.64#ibcon#first serial, iclass 12, count 2 2006.196.07:42:00.64#ibcon#enter sib2, iclass 12, count 2 2006.196.07:42:00.64#ibcon#flushed, iclass 12, count 2 2006.196.07:42:00.64#ibcon#about to write, iclass 12, count 2 2006.196.07:42:00.64#ibcon#wrote, iclass 12, count 2 2006.196.07:42:00.64#ibcon#about to read 3, iclass 12, count 2 2006.196.07:42:00.66#ibcon#read 3, iclass 12, count 2 2006.196.07:42:00.66#ibcon#about to read 4, iclass 12, count 2 2006.196.07:42:00.66#ibcon#read 4, iclass 12, count 2 2006.196.07:42:00.66#ibcon#about to read 5, iclass 12, count 2 2006.196.07:42:00.66#ibcon#read 5, iclass 12, count 2 2006.196.07:42:00.66#ibcon#about to read 6, iclass 12, count 2 2006.196.07:42:00.66#ibcon#read 6, iclass 12, count 2 2006.196.07:42:00.66#ibcon#end of sib2, iclass 12, count 2 2006.196.07:42:00.66#ibcon#*mode == 0, iclass 12, count 2 2006.196.07:42:00.66#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.196.07:42:00.66#ibcon#[27=AT01-04\r\n] 2006.196.07:42:00.66#ibcon#*before write, iclass 12, count 2 2006.196.07:42:00.66#ibcon#enter sib2, iclass 12, count 2 2006.196.07:42:00.66#ibcon#flushed, iclass 12, count 2 2006.196.07:42:00.66#ibcon#about to write, iclass 12, count 2 2006.196.07:42:00.66#ibcon#wrote, iclass 12, count 2 2006.196.07:42:00.66#ibcon#about to read 3, iclass 12, count 2 2006.196.07:42:00.69#ibcon#read 3, iclass 12, count 2 2006.196.07:42:00.69#ibcon#about to read 4, iclass 12, count 2 2006.196.07:42:00.69#ibcon#read 4, iclass 12, count 2 2006.196.07:42:00.69#ibcon#about to read 5, iclass 12, count 2 2006.196.07:42:00.69#ibcon#read 5, iclass 12, count 2 2006.196.07:42:00.69#ibcon#about to read 6, iclass 12, count 2 2006.196.07:42:00.69#ibcon#read 6, iclass 12, count 2 2006.196.07:42:00.69#ibcon#end of sib2, iclass 12, count 2 2006.196.07:42:00.69#ibcon#*after write, iclass 12, count 2 2006.196.07:42:00.69#ibcon#*before return 0, iclass 12, count 2 2006.196.07:42:00.69#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.196.07:42:00.69#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.196.07:42:00.69#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.196.07:42:00.69#ibcon#ireg 7 cls_cnt 0 2006.196.07:42:00.69#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.196.07:42:00.81#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.196.07:42:00.81#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.196.07:42:00.81#ibcon#enter wrdev, iclass 12, count 0 2006.196.07:42:00.81#ibcon#first serial, iclass 12, count 0 2006.196.07:42:00.81#ibcon#enter sib2, iclass 12, count 0 2006.196.07:42:00.81#ibcon#flushed, iclass 12, count 0 2006.196.07:42:00.81#ibcon#about to write, iclass 12, count 0 2006.196.07:42:00.81#ibcon#wrote, iclass 12, count 0 2006.196.07:42:00.81#ibcon#about to read 3, iclass 12, count 0 2006.196.07:42:00.83#ibcon#read 3, iclass 12, count 0 2006.196.07:42:00.83#ibcon#about to read 4, iclass 12, count 0 2006.196.07:42:00.83#ibcon#read 4, iclass 12, count 0 2006.196.07:42:00.83#ibcon#about to read 5, iclass 12, count 0 2006.196.07:42:00.83#ibcon#read 5, iclass 12, count 0 2006.196.07:42:00.83#ibcon#about to read 6, iclass 12, count 0 2006.196.07:42:00.83#ibcon#read 6, iclass 12, count 0 2006.196.07:42:00.83#ibcon#end of sib2, iclass 12, count 0 2006.196.07:42:00.83#ibcon#*mode == 0, iclass 12, count 0 2006.196.07:42:00.83#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.196.07:42:00.83#ibcon#[27=USB\r\n] 2006.196.07:42:00.83#ibcon#*before write, iclass 12, count 0 2006.196.07:42:00.83#ibcon#enter sib2, iclass 12, count 0 2006.196.07:42:00.83#ibcon#flushed, iclass 12, count 0 2006.196.07:42:00.83#ibcon#about to write, iclass 12, count 0 2006.196.07:42:00.83#ibcon#wrote, iclass 12, count 0 2006.196.07:42:00.83#ibcon#about to read 3, iclass 12, count 0 2006.196.07:42:00.86#ibcon#read 3, iclass 12, count 0 2006.196.07:42:00.86#ibcon#about to read 4, iclass 12, count 0 2006.196.07:42:00.86#ibcon#read 4, iclass 12, count 0 2006.196.07:42:00.86#ibcon#about to read 5, iclass 12, count 0 2006.196.07:42:00.86#ibcon#read 5, iclass 12, count 0 2006.196.07:42:00.86#ibcon#about to read 6, iclass 12, count 0 2006.196.07:42:00.86#ibcon#read 6, iclass 12, count 0 2006.196.07:42:00.86#ibcon#end of sib2, iclass 12, count 0 2006.196.07:42:00.86#ibcon#*after write, iclass 12, count 0 2006.196.07:42:00.86#ibcon#*before return 0, iclass 12, count 0 2006.196.07:42:00.86#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.196.07:42:00.86#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.196.07:42:00.86#ibcon#about to clear, iclass 12 cls_cnt 0 2006.196.07:42:00.86#ibcon#cleared, iclass 12 cls_cnt 0 2006.196.07:42:00.86$vc4f8/vblo=2,640.99 2006.196.07:42:00.86#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.196.07:42:00.86#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.196.07:42:00.86#ibcon#ireg 17 cls_cnt 0 2006.196.07:42:00.86#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.196.07:42:00.86#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.196.07:42:00.86#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.196.07:42:00.86#ibcon#enter wrdev, iclass 14, count 0 2006.196.07:42:00.86#ibcon#first serial, iclass 14, count 0 2006.196.07:42:00.86#ibcon#enter sib2, iclass 14, count 0 2006.196.07:42:00.86#ibcon#flushed, iclass 14, count 0 2006.196.07:42:00.86#ibcon#about to write, iclass 14, count 0 2006.196.07:42:00.86#ibcon#wrote, iclass 14, count 0 2006.196.07:42:00.86#ibcon#about to read 3, iclass 14, count 0 2006.196.07:42:00.88#ibcon#read 3, iclass 14, count 0 2006.196.07:42:00.88#ibcon#about to read 4, iclass 14, count 0 2006.196.07:42:00.88#ibcon#read 4, iclass 14, count 0 2006.196.07:42:00.88#ibcon#about to read 5, iclass 14, count 0 2006.196.07:42:00.88#ibcon#read 5, iclass 14, count 0 2006.196.07:42:00.88#ibcon#about to read 6, iclass 14, count 0 2006.196.07:42:00.88#ibcon#read 6, iclass 14, count 0 2006.196.07:42:00.88#ibcon#end of sib2, iclass 14, count 0 2006.196.07:42:00.88#ibcon#*mode == 0, iclass 14, count 0 2006.196.07:42:00.88#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.196.07:42:00.88#ibcon#[28=FRQ=02,640.99\r\n] 2006.196.07:42:00.88#ibcon#*before write, iclass 14, count 0 2006.196.07:42:00.88#ibcon#enter sib2, iclass 14, count 0 2006.196.07:42:00.88#ibcon#flushed, iclass 14, count 0 2006.196.07:42:00.88#ibcon#about to write, iclass 14, count 0 2006.196.07:42:00.88#ibcon#wrote, iclass 14, count 0 2006.196.07:42:00.88#ibcon#about to read 3, iclass 14, count 0 2006.196.07:42:00.92#ibcon#read 3, iclass 14, count 0 2006.196.07:42:00.92#ibcon#about to read 4, iclass 14, count 0 2006.196.07:42:00.92#ibcon#read 4, iclass 14, count 0 2006.196.07:42:00.92#ibcon#about to read 5, iclass 14, count 0 2006.196.07:42:00.92#ibcon#read 5, iclass 14, count 0 2006.196.07:42:00.92#ibcon#about to read 6, iclass 14, count 0 2006.196.07:42:00.92#ibcon#read 6, iclass 14, count 0 2006.196.07:42:00.92#ibcon#end of sib2, iclass 14, count 0 2006.196.07:42:00.92#ibcon#*after write, iclass 14, count 0 2006.196.07:42:00.92#ibcon#*before return 0, iclass 14, count 0 2006.196.07:42:00.92#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.196.07:42:00.92#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.196.07:42:00.92#ibcon#about to clear, iclass 14 cls_cnt 0 2006.196.07:42:00.92#ibcon#cleared, iclass 14 cls_cnt 0 2006.196.07:42:00.92$vc4f8/vb=2,4 2006.196.07:42:00.92#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.196.07:42:00.92#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.196.07:42:00.92#ibcon#ireg 11 cls_cnt 2 2006.196.07:42:00.92#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.196.07:42:00.98#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.196.07:42:00.98#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.196.07:42:00.98#ibcon#enter wrdev, iclass 16, count 2 2006.196.07:42:00.98#ibcon#first serial, iclass 16, count 2 2006.196.07:42:00.98#ibcon#enter sib2, iclass 16, count 2 2006.196.07:42:00.98#ibcon#flushed, iclass 16, count 2 2006.196.07:42:00.98#ibcon#about to write, iclass 16, count 2 2006.196.07:42:00.98#ibcon#wrote, iclass 16, count 2 2006.196.07:42:00.98#ibcon#about to read 3, iclass 16, count 2 2006.196.07:42:01.00#ibcon#read 3, iclass 16, count 2 2006.196.07:42:01.00#ibcon#about to read 4, iclass 16, count 2 2006.196.07:42:01.00#ibcon#read 4, iclass 16, count 2 2006.196.07:42:01.00#ibcon#about to read 5, iclass 16, count 2 2006.196.07:42:01.00#ibcon#read 5, iclass 16, count 2 2006.196.07:42:01.00#ibcon#about to read 6, iclass 16, count 2 2006.196.07:42:01.00#ibcon#read 6, iclass 16, count 2 2006.196.07:42:01.00#ibcon#end of sib2, iclass 16, count 2 2006.196.07:42:01.00#ibcon#*mode == 0, iclass 16, count 2 2006.196.07:42:01.00#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.196.07:42:01.00#ibcon#[27=AT02-04\r\n] 2006.196.07:42:01.00#ibcon#*before write, iclass 16, count 2 2006.196.07:42:01.00#ibcon#enter sib2, iclass 16, count 2 2006.196.07:42:01.00#ibcon#flushed, iclass 16, count 2 2006.196.07:42:01.00#ibcon#about to write, iclass 16, count 2 2006.196.07:42:01.00#ibcon#wrote, iclass 16, count 2 2006.196.07:42:01.00#ibcon#about to read 3, iclass 16, count 2 2006.196.07:42:01.03#ibcon#read 3, iclass 16, count 2 2006.196.07:42:01.03#ibcon#about to read 4, iclass 16, count 2 2006.196.07:42:01.03#ibcon#read 4, iclass 16, count 2 2006.196.07:42:01.03#ibcon#about to read 5, iclass 16, count 2 2006.196.07:42:01.03#ibcon#read 5, iclass 16, count 2 2006.196.07:42:01.03#ibcon#about to read 6, iclass 16, count 2 2006.196.07:42:01.03#ibcon#read 6, iclass 16, count 2 2006.196.07:42:01.03#ibcon#end of sib2, iclass 16, count 2 2006.196.07:42:01.03#ibcon#*after write, iclass 16, count 2 2006.196.07:42:01.03#ibcon#*before return 0, iclass 16, count 2 2006.196.07:42:01.03#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.196.07:42:01.03#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.196.07:42:01.03#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.196.07:42:01.03#ibcon#ireg 7 cls_cnt 0 2006.196.07:42:01.03#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.196.07:42:01.15#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.196.07:42:01.15#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.196.07:42:01.15#ibcon#enter wrdev, iclass 16, count 0 2006.196.07:42:01.15#ibcon#first serial, iclass 16, count 0 2006.196.07:42:01.15#ibcon#enter sib2, iclass 16, count 0 2006.196.07:42:01.15#ibcon#flushed, iclass 16, count 0 2006.196.07:42:01.15#ibcon#about to write, iclass 16, count 0 2006.196.07:42:01.15#ibcon#wrote, iclass 16, count 0 2006.196.07:42:01.15#ibcon#about to read 3, iclass 16, count 0 2006.196.07:42:01.17#ibcon#read 3, iclass 16, count 0 2006.196.07:42:01.17#ibcon#about to read 4, iclass 16, count 0 2006.196.07:42:01.17#ibcon#read 4, iclass 16, count 0 2006.196.07:42:01.17#ibcon#about to read 5, iclass 16, count 0 2006.196.07:42:01.17#ibcon#read 5, iclass 16, count 0 2006.196.07:42:01.17#ibcon#about to read 6, iclass 16, count 0 2006.196.07:42:01.17#ibcon#read 6, iclass 16, count 0 2006.196.07:42:01.17#ibcon#end of sib2, iclass 16, count 0 2006.196.07:42:01.17#ibcon#*mode == 0, iclass 16, count 0 2006.196.07:42:01.17#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.196.07:42:01.17#ibcon#[27=USB\r\n] 2006.196.07:42:01.17#ibcon#*before write, iclass 16, count 0 2006.196.07:42:01.17#ibcon#enter sib2, iclass 16, count 0 2006.196.07:42:01.17#ibcon#flushed, iclass 16, count 0 2006.196.07:42:01.17#ibcon#about to write, iclass 16, count 0 2006.196.07:42:01.17#ibcon#wrote, iclass 16, count 0 2006.196.07:42:01.17#ibcon#about to read 3, iclass 16, count 0 2006.196.07:42:01.20#ibcon#read 3, iclass 16, count 0 2006.196.07:42:01.20#ibcon#about to read 4, iclass 16, count 0 2006.196.07:42:01.20#ibcon#read 4, iclass 16, count 0 2006.196.07:42:01.20#ibcon#about to read 5, iclass 16, count 0 2006.196.07:42:01.20#ibcon#read 5, iclass 16, count 0 2006.196.07:42:01.20#ibcon#about to read 6, iclass 16, count 0 2006.196.07:42:01.20#ibcon#read 6, iclass 16, count 0 2006.196.07:42:01.20#ibcon#end of sib2, iclass 16, count 0 2006.196.07:42:01.20#ibcon#*after write, iclass 16, count 0 2006.196.07:42:01.20#ibcon#*before return 0, iclass 16, count 0 2006.196.07:42:01.20#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.196.07:42:01.20#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.196.07:42:01.20#ibcon#about to clear, iclass 16 cls_cnt 0 2006.196.07:42:01.20#ibcon#cleared, iclass 16 cls_cnt 0 2006.196.07:42:01.20$vc4f8/vblo=3,656.99 2006.196.07:42:01.20#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.196.07:42:01.20#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.196.07:42:01.20#ibcon#ireg 17 cls_cnt 0 2006.196.07:42:01.20#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.196.07:42:01.20#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.196.07:42:01.20#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.196.07:42:01.20#ibcon#enter wrdev, iclass 18, count 0 2006.196.07:42:01.20#ibcon#first serial, iclass 18, count 0 2006.196.07:42:01.20#ibcon#enter sib2, iclass 18, count 0 2006.196.07:42:01.20#ibcon#flushed, iclass 18, count 0 2006.196.07:42:01.20#ibcon#about to write, iclass 18, count 0 2006.196.07:42:01.20#ibcon#wrote, iclass 18, count 0 2006.196.07:42:01.20#ibcon#about to read 3, iclass 18, count 0 2006.196.07:42:01.22#ibcon#read 3, iclass 18, count 0 2006.196.07:42:01.22#ibcon#about to read 4, iclass 18, count 0 2006.196.07:42:01.22#ibcon#read 4, iclass 18, count 0 2006.196.07:42:01.22#ibcon#about to read 5, iclass 18, count 0 2006.196.07:42:01.22#ibcon#read 5, iclass 18, count 0 2006.196.07:42:01.22#ibcon#about to read 6, iclass 18, count 0 2006.196.07:42:01.22#ibcon#read 6, iclass 18, count 0 2006.196.07:42:01.22#ibcon#end of sib2, iclass 18, count 0 2006.196.07:42:01.22#ibcon#*mode == 0, iclass 18, count 0 2006.196.07:42:01.22#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.196.07:42:01.22#ibcon#[28=FRQ=03,656.99\r\n] 2006.196.07:42:01.22#ibcon#*before write, iclass 18, count 0 2006.196.07:42:01.22#ibcon#enter sib2, iclass 18, count 0 2006.196.07:42:01.22#ibcon#flushed, iclass 18, count 0 2006.196.07:42:01.22#ibcon#about to write, iclass 18, count 0 2006.196.07:42:01.22#ibcon#wrote, iclass 18, count 0 2006.196.07:42:01.22#ibcon#about to read 3, iclass 18, count 0 2006.196.07:42:01.26#ibcon#read 3, iclass 18, count 0 2006.196.07:42:01.26#ibcon#about to read 4, iclass 18, count 0 2006.196.07:42:01.26#ibcon#read 4, iclass 18, count 0 2006.196.07:42:01.26#ibcon#about to read 5, iclass 18, count 0 2006.196.07:42:01.26#ibcon#read 5, iclass 18, count 0 2006.196.07:42:01.26#ibcon#about to read 6, iclass 18, count 0 2006.196.07:42:01.26#ibcon#read 6, iclass 18, count 0 2006.196.07:42:01.26#ibcon#end of sib2, iclass 18, count 0 2006.196.07:42:01.26#ibcon#*after write, iclass 18, count 0 2006.196.07:42:01.26#ibcon#*before return 0, iclass 18, count 0 2006.196.07:42:01.26#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.196.07:42:01.26#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.196.07:42:01.26#ibcon#about to clear, iclass 18 cls_cnt 0 2006.196.07:42:01.26#ibcon#cleared, iclass 18 cls_cnt 0 2006.196.07:42:01.26$vc4f8/vb=3,4 2006.196.07:42:01.26#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.196.07:42:01.26#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.196.07:42:01.26#ibcon#ireg 11 cls_cnt 2 2006.196.07:42:01.26#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.196.07:42:01.32#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.196.07:42:01.32#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.196.07:42:01.32#ibcon#enter wrdev, iclass 20, count 2 2006.196.07:42:01.32#ibcon#first serial, iclass 20, count 2 2006.196.07:42:01.32#ibcon#enter sib2, iclass 20, count 2 2006.196.07:42:01.32#ibcon#flushed, iclass 20, count 2 2006.196.07:42:01.32#ibcon#about to write, iclass 20, count 2 2006.196.07:42:01.32#ibcon#wrote, iclass 20, count 2 2006.196.07:42:01.32#ibcon#about to read 3, iclass 20, count 2 2006.196.07:42:01.34#ibcon#read 3, iclass 20, count 2 2006.196.07:42:01.34#ibcon#about to read 4, iclass 20, count 2 2006.196.07:42:01.34#ibcon#read 4, iclass 20, count 2 2006.196.07:42:01.34#ibcon#about to read 5, iclass 20, count 2 2006.196.07:42:01.34#ibcon#read 5, iclass 20, count 2 2006.196.07:42:01.34#ibcon#about to read 6, iclass 20, count 2 2006.196.07:42:01.34#ibcon#read 6, iclass 20, count 2 2006.196.07:42:01.34#ibcon#end of sib2, iclass 20, count 2 2006.196.07:42:01.34#ibcon#*mode == 0, iclass 20, count 2 2006.196.07:42:01.34#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.196.07:42:01.34#ibcon#[27=AT03-04\r\n] 2006.196.07:42:01.34#ibcon#*before write, iclass 20, count 2 2006.196.07:42:01.34#ibcon#enter sib2, iclass 20, count 2 2006.196.07:42:01.34#ibcon#flushed, iclass 20, count 2 2006.196.07:42:01.34#ibcon#about to write, iclass 20, count 2 2006.196.07:42:01.34#ibcon#wrote, iclass 20, count 2 2006.196.07:42:01.34#ibcon#about to read 3, iclass 20, count 2 2006.196.07:42:01.37#ibcon#read 3, iclass 20, count 2 2006.196.07:42:01.37#ibcon#about to read 4, iclass 20, count 2 2006.196.07:42:01.37#ibcon#read 4, iclass 20, count 2 2006.196.07:42:01.37#ibcon#about to read 5, iclass 20, count 2 2006.196.07:42:01.37#ibcon#read 5, iclass 20, count 2 2006.196.07:42:01.37#ibcon#about to read 6, iclass 20, count 2 2006.196.07:42:01.37#ibcon#read 6, iclass 20, count 2 2006.196.07:42:01.37#ibcon#end of sib2, iclass 20, count 2 2006.196.07:42:01.37#ibcon#*after write, iclass 20, count 2 2006.196.07:42:01.37#ibcon#*before return 0, iclass 20, count 2 2006.196.07:42:01.37#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.196.07:42:01.37#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.196.07:42:01.37#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.196.07:42:01.37#ibcon#ireg 7 cls_cnt 0 2006.196.07:42:01.37#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.196.07:42:01.49#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.196.07:42:01.49#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.196.07:42:01.49#ibcon#enter wrdev, iclass 20, count 0 2006.196.07:42:01.49#ibcon#first serial, iclass 20, count 0 2006.196.07:42:01.49#ibcon#enter sib2, iclass 20, count 0 2006.196.07:42:01.49#ibcon#flushed, iclass 20, count 0 2006.196.07:42:01.49#ibcon#about to write, iclass 20, count 0 2006.196.07:42:01.49#ibcon#wrote, iclass 20, count 0 2006.196.07:42:01.49#ibcon#about to read 3, iclass 20, count 0 2006.196.07:42:01.51#ibcon#read 3, iclass 20, count 0 2006.196.07:42:01.51#ibcon#about to read 4, iclass 20, count 0 2006.196.07:42:01.51#ibcon#read 4, iclass 20, count 0 2006.196.07:42:01.51#ibcon#about to read 5, iclass 20, count 0 2006.196.07:42:01.51#ibcon#read 5, iclass 20, count 0 2006.196.07:42:01.51#ibcon#about to read 6, iclass 20, count 0 2006.196.07:42:01.51#ibcon#read 6, iclass 20, count 0 2006.196.07:42:01.51#ibcon#end of sib2, iclass 20, count 0 2006.196.07:42:01.51#ibcon#*mode == 0, iclass 20, count 0 2006.196.07:42:01.51#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.196.07:42:01.51#ibcon#[27=USB\r\n] 2006.196.07:42:01.51#ibcon#*before write, iclass 20, count 0 2006.196.07:42:01.51#ibcon#enter sib2, iclass 20, count 0 2006.196.07:42:01.51#ibcon#flushed, iclass 20, count 0 2006.196.07:42:01.51#ibcon#about to write, iclass 20, count 0 2006.196.07:42:01.51#ibcon#wrote, iclass 20, count 0 2006.196.07:42:01.51#ibcon#about to read 3, iclass 20, count 0 2006.196.07:42:01.54#ibcon#read 3, iclass 20, count 0 2006.196.07:42:01.54#ibcon#about to read 4, iclass 20, count 0 2006.196.07:42:01.54#ibcon#read 4, iclass 20, count 0 2006.196.07:42:01.54#ibcon#about to read 5, iclass 20, count 0 2006.196.07:42:01.54#ibcon#read 5, iclass 20, count 0 2006.196.07:42:01.54#ibcon#about to read 6, iclass 20, count 0 2006.196.07:42:01.54#ibcon#read 6, iclass 20, count 0 2006.196.07:42:01.54#ibcon#end of sib2, iclass 20, count 0 2006.196.07:42:01.54#ibcon#*after write, iclass 20, count 0 2006.196.07:42:01.54#ibcon#*before return 0, iclass 20, count 0 2006.196.07:42:01.54#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.196.07:42:01.54#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.196.07:42:01.54#ibcon#about to clear, iclass 20 cls_cnt 0 2006.196.07:42:01.54#ibcon#cleared, iclass 20 cls_cnt 0 2006.196.07:42:01.54$vc4f8/vblo=4,712.99 2006.196.07:42:01.54#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.196.07:42:01.54#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.196.07:42:01.54#ibcon#ireg 17 cls_cnt 0 2006.196.07:42:01.54#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.196.07:42:01.54#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.196.07:42:01.54#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.196.07:42:01.54#ibcon#enter wrdev, iclass 22, count 0 2006.196.07:42:01.54#ibcon#first serial, iclass 22, count 0 2006.196.07:42:01.54#ibcon#enter sib2, iclass 22, count 0 2006.196.07:42:01.54#ibcon#flushed, iclass 22, count 0 2006.196.07:42:01.54#ibcon#about to write, iclass 22, count 0 2006.196.07:42:01.54#ibcon#wrote, iclass 22, count 0 2006.196.07:42:01.54#ibcon#about to read 3, iclass 22, count 0 2006.196.07:42:01.56#ibcon#read 3, iclass 22, count 0 2006.196.07:42:01.56#ibcon#about to read 4, iclass 22, count 0 2006.196.07:42:01.56#ibcon#read 4, iclass 22, count 0 2006.196.07:42:01.56#ibcon#about to read 5, iclass 22, count 0 2006.196.07:42:01.56#ibcon#read 5, iclass 22, count 0 2006.196.07:42:01.56#ibcon#about to read 6, iclass 22, count 0 2006.196.07:42:01.56#ibcon#read 6, iclass 22, count 0 2006.196.07:42:01.56#ibcon#end of sib2, iclass 22, count 0 2006.196.07:42:01.56#ibcon#*mode == 0, iclass 22, count 0 2006.196.07:42:01.56#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.196.07:42:01.56#ibcon#[28=FRQ=04,712.99\r\n] 2006.196.07:42:01.56#ibcon#*before write, iclass 22, count 0 2006.196.07:42:01.56#ibcon#enter sib2, iclass 22, count 0 2006.196.07:42:01.56#ibcon#flushed, iclass 22, count 0 2006.196.07:42:01.56#ibcon#about to write, iclass 22, count 0 2006.196.07:42:01.56#ibcon#wrote, iclass 22, count 0 2006.196.07:42:01.56#ibcon#about to read 3, iclass 22, count 0 2006.196.07:42:01.60#ibcon#read 3, iclass 22, count 0 2006.196.07:42:01.60#ibcon#about to read 4, iclass 22, count 0 2006.196.07:42:01.60#ibcon#read 4, iclass 22, count 0 2006.196.07:42:01.60#ibcon#about to read 5, iclass 22, count 0 2006.196.07:42:01.60#ibcon#read 5, iclass 22, count 0 2006.196.07:42:01.60#ibcon#about to read 6, iclass 22, count 0 2006.196.07:42:01.60#ibcon#read 6, iclass 22, count 0 2006.196.07:42:01.60#ibcon#end of sib2, iclass 22, count 0 2006.196.07:42:01.60#ibcon#*after write, iclass 22, count 0 2006.196.07:42:01.60#ibcon#*before return 0, iclass 22, count 0 2006.196.07:42:01.60#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.196.07:42:01.60#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.196.07:42:01.60#ibcon#about to clear, iclass 22 cls_cnt 0 2006.196.07:42:01.60#ibcon#cleared, iclass 22 cls_cnt 0 2006.196.07:42:01.60$vc4f8/vb=4,4 2006.196.07:42:01.60#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.196.07:42:01.60#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.196.07:42:01.60#ibcon#ireg 11 cls_cnt 2 2006.196.07:42:01.60#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.196.07:42:01.66#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.196.07:42:01.66#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.196.07:42:01.66#ibcon#enter wrdev, iclass 24, count 2 2006.196.07:42:01.66#ibcon#first serial, iclass 24, count 2 2006.196.07:42:01.66#ibcon#enter sib2, iclass 24, count 2 2006.196.07:42:01.66#ibcon#flushed, iclass 24, count 2 2006.196.07:42:01.66#ibcon#about to write, iclass 24, count 2 2006.196.07:42:01.66#ibcon#wrote, iclass 24, count 2 2006.196.07:42:01.66#ibcon#about to read 3, iclass 24, count 2 2006.196.07:42:01.68#ibcon#read 3, iclass 24, count 2 2006.196.07:42:01.68#ibcon#about to read 4, iclass 24, count 2 2006.196.07:42:01.68#ibcon#read 4, iclass 24, count 2 2006.196.07:42:01.68#ibcon#about to read 5, iclass 24, count 2 2006.196.07:42:01.68#ibcon#read 5, iclass 24, count 2 2006.196.07:42:01.68#ibcon#about to read 6, iclass 24, count 2 2006.196.07:42:01.68#ibcon#read 6, iclass 24, count 2 2006.196.07:42:01.68#ibcon#end of sib2, iclass 24, count 2 2006.196.07:42:01.68#ibcon#*mode == 0, iclass 24, count 2 2006.196.07:42:01.68#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.196.07:42:01.68#ibcon#[27=AT04-04\r\n] 2006.196.07:42:01.68#ibcon#*before write, iclass 24, count 2 2006.196.07:42:01.68#ibcon#enter sib2, iclass 24, count 2 2006.196.07:42:01.68#ibcon#flushed, iclass 24, count 2 2006.196.07:42:01.68#ibcon#about to write, iclass 24, count 2 2006.196.07:42:01.68#ibcon#wrote, iclass 24, count 2 2006.196.07:42:01.68#ibcon#about to read 3, iclass 24, count 2 2006.196.07:42:01.71#ibcon#read 3, iclass 24, count 2 2006.196.07:42:01.71#ibcon#about to read 4, iclass 24, count 2 2006.196.07:42:01.71#ibcon#read 4, iclass 24, count 2 2006.196.07:42:01.71#ibcon#about to read 5, iclass 24, count 2 2006.196.07:42:01.71#ibcon#read 5, iclass 24, count 2 2006.196.07:42:01.71#ibcon#about to read 6, iclass 24, count 2 2006.196.07:42:01.71#ibcon#read 6, iclass 24, count 2 2006.196.07:42:01.71#ibcon#end of sib2, iclass 24, count 2 2006.196.07:42:01.71#ibcon#*after write, iclass 24, count 2 2006.196.07:42:01.71#ibcon#*before return 0, iclass 24, count 2 2006.196.07:42:01.71#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.196.07:42:01.71#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.196.07:42:01.71#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.196.07:42:01.71#ibcon#ireg 7 cls_cnt 0 2006.196.07:42:01.71#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.196.07:42:01.83#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.196.07:42:01.83#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.196.07:42:01.83#ibcon#enter wrdev, iclass 24, count 0 2006.196.07:42:01.83#ibcon#first serial, iclass 24, count 0 2006.196.07:42:01.83#ibcon#enter sib2, iclass 24, count 0 2006.196.07:42:01.83#ibcon#flushed, iclass 24, count 0 2006.196.07:42:01.83#ibcon#about to write, iclass 24, count 0 2006.196.07:42:01.83#ibcon#wrote, iclass 24, count 0 2006.196.07:42:01.83#ibcon#about to read 3, iclass 24, count 0 2006.196.07:42:01.85#ibcon#read 3, iclass 24, count 0 2006.196.07:42:01.85#ibcon#about to read 4, iclass 24, count 0 2006.196.07:42:01.85#ibcon#read 4, iclass 24, count 0 2006.196.07:42:01.85#ibcon#about to read 5, iclass 24, count 0 2006.196.07:42:01.85#ibcon#read 5, iclass 24, count 0 2006.196.07:42:01.85#ibcon#about to read 6, iclass 24, count 0 2006.196.07:42:01.85#ibcon#read 6, iclass 24, count 0 2006.196.07:42:01.85#ibcon#end of sib2, iclass 24, count 0 2006.196.07:42:01.85#ibcon#*mode == 0, iclass 24, count 0 2006.196.07:42:01.85#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.196.07:42:01.85#ibcon#[27=USB\r\n] 2006.196.07:42:01.85#ibcon#*before write, iclass 24, count 0 2006.196.07:42:01.85#ibcon#enter sib2, iclass 24, count 0 2006.196.07:42:01.85#ibcon#flushed, iclass 24, count 0 2006.196.07:42:01.85#ibcon#about to write, iclass 24, count 0 2006.196.07:42:01.85#ibcon#wrote, iclass 24, count 0 2006.196.07:42:01.85#ibcon#about to read 3, iclass 24, count 0 2006.196.07:42:01.88#ibcon#read 3, iclass 24, count 0 2006.196.07:42:01.88#ibcon#about to read 4, iclass 24, count 0 2006.196.07:42:01.88#ibcon#read 4, iclass 24, count 0 2006.196.07:42:01.88#ibcon#about to read 5, iclass 24, count 0 2006.196.07:42:01.88#ibcon#read 5, iclass 24, count 0 2006.196.07:42:01.88#ibcon#about to read 6, iclass 24, count 0 2006.196.07:42:01.88#ibcon#read 6, iclass 24, count 0 2006.196.07:42:01.88#ibcon#end of sib2, iclass 24, count 0 2006.196.07:42:01.88#ibcon#*after write, iclass 24, count 0 2006.196.07:42:01.88#ibcon#*before return 0, iclass 24, count 0 2006.196.07:42:01.88#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.196.07:42:01.88#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.196.07:42:01.88#ibcon#about to clear, iclass 24 cls_cnt 0 2006.196.07:42:01.88#ibcon#cleared, iclass 24 cls_cnt 0 2006.196.07:42:01.88$vc4f8/vblo=5,744.99 2006.196.07:42:01.88#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.196.07:42:01.88#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.196.07:42:01.88#ibcon#ireg 17 cls_cnt 0 2006.196.07:42:01.88#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.196.07:42:01.88#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.196.07:42:01.88#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.196.07:42:01.88#ibcon#enter wrdev, iclass 26, count 0 2006.196.07:42:01.88#ibcon#first serial, iclass 26, count 0 2006.196.07:42:01.88#ibcon#enter sib2, iclass 26, count 0 2006.196.07:42:01.88#ibcon#flushed, iclass 26, count 0 2006.196.07:42:01.88#ibcon#about to write, iclass 26, count 0 2006.196.07:42:01.88#ibcon#wrote, iclass 26, count 0 2006.196.07:42:01.88#ibcon#about to read 3, iclass 26, count 0 2006.196.07:42:01.90#ibcon#read 3, iclass 26, count 0 2006.196.07:42:01.90#ibcon#about to read 4, iclass 26, count 0 2006.196.07:42:01.90#ibcon#read 4, iclass 26, count 0 2006.196.07:42:01.90#ibcon#about to read 5, iclass 26, count 0 2006.196.07:42:01.90#ibcon#read 5, iclass 26, count 0 2006.196.07:42:01.90#ibcon#about to read 6, iclass 26, count 0 2006.196.07:42:01.90#ibcon#read 6, iclass 26, count 0 2006.196.07:42:01.90#ibcon#end of sib2, iclass 26, count 0 2006.196.07:42:01.90#ibcon#*mode == 0, iclass 26, count 0 2006.196.07:42:01.90#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.196.07:42:01.90#ibcon#[28=FRQ=05,744.99\r\n] 2006.196.07:42:01.90#ibcon#*before write, iclass 26, count 0 2006.196.07:42:01.90#ibcon#enter sib2, iclass 26, count 0 2006.196.07:42:01.90#ibcon#flushed, iclass 26, count 0 2006.196.07:42:01.90#ibcon#about to write, iclass 26, count 0 2006.196.07:42:01.90#ibcon#wrote, iclass 26, count 0 2006.196.07:42:01.90#ibcon#about to read 3, iclass 26, count 0 2006.196.07:42:01.94#ibcon#read 3, iclass 26, count 0 2006.196.07:42:01.94#ibcon#about to read 4, iclass 26, count 0 2006.196.07:42:01.94#ibcon#read 4, iclass 26, count 0 2006.196.07:42:01.94#ibcon#about to read 5, iclass 26, count 0 2006.196.07:42:01.94#ibcon#read 5, iclass 26, count 0 2006.196.07:42:01.94#ibcon#about to read 6, iclass 26, count 0 2006.196.07:42:01.94#ibcon#read 6, iclass 26, count 0 2006.196.07:42:01.94#ibcon#end of sib2, iclass 26, count 0 2006.196.07:42:01.94#ibcon#*after write, iclass 26, count 0 2006.196.07:42:01.94#ibcon#*before return 0, iclass 26, count 0 2006.196.07:42:01.94#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.196.07:42:01.94#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.196.07:42:01.94#ibcon#about to clear, iclass 26 cls_cnt 0 2006.196.07:42:01.94#ibcon#cleared, iclass 26 cls_cnt 0 2006.196.07:42:01.94$vc4f8/vb=5,4 2006.196.07:42:01.94#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.196.07:42:01.94#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.196.07:42:01.94#ibcon#ireg 11 cls_cnt 2 2006.196.07:42:01.94#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.196.07:42:02.00#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.196.07:42:02.00#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.196.07:42:02.00#ibcon#enter wrdev, iclass 28, count 2 2006.196.07:42:02.00#ibcon#first serial, iclass 28, count 2 2006.196.07:42:02.00#ibcon#enter sib2, iclass 28, count 2 2006.196.07:42:02.00#ibcon#flushed, iclass 28, count 2 2006.196.07:42:02.00#ibcon#about to write, iclass 28, count 2 2006.196.07:42:02.00#ibcon#wrote, iclass 28, count 2 2006.196.07:42:02.00#ibcon#about to read 3, iclass 28, count 2 2006.196.07:42:02.02#ibcon#read 3, iclass 28, count 2 2006.196.07:42:02.02#ibcon#about to read 4, iclass 28, count 2 2006.196.07:42:02.02#ibcon#read 4, iclass 28, count 2 2006.196.07:42:02.02#ibcon#about to read 5, iclass 28, count 2 2006.196.07:42:02.02#ibcon#read 5, iclass 28, count 2 2006.196.07:42:02.02#ibcon#about to read 6, iclass 28, count 2 2006.196.07:42:02.02#ibcon#read 6, iclass 28, count 2 2006.196.07:42:02.02#ibcon#end of sib2, iclass 28, count 2 2006.196.07:42:02.02#ibcon#*mode == 0, iclass 28, count 2 2006.196.07:42:02.02#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.196.07:42:02.02#ibcon#[27=AT05-04\r\n] 2006.196.07:42:02.02#ibcon#*before write, iclass 28, count 2 2006.196.07:42:02.02#ibcon#enter sib2, iclass 28, count 2 2006.196.07:42:02.02#ibcon#flushed, iclass 28, count 2 2006.196.07:42:02.02#ibcon#about to write, iclass 28, count 2 2006.196.07:42:02.02#ibcon#wrote, iclass 28, count 2 2006.196.07:42:02.02#ibcon#about to read 3, iclass 28, count 2 2006.196.07:42:02.05#ibcon#read 3, iclass 28, count 2 2006.196.07:42:02.05#ibcon#about to read 4, iclass 28, count 2 2006.196.07:42:02.05#ibcon#read 4, iclass 28, count 2 2006.196.07:42:02.05#ibcon#about to read 5, iclass 28, count 2 2006.196.07:42:02.05#ibcon#read 5, iclass 28, count 2 2006.196.07:42:02.05#ibcon#about to read 6, iclass 28, count 2 2006.196.07:42:02.05#ibcon#read 6, iclass 28, count 2 2006.196.07:42:02.05#ibcon#end of sib2, iclass 28, count 2 2006.196.07:42:02.05#ibcon#*after write, iclass 28, count 2 2006.196.07:42:02.05#ibcon#*before return 0, iclass 28, count 2 2006.196.07:42:02.05#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.196.07:42:02.05#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.196.07:42:02.05#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.196.07:42:02.05#ibcon#ireg 7 cls_cnt 0 2006.196.07:42:02.05#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.196.07:42:02.17#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.196.07:42:02.17#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.196.07:42:02.17#ibcon#enter wrdev, iclass 28, count 0 2006.196.07:42:02.17#ibcon#first serial, iclass 28, count 0 2006.196.07:42:02.17#ibcon#enter sib2, iclass 28, count 0 2006.196.07:42:02.17#ibcon#flushed, iclass 28, count 0 2006.196.07:42:02.17#ibcon#about to write, iclass 28, count 0 2006.196.07:42:02.17#ibcon#wrote, iclass 28, count 0 2006.196.07:42:02.17#ibcon#about to read 3, iclass 28, count 0 2006.196.07:42:02.20#ibcon#read 3, iclass 28, count 0 2006.196.07:42:02.20#ibcon#about to read 4, iclass 28, count 0 2006.196.07:42:02.20#ibcon#read 4, iclass 28, count 0 2006.196.07:42:02.20#ibcon#about to read 5, iclass 28, count 0 2006.196.07:42:02.20#ibcon#read 5, iclass 28, count 0 2006.196.07:42:02.20#ibcon#about to read 6, iclass 28, count 0 2006.196.07:42:02.20#ibcon#read 6, iclass 28, count 0 2006.196.07:42:02.20#ibcon#end of sib2, iclass 28, count 0 2006.196.07:42:02.20#ibcon#*mode == 0, iclass 28, count 0 2006.196.07:42:02.20#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.196.07:42:02.20#ibcon#[27=USB\r\n] 2006.196.07:42:02.20#ibcon#*before write, iclass 28, count 0 2006.196.07:42:02.20#ibcon#enter sib2, iclass 28, count 0 2006.196.07:42:02.20#ibcon#flushed, iclass 28, count 0 2006.196.07:42:02.20#ibcon#about to write, iclass 28, count 0 2006.196.07:42:02.20#ibcon#wrote, iclass 28, count 0 2006.196.07:42:02.20#ibcon#about to read 3, iclass 28, count 0 2006.196.07:42:02.23#ibcon#read 3, iclass 28, count 0 2006.196.07:42:02.23#ibcon#about to read 4, iclass 28, count 0 2006.196.07:42:02.23#ibcon#read 4, iclass 28, count 0 2006.196.07:42:02.23#ibcon#about to read 5, iclass 28, count 0 2006.196.07:42:02.23#ibcon#read 5, iclass 28, count 0 2006.196.07:42:02.23#ibcon#about to read 6, iclass 28, count 0 2006.196.07:42:02.23#ibcon#read 6, iclass 28, count 0 2006.196.07:42:02.23#ibcon#end of sib2, iclass 28, count 0 2006.196.07:42:02.23#ibcon#*after write, iclass 28, count 0 2006.196.07:42:02.23#ibcon#*before return 0, iclass 28, count 0 2006.196.07:42:02.23#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.196.07:42:02.23#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.196.07:42:02.23#ibcon#about to clear, iclass 28 cls_cnt 0 2006.196.07:42:02.23#ibcon#cleared, iclass 28 cls_cnt 0 2006.196.07:42:02.23$vc4f8/vblo=6,752.99 2006.196.07:42:02.23#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.196.07:42:02.23#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.196.07:42:02.23#ibcon#ireg 17 cls_cnt 0 2006.196.07:42:02.23#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.196.07:42:02.23#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.196.07:42:02.23#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.196.07:42:02.23#ibcon#enter wrdev, iclass 30, count 0 2006.196.07:42:02.23#ibcon#first serial, iclass 30, count 0 2006.196.07:42:02.23#ibcon#enter sib2, iclass 30, count 0 2006.196.07:42:02.23#ibcon#flushed, iclass 30, count 0 2006.196.07:42:02.23#ibcon#about to write, iclass 30, count 0 2006.196.07:42:02.23#ibcon#wrote, iclass 30, count 0 2006.196.07:42:02.23#ibcon#about to read 3, iclass 30, count 0 2006.196.07:42:02.25#ibcon#read 3, iclass 30, count 0 2006.196.07:42:02.25#ibcon#about to read 4, iclass 30, count 0 2006.196.07:42:02.25#ibcon#read 4, iclass 30, count 0 2006.196.07:42:02.25#ibcon#about to read 5, iclass 30, count 0 2006.196.07:42:02.25#ibcon#read 5, iclass 30, count 0 2006.196.07:42:02.25#ibcon#about to read 6, iclass 30, count 0 2006.196.07:42:02.25#ibcon#read 6, iclass 30, count 0 2006.196.07:42:02.25#ibcon#end of sib2, iclass 30, count 0 2006.196.07:42:02.25#ibcon#*mode == 0, iclass 30, count 0 2006.196.07:42:02.25#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.196.07:42:02.25#ibcon#[28=FRQ=06,752.99\r\n] 2006.196.07:42:02.25#ibcon#*before write, iclass 30, count 0 2006.196.07:42:02.25#ibcon#enter sib2, iclass 30, count 0 2006.196.07:42:02.25#ibcon#flushed, iclass 30, count 0 2006.196.07:42:02.25#ibcon#about to write, iclass 30, count 0 2006.196.07:42:02.25#ibcon#wrote, iclass 30, count 0 2006.196.07:42:02.25#ibcon#about to read 3, iclass 30, count 0 2006.196.07:42:02.29#ibcon#read 3, iclass 30, count 0 2006.196.07:42:02.29#ibcon#about to read 4, iclass 30, count 0 2006.196.07:42:02.29#ibcon#read 4, iclass 30, count 0 2006.196.07:42:02.29#ibcon#about to read 5, iclass 30, count 0 2006.196.07:42:02.29#ibcon#read 5, iclass 30, count 0 2006.196.07:42:02.29#ibcon#about to read 6, iclass 30, count 0 2006.196.07:42:02.29#ibcon#read 6, iclass 30, count 0 2006.196.07:42:02.29#ibcon#end of sib2, iclass 30, count 0 2006.196.07:42:02.29#ibcon#*after write, iclass 30, count 0 2006.196.07:42:02.29#ibcon#*before return 0, iclass 30, count 0 2006.196.07:42:02.29#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.196.07:42:02.29#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.196.07:42:02.29#ibcon#about to clear, iclass 30 cls_cnt 0 2006.196.07:42:02.29#ibcon#cleared, iclass 30 cls_cnt 0 2006.196.07:42:02.29$vc4f8/vb=6,4 2006.196.07:42:02.29#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.196.07:42:02.29#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.196.07:42:02.29#ibcon#ireg 11 cls_cnt 2 2006.196.07:42:02.29#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.196.07:42:02.35#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.196.07:42:02.35#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.196.07:42:02.35#ibcon#enter wrdev, iclass 32, count 2 2006.196.07:42:02.35#ibcon#first serial, iclass 32, count 2 2006.196.07:42:02.35#ibcon#enter sib2, iclass 32, count 2 2006.196.07:42:02.35#ibcon#flushed, iclass 32, count 2 2006.196.07:42:02.35#ibcon#about to write, iclass 32, count 2 2006.196.07:42:02.35#ibcon#wrote, iclass 32, count 2 2006.196.07:42:02.35#ibcon#about to read 3, iclass 32, count 2 2006.196.07:42:02.37#ibcon#read 3, iclass 32, count 2 2006.196.07:42:02.37#ibcon#about to read 4, iclass 32, count 2 2006.196.07:42:02.37#ibcon#read 4, iclass 32, count 2 2006.196.07:42:02.37#ibcon#about to read 5, iclass 32, count 2 2006.196.07:42:02.37#ibcon#read 5, iclass 32, count 2 2006.196.07:42:02.37#ibcon#about to read 6, iclass 32, count 2 2006.196.07:42:02.37#ibcon#read 6, iclass 32, count 2 2006.196.07:42:02.37#ibcon#end of sib2, iclass 32, count 2 2006.196.07:42:02.37#ibcon#*mode == 0, iclass 32, count 2 2006.196.07:42:02.37#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.196.07:42:02.37#ibcon#[27=AT06-04\r\n] 2006.196.07:42:02.37#ibcon#*before write, iclass 32, count 2 2006.196.07:42:02.37#ibcon#enter sib2, iclass 32, count 2 2006.196.07:42:02.37#ibcon#flushed, iclass 32, count 2 2006.196.07:42:02.37#ibcon#about to write, iclass 32, count 2 2006.196.07:42:02.37#ibcon#wrote, iclass 32, count 2 2006.196.07:42:02.37#ibcon#about to read 3, iclass 32, count 2 2006.196.07:42:02.40#ibcon#read 3, iclass 32, count 2 2006.196.07:42:02.40#ibcon#about to read 4, iclass 32, count 2 2006.196.07:42:02.40#ibcon#read 4, iclass 32, count 2 2006.196.07:42:02.40#ibcon#about to read 5, iclass 32, count 2 2006.196.07:42:02.40#ibcon#read 5, iclass 32, count 2 2006.196.07:42:02.40#ibcon#about to read 6, iclass 32, count 2 2006.196.07:42:02.40#ibcon#read 6, iclass 32, count 2 2006.196.07:42:02.40#ibcon#end of sib2, iclass 32, count 2 2006.196.07:42:02.40#ibcon#*after write, iclass 32, count 2 2006.196.07:42:02.40#ibcon#*before return 0, iclass 32, count 2 2006.196.07:42:02.40#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.196.07:42:02.40#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.196.07:42:02.40#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.196.07:42:02.40#ibcon#ireg 7 cls_cnt 0 2006.196.07:42:02.40#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.196.07:42:02.52#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.196.07:42:02.52#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.196.07:42:02.52#ibcon#enter wrdev, iclass 32, count 0 2006.196.07:42:02.52#ibcon#first serial, iclass 32, count 0 2006.196.07:42:02.52#ibcon#enter sib2, iclass 32, count 0 2006.196.07:42:02.52#ibcon#flushed, iclass 32, count 0 2006.196.07:42:02.52#ibcon#about to write, iclass 32, count 0 2006.196.07:42:02.52#ibcon#wrote, iclass 32, count 0 2006.196.07:42:02.52#ibcon#about to read 3, iclass 32, count 0 2006.196.07:42:02.54#ibcon#read 3, iclass 32, count 0 2006.196.07:42:02.54#ibcon#about to read 4, iclass 32, count 0 2006.196.07:42:02.54#ibcon#read 4, iclass 32, count 0 2006.196.07:42:02.54#ibcon#about to read 5, iclass 32, count 0 2006.196.07:42:02.54#ibcon#read 5, iclass 32, count 0 2006.196.07:42:02.54#ibcon#about to read 6, iclass 32, count 0 2006.196.07:42:02.54#ibcon#read 6, iclass 32, count 0 2006.196.07:42:02.54#ibcon#end of sib2, iclass 32, count 0 2006.196.07:42:02.54#ibcon#*mode == 0, iclass 32, count 0 2006.196.07:42:02.54#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.196.07:42:02.54#ibcon#[27=USB\r\n] 2006.196.07:42:02.54#ibcon#*before write, iclass 32, count 0 2006.196.07:42:02.54#ibcon#enter sib2, iclass 32, count 0 2006.196.07:42:02.54#ibcon#flushed, iclass 32, count 0 2006.196.07:42:02.54#ibcon#about to write, iclass 32, count 0 2006.196.07:42:02.54#ibcon#wrote, iclass 32, count 0 2006.196.07:42:02.54#ibcon#about to read 3, iclass 32, count 0 2006.196.07:42:02.57#ibcon#read 3, iclass 32, count 0 2006.196.07:42:02.57#ibcon#about to read 4, iclass 32, count 0 2006.196.07:42:02.57#ibcon#read 4, iclass 32, count 0 2006.196.07:42:02.57#ibcon#about to read 5, iclass 32, count 0 2006.196.07:42:02.57#ibcon#read 5, iclass 32, count 0 2006.196.07:42:02.57#ibcon#about to read 6, iclass 32, count 0 2006.196.07:42:02.57#ibcon#read 6, iclass 32, count 0 2006.196.07:42:02.57#ibcon#end of sib2, iclass 32, count 0 2006.196.07:42:02.57#ibcon#*after write, iclass 32, count 0 2006.196.07:42:02.57#ibcon#*before return 0, iclass 32, count 0 2006.196.07:42:02.57#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.196.07:42:02.57#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.196.07:42:02.57#ibcon#about to clear, iclass 32 cls_cnt 0 2006.196.07:42:02.57#ibcon#cleared, iclass 32 cls_cnt 0 2006.196.07:42:02.57$vc4f8/vabw=wide 2006.196.07:42:02.57#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.196.07:42:02.57#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.196.07:42:02.57#ibcon#ireg 8 cls_cnt 0 2006.196.07:42:02.57#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.196.07:42:02.57#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.196.07:42:02.57#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.196.07:42:02.57#ibcon#enter wrdev, iclass 34, count 0 2006.196.07:42:02.57#ibcon#first serial, iclass 34, count 0 2006.196.07:42:02.57#ibcon#enter sib2, iclass 34, count 0 2006.196.07:42:02.57#ibcon#flushed, iclass 34, count 0 2006.196.07:42:02.57#ibcon#about to write, iclass 34, count 0 2006.196.07:42:02.57#ibcon#wrote, iclass 34, count 0 2006.196.07:42:02.57#ibcon#about to read 3, iclass 34, count 0 2006.196.07:42:02.59#ibcon#read 3, iclass 34, count 0 2006.196.07:42:02.59#ibcon#about to read 4, iclass 34, count 0 2006.196.07:42:02.59#ibcon#read 4, iclass 34, count 0 2006.196.07:42:02.59#ibcon#about to read 5, iclass 34, count 0 2006.196.07:42:02.59#ibcon#read 5, iclass 34, count 0 2006.196.07:42:02.59#ibcon#about to read 6, iclass 34, count 0 2006.196.07:42:02.59#ibcon#read 6, iclass 34, count 0 2006.196.07:42:02.59#ibcon#end of sib2, iclass 34, count 0 2006.196.07:42:02.59#ibcon#*mode == 0, iclass 34, count 0 2006.196.07:42:02.59#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.196.07:42:02.59#ibcon#[25=BW32\r\n] 2006.196.07:42:02.59#ibcon#*before write, iclass 34, count 0 2006.196.07:42:02.59#ibcon#enter sib2, iclass 34, count 0 2006.196.07:42:02.59#ibcon#flushed, iclass 34, count 0 2006.196.07:42:02.59#ibcon#about to write, iclass 34, count 0 2006.196.07:42:02.59#ibcon#wrote, iclass 34, count 0 2006.196.07:42:02.59#ibcon#about to read 3, iclass 34, count 0 2006.196.07:42:02.62#ibcon#read 3, iclass 34, count 0 2006.196.07:42:02.62#ibcon#about to read 4, iclass 34, count 0 2006.196.07:42:02.62#ibcon#read 4, iclass 34, count 0 2006.196.07:42:02.62#ibcon#about to read 5, iclass 34, count 0 2006.196.07:42:02.62#ibcon#read 5, iclass 34, count 0 2006.196.07:42:02.62#ibcon#about to read 6, iclass 34, count 0 2006.196.07:42:02.62#ibcon#read 6, iclass 34, count 0 2006.196.07:42:02.62#ibcon#end of sib2, iclass 34, count 0 2006.196.07:42:02.62#ibcon#*after write, iclass 34, count 0 2006.196.07:42:02.62#ibcon#*before return 0, iclass 34, count 0 2006.196.07:42:02.62#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.196.07:42:02.62#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.196.07:42:02.62#ibcon#about to clear, iclass 34 cls_cnt 0 2006.196.07:42:02.62#ibcon#cleared, iclass 34 cls_cnt 0 2006.196.07:42:02.62$vc4f8/vbbw=wide 2006.196.07:42:02.62#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.196.07:42:02.62#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.196.07:42:02.62#ibcon#ireg 8 cls_cnt 0 2006.196.07:42:02.62#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.196.07:42:02.69#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.196.07:42:02.69#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.196.07:42:02.69#ibcon#enter wrdev, iclass 36, count 0 2006.196.07:42:02.69#ibcon#first serial, iclass 36, count 0 2006.196.07:42:02.69#ibcon#enter sib2, iclass 36, count 0 2006.196.07:42:02.69#ibcon#flushed, iclass 36, count 0 2006.196.07:42:02.69#ibcon#about to write, iclass 36, count 0 2006.196.07:42:02.69#ibcon#wrote, iclass 36, count 0 2006.196.07:42:02.69#ibcon#about to read 3, iclass 36, count 0 2006.196.07:42:02.71#ibcon#read 3, iclass 36, count 0 2006.196.07:42:02.71#ibcon#about to read 4, iclass 36, count 0 2006.196.07:42:02.71#ibcon#read 4, iclass 36, count 0 2006.196.07:42:02.71#ibcon#about to read 5, iclass 36, count 0 2006.196.07:42:02.71#ibcon#read 5, iclass 36, count 0 2006.196.07:42:02.71#ibcon#about to read 6, iclass 36, count 0 2006.196.07:42:02.71#ibcon#read 6, iclass 36, count 0 2006.196.07:42:02.71#ibcon#end of sib2, iclass 36, count 0 2006.196.07:42:02.71#ibcon#*mode == 0, iclass 36, count 0 2006.196.07:42:02.71#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.196.07:42:02.71#ibcon#[27=BW32\r\n] 2006.196.07:42:02.71#ibcon#*before write, iclass 36, count 0 2006.196.07:42:02.71#ibcon#enter sib2, iclass 36, count 0 2006.196.07:42:02.71#ibcon#flushed, iclass 36, count 0 2006.196.07:42:02.71#ibcon#about to write, iclass 36, count 0 2006.196.07:42:02.71#ibcon#wrote, iclass 36, count 0 2006.196.07:42:02.71#ibcon#about to read 3, iclass 36, count 0 2006.196.07:42:02.74#ibcon#read 3, iclass 36, count 0 2006.196.07:42:02.74#ibcon#about to read 4, iclass 36, count 0 2006.196.07:42:02.74#ibcon#read 4, iclass 36, count 0 2006.196.07:42:02.74#ibcon#about to read 5, iclass 36, count 0 2006.196.07:42:02.74#ibcon#read 5, iclass 36, count 0 2006.196.07:42:02.74#ibcon#about to read 6, iclass 36, count 0 2006.196.07:42:02.74#ibcon#read 6, iclass 36, count 0 2006.196.07:42:02.74#ibcon#end of sib2, iclass 36, count 0 2006.196.07:42:02.74#ibcon#*after write, iclass 36, count 0 2006.196.07:42:02.74#ibcon#*before return 0, iclass 36, count 0 2006.196.07:42:02.74#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.196.07:42:02.74#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.196.07:42:02.74#ibcon#about to clear, iclass 36 cls_cnt 0 2006.196.07:42:02.74#ibcon#cleared, iclass 36 cls_cnt 0 2006.196.07:42:02.74$4f8m12a/ifd4f 2006.196.07:42:02.74$ifd4f/lo= 2006.196.07:42:02.74$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.196.07:42:02.74$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.196.07:42:02.74$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.196.07:42:02.74$ifd4f/patch= 2006.196.07:42:02.74$ifd4f/patch=lo1,a1,a2,a3,a4 2006.196.07:42:02.74$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.196.07:42:02.74$ifd4f/patch=lo3,a5,a6,a7,a8 2006.196.07:42:02.74$4f8m12a/"form=m,16.000,1:2 2006.196.07:42:02.74$4f8m12a/"tpicd 2006.196.07:42:02.74$4f8m12a/echo=off 2006.196.07:42:02.74$4f8m12a/xlog=off 2006.196.07:42:02.74:!2006.196.07:43:00 2006.196.07:42:40.14#trakl#Source acquired 2006.196.07:42:42.14#flagr#flagr/antenna,acquired 2006.196.07:43:00.00:preob 2006.196.07:43:01.14/onsource/TRACKING 2006.196.07:43:01.14:!2006.196.07:43:10 2006.196.07:43:10.00:data_valid=on 2006.196.07:43:10.00:midob 2006.196.07:43:10.14/onsource/TRACKING 2006.196.07:43:10.14/wx/29.87,1004.0,87 2006.196.07:43:10.29/cable/+6.3356E-03 2006.196.07:43:11.38/va/01,08,usb,yes,31,32 2006.196.07:43:11.38/va/02,07,usb,yes,31,32 2006.196.07:43:11.38/va/03,06,usb,yes,33,33 2006.196.07:43:11.38/va/04,07,usb,yes,32,34 2006.196.07:43:11.38/va/05,07,usb,yes,33,35 2006.196.07:43:11.38/va/06,06,usb,yes,33,32 2006.196.07:43:11.38/va/07,06,usb,yes,33,33 2006.196.07:43:11.38/va/08,07,usb,yes,31,31 2006.196.07:43:11.61/valo/01,532.99,yes,locked 2006.196.07:43:11.61/valo/02,572.99,yes,locked 2006.196.07:43:11.61/valo/03,672.99,yes,locked 2006.196.07:43:11.61/valo/04,832.99,yes,locked 2006.196.07:43:11.61/valo/05,652.99,yes,locked 2006.196.07:43:11.61/valo/06,772.99,yes,locked 2006.196.07:43:11.61/valo/07,832.99,yes,locked 2006.196.07:43:11.61/valo/08,852.99,yes,locked 2006.196.07:43:12.70/vb/01,04,usb,yes,30,28 2006.196.07:43:12.70/vb/02,04,usb,yes,31,33 2006.196.07:43:12.70/vb/03,04,usb,yes,28,31 2006.196.07:43:12.70/vb/04,04,usb,yes,28,29 2006.196.07:43:12.70/vb/05,04,usb,yes,27,31 2006.196.07:43:12.70/vb/06,04,usb,yes,28,31 2006.196.07:43:12.70/vb/07,04,usb,yes,30,30 2006.196.07:43:12.70/vb/08,04,usb,yes,28,31 2006.196.07:43:12.94/vblo/01,632.99,yes,locked 2006.196.07:43:12.94/vblo/02,640.99,yes,locked 2006.196.07:43:12.94/vblo/03,656.99,yes,locked 2006.196.07:43:12.94/vblo/04,712.99,yes,locked 2006.196.07:43:12.94/vblo/05,744.99,yes,locked 2006.196.07:43:12.94/vblo/06,752.99,yes,locked 2006.196.07:43:12.94/vblo/07,734.99,yes,locked 2006.196.07:43:12.94/vblo/08,744.99,yes,locked 2006.196.07:43:13.09/vabw/8 2006.196.07:43:13.24/vbbw/8 2006.196.07:43:13.33/xfe/off,on,15.2 2006.196.07:43:13.72/ifatt/23,28,28,28 2006.196.07:43:14.06/fmout-gps/S +3.35E-07 2006.196.07:43:14.13:!2006.196.07:46:00 2006.196.07:46:00.00:data_valid=off 2006.196.07:46:00.00:postob 2006.196.07:46:00.15/cable/+6.3340E-03 2006.196.07:46:00.15/wx/29.78,1004.0,88 2006.196.07:46:01.07/fmout-gps/S +3.35E-07 2006.196.07:46:01.07:scan_name=196-0749,k06196,60 2006.196.07:46:01.07:source=0804+499,080839.67,495036.5,2000.0,cw 2006.196.07:46:02.14#flagr#flagr/antenna,new-source 2006.196.07:46:02.14:checkk5 2006.196.07:46:02.51/chk_autoobs//k5ts1/ autoobs is running! 2006.196.07:46:02.89/chk_autoobs//k5ts2/ autoobs is running! 2006.196.07:46:03.27/chk_autoobs//k5ts3/ autoobs is running! 2006.196.07:46:03.65/chk_autoobs//k5ts4/ autoobs is running! 2006.196.07:46:04.02/chk_obsdata//k5ts1/T1960743??a.dat file size is correct (nominal:1360MB, actual:1352MB). 2006.196.07:46:04.38/chk_obsdata//k5ts2/T1960743??b.dat file size is correct (nominal:1360MB, actual:1352MB). 2006.196.07:46:04.75/chk_obsdata//k5ts3/T1960743??c.dat file size is correct (nominal:1360MB, actual:1352MB). 2006.196.07:46:05.12/chk_obsdata//k5ts4/T1960743??d.dat file size is correct (nominal:1360MB, actual:1352MB). 2006.196.07:46:05.82/k5log//k5ts1_log_newline 2006.196.07:46:06.51/k5log//k5ts2_log_newline 2006.196.07:46:07.20/k5log//k5ts3_log_newline 2006.196.07:46:07.91/k5log//k5ts4_log_newline 2006.196.07:46:07.94/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.196.07:46:07.94:4f8m12a=1 2006.196.07:46:07.94$4f8m12a/echo=on 2006.196.07:46:07.94$4f8m12a/pcalon 2006.196.07:46:07.94$pcalon/"no phase cal control is implemented here 2006.196.07:46:07.94$4f8m12a/"tpicd=stop 2006.196.07:46:07.94$4f8m12a/vc4f8 2006.196.07:46:07.94$vc4f8/valo=1,532.99 2006.196.07:46:07.94#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.196.07:46:07.94#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.196.07:46:07.94#ibcon#ireg 17 cls_cnt 0 2006.196.07:46:07.94#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.196.07:46:07.94#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.196.07:46:07.94#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.196.07:46:07.94#ibcon#enter wrdev, iclass 27, count 0 2006.196.07:46:07.94#ibcon#first serial, iclass 27, count 0 2006.196.07:46:07.94#ibcon#enter sib2, iclass 27, count 0 2006.196.07:46:07.94#ibcon#flushed, iclass 27, count 0 2006.196.07:46:07.94#ibcon#about to write, iclass 27, count 0 2006.196.07:46:07.94#ibcon#wrote, iclass 27, count 0 2006.196.07:46:07.94#ibcon#about to read 3, iclass 27, count 0 2006.196.07:46:07.96#ibcon#read 3, iclass 27, count 0 2006.196.07:46:07.96#ibcon#about to read 4, iclass 27, count 0 2006.196.07:46:07.96#ibcon#read 4, iclass 27, count 0 2006.196.07:46:07.96#ibcon#about to read 5, iclass 27, count 0 2006.196.07:46:07.96#ibcon#read 5, iclass 27, count 0 2006.196.07:46:07.96#ibcon#about to read 6, iclass 27, count 0 2006.196.07:46:07.96#ibcon#read 6, iclass 27, count 0 2006.196.07:46:07.96#ibcon#end of sib2, iclass 27, count 0 2006.196.07:46:07.96#ibcon#*mode == 0, iclass 27, count 0 2006.196.07:46:07.96#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.196.07:46:07.96#ibcon#[26=FRQ=01,532.99\r\n] 2006.196.07:46:07.96#ibcon#*before write, iclass 27, count 0 2006.196.07:46:07.96#ibcon#enter sib2, iclass 27, count 0 2006.196.07:46:07.96#ibcon#flushed, iclass 27, count 0 2006.196.07:46:07.96#ibcon#about to write, iclass 27, count 0 2006.196.07:46:07.96#ibcon#wrote, iclass 27, count 0 2006.196.07:46:07.96#ibcon#about to read 3, iclass 27, count 0 2006.196.07:46:08.01#ibcon#read 3, iclass 27, count 0 2006.196.07:46:08.01#ibcon#about to read 4, iclass 27, count 0 2006.196.07:46:08.01#ibcon#read 4, iclass 27, count 0 2006.196.07:46:08.01#ibcon#about to read 5, iclass 27, count 0 2006.196.07:46:08.01#ibcon#read 5, iclass 27, count 0 2006.196.07:46:08.01#ibcon#about to read 6, iclass 27, count 0 2006.196.07:46:08.01#ibcon#read 6, iclass 27, count 0 2006.196.07:46:08.01#ibcon#end of sib2, iclass 27, count 0 2006.196.07:46:08.01#ibcon#*after write, iclass 27, count 0 2006.196.07:46:08.01#ibcon#*before return 0, iclass 27, count 0 2006.196.07:46:08.01#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.196.07:46:08.01#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.196.07:46:08.01#ibcon#about to clear, iclass 27 cls_cnt 0 2006.196.07:46:08.01#ibcon#cleared, iclass 27 cls_cnt 0 2006.196.07:46:08.01$vc4f8/va=1,8 2006.196.07:46:08.01#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.196.07:46:08.01#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.196.07:46:08.01#ibcon#ireg 11 cls_cnt 2 2006.196.07:46:08.01#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.196.07:46:08.01#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.196.07:46:08.01#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.196.07:46:08.01#ibcon#enter wrdev, iclass 29, count 2 2006.196.07:46:08.01#ibcon#first serial, iclass 29, count 2 2006.196.07:46:08.01#ibcon#enter sib2, iclass 29, count 2 2006.196.07:46:08.01#ibcon#flushed, iclass 29, count 2 2006.196.07:46:08.01#ibcon#about to write, iclass 29, count 2 2006.196.07:46:08.01#ibcon#wrote, iclass 29, count 2 2006.196.07:46:08.01#ibcon#about to read 3, iclass 29, count 2 2006.196.07:46:08.03#ibcon#read 3, iclass 29, count 2 2006.196.07:46:08.03#ibcon#about to read 4, iclass 29, count 2 2006.196.07:46:08.03#ibcon#read 4, iclass 29, count 2 2006.196.07:46:08.03#ibcon#about to read 5, iclass 29, count 2 2006.196.07:46:08.03#ibcon#read 5, iclass 29, count 2 2006.196.07:46:08.03#ibcon#about to read 6, iclass 29, count 2 2006.196.07:46:08.03#ibcon#read 6, iclass 29, count 2 2006.196.07:46:08.03#ibcon#end of sib2, iclass 29, count 2 2006.196.07:46:08.03#ibcon#*mode == 0, iclass 29, count 2 2006.196.07:46:08.03#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.196.07:46:08.03#ibcon#[25=AT01-08\r\n] 2006.196.07:46:08.03#ibcon#*before write, iclass 29, count 2 2006.196.07:46:08.03#ibcon#enter sib2, iclass 29, count 2 2006.196.07:46:08.03#ibcon#flushed, iclass 29, count 2 2006.196.07:46:08.03#ibcon#about to write, iclass 29, count 2 2006.196.07:46:08.03#ibcon#wrote, iclass 29, count 2 2006.196.07:46:08.03#ibcon#about to read 3, iclass 29, count 2 2006.196.07:46:08.06#ibcon#read 3, iclass 29, count 2 2006.196.07:46:08.06#ibcon#about to read 4, iclass 29, count 2 2006.196.07:46:08.06#ibcon#read 4, iclass 29, count 2 2006.196.07:46:08.06#ibcon#about to read 5, iclass 29, count 2 2006.196.07:46:08.06#ibcon#read 5, iclass 29, count 2 2006.196.07:46:08.06#ibcon#about to read 6, iclass 29, count 2 2006.196.07:46:08.06#ibcon#read 6, iclass 29, count 2 2006.196.07:46:08.06#ibcon#end of sib2, iclass 29, count 2 2006.196.07:46:08.06#ibcon#*after write, iclass 29, count 2 2006.196.07:46:08.06#ibcon#*before return 0, iclass 29, count 2 2006.196.07:46:08.06#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.196.07:46:08.06#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.196.07:46:08.06#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.196.07:46:08.06#ibcon#ireg 7 cls_cnt 0 2006.196.07:46:08.06#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.196.07:46:08.18#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.196.07:46:08.18#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.196.07:46:08.18#ibcon#enter wrdev, iclass 29, count 0 2006.196.07:46:08.18#ibcon#first serial, iclass 29, count 0 2006.196.07:46:08.18#ibcon#enter sib2, iclass 29, count 0 2006.196.07:46:08.18#ibcon#flushed, iclass 29, count 0 2006.196.07:46:08.18#ibcon#about to write, iclass 29, count 0 2006.196.07:46:08.18#ibcon#wrote, iclass 29, count 0 2006.196.07:46:08.18#ibcon#about to read 3, iclass 29, count 0 2006.196.07:46:08.20#ibcon#read 3, iclass 29, count 0 2006.196.07:46:08.20#ibcon#about to read 4, iclass 29, count 0 2006.196.07:46:08.20#ibcon#read 4, iclass 29, count 0 2006.196.07:46:08.20#ibcon#about to read 5, iclass 29, count 0 2006.196.07:46:08.20#ibcon#read 5, iclass 29, count 0 2006.196.07:46:08.20#ibcon#about to read 6, iclass 29, count 0 2006.196.07:46:08.20#ibcon#read 6, iclass 29, count 0 2006.196.07:46:08.20#ibcon#end of sib2, iclass 29, count 0 2006.196.07:46:08.20#ibcon#*mode == 0, iclass 29, count 0 2006.196.07:46:08.20#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.196.07:46:08.20#ibcon#[25=USB\r\n] 2006.196.07:46:08.20#ibcon#*before write, iclass 29, count 0 2006.196.07:46:08.20#ibcon#enter sib2, iclass 29, count 0 2006.196.07:46:08.20#ibcon#flushed, iclass 29, count 0 2006.196.07:46:08.20#ibcon#about to write, iclass 29, count 0 2006.196.07:46:08.20#ibcon#wrote, iclass 29, count 0 2006.196.07:46:08.20#ibcon#about to read 3, iclass 29, count 0 2006.196.07:46:08.23#ibcon#read 3, iclass 29, count 0 2006.196.07:46:08.23#ibcon#about to read 4, iclass 29, count 0 2006.196.07:46:08.23#ibcon#read 4, iclass 29, count 0 2006.196.07:46:08.23#ibcon#about to read 5, iclass 29, count 0 2006.196.07:46:08.23#ibcon#read 5, iclass 29, count 0 2006.196.07:46:08.23#ibcon#about to read 6, iclass 29, count 0 2006.196.07:46:08.23#ibcon#read 6, iclass 29, count 0 2006.196.07:46:08.23#ibcon#end of sib2, iclass 29, count 0 2006.196.07:46:08.23#ibcon#*after write, iclass 29, count 0 2006.196.07:46:08.23#ibcon#*before return 0, iclass 29, count 0 2006.196.07:46:08.23#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.196.07:46:08.23#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.196.07:46:08.23#ibcon#about to clear, iclass 29 cls_cnt 0 2006.196.07:46:08.23#ibcon#cleared, iclass 29 cls_cnt 0 2006.196.07:46:08.23$vc4f8/valo=2,572.99 2006.196.07:46:08.23#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.196.07:46:08.23#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.196.07:46:08.23#ibcon#ireg 17 cls_cnt 0 2006.196.07:46:08.23#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.196.07:46:08.23#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.196.07:46:08.23#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.196.07:46:08.23#ibcon#enter wrdev, iclass 31, count 0 2006.196.07:46:08.23#ibcon#first serial, iclass 31, count 0 2006.196.07:46:08.23#ibcon#enter sib2, iclass 31, count 0 2006.196.07:46:08.23#ibcon#flushed, iclass 31, count 0 2006.196.07:46:08.23#ibcon#about to write, iclass 31, count 0 2006.196.07:46:08.23#ibcon#wrote, iclass 31, count 0 2006.196.07:46:08.23#ibcon#about to read 3, iclass 31, count 0 2006.196.07:46:08.25#ibcon#read 3, iclass 31, count 0 2006.196.07:46:08.25#ibcon#about to read 4, iclass 31, count 0 2006.196.07:46:08.25#ibcon#read 4, iclass 31, count 0 2006.196.07:46:08.25#ibcon#about to read 5, iclass 31, count 0 2006.196.07:46:08.25#ibcon#read 5, iclass 31, count 0 2006.196.07:46:08.25#ibcon#about to read 6, iclass 31, count 0 2006.196.07:46:08.25#ibcon#read 6, iclass 31, count 0 2006.196.07:46:08.25#ibcon#end of sib2, iclass 31, count 0 2006.196.07:46:08.25#ibcon#*mode == 0, iclass 31, count 0 2006.196.07:46:08.25#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.196.07:46:08.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.196.07:46:08.25#ibcon#*before write, iclass 31, count 0 2006.196.07:46:08.25#ibcon#enter sib2, iclass 31, count 0 2006.196.07:46:08.25#ibcon#flushed, iclass 31, count 0 2006.196.07:46:08.25#ibcon#about to write, iclass 31, count 0 2006.196.07:46:08.25#ibcon#wrote, iclass 31, count 0 2006.196.07:46:08.25#ibcon#about to read 3, iclass 31, count 0 2006.196.07:46:08.30#ibcon#read 3, iclass 31, count 0 2006.196.07:46:08.30#ibcon#about to read 4, iclass 31, count 0 2006.196.07:46:08.30#ibcon#read 4, iclass 31, count 0 2006.196.07:46:08.30#ibcon#about to read 5, iclass 31, count 0 2006.196.07:46:08.30#ibcon#read 5, iclass 31, count 0 2006.196.07:46:08.30#ibcon#about to read 6, iclass 31, count 0 2006.196.07:46:08.30#ibcon#read 6, iclass 31, count 0 2006.196.07:46:08.30#ibcon#end of sib2, iclass 31, count 0 2006.196.07:46:08.30#ibcon#*after write, iclass 31, count 0 2006.196.07:46:08.30#ibcon#*before return 0, iclass 31, count 0 2006.196.07:46:08.30#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.196.07:46:08.30#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.196.07:46:08.30#ibcon#about to clear, iclass 31 cls_cnt 0 2006.196.07:46:08.30#ibcon#cleared, iclass 31 cls_cnt 0 2006.196.07:46:08.30$vc4f8/va=2,7 2006.196.07:46:08.30#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.196.07:46:08.30#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.196.07:46:08.30#ibcon#ireg 11 cls_cnt 2 2006.196.07:46:08.30#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.196.07:46:08.35#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.196.07:46:08.35#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.196.07:46:08.35#ibcon#enter wrdev, iclass 33, count 2 2006.196.07:46:08.35#ibcon#first serial, iclass 33, count 2 2006.196.07:46:08.35#ibcon#enter sib2, iclass 33, count 2 2006.196.07:46:08.35#ibcon#flushed, iclass 33, count 2 2006.196.07:46:08.35#ibcon#about to write, iclass 33, count 2 2006.196.07:46:08.35#ibcon#wrote, iclass 33, count 2 2006.196.07:46:08.35#ibcon#about to read 3, iclass 33, count 2 2006.196.07:46:08.37#ibcon#read 3, iclass 33, count 2 2006.196.07:46:08.37#ibcon#about to read 4, iclass 33, count 2 2006.196.07:46:08.37#ibcon#read 4, iclass 33, count 2 2006.196.07:46:08.37#ibcon#about to read 5, iclass 33, count 2 2006.196.07:46:08.37#ibcon#read 5, iclass 33, count 2 2006.196.07:46:08.37#ibcon#about to read 6, iclass 33, count 2 2006.196.07:46:08.37#ibcon#read 6, iclass 33, count 2 2006.196.07:46:08.37#ibcon#end of sib2, iclass 33, count 2 2006.196.07:46:08.37#ibcon#*mode == 0, iclass 33, count 2 2006.196.07:46:08.37#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.196.07:46:08.37#ibcon#[25=AT02-07\r\n] 2006.196.07:46:08.37#ibcon#*before write, iclass 33, count 2 2006.196.07:46:08.37#ibcon#enter sib2, iclass 33, count 2 2006.196.07:46:08.37#ibcon#flushed, iclass 33, count 2 2006.196.07:46:08.37#ibcon#about to write, iclass 33, count 2 2006.196.07:46:08.37#ibcon#wrote, iclass 33, count 2 2006.196.07:46:08.37#ibcon#about to read 3, iclass 33, count 2 2006.196.07:46:08.40#ibcon#read 3, iclass 33, count 2 2006.196.07:46:08.40#ibcon#about to read 4, iclass 33, count 2 2006.196.07:46:08.40#ibcon#read 4, iclass 33, count 2 2006.196.07:46:08.40#ibcon#about to read 5, iclass 33, count 2 2006.196.07:46:08.40#ibcon#read 5, iclass 33, count 2 2006.196.07:46:08.40#ibcon#about to read 6, iclass 33, count 2 2006.196.07:46:08.40#ibcon#read 6, iclass 33, count 2 2006.196.07:46:08.40#ibcon#end of sib2, iclass 33, count 2 2006.196.07:46:08.40#ibcon#*after write, iclass 33, count 2 2006.196.07:46:08.40#ibcon#*before return 0, iclass 33, count 2 2006.196.07:46:08.40#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.196.07:46:08.40#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.196.07:46:08.40#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.196.07:46:08.40#ibcon#ireg 7 cls_cnt 0 2006.196.07:46:08.40#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.196.07:46:08.52#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.196.07:46:08.52#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.196.07:46:08.52#ibcon#enter wrdev, iclass 33, count 0 2006.196.07:46:08.52#ibcon#first serial, iclass 33, count 0 2006.196.07:46:08.52#ibcon#enter sib2, iclass 33, count 0 2006.196.07:46:08.52#ibcon#flushed, iclass 33, count 0 2006.196.07:46:08.52#ibcon#about to write, iclass 33, count 0 2006.196.07:46:08.52#ibcon#wrote, iclass 33, count 0 2006.196.07:46:08.52#ibcon#about to read 3, iclass 33, count 0 2006.196.07:46:08.54#ibcon#read 3, iclass 33, count 0 2006.196.07:46:08.54#ibcon#about to read 4, iclass 33, count 0 2006.196.07:46:08.54#ibcon#read 4, iclass 33, count 0 2006.196.07:46:08.54#ibcon#about to read 5, iclass 33, count 0 2006.196.07:46:08.54#ibcon#read 5, iclass 33, count 0 2006.196.07:46:08.54#ibcon#about to read 6, iclass 33, count 0 2006.196.07:46:08.54#ibcon#read 6, iclass 33, count 0 2006.196.07:46:08.54#ibcon#end of sib2, iclass 33, count 0 2006.196.07:46:08.54#ibcon#*mode == 0, iclass 33, count 0 2006.196.07:46:08.54#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.196.07:46:08.54#ibcon#[25=USB\r\n] 2006.196.07:46:08.54#ibcon#*before write, iclass 33, count 0 2006.196.07:46:08.54#ibcon#enter sib2, iclass 33, count 0 2006.196.07:46:08.54#ibcon#flushed, iclass 33, count 0 2006.196.07:46:08.54#ibcon#about to write, iclass 33, count 0 2006.196.07:46:08.54#ibcon#wrote, iclass 33, count 0 2006.196.07:46:08.54#ibcon#about to read 3, iclass 33, count 0 2006.196.07:46:08.57#ibcon#read 3, iclass 33, count 0 2006.196.07:46:08.57#ibcon#about to read 4, iclass 33, count 0 2006.196.07:46:08.57#ibcon#read 4, iclass 33, count 0 2006.196.07:46:08.57#ibcon#about to read 5, iclass 33, count 0 2006.196.07:46:08.57#ibcon#read 5, iclass 33, count 0 2006.196.07:46:08.57#ibcon#about to read 6, iclass 33, count 0 2006.196.07:46:08.57#ibcon#read 6, iclass 33, count 0 2006.196.07:46:08.57#ibcon#end of sib2, iclass 33, count 0 2006.196.07:46:08.57#ibcon#*after write, iclass 33, count 0 2006.196.07:46:08.57#ibcon#*before return 0, iclass 33, count 0 2006.196.07:46:08.57#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.196.07:46:08.57#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.196.07:46:08.57#ibcon#about to clear, iclass 33 cls_cnt 0 2006.196.07:46:08.57#ibcon#cleared, iclass 33 cls_cnt 0 2006.196.07:46:08.57$vc4f8/valo=3,672.99 2006.196.07:46:08.57#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.196.07:46:08.57#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.196.07:46:08.57#ibcon#ireg 17 cls_cnt 0 2006.196.07:46:08.57#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.196.07:46:08.57#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.196.07:46:08.57#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.196.07:46:08.57#ibcon#enter wrdev, iclass 35, count 0 2006.196.07:46:08.57#ibcon#first serial, iclass 35, count 0 2006.196.07:46:08.57#ibcon#enter sib2, iclass 35, count 0 2006.196.07:46:08.57#ibcon#flushed, iclass 35, count 0 2006.196.07:46:08.57#ibcon#about to write, iclass 35, count 0 2006.196.07:46:08.57#ibcon#wrote, iclass 35, count 0 2006.196.07:46:08.57#ibcon#about to read 3, iclass 35, count 0 2006.196.07:46:08.59#ibcon#read 3, iclass 35, count 0 2006.196.07:46:08.59#ibcon#about to read 4, iclass 35, count 0 2006.196.07:46:08.59#ibcon#read 4, iclass 35, count 0 2006.196.07:46:08.59#ibcon#about to read 5, iclass 35, count 0 2006.196.07:46:08.59#ibcon#read 5, iclass 35, count 0 2006.196.07:46:08.59#ibcon#about to read 6, iclass 35, count 0 2006.196.07:46:08.59#ibcon#read 6, iclass 35, count 0 2006.196.07:46:08.59#ibcon#end of sib2, iclass 35, count 0 2006.196.07:46:08.59#ibcon#*mode == 0, iclass 35, count 0 2006.196.07:46:08.59#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.196.07:46:08.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.196.07:46:08.59#ibcon#*before write, iclass 35, count 0 2006.196.07:46:08.59#ibcon#enter sib2, iclass 35, count 0 2006.196.07:46:08.59#ibcon#flushed, iclass 35, count 0 2006.196.07:46:08.59#ibcon#about to write, iclass 35, count 0 2006.196.07:46:08.59#ibcon#wrote, iclass 35, count 0 2006.196.07:46:08.59#ibcon#about to read 3, iclass 35, count 0 2006.196.07:46:08.64#ibcon#read 3, iclass 35, count 0 2006.196.07:46:08.64#ibcon#about to read 4, iclass 35, count 0 2006.196.07:46:08.64#ibcon#read 4, iclass 35, count 0 2006.196.07:46:08.64#ibcon#about to read 5, iclass 35, count 0 2006.196.07:46:08.64#ibcon#read 5, iclass 35, count 0 2006.196.07:46:08.64#ibcon#about to read 6, iclass 35, count 0 2006.196.07:46:08.64#ibcon#read 6, iclass 35, count 0 2006.196.07:46:08.64#ibcon#end of sib2, iclass 35, count 0 2006.196.07:46:08.64#ibcon#*after write, iclass 35, count 0 2006.196.07:46:08.64#ibcon#*before return 0, iclass 35, count 0 2006.196.07:46:08.64#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.196.07:46:08.64#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.196.07:46:08.64#ibcon#about to clear, iclass 35 cls_cnt 0 2006.196.07:46:08.64#ibcon#cleared, iclass 35 cls_cnt 0 2006.196.07:46:08.64$vc4f8/va=3,6 2006.196.07:46:08.64#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.196.07:46:08.64#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.196.07:46:08.64#ibcon#ireg 11 cls_cnt 2 2006.196.07:46:08.64#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.196.07:46:08.69#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.196.07:46:08.69#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.196.07:46:08.69#ibcon#enter wrdev, iclass 37, count 2 2006.196.07:46:08.69#ibcon#first serial, iclass 37, count 2 2006.196.07:46:08.69#ibcon#enter sib2, iclass 37, count 2 2006.196.07:46:08.69#ibcon#flushed, iclass 37, count 2 2006.196.07:46:08.69#ibcon#about to write, iclass 37, count 2 2006.196.07:46:08.69#ibcon#wrote, iclass 37, count 2 2006.196.07:46:08.69#ibcon#about to read 3, iclass 37, count 2 2006.196.07:46:08.71#ibcon#read 3, iclass 37, count 2 2006.196.07:46:08.71#ibcon#about to read 4, iclass 37, count 2 2006.196.07:46:08.71#ibcon#read 4, iclass 37, count 2 2006.196.07:46:08.71#ibcon#about to read 5, iclass 37, count 2 2006.196.07:46:08.71#ibcon#read 5, iclass 37, count 2 2006.196.07:46:08.71#ibcon#about to read 6, iclass 37, count 2 2006.196.07:46:08.71#ibcon#read 6, iclass 37, count 2 2006.196.07:46:08.71#ibcon#end of sib2, iclass 37, count 2 2006.196.07:46:08.71#ibcon#*mode == 0, iclass 37, count 2 2006.196.07:46:08.71#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.196.07:46:08.71#ibcon#[25=AT03-06\r\n] 2006.196.07:46:08.71#ibcon#*before write, iclass 37, count 2 2006.196.07:46:08.71#ibcon#enter sib2, iclass 37, count 2 2006.196.07:46:08.71#ibcon#flushed, iclass 37, count 2 2006.196.07:46:08.71#ibcon#about to write, iclass 37, count 2 2006.196.07:46:08.71#ibcon#wrote, iclass 37, count 2 2006.196.07:46:08.71#ibcon#about to read 3, iclass 37, count 2 2006.196.07:46:08.74#ibcon#read 3, iclass 37, count 2 2006.196.07:46:08.74#ibcon#about to read 4, iclass 37, count 2 2006.196.07:46:08.74#ibcon#read 4, iclass 37, count 2 2006.196.07:46:08.74#ibcon#about to read 5, iclass 37, count 2 2006.196.07:46:08.74#ibcon#read 5, iclass 37, count 2 2006.196.07:46:08.74#ibcon#about to read 6, iclass 37, count 2 2006.196.07:46:08.74#ibcon#read 6, iclass 37, count 2 2006.196.07:46:08.74#ibcon#end of sib2, iclass 37, count 2 2006.196.07:46:08.74#ibcon#*after write, iclass 37, count 2 2006.196.07:46:08.74#ibcon#*before return 0, iclass 37, count 2 2006.196.07:46:08.74#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.196.07:46:08.74#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.196.07:46:08.74#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.196.07:46:08.74#ibcon#ireg 7 cls_cnt 0 2006.196.07:46:08.74#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.196.07:46:08.86#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.196.07:46:08.86#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.196.07:46:08.86#ibcon#enter wrdev, iclass 37, count 0 2006.196.07:46:08.86#ibcon#first serial, iclass 37, count 0 2006.196.07:46:08.86#ibcon#enter sib2, iclass 37, count 0 2006.196.07:46:08.86#ibcon#flushed, iclass 37, count 0 2006.196.07:46:08.86#ibcon#about to write, iclass 37, count 0 2006.196.07:46:08.86#ibcon#wrote, iclass 37, count 0 2006.196.07:46:08.86#ibcon#about to read 3, iclass 37, count 0 2006.196.07:46:08.88#ibcon#read 3, iclass 37, count 0 2006.196.07:46:08.88#ibcon#about to read 4, iclass 37, count 0 2006.196.07:46:08.88#ibcon#read 4, iclass 37, count 0 2006.196.07:46:08.88#ibcon#about to read 5, iclass 37, count 0 2006.196.07:46:08.88#ibcon#read 5, iclass 37, count 0 2006.196.07:46:08.88#ibcon#about to read 6, iclass 37, count 0 2006.196.07:46:08.88#ibcon#read 6, iclass 37, count 0 2006.196.07:46:08.88#ibcon#end of sib2, iclass 37, count 0 2006.196.07:46:08.88#ibcon#*mode == 0, iclass 37, count 0 2006.196.07:46:08.88#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.196.07:46:08.88#ibcon#[25=USB\r\n] 2006.196.07:46:08.88#ibcon#*before write, iclass 37, count 0 2006.196.07:46:08.88#ibcon#enter sib2, iclass 37, count 0 2006.196.07:46:08.88#ibcon#flushed, iclass 37, count 0 2006.196.07:46:08.88#ibcon#about to write, iclass 37, count 0 2006.196.07:46:08.88#ibcon#wrote, iclass 37, count 0 2006.196.07:46:08.88#ibcon#about to read 3, iclass 37, count 0 2006.196.07:46:08.91#ibcon#read 3, iclass 37, count 0 2006.196.07:46:08.91#ibcon#about to read 4, iclass 37, count 0 2006.196.07:46:08.91#ibcon#read 4, iclass 37, count 0 2006.196.07:46:08.91#ibcon#about to read 5, iclass 37, count 0 2006.196.07:46:08.91#ibcon#read 5, iclass 37, count 0 2006.196.07:46:08.91#ibcon#about to read 6, iclass 37, count 0 2006.196.07:46:08.91#ibcon#read 6, iclass 37, count 0 2006.196.07:46:08.91#ibcon#end of sib2, iclass 37, count 0 2006.196.07:46:08.91#ibcon#*after write, iclass 37, count 0 2006.196.07:46:08.91#ibcon#*before return 0, iclass 37, count 0 2006.196.07:46:08.91#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.196.07:46:08.91#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.196.07:46:08.91#ibcon#about to clear, iclass 37 cls_cnt 0 2006.196.07:46:08.91#ibcon#cleared, iclass 37 cls_cnt 0 2006.196.07:46:08.91$vc4f8/valo=4,832.99 2006.196.07:46:08.91#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.196.07:46:08.91#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.196.07:46:08.91#ibcon#ireg 17 cls_cnt 0 2006.196.07:46:08.91#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.196.07:46:08.91#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.196.07:46:08.91#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.196.07:46:08.91#ibcon#enter wrdev, iclass 39, count 0 2006.196.07:46:08.91#ibcon#first serial, iclass 39, count 0 2006.196.07:46:08.91#ibcon#enter sib2, iclass 39, count 0 2006.196.07:46:08.91#ibcon#flushed, iclass 39, count 0 2006.196.07:46:08.91#ibcon#about to write, iclass 39, count 0 2006.196.07:46:08.91#ibcon#wrote, iclass 39, count 0 2006.196.07:46:08.91#ibcon#about to read 3, iclass 39, count 0 2006.196.07:46:08.93#ibcon#read 3, iclass 39, count 0 2006.196.07:46:08.93#ibcon#about to read 4, iclass 39, count 0 2006.196.07:46:08.93#ibcon#read 4, iclass 39, count 0 2006.196.07:46:08.93#ibcon#about to read 5, iclass 39, count 0 2006.196.07:46:08.93#ibcon#read 5, iclass 39, count 0 2006.196.07:46:08.93#ibcon#about to read 6, iclass 39, count 0 2006.196.07:46:08.93#ibcon#read 6, iclass 39, count 0 2006.196.07:46:08.93#ibcon#end of sib2, iclass 39, count 0 2006.196.07:46:08.93#ibcon#*mode == 0, iclass 39, count 0 2006.196.07:46:08.93#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.196.07:46:08.93#ibcon#[26=FRQ=04,832.99\r\n] 2006.196.07:46:08.93#ibcon#*before write, iclass 39, count 0 2006.196.07:46:08.93#ibcon#enter sib2, iclass 39, count 0 2006.196.07:46:08.93#ibcon#flushed, iclass 39, count 0 2006.196.07:46:08.93#ibcon#about to write, iclass 39, count 0 2006.196.07:46:08.93#ibcon#wrote, iclass 39, count 0 2006.196.07:46:08.93#ibcon#about to read 3, iclass 39, count 0 2006.196.07:46:08.98#ibcon#read 3, iclass 39, count 0 2006.196.07:46:08.98#ibcon#about to read 4, iclass 39, count 0 2006.196.07:46:08.98#ibcon#read 4, iclass 39, count 0 2006.196.07:46:08.98#ibcon#about to read 5, iclass 39, count 0 2006.196.07:46:08.98#ibcon#read 5, iclass 39, count 0 2006.196.07:46:08.98#ibcon#about to read 6, iclass 39, count 0 2006.196.07:46:08.98#ibcon#read 6, iclass 39, count 0 2006.196.07:46:08.98#ibcon#end of sib2, iclass 39, count 0 2006.196.07:46:08.98#ibcon#*after write, iclass 39, count 0 2006.196.07:46:08.98#ibcon#*before return 0, iclass 39, count 0 2006.196.07:46:08.98#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.196.07:46:08.98#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.196.07:46:08.98#ibcon#about to clear, iclass 39 cls_cnt 0 2006.196.07:46:08.98#ibcon#cleared, iclass 39 cls_cnt 0 2006.196.07:46:08.98$vc4f8/va=4,7 2006.196.07:46:08.98#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.196.07:46:08.98#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.196.07:46:08.98#ibcon#ireg 11 cls_cnt 2 2006.196.07:46:08.98#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.196.07:46:09.03#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.196.07:46:09.03#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.196.07:46:09.03#ibcon#enter wrdev, iclass 3, count 2 2006.196.07:46:09.03#ibcon#first serial, iclass 3, count 2 2006.196.07:46:09.03#ibcon#enter sib2, iclass 3, count 2 2006.196.07:46:09.03#ibcon#flushed, iclass 3, count 2 2006.196.07:46:09.03#ibcon#about to write, iclass 3, count 2 2006.196.07:46:09.03#ibcon#wrote, iclass 3, count 2 2006.196.07:46:09.03#ibcon#about to read 3, iclass 3, count 2 2006.196.07:46:09.05#ibcon#read 3, iclass 3, count 2 2006.196.07:46:09.05#ibcon#about to read 4, iclass 3, count 2 2006.196.07:46:09.05#ibcon#read 4, iclass 3, count 2 2006.196.07:46:09.05#ibcon#about to read 5, iclass 3, count 2 2006.196.07:46:09.05#ibcon#read 5, iclass 3, count 2 2006.196.07:46:09.05#ibcon#about to read 6, iclass 3, count 2 2006.196.07:46:09.05#ibcon#read 6, iclass 3, count 2 2006.196.07:46:09.05#ibcon#end of sib2, iclass 3, count 2 2006.196.07:46:09.05#ibcon#*mode == 0, iclass 3, count 2 2006.196.07:46:09.05#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.196.07:46:09.05#ibcon#[25=AT04-07\r\n] 2006.196.07:46:09.05#ibcon#*before write, iclass 3, count 2 2006.196.07:46:09.05#ibcon#enter sib2, iclass 3, count 2 2006.196.07:46:09.05#ibcon#flushed, iclass 3, count 2 2006.196.07:46:09.05#ibcon#about to write, iclass 3, count 2 2006.196.07:46:09.05#ibcon#wrote, iclass 3, count 2 2006.196.07:46:09.05#ibcon#about to read 3, iclass 3, count 2 2006.196.07:46:09.08#ibcon#read 3, iclass 3, count 2 2006.196.07:46:09.08#ibcon#about to read 4, iclass 3, count 2 2006.196.07:46:09.08#ibcon#read 4, iclass 3, count 2 2006.196.07:46:09.08#ibcon#about to read 5, iclass 3, count 2 2006.196.07:46:09.08#ibcon#read 5, iclass 3, count 2 2006.196.07:46:09.08#ibcon#about to read 6, iclass 3, count 2 2006.196.07:46:09.08#ibcon#read 6, iclass 3, count 2 2006.196.07:46:09.08#ibcon#end of sib2, iclass 3, count 2 2006.196.07:46:09.08#ibcon#*after write, iclass 3, count 2 2006.196.07:46:09.08#ibcon#*before return 0, iclass 3, count 2 2006.196.07:46:09.08#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.196.07:46:09.08#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.196.07:46:09.08#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.196.07:46:09.08#ibcon#ireg 7 cls_cnt 0 2006.196.07:46:09.08#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.196.07:46:09.20#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.196.07:46:09.20#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.196.07:46:09.20#ibcon#enter wrdev, iclass 3, count 0 2006.196.07:46:09.20#ibcon#first serial, iclass 3, count 0 2006.196.07:46:09.20#ibcon#enter sib2, iclass 3, count 0 2006.196.07:46:09.20#ibcon#flushed, iclass 3, count 0 2006.196.07:46:09.20#ibcon#about to write, iclass 3, count 0 2006.196.07:46:09.20#ibcon#wrote, iclass 3, count 0 2006.196.07:46:09.20#ibcon#about to read 3, iclass 3, count 0 2006.196.07:46:09.22#ibcon#read 3, iclass 3, count 0 2006.196.07:46:09.22#ibcon#about to read 4, iclass 3, count 0 2006.196.07:46:09.22#ibcon#read 4, iclass 3, count 0 2006.196.07:46:09.22#ibcon#about to read 5, iclass 3, count 0 2006.196.07:46:09.22#ibcon#read 5, iclass 3, count 0 2006.196.07:46:09.22#ibcon#about to read 6, iclass 3, count 0 2006.196.07:46:09.22#ibcon#read 6, iclass 3, count 0 2006.196.07:46:09.22#ibcon#end of sib2, iclass 3, count 0 2006.196.07:46:09.22#ibcon#*mode == 0, iclass 3, count 0 2006.196.07:46:09.22#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.196.07:46:09.22#ibcon#[25=USB\r\n] 2006.196.07:46:09.22#ibcon#*before write, iclass 3, count 0 2006.196.07:46:09.22#ibcon#enter sib2, iclass 3, count 0 2006.196.07:46:09.22#ibcon#flushed, iclass 3, count 0 2006.196.07:46:09.22#ibcon#about to write, iclass 3, count 0 2006.196.07:46:09.22#ibcon#wrote, iclass 3, count 0 2006.196.07:46:09.22#ibcon#about to read 3, iclass 3, count 0 2006.196.07:46:09.25#ibcon#read 3, iclass 3, count 0 2006.196.07:46:09.25#ibcon#about to read 4, iclass 3, count 0 2006.196.07:46:09.25#ibcon#read 4, iclass 3, count 0 2006.196.07:46:09.25#ibcon#about to read 5, iclass 3, count 0 2006.196.07:46:09.25#ibcon#read 5, iclass 3, count 0 2006.196.07:46:09.25#ibcon#about to read 6, iclass 3, count 0 2006.196.07:46:09.25#ibcon#read 6, iclass 3, count 0 2006.196.07:46:09.25#ibcon#end of sib2, iclass 3, count 0 2006.196.07:46:09.25#ibcon#*after write, iclass 3, count 0 2006.196.07:46:09.25#ibcon#*before return 0, iclass 3, count 0 2006.196.07:46:09.25#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.196.07:46:09.25#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.196.07:46:09.25#ibcon#about to clear, iclass 3 cls_cnt 0 2006.196.07:46:09.25#ibcon#cleared, iclass 3 cls_cnt 0 2006.196.07:46:09.25$vc4f8/valo=5,652.99 2006.196.07:46:09.25#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.196.07:46:09.25#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.196.07:46:09.25#ibcon#ireg 17 cls_cnt 0 2006.196.07:46:09.25#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.196.07:46:09.25#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.196.07:46:09.25#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.196.07:46:09.25#ibcon#enter wrdev, iclass 5, count 0 2006.196.07:46:09.25#ibcon#first serial, iclass 5, count 0 2006.196.07:46:09.25#ibcon#enter sib2, iclass 5, count 0 2006.196.07:46:09.25#ibcon#flushed, iclass 5, count 0 2006.196.07:46:09.25#ibcon#about to write, iclass 5, count 0 2006.196.07:46:09.25#ibcon#wrote, iclass 5, count 0 2006.196.07:46:09.25#ibcon#about to read 3, iclass 5, count 0 2006.196.07:46:09.27#ibcon#read 3, iclass 5, count 0 2006.196.07:46:09.27#ibcon#about to read 4, iclass 5, count 0 2006.196.07:46:09.27#ibcon#read 4, iclass 5, count 0 2006.196.07:46:09.27#ibcon#about to read 5, iclass 5, count 0 2006.196.07:46:09.27#ibcon#read 5, iclass 5, count 0 2006.196.07:46:09.27#ibcon#about to read 6, iclass 5, count 0 2006.196.07:46:09.27#ibcon#read 6, iclass 5, count 0 2006.196.07:46:09.27#ibcon#end of sib2, iclass 5, count 0 2006.196.07:46:09.27#ibcon#*mode == 0, iclass 5, count 0 2006.196.07:46:09.27#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.196.07:46:09.27#ibcon#[26=FRQ=05,652.99\r\n] 2006.196.07:46:09.27#ibcon#*before write, iclass 5, count 0 2006.196.07:46:09.27#ibcon#enter sib2, iclass 5, count 0 2006.196.07:46:09.27#ibcon#flushed, iclass 5, count 0 2006.196.07:46:09.27#ibcon#about to write, iclass 5, count 0 2006.196.07:46:09.27#ibcon#wrote, iclass 5, count 0 2006.196.07:46:09.27#ibcon#about to read 3, iclass 5, count 0 2006.196.07:46:09.31#ibcon#read 3, iclass 5, count 0 2006.196.07:46:09.31#ibcon#about to read 4, iclass 5, count 0 2006.196.07:46:09.31#ibcon#read 4, iclass 5, count 0 2006.196.07:46:09.31#ibcon#about to read 5, iclass 5, count 0 2006.196.07:46:09.31#ibcon#read 5, iclass 5, count 0 2006.196.07:46:09.31#ibcon#about to read 6, iclass 5, count 0 2006.196.07:46:09.31#ibcon#read 6, iclass 5, count 0 2006.196.07:46:09.31#ibcon#end of sib2, iclass 5, count 0 2006.196.07:46:09.31#ibcon#*after write, iclass 5, count 0 2006.196.07:46:09.31#ibcon#*before return 0, iclass 5, count 0 2006.196.07:46:09.31#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.196.07:46:09.31#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.196.07:46:09.31#ibcon#about to clear, iclass 5 cls_cnt 0 2006.196.07:46:09.31#ibcon#cleared, iclass 5 cls_cnt 0 2006.196.07:46:09.31$vc4f8/va=5,7 2006.196.07:46:09.31#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.196.07:46:09.31#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.196.07:46:09.31#ibcon#ireg 11 cls_cnt 2 2006.196.07:46:09.31#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.196.07:46:09.37#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.196.07:46:09.37#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.196.07:46:09.37#ibcon#enter wrdev, iclass 7, count 2 2006.196.07:46:09.37#ibcon#first serial, iclass 7, count 2 2006.196.07:46:09.37#ibcon#enter sib2, iclass 7, count 2 2006.196.07:46:09.37#ibcon#flushed, iclass 7, count 2 2006.196.07:46:09.37#ibcon#about to write, iclass 7, count 2 2006.196.07:46:09.37#ibcon#wrote, iclass 7, count 2 2006.196.07:46:09.37#ibcon#about to read 3, iclass 7, count 2 2006.196.07:46:09.39#ibcon#read 3, iclass 7, count 2 2006.196.07:46:09.39#ibcon#about to read 4, iclass 7, count 2 2006.196.07:46:09.39#ibcon#read 4, iclass 7, count 2 2006.196.07:46:09.39#ibcon#about to read 5, iclass 7, count 2 2006.196.07:46:09.39#ibcon#read 5, iclass 7, count 2 2006.196.07:46:09.39#ibcon#about to read 6, iclass 7, count 2 2006.196.07:46:09.39#ibcon#read 6, iclass 7, count 2 2006.196.07:46:09.39#ibcon#end of sib2, iclass 7, count 2 2006.196.07:46:09.39#ibcon#*mode == 0, iclass 7, count 2 2006.196.07:46:09.39#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.196.07:46:09.39#ibcon#[25=AT05-07\r\n] 2006.196.07:46:09.39#ibcon#*before write, iclass 7, count 2 2006.196.07:46:09.39#ibcon#enter sib2, iclass 7, count 2 2006.196.07:46:09.39#ibcon#flushed, iclass 7, count 2 2006.196.07:46:09.39#ibcon#about to write, iclass 7, count 2 2006.196.07:46:09.39#ibcon#wrote, iclass 7, count 2 2006.196.07:46:09.39#ibcon#about to read 3, iclass 7, count 2 2006.196.07:46:09.42#ibcon#read 3, iclass 7, count 2 2006.196.07:46:09.42#ibcon#about to read 4, iclass 7, count 2 2006.196.07:46:09.42#ibcon#read 4, iclass 7, count 2 2006.196.07:46:09.42#ibcon#about to read 5, iclass 7, count 2 2006.196.07:46:09.42#ibcon#read 5, iclass 7, count 2 2006.196.07:46:09.42#ibcon#about to read 6, iclass 7, count 2 2006.196.07:46:09.42#ibcon#read 6, iclass 7, count 2 2006.196.07:46:09.42#ibcon#end of sib2, iclass 7, count 2 2006.196.07:46:09.42#ibcon#*after write, iclass 7, count 2 2006.196.07:46:09.42#ibcon#*before return 0, iclass 7, count 2 2006.196.07:46:09.42#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.196.07:46:09.42#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.196.07:46:09.42#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.196.07:46:09.42#ibcon#ireg 7 cls_cnt 0 2006.196.07:46:09.42#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.196.07:46:09.54#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.196.07:46:09.54#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.196.07:46:09.54#ibcon#enter wrdev, iclass 7, count 0 2006.196.07:46:09.54#ibcon#first serial, iclass 7, count 0 2006.196.07:46:09.54#ibcon#enter sib2, iclass 7, count 0 2006.196.07:46:09.54#ibcon#flushed, iclass 7, count 0 2006.196.07:46:09.54#ibcon#about to write, iclass 7, count 0 2006.196.07:46:09.54#ibcon#wrote, iclass 7, count 0 2006.196.07:46:09.54#ibcon#about to read 3, iclass 7, count 0 2006.196.07:46:09.56#ibcon#read 3, iclass 7, count 0 2006.196.07:46:09.56#ibcon#about to read 4, iclass 7, count 0 2006.196.07:46:09.56#ibcon#read 4, iclass 7, count 0 2006.196.07:46:09.56#ibcon#about to read 5, iclass 7, count 0 2006.196.07:46:09.56#ibcon#read 5, iclass 7, count 0 2006.196.07:46:09.56#ibcon#about to read 6, iclass 7, count 0 2006.196.07:46:09.56#ibcon#read 6, iclass 7, count 0 2006.196.07:46:09.56#ibcon#end of sib2, iclass 7, count 0 2006.196.07:46:09.56#ibcon#*mode == 0, iclass 7, count 0 2006.196.07:46:09.56#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.196.07:46:09.56#ibcon#[25=USB\r\n] 2006.196.07:46:09.56#ibcon#*before write, iclass 7, count 0 2006.196.07:46:09.56#ibcon#enter sib2, iclass 7, count 0 2006.196.07:46:09.56#ibcon#flushed, iclass 7, count 0 2006.196.07:46:09.56#ibcon#about to write, iclass 7, count 0 2006.196.07:46:09.56#ibcon#wrote, iclass 7, count 0 2006.196.07:46:09.56#ibcon#about to read 3, iclass 7, count 0 2006.196.07:46:09.59#ibcon#read 3, iclass 7, count 0 2006.196.07:46:09.59#ibcon#about to read 4, iclass 7, count 0 2006.196.07:46:09.59#ibcon#read 4, iclass 7, count 0 2006.196.07:46:09.59#ibcon#about to read 5, iclass 7, count 0 2006.196.07:46:09.59#ibcon#read 5, iclass 7, count 0 2006.196.07:46:09.59#ibcon#about to read 6, iclass 7, count 0 2006.196.07:46:09.59#ibcon#read 6, iclass 7, count 0 2006.196.07:46:09.59#ibcon#end of sib2, iclass 7, count 0 2006.196.07:46:09.59#ibcon#*after write, iclass 7, count 0 2006.196.07:46:09.59#ibcon#*before return 0, iclass 7, count 0 2006.196.07:46:09.59#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.196.07:46:09.59#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.196.07:46:09.59#ibcon#about to clear, iclass 7 cls_cnt 0 2006.196.07:46:09.59#ibcon#cleared, iclass 7 cls_cnt 0 2006.196.07:46:09.59$vc4f8/valo=6,772.99 2006.196.07:46:09.59#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.196.07:46:09.59#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.196.07:46:09.59#ibcon#ireg 17 cls_cnt 0 2006.196.07:46:09.59#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.196.07:46:09.59#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.196.07:46:09.59#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.196.07:46:09.59#ibcon#enter wrdev, iclass 11, count 0 2006.196.07:46:09.59#ibcon#first serial, iclass 11, count 0 2006.196.07:46:09.59#ibcon#enter sib2, iclass 11, count 0 2006.196.07:46:09.59#ibcon#flushed, iclass 11, count 0 2006.196.07:46:09.59#ibcon#about to write, iclass 11, count 0 2006.196.07:46:09.59#ibcon#wrote, iclass 11, count 0 2006.196.07:46:09.59#ibcon#about to read 3, iclass 11, count 0 2006.196.07:46:09.61#ibcon#read 3, iclass 11, count 0 2006.196.07:46:09.61#ibcon#about to read 4, iclass 11, count 0 2006.196.07:46:09.61#ibcon#read 4, iclass 11, count 0 2006.196.07:46:09.61#ibcon#about to read 5, iclass 11, count 0 2006.196.07:46:09.61#ibcon#read 5, iclass 11, count 0 2006.196.07:46:09.61#ibcon#about to read 6, iclass 11, count 0 2006.196.07:46:09.61#ibcon#read 6, iclass 11, count 0 2006.196.07:46:09.61#ibcon#end of sib2, iclass 11, count 0 2006.196.07:46:09.61#ibcon#*mode == 0, iclass 11, count 0 2006.196.07:46:09.61#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.196.07:46:09.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.196.07:46:09.61#ibcon#*before write, iclass 11, count 0 2006.196.07:46:09.61#ibcon#enter sib2, iclass 11, count 0 2006.196.07:46:09.61#ibcon#flushed, iclass 11, count 0 2006.196.07:46:09.61#ibcon#about to write, iclass 11, count 0 2006.196.07:46:09.61#ibcon#wrote, iclass 11, count 0 2006.196.07:46:09.61#ibcon#about to read 3, iclass 11, count 0 2006.196.07:46:09.65#ibcon#read 3, iclass 11, count 0 2006.196.07:46:09.65#ibcon#about to read 4, iclass 11, count 0 2006.196.07:46:09.65#ibcon#read 4, iclass 11, count 0 2006.196.07:46:09.65#ibcon#about to read 5, iclass 11, count 0 2006.196.07:46:09.65#ibcon#read 5, iclass 11, count 0 2006.196.07:46:09.65#ibcon#about to read 6, iclass 11, count 0 2006.196.07:46:09.65#ibcon#read 6, iclass 11, count 0 2006.196.07:46:09.65#ibcon#end of sib2, iclass 11, count 0 2006.196.07:46:09.65#ibcon#*after write, iclass 11, count 0 2006.196.07:46:09.65#ibcon#*before return 0, iclass 11, count 0 2006.196.07:46:09.65#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.196.07:46:09.65#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.196.07:46:09.65#ibcon#about to clear, iclass 11 cls_cnt 0 2006.196.07:46:09.65#ibcon#cleared, iclass 11 cls_cnt 0 2006.196.07:46:09.65$vc4f8/va=6,6 2006.196.07:46:09.65#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.196.07:46:09.65#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.196.07:46:09.65#ibcon#ireg 11 cls_cnt 2 2006.196.07:46:09.65#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.196.07:46:09.71#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.196.07:46:09.71#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.196.07:46:09.71#ibcon#enter wrdev, iclass 13, count 2 2006.196.07:46:09.71#ibcon#first serial, iclass 13, count 2 2006.196.07:46:09.71#ibcon#enter sib2, iclass 13, count 2 2006.196.07:46:09.71#ibcon#flushed, iclass 13, count 2 2006.196.07:46:09.71#ibcon#about to write, iclass 13, count 2 2006.196.07:46:09.71#ibcon#wrote, iclass 13, count 2 2006.196.07:46:09.71#ibcon#about to read 3, iclass 13, count 2 2006.196.07:46:09.73#ibcon#read 3, iclass 13, count 2 2006.196.07:46:09.73#ibcon#about to read 4, iclass 13, count 2 2006.196.07:46:09.73#ibcon#read 4, iclass 13, count 2 2006.196.07:46:09.73#ibcon#about to read 5, iclass 13, count 2 2006.196.07:46:09.73#ibcon#read 5, iclass 13, count 2 2006.196.07:46:09.73#ibcon#about to read 6, iclass 13, count 2 2006.196.07:46:09.73#ibcon#read 6, iclass 13, count 2 2006.196.07:46:09.73#ibcon#end of sib2, iclass 13, count 2 2006.196.07:46:09.73#ibcon#*mode == 0, iclass 13, count 2 2006.196.07:46:09.73#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.196.07:46:09.73#ibcon#[25=AT06-06\r\n] 2006.196.07:46:09.73#ibcon#*before write, iclass 13, count 2 2006.196.07:46:09.73#ibcon#enter sib2, iclass 13, count 2 2006.196.07:46:09.73#ibcon#flushed, iclass 13, count 2 2006.196.07:46:09.73#ibcon#about to write, iclass 13, count 2 2006.196.07:46:09.73#ibcon#wrote, iclass 13, count 2 2006.196.07:46:09.73#ibcon#about to read 3, iclass 13, count 2 2006.196.07:46:09.76#ibcon#read 3, iclass 13, count 2 2006.196.07:46:09.76#ibcon#about to read 4, iclass 13, count 2 2006.196.07:46:09.76#ibcon#read 4, iclass 13, count 2 2006.196.07:46:09.76#ibcon#about to read 5, iclass 13, count 2 2006.196.07:46:09.76#ibcon#read 5, iclass 13, count 2 2006.196.07:46:09.76#ibcon#about to read 6, iclass 13, count 2 2006.196.07:46:09.76#ibcon#read 6, iclass 13, count 2 2006.196.07:46:09.76#ibcon#end of sib2, iclass 13, count 2 2006.196.07:46:09.76#ibcon#*after write, iclass 13, count 2 2006.196.07:46:09.76#ibcon#*before return 0, iclass 13, count 2 2006.196.07:46:09.76#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.196.07:46:09.76#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.196.07:46:09.76#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.196.07:46:09.76#ibcon#ireg 7 cls_cnt 0 2006.196.07:46:09.76#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.196.07:46:09.88#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.196.07:46:09.88#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.196.07:46:09.88#ibcon#enter wrdev, iclass 13, count 0 2006.196.07:46:09.88#ibcon#first serial, iclass 13, count 0 2006.196.07:46:09.88#ibcon#enter sib2, iclass 13, count 0 2006.196.07:46:09.88#ibcon#flushed, iclass 13, count 0 2006.196.07:46:09.88#ibcon#about to write, iclass 13, count 0 2006.196.07:46:09.88#ibcon#wrote, iclass 13, count 0 2006.196.07:46:09.88#ibcon#about to read 3, iclass 13, count 0 2006.196.07:46:09.90#ibcon#read 3, iclass 13, count 0 2006.196.07:46:09.90#ibcon#about to read 4, iclass 13, count 0 2006.196.07:46:09.90#ibcon#read 4, iclass 13, count 0 2006.196.07:46:09.90#ibcon#about to read 5, iclass 13, count 0 2006.196.07:46:09.90#ibcon#read 5, iclass 13, count 0 2006.196.07:46:09.90#ibcon#about to read 6, iclass 13, count 0 2006.196.07:46:09.90#ibcon#read 6, iclass 13, count 0 2006.196.07:46:09.90#ibcon#end of sib2, iclass 13, count 0 2006.196.07:46:09.90#ibcon#*mode == 0, iclass 13, count 0 2006.196.07:46:09.90#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.196.07:46:09.90#ibcon#[25=USB\r\n] 2006.196.07:46:09.90#ibcon#*before write, iclass 13, count 0 2006.196.07:46:09.90#ibcon#enter sib2, iclass 13, count 0 2006.196.07:46:09.90#ibcon#flushed, iclass 13, count 0 2006.196.07:46:09.90#ibcon#about to write, iclass 13, count 0 2006.196.07:46:09.90#ibcon#wrote, iclass 13, count 0 2006.196.07:46:09.90#ibcon#about to read 3, iclass 13, count 0 2006.196.07:46:09.93#ibcon#read 3, iclass 13, count 0 2006.196.07:46:09.93#ibcon#about to read 4, iclass 13, count 0 2006.196.07:46:09.93#ibcon#read 4, iclass 13, count 0 2006.196.07:46:09.93#ibcon#about to read 5, iclass 13, count 0 2006.196.07:46:09.93#ibcon#read 5, iclass 13, count 0 2006.196.07:46:09.93#ibcon#about to read 6, iclass 13, count 0 2006.196.07:46:09.93#ibcon#read 6, iclass 13, count 0 2006.196.07:46:09.93#ibcon#end of sib2, iclass 13, count 0 2006.196.07:46:09.93#ibcon#*after write, iclass 13, count 0 2006.196.07:46:09.93#ibcon#*before return 0, iclass 13, count 0 2006.196.07:46:09.93#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.196.07:46:09.93#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.196.07:46:09.93#ibcon#about to clear, iclass 13 cls_cnt 0 2006.196.07:46:09.93#ibcon#cleared, iclass 13 cls_cnt 0 2006.196.07:46:09.93$vc4f8/valo=7,832.99 2006.196.07:46:09.93#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.196.07:46:09.93#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.196.07:46:09.93#ibcon#ireg 17 cls_cnt 0 2006.196.07:46:09.93#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.196.07:46:09.93#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.196.07:46:09.93#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.196.07:46:09.93#ibcon#enter wrdev, iclass 15, count 0 2006.196.07:46:09.93#ibcon#first serial, iclass 15, count 0 2006.196.07:46:09.93#ibcon#enter sib2, iclass 15, count 0 2006.196.07:46:09.93#ibcon#flushed, iclass 15, count 0 2006.196.07:46:09.93#ibcon#about to write, iclass 15, count 0 2006.196.07:46:09.93#ibcon#wrote, iclass 15, count 0 2006.196.07:46:09.93#ibcon#about to read 3, iclass 15, count 0 2006.196.07:46:09.95#ibcon#read 3, iclass 15, count 0 2006.196.07:46:09.95#ibcon#about to read 4, iclass 15, count 0 2006.196.07:46:09.95#ibcon#read 4, iclass 15, count 0 2006.196.07:46:09.95#ibcon#about to read 5, iclass 15, count 0 2006.196.07:46:09.95#ibcon#read 5, iclass 15, count 0 2006.196.07:46:09.95#ibcon#about to read 6, iclass 15, count 0 2006.196.07:46:09.95#ibcon#read 6, iclass 15, count 0 2006.196.07:46:09.95#ibcon#end of sib2, iclass 15, count 0 2006.196.07:46:09.95#ibcon#*mode == 0, iclass 15, count 0 2006.196.07:46:09.95#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.196.07:46:09.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.196.07:46:09.95#ibcon#*before write, iclass 15, count 0 2006.196.07:46:09.95#ibcon#enter sib2, iclass 15, count 0 2006.196.07:46:09.95#ibcon#flushed, iclass 15, count 0 2006.196.07:46:09.95#ibcon#about to write, iclass 15, count 0 2006.196.07:46:09.95#ibcon#wrote, iclass 15, count 0 2006.196.07:46:09.95#ibcon#about to read 3, iclass 15, count 0 2006.196.07:46:09.99#ibcon#read 3, iclass 15, count 0 2006.196.07:46:09.99#ibcon#about to read 4, iclass 15, count 0 2006.196.07:46:09.99#ibcon#read 4, iclass 15, count 0 2006.196.07:46:09.99#ibcon#about to read 5, iclass 15, count 0 2006.196.07:46:09.99#ibcon#read 5, iclass 15, count 0 2006.196.07:46:09.99#ibcon#about to read 6, iclass 15, count 0 2006.196.07:46:09.99#ibcon#read 6, iclass 15, count 0 2006.196.07:46:09.99#ibcon#end of sib2, iclass 15, count 0 2006.196.07:46:09.99#ibcon#*after write, iclass 15, count 0 2006.196.07:46:09.99#ibcon#*before return 0, iclass 15, count 0 2006.196.07:46:09.99#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.196.07:46:09.99#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.196.07:46:09.99#ibcon#about to clear, iclass 15 cls_cnt 0 2006.196.07:46:09.99#ibcon#cleared, iclass 15 cls_cnt 0 2006.196.07:46:09.99$vc4f8/va=7,6 2006.196.07:46:09.99#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.196.07:46:09.99#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.196.07:46:09.99#ibcon#ireg 11 cls_cnt 2 2006.196.07:46:09.99#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.196.07:46:10.05#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.196.07:46:10.05#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.196.07:46:10.05#ibcon#enter wrdev, iclass 17, count 2 2006.196.07:46:10.05#ibcon#first serial, iclass 17, count 2 2006.196.07:46:10.05#ibcon#enter sib2, iclass 17, count 2 2006.196.07:46:10.05#ibcon#flushed, iclass 17, count 2 2006.196.07:46:10.05#ibcon#about to write, iclass 17, count 2 2006.196.07:46:10.05#ibcon#wrote, iclass 17, count 2 2006.196.07:46:10.05#ibcon#about to read 3, iclass 17, count 2 2006.196.07:46:10.07#ibcon#read 3, iclass 17, count 2 2006.196.07:46:10.07#ibcon#about to read 4, iclass 17, count 2 2006.196.07:46:10.07#ibcon#read 4, iclass 17, count 2 2006.196.07:46:10.07#ibcon#about to read 5, iclass 17, count 2 2006.196.07:46:10.07#ibcon#read 5, iclass 17, count 2 2006.196.07:46:10.07#ibcon#about to read 6, iclass 17, count 2 2006.196.07:46:10.07#ibcon#read 6, iclass 17, count 2 2006.196.07:46:10.07#ibcon#end of sib2, iclass 17, count 2 2006.196.07:46:10.07#ibcon#*mode == 0, iclass 17, count 2 2006.196.07:46:10.07#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.196.07:46:10.07#ibcon#[25=AT07-06\r\n] 2006.196.07:46:10.07#ibcon#*before write, iclass 17, count 2 2006.196.07:46:10.07#ibcon#enter sib2, iclass 17, count 2 2006.196.07:46:10.07#ibcon#flushed, iclass 17, count 2 2006.196.07:46:10.07#ibcon#about to write, iclass 17, count 2 2006.196.07:46:10.07#ibcon#wrote, iclass 17, count 2 2006.196.07:46:10.07#ibcon#about to read 3, iclass 17, count 2 2006.196.07:46:10.10#ibcon#read 3, iclass 17, count 2 2006.196.07:46:10.10#ibcon#about to read 4, iclass 17, count 2 2006.196.07:46:10.10#ibcon#read 4, iclass 17, count 2 2006.196.07:46:10.10#ibcon#about to read 5, iclass 17, count 2 2006.196.07:46:10.10#ibcon#read 5, iclass 17, count 2 2006.196.07:46:10.10#ibcon#about to read 6, iclass 17, count 2 2006.196.07:46:10.10#ibcon#read 6, iclass 17, count 2 2006.196.07:46:10.10#ibcon#end of sib2, iclass 17, count 2 2006.196.07:46:10.10#ibcon#*after write, iclass 17, count 2 2006.196.07:46:10.10#ibcon#*before return 0, iclass 17, count 2 2006.196.07:46:10.10#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.196.07:46:10.10#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.196.07:46:10.10#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.196.07:46:10.10#ibcon#ireg 7 cls_cnt 0 2006.196.07:46:10.10#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.196.07:46:10.22#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.196.07:46:10.22#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.196.07:46:10.22#ibcon#enter wrdev, iclass 17, count 0 2006.196.07:46:10.22#ibcon#first serial, iclass 17, count 0 2006.196.07:46:10.22#ibcon#enter sib2, iclass 17, count 0 2006.196.07:46:10.22#ibcon#flushed, iclass 17, count 0 2006.196.07:46:10.22#ibcon#about to write, iclass 17, count 0 2006.196.07:46:10.22#ibcon#wrote, iclass 17, count 0 2006.196.07:46:10.22#ibcon#about to read 3, iclass 17, count 0 2006.196.07:46:10.25#ibcon#read 3, iclass 17, count 0 2006.196.07:46:10.25#ibcon#about to read 4, iclass 17, count 0 2006.196.07:46:10.25#ibcon#read 4, iclass 17, count 0 2006.196.07:46:10.25#ibcon#about to read 5, iclass 17, count 0 2006.196.07:46:10.25#ibcon#read 5, iclass 17, count 0 2006.196.07:46:10.25#ibcon#about to read 6, iclass 17, count 0 2006.196.07:46:10.25#ibcon#read 6, iclass 17, count 0 2006.196.07:46:10.25#ibcon#end of sib2, iclass 17, count 0 2006.196.07:46:10.25#ibcon#*mode == 0, iclass 17, count 0 2006.196.07:46:10.25#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.196.07:46:10.25#ibcon#[25=USB\r\n] 2006.196.07:46:10.25#ibcon#*before write, iclass 17, count 0 2006.196.07:46:10.25#ibcon#enter sib2, iclass 17, count 0 2006.196.07:46:10.25#ibcon#flushed, iclass 17, count 0 2006.196.07:46:10.25#ibcon#about to write, iclass 17, count 0 2006.196.07:46:10.25#ibcon#wrote, iclass 17, count 0 2006.196.07:46:10.25#ibcon#about to read 3, iclass 17, count 0 2006.196.07:46:10.28#ibcon#read 3, iclass 17, count 0 2006.196.07:46:10.28#ibcon#about to read 4, iclass 17, count 0 2006.196.07:46:10.28#ibcon#read 4, iclass 17, count 0 2006.196.07:46:10.28#ibcon#about to read 5, iclass 17, count 0 2006.196.07:46:10.28#ibcon#read 5, iclass 17, count 0 2006.196.07:46:10.28#ibcon#about to read 6, iclass 17, count 0 2006.196.07:46:10.28#ibcon#read 6, iclass 17, count 0 2006.196.07:46:10.28#ibcon#end of sib2, iclass 17, count 0 2006.196.07:46:10.28#ibcon#*after write, iclass 17, count 0 2006.196.07:46:10.28#ibcon#*before return 0, iclass 17, count 0 2006.196.07:46:10.28#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.196.07:46:10.28#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.196.07:46:10.28#ibcon#about to clear, iclass 17 cls_cnt 0 2006.196.07:46:10.28#ibcon#cleared, iclass 17 cls_cnt 0 2006.196.07:46:10.28$vc4f8/valo=8,852.99 2006.196.07:46:10.28#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.196.07:46:10.28#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.196.07:46:10.28#ibcon#ireg 17 cls_cnt 0 2006.196.07:46:10.28#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.196.07:46:10.28#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.196.07:46:10.28#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.196.07:46:10.28#ibcon#enter wrdev, iclass 19, count 0 2006.196.07:46:10.28#ibcon#first serial, iclass 19, count 0 2006.196.07:46:10.28#ibcon#enter sib2, iclass 19, count 0 2006.196.07:46:10.28#ibcon#flushed, iclass 19, count 0 2006.196.07:46:10.28#ibcon#about to write, iclass 19, count 0 2006.196.07:46:10.28#ibcon#wrote, iclass 19, count 0 2006.196.07:46:10.28#ibcon#about to read 3, iclass 19, count 0 2006.196.07:46:10.30#ibcon#read 3, iclass 19, count 0 2006.196.07:46:10.30#ibcon#about to read 4, iclass 19, count 0 2006.196.07:46:10.30#ibcon#read 4, iclass 19, count 0 2006.196.07:46:10.30#ibcon#about to read 5, iclass 19, count 0 2006.196.07:46:10.30#ibcon#read 5, iclass 19, count 0 2006.196.07:46:10.30#ibcon#about to read 6, iclass 19, count 0 2006.196.07:46:10.30#ibcon#read 6, iclass 19, count 0 2006.196.07:46:10.30#ibcon#end of sib2, iclass 19, count 0 2006.196.07:46:10.30#ibcon#*mode == 0, iclass 19, count 0 2006.196.07:46:10.30#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.196.07:46:10.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.196.07:46:10.30#ibcon#*before write, iclass 19, count 0 2006.196.07:46:10.30#ibcon#enter sib2, iclass 19, count 0 2006.196.07:46:10.30#ibcon#flushed, iclass 19, count 0 2006.196.07:46:10.30#ibcon#about to write, iclass 19, count 0 2006.196.07:46:10.30#ibcon#wrote, iclass 19, count 0 2006.196.07:46:10.30#ibcon#about to read 3, iclass 19, count 0 2006.196.07:46:10.34#ibcon#read 3, iclass 19, count 0 2006.196.07:46:10.34#ibcon#about to read 4, iclass 19, count 0 2006.196.07:46:10.34#ibcon#read 4, iclass 19, count 0 2006.196.07:46:10.34#ibcon#about to read 5, iclass 19, count 0 2006.196.07:46:10.34#ibcon#read 5, iclass 19, count 0 2006.196.07:46:10.34#ibcon#about to read 6, iclass 19, count 0 2006.196.07:46:10.34#ibcon#read 6, iclass 19, count 0 2006.196.07:46:10.34#ibcon#end of sib2, iclass 19, count 0 2006.196.07:46:10.34#ibcon#*after write, iclass 19, count 0 2006.196.07:46:10.34#ibcon#*before return 0, iclass 19, count 0 2006.196.07:46:10.34#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.196.07:46:10.34#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.196.07:46:10.34#ibcon#about to clear, iclass 19 cls_cnt 0 2006.196.07:46:10.34#ibcon#cleared, iclass 19 cls_cnt 0 2006.196.07:46:10.34$vc4f8/va=8,7 2006.196.07:46:10.34#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.196.07:46:10.34#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.196.07:46:10.34#ibcon#ireg 11 cls_cnt 2 2006.196.07:46:10.34#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.196.07:46:10.40#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.196.07:46:10.40#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.196.07:46:10.40#ibcon#enter wrdev, iclass 21, count 2 2006.196.07:46:10.40#ibcon#first serial, iclass 21, count 2 2006.196.07:46:10.40#ibcon#enter sib2, iclass 21, count 2 2006.196.07:46:10.40#ibcon#flushed, iclass 21, count 2 2006.196.07:46:10.40#ibcon#about to write, iclass 21, count 2 2006.196.07:46:10.40#ibcon#wrote, iclass 21, count 2 2006.196.07:46:10.40#ibcon#about to read 3, iclass 21, count 2 2006.196.07:46:10.42#ibcon#read 3, iclass 21, count 2 2006.196.07:46:10.42#ibcon#about to read 4, iclass 21, count 2 2006.196.07:46:10.42#ibcon#read 4, iclass 21, count 2 2006.196.07:46:10.42#ibcon#about to read 5, iclass 21, count 2 2006.196.07:46:10.42#ibcon#read 5, iclass 21, count 2 2006.196.07:46:10.42#ibcon#about to read 6, iclass 21, count 2 2006.196.07:46:10.42#ibcon#read 6, iclass 21, count 2 2006.196.07:46:10.42#ibcon#end of sib2, iclass 21, count 2 2006.196.07:46:10.42#ibcon#*mode == 0, iclass 21, count 2 2006.196.07:46:10.42#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.196.07:46:10.42#ibcon#[25=AT08-07\r\n] 2006.196.07:46:10.42#ibcon#*before write, iclass 21, count 2 2006.196.07:46:10.42#ibcon#enter sib2, iclass 21, count 2 2006.196.07:46:10.42#ibcon#flushed, iclass 21, count 2 2006.196.07:46:10.42#ibcon#about to write, iclass 21, count 2 2006.196.07:46:10.42#ibcon#wrote, iclass 21, count 2 2006.196.07:46:10.42#ibcon#about to read 3, iclass 21, count 2 2006.196.07:46:10.45#ibcon#read 3, iclass 21, count 2 2006.196.07:46:10.45#ibcon#about to read 4, iclass 21, count 2 2006.196.07:46:10.45#ibcon#read 4, iclass 21, count 2 2006.196.07:46:10.45#ibcon#about to read 5, iclass 21, count 2 2006.196.07:46:10.45#ibcon#read 5, iclass 21, count 2 2006.196.07:46:10.45#ibcon#about to read 6, iclass 21, count 2 2006.196.07:46:10.45#ibcon#read 6, iclass 21, count 2 2006.196.07:46:10.45#ibcon#end of sib2, iclass 21, count 2 2006.196.07:46:10.45#ibcon#*after write, iclass 21, count 2 2006.196.07:46:10.45#ibcon#*before return 0, iclass 21, count 2 2006.196.07:46:10.45#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.196.07:46:10.45#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.196.07:46:10.45#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.196.07:46:10.45#ibcon#ireg 7 cls_cnt 0 2006.196.07:46:10.45#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.196.07:46:10.57#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.196.07:46:10.57#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.196.07:46:10.57#ibcon#enter wrdev, iclass 21, count 0 2006.196.07:46:10.57#ibcon#first serial, iclass 21, count 0 2006.196.07:46:10.57#ibcon#enter sib2, iclass 21, count 0 2006.196.07:46:10.57#ibcon#flushed, iclass 21, count 0 2006.196.07:46:10.57#ibcon#about to write, iclass 21, count 0 2006.196.07:46:10.57#ibcon#wrote, iclass 21, count 0 2006.196.07:46:10.57#ibcon#about to read 3, iclass 21, count 0 2006.196.07:46:10.59#ibcon#read 3, iclass 21, count 0 2006.196.07:46:10.59#ibcon#about to read 4, iclass 21, count 0 2006.196.07:46:10.59#ibcon#read 4, iclass 21, count 0 2006.196.07:46:10.59#ibcon#about to read 5, iclass 21, count 0 2006.196.07:46:10.59#ibcon#read 5, iclass 21, count 0 2006.196.07:46:10.59#ibcon#about to read 6, iclass 21, count 0 2006.196.07:46:10.59#ibcon#read 6, iclass 21, count 0 2006.196.07:46:10.59#ibcon#end of sib2, iclass 21, count 0 2006.196.07:46:10.59#ibcon#*mode == 0, iclass 21, count 0 2006.196.07:46:10.59#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.196.07:46:10.59#ibcon#[25=USB\r\n] 2006.196.07:46:10.59#ibcon#*before write, iclass 21, count 0 2006.196.07:46:10.59#ibcon#enter sib2, iclass 21, count 0 2006.196.07:46:10.59#ibcon#flushed, iclass 21, count 0 2006.196.07:46:10.59#ibcon#about to write, iclass 21, count 0 2006.196.07:46:10.59#ibcon#wrote, iclass 21, count 0 2006.196.07:46:10.59#ibcon#about to read 3, iclass 21, count 0 2006.196.07:46:10.62#ibcon#read 3, iclass 21, count 0 2006.196.07:46:10.62#ibcon#about to read 4, iclass 21, count 0 2006.196.07:46:10.62#ibcon#read 4, iclass 21, count 0 2006.196.07:46:10.62#ibcon#about to read 5, iclass 21, count 0 2006.196.07:46:10.62#ibcon#read 5, iclass 21, count 0 2006.196.07:46:10.62#ibcon#about to read 6, iclass 21, count 0 2006.196.07:46:10.62#ibcon#read 6, iclass 21, count 0 2006.196.07:46:10.62#ibcon#end of sib2, iclass 21, count 0 2006.196.07:46:10.62#ibcon#*after write, iclass 21, count 0 2006.196.07:46:10.62#ibcon#*before return 0, iclass 21, count 0 2006.196.07:46:10.62#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.196.07:46:10.62#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.196.07:46:10.62#ibcon#about to clear, iclass 21 cls_cnt 0 2006.196.07:46:10.62#ibcon#cleared, iclass 21 cls_cnt 0 2006.196.07:46:10.62$vc4f8/vblo=1,632.99 2006.196.07:46:10.62#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.196.07:46:10.62#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.196.07:46:10.62#ibcon#ireg 17 cls_cnt 0 2006.196.07:46:10.62#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.196.07:46:10.62#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.196.07:46:10.62#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.196.07:46:10.62#ibcon#enter wrdev, iclass 23, count 0 2006.196.07:46:10.62#ibcon#first serial, iclass 23, count 0 2006.196.07:46:10.62#ibcon#enter sib2, iclass 23, count 0 2006.196.07:46:10.62#ibcon#flushed, iclass 23, count 0 2006.196.07:46:10.62#ibcon#about to write, iclass 23, count 0 2006.196.07:46:10.62#ibcon#wrote, iclass 23, count 0 2006.196.07:46:10.62#ibcon#about to read 3, iclass 23, count 0 2006.196.07:46:10.64#ibcon#read 3, iclass 23, count 0 2006.196.07:46:10.64#ibcon#about to read 4, iclass 23, count 0 2006.196.07:46:10.64#ibcon#read 4, iclass 23, count 0 2006.196.07:46:10.64#ibcon#about to read 5, iclass 23, count 0 2006.196.07:46:10.64#ibcon#read 5, iclass 23, count 0 2006.196.07:46:10.64#ibcon#about to read 6, iclass 23, count 0 2006.196.07:46:10.64#ibcon#read 6, iclass 23, count 0 2006.196.07:46:10.64#ibcon#end of sib2, iclass 23, count 0 2006.196.07:46:10.64#ibcon#*mode == 0, iclass 23, count 0 2006.196.07:46:10.64#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.196.07:46:10.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.196.07:46:10.64#ibcon#*before write, iclass 23, count 0 2006.196.07:46:10.64#ibcon#enter sib2, iclass 23, count 0 2006.196.07:46:10.64#ibcon#flushed, iclass 23, count 0 2006.196.07:46:10.64#ibcon#about to write, iclass 23, count 0 2006.196.07:46:10.64#ibcon#wrote, iclass 23, count 0 2006.196.07:46:10.64#ibcon#about to read 3, iclass 23, count 0 2006.196.07:46:10.68#ibcon#read 3, iclass 23, count 0 2006.196.07:46:10.68#ibcon#about to read 4, iclass 23, count 0 2006.196.07:46:10.68#ibcon#read 4, iclass 23, count 0 2006.196.07:46:10.68#ibcon#about to read 5, iclass 23, count 0 2006.196.07:46:10.68#ibcon#read 5, iclass 23, count 0 2006.196.07:46:10.68#ibcon#about to read 6, iclass 23, count 0 2006.196.07:46:10.68#ibcon#read 6, iclass 23, count 0 2006.196.07:46:10.68#ibcon#end of sib2, iclass 23, count 0 2006.196.07:46:10.68#ibcon#*after write, iclass 23, count 0 2006.196.07:46:10.68#ibcon#*before return 0, iclass 23, count 0 2006.196.07:46:10.68#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.196.07:46:10.68#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.196.07:46:10.68#ibcon#about to clear, iclass 23 cls_cnt 0 2006.196.07:46:10.68#ibcon#cleared, iclass 23 cls_cnt 0 2006.196.07:46:10.68$vc4f8/vb=1,4 2006.196.07:46:10.68#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.196.07:46:10.68#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.196.07:46:10.68#ibcon#ireg 11 cls_cnt 2 2006.196.07:46:10.68#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.196.07:46:10.68#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.196.07:46:10.68#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.196.07:46:10.68#ibcon#enter wrdev, iclass 25, count 2 2006.196.07:46:10.68#ibcon#first serial, iclass 25, count 2 2006.196.07:46:10.68#ibcon#enter sib2, iclass 25, count 2 2006.196.07:46:10.68#ibcon#flushed, iclass 25, count 2 2006.196.07:46:10.68#ibcon#about to write, iclass 25, count 2 2006.196.07:46:10.68#ibcon#wrote, iclass 25, count 2 2006.196.07:46:10.68#ibcon#about to read 3, iclass 25, count 2 2006.196.07:46:10.70#ibcon#read 3, iclass 25, count 2 2006.196.07:46:10.70#ibcon#about to read 4, iclass 25, count 2 2006.196.07:46:10.70#ibcon#read 4, iclass 25, count 2 2006.196.07:46:10.70#ibcon#about to read 5, iclass 25, count 2 2006.196.07:46:10.70#ibcon#read 5, iclass 25, count 2 2006.196.07:46:10.70#ibcon#about to read 6, iclass 25, count 2 2006.196.07:46:10.70#ibcon#read 6, iclass 25, count 2 2006.196.07:46:10.70#ibcon#end of sib2, iclass 25, count 2 2006.196.07:46:10.70#ibcon#*mode == 0, iclass 25, count 2 2006.196.07:46:10.70#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.196.07:46:10.70#ibcon#[27=AT01-04\r\n] 2006.196.07:46:10.70#ibcon#*before write, iclass 25, count 2 2006.196.07:46:10.70#ibcon#enter sib2, iclass 25, count 2 2006.196.07:46:10.70#ibcon#flushed, iclass 25, count 2 2006.196.07:46:10.70#ibcon#about to write, iclass 25, count 2 2006.196.07:46:10.70#ibcon#wrote, iclass 25, count 2 2006.196.07:46:10.70#ibcon#about to read 3, iclass 25, count 2 2006.196.07:46:10.73#ibcon#read 3, iclass 25, count 2 2006.196.07:46:10.73#ibcon#about to read 4, iclass 25, count 2 2006.196.07:46:10.73#ibcon#read 4, iclass 25, count 2 2006.196.07:46:10.73#ibcon#about to read 5, iclass 25, count 2 2006.196.07:46:10.73#ibcon#read 5, iclass 25, count 2 2006.196.07:46:10.73#ibcon#about to read 6, iclass 25, count 2 2006.196.07:46:10.73#ibcon#read 6, iclass 25, count 2 2006.196.07:46:10.73#ibcon#end of sib2, iclass 25, count 2 2006.196.07:46:10.73#ibcon#*after write, iclass 25, count 2 2006.196.07:46:10.73#ibcon#*before return 0, iclass 25, count 2 2006.196.07:46:10.73#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.196.07:46:10.73#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.196.07:46:10.73#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.196.07:46:10.73#ibcon#ireg 7 cls_cnt 0 2006.196.07:46:10.73#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.196.07:46:10.85#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.196.07:46:10.85#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.196.07:46:10.85#ibcon#enter wrdev, iclass 25, count 0 2006.196.07:46:10.85#ibcon#first serial, iclass 25, count 0 2006.196.07:46:10.85#ibcon#enter sib2, iclass 25, count 0 2006.196.07:46:10.85#ibcon#flushed, iclass 25, count 0 2006.196.07:46:10.85#ibcon#about to write, iclass 25, count 0 2006.196.07:46:10.85#ibcon#wrote, iclass 25, count 0 2006.196.07:46:10.85#ibcon#about to read 3, iclass 25, count 0 2006.196.07:46:10.87#ibcon#read 3, iclass 25, count 0 2006.196.07:46:10.87#ibcon#about to read 4, iclass 25, count 0 2006.196.07:46:10.87#ibcon#read 4, iclass 25, count 0 2006.196.07:46:10.87#ibcon#about to read 5, iclass 25, count 0 2006.196.07:46:10.87#ibcon#read 5, iclass 25, count 0 2006.196.07:46:10.87#ibcon#about to read 6, iclass 25, count 0 2006.196.07:46:10.87#ibcon#read 6, iclass 25, count 0 2006.196.07:46:10.87#ibcon#end of sib2, iclass 25, count 0 2006.196.07:46:10.87#ibcon#*mode == 0, iclass 25, count 0 2006.196.07:46:10.87#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.196.07:46:10.87#ibcon#[27=USB\r\n] 2006.196.07:46:10.87#ibcon#*before write, iclass 25, count 0 2006.196.07:46:10.87#ibcon#enter sib2, iclass 25, count 0 2006.196.07:46:10.87#ibcon#flushed, iclass 25, count 0 2006.196.07:46:10.87#ibcon#about to write, iclass 25, count 0 2006.196.07:46:10.87#ibcon#wrote, iclass 25, count 0 2006.196.07:46:10.87#ibcon#about to read 3, iclass 25, count 0 2006.196.07:46:10.90#ibcon#read 3, iclass 25, count 0 2006.196.07:46:10.90#ibcon#about to read 4, iclass 25, count 0 2006.196.07:46:10.90#ibcon#read 4, iclass 25, count 0 2006.196.07:46:10.90#ibcon#about to read 5, iclass 25, count 0 2006.196.07:46:10.90#ibcon#read 5, iclass 25, count 0 2006.196.07:46:10.90#ibcon#about to read 6, iclass 25, count 0 2006.196.07:46:10.90#ibcon#read 6, iclass 25, count 0 2006.196.07:46:10.90#ibcon#end of sib2, iclass 25, count 0 2006.196.07:46:10.90#ibcon#*after write, iclass 25, count 0 2006.196.07:46:10.90#ibcon#*before return 0, iclass 25, count 0 2006.196.07:46:10.90#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.196.07:46:10.90#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.196.07:46:10.90#ibcon#about to clear, iclass 25 cls_cnt 0 2006.196.07:46:10.90#ibcon#cleared, iclass 25 cls_cnt 0 2006.196.07:46:10.90$vc4f8/vblo=2,640.99 2006.196.07:46:10.90#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.196.07:46:10.90#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.196.07:46:10.90#ibcon#ireg 17 cls_cnt 0 2006.196.07:46:10.90#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.196.07:46:10.90#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.196.07:46:10.90#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.196.07:46:10.90#ibcon#enter wrdev, iclass 27, count 0 2006.196.07:46:10.90#ibcon#first serial, iclass 27, count 0 2006.196.07:46:10.90#ibcon#enter sib2, iclass 27, count 0 2006.196.07:46:10.90#ibcon#flushed, iclass 27, count 0 2006.196.07:46:10.90#ibcon#about to write, iclass 27, count 0 2006.196.07:46:10.90#ibcon#wrote, iclass 27, count 0 2006.196.07:46:10.90#ibcon#about to read 3, iclass 27, count 0 2006.196.07:46:10.92#ibcon#read 3, iclass 27, count 0 2006.196.07:46:10.92#ibcon#about to read 4, iclass 27, count 0 2006.196.07:46:10.92#ibcon#read 4, iclass 27, count 0 2006.196.07:46:10.92#ibcon#about to read 5, iclass 27, count 0 2006.196.07:46:10.92#ibcon#read 5, iclass 27, count 0 2006.196.07:46:10.92#ibcon#about to read 6, iclass 27, count 0 2006.196.07:46:10.92#ibcon#read 6, iclass 27, count 0 2006.196.07:46:10.92#ibcon#end of sib2, iclass 27, count 0 2006.196.07:46:10.92#ibcon#*mode == 0, iclass 27, count 0 2006.196.07:46:10.92#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.196.07:46:10.92#ibcon#[28=FRQ=02,640.99\r\n] 2006.196.07:46:10.92#ibcon#*before write, iclass 27, count 0 2006.196.07:46:10.92#ibcon#enter sib2, iclass 27, count 0 2006.196.07:46:10.92#ibcon#flushed, iclass 27, count 0 2006.196.07:46:10.92#ibcon#about to write, iclass 27, count 0 2006.196.07:46:10.92#ibcon#wrote, iclass 27, count 0 2006.196.07:46:10.92#ibcon#about to read 3, iclass 27, count 0 2006.196.07:46:10.96#ibcon#read 3, iclass 27, count 0 2006.196.07:46:10.96#ibcon#about to read 4, iclass 27, count 0 2006.196.07:46:10.96#ibcon#read 4, iclass 27, count 0 2006.196.07:46:10.96#ibcon#about to read 5, iclass 27, count 0 2006.196.07:46:10.96#ibcon#read 5, iclass 27, count 0 2006.196.07:46:10.96#ibcon#about to read 6, iclass 27, count 0 2006.196.07:46:10.96#ibcon#read 6, iclass 27, count 0 2006.196.07:46:10.96#ibcon#end of sib2, iclass 27, count 0 2006.196.07:46:10.96#ibcon#*after write, iclass 27, count 0 2006.196.07:46:10.96#ibcon#*before return 0, iclass 27, count 0 2006.196.07:46:10.96#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.196.07:46:10.96#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.196.07:46:10.96#ibcon#about to clear, iclass 27 cls_cnt 0 2006.196.07:46:10.96#ibcon#cleared, iclass 27 cls_cnt 0 2006.196.07:46:10.96$vc4f8/vb=2,4 2006.196.07:46:10.96#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.196.07:46:10.96#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.196.07:46:10.96#ibcon#ireg 11 cls_cnt 2 2006.196.07:46:10.96#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.196.07:46:10.98#abcon#<5=/04 4.2 6.7 29.77 881004.0\r\n> 2006.196.07:46:11.00#abcon#{5=INTERFACE CLEAR} 2006.196.07:46:11.02#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.196.07:46:11.02#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.196.07:46:11.02#ibcon#enter wrdev, iclass 30, count 2 2006.196.07:46:11.02#ibcon#first serial, iclass 30, count 2 2006.196.07:46:11.02#ibcon#enter sib2, iclass 30, count 2 2006.196.07:46:11.02#ibcon#flushed, iclass 30, count 2 2006.196.07:46:11.02#ibcon#about to write, iclass 30, count 2 2006.196.07:46:11.02#ibcon#wrote, iclass 30, count 2 2006.196.07:46:11.02#ibcon#about to read 3, iclass 30, count 2 2006.196.07:46:11.04#ibcon#read 3, iclass 30, count 2 2006.196.07:46:11.04#ibcon#about to read 4, iclass 30, count 2 2006.196.07:46:11.04#ibcon#read 4, iclass 30, count 2 2006.196.07:46:11.04#ibcon#about to read 5, iclass 30, count 2 2006.196.07:46:11.04#ibcon#read 5, iclass 30, count 2 2006.196.07:46:11.04#ibcon#about to read 6, iclass 30, count 2 2006.196.07:46:11.04#ibcon#read 6, iclass 30, count 2 2006.196.07:46:11.04#ibcon#end of sib2, iclass 30, count 2 2006.196.07:46:11.04#ibcon#*mode == 0, iclass 30, count 2 2006.196.07:46:11.04#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.196.07:46:11.04#ibcon#[27=AT02-04\r\n] 2006.196.07:46:11.04#ibcon#*before write, iclass 30, count 2 2006.196.07:46:11.04#ibcon#enter sib2, iclass 30, count 2 2006.196.07:46:11.04#ibcon#flushed, iclass 30, count 2 2006.196.07:46:11.04#ibcon#about to write, iclass 30, count 2 2006.196.07:46:11.04#ibcon#wrote, iclass 30, count 2 2006.196.07:46:11.04#ibcon#about to read 3, iclass 30, count 2 2006.196.07:46:11.06#abcon#[5=S1D000X0/0*\r\n] 2006.196.07:46:11.07#ibcon#read 3, iclass 30, count 2 2006.196.07:46:11.07#ibcon#about to read 4, iclass 30, count 2 2006.196.07:46:11.07#ibcon#read 4, iclass 30, count 2 2006.196.07:46:11.07#ibcon#about to read 5, iclass 30, count 2 2006.196.07:46:11.07#ibcon#read 5, iclass 30, count 2 2006.196.07:46:11.07#ibcon#about to read 6, iclass 30, count 2 2006.196.07:46:11.07#ibcon#read 6, iclass 30, count 2 2006.196.07:46:11.07#ibcon#end of sib2, iclass 30, count 2 2006.196.07:46:11.07#ibcon#*after write, iclass 30, count 2 2006.196.07:46:11.07#ibcon#*before return 0, iclass 30, count 2 2006.196.07:46:11.07#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.196.07:46:11.07#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.196.07:46:11.07#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.196.07:46:11.07#ibcon#ireg 7 cls_cnt 0 2006.196.07:46:11.07#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.196.07:46:11.19#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.196.07:46:11.19#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.196.07:46:11.19#ibcon#enter wrdev, iclass 30, count 0 2006.196.07:46:11.19#ibcon#first serial, iclass 30, count 0 2006.196.07:46:11.19#ibcon#enter sib2, iclass 30, count 0 2006.196.07:46:11.19#ibcon#flushed, iclass 30, count 0 2006.196.07:46:11.19#ibcon#about to write, iclass 30, count 0 2006.196.07:46:11.19#ibcon#wrote, iclass 30, count 0 2006.196.07:46:11.19#ibcon#about to read 3, iclass 30, count 0 2006.196.07:46:11.21#ibcon#read 3, iclass 30, count 0 2006.196.07:46:11.21#ibcon#about to read 4, iclass 30, count 0 2006.196.07:46:11.21#ibcon#read 4, iclass 30, count 0 2006.196.07:46:11.21#ibcon#about to read 5, iclass 30, count 0 2006.196.07:46:11.21#ibcon#read 5, iclass 30, count 0 2006.196.07:46:11.21#ibcon#about to read 6, iclass 30, count 0 2006.196.07:46:11.21#ibcon#read 6, iclass 30, count 0 2006.196.07:46:11.21#ibcon#end of sib2, iclass 30, count 0 2006.196.07:46:11.21#ibcon#*mode == 0, iclass 30, count 0 2006.196.07:46:11.21#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.196.07:46:11.21#ibcon#[27=USB\r\n] 2006.196.07:46:11.21#ibcon#*before write, iclass 30, count 0 2006.196.07:46:11.21#ibcon#enter sib2, iclass 30, count 0 2006.196.07:46:11.21#ibcon#flushed, iclass 30, count 0 2006.196.07:46:11.21#ibcon#about to write, iclass 30, count 0 2006.196.07:46:11.21#ibcon#wrote, iclass 30, count 0 2006.196.07:46:11.21#ibcon#about to read 3, iclass 30, count 0 2006.196.07:46:11.24#ibcon#read 3, iclass 30, count 0 2006.196.07:46:11.24#ibcon#about to read 4, iclass 30, count 0 2006.196.07:46:11.24#ibcon#read 4, iclass 30, count 0 2006.196.07:46:11.24#ibcon#about to read 5, iclass 30, count 0 2006.196.07:46:11.24#ibcon#read 5, iclass 30, count 0 2006.196.07:46:11.24#ibcon#about to read 6, iclass 30, count 0 2006.196.07:46:11.24#ibcon#read 6, iclass 30, count 0 2006.196.07:46:11.24#ibcon#end of sib2, iclass 30, count 0 2006.196.07:46:11.24#ibcon#*after write, iclass 30, count 0 2006.196.07:46:11.24#ibcon#*before return 0, iclass 30, count 0 2006.196.07:46:11.24#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.196.07:46:11.24#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.196.07:46:11.24#ibcon#about to clear, iclass 30 cls_cnt 0 2006.196.07:46:11.24#ibcon#cleared, iclass 30 cls_cnt 0 2006.196.07:46:11.24$vc4f8/vblo=3,656.99 2006.196.07:46:11.24#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.196.07:46:11.24#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.196.07:46:11.24#ibcon#ireg 17 cls_cnt 0 2006.196.07:46:11.24#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.196.07:46:11.24#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.196.07:46:11.24#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.196.07:46:11.24#ibcon#enter wrdev, iclass 35, count 0 2006.196.07:46:11.24#ibcon#first serial, iclass 35, count 0 2006.196.07:46:11.24#ibcon#enter sib2, iclass 35, count 0 2006.196.07:46:11.24#ibcon#flushed, iclass 35, count 0 2006.196.07:46:11.24#ibcon#about to write, iclass 35, count 0 2006.196.07:46:11.24#ibcon#wrote, iclass 35, count 0 2006.196.07:46:11.24#ibcon#about to read 3, iclass 35, count 0 2006.196.07:46:11.26#ibcon#read 3, iclass 35, count 0 2006.196.07:46:11.26#ibcon#about to read 4, iclass 35, count 0 2006.196.07:46:11.26#ibcon#read 4, iclass 35, count 0 2006.196.07:46:11.26#ibcon#about to read 5, iclass 35, count 0 2006.196.07:46:11.26#ibcon#read 5, iclass 35, count 0 2006.196.07:46:11.26#ibcon#about to read 6, iclass 35, count 0 2006.196.07:46:11.26#ibcon#read 6, iclass 35, count 0 2006.196.07:46:11.26#ibcon#end of sib2, iclass 35, count 0 2006.196.07:46:11.26#ibcon#*mode == 0, iclass 35, count 0 2006.196.07:46:11.26#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.196.07:46:11.26#ibcon#[28=FRQ=03,656.99\r\n] 2006.196.07:46:11.26#ibcon#*before write, iclass 35, count 0 2006.196.07:46:11.26#ibcon#enter sib2, iclass 35, count 0 2006.196.07:46:11.26#ibcon#flushed, iclass 35, count 0 2006.196.07:46:11.26#ibcon#about to write, iclass 35, count 0 2006.196.07:46:11.26#ibcon#wrote, iclass 35, count 0 2006.196.07:46:11.26#ibcon#about to read 3, iclass 35, count 0 2006.196.07:46:11.30#ibcon#read 3, iclass 35, count 0 2006.196.07:46:11.30#ibcon#about to read 4, iclass 35, count 0 2006.196.07:46:11.30#ibcon#read 4, iclass 35, count 0 2006.196.07:46:11.30#ibcon#about to read 5, iclass 35, count 0 2006.196.07:46:11.30#ibcon#read 5, iclass 35, count 0 2006.196.07:46:11.30#ibcon#about to read 6, iclass 35, count 0 2006.196.07:46:11.30#ibcon#read 6, iclass 35, count 0 2006.196.07:46:11.30#ibcon#end of sib2, iclass 35, count 0 2006.196.07:46:11.30#ibcon#*after write, iclass 35, count 0 2006.196.07:46:11.30#ibcon#*before return 0, iclass 35, count 0 2006.196.07:46:11.30#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.196.07:46:11.30#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.196.07:46:11.30#ibcon#about to clear, iclass 35 cls_cnt 0 2006.196.07:46:11.30#ibcon#cleared, iclass 35 cls_cnt 0 2006.196.07:46:11.30$vc4f8/vb=3,4 2006.196.07:46:11.30#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.196.07:46:11.30#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.196.07:46:11.30#ibcon#ireg 11 cls_cnt 2 2006.196.07:46:11.30#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.196.07:46:11.36#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.196.07:46:11.36#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.196.07:46:11.36#ibcon#enter wrdev, iclass 37, count 2 2006.196.07:46:11.36#ibcon#first serial, iclass 37, count 2 2006.196.07:46:11.36#ibcon#enter sib2, iclass 37, count 2 2006.196.07:46:11.36#ibcon#flushed, iclass 37, count 2 2006.196.07:46:11.36#ibcon#about to write, iclass 37, count 2 2006.196.07:46:11.36#ibcon#wrote, iclass 37, count 2 2006.196.07:46:11.36#ibcon#about to read 3, iclass 37, count 2 2006.196.07:46:11.38#ibcon#read 3, iclass 37, count 2 2006.196.07:46:11.38#ibcon#about to read 4, iclass 37, count 2 2006.196.07:46:11.38#ibcon#read 4, iclass 37, count 2 2006.196.07:46:11.38#ibcon#about to read 5, iclass 37, count 2 2006.196.07:46:11.38#ibcon#read 5, iclass 37, count 2 2006.196.07:46:11.38#ibcon#about to read 6, iclass 37, count 2 2006.196.07:46:11.38#ibcon#read 6, iclass 37, count 2 2006.196.07:46:11.38#ibcon#end of sib2, iclass 37, count 2 2006.196.07:46:11.38#ibcon#*mode == 0, iclass 37, count 2 2006.196.07:46:11.38#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.196.07:46:11.38#ibcon#[27=AT03-04\r\n] 2006.196.07:46:11.38#ibcon#*before write, iclass 37, count 2 2006.196.07:46:11.38#ibcon#enter sib2, iclass 37, count 2 2006.196.07:46:11.38#ibcon#flushed, iclass 37, count 2 2006.196.07:46:11.38#ibcon#about to write, iclass 37, count 2 2006.196.07:46:11.38#ibcon#wrote, iclass 37, count 2 2006.196.07:46:11.38#ibcon#about to read 3, iclass 37, count 2 2006.196.07:46:11.41#ibcon#read 3, iclass 37, count 2 2006.196.07:46:11.41#ibcon#about to read 4, iclass 37, count 2 2006.196.07:46:11.41#ibcon#read 4, iclass 37, count 2 2006.196.07:46:11.41#ibcon#about to read 5, iclass 37, count 2 2006.196.07:46:11.41#ibcon#read 5, iclass 37, count 2 2006.196.07:46:11.41#ibcon#about to read 6, iclass 37, count 2 2006.196.07:46:11.41#ibcon#read 6, iclass 37, count 2 2006.196.07:46:11.41#ibcon#end of sib2, iclass 37, count 2 2006.196.07:46:11.41#ibcon#*after write, iclass 37, count 2 2006.196.07:46:11.41#ibcon#*before return 0, iclass 37, count 2 2006.196.07:46:11.41#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.196.07:46:11.41#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.196.07:46:11.41#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.196.07:46:11.41#ibcon#ireg 7 cls_cnt 0 2006.196.07:46:11.41#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.196.07:46:11.53#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.196.07:46:11.53#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.196.07:46:11.53#ibcon#enter wrdev, iclass 37, count 0 2006.196.07:46:11.53#ibcon#first serial, iclass 37, count 0 2006.196.07:46:11.53#ibcon#enter sib2, iclass 37, count 0 2006.196.07:46:11.53#ibcon#flushed, iclass 37, count 0 2006.196.07:46:11.53#ibcon#about to write, iclass 37, count 0 2006.196.07:46:11.53#ibcon#wrote, iclass 37, count 0 2006.196.07:46:11.53#ibcon#about to read 3, iclass 37, count 0 2006.196.07:46:11.55#ibcon#read 3, iclass 37, count 0 2006.196.07:46:11.55#ibcon#about to read 4, iclass 37, count 0 2006.196.07:46:11.55#ibcon#read 4, iclass 37, count 0 2006.196.07:46:11.55#ibcon#about to read 5, iclass 37, count 0 2006.196.07:46:11.55#ibcon#read 5, iclass 37, count 0 2006.196.07:46:11.55#ibcon#about to read 6, iclass 37, count 0 2006.196.07:46:11.55#ibcon#read 6, iclass 37, count 0 2006.196.07:46:11.55#ibcon#end of sib2, iclass 37, count 0 2006.196.07:46:11.55#ibcon#*mode == 0, iclass 37, count 0 2006.196.07:46:11.55#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.196.07:46:11.55#ibcon#[27=USB\r\n] 2006.196.07:46:11.55#ibcon#*before write, iclass 37, count 0 2006.196.07:46:11.55#ibcon#enter sib2, iclass 37, count 0 2006.196.07:46:11.55#ibcon#flushed, iclass 37, count 0 2006.196.07:46:11.55#ibcon#about to write, iclass 37, count 0 2006.196.07:46:11.55#ibcon#wrote, iclass 37, count 0 2006.196.07:46:11.55#ibcon#about to read 3, iclass 37, count 0 2006.196.07:46:11.58#ibcon#read 3, iclass 37, count 0 2006.196.07:46:11.58#ibcon#about to read 4, iclass 37, count 0 2006.196.07:46:11.58#ibcon#read 4, iclass 37, count 0 2006.196.07:46:11.58#ibcon#about to read 5, iclass 37, count 0 2006.196.07:46:11.58#ibcon#read 5, iclass 37, count 0 2006.196.07:46:11.58#ibcon#about to read 6, iclass 37, count 0 2006.196.07:46:11.58#ibcon#read 6, iclass 37, count 0 2006.196.07:46:11.58#ibcon#end of sib2, iclass 37, count 0 2006.196.07:46:11.58#ibcon#*after write, iclass 37, count 0 2006.196.07:46:11.58#ibcon#*before return 0, iclass 37, count 0 2006.196.07:46:11.58#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.196.07:46:11.58#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.196.07:46:11.58#ibcon#about to clear, iclass 37 cls_cnt 0 2006.196.07:46:11.58#ibcon#cleared, iclass 37 cls_cnt 0 2006.196.07:46:11.58$vc4f8/vblo=4,712.99 2006.196.07:46:11.58#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.196.07:46:11.58#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.196.07:46:11.58#ibcon#ireg 17 cls_cnt 0 2006.196.07:46:11.58#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.196.07:46:11.58#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.196.07:46:11.58#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.196.07:46:11.58#ibcon#enter wrdev, iclass 39, count 0 2006.196.07:46:11.58#ibcon#first serial, iclass 39, count 0 2006.196.07:46:11.58#ibcon#enter sib2, iclass 39, count 0 2006.196.07:46:11.58#ibcon#flushed, iclass 39, count 0 2006.196.07:46:11.58#ibcon#about to write, iclass 39, count 0 2006.196.07:46:11.58#ibcon#wrote, iclass 39, count 0 2006.196.07:46:11.58#ibcon#about to read 3, iclass 39, count 0 2006.196.07:46:11.60#ibcon#read 3, iclass 39, count 0 2006.196.07:46:11.60#ibcon#about to read 4, iclass 39, count 0 2006.196.07:46:11.60#ibcon#read 4, iclass 39, count 0 2006.196.07:46:11.60#ibcon#about to read 5, iclass 39, count 0 2006.196.07:46:11.60#ibcon#read 5, iclass 39, count 0 2006.196.07:46:11.60#ibcon#about to read 6, iclass 39, count 0 2006.196.07:46:11.60#ibcon#read 6, iclass 39, count 0 2006.196.07:46:11.60#ibcon#end of sib2, iclass 39, count 0 2006.196.07:46:11.60#ibcon#*mode == 0, iclass 39, count 0 2006.196.07:46:11.60#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.196.07:46:11.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.196.07:46:11.60#ibcon#*before write, iclass 39, count 0 2006.196.07:46:11.60#ibcon#enter sib2, iclass 39, count 0 2006.196.07:46:11.60#ibcon#flushed, iclass 39, count 0 2006.196.07:46:11.60#ibcon#about to write, iclass 39, count 0 2006.196.07:46:11.60#ibcon#wrote, iclass 39, count 0 2006.196.07:46:11.60#ibcon#about to read 3, iclass 39, count 0 2006.196.07:46:11.64#ibcon#read 3, iclass 39, count 0 2006.196.07:46:11.64#ibcon#about to read 4, iclass 39, count 0 2006.196.07:46:11.64#ibcon#read 4, iclass 39, count 0 2006.196.07:46:11.64#ibcon#about to read 5, iclass 39, count 0 2006.196.07:46:11.64#ibcon#read 5, iclass 39, count 0 2006.196.07:46:11.64#ibcon#about to read 6, iclass 39, count 0 2006.196.07:46:11.64#ibcon#read 6, iclass 39, count 0 2006.196.07:46:11.64#ibcon#end of sib2, iclass 39, count 0 2006.196.07:46:11.64#ibcon#*after write, iclass 39, count 0 2006.196.07:46:11.64#ibcon#*before return 0, iclass 39, count 0 2006.196.07:46:11.64#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.196.07:46:11.64#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.196.07:46:11.64#ibcon#about to clear, iclass 39 cls_cnt 0 2006.196.07:46:11.64#ibcon#cleared, iclass 39 cls_cnt 0 2006.196.07:46:11.64$vc4f8/vb=4,4 2006.196.07:46:11.64#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.196.07:46:11.64#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.196.07:46:11.64#ibcon#ireg 11 cls_cnt 2 2006.196.07:46:11.64#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.196.07:46:11.70#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.196.07:46:11.70#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.196.07:46:11.70#ibcon#enter wrdev, iclass 3, count 2 2006.196.07:46:11.70#ibcon#first serial, iclass 3, count 2 2006.196.07:46:11.70#ibcon#enter sib2, iclass 3, count 2 2006.196.07:46:11.70#ibcon#flushed, iclass 3, count 2 2006.196.07:46:11.70#ibcon#about to write, iclass 3, count 2 2006.196.07:46:11.70#ibcon#wrote, iclass 3, count 2 2006.196.07:46:11.70#ibcon#about to read 3, iclass 3, count 2 2006.196.07:46:11.72#ibcon#read 3, iclass 3, count 2 2006.196.07:46:11.72#ibcon#about to read 4, iclass 3, count 2 2006.196.07:46:11.72#ibcon#read 4, iclass 3, count 2 2006.196.07:46:11.72#ibcon#about to read 5, iclass 3, count 2 2006.196.07:46:11.72#ibcon#read 5, iclass 3, count 2 2006.196.07:46:11.72#ibcon#about to read 6, iclass 3, count 2 2006.196.07:46:11.72#ibcon#read 6, iclass 3, count 2 2006.196.07:46:11.72#ibcon#end of sib2, iclass 3, count 2 2006.196.07:46:11.72#ibcon#*mode == 0, iclass 3, count 2 2006.196.07:46:11.72#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.196.07:46:11.72#ibcon#[27=AT04-04\r\n] 2006.196.07:46:11.72#ibcon#*before write, iclass 3, count 2 2006.196.07:46:11.72#ibcon#enter sib2, iclass 3, count 2 2006.196.07:46:11.72#ibcon#flushed, iclass 3, count 2 2006.196.07:46:11.72#ibcon#about to write, iclass 3, count 2 2006.196.07:46:11.72#ibcon#wrote, iclass 3, count 2 2006.196.07:46:11.72#ibcon#about to read 3, iclass 3, count 2 2006.196.07:46:11.75#ibcon#read 3, iclass 3, count 2 2006.196.07:46:11.75#ibcon#about to read 4, iclass 3, count 2 2006.196.07:46:11.75#ibcon#read 4, iclass 3, count 2 2006.196.07:46:11.75#ibcon#about to read 5, iclass 3, count 2 2006.196.07:46:11.75#ibcon#read 5, iclass 3, count 2 2006.196.07:46:11.75#ibcon#about to read 6, iclass 3, count 2 2006.196.07:46:11.75#ibcon#read 6, iclass 3, count 2 2006.196.07:46:11.75#ibcon#end of sib2, iclass 3, count 2 2006.196.07:46:11.75#ibcon#*after write, iclass 3, count 2 2006.196.07:46:11.75#ibcon#*before return 0, iclass 3, count 2 2006.196.07:46:11.75#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.196.07:46:11.75#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.196.07:46:11.75#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.196.07:46:11.75#ibcon#ireg 7 cls_cnt 0 2006.196.07:46:11.75#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.196.07:46:11.87#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.196.07:46:11.87#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.196.07:46:11.87#ibcon#enter wrdev, iclass 3, count 0 2006.196.07:46:11.87#ibcon#first serial, iclass 3, count 0 2006.196.07:46:11.87#ibcon#enter sib2, iclass 3, count 0 2006.196.07:46:11.87#ibcon#flushed, iclass 3, count 0 2006.196.07:46:11.87#ibcon#about to write, iclass 3, count 0 2006.196.07:46:11.87#ibcon#wrote, iclass 3, count 0 2006.196.07:46:11.87#ibcon#about to read 3, iclass 3, count 0 2006.196.07:46:11.89#ibcon#read 3, iclass 3, count 0 2006.196.07:46:11.89#ibcon#about to read 4, iclass 3, count 0 2006.196.07:46:11.89#ibcon#read 4, iclass 3, count 0 2006.196.07:46:11.89#ibcon#about to read 5, iclass 3, count 0 2006.196.07:46:11.89#ibcon#read 5, iclass 3, count 0 2006.196.07:46:11.89#ibcon#about to read 6, iclass 3, count 0 2006.196.07:46:11.89#ibcon#read 6, iclass 3, count 0 2006.196.07:46:11.89#ibcon#end of sib2, iclass 3, count 0 2006.196.07:46:11.89#ibcon#*mode == 0, iclass 3, count 0 2006.196.07:46:11.89#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.196.07:46:11.89#ibcon#[27=USB\r\n] 2006.196.07:46:11.89#ibcon#*before write, iclass 3, count 0 2006.196.07:46:11.89#ibcon#enter sib2, iclass 3, count 0 2006.196.07:46:11.89#ibcon#flushed, iclass 3, count 0 2006.196.07:46:11.89#ibcon#about to write, iclass 3, count 0 2006.196.07:46:11.89#ibcon#wrote, iclass 3, count 0 2006.196.07:46:11.89#ibcon#about to read 3, iclass 3, count 0 2006.196.07:46:11.92#ibcon#read 3, iclass 3, count 0 2006.196.07:46:11.92#ibcon#about to read 4, iclass 3, count 0 2006.196.07:46:11.92#ibcon#read 4, iclass 3, count 0 2006.196.07:46:11.92#ibcon#about to read 5, iclass 3, count 0 2006.196.07:46:11.92#ibcon#read 5, iclass 3, count 0 2006.196.07:46:11.92#ibcon#about to read 6, iclass 3, count 0 2006.196.07:46:11.92#ibcon#read 6, iclass 3, count 0 2006.196.07:46:11.92#ibcon#end of sib2, iclass 3, count 0 2006.196.07:46:11.92#ibcon#*after write, iclass 3, count 0 2006.196.07:46:11.92#ibcon#*before return 0, iclass 3, count 0 2006.196.07:46:11.92#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.196.07:46:11.92#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.196.07:46:11.92#ibcon#about to clear, iclass 3 cls_cnt 0 2006.196.07:46:11.92#ibcon#cleared, iclass 3 cls_cnt 0 2006.196.07:46:11.92$vc4f8/vblo=5,744.99 2006.196.07:46:11.92#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.196.07:46:11.92#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.196.07:46:11.92#ibcon#ireg 17 cls_cnt 0 2006.196.07:46:11.92#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.196.07:46:11.92#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.196.07:46:11.92#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.196.07:46:11.92#ibcon#enter wrdev, iclass 5, count 0 2006.196.07:46:11.92#ibcon#first serial, iclass 5, count 0 2006.196.07:46:11.92#ibcon#enter sib2, iclass 5, count 0 2006.196.07:46:11.92#ibcon#flushed, iclass 5, count 0 2006.196.07:46:11.92#ibcon#about to write, iclass 5, count 0 2006.196.07:46:11.92#ibcon#wrote, iclass 5, count 0 2006.196.07:46:11.92#ibcon#about to read 3, iclass 5, count 0 2006.196.07:46:11.94#ibcon#read 3, iclass 5, count 0 2006.196.07:46:11.94#ibcon#about to read 4, iclass 5, count 0 2006.196.07:46:11.94#ibcon#read 4, iclass 5, count 0 2006.196.07:46:11.94#ibcon#about to read 5, iclass 5, count 0 2006.196.07:46:11.94#ibcon#read 5, iclass 5, count 0 2006.196.07:46:11.94#ibcon#about to read 6, iclass 5, count 0 2006.196.07:46:11.94#ibcon#read 6, iclass 5, count 0 2006.196.07:46:11.94#ibcon#end of sib2, iclass 5, count 0 2006.196.07:46:11.94#ibcon#*mode == 0, iclass 5, count 0 2006.196.07:46:11.94#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.196.07:46:11.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.196.07:46:11.94#ibcon#*before write, iclass 5, count 0 2006.196.07:46:11.94#ibcon#enter sib2, iclass 5, count 0 2006.196.07:46:11.94#ibcon#flushed, iclass 5, count 0 2006.196.07:46:11.94#ibcon#about to write, iclass 5, count 0 2006.196.07:46:11.94#ibcon#wrote, iclass 5, count 0 2006.196.07:46:11.94#ibcon#about to read 3, iclass 5, count 0 2006.196.07:46:11.98#ibcon#read 3, iclass 5, count 0 2006.196.07:46:11.98#ibcon#about to read 4, iclass 5, count 0 2006.196.07:46:11.98#ibcon#read 4, iclass 5, count 0 2006.196.07:46:11.98#ibcon#about to read 5, iclass 5, count 0 2006.196.07:46:11.98#ibcon#read 5, iclass 5, count 0 2006.196.07:46:11.98#ibcon#about to read 6, iclass 5, count 0 2006.196.07:46:11.98#ibcon#read 6, iclass 5, count 0 2006.196.07:46:11.98#ibcon#end of sib2, iclass 5, count 0 2006.196.07:46:11.98#ibcon#*after write, iclass 5, count 0 2006.196.07:46:11.98#ibcon#*before return 0, iclass 5, count 0 2006.196.07:46:11.98#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.196.07:46:11.98#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.196.07:46:11.98#ibcon#about to clear, iclass 5 cls_cnt 0 2006.196.07:46:11.98#ibcon#cleared, iclass 5 cls_cnt 0 2006.196.07:46:11.98$vc4f8/vb=5,4 2006.196.07:46:11.98#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.196.07:46:11.98#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.196.07:46:11.98#ibcon#ireg 11 cls_cnt 2 2006.196.07:46:11.98#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.196.07:46:12.04#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.196.07:46:12.04#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.196.07:46:12.04#ibcon#enter wrdev, iclass 7, count 2 2006.196.07:46:12.04#ibcon#first serial, iclass 7, count 2 2006.196.07:46:12.04#ibcon#enter sib2, iclass 7, count 2 2006.196.07:46:12.04#ibcon#flushed, iclass 7, count 2 2006.196.07:46:12.04#ibcon#about to write, iclass 7, count 2 2006.196.07:46:12.04#ibcon#wrote, iclass 7, count 2 2006.196.07:46:12.04#ibcon#about to read 3, iclass 7, count 2 2006.196.07:46:12.06#ibcon#read 3, iclass 7, count 2 2006.196.07:46:12.06#ibcon#about to read 4, iclass 7, count 2 2006.196.07:46:12.06#ibcon#read 4, iclass 7, count 2 2006.196.07:46:12.06#ibcon#about to read 5, iclass 7, count 2 2006.196.07:46:12.06#ibcon#read 5, iclass 7, count 2 2006.196.07:46:12.06#ibcon#about to read 6, iclass 7, count 2 2006.196.07:46:12.06#ibcon#read 6, iclass 7, count 2 2006.196.07:46:12.06#ibcon#end of sib2, iclass 7, count 2 2006.196.07:46:12.06#ibcon#*mode == 0, iclass 7, count 2 2006.196.07:46:12.06#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.196.07:46:12.06#ibcon#[27=AT05-04\r\n] 2006.196.07:46:12.06#ibcon#*before write, iclass 7, count 2 2006.196.07:46:12.06#ibcon#enter sib2, iclass 7, count 2 2006.196.07:46:12.06#ibcon#flushed, iclass 7, count 2 2006.196.07:46:12.06#ibcon#about to write, iclass 7, count 2 2006.196.07:46:12.06#ibcon#wrote, iclass 7, count 2 2006.196.07:46:12.06#ibcon#about to read 3, iclass 7, count 2 2006.196.07:46:12.09#ibcon#read 3, iclass 7, count 2 2006.196.07:46:12.09#ibcon#about to read 4, iclass 7, count 2 2006.196.07:46:12.09#ibcon#read 4, iclass 7, count 2 2006.196.07:46:12.09#ibcon#about to read 5, iclass 7, count 2 2006.196.07:46:12.09#ibcon#read 5, iclass 7, count 2 2006.196.07:46:12.09#ibcon#about to read 6, iclass 7, count 2 2006.196.07:46:12.09#ibcon#read 6, iclass 7, count 2 2006.196.07:46:12.09#ibcon#end of sib2, iclass 7, count 2 2006.196.07:46:12.09#ibcon#*after write, iclass 7, count 2 2006.196.07:46:12.09#ibcon#*before return 0, iclass 7, count 2 2006.196.07:46:12.09#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.196.07:46:12.09#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.196.07:46:12.09#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.196.07:46:12.09#ibcon#ireg 7 cls_cnt 0 2006.196.07:46:12.09#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.196.07:46:12.21#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.196.07:46:12.21#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.196.07:46:12.21#ibcon#enter wrdev, iclass 7, count 0 2006.196.07:46:12.21#ibcon#first serial, iclass 7, count 0 2006.196.07:46:12.21#ibcon#enter sib2, iclass 7, count 0 2006.196.07:46:12.21#ibcon#flushed, iclass 7, count 0 2006.196.07:46:12.21#ibcon#about to write, iclass 7, count 0 2006.196.07:46:12.21#ibcon#wrote, iclass 7, count 0 2006.196.07:46:12.21#ibcon#about to read 3, iclass 7, count 0 2006.196.07:46:12.23#ibcon#read 3, iclass 7, count 0 2006.196.07:46:12.23#ibcon#about to read 4, iclass 7, count 0 2006.196.07:46:12.23#ibcon#read 4, iclass 7, count 0 2006.196.07:46:12.23#ibcon#about to read 5, iclass 7, count 0 2006.196.07:46:12.23#ibcon#read 5, iclass 7, count 0 2006.196.07:46:12.23#ibcon#about to read 6, iclass 7, count 0 2006.196.07:46:12.23#ibcon#read 6, iclass 7, count 0 2006.196.07:46:12.23#ibcon#end of sib2, iclass 7, count 0 2006.196.07:46:12.23#ibcon#*mode == 0, iclass 7, count 0 2006.196.07:46:12.23#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.196.07:46:12.23#ibcon#[27=USB\r\n] 2006.196.07:46:12.23#ibcon#*before write, iclass 7, count 0 2006.196.07:46:12.23#ibcon#enter sib2, iclass 7, count 0 2006.196.07:46:12.23#ibcon#flushed, iclass 7, count 0 2006.196.07:46:12.23#ibcon#about to write, iclass 7, count 0 2006.196.07:46:12.23#ibcon#wrote, iclass 7, count 0 2006.196.07:46:12.23#ibcon#about to read 3, iclass 7, count 0 2006.196.07:46:12.26#ibcon#read 3, iclass 7, count 0 2006.196.07:46:12.26#ibcon#about to read 4, iclass 7, count 0 2006.196.07:46:12.26#ibcon#read 4, iclass 7, count 0 2006.196.07:46:12.26#ibcon#about to read 5, iclass 7, count 0 2006.196.07:46:12.26#ibcon#read 5, iclass 7, count 0 2006.196.07:46:12.26#ibcon#about to read 6, iclass 7, count 0 2006.196.07:46:12.26#ibcon#read 6, iclass 7, count 0 2006.196.07:46:12.26#ibcon#end of sib2, iclass 7, count 0 2006.196.07:46:12.26#ibcon#*after write, iclass 7, count 0 2006.196.07:46:12.26#ibcon#*before return 0, iclass 7, count 0 2006.196.07:46:12.26#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.196.07:46:12.26#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.196.07:46:12.26#ibcon#about to clear, iclass 7 cls_cnt 0 2006.196.07:46:12.26#ibcon#cleared, iclass 7 cls_cnt 0 2006.196.07:46:12.26$vc4f8/vblo=6,752.99 2006.196.07:46:12.26#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.196.07:46:12.26#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.196.07:46:12.26#ibcon#ireg 17 cls_cnt 0 2006.196.07:46:12.26#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.196.07:46:12.26#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.196.07:46:12.26#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.196.07:46:12.26#ibcon#enter wrdev, iclass 11, count 0 2006.196.07:46:12.26#ibcon#first serial, iclass 11, count 0 2006.196.07:46:12.26#ibcon#enter sib2, iclass 11, count 0 2006.196.07:46:12.26#ibcon#flushed, iclass 11, count 0 2006.196.07:46:12.26#ibcon#about to write, iclass 11, count 0 2006.196.07:46:12.26#ibcon#wrote, iclass 11, count 0 2006.196.07:46:12.26#ibcon#about to read 3, iclass 11, count 0 2006.196.07:46:12.28#ibcon#read 3, iclass 11, count 0 2006.196.07:46:12.28#ibcon#about to read 4, iclass 11, count 0 2006.196.07:46:12.28#ibcon#read 4, iclass 11, count 0 2006.196.07:46:12.28#ibcon#about to read 5, iclass 11, count 0 2006.196.07:46:12.28#ibcon#read 5, iclass 11, count 0 2006.196.07:46:12.28#ibcon#about to read 6, iclass 11, count 0 2006.196.07:46:12.28#ibcon#read 6, iclass 11, count 0 2006.196.07:46:12.28#ibcon#end of sib2, iclass 11, count 0 2006.196.07:46:12.28#ibcon#*mode == 0, iclass 11, count 0 2006.196.07:46:12.28#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.196.07:46:12.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.196.07:46:12.28#ibcon#*before write, iclass 11, count 0 2006.196.07:46:12.28#ibcon#enter sib2, iclass 11, count 0 2006.196.07:46:12.28#ibcon#flushed, iclass 11, count 0 2006.196.07:46:12.28#ibcon#about to write, iclass 11, count 0 2006.196.07:46:12.28#ibcon#wrote, iclass 11, count 0 2006.196.07:46:12.28#ibcon#about to read 3, iclass 11, count 0 2006.196.07:46:12.32#ibcon#read 3, iclass 11, count 0 2006.196.07:46:12.32#ibcon#about to read 4, iclass 11, count 0 2006.196.07:46:12.32#ibcon#read 4, iclass 11, count 0 2006.196.07:46:12.32#ibcon#about to read 5, iclass 11, count 0 2006.196.07:46:12.32#ibcon#read 5, iclass 11, count 0 2006.196.07:46:12.32#ibcon#about to read 6, iclass 11, count 0 2006.196.07:46:12.32#ibcon#read 6, iclass 11, count 0 2006.196.07:46:12.32#ibcon#end of sib2, iclass 11, count 0 2006.196.07:46:12.32#ibcon#*after write, iclass 11, count 0 2006.196.07:46:12.32#ibcon#*before return 0, iclass 11, count 0 2006.196.07:46:12.32#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.196.07:46:12.32#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.196.07:46:12.32#ibcon#about to clear, iclass 11 cls_cnt 0 2006.196.07:46:12.32#ibcon#cleared, iclass 11 cls_cnt 0 2006.196.07:46:12.32$vc4f8/vb=6,4 2006.196.07:46:12.32#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.196.07:46:12.32#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.196.07:46:12.32#ibcon#ireg 11 cls_cnt 2 2006.196.07:46:12.32#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.196.07:46:12.38#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.196.07:46:12.38#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.196.07:46:12.38#ibcon#enter wrdev, iclass 13, count 2 2006.196.07:46:12.38#ibcon#first serial, iclass 13, count 2 2006.196.07:46:12.38#ibcon#enter sib2, iclass 13, count 2 2006.196.07:46:12.38#ibcon#flushed, iclass 13, count 2 2006.196.07:46:12.38#ibcon#about to write, iclass 13, count 2 2006.196.07:46:12.38#ibcon#wrote, iclass 13, count 2 2006.196.07:46:12.38#ibcon#about to read 3, iclass 13, count 2 2006.196.07:46:12.40#ibcon#read 3, iclass 13, count 2 2006.196.07:46:12.40#ibcon#about to read 4, iclass 13, count 2 2006.196.07:46:12.40#ibcon#read 4, iclass 13, count 2 2006.196.07:46:12.40#ibcon#about to read 5, iclass 13, count 2 2006.196.07:46:12.40#ibcon#read 5, iclass 13, count 2 2006.196.07:46:12.40#ibcon#about to read 6, iclass 13, count 2 2006.196.07:46:12.40#ibcon#read 6, iclass 13, count 2 2006.196.07:46:12.40#ibcon#end of sib2, iclass 13, count 2 2006.196.07:46:12.40#ibcon#*mode == 0, iclass 13, count 2 2006.196.07:46:12.40#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.196.07:46:12.40#ibcon#[27=AT06-04\r\n] 2006.196.07:46:12.40#ibcon#*before write, iclass 13, count 2 2006.196.07:46:12.40#ibcon#enter sib2, iclass 13, count 2 2006.196.07:46:12.40#ibcon#flushed, iclass 13, count 2 2006.196.07:46:12.40#ibcon#about to write, iclass 13, count 2 2006.196.07:46:12.40#ibcon#wrote, iclass 13, count 2 2006.196.07:46:12.40#ibcon#about to read 3, iclass 13, count 2 2006.196.07:46:12.43#ibcon#read 3, iclass 13, count 2 2006.196.07:46:12.43#ibcon#about to read 4, iclass 13, count 2 2006.196.07:46:12.43#ibcon#read 4, iclass 13, count 2 2006.196.07:46:12.43#ibcon#about to read 5, iclass 13, count 2 2006.196.07:46:12.43#ibcon#read 5, iclass 13, count 2 2006.196.07:46:12.43#ibcon#about to read 6, iclass 13, count 2 2006.196.07:46:12.43#ibcon#read 6, iclass 13, count 2 2006.196.07:46:12.43#ibcon#end of sib2, iclass 13, count 2 2006.196.07:46:12.43#ibcon#*after write, iclass 13, count 2 2006.196.07:46:12.43#ibcon#*before return 0, iclass 13, count 2 2006.196.07:46:12.43#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.196.07:46:12.43#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.196.07:46:12.43#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.196.07:46:12.43#ibcon#ireg 7 cls_cnt 0 2006.196.07:46:12.43#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.196.07:46:12.55#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.196.07:46:12.55#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.196.07:46:12.55#ibcon#enter wrdev, iclass 13, count 0 2006.196.07:46:12.55#ibcon#first serial, iclass 13, count 0 2006.196.07:46:12.55#ibcon#enter sib2, iclass 13, count 0 2006.196.07:46:12.55#ibcon#flushed, iclass 13, count 0 2006.196.07:46:12.55#ibcon#about to write, iclass 13, count 0 2006.196.07:46:12.55#ibcon#wrote, iclass 13, count 0 2006.196.07:46:12.55#ibcon#about to read 3, iclass 13, count 0 2006.196.07:46:12.57#ibcon#read 3, iclass 13, count 0 2006.196.07:46:12.57#ibcon#about to read 4, iclass 13, count 0 2006.196.07:46:12.57#ibcon#read 4, iclass 13, count 0 2006.196.07:46:12.57#ibcon#about to read 5, iclass 13, count 0 2006.196.07:46:12.57#ibcon#read 5, iclass 13, count 0 2006.196.07:46:12.57#ibcon#about to read 6, iclass 13, count 0 2006.196.07:46:12.57#ibcon#read 6, iclass 13, count 0 2006.196.07:46:12.57#ibcon#end of sib2, iclass 13, count 0 2006.196.07:46:12.57#ibcon#*mode == 0, iclass 13, count 0 2006.196.07:46:12.57#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.196.07:46:12.57#ibcon#[27=USB\r\n] 2006.196.07:46:12.57#ibcon#*before write, iclass 13, count 0 2006.196.07:46:12.57#ibcon#enter sib2, iclass 13, count 0 2006.196.07:46:12.57#ibcon#flushed, iclass 13, count 0 2006.196.07:46:12.57#ibcon#about to write, iclass 13, count 0 2006.196.07:46:12.57#ibcon#wrote, iclass 13, count 0 2006.196.07:46:12.57#ibcon#about to read 3, iclass 13, count 0 2006.196.07:46:12.60#ibcon#read 3, iclass 13, count 0 2006.196.07:46:12.60#ibcon#about to read 4, iclass 13, count 0 2006.196.07:46:12.60#ibcon#read 4, iclass 13, count 0 2006.196.07:46:12.60#ibcon#about to read 5, iclass 13, count 0 2006.196.07:46:12.60#ibcon#read 5, iclass 13, count 0 2006.196.07:46:12.60#ibcon#about to read 6, iclass 13, count 0 2006.196.07:46:12.60#ibcon#read 6, iclass 13, count 0 2006.196.07:46:12.60#ibcon#end of sib2, iclass 13, count 0 2006.196.07:46:12.60#ibcon#*after write, iclass 13, count 0 2006.196.07:46:12.60#ibcon#*before return 0, iclass 13, count 0 2006.196.07:46:12.60#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.196.07:46:12.60#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.196.07:46:12.60#ibcon#about to clear, iclass 13 cls_cnt 0 2006.196.07:46:12.60#ibcon#cleared, iclass 13 cls_cnt 0 2006.196.07:46:12.60$vc4f8/vabw=wide 2006.196.07:46:12.60#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.196.07:46:12.60#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.196.07:46:12.60#ibcon#ireg 8 cls_cnt 0 2006.196.07:46:12.60#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.196.07:46:12.60#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.196.07:46:12.60#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.196.07:46:12.60#ibcon#enter wrdev, iclass 15, count 0 2006.196.07:46:12.60#ibcon#first serial, iclass 15, count 0 2006.196.07:46:12.60#ibcon#enter sib2, iclass 15, count 0 2006.196.07:46:12.60#ibcon#flushed, iclass 15, count 0 2006.196.07:46:12.60#ibcon#about to write, iclass 15, count 0 2006.196.07:46:12.60#ibcon#wrote, iclass 15, count 0 2006.196.07:46:12.60#ibcon#about to read 3, iclass 15, count 0 2006.196.07:46:12.62#ibcon#read 3, iclass 15, count 0 2006.196.07:46:12.62#ibcon#about to read 4, iclass 15, count 0 2006.196.07:46:12.62#ibcon#read 4, iclass 15, count 0 2006.196.07:46:12.62#ibcon#about to read 5, iclass 15, count 0 2006.196.07:46:12.62#ibcon#read 5, iclass 15, count 0 2006.196.07:46:12.62#ibcon#about to read 6, iclass 15, count 0 2006.196.07:46:12.62#ibcon#read 6, iclass 15, count 0 2006.196.07:46:12.62#ibcon#end of sib2, iclass 15, count 0 2006.196.07:46:12.62#ibcon#*mode == 0, iclass 15, count 0 2006.196.07:46:12.62#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.196.07:46:12.62#ibcon#[25=BW32\r\n] 2006.196.07:46:12.62#ibcon#*before write, iclass 15, count 0 2006.196.07:46:12.62#ibcon#enter sib2, iclass 15, count 0 2006.196.07:46:12.62#ibcon#flushed, iclass 15, count 0 2006.196.07:46:12.62#ibcon#about to write, iclass 15, count 0 2006.196.07:46:12.62#ibcon#wrote, iclass 15, count 0 2006.196.07:46:12.62#ibcon#about to read 3, iclass 15, count 0 2006.196.07:46:12.65#ibcon#read 3, iclass 15, count 0 2006.196.07:46:12.65#ibcon#about to read 4, iclass 15, count 0 2006.196.07:46:12.65#ibcon#read 4, iclass 15, count 0 2006.196.07:46:12.65#ibcon#about to read 5, iclass 15, count 0 2006.196.07:46:12.65#ibcon#read 5, iclass 15, count 0 2006.196.07:46:12.65#ibcon#about to read 6, iclass 15, count 0 2006.196.07:46:12.65#ibcon#read 6, iclass 15, count 0 2006.196.07:46:12.65#ibcon#end of sib2, iclass 15, count 0 2006.196.07:46:12.65#ibcon#*after write, iclass 15, count 0 2006.196.07:46:12.65#ibcon#*before return 0, iclass 15, count 0 2006.196.07:46:12.65#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.196.07:46:12.65#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.196.07:46:12.65#ibcon#about to clear, iclass 15 cls_cnt 0 2006.196.07:46:12.65#ibcon#cleared, iclass 15 cls_cnt 0 2006.196.07:46:12.65$vc4f8/vbbw=wide 2006.196.07:46:12.65#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.196.07:46:12.65#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.196.07:46:12.65#ibcon#ireg 8 cls_cnt 0 2006.196.07:46:12.65#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.196.07:46:12.72#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.196.07:46:12.72#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.196.07:46:12.72#ibcon#enter wrdev, iclass 17, count 0 2006.196.07:46:12.72#ibcon#first serial, iclass 17, count 0 2006.196.07:46:12.72#ibcon#enter sib2, iclass 17, count 0 2006.196.07:46:12.72#ibcon#flushed, iclass 17, count 0 2006.196.07:46:12.72#ibcon#about to write, iclass 17, count 0 2006.196.07:46:12.72#ibcon#wrote, iclass 17, count 0 2006.196.07:46:12.72#ibcon#about to read 3, iclass 17, count 0 2006.196.07:46:12.74#ibcon#read 3, iclass 17, count 0 2006.196.07:46:12.74#ibcon#about to read 4, iclass 17, count 0 2006.196.07:46:12.74#ibcon#read 4, iclass 17, count 0 2006.196.07:46:12.74#ibcon#about to read 5, iclass 17, count 0 2006.196.07:46:12.74#ibcon#read 5, iclass 17, count 0 2006.196.07:46:12.74#ibcon#about to read 6, iclass 17, count 0 2006.196.07:46:12.74#ibcon#read 6, iclass 17, count 0 2006.196.07:46:12.74#ibcon#end of sib2, iclass 17, count 0 2006.196.07:46:12.74#ibcon#*mode == 0, iclass 17, count 0 2006.196.07:46:12.74#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.196.07:46:12.74#ibcon#[27=BW32\r\n] 2006.196.07:46:12.74#ibcon#*before write, iclass 17, count 0 2006.196.07:46:12.74#ibcon#enter sib2, iclass 17, count 0 2006.196.07:46:12.74#ibcon#flushed, iclass 17, count 0 2006.196.07:46:12.74#ibcon#about to write, iclass 17, count 0 2006.196.07:46:12.74#ibcon#wrote, iclass 17, count 0 2006.196.07:46:12.74#ibcon#about to read 3, iclass 17, count 0 2006.196.07:46:12.77#ibcon#read 3, iclass 17, count 0 2006.196.07:46:12.77#ibcon#about to read 4, iclass 17, count 0 2006.196.07:46:12.77#ibcon#read 4, iclass 17, count 0 2006.196.07:46:12.77#ibcon#about to read 5, iclass 17, count 0 2006.196.07:46:12.77#ibcon#read 5, iclass 17, count 0 2006.196.07:46:12.77#ibcon#about to read 6, iclass 17, count 0 2006.196.07:46:12.77#ibcon#read 6, iclass 17, count 0 2006.196.07:46:12.77#ibcon#end of sib2, iclass 17, count 0 2006.196.07:46:12.77#ibcon#*after write, iclass 17, count 0 2006.196.07:46:12.77#ibcon#*before return 0, iclass 17, count 0 2006.196.07:46:12.77#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.196.07:46:12.77#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.196.07:46:12.77#ibcon#about to clear, iclass 17 cls_cnt 0 2006.196.07:46:12.77#ibcon#cleared, iclass 17 cls_cnt 0 2006.196.07:46:12.77$4f8m12a/ifd4f 2006.196.07:46:12.77$ifd4f/lo= 2006.196.07:46:12.77$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.196.07:46:12.77$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.196.07:46:12.77$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.196.07:46:12.77$ifd4f/patch= 2006.196.07:46:12.77$ifd4f/patch=lo1,a1,a2,a3,a4 2006.196.07:46:12.77$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.196.07:46:12.77$ifd4f/patch=lo3,a5,a6,a7,a8 2006.196.07:46:12.77$4f8m12a/"form=m,16.000,1:2 2006.196.07:46:12.77$4f8m12a/"tpicd 2006.196.07:46:12.77$4f8m12a/echo=off 2006.196.07:46:12.77$4f8m12a/xlog=off 2006.196.07:46:12.77:!2006.196.07:48:50 2006.196.07:46:27.14#trakl#Source acquired 2006.196.07:46:28.14#flagr#flagr/antenna,acquired 2006.196.07:48:50.00:preob 2006.196.07:48:50.14/onsource/TRACKING 2006.196.07:48:50.14:!2006.196.07:49:00 2006.196.07:49:00.00:data_valid=on 2006.196.07:49:00.00:midob 2006.196.07:49:01.13/onsource/TRACKING 2006.196.07:49:01.13/wx/29.72,1004.1,88 2006.196.07:49:01.26/cable/+6.3350E-03 2006.196.07:49:02.35/va/01,08,usb,yes,29,30 2006.196.07:49:02.35/va/02,07,usb,yes,29,30 2006.196.07:49:02.35/va/03,06,usb,yes,31,31 2006.196.07:49:02.35/va/04,07,usb,yes,30,32 2006.196.07:49:02.35/va/05,07,usb,yes,32,33 2006.196.07:49:02.35/va/06,06,usb,yes,31,31 2006.196.07:49:02.35/va/07,06,usb,yes,31,31 2006.196.07:49:02.35/va/08,07,usb,yes,30,29 2006.196.07:49:02.58/valo/01,532.99,yes,locked 2006.196.07:49:02.58/valo/02,572.99,yes,locked 2006.196.07:49:02.58/valo/03,672.99,yes,locked 2006.196.07:49:02.58/valo/04,832.99,yes,locked 2006.196.07:49:02.58/valo/05,652.99,yes,locked 2006.196.07:49:02.58/valo/06,772.99,yes,locked 2006.196.07:49:02.58/valo/07,832.99,yes,locked 2006.196.07:49:02.58/valo/08,852.99,yes,locked 2006.196.07:49:03.67/vb/01,04,usb,yes,29,27 2006.196.07:49:03.67/vb/02,04,usb,yes,30,32 2006.196.07:49:03.67/vb/03,04,usb,yes,27,30 2006.196.07:49:03.67/vb/04,04,usb,yes,28,28 2006.196.07:49:03.67/vb/05,04,usb,yes,26,30 2006.196.07:49:03.67/vb/06,04,usb,yes,27,30 2006.196.07:49:03.67/vb/07,04,usb,yes,29,29 2006.196.07:49:03.67/vb/08,04,usb,yes,27,30 2006.196.07:49:03.91/vblo/01,632.99,yes,locked 2006.196.07:49:03.91/vblo/02,640.99,yes,locked 2006.196.07:49:03.91/vblo/03,656.99,yes,locked 2006.196.07:49:03.91/vblo/04,712.99,yes,locked 2006.196.07:49:03.91/vblo/05,744.99,yes,locked 2006.196.07:49:03.91/vblo/06,752.99,yes,locked 2006.196.07:49:03.91/vblo/07,734.99,yes,locked 2006.196.07:49:03.91/vblo/08,744.99,yes,locked 2006.196.07:49:04.06/vabw/8 2006.196.07:49:04.21/vbbw/8 2006.196.07:49:04.30/xfe/off,on,15.0 2006.196.07:49:04.68/ifatt/23,28,28,28 2006.196.07:49:05.07/fmout-gps/S +3.35E-07 2006.196.07:49:05.11:!2006.196.07:50:00 2006.196.07:50:00.00:data_valid=off 2006.196.07:50:00.00:postob 2006.196.07:50:00.08/cable/+6.3352E-03 2006.196.07:50:00.08/wx/29.69,1004.0,88 2006.196.07:50:01.07/fmout-gps/S +3.34E-07 2006.196.07:50:01.07:scan_name=196-0750,k06196,60 2006.196.07:50:01.07:source=1128+385,113053.28,381518.5,2000.0,cw 2006.196.07:50:01.13#flagr#flagr/antenna,new-source 2006.196.07:50:02.13:checkk5 2006.196.07:50:02.50/chk_autoobs//k5ts1/ autoobs is running! 2006.196.07:50:02.88/chk_autoobs//k5ts2/ autoobs is running! 2006.196.07:50:03.27/chk_autoobs//k5ts3/ autoobs is running! 2006.196.07:50:03.65/chk_autoobs//k5ts4/ autoobs is running! 2006.196.07:50:04.02/chk_obsdata//k5ts1/T1960749??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.07:50:04.39/chk_obsdata//k5ts2/T1960749??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.07:50:04.75/chk_obsdata//k5ts3/T1960749??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.07:50:05.12/chk_obsdata//k5ts4/T1960749??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.07:50:05.83/k5log//k5ts1_log_newline 2006.196.07:50:06.52/k5log//k5ts2_log_newline 2006.196.07:50:07.23/k5log//k5ts3_log_newline 2006.196.07:50:07.92/k5log//k5ts4_log_newline 2006.196.07:50:07.94/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.196.07:50:07.94:4f8m12a=1 2006.196.07:50:07.95$4f8m12a/echo=on 2006.196.07:50:07.95$4f8m12a/pcalon 2006.196.07:50:07.95$pcalon/"no phase cal control is implemented here 2006.196.07:50:07.95$4f8m12a/"tpicd=stop 2006.196.07:50:07.95$4f8m12a/vc4f8 2006.196.07:50:07.95$vc4f8/valo=1,532.99 2006.196.07:50:07.95#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.196.07:50:07.95#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.196.07:50:07.95#ibcon#ireg 17 cls_cnt 0 2006.196.07:50:07.95#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.196.07:50:07.95#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.196.07:50:07.95#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.196.07:50:07.95#ibcon#enter wrdev, iclass 40, count 0 2006.196.07:50:07.95#ibcon#first serial, iclass 40, count 0 2006.196.07:50:07.95#ibcon#enter sib2, iclass 40, count 0 2006.196.07:50:07.95#ibcon#flushed, iclass 40, count 0 2006.196.07:50:07.95#ibcon#about to write, iclass 40, count 0 2006.196.07:50:07.95#ibcon#wrote, iclass 40, count 0 2006.196.07:50:07.95#ibcon#about to read 3, iclass 40, count 0 2006.196.07:50:07.99#ibcon#read 3, iclass 40, count 0 2006.196.07:50:07.99#ibcon#about to read 4, iclass 40, count 0 2006.196.07:50:07.99#ibcon#read 4, iclass 40, count 0 2006.196.07:50:07.99#ibcon#about to read 5, iclass 40, count 0 2006.196.07:50:07.99#ibcon#read 5, iclass 40, count 0 2006.196.07:50:07.99#ibcon#about to read 6, iclass 40, count 0 2006.196.07:50:07.99#ibcon#read 6, iclass 40, count 0 2006.196.07:50:07.99#ibcon#end of sib2, iclass 40, count 0 2006.196.07:50:07.99#ibcon#*mode == 0, iclass 40, count 0 2006.196.07:50:07.99#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.196.07:50:07.99#ibcon#[26=FRQ=01,532.99\r\n] 2006.196.07:50:07.99#ibcon#*before write, iclass 40, count 0 2006.196.07:50:07.99#ibcon#enter sib2, iclass 40, count 0 2006.196.07:50:07.99#ibcon#flushed, iclass 40, count 0 2006.196.07:50:07.99#ibcon#about to write, iclass 40, count 0 2006.196.07:50:07.99#ibcon#wrote, iclass 40, count 0 2006.196.07:50:07.99#ibcon#about to read 3, iclass 40, count 0 2006.196.07:50:08.04#ibcon#read 3, iclass 40, count 0 2006.196.07:50:08.04#ibcon#about to read 4, iclass 40, count 0 2006.196.07:50:08.04#ibcon#read 4, iclass 40, count 0 2006.196.07:50:08.04#ibcon#about to read 5, iclass 40, count 0 2006.196.07:50:08.04#ibcon#read 5, iclass 40, count 0 2006.196.07:50:08.04#ibcon#about to read 6, iclass 40, count 0 2006.196.07:50:08.04#ibcon#read 6, iclass 40, count 0 2006.196.07:50:08.04#ibcon#end of sib2, iclass 40, count 0 2006.196.07:50:08.04#ibcon#*after write, iclass 40, count 0 2006.196.07:50:08.04#ibcon#*before return 0, iclass 40, count 0 2006.196.07:50:08.04#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.196.07:50:08.04#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.196.07:50:08.04#ibcon#about to clear, iclass 40 cls_cnt 0 2006.196.07:50:08.04#ibcon#cleared, iclass 40 cls_cnt 0 2006.196.07:50:08.04$vc4f8/va=1,8 2006.196.07:50:08.04#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.196.07:50:08.04#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.196.07:50:08.04#ibcon#ireg 11 cls_cnt 2 2006.196.07:50:08.04#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.196.07:50:08.04#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.196.07:50:08.04#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.196.07:50:08.04#ibcon#enter wrdev, iclass 4, count 2 2006.196.07:50:08.04#ibcon#first serial, iclass 4, count 2 2006.196.07:50:08.04#ibcon#enter sib2, iclass 4, count 2 2006.196.07:50:08.04#ibcon#flushed, iclass 4, count 2 2006.196.07:50:08.04#ibcon#about to write, iclass 4, count 2 2006.196.07:50:08.04#ibcon#wrote, iclass 4, count 2 2006.196.07:50:08.04#ibcon#about to read 3, iclass 4, count 2 2006.196.07:50:08.06#ibcon#read 3, iclass 4, count 2 2006.196.07:50:08.06#ibcon#about to read 4, iclass 4, count 2 2006.196.07:50:08.06#ibcon#read 4, iclass 4, count 2 2006.196.07:50:08.06#ibcon#about to read 5, iclass 4, count 2 2006.196.07:50:08.06#ibcon#read 5, iclass 4, count 2 2006.196.07:50:08.06#ibcon#about to read 6, iclass 4, count 2 2006.196.07:50:08.06#ibcon#read 6, iclass 4, count 2 2006.196.07:50:08.06#ibcon#end of sib2, iclass 4, count 2 2006.196.07:50:08.06#ibcon#*mode == 0, iclass 4, count 2 2006.196.07:50:08.06#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.196.07:50:08.06#ibcon#[25=AT01-08\r\n] 2006.196.07:50:08.06#ibcon#*before write, iclass 4, count 2 2006.196.07:50:08.06#ibcon#enter sib2, iclass 4, count 2 2006.196.07:50:08.06#ibcon#flushed, iclass 4, count 2 2006.196.07:50:08.06#ibcon#about to write, iclass 4, count 2 2006.196.07:50:08.06#ibcon#wrote, iclass 4, count 2 2006.196.07:50:08.06#ibcon#about to read 3, iclass 4, count 2 2006.196.07:50:08.09#ibcon#read 3, iclass 4, count 2 2006.196.07:50:08.09#ibcon#about to read 4, iclass 4, count 2 2006.196.07:50:08.09#ibcon#read 4, iclass 4, count 2 2006.196.07:50:08.09#ibcon#about to read 5, iclass 4, count 2 2006.196.07:50:08.09#ibcon#read 5, iclass 4, count 2 2006.196.07:50:08.09#ibcon#about to read 6, iclass 4, count 2 2006.196.07:50:08.09#ibcon#read 6, iclass 4, count 2 2006.196.07:50:08.09#ibcon#end of sib2, iclass 4, count 2 2006.196.07:50:08.09#ibcon#*after write, iclass 4, count 2 2006.196.07:50:08.09#ibcon#*before return 0, iclass 4, count 2 2006.196.07:50:08.09#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.196.07:50:08.09#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.196.07:50:08.09#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.196.07:50:08.09#ibcon#ireg 7 cls_cnt 0 2006.196.07:50:08.09#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.196.07:50:08.21#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.196.07:50:08.21#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.196.07:50:08.21#ibcon#enter wrdev, iclass 4, count 0 2006.196.07:50:08.21#ibcon#first serial, iclass 4, count 0 2006.196.07:50:08.21#ibcon#enter sib2, iclass 4, count 0 2006.196.07:50:08.21#ibcon#flushed, iclass 4, count 0 2006.196.07:50:08.21#ibcon#about to write, iclass 4, count 0 2006.196.07:50:08.21#ibcon#wrote, iclass 4, count 0 2006.196.07:50:08.21#ibcon#about to read 3, iclass 4, count 0 2006.196.07:50:08.23#ibcon#read 3, iclass 4, count 0 2006.196.07:50:08.23#ibcon#about to read 4, iclass 4, count 0 2006.196.07:50:08.23#ibcon#read 4, iclass 4, count 0 2006.196.07:50:08.23#ibcon#about to read 5, iclass 4, count 0 2006.196.07:50:08.23#ibcon#read 5, iclass 4, count 0 2006.196.07:50:08.23#ibcon#about to read 6, iclass 4, count 0 2006.196.07:50:08.23#ibcon#read 6, iclass 4, count 0 2006.196.07:50:08.23#ibcon#end of sib2, iclass 4, count 0 2006.196.07:50:08.23#ibcon#*mode == 0, iclass 4, count 0 2006.196.07:50:08.23#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.196.07:50:08.23#ibcon#[25=USB\r\n] 2006.196.07:50:08.23#ibcon#*before write, iclass 4, count 0 2006.196.07:50:08.23#ibcon#enter sib2, iclass 4, count 0 2006.196.07:50:08.23#ibcon#flushed, iclass 4, count 0 2006.196.07:50:08.23#ibcon#about to write, iclass 4, count 0 2006.196.07:50:08.23#ibcon#wrote, iclass 4, count 0 2006.196.07:50:08.23#ibcon#about to read 3, iclass 4, count 0 2006.196.07:50:08.26#ibcon#read 3, iclass 4, count 0 2006.196.07:50:08.26#ibcon#about to read 4, iclass 4, count 0 2006.196.07:50:08.26#ibcon#read 4, iclass 4, count 0 2006.196.07:50:08.26#ibcon#about to read 5, iclass 4, count 0 2006.196.07:50:08.26#ibcon#read 5, iclass 4, count 0 2006.196.07:50:08.26#ibcon#about to read 6, iclass 4, count 0 2006.196.07:50:08.26#ibcon#read 6, iclass 4, count 0 2006.196.07:50:08.26#ibcon#end of sib2, iclass 4, count 0 2006.196.07:50:08.26#ibcon#*after write, iclass 4, count 0 2006.196.07:50:08.26#ibcon#*before return 0, iclass 4, count 0 2006.196.07:50:08.26#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.196.07:50:08.26#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.196.07:50:08.26#ibcon#about to clear, iclass 4 cls_cnt 0 2006.196.07:50:08.26#ibcon#cleared, iclass 4 cls_cnt 0 2006.196.07:50:08.26$vc4f8/valo=2,572.99 2006.196.07:50:08.26#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.196.07:50:08.26#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.196.07:50:08.26#ibcon#ireg 17 cls_cnt 0 2006.196.07:50:08.26#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.196.07:50:08.26#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.196.07:50:08.26#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.196.07:50:08.26#ibcon#enter wrdev, iclass 6, count 0 2006.196.07:50:08.26#ibcon#first serial, iclass 6, count 0 2006.196.07:50:08.26#ibcon#enter sib2, iclass 6, count 0 2006.196.07:50:08.26#ibcon#flushed, iclass 6, count 0 2006.196.07:50:08.26#ibcon#about to write, iclass 6, count 0 2006.196.07:50:08.26#ibcon#wrote, iclass 6, count 0 2006.196.07:50:08.26#ibcon#about to read 3, iclass 6, count 0 2006.196.07:50:08.28#ibcon#read 3, iclass 6, count 0 2006.196.07:50:08.28#ibcon#about to read 4, iclass 6, count 0 2006.196.07:50:08.28#ibcon#read 4, iclass 6, count 0 2006.196.07:50:08.28#ibcon#about to read 5, iclass 6, count 0 2006.196.07:50:08.28#ibcon#read 5, iclass 6, count 0 2006.196.07:50:08.28#ibcon#about to read 6, iclass 6, count 0 2006.196.07:50:08.28#ibcon#read 6, iclass 6, count 0 2006.196.07:50:08.28#ibcon#end of sib2, iclass 6, count 0 2006.196.07:50:08.28#ibcon#*mode == 0, iclass 6, count 0 2006.196.07:50:08.28#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.196.07:50:08.28#ibcon#[26=FRQ=02,572.99\r\n] 2006.196.07:50:08.28#ibcon#*before write, iclass 6, count 0 2006.196.07:50:08.28#ibcon#enter sib2, iclass 6, count 0 2006.196.07:50:08.28#ibcon#flushed, iclass 6, count 0 2006.196.07:50:08.28#ibcon#about to write, iclass 6, count 0 2006.196.07:50:08.28#ibcon#wrote, iclass 6, count 0 2006.196.07:50:08.28#ibcon#about to read 3, iclass 6, count 0 2006.196.07:50:08.33#ibcon#read 3, iclass 6, count 0 2006.196.07:50:08.33#ibcon#about to read 4, iclass 6, count 0 2006.196.07:50:08.33#ibcon#read 4, iclass 6, count 0 2006.196.07:50:08.33#ibcon#about to read 5, iclass 6, count 0 2006.196.07:50:08.33#ibcon#read 5, iclass 6, count 0 2006.196.07:50:08.33#ibcon#about to read 6, iclass 6, count 0 2006.196.07:50:08.33#ibcon#read 6, iclass 6, count 0 2006.196.07:50:08.33#ibcon#end of sib2, iclass 6, count 0 2006.196.07:50:08.33#ibcon#*after write, iclass 6, count 0 2006.196.07:50:08.33#ibcon#*before return 0, iclass 6, count 0 2006.196.07:50:08.33#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.196.07:50:08.33#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.196.07:50:08.33#ibcon#about to clear, iclass 6 cls_cnt 0 2006.196.07:50:08.33#ibcon#cleared, iclass 6 cls_cnt 0 2006.196.07:50:08.33$vc4f8/va=2,7 2006.196.07:50:08.33#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.196.07:50:08.33#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.196.07:50:08.33#ibcon#ireg 11 cls_cnt 2 2006.196.07:50:08.33#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.196.07:50:08.38#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.196.07:50:08.38#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.196.07:50:08.38#ibcon#enter wrdev, iclass 10, count 2 2006.196.07:50:08.38#ibcon#first serial, iclass 10, count 2 2006.196.07:50:08.38#ibcon#enter sib2, iclass 10, count 2 2006.196.07:50:08.38#ibcon#flushed, iclass 10, count 2 2006.196.07:50:08.38#ibcon#about to write, iclass 10, count 2 2006.196.07:50:08.38#ibcon#wrote, iclass 10, count 2 2006.196.07:50:08.38#ibcon#about to read 3, iclass 10, count 2 2006.196.07:50:08.40#ibcon#read 3, iclass 10, count 2 2006.196.07:50:08.40#ibcon#about to read 4, iclass 10, count 2 2006.196.07:50:08.40#ibcon#read 4, iclass 10, count 2 2006.196.07:50:08.40#ibcon#about to read 5, iclass 10, count 2 2006.196.07:50:08.40#ibcon#read 5, iclass 10, count 2 2006.196.07:50:08.40#ibcon#about to read 6, iclass 10, count 2 2006.196.07:50:08.40#ibcon#read 6, iclass 10, count 2 2006.196.07:50:08.40#ibcon#end of sib2, iclass 10, count 2 2006.196.07:50:08.40#ibcon#*mode == 0, iclass 10, count 2 2006.196.07:50:08.40#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.196.07:50:08.40#ibcon#[25=AT02-07\r\n] 2006.196.07:50:08.40#ibcon#*before write, iclass 10, count 2 2006.196.07:50:08.40#ibcon#enter sib2, iclass 10, count 2 2006.196.07:50:08.40#ibcon#flushed, iclass 10, count 2 2006.196.07:50:08.40#ibcon#about to write, iclass 10, count 2 2006.196.07:50:08.40#ibcon#wrote, iclass 10, count 2 2006.196.07:50:08.40#ibcon#about to read 3, iclass 10, count 2 2006.196.07:50:08.43#ibcon#read 3, iclass 10, count 2 2006.196.07:50:08.43#ibcon#about to read 4, iclass 10, count 2 2006.196.07:50:08.43#ibcon#read 4, iclass 10, count 2 2006.196.07:50:08.43#ibcon#about to read 5, iclass 10, count 2 2006.196.07:50:08.43#ibcon#read 5, iclass 10, count 2 2006.196.07:50:08.43#ibcon#about to read 6, iclass 10, count 2 2006.196.07:50:08.43#ibcon#read 6, iclass 10, count 2 2006.196.07:50:08.43#ibcon#end of sib2, iclass 10, count 2 2006.196.07:50:08.43#ibcon#*after write, iclass 10, count 2 2006.196.07:50:08.43#ibcon#*before return 0, iclass 10, count 2 2006.196.07:50:08.43#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.196.07:50:08.43#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.196.07:50:08.43#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.196.07:50:08.43#ibcon#ireg 7 cls_cnt 0 2006.196.07:50:08.43#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.196.07:50:08.55#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.196.07:50:08.55#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.196.07:50:08.55#ibcon#enter wrdev, iclass 10, count 0 2006.196.07:50:08.55#ibcon#first serial, iclass 10, count 0 2006.196.07:50:08.55#ibcon#enter sib2, iclass 10, count 0 2006.196.07:50:08.55#ibcon#flushed, iclass 10, count 0 2006.196.07:50:08.55#ibcon#about to write, iclass 10, count 0 2006.196.07:50:08.55#ibcon#wrote, iclass 10, count 0 2006.196.07:50:08.55#ibcon#about to read 3, iclass 10, count 0 2006.196.07:50:08.57#ibcon#read 3, iclass 10, count 0 2006.196.07:50:08.57#ibcon#about to read 4, iclass 10, count 0 2006.196.07:50:08.57#ibcon#read 4, iclass 10, count 0 2006.196.07:50:08.57#ibcon#about to read 5, iclass 10, count 0 2006.196.07:50:08.57#ibcon#read 5, iclass 10, count 0 2006.196.07:50:08.57#ibcon#about to read 6, iclass 10, count 0 2006.196.07:50:08.57#ibcon#read 6, iclass 10, count 0 2006.196.07:50:08.57#ibcon#end of sib2, iclass 10, count 0 2006.196.07:50:08.57#ibcon#*mode == 0, iclass 10, count 0 2006.196.07:50:08.57#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.196.07:50:08.57#ibcon#[25=USB\r\n] 2006.196.07:50:08.57#ibcon#*before write, iclass 10, count 0 2006.196.07:50:08.57#ibcon#enter sib2, iclass 10, count 0 2006.196.07:50:08.57#ibcon#flushed, iclass 10, count 0 2006.196.07:50:08.57#ibcon#about to write, iclass 10, count 0 2006.196.07:50:08.57#ibcon#wrote, iclass 10, count 0 2006.196.07:50:08.57#ibcon#about to read 3, iclass 10, count 0 2006.196.07:50:08.60#ibcon#read 3, iclass 10, count 0 2006.196.07:50:08.60#ibcon#about to read 4, iclass 10, count 0 2006.196.07:50:08.60#ibcon#read 4, iclass 10, count 0 2006.196.07:50:08.60#ibcon#about to read 5, iclass 10, count 0 2006.196.07:50:08.60#ibcon#read 5, iclass 10, count 0 2006.196.07:50:08.60#ibcon#about to read 6, iclass 10, count 0 2006.196.07:50:08.60#ibcon#read 6, iclass 10, count 0 2006.196.07:50:08.60#ibcon#end of sib2, iclass 10, count 0 2006.196.07:50:08.60#ibcon#*after write, iclass 10, count 0 2006.196.07:50:08.60#ibcon#*before return 0, iclass 10, count 0 2006.196.07:50:08.60#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.196.07:50:08.60#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.196.07:50:08.60#ibcon#about to clear, iclass 10 cls_cnt 0 2006.196.07:50:08.60#ibcon#cleared, iclass 10 cls_cnt 0 2006.196.07:50:08.60$vc4f8/valo=3,672.99 2006.196.07:50:08.60#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.196.07:50:08.60#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.196.07:50:08.60#ibcon#ireg 17 cls_cnt 0 2006.196.07:50:08.60#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.196.07:50:08.60#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.196.07:50:08.60#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.196.07:50:08.60#ibcon#enter wrdev, iclass 12, count 0 2006.196.07:50:08.60#ibcon#first serial, iclass 12, count 0 2006.196.07:50:08.60#ibcon#enter sib2, iclass 12, count 0 2006.196.07:50:08.60#ibcon#flushed, iclass 12, count 0 2006.196.07:50:08.60#ibcon#about to write, iclass 12, count 0 2006.196.07:50:08.60#ibcon#wrote, iclass 12, count 0 2006.196.07:50:08.60#ibcon#about to read 3, iclass 12, count 0 2006.196.07:50:08.62#ibcon#read 3, iclass 12, count 0 2006.196.07:50:08.62#ibcon#about to read 4, iclass 12, count 0 2006.196.07:50:08.62#ibcon#read 4, iclass 12, count 0 2006.196.07:50:08.62#ibcon#about to read 5, iclass 12, count 0 2006.196.07:50:08.62#ibcon#read 5, iclass 12, count 0 2006.196.07:50:08.62#ibcon#about to read 6, iclass 12, count 0 2006.196.07:50:08.62#ibcon#read 6, iclass 12, count 0 2006.196.07:50:08.62#ibcon#end of sib2, iclass 12, count 0 2006.196.07:50:08.62#ibcon#*mode == 0, iclass 12, count 0 2006.196.07:50:08.62#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.196.07:50:08.62#ibcon#[26=FRQ=03,672.99\r\n] 2006.196.07:50:08.62#ibcon#*before write, iclass 12, count 0 2006.196.07:50:08.62#ibcon#enter sib2, iclass 12, count 0 2006.196.07:50:08.62#ibcon#flushed, iclass 12, count 0 2006.196.07:50:08.62#ibcon#about to write, iclass 12, count 0 2006.196.07:50:08.62#ibcon#wrote, iclass 12, count 0 2006.196.07:50:08.62#ibcon#about to read 3, iclass 12, count 0 2006.196.07:50:08.67#ibcon#read 3, iclass 12, count 0 2006.196.07:50:08.67#ibcon#about to read 4, iclass 12, count 0 2006.196.07:50:08.67#ibcon#read 4, iclass 12, count 0 2006.196.07:50:08.67#ibcon#about to read 5, iclass 12, count 0 2006.196.07:50:08.67#ibcon#read 5, iclass 12, count 0 2006.196.07:50:08.67#ibcon#about to read 6, iclass 12, count 0 2006.196.07:50:08.67#ibcon#read 6, iclass 12, count 0 2006.196.07:50:08.67#ibcon#end of sib2, iclass 12, count 0 2006.196.07:50:08.67#ibcon#*after write, iclass 12, count 0 2006.196.07:50:08.67#ibcon#*before return 0, iclass 12, count 0 2006.196.07:50:08.67#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.196.07:50:08.67#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.196.07:50:08.67#ibcon#about to clear, iclass 12 cls_cnt 0 2006.196.07:50:08.67#ibcon#cleared, iclass 12 cls_cnt 0 2006.196.07:50:08.67$vc4f8/va=3,6 2006.196.07:50:08.67#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.196.07:50:08.67#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.196.07:50:08.67#ibcon#ireg 11 cls_cnt 2 2006.196.07:50:08.67#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.196.07:50:08.72#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.196.07:50:08.72#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.196.07:50:08.72#ibcon#enter wrdev, iclass 14, count 2 2006.196.07:50:08.72#ibcon#first serial, iclass 14, count 2 2006.196.07:50:08.72#ibcon#enter sib2, iclass 14, count 2 2006.196.07:50:08.72#ibcon#flushed, iclass 14, count 2 2006.196.07:50:08.72#ibcon#about to write, iclass 14, count 2 2006.196.07:50:08.72#ibcon#wrote, iclass 14, count 2 2006.196.07:50:08.72#ibcon#about to read 3, iclass 14, count 2 2006.196.07:50:08.74#ibcon#read 3, iclass 14, count 2 2006.196.07:50:08.74#ibcon#about to read 4, iclass 14, count 2 2006.196.07:50:08.74#ibcon#read 4, iclass 14, count 2 2006.196.07:50:08.74#ibcon#about to read 5, iclass 14, count 2 2006.196.07:50:08.74#ibcon#read 5, iclass 14, count 2 2006.196.07:50:08.74#ibcon#about to read 6, iclass 14, count 2 2006.196.07:50:08.74#ibcon#read 6, iclass 14, count 2 2006.196.07:50:08.74#ibcon#end of sib2, iclass 14, count 2 2006.196.07:50:08.74#ibcon#*mode == 0, iclass 14, count 2 2006.196.07:50:08.74#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.196.07:50:08.74#ibcon#[25=AT03-06\r\n] 2006.196.07:50:08.74#ibcon#*before write, iclass 14, count 2 2006.196.07:50:08.74#ibcon#enter sib2, iclass 14, count 2 2006.196.07:50:08.74#ibcon#flushed, iclass 14, count 2 2006.196.07:50:08.74#ibcon#about to write, iclass 14, count 2 2006.196.07:50:08.74#ibcon#wrote, iclass 14, count 2 2006.196.07:50:08.74#ibcon#about to read 3, iclass 14, count 2 2006.196.07:50:08.77#ibcon#read 3, iclass 14, count 2 2006.196.07:50:08.77#ibcon#about to read 4, iclass 14, count 2 2006.196.07:50:08.77#ibcon#read 4, iclass 14, count 2 2006.196.07:50:08.77#ibcon#about to read 5, iclass 14, count 2 2006.196.07:50:08.77#ibcon#read 5, iclass 14, count 2 2006.196.07:50:08.77#ibcon#about to read 6, iclass 14, count 2 2006.196.07:50:08.77#ibcon#read 6, iclass 14, count 2 2006.196.07:50:08.77#ibcon#end of sib2, iclass 14, count 2 2006.196.07:50:08.77#ibcon#*after write, iclass 14, count 2 2006.196.07:50:08.77#ibcon#*before return 0, iclass 14, count 2 2006.196.07:50:08.77#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.196.07:50:08.77#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.196.07:50:08.77#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.196.07:50:08.77#ibcon#ireg 7 cls_cnt 0 2006.196.07:50:08.77#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.196.07:50:08.89#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.196.07:50:08.89#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.196.07:50:08.89#ibcon#enter wrdev, iclass 14, count 0 2006.196.07:50:08.89#ibcon#first serial, iclass 14, count 0 2006.196.07:50:08.89#ibcon#enter sib2, iclass 14, count 0 2006.196.07:50:08.89#ibcon#flushed, iclass 14, count 0 2006.196.07:50:08.89#ibcon#about to write, iclass 14, count 0 2006.196.07:50:08.89#ibcon#wrote, iclass 14, count 0 2006.196.07:50:08.89#ibcon#about to read 3, iclass 14, count 0 2006.196.07:50:08.91#ibcon#read 3, iclass 14, count 0 2006.196.07:50:08.91#ibcon#about to read 4, iclass 14, count 0 2006.196.07:50:08.91#ibcon#read 4, iclass 14, count 0 2006.196.07:50:08.91#ibcon#about to read 5, iclass 14, count 0 2006.196.07:50:08.91#ibcon#read 5, iclass 14, count 0 2006.196.07:50:08.91#ibcon#about to read 6, iclass 14, count 0 2006.196.07:50:08.91#ibcon#read 6, iclass 14, count 0 2006.196.07:50:08.91#ibcon#end of sib2, iclass 14, count 0 2006.196.07:50:08.91#ibcon#*mode == 0, iclass 14, count 0 2006.196.07:50:08.91#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.196.07:50:08.91#ibcon#[25=USB\r\n] 2006.196.07:50:08.91#ibcon#*before write, iclass 14, count 0 2006.196.07:50:08.91#ibcon#enter sib2, iclass 14, count 0 2006.196.07:50:08.91#ibcon#flushed, iclass 14, count 0 2006.196.07:50:08.91#ibcon#about to write, iclass 14, count 0 2006.196.07:50:08.91#ibcon#wrote, iclass 14, count 0 2006.196.07:50:08.91#ibcon#about to read 3, iclass 14, count 0 2006.196.07:50:08.94#ibcon#read 3, iclass 14, count 0 2006.196.07:50:08.94#ibcon#about to read 4, iclass 14, count 0 2006.196.07:50:08.94#ibcon#read 4, iclass 14, count 0 2006.196.07:50:08.94#ibcon#about to read 5, iclass 14, count 0 2006.196.07:50:08.94#ibcon#read 5, iclass 14, count 0 2006.196.07:50:08.94#ibcon#about to read 6, iclass 14, count 0 2006.196.07:50:08.94#ibcon#read 6, iclass 14, count 0 2006.196.07:50:08.94#ibcon#end of sib2, iclass 14, count 0 2006.196.07:50:08.94#ibcon#*after write, iclass 14, count 0 2006.196.07:50:08.94#ibcon#*before return 0, iclass 14, count 0 2006.196.07:50:08.94#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.196.07:50:08.94#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.196.07:50:08.94#ibcon#about to clear, iclass 14 cls_cnt 0 2006.196.07:50:08.94#ibcon#cleared, iclass 14 cls_cnt 0 2006.196.07:50:08.94$vc4f8/valo=4,832.99 2006.196.07:50:08.94#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.196.07:50:08.94#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.196.07:50:08.94#ibcon#ireg 17 cls_cnt 0 2006.196.07:50:08.94#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.196.07:50:08.94#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.196.07:50:08.94#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.196.07:50:08.94#ibcon#enter wrdev, iclass 16, count 0 2006.196.07:50:08.94#ibcon#first serial, iclass 16, count 0 2006.196.07:50:08.94#ibcon#enter sib2, iclass 16, count 0 2006.196.07:50:08.94#ibcon#flushed, iclass 16, count 0 2006.196.07:50:08.94#ibcon#about to write, iclass 16, count 0 2006.196.07:50:08.94#ibcon#wrote, iclass 16, count 0 2006.196.07:50:08.94#ibcon#about to read 3, iclass 16, count 0 2006.196.07:50:08.96#ibcon#read 3, iclass 16, count 0 2006.196.07:50:08.96#ibcon#about to read 4, iclass 16, count 0 2006.196.07:50:08.96#ibcon#read 4, iclass 16, count 0 2006.196.07:50:08.96#ibcon#about to read 5, iclass 16, count 0 2006.196.07:50:08.96#ibcon#read 5, iclass 16, count 0 2006.196.07:50:08.96#ibcon#about to read 6, iclass 16, count 0 2006.196.07:50:08.96#ibcon#read 6, iclass 16, count 0 2006.196.07:50:08.96#ibcon#end of sib2, iclass 16, count 0 2006.196.07:50:08.96#ibcon#*mode == 0, iclass 16, count 0 2006.196.07:50:08.96#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.196.07:50:08.96#ibcon#[26=FRQ=04,832.99\r\n] 2006.196.07:50:08.96#ibcon#*before write, iclass 16, count 0 2006.196.07:50:08.96#ibcon#enter sib2, iclass 16, count 0 2006.196.07:50:08.96#ibcon#flushed, iclass 16, count 0 2006.196.07:50:08.96#ibcon#about to write, iclass 16, count 0 2006.196.07:50:08.96#ibcon#wrote, iclass 16, count 0 2006.196.07:50:08.96#ibcon#about to read 3, iclass 16, count 0 2006.196.07:50:09.00#ibcon#read 3, iclass 16, count 0 2006.196.07:50:09.00#ibcon#about to read 4, iclass 16, count 0 2006.196.07:50:09.00#ibcon#read 4, iclass 16, count 0 2006.196.07:50:09.00#ibcon#about to read 5, iclass 16, count 0 2006.196.07:50:09.00#ibcon#read 5, iclass 16, count 0 2006.196.07:50:09.00#ibcon#about to read 6, iclass 16, count 0 2006.196.07:50:09.00#ibcon#read 6, iclass 16, count 0 2006.196.07:50:09.00#ibcon#end of sib2, iclass 16, count 0 2006.196.07:50:09.00#ibcon#*after write, iclass 16, count 0 2006.196.07:50:09.00#ibcon#*before return 0, iclass 16, count 0 2006.196.07:50:09.00#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.196.07:50:09.00#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.196.07:50:09.00#ibcon#about to clear, iclass 16 cls_cnt 0 2006.196.07:50:09.00#ibcon#cleared, iclass 16 cls_cnt 0 2006.196.07:50:09.00$vc4f8/va=4,7 2006.196.07:50:09.00#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.196.07:50:09.00#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.196.07:50:09.00#ibcon#ireg 11 cls_cnt 2 2006.196.07:50:09.00#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.196.07:50:09.06#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.196.07:50:09.06#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.196.07:50:09.06#ibcon#enter wrdev, iclass 18, count 2 2006.196.07:50:09.06#ibcon#first serial, iclass 18, count 2 2006.196.07:50:09.06#ibcon#enter sib2, iclass 18, count 2 2006.196.07:50:09.06#ibcon#flushed, iclass 18, count 2 2006.196.07:50:09.06#ibcon#about to write, iclass 18, count 2 2006.196.07:50:09.06#ibcon#wrote, iclass 18, count 2 2006.196.07:50:09.06#ibcon#about to read 3, iclass 18, count 2 2006.196.07:50:09.08#ibcon#read 3, iclass 18, count 2 2006.196.07:50:09.08#ibcon#about to read 4, iclass 18, count 2 2006.196.07:50:09.08#ibcon#read 4, iclass 18, count 2 2006.196.07:50:09.08#ibcon#about to read 5, iclass 18, count 2 2006.196.07:50:09.08#ibcon#read 5, iclass 18, count 2 2006.196.07:50:09.08#ibcon#about to read 6, iclass 18, count 2 2006.196.07:50:09.08#ibcon#read 6, iclass 18, count 2 2006.196.07:50:09.08#ibcon#end of sib2, iclass 18, count 2 2006.196.07:50:09.08#ibcon#*mode == 0, iclass 18, count 2 2006.196.07:50:09.08#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.196.07:50:09.08#ibcon#[25=AT04-07\r\n] 2006.196.07:50:09.08#ibcon#*before write, iclass 18, count 2 2006.196.07:50:09.08#ibcon#enter sib2, iclass 18, count 2 2006.196.07:50:09.08#ibcon#flushed, iclass 18, count 2 2006.196.07:50:09.08#ibcon#about to write, iclass 18, count 2 2006.196.07:50:09.08#ibcon#wrote, iclass 18, count 2 2006.196.07:50:09.08#ibcon#about to read 3, iclass 18, count 2 2006.196.07:50:09.11#ibcon#read 3, iclass 18, count 2 2006.196.07:50:09.11#ibcon#about to read 4, iclass 18, count 2 2006.196.07:50:09.11#ibcon#read 4, iclass 18, count 2 2006.196.07:50:09.11#ibcon#about to read 5, iclass 18, count 2 2006.196.07:50:09.11#ibcon#read 5, iclass 18, count 2 2006.196.07:50:09.11#ibcon#about to read 6, iclass 18, count 2 2006.196.07:50:09.11#ibcon#read 6, iclass 18, count 2 2006.196.07:50:09.11#ibcon#end of sib2, iclass 18, count 2 2006.196.07:50:09.11#ibcon#*after write, iclass 18, count 2 2006.196.07:50:09.11#ibcon#*before return 0, iclass 18, count 2 2006.196.07:50:09.11#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.196.07:50:09.11#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.196.07:50:09.11#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.196.07:50:09.11#ibcon#ireg 7 cls_cnt 0 2006.196.07:50:09.11#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.196.07:50:09.23#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.196.07:50:09.23#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.196.07:50:09.23#ibcon#enter wrdev, iclass 18, count 0 2006.196.07:50:09.23#ibcon#first serial, iclass 18, count 0 2006.196.07:50:09.23#ibcon#enter sib2, iclass 18, count 0 2006.196.07:50:09.23#ibcon#flushed, iclass 18, count 0 2006.196.07:50:09.23#ibcon#about to write, iclass 18, count 0 2006.196.07:50:09.23#ibcon#wrote, iclass 18, count 0 2006.196.07:50:09.23#ibcon#about to read 3, iclass 18, count 0 2006.196.07:50:09.25#ibcon#read 3, iclass 18, count 0 2006.196.07:50:09.25#ibcon#about to read 4, iclass 18, count 0 2006.196.07:50:09.25#ibcon#read 4, iclass 18, count 0 2006.196.07:50:09.25#ibcon#about to read 5, iclass 18, count 0 2006.196.07:50:09.25#ibcon#read 5, iclass 18, count 0 2006.196.07:50:09.25#ibcon#about to read 6, iclass 18, count 0 2006.196.07:50:09.25#ibcon#read 6, iclass 18, count 0 2006.196.07:50:09.25#ibcon#end of sib2, iclass 18, count 0 2006.196.07:50:09.25#ibcon#*mode == 0, iclass 18, count 0 2006.196.07:50:09.25#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.196.07:50:09.25#ibcon#[25=USB\r\n] 2006.196.07:50:09.25#ibcon#*before write, iclass 18, count 0 2006.196.07:50:09.25#ibcon#enter sib2, iclass 18, count 0 2006.196.07:50:09.25#ibcon#flushed, iclass 18, count 0 2006.196.07:50:09.25#ibcon#about to write, iclass 18, count 0 2006.196.07:50:09.25#ibcon#wrote, iclass 18, count 0 2006.196.07:50:09.25#ibcon#about to read 3, iclass 18, count 0 2006.196.07:50:09.28#ibcon#read 3, iclass 18, count 0 2006.196.07:50:09.28#ibcon#about to read 4, iclass 18, count 0 2006.196.07:50:09.28#ibcon#read 4, iclass 18, count 0 2006.196.07:50:09.28#ibcon#about to read 5, iclass 18, count 0 2006.196.07:50:09.28#ibcon#read 5, iclass 18, count 0 2006.196.07:50:09.28#ibcon#about to read 6, iclass 18, count 0 2006.196.07:50:09.28#ibcon#read 6, iclass 18, count 0 2006.196.07:50:09.28#ibcon#end of sib2, iclass 18, count 0 2006.196.07:50:09.28#ibcon#*after write, iclass 18, count 0 2006.196.07:50:09.28#ibcon#*before return 0, iclass 18, count 0 2006.196.07:50:09.28#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.196.07:50:09.28#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.196.07:50:09.28#ibcon#about to clear, iclass 18 cls_cnt 0 2006.196.07:50:09.28#ibcon#cleared, iclass 18 cls_cnt 0 2006.196.07:50:09.28$vc4f8/valo=5,652.99 2006.196.07:50:09.28#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.196.07:50:09.28#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.196.07:50:09.28#ibcon#ireg 17 cls_cnt 0 2006.196.07:50:09.28#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.196.07:50:09.28#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.196.07:50:09.28#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.196.07:50:09.28#ibcon#enter wrdev, iclass 20, count 0 2006.196.07:50:09.28#ibcon#first serial, iclass 20, count 0 2006.196.07:50:09.28#ibcon#enter sib2, iclass 20, count 0 2006.196.07:50:09.28#ibcon#flushed, iclass 20, count 0 2006.196.07:50:09.28#ibcon#about to write, iclass 20, count 0 2006.196.07:50:09.28#ibcon#wrote, iclass 20, count 0 2006.196.07:50:09.28#ibcon#about to read 3, iclass 20, count 0 2006.196.07:50:09.30#ibcon#read 3, iclass 20, count 0 2006.196.07:50:09.30#ibcon#about to read 4, iclass 20, count 0 2006.196.07:50:09.30#ibcon#read 4, iclass 20, count 0 2006.196.07:50:09.30#ibcon#about to read 5, iclass 20, count 0 2006.196.07:50:09.30#ibcon#read 5, iclass 20, count 0 2006.196.07:50:09.30#ibcon#about to read 6, iclass 20, count 0 2006.196.07:50:09.30#ibcon#read 6, iclass 20, count 0 2006.196.07:50:09.30#ibcon#end of sib2, iclass 20, count 0 2006.196.07:50:09.30#ibcon#*mode == 0, iclass 20, count 0 2006.196.07:50:09.30#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.196.07:50:09.30#ibcon#[26=FRQ=05,652.99\r\n] 2006.196.07:50:09.30#ibcon#*before write, iclass 20, count 0 2006.196.07:50:09.30#ibcon#enter sib2, iclass 20, count 0 2006.196.07:50:09.30#ibcon#flushed, iclass 20, count 0 2006.196.07:50:09.30#ibcon#about to write, iclass 20, count 0 2006.196.07:50:09.30#ibcon#wrote, iclass 20, count 0 2006.196.07:50:09.30#ibcon#about to read 3, iclass 20, count 0 2006.196.07:50:09.34#ibcon#read 3, iclass 20, count 0 2006.196.07:50:09.34#ibcon#about to read 4, iclass 20, count 0 2006.196.07:50:09.34#ibcon#read 4, iclass 20, count 0 2006.196.07:50:09.34#ibcon#about to read 5, iclass 20, count 0 2006.196.07:50:09.34#ibcon#read 5, iclass 20, count 0 2006.196.07:50:09.34#ibcon#about to read 6, iclass 20, count 0 2006.196.07:50:09.34#ibcon#read 6, iclass 20, count 0 2006.196.07:50:09.34#ibcon#end of sib2, iclass 20, count 0 2006.196.07:50:09.34#ibcon#*after write, iclass 20, count 0 2006.196.07:50:09.34#ibcon#*before return 0, iclass 20, count 0 2006.196.07:50:09.34#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.196.07:50:09.34#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.196.07:50:09.34#ibcon#about to clear, iclass 20 cls_cnt 0 2006.196.07:50:09.34#ibcon#cleared, iclass 20 cls_cnt 0 2006.196.07:50:09.34$vc4f8/va=5,7 2006.196.07:50:09.34#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.196.07:50:09.34#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.196.07:50:09.34#ibcon#ireg 11 cls_cnt 2 2006.196.07:50:09.34#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.196.07:50:09.40#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.196.07:50:09.40#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.196.07:50:09.40#ibcon#enter wrdev, iclass 22, count 2 2006.196.07:50:09.40#ibcon#first serial, iclass 22, count 2 2006.196.07:50:09.40#ibcon#enter sib2, iclass 22, count 2 2006.196.07:50:09.40#ibcon#flushed, iclass 22, count 2 2006.196.07:50:09.40#ibcon#about to write, iclass 22, count 2 2006.196.07:50:09.40#ibcon#wrote, iclass 22, count 2 2006.196.07:50:09.40#ibcon#about to read 3, iclass 22, count 2 2006.196.07:50:09.42#ibcon#read 3, iclass 22, count 2 2006.196.07:50:09.42#ibcon#about to read 4, iclass 22, count 2 2006.196.07:50:09.42#ibcon#read 4, iclass 22, count 2 2006.196.07:50:09.42#ibcon#about to read 5, iclass 22, count 2 2006.196.07:50:09.42#ibcon#read 5, iclass 22, count 2 2006.196.07:50:09.42#ibcon#about to read 6, iclass 22, count 2 2006.196.07:50:09.42#ibcon#read 6, iclass 22, count 2 2006.196.07:50:09.42#ibcon#end of sib2, iclass 22, count 2 2006.196.07:50:09.42#ibcon#*mode == 0, iclass 22, count 2 2006.196.07:50:09.42#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.196.07:50:09.42#ibcon#[25=AT05-07\r\n] 2006.196.07:50:09.42#ibcon#*before write, iclass 22, count 2 2006.196.07:50:09.42#ibcon#enter sib2, iclass 22, count 2 2006.196.07:50:09.42#ibcon#flushed, iclass 22, count 2 2006.196.07:50:09.42#ibcon#about to write, iclass 22, count 2 2006.196.07:50:09.42#ibcon#wrote, iclass 22, count 2 2006.196.07:50:09.42#ibcon#about to read 3, iclass 22, count 2 2006.196.07:50:09.45#ibcon#read 3, iclass 22, count 2 2006.196.07:50:09.45#ibcon#about to read 4, iclass 22, count 2 2006.196.07:50:09.45#ibcon#read 4, iclass 22, count 2 2006.196.07:50:09.45#ibcon#about to read 5, iclass 22, count 2 2006.196.07:50:09.45#ibcon#read 5, iclass 22, count 2 2006.196.07:50:09.45#ibcon#about to read 6, iclass 22, count 2 2006.196.07:50:09.45#ibcon#read 6, iclass 22, count 2 2006.196.07:50:09.45#ibcon#end of sib2, iclass 22, count 2 2006.196.07:50:09.45#ibcon#*after write, iclass 22, count 2 2006.196.07:50:09.45#ibcon#*before return 0, iclass 22, count 2 2006.196.07:50:09.45#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.196.07:50:09.45#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.196.07:50:09.45#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.196.07:50:09.45#ibcon#ireg 7 cls_cnt 0 2006.196.07:50:09.45#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.196.07:50:09.57#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.196.07:50:09.57#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.196.07:50:09.57#ibcon#enter wrdev, iclass 22, count 0 2006.196.07:50:09.57#ibcon#first serial, iclass 22, count 0 2006.196.07:50:09.57#ibcon#enter sib2, iclass 22, count 0 2006.196.07:50:09.57#ibcon#flushed, iclass 22, count 0 2006.196.07:50:09.57#ibcon#about to write, iclass 22, count 0 2006.196.07:50:09.57#ibcon#wrote, iclass 22, count 0 2006.196.07:50:09.57#ibcon#about to read 3, iclass 22, count 0 2006.196.07:50:09.59#ibcon#read 3, iclass 22, count 0 2006.196.07:50:09.59#ibcon#about to read 4, iclass 22, count 0 2006.196.07:50:09.59#ibcon#read 4, iclass 22, count 0 2006.196.07:50:09.59#ibcon#about to read 5, iclass 22, count 0 2006.196.07:50:09.59#ibcon#read 5, iclass 22, count 0 2006.196.07:50:09.59#ibcon#about to read 6, iclass 22, count 0 2006.196.07:50:09.59#ibcon#read 6, iclass 22, count 0 2006.196.07:50:09.59#ibcon#end of sib2, iclass 22, count 0 2006.196.07:50:09.59#ibcon#*mode == 0, iclass 22, count 0 2006.196.07:50:09.59#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.196.07:50:09.59#ibcon#[25=USB\r\n] 2006.196.07:50:09.59#ibcon#*before write, iclass 22, count 0 2006.196.07:50:09.59#ibcon#enter sib2, iclass 22, count 0 2006.196.07:50:09.59#ibcon#flushed, iclass 22, count 0 2006.196.07:50:09.59#ibcon#about to write, iclass 22, count 0 2006.196.07:50:09.59#ibcon#wrote, iclass 22, count 0 2006.196.07:50:09.59#ibcon#about to read 3, iclass 22, count 0 2006.196.07:50:09.62#ibcon#read 3, iclass 22, count 0 2006.196.07:50:09.62#ibcon#about to read 4, iclass 22, count 0 2006.196.07:50:09.62#ibcon#read 4, iclass 22, count 0 2006.196.07:50:09.62#ibcon#about to read 5, iclass 22, count 0 2006.196.07:50:09.62#ibcon#read 5, iclass 22, count 0 2006.196.07:50:09.62#ibcon#about to read 6, iclass 22, count 0 2006.196.07:50:09.62#ibcon#read 6, iclass 22, count 0 2006.196.07:50:09.62#ibcon#end of sib2, iclass 22, count 0 2006.196.07:50:09.62#ibcon#*after write, iclass 22, count 0 2006.196.07:50:09.62#ibcon#*before return 0, iclass 22, count 0 2006.196.07:50:09.62#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.196.07:50:09.62#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.196.07:50:09.62#ibcon#about to clear, iclass 22 cls_cnt 0 2006.196.07:50:09.62#ibcon#cleared, iclass 22 cls_cnt 0 2006.196.07:50:09.62$vc4f8/valo=6,772.99 2006.196.07:50:09.62#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.196.07:50:09.62#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.196.07:50:09.62#ibcon#ireg 17 cls_cnt 0 2006.196.07:50:09.62#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.196.07:50:09.62#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.196.07:50:09.62#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.196.07:50:09.62#ibcon#enter wrdev, iclass 24, count 0 2006.196.07:50:09.62#ibcon#first serial, iclass 24, count 0 2006.196.07:50:09.62#ibcon#enter sib2, iclass 24, count 0 2006.196.07:50:09.62#ibcon#flushed, iclass 24, count 0 2006.196.07:50:09.62#ibcon#about to write, iclass 24, count 0 2006.196.07:50:09.62#ibcon#wrote, iclass 24, count 0 2006.196.07:50:09.62#ibcon#about to read 3, iclass 24, count 0 2006.196.07:50:09.64#ibcon#read 3, iclass 24, count 0 2006.196.07:50:09.64#ibcon#about to read 4, iclass 24, count 0 2006.196.07:50:09.64#ibcon#read 4, iclass 24, count 0 2006.196.07:50:09.64#ibcon#about to read 5, iclass 24, count 0 2006.196.07:50:09.64#ibcon#read 5, iclass 24, count 0 2006.196.07:50:09.64#ibcon#about to read 6, iclass 24, count 0 2006.196.07:50:09.64#ibcon#read 6, iclass 24, count 0 2006.196.07:50:09.64#ibcon#end of sib2, iclass 24, count 0 2006.196.07:50:09.64#ibcon#*mode == 0, iclass 24, count 0 2006.196.07:50:09.64#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.196.07:50:09.64#ibcon#[26=FRQ=06,772.99\r\n] 2006.196.07:50:09.64#ibcon#*before write, iclass 24, count 0 2006.196.07:50:09.64#ibcon#enter sib2, iclass 24, count 0 2006.196.07:50:09.64#ibcon#flushed, iclass 24, count 0 2006.196.07:50:09.64#ibcon#about to write, iclass 24, count 0 2006.196.07:50:09.64#ibcon#wrote, iclass 24, count 0 2006.196.07:50:09.64#ibcon#about to read 3, iclass 24, count 0 2006.196.07:50:09.69#ibcon#read 3, iclass 24, count 0 2006.196.07:50:09.69#ibcon#about to read 4, iclass 24, count 0 2006.196.07:50:09.69#ibcon#read 4, iclass 24, count 0 2006.196.07:50:09.69#ibcon#about to read 5, iclass 24, count 0 2006.196.07:50:09.69#ibcon#read 5, iclass 24, count 0 2006.196.07:50:09.69#ibcon#about to read 6, iclass 24, count 0 2006.196.07:50:09.69#ibcon#read 6, iclass 24, count 0 2006.196.07:50:09.69#ibcon#end of sib2, iclass 24, count 0 2006.196.07:50:09.69#ibcon#*after write, iclass 24, count 0 2006.196.07:50:09.69#ibcon#*before return 0, iclass 24, count 0 2006.196.07:50:09.69#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.196.07:50:09.69#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.196.07:50:09.69#ibcon#about to clear, iclass 24 cls_cnt 0 2006.196.07:50:09.69#ibcon#cleared, iclass 24 cls_cnt 0 2006.196.07:50:09.69$vc4f8/va=6,6 2006.196.07:50:09.69#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.196.07:50:09.69#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.196.07:50:09.69#ibcon#ireg 11 cls_cnt 2 2006.196.07:50:09.69#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.196.07:50:09.74#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.196.07:50:09.74#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.196.07:50:09.74#ibcon#enter wrdev, iclass 26, count 2 2006.196.07:50:09.74#ibcon#first serial, iclass 26, count 2 2006.196.07:50:09.74#ibcon#enter sib2, iclass 26, count 2 2006.196.07:50:09.74#ibcon#flushed, iclass 26, count 2 2006.196.07:50:09.74#ibcon#about to write, iclass 26, count 2 2006.196.07:50:09.74#ibcon#wrote, iclass 26, count 2 2006.196.07:50:09.74#ibcon#about to read 3, iclass 26, count 2 2006.196.07:50:09.76#ibcon#read 3, iclass 26, count 2 2006.196.07:50:09.76#ibcon#about to read 4, iclass 26, count 2 2006.196.07:50:09.76#ibcon#read 4, iclass 26, count 2 2006.196.07:50:09.76#ibcon#about to read 5, iclass 26, count 2 2006.196.07:50:09.76#ibcon#read 5, iclass 26, count 2 2006.196.07:50:09.76#ibcon#about to read 6, iclass 26, count 2 2006.196.07:50:09.76#ibcon#read 6, iclass 26, count 2 2006.196.07:50:09.76#ibcon#end of sib2, iclass 26, count 2 2006.196.07:50:09.76#ibcon#*mode == 0, iclass 26, count 2 2006.196.07:50:09.76#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.196.07:50:09.76#ibcon#[25=AT06-06\r\n] 2006.196.07:50:09.76#ibcon#*before write, iclass 26, count 2 2006.196.07:50:09.76#ibcon#enter sib2, iclass 26, count 2 2006.196.07:50:09.76#ibcon#flushed, iclass 26, count 2 2006.196.07:50:09.76#ibcon#about to write, iclass 26, count 2 2006.196.07:50:09.76#ibcon#wrote, iclass 26, count 2 2006.196.07:50:09.76#ibcon#about to read 3, iclass 26, count 2 2006.196.07:50:09.79#ibcon#read 3, iclass 26, count 2 2006.196.07:50:09.79#ibcon#about to read 4, iclass 26, count 2 2006.196.07:50:09.79#ibcon#read 4, iclass 26, count 2 2006.196.07:50:09.79#ibcon#about to read 5, iclass 26, count 2 2006.196.07:50:09.79#ibcon#read 5, iclass 26, count 2 2006.196.07:50:09.79#ibcon#about to read 6, iclass 26, count 2 2006.196.07:50:09.79#ibcon#read 6, iclass 26, count 2 2006.196.07:50:09.79#ibcon#end of sib2, iclass 26, count 2 2006.196.07:50:09.79#ibcon#*after write, iclass 26, count 2 2006.196.07:50:09.79#ibcon#*before return 0, iclass 26, count 2 2006.196.07:50:09.79#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.196.07:50:09.79#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.196.07:50:09.79#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.196.07:50:09.79#ibcon#ireg 7 cls_cnt 0 2006.196.07:50:09.79#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.196.07:50:09.91#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.196.07:50:09.91#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.196.07:50:09.91#ibcon#enter wrdev, iclass 26, count 0 2006.196.07:50:09.91#ibcon#first serial, iclass 26, count 0 2006.196.07:50:09.91#ibcon#enter sib2, iclass 26, count 0 2006.196.07:50:09.91#ibcon#flushed, iclass 26, count 0 2006.196.07:50:09.91#ibcon#about to write, iclass 26, count 0 2006.196.07:50:09.91#ibcon#wrote, iclass 26, count 0 2006.196.07:50:09.91#ibcon#about to read 3, iclass 26, count 0 2006.196.07:50:09.93#ibcon#read 3, iclass 26, count 0 2006.196.07:50:09.93#ibcon#about to read 4, iclass 26, count 0 2006.196.07:50:09.93#ibcon#read 4, iclass 26, count 0 2006.196.07:50:09.93#ibcon#about to read 5, iclass 26, count 0 2006.196.07:50:09.93#ibcon#read 5, iclass 26, count 0 2006.196.07:50:09.93#ibcon#about to read 6, iclass 26, count 0 2006.196.07:50:09.93#ibcon#read 6, iclass 26, count 0 2006.196.07:50:09.93#ibcon#end of sib2, iclass 26, count 0 2006.196.07:50:09.93#ibcon#*mode == 0, iclass 26, count 0 2006.196.07:50:09.93#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.196.07:50:09.93#ibcon#[25=USB\r\n] 2006.196.07:50:09.93#ibcon#*before write, iclass 26, count 0 2006.196.07:50:09.93#ibcon#enter sib2, iclass 26, count 0 2006.196.07:50:09.93#ibcon#flushed, iclass 26, count 0 2006.196.07:50:09.93#ibcon#about to write, iclass 26, count 0 2006.196.07:50:09.93#ibcon#wrote, iclass 26, count 0 2006.196.07:50:09.93#ibcon#about to read 3, iclass 26, count 0 2006.196.07:50:09.96#ibcon#read 3, iclass 26, count 0 2006.196.07:50:09.96#ibcon#about to read 4, iclass 26, count 0 2006.196.07:50:09.96#ibcon#read 4, iclass 26, count 0 2006.196.07:50:09.96#ibcon#about to read 5, iclass 26, count 0 2006.196.07:50:09.96#ibcon#read 5, iclass 26, count 0 2006.196.07:50:09.96#ibcon#about to read 6, iclass 26, count 0 2006.196.07:50:09.96#ibcon#read 6, iclass 26, count 0 2006.196.07:50:09.96#ibcon#end of sib2, iclass 26, count 0 2006.196.07:50:09.96#ibcon#*after write, iclass 26, count 0 2006.196.07:50:09.96#ibcon#*before return 0, iclass 26, count 0 2006.196.07:50:09.96#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.196.07:50:09.96#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.196.07:50:09.96#ibcon#about to clear, iclass 26 cls_cnt 0 2006.196.07:50:09.96#ibcon#cleared, iclass 26 cls_cnt 0 2006.196.07:50:09.96$vc4f8/valo=7,832.99 2006.196.07:50:09.96#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.196.07:50:09.96#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.196.07:50:09.96#ibcon#ireg 17 cls_cnt 0 2006.196.07:50:09.96#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.196.07:50:09.96#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.196.07:50:09.96#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.196.07:50:09.96#ibcon#enter wrdev, iclass 28, count 0 2006.196.07:50:09.96#ibcon#first serial, iclass 28, count 0 2006.196.07:50:09.96#ibcon#enter sib2, iclass 28, count 0 2006.196.07:50:09.96#ibcon#flushed, iclass 28, count 0 2006.196.07:50:09.96#ibcon#about to write, iclass 28, count 0 2006.196.07:50:09.96#ibcon#wrote, iclass 28, count 0 2006.196.07:50:09.96#ibcon#about to read 3, iclass 28, count 0 2006.196.07:50:09.98#ibcon#read 3, iclass 28, count 0 2006.196.07:50:09.98#ibcon#about to read 4, iclass 28, count 0 2006.196.07:50:09.98#ibcon#read 4, iclass 28, count 0 2006.196.07:50:09.98#ibcon#about to read 5, iclass 28, count 0 2006.196.07:50:09.98#ibcon#read 5, iclass 28, count 0 2006.196.07:50:09.98#ibcon#about to read 6, iclass 28, count 0 2006.196.07:50:09.98#ibcon#read 6, iclass 28, count 0 2006.196.07:50:09.98#ibcon#end of sib2, iclass 28, count 0 2006.196.07:50:09.98#ibcon#*mode == 0, iclass 28, count 0 2006.196.07:50:09.98#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.196.07:50:09.98#ibcon#[26=FRQ=07,832.99\r\n] 2006.196.07:50:09.98#ibcon#*before write, iclass 28, count 0 2006.196.07:50:09.98#ibcon#enter sib2, iclass 28, count 0 2006.196.07:50:09.98#ibcon#flushed, iclass 28, count 0 2006.196.07:50:09.98#ibcon#about to write, iclass 28, count 0 2006.196.07:50:09.98#ibcon#wrote, iclass 28, count 0 2006.196.07:50:09.98#ibcon#about to read 3, iclass 28, count 0 2006.196.07:50:10.02#ibcon#read 3, iclass 28, count 0 2006.196.07:50:10.02#ibcon#about to read 4, iclass 28, count 0 2006.196.07:50:10.02#ibcon#read 4, iclass 28, count 0 2006.196.07:50:10.02#ibcon#about to read 5, iclass 28, count 0 2006.196.07:50:10.02#ibcon#read 5, iclass 28, count 0 2006.196.07:50:10.02#ibcon#about to read 6, iclass 28, count 0 2006.196.07:50:10.02#ibcon#read 6, iclass 28, count 0 2006.196.07:50:10.02#ibcon#end of sib2, iclass 28, count 0 2006.196.07:50:10.02#ibcon#*after write, iclass 28, count 0 2006.196.07:50:10.02#ibcon#*before return 0, iclass 28, count 0 2006.196.07:50:10.02#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.196.07:50:10.02#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.196.07:50:10.02#ibcon#about to clear, iclass 28 cls_cnt 0 2006.196.07:50:10.02#ibcon#cleared, iclass 28 cls_cnt 0 2006.196.07:50:10.02$vc4f8/va=7,6 2006.196.07:50:10.02#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.196.07:50:10.02#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.196.07:50:10.02#ibcon#ireg 11 cls_cnt 2 2006.196.07:50:10.02#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.196.07:50:10.08#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.196.07:50:10.08#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.196.07:50:10.08#ibcon#enter wrdev, iclass 30, count 2 2006.196.07:50:10.08#ibcon#first serial, iclass 30, count 2 2006.196.07:50:10.08#ibcon#enter sib2, iclass 30, count 2 2006.196.07:50:10.08#ibcon#flushed, iclass 30, count 2 2006.196.07:50:10.08#ibcon#about to write, iclass 30, count 2 2006.196.07:50:10.08#ibcon#wrote, iclass 30, count 2 2006.196.07:50:10.08#ibcon#about to read 3, iclass 30, count 2 2006.196.07:50:10.10#ibcon#read 3, iclass 30, count 2 2006.196.07:50:10.10#ibcon#about to read 4, iclass 30, count 2 2006.196.07:50:10.10#ibcon#read 4, iclass 30, count 2 2006.196.07:50:10.10#ibcon#about to read 5, iclass 30, count 2 2006.196.07:50:10.10#ibcon#read 5, iclass 30, count 2 2006.196.07:50:10.10#ibcon#about to read 6, iclass 30, count 2 2006.196.07:50:10.10#ibcon#read 6, iclass 30, count 2 2006.196.07:50:10.10#ibcon#end of sib2, iclass 30, count 2 2006.196.07:50:10.10#ibcon#*mode == 0, iclass 30, count 2 2006.196.07:50:10.10#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.196.07:50:10.10#ibcon#[25=AT07-06\r\n] 2006.196.07:50:10.10#ibcon#*before write, iclass 30, count 2 2006.196.07:50:10.10#ibcon#enter sib2, iclass 30, count 2 2006.196.07:50:10.10#ibcon#flushed, iclass 30, count 2 2006.196.07:50:10.10#ibcon#about to write, iclass 30, count 2 2006.196.07:50:10.10#ibcon#wrote, iclass 30, count 2 2006.196.07:50:10.10#ibcon#about to read 3, iclass 30, count 2 2006.196.07:50:10.13#ibcon#read 3, iclass 30, count 2 2006.196.07:50:10.13#ibcon#about to read 4, iclass 30, count 2 2006.196.07:50:10.13#ibcon#read 4, iclass 30, count 2 2006.196.07:50:10.13#ibcon#about to read 5, iclass 30, count 2 2006.196.07:50:10.13#ibcon#read 5, iclass 30, count 2 2006.196.07:50:10.13#ibcon#about to read 6, iclass 30, count 2 2006.196.07:50:10.13#ibcon#read 6, iclass 30, count 2 2006.196.07:50:10.13#ibcon#end of sib2, iclass 30, count 2 2006.196.07:50:10.13#ibcon#*after write, iclass 30, count 2 2006.196.07:50:10.13#ibcon#*before return 0, iclass 30, count 2 2006.196.07:50:10.13#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.196.07:50:10.13#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.196.07:50:10.13#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.196.07:50:10.13#ibcon#ireg 7 cls_cnt 0 2006.196.07:50:10.13#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.196.07:50:10.25#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.196.07:50:10.25#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.196.07:50:10.25#ibcon#enter wrdev, iclass 30, count 0 2006.196.07:50:10.25#ibcon#first serial, iclass 30, count 0 2006.196.07:50:10.25#ibcon#enter sib2, iclass 30, count 0 2006.196.07:50:10.25#ibcon#flushed, iclass 30, count 0 2006.196.07:50:10.25#ibcon#about to write, iclass 30, count 0 2006.196.07:50:10.25#ibcon#wrote, iclass 30, count 0 2006.196.07:50:10.25#ibcon#about to read 3, iclass 30, count 0 2006.196.07:50:10.27#ibcon#read 3, iclass 30, count 0 2006.196.07:50:10.27#ibcon#about to read 4, iclass 30, count 0 2006.196.07:50:10.27#ibcon#read 4, iclass 30, count 0 2006.196.07:50:10.27#ibcon#about to read 5, iclass 30, count 0 2006.196.07:50:10.27#ibcon#read 5, iclass 30, count 0 2006.196.07:50:10.27#ibcon#about to read 6, iclass 30, count 0 2006.196.07:50:10.27#ibcon#read 6, iclass 30, count 0 2006.196.07:50:10.27#ibcon#end of sib2, iclass 30, count 0 2006.196.07:50:10.27#ibcon#*mode == 0, iclass 30, count 0 2006.196.07:50:10.27#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.196.07:50:10.27#ibcon#[25=USB\r\n] 2006.196.07:50:10.27#ibcon#*before write, iclass 30, count 0 2006.196.07:50:10.27#ibcon#enter sib2, iclass 30, count 0 2006.196.07:50:10.27#ibcon#flushed, iclass 30, count 0 2006.196.07:50:10.27#ibcon#about to write, iclass 30, count 0 2006.196.07:50:10.27#ibcon#wrote, iclass 30, count 0 2006.196.07:50:10.27#ibcon#about to read 3, iclass 30, count 0 2006.196.07:50:10.30#ibcon#read 3, iclass 30, count 0 2006.196.07:50:10.30#ibcon#about to read 4, iclass 30, count 0 2006.196.07:50:10.30#ibcon#read 4, iclass 30, count 0 2006.196.07:50:10.30#ibcon#about to read 5, iclass 30, count 0 2006.196.07:50:10.30#ibcon#read 5, iclass 30, count 0 2006.196.07:50:10.30#ibcon#about to read 6, iclass 30, count 0 2006.196.07:50:10.30#ibcon#read 6, iclass 30, count 0 2006.196.07:50:10.30#ibcon#end of sib2, iclass 30, count 0 2006.196.07:50:10.30#ibcon#*after write, iclass 30, count 0 2006.196.07:50:10.30#ibcon#*before return 0, iclass 30, count 0 2006.196.07:50:10.30#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.196.07:50:10.30#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.196.07:50:10.30#ibcon#about to clear, iclass 30 cls_cnt 0 2006.196.07:50:10.30#ibcon#cleared, iclass 30 cls_cnt 0 2006.196.07:50:10.30$vc4f8/valo=8,852.99 2006.196.07:50:10.30#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.196.07:50:10.30#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.196.07:50:10.30#ibcon#ireg 17 cls_cnt 0 2006.196.07:50:10.30#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.196.07:50:10.30#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.196.07:50:10.30#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.196.07:50:10.30#ibcon#enter wrdev, iclass 32, count 0 2006.196.07:50:10.30#ibcon#first serial, iclass 32, count 0 2006.196.07:50:10.30#ibcon#enter sib2, iclass 32, count 0 2006.196.07:50:10.30#ibcon#flushed, iclass 32, count 0 2006.196.07:50:10.30#ibcon#about to write, iclass 32, count 0 2006.196.07:50:10.30#ibcon#wrote, iclass 32, count 0 2006.196.07:50:10.30#ibcon#about to read 3, iclass 32, count 0 2006.196.07:50:10.32#ibcon#read 3, iclass 32, count 0 2006.196.07:50:10.32#ibcon#about to read 4, iclass 32, count 0 2006.196.07:50:10.32#ibcon#read 4, iclass 32, count 0 2006.196.07:50:10.32#ibcon#about to read 5, iclass 32, count 0 2006.196.07:50:10.32#ibcon#read 5, iclass 32, count 0 2006.196.07:50:10.32#ibcon#about to read 6, iclass 32, count 0 2006.196.07:50:10.32#ibcon#read 6, iclass 32, count 0 2006.196.07:50:10.32#ibcon#end of sib2, iclass 32, count 0 2006.196.07:50:10.32#ibcon#*mode == 0, iclass 32, count 0 2006.196.07:50:10.32#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.196.07:50:10.32#ibcon#[26=FRQ=08,852.99\r\n] 2006.196.07:50:10.32#ibcon#*before write, iclass 32, count 0 2006.196.07:50:10.32#ibcon#enter sib2, iclass 32, count 0 2006.196.07:50:10.32#ibcon#flushed, iclass 32, count 0 2006.196.07:50:10.32#ibcon#about to write, iclass 32, count 0 2006.196.07:50:10.32#ibcon#wrote, iclass 32, count 0 2006.196.07:50:10.32#ibcon#about to read 3, iclass 32, count 0 2006.196.07:50:10.37#ibcon#read 3, iclass 32, count 0 2006.196.07:50:10.37#ibcon#about to read 4, iclass 32, count 0 2006.196.07:50:10.37#ibcon#read 4, iclass 32, count 0 2006.196.07:50:10.37#ibcon#about to read 5, iclass 32, count 0 2006.196.07:50:10.37#ibcon#read 5, iclass 32, count 0 2006.196.07:50:10.37#ibcon#about to read 6, iclass 32, count 0 2006.196.07:50:10.37#ibcon#read 6, iclass 32, count 0 2006.196.07:50:10.37#ibcon#end of sib2, iclass 32, count 0 2006.196.07:50:10.37#ibcon#*after write, iclass 32, count 0 2006.196.07:50:10.37#ibcon#*before return 0, iclass 32, count 0 2006.196.07:50:10.37#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.196.07:50:10.37#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.196.07:50:10.37#ibcon#about to clear, iclass 32 cls_cnt 0 2006.196.07:50:10.37#ibcon#cleared, iclass 32 cls_cnt 0 2006.196.07:50:10.37$vc4f8/va=8,7 2006.196.07:50:10.37#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.196.07:50:10.37#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.196.07:50:10.37#ibcon#ireg 11 cls_cnt 2 2006.196.07:50:10.37#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.196.07:50:10.42#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.196.07:50:10.42#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.196.07:50:10.42#ibcon#enter wrdev, iclass 34, count 2 2006.196.07:50:10.42#ibcon#first serial, iclass 34, count 2 2006.196.07:50:10.42#ibcon#enter sib2, iclass 34, count 2 2006.196.07:50:10.42#ibcon#flushed, iclass 34, count 2 2006.196.07:50:10.42#ibcon#about to write, iclass 34, count 2 2006.196.07:50:10.42#ibcon#wrote, iclass 34, count 2 2006.196.07:50:10.42#ibcon#about to read 3, iclass 34, count 2 2006.196.07:50:10.44#ibcon#read 3, iclass 34, count 2 2006.196.07:50:10.44#ibcon#about to read 4, iclass 34, count 2 2006.196.07:50:10.44#ibcon#read 4, iclass 34, count 2 2006.196.07:50:10.44#ibcon#about to read 5, iclass 34, count 2 2006.196.07:50:10.44#ibcon#read 5, iclass 34, count 2 2006.196.07:50:10.44#ibcon#about to read 6, iclass 34, count 2 2006.196.07:50:10.44#ibcon#read 6, iclass 34, count 2 2006.196.07:50:10.44#ibcon#end of sib2, iclass 34, count 2 2006.196.07:50:10.44#ibcon#*mode == 0, iclass 34, count 2 2006.196.07:50:10.44#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.196.07:50:10.44#ibcon#[25=AT08-07\r\n] 2006.196.07:50:10.44#ibcon#*before write, iclass 34, count 2 2006.196.07:50:10.44#ibcon#enter sib2, iclass 34, count 2 2006.196.07:50:10.44#ibcon#flushed, iclass 34, count 2 2006.196.07:50:10.44#ibcon#about to write, iclass 34, count 2 2006.196.07:50:10.44#ibcon#wrote, iclass 34, count 2 2006.196.07:50:10.44#ibcon#about to read 3, iclass 34, count 2 2006.196.07:50:10.47#ibcon#read 3, iclass 34, count 2 2006.196.07:50:10.47#ibcon#about to read 4, iclass 34, count 2 2006.196.07:50:10.47#ibcon#read 4, iclass 34, count 2 2006.196.07:50:10.47#ibcon#about to read 5, iclass 34, count 2 2006.196.07:50:10.47#ibcon#read 5, iclass 34, count 2 2006.196.07:50:10.47#ibcon#about to read 6, iclass 34, count 2 2006.196.07:50:10.47#ibcon#read 6, iclass 34, count 2 2006.196.07:50:10.47#ibcon#end of sib2, iclass 34, count 2 2006.196.07:50:10.47#ibcon#*after write, iclass 34, count 2 2006.196.07:50:10.47#ibcon#*before return 0, iclass 34, count 2 2006.196.07:50:10.47#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.196.07:50:10.47#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.196.07:50:10.47#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.196.07:50:10.47#ibcon#ireg 7 cls_cnt 0 2006.196.07:50:10.47#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.196.07:50:10.59#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.196.07:50:10.59#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.196.07:50:10.59#ibcon#enter wrdev, iclass 34, count 0 2006.196.07:50:10.59#ibcon#first serial, iclass 34, count 0 2006.196.07:50:10.59#ibcon#enter sib2, iclass 34, count 0 2006.196.07:50:10.59#ibcon#flushed, iclass 34, count 0 2006.196.07:50:10.59#ibcon#about to write, iclass 34, count 0 2006.196.07:50:10.59#ibcon#wrote, iclass 34, count 0 2006.196.07:50:10.59#ibcon#about to read 3, iclass 34, count 0 2006.196.07:50:10.61#ibcon#read 3, iclass 34, count 0 2006.196.07:50:10.61#ibcon#about to read 4, iclass 34, count 0 2006.196.07:50:10.61#ibcon#read 4, iclass 34, count 0 2006.196.07:50:10.61#ibcon#about to read 5, iclass 34, count 0 2006.196.07:50:10.61#ibcon#read 5, iclass 34, count 0 2006.196.07:50:10.61#ibcon#about to read 6, iclass 34, count 0 2006.196.07:50:10.61#ibcon#read 6, iclass 34, count 0 2006.196.07:50:10.61#ibcon#end of sib2, iclass 34, count 0 2006.196.07:50:10.61#ibcon#*mode == 0, iclass 34, count 0 2006.196.07:50:10.61#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.196.07:50:10.61#ibcon#[25=USB\r\n] 2006.196.07:50:10.61#ibcon#*before write, iclass 34, count 0 2006.196.07:50:10.61#ibcon#enter sib2, iclass 34, count 0 2006.196.07:50:10.61#ibcon#flushed, iclass 34, count 0 2006.196.07:50:10.61#ibcon#about to write, iclass 34, count 0 2006.196.07:50:10.61#ibcon#wrote, iclass 34, count 0 2006.196.07:50:10.61#ibcon#about to read 3, iclass 34, count 0 2006.196.07:50:10.64#ibcon#read 3, iclass 34, count 0 2006.196.07:50:10.64#ibcon#about to read 4, iclass 34, count 0 2006.196.07:50:10.64#ibcon#read 4, iclass 34, count 0 2006.196.07:50:10.64#ibcon#about to read 5, iclass 34, count 0 2006.196.07:50:10.64#ibcon#read 5, iclass 34, count 0 2006.196.07:50:10.64#ibcon#about to read 6, iclass 34, count 0 2006.196.07:50:10.64#ibcon#read 6, iclass 34, count 0 2006.196.07:50:10.64#ibcon#end of sib2, iclass 34, count 0 2006.196.07:50:10.64#ibcon#*after write, iclass 34, count 0 2006.196.07:50:10.64#ibcon#*before return 0, iclass 34, count 0 2006.196.07:50:10.64#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.196.07:50:10.64#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.196.07:50:10.64#ibcon#about to clear, iclass 34 cls_cnt 0 2006.196.07:50:10.64#ibcon#cleared, iclass 34 cls_cnt 0 2006.196.07:50:10.64$vc4f8/vblo=1,632.99 2006.196.07:50:10.64#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.196.07:50:10.64#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.196.07:50:10.64#ibcon#ireg 17 cls_cnt 0 2006.196.07:50:10.64#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.196.07:50:10.64#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.196.07:50:10.64#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.196.07:50:10.64#ibcon#enter wrdev, iclass 36, count 0 2006.196.07:50:10.64#ibcon#first serial, iclass 36, count 0 2006.196.07:50:10.64#ibcon#enter sib2, iclass 36, count 0 2006.196.07:50:10.64#ibcon#flushed, iclass 36, count 0 2006.196.07:50:10.64#ibcon#about to write, iclass 36, count 0 2006.196.07:50:10.64#ibcon#wrote, iclass 36, count 0 2006.196.07:50:10.64#ibcon#about to read 3, iclass 36, count 0 2006.196.07:50:10.66#ibcon#read 3, iclass 36, count 0 2006.196.07:50:10.66#ibcon#about to read 4, iclass 36, count 0 2006.196.07:50:10.66#ibcon#read 4, iclass 36, count 0 2006.196.07:50:10.66#ibcon#about to read 5, iclass 36, count 0 2006.196.07:50:10.66#ibcon#read 5, iclass 36, count 0 2006.196.07:50:10.66#ibcon#about to read 6, iclass 36, count 0 2006.196.07:50:10.66#ibcon#read 6, iclass 36, count 0 2006.196.07:50:10.66#ibcon#end of sib2, iclass 36, count 0 2006.196.07:50:10.66#ibcon#*mode == 0, iclass 36, count 0 2006.196.07:50:10.66#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.196.07:50:10.66#ibcon#[28=FRQ=01,632.99\r\n] 2006.196.07:50:10.66#ibcon#*before write, iclass 36, count 0 2006.196.07:50:10.66#ibcon#enter sib2, iclass 36, count 0 2006.196.07:50:10.66#ibcon#flushed, iclass 36, count 0 2006.196.07:50:10.66#ibcon#about to write, iclass 36, count 0 2006.196.07:50:10.66#ibcon#wrote, iclass 36, count 0 2006.196.07:50:10.66#ibcon#about to read 3, iclass 36, count 0 2006.196.07:50:10.70#ibcon#read 3, iclass 36, count 0 2006.196.07:50:10.70#ibcon#about to read 4, iclass 36, count 0 2006.196.07:50:10.70#ibcon#read 4, iclass 36, count 0 2006.196.07:50:10.70#ibcon#about to read 5, iclass 36, count 0 2006.196.07:50:10.70#ibcon#read 5, iclass 36, count 0 2006.196.07:50:10.70#ibcon#about to read 6, iclass 36, count 0 2006.196.07:50:10.70#ibcon#read 6, iclass 36, count 0 2006.196.07:50:10.70#ibcon#end of sib2, iclass 36, count 0 2006.196.07:50:10.70#ibcon#*after write, iclass 36, count 0 2006.196.07:50:10.70#ibcon#*before return 0, iclass 36, count 0 2006.196.07:50:10.70#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.196.07:50:10.70#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.196.07:50:10.70#ibcon#about to clear, iclass 36 cls_cnt 0 2006.196.07:50:10.70#ibcon#cleared, iclass 36 cls_cnt 0 2006.196.07:50:10.70$vc4f8/vb=1,4 2006.196.07:50:10.70#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.196.07:50:10.70#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.196.07:50:10.70#ibcon#ireg 11 cls_cnt 2 2006.196.07:50:10.70#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.196.07:50:10.70#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.196.07:50:10.70#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.196.07:50:10.70#ibcon#enter wrdev, iclass 38, count 2 2006.196.07:50:10.70#ibcon#first serial, iclass 38, count 2 2006.196.07:50:10.70#ibcon#enter sib2, iclass 38, count 2 2006.196.07:50:10.70#ibcon#flushed, iclass 38, count 2 2006.196.07:50:10.70#ibcon#about to write, iclass 38, count 2 2006.196.07:50:10.70#ibcon#wrote, iclass 38, count 2 2006.196.07:50:10.70#ibcon#about to read 3, iclass 38, count 2 2006.196.07:50:10.72#ibcon#read 3, iclass 38, count 2 2006.196.07:50:10.72#ibcon#about to read 4, iclass 38, count 2 2006.196.07:50:10.72#ibcon#read 4, iclass 38, count 2 2006.196.07:50:10.72#ibcon#about to read 5, iclass 38, count 2 2006.196.07:50:10.72#ibcon#read 5, iclass 38, count 2 2006.196.07:50:10.72#ibcon#about to read 6, iclass 38, count 2 2006.196.07:50:10.72#ibcon#read 6, iclass 38, count 2 2006.196.07:50:10.72#ibcon#end of sib2, iclass 38, count 2 2006.196.07:50:10.72#ibcon#*mode == 0, iclass 38, count 2 2006.196.07:50:10.72#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.196.07:50:10.72#ibcon#[27=AT01-04\r\n] 2006.196.07:50:10.72#ibcon#*before write, iclass 38, count 2 2006.196.07:50:10.72#ibcon#enter sib2, iclass 38, count 2 2006.196.07:50:10.72#ibcon#flushed, iclass 38, count 2 2006.196.07:50:10.72#ibcon#about to write, iclass 38, count 2 2006.196.07:50:10.72#ibcon#wrote, iclass 38, count 2 2006.196.07:50:10.72#ibcon#about to read 3, iclass 38, count 2 2006.196.07:50:10.75#ibcon#read 3, iclass 38, count 2 2006.196.07:50:10.75#ibcon#about to read 4, iclass 38, count 2 2006.196.07:50:10.75#ibcon#read 4, iclass 38, count 2 2006.196.07:50:10.75#ibcon#about to read 5, iclass 38, count 2 2006.196.07:50:10.75#ibcon#read 5, iclass 38, count 2 2006.196.07:50:10.75#ibcon#about to read 6, iclass 38, count 2 2006.196.07:50:10.75#ibcon#read 6, iclass 38, count 2 2006.196.07:50:10.75#ibcon#end of sib2, iclass 38, count 2 2006.196.07:50:10.75#ibcon#*after write, iclass 38, count 2 2006.196.07:50:10.75#ibcon#*before return 0, iclass 38, count 2 2006.196.07:50:10.75#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.196.07:50:10.75#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.196.07:50:10.75#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.196.07:50:10.75#ibcon#ireg 7 cls_cnt 0 2006.196.07:50:10.75#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.196.07:50:10.87#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.196.07:50:10.87#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.196.07:50:10.87#ibcon#enter wrdev, iclass 38, count 0 2006.196.07:50:10.87#ibcon#first serial, iclass 38, count 0 2006.196.07:50:10.87#ibcon#enter sib2, iclass 38, count 0 2006.196.07:50:10.87#ibcon#flushed, iclass 38, count 0 2006.196.07:50:10.87#ibcon#about to write, iclass 38, count 0 2006.196.07:50:10.87#ibcon#wrote, iclass 38, count 0 2006.196.07:50:10.87#ibcon#about to read 3, iclass 38, count 0 2006.196.07:50:10.89#ibcon#read 3, iclass 38, count 0 2006.196.07:50:10.89#ibcon#about to read 4, iclass 38, count 0 2006.196.07:50:10.89#ibcon#read 4, iclass 38, count 0 2006.196.07:50:10.89#ibcon#about to read 5, iclass 38, count 0 2006.196.07:50:10.89#ibcon#read 5, iclass 38, count 0 2006.196.07:50:10.89#ibcon#about to read 6, iclass 38, count 0 2006.196.07:50:10.89#ibcon#read 6, iclass 38, count 0 2006.196.07:50:10.89#ibcon#end of sib2, iclass 38, count 0 2006.196.07:50:10.89#ibcon#*mode == 0, iclass 38, count 0 2006.196.07:50:10.89#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.196.07:50:10.89#ibcon#[27=USB\r\n] 2006.196.07:50:10.89#ibcon#*before write, iclass 38, count 0 2006.196.07:50:10.89#ibcon#enter sib2, iclass 38, count 0 2006.196.07:50:10.89#ibcon#flushed, iclass 38, count 0 2006.196.07:50:10.89#ibcon#about to write, iclass 38, count 0 2006.196.07:50:10.89#ibcon#wrote, iclass 38, count 0 2006.196.07:50:10.89#ibcon#about to read 3, iclass 38, count 0 2006.196.07:50:10.92#ibcon#read 3, iclass 38, count 0 2006.196.07:50:10.92#ibcon#about to read 4, iclass 38, count 0 2006.196.07:50:10.92#ibcon#read 4, iclass 38, count 0 2006.196.07:50:10.92#ibcon#about to read 5, iclass 38, count 0 2006.196.07:50:10.92#ibcon#read 5, iclass 38, count 0 2006.196.07:50:10.92#ibcon#about to read 6, iclass 38, count 0 2006.196.07:50:10.92#ibcon#read 6, iclass 38, count 0 2006.196.07:50:10.92#ibcon#end of sib2, iclass 38, count 0 2006.196.07:50:10.92#ibcon#*after write, iclass 38, count 0 2006.196.07:50:10.92#ibcon#*before return 0, iclass 38, count 0 2006.196.07:50:10.92#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.196.07:50:10.92#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.196.07:50:10.92#ibcon#about to clear, iclass 38 cls_cnt 0 2006.196.07:50:10.92#ibcon#cleared, iclass 38 cls_cnt 0 2006.196.07:50:10.92$vc4f8/vblo=2,640.99 2006.196.07:50:10.92#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.196.07:50:10.92#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.196.07:50:10.92#ibcon#ireg 17 cls_cnt 0 2006.196.07:50:10.92#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.196.07:50:10.92#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.196.07:50:10.92#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.196.07:50:10.92#ibcon#enter wrdev, iclass 40, count 0 2006.196.07:50:10.92#ibcon#first serial, iclass 40, count 0 2006.196.07:50:10.92#ibcon#enter sib2, iclass 40, count 0 2006.196.07:50:10.92#ibcon#flushed, iclass 40, count 0 2006.196.07:50:10.92#ibcon#about to write, iclass 40, count 0 2006.196.07:50:10.92#ibcon#wrote, iclass 40, count 0 2006.196.07:50:10.92#ibcon#about to read 3, iclass 40, count 0 2006.196.07:50:10.94#ibcon#read 3, iclass 40, count 0 2006.196.07:50:10.94#ibcon#about to read 4, iclass 40, count 0 2006.196.07:50:10.94#ibcon#read 4, iclass 40, count 0 2006.196.07:50:10.94#ibcon#about to read 5, iclass 40, count 0 2006.196.07:50:10.94#ibcon#read 5, iclass 40, count 0 2006.196.07:50:10.94#ibcon#about to read 6, iclass 40, count 0 2006.196.07:50:10.94#ibcon#read 6, iclass 40, count 0 2006.196.07:50:10.94#ibcon#end of sib2, iclass 40, count 0 2006.196.07:50:10.94#ibcon#*mode == 0, iclass 40, count 0 2006.196.07:50:10.94#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.196.07:50:10.94#ibcon#[28=FRQ=02,640.99\r\n] 2006.196.07:50:10.94#ibcon#*before write, iclass 40, count 0 2006.196.07:50:10.94#ibcon#enter sib2, iclass 40, count 0 2006.196.07:50:10.94#ibcon#flushed, iclass 40, count 0 2006.196.07:50:10.94#ibcon#about to write, iclass 40, count 0 2006.196.07:50:10.94#ibcon#wrote, iclass 40, count 0 2006.196.07:50:10.94#ibcon#about to read 3, iclass 40, count 0 2006.196.07:50:10.98#ibcon#read 3, iclass 40, count 0 2006.196.07:50:10.98#ibcon#about to read 4, iclass 40, count 0 2006.196.07:50:10.98#ibcon#read 4, iclass 40, count 0 2006.196.07:50:10.98#ibcon#about to read 5, iclass 40, count 0 2006.196.07:50:10.98#ibcon#read 5, iclass 40, count 0 2006.196.07:50:10.98#ibcon#about to read 6, iclass 40, count 0 2006.196.07:50:10.98#ibcon#read 6, iclass 40, count 0 2006.196.07:50:10.98#ibcon#end of sib2, iclass 40, count 0 2006.196.07:50:10.98#ibcon#*after write, iclass 40, count 0 2006.196.07:50:10.98#ibcon#*before return 0, iclass 40, count 0 2006.196.07:50:10.98#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.196.07:50:10.98#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.196.07:50:10.98#ibcon#about to clear, iclass 40 cls_cnt 0 2006.196.07:50:10.98#ibcon#cleared, iclass 40 cls_cnt 0 2006.196.07:50:10.98$vc4f8/vb=2,4 2006.196.07:50:10.98#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.196.07:50:10.98#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.196.07:50:10.98#ibcon#ireg 11 cls_cnt 2 2006.196.07:50:10.98#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.196.07:50:11.04#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.196.07:50:11.04#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.196.07:50:11.04#ibcon#enter wrdev, iclass 4, count 2 2006.196.07:50:11.04#ibcon#first serial, iclass 4, count 2 2006.196.07:50:11.04#ibcon#enter sib2, iclass 4, count 2 2006.196.07:50:11.04#ibcon#flushed, iclass 4, count 2 2006.196.07:50:11.04#ibcon#about to write, iclass 4, count 2 2006.196.07:50:11.04#ibcon#wrote, iclass 4, count 2 2006.196.07:50:11.04#ibcon#about to read 3, iclass 4, count 2 2006.196.07:50:11.06#ibcon#read 3, iclass 4, count 2 2006.196.07:50:11.06#ibcon#about to read 4, iclass 4, count 2 2006.196.07:50:11.06#ibcon#read 4, iclass 4, count 2 2006.196.07:50:11.06#ibcon#about to read 5, iclass 4, count 2 2006.196.07:50:11.06#ibcon#read 5, iclass 4, count 2 2006.196.07:50:11.06#ibcon#about to read 6, iclass 4, count 2 2006.196.07:50:11.06#ibcon#read 6, iclass 4, count 2 2006.196.07:50:11.06#ibcon#end of sib2, iclass 4, count 2 2006.196.07:50:11.06#ibcon#*mode == 0, iclass 4, count 2 2006.196.07:50:11.06#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.196.07:50:11.06#ibcon#[27=AT02-04\r\n] 2006.196.07:50:11.06#ibcon#*before write, iclass 4, count 2 2006.196.07:50:11.06#ibcon#enter sib2, iclass 4, count 2 2006.196.07:50:11.06#ibcon#flushed, iclass 4, count 2 2006.196.07:50:11.06#ibcon#about to write, iclass 4, count 2 2006.196.07:50:11.06#ibcon#wrote, iclass 4, count 2 2006.196.07:50:11.06#ibcon#about to read 3, iclass 4, count 2 2006.196.07:50:11.09#ibcon#read 3, iclass 4, count 2 2006.196.07:50:11.09#ibcon#about to read 4, iclass 4, count 2 2006.196.07:50:11.09#ibcon#read 4, iclass 4, count 2 2006.196.07:50:11.09#ibcon#about to read 5, iclass 4, count 2 2006.196.07:50:11.09#ibcon#read 5, iclass 4, count 2 2006.196.07:50:11.09#ibcon#about to read 6, iclass 4, count 2 2006.196.07:50:11.09#ibcon#read 6, iclass 4, count 2 2006.196.07:50:11.09#ibcon#end of sib2, iclass 4, count 2 2006.196.07:50:11.09#ibcon#*after write, iclass 4, count 2 2006.196.07:50:11.09#ibcon#*before return 0, iclass 4, count 2 2006.196.07:50:11.09#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.196.07:50:11.09#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.196.07:50:11.09#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.196.07:50:11.09#ibcon#ireg 7 cls_cnt 0 2006.196.07:50:11.09#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.196.07:50:11.21#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.196.07:50:11.21#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.196.07:50:11.21#ibcon#enter wrdev, iclass 4, count 0 2006.196.07:50:11.21#ibcon#first serial, iclass 4, count 0 2006.196.07:50:11.21#ibcon#enter sib2, iclass 4, count 0 2006.196.07:50:11.21#ibcon#flushed, iclass 4, count 0 2006.196.07:50:11.21#ibcon#about to write, iclass 4, count 0 2006.196.07:50:11.21#ibcon#wrote, iclass 4, count 0 2006.196.07:50:11.21#ibcon#about to read 3, iclass 4, count 0 2006.196.07:50:11.24#ibcon#read 3, iclass 4, count 0 2006.196.07:50:11.24#ibcon#about to read 4, iclass 4, count 0 2006.196.07:50:11.24#ibcon#read 4, iclass 4, count 0 2006.196.07:50:11.24#ibcon#about to read 5, iclass 4, count 0 2006.196.07:50:11.24#ibcon#read 5, iclass 4, count 0 2006.196.07:50:11.24#ibcon#about to read 6, iclass 4, count 0 2006.196.07:50:11.24#ibcon#read 6, iclass 4, count 0 2006.196.07:50:11.24#ibcon#end of sib2, iclass 4, count 0 2006.196.07:50:11.24#ibcon#*mode == 0, iclass 4, count 0 2006.196.07:50:11.24#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.196.07:50:11.24#ibcon#[27=USB\r\n] 2006.196.07:50:11.24#ibcon#*before write, iclass 4, count 0 2006.196.07:50:11.24#ibcon#enter sib2, iclass 4, count 0 2006.196.07:50:11.24#ibcon#flushed, iclass 4, count 0 2006.196.07:50:11.24#ibcon#about to write, iclass 4, count 0 2006.196.07:50:11.24#ibcon#wrote, iclass 4, count 0 2006.196.07:50:11.24#ibcon#about to read 3, iclass 4, count 0 2006.196.07:50:11.27#ibcon#read 3, iclass 4, count 0 2006.196.07:50:11.27#ibcon#about to read 4, iclass 4, count 0 2006.196.07:50:11.27#ibcon#read 4, iclass 4, count 0 2006.196.07:50:11.27#ibcon#about to read 5, iclass 4, count 0 2006.196.07:50:11.27#ibcon#read 5, iclass 4, count 0 2006.196.07:50:11.27#ibcon#about to read 6, iclass 4, count 0 2006.196.07:50:11.27#ibcon#read 6, iclass 4, count 0 2006.196.07:50:11.27#ibcon#end of sib2, iclass 4, count 0 2006.196.07:50:11.27#ibcon#*after write, iclass 4, count 0 2006.196.07:50:11.27#ibcon#*before return 0, iclass 4, count 0 2006.196.07:50:11.27#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.196.07:50:11.27#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.196.07:50:11.27#ibcon#about to clear, iclass 4 cls_cnt 0 2006.196.07:50:11.27#ibcon#cleared, iclass 4 cls_cnt 0 2006.196.07:50:11.27$vc4f8/vblo=3,656.99 2006.196.07:50:11.27#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.196.07:50:11.27#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.196.07:50:11.27#ibcon#ireg 17 cls_cnt 0 2006.196.07:50:11.27#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.196.07:50:11.27#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.196.07:50:11.27#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.196.07:50:11.27#ibcon#enter wrdev, iclass 6, count 0 2006.196.07:50:11.27#ibcon#first serial, iclass 6, count 0 2006.196.07:50:11.27#ibcon#enter sib2, iclass 6, count 0 2006.196.07:50:11.27#ibcon#flushed, iclass 6, count 0 2006.196.07:50:11.27#ibcon#about to write, iclass 6, count 0 2006.196.07:50:11.27#ibcon#wrote, iclass 6, count 0 2006.196.07:50:11.27#ibcon#about to read 3, iclass 6, count 0 2006.196.07:50:11.29#ibcon#read 3, iclass 6, count 0 2006.196.07:50:11.29#ibcon#about to read 4, iclass 6, count 0 2006.196.07:50:11.29#ibcon#read 4, iclass 6, count 0 2006.196.07:50:11.29#ibcon#about to read 5, iclass 6, count 0 2006.196.07:50:11.29#ibcon#read 5, iclass 6, count 0 2006.196.07:50:11.29#ibcon#about to read 6, iclass 6, count 0 2006.196.07:50:11.29#ibcon#read 6, iclass 6, count 0 2006.196.07:50:11.29#ibcon#end of sib2, iclass 6, count 0 2006.196.07:50:11.29#ibcon#*mode == 0, iclass 6, count 0 2006.196.07:50:11.29#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.196.07:50:11.29#ibcon#[28=FRQ=03,656.99\r\n] 2006.196.07:50:11.29#ibcon#*before write, iclass 6, count 0 2006.196.07:50:11.29#ibcon#enter sib2, iclass 6, count 0 2006.196.07:50:11.29#ibcon#flushed, iclass 6, count 0 2006.196.07:50:11.29#ibcon#about to write, iclass 6, count 0 2006.196.07:50:11.29#ibcon#wrote, iclass 6, count 0 2006.196.07:50:11.29#ibcon#about to read 3, iclass 6, count 0 2006.196.07:50:11.33#ibcon#read 3, iclass 6, count 0 2006.196.07:50:11.33#ibcon#about to read 4, iclass 6, count 0 2006.196.07:50:11.33#ibcon#read 4, iclass 6, count 0 2006.196.07:50:11.33#ibcon#about to read 5, iclass 6, count 0 2006.196.07:50:11.33#ibcon#read 5, iclass 6, count 0 2006.196.07:50:11.33#ibcon#about to read 6, iclass 6, count 0 2006.196.07:50:11.33#ibcon#read 6, iclass 6, count 0 2006.196.07:50:11.33#ibcon#end of sib2, iclass 6, count 0 2006.196.07:50:11.33#ibcon#*after write, iclass 6, count 0 2006.196.07:50:11.33#ibcon#*before return 0, iclass 6, count 0 2006.196.07:50:11.33#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.196.07:50:11.33#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.196.07:50:11.33#ibcon#about to clear, iclass 6 cls_cnt 0 2006.196.07:50:11.33#ibcon#cleared, iclass 6 cls_cnt 0 2006.196.07:50:11.33$vc4f8/vb=3,4 2006.196.07:50:11.33#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.196.07:50:11.33#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.196.07:50:11.33#ibcon#ireg 11 cls_cnt 2 2006.196.07:50:11.33#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.196.07:50:11.39#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.196.07:50:11.39#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.196.07:50:11.39#ibcon#enter wrdev, iclass 10, count 2 2006.196.07:50:11.39#ibcon#first serial, iclass 10, count 2 2006.196.07:50:11.39#ibcon#enter sib2, iclass 10, count 2 2006.196.07:50:11.39#ibcon#flushed, iclass 10, count 2 2006.196.07:50:11.39#ibcon#about to write, iclass 10, count 2 2006.196.07:50:11.39#ibcon#wrote, iclass 10, count 2 2006.196.07:50:11.39#ibcon#about to read 3, iclass 10, count 2 2006.196.07:50:11.41#ibcon#read 3, iclass 10, count 2 2006.196.07:50:11.41#ibcon#about to read 4, iclass 10, count 2 2006.196.07:50:11.41#ibcon#read 4, iclass 10, count 2 2006.196.07:50:11.41#ibcon#about to read 5, iclass 10, count 2 2006.196.07:50:11.41#ibcon#read 5, iclass 10, count 2 2006.196.07:50:11.41#ibcon#about to read 6, iclass 10, count 2 2006.196.07:50:11.41#ibcon#read 6, iclass 10, count 2 2006.196.07:50:11.41#ibcon#end of sib2, iclass 10, count 2 2006.196.07:50:11.41#ibcon#*mode == 0, iclass 10, count 2 2006.196.07:50:11.41#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.196.07:50:11.41#ibcon#[27=AT03-04\r\n] 2006.196.07:50:11.41#ibcon#*before write, iclass 10, count 2 2006.196.07:50:11.41#ibcon#enter sib2, iclass 10, count 2 2006.196.07:50:11.41#ibcon#flushed, iclass 10, count 2 2006.196.07:50:11.41#ibcon#about to write, iclass 10, count 2 2006.196.07:50:11.41#ibcon#wrote, iclass 10, count 2 2006.196.07:50:11.41#ibcon#about to read 3, iclass 10, count 2 2006.196.07:50:11.44#ibcon#read 3, iclass 10, count 2 2006.196.07:50:11.44#ibcon#about to read 4, iclass 10, count 2 2006.196.07:50:11.44#ibcon#read 4, iclass 10, count 2 2006.196.07:50:11.44#ibcon#about to read 5, iclass 10, count 2 2006.196.07:50:11.44#ibcon#read 5, iclass 10, count 2 2006.196.07:50:11.44#ibcon#about to read 6, iclass 10, count 2 2006.196.07:50:11.44#ibcon#read 6, iclass 10, count 2 2006.196.07:50:11.44#ibcon#end of sib2, iclass 10, count 2 2006.196.07:50:11.44#ibcon#*after write, iclass 10, count 2 2006.196.07:50:11.44#ibcon#*before return 0, iclass 10, count 2 2006.196.07:50:11.44#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.196.07:50:11.44#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.196.07:50:11.44#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.196.07:50:11.44#ibcon#ireg 7 cls_cnt 0 2006.196.07:50:11.44#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.196.07:50:11.56#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.196.07:50:11.56#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.196.07:50:11.56#ibcon#enter wrdev, iclass 10, count 0 2006.196.07:50:11.56#ibcon#first serial, iclass 10, count 0 2006.196.07:50:11.56#ibcon#enter sib2, iclass 10, count 0 2006.196.07:50:11.56#ibcon#flushed, iclass 10, count 0 2006.196.07:50:11.56#ibcon#about to write, iclass 10, count 0 2006.196.07:50:11.56#ibcon#wrote, iclass 10, count 0 2006.196.07:50:11.56#ibcon#about to read 3, iclass 10, count 0 2006.196.07:50:11.58#ibcon#read 3, iclass 10, count 0 2006.196.07:50:11.58#ibcon#about to read 4, iclass 10, count 0 2006.196.07:50:11.58#ibcon#read 4, iclass 10, count 0 2006.196.07:50:11.58#ibcon#about to read 5, iclass 10, count 0 2006.196.07:50:11.58#ibcon#read 5, iclass 10, count 0 2006.196.07:50:11.58#ibcon#about to read 6, iclass 10, count 0 2006.196.07:50:11.58#ibcon#read 6, iclass 10, count 0 2006.196.07:50:11.58#ibcon#end of sib2, iclass 10, count 0 2006.196.07:50:11.58#ibcon#*mode == 0, iclass 10, count 0 2006.196.07:50:11.58#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.196.07:50:11.58#ibcon#[27=USB\r\n] 2006.196.07:50:11.58#ibcon#*before write, iclass 10, count 0 2006.196.07:50:11.58#ibcon#enter sib2, iclass 10, count 0 2006.196.07:50:11.58#ibcon#flushed, iclass 10, count 0 2006.196.07:50:11.58#ibcon#about to write, iclass 10, count 0 2006.196.07:50:11.58#ibcon#wrote, iclass 10, count 0 2006.196.07:50:11.58#ibcon#about to read 3, iclass 10, count 0 2006.196.07:50:11.61#ibcon#read 3, iclass 10, count 0 2006.196.07:50:11.61#ibcon#about to read 4, iclass 10, count 0 2006.196.07:50:11.61#ibcon#read 4, iclass 10, count 0 2006.196.07:50:11.61#ibcon#about to read 5, iclass 10, count 0 2006.196.07:50:11.61#ibcon#read 5, iclass 10, count 0 2006.196.07:50:11.61#ibcon#about to read 6, iclass 10, count 0 2006.196.07:50:11.61#ibcon#read 6, iclass 10, count 0 2006.196.07:50:11.61#ibcon#end of sib2, iclass 10, count 0 2006.196.07:50:11.61#ibcon#*after write, iclass 10, count 0 2006.196.07:50:11.61#ibcon#*before return 0, iclass 10, count 0 2006.196.07:50:11.61#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.196.07:50:11.61#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.196.07:50:11.61#ibcon#about to clear, iclass 10 cls_cnt 0 2006.196.07:50:11.61#ibcon#cleared, iclass 10 cls_cnt 0 2006.196.07:50:11.61$vc4f8/vblo=4,712.99 2006.196.07:50:11.61#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.196.07:50:11.61#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.196.07:50:11.61#ibcon#ireg 17 cls_cnt 0 2006.196.07:50:11.61#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.196.07:50:11.61#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.196.07:50:11.61#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.196.07:50:11.61#ibcon#enter wrdev, iclass 12, count 0 2006.196.07:50:11.61#ibcon#first serial, iclass 12, count 0 2006.196.07:50:11.61#ibcon#enter sib2, iclass 12, count 0 2006.196.07:50:11.61#ibcon#flushed, iclass 12, count 0 2006.196.07:50:11.61#ibcon#about to write, iclass 12, count 0 2006.196.07:50:11.61#ibcon#wrote, iclass 12, count 0 2006.196.07:50:11.61#ibcon#about to read 3, iclass 12, count 0 2006.196.07:50:11.63#ibcon#read 3, iclass 12, count 0 2006.196.07:50:11.63#ibcon#about to read 4, iclass 12, count 0 2006.196.07:50:11.63#ibcon#read 4, iclass 12, count 0 2006.196.07:50:11.63#ibcon#about to read 5, iclass 12, count 0 2006.196.07:50:11.63#ibcon#read 5, iclass 12, count 0 2006.196.07:50:11.63#ibcon#about to read 6, iclass 12, count 0 2006.196.07:50:11.63#ibcon#read 6, iclass 12, count 0 2006.196.07:50:11.63#ibcon#end of sib2, iclass 12, count 0 2006.196.07:50:11.63#ibcon#*mode == 0, iclass 12, count 0 2006.196.07:50:11.63#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.196.07:50:11.63#ibcon#[28=FRQ=04,712.99\r\n] 2006.196.07:50:11.63#ibcon#*before write, iclass 12, count 0 2006.196.07:50:11.63#ibcon#enter sib2, iclass 12, count 0 2006.196.07:50:11.63#ibcon#flushed, iclass 12, count 0 2006.196.07:50:11.63#ibcon#about to write, iclass 12, count 0 2006.196.07:50:11.63#ibcon#wrote, iclass 12, count 0 2006.196.07:50:11.63#ibcon#about to read 3, iclass 12, count 0 2006.196.07:50:11.67#ibcon#read 3, iclass 12, count 0 2006.196.07:50:11.67#ibcon#about to read 4, iclass 12, count 0 2006.196.07:50:11.67#ibcon#read 4, iclass 12, count 0 2006.196.07:50:11.67#ibcon#about to read 5, iclass 12, count 0 2006.196.07:50:11.67#ibcon#read 5, iclass 12, count 0 2006.196.07:50:11.67#ibcon#about to read 6, iclass 12, count 0 2006.196.07:50:11.67#ibcon#read 6, iclass 12, count 0 2006.196.07:50:11.67#ibcon#end of sib2, iclass 12, count 0 2006.196.07:50:11.67#ibcon#*after write, iclass 12, count 0 2006.196.07:50:11.67#ibcon#*before return 0, iclass 12, count 0 2006.196.07:50:11.67#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.196.07:50:11.67#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.196.07:50:11.67#ibcon#about to clear, iclass 12 cls_cnt 0 2006.196.07:50:11.67#ibcon#cleared, iclass 12 cls_cnt 0 2006.196.07:50:11.67$vc4f8/vb=4,4 2006.196.07:50:11.67#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.196.07:50:11.67#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.196.07:50:11.67#ibcon#ireg 11 cls_cnt 2 2006.196.07:50:11.67#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.196.07:50:11.73#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.196.07:50:11.73#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.196.07:50:11.73#ibcon#enter wrdev, iclass 14, count 2 2006.196.07:50:11.73#ibcon#first serial, iclass 14, count 2 2006.196.07:50:11.73#ibcon#enter sib2, iclass 14, count 2 2006.196.07:50:11.73#ibcon#flushed, iclass 14, count 2 2006.196.07:50:11.73#ibcon#about to write, iclass 14, count 2 2006.196.07:50:11.73#ibcon#wrote, iclass 14, count 2 2006.196.07:50:11.73#ibcon#about to read 3, iclass 14, count 2 2006.196.07:50:11.75#ibcon#read 3, iclass 14, count 2 2006.196.07:50:11.75#ibcon#about to read 4, iclass 14, count 2 2006.196.07:50:11.75#ibcon#read 4, iclass 14, count 2 2006.196.07:50:11.75#ibcon#about to read 5, iclass 14, count 2 2006.196.07:50:11.75#ibcon#read 5, iclass 14, count 2 2006.196.07:50:11.75#ibcon#about to read 6, iclass 14, count 2 2006.196.07:50:11.75#ibcon#read 6, iclass 14, count 2 2006.196.07:50:11.75#ibcon#end of sib2, iclass 14, count 2 2006.196.07:50:11.75#ibcon#*mode == 0, iclass 14, count 2 2006.196.07:50:11.75#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.196.07:50:11.75#ibcon#[27=AT04-04\r\n] 2006.196.07:50:11.75#ibcon#*before write, iclass 14, count 2 2006.196.07:50:11.75#ibcon#enter sib2, iclass 14, count 2 2006.196.07:50:11.75#ibcon#flushed, iclass 14, count 2 2006.196.07:50:11.75#ibcon#about to write, iclass 14, count 2 2006.196.07:50:11.75#ibcon#wrote, iclass 14, count 2 2006.196.07:50:11.75#ibcon#about to read 3, iclass 14, count 2 2006.196.07:50:11.78#ibcon#read 3, iclass 14, count 2 2006.196.07:50:11.78#ibcon#about to read 4, iclass 14, count 2 2006.196.07:50:11.78#ibcon#read 4, iclass 14, count 2 2006.196.07:50:11.78#ibcon#about to read 5, iclass 14, count 2 2006.196.07:50:11.78#ibcon#read 5, iclass 14, count 2 2006.196.07:50:11.78#ibcon#about to read 6, iclass 14, count 2 2006.196.07:50:11.78#ibcon#read 6, iclass 14, count 2 2006.196.07:50:11.78#ibcon#end of sib2, iclass 14, count 2 2006.196.07:50:11.78#ibcon#*after write, iclass 14, count 2 2006.196.07:50:11.78#ibcon#*before return 0, iclass 14, count 2 2006.196.07:50:11.78#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.196.07:50:11.78#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.196.07:50:11.78#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.196.07:50:11.78#ibcon#ireg 7 cls_cnt 0 2006.196.07:50:11.78#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.196.07:50:11.90#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.196.07:50:11.90#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.196.07:50:11.90#ibcon#enter wrdev, iclass 14, count 0 2006.196.07:50:11.90#ibcon#first serial, iclass 14, count 0 2006.196.07:50:11.90#ibcon#enter sib2, iclass 14, count 0 2006.196.07:50:11.90#ibcon#flushed, iclass 14, count 0 2006.196.07:50:11.90#ibcon#about to write, iclass 14, count 0 2006.196.07:50:11.90#ibcon#wrote, iclass 14, count 0 2006.196.07:50:11.90#ibcon#about to read 3, iclass 14, count 0 2006.196.07:50:11.92#ibcon#read 3, iclass 14, count 0 2006.196.07:50:11.92#ibcon#about to read 4, iclass 14, count 0 2006.196.07:50:11.92#ibcon#read 4, iclass 14, count 0 2006.196.07:50:11.92#ibcon#about to read 5, iclass 14, count 0 2006.196.07:50:11.92#ibcon#read 5, iclass 14, count 0 2006.196.07:50:11.92#ibcon#about to read 6, iclass 14, count 0 2006.196.07:50:11.92#ibcon#read 6, iclass 14, count 0 2006.196.07:50:11.92#ibcon#end of sib2, iclass 14, count 0 2006.196.07:50:11.92#ibcon#*mode == 0, iclass 14, count 0 2006.196.07:50:11.92#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.196.07:50:11.92#ibcon#[27=USB\r\n] 2006.196.07:50:11.92#ibcon#*before write, iclass 14, count 0 2006.196.07:50:11.92#ibcon#enter sib2, iclass 14, count 0 2006.196.07:50:11.92#ibcon#flushed, iclass 14, count 0 2006.196.07:50:11.92#ibcon#about to write, iclass 14, count 0 2006.196.07:50:11.92#ibcon#wrote, iclass 14, count 0 2006.196.07:50:11.92#ibcon#about to read 3, iclass 14, count 0 2006.196.07:50:11.95#ibcon#read 3, iclass 14, count 0 2006.196.07:50:11.95#ibcon#about to read 4, iclass 14, count 0 2006.196.07:50:11.95#ibcon#read 4, iclass 14, count 0 2006.196.07:50:11.95#ibcon#about to read 5, iclass 14, count 0 2006.196.07:50:11.95#ibcon#read 5, iclass 14, count 0 2006.196.07:50:11.95#ibcon#about to read 6, iclass 14, count 0 2006.196.07:50:11.95#ibcon#read 6, iclass 14, count 0 2006.196.07:50:11.95#ibcon#end of sib2, iclass 14, count 0 2006.196.07:50:11.95#ibcon#*after write, iclass 14, count 0 2006.196.07:50:11.95#ibcon#*before return 0, iclass 14, count 0 2006.196.07:50:11.95#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.196.07:50:11.95#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.196.07:50:11.95#ibcon#about to clear, iclass 14 cls_cnt 0 2006.196.07:50:11.95#ibcon#cleared, iclass 14 cls_cnt 0 2006.196.07:50:11.95$vc4f8/vblo=5,744.99 2006.196.07:50:11.95#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.196.07:50:11.95#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.196.07:50:11.95#ibcon#ireg 17 cls_cnt 0 2006.196.07:50:11.95#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.196.07:50:11.95#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.196.07:50:11.95#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.196.07:50:11.95#ibcon#enter wrdev, iclass 16, count 0 2006.196.07:50:11.95#ibcon#first serial, iclass 16, count 0 2006.196.07:50:11.95#ibcon#enter sib2, iclass 16, count 0 2006.196.07:50:11.95#ibcon#flushed, iclass 16, count 0 2006.196.07:50:11.95#ibcon#about to write, iclass 16, count 0 2006.196.07:50:11.95#ibcon#wrote, iclass 16, count 0 2006.196.07:50:11.95#ibcon#about to read 3, iclass 16, count 0 2006.196.07:50:11.97#ibcon#read 3, iclass 16, count 0 2006.196.07:50:11.97#ibcon#about to read 4, iclass 16, count 0 2006.196.07:50:11.97#ibcon#read 4, iclass 16, count 0 2006.196.07:50:11.97#ibcon#about to read 5, iclass 16, count 0 2006.196.07:50:11.97#ibcon#read 5, iclass 16, count 0 2006.196.07:50:11.97#ibcon#about to read 6, iclass 16, count 0 2006.196.07:50:11.97#ibcon#read 6, iclass 16, count 0 2006.196.07:50:11.97#ibcon#end of sib2, iclass 16, count 0 2006.196.07:50:11.97#ibcon#*mode == 0, iclass 16, count 0 2006.196.07:50:11.97#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.196.07:50:11.97#ibcon#[28=FRQ=05,744.99\r\n] 2006.196.07:50:11.97#ibcon#*before write, iclass 16, count 0 2006.196.07:50:11.97#ibcon#enter sib2, iclass 16, count 0 2006.196.07:50:11.97#ibcon#flushed, iclass 16, count 0 2006.196.07:50:11.97#ibcon#about to write, iclass 16, count 0 2006.196.07:50:11.97#ibcon#wrote, iclass 16, count 0 2006.196.07:50:11.97#ibcon#about to read 3, iclass 16, count 0 2006.196.07:50:12.02#ibcon#read 3, iclass 16, count 0 2006.196.07:50:12.02#ibcon#about to read 4, iclass 16, count 0 2006.196.07:50:12.02#ibcon#read 4, iclass 16, count 0 2006.196.07:50:12.02#ibcon#about to read 5, iclass 16, count 0 2006.196.07:50:12.02#ibcon#read 5, iclass 16, count 0 2006.196.07:50:12.02#ibcon#about to read 6, iclass 16, count 0 2006.196.07:50:12.02#ibcon#read 6, iclass 16, count 0 2006.196.07:50:12.02#ibcon#end of sib2, iclass 16, count 0 2006.196.07:50:12.02#ibcon#*after write, iclass 16, count 0 2006.196.07:50:12.02#ibcon#*before return 0, iclass 16, count 0 2006.196.07:50:12.02#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.196.07:50:12.02#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.196.07:50:12.02#ibcon#about to clear, iclass 16 cls_cnt 0 2006.196.07:50:12.02#ibcon#cleared, iclass 16 cls_cnt 0 2006.196.07:50:12.02$vc4f8/vb=5,4 2006.196.07:50:12.02#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.196.07:50:12.02#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.196.07:50:12.02#ibcon#ireg 11 cls_cnt 2 2006.196.07:50:12.02#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.196.07:50:12.07#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.196.07:50:12.07#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.196.07:50:12.07#ibcon#enter wrdev, iclass 18, count 2 2006.196.07:50:12.07#ibcon#first serial, iclass 18, count 2 2006.196.07:50:12.07#ibcon#enter sib2, iclass 18, count 2 2006.196.07:50:12.07#ibcon#flushed, iclass 18, count 2 2006.196.07:50:12.07#ibcon#about to write, iclass 18, count 2 2006.196.07:50:12.07#ibcon#wrote, iclass 18, count 2 2006.196.07:50:12.07#ibcon#about to read 3, iclass 18, count 2 2006.196.07:50:12.09#ibcon#read 3, iclass 18, count 2 2006.196.07:50:12.09#ibcon#about to read 4, iclass 18, count 2 2006.196.07:50:12.09#ibcon#read 4, iclass 18, count 2 2006.196.07:50:12.09#ibcon#about to read 5, iclass 18, count 2 2006.196.07:50:12.09#ibcon#read 5, iclass 18, count 2 2006.196.07:50:12.09#ibcon#about to read 6, iclass 18, count 2 2006.196.07:50:12.09#ibcon#read 6, iclass 18, count 2 2006.196.07:50:12.09#ibcon#end of sib2, iclass 18, count 2 2006.196.07:50:12.09#ibcon#*mode == 0, iclass 18, count 2 2006.196.07:50:12.09#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.196.07:50:12.09#ibcon#[27=AT05-04\r\n] 2006.196.07:50:12.09#ibcon#*before write, iclass 18, count 2 2006.196.07:50:12.09#ibcon#enter sib2, iclass 18, count 2 2006.196.07:50:12.09#ibcon#flushed, iclass 18, count 2 2006.196.07:50:12.09#ibcon#about to write, iclass 18, count 2 2006.196.07:50:12.09#ibcon#wrote, iclass 18, count 2 2006.196.07:50:12.09#ibcon#about to read 3, iclass 18, count 2 2006.196.07:50:12.12#ibcon#read 3, iclass 18, count 2 2006.196.07:50:12.12#ibcon#about to read 4, iclass 18, count 2 2006.196.07:50:12.12#ibcon#read 4, iclass 18, count 2 2006.196.07:50:12.12#ibcon#about to read 5, iclass 18, count 2 2006.196.07:50:12.12#ibcon#read 5, iclass 18, count 2 2006.196.07:50:12.12#ibcon#about to read 6, iclass 18, count 2 2006.196.07:50:12.12#ibcon#read 6, iclass 18, count 2 2006.196.07:50:12.12#ibcon#end of sib2, iclass 18, count 2 2006.196.07:50:12.12#ibcon#*after write, iclass 18, count 2 2006.196.07:50:12.12#ibcon#*before return 0, iclass 18, count 2 2006.196.07:50:12.12#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.196.07:50:12.12#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.196.07:50:12.12#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.196.07:50:12.12#ibcon#ireg 7 cls_cnt 0 2006.196.07:50:12.12#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.196.07:50:12.24#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.196.07:50:12.24#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.196.07:50:12.24#ibcon#enter wrdev, iclass 18, count 0 2006.196.07:50:12.24#ibcon#first serial, iclass 18, count 0 2006.196.07:50:12.24#ibcon#enter sib2, iclass 18, count 0 2006.196.07:50:12.24#ibcon#flushed, iclass 18, count 0 2006.196.07:50:12.24#ibcon#about to write, iclass 18, count 0 2006.196.07:50:12.24#ibcon#wrote, iclass 18, count 0 2006.196.07:50:12.24#ibcon#about to read 3, iclass 18, count 0 2006.196.07:50:12.26#ibcon#read 3, iclass 18, count 0 2006.196.07:50:12.26#ibcon#about to read 4, iclass 18, count 0 2006.196.07:50:12.26#ibcon#read 4, iclass 18, count 0 2006.196.07:50:12.26#ibcon#about to read 5, iclass 18, count 0 2006.196.07:50:12.26#ibcon#read 5, iclass 18, count 0 2006.196.07:50:12.26#ibcon#about to read 6, iclass 18, count 0 2006.196.07:50:12.26#ibcon#read 6, iclass 18, count 0 2006.196.07:50:12.26#ibcon#end of sib2, iclass 18, count 0 2006.196.07:50:12.26#ibcon#*mode == 0, iclass 18, count 0 2006.196.07:50:12.26#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.196.07:50:12.26#ibcon#[27=USB\r\n] 2006.196.07:50:12.26#ibcon#*before write, iclass 18, count 0 2006.196.07:50:12.26#ibcon#enter sib2, iclass 18, count 0 2006.196.07:50:12.26#ibcon#flushed, iclass 18, count 0 2006.196.07:50:12.26#ibcon#about to write, iclass 18, count 0 2006.196.07:50:12.26#ibcon#wrote, iclass 18, count 0 2006.196.07:50:12.26#ibcon#about to read 3, iclass 18, count 0 2006.196.07:50:12.29#ibcon#read 3, iclass 18, count 0 2006.196.07:50:12.29#ibcon#about to read 4, iclass 18, count 0 2006.196.07:50:12.29#ibcon#read 4, iclass 18, count 0 2006.196.07:50:12.29#ibcon#about to read 5, iclass 18, count 0 2006.196.07:50:12.29#ibcon#read 5, iclass 18, count 0 2006.196.07:50:12.29#ibcon#about to read 6, iclass 18, count 0 2006.196.07:50:12.29#ibcon#read 6, iclass 18, count 0 2006.196.07:50:12.29#ibcon#end of sib2, iclass 18, count 0 2006.196.07:50:12.29#ibcon#*after write, iclass 18, count 0 2006.196.07:50:12.29#ibcon#*before return 0, iclass 18, count 0 2006.196.07:50:12.29#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.196.07:50:12.29#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.196.07:50:12.29#ibcon#about to clear, iclass 18 cls_cnt 0 2006.196.07:50:12.29#ibcon#cleared, iclass 18 cls_cnt 0 2006.196.07:50:12.29$vc4f8/vblo=6,752.99 2006.196.07:50:12.29#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.196.07:50:12.29#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.196.07:50:12.29#ibcon#ireg 17 cls_cnt 0 2006.196.07:50:12.29#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.196.07:50:12.29#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.196.07:50:12.29#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.196.07:50:12.29#ibcon#enter wrdev, iclass 20, count 0 2006.196.07:50:12.29#ibcon#first serial, iclass 20, count 0 2006.196.07:50:12.29#ibcon#enter sib2, iclass 20, count 0 2006.196.07:50:12.29#ibcon#flushed, iclass 20, count 0 2006.196.07:50:12.29#ibcon#about to write, iclass 20, count 0 2006.196.07:50:12.29#ibcon#wrote, iclass 20, count 0 2006.196.07:50:12.29#ibcon#about to read 3, iclass 20, count 0 2006.196.07:50:12.31#ibcon#read 3, iclass 20, count 0 2006.196.07:50:12.31#ibcon#about to read 4, iclass 20, count 0 2006.196.07:50:12.31#ibcon#read 4, iclass 20, count 0 2006.196.07:50:12.31#ibcon#about to read 5, iclass 20, count 0 2006.196.07:50:12.31#ibcon#read 5, iclass 20, count 0 2006.196.07:50:12.31#ibcon#about to read 6, iclass 20, count 0 2006.196.07:50:12.31#ibcon#read 6, iclass 20, count 0 2006.196.07:50:12.31#ibcon#end of sib2, iclass 20, count 0 2006.196.07:50:12.31#ibcon#*mode == 0, iclass 20, count 0 2006.196.07:50:12.31#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.196.07:50:12.31#ibcon#[28=FRQ=06,752.99\r\n] 2006.196.07:50:12.31#ibcon#*before write, iclass 20, count 0 2006.196.07:50:12.31#ibcon#enter sib2, iclass 20, count 0 2006.196.07:50:12.31#ibcon#flushed, iclass 20, count 0 2006.196.07:50:12.31#ibcon#about to write, iclass 20, count 0 2006.196.07:50:12.31#ibcon#wrote, iclass 20, count 0 2006.196.07:50:12.31#ibcon#about to read 3, iclass 20, count 0 2006.196.07:50:12.35#ibcon#read 3, iclass 20, count 0 2006.196.07:50:12.35#ibcon#about to read 4, iclass 20, count 0 2006.196.07:50:12.35#ibcon#read 4, iclass 20, count 0 2006.196.07:50:12.35#ibcon#about to read 5, iclass 20, count 0 2006.196.07:50:12.35#ibcon#read 5, iclass 20, count 0 2006.196.07:50:12.35#ibcon#about to read 6, iclass 20, count 0 2006.196.07:50:12.35#ibcon#read 6, iclass 20, count 0 2006.196.07:50:12.35#ibcon#end of sib2, iclass 20, count 0 2006.196.07:50:12.35#ibcon#*after write, iclass 20, count 0 2006.196.07:50:12.35#ibcon#*before return 0, iclass 20, count 0 2006.196.07:50:12.35#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.196.07:50:12.35#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.196.07:50:12.35#ibcon#about to clear, iclass 20 cls_cnt 0 2006.196.07:50:12.35#ibcon#cleared, iclass 20 cls_cnt 0 2006.196.07:50:12.35$vc4f8/vb=6,4 2006.196.07:50:12.35#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.196.07:50:12.35#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.196.07:50:12.35#ibcon#ireg 11 cls_cnt 2 2006.196.07:50:12.35#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.196.07:50:12.41#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.196.07:50:12.41#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.196.07:50:12.41#ibcon#enter wrdev, iclass 22, count 2 2006.196.07:50:12.41#ibcon#first serial, iclass 22, count 2 2006.196.07:50:12.41#ibcon#enter sib2, iclass 22, count 2 2006.196.07:50:12.41#ibcon#flushed, iclass 22, count 2 2006.196.07:50:12.41#ibcon#about to write, iclass 22, count 2 2006.196.07:50:12.41#ibcon#wrote, iclass 22, count 2 2006.196.07:50:12.41#ibcon#about to read 3, iclass 22, count 2 2006.196.07:50:12.43#ibcon#read 3, iclass 22, count 2 2006.196.07:50:12.43#ibcon#about to read 4, iclass 22, count 2 2006.196.07:50:12.43#ibcon#read 4, iclass 22, count 2 2006.196.07:50:12.43#ibcon#about to read 5, iclass 22, count 2 2006.196.07:50:12.43#ibcon#read 5, iclass 22, count 2 2006.196.07:50:12.43#ibcon#about to read 6, iclass 22, count 2 2006.196.07:50:12.43#ibcon#read 6, iclass 22, count 2 2006.196.07:50:12.43#ibcon#end of sib2, iclass 22, count 2 2006.196.07:50:12.43#ibcon#*mode == 0, iclass 22, count 2 2006.196.07:50:12.43#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.196.07:50:12.43#ibcon#[27=AT06-04\r\n] 2006.196.07:50:12.43#ibcon#*before write, iclass 22, count 2 2006.196.07:50:12.43#ibcon#enter sib2, iclass 22, count 2 2006.196.07:50:12.43#ibcon#flushed, iclass 22, count 2 2006.196.07:50:12.43#ibcon#about to write, iclass 22, count 2 2006.196.07:50:12.43#ibcon#wrote, iclass 22, count 2 2006.196.07:50:12.43#ibcon#about to read 3, iclass 22, count 2 2006.196.07:50:12.46#ibcon#read 3, iclass 22, count 2 2006.196.07:50:12.46#ibcon#about to read 4, iclass 22, count 2 2006.196.07:50:12.46#ibcon#read 4, iclass 22, count 2 2006.196.07:50:12.46#ibcon#about to read 5, iclass 22, count 2 2006.196.07:50:12.46#ibcon#read 5, iclass 22, count 2 2006.196.07:50:12.46#ibcon#about to read 6, iclass 22, count 2 2006.196.07:50:12.46#ibcon#read 6, iclass 22, count 2 2006.196.07:50:12.46#ibcon#end of sib2, iclass 22, count 2 2006.196.07:50:12.46#ibcon#*after write, iclass 22, count 2 2006.196.07:50:12.46#ibcon#*before return 0, iclass 22, count 2 2006.196.07:50:12.46#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.196.07:50:12.46#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.196.07:50:12.46#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.196.07:50:12.46#ibcon#ireg 7 cls_cnt 0 2006.196.07:50:12.46#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.196.07:50:12.58#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.196.07:50:12.58#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.196.07:50:12.58#ibcon#enter wrdev, iclass 22, count 0 2006.196.07:50:12.58#ibcon#first serial, iclass 22, count 0 2006.196.07:50:12.58#ibcon#enter sib2, iclass 22, count 0 2006.196.07:50:12.58#ibcon#flushed, iclass 22, count 0 2006.196.07:50:12.58#ibcon#about to write, iclass 22, count 0 2006.196.07:50:12.58#ibcon#wrote, iclass 22, count 0 2006.196.07:50:12.58#ibcon#about to read 3, iclass 22, count 0 2006.196.07:50:12.60#ibcon#read 3, iclass 22, count 0 2006.196.07:50:12.60#ibcon#about to read 4, iclass 22, count 0 2006.196.07:50:12.60#ibcon#read 4, iclass 22, count 0 2006.196.07:50:12.60#ibcon#about to read 5, iclass 22, count 0 2006.196.07:50:12.60#ibcon#read 5, iclass 22, count 0 2006.196.07:50:12.60#ibcon#about to read 6, iclass 22, count 0 2006.196.07:50:12.60#ibcon#read 6, iclass 22, count 0 2006.196.07:50:12.60#ibcon#end of sib2, iclass 22, count 0 2006.196.07:50:12.60#ibcon#*mode == 0, iclass 22, count 0 2006.196.07:50:12.60#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.196.07:50:12.60#ibcon#[27=USB\r\n] 2006.196.07:50:12.60#ibcon#*before write, iclass 22, count 0 2006.196.07:50:12.60#ibcon#enter sib2, iclass 22, count 0 2006.196.07:50:12.60#ibcon#flushed, iclass 22, count 0 2006.196.07:50:12.60#ibcon#about to write, iclass 22, count 0 2006.196.07:50:12.60#ibcon#wrote, iclass 22, count 0 2006.196.07:50:12.60#ibcon#about to read 3, iclass 22, count 0 2006.196.07:50:12.63#ibcon#read 3, iclass 22, count 0 2006.196.07:50:12.63#ibcon#about to read 4, iclass 22, count 0 2006.196.07:50:12.63#ibcon#read 4, iclass 22, count 0 2006.196.07:50:12.63#ibcon#about to read 5, iclass 22, count 0 2006.196.07:50:12.63#ibcon#read 5, iclass 22, count 0 2006.196.07:50:12.63#ibcon#about to read 6, iclass 22, count 0 2006.196.07:50:12.63#ibcon#read 6, iclass 22, count 0 2006.196.07:50:12.63#ibcon#end of sib2, iclass 22, count 0 2006.196.07:50:12.63#ibcon#*after write, iclass 22, count 0 2006.196.07:50:12.63#ibcon#*before return 0, iclass 22, count 0 2006.196.07:50:12.63#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.196.07:50:12.63#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.196.07:50:12.63#ibcon#about to clear, iclass 22 cls_cnt 0 2006.196.07:50:12.63#ibcon#cleared, iclass 22 cls_cnt 0 2006.196.07:50:12.63$vc4f8/vabw=wide 2006.196.07:50:12.63#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.196.07:50:12.63#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.196.07:50:12.63#ibcon#ireg 8 cls_cnt 0 2006.196.07:50:12.63#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.196.07:50:12.63#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.196.07:50:12.63#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.196.07:50:12.63#ibcon#enter wrdev, iclass 24, count 0 2006.196.07:50:12.63#ibcon#first serial, iclass 24, count 0 2006.196.07:50:12.63#ibcon#enter sib2, iclass 24, count 0 2006.196.07:50:12.63#ibcon#flushed, iclass 24, count 0 2006.196.07:50:12.63#ibcon#about to write, iclass 24, count 0 2006.196.07:50:12.63#ibcon#wrote, iclass 24, count 0 2006.196.07:50:12.63#ibcon#about to read 3, iclass 24, count 0 2006.196.07:50:12.65#ibcon#read 3, iclass 24, count 0 2006.196.07:50:12.65#ibcon#about to read 4, iclass 24, count 0 2006.196.07:50:12.65#ibcon#read 4, iclass 24, count 0 2006.196.07:50:12.65#ibcon#about to read 5, iclass 24, count 0 2006.196.07:50:12.65#ibcon#read 5, iclass 24, count 0 2006.196.07:50:12.65#ibcon#about to read 6, iclass 24, count 0 2006.196.07:50:12.65#ibcon#read 6, iclass 24, count 0 2006.196.07:50:12.65#ibcon#end of sib2, iclass 24, count 0 2006.196.07:50:12.65#ibcon#*mode == 0, iclass 24, count 0 2006.196.07:50:12.65#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.196.07:50:12.65#ibcon#[25=BW32\r\n] 2006.196.07:50:12.65#ibcon#*before write, iclass 24, count 0 2006.196.07:50:12.65#ibcon#enter sib2, iclass 24, count 0 2006.196.07:50:12.65#ibcon#flushed, iclass 24, count 0 2006.196.07:50:12.65#ibcon#about to write, iclass 24, count 0 2006.196.07:50:12.65#ibcon#wrote, iclass 24, count 0 2006.196.07:50:12.65#ibcon#about to read 3, iclass 24, count 0 2006.196.07:50:12.69#ibcon#read 3, iclass 24, count 0 2006.196.07:50:12.69#ibcon#about to read 4, iclass 24, count 0 2006.196.07:50:12.69#ibcon#read 4, iclass 24, count 0 2006.196.07:50:12.69#ibcon#about to read 5, iclass 24, count 0 2006.196.07:50:12.69#ibcon#read 5, iclass 24, count 0 2006.196.07:50:12.69#ibcon#about to read 6, iclass 24, count 0 2006.196.07:50:12.69#ibcon#read 6, iclass 24, count 0 2006.196.07:50:12.69#ibcon#end of sib2, iclass 24, count 0 2006.196.07:50:12.69#ibcon#*after write, iclass 24, count 0 2006.196.07:50:12.69#ibcon#*before return 0, iclass 24, count 0 2006.196.07:50:12.69#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.196.07:50:12.69#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.196.07:50:12.69#ibcon#about to clear, iclass 24 cls_cnt 0 2006.196.07:50:12.69#ibcon#cleared, iclass 24 cls_cnt 0 2006.196.07:50:12.69$vc4f8/vbbw=wide 2006.196.07:50:12.69#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.196.07:50:12.69#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.196.07:50:12.69#ibcon#ireg 8 cls_cnt 0 2006.196.07:50:12.69#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.196.07:50:12.75#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.196.07:50:12.75#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.196.07:50:12.75#ibcon#enter wrdev, iclass 26, count 0 2006.196.07:50:12.75#ibcon#first serial, iclass 26, count 0 2006.196.07:50:12.75#ibcon#enter sib2, iclass 26, count 0 2006.196.07:50:12.75#ibcon#flushed, iclass 26, count 0 2006.196.07:50:12.75#ibcon#about to write, iclass 26, count 0 2006.196.07:50:12.75#ibcon#wrote, iclass 26, count 0 2006.196.07:50:12.75#ibcon#about to read 3, iclass 26, count 0 2006.196.07:50:12.77#ibcon#read 3, iclass 26, count 0 2006.196.07:50:12.77#ibcon#about to read 4, iclass 26, count 0 2006.196.07:50:12.77#ibcon#read 4, iclass 26, count 0 2006.196.07:50:12.77#ibcon#about to read 5, iclass 26, count 0 2006.196.07:50:12.77#ibcon#read 5, iclass 26, count 0 2006.196.07:50:12.77#ibcon#about to read 6, iclass 26, count 0 2006.196.07:50:12.77#ibcon#read 6, iclass 26, count 0 2006.196.07:50:12.77#ibcon#end of sib2, iclass 26, count 0 2006.196.07:50:12.77#ibcon#*mode == 0, iclass 26, count 0 2006.196.07:50:12.77#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.196.07:50:12.77#ibcon#[27=BW32\r\n] 2006.196.07:50:12.77#ibcon#*before write, iclass 26, count 0 2006.196.07:50:12.77#ibcon#enter sib2, iclass 26, count 0 2006.196.07:50:12.77#ibcon#flushed, iclass 26, count 0 2006.196.07:50:12.77#ibcon#about to write, iclass 26, count 0 2006.196.07:50:12.77#ibcon#wrote, iclass 26, count 0 2006.196.07:50:12.77#ibcon#about to read 3, iclass 26, count 0 2006.196.07:50:12.80#ibcon#read 3, iclass 26, count 0 2006.196.07:50:12.80#ibcon#about to read 4, iclass 26, count 0 2006.196.07:50:12.80#ibcon#read 4, iclass 26, count 0 2006.196.07:50:12.80#ibcon#about to read 5, iclass 26, count 0 2006.196.07:50:12.80#ibcon#read 5, iclass 26, count 0 2006.196.07:50:12.80#ibcon#about to read 6, iclass 26, count 0 2006.196.07:50:12.80#ibcon#read 6, iclass 26, count 0 2006.196.07:50:12.80#ibcon#end of sib2, iclass 26, count 0 2006.196.07:50:12.80#ibcon#*after write, iclass 26, count 0 2006.196.07:50:12.80#ibcon#*before return 0, iclass 26, count 0 2006.196.07:50:12.80#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.196.07:50:12.80#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.196.07:50:12.80#ibcon#about to clear, iclass 26 cls_cnt 0 2006.196.07:50:12.80#ibcon#cleared, iclass 26 cls_cnt 0 2006.196.07:50:12.80$4f8m12a/ifd4f 2006.196.07:50:12.80$ifd4f/lo= 2006.196.07:50:12.80$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.196.07:50:12.80$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.196.07:50:12.80$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.196.07:50:12.80$ifd4f/patch= 2006.196.07:50:12.80$ifd4f/patch=lo1,a1,a2,a3,a4 2006.196.07:50:12.80$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.196.07:50:12.80$ifd4f/patch=lo3,a5,a6,a7,a8 2006.196.07:50:12.80$4f8m12a/"form=m,16.000,1:2 2006.196.07:50:12.80$4f8m12a/"tpicd 2006.196.07:50:12.80$4f8m12a/echo=off 2006.196.07:50:12.80$4f8m12a/xlog=off 2006.196.07:50:12.80:!2006.196.07:50:40 2006.196.07:50:24.13#trakl#Source acquired 2006.196.07:50:25.13#flagr#flagr/antenna,acquired 2006.196.07:50:40.00:preob 2006.196.07:50:41.13/onsource/TRACKING 2006.196.07:50:41.13:!2006.196.07:50:50 2006.196.07:50:50.00:data_valid=on 2006.196.07:50:50.00:midob 2006.196.07:50:50.13/onsource/TRACKING 2006.196.07:50:50.13/wx/29.68,1004.0,89 2006.196.07:50:50.22/cable/+6.3366E-03 2006.196.07:50:51.31/va/01,08,usb,yes,28,30 2006.196.07:50:51.31/va/02,07,usb,yes,28,30 2006.196.07:50:51.31/va/03,06,usb,yes,30,30 2006.196.07:50:51.31/va/04,07,usb,yes,29,31 2006.196.07:50:51.31/va/05,07,usb,yes,31,32 2006.196.07:50:51.31/va/06,06,usb,yes,30,30 2006.196.07:50:51.31/va/07,06,usb,yes,30,30 2006.196.07:50:51.31/va/08,07,usb,yes,29,28 2006.196.07:50:51.54/valo/01,532.99,yes,locked 2006.196.07:50:51.54/valo/02,572.99,yes,locked 2006.196.07:50:51.54/valo/03,672.99,yes,locked 2006.196.07:50:51.54/valo/04,832.99,yes,locked 2006.196.07:50:51.54/valo/05,652.99,yes,locked 2006.196.07:50:51.54/valo/06,772.99,yes,locked 2006.196.07:50:51.54/valo/07,832.99,yes,locked 2006.196.07:50:51.54/valo/08,852.99,yes,locked 2006.196.07:50:52.63/vb/01,04,usb,yes,28,27 2006.196.07:50:52.63/vb/02,04,usb,yes,30,31 2006.196.07:50:52.63/vb/03,04,usb,yes,26,30 2006.196.07:50:52.63/vb/04,04,usb,yes,27,27 2006.196.07:50:52.63/vb/05,04,usb,yes,26,30 2006.196.07:50:52.63/vb/06,04,usb,yes,27,29 2006.196.07:50:52.63/vb/07,04,usb,yes,29,29 2006.196.07:50:52.63/vb/08,04,usb,yes,26,30 2006.196.07:50:52.87/vblo/01,632.99,yes,locked 2006.196.07:50:52.87/vblo/02,640.99,yes,locked 2006.196.07:50:52.87/vblo/03,656.99,yes,locked 2006.196.07:50:52.87/vblo/04,712.99,yes,locked 2006.196.07:50:52.87/vblo/05,744.99,yes,locked 2006.196.07:50:52.87/vblo/06,752.99,yes,locked 2006.196.07:50:52.87/vblo/07,734.99,yes,locked 2006.196.07:50:52.87/vblo/08,744.99,yes,locked 2006.196.07:50:53.02/vabw/8 2006.196.07:50:53.17/vbbw/8 2006.196.07:50:53.26/xfe/off,on,15.0 2006.196.07:50:53.63/ifatt/23,28,28,28 2006.196.07:50:54.07/fmout-gps/S +3.34E-07 2006.196.07:50:54.14:!2006.196.07:51:50 2006.196.07:51:50.00:data_valid=off 2006.196.07:51:50.00:postob 2006.196.07:51:50.14/cable/+6.3342E-03 2006.196.07:51:50.14/wx/29.66,1004.0,89 2006.196.07:51:51.07/fmout-gps/S +3.35E-07 2006.196.07:51:51.07:scan_name=196-0752,k06196,60 2006.196.07:51:51.07:source=oj287,085448.87,200630.6,2000.0,cw 2006.196.07:51:51.14#flagr#flagr/antenna,new-source 2006.196.07:51:52.14:checkk5 2006.196.07:51:52.51/chk_autoobs//k5ts1/ autoobs is running! 2006.196.07:51:52.88/chk_autoobs//k5ts2/ autoobs is running! 2006.196.07:51:53.25/chk_autoobs//k5ts3/ autoobs is running! 2006.196.07:51:53.63/chk_autoobs//k5ts4/ autoobs is running! 2006.196.07:51:54.00/chk_obsdata//k5ts1/T1960750??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.196.07:51:54.37/chk_obsdata//k5ts2/T1960750??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.196.07:51:54.74/chk_obsdata//k5ts3/T1960750??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.196.07:51:55.10/chk_obsdata//k5ts4/T1960750??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.196.07:51:55.79/k5log//k5ts1_log_newline 2006.196.07:51:56.47/k5log//k5ts2_log_newline 2006.196.07:51:57.17/k5log//k5ts3_log_newline 2006.196.07:51:57.85/k5log//k5ts4_log_newline 2006.196.07:51:57.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.196.07:51:57.88:4f8m12a=1 2006.196.07:51:57.88$4f8m12a/echo=on 2006.196.07:51:57.88$4f8m12a/pcalon 2006.196.07:51:57.88$pcalon/"no phase cal control is implemented here 2006.196.07:51:57.88$4f8m12a/"tpicd=stop 2006.196.07:51:57.88$4f8m12a/vc4f8 2006.196.07:51:57.88$vc4f8/valo=1,532.99 2006.196.07:51:57.88#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.196.07:51:57.88#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.196.07:51:57.88#ibcon#ireg 17 cls_cnt 0 2006.196.07:51:57.88#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.196.07:51:57.88#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.196.07:51:57.88#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.196.07:51:57.88#ibcon#enter wrdev, iclass 37, count 0 2006.196.07:51:57.88#ibcon#first serial, iclass 37, count 0 2006.196.07:51:57.88#ibcon#enter sib2, iclass 37, count 0 2006.196.07:51:57.88#ibcon#flushed, iclass 37, count 0 2006.196.07:51:57.88#ibcon#about to write, iclass 37, count 0 2006.196.07:51:57.88#ibcon#wrote, iclass 37, count 0 2006.196.07:51:57.88#ibcon#about to read 3, iclass 37, count 0 2006.196.07:51:57.92#ibcon#read 3, iclass 37, count 0 2006.196.07:51:57.92#ibcon#about to read 4, iclass 37, count 0 2006.196.07:51:57.92#ibcon#read 4, iclass 37, count 0 2006.196.07:51:57.92#ibcon#about to read 5, iclass 37, count 0 2006.196.07:51:57.92#ibcon#read 5, iclass 37, count 0 2006.196.07:51:57.92#ibcon#about to read 6, iclass 37, count 0 2006.196.07:51:57.92#ibcon#read 6, iclass 37, count 0 2006.196.07:51:57.92#ibcon#end of sib2, iclass 37, count 0 2006.196.07:51:57.92#ibcon#*mode == 0, iclass 37, count 0 2006.196.07:51:57.92#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.196.07:51:57.92#ibcon#[26=FRQ=01,532.99\r\n] 2006.196.07:51:57.92#ibcon#*before write, iclass 37, count 0 2006.196.07:51:57.92#ibcon#enter sib2, iclass 37, count 0 2006.196.07:51:57.92#ibcon#flushed, iclass 37, count 0 2006.196.07:51:57.92#ibcon#about to write, iclass 37, count 0 2006.196.07:51:57.92#ibcon#wrote, iclass 37, count 0 2006.196.07:51:57.92#ibcon#about to read 3, iclass 37, count 0 2006.196.07:51:57.97#ibcon#read 3, iclass 37, count 0 2006.196.07:51:57.97#ibcon#about to read 4, iclass 37, count 0 2006.196.07:51:57.97#ibcon#read 4, iclass 37, count 0 2006.196.07:51:57.97#ibcon#about to read 5, iclass 37, count 0 2006.196.07:51:57.97#ibcon#read 5, iclass 37, count 0 2006.196.07:51:57.97#ibcon#about to read 6, iclass 37, count 0 2006.196.07:51:57.97#ibcon#read 6, iclass 37, count 0 2006.196.07:51:57.97#ibcon#end of sib2, iclass 37, count 0 2006.196.07:51:57.97#ibcon#*after write, iclass 37, count 0 2006.196.07:51:57.97#ibcon#*before return 0, iclass 37, count 0 2006.196.07:51:57.97#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.196.07:51:57.97#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.196.07:51:57.97#ibcon#about to clear, iclass 37 cls_cnt 0 2006.196.07:51:57.97#ibcon#cleared, iclass 37 cls_cnt 0 2006.196.07:51:57.97$vc4f8/va=1,8 2006.196.07:51:57.97#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.196.07:51:57.97#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.196.07:51:57.97#ibcon#ireg 11 cls_cnt 2 2006.196.07:51:57.97#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.196.07:51:57.97#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.196.07:51:57.97#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.196.07:51:57.97#ibcon#enter wrdev, iclass 39, count 2 2006.196.07:51:57.97#ibcon#first serial, iclass 39, count 2 2006.196.07:51:57.97#ibcon#enter sib2, iclass 39, count 2 2006.196.07:51:57.97#ibcon#flushed, iclass 39, count 2 2006.196.07:51:57.97#ibcon#about to write, iclass 39, count 2 2006.196.07:51:57.97#ibcon#wrote, iclass 39, count 2 2006.196.07:51:57.97#ibcon#about to read 3, iclass 39, count 2 2006.196.07:51:57.99#ibcon#read 3, iclass 39, count 2 2006.196.07:51:57.99#ibcon#about to read 4, iclass 39, count 2 2006.196.07:51:57.99#ibcon#read 4, iclass 39, count 2 2006.196.07:51:57.99#ibcon#about to read 5, iclass 39, count 2 2006.196.07:51:57.99#ibcon#read 5, iclass 39, count 2 2006.196.07:51:57.99#ibcon#about to read 6, iclass 39, count 2 2006.196.07:51:57.99#ibcon#read 6, iclass 39, count 2 2006.196.07:51:57.99#ibcon#end of sib2, iclass 39, count 2 2006.196.07:51:57.99#ibcon#*mode == 0, iclass 39, count 2 2006.196.07:51:57.99#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.196.07:51:57.99#ibcon#[25=AT01-08\r\n] 2006.196.07:51:57.99#ibcon#*before write, iclass 39, count 2 2006.196.07:51:57.99#ibcon#enter sib2, iclass 39, count 2 2006.196.07:51:57.99#ibcon#flushed, iclass 39, count 2 2006.196.07:51:57.99#ibcon#about to write, iclass 39, count 2 2006.196.07:51:57.99#ibcon#wrote, iclass 39, count 2 2006.196.07:51:57.99#ibcon#about to read 3, iclass 39, count 2 2006.196.07:51:58.02#ibcon#read 3, iclass 39, count 2 2006.196.07:51:58.02#ibcon#about to read 4, iclass 39, count 2 2006.196.07:51:58.02#ibcon#read 4, iclass 39, count 2 2006.196.07:51:58.02#ibcon#about to read 5, iclass 39, count 2 2006.196.07:51:58.02#ibcon#read 5, iclass 39, count 2 2006.196.07:51:58.02#ibcon#about to read 6, iclass 39, count 2 2006.196.07:51:58.02#ibcon#read 6, iclass 39, count 2 2006.196.07:51:58.02#ibcon#end of sib2, iclass 39, count 2 2006.196.07:51:58.02#ibcon#*after write, iclass 39, count 2 2006.196.07:51:58.02#ibcon#*before return 0, iclass 39, count 2 2006.196.07:51:58.02#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.196.07:51:58.02#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.196.07:51:58.02#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.196.07:51:58.02#ibcon#ireg 7 cls_cnt 0 2006.196.07:51:58.02#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.196.07:51:58.14#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.196.07:51:58.14#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.196.07:51:58.14#ibcon#enter wrdev, iclass 39, count 0 2006.196.07:51:58.14#ibcon#first serial, iclass 39, count 0 2006.196.07:51:58.14#ibcon#enter sib2, iclass 39, count 0 2006.196.07:51:58.14#ibcon#flushed, iclass 39, count 0 2006.196.07:51:58.14#ibcon#about to write, iclass 39, count 0 2006.196.07:51:58.14#ibcon#wrote, iclass 39, count 0 2006.196.07:51:58.14#ibcon#about to read 3, iclass 39, count 0 2006.196.07:51:58.16#ibcon#read 3, iclass 39, count 0 2006.196.07:51:58.16#ibcon#about to read 4, iclass 39, count 0 2006.196.07:51:58.16#ibcon#read 4, iclass 39, count 0 2006.196.07:51:58.16#ibcon#about to read 5, iclass 39, count 0 2006.196.07:51:58.16#ibcon#read 5, iclass 39, count 0 2006.196.07:51:58.16#ibcon#about to read 6, iclass 39, count 0 2006.196.07:51:58.16#ibcon#read 6, iclass 39, count 0 2006.196.07:51:58.16#ibcon#end of sib2, iclass 39, count 0 2006.196.07:51:58.16#ibcon#*mode == 0, iclass 39, count 0 2006.196.07:51:58.16#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.196.07:51:58.16#ibcon#[25=USB\r\n] 2006.196.07:51:58.16#ibcon#*before write, iclass 39, count 0 2006.196.07:51:58.16#ibcon#enter sib2, iclass 39, count 0 2006.196.07:51:58.16#ibcon#flushed, iclass 39, count 0 2006.196.07:51:58.16#ibcon#about to write, iclass 39, count 0 2006.196.07:51:58.16#ibcon#wrote, iclass 39, count 0 2006.196.07:51:58.16#ibcon#about to read 3, iclass 39, count 0 2006.196.07:51:58.19#ibcon#read 3, iclass 39, count 0 2006.196.07:51:58.19#ibcon#about to read 4, iclass 39, count 0 2006.196.07:51:58.19#ibcon#read 4, iclass 39, count 0 2006.196.07:51:58.19#ibcon#about to read 5, iclass 39, count 0 2006.196.07:51:58.19#ibcon#read 5, iclass 39, count 0 2006.196.07:51:58.19#ibcon#about to read 6, iclass 39, count 0 2006.196.07:51:58.19#ibcon#read 6, iclass 39, count 0 2006.196.07:51:58.19#ibcon#end of sib2, iclass 39, count 0 2006.196.07:51:58.19#ibcon#*after write, iclass 39, count 0 2006.196.07:51:58.19#ibcon#*before return 0, iclass 39, count 0 2006.196.07:51:58.19#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.196.07:51:58.19#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.196.07:51:58.19#ibcon#about to clear, iclass 39 cls_cnt 0 2006.196.07:51:58.19#ibcon#cleared, iclass 39 cls_cnt 0 2006.196.07:51:58.19$vc4f8/valo=2,572.99 2006.196.07:51:58.19#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.196.07:51:58.19#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.196.07:51:58.19#ibcon#ireg 17 cls_cnt 0 2006.196.07:51:58.19#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.196.07:51:58.19#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.196.07:51:58.19#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.196.07:51:58.19#ibcon#enter wrdev, iclass 3, count 0 2006.196.07:51:58.19#ibcon#first serial, iclass 3, count 0 2006.196.07:51:58.19#ibcon#enter sib2, iclass 3, count 0 2006.196.07:51:58.19#ibcon#flushed, iclass 3, count 0 2006.196.07:51:58.19#ibcon#about to write, iclass 3, count 0 2006.196.07:51:58.19#ibcon#wrote, iclass 3, count 0 2006.196.07:51:58.19#ibcon#about to read 3, iclass 3, count 0 2006.196.07:51:58.21#ibcon#read 3, iclass 3, count 0 2006.196.07:51:58.21#ibcon#about to read 4, iclass 3, count 0 2006.196.07:51:58.21#ibcon#read 4, iclass 3, count 0 2006.196.07:51:58.21#ibcon#about to read 5, iclass 3, count 0 2006.196.07:51:58.21#ibcon#read 5, iclass 3, count 0 2006.196.07:51:58.21#ibcon#about to read 6, iclass 3, count 0 2006.196.07:51:58.21#ibcon#read 6, iclass 3, count 0 2006.196.07:51:58.21#ibcon#end of sib2, iclass 3, count 0 2006.196.07:51:58.21#ibcon#*mode == 0, iclass 3, count 0 2006.196.07:51:58.21#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.196.07:51:58.21#ibcon#[26=FRQ=02,572.99\r\n] 2006.196.07:51:58.21#ibcon#*before write, iclass 3, count 0 2006.196.07:51:58.21#ibcon#enter sib2, iclass 3, count 0 2006.196.07:51:58.21#ibcon#flushed, iclass 3, count 0 2006.196.07:51:58.21#ibcon#about to write, iclass 3, count 0 2006.196.07:51:58.21#ibcon#wrote, iclass 3, count 0 2006.196.07:51:58.21#ibcon#about to read 3, iclass 3, count 0 2006.196.07:51:58.26#ibcon#read 3, iclass 3, count 0 2006.196.07:51:58.26#ibcon#about to read 4, iclass 3, count 0 2006.196.07:51:58.26#ibcon#read 4, iclass 3, count 0 2006.196.07:51:58.26#ibcon#about to read 5, iclass 3, count 0 2006.196.07:51:58.26#ibcon#read 5, iclass 3, count 0 2006.196.07:51:58.26#ibcon#about to read 6, iclass 3, count 0 2006.196.07:51:58.26#ibcon#read 6, iclass 3, count 0 2006.196.07:51:58.26#ibcon#end of sib2, iclass 3, count 0 2006.196.07:51:58.26#ibcon#*after write, iclass 3, count 0 2006.196.07:51:58.26#ibcon#*before return 0, iclass 3, count 0 2006.196.07:51:58.26#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.196.07:51:58.26#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.196.07:51:58.26#ibcon#about to clear, iclass 3 cls_cnt 0 2006.196.07:51:58.26#ibcon#cleared, iclass 3 cls_cnt 0 2006.196.07:51:58.26$vc4f8/va=2,7 2006.196.07:51:58.26#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.196.07:51:58.26#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.196.07:51:58.26#ibcon#ireg 11 cls_cnt 2 2006.196.07:51:58.26#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.196.07:51:58.31#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.196.07:51:58.31#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.196.07:51:58.31#ibcon#enter wrdev, iclass 5, count 2 2006.196.07:51:58.31#ibcon#first serial, iclass 5, count 2 2006.196.07:51:58.31#ibcon#enter sib2, iclass 5, count 2 2006.196.07:51:58.31#ibcon#flushed, iclass 5, count 2 2006.196.07:51:58.31#ibcon#about to write, iclass 5, count 2 2006.196.07:51:58.31#ibcon#wrote, iclass 5, count 2 2006.196.07:51:58.31#ibcon#about to read 3, iclass 5, count 2 2006.196.07:51:58.33#ibcon#read 3, iclass 5, count 2 2006.196.07:51:58.33#ibcon#about to read 4, iclass 5, count 2 2006.196.07:51:58.33#ibcon#read 4, iclass 5, count 2 2006.196.07:51:58.33#ibcon#about to read 5, iclass 5, count 2 2006.196.07:51:58.33#ibcon#read 5, iclass 5, count 2 2006.196.07:51:58.33#ibcon#about to read 6, iclass 5, count 2 2006.196.07:51:58.33#ibcon#read 6, iclass 5, count 2 2006.196.07:51:58.33#ibcon#end of sib2, iclass 5, count 2 2006.196.07:51:58.33#ibcon#*mode == 0, iclass 5, count 2 2006.196.07:51:58.33#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.196.07:51:58.33#ibcon#[25=AT02-07\r\n] 2006.196.07:51:58.33#ibcon#*before write, iclass 5, count 2 2006.196.07:51:58.33#ibcon#enter sib2, iclass 5, count 2 2006.196.07:51:58.33#ibcon#flushed, iclass 5, count 2 2006.196.07:51:58.33#ibcon#about to write, iclass 5, count 2 2006.196.07:51:58.33#ibcon#wrote, iclass 5, count 2 2006.196.07:51:58.33#ibcon#about to read 3, iclass 5, count 2 2006.196.07:51:58.36#ibcon#read 3, iclass 5, count 2 2006.196.07:51:58.36#ibcon#about to read 4, iclass 5, count 2 2006.196.07:51:58.36#ibcon#read 4, iclass 5, count 2 2006.196.07:51:58.36#ibcon#about to read 5, iclass 5, count 2 2006.196.07:51:58.36#ibcon#read 5, iclass 5, count 2 2006.196.07:51:58.36#ibcon#about to read 6, iclass 5, count 2 2006.196.07:51:58.36#ibcon#read 6, iclass 5, count 2 2006.196.07:51:58.36#ibcon#end of sib2, iclass 5, count 2 2006.196.07:51:58.36#ibcon#*after write, iclass 5, count 2 2006.196.07:51:58.36#ibcon#*before return 0, iclass 5, count 2 2006.196.07:51:58.36#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.196.07:51:58.36#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.196.07:51:58.36#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.196.07:51:58.36#ibcon#ireg 7 cls_cnt 0 2006.196.07:51:58.36#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.196.07:51:58.48#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.196.07:51:58.48#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.196.07:51:58.48#ibcon#enter wrdev, iclass 5, count 0 2006.196.07:51:58.48#ibcon#first serial, iclass 5, count 0 2006.196.07:51:58.48#ibcon#enter sib2, iclass 5, count 0 2006.196.07:51:58.48#ibcon#flushed, iclass 5, count 0 2006.196.07:51:58.48#ibcon#about to write, iclass 5, count 0 2006.196.07:51:58.48#ibcon#wrote, iclass 5, count 0 2006.196.07:51:58.48#ibcon#about to read 3, iclass 5, count 0 2006.196.07:51:58.50#ibcon#read 3, iclass 5, count 0 2006.196.07:51:58.50#ibcon#about to read 4, iclass 5, count 0 2006.196.07:51:58.50#ibcon#read 4, iclass 5, count 0 2006.196.07:51:58.50#ibcon#about to read 5, iclass 5, count 0 2006.196.07:51:58.50#ibcon#read 5, iclass 5, count 0 2006.196.07:51:58.50#ibcon#about to read 6, iclass 5, count 0 2006.196.07:51:58.50#ibcon#read 6, iclass 5, count 0 2006.196.07:51:58.50#ibcon#end of sib2, iclass 5, count 0 2006.196.07:51:58.50#ibcon#*mode == 0, iclass 5, count 0 2006.196.07:51:58.50#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.196.07:51:58.50#ibcon#[25=USB\r\n] 2006.196.07:51:58.50#ibcon#*before write, iclass 5, count 0 2006.196.07:51:58.50#ibcon#enter sib2, iclass 5, count 0 2006.196.07:51:58.50#ibcon#flushed, iclass 5, count 0 2006.196.07:51:58.50#ibcon#about to write, iclass 5, count 0 2006.196.07:51:58.50#ibcon#wrote, iclass 5, count 0 2006.196.07:51:58.50#ibcon#about to read 3, iclass 5, count 0 2006.196.07:51:58.53#ibcon#read 3, iclass 5, count 0 2006.196.07:51:58.53#ibcon#about to read 4, iclass 5, count 0 2006.196.07:51:58.53#ibcon#read 4, iclass 5, count 0 2006.196.07:51:58.53#ibcon#about to read 5, iclass 5, count 0 2006.196.07:51:58.53#ibcon#read 5, iclass 5, count 0 2006.196.07:51:58.53#ibcon#about to read 6, iclass 5, count 0 2006.196.07:51:58.53#ibcon#read 6, iclass 5, count 0 2006.196.07:51:58.53#ibcon#end of sib2, iclass 5, count 0 2006.196.07:51:58.53#ibcon#*after write, iclass 5, count 0 2006.196.07:51:58.53#ibcon#*before return 0, iclass 5, count 0 2006.196.07:51:58.53#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.196.07:51:58.53#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.196.07:51:58.53#ibcon#about to clear, iclass 5 cls_cnt 0 2006.196.07:51:58.53#ibcon#cleared, iclass 5 cls_cnt 0 2006.196.07:51:58.53$vc4f8/valo=3,672.99 2006.196.07:51:58.53#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.196.07:51:58.53#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.196.07:51:58.53#ibcon#ireg 17 cls_cnt 0 2006.196.07:51:58.53#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.196.07:51:58.53#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.196.07:51:58.53#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.196.07:51:58.53#ibcon#enter wrdev, iclass 7, count 0 2006.196.07:51:58.53#ibcon#first serial, iclass 7, count 0 2006.196.07:51:58.53#ibcon#enter sib2, iclass 7, count 0 2006.196.07:51:58.53#ibcon#flushed, iclass 7, count 0 2006.196.07:51:58.53#ibcon#about to write, iclass 7, count 0 2006.196.07:51:58.53#ibcon#wrote, iclass 7, count 0 2006.196.07:51:58.53#ibcon#about to read 3, iclass 7, count 0 2006.196.07:51:58.55#ibcon#read 3, iclass 7, count 0 2006.196.07:51:58.55#ibcon#about to read 4, iclass 7, count 0 2006.196.07:51:58.55#ibcon#read 4, iclass 7, count 0 2006.196.07:51:58.55#ibcon#about to read 5, iclass 7, count 0 2006.196.07:51:58.55#ibcon#read 5, iclass 7, count 0 2006.196.07:51:58.55#ibcon#about to read 6, iclass 7, count 0 2006.196.07:51:58.55#ibcon#read 6, iclass 7, count 0 2006.196.07:51:58.55#ibcon#end of sib2, iclass 7, count 0 2006.196.07:51:58.55#ibcon#*mode == 0, iclass 7, count 0 2006.196.07:51:58.55#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.196.07:51:58.55#ibcon#[26=FRQ=03,672.99\r\n] 2006.196.07:51:58.55#ibcon#*before write, iclass 7, count 0 2006.196.07:51:58.55#ibcon#enter sib2, iclass 7, count 0 2006.196.07:51:58.55#ibcon#flushed, iclass 7, count 0 2006.196.07:51:58.55#ibcon#about to write, iclass 7, count 0 2006.196.07:51:58.55#ibcon#wrote, iclass 7, count 0 2006.196.07:51:58.55#ibcon#about to read 3, iclass 7, count 0 2006.196.07:51:58.60#ibcon#read 3, iclass 7, count 0 2006.196.07:51:58.60#ibcon#about to read 4, iclass 7, count 0 2006.196.07:51:58.60#ibcon#read 4, iclass 7, count 0 2006.196.07:51:58.60#ibcon#about to read 5, iclass 7, count 0 2006.196.07:51:58.60#ibcon#read 5, iclass 7, count 0 2006.196.07:51:58.60#ibcon#about to read 6, iclass 7, count 0 2006.196.07:51:58.60#ibcon#read 6, iclass 7, count 0 2006.196.07:51:58.60#ibcon#end of sib2, iclass 7, count 0 2006.196.07:51:58.60#ibcon#*after write, iclass 7, count 0 2006.196.07:51:58.60#ibcon#*before return 0, iclass 7, count 0 2006.196.07:51:58.60#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.196.07:51:58.60#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.196.07:51:58.60#ibcon#about to clear, iclass 7 cls_cnt 0 2006.196.07:51:58.60#ibcon#cleared, iclass 7 cls_cnt 0 2006.196.07:51:58.60$vc4f8/va=3,6 2006.196.07:51:58.60#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.196.07:51:58.60#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.196.07:51:58.60#ibcon#ireg 11 cls_cnt 2 2006.196.07:51:58.60#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.196.07:51:58.65#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.196.07:51:58.65#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.196.07:51:58.65#ibcon#enter wrdev, iclass 11, count 2 2006.196.07:51:58.65#ibcon#first serial, iclass 11, count 2 2006.196.07:51:58.65#ibcon#enter sib2, iclass 11, count 2 2006.196.07:51:58.65#ibcon#flushed, iclass 11, count 2 2006.196.07:51:58.65#ibcon#about to write, iclass 11, count 2 2006.196.07:51:58.65#ibcon#wrote, iclass 11, count 2 2006.196.07:51:58.65#ibcon#about to read 3, iclass 11, count 2 2006.196.07:51:58.67#ibcon#read 3, iclass 11, count 2 2006.196.07:51:58.67#ibcon#about to read 4, iclass 11, count 2 2006.196.07:51:58.67#ibcon#read 4, iclass 11, count 2 2006.196.07:51:58.67#ibcon#about to read 5, iclass 11, count 2 2006.196.07:51:58.67#ibcon#read 5, iclass 11, count 2 2006.196.07:51:58.67#ibcon#about to read 6, iclass 11, count 2 2006.196.07:51:58.67#ibcon#read 6, iclass 11, count 2 2006.196.07:51:58.67#ibcon#end of sib2, iclass 11, count 2 2006.196.07:51:58.67#ibcon#*mode == 0, iclass 11, count 2 2006.196.07:51:58.67#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.196.07:51:58.67#ibcon#[25=AT03-06\r\n] 2006.196.07:51:58.67#ibcon#*before write, iclass 11, count 2 2006.196.07:51:58.67#ibcon#enter sib2, iclass 11, count 2 2006.196.07:51:58.67#ibcon#flushed, iclass 11, count 2 2006.196.07:51:58.67#ibcon#about to write, iclass 11, count 2 2006.196.07:51:58.67#ibcon#wrote, iclass 11, count 2 2006.196.07:51:58.67#ibcon#about to read 3, iclass 11, count 2 2006.196.07:51:58.70#ibcon#read 3, iclass 11, count 2 2006.196.07:51:58.70#ibcon#about to read 4, iclass 11, count 2 2006.196.07:51:58.70#ibcon#read 4, iclass 11, count 2 2006.196.07:51:58.70#ibcon#about to read 5, iclass 11, count 2 2006.196.07:51:58.70#ibcon#read 5, iclass 11, count 2 2006.196.07:51:58.70#ibcon#about to read 6, iclass 11, count 2 2006.196.07:51:58.70#ibcon#read 6, iclass 11, count 2 2006.196.07:51:58.70#ibcon#end of sib2, iclass 11, count 2 2006.196.07:51:58.70#ibcon#*after write, iclass 11, count 2 2006.196.07:51:58.70#ibcon#*before return 0, iclass 11, count 2 2006.196.07:51:58.70#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.196.07:51:58.70#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.196.07:51:58.70#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.196.07:51:58.70#ibcon#ireg 7 cls_cnt 0 2006.196.07:51:58.70#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.196.07:51:58.82#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.196.07:51:58.82#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.196.07:51:58.82#ibcon#enter wrdev, iclass 11, count 0 2006.196.07:51:58.82#ibcon#first serial, iclass 11, count 0 2006.196.07:51:58.82#ibcon#enter sib2, iclass 11, count 0 2006.196.07:51:58.82#ibcon#flushed, iclass 11, count 0 2006.196.07:51:58.82#ibcon#about to write, iclass 11, count 0 2006.196.07:51:58.82#ibcon#wrote, iclass 11, count 0 2006.196.07:51:58.82#ibcon#about to read 3, iclass 11, count 0 2006.196.07:51:58.84#ibcon#read 3, iclass 11, count 0 2006.196.07:51:58.84#ibcon#about to read 4, iclass 11, count 0 2006.196.07:51:58.84#ibcon#read 4, iclass 11, count 0 2006.196.07:51:58.84#ibcon#about to read 5, iclass 11, count 0 2006.196.07:51:58.84#ibcon#read 5, iclass 11, count 0 2006.196.07:51:58.84#ibcon#about to read 6, iclass 11, count 0 2006.196.07:51:58.84#ibcon#read 6, iclass 11, count 0 2006.196.07:51:58.84#ibcon#end of sib2, iclass 11, count 0 2006.196.07:51:58.84#ibcon#*mode == 0, iclass 11, count 0 2006.196.07:51:58.84#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.196.07:51:58.84#ibcon#[25=USB\r\n] 2006.196.07:51:58.84#ibcon#*before write, iclass 11, count 0 2006.196.07:51:58.84#ibcon#enter sib2, iclass 11, count 0 2006.196.07:51:58.84#ibcon#flushed, iclass 11, count 0 2006.196.07:51:58.84#ibcon#about to write, iclass 11, count 0 2006.196.07:51:58.84#ibcon#wrote, iclass 11, count 0 2006.196.07:51:58.84#ibcon#about to read 3, iclass 11, count 0 2006.196.07:51:58.87#ibcon#read 3, iclass 11, count 0 2006.196.07:51:58.87#ibcon#about to read 4, iclass 11, count 0 2006.196.07:51:58.87#ibcon#read 4, iclass 11, count 0 2006.196.07:51:58.87#ibcon#about to read 5, iclass 11, count 0 2006.196.07:51:58.87#ibcon#read 5, iclass 11, count 0 2006.196.07:51:58.87#ibcon#about to read 6, iclass 11, count 0 2006.196.07:51:58.87#ibcon#read 6, iclass 11, count 0 2006.196.07:51:58.87#ibcon#end of sib2, iclass 11, count 0 2006.196.07:51:58.87#ibcon#*after write, iclass 11, count 0 2006.196.07:51:58.87#ibcon#*before return 0, iclass 11, count 0 2006.196.07:51:58.87#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.196.07:51:58.87#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.196.07:51:58.87#ibcon#about to clear, iclass 11 cls_cnt 0 2006.196.07:51:58.87#ibcon#cleared, iclass 11 cls_cnt 0 2006.196.07:51:58.87$vc4f8/valo=4,832.99 2006.196.07:51:58.87#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.196.07:51:58.87#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.196.07:51:58.87#ibcon#ireg 17 cls_cnt 0 2006.196.07:51:58.87#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.196.07:51:58.87#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.196.07:51:58.87#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.196.07:51:58.87#ibcon#enter wrdev, iclass 13, count 0 2006.196.07:51:58.87#ibcon#first serial, iclass 13, count 0 2006.196.07:51:58.87#ibcon#enter sib2, iclass 13, count 0 2006.196.07:51:58.87#ibcon#flushed, iclass 13, count 0 2006.196.07:51:58.87#ibcon#about to write, iclass 13, count 0 2006.196.07:51:58.87#ibcon#wrote, iclass 13, count 0 2006.196.07:51:58.87#ibcon#about to read 3, iclass 13, count 0 2006.196.07:51:58.89#ibcon#read 3, iclass 13, count 0 2006.196.07:51:58.89#ibcon#about to read 4, iclass 13, count 0 2006.196.07:51:58.89#ibcon#read 4, iclass 13, count 0 2006.196.07:51:58.89#ibcon#about to read 5, iclass 13, count 0 2006.196.07:51:58.89#ibcon#read 5, iclass 13, count 0 2006.196.07:51:58.89#ibcon#about to read 6, iclass 13, count 0 2006.196.07:51:58.89#ibcon#read 6, iclass 13, count 0 2006.196.07:51:58.89#ibcon#end of sib2, iclass 13, count 0 2006.196.07:51:58.89#ibcon#*mode == 0, iclass 13, count 0 2006.196.07:51:58.89#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.196.07:51:58.89#ibcon#[26=FRQ=04,832.99\r\n] 2006.196.07:51:58.89#ibcon#*before write, iclass 13, count 0 2006.196.07:51:58.89#ibcon#enter sib2, iclass 13, count 0 2006.196.07:51:58.89#ibcon#flushed, iclass 13, count 0 2006.196.07:51:58.89#ibcon#about to write, iclass 13, count 0 2006.196.07:51:58.89#ibcon#wrote, iclass 13, count 0 2006.196.07:51:58.89#ibcon#about to read 3, iclass 13, count 0 2006.196.07:51:58.93#ibcon#read 3, iclass 13, count 0 2006.196.07:51:58.93#ibcon#about to read 4, iclass 13, count 0 2006.196.07:51:58.93#ibcon#read 4, iclass 13, count 0 2006.196.07:51:58.93#ibcon#about to read 5, iclass 13, count 0 2006.196.07:51:58.93#ibcon#read 5, iclass 13, count 0 2006.196.07:51:58.93#ibcon#about to read 6, iclass 13, count 0 2006.196.07:51:58.93#ibcon#read 6, iclass 13, count 0 2006.196.07:51:58.93#ibcon#end of sib2, iclass 13, count 0 2006.196.07:51:58.93#ibcon#*after write, iclass 13, count 0 2006.196.07:51:58.93#ibcon#*before return 0, iclass 13, count 0 2006.196.07:51:58.93#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.196.07:51:58.93#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.196.07:51:58.93#ibcon#about to clear, iclass 13 cls_cnt 0 2006.196.07:51:58.93#ibcon#cleared, iclass 13 cls_cnt 0 2006.196.07:51:58.93$vc4f8/va=4,7 2006.196.07:51:58.93#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.196.07:51:58.93#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.196.07:51:58.93#ibcon#ireg 11 cls_cnt 2 2006.196.07:51:58.93#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.196.07:51:58.99#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.196.07:51:58.99#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.196.07:51:58.99#ibcon#enter wrdev, iclass 15, count 2 2006.196.07:51:58.99#ibcon#first serial, iclass 15, count 2 2006.196.07:51:58.99#ibcon#enter sib2, iclass 15, count 2 2006.196.07:51:58.99#ibcon#flushed, iclass 15, count 2 2006.196.07:51:58.99#ibcon#about to write, iclass 15, count 2 2006.196.07:51:58.99#ibcon#wrote, iclass 15, count 2 2006.196.07:51:58.99#ibcon#about to read 3, iclass 15, count 2 2006.196.07:51:59.01#ibcon#read 3, iclass 15, count 2 2006.196.07:51:59.01#ibcon#about to read 4, iclass 15, count 2 2006.196.07:51:59.01#ibcon#read 4, iclass 15, count 2 2006.196.07:51:59.01#ibcon#about to read 5, iclass 15, count 2 2006.196.07:51:59.01#ibcon#read 5, iclass 15, count 2 2006.196.07:51:59.01#ibcon#about to read 6, iclass 15, count 2 2006.196.07:51:59.01#ibcon#read 6, iclass 15, count 2 2006.196.07:51:59.01#ibcon#end of sib2, iclass 15, count 2 2006.196.07:51:59.01#ibcon#*mode == 0, iclass 15, count 2 2006.196.07:51:59.01#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.196.07:51:59.01#ibcon#[25=AT04-07\r\n] 2006.196.07:51:59.01#ibcon#*before write, iclass 15, count 2 2006.196.07:51:59.01#ibcon#enter sib2, iclass 15, count 2 2006.196.07:51:59.01#ibcon#flushed, iclass 15, count 2 2006.196.07:51:59.01#ibcon#about to write, iclass 15, count 2 2006.196.07:51:59.01#ibcon#wrote, iclass 15, count 2 2006.196.07:51:59.01#ibcon#about to read 3, iclass 15, count 2 2006.196.07:51:59.04#ibcon#read 3, iclass 15, count 2 2006.196.07:51:59.04#ibcon#about to read 4, iclass 15, count 2 2006.196.07:51:59.04#ibcon#read 4, iclass 15, count 2 2006.196.07:51:59.04#ibcon#about to read 5, iclass 15, count 2 2006.196.07:51:59.04#ibcon#read 5, iclass 15, count 2 2006.196.07:51:59.04#ibcon#about to read 6, iclass 15, count 2 2006.196.07:51:59.04#ibcon#read 6, iclass 15, count 2 2006.196.07:51:59.04#ibcon#end of sib2, iclass 15, count 2 2006.196.07:51:59.04#ibcon#*after write, iclass 15, count 2 2006.196.07:51:59.04#ibcon#*before return 0, iclass 15, count 2 2006.196.07:51:59.04#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.196.07:51:59.04#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.196.07:51:59.04#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.196.07:51:59.04#ibcon#ireg 7 cls_cnt 0 2006.196.07:51:59.04#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.196.07:51:59.16#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.196.07:51:59.16#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.196.07:51:59.16#ibcon#enter wrdev, iclass 15, count 0 2006.196.07:51:59.16#ibcon#first serial, iclass 15, count 0 2006.196.07:51:59.16#ibcon#enter sib2, iclass 15, count 0 2006.196.07:51:59.16#ibcon#flushed, iclass 15, count 0 2006.196.07:51:59.16#ibcon#about to write, iclass 15, count 0 2006.196.07:51:59.16#ibcon#wrote, iclass 15, count 0 2006.196.07:51:59.16#ibcon#about to read 3, iclass 15, count 0 2006.196.07:51:59.18#ibcon#read 3, iclass 15, count 0 2006.196.07:51:59.18#ibcon#about to read 4, iclass 15, count 0 2006.196.07:51:59.18#ibcon#read 4, iclass 15, count 0 2006.196.07:51:59.18#ibcon#about to read 5, iclass 15, count 0 2006.196.07:51:59.18#ibcon#read 5, iclass 15, count 0 2006.196.07:51:59.18#ibcon#about to read 6, iclass 15, count 0 2006.196.07:51:59.18#ibcon#read 6, iclass 15, count 0 2006.196.07:51:59.18#ibcon#end of sib2, iclass 15, count 0 2006.196.07:51:59.18#ibcon#*mode == 0, iclass 15, count 0 2006.196.07:51:59.18#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.196.07:51:59.18#ibcon#[25=USB\r\n] 2006.196.07:51:59.18#ibcon#*before write, iclass 15, count 0 2006.196.07:51:59.18#ibcon#enter sib2, iclass 15, count 0 2006.196.07:51:59.18#ibcon#flushed, iclass 15, count 0 2006.196.07:51:59.18#ibcon#about to write, iclass 15, count 0 2006.196.07:51:59.18#ibcon#wrote, iclass 15, count 0 2006.196.07:51:59.18#ibcon#about to read 3, iclass 15, count 0 2006.196.07:51:59.21#ibcon#read 3, iclass 15, count 0 2006.196.07:51:59.21#ibcon#about to read 4, iclass 15, count 0 2006.196.07:51:59.21#ibcon#read 4, iclass 15, count 0 2006.196.07:51:59.21#ibcon#about to read 5, iclass 15, count 0 2006.196.07:51:59.21#ibcon#read 5, iclass 15, count 0 2006.196.07:51:59.21#ibcon#about to read 6, iclass 15, count 0 2006.196.07:51:59.21#ibcon#read 6, iclass 15, count 0 2006.196.07:51:59.21#ibcon#end of sib2, iclass 15, count 0 2006.196.07:51:59.21#ibcon#*after write, iclass 15, count 0 2006.196.07:51:59.21#ibcon#*before return 0, iclass 15, count 0 2006.196.07:51:59.21#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.196.07:51:59.21#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.196.07:51:59.21#ibcon#about to clear, iclass 15 cls_cnt 0 2006.196.07:51:59.21#ibcon#cleared, iclass 15 cls_cnt 0 2006.196.07:51:59.21$vc4f8/valo=5,652.99 2006.196.07:51:59.21#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.196.07:51:59.21#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.196.07:51:59.21#ibcon#ireg 17 cls_cnt 0 2006.196.07:51:59.21#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.196.07:51:59.21#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.196.07:51:59.21#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.196.07:51:59.21#ibcon#enter wrdev, iclass 17, count 0 2006.196.07:51:59.21#ibcon#first serial, iclass 17, count 0 2006.196.07:51:59.21#ibcon#enter sib2, iclass 17, count 0 2006.196.07:51:59.21#ibcon#flushed, iclass 17, count 0 2006.196.07:51:59.21#ibcon#about to write, iclass 17, count 0 2006.196.07:51:59.21#ibcon#wrote, iclass 17, count 0 2006.196.07:51:59.21#ibcon#about to read 3, iclass 17, count 0 2006.196.07:51:59.23#ibcon#read 3, iclass 17, count 0 2006.196.07:51:59.23#ibcon#about to read 4, iclass 17, count 0 2006.196.07:51:59.23#ibcon#read 4, iclass 17, count 0 2006.196.07:51:59.23#ibcon#about to read 5, iclass 17, count 0 2006.196.07:51:59.23#ibcon#read 5, iclass 17, count 0 2006.196.07:51:59.23#ibcon#about to read 6, iclass 17, count 0 2006.196.07:51:59.23#ibcon#read 6, iclass 17, count 0 2006.196.07:51:59.23#ibcon#end of sib2, iclass 17, count 0 2006.196.07:51:59.23#ibcon#*mode == 0, iclass 17, count 0 2006.196.07:51:59.23#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.196.07:51:59.23#ibcon#[26=FRQ=05,652.99\r\n] 2006.196.07:51:59.23#ibcon#*before write, iclass 17, count 0 2006.196.07:51:59.23#ibcon#enter sib2, iclass 17, count 0 2006.196.07:51:59.23#ibcon#flushed, iclass 17, count 0 2006.196.07:51:59.23#ibcon#about to write, iclass 17, count 0 2006.196.07:51:59.23#ibcon#wrote, iclass 17, count 0 2006.196.07:51:59.23#ibcon#about to read 3, iclass 17, count 0 2006.196.07:51:59.27#ibcon#read 3, iclass 17, count 0 2006.196.07:51:59.27#ibcon#about to read 4, iclass 17, count 0 2006.196.07:51:59.27#ibcon#read 4, iclass 17, count 0 2006.196.07:51:59.27#ibcon#about to read 5, iclass 17, count 0 2006.196.07:51:59.27#ibcon#read 5, iclass 17, count 0 2006.196.07:51:59.27#ibcon#about to read 6, iclass 17, count 0 2006.196.07:51:59.27#ibcon#read 6, iclass 17, count 0 2006.196.07:51:59.27#ibcon#end of sib2, iclass 17, count 0 2006.196.07:51:59.27#ibcon#*after write, iclass 17, count 0 2006.196.07:51:59.27#ibcon#*before return 0, iclass 17, count 0 2006.196.07:51:59.27#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.196.07:51:59.27#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.196.07:51:59.27#ibcon#about to clear, iclass 17 cls_cnt 0 2006.196.07:51:59.27#ibcon#cleared, iclass 17 cls_cnt 0 2006.196.07:51:59.27$vc4f8/va=5,7 2006.196.07:51:59.27#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.196.07:51:59.27#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.196.07:51:59.27#ibcon#ireg 11 cls_cnt 2 2006.196.07:51:59.27#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.196.07:51:59.33#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.196.07:51:59.33#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.196.07:51:59.33#ibcon#enter wrdev, iclass 19, count 2 2006.196.07:51:59.33#ibcon#first serial, iclass 19, count 2 2006.196.07:51:59.33#ibcon#enter sib2, iclass 19, count 2 2006.196.07:51:59.33#ibcon#flushed, iclass 19, count 2 2006.196.07:51:59.33#ibcon#about to write, iclass 19, count 2 2006.196.07:51:59.33#ibcon#wrote, iclass 19, count 2 2006.196.07:51:59.33#ibcon#about to read 3, iclass 19, count 2 2006.196.07:51:59.35#ibcon#read 3, iclass 19, count 2 2006.196.07:51:59.35#ibcon#about to read 4, iclass 19, count 2 2006.196.07:51:59.35#ibcon#read 4, iclass 19, count 2 2006.196.07:51:59.35#ibcon#about to read 5, iclass 19, count 2 2006.196.07:51:59.35#ibcon#read 5, iclass 19, count 2 2006.196.07:51:59.35#ibcon#about to read 6, iclass 19, count 2 2006.196.07:51:59.35#ibcon#read 6, iclass 19, count 2 2006.196.07:51:59.35#ibcon#end of sib2, iclass 19, count 2 2006.196.07:51:59.35#ibcon#*mode == 0, iclass 19, count 2 2006.196.07:51:59.35#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.196.07:51:59.35#ibcon#[25=AT05-07\r\n] 2006.196.07:51:59.35#ibcon#*before write, iclass 19, count 2 2006.196.07:51:59.35#ibcon#enter sib2, iclass 19, count 2 2006.196.07:51:59.35#ibcon#flushed, iclass 19, count 2 2006.196.07:51:59.35#ibcon#about to write, iclass 19, count 2 2006.196.07:51:59.35#ibcon#wrote, iclass 19, count 2 2006.196.07:51:59.35#ibcon#about to read 3, iclass 19, count 2 2006.196.07:51:59.38#ibcon#read 3, iclass 19, count 2 2006.196.07:51:59.38#ibcon#about to read 4, iclass 19, count 2 2006.196.07:51:59.38#ibcon#read 4, iclass 19, count 2 2006.196.07:51:59.38#ibcon#about to read 5, iclass 19, count 2 2006.196.07:51:59.38#ibcon#read 5, iclass 19, count 2 2006.196.07:51:59.38#ibcon#about to read 6, iclass 19, count 2 2006.196.07:51:59.38#ibcon#read 6, iclass 19, count 2 2006.196.07:51:59.38#ibcon#end of sib2, iclass 19, count 2 2006.196.07:51:59.38#ibcon#*after write, iclass 19, count 2 2006.196.07:51:59.38#ibcon#*before return 0, iclass 19, count 2 2006.196.07:51:59.38#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.196.07:51:59.38#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.196.07:51:59.38#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.196.07:51:59.38#ibcon#ireg 7 cls_cnt 0 2006.196.07:51:59.38#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.196.07:51:59.50#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.196.07:51:59.50#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.196.07:51:59.50#ibcon#enter wrdev, iclass 19, count 0 2006.196.07:51:59.50#ibcon#first serial, iclass 19, count 0 2006.196.07:51:59.50#ibcon#enter sib2, iclass 19, count 0 2006.196.07:51:59.50#ibcon#flushed, iclass 19, count 0 2006.196.07:51:59.50#ibcon#about to write, iclass 19, count 0 2006.196.07:51:59.50#ibcon#wrote, iclass 19, count 0 2006.196.07:51:59.50#ibcon#about to read 3, iclass 19, count 0 2006.196.07:51:59.52#ibcon#read 3, iclass 19, count 0 2006.196.07:51:59.52#ibcon#about to read 4, iclass 19, count 0 2006.196.07:51:59.52#ibcon#read 4, iclass 19, count 0 2006.196.07:51:59.52#ibcon#about to read 5, iclass 19, count 0 2006.196.07:51:59.52#ibcon#read 5, iclass 19, count 0 2006.196.07:51:59.52#ibcon#about to read 6, iclass 19, count 0 2006.196.07:51:59.52#ibcon#read 6, iclass 19, count 0 2006.196.07:51:59.52#ibcon#end of sib2, iclass 19, count 0 2006.196.07:51:59.52#ibcon#*mode == 0, iclass 19, count 0 2006.196.07:51:59.52#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.196.07:51:59.52#ibcon#[25=USB\r\n] 2006.196.07:51:59.52#ibcon#*before write, iclass 19, count 0 2006.196.07:51:59.52#ibcon#enter sib2, iclass 19, count 0 2006.196.07:51:59.52#ibcon#flushed, iclass 19, count 0 2006.196.07:51:59.52#ibcon#about to write, iclass 19, count 0 2006.196.07:51:59.52#ibcon#wrote, iclass 19, count 0 2006.196.07:51:59.52#ibcon#about to read 3, iclass 19, count 0 2006.196.07:51:59.55#ibcon#read 3, iclass 19, count 0 2006.196.07:51:59.55#ibcon#about to read 4, iclass 19, count 0 2006.196.07:51:59.55#ibcon#read 4, iclass 19, count 0 2006.196.07:51:59.55#ibcon#about to read 5, iclass 19, count 0 2006.196.07:51:59.55#ibcon#read 5, iclass 19, count 0 2006.196.07:51:59.55#ibcon#about to read 6, iclass 19, count 0 2006.196.07:51:59.55#ibcon#read 6, iclass 19, count 0 2006.196.07:51:59.55#ibcon#end of sib2, iclass 19, count 0 2006.196.07:51:59.55#ibcon#*after write, iclass 19, count 0 2006.196.07:51:59.55#ibcon#*before return 0, iclass 19, count 0 2006.196.07:51:59.55#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.196.07:51:59.55#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.196.07:51:59.55#ibcon#about to clear, iclass 19 cls_cnt 0 2006.196.07:51:59.55#ibcon#cleared, iclass 19 cls_cnt 0 2006.196.07:51:59.55$vc4f8/valo=6,772.99 2006.196.07:51:59.55#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.196.07:51:59.55#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.196.07:51:59.55#ibcon#ireg 17 cls_cnt 0 2006.196.07:51:59.55#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.196.07:51:59.55#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.196.07:51:59.55#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.196.07:51:59.55#ibcon#enter wrdev, iclass 21, count 0 2006.196.07:51:59.55#ibcon#first serial, iclass 21, count 0 2006.196.07:51:59.55#ibcon#enter sib2, iclass 21, count 0 2006.196.07:51:59.55#ibcon#flushed, iclass 21, count 0 2006.196.07:51:59.55#ibcon#about to write, iclass 21, count 0 2006.196.07:51:59.55#ibcon#wrote, iclass 21, count 0 2006.196.07:51:59.55#ibcon#about to read 3, iclass 21, count 0 2006.196.07:51:59.57#ibcon#read 3, iclass 21, count 0 2006.196.07:51:59.57#ibcon#about to read 4, iclass 21, count 0 2006.196.07:51:59.57#ibcon#read 4, iclass 21, count 0 2006.196.07:51:59.57#ibcon#about to read 5, iclass 21, count 0 2006.196.07:51:59.57#ibcon#read 5, iclass 21, count 0 2006.196.07:51:59.57#ibcon#about to read 6, iclass 21, count 0 2006.196.07:51:59.57#ibcon#read 6, iclass 21, count 0 2006.196.07:51:59.57#ibcon#end of sib2, iclass 21, count 0 2006.196.07:51:59.57#ibcon#*mode == 0, iclass 21, count 0 2006.196.07:51:59.57#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.196.07:51:59.57#ibcon#[26=FRQ=06,772.99\r\n] 2006.196.07:51:59.57#ibcon#*before write, iclass 21, count 0 2006.196.07:51:59.57#ibcon#enter sib2, iclass 21, count 0 2006.196.07:51:59.57#ibcon#flushed, iclass 21, count 0 2006.196.07:51:59.57#ibcon#about to write, iclass 21, count 0 2006.196.07:51:59.57#ibcon#wrote, iclass 21, count 0 2006.196.07:51:59.57#ibcon#about to read 3, iclass 21, count 0 2006.196.07:51:59.61#ibcon#read 3, iclass 21, count 0 2006.196.07:51:59.61#ibcon#about to read 4, iclass 21, count 0 2006.196.07:51:59.61#ibcon#read 4, iclass 21, count 0 2006.196.07:51:59.61#ibcon#about to read 5, iclass 21, count 0 2006.196.07:51:59.61#ibcon#read 5, iclass 21, count 0 2006.196.07:51:59.61#ibcon#about to read 6, iclass 21, count 0 2006.196.07:51:59.61#ibcon#read 6, iclass 21, count 0 2006.196.07:51:59.61#ibcon#end of sib2, iclass 21, count 0 2006.196.07:51:59.61#ibcon#*after write, iclass 21, count 0 2006.196.07:51:59.61#ibcon#*before return 0, iclass 21, count 0 2006.196.07:51:59.61#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.196.07:51:59.61#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.196.07:51:59.61#ibcon#about to clear, iclass 21 cls_cnt 0 2006.196.07:51:59.61#ibcon#cleared, iclass 21 cls_cnt 0 2006.196.07:51:59.61$vc4f8/va=6,6 2006.196.07:51:59.61#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.196.07:51:59.61#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.196.07:51:59.61#ibcon#ireg 11 cls_cnt 2 2006.196.07:51:59.61#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.196.07:51:59.67#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.196.07:51:59.67#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.196.07:51:59.67#ibcon#enter wrdev, iclass 23, count 2 2006.196.07:51:59.67#ibcon#first serial, iclass 23, count 2 2006.196.07:51:59.67#ibcon#enter sib2, iclass 23, count 2 2006.196.07:51:59.67#ibcon#flushed, iclass 23, count 2 2006.196.07:51:59.67#ibcon#about to write, iclass 23, count 2 2006.196.07:51:59.67#ibcon#wrote, iclass 23, count 2 2006.196.07:51:59.67#ibcon#about to read 3, iclass 23, count 2 2006.196.07:51:59.69#ibcon#read 3, iclass 23, count 2 2006.196.07:51:59.69#ibcon#about to read 4, iclass 23, count 2 2006.196.07:51:59.69#ibcon#read 4, iclass 23, count 2 2006.196.07:51:59.69#ibcon#about to read 5, iclass 23, count 2 2006.196.07:51:59.69#ibcon#read 5, iclass 23, count 2 2006.196.07:51:59.69#ibcon#about to read 6, iclass 23, count 2 2006.196.07:51:59.69#ibcon#read 6, iclass 23, count 2 2006.196.07:51:59.69#ibcon#end of sib2, iclass 23, count 2 2006.196.07:51:59.69#ibcon#*mode == 0, iclass 23, count 2 2006.196.07:51:59.69#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.196.07:51:59.69#ibcon#[25=AT06-06\r\n] 2006.196.07:51:59.69#ibcon#*before write, iclass 23, count 2 2006.196.07:51:59.69#ibcon#enter sib2, iclass 23, count 2 2006.196.07:51:59.69#ibcon#flushed, iclass 23, count 2 2006.196.07:51:59.69#ibcon#about to write, iclass 23, count 2 2006.196.07:51:59.69#ibcon#wrote, iclass 23, count 2 2006.196.07:51:59.69#ibcon#about to read 3, iclass 23, count 2 2006.196.07:51:59.72#ibcon#read 3, iclass 23, count 2 2006.196.07:51:59.72#ibcon#about to read 4, iclass 23, count 2 2006.196.07:51:59.72#ibcon#read 4, iclass 23, count 2 2006.196.07:51:59.72#ibcon#about to read 5, iclass 23, count 2 2006.196.07:51:59.72#ibcon#read 5, iclass 23, count 2 2006.196.07:51:59.72#ibcon#about to read 6, iclass 23, count 2 2006.196.07:51:59.72#ibcon#read 6, iclass 23, count 2 2006.196.07:51:59.72#ibcon#end of sib2, iclass 23, count 2 2006.196.07:51:59.72#ibcon#*after write, iclass 23, count 2 2006.196.07:51:59.72#ibcon#*before return 0, iclass 23, count 2 2006.196.07:51:59.72#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.196.07:51:59.72#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.196.07:51:59.72#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.196.07:51:59.72#ibcon#ireg 7 cls_cnt 0 2006.196.07:51:59.72#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.196.07:51:59.84#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.196.07:51:59.84#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.196.07:51:59.84#ibcon#enter wrdev, iclass 23, count 0 2006.196.07:51:59.84#ibcon#first serial, iclass 23, count 0 2006.196.07:51:59.84#ibcon#enter sib2, iclass 23, count 0 2006.196.07:51:59.84#ibcon#flushed, iclass 23, count 0 2006.196.07:51:59.84#ibcon#about to write, iclass 23, count 0 2006.196.07:51:59.84#ibcon#wrote, iclass 23, count 0 2006.196.07:51:59.84#ibcon#about to read 3, iclass 23, count 0 2006.196.07:51:59.86#ibcon#read 3, iclass 23, count 0 2006.196.07:51:59.86#ibcon#about to read 4, iclass 23, count 0 2006.196.07:51:59.86#ibcon#read 4, iclass 23, count 0 2006.196.07:51:59.86#ibcon#about to read 5, iclass 23, count 0 2006.196.07:51:59.86#ibcon#read 5, iclass 23, count 0 2006.196.07:51:59.86#ibcon#about to read 6, iclass 23, count 0 2006.196.07:51:59.86#ibcon#read 6, iclass 23, count 0 2006.196.07:51:59.86#ibcon#end of sib2, iclass 23, count 0 2006.196.07:51:59.86#ibcon#*mode == 0, iclass 23, count 0 2006.196.07:51:59.86#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.196.07:51:59.86#ibcon#[25=USB\r\n] 2006.196.07:51:59.86#ibcon#*before write, iclass 23, count 0 2006.196.07:51:59.86#ibcon#enter sib2, iclass 23, count 0 2006.196.07:51:59.86#ibcon#flushed, iclass 23, count 0 2006.196.07:51:59.86#ibcon#about to write, iclass 23, count 0 2006.196.07:51:59.86#ibcon#wrote, iclass 23, count 0 2006.196.07:51:59.86#ibcon#about to read 3, iclass 23, count 0 2006.196.07:51:59.89#ibcon#read 3, iclass 23, count 0 2006.196.07:51:59.89#ibcon#about to read 4, iclass 23, count 0 2006.196.07:51:59.89#ibcon#read 4, iclass 23, count 0 2006.196.07:51:59.89#ibcon#about to read 5, iclass 23, count 0 2006.196.07:51:59.89#ibcon#read 5, iclass 23, count 0 2006.196.07:51:59.89#ibcon#about to read 6, iclass 23, count 0 2006.196.07:51:59.89#ibcon#read 6, iclass 23, count 0 2006.196.07:51:59.89#ibcon#end of sib2, iclass 23, count 0 2006.196.07:51:59.89#ibcon#*after write, iclass 23, count 0 2006.196.07:51:59.89#ibcon#*before return 0, iclass 23, count 0 2006.196.07:51:59.89#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.196.07:51:59.89#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.196.07:51:59.89#ibcon#about to clear, iclass 23 cls_cnt 0 2006.196.07:51:59.89#ibcon#cleared, iclass 23 cls_cnt 0 2006.196.07:51:59.89$vc4f8/valo=7,832.99 2006.196.07:51:59.89#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.196.07:51:59.89#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.196.07:51:59.89#ibcon#ireg 17 cls_cnt 0 2006.196.07:51:59.89#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.196.07:51:59.89#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.196.07:51:59.89#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.196.07:51:59.89#ibcon#enter wrdev, iclass 25, count 0 2006.196.07:51:59.89#ibcon#first serial, iclass 25, count 0 2006.196.07:51:59.89#ibcon#enter sib2, iclass 25, count 0 2006.196.07:51:59.89#ibcon#flushed, iclass 25, count 0 2006.196.07:51:59.89#ibcon#about to write, iclass 25, count 0 2006.196.07:51:59.89#ibcon#wrote, iclass 25, count 0 2006.196.07:51:59.89#ibcon#about to read 3, iclass 25, count 0 2006.196.07:51:59.91#ibcon#read 3, iclass 25, count 0 2006.196.07:51:59.91#ibcon#about to read 4, iclass 25, count 0 2006.196.07:51:59.91#ibcon#read 4, iclass 25, count 0 2006.196.07:51:59.91#ibcon#about to read 5, iclass 25, count 0 2006.196.07:51:59.91#ibcon#read 5, iclass 25, count 0 2006.196.07:51:59.91#ibcon#about to read 6, iclass 25, count 0 2006.196.07:51:59.91#ibcon#read 6, iclass 25, count 0 2006.196.07:51:59.91#ibcon#end of sib2, iclass 25, count 0 2006.196.07:51:59.91#ibcon#*mode == 0, iclass 25, count 0 2006.196.07:51:59.91#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.196.07:51:59.91#ibcon#[26=FRQ=07,832.99\r\n] 2006.196.07:51:59.91#ibcon#*before write, iclass 25, count 0 2006.196.07:51:59.91#ibcon#enter sib2, iclass 25, count 0 2006.196.07:51:59.91#ibcon#flushed, iclass 25, count 0 2006.196.07:51:59.91#ibcon#about to write, iclass 25, count 0 2006.196.07:51:59.91#ibcon#wrote, iclass 25, count 0 2006.196.07:51:59.91#ibcon#about to read 3, iclass 25, count 0 2006.196.07:51:59.95#ibcon#read 3, iclass 25, count 0 2006.196.07:51:59.95#ibcon#about to read 4, iclass 25, count 0 2006.196.07:51:59.95#ibcon#read 4, iclass 25, count 0 2006.196.07:51:59.95#ibcon#about to read 5, iclass 25, count 0 2006.196.07:51:59.95#ibcon#read 5, iclass 25, count 0 2006.196.07:51:59.95#ibcon#about to read 6, iclass 25, count 0 2006.196.07:51:59.95#ibcon#read 6, iclass 25, count 0 2006.196.07:51:59.95#ibcon#end of sib2, iclass 25, count 0 2006.196.07:51:59.95#ibcon#*after write, iclass 25, count 0 2006.196.07:51:59.95#ibcon#*before return 0, iclass 25, count 0 2006.196.07:51:59.95#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.196.07:51:59.95#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.196.07:51:59.95#ibcon#about to clear, iclass 25 cls_cnt 0 2006.196.07:51:59.95#ibcon#cleared, iclass 25 cls_cnt 0 2006.196.07:51:59.95$vc4f8/va=7,6 2006.196.07:51:59.95#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.196.07:51:59.95#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.196.07:51:59.95#ibcon#ireg 11 cls_cnt 2 2006.196.07:51:59.95#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.196.07:52:00.01#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.196.07:52:00.01#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.196.07:52:00.01#ibcon#enter wrdev, iclass 27, count 2 2006.196.07:52:00.01#ibcon#first serial, iclass 27, count 2 2006.196.07:52:00.01#ibcon#enter sib2, iclass 27, count 2 2006.196.07:52:00.01#ibcon#flushed, iclass 27, count 2 2006.196.07:52:00.01#ibcon#about to write, iclass 27, count 2 2006.196.07:52:00.01#ibcon#wrote, iclass 27, count 2 2006.196.07:52:00.01#ibcon#about to read 3, iclass 27, count 2 2006.196.07:52:00.03#ibcon#read 3, iclass 27, count 2 2006.196.07:52:00.03#ibcon#about to read 4, iclass 27, count 2 2006.196.07:52:00.03#ibcon#read 4, iclass 27, count 2 2006.196.07:52:00.03#ibcon#about to read 5, iclass 27, count 2 2006.196.07:52:00.03#ibcon#read 5, iclass 27, count 2 2006.196.07:52:00.03#ibcon#about to read 6, iclass 27, count 2 2006.196.07:52:00.03#ibcon#read 6, iclass 27, count 2 2006.196.07:52:00.03#ibcon#end of sib2, iclass 27, count 2 2006.196.07:52:00.03#ibcon#*mode == 0, iclass 27, count 2 2006.196.07:52:00.03#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.196.07:52:00.03#ibcon#[25=AT07-06\r\n] 2006.196.07:52:00.03#ibcon#*before write, iclass 27, count 2 2006.196.07:52:00.03#ibcon#enter sib2, iclass 27, count 2 2006.196.07:52:00.03#ibcon#flushed, iclass 27, count 2 2006.196.07:52:00.03#ibcon#about to write, iclass 27, count 2 2006.196.07:52:00.03#ibcon#wrote, iclass 27, count 2 2006.196.07:52:00.03#ibcon#about to read 3, iclass 27, count 2 2006.196.07:52:00.06#ibcon#read 3, iclass 27, count 2 2006.196.07:52:00.06#ibcon#about to read 4, iclass 27, count 2 2006.196.07:52:00.06#ibcon#read 4, iclass 27, count 2 2006.196.07:52:00.06#ibcon#about to read 5, iclass 27, count 2 2006.196.07:52:00.06#ibcon#read 5, iclass 27, count 2 2006.196.07:52:00.06#ibcon#about to read 6, iclass 27, count 2 2006.196.07:52:00.06#ibcon#read 6, iclass 27, count 2 2006.196.07:52:00.06#ibcon#end of sib2, iclass 27, count 2 2006.196.07:52:00.06#ibcon#*after write, iclass 27, count 2 2006.196.07:52:00.06#ibcon#*before return 0, iclass 27, count 2 2006.196.07:52:00.06#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.196.07:52:00.06#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.196.07:52:00.06#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.196.07:52:00.06#ibcon#ireg 7 cls_cnt 0 2006.196.07:52:00.06#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.196.07:52:00.18#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.196.07:52:00.18#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.196.07:52:00.18#ibcon#enter wrdev, iclass 27, count 0 2006.196.07:52:00.18#ibcon#first serial, iclass 27, count 0 2006.196.07:52:00.18#ibcon#enter sib2, iclass 27, count 0 2006.196.07:52:00.18#ibcon#flushed, iclass 27, count 0 2006.196.07:52:00.18#ibcon#about to write, iclass 27, count 0 2006.196.07:52:00.18#ibcon#wrote, iclass 27, count 0 2006.196.07:52:00.18#ibcon#about to read 3, iclass 27, count 0 2006.196.07:52:00.21#ibcon#read 3, iclass 27, count 0 2006.196.07:52:00.21#ibcon#about to read 4, iclass 27, count 0 2006.196.07:52:00.21#ibcon#read 4, iclass 27, count 0 2006.196.07:52:00.21#ibcon#about to read 5, iclass 27, count 0 2006.196.07:52:00.21#ibcon#read 5, iclass 27, count 0 2006.196.07:52:00.21#ibcon#about to read 6, iclass 27, count 0 2006.196.07:52:00.21#ibcon#read 6, iclass 27, count 0 2006.196.07:52:00.21#ibcon#end of sib2, iclass 27, count 0 2006.196.07:52:00.21#ibcon#*mode == 0, iclass 27, count 0 2006.196.07:52:00.21#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.196.07:52:00.21#ibcon#[25=USB\r\n] 2006.196.07:52:00.21#ibcon#*before write, iclass 27, count 0 2006.196.07:52:00.21#ibcon#enter sib2, iclass 27, count 0 2006.196.07:52:00.21#ibcon#flushed, iclass 27, count 0 2006.196.07:52:00.21#ibcon#about to write, iclass 27, count 0 2006.196.07:52:00.21#ibcon#wrote, iclass 27, count 0 2006.196.07:52:00.21#ibcon#about to read 3, iclass 27, count 0 2006.196.07:52:00.24#ibcon#read 3, iclass 27, count 0 2006.196.07:52:00.24#ibcon#about to read 4, iclass 27, count 0 2006.196.07:52:00.24#ibcon#read 4, iclass 27, count 0 2006.196.07:52:00.24#ibcon#about to read 5, iclass 27, count 0 2006.196.07:52:00.24#ibcon#read 5, iclass 27, count 0 2006.196.07:52:00.24#ibcon#about to read 6, iclass 27, count 0 2006.196.07:52:00.24#ibcon#read 6, iclass 27, count 0 2006.196.07:52:00.24#ibcon#end of sib2, iclass 27, count 0 2006.196.07:52:00.24#ibcon#*after write, iclass 27, count 0 2006.196.07:52:00.24#ibcon#*before return 0, iclass 27, count 0 2006.196.07:52:00.24#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.196.07:52:00.24#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.196.07:52:00.24#ibcon#about to clear, iclass 27 cls_cnt 0 2006.196.07:52:00.24#ibcon#cleared, iclass 27 cls_cnt 0 2006.196.07:52:00.24$vc4f8/valo=8,852.99 2006.196.07:52:00.24#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.196.07:52:00.24#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.196.07:52:00.24#ibcon#ireg 17 cls_cnt 0 2006.196.07:52:00.24#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.196.07:52:00.24#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.196.07:52:00.24#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.196.07:52:00.24#ibcon#enter wrdev, iclass 29, count 0 2006.196.07:52:00.24#ibcon#first serial, iclass 29, count 0 2006.196.07:52:00.24#ibcon#enter sib2, iclass 29, count 0 2006.196.07:52:00.24#ibcon#flushed, iclass 29, count 0 2006.196.07:52:00.24#ibcon#about to write, iclass 29, count 0 2006.196.07:52:00.24#ibcon#wrote, iclass 29, count 0 2006.196.07:52:00.24#ibcon#about to read 3, iclass 29, count 0 2006.196.07:52:00.26#ibcon#read 3, iclass 29, count 0 2006.196.07:52:00.26#ibcon#about to read 4, iclass 29, count 0 2006.196.07:52:00.26#ibcon#read 4, iclass 29, count 0 2006.196.07:52:00.26#ibcon#about to read 5, iclass 29, count 0 2006.196.07:52:00.26#ibcon#read 5, iclass 29, count 0 2006.196.07:52:00.26#ibcon#about to read 6, iclass 29, count 0 2006.196.07:52:00.26#ibcon#read 6, iclass 29, count 0 2006.196.07:52:00.26#ibcon#end of sib2, iclass 29, count 0 2006.196.07:52:00.26#ibcon#*mode == 0, iclass 29, count 0 2006.196.07:52:00.26#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.196.07:52:00.26#ibcon#[26=FRQ=08,852.99\r\n] 2006.196.07:52:00.26#ibcon#*before write, iclass 29, count 0 2006.196.07:52:00.26#ibcon#enter sib2, iclass 29, count 0 2006.196.07:52:00.26#ibcon#flushed, iclass 29, count 0 2006.196.07:52:00.26#ibcon#about to write, iclass 29, count 0 2006.196.07:52:00.26#ibcon#wrote, iclass 29, count 0 2006.196.07:52:00.26#ibcon#about to read 3, iclass 29, count 0 2006.196.07:52:00.30#ibcon#read 3, iclass 29, count 0 2006.196.07:52:00.30#ibcon#about to read 4, iclass 29, count 0 2006.196.07:52:00.30#ibcon#read 4, iclass 29, count 0 2006.196.07:52:00.30#ibcon#about to read 5, iclass 29, count 0 2006.196.07:52:00.30#ibcon#read 5, iclass 29, count 0 2006.196.07:52:00.30#ibcon#about to read 6, iclass 29, count 0 2006.196.07:52:00.30#ibcon#read 6, iclass 29, count 0 2006.196.07:52:00.30#ibcon#end of sib2, iclass 29, count 0 2006.196.07:52:00.30#ibcon#*after write, iclass 29, count 0 2006.196.07:52:00.30#ibcon#*before return 0, iclass 29, count 0 2006.196.07:52:00.30#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.196.07:52:00.30#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.196.07:52:00.30#ibcon#about to clear, iclass 29 cls_cnt 0 2006.196.07:52:00.30#ibcon#cleared, iclass 29 cls_cnt 0 2006.196.07:52:00.30$vc4f8/va=8,7 2006.196.07:52:00.30#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.196.07:52:00.30#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.196.07:52:00.30#ibcon#ireg 11 cls_cnt 2 2006.196.07:52:00.30#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.196.07:52:00.36#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.196.07:52:00.36#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.196.07:52:00.36#ibcon#enter wrdev, iclass 31, count 2 2006.196.07:52:00.36#ibcon#first serial, iclass 31, count 2 2006.196.07:52:00.36#ibcon#enter sib2, iclass 31, count 2 2006.196.07:52:00.36#ibcon#flushed, iclass 31, count 2 2006.196.07:52:00.36#ibcon#about to write, iclass 31, count 2 2006.196.07:52:00.36#ibcon#wrote, iclass 31, count 2 2006.196.07:52:00.36#ibcon#about to read 3, iclass 31, count 2 2006.196.07:52:00.38#ibcon#read 3, iclass 31, count 2 2006.196.07:52:00.38#ibcon#about to read 4, iclass 31, count 2 2006.196.07:52:00.38#ibcon#read 4, iclass 31, count 2 2006.196.07:52:00.38#ibcon#about to read 5, iclass 31, count 2 2006.196.07:52:00.38#ibcon#read 5, iclass 31, count 2 2006.196.07:52:00.38#ibcon#about to read 6, iclass 31, count 2 2006.196.07:52:00.38#ibcon#read 6, iclass 31, count 2 2006.196.07:52:00.38#ibcon#end of sib2, iclass 31, count 2 2006.196.07:52:00.38#ibcon#*mode == 0, iclass 31, count 2 2006.196.07:52:00.38#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.196.07:52:00.38#ibcon#[25=AT08-07\r\n] 2006.196.07:52:00.38#ibcon#*before write, iclass 31, count 2 2006.196.07:52:00.38#ibcon#enter sib2, iclass 31, count 2 2006.196.07:52:00.38#ibcon#flushed, iclass 31, count 2 2006.196.07:52:00.38#ibcon#about to write, iclass 31, count 2 2006.196.07:52:00.38#ibcon#wrote, iclass 31, count 2 2006.196.07:52:00.38#ibcon#about to read 3, iclass 31, count 2 2006.196.07:52:00.41#ibcon#read 3, iclass 31, count 2 2006.196.07:52:00.41#ibcon#about to read 4, iclass 31, count 2 2006.196.07:52:00.41#ibcon#read 4, iclass 31, count 2 2006.196.07:52:00.41#ibcon#about to read 5, iclass 31, count 2 2006.196.07:52:00.41#ibcon#read 5, iclass 31, count 2 2006.196.07:52:00.41#ibcon#about to read 6, iclass 31, count 2 2006.196.07:52:00.41#ibcon#read 6, iclass 31, count 2 2006.196.07:52:00.41#ibcon#end of sib2, iclass 31, count 2 2006.196.07:52:00.41#ibcon#*after write, iclass 31, count 2 2006.196.07:52:00.41#ibcon#*before return 0, iclass 31, count 2 2006.196.07:52:00.41#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.196.07:52:00.41#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.196.07:52:00.41#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.196.07:52:00.41#ibcon#ireg 7 cls_cnt 0 2006.196.07:52:00.41#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.196.07:52:00.53#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.196.07:52:00.53#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.196.07:52:00.53#ibcon#enter wrdev, iclass 31, count 0 2006.196.07:52:00.53#ibcon#first serial, iclass 31, count 0 2006.196.07:52:00.53#ibcon#enter sib2, iclass 31, count 0 2006.196.07:52:00.53#ibcon#flushed, iclass 31, count 0 2006.196.07:52:00.53#ibcon#about to write, iclass 31, count 0 2006.196.07:52:00.53#ibcon#wrote, iclass 31, count 0 2006.196.07:52:00.53#ibcon#about to read 3, iclass 31, count 0 2006.196.07:52:00.55#ibcon#read 3, iclass 31, count 0 2006.196.07:52:00.55#ibcon#about to read 4, iclass 31, count 0 2006.196.07:52:00.55#ibcon#read 4, iclass 31, count 0 2006.196.07:52:00.55#ibcon#about to read 5, iclass 31, count 0 2006.196.07:52:00.55#ibcon#read 5, iclass 31, count 0 2006.196.07:52:00.55#ibcon#about to read 6, iclass 31, count 0 2006.196.07:52:00.55#ibcon#read 6, iclass 31, count 0 2006.196.07:52:00.55#ibcon#end of sib2, iclass 31, count 0 2006.196.07:52:00.55#ibcon#*mode == 0, iclass 31, count 0 2006.196.07:52:00.55#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.196.07:52:00.55#ibcon#[25=USB\r\n] 2006.196.07:52:00.55#ibcon#*before write, iclass 31, count 0 2006.196.07:52:00.55#ibcon#enter sib2, iclass 31, count 0 2006.196.07:52:00.55#ibcon#flushed, iclass 31, count 0 2006.196.07:52:00.55#ibcon#about to write, iclass 31, count 0 2006.196.07:52:00.55#ibcon#wrote, iclass 31, count 0 2006.196.07:52:00.55#ibcon#about to read 3, iclass 31, count 0 2006.196.07:52:00.58#ibcon#read 3, iclass 31, count 0 2006.196.07:52:00.58#ibcon#about to read 4, iclass 31, count 0 2006.196.07:52:00.58#ibcon#read 4, iclass 31, count 0 2006.196.07:52:00.58#ibcon#about to read 5, iclass 31, count 0 2006.196.07:52:00.58#ibcon#read 5, iclass 31, count 0 2006.196.07:52:00.58#ibcon#about to read 6, iclass 31, count 0 2006.196.07:52:00.58#ibcon#read 6, iclass 31, count 0 2006.196.07:52:00.58#ibcon#end of sib2, iclass 31, count 0 2006.196.07:52:00.58#ibcon#*after write, iclass 31, count 0 2006.196.07:52:00.58#ibcon#*before return 0, iclass 31, count 0 2006.196.07:52:00.58#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.196.07:52:00.58#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.196.07:52:00.58#ibcon#about to clear, iclass 31 cls_cnt 0 2006.196.07:52:00.58#ibcon#cleared, iclass 31 cls_cnt 0 2006.196.07:52:00.58$vc4f8/vblo=1,632.99 2006.196.07:52:00.58#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.196.07:52:00.58#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.196.07:52:00.58#ibcon#ireg 17 cls_cnt 0 2006.196.07:52:00.58#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.196.07:52:00.58#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.196.07:52:00.58#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.196.07:52:00.58#ibcon#enter wrdev, iclass 33, count 0 2006.196.07:52:00.58#ibcon#first serial, iclass 33, count 0 2006.196.07:52:00.58#ibcon#enter sib2, iclass 33, count 0 2006.196.07:52:00.58#ibcon#flushed, iclass 33, count 0 2006.196.07:52:00.58#ibcon#about to write, iclass 33, count 0 2006.196.07:52:00.58#ibcon#wrote, iclass 33, count 0 2006.196.07:52:00.58#ibcon#about to read 3, iclass 33, count 0 2006.196.07:52:00.60#ibcon#read 3, iclass 33, count 0 2006.196.07:52:00.60#ibcon#about to read 4, iclass 33, count 0 2006.196.07:52:00.60#ibcon#read 4, iclass 33, count 0 2006.196.07:52:00.60#ibcon#about to read 5, iclass 33, count 0 2006.196.07:52:00.60#ibcon#read 5, iclass 33, count 0 2006.196.07:52:00.60#ibcon#about to read 6, iclass 33, count 0 2006.196.07:52:00.60#ibcon#read 6, iclass 33, count 0 2006.196.07:52:00.60#ibcon#end of sib2, iclass 33, count 0 2006.196.07:52:00.60#ibcon#*mode == 0, iclass 33, count 0 2006.196.07:52:00.60#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.196.07:52:00.60#ibcon#[28=FRQ=01,632.99\r\n] 2006.196.07:52:00.60#ibcon#*before write, iclass 33, count 0 2006.196.07:52:00.60#ibcon#enter sib2, iclass 33, count 0 2006.196.07:52:00.60#ibcon#flushed, iclass 33, count 0 2006.196.07:52:00.60#ibcon#about to write, iclass 33, count 0 2006.196.07:52:00.60#ibcon#wrote, iclass 33, count 0 2006.196.07:52:00.60#ibcon#about to read 3, iclass 33, count 0 2006.196.07:52:00.64#ibcon#read 3, iclass 33, count 0 2006.196.07:52:00.64#ibcon#about to read 4, iclass 33, count 0 2006.196.07:52:00.64#ibcon#read 4, iclass 33, count 0 2006.196.07:52:00.64#ibcon#about to read 5, iclass 33, count 0 2006.196.07:52:00.64#ibcon#read 5, iclass 33, count 0 2006.196.07:52:00.64#ibcon#about to read 6, iclass 33, count 0 2006.196.07:52:00.64#ibcon#read 6, iclass 33, count 0 2006.196.07:52:00.64#ibcon#end of sib2, iclass 33, count 0 2006.196.07:52:00.64#ibcon#*after write, iclass 33, count 0 2006.196.07:52:00.64#ibcon#*before return 0, iclass 33, count 0 2006.196.07:52:00.64#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.196.07:52:00.64#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.196.07:52:00.64#ibcon#about to clear, iclass 33 cls_cnt 0 2006.196.07:52:00.64#ibcon#cleared, iclass 33 cls_cnt 0 2006.196.07:52:00.64$vc4f8/vb=1,4 2006.196.07:52:00.64#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.196.07:52:00.64#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.196.07:52:00.64#ibcon#ireg 11 cls_cnt 2 2006.196.07:52:00.64#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.196.07:52:00.64#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.196.07:52:00.64#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.196.07:52:00.64#ibcon#enter wrdev, iclass 35, count 2 2006.196.07:52:00.64#ibcon#first serial, iclass 35, count 2 2006.196.07:52:00.64#ibcon#enter sib2, iclass 35, count 2 2006.196.07:52:00.64#ibcon#flushed, iclass 35, count 2 2006.196.07:52:00.64#ibcon#about to write, iclass 35, count 2 2006.196.07:52:00.64#ibcon#wrote, iclass 35, count 2 2006.196.07:52:00.64#ibcon#about to read 3, iclass 35, count 2 2006.196.07:52:00.66#ibcon#read 3, iclass 35, count 2 2006.196.07:52:00.66#ibcon#about to read 4, iclass 35, count 2 2006.196.07:52:00.66#ibcon#read 4, iclass 35, count 2 2006.196.07:52:00.66#ibcon#about to read 5, iclass 35, count 2 2006.196.07:52:00.66#ibcon#read 5, iclass 35, count 2 2006.196.07:52:00.66#ibcon#about to read 6, iclass 35, count 2 2006.196.07:52:00.66#ibcon#read 6, iclass 35, count 2 2006.196.07:52:00.66#ibcon#end of sib2, iclass 35, count 2 2006.196.07:52:00.66#ibcon#*mode == 0, iclass 35, count 2 2006.196.07:52:00.66#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.196.07:52:00.66#ibcon#[27=AT01-04\r\n] 2006.196.07:52:00.66#ibcon#*before write, iclass 35, count 2 2006.196.07:52:00.66#ibcon#enter sib2, iclass 35, count 2 2006.196.07:52:00.66#ibcon#flushed, iclass 35, count 2 2006.196.07:52:00.66#ibcon#about to write, iclass 35, count 2 2006.196.07:52:00.66#ibcon#wrote, iclass 35, count 2 2006.196.07:52:00.66#ibcon#about to read 3, iclass 35, count 2 2006.196.07:52:00.69#ibcon#read 3, iclass 35, count 2 2006.196.07:52:00.69#ibcon#about to read 4, iclass 35, count 2 2006.196.07:52:00.69#ibcon#read 4, iclass 35, count 2 2006.196.07:52:00.69#ibcon#about to read 5, iclass 35, count 2 2006.196.07:52:00.69#ibcon#read 5, iclass 35, count 2 2006.196.07:52:00.69#ibcon#about to read 6, iclass 35, count 2 2006.196.07:52:00.69#ibcon#read 6, iclass 35, count 2 2006.196.07:52:00.69#ibcon#end of sib2, iclass 35, count 2 2006.196.07:52:00.69#ibcon#*after write, iclass 35, count 2 2006.196.07:52:00.69#ibcon#*before return 0, iclass 35, count 2 2006.196.07:52:00.69#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.196.07:52:00.69#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.196.07:52:00.69#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.196.07:52:00.69#ibcon#ireg 7 cls_cnt 0 2006.196.07:52:00.69#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.196.07:52:00.81#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.196.07:52:00.81#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.196.07:52:00.81#ibcon#enter wrdev, iclass 35, count 0 2006.196.07:52:00.81#ibcon#first serial, iclass 35, count 0 2006.196.07:52:00.81#ibcon#enter sib2, iclass 35, count 0 2006.196.07:52:00.81#ibcon#flushed, iclass 35, count 0 2006.196.07:52:00.81#ibcon#about to write, iclass 35, count 0 2006.196.07:52:00.81#ibcon#wrote, iclass 35, count 0 2006.196.07:52:00.81#ibcon#about to read 3, iclass 35, count 0 2006.196.07:52:00.83#ibcon#read 3, iclass 35, count 0 2006.196.07:52:00.83#ibcon#about to read 4, iclass 35, count 0 2006.196.07:52:00.83#ibcon#read 4, iclass 35, count 0 2006.196.07:52:00.83#ibcon#about to read 5, iclass 35, count 0 2006.196.07:52:00.83#ibcon#read 5, iclass 35, count 0 2006.196.07:52:00.83#ibcon#about to read 6, iclass 35, count 0 2006.196.07:52:00.83#ibcon#read 6, iclass 35, count 0 2006.196.07:52:00.83#ibcon#end of sib2, iclass 35, count 0 2006.196.07:52:00.83#ibcon#*mode == 0, iclass 35, count 0 2006.196.07:52:00.83#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.196.07:52:00.83#ibcon#[27=USB\r\n] 2006.196.07:52:00.83#ibcon#*before write, iclass 35, count 0 2006.196.07:52:00.83#ibcon#enter sib2, iclass 35, count 0 2006.196.07:52:00.83#ibcon#flushed, iclass 35, count 0 2006.196.07:52:00.83#ibcon#about to write, iclass 35, count 0 2006.196.07:52:00.83#ibcon#wrote, iclass 35, count 0 2006.196.07:52:00.83#ibcon#about to read 3, iclass 35, count 0 2006.196.07:52:00.86#ibcon#read 3, iclass 35, count 0 2006.196.07:52:00.86#ibcon#about to read 4, iclass 35, count 0 2006.196.07:52:00.86#ibcon#read 4, iclass 35, count 0 2006.196.07:52:00.86#ibcon#about to read 5, iclass 35, count 0 2006.196.07:52:00.86#ibcon#read 5, iclass 35, count 0 2006.196.07:52:00.86#ibcon#about to read 6, iclass 35, count 0 2006.196.07:52:00.86#ibcon#read 6, iclass 35, count 0 2006.196.07:52:00.86#ibcon#end of sib2, iclass 35, count 0 2006.196.07:52:00.86#ibcon#*after write, iclass 35, count 0 2006.196.07:52:00.86#ibcon#*before return 0, iclass 35, count 0 2006.196.07:52:00.86#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.196.07:52:00.86#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.196.07:52:00.86#ibcon#about to clear, iclass 35 cls_cnt 0 2006.196.07:52:00.86#ibcon#cleared, iclass 35 cls_cnt 0 2006.196.07:52:00.86$vc4f8/vblo=2,640.99 2006.196.07:52:00.86#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.196.07:52:00.86#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.196.07:52:00.86#ibcon#ireg 17 cls_cnt 0 2006.196.07:52:00.86#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.196.07:52:00.86#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.196.07:52:00.86#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.196.07:52:00.86#ibcon#enter wrdev, iclass 37, count 0 2006.196.07:52:00.86#ibcon#first serial, iclass 37, count 0 2006.196.07:52:00.86#ibcon#enter sib2, iclass 37, count 0 2006.196.07:52:00.86#ibcon#flushed, iclass 37, count 0 2006.196.07:52:00.86#ibcon#about to write, iclass 37, count 0 2006.196.07:52:00.86#ibcon#wrote, iclass 37, count 0 2006.196.07:52:00.86#ibcon#about to read 3, iclass 37, count 0 2006.196.07:52:00.88#ibcon#read 3, iclass 37, count 0 2006.196.07:52:00.88#ibcon#about to read 4, iclass 37, count 0 2006.196.07:52:00.88#ibcon#read 4, iclass 37, count 0 2006.196.07:52:00.88#ibcon#about to read 5, iclass 37, count 0 2006.196.07:52:00.88#ibcon#read 5, iclass 37, count 0 2006.196.07:52:00.88#ibcon#about to read 6, iclass 37, count 0 2006.196.07:52:00.88#ibcon#read 6, iclass 37, count 0 2006.196.07:52:00.88#ibcon#end of sib2, iclass 37, count 0 2006.196.07:52:00.88#ibcon#*mode == 0, iclass 37, count 0 2006.196.07:52:00.88#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.196.07:52:00.88#ibcon#[28=FRQ=02,640.99\r\n] 2006.196.07:52:00.88#ibcon#*before write, iclass 37, count 0 2006.196.07:52:00.88#ibcon#enter sib2, iclass 37, count 0 2006.196.07:52:00.88#ibcon#flushed, iclass 37, count 0 2006.196.07:52:00.88#ibcon#about to write, iclass 37, count 0 2006.196.07:52:00.88#ibcon#wrote, iclass 37, count 0 2006.196.07:52:00.88#ibcon#about to read 3, iclass 37, count 0 2006.196.07:52:00.93#ibcon#read 3, iclass 37, count 0 2006.196.07:52:00.93#ibcon#about to read 4, iclass 37, count 0 2006.196.07:52:00.93#ibcon#read 4, iclass 37, count 0 2006.196.07:52:00.93#ibcon#about to read 5, iclass 37, count 0 2006.196.07:52:00.93#ibcon#read 5, iclass 37, count 0 2006.196.07:52:00.93#ibcon#about to read 6, iclass 37, count 0 2006.196.07:52:00.93#ibcon#read 6, iclass 37, count 0 2006.196.07:52:00.93#ibcon#end of sib2, iclass 37, count 0 2006.196.07:52:00.93#ibcon#*after write, iclass 37, count 0 2006.196.07:52:00.93#ibcon#*before return 0, iclass 37, count 0 2006.196.07:52:00.93#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.196.07:52:00.93#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.196.07:52:00.93#ibcon#about to clear, iclass 37 cls_cnt 0 2006.196.07:52:00.93#ibcon#cleared, iclass 37 cls_cnt 0 2006.196.07:52:00.93$vc4f8/vb=2,4 2006.196.07:52:00.93#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.196.07:52:00.93#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.196.07:52:00.93#ibcon#ireg 11 cls_cnt 2 2006.196.07:52:00.93#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.196.07:52:00.98#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.196.07:52:00.98#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.196.07:52:00.98#ibcon#enter wrdev, iclass 39, count 2 2006.196.07:52:00.98#ibcon#first serial, iclass 39, count 2 2006.196.07:52:00.98#ibcon#enter sib2, iclass 39, count 2 2006.196.07:52:00.98#ibcon#flushed, iclass 39, count 2 2006.196.07:52:00.98#ibcon#about to write, iclass 39, count 2 2006.196.07:52:00.98#ibcon#wrote, iclass 39, count 2 2006.196.07:52:00.98#ibcon#about to read 3, iclass 39, count 2 2006.196.07:52:01.00#ibcon#read 3, iclass 39, count 2 2006.196.07:52:01.00#ibcon#about to read 4, iclass 39, count 2 2006.196.07:52:01.00#ibcon#read 4, iclass 39, count 2 2006.196.07:52:01.00#ibcon#about to read 5, iclass 39, count 2 2006.196.07:52:01.00#ibcon#read 5, iclass 39, count 2 2006.196.07:52:01.00#ibcon#about to read 6, iclass 39, count 2 2006.196.07:52:01.00#ibcon#read 6, iclass 39, count 2 2006.196.07:52:01.00#ibcon#end of sib2, iclass 39, count 2 2006.196.07:52:01.00#ibcon#*mode == 0, iclass 39, count 2 2006.196.07:52:01.00#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.196.07:52:01.00#ibcon#[27=AT02-04\r\n] 2006.196.07:52:01.00#ibcon#*before write, iclass 39, count 2 2006.196.07:52:01.00#ibcon#enter sib2, iclass 39, count 2 2006.196.07:52:01.00#ibcon#flushed, iclass 39, count 2 2006.196.07:52:01.00#ibcon#about to write, iclass 39, count 2 2006.196.07:52:01.00#ibcon#wrote, iclass 39, count 2 2006.196.07:52:01.00#ibcon#about to read 3, iclass 39, count 2 2006.196.07:52:01.03#ibcon#read 3, iclass 39, count 2 2006.196.07:52:01.03#ibcon#about to read 4, iclass 39, count 2 2006.196.07:52:01.03#ibcon#read 4, iclass 39, count 2 2006.196.07:52:01.03#ibcon#about to read 5, iclass 39, count 2 2006.196.07:52:01.03#ibcon#read 5, iclass 39, count 2 2006.196.07:52:01.03#ibcon#about to read 6, iclass 39, count 2 2006.196.07:52:01.03#ibcon#read 6, iclass 39, count 2 2006.196.07:52:01.03#ibcon#end of sib2, iclass 39, count 2 2006.196.07:52:01.03#ibcon#*after write, iclass 39, count 2 2006.196.07:52:01.03#ibcon#*before return 0, iclass 39, count 2 2006.196.07:52:01.03#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.196.07:52:01.03#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.196.07:52:01.03#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.196.07:52:01.03#ibcon#ireg 7 cls_cnt 0 2006.196.07:52:01.03#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.196.07:52:01.15#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.196.07:52:01.15#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.196.07:52:01.15#ibcon#enter wrdev, iclass 39, count 0 2006.196.07:52:01.15#ibcon#first serial, iclass 39, count 0 2006.196.07:52:01.15#ibcon#enter sib2, iclass 39, count 0 2006.196.07:52:01.15#ibcon#flushed, iclass 39, count 0 2006.196.07:52:01.15#ibcon#about to write, iclass 39, count 0 2006.196.07:52:01.15#ibcon#wrote, iclass 39, count 0 2006.196.07:52:01.15#ibcon#about to read 3, iclass 39, count 0 2006.196.07:52:01.17#ibcon#read 3, iclass 39, count 0 2006.196.07:52:01.17#ibcon#about to read 4, iclass 39, count 0 2006.196.07:52:01.17#ibcon#read 4, iclass 39, count 0 2006.196.07:52:01.17#ibcon#about to read 5, iclass 39, count 0 2006.196.07:52:01.17#ibcon#read 5, iclass 39, count 0 2006.196.07:52:01.17#ibcon#about to read 6, iclass 39, count 0 2006.196.07:52:01.17#ibcon#read 6, iclass 39, count 0 2006.196.07:52:01.17#ibcon#end of sib2, iclass 39, count 0 2006.196.07:52:01.17#ibcon#*mode == 0, iclass 39, count 0 2006.196.07:52:01.17#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.196.07:52:01.17#ibcon#[27=USB\r\n] 2006.196.07:52:01.17#ibcon#*before write, iclass 39, count 0 2006.196.07:52:01.17#ibcon#enter sib2, iclass 39, count 0 2006.196.07:52:01.17#ibcon#flushed, iclass 39, count 0 2006.196.07:52:01.17#ibcon#about to write, iclass 39, count 0 2006.196.07:52:01.17#ibcon#wrote, iclass 39, count 0 2006.196.07:52:01.17#ibcon#about to read 3, iclass 39, count 0 2006.196.07:52:01.20#ibcon#read 3, iclass 39, count 0 2006.196.07:52:01.20#ibcon#about to read 4, iclass 39, count 0 2006.196.07:52:01.20#ibcon#read 4, iclass 39, count 0 2006.196.07:52:01.20#ibcon#about to read 5, iclass 39, count 0 2006.196.07:52:01.20#ibcon#read 5, iclass 39, count 0 2006.196.07:52:01.20#ibcon#about to read 6, iclass 39, count 0 2006.196.07:52:01.20#ibcon#read 6, iclass 39, count 0 2006.196.07:52:01.20#ibcon#end of sib2, iclass 39, count 0 2006.196.07:52:01.20#ibcon#*after write, iclass 39, count 0 2006.196.07:52:01.20#ibcon#*before return 0, iclass 39, count 0 2006.196.07:52:01.20#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.196.07:52:01.20#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.196.07:52:01.20#ibcon#about to clear, iclass 39 cls_cnt 0 2006.196.07:52:01.20#ibcon#cleared, iclass 39 cls_cnt 0 2006.196.07:52:01.20$vc4f8/vblo=3,656.99 2006.196.07:52:01.20#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.196.07:52:01.20#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.196.07:52:01.20#ibcon#ireg 17 cls_cnt 0 2006.196.07:52:01.20#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.196.07:52:01.20#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.196.07:52:01.20#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.196.07:52:01.20#ibcon#enter wrdev, iclass 3, count 0 2006.196.07:52:01.20#ibcon#first serial, iclass 3, count 0 2006.196.07:52:01.20#ibcon#enter sib2, iclass 3, count 0 2006.196.07:52:01.20#ibcon#flushed, iclass 3, count 0 2006.196.07:52:01.20#ibcon#about to write, iclass 3, count 0 2006.196.07:52:01.20#ibcon#wrote, iclass 3, count 0 2006.196.07:52:01.20#ibcon#about to read 3, iclass 3, count 0 2006.196.07:52:01.22#ibcon#read 3, iclass 3, count 0 2006.196.07:52:01.22#ibcon#about to read 4, iclass 3, count 0 2006.196.07:52:01.22#ibcon#read 4, iclass 3, count 0 2006.196.07:52:01.22#ibcon#about to read 5, iclass 3, count 0 2006.196.07:52:01.22#ibcon#read 5, iclass 3, count 0 2006.196.07:52:01.22#ibcon#about to read 6, iclass 3, count 0 2006.196.07:52:01.22#ibcon#read 6, iclass 3, count 0 2006.196.07:52:01.22#ibcon#end of sib2, iclass 3, count 0 2006.196.07:52:01.22#ibcon#*mode == 0, iclass 3, count 0 2006.196.07:52:01.22#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.196.07:52:01.22#ibcon#[28=FRQ=03,656.99\r\n] 2006.196.07:52:01.22#ibcon#*before write, iclass 3, count 0 2006.196.07:52:01.22#ibcon#enter sib2, iclass 3, count 0 2006.196.07:52:01.22#ibcon#flushed, iclass 3, count 0 2006.196.07:52:01.22#ibcon#about to write, iclass 3, count 0 2006.196.07:52:01.22#ibcon#wrote, iclass 3, count 0 2006.196.07:52:01.22#ibcon#about to read 3, iclass 3, count 0 2006.196.07:52:01.26#ibcon#read 3, iclass 3, count 0 2006.196.07:52:01.26#ibcon#about to read 4, iclass 3, count 0 2006.196.07:52:01.26#ibcon#read 4, iclass 3, count 0 2006.196.07:52:01.26#ibcon#about to read 5, iclass 3, count 0 2006.196.07:52:01.26#ibcon#read 5, iclass 3, count 0 2006.196.07:52:01.26#ibcon#about to read 6, iclass 3, count 0 2006.196.07:52:01.26#ibcon#read 6, iclass 3, count 0 2006.196.07:52:01.26#ibcon#end of sib2, iclass 3, count 0 2006.196.07:52:01.26#ibcon#*after write, iclass 3, count 0 2006.196.07:52:01.26#ibcon#*before return 0, iclass 3, count 0 2006.196.07:52:01.26#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.196.07:52:01.26#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.196.07:52:01.26#ibcon#about to clear, iclass 3 cls_cnt 0 2006.196.07:52:01.26#ibcon#cleared, iclass 3 cls_cnt 0 2006.196.07:52:01.26$vc4f8/vb=3,4 2006.196.07:52:01.26#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.196.07:52:01.26#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.196.07:52:01.26#ibcon#ireg 11 cls_cnt 2 2006.196.07:52:01.26#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.196.07:52:01.32#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.196.07:52:01.32#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.196.07:52:01.32#ibcon#enter wrdev, iclass 5, count 2 2006.196.07:52:01.32#ibcon#first serial, iclass 5, count 2 2006.196.07:52:01.32#ibcon#enter sib2, iclass 5, count 2 2006.196.07:52:01.32#ibcon#flushed, iclass 5, count 2 2006.196.07:52:01.32#ibcon#about to write, iclass 5, count 2 2006.196.07:52:01.32#ibcon#wrote, iclass 5, count 2 2006.196.07:52:01.32#ibcon#about to read 3, iclass 5, count 2 2006.196.07:52:01.34#ibcon#read 3, iclass 5, count 2 2006.196.07:52:01.34#ibcon#about to read 4, iclass 5, count 2 2006.196.07:52:01.34#ibcon#read 4, iclass 5, count 2 2006.196.07:52:01.34#ibcon#about to read 5, iclass 5, count 2 2006.196.07:52:01.34#ibcon#read 5, iclass 5, count 2 2006.196.07:52:01.34#ibcon#about to read 6, iclass 5, count 2 2006.196.07:52:01.34#ibcon#read 6, iclass 5, count 2 2006.196.07:52:01.34#ibcon#end of sib2, iclass 5, count 2 2006.196.07:52:01.34#ibcon#*mode == 0, iclass 5, count 2 2006.196.07:52:01.34#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.196.07:52:01.34#ibcon#[27=AT03-04\r\n] 2006.196.07:52:01.34#ibcon#*before write, iclass 5, count 2 2006.196.07:52:01.34#ibcon#enter sib2, iclass 5, count 2 2006.196.07:52:01.34#ibcon#flushed, iclass 5, count 2 2006.196.07:52:01.34#ibcon#about to write, iclass 5, count 2 2006.196.07:52:01.34#ibcon#wrote, iclass 5, count 2 2006.196.07:52:01.34#ibcon#about to read 3, iclass 5, count 2 2006.196.07:52:01.37#ibcon#read 3, iclass 5, count 2 2006.196.07:52:01.37#ibcon#about to read 4, iclass 5, count 2 2006.196.07:52:01.37#ibcon#read 4, iclass 5, count 2 2006.196.07:52:01.37#ibcon#about to read 5, iclass 5, count 2 2006.196.07:52:01.37#ibcon#read 5, iclass 5, count 2 2006.196.07:52:01.37#ibcon#about to read 6, iclass 5, count 2 2006.196.07:52:01.37#ibcon#read 6, iclass 5, count 2 2006.196.07:52:01.37#ibcon#end of sib2, iclass 5, count 2 2006.196.07:52:01.37#ibcon#*after write, iclass 5, count 2 2006.196.07:52:01.37#ibcon#*before return 0, iclass 5, count 2 2006.196.07:52:01.37#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.196.07:52:01.37#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.196.07:52:01.37#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.196.07:52:01.37#ibcon#ireg 7 cls_cnt 0 2006.196.07:52:01.37#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.196.07:52:01.49#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.196.07:52:01.49#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.196.07:52:01.49#ibcon#enter wrdev, iclass 5, count 0 2006.196.07:52:01.49#ibcon#first serial, iclass 5, count 0 2006.196.07:52:01.49#ibcon#enter sib2, iclass 5, count 0 2006.196.07:52:01.49#ibcon#flushed, iclass 5, count 0 2006.196.07:52:01.49#ibcon#about to write, iclass 5, count 0 2006.196.07:52:01.49#ibcon#wrote, iclass 5, count 0 2006.196.07:52:01.49#ibcon#about to read 3, iclass 5, count 0 2006.196.07:52:01.51#ibcon#read 3, iclass 5, count 0 2006.196.07:52:01.51#ibcon#about to read 4, iclass 5, count 0 2006.196.07:52:01.51#ibcon#read 4, iclass 5, count 0 2006.196.07:52:01.51#ibcon#about to read 5, iclass 5, count 0 2006.196.07:52:01.51#ibcon#read 5, iclass 5, count 0 2006.196.07:52:01.51#ibcon#about to read 6, iclass 5, count 0 2006.196.07:52:01.51#ibcon#read 6, iclass 5, count 0 2006.196.07:52:01.51#ibcon#end of sib2, iclass 5, count 0 2006.196.07:52:01.51#ibcon#*mode == 0, iclass 5, count 0 2006.196.07:52:01.51#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.196.07:52:01.51#ibcon#[27=USB\r\n] 2006.196.07:52:01.51#ibcon#*before write, iclass 5, count 0 2006.196.07:52:01.51#ibcon#enter sib2, iclass 5, count 0 2006.196.07:52:01.51#ibcon#flushed, iclass 5, count 0 2006.196.07:52:01.51#ibcon#about to write, iclass 5, count 0 2006.196.07:52:01.51#ibcon#wrote, iclass 5, count 0 2006.196.07:52:01.51#ibcon#about to read 3, iclass 5, count 0 2006.196.07:52:01.54#ibcon#read 3, iclass 5, count 0 2006.196.07:52:01.54#ibcon#about to read 4, iclass 5, count 0 2006.196.07:52:01.54#ibcon#read 4, iclass 5, count 0 2006.196.07:52:01.54#ibcon#about to read 5, iclass 5, count 0 2006.196.07:52:01.54#ibcon#read 5, iclass 5, count 0 2006.196.07:52:01.54#ibcon#about to read 6, iclass 5, count 0 2006.196.07:52:01.54#ibcon#read 6, iclass 5, count 0 2006.196.07:52:01.54#ibcon#end of sib2, iclass 5, count 0 2006.196.07:52:01.54#ibcon#*after write, iclass 5, count 0 2006.196.07:52:01.54#ibcon#*before return 0, iclass 5, count 0 2006.196.07:52:01.54#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.196.07:52:01.54#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.196.07:52:01.54#ibcon#about to clear, iclass 5 cls_cnt 0 2006.196.07:52:01.54#ibcon#cleared, iclass 5 cls_cnt 0 2006.196.07:52:01.54$vc4f8/vblo=4,712.99 2006.196.07:52:01.54#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.196.07:52:01.54#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.196.07:52:01.54#ibcon#ireg 17 cls_cnt 0 2006.196.07:52:01.54#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.196.07:52:01.54#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.196.07:52:01.54#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.196.07:52:01.54#ibcon#enter wrdev, iclass 7, count 0 2006.196.07:52:01.54#ibcon#first serial, iclass 7, count 0 2006.196.07:52:01.54#ibcon#enter sib2, iclass 7, count 0 2006.196.07:52:01.54#ibcon#flushed, iclass 7, count 0 2006.196.07:52:01.54#ibcon#about to write, iclass 7, count 0 2006.196.07:52:01.54#ibcon#wrote, iclass 7, count 0 2006.196.07:52:01.54#ibcon#about to read 3, iclass 7, count 0 2006.196.07:52:01.56#ibcon#read 3, iclass 7, count 0 2006.196.07:52:01.56#ibcon#about to read 4, iclass 7, count 0 2006.196.07:52:01.56#ibcon#read 4, iclass 7, count 0 2006.196.07:52:01.56#ibcon#about to read 5, iclass 7, count 0 2006.196.07:52:01.56#ibcon#read 5, iclass 7, count 0 2006.196.07:52:01.56#ibcon#about to read 6, iclass 7, count 0 2006.196.07:52:01.56#ibcon#read 6, iclass 7, count 0 2006.196.07:52:01.56#ibcon#end of sib2, iclass 7, count 0 2006.196.07:52:01.56#ibcon#*mode == 0, iclass 7, count 0 2006.196.07:52:01.56#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.196.07:52:01.56#ibcon#[28=FRQ=04,712.99\r\n] 2006.196.07:52:01.56#ibcon#*before write, iclass 7, count 0 2006.196.07:52:01.56#ibcon#enter sib2, iclass 7, count 0 2006.196.07:52:01.56#ibcon#flushed, iclass 7, count 0 2006.196.07:52:01.56#ibcon#about to write, iclass 7, count 0 2006.196.07:52:01.56#ibcon#wrote, iclass 7, count 0 2006.196.07:52:01.56#ibcon#about to read 3, iclass 7, count 0 2006.196.07:52:01.60#ibcon#read 3, iclass 7, count 0 2006.196.07:52:01.60#ibcon#about to read 4, iclass 7, count 0 2006.196.07:52:01.60#ibcon#read 4, iclass 7, count 0 2006.196.07:52:01.60#ibcon#about to read 5, iclass 7, count 0 2006.196.07:52:01.60#ibcon#read 5, iclass 7, count 0 2006.196.07:52:01.60#ibcon#about to read 6, iclass 7, count 0 2006.196.07:52:01.60#ibcon#read 6, iclass 7, count 0 2006.196.07:52:01.60#ibcon#end of sib2, iclass 7, count 0 2006.196.07:52:01.60#ibcon#*after write, iclass 7, count 0 2006.196.07:52:01.60#ibcon#*before return 0, iclass 7, count 0 2006.196.07:52:01.60#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.196.07:52:01.60#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.196.07:52:01.60#ibcon#about to clear, iclass 7 cls_cnt 0 2006.196.07:52:01.60#ibcon#cleared, iclass 7 cls_cnt 0 2006.196.07:52:01.60$vc4f8/vb=4,4 2006.196.07:52:01.60#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.196.07:52:01.60#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.196.07:52:01.60#ibcon#ireg 11 cls_cnt 2 2006.196.07:52:01.60#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.196.07:52:01.66#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.196.07:52:01.66#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.196.07:52:01.66#ibcon#enter wrdev, iclass 11, count 2 2006.196.07:52:01.66#ibcon#first serial, iclass 11, count 2 2006.196.07:52:01.66#ibcon#enter sib2, iclass 11, count 2 2006.196.07:52:01.66#ibcon#flushed, iclass 11, count 2 2006.196.07:52:01.66#ibcon#about to write, iclass 11, count 2 2006.196.07:52:01.66#ibcon#wrote, iclass 11, count 2 2006.196.07:52:01.66#ibcon#about to read 3, iclass 11, count 2 2006.196.07:52:01.68#ibcon#read 3, iclass 11, count 2 2006.196.07:52:01.68#ibcon#about to read 4, iclass 11, count 2 2006.196.07:52:01.68#ibcon#read 4, iclass 11, count 2 2006.196.07:52:01.68#ibcon#about to read 5, iclass 11, count 2 2006.196.07:52:01.68#ibcon#read 5, iclass 11, count 2 2006.196.07:52:01.68#ibcon#about to read 6, iclass 11, count 2 2006.196.07:52:01.68#ibcon#read 6, iclass 11, count 2 2006.196.07:52:01.68#ibcon#end of sib2, iclass 11, count 2 2006.196.07:52:01.68#ibcon#*mode == 0, iclass 11, count 2 2006.196.07:52:01.68#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.196.07:52:01.68#ibcon#[27=AT04-04\r\n] 2006.196.07:52:01.68#ibcon#*before write, iclass 11, count 2 2006.196.07:52:01.68#ibcon#enter sib2, iclass 11, count 2 2006.196.07:52:01.68#ibcon#flushed, iclass 11, count 2 2006.196.07:52:01.68#ibcon#about to write, iclass 11, count 2 2006.196.07:52:01.68#ibcon#wrote, iclass 11, count 2 2006.196.07:52:01.68#ibcon#about to read 3, iclass 11, count 2 2006.196.07:52:01.71#ibcon#read 3, iclass 11, count 2 2006.196.07:52:01.71#ibcon#about to read 4, iclass 11, count 2 2006.196.07:52:01.71#ibcon#read 4, iclass 11, count 2 2006.196.07:52:01.71#ibcon#about to read 5, iclass 11, count 2 2006.196.07:52:01.71#ibcon#read 5, iclass 11, count 2 2006.196.07:52:01.71#ibcon#about to read 6, iclass 11, count 2 2006.196.07:52:01.71#ibcon#read 6, iclass 11, count 2 2006.196.07:52:01.71#ibcon#end of sib2, iclass 11, count 2 2006.196.07:52:01.71#ibcon#*after write, iclass 11, count 2 2006.196.07:52:01.71#ibcon#*before return 0, iclass 11, count 2 2006.196.07:52:01.71#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.196.07:52:01.71#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.196.07:52:01.71#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.196.07:52:01.71#ibcon#ireg 7 cls_cnt 0 2006.196.07:52:01.71#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.196.07:52:01.83#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.196.07:52:01.83#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.196.07:52:01.83#ibcon#enter wrdev, iclass 11, count 0 2006.196.07:52:01.83#ibcon#first serial, iclass 11, count 0 2006.196.07:52:01.83#ibcon#enter sib2, iclass 11, count 0 2006.196.07:52:01.83#ibcon#flushed, iclass 11, count 0 2006.196.07:52:01.83#ibcon#about to write, iclass 11, count 0 2006.196.07:52:01.83#ibcon#wrote, iclass 11, count 0 2006.196.07:52:01.83#ibcon#about to read 3, iclass 11, count 0 2006.196.07:52:01.85#ibcon#read 3, iclass 11, count 0 2006.196.07:52:01.85#ibcon#about to read 4, iclass 11, count 0 2006.196.07:52:01.85#ibcon#read 4, iclass 11, count 0 2006.196.07:52:01.85#ibcon#about to read 5, iclass 11, count 0 2006.196.07:52:01.85#ibcon#read 5, iclass 11, count 0 2006.196.07:52:01.85#ibcon#about to read 6, iclass 11, count 0 2006.196.07:52:01.85#ibcon#read 6, iclass 11, count 0 2006.196.07:52:01.85#ibcon#end of sib2, iclass 11, count 0 2006.196.07:52:01.85#ibcon#*mode == 0, iclass 11, count 0 2006.196.07:52:01.85#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.196.07:52:01.85#ibcon#[27=USB\r\n] 2006.196.07:52:01.85#ibcon#*before write, iclass 11, count 0 2006.196.07:52:01.85#ibcon#enter sib2, iclass 11, count 0 2006.196.07:52:01.85#ibcon#flushed, iclass 11, count 0 2006.196.07:52:01.85#ibcon#about to write, iclass 11, count 0 2006.196.07:52:01.85#ibcon#wrote, iclass 11, count 0 2006.196.07:52:01.85#ibcon#about to read 3, iclass 11, count 0 2006.196.07:52:01.88#ibcon#read 3, iclass 11, count 0 2006.196.07:52:01.88#ibcon#about to read 4, iclass 11, count 0 2006.196.07:52:01.88#ibcon#read 4, iclass 11, count 0 2006.196.07:52:01.88#ibcon#about to read 5, iclass 11, count 0 2006.196.07:52:01.88#ibcon#read 5, iclass 11, count 0 2006.196.07:52:01.88#ibcon#about to read 6, iclass 11, count 0 2006.196.07:52:01.88#ibcon#read 6, iclass 11, count 0 2006.196.07:52:01.88#ibcon#end of sib2, iclass 11, count 0 2006.196.07:52:01.88#ibcon#*after write, iclass 11, count 0 2006.196.07:52:01.88#ibcon#*before return 0, iclass 11, count 0 2006.196.07:52:01.88#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.196.07:52:01.88#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.196.07:52:01.88#ibcon#about to clear, iclass 11 cls_cnt 0 2006.196.07:52:01.88#ibcon#cleared, iclass 11 cls_cnt 0 2006.196.07:52:01.88$vc4f8/vblo=5,744.99 2006.196.07:52:01.88#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.196.07:52:01.88#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.196.07:52:01.88#ibcon#ireg 17 cls_cnt 0 2006.196.07:52:01.88#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.196.07:52:01.88#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.196.07:52:01.88#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.196.07:52:01.88#ibcon#enter wrdev, iclass 13, count 0 2006.196.07:52:01.88#ibcon#first serial, iclass 13, count 0 2006.196.07:52:01.88#ibcon#enter sib2, iclass 13, count 0 2006.196.07:52:01.88#ibcon#flushed, iclass 13, count 0 2006.196.07:52:01.88#ibcon#about to write, iclass 13, count 0 2006.196.07:52:01.88#ibcon#wrote, iclass 13, count 0 2006.196.07:52:01.88#ibcon#about to read 3, iclass 13, count 0 2006.196.07:52:01.90#ibcon#read 3, iclass 13, count 0 2006.196.07:52:01.90#ibcon#about to read 4, iclass 13, count 0 2006.196.07:52:01.90#ibcon#read 4, iclass 13, count 0 2006.196.07:52:01.90#ibcon#about to read 5, iclass 13, count 0 2006.196.07:52:01.90#ibcon#read 5, iclass 13, count 0 2006.196.07:52:01.90#ibcon#about to read 6, iclass 13, count 0 2006.196.07:52:01.90#ibcon#read 6, iclass 13, count 0 2006.196.07:52:01.90#ibcon#end of sib2, iclass 13, count 0 2006.196.07:52:01.90#ibcon#*mode == 0, iclass 13, count 0 2006.196.07:52:01.90#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.196.07:52:01.90#ibcon#[28=FRQ=05,744.99\r\n] 2006.196.07:52:01.90#ibcon#*before write, iclass 13, count 0 2006.196.07:52:01.90#ibcon#enter sib2, iclass 13, count 0 2006.196.07:52:01.90#ibcon#flushed, iclass 13, count 0 2006.196.07:52:01.90#ibcon#about to write, iclass 13, count 0 2006.196.07:52:01.90#ibcon#wrote, iclass 13, count 0 2006.196.07:52:01.90#ibcon#about to read 3, iclass 13, count 0 2006.196.07:52:01.95#ibcon#read 3, iclass 13, count 0 2006.196.07:52:01.95#ibcon#about to read 4, iclass 13, count 0 2006.196.07:52:01.95#ibcon#read 4, iclass 13, count 0 2006.196.07:52:01.95#ibcon#about to read 5, iclass 13, count 0 2006.196.07:52:01.95#ibcon#read 5, iclass 13, count 0 2006.196.07:52:01.95#ibcon#about to read 6, iclass 13, count 0 2006.196.07:52:01.95#ibcon#read 6, iclass 13, count 0 2006.196.07:52:01.95#ibcon#end of sib2, iclass 13, count 0 2006.196.07:52:01.95#ibcon#*after write, iclass 13, count 0 2006.196.07:52:01.95#ibcon#*before return 0, iclass 13, count 0 2006.196.07:52:01.95#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.196.07:52:01.95#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.196.07:52:01.95#ibcon#about to clear, iclass 13 cls_cnt 0 2006.196.07:52:01.95#ibcon#cleared, iclass 13 cls_cnt 0 2006.196.07:52:01.95$vc4f8/vb=5,4 2006.196.07:52:01.95#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.196.07:52:01.95#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.196.07:52:01.95#ibcon#ireg 11 cls_cnt 2 2006.196.07:52:01.95#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.196.07:52:02.00#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.196.07:52:02.00#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.196.07:52:02.00#ibcon#enter wrdev, iclass 15, count 2 2006.196.07:52:02.00#ibcon#first serial, iclass 15, count 2 2006.196.07:52:02.00#ibcon#enter sib2, iclass 15, count 2 2006.196.07:52:02.00#ibcon#flushed, iclass 15, count 2 2006.196.07:52:02.00#ibcon#about to write, iclass 15, count 2 2006.196.07:52:02.00#ibcon#wrote, iclass 15, count 2 2006.196.07:52:02.00#ibcon#about to read 3, iclass 15, count 2 2006.196.07:52:02.02#ibcon#read 3, iclass 15, count 2 2006.196.07:52:02.02#ibcon#about to read 4, iclass 15, count 2 2006.196.07:52:02.02#ibcon#read 4, iclass 15, count 2 2006.196.07:52:02.02#ibcon#about to read 5, iclass 15, count 2 2006.196.07:52:02.02#ibcon#read 5, iclass 15, count 2 2006.196.07:52:02.02#ibcon#about to read 6, iclass 15, count 2 2006.196.07:52:02.02#ibcon#read 6, iclass 15, count 2 2006.196.07:52:02.02#ibcon#end of sib2, iclass 15, count 2 2006.196.07:52:02.02#ibcon#*mode == 0, iclass 15, count 2 2006.196.07:52:02.02#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.196.07:52:02.02#ibcon#[27=AT05-04\r\n] 2006.196.07:52:02.02#ibcon#*before write, iclass 15, count 2 2006.196.07:52:02.02#ibcon#enter sib2, iclass 15, count 2 2006.196.07:52:02.02#ibcon#flushed, iclass 15, count 2 2006.196.07:52:02.02#ibcon#about to write, iclass 15, count 2 2006.196.07:52:02.02#ibcon#wrote, iclass 15, count 2 2006.196.07:52:02.02#ibcon#about to read 3, iclass 15, count 2 2006.196.07:52:02.05#ibcon#read 3, iclass 15, count 2 2006.196.07:52:02.05#ibcon#about to read 4, iclass 15, count 2 2006.196.07:52:02.05#ibcon#read 4, iclass 15, count 2 2006.196.07:52:02.05#ibcon#about to read 5, iclass 15, count 2 2006.196.07:52:02.05#ibcon#read 5, iclass 15, count 2 2006.196.07:52:02.05#ibcon#about to read 6, iclass 15, count 2 2006.196.07:52:02.05#ibcon#read 6, iclass 15, count 2 2006.196.07:52:02.05#ibcon#end of sib2, iclass 15, count 2 2006.196.07:52:02.05#ibcon#*after write, iclass 15, count 2 2006.196.07:52:02.05#ibcon#*before return 0, iclass 15, count 2 2006.196.07:52:02.05#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.196.07:52:02.05#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.196.07:52:02.05#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.196.07:52:02.05#ibcon#ireg 7 cls_cnt 0 2006.196.07:52:02.05#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.196.07:52:02.17#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.196.07:52:02.17#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.196.07:52:02.17#ibcon#enter wrdev, iclass 15, count 0 2006.196.07:52:02.17#ibcon#first serial, iclass 15, count 0 2006.196.07:52:02.17#ibcon#enter sib2, iclass 15, count 0 2006.196.07:52:02.17#ibcon#flushed, iclass 15, count 0 2006.196.07:52:02.17#ibcon#about to write, iclass 15, count 0 2006.196.07:52:02.17#ibcon#wrote, iclass 15, count 0 2006.196.07:52:02.17#ibcon#about to read 3, iclass 15, count 0 2006.196.07:52:02.19#ibcon#read 3, iclass 15, count 0 2006.196.07:52:02.19#ibcon#about to read 4, iclass 15, count 0 2006.196.07:52:02.19#ibcon#read 4, iclass 15, count 0 2006.196.07:52:02.19#ibcon#about to read 5, iclass 15, count 0 2006.196.07:52:02.19#ibcon#read 5, iclass 15, count 0 2006.196.07:52:02.19#ibcon#about to read 6, iclass 15, count 0 2006.196.07:52:02.19#ibcon#read 6, iclass 15, count 0 2006.196.07:52:02.19#ibcon#end of sib2, iclass 15, count 0 2006.196.07:52:02.19#ibcon#*mode == 0, iclass 15, count 0 2006.196.07:52:02.19#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.196.07:52:02.19#ibcon#[27=USB\r\n] 2006.196.07:52:02.19#ibcon#*before write, iclass 15, count 0 2006.196.07:52:02.19#ibcon#enter sib2, iclass 15, count 0 2006.196.07:52:02.19#ibcon#flushed, iclass 15, count 0 2006.196.07:52:02.19#ibcon#about to write, iclass 15, count 0 2006.196.07:52:02.19#ibcon#wrote, iclass 15, count 0 2006.196.07:52:02.19#ibcon#about to read 3, iclass 15, count 0 2006.196.07:52:02.22#ibcon#read 3, iclass 15, count 0 2006.196.07:52:02.22#ibcon#about to read 4, iclass 15, count 0 2006.196.07:52:02.22#ibcon#read 4, iclass 15, count 0 2006.196.07:52:02.22#ibcon#about to read 5, iclass 15, count 0 2006.196.07:52:02.22#ibcon#read 5, iclass 15, count 0 2006.196.07:52:02.22#ibcon#about to read 6, iclass 15, count 0 2006.196.07:52:02.22#ibcon#read 6, iclass 15, count 0 2006.196.07:52:02.22#ibcon#end of sib2, iclass 15, count 0 2006.196.07:52:02.22#ibcon#*after write, iclass 15, count 0 2006.196.07:52:02.22#ibcon#*before return 0, iclass 15, count 0 2006.196.07:52:02.22#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.196.07:52:02.22#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.196.07:52:02.22#ibcon#about to clear, iclass 15 cls_cnt 0 2006.196.07:52:02.22#ibcon#cleared, iclass 15 cls_cnt 0 2006.196.07:52:02.22$vc4f8/vblo=6,752.99 2006.196.07:52:02.22#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.196.07:52:02.22#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.196.07:52:02.22#ibcon#ireg 17 cls_cnt 0 2006.196.07:52:02.22#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.196.07:52:02.22#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.196.07:52:02.22#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.196.07:52:02.22#ibcon#enter wrdev, iclass 17, count 0 2006.196.07:52:02.22#ibcon#first serial, iclass 17, count 0 2006.196.07:52:02.22#ibcon#enter sib2, iclass 17, count 0 2006.196.07:52:02.22#ibcon#flushed, iclass 17, count 0 2006.196.07:52:02.22#ibcon#about to write, iclass 17, count 0 2006.196.07:52:02.22#ibcon#wrote, iclass 17, count 0 2006.196.07:52:02.22#ibcon#about to read 3, iclass 17, count 0 2006.196.07:52:02.24#ibcon#read 3, iclass 17, count 0 2006.196.07:52:02.24#ibcon#about to read 4, iclass 17, count 0 2006.196.07:52:02.24#ibcon#read 4, iclass 17, count 0 2006.196.07:52:02.24#ibcon#about to read 5, iclass 17, count 0 2006.196.07:52:02.24#ibcon#read 5, iclass 17, count 0 2006.196.07:52:02.24#ibcon#about to read 6, iclass 17, count 0 2006.196.07:52:02.24#ibcon#read 6, iclass 17, count 0 2006.196.07:52:02.24#ibcon#end of sib2, iclass 17, count 0 2006.196.07:52:02.24#ibcon#*mode == 0, iclass 17, count 0 2006.196.07:52:02.24#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.196.07:52:02.24#ibcon#[28=FRQ=06,752.99\r\n] 2006.196.07:52:02.24#ibcon#*before write, iclass 17, count 0 2006.196.07:52:02.24#ibcon#enter sib2, iclass 17, count 0 2006.196.07:52:02.24#ibcon#flushed, iclass 17, count 0 2006.196.07:52:02.24#ibcon#about to write, iclass 17, count 0 2006.196.07:52:02.24#ibcon#wrote, iclass 17, count 0 2006.196.07:52:02.24#ibcon#about to read 3, iclass 17, count 0 2006.196.07:52:02.28#ibcon#read 3, iclass 17, count 0 2006.196.07:52:02.28#ibcon#about to read 4, iclass 17, count 0 2006.196.07:52:02.28#ibcon#read 4, iclass 17, count 0 2006.196.07:52:02.28#ibcon#about to read 5, iclass 17, count 0 2006.196.07:52:02.28#ibcon#read 5, iclass 17, count 0 2006.196.07:52:02.28#ibcon#about to read 6, iclass 17, count 0 2006.196.07:52:02.28#ibcon#read 6, iclass 17, count 0 2006.196.07:52:02.28#ibcon#end of sib2, iclass 17, count 0 2006.196.07:52:02.28#ibcon#*after write, iclass 17, count 0 2006.196.07:52:02.28#ibcon#*before return 0, iclass 17, count 0 2006.196.07:52:02.28#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.196.07:52:02.28#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.196.07:52:02.28#ibcon#about to clear, iclass 17 cls_cnt 0 2006.196.07:52:02.28#ibcon#cleared, iclass 17 cls_cnt 0 2006.196.07:52:02.28$vc4f8/vb=6,4 2006.196.07:52:02.28#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.196.07:52:02.28#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.196.07:52:02.28#ibcon#ireg 11 cls_cnt 2 2006.196.07:52:02.28#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.196.07:52:02.34#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.196.07:52:02.34#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.196.07:52:02.34#ibcon#enter wrdev, iclass 19, count 2 2006.196.07:52:02.34#ibcon#first serial, iclass 19, count 2 2006.196.07:52:02.34#ibcon#enter sib2, iclass 19, count 2 2006.196.07:52:02.34#ibcon#flushed, iclass 19, count 2 2006.196.07:52:02.34#ibcon#about to write, iclass 19, count 2 2006.196.07:52:02.34#ibcon#wrote, iclass 19, count 2 2006.196.07:52:02.34#ibcon#about to read 3, iclass 19, count 2 2006.196.07:52:02.36#ibcon#read 3, iclass 19, count 2 2006.196.07:52:02.36#ibcon#about to read 4, iclass 19, count 2 2006.196.07:52:02.36#ibcon#read 4, iclass 19, count 2 2006.196.07:52:02.36#ibcon#about to read 5, iclass 19, count 2 2006.196.07:52:02.36#ibcon#read 5, iclass 19, count 2 2006.196.07:52:02.36#ibcon#about to read 6, iclass 19, count 2 2006.196.07:52:02.36#ibcon#read 6, iclass 19, count 2 2006.196.07:52:02.36#ibcon#end of sib2, iclass 19, count 2 2006.196.07:52:02.36#ibcon#*mode == 0, iclass 19, count 2 2006.196.07:52:02.36#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.196.07:52:02.36#ibcon#[27=AT06-04\r\n] 2006.196.07:52:02.36#ibcon#*before write, iclass 19, count 2 2006.196.07:52:02.36#ibcon#enter sib2, iclass 19, count 2 2006.196.07:52:02.36#ibcon#flushed, iclass 19, count 2 2006.196.07:52:02.36#ibcon#about to write, iclass 19, count 2 2006.196.07:52:02.36#ibcon#wrote, iclass 19, count 2 2006.196.07:52:02.36#ibcon#about to read 3, iclass 19, count 2 2006.196.07:52:02.39#ibcon#read 3, iclass 19, count 2 2006.196.07:52:02.39#ibcon#about to read 4, iclass 19, count 2 2006.196.07:52:02.39#ibcon#read 4, iclass 19, count 2 2006.196.07:52:02.39#ibcon#about to read 5, iclass 19, count 2 2006.196.07:52:02.39#ibcon#read 5, iclass 19, count 2 2006.196.07:52:02.39#ibcon#about to read 6, iclass 19, count 2 2006.196.07:52:02.39#ibcon#read 6, iclass 19, count 2 2006.196.07:52:02.39#ibcon#end of sib2, iclass 19, count 2 2006.196.07:52:02.39#ibcon#*after write, iclass 19, count 2 2006.196.07:52:02.39#ibcon#*before return 0, iclass 19, count 2 2006.196.07:52:02.39#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.196.07:52:02.39#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.196.07:52:02.39#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.196.07:52:02.39#ibcon#ireg 7 cls_cnt 0 2006.196.07:52:02.39#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.196.07:52:02.51#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.196.07:52:02.51#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.196.07:52:02.51#ibcon#enter wrdev, iclass 19, count 0 2006.196.07:52:02.51#ibcon#first serial, iclass 19, count 0 2006.196.07:52:02.51#ibcon#enter sib2, iclass 19, count 0 2006.196.07:52:02.51#ibcon#flushed, iclass 19, count 0 2006.196.07:52:02.51#ibcon#about to write, iclass 19, count 0 2006.196.07:52:02.51#ibcon#wrote, iclass 19, count 0 2006.196.07:52:02.51#ibcon#about to read 3, iclass 19, count 0 2006.196.07:52:02.53#ibcon#read 3, iclass 19, count 0 2006.196.07:52:02.53#ibcon#about to read 4, iclass 19, count 0 2006.196.07:52:02.53#ibcon#read 4, iclass 19, count 0 2006.196.07:52:02.53#ibcon#about to read 5, iclass 19, count 0 2006.196.07:52:02.53#ibcon#read 5, iclass 19, count 0 2006.196.07:52:02.53#ibcon#about to read 6, iclass 19, count 0 2006.196.07:52:02.53#ibcon#read 6, iclass 19, count 0 2006.196.07:52:02.53#ibcon#end of sib2, iclass 19, count 0 2006.196.07:52:02.53#ibcon#*mode == 0, iclass 19, count 0 2006.196.07:52:02.53#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.196.07:52:02.53#ibcon#[27=USB\r\n] 2006.196.07:52:02.53#ibcon#*before write, iclass 19, count 0 2006.196.07:52:02.53#ibcon#enter sib2, iclass 19, count 0 2006.196.07:52:02.53#ibcon#flushed, iclass 19, count 0 2006.196.07:52:02.53#ibcon#about to write, iclass 19, count 0 2006.196.07:52:02.53#ibcon#wrote, iclass 19, count 0 2006.196.07:52:02.53#ibcon#about to read 3, iclass 19, count 0 2006.196.07:52:02.56#ibcon#read 3, iclass 19, count 0 2006.196.07:52:02.56#ibcon#about to read 4, iclass 19, count 0 2006.196.07:52:02.56#ibcon#read 4, iclass 19, count 0 2006.196.07:52:02.56#ibcon#about to read 5, iclass 19, count 0 2006.196.07:52:02.56#ibcon#read 5, iclass 19, count 0 2006.196.07:52:02.56#ibcon#about to read 6, iclass 19, count 0 2006.196.07:52:02.56#ibcon#read 6, iclass 19, count 0 2006.196.07:52:02.56#ibcon#end of sib2, iclass 19, count 0 2006.196.07:52:02.56#ibcon#*after write, iclass 19, count 0 2006.196.07:52:02.56#ibcon#*before return 0, iclass 19, count 0 2006.196.07:52:02.56#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.196.07:52:02.56#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.196.07:52:02.56#ibcon#about to clear, iclass 19 cls_cnt 0 2006.196.07:52:02.56#ibcon#cleared, iclass 19 cls_cnt 0 2006.196.07:52:02.56$vc4f8/vabw=wide 2006.196.07:52:02.56#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.196.07:52:02.56#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.196.07:52:02.56#ibcon#ireg 8 cls_cnt 0 2006.196.07:52:02.56#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.196.07:52:02.56#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.196.07:52:02.56#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.196.07:52:02.56#ibcon#enter wrdev, iclass 21, count 0 2006.196.07:52:02.56#ibcon#first serial, iclass 21, count 0 2006.196.07:52:02.56#ibcon#enter sib2, iclass 21, count 0 2006.196.07:52:02.56#ibcon#flushed, iclass 21, count 0 2006.196.07:52:02.56#ibcon#about to write, iclass 21, count 0 2006.196.07:52:02.56#ibcon#wrote, iclass 21, count 0 2006.196.07:52:02.56#ibcon#about to read 3, iclass 21, count 0 2006.196.07:52:02.58#ibcon#read 3, iclass 21, count 0 2006.196.07:52:02.58#ibcon#about to read 4, iclass 21, count 0 2006.196.07:52:02.58#ibcon#read 4, iclass 21, count 0 2006.196.07:52:02.58#ibcon#about to read 5, iclass 21, count 0 2006.196.07:52:02.58#ibcon#read 5, iclass 21, count 0 2006.196.07:52:02.58#ibcon#about to read 6, iclass 21, count 0 2006.196.07:52:02.58#ibcon#read 6, iclass 21, count 0 2006.196.07:52:02.58#ibcon#end of sib2, iclass 21, count 0 2006.196.07:52:02.58#ibcon#*mode == 0, iclass 21, count 0 2006.196.07:52:02.58#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.196.07:52:02.58#ibcon#[25=BW32\r\n] 2006.196.07:52:02.58#ibcon#*before write, iclass 21, count 0 2006.196.07:52:02.58#ibcon#enter sib2, iclass 21, count 0 2006.196.07:52:02.58#ibcon#flushed, iclass 21, count 0 2006.196.07:52:02.58#ibcon#about to write, iclass 21, count 0 2006.196.07:52:02.58#ibcon#wrote, iclass 21, count 0 2006.196.07:52:02.58#ibcon#about to read 3, iclass 21, count 0 2006.196.07:52:02.61#ibcon#read 3, iclass 21, count 0 2006.196.07:52:02.61#ibcon#about to read 4, iclass 21, count 0 2006.196.07:52:02.61#ibcon#read 4, iclass 21, count 0 2006.196.07:52:02.61#ibcon#about to read 5, iclass 21, count 0 2006.196.07:52:02.61#ibcon#read 5, iclass 21, count 0 2006.196.07:52:02.61#ibcon#about to read 6, iclass 21, count 0 2006.196.07:52:02.61#ibcon#read 6, iclass 21, count 0 2006.196.07:52:02.61#ibcon#end of sib2, iclass 21, count 0 2006.196.07:52:02.61#ibcon#*after write, iclass 21, count 0 2006.196.07:52:02.61#ibcon#*before return 0, iclass 21, count 0 2006.196.07:52:02.61#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.196.07:52:02.61#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.196.07:52:02.61#ibcon#about to clear, iclass 21 cls_cnt 0 2006.196.07:52:02.61#ibcon#cleared, iclass 21 cls_cnt 0 2006.196.07:52:02.61$vc4f8/vbbw=wide 2006.196.07:52:02.61#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.196.07:52:02.61#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.196.07:52:02.61#ibcon#ireg 8 cls_cnt 0 2006.196.07:52:02.61#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.196.07:52:02.68#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.196.07:52:02.68#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.196.07:52:02.68#ibcon#enter wrdev, iclass 23, count 0 2006.196.07:52:02.68#ibcon#first serial, iclass 23, count 0 2006.196.07:52:02.68#ibcon#enter sib2, iclass 23, count 0 2006.196.07:52:02.68#ibcon#flushed, iclass 23, count 0 2006.196.07:52:02.68#ibcon#about to write, iclass 23, count 0 2006.196.07:52:02.68#ibcon#wrote, iclass 23, count 0 2006.196.07:52:02.68#ibcon#about to read 3, iclass 23, count 0 2006.196.07:52:02.70#ibcon#read 3, iclass 23, count 0 2006.196.07:52:02.70#ibcon#about to read 4, iclass 23, count 0 2006.196.07:52:02.70#ibcon#read 4, iclass 23, count 0 2006.196.07:52:02.70#ibcon#about to read 5, iclass 23, count 0 2006.196.07:52:02.70#ibcon#read 5, iclass 23, count 0 2006.196.07:52:02.70#ibcon#about to read 6, iclass 23, count 0 2006.196.07:52:02.70#ibcon#read 6, iclass 23, count 0 2006.196.07:52:02.70#ibcon#end of sib2, iclass 23, count 0 2006.196.07:52:02.70#ibcon#*mode == 0, iclass 23, count 0 2006.196.07:52:02.70#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.196.07:52:02.70#ibcon#[27=BW32\r\n] 2006.196.07:52:02.70#ibcon#*before write, iclass 23, count 0 2006.196.07:52:02.70#ibcon#enter sib2, iclass 23, count 0 2006.196.07:52:02.70#ibcon#flushed, iclass 23, count 0 2006.196.07:52:02.70#ibcon#about to write, iclass 23, count 0 2006.196.07:52:02.70#ibcon#wrote, iclass 23, count 0 2006.196.07:52:02.70#ibcon#about to read 3, iclass 23, count 0 2006.196.07:52:02.73#ibcon#read 3, iclass 23, count 0 2006.196.07:52:02.73#ibcon#about to read 4, iclass 23, count 0 2006.196.07:52:02.73#ibcon#read 4, iclass 23, count 0 2006.196.07:52:02.73#ibcon#about to read 5, iclass 23, count 0 2006.196.07:52:02.73#ibcon#read 5, iclass 23, count 0 2006.196.07:52:02.73#ibcon#about to read 6, iclass 23, count 0 2006.196.07:52:02.73#ibcon#read 6, iclass 23, count 0 2006.196.07:52:02.73#ibcon#end of sib2, iclass 23, count 0 2006.196.07:52:02.73#ibcon#*after write, iclass 23, count 0 2006.196.07:52:02.73#ibcon#*before return 0, iclass 23, count 0 2006.196.07:52:02.73#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.196.07:52:02.73#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.196.07:52:02.73#ibcon#about to clear, iclass 23 cls_cnt 0 2006.196.07:52:02.73#ibcon#cleared, iclass 23 cls_cnt 0 2006.196.07:52:02.73$4f8m12a/ifd4f 2006.196.07:52:02.73$ifd4f/lo= 2006.196.07:52:02.73$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.196.07:52:02.73$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.196.07:52:02.73$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.196.07:52:02.73$ifd4f/patch= 2006.196.07:52:02.73$ifd4f/patch=lo1,a1,a2,a3,a4 2006.196.07:52:02.73$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.196.07:52:02.73$ifd4f/patch=lo3,a5,a6,a7,a8 2006.196.07:52:02.73$4f8m12a/"form=m,16.000,1:2 2006.196.07:52:02.73$4f8m12a/"tpicd 2006.196.07:52:02.73$4f8m12a/echo=off 2006.196.07:52:02.73$4f8m12a/xlog=off 2006.196.07:52:02.73:!2006.196.07:52:30 2006.196.07:52:17.14#trakl#Source acquired 2006.196.07:52:18.14#flagr#flagr/antenna,acquired 2006.196.07:52:30.00:preob 2006.196.07:52:31.14/onsource/TRACKING 2006.196.07:52:31.14:!2006.196.07:52:40 2006.196.07:52:40.00:data_valid=on 2006.196.07:52:40.00:midob 2006.196.07:52:40.14/onsource/TRACKING 2006.196.07:52:40.14/wx/29.64,1004.0,89 2006.196.07:52:40.30/cable/+6.3365E-03 2006.196.07:52:41.39/va/01,08,usb,yes,29,31 2006.196.07:52:41.39/va/02,07,usb,yes,29,31 2006.196.07:52:41.39/va/03,06,usb,yes,31,31 2006.196.07:52:41.39/va/04,07,usb,yes,30,32 2006.196.07:52:41.39/va/05,07,usb,yes,32,34 2006.196.07:52:41.39/va/06,06,usb,yes,31,31 2006.196.07:52:41.39/va/07,06,usb,yes,31,31 2006.196.07:52:41.39/va/08,07,usb,yes,30,29 2006.196.07:52:41.62/valo/01,532.99,yes,locked 2006.196.07:52:41.62/valo/02,572.99,yes,locked 2006.196.07:52:41.62/valo/03,672.99,yes,locked 2006.196.07:52:41.62/valo/04,832.99,yes,locked 2006.196.07:52:41.62/valo/05,652.99,yes,locked 2006.196.07:52:41.62/valo/06,772.99,yes,locked 2006.196.07:52:41.62/valo/07,832.99,yes,locked 2006.196.07:52:41.62/valo/08,852.99,yes,locked 2006.196.07:52:42.71/vb/01,04,usb,yes,29,27 2006.196.07:52:42.71/vb/02,04,usb,yes,30,32 2006.196.07:52:42.71/vb/03,04,usb,yes,27,30 2006.196.07:52:42.71/vb/04,04,usb,yes,28,28 2006.196.07:52:42.71/vb/05,04,usb,yes,26,30 2006.196.07:52:42.71/vb/06,04,usb,yes,27,30 2006.196.07:52:42.71/vb/07,04,usb,yes,29,29 2006.196.07:52:42.71/vb/08,04,usb,yes,27,30 2006.196.07:52:42.95/vblo/01,632.99,yes,locked 2006.196.07:52:42.95/vblo/02,640.99,yes,locked 2006.196.07:52:42.95/vblo/03,656.99,yes,locked 2006.196.07:52:42.95/vblo/04,712.99,yes,locked 2006.196.07:52:42.95/vblo/05,744.99,yes,locked 2006.196.07:52:42.95/vblo/06,752.99,yes,locked 2006.196.07:52:42.95/vblo/07,734.99,yes,locked 2006.196.07:52:42.95/vblo/08,744.99,yes,locked 2006.196.07:52:43.10/vabw/8 2006.196.07:52:43.25/vbbw/8 2006.196.07:52:43.36/xfe/off,on,15.2 2006.196.07:52:43.74/ifatt/23,28,28,28 2006.196.07:52:44.07/fmout-gps/S +3.34E-07 2006.196.07:52:44.11:!2006.196.07:53:40 2006.196.07:53:40.00:data_valid=off 2006.196.07:53:40.00:postob 2006.196.07:53:40.14/cable/+6.3355E-03 2006.196.07:53:40.14/wx/29.62,1004.0,89 2006.196.07:53:41.07/fmout-gps/S +3.35E-07 2006.196.07:53:41.07:scan_name=196-0754,k06196,60 2006.196.07:53:41.07:source=0955+476,095819.67,472507.8,2000.0,cw 2006.196.07:53:41.14#flagr#flagr/antenna,new-source 2006.196.07:53:42.14:checkk5 2006.196.07:53:42.51/chk_autoobs//k5ts1/ autoobs is running! 2006.196.07:53:42.88/chk_autoobs//k5ts2/ autoobs is running! 2006.196.07:53:43.26/chk_autoobs//k5ts3/ autoobs is running! 2006.196.07:53:43.63/chk_autoobs//k5ts4/ autoobs is running! 2006.196.07:53:43.99/chk_obsdata//k5ts1/T1960752??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.07:53:44.37/chk_obsdata//k5ts2/T1960752??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.07:53:44.74/chk_obsdata//k5ts3/T1960752??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.07:53:45.11/chk_obsdata//k5ts4/T1960752??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.07:53:45.79/k5log//k5ts1_log_newline 2006.196.07:53:46.49/k5log//k5ts2_log_newline 2006.196.07:53:47.18/k5log//k5ts3_log_newline 2006.196.07:53:47.86/k5log//k5ts4_log_newline 2006.196.07:53:47.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.196.07:53:47.89:4f8m12a=1 2006.196.07:53:47.89$4f8m12a/echo=on 2006.196.07:53:47.89$4f8m12a/pcalon 2006.196.07:53:47.89$pcalon/"no phase cal control is implemented here 2006.196.07:53:47.89$4f8m12a/"tpicd=stop 2006.196.07:53:47.89$4f8m12a/vc4f8 2006.196.07:53:47.89$vc4f8/valo=1,532.99 2006.196.07:53:47.89#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.196.07:53:47.89#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.196.07:53:47.89#ibcon#ireg 17 cls_cnt 0 2006.196.07:53:47.89#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.196.07:53:47.89#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.196.07:53:47.89#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.196.07:53:47.89#ibcon#enter wrdev, iclass 30, count 0 2006.196.07:53:47.89#ibcon#first serial, iclass 30, count 0 2006.196.07:53:47.89#ibcon#enter sib2, iclass 30, count 0 2006.196.07:53:47.89#ibcon#flushed, iclass 30, count 0 2006.196.07:53:47.89#ibcon#about to write, iclass 30, count 0 2006.196.07:53:47.89#ibcon#wrote, iclass 30, count 0 2006.196.07:53:47.89#ibcon#about to read 3, iclass 30, count 0 2006.196.07:53:47.91#ibcon#read 3, iclass 30, count 0 2006.196.07:53:47.91#ibcon#about to read 4, iclass 30, count 0 2006.196.07:53:47.91#ibcon#read 4, iclass 30, count 0 2006.196.07:53:47.91#ibcon#about to read 5, iclass 30, count 0 2006.196.07:53:47.91#ibcon#read 5, iclass 30, count 0 2006.196.07:53:47.91#ibcon#about to read 6, iclass 30, count 0 2006.196.07:53:47.91#ibcon#read 6, iclass 30, count 0 2006.196.07:53:47.91#ibcon#end of sib2, iclass 30, count 0 2006.196.07:53:47.91#ibcon#*mode == 0, iclass 30, count 0 2006.196.07:53:47.91#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.196.07:53:47.91#ibcon#[26=FRQ=01,532.99\r\n] 2006.196.07:53:47.91#ibcon#*before write, iclass 30, count 0 2006.196.07:53:47.91#ibcon#enter sib2, iclass 30, count 0 2006.196.07:53:47.91#ibcon#flushed, iclass 30, count 0 2006.196.07:53:47.91#ibcon#about to write, iclass 30, count 0 2006.196.07:53:47.91#ibcon#wrote, iclass 30, count 0 2006.196.07:53:47.91#ibcon#about to read 3, iclass 30, count 0 2006.196.07:53:47.96#ibcon#read 3, iclass 30, count 0 2006.196.07:53:47.96#ibcon#about to read 4, iclass 30, count 0 2006.196.07:53:47.96#ibcon#read 4, iclass 30, count 0 2006.196.07:53:47.96#ibcon#about to read 5, iclass 30, count 0 2006.196.07:53:47.96#ibcon#read 5, iclass 30, count 0 2006.196.07:53:47.96#ibcon#about to read 6, iclass 30, count 0 2006.196.07:53:47.96#ibcon#read 6, iclass 30, count 0 2006.196.07:53:47.96#ibcon#end of sib2, iclass 30, count 0 2006.196.07:53:47.96#ibcon#*after write, iclass 30, count 0 2006.196.07:53:47.96#ibcon#*before return 0, iclass 30, count 0 2006.196.07:53:47.96#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.196.07:53:47.96#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.196.07:53:47.96#ibcon#about to clear, iclass 30 cls_cnt 0 2006.196.07:53:47.96#ibcon#cleared, iclass 30 cls_cnt 0 2006.196.07:53:47.96$vc4f8/va=1,8 2006.196.07:53:47.96#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.196.07:53:47.96#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.196.07:53:47.96#ibcon#ireg 11 cls_cnt 2 2006.196.07:53:47.96#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.196.07:53:47.96#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.196.07:53:47.96#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.196.07:53:47.96#ibcon#enter wrdev, iclass 32, count 2 2006.196.07:53:47.96#ibcon#first serial, iclass 32, count 2 2006.196.07:53:47.96#ibcon#enter sib2, iclass 32, count 2 2006.196.07:53:47.96#ibcon#flushed, iclass 32, count 2 2006.196.07:53:47.96#ibcon#about to write, iclass 32, count 2 2006.196.07:53:47.96#ibcon#wrote, iclass 32, count 2 2006.196.07:53:47.96#ibcon#about to read 3, iclass 32, count 2 2006.196.07:53:47.98#ibcon#read 3, iclass 32, count 2 2006.196.07:53:47.98#ibcon#about to read 4, iclass 32, count 2 2006.196.07:53:47.98#ibcon#read 4, iclass 32, count 2 2006.196.07:53:47.98#ibcon#about to read 5, iclass 32, count 2 2006.196.07:53:47.98#ibcon#read 5, iclass 32, count 2 2006.196.07:53:47.98#ibcon#about to read 6, iclass 32, count 2 2006.196.07:53:47.98#ibcon#read 6, iclass 32, count 2 2006.196.07:53:47.98#ibcon#end of sib2, iclass 32, count 2 2006.196.07:53:47.98#ibcon#*mode == 0, iclass 32, count 2 2006.196.07:53:47.98#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.196.07:53:47.98#ibcon#[25=AT01-08\r\n] 2006.196.07:53:47.98#ibcon#*before write, iclass 32, count 2 2006.196.07:53:47.98#ibcon#enter sib2, iclass 32, count 2 2006.196.07:53:47.98#ibcon#flushed, iclass 32, count 2 2006.196.07:53:47.98#ibcon#about to write, iclass 32, count 2 2006.196.07:53:47.98#ibcon#wrote, iclass 32, count 2 2006.196.07:53:47.98#ibcon#about to read 3, iclass 32, count 2 2006.196.07:53:48.01#ibcon#read 3, iclass 32, count 2 2006.196.07:53:48.01#ibcon#about to read 4, iclass 32, count 2 2006.196.07:53:48.01#ibcon#read 4, iclass 32, count 2 2006.196.07:53:48.01#ibcon#about to read 5, iclass 32, count 2 2006.196.07:53:48.01#ibcon#read 5, iclass 32, count 2 2006.196.07:53:48.01#ibcon#about to read 6, iclass 32, count 2 2006.196.07:53:48.01#ibcon#read 6, iclass 32, count 2 2006.196.07:53:48.01#ibcon#end of sib2, iclass 32, count 2 2006.196.07:53:48.01#ibcon#*after write, iclass 32, count 2 2006.196.07:53:48.01#ibcon#*before return 0, iclass 32, count 2 2006.196.07:53:48.01#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.196.07:53:48.01#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.196.07:53:48.01#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.196.07:53:48.01#ibcon#ireg 7 cls_cnt 0 2006.196.07:53:48.01#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.196.07:53:48.13#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.196.07:53:48.13#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.196.07:53:48.13#ibcon#enter wrdev, iclass 32, count 0 2006.196.07:53:48.13#ibcon#first serial, iclass 32, count 0 2006.196.07:53:48.13#ibcon#enter sib2, iclass 32, count 0 2006.196.07:53:48.13#ibcon#flushed, iclass 32, count 0 2006.196.07:53:48.13#ibcon#about to write, iclass 32, count 0 2006.196.07:53:48.13#ibcon#wrote, iclass 32, count 0 2006.196.07:53:48.13#ibcon#about to read 3, iclass 32, count 0 2006.196.07:53:48.15#ibcon#read 3, iclass 32, count 0 2006.196.07:53:48.15#ibcon#about to read 4, iclass 32, count 0 2006.196.07:53:48.15#ibcon#read 4, iclass 32, count 0 2006.196.07:53:48.15#ibcon#about to read 5, iclass 32, count 0 2006.196.07:53:48.15#ibcon#read 5, iclass 32, count 0 2006.196.07:53:48.15#ibcon#about to read 6, iclass 32, count 0 2006.196.07:53:48.15#ibcon#read 6, iclass 32, count 0 2006.196.07:53:48.15#ibcon#end of sib2, iclass 32, count 0 2006.196.07:53:48.15#ibcon#*mode == 0, iclass 32, count 0 2006.196.07:53:48.15#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.196.07:53:48.15#ibcon#[25=USB\r\n] 2006.196.07:53:48.15#ibcon#*before write, iclass 32, count 0 2006.196.07:53:48.15#ibcon#enter sib2, iclass 32, count 0 2006.196.07:53:48.15#ibcon#flushed, iclass 32, count 0 2006.196.07:53:48.15#ibcon#about to write, iclass 32, count 0 2006.196.07:53:48.15#ibcon#wrote, iclass 32, count 0 2006.196.07:53:48.15#ibcon#about to read 3, iclass 32, count 0 2006.196.07:53:48.18#ibcon#read 3, iclass 32, count 0 2006.196.07:53:48.18#ibcon#about to read 4, iclass 32, count 0 2006.196.07:53:48.18#ibcon#read 4, iclass 32, count 0 2006.196.07:53:48.18#ibcon#about to read 5, iclass 32, count 0 2006.196.07:53:48.18#ibcon#read 5, iclass 32, count 0 2006.196.07:53:48.18#ibcon#about to read 6, iclass 32, count 0 2006.196.07:53:48.18#ibcon#read 6, iclass 32, count 0 2006.196.07:53:48.18#ibcon#end of sib2, iclass 32, count 0 2006.196.07:53:48.18#ibcon#*after write, iclass 32, count 0 2006.196.07:53:48.18#ibcon#*before return 0, iclass 32, count 0 2006.196.07:53:48.18#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.196.07:53:48.18#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.196.07:53:48.18#ibcon#about to clear, iclass 32 cls_cnt 0 2006.196.07:53:48.18#ibcon#cleared, iclass 32 cls_cnt 0 2006.196.07:53:48.18$vc4f8/valo=2,572.99 2006.196.07:53:48.18#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.196.07:53:48.18#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.196.07:53:48.18#ibcon#ireg 17 cls_cnt 0 2006.196.07:53:48.18#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.196.07:53:48.18#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.196.07:53:48.18#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.196.07:53:48.18#ibcon#enter wrdev, iclass 34, count 0 2006.196.07:53:48.18#ibcon#first serial, iclass 34, count 0 2006.196.07:53:48.18#ibcon#enter sib2, iclass 34, count 0 2006.196.07:53:48.18#ibcon#flushed, iclass 34, count 0 2006.196.07:53:48.18#ibcon#about to write, iclass 34, count 0 2006.196.07:53:48.18#ibcon#wrote, iclass 34, count 0 2006.196.07:53:48.18#ibcon#about to read 3, iclass 34, count 0 2006.196.07:53:48.20#ibcon#read 3, iclass 34, count 0 2006.196.07:53:48.20#ibcon#about to read 4, iclass 34, count 0 2006.196.07:53:48.20#ibcon#read 4, iclass 34, count 0 2006.196.07:53:48.20#ibcon#about to read 5, iclass 34, count 0 2006.196.07:53:48.20#ibcon#read 5, iclass 34, count 0 2006.196.07:53:48.20#ibcon#about to read 6, iclass 34, count 0 2006.196.07:53:48.20#ibcon#read 6, iclass 34, count 0 2006.196.07:53:48.20#ibcon#end of sib2, iclass 34, count 0 2006.196.07:53:48.20#ibcon#*mode == 0, iclass 34, count 0 2006.196.07:53:48.20#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.196.07:53:48.20#ibcon#[26=FRQ=02,572.99\r\n] 2006.196.07:53:48.20#ibcon#*before write, iclass 34, count 0 2006.196.07:53:48.20#ibcon#enter sib2, iclass 34, count 0 2006.196.07:53:48.20#ibcon#flushed, iclass 34, count 0 2006.196.07:53:48.20#ibcon#about to write, iclass 34, count 0 2006.196.07:53:48.20#ibcon#wrote, iclass 34, count 0 2006.196.07:53:48.20#ibcon#about to read 3, iclass 34, count 0 2006.196.07:53:48.25#ibcon#read 3, iclass 34, count 0 2006.196.07:53:48.25#ibcon#about to read 4, iclass 34, count 0 2006.196.07:53:48.25#ibcon#read 4, iclass 34, count 0 2006.196.07:53:48.25#ibcon#about to read 5, iclass 34, count 0 2006.196.07:53:48.25#ibcon#read 5, iclass 34, count 0 2006.196.07:53:48.25#ibcon#about to read 6, iclass 34, count 0 2006.196.07:53:48.25#ibcon#read 6, iclass 34, count 0 2006.196.07:53:48.25#ibcon#end of sib2, iclass 34, count 0 2006.196.07:53:48.25#ibcon#*after write, iclass 34, count 0 2006.196.07:53:48.25#ibcon#*before return 0, iclass 34, count 0 2006.196.07:53:48.25#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.196.07:53:48.25#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.196.07:53:48.25#ibcon#about to clear, iclass 34 cls_cnt 0 2006.196.07:53:48.25#ibcon#cleared, iclass 34 cls_cnt 0 2006.196.07:53:48.25$vc4f8/va=2,7 2006.196.07:53:48.25#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.196.07:53:48.25#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.196.07:53:48.25#ibcon#ireg 11 cls_cnt 2 2006.196.07:53:48.25#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.196.07:53:48.30#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.196.07:53:48.30#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.196.07:53:48.30#ibcon#enter wrdev, iclass 36, count 2 2006.196.07:53:48.30#ibcon#first serial, iclass 36, count 2 2006.196.07:53:48.30#ibcon#enter sib2, iclass 36, count 2 2006.196.07:53:48.30#ibcon#flushed, iclass 36, count 2 2006.196.07:53:48.30#ibcon#about to write, iclass 36, count 2 2006.196.07:53:48.30#ibcon#wrote, iclass 36, count 2 2006.196.07:53:48.30#ibcon#about to read 3, iclass 36, count 2 2006.196.07:53:48.32#ibcon#read 3, iclass 36, count 2 2006.196.07:53:48.32#ibcon#about to read 4, iclass 36, count 2 2006.196.07:53:48.32#ibcon#read 4, iclass 36, count 2 2006.196.07:53:48.32#ibcon#about to read 5, iclass 36, count 2 2006.196.07:53:48.32#ibcon#read 5, iclass 36, count 2 2006.196.07:53:48.32#ibcon#about to read 6, iclass 36, count 2 2006.196.07:53:48.32#ibcon#read 6, iclass 36, count 2 2006.196.07:53:48.32#ibcon#end of sib2, iclass 36, count 2 2006.196.07:53:48.32#ibcon#*mode == 0, iclass 36, count 2 2006.196.07:53:48.32#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.196.07:53:48.32#ibcon#[25=AT02-07\r\n] 2006.196.07:53:48.32#ibcon#*before write, iclass 36, count 2 2006.196.07:53:48.32#ibcon#enter sib2, iclass 36, count 2 2006.196.07:53:48.32#ibcon#flushed, iclass 36, count 2 2006.196.07:53:48.32#ibcon#about to write, iclass 36, count 2 2006.196.07:53:48.32#ibcon#wrote, iclass 36, count 2 2006.196.07:53:48.32#ibcon#about to read 3, iclass 36, count 2 2006.196.07:53:48.35#ibcon#read 3, iclass 36, count 2 2006.196.07:53:48.35#ibcon#about to read 4, iclass 36, count 2 2006.196.07:53:48.35#ibcon#read 4, iclass 36, count 2 2006.196.07:53:48.35#ibcon#about to read 5, iclass 36, count 2 2006.196.07:53:48.35#ibcon#read 5, iclass 36, count 2 2006.196.07:53:48.35#ibcon#about to read 6, iclass 36, count 2 2006.196.07:53:48.35#ibcon#read 6, iclass 36, count 2 2006.196.07:53:48.35#ibcon#end of sib2, iclass 36, count 2 2006.196.07:53:48.35#ibcon#*after write, iclass 36, count 2 2006.196.07:53:48.35#ibcon#*before return 0, iclass 36, count 2 2006.196.07:53:48.35#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.196.07:53:48.35#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.196.07:53:48.35#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.196.07:53:48.35#ibcon#ireg 7 cls_cnt 0 2006.196.07:53:48.35#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.196.07:53:48.47#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.196.07:53:48.47#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.196.07:53:48.47#ibcon#enter wrdev, iclass 36, count 0 2006.196.07:53:48.47#ibcon#first serial, iclass 36, count 0 2006.196.07:53:48.47#ibcon#enter sib2, iclass 36, count 0 2006.196.07:53:48.47#ibcon#flushed, iclass 36, count 0 2006.196.07:53:48.47#ibcon#about to write, iclass 36, count 0 2006.196.07:53:48.47#ibcon#wrote, iclass 36, count 0 2006.196.07:53:48.47#ibcon#about to read 3, iclass 36, count 0 2006.196.07:53:48.49#ibcon#read 3, iclass 36, count 0 2006.196.07:53:48.49#ibcon#about to read 4, iclass 36, count 0 2006.196.07:53:48.49#ibcon#read 4, iclass 36, count 0 2006.196.07:53:48.49#ibcon#about to read 5, iclass 36, count 0 2006.196.07:53:48.49#ibcon#read 5, iclass 36, count 0 2006.196.07:53:48.49#ibcon#about to read 6, iclass 36, count 0 2006.196.07:53:48.49#ibcon#read 6, iclass 36, count 0 2006.196.07:53:48.49#ibcon#end of sib2, iclass 36, count 0 2006.196.07:53:48.49#ibcon#*mode == 0, iclass 36, count 0 2006.196.07:53:48.49#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.196.07:53:48.49#ibcon#[25=USB\r\n] 2006.196.07:53:48.49#ibcon#*before write, iclass 36, count 0 2006.196.07:53:48.49#ibcon#enter sib2, iclass 36, count 0 2006.196.07:53:48.49#ibcon#flushed, iclass 36, count 0 2006.196.07:53:48.49#ibcon#about to write, iclass 36, count 0 2006.196.07:53:48.49#ibcon#wrote, iclass 36, count 0 2006.196.07:53:48.49#ibcon#about to read 3, iclass 36, count 0 2006.196.07:53:48.52#ibcon#read 3, iclass 36, count 0 2006.196.07:53:48.52#ibcon#about to read 4, iclass 36, count 0 2006.196.07:53:48.52#ibcon#read 4, iclass 36, count 0 2006.196.07:53:48.52#ibcon#about to read 5, iclass 36, count 0 2006.196.07:53:48.52#ibcon#read 5, iclass 36, count 0 2006.196.07:53:48.52#ibcon#about to read 6, iclass 36, count 0 2006.196.07:53:48.52#ibcon#read 6, iclass 36, count 0 2006.196.07:53:48.52#ibcon#end of sib2, iclass 36, count 0 2006.196.07:53:48.52#ibcon#*after write, iclass 36, count 0 2006.196.07:53:48.52#ibcon#*before return 0, iclass 36, count 0 2006.196.07:53:48.52#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.196.07:53:48.52#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.196.07:53:48.52#ibcon#about to clear, iclass 36 cls_cnt 0 2006.196.07:53:48.52#ibcon#cleared, iclass 36 cls_cnt 0 2006.196.07:53:48.52$vc4f8/valo=3,672.99 2006.196.07:53:48.52#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.196.07:53:48.52#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.196.07:53:48.52#ibcon#ireg 17 cls_cnt 0 2006.196.07:53:48.52#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.196.07:53:48.52#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.196.07:53:48.52#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.196.07:53:48.52#ibcon#enter wrdev, iclass 38, count 0 2006.196.07:53:48.52#ibcon#first serial, iclass 38, count 0 2006.196.07:53:48.52#ibcon#enter sib2, iclass 38, count 0 2006.196.07:53:48.52#ibcon#flushed, iclass 38, count 0 2006.196.07:53:48.52#ibcon#about to write, iclass 38, count 0 2006.196.07:53:48.52#ibcon#wrote, iclass 38, count 0 2006.196.07:53:48.52#ibcon#about to read 3, iclass 38, count 0 2006.196.07:53:48.54#ibcon#read 3, iclass 38, count 0 2006.196.07:53:48.54#ibcon#about to read 4, iclass 38, count 0 2006.196.07:53:48.54#ibcon#read 4, iclass 38, count 0 2006.196.07:53:48.54#ibcon#about to read 5, iclass 38, count 0 2006.196.07:53:48.54#ibcon#read 5, iclass 38, count 0 2006.196.07:53:48.54#ibcon#about to read 6, iclass 38, count 0 2006.196.07:53:48.54#ibcon#read 6, iclass 38, count 0 2006.196.07:53:48.54#ibcon#end of sib2, iclass 38, count 0 2006.196.07:53:48.54#ibcon#*mode == 0, iclass 38, count 0 2006.196.07:53:48.54#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.196.07:53:48.54#ibcon#[26=FRQ=03,672.99\r\n] 2006.196.07:53:48.54#ibcon#*before write, iclass 38, count 0 2006.196.07:53:48.54#ibcon#enter sib2, iclass 38, count 0 2006.196.07:53:48.54#ibcon#flushed, iclass 38, count 0 2006.196.07:53:48.54#ibcon#about to write, iclass 38, count 0 2006.196.07:53:48.54#ibcon#wrote, iclass 38, count 0 2006.196.07:53:48.54#ibcon#about to read 3, iclass 38, count 0 2006.196.07:53:48.59#ibcon#read 3, iclass 38, count 0 2006.196.07:53:48.59#ibcon#about to read 4, iclass 38, count 0 2006.196.07:53:48.59#ibcon#read 4, iclass 38, count 0 2006.196.07:53:48.59#ibcon#about to read 5, iclass 38, count 0 2006.196.07:53:48.59#ibcon#read 5, iclass 38, count 0 2006.196.07:53:48.59#ibcon#about to read 6, iclass 38, count 0 2006.196.07:53:48.59#ibcon#read 6, iclass 38, count 0 2006.196.07:53:48.59#ibcon#end of sib2, iclass 38, count 0 2006.196.07:53:48.59#ibcon#*after write, iclass 38, count 0 2006.196.07:53:48.59#ibcon#*before return 0, iclass 38, count 0 2006.196.07:53:48.59#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.196.07:53:48.59#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.196.07:53:48.59#ibcon#about to clear, iclass 38 cls_cnt 0 2006.196.07:53:48.59#ibcon#cleared, iclass 38 cls_cnt 0 2006.196.07:53:48.59$vc4f8/va=3,6 2006.196.07:53:48.59#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.196.07:53:48.59#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.196.07:53:48.59#ibcon#ireg 11 cls_cnt 2 2006.196.07:53:48.59#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.196.07:53:48.64#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.196.07:53:48.64#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.196.07:53:48.64#ibcon#enter wrdev, iclass 40, count 2 2006.196.07:53:48.64#ibcon#first serial, iclass 40, count 2 2006.196.07:53:48.64#ibcon#enter sib2, iclass 40, count 2 2006.196.07:53:48.64#ibcon#flushed, iclass 40, count 2 2006.196.07:53:48.64#ibcon#about to write, iclass 40, count 2 2006.196.07:53:48.64#ibcon#wrote, iclass 40, count 2 2006.196.07:53:48.64#ibcon#about to read 3, iclass 40, count 2 2006.196.07:53:48.66#ibcon#read 3, iclass 40, count 2 2006.196.07:53:48.66#ibcon#about to read 4, iclass 40, count 2 2006.196.07:53:48.66#ibcon#read 4, iclass 40, count 2 2006.196.07:53:48.66#ibcon#about to read 5, iclass 40, count 2 2006.196.07:53:48.66#ibcon#read 5, iclass 40, count 2 2006.196.07:53:48.66#ibcon#about to read 6, iclass 40, count 2 2006.196.07:53:48.66#ibcon#read 6, iclass 40, count 2 2006.196.07:53:48.66#ibcon#end of sib2, iclass 40, count 2 2006.196.07:53:48.66#ibcon#*mode == 0, iclass 40, count 2 2006.196.07:53:48.66#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.196.07:53:48.66#ibcon#[25=AT03-06\r\n] 2006.196.07:53:48.66#ibcon#*before write, iclass 40, count 2 2006.196.07:53:48.66#ibcon#enter sib2, iclass 40, count 2 2006.196.07:53:48.66#ibcon#flushed, iclass 40, count 2 2006.196.07:53:48.66#ibcon#about to write, iclass 40, count 2 2006.196.07:53:48.66#ibcon#wrote, iclass 40, count 2 2006.196.07:53:48.66#ibcon#about to read 3, iclass 40, count 2 2006.196.07:53:48.69#ibcon#read 3, iclass 40, count 2 2006.196.07:53:48.69#ibcon#about to read 4, iclass 40, count 2 2006.196.07:53:48.69#ibcon#read 4, iclass 40, count 2 2006.196.07:53:48.69#ibcon#about to read 5, iclass 40, count 2 2006.196.07:53:48.69#ibcon#read 5, iclass 40, count 2 2006.196.07:53:48.69#ibcon#about to read 6, iclass 40, count 2 2006.196.07:53:48.69#ibcon#read 6, iclass 40, count 2 2006.196.07:53:48.69#ibcon#end of sib2, iclass 40, count 2 2006.196.07:53:48.69#ibcon#*after write, iclass 40, count 2 2006.196.07:53:48.69#ibcon#*before return 0, iclass 40, count 2 2006.196.07:53:48.69#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.196.07:53:48.69#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.196.07:53:48.69#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.196.07:53:48.69#ibcon#ireg 7 cls_cnt 0 2006.196.07:53:48.69#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.196.07:53:48.78#abcon#<5=/04 3.8 6.7 29.62 891004.0\r\n> 2006.196.07:53:48.80#abcon#{5=INTERFACE CLEAR} 2006.196.07:53:48.81#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.196.07:53:48.81#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.196.07:53:48.81#ibcon#enter wrdev, iclass 40, count 0 2006.196.07:53:48.81#ibcon#first serial, iclass 40, count 0 2006.196.07:53:48.81#ibcon#enter sib2, iclass 40, count 0 2006.196.07:53:48.81#ibcon#flushed, iclass 40, count 0 2006.196.07:53:48.81#ibcon#about to write, iclass 40, count 0 2006.196.07:53:48.81#ibcon#wrote, iclass 40, count 0 2006.196.07:53:48.81#ibcon#about to read 3, iclass 40, count 0 2006.196.07:53:48.84#ibcon#read 3, iclass 40, count 0 2006.196.07:53:48.84#ibcon#about to read 4, iclass 40, count 0 2006.196.07:53:48.84#ibcon#read 4, iclass 40, count 0 2006.196.07:53:48.84#ibcon#about to read 5, iclass 40, count 0 2006.196.07:53:48.84#ibcon#read 5, iclass 40, count 0 2006.196.07:53:48.84#ibcon#about to read 6, iclass 40, count 0 2006.196.07:53:48.84#ibcon#read 6, iclass 40, count 0 2006.196.07:53:48.84#ibcon#end of sib2, iclass 40, count 0 2006.196.07:53:48.84#ibcon#*mode == 0, iclass 40, count 0 2006.196.07:53:48.84#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.196.07:53:48.84#ibcon#[25=USB\r\n] 2006.196.07:53:48.84#ibcon#*before write, iclass 40, count 0 2006.196.07:53:48.84#ibcon#enter sib2, iclass 40, count 0 2006.196.07:53:48.84#ibcon#flushed, iclass 40, count 0 2006.196.07:53:48.84#ibcon#about to write, iclass 40, count 0 2006.196.07:53:48.84#ibcon#wrote, iclass 40, count 0 2006.196.07:53:48.84#ibcon#about to read 3, iclass 40, count 0 2006.196.07:53:48.86#abcon#[5=S1D000X0/0*\r\n] 2006.196.07:53:48.87#ibcon#read 3, iclass 40, count 0 2006.196.07:53:48.87#ibcon#about to read 4, iclass 40, count 0 2006.196.07:53:48.87#ibcon#read 4, iclass 40, count 0 2006.196.07:53:48.87#ibcon#about to read 5, iclass 40, count 0 2006.196.07:53:48.87#ibcon#read 5, iclass 40, count 0 2006.196.07:53:48.87#ibcon#about to read 6, iclass 40, count 0 2006.196.07:53:48.87#ibcon#read 6, iclass 40, count 0 2006.196.07:53:48.87#ibcon#end of sib2, iclass 40, count 0 2006.196.07:53:48.87#ibcon#*after write, iclass 40, count 0 2006.196.07:53:48.87#ibcon#*before return 0, iclass 40, count 0 2006.196.07:53:48.87#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.196.07:53:48.87#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.196.07:53:48.87#ibcon#about to clear, iclass 40 cls_cnt 0 2006.196.07:53:48.87#ibcon#cleared, iclass 40 cls_cnt 0 2006.196.07:53:48.87$vc4f8/valo=4,832.99 2006.196.07:53:48.87#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.196.07:53:48.87#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.196.07:53:48.87#ibcon#ireg 17 cls_cnt 0 2006.196.07:53:48.87#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.196.07:53:48.87#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.196.07:53:48.87#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.196.07:53:48.87#ibcon#enter wrdev, iclass 10, count 0 2006.196.07:53:48.87#ibcon#first serial, iclass 10, count 0 2006.196.07:53:48.87#ibcon#enter sib2, iclass 10, count 0 2006.196.07:53:48.87#ibcon#flushed, iclass 10, count 0 2006.196.07:53:48.87#ibcon#about to write, iclass 10, count 0 2006.196.07:53:48.87#ibcon#wrote, iclass 10, count 0 2006.196.07:53:48.87#ibcon#about to read 3, iclass 10, count 0 2006.196.07:53:48.89#ibcon#read 3, iclass 10, count 0 2006.196.07:53:48.89#ibcon#about to read 4, iclass 10, count 0 2006.196.07:53:48.89#ibcon#read 4, iclass 10, count 0 2006.196.07:53:48.89#ibcon#about to read 5, iclass 10, count 0 2006.196.07:53:48.89#ibcon#read 5, iclass 10, count 0 2006.196.07:53:48.89#ibcon#about to read 6, iclass 10, count 0 2006.196.07:53:48.89#ibcon#read 6, iclass 10, count 0 2006.196.07:53:48.89#ibcon#end of sib2, iclass 10, count 0 2006.196.07:53:48.89#ibcon#*mode == 0, iclass 10, count 0 2006.196.07:53:48.89#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.196.07:53:48.89#ibcon#[26=FRQ=04,832.99\r\n] 2006.196.07:53:48.89#ibcon#*before write, iclass 10, count 0 2006.196.07:53:48.89#ibcon#enter sib2, iclass 10, count 0 2006.196.07:53:48.89#ibcon#flushed, iclass 10, count 0 2006.196.07:53:48.89#ibcon#about to write, iclass 10, count 0 2006.196.07:53:48.89#ibcon#wrote, iclass 10, count 0 2006.196.07:53:48.89#ibcon#about to read 3, iclass 10, count 0 2006.196.07:53:48.93#ibcon#read 3, iclass 10, count 0 2006.196.07:53:48.93#ibcon#about to read 4, iclass 10, count 0 2006.196.07:53:48.93#ibcon#read 4, iclass 10, count 0 2006.196.07:53:48.93#ibcon#about to read 5, iclass 10, count 0 2006.196.07:53:48.93#ibcon#read 5, iclass 10, count 0 2006.196.07:53:48.93#ibcon#about to read 6, iclass 10, count 0 2006.196.07:53:48.93#ibcon#read 6, iclass 10, count 0 2006.196.07:53:48.93#ibcon#end of sib2, iclass 10, count 0 2006.196.07:53:48.93#ibcon#*after write, iclass 10, count 0 2006.196.07:53:48.93#ibcon#*before return 0, iclass 10, count 0 2006.196.07:53:48.93#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.196.07:53:48.93#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.196.07:53:48.93#ibcon#about to clear, iclass 10 cls_cnt 0 2006.196.07:53:48.93#ibcon#cleared, iclass 10 cls_cnt 0 2006.196.07:53:48.93$vc4f8/va=4,7 2006.196.07:53:48.93#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.196.07:53:48.93#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.196.07:53:48.93#ibcon#ireg 11 cls_cnt 2 2006.196.07:53:48.93#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.196.07:53:48.99#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.196.07:53:48.99#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.196.07:53:48.99#ibcon#enter wrdev, iclass 12, count 2 2006.196.07:53:48.99#ibcon#first serial, iclass 12, count 2 2006.196.07:53:48.99#ibcon#enter sib2, iclass 12, count 2 2006.196.07:53:48.99#ibcon#flushed, iclass 12, count 2 2006.196.07:53:48.99#ibcon#about to write, iclass 12, count 2 2006.196.07:53:48.99#ibcon#wrote, iclass 12, count 2 2006.196.07:53:48.99#ibcon#about to read 3, iclass 12, count 2 2006.196.07:53:49.01#ibcon#read 3, iclass 12, count 2 2006.196.07:53:49.01#ibcon#about to read 4, iclass 12, count 2 2006.196.07:53:49.01#ibcon#read 4, iclass 12, count 2 2006.196.07:53:49.01#ibcon#about to read 5, iclass 12, count 2 2006.196.07:53:49.01#ibcon#read 5, iclass 12, count 2 2006.196.07:53:49.01#ibcon#about to read 6, iclass 12, count 2 2006.196.07:53:49.01#ibcon#read 6, iclass 12, count 2 2006.196.07:53:49.01#ibcon#end of sib2, iclass 12, count 2 2006.196.07:53:49.01#ibcon#*mode == 0, iclass 12, count 2 2006.196.07:53:49.01#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.196.07:53:49.01#ibcon#[25=AT04-07\r\n] 2006.196.07:53:49.01#ibcon#*before write, iclass 12, count 2 2006.196.07:53:49.01#ibcon#enter sib2, iclass 12, count 2 2006.196.07:53:49.01#ibcon#flushed, iclass 12, count 2 2006.196.07:53:49.01#ibcon#about to write, iclass 12, count 2 2006.196.07:53:49.01#ibcon#wrote, iclass 12, count 2 2006.196.07:53:49.01#ibcon#about to read 3, iclass 12, count 2 2006.196.07:53:49.04#ibcon#read 3, iclass 12, count 2 2006.196.07:53:49.04#ibcon#about to read 4, iclass 12, count 2 2006.196.07:53:49.04#ibcon#read 4, iclass 12, count 2 2006.196.07:53:49.04#ibcon#about to read 5, iclass 12, count 2 2006.196.07:53:49.04#ibcon#read 5, iclass 12, count 2 2006.196.07:53:49.04#ibcon#about to read 6, iclass 12, count 2 2006.196.07:53:49.04#ibcon#read 6, iclass 12, count 2 2006.196.07:53:49.04#ibcon#end of sib2, iclass 12, count 2 2006.196.07:53:49.04#ibcon#*after write, iclass 12, count 2 2006.196.07:53:49.04#ibcon#*before return 0, iclass 12, count 2 2006.196.07:53:49.04#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.196.07:53:49.04#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.196.07:53:49.04#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.196.07:53:49.04#ibcon#ireg 7 cls_cnt 0 2006.196.07:53:49.04#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.196.07:53:49.16#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.196.07:53:49.16#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.196.07:53:49.16#ibcon#enter wrdev, iclass 12, count 0 2006.196.07:53:49.16#ibcon#first serial, iclass 12, count 0 2006.196.07:53:49.16#ibcon#enter sib2, iclass 12, count 0 2006.196.07:53:49.16#ibcon#flushed, iclass 12, count 0 2006.196.07:53:49.16#ibcon#about to write, iclass 12, count 0 2006.196.07:53:49.16#ibcon#wrote, iclass 12, count 0 2006.196.07:53:49.16#ibcon#about to read 3, iclass 12, count 0 2006.196.07:53:49.18#ibcon#read 3, iclass 12, count 0 2006.196.07:53:49.18#ibcon#about to read 4, iclass 12, count 0 2006.196.07:53:49.18#ibcon#read 4, iclass 12, count 0 2006.196.07:53:49.18#ibcon#about to read 5, iclass 12, count 0 2006.196.07:53:49.18#ibcon#read 5, iclass 12, count 0 2006.196.07:53:49.18#ibcon#about to read 6, iclass 12, count 0 2006.196.07:53:49.18#ibcon#read 6, iclass 12, count 0 2006.196.07:53:49.18#ibcon#end of sib2, iclass 12, count 0 2006.196.07:53:49.18#ibcon#*mode == 0, iclass 12, count 0 2006.196.07:53:49.18#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.196.07:53:49.18#ibcon#[25=USB\r\n] 2006.196.07:53:49.18#ibcon#*before write, iclass 12, count 0 2006.196.07:53:49.18#ibcon#enter sib2, iclass 12, count 0 2006.196.07:53:49.18#ibcon#flushed, iclass 12, count 0 2006.196.07:53:49.18#ibcon#about to write, iclass 12, count 0 2006.196.07:53:49.18#ibcon#wrote, iclass 12, count 0 2006.196.07:53:49.18#ibcon#about to read 3, iclass 12, count 0 2006.196.07:53:49.21#ibcon#read 3, iclass 12, count 0 2006.196.07:53:49.21#ibcon#about to read 4, iclass 12, count 0 2006.196.07:53:49.21#ibcon#read 4, iclass 12, count 0 2006.196.07:53:49.21#ibcon#about to read 5, iclass 12, count 0 2006.196.07:53:49.21#ibcon#read 5, iclass 12, count 0 2006.196.07:53:49.21#ibcon#about to read 6, iclass 12, count 0 2006.196.07:53:49.21#ibcon#read 6, iclass 12, count 0 2006.196.07:53:49.21#ibcon#end of sib2, iclass 12, count 0 2006.196.07:53:49.21#ibcon#*after write, iclass 12, count 0 2006.196.07:53:49.21#ibcon#*before return 0, iclass 12, count 0 2006.196.07:53:49.21#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.196.07:53:49.21#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.196.07:53:49.21#ibcon#about to clear, iclass 12 cls_cnt 0 2006.196.07:53:49.21#ibcon#cleared, iclass 12 cls_cnt 0 2006.196.07:53:49.21$vc4f8/valo=5,652.99 2006.196.07:53:49.21#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.196.07:53:49.21#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.196.07:53:49.21#ibcon#ireg 17 cls_cnt 0 2006.196.07:53:49.21#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.196.07:53:49.21#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.196.07:53:49.21#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.196.07:53:49.21#ibcon#enter wrdev, iclass 14, count 0 2006.196.07:53:49.21#ibcon#first serial, iclass 14, count 0 2006.196.07:53:49.21#ibcon#enter sib2, iclass 14, count 0 2006.196.07:53:49.21#ibcon#flushed, iclass 14, count 0 2006.196.07:53:49.21#ibcon#about to write, iclass 14, count 0 2006.196.07:53:49.21#ibcon#wrote, iclass 14, count 0 2006.196.07:53:49.21#ibcon#about to read 3, iclass 14, count 0 2006.196.07:53:49.23#ibcon#read 3, iclass 14, count 0 2006.196.07:53:49.23#ibcon#about to read 4, iclass 14, count 0 2006.196.07:53:49.23#ibcon#read 4, iclass 14, count 0 2006.196.07:53:49.23#ibcon#about to read 5, iclass 14, count 0 2006.196.07:53:49.23#ibcon#read 5, iclass 14, count 0 2006.196.07:53:49.23#ibcon#about to read 6, iclass 14, count 0 2006.196.07:53:49.23#ibcon#read 6, iclass 14, count 0 2006.196.07:53:49.23#ibcon#end of sib2, iclass 14, count 0 2006.196.07:53:49.23#ibcon#*mode == 0, iclass 14, count 0 2006.196.07:53:49.23#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.196.07:53:49.23#ibcon#[26=FRQ=05,652.99\r\n] 2006.196.07:53:49.23#ibcon#*before write, iclass 14, count 0 2006.196.07:53:49.23#ibcon#enter sib2, iclass 14, count 0 2006.196.07:53:49.23#ibcon#flushed, iclass 14, count 0 2006.196.07:53:49.23#ibcon#about to write, iclass 14, count 0 2006.196.07:53:49.23#ibcon#wrote, iclass 14, count 0 2006.196.07:53:49.23#ibcon#about to read 3, iclass 14, count 0 2006.196.07:53:49.27#ibcon#read 3, iclass 14, count 0 2006.196.07:53:49.27#ibcon#about to read 4, iclass 14, count 0 2006.196.07:53:49.27#ibcon#read 4, iclass 14, count 0 2006.196.07:53:49.27#ibcon#about to read 5, iclass 14, count 0 2006.196.07:53:49.27#ibcon#read 5, iclass 14, count 0 2006.196.07:53:49.27#ibcon#about to read 6, iclass 14, count 0 2006.196.07:53:49.27#ibcon#read 6, iclass 14, count 0 2006.196.07:53:49.27#ibcon#end of sib2, iclass 14, count 0 2006.196.07:53:49.27#ibcon#*after write, iclass 14, count 0 2006.196.07:53:49.27#ibcon#*before return 0, iclass 14, count 0 2006.196.07:53:49.27#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.196.07:53:49.27#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.196.07:53:49.27#ibcon#about to clear, iclass 14 cls_cnt 0 2006.196.07:53:49.27#ibcon#cleared, iclass 14 cls_cnt 0 2006.196.07:53:49.27$vc4f8/va=5,7 2006.196.07:53:49.27#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.196.07:53:49.27#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.196.07:53:49.27#ibcon#ireg 11 cls_cnt 2 2006.196.07:53:49.27#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.196.07:53:49.33#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.196.07:53:49.33#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.196.07:53:49.33#ibcon#enter wrdev, iclass 16, count 2 2006.196.07:53:49.33#ibcon#first serial, iclass 16, count 2 2006.196.07:53:49.33#ibcon#enter sib2, iclass 16, count 2 2006.196.07:53:49.33#ibcon#flushed, iclass 16, count 2 2006.196.07:53:49.33#ibcon#about to write, iclass 16, count 2 2006.196.07:53:49.33#ibcon#wrote, iclass 16, count 2 2006.196.07:53:49.33#ibcon#about to read 3, iclass 16, count 2 2006.196.07:53:49.35#ibcon#read 3, iclass 16, count 2 2006.196.07:53:49.35#ibcon#about to read 4, iclass 16, count 2 2006.196.07:53:49.35#ibcon#read 4, iclass 16, count 2 2006.196.07:53:49.35#ibcon#about to read 5, iclass 16, count 2 2006.196.07:53:49.35#ibcon#read 5, iclass 16, count 2 2006.196.07:53:49.35#ibcon#about to read 6, iclass 16, count 2 2006.196.07:53:49.35#ibcon#read 6, iclass 16, count 2 2006.196.07:53:49.35#ibcon#end of sib2, iclass 16, count 2 2006.196.07:53:49.35#ibcon#*mode == 0, iclass 16, count 2 2006.196.07:53:49.35#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.196.07:53:49.35#ibcon#[25=AT05-07\r\n] 2006.196.07:53:49.35#ibcon#*before write, iclass 16, count 2 2006.196.07:53:49.35#ibcon#enter sib2, iclass 16, count 2 2006.196.07:53:49.35#ibcon#flushed, iclass 16, count 2 2006.196.07:53:49.35#ibcon#about to write, iclass 16, count 2 2006.196.07:53:49.35#ibcon#wrote, iclass 16, count 2 2006.196.07:53:49.35#ibcon#about to read 3, iclass 16, count 2 2006.196.07:53:49.38#ibcon#read 3, iclass 16, count 2 2006.196.07:53:49.38#ibcon#about to read 4, iclass 16, count 2 2006.196.07:53:49.38#ibcon#read 4, iclass 16, count 2 2006.196.07:53:49.38#ibcon#about to read 5, iclass 16, count 2 2006.196.07:53:49.38#ibcon#read 5, iclass 16, count 2 2006.196.07:53:49.38#ibcon#about to read 6, iclass 16, count 2 2006.196.07:53:49.38#ibcon#read 6, iclass 16, count 2 2006.196.07:53:49.38#ibcon#end of sib2, iclass 16, count 2 2006.196.07:53:49.38#ibcon#*after write, iclass 16, count 2 2006.196.07:53:49.38#ibcon#*before return 0, iclass 16, count 2 2006.196.07:53:49.38#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.196.07:53:49.38#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.196.07:53:49.38#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.196.07:53:49.38#ibcon#ireg 7 cls_cnt 0 2006.196.07:53:49.38#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.196.07:53:49.50#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.196.07:53:49.50#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.196.07:53:49.50#ibcon#enter wrdev, iclass 16, count 0 2006.196.07:53:49.50#ibcon#first serial, iclass 16, count 0 2006.196.07:53:49.50#ibcon#enter sib2, iclass 16, count 0 2006.196.07:53:49.50#ibcon#flushed, iclass 16, count 0 2006.196.07:53:49.50#ibcon#about to write, iclass 16, count 0 2006.196.07:53:49.50#ibcon#wrote, iclass 16, count 0 2006.196.07:53:49.50#ibcon#about to read 3, iclass 16, count 0 2006.196.07:53:49.52#ibcon#read 3, iclass 16, count 0 2006.196.07:53:49.52#ibcon#about to read 4, iclass 16, count 0 2006.196.07:53:49.52#ibcon#read 4, iclass 16, count 0 2006.196.07:53:49.52#ibcon#about to read 5, iclass 16, count 0 2006.196.07:53:49.52#ibcon#read 5, iclass 16, count 0 2006.196.07:53:49.52#ibcon#about to read 6, iclass 16, count 0 2006.196.07:53:49.52#ibcon#read 6, iclass 16, count 0 2006.196.07:53:49.52#ibcon#end of sib2, iclass 16, count 0 2006.196.07:53:49.52#ibcon#*mode == 0, iclass 16, count 0 2006.196.07:53:49.52#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.196.07:53:49.52#ibcon#[25=USB\r\n] 2006.196.07:53:49.52#ibcon#*before write, iclass 16, count 0 2006.196.07:53:49.52#ibcon#enter sib2, iclass 16, count 0 2006.196.07:53:49.52#ibcon#flushed, iclass 16, count 0 2006.196.07:53:49.52#ibcon#about to write, iclass 16, count 0 2006.196.07:53:49.52#ibcon#wrote, iclass 16, count 0 2006.196.07:53:49.52#ibcon#about to read 3, iclass 16, count 0 2006.196.07:53:49.55#ibcon#read 3, iclass 16, count 0 2006.196.07:53:49.55#ibcon#about to read 4, iclass 16, count 0 2006.196.07:53:49.55#ibcon#read 4, iclass 16, count 0 2006.196.07:53:49.55#ibcon#about to read 5, iclass 16, count 0 2006.196.07:53:49.55#ibcon#read 5, iclass 16, count 0 2006.196.07:53:49.55#ibcon#about to read 6, iclass 16, count 0 2006.196.07:53:49.55#ibcon#read 6, iclass 16, count 0 2006.196.07:53:49.55#ibcon#end of sib2, iclass 16, count 0 2006.196.07:53:49.55#ibcon#*after write, iclass 16, count 0 2006.196.07:53:49.55#ibcon#*before return 0, iclass 16, count 0 2006.196.07:53:49.55#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.196.07:53:49.55#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.196.07:53:49.55#ibcon#about to clear, iclass 16 cls_cnt 0 2006.196.07:53:49.55#ibcon#cleared, iclass 16 cls_cnt 0 2006.196.07:53:49.55$vc4f8/valo=6,772.99 2006.196.07:53:49.55#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.196.07:53:49.55#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.196.07:53:49.55#ibcon#ireg 17 cls_cnt 0 2006.196.07:53:49.55#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.196.07:53:49.55#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.196.07:53:49.55#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.196.07:53:49.55#ibcon#enter wrdev, iclass 18, count 0 2006.196.07:53:49.55#ibcon#first serial, iclass 18, count 0 2006.196.07:53:49.55#ibcon#enter sib2, iclass 18, count 0 2006.196.07:53:49.55#ibcon#flushed, iclass 18, count 0 2006.196.07:53:49.55#ibcon#about to write, iclass 18, count 0 2006.196.07:53:49.55#ibcon#wrote, iclass 18, count 0 2006.196.07:53:49.55#ibcon#about to read 3, iclass 18, count 0 2006.196.07:53:49.57#ibcon#read 3, iclass 18, count 0 2006.196.07:53:49.57#ibcon#about to read 4, iclass 18, count 0 2006.196.07:53:49.57#ibcon#read 4, iclass 18, count 0 2006.196.07:53:49.57#ibcon#about to read 5, iclass 18, count 0 2006.196.07:53:49.57#ibcon#read 5, iclass 18, count 0 2006.196.07:53:49.57#ibcon#about to read 6, iclass 18, count 0 2006.196.07:53:49.57#ibcon#read 6, iclass 18, count 0 2006.196.07:53:49.57#ibcon#end of sib2, iclass 18, count 0 2006.196.07:53:49.57#ibcon#*mode == 0, iclass 18, count 0 2006.196.07:53:49.57#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.196.07:53:49.57#ibcon#[26=FRQ=06,772.99\r\n] 2006.196.07:53:49.57#ibcon#*before write, iclass 18, count 0 2006.196.07:53:49.57#ibcon#enter sib2, iclass 18, count 0 2006.196.07:53:49.57#ibcon#flushed, iclass 18, count 0 2006.196.07:53:49.57#ibcon#about to write, iclass 18, count 0 2006.196.07:53:49.57#ibcon#wrote, iclass 18, count 0 2006.196.07:53:49.57#ibcon#about to read 3, iclass 18, count 0 2006.196.07:53:49.62#ibcon#read 3, iclass 18, count 0 2006.196.07:53:49.62#ibcon#about to read 4, iclass 18, count 0 2006.196.07:53:49.62#ibcon#read 4, iclass 18, count 0 2006.196.07:53:49.62#ibcon#about to read 5, iclass 18, count 0 2006.196.07:53:49.62#ibcon#read 5, iclass 18, count 0 2006.196.07:53:49.62#ibcon#about to read 6, iclass 18, count 0 2006.196.07:53:49.62#ibcon#read 6, iclass 18, count 0 2006.196.07:53:49.62#ibcon#end of sib2, iclass 18, count 0 2006.196.07:53:49.62#ibcon#*after write, iclass 18, count 0 2006.196.07:53:49.62#ibcon#*before return 0, iclass 18, count 0 2006.196.07:53:49.62#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.196.07:53:49.62#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.196.07:53:49.62#ibcon#about to clear, iclass 18 cls_cnt 0 2006.196.07:53:49.62#ibcon#cleared, iclass 18 cls_cnt 0 2006.196.07:53:49.62$vc4f8/va=6,6 2006.196.07:53:49.62#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.196.07:53:49.62#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.196.07:53:49.62#ibcon#ireg 11 cls_cnt 2 2006.196.07:53:49.62#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.196.07:53:49.67#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.196.07:53:49.67#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.196.07:53:49.67#ibcon#enter wrdev, iclass 20, count 2 2006.196.07:53:49.67#ibcon#first serial, iclass 20, count 2 2006.196.07:53:49.67#ibcon#enter sib2, iclass 20, count 2 2006.196.07:53:49.67#ibcon#flushed, iclass 20, count 2 2006.196.07:53:49.67#ibcon#about to write, iclass 20, count 2 2006.196.07:53:49.67#ibcon#wrote, iclass 20, count 2 2006.196.07:53:49.67#ibcon#about to read 3, iclass 20, count 2 2006.196.07:53:49.69#ibcon#read 3, iclass 20, count 2 2006.196.07:53:49.69#ibcon#about to read 4, iclass 20, count 2 2006.196.07:53:49.69#ibcon#read 4, iclass 20, count 2 2006.196.07:53:49.69#ibcon#about to read 5, iclass 20, count 2 2006.196.07:53:49.69#ibcon#read 5, iclass 20, count 2 2006.196.07:53:49.69#ibcon#about to read 6, iclass 20, count 2 2006.196.07:53:49.69#ibcon#read 6, iclass 20, count 2 2006.196.07:53:49.69#ibcon#end of sib2, iclass 20, count 2 2006.196.07:53:49.69#ibcon#*mode == 0, iclass 20, count 2 2006.196.07:53:49.69#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.196.07:53:49.69#ibcon#[25=AT06-06\r\n] 2006.196.07:53:49.69#ibcon#*before write, iclass 20, count 2 2006.196.07:53:49.69#ibcon#enter sib2, iclass 20, count 2 2006.196.07:53:49.69#ibcon#flushed, iclass 20, count 2 2006.196.07:53:49.69#ibcon#about to write, iclass 20, count 2 2006.196.07:53:49.69#ibcon#wrote, iclass 20, count 2 2006.196.07:53:49.69#ibcon#about to read 3, iclass 20, count 2 2006.196.07:53:49.72#ibcon#read 3, iclass 20, count 2 2006.196.07:53:49.72#ibcon#about to read 4, iclass 20, count 2 2006.196.07:53:49.72#ibcon#read 4, iclass 20, count 2 2006.196.07:53:49.72#ibcon#about to read 5, iclass 20, count 2 2006.196.07:53:49.72#ibcon#read 5, iclass 20, count 2 2006.196.07:53:49.72#ibcon#about to read 6, iclass 20, count 2 2006.196.07:53:49.72#ibcon#read 6, iclass 20, count 2 2006.196.07:53:49.72#ibcon#end of sib2, iclass 20, count 2 2006.196.07:53:49.72#ibcon#*after write, iclass 20, count 2 2006.196.07:53:49.72#ibcon#*before return 0, iclass 20, count 2 2006.196.07:53:49.72#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.196.07:53:49.72#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.196.07:53:49.72#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.196.07:53:49.72#ibcon#ireg 7 cls_cnt 0 2006.196.07:53:49.72#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.196.07:53:49.84#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.196.07:53:49.84#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.196.07:53:49.84#ibcon#enter wrdev, iclass 20, count 0 2006.196.07:53:49.84#ibcon#first serial, iclass 20, count 0 2006.196.07:53:49.84#ibcon#enter sib2, iclass 20, count 0 2006.196.07:53:49.84#ibcon#flushed, iclass 20, count 0 2006.196.07:53:49.84#ibcon#about to write, iclass 20, count 0 2006.196.07:53:49.84#ibcon#wrote, iclass 20, count 0 2006.196.07:53:49.84#ibcon#about to read 3, iclass 20, count 0 2006.196.07:53:49.86#ibcon#read 3, iclass 20, count 0 2006.196.07:53:49.86#ibcon#about to read 4, iclass 20, count 0 2006.196.07:53:49.86#ibcon#read 4, iclass 20, count 0 2006.196.07:53:49.86#ibcon#about to read 5, iclass 20, count 0 2006.196.07:53:49.86#ibcon#read 5, iclass 20, count 0 2006.196.07:53:49.86#ibcon#about to read 6, iclass 20, count 0 2006.196.07:53:49.86#ibcon#read 6, iclass 20, count 0 2006.196.07:53:49.86#ibcon#end of sib2, iclass 20, count 0 2006.196.07:53:49.86#ibcon#*mode == 0, iclass 20, count 0 2006.196.07:53:49.86#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.196.07:53:49.86#ibcon#[25=USB\r\n] 2006.196.07:53:49.86#ibcon#*before write, iclass 20, count 0 2006.196.07:53:49.86#ibcon#enter sib2, iclass 20, count 0 2006.196.07:53:49.86#ibcon#flushed, iclass 20, count 0 2006.196.07:53:49.86#ibcon#about to write, iclass 20, count 0 2006.196.07:53:49.86#ibcon#wrote, iclass 20, count 0 2006.196.07:53:49.86#ibcon#about to read 3, iclass 20, count 0 2006.196.07:53:49.89#ibcon#read 3, iclass 20, count 0 2006.196.07:53:49.89#ibcon#about to read 4, iclass 20, count 0 2006.196.07:53:49.89#ibcon#read 4, iclass 20, count 0 2006.196.07:53:49.89#ibcon#about to read 5, iclass 20, count 0 2006.196.07:53:49.89#ibcon#read 5, iclass 20, count 0 2006.196.07:53:49.89#ibcon#about to read 6, iclass 20, count 0 2006.196.07:53:49.89#ibcon#read 6, iclass 20, count 0 2006.196.07:53:49.89#ibcon#end of sib2, iclass 20, count 0 2006.196.07:53:49.89#ibcon#*after write, iclass 20, count 0 2006.196.07:53:49.89#ibcon#*before return 0, iclass 20, count 0 2006.196.07:53:49.89#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.196.07:53:49.89#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.196.07:53:49.89#ibcon#about to clear, iclass 20 cls_cnt 0 2006.196.07:53:49.89#ibcon#cleared, iclass 20 cls_cnt 0 2006.196.07:53:49.89$vc4f8/valo=7,832.99 2006.196.07:53:49.89#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.196.07:53:49.89#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.196.07:53:49.89#ibcon#ireg 17 cls_cnt 0 2006.196.07:53:49.89#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.196.07:53:49.89#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.196.07:53:49.89#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.196.07:53:49.89#ibcon#enter wrdev, iclass 22, count 0 2006.196.07:53:49.89#ibcon#first serial, iclass 22, count 0 2006.196.07:53:49.89#ibcon#enter sib2, iclass 22, count 0 2006.196.07:53:49.89#ibcon#flushed, iclass 22, count 0 2006.196.07:53:49.89#ibcon#about to write, iclass 22, count 0 2006.196.07:53:49.89#ibcon#wrote, iclass 22, count 0 2006.196.07:53:49.89#ibcon#about to read 3, iclass 22, count 0 2006.196.07:53:49.91#ibcon#read 3, iclass 22, count 0 2006.196.07:53:49.91#ibcon#about to read 4, iclass 22, count 0 2006.196.07:53:49.91#ibcon#read 4, iclass 22, count 0 2006.196.07:53:49.91#ibcon#about to read 5, iclass 22, count 0 2006.196.07:53:49.91#ibcon#read 5, iclass 22, count 0 2006.196.07:53:49.91#ibcon#about to read 6, iclass 22, count 0 2006.196.07:53:49.91#ibcon#read 6, iclass 22, count 0 2006.196.07:53:49.91#ibcon#end of sib2, iclass 22, count 0 2006.196.07:53:49.91#ibcon#*mode == 0, iclass 22, count 0 2006.196.07:53:49.91#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.196.07:53:49.91#ibcon#[26=FRQ=07,832.99\r\n] 2006.196.07:53:49.91#ibcon#*before write, iclass 22, count 0 2006.196.07:53:49.91#ibcon#enter sib2, iclass 22, count 0 2006.196.07:53:49.91#ibcon#flushed, iclass 22, count 0 2006.196.07:53:49.91#ibcon#about to write, iclass 22, count 0 2006.196.07:53:49.91#ibcon#wrote, iclass 22, count 0 2006.196.07:53:49.91#ibcon#about to read 3, iclass 22, count 0 2006.196.07:53:49.95#ibcon#read 3, iclass 22, count 0 2006.196.07:53:49.95#ibcon#about to read 4, iclass 22, count 0 2006.196.07:53:49.95#ibcon#read 4, iclass 22, count 0 2006.196.07:53:49.95#ibcon#about to read 5, iclass 22, count 0 2006.196.07:53:49.95#ibcon#read 5, iclass 22, count 0 2006.196.07:53:49.95#ibcon#about to read 6, iclass 22, count 0 2006.196.07:53:49.95#ibcon#read 6, iclass 22, count 0 2006.196.07:53:49.95#ibcon#end of sib2, iclass 22, count 0 2006.196.07:53:49.95#ibcon#*after write, iclass 22, count 0 2006.196.07:53:49.95#ibcon#*before return 0, iclass 22, count 0 2006.196.07:53:49.95#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.196.07:53:49.95#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.196.07:53:49.95#ibcon#about to clear, iclass 22 cls_cnt 0 2006.196.07:53:49.95#ibcon#cleared, iclass 22 cls_cnt 0 2006.196.07:53:49.95$vc4f8/va=7,6 2006.196.07:53:49.95#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.196.07:53:49.95#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.196.07:53:49.95#ibcon#ireg 11 cls_cnt 2 2006.196.07:53:49.95#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.196.07:53:50.01#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.196.07:53:50.01#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.196.07:53:50.01#ibcon#enter wrdev, iclass 24, count 2 2006.196.07:53:50.01#ibcon#first serial, iclass 24, count 2 2006.196.07:53:50.01#ibcon#enter sib2, iclass 24, count 2 2006.196.07:53:50.01#ibcon#flushed, iclass 24, count 2 2006.196.07:53:50.01#ibcon#about to write, iclass 24, count 2 2006.196.07:53:50.01#ibcon#wrote, iclass 24, count 2 2006.196.07:53:50.01#ibcon#about to read 3, iclass 24, count 2 2006.196.07:53:50.03#ibcon#read 3, iclass 24, count 2 2006.196.07:53:50.03#ibcon#about to read 4, iclass 24, count 2 2006.196.07:53:50.03#ibcon#read 4, iclass 24, count 2 2006.196.07:53:50.03#ibcon#about to read 5, iclass 24, count 2 2006.196.07:53:50.03#ibcon#read 5, iclass 24, count 2 2006.196.07:53:50.03#ibcon#about to read 6, iclass 24, count 2 2006.196.07:53:50.03#ibcon#read 6, iclass 24, count 2 2006.196.07:53:50.03#ibcon#end of sib2, iclass 24, count 2 2006.196.07:53:50.03#ibcon#*mode == 0, iclass 24, count 2 2006.196.07:53:50.03#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.196.07:53:50.03#ibcon#[25=AT07-06\r\n] 2006.196.07:53:50.03#ibcon#*before write, iclass 24, count 2 2006.196.07:53:50.03#ibcon#enter sib2, iclass 24, count 2 2006.196.07:53:50.03#ibcon#flushed, iclass 24, count 2 2006.196.07:53:50.03#ibcon#about to write, iclass 24, count 2 2006.196.07:53:50.03#ibcon#wrote, iclass 24, count 2 2006.196.07:53:50.03#ibcon#about to read 3, iclass 24, count 2 2006.196.07:53:50.06#ibcon#read 3, iclass 24, count 2 2006.196.07:53:50.06#ibcon#about to read 4, iclass 24, count 2 2006.196.07:53:50.06#ibcon#read 4, iclass 24, count 2 2006.196.07:53:50.06#ibcon#about to read 5, iclass 24, count 2 2006.196.07:53:50.06#ibcon#read 5, iclass 24, count 2 2006.196.07:53:50.06#ibcon#about to read 6, iclass 24, count 2 2006.196.07:53:50.06#ibcon#read 6, iclass 24, count 2 2006.196.07:53:50.06#ibcon#end of sib2, iclass 24, count 2 2006.196.07:53:50.06#ibcon#*after write, iclass 24, count 2 2006.196.07:53:50.06#ibcon#*before return 0, iclass 24, count 2 2006.196.07:53:50.06#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.196.07:53:50.06#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.196.07:53:50.06#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.196.07:53:50.06#ibcon#ireg 7 cls_cnt 0 2006.196.07:53:50.06#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.196.07:53:50.18#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.196.07:53:50.18#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.196.07:53:50.18#ibcon#enter wrdev, iclass 24, count 0 2006.196.07:53:50.18#ibcon#first serial, iclass 24, count 0 2006.196.07:53:50.18#ibcon#enter sib2, iclass 24, count 0 2006.196.07:53:50.18#ibcon#flushed, iclass 24, count 0 2006.196.07:53:50.18#ibcon#about to write, iclass 24, count 0 2006.196.07:53:50.18#ibcon#wrote, iclass 24, count 0 2006.196.07:53:50.18#ibcon#about to read 3, iclass 24, count 0 2006.196.07:53:50.20#ibcon#read 3, iclass 24, count 0 2006.196.07:53:50.20#ibcon#about to read 4, iclass 24, count 0 2006.196.07:53:50.20#ibcon#read 4, iclass 24, count 0 2006.196.07:53:50.20#ibcon#about to read 5, iclass 24, count 0 2006.196.07:53:50.20#ibcon#read 5, iclass 24, count 0 2006.196.07:53:50.20#ibcon#about to read 6, iclass 24, count 0 2006.196.07:53:50.20#ibcon#read 6, iclass 24, count 0 2006.196.07:53:50.20#ibcon#end of sib2, iclass 24, count 0 2006.196.07:53:50.20#ibcon#*mode == 0, iclass 24, count 0 2006.196.07:53:50.20#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.196.07:53:50.20#ibcon#[25=USB\r\n] 2006.196.07:53:50.20#ibcon#*before write, iclass 24, count 0 2006.196.07:53:50.20#ibcon#enter sib2, iclass 24, count 0 2006.196.07:53:50.20#ibcon#flushed, iclass 24, count 0 2006.196.07:53:50.20#ibcon#about to write, iclass 24, count 0 2006.196.07:53:50.20#ibcon#wrote, iclass 24, count 0 2006.196.07:53:50.20#ibcon#about to read 3, iclass 24, count 0 2006.196.07:53:50.23#ibcon#read 3, iclass 24, count 0 2006.196.07:53:50.23#ibcon#about to read 4, iclass 24, count 0 2006.196.07:53:50.23#ibcon#read 4, iclass 24, count 0 2006.196.07:53:50.23#ibcon#about to read 5, iclass 24, count 0 2006.196.07:53:50.23#ibcon#read 5, iclass 24, count 0 2006.196.07:53:50.23#ibcon#about to read 6, iclass 24, count 0 2006.196.07:53:50.23#ibcon#read 6, iclass 24, count 0 2006.196.07:53:50.23#ibcon#end of sib2, iclass 24, count 0 2006.196.07:53:50.23#ibcon#*after write, iclass 24, count 0 2006.196.07:53:50.23#ibcon#*before return 0, iclass 24, count 0 2006.196.07:53:50.23#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.196.07:53:50.23#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.196.07:53:50.23#ibcon#about to clear, iclass 24 cls_cnt 0 2006.196.07:53:50.23#ibcon#cleared, iclass 24 cls_cnt 0 2006.196.07:53:50.23$vc4f8/valo=8,852.99 2006.196.07:53:50.23#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.196.07:53:50.23#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.196.07:53:50.23#ibcon#ireg 17 cls_cnt 0 2006.196.07:53:50.23#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.196.07:53:50.23#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.196.07:53:50.23#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.196.07:53:50.23#ibcon#enter wrdev, iclass 26, count 0 2006.196.07:53:50.23#ibcon#first serial, iclass 26, count 0 2006.196.07:53:50.23#ibcon#enter sib2, iclass 26, count 0 2006.196.07:53:50.23#ibcon#flushed, iclass 26, count 0 2006.196.07:53:50.23#ibcon#about to write, iclass 26, count 0 2006.196.07:53:50.23#ibcon#wrote, iclass 26, count 0 2006.196.07:53:50.23#ibcon#about to read 3, iclass 26, count 0 2006.196.07:53:50.25#ibcon#read 3, iclass 26, count 0 2006.196.07:53:50.25#ibcon#about to read 4, iclass 26, count 0 2006.196.07:53:50.25#ibcon#read 4, iclass 26, count 0 2006.196.07:53:50.25#ibcon#about to read 5, iclass 26, count 0 2006.196.07:53:50.25#ibcon#read 5, iclass 26, count 0 2006.196.07:53:50.25#ibcon#about to read 6, iclass 26, count 0 2006.196.07:53:50.25#ibcon#read 6, iclass 26, count 0 2006.196.07:53:50.25#ibcon#end of sib2, iclass 26, count 0 2006.196.07:53:50.25#ibcon#*mode == 0, iclass 26, count 0 2006.196.07:53:50.25#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.196.07:53:50.25#ibcon#[26=FRQ=08,852.99\r\n] 2006.196.07:53:50.25#ibcon#*before write, iclass 26, count 0 2006.196.07:53:50.25#ibcon#enter sib2, iclass 26, count 0 2006.196.07:53:50.25#ibcon#flushed, iclass 26, count 0 2006.196.07:53:50.25#ibcon#about to write, iclass 26, count 0 2006.196.07:53:50.25#ibcon#wrote, iclass 26, count 0 2006.196.07:53:50.25#ibcon#about to read 3, iclass 26, count 0 2006.196.07:53:50.29#ibcon#read 3, iclass 26, count 0 2006.196.07:53:50.29#ibcon#about to read 4, iclass 26, count 0 2006.196.07:53:50.29#ibcon#read 4, iclass 26, count 0 2006.196.07:53:50.29#ibcon#about to read 5, iclass 26, count 0 2006.196.07:53:50.29#ibcon#read 5, iclass 26, count 0 2006.196.07:53:50.29#ibcon#about to read 6, iclass 26, count 0 2006.196.07:53:50.29#ibcon#read 6, iclass 26, count 0 2006.196.07:53:50.29#ibcon#end of sib2, iclass 26, count 0 2006.196.07:53:50.29#ibcon#*after write, iclass 26, count 0 2006.196.07:53:50.29#ibcon#*before return 0, iclass 26, count 0 2006.196.07:53:50.29#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.196.07:53:50.29#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.196.07:53:50.29#ibcon#about to clear, iclass 26 cls_cnt 0 2006.196.07:53:50.29#ibcon#cleared, iclass 26 cls_cnt 0 2006.196.07:53:50.29$vc4f8/va=8,7 2006.196.07:53:50.29#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.196.07:53:50.29#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.196.07:53:50.29#ibcon#ireg 11 cls_cnt 2 2006.196.07:53:50.29#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.196.07:53:50.35#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.196.07:53:50.35#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.196.07:53:50.35#ibcon#enter wrdev, iclass 28, count 2 2006.196.07:53:50.35#ibcon#first serial, iclass 28, count 2 2006.196.07:53:50.35#ibcon#enter sib2, iclass 28, count 2 2006.196.07:53:50.35#ibcon#flushed, iclass 28, count 2 2006.196.07:53:50.35#ibcon#about to write, iclass 28, count 2 2006.196.07:53:50.35#ibcon#wrote, iclass 28, count 2 2006.196.07:53:50.35#ibcon#about to read 3, iclass 28, count 2 2006.196.07:53:50.37#ibcon#read 3, iclass 28, count 2 2006.196.07:53:50.37#ibcon#about to read 4, iclass 28, count 2 2006.196.07:53:50.37#ibcon#read 4, iclass 28, count 2 2006.196.07:53:50.37#ibcon#about to read 5, iclass 28, count 2 2006.196.07:53:50.37#ibcon#read 5, iclass 28, count 2 2006.196.07:53:50.37#ibcon#about to read 6, iclass 28, count 2 2006.196.07:53:50.37#ibcon#read 6, iclass 28, count 2 2006.196.07:53:50.37#ibcon#end of sib2, iclass 28, count 2 2006.196.07:53:50.37#ibcon#*mode == 0, iclass 28, count 2 2006.196.07:53:50.37#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.196.07:53:50.37#ibcon#[25=AT08-07\r\n] 2006.196.07:53:50.37#ibcon#*before write, iclass 28, count 2 2006.196.07:53:50.37#ibcon#enter sib2, iclass 28, count 2 2006.196.07:53:50.37#ibcon#flushed, iclass 28, count 2 2006.196.07:53:50.37#ibcon#about to write, iclass 28, count 2 2006.196.07:53:50.37#ibcon#wrote, iclass 28, count 2 2006.196.07:53:50.37#ibcon#about to read 3, iclass 28, count 2 2006.196.07:53:50.40#ibcon#read 3, iclass 28, count 2 2006.196.07:53:50.40#ibcon#about to read 4, iclass 28, count 2 2006.196.07:53:50.40#ibcon#read 4, iclass 28, count 2 2006.196.07:53:50.40#ibcon#about to read 5, iclass 28, count 2 2006.196.07:53:50.40#ibcon#read 5, iclass 28, count 2 2006.196.07:53:50.40#ibcon#about to read 6, iclass 28, count 2 2006.196.07:53:50.40#ibcon#read 6, iclass 28, count 2 2006.196.07:53:50.40#ibcon#end of sib2, iclass 28, count 2 2006.196.07:53:50.40#ibcon#*after write, iclass 28, count 2 2006.196.07:53:50.40#ibcon#*before return 0, iclass 28, count 2 2006.196.07:53:50.40#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.196.07:53:50.40#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.196.07:53:50.40#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.196.07:53:50.40#ibcon#ireg 7 cls_cnt 0 2006.196.07:53:50.40#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.196.07:53:50.52#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.196.07:53:50.52#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.196.07:53:50.52#ibcon#enter wrdev, iclass 28, count 0 2006.196.07:53:50.52#ibcon#first serial, iclass 28, count 0 2006.196.07:53:50.52#ibcon#enter sib2, iclass 28, count 0 2006.196.07:53:50.52#ibcon#flushed, iclass 28, count 0 2006.196.07:53:50.52#ibcon#about to write, iclass 28, count 0 2006.196.07:53:50.52#ibcon#wrote, iclass 28, count 0 2006.196.07:53:50.52#ibcon#about to read 3, iclass 28, count 0 2006.196.07:53:50.54#ibcon#read 3, iclass 28, count 0 2006.196.07:53:50.54#ibcon#about to read 4, iclass 28, count 0 2006.196.07:53:50.54#ibcon#read 4, iclass 28, count 0 2006.196.07:53:50.54#ibcon#about to read 5, iclass 28, count 0 2006.196.07:53:50.54#ibcon#read 5, iclass 28, count 0 2006.196.07:53:50.54#ibcon#about to read 6, iclass 28, count 0 2006.196.07:53:50.54#ibcon#read 6, iclass 28, count 0 2006.196.07:53:50.54#ibcon#end of sib2, iclass 28, count 0 2006.196.07:53:50.54#ibcon#*mode == 0, iclass 28, count 0 2006.196.07:53:50.54#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.196.07:53:50.54#ibcon#[25=USB\r\n] 2006.196.07:53:50.54#ibcon#*before write, iclass 28, count 0 2006.196.07:53:50.54#ibcon#enter sib2, iclass 28, count 0 2006.196.07:53:50.54#ibcon#flushed, iclass 28, count 0 2006.196.07:53:50.54#ibcon#about to write, iclass 28, count 0 2006.196.07:53:50.54#ibcon#wrote, iclass 28, count 0 2006.196.07:53:50.54#ibcon#about to read 3, iclass 28, count 0 2006.196.07:53:50.57#ibcon#read 3, iclass 28, count 0 2006.196.07:53:50.57#ibcon#about to read 4, iclass 28, count 0 2006.196.07:53:50.57#ibcon#read 4, iclass 28, count 0 2006.196.07:53:50.57#ibcon#about to read 5, iclass 28, count 0 2006.196.07:53:50.57#ibcon#read 5, iclass 28, count 0 2006.196.07:53:50.57#ibcon#about to read 6, iclass 28, count 0 2006.196.07:53:50.57#ibcon#read 6, iclass 28, count 0 2006.196.07:53:50.57#ibcon#end of sib2, iclass 28, count 0 2006.196.07:53:50.57#ibcon#*after write, iclass 28, count 0 2006.196.07:53:50.57#ibcon#*before return 0, iclass 28, count 0 2006.196.07:53:50.57#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.196.07:53:50.57#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.196.07:53:50.57#ibcon#about to clear, iclass 28 cls_cnt 0 2006.196.07:53:50.57#ibcon#cleared, iclass 28 cls_cnt 0 2006.196.07:53:50.57$vc4f8/vblo=1,632.99 2006.196.07:53:50.57#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.196.07:53:50.57#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.196.07:53:50.57#ibcon#ireg 17 cls_cnt 0 2006.196.07:53:50.57#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.196.07:53:50.57#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.196.07:53:50.57#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.196.07:53:50.57#ibcon#enter wrdev, iclass 30, count 0 2006.196.07:53:50.57#ibcon#first serial, iclass 30, count 0 2006.196.07:53:50.57#ibcon#enter sib2, iclass 30, count 0 2006.196.07:53:50.57#ibcon#flushed, iclass 30, count 0 2006.196.07:53:50.57#ibcon#about to write, iclass 30, count 0 2006.196.07:53:50.57#ibcon#wrote, iclass 30, count 0 2006.196.07:53:50.57#ibcon#about to read 3, iclass 30, count 0 2006.196.07:53:50.59#ibcon#read 3, iclass 30, count 0 2006.196.07:53:50.59#ibcon#about to read 4, iclass 30, count 0 2006.196.07:53:50.59#ibcon#read 4, iclass 30, count 0 2006.196.07:53:50.59#ibcon#about to read 5, iclass 30, count 0 2006.196.07:53:50.59#ibcon#read 5, iclass 30, count 0 2006.196.07:53:50.59#ibcon#about to read 6, iclass 30, count 0 2006.196.07:53:50.59#ibcon#read 6, iclass 30, count 0 2006.196.07:53:50.59#ibcon#end of sib2, iclass 30, count 0 2006.196.07:53:50.59#ibcon#*mode == 0, iclass 30, count 0 2006.196.07:53:50.59#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.196.07:53:50.59#ibcon#[28=FRQ=01,632.99\r\n] 2006.196.07:53:50.59#ibcon#*before write, iclass 30, count 0 2006.196.07:53:50.59#ibcon#enter sib2, iclass 30, count 0 2006.196.07:53:50.59#ibcon#flushed, iclass 30, count 0 2006.196.07:53:50.59#ibcon#about to write, iclass 30, count 0 2006.196.07:53:50.59#ibcon#wrote, iclass 30, count 0 2006.196.07:53:50.59#ibcon#about to read 3, iclass 30, count 0 2006.196.07:53:50.63#ibcon#read 3, iclass 30, count 0 2006.196.07:53:50.63#ibcon#about to read 4, iclass 30, count 0 2006.196.07:53:50.63#ibcon#read 4, iclass 30, count 0 2006.196.07:53:50.63#ibcon#about to read 5, iclass 30, count 0 2006.196.07:53:50.63#ibcon#read 5, iclass 30, count 0 2006.196.07:53:50.63#ibcon#about to read 6, iclass 30, count 0 2006.196.07:53:50.63#ibcon#read 6, iclass 30, count 0 2006.196.07:53:50.63#ibcon#end of sib2, iclass 30, count 0 2006.196.07:53:50.63#ibcon#*after write, iclass 30, count 0 2006.196.07:53:50.63#ibcon#*before return 0, iclass 30, count 0 2006.196.07:53:50.63#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.196.07:53:50.63#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.196.07:53:50.63#ibcon#about to clear, iclass 30 cls_cnt 0 2006.196.07:53:50.63#ibcon#cleared, iclass 30 cls_cnt 0 2006.196.07:53:50.63$vc4f8/vb=1,4 2006.196.07:53:50.63#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.196.07:53:50.63#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.196.07:53:50.63#ibcon#ireg 11 cls_cnt 2 2006.196.07:53:50.63#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.196.07:53:50.63#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.196.07:53:50.63#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.196.07:53:50.63#ibcon#enter wrdev, iclass 32, count 2 2006.196.07:53:50.63#ibcon#first serial, iclass 32, count 2 2006.196.07:53:50.63#ibcon#enter sib2, iclass 32, count 2 2006.196.07:53:50.63#ibcon#flushed, iclass 32, count 2 2006.196.07:53:50.63#ibcon#about to write, iclass 32, count 2 2006.196.07:53:50.63#ibcon#wrote, iclass 32, count 2 2006.196.07:53:50.63#ibcon#about to read 3, iclass 32, count 2 2006.196.07:53:50.65#ibcon#read 3, iclass 32, count 2 2006.196.07:53:50.65#ibcon#about to read 4, iclass 32, count 2 2006.196.07:53:50.65#ibcon#read 4, iclass 32, count 2 2006.196.07:53:50.65#ibcon#about to read 5, iclass 32, count 2 2006.196.07:53:50.65#ibcon#read 5, iclass 32, count 2 2006.196.07:53:50.65#ibcon#about to read 6, iclass 32, count 2 2006.196.07:53:50.65#ibcon#read 6, iclass 32, count 2 2006.196.07:53:50.65#ibcon#end of sib2, iclass 32, count 2 2006.196.07:53:50.65#ibcon#*mode == 0, iclass 32, count 2 2006.196.07:53:50.65#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.196.07:53:50.65#ibcon#[27=AT01-04\r\n] 2006.196.07:53:50.65#ibcon#*before write, iclass 32, count 2 2006.196.07:53:50.65#ibcon#enter sib2, iclass 32, count 2 2006.196.07:53:50.65#ibcon#flushed, iclass 32, count 2 2006.196.07:53:50.65#ibcon#about to write, iclass 32, count 2 2006.196.07:53:50.65#ibcon#wrote, iclass 32, count 2 2006.196.07:53:50.65#ibcon#about to read 3, iclass 32, count 2 2006.196.07:53:50.68#ibcon#read 3, iclass 32, count 2 2006.196.07:53:50.68#ibcon#about to read 4, iclass 32, count 2 2006.196.07:53:50.68#ibcon#read 4, iclass 32, count 2 2006.196.07:53:50.68#ibcon#about to read 5, iclass 32, count 2 2006.196.07:53:50.68#ibcon#read 5, iclass 32, count 2 2006.196.07:53:50.68#ibcon#about to read 6, iclass 32, count 2 2006.196.07:53:50.68#ibcon#read 6, iclass 32, count 2 2006.196.07:53:50.68#ibcon#end of sib2, iclass 32, count 2 2006.196.07:53:50.68#ibcon#*after write, iclass 32, count 2 2006.196.07:53:50.68#ibcon#*before return 0, iclass 32, count 2 2006.196.07:53:50.68#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.196.07:53:50.68#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.196.07:53:50.68#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.196.07:53:50.68#ibcon#ireg 7 cls_cnt 0 2006.196.07:53:50.68#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.196.07:53:50.80#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.196.07:53:50.80#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.196.07:53:50.80#ibcon#enter wrdev, iclass 32, count 0 2006.196.07:53:50.80#ibcon#first serial, iclass 32, count 0 2006.196.07:53:50.80#ibcon#enter sib2, iclass 32, count 0 2006.196.07:53:50.80#ibcon#flushed, iclass 32, count 0 2006.196.07:53:50.80#ibcon#about to write, iclass 32, count 0 2006.196.07:53:50.80#ibcon#wrote, iclass 32, count 0 2006.196.07:53:50.80#ibcon#about to read 3, iclass 32, count 0 2006.196.07:53:50.82#ibcon#read 3, iclass 32, count 0 2006.196.07:53:50.82#ibcon#about to read 4, iclass 32, count 0 2006.196.07:53:50.82#ibcon#read 4, iclass 32, count 0 2006.196.07:53:50.82#ibcon#about to read 5, iclass 32, count 0 2006.196.07:53:50.82#ibcon#read 5, iclass 32, count 0 2006.196.07:53:50.82#ibcon#about to read 6, iclass 32, count 0 2006.196.07:53:50.82#ibcon#read 6, iclass 32, count 0 2006.196.07:53:50.82#ibcon#end of sib2, iclass 32, count 0 2006.196.07:53:50.82#ibcon#*mode == 0, iclass 32, count 0 2006.196.07:53:50.82#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.196.07:53:50.82#ibcon#[27=USB\r\n] 2006.196.07:53:50.82#ibcon#*before write, iclass 32, count 0 2006.196.07:53:50.82#ibcon#enter sib2, iclass 32, count 0 2006.196.07:53:50.82#ibcon#flushed, iclass 32, count 0 2006.196.07:53:50.82#ibcon#about to write, iclass 32, count 0 2006.196.07:53:50.82#ibcon#wrote, iclass 32, count 0 2006.196.07:53:50.82#ibcon#about to read 3, iclass 32, count 0 2006.196.07:53:50.85#ibcon#read 3, iclass 32, count 0 2006.196.07:53:50.85#ibcon#about to read 4, iclass 32, count 0 2006.196.07:53:50.85#ibcon#read 4, iclass 32, count 0 2006.196.07:53:50.85#ibcon#about to read 5, iclass 32, count 0 2006.196.07:53:50.85#ibcon#read 5, iclass 32, count 0 2006.196.07:53:50.85#ibcon#about to read 6, iclass 32, count 0 2006.196.07:53:50.85#ibcon#read 6, iclass 32, count 0 2006.196.07:53:50.85#ibcon#end of sib2, iclass 32, count 0 2006.196.07:53:50.85#ibcon#*after write, iclass 32, count 0 2006.196.07:53:50.85#ibcon#*before return 0, iclass 32, count 0 2006.196.07:53:50.85#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.196.07:53:50.85#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.196.07:53:50.85#ibcon#about to clear, iclass 32 cls_cnt 0 2006.196.07:53:50.85#ibcon#cleared, iclass 32 cls_cnt 0 2006.196.07:53:50.85$vc4f8/vblo=2,640.99 2006.196.07:53:50.85#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.196.07:53:50.85#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.196.07:53:50.85#ibcon#ireg 17 cls_cnt 0 2006.196.07:53:50.85#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.196.07:53:50.85#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.196.07:53:50.85#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.196.07:53:50.85#ibcon#enter wrdev, iclass 34, count 0 2006.196.07:53:50.85#ibcon#first serial, iclass 34, count 0 2006.196.07:53:50.85#ibcon#enter sib2, iclass 34, count 0 2006.196.07:53:50.85#ibcon#flushed, iclass 34, count 0 2006.196.07:53:50.85#ibcon#about to write, iclass 34, count 0 2006.196.07:53:50.85#ibcon#wrote, iclass 34, count 0 2006.196.07:53:50.85#ibcon#about to read 3, iclass 34, count 0 2006.196.07:53:50.87#ibcon#read 3, iclass 34, count 0 2006.196.07:53:50.87#ibcon#about to read 4, iclass 34, count 0 2006.196.07:53:50.87#ibcon#read 4, iclass 34, count 0 2006.196.07:53:50.87#ibcon#about to read 5, iclass 34, count 0 2006.196.07:53:50.87#ibcon#read 5, iclass 34, count 0 2006.196.07:53:50.87#ibcon#about to read 6, iclass 34, count 0 2006.196.07:53:50.87#ibcon#read 6, iclass 34, count 0 2006.196.07:53:50.87#ibcon#end of sib2, iclass 34, count 0 2006.196.07:53:50.87#ibcon#*mode == 0, iclass 34, count 0 2006.196.07:53:50.87#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.196.07:53:50.87#ibcon#[28=FRQ=02,640.99\r\n] 2006.196.07:53:50.87#ibcon#*before write, iclass 34, count 0 2006.196.07:53:50.87#ibcon#enter sib2, iclass 34, count 0 2006.196.07:53:50.87#ibcon#flushed, iclass 34, count 0 2006.196.07:53:50.87#ibcon#about to write, iclass 34, count 0 2006.196.07:53:50.87#ibcon#wrote, iclass 34, count 0 2006.196.07:53:50.87#ibcon#about to read 3, iclass 34, count 0 2006.196.07:53:50.91#ibcon#read 3, iclass 34, count 0 2006.196.07:53:50.91#ibcon#about to read 4, iclass 34, count 0 2006.196.07:53:50.91#ibcon#read 4, iclass 34, count 0 2006.196.07:53:50.91#ibcon#about to read 5, iclass 34, count 0 2006.196.07:53:50.91#ibcon#read 5, iclass 34, count 0 2006.196.07:53:50.91#ibcon#about to read 6, iclass 34, count 0 2006.196.07:53:50.91#ibcon#read 6, iclass 34, count 0 2006.196.07:53:50.91#ibcon#end of sib2, iclass 34, count 0 2006.196.07:53:50.91#ibcon#*after write, iclass 34, count 0 2006.196.07:53:50.91#ibcon#*before return 0, iclass 34, count 0 2006.196.07:53:50.91#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.196.07:53:50.91#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.196.07:53:50.91#ibcon#about to clear, iclass 34 cls_cnt 0 2006.196.07:53:50.91#ibcon#cleared, iclass 34 cls_cnt 0 2006.196.07:53:50.91$vc4f8/vb=2,4 2006.196.07:53:50.91#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.196.07:53:50.91#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.196.07:53:50.91#ibcon#ireg 11 cls_cnt 2 2006.196.07:53:50.91#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.196.07:53:50.97#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.196.07:53:50.97#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.196.07:53:50.97#ibcon#enter wrdev, iclass 36, count 2 2006.196.07:53:50.97#ibcon#first serial, iclass 36, count 2 2006.196.07:53:50.97#ibcon#enter sib2, iclass 36, count 2 2006.196.07:53:50.97#ibcon#flushed, iclass 36, count 2 2006.196.07:53:50.97#ibcon#about to write, iclass 36, count 2 2006.196.07:53:50.97#ibcon#wrote, iclass 36, count 2 2006.196.07:53:50.97#ibcon#about to read 3, iclass 36, count 2 2006.196.07:53:50.99#ibcon#read 3, iclass 36, count 2 2006.196.07:53:50.99#ibcon#about to read 4, iclass 36, count 2 2006.196.07:53:50.99#ibcon#read 4, iclass 36, count 2 2006.196.07:53:50.99#ibcon#about to read 5, iclass 36, count 2 2006.196.07:53:50.99#ibcon#read 5, iclass 36, count 2 2006.196.07:53:50.99#ibcon#about to read 6, iclass 36, count 2 2006.196.07:53:50.99#ibcon#read 6, iclass 36, count 2 2006.196.07:53:50.99#ibcon#end of sib2, iclass 36, count 2 2006.196.07:53:50.99#ibcon#*mode == 0, iclass 36, count 2 2006.196.07:53:50.99#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.196.07:53:50.99#ibcon#[27=AT02-04\r\n] 2006.196.07:53:50.99#ibcon#*before write, iclass 36, count 2 2006.196.07:53:50.99#ibcon#enter sib2, iclass 36, count 2 2006.196.07:53:50.99#ibcon#flushed, iclass 36, count 2 2006.196.07:53:50.99#ibcon#about to write, iclass 36, count 2 2006.196.07:53:50.99#ibcon#wrote, iclass 36, count 2 2006.196.07:53:50.99#ibcon#about to read 3, iclass 36, count 2 2006.196.07:53:51.02#ibcon#read 3, iclass 36, count 2 2006.196.07:53:51.02#ibcon#about to read 4, iclass 36, count 2 2006.196.07:53:51.02#ibcon#read 4, iclass 36, count 2 2006.196.07:53:51.02#ibcon#about to read 5, iclass 36, count 2 2006.196.07:53:51.02#ibcon#read 5, iclass 36, count 2 2006.196.07:53:51.02#ibcon#about to read 6, iclass 36, count 2 2006.196.07:53:51.02#ibcon#read 6, iclass 36, count 2 2006.196.07:53:51.02#ibcon#end of sib2, iclass 36, count 2 2006.196.07:53:51.02#ibcon#*after write, iclass 36, count 2 2006.196.07:53:51.02#ibcon#*before return 0, iclass 36, count 2 2006.196.07:53:51.02#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.196.07:53:51.02#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.196.07:53:51.02#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.196.07:53:51.02#ibcon#ireg 7 cls_cnt 0 2006.196.07:53:51.02#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.196.07:53:51.14#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.196.07:53:51.14#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.196.07:53:51.14#ibcon#enter wrdev, iclass 36, count 0 2006.196.07:53:51.14#ibcon#first serial, iclass 36, count 0 2006.196.07:53:51.14#ibcon#enter sib2, iclass 36, count 0 2006.196.07:53:51.14#ibcon#flushed, iclass 36, count 0 2006.196.07:53:51.14#ibcon#about to write, iclass 36, count 0 2006.196.07:53:51.14#ibcon#wrote, iclass 36, count 0 2006.196.07:53:51.14#ibcon#about to read 3, iclass 36, count 0 2006.196.07:53:51.16#ibcon#read 3, iclass 36, count 0 2006.196.07:53:51.16#ibcon#about to read 4, iclass 36, count 0 2006.196.07:53:51.16#ibcon#read 4, iclass 36, count 0 2006.196.07:53:51.16#ibcon#about to read 5, iclass 36, count 0 2006.196.07:53:51.16#ibcon#read 5, iclass 36, count 0 2006.196.07:53:51.16#ibcon#about to read 6, iclass 36, count 0 2006.196.07:53:51.16#ibcon#read 6, iclass 36, count 0 2006.196.07:53:51.16#ibcon#end of sib2, iclass 36, count 0 2006.196.07:53:51.16#ibcon#*mode == 0, iclass 36, count 0 2006.196.07:53:51.16#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.196.07:53:51.16#ibcon#[27=USB\r\n] 2006.196.07:53:51.16#ibcon#*before write, iclass 36, count 0 2006.196.07:53:51.16#ibcon#enter sib2, iclass 36, count 0 2006.196.07:53:51.16#ibcon#flushed, iclass 36, count 0 2006.196.07:53:51.16#ibcon#about to write, iclass 36, count 0 2006.196.07:53:51.16#ibcon#wrote, iclass 36, count 0 2006.196.07:53:51.16#ibcon#about to read 3, iclass 36, count 0 2006.196.07:53:51.19#ibcon#read 3, iclass 36, count 0 2006.196.07:53:51.19#ibcon#about to read 4, iclass 36, count 0 2006.196.07:53:51.19#ibcon#read 4, iclass 36, count 0 2006.196.07:53:51.19#ibcon#about to read 5, iclass 36, count 0 2006.196.07:53:51.19#ibcon#read 5, iclass 36, count 0 2006.196.07:53:51.19#ibcon#about to read 6, iclass 36, count 0 2006.196.07:53:51.19#ibcon#read 6, iclass 36, count 0 2006.196.07:53:51.19#ibcon#end of sib2, iclass 36, count 0 2006.196.07:53:51.19#ibcon#*after write, iclass 36, count 0 2006.196.07:53:51.19#ibcon#*before return 0, iclass 36, count 0 2006.196.07:53:51.19#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.196.07:53:51.19#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.196.07:53:51.19#ibcon#about to clear, iclass 36 cls_cnt 0 2006.196.07:53:51.19#ibcon#cleared, iclass 36 cls_cnt 0 2006.196.07:53:51.19$vc4f8/vblo=3,656.99 2006.196.07:53:51.19#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.196.07:53:51.19#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.196.07:53:51.19#ibcon#ireg 17 cls_cnt 0 2006.196.07:53:51.19#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.196.07:53:51.19#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.196.07:53:51.19#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.196.07:53:51.19#ibcon#enter wrdev, iclass 38, count 0 2006.196.07:53:51.19#ibcon#first serial, iclass 38, count 0 2006.196.07:53:51.19#ibcon#enter sib2, iclass 38, count 0 2006.196.07:53:51.19#ibcon#flushed, iclass 38, count 0 2006.196.07:53:51.19#ibcon#about to write, iclass 38, count 0 2006.196.07:53:51.19#ibcon#wrote, iclass 38, count 0 2006.196.07:53:51.19#ibcon#about to read 3, iclass 38, count 0 2006.196.07:53:51.21#ibcon#read 3, iclass 38, count 0 2006.196.07:53:51.21#ibcon#about to read 4, iclass 38, count 0 2006.196.07:53:51.21#ibcon#read 4, iclass 38, count 0 2006.196.07:53:51.21#ibcon#about to read 5, iclass 38, count 0 2006.196.07:53:51.21#ibcon#read 5, iclass 38, count 0 2006.196.07:53:51.21#ibcon#about to read 6, iclass 38, count 0 2006.196.07:53:51.21#ibcon#read 6, iclass 38, count 0 2006.196.07:53:51.21#ibcon#end of sib2, iclass 38, count 0 2006.196.07:53:51.21#ibcon#*mode == 0, iclass 38, count 0 2006.196.07:53:51.21#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.196.07:53:51.21#ibcon#[28=FRQ=03,656.99\r\n] 2006.196.07:53:51.21#ibcon#*before write, iclass 38, count 0 2006.196.07:53:51.21#ibcon#enter sib2, iclass 38, count 0 2006.196.07:53:51.21#ibcon#flushed, iclass 38, count 0 2006.196.07:53:51.21#ibcon#about to write, iclass 38, count 0 2006.196.07:53:51.21#ibcon#wrote, iclass 38, count 0 2006.196.07:53:51.21#ibcon#about to read 3, iclass 38, count 0 2006.196.07:53:51.25#ibcon#read 3, iclass 38, count 0 2006.196.07:53:51.25#ibcon#about to read 4, iclass 38, count 0 2006.196.07:53:51.25#ibcon#read 4, iclass 38, count 0 2006.196.07:53:51.25#ibcon#about to read 5, iclass 38, count 0 2006.196.07:53:51.25#ibcon#read 5, iclass 38, count 0 2006.196.07:53:51.25#ibcon#about to read 6, iclass 38, count 0 2006.196.07:53:51.25#ibcon#read 6, iclass 38, count 0 2006.196.07:53:51.25#ibcon#end of sib2, iclass 38, count 0 2006.196.07:53:51.25#ibcon#*after write, iclass 38, count 0 2006.196.07:53:51.25#ibcon#*before return 0, iclass 38, count 0 2006.196.07:53:51.25#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.196.07:53:51.25#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.196.07:53:51.25#ibcon#about to clear, iclass 38 cls_cnt 0 2006.196.07:53:51.25#ibcon#cleared, iclass 38 cls_cnt 0 2006.196.07:53:51.25$vc4f8/vb=3,4 2006.196.07:53:51.25#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.196.07:53:51.25#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.196.07:53:51.25#ibcon#ireg 11 cls_cnt 2 2006.196.07:53:51.25#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.196.07:53:51.31#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.196.07:53:51.31#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.196.07:53:51.31#ibcon#enter wrdev, iclass 40, count 2 2006.196.07:53:51.31#ibcon#first serial, iclass 40, count 2 2006.196.07:53:51.31#ibcon#enter sib2, iclass 40, count 2 2006.196.07:53:51.31#ibcon#flushed, iclass 40, count 2 2006.196.07:53:51.31#ibcon#about to write, iclass 40, count 2 2006.196.07:53:51.31#ibcon#wrote, iclass 40, count 2 2006.196.07:53:51.31#ibcon#about to read 3, iclass 40, count 2 2006.196.07:53:51.33#ibcon#read 3, iclass 40, count 2 2006.196.07:53:51.33#ibcon#about to read 4, iclass 40, count 2 2006.196.07:53:51.33#ibcon#read 4, iclass 40, count 2 2006.196.07:53:51.33#ibcon#about to read 5, iclass 40, count 2 2006.196.07:53:51.33#ibcon#read 5, iclass 40, count 2 2006.196.07:53:51.33#ibcon#about to read 6, iclass 40, count 2 2006.196.07:53:51.33#ibcon#read 6, iclass 40, count 2 2006.196.07:53:51.33#ibcon#end of sib2, iclass 40, count 2 2006.196.07:53:51.33#ibcon#*mode == 0, iclass 40, count 2 2006.196.07:53:51.33#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.196.07:53:51.33#ibcon#[27=AT03-04\r\n] 2006.196.07:53:51.33#ibcon#*before write, iclass 40, count 2 2006.196.07:53:51.33#ibcon#enter sib2, iclass 40, count 2 2006.196.07:53:51.33#ibcon#flushed, iclass 40, count 2 2006.196.07:53:51.33#ibcon#about to write, iclass 40, count 2 2006.196.07:53:51.33#ibcon#wrote, iclass 40, count 2 2006.196.07:53:51.33#ibcon#about to read 3, iclass 40, count 2 2006.196.07:53:51.36#ibcon#read 3, iclass 40, count 2 2006.196.07:53:51.36#ibcon#about to read 4, iclass 40, count 2 2006.196.07:53:51.36#ibcon#read 4, iclass 40, count 2 2006.196.07:53:51.36#ibcon#about to read 5, iclass 40, count 2 2006.196.07:53:51.36#ibcon#read 5, iclass 40, count 2 2006.196.07:53:51.36#ibcon#about to read 6, iclass 40, count 2 2006.196.07:53:51.36#ibcon#read 6, iclass 40, count 2 2006.196.07:53:51.36#ibcon#end of sib2, iclass 40, count 2 2006.196.07:53:51.36#ibcon#*after write, iclass 40, count 2 2006.196.07:53:51.36#ibcon#*before return 0, iclass 40, count 2 2006.196.07:53:51.36#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.196.07:53:51.36#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.196.07:53:51.36#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.196.07:53:51.36#ibcon#ireg 7 cls_cnt 0 2006.196.07:53:51.36#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.196.07:53:51.48#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.196.07:53:51.48#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.196.07:53:51.48#ibcon#enter wrdev, iclass 40, count 0 2006.196.07:53:51.48#ibcon#first serial, iclass 40, count 0 2006.196.07:53:51.48#ibcon#enter sib2, iclass 40, count 0 2006.196.07:53:51.48#ibcon#flushed, iclass 40, count 0 2006.196.07:53:51.48#ibcon#about to write, iclass 40, count 0 2006.196.07:53:51.48#ibcon#wrote, iclass 40, count 0 2006.196.07:53:51.48#ibcon#about to read 3, iclass 40, count 0 2006.196.07:53:51.50#ibcon#read 3, iclass 40, count 0 2006.196.07:53:51.50#ibcon#about to read 4, iclass 40, count 0 2006.196.07:53:51.50#ibcon#read 4, iclass 40, count 0 2006.196.07:53:51.50#ibcon#about to read 5, iclass 40, count 0 2006.196.07:53:51.50#ibcon#read 5, iclass 40, count 0 2006.196.07:53:51.50#ibcon#about to read 6, iclass 40, count 0 2006.196.07:53:51.50#ibcon#read 6, iclass 40, count 0 2006.196.07:53:51.50#ibcon#end of sib2, iclass 40, count 0 2006.196.07:53:51.50#ibcon#*mode == 0, iclass 40, count 0 2006.196.07:53:51.50#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.196.07:53:51.50#ibcon#[27=USB\r\n] 2006.196.07:53:51.50#ibcon#*before write, iclass 40, count 0 2006.196.07:53:51.50#ibcon#enter sib2, iclass 40, count 0 2006.196.07:53:51.50#ibcon#flushed, iclass 40, count 0 2006.196.07:53:51.50#ibcon#about to write, iclass 40, count 0 2006.196.07:53:51.50#ibcon#wrote, iclass 40, count 0 2006.196.07:53:51.50#ibcon#about to read 3, iclass 40, count 0 2006.196.07:53:51.53#ibcon#read 3, iclass 40, count 0 2006.196.07:53:51.53#ibcon#about to read 4, iclass 40, count 0 2006.196.07:53:51.53#ibcon#read 4, iclass 40, count 0 2006.196.07:53:51.53#ibcon#about to read 5, iclass 40, count 0 2006.196.07:53:51.53#ibcon#read 5, iclass 40, count 0 2006.196.07:53:51.53#ibcon#about to read 6, iclass 40, count 0 2006.196.07:53:51.53#ibcon#read 6, iclass 40, count 0 2006.196.07:53:51.53#ibcon#end of sib2, iclass 40, count 0 2006.196.07:53:51.53#ibcon#*after write, iclass 40, count 0 2006.196.07:53:51.53#ibcon#*before return 0, iclass 40, count 0 2006.196.07:53:51.53#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.196.07:53:51.53#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.196.07:53:51.53#ibcon#about to clear, iclass 40 cls_cnt 0 2006.196.07:53:51.53#ibcon#cleared, iclass 40 cls_cnt 0 2006.196.07:53:51.53$vc4f8/vblo=4,712.99 2006.196.07:53:51.53#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.196.07:53:51.53#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.196.07:53:51.53#ibcon#ireg 17 cls_cnt 0 2006.196.07:53:51.53#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.196.07:53:51.53#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.196.07:53:51.53#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.196.07:53:51.53#ibcon#enter wrdev, iclass 4, count 0 2006.196.07:53:51.53#ibcon#first serial, iclass 4, count 0 2006.196.07:53:51.53#ibcon#enter sib2, iclass 4, count 0 2006.196.07:53:51.53#ibcon#flushed, iclass 4, count 0 2006.196.07:53:51.53#ibcon#about to write, iclass 4, count 0 2006.196.07:53:51.53#ibcon#wrote, iclass 4, count 0 2006.196.07:53:51.53#ibcon#about to read 3, iclass 4, count 0 2006.196.07:53:51.55#ibcon#read 3, iclass 4, count 0 2006.196.07:53:51.55#ibcon#about to read 4, iclass 4, count 0 2006.196.07:53:51.55#ibcon#read 4, iclass 4, count 0 2006.196.07:53:51.55#ibcon#about to read 5, iclass 4, count 0 2006.196.07:53:51.55#ibcon#read 5, iclass 4, count 0 2006.196.07:53:51.55#ibcon#about to read 6, iclass 4, count 0 2006.196.07:53:51.55#ibcon#read 6, iclass 4, count 0 2006.196.07:53:51.55#ibcon#end of sib2, iclass 4, count 0 2006.196.07:53:51.55#ibcon#*mode == 0, iclass 4, count 0 2006.196.07:53:51.55#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.196.07:53:51.55#ibcon#[28=FRQ=04,712.99\r\n] 2006.196.07:53:51.55#ibcon#*before write, iclass 4, count 0 2006.196.07:53:51.55#ibcon#enter sib2, iclass 4, count 0 2006.196.07:53:51.55#ibcon#flushed, iclass 4, count 0 2006.196.07:53:51.55#ibcon#about to write, iclass 4, count 0 2006.196.07:53:51.55#ibcon#wrote, iclass 4, count 0 2006.196.07:53:51.55#ibcon#about to read 3, iclass 4, count 0 2006.196.07:53:51.59#ibcon#read 3, iclass 4, count 0 2006.196.07:53:51.59#ibcon#about to read 4, iclass 4, count 0 2006.196.07:53:51.59#ibcon#read 4, iclass 4, count 0 2006.196.07:53:51.59#ibcon#about to read 5, iclass 4, count 0 2006.196.07:53:51.59#ibcon#read 5, iclass 4, count 0 2006.196.07:53:51.59#ibcon#about to read 6, iclass 4, count 0 2006.196.07:53:51.59#ibcon#read 6, iclass 4, count 0 2006.196.07:53:51.59#ibcon#end of sib2, iclass 4, count 0 2006.196.07:53:51.59#ibcon#*after write, iclass 4, count 0 2006.196.07:53:51.59#ibcon#*before return 0, iclass 4, count 0 2006.196.07:53:51.59#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.196.07:53:51.59#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.196.07:53:51.59#ibcon#about to clear, iclass 4 cls_cnt 0 2006.196.07:53:51.59#ibcon#cleared, iclass 4 cls_cnt 0 2006.196.07:53:51.59$vc4f8/vb=4,4 2006.196.07:53:51.59#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.196.07:53:51.59#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.196.07:53:51.59#ibcon#ireg 11 cls_cnt 2 2006.196.07:53:51.59#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.196.07:53:51.65#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.196.07:53:51.65#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.196.07:53:51.65#ibcon#enter wrdev, iclass 6, count 2 2006.196.07:53:51.65#ibcon#first serial, iclass 6, count 2 2006.196.07:53:51.65#ibcon#enter sib2, iclass 6, count 2 2006.196.07:53:51.65#ibcon#flushed, iclass 6, count 2 2006.196.07:53:51.65#ibcon#about to write, iclass 6, count 2 2006.196.07:53:51.65#ibcon#wrote, iclass 6, count 2 2006.196.07:53:51.65#ibcon#about to read 3, iclass 6, count 2 2006.196.07:53:51.67#ibcon#read 3, iclass 6, count 2 2006.196.07:53:51.67#ibcon#about to read 4, iclass 6, count 2 2006.196.07:53:51.67#ibcon#read 4, iclass 6, count 2 2006.196.07:53:51.67#ibcon#about to read 5, iclass 6, count 2 2006.196.07:53:51.67#ibcon#read 5, iclass 6, count 2 2006.196.07:53:51.67#ibcon#about to read 6, iclass 6, count 2 2006.196.07:53:51.67#ibcon#read 6, iclass 6, count 2 2006.196.07:53:51.67#ibcon#end of sib2, iclass 6, count 2 2006.196.07:53:51.67#ibcon#*mode == 0, iclass 6, count 2 2006.196.07:53:51.67#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.196.07:53:51.67#ibcon#[27=AT04-04\r\n] 2006.196.07:53:51.67#ibcon#*before write, iclass 6, count 2 2006.196.07:53:51.67#ibcon#enter sib2, iclass 6, count 2 2006.196.07:53:51.67#ibcon#flushed, iclass 6, count 2 2006.196.07:53:51.67#ibcon#about to write, iclass 6, count 2 2006.196.07:53:51.67#ibcon#wrote, iclass 6, count 2 2006.196.07:53:51.67#ibcon#about to read 3, iclass 6, count 2 2006.196.07:53:51.70#ibcon#read 3, iclass 6, count 2 2006.196.07:53:51.70#ibcon#about to read 4, iclass 6, count 2 2006.196.07:53:51.70#ibcon#read 4, iclass 6, count 2 2006.196.07:53:51.70#ibcon#about to read 5, iclass 6, count 2 2006.196.07:53:51.70#ibcon#read 5, iclass 6, count 2 2006.196.07:53:51.70#ibcon#about to read 6, iclass 6, count 2 2006.196.07:53:51.70#ibcon#read 6, iclass 6, count 2 2006.196.07:53:51.70#ibcon#end of sib2, iclass 6, count 2 2006.196.07:53:51.70#ibcon#*after write, iclass 6, count 2 2006.196.07:53:51.70#ibcon#*before return 0, iclass 6, count 2 2006.196.07:53:51.70#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.196.07:53:51.70#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.196.07:53:51.70#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.196.07:53:51.70#ibcon#ireg 7 cls_cnt 0 2006.196.07:53:51.70#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.196.07:53:51.82#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.196.07:53:51.82#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.196.07:53:51.82#ibcon#enter wrdev, iclass 6, count 0 2006.196.07:53:51.82#ibcon#first serial, iclass 6, count 0 2006.196.07:53:51.82#ibcon#enter sib2, iclass 6, count 0 2006.196.07:53:51.82#ibcon#flushed, iclass 6, count 0 2006.196.07:53:51.82#ibcon#about to write, iclass 6, count 0 2006.196.07:53:51.82#ibcon#wrote, iclass 6, count 0 2006.196.07:53:51.82#ibcon#about to read 3, iclass 6, count 0 2006.196.07:53:51.84#ibcon#read 3, iclass 6, count 0 2006.196.07:53:51.84#ibcon#about to read 4, iclass 6, count 0 2006.196.07:53:51.84#ibcon#read 4, iclass 6, count 0 2006.196.07:53:51.84#ibcon#about to read 5, iclass 6, count 0 2006.196.07:53:51.84#ibcon#read 5, iclass 6, count 0 2006.196.07:53:51.84#ibcon#about to read 6, iclass 6, count 0 2006.196.07:53:51.84#ibcon#read 6, iclass 6, count 0 2006.196.07:53:51.84#ibcon#end of sib2, iclass 6, count 0 2006.196.07:53:51.84#ibcon#*mode == 0, iclass 6, count 0 2006.196.07:53:51.84#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.196.07:53:51.84#ibcon#[27=USB\r\n] 2006.196.07:53:51.84#ibcon#*before write, iclass 6, count 0 2006.196.07:53:51.84#ibcon#enter sib2, iclass 6, count 0 2006.196.07:53:51.84#ibcon#flushed, iclass 6, count 0 2006.196.07:53:51.84#ibcon#about to write, iclass 6, count 0 2006.196.07:53:51.84#ibcon#wrote, iclass 6, count 0 2006.196.07:53:51.84#ibcon#about to read 3, iclass 6, count 0 2006.196.07:53:51.87#ibcon#read 3, iclass 6, count 0 2006.196.07:53:51.87#ibcon#about to read 4, iclass 6, count 0 2006.196.07:53:51.87#ibcon#read 4, iclass 6, count 0 2006.196.07:53:51.87#ibcon#about to read 5, iclass 6, count 0 2006.196.07:53:51.87#ibcon#read 5, iclass 6, count 0 2006.196.07:53:51.87#ibcon#about to read 6, iclass 6, count 0 2006.196.07:53:51.87#ibcon#read 6, iclass 6, count 0 2006.196.07:53:51.87#ibcon#end of sib2, iclass 6, count 0 2006.196.07:53:51.87#ibcon#*after write, iclass 6, count 0 2006.196.07:53:51.87#ibcon#*before return 0, iclass 6, count 0 2006.196.07:53:51.87#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.196.07:53:51.87#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.196.07:53:51.87#ibcon#about to clear, iclass 6 cls_cnt 0 2006.196.07:53:51.87#ibcon#cleared, iclass 6 cls_cnt 0 2006.196.07:53:51.87$vc4f8/vblo=5,744.99 2006.196.07:53:51.87#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.196.07:53:51.87#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.196.07:53:51.87#ibcon#ireg 17 cls_cnt 0 2006.196.07:53:51.87#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.196.07:53:51.87#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.196.07:53:51.87#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.196.07:53:51.87#ibcon#enter wrdev, iclass 10, count 0 2006.196.07:53:51.87#ibcon#first serial, iclass 10, count 0 2006.196.07:53:51.87#ibcon#enter sib2, iclass 10, count 0 2006.196.07:53:51.87#ibcon#flushed, iclass 10, count 0 2006.196.07:53:51.87#ibcon#about to write, iclass 10, count 0 2006.196.07:53:51.87#ibcon#wrote, iclass 10, count 0 2006.196.07:53:51.87#ibcon#about to read 3, iclass 10, count 0 2006.196.07:53:51.89#ibcon#read 3, iclass 10, count 0 2006.196.07:53:51.89#ibcon#about to read 4, iclass 10, count 0 2006.196.07:53:51.89#ibcon#read 4, iclass 10, count 0 2006.196.07:53:51.89#ibcon#about to read 5, iclass 10, count 0 2006.196.07:53:51.89#ibcon#read 5, iclass 10, count 0 2006.196.07:53:51.89#ibcon#about to read 6, iclass 10, count 0 2006.196.07:53:51.89#ibcon#read 6, iclass 10, count 0 2006.196.07:53:51.89#ibcon#end of sib2, iclass 10, count 0 2006.196.07:53:51.89#ibcon#*mode == 0, iclass 10, count 0 2006.196.07:53:51.89#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.196.07:53:51.89#ibcon#[28=FRQ=05,744.99\r\n] 2006.196.07:53:51.89#ibcon#*before write, iclass 10, count 0 2006.196.07:53:51.89#ibcon#enter sib2, iclass 10, count 0 2006.196.07:53:51.89#ibcon#flushed, iclass 10, count 0 2006.196.07:53:51.89#ibcon#about to write, iclass 10, count 0 2006.196.07:53:51.89#ibcon#wrote, iclass 10, count 0 2006.196.07:53:51.89#ibcon#about to read 3, iclass 10, count 0 2006.196.07:53:51.94#ibcon#read 3, iclass 10, count 0 2006.196.07:53:51.94#ibcon#about to read 4, iclass 10, count 0 2006.196.07:53:51.94#ibcon#read 4, iclass 10, count 0 2006.196.07:53:51.94#ibcon#about to read 5, iclass 10, count 0 2006.196.07:53:51.94#ibcon#read 5, iclass 10, count 0 2006.196.07:53:51.94#ibcon#about to read 6, iclass 10, count 0 2006.196.07:53:51.94#ibcon#read 6, iclass 10, count 0 2006.196.07:53:51.94#ibcon#end of sib2, iclass 10, count 0 2006.196.07:53:51.94#ibcon#*after write, iclass 10, count 0 2006.196.07:53:51.94#ibcon#*before return 0, iclass 10, count 0 2006.196.07:53:51.94#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.196.07:53:51.94#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.196.07:53:51.94#ibcon#about to clear, iclass 10 cls_cnt 0 2006.196.07:53:51.94#ibcon#cleared, iclass 10 cls_cnt 0 2006.196.07:53:51.94$vc4f8/vb=5,4 2006.196.07:53:51.94#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.196.07:53:51.94#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.196.07:53:51.94#ibcon#ireg 11 cls_cnt 2 2006.196.07:53:51.94#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.196.07:53:51.99#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.196.07:53:51.99#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.196.07:53:51.99#ibcon#enter wrdev, iclass 12, count 2 2006.196.07:53:51.99#ibcon#first serial, iclass 12, count 2 2006.196.07:53:51.99#ibcon#enter sib2, iclass 12, count 2 2006.196.07:53:51.99#ibcon#flushed, iclass 12, count 2 2006.196.07:53:51.99#ibcon#about to write, iclass 12, count 2 2006.196.07:53:51.99#ibcon#wrote, iclass 12, count 2 2006.196.07:53:51.99#ibcon#about to read 3, iclass 12, count 2 2006.196.07:53:52.01#ibcon#read 3, iclass 12, count 2 2006.196.07:53:52.01#ibcon#about to read 4, iclass 12, count 2 2006.196.07:53:52.01#ibcon#read 4, iclass 12, count 2 2006.196.07:53:52.01#ibcon#about to read 5, iclass 12, count 2 2006.196.07:53:52.01#ibcon#read 5, iclass 12, count 2 2006.196.07:53:52.01#ibcon#about to read 6, iclass 12, count 2 2006.196.07:53:52.01#ibcon#read 6, iclass 12, count 2 2006.196.07:53:52.01#ibcon#end of sib2, iclass 12, count 2 2006.196.07:53:52.01#ibcon#*mode == 0, iclass 12, count 2 2006.196.07:53:52.01#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.196.07:53:52.01#ibcon#[27=AT05-04\r\n] 2006.196.07:53:52.01#ibcon#*before write, iclass 12, count 2 2006.196.07:53:52.01#ibcon#enter sib2, iclass 12, count 2 2006.196.07:53:52.01#ibcon#flushed, iclass 12, count 2 2006.196.07:53:52.01#ibcon#about to write, iclass 12, count 2 2006.196.07:53:52.01#ibcon#wrote, iclass 12, count 2 2006.196.07:53:52.01#ibcon#about to read 3, iclass 12, count 2 2006.196.07:53:52.04#ibcon#read 3, iclass 12, count 2 2006.196.07:53:52.04#ibcon#about to read 4, iclass 12, count 2 2006.196.07:53:52.04#ibcon#read 4, iclass 12, count 2 2006.196.07:53:52.04#ibcon#about to read 5, iclass 12, count 2 2006.196.07:53:52.04#ibcon#read 5, iclass 12, count 2 2006.196.07:53:52.04#ibcon#about to read 6, iclass 12, count 2 2006.196.07:53:52.04#ibcon#read 6, iclass 12, count 2 2006.196.07:53:52.04#ibcon#end of sib2, iclass 12, count 2 2006.196.07:53:52.04#ibcon#*after write, iclass 12, count 2 2006.196.07:53:52.04#ibcon#*before return 0, iclass 12, count 2 2006.196.07:53:52.04#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.196.07:53:52.04#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.196.07:53:52.04#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.196.07:53:52.04#ibcon#ireg 7 cls_cnt 0 2006.196.07:53:52.04#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.196.07:53:52.16#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.196.07:53:52.16#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.196.07:53:52.16#ibcon#enter wrdev, iclass 12, count 0 2006.196.07:53:52.16#ibcon#first serial, iclass 12, count 0 2006.196.07:53:52.16#ibcon#enter sib2, iclass 12, count 0 2006.196.07:53:52.16#ibcon#flushed, iclass 12, count 0 2006.196.07:53:52.16#ibcon#about to write, iclass 12, count 0 2006.196.07:53:52.16#ibcon#wrote, iclass 12, count 0 2006.196.07:53:52.16#ibcon#about to read 3, iclass 12, count 0 2006.196.07:53:52.18#ibcon#read 3, iclass 12, count 0 2006.196.07:53:52.18#ibcon#about to read 4, iclass 12, count 0 2006.196.07:53:52.18#ibcon#read 4, iclass 12, count 0 2006.196.07:53:52.18#ibcon#about to read 5, iclass 12, count 0 2006.196.07:53:52.18#ibcon#read 5, iclass 12, count 0 2006.196.07:53:52.18#ibcon#about to read 6, iclass 12, count 0 2006.196.07:53:52.18#ibcon#read 6, iclass 12, count 0 2006.196.07:53:52.18#ibcon#end of sib2, iclass 12, count 0 2006.196.07:53:52.18#ibcon#*mode == 0, iclass 12, count 0 2006.196.07:53:52.18#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.196.07:53:52.18#ibcon#[27=USB\r\n] 2006.196.07:53:52.18#ibcon#*before write, iclass 12, count 0 2006.196.07:53:52.18#ibcon#enter sib2, iclass 12, count 0 2006.196.07:53:52.18#ibcon#flushed, iclass 12, count 0 2006.196.07:53:52.18#ibcon#about to write, iclass 12, count 0 2006.196.07:53:52.18#ibcon#wrote, iclass 12, count 0 2006.196.07:53:52.18#ibcon#about to read 3, iclass 12, count 0 2006.196.07:53:52.21#ibcon#read 3, iclass 12, count 0 2006.196.07:53:52.21#ibcon#about to read 4, iclass 12, count 0 2006.196.07:53:52.21#ibcon#read 4, iclass 12, count 0 2006.196.07:53:52.21#ibcon#about to read 5, iclass 12, count 0 2006.196.07:53:52.21#ibcon#read 5, iclass 12, count 0 2006.196.07:53:52.21#ibcon#about to read 6, iclass 12, count 0 2006.196.07:53:52.21#ibcon#read 6, iclass 12, count 0 2006.196.07:53:52.21#ibcon#end of sib2, iclass 12, count 0 2006.196.07:53:52.21#ibcon#*after write, iclass 12, count 0 2006.196.07:53:52.21#ibcon#*before return 0, iclass 12, count 0 2006.196.07:53:52.21#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.196.07:53:52.21#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.196.07:53:52.21#ibcon#about to clear, iclass 12 cls_cnt 0 2006.196.07:53:52.21#ibcon#cleared, iclass 12 cls_cnt 0 2006.196.07:53:52.21$vc4f8/vblo=6,752.99 2006.196.07:53:52.21#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.196.07:53:52.21#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.196.07:53:52.21#ibcon#ireg 17 cls_cnt 0 2006.196.07:53:52.21#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.196.07:53:52.21#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.196.07:53:52.21#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.196.07:53:52.21#ibcon#enter wrdev, iclass 14, count 0 2006.196.07:53:52.21#ibcon#first serial, iclass 14, count 0 2006.196.07:53:52.21#ibcon#enter sib2, iclass 14, count 0 2006.196.07:53:52.21#ibcon#flushed, iclass 14, count 0 2006.196.07:53:52.21#ibcon#about to write, iclass 14, count 0 2006.196.07:53:52.21#ibcon#wrote, iclass 14, count 0 2006.196.07:53:52.21#ibcon#about to read 3, iclass 14, count 0 2006.196.07:53:52.23#ibcon#read 3, iclass 14, count 0 2006.196.07:53:52.23#ibcon#about to read 4, iclass 14, count 0 2006.196.07:53:52.23#ibcon#read 4, iclass 14, count 0 2006.196.07:53:52.23#ibcon#about to read 5, iclass 14, count 0 2006.196.07:53:52.23#ibcon#read 5, iclass 14, count 0 2006.196.07:53:52.23#ibcon#about to read 6, iclass 14, count 0 2006.196.07:53:52.23#ibcon#read 6, iclass 14, count 0 2006.196.07:53:52.23#ibcon#end of sib2, iclass 14, count 0 2006.196.07:53:52.23#ibcon#*mode == 0, iclass 14, count 0 2006.196.07:53:52.23#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.196.07:53:52.23#ibcon#[28=FRQ=06,752.99\r\n] 2006.196.07:53:52.23#ibcon#*before write, iclass 14, count 0 2006.196.07:53:52.23#ibcon#enter sib2, iclass 14, count 0 2006.196.07:53:52.23#ibcon#flushed, iclass 14, count 0 2006.196.07:53:52.23#ibcon#about to write, iclass 14, count 0 2006.196.07:53:52.23#ibcon#wrote, iclass 14, count 0 2006.196.07:53:52.23#ibcon#about to read 3, iclass 14, count 0 2006.196.07:53:52.27#ibcon#read 3, iclass 14, count 0 2006.196.07:53:52.27#ibcon#about to read 4, iclass 14, count 0 2006.196.07:53:52.27#ibcon#read 4, iclass 14, count 0 2006.196.07:53:52.27#ibcon#about to read 5, iclass 14, count 0 2006.196.07:53:52.27#ibcon#read 5, iclass 14, count 0 2006.196.07:53:52.27#ibcon#about to read 6, iclass 14, count 0 2006.196.07:53:52.27#ibcon#read 6, iclass 14, count 0 2006.196.07:53:52.27#ibcon#end of sib2, iclass 14, count 0 2006.196.07:53:52.27#ibcon#*after write, iclass 14, count 0 2006.196.07:53:52.27#ibcon#*before return 0, iclass 14, count 0 2006.196.07:53:52.27#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.196.07:53:52.27#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.196.07:53:52.27#ibcon#about to clear, iclass 14 cls_cnt 0 2006.196.07:53:52.27#ibcon#cleared, iclass 14 cls_cnt 0 2006.196.07:53:52.27$vc4f8/vb=6,4 2006.196.07:53:52.27#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.196.07:53:52.27#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.196.07:53:52.27#ibcon#ireg 11 cls_cnt 2 2006.196.07:53:52.27#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.196.07:53:52.33#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.196.07:53:52.33#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.196.07:53:52.33#ibcon#enter wrdev, iclass 16, count 2 2006.196.07:53:52.33#ibcon#first serial, iclass 16, count 2 2006.196.07:53:52.33#ibcon#enter sib2, iclass 16, count 2 2006.196.07:53:52.33#ibcon#flushed, iclass 16, count 2 2006.196.07:53:52.33#ibcon#about to write, iclass 16, count 2 2006.196.07:53:52.33#ibcon#wrote, iclass 16, count 2 2006.196.07:53:52.33#ibcon#about to read 3, iclass 16, count 2 2006.196.07:53:52.35#ibcon#read 3, iclass 16, count 2 2006.196.07:53:52.35#ibcon#about to read 4, iclass 16, count 2 2006.196.07:53:52.35#ibcon#read 4, iclass 16, count 2 2006.196.07:53:52.35#ibcon#about to read 5, iclass 16, count 2 2006.196.07:53:52.35#ibcon#read 5, iclass 16, count 2 2006.196.07:53:52.35#ibcon#about to read 6, iclass 16, count 2 2006.196.07:53:52.35#ibcon#read 6, iclass 16, count 2 2006.196.07:53:52.35#ibcon#end of sib2, iclass 16, count 2 2006.196.07:53:52.35#ibcon#*mode == 0, iclass 16, count 2 2006.196.07:53:52.35#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.196.07:53:52.35#ibcon#[27=AT06-04\r\n] 2006.196.07:53:52.35#ibcon#*before write, iclass 16, count 2 2006.196.07:53:52.35#ibcon#enter sib2, iclass 16, count 2 2006.196.07:53:52.35#ibcon#flushed, iclass 16, count 2 2006.196.07:53:52.35#ibcon#about to write, iclass 16, count 2 2006.196.07:53:52.35#ibcon#wrote, iclass 16, count 2 2006.196.07:53:52.35#ibcon#about to read 3, iclass 16, count 2 2006.196.07:53:52.38#ibcon#read 3, iclass 16, count 2 2006.196.07:53:52.38#ibcon#about to read 4, iclass 16, count 2 2006.196.07:53:52.38#ibcon#read 4, iclass 16, count 2 2006.196.07:53:52.38#ibcon#about to read 5, iclass 16, count 2 2006.196.07:53:52.38#ibcon#read 5, iclass 16, count 2 2006.196.07:53:52.38#ibcon#about to read 6, iclass 16, count 2 2006.196.07:53:52.38#ibcon#read 6, iclass 16, count 2 2006.196.07:53:52.38#ibcon#end of sib2, iclass 16, count 2 2006.196.07:53:52.38#ibcon#*after write, iclass 16, count 2 2006.196.07:53:52.38#ibcon#*before return 0, iclass 16, count 2 2006.196.07:53:52.38#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.196.07:53:52.38#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.196.07:53:52.38#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.196.07:53:52.38#ibcon#ireg 7 cls_cnt 0 2006.196.07:53:52.38#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.196.07:53:52.50#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.196.07:53:52.50#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.196.07:53:52.50#ibcon#enter wrdev, iclass 16, count 0 2006.196.07:53:52.50#ibcon#first serial, iclass 16, count 0 2006.196.07:53:52.50#ibcon#enter sib2, iclass 16, count 0 2006.196.07:53:52.50#ibcon#flushed, iclass 16, count 0 2006.196.07:53:52.50#ibcon#about to write, iclass 16, count 0 2006.196.07:53:52.50#ibcon#wrote, iclass 16, count 0 2006.196.07:53:52.50#ibcon#about to read 3, iclass 16, count 0 2006.196.07:53:52.52#ibcon#read 3, iclass 16, count 0 2006.196.07:53:52.52#ibcon#about to read 4, iclass 16, count 0 2006.196.07:53:52.52#ibcon#read 4, iclass 16, count 0 2006.196.07:53:52.52#ibcon#about to read 5, iclass 16, count 0 2006.196.07:53:52.52#ibcon#read 5, iclass 16, count 0 2006.196.07:53:52.52#ibcon#about to read 6, iclass 16, count 0 2006.196.07:53:52.52#ibcon#read 6, iclass 16, count 0 2006.196.07:53:52.52#ibcon#end of sib2, iclass 16, count 0 2006.196.07:53:52.52#ibcon#*mode == 0, iclass 16, count 0 2006.196.07:53:52.52#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.196.07:53:52.52#ibcon#[27=USB\r\n] 2006.196.07:53:52.52#ibcon#*before write, iclass 16, count 0 2006.196.07:53:52.52#ibcon#enter sib2, iclass 16, count 0 2006.196.07:53:52.52#ibcon#flushed, iclass 16, count 0 2006.196.07:53:52.52#ibcon#about to write, iclass 16, count 0 2006.196.07:53:52.52#ibcon#wrote, iclass 16, count 0 2006.196.07:53:52.52#ibcon#about to read 3, iclass 16, count 0 2006.196.07:53:52.55#ibcon#read 3, iclass 16, count 0 2006.196.07:53:52.55#ibcon#about to read 4, iclass 16, count 0 2006.196.07:53:52.55#ibcon#read 4, iclass 16, count 0 2006.196.07:53:52.55#ibcon#about to read 5, iclass 16, count 0 2006.196.07:53:52.55#ibcon#read 5, iclass 16, count 0 2006.196.07:53:52.55#ibcon#about to read 6, iclass 16, count 0 2006.196.07:53:52.55#ibcon#read 6, iclass 16, count 0 2006.196.07:53:52.55#ibcon#end of sib2, iclass 16, count 0 2006.196.07:53:52.55#ibcon#*after write, iclass 16, count 0 2006.196.07:53:52.55#ibcon#*before return 0, iclass 16, count 0 2006.196.07:53:52.55#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.196.07:53:52.55#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.196.07:53:52.55#ibcon#about to clear, iclass 16 cls_cnt 0 2006.196.07:53:52.55#ibcon#cleared, iclass 16 cls_cnt 0 2006.196.07:53:52.55$vc4f8/vabw=wide 2006.196.07:53:52.55#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.196.07:53:52.55#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.196.07:53:52.55#ibcon#ireg 8 cls_cnt 0 2006.196.07:53:52.55#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.196.07:53:52.55#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.196.07:53:52.55#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.196.07:53:52.55#ibcon#enter wrdev, iclass 18, count 0 2006.196.07:53:52.55#ibcon#first serial, iclass 18, count 0 2006.196.07:53:52.55#ibcon#enter sib2, iclass 18, count 0 2006.196.07:53:52.55#ibcon#flushed, iclass 18, count 0 2006.196.07:53:52.55#ibcon#about to write, iclass 18, count 0 2006.196.07:53:52.55#ibcon#wrote, iclass 18, count 0 2006.196.07:53:52.55#ibcon#about to read 3, iclass 18, count 0 2006.196.07:53:52.57#ibcon#read 3, iclass 18, count 0 2006.196.07:53:52.57#ibcon#about to read 4, iclass 18, count 0 2006.196.07:53:52.57#ibcon#read 4, iclass 18, count 0 2006.196.07:53:52.57#ibcon#about to read 5, iclass 18, count 0 2006.196.07:53:52.57#ibcon#read 5, iclass 18, count 0 2006.196.07:53:52.57#ibcon#about to read 6, iclass 18, count 0 2006.196.07:53:52.57#ibcon#read 6, iclass 18, count 0 2006.196.07:53:52.57#ibcon#end of sib2, iclass 18, count 0 2006.196.07:53:52.57#ibcon#*mode == 0, iclass 18, count 0 2006.196.07:53:52.57#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.196.07:53:52.57#ibcon#[25=BW32\r\n] 2006.196.07:53:52.57#ibcon#*before write, iclass 18, count 0 2006.196.07:53:52.57#ibcon#enter sib2, iclass 18, count 0 2006.196.07:53:52.57#ibcon#flushed, iclass 18, count 0 2006.196.07:53:52.57#ibcon#about to write, iclass 18, count 0 2006.196.07:53:52.57#ibcon#wrote, iclass 18, count 0 2006.196.07:53:52.57#ibcon#about to read 3, iclass 18, count 0 2006.196.07:53:52.61#ibcon#read 3, iclass 18, count 0 2006.196.07:53:52.61#ibcon#about to read 4, iclass 18, count 0 2006.196.07:53:52.61#ibcon#read 4, iclass 18, count 0 2006.196.07:53:52.61#ibcon#about to read 5, iclass 18, count 0 2006.196.07:53:52.61#ibcon#read 5, iclass 18, count 0 2006.196.07:53:52.61#ibcon#about to read 6, iclass 18, count 0 2006.196.07:53:52.61#ibcon#read 6, iclass 18, count 0 2006.196.07:53:52.61#ibcon#end of sib2, iclass 18, count 0 2006.196.07:53:52.61#ibcon#*after write, iclass 18, count 0 2006.196.07:53:52.61#ibcon#*before return 0, iclass 18, count 0 2006.196.07:53:52.61#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.196.07:53:52.61#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.196.07:53:52.61#ibcon#about to clear, iclass 18 cls_cnt 0 2006.196.07:53:52.61#ibcon#cleared, iclass 18 cls_cnt 0 2006.196.07:53:52.61$vc4f8/vbbw=wide 2006.196.07:53:52.61#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.196.07:53:52.61#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.196.07:53:52.61#ibcon#ireg 8 cls_cnt 0 2006.196.07:53:52.61#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.196.07:53:52.67#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.196.07:53:52.67#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.196.07:53:52.67#ibcon#enter wrdev, iclass 20, count 0 2006.196.07:53:52.67#ibcon#first serial, iclass 20, count 0 2006.196.07:53:52.67#ibcon#enter sib2, iclass 20, count 0 2006.196.07:53:52.67#ibcon#flushed, iclass 20, count 0 2006.196.07:53:52.67#ibcon#about to write, iclass 20, count 0 2006.196.07:53:52.67#ibcon#wrote, iclass 20, count 0 2006.196.07:53:52.67#ibcon#about to read 3, iclass 20, count 0 2006.196.07:53:52.69#ibcon#read 3, iclass 20, count 0 2006.196.07:53:52.69#ibcon#about to read 4, iclass 20, count 0 2006.196.07:53:52.69#ibcon#read 4, iclass 20, count 0 2006.196.07:53:52.69#ibcon#about to read 5, iclass 20, count 0 2006.196.07:53:52.69#ibcon#read 5, iclass 20, count 0 2006.196.07:53:52.69#ibcon#about to read 6, iclass 20, count 0 2006.196.07:53:52.69#ibcon#read 6, iclass 20, count 0 2006.196.07:53:52.69#ibcon#end of sib2, iclass 20, count 0 2006.196.07:53:52.69#ibcon#*mode == 0, iclass 20, count 0 2006.196.07:53:52.69#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.196.07:53:52.69#ibcon#[27=BW32\r\n] 2006.196.07:53:52.69#ibcon#*before write, iclass 20, count 0 2006.196.07:53:52.69#ibcon#enter sib2, iclass 20, count 0 2006.196.07:53:52.69#ibcon#flushed, iclass 20, count 0 2006.196.07:53:52.69#ibcon#about to write, iclass 20, count 0 2006.196.07:53:52.69#ibcon#wrote, iclass 20, count 0 2006.196.07:53:52.69#ibcon#about to read 3, iclass 20, count 0 2006.196.07:53:52.72#ibcon#read 3, iclass 20, count 0 2006.196.07:53:52.72#ibcon#about to read 4, iclass 20, count 0 2006.196.07:53:52.72#ibcon#read 4, iclass 20, count 0 2006.196.07:53:52.72#ibcon#about to read 5, iclass 20, count 0 2006.196.07:53:52.72#ibcon#read 5, iclass 20, count 0 2006.196.07:53:52.72#ibcon#about to read 6, iclass 20, count 0 2006.196.07:53:52.72#ibcon#read 6, iclass 20, count 0 2006.196.07:53:52.72#ibcon#end of sib2, iclass 20, count 0 2006.196.07:53:52.72#ibcon#*after write, iclass 20, count 0 2006.196.07:53:52.72#ibcon#*before return 0, iclass 20, count 0 2006.196.07:53:52.72#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.196.07:53:52.72#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.196.07:53:52.72#ibcon#about to clear, iclass 20 cls_cnt 0 2006.196.07:53:52.72#ibcon#cleared, iclass 20 cls_cnt 0 2006.196.07:53:52.72$4f8m12a/ifd4f 2006.196.07:53:52.72$ifd4f/lo= 2006.196.07:53:52.72$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.196.07:53:52.72$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.196.07:53:52.72$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.196.07:53:52.72$ifd4f/patch= 2006.196.07:53:52.72$ifd4f/patch=lo1,a1,a2,a3,a4 2006.196.07:53:52.72$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.196.07:53:52.72$ifd4f/patch=lo3,a5,a6,a7,a8 2006.196.07:53:52.72$4f8m12a/"form=m,16.000,1:2 2006.196.07:53:52.72$4f8m12a/"tpicd 2006.196.07:53:52.72$4f8m12a/echo=off 2006.196.07:53:52.72$4f8m12a/xlog=off 2006.196.07:53:52.72:!2006.196.07:54:20 2006.196.07:54:03.14#trakl#Source acquired 2006.196.07:54:05.14#flagr#flagr/antenna,acquired 2006.196.07:54:20.00:preob 2006.196.07:54:21.14/onsource/TRACKING 2006.196.07:54:21.14:!2006.196.07:54:30 2006.196.07:54:30.00:data_valid=on 2006.196.07:54:30.00:midob 2006.196.07:54:30.14/onsource/TRACKING 2006.196.07:54:30.14/wx/29.60,1004.0,89 2006.196.07:54:30.22/cable/+6.3353E-03 2006.196.07:54:31.31/va/01,08,usb,yes,28,30 2006.196.07:54:31.31/va/02,07,usb,yes,28,30 2006.196.07:54:31.31/va/03,06,usb,yes,30,30 2006.196.07:54:31.31/va/04,07,usb,yes,29,32 2006.196.07:54:31.31/va/05,07,usb,yes,31,33 2006.196.07:54:31.31/va/06,06,usb,yes,30,30 2006.196.07:54:31.31/va/07,06,usb,yes,31,30 2006.196.07:54:31.31/va/08,07,usb,yes,29,29 2006.196.07:54:31.54/valo/01,532.99,yes,locked 2006.196.07:54:31.54/valo/02,572.99,yes,locked 2006.196.07:54:31.54/valo/03,672.99,yes,locked 2006.196.07:54:31.54/valo/04,832.99,yes,locked 2006.196.07:54:31.54/valo/05,652.99,yes,locked 2006.196.07:54:31.54/valo/06,772.99,yes,locked 2006.196.07:54:31.54/valo/07,832.99,yes,locked 2006.196.07:54:31.54/valo/08,852.99,yes,locked 2006.196.07:54:32.63/vb/01,04,usb,yes,28,27 2006.196.07:54:32.63/vb/02,04,usb,yes,30,32 2006.196.07:54:32.63/vb/03,04,usb,yes,27,30 2006.196.07:54:32.63/vb/04,04,usb,yes,27,28 2006.196.07:54:32.63/vb/05,04,usb,yes,26,30 2006.196.07:54:32.63/vb/06,04,usb,yes,27,30 2006.196.07:54:32.63/vb/07,04,usb,yes,29,29 2006.196.07:54:32.63/vb/08,04,usb,yes,27,30 2006.196.07:54:32.87/vblo/01,632.99,yes,locked 2006.196.07:54:32.87/vblo/02,640.99,yes,locked 2006.196.07:54:32.87/vblo/03,656.99,yes,locked 2006.196.07:54:32.87/vblo/04,712.99,yes,locked 2006.196.07:54:32.87/vblo/05,744.99,yes,locked 2006.196.07:54:32.87/vblo/06,752.99,yes,locked 2006.196.07:54:32.87/vblo/07,734.99,yes,locked 2006.196.07:54:32.87/vblo/08,744.99,yes,locked 2006.196.07:54:33.02/vabw/8 2006.196.07:54:33.17/vbbw/8 2006.196.07:54:33.26/xfe/off,on,14.7 2006.196.07:54:33.63/ifatt/23,28,28,28 2006.196.07:54:34.07/fmout-gps/S +3.34E-07 2006.196.07:54:34.11:!2006.196.07:55:30 2006.196.07:55:30.00:data_valid=off 2006.196.07:55:30.00:postob 2006.196.07:55:30.10/cable/+6.3351E-03 2006.196.07:55:30.10/wx/29.58,1004.0,90 2006.196.07:55:31.07/fmout-gps/S +3.35E-07 2006.196.07:55:31.07:scan_name=196-0756,k06196,60 2006.196.07:55:31.07:source=0642+449,064632.03,445116.6,2000.0,cw 2006.196.07:55:31.14#flagr#flagr/antenna,new-source 2006.196.07:55:32.14:checkk5 2006.196.07:55:32.51/chk_autoobs//k5ts1/ autoobs is running! 2006.196.07:55:32.88/chk_autoobs//k5ts2/ autoobs is running! 2006.196.07:55:33.26/chk_autoobs//k5ts3/ autoobs is running! 2006.196.07:55:33.63/chk_autoobs//k5ts4/ autoobs is running! 2006.196.07:55:33.99/chk_obsdata//k5ts1/T1960754??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.07:55:34.36/chk_obsdata//k5ts2/T1960754??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.07:55:34.73/chk_obsdata//k5ts3/T1960754??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.07:55:35.10/chk_obsdata//k5ts4/T1960754??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.07:55:35.79/k5log//k5ts1_log_newline 2006.196.07:55:36.48/k5log//k5ts2_log_newline 2006.196.07:55:37.17/k5log//k5ts3_log_newline 2006.196.07:55:37.85/k5log//k5ts4_log_newline 2006.196.07:55:37.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.196.07:55:37.88:4f8m12a=2 2006.196.07:55:37.88$4f8m12a/echo=on 2006.196.07:55:37.88$4f8m12a/pcalon 2006.196.07:55:37.88$pcalon/"no phase cal control is implemented here 2006.196.07:55:37.88$4f8m12a/"tpicd=stop 2006.196.07:55:37.88$4f8m12a/vc4f8 2006.196.07:55:37.88$vc4f8/valo=1,532.99 2006.196.07:55:37.88#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.196.07:55:37.88#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.196.07:55:37.88#ibcon#ireg 17 cls_cnt 0 2006.196.07:55:37.88#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.196.07:55:37.88#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.196.07:55:37.88#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.196.07:55:37.88#ibcon#enter wrdev, iclass 27, count 0 2006.196.07:55:37.88#ibcon#first serial, iclass 27, count 0 2006.196.07:55:37.88#ibcon#enter sib2, iclass 27, count 0 2006.196.07:55:37.88#ibcon#flushed, iclass 27, count 0 2006.196.07:55:37.88#ibcon#about to write, iclass 27, count 0 2006.196.07:55:37.88#ibcon#wrote, iclass 27, count 0 2006.196.07:55:37.88#ibcon#about to read 3, iclass 27, count 0 2006.196.07:55:37.90#ibcon#read 3, iclass 27, count 0 2006.196.07:55:37.90#ibcon#about to read 4, iclass 27, count 0 2006.196.07:55:37.90#ibcon#read 4, iclass 27, count 0 2006.196.07:55:37.90#ibcon#about to read 5, iclass 27, count 0 2006.196.07:55:37.90#ibcon#read 5, iclass 27, count 0 2006.196.07:55:37.90#ibcon#about to read 6, iclass 27, count 0 2006.196.07:55:37.90#ibcon#read 6, iclass 27, count 0 2006.196.07:55:37.90#ibcon#end of sib2, iclass 27, count 0 2006.196.07:55:37.90#ibcon#*mode == 0, iclass 27, count 0 2006.196.07:55:37.90#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.196.07:55:37.90#ibcon#[26=FRQ=01,532.99\r\n] 2006.196.07:55:37.90#ibcon#*before write, iclass 27, count 0 2006.196.07:55:37.90#ibcon#enter sib2, iclass 27, count 0 2006.196.07:55:37.90#ibcon#flushed, iclass 27, count 0 2006.196.07:55:37.90#ibcon#about to write, iclass 27, count 0 2006.196.07:55:37.90#ibcon#wrote, iclass 27, count 0 2006.196.07:55:37.90#ibcon#about to read 3, iclass 27, count 0 2006.196.07:55:37.95#ibcon#read 3, iclass 27, count 0 2006.196.07:55:37.95#ibcon#about to read 4, iclass 27, count 0 2006.196.07:55:37.95#ibcon#read 4, iclass 27, count 0 2006.196.07:55:37.95#ibcon#about to read 5, iclass 27, count 0 2006.196.07:55:37.95#ibcon#read 5, iclass 27, count 0 2006.196.07:55:37.95#ibcon#about to read 6, iclass 27, count 0 2006.196.07:55:37.95#ibcon#read 6, iclass 27, count 0 2006.196.07:55:37.95#ibcon#end of sib2, iclass 27, count 0 2006.196.07:55:37.95#ibcon#*after write, iclass 27, count 0 2006.196.07:55:37.95#ibcon#*before return 0, iclass 27, count 0 2006.196.07:55:37.95#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.196.07:55:37.95#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.196.07:55:37.95#ibcon#about to clear, iclass 27 cls_cnt 0 2006.196.07:55:37.95#ibcon#cleared, iclass 27 cls_cnt 0 2006.196.07:55:37.95$vc4f8/va=1,8 2006.196.07:55:37.95#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.196.07:55:37.95#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.196.07:55:37.95#ibcon#ireg 11 cls_cnt 2 2006.196.07:55:37.95#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.196.07:55:37.95#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.196.07:55:37.95#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.196.07:55:37.95#ibcon#enter wrdev, iclass 29, count 2 2006.196.07:55:37.95#ibcon#first serial, iclass 29, count 2 2006.196.07:55:37.95#ibcon#enter sib2, iclass 29, count 2 2006.196.07:55:37.95#ibcon#flushed, iclass 29, count 2 2006.196.07:55:37.95#ibcon#about to write, iclass 29, count 2 2006.196.07:55:37.95#ibcon#wrote, iclass 29, count 2 2006.196.07:55:37.95#ibcon#about to read 3, iclass 29, count 2 2006.196.07:55:37.97#ibcon#read 3, iclass 29, count 2 2006.196.07:55:37.97#ibcon#about to read 4, iclass 29, count 2 2006.196.07:55:37.97#ibcon#read 4, iclass 29, count 2 2006.196.07:55:37.97#ibcon#about to read 5, iclass 29, count 2 2006.196.07:55:37.97#ibcon#read 5, iclass 29, count 2 2006.196.07:55:37.97#ibcon#about to read 6, iclass 29, count 2 2006.196.07:55:37.97#ibcon#read 6, iclass 29, count 2 2006.196.07:55:37.97#ibcon#end of sib2, iclass 29, count 2 2006.196.07:55:37.97#ibcon#*mode == 0, iclass 29, count 2 2006.196.07:55:37.97#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.196.07:55:37.97#ibcon#[25=AT01-08\r\n] 2006.196.07:55:37.97#ibcon#*before write, iclass 29, count 2 2006.196.07:55:37.97#ibcon#enter sib2, iclass 29, count 2 2006.196.07:55:37.97#ibcon#flushed, iclass 29, count 2 2006.196.07:55:37.97#ibcon#about to write, iclass 29, count 2 2006.196.07:55:37.97#ibcon#wrote, iclass 29, count 2 2006.196.07:55:37.97#ibcon#about to read 3, iclass 29, count 2 2006.196.07:55:38.00#ibcon#read 3, iclass 29, count 2 2006.196.07:55:38.00#ibcon#about to read 4, iclass 29, count 2 2006.196.07:55:38.00#ibcon#read 4, iclass 29, count 2 2006.196.07:55:38.00#ibcon#about to read 5, iclass 29, count 2 2006.196.07:55:38.00#ibcon#read 5, iclass 29, count 2 2006.196.07:55:38.00#ibcon#about to read 6, iclass 29, count 2 2006.196.07:55:38.00#ibcon#read 6, iclass 29, count 2 2006.196.07:55:38.00#ibcon#end of sib2, iclass 29, count 2 2006.196.07:55:38.00#ibcon#*after write, iclass 29, count 2 2006.196.07:55:38.00#ibcon#*before return 0, iclass 29, count 2 2006.196.07:55:38.00#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.196.07:55:38.00#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.196.07:55:38.00#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.196.07:55:38.00#ibcon#ireg 7 cls_cnt 0 2006.196.07:55:38.00#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.196.07:55:38.12#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.196.07:55:38.12#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.196.07:55:38.12#ibcon#enter wrdev, iclass 29, count 0 2006.196.07:55:38.12#ibcon#first serial, iclass 29, count 0 2006.196.07:55:38.12#ibcon#enter sib2, iclass 29, count 0 2006.196.07:55:38.12#ibcon#flushed, iclass 29, count 0 2006.196.07:55:38.12#ibcon#about to write, iclass 29, count 0 2006.196.07:55:38.12#ibcon#wrote, iclass 29, count 0 2006.196.07:55:38.12#ibcon#about to read 3, iclass 29, count 0 2006.196.07:55:38.14#ibcon#read 3, iclass 29, count 0 2006.196.07:55:38.14#ibcon#about to read 4, iclass 29, count 0 2006.196.07:55:38.14#ibcon#read 4, iclass 29, count 0 2006.196.07:55:38.14#ibcon#about to read 5, iclass 29, count 0 2006.196.07:55:38.14#ibcon#read 5, iclass 29, count 0 2006.196.07:55:38.14#ibcon#about to read 6, iclass 29, count 0 2006.196.07:55:38.14#ibcon#read 6, iclass 29, count 0 2006.196.07:55:38.14#ibcon#end of sib2, iclass 29, count 0 2006.196.07:55:38.14#ibcon#*mode == 0, iclass 29, count 0 2006.196.07:55:38.14#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.196.07:55:38.14#ibcon#[25=USB\r\n] 2006.196.07:55:38.14#ibcon#*before write, iclass 29, count 0 2006.196.07:55:38.14#ibcon#enter sib2, iclass 29, count 0 2006.196.07:55:38.14#ibcon#flushed, iclass 29, count 0 2006.196.07:55:38.14#ibcon#about to write, iclass 29, count 0 2006.196.07:55:38.14#ibcon#wrote, iclass 29, count 0 2006.196.07:55:38.14#ibcon#about to read 3, iclass 29, count 0 2006.196.07:55:38.17#ibcon#read 3, iclass 29, count 0 2006.196.07:55:38.17#ibcon#about to read 4, iclass 29, count 0 2006.196.07:55:38.17#ibcon#read 4, iclass 29, count 0 2006.196.07:55:38.17#ibcon#about to read 5, iclass 29, count 0 2006.196.07:55:38.17#ibcon#read 5, iclass 29, count 0 2006.196.07:55:38.17#ibcon#about to read 6, iclass 29, count 0 2006.196.07:55:38.17#ibcon#read 6, iclass 29, count 0 2006.196.07:55:38.17#ibcon#end of sib2, iclass 29, count 0 2006.196.07:55:38.17#ibcon#*after write, iclass 29, count 0 2006.196.07:55:38.17#ibcon#*before return 0, iclass 29, count 0 2006.196.07:55:38.17#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.196.07:55:38.17#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.196.07:55:38.17#ibcon#about to clear, iclass 29 cls_cnt 0 2006.196.07:55:38.17#ibcon#cleared, iclass 29 cls_cnt 0 2006.196.07:55:38.17$vc4f8/valo=2,572.99 2006.196.07:55:38.17#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.196.07:55:38.17#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.196.07:55:38.17#ibcon#ireg 17 cls_cnt 0 2006.196.07:55:38.17#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.196.07:55:38.17#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.196.07:55:38.17#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.196.07:55:38.17#ibcon#enter wrdev, iclass 31, count 0 2006.196.07:55:38.17#ibcon#first serial, iclass 31, count 0 2006.196.07:55:38.17#ibcon#enter sib2, iclass 31, count 0 2006.196.07:55:38.17#ibcon#flushed, iclass 31, count 0 2006.196.07:55:38.17#ibcon#about to write, iclass 31, count 0 2006.196.07:55:38.17#ibcon#wrote, iclass 31, count 0 2006.196.07:55:38.17#ibcon#about to read 3, iclass 31, count 0 2006.196.07:55:38.19#ibcon#read 3, iclass 31, count 0 2006.196.07:55:38.19#ibcon#about to read 4, iclass 31, count 0 2006.196.07:55:38.19#ibcon#read 4, iclass 31, count 0 2006.196.07:55:38.19#ibcon#about to read 5, iclass 31, count 0 2006.196.07:55:38.19#ibcon#read 5, iclass 31, count 0 2006.196.07:55:38.19#ibcon#about to read 6, iclass 31, count 0 2006.196.07:55:38.19#ibcon#read 6, iclass 31, count 0 2006.196.07:55:38.19#ibcon#end of sib2, iclass 31, count 0 2006.196.07:55:38.19#ibcon#*mode == 0, iclass 31, count 0 2006.196.07:55:38.19#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.196.07:55:38.19#ibcon#[26=FRQ=02,572.99\r\n] 2006.196.07:55:38.19#ibcon#*before write, iclass 31, count 0 2006.196.07:55:38.19#ibcon#enter sib2, iclass 31, count 0 2006.196.07:55:38.19#ibcon#flushed, iclass 31, count 0 2006.196.07:55:38.19#ibcon#about to write, iclass 31, count 0 2006.196.07:55:38.19#ibcon#wrote, iclass 31, count 0 2006.196.07:55:38.19#ibcon#about to read 3, iclass 31, count 0 2006.196.07:55:38.24#ibcon#read 3, iclass 31, count 0 2006.196.07:55:38.24#ibcon#about to read 4, iclass 31, count 0 2006.196.07:55:38.24#ibcon#read 4, iclass 31, count 0 2006.196.07:55:38.24#ibcon#about to read 5, iclass 31, count 0 2006.196.07:55:38.24#ibcon#read 5, iclass 31, count 0 2006.196.07:55:38.24#ibcon#about to read 6, iclass 31, count 0 2006.196.07:55:38.24#ibcon#read 6, iclass 31, count 0 2006.196.07:55:38.24#ibcon#end of sib2, iclass 31, count 0 2006.196.07:55:38.24#ibcon#*after write, iclass 31, count 0 2006.196.07:55:38.24#ibcon#*before return 0, iclass 31, count 0 2006.196.07:55:38.24#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.196.07:55:38.24#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.196.07:55:38.24#ibcon#about to clear, iclass 31 cls_cnt 0 2006.196.07:55:38.24#ibcon#cleared, iclass 31 cls_cnt 0 2006.196.07:55:38.24$vc4f8/va=2,7 2006.196.07:55:38.24#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.196.07:55:38.24#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.196.07:55:38.24#ibcon#ireg 11 cls_cnt 2 2006.196.07:55:38.24#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.196.07:55:38.29#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.196.07:55:38.29#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.196.07:55:38.29#ibcon#enter wrdev, iclass 33, count 2 2006.196.07:55:38.29#ibcon#first serial, iclass 33, count 2 2006.196.07:55:38.29#ibcon#enter sib2, iclass 33, count 2 2006.196.07:55:38.29#ibcon#flushed, iclass 33, count 2 2006.196.07:55:38.29#ibcon#about to write, iclass 33, count 2 2006.196.07:55:38.29#ibcon#wrote, iclass 33, count 2 2006.196.07:55:38.29#ibcon#about to read 3, iclass 33, count 2 2006.196.07:55:38.31#ibcon#read 3, iclass 33, count 2 2006.196.07:55:38.31#ibcon#about to read 4, iclass 33, count 2 2006.196.07:55:38.31#ibcon#read 4, iclass 33, count 2 2006.196.07:55:38.31#ibcon#about to read 5, iclass 33, count 2 2006.196.07:55:38.31#ibcon#read 5, iclass 33, count 2 2006.196.07:55:38.31#ibcon#about to read 6, iclass 33, count 2 2006.196.07:55:38.31#ibcon#read 6, iclass 33, count 2 2006.196.07:55:38.31#ibcon#end of sib2, iclass 33, count 2 2006.196.07:55:38.31#ibcon#*mode == 0, iclass 33, count 2 2006.196.07:55:38.31#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.196.07:55:38.31#ibcon#[25=AT02-07\r\n] 2006.196.07:55:38.31#ibcon#*before write, iclass 33, count 2 2006.196.07:55:38.31#ibcon#enter sib2, iclass 33, count 2 2006.196.07:55:38.31#ibcon#flushed, iclass 33, count 2 2006.196.07:55:38.31#ibcon#about to write, iclass 33, count 2 2006.196.07:55:38.31#ibcon#wrote, iclass 33, count 2 2006.196.07:55:38.31#ibcon#about to read 3, iclass 33, count 2 2006.196.07:55:38.34#ibcon#read 3, iclass 33, count 2 2006.196.07:55:38.34#ibcon#about to read 4, iclass 33, count 2 2006.196.07:55:38.34#ibcon#read 4, iclass 33, count 2 2006.196.07:55:38.34#ibcon#about to read 5, iclass 33, count 2 2006.196.07:55:38.34#ibcon#read 5, iclass 33, count 2 2006.196.07:55:38.34#ibcon#about to read 6, iclass 33, count 2 2006.196.07:55:38.34#ibcon#read 6, iclass 33, count 2 2006.196.07:55:38.34#ibcon#end of sib2, iclass 33, count 2 2006.196.07:55:38.34#ibcon#*after write, iclass 33, count 2 2006.196.07:55:38.34#ibcon#*before return 0, iclass 33, count 2 2006.196.07:55:38.34#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.196.07:55:38.34#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.196.07:55:38.34#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.196.07:55:38.34#ibcon#ireg 7 cls_cnt 0 2006.196.07:55:38.34#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.196.07:55:38.46#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.196.07:55:38.46#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.196.07:55:38.46#ibcon#enter wrdev, iclass 33, count 0 2006.196.07:55:38.46#ibcon#first serial, iclass 33, count 0 2006.196.07:55:38.46#ibcon#enter sib2, iclass 33, count 0 2006.196.07:55:38.46#ibcon#flushed, iclass 33, count 0 2006.196.07:55:38.46#ibcon#about to write, iclass 33, count 0 2006.196.07:55:38.46#ibcon#wrote, iclass 33, count 0 2006.196.07:55:38.46#ibcon#about to read 3, iclass 33, count 0 2006.196.07:55:38.48#ibcon#read 3, iclass 33, count 0 2006.196.07:55:38.48#ibcon#about to read 4, iclass 33, count 0 2006.196.07:55:38.48#ibcon#read 4, iclass 33, count 0 2006.196.07:55:38.48#ibcon#about to read 5, iclass 33, count 0 2006.196.07:55:38.48#ibcon#read 5, iclass 33, count 0 2006.196.07:55:38.48#ibcon#about to read 6, iclass 33, count 0 2006.196.07:55:38.48#ibcon#read 6, iclass 33, count 0 2006.196.07:55:38.48#ibcon#end of sib2, iclass 33, count 0 2006.196.07:55:38.48#ibcon#*mode == 0, iclass 33, count 0 2006.196.07:55:38.48#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.196.07:55:38.48#ibcon#[25=USB\r\n] 2006.196.07:55:38.48#ibcon#*before write, iclass 33, count 0 2006.196.07:55:38.48#ibcon#enter sib2, iclass 33, count 0 2006.196.07:55:38.48#ibcon#flushed, iclass 33, count 0 2006.196.07:55:38.48#ibcon#about to write, iclass 33, count 0 2006.196.07:55:38.48#ibcon#wrote, iclass 33, count 0 2006.196.07:55:38.48#ibcon#about to read 3, iclass 33, count 0 2006.196.07:55:38.51#ibcon#read 3, iclass 33, count 0 2006.196.07:55:38.51#ibcon#about to read 4, iclass 33, count 0 2006.196.07:55:38.51#ibcon#read 4, iclass 33, count 0 2006.196.07:55:38.51#ibcon#about to read 5, iclass 33, count 0 2006.196.07:55:38.51#ibcon#read 5, iclass 33, count 0 2006.196.07:55:38.51#ibcon#about to read 6, iclass 33, count 0 2006.196.07:55:38.51#ibcon#read 6, iclass 33, count 0 2006.196.07:55:38.51#ibcon#end of sib2, iclass 33, count 0 2006.196.07:55:38.51#ibcon#*after write, iclass 33, count 0 2006.196.07:55:38.51#ibcon#*before return 0, iclass 33, count 0 2006.196.07:55:38.51#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.196.07:55:38.51#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.196.07:55:38.51#ibcon#about to clear, iclass 33 cls_cnt 0 2006.196.07:55:38.51#ibcon#cleared, iclass 33 cls_cnt 0 2006.196.07:55:38.51$vc4f8/valo=3,672.99 2006.196.07:55:38.51#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.196.07:55:38.51#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.196.07:55:38.51#ibcon#ireg 17 cls_cnt 0 2006.196.07:55:38.51#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.196.07:55:38.51#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.196.07:55:38.51#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.196.07:55:38.51#ibcon#enter wrdev, iclass 35, count 0 2006.196.07:55:38.51#ibcon#first serial, iclass 35, count 0 2006.196.07:55:38.51#ibcon#enter sib2, iclass 35, count 0 2006.196.07:55:38.51#ibcon#flushed, iclass 35, count 0 2006.196.07:55:38.51#ibcon#about to write, iclass 35, count 0 2006.196.07:55:38.51#ibcon#wrote, iclass 35, count 0 2006.196.07:55:38.51#ibcon#about to read 3, iclass 35, count 0 2006.196.07:55:38.53#ibcon#read 3, iclass 35, count 0 2006.196.07:55:38.53#ibcon#about to read 4, iclass 35, count 0 2006.196.07:55:38.53#ibcon#read 4, iclass 35, count 0 2006.196.07:55:38.53#ibcon#about to read 5, iclass 35, count 0 2006.196.07:55:38.53#ibcon#read 5, iclass 35, count 0 2006.196.07:55:38.53#ibcon#about to read 6, iclass 35, count 0 2006.196.07:55:38.53#ibcon#read 6, iclass 35, count 0 2006.196.07:55:38.53#ibcon#end of sib2, iclass 35, count 0 2006.196.07:55:38.53#ibcon#*mode == 0, iclass 35, count 0 2006.196.07:55:38.53#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.196.07:55:38.53#ibcon#[26=FRQ=03,672.99\r\n] 2006.196.07:55:38.53#ibcon#*before write, iclass 35, count 0 2006.196.07:55:38.53#ibcon#enter sib2, iclass 35, count 0 2006.196.07:55:38.53#ibcon#flushed, iclass 35, count 0 2006.196.07:55:38.53#ibcon#about to write, iclass 35, count 0 2006.196.07:55:38.53#ibcon#wrote, iclass 35, count 0 2006.196.07:55:38.53#ibcon#about to read 3, iclass 35, count 0 2006.196.07:55:38.58#ibcon#read 3, iclass 35, count 0 2006.196.07:55:38.58#ibcon#about to read 4, iclass 35, count 0 2006.196.07:55:38.58#ibcon#read 4, iclass 35, count 0 2006.196.07:55:38.58#ibcon#about to read 5, iclass 35, count 0 2006.196.07:55:38.58#ibcon#read 5, iclass 35, count 0 2006.196.07:55:38.58#ibcon#about to read 6, iclass 35, count 0 2006.196.07:55:38.58#ibcon#read 6, iclass 35, count 0 2006.196.07:55:38.58#ibcon#end of sib2, iclass 35, count 0 2006.196.07:55:38.58#ibcon#*after write, iclass 35, count 0 2006.196.07:55:38.58#ibcon#*before return 0, iclass 35, count 0 2006.196.07:55:38.58#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.196.07:55:38.58#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.196.07:55:38.58#ibcon#about to clear, iclass 35 cls_cnt 0 2006.196.07:55:38.58#ibcon#cleared, iclass 35 cls_cnt 0 2006.196.07:55:38.58$vc4f8/va=3,6 2006.196.07:55:38.58#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.196.07:55:38.58#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.196.07:55:38.58#ibcon#ireg 11 cls_cnt 2 2006.196.07:55:38.58#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.196.07:55:38.63#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.196.07:55:38.63#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.196.07:55:38.63#ibcon#enter wrdev, iclass 37, count 2 2006.196.07:55:38.63#ibcon#first serial, iclass 37, count 2 2006.196.07:55:38.63#ibcon#enter sib2, iclass 37, count 2 2006.196.07:55:38.63#ibcon#flushed, iclass 37, count 2 2006.196.07:55:38.63#ibcon#about to write, iclass 37, count 2 2006.196.07:55:38.63#ibcon#wrote, iclass 37, count 2 2006.196.07:55:38.63#ibcon#about to read 3, iclass 37, count 2 2006.196.07:55:38.65#ibcon#read 3, iclass 37, count 2 2006.196.07:55:38.65#ibcon#about to read 4, iclass 37, count 2 2006.196.07:55:38.65#ibcon#read 4, iclass 37, count 2 2006.196.07:55:38.65#ibcon#about to read 5, iclass 37, count 2 2006.196.07:55:38.65#ibcon#read 5, iclass 37, count 2 2006.196.07:55:38.65#ibcon#about to read 6, iclass 37, count 2 2006.196.07:55:38.65#ibcon#read 6, iclass 37, count 2 2006.196.07:55:38.65#ibcon#end of sib2, iclass 37, count 2 2006.196.07:55:38.65#ibcon#*mode == 0, iclass 37, count 2 2006.196.07:55:38.65#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.196.07:55:38.65#ibcon#[25=AT03-06\r\n] 2006.196.07:55:38.65#ibcon#*before write, iclass 37, count 2 2006.196.07:55:38.65#ibcon#enter sib2, iclass 37, count 2 2006.196.07:55:38.65#ibcon#flushed, iclass 37, count 2 2006.196.07:55:38.65#ibcon#about to write, iclass 37, count 2 2006.196.07:55:38.65#ibcon#wrote, iclass 37, count 2 2006.196.07:55:38.65#ibcon#about to read 3, iclass 37, count 2 2006.196.07:55:38.68#ibcon#read 3, iclass 37, count 2 2006.196.07:55:38.68#ibcon#about to read 4, iclass 37, count 2 2006.196.07:55:38.68#ibcon#read 4, iclass 37, count 2 2006.196.07:55:38.68#ibcon#about to read 5, iclass 37, count 2 2006.196.07:55:38.68#ibcon#read 5, iclass 37, count 2 2006.196.07:55:38.68#ibcon#about to read 6, iclass 37, count 2 2006.196.07:55:38.68#ibcon#read 6, iclass 37, count 2 2006.196.07:55:38.68#ibcon#end of sib2, iclass 37, count 2 2006.196.07:55:38.68#ibcon#*after write, iclass 37, count 2 2006.196.07:55:38.68#ibcon#*before return 0, iclass 37, count 2 2006.196.07:55:38.68#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.196.07:55:38.68#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.196.07:55:38.68#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.196.07:55:38.68#ibcon#ireg 7 cls_cnt 0 2006.196.07:55:38.68#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.196.07:55:38.80#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.196.07:55:38.80#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.196.07:55:38.80#ibcon#enter wrdev, iclass 37, count 0 2006.196.07:55:38.80#ibcon#first serial, iclass 37, count 0 2006.196.07:55:38.80#ibcon#enter sib2, iclass 37, count 0 2006.196.07:55:38.80#ibcon#flushed, iclass 37, count 0 2006.196.07:55:38.80#ibcon#about to write, iclass 37, count 0 2006.196.07:55:38.80#ibcon#wrote, iclass 37, count 0 2006.196.07:55:38.80#ibcon#about to read 3, iclass 37, count 0 2006.196.07:55:38.82#ibcon#read 3, iclass 37, count 0 2006.196.07:55:38.82#ibcon#about to read 4, iclass 37, count 0 2006.196.07:55:38.82#ibcon#read 4, iclass 37, count 0 2006.196.07:55:38.82#ibcon#about to read 5, iclass 37, count 0 2006.196.07:55:38.82#ibcon#read 5, iclass 37, count 0 2006.196.07:55:38.82#ibcon#about to read 6, iclass 37, count 0 2006.196.07:55:38.82#ibcon#read 6, iclass 37, count 0 2006.196.07:55:38.82#ibcon#end of sib2, iclass 37, count 0 2006.196.07:55:38.82#ibcon#*mode == 0, iclass 37, count 0 2006.196.07:55:38.82#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.196.07:55:38.82#ibcon#[25=USB\r\n] 2006.196.07:55:38.82#ibcon#*before write, iclass 37, count 0 2006.196.07:55:38.82#ibcon#enter sib2, iclass 37, count 0 2006.196.07:55:38.82#ibcon#flushed, iclass 37, count 0 2006.196.07:55:38.82#ibcon#about to write, iclass 37, count 0 2006.196.07:55:38.82#ibcon#wrote, iclass 37, count 0 2006.196.07:55:38.82#ibcon#about to read 3, iclass 37, count 0 2006.196.07:55:38.85#ibcon#read 3, iclass 37, count 0 2006.196.07:55:38.85#ibcon#about to read 4, iclass 37, count 0 2006.196.07:55:38.85#ibcon#read 4, iclass 37, count 0 2006.196.07:55:38.85#ibcon#about to read 5, iclass 37, count 0 2006.196.07:55:38.85#ibcon#read 5, iclass 37, count 0 2006.196.07:55:38.85#ibcon#about to read 6, iclass 37, count 0 2006.196.07:55:38.85#ibcon#read 6, iclass 37, count 0 2006.196.07:55:38.85#ibcon#end of sib2, iclass 37, count 0 2006.196.07:55:38.85#ibcon#*after write, iclass 37, count 0 2006.196.07:55:38.85#ibcon#*before return 0, iclass 37, count 0 2006.196.07:55:38.85#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.196.07:55:38.85#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.196.07:55:38.85#ibcon#about to clear, iclass 37 cls_cnt 0 2006.196.07:55:38.85#ibcon#cleared, iclass 37 cls_cnt 0 2006.196.07:55:38.85$vc4f8/valo=4,832.99 2006.196.07:55:38.85#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.196.07:55:38.85#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.196.07:55:38.85#ibcon#ireg 17 cls_cnt 0 2006.196.07:55:38.85#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.196.07:55:38.85#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.196.07:55:38.85#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.196.07:55:38.85#ibcon#enter wrdev, iclass 39, count 0 2006.196.07:55:38.85#ibcon#first serial, iclass 39, count 0 2006.196.07:55:38.85#ibcon#enter sib2, iclass 39, count 0 2006.196.07:55:38.85#ibcon#flushed, iclass 39, count 0 2006.196.07:55:38.85#ibcon#about to write, iclass 39, count 0 2006.196.07:55:38.85#ibcon#wrote, iclass 39, count 0 2006.196.07:55:38.85#ibcon#about to read 3, iclass 39, count 0 2006.196.07:55:38.87#ibcon#read 3, iclass 39, count 0 2006.196.07:55:38.87#ibcon#about to read 4, iclass 39, count 0 2006.196.07:55:38.87#ibcon#read 4, iclass 39, count 0 2006.196.07:55:38.87#ibcon#about to read 5, iclass 39, count 0 2006.196.07:55:38.87#ibcon#read 5, iclass 39, count 0 2006.196.07:55:38.87#ibcon#about to read 6, iclass 39, count 0 2006.196.07:55:38.87#ibcon#read 6, iclass 39, count 0 2006.196.07:55:38.87#ibcon#end of sib2, iclass 39, count 0 2006.196.07:55:38.87#ibcon#*mode == 0, iclass 39, count 0 2006.196.07:55:38.87#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.196.07:55:38.87#ibcon#[26=FRQ=04,832.99\r\n] 2006.196.07:55:38.87#ibcon#*before write, iclass 39, count 0 2006.196.07:55:38.87#ibcon#enter sib2, iclass 39, count 0 2006.196.07:55:38.87#ibcon#flushed, iclass 39, count 0 2006.196.07:55:38.87#ibcon#about to write, iclass 39, count 0 2006.196.07:55:38.87#ibcon#wrote, iclass 39, count 0 2006.196.07:55:38.87#ibcon#about to read 3, iclass 39, count 0 2006.196.07:55:38.92#ibcon#read 3, iclass 39, count 0 2006.196.07:55:38.92#ibcon#about to read 4, iclass 39, count 0 2006.196.07:55:38.92#ibcon#read 4, iclass 39, count 0 2006.196.07:55:38.92#ibcon#about to read 5, iclass 39, count 0 2006.196.07:55:38.92#ibcon#read 5, iclass 39, count 0 2006.196.07:55:38.92#ibcon#about to read 6, iclass 39, count 0 2006.196.07:55:38.92#ibcon#read 6, iclass 39, count 0 2006.196.07:55:38.92#ibcon#end of sib2, iclass 39, count 0 2006.196.07:55:38.92#ibcon#*after write, iclass 39, count 0 2006.196.07:55:38.92#ibcon#*before return 0, iclass 39, count 0 2006.196.07:55:38.92#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.196.07:55:38.92#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.196.07:55:38.92#ibcon#about to clear, iclass 39 cls_cnt 0 2006.196.07:55:38.92#ibcon#cleared, iclass 39 cls_cnt 0 2006.196.07:55:38.92$vc4f8/va=4,7 2006.196.07:55:38.92#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.196.07:55:38.92#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.196.07:55:38.92#ibcon#ireg 11 cls_cnt 2 2006.196.07:55:38.92#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.196.07:55:38.97#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.196.07:55:38.97#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.196.07:55:38.97#ibcon#enter wrdev, iclass 3, count 2 2006.196.07:55:38.97#ibcon#first serial, iclass 3, count 2 2006.196.07:55:38.97#ibcon#enter sib2, iclass 3, count 2 2006.196.07:55:38.97#ibcon#flushed, iclass 3, count 2 2006.196.07:55:38.97#ibcon#about to write, iclass 3, count 2 2006.196.07:55:38.97#ibcon#wrote, iclass 3, count 2 2006.196.07:55:38.97#ibcon#about to read 3, iclass 3, count 2 2006.196.07:55:38.99#ibcon#read 3, iclass 3, count 2 2006.196.07:55:38.99#ibcon#about to read 4, iclass 3, count 2 2006.196.07:55:38.99#ibcon#read 4, iclass 3, count 2 2006.196.07:55:38.99#ibcon#about to read 5, iclass 3, count 2 2006.196.07:55:38.99#ibcon#read 5, iclass 3, count 2 2006.196.07:55:38.99#ibcon#about to read 6, iclass 3, count 2 2006.196.07:55:38.99#ibcon#read 6, iclass 3, count 2 2006.196.07:55:38.99#ibcon#end of sib2, iclass 3, count 2 2006.196.07:55:38.99#ibcon#*mode == 0, iclass 3, count 2 2006.196.07:55:38.99#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.196.07:55:38.99#ibcon#[25=AT04-07\r\n] 2006.196.07:55:38.99#ibcon#*before write, iclass 3, count 2 2006.196.07:55:38.99#ibcon#enter sib2, iclass 3, count 2 2006.196.07:55:38.99#ibcon#flushed, iclass 3, count 2 2006.196.07:55:38.99#ibcon#about to write, iclass 3, count 2 2006.196.07:55:38.99#ibcon#wrote, iclass 3, count 2 2006.196.07:55:38.99#ibcon#about to read 3, iclass 3, count 2 2006.196.07:55:39.02#ibcon#read 3, iclass 3, count 2 2006.196.07:55:39.02#ibcon#about to read 4, iclass 3, count 2 2006.196.07:55:39.02#ibcon#read 4, iclass 3, count 2 2006.196.07:55:39.02#ibcon#about to read 5, iclass 3, count 2 2006.196.07:55:39.02#ibcon#read 5, iclass 3, count 2 2006.196.07:55:39.02#ibcon#about to read 6, iclass 3, count 2 2006.196.07:55:39.02#ibcon#read 6, iclass 3, count 2 2006.196.07:55:39.02#ibcon#end of sib2, iclass 3, count 2 2006.196.07:55:39.02#ibcon#*after write, iclass 3, count 2 2006.196.07:55:39.02#ibcon#*before return 0, iclass 3, count 2 2006.196.07:55:39.02#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.196.07:55:39.02#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.196.07:55:39.02#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.196.07:55:39.02#ibcon#ireg 7 cls_cnt 0 2006.196.07:55:39.02#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.196.07:55:39.14#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.196.07:55:39.14#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.196.07:55:39.14#ibcon#enter wrdev, iclass 3, count 0 2006.196.07:55:39.14#ibcon#first serial, iclass 3, count 0 2006.196.07:55:39.14#ibcon#enter sib2, iclass 3, count 0 2006.196.07:55:39.14#ibcon#flushed, iclass 3, count 0 2006.196.07:55:39.14#ibcon#about to write, iclass 3, count 0 2006.196.07:55:39.14#ibcon#wrote, iclass 3, count 0 2006.196.07:55:39.14#ibcon#about to read 3, iclass 3, count 0 2006.196.07:55:39.16#ibcon#read 3, iclass 3, count 0 2006.196.07:55:39.16#ibcon#about to read 4, iclass 3, count 0 2006.196.07:55:39.16#ibcon#read 4, iclass 3, count 0 2006.196.07:55:39.16#ibcon#about to read 5, iclass 3, count 0 2006.196.07:55:39.16#ibcon#read 5, iclass 3, count 0 2006.196.07:55:39.16#ibcon#about to read 6, iclass 3, count 0 2006.196.07:55:39.16#ibcon#read 6, iclass 3, count 0 2006.196.07:55:39.16#ibcon#end of sib2, iclass 3, count 0 2006.196.07:55:39.16#ibcon#*mode == 0, iclass 3, count 0 2006.196.07:55:39.16#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.196.07:55:39.16#ibcon#[25=USB\r\n] 2006.196.07:55:39.16#ibcon#*before write, iclass 3, count 0 2006.196.07:55:39.16#ibcon#enter sib2, iclass 3, count 0 2006.196.07:55:39.16#ibcon#flushed, iclass 3, count 0 2006.196.07:55:39.16#ibcon#about to write, iclass 3, count 0 2006.196.07:55:39.16#ibcon#wrote, iclass 3, count 0 2006.196.07:55:39.16#ibcon#about to read 3, iclass 3, count 0 2006.196.07:55:39.19#ibcon#read 3, iclass 3, count 0 2006.196.07:55:39.19#ibcon#about to read 4, iclass 3, count 0 2006.196.07:55:39.19#ibcon#read 4, iclass 3, count 0 2006.196.07:55:39.19#ibcon#about to read 5, iclass 3, count 0 2006.196.07:55:39.19#ibcon#read 5, iclass 3, count 0 2006.196.07:55:39.19#ibcon#about to read 6, iclass 3, count 0 2006.196.07:55:39.19#ibcon#read 6, iclass 3, count 0 2006.196.07:55:39.19#ibcon#end of sib2, iclass 3, count 0 2006.196.07:55:39.19#ibcon#*after write, iclass 3, count 0 2006.196.07:55:39.19#ibcon#*before return 0, iclass 3, count 0 2006.196.07:55:39.19#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.196.07:55:39.19#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.196.07:55:39.19#ibcon#about to clear, iclass 3 cls_cnt 0 2006.196.07:55:39.19#ibcon#cleared, iclass 3 cls_cnt 0 2006.196.07:55:39.19$vc4f8/valo=5,652.99 2006.196.07:55:39.19#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.196.07:55:39.19#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.196.07:55:39.19#ibcon#ireg 17 cls_cnt 0 2006.196.07:55:39.19#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.196.07:55:39.19#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.196.07:55:39.19#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.196.07:55:39.19#ibcon#enter wrdev, iclass 5, count 0 2006.196.07:55:39.19#ibcon#first serial, iclass 5, count 0 2006.196.07:55:39.19#ibcon#enter sib2, iclass 5, count 0 2006.196.07:55:39.19#ibcon#flushed, iclass 5, count 0 2006.196.07:55:39.19#ibcon#about to write, iclass 5, count 0 2006.196.07:55:39.19#ibcon#wrote, iclass 5, count 0 2006.196.07:55:39.19#ibcon#about to read 3, iclass 5, count 0 2006.196.07:55:39.21#ibcon#read 3, iclass 5, count 0 2006.196.07:55:39.21#ibcon#about to read 4, iclass 5, count 0 2006.196.07:55:39.21#ibcon#read 4, iclass 5, count 0 2006.196.07:55:39.21#ibcon#about to read 5, iclass 5, count 0 2006.196.07:55:39.21#ibcon#read 5, iclass 5, count 0 2006.196.07:55:39.21#ibcon#about to read 6, iclass 5, count 0 2006.196.07:55:39.21#ibcon#read 6, iclass 5, count 0 2006.196.07:55:39.21#ibcon#end of sib2, iclass 5, count 0 2006.196.07:55:39.21#ibcon#*mode == 0, iclass 5, count 0 2006.196.07:55:39.21#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.196.07:55:39.21#ibcon#[26=FRQ=05,652.99\r\n] 2006.196.07:55:39.21#ibcon#*before write, iclass 5, count 0 2006.196.07:55:39.21#ibcon#enter sib2, iclass 5, count 0 2006.196.07:55:39.21#ibcon#flushed, iclass 5, count 0 2006.196.07:55:39.21#ibcon#about to write, iclass 5, count 0 2006.196.07:55:39.21#ibcon#wrote, iclass 5, count 0 2006.196.07:55:39.21#ibcon#about to read 3, iclass 5, count 0 2006.196.07:55:39.25#ibcon#read 3, iclass 5, count 0 2006.196.07:55:39.25#ibcon#about to read 4, iclass 5, count 0 2006.196.07:55:39.25#ibcon#read 4, iclass 5, count 0 2006.196.07:55:39.25#ibcon#about to read 5, iclass 5, count 0 2006.196.07:55:39.25#ibcon#read 5, iclass 5, count 0 2006.196.07:55:39.25#ibcon#about to read 6, iclass 5, count 0 2006.196.07:55:39.25#ibcon#read 6, iclass 5, count 0 2006.196.07:55:39.25#ibcon#end of sib2, iclass 5, count 0 2006.196.07:55:39.25#ibcon#*after write, iclass 5, count 0 2006.196.07:55:39.25#ibcon#*before return 0, iclass 5, count 0 2006.196.07:55:39.25#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.196.07:55:39.25#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.196.07:55:39.25#ibcon#about to clear, iclass 5 cls_cnt 0 2006.196.07:55:39.25#ibcon#cleared, iclass 5 cls_cnt 0 2006.196.07:55:39.25$vc4f8/va=5,7 2006.196.07:55:39.25#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.196.07:55:39.25#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.196.07:55:39.25#ibcon#ireg 11 cls_cnt 2 2006.196.07:55:39.25#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.196.07:55:39.31#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.196.07:55:39.31#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.196.07:55:39.31#ibcon#enter wrdev, iclass 7, count 2 2006.196.07:55:39.31#ibcon#first serial, iclass 7, count 2 2006.196.07:55:39.31#ibcon#enter sib2, iclass 7, count 2 2006.196.07:55:39.31#ibcon#flushed, iclass 7, count 2 2006.196.07:55:39.31#ibcon#about to write, iclass 7, count 2 2006.196.07:55:39.31#ibcon#wrote, iclass 7, count 2 2006.196.07:55:39.31#ibcon#about to read 3, iclass 7, count 2 2006.196.07:55:39.33#ibcon#read 3, iclass 7, count 2 2006.196.07:55:39.33#ibcon#about to read 4, iclass 7, count 2 2006.196.07:55:39.33#ibcon#read 4, iclass 7, count 2 2006.196.07:55:39.33#ibcon#about to read 5, iclass 7, count 2 2006.196.07:55:39.33#ibcon#read 5, iclass 7, count 2 2006.196.07:55:39.33#ibcon#about to read 6, iclass 7, count 2 2006.196.07:55:39.33#ibcon#read 6, iclass 7, count 2 2006.196.07:55:39.33#ibcon#end of sib2, iclass 7, count 2 2006.196.07:55:39.33#ibcon#*mode == 0, iclass 7, count 2 2006.196.07:55:39.33#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.196.07:55:39.33#ibcon#[25=AT05-07\r\n] 2006.196.07:55:39.33#ibcon#*before write, iclass 7, count 2 2006.196.07:55:39.33#ibcon#enter sib2, iclass 7, count 2 2006.196.07:55:39.33#ibcon#flushed, iclass 7, count 2 2006.196.07:55:39.33#ibcon#about to write, iclass 7, count 2 2006.196.07:55:39.33#ibcon#wrote, iclass 7, count 2 2006.196.07:55:39.33#ibcon#about to read 3, iclass 7, count 2 2006.196.07:55:39.36#ibcon#read 3, iclass 7, count 2 2006.196.07:55:39.36#ibcon#about to read 4, iclass 7, count 2 2006.196.07:55:39.36#ibcon#read 4, iclass 7, count 2 2006.196.07:55:39.36#ibcon#about to read 5, iclass 7, count 2 2006.196.07:55:39.36#ibcon#read 5, iclass 7, count 2 2006.196.07:55:39.36#ibcon#about to read 6, iclass 7, count 2 2006.196.07:55:39.36#ibcon#read 6, iclass 7, count 2 2006.196.07:55:39.36#ibcon#end of sib2, iclass 7, count 2 2006.196.07:55:39.36#ibcon#*after write, iclass 7, count 2 2006.196.07:55:39.36#ibcon#*before return 0, iclass 7, count 2 2006.196.07:55:39.36#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.196.07:55:39.36#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.196.07:55:39.36#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.196.07:55:39.36#ibcon#ireg 7 cls_cnt 0 2006.196.07:55:39.36#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.196.07:55:39.48#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.196.07:55:39.48#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.196.07:55:39.48#ibcon#enter wrdev, iclass 7, count 0 2006.196.07:55:39.48#ibcon#first serial, iclass 7, count 0 2006.196.07:55:39.48#ibcon#enter sib2, iclass 7, count 0 2006.196.07:55:39.48#ibcon#flushed, iclass 7, count 0 2006.196.07:55:39.48#ibcon#about to write, iclass 7, count 0 2006.196.07:55:39.48#ibcon#wrote, iclass 7, count 0 2006.196.07:55:39.48#ibcon#about to read 3, iclass 7, count 0 2006.196.07:55:39.50#ibcon#read 3, iclass 7, count 0 2006.196.07:55:39.50#ibcon#about to read 4, iclass 7, count 0 2006.196.07:55:39.50#ibcon#read 4, iclass 7, count 0 2006.196.07:55:39.50#ibcon#about to read 5, iclass 7, count 0 2006.196.07:55:39.50#ibcon#read 5, iclass 7, count 0 2006.196.07:55:39.50#ibcon#about to read 6, iclass 7, count 0 2006.196.07:55:39.50#ibcon#read 6, iclass 7, count 0 2006.196.07:55:39.50#ibcon#end of sib2, iclass 7, count 0 2006.196.07:55:39.50#ibcon#*mode == 0, iclass 7, count 0 2006.196.07:55:39.50#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.196.07:55:39.50#ibcon#[25=USB\r\n] 2006.196.07:55:39.50#ibcon#*before write, iclass 7, count 0 2006.196.07:55:39.50#ibcon#enter sib2, iclass 7, count 0 2006.196.07:55:39.50#ibcon#flushed, iclass 7, count 0 2006.196.07:55:39.50#ibcon#about to write, iclass 7, count 0 2006.196.07:55:39.50#ibcon#wrote, iclass 7, count 0 2006.196.07:55:39.50#ibcon#about to read 3, iclass 7, count 0 2006.196.07:55:39.53#ibcon#read 3, iclass 7, count 0 2006.196.07:55:39.53#ibcon#about to read 4, iclass 7, count 0 2006.196.07:55:39.53#ibcon#read 4, iclass 7, count 0 2006.196.07:55:39.53#ibcon#about to read 5, iclass 7, count 0 2006.196.07:55:39.53#ibcon#read 5, iclass 7, count 0 2006.196.07:55:39.53#ibcon#about to read 6, iclass 7, count 0 2006.196.07:55:39.53#ibcon#read 6, iclass 7, count 0 2006.196.07:55:39.53#ibcon#end of sib2, iclass 7, count 0 2006.196.07:55:39.53#ibcon#*after write, iclass 7, count 0 2006.196.07:55:39.53#ibcon#*before return 0, iclass 7, count 0 2006.196.07:55:39.53#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.196.07:55:39.53#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.196.07:55:39.53#ibcon#about to clear, iclass 7 cls_cnt 0 2006.196.07:55:39.53#ibcon#cleared, iclass 7 cls_cnt 0 2006.196.07:55:39.53$vc4f8/valo=6,772.99 2006.196.07:55:39.53#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.196.07:55:39.53#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.196.07:55:39.53#ibcon#ireg 17 cls_cnt 0 2006.196.07:55:39.53#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.196.07:55:39.53#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.196.07:55:39.53#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.196.07:55:39.53#ibcon#enter wrdev, iclass 11, count 0 2006.196.07:55:39.53#ibcon#first serial, iclass 11, count 0 2006.196.07:55:39.53#ibcon#enter sib2, iclass 11, count 0 2006.196.07:55:39.53#ibcon#flushed, iclass 11, count 0 2006.196.07:55:39.53#ibcon#about to write, iclass 11, count 0 2006.196.07:55:39.53#ibcon#wrote, iclass 11, count 0 2006.196.07:55:39.53#ibcon#about to read 3, iclass 11, count 0 2006.196.07:55:39.55#ibcon#read 3, iclass 11, count 0 2006.196.07:55:39.55#ibcon#about to read 4, iclass 11, count 0 2006.196.07:55:39.55#ibcon#read 4, iclass 11, count 0 2006.196.07:55:39.55#ibcon#about to read 5, iclass 11, count 0 2006.196.07:55:39.55#ibcon#read 5, iclass 11, count 0 2006.196.07:55:39.55#ibcon#about to read 6, iclass 11, count 0 2006.196.07:55:39.55#ibcon#read 6, iclass 11, count 0 2006.196.07:55:39.55#ibcon#end of sib2, iclass 11, count 0 2006.196.07:55:39.55#ibcon#*mode == 0, iclass 11, count 0 2006.196.07:55:39.55#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.196.07:55:39.55#ibcon#[26=FRQ=06,772.99\r\n] 2006.196.07:55:39.55#ibcon#*before write, iclass 11, count 0 2006.196.07:55:39.55#ibcon#enter sib2, iclass 11, count 0 2006.196.07:55:39.55#ibcon#flushed, iclass 11, count 0 2006.196.07:55:39.55#ibcon#about to write, iclass 11, count 0 2006.196.07:55:39.55#ibcon#wrote, iclass 11, count 0 2006.196.07:55:39.55#ibcon#about to read 3, iclass 11, count 0 2006.196.07:55:39.60#ibcon#read 3, iclass 11, count 0 2006.196.07:55:39.60#ibcon#about to read 4, iclass 11, count 0 2006.196.07:55:39.60#ibcon#read 4, iclass 11, count 0 2006.196.07:55:39.60#ibcon#about to read 5, iclass 11, count 0 2006.196.07:55:39.60#ibcon#read 5, iclass 11, count 0 2006.196.07:55:39.60#ibcon#about to read 6, iclass 11, count 0 2006.196.07:55:39.60#ibcon#read 6, iclass 11, count 0 2006.196.07:55:39.60#ibcon#end of sib2, iclass 11, count 0 2006.196.07:55:39.60#ibcon#*after write, iclass 11, count 0 2006.196.07:55:39.60#ibcon#*before return 0, iclass 11, count 0 2006.196.07:55:39.60#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.196.07:55:39.60#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.196.07:55:39.60#ibcon#about to clear, iclass 11 cls_cnt 0 2006.196.07:55:39.60#ibcon#cleared, iclass 11 cls_cnt 0 2006.196.07:55:39.60$vc4f8/va=6,6 2006.196.07:55:39.60#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.196.07:55:39.60#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.196.07:55:39.60#ibcon#ireg 11 cls_cnt 2 2006.196.07:55:39.60#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.196.07:55:39.65#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.196.07:55:39.65#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.196.07:55:39.65#ibcon#enter wrdev, iclass 13, count 2 2006.196.07:55:39.65#ibcon#first serial, iclass 13, count 2 2006.196.07:55:39.65#ibcon#enter sib2, iclass 13, count 2 2006.196.07:55:39.65#ibcon#flushed, iclass 13, count 2 2006.196.07:55:39.65#ibcon#about to write, iclass 13, count 2 2006.196.07:55:39.65#ibcon#wrote, iclass 13, count 2 2006.196.07:55:39.65#ibcon#about to read 3, iclass 13, count 2 2006.196.07:55:39.67#ibcon#read 3, iclass 13, count 2 2006.196.07:55:39.67#ibcon#about to read 4, iclass 13, count 2 2006.196.07:55:39.67#ibcon#read 4, iclass 13, count 2 2006.196.07:55:39.67#ibcon#about to read 5, iclass 13, count 2 2006.196.07:55:39.67#ibcon#read 5, iclass 13, count 2 2006.196.07:55:39.67#ibcon#about to read 6, iclass 13, count 2 2006.196.07:55:39.67#ibcon#read 6, iclass 13, count 2 2006.196.07:55:39.67#ibcon#end of sib2, iclass 13, count 2 2006.196.07:55:39.67#ibcon#*mode == 0, iclass 13, count 2 2006.196.07:55:39.67#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.196.07:55:39.67#ibcon#[25=AT06-06\r\n] 2006.196.07:55:39.67#ibcon#*before write, iclass 13, count 2 2006.196.07:55:39.67#ibcon#enter sib2, iclass 13, count 2 2006.196.07:55:39.67#ibcon#flushed, iclass 13, count 2 2006.196.07:55:39.67#ibcon#about to write, iclass 13, count 2 2006.196.07:55:39.67#ibcon#wrote, iclass 13, count 2 2006.196.07:55:39.67#ibcon#about to read 3, iclass 13, count 2 2006.196.07:55:39.70#ibcon#read 3, iclass 13, count 2 2006.196.07:55:39.70#ibcon#about to read 4, iclass 13, count 2 2006.196.07:55:39.70#ibcon#read 4, iclass 13, count 2 2006.196.07:55:39.70#ibcon#about to read 5, iclass 13, count 2 2006.196.07:55:39.70#ibcon#read 5, iclass 13, count 2 2006.196.07:55:39.70#ibcon#about to read 6, iclass 13, count 2 2006.196.07:55:39.70#ibcon#read 6, iclass 13, count 2 2006.196.07:55:39.70#ibcon#end of sib2, iclass 13, count 2 2006.196.07:55:39.70#ibcon#*after write, iclass 13, count 2 2006.196.07:55:39.70#ibcon#*before return 0, iclass 13, count 2 2006.196.07:55:39.70#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.196.07:55:39.70#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.196.07:55:39.70#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.196.07:55:39.70#ibcon#ireg 7 cls_cnt 0 2006.196.07:55:39.70#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.196.07:55:39.82#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.196.07:55:39.82#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.196.07:55:39.82#ibcon#enter wrdev, iclass 13, count 0 2006.196.07:55:39.82#ibcon#first serial, iclass 13, count 0 2006.196.07:55:39.82#ibcon#enter sib2, iclass 13, count 0 2006.196.07:55:39.82#ibcon#flushed, iclass 13, count 0 2006.196.07:55:39.82#ibcon#about to write, iclass 13, count 0 2006.196.07:55:39.82#ibcon#wrote, iclass 13, count 0 2006.196.07:55:39.82#ibcon#about to read 3, iclass 13, count 0 2006.196.07:55:39.84#ibcon#read 3, iclass 13, count 0 2006.196.07:55:39.84#ibcon#about to read 4, iclass 13, count 0 2006.196.07:55:39.84#ibcon#read 4, iclass 13, count 0 2006.196.07:55:39.84#ibcon#about to read 5, iclass 13, count 0 2006.196.07:55:39.84#ibcon#read 5, iclass 13, count 0 2006.196.07:55:39.84#ibcon#about to read 6, iclass 13, count 0 2006.196.07:55:39.84#ibcon#read 6, iclass 13, count 0 2006.196.07:55:39.84#ibcon#end of sib2, iclass 13, count 0 2006.196.07:55:39.84#ibcon#*mode == 0, iclass 13, count 0 2006.196.07:55:39.84#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.196.07:55:39.84#ibcon#[25=USB\r\n] 2006.196.07:55:39.84#ibcon#*before write, iclass 13, count 0 2006.196.07:55:39.84#ibcon#enter sib2, iclass 13, count 0 2006.196.07:55:39.84#ibcon#flushed, iclass 13, count 0 2006.196.07:55:39.84#ibcon#about to write, iclass 13, count 0 2006.196.07:55:39.84#ibcon#wrote, iclass 13, count 0 2006.196.07:55:39.84#ibcon#about to read 3, iclass 13, count 0 2006.196.07:55:39.87#ibcon#read 3, iclass 13, count 0 2006.196.07:55:39.87#ibcon#about to read 4, iclass 13, count 0 2006.196.07:55:39.87#ibcon#read 4, iclass 13, count 0 2006.196.07:55:39.87#ibcon#about to read 5, iclass 13, count 0 2006.196.07:55:39.87#ibcon#read 5, iclass 13, count 0 2006.196.07:55:39.87#ibcon#about to read 6, iclass 13, count 0 2006.196.07:55:39.87#ibcon#read 6, iclass 13, count 0 2006.196.07:55:39.87#ibcon#end of sib2, iclass 13, count 0 2006.196.07:55:39.87#ibcon#*after write, iclass 13, count 0 2006.196.07:55:39.87#ibcon#*before return 0, iclass 13, count 0 2006.196.07:55:39.87#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.196.07:55:39.87#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.196.07:55:39.87#ibcon#about to clear, iclass 13 cls_cnt 0 2006.196.07:55:39.87#ibcon#cleared, iclass 13 cls_cnt 0 2006.196.07:55:39.87$vc4f8/valo=7,832.99 2006.196.07:55:39.87#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.196.07:55:39.87#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.196.07:55:39.87#ibcon#ireg 17 cls_cnt 0 2006.196.07:55:39.87#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.196.07:55:39.87#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.196.07:55:39.87#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.196.07:55:39.87#ibcon#enter wrdev, iclass 15, count 0 2006.196.07:55:39.87#ibcon#first serial, iclass 15, count 0 2006.196.07:55:39.87#ibcon#enter sib2, iclass 15, count 0 2006.196.07:55:39.87#ibcon#flushed, iclass 15, count 0 2006.196.07:55:39.87#ibcon#about to write, iclass 15, count 0 2006.196.07:55:39.87#ibcon#wrote, iclass 15, count 0 2006.196.07:55:39.87#ibcon#about to read 3, iclass 15, count 0 2006.196.07:55:39.89#ibcon#read 3, iclass 15, count 0 2006.196.07:55:39.89#ibcon#about to read 4, iclass 15, count 0 2006.196.07:55:39.89#ibcon#read 4, iclass 15, count 0 2006.196.07:55:39.89#ibcon#about to read 5, iclass 15, count 0 2006.196.07:55:39.89#ibcon#read 5, iclass 15, count 0 2006.196.07:55:39.89#ibcon#about to read 6, iclass 15, count 0 2006.196.07:55:39.89#ibcon#read 6, iclass 15, count 0 2006.196.07:55:39.89#ibcon#end of sib2, iclass 15, count 0 2006.196.07:55:39.89#ibcon#*mode == 0, iclass 15, count 0 2006.196.07:55:39.89#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.196.07:55:39.89#ibcon#[26=FRQ=07,832.99\r\n] 2006.196.07:55:39.89#ibcon#*before write, iclass 15, count 0 2006.196.07:55:39.89#ibcon#enter sib2, iclass 15, count 0 2006.196.07:55:39.89#ibcon#flushed, iclass 15, count 0 2006.196.07:55:39.89#ibcon#about to write, iclass 15, count 0 2006.196.07:55:39.89#ibcon#wrote, iclass 15, count 0 2006.196.07:55:39.89#ibcon#about to read 3, iclass 15, count 0 2006.196.07:55:39.93#ibcon#read 3, iclass 15, count 0 2006.196.07:55:39.93#ibcon#about to read 4, iclass 15, count 0 2006.196.07:55:39.93#ibcon#read 4, iclass 15, count 0 2006.196.07:55:39.93#ibcon#about to read 5, iclass 15, count 0 2006.196.07:55:39.93#ibcon#read 5, iclass 15, count 0 2006.196.07:55:39.93#ibcon#about to read 6, iclass 15, count 0 2006.196.07:55:39.93#ibcon#read 6, iclass 15, count 0 2006.196.07:55:39.93#ibcon#end of sib2, iclass 15, count 0 2006.196.07:55:39.93#ibcon#*after write, iclass 15, count 0 2006.196.07:55:39.93#ibcon#*before return 0, iclass 15, count 0 2006.196.07:55:39.93#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.196.07:55:39.93#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.196.07:55:39.93#ibcon#about to clear, iclass 15 cls_cnt 0 2006.196.07:55:39.93#ibcon#cleared, iclass 15 cls_cnt 0 2006.196.07:55:39.93$vc4f8/va=7,6 2006.196.07:55:39.93#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.196.07:55:39.93#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.196.07:55:39.93#ibcon#ireg 11 cls_cnt 2 2006.196.07:55:39.93#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.196.07:55:39.99#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.196.07:55:39.99#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.196.07:55:39.99#ibcon#enter wrdev, iclass 17, count 2 2006.196.07:55:39.99#ibcon#first serial, iclass 17, count 2 2006.196.07:55:39.99#ibcon#enter sib2, iclass 17, count 2 2006.196.07:55:39.99#ibcon#flushed, iclass 17, count 2 2006.196.07:55:39.99#ibcon#about to write, iclass 17, count 2 2006.196.07:55:39.99#ibcon#wrote, iclass 17, count 2 2006.196.07:55:39.99#ibcon#about to read 3, iclass 17, count 2 2006.196.07:55:40.01#ibcon#read 3, iclass 17, count 2 2006.196.07:55:40.01#ibcon#about to read 4, iclass 17, count 2 2006.196.07:55:40.01#ibcon#read 4, iclass 17, count 2 2006.196.07:55:40.01#ibcon#about to read 5, iclass 17, count 2 2006.196.07:55:40.01#ibcon#read 5, iclass 17, count 2 2006.196.07:55:40.01#ibcon#about to read 6, iclass 17, count 2 2006.196.07:55:40.01#ibcon#read 6, iclass 17, count 2 2006.196.07:55:40.01#ibcon#end of sib2, iclass 17, count 2 2006.196.07:55:40.01#ibcon#*mode == 0, iclass 17, count 2 2006.196.07:55:40.01#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.196.07:55:40.01#ibcon#[25=AT07-06\r\n] 2006.196.07:55:40.01#ibcon#*before write, iclass 17, count 2 2006.196.07:55:40.01#ibcon#enter sib2, iclass 17, count 2 2006.196.07:55:40.01#ibcon#flushed, iclass 17, count 2 2006.196.07:55:40.01#ibcon#about to write, iclass 17, count 2 2006.196.07:55:40.01#ibcon#wrote, iclass 17, count 2 2006.196.07:55:40.01#ibcon#about to read 3, iclass 17, count 2 2006.196.07:55:40.04#ibcon#read 3, iclass 17, count 2 2006.196.07:55:40.04#ibcon#about to read 4, iclass 17, count 2 2006.196.07:55:40.04#ibcon#read 4, iclass 17, count 2 2006.196.07:55:40.04#ibcon#about to read 5, iclass 17, count 2 2006.196.07:55:40.04#ibcon#read 5, iclass 17, count 2 2006.196.07:55:40.04#ibcon#about to read 6, iclass 17, count 2 2006.196.07:55:40.04#ibcon#read 6, iclass 17, count 2 2006.196.07:55:40.04#ibcon#end of sib2, iclass 17, count 2 2006.196.07:55:40.04#ibcon#*after write, iclass 17, count 2 2006.196.07:55:40.04#ibcon#*before return 0, iclass 17, count 2 2006.196.07:55:40.04#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.196.07:55:40.04#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.196.07:55:40.04#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.196.07:55:40.04#ibcon#ireg 7 cls_cnt 0 2006.196.07:55:40.04#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.196.07:55:40.16#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.196.07:55:40.16#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.196.07:55:40.16#ibcon#enter wrdev, iclass 17, count 0 2006.196.07:55:40.16#ibcon#first serial, iclass 17, count 0 2006.196.07:55:40.16#ibcon#enter sib2, iclass 17, count 0 2006.196.07:55:40.16#ibcon#flushed, iclass 17, count 0 2006.196.07:55:40.16#ibcon#about to write, iclass 17, count 0 2006.196.07:55:40.16#ibcon#wrote, iclass 17, count 0 2006.196.07:55:40.16#ibcon#about to read 3, iclass 17, count 0 2006.196.07:55:40.18#ibcon#read 3, iclass 17, count 0 2006.196.07:55:40.18#ibcon#about to read 4, iclass 17, count 0 2006.196.07:55:40.18#ibcon#read 4, iclass 17, count 0 2006.196.07:55:40.18#ibcon#about to read 5, iclass 17, count 0 2006.196.07:55:40.18#ibcon#read 5, iclass 17, count 0 2006.196.07:55:40.18#ibcon#about to read 6, iclass 17, count 0 2006.196.07:55:40.18#ibcon#read 6, iclass 17, count 0 2006.196.07:55:40.18#ibcon#end of sib2, iclass 17, count 0 2006.196.07:55:40.18#ibcon#*mode == 0, iclass 17, count 0 2006.196.07:55:40.18#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.196.07:55:40.18#ibcon#[25=USB\r\n] 2006.196.07:55:40.18#ibcon#*before write, iclass 17, count 0 2006.196.07:55:40.18#ibcon#enter sib2, iclass 17, count 0 2006.196.07:55:40.18#ibcon#flushed, iclass 17, count 0 2006.196.07:55:40.18#ibcon#about to write, iclass 17, count 0 2006.196.07:55:40.18#ibcon#wrote, iclass 17, count 0 2006.196.07:55:40.18#ibcon#about to read 3, iclass 17, count 0 2006.196.07:55:40.21#ibcon#read 3, iclass 17, count 0 2006.196.07:55:40.21#ibcon#about to read 4, iclass 17, count 0 2006.196.07:55:40.21#ibcon#read 4, iclass 17, count 0 2006.196.07:55:40.21#ibcon#about to read 5, iclass 17, count 0 2006.196.07:55:40.21#ibcon#read 5, iclass 17, count 0 2006.196.07:55:40.21#ibcon#about to read 6, iclass 17, count 0 2006.196.07:55:40.21#ibcon#read 6, iclass 17, count 0 2006.196.07:55:40.21#ibcon#end of sib2, iclass 17, count 0 2006.196.07:55:40.21#ibcon#*after write, iclass 17, count 0 2006.196.07:55:40.21#ibcon#*before return 0, iclass 17, count 0 2006.196.07:55:40.21#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.196.07:55:40.21#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.196.07:55:40.21#ibcon#about to clear, iclass 17 cls_cnt 0 2006.196.07:55:40.21#ibcon#cleared, iclass 17 cls_cnt 0 2006.196.07:55:40.21$vc4f8/valo=8,852.99 2006.196.07:55:40.21#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.196.07:55:40.21#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.196.07:55:40.21#ibcon#ireg 17 cls_cnt 0 2006.196.07:55:40.21#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.196.07:55:40.21#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.196.07:55:40.21#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.196.07:55:40.21#ibcon#enter wrdev, iclass 19, count 0 2006.196.07:55:40.21#ibcon#first serial, iclass 19, count 0 2006.196.07:55:40.21#ibcon#enter sib2, iclass 19, count 0 2006.196.07:55:40.21#ibcon#flushed, iclass 19, count 0 2006.196.07:55:40.21#ibcon#about to write, iclass 19, count 0 2006.196.07:55:40.21#ibcon#wrote, iclass 19, count 0 2006.196.07:55:40.21#ibcon#about to read 3, iclass 19, count 0 2006.196.07:55:40.23#ibcon#read 3, iclass 19, count 0 2006.196.07:55:40.23#ibcon#about to read 4, iclass 19, count 0 2006.196.07:55:40.23#ibcon#read 4, iclass 19, count 0 2006.196.07:55:40.23#ibcon#about to read 5, iclass 19, count 0 2006.196.07:55:40.23#ibcon#read 5, iclass 19, count 0 2006.196.07:55:40.23#ibcon#about to read 6, iclass 19, count 0 2006.196.07:55:40.23#ibcon#read 6, iclass 19, count 0 2006.196.07:55:40.23#ibcon#end of sib2, iclass 19, count 0 2006.196.07:55:40.23#ibcon#*mode == 0, iclass 19, count 0 2006.196.07:55:40.23#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.196.07:55:40.23#ibcon#[26=FRQ=08,852.99\r\n] 2006.196.07:55:40.23#ibcon#*before write, iclass 19, count 0 2006.196.07:55:40.23#ibcon#enter sib2, iclass 19, count 0 2006.196.07:55:40.23#ibcon#flushed, iclass 19, count 0 2006.196.07:55:40.23#ibcon#about to write, iclass 19, count 0 2006.196.07:55:40.23#ibcon#wrote, iclass 19, count 0 2006.196.07:55:40.23#ibcon#about to read 3, iclass 19, count 0 2006.196.07:55:40.27#ibcon#read 3, iclass 19, count 0 2006.196.07:55:40.27#ibcon#about to read 4, iclass 19, count 0 2006.196.07:55:40.27#ibcon#read 4, iclass 19, count 0 2006.196.07:55:40.27#ibcon#about to read 5, iclass 19, count 0 2006.196.07:55:40.27#ibcon#read 5, iclass 19, count 0 2006.196.07:55:40.27#ibcon#about to read 6, iclass 19, count 0 2006.196.07:55:40.27#ibcon#read 6, iclass 19, count 0 2006.196.07:55:40.27#ibcon#end of sib2, iclass 19, count 0 2006.196.07:55:40.27#ibcon#*after write, iclass 19, count 0 2006.196.07:55:40.27#ibcon#*before return 0, iclass 19, count 0 2006.196.07:55:40.27#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.196.07:55:40.27#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.196.07:55:40.27#ibcon#about to clear, iclass 19 cls_cnt 0 2006.196.07:55:40.27#ibcon#cleared, iclass 19 cls_cnt 0 2006.196.07:55:40.27$vc4f8/va=8,7 2006.196.07:55:40.27#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.196.07:55:40.27#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.196.07:55:40.27#ibcon#ireg 11 cls_cnt 2 2006.196.07:55:40.27#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.196.07:55:40.33#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.196.07:55:40.33#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.196.07:55:40.33#ibcon#enter wrdev, iclass 21, count 2 2006.196.07:55:40.33#ibcon#first serial, iclass 21, count 2 2006.196.07:55:40.33#ibcon#enter sib2, iclass 21, count 2 2006.196.07:55:40.33#ibcon#flushed, iclass 21, count 2 2006.196.07:55:40.33#ibcon#about to write, iclass 21, count 2 2006.196.07:55:40.33#ibcon#wrote, iclass 21, count 2 2006.196.07:55:40.33#ibcon#about to read 3, iclass 21, count 2 2006.196.07:55:40.35#ibcon#read 3, iclass 21, count 2 2006.196.07:55:40.35#ibcon#about to read 4, iclass 21, count 2 2006.196.07:55:40.35#ibcon#read 4, iclass 21, count 2 2006.196.07:55:40.35#ibcon#about to read 5, iclass 21, count 2 2006.196.07:55:40.35#ibcon#read 5, iclass 21, count 2 2006.196.07:55:40.35#ibcon#about to read 6, iclass 21, count 2 2006.196.07:55:40.35#ibcon#read 6, iclass 21, count 2 2006.196.07:55:40.35#ibcon#end of sib2, iclass 21, count 2 2006.196.07:55:40.35#ibcon#*mode == 0, iclass 21, count 2 2006.196.07:55:40.35#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.196.07:55:40.35#ibcon#[25=AT08-07\r\n] 2006.196.07:55:40.35#ibcon#*before write, iclass 21, count 2 2006.196.07:55:40.35#ibcon#enter sib2, iclass 21, count 2 2006.196.07:55:40.35#ibcon#flushed, iclass 21, count 2 2006.196.07:55:40.35#ibcon#about to write, iclass 21, count 2 2006.196.07:55:40.35#ibcon#wrote, iclass 21, count 2 2006.196.07:55:40.35#ibcon#about to read 3, iclass 21, count 2 2006.196.07:55:40.38#ibcon#read 3, iclass 21, count 2 2006.196.07:55:40.38#ibcon#about to read 4, iclass 21, count 2 2006.196.07:55:40.38#ibcon#read 4, iclass 21, count 2 2006.196.07:55:40.38#ibcon#about to read 5, iclass 21, count 2 2006.196.07:55:40.38#ibcon#read 5, iclass 21, count 2 2006.196.07:55:40.38#ibcon#about to read 6, iclass 21, count 2 2006.196.07:55:40.38#ibcon#read 6, iclass 21, count 2 2006.196.07:55:40.38#ibcon#end of sib2, iclass 21, count 2 2006.196.07:55:40.38#ibcon#*after write, iclass 21, count 2 2006.196.07:55:40.38#ibcon#*before return 0, iclass 21, count 2 2006.196.07:55:40.38#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.196.07:55:40.38#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.196.07:55:40.38#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.196.07:55:40.38#ibcon#ireg 7 cls_cnt 0 2006.196.07:55:40.38#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.196.07:55:40.50#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.196.07:55:40.50#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.196.07:55:40.50#ibcon#enter wrdev, iclass 21, count 0 2006.196.07:55:40.50#ibcon#first serial, iclass 21, count 0 2006.196.07:55:40.50#ibcon#enter sib2, iclass 21, count 0 2006.196.07:55:40.50#ibcon#flushed, iclass 21, count 0 2006.196.07:55:40.50#ibcon#about to write, iclass 21, count 0 2006.196.07:55:40.50#ibcon#wrote, iclass 21, count 0 2006.196.07:55:40.50#ibcon#about to read 3, iclass 21, count 0 2006.196.07:55:40.52#ibcon#read 3, iclass 21, count 0 2006.196.07:55:40.52#ibcon#about to read 4, iclass 21, count 0 2006.196.07:55:40.52#ibcon#read 4, iclass 21, count 0 2006.196.07:55:40.52#ibcon#about to read 5, iclass 21, count 0 2006.196.07:55:40.52#ibcon#read 5, iclass 21, count 0 2006.196.07:55:40.52#ibcon#about to read 6, iclass 21, count 0 2006.196.07:55:40.52#ibcon#read 6, iclass 21, count 0 2006.196.07:55:40.52#ibcon#end of sib2, iclass 21, count 0 2006.196.07:55:40.52#ibcon#*mode == 0, iclass 21, count 0 2006.196.07:55:40.52#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.196.07:55:40.52#ibcon#[25=USB\r\n] 2006.196.07:55:40.52#ibcon#*before write, iclass 21, count 0 2006.196.07:55:40.52#ibcon#enter sib2, iclass 21, count 0 2006.196.07:55:40.52#ibcon#flushed, iclass 21, count 0 2006.196.07:55:40.52#ibcon#about to write, iclass 21, count 0 2006.196.07:55:40.52#ibcon#wrote, iclass 21, count 0 2006.196.07:55:40.52#ibcon#about to read 3, iclass 21, count 0 2006.196.07:55:40.55#ibcon#read 3, iclass 21, count 0 2006.196.07:55:40.55#ibcon#about to read 4, iclass 21, count 0 2006.196.07:55:40.55#ibcon#read 4, iclass 21, count 0 2006.196.07:55:40.55#ibcon#about to read 5, iclass 21, count 0 2006.196.07:55:40.55#ibcon#read 5, iclass 21, count 0 2006.196.07:55:40.55#ibcon#about to read 6, iclass 21, count 0 2006.196.07:55:40.55#ibcon#read 6, iclass 21, count 0 2006.196.07:55:40.55#ibcon#end of sib2, iclass 21, count 0 2006.196.07:55:40.55#ibcon#*after write, iclass 21, count 0 2006.196.07:55:40.55#ibcon#*before return 0, iclass 21, count 0 2006.196.07:55:40.55#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.196.07:55:40.55#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.196.07:55:40.55#ibcon#about to clear, iclass 21 cls_cnt 0 2006.196.07:55:40.55#ibcon#cleared, iclass 21 cls_cnt 0 2006.196.07:55:40.55$vc4f8/vblo=1,632.99 2006.196.07:55:40.55#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.196.07:55:40.55#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.196.07:55:40.55#ibcon#ireg 17 cls_cnt 0 2006.196.07:55:40.55#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.196.07:55:40.55#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.196.07:55:40.55#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.196.07:55:40.55#ibcon#enter wrdev, iclass 23, count 0 2006.196.07:55:40.55#ibcon#first serial, iclass 23, count 0 2006.196.07:55:40.55#ibcon#enter sib2, iclass 23, count 0 2006.196.07:55:40.55#ibcon#flushed, iclass 23, count 0 2006.196.07:55:40.55#ibcon#about to write, iclass 23, count 0 2006.196.07:55:40.55#ibcon#wrote, iclass 23, count 0 2006.196.07:55:40.55#ibcon#about to read 3, iclass 23, count 0 2006.196.07:55:40.57#ibcon#read 3, iclass 23, count 0 2006.196.07:55:40.57#ibcon#about to read 4, iclass 23, count 0 2006.196.07:55:40.57#ibcon#read 4, iclass 23, count 0 2006.196.07:55:40.57#ibcon#about to read 5, iclass 23, count 0 2006.196.07:55:40.57#ibcon#read 5, iclass 23, count 0 2006.196.07:55:40.57#ibcon#about to read 6, iclass 23, count 0 2006.196.07:55:40.57#ibcon#read 6, iclass 23, count 0 2006.196.07:55:40.57#ibcon#end of sib2, iclass 23, count 0 2006.196.07:55:40.57#ibcon#*mode == 0, iclass 23, count 0 2006.196.07:55:40.57#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.196.07:55:40.57#ibcon#[28=FRQ=01,632.99\r\n] 2006.196.07:55:40.57#ibcon#*before write, iclass 23, count 0 2006.196.07:55:40.57#ibcon#enter sib2, iclass 23, count 0 2006.196.07:55:40.57#ibcon#flushed, iclass 23, count 0 2006.196.07:55:40.57#ibcon#about to write, iclass 23, count 0 2006.196.07:55:40.57#ibcon#wrote, iclass 23, count 0 2006.196.07:55:40.57#ibcon#about to read 3, iclass 23, count 0 2006.196.07:55:40.61#ibcon#read 3, iclass 23, count 0 2006.196.07:55:40.61#ibcon#about to read 4, iclass 23, count 0 2006.196.07:55:40.61#ibcon#read 4, iclass 23, count 0 2006.196.07:55:40.61#ibcon#about to read 5, iclass 23, count 0 2006.196.07:55:40.61#ibcon#read 5, iclass 23, count 0 2006.196.07:55:40.61#ibcon#about to read 6, iclass 23, count 0 2006.196.07:55:40.61#ibcon#read 6, iclass 23, count 0 2006.196.07:55:40.61#ibcon#end of sib2, iclass 23, count 0 2006.196.07:55:40.61#ibcon#*after write, iclass 23, count 0 2006.196.07:55:40.61#ibcon#*before return 0, iclass 23, count 0 2006.196.07:55:40.61#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.196.07:55:40.61#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.196.07:55:40.61#ibcon#about to clear, iclass 23 cls_cnt 0 2006.196.07:55:40.61#ibcon#cleared, iclass 23 cls_cnt 0 2006.196.07:55:40.61$vc4f8/vb=1,4 2006.196.07:55:40.61#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.196.07:55:40.61#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.196.07:55:40.61#ibcon#ireg 11 cls_cnt 2 2006.196.07:55:40.61#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.196.07:55:40.61#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.196.07:55:40.61#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.196.07:55:40.61#ibcon#enter wrdev, iclass 26, count 2 2006.196.07:55:40.61#ibcon#first serial, iclass 26, count 2 2006.196.07:55:40.61#ibcon#enter sib2, iclass 26, count 2 2006.196.07:55:40.61#ibcon#flushed, iclass 26, count 2 2006.196.07:55:40.61#ibcon#about to write, iclass 26, count 2 2006.196.07:55:40.61#ibcon#wrote, iclass 26, count 2 2006.196.07:55:40.61#ibcon#about to read 3, iclass 26, count 2 2006.196.07:55:40.63#ibcon#read 3, iclass 26, count 2 2006.196.07:55:40.63#ibcon#about to read 4, iclass 26, count 2 2006.196.07:55:40.63#ibcon#read 4, iclass 26, count 2 2006.196.07:55:40.63#ibcon#about to read 5, iclass 26, count 2 2006.196.07:55:40.63#ibcon#read 5, iclass 26, count 2 2006.196.07:55:40.63#ibcon#about to read 6, iclass 26, count 2 2006.196.07:55:40.63#ibcon#read 6, iclass 26, count 2 2006.196.07:55:40.63#ibcon#end of sib2, iclass 26, count 2 2006.196.07:55:40.63#ibcon#*mode == 0, iclass 26, count 2 2006.196.07:55:40.63#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.196.07:55:40.63#ibcon#[27=AT01-04\r\n] 2006.196.07:55:40.63#ibcon#*before write, iclass 26, count 2 2006.196.07:55:40.63#ibcon#enter sib2, iclass 26, count 2 2006.196.07:55:40.63#ibcon#flushed, iclass 26, count 2 2006.196.07:55:40.63#ibcon#about to write, iclass 26, count 2 2006.196.07:55:40.63#ibcon#wrote, iclass 26, count 2 2006.196.07:55:40.63#ibcon#about to read 3, iclass 26, count 2 2006.196.07:55:40.65#abcon#<5=/04 3.7 6.7 29.58 891004.0\r\n> 2006.196.07:55:40.66#ibcon#read 3, iclass 26, count 2 2006.196.07:55:40.66#ibcon#about to read 4, iclass 26, count 2 2006.196.07:55:40.66#ibcon#read 4, iclass 26, count 2 2006.196.07:55:40.66#ibcon#about to read 5, iclass 26, count 2 2006.196.07:55:40.66#ibcon#read 5, iclass 26, count 2 2006.196.07:55:40.66#ibcon#about to read 6, iclass 26, count 2 2006.196.07:55:40.66#ibcon#read 6, iclass 26, count 2 2006.196.07:55:40.66#ibcon#end of sib2, iclass 26, count 2 2006.196.07:55:40.66#ibcon#*after write, iclass 26, count 2 2006.196.07:55:40.66#ibcon#*before return 0, iclass 26, count 2 2006.196.07:55:40.66#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.196.07:55:40.66#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.196.07:55:40.66#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.196.07:55:40.66#ibcon#ireg 7 cls_cnt 0 2006.196.07:55:40.66#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.196.07:55:40.67#abcon#{5=INTERFACE CLEAR} 2006.196.07:55:40.73#abcon#[5=S1D000X0/0*\r\n] 2006.196.07:55:40.78#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.196.07:55:40.78#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.196.07:55:40.78#ibcon#enter wrdev, iclass 26, count 0 2006.196.07:55:40.78#ibcon#first serial, iclass 26, count 0 2006.196.07:55:40.78#ibcon#enter sib2, iclass 26, count 0 2006.196.07:55:40.78#ibcon#flushed, iclass 26, count 0 2006.196.07:55:40.78#ibcon#about to write, iclass 26, count 0 2006.196.07:55:40.78#ibcon#wrote, iclass 26, count 0 2006.196.07:55:40.78#ibcon#about to read 3, iclass 26, count 0 2006.196.07:55:40.80#ibcon#read 3, iclass 26, count 0 2006.196.07:55:40.80#ibcon#about to read 4, iclass 26, count 0 2006.196.07:55:40.80#ibcon#read 4, iclass 26, count 0 2006.196.07:55:40.80#ibcon#about to read 5, iclass 26, count 0 2006.196.07:55:40.80#ibcon#read 5, iclass 26, count 0 2006.196.07:55:40.80#ibcon#about to read 6, iclass 26, count 0 2006.196.07:55:40.80#ibcon#read 6, iclass 26, count 0 2006.196.07:55:40.80#ibcon#end of sib2, iclass 26, count 0 2006.196.07:55:40.80#ibcon#*mode == 0, iclass 26, count 0 2006.196.07:55:40.80#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.196.07:55:40.80#ibcon#[27=USB\r\n] 2006.196.07:55:40.80#ibcon#*before write, iclass 26, count 0 2006.196.07:55:40.80#ibcon#enter sib2, iclass 26, count 0 2006.196.07:55:40.80#ibcon#flushed, iclass 26, count 0 2006.196.07:55:40.80#ibcon#about to write, iclass 26, count 0 2006.196.07:55:40.80#ibcon#wrote, iclass 26, count 0 2006.196.07:55:40.80#ibcon#about to read 3, iclass 26, count 0 2006.196.07:55:40.83#ibcon#read 3, iclass 26, count 0 2006.196.07:55:40.83#ibcon#about to read 4, iclass 26, count 0 2006.196.07:55:40.83#ibcon#read 4, iclass 26, count 0 2006.196.07:55:40.83#ibcon#about to read 5, iclass 26, count 0 2006.196.07:55:40.83#ibcon#read 5, iclass 26, count 0 2006.196.07:55:40.83#ibcon#about to read 6, iclass 26, count 0 2006.196.07:55:40.83#ibcon#read 6, iclass 26, count 0 2006.196.07:55:40.83#ibcon#end of sib2, iclass 26, count 0 2006.196.07:55:40.83#ibcon#*after write, iclass 26, count 0 2006.196.07:55:40.83#ibcon#*before return 0, iclass 26, count 0 2006.196.07:55:40.83#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.196.07:55:40.83#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.196.07:55:40.83#ibcon#about to clear, iclass 26 cls_cnt 0 2006.196.07:55:40.83#ibcon#cleared, iclass 26 cls_cnt 0 2006.196.07:55:40.83$vc4f8/vblo=2,640.99 2006.196.07:55:40.83#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.196.07:55:40.83#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.196.07:55:40.83#ibcon#ireg 17 cls_cnt 0 2006.196.07:55:40.83#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.196.07:55:40.83#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.196.07:55:40.83#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.196.07:55:40.83#ibcon#enter wrdev, iclass 31, count 0 2006.196.07:55:40.83#ibcon#first serial, iclass 31, count 0 2006.196.07:55:40.83#ibcon#enter sib2, iclass 31, count 0 2006.196.07:55:40.83#ibcon#flushed, iclass 31, count 0 2006.196.07:55:40.83#ibcon#about to write, iclass 31, count 0 2006.196.07:55:40.83#ibcon#wrote, iclass 31, count 0 2006.196.07:55:40.83#ibcon#about to read 3, iclass 31, count 0 2006.196.07:55:40.85#ibcon#read 3, iclass 31, count 0 2006.196.07:55:40.85#ibcon#about to read 4, iclass 31, count 0 2006.196.07:55:40.85#ibcon#read 4, iclass 31, count 0 2006.196.07:55:40.85#ibcon#about to read 5, iclass 31, count 0 2006.196.07:55:40.85#ibcon#read 5, iclass 31, count 0 2006.196.07:55:40.85#ibcon#about to read 6, iclass 31, count 0 2006.196.07:55:40.85#ibcon#read 6, iclass 31, count 0 2006.196.07:55:40.85#ibcon#end of sib2, iclass 31, count 0 2006.196.07:55:40.85#ibcon#*mode == 0, iclass 31, count 0 2006.196.07:55:40.85#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.196.07:55:40.85#ibcon#[28=FRQ=02,640.99\r\n] 2006.196.07:55:40.85#ibcon#*before write, iclass 31, count 0 2006.196.07:55:40.85#ibcon#enter sib2, iclass 31, count 0 2006.196.07:55:40.85#ibcon#flushed, iclass 31, count 0 2006.196.07:55:40.85#ibcon#about to write, iclass 31, count 0 2006.196.07:55:40.85#ibcon#wrote, iclass 31, count 0 2006.196.07:55:40.85#ibcon#about to read 3, iclass 31, count 0 2006.196.07:55:40.90#ibcon#read 3, iclass 31, count 0 2006.196.07:55:40.90#ibcon#about to read 4, iclass 31, count 0 2006.196.07:55:40.90#ibcon#read 4, iclass 31, count 0 2006.196.07:55:40.90#ibcon#about to read 5, iclass 31, count 0 2006.196.07:55:40.90#ibcon#read 5, iclass 31, count 0 2006.196.07:55:40.90#ibcon#about to read 6, iclass 31, count 0 2006.196.07:55:40.90#ibcon#read 6, iclass 31, count 0 2006.196.07:55:40.90#ibcon#end of sib2, iclass 31, count 0 2006.196.07:55:40.90#ibcon#*after write, iclass 31, count 0 2006.196.07:55:40.90#ibcon#*before return 0, iclass 31, count 0 2006.196.07:55:40.90#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.196.07:55:40.90#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.196.07:55:40.90#ibcon#about to clear, iclass 31 cls_cnt 0 2006.196.07:55:40.90#ibcon#cleared, iclass 31 cls_cnt 0 2006.196.07:55:40.90$vc4f8/vb=2,4 2006.196.07:55:40.90#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.196.07:55:40.90#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.196.07:55:40.90#ibcon#ireg 11 cls_cnt 2 2006.196.07:55:40.90#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.196.07:55:40.95#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.196.07:55:40.95#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.196.07:55:40.95#ibcon#enter wrdev, iclass 33, count 2 2006.196.07:55:40.95#ibcon#first serial, iclass 33, count 2 2006.196.07:55:40.95#ibcon#enter sib2, iclass 33, count 2 2006.196.07:55:40.95#ibcon#flushed, iclass 33, count 2 2006.196.07:55:40.95#ibcon#about to write, iclass 33, count 2 2006.196.07:55:40.95#ibcon#wrote, iclass 33, count 2 2006.196.07:55:40.95#ibcon#about to read 3, iclass 33, count 2 2006.196.07:55:40.97#ibcon#read 3, iclass 33, count 2 2006.196.07:55:40.97#ibcon#about to read 4, iclass 33, count 2 2006.196.07:55:40.97#ibcon#read 4, iclass 33, count 2 2006.196.07:55:40.97#ibcon#about to read 5, iclass 33, count 2 2006.196.07:55:40.97#ibcon#read 5, iclass 33, count 2 2006.196.07:55:40.97#ibcon#about to read 6, iclass 33, count 2 2006.196.07:55:40.97#ibcon#read 6, iclass 33, count 2 2006.196.07:55:40.97#ibcon#end of sib2, iclass 33, count 2 2006.196.07:55:40.97#ibcon#*mode == 0, iclass 33, count 2 2006.196.07:55:40.97#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.196.07:55:40.97#ibcon#[27=AT02-04\r\n] 2006.196.07:55:40.97#ibcon#*before write, iclass 33, count 2 2006.196.07:55:40.97#ibcon#enter sib2, iclass 33, count 2 2006.196.07:55:40.97#ibcon#flushed, iclass 33, count 2 2006.196.07:55:40.97#ibcon#about to write, iclass 33, count 2 2006.196.07:55:40.97#ibcon#wrote, iclass 33, count 2 2006.196.07:55:40.97#ibcon#about to read 3, iclass 33, count 2 2006.196.07:55:41.00#ibcon#read 3, iclass 33, count 2 2006.196.07:55:41.00#ibcon#about to read 4, iclass 33, count 2 2006.196.07:55:41.00#ibcon#read 4, iclass 33, count 2 2006.196.07:55:41.00#ibcon#about to read 5, iclass 33, count 2 2006.196.07:55:41.00#ibcon#read 5, iclass 33, count 2 2006.196.07:55:41.00#ibcon#about to read 6, iclass 33, count 2 2006.196.07:55:41.00#ibcon#read 6, iclass 33, count 2 2006.196.07:55:41.00#ibcon#end of sib2, iclass 33, count 2 2006.196.07:55:41.00#ibcon#*after write, iclass 33, count 2 2006.196.07:55:41.00#ibcon#*before return 0, iclass 33, count 2 2006.196.07:55:41.00#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.196.07:55:41.00#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.196.07:55:41.00#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.196.07:55:41.00#ibcon#ireg 7 cls_cnt 0 2006.196.07:55:41.00#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.196.07:55:41.12#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.196.07:55:41.12#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.196.07:55:41.12#ibcon#enter wrdev, iclass 33, count 0 2006.196.07:55:41.12#ibcon#first serial, iclass 33, count 0 2006.196.07:55:41.12#ibcon#enter sib2, iclass 33, count 0 2006.196.07:55:41.12#ibcon#flushed, iclass 33, count 0 2006.196.07:55:41.12#ibcon#about to write, iclass 33, count 0 2006.196.07:55:41.12#ibcon#wrote, iclass 33, count 0 2006.196.07:55:41.12#ibcon#about to read 3, iclass 33, count 0 2006.196.07:55:41.14#ibcon#read 3, iclass 33, count 0 2006.196.07:55:41.14#ibcon#about to read 4, iclass 33, count 0 2006.196.07:55:41.14#ibcon#read 4, iclass 33, count 0 2006.196.07:55:41.14#ibcon#about to read 5, iclass 33, count 0 2006.196.07:55:41.14#ibcon#read 5, iclass 33, count 0 2006.196.07:55:41.14#ibcon#about to read 6, iclass 33, count 0 2006.196.07:55:41.14#ibcon#read 6, iclass 33, count 0 2006.196.07:55:41.14#ibcon#end of sib2, iclass 33, count 0 2006.196.07:55:41.14#ibcon#*mode == 0, iclass 33, count 0 2006.196.07:55:41.14#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.196.07:55:41.14#ibcon#[27=USB\r\n] 2006.196.07:55:41.14#ibcon#*before write, iclass 33, count 0 2006.196.07:55:41.14#ibcon#enter sib2, iclass 33, count 0 2006.196.07:55:41.14#ibcon#flushed, iclass 33, count 0 2006.196.07:55:41.14#ibcon#about to write, iclass 33, count 0 2006.196.07:55:41.14#ibcon#wrote, iclass 33, count 0 2006.196.07:55:41.14#ibcon#about to read 3, iclass 33, count 0 2006.196.07:55:41.17#ibcon#read 3, iclass 33, count 0 2006.196.07:55:41.17#ibcon#about to read 4, iclass 33, count 0 2006.196.07:55:41.17#ibcon#read 4, iclass 33, count 0 2006.196.07:55:41.17#ibcon#about to read 5, iclass 33, count 0 2006.196.07:55:41.17#ibcon#read 5, iclass 33, count 0 2006.196.07:55:41.17#ibcon#about to read 6, iclass 33, count 0 2006.196.07:55:41.17#ibcon#read 6, iclass 33, count 0 2006.196.07:55:41.17#ibcon#end of sib2, iclass 33, count 0 2006.196.07:55:41.17#ibcon#*after write, iclass 33, count 0 2006.196.07:55:41.17#ibcon#*before return 0, iclass 33, count 0 2006.196.07:55:41.17#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.196.07:55:41.17#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.196.07:55:41.17#ibcon#about to clear, iclass 33 cls_cnt 0 2006.196.07:55:41.17#ibcon#cleared, iclass 33 cls_cnt 0 2006.196.07:55:41.17$vc4f8/vblo=3,656.99 2006.196.07:55:41.17#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.196.07:55:41.17#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.196.07:55:41.17#ibcon#ireg 17 cls_cnt 0 2006.196.07:55:41.17#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.196.07:55:41.17#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.196.07:55:41.17#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.196.07:55:41.17#ibcon#enter wrdev, iclass 35, count 0 2006.196.07:55:41.17#ibcon#first serial, iclass 35, count 0 2006.196.07:55:41.17#ibcon#enter sib2, iclass 35, count 0 2006.196.07:55:41.17#ibcon#flushed, iclass 35, count 0 2006.196.07:55:41.17#ibcon#about to write, iclass 35, count 0 2006.196.07:55:41.17#ibcon#wrote, iclass 35, count 0 2006.196.07:55:41.17#ibcon#about to read 3, iclass 35, count 0 2006.196.07:55:41.19#ibcon#read 3, iclass 35, count 0 2006.196.07:55:41.19#ibcon#about to read 4, iclass 35, count 0 2006.196.07:55:41.19#ibcon#read 4, iclass 35, count 0 2006.196.07:55:41.19#ibcon#about to read 5, iclass 35, count 0 2006.196.07:55:41.19#ibcon#read 5, iclass 35, count 0 2006.196.07:55:41.19#ibcon#about to read 6, iclass 35, count 0 2006.196.07:55:41.19#ibcon#read 6, iclass 35, count 0 2006.196.07:55:41.19#ibcon#end of sib2, iclass 35, count 0 2006.196.07:55:41.19#ibcon#*mode == 0, iclass 35, count 0 2006.196.07:55:41.19#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.196.07:55:41.19#ibcon#[28=FRQ=03,656.99\r\n] 2006.196.07:55:41.19#ibcon#*before write, iclass 35, count 0 2006.196.07:55:41.19#ibcon#enter sib2, iclass 35, count 0 2006.196.07:55:41.19#ibcon#flushed, iclass 35, count 0 2006.196.07:55:41.19#ibcon#about to write, iclass 35, count 0 2006.196.07:55:41.19#ibcon#wrote, iclass 35, count 0 2006.196.07:55:41.19#ibcon#about to read 3, iclass 35, count 0 2006.196.07:55:41.23#ibcon#read 3, iclass 35, count 0 2006.196.07:55:41.23#ibcon#about to read 4, iclass 35, count 0 2006.196.07:55:41.23#ibcon#read 4, iclass 35, count 0 2006.196.07:55:41.23#ibcon#about to read 5, iclass 35, count 0 2006.196.07:55:41.23#ibcon#read 5, iclass 35, count 0 2006.196.07:55:41.23#ibcon#about to read 6, iclass 35, count 0 2006.196.07:55:41.23#ibcon#read 6, iclass 35, count 0 2006.196.07:55:41.23#ibcon#end of sib2, iclass 35, count 0 2006.196.07:55:41.23#ibcon#*after write, iclass 35, count 0 2006.196.07:55:41.23#ibcon#*before return 0, iclass 35, count 0 2006.196.07:55:41.23#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.196.07:55:41.23#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.196.07:55:41.23#ibcon#about to clear, iclass 35 cls_cnt 0 2006.196.07:55:41.23#ibcon#cleared, iclass 35 cls_cnt 0 2006.196.07:55:41.23$vc4f8/vb=3,4 2006.196.07:55:41.23#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.196.07:55:41.23#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.196.07:55:41.23#ibcon#ireg 11 cls_cnt 2 2006.196.07:55:41.23#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.196.07:55:41.29#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.196.07:55:41.29#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.196.07:55:41.29#ibcon#enter wrdev, iclass 37, count 2 2006.196.07:55:41.29#ibcon#first serial, iclass 37, count 2 2006.196.07:55:41.29#ibcon#enter sib2, iclass 37, count 2 2006.196.07:55:41.29#ibcon#flushed, iclass 37, count 2 2006.196.07:55:41.29#ibcon#about to write, iclass 37, count 2 2006.196.07:55:41.29#ibcon#wrote, iclass 37, count 2 2006.196.07:55:41.29#ibcon#about to read 3, iclass 37, count 2 2006.196.07:55:41.31#ibcon#read 3, iclass 37, count 2 2006.196.07:55:41.31#ibcon#about to read 4, iclass 37, count 2 2006.196.07:55:41.31#ibcon#read 4, iclass 37, count 2 2006.196.07:55:41.31#ibcon#about to read 5, iclass 37, count 2 2006.196.07:55:41.31#ibcon#read 5, iclass 37, count 2 2006.196.07:55:41.31#ibcon#about to read 6, iclass 37, count 2 2006.196.07:55:41.31#ibcon#read 6, iclass 37, count 2 2006.196.07:55:41.31#ibcon#end of sib2, iclass 37, count 2 2006.196.07:55:41.31#ibcon#*mode == 0, iclass 37, count 2 2006.196.07:55:41.31#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.196.07:55:41.31#ibcon#[27=AT03-04\r\n] 2006.196.07:55:41.31#ibcon#*before write, iclass 37, count 2 2006.196.07:55:41.31#ibcon#enter sib2, iclass 37, count 2 2006.196.07:55:41.31#ibcon#flushed, iclass 37, count 2 2006.196.07:55:41.31#ibcon#about to write, iclass 37, count 2 2006.196.07:55:41.31#ibcon#wrote, iclass 37, count 2 2006.196.07:55:41.31#ibcon#about to read 3, iclass 37, count 2 2006.196.07:55:41.34#ibcon#read 3, iclass 37, count 2 2006.196.07:55:41.34#ibcon#about to read 4, iclass 37, count 2 2006.196.07:55:41.34#ibcon#read 4, iclass 37, count 2 2006.196.07:55:41.34#ibcon#about to read 5, iclass 37, count 2 2006.196.07:55:41.34#ibcon#read 5, iclass 37, count 2 2006.196.07:55:41.34#ibcon#about to read 6, iclass 37, count 2 2006.196.07:55:41.34#ibcon#read 6, iclass 37, count 2 2006.196.07:55:41.34#ibcon#end of sib2, iclass 37, count 2 2006.196.07:55:41.34#ibcon#*after write, iclass 37, count 2 2006.196.07:55:41.34#ibcon#*before return 0, iclass 37, count 2 2006.196.07:55:41.34#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.196.07:55:41.34#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.196.07:55:41.34#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.196.07:55:41.34#ibcon#ireg 7 cls_cnt 0 2006.196.07:55:41.34#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.196.07:55:41.46#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.196.07:55:41.46#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.196.07:55:41.46#ibcon#enter wrdev, iclass 37, count 0 2006.196.07:55:41.46#ibcon#first serial, iclass 37, count 0 2006.196.07:55:41.46#ibcon#enter sib2, iclass 37, count 0 2006.196.07:55:41.46#ibcon#flushed, iclass 37, count 0 2006.196.07:55:41.46#ibcon#about to write, iclass 37, count 0 2006.196.07:55:41.46#ibcon#wrote, iclass 37, count 0 2006.196.07:55:41.46#ibcon#about to read 3, iclass 37, count 0 2006.196.07:55:41.48#ibcon#read 3, iclass 37, count 0 2006.196.07:55:41.48#ibcon#about to read 4, iclass 37, count 0 2006.196.07:55:41.48#ibcon#read 4, iclass 37, count 0 2006.196.07:55:41.48#ibcon#about to read 5, iclass 37, count 0 2006.196.07:55:41.48#ibcon#read 5, iclass 37, count 0 2006.196.07:55:41.48#ibcon#about to read 6, iclass 37, count 0 2006.196.07:55:41.48#ibcon#read 6, iclass 37, count 0 2006.196.07:55:41.48#ibcon#end of sib2, iclass 37, count 0 2006.196.07:55:41.48#ibcon#*mode == 0, iclass 37, count 0 2006.196.07:55:41.48#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.196.07:55:41.48#ibcon#[27=USB\r\n] 2006.196.07:55:41.48#ibcon#*before write, iclass 37, count 0 2006.196.07:55:41.48#ibcon#enter sib2, iclass 37, count 0 2006.196.07:55:41.48#ibcon#flushed, iclass 37, count 0 2006.196.07:55:41.48#ibcon#about to write, iclass 37, count 0 2006.196.07:55:41.48#ibcon#wrote, iclass 37, count 0 2006.196.07:55:41.48#ibcon#about to read 3, iclass 37, count 0 2006.196.07:55:41.51#ibcon#read 3, iclass 37, count 0 2006.196.07:55:41.51#ibcon#about to read 4, iclass 37, count 0 2006.196.07:55:41.51#ibcon#read 4, iclass 37, count 0 2006.196.07:55:41.51#ibcon#about to read 5, iclass 37, count 0 2006.196.07:55:41.51#ibcon#read 5, iclass 37, count 0 2006.196.07:55:41.51#ibcon#about to read 6, iclass 37, count 0 2006.196.07:55:41.51#ibcon#read 6, iclass 37, count 0 2006.196.07:55:41.51#ibcon#end of sib2, iclass 37, count 0 2006.196.07:55:41.51#ibcon#*after write, iclass 37, count 0 2006.196.07:55:41.51#ibcon#*before return 0, iclass 37, count 0 2006.196.07:55:41.51#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.196.07:55:41.51#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.196.07:55:41.51#ibcon#about to clear, iclass 37 cls_cnt 0 2006.196.07:55:41.51#ibcon#cleared, iclass 37 cls_cnt 0 2006.196.07:55:41.51$vc4f8/vblo=4,712.99 2006.196.07:55:41.51#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.196.07:55:41.51#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.196.07:55:41.51#ibcon#ireg 17 cls_cnt 0 2006.196.07:55:41.51#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.196.07:55:41.51#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.196.07:55:41.51#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.196.07:55:41.51#ibcon#enter wrdev, iclass 39, count 0 2006.196.07:55:41.51#ibcon#first serial, iclass 39, count 0 2006.196.07:55:41.51#ibcon#enter sib2, iclass 39, count 0 2006.196.07:55:41.51#ibcon#flushed, iclass 39, count 0 2006.196.07:55:41.51#ibcon#about to write, iclass 39, count 0 2006.196.07:55:41.51#ibcon#wrote, iclass 39, count 0 2006.196.07:55:41.51#ibcon#about to read 3, iclass 39, count 0 2006.196.07:55:41.53#ibcon#read 3, iclass 39, count 0 2006.196.07:55:41.53#ibcon#about to read 4, iclass 39, count 0 2006.196.07:55:41.53#ibcon#read 4, iclass 39, count 0 2006.196.07:55:41.53#ibcon#about to read 5, iclass 39, count 0 2006.196.07:55:41.53#ibcon#read 5, iclass 39, count 0 2006.196.07:55:41.53#ibcon#about to read 6, iclass 39, count 0 2006.196.07:55:41.53#ibcon#read 6, iclass 39, count 0 2006.196.07:55:41.53#ibcon#end of sib2, iclass 39, count 0 2006.196.07:55:41.53#ibcon#*mode == 0, iclass 39, count 0 2006.196.07:55:41.53#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.196.07:55:41.53#ibcon#[28=FRQ=04,712.99\r\n] 2006.196.07:55:41.53#ibcon#*before write, iclass 39, count 0 2006.196.07:55:41.53#ibcon#enter sib2, iclass 39, count 0 2006.196.07:55:41.53#ibcon#flushed, iclass 39, count 0 2006.196.07:55:41.53#ibcon#about to write, iclass 39, count 0 2006.196.07:55:41.53#ibcon#wrote, iclass 39, count 0 2006.196.07:55:41.53#ibcon#about to read 3, iclass 39, count 0 2006.196.07:55:41.57#ibcon#read 3, iclass 39, count 0 2006.196.07:55:41.57#ibcon#about to read 4, iclass 39, count 0 2006.196.07:55:41.57#ibcon#read 4, iclass 39, count 0 2006.196.07:55:41.57#ibcon#about to read 5, iclass 39, count 0 2006.196.07:55:41.57#ibcon#read 5, iclass 39, count 0 2006.196.07:55:41.57#ibcon#about to read 6, iclass 39, count 0 2006.196.07:55:41.57#ibcon#read 6, iclass 39, count 0 2006.196.07:55:41.57#ibcon#end of sib2, iclass 39, count 0 2006.196.07:55:41.57#ibcon#*after write, iclass 39, count 0 2006.196.07:55:41.57#ibcon#*before return 0, iclass 39, count 0 2006.196.07:55:41.57#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.196.07:55:41.57#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.196.07:55:41.57#ibcon#about to clear, iclass 39 cls_cnt 0 2006.196.07:55:41.57#ibcon#cleared, iclass 39 cls_cnt 0 2006.196.07:55:41.57$vc4f8/vb=4,4 2006.196.07:55:41.57#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.196.07:55:41.57#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.196.07:55:41.57#ibcon#ireg 11 cls_cnt 2 2006.196.07:55:41.57#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.196.07:55:41.63#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.196.07:55:41.63#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.196.07:55:41.63#ibcon#enter wrdev, iclass 3, count 2 2006.196.07:55:41.63#ibcon#first serial, iclass 3, count 2 2006.196.07:55:41.63#ibcon#enter sib2, iclass 3, count 2 2006.196.07:55:41.63#ibcon#flushed, iclass 3, count 2 2006.196.07:55:41.63#ibcon#about to write, iclass 3, count 2 2006.196.07:55:41.63#ibcon#wrote, iclass 3, count 2 2006.196.07:55:41.63#ibcon#about to read 3, iclass 3, count 2 2006.196.07:55:41.65#ibcon#read 3, iclass 3, count 2 2006.196.07:55:41.65#ibcon#about to read 4, iclass 3, count 2 2006.196.07:55:41.65#ibcon#read 4, iclass 3, count 2 2006.196.07:55:41.65#ibcon#about to read 5, iclass 3, count 2 2006.196.07:55:41.65#ibcon#read 5, iclass 3, count 2 2006.196.07:55:41.65#ibcon#about to read 6, iclass 3, count 2 2006.196.07:55:41.65#ibcon#read 6, iclass 3, count 2 2006.196.07:55:41.65#ibcon#end of sib2, iclass 3, count 2 2006.196.07:55:41.65#ibcon#*mode == 0, iclass 3, count 2 2006.196.07:55:41.65#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.196.07:55:41.65#ibcon#[27=AT04-04\r\n] 2006.196.07:55:41.65#ibcon#*before write, iclass 3, count 2 2006.196.07:55:41.65#ibcon#enter sib2, iclass 3, count 2 2006.196.07:55:41.65#ibcon#flushed, iclass 3, count 2 2006.196.07:55:41.65#ibcon#about to write, iclass 3, count 2 2006.196.07:55:41.65#ibcon#wrote, iclass 3, count 2 2006.196.07:55:41.65#ibcon#about to read 3, iclass 3, count 2 2006.196.07:55:41.68#ibcon#read 3, iclass 3, count 2 2006.196.07:55:41.68#ibcon#about to read 4, iclass 3, count 2 2006.196.07:55:41.68#ibcon#read 4, iclass 3, count 2 2006.196.07:55:41.68#ibcon#about to read 5, iclass 3, count 2 2006.196.07:55:41.68#ibcon#read 5, iclass 3, count 2 2006.196.07:55:41.68#ibcon#about to read 6, iclass 3, count 2 2006.196.07:55:41.68#ibcon#read 6, iclass 3, count 2 2006.196.07:55:41.68#ibcon#end of sib2, iclass 3, count 2 2006.196.07:55:41.68#ibcon#*after write, iclass 3, count 2 2006.196.07:55:41.68#ibcon#*before return 0, iclass 3, count 2 2006.196.07:55:41.68#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.196.07:55:41.68#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.196.07:55:41.68#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.196.07:55:41.68#ibcon#ireg 7 cls_cnt 0 2006.196.07:55:41.68#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.196.07:55:41.80#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.196.07:55:41.80#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.196.07:55:41.80#ibcon#enter wrdev, iclass 3, count 0 2006.196.07:55:41.80#ibcon#first serial, iclass 3, count 0 2006.196.07:55:41.80#ibcon#enter sib2, iclass 3, count 0 2006.196.07:55:41.80#ibcon#flushed, iclass 3, count 0 2006.196.07:55:41.80#ibcon#about to write, iclass 3, count 0 2006.196.07:55:41.80#ibcon#wrote, iclass 3, count 0 2006.196.07:55:41.80#ibcon#about to read 3, iclass 3, count 0 2006.196.07:55:41.82#ibcon#read 3, iclass 3, count 0 2006.196.07:55:41.82#ibcon#about to read 4, iclass 3, count 0 2006.196.07:55:41.82#ibcon#read 4, iclass 3, count 0 2006.196.07:55:41.82#ibcon#about to read 5, iclass 3, count 0 2006.196.07:55:41.82#ibcon#read 5, iclass 3, count 0 2006.196.07:55:41.82#ibcon#about to read 6, iclass 3, count 0 2006.196.07:55:41.82#ibcon#read 6, iclass 3, count 0 2006.196.07:55:41.82#ibcon#end of sib2, iclass 3, count 0 2006.196.07:55:41.82#ibcon#*mode == 0, iclass 3, count 0 2006.196.07:55:41.82#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.196.07:55:41.82#ibcon#[27=USB\r\n] 2006.196.07:55:41.82#ibcon#*before write, iclass 3, count 0 2006.196.07:55:41.82#ibcon#enter sib2, iclass 3, count 0 2006.196.07:55:41.82#ibcon#flushed, iclass 3, count 0 2006.196.07:55:41.82#ibcon#about to write, iclass 3, count 0 2006.196.07:55:41.82#ibcon#wrote, iclass 3, count 0 2006.196.07:55:41.82#ibcon#about to read 3, iclass 3, count 0 2006.196.07:55:41.85#ibcon#read 3, iclass 3, count 0 2006.196.07:55:41.85#ibcon#about to read 4, iclass 3, count 0 2006.196.07:55:41.85#ibcon#read 4, iclass 3, count 0 2006.196.07:55:41.85#ibcon#about to read 5, iclass 3, count 0 2006.196.07:55:41.85#ibcon#read 5, iclass 3, count 0 2006.196.07:55:41.85#ibcon#about to read 6, iclass 3, count 0 2006.196.07:55:41.85#ibcon#read 6, iclass 3, count 0 2006.196.07:55:41.85#ibcon#end of sib2, iclass 3, count 0 2006.196.07:55:41.85#ibcon#*after write, iclass 3, count 0 2006.196.07:55:41.85#ibcon#*before return 0, iclass 3, count 0 2006.196.07:55:41.85#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.196.07:55:41.85#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.196.07:55:41.85#ibcon#about to clear, iclass 3 cls_cnt 0 2006.196.07:55:41.85#ibcon#cleared, iclass 3 cls_cnt 0 2006.196.07:55:41.85$vc4f8/vblo=5,744.99 2006.196.07:55:41.85#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.196.07:55:41.85#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.196.07:55:41.85#ibcon#ireg 17 cls_cnt 0 2006.196.07:55:41.85#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.196.07:55:41.85#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.196.07:55:41.85#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.196.07:55:41.85#ibcon#enter wrdev, iclass 5, count 0 2006.196.07:55:41.85#ibcon#first serial, iclass 5, count 0 2006.196.07:55:41.85#ibcon#enter sib2, iclass 5, count 0 2006.196.07:55:41.85#ibcon#flushed, iclass 5, count 0 2006.196.07:55:41.85#ibcon#about to write, iclass 5, count 0 2006.196.07:55:41.85#ibcon#wrote, iclass 5, count 0 2006.196.07:55:41.85#ibcon#about to read 3, iclass 5, count 0 2006.196.07:55:41.87#ibcon#read 3, iclass 5, count 0 2006.196.07:55:41.87#ibcon#about to read 4, iclass 5, count 0 2006.196.07:55:41.87#ibcon#read 4, iclass 5, count 0 2006.196.07:55:41.87#ibcon#about to read 5, iclass 5, count 0 2006.196.07:55:41.87#ibcon#read 5, iclass 5, count 0 2006.196.07:55:41.87#ibcon#about to read 6, iclass 5, count 0 2006.196.07:55:41.87#ibcon#read 6, iclass 5, count 0 2006.196.07:55:41.87#ibcon#end of sib2, iclass 5, count 0 2006.196.07:55:41.87#ibcon#*mode == 0, iclass 5, count 0 2006.196.07:55:41.87#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.196.07:55:41.87#ibcon#[28=FRQ=05,744.99\r\n] 2006.196.07:55:41.87#ibcon#*before write, iclass 5, count 0 2006.196.07:55:41.87#ibcon#enter sib2, iclass 5, count 0 2006.196.07:55:41.87#ibcon#flushed, iclass 5, count 0 2006.196.07:55:41.87#ibcon#about to write, iclass 5, count 0 2006.196.07:55:41.87#ibcon#wrote, iclass 5, count 0 2006.196.07:55:41.87#ibcon#about to read 3, iclass 5, count 0 2006.196.07:55:41.92#ibcon#read 3, iclass 5, count 0 2006.196.07:55:41.92#ibcon#about to read 4, iclass 5, count 0 2006.196.07:55:41.92#ibcon#read 4, iclass 5, count 0 2006.196.07:55:41.92#ibcon#about to read 5, iclass 5, count 0 2006.196.07:55:41.92#ibcon#read 5, iclass 5, count 0 2006.196.07:55:41.92#ibcon#about to read 6, iclass 5, count 0 2006.196.07:55:41.92#ibcon#read 6, iclass 5, count 0 2006.196.07:55:41.92#ibcon#end of sib2, iclass 5, count 0 2006.196.07:55:41.92#ibcon#*after write, iclass 5, count 0 2006.196.07:55:41.92#ibcon#*before return 0, iclass 5, count 0 2006.196.07:55:41.92#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.196.07:55:41.92#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.196.07:55:41.92#ibcon#about to clear, iclass 5 cls_cnt 0 2006.196.07:55:41.92#ibcon#cleared, iclass 5 cls_cnt 0 2006.196.07:55:41.92$vc4f8/vb=5,4 2006.196.07:55:41.92#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.196.07:55:41.92#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.196.07:55:41.92#ibcon#ireg 11 cls_cnt 2 2006.196.07:55:41.92#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.196.07:55:41.97#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.196.07:55:41.97#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.196.07:55:41.97#ibcon#enter wrdev, iclass 7, count 2 2006.196.07:55:41.97#ibcon#first serial, iclass 7, count 2 2006.196.07:55:41.97#ibcon#enter sib2, iclass 7, count 2 2006.196.07:55:41.97#ibcon#flushed, iclass 7, count 2 2006.196.07:55:41.97#ibcon#about to write, iclass 7, count 2 2006.196.07:55:41.97#ibcon#wrote, iclass 7, count 2 2006.196.07:55:41.97#ibcon#about to read 3, iclass 7, count 2 2006.196.07:55:41.99#ibcon#read 3, iclass 7, count 2 2006.196.07:55:41.99#ibcon#about to read 4, iclass 7, count 2 2006.196.07:55:41.99#ibcon#read 4, iclass 7, count 2 2006.196.07:55:41.99#ibcon#about to read 5, iclass 7, count 2 2006.196.07:55:41.99#ibcon#read 5, iclass 7, count 2 2006.196.07:55:41.99#ibcon#about to read 6, iclass 7, count 2 2006.196.07:55:41.99#ibcon#read 6, iclass 7, count 2 2006.196.07:55:41.99#ibcon#end of sib2, iclass 7, count 2 2006.196.07:55:41.99#ibcon#*mode == 0, iclass 7, count 2 2006.196.07:55:41.99#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.196.07:55:41.99#ibcon#[27=AT05-04\r\n] 2006.196.07:55:41.99#ibcon#*before write, iclass 7, count 2 2006.196.07:55:41.99#ibcon#enter sib2, iclass 7, count 2 2006.196.07:55:41.99#ibcon#flushed, iclass 7, count 2 2006.196.07:55:41.99#ibcon#about to write, iclass 7, count 2 2006.196.07:55:41.99#ibcon#wrote, iclass 7, count 2 2006.196.07:55:41.99#ibcon#about to read 3, iclass 7, count 2 2006.196.07:55:42.02#ibcon#read 3, iclass 7, count 2 2006.196.07:55:42.02#ibcon#about to read 4, iclass 7, count 2 2006.196.07:55:42.02#ibcon#read 4, iclass 7, count 2 2006.196.07:55:42.02#ibcon#about to read 5, iclass 7, count 2 2006.196.07:55:42.02#ibcon#read 5, iclass 7, count 2 2006.196.07:55:42.02#ibcon#about to read 6, iclass 7, count 2 2006.196.07:55:42.02#ibcon#read 6, iclass 7, count 2 2006.196.07:55:42.02#ibcon#end of sib2, iclass 7, count 2 2006.196.07:55:42.02#ibcon#*after write, iclass 7, count 2 2006.196.07:55:42.02#ibcon#*before return 0, iclass 7, count 2 2006.196.07:55:42.02#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.196.07:55:42.02#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.196.07:55:42.02#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.196.07:55:42.02#ibcon#ireg 7 cls_cnt 0 2006.196.07:55:42.02#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.196.07:55:42.14#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.196.07:55:42.14#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.196.07:55:42.14#ibcon#enter wrdev, iclass 7, count 0 2006.196.07:55:42.14#ibcon#first serial, iclass 7, count 0 2006.196.07:55:42.14#ibcon#enter sib2, iclass 7, count 0 2006.196.07:55:42.14#ibcon#flushed, iclass 7, count 0 2006.196.07:55:42.14#ibcon#about to write, iclass 7, count 0 2006.196.07:55:42.14#ibcon#wrote, iclass 7, count 0 2006.196.07:55:42.14#ibcon#about to read 3, iclass 7, count 0 2006.196.07:55:42.16#ibcon#read 3, iclass 7, count 0 2006.196.07:55:42.16#ibcon#about to read 4, iclass 7, count 0 2006.196.07:55:42.16#ibcon#read 4, iclass 7, count 0 2006.196.07:55:42.16#ibcon#about to read 5, iclass 7, count 0 2006.196.07:55:42.16#ibcon#read 5, iclass 7, count 0 2006.196.07:55:42.16#ibcon#about to read 6, iclass 7, count 0 2006.196.07:55:42.16#ibcon#read 6, iclass 7, count 0 2006.196.07:55:42.16#ibcon#end of sib2, iclass 7, count 0 2006.196.07:55:42.16#ibcon#*mode == 0, iclass 7, count 0 2006.196.07:55:42.16#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.196.07:55:42.16#ibcon#[27=USB\r\n] 2006.196.07:55:42.16#ibcon#*before write, iclass 7, count 0 2006.196.07:55:42.16#ibcon#enter sib2, iclass 7, count 0 2006.196.07:55:42.16#ibcon#flushed, iclass 7, count 0 2006.196.07:55:42.16#ibcon#about to write, iclass 7, count 0 2006.196.07:55:42.16#ibcon#wrote, iclass 7, count 0 2006.196.07:55:42.16#ibcon#about to read 3, iclass 7, count 0 2006.196.07:55:42.19#ibcon#read 3, iclass 7, count 0 2006.196.07:55:42.19#ibcon#about to read 4, iclass 7, count 0 2006.196.07:55:42.19#ibcon#read 4, iclass 7, count 0 2006.196.07:55:42.19#ibcon#about to read 5, iclass 7, count 0 2006.196.07:55:42.19#ibcon#read 5, iclass 7, count 0 2006.196.07:55:42.19#ibcon#about to read 6, iclass 7, count 0 2006.196.07:55:42.19#ibcon#read 6, iclass 7, count 0 2006.196.07:55:42.19#ibcon#end of sib2, iclass 7, count 0 2006.196.07:55:42.19#ibcon#*after write, iclass 7, count 0 2006.196.07:55:42.19#ibcon#*before return 0, iclass 7, count 0 2006.196.07:55:42.19#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.196.07:55:42.19#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.196.07:55:42.19#ibcon#about to clear, iclass 7 cls_cnt 0 2006.196.07:55:42.19#ibcon#cleared, iclass 7 cls_cnt 0 2006.196.07:55:42.19$vc4f8/vblo=6,752.99 2006.196.07:55:42.19#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.196.07:55:42.19#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.196.07:55:42.19#ibcon#ireg 17 cls_cnt 0 2006.196.07:55:42.19#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.196.07:55:42.19#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.196.07:55:42.19#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.196.07:55:42.19#ibcon#enter wrdev, iclass 11, count 0 2006.196.07:55:42.19#ibcon#first serial, iclass 11, count 0 2006.196.07:55:42.19#ibcon#enter sib2, iclass 11, count 0 2006.196.07:55:42.19#ibcon#flushed, iclass 11, count 0 2006.196.07:55:42.19#ibcon#about to write, iclass 11, count 0 2006.196.07:55:42.19#ibcon#wrote, iclass 11, count 0 2006.196.07:55:42.19#ibcon#about to read 3, iclass 11, count 0 2006.196.07:55:42.21#ibcon#read 3, iclass 11, count 0 2006.196.07:55:42.21#ibcon#about to read 4, iclass 11, count 0 2006.196.07:55:42.21#ibcon#read 4, iclass 11, count 0 2006.196.07:55:42.21#ibcon#about to read 5, iclass 11, count 0 2006.196.07:55:42.21#ibcon#read 5, iclass 11, count 0 2006.196.07:55:42.21#ibcon#about to read 6, iclass 11, count 0 2006.196.07:55:42.21#ibcon#read 6, iclass 11, count 0 2006.196.07:55:42.21#ibcon#end of sib2, iclass 11, count 0 2006.196.07:55:42.21#ibcon#*mode == 0, iclass 11, count 0 2006.196.07:55:42.21#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.196.07:55:42.21#ibcon#[28=FRQ=06,752.99\r\n] 2006.196.07:55:42.21#ibcon#*before write, iclass 11, count 0 2006.196.07:55:42.21#ibcon#enter sib2, iclass 11, count 0 2006.196.07:55:42.21#ibcon#flushed, iclass 11, count 0 2006.196.07:55:42.21#ibcon#about to write, iclass 11, count 0 2006.196.07:55:42.21#ibcon#wrote, iclass 11, count 0 2006.196.07:55:42.21#ibcon#about to read 3, iclass 11, count 0 2006.196.07:55:42.25#ibcon#read 3, iclass 11, count 0 2006.196.07:55:42.25#ibcon#about to read 4, iclass 11, count 0 2006.196.07:55:42.25#ibcon#read 4, iclass 11, count 0 2006.196.07:55:42.25#ibcon#about to read 5, iclass 11, count 0 2006.196.07:55:42.25#ibcon#read 5, iclass 11, count 0 2006.196.07:55:42.25#ibcon#about to read 6, iclass 11, count 0 2006.196.07:55:42.25#ibcon#read 6, iclass 11, count 0 2006.196.07:55:42.25#ibcon#end of sib2, iclass 11, count 0 2006.196.07:55:42.25#ibcon#*after write, iclass 11, count 0 2006.196.07:55:42.25#ibcon#*before return 0, iclass 11, count 0 2006.196.07:55:42.25#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.196.07:55:42.25#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.196.07:55:42.25#ibcon#about to clear, iclass 11 cls_cnt 0 2006.196.07:55:42.25#ibcon#cleared, iclass 11 cls_cnt 0 2006.196.07:55:42.25$vc4f8/vb=6,4 2006.196.07:55:42.25#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.196.07:55:42.25#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.196.07:55:42.25#ibcon#ireg 11 cls_cnt 2 2006.196.07:55:42.25#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.196.07:55:42.31#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.196.07:55:42.31#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.196.07:55:42.31#ibcon#enter wrdev, iclass 13, count 2 2006.196.07:55:42.31#ibcon#first serial, iclass 13, count 2 2006.196.07:55:42.31#ibcon#enter sib2, iclass 13, count 2 2006.196.07:55:42.31#ibcon#flushed, iclass 13, count 2 2006.196.07:55:42.31#ibcon#about to write, iclass 13, count 2 2006.196.07:55:42.31#ibcon#wrote, iclass 13, count 2 2006.196.07:55:42.31#ibcon#about to read 3, iclass 13, count 2 2006.196.07:55:42.33#ibcon#read 3, iclass 13, count 2 2006.196.07:55:42.33#ibcon#about to read 4, iclass 13, count 2 2006.196.07:55:42.33#ibcon#read 4, iclass 13, count 2 2006.196.07:55:42.33#ibcon#about to read 5, iclass 13, count 2 2006.196.07:55:42.33#ibcon#read 5, iclass 13, count 2 2006.196.07:55:42.33#ibcon#about to read 6, iclass 13, count 2 2006.196.07:55:42.33#ibcon#read 6, iclass 13, count 2 2006.196.07:55:42.33#ibcon#end of sib2, iclass 13, count 2 2006.196.07:55:42.33#ibcon#*mode == 0, iclass 13, count 2 2006.196.07:55:42.33#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.196.07:55:42.33#ibcon#[27=AT06-04\r\n] 2006.196.07:55:42.33#ibcon#*before write, iclass 13, count 2 2006.196.07:55:42.33#ibcon#enter sib2, iclass 13, count 2 2006.196.07:55:42.33#ibcon#flushed, iclass 13, count 2 2006.196.07:55:42.33#ibcon#about to write, iclass 13, count 2 2006.196.07:55:42.33#ibcon#wrote, iclass 13, count 2 2006.196.07:55:42.33#ibcon#about to read 3, iclass 13, count 2 2006.196.07:55:42.36#ibcon#read 3, iclass 13, count 2 2006.196.07:55:42.36#ibcon#about to read 4, iclass 13, count 2 2006.196.07:55:42.36#ibcon#read 4, iclass 13, count 2 2006.196.07:55:42.36#ibcon#about to read 5, iclass 13, count 2 2006.196.07:55:42.36#ibcon#read 5, iclass 13, count 2 2006.196.07:55:42.36#ibcon#about to read 6, iclass 13, count 2 2006.196.07:55:42.36#ibcon#read 6, iclass 13, count 2 2006.196.07:55:42.36#ibcon#end of sib2, iclass 13, count 2 2006.196.07:55:42.36#ibcon#*after write, iclass 13, count 2 2006.196.07:55:42.36#ibcon#*before return 0, iclass 13, count 2 2006.196.07:55:42.36#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.196.07:55:42.36#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.196.07:55:42.36#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.196.07:55:42.36#ibcon#ireg 7 cls_cnt 0 2006.196.07:55:42.36#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.196.07:55:42.48#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.196.07:55:42.48#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.196.07:55:42.48#ibcon#enter wrdev, iclass 13, count 0 2006.196.07:55:42.48#ibcon#first serial, iclass 13, count 0 2006.196.07:55:42.48#ibcon#enter sib2, iclass 13, count 0 2006.196.07:55:42.48#ibcon#flushed, iclass 13, count 0 2006.196.07:55:42.48#ibcon#about to write, iclass 13, count 0 2006.196.07:55:42.48#ibcon#wrote, iclass 13, count 0 2006.196.07:55:42.48#ibcon#about to read 3, iclass 13, count 0 2006.196.07:55:42.50#ibcon#read 3, iclass 13, count 0 2006.196.07:55:42.50#ibcon#about to read 4, iclass 13, count 0 2006.196.07:55:42.50#ibcon#read 4, iclass 13, count 0 2006.196.07:55:42.50#ibcon#about to read 5, iclass 13, count 0 2006.196.07:55:42.50#ibcon#read 5, iclass 13, count 0 2006.196.07:55:42.50#ibcon#about to read 6, iclass 13, count 0 2006.196.07:55:42.50#ibcon#read 6, iclass 13, count 0 2006.196.07:55:42.50#ibcon#end of sib2, iclass 13, count 0 2006.196.07:55:42.50#ibcon#*mode == 0, iclass 13, count 0 2006.196.07:55:42.50#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.196.07:55:42.50#ibcon#[27=USB\r\n] 2006.196.07:55:42.50#ibcon#*before write, iclass 13, count 0 2006.196.07:55:42.50#ibcon#enter sib2, iclass 13, count 0 2006.196.07:55:42.50#ibcon#flushed, iclass 13, count 0 2006.196.07:55:42.50#ibcon#about to write, iclass 13, count 0 2006.196.07:55:42.50#ibcon#wrote, iclass 13, count 0 2006.196.07:55:42.50#ibcon#about to read 3, iclass 13, count 0 2006.196.07:55:42.53#ibcon#read 3, iclass 13, count 0 2006.196.07:55:42.53#ibcon#about to read 4, iclass 13, count 0 2006.196.07:55:42.53#ibcon#read 4, iclass 13, count 0 2006.196.07:55:42.53#ibcon#about to read 5, iclass 13, count 0 2006.196.07:55:42.53#ibcon#read 5, iclass 13, count 0 2006.196.07:55:42.53#ibcon#about to read 6, iclass 13, count 0 2006.196.07:55:42.53#ibcon#read 6, iclass 13, count 0 2006.196.07:55:42.53#ibcon#end of sib2, iclass 13, count 0 2006.196.07:55:42.53#ibcon#*after write, iclass 13, count 0 2006.196.07:55:42.53#ibcon#*before return 0, iclass 13, count 0 2006.196.07:55:42.53#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.196.07:55:42.53#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.196.07:55:42.53#ibcon#about to clear, iclass 13 cls_cnt 0 2006.196.07:55:42.53#ibcon#cleared, iclass 13 cls_cnt 0 2006.196.07:55:42.53$vc4f8/vabw=wide 2006.196.07:55:42.53#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.196.07:55:42.53#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.196.07:55:42.53#ibcon#ireg 8 cls_cnt 0 2006.196.07:55:42.53#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.196.07:55:42.53#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.196.07:55:42.53#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.196.07:55:42.53#ibcon#enter wrdev, iclass 15, count 0 2006.196.07:55:42.53#ibcon#first serial, iclass 15, count 0 2006.196.07:55:42.53#ibcon#enter sib2, iclass 15, count 0 2006.196.07:55:42.53#ibcon#flushed, iclass 15, count 0 2006.196.07:55:42.53#ibcon#about to write, iclass 15, count 0 2006.196.07:55:42.53#ibcon#wrote, iclass 15, count 0 2006.196.07:55:42.53#ibcon#about to read 3, iclass 15, count 0 2006.196.07:55:42.55#ibcon#read 3, iclass 15, count 0 2006.196.07:55:42.55#ibcon#about to read 4, iclass 15, count 0 2006.196.07:55:42.55#ibcon#read 4, iclass 15, count 0 2006.196.07:55:42.55#ibcon#about to read 5, iclass 15, count 0 2006.196.07:55:42.55#ibcon#read 5, iclass 15, count 0 2006.196.07:55:42.55#ibcon#about to read 6, iclass 15, count 0 2006.196.07:55:42.55#ibcon#read 6, iclass 15, count 0 2006.196.07:55:42.55#ibcon#end of sib2, iclass 15, count 0 2006.196.07:55:42.55#ibcon#*mode == 0, iclass 15, count 0 2006.196.07:55:42.55#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.196.07:55:42.55#ibcon#[25=BW32\r\n] 2006.196.07:55:42.55#ibcon#*before write, iclass 15, count 0 2006.196.07:55:42.55#ibcon#enter sib2, iclass 15, count 0 2006.196.07:55:42.55#ibcon#flushed, iclass 15, count 0 2006.196.07:55:42.55#ibcon#about to write, iclass 15, count 0 2006.196.07:55:42.55#ibcon#wrote, iclass 15, count 0 2006.196.07:55:42.55#ibcon#about to read 3, iclass 15, count 0 2006.196.07:55:42.59#ibcon#read 3, iclass 15, count 0 2006.196.07:55:42.59#ibcon#about to read 4, iclass 15, count 0 2006.196.07:55:42.59#ibcon#read 4, iclass 15, count 0 2006.196.07:55:42.59#ibcon#about to read 5, iclass 15, count 0 2006.196.07:55:42.59#ibcon#read 5, iclass 15, count 0 2006.196.07:55:42.59#ibcon#about to read 6, iclass 15, count 0 2006.196.07:55:42.59#ibcon#read 6, iclass 15, count 0 2006.196.07:55:42.59#ibcon#end of sib2, iclass 15, count 0 2006.196.07:55:42.59#ibcon#*after write, iclass 15, count 0 2006.196.07:55:42.59#ibcon#*before return 0, iclass 15, count 0 2006.196.07:55:42.59#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.196.07:55:42.59#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.196.07:55:42.59#ibcon#about to clear, iclass 15 cls_cnt 0 2006.196.07:55:42.59#ibcon#cleared, iclass 15 cls_cnt 0 2006.196.07:55:42.59$vc4f8/vbbw=wide 2006.196.07:55:42.59#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.196.07:55:42.59#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.196.07:55:42.59#ibcon#ireg 8 cls_cnt 0 2006.196.07:55:42.59#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.196.07:55:42.65#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.196.07:55:42.65#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.196.07:55:42.65#ibcon#enter wrdev, iclass 17, count 0 2006.196.07:55:42.65#ibcon#first serial, iclass 17, count 0 2006.196.07:55:42.65#ibcon#enter sib2, iclass 17, count 0 2006.196.07:55:42.65#ibcon#flushed, iclass 17, count 0 2006.196.07:55:42.65#ibcon#about to write, iclass 17, count 0 2006.196.07:55:42.65#ibcon#wrote, iclass 17, count 0 2006.196.07:55:42.65#ibcon#about to read 3, iclass 17, count 0 2006.196.07:55:42.67#ibcon#read 3, iclass 17, count 0 2006.196.07:55:42.67#ibcon#about to read 4, iclass 17, count 0 2006.196.07:55:42.67#ibcon#read 4, iclass 17, count 0 2006.196.07:55:42.67#ibcon#about to read 5, iclass 17, count 0 2006.196.07:55:42.67#ibcon#read 5, iclass 17, count 0 2006.196.07:55:42.67#ibcon#about to read 6, iclass 17, count 0 2006.196.07:55:42.67#ibcon#read 6, iclass 17, count 0 2006.196.07:55:42.67#ibcon#end of sib2, iclass 17, count 0 2006.196.07:55:42.67#ibcon#*mode == 0, iclass 17, count 0 2006.196.07:55:42.67#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.196.07:55:42.67#ibcon#[27=BW32\r\n] 2006.196.07:55:42.67#ibcon#*before write, iclass 17, count 0 2006.196.07:55:42.67#ibcon#enter sib2, iclass 17, count 0 2006.196.07:55:42.67#ibcon#flushed, iclass 17, count 0 2006.196.07:55:42.67#ibcon#about to write, iclass 17, count 0 2006.196.07:55:42.67#ibcon#wrote, iclass 17, count 0 2006.196.07:55:42.67#ibcon#about to read 3, iclass 17, count 0 2006.196.07:55:42.70#ibcon#read 3, iclass 17, count 0 2006.196.07:55:42.70#ibcon#about to read 4, iclass 17, count 0 2006.196.07:55:42.70#ibcon#read 4, iclass 17, count 0 2006.196.07:55:42.70#ibcon#about to read 5, iclass 17, count 0 2006.196.07:55:42.70#ibcon#read 5, iclass 17, count 0 2006.196.07:55:42.70#ibcon#about to read 6, iclass 17, count 0 2006.196.07:55:42.70#ibcon#read 6, iclass 17, count 0 2006.196.07:55:42.70#ibcon#end of sib2, iclass 17, count 0 2006.196.07:55:42.70#ibcon#*after write, iclass 17, count 0 2006.196.07:55:42.70#ibcon#*before return 0, iclass 17, count 0 2006.196.07:55:42.70#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.196.07:55:42.70#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.196.07:55:42.70#ibcon#about to clear, iclass 17 cls_cnt 0 2006.196.07:55:42.70#ibcon#cleared, iclass 17 cls_cnt 0 2006.196.07:55:42.70$4f8m12a/ifd4f 2006.196.07:55:42.70$ifd4f/lo= 2006.196.07:55:42.70$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.196.07:55:42.70$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.196.07:55:42.70$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.196.07:55:42.70$ifd4f/patch= 2006.196.07:55:42.70$ifd4f/patch=lo1,a1,a2,a3,a4 2006.196.07:55:42.70$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.196.07:55:42.70$ifd4f/patch=lo3,a5,a6,a7,a8 2006.196.07:55:42.70$4f8m12a/"form=m,16.000,1:2 2006.196.07:55:42.70$4f8m12a/"tpicd 2006.196.07:55:42.70$4f8m12a/echo=off 2006.196.07:55:42.70$4f8m12a/xlog=off 2006.196.07:55:42.70:!2006.196.07:56:30 2006.196.07:55:55.14#trakl#Source acquired 2006.196.07:55:55.14#flagr#flagr/antenna,acquired 2006.196.07:56:30.00:preob 2006.196.07:56:30.14/onsource/TRACKING 2006.196.07:56:30.14:!2006.196.07:56:40 2006.196.07:56:40.00:data_valid=on 2006.196.07:56:40.00:midob 2006.196.07:56:40.14/onsource/TRACKING 2006.196.07:56:40.14/wx/29.57,1004.0,89 2006.196.07:56:40.21/cable/+6.3362E-03 2006.196.07:56:41.30/va/01,08,usb,yes,30,32 2006.196.07:56:41.30/va/02,07,usb,yes,31,32 2006.196.07:56:41.30/va/03,06,usb,yes,32,32 2006.196.07:56:41.30/va/04,07,usb,yes,32,34 2006.196.07:56:41.30/va/05,07,usb,yes,34,36 2006.196.07:56:41.30/va/06,06,usb,yes,33,33 2006.196.07:56:41.30/va/07,06,usb,yes,33,33 2006.196.07:56:41.30/va/08,07,usb,yes,32,31 2006.196.07:56:41.53/valo/01,532.99,yes,locked 2006.196.07:56:41.53/valo/02,572.99,yes,locked 2006.196.07:56:41.53/valo/03,672.99,yes,locked 2006.196.07:56:41.53/valo/04,832.99,yes,locked 2006.196.07:56:41.53/valo/05,652.99,yes,locked 2006.196.07:56:41.53/valo/06,772.99,yes,locked 2006.196.07:56:41.53/valo/07,832.99,yes,locked 2006.196.07:56:41.53/valo/08,852.99,yes,locked 2006.196.07:56:42.62/vb/01,04,usb,yes,30,28 2006.196.07:56:42.62/vb/02,04,usb,yes,31,33 2006.196.07:56:42.62/vb/03,04,usb,yes,28,31 2006.196.07:56:42.62/vb/04,04,usb,yes,28,29 2006.196.07:56:42.62/vb/05,04,usb,yes,27,31 2006.196.07:56:42.62/vb/06,04,usb,yes,28,31 2006.196.07:56:42.62/vb/07,04,usb,yes,30,30 2006.196.07:56:42.62/vb/08,04,usb,yes,28,31 2006.196.07:56:42.86/vblo/01,632.99,yes,locked 2006.196.07:56:42.86/vblo/02,640.99,yes,locked 2006.196.07:56:42.86/vblo/03,656.99,yes,locked 2006.196.07:56:42.86/vblo/04,712.99,yes,locked 2006.196.07:56:42.86/vblo/05,744.99,yes,locked 2006.196.07:56:42.86/vblo/06,752.99,yes,locked 2006.196.07:56:42.86/vblo/07,734.99,yes,locked 2006.196.07:56:42.86/vblo/08,744.99,yes,locked 2006.196.07:56:43.01/vabw/8 2006.196.07:56:43.16/vbbw/8 2006.196.07:56:43.25/xfe/off,on,16.0 2006.196.07:56:43.65/ifatt/23,28,28,28 2006.196.07:56:44.07/fmout-gps/S +3.35E-07 2006.196.07:56:44.11:!2006.196.07:57:40 2006.196.07:57:40.00:data_valid=off 2006.196.07:57:40.00:postob 2006.196.07:57:40.08/cable/+6.3362E-03 2006.196.07:57:40.08/wx/29.55,1004.0,89 2006.196.07:57:41.07/fmout-gps/S +3.34E-07 2006.196.07:57:41.07:scan_name=196-0800,k06196,60 2006.196.07:57:41.07:source=0602+673,060752.67,672055.4,2000.0,cw 2006.196.07:57:41.14#flagr#flagr/antenna,new-source 2006.196.07:57:42.14:checkk5 2006.196.07:57:42.52/chk_autoobs//k5ts1/ autoobs is running! 2006.196.07:57:42.90/chk_autoobs//k5ts2/ autoobs is running! 2006.196.07:57:43.27/chk_autoobs//k5ts3/ autoobs is running! 2006.196.07:57:43.64/chk_autoobs//k5ts4/ autoobs is running! 2006.196.07:57:44.01/chk_obsdata//k5ts1/T1960756??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.196.07:57:44.38/chk_obsdata//k5ts2/T1960756??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.196.07:57:44.75/chk_obsdata//k5ts3/T1960756??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.196.07:57:45.13/chk_obsdata//k5ts4/T1960756??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.196.07:57:45.82/k5log//k5ts1_log_newline 2006.196.07:57:46.52/k5log//k5ts2_log_newline 2006.196.07:57:47.21/k5log//k5ts3_log_newline 2006.196.07:57:47.91/k5log//k5ts4_log_newline 2006.196.07:57:47.94/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.196.07:57:47.94:4f8m12a=2 2006.196.07:57:47.94$4f8m12a/echo=on 2006.196.07:57:47.94$4f8m12a/pcalon 2006.196.07:57:47.94$pcalon/"no phase cal control is implemented here 2006.196.07:57:47.94$4f8m12a/"tpicd=stop 2006.196.07:57:47.94$4f8m12a/vc4f8 2006.196.07:57:47.94$vc4f8/valo=1,532.99 2006.196.07:57:47.94#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.196.07:57:47.94#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.196.07:57:47.94#ibcon#ireg 17 cls_cnt 0 2006.196.07:57:47.94#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.196.07:57:47.94#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.196.07:57:47.94#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.196.07:57:47.94#ibcon#enter wrdev, iclass 32, count 0 2006.196.07:57:47.94#ibcon#first serial, iclass 32, count 0 2006.196.07:57:47.94#ibcon#enter sib2, iclass 32, count 0 2006.196.07:57:47.94#ibcon#flushed, iclass 32, count 0 2006.196.07:57:47.94#ibcon#about to write, iclass 32, count 0 2006.196.07:57:47.94#ibcon#wrote, iclass 32, count 0 2006.196.07:57:47.94#ibcon#about to read 3, iclass 32, count 0 2006.196.07:57:47.96#ibcon#read 3, iclass 32, count 0 2006.196.07:57:47.96#ibcon#about to read 4, iclass 32, count 0 2006.196.07:57:47.96#ibcon#read 4, iclass 32, count 0 2006.196.07:57:47.96#ibcon#about to read 5, iclass 32, count 0 2006.196.07:57:47.96#ibcon#read 5, iclass 32, count 0 2006.196.07:57:47.96#ibcon#about to read 6, iclass 32, count 0 2006.196.07:57:47.96#ibcon#read 6, iclass 32, count 0 2006.196.07:57:47.96#ibcon#end of sib2, iclass 32, count 0 2006.196.07:57:47.96#ibcon#*mode == 0, iclass 32, count 0 2006.196.07:57:47.96#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.196.07:57:47.96#ibcon#[26=FRQ=01,532.99\r\n] 2006.196.07:57:47.96#ibcon#*before write, iclass 32, count 0 2006.196.07:57:47.96#ibcon#enter sib2, iclass 32, count 0 2006.196.07:57:47.96#ibcon#flushed, iclass 32, count 0 2006.196.07:57:47.96#ibcon#about to write, iclass 32, count 0 2006.196.07:57:47.96#ibcon#wrote, iclass 32, count 0 2006.196.07:57:47.96#ibcon#about to read 3, iclass 32, count 0 2006.196.07:57:48.01#ibcon#read 3, iclass 32, count 0 2006.196.07:57:48.01#ibcon#about to read 4, iclass 32, count 0 2006.196.07:57:48.01#ibcon#read 4, iclass 32, count 0 2006.196.07:57:48.01#ibcon#about to read 5, iclass 32, count 0 2006.196.07:57:48.01#ibcon#read 5, iclass 32, count 0 2006.196.07:57:48.01#ibcon#about to read 6, iclass 32, count 0 2006.196.07:57:48.01#ibcon#read 6, iclass 32, count 0 2006.196.07:57:48.01#ibcon#end of sib2, iclass 32, count 0 2006.196.07:57:48.01#ibcon#*after write, iclass 32, count 0 2006.196.07:57:48.01#ibcon#*before return 0, iclass 32, count 0 2006.196.07:57:48.01#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.196.07:57:48.01#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.196.07:57:48.01#ibcon#about to clear, iclass 32 cls_cnt 0 2006.196.07:57:48.01#ibcon#cleared, iclass 32 cls_cnt 0 2006.196.07:57:48.01$vc4f8/va=1,8 2006.196.07:57:48.01#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.196.07:57:48.01#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.196.07:57:48.01#ibcon#ireg 11 cls_cnt 2 2006.196.07:57:48.01#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.196.07:57:48.01#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.196.07:57:48.01#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.196.07:57:48.01#ibcon#enter wrdev, iclass 34, count 2 2006.196.07:57:48.01#ibcon#first serial, iclass 34, count 2 2006.196.07:57:48.01#ibcon#enter sib2, iclass 34, count 2 2006.196.07:57:48.01#ibcon#flushed, iclass 34, count 2 2006.196.07:57:48.01#ibcon#about to write, iclass 34, count 2 2006.196.07:57:48.01#ibcon#wrote, iclass 34, count 2 2006.196.07:57:48.01#ibcon#about to read 3, iclass 34, count 2 2006.196.07:57:48.03#ibcon#read 3, iclass 34, count 2 2006.196.07:57:48.03#ibcon#about to read 4, iclass 34, count 2 2006.196.07:57:48.03#ibcon#read 4, iclass 34, count 2 2006.196.07:57:48.03#ibcon#about to read 5, iclass 34, count 2 2006.196.07:57:48.03#ibcon#read 5, iclass 34, count 2 2006.196.07:57:48.03#ibcon#about to read 6, iclass 34, count 2 2006.196.07:57:48.03#ibcon#read 6, iclass 34, count 2 2006.196.07:57:48.03#ibcon#end of sib2, iclass 34, count 2 2006.196.07:57:48.03#ibcon#*mode == 0, iclass 34, count 2 2006.196.07:57:48.03#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.196.07:57:48.03#ibcon#[25=AT01-08\r\n] 2006.196.07:57:48.03#ibcon#*before write, iclass 34, count 2 2006.196.07:57:48.03#ibcon#enter sib2, iclass 34, count 2 2006.196.07:57:48.03#ibcon#flushed, iclass 34, count 2 2006.196.07:57:48.03#ibcon#about to write, iclass 34, count 2 2006.196.07:57:48.03#ibcon#wrote, iclass 34, count 2 2006.196.07:57:48.03#ibcon#about to read 3, iclass 34, count 2 2006.196.07:57:48.06#ibcon#read 3, iclass 34, count 2 2006.196.07:57:48.06#ibcon#about to read 4, iclass 34, count 2 2006.196.07:57:48.06#ibcon#read 4, iclass 34, count 2 2006.196.07:57:48.06#ibcon#about to read 5, iclass 34, count 2 2006.196.07:57:48.06#ibcon#read 5, iclass 34, count 2 2006.196.07:57:48.06#ibcon#about to read 6, iclass 34, count 2 2006.196.07:57:48.06#ibcon#read 6, iclass 34, count 2 2006.196.07:57:48.06#ibcon#end of sib2, iclass 34, count 2 2006.196.07:57:48.06#ibcon#*after write, iclass 34, count 2 2006.196.07:57:48.06#ibcon#*before return 0, iclass 34, count 2 2006.196.07:57:48.06#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.196.07:57:48.06#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.196.07:57:48.06#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.196.07:57:48.06#ibcon#ireg 7 cls_cnt 0 2006.196.07:57:48.06#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.196.07:57:48.18#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.196.07:57:48.18#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.196.07:57:48.18#ibcon#enter wrdev, iclass 34, count 0 2006.196.07:57:48.18#ibcon#first serial, iclass 34, count 0 2006.196.07:57:48.18#ibcon#enter sib2, iclass 34, count 0 2006.196.07:57:48.18#ibcon#flushed, iclass 34, count 0 2006.196.07:57:48.18#ibcon#about to write, iclass 34, count 0 2006.196.07:57:48.18#ibcon#wrote, iclass 34, count 0 2006.196.07:57:48.18#ibcon#about to read 3, iclass 34, count 0 2006.196.07:57:48.20#ibcon#read 3, iclass 34, count 0 2006.196.07:57:48.20#ibcon#about to read 4, iclass 34, count 0 2006.196.07:57:48.20#ibcon#read 4, iclass 34, count 0 2006.196.07:57:48.20#ibcon#about to read 5, iclass 34, count 0 2006.196.07:57:48.20#ibcon#read 5, iclass 34, count 0 2006.196.07:57:48.20#ibcon#about to read 6, iclass 34, count 0 2006.196.07:57:48.20#ibcon#read 6, iclass 34, count 0 2006.196.07:57:48.20#ibcon#end of sib2, iclass 34, count 0 2006.196.07:57:48.20#ibcon#*mode == 0, iclass 34, count 0 2006.196.07:57:48.20#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.196.07:57:48.20#ibcon#[25=USB\r\n] 2006.196.07:57:48.20#ibcon#*before write, iclass 34, count 0 2006.196.07:57:48.20#ibcon#enter sib2, iclass 34, count 0 2006.196.07:57:48.20#ibcon#flushed, iclass 34, count 0 2006.196.07:57:48.20#ibcon#about to write, iclass 34, count 0 2006.196.07:57:48.20#ibcon#wrote, iclass 34, count 0 2006.196.07:57:48.20#ibcon#about to read 3, iclass 34, count 0 2006.196.07:57:48.23#ibcon#read 3, iclass 34, count 0 2006.196.07:57:48.23#ibcon#about to read 4, iclass 34, count 0 2006.196.07:57:48.23#ibcon#read 4, iclass 34, count 0 2006.196.07:57:48.23#ibcon#about to read 5, iclass 34, count 0 2006.196.07:57:48.23#ibcon#read 5, iclass 34, count 0 2006.196.07:57:48.23#ibcon#about to read 6, iclass 34, count 0 2006.196.07:57:48.23#ibcon#read 6, iclass 34, count 0 2006.196.07:57:48.23#ibcon#end of sib2, iclass 34, count 0 2006.196.07:57:48.23#ibcon#*after write, iclass 34, count 0 2006.196.07:57:48.23#ibcon#*before return 0, iclass 34, count 0 2006.196.07:57:48.23#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.196.07:57:48.23#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.196.07:57:48.23#ibcon#about to clear, iclass 34 cls_cnt 0 2006.196.07:57:48.23#ibcon#cleared, iclass 34 cls_cnt 0 2006.196.07:57:48.23$vc4f8/valo=2,572.99 2006.196.07:57:48.23#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.196.07:57:48.23#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.196.07:57:48.23#ibcon#ireg 17 cls_cnt 0 2006.196.07:57:48.23#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.196.07:57:48.23#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.196.07:57:48.23#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.196.07:57:48.23#ibcon#enter wrdev, iclass 36, count 0 2006.196.07:57:48.23#ibcon#first serial, iclass 36, count 0 2006.196.07:57:48.23#ibcon#enter sib2, iclass 36, count 0 2006.196.07:57:48.23#ibcon#flushed, iclass 36, count 0 2006.196.07:57:48.23#ibcon#about to write, iclass 36, count 0 2006.196.07:57:48.23#ibcon#wrote, iclass 36, count 0 2006.196.07:57:48.23#ibcon#about to read 3, iclass 36, count 0 2006.196.07:57:48.25#ibcon#read 3, iclass 36, count 0 2006.196.07:57:48.25#ibcon#about to read 4, iclass 36, count 0 2006.196.07:57:48.25#ibcon#read 4, iclass 36, count 0 2006.196.07:57:48.25#ibcon#about to read 5, iclass 36, count 0 2006.196.07:57:48.25#ibcon#read 5, iclass 36, count 0 2006.196.07:57:48.25#ibcon#about to read 6, iclass 36, count 0 2006.196.07:57:48.25#ibcon#read 6, iclass 36, count 0 2006.196.07:57:48.25#ibcon#end of sib2, iclass 36, count 0 2006.196.07:57:48.25#ibcon#*mode == 0, iclass 36, count 0 2006.196.07:57:48.25#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.196.07:57:48.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.196.07:57:48.25#ibcon#*before write, iclass 36, count 0 2006.196.07:57:48.25#ibcon#enter sib2, iclass 36, count 0 2006.196.07:57:48.25#ibcon#flushed, iclass 36, count 0 2006.196.07:57:48.25#ibcon#about to write, iclass 36, count 0 2006.196.07:57:48.25#ibcon#wrote, iclass 36, count 0 2006.196.07:57:48.25#ibcon#about to read 3, iclass 36, count 0 2006.196.07:57:48.30#ibcon#read 3, iclass 36, count 0 2006.196.07:57:48.30#ibcon#about to read 4, iclass 36, count 0 2006.196.07:57:48.30#ibcon#read 4, iclass 36, count 0 2006.196.07:57:48.30#ibcon#about to read 5, iclass 36, count 0 2006.196.07:57:48.30#ibcon#read 5, iclass 36, count 0 2006.196.07:57:48.30#ibcon#about to read 6, iclass 36, count 0 2006.196.07:57:48.30#ibcon#read 6, iclass 36, count 0 2006.196.07:57:48.30#ibcon#end of sib2, iclass 36, count 0 2006.196.07:57:48.30#ibcon#*after write, iclass 36, count 0 2006.196.07:57:48.30#ibcon#*before return 0, iclass 36, count 0 2006.196.07:57:48.30#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.196.07:57:48.30#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.196.07:57:48.30#ibcon#about to clear, iclass 36 cls_cnt 0 2006.196.07:57:48.30#ibcon#cleared, iclass 36 cls_cnt 0 2006.196.07:57:48.30$vc4f8/va=2,7 2006.196.07:57:48.30#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.196.07:57:48.30#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.196.07:57:48.30#ibcon#ireg 11 cls_cnt 2 2006.196.07:57:48.30#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.196.07:57:48.35#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.196.07:57:48.35#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.196.07:57:48.35#ibcon#enter wrdev, iclass 38, count 2 2006.196.07:57:48.35#ibcon#first serial, iclass 38, count 2 2006.196.07:57:48.35#ibcon#enter sib2, iclass 38, count 2 2006.196.07:57:48.35#ibcon#flushed, iclass 38, count 2 2006.196.07:57:48.35#ibcon#about to write, iclass 38, count 2 2006.196.07:57:48.35#ibcon#wrote, iclass 38, count 2 2006.196.07:57:48.35#ibcon#about to read 3, iclass 38, count 2 2006.196.07:57:48.37#ibcon#read 3, iclass 38, count 2 2006.196.07:57:48.37#ibcon#about to read 4, iclass 38, count 2 2006.196.07:57:48.37#ibcon#read 4, iclass 38, count 2 2006.196.07:57:48.37#ibcon#about to read 5, iclass 38, count 2 2006.196.07:57:48.37#ibcon#read 5, iclass 38, count 2 2006.196.07:57:48.37#ibcon#about to read 6, iclass 38, count 2 2006.196.07:57:48.37#ibcon#read 6, iclass 38, count 2 2006.196.07:57:48.37#ibcon#end of sib2, iclass 38, count 2 2006.196.07:57:48.37#ibcon#*mode == 0, iclass 38, count 2 2006.196.07:57:48.37#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.196.07:57:48.37#ibcon#[25=AT02-07\r\n] 2006.196.07:57:48.37#ibcon#*before write, iclass 38, count 2 2006.196.07:57:48.37#ibcon#enter sib2, iclass 38, count 2 2006.196.07:57:48.37#ibcon#flushed, iclass 38, count 2 2006.196.07:57:48.37#ibcon#about to write, iclass 38, count 2 2006.196.07:57:48.37#ibcon#wrote, iclass 38, count 2 2006.196.07:57:48.37#ibcon#about to read 3, iclass 38, count 2 2006.196.07:57:48.40#ibcon#read 3, iclass 38, count 2 2006.196.07:57:48.40#ibcon#about to read 4, iclass 38, count 2 2006.196.07:57:48.40#ibcon#read 4, iclass 38, count 2 2006.196.07:57:48.40#ibcon#about to read 5, iclass 38, count 2 2006.196.07:57:48.40#ibcon#read 5, iclass 38, count 2 2006.196.07:57:48.40#ibcon#about to read 6, iclass 38, count 2 2006.196.07:57:48.40#ibcon#read 6, iclass 38, count 2 2006.196.07:57:48.40#ibcon#end of sib2, iclass 38, count 2 2006.196.07:57:48.40#ibcon#*after write, iclass 38, count 2 2006.196.07:57:48.40#ibcon#*before return 0, iclass 38, count 2 2006.196.07:57:48.40#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.196.07:57:48.40#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.196.07:57:48.40#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.196.07:57:48.40#ibcon#ireg 7 cls_cnt 0 2006.196.07:57:48.40#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.196.07:57:48.52#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.196.07:57:48.52#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.196.07:57:48.52#ibcon#enter wrdev, iclass 38, count 0 2006.196.07:57:48.52#ibcon#first serial, iclass 38, count 0 2006.196.07:57:48.52#ibcon#enter sib2, iclass 38, count 0 2006.196.07:57:48.52#ibcon#flushed, iclass 38, count 0 2006.196.07:57:48.52#ibcon#about to write, iclass 38, count 0 2006.196.07:57:48.52#ibcon#wrote, iclass 38, count 0 2006.196.07:57:48.52#ibcon#about to read 3, iclass 38, count 0 2006.196.07:57:48.54#ibcon#read 3, iclass 38, count 0 2006.196.07:57:48.54#ibcon#about to read 4, iclass 38, count 0 2006.196.07:57:48.54#ibcon#read 4, iclass 38, count 0 2006.196.07:57:48.54#ibcon#about to read 5, iclass 38, count 0 2006.196.07:57:48.54#ibcon#read 5, iclass 38, count 0 2006.196.07:57:48.54#ibcon#about to read 6, iclass 38, count 0 2006.196.07:57:48.54#ibcon#read 6, iclass 38, count 0 2006.196.07:57:48.54#ibcon#end of sib2, iclass 38, count 0 2006.196.07:57:48.54#ibcon#*mode == 0, iclass 38, count 0 2006.196.07:57:48.54#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.196.07:57:48.54#ibcon#[25=USB\r\n] 2006.196.07:57:48.54#ibcon#*before write, iclass 38, count 0 2006.196.07:57:48.54#ibcon#enter sib2, iclass 38, count 0 2006.196.07:57:48.54#ibcon#flushed, iclass 38, count 0 2006.196.07:57:48.54#ibcon#about to write, iclass 38, count 0 2006.196.07:57:48.54#ibcon#wrote, iclass 38, count 0 2006.196.07:57:48.54#ibcon#about to read 3, iclass 38, count 0 2006.196.07:57:48.57#ibcon#read 3, iclass 38, count 0 2006.196.07:57:48.57#ibcon#about to read 4, iclass 38, count 0 2006.196.07:57:48.57#ibcon#read 4, iclass 38, count 0 2006.196.07:57:48.57#ibcon#about to read 5, iclass 38, count 0 2006.196.07:57:48.57#ibcon#read 5, iclass 38, count 0 2006.196.07:57:48.57#ibcon#about to read 6, iclass 38, count 0 2006.196.07:57:48.57#ibcon#read 6, iclass 38, count 0 2006.196.07:57:48.57#ibcon#end of sib2, iclass 38, count 0 2006.196.07:57:48.57#ibcon#*after write, iclass 38, count 0 2006.196.07:57:48.57#ibcon#*before return 0, iclass 38, count 0 2006.196.07:57:48.57#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.196.07:57:48.57#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.196.07:57:48.57#ibcon#about to clear, iclass 38 cls_cnt 0 2006.196.07:57:48.57#ibcon#cleared, iclass 38 cls_cnt 0 2006.196.07:57:48.57$vc4f8/valo=3,672.99 2006.196.07:57:48.57#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.196.07:57:48.57#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.196.07:57:48.57#ibcon#ireg 17 cls_cnt 0 2006.196.07:57:48.57#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.196.07:57:48.57#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.196.07:57:48.57#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.196.07:57:48.57#ibcon#enter wrdev, iclass 40, count 0 2006.196.07:57:48.57#ibcon#first serial, iclass 40, count 0 2006.196.07:57:48.57#ibcon#enter sib2, iclass 40, count 0 2006.196.07:57:48.57#ibcon#flushed, iclass 40, count 0 2006.196.07:57:48.57#ibcon#about to write, iclass 40, count 0 2006.196.07:57:48.57#ibcon#wrote, iclass 40, count 0 2006.196.07:57:48.57#ibcon#about to read 3, iclass 40, count 0 2006.196.07:57:48.59#ibcon#read 3, iclass 40, count 0 2006.196.07:57:48.59#ibcon#about to read 4, iclass 40, count 0 2006.196.07:57:48.59#ibcon#read 4, iclass 40, count 0 2006.196.07:57:48.59#ibcon#about to read 5, iclass 40, count 0 2006.196.07:57:48.59#ibcon#read 5, iclass 40, count 0 2006.196.07:57:48.59#ibcon#about to read 6, iclass 40, count 0 2006.196.07:57:48.59#ibcon#read 6, iclass 40, count 0 2006.196.07:57:48.59#ibcon#end of sib2, iclass 40, count 0 2006.196.07:57:48.59#ibcon#*mode == 0, iclass 40, count 0 2006.196.07:57:48.59#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.196.07:57:48.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.196.07:57:48.59#ibcon#*before write, iclass 40, count 0 2006.196.07:57:48.59#ibcon#enter sib2, iclass 40, count 0 2006.196.07:57:48.59#ibcon#flushed, iclass 40, count 0 2006.196.07:57:48.59#ibcon#about to write, iclass 40, count 0 2006.196.07:57:48.59#ibcon#wrote, iclass 40, count 0 2006.196.07:57:48.59#ibcon#about to read 3, iclass 40, count 0 2006.196.07:57:48.64#ibcon#read 3, iclass 40, count 0 2006.196.07:57:48.64#ibcon#about to read 4, iclass 40, count 0 2006.196.07:57:48.64#ibcon#read 4, iclass 40, count 0 2006.196.07:57:48.64#ibcon#about to read 5, iclass 40, count 0 2006.196.07:57:48.64#ibcon#read 5, iclass 40, count 0 2006.196.07:57:48.64#ibcon#about to read 6, iclass 40, count 0 2006.196.07:57:48.64#ibcon#read 6, iclass 40, count 0 2006.196.07:57:48.64#ibcon#end of sib2, iclass 40, count 0 2006.196.07:57:48.64#ibcon#*after write, iclass 40, count 0 2006.196.07:57:48.64#ibcon#*before return 0, iclass 40, count 0 2006.196.07:57:48.64#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.196.07:57:48.64#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.196.07:57:48.64#ibcon#about to clear, iclass 40 cls_cnt 0 2006.196.07:57:48.64#ibcon#cleared, iclass 40 cls_cnt 0 2006.196.07:57:48.64$vc4f8/va=3,6 2006.196.07:57:48.64#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.196.07:57:48.64#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.196.07:57:48.64#ibcon#ireg 11 cls_cnt 2 2006.196.07:57:48.64#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.196.07:57:48.69#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.196.07:57:48.69#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.196.07:57:48.69#ibcon#enter wrdev, iclass 4, count 2 2006.196.07:57:48.69#ibcon#first serial, iclass 4, count 2 2006.196.07:57:48.69#ibcon#enter sib2, iclass 4, count 2 2006.196.07:57:48.69#ibcon#flushed, iclass 4, count 2 2006.196.07:57:48.69#ibcon#about to write, iclass 4, count 2 2006.196.07:57:48.69#ibcon#wrote, iclass 4, count 2 2006.196.07:57:48.69#ibcon#about to read 3, iclass 4, count 2 2006.196.07:57:48.71#ibcon#read 3, iclass 4, count 2 2006.196.07:57:48.71#ibcon#about to read 4, iclass 4, count 2 2006.196.07:57:48.71#ibcon#read 4, iclass 4, count 2 2006.196.07:57:48.71#ibcon#about to read 5, iclass 4, count 2 2006.196.07:57:48.71#ibcon#read 5, iclass 4, count 2 2006.196.07:57:48.71#ibcon#about to read 6, iclass 4, count 2 2006.196.07:57:48.71#ibcon#read 6, iclass 4, count 2 2006.196.07:57:48.71#ibcon#end of sib2, iclass 4, count 2 2006.196.07:57:48.71#ibcon#*mode == 0, iclass 4, count 2 2006.196.07:57:48.71#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.196.07:57:48.71#ibcon#[25=AT03-06\r\n] 2006.196.07:57:48.71#ibcon#*before write, iclass 4, count 2 2006.196.07:57:48.71#ibcon#enter sib2, iclass 4, count 2 2006.196.07:57:48.71#ibcon#flushed, iclass 4, count 2 2006.196.07:57:48.71#ibcon#about to write, iclass 4, count 2 2006.196.07:57:48.71#ibcon#wrote, iclass 4, count 2 2006.196.07:57:48.71#ibcon#about to read 3, iclass 4, count 2 2006.196.07:57:48.74#ibcon#read 3, iclass 4, count 2 2006.196.07:57:48.74#ibcon#about to read 4, iclass 4, count 2 2006.196.07:57:48.74#ibcon#read 4, iclass 4, count 2 2006.196.07:57:48.74#ibcon#about to read 5, iclass 4, count 2 2006.196.07:57:48.74#ibcon#read 5, iclass 4, count 2 2006.196.07:57:48.74#ibcon#about to read 6, iclass 4, count 2 2006.196.07:57:48.74#ibcon#read 6, iclass 4, count 2 2006.196.07:57:48.74#ibcon#end of sib2, iclass 4, count 2 2006.196.07:57:48.74#ibcon#*after write, iclass 4, count 2 2006.196.07:57:48.74#ibcon#*before return 0, iclass 4, count 2 2006.196.07:57:48.74#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.196.07:57:48.74#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.196.07:57:48.74#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.196.07:57:48.74#ibcon#ireg 7 cls_cnt 0 2006.196.07:57:48.74#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.196.07:57:48.86#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.196.07:57:48.86#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.196.07:57:48.86#ibcon#enter wrdev, iclass 4, count 0 2006.196.07:57:48.86#ibcon#first serial, iclass 4, count 0 2006.196.07:57:48.86#ibcon#enter sib2, iclass 4, count 0 2006.196.07:57:48.86#ibcon#flushed, iclass 4, count 0 2006.196.07:57:48.86#ibcon#about to write, iclass 4, count 0 2006.196.07:57:48.86#ibcon#wrote, iclass 4, count 0 2006.196.07:57:48.86#ibcon#about to read 3, iclass 4, count 0 2006.196.07:57:48.88#ibcon#read 3, iclass 4, count 0 2006.196.07:57:48.88#ibcon#about to read 4, iclass 4, count 0 2006.196.07:57:48.88#ibcon#read 4, iclass 4, count 0 2006.196.07:57:48.88#ibcon#about to read 5, iclass 4, count 0 2006.196.07:57:48.88#ibcon#read 5, iclass 4, count 0 2006.196.07:57:48.88#ibcon#about to read 6, iclass 4, count 0 2006.196.07:57:48.88#ibcon#read 6, iclass 4, count 0 2006.196.07:57:48.88#ibcon#end of sib2, iclass 4, count 0 2006.196.07:57:48.88#ibcon#*mode == 0, iclass 4, count 0 2006.196.07:57:48.88#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.196.07:57:48.88#ibcon#[25=USB\r\n] 2006.196.07:57:48.88#ibcon#*before write, iclass 4, count 0 2006.196.07:57:48.88#ibcon#enter sib2, iclass 4, count 0 2006.196.07:57:48.88#ibcon#flushed, iclass 4, count 0 2006.196.07:57:48.88#ibcon#about to write, iclass 4, count 0 2006.196.07:57:48.88#ibcon#wrote, iclass 4, count 0 2006.196.07:57:48.88#ibcon#about to read 3, iclass 4, count 0 2006.196.07:57:48.91#ibcon#read 3, iclass 4, count 0 2006.196.07:57:48.91#ibcon#about to read 4, iclass 4, count 0 2006.196.07:57:48.91#ibcon#read 4, iclass 4, count 0 2006.196.07:57:48.91#ibcon#about to read 5, iclass 4, count 0 2006.196.07:57:48.91#ibcon#read 5, iclass 4, count 0 2006.196.07:57:48.91#ibcon#about to read 6, iclass 4, count 0 2006.196.07:57:48.91#ibcon#read 6, iclass 4, count 0 2006.196.07:57:48.91#ibcon#end of sib2, iclass 4, count 0 2006.196.07:57:48.91#ibcon#*after write, iclass 4, count 0 2006.196.07:57:48.91#ibcon#*before return 0, iclass 4, count 0 2006.196.07:57:48.91#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.196.07:57:48.91#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.196.07:57:48.91#ibcon#about to clear, iclass 4 cls_cnt 0 2006.196.07:57:48.91#ibcon#cleared, iclass 4 cls_cnt 0 2006.196.07:57:48.91$vc4f8/valo=4,832.99 2006.196.07:57:48.91#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.196.07:57:48.91#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.196.07:57:48.91#ibcon#ireg 17 cls_cnt 0 2006.196.07:57:48.91#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.196.07:57:48.91#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.196.07:57:48.91#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.196.07:57:48.91#ibcon#enter wrdev, iclass 6, count 0 2006.196.07:57:48.91#ibcon#first serial, iclass 6, count 0 2006.196.07:57:48.91#ibcon#enter sib2, iclass 6, count 0 2006.196.07:57:48.91#ibcon#flushed, iclass 6, count 0 2006.196.07:57:48.91#ibcon#about to write, iclass 6, count 0 2006.196.07:57:48.91#ibcon#wrote, iclass 6, count 0 2006.196.07:57:48.91#ibcon#about to read 3, iclass 6, count 0 2006.196.07:57:48.93#ibcon#read 3, iclass 6, count 0 2006.196.07:57:48.93#ibcon#about to read 4, iclass 6, count 0 2006.196.07:57:48.93#ibcon#read 4, iclass 6, count 0 2006.196.07:57:48.93#ibcon#about to read 5, iclass 6, count 0 2006.196.07:57:48.93#ibcon#read 5, iclass 6, count 0 2006.196.07:57:48.93#ibcon#about to read 6, iclass 6, count 0 2006.196.07:57:48.93#ibcon#read 6, iclass 6, count 0 2006.196.07:57:48.93#ibcon#end of sib2, iclass 6, count 0 2006.196.07:57:48.93#ibcon#*mode == 0, iclass 6, count 0 2006.196.07:57:48.93#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.196.07:57:48.93#ibcon#[26=FRQ=04,832.99\r\n] 2006.196.07:57:48.93#ibcon#*before write, iclass 6, count 0 2006.196.07:57:48.93#ibcon#enter sib2, iclass 6, count 0 2006.196.07:57:48.93#ibcon#flushed, iclass 6, count 0 2006.196.07:57:48.93#ibcon#about to write, iclass 6, count 0 2006.196.07:57:48.93#ibcon#wrote, iclass 6, count 0 2006.196.07:57:48.93#ibcon#about to read 3, iclass 6, count 0 2006.196.07:57:48.98#ibcon#read 3, iclass 6, count 0 2006.196.07:57:48.98#ibcon#about to read 4, iclass 6, count 0 2006.196.07:57:48.98#ibcon#read 4, iclass 6, count 0 2006.196.07:57:48.98#ibcon#about to read 5, iclass 6, count 0 2006.196.07:57:48.98#ibcon#read 5, iclass 6, count 0 2006.196.07:57:48.98#ibcon#about to read 6, iclass 6, count 0 2006.196.07:57:48.98#ibcon#read 6, iclass 6, count 0 2006.196.07:57:48.98#ibcon#end of sib2, iclass 6, count 0 2006.196.07:57:48.98#ibcon#*after write, iclass 6, count 0 2006.196.07:57:48.98#ibcon#*before return 0, iclass 6, count 0 2006.196.07:57:48.98#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.196.07:57:48.98#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.196.07:57:48.98#ibcon#about to clear, iclass 6 cls_cnt 0 2006.196.07:57:48.98#ibcon#cleared, iclass 6 cls_cnt 0 2006.196.07:57:48.98$vc4f8/va=4,7 2006.196.07:57:48.98#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.196.07:57:48.98#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.196.07:57:48.98#ibcon#ireg 11 cls_cnt 2 2006.196.07:57:48.98#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.196.07:57:49.03#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.196.07:57:49.03#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.196.07:57:49.03#ibcon#enter wrdev, iclass 10, count 2 2006.196.07:57:49.03#ibcon#first serial, iclass 10, count 2 2006.196.07:57:49.03#ibcon#enter sib2, iclass 10, count 2 2006.196.07:57:49.03#ibcon#flushed, iclass 10, count 2 2006.196.07:57:49.03#ibcon#about to write, iclass 10, count 2 2006.196.07:57:49.03#ibcon#wrote, iclass 10, count 2 2006.196.07:57:49.03#ibcon#about to read 3, iclass 10, count 2 2006.196.07:57:49.05#ibcon#read 3, iclass 10, count 2 2006.196.07:57:49.05#ibcon#about to read 4, iclass 10, count 2 2006.196.07:57:49.05#ibcon#read 4, iclass 10, count 2 2006.196.07:57:49.05#ibcon#about to read 5, iclass 10, count 2 2006.196.07:57:49.05#ibcon#read 5, iclass 10, count 2 2006.196.07:57:49.05#ibcon#about to read 6, iclass 10, count 2 2006.196.07:57:49.05#ibcon#read 6, iclass 10, count 2 2006.196.07:57:49.05#ibcon#end of sib2, iclass 10, count 2 2006.196.07:57:49.05#ibcon#*mode == 0, iclass 10, count 2 2006.196.07:57:49.05#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.196.07:57:49.05#ibcon#[25=AT04-07\r\n] 2006.196.07:57:49.05#ibcon#*before write, iclass 10, count 2 2006.196.07:57:49.05#ibcon#enter sib2, iclass 10, count 2 2006.196.07:57:49.05#ibcon#flushed, iclass 10, count 2 2006.196.07:57:49.05#ibcon#about to write, iclass 10, count 2 2006.196.07:57:49.05#ibcon#wrote, iclass 10, count 2 2006.196.07:57:49.05#ibcon#about to read 3, iclass 10, count 2 2006.196.07:57:49.08#ibcon#read 3, iclass 10, count 2 2006.196.07:57:49.08#ibcon#about to read 4, iclass 10, count 2 2006.196.07:57:49.08#ibcon#read 4, iclass 10, count 2 2006.196.07:57:49.08#ibcon#about to read 5, iclass 10, count 2 2006.196.07:57:49.08#ibcon#read 5, iclass 10, count 2 2006.196.07:57:49.08#ibcon#about to read 6, iclass 10, count 2 2006.196.07:57:49.08#ibcon#read 6, iclass 10, count 2 2006.196.07:57:49.08#ibcon#end of sib2, iclass 10, count 2 2006.196.07:57:49.08#ibcon#*after write, iclass 10, count 2 2006.196.07:57:49.08#ibcon#*before return 0, iclass 10, count 2 2006.196.07:57:49.08#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.196.07:57:49.08#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.196.07:57:49.08#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.196.07:57:49.08#ibcon#ireg 7 cls_cnt 0 2006.196.07:57:49.08#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.196.07:57:49.20#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.196.07:57:49.20#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.196.07:57:49.20#ibcon#enter wrdev, iclass 10, count 0 2006.196.07:57:49.20#ibcon#first serial, iclass 10, count 0 2006.196.07:57:49.20#ibcon#enter sib2, iclass 10, count 0 2006.196.07:57:49.20#ibcon#flushed, iclass 10, count 0 2006.196.07:57:49.20#ibcon#about to write, iclass 10, count 0 2006.196.07:57:49.20#ibcon#wrote, iclass 10, count 0 2006.196.07:57:49.20#ibcon#about to read 3, iclass 10, count 0 2006.196.07:57:49.22#ibcon#read 3, iclass 10, count 0 2006.196.07:57:49.22#ibcon#about to read 4, iclass 10, count 0 2006.196.07:57:49.22#ibcon#read 4, iclass 10, count 0 2006.196.07:57:49.22#ibcon#about to read 5, iclass 10, count 0 2006.196.07:57:49.22#ibcon#read 5, iclass 10, count 0 2006.196.07:57:49.22#ibcon#about to read 6, iclass 10, count 0 2006.196.07:57:49.22#ibcon#read 6, iclass 10, count 0 2006.196.07:57:49.22#ibcon#end of sib2, iclass 10, count 0 2006.196.07:57:49.22#ibcon#*mode == 0, iclass 10, count 0 2006.196.07:57:49.22#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.196.07:57:49.22#ibcon#[25=USB\r\n] 2006.196.07:57:49.22#ibcon#*before write, iclass 10, count 0 2006.196.07:57:49.22#ibcon#enter sib2, iclass 10, count 0 2006.196.07:57:49.22#ibcon#flushed, iclass 10, count 0 2006.196.07:57:49.22#ibcon#about to write, iclass 10, count 0 2006.196.07:57:49.22#ibcon#wrote, iclass 10, count 0 2006.196.07:57:49.22#ibcon#about to read 3, iclass 10, count 0 2006.196.07:57:49.25#ibcon#read 3, iclass 10, count 0 2006.196.07:57:49.25#ibcon#about to read 4, iclass 10, count 0 2006.196.07:57:49.25#ibcon#read 4, iclass 10, count 0 2006.196.07:57:49.25#ibcon#about to read 5, iclass 10, count 0 2006.196.07:57:49.25#ibcon#read 5, iclass 10, count 0 2006.196.07:57:49.25#ibcon#about to read 6, iclass 10, count 0 2006.196.07:57:49.25#ibcon#read 6, iclass 10, count 0 2006.196.07:57:49.25#ibcon#end of sib2, iclass 10, count 0 2006.196.07:57:49.25#ibcon#*after write, iclass 10, count 0 2006.196.07:57:49.25#ibcon#*before return 0, iclass 10, count 0 2006.196.07:57:49.25#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.196.07:57:49.25#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.196.07:57:49.25#ibcon#about to clear, iclass 10 cls_cnt 0 2006.196.07:57:49.25#ibcon#cleared, iclass 10 cls_cnt 0 2006.196.07:57:49.25$vc4f8/valo=5,652.99 2006.196.07:57:49.25#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.196.07:57:49.25#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.196.07:57:49.25#ibcon#ireg 17 cls_cnt 0 2006.196.07:57:49.25#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.196.07:57:49.25#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.196.07:57:49.25#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.196.07:57:49.25#ibcon#enter wrdev, iclass 12, count 0 2006.196.07:57:49.25#ibcon#first serial, iclass 12, count 0 2006.196.07:57:49.25#ibcon#enter sib2, iclass 12, count 0 2006.196.07:57:49.25#ibcon#flushed, iclass 12, count 0 2006.196.07:57:49.25#ibcon#about to write, iclass 12, count 0 2006.196.07:57:49.25#ibcon#wrote, iclass 12, count 0 2006.196.07:57:49.25#ibcon#about to read 3, iclass 12, count 0 2006.196.07:57:49.27#ibcon#read 3, iclass 12, count 0 2006.196.07:57:49.27#ibcon#about to read 4, iclass 12, count 0 2006.196.07:57:49.27#ibcon#read 4, iclass 12, count 0 2006.196.07:57:49.27#ibcon#about to read 5, iclass 12, count 0 2006.196.07:57:49.27#ibcon#read 5, iclass 12, count 0 2006.196.07:57:49.27#ibcon#about to read 6, iclass 12, count 0 2006.196.07:57:49.27#ibcon#read 6, iclass 12, count 0 2006.196.07:57:49.27#ibcon#end of sib2, iclass 12, count 0 2006.196.07:57:49.27#ibcon#*mode == 0, iclass 12, count 0 2006.196.07:57:49.27#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.196.07:57:49.27#ibcon#[26=FRQ=05,652.99\r\n] 2006.196.07:57:49.27#ibcon#*before write, iclass 12, count 0 2006.196.07:57:49.27#ibcon#enter sib2, iclass 12, count 0 2006.196.07:57:49.27#ibcon#flushed, iclass 12, count 0 2006.196.07:57:49.27#ibcon#about to write, iclass 12, count 0 2006.196.07:57:49.27#ibcon#wrote, iclass 12, count 0 2006.196.07:57:49.27#ibcon#about to read 3, iclass 12, count 0 2006.196.07:57:49.31#ibcon#read 3, iclass 12, count 0 2006.196.07:57:49.31#ibcon#about to read 4, iclass 12, count 0 2006.196.07:57:49.31#ibcon#read 4, iclass 12, count 0 2006.196.07:57:49.31#ibcon#about to read 5, iclass 12, count 0 2006.196.07:57:49.31#ibcon#read 5, iclass 12, count 0 2006.196.07:57:49.31#ibcon#about to read 6, iclass 12, count 0 2006.196.07:57:49.31#ibcon#read 6, iclass 12, count 0 2006.196.07:57:49.31#ibcon#end of sib2, iclass 12, count 0 2006.196.07:57:49.31#ibcon#*after write, iclass 12, count 0 2006.196.07:57:49.31#ibcon#*before return 0, iclass 12, count 0 2006.196.07:57:49.31#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.196.07:57:49.31#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.196.07:57:49.31#ibcon#about to clear, iclass 12 cls_cnt 0 2006.196.07:57:49.31#ibcon#cleared, iclass 12 cls_cnt 0 2006.196.07:57:49.31$vc4f8/va=5,7 2006.196.07:57:49.31#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.196.07:57:49.31#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.196.07:57:49.31#ibcon#ireg 11 cls_cnt 2 2006.196.07:57:49.31#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.196.07:57:49.37#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.196.07:57:49.37#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.196.07:57:49.37#ibcon#enter wrdev, iclass 14, count 2 2006.196.07:57:49.37#ibcon#first serial, iclass 14, count 2 2006.196.07:57:49.37#ibcon#enter sib2, iclass 14, count 2 2006.196.07:57:49.37#ibcon#flushed, iclass 14, count 2 2006.196.07:57:49.37#ibcon#about to write, iclass 14, count 2 2006.196.07:57:49.37#ibcon#wrote, iclass 14, count 2 2006.196.07:57:49.37#ibcon#about to read 3, iclass 14, count 2 2006.196.07:57:49.39#ibcon#read 3, iclass 14, count 2 2006.196.07:57:49.39#ibcon#about to read 4, iclass 14, count 2 2006.196.07:57:49.39#ibcon#read 4, iclass 14, count 2 2006.196.07:57:49.39#ibcon#about to read 5, iclass 14, count 2 2006.196.07:57:49.39#ibcon#read 5, iclass 14, count 2 2006.196.07:57:49.39#ibcon#about to read 6, iclass 14, count 2 2006.196.07:57:49.39#ibcon#read 6, iclass 14, count 2 2006.196.07:57:49.39#ibcon#end of sib2, iclass 14, count 2 2006.196.07:57:49.39#ibcon#*mode == 0, iclass 14, count 2 2006.196.07:57:49.39#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.196.07:57:49.39#ibcon#[25=AT05-07\r\n] 2006.196.07:57:49.39#ibcon#*before write, iclass 14, count 2 2006.196.07:57:49.39#ibcon#enter sib2, iclass 14, count 2 2006.196.07:57:49.39#ibcon#flushed, iclass 14, count 2 2006.196.07:57:49.39#ibcon#about to write, iclass 14, count 2 2006.196.07:57:49.39#ibcon#wrote, iclass 14, count 2 2006.196.07:57:49.39#ibcon#about to read 3, iclass 14, count 2 2006.196.07:57:49.43#ibcon#read 3, iclass 14, count 2 2006.196.07:57:49.43#ibcon#about to read 4, iclass 14, count 2 2006.196.07:57:49.43#ibcon#read 4, iclass 14, count 2 2006.196.07:57:49.43#ibcon#about to read 5, iclass 14, count 2 2006.196.07:57:49.43#ibcon#read 5, iclass 14, count 2 2006.196.07:57:49.43#ibcon#about to read 6, iclass 14, count 2 2006.196.07:57:49.43#ibcon#read 6, iclass 14, count 2 2006.196.07:57:49.43#ibcon#end of sib2, iclass 14, count 2 2006.196.07:57:49.43#ibcon#*after write, iclass 14, count 2 2006.196.07:57:49.43#ibcon#*before return 0, iclass 14, count 2 2006.196.07:57:49.43#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.196.07:57:49.43#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.196.07:57:49.43#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.196.07:57:49.43#ibcon#ireg 7 cls_cnt 0 2006.196.07:57:49.43#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.196.07:57:49.55#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.196.07:57:49.55#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.196.07:57:49.55#ibcon#enter wrdev, iclass 14, count 0 2006.196.07:57:49.55#ibcon#first serial, iclass 14, count 0 2006.196.07:57:49.55#ibcon#enter sib2, iclass 14, count 0 2006.196.07:57:49.55#ibcon#flushed, iclass 14, count 0 2006.196.07:57:49.55#ibcon#about to write, iclass 14, count 0 2006.196.07:57:49.55#ibcon#wrote, iclass 14, count 0 2006.196.07:57:49.55#ibcon#about to read 3, iclass 14, count 0 2006.196.07:57:49.57#ibcon#read 3, iclass 14, count 0 2006.196.07:57:49.57#ibcon#about to read 4, iclass 14, count 0 2006.196.07:57:49.57#ibcon#read 4, iclass 14, count 0 2006.196.07:57:49.57#ibcon#about to read 5, iclass 14, count 0 2006.196.07:57:49.57#ibcon#read 5, iclass 14, count 0 2006.196.07:57:49.57#ibcon#about to read 6, iclass 14, count 0 2006.196.07:57:49.57#ibcon#read 6, iclass 14, count 0 2006.196.07:57:49.57#ibcon#end of sib2, iclass 14, count 0 2006.196.07:57:49.57#ibcon#*mode == 0, iclass 14, count 0 2006.196.07:57:49.57#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.196.07:57:49.57#ibcon#[25=USB\r\n] 2006.196.07:57:49.57#ibcon#*before write, iclass 14, count 0 2006.196.07:57:49.57#ibcon#enter sib2, iclass 14, count 0 2006.196.07:57:49.57#ibcon#flushed, iclass 14, count 0 2006.196.07:57:49.57#ibcon#about to write, iclass 14, count 0 2006.196.07:57:49.57#ibcon#wrote, iclass 14, count 0 2006.196.07:57:49.57#ibcon#about to read 3, iclass 14, count 0 2006.196.07:57:49.60#ibcon#read 3, iclass 14, count 0 2006.196.07:57:49.60#ibcon#about to read 4, iclass 14, count 0 2006.196.07:57:49.60#ibcon#read 4, iclass 14, count 0 2006.196.07:57:49.60#ibcon#about to read 5, iclass 14, count 0 2006.196.07:57:49.60#ibcon#read 5, iclass 14, count 0 2006.196.07:57:49.60#ibcon#about to read 6, iclass 14, count 0 2006.196.07:57:49.60#ibcon#read 6, iclass 14, count 0 2006.196.07:57:49.60#ibcon#end of sib2, iclass 14, count 0 2006.196.07:57:49.60#ibcon#*after write, iclass 14, count 0 2006.196.07:57:49.60#ibcon#*before return 0, iclass 14, count 0 2006.196.07:57:49.60#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.196.07:57:49.60#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.196.07:57:49.60#ibcon#about to clear, iclass 14 cls_cnt 0 2006.196.07:57:49.60#ibcon#cleared, iclass 14 cls_cnt 0 2006.196.07:57:49.60$vc4f8/valo=6,772.99 2006.196.07:57:49.60#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.196.07:57:49.60#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.196.07:57:49.60#ibcon#ireg 17 cls_cnt 0 2006.196.07:57:49.60#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.196.07:57:49.60#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.196.07:57:49.60#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.196.07:57:49.60#ibcon#enter wrdev, iclass 16, count 0 2006.196.07:57:49.60#ibcon#first serial, iclass 16, count 0 2006.196.07:57:49.60#ibcon#enter sib2, iclass 16, count 0 2006.196.07:57:49.60#ibcon#flushed, iclass 16, count 0 2006.196.07:57:49.60#ibcon#about to write, iclass 16, count 0 2006.196.07:57:49.60#ibcon#wrote, iclass 16, count 0 2006.196.07:57:49.60#ibcon#about to read 3, iclass 16, count 0 2006.196.07:57:49.62#ibcon#read 3, iclass 16, count 0 2006.196.07:57:49.62#ibcon#about to read 4, iclass 16, count 0 2006.196.07:57:49.62#ibcon#read 4, iclass 16, count 0 2006.196.07:57:49.62#ibcon#about to read 5, iclass 16, count 0 2006.196.07:57:49.62#ibcon#read 5, iclass 16, count 0 2006.196.07:57:49.62#ibcon#about to read 6, iclass 16, count 0 2006.196.07:57:49.62#ibcon#read 6, iclass 16, count 0 2006.196.07:57:49.62#ibcon#end of sib2, iclass 16, count 0 2006.196.07:57:49.62#ibcon#*mode == 0, iclass 16, count 0 2006.196.07:57:49.62#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.196.07:57:49.62#ibcon#[26=FRQ=06,772.99\r\n] 2006.196.07:57:49.62#ibcon#*before write, iclass 16, count 0 2006.196.07:57:49.62#ibcon#enter sib2, iclass 16, count 0 2006.196.07:57:49.62#ibcon#flushed, iclass 16, count 0 2006.196.07:57:49.62#ibcon#about to write, iclass 16, count 0 2006.196.07:57:49.62#ibcon#wrote, iclass 16, count 0 2006.196.07:57:49.62#ibcon#about to read 3, iclass 16, count 0 2006.196.07:57:49.67#ibcon#read 3, iclass 16, count 0 2006.196.07:57:49.67#ibcon#about to read 4, iclass 16, count 0 2006.196.07:57:49.67#ibcon#read 4, iclass 16, count 0 2006.196.07:57:49.67#ibcon#about to read 5, iclass 16, count 0 2006.196.07:57:49.67#ibcon#read 5, iclass 16, count 0 2006.196.07:57:49.67#ibcon#about to read 6, iclass 16, count 0 2006.196.07:57:49.67#ibcon#read 6, iclass 16, count 0 2006.196.07:57:49.67#ibcon#end of sib2, iclass 16, count 0 2006.196.07:57:49.67#ibcon#*after write, iclass 16, count 0 2006.196.07:57:49.67#ibcon#*before return 0, iclass 16, count 0 2006.196.07:57:49.67#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.196.07:57:49.67#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.196.07:57:49.67#ibcon#about to clear, iclass 16 cls_cnt 0 2006.196.07:57:49.67#ibcon#cleared, iclass 16 cls_cnt 0 2006.196.07:57:49.67$vc4f8/va=6,6 2006.196.07:57:49.67#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.196.07:57:49.67#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.196.07:57:49.67#ibcon#ireg 11 cls_cnt 2 2006.196.07:57:49.67#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.196.07:57:49.72#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.196.07:57:49.72#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.196.07:57:49.72#ibcon#enter wrdev, iclass 18, count 2 2006.196.07:57:49.72#ibcon#first serial, iclass 18, count 2 2006.196.07:57:49.72#ibcon#enter sib2, iclass 18, count 2 2006.196.07:57:49.72#ibcon#flushed, iclass 18, count 2 2006.196.07:57:49.72#ibcon#about to write, iclass 18, count 2 2006.196.07:57:49.72#ibcon#wrote, iclass 18, count 2 2006.196.07:57:49.72#ibcon#about to read 3, iclass 18, count 2 2006.196.07:57:49.74#ibcon#read 3, iclass 18, count 2 2006.196.07:57:49.74#ibcon#about to read 4, iclass 18, count 2 2006.196.07:57:49.74#ibcon#read 4, iclass 18, count 2 2006.196.07:57:49.74#ibcon#about to read 5, iclass 18, count 2 2006.196.07:57:49.74#ibcon#read 5, iclass 18, count 2 2006.196.07:57:49.74#ibcon#about to read 6, iclass 18, count 2 2006.196.07:57:49.74#ibcon#read 6, iclass 18, count 2 2006.196.07:57:49.74#ibcon#end of sib2, iclass 18, count 2 2006.196.07:57:49.74#ibcon#*mode == 0, iclass 18, count 2 2006.196.07:57:49.74#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.196.07:57:49.74#ibcon#[25=AT06-06\r\n] 2006.196.07:57:49.74#ibcon#*before write, iclass 18, count 2 2006.196.07:57:49.74#ibcon#enter sib2, iclass 18, count 2 2006.196.07:57:49.74#ibcon#flushed, iclass 18, count 2 2006.196.07:57:49.74#ibcon#about to write, iclass 18, count 2 2006.196.07:57:49.74#ibcon#wrote, iclass 18, count 2 2006.196.07:57:49.74#ibcon#about to read 3, iclass 18, count 2 2006.196.07:57:49.77#ibcon#read 3, iclass 18, count 2 2006.196.07:57:49.77#ibcon#about to read 4, iclass 18, count 2 2006.196.07:57:49.77#ibcon#read 4, iclass 18, count 2 2006.196.07:57:49.77#ibcon#about to read 5, iclass 18, count 2 2006.196.07:57:49.77#ibcon#read 5, iclass 18, count 2 2006.196.07:57:49.77#ibcon#about to read 6, iclass 18, count 2 2006.196.07:57:49.77#ibcon#read 6, iclass 18, count 2 2006.196.07:57:49.77#ibcon#end of sib2, iclass 18, count 2 2006.196.07:57:49.77#ibcon#*after write, iclass 18, count 2 2006.196.07:57:49.77#ibcon#*before return 0, iclass 18, count 2 2006.196.07:57:49.77#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.196.07:57:49.77#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.196.07:57:49.77#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.196.07:57:49.77#ibcon#ireg 7 cls_cnt 0 2006.196.07:57:49.77#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.196.07:57:49.89#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.196.07:57:49.89#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.196.07:57:49.89#ibcon#enter wrdev, iclass 18, count 0 2006.196.07:57:49.89#ibcon#first serial, iclass 18, count 0 2006.196.07:57:49.89#ibcon#enter sib2, iclass 18, count 0 2006.196.07:57:49.89#ibcon#flushed, iclass 18, count 0 2006.196.07:57:49.89#ibcon#about to write, iclass 18, count 0 2006.196.07:57:49.89#ibcon#wrote, iclass 18, count 0 2006.196.07:57:49.89#ibcon#about to read 3, iclass 18, count 0 2006.196.07:57:49.91#ibcon#read 3, iclass 18, count 0 2006.196.07:57:49.91#ibcon#about to read 4, iclass 18, count 0 2006.196.07:57:49.91#ibcon#read 4, iclass 18, count 0 2006.196.07:57:49.91#ibcon#about to read 5, iclass 18, count 0 2006.196.07:57:49.91#ibcon#read 5, iclass 18, count 0 2006.196.07:57:49.91#ibcon#about to read 6, iclass 18, count 0 2006.196.07:57:49.91#ibcon#read 6, iclass 18, count 0 2006.196.07:57:49.91#ibcon#end of sib2, iclass 18, count 0 2006.196.07:57:49.91#ibcon#*mode == 0, iclass 18, count 0 2006.196.07:57:49.91#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.196.07:57:49.91#ibcon#[25=USB\r\n] 2006.196.07:57:49.91#ibcon#*before write, iclass 18, count 0 2006.196.07:57:49.91#ibcon#enter sib2, iclass 18, count 0 2006.196.07:57:49.91#ibcon#flushed, iclass 18, count 0 2006.196.07:57:49.91#ibcon#about to write, iclass 18, count 0 2006.196.07:57:49.91#ibcon#wrote, iclass 18, count 0 2006.196.07:57:49.91#ibcon#about to read 3, iclass 18, count 0 2006.196.07:57:49.94#ibcon#read 3, iclass 18, count 0 2006.196.07:57:49.94#ibcon#about to read 4, iclass 18, count 0 2006.196.07:57:49.94#ibcon#read 4, iclass 18, count 0 2006.196.07:57:49.94#ibcon#about to read 5, iclass 18, count 0 2006.196.07:57:49.94#ibcon#read 5, iclass 18, count 0 2006.196.07:57:49.94#ibcon#about to read 6, iclass 18, count 0 2006.196.07:57:49.94#ibcon#read 6, iclass 18, count 0 2006.196.07:57:49.94#ibcon#end of sib2, iclass 18, count 0 2006.196.07:57:49.94#ibcon#*after write, iclass 18, count 0 2006.196.07:57:49.94#ibcon#*before return 0, iclass 18, count 0 2006.196.07:57:49.94#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.196.07:57:49.94#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.196.07:57:49.94#ibcon#about to clear, iclass 18 cls_cnt 0 2006.196.07:57:49.94#ibcon#cleared, iclass 18 cls_cnt 0 2006.196.07:57:49.94$vc4f8/valo=7,832.99 2006.196.07:57:49.94#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.196.07:57:49.94#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.196.07:57:49.94#ibcon#ireg 17 cls_cnt 0 2006.196.07:57:49.94#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.196.07:57:49.94#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.196.07:57:49.94#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.196.07:57:49.94#ibcon#enter wrdev, iclass 20, count 0 2006.196.07:57:49.94#ibcon#first serial, iclass 20, count 0 2006.196.07:57:49.94#ibcon#enter sib2, iclass 20, count 0 2006.196.07:57:49.94#ibcon#flushed, iclass 20, count 0 2006.196.07:57:49.94#ibcon#about to write, iclass 20, count 0 2006.196.07:57:49.94#ibcon#wrote, iclass 20, count 0 2006.196.07:57:49.94#ibcon#about to read 3, iclass 20, count 0 2006.196.07:57:49.96#ibcon#read 3, iclass 20, count 0 2006.196.07:57:49.96#ibcon#about to read 4, iclass 20, count 0 2006.196.07:57:49.96#ibcon#read 4, iclass 20, count 0 2006.196.07:57:49.96#ibcon#about to read 5, iclass 20, count 0 2006.196.07:57:49.96#ibcon#read 5, iclass 20, count 0 2006.196.07:57:49.96#ibcon#about to read 6, iclass 20, count 0 2006.196.07:57:49.96#ibcon#read 6, iclass 20, count 0 2006.196.07:57:49.96#ibcon#end of sib2, iclass 20, count 0 2006.196.07:57:49.96#ibcon#*mode == 0, iclass 20, count 0 2006.196.07:57:49.96#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.196.07:57:49.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.196.07:57:49.96#ibcon#*before write, iclass 20, count 0 2006.196.07:57:49.96#ibcon#enter sib2, iclass 20, count 0 2006.196.07:57:49.96#ibcon#flushed, iclass 20, count 0 2006.196.07:57:49.96#ibcon#about to write, iclass 20, count 0 2006.196.07:57:49.96#ibcon#wrote, iclass 20, count 0 2006.196.07:57:49.96#ibcon#about to read 3, iclass 20, count 0 2006.196.07:57:50.00#ibcon#read 3, iclass 20, count 0 2006.196.07:57:50.00#ibcon#about to read 4, iclass 20, count 0 2006.196.07:57:50.00#ibcon#read 4, iclass 20, count 0 2006.196.07:57:50.00#ibcon#about to read 5, iclass 20, count 0 2006.196.07:57:50.00#ibcon#read 5, iclass 20, count 0 2006.196.07:57:50.00#ibcon#about to read 6, iclass 20, count 0 2006.196.07:57:50.00#ibcon#read 6, iclass 20, count 0 2006.196.07:57:50.00#ibcon#end of sib2, iclass 20, count 0 2006.196.07:57:50.00#ibcon#*after write, iclass 20, count 0 2006.196.07:57:50.00#ibcon#*before return 0, iclass 20, count 0 2006.196.07:57:50.00#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.196.07:57:50.00#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.196.07:57:50.00#ibcon#about to clear, iclass 20 cls_cnt 0 2006.196.07:57:50.00#ibcon#cleared, iclass 20 cls_cnt 0 2006.196.07:57:50.00$vc4f8/va=7,6 2006.196.07:57:50.00#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.196.07:57:50.00#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.196.07:57:50.00#ibcon#ireg 11 cls_cnt 2 2006.196.07:57:50.00#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.196.07:57:50.06#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.196.07:57:50.06#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.196.07:57:50.06#ibcon#enter wrdev, iclass 22, count 2 2006.196.07:57:50.06#ibcon#first serial, iclass 22, count 2 2006.196.07:57:50.06#ibcon#enter sib2, iclass 22, count 2 2006.196.07:57:50.06#ibcon#flushed, iclass 22, count 2 2006.196.07:57:50.06#ibcon#about to write, iclass 22, count 2 2006.196.07:57:50.06#ibcon#wrote, iclass 22, count 2 2006.196.07:57:50.06#ibcon#about to read 3, iclass 22, count 2 2006.196.07:57:50.08#ibcon#read 3, iclass 22, count 2 2006.196.07:57:50.08#ibcon#about to read 4, iclass 22, count 2 2006.196.07:57:50.08#ibcon#read 4, iclass 22, count 2 2006.196.07:57:50.08#ibcon#about to read 5, iclass 22, count 2 2006.196.07:57:50.08#ibcon#read 5, iclass 22, count 2 2006.196.07:57:50.08#ibcon#about to read 6, iclass 22, count 2 2006.196.07:57:50.08#ibcon#read 6, iclass 22, count 2 2006.196.07:57:50.08#ibcon#end of sib2, iclass 22, count 2 2006.196.07:57:50.08#ibcon#*mode == 0, iclass 22, count 2 2006.196.07:57:50.08#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.196.07:57:50.08#ibcon#[25=AT07-06\r\n] 2006.196.07:57:50.08#ibcon#*before write, iclass 22, count 2 2006.196.07:57:50.08#ibcon#enter sib2, iclass 22, count 2 2006.196.07:57:50.08#ibcon#flushed, iclass 22, count 2 2006.196.07:57:50.08#ibcon#about to write, iclass 22, count 2 2006.196.07:57:50.08#ibcon#wrote, iclass 22, count 2 2006.196.07:57:50.08#ibcon#about to read 3, iclass 22, count 2 2006.196.07:57:50.11#ibcon#read 3, iclass 22, count 2 2006.196.07:57:50.11#ibcon#about to read 4, iclass 22, count 2 2006.196.07:57:50.11#ibcon#read 4, iclass 22, count 2 2006.196.07:57:50.11#ibcon#about to read 5, iclass 22, count 2 2006.196.07:57:50.11#ibcon#read 5, iclass 22, count 2 2006.196.07:57:50.11#ibcon#about to read 6, iclass 22, count 2 2006.196.07:57:50.11#ibcon#read 6, iclass 22, count 2 2006.196.07:57:50.11#ibcon#end of sib2, iclass 22, count 2 2006.196.07:57:50.11#ibcon#*after write, iclass 22, count 2 2006.196.07:57:50.11#ibcon#*before return 0, iclass 22, count 2 2006.196.07:57:50.11#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.196.07:57:50.11#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.196.07:57:50.11#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.196.07:57:50.11#ibcon#ireg 7 cls_cnt 0 2006.196.07:57:50.11#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.196.07:57:50.23#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.196.07:57:50.23#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.196.07:57:50.23#ibcon#enter wrdev, iclass 22, count 0 2006.196.07:57:50.23#ibcon#first serial, iclass 22, count 0 2006.196.07:57:50.23#ibcon#enter sib2, iclass 22, count 0 2006.196.07:57:50.23#ibcon#flushed, iclass 22, count 0 2006.196.07:57:50.23#ibcon#about to write, iclass 22, count 0 2006.196.07:57:50.23#ibcon#wrote, iclass 22, count 0 2006.196.07:57:50.23#ibcon#about to read 3, iclass 22, count 0 2006.196.07:57:50.25#ibcon#read 3, iclass 22, count 0 2006.196.07:57:50.25#ibcon#about to read 4, iclass 22, count 0 2006.196.07:57:50.25#ibcon#read 4, iclass 22, count 0 2006.196.07:57:50.25#ibcon#about to read 5, iclass 22, count 0 2006.196.07:57:50.25#ibcon#read 5, iclass 22, count 0 2006.196.07:57:50.25#ibcon#about to read 6, iclass 22, count 0 2006.196.07:57:50.25#ibcon#read 6, iclass 22, count 0 2006.196.07:57:50.25#ibcon#end of sib2, iclass 22, count 0 2006.196.07:57:50.25#ibcon#*mode == 0, iclass 22, count 0 2006.196.07:57:50.25#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.196.07:57:50.25#ibcon#[25=USB\r\n] 2006.196.07:57:50.25#ibcon#*before write, iclass 22, count 0 2006.196.07:57:50.25#ibcon#enter sib2, iclass 22, count 0 2006.196.07:57:50.25#ibcon#flushed, iclass 22, count 0 2006.196.07:57:50.25#ibcon#about to write, iclass 22, count 0 2006.196.07:57:50.25#ibcon#wrote, iclass 22, count 0 2006.196.07:57:50.25#ibcon#about to read 3, iclass 22, count 0 2006.196.07:57:50.28#ibcon#read 3, iclass 22, count 0 2006.196.07:57:50.28#ibcon#about to read 4, iclass 22, count 0 2006.196.07:57:50.28#ibcon#read 4, iclass 22, count 0 2006.196.07:57:50.28#ibcon#about to read 5, iclass 22, count 0 2006.196.07:57:50.28#ibcon#read 5, iclass 22, count 0 2006.196.07:57:50.28#ibcon#about to read 6, iclass 22, count 0 2006.196.07:57:50.28#ibcon#read 6, iclass 22, count 0 2006.196.07:57:50.28#ibcon#end of sib2, iclass 22, count 0 2006.196.07:57:50.28#ibcon#*after write, iclass 22, count 0 2006.196.07:57:50.28#ibcon#*before return 0, iclass 22, count 0 2006.196.07:57:50.28#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.196.07:57:50.28#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.196.07:57:50.28#ibcon#about to clear, iclass 22 cls_cnt 0 2006.196.07:57:50.28#ibcon#cleared, iclass 22 cls_cnt 0 2006.196.07:57:50.28$vc4f8/valo=8,852.99 2006.196.07:57:50.28#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.196.07:57:50.28#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.196.07:57:50.28#ibcon#ireg 17 cls_cnt 0 2006.196.07:57:50.28#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.196.07:57:50.28#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.196.07:57:50.28#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.196.07:57:50.28#ibcon#enter wrdev, iclass 24, count 0 2006.196.07:57:50.28#ibcon#first serial, iclass 24, count 0 2006.196.07:57:50.28#ibcon#enter sib2, iclass 24, count 0 2006.196.07:57:50.28#ibcon#flushed, iclass 24, count 0 2006.196.07:57:50.28#ibcon#about to write, iclass 24, count 0 2006.196.07:57:50.28#ibcon#wrote, iclass 24, count 0 2006.196.07:57:50.28#ibcon#about to read 3, iclass 24, count 0 2006.196.07:57:50.30#ibcon#read 3, iclass 24, count 0 2006.196.07:57:50.30#ibcon#about to read 4, iclass 24, count 0 2006.196.07:57:50.30#ibcon#read 4, iclass 24, count 0 2006.196.07:57:50.30#ibcon#about to read 5, iclass 24, count 0 2006.196.07:57:50.30#ibcon#read 5, iclass 24, count 0 2006.196.07:57:50.30#ibcon#about to read 6, iclass 24, count 0 2006.196.07:57:50.30#ibcon#read 6, iclass 24, count 0 2006.196.07:57:50.30#ibcon#end of sib2, iclass 24, count 0 2006.196.07:57:50.30#ibcon#*mode == 0, iclass 24, count 0 2006.196.07:57:50.30#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.196.07:57:50.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.196.07:57:50.30#ibcon#*before write, iclass 24, count 0 2006.196.07:57:50.30#ibcon#enter sib2, iclass 24, count 0 2006.196.07:57:50.30#ibcon#flushed, iclass 24, count 0 2006.196.07:57:50.30#ibcon#about to write, iclass 24, count 0 2006.196.07:57:50.30#ibcon#wrote, iclass 24, count 0 2006.196.07:57:50.30#ibcon#about to read 3, iclass 24, count 0 2006.196.07:57:50.35#ibcon#read 3, iclass 24, count 0 2006.196.07:57:50.35#ibcon#about to read 4, iclass 24, count 0 2006.196.07:57:50.35#ibcon#read 4, iclass 24, count 0 2006.196.07:57:50.35#ibcon#about to read 5, iclass 24, count 0 2006.196.07:57:50.35#ibcon#read 5, iclass 24, count 0 2006.196.07:57:50.35#ibcon#about to read 6, iclass 24, count 0 2006.196.07:57:50.35#ibcon#read 6, iclass 24, count 0 2006.196.07:57:50.35#ibcon#end of sib2, iclass 24, count 0 2006.196.07:57:50.35#ibcon#*after write, iclass 24, count 0 2006.196.07:57:50.35#ibcon#*before return 0, iclass 24, count 0 2006.196.07:57:50.35#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.196.07:57:50.35#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.196.07:57:50.35#ibcon#about to clear, iclass 24 cls_cnt 0 2006.196.07:57:50.35#ibcon#cleared, iclass 24 cls_cnt 0 2006.196.07:57:50.35$vc4f8/va=8,7 2006.196.07:57:50.35#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.196.07:57:50.35#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.196.07:57:50.35#ibcon#ireg 11 cls_cnt 2 2006.196.07:57:50.35#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.196.07:57:50.40#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.196.07:57:50.40#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.196.07:57:50.40#ibcon#enter wrdev, iclass 26, count 2 2006.196.07:57:50.40#ibcon#first serial, iclass 26, count 2 2006.196.07:57:50.40#ibcon#enter sib2, iclass 26, count 2 2006.196.07:57:50.40#ibcon#flushed, iclass 26, count 2 2006.196.07:57:50.40#ibcon#about to write, iclass 26, count 2 2006.196.07:57:50.40#ibcon#wrote, iclass 26, count 2 2006.196.07:57:50.40#ibcon#about to read 3, iclass 26, count 2 2006.196.07:57:50.42#ibcon#read 3, iclass 26, count 2 2006.196.07:57:50.42#ibcon#about to read 4, iclass 26, count 2 2006.196.07:57:50.42#ibcon#read 4, iclass 26, count 2 2006.196.07:57:50.42#ibcon#about to read 5, iclass 26, count 2 2006.196.07:57:50.42#ibcon#read 5, iclass 26, count 2 2006.196.07:57:50.42#ibcon#about to read 6, iclass 26, count 2 2006.196.07:57:50.42#ibcon#read 6, iclass 26, count 2 2006.196.07:57:50.42#ibcon#end of sib2, iclass 26, count 2 2006.196.07:57:50.42#ibcon#*mode == 0, iclass 26, count 2 2006.196.07:57:50.42#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.196.07:57:50.42#ibcon#[25=AT08-07\r\n] 2006.196.07:57:50.42#ibcon#*before write, iclass 26, count 2 2006.196.07:57:50.42#ibcon#enter sib2, iclass 26, count 2 2006.196.07:57:50.42#ibcon#flushed, iclass 26, count 2 2006.196.07:57:50.42#ibcon#about to write, iclass 26, count 2 2006.196.07:57:50.42#ibcon#wrote, iclass 26, count 2 2006.196.07:57:50.42#ibcon#about to read 3, iclass 26, count 2 2006.196.07:57:50.45#ibcon#read 3, iclass 26, count 2 2006.196.07:57:50.45#ibcon#about to read 4, iclass 26, count 2 2006.196.07:57:50.45#ibcon#read 4, iclass 26, count 2 2006.196.07:57:50.45#ibcon#about to read 5, iclass 26, count 2 2006.196.07:57:50.45#ibcon#read 5, iclass 26, count 2 2006.196.07:57:50.45#ibcon#about to read 6, iclass 26, count 2 2006.196.07:57:50.45#ibcon#read 6, iclass 26, count 2 2006.196.07:57:50.45#ibcon#end of sib2, iclass 26, count 2 2006.196.07:57:50.45#ibcon#*after write, iclass 26, count 2 2006.196.07:57:50.45#ibcon#*before return 0, iclass 26, count 2 2006.196.07:57:50.45#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.196.07:57:50.45#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.196.07:57:50.45#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.196.07:57:50.45#ibcon#ireg 7 cls_cnt 0 2006.196.07:57:50.45#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.196.07:57:50.57#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.196.07:57:50.57#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.196.07:57:50.57#ibcon#enter wrdev, iclass 26, count 0 2006.196.07:57:50.57#ibcon#first serial, iclass 26, count 0 2006.196.07:57:50.57#ibcon#enter sib2, iclass 26, count 0 2006.196.07:57:50.57#ibcon#flushed, iclass 26, count 0 2006.196.07:57:50.57#ibcon#about to write, iclass 26, count 0 2006.196.07:57:50.57#ibcon#wrote, iclass 26, count 0 2006.196.07:57:50.57#ibcon#about to read 3, iclass 26, count 0 2006.196.07:57:50.59#ibcon#read 3, iclass 26, count 0 2006.196.07:57:50.59#ibcon#about to read 4, iclass 26, count 0 2006.196.07:57:50.59#ibcon#read 4, iclass 26, count 0 2006.196.07:57:50.59#ibcon#about to read 5, iclass 26, count 0 2006.196.07:57:50.59#ibcon#read 5, iclass 26, count 0 2006.196.07:57:50.59#ibcon#about to read 6, iclass 26, count 0 2006.196.07:57:50.59#ibcon#read 6, iclass 26, count 0 2006.196.07:57:50.59#ibcon#end of sib2, iclass 26, count 0 2006.196.07:57:50.59#ibcon#*mode == 0, iclass 26, count 0 2006.196.07:57:50.59#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.196.07:57:50.59#ibcon#[25=USB\r\n] 2006.196.07:57:50.59#ibcon#*before write, iclass 26, count 0 2006.196.07:57:50.59#ibcon#enter sib2, iclass 26, count 0 2006.196.07:57:50.59#ibcon#flushed, iclass 26, count 0 2006.196.07:57:50.59#ibcon#about to write, iclass 26, count 0 2006.196.07:57:50.59#ibcon#wrote, iclass 26, count 0 2006.196.07:57:50.59#ibcon#about to read 3, iclass 26, count 0 2006.196.07:57:50.62#ibcon#read 3, iclass 26, count 0 2006.196.07:57:50.62#ibcon#about to read 4, iclass 26, count 0 2006.196.07:57:50.62#ibcon#read 4, iclass 26, count 0 2006.196.07:57:50.62#ibcon#about to read 5, iclass 26, count 0 2006.196.07:57:50.62#ibcon#read 5, iclass 26, count 0 2006.196.07:57:50.62#ibcon#about to read 6, iclass 26, count 0 2006.196.07:57:50.62#ibcon#read 6, iclass 26, count 0 2006.196.07:57:50.62#ibcon#end of sib2, iclass 26, count 0 2006.196.07:57:50.62#ibcon#*after write, iclass 26, count 0 2006.196.07:57:50.62#ibcon#*before return 0, iclass 26, count 0 2006.196.07:57:50.62#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.196.07:57:50.62#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.196.07:57:50.62#ibcon#about to clear, iclass 26 cls_cnt 0 2006.196.07:57:50.62#ibcon#cleared, iclass 26 cls_cnt 0 2006.196.07:57:50.62$vc4f8/vblo=1,632.99 2006.196.07:57:50.62#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.196.07:57:50.62#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.196.07:57:50.62#ibcon#ireg 17 cls_cnt 0 2006.196.07:57:50.62#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.196.07:57:50.62#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.196.07:57:50.62#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.196.07:57:50.62#ibcon#enter wrdev, iclass 28, count 0 2006.196.07:57:50.62#ibcon#first serial, iclass 28, count 0 2006.196.07:57:50.62#ibcon#enter sib2, iclass 28, count 0 2006.196.07:57:50.62#ibcon#flushed, iclass 28, count 0 2006.196.07:57:50.62#ibcon#about to write, iclass 28, count 0 2006.196.07:57:50.62#ibcon#wrote, iclass 28, count 0 2006.196.07:57:50.62#ibcon#about to read 3, iclass 28, count 0 2006.196.07:57:50.64#ibcon#read 3, iclass 28, count 0 2006.196.07:57:50.64#ibcon#about to read 4, iclass 28, count 0 2006.196.07:57:50.64#ibcon#read 4, iclass 28, count 0 2006.196.07:57:50.64#ibcon#about to read 5, iclass 28, count 0 2006.196.07:57:50.64#ibcon#read 5, iclass 28, count 0 2006.196.07:57:50.64#ibcon#about to read 6, iclass 28, count 0 2006.196.07:57:50.64#ibcon#read 6, iclass 28, count 0 2006.196.07:57:50.64#ibcon#end of sib2, iclass 28, count 0 2006.196.07:57:50.64#ibcon#*mode == 0, iclass 28, count 0 2006.196.07:57:50.64#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.196.07:57:50.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.196.07:57:50.64#ibcon#*before write, iclass 28, count 0 2006.196.07:57:50.64#ibcon#enter sib2, iclass 28, count 0 2006.196.07:57:50.64#ibcon#flushed, iclass 28, count 0 2006.196.07:57:50.64#ibcon#about to write, iclass 28, count 0 2006.196.07:57:50.64#ibcon#wrote, iclass 28, count 0 2006.196.07:57:50.64#ibcon#about to read 3, iclass 28, count 0 2006.196.07:57:50.68#ibcon#read 3, iclass 28, count 0 2006.196.07:57:50.68#ibcon#about to read 4, iclass 28, count 0 2006.196.07:57:50.68#ibcon#read 4, iclass 28, count 0 2006.196.07:57:50.68#ibcon#about to read 5, iclass 28, count 0 2006.196.07:57:50.68#ibcon#read 5, iclass 28, count 0 2006.196.07:57:50.68#ibcon#about to read 6, iclass 28, count 0 2006.196.07:57:50.68#ibcon#read 6, iclass 28, count 0 2006.196.07:57:50.68#ibcon#end of sib2, iclass 28, count 0 2006.196.07:57:50.68#ibcon#*after write, iclass 28, count 0 2006.196.07:57:50.68#ibcon#*before return 0, iclass 28, count 0 2006.196.07:57:50.68#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.196.07:57:50.68#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.196.07:57:50.68#ibcon#about to clear, iclass 28 cls_cnt 0 2006.196.07:57:50.68#ibcon#cleared, iclass 28 cls_cnt 0 2006.196.07:57:50.68$vc4f8/vb=1,4 2006.196.07:57:50.68#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.196.07:57:50.68#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.196.07:57:50.68#ibcon#ireg 11 cls_cnt 2 2006.196.07:57:50.68#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.196.07:57:50.68#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.196.07:57:50.68#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.196.07:57:50.68#ibcon#enter wrdev, iclass 30, count 2 2006.196.07:57:50.68#ibcon#first serial, iclass 30, count 2 2006.196.07:57:50.68#ibcon#enter sib2, iclass 30, count 2 2006.196.07:57:50.68#ibcon#flushed, iclass 30, count 2 2006.196.07:57:50.68#ibcon#about to write, iclass 30, count 2 2006.196.07:57:50.68#ibcon#wrote, iclass 30, count 2 2006.196.07:57:50.68#ibcon#about to read 3, iclass 30, count 2 2006.196.07:57:50.70#ibcon#read 3, iclass 30, count 2 2006.196.07:57:50.70#ibcon#about to read 4, iclass 30, count 2 2006.196.07:57:50.70#ibcon#read 4, iclass 30, count 2 2006.196.07:57:50.70#ibcon#about to read 5, iclass 30, count 2 2006.196.07:57:50.70#ibcon#read 5, iclass 30, count 2 2006.196.07:57:50.70#ibcon#about to read 6, iclass 30, count 2 2006.196.07:57:50.70#ibcon#read 6, iclass 30, count 2 2006.196.07:57:50.70#ibcon#end of sib2, iclass 30, count 2 2006.196.07:57:50.70#ibcon#*mode == 0, iclass 30, count 2 2006.196.07:57:50.70#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.196.07:57:50.70#ibcon#[27=AT01-04\r\n] 2006.196.07:57:50.70#ibcon#*before write, iclass 30, count 2 2006.196.07:57:50.70#ibcon#enter sib2, iclass 30, count 2 2006.196.07:57:50.70#ibcon#flushed, iclass 30, count 2 2006.196.07:57:50.70#ibcon#about to write, iclass 30, count 2 2006.196.07:57:50.70#ibcon#wrote, iclass 30, count 2 2006.196.07:57:50.70#ibcon#about to read 3, iclass 30, count 2 2006.196.07:57:50.73#ibcon#read 3, iclass 30, count 2 2006.196.07:57:50.73#ibcon#about to read 4, iclass 30, count 2 2006.196.07:57:50.73#ibcon#read 4, iclass 30, count 2 2006.196.07:57:50.73#ibcon#about to read 5, iclass 30, count 2 2006.196.07:57:50.73#ibcon#read 5, iclass 30, count 2 2006.196.07:57:50.73#ibcon#about to read 6, iclass 30, count 2 2006.196.07:57:50.73#ibcon#read 6, iclass 30, count 2 2006.196.07:57:50.73#ibcon#end of sib2, iclass 30, count 2 2006.196.07:57:50.73#ibcon#*after write, iclass 30, count 2 2006.196.07:57:50.73#ibcon#*before return 0, iclass 30, count 2 2006.196.07:57:50.73#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.196.07:57:50.73#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.196.07:57:50.73#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.196.07:57:50.73#ibcon#ireg 7 cls_cnt 0 2006.196.07:57:50.73#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.196.07:57:50.85#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.196.07:57:50.85#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.196.07:57:50.85#ibcon#enter wrdev, iclass 30, count 0 2006.196.07:57:50.85#ibcon#first serial, iclass 30, count 0 2006.196.07:57:50.85#ibcon#enter sib2, iclass 30, count 0 2006.196.07:57:50.85#ibcon#flushed, iclass 30, count 0 2006.196.07:57:50.85#ibcon#about to write, iclass 30, count 0 2006.196.07:57:50.85#ibcon#wrote, iclass 30, count 0 2006.196.07:57:50.85#ibcon#about to read 3, iclass 30, count 0 2006.196.07:57:50.87#ibcon#read 3, iclass 30, count 0 2006.196.07:57:50.87#ibcon#about to read 4, iclass 30, count 0 2006.196.07:57:50.87#ibcon#read 4, iclass 30, count 0 2006.196.07:57:50.87#ibcon#about to read 5, iclass 30, count 0 2006.196.07:57:50.87#ibcon#read 5, iclass 30, count 0 2006.196.07:57:50.87#ibcon#about to read 6, iclass 30, count 0 2006.196.07:57:50.87#ibcon#read 6, iclass 30, count 0 2006.196.07:57:50.87#ibcon#end of sib2, iclass 30, count 0 2006.196.07:57:50.87#ibcon#*mode == 0, iclass 30, count 0 2006.196.07:57:50.87#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.196.07:57:50.87#ibcon#[27=USB\r\n] 2006.196.07:57:50.87#ibcon#*before write, iclass 30, count 0 2006.196.07:57:50.87#ibcon#enter sib2, iclass 30, count 0 2006.196.07:57:50.87#ibcon#flushed, iclass 30, count 0 2006.196.07:57:50.87#ibcon#about to write, iclass 30, count 0 2006.196.07:57:50.87#ibcon#wrote, iclass 30, count 0 2006.196.07:57:50.87#ibcon#about to read 3, iclass 30, count 0 2006.196.07:57:50.90#ibcon#read 3, iclass 30, count 0 2006.196.07:57:50.90#ibcon#about to read 4, iclass 30, count 0 2006.196.07:57:50.90#ibcon#read 4, iclass 30, count 0 2006.196.07:57:50.90#ibcon#about to read 5, iclass 30, count 0 2006.196.07:57:50.90#ibcon#read 5, iclass 30, count 0 2006.196.07:57:50.90#ibcon#about to read 6, iclass 30, count 0 2006.196.07:57:50.90#ibcon#read 6, iclass 30, count 0 2006.196.07:57:50.90#ibcon#end of sib2, iclass 30, count 0 2006.196.07:57:50.90#ibcon#*after write, iclass 30, count 0 2006.196.07:57:50.90#ibcon#*before return 0, iclass 30, count 0 2006.196.07:57:50.90#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.196.07:57:50.90#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.196.07:57:50.90#ibcon#about to clear, iclass 30 cls_cnt 0 2006.196.07:57:50.90#ibcon#cleared, iclass 30 cls_cnt 0 2006.196.07:57:50.90$vc4f8/vblo=2,640.99 2006.196.07:57:50.90#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.196.07:57:50.90#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.196.07:57:50.90#ibcon#ireg 17 cls_cnt 0 2006.196.07:57:50.90#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.196.07:57:50.90#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.196.07:57:50.90#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.196.07:57:50.90#ibcon#enter wrdev, iclass 32, count 0 2006.196.07:57:50.90#ibcon#first serial, iclass 32, count 0 2006.196.07:57:50.90#ibcon#enter sib2, iclass 32, count 0 2006.196.07:57:50.90#ibcon#flushed, iclass 32, count 0 2006.196.07:57:50.90#ibcon#about to write, iclass 32, count 0 2006.196.07:57:50.90#ibcon#wrote, iclass 32, count 0 2006.196.07:57:50.90#ibcon#about to read 3, iclass 32, count 0 2006.196.07:57:50.92#ibcon#read 3, iclass 32, count 0 2006.196.07:57:50.92#ibcon#about to read 4, iclass 32, count 0 2006.196.07:57:50.92#ibcon#read 4, iclass 32, count 0 2006.196.07:57:50.92#ibcon#about to read 5, iclass 32, count 0 2006.196.07:57:50.92#ibcon#read 5, iclass 32, count 0 2006.196.07:57:50.92#ibcon#about to read 6, iclass 32, count 0 2006.196.07:57:50.92#ibcon#read 6, iclass 32, count 0 2006.196.07:57:50.92#ibcon#end of sib2, iclass 32, count 0 2006.196.07:57:50.92#ibcon#*mode == 0, iclass 32, count 0 2006.196.07:57:50.92#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.196.07:57:50.92#ibcon#[28=FRQ=02,640.99\r\n] 2006.196.07:57:50.92#ibcon#*before write, iclass 32, count 0 2006.196.07:57:50.92#ibcon#enter sib2, iclass 32, count 0 2006.196.07:57:50.92#ibcon#flushed, iclass 32, count 0 2006.196.07:57:50.92#ibcon#about to write, iclass 32, count 0 2006.196.07:57:50.92#ibcon#wrote, iclass 32, count 0 2006.196.07:57:50.92#ibcon#about to read 3, iclass 32, count 0 2006.196.07:57:50.97#ibcon#read 3, iclass 32, count 0 2006.196.07:57:50.97#ibcon#about to read 4, iclass 32, count 0 2006.196.07:57:50.97#ibcon#read 4, iclass 32, count 0 2006.196.07:57:50.97#ibcon#about to read 5, iclass 32, count 0 2006.196.07:57:50.97#ibcon#read 5, iclass 32, count 0 2006.196.07:57:50.97#ibcon#about to read 6, iclass 32, count 0 2006.196.07:57:50.97#ibcon#read 6, iclass 32, count 0 2006.196.07:57:50.97#ibcon#end of sib2, iclass 32, count 0 2006.196.07:57:50.97#ibcon#*after write, iclass 32, count 0 2006.196.07:57:50.97#ibcon#*before return 0, iclass 32, count 0 2006.196.07:57:50.97#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.196.07:57:50.97#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.196.07:57:50.97#ibcon#about to clear, iclass 32 cls_cnt 0 2006.196.07:57:50.97#ibcon#cleared, iclass 32 cls_cnt 0 2006.196.07:57:50.97$vc4f8/vb=2,4 2006.196.07:57:50.97#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.196.07:57:50.97#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.196.07:57:50.97#ibcon#ireg 11 cls_cnt 2 2006.196.07:57:50.97#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.196.07:57:51.02#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.196.07:57:51.02#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.196.07:57:51.02#ibcon#enter wrdev, iclass 34, count 2 2006.196.07:57:51.02#ibcon#first serial, iclass 34, count 2 2006.196.07:57:51.02#ibcon#enter sib2, iclass 34, count 2 2006.196.07:57:51.02#ibcon#flushed, iclass 34, count 2 2006.196.07:57:51.02#ibcon#about to write, iclass 34, count 2 2006.196.07:57:51.02#ibcon#wrote, iclass 34, count 2 2006.196.07:57:51.02#ibcon#about to read 3, iclass 34, count 2 2006.196.07:57:51.04#ibcon#read 3, iclass 34, count 2 2006.196.07:57:51.04#ibcon#about to read 4, iclass 34, count 2 2006.196.07:57:51.04#ibcon#read 4, iclass 34, count 2 2006.196.07:57:51.04#ibcon#about to read 5, iclass 34, count 2 2006.196.07:57:51.04#ibcon#read 5, iclass 34, count 2 2006.196.07:57:51.04#ibcon#about to read 6, iclass 34, count 2 2006.196.07:57:51.04#ibcon#read 6, iclass 34, count 2 2006.196.07:57:51.04#ibcon#end of sib2, iclass 34, count 2 2006.196.07:57:51.04#ibcon#*mode == 0, iclass 34, count 2 2006.196.07:57:51.04#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.196.07:57:51.04#ibcon#[27=AT02-04\r\n] 2006.196.07:57:51.04#ibcon#*before write, iclass 34, count 2 2006.196.07:57:51.04#ibcon#enter sib2, iclass 34, count 2 2006.196.07:57:51.04#ibcon#flushed, iclass 34, count 2 2006.196.07:57:51.04#ibcon#about to write, iclass 34, count 2 2006.196.07:57:51.04#ibcon#wrote, iclass 34, count 2 2006.196.07:57:51.04#ibcon#about to read 3, iclass 34, count 2 2006.196.07:57:51.07#ibcon#read 3, iclass 34, count 2 2006.196.07:57:51.07#ibcon#about to read 4, iclass 34, count 2 2006.196.07:57:51.07#ibcon#read 4, iclass 34, count 2 2006.196.07:57:51.07#ibcon#about to read 5, iclass 34, count 2 2006.196.07:57:51.07#ibcon#read 5, iclass 34, count 2 2006.196.07:57:51.07#ibcon#about to read 6, iclass 34, count 2 2006.196.07:57:51.07#ibcon#read 6, iclass 34, count 2 2006.196.07:57:51.07#ibcon#end of sib2, iclass 34, count 2 2006.196.07:57:51.07#ibcon#*after write, iclass 34, count 2 2006.196.07:57:51.07#ibcon#*before return 0, iclass 34, count 2 2006.196.07:57:51.07#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.196.07:57:51.07#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.196.07:57:51.07#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.196.07:57:51.07#ibcon#ireg 7 cls_cnt 0 2006.196.07:57:51.07#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.196.07:57:51.19#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.196.07:57:51.19#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.196.07:57:51.19#ibcon#enter wrdev, iclass 34, count 0 2006.196.07:57:51.19#ibcon#first serial, iclass 34, count 0 2006.196.07:57:51.19#ibcon#enter sib2, iclass 34, count 0 2006.196.07:57:51.19#ibcon#flushed, iclass 34, count 0 2006.196.07:57:51.19#ibcon#about to write, iclass 34, count 0 2006.196.07:57:51.19#ibcon#wrote, iclass 34, count 0 2006.196.07:57:51.19#ibcon#about to read 3, iclass 34, count 0 2006.196.07:57:51.21#ibcon#read 3, iclass 34, count 0 2006.196.07:57:51.21#ibcon#about to read 4, iclass 34, count 0 2006.196.07:57:51.21#ibcon#read 4, iclass 34, count 0 2006.196.07:57:51.21#ibcon#about to read 5, iclass 34, count 0 2006.196.07:57:51.21#ibcon#read 5, iclass 34, count 0 2006.196.07:57:51.21#ibcon#about to read 6, iclass 34, count 0 2006.196.07:57:51.21#ibcon#read 6, iclass 34, count 0 2006.196.07:57:51.21#ibcon#end of sib2, iclass 34, count 0 2006.196.07:57:51.21#ibcon#*mode == 0, iclass 34, count 0 2006.196.07:57:51.21#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.196.07:57:51.21#ibcon#[27=USB\r\n] 2006.196.07:57:51.21#ibcon#*before write, iclass 34, count 0 2006.196.07:57:51.21#ibcon#enter sib2, iclass 34, count 0 2006.196.07:57:51.21#ibcon#flushed, iclass 34, count 0 2006.196.07:57:51.21#ibcon#about to write, iclass 34, count 0 2006.196.07:57:51.21#ibcon#wrote, iclass 34, count 0 2006.196.07:57:51.21#ibcon#about to read 3, iclass 34, count 0 2006.196.07:57:51.24#ibcon#read 3, iclass 34, count 0 2006.196.07:57:51.24#ibcon#about to read 4, iclass 34, count 0 2006.196.07:57:51.24#ibcon#read 4, iclass 34, count 0 2006.196.07:57:51.24#ibcon#about to read 5, iclass 34, count 0 2006.196.07:57:51.24#ibcon#read 5, iclass 34, count 0 2006.196.07:57:51.24#ibcon#about to read 6, iclass 34, count 0 2006.196.07:57:51.24#ibcon#read 6, iclass 34, count 0 2006.196.07:57:51.24#ibcon#end of sib2, iclass 34, count 0 2006.196.07:57:51.24#ibcon#*after write, iclass 34, count 0 2006.196.07:57:51.24#ibcon#*before return 0, iclass 34, count 0 2006.196.07:57:51.24#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.196.07:57:51.24#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.196.07:57:51.24#ibcon#about to clear, iclass 34 cls_cnt 0 2006.196.07:57:51.24#ibcon#cleared, iclass 34 cls_cnt 0 2006.196.07:57:51.24$vc4f8/vblo=3,656.99 2006.196.07:57:51.24#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.196.07:57:51.24#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.196.07:57:51.24#ibcon#ireg 17 cls_cnt 0 2006.196.07:57:51.24#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.196.07:57:51.24#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.196.07:57:51.24#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.196.07:57:51.24#ibcon#enter wrdev, iclass 36, count 0 2006.196.07:57:51.24#ibcon#first serial, iclass 36, count 0 2006.196.07:57:51.24#ibcon#enter sib2, iclass 36, count 0 2006.196.07:57:51.24#ibcon#flushed, iclass 36, count 0 2006.196.07:57:51.24#ibcon#about to write, iclass 36, count 0 2006.196.07:57:51.24#ibcon#wrote, iclass 36, count 0 2006.196.07:57:51.24#ibcon#about to read 3, iclass 36, count 0 2006.196.07:57:51.26#ibcon#read 3, iclass 36, count 0 2006.196.07:57:51.26#ibcon#about to read 4, iclass 36, count 0 2006.196.07:57:51.26#ibcon#read 4, iclass 36, count 0 2006.196.07:57:51.26#ibcon#about to read 5, iclass 36, count 0 2006.196.07:57:51.26#ibcon#read 5, iclass 36, count 0 2006.196.07:57:51.26#ibcon#about to read 6, iclass 36, count 0 2006.196.07:57:51.26#ibcon#read 6, iclass 36, count 0 2006.196.07:57:51.26#ibcon#end of sib2, iclass 36, count 0 2006.196.07:57:51.26#ibcon#*mode == 0, iclass 36, count 0 2006.196.07:57:51.26#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.196.07:57:51.26#ibcon#[28=FRQ=03,656.99\r\n] 2006.196.07:57:51.26#ibcon#*before write, iclass 36, count 0 2006.196.07:57:51.26#ibcon#enter sib2, iclass 36, count 0 2006.196.07:57:51.26#ibcon#flushed, iclass 36, count 0 2006.196.07:57:51.26#ibcon#about to write, iclass 36, count 0 2006.196.07:57:51.26#ibcon#wrote, iclass 36, count 0 2006.196.07:57:51.26#ibcon#about to read 3, iclass 36, count 0 2006.196.07:57:51.30#ibcon#read 3, iclass 36, count 0 2006.196.07:57:51.30#ibcon#about to read 4, iclass 36, count 0 2006.196.07:57:51.30#ibcon#read 4, iclass 36, count 0 2006.196.07:57:51.30#ibcon#about to read 5, iclass 36, count 0 2006.196.07:57:51.30#ibcon#read 5, iclass 36, count 0 2006.196.07:57:51.30#ibcon#about to read 6, iclass 36, count 0 2006.196.07:57:51.30#ibcon#read 6, iclass 36, count 0 2006.196.07:57:51.30#ibcon#end of sib2, iclass 36, count 0 2006.196.07:57:51.30#ibcon#*after write, iclass 36, count 0 2006.196.07:57:51.30#ibcon#*before return 0, iclass 36, count 0 2006.196.07:57:51.30#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.196.07:57:51.30#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.196.07:57:51.30#ibcon#about to clear, iclass 36 cls_cnt 0 2006.196.07:57:51.30#ibcon#cleared, iclass 36 cls_cnt 0 2006.196.07:57:51.30$vc4f8/vb=3,4 2006.196.07:57:51.30#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.196.07:57:51.30#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.196.07:57:51.30#ibcon#ireg 11 cls_cnt 2 2006.196.07:57:51.30#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.196.07:57:51.36#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.196.07:57:51.36#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.196.07:57:51.36#ibcon#enter wrdev, iclass 38, count 2 2006.196.07:57:51.36#ibcon#first serial, iclass 38, count 2 2006.196.07:57:51.36#ibcon#enter sib2, iclass 38, count 2 2006.196.07:57:51.36#ibcon#flushed, iclass 38, count 2 2006.196.07:57:51.36#ibcon#about to write, iclass 38, count 2 2006.196.07:57:51.36#ibcon#wrote, iclass 38, count 2 2006.196.07:57:51.36#ibcon#about to read 3, iclass 38, count 2 2006.196.07:57:51.38#ibcon#read 3, iclass 38, count 2 2006.196.07:57:51.38#ibcon#about to read 4, iclass 38, count 2 2006.196.07:57:51.38#ibcon#read 4, iclass 38, count 2 2006.196.07:57:51.38#ibcon#about to read 5, iclass 38, count 2 2006.196.07:57:51.38#ibcon#read 5, iclass 38, count 2 2006.196.07:57:51.38#ibcon#about to read 6, iclass 38, count 2 2006.196.07:57:51.38#ibcon#read 6, iclass 38, count 2 2006.196.07:57:51.38#ibcon#end of sib2, iclass 38, count 2 2006.196.07:57:51.38#ibcon#*mode == 0, iclass 38, count 2 2006.196.07:57:51.38#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.196.07:57:51.38#ibcon#[27=AT03-04\r\n] 2006.196.07:57:51.38#ibcon#*before write, iclass 38, count 2 2006.196.07:57:51.38#ibcon#enter sib2, iclass 38, count 2 2006.196.07:57:51.38#ibcon#flushed, iclass 38, count 2 2006.196.07:57:51.38#ibcon#about to write, iclass 38, count 2 2006.196.07:57:51.38#ibcon#wrote, iclass 38, count 2 2006.196.07:57:51.38#ibcon#about to read 3, iclass 38, count 2 2006.196.07:57:51.41#ibcon#read 3, iclass 38, count 2 2006.196.07:57:51.41#ibcon#about to read 4, iclass 38, count 2 2006.196.07:57:51.41#ibcon#read 4, iclass 38, count 2 2006.196.07:57:51.41#ibcon#about to read 5, iclass 38, count 2 2006.196.07:57:51.41#ibcon#read 5, iclass 38, count 2 2006.196.07:57:51.41#ibcon#about to read 6, iclass 38, count 2 2006.196.07:57:51.41#ibcon#read 6, iclass 38, count 2 2006.196.07:57:51.41#ibcon#end of sib2, iclass 38, count 2 2006.196.07:57:51.41#ibcon#*after write, iclass 38, count 2 2006.196.07:57:51.41#ibcon#*before return 0, iclass 38, count 2 2006.196.07:57:51.41#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.196.07:57:51.41#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.196.07:57:51.41#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.196.07:57:51.41#ibcon#ireg 7 cls_cnt 0 2006.196.07:57:51.41#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.196.07:57:51.53#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.196.07:57:51.53#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.196.07:57:51.53#ibcon#enter wrdev, iclass 38, count 0 2006.196.07:57:51.53#ibcon#first serial, iclass 38, count 0 2006.196.07:57:51.53#ibcon#enter sib2, iclass 38, count 0 2006.196.07:57:51.53#ibcon#flushed, iclass 38, count 0 2006.196.07:57:51.53#ibcon#about to write, iclass 38, count 0 2006.196.07:57:51.53#ibcon#wrote, iclass 38, count 0 2006.196.07:57:51.53#ibcon#about to read 3, iclass 38, count 0 2006.196.07:57:51.55#ibcon#read 3, iclass 38, count 0 2006.196.07:57:51.55#ibcon#about to read 4, iclass 38, count 0 2006.196.07:57:51.55#ibcon#read 4, iclass 38, count 0 2006.196.07:57:51.55#ibcon#about to read 5, iclass 38, count 0 2006.196.07:57:51.55#ibcon#read 5, iclass 38, count 0 2006.196.07:57:51.55#ibcon#about to read 6, iclass 38, count 0 2006.196.07:57:51.55#ibcon#read 6, iclass 38, count 0 2006.196.07:57:51.55#ibcon#end of sib2, iclass 38, count 0 2006.196.07:57:51.55#ibcon#*mode == 0, iclass 38, count 0 2006.196.07:57:51.55#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.196.07:57:51.55#ibcon#[27=USB\r\n] 2006.196.07:57:51.55#ibcon#*before write, iclass 38, count 0 2006.196.07:57:51.55#ibcon#enter sib2, iclass 38, count 0 2006.196.07:57:51.55#ibcon#flushed, iclass 38, count 0 2006.196.07:57:51.55#ibcon#about to write, iclass 38, count 0 2006.196.07:57:51.55#ibcon#wrote, iclass 38, count 0 2006.196.07:57:51.55#ibcon#about to read 3, iclass 38, count 0 2006.196.07:57:51.58#ibcon#read 3, iclass 38, count 0 2006.196.07:57:51.58#ibcon#about to read 4, iclass 38, count 0 2006.196.07:57:51.58#ibcon#read 4, iclass 38, count 0 2006.196.07:57:51.58#ibcon#about to read 5, iclass 38, count 0 2006.196.07:57:51.58#ibcon#read 5, iclass 38, count 0 2006.196.07:57:51.58#ibcon#about to read 6, iclass 38, count 0 2006.196.07:57:51.58#ibcon#read 6, iclass 38, count 0 2006.196.07:57:51.58#ibcon#end of sib2, iclass 38, count 0 2006.196.07:57:51.58#ibcon#*after write, iclass 38, count 0 2006.196.07:57:51.58#ibcon#*before return 0, iclass 38, count 0 2006.196.07:57:51.58#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.196.07:57:51.58#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.196.07:57:51.58#ibcon#about to clear, iclass 38 cls_cnt 0 2006.196.07:57:51.58#ibcon#cleared, iclass 38 cls_cnt 0 2006.196.07:57:51.58$vc4f8/vblo=4,712.99 2006.196.07:57:51.58#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.196.07:57:51.58#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.196.07:57:51.58#ibcon#ireg 17 cls_cnt 0 2006.196.07:57:51.58#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.196.07:57:51.58#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.196.07:57:51.58#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.196.07:57:51.58#ibcon#enter wrdev, iclass 40, count 0 2006.196.07:57:51.58#ibcon#first serial, iclass 40, count 0 2006.196.07:57:51.58#ibcon#enter sib2, iclass 40, count 0 2006.196.07:57:51.58#ibcon#flushed, iclass 40, count 0 2006.196.07:57:51.58#ibcon#about to write, iclass 40, count 0 2006.196.07:57:51.58#ibcon#wrote, iclass 40, count 0 2006.196.07:57:51.58#ibcon#about to read 3, iclass 40, count 0 2006.196.07:57:51.60#ibcon#read 3, iclass 40, count 0 2006.196.07:57:51.60#ibcon#about to read 4, iclass 40, count 0 2006.196.07:57:51.60#ibcon#read 4, iclass 40, count 0 2006.196.07:57:51.60#ibcon#about to read 5, iclass 40, count 0 2006.196.07:57:51.60#ibcon#read 5, iclass 40, count 0 2006.196.07:57:51.60#ibcon#about to read 6, iclass 40, count 0 2006.196.07:57:51.60#ibcon#read 6, iclass 40, count 0 2006.196.07:57:51.60#ibcon#end of sib2, iclass 40, count 0 2006.196.07:57:51.60#ibcon#*mode == 0, iclass 40, count 0 2006.196.07:57:51.60#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.196.07:57:51.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.196.07:57:51.60#ibcon#*before write, iclass 40, count 0 2006.196.07:57:51.60#ibcon#enter sib2, iclass 40, count 0 2006.196.07:57:51.60#ibcon#flushed, iclass 40, count 0 2006.196.07:57:51.60#ibcon#about to write, iclass 40, count 0 2006.196.07:57:51.60#ibcon#wrote, iclass 40, count 0 2006.196.07:57:51.60#ibcon#about to read 3, iclass 40, count 0 2006.196.07:57:51.65#ibcon#read 3, iclass 40, count 0 2006.196.07:57:51.65#ibcon#about to read 4, iclass 40, count 0 2006.196.07:57:51.65#ibcon#read 4, iclass 40, count 0 2006.196.07:57:51.65#ibcon#about to read 5, iclass 40, count 0 2006.196.07:57:51.65#ibcon#read 5, iclass 40, count 0 2006.196.07:57:51.65#ibcon#about to read 6, iclass 40, count 0 2006.196.07:57:51.65#ibcon#read 6, iclass 40, count 0 2006.196.07:57:51.65#ibcon#end of sib2, iclass 40, count 0 2006.196.07:57:51.65#ibcon#*after write, iclass 40, count 0 2006.196.07:57:51.65#ibcon#*before return 0, iclass 40, count 0 2006.196.07:57:51.65#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.196.07:57:51.65#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.196.07:57:51.65#ibcon#about to clear, iclass 40 cls_cnt 0 2006.196.07:57:51.65#ibcon#cleared, iclass 40 cls_cnt 0 2006.196.07:57:51.65$vc4f8/vb=4,4 2006.196.07:57:51.65#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.196.07:57:51.65#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.196.07:57:51.65#ibcon#ireg 11 cls_cnt 2 2006.196.07:57:51.65#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.196.07:57:51.70#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.196.07:57:51.70#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.196.07:57:51.70#ibcon#enter wrdev, iclass 4, count 2 2006.196.07:57:51.70#ibcon#first serial, iclass 4, count 2 2006.196.07:57:51.70#ibcon#enter sib2, iclass 4, count 2 2006.196.07:57:51.70#ibcon#flushed, iclass 4, count 2 2006.196.07:57:51.70#ibcon#about to write, iclass 4, count 2 2006.196.07:57:51.70#ibcon#wrote, iclass 4, count 2 2006.196.07:57:51.70#ibcon#about to read 3, iclass 4, count 2 2006.196.07:57:51.72#ibcon#read 3, iclass 4, count 2 2006.196.07:57:51.72#ibcon#about to read 4, iclass 4, count 2 2006.196.07:57:51.72#ibcon#read 4, iclass 4, count 2 2006.196.07:57:51.72#ibcon#about to read 5, iclass 4, count 2 2006.196.07:57:51.72#ibcon#read 5, iclass 4, count 2 2006.196.07:57:51.72#ibcon#about to read 6, iclass 4, count 2 2006.196.07:57:51.72#ibcon#read 6, iclass 4, count 2 2006.196.07:57:51.72#ibcon#end of sib2, iclass 4, count 2 2006.196.07:57:51.72#ibcon#*mode == 0, iclass 4, count 2 2006.196.07:57:51.72#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.196.07:57:51.72#ibcon#[27=AT04-04\r\n] 2006.196.07:57:51.72#ibcon#*before write, iclass 4, count 2 2006.196.07:57:51.72#ibcon#enter sib2, iclass 4, count 2 2006.196.07:57:51.72#ibcon#flushed, iclass 4, count 2 2006.196.07:57:51.72#ibcon#about to write, iclass 4, count 2 2006.196.07:57:51.72#ibcon#wrote, iclass 4, count 2 2006.196.07:57:51.72#ibcon#about to read 3, iclass 4, count 2 2006.196.07:57:51.75#ibcon#read 3, iclass 4, count 2 2006.196.07:57:51.75#ibcon#about to read 4, iclass 4, count 2 2006.196.07:57:51.75#ibcon#read 4, iclass 4, count 2 2006.196.07:57:51.75#ibcon#about to read 5, iclass 4, count 2 2006.196.07:57:51.75#ibcon#read 5, iclass 4, count 2 2006.196.07:57:51.75#ibcon#about to read 6, iclass 4, count 2 2006.196.07:57:51.75#ibcon#read 6, iclass 4, count 2 2006.196.07:57:51.75#ibcon#end of sib2, iclass 4, count 2 2006.196.07:57:51.75#ibcon#*after write, iclass 4, count 2 2006.196.07:57:51.75#ibcon#*before return 0, iclass 4, count 2 2006.196.07:57:51.75#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.196.07:57:51.75#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.196.07:57:51.75#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.196.07:57:51.75#ibcon#ireg 7 cls_cnt 0 2006.196.07:57:51.75#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.196.07:57:51.87#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.196.07:57:51.87#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.196.07:57:51.87#ibcon#enter wrdev, iclass 4, count 0 2006.196.07:57:51.87#ibcon#first serial, iclass 4, count 0 2006.196.07:57:51.87#ibcon#enter sib2, iclass 4, count 0 2006.196.07:57:51.87#ibcon#flushed, iclass 4, count 0 2006.196.07:57:51.87#ibcon#about to write, iclass 4, count 0 2006.196.07:57:51.87#ibcon#wrote, iclass 4, count 0 2006.196.07:57:51.87#ibcon#about to read 3, iclass 4, count 0 2006.196.07:57:51.89#ibcon#read 3, iclass 4, count 0 2006.196.07:57:51.89#ibcon#about to read 4, iclass 4, count 0 2006.196.07:57:51.89#ibcon#read 4, iclass 4, count 0 2006.196.07:57:51.89#ibcon#about to read 5, iclass 4, count 0 2006.196.07:57:51.89#ibcon#read 5, iclass 4, count 0 2006.196.07:57:51.89#ibcon#about to read 6, iclass 4, count 0 2006.196.07:57:51.89#ibcon#read 6, iclass 4, count 0 2006.196.07:57:51.89#ibcon#end of sib2, iclass 4, count 0 2006.196.07:57:51.89#ibcon#*mode == 0, iclass 4, count 0 2006.196.07:57:51.89#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.196.07:57:51.89#ibcon#[27=USB\r\n] 2006.196.07:57:51.89#ibcon#*before write, iclass 4, count 0 2006.196.07:57:51.89#ibcon#enter sib2, iclass 4, count 0 2006.196.07:57:51.89#ibcon#flushed, iclass 4, count 0 2006.196.07:57:51.89#ibcon#about to write, iclass 4, count 0 2006.196.07:57:51.89#ibcon#wrote, iclass 4, count 0 2006.196.07:57:51.89#ibcon#about to read 3, iclass 4, count 0 2006.196.07:57:51.92#ibcon#read 3, iclass 4, count 0 2006.196.07:57:51.92#ibcon#about to read 4, iclass 4, count 0 2006.196.07:57:51.92#ibcon#read 4, iclass 4, count 0 2006.196.07:57:51.92#ibcon#about to read 5, iclass 4, count 0 2006.196.07:57:51.92#ibcon#read 5, iclass 4, count 0 2006.196.07:57:51.92#ibcon#about to read 6, iclass 4, count 0 2006.196.07:57:51.92#ibcon#read 6, iclass 4, count 0 2006.196.07:57:51.92#ibcon#end of sib2, iclass 4, count 0 2006.196.07:57:51.92#ibcon#*after write, iclass 4, count 0 2006.196.07:57:51.92#ibcon#*before return 0, iclass 4, count 0 2006.196.07:57:51.92#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.196.07:57:51.92#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.196.07:57:51.92#ibcon#about to clear, iclass 4 cls_cnt 0 2006.196.07:57:51.92#ibcon#cleared, iclass 4 cls_cnt 0 2006.196.07:57:51.92$vc4f8/vblo=5,744.99 2006.196.07:57:51.92#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.196.07:57:51.92#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.196.07:57:51.92#ibcon#ireg 17 cls_cnt 0 2006.196.07:57:51.92#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.196.07:57:51.92#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.196.07:57:51.92#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.196.07:57:51.92#ibcon#enter wrdev, iclass 6, count 0 2006.196.07:57:51.92#ibcon#first serial, iclass 6, count 0 2006.196.07:57:51.92#ibcon#enter sib2, iclass 6, count 0 2006.196.07:57:51.92#ibcon#flushed, iclass 6, count 0 2006.196.07:57:51.92#ibcon#about to write, iclass 6, count 0 2006.196.07:57:51.92#ibcon#wrote, iclass 6, count 0 2006.196.07:57:51.92#ibcon#about to read 3, iclass 6, count 0 2006.196.07:57:51.94#ibcon#read 3, iclass 6, count 0 2006.196.07:57:51.94#ibcon#about to read 4, iclass 6, count 0 2006.196.07:57:51.94#ibcon#read 4, iclass 6, count 0 2006.196.07:57:51.94#ibcon#about to read 5, iclass 6, count 0 2006.196.07:57:51.94#ibcon#read 5, iclass 6, count 0 2006.196.07:57:51.94#ibcon#about to read 6, iclass 6, count 0 2006.196.07:57:51.94#ibcon#read 6, iclass 6, count 0 2006.196.07:57:51.94#ibcon#end of sib2, iclass 6, count 0 2006.196.07:57:51.94#ibcon#*mode == 0, iclass 6, count 0 2006.196.07:57:51.94#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.196.07:57:51.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.196.07:57:51.94#ibcon#*before write, iclass 6, count 0 2006.196.07:57:51.94#ibcon#enter sib2, iclass 6, count 0 2006.196.07:57:51.94#ibcon#flushed, iclass 6, count 0 2006.196.07:57:51.94#ibcon#about to write, iclass 6, count 0 2006.196.07:57:51.94#ibcon#wrote, iclass 6, count 0 2006.196.07:57:51.94#ibcon#about to read 3, iclass 6, count 0 2006.196.07:57:51.98#ibcon#read 3, iclass 6, count 0 2006.196.07:57:51.98#ibcon#about to read 4, iclass 6, count 0 2006.196.07:57:51.98#ibcon#read 4, iclass 6, count 0 2006.196.07:57:51.98#ibcon#about to read 5, iclass 6, count 0 2006.196.07:57:51.98#ibcon#read 5, iclass 6, count 0 2006.196.07:57:51.98#ibcon#about to read 6, iclass 6, count 0 2006.196.07:57:51.98#ibcon#read 6, iclass 6, count 0 2006.196.07:57:51.98#ibcon#end of sib2, iclass 6, count 0 2006.196.07:57:51.98#ibcon#*after write, iclass 6, count 0 2006.196.07:57:51.98#ibcon#*before return 0, iclass 6, count 0 2006.196.07:57:51.98#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.196.07:57:51.98#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.196.07:57:51.98#ibcon#about to clear, iclass 6 cls_cnt 0 2006.196.07:57:51.98#ibcon#cleared, iclass 6 cls_cnt 0 2006.196.07:57:51.98$vc4f8/vb=5,4 2006.196.07:57:51.98#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.196.07:57:51.98#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.196.07:57:51.98#ibcon#ireg 11 cls_cnt 2 2006.196.07:57:51.98#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.196.07:57:52.04#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.196.07:57:52.04#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.196.07:57:52.04#ibcon#enter wrdev, iclass 10, count 2 2006.196.07:57:52.04#ibcon#first serial, iclass 10, count 2 2006.196.07:57:52.04#ibcon#enter sib2, iclass 10, count 2 2006.196.07:57:52.04#ibcon#flushed, iclass 10, count 2 2006.196.07:57:52.04#ibcon#about to write, iclass 10, count 2 2006.196.07:57:52.04#ibcon#wrote, iclass 10, count 2 2006.196.07:57:52.04#ibcon#about to read 3, iclass 10, count 2 2006.196.07:57:52.06#ibcon#read 3, iclass 10, count 2 2006.196.07:57:52.06#ibcon#about to read 4, iclass 10, count 2 2006.196.07:57:52.06#ibcon#read 4, iclass 10, count 2 2006.196.07:57:52.06#ibcon#about to read 5, iclass 10, count 2 2006.196.07:57:52.06#ibcon#read 5, iclass 10, count 2 2006.196.07:57:52.06#ibcon#about to read 6, iclass 10, count 2 2006.196.07:57:52.06#ibcon#read 6, iclass 10, count 2 2006.196.07:57:52.06#ibcon#end of sib2, iclass 10, count 2 2006.196.07:57:52.06#ibcon#*mode == 0, iclass 10, count 2 2006.196.07:57:52.06#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.196.07:57:52.06#ibcon#[27=AT05-04\r\n] 2006.196.07:57:52.06#ibcon#*before write, iclass 10, count 2 2006.196.07:57:52.06#ibcon#enter sib2, iclass 10, count 2 2006.196.07:57:52.06#ibcon#flushed, iclass 10, count 2 2006.196.07:57:52.06#ibcon#about to write, iclass 10, count 2 2006.196.07:57:52.06#ibcon#wrote, iclass 10, count 2 2006.196.07:57:52.06#ibcon#about to read 3, iclass 10, count 2 2006.196.07:57:52.09#ibcon#read 3, iclass 10, count 2 2006.196.07:57:52.09#ibcon#about to read 4, iclass 10, count 2 2006.196.07:57:52.09#ibcon#read 4, iclass 10, count 2 2006.196.07:57:52.09#ibcon#about to read 5, iclass 10, count 2 2006.196.07:57:52.09#ibcon#read 5, iclass 10, count 2 2006.196.07:57:52.09#ibcon#about to read 6, iclass 10, count 2 2006.196.07:57:52.09#ibcon#read 6, iclass 10, count 2 2006.196.07:57:52.09#ibcon#end of sib2, iclass 10, count 2 2006.196.07:57:52.09#ibcon#*after write, iclass 10, count 2 2006.196.07:57:52.09#ibcon#*before return 0, iclass 10, count 2 2006.196.07:57:52.09#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.196.07:57:52.09#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.196.07:57:52.09#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.196.07:57:52.09#ibcon#ireg 7 cls_cnt 0 2006.196.07:57:52.09#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.196.07:57:52.21#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.196.07:57:52.21#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.196.07:57:52.21#ibcon#enter wrdev, iclass 10, count 0 2006.196.07:57:52.21#ibcon#first serial, iclass 10, count 0 2006.196.07:57:52.21#ibcon#enter sib2, iclass 10, count 0 2006.196.07:57:52.21#ibcon#flushed, iclass 10, count 0 2006.196.07:57:52.21#ibcon#about to write, iclass 10, count 0 2006.196.07:57:52.21#ibcon#wrote, iclass 10, count 0 2006.196.07:57:52.21#ibcon#about to read 3, iclass 10, count 0 2006.196.07:57:52.23#ibcon#read 3, iclass 10, count 0 2006.196.07:57:52.23#ibcon#about to read 4, iclass 10, count 0 2006.196.07:57:52.23#ibcon#read 4, iclass 10, count 0 2006.196.07:57:52.23#ibcon#about to read 5, iclass 10, count 0 2006.196.07:57:52.23#ibcon#read 5, iclass 10, count 0 2006.196.07:57:52.23#ibcon#about to read 6, iclass 10, count 0 2006.196.07:57:52.23#ibcon#read 6, iclass 10, count 0 2006.196.07:57:52.23#ibcon#end of sib2, iclass 10, count 0 2006.196.07:57:52.23#ibcon#*mode == 0, iclass 10, count 0 2006.196.07:57:52.23#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.196.07:57:52.23#ibcon#[27=USB\r\n] 2006.196.07:57:52.23#ibcon#*before write, iclass 10, count 0 2006.196.07:57:52.23#ibcon#enter sib2, iclass 10, count 0 2006.196.07:57:52.23#ibcon#flushed, iclass 10, count 0 2006.196.07:57:52.23#ibcon#about to write, iclass 10, count 0 2006.196.07:57:52.23#ibcon#wrote, iclass 10, count 0 2006.196.07:57:52.23#ibcon#about to read 3, iclass 10, count 0 2006.196.07:57:52.26#ibcon#read 3, iclass 10, count 0 2006.196.07:57:52.26#ibcon#about to read 4, iclass 10, count 0 2006.196.07:57:52.26#ibcon#read 4, iclass 10, count 0 2006.196.07:57:52.26#ibcon#about to read 5, iclass 10, count 0 2006.196.07:57:52.26#ibcon#read 5, iclass 10, count 0 2006.196.07:57:52.26#ibcon#about to read 6, iclass 10, count 0 2006.196.07:57:52.26#ibcon#read 6, iclass 10, count 0 2006.196.07:57:52.26#ibcon#end of sib2, iclass 10, count 0 2006.196.07:57:52.26#ibcon#*after write, iclass 10, count 0 2006.196.07:57:52.26#ibcon#*before return 0, iclass 10, count 0 2006.196.07:57:52.26#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.196.07:57:52.26#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.196.07:57:52.26#ibcon#about to clear, iclass 10 cls_cnt 0 2006.196.07:57:52.26#ibcon#cleared, iclass 10 cls_cnt 0 2006.196.07:57:52.26$vc4f8/vblo=6,752.99 2006.196.07:57:52.26#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.196.07:57:52.26#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.196.07:57:52.26#ibcon#ireg 17 cls_cnt 0 2006.196.07:57:52.26#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.196.07:57:52.26#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.196.07:57:52.26#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.196.07:57:52.26#ibcon#enter wrdev, iclass 12, count 0 2006.196.07:57:52.26#ibcon#first serial, iclass 12, count 0 2006.196.07:57:52.26#ibcon#enter sib2, iclass 12, count 0 2006.196.07:57:52.26#ibcon#flushed, iclass 12, count 0 2006.196.07:57:52.26#ibcon#about to write, iclass 12, count 0 2006.196.07:57:52.26#ibcon#wrote, iclass 12, count 0 2006.196.07:57:52.26#ibcon#about to read 3, iclass 12, count 0 2006.196.07:57:52.28#ibcon#read 3, iclass 12, count 0 2006.196.07:57:52.28#ibcon#about to read 4, iclass 12, count 0 2006.196.07:57:52.28#ibcon#read 4, iclass 12, count 0 2006.196.07:57:52.28#ibcon#about to read 5, iclass 12, count 0 2006.196.07:57:52.28#ibcon#read 5, iclass 12, count 0 2006.196.07:57:52.28#ibcon#about to read 6, iclass 12, count 0 2006.196.07:57:52.28#ibcon#read 6, iclass 12, count 0 2006.196.07:57:52.28#ibcon#end of sib2, iclass 12, count 0 2006.196.07:57:52.28#ibcon#*mode == 0, iclass 12, count 0 2006.196.07:57:52.28#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.196.07:57:52.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.196.07:57:52.28#ibcon#*before write, iclass 12, count 0 2006.196.07:57:52.28#ibcon#enter sib2, iclass 12, count 0 2006.196.07:57:52.28#ibcon#flushed, iclass 12, count 0 2006.196.07:57:52.28#ibcon#about to write, iclass 12, count 0 2006.196.07:57:52.28#ibcon#wrote, iclass 12, count 0 2006.196.07:57:52.28#ibcon#about to read 3, iclass 12, count 0 2006.196.07:57:52.32#ibcon#read 3, iclass 12, count 0 2006.196.07:57:52.32#ibcon#about to read 4, iclass 12, count 0 2006.196.07:57:52.32#ibcon#read 4, iclass 12, count 0 2006.196.07:57:52.32#ibcon#about to read 5, iclass 12, count 0 2006.196.07:57:52.32#ibcon#read 5, iclass 12, count 0 2006.196.07:57:52.32#ibcon#about to read 6, iclass 12, count 0 2006.196.07:57:52.32#ibcon#read 6, iclass 12, count 0 2006.196.07:57:52.32#ibcon#end of sib2, iclass 12, count 0 2006.196.07:57:52.32#ibcon#*after write, iclass 12, count 0 2006.196.07:57:52.32#ibcon#*before return 0, iclass 12, count 0 2006.196.07:57:52.32#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.196.07:57:52.32#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.196.07:57:52.32#ibcon#about to clear, iclass 12 cls_cnt 0 2006.196.07:57:52.32#ibcon#cleared, iclass 12 cls_cnt 0 2006.196.07:57:52.32$vc4f8/vb=6,4 2006.196.07:57:52.32#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.196.07:57:52.32#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.196.07:57:52.32#ibcon#ireg 11 cls_cnt 2 2006.196.07:57:52.32#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.196.07:57:52.38#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.196.07:57:52.38#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.196.07:57:52.38#ibcon#enter wrdev, iclass 14, count 2 2006.196.07:57:52.38#ibcon#first serial, iclass 14, count 2 2006.196.07:57:52.38#ibcon#enter sib2, iclass 14, count 2 2006.196.07:57:52.38#ibcon#flushed, iclass 14, count 2 2006.196.07:57:52.38#ibcon#about to write, iclass 14, count 2 2006.196.07:57:52.38#ibcon#wrote, iclass 14, count 2 2006.196.07:57:52.38#ibcon#about to read 3, iclass 14, count 2 2006.196.07:57:52.40#ibcon#read 3, iclass 14, count 2 2006.196.07:57:52.40#ibcon#about to read 4, iclass 14, count 2 2006.196.07:57:52.40#ibcon#read 4, iclass 14, count 2 2006.196.07:57:52.40#ibcon#about to read 5, iclass 14, count 2 2006.196.07:57:52.40#ibcon#read 5, iclass 14, count 2 2006.196.07:57:52.40#ibcon#about to read 6, iclass 14, count 2 2006.196.07:57:52.40#ibcon#read 6, iclass 14, count 2 2006.196.07:57:52.40#ibcon#end of sib2, iclass 14, count 2 2006.196.07:57:52.40#ibcon#*mode == 0, iclass 14, count 2 2006.196.07:57:52.40#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.196.07:57:52.40#ibcon#[27=AT06-04\r\n] 2006.196.07:57:52.40#ibcon#*before write, iclass 14, count 2 2006.196.07:57:52.40#ibcon#enter sib2, iclass 14, count 2 2006.196.07:57:52.40#ibcon#flushed, iclass 14, count 2 2006.196.07:57:52.40#ibcon#about to write, iclass 14, count 2 2006.196.07:57:52.40#ibcon#wrote, iclass 14, count 2 2006.196.07:57:52.40#ibcon#about to read 3, iclass 14, count 2 2006.196.07:57:52.43#ibcon#read 3, iclass 14, count 2 2006.196.07:57:52.43#ibcon#about to read 4, iclass 14, count 2 2006.196.07:57:52.43#ibcon#read 4, iclass 14, count 2 2006.196.07:57:52.43#ibcon#about to read 5, iclass 14, count 2 2006.196.07:57:52.43#ibcon#read 5, iclass 14, count 2 2006.196.07:57:52.43#ibcon#about to read 6, iclass 14, count 2 2006.196.07:57:52.43#ibcon#read 6, iclass 14, count 2 2006.196.07:57:52.43#ibcon#end of sib2, iclass 14, count 2 2006.196.07:57:52.43#ibcon#*after write, iclass 14, count 2 2006.196.07:57:52.43#ibcon#*before return 0, iclass 14, count 2 2006.196.07:57:52.43#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.196.07:57:52.43#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.196.07:57:52.43#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.196.07:57:52.43#ibcon#ireg 7 cls_cnt 0 2006.196.07:57:52.43#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.196.07:57:52.55#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.196.07:57:52.55#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.196.07:57:52.55#ibcon#enter wrdev, iclass 14, count 0 2006.196.07:57:52.55#ibcon#first serial, iclass 14, count 0 2006.196.07:57:52.55#ibcon#enter sib2, iclass 14, count 0 2006.196.07:57:52.55#ibcon#flushed, iclass 14, count 0 2006.196.07:57:52.55#ibcon#about to write, iclass 14, count 0 2006.196.07:57:52.55#ibcon#wrote, iclass 14, count 0 2006.196.07:57:52.55#ibcon#about to read 3, iclass 14, count 0 2006.196.07:57:52.57#ibcon#read 3, iclass 14, count 0 2006.196.07:57:52.57#ibcon#about to read 4, iclass 14, count 0 2006.196.07:57:52.57#ibcon#read 4, iclass 14, count 0 2006.196.07:57:52.57#ibcon#about to read 5, iclass 14, count 0 2006.196.07:57:52.57#ibcon#read 5, iclass 14, count 0 2006.196.07:57:52.57#ibcon#about to read 6, iclass 14, count 0 2006.196.07:57:52.57#ibcon#read 6, iclass 14, count 0 2006.196.07:57:52.57#ibcon#end of sib2, iclass 14, count 0 2006.196.07:57:52.57#ibcon#*mode == 0, iclass 14, count 0 2006.196.07:57:52.57#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.196.07:57:52.57#ibcon#[27=USB\r\n] 2006.196.07:57:52.57#ibcon#*before write, iclass 14, count 0 2006.196.07:57:52.57#ibcon#enter sib2, iclass 14, count 0 2006.196.07:57:52.57#ibcon#flushed, iclass 14, count 0 2006.196.07:57:52.57#ibcon#about to write, iclass 14, count 0 2006.196.07:57:52.57#ibcon#wrote, iclass 14, count 0 2006.196.07:57:52.57#ibcon#about to read 3, iclass 14, count 0 2006.196.07:57:52.60#ibcon#read 3, iclass 14, count 0 2006.196.07:57:52.60#ibcon#about to read 4, iclass 14, count 0 2006.196.07:57:52.60#ibcon#read 4, iclass 14, count 0 2006.196.07:57:52.60#ibcon#about to read 5, iclass 14, count 0 2006.196.07:57:52.60#ibcon#read 5, iclass 14, count 0 2006.196.07:57:52.60#ibcon#about to read 6, iclass 14, count 0 2006.196.07:57:52.60#ibcon#read 6, iclass 14, count 0 2006.196.07:57:52.60#ibcon#end of sib2, iclass 14, count 0 2006.196.07:57:52.60#ibcon#*after write, iclass 14, count 0 2006.196.07:57:52.60#ibcon#*before return 0, iclass 14, count 0 2006.196.07:57:52.60#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.196.07:57:52.60#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.196.07:57:52.60#ibcon#about to clear, iclass 14 cls_cnt 0 2006.196.07:57:52.60#ibcon#cleared, iclass 14 cls_cnt 0 2006.196.07:57:52.60$vc4f8/vabw=wide 2006.196.07:57:52.60#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.196.07:57:52.60#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.196.07:57:52.60#ibcon#ireg 8 cls_cnt 0 2006.196.07:57:52.60#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.196.07:57:52.60#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.196.07:57:52.60#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.196.07:57:52.60#ibcon#enter wrdev, iclass 16, count 0 2006.196.07:57:52.60#ibcon#first serial, iclass 16, count 0 2006.196.07:57:52.60#ibcon#enter sib2, iclass 16, count 0 2006.196.07:57:52.60#ibcon#flushed, iclass 16, count 0 2006.196.07:57:52.60#ibcon#about to write, iclass 16, count 0 2006.196.07:57:52.60#ibcon#wrote, iclass 16, count 0 2006.196.07:57:52.60#ibcon#about to read 3, iclass 16, count 0 2006.196.07:57:52.62#ibcon#read 3, iclass 16, count 0 2006.196.07:57:52.62#ibcon#about to read 4, iclass 16, count 0 2006.196.07:57:52.62#ibcon#read 4, iclass 16, count 0 2006.196.07:57:52.62#ibcon#about to read 5, iclass 16, count 0 2006.196.07:57:52.62#ibcon#read 5, iclass 16, count 0 2006.196.07:57:52.62#ibcon#about to read 6, iclass 16, count 0 2006.196.07:57:52.62#ibcon#read 6, iclass 16, count 0 2006.196.07:57:52.62#ibcon#end of sib2, iclass 16, count 0 2006.196.07:57:52.62#ibcon#*mode == 0, iclass 16, count 0 2006.196.07:57:52.62#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.196.07:57:52.62#ibcon#[25=BW32\r\n] 2006.196.07:57:52.62#ibcon#*before write, iclass 16, count 0 2006.196.07:57:52.62#ibcon#enter sib2, iclass 16, count 0 2006.196.07:57:52.62#ibcon#flushed, iclass 16, count 0 2006.196.07:57:52.62#ibcon#about to write, iclass 16, count 0 2006.196.07:57:52.62#ibcon#wrote, iclass 16, count 0 2006.196.07:57:52.62#ibcon#about to read 3, iclass 16, count 0 2006.196.07:57:52.65#ibcon#read 3, iclass 16, count 0 2006.196.07:57:52.65#ibcon#about to read 4, iclass 16, count 0 2006.196.07:57:52.65#ibcon#read 4, iclass 16, count 0 2006.196.07:57:52.65#ibcon#about to read 5, iclass 16, count 0 2006.196.07:57:52.65#ibcon#read 5, iclass 16, count 0 2006.196.07:57:52.65#ibcon#about to read 6, iclass 16, count 0 2006.196.07:57:52.65#ibcon#read 6, iclass 16, count 0 2006.196.07:57:52.65#ibcon#end of sib2, iclass 16, count 0 2006.196.07:57:52.65#ibcon#*after write, iclass 16, count 0 2006.196.07:57:52.65#ibcon#*before return 0, iclass 16, count 0 2006.196.07:57:52.65#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.196.07:57:52.65#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.196.07:57:52.65#ibcon#about to clear, iclass 16 cls_cnt 0 2006.196.07:57:52.65#ibcon#cleared, iclass 16 cls_cnt 0 2006.196.07:57:52.65$vc4f8/vbbw=wide 2006.196.07:57:52.65#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.196.07:57:52.65#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.196.07:57:52.65#ibcon#ireg 8 cls_cnt 0 2006.196.07:57:52.65#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.196.07:57:52.72#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.196.07:57:52.72#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.196.07:57:52.72#ibcon#enter wrdev, iclass 18, count 0 2006.196.07:57:52.72#ibcon#first serial, iclass 18, count 0 2006.196.07:57:52.72#ibcon#enter sib2, iclass 18, count 0 2006.196.07:57:52.72#ibcon#flushed, iclass 18, count 0 2006.196.07:57:52.72#ibcon#about to write, iclass 18, count 0 2006.196.07:57:52.72#ibcon#wrote, iclass 18, count 0 2006.196.07:57:52.72#ibcon#about to read 3, iclass 18, count 0 2006.196.07:57:52.74#ibcon#read 3, iclass 18, count 0 2006.196.07:57:52.74#ibcon#about to read 4, iclass 18, count 0 2006.196.07:57:52.74#ibcon#read 4, iclass 18, count 0 2006.196.07:57:52.74#ibcon#about to read 5, iclass 18, count 0 2006.196.07:57:52.74#ibcon#read 5, iclass 18, count 0 2006.196.07:57:52.74#ibcon#about to read 6, iclass 18, count 0 2006.196.07:57:52.74#ibcon#read 6, iclass 18, count 0 2006.196.07:57:52.74#ibcon#end of sib2, iclass 18, count 0 2006.196.07:57:52.74#ibcon#*mode == 0, iclass 18, count 0 2006.196.07:57:52.74#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.196.07:57:52.74#ibcon#[27=BW32\r\n] 2006.196.07:57:52.74#ibcon#*before write, iclass 18, count 0 2006.196.07:57:52.74#ibcon#enter sib2, iclass 18, count 0 2006.196.07:57:52.74#ibcon#flushed, iclass 18, count 0 2006.196.07:57:52.74#ibcon#about to write, iclass 18, count 0 2006.196.07:57:52.74#ibcon#wrote, iclass 18, count 0 2006.196.07:57:52.74#ibcon#about to read 3, iclass 18, count 0 2006.196.07:57:52.77#ibcon#read 3, iclass 18, count 0 2006.196.07:57:52.77#ibcon#about to read 4, iclass 18, count 0 2006.196.07:57:52.77#ibcon#read 4, iclass 18, count 0 2006.196.07:57:52.77#ibcon#about to read 5, iclass 18, count 0 2006.196.07:57:52.77#ibcon#read 5, iclass 18, count 0 2006.196.07:57:52.77#ibcon#about to read 6, iclass 18, count 0 2006.196.07:57:52.77#ibcon#read 6, iclass 18, count 0 2006.196.07:57:52.77#ibcon#end of sib2, iclass 18, count 0 2006.196.07:57:52.77#ibcon#*after write, iclass 18, count 0 2006.196.07:57:52.77#ibcon#*before return 0, iclass 18, count 0 2006.196.07:57:52.77#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.196.07:57:52.77#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.196.07:57:52.77#ibcon#about to clear, iclass 18 cls_cnt 0 2006.196.07:57:52.77#ibcon#cleared, iclass 18 cls_cnt 0 2006.196.07:57:52.77$4f8m12a/ifd4f 2006.196.07:57:52.77$ifd4f/lo= 2006.196.07:57:52.77$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.196.07:57:52.77$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.196.07:57:52.77$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.196.07:57:52.77$ifd4f/patch= 2006.196.07:57:52.77$ifd4f/patch=lo1,a1,a2,a3,a4 2006.196.07:57:52.77$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.196.07:57:52.77$ifd4f/patch=lo3,a5,a6,a7,a8 2006.196.07:57:52.77$4f8m12a/"form=m,16.000,1:2 2006.196.07:57:52.77$4f8m12a/"tpicd 2006.196.07:57:52.77$4f8m12a/echo=off 2006.196.07:57:52.77$4f8m12a/xlog=off 2006.196.07:57:52.77:!2006.196.08:00:00 2006.196.07:58:01.13#trakl#Source acquired 2006.196.07:58:02.13#flagr#flagr/antenna,acquired 2006.196.08:00:00.00:preob 2006.196.08:00:00.14/onsource/TRACKING 2006.196.08:00:00.14:!2006.196.08:00:10 2006.196.08:00:10.00:data_valid=on 2006.196.08:00:10.00:midob 2006.196.08:00:11.14/onsource/TRACKING 2006.196.08:00:11.14/wx/29.50,1004.0,90 2006.196.08:00:11.26/cable/+6.3341E-03 2006.196.08:00:12.35/va/01,08,usb,yes,30,31 2006.196.08:00:12.35/va/02,07,usb,yes,30,31 2006.196.08:00:12.35/va/03,06,usb,yes,31,32 2006.196.08:00:12.35/va/04,07,usb,yes,31,33 2006.196.08:00:12.35/va/05,07,usb,yes,33,35 2006.196.08:00:12.35/va/06,06,usb,yes,32,32 2006.196.08:00:12.35/va/07,06,usb,yes,32,32 2006.196.08:00:12.35/va/08,07,usb,yes,31,30 2006.196.08:00:12.58/valo/01,532.99,yes,locked 2006.196.08:00:12.58/valo/02,572.99,yes,locked 2006.196.08:00:12.58/valo/03,672.99,yes,locked 2006.196.08:00:12.58/valo/04,832.99,yes,locked 2006.196.08:00:12.58/valo/05,652.99,yes,locked 2006.196.08:00:12.58/valo/06,772.99,yes,locked 2006.196.08:00:12.58/valo/07,832.99,yes,locked 2006.196.08:00:12.58/valo/08,852.99,yes,locked 2006.196.08:00:13.67/vb/01,04,usb,yes,29,28 2006.196.08:00:13.67/vb/02,04,usb,yes,31,32 2006.196.08:00:13.67/vb/03,04,usb,yes,27,31 2006.196.08:00:13.67/vb/04,04,usb,yes,28,28 2006.196.08:00:13.67/vb/05,04,usb,yes,27,31 2006.196.08:00:13.67/vb/06,04,usb,yes,28,30 2006.196.08:00:13.67/vb/07,04,usb,yes,30,30 2006.196.08:00:13.67/vb/08,04,usb,yes,27,31 2006.196.08:00:13.91/vblo/01,632.99,yes,locked 2006.196.08:00:13.91/vblo/02,640.99,yes,locked 2006.196.08:00:13.91/vblo/03,656.99,yes,locked 2006.196.08:00:13.91/vblo/04,712.99,yes,locked 2006.196.08:00:13.91/vblo/05,744.99,yes,locked 2006.196.08:00:13.91/vblo/06,752.99,yes,locked 2006.196.08:00:13.91/vblo/07,734.99,yes,locked 2006.196.08:00:13.91/vblo/08,744.99,yes,locked 2006.196.08:00:14.06/vabw/8 2006.196.08:00:14.21/vbbw/8 2006.196.08:00:14.30/xfe/off,on,15.2 2006.196.08:00:14.68/ifatt/23,28,28,28 2006.196.08:00:15.07/fmout-gps/S +3.36E-07 2006.196.08:00:15.11:!2006.196.08:01:10 2006.196.08:01:10.00:data_valid=off 2006.196.08:01:10.00:postob 2006.196.08:01:10.07/cable/+6.3348E-03 2006.196.08:01:10.07/wx/29.46,1004.0,91 2006.196.08:01:11.07/fmout-gps/S +3.34E-07 2006.196.08:01:11.07:scan_name=196-0803,k06196,60 2006.196.08:01:11.07:source=1739+522,174036.98,521143.4,2000.0,cw 2006.196.08:01:11.14#flagr#flagr/antenna,new-source 2006.196.08:01:12.14:checkk5 2006.196.08:01:12.51/chk_autoobs//k5ts1/ autoobs is running! 2006.196.08:01:12.88/chk_autoobs//k5ts2/ autoobs is running! 2006.196.08:01:13.26/chk_autoobs//k5ts3/ autoobs is running! 2006.196.08:01:13.64/chk_autoobs//k5ts4/ autoobs is running! 2006.196.08:01:14.01/chk_obsdata//k5ts1/T1960800??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.08:01:14.38/chk_obsdata//k5ts2/T1960800??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.08:01:14.75/chk_obsdata//k5ts3/T1960800??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.08:01:15.13/chk_obsdata//k5ts4/T1960800??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.08:01:15.82/k5log//k5ts1_log_newline 2006.196.08:01:16.51/k5log//k5ts2_log_newline 2006.196.08:01:17.20/k5log//k5ts3_log_newline 2006.196.08:01:17.90/k5log//k5ts4_log_newline 2006.196.08:01:17.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.196.08:01:17.92:4f8m12a=2 2006.196.08:01:17.92$4f8m12a/echo=on 2006.196.08:01:17.92$4f8m12a/pcalon 2006.196.08:01:17.92$pcalon/"no phase cal control is implemented here 2006.196.08:01:17.92$4f8m12a/"tpicd=stop 2006.196.08:01:17.92$4f8m12a/vc4f8 2006.196.08:01:17.92$vc4f8/valo=1,532.99 2006.196.08:01:17.93#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.196.08:01:17.93#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.196.08:01:17.93#ibcon#ireg 17 cls_cnt 0 2006.196.08:01:17.93#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.196.08:01:17.93#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.196.08:01:17.93#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.196.08:01:17.93#ibcon#enter wrdev, iclass 24, count 0 2006.196.08:01:17.93#ibcon#first serial, iclass 24, count 0 2006.196.08:01:17.93#ibcon#enter sib2, iclass 24, count 0 2006.196.08:01:17.93#ibcon#flushed, iclass 24, count 0 2006.196.08:01:17.93#ibcon#about to write, iclass 24, count 0 2006.196.08:01:17.93#ibcon#wrote, iclass 24, count 0 2006.196.08:01:17.93#ibcon#about to read 3, iclass 24, count 0 2006.196.08:01:17.96#ibcon#read 3, iclass 24, count 0 2006.196.08:01:17.96#ibcon#about to read 4, iclass 24, count 0 2006.196.08:01:17.96#ibcon#read 4, iclass 24, count 0 2006.196.08:01:17.96#ibcon#about to read 5, iclass 24, count 0 2006.196.08:01:17.96#ibcon#read 5, iclass 24, count 0 2006.196.08:01:17.96#ibcon#about to read 6, iclass 24, count 0 2006.196.08:01:17.96#ibcon#read 6, iclass 24, count 0 2006.196.08:01:17.96#ibcon#end of sib2, iclass 24, count 0 2006.196.08:01:17.96#ibcon#*mode == 0, iclass 24, count 0 2006.196.08:01:17.96#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.196.08:01:17.96#ibcon#[26=FRQ=01,532.99\r\n] 2006.196.08:01:17.96#ibcon#*before write, iclass 24, count 0 2006.196.08:01:17.96#ibcon#enter sib2, iclass 24, count 0 2006.196.08:01:17.96#ibcon#flushed, iclass 24, count 0 2006.196.08:01:17.96#ibcon#about to write, iclass 24, count 0 2006.196.08:01:17.96#ibcon#wrote, iclass 24, count 0 2006.196.08:01:17.96#ibcon#about to read 3, iclass 24, count 0 2006.196.08:01:18.02#ibcon#read 3, iclass 24, count 0 2006.196.08:01:18.02#ibcon#about to read 4, iclass 24, count 0 2006.196.08:01:18.02#ibcon#read 4, iclass 24, count 0 2006.196.08:01:18.02#ibcon#about to read 5, iclass 24, count 0 2006.196.08:01:18.02#ibcon#read 5, iclass 24, count 0 2006.196.08:01:18.02#ibcon#about to read 6, iclass 24, count 0 2006.196.08:01:18.02#ibcon#read 6, iclass 24, count 0 2006.196.08:01:18.02#ibcon#end of sib2, iclass 24, count 0 2006.196.08:01:18.02#ibcon#*after write, iclass 24, count 0 2006.196.08:01:18.02#ibcon#*before return 0, iclass 24, count 0 2006.196.08:01:18.02#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.196.08:01:18.02#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.196.08:01:18.02#ibcon#about to clear, iclass 24 cls_cnt 0 2006.196.08:01:18.02#ibcon#cleared, iclass 24 cls_cnt 0 2006.196.08:01:18.02$vc4f8/va=1,8 2006.196.08:01:18.02#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.196.08:01:18.02#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.196.08:01:18.02#ibcon#ireg 11 cls_cnt 2 2006.196.08:01:18.02#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.196.08:01:18.02#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.196.08:01:18.02#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.196.08:01:18.02#ibcon#enter wrdev, iclass 26, count 2 2006.196.08:01:18.02#ibcon#first serial, iclass 26, count 2 2006.196.08:01:18.02#ibcon#enter sib2, iclass 26, count 2 2006.196.08:01:18.02#ibcon#flushed, iclass 26, count 2 2006.196.08:01:18.02#ibcon#about to write, iclass 26, count 2 2006.196.08:01:18.02#ibcon#wrote, iclass 26, count 2 2006.196.08:01:18.02#ibcon#about to read 3, iclass 26, count 2 2006.196.08:01:18.04#ibcon#read 3, iclass 26, count 2 2006.196.08:01:18.04#ibcon#about to read 4, iclass 26, count 2 2006.196.08:01:18.04#ibcon#read 4, iclass 26, count 2 2006.196.08:01:18.04#ibcon#about to read 5, iclass 26, count 2 2006.196.08:01:18.04#ibcon#read 5, iclass 26, count 2 2006.196.08:01:18.04#ibcon#about to read 6, iclass 26, count 2 2006.196.08:01:18.04#ibcon#read 6, iclass 26, count 2 2006.196.08:01:18.04#ibcon#end of sib2, iclass 26, count 2 2006.196.08:01:18.04#ibcon#*mode == 0, iclass 26, count 2 2006.196.08:01:18.04#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.196.08:01:18.04#ibcon#[25=AT01-08\r\n] 2006.196.08:01:18.04#ibcon#*before write, iclass 26, count 2 2006.196.08:01:18.04#ibcon#enter sib2, iclass 26, count 2 2006.196.08:01:18.04#ibcon#flushed, iclass 26, count 2 2006.196.08:01:18.04#ibcon#about to write, iclass 26, count 2 2006.196.08:01:18.04#ibcon#wrote, iclass 26, count 2 2006.196.08:01:18.04#ibcon#about to read 3, iclass 26, count 2 2006.196.08:01:18.08#ibcon#read 3, iclass 26, count 2 2006.196.08:01:18.08#ibcon#about to read 4, iclass 26, count 2 2006.196.08:01:18.08#ibcon#read 4, iclass 26, count 2 2006.196.08:01:18.08#ibcon#about to read 5, iclass 26, count 2 2006.196.08:01:18.08#ibcon#read 5, iclass 26, count 2 2006.196.08:01:18.08#ibcon#about to read 6, iclass 26, count 2 2006.196.08:01:18.08#ibcon#read 6, iclass 26, count 2 2006.196.08:01:18.08#ibcon#end of sib2, iclass 26, count 2 2006.196.08:01:18.08#ibcon#*after write, iclass 26, count 2 2006.196.08:01:18.08#ibcon#*before return 0, iclass 26, count 2 2006.196.08:01:18.08#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.196.08:01:18.08#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.196.08:01:18.08#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.196.08:01:18.08#ibcon#ireg 7 cls_cnt 0 2006.196.08:01:18.08#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.196.08:01:18.20#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.196.08:01:18.20#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.196.08:01:18.20#ibcon#enter wrdev, iclass 26, count 0 2006.196.08:01:18.20#ibcon#first serial, iclass 26, count 0 2006.196.08:01:18.20#ibcon#enter sib2, iclass 26, count 0 2006.196.08:01:18.20#ibcon#flushed, iclass 26, count 0 2006.196.08:01:18.20#ibcon#about to write, iclass 26, count 0 2006.196.08:01:18.20#ibcon#wrote, iclass 26, count 0 2006.196.08:01:18.20#ibcon#about to read 3, iclass 26, count 0 2006.196.08:01:18.22#ibcon#read 3, iclass 26, count 0 2006.196.08:01:18.22#ibcon#about to read 4, iclass 26, count 0 2006.196.08:01:18.22#ibcon#read 4, iclass 26, count 0 2006.196.08:01:18.22#ibcon#about to read 5, iclass 26, count 0 2006.196.08:01:18.22#ibcon#read 5, iclass 26, count 0 2006.196.08:01:18.22#ibcon#about to read 6, iclass 26, count 0 2006.196.08:01:18.22#ibcon#read 6, iclass 26, count 0 2006.196.08:01:18.22#ibcon#end of sib2, iclass 26, count 0 2006.196.08:01:18.22#ibcon#*mode == 0, iclass 26, count 0 2006.196.08:01:18.22#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.196.08:01:18.22#ibcon#[25=USB\r\n] 2006.196.08:01:18.22#ibcon#*before write, iclass 26, count 0 2006.196.08:01:18.22#ibcon#enter sib2, iclass 26, count 0 2006.196.08:01:18.22#ibcon#flushed, iclass 26, count 0 2006.196.08:01:18.22#ibcon#about to write, iclass 26, count 0 2006.196.08:01:18.22#ibcon#wrote, iclass 26, count 0 2006.196.08:01:18.22#ibcon#about to read 3, iclass 26, count 0 2006.196.08:01:18.25#ibcon#read 3, iclass 26, count 0 2006.196.08:01:18.25#ibcon#about to read 4, iclass 26, count 0 2006.196.08:01:18.25#ibcon#read 4, iclass 26, count 0 2006.196.08:01:18.25#ibcon#about to read 5, iclass 26, count 0 2006.196.08:01:18.25#ibcon#read 5, iclass 26, count 0 2006.196.08:01:18.25#ibcon#about to read 6, iclass 26, count 0 2006.196.08:01:18.25#ibcon#read 6, iclass 26, count 0 2006.196.08:01:18.25#ibcon#end of sib2, iclass 26, count 0 2006.196.08:01:18.25#ibcon#*after write, iclass 26, count 0 2006.196.08:01:18.25#ibcon#*before return 0, iclass 26, count 0 2006.196.08:01:18.25#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.196.08:01:18.25#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.196.08:01:18.25#ibcon#about to clear, iclass 26 cls_cnt 0 2006.196.08:01:18.25#ibcon#cleared, iclass 26 cls_cnt 0 2006.196.08:01:18.25$vc4f8/valo=2,572.99 2006.196.08:01:18.25#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.196.08:01:18.25#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.196.08:01:18.25#ibcon#ireg 17 cls_cnt 0 2006.196.08:01:18.25#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.196.08:01:18.25#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.196.08:01:18.25#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.196.08:01:18.25#ibcon#enter wrdev, iclass 28, count 0 2006.196.08:01:18.25#ibcon#first serial, iclass 28, count 0 2006.196.08:01:18.25#ibcon#enter sib2, iclass 28, count 0 2006.196.08:01:18.25#ibcon#flushed, iclass 28, count 0 2006.196.08:01:18.25#ibcon#about to write, iclass 28, count 0 2006.196.08:01:18.25#ibcon#wrote, iclass 28, count 0 2006.196.08:01:18.25#ibcon#about to read 3, iclass 28, count 0 2006.196.08:01:18.27#ibcon#read 3, iclass 28, count 0 2006.196.08:01:18.27#ibcon#about to read 4, iclass 28, count 0 2006.196.08:01:18.27#ibcon#read 4, iclass 28, count 0 2006.196.08:01:18.27#ibcon#about to read 5, iclass 28, count 0 2006.196.08:01:18.27#ibcon#read 5, iclass 28, count 0 2006.196.08:01:18.27#ibcon#about to read 6, iclass 28, count 0 2006.196.08:01:18.27#ibcon#read 6, iclass 28, count 0 2006.196.08:01:18.27#ibcon#end of sib2, iclass 28, count 0 2006.196.08:01:18.27#ibcon#*mode == 0, iclass 28, count 0 2006.196.08:01:18.27#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.196.08:01:18.27#ibcon#[26=FRQ=02,572.99\r\n] 2006.196.08:01:18.27#ibcon#*before write, iclass 28, count 0 2006.196.08:01:18.27#ibcon#enter sib2, iclass 28, count 0 2006.196.08:01:18.27#ibcon#flushed, iclass 28, count 0 2006.196.08:01:18.27#ibcon#about to write, iclass 28, count 0 2006.196.08:01:18.27#ibcon#wrote, iclass 28, count 0 2006.196.08:01:18.27#ibcon#about to read 3, iclass 28, count 0 2006.196.08:01:18.31#ibcon#read 3, iclass 28, count 0 2006.196.08:01:18.31#ibcon#about to read 4, iclass 28, count 0 2006.196.08:01:18.31#ibcon#read 4, iclass 28, count 0 2006.196.08:01:18.31#ibcon#about to read 5, iclass 28, count 0 2006.196.08:01:18.31#ibcon#read 5, iclass 28, count 0 2006.196.08:01:18.31#ibcon#about to read 6, iclass 28, count 0 2006.196.08:01:18.31#ibcon#read 6, iclass 28, count 0 2006.196.08:01:18.31#ibcon#end of sib2, iclass 28, count 0 2006.196.08:01:18.31#ibcon#*after write, iclass 28, count 0 2006.196.08:01:18.31#ibcon#*before return 0, iclass 28, count 0 2006.196.08:01:18.31#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.196.08:01:18.31#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.196.08:01:18.31#ibcon#about to clear, iclass 28 cls_cnt 0 2006.196.08:01:18.31#ibcon#cleared, iclass 28 cls_cnt 0 2006.196.08:01:18.31$vc4f8/va=2,7 2006.196.08:01:18.31#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.196.08:01:18.31#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.196.08:01:18.31#ibcon#ireg 11 cls_cnt 2 2006.196.08:01:18.31#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.196.08:01:18.37#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.196.08:01:18.37#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.196.08:01:18.37#ibcon#enter wrdev, iclass 30, count 2 2006.196.08:01:18.37#ibcon#first serial, iclass 30, count 2 2006.196.08:01:18.37#ibcon#enter sib2, iclass 30, count 2 2006.196.08:01:18.37#ibcon#flushed, iclass 30, count 2 2006.196.08:01:18.37#ibcon#about to write, iclass 30, count 2 2006.196.08:01:18.37#ibcon#wrote, iclass 30, count 2 2006.196.08:01:18.37#ibcon#about to read 3, iclass 30, count 2 2006.196.08:01:18.39#ibcon#read 3, iclass 30, count 2 2006.196.08:01:18.39#ibcon#about to read 4, iclass 30, count 2 2006.196.08:01:18.39#ibcon#read 4, iclass 30, count 2 2006.196.08:01:18.39#ibcon#about to read 5, iclass 30, count 2 2006.196.08:01:18.39#ibcon#read 5, iclass 30, count 2 2006.196.08:01:18.39#ibcon#about to read 6, iclass 30, count 2 2006.196.08:01:18.39#ibcon#read 6, iclass 30, count 2 2006.196.08:01:18.39#ibcon#end of sib2, iclass 30, count 2 2006.196.08:01:18.39#ibcon#*mode == 0, iclass 30, count 2 2006.196.08:01:18.39#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.196.08:01:18.39#ibcon#[25=AT02-07\r\n] 2006.196.08:01:18.39#ibcon#*before write, iclass 30, count 2 2006.196.08:01:18.39#ibcon#enter sib2, iclass 30, count 2 2006.196.08:01:18.39#ibcon#flushed, iclass 30, count 2 2006.196.08:01:18.39#ibcon#about to write, iclass 30, count 2 2006.196.08:01:18.39#ibcon#wrote, iclass 30, count 2 2006.196.08:01:18.39#ibcon#about to read 3, iclass 30, count 2 2006.196.08:01:18.42#ibcon#read 3, iclass 30, count 2 2006.196.08:01:18.42#ibcon#about to read 4, iclass 30, count 2 2006.196.08:01:18.42#ibcon#read 4, iclass 30, count 2 2006.196.08:01:18.42#ibcon#about to read 5, iclass 30, count 2 2006.196.08:01:18.42#ibcon#read 5, iclass 30, count 2 2006.196.08:01:18.42#ibcon#about to read 6, iclass 30, count 2 2006.196.08:01:18.42#ibcon#read 6, iclass 30, count 2 2006.196.08:01:18.42#ibcon#end of sib2, iclass 30, count 2 2006.196.08:01:18.42#ibcon#*after write, iclass 30, count 2 2006.196.08:01:18.42#ibcon#*before return 0, iclass 30, count 2 2006.196.08:01:18.42#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.196.08:01:18.42#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.196.08:01:18.42#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.196.08:01:18.42#ibcon#ireg 7 cls_cnt 0 2006.196.08:01:18.42#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.196.08:01:18.54#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.196.08:01:18.54#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.196.08:01:18.54#ibcon#enter wrdev, iclass 30, count 0 2006.196.08:01:18.54#ibcon#first serial, iclass 30, count 0 2006.196.08:01:18.54#ibcon#enter sib2, iclass 30, count 0 2006.196.08:01:18.54#ibcon#flushed, iclass 30, count 0 2006.196.08:01:18.54#ibcon#about to write, iclass 30, count 0 2006.196.08:01:18.54#ibcon#wrote, iclass 30, count 0 2006.196.08:01:18.54#ibcon#about to read 3, iclass 30, count 0 2006.196.08:01:18.56#ibcon#read 3, iclass 30, count 0 2006.196.08:01:18.56#ibcon#about to read 4, iclass 30, count 0 2006.196.08:01:18.56#ibcon#read 4, iclass 30, count 0 2006.196.08:01:18.56#ibcon#about to read 5, iclass 30, count 0 2006.196.08:01:18.56#ibcon#read 5, iclass 30, count 0 2006.196.08:01:18.56#ibcon#about to read 6, iclass 30, count 0 2006.196.08:01:18.56#ibcon#read 6, iclass 30, count 0 2006.196.08:01:18.56#ibcon#end of sib2, iclass 30, count 0 2006.196.08:01:18.56#ibcon#*mode == 0, iclass 30, count 0 2006.196.08:01:18.56#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.196.08:01:18.56#ibcon#[25=USB\r\n] 2006.196.08:01:18.56#ibcon#*before write, iclass 30, count 0 2006.196.08:01:18.56#ibcon#enter sib2, iclass 30, count 0 2006.196.08:01:18.56#ibcon#flushed, iclass 30, count 0 2006.196.08:01:18.56#ibcon#about to write, iclass 30, count 0 2006.196.08:01:18.56#ibcon#wrote, iclass 30, count 0 2006.196.08:01:18.56#ibcon#about to read 3, iclass 30, count 0 2006.196.08:01:18.59#ibcon#read 3, iclass 30, count 0 2006.196.08:01:18.59#ibcon#about to read 4, iclass 30, count 0 2006.196.08:01:18.59#ibcon#read 4, iclass 30, count 0 2006.196.08:01:18.59#ibcon#about to read 5, iclass 30, count 0 2006.196.08:01:18.59#ibcon#read 5, iclass 30, count 0 2006.196.08:01:18.59#ibcon#about to read 6, iclass 30, count 0 2006.196.08:01:18.59#ibcon#read 6, iclass 30, count 0 2006.196.08:01:18.59#ibcon#end of sib2, iclass 30, count 0 2006.196.08:01:18.59#ibcon#*after write, iclass 30, count 0 2006.196.08:01:18.59#ibcon#*before return 0, iclass 30, count 0 2006.196.08:01:18.59#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.196.08:01:18.59#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.196.08:01:18.59#ibcon#about to clear, iclass 30 cls_cnt 0 2006.196.08:01:18.59#ibcon#cleared, iclass 30 cls_cnt 0 2006.196.08:01:18.59$vc4f8/valo=3,672.99 2006.196.08:01:18.59#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.196.08:01:18.59#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.196.08:01:18.59#ibcon#ireg 17 cls_cnt 0 2006.196.08:01:18.59#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.196.08:01:18.59#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.196.08:01:18.59#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.196.08:01:18.59#ibcon#enter wrdev, iclass 32, count 0 2006.196.08:01:18.59#ibcon#first serial, iclass 32, count 0 2006.196.08:01:18.59#ibcon#enter sib2, iclass 32, count 0 2006.196.08:01:18.59#ibcon#flushed, iclass 32, count 0 2006.196.08:01:18.59#ibcon#about to write, iclass 32, count 0 2006.196.08:01:18.59#ibcon#wrote, iclass 32, count 0 2006.196.08:01:18.59#ibcon#about to read 3, iclass 32, count 0 2006.196.08:01:18.61#ibcon#read 3, iclass 32, count 0 2006.196.08:01:18.61#ibcon#about to read 4, iclass 32, count 0 2006.196.08:01:18.61#ibcon#read 4, iclass 32, count 0 2006.196.08:01:18.61#ibcon#about to read 5, iclass 32, count 0 2006.196.08:01:18.61#ibcon#read 5, iclass 32, count 0 2006.196.08:01:18.61#ibcon#about to read 6, iclass 32, count 0 2006.196.08:01:18.61#ibcon#read 6, iclass 32, count 0 2006.196.08:01:18.61#ibcon#end of sib2, iclass 32, count 0 2006.196.08:01:18.61#ibcon#*mode == 0, iclass 32, count 0 2006.196.08:01:18.61#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.196.08:01:18.61#ibcon#[26=FRQ=03,672.99\r\n] 2006.196.08:01:18.61#ibcon#*before write, iclass 32, count 0 2006.196.08:01:18.61#ibcon#enter sib2, iclass 32, count 0 2006.196.08:01:18.61#ibcon#flushed, iclass 32, count 0 2006.196.08:01:18.61#ibcon#about to write, iclass 32, count 0 2006.196.08:01:18.61#ibcon#wrote, iclass 32, count 0 2006.196.08:01:18.61#ibcon#about to read 3, iclass 32, count 0 2006.196.08:01:18.66#ibcon#read 3, iclass 32, count 0 2006.196.08:01:18.66#ibcon#about to read 4, iclass 32, count 0 2006.196.08:01:18.66#ibcon#read 4, iclass 32, count 0 2006.196.08:01:18.66#ibcon#about to read 5, iclass 32, count 0 2006.196.08:01:18.66#ibcon#read 5, iclass 32, count 0 2006.196.08:01:18.66#ibcon#about to read 6, iclass 32, count 0 2006.196.08:01:18.66#ibcon#read 6, iclass 32, count 0 2006.196.08:01:18.66#ibcon#end of sib2, iclass 32, count 0 2006.196.08:01:18.66#ibcon#*after write, iclass 32, count 0 2006.196.08:01:18.66#ibcon#*before return 0, iclass 32, count 0 2006.196.08:01:18.66#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.196.08:01:18.66#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.196.08:01:18.66#ibcon#about to clear, iclass 32 cls_cnt 0 2006.196.08:01:18.66#ibcon#cleared, iclass 32 cls_cnt 0 2006.196.08:01:18.66$vc4f8/va=3,6 2006.196.08:01:18.66#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.196.08:01:18.66#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.196.08:01:18.66#ibcon#ireg 11 cls_cnt 2 2006.196.08:01:18.66#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.196.08:01:18.71#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.196.08:01:18.71#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.196.08:01:18.71#ibcon#enter wrdev, iclass 34, count 2 2006.196.08:01:18.71#ibcon#first serial, iclass 34, count 2 2006.196.08:01:18.71#ibcon#enter sib2, iclass 34, count 2 2006.196.08:01:18.71#ibcon#flushed, iclass 34, count 2 2006.196.08:01:18.71#ibcon#about to write, iclass 34, count 2 2006.196.08:01:18.71#ibcon#wrote, iclass 34, count 2 2006.196.08:01:18.71#ibcon#about to read 3, iclass 34, count 2 2006.196.08:01:18.73#ibcon#read 3, iclass 34, count 2 2006.196.08:01:18.73#ibcon#about to read 4, iclass 34, count 2 2006.196.08:01:18.73#ibcon#read 4, iclass 34, count 2 2006.196.08:01:18.73#ibcon#about to read 5, iclass 34, count 2 2006.196.08:01:18.73#ibcon#read 5, iclass 34, count 2 2006.196.08:01:18.73#ibcon#about to read 6, iclass 34, count 2 2006.196.08:01:18.73#ibcon#read 6, iclass 34, count 2 2006.196.08:01:18.73#ibcon#end of sib2, iclass 34, count 2 2006.196.08:01:18.73#ibcon#*mode == 0, iclass 34, count 2 2006.196.08:01:18.73#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.196.08:01:18.73#ibcon#[25=AT03-06\r\n] 2006.196.08:01:18.73#ibcon#*before write, iclass 34, count 2 2006.196.08:01:18.73#ibcon#enter sib2, iclass 34, count 2 2006.196.08:01:18.73#ibcon#flushed, iclass 34, count 2 2006.196.08:01:18.73#ibcon#about to write, iclass 34, count 2 2006.196.08:01:18.73#ibcon#wrote, iclass 34, count 2 2006.196.08:01:18.73#ibcon#about to read 3, iclass 34, count 2 2006.196.08:01:18.76#ibcon#read 3, iclass 34, count 2 2006.196.08:01:18.76#ibcon#about to read 4, iclass 34, count 2 2006.196.08:01:18.76#ibcon#read 4, iclass 34, count 2 2006.196.08:01:18.76#ibcon#about to read 5, iclass 34, count 2 2006.196.08:01:18.76#ibcon#read 5, iclass 34, count 2 2006.196.08:01:18.76#ibcon#about to read 6, iclass 34, count 2 2006.196.08:01:18.76#ibcon#read 6, iclass 34, count 2 2006.196.08:01:18.76#ibcon#end of sib2, iclass 34, count 2 2006.196.08:01:18.76#ibcon#*after write, iclass 34, count 2 2006.196.08:01:18.76#ibcon#*before return 0, iclass 34, count 2 2006.196.08:01:18.76#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.196.08:01:18.76#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.196.08:01:18.76#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.196.08:01:18.76#ibcon#ireg 7 cls_cnt 0 2006.196.08:01:18.76#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.196.08:01:18.88#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.196.08:01:18.88#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.196.08:01:18.88#ibcon#enter wrdev, iclass 34, count 0 2006.196.08:01:18.88#ibcon#first serial, iclass 34, count 0 2006.196.08:01:18.88#ibcon#enter sib2, iclass 34, count 0 2006.196.08:01:18.88#ibcon#flushed, iclass 34, count 0 2006.196.08:01:18.88#ibcon#about to write, iclass 34, count 0 2006.196.08:01:18.88#ibcon#wrote, iclass 34, count 0 2006.196.08:01:18.88#ibcon#about to read 3, iclass 34, count 0 2006.196.08:01:18.90#ibcon#read 3, iclass 34, count 0 2006.196.08:01:18.90#ibcon#about to read 4, iclass 34, count 0 2006.196.08:01:18.90#ibcon#read 4, iclass 34, count 0 2006.196.08:01:18.90#ibcon#about to read 5, iclass 34, count 0 2006.196.08:01:18.90#ibcon#read 5, iclass 34, count 0 2006.196.08:01:18.90#ibcon#about to read 6, iclass 34, count 0 2006.196.08:01:18.90#ibcon#read 6, iclass 34, count 0 2006.196.08:01:18.90#ibcon#end of sib2, iclass 34, count 0 2006.196.08:01:18.90#ibcon#*mode == 0, iclass 34, count 0 2006.196.08:01:18.90#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.196.08:01:18.90#ibcon#[25=USB\r\n] 2006.196.08:01:18.90#ibcon#*before write, iclass 34, count 0 2006.196.08:01:18.90#ibcon#enter sib2, iclass 34, count 0 2006.196.08:01:18.90#ibcon#flushed, iclass 34, count 0 2006.196.08:01:18.90#ibcon#about to write, iclass 34, count 0 2006.196.08:01:18.90#ibcon#wrote, iclass 34, count 0 2006.196.08:01:18.90#ibcon#about to read 3, iclass 34, count 0 2006.196.08:01:18.93#ibcon#read 3, iclass 34, count 0 2006.196.08:01:18.93#ibcon#about to read 4, iclass 34, count 0 2006.196.08:01:18.93#ibcon#read 4, iclass 34, count 0 2006.196.08:01:18.93#ibcon#about to read 5, iclass 34, count 0 2006.196.08:01:18.93#ibcon#read 5, iclass 34, count 0 2006.196.08:01:18.93#ibcon#about to read 6, iclass 34, count 0 2006.196.08:01:18.93#ibcon#read 6, iclass 34, count 0 2006.196.08:01:18.93#ibcon#end of sib2, iclass 34, count 0 2006.196.08:01:18.93#ibcon#*after write, iclass 34, count 0 2006.196.08:01:18.93#ibcon#*before return 0, iclass 34, count 0 2006.196.08:01:18.93#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.196.08:01:18.93#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.196.08:01:18.93#ibcon#about to clear, iclass 34 cls_cnt 0 2006.196.08:01:18.93#ibcon#cleared, iclass 34 cls_cnt 0 2006.196.08:01:18.93$vc4f8/valo=4,832.99 2006.196.08:01:18.93#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.196.08:01:18.93#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.196.08:01:18.93#ibcon#ireg 17 cls_cnt 0 2006.196.08:01:18.93#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.196.08:01:18.93#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.196.08:01:18.93#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.196.08:01:18.93#ibcon#enter wrdev, iclass 36, count 0 2006.196.08:01:18.93#ibcon#first serial, iclass 36, count 0 2006.196.08:01:18.93#ibcon#enter sib2, iclass 36, count 0 2006.196.08:01:18.93#ibcon#flushed, iclass 36, count 0 2006.196.08:01:18.93#ibcon#about to write, iclass 36, count 0 2006.196.08:01:18.93#ibcon#wrote, iclass 36, count 0 2006.196.08:01:18.93#ibcon#about to read 3, iclass 36, count 0 2006.196.08:01:18.95#ibcon#read 3, iclass 36, count 0 2006.196.08:01:18.95#ibcon#about to read 4, iclass 36, count 0 2006.196.08:01:18.95#ibcon#read 4, iclass 36, count 0 2006.196.08:01:18.95#ibcon#about to read 5, iclass 36, count 0 2006.196.08:01:18.95#ibcon#read 5, iclass 36, count 0 2006.196.08:01:18.95#ibcon#about to read 6, iclass 36, count 0 2006.196.08:01:18.95#ibcon#read 6, iclass 36, count 0 2006.196.08:01:18.95#ibcon#end of sib2, iclass 36, count 0 2006.196.08:01:18.95#ibcon#*mode == 0, iclass 36, count 0 2006.196.08:01:18.95#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.196.08:01:18.95#ibcon#[26=FRQ=04,832.99\r\n] 2006.196.08:01:18.95#ibcon#*before write, iclass 36, count 0 2006.196.08:01:18.95#ibcon#enter sib2, iclass 36, count 0 2006.196.08:01:18.95#ibcon#flushed, iclass 36, count 0 2006.196.08:01:18.95#ibcon#about to write, iclass 36, count 0 2006.196.08:01:18.95#ibcon#wrote, iclass 36, count 0 2006.196.08:01:18.95#ibcon#about to read 3, iclass 36, count 0 2006.196.08:01:18.99#ibcon#read 3, iclass 36, count 0 2006.196.08:01:18.99#ibcon#about to read 4, iclass 36, count 0 2006.196.08:01:18.99#ibcon#read 4, iclass 36, count 0 2006.196.08:01:18.99#ibcon#about to read 5, iclass 36, count 0 2006.196.08:01:18.99#ibcon#read 5, iclass 36, count 0 2006.196.08:01:18.99#ibcon#about to read 6, iclass 36, count 0 2006.196.08:01:18.99#ibcon#read 6, iclass 36, count 0 2006.196.08:01:18.99#ibcon#end of sib2, iclass 36, count 0 2006.196.08:01:18.99#ibcon#*after write, iclass 36, count 0 2006.196.08:01:18.99#ibcon#*before return 0, iclass 36, count 0 2006.196.08:01:18.99#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.196.08:01:18.99#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.196.08:01:18.99#ibcon#about to clear, iclass 36 cls_cnt 0 2006.196.08:01:18.99#ibcon#cleared, iclass 36 cls_cnt 0 2006.196.08:01:18.99$vc4f8/va=4,7 2006.196.08:01:18.99#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.196.08:01:18.99#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.196.08:01:18.99#ibcon#ireg 11 cls_cnt 2 2006.196.08:01:18.99#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.196.08:01:19.05#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.196.08:01:19.05#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.196.08:01:19.05#ibcon#enter wrdev, iclass 38, count 2 2006.196.08:01:19.05#ibcon#first serial, iclass 38, count 2 2006.196.08:01:19.05#ibcon#enter sib2, iclass 38, count 2 2006.196.08:01:19.05#ibcon#flushed, iclass 38, count 2 2006.196.08:01:19.05#ibcon#about to write, iclass 38, count 2 2006.196.08:01:19.05#ibcon#wrote, iclass 38, count 2 2006.196.08:01:19.05#ibcon#about to read 3, iclass 38, count 2 2006.196.08:01:19.07#ibcon#read 3, iclass 38, count 2 2006.196.08:01:19.07#ibcon#about to read 4, iclass 38, count 2 2006.196.08:01:19.07#ibcon#read 4, iclass 38, count 2 2006.196.08:01:19.07#ibcon#about to read 5, iclass 38, count 2 2006.196.08:01:19.07#ibcon#read 5, iclass 38, count 2 2006.196.08:01:19.07#ibcon#about to read 6, iclass 38, count 2 2006.196.08:01:19.07#ibcon#read 6, iclass 38, count 2 2006.196.08:01:19.07#ibcon#end of sib2, iclass 38, count 2 2006.196.08:01:19.07#ibcon#*mode == 0, iclass 38, count 2 2006.196.08:01:19.07#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.196.08:01:19.07#ibcon#[25=AT04-07\r\n] 2006.196.08:01:19.07#ibcon#*before write, iclass 38, count 2 2006.196.08:01:19.07#ibcon#enter sib2, iclass 38, count 2 2006.196.08:01:19.07#ibcon#flushed, iclass 38, count 2 2006.196.08:01:19.07#ibcon#about to write, iclass 38, count 2 2006.196.08:01:19.07#ibcon#wrote, iclass 38, count 2 2006.196.08:01:19.07#ibcon#about to read 3, iclass 38, count 2 2006.196.08:01:19.10#ibcon#read 3, iclass 38, count 2 2006.196.08:01:19.10#ibcon#about to read 4, iclass 38, count 2 2006.196.08:01:19.10#ibcon#read 4, iclass 38, count 2 2006.196.08:01:19.10#ibcon#about to read 5, iclass 38, count 2 2006.196.08:01:19.10#ibcon#read 5, iclass 38, count 2 2006.196.08:01:19.10#ibcon#about to read 6, iclass 38, count 2 2006.196.08:01:19.10#ibcon#read 6, iclass 38, count 2 2006.196.08:01:19.10#ibcon#end of sib2, iclass 38, count 2 2006.196.08:01:19.10#ibcon#*after write, iclass 38, count 2 2006.196.08:01:19.10#ibcon#*before return 0, iclass 38, count 2 2006.196.08:01:19.10#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.196.08:01:19.10#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.196.08:01:19.10#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.196.08:01:19.10#ibcon#ireg 7 cls_cnt 0 2006.196.08:01:19.10#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.196.08:01:19.18#abcon#<5=/05 3.6 6.7 29.46 911004.0\r\n> 2006.196.08:01:19.20#abcon#{5=INTERFACE CLEAR} 2006.196.08:01:19.22#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.196.08:01:19.22#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.196.08:01:19.22#ibcon#enter wrdev, iclass 38, count 0 2006.196.08:01:19.22#ibcon#first serial, iclass 38, count 0 2006.196.08:01:19.22#ibcon#enter sib2, iclass 38, count 0 2006.196.08:01:19.22#ibcon#flushed, iclass 38, count 0 2006.196.08:01:19.22#ibcon#about to write, iclass 38, count 0 2006.196.08:01:19.22#ibcon#wrote, iclass 38, count 0 2006.196.08:01:19.22#ibcon#about to read 3, iclass 38, count 0 2006.196.08:01:19.24#ibcon#read 3, iclass 38, count 0 2006.196.08:01:19.24#ibcon#about to read 4, iclass 38, count 0 2006.196.08:01:19.24#ibcon#read 4, iclass 38, count 0 2006.196.08:01:19.24#ibcon#about to read 5, iclass 38, count 0 2006.196.08:01:19.24#ibcon#read 5, iclass 38, count 0 2006.196.08:01:19.24#ibcon#about to read 6, iclass 38, count 0 2006.196.08:01:19.24#ibcon#read 6, iclass 38, count 0 2006.196.08:01:19.24#ibcon#end of sib2, iclass 38, count 0 2006.196.08:01:19.24#ibcon#*mode == 0, iclass 38, count 0 2006.196.08:01:19.24#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.196.08:01:19.24#ibcon#[25=USB\r\n] 2006.196.08:01:19.24#ibcon#*before write, iclass 38, count 0 2006.196.08:01:19.24#ibcon#enter sib2, iclass 38, count 0 2006.196.08:01:19.24#ibcon#flushed, iclass 38, count 0 2006.196.08:01:19.24#ibcon#about to write, iclass 38, count 0 2006.196.08:01:19.24#ibcon#wrote, iclass 38, count 0 2006.196.08:01:19.24#ibcon#about to read 3, iclass 38, count 0 2006.196.08:01:19.26#abcon#[5=S1D000X0/0*\r\n] 2006.196.08:01:19.27#ibcon#read 3, iclass 38, count 0 2006.196.08:01:19.27#ibcon#about to read 4, iclass 38, count 0 2006.196.08:01:19.27#ibcon#read 4, iclass 38, count 0 2006.196.08:01:19.27#ibcon#about to read 5, iclass 38, count 0 2006.196.08:01:19.27#ibcon#read 5, iclass 38, count 0 2006.196.08:01:19.27#ibcon#about to read 6, iclass 38, count 0 2006.196.08:01:19.27#ibcon#read 6, iclass 38, count 0 2006.196.08:01:19.27#ibcon#end of sib2, iclass 38, count 0 2006.196.08:01:19.27#ibcon#*after write, iclass 38, count 0 2006.196.08:01:19.27#ibcon#*before return 0, iclass 38, count 0 2006.196.08:01:19.27#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.196.08:01:19.27#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.196.08:01:19.27#ibcon#about to clear, iclass 38 cls_cnt 0 2006.196.08:01:19.27#ibcon#cleared, iclass 38 cls_cnt 0 2006.196.08:01:19.27$vc4f8/valo=5,652.99 2006.196.08:01:19.27#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.196.08:01:19.27#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.196.08:01:19.27#ibcon#ireg 17 cls_cnt 0 2006.196.08:01:19.27#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.196.08:01:19.27#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.196.08:01:19.27#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.196.08:01:19.27#ibcon#enter wrdev, iclass 6, count 0 2006.196.08:01:19.27#ibcon#first serial, iclass 6, count 0 2006.196.08:01:19.27#ibcon#enter sib2, iclass 6, count 0 2006.196.08:01:19.27#ibcon#flushed, iclass 6, count 0 2006.196.08:01:19.27#ibcon#about to write, iclass 6, count 0 2006.196.08:01:19.27#ibcon#wrote, iclass 6, count 0 2006.196.08:01:19.27#ibcon#about to read 3, iclass 6, count 0 2006.196.08:01:19.29#ibcon#read 3, iclass 6, count 0 2006.196.08:01:19.29#ibcon#about to read 4, iclass 6, count 0 2006.196.08:01:19.29#ibcon#read 4, iclass 6, count 0 2006.196.08:01:19.29#ibcon#about to read 5, iclass 6, count 0 2006.196.08:01:19.29#ibcon#read 5, iclass 6, count 0 2006.196.08:01:19.29#ibcon#about to read 6, iclass 6, count 0 2006.196.08:01:19.29#ibcon#read 6, iclass 6, count 0 2006.196.08:01:19.29#ibcon#end of sib2, iclass 6, count 0 2006.196.08:01:19.29#ibcon#*mode == 0, iclass 6, count 0 2006.196.08:01:19.29#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.196.08:01:19.29#ibcon#[26=FRQ=05,652.99\r\n] 2006.196.08:01:19.29#ibcon#*before write, iclass 6, count 0 2006.196.08:01:19.29#ibcon#enter sib2, iclass 6, count 0 2006.196.08:01:19.29#ibcon#flushed, iclass 6, count 0 2006.196.08:01:19.29#ibcon#about to write, iclass 6, count 0 2006.196.08:01:19.29#ibcon#wrote, iclass 6, count 0 2006.196.08:01:19.29#ibcon#about to read 3, iclass 6, count 0 2006.196.08:01:19.33#ibcon#read 3, iclass 6, count 0 2006.196.08:01:19.33#ibcon#about to read 4, iclass 6, count 0 2006.196.08:01:19.33#ibcon#read 4, iclass 6, count 0 2006.196.08:01:19.33#ibcon#about to read 5, iclass 6, count 0 2006.196.08:01:19.33#ibcon#read 5, iclass 6, count 0 2006.196.08:01:19.33#ibcon#about to read 6, iclass 6, count 0 2006.196.08:01:19.33#ibcon#read 6, iclass 6, count 0 2006.196.08:01:19.33#ibcon#end of sib2, iclass 6, count 0 2006.196.08:01:19.33#ibcon#*after write, iclass 6, count 0 2006.196.08:01:19.33#ibcon#*before return 0, iclass 6, count 0 2006.196.08:01:19.33#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.196.08:01:19.33#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.196.08:01:19.33#ibcon#about to clear, iclass 6 cls_cnt 0 2006.196.08:01:19.33#ibcon#cleared, iclass 6 cls_cnt 0 2006.196.08:01:19.33$vc4f8/va=5,7 2006.196.08:01:19.33#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.196.08:01:19.33#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.196.08:01:19.33#ibcon#ireg 11 cls_cnt 2 2006.196.08:01:19.33#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.196.08:01:19.39#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.196.08:01:19.39#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.196.08:01:19.39#ibcon#enter wrdev, iclass 10, count 2 2006.196.08:01:19.39#ibcon#first serial, iclass 10, count 2 2006.196.08:01:19.39#ibcon#enter sib2, iclass 10, count 2 2006.196.08:01:19.39#ibcon#flushed, iclass 10, count 2 2006.196.08:01:19.39#ibcon#about to write, iclass 10, count 2 2006.196.08:01:19.39#ibcon#wrote, iclass 10, count 2 2006.196.08:01:19.39#ibcon#about to read 3, iclass 10, count 2 2006.196.08:01:19.41#ibcon#read 3, iclass 10, count 2 2006.196.08:01:19.41#ibcon#about to read 4, iclass 10, count 2 2006.196.08:01:19.41#ibcon#read 4, iclass 10, count 2 2006.196.08:01:19.41#ibcon#about to read 5, iclass 10, count 2 2006.196.08:01:19.41#ibcon#read 5, iclass 10, count 2 2006.196.08:01:19.41#ibcon#about to read 6, iclass 10, count 2 2006.196.08:01:19.41#ibcon#read 6, iclass 10, count 2 2006.196.08:01:19.41#ibcon#end of sib2, iclass 10, count 2 2006.196.08:01:19.41#ibcon#*mode == 0, iclass 10, count 2 2006.196.08:01:19.41#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.196.08:01:19.41#ibcon#[25=AT05-07\r\n] 2006.196.08:01:19.41#ibcon#*before write, iclass 10, count 2 2006.196.08:01:19.41#ibcon#enter sib2, iclass 10, count 2 2006.196.08:01:19.41#ibcon#flushed, iclass 10, count 2 2006.196.08:01:19.41#ibcon#about to write, iclass 10, count 2 2006.196.08:01:19.41#ibcon#wrote, iclass 10, count 2 2006.196.08:01:19.41#ibcon#about to read 3, iclass 10, count 2 2006.196.08:01:19.44#ibcon#read 3, iclass 10, count 2 2006.196.08:01:19.44#ibcon#about to read 4, iclass 10, count 2 2006.196.08:01:19.44#ibcon#read 4, iclass 10, count 2 2006.196.08:01:19.44#ibcon#about to read 5, iclass 10, count 2 2006.196.08:01:19.44#ibcon#read 5, iclass 10, count 2 2006.196.08:01:19.44#ibcon#about to read 6, iclass 10, count 2 2006.196.08:01:19.44#ibcon#read 6, iclass 10, count 2 2006.196.08:01:19.44#ibcon#end of sib2, iclass 10, count 2 2006.196.08:01:19.44#ibcon#*after write, iclass 10, count 2 2006.196.08:01:19.44#ibcon#*before return 0, iclass 10, count 2 2006.196.08:01:19.44#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.196.08:01:19.44#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.196.08:01:19.44#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.196.08:01:19.44#ibcon#ireg 7 cls_cnt 0 2006.196.08:01:19.44#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.196.08:01:19.56#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.196.08:01:19.56#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.196.08:01:19.56#ibcon#enter wrdev, iclass 10, count 0 2006.196.08:01:19.56#ibcon#first serial, iclass 10, count 0 2006.196.08:01:19.56#ibcon#enter sib2, iclass 10, count 0 2006.196.08:01:19.56#ibcon#flushed, iclass 10, count 0 2006.196.08:01:19.56#ibcon#about to write, iclass 10, count 0 2006.196.08:01:19.56#ibcon#wrote, iclass 10, count 0 2006.196.08:01:19.56#ibcon#about to read 3, iclass 10, count 0 2006.196.08:01:19.58#ibcon#read 3, iclass 10, count 0 2006.196.08:01:19.58#ibcon#about to read 4, iclass 10, count 0 2006.196.08:01:19.58#ibcon#read 4, iclass 10, count 0 2006.196.08:01:19.58#ibcon#about to read 5, iclass 10, count 0 2006.196.08:01:19.58#ibcon#read 5, iclass 10, count 0 2006.196.08:01:19.58#ibcon#about to read 6, iclass 10, count 0 2006.196.08:01:19.58#ibcon#read 6, iclass 10, count 0 2006.196.08:01:19.58#ibcon#end of sib2, iclass 10, count 0 2006.196.08:01:19.58#ibcon#*mode == 0, iclass 10, count 0 2006.196.08:01:19.58#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.196.08:01:19.58#ibcon#[25=USB\r\n] 2006.196.08:01:19.58#ibcon#*before write, iclass 10, count 0 2006.196.08:01:19.58#ibcon#enter sib2, iclass 10, count 0 2006.196.08:01:19.58#ibcon#flushed, iclass 10, count 0 2006.196.08:01:19.58#ibcon#about to write, iclass 10, count 0 2006.196.08:01:19.58#ibcon#wrote, iclass 10, count 0 2006.196.08:01:19.58#ibcon#about to read 3, iclass 10, count 0 2006.196.08:01:19.61#ibcon#read 3, iclass 10, count 0 2006.196.08:01:19.61#ibcon#about to read 4, iclass 10, count 0 2006.196.08:01:19.61#ibcon#read 4, iclass 10, count 0 2006.196.08:01:19.61#ibcon#about to read 5, iclass 10, count 0 2006.196.08:01:19.61#ibcon#read 5, iclass 10, count 0 2006.196.08:01:19.61#ibcon#about to read 6, iclass 10, count 0 2006.196.08:01:19.61#ibcon#read 6, iclass 10, count 0 2006.196.08:01:19.61#ibcon#end of sib2, iclass 10, count 0 2006.196.08:01:19.61#ibcon#*after write, iclass 10, count 0 2006.196.08:01:19.61#ibcon#*before return 0, iclass 10, count 0 2006.196.08:01:19.61#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.196.08:01:19.61#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.196.08:01:19.61#ibcon#about to clear, iclass 10 cls_cnt 0 2006.196.08:01:19.61#ibcon#cleared, iclass 10 cls_cnt 0 2006.196.08:01:19.61$vc4f8/valo=6,772.99 2006.196.08:01:19.61#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.196.08:01:19.61#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.196.08:01:19.61#ibcon#ireg 17 cls_cnt 0 2006.196.08:01:19.61#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.196.08:01:19.61#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.196.08:01:19.61#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.196.08:01:19.61#ibcon#enter wrdev, iclass 12, count 0 2006.196.08:01:19.61#ibcon#first serial, iclass 12, count 0 2006.196.08:01:19.61#ibcon#enter sib2, iclass 12, count 0 2006.196.08:01:19.61#ibcon#flushed, iclass 12, count 0 2006.196.08:01:19.61#ibcon#about to write, iclass 12, count 0 2006.196.08:01:19.61#ibcon#wrote, iclass 12, count 0 2006.196.08:01:19.61#ibcon#about to read 3, iclass 12, count 0 2006.196.08:01:19.63#ibcon#read 3, iclass 12, count 0 2006.196.08:01:19.63#ibcon#about to read 4, iclass 12, count 0 2006.196.08:01:19.63#ibcon#read 4, iclass 12, count 0 2006.196.08:01:19.63#ibcon#about to read 5, iclass 12, count 0 2006.196.08:01:19.63#ibcon#read 5, iclass 12, count 0 2006.196.08:01:19.63#ibcon#about to read 6, iclass 12, count 0 2006.196.08:01:19.63#ibcon#read 6, iclass 12, count 0 2006.196.08:01:19.63#ibcon#end of sib2, iclass 12, count 0 2006.196.08:01:19.63#ibcon#*mode == 0, iclass 12, count 0 2006.196.08:01:19.63#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.196.08:01:19.63#ibcon#[26=FRQ=06,772.99\r\n] 2006.196.08:01:19.63#ibcon#*before write, iclass 12, count 0 2006.196.08:01:19.63#ibcon#enter sib2, iclass 12, count 0 2006.196.08:01:19.63#ibcon#flushed, iclass 12, count 0 2006.196.08:01:19.63#ibcon#about to write, iclass 12, count 0 2006.196.08:01:19.63#ibcon#wrote, iclass 12, count 0 2006.196.08:01:19.63#ibcon#about to read 3, iclass 12, count 0 2006.196.08:01:19.67#ibcon#read 3, iclass 12, count 0 2006.196.08:01:19.67#ibcon#about to read 4, iclass 12, count 0 2006.196.08:01:19.67#ibcon#read 4, iclass 12, count 0 2006.196.08:01:19.67#ibcon#about to read 5, iclass 12, count 0 2006.196.08:01:19.67#ibcon#read 5, iclass 12, count 0 2006.196.08:01:19.67#ibcon#about to read 6, iclass 12, count 0 2006.196.08:01:19.67#ibcon#read 6, iclass 12, count 0 2006.196.08:01:19.67#ibcon#end of sib2, iclass 12, count 0 2006.196.08:01:19.67#ibcon#*after write, iclass 12, count 0 2006.196.08:01:19.67#ibcon#*before return 0, iclass 12, count 0 2006.196.08:01:19.67#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.196.08:01:19.67#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.196.08:01:19.67#ibcon#about to clear, iclass 12 cls_cnt 0 2006.196.08:01:19.67#ibcon#cleared, iclass 12 cls_cnt 0 2006.196.08:01:19.67$vc4f8/va=6,6 2006.196.08:01:19.67#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.196.08:01:19.67#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.196.08:01:19.67#ibcon#ireg 11 cls_cnt 2 2006.196.08:01:19.67#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.196.08:01:19.73#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.196.08:01:19.73#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.196.08:01:19.73#ibcon#enter wrdev, iclass 14, count 2 2006.196.08:01:19.73#ibcon#first serial, iclass 14, count 2 2006.196.08:01:19.73#ibcon#enter sib2, iclass 14, count 2 2006.196.08:01:19.73#ibcon#flushed, iclass 14, count 2 2006.196.08:01:19.73#ibcon#about to write, iclass 14, count 2 2006.196.08:01:19.73#ibcon#wrote, iclass 14, count 2 2006.196.08:01:19.73#ibcon#about to read 3, iclass 14, count 2 2006.196.08:01:19.75#ibcon#read 3, iclass 14, count 2 2006.196.08:01:19.75#ibcon#about to read 4, iclass 14, count 2 2006.196.08:01:19.75#ibcon#read 4, iclass 14, count 2 2006.196.08:01:19.75#ibcon#about to read 5, iclass 14, count 2 2006.196.08:01:19.75#ibcon#read 5, iclass 14, count 2 2006.196.08:01:19.75#ibcon#about to read 6, iclass 14, count 2 2006.196.08:01:19.75#ibcon#read 6, iclass 14, count 2 2006.196.08:01:19.75#ibcon#end of sib2, iclass 14, count 2 2006.196.08:01:19.75#ibcon#*mode == 0, iclass 14, count 2 2006.196.08:01:19.75#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.196.08:01:19.75#ibcon#[25=AT06-06\r\n] 2006.196.08:01:19.75#ibcon#*before write, iclass 14, count 2 2006.196.08:01:19.75#ibcon#enter sib2, iclass 14, count 2 2006.196.08:01:19.75#ibcon#flushed, iclass 14, count 2 2006.196.08:01:19.75#ibcon#about to write, iclass 14, count 2 2006.196.08:01:19.75#ibcon#wrote, iclass 14, count 2 2006.196.08:01:19.75#ibcon#about to read 3, iclass 14, count 2 2006.196.08:01:19.78#ibcon#read 3, iclass 14, count 2 2006.196.08:01:19.78#ibcon#about to read 4, iclass 14, count 2 2006.196.08:01:19.78#ibcon#read 4, iclass 14, count 2 2006.196.08:01:19.78#ibcon#about to read 5, iclass 14, count 2 2006.196.08:01:19.78#ibcon#read 5, iclass 14, count 2 2006.196.08:01:19.78#ibcon#about to read 6, iclass 14, count 2 2006.196.08:01:19.78#ibcon#read 6, iclass 14, count 2 2006.196.08:01:19.78#ibcon#end of sib2, iclass 14, count 2 2006.196.08:01:19.78#ibcon#*after write, iclass 14, count 2 2006.196.08:01:19.78#ibcon#*before return 0, iclass 14, count 2 2006.196.08:01:19.78#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.196.08:01:19.78#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.196.08:01:19.78#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.196.08:01:19.78#ibcon#ireg 7 cls_cnt 0 2006.196.08:01:19.78#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.196.08:01:19.90#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.196.08:01:19.90#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.196.08:01:19.90#ibcon#enter wrdev, iclass 14, count 0 2006.196.08:01:19.90#ibcon#first serial, iclass 14, count 0 2006.196.08:01:19.90#ibcon#enter sib2, iclass 14, count 0 2006.196.08:01:19.90#ibcon#flushed, iclass 14, count 0 2006.196.08:01:19.90#ibcon#about to write, iclass 14, count 0 2006.196.08:01:19.90#ibcon#wrote, iclass 14, count 0 2006.196.08:01:19.90#ibcon#about to read 3, iclass 14, count 0 2006.196.08:01:19.92#ibcon#read 3, iclass 14, count 0 2006.196.08:01:19.92#ibcon#about to read 4, iclass 14, count 0 2006.196.08:01:19.92#ibcon#read 4, iclass 14, count 0 2006.196.08:01:19.92#ibcon#about to read 5, iclass 14, count 0 2006.196.08:01:19.92#ibcon#read 5, iclass 14, count 0 2006.196.08:01:19.92#ibcon#about to read 6, iclass 14, count 0 2006.196.08:01:19.92#ibcon#read 6, iclass 14, count 0 2006.196.08:01:19.92#ibcon#end of sib2, iclass 14, count 0 2006.196.08:01:19.92#ibcon#*mode == 0, iclass 14, count 0 2006.196.08:01:19.92#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.196.08:01:19.92#ibcon#[25=USB\r\n] 2006.196.08:01:19.92#ibcon#*before write, iclass 14, count 0 2006.196.08:01:19.92#ibcon#enter sib2, iclass 14, count 0 2006.196.08:01:19.92#ibcon#flushed, iclass 14, count 0 2006.196.08:01:19.92#ibcon#about to write, iclass 14, count 0 2006.196.08:01:19.92#ibcon#wrote, iclass 14, count 0 2006.196.08:01:19.92#ibcon#about to read 3, iclass 14, count 0 2006.196.08:01:19.95#ibcon#read 3, iclass 14, count 0 2006.196.08:01:19.95#ibcon#about to read 4, iclass 14, count 0 2006.196.08:01:19.95#ibcon#read 4, iclass 14, count 0 2006.196.08:01:19.95#ibcon#about to read 5, iclass 14, count 0 2006.196.08:01:19.95#ibcon#read 5, iclass 14, count 0 2006.196.08:01:19.95#ibcon#about to read 6, iclass 14, count 0 2006.196.08:01:19.95#ibcon#read 6, iclass 14, count 0 2006.196.08:01:19.95#ibcon#end of sib2, iclass 14, count 0 2006.196.08:01:19.95#ibcon#*after write, iclass 14, count 0 2006.196.08:01:19.95#ibcon#*before return 0, iclass 14, count 0 2006.196.08:01:19.95#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.196.08:01:19.95#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.196.08:01:19.95#ibcon#about to clear, iclass 14 cls_cnt 0 2006.196.08:01:19.95#ibcon#cleared, iclass 14 cls_cnt 0 2006.196.08:01:19.95$vc4f8/valo=7,832.99 2006.196.08:01:19.95#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.196.08:01:19.95#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.196.08:01:19.95#ibcon#ireg 17 cls_cnt 0 2006.196.08:01:19.95#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.196.08:01:19.95#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.196.08:01:19.95#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.196.08:01:19.95#ibcon#enter wrdev, iclass 16, count 0 2006.196.08:01:19.95#ibcon#first serial, iclass 16, count 0 2006.196.08:01:19.95#ibcon#enter sib2, iclass 16, count 0 2006.196.08:01:19.95#ibcon#flushed, iclass 16, count 0 2006.196.08:01:19.95#ibcon#about to write, iclass 16, count 0 2006.196.08:01:19.95#ibcon#wrote, iclass 16, count 0 2006.196.08:01:19.95#ibcon#about to read 3, iclass 16, count 0 2006.196.08:01:19.97#ibcon#read 3, iclass 16, count 0 2006.196.08:01:19.97#ibcon#about to read 4, iclass 16, count 0 2006.196.08:01:19.97#ibcon#read 4, iclass 16, count 0 2006.196.08:01:19.97#ibcon#about to read 5, iclass 16, count 0 2006.196.08:01:19.97#ibcon#read 5, iclass 16, count 0 2006.196.08:01:19.97#ibcon#about to read 6, iclass 16, count 0 2006.196.08:01:19.97#ibcon#read 6, iclass 16, count 0 2006.196.08:01:19.97#ibcon#end of sib2, iclass 16, count 0 2006.196.08:01:19.97#ibcon#*mode == 0, iclass 16, count 0 2006.196.08:01:19.97#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.196.08:01:19.97#ibcon#[26=FRQ=07,832.99\r\n] 2006.196.08:01:19.97#ibcon#*before write, iclass 16, count 0 2006.196.08:01:19.97#ibcon#enter sib2, iclass 16, count 0 2006.196.08:01:19.97#ibcon#flushed, iclass 16, count 0 2006.196.08:01:19.97#ibcon#about to write, iclass 16, count 0 2006.196.08:01:19.97#ibcon#wrote, iclass 16, count 0 2006.196.08:01:19.97#ibcon#about to read 3, iclass 16, count 0 2006.196.08:01:20.01#ibcon#read 3, iclass 16, count 0 2006.196.08:01:20.01#ibcon#about to read 4, iclass 16, count 0 2006.196.08:01:20.01#ibcon#read 4, iclass 16, count 0 2006.196.08:01:20.01#ibcon#about to read 5, iclass 16, count 0 2006.196.08:01:20.01#ibcon#read 5, iclass 16, count 0 2006.196.08:01:20.01#ibcon#about to read 6, iclass 16, count 0 2006.196.08:01:20.01#ibcon#read 6, iclass 16, count 0 2006.196.08:01:20.01#ibcon#end of sib2, iclass 16, count 0 2006.196.08:01:20.01#ibcon#*after write, iclass 16, count 0 2006.196.08:01:20.01#ibcon#*before return 0, iclass 16, count 0 2006.196.08:01:20.01#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.196.08:01:20.01#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.196.08:01:20.01#ibcon#about to clear, iclass 16 cls_cnt 0 2006.196.08:01:20.01#ibcon#cleared, iclass 16 cls_cnt 0 2006.196.08:01:20.01$vc4f8/va=7,6 2006.196.08:01:20.01#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.196.08:01:20.01#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.196.08:01:20.01#ibcon#ireg 11 cls_cnt 2 2006.196.08:01:20.01#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.196.08:01:20.07#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.196.08:01:20.07#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.196.08:01:20.07#ibcon#enter wrdev, iclass 18, count 2 2006.196.08:01:20.07#ibcon#first serial, iclass 18, count 2 2006.196.08:01:20.07#ibcon#enter sib2, iclass 18, count 2 2006.196.08:01:20.07#ibcon#flushed, iclass 18, count 2 2006.196.08:01:20.07#ibcon#about to write, iclass 18, count 2 2006.196.08:01:20.07#ibcon#wrote, iclass 18, count 2 2006.196.08:01:20.07#ibcon#about to read 3, iclass 18, count 2 2006.196.08:01:20.09#ibcon#read 3, iclass 18, count 2 2006.196.08:01:20.09#ibcon#about to read 4, iclass 18, count 2 2006.196.08:01:20.09#ibcon#read 4, iclass 18, count 2 2006.196.08:01:20.09#ibcon#about to read 5, iclass 18, count 2 2006.196.08:01:20.09#ibcon#read 5, iclass 18, count 2 2006.196.08:01:20.09#ibcon#about to read 6, iclass 18, count 2 2006.196.08:01:20.09#ibcon#read 6, iclass 18, count 2 2006.196.08:01:20.09#ibcon#end of sib2, iclass 18, count 2 2006.196.08:01:20.09#ibcon#*mode == 0, iclass 18, count 2 2006.196.08:01:20.09#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.196.08:01:20.09#ibcon#[25=AT07-06\r\n] 2006.196.08:01:20.09#ibcon#*before write, iclass 18, count 2 2006.196.08:01:20.09#ibcon#enter sib2, iclass 18, count 2 2006.196.08:01:20.09#ibcon#flushed, iclass 18, count 2 2006.196.08:01:20.09#ibcon#about to write, iclass 18, count 2 2006.196.08:01:20.09#ibcon#wrote, iclass 18, count 2 2006.196.08:01:20.09#ibcon#about to read 3, iclass 18, count 2 2006.196.08:01:20.12#ibcon#read 3, iclass 18, count 2 2006.196.08:01:20.12#ibcon#about to read 4, iclass 18, count 2 2006.196.08:01:20.12#ibcon#read 4, iclass 18, count 2 2006.196.08:01:20.12#ibcon#about to read 5, iclass 18, count 2 2006.196.08:01:20.12#ibcon#read 5, iclass 18, count 2 2006.196.08:01:20.12#ibcon#about to read 6, iclass 18, count 2 2006.196.08:01:20.12#ibcon#read 6, iclass 18, count 2 2006.196.08:01:20.12#ibcon#end of sib2, iclass 18, count 2 2006.196.08:01:20.12#ibcon#*after write, iclass 18, count 2 2006.196.08:01:20.12#ibcon#*before return 0, iclass 18, count 2 2006.196.08:01:20.12#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.196.08:01:20.12#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.196.08:01:20.12#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.196.08:01:20.12#ibcon#ireg 7 cls_cnt 0 2006.196.08:01:20.12#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.196.08:01:20.24#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.196.08:01:20.24#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.196.08:01:20.24#ibcon#enter wrdev, iclass 18, count 0 2006.196.08:01:20.24#ibcon#first serial, iclass 18, count 0 2006.196.08:01:20.24#ibcon#enter sib2, iclass 18, count 0 2006.196.08:01:20.24#ibcon#flushed, iclass 18, count 0 2006.196.08:01:20.24#ibcon#about to write, iclass 18, count 0 2006.196.08:01:20.24#ibcon#wrote, iclass 18, count 0 2006.196.08:01:20.24#ibcon#about to read 3, iclass 18, count 0 2006.196.08:01:20.26#ibcon#read 3, iclass 18, count 0 2006.196.08:01:20.26#ibcon#about to read 4, iclass 18, count 0 2006.196.08:01:20.26#ibcon#read 4, iclass 18, count 0 2006.196.08:01:20.26#ibcon#about to read 5, iclass 18, count 0 2006.196.08:01:20.26#ibcon#read 5, iclass 18, count 0 2006.196.08:01:20.26#ibcon#about to read 6, iclass 18, count 0 2006.196.08:01:20.26#ibcon#read 6, iclass 18, count 0 2006.196.08:01:20.26#ibcon#end of sib2, iclass 18, count 0 2006.196.08:01:20.26#ibcon#*mode == 0, iclass 18, count 0 2006.196.08:01:20.26#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.196.08:01:20.26#ibcon#[25=USB\r\n] 2006.196.08:01:20.26#ibcon#*before write, iclass 18, count 0 2006.196.08:01:20.26#ibcon#enter sib2, iclass 18, count 0 2006.196.08:01:20.26#ibcon#flushed, iclass 18, count 0 2006.196.08:01:20.26#ibcon#about to write, iclass 18, count 0 2006.196.08:01:20.26#ibcon#wrote, iclass 18, count 0 2006.196.08:01:20.26#ibcon#about to read 3, iclass 18, count 0 2006.196.08:01:20.29#ibcon#read 3, iclass 18, count 0 2006.196.08:01:20.29#ibcon#about to read 4, iclass 18, count 0 2006.196.08:01:20.29#ibcon#read 4, iclass 18, count 0 2006.196.08:01:20.29#ibcon#about to read 5, iclass 18, count 0 2006.196.08:01:20.29#ibcon#read 5, iclass 18, count 0 2006.196.08:01:20.29#ibcon#about to read 6, iclass 18, count 0 2006.196.08:01:20.29#ibcon#read 6, iclass 18, count 0 2006.196.08:01:20.29#ibcon#end of sib2, iclass 18, count 0 2006.196.08:01:20.29#ibcon#*after write, iclass 18, count 0 2006.196.08:01:20.29#ibcon#*before return 0, iclass 18, count 0 2006.196.08:01:20.29#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.196.08:01:20.29#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.196.08:01:20.29#ibcon#about to clear, iclass 18 cls_cnt 0 2006.196.08:01:20.29#ibcon#cleared, iclass 18 cls_cnt 0 2006.196.08:01:20.29$vc4f8/valo=8,852.99 2006.196.08:01:20.29#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.196.08:01:20.29#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.196.08:01:20.29#ibcon#ireg 17 cls_cnt 0 2006.196.08:01:20.29#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.196.08:01:20.29#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.196.08:01:20.29#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.196.08:01:20.29#ibcon#enter wrdev, iclass 20, count 0 2006.196.08:01:20.29#ibcon#first serial, iclass 20, count 0 2006.196.08:01:20.29#ibcon#enter sib2, iclass 20, count 0 2006.196.08:01:20.29#ibcon#flushed, iclass 20, count 0 2006.196.08:01:20.29#ibcon#about to write, iclass 20, count 0 2006.196.08:01:20.29#ibcon#wrote, iclass 20, count 0 2006.196.08:01:20.29#ibcon#about to read 3, iclass 20, count 0 2006.196.08:01:20.31#ibcon#read 3, iclass 20, count 0 2006.196.08:01:20.31#ibcon#about to read 4, iclass 20, count 0 2006.196.08:01:20.31#ibcon#read 4, iclass 20, count 0 2006.196.08:01:20.31#ibcon#about to read 5, iclass 20, count 0 2006.196.08:01:20.31#ibcon#read 5, iclass 20, count 0 2006.196.08:01:20.31#ibcon#about to read 6, iclass 20, count 0 2006.196.08:01:20.31#ibcon#read 6, iclass 20, count 0 2006.196.08:01:20.31#ibcon#end of sib2, iclass 20, count 0 2006.196.08:01:20.31#ibcon#*mode == 0, iclass 20, count 0 2006.196.08:01:20.31#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.196.08:01:20.31#ibcon#[26=FRQ=08,852.99\r\n] 2006.196.08:01:20.31#ibcon#*before write, iclass 20, count 0 2006.196.08:01:20.31#ibcon#enter sib2, iclass 20, count 0 2006.196.08:01:20.31#ibcon#flushed, iclass 20, count 0 2006.196.08:01:20.31#ibcon#about to write, iclass 20, count 0 2006.196.08:01:20.31#ibcon#wrote, iclass 20, count 0 2006.196.08:01:20.31#ibcon#about to read 3, iclass 20, count 0 2006.196.08:01:20.36#ibcon#read 3, iclass 20, count 0 2006.196.08:01:20.36#ibcon#about to read 4, iclass 20, count 0 2006.196.08:01:20.36#ibcon#read 4, iclass 20, count 0 2006.196.08:01:20.36#ibcon#about to read 5, iclass 20, count 0 2006.196.08:01:20.36#ibcon#read 5, iclass 20, count 0 2006.196.08:01:20.36#ibcon#about to read 6, iclass 20, count 0 2006.196.08:01:20.36#ibcon#read 6, iclass 20, count 0 2006.196.08:01:20.36#ibcon#end of sib2, iclass 20, count 0 2006.196.08:01:20.36#ibcon#*after write, iclass 20, count 0 2006.196.08:01:20.36#ibcon#*before return 0, iclass 20, count 0 2006.196.08:01:20.36#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.196.08:01:20.36#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.196.08:01:20.36#ibcon#about to clear, iclass 20 cls_cnt 0 2006.196.08:01:20.36#ibcon#cleared, iclass 20 cls_cnt 0 2006.196.08:01:20.36$vc4f8/va=8,7 2006.196.08:01:20.36#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.196.08:01:20.36#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.196.08:01:20.36#ibcon#ireg 11 cls_cnt 2 2006.196.08:01:20.36#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.196.08:01:20.41#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.196.08:01:20.41#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.196.08:01:20.41#ibcon#enter wrdev, iclass 22, count 2 2006.196.08:01:20.41#ibcon#first serial, iclass 22, count 2 2006.196.08:01:20.41#ibcon#enter sib2, iclass 22, count 2 2006.196.08:01:20.41#ibcon#flushed, iclass 22, count 2 2006.196.08:01:20.41#ibcon#about to write, iclass 22, count 2 2006.196.08:01:20.41#ibcon#wrote, iclass 22, count 2 2006.196.08:01:20.41#ibcon#about to read 3, iclass 22, count 2 2006.196.08:01:20.43#ibcon#read 3, iclass 22, count 2 2006.196.08:01:20.43#ibcon#about to read 4, iclass 22, count 2 2006.196.08:01:20.43#ibcon#read 4, iclass 22, count 2 2006.196.08:01:20.43#ibcon#about to read 5, iclass 22, count 2 2006.196.08:01:20.43#ibcon#read 5, iclass 22, count 2 2006.196.08:01:20.43#ibcon#about to read 6, iclass 22, count 2 2006.196.08:01:20.43#ibcon#read 6, iclass 22, count 2 2006.196.08:01:20.43#ibcon#end of sib2, iclass 22, count 2 2006.196.08:01:20.43#ibcon#*mode == 0, iclass 22, count 2 2006.196.08:01:20.43#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.196.08:01:20.43#ibcon#[25=AT08-07\r\n] 2006.196.08:01:20.43#ibcon#*before write, iclass 22, count 2 2006.196.08:01:20.43#ibcon#enter sib2, iclass 22, count 2 2006.196.08:01:20.43#ibcon#flushed, iclass 22, count 2 2006.196.08:01:20.43#ibcon#about to write, iclass 22, count 2 2006.196.08:01:20.43#ibcon#wrote, iclass 22, count 2 2006.196.08:01:20.43#ibcon#about to read 3, iclass 22, count 2 2006.196.08:01:20.46#ibcon#read 3, iclass 22, count 2 2006.196.08:01:20.46#ibcon#about to read 4, iclass 22, count 2 2006.196.08:01:20.46#ibcon#read 4, iclass 22, count 2 2006.196.08:01:20.46#ibcon#about to read 5, iclass 22, count 2 2006.196.08:01:20.46#ibcon#read 5, iclass 22, count 2 2006.196.08:01:20.46#ibcon#about to read 6, iclass 22, count 2 2006.196.08:01:20.46#ibcon#read 6, iclass 22, count 2 2006.196.08:01:20.46#ibcon#end of sib2, iclass 22, count 2 2006.196.08:01:20.46#ibcon#*after write, iclass 22, count 2 2006.196.08:01:20.46#ibcon#*before return 0, iclass 22, count 2 2006.196.08:01:20.46#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.196.08:01:20.46#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.196.08:01:20.46#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.196.08:01:20.46#ibcon#ireg 7 cls_cnt 0 2006.196.08:01:20.46#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.196.08:01:20.58#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.196.08:01:20.58#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.196.08:01:20.58#ibcon#enter wrdev, iclass 22, count 0 2006.196.08:01:20.58#ibcon#first serial, iclass 22, count 0 2006.196.08:01:20.58#ibcon#enter sib2, iclass 22, count 0 2006.196.08:01:20.58#ibcon#flushed, iclass 22, count 0 2006.196.08:01:20.58#ibcon#about to write, iclass 22, count 0 2006.196.08:01:20.58#ibcon#wrote, iclass 22, count 0 2006.196.08:01:20.58#ibcon#about to read 3, iclass 22, count 0 2006.196.08:01:20.60#ibcon#read 3, iclass 22, count 0 2006.196.08:01:20.60#ibcon#about to read 4, iclass 22, count 0 2006.196.08:01:20.60#ibcon#read 4, iclass 22, count 0 2006.196.08:01:20.60#ibcon#about to read 5, iclass 22, count 0 2006.196.08:01:20.60#ibcon#read 5, iclass 22, count 0 2006.196.08:01:20.60#ibcon#about to read 6, iclass 22, count 0 2006.196.08:01:20.60#ibcon#read 6, iclass 22, count 0 2006.196.08:01:20.60#ibcon#end of sib2, iclass 22, count 0 2006.196.08:01:20.60#ibcon#*mode == 0, iclass 22, count 0 2006.196.08:01:20.60#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.196.08:01:20.60#ibcon#[25=USB\r\n] 2006.196.08:01:20.60#ibcon#*before write, iclass 22, count 0 2006.196.08:01:20.60#ibcon#enter sib2, iclass 22, count 0 2006.196.08:01:20.60#ibcon#flushed, iclass 22, count 0 2006.196.08:01:20.60#ibcon#about to write, iclass 22, count 0 2006.196.08:01:20.60#ibcon#wrote, iclass 22, count 0 2006.196.08:01:20.60#ibcon#about to read 3, iclass 22, count 0 2006.196.08:01:20.63#ibcon#read 3, iclass 22, count 0 2006.196.08:01:20.63#ibcon#about to read 4, iclass 22, count 0 2006.196.08:01:20.63#ibcon#read 4, iclass 22, count 0 2006.196.08:01:20.63#ibcon#about to read 5, iclass 22, count 0 2006.196.08:01:20.63#ibcon#read 5, iclass 22, count 0 2006.196.08:01:20.63#ibcon#about to read 6, iclass 22, count 0 2006.196.08:01:20.63#ibcon#read 6, iclass 22, count 0 2006.196.08:01:20.63#ibcon#end of sib2, iclass 22, count 0 2006.196.08:01:20.63#ibcon#*after write, iclass 22, count 0 2006.196.08:01:20.63#ibcon#*before return 0, iclass 22, count 0 2006.196.08:01:20.63#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.196.08:01:20.63#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.196.08:01:20.63#ibcon#about to clear, iclass 22 cls_cnt 0 2006.196.08:01:20.63#ibcon#cleared, iclass 22 cls_cnt 0 2006.196.08:01:20.63$vc4f8/vblo=1,632.99 2006.196.08:01:20.63#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.196.08:01:20.63#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.196.08:01:20.63#ibcon#ireg 17 cls_cnt 0 2006.196.08:01:20.63#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.196.08:01:20.63#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.196.08:01:20.63#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.196.08:01:20.63#ibcon#enter wrdev, iclass 24, count 0 2006.196.08:01:20.63#ibcon#first serial, iclass 24, count 0 2006.196.08:01:20.63#ibcon#enter sib2, iclass 24, count 0 2006.196.08:01:20.63#ibcon#flushed, iclass 24, count 0 2006.196.08:01:20.63#ibcon#about to write, iclass 24, count 0 2006.196.08:01:20.63#ibcon#wrote, iclass 24, count 0 2006.196.08:01:20.63#ibcon#about to read 3, iclass 24, count 0 2006.196.08:01:20.65#ibcon#read 3, iclass 24, count 0 2006.196.08:01:20.65#ibcon#about to read 4, iclass 24, count 0 2006.196.08:01:20.65#ibcon#read 4, iclass 24, count 0 2006.196.08:01:20.65#ibcon#about to read 5, iclass 24, count 0 2006.196.08:01:20.65#ibcon#read 5, iclass 24, count 0 2006.196.08:01:20.65#ibcon#about to read 6, iclass 24, count 0 2006.196.08:01:20.65#ibcon#read 6, iclass 24, count 0 2006.196.08:01:20.65#ibcon#end of sib2, iclass 24, count 0 2006.196.08:01:20.65#ibcon#*mode == 0, iclass 24, count 0 2006.196.08:01:20.65#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.196.08:01:20.65#ibcon#[28=FRQ=01,632.99\r\n] 2006.196.08:01:20.65#ibcon#*before write, iclass 24, count 0 2006.196.08:01:20.65#ibcon#enter sib2, iclass 24, count 0 2006.196.08:01:20.65#ibcon#flushed, iclass 24, count 0 2006.196.08:01:20.65#ibcon#about to write, iclass 24, count 0 2006.196.08:01:20.65#ibcon#wrote, iclass 24, count 0 2006.196.08:01:20.65#ibcon#about to read 3, iclass 24, count 0 2006.196.08:01:20.69#ibcon#read 3, iclass 24, count 0 2006.196.08:01:20.69#ibcon#about to read 4, iclass 24, count 0 2006.196.08:01:20.69#ibcon#read 4, iclass 24, count 0 2006.196.08:01:20.69#ibcon#about to read 5, iclass 24, count 0 2006.196.08:01:20.69#ibcon#read 5, iclass 24, count 0 2006.196.08:01:20.69#ibcon#about to read 6, iclass 24, count 0 2006.196.08:01:20.69#ibcon#read 6, iclass 24, count 0 2006.196.08:01:20.69#ibcon#end of sib2, iclass 24, count 0 2006.196.08:01:20.69#ibcon#*after write, iclass 24, count 0 2006.196.08:01:20.69#ibcon#*before return 0, iclass 24, count 0 2006.196.08:01:20.69#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.196.08:01:20.69#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.196.08:01:20.69#ibcon#about to clear, iclass 24 cls_cnt 0 2006.196.08:01:20.69#ibcon#cleared, iclass 24 cls_cnt 0 2006.196.08:01:20.69$vc4f8/vb=1,4 2006.196.08:01:20.69#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.196.08:01:20.69#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.196.08:01:20.69#ibcon#ireg 11 cls_cnt 2 2006.196.08:01:20.69#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.196.08:01:20.69#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.196.08:01:20.69#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.196.08:01:20.69#ibcon#enter wrdev, iclass 26, count 2 2006.196.08:01:20.69#ibcon#first serial, iclass 26, count 2 2006.196.08:01:20.69#ibcon#enter sib2, iclass 26, count 2 2006.196.08:01:20.69#ibcon#flushed, iclass 26, count 2 2006.196.08:01:20.69#ibcon#about to write, iclass 26, count 2 2006.196.08:01:20.69#ibcon#wrote, iclass 26, count 2 2006.196.08:01:20.69#ibcon#about to read 3, iclass 26, count 2 2006.196.08:01:20.71#ibcon#read 3, iclass 26, count 2 2006.196.08:01:20.71#ibcon#about to read 4, iclass 26, count 2 2006.196.08:01:20.71#ibcon#read 4, iclass 26, count 2 2006.196.08:01:20.71#ibcon#about to read 5, iclass 26, count 2 2006.196.08:01:20.71#ibcon#read 5, iclass 26, count 2 2006.196.08:01:20.71#ibcon#about to read 6, iclass 26, count 2 2006.196.08:01:20.71#ibcon#read 6, iclass 26, count 2 2006.196.08:01:20.71#ibcon#end of sib2, iclass 26, count 2 2006.196.08:01:20.71#ibcon#*mode == 0, iclass 26, count 2 2006.196.08:01:20.71#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.196.08:01:20.71#ibcon#[27=AT01-04\r\n] 2006.196.08:01:20.71#ibcon#*before write, iclass 26, count 2 2006.196.08:01:20.71#ibcon#enter sib2, iclass 26, count 2 2006.196.08:01:20.71#ibcon#flushed, iclass 26, count 2 2006.196.08:01:20.71#ibcon#about to write, iclass 26, count 2 2006.196.08:01:20.71#ibcon#wrote, iclass 26, count 2 2006.196.08:01:20.71#ibcon#about to read 3, iclass 26, count 2 2006.196.08:01:20.74#ibcon#read 3, iclass 26, count 2 2006.196.08:01:20.74#ibcon#about to read 4, iclass 26, count 2 2006.196.08:01:20.74#ibcon#read 4, iclass 26, count 2 2006.196.08:01:20.74#ibcon#about to read 5, iclass 26, count 2 2006.196.08:01:20.74#ibcon#read 5, iclass 26, count 2 2006.196.08:01:20.74#ibcon#about to read 6, iclass 26, count 2 2006.196.08:01:20.74#ibcon#read 6, iclass 26, count 2 2006.196.08:01:20.74#ibcon#end of sib2, iclass 26, count 2 2006.196.08:01:20.74#ibcon#*after write, iclass 26, count 2 2006.196.08:01:20.74#ibcon#*before return 0, iclass 26, count 2 2006.196.08:01:20.74#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.196.08:01:20.74#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.196.08:01:20.74#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.196.08:01:20.74#ibcon#ireg 7 cls_cnt 0 2006.196.08:01:20.74#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.196.08:01:20.86#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.196.08:01:20.86#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.196.08:01:20.86#ibcon#enter wrdev, iclass 26, count 0 2006.196.08:01:20.86#ibcon#first serial, iclass 26, count 0 2006.196.08:01:20.86#ibcon#enter sib2, iclass 26, count 0 2006.196.08:01:20.86#ibcon#flushed, iclass 26, count 0 2006.196.08:01:20.86#ibcon#about to write, iclass 26, count 0 2006.196.08:01:20.86#ibcon#wrote, iclass 26, count 0 2006.196.08:01:20.86#ibcon#about to read 3, iclass 26, count 0 2006.196.08:01:20.88#ibcon#read 3, iclass 26, count 0 2006.196.08:01:20.88#ibcon#about to read 4, iclass 26, count 0 2006.196.08:01:20.88#ibcon#read 4, iclass 26, count 0 2006.196.08:01:20.88#ibcon#about to read 5, iclass 26, count 0 2006.196.08:01:20.88#ibcon#read 5, iclass 26, count 0 2006.196.08:01:20.88#ibcon#about to read 6, iclass 26, count 0 2006.196.08:01:20.88#ibcon#read 6, iclass 26, count 0 2006.196.08:01:20.88#ibcon#end of sib2, iclass 26, count 0 2006.196.08:01:20.88#ibcon#*mode == 0, iclass 26, count 0 2006.196.08:01:20.88#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.196.08:01:20.88#ibcon#[27=USB\r\n] 2006.196.08:01:20.88#ibcon#*before write, iclass 26, count 0 2006.196.08:01:20.88#ibcon#enter sib2, iclass 26, count 0 2006.196.08:01:20.88#ibcon#flushed, iclass 26, count 0 2006.196.08:01:20.88#ibcon#about to write, iclass 26, count 0 2006.196.08:01:20.88#ibcon#wrote, iclass 26, count 0 2006.196.08:01:20.88#ibcon#about to read 3, iclass 26, count 0 2006.196.08:01:20.91#ibcon#read 3, iclass 26, count 0 2006.196.08:01:20.91#ibcon#about to read 4, iclass 26, count 0 2006.196.08:01:20.91#ibcon#read 4, iclass 26, count 0 2006.196.08:01:20.91#ibcon#about to read 5, iclass 26, count 0 2006.196.08:01:20.91#ibcon#read 5, iclass 26, count 0 2006.196.08:01:20.91#ibcon#about to read 6, iclass 26, count 0 2006.196.08:01:20.91#ibcon#read 6, iclass 26, count 0 2006.196.08:01:20.91#ibcon#end of sib2, iclass 26, count 0 2006.196.08:01:20.91#ibcon#*after write, iclass 26, count 0 2006.196.08:01:20.91#ibcon#*before return 0, iclass 26, count 0 2006.196.08:01:20.91#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.196.08:01:20.91#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.196.08:01:20.91#ibcon#about to clear, iclass 26 cls_cnt 0 2006.196.08:01:20.91#ibcon#cleared, iclass 26 cls_cnt 0 2006.196.08:01:20.91$vc4f8/vblo=2,640.99 2006.196.08:01:20.91#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.196.08:01:20.91#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.196.08:01:20.91#ibcon#ireg 17 cls_cnt 0 2006.196.08:01:20.91#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.196.08:01:20.91#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.196.08:01:20.91#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.196.08:01:20.91#ibcon#enter wrdev, iclass 28, count 0 2006.196.08:01:20.91#ibcon#first serial, iclass 28, count 0 2006.196.08:01:20.91#ibcon#enter sib2, iclass 28, count 0 2006.196.08:01:20.91#ibcon#flushed, iclass 28, count 0 2006.196.08:01:20.91#ibcon#about to write, iclass 28, count 0 2006.196.08:01:20.91#ibcon#wrote, iclass 28, count 0 2006.196.08:01:20.91#ibcon#about to read 3, iclass 28, count 0 2006.196.08:01:20.93#ibcon#read 3, iclass 28, count 0 2006.196.08:01:20.93#ibcon#about to read 4, iclass 28, count 0 2006.196.08:01:20.93#ibcon#read 4, iclass 28, count 0 2006.196.08:01:20.93#ibcon#about to read 5, iclass 28, count 0 2006.196.08:01:20.93#ibcon#read 5, iclass 28, count 0 2006.196.08:01:20.93#ibcon#about to read 6, iclass 28, count 0 2006.196.08:01:20.93#ibcon#read 6, iclass 28, count 0 2006.196.08:01:20.93#ibcon#end of sib2, iclass 28, count 0 2006.196.08:01:20.93#ibcon#*mode == 0, iclass 28, count 0 2006.196.08:01:20.93#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.196.08:01:20.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.196.08:01:20.93#ibcon#*before write, iclass 28, count 0 2006.196.08:01:20.93#ibcon#enter sib2, iclass 28, count 0 2006.196.08:01:20.93#ibcon#flushed, iclass 28, count 0 2006.196.08:01:20.93#ibcon#about to write, iclass 28, count 0 2006.196.08:01:20.93#ibcon#wrote, iclass 28, count 0 2006.196.08:01:20.93#ibcon#about to read 3, iclass 28, count 0 2006.196.08:01:20.97#ibcon#read 3, iclass 28, count 0 2006.196.08:01:20.97#ibcon#about to read 4, iclass 28, count 0 2006.196.08:01:20.97#ibcon#read 4, iclass 28, count 0 2006.196.08:01:20.97#ibcon#about to read 5, iclass 28, count 0 2006.196.08:01:20.97#ibcon#read 5, iclass 28, count 0 2006.196.08:01:20.97#ibcon#about to read 6, iclass 28, count 0 2006.196.08:01:20.97#ibcon#read 6, iclass 28, count 0 2006.196.08:01:20.97#ibcon#end of sib2, iclass 28, count 0 2006.196.08:01:20.97#ibcon#*after write, iclass 28, count 0 2006.196.08:01:20.97#ibcon#*before return 0, iclass 28, count 0 2006.196.08:01:20.97#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.196.08:01:20.97#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.196.08:01:20.97#ibcon#about to clear, iclass 28 cls_cnt 0 2006.196.08:01:20.97#ibcon#cleared, iclass 28 cls_cnt 0 2006.196.08:01:20.97$vc4f8/vb=2,4 2006.196.08:01:20.97#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.196.08:01:20.97#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.196.08:01:20.97#ibcon#ireg 11 cls_cnt 2 2006.196.08:01:20.97#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.196.08:01:21.03#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.196.08:01:21.03#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.196.08:01:21.03#ibcon#enter wrdev, iclass 30, count 2 2006.196.08:01:21.03#ibcon#first serial, iclass 30, count 2 2006.196.08:01:21.03#ibcon#enter sib2, iclass 30, count 2 2006.196.08:01:21.03#ibcon#flushed, iclass 30, count 2 2006.196.08:01:21.03#ibcon#about to write, iclass 30, count 2 2006.196.08:01:21.03#ibcon#wrote, iclass 30, count 2 2006.196.08:01:21.03#ibcon#about to read 3, iclass 30, count 2 2006.196.08:01:21.05#ibcon#read 3, iclass 30, count 2 2006.196.08:01:21.05#ibcon#about to read 4, iclass 30, count 2 2006.196.08:01:21.05#ibcon#read 4, iclass 30, count 2 2006.196.08:01:21.05#ibcon#about to read 5, iclass 30, count 2 2006.196.08:01:21.05#ibcon#read 5, iclass 30, count 2 2006.196.08:01:21.05#ibcon#about to read 6, iclass 30, count 2 2006.196.08:01:21.05#ibcon#read 6, iclass 30, count 2 2006.196.08:01:21.05#ibcon#end of sib2, iclass 30, count 2 2006.196.08:01:21.05#ibcon#*mode == 0, iclass 30, count 2 2006.196.08:01:21.05#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.196.08:01:21.05#ibcon#[27=AT02-04\r\n] 2006.196.08:01:21.05#ibcon#*before write, iclass 30, count 2 2006.196.08:01:21.05#ibcon#enter sib2, iclass 30, count 2 2006.196.08:01:21.05#ibcon#flushed, iclass 30, count 2 2006.196.08:01:21.05#ibcon#about to write, iclass 30, count 2 2006.196.08:01:21.05#ibcon#wrote, iclass 30, count 2 2006.196.08:01:21.05#ibcon#about to read 3, iclass 30, count 2 2006.196.08:01:21.08#ibcon#read 3, iclass 30, count 2 2006.196.08:01:21.08#ibcon#about to read 4, iclass 30, count 2 2006.196.08:01:21.08#ibcon#read 4, iclass 30, count 2 2006.196.08:01:21.08#ibcon#about to read 5, iclass 30, count 2 2006.196.08:01:21.08#ibcon#read 5, iclass 30, count 2 2006.196.08:01:21.08#ibcon#about to read 6, iclass 30, count 2 2006.196.08:01:21.08#ibcon#read 6, iclass 30, count 2 2006.196.08:01:21.08#ibcon#end of sib2, iclass 30, count 2 2006.196.08:01:21.08#ibcon#*after write, iclass 30, count 2 2006.196.08:01:21.08#ibcon#*before return 0, iclass 30, count 2 2006.196.08:01:21.08#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.196.08:01:21.08#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.196.08:01:21.08#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.196.08:01:21.08#ibcon#ireg 7 cls_cnt 0 2006.196.08:01:21.08#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.196.08:01:21.20#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.196.08:01:21.20#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.196.08:01:21.20#ibcon#enter wrdev, iclass 30, count 0 2006.196.08:01:21.20#ibcon#first serial, iclass 30, count 0 2006.196.08:01:21.20#ibcon#enter sib2, iclass 30, count 0 2006.196.08:01:21.20#ibcon#flushed, iclass 30, count 0 2006.196.08:01:21.20#ibcon#about to write, iclass 30, count 0 2006.196.08:01:21.20#ibcon#wrote, iclass 30, count 0 2006.196.08:01:21.20#ibcon#about to read 3, iclass 30, count 0 2006.196.08:01:21.22#ibcon#read 3, iclass 30, count 0 2006.196.08:01:21.22#ibcon#about to read 4, iclass 30, count 0 2006.196.08:01:21.22#ibcon#read 4, iclass 30, count 0 2006.196.08:01:21.22#ibcon#about to read 5, iclass 30, count 0 2006.196.08:01:21.22#ibcon#read 5, iclass 30, count 0 2006.196.08:01:21.22#ibcon#about to read 6, iclass 30, count 0 2006.196.08:01:21.22#ibcon#read 6, iclass 30, count 0 2006.196.08:01:21.22#ibcon#end of sib2, iclass 30, count 0 2006.196.08:01:21.22#ibcon#*mode == 0, iclass 30, count 0 2006.196.08:01:21.22#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.196.08:01:21.22#ibcon#[27=USB\r\n] 2006.196.08:01:21.22#ibcon#*before write, iclass 30, count 0 2006.196.08:01:21.22#ibcon#enter sib2, iclass 30, count 0 2006.196.08:01:21.22#ibcon#flushed, iclass 30, count 0 2006.196.08:01:21.22#ibcon#about to write, iclass 30, count 0 2006.196.08:01:21.22#ibcon#wrote, iclass 30, count 0 2006.196.08:01:21.22#ibcon#about to read 3, iclass 30, count 0 2006.196.08:01:21.25#ibcon#read 3, iclass 30, count 0 2006.196.08:01:21.25#ibcon#about to read 4, iclass 30, count 0 2006.196.08:01:21.25#ibcon#read 4, iclass 30, count 0 2006.196.08:01:21.25#ibcon#about to read 5, iclass 30, count 0 2006.196.08:01:21.25#ibcon#read 5, iclass 30, count 0 2006.196.08:01:21.25#ibcon#about to read 6, iclass 30, count 0 2006.196.08:01:21.25#ibcon#read 6, iclass 30, count 0 2006.196.08:01:21.25#ibcon#end of sib2, iclass 30, count 0 2006.196.08:01:21.25#ibcon#*after write, iclass 30, count 0 2006.196.08:01:21.25#ibcon#*before return 0, iclass 30, count 0 2006.196.08:01:21.25#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.196.08:01:21.25#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.196.08:01:21.25#ibcon#about to clear, iclass 30 cls_cnt 0 2006.196.08:01:21.25#ibcon#cleared, iclass 30 cls_cnt 0 2006.196.08:01:21.25$vc4f8/vblo=3,656.99 2006.196.08:01:21.25#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.196.08:01:21.25#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.196.08:01:21.25#ibcon#ireg 17 cls_cnt 0 2006.196.08:01:21.25#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.196.08:01:21.25#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.196.08:01:21.25#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.196.08:01:21.25#ibcon#enter wrdev, iclass 32, count 0 2006.196.08:01:21.25#ibcon#first serial, iclass 32, count 0 2006.196.08:01:21.25#ibcon#enter sib2, iclass 32, count 0 2006.196.08:01:21.25#ibcon#flushed, iclass 32, count 0 2006.196.08:01:21.25#ibcon#about to write, iclass 32, count 0 2006.196.08:01:21.25#ibcon#wrote, iclass 32, count 0 2006.196.08:01:21.25#ibcon#about to read 3, iclass 32, count 0 2006.196.08:01:21.27#ibcon#read 3, iclass 32, count 0 2006.196.08:01:21.27#ibcon#about to read 4, iclass 32, count 0 2006.196.08:01:21.27#ibcon#read 4, iclass 32, count 0 2006.196.08:01:21.27#ibcon#about to read 5, iclass 32, count 0 2006.196.08:01:21.27#ibcon#read 5, iclass 32, count 0 2006.196.08:01:21.27#ibcon#about to read 6, iclass 32, count 0 2006.196.08:01:21.27#ibcon#read 6, iclass 32, count 0 2006.196.08:01:21.27#ibcon#end of sib2, iclass 32, count 0 2006.196.08:01:21.27#ibcon#*mode == 0, iclass 32, count 0 2006.196.08:01:21.27#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.196.08:01:21.27#ibcon#[28=FRQ=03,656.99\r\n] 2006.196.08:01:21.27#ibcon#*before write, iclass 32, count 0 2006.196.08:01:21.27#ibcon#enter sib2, iclass 32, count 0 2006.196.08:01:21.27#ibcon#flushed, iclass 32, count 0 2006.196.08:01:21.27#ibcon#about to write, iclass 32, count 0 2006.196.08:01:21.27#ibcon#wrote, iclass 32, count 0 2006.196.08:01:21.27#ibcon#about to read 3, iclass 32, count 0 2006.196.08:01:21.31#ibcon#read 3, iclass 32, count 0 2006.196.08:01:21.31#ibcon#about to read 4, iclass 32, count 0 2006.196.08:01:21.31#ibcon#read 4, iclass 32, count 0 2006.196.08:01:21.31#ibcon#about to read 5, iclass 32, count 0 2006.196.08:01:21.31#ibcon#read 5, iclass 32, count 0 2006.196.08:01:21.31#ibcon#about to read 6, iclass 32, count 0 2006.196.08:01:21.31#ibcon#read 6, iclass 32, count 0 2006.196.08:01:21.31#ibcon#end of sib2, iclass 32, count 0 2006.196.08:01:21.31#ibcon#*after write, iclass 32, count 0 2006.196.08:01:21.31#ibcon#*before return 0, iclass 32, count 0 2006.196.08:01:21.31#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.196.08:01:21.31#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.196.08:01:21.31#ibcon#about to clear, iclass 32 cls_cnt 0 2006.196.08:01:21.31#ibcon#cleared, iclass 32 cls_cnt 0 2006.196.08:01:21.31$vc4f8/vb=3,4 2006.196.08:01:21.31#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.196.08:01:21.31#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.196.08:01:21.31#ibcon#ireg 11 cls_cnt 2 2006.196.08:01:21.31#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.196.08:01:21.37#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.196.08:01:21.37#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.196.08:01:21.37#ibcon#enter wrdev, iclass 34, count 2 2006.196.08:01:21.37#ibcon#first serial, iclass 34, count 2 2006.196.08:01:21.37#ibcon#enter sib2, iclass 34, count 2 2006.196.08:01:21.37#ibcon#flushed, iclass 34, count 2 2006.196.08:01:21.37#ibcon#about to write, iclass 34, count 2 2006.196.08:01:21.37#ibcon#wrote, iclass 34, count 2 2006.196.08:01:21.37#ibcon#about to read 3, iclass 34, count 2 2006.196.08:01:21.39#ibcon#read 3, iclass 34, count 2 2006.196.08:01:21.39#ibcon#about to read 4, iclass 34, count 2 2006.196.08:01:21.39#ibcon#read 4, iclass 34, count 2 2006.196.08:01:21.39#ibcon#about to read 5, iclass 34, count 2 2006.196.08:01:21.39#ibcon#read 5, iclass 34, count 2 2006.196.08:01:21.39#ibcon#about to read 6, iclass 34, count 2 2006.196.08:01:21.39#ibcon#read 6, iclass 34, count 2 2006.196.08:01:21.39#ibcon#end of sib2, iclass 34, count 2 2006.196.08:01:21.39#ibcon#*mode == 0, iclass 34, count 2 2006.196.08:01:21.39#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.196.08:01:21.39#ibcon#[27=AT03-04\r\n] 2006.196.08:01:21.39#ibcon#*before write, iclass 34, count 2 2006.196.08:01:21.39#ibcon#enter sib2, iclass 34, count 2 2006.196.08:01:21.39#ibcon#flushed, iclass 34, count 2 2006.196.08:01:21.39#ibcon#about to write, iclass 34, count 2 2006.196.08:01:21.39#ibcon#wrote, iclass 34, count 2 2006.196.08:01:21.39#ibcon#about to read 3, iclass 34, count 2 2006.196.08:01:21.42#ibcon#read 3, iclass 34, count 2 2006.196.08:01:21.42#ibcon#about to read 4, iclass 34, count 2 2006.196.08:01:21.42#ibcon#read 4, iclass 34, count 2 2006.196.08:01:21.42#ibcon#about to read 5, iclass 34, count 2 2006.196.08:01:21.42#ibcon#read 5, iclass 34, count 2 2006.196.08:01:21.42#ibcon#about to read 6, iclass 34, count 2 2006.196.08:01:21.42#ibcon#read 6, iclass 34, count 2 2006.196.08:01:21.42#ibcon#end of sib2, iclass 34, count 2 2006.196.08:01:21.42#ibcon#*after write, iclass 34, count 2 2006.196.08:01:21.42#ibcon#*before return 0, iclass 34, count 2 2006.196.08:01:21.42#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.196.08:01:21.42#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.196.08:01:21.42#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.196.08:01:21.42#ibcon#ireg 7 cls_cnt 0 2006.196.08:01:21.42#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.196.08:01:21.54#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.196.08:01:21.54#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.196.08:01:21.54#ibcon#enter wrdev, iclass 34, count 0 2006.196.08:01:21.54#ibcon#first serial, iclass 34, count 0 2006.196.08:01:21.54#ibcon#enter sib2, iclass 34, count 0 2006.196.08:01:21.54#ibcon#flushed, iclass 34, count 0 2006.196.08:01:21.54#ibcon#about to write, iclass 34, count 0 2006.196.08:01:21.54#ibcon#wrote, iclass 34, count 0 2006.196.08:01:21.54#ibcon#about to read 3, iclass 34, count 0 2006.196.08:01:21.56#ibcon#read 3, iclass 34, count 0 2006.196.08:01:21.56#ibcon#about to read 4, iclass 34, count 0 2006.196.08:01:21.56#ibcon#read 4, iclass 34, count 0 2006.196.08:01:21.56#ibcon#about to read 5, iclass 34, count 0 2006.196.08:01:21.56#ibcon#read 5, iclass 34, count 0 2006.196.08:01:21.56#ibcon#about to read 6, iclass 34, count 0 2006.196.08:01:21.56#ibcon#read 6, iclass 34, count 0 2006.196.08:01:21.56#ibcon#end of sib2, iclass 34, count 0 2006.196.08:01:21.56#ibcon#*mode == 0, iclass 34, count 0 2006.196.08:01:21.56#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.196.08:01:21.56#ibcon#[27=USB\r\n] 2006.196.08:01:21.56#ibcon#*before write, iclass 34, count 0 2006.196.08:01:21.56#ibcon#enter sib2, iclass 34, count 0 2006.196.08:01:21.56#ibcon#flushed, iclass 34, count 0 2006.196.08:01:21.56#ibcon#about to write, iclass 34, count 0 2006.196.08:01:21.56#ibcon#wrote, iclass 34, count 0 2006.196.08:01:21.56#ibcon#about to read 3, iclass 34, count 0 2006.196.08:01:21.59#ibcon#read 3, iclass 34, count 0 2006.196.08:01:21.59#ibcon#about to read 4, iclass 34, count 0 2006.196.08:01:21.59#ibcon#read 4, iclass 34, count 0 2006.196.08:01:21.59#ibcon#about to read 5, iclass 34, count 0 2006.196.08:01:21.59#ibcon#read 5, iclass 34, count 0 2006.196.08:01:21.59#ibcon#about to read 6, iclass 34, count 0 2006.196.08:01:21.59#ibcon#read 6, iclass 34, count 0 2006.196.08:01:21.59#ibcon#end of sib2, iclass 34, count 0 2006.196.08:01:21.59#ibcon#*after write, iclass 34, count 0 2006.196.08:01:21.59#ibcon#*before return 0, iclass 34, count 0 2006.196.08:01:21.59#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.196.08:01:21.59#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.196.08:01:21.59#ibcon#about to clear, iclass 34 cls_cnt 0 2006.196.08:01:21.59#ibcon#cleared, iclass 34 cls_cnt 0 2006.196.08:01:21.59$vc4f8/vblo=4,712.99 2006.196.08:01:21.59#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.196.08:01:21.59#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.196.08:01:21.59#ibcon#ireg 17 cls_cnt 0 2006.196.08:01:21.59#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.196.08:01:21.59#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.196.08:01:21.59#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.196.08:01:21.59#ibcon#enter wrdev, iclass 36, count 0 2006.196.08:01:21.59#ibcon#first serial, iclass 36, count 0 2006.196.08:01:21.59#ibcon#enter sib2, iclass 36, count 0 2006.196.08:01:21.59#ibcon#flushed, iclass 36, count 0 2006.196.08:01:21.59#ibcon#about to write, iclass 36, count 0 2006.196.08:01:21.59#ibcon#wrote, iclass 36, count 0 2006.196.08:01:21.59#ibcon#about to read 3, iclass 36, count 0 2006.196.08:01:21.61#ibcon#read 3, iclass 36, count 0 2006.196.08:01:21.61#ibcon#about to read 4, iclass 36, count 0 2006.196.08:01:21.61#ibcon#read 4, iclass 36, count 0 2006.196.08:01:21.61#ibcon#about to read 5, iclass 36, count 0 2006.196.08:01:21.61#ibcon#read 5, iclass 36, count 0 2006.196.08:01:21.61#ibcon#about to read 6, iclass 36, count 0 2006.196.08:01:21.61#ibcon#read 6, iclass 36, count 0 2006.196.08:01:21.61#ibcon#end of sib2, iclass 36, count 0 2006.196.08:01:21.61#ibcon#*mode == 0, iclass 36, count 0 2006.196.08:01:21.61#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.196.08:01:21.61#ibcon#[28=FRQ=04,712.99\r\n] 2006.196.08:01:21.61#ibcon#*before write, iclass 36, count 0 2006.196.08:01:21.61#ibcon#enter sib2, iclass 36, count 0 2006.196.08:01:21.61#ibcon#flushed, iclass 36, count 0 2006.196.08:01:21.61#ibcon#about to write, iclass 36, count 0 2006.196.08:01:21.61#ibcon#wrote, iclass 36, count 0 2006.196.08:01:21.61#ibcon#about to read 3, iclass 36, count 0 2006.196.08:01:21.65#ibcon#read 3, iclass 36, count 0 2006.196.08:01:21.65#ibcon#about to read 4, iclass 36, count 0 2006.196.08:01:21.65#ibcon#read 4, iclass 36, count 0 2006.196.08:01:21.65#ibcon#about to read 5, iclass 36, count 0 2006.196.08:01:21.65#ibcon#read 5, iclass 36, count 0 2006.196.08:01:21.65#ibcon#about to read 6, iclass 36, count 0 2006.196.08:01:21.65#ibcon#read 6, iclass 36, count 0 2006.196.08:01:21.65#ibcon#end of sib2, iclass 36, count 0 2006.196.08:01:21.65#ibcon#*after write, iclass 36, count 0 2006.196.08:01:21.65#ibcon#*before return 0, iclass 36, count 0 2006.196.08:01:21.65#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.196.08:01:21.65#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.196.08:01:21.65#ibcon#about to clear, iclass 36 cls_cnt 0 2006.196.08:01:21.65#ibcon#cleared, iclass 36 cls_cnt 0 2006.196.08:01:21.65$vc4f8/vb=4,4 2006.196.08:01:21.65#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.196.08:01:21.65#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.196.08:01:21.65#ibcon#ireg 11 cls_cnt 2 2006.196.08:01:21.65#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.196.08:01:21.71#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.196.08:01:21.71#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.196.08:01:21.71#ibcon#enter wrdev, iclass 38, count 2 2006.196.08:01:21.71#ibcon#first serial, iclass 38, count 2 2006.196.08:01:21.71#ibcon#enter sib2, iclass 38, count 2 2006.196.08:01:21.71#ibcon#flushed, iclass 38, count 2 2006.196.08:01:21.71#ibcon#about to write, iclass 38, count 2 2006.196.08:01:21.71#ibcon#wrote, iclass 38, count 2 2006.196.08:01:21.71#ibcon#about to read 3, iclass 38, count 2 2006.196.08:01:21.73#ibcon#read 3, iclass 38, count 2 2006.196.08:01:21.73#ibcon#about to read 4, iclass 38, count 2 2006.196.08:01:21.73#ibcon#read 4, iclass 38, count 2 2006.196.08:01:21.73#ibcon#about to read 5, iclass 38, count 2 2006.196.08:01:21.73#ibcon#read 5, iclass 38, count 2 2006.196.08:01:21.73#ibcon#about to read 6, iclass 38, count 2 2006.196.08:01:21.73#ibcon#read 6, iclass 38, count 2 2006.196.08:01:21.73#ibcon#end of sib2, iclass 38, count 2 2006.196.08:01:21.73#ibcon#*mode == 0, iclass 38, count 2 2006.196.08:01:21.73#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.196.08:01:21.73#ibcon#[27=AT04-04\r\n] 2006.196.08:01:21.73#ibcon#*before write, iclass 38, count 2 2006.196.08:01:21.73#ibcon#enter sib2, iclass 38, count 2 2006.196.08:01:21.73#ibcon#flushed, iclass 38, count 2 2006.196.08:01:21.73#ibcon#about to write, iclass 38, count 2 2006.196.08:01:21.73#ibcon#wrote, iclass 38, count 2 2006.196.08:01:21.73#ibcon#about to read 3, iclass 38, count 2 2006.196.08:01:21.76#ibcon#read 3, iclass 38, count 2 2006.196.08:01:21.76#ibcon#about to read 4, iclass 38, count 2 2006.196.08:01:21.76#ibcon#read 4, iclass 38, count 2 2006.196.08:01:21.76#ibcon#about to read 5, iclass 38, count 2 2006.196.08:01:21.76#ibcon#read 5, iclass 38, count 2 2006.196.08:01:21.76#ibcon#about to read 6, iclass 38, count 2 2006.196.08:01:21.76#ibcon#read 6, iclass 38, count 2 2006.196.08:01:21.76#ibcon#end of sib2, iclass 38, count 2 2006.196.08:01:21.76#ibcon#*after write, iclass 38, count 2 2006.196.08:01:21.76#ibcon#*before return 0, iclass 38, count 2 2006.196.08:01:21.76#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.196.08:01:21.76#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.196.08:01:21.76#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.196.08:01:21.76#ibcon#ireg 7 cls_cnt 0 2006.196.08:01:21.76#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.196.08:01:21.88#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.196.08:01:21.88#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.196.08:01:21.88#ibcon#enter wrdev, iclass 38, count 0 2006.196.08:01:21.88#ibcon#first serial, iclass 38, count 0 2006.196.08:01:21.88#ibcon#enter sib2, iclass 38, count 0 2006.196.08:01:21.88#ibcon#flushed, iclass 38, count 0 2006.196.08:01:21.88#ibcon#about to write, iclass 38, count 0 2006.196.08:01:21.88#ibcon#wrote, iclass 38, count 0 2006.196.08:01:21.88#ibcon#about to read 3, iclass 38, count 0 2006.196.08:01:21.90#ibcon#read 3, iclass 38, count 0 2006.196.08:01:21.90#ibcon#about to read 4, iclass 38, count 0 2006.196.08:01:21.90#ibcon#read 4, iclass 38, count 0 2006.196.08:01:21.90#ibcon#about to read 5, iclass 38, count 0 2006.196.08:01:21.90#ibcon#read 5, iclass 38, count 0 2006.196.08:01:21.90#ibcon#about to read 6, iclass 38, count 0 2006.196.08:01:21.90#ibcon#read 6, iclass 38, count 0 2006.196.08:01:21.90#ibcon#end of sib2, iclass 38, count 0 2006.196.08:01:21.90#ibcon#*mode == 0, iclass 38, count 0 2006.196.08:01:21.90#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.196.08:01:21.90#ibcon#[27=USB\r\n] 2006.196.08:01:21.90#ibcon#*before write, iclass 38, count 0 2006.196.08:01:21.90#ibcon#enter sib2, iclass 38, count 0 2006.196.08:01:21.90#ibcon#flushed, iclass 38, count 0 2006.196.08:01:21.90#ibcon#about to write, iclass 38, count 0 2006.196.08:01:21.90#ibcon#wrote, iclass 38, count 0 2006.196.08:01:21.90#ibcon#about to read 3, iclass 38, count 0 2006.196.08:01:21.93#ibcon#read 3, iclass 38, count 0 2006.196.08:01:21.93#ibcon#about to read 4, iclass 38, count 0 2006.196.08:01:21.93#ibcon#read 4, iclass 38, count 0 2006.196.08:01:21.93#ibcon#about to read 5, iclass 38, count 0 2006.196.08:01:21.93#ibcon#read 5, iclass 38, count 0 2006.196.08:01:21.93#ibcon#about to read 6, iclass 38, count 0 2006.196.08:01:21.93#ibcon#read 6, iclass 38, count 0 2006.196.08:01:21.93#ibcon#end of sib2, iclass 38, count 0 2006.196.08:01:21.93#ibcon#*after write, iclass 38, count 0 2006.196.08:01:21.93#ibcon#*before return 0, iclass 38, count 0 2006.196.08:01:21.93#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.196.08:01:21.93#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.196.08:01:21.93#ibcon#about to clear, iclass 38 cls_cnt 0 2006.196.08:01:21.93#ibcon#cleared, iclass 38 cls_cnt 0 2006.196.08:01:21.93$vc4f8/vblo=5,744.99 2006.196.08:01:21.93#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.196.08:01:21.93#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.196.08:01:21.93#ibcon#ireg 17 cls_cnt 0 2006.196.08:01:21.93#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.196.08:01:21.93#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.196.08:01:21.93#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.196.08:01:21.93#ibcon#enter wrdev, iclass 40, count 0 2006.196.08:01:21.93#ibcon#first serial, iclass 40, count 0 2006.196.08:01:21.93#ibcon#enter sib2, iclass 40, count 0 2006.196.08:01:21.93#ibcon#flushed, iclass 40, count 0 2006.196.08:01:21.93#ibcon#about to write, iclass 40, count 0 2006.196.08:01:21.93#ibcon#wrote, iclass 40, count 0 2006.196.08:01:21.93#ibcon#about to read 3, iclass 40, count 0 2006.196.08:01:21.95#ibcon#read 3, iclass 40, count 0 2006.196.08:01:21.95#ibcon#about to read 4, iclass 40, count 0 2006.196.08:01:21.95#ibcon#read 4, iclass 40, count 0 2006.196.08:01:21.95#ibcon#about to read 5, iclass 40, count 0 2006.196.08:01:21.95#ibcon#read 5, iclass 40, count 0 2006.196.08:01:21.95#ibcon#about to read 6, iclass 40, count 0 2006.196.08:01:21.95#ibcon#read 6, iclass 40, count 0 2006.196.08:01:21.95#ibcon#end of sib2, iclass 40, count 0 2006.196.08:01:21.95#ibcon#*mode == 0, iclass 40, count 0 2006.196.08:01:21.95#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.196.08:01:21.95#ibcon#[28=FRQ=05,744.99\r\n] 2006.196.08:01:21.95#ibcon#*before write, iclass 40, count 0 2006.196.08:01:21.95#ibcon#enter sib2, iclass 40, count 0 2006.196.08:01:21.95#ibcon#flushed, iclass 40, count 0 2006.196.08:01:21.95#ibcon#about to write, iclass 40, count 0 2006.196.08:01:21.95#ibcon#wrote, iclass 40, count 0 2006.196.08:01:21.95#ibcon#about to read 3, iclass 40, count 0 2006.196.08:01:22.00#ibcon#read 3, iclass 40, count 0 2006.196.08:01:22.00#ibcon#about to read 4, iclass 40, count 0 2006.196.08:01:22.00#ibcon#read 4, iclass 40, count 0 2006.196.08:01:22.00#ibcon#about to read 5, iclass 40, count 0 2006.196.08:01:22.00#ibcon#read 5, iclass 40, count 0 2006.196.08:01:22.00#ibcon#about to read 6, iclass 40, count 0 2006.196.08:01:22.00#ibcon#read 6, iclass 40, count 0 2006.196.08:01:22.00#ibcon#end of sib2, iclass 40, count 0 2006.196.08:01:22.00#ibcon#*after write, iclass 40, count 0 2006.196.08:01:22.00#ibcon#*before return 0, iclass 40, count 0 2006.196.08:01:22.00#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.196.08:01:22.00#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.196.08:01:22.00#ibcon#about to clear, iclass 40 cls_cnt 0 2006.196.08:01:22.00#ibcon#cleared, iclass 40 cls_cnt 0 2006.196.08:01:22.00$vc4f8/vb=5,4 2006.196.08:01:22.00#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.196.08:01:22.00#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.196.08:01:22.00#ibcon#ireg 11 cls_cnt 2 2006.196.08:01:22.00#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.196.08:01:22.05#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.196.08:01:22.05#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.196.08:01:22.05#ibcon#enter wrdev, iclass 4, count 2 2006.196.08:01:22.05#ibcon#first serial, iclass 4, count 2 2006.196.08:01:22.05#ibcon#enter sib2, iclass 4, count 2 2006.196.08:01:22.05#ibcon#flushed, iclass 4, count 2 2006.196.08:01:22.05#ibcon#about to write, iclass 4, count 2 2006.196.08:01:22.05#ibcon#wrote, iclass 4, count 2 2006.196.08:01:22.05#ibcon#about to read 3, iclass 4, count 2 2006.196.08:01:22.07#ibcon#read 3, iclass 4, count 2 2006.196.08:01:22.07#ibcon#about to read 4, iclass 4, count 2 2006.196.08:01:22.07#ibcon#read 4, iclass 4, count 2 2006.196.08:01:22.07#ibcon#about to read 5, iclass 4, count 2 2006.196.08:01:22.07#ibcon#read 5, iclass 4, count 2 2006.196.08:01:22.07#ibcon#about to read 6, iclass 4, count 2 2006.196.08:01:22.07#ibcon#read 6, iclass 4, count 2 2006.196.08:01:22.07#ibcon#end of sib2, iclass 4, count 2 2006.196.08:01:22.07#ibcon#*mode == 0, iclass 4, count 2 2006.196.08:01:22.07#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.196.08:01:22.07#ibcon#[27=AT05-04\r\n] 2006.196.08:01:22.07#ibcon#*before write, iclass 4, count 2 2006.196.08:01:22.07#ibcon#enter sib2, iclass 4, count 2 2006.196.08:01:22.07#ibcon#flushed, iclass 4, count 2 2006.196.08:01:22.07#ibcon#about to write, iclass 4, count 2 2006.196.08:01:22.07#ibcon#wrote, iclass 4, count 2 2006.196.08:01:22.07#ibcon#about to read 3, iclass 4, count 2 2006.196.08:01:22.10#ibcon#read 3, iclass 4, count 2 2006.196.08:01:22.10#ibcon#about to read 4, iclass 4, count 2 2006.196.08:01:22.10#ibcon#read 4, iclass 4, count 2 2006.196.08:01:22.10#ibcon#about to read 5, iclass 4, count 2 2006.196.08:01:22.10#ibcon#read 5, iclass 4, count 2 2006.196.08:01:22.10#ibcon#about to read 6, iclass 4, count 2 2006.196.08:01:22.10#ibcon#read 6, iclass 4, count 2 2006.196.08:01:22.10#ibcon#end of sib2, iclass 4, count 2 2006.196.08:01:22.10#ibcon#*after write, iclass 4, count 2 2006.196.08:01:22.10#ibcon#*before return 0, iclass 4, count 2 2006.196.08:01:22.10#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.196.08:01:22.10#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.196.08:01:22.10#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.196.08:01:22.10#ibcon#ireg 7 cls_cnt 0 2006.196.08:01:22.10#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.196.08:01:22.22#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.196.08:01:22.22#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.196.08:01:22.22#ibcon#enter wrdev, iclass 4, count 0 2006.196.08:01:22.22#ibcon#first serial, iclass 4, count 0 2006.196.08:01:22.22#ibcon#enter sib2, iclass 4, count 0 2006.196.08:01:22.22#ibcon#flushed, iclass 4, count 0 2006.196.08:01:22.22#ibcon#about to write, iclass 4, count 0 2006.196.08:01:22.22#ibcon#wrote, iclass 4, count 0 2006.196.08:01:22.22#ibcon#about to read 3, iclass 4, count 0 2006.196.08:01:22.24#ibcon#read 3, iclass 4, count 0 2006.196.08:01:22.24#ibcon#about to read 4, iclass 4, count 0 2006.196.08:01:22.24#ibcon#read 4, iclass 4, count 0 2006.196.08:01:22.24#ibcon#about to read 5, iclass 4, count 0 2006.196.08:01:22.24#ibcon#read 5, iclass 4, count 0 2006.196.08:01:22.24#ibcon#about to read 6, iclass 4, count 0 2006.196.08:01:22.24#ibcon#read 6, iclass 4, count 0 2006.196.08:01:22.24#ibcon#end of sib2, iclass 4, count 0 2006.196.08:01:22.24#ibcon#*mode == 0, iclass 4, count 0 2006.196.08:01:22.24#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.196.08:01:22.24#ibcon#[27=USB\r\n] 2006.196.08:01:22.24#ibcon#*before write, iclass 4, count 0 2006.196.08:01:22.24#ibcon#enter sib2, iclass 4, count 0 2006.196.08:01:22.24#ibcon#flushed, iclass 4, count 0 2006.196.08:01:22.24#ibcon#about to write, iclass 4, count 0 2006.196.08:01:22.24#ibcon#wrote, iclass 4, count 0 2006.196.08:01:22.24#ibcon#about to read 3, iclass 4, count 0 2006.196.08:01:22.27#ibcon#read 3, iclass 4, count 0 2006.196.08:01:22.27#ibcon#about to read 4, iclass 4, count 0 2006.196.08:01:22.27#ibcon#read 4, iclass 4, count 0 2006.196.08:01:22.27#ibcon#about to read 5, iclass 4, count 0 2006.196.08:01:22.27#ibcon#read 5, iclass 4, count 0 2006.196.08:01:22.27#ibcon#about to read 6, iclass 4, count 0 2006.196.08:01:22.27#ibcon#read 6, iclass 4, count 0 2006.196.08:01:22.27#ibcon#end of sib2, iclass 4, count 0 2006.196.08:01:22.27#ibcon#*after write, iclass 4, count 0 2006.196.08:01:22.27#ibcon#*before return 0, iclass 4, count 0 2006.196.08:01:22.27#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.196.08:01:22.27#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.196.08:01:22.27#ibcon#about to clear, iclass 4 cls_cnt 0 2006.196.08:01:22.27#ibcon#cleared, iclass 4 cls_cnt 0 2006.196.08:01:22.27$vc4f8/vblo=6,752.99 2006.196.08:01:22.27#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.196.08:01:22.27#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.196.08:01:22.27#ibcon#ireg 17 cls_cnt 0 2006.196.08:01:22.27#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.196.08:01:22.27#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.196.08:01:22.27#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.196.08:01:22.27#ibcon#enter wrdev, iclass 6, count 0 2006.196.08:01:22.27#ibcon#first serial, iclass 6, count 0 2006.196.08:01:22.27#ibcon#enter sib2, iclass 6, count 0 2006.196.08:01:22.27#ibcon#flushed, iclass 6, count 0 2006.196.08:01:22.27#ibcon#about to write, iclass 6, count 0 2006.196.08:01:22.27#ibcon#wrote, iclass 6, count 0 2006.196.08:01:22.27#ibcon#about to read 3, iclass 6, count 0 2006.196.08:01:22.29#ibcon#read 3, iclass 6, count 0 2006.196.08:01:22.29#ibcon#about to read 4, iclass 6, count 0 2006.196.08:01:22.29#ibcon#read 4, iclass 6, count 0 2006.196.08:01:22.29#ibcon#about to read 5, iclass 6, count 0 2006.196.08:01:22.29#ibcon#read 5, iclass 6, count 0 2006.196.08:01:22.29#ibcon#about to read 6, iclass 6, count 0 2006.196.08:01:22.29#ibcon#read 6, iclass 6, count 0 2006.196.08:01:22.29#ibcon#end of sib2, iclass 6, count 0 2006.196.08:01:22.29#ibcon#*mode == 0, iclass 6, count 0 2006.196.08:01:22.29#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.196.08:01:22.29#ibcon#[28=FRQ=06,752.99\r\n] 2006.196.08:01:22.29#ibcon#*before write, iclass 6, count 0 2006.196.08:01:22.29#ibcon#enter sib2, iclass 6, count 0 2006.196.08:01:22.29#ibcon#flushed, iclass 6, count 0 2006.196.08:01:22.29#ibcon#about to write, iclass 6, count 0 2006.196.08:01:22.29#ibcon#wrote, iclass 6, count 0 2006.196.08:01:22.29#ibcon#about to read 3, iclass 6, count 0 2006.196.08:01:22.33#ibcon#read 3, iclass 6, count 0 2006.196.08:01:22.33#ibcon#about to read 4, iclass 6, count 0 2006.196.08:01:22.33#ibcon#read 4, iclass 6, count 0 2006.196.08:01:22.33#ibcon#about to read 5, iclass 6, count 0 2006.196.08:01:22.33#ibcon#read 5, iclass 6, count 0 2006.196.08:01:22.33#ibcon#about to read 6, iclass 6, count 0 2006.196.08:01:22.33#ibcon#read 6, iclass 6, count 0 2006.196.08:01:22.33#ibcon#end of sib2, iclass 6, count 0 2006.196.08:01:22.33#ibcon#*after write, iclass 6, count 0 2006.196.08:01:22.33#ibcon#*before return 0, iclass 6, count 0 2006.196.08:01:22.33#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.196.08:01:22.33#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.196.08:01:22.33#ibcon#about to clear, iclass 6 cls_cnt 0 2006.196.08:01:22.33#ibcon#cleared, iclass 6 cls_cnt 0 2006.196.08:01:22.33$vc4f8/vb=6,4 2006.196.08:01:22.33#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.196.08:01:22.33#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.196.08:01:22.33#ibcon#ireg 11 cls_cnt 2 2006.196.08:01:22.33#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.196.08:01:22.39#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.196.08:01:22.39#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.196.08:01:22.39#ibcon#enter wrdev, iclass 10, count 2 2006.196.08:01:22.39#ibcon#first serial, iclass 10, count 2 2006.196.08:01:22.39#ibcon#enter sib2, iclass 10, count 2 2006.196.08:01:22.39#ibcon#flushed, iclass 10, count 2 2006.196.08:01:22.39#ibcon#about to write, iclass 10, count 2 2006.196.08:01:22.39#ibcon#wrote, iclass 10, count 2 2006.196.08:01:22.39#ibcon#about to read 3, iclass 10, count 2 2006.196.08:01:22.41#ibcon#read 3, iclass 10, count 2 2006.196.08:01:22.41#ibcon#about to read 4, iclass 10, count 2 2006.196.08:01:22.41#ibcon#read 4, iclass 10, count 2 2006.196.08:01:22.41#ibcon#about to read 5, iclass 10, count 2 2006.196.08:01:22.41#ibcon#read 5, iclass 10, count 2 2006.196.08:01:22.41#ibcon#about to read 6, iclass 10, count 2 2006.196.08:01:22.41#ibcon#read 6, iclass 10, count 2 2006.196.08:01:22.41#ibcon#end of sib2, iclass 10, count 2 2006.196.08:01:22.41#ibcon#*mode == 0, iclass 10, count 2 2006.196.08:01:22.41#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.196.08:01:22.41#ibcon#[27=AT06-04\r\n] 2006.196.08:01:22.41#ibcon#*before write, iclass 10, count 2 2006.196.08:01:22.41#ibcon#enter sib2, iclass 10, count 2 2006.196.08:01:22.41#ibcon#flushed, iclass 10, count 2 2006.196.08:01:22.41#ibcon#about to write, iclass 10, count 2 2006.196.08:01:22.41#ibcon#wrote, iclass 10, count 2 2006.196.08:01:22.41#ibcon#about to read 3, iclass 10, count 2 2006.196.08:01:22.44#ibcon#read 3, iclass 10, count 2 2006.196.08:01:22.44#ibcon#about to read 4, iclass 10, count 2 2006.196.08:01:22.44#ibcon#read 4, iclass 10, count 2 2006.196.08:01:22.44#ibcon#about to read 5, iclass 10, count 2 2006.196.08:01:22.44#ibcon#read 5, iclass 10, count 2 2006.196.08:01:22.44#ibcon#about to read 6, iclass 10, count 2 2006.196.08:01:22.44#ibcon#read 6, iclass 10, count 2 2006.196.08:01:22.44#ibcon#end of sib2, iclass 10, count 2 2006.196.08:01:22.44#ibcon#*after write, iclass 10, count 2 2006.196.08:01:22.44#ibcon#*before return 0, iclass 10, count 2 2006.196.08:01:22.44#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.196.08:01:22.44#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.196.08:01:22.44#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.196.08:01:22.44#ibcon#ireg 7 cls_cnt 0 2006.196.08:01:22.44#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.196.08:01:22.56#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.196.08:01:22.56#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.196.08:01:22.56#ibcon#enter wrdev, iclass 10, count 0 2006.196.08:01:22.56#ibcon#first serial, iclass 10, count 0 2006.196.08:01:22.56#ibcon#enter sib2, iclass 10, count 0 2006.196.08:01:22.56#ibcon#flushed, iclass 10, count 0 2006.196.08:01:22.56#ibcon#about to write, iclass 10, count 0 2006.196.08:01:22.56#ibcon#wrote, iclass 10, count 0 2006.196.08:01:22.56#ibcon#about to read 3, iclass 10, count 0 2006.196.08:01:22.58#ibcon#read 3, iclass 10, count 0 2006.196.08:01:22.58#ibcon#about to read 4, iclass 10, count 0 2006.196.08:01:22.58#ibcon#read 4, iclass 10, count 0 2006.196.08:01:22.58#ibcon#about to read 5, iclass 10, count 0 2006.196.08:01:22.58#ibcon#read 5, iclass 10, count 0 2006.196.08:01:22.58#ibcon#about to read 6, iclass 10, count 0 2006.196.08:01:22.58#ibcon#read 6, iclass 10, count 0 2006.196.08:01:22.58#ibcon#end of sib2, iclass 10, count 0 2006.196.08:01:22.58#ibcon#*mode == 0, iclass 10, count 0 2006.196.08:01:22.58#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.196.08:01:22.58#ibcon#[27=USB\r\n] 2006.196.08:01:22.58#ibcon#*before write, iclass 10, count 0 2006.196.08:01:22.58#ibcon#enter sib2, iclass 10, count 0 2006.196.08:01:22.58#ibcon#flushed, iclass 10, count 0 2006.196.08:01:22.58#ibcon#about to write, iclass 10, count 0 2006.196.08:01:22.58#ibcon#wrote, iclass 10, count 0 2006.196.08:01:22.58#ibcon#about to read 3, iclass 10, count 0 2006.196.08:01:22.61#ibcon#read 3, iclass 10, count 0 2006.196.08:01:22.61#ibcon#about to read 4, iclass 10, count 0 2006.196.08:01:22.61#ibcon#read 4, iclass 10, count 0 2006.196.08:01:22.61#ibcon#about to read 5, iclass 10, count 0 2006.196.08:01:22.61#ibcon#read 5, iclass 10, count 0 2006.196.08:01:22.61#ibcon#about to read 6, iclass 10, count 0 2006.196.08:01:22.61#ibcon#read 6, iclass 10, count 0 2006.196.08:01:22.61#ibcon#end of sib2, iclass 10, count 0 2006.196.08:01:22.61#ibcon#*after write, iclass 10, count 0 2006.196.08:01:22.61#ibcon#*before return 0, iclass 10, count 0 2006.196.08:01:22.61#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.196.08:01:22.61#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.196.08:01:22.61#ibcon#about to clear, iclass 10 cls_cnt 0 2006.196.08:01:22.61#ibcon#cleared, iclass 10 cls_cnt 0 2006.196.08:01:22.61$vc4f8/vabw=wide 2006.196.08:01:22.61#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.196.08:01:22.61#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.196.08:01:22.61#ibcon#ireg 8 cls_cnt 0 2006.196.08:01:22.61#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.196.08:01:22.61#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.196.08:01:22.61#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.196.08:01:22.61#ibcon#enter wrdev, iclass 12, count 0 2006.196.08:01:22.61#ibcon#first serial, iclass 12, count 0 2006.196.08:01:22.61#ibcon#enter sib2, iclass 12, count 0 2006.196.08:01:22.61#ibcon#flushed, iclass 12, count 0 2006.196.08:01:22.61#ibcon#about to write, iclass 12, count 0 2006.196.08:01:22.61#ibcon#wrote, iclass 12, count 0 2006.196.08:01:22.61#ibcon#about to read 3, iclass 12, count 0 2006.196.08:01:22.63#ibcon#read 3, iclass 12, count 0 2006.196.08:01:22.63#ibcon#about to read 4, iclass 12, count 0 2006.196.08:01:22.63#ibcon#read 4, iclass 12, count 0 2006.196.08:01:22.63#ibcon#about to read 5, iclass 12, count 0 2006.196.08:01:22.63#ibcon#read 5, iclass 12, count 0 2006.196.08:01:22.63#ibcon#about to read 6, iclass 12, count 0 2006.196.08:01:22.63#ibcon#read 6, iclass 12, count 0 2006.196.08:01:22.63#ibcon#end of sib2, iclass 12, count 0 2006.196.08:01:22.63#ibcon#*mode == 0, iclass 12, count 0 2006.196.08:01:22.63#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.196.08:01:22.63#ibcon#[25=BW32\r\n] 2006.196.08:01:22.63#ibcon#*before write, iclass 12, count 0 2006.196.08:01:22.63#ibcon#enter sib2, iclass 12, count 0 2006.196.08:01:22.63#ibcon#flushed, iclass 12, count 0 2006.196.08:01:22.63#ibcon#about to write, iclass 12, count 0 2006.196.08:01:22.63#ibcon#wrote, iclass 12, count 0 2006.196.08:01:22.63#ibcon#about to read 3, iclass 12, count 0 2006.196.08:01:22.66#ibcon#read 3, iclass 12, count 0 2006.196.08:01:22.66#ibcon#about to read 4, iclass 12, count 0 2006.196.08:01:22.66#ibcon#read 4, iclass 12, count 0 2006.196.08:01:22.66#ibcon#about to read 5, iclass 12, count 0 2006.196.08:01:22.66#ibcon#read 5, iclass 12, count 0 2006.196.08:01:22.66#ibcon#about to read 6, iclass 12, count 0 2006.196.08:01:22.66#ibcon#read 6, iclass 12, count 0 2006.196.08:01:22.66#ibcon#end of sib2, iclass 12, count 0 2006.196.08:01:22.66#ibcon#*after write, iclass 12, count 0 2006.196.08:01:22.66#ibcon#*before return 0, iclass 12, count 0 2006.196.08:01:22.66#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.196.08:01:22.66#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.196.08:01:22.66#ibcon#about to clear, iclass 12 cls_cnt 0 2006.196.08:01:22.66#ibcon#cleared, iclass 12 cls_cnt 0 2006.196.08:01:22.66$vc4f8/vbbw=wide 2006.196.08:01:22.66#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.196.08:01:22.66#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.196.08:01:22.66#ibcon#ireg 8 cls_cnt 0 2006.196.08:01:22.66#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.196.08:01:22.73#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.196.08:01:22.73#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.196.08:01:22.73#ibcon#enter wrdev, iclass 14, count 0 2006.196.08:01:22.73#ibcon#first serial, iclass 14, count 0 2006.196.08:01:22.73#ibcon#enter sib2, iclass 14, count 0 2006.196.08:01:22.73#ibcon#flushed, iclass 14, count 0 2006.196.08:01:22.73#ibcon#about to write, iclass 14, count 0 2006.196.08:01:22.73#ibcon#wrote, iclass 14, count 0 2006.196.08:01:22.73#ibcon#about to read 3, iclass 14, count 0 2006.196.08:01:22.75#ibcon#read 3, iclass 14, count 0 2006.196.08:01:22.75#ibcon#about to read 4, iclass 14, count 0 2006.196.08:01:22.75#ibcon#read 4, iclass 14, count 0 2006.196.08:01:22.75#ibcon#about to read 5, iclass 14, count 0 2006.196.08:01:22.75#ibcon#read 5, iclass 14, count 0 2006.196.08:01:22.75#ibcon#about to read 6, iclass 14, count 0 2006.196.08:01:22.75#ibcon#read 6, iclass 14, count 0 2006.196.08:01:22.75#ibcon#end of sib2, iclass 14, count 0 2006.196.08:01:22.75#ibcon#*mode == 0, iclass 14, count 0 2006.196.08:01:22.75#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.196.08:01:22.75#ibcon#[27=BW32\r\n] 2006.196.08:01:22.75#ibcon#*before write, iclass 14, count 0 2006.196.08:01:22.75#ibcon#enter sib2, iclass 14, count 0 2006.196.08:01:22.75#ibcon#flushed, iclass 14, count 0 2006.196.08:01:22.75#ibcon#about to write, iclass 14, count 0 2006.196.08:01:22.75#ibcon#wrote, iclass 14, count 0 2006.196.08:01:22.75#ibcon#about to read 3, iclass 14, count 0 2006.196.08:01:22.78#ibcon#read 3, iclass 14, count 0 2006.196.08:01:22.78#ibcon#about to read 4, iclass 14, count 0 2006.196.08:01:22.78#ibcon#read 4, iclass 14, count 0 2006.196.08:01:22.78#ibcon#about to read 5, iclass 14, count 0 2006.196.08:01:22.78#ibcon#read 5, iclass 14, count 0 2006.196.08:01:22.78#ibcon#about to read 6, iclass 14, count 0 2006.196.08:01:22.78#ibcon#read 6, iclass 14, count 0 2006.196.08:01:22.78#ibcon#end of sib2, iclass 14, count 0 2006.196.08:01:22.78#ibcon#*after write, iclass 14, count 0 2006.196.08:01:22.78#ibcon#*before return 0, iclass 14, count 0 2006.196.08:01:22.78#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.196.08:01:22.78#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.196.08:01:22.78#ibcon#about to clear, iclass 14 cls_cnt 0 2006.196.08:01:22.78#ibcon#cleared, iclass 14 cls_cnt 0 2006.196.08:01:22.78$4f8m12a/ifd4f 2006.196.08:01:22.78$ifd4f/lo= 2006.196.08:01:22.78$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.196.08:01:22.78$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.196.08:01:22.78$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.196.08:01:22.78$ifd4f/patch= 2006.196.08:01:22.78$ifd4f/patch=lo1,a1,a2,a3,a4 2006.196.08:01:22.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.196.08:01:22.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.196.08:01:22.78$4f8m12a/"form=m,16.000,1:2 2006.196.08:01:22.78$4f8m12a/"tpicd 2006.196.08:01:22.78$4f8m12a/echo=off 2006.196.08:01:22.78$4f8m12a/xlog=off 2006.196.08:01:22.78:!2006.196.08:03:20 2006.196.08:01:44.14#trakl#Source acquired 2006.196.08:01:44.14#flagr#flagr/antenna,acquired 2006.196.08:03:20.00:preob 2006.196.08:03:21.14/onsource/TRACKING 2006.196.08:03:21.14:!2006.196.08:03:30 2006.196.08:03:30.00:data_valid=on 2006.196.08:03:30.00:midob 2006.196.08:03:30.14/onsource/TRACKING 2006.196.08:03:30.14/wx/29.41,1004.0,90 2006.196.08:03:30.34/cable/+6.3352E-03 2006.196.08:03:31.43/va/01,08,usb,yes,29,30 2006.196.08:03:31.43/va/02,07,usb,yes,29,30 2006.196.08:03:31.43/va/03,06,usb,yes,31,31 2006.196.08:03:31.43/va/04,07,usb,yes,30,32 2006.196.08:03:31.43/va/05,07,usb,yes,32,34 2006.196.08:03:31.43/va/06,06,usb,yes,31,31 2006.196.08:03:31.43/va/07,06,usb,yes,32,32 2006.196.08:03:31.43/va/08,07,usb,yes,30,30 2006.196.08:03:31.66/valo/01,532.99,yes,locked 2006.196.08:03:31.66/valo/02,572.99,yes,locked 2006.196.08:03:31.66/valo/03,672.99,yes,locked 2006.196.08:03:31.66/valo/04,832.99,yes,locked 2006.196.08:03:31.66/valo/05,652.99,yes,locked 2006.196.08:03:31.66/valo/06,772.99,yes,locked 2006.196.08:03:31.66/valo/07,832.99,yes,locked 2006.196.08:03:31.66/valo/08,852.99,yes,locked 2006.196.08:03:32.75/vb/01,04,usb,yes,29,27 2006.196.08:03:32.75/vb/02,04,usb,yes,30,32 2006.196.08:03:32.75/vb/03,04,usb,yes,27,31 2006.196.08:03:32.75/vb/04,04,usb,yes,28,28 2006.196.08:03:32.75/vb/05,04,usb,yes,26,30 2006.196.08:03:32.75/vb/06,04,usb,yes,27,30 2006.196.08:03:32.75/vb/07,04,usb,yes,29,29 2006.196.08:03:32.75/vb/08,04,usb,yes,27,30 2006.196.08:03:32.98/vblo/01,632.99,yes,locked 2006.196.08:03:32.98/vblo/02,640.99,yes,locked 2006.196.08:03:32.98/vblo/03,656.99,yes,locked 2006.196.08:03:32.98/vblo/04,712.99,yes,locked 2006.196.08:03:32.98/vblo/05,744.99,yes,locked 2006.196.08:03:32.98/vblo/06,752.99,yes,locked 2006.196.08:03:32.98/vblo/07,734.99,yes,locked 2006.196.08:03:32.98/vblo/08,744.99,yes,locked 2006.196.08:03:33.13/vabw/8 2006.196.08:03:33.28/vbbw/8 2006.196.08:03:33.37/xfe/off,on,15.0 2006.196.08:03:33.74/ifatt/23,28,28,28 2006.196.08:03:34.07/fmout-gps/S +3.36E-07 2006.196.08:03:34.11:!2006.196.08:04:30 2006.196.08:04:30.00:data_valid=off 2006.196.08:04:30.00:postob 2006.196.08:04:30.14/cable/+6.3356E-03 2006.196.08:04:30.14/wx/29.39,1004.0,91 2006.196.08:04:31.07/fmout-gps/S +3.36E-07 2006.196.08:04:31.07:scan_name=196-0805,k06196,60 2006.196.08:04:31.07:source=3c371,180650.68,694928.1,2000.0,cw 2006.196.08:04:31.14#flagr#flagr/antenna,new-source 2006.196.08:04:32.14:checkk5 2006.196.08:04:32.51/chk_autoobs//k5ts1/ autoobs is running! 2006.196.08:04:32.90/chk_autoobs//k5ts2/ autoobs is running! 2006.196.08:04:33.28/chk_autoobs//k5ts3/ autoobs is running! 2006.196.08:04:33.65/chk_autoobs//k5ts4/ autoobs is running! 2006.196.08:04:34.02/chk_obsdata//k5ts1/T1960803??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.08:04:34.39/chk_obsdata//k5ts2/T1960803??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.08:04:34.76/chk_obsdata//k5ts3/T1960803??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.08:04:35.13/chk_obsdata//k5ts4/T1960803??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.08:04:35.82/k5log//k5ts1_log_newline 2006.196.08:04:36.52/k5log//k5ts2_log_newline 2006.196.08:04:37.21/k5log//k5ts3_log_newline 2006.196.08:04:37.90/k5log//k5ts4_log_newline 2006.196.08:04:37.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.196.08:04:37.92:4f8m12a=2 2006.196.08:04:37.92$4f8m12a/echo=on 2006.196.08:04:37.92$4f8m12a/pcalon 2006.196.08:04:37.92$pcalon/"no phase cal control is implemented here 2006.196.08:04:37.92$4f8m12a/"tpicd=stop 2006.196.08:04:37.92$4f8m12a/vc4f8 2006.196.08:04:37.92$vc4f8/valo=1,532.99 2006.196.08:04:37.93#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.196.08:04:37.93#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.196.08:04:37.93#ibcon#ireg 17 cls_cnt 0 2006.196.08:04:37.93#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.196.08:04:37.93#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.196.08:04:37.93#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.196.08:04:37.93#ibcon#enter wrdev, iclass 21, count 0 2006.196.08:04:37.93#ibcon#first serial, iclass 21, count 0 2006.196.08:04:37.93#ibcon#enter sib2, iclass 21, count 0 2006.196.08:04:37.93#ibcon#flushed, iclass 21, count 0 2006.196.08:04:37.93#ibcon#about to write, iclass 21, count 0 2006.196.08:04:37.93#ibcon#wrote, iclass 21, count 0 2006.196.08:04:37.93#ibcon#about to read 3, iclass 21, count 0 2006.196.08:04:37.97#ibcon#read 3, iclass 21, count 0 2006.196.08:04:37.97#ibcon#about to read 4, iclass 21, count 0 2006.196.08:04:37.97#ibcon#read 4, iclass 21, count 0 2006.196.08:04:37.97#ibcon#about to read 5, iclass 21, count 0 2006.196.08:04:37.97#ibcon#read 5, iclass 21, count 0 2006.196.08:04:37.97#ibcon#about to read 6, iclass 21, count 0 2006.196.08:04:37.97#ibcon#read 6, iclass 21, count 0 2006.196.08:04:37.97#ibcon#end of sib2, iclass 21, count 0 2006.196.08:04:37.97#ibcon#*mode == 0, iclass 21, count 0 2006.196.08:04:37.97#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.196.08:04:37.97#ibcon#[26=FRQ=01,532.99\r\n] 2006.196.08:04:37.97#ibcon#*before write, iclass 21, count 0 2006.196.08:04:37.97#ibcon#enter sib2, iclass 21, count 0 2006.196.08:04:37.97#ibcon#flushed, iclass 21, count 0 2006.196.08:04:37.97#ibcon#about to write, iclass 21, count 0 2006.196.08:04:37.97#ibcon#wrote, iclass 21, count 0 2006.196.08:04:37.97#ibcon#about to read 3, iclass 21, count 0 2006.196.08:04:38.02#ibcon#read 3, iclass 21, count 0 2006.196.08:04:38.02#ibcon#about to read 4, iclass 21, count 0 2006.196.08:04:38.02#ibcon#read 4, iclass 21, count 0 2006.196.08:04:38.02#ibcon#about to read 5, iclass 21, count 0 2006.196.08:04:38.02#ibcon#read 5, iclass 21, count 0 2006.196.08:04:38.02#ibcon#about to read 6, iclass 21, count 0 2006.196.08:04:38.02#ibcon#read 6, iclass 21, count 0 2006.196.08:04:38.02#ibcon#end of sib2, iclass 21, count 0 2006.196.08:04:38.02#ibcon#*after write, iclass 21, count 0 2006.196.08:04:38.02#ibcon#*before return 0, iclass 21, count 0 2006.196.08:04:38.02#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.196.08:04:38.02#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.196.08:04:38.02#ibcon#about to clear, iclass 21 cls_cnt 0 2006.196.08:04:38.02#ibcon#cleared, iclass 21 cls_cnt 0 2006.196.08:04:38.02$vc4f8/va=1,8 2006.196.08:04:38.02#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.196.08:04:38.02#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.196.08:04:38.02#ibcon#ireg 11 cls_cnt 2 2006.196.08:04:38.02#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.196.08:04:38.02#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.196.08:04:38.02#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.196.08:04:38.02#ibcon#enter wrdev, iclass 23, count 2 2006.196.08:04:38.02#ibcon#first serial, iclass 23, count 2 2006.196.08:04:38.02#ibcon#enter sib2, iclass 23, count 2 2006.196.08:04:38.02#ibcon#flushed, iclass 23, count 2 2006.196.08:04:38.02#ibcon#about to write, iclass 23, count 2 2006.196.08:04:38.02#ibcon#wrote, iclass 23, count 2 2006.196.08:04:38.02#ibcon#about to read 3, iclass 23, count 2 2006.196.08:04:38.04#ibcon#read 3, iclass 23, count 2 2006.196.08:04:38.04#ibcon#about to read 4, iclass 23, count 2 2006.196.08:04:38.04#ibcon#read 4, iclass 23, count 2 2006.196.08:04:38.04#ibcon#about to read 5, iclass 23, count 2 2006.196.08:04:38.04#ibcon#read 5, iclass 23, count 2 2006.196.08:04:38.04#ibcon#about to read 6, iclass 23, count 2 2006.196.08:04:38.04#ibcon#read 6, iclass 23, count 2 2006.196.08:04:38.04#ibcon#end of sib2, iclass 23, count 2 2006.196.08:04:38.04#ibcon#*mode == 0, iclass 23, count 2 2006.196.08:04:38.04#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.196.08:04:38.04#ibcon#[25=AT01-08\r\n] 2006.196.08:04:38.04#ibcon#*before write, iclass 23, count 2 2006.196.08:04:38.04#ibcon#enter sib2, iclass 23, count 2 2006.196.08:04:38.04#ibcon#flushed, iclass 23, count 2 2006.196.08:04:38.04#ibcon#about to write, iclass 23, count 2 2006.196.08:04:38.04#ibcon#wrote, iclass 23, count 2 2006.196.08:04:38.04#ibcon#about to read 3, iclass 23, count 2 2006.196.08:04:38.07#ibcon#read 3, iclass 23, count 2 2006.196.08:04:38.07#ibcon#about to read 4, iclass 23, count 2 2006.196.08:04:38.07#ibcon#read 4, iclass 23, count 2 2006.196.08:04:38.07#ibcon#about to read 5, iclass 23, count 2 2006.196.08:04:38.07#ibcon#read 5, iclass 23, count 2 2006.196.08:04:38.07#ibcon#about to read 6, iclass 23, count 2 2006.196.08:04:38.07#ibcon#read 6, iclass 23, count 2 2006.196.08:04:38.07#ibcon#end of sib2, iclass 23, count 2 2006.196.08:04:38.07#ibcon#*after write, iclass 23, count 2 2006.196.08:04:38.07#ibcon#*before return 0, iclass 23, count 2 2006.196.08:04:38.07#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.196.08:04:38.07#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.196.08:04:38.07#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.196.08:04:38.07#ibcon#ireg 7 cls_cnt 0 2006.196.08:04:38.07#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.196.08:04:38.19#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.196.08:04:38.19#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.196.08:04:38.19#ibcon#enter wrdev, iclass 23, count 0 2006.196.08:04:38.19#ibcon#first serial, iclass 23, count 0 2006.196.08:04:38.19#ibcon#enter sib2, iclass 23, count 0 2006.196.08:04:38.19#ibcon#flushed, iclass 23, count 0 2006.196.08:04:38.19#ibcon#about to write, iclass 23, count 0 2006.196.08:04:38.19#ibcon#wrote, iclass 23, count 0 2006.196.08:04:38.19#ibcon#about to read 3, iclass 23, count 0 2006.196.08:04:38.21#ibcon#read 3, iclass 23, count 0 2006.196.08:04:38.21#ibcon#about to read 4, iclass 23, count 0 2006.196.08:04:38.21#ibcon#read 4, iclass 23, count 0 2006.196.08:04:38.21#ibcon#about to read 5, iclass 23, count 0 2006.196.08:04:38.21#ibcon#read 5, iclass 23, count 0 2006.196.08:04:38.21#ibcon#about to read 6, iclass 23, count 0 2006.196.08:04:38.21#ibcon#read 6, iclass 23, count 0 2006.196.08:04:38.21#ibcon#end of sib2, iclass 23, count 0 2006.196.08:04:38.21#ibcon#*mode == 0, iclass 23, count 0 2006.196.08:04:38.21#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.196.08:04:38.21#ibcon#[25=USB\r\n] 2006.196.08:04:38.21#ibcon#*before write, iclass 23, count 0 2006.196.08:04:38.21#ibcon#enter sib2, iclass 23, count 0 2006.196.08:04:38.21#ibcon#flushed, iclass 23, count 0 2006.196.08:04:38.21#ibcon#about to write, iclass 23, count 0 2006.196.08:04:38.21#ibcon#wrote, iclass 23, count 0 2006.196.08:04:38.21#ibcon#about to read 3, iclass 23, count 0 2006.196.08:04:38.24#ibcon#read 3, iclass 23, count 0 2006.196.08:04:38.24#ibcon#about to read 4, iclass 23, count 0 2006.196.08:04:38.24#ibcon#read 4, iclass 23, count 0 2006.196.08:04:38.24#ibcon#about to read 5, iclass 23, count 0 2006.196.08:04:38.24#ibcon#read 5, iclass 23, count 0 2006.196.08:04:38.24#ibcon#about to read 6, iclass 23, count 0 2006.196.08:04:38.24#ibcon#read 6, iclass 23, count 0 2006.196.08:04:38.24#ibcon#end of sib2, iclass 23, count 0 2006.196.08:04:38.24#ibcon#*after write, iclass 23, count 0 2006.196.08:04:38.24#ibcon#*before return 0, iclass 23, count 0 2006.196.08:04:38.24#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.196.08:04:38.24#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.196.08:04:38.24#ibcon#about to clear, iclass 23 cls_cnt 0 2006.196.08:04:38.24#ibcon#cleared, iclass 23 cls_cnt 0 2006.196.08:04:38.24$vc4f8/valo=2,572.99 2006.196.08:04:38.24#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.196.08:04:38.24#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.196.08:04:38.24#ibcon#ireg 17 cls_cnt 0 2006.196.08:04:38.24#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.196.08:04:38.24#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.196.08:04:38.24#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.196.08:04:38.24#ibcon#enter wrdev, iclass 25, count 0 2006.196.08:04:38.24#ibcon#first serial, iclass 25, count 0 2006.196.08:04:38.24#ibcon#enter sib2, iclass 25, count 0 2006.196.08:04:38.24#ibcon#flushed, iclass 25, count 0 2006.196.08:04:38.24#ibcon#about to write, iclass 25, count 0 2006.196.08:04:38.24#ibcon#wrote, iclass 25, count 0 2006.196.08:04:38.24#ibcon#about to read 3, iclass 25, count 0 2006.196.08:04:38.26#ibcon#read 3, iclass 25, count 0 2006.196.08:04:38.26#ibcon#about to read 4, iclass 25, count 0 2006.196.08:04:38.26#ibcon#read 4, iclass 25, count 0 2006.196.08:04:38.26#ibcon#about to read 5, iclass 25, count 0 2006.196.08:04:38.26#ibcon#read 5, iclass 25, count 0 2006.196.08:04:38.26#ibcon#about to read 6, iclass 25, count 0 2006.196.08:04:38.26#ibcon#read 6, iclass 25, count 0 2006.196.08:04:38.26#ibcon#end of sib2, iclass 25, count 0 2006.196.08:04:38.26#ibcon#*mode == 0, iclass 25, count 0 2006.196.08:04:38.26#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.196.08:04:38.26#ibcon#[26=FRQ=02,572.99\r\n] 2006.196.08:04:38.26#ibcon#*before write, iclass 25, count 0 2006.196.08:04:38.26#ibcon#enter sib2, iclass 25, count 0 2006.196.08:04:38.26#ibcon#flushed, iclass 25, count 0 2006.196.08:04:38.26#ibcon#about to write, iclass 25, count 0 2006.196.08:04:38.26#ibcon#wrote, iclass 25, count 0 2006.196.08:04:38.26#ibcon#about to read 3, iclass 25, count 0 2006.196.08:04:38.30#ibcon#read 3, iclass 25, count 0 2006.196.08:04:38.30#ibcon#about to read 4, iclass 25, count 0 2006.196.08:04:38.30#ibcon#read 4, iclass 25, count 0 2006.196.08:04:38.30#ibcon#about to read 5, iclass 25, count 0 2006.196.08:04:38.30#ibcon#read 5, iclass 25, count 0 2006.196.08:04:38.30#ibcon#about to read 6, iclass 25, count 0 2006.196.08:04:38.30#ibcon#read 6, iclass 25, count 0 2006.196.08:04:38.30#ibcon#end of sib2, iclass 25, count 0 2006.196.08:04:38.30#ibcon#*after write, iclass 25, count 0 2006.196.08:04:38.30#ibcon#*before return 0, iclass 25, count 0 2006.196.08:04:38.30#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.196.08:04:38.30#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.196.08:04:38.30#ibcon#about to clear, iclass 25 cls_cnt 0 2006.196.08:04:38.30#ibcon#cleared, iclass 25 cls_cnt 0 2006.196.08:04:38.30$vc4f8/va=2,7 2006.196.08:04:38.30#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.196.08:04:38.30#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.196.08:04:38.30#ibcon#ireg 11 cls_cnt 2 2006.196.08:04:38.30#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.196.08:04:38.36#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.196.08:04:38.36#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.196.08:04:38.36#ibcon#enter wrdev, iclass 27, count 2 2006.196.08:04:38.36#ibcon#first serial, iclass 27, count 2 2006.196.08:04:38.36#ibcon#enter sib2, iclass 27, count 2 2006.196.08:04:38.36#ibcon#flushed, iclass 27, count 2 2006.196.08:04:38.36#ibcon#about to write, iclass 27, count 2 2006.196.08:04:38.36#ibcon#wrote, iclass 27, count 2 2006.196.08:04:38.36#ibcon#about to read 3, iclass 27, count 2 2006.196.08:04:38.38#ibcon#read 3, iclass 27, count 2 2006.196.08:04:38.38#ibcon#about to read 4, iclass 27, count 2 2006.196.08:04:38.38#ibcon#read 4, iclass 27, count 2 2006.196.08:04:38.38#ibcon#about to read 5, iclass 27, count 2 2006.196.08:04:38.38#ibcon#read 5, iclass 27, count 2 2006.196.08:04:38.38#ibcon#about to read 6, iclass 27, count 2 2006.196.08:04:38.38#ibcon#read 6, iclass 27, count 2 2006.196.08:04:38.38#ibcon#end of sib2, iclass 27, count 2 2006.196.08:04:38.38#ibcon#*mode == 0, iclass 27, count 2 2006.196.08:04:38.38#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.196.08:04:38.38#ibcon#[25=AT02-07\r\n] 2006.196.08:04:38.38#ibcon#*before write, iclass 27, count 2 2006.196.08:04:38.38#ibcon#enter sib2, iclass 27, count 2 2006.196.08:04:38.38#ibcon#flushed, iclass 27, count 2 2006.196.08:04:38.38#ibcon#about to write, iclass 27, count 2 2006.196.08:04:38.38#ibcon#wrote, iclass 27, count 2 2006.196.08:04:38.38#ibcon#about to read 3, iclass 27, count 2 2006.196.08:04:38.41#ibcon#read 3, iclass 27, count 2 2006.196.08:04:38.41#ibcon#about to read 4, iclass 27, count 2 2006.196.08:04:38.41#ibcon#read 4, iclass 27, count 2 2006.196.08:04:38.41#ibcon#about to read 5, iclass 27, count 2 2006.196.08:04:38.41#ibcon#read 5, iclass 27, count 2 2006.196.08:04:38.41#ibcon#about to read 6, iclass 27, count 2 2006.196.08:04:38.41#ibcon#read 6, iclass 27, count 2 2006.196.08:04:38.41#ibcon#end of sib2, iclass 27, count 2 2006.196.08:04:38.41#ibcon#*after write, iclass 27, count 2 2006.196.08:04:38.41#ibcon#*before return 0, iclass 27, count 2 2006.196.08:04:38.41#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.196.08:04:38.41#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.196.08:04:38.41#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.196.08:04:38.41#ibcon#ireg 7 cls_cnt 0 2006.196.08:04:38.41#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.196.08:04:38.53#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.196.08:04:38.53#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.196.08:04:38.53#ibcon#enter wrdev, iclass 27, count 0 2006.196.08:04:38.53#ibcon#first serial, iclass 27, count 0 2006.196.08:04:38.53#ibcon#enter sib2, iclass 27, count 0 2006.196.08:04:38.53#ibcon#flushed, iclass 27, count 0 2006.196.08:04:38.53#ibcon#about to write, iclass 27, count 0 2006.196.08:04:38.53#ibcon#wrote, iclass 27, count 0 2006.196.08:04:38.53#ibcon#about to read 3, iclass 27, count 0 2006.196.08:04:38.55#ibcon#read 3, iclass 27, count 0 2006.196.08:04:38.55#ibcon#about to read 4, iclass 27, count 0 2006.196.08:04:38.55#ibcon#read 4, iclass 27, count 0 2006.196.08:04:38.55#ibcon#about to read 5, iclass 27, count 0 2006.196.08:04:38.55#ibcon#read 5, iclass 27, count 0 2006.196.08:04:38.55#ibcon#about to read 6, iclass 27, count 0 2006.196.08:04:38.55#ibcon#read 6, iclass 27, count 0 2006.196.08:04:38.55#ibcon#end of sib2, iclass 27, count 0 2006.196.08:04:38.55#ibcon#*mode == 0, iclass 27, count 0 2006.196.08:04:38.55#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.196.08:04:38.55#ibcon#[25=USB\r\n] 2006.196.08:04:38.55#ibcon#*before write, iclass 27, count 0 2006.196.08:04:38.55#ibcon#enter sib2, iclass 27, count 0 2006.196.08:04:38.55#ibcon#flushed, iclass 27, count 0 2006.196.08:04:38.55#ibcon#about to write, iclass 27, count 0 2006.196.08:04:38.55#ibcon#wrote, iclass 27, count 0 2006.196.08:04:38.55#ibcon#about to read 3, iclass 27, count 0 2006.196.08:04:38.58#ibcon#read 3, iclass 27, count 0 2006.196.08:04:38.58#ibcon#about to read 4, iclass 27, count 0 2006.196.08:04:38.58#ibcon#read 4, iclass 27, count 0 2006.196.08:04:38.58#ibcon#about to read 5, iclass 27, count 0 2006.196.08:04:38.58#ibcon#read 5, iclass 27, count 0 2006.196.08:04:38.58#ibcon#about to read 6, iclass 27, count 0 2006.196.08:04:38.58#ibcon#read 6, iclass 27, count 0 2006.196.08:04:38.58#ibcon#end of sib2, iclass 27, count 0 2006.196.08:04:38.58#ibcon#*after write, iclass 27, count 0 2006.196.08:04:38.58#ibcon#*before return 0, iclass 27, count 0 2006.196.08:04:38.58#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.196.08:04:38.58#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.196.08:04:38.58#ibcon#about to clear, iclass 27 cls_cnt 0 2006.196.08:04:38.58#ibcon#cleared, iclass 27 cls_cnt 0 2006.196.08:04:38.58$vc4f8/valo=3,672.99 2006.196.08:04:38.58#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.196.08:04:38.58#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.196.08:04:38.58#ibcon#ireg 17 cls_cnt 0 2006.196.08:04:38.58#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.196.08:04:38.58#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.196.08:04:38.58#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.196.08:04:38.58#ibcon#enter wrdev, iclass 29, count 0 2006.196.08:04:38.58#ibcon#first serial, iclass 29, count 0 2006.196.08:04:38.58#ibcon#enter sib2, iclass 29, count 0 2006.196.08:04:38.58#ibcon#flushed, iclass 29, count 0 2006.196.08:04:38.58#ibcon#about to write, iclass 29, count 0 2006.196.08:04:38.58#ibcon#wrote, iclass 29, count 0 2006.196.08:04:38.58#ibcon#about to read 3, iclass 29, count 0 2006.196.08:04:38.60#ibcon#read 3, iclass 29, count 0 2006.196.08:04:38.60#ibcon#about to read 4, iclass 29, count 0 2006.196.08:04:38.60#ibcon#read 4, iclass 29, count 0 2006.196.08:04:38.60#ibcon#about to read 5, iclass 29, count 0 2006.196.08:04:38.60#ibcon#read 5, iclass 29, count 0 2006.196.08:04:38.60#ibcon#about to read 6, iclass 29, count 0 2006.196.08:04:38.60#ibcon#read 6, iclass 29, count 0 2006.196.08:04:38.60#ibcon#end of sib2, iclass 29, count 0 2006.196.08:04:38.60#ibcon#*mode == 0, iclass 29, count 0 2006.196.08:04:38.60#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.196.08:04:38.60#ibcon#[26=FRQ=03,672.99\r\n] 2006.196.08:04:38.60#ibcon#*before write, iclass 29, count 0 2006.196.08:04:38.60#ibcon#enter sib2, iclass 29, count 0 2006.196.08:04:38.60#ibcon#flushed, iclass 29, count 0 2006.196.08:04:38.60#ibcon#about to write, iclass 29, count 0 2006.196.08:04:38.60#ibcon#wrote, iclass 29, count 0 2006.196.08:04:38.60#ibcon#about to read 3, iclass 29, count 0 2006.196.08:04:38.65#ibcon#read 3, iclass 29, count 0 2006.196.08:04:38.65#ibcon#about to read 4, iclass 29, count 0 2006.196.08:04:38.65#ibcon#read 4, iclass 29, count 0 2006.196.08:04:38.65#ibcon#about to read 5, iclass 29, count 0 2006.196.08:04:38.65#ibcon#read 5, iclass 29, count 0 2006.196.08:04:38.65#ibcon#about to read 6, iclass 29, count 0 2006.196.08:04:38.65#ibcon#read 6, iclass 29, count 0 2006.196.08:04:38.65#ibcon#end of sib2, iclass 29, count 0 2006.196.08:04:38.65#ibcon#*after write, iclass 29, count 0 2006.196.08:04:38.65#ibcon#*before return 0, iclass 29, count 0 2006.196.08:04:38.65#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.196.08:04:38.65#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.196.08:04:38.65#ibcon#about to clear, iclass 29 cls_cnt 0 2006.196.08:04:38.65#ibcon#cleared, iclass 29 cls_cnt 0 2006.196.08:04:38.65$vc4f8/va=3,6 2006.196.08:04:38.65#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.196.08:04:38.65#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.196.08:04:38.65#ibcon#ireg 11 cls_cnt 2 2006.196.08:04:38.65#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.196.08:04:38.70#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.196.08:04:38.70#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.196.08:04:38.70#ibcon#enter wrdev, iclass 31, count 2 2006.196.08:04:38.70#ibcon#first serial, iclass 31, count 2 2006.196.08:04:38.70#ibcon#enter sib2, iclass 31, count 2 2006.196.08:04:38.70#ibcon#flushed, iclass 31, count 2 2006.196.08:04:38.70#ibcon#about to write, iclass 31, count 2 2006.196.08:04:38.70#ibcon#wrote, iclass 31, count 2 2006.196.08:04:38.70#ibcon#about to read 3, iclass 31, count 2 2006.196.08:04:38.72#ibcon#read 3, iclass 31, count 2 2006.196.08:04:38.72#ibcon#about to read 4, iclass 31, count 2 2006.196.08:04:38.72#ibcon#read 4, iclass 31, count 2 2006.196.08:04:38.72#ibcon#about to read 5, iclass 31, count 2 2006.196.08:04:38.72#ibcon#read 5, iclass 31, count 2 2006.196.08:04:38.72#ibcon#about to read 6, iclass 31, count 2 2006.196.08:04:38.72#ibcon#read 6, iclass 31, count 2 2006.196.08:04:38.72#ibcon#end of sib2, iclass 31, count 2 2006.196.08:04:38.72#ibcon#*mode == 0, iclass 31, count 2 2006.196.08:04:38.72#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.196.08:04:38.72#ibcon#[25=AT03-06\r\n] 2006.196.08:04:38.72#ibcon#*before write, iclass 31, count 2 2006.196.08:04:38.72#ibcon#enter sib2, iclass 31, count 2 2006.196.08:04:38.72#ibcon#flushed, iclass 31, count 2 2006.196.08:04:38.72#ibcon#about to write, iclass 31, count 2 2006.196.08:04:38.72#ibcon#wrote, iclass 31, count 2 2006.196.08:04:38.72#ibcon#about to read 3, iclass 31, count 2 2006.196.08:04:38.75#ibcon#read 3, iclass 31, count 2 2006.196.08:04:38.75#ibcon#about to read 4, iclass 31, count 2 2006.196.08:04:38.75#ibcon#read 4, iclass 31, count 2 2006.196.08:04:38.75#ibcon#about to read 5, iclass 31, count 2 2006.196.08:04:38.75#ibcon#read 5, iclass 31, count 2 2006.196.08:04:38.75#ibcon#about to read 6, iclass 31, count 2 2006.196.08:04:38.75#ibcon#read 6, iclass 31, count 2 2006.196.08:04:38.75#ibcon#end of sib2, iclass 31, count 2 2006.196.08:04:38.75#ibcon#*after write, iclass 31, count 2 2006.196.08:04:38.75#ibcon#*before return 0, iclass 31, count 2 2006.196.08:04:38.75#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.196.08:04:38.75#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.196.08:04:38.75#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.196.08:04:38.75#ibcon#ireg 7 cls_cnt 0 2006.196.08:04:38.75#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.196.08:04:38.87#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.196.08:04:38.87#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.196.08:04:38.87#ibcon#enter wrdev, iclass 31, count 0 2006.196.08:04:38.87#ibcon#first serial, iclass 31, count 0 2006.196.08:04:38.87#ibcon#enter sib2, iclass 31, count 0 2006.196.08:04:38.87#ibcon#flushed, iclass 31, count 0 2006.196.08:04:38.87#ibcon#about to write, iclass 31, count 0 2006.196.08:04:38.87#ibcon#wrote, iclass 31, count 0 2006.196.08:04:38.87#ibcon#about to read 3, iclass 31, count 0 2006.196.08:04:38.89#ibcon#read 3, iclass 31, count 0 2006.196.08:04:38.89#ibcon#about to read 4, iclass 31, count 0 2006.196.08:04:38.89#ibcon#read 4, iclass 31, count 0 2006.196.08:04:38.89#ibcon#about to read 5, iclass 31, count 0 2006.196.08:04:38.89#ibcon#read 5, iclass 31, count 0 2006.196.08:04:38.89#ibcon#about to read 6, iclass 31, count 0 2006.196.08:04:38.89#ibcon#read 6, iclass 31, count 0 2006.196.08:04:38.89#ibcon#end of sib2, iclass 31, count 0 2006.196.08:04:38.89#ibcon#*mode == 0, iclass 31, count 0 2006.196.08:04:38.89#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.196.08:04:38.89#ibcon#[25=USB\r\n] 2006.196.08:04:38.89#ibcon#*before write, iclass 31, count 0 2006.196.08:04:38.89#ibcon#enter sib2, iclass 31, count 0 2006.196.08:04:38.89#ibcon#flushed, iclass 31, count 0 2006.196.08:04:38.89#ibcon#about to write, iclass 31, count 0 2006.196.08:04:38.89#ibcon#wrote, iclass 31, count 0 2006.196.08:04:38.89#ibcon#about to read 3, iclass 31, count 0 2006.196.08:04:38.92#ibcon#read 3, iclass 31, count 0 2006.196.08:04:38.92#ibcon#about to read 4, iclass 31, count 0 2006.196.08:04:38.92#ibcon#read 4, iclass 31, count 0 2006.196.08:04:38.92#ibcon#about to read 5, iclass 31, count 0 2006.196.08:04:38.92#ibcon#read 5, iclass 31, count 0 2006.196.08:04:38.92#ibcon#about to read 6, iclass 31, count 0 2006.196.08:04:38.92#ibcon#read 6, iclass 31, count 0 2006.196.08:04:38.92#ibcon#end of sib2, iclass 31, count 0 2006.196.08:04:38.92#ibcon#*after write, iclass 31, count 0 2006.196.08:04:38.92#ibcon#*before return 0, iclass 31, count 0 2006.196.08:04:38.92#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.196.08:04:38.92#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.196.08:04:38.92#ibcon#about to clear, iclass 31 cls_cnt 0 2006.196.08:04:38.92#ibcon#cleared, iclass 31 cls_cnt 0 2006.196.08:04:38.92$vc4f8/valo=4,832.99 2006.196.08:04:38.92#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.196.08:04:38.92#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.196.08:04:38.92#ibcon#ireg 17 cls_cnt 0 2006.196.08:04:38.92#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:04:38.92#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:04:38.92#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:04:38.92#ibcon#enter wrdev, iclass 33, count 0 2006.196.08:04:38.92#ibcon#first serial, iclass 33, count 0 2006.196.08:04:38.92#ibcon#enter sib2, iclass 33, count 0 2006.196.08:04:38.92#ibcon#flushed, iclass 33, count 0 2006.196.08:04:38.92#ibcon#about to write, iclass 33, count 0 2006.196.08:04:38.92#ibcon#wrote, iclass 33, count 0 2006.196.08:04:38.92#ibcon#about to read 3, iclass 33, count 0 2006.196.08:04:38.94#ibcon#read 3, iclass 33, count 0 2006.196.08:04:38.94#ibcon#about to read 4, iclass 33, count 0 2006.196.08:04:38.94#ibcon#read 4, iclass 33, count 0 2006.196.08:04:38.94#ibcon#about to read 5, iclass 33, count 0 2006.196.08:04:38.94#ibcon#read 5, iclass 33, count 0 2006.196.08:04:38.94#ibcon#about to read 6, iclass 33, count 0 2006.196.08:04:38.94#ibcon#read 6, iclass 33, count 0 2006.196.08:04:38.94#ibcon#end of sib2, iclass 33, count 0 2006.196.08:04:38.94#ibcon#*mode == 0, iclass 33, count 0 2006.196.08:04:38.94#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.196.08:04:38.94#ibcon#[26=FRQ=04,832.99\r\n] 2006.196.08:04:38.94#ibcon#*before write, iclass 33, count 0 2006.196.08:04:38.94#ibcon#enter sib2, iclass 33, count 0 2006.196.08:04:38.94#ibcon#flushed, iclass 33, count 0 2006.196.08:04:38.94#ibcon#about to write, iclass 33, count 0 2006.196.08:04:38.94#ibcon#wrote, iclass 33, count 0 2006.196.08:04:38.94#ibcon#about to read 3, iclass 33, count 0 2006.196.08:04:38.98#ibcon#read 3, iclass 33, count 0 2006.196.08:04:38.98#ibcon#about to read 4, iclass 33, count 0 2006.196.08:04:38.98#ibcon#read 4, iclass 33, count 0 2006.196.08:04:38.98#ibcon#about to read 5, iclass 33, count 0 2006.196.08:04:38.98#ibcon#read 5, iclass 33, count 0 2006.196.08:04:38.98#ibcon#about to read 6, iclass 33, count 0 2006.196.08:04:38.98#ibcon#read 6, iclass 33, count 0 2006.196.08:04:38.98#ibcon#end of sib2, iclass 33, count 0 2006.196.08:04:38.98#ibcon#*after write, iclass 33, count 0 2006.196.08:04:38.98#ibcon#*before return 0, iclass 33, count 0 2006.196.08:04:38.98#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:04:38.98#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:04:38.98#ibcon#about to clear, iclass 33 cls_cnt 0 2006.196.08:04:38.98#ibcon#cleared, iclass 33 cls_cnt 0 2006.196.08:04:38.98$vc4f8/va=4,7 2006.196.08:04:38.98#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.196.08:04:38.98#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.196.08:04:38.98#ibcon#ireg 11 cls_cnt 2 2006.196.08:04:38.98#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.196.08:04:39.04#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.196.08:04:39.04#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.196.08:04:39.04#ibcon#enter wrdev, iclass 35, count 2 2006.196.08:04:39.04#ibcon#first serial, iclass 35, count 2 2006.196.08:04:39.04#ibcon#enter sib2, iclass 35, count 2 2006.196.08:04:39.04#ibcon#flushed, iclass 35, count 2 2006.196.08:04:39.04#ibcon#about to write, iclass 35, count 2 2006.196.08:04:39.04#ibcon#wrote, iclass 35, count 2 2006.196.08:04:39.04#ibcon#about to read 3, iclass 35, count 2 2006.196.08:04:39.06#ibcon#read 3, iclass 35, count 2 2006.196.08:04:39.06#ibcon#about to read 4, iclass 35, count 2 2006.196.08:04:39.06#ibcon#read 4, iclass 35, count 2 2006.196.08:04:39.06#ibcon#about to read 5, iclass 35, count 2 2006.196.08:04:39.06#ibcon#read 5, iclass 35, count 2 2006.196.08:04:39.06#ibcon#about to read 6, iclass 35, count 2 2006.196.08:04:39.06#ibcon#read 6, iclass 35, count 2 2006.196.08:04:39.06#ibcon#end of sib2, iclass 35, count 2 2006.196.08:04:39.06#ibcon#*mode == 0, iclass 35, count 2 2006.196.08:04:39.06#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.196.08:04:39.06#ibcon#[25=AT04-07\r\n] 2006.196.08:04:39.06#ibcon#*before write, iclass 35, count 2 2006.196.08:04:39.06#ibcon#enter sib2, iclass 35, count 2 2006.196.08:04:39.06#ibcon#flushed, iclass 35, count 2 2006.196.08:04:39.06#ibcon#about to write, iclass 35, count 2 2006.196.08:04:39.06#ibcon#wrote, iclass 35, count 2 2006.196.08:04:39.06#ibcon#about to read 3, iclass 35, count 2 2006.196.08:04:39.09#ibcon#read 3, iclass 35, count 2 2006.196.08:04:39.09#ibcon#about to read 4, iclass 35, count 2 2006.196.08:04:39.09#ibcon#read 4, iclass 35, count 2 2006.196.08:04:39.09#ibcon#about to read 5, iclass 35, count 2 2006.196.08:04:39.09#ibcon#read 5, iclass 35, count 2 2006.196.08:04:39.09#ibcon#about to read 6, iclass 35, count 2 2006.196.08:04:39.09#ibcon#read 6, iclass 35, count 2 2006.196.08:04:39.09#ibcon#end of sib2, iclass 35, count 2 2006.196.08:04:39.09#ibcon#*after write, iclass 35, count 2 2006.196.08:04:39.09#ibcon#*before return 0, iclass 35, count 2 2006.196.08:04:39.09#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.196.08:04:39.09#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.196.08:04:39.09#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.196.08:04:39.09#ibcon#ireg 7 cls_cnt 0 2006.196.08:04:39.09#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.196.08:04:39.21#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.196.08:04:39.21#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.196.08:04:39.21#ibcon#enter wrdev, iclass 35, count 0 2006.196.08:04:39.21#ibcon#first serial, iclass 35, count 0 2006.196.08:04:39.21#ibcon#enter sib2, iclass 35, count 0 2006.196.08:04:39.21#ibcon#flushed, iclass 35, count 0 2006.196.08:04:39.21#ibcon#about to write, iclass 35, count 0 2006.196.08:04:39.21#ibcon#wrote, iclass 35, count 0 2006.196.08:04:39.21#ibcon#about to read 3, iclass 35, count 0 2006.196.08:04:39.23#ibcon#read 3, iclass 35, count 0 2006.196.08:04:39.23#ibcon#about to read 4, iclass 35, count 0 2006.196.08:04:39.23#ibcon#read 4, iclass 35, count 0 2006.196.08:04:39.23#ibcon#about to read 5, iclass 35, count 0 2006.196.08:04:39.23#ibcon#read 5, iclass 35, count 0 2006.196.08:04:39.23#ibcon#about to read 6, iclass 35, count 0 2006.196.08:04:39.23#ibcon#read 6, iclass 35, count 0 2006.196.08:04:39.23#ibcon#end of sib2, iclass 35, count 0 2006.196.08:04:39.23#ibcon#*mode == 0, iclass 35, count 0 2006.196.08:04:39.23#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.196.08:04:39.23#ibcon#[25=USB\r\n] 2006.196.08:04:39.23#ibcon#*before write, iclass 35, count 0 2006.196.08:04:39.23#ibcon#enter sib2, iclass 35, count 0 2006.196.08:04:39.23#ibcon#flushed, iclass 35, count 0 2006.196.08:04:39.23#ibcon#about to write, iclass 35, count 0 2006.196.08:04:39.23#ibcon#wrote, iclass 35, count 0 2006.196.08:04:39.23#ibcon#about to read 3, iclass 35, count 0 2006.196.08:04:39.26#ibcon#read 3, iclass 35, count 0 2006.196.08:04:39.26#ibcon#about to read 4, iclass 35, count 0 2006.196.08:04:39.26#ibcon#read 4, iclass 35, count 0 2006.196.08:04:39.26#ibcon#about to read 5, iclass 35, count 0 2006.196.08:04:39.26#ibcon#read 5, iclass 35, count 0 2006.196.08:04:39.26#ibcon#about to read 6, iclass 35, count 0 2006.196.08:04:39.26#ibcon#read 6, iclass 35, count 0 2006.196.08:04:39.26#ibcon#end of sib2, iclass 35, count 0 2006.196.08:04:39.26#ibcon#*after write, iclass 35, count 0 2006.196.08:04:39.26#ibcon#*before return 0, iclass 35, count 0 2006.196.08:04:39.26#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.196.08:04:39.26#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.196.08:04:39.26#ibcon#about to clear, iclass 35 cls_cnt 0 2006.196.08:04:39.26#ibcon#cleared, iclass 35 cls_cnt 0 2006.196.08:04:39.26$vc4f8/valo=5,652.99 2006.196.08:04:39.26#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.196.08:04:39.26#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.196.08:04:39.26#ibcon#ireg 17 cls_cnt 0 2006.196.08:04:39.26#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.196.08:04:39.26#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.196.08:04:39.26#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.196.08:04:39.26#ibcon#enter wrdev, iclass 37, count 0 2006.196.08:04:39.26#ibcon#first serial, iclass 37, count 0 2006.196.08:04:39.26#ibcon#enter sib2, iclass 37, count 0 2006.196.08:04:39.26#ibcon#flushed, iclass 37, count 0 2006.196.08:04:39.26#ibcon#about to write, iclass 37, count 0 2006.196.08:04:39.26#ibcon#wrote, iclass 37, count 0 2006.196.08:04:39.26#ibcon#about to read 3, iclass 37, count 0 2006.196.08:04:39.28#ibcon#read 3, iclass 37, count 0 2006.196.08:04:39.28#ibcon#about to read 4, iclass 37, count 0 2006.196.08:04:39.28#ibcon#read 4, iclass 37, count 0 2006.196.08:04:39.28#ibcon#about to read 5, iclass 37, count 0 2006.196.08:04:39.28#ibcon#read 5, iclass 37, count 0 2006.196.08:04:39.28#ibcon#about to read 6, iclass 37, count 0 2006.196.08:04:39.28#ibcon#read 6, iclass 37, count 0 2006.196.08:04:39.28#ibcon#end of sib2, iclass 37, count 0 2006.196.08:04:39.28#ibcon#*mode == 0, iclass 37, count 0 2006.196.08:04:39.28#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.196.08:04:39.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.196.08:04:39.28#ibcon#*before write, iclass 37, count 0 2006.196.08:04:39.28#ibcon#enter sib2, iclass 37, count 0 2006.196.08:04:39.28#ibcon#flushed, iclass 37, count 0 2006.196.08:04:39.28#ibcon#about to write, iclass 37, count 0 2006.196.08:04:39.28#ibcon#wrote, iclass 37, count 0 2006.196.08:04:39.28#ibcon#about to read 3, iclass 37, count 0 2006.196.08:04:39.32#ibcon#read 3, iclass 37, count 0 2006.196.08:04:39.32#ibcon#about to read 4, iclass 37, count 0 2006.196.08:04:39.32#ibcon#read 4, iclass 37, count 0 2006.196.08:04:39.32#ibcon#about to read 5, iclass 37, count 0 2006.196.08:04:39.32#ibcon#read 5, iclass 37, count 0 2006.196.08:04:39.32#ibcon#about to read 6, iclass 37, count 0 2006.196.08:04:39.32#ibcon#read 6, iclass 37, count 0 2006.196.08:04:39.32#ibcon#end of sib2, iclass 37, count 0 2006.196.08:04:39.32#ibcon#*after write, iclass 37, count 0 2006.196.08:04:39.32#ibcon#*before return 0, iclass 37, count 0 2006.196.08:04:39.32#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.196.08:04:39.32#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.196.08:04:39.32#ibcon#about to clear, iclass 37 cls_cnt 0 2006.196.08:04:39.32#ibcon#cleared, iclass 37 cls_cnt 0 2006.196.08:04:39.32$vc4f8/va=5,7 2006.196.08:04:39.32#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.196.08:04:39.32#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.196.08:04:39.32#ibcon#ireg 11 cls_cnt 2 2006.196.08:04:39.32#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.196.08:04:39.38#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.196.08:04:39.38#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.196.08:04:39.38#ibcon#enter wrdev, iclass 39, count 2 2006.196.08:04:39.38#ibcon#first serial, iclass 39, count 2 2006.196.08:04:39.38#ibcon#enter sib2, iclass 39, count 2 2006.196.08:04:39.38#ibcon#flushed, iclass 39, count 2 2006.196.08:04:39.38#ibcon#about to write, iclass 39, count 2 2006.196.08:04:39.38#ibcon#wrote, iclass 39, count 2 2006.196.08:04:39.38#ibcon#about to read 3, iclass 39, count 2 2006.196.08:04:39.40#ibcon#read 3, iclass 39, count 2 2006.196.08:04:39.40#ibcon#about to read 4, iclass 39, count 2 2006.196.08:04:39.40#ibcon#read 4, iclass 39, count 2 2006.196.08:04:39.40#ibcon#about to read 5, iclass 39, count 2 2006.196.08:04:39.40#ibcon#read 5, iclass 39, count 2 2006.196.08:04:39.40#ibcon#about to read 6, iclass 39, count 2 2006.196.08:04:39.40#ibcon#read 6, iclass 39, count 2 2006.196.08:04:39.40#ibcon#end of sib2, iclass 39, count 2 2006.196.08:04:39.40#ibcon#*mode == 0, iclass 39, count 2 2006.196.08:04:39.40#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.196.08:04:39.40#ibcon#[25=AT05-07\r\n] 2006.196.08:04:39.40#ibcon#*before write, iclass 39, count 2 2006.196.08:04:39.40#ibcon#enter sib2, iclass 39, count 2 2006.196.08:04:39.40#ibcon#flushed, iclass 39, count 2 2006.196.08:04:39.40#ibcon#about to write, iclass 39, count 2 2006.196.08:04:39.40#ibcon#wrote, iclass 39, count 2 2006.196.08:04:39.40#ibcon#about to read 3, iclass 39, count 2 2006.196.08:04:39.43#ibcon#read 3, iclass 39, count 2 2006.196.08:04:39.43#ibcon#about to read 4, iclass 39, count 2 2006.196.08:04:39.43#ibcon#read 4, iclass 39, count 2 2006.196.08:04:39.43#ibcon#about to read 5, iclass 39, count 2 2006.196.08:04:39.43#ibcon#read 5, iclass 39, count 2 2006.196.08:04:39.43#ibcon#about to read 6, iclass 39, count 2 2006.196.08:04:39.43#ibcon#read 6, iclass 39, count 2 2006.196.08:04:39.43#ibcon#end of sib2, iclass 39, count 2 2006.196.08:04:39.43#ibcon#*after write, iclass 39, count 2 2006.196.08:04:39.43#ibcon#*before return 0, iclass 39, count 2 2006.196.08:04:39.43#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.196.08:04:39.43#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.196.08:04:39.43#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.196.08:04:39.43#ibcon#ireg 7 cls_cnt 0 2006.196.08:04:39.43#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.196.08:04:39.55#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.196.08:04:39.55#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.196.08:04:39.55#ibcon#enter wrdev, iclass 39, count 0 2006.196.08:04:39.55#ibcon#first serial, iclass 39, count 0 2006.196.08:04:39.55#ibcon#enter sib2, iclass 39, count 0 2006.196.08:04:39.55#ibcon#flushed, iclass 39, count 0 2006.196.08:04:39.55#ibcon#about to write, iclass 39, count 0 2006.196.08:04:39.55#ibcon#wrote, iclass 39, count 0 2006.196.08:04:39.55#ibcon#about to read 3, iclass 39, count 0 2006.196.08:04:39.57#ibcon#read 3, iclass 39, count 0 2006.196.08:04:39.57#ibcon#about to read 4, iclass 39, count 0 2006.196.08:04:39.57#ibcon#read 4, iclass 39, count 0 2006.196.08:04:39.57#ibcon#about to read 5, iclass 39, count 0 2006.196.08:04:39.57#ibcon#read 5, iclass 39, count 0 2006.196.08:04:39.57#ibcon#about to read 6, iclass 39, count 0 2006.196.08:04:39.57#ibcon#read 6, iclass 39, count 0 2006.196.08:04:39.57#ibcon#end of sib2, iclass 39, count 0 2006.196.08:04:39.57#ibcon#*mode == 0, iclass 39, count 0 2006.196.08:04:39.57#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.196.08:04:39.57#ibcon#[25=USB\r\n] 2006.196.08:04:39.57#ibcon#*before write, iclass 39, count 0 2006.196.08:04:39.57#ibcon#enter sib2, iclass 39, count 0 2006.196.08:04:39.57#ibcon#flushed, iclass 39, count 0 2006.196.08:04:39.57#ibcon#about to write, iclass 39, count 0 2006.196.08:04:39.57#ibcon#wrote, iclass 39, count 0 2006.196.08:04:39.57#ibcon#about to read 3, iclass 39, count 0 2006.196.08:04:39.60#ibcon#read 3, iclass 39, count 0 2006.196.08:04:39.60#ibcon#about to read 4, iclass 39, count 0 2006.196.08:04:39.60#ibcon#read 4, iclass 39, count 0 2006.196.08:04:39.60#ibcon#about to read 5, iclass 39, count 0 2006.196.08:04:39.60#ibcon#read 5, iclass 39, count 0 2006.196.08:04:39.60#ibcon#about to read 6, iclass 39, count 0 2006.196.08:04:39.60#ibcon#read 6, iclass 39, count 0 2006.196.08:04:39.60#ibcon#end of sib2, iclass 39, count 0 2006.196.08:04:39.60#ibcon#*after write, iclass 39, count 0 2006.196.08:04:39.60#ibcon#*before return 0, iclass 39, count 0 2006.196.08:04:39.60#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.196.08:04:39.60#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.196.08:04:39.60#ibcon#about to clear, iclass 39 cls_cnt 0 2006.196.08:04:39.60#ibcon#cleared, iclass 39 cls_cnt 0 2006.196.08:04:39.60$vc4f8/valo=6,772.99 2006.196.08:04:39.60#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.196.08:04:39.60#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.196.08:04:39.60#ibcon#ireg 17 cls_cnt 0 2006.196.08:04:39.60#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.196.08:04:39.60#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.196.08:04:39.60#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.196.08:04:39.60#ibcon#enter wrdev, iclass 3, count 0 2006.196.08:04:39.60#ibcon#first serial, iclass 3, count 0 2006.196.08:04:39.60#ibcon#enter sib2, iclass 3, count 0 2006.196.08:04:39.60#ibcon#flushed, iclass 3, count 0 2006.196.08:04:39.60#ibcon#about to write, iclass 3, count 0 2006.196.08:04:39.60#ibcon#wrote, iclass 3, count 0 2006.196.08:04:39.60#ibcon#about to read 3, iclass 3, count 0 2006.196.08:04:39.62#ibcon#read 3, iclass 3, count 0 2006.196.08:04:39.62#ibcon#about to read 4, iclass 3, count 0 2006.196.08:04:39.62#ibcon#read 4, iclass 3, count 0 2006.196.08:04:39.62#ibcon#about to read 5, iclass 3, count 0 2006.196.08:04:39.62#ibcon#read 5, iclass 3, count 0 2006.196.08:04:39.62#ibcon#about to read 6, iclass 3, count 0 2006.196.08:04:39.62#ibcon#read 6, iclass 3, count 0 2006.196.08:04:39.62#ibcon#end of sib2, iclass 3, count 0 2006.196.08:04:39.62#ibcon#*mode == 0, iclass 3, count 0 2006.196.08:04:39.62#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.196.08:04:39.62#ibcon#[26=FRQ=06,772.99\r\n] 2006.196.08:04:39.62#ibcon#*before write, iclass 3, count 0 2006.196.08:04:39.62#ibcon#enter sib2, iclass 3, count 0 2006.196.08:04:39.62#ibcon#flushed, iclass 3, count 0 2006.196.08:04:39.62#ibcon#about to write, iclass 3, count 0 2006.196.08:04:39.62#ibcon#wrote, iclass 3, count 0 2006.196.08:04:39.62#ibcon#about to read 3, iclass 3, count 0 2006.196.08:04:39.66#ibcon#read 3, iclass 3, count 0 2006.196.08:04:39.66#ibcon#about to read 4, iclass 3, count 0 2006.196.08:04:39.66#ibcon#read 4, iclass 3, count 0 2006.196.08:04:39.66#ibcon#about to read 5, iclass 3, count 0 2006.196.08:04:39.66#ibcon#read 5, iclass 3, count 0 2006.196.08:04:39.66#ibcon#about to read 6, iclass 3, count 0 2006.196.08:04:39.66#ibcon#read 6, iclass 3, count 0 2006.196.08:04:39.66#ibcon#end of sib2, iclass 3, count 0 2006.196.08:04:39.66#ibcon#*after write, iclass 3, count 0 2006.196.08:04:39.66#ibcon#*before return 0, iclass 3, count 0 2006.196.08:04:39.66#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.196.08:04:39.66#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.196.08:04:39.66#ibcon#about to clear, iclass 3 cls_cnt 0 2006.196.08:04:39.66#ibcon#cleared, iclass 3 cls_cnt 0 2006.196.08:04:39.66$vc4f8/va=6,6 2006.196.08:04:39.66#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.196.08:04:39.66#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.196.08:04:39.66#ibcon#ireg 11 cls_cnt 2 2006.196.08:04:39.66#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.196.08:04:39.72#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.196.08:04:39.72#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.196.08:04:39.72#ibcon#enter wrdev, iclass 5, count 2 2006.196.08:04:39.72#ibcon#first serial, iclass 5, count 2 2006.196.08:04:39.72#ibcon#enter sib2, iclass 5, count 2 2006.196.08:04:39.72#ibcon#flushed, iclass 5, count 2 2006.196.08:04:39.72#ibcon#about to write, iclass 5, count 2 2006.196.08:04:39.72#ibcon#wrote, iclass 5, count 2 2006.196.08:04:39.72#ibcon#about to read 3, iclass 5, count 2 2006.196.08:04:39.74#ibcon#read 3, iclass 5, count 2 2006.196.08:04:39.74#ibcon#about to read 4, iclass 5, count 2 2006.196.08:04:39.74#ibcon#read 4, iclass 5, count 2 2006.196.08:04:39.74#ibcon#about to read 5, iclass 5, count 2 2006.196.08:04:39.74#ibcon#read 5, iclass 5, count 2 2006.196.08:04:39.74#ibcon#about to read 6, iclass 5, count 2 2006.196.08:04:39.74#ibcon#read 6, iclass 5, count 2 2006.196.08:04:39.74#ibcon#end of sib2, iclass 5, count 2 2006.196.08:04:39.74#ibcon#*mode == 0, iclass 5, count 2 2006.196.08:04:39.74#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.196.08:04:39.74#ibcon#[25=AT06-06\r\n] 2006.196.08:04:39.74#ibcon#*before write, iclass 5, count 2 2006.196.08:04:39.74#ibcon#enter sib2, iclass 5, count 2 2006.196.08:04:39.74#ibcon#flushed, iclass 5, count 2 2006.196.08:04:39.74#ibcon#about to write, iclass 5, count 2 2006.196.08:04:39.74#ibcon#wrote, iclass 5, count 2 2006.196.08:04:39.74#ibcon#about to read 3, iclass 5, count 2 2006.196.08:04:39.77#ibcon#read 3, iclass 5, count 2 2006.196.08:04:39.77#ibcon#about to read 4, iclass 5, count 2 2006.196.08:04:39.77#ibcon#read 4, iclass 5, count 2 2006.196.08:04:39.77#ibcon#about to read 5, iclass 5, count 2 2006.196.08:04:39.77#ibcon#read 5, iclass 5, count 2 2006.196.08:04:39.77#ibcon#about to read 6, iclass 5, count 2 2006.196.08:04:39.77#ibcon#read 6, iclass 5, count 2 2006.196.08:04:39.77#ibcon#end of sib2, iclass 5, count 2 2006.196.08:04:39.77#ibcon#*after write, iclass 5, count 2 2006.196.08:04:39.77#ibcon#*before return 0, iclass 5, count 2 2006.196.08:04:39.77#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.196.08:04:39.77#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.196.08:04:39.77#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.196.08:04:39.77#ibcon#ireg 7 cls_cnt 0 2006.196.08:04:39.77#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.196.08:04:39.89#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.196.08:04:39.89#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.196.08:04:39.89#ibcon#enter wrdev, iclass 5, count 0 2006.196.08:04:39.89#ibcon#first serial, iclass 5, count 0 2006.196.08:04:39.89#ibcon#enter sib2, iclass 5, count 0 2006.196.08:04:39.89#ibcon#flushed, iclass 5, count 0 2006.196.08:04:39.89#ibcon#about to write, iclass 5, count 0 2006.196.08:04:39.89#ibcon#wrote, iclass 5, count 0 2006.196.08:04:39.89#ibcon#about to read 3, iclass 5, count 0 2006.196.08:04:39.91#ibcon#read 3, iclass 5, count 0 2006.196.08:04:39.91#ibcon#about to read 4, iclass 5, count 0 2006.196.08:04:39.91#ibcon#read 4, iclass 5, count 0 2006.196.08:04:39.91#ibcon#about to read 5, iclass 5, count 0 2006.196.08:04:39.91#ibcon#read 5, iclass 5, count 0 2006.196.08:04:39.91#ibcon#about to read 6, iclass 5, count 0 2006.196.08:04:39.91#ibcon#read 6, iclass 5, count 0 2006.196.08:04:39.91#ibcon#end of sib2, iclass 5, count 0 2006.196.08:04:39.91#ibcon#*mode == 0, iclass 5, count 0 2006.196.08:04:39.91#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.196.08:04:39.91#ibcon#[25=USB\r\n] 2006.196.08:04:39.91#ibcon#*before write, iclass 5, count 0 2006.196.08:04:39.91#ibcon#enter sib2, iclass 5, count 0 2006.196.08:04:39.91#ibcon#flushed, iclass 5, count 0 2006.196.08:04:39.91#ibcon#about to write, iclass 5, count 0 2006.196.08:04:39.91#ibcon#wrote, iclass 5, count 0 2006.196.08:04:39.91#ibcon#about to read 3, iclass 5, count 0 2006.196.08:04:39.94#ibcon#read 3, iclass 5, count 0 2006.196.08:04:39.94#ibcon#about to read 4, iclass 5, count 0 2006.196.08:04:39.94#ibcon#read 4, iclass 5, count 0 2006.196.08:04:39.94#ibcon#about to read 5, iclass 5, count 0 2006.196.08:04:39.94#ibcon#read 5, iclass 5, count 0 2006.196.08:04:39.94#ibcon#about to read 6, iclass 5, count 0 2006.196.08:04:39.94#ibcon#read 6, iclass 5, count 0 2006.196.08:04:39.94#ibcon#end of sib2, iclass 5, count 0 2006.196.08:04:39.94#ibcon#*after write, iclass 5, count 0 2006.196.08:04:39.94#ibcon#*before return 0, iclass 5, count 0 2006.196.08:04:39.94#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.196.08:04:39.94#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.196.08:04:39.94#ibcon#about to clear, iclass 5 cls_cnt 0 2006.196.08:04:39.94#ibcon#cleared, iclass 5 cls_cnt 0 2006.196.08:04:39.94$vc4f8/valo=7,832.99 2006.196.08:04:39.94#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.196.08:04:39.94#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.196.08:04:39.94#ibcon#ireg 17 cls_cnt 0 2006.196.08:04:39.94#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.196.08:04:39.94#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.196.08:04:39.94#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.196.08:04:39.94#ibcon#enter wrdev, iclass 7, count 0 2006.196.08:04:39.94#ibcon#first serial, iclass 7, count 0 2006.196.08:04:39.94#ibcon#enter sib2, iclass 7, count 0 2006.196.08:04:39.94#ibcon#flushed, iclass 7, count 0 2006.196.08:04:39.94#ibcon#about to write, iclass 7, count 0 2006.196.08:04:39.94#ibcon#wrote, iclass 7, count 0 2006.196.08:04:39.94#ibcon#about to read 3, iclass 7, count 0 2006.196.08:04:39.96#ibcon#read 3, iclass 7, count 0 2006.196.08:04:39.96#ibcon#about to read 4, iclass 7, count 0 2006.196.08:04:39.96#ibcon#read 4, iclass 7, count 0 2006.196.08:04:39.96#ibcon#about to read 5, iclass 7, count 0 2006.196.08:04:39.96#ibcon#read 5, iclass 7, count 0 2006.196.08:04:39.96#ibcon#about to read 6, iclass 7, count 0 2006.196.08:04:39.96#ibcon#read 6, iclass 7, count 0 2006.196.08:04:39.96#ibcon#end of sib2, iclass 7, count 0 2006.196.08:04:39.96#ibcon#*mode == 0, iclass 7, count 0 2006.196.08:04:39.96#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.196.08:04:39.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.196.08:04:39.96#ibcon#*before write, iclass 7, count 0 2006.196.08:04:39.96#ibcon#enter sib2, iclass 7, count 0 2006.196.08:04:39.96#ibcon#flushed, iclass 7, count 0 2006.196.08:04:39.96#ibcon#about to write, iclass 7, count 0 2006.196.08:04:39.96#ibcon#wrote, iclass 7, count 0 2006.196.08:04:39.96#ibcon#about to read 3, iclass 7, count 0 2006.196.08:04:40.00#ibcon#read 3, iclass 7, count 0 2006.196.08:04:40.00#ibcon#about to read 4, iclass 7, count 0 2006.196.08:04:40.00#ibcon#read 4, iclass 7, count 0 2006.196.08:04:40.00#ibcon#about to read 5, iclass 7, count 0 2006.196.08:04:40.00#ibcon#read 5, iclass 7, count 0 2006.196.08:04:40.00#ibcon#about to read 6, iclass 7, count 0 2006.196.08:04:40.00#ibcon#read 6, iclass 7, count 0 2006.196.08:04:40.00#ibcon#end of sib2, iclass 7, count 0 2006.196.08:04:40.00#ibcon#*after write, iclass 7, count 0 2006.196.08:04:40.00#ibcon#*before return 0, iclass 7, count 0 2006.196.08:04:40.00#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.196.08:04:40.00#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.196.08:04:40.00#ibcon#about to clear, iclass 7 cls_cnt 0 2006.196.08:04:40.00#ibcon#cleared, iclass 7 cls_cnt 0 2006.196.08:04:40.00$vc4f8/va=7,6 2006.196.08:04:40.00#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.196.08:04:40.00#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.196.08:04:40.00#ibcon#ireg 11 cls_cnt 2 2006.196.08:04:40.00#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.196.08:04:40.06#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.196.08:04:40.06#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.196.08:04:40.06#ibcon#enter wrdev, iclass 11, count 2 2006.196.08:04:40.06#ibcon#first serial, iclass 11, count 2 2006.196.08:04:40.06#ibcon#enter sib2, iclass 11, count 2 2006.196.08:04:40.06#ibcon#flushed, iclass 11, count 2 2006.196.08:04:40.06#ibcon#about to write, iclass 11, count 2 2006.196.08:04:40.06#ibcon#wrote, iclass 11, count 2 2006.196.08:04:40.06#ibcon#about to read 3, iclass 11, count 2 2006.196.08:04:40.08#ibcon#read 3, iclass 11, count 2 2006.196.08:04:40.08#ibcon#about to read 4, iclass 11, count 2 2006.196.08:04:40.08#ibcon#read 4, iclass 11, count 2 2006.196.08:04:40.08#ibcon#about to read 5, iclass 11, count 2 2006.196.08:04:40.08#ibcon#read 5, iclass 11, count 2 2006.196.08:04:40.08#ibcon#about to read 6, iclass 11, count 2 2006.196.08:04:40.08#ibcon#read 6, iclass 11, count 2 2006.196.08:04:40.08#ibcon#end of sib2, iclass 11, count 2 2006.196.08:04:40.08#ibcon#*mode == 0, iclass 11, count 2 2006.196.08:04:40.08#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.196.08:04:40.08#ibcon#[25=AT07-06\r\n] 2006.196.08:04:40.08#ibcon#*before write, iclass 11, count 2 2006.196.08:04:40.08#ibcon#enter sib2, iclass 11, count 2 2006.196.08:04:40.08#ibcon#flushed, iclass 11, count 2 2006.196.08:04:40.08#ibcon#about to write, iclass 11, count 2 2006.196.08:04:40.08#ibcon#wrote, iclass 11, count 2 2006.196.08:04:40.08#ibcon#about to read 3, iclass 11, count 2 2006.196.08:04:40.11#ibcon#read 3, iclass 11, count 2 2006.196.08:04:40.11#ibcon#about to read 4, iclass 11, count 2 2006.196.08:04:40.11#ibcon#read 4, iclass 11, count 2 2006.196.08:04:40.11#ibcon#about to read 5, iclass 11, count 2 2006.196.08:04:40.11#ibcon#read 5, iclass 11, count 2 2006.196.08:04:40.11#ibcon#about to read 6, iclass 11, count 2 2006.196.08:04:40.11#ibcon#read 6, iclass 11, count 2 2006.196.08:04:40.11#ibcon#end of sib2, iclass 11, count 2 2006.196.08:04:40.11#ibcon#*after write, iclass 11, count 2 2006.196.08:04:40.11#ibcon#*before return 0, iclass 11, count 2 2006.196.08:04:40.11#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.196.08:04:40.11#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.196.08:04:40.11#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.196.08:04:40.11#ibcon#ireg 7 cls_cnt 0 2006.196.08:04:40.11#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.196.08:04:40.23#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.196.08:04:40.23#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.196.08:04:40.23#ibcon#enter wrdev, iclass 11, count 0 2006.196.08:04:40.23#ibcon#first serial, iclass 11, count 0 2006.196.08:04:40.23#ibcon#enter sib2, iclass 11, count 0 2006.196.08:04:40.23#ibcon#flushed, iclass 11, count 0 2006.196.08:04:40.23#ibcon#about to write, iclass 11, count 0 2006.196.08:04:40.23#ibcon#wrote, iclass 11, count 0 2006.196.08:04:40.23#ibcon#about to read 3, iclass 11, count 0 2006.196.08:04:40.25#ibcon#read 3, iclass 11, count 0 2006.196.08:04:40.25#ibcon#about to read 4, iclass 11, count 0 2006.196.08:04:40.25#ibcon#read 4, iclass 11, count 0 2006.196.08:04:40.25#ibcon#about to read 5, iclass 11, count 0 2006.196.08:04:40.25#ibcon#read 5, iclass 11, count 0 2006.196.08:04:40.25#ibcon#about to read 6, iclass 11, count 0 2006.196.08:04:40.25#ibcon#read 6, iclass 11, count 0 2006.196.08:04:40.25#ibcon#end of sib2, iclass 11, count 0 2006.196.08:04:40.25#ibcon#*mode == 0, iclass 11, count 0 2006.196.08:04:40.25#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.196.08:04:40.25#ibcon#[25=USB\r\n] 2006.196.08:04:40.25#ibcon#*before write, iclass 11, count 0 2006.196.08:04:40.25#ibcon#enter sib2, iclass 11, count 0 2006.196.08:04:40.25#ibcon#flushed, iclass 11, count 0 2006.196.08:04:40.25#ibcon#about to write, iclass 11, count 0 2006.196.08:04:40.25#ibcon#wrote, iclass 11, count 0 2006.196.08:04:40.25#ibcon#about to read 3, iclass 11, count 0 2006.196.08:04:40.28#ibcon#read 3, iclass 11, count 0 2006.196.08:04:40.28#ibcon#about to read 4, iclass 11, count 0 2006.196.08:04:40.28#ibcon#read 4, iclass 11, count 0 2006.196.08:04:40.28#ibcon#about to read 5, iclass 11, count 0 2006.196.08:04:40.28#ibcon#read 5, iclass 11, count 0 2006.196.08:04:40.28#ibcon#about to read 6, iclass 11, count 0 2006.196.08:04:40.28#ibcon#read 6, iclass 11, count 0 2006.196.08:04:40.28#ibcon#end of sib2, iclass 11, count 0 2006.196.08:04:40.28#ibcon#*after write, iclass 11, count 0 2006.196.08:04:40.28#ibcon#*before return 0, iclass 11, count 0 2006.196.08:04:40.28#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.196.08:04:40.28#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.196.08:04:40.28#ibcon#about to clear, iclass 11 cls_cnt 0 2006.196.08:04:40.28#ibcon#cleared, iclass 11 cls_cnt 0 2006.196.08:04:40.28$vc4f8/valo=8,852.99 2006.196.08:04:40.28#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.196.08:04:40.28#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.196.08:04:40.28#ibcon#ireg 17 cls_cnt 0 2006.196.08:04:40.28#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.196.08:04:40.28#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.196.08:04:40.28#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.196.08:04:40.28#ibcon#enter wrdev, iclass 13, count 0 2006.196.08:04:40.28#ibcon#first serial, iclass 13, count 0 2006.196.08:04:40.28#ibcon#enter sib2, iclass 13, count 0 2006.196.08:04:40.28#ibcon#flushed, iclass 13, count 0 2006.196.08:04:40.28#ibcon#about to write, iclass 13, count 0 2006.196.08:04:40.28#ibcon#wrote, iclass 13, count 0 2006.196.08:04:40.28#ibcon#about to read 3, iclass 13, count 0 2006.196.08:04:40.30#ibcon#read 3, iclass 13, count 0 2006.196.08:04:40.30#ibcon#about to read 4, iclass 13, count 0 2006.196.08:04:40.30#ibcon#read 4, iclass 13, count 0 2006.196.08:04:40.30#ibcon#about to read 5, iclass 13, count 0 2006.196.08:04:40.30#ibcon#read 5, iclass 13, count 0 2006.196.08:04:40.30#ibcon#about to read 6, iclass 13, count 0 2006.196.08:04:40.30#ibcon#read 6, iclass 13, count 0 2006.196.08:04:40.30#ibcon#end of sib2, iclass 13, count 0 2006.196.08:04:40.30#ibcon#*mode == 0, iclass 13, count 0 2006.196.08:04:40.30#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.196.08:04:40.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.196.08:04:40.30#ibcon#*before write, iclass 13, count 0 2006.196.08:04:40.30#ibcon#enter sib2, iclass 13, count 0 2006.196.08:04:40.30#ibcon#flushed, iclass 13, count 0 2006.196.08:04:40.30#ibcon#about to write, iclass 13, count 0 2006.196.08:04:40.30#ibcon#wrote, iclass 13, count 0 2006.196.08:04:40.30#ibcon#about to read 3, iclass 13, count 0 2006.196.08:04:40.35#ibcon#read 3, iclass 13, count 0 2006.196.08:04:40.35#ibcon#about to read 4, iclass 13, count 0 2006.196.08:04:40.35#ibcon#read 4, iclass 13, count 0 2006.196.08:04:40.35#ibcon#about to read 5, iclass 13, count 0 2006.196.08:04:40.35#ibcon#read 5, iclass 13, count 0 2006.196.08:04:40.35#ibcon#about to read 6, iclass 13, count 0 2006.196.08:04:40.35#ibcon#read 6, iclass 13, count 0 2006.196.08:04:40.35#ibcon#end of sib2, iclass 13, count 0 2006.196.08:04:40.35#ibcon#*after write, iclass 13, count 0 2006.196.08:04:40.35#ibcon#*before return 0, iclass 13, count 0 2006.196.08:04:40.35#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.196.08:04:40.35#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.196.08:04:40.35#ibcon#about to clear, iclass 13 cls_cnt 0 2006.196.08:04:40.35#ibcon#cleared, iclass 13 cls_cnt 0 2006.196.08:04:40.35$vc4f8/va=8,7 2006.196.08:04:40.35#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.196.08:04:40.35#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.196.08:04:40.35#ibcon#ireg 11 cls_cnt 2 2006.196.08:04:40.35#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.196.08:04:40.40#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.196.08:04:40.40#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.196.08:04:40.40#ibcon#enter wrdev, iclass 15, count 2 2006.196.08:04:40.40#ibcon#first serial, iclass 15, count 2 2006.196.08:04:40.40#ibcon#enter sib2, iclass 15, count 2 2006.196.08:04:40.40#ibcon#flushed, iclass 15, count 2 2006.196.08:04:40.40#ibcon#about to write, iclass 15, count 2 2006.196.08:04:40.40#ibcon#wrote, iclass 15, count 2 2006.196.08:04:40.40#ibcon#about to read 3, iclass 15, count 2 2006.196.08:04:40.42#ibcon#read 3, iclass 15, count 2 2006.196.08:04:40.42#ibcon#about to read 4, iclass 15, count 2 2006.196.08:04:40.42#ibcon#read 4, iclass 15, count 2 2006.196.08:04:40.42#ibcon#about to read 5, iclass 15, count 2 2006.196.08:04:40.42#ibcon#read 5, iclass 15, count 2 2006.196.08:04:40.42#ibcon#about to read 6, iclass 15, count 2 2006.196.08:04:40.42#ibcon#read 6, iclass 15, count 2 2006.196.08:04:40.42#ibcon#end of sib2, iclass 15, count 2 2006.196.08:04:40.42#ibcon#*mode == 0, iclass 15, count 2 2006.196.08:04:40.42#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.196.08:04:40.42#ibcon#[25=AT08-07\r\n] 2006.196.08:04:40.42#ibcon#*before write, iclass 15, count 2 2006.196.08:04:40.42#ibcon#enter sib2, iclass 15, count 2 2006.196.08:04:40.42#ibcon#flushed, iclass 15, count 2 2006.196.08:04:40.42#ibcon#about to write, iclass 15, count 2 2006.196.08:04:40.42#ibcon#wrote, iclass 15, count 2 2006.196.08:04:40.42#ibcon#about to read 3, iclass 15, count 2 2006.196.08:04:40.45#ibcon#read 3, iclass 15, count 2 2006.196.08:04:40.45#ibcon#about to read 4, iclass 15, count 2 2006.196.08:04:40.45#ibcon#read 4, iclass 15, count 2 2006.196.08:04:40.45#ibcon#about to read 5, iclass 15, count 2 2006.196.08:04:40.45#ibcon#read 5, iclass 15, count 2 2006.196.08:04:40.45#ibcon#about to read 6, iclass 15, count 2 2006.196.08:04:40.45#ibcon#read 6, iclass 15, count 2 2006.196.08:04:40.45#ibcon#end of sib2, iclass 15, count 2 2006.196.08:04:40.45#ibcon#*after write, iclass 15, count 2 2006.196.08:04:40.45#ibcon#*before return 0, iclass 15, count 2 2006.196.08:04:40.45#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.196.08:04:40.45#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.196.08:04:40.45#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.196.08:04:40.45#ibcon#ireg 7 cls_cnt 0 2006.196.08:04:40.45#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.196.08:04:40.57#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.196.08:04:40.57#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.196.08:04:40.57#ibcon#enter wrdev, iclass 15, count 0 2006.196.08:04:40.57#ibcon#first serial, iclass 15, count 0 2006.196.08:04:40.57#ibcon#enter sib2, iclass 15, count 0 2006.196.08:04:40.57#ibcon#flushed, iclass 15, count 0 2006.196.08:04:40.57#ibcon#about to write, iclass 15, count 0 2006.196.08:04:40.57#ibcon#wrote, iclass 15, count 0 2006.196.08:04:40.57#ibcon#about to read 3, iclass 15, count 0 2006.196.08:04:40.59#ibcon#read 3, iclass 15, count 0 2006.196.08:04:40.59#ibcon#about to read 4, iclass 15, count 0 2006.196.08:04:40.59#ibcon#read 4, iclass 15, count 0 2006.196.08:04:40.59#ibcon#about to read 5, iclass 15, count 0 2006.196.08:04:40.59#ibcon#read 5, iclass 15, count 0 2006.196.08:04:40.59#ibcon#about to read 6, iclass 15, count 0 2006.196.08:04:40.59#ibcon#read 6, iclass 15, count 0 2006.196.08:04:40.59#ibcon#end of sib2, iclass 15, count 0 2006.196.08:04:40.59#ibcon#*mode == 0, iclass 15, count 0 2006.196.08:04:40.59#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.196.08:04:40.59#ibcon#[25=USB\r\n] 2006.196.08:04:40.59#ibcon#*before write, iclass 15, count 0 2006.196.08:04:40.59#ibcon#enter sib2, iclass 15, count 0 2006.196.08:04:40.59#ibcon#flushed, iclass 15, count 0 2006.196.08:04:40.59#ibcon#about to write, iclass 15, count 0 2006.196.08:04:40.59#ibcon#wrote, iclass 15, count 0 2006.196.08:04:40.59#ibcon#about to read 3, iclass 15, count 0 2006.196.08:04:40.62#ibcon#read 3, iclass 15, count 0 2006.196.08:04:40.62#ibcon#about to read 4, iclass 15, count 0 2006.196.08:04:40.62#ibcon#read 4, iclass 15, count 0 2006.196.08:04:40.62#ibcon#about to read 5, iclass 15, count 0 2006.196.08:04:40.62#ibcon#read 5, iclass 15, count 0 2006.196.08:04:40.62#ibcon#about to read 6, iclass 15, count 0 2006.196.08:04:40.62#ibcon#read 6, iclass 15, count 0 2006.196.08:04:40.62#ibcon#end of sib2, iclass 15, count 0 2006.196.08:04:40.62#ibcon#*after write, iclass 15, count 0 2006.196.08:04:40.62#ibcon#*before return 0, iclass 15, count 0 2006.196.08:04:40.62#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.196.08:04:40.62#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.196.08:04:40.62#ibcon#about to clear, iclass 15 cls_cnt 0 2006.196.08:04:40.62#ibcon#cleared, iclass 15 cls_cnt 0 2006.196.08:04:40.62$vc4f8/vblo=1,632.99 2006.196.08:04:40.62#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.196.08:04:40.62#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.196.08:04:40.62#ibcon#ireg 17 cls_cnt 0 2006.196.08:04:40.62#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.196.08:04:40.62#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.196.08:04:40.62#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.196.08:04:40.62#ibcon#enter wrdev, iclass 17, count 0 2006.196.08:04:40.62#ibcon#first serial, iclass 17, count 0 2006.196.08:04:40.62#ibcon#enter sib2, iclass 17, count 0 2006.196.08:04:40.62#ibcon#flushed, iclass 17, count 0 2006.196.08:04:40.62#ibcon#about to write, iclass 17, count 0 2006.196.08:04:40.62#ibcon#wrote, iclass 17, count 0 2006.196.08:04:40.62#ibcon#about to read 3, iclass 17, count 0 2006.196.08:04:40.64#ibcon#read 3, iclass 17, count 0 2006.196.08:04:40.64#ibcon#about to read 4, iclass 17, count 0 2006.196.08:04:40.64#ibcon#read 4, iclass 17, count 0 2006.196.08:04:40.64#ibcon#about to read 5, iclass 17, count 0 2006.196.08:04:40.64#ibcon#read 5, iclass 17, count 0 2006.196.08:04:40.64#ibcon#about to read 6, iclass 17, count 0 2006.196.08:04:40.64#ibcon#read 6, iclass 17, count 0 2006.196.08:04:40.64#ibcon#end of sib2, iclass 17, count 0 2006.196.08:04:40.64#ibcon#*mode == 0, iclass 17, count 0 2006.196.08:04:40.64#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.196.08:04:40.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.196.08:04:40.64#ibcon#*before write, iclass 17, count 0 2006.196.08:04:40.64#ibcon#enter sib2, iclass 17, count 0 2006.196.08:04:40.64#ibcon#flushed, iclass 17, count 0 2006.196.08:04:40.64#ibcon#about to write, iclass 17, count 0 2006.196.08:04:40.64#ibcon#wrote, iclass 17, count 0 2006.196.08:04:40.64#ibcon#about to read 3, iclass 17, count 0 2006.196.08:04:40.68#ibcon#read 3, iclass 17, count 0 2006.196.08:04:40.68#ibcon#about to read 4, iclass 17, count 0 2006.196.08:04:40.68#ibcon#read 4, iclass 17, count 0 2006.196.08:04:40.68#ibcon#about to read 5, iclass 17, count 0 2006.196.08:04:40.68#ibcon#read 5, iclass 17, count 0 2006.196.08:04:40.68#ibcon#about to read 6, iclass 17, count 0 2006.196.08:04:40.68#ibcon#read 6, iclass 17, count 0 2006.196.08:04:40.68#ibcon#end of sib2, iclass 17, count 0 2006.196.08:04:40.68#ibcon#*after write, iclass 17, count 0 2006.196.08:04:40.68#ibcon#*before return 0, iclass 17, count 0 2006.196.08:04:40.68#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.196.08:04:40.68#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.196.08:04:40.68#ibcon#about to clear, iclass 17 cls_cnt 0 2006.196.08:04:40.68#ibcon#cleared, iclass 17 cls_cnt 0 2006.196.08:04:40.68$vc4f8/vb=1,4 2006.196.08:04:40.68#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.196.08:04:40.68#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.196.08:04:40.68#ibcon#ireg 11 cls_cnt 2 2006.196.08:04:40.68#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.196.08:04:40.68#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.196.08:04:40.68#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.196.08:04:40.68#ibcon#enter wrdev, iclass 19, count 2 2006.196.08:04:40.68#ibcon#first serial, iclass 19, count 2 2006.196.08:04:40.68#ibcon#enter sib2, iclass 19, count 2 2006.196.08:04:40.68#ibcon#flushed, iclass 19, count 2 2006.196.08:04:40.68#ibcon#about to write, iclass 19, count 2 2006.196.08:04:40.68#ibcon#wrote, iclass 19, count 2 2006.196.08:04:40.68#ibcon#about to read 3, iclass 19, count 2 2006.196.08:04:40.70#ibcon#read 3, iclass 19, count 2 2006.196.08:04:40.70#ibcon#about to read 4, iclass 19, count 2 2006.196.08:04:40.70#ibcon#read 4, iclass 19, count 2 2006.196.08:04:40.70#ibcon#about to read 5, iclass 19, count 2 2006.196.08:04:40.70#ibcon#read 5, iclass 19, count 2 2006.196.08:04:40.70#ibcon#about to read 6, iclass 19, count 2 2006.196.08:04:40.70#ibcon#read 6, iclass 19, count 2 2006.196.08:04:40.70#ibcon#end of sib2, iclass 19, count 2 2006.196.08:04:40.70#ibcon#*mode == 0, iclass 19, count 2 2006.196.08:04:40.70#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.196.08:04:40.70#ibcon#[27=AT01-04\r\n] 2006.196.08:04:40.70#ibcon#*before write, iclass 19, count 2 2006.196.08:04:40.70#ibcon#enter sib2, iclass 19, count 2 2006.196.08:04:40.70#ibcon#flushed, iclass 19, count 2 2006.196.08:04:40.70#ibcon#about to write, iclass 19, count 2 2006.196.08:04:40.70#ibcon#wrote, iclass 19, count 2 2006.196.08:04:40.70#ibcon#about to read 3, iclass 19, count 2 2006.196.08:04:40.73#ibcon#read 3, iclass 19, count 2 2006.196.08:04:40.73#ibcon#about to read 4, iclass 19, count 2 2006.196.08:04:40.73#ibcon#read 4, iclass 19, count 2 2006.196.08:04:40.73#ibcon#about to read 5, iclass 19, count 2 2006.196.08:04:40.73#ibcon#read 5, iclass 19, count 2 2006.196.08:04:40.73#ibcon#about to read 6, iclass 19, count 2 2006.196.08:04:40.73#ibcon#read 6, iclass 19, count 2 2006.196.08:04:40.73#ibcon#end of sib2, iclass 19, count 2 2006.196.08:04:40.73#ibcon#*after write, iclass 19, count 2 2006.196.08:04:40.73#ibcon#*before return 0, iclass 19, count 2 2006.196.08:04:40.73#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.196.08:04:40.73#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.196.08:04:40.73#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.196.08:04:40.73#ibcon#ireg 7 cls_cnt 0 2006.196.08:04:40.73#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.196.08:04:40.85#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.196.08:04:40.85#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.196.08:04:40.85#ibcon#enter wrdev, iclass 19, count 0 2006.196.08:04:40.85#ibcon#first serial, iclass 19, count 0 2006.196.08:04:40.85#ibcon#enter sib2, iclass 19, count 0 2006.196.08:04:40.85#ibcon#flushed, iclass 19, count 0 2006.196.08:04:40.85#ibcon#about to write, iclass 19, count 0 2006.196.08:04:40.85#ibcon#wrote, iclass 19, count 0 2006.196.08:04:40.85#ibcon#about to read 3, iclass 19, count 0 2006.196.08:04:40.87#ibcon#read 3, iclass 19, count 0 2006.196.08:04:40.87#ibcon#about to read 4, iclass 19, count 0 2006.196.08:04:40.87#ibcon#read 4, iclass 19, count 0 2006.196.08:04:40.87#ibcon#about to read 5, iclass 19, count 0 2006.196.08:04:40.87#ibcon#read 5, iclass 19, count 0 2006.196.08:04:40.87#ibcon#about to read 6, iclass 19, count 0 2006.196.08:04:40.87#ibcon#read 6, iclass 19, count 0 2006.196.08:04:40.87#ibcon#end of sib2, iclass 19, count 0 2006.196.08:04:40.87#ibcon#*mode == 0, iclass 19, count 0 2006.196.08:04:40.87#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.196.08:04:40.87#ibcon#[27=USB\r\n] 2006.196.08:04:40.87#ibcon#*before write, iclass 19, count 0 2006.196.08:04:40.87#ibcon#enter sib2, iclass 19, count 0 2006.196.08:04:40.87#ibcon#flushed, iclass 19, count 0 2006.196.08:04:40.87#ibcon#about to write, iclass 19, count 0 2006.196.08:04:40.87#ibcon#wrote, iclass 19, count 0 2006.196.08:04:40.87#ibcon#about to read 3, iclass 19, count 0 2006.196.08:04:40.90#ibcon#read 3, iclass 19, count 0 2006.196.08:04:40.90#ibcon#about to read 4, iclass 19, count 0 2006.196.08:04:40.90#ibcon#read 4, iclass 19, count 0 2006.196.08:04:40.90#ibcon#about to read 5, iclass 19, count 0 2006.196.08:04:40.90#ibcon#read 5, iclass 19, count 0 2006.196.08:04:40.90#ibcon#about to read 6, iclass 19, count 0 2006.196.08:04:40.90#ibcon#read 6, iclass 19, count 0 2006.196.08:04:40.90#ibcon#end of sib2, iclass 19, count 0 2006.196.08:04:40.90#ibcon#*after write, iclass 19, count 0 2006.196.08:04:40.90#ibcon#*before return 0, iclass 19, count 0 2006.196.08:04:40.90#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.196.08:04:40.90#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.196.08:04:40.90#ibcon#about to clear, iclass 19 cls_cnt 0 2006.196.08:04:40.90#ibcon#cleared, iclass 19 cls_cnt 0 2006.196.08:04:40.90$vc4f8/vblo=2,640.99 2006.196.08:04:40.90#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.196.08:04:40.90#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.196.08:04:40.90#ibcon#ireg 17 cls_cnt 0 2006.196.08:04:40.90#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.196.08:04:40.90#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.196.08:04:40.90#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.196.08:04:40.90#ibcon#enter wrdev, iclass 21, count 0 2006.196.08:04:40.90#ibcon#first serial, iclass 21, count 0 2006.196.08:04:40.90#ibcon#enter sib2, iclass 21, count 0 2006.196.08:04:40.90#ibcon#flushed, iclass 21, count 0 2006.196.08:04:40.90#ibcon#about to write, iclass 21, count 0 2006.196.08:04:40.90#ibcon#wrote, iclass 21, count 0 2006.196.08:04:40.90#ibcon#about to read 3, iclass 21, count 0 2006.196.08:04:40.92#ibcon#read 3, iclass 21, count 0 2006.196.08:04:40.92#ibcon#about to read 4, iclass 21, count 0 2006.196.08:04:40.92#ibcon#read 4, iclass 21, count 0 2006.196.08:04:40.92#ibcon#about to read 5, iclass 21, count 0 2006.196.08:04:40.92#ibcon#read 5, iclass 21, count 0 2006.196.08:04:40.92#ibcon#about to read 6, iclass 21, count 0 2006.196.08:04:40.92#ibcon#read 6, iclass 21, count 0 2006.196.08:04:40.92#ibcon#end of sib2, iclass 21, count 0 2006.196.08:04:40.92#ibcon#*mode == 0, iclass 21, count 0 2006.196.08:04:40.92#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.196.08:04:40.92#ibcon#[28=FRQ=02,640.99\r\n] 2006.196.08:04:40.92#ibcon#*before write, iclass 21, count 0 2006.196.08:04:40.92#ibcon#enter sib2, iclass 21, count 0 2006.196.08:04:40.92#ibcon#flushed, iclass 21, count 0 2006.196.08:04:40.92#ibcon#about to write, iclass 21, count 0 2006.196.08:04:40.92#ibcon#wrote, iclass 21, count 0 2006.196.08:04:40.92#ibcon#about to read 3, iclass 21, count 0 2006.196.08:04:40.97#ibcon#read 3, iclass 21, count 0 2006.196.08:04:40.97#ibcon#about to read 4, iclass 21, count 0 2006.196.08:04:40.97#ibcon#read 4, iclass 21, count 0 2006.196.08:04:40.97#ibcon#about to read 5, iclass 21, count 0 2006.196.08:04:40.97#ibcon#read 5, iclass 21, count 0 2006.196.08:04:40.97#ibcon#about to read 6, iclass 21, count 0 2006.196.08:04:40.97#ibcon#read 6, iclass 21, count 0 2006.196.08:04:40.97#ibcon#end of sib2, iclass 21, count 0 2006.196.08:04:40.97#ibcon#*after write, iclass 21, count 0 2006.196.08:04:40.97#ibcon#*before return 0, iclass 21, count 0 2006.196.08:04:40.97#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.196.08:04:40.97#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.196.08:04:40.97#ibcon#about to clear, iclass 21 cls_cnt 0 2006.196.08:04:40.97#ibcon#cleared, iclass 21 cls_cnt 0 2006.196.08:04:40.97$vc4f8/vb=2,4 2006.196.08:04:40.97#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.196.08:04:40.97#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.196.08:04:40.97#ibcon#ireg 11 cls_cnt 2 2006.196.08:04:40.97#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.196.08:04:41.02#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.196.08:04:41.02#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.196.08:04:41.02#ibcon#enter wrdev, iclass 23, count 2 2006.196.08:04:41.02#ibcon#first serial, iclass 23, count 2 2006.196.08:04:41.02#ibcon#enter sib2, iclass 23, count 2 2006.196.08:04:41.02#ibcon#flushed, iclass 23, count 2 2006.196.08:04:41.02#ibcon#about to write, iclass 23, count 2 2006.196.08:04:41.02#ibcon#wrote, iclass 23, count 2 2006.196.08:04:41.02#ibcon#about to read 3, iclass 23, count 2 2006.196.08:04:41.04#ibcon#read 3, iclass 23, count 2 2006.196.08:04:41.04#ibcon#about to read 4, iclass 23, count 2 2006.196.08:04:41.04#ibcon#read 4, iclass 23, count 2 2006.196.08:04:41.04#ibcon#about to read 5, iclass 23, count 2 2006.196.08:04:41.04#ibcon#read 5, iclass 23, count 2 2006.196.08:04:41.04#ibcon#about to read 6, iclass 23, count 2 2006.196.08:04:41.04#ibcon#read 6, iclass 23, count 2 2006.196.08:04:41.04#ibcon#end of sib2, iclass 23, count 2 2006.196.08:04:41.04#ibcon#*mode == 0, iclass 23, count 2 2006.196.08:04:41.04#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.196.08:04:41.04#ibcon#[27=AT02-04\r\n] 2006.196.08:04:41.04#ibcon#*before write, iclass 23, count 2 2006.196.08:04:41.04#ibcon#enter sib2, iclass 23, count 2 2006.196.08:04:41.04#ibcon#flushed, iclass 23, count 2 2006.196.08:04:41.04#ibcon#about to write, iclass 23, count 2 2006.196.08:04:41.04#ibcon#wrote, iclass 23, count 2 2006.196.08:04:41.04#ibcon#about to read 3, iclass 23, count 2 2006.196.08:04:41.07#ibcon#read 3, iclass 23, count 2 2006.196.08:04:41.07#ibcon#about to read 4, iclass 23, count 2 2006.196.08:04:41.07#ibcon#read 4, iclass 23, count 2 2006.196.08:04:41.07#ibcon#about to read 5, iclass 23, count 2 2006.196.08:04:41.07#ibcon#read 5, iclass 23, count 2 2006.196.08:04:41.07#ibcon#about to read 6, iclass 23, count 2 2006.196.08:04:41.07#ibcon#read 6, iclass 23, count 2 2006.196.08:04:41.07#ibcon#end of sib2, iclass 23, count 2 2006.196.08:04:41.07#ibcon#*after write, iclass 23, count 2 2006.196.08:04:41.07#ibcon#*before return 0, iclass 23, count 2 2006.196.08:04:41.07#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.196.08:04:41.07#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.196.08:04:41.07#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.196.08:04:41.07#ibcon#ireg 7 cls_cnt 0 2006.196.08:04:41.07#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.196.08:04:41.19#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.196.08:04:41.19#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.196.08:04:41.19#ibcon#enter wrdev, iclass 23, count 0 2006.196.08:04:41.19#ibcon#first serial, iclass 23, count 0 2006.196.08:04:41.19#ibcon#enter sib2, iclass 23, count 0 2006.196.08:04:41.19#ibcon#flushed, iclass 23, count 0 2006.196.08:04:41.19#ibcon#about to write, iclass 23, count 0 2006.196.08:04:41.19#ibcon#wrote, iclass 23, count 0 2006.196.08:04:41.19#ibcon#about to read 3, iclass 23, count 0 2006.196.08:04:41.21#ibcon#read 3, iclass 23, count 0 2006.196.08:04:41.21#ibcon#about to read 4, iclass 23, count 0 2006.196.08:04:41.21#ibcon#read 4, iclass 23, count 0 2006.196.08:04:41.21#ibcon#about to read 5, iclass 23, count 0 2006.196.08:04:41.21#ibcon#read 5, iclass 23, count 0 2006.196.08:04:41.21#ibcon#about to read 6, iclass 23, count 0 2006.196.08:04:41.21#ibcon#read 6, iclass 23, count 0 2006.196.08:04:41.21#ibcon#end of sib2, iclass 23, count 0 2006.196.08:04:41.21#ibcon#*mode == 0, iclass 23, count 0 2006.196.08:04:41.21#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.196.08:04:41.21#ibcon#[27=USB\r\n] 2006.196.08:04:41.21#ibcon#*before write, iclass 23, count 0 2006.196.08:04:41.21#ibcon#enter sib2, iclass 23, count 0 2006.196.08:04:41.21#ibcon#flushed, iclass 23, count 0 2006.196.08:04:41.21#ibcon#about to write, iclass 23, count 0 2006.196.08:04:41.21#ibcon#wrote, iclass 23, count 0 2006.196.08:04:41.21#ibcon#about to read 3, iclass 23, count 0 2006.196.08:04:41.24#ibcon#read 3, iclass 23, count 0 2006.196.08:04:41.24#ibcon#about to read 4, iclass 23, count 0 2006.196.08:04:41.24#ibcon#read 4, iclass 23, count 0 2006.196.08:04:41.24#ibcon#about to read 5, iclass 23, count 0 2006.196.08:04:41.24#ibcon#read 5, iclass 23, count 0 2006.196.08:04:41.24#ibcon#about to read 6, iclass 23, count 0 2006.196.08:04:41.24#ibcon#read 6, iclass 23, count 0 2006.196.08:04:41.24#ibcon#end of sib2, iclass 23, count 0 2006.196.08:04:41.24#ibcon#*after write, iclass 23, count 0 2006.196.08:04:41.24#ibcon#*before return 0, iclass 23, count 0 2006.196.08:04:41.24#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.196.08:04:41.24#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.196.08:04:41.24#ibcon#about to clear, iclass 23 cls_cnt 0 2006.196.08:04:41.24#ibcon#cleared, iclass 23 cls_cnt 0 2006.196.08:04:41.24$vc4f8/vblo=3,656.99 2006.196.08:04:41.24#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.196.08:04:41.24#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.196.08:04:41.24#ibcon#ireg 17 cls_cnt 0 2006.196.08:04:41.24#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.196.08:04:41.24#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.196.08:04:41.24#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.196.08:04:41.24#ibcon#enter wrdev, iclass 25, count 0 2006.196.08:04:41.24#ibcon#first serial, iclass 25, count 0 2006.196.08:04:41.24#ibcon#enter sib2, iclass 25, count 0 2006.196.08:04:41.24#ibcon#flushed, iclass 25, count 0 2006.196.08:04:41.24#ibcon#about to write, iclass 25, count 0 2006.196.08:04:41.24#ibcon#wrote, iclass 25, count 0 2006.196.08:04:41.24#ibcon#about to read 3, iclass 25, count 0 2006.196.08:04:41.26#ibcon#read 3, iclass 25, count 0 2006.196.08:04:41.26#ibcon#about to read 4, iclass 25, count 0 2006.196.08:04:41.26#ibcon#read 4, iclass 25, count 0 2006.196.08:04:41.26#ibcon#about to read 5, iclass 25, count 0 2006.196.08:04:41.26#ibcon#read 5, iclass 25, count 0 2006.196.08:04:41.26#ibcon#about to read 6, iclass 25, count 0 2006.196.08:04:41.26#ibcon#read 6, iclass 25, count 0 2006.196.08:04:41.26#ibcon#end of sib2, iclass 25, count 0 2006.196.08:04:41.26#ibcon#*mode == 0, iclass 25, count 0 2006.196.08:04:41.26#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.196.08:04:41.26#ibcon#[28=FRQ=03,656.99\r\n] 2006.196.08:04:41.26#ibcon#*before write, iclass 25, count 0 2006.196.08:04:41.26#ibcon#enter sib2, iclass 25, count 0 2006.196.08:04:41.26#ibcon#flushed, iclass 25, count 0 2006.196.08:04:41.26#ibcon#about to write, iclass 25, count 0 2006.196.08:04:41.26#ibcon#wrote, iclass 25, count 0 2006.196.08:04:41.26#ibcon#about to read 3, iclass 25, count 0 2006.196.08:04:41.30#ibcon#read 3, iclass 25, count 0 2006.196.08:04:41.30#ibcon#about to read 4, iclass 25, count 0 2006.196.08:04:41.30#ibcon#read 4, iclass 25, count 0 2006.196.08:04:41.30#ibcon#about to read 5, iclass 25, count 0 2006.196.08:04:41.30#ibcon#read 5, iclass 25, count 0 2006.196.08:04:41.30#ibcon#about to read 6, iclass 25, count 0 2006.196.08:04:41.30#ibcon#read 6, iclass 25, count 0 2006.196.08:04:41.30#ibcon#end of sib2, iclass 25, count 0 2006.196.08:04:41.30#ibcon#*after write, iclass 25, count 0 2006.196.08:04:41.30#ibcon#*before return 0, iclass 25, count 0 2006.196.08:04:41.30#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.196.08:04:41.30#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.196.08:04:41.30#ibcon#about to clear, iclass 25 cls_cnt 0 2006.196.08:04:41.30#ibcon#cleared, iclass 25 cls_cnt 0 2006.196.08:04:41.30$vc4f8/vb=3,4 2006.196.08:04:41.30#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.196.08:04:41.30#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.196.08:04:41.30#ibcon#ireg 11 cls_cnt 2 2006.196.08:04:41.30#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.196.08:04:41.36#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.196.08:04:41.36#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.196.08:04:41.36#ibcon#enter wrdev, iclass 27, count 2 2006.196.08:04:41.36#ibcon#first serial, iclass 27, count 2 2006.196.08:04:41.36#ibcon#enter sib2, iclass 27, count 2 2006.196.08:04:41.36#ibcon#flushed, iclass 27, count 2 2006.196.08:04:41.36#ibcon#about to write, iclass 27, count 2 2006.196.08:04:41.36#ibcon#wrote, iclass 27, count 2 2006.196.08:04:41.36#ibcon#about to read 3, iclass 27, count 2 2006.196.08:04:41.38#ibcon#read 3, iclass 27, count 2 2006.196.08:04:41.38#ibcon#about to read 4, iclass 27, count 2 2006.196.08:04:41.38#ibcon#read 4, iclass 27, count 2 2006.196.08:04:41.38#ibcon#about to read 5, iclass 27, count 2 2006.196.08:04:41.38#ibcon#read 5, iclass 27, count 2 2006.196.08:04:41.38#ibcon#about to read 6, iclass 27, count 2 2006.196.08:04:41.38#ibcon#read 6, iclass 27, count 2 2006.196.08:04:41.38#ibcon#end of sib2, iclass 27, count 2 2006.196.08:04:41.38#ibcon#*mode == 0, iclass 27, count 2 2006.196.08:04:41.38#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.196.08:04:41.38#ibcon#[27=AT03-04\r\n] 2006.196.08:04:41.38#ibcon#*before write, iclass 27, count 2 2006.196.08:04:41.38#ibcon#enter sib2, iclass 27, count 2 2006.196.08:04:41.38#ibcon#flushed, iclass 27, count 2 2006.196.08:04:41.38#ibcon#about to write, iclass 27, count 2 2006.196.08:04:41.38#ibcon#wrote, iclass 27, count 2 2006.196.08:04:41.38#ibcon#about to read 3, iclass 27, count 2 2006.196.08:04:41.41#ibcon#read 3, iclass 27, count 2 2006.196.08:04:41.41#ibcon#about to read 4, iclass 27, count 2 2006.196.08:04:41.41#ibcon#read 4, iclass 27, count 2 2006.196.08:04:41.41#ibcon#about to read 5, iclass 27, count 2 2006.196.08:04:41.41#ibcon#read 5, iclass 27, count 2 2006.196.08:04:41.41#ibcon#about to read 6, iclass 27, count 2 2006.196.08:04:41.41#ibcon#read 6, iclass 27, count 2 2006.196.08:04:41.41#ibcon#end of sib2, iclass 27, count 2 2006.196.08:04:41.41#ibcon#*after write, iclass 27, count 2 2006.196.08:04:41.41#ibcon#*before return 0, iclass 27, count 2 2006.196.08:04:41.41#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.196.08:04:41.41#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.196.08:04:41.41#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.196.08:04:41.41#ibcon#ireg 7 cls_cnt 0 2006.196.08:04:41.41#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.196.08:04:41.53#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.196.08:04:41.53#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.196.08:04:41.53#ibcon#enter wrdev, iclass 27, count 0 2006.196.08:04:41.53#ibcon#first serial, iclass 27, count 0 2006.196.08:04:41.53#ibcon#enter sib2, iclass 27, count 0 2006.196.08:04:41.53#ibcon#flushed, iclass 27, count 0 2006.196.08:04:41.53#ibcon#about to write, iclass 27, count 0 2006.196.08:04:41.53#ibcon#wrote, iclass 27, count 0 2006.196.08:04:41.53#ibcon#about to read 3, iclass 27, count 0 2006.196.08:04:41.55#ibcon#read 3, iclass 27, count 0 2006.196.08:04:41.55#ibcon#about to read 4, iclass 27, count 0 2006.196.08:04:41.55#ibcon#read 4, iclass 27, count 0 2006.196.08:04:41.55#ibcon#about to read 5, iclass 27, count 0 2006.196.08:04:41.55#ibcon#read 5, iclass 27, count 0 2006.196.08:04:41.55#ibcon#about to read 6, iclass 27, count 0 2006.196.08:04:41.55#ibcon#read 6, iclass 27, count 0 2006.196.08:04:41.55#ibcon#end of sib2, iclass 27, count 0 2006.196.08:04:41.55#ibcon#*mode == 0, iclass 27, count 0 2006.196.08:04:41.55#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.196.08:04:41.55#ibcon#[27=USB\r\n] 2006.196.08:04:41.55#ibcon#*before write, iclass 27, count 0 2006.196.08:04:41.55#ibcon#enter sib2, iclass 27, count 0 2006.196.08:04:41.55#ibcon#flushed, iclass 27, count 0 2006.196.08:04:41.55#ibcon#about to write, iclass 27, count 0 2006.196.08:04:41.55#ibcon#wrote, iclass 27, count 0 2006.196.08:04:41.55#ibcon#about to read 3, iclass 27, count 0 2006.196.08:04:41.58#ibcon#read 3, iclass 27, count 0 2006.196.08:04:41.58#ibcon#about to read 4, iclass 27, count 0 2006.196.08:04:41.58#ibcon#read 4, iclass 27, count 0 2006.196.08:04:41.58#ibcon#about to read 5, iclass 27, count 0 2006.196.08:04:41.58#ibcon#read 5, iclass 27, count 0 2006.196.08:04:41.58#ibcon#about to read 6, iclass 27, count 0 2006.196.08:04:41.58#ibcon#read 6, iclass 27, count 0 2006.196.08:04:41.58#ibcon#end of sib2, iclass 27, count 0 2006.196.08:04:41.58#ibcon#*after write, iclass 27, count 0 2006.196.08:04:41.58#ibcon#*before return 0, iclass 27, count 0 2006.196.08:04:41.58#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.196.08:04:41.58#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.196.08:04:41.58#ibcon#about to clear, iclass 27 cls_cnt 0 2006.196.08:04:41.58#ibcon#cleared, iclass 27 cls_cnt 0 2006.196.08:04:41.58$vc4f8/vblo=4,712.99 2006.196.08:04:41.58#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.196.08:04:41.58#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.196.08:04:41.58#ibcon#ireg 17 cls_cnt 0 2006.196.08:04:41.58#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.196.08:04:41.58#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.196.08:04:41.58#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.196.08:04:41.58#ibcon#enter wrdev, iclass 29, count 0 2006.196.08:04:41.58#ibcon#first serial, iclass 29, count 0 2006.196.08:04:41.58#ibcon#enter sib2, iclass 29, count 0 2006.196.08:04:41.58#ibcon#flushed, iclass 29, count 0 2006.196.08:04:41.58#ibcon#about to write, iclass 29, count 0 2006.196.08:04:41.58#ibcon#wrote, iclass 29, count 0 2006.196.08:04:41.58#ibcon#about to read 3, iclass 29, count 0 2006.196.08:04:41.60#ibcon#read 3, iclass 29, count 0 2006.196.08:04:41.60#ibcon#about to read 4, iclass 29, count 0 2006.196.08:04:41.60#ibcon#read 4, iclass 29, count 0 2006.196.08:04:41.60#ibcon#about to read 5, iclass 29, count 0 2006.196.08:04:41.60#ibcon#read 5, iclass 29, count 0 2006.196.08:04:41.60#ibcon#about to read 6, iclass 29, count 0 2006.196.08:04:41.60#ibcon#read 6, iclass 29, count 0 2006.196.08:04:41.60#ibcon#end of sib2, iclass 29, count 0 2006.196.08:04:41.60#ibcon#*mode == 0, iclass 29, count 0 2006.196.08:04:41.60#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.196.08:04:41.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.196.08:04:41.60#ibcon#*before write, iclass 29, count 0 2006.196.08:04:41.60#ibcon#enter sib2, iclass 29, count 0 2006.196.08:04:41.60#ibcon#flushed, iclass 29, count 0 2006.196.08:04:41.60#ibcon#about to write, iclass 29, count 0 2006.196.08:04:41.60#ibcon#wrote, iclass 29, count 0 2006.196.08:04:41.60#ibcon#about to read 3, iclass 29, count 0 2006.196.08:04:41.64#ibcon#read 3, iclass 29, count 0 2006.196.08:04:41.64#ibcon#about to read 4, iclass 29, count 0 2006.196.08:04:41.64#ibcon#read 4, iclass 29, count 0 2006.196.08:04:41.64#ibcon#about to read 5, iclass 29, count 0 2006.196.08:04:41.64#ibcon#read 5, iclass 29, count 0 2006.196.08:04:41.64#ibcon#about to read 6, iclass 29, count 0 2006.196.08:04:41.64#ibcon#read 6, iclass 29, count 0 2006.196.08:04:41.64#ibcon#end of sib2, iclass 29, count 0 2006.196.08:04:41.64#ibcon#*after write, iclass 29, count 0 2006.196.08:04:41.64#ibcon#*before return 0, iclass 29, count 0 2006.196.08:04:41.64#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.196.08:04:41.64#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.196.08:04:41.64#ibcon#about to clear, iclass 29 cls_cnt 0 2006.196.08:04:41.64#ibcon#cleared, iclass 29 cls_cnt 0 2006.196.08:04:41.64$vc4f8/vb=4,4 2006.196.08:04:41.64#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.196.08:04:41.64#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.196.08:04:41.64#ibcon#ireg 11 cls_cnt 2 2006.196.08:04:41.64#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.196.08:04:41.70#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.196.08:04:41.70#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.196.08:04:41.70#ibcon#enter wrdev, iclass 31, count 2 2006.196.08:04:41.70#ibcon#first serial, iclass 31, count 2 2006.196.08:04:41.70#ibcon#enter sib2, iclass 31, count 2 2006.196.08:04:41.70#ibcon#flushed, iclass 31, count 2 2006.196.08:04:41.70#ibcon#about to write, iclass 31, count 2 2006.196.08:04:41.70#ibcon#wrote, iclass 31, count 2 2006.196.08:04:41.70#ibcon#about to read 3, iclass 31, count 2 2006.196.08:04:41.72#ibcon#read 3, iclass 31, count 2 2006.196.08:04:41.72#ibcon#about to read 4, iclass 31, count 2 2006.196.08:04:41.72#ibcon#read 4, iclass 31, count 2 2006.196.08:04:41.72#ibcon#about to read 5, iclass 31, count 2 2006.196.08:04:41.72#ibcon#read 5, iclass 31, count 2 2006.196.08:04:41.72#ibcon#about to read 6, iclass 31, count 2 2006.196.08:04:41.72#ibcon#read 6, iclass 31, count 2 2006.196.08:04:41.72#ibcon#end of sib2, iclass 31, count 2 2006.196.08:04:41.72#ibcon#*mode == 0, iclass 31, count 2 2006.196.08:04:41.72#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.196.08:04:41.72#ibcon#[27=AT04-04\r\n] 2006.196.08:04:41.72#ibcon#*before write, iclass 31, count 2 2006.196.08:04:41.72#ibcon#enter sib2, iclass 31, count 2 2006.196.08:04:41.72#ibcon#flushed, iclass 31, count 2 2006.196.08:04:41.72#ibcon#about to write, iclass 31, count 2 2006.196.08:04:41.72#ibcon#wrote, iclass 31, count 2 2006.196.08:04:41.72#ibcon#about to read 3, iclass 31, count 2 2006.196.08:04:41.75#ibcon#read 3, iclass 31, count 2 2006.196.08:04:41.75#ibcon#about to read 4, iclass 31, count 2 2006.196.08:04:41.75#ibcon#read 4, iclass 31, count 2 2006.196.08:04:41.75#ibcon#about to read 5, iclass 31, count 2 2006.196.08:04:41.75#ibcon#read 5, iclass 31, count 2 2006.196.08:04:41.75#ibcon#about to read 6, iclass 31, count 2 2006.196.08:04:41.75#ibcon#read 6, iclass 31, count 2 2006.196.08:04:41.75#ibcon#end of sib2, iclass 31, count 2 2006.196.08:04:41.75#ibcon#*after write, iclass 31, count 2 2006.196.08:04:41.75#ibcon#*before return 0, iclass 31, count 2 2006.196.08:04:41.75#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.196.08:04:41.75#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.196.08:04:41.75#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.196.08:04:41.75#ibcon#ireg 7 cls_cnt 0 2006.196.08:04:41.75#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.196.08:04:41.87#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.196.08:04:41.87#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.196.08:04:41.87#ibcon#enter wrdev, iclass 31, count 0 2006.196.08:04:41.87#ibcon#first serial, iclass 31, count 0 2006.196.08:04:41.87#ibcon#enter sib2, iclass 31, count 0 2006.196.08:04:41.87#ibcon#flushed, iclass 31, count 0 2006.196.08:04:41.87#ibcon#about to write, iclass 31, count 0 2006.196.08:04:41.87#ibcon#wrote, iclass 31, count 0 2006.196.08:04:41.87#ibcon#about to read 3, iclass 31, count 0 2006.196.08:04:41.89#ibcon#read 3, iclass 31, count 0 2006.196.08:04:41.89#ibcon#about to read 4, iclass 31, count 0 2006.196.08:04:41.89#ibcon#read 4, iclass 31, count 0 2006.196.08:04:41.89#ibcon#about to read 5, iclass 31, count 0 2006.196.08:04:41.89#ibcon#read 5, iclass 31, count 0 2006.196.08:04:41.89#ibcon#about to read 6, iclass 31, count 0 2006.196.08:04:41.89#ibcon#read 6, iclass 31, count 0 2006.196.08:04:41.89#ibcon#end of sib2, iclass 31, count 0 2006.196.08:04:41.89#ibcon#*mode == 0, iclass 31, count 0 2006.196.08:04:41.89#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.196.08:04:41.89#ibcon#[27=USB\r\n] 2006.196.08:04:41.89#ibcon#*before write, iclass 31, count 0 2006.196.08:04:41.89#ibcon#enter sib2, iclass 31, count 0 2006.196.08:04:41.89#ibcon#flushed, iclass 31, count 0 2006.196.08:04:41.89#ibcon#about to write, iclass 31, count 0 2006.196.08:04:41.89#ibcon#wrote, iclass 31, count 0 2006.196.08:04:41.89#ibcon#about to read 3, iclass 31, count 0 2006.196.08:04:41.92#ibcon#read 3, iclass 31, count 0 2006.196.08:04:41.92#ibcon#about to read 4, iclass 31, count 0 2006.196.08:04:41.92#ibcon#read 4, iclass 31, count 0 2006.196.08:04:41.92#ibcon#about to read 5, iclass 31, count 0 2006.196.08:04:41.92#ibcon#read 5, iclass 31, count 0 2006.196.08:04:41.92#ibcon#about to read 6, iclass 31, count 0 2006.196.08:04:41.92#ibcon#read 6, iclass 31, count 0 2006.196.08:04:41.92#ibcon#end of sib2, iclass 31, count 0 2006.196.08:04:41.92#ibcon#*after write, iclass 31, count 0 2006.196.08:04:41.92#ibcon#*before return 0, iclass 31, count 0 2006.196.08:04:41.92#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.196.08:04:41.92#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.196.08:04:41.92#ibcon#about to clear, iclass 31 cls_cnt 0 2006.196.08:04:41.92#ibcon#cleared, iclass 31 cls_cnt 0 2006.196.08:04:41.92$vc4f8/vblo=5,744.99 2006.196.08:04:41.92#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.196.08:04:41.92#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.196.08:04:41.92#ibcon#ireg 17 cls_cnt 0 2006.196.08:04:41.92#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:04:41.92#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:04:41.92#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:04:41.92#ibcon#enter wrdev, iclass 33, count 0 2006.196.08:04:41.92#ibcon#first serial, iclass 33, count 0 2006.196.08:04:41.92#ibcon#enter sib2, iclass 33, count 0 2006.196.08:04:41.92#ibcon#flushed, iclass 33, count 0 2006.196.08:04:41.92#ibcon#about to write, iclass 33, count 0 2006.196.08:04:41.92#ibcon#wrote, iclass 33, count 0 2006.196.08:04:41.92#ibcon#about to read 3, iclass 33, count 0 2006.196.08:04:41.94#ibcon#read 3, iclass 33, count 0 2006.196.08:04:41.94#ibcon#about to read 4, iclass 33, count 0 2006.196.08:04:41.94#ibcon#read 4, iclass 33, count 0 2006.196.08:04:41.94#ibcon#about to read 5, iclass 33, count 0 2006.196.08:04:41.94#ibcon#read 5, iclass 33, count 0 2006.196.08:04:41.94#ibcon#about to read 6, iclass 33, count 0 2006.196.08:04:41.94#ibcon#read 6, iclass 33, count 0 2006.196.08:04:41.94#ibcon#end of sib2, iclass 33, count 0 2006.196.08:04:41.94#ibcon#*mode == 0, iclass 33, count 0 2006.196.08:04:41.94#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.196.08:04:41.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.196.08:04:41.94#ibcon#*before write, iclass 33, count 0 2006.196.08:04:41.94#ibcon#enter sib2, iclass 33, count 0 2006.196.08:04:41.94#ibcon#flushed, iclass 33, count 0 2006.196.08:04:41.94#ibcon#about to write, iclass 33, count 0 2006.196.08:04:41.94#ibcon#wrote, iclass 33, count 0 2006.196.08:04:41.94#ibcon#about to read 3, iclass 33, count 0 2006.196.08:04:41.99#ibcon#read 3, iclass 33, count 0 2006.196.08:04:41.99#ibcon#about to read 4, iclass 33, count 0 2006.196.08:04:41.99#ibcon#read 4, iclass 33, count 0 2006.196.08:04:41.99#ibcon#about to read 5, iclass 33, count 0 2006.196.08:04:41.99#ibcon#read 5, iclass 33, count 0 2006.196.08:04:41.99#ibcon#about to read 6, iclass 33, count 0 2006.196.08:04:41.99#ibcon#read 6, iclass 33, count 0 2006.196.08:04:41.99#ibcon#end of sib2, iclass 33, count 0 2006.196.08:04:41.99#ibcon#*after write, iclass 33, count 0 2006.196.08:04:41.99#ibcon#*before return 0, iclass 33, count 0 2006.196.08:04:41.99#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:04:41.99#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:04:41.99#ibcon#about to clear, iclass 33 cls_cnt 0 2006.196.08:04:41.99#ibcon#cleared, iclass 33 cls_cnt 0 2006.196.08:04:41.99$vc4f8/vb=5,4 2006.196.08:04:41.99#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.196.08:04:41.99#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.196.08:04:41.99#ibcon#ireg 11 cls_cnt 2 2006.196.08:04:41.99#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.196.08:04:42.04#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.196.08:04:42.04#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.196.08:04:42.04#ibcon#enter wrdev, iclass 35, count 2 2006.196.08:04:42.04#ibcon#first serial, iclass 35, count 2 2006.196.08:04:42.04#ibcon#enter sib2, iclass 35, count 2 2006.196.08:04:42.04#ibcon#flushed, iclass 35, count 2 2006.196.08:04:42.04#ibcon#about to write, iclass 35, count 2 2006.196.08:04:42.04#ibcon#wrote, iclass 35, count 2 2006.196.08:04:42.04#ibcon#about to read 3, iclass 35, count 2 2006.196.08:04:42.06#ibcon#read 3, iclass 35, count 2 2006.196.08:04:42.06#ibcon#about to read 4, iclass 35, count 2 2006.196.08:04:42.06#ibcon#read 4, iclass 35, count 2 2006.196.08:04:42.06#ibcon#about to read 5, iclass 35, count 2 2006.196.08:04:42.06#ibcon#read 5, iclass 35, count 2 2006.196.08:04:42.06#ibcon#about to read 6, iclass 35, count 2 2006.196.08:04:42.06#ibcon#read 6, iclass 35, count 2 2006.196.08:04:42.06#ibcon#end of sib2, iclass 35, count 2 2006.196.08:04:42.06#ibcon#*mode == 0, iclass 35, count 2 2006.196.08:04:42.06#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.196.08:04:42.06#ibcon#[27=AT05-04\r\n] 2006.196.08:04:42.06#ibcon#*before write, iclass 35, count 2 2006.196.08:04:42.06#ibcon#enter sib2, iclass 35, count 2 2006.196.08:04:42.06#ibcon#flushed, iclass 35, count 2 2006.196.08:04:42.06#ibcon#about to write, iclass 35, count 2 2006.196.08:04:42.06#ibcon#wrote, iclass 35, count 2 2006.196.08:04:42.06#ibcon#about to read 3, iclass 35, count 2 2006.196.08:04:42.09#ibcon#read 3, iclass 35, count 2 2006.196.08:04:42.09#ibcon#about to read 4, iclass 35, count 2 2006.196.08:04:42.09#ibcon#read 4, iclass 35, count 2 2006.196.08:04:42.09#ibcon#about to read 5, iclass 35, count 2 2006.196.08:04:42.09#ibcon#read 5, iclass 35, count 2 2006.196.08:04:42.09#ibcon#about to read 6, iclass 35, count 2 2006.196.08:04:42.09#ibcon#read 6, iclass 35, count 2 2006.196.08:04:42.09#ibcon#end of sib2, iclass 35, count 2 2006.196.08:04:42.09#ibcon#*after write, iclass 35, count 2 2006.196.08:04:42.09#ibcon#*before return 0, iclass 35, count 2 2006.196.08:04:42.09#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.196.08:04:42.09#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.196.08:04:42.09#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.196.08:04:42.09#ibcon#ireg 7 cls_cnt 0 2006.196.08:04:42.09#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.196.08:04:42.21#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.196.08:04:42.21#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.196.08:04:42.21#ibcon#enter wrdev, iclass 35, count 0 2006.196.08:04:42.21#ibcon#first serial, iclass 35, count 0 2006.196.08:04:42.21#ibcon#enter sib2, iclass 35, count 0 2006.196.08:04:42.21#ibcon#flushed, iclass 35, count 0 2006.196.08:04:42.21#ibcon#about to write, iclass 35, count 0 2006.196.08:04:42.21#ibcon#wrote, iclass 35, count 0 2006.196.08:04:42.21#ibcon#about to read 3, iclass 35, count 0 2006.196.08:04:42.23#ibcon#read 3, iclass 35, count 0 2006.196.08:04:42.23#ibcon#about to read 4, iclass 35, count 0 2006.196.08:04:42.23#ibcon#read 4, iclass 35, count 0 2006.196.08:04:42.23#ibcon#about to read 5, iclass 35, count 0 2006.196.08:04:42.23#ibcon#read 5, iclass 35, count 0 2006.196.08:04:42.23#ibcon#about to read 6, iclass 35, count 0 2006.196.08:04:42.23#ibcon#read 6, iclass 35, count 0 2006.196.08:04:42.23#ibcon#end of sib2, iclass 35, count 0 2006.196.08:04:42.23#ibcon#*mode == 0, iclass 35, count 0 2006.196.08:04:42.23#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.196.08:04:42.23#ibcon#[27=USB\r\n] 2006.196.08:04:42.23#ibcon#*before write, iclass 35, count 0 2006.196.08:04:42.23#ibcon#enter sib2, iclass 35, count 0 2006.196.08:04:42.23#ibcon#flushed, iclass 35, count 0 2006.196.08:04:42.23#ibcon#about to write, iclass 35, count 0 2006.196.08:04:42.23#ibcon#wrote, iclass 35, count 0 2006.196.08:04:42.23#ibcon#about to read 3, iclass 35, count 0 2006.196.08:04:42.26#ibcon#read 3, iclass 35, count 0 2006.196.08:04:42.26#ibcon#about to read 4, iclass 35, count 0 2006.196.08:04:42.26#ibcon#read 4, iclass 35, count 0 2006.196.08:04:42.26#ibcon#about to read 5, iclass 35, count 0 2006.196.08:04:42.26#ibcon#read 5, iclass 35, count 0 2006.196.08:04:42.26#ibcon#about to read 6, iclass 35, count 0 2006.196.08:04:42.26#ibcon#read 6, iclass 35, count 0 2006.196.08:04:42.26#ibcon#end of sib2, iclass 35, count 0 2006.196.08:04:42.26#ibcon#*after write, iclass 35, count 0 2006.196.08:04:42.26#ibcon#*before return 0, iclass 35, count 0 2006.196.08:04:42.26#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.196.08:04:42.26#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.196.08:04:42.26#ibcon#about to clear, iclass 35 cls_cnt 0 2006.196.08:04:42.26#ibcon#cleared, iclass 35 cls_cnt 0 2006.196.08:04:42.26$vc4f8/vblo=6,752.99 2006.196.08:04:42.26#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.196.08:04:42.26#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.196.08:04:42.26#ibcon#ireg 17 cls_cnt 0 2006.196.08:04:42.26#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.196.08:04:42.26#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.196.08:04:42.26#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.196.08:04:42.26#ibcon#enter wrdev, iclass 37, count 0 2006.196.08:04:42.26#ibcon#first serial, iclass 37, count 0 2006.196.08:04:42.26#ibcon#enter sib2, iclass 37, count 0 2006.196.08:04:42.26#ibcon#flushed, iclass 37, count 0 2006.196.08:04:42.26#ibcon#about to write, iclass 37, count 0 2006.196.08:04:42.26#ibcon#wrote, iclass 37, count 0 2006.196.08:04:42.26#ibcon#about to read 3, iclass 37, count 0 2006.196.08:04:42.28#ibcon#read 3, iclass 37, count 0 2006.196.08:04:42.28#ibcon#about to read 4, iclass 37, count 0 2006.196.08:04:42.28#ibcon#read 4, iclass 37, count 0 2006.196.08:04:42.28#ibcon#about to read 5, iclass 37, count 0 2006.196.08:04:42.28#ibcon#read 5, iclass 37, count 0 2006.196.08:04:42.28#ibcon#about to read 6, iclass 37, count 0 2006.196.08:04:42.28#ibcon#read 6, iclass 37, count 0 2006.196.08:04:42.28#ibcon#end of sib2, iclass 37, count 0 2006.196.08:04:42.28#ibcon#*mode == 0, iclass 37, count 0 2006.196.08:04:42.28#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.196.08:04:42.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.196.08:04:42.28#ibcon#*before write, iclass 37, count 0 2006.196.08:04:42.28#ibcon#enter sib2, iclass 37, count 0 2006.196.08:04:42.28#ibcon#flushed, iclass 37, count 0 2006.196.08:04:42.28#ibcon#about to write, iclass 37, count 0 2006.196.08:04:42.28#ibcon#wrote, iclass 37, count 0 2006.196.08:04:42.28#ibcon#about to read 3, iclass 37, count 0 2006.196.08:04:42.32#ibcon#read 3, iclass 37, count 0 2006.196.08:04:42.32#ibcon#about to read 4, iclass 37, count 0 2006.196.08:04:42.32#ibcon#read 4, iclass 37, count 0 2006.196.08:04:42.32#ibcon#about to read 5, iclass 37, count 0 2006.196.08:04:42.32#ibcon#read 5, iclass 37, count 0 2006.196.08:04:42.32#ibcon#about to read 6, iclass 37, count 0 2006.196.08:04:42.32#ibcon#read 6, iclass 37, count 0 2006.196.08:04:42.32#ibcon#end of sib2, iclass 37, count 0 2006.196.08:04:42.32#ibcon#*after write, iclass 37, count 0 2006.196.08:04:42.32#ibcon#*before return 0, iclass 37, count 0 2006.196.08:04:42.32#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.196.08:04:42.32#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.196.08:04:42.32#ibcon#about to clear, iclass 37 cls_cnt 0 2006.196.08:04:42.32#ibcon#cleared, iclass 37 cls_cnt 0 2006.196.08:04:42.32$vc4f8/vb=6,4 2006.196.08:04:42.32#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.196.08:04:42.32#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.196.08:04:42.32#ibcon#ireg 11 cls_cnt 2 2006.196.08:04:42.32#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.196.08:04:42.38#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.196.08:04:42.38#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.196.08:04:42.38#ibcon#enter wrdev, iclass 39, count 2 2006.196.08:04:42.38#ibcon#first serial, iclass 39, count 2 2006.196.08:04:42.38#ibcon#enter sib2, iclass 39, count 2 2006.196.08:04:42.38#ibcon#flushed, iclass 39, count 2 2006.196.08:04:42.38#ibcon#about to write, iclass 39, count 2 2006.196.08:04:42.38#ibcon#wrote, iclass 39, count 2 2006.196.08:04:42.38#ibcon#about to read 3, iclass 39, count 2 2006.196.08:04:42.40#ibcon#read 3, iclass 39, count 2 2006.196.08:04:42.40#ibcon#about to read 4, iclass 39, count 2 2006.196.08:04:42.40#ibcon#read 4, iclass 39, count 2 2006.196.08:04:42.40#ibcon#about to read 5, iclass 39, count 2 2006.196.08:04:42.40#ibcon#read 5, iclass 39, count 2 2006.196.08:04:42.40#ibcon#about to read 6, iclass 39, count 2 2006.196.08:04:42.40#ibcon#read 6, iclass 39, count 2 2006.196.08:04:42.40#ibcon#end of sib2, iclass 39, count 2 2006.196.08:04:42.40#ibcon#*mode == 0, iclass 39, count 2 2006.196.08:04:42.40#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.196.08:04:42.40#ibcon#[27=AT06-04\r\n] 2006.196.08:04:42.40#ibcon#*before write, iclass 39, count 2 2006.196.08:04:42.40#ibcon#enter sib2, iclass 39, count 2 2006.196.08:04:42.40#ibcon#flushed, iclass 39, count 2 2006.196.08:04:42.40#ibcon#about to write, iclass 39, count 2 2006.196.08:04:42.40#ibcon#wrote, iclass 39, count 2 2006.196.08:04:42.40#ibcon#about to read 3, iclass 39, count 2 2006.196.08:04:42.43#ibcon#read 3, iclass 39, count 2 2006.196.08:04:42.43#ibcon#about to read 4, iclass 39, count 2 2006.196.08:04:42.43#ibcon#read 4, iclass 39, count 2 2006.196.08:04:42.43#ibcon#about to read 5, iclass 39, count 2 2006.196.08:04:42.43#ibcon#read 5, iclass 39, count 2 2006.196.08:04:42.43#ibcon#about to read 6, iclass 39, count 2 2006.196.08:04:42.43#ibcon#read 6, iclass 39, count 2 2006.196.08:04:42.43#ibcon#end of sib2, iclass 39, count 2 2006.196.08:04:42.43#ibcon#*after write, iclass 39, count 2 2006.196.08:04:42.43#ibcon#*before return 0, iclass 39, count 2 2006.196.08:04:42.43#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.196.08:04:42.43#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.196.08:04:42.43#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.196.08:04:42.43#ibcon#ireg 7 cls_cnt 0 2006.196.08:04:42.43#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.196.08:04:42.55#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.196.08:04:42.55#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.196.08:04:42.55#ibcon#enter wrdev, iclass 39, count 0 2006.196.08:04:42.55#ibcon#first serial, iclass 39, count 0 2006.196.08:04:42.55#ibcon#enter sib2, iclass 39, count 0 2006.196.08:04:42.55#ibcon#flushed, iclass 39, count 0 2006.196.08:04:42.55#ibcon#about to write, iclass 39, count 0 2006.196.08:04:42.55#ibcon#wrote, iclass 39, count 0 2006.196.08:04:42.55#ibcon#about to read 3, iclass 39, count 0 2006.196.08:04:42.57#ibcon#read 3, iclass 39, count 0 2006.196.08:04:42.57#ibcon#about to read 4, iclass 39, count 0 2006.196.08:04:42.57#ibcon#read 4, iclass 39, count 0 2006.196.08:04:42.57#ibcon#about to read 5, iclass 39, count 0 2006.196.08:04:42.57#ibcon#read 5, iclass 39, count 0 2006.196.08:04:42.57#ibcon#about to read 6, iclass 39, count 0 2006.196.08:04:42.57#ibcon#read 6, iclass 39, count 0 2006.196.08:04:42.57#ibcon#end of sib2, iclass 39, count 0 2006.196.08:04:42.57#ibcon#*mode == 0, iclass 39, count 0 2006.196.08:04:42.57#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.196.08:04:42.57#ibcon#[27=USB\r\n] 2006.196.08:04:42.57#ibcon#*before write, iclass 39, count 0 2006.196.08:04:42.57#ibcon#enter sib2, iclass 39, count 0 2006.196.08:04:42.57#ibcon#flushed, iclass 39, count 0 2006.196.08:04:42.57#ibcon#about to write, iclass 39, count 0 2006.196.08:04:42.57#ibcon#wrote, iclass 39, count 0 2006.196.08:04:42.57#ibcon#about to read 3, iclass 39, count 0 2006.196.08:04:42.58#abcon#<5=/04 3.3 6.7 29.39 901003.9\r\n> 2006.196.08:04:42.60#abcon#{5=INTERFACE CLEAR} 2006.196.08:04:42.60#ibcon#read 3, iclass 39, count 0 2006.196.08:04:42.60#ibcon#about to read 4, iclass 39, count 0 2006.196.08:04:42.60#ibcon#read 4, iclass 39, count 0 2006.196.08:04:42.60#ibcon#about to read 5, iclass 39, count 0 2006.196.08:04:42.60#ibcon#read 5, iclass 39, count 0 2006.196.08:04:42.60#ibcon#about to read 6, iclass 39, count 0 2006.196.08:04:42.60#ibcon#read 6, iclass 39, count 0 2006.196.08:04:42.60#ibcon#end of sib2, iclass 39, count 0 2006.196.08:04:42.60#ibcon#*after write, iclass 39, count 0 2006.196.08:04:42.60#ibcon#*before return 0, iclass 39, count 0 2006.196.08:04:42.60#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.196.08:04:42.60#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.196.08:04:42.60#ibcon#about to clear, iclass 39 cls_cnt 0 2006.196.08:04:42.60#ibcon#cleared, iclass 39 cls_cnt 0 2006.196.08:04:42.60$vc4f8/vabw=wide 2006.196.08:04:42.60#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.196.08:04:42.60#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.196.08:04:42.60#ibcon#ireg 8 cls_cnt 0 2006.196.08:04:42.60#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.196.08:04:42.60#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.196.08:04:42.60#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.196.08:04:42.60#ibcon#enter wrdev, iclass 6, count 0 2006.196.08:04:42.60#ibcon#first serial, iclass 6, count 0 2006.196.08:04:42.60#ibcon#enter sib2, iclass 6, count 0 2006.196.08:04:42.60#ibcon#flushed, iclass 6, count 0 2006.196.08:04:42.60#ibcon#about to write, iclass 6, count 0 2006.196.08:04:42.60#ibcon#wrote, iclass 6, count 0 2006.196.08:04:42.60#ibcon#about to read 3, iclass 6, count 0 2006.196.08:04:42.62#ibcon#read 3, iclass 6, count 0 2006.196.08:04:42.62#ibcon#about to read 4, iclass 6, count 0 2006.196.08:04:42.62#ibcon#read 4, iclass 6, count 0 2006.196.08:04:42.62#ibcon#about to read 5, iclass 6, count 0 2006.196.08:04:42.62#ibcon#read 5, iclass 6, count 0 2006.196.08:04:42.62#ibcon#about to read 6, iclass 6, count 0 2006.196.08:04:42.62#ibcon#read 6, iclass 6, count 0 2006.196.08:04:42.62#ibcon#end of sib2, iclass 6, count 0 2006.196.08:04:42.62#ibcon#*mode == 0, iclass 6, count 0 2006.196.08:04:42.62#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.196.08:04:42.62#ibcon#[25=BW32\r\n] 2006.196.08:04:42.62#ibcon#*before write, iclass 6, count 0 2006.196.08:04:42.62#ibcon#enter sib2, iclass 6, count 0 2006.196.08:04:42.62#ibcon#flushed, iclass 6, count 0 2006.196.08:04:42.62#ibcon#about to write, iclass 6, count 0 2006.196.08:04:42.62#ibcon#wrote, iclass 6, count 0 2006.196.08:04:42.62#ibcon#about to read 3, iclass 6, count 0 2006.196.08:04:42.66#ibcon#read 3, iclass 6, count 0 2006.196.08:04:42.66#ibcon#about to read 4, iclass 6, count 0 2006.196.08:04:42.66#ibcon#read 4, iclass 6, count 0 2006.196.08:04:42.66#ibcon#about to read 5, iclass 6, count 0 2006.196.08:04:42.66#ibcon#read 5, iclass 6, count 0 2006.196.08:04:42.66#ibcon#about to read 6, iclass 6, count 0 2006.196.08:04:42.66#ibcon#read 6, iclass 6, count 0 2006.196.08:04:42.66#ibcon#end of sib2, iclass 6, count 0 2006.196.08:04:42.66#ibcon#*after write, iclass 6, count 0 2006.196.08:04:42.66#ibcon#*before return 0, iclass 6, count 0 2006.196.08:04:42.66#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.196.08:04:42.66#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.196.08:04:42.66#ibcon#about to clear, iclass 6 cls_cnt 0 2006.196.08:04:42.66#ibcon#cleared, iclass 6 cls_cnt 0 2006.196.08:04:42.66$vc4f8/vbbw=wide 2006.196.08:04:42.66#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.196.08:04:42.66#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.196.08:04:42.66#ibcon#ireg 8 cls_cnt 0 2006.196.08:04:42.66#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.196.08:04:42.66#abcon#[5=S1D000X0/0*\r\n] 2006.196.08:04:42.72#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.196.08:04:42.72#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.196.08:04:42.72#ibcon#enter wrdev, iclass 11, count 0 2006.196.08:04:42.72#ibcon#first serial, iclass 11, count 0 2006.196.08:04:42.72#ibcon#enter sib2, iclass 11, count 0 2006.196.08:04:42.72#ibcon#flushed, iclass 11, count 0 2006.196.08:04:42.72#ibcon#about to write, iclass 11, count 0 2006.196.08:04:42.72#ibcon#wrote, iclass 11, count 0 2006.196.08:04:42.72#ibcon#about to read 3, iclass 11, count 0 2006.196.08:04:42.74#ibcon#read 3, iclass 11, count 0 2006.196.08:04:42.74#ibcon#about to read 4, iclass 11, count 0 2006.196.08:04:42.74#ibcon#read 4, iclass 11, count 0 2006.196.08:04:42.74#ibcon#about to read 5, iclass 11, count 0 2006.196.08:04:42.74#ibcon#read 5, iclass 11, count 0 2006.196.08:04:42.74#ibcon#about to read 6, iclass 11, count 0 2006.196.08:04:42.74#ibcon#read 6, iclass 11, count 0 2006.196.08:04:42.74#ibcon#end of sib2, iclass 11, count 0 2006.196.08:04:42.74#ibcon#*mode == 0, iclass 11, count 0 2006.196.08:04:42.74#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.196.08:04:42.74#ibcon#[27=BW32\r\n] 2006.196.08:04:42.74#ibcon#*before write, iclass 11, count 0 2006.196.08:04:42.74#ibcon#enter sib2, iclass 11, count 0 2006.196.08:04:42.74#ibcon#flushed, iclass 11, count 0 2006.196.08:04:42.74#ibcon#about to write, iclass 11, count 0 2006.196.08:04:42.74#ibcon#wrote, iclass 11, count 0 2006.196.08:04:42.74#ibcon#about to read 3, iclass 11, count 0 2006.196.08:04:42.77#ibcon#read 3, iclass 11, count 0 2006.196.08:04:42.77#ibcon#about to read 4, iclass 11, count 0 2006.196.08:04:42.77#ibcon#read 4, iclass 11, count 0 2006.196.08:04:42.77#ibcon#about to read 5, iclass 11, count 0 2006.196.08:04:42.77#ibcon#read 5, iclass 11, count 0 2006.196.08:04:42.77#ibcon#about to read 6, iclass 11, count 0 2006.196.08:04:42.77#ibcon#read 6, iclass 11, count 0 2006.196.08:04:42.77#ibcon#end of sib2, iclass 11, count 0 2006.196.08:04:42.77#ibcon#*after write, iclass 11, count 0 2006.196.08:04:42.77#ibcon#*before return 0, iclass 11, count 0 2006.196.08:04:42.77#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.196.08:04:42.77#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.196.08:04:42.77#ibcon#about to clear, iclass 11 cls_cnt 0 2006.196.08:04:42.77#ibcon#cleared, iclass 11 cls_cnt 0 2006.196.08:04:42.77$4f8m12a/ifd4f 2006.196.08:04:42.77$ifd4f/lo= 2006.196.08:04:42.77$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.196.08:04:42.77$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.196.08:04:42.77$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.196.08:04:42.77$ifd4f/patch= 2006.196.08:04:42.77$ifd4f/patch=lo1,a1,a2,a3,a4 2006.196.08:04:42.77$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.196.08:04:42.77$ifd4f/patch=lo3,a5,a6,a7,a8 2006.196.08:04:42.77$4f8m12a/"form=m,16.000,1:2 2006.196.08:04:42.77$4f8m12a/"tpicd 2006.196.08:04:42.77$4f8m12a/echo=off 2006.196.08:04:42.77$4f8m12a/xlog=off 2006.196.08:04:42.77:!2006.196.08:05:10 2006.196.08:04:49.14#trakl#Source acquired 2006.196.08:04:49.14#flagr#flagr/antenna,acquired 2006.196.08:05:10.00:preob 2006.196.08:05:11.14/onsource/TRACKING 2006.196.08:05:11.14:!2006.196.08:05:20 2006.196.08:05:20.00:data_valid=on 2006.196.08:05:20.00:midob 2006.196.08:05:20.14/onsource/TRACKING 2006.196.08:05:20.14/wx/29.38,1003.9,89 2006.196.08:05:20.27/cable/+6.3333E-03 2006.196.08:05:21.36/va/01,08,usb,yes,29,31 2006.196.08:05:21.36/va/02,07,usb,yes,29,31 2006.196.08:05:21.36/va/03,06,usb,yes,31,31 2006.196.08:05:21.36/va/04,07,usb,yes,30,32 2006.196.08:05:21.36/va/05,07,usb,yes,32,34 2006.196.08:05:21.36/va/06,06,usb,yes,31,31 2006.196.08:05:21.36/va/07,06,usb,yes,32,32 2006.196.08:05:21.36/va/08,07,usb,yes,30,30 2006.196.08:05:21.59/valo/01,532.99,yes,locked 2006.196.08:05:21.59/valo/02,572.99,yes,locked 2006.196.08:05:21.59/valo/03,672.99,yes,locked 2006.196.08:05:21.59/valo/04,832.99,yes,locked 2006.196.08:05:21.59/valo/05,652.99,yes,locked 2006.196.08:05:21.59/valo/06,772.99,yes,locked 2006.196.08:05:21.59/valo/07,832.99,yes,locked 2006.196.08:05:21.59/valo/08,852.99,yes,locked 2006.196.08:05:22.68/vb/01,04,usb,yes,29,27 2006.196.08:05:22.68/vb/02,04,usb,yes,30,32 2006.196.08:05:22.68/vb/03,04,usb,yes,27,31 2006.196.08:05:22.68/vb/04,04,usb,yes,28,28 2006.196.08:05:22.68/vb/05,04,usb,yes,26,30 2006.196.08:05:22.68/vb/06,04,usb,yes,27,30 2006.196.08:05:22.68/vb/07,04,usb,yes,29,29 2006.196.08:05:22.68/vb/08,04,usb,yes,27,30 2006.196.08:05:22.91/vblo/01,632.99,yes,locked 2006.196.08:05:22.91/vblo/02,640.99,yes,locked 2006.196.08:05:22.91/vblo/03,656.99,yes,locked 2006.196.08:05:22.91/vblo/04,712.99,yes,locked 2006.196.08:05:22.91/vblo/05,744.99,yes,locked 2006.196.08:05:22.91/vblo/06,752.99,yes,locked 2006.196.08:05:22.91/vblo/07,734.99,yes,locked 2006.196.08:05:22.91/vblo/08,744.99,yes,locked 2006.196.08:05:23.06/vabw/8 2006.196.08:05:23.21/vbbw/8 2006.196.08:05:23.30/xfe/off,on,14.7 2006.196.08:05:23.73/ifatt/23,28,28,28 2006.196.08:05:24.07/fmout-gps/S +3.36E-07 2006.196.08:05:24.14:!2006.196.08:06:20 2006.196.08:06:20.00:data_valid=off 2006.196.08:06:20.00:postob 2006.196.08:06:20.14/cable/+6.3335E-03 2006.196.08:06:20.14/wx/29.35,1003.9,91 2006.196.08:06:21.07/fmout-gps/S +3.37E-07 2006.196.08:06:21.07:scan_name=196-0807,k06196,60 2006.196.08:06:21.07:source=1300+580,130252.47,574837.6,2000.0,neutral 2006.196.08:06:21.14#flagr#flagr/antenna,new-source 2006.196.08:06:22.13:checkk5 2006.196.08:06:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.196.08:06:22.89/chk_autoobs//k5ts2/ autoobs is running! 2006.196.08:06:23.27/chk_autoobs//k5ts3/ autoobs is running! 2006.196.08:06:23.65/chk_autoobs//k5ts4/ autoobs is running! 2006.196.08:06:24.02/chk_obsdata//k5ts1/T1960805??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.08:06:24.39/chk_obsdata//k5ts2/T1960805??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.08:06:24.76/chk_obsdata//k5ts3/T1960805??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.08:06:25.13/chk_obsdata//k5ts4/T1960805??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.08:06:25.82/k5log//k5ts1_log_newline 2006.196.08:06:26.51/k5log//k5ts2_log_newline 2006.196.08:06:27.20/k5log//k5ts3_log_newline 2006.196.08:06:27.89/k5log//k5ts4_log_newline 2006.196.08:06:27.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.196.08:06:27.91:4f8m12a=2 2006.196.08:06:27.91$4f8m12a/echo=on 2006.196.08:06:27.91$4f8m12a/pcalon 2006.196.08:06:27.91$pcalon/"no phase cal control is implemented here 2006.196.08:06:27.91$4f8m12a/"tpicd=stop 2006.196.08:06:27.91$4f8m12a/vc4f8 2006.196.08:06:27.91$vc4f8/valo=1,532.99 2006.196.08:06:27.92#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.196.08:06:27.92#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.196.08:06:27.92#ibcon#ireg 17 cls_cnt 0 2006.196.08:06:27.92#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.196.08:06:27.92#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.196.08:06:27.92#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.196.08:06:27.92#ibcon#enter wrdev, iclass 18, count 0 2006.196.08:06:27.92#ibcon#first serial, iclass 18, count 0 2006.196.08:06:27.92#ibcon#enter sib2, iclass 18, count 0 2006.196.08:06:27.92#ibcon#flushed, iclass 18, count 0 2006.196.08:06:27.92#ibcon#about to write, iclass 18, count 0 2006.196.08:06:27.92#ibcon#wrote, iclass 18, count 0 2006.196.08:06:27.92#ibcon#about to read 3, iclass 18, count 0 2006.196.08:06:27.96#ibcon#read 3, iclass 18, count 0 2006.196.08:06:27.96#ibcon#about to read 4, iclass 18, count 0 2006.196.08:06:27.96#ibcon#read 4, iclass 18, count 0 2006.196.08:06:27.96#ibcon#about to read 5, iclass 18, count 0 2006.196.08:06:27.96#ibcon#read 5, iclass 18, count 0 2006.196.08:06:27.96#ibcon#about to read 6, iclass 18, count 0 2006.196.08:06:27.96#ibcon#read 6, iclass 18, count 0 2006.196.08:06:27.96#ibcon#end of sib2, iclass 18, count 0 2006.196.08:06:27.96#ibcon#*mode == 0, iclass 18, count 0 2006.196.08:06:27.96#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.196.08:06:27.96#ibcon#[26=FRQ=01,532.99\r\n] 2006.196.08:06:27.96#ibcon#*before write, iclass 18, count 0 2006.196.08:06:27.96#ibcon#enter sib2, iclass 18, count 0 2006.196.08:06:27.96#ibcon#flushed, iclass 18, count 0 2006.196.08:06:27.96#ibcon#about to write, iclass 18, count 0 2006.196.08:06:27.96#ibcon#wrote, iclass 18, count 0 2006.196.08:06:27.96#ibcon#about to read 3, iclass 18, count 0 2006.196.08:06:28.01#ibcon#read 3, iclass 18, count 0 2006.196.08:06:28.01#ibcon#about to read 4, iclass 18, count 0 2006.196.08:06:28.01#ibcon#read 4, iclass 18, count 0 2006.196.08:06:28.01#ibcon#about to read 5, iclass 18, count 0 2006.196.08:06:28.01#ibcon#read 5, iclass 18, count 0 2006.196.08:06:28.01#ibcon#about to read 6, iclass 18, count 0 2006.196.08:06:28.01#ibcon#read 6, iclass 18, count 0 2006.196.08:06:28.01#ibcon#end of sib2, iclass 18, count 0 2006.196.08:06:28.01#ibcon#*after write, iclass 18, count 0 2006.196.08:06:28.01#ibcon#*before return 0, iclass 18, count 0 2006.196.08:06:28.01#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.196.08:06:28.01#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.196.08:06:28.01#ibcon#about to clear, iclass 18 cls_cnt 0 2006.196.08:06:28.01#ibcon#cleared, iclass 18 cls_cnt 0 2006.196.08:06:28.01$vc4f8/va=1,8 2006.196.08:06:28.01#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.196.08:06:28.01#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.196.08:06:28.01#ibcon#ireg 11 cls_cnt 2 2006.196.08:06:28.01#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.196.08:06:28.01#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.196.08:06:28.01#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.196.08:06:28.01#ibcon#enter wrdev, iclass 20, count 2 2006.196.08:06:28.01#ibcon#first serial, iclass 20, count 2 2006.196.08:06:28.01#ibcon#enter sib2, iclass 20, count 2 2006.196.08:06:28.01#ibcon#flushed, iclass 20, count 2 2006.196.08:06:28.01#ibcon#about to write, iclass 20, count 2 2006.196.08:06:28.01#ibcon#wrote, iclass 20, count 2 2006.196.08:06:28.01#ibcon#about to read 3, iclass 20, count 2 2006.196.08:06:28.03#ibcon#read 3, iclass 20, count 2 2006.196.08:06:28.03#ibcon#about to read 4, iclass 20, count 2 2006.196.08:06:28.03#ibcon#read 4, iclass 20, count 2 2006.196.08:06:28.03#ibcon#about to read 5, iclass 20, count 2 2006.196.08:06:28.03#ibcon#read 5, iclass 20, count 2 2006.196.08:06:28.03#ibcon#about to read 6, iclass 20, count 2 2006.196.08:06:28.03#ibcon#read 6, iclass 20, count 2 2006.196.08:06:28.03#ibcon#end of sib2, iclass 20, count 2 2006.196.08:06:28.03#ibcon#*mode == 0, iclass 20, count 2 2006.196.08:06:28.03#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.196.08:06:28.03#ibcon#[25=AT01-08\r\n] 2006.196.08:06:28.03#ibcon#*before write, iclass 20, count 2 2006.196.08:06:28.03#ibcon#enter sib2, iclass 20, count 2 2006.196.08:06:28.03#ibcon#flushed, iclass 20, count 2 2006.196.08:06:28.03#ibcon#about to write, iclass 20, count 2 2006.196.08:06:28.03#ibcon#wrote, iclass 20, count 2 2006.196.08:06:28.03#ibcon#about to read 3, iclass 20, count 2 2006.196.08:06:28.07#ibcon#read 3, iclass 20, count 2 2006.196.08:06:28.07#ibcon#about to read 4, iclass 20, count 2 2006.196.08:06:28.07#ibcon#read 4, iclass 20, count 2 2006.196.08:06:28.07#ibcon#about to read 5, iclass 20, count 2 2006.196.08:06:28.07#ibcon#read 5, iclass 20, count 2 2006.196.08:06:28.07#ibcon#about to read 6, iclass 20, count 2 2006.196.08:06:28.07#ibcon#read 6, iclass 20, count 2 2006.196.08:06:28.07#ibcon#end of sib2, iclass 20, count 2 2006.196.08:06:28.07#ibcon#*after write, iclass 20, count 2 2006.196.08:06:28.07#ibcon#*before return 0, iclass 20, count 2 2006.196.08:06:28.07#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.196.08:06:28.07#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.196.08:06:28.07#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.196.08:06:28.07#ibcon#ireg 7 cls_cnt 0 2006.196.08:06:28.07#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.196.08:06:28.19#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.196.08:06:28.19#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.196.08:06:28.19#ibcon#enter wrdev, iclass 20, count 0 2006.196.08:06:28.19#ibcon#first serial, iclass 20, count 0 2006.196.08:06:28.19#ibcon#enter sib2, iclass 20, count 0 2006.196.08:06:28.19#ibcon#flushed, iclass 20, count 0 2006.196.08:06:28.19#ibcon#about to write, iclass 20, count 0 2006.196.08:06:28.19#ibcon#wrote, iclass 20, count 0 2006.196.08:06:28.19#ibcon#about to read 3, iclass 20, count 0 2006.196.08:06:28.22#ibcon#read 3, iclass 20, count 0 2006.196.08:06:28.22#ibcon#about to read 4, iclass 20, count 0 2006.196.08:06:28.22#ibcon#read 4, iclass 20, count 0 2006.196.08:06:28.22#ibcon#about to read 5, iclass 20, count 0 2006.196.08:06:28.22#ibcon#read 5, iclass 20, count 0 2006.196.08:06:28.22#ibcon#about to read 6, iclass 20, count 0 2006.196.08:06:28.22#ibcon#read 6, iclass 20, count 0 2006.196.08:06:28.22#ibcon#end of sib2, iclass 20, count 0 2006.196.08:06:28.22#ibcon#*mode == 0, iclass 20, count 0 2006.196.08:06:28.22#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.196.08:06:28.22#ibcon#[25=USB\r\n] 2006.196.08:06:28.22#ibcon#*before write, iclass 20, count 0 2006.196.08:06:28.22#ibcon#enter sib2, iclass 20, count 0 2006.196.08:06:28.22#ibcon#flushed, iclass 20, count 0 2006.196.08:06:28.22#ibcon#about to write, iclass 20, count 0 2006.196.08:06:28.22#ibcon#wrote, iclass 20, count 0 2006.196.08:06:28.22#ibcon#about to read 3, iclass 20, count 0 2006.196.08:06:28.25#ibcon#read 3, iclass 20, count 0 2006.196.08:06:28.25#ibcon#about to read 4, iclass 20, count 0 2006.196.08:06:28.25#ibcon#read 4, iclass 20, count 0 2006.196.08:06:28.25#ibcon#about to read 5, iclass 20, count 0 2006.196.08:06:28.25#ibcon#read 5, iclass 20, count 0 2006.196.08:06:28.25#ibcon#about to read 6, iclass 20, count 0 2006.196.08:06:28.25#ibcon#read 6, iclass 20, count 0 2006.196.08:06:28.25#ibcon#end of sib2, iclass 20, count 0 2006.196.08:06:28.25#ibcon#*after write, iclass 20, count 0 2006.196.08:06:28.25#ibcon#*before return 0, iclass 20, count 0 2006.196.08:06:28.25#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.196.08:06:28.25#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.196.08:06:28.25#ibcon#about to clear, iclass 20 cls_cnt 0 2006.196.08:06:28.25#ibcon#cleared, iclass 20 cls_cnt 0 2006.196.08:06:28.25$vc4f8/valo=2,572.99 2006.196.08:06:28.25#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.196.08:06:28.25#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.196.08:06:28.25#ibcon#ireg 17 cls_cnt 0 2006.196.08:06:28.25#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.196.08:06:28.25#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.196.08:06:28.25#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.196.08:06:28.25#ibcon#enter wrdev, iclass 22, count 0 2006.196.08:06:28.25#ibcon#first serial, iclass 22, count 0 2006.196.08:06:28.25#ibcon#enter sib2, iclass 22, count 0 2006.196.08:06:28.25#ibcon#flushed, iclass 22, count 0 2006.196.08:06:28.25#ibcon#about to write, iclass 22, count 0 2006.196.08:06:28.25#ibcon#wrote, iclass 22, count 0 2006.196.08:06:28.25#ibcon#about to read 3, iclass 22, count 0 2006.196.08:06:28.27#ibcon#read 3, iclass 22, count 0 2006.196.08:06:28.27#ibcon#about to read 4, iclass 22, count 0 2006.196.08:06:28.27#ibcon#read 4, iclass 22, count 0 2006.196.08:06:28.27#ibcon#about to read 5, iclass 22, count 0 2006.196.08:06:28.27#ibcon#read 5, iclass 22, count 0 2006.196.08:06:28.27#ibcon#about to read 6, iclass 22, count 0 2006.196.08:06:28.27#ibcon#read 6, iclass 22, count 0 2006.196.08:06:28.27#ibcon#end of sib2, iclass 22, count 0 2006.196.08:06:28.27#ibcon#*mode == 0, iclass 22, count 0 2006.196.08:06:28.27#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.196.08:06:28.27#ibcon#[26=FRQ=02,572.99\r\n] 2006.196.08:06:28.27#ibcon#*before write, iclass 22, count 0 2006.196.08:06:28.27#ibcon#enter sib2, iclass 22, count 0 2006.196.08:06:28.27#ibcon#flushed, iclass 22, count 0 2006.196.08:06:28.27#ibcon#about to write, iclass 22, count 0 2006.196.08:06:28.27#ibcon#wrote, iclass 22, count 0 2006.196.08:06:28.27#ibcon#about to read 3, iclass 22, count 0 2006.196.08:06:28.31#ibcon#read 3, iclass 22, count 0 2006.196.08:06:28.31#ibcon#about to read 4, iclass 22, count 0 2006.196.08:06:28.31#ibcon#read 4, iclass 22, count 0 2006.196.08:06:28.31#ibcon#about to read 5, iclass 22, count 0 2006.196.08:06:28.31#ibcon#read 5, iclass 22, count 0 2006.196.08:06:28.31#ibcon#about to read 6, iclass 22, count 0 2006.196.08:06:28.31#ibcon#read 6, iclass 22, count 0 2006.196.08:06:28.31#ibcon#end of sib2, iclass 22, count 0 2006.196.08:06:28.31#ibcon#*after write, iclass 22, count 0 2006.196.08:06:28.31#ibcon#*before return 0, iclass 22, count 0 2006.196.08:06:28.31#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.196.08:06:28.31#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.196.08:06:28.31#ibcon#about to clear, iclass 22 cls_cnt 0 2006.196.08:06:28.31#ibcon#cleared, iclass 22 cls_cnt 0 2006.196.08:06:28.31$vc4f8/va=2,7 2006.196.08:06:28.31#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.196.08:06:28.31#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.196.08:06:28.31#ibcon#ireg 11 cls_cnt 2 2006.196.08:06:28.31#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.196.08:06:28.37#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.196.08:06:28.37#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.196.08:06:28.37#ibcon#enter wrdev, iclass 24, count 2 2006.196.08:06:28.37#ibcon#first serial, iclass 24, count 2 2006.196.08:06:28.37#ibcon#enter sib2, iclass 24, count 2 2006.196.08:06:28.37#ibcon#flushed, iclass 24, count 2 2006.196.08:06:28.37#ibcon#about to write, iclass 24, count 2 2006.196.08:06:28.37#ibcon#wrote, iclass 24, count 2 2006.196.08:06:28.37#ibcon#about to read 3, iclass 24, count 2 2006.196.08:06:28.39#ibcon#read 3, iclass 24, count 2 2006.196.08:06:28.39#ibcon#about to read 4, iclass 24, count 2 2006.196.08:06:28.39#ibcon#read 4, iclass 24, count 2 2006.196.08:06:28.39#ibcon#about to read 5, iclass 24, count 2 2006.196.08:06:28.39#ibcon#read 5, iclass 24, count 2 2006.196.08:06:28.39#ibcon#about to read 6, iclass 24, count 2 2006.196.08:06:28.39#ibcon#read 6, iclass 24, count 2 2006.196.08:06:28.39#ibcon#end of sib2, iclass 24, count 2 2006.196.08:06:28.39#ibcon#*mode == 0, iclass 24, count 2 2006.196.08:06:28.39#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.196.08:06:28.39#ibcon#[25=AT02-07\r\n] 2006.196.08:06:28.39#ibcon#*before write, iclass 24, count 2 2006.196.08:06:28.39#ibcon#enter sib2, iclass 24, count 2 2006.196.08:06:28.39#ibcon#flushed, iclass 24, count 2 2006.196.08:06:28.39#ibcon#about to write, iclass 24, count 2 2006.196.08:06:28.39#ibcon#wrote, iclass 24, count 2 2006.196.08:06:28.39#ibcon#about to read 3, iclass 24, count 2 2006.196.08:06:28.42#ibcon#read 3, iclass 24, count 2 2006.196.08:06:28.42#ibcon#about to read 4, iclass 24, count 2 2006.196.08:06:28.42#ibcon#read 4, iclass 24, count 2 2006.196.08:06:28.42#ibcon#about to read 5, iclass 24, count 2 2006.196.08:06:28.42#ibcon#read 5, iclass 24, count 2 2006.196.08:06:28.42#ibcon#about to read 6, iclass 24, count 2 2006.196.08:06:28.42#ibcon#read 6, iclass 24, count 2 2006.196.08:06:28.42#ibcon#end of sib2, iclass 24, count 2 2006.196.08:06:28.42#ibcon#*after write, iclass 24, count 2 2006.196.08:06:28.42#ibcon#*before return 0, iclass 24, count 2 2006.196.08:06:28.42#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.196.08:06:28.42#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.196.08:06:28.42#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.196.08:06:28.42#ibcon#ireg 7 cls_cnt 0 2006.196.08:06:28.42#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.196.08:06:28.54#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.196.08:06:28.54#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.196.08:06:28.54#ibcon#enter wrdev, iclass 24, count 0 2006.196.08:06:28.54#ibcon#first serial, iclass 24, count 0 2006.196.08:06:28.54#ibcon#enter sib2, iclass 24, count 0 2006.196.08:06:28.54#ibcon#flushed, iclass 24, count 0 2006.196.08:06:28.54#ibcon#about to write, iclass 24, count 0 2006.196.08:06:28.54#ibcon#wrote, iclass 24, count 0 2006.196.08:06:28.54#ibcon#about to read 3, iclass 24, count 0 2006.196.08:06:28.56#ibcon#read 3, iclass 24, count 0 2006.196.08:06:28.56#ibcon#about to read 4, iclass 24, count 0 2006.196.08:06:28.56#ibcon#read 4, iclass 24, count 0 2006.196.08:06:28.56#ibcon#about to read 5, iclass 24, count 0 2006.196.08:06:28.56#ibcon#read 5, iclass 24, count 0 2006.196.08:06:28.56#ibcon#about to read 6, iclass 24, count 0 2006.196.08:06:28.56#ibcon#read 6, iclass 24, count 0 2006.196.08:06:28.56#ibcon#end of sib2, iclass 24, count 0 2006.196.08:06:28.56#ibcon#*mode == 0, iclass 24, count 0 2006.196.08:06:28.56#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.196.08:06:28.56#ibcon#[25=USB\r\n] 2006.196.08:06:28.56#ibcon#*before write, iclass 24, count 0 2006.196.08:06:28.56#ibcon#enter sib2, iclass 24, count 0 2006.196.08:06:28.56#ibcon#flushed, iclass 24, count 0 2006.196.08:06:28.56#ibcon#about to write, iclass 24, count 0 2006.196.08:06:28.56#ibcon#wrote, iclass 24, count 0 2006.196.08:06:28.56#ibcon#about to read 3, iclass 24, count 0 2006.196.08:06:28.59#ibcon#read 3, iclass 24, count 0 2006.196.08:06:28.59#ibcon#about to read 4, iclass 24, count 0 2006.196.08:06:28.59#ibcon#read 4, iclass 24, count 0 2006.196.08:06:28.59#ibcon#about to read 5, iclass 24, count 0 2006.196.08:06:28.59#ibcon#read 5, iclass 24, count 0 2006.196.08:06:28.59#ibcon#about to read 6, iclass 24, count 0 2006.196.08:06:28.59#ibcon#read 6, iclass 24, count 0 2006.196.08:06:28.59#ibcon#end of sib2, iclass 24, count 0 2006.196.08:06:28.59#ibcon#*after write, iclass 24, count 0 2006.196.08:06:28.59#ibcon#*before return 0, iclass 24, count 0 2006.196.08:06:28.59#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.196.08:06:28.59#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.196.08:06:28.59#ibcon#about to clear, iclass 24 cls_cnt 0 2006.196.08:06:28.59#ibcon#cleared, iclass 24 cls_cnt 0 2006.196.08:06:28.59$vc4f8/valo=3,672.99 2006.196.08:06:28.59#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.196.08:06:28.59#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.196.08:06:28.59#ibcon#ireg 17 cls_cnt 0 2006.196.08:06:28.59#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.196.08:06:28.59#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.196.08:06:28.59#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.196.08:06:28.59#ibcon#enter wrdev, iclass 26, count 0 2006.196.08:06:28.59#ibcon#first serial, iclass 26, count 0 2006.196.08:06:28.59#ibcon#enter sib2, iclass 26, count 0 2006.196.08:06:28.59#ibcon#flushed, iclass 26, count 0 2006.196.08:06:28.59#ibcon#about to write, iclass 26, count 0 2006.196.08:06:28.59#ibcon#wrote, iclass 26, count 0 2006.196.08:06:28.59#ibcon#about to read 3, iclass 26, count 0 2006.196.08:06:28.61#ibcon#read 3, iclass 26, count 0 2006.196.08:06:28.61#ibcon#about to read 4, iclass 26, count 0 2006.196.08:06:28.61#ibcon#read 4, iclass 26, count 0 2006.196.08:06:28.61#ibcon#about to read 5, iclass 26, count 0 2006.196.08:06:28.61#ibcon#read 5, iclass 26, count 0 2006.196.08:06:28.61#ibcon#about to read 6, iclass 26, count 0 2006.196.08:06:28.61#ibcon#read 6, iclass 26, count 0 2006.196.08:06:28.61#ibcon#end of sib2, iclass 26, count 0 2006.196.08:06:28.61#ibcon#*mode == 0, iclass 26, count 0 2006.196.08:06:28.61#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.196.08:06:28.61#ibcon#[26=FRQ=03,672.99\r\n] 2006.196.08:06:28.61#ibcon#*before write, iclass 26, count 0 2006.196.08:06:28.61#ibcon#enter sib2, iclass 26, count 0 2006.196.08:06:28.61#ibcon#flushed, iclass 26, count 0 2006.196.08:06:28.61#ibcon#about to write, iclass 26, count 0 2006.196.08:06:28.61#ibcon#wrote, iclass 26, count 0 2006.196.08:06:28.61#ibcon#about to read 3, iclass 26, count 0 2006.196.08:06:28.66#ibcon#read 3, iclass 26, count 0 2006.196.08:06:28.66#ibcon#about to read 4, iclass 26, count 0 2006.196.08:06:28.66#ibcon#read 4, iclass 26, count 0 2006.196.08:06:28.66#ibcon#about to read 5, iclass 26, count 0 2006.196.08:06:28.66#ibcon#read 5, iclass 26, count 0 2006.196.08:06:28.66#ibcon#about to read 6, iclass 26, count 0 2006.196.08:06:28.66#ibcon#read 6, iclass 26, count 0 2006.196.08:06:28.66#ibcon#end of sib2, iclass 26, count 0 2006.196.08:06:28.66#ibcon#*after write, iclass 26, count 0 2006.196.08:06:28.66#ibcon#*before return 0, iclass 26, count 0 2006.196.08:06:28.66#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.196.08:06:28.66#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.196.08:06:28.66#ibcon#about to clear, iclass 26 cls_cnt 0 2006.196.08:06:28.66#ibcon#cleared, iclass 26 cls_cnt 0 2006.196.08:06:28.66$vc4f8/va=3,6 2006.196.08:06:28.66#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.196.08:06:28.66#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.196.08:06:28.66#ibcon#ireg 11 cls_cnt 2 2006.196.08:06:28.66#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.196.08:06:28.71#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.196.08:06:28.71#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.196.08:06:28.71#ibcon#enter wrdev, iclass 28, count 2 2006.196.08:06:28.71#ibcon#first serial, iclass 28, count 2 2006.196.08:06:28.71#ibcon#enter sib2, iclass 28, count 2 2006.196.08:06:28.71#ibcon#flushed, iclass 28, count 2 2006.196.08:06:28.71#ibcon#about to write, iclass 28, count 2 2006.196.08:06:28.71#ibcon#wrote, iclass 28, count 2 2006.196.08:06:28.71#ibcon#about to read 3, iclass 28, count 2 2006.196.08:06:28.73#ibcon#read 3, iclass 28, count 2 2006.196.08:06:28.73#ibcon#about to read 4, iclass 28, count 2 2006.196.08:06:28.73#ibcon#read 4, iclass 28, count 2 2006.196.08:06:28.73#ibcon#about to read 5, iclass 28, count 2 2006.196.08:06:28.73#ibcon#read 5, iclass 28, count 2 2006.196.08:06:28.73#ibcon#about to read 6, iclass 28, count 2 2006.196.08:06:28.73#ibcon#read 6, iclass 28, count 2 2006.196.08:06:28.73#ibcon#end of sib2, iclass 28, count 2 2006.196.08:06:28.73#ibcon#*mode == 0, iclass 28, count 2 2006.196.08:06:28.73#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.196.08:06:28.73#ibcon#[25=AT03-06\r\n] 2006.196.08:06:28.73#ibcon#*before write, iclass 28, count 2 2006.196.08:06:28.73#ibcon#enter sib2, iclass 28, count 2 2006.196.08:06:28.73#ibcon#flushed, iclass 28, count 2 2006.196.08:06:28.73#ibcon#about to write, iclass 28, count 2 2006.196.08:06:28.73#ibcon#wrote, iclass 28, count 2 2006.196.08:06:28.73#ibcon#about to read 3, iclass 28, count 2 2006.196.08:06:28.76#ibcon#read 3, iclass 28, count 2 2006.196.08:06:28.76#ibcon#about to read 4, iclass 28, count 2 2006.196.08:06:28.76#ibcon#read 4, iclass 28, count 2 2006.196.08:06:28.76#ibcon#about to read 5, iclass 28, count 2 2006.196.08:06:28.76#ibcon#read 5, iclass 28, count 2 2006.196.08:06:28.76#ibcon#about to read 6, iclass 28, count 2 2006.196.08:06:28.76#ibcon#read 6, iclass 28, count 2 2006.196.08:06:28.76#ibcon#end of sib2, iclass 28, count 2 2006.196.08:06:28.76#ibcon#*after write, iclass 28, count 2 2006.196.08:06:28.76#ibcon#*before return 0, iclass 28, count 2 2006.196.08:06:28.76#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.196.08:06:28.76#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.196.08:06:28.76#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.196.08:06:28.76#ibcon#ireg 7 cls_cnt 0 2006.196.08:06:28.76#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.196.08:06:28.88#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.196.08:06:28.88#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.196.08:06:28.88#ibcon#enter wrdev, iclass 28, count 0 2006.196.08:06:28.88#ibcon#first serial, iclass 28, count 0 2006.196.08:06:28.88#ibcon#enter sib2, iclass 28, count 0 2006.196.08:06:28.88#ibcon#flushed, iclass 28, count 0 2006.196.08:06:28.88#ibcon#about to write, iclass 28, count 0 2006.196.08:06:28.88#ibcon#wrote, iclass 28, count 0 2006.196.08:06:28.88#ibcon#about to read 3, iclass 28, count 0 2006.196.08:06:28.90#ibcon#read 3, iclass 28, count 0 2006.196.08:06:28.90#ibcon#about to read 4, iclass 28, count 0 2006.196.08:06:28.90#ibcon#read 4, iclass 28, count 0 2006.196.08:06:28.90#ibcon#about to read 5, iclass 28, count 0 2006.196.08:06:28.90#ibcon#read 5, iclass 28, count 0 2006.196.08:06:28.90#ibcon#about to read 6, iclass 28, count 0 2006.196.08:06:28.90#ibcon#read 6, iclass 28, count 0 2006.196.08:06:28.90#ibcon#end of sib2, iclass 28, count 0 2006.196.08:06:28.90#ibcon#*mode == 0, iclass 28, count 0 2006.196.08:06:28.90#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.196.08:06:28.90#ibcon#[25=USB\r\n] 2006.196.08:06:28.90#ibcon#*before write, iclass 28, count 0 2006.196.08:06:28.90#ibcon#enter sib2, iclass 28, count 0 2006.196.08:06:28.90#ibcon#flushed, iclass 28, count 0 2006.196.08:06:28.90#ibcon#about to write, iclass 28, count 0 2006.196.08:06:28.90#ibcon#wrote, iclass 28, count 0 2006.196.08:06:28.90#ibcon#about to read 3, iclass 28, count 0 2006.196.08:06:28.93#ibcon#read 3, iclass 28, count 0 2006.196.08:06:28.93#ibcon#about to read 4, iclass 28, count 0 2006.196.08:06:28.93#ibcon#read 4, iclass 28, count 0 2006.196.08:06:28.93#ibcon#about to read 5, iclass 28, count 0 2006.196.08:06:28.93#ibcon#read 5, iclass 28, count 0 2006.196.08:06:28.93#ibcon#about to read 6, iclass 28, count 0 2006.196.08:06:28.93#ibcon#read 6, iclass 28, count 0 2006.196.08:06:28.93#ibcon#end of sib2, iclass 28, count 0 2006.196.08:06:28.93#ibcon#*after write, iclass 28, count 0 2006.196.08:06:28.93#ibcon#*before return 0, iclass 28, count 0 2006.196.08:06:28.93#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.196.08:06:28.93#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.196.08:06:28.93#ibcon#about to clear, iclass 28 cls_cnt 0 2006.196.08:06:28.93#ibcon#cleared, iclass 28 cls_cnt 0 2006.196.08:06:28.93$vc4f8/valo=4,832.99 2006.196.08:06:28.93#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.196.08:06:28.93#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.196.08:06:28.93#ibcon#ireg 17 cls_cnt 0 2006.196.08:06:28.93#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.196.08:06:28.93#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.196.08:06:28.93#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.196.08:06:28.93#ibcon#enter wrdev, iclass 30, count 0 2006.196.08:06:28.93#ibcon#first serial, iclass 30, count 0 2006.196.08:06:28.93#ibcon#enter sib2, iclass 30, count 0 2006.196.08:06:28.93#ibcon#flushed, iclass 30, count 0 2006.196.08:06:28.93#ibcon#about to write, iclass 30, count 0 2006.196.08:06:28.93#ibcon#wrote, iclass 30, count 0 2006.196.08:06:28.93#ibcon#about to read 3, iclass 30, count 0 2006.196.08:06:28.95#ibcon#read 3, iclass 30, count 0 2006.196.08:06:28.95#ibcon#about to read 4, iclass 30, count 0 2006.196.08:06:28.95#ibcon#read 4, iclass 30, count 0 2006.196.08:06:28.95#ibcon#about to read 5, iclass 30, count 0 2006.196.08:06:28.95#ibcon#read 5, iclass 30, count 0 2006.196.08:06:28.95#ibcon#about to read 6, iclass 30, count 0 2006.196.08:06:28.95#ibcon#read 6, iclass 30, count 0 2006.196.08:06:28.95#ibcon#end of sib2, iclass 30, count 0 2006.196.08:06:28.95#ibcon#*mode == 0, iclass 30, count 0 2006.196.08:06:28.95#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.196.08:06:28.95#ibcon#[26=FRQ=04,832.99\r\n] 2006.196.08:06:28.95#ibcon#*before write, iclass 30, count 0 2006.196.08:06:28.95#ibcon#enter sib2, iclass 30, count 0 2006.196.08:06:28.95#ibcon#flushed, iclass 30, count 0 2006.196.08:06:28.95#ibcon#about to write, iclass 30, count 0 2006.196.08:06:28.95#ibcon#wrote, iclass 30, count 0 2006.196.08:06:28.95#ibcon#about to read 3, iclass 30, count 0 2006.196.08:06:28.99#ibcon#read 3, iclass 30, count 0 2006.196.08:06:28.99#ibcon#about to read 4, iclass 30, count 0 2006.196.08:06:28.99#ibcon#read 4, iclass 30, count 0 2006.196.08:06:28.99#ibcon#about to read 5, iclass 30, count 0 2006.196.08:06:28.99#ibcon#read 5, iclass 30, count 0 2006.196.08:06:28.99#ibcon#about to read 6, iclass 30, count 0 2006.196.08:06:28.99#ibcon#read 6, iclass 30, count 0 2006.196.08:06:28.99#ibcon#end of sib2, iclass 30, count 0 2006.196.08:06:28.99#ibcon#*after write, iclass 30, count 0 2006.196.08:06:28.99#ibcon#*before return 0, iclass 30, count 0 2006.196.08:06:28.99#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.196.08:06:28.99#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.196.08:06:28.99#ibcon#about to clear, iclass 30 cls_cnt 0 2006.196.08:06:28.99#ibcon#cleared, iclass 30 cls_cnt 0 2006.196.08:06:28.99$vc4f8/va=4,7 2006.196.08:06:28.99#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.196.08:06:28.99#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.196.08:06:28.99#ibcon#ireg 11 cls_cnt 2 2006.196.08:06:28.99#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.196.08:06:29.05#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.196.08:06:29.05#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.196.08:06:29.05#ibcon#enter wrdev, iclass 32, count 2 2006.196.08:06:29.05#ibcon#first serial, iclass 32, count 2 2006.196.08:06:29.05#ibcon#enter sib2, iclass 32, count 2 2006.196.08:06:29.05#ibcon#flushed, iclass 32, count 2 2006.196.08:06:29.05#ibcon#about to write, iclass 32, count 2 2006.196.08:06:29.05#ibcon#wrote, iclass 32, count 2 2006.196.08:06:29.05#ibcon#about to read 3, iclass 32, count 2 2006.196.08:06:29.07#ibcon#read 3, iclass 32, count 2 2006.196.08:06:29.07#ibcon#about to read 4, iclass 32, count 2 2006.196.08:06:29.07#ibcon#read 4, iclass 32, count 2 2006.196.08:06:29.07#ibcon#about to read 5, iclass 32, count 2 2006.196.08:06:29.07#ibcon#read 5, iclass 32, count 2 2006.196.08:06:29.07#ibcon#about to read 6, iclass 32, count 2 2006.196.08:06:29.07#ibcon#read 6, iclass 32, count 2 2006.196.08:06:29.07#ibcon#end of sib2, iclass 32, count 2 2006.196.08:06:29.07#ibcon#*mode == 0, iclass 32, count 2 2006.196.08:06:29.07#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.196.08:06:29.07#ibcon#[25=AT04-07\r\n] 2006.196.08:06:29.07#ibcon#*before write, iclass 32, count 2 2006.196.08:06:29.07#ibcon#enter sib2, iclass 32, count 2 2006.196.08:06:29.07#ibcon#flushed, iclass 32, count 2 2006.196.08:06:29.07#ibcon#about to write, iclass 32, count 2 2006.196.08:06:29.07#ibcon#wrote, iclass 32, count 2 2006.196.08:06:29.07#ibcon#about to read 3, iclass 32, count 2 2006.196.08:06:29.10#ibcon#read 3, iclass 32, count 2 2006.196.08:06:29.10#ibcon#about to read 4, iclass 32, count 2 2006.196.08:06:29.10#ibcon#read 4, iclass 32, count 2 2006.196.08:06:29.10#ibcon#about to read 5, iclass 32, count 2 2006.196.08:06:29.10#ibcon#read 5, iclass 32, count 2 2006.196.08:06:29.10#ibcon#about to read 6, iclass 32, count 2 2006.196.08:06:29.10#ibcon#read 6, iclass 32, count 2 2006.196.08:06:29.10#ibcon#end of sib2, iclass 32, count 2 2006.196.08:06:29.10#ibcon#*after write, iclass 32, count 2 2006.196.08:06:29.10#ibcon#*before return 0, iclass 32, count 2 2006.196.08:06:29.10#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.196.08:06:29.10#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.196.08:06:29.10#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.196.08:06:29.10#ibcon#ireg 7 cls_cnt 0 2006.196.08:06:29.10#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.196.08:06:29.22#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.196.08:06:29.22#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.196.08:06:29.22#ibcon#enter wrdev, iclass 32, count 0 2006.196.08:06:29.22#ibcon#first serial, iclass 32, count 0 2006.196.08:06:29.22#ibcon#enter sib2, iclass 32, count 0 2006.196.08:06:29.22#ibcon#flushed, iclass 32, count 0 2006.196.08:06:29.22#ibcon#about to write, iclass 32, count 0 2006.196.08:06:29.22#ibcon#wrote, iclass 32, count 0 2006.196.08:06:29.22#ibcon#about to read 3, iclass 32, count 0 2006.196.08:06:29.24#ibcon#read 3, iclass 32, count 0 2006.196.08:06:29.24#ibcon#about to read 4, iclass 32, count 0 2006.196.08:06:29.24#ibcon#read 4, iclass 32, count 0 2006.196.08:06:29.24#ibcon#about to read 5, iclass 32, count 0 2006.196.08:06:29.24#ibcon#read 5, iclass 32, count 0 2006.196.08:06:29.24#ibcon#about to read 6, iclass 32, count 0 2006.196.08:06:29.24#ibcon#read 6, iclass 32, count 0 2006.196.08:06:29.24#ibcon#end of sib2, iclass 32, count 0 2006.196.08:06:29.24#ibcon#*mode == 0, iclass 32, count 0 2006.196.08:06:29.24#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.196.08:06:29.24#ibcon#[25=USB\r\n] 2006.196.08:06:29.24#ibcon#*before write, iclass 32, count 0 2006.196.08:06:29.24#ibcon#enter sib2, iclass 32, count 0 2006.196.08:06:29.24#ibcon#flushed, iclass 32, count 0 2006.196.08:06:29.24#ibcon#about to write, iclass 32, count 0 2006.196.08:06:29.24#ibcon#wrote, iclass 32, count 0 2006.196.08:06:29.24#ibcon#about to read 3, iclass 32, count 0 2006.196.08:06:29.27#ibcon#read 3, iclass 32, count 0 2006.196.08:06:29.27#ibcon#about to read 4, iclass 32, count 0 2006.196.08:06:29.27#ibcon#read 4, iclass 32, count 0 2006.196.08:06:29.27#ibcon#about to read 5, iclass 32, count 0 2006.196.08:06:29.27#ibcon#read 5, iclass 32, count 0 2006.196.08:06:29.27#ibcon#about to read 6, iclass 32, count 0 2006.196.08:06:29.27#ibcon#read 6, iclass 32, count 0 2006.196.08:06:29.27#ibcon#end of sib2, iclass 32, count 0 2006.196.08:06:29.27#ibcon#*after write, iclass 32, count 0 2006.196.08:06:29.27#ibcon#*before return 0, iclass 32, count 0 2006.196.08:06:29.27#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.196.08:06:29.27#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.196.08:06:29.27#ibcon#about to clear, iclass 32 cls_cnt 0 2006.196.08:06:29.27#ibcon#cleared, iclass 32 cls_cnt 0 2006.196.08:06:29.27$vc4f8/valo=5,652.99 2006.196.08:06:29.27#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.196.08:06:29.27#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.196.08:06:29.27#ibcon#ireg 17 cls_cnt 0 2006.196.08:06:29.27#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.196.08:06:29.27#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.196.08:06:29.27#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.196.08:06:29.27#ibcon#enter wrdev, iclass 34, count 0 2006.196.08:06:29.27#ibcon#first serial, iclass 34, count 0 2006.196.08:06:29.27#ibcon#enter sib2, iclass 34, count 0 2006.196.08:06:29.27#ibcon#flushed, iclass 34, count 0 2006.196.08:06:29.27#ibcon#about to write, iclass 34, count 0 2006.196.08:06:29.27#ibcon#wrote, iclass 34, count 0 2006.196.08:06:29.27#ibcon#about to read 3, iclass 34, count 0 2006.196.08:06:29.29#ibcon#read 3, iclass 34, count 0 2006.196.08:06:29.29#ibcon#about to read 4, iclass 34, count 0 2006.196.08:06:29.29#ibcon#read 4, iclass 34, count 0 2006.196.08:06:29.29#ibcon#about to read 5, iclass 34, count 0 2006.196.08:06:29.29#ibcon#read 5, iclass 34, count 0 2006.196.08:06:29.29#ibcon#about to read 6, iclass 34, count 0 2006.196.08:06:29.29#ibcon#read 6, iclass 34, count 0 2006.196.08:06:29.29#ibcon#end of sib2, iclass 34, count 0 2006.196.08:06:29.29#ibcon#*mode == 0, iclass 34, count 0 2006.196.08:06:29.29#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.196.08:06:29.29#ibcon#[26=FRQ=05,652.99\r\n] 2006.196.08:06:29.29#ibcon#*before write, iclass 34, count 0 2006.196.08:06:29.29#ibcon#enter sib2, iclass 34, count 0 2006.196.08:06:29.29#ibcon#flushed, iclass 34, count 0 2006.196.08:06:29.29#ibcon#about to write, iclass 34, count 0 2006.196.08:06:29.29#ibcon#wrote, iclass 34, count 0 2006.196.08:06:29.29#ibcon#about to read 3, iclass 34, count 0 2006.196.08:06:29.33#ibcon#read 3, iclass 34, count 0 2006.196.08:06:29.33#ibcon#about to read 4, iclass 34, count 0 2006.196.08:06:29.33#ibcon#read 4, iclass 34, count 0 2006.196.08:06:29.33#ibcon#about to read 5, iclass 34, count 0 2006.196.08:06:29.33#ibcon#read 5, iclass 34, count 0 2006.196.08:06:29.33#ibcon#about to read 6, iclass 34, count 0 2006.196.08:06:29.33#ibcon#read 6, iclass 34, count 0 2006.196.08:06:29.33#ibcon#end of sib2, iclass 34, count 0 2006.196.08:06:29.33#ibcon#*after write, iclass 34, count 0 2006.196.08:06:29.33#ibcon#*before return 0, iclass 34, count 0 2006.196.08:06:29.33#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.196.08:06:29.33#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.196.08:06:29.33#ibcon#about to clear, iclass 34 cls_cnt 0 2006.196.08:06:29.33#ibcon#cleared, iclass 34 cls_cnt 0 2006.196.08:06:29.33$vc4f8/va=5,7 2006.196.08:06:29.33#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.196.08:06:29.33#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.196.08:06:29.33#ibcon#ireg 11 cls_cnt 2 2006.196.08:06:29.33#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.196.08:06:29.39#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.196.08:06:29.39#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.196.08:06:29.39#ibcon#enter wrdev, iclass 36, count 2 2006.196.08:06:29.39#ibcon#first serial, iclass 36, count 2 2006.196.08:06:29.39#ibcon#enter sib2, iclass 36, count 2 2006.196.08:06:29.39#ibcon#flushed, iclass 36, count 2 2006.196.08:06:29.39#ibcon#about to write, iclass 36, count 2 2006.196.08:06:29.39#ibcon#wrote, iclass 36, count 2 2006.196.08:06:29.39#ibcon#about to read 3, iclass 36, count 2 2006.196.08:06:29.41#ibcon#read 3, iclass 36, count 2 2006.196.08:06:29.41#ibcon#about to read 4, iclass 36, count 2 2006.196.08:06:29.41#ibcon#read 4, iclass 36, count 2 2006.196.08:06:29.41#ibcon#about to read 5, iclass 36, count 2 2006.196.08:06:29.41#ibcon#read 5, iclass 36, count 2 2006.196.08:06:29.41#ibcon#about to read 6, iclass 36, count 2 2006.196.08:06:29.41#ibcon#read 6, iclass 36, count 2 2006.196.08:06:29.41#ibcon#end of sib2, iclass 36, count 2 2006.196.08:06:29.41#ibcon#*mode == 0, iclass 36, count 2 2006.196.08:06:29.41#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.196.08:06:29.41#ibcon#[25=AT05-07\r\n] 2006.196.08:06:29.41#ibcon#*before write, iclass 36, count 2 2006.196.08:06:29.41#ibcon#enter sib2, iclass 36, count 2 2006.196.08:06:29.41#ibcon#flushed, iclass 36, count 2 2006.196.08:06:29.41#ibcon#about to write, iclass 36, count 2 2006.196.08:06:29.41#ibcon#wrote, iclass 36, count 2 2006.196.08:06:29.41#ibcon#about to read 3, iclass 36, count 2 2006.196.08:06:29.44#ibcon#read 3, iclass 36, count 2 2006.196.08:06:29.44#ibcon#about to read 4, iclass 36, count 2 2006.196.08:06:29.44#ibcon#read 4, iclass 36, count 2 2006.196.08:06:29.44#ibcon#about to read 5, iclass 36, count 2 2006.196.08:06:29.44#ibcon#read 5, iclass 36, count 2 2006.196.08:06:29.44#ibcon#about to read 6, iclass 36, count 2 2006.196.08:06:29.44#ibcon#read 6, iclass 36, count 2 2006.196.08:06:29.44#ibcon#end of sib2, iclass 36, count 2 2006.196.08:06:29.44#ibcon#*after write, iclass 36, count 2 2006.196.08:06:29.44#ibcon#*before return 0, iclass 36, count 2 2006.196.08:06:29.44#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.196.08:06:29.44#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.196.08:06:29.44#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.196.08:06:29.44#ibcon#ireg 7 cls_cnt 0 2006.196.08:06:29.44#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.196.08:06:29.56#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.196.08:06:29.56#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.196.08:06:29.56#ibcon#enter wrdev, iclass 36, count 0 2006.196.08:06:29.56#ibcon#first serial, iclass 36, count 0 2006.196.08:06:29.56#ibcon#enter sib2, iclass 36, count 0 2006.196.08:06:29.56#ibcon#flushed, iclass 36, count 0 2006.196.08:06:29.56#ibcon#about to write, iclass 36, count 0 2006.196.08:06:29.56#ibcon#wrote, iclass 36, count 0 2006.196.08:06:29.56#ibcon#about to read 3, iclass 36, count 0 2006.196.08:06:29.58#ibcon#read 3, iclass 36, count 0 2006.196.08:06:29.58#ibcon#about to read 4, iclass 36, count 0 2006.196.08:06:29.58#ibcon#read 4, iclass 36, count 0 2006.196.08:06:29.58#ibcon#about to read 5, iclass 36, count 0 2006.196.08:06:29.58#ibcon#read 5, iclass 36, count 0 2006.196.08:06:29.58#ibcon#about to read 6, iclass 36, count 0 2006.196.08:06:29.58#ibcon#read 6, iclass 36, count 0 2006.196.08:06:29.58#ibcon#end of sib2, iclass 36, count 0 2006.196.08:06:29.58#ibcon#*mode == 0, iclass 36, count 0 2006.196.08:06:29.58#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.196.08:06:29.58#ibcon#[25=USB\r\n] 2006.196.08:06:29.58#ibcon#*before write, iclass 36, count 0 2006.196.08:06:29.58#ibcon#enter sib2, iclass 36, count 0 2006.196.08:06:29.58#ibcon#flushed, iclass 36, count 0 2006.196.08:06:29.58#ibcon#about to write, iclass 36, count 0 2006.196.08:06:29.58#ibcon#wrote, iclass 36, count 0 2006.196.08:06:29.58#ibcon#about to read 3, iclass 36, count 0 2006.196.08:06:29.61#ibcon#read 3, iclass 36, count 0 2006.196.08:06:29.61#ibcon#about to read 4, iclass 36, count 0 2006.196.08:06:29.61#ibcon#read 4, iclass 36, count 0 2006.196.08:06:29.61#ibcon#about to read 5, iclass 36, count 0 2006.196.08:06:29.61#ibcon#read 5, iclass 36, count 0 2006.196.08:06:29.61#ibcon#about to read 6, iclass 36, count 0 2006.196.08:06:29.61#ibcon#read 6, iclass 36, count 0 2006.196.08:06:29.61#ibcon#end of sib2, iclass 36, count 0 2006.196.08:06:29.61#ibcon#*after write, iclass 36, count 0 2006.196.08:06:29.61#ibcon#*before return 0, iclass 36, count 0 2006.196.08:06:29.61#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.196.08:06:29.61#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.196.08:06:29.61#ibcon#about to clear, iclass 36 cls_cnt 0 2006.196.08:06:29.61#ibcon#cleared, iclass 36 cls_cnt 0 2006.196.08:06:29.61$vc4f8/valo=6,772.99 2006.196.08:06:29.61#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.196.08:06:29.61#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.196.08:06:29.61#ibcon#ireg 17 cls_cnt 0 2006.196.08:06:29.61#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.196.08:06:29.61#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.196.08:06:29.61#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.196.08:06:29.61#ibcon#enter wrdev, iclass 38, count 0 2006.196.08:06:29.61#ibcon#first serial, iclass 38, count 0 2006.196.08:06:29.61#ibcon#enter sib2, iclass 38, count 0 2006.196.08:06:29.61#ibcon#flushed, iclass 38, count 0 2006.196.08:06:29.61#ibcon#about to write, iclass 38, count 0 2006.196.08:06:29.61#ibcon#wrote, iclass 38, count 0 2006.196.08:06:29.61#ibcon#about to read 3, iclass 38, count 0 2006.196.08:06:29.63#ibcon#read 3, iclass 38, count 0 2006.196.08:06:29.63#ibcon#about to read 4, iclass 38, count 0 2006.196.08:06:29.63#ibcon#read 4, iclass 38, count 0 2006.196.08:06:29.63#ibcon#about to read 5, iclass 38, count 0 2006.196.08:06:29.63#ibcon#read 5, iclass 38, count 0 2006.196.08:06:29.63#ibcon#about to read 6, iclass 38, count 0 2006.196.08:06:29.63#ibcon#read 6, iclass 38, count 0 2006.196.08:06:29.63#ibcon#end of sib2, iclass 38, count 0 2006.196.08:06:29.63#ibcon#*mode == 0, iclass 38, count 0 2006.196.08:06:29.63#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.196.08:06:29.63#ibcon#[26=FRQ=06,772.99\r\n] 2006.196.08:06:29.63#ibcon#*before write, iclass 38, count 0 2006.196.08:06:29.63#ibcon#enter sib2, iclass 38, count 0 2006.196.08:06:29.63#ibcon#flushed, iclass 38, count 0 2006.196.08:06:29.63#ibcon#about to write, iclass 38, count 0 2006.196.08:06:29.63#ibcon#wrote, iclass 38, count 0 2006.196.08:06:29.63#ibcon#about to read 3, iclass 38, count 0 2006.196.08:06:29.68#ibcon#read 3, iclass 38, count 0 2006.196.08:06:29.68#ibcon#about to read 4, iclass 38, count 0 2006.196.08:06:29.68#ibcon#read 4, iclass 38, count 0 2006.196.08:06:29.68#ibcon#about to read 5, iclass 38, count 0 2006.196.08:06:29.68#ibcon#read 5, iclass 38, count 0 2006.196.08:06:29.68#ibcon#about to read 6, iclass 38, count 0 2006.196.08:06:29.68#ibcon#read 6, iclass 38, count 0 2006.196.08:06:29.68#ibcon#end of sib2, iclass 38, count 0 2006.196.08:06:29.68#ibcon#*after write, iclass 38, count 0 2006.196.08:06:29.68#ibcon#*before return 0, iclass 38, count 0 2006.196.08:06:29.68#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.196.08:06:29.68#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.196.08:06:29.68#ibcon#about to clear, iclass 38 cls_cnt 0 2006.196.08:06:29.68#ibcon#cleared, iclass 38 cls_cnt 0 2006.196.08:06:29.68$vc4f8/va=6,6 2006.196.08:06:29.68#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.196.08:06:29.68#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.196.08:06:29.68#ibcon#ireg 11 cls_cnt 2 2006.196.08:06:29.68#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.196.08:06:29.73#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.196.08:06:29.73#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.196.08:06:29.73#ibcon#enter wrdev, iclass 40, count 2 2006.196.08:06:29.73#ibcon#first serial, iclass 40, count 2 2006.196.08:06:29.73#ibcon#enter sib2, iclass 40, count 2 2006.196.08:06:29.73#ibcon#flushed, iclass 40, count 2 2006.196.08:06:29.73#ibcon#about to write, iclass 40, count 2 2006.196.08:06:29.73#ibcon#wrote, iclass 40, count 2 2006.196.08:06:29.73#ibcon#about to read 3, iclass 40, count 2 2006.196.08:06:29.75#ibcon#read 3, iclass 40, count 2 2006.196.08:06:29.75#ibcon#about to read 4, iclass 40, count 2 2006.196.08:06:29.75#ibcon#read 4, iclass 40, count 2 2006.196.08:06:29.75#ibcon#about to read 5, iclass 40, count 2 2006.196.08:06:29.75#ibcon#read 5, iclass 40, count 2 2006.196.08:06:29.75#ibcon#about to read 6, iclass 40, count 2 2006.196.08:06:29.75#ibcon#read 6, iclass 40, count 2 2006.196.08:06:29.75#ibcon#end of sib2, iclass 40, count 2 2006.196.08:06:29.75#ibcon#*mode == 0, iclass 40, count 2 2006.196.08:06:29.75#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.196.08:06:29.75#ibcon#[25=AT06-06\r\n] 2006.196.08:06:29.75#ibcon#*before write, iclass 40, count 2 2006.196.08:06:29.75#ibcon#enter sib2, iclass 40, count 2 2006.196.08:06:29.75#ibcon#flushed, iclass 40, count 2 2006.196.08:06:29.75#ibcon#about to write, iclass 40, count 2 2006.196.08:06:29.75#ibcon#wrote, iclass 40, count 2 2006.196.08:06:29.75#ibcon#about to read 3, iclass 40, count 2 2006.196.08:06:29.78#ibcon#read 3, iclass 40, count 2 2006.196.08:06:29.78#ibcon#about to read 4, iclass 40, count 2 2006.196.08:06:29.78#ibcon#read 4, iclass 40, count 2 2006.196.08:06:29.78#ibcon#about to read 5, iclass 40, count 2 2006.196.08:06:29.78#ibcon#read 5, iclass 40, count 2 2006.196.08:06:29.78#ibcon#about to read 6, iclass 40, count 2 2006.196.08:06:29.78#ibcon#read 6, iclass 40, count 2 2006.196.08:06:29.78#ibcon#end of sib2, iclass 40, count 2 2006.196.08:06:29.78#ibcon#*after write, iclass 40, count 2 2006.196.08:06:29.78#ibcon#*before return 0, iclass 40, count 2 2006.196.08:06:29.78#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.196.08:06:29.78#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.196.08:06:29.78#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.196.08:06:29.78#ibcon#ireg 7 cls_cnt 0 2006.196.08:06:29.78#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.196.08:06:29.90#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.196.08:06:29.90#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.196.08:06:29.90#ibcon#enter wrdev, iclass 40, count 0 2006.196.08:06:29.90#ibcon#first serial, iclass 40, count 0 2006.196.08:06:29.90#ibcon#enter sib2, iclass 40, count 0 2006.196.08:06:29.90#ibcon#flushed, iclass 40, count 0 2006.196.08:06:29.90#ibcon#about to write, iclass 40, count 0 2006.196.08:06:29.90#ibcon#wrote, iclass 40, count 0 2006.196.08:06:29.90#ibcon#about to read 3, iclass 40, count 0 2006.196.08:06:29.92#ibcon#read 3, iclass 40, count 0 2006.196.08:06:29.92#ibcon#about to read 4, iclass 40, count 0 2006.196.08:06:29.92#ibcon#read 4, iclass 40, count 0 2006.196.08:06:29.92#ibcon#about to read 5, iclass 40, count 0 2006.196.08:06:29.92#ibcon#read 5, iclass 40, count 0 2006.196.08:06:29.92#ibcon#about to read 6, iclass 40, count 0 2006.196.08:06:29.92#ibcon#read 6, iclass 40, count 0 2006.196.08:06:29.92#ibcon#end of sib2, iclass 40, count 0 2006.196.08:06:29.92#ibcon#*mode == 0, iclass 40, count 0 2006.196.08:06:29.92#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.196.08:06:29.92#ibcon#[25=USB\r\n] 2006.196.08:06:29.92#ibcon#*before write, iclass 40, count 0 2006.196.08:06:29.92#ibcon#enter sib2, iclass 40, count 0 2006.196.08:06:29.92#ibcon#flushed, iclass 40, count 0 2006.196.08:06:29.92#ibcon#about to write, iclass 40, count 0 2006.196.08:06:29.92#ibcon#wrote, iclass 40, count 0 2006.196.08:06:29.92#ibcon#about to read 3, iclass 40, count 0 2006.196.08:06:29.95#ibcon#read 3, iclass 40, count 0 2006.196.08:06:29.95#ibcon#about to read 4, iclass 40, count 0 2006.196.08:06:29.95#ibcon#read 4, iclass 40, count 0 2006.196.08:06:29.95#ibcon#about to read 5, iclass 40, count 0 2006.196.08:06:29.95#ibcon#read 5, iclass 40, count 0 2006.196.08:06:29.95#ibcon#about to read 6, iclass 40, count 0 2006.196.08:06:29.95#ibcon#read 6, iclass 40, count 0 2006.196.08:06:29.95#ibcon#end of sib2, iclass 40, count 0 2006.196.08:06:29.95#ibcon#*after write, iclass 40, count 0 2006.196.08:06:29.95#ibcon#*before return 0, iclass 40, count 0 2006.196.08:06:29.95#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.196.08:06:29.95#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.196.08:06:29.95#ibcon#about to clear, iclass 40 cls_cnt 0 2006.196.08:06:29.95#ibcon#cleared, iclass 40 cls_cnt 0 2006.196.08:06:29.95$vc4f8/valo=7,832.99 2006.196.08:06:29.95#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.196.08:06:29.95#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.196.08:06:29.95#ibcon#ireg 17 cls_cnt 0 2006.196.08:06:29.95#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.196.08:06:29.95#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.196.08:06:29.95#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.196.08:06:29.95#ibcon#enter wrdev, iclass 4, count 0 2006.196.08:06:29.95#ibcon#first serial, iclass 4, count 0 2006.196.08:06:29.95#ibcon#enter sib2, iclass 4, count 0 2006.196.08:06:29.95#ibcon#flushed, iclass 4, count 0 2006.196.08:06:29.95#ibcon#about to write, iclass 4, count 0 2006.196.08:06:29.95#ibcon#wrote, iclass 4, count 0 2006.196.08:06:29.95#ibcon#about to read 3, iclass 4, count 0 2006.196.08:06:29.97#ibcon#read 3, iclass 4, count 0 2006.196.08:06:29.97#ibcon#about to read 4, iclass 4, count 0 2006.196.08:06:29.97#ibcon#read 4, iclass 4, count 0 2006.196.08:06:29.97#ibcon#about to read 5, iclass 4, count 0 2006.196.08:06:29.97#ibcon#read 5, iclass 4, count 0 2006.196.08:06:29.97#ibcon#about to read 6, iclass 4, count 0 2006.196.08:06:29.97#ibcon#read 6, iclass 4, count 0 2006.196.08:06:29.97#ibcon#end of sib2, iclass 4, count 0 2006.196.08:06:29.97#ibcon#*mode == 0, iclass 4, count 0 2006.196.08:06:29.97#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.196.08:06:29.97#ibcon#[26=FRQ=07,832.99\r\n] 2006.196.08:06:29.97#ibcon#*before write, iclass 4, count 0 2006.196.08:06:29.97#ibcon#enter sib2, iclass 4, count 0 2006.196.08:06:29.97#ibcon#flushed, iclass 4, count 0 2006.196.08:06:29.97#ibcon#about to write, iclass 4, count 0 2006.196.08:06:29.97#ibcon#wrote, iclass 4, count 0 2006.196.08:06:29.97#ibcon#about to read 3, iclass 4, count 0 2006.196.08:06:30.01#ibcon#read 3, iclass 4, count 0 2006.196.08:06:30.01#ibcon#about to read 4, iclass 4, count 0 2006.196.08:06:30.01#ibcon#read 4, iclass 4, count 0 2006.196.08:06:30.01#ibcon#about to read 5, iclass 4, count 0 2006.196.08:06:30.01#ibcon#read 5, iclass 4, count 0 2006.196.08:06:30.01#ibcon#about to read 6, iclass 4, count 0 2006.196.08:06:30.01#ibcon#read 6, iclass 4, count 0 2006.196.08:06:30.01#ibcon#end of sib2, iclass 4, count 0 2006.196.08:06:30.01#ibcon#*after write, iclass 4, count 0 2006.196.08:06:30.01#ibcon#*before return 0, iclass 4, count 0 2006.196.08:06:30.01#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.196.08:06:30.01#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.196.08:06:30.01#ibcon#about to clear, iclass 4 cls_cnt 0 2006.196.08:06:30.01#ibcon#cleared, iclass 4 cls_cnt 0 2006.196.08:06:30.01$vc4f8/va=7,6 2006.196.08:06:30.01#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.196.08:06:30.01#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.196.08:06:30.01#ibcon#ireg 11 cls_cnt 2 2006.196.08:06:30.01#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.196.08:06:30.07#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.196.08:06:30.07#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.196.08:06:30.07#ibcon#enter wrdev, iclass 6, count 2 2006.196.08:06:30.07#ibcon#first serial, iclass 6, count 2 2006.196.08:06:30.07#ibcon#enter sib2, iclass 6, count 2 2006.196.08:06:30.07#ibcon#flushed, iclass 6, count 2 2006.196.08:06:30.07#ibcon#about to write, iclass 6, count 2 2006.196.08:06:30.07#ibcon#wrote, iclass 6, count 2 2006.196.08:06:30.07#ibcon#about to read 3, iclass 6, count 2 2006.196.08:06:30.09#ibcon#read 3, iclass 6, count 2 2006.196.08:06:30.09#ibcon#about to read 4, iclass 6, count 2 2006.196.08:06:30.09#ibcon#read 4, iclass 6, count 2 2006.196.08:06:30.09#ibcon#about to read 5, iclass 6, count 2 2006.196.08:06:30.09#ibcon#read 5, iclass 6, count 2 2006.196.08:06:30.09#ibcon#about to read 6, iclass 6, count 2 2006.196.08:06:30.09#ibcon#read 6, iclass 6, count 2 2006.196.08:06:30.09#ibcon#end of sib2, iclass 6, count 2 2006.196.08:06:30.09#ibcon#*mode == 0, iclass 6, count 2 2006.196.08:06:30.09#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.196.08:06:30.09#ibcon#[25=AT07-06\r\n] 2006.196.08:06:30.09#ibcon#*before write, iclass 6, count 2 2006.196.08:06:30.09#ibcon#enter sib2, iclass 6, count 2 2006.196.08:06:30.09#ibcon#flushed, iclass 6, count 2 2006.196.08:06:30.09#ibcon#about to write, iclass 6, count 2 2006.196.08:06:30.09#ibcon#wrote, iclass 6, count 2 2006.196.08:06:30.09#ibcon#about to read 3, iclass 6, count 2 2006.196.08:06:30.12#ibcon#read 3, iclass 6, count 2 2006.196.08:06:30.12#ibcon#about to read 4, iclass 6, count 2 2006.196.08:06:30.12#ibcon#read 4, iclass 6, count 2 2006.196.08:06:30.12#ibcon#about to read 5, iclass 6, count 2 2006.196.08:06:30.12#ibcon#read 5, iclass 6, count 2 2006.196.08:06:30.12#ibcon#about to read 6, iclass 6, count 2 2006.196.08:06:30.12#ibcon#read 6, iclass 6, count 2 2006.196.08:06:30.12#ibcon#end of sib2, iclass 6, count 2 2006.196.08:06:30.12#ibcon#*after write, iclass 6, count 2 2006.196.08:06:30.12#ibcon#*before return 0, iclass 6, count 2 2006.196.08:06:30.12#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.196.08:06:30.12#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.196.08:06:30.12#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.196.08:06:30.12#ibcon#ireg 7 cls_cnt 0 2006.196.08:06:30.12#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.196.08:06:30.24#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.196.08:06:30.24#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.196.08:06:30.24#ibcon#enter wrdev, iclass 6, count 0 2006.196.08:06:30.24#ibcon#first serial, iclass 6, count 0 2006.196.08:06:30.24#ibcon#enter sib2, iclass 6, count 0 2006.196.08:06:30.24#ibcon#flushed, iclass 6, count 0 2006.196.08:06:30.24#ibcon#about to write, iclass 6, count 0 2006.196.08:06:30.24#ibcon#wrote, iclass 6, count 0 2006.196.08:06:30.24#ibcon#about to read 3, iclass 6, count 0 2006.196.08:06:30.26#ibcon#read 3, iclass 6, count 0 2006.196.08:06:30.26#ibcon#about to read 4, iclass 6, count 0 2006.196.08:06:30.26#ibcon#read 4, iclass 6, count 0 2006.196.08:06:30.26#ibcon#about to read 5, iclass 6, count 0 2006.196.08:06:30.26#ibcon#read 5, iclass 6, count 0 2006.196.08:06:30.26#ibcon#about to read 6, iclass 6, count 0 2006.196.08:06:30.26#ibcon#read 6, iclass 6, count 0 2006.196.08:06:30.26#ibcon#end of sib2, iclass 6, count 0 2006.196.08:06:30.26#ibcon#*mode == 0, iclass 6, count 0 2006.196.08:06:30.26#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.196.08:06:30.26#ibcon#[25=USB\r\n] 2006.196.08:06:30.26#ibcon#*before write, iclass 6, count 0 2006.196.08:06:30.26#ibcon#enter sib2, iclass 6, count 0 2006.196.08:06:30.26#ibcon#flushed, iclass 6, count 0 2006.196.08:06:30.26#ibcon#about to write, iclass 6, count 0 2006.196.08:06:30.26#ibcon#wrote, iclass 6, count 0 2006.196.08:06:30.26#ibcon#about to read 3, iclass 6, count 0 2006.196.08:06:30.29#ibcon#read 3, iclass 6, count 0 2006.196.08:06:30.29#ibcon#about to read 4, iclass 6, count 0 2006.196.08:06:30.29#ibcon#read 4, iclass 6, count 0 2006.196.08:06:30.29#ibcon#about to read 5, iclass 6, count 0 2006.196.08:06:30.29#ibcon#read 5, iclass 6, count 0 2006.196.08:06:30.29#ibcon#about to read 6, iclass 6, count 0 2006.196.08:06:30.29#ibcon#read 6, iclass 6, count 0 2006.196.08:06:30.29#ibcon#end of sib2, iclass 6, count 0 2006.196.08:06:30.29#ibcon#*after write, iclass 6, count 0 2006.196.08:06:30.29#ibcon#*before return 0, iclass 6, count 0 2006.196.08:06:30.29#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.196.08:06:30.29#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.196.08:06:30.29#ibcon#about to clear, iclass 6 cls_cnt 0 2006.196.08:06:30.29#ibcon#cleared, iclass 6 cls_cnt 0 2006.196.08:06:30.29$vc4f8/valo=8,852.99 2006.196.08:06:30.29#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.196.08:06:30.29#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.196.08:06:30.29#ibcon#ireg 17 cls_cnt 0 2006.196.08:06:30.29#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.196.08:06:30.29#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.196.08:06:30.29#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.196.08:06:30.29#ibcon#enter wrdev, iclass 10, count 0 2006.196.08:06:30.29#ibcon#first serial, iclass 10, count 0 2006.196.08:06:30.29#ibcon#enter sib2, iclass 10, count 0 2006.196.08:06:30.29#ibcon#flushed, iclass 10, count 0 2006.196.08:06:30.29#ibcon#about to write, iclass 10, count 0 2006.196.08:06:30.29#ibcon#wrote, iclass 10, count 0 2006.196.08:06:30.29#ibcon#about to read 3, iclass 10, count 0 2006.196.08:06:30.31#ibcon#read 3, iclass 10, count 0 2006.196.08:06:30.31#ibcon#about to read 4, iclass 10, count 0 2006.196.08:06:30.31#ibcon#read 4, iclass 10, count 0 2006.196.08:06:30.31#ibcon#about to read 5, iclass 10, count 0 2006.196.08:06:30.31#ibcon#read 5, iclass 10, count 0 2006.196.08:06:30.31#ibcon#about to read 6, iclass 10, count 0 2006.196.08:06:30.31#ibcon#read 6, iclass 10, count 0 2006.196.08:06:30.31#ibcon#end of sib2, iclass 10, count 0 2006.196.08:06:30.31#ibcon#*mode == 0, iclass 10, count 0 2006.196.08:06:30.31#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.196.08:06:30.31#ibcon#[26=FRQ=08,852.99\r\n] 2006.196.08:06:30.31#ibcon#*before write, iclass 10, count 0 2006.196.08:06:30.31#ibcon#enter sib2, iclass 10, count 0 2006.196.08:06:30.31#ibcon#flushed, iclass 10, count 0 2006.196.08:06:30.31#ibcon#about to write, iclass 10, count 0 2006.196.08:06:30.31#ibcon#wrote, iclass 10, count 0 2006.196.08:06:30.31#ibcon#about to read 3, iclass 10, count 0 2006.196.08:06:30.36#ibcon#read 3, iclass 10, count 0 2006.196.08:06:30.36#ibcon#about to read 4, iclass 10, count 0 2006.196.08:06:30.36#ibcon#read 4, iclass 10, count 0 2006.196.08:06:30.36#ibcon#about to read 5, iclass 10, count 0 2006.196.08:06:30.36#ibcon#read 5, iclass 10, count 0 2006.196.08:06:30.36#ibcon#about to read 6, iclass 10, count 0 2006.196.08:06:30.36#ibcon#read 6, iclass 10, count 0 2006.196.08:06:30.36#ibcon#end of sib2, iclass 10, count 0 2006.196.08:06:30.36#ibcon#*after write, iclass 10, count 0 2006.196.08:06:30.36#ibcon#*before return 0, iclass 10, count 0 2006.196.08:06:30.36#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.196.08:06:30.36#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.196.08:06:30.36#ibcon#about to clear, iclass 10 cls_cnt 0 2006.196.08:06:30.36#ibcon#cleared, iclass 10 cls_cnt 0 2006.196.08:06:30.36$vc4f8/va=8,7 2006.196.08:06:30.36#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.196.08:06:30.36#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.196.08:06:30.36#ibcon#ireg 11 cls_cnt 2 2006.196.08:06:30.36#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.196.08:06:30.41#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.196.08:06:30.41#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.196.08:06:30.41#ibcon#enter wrdev, iclass 12, count 2 2006.196.08:06:30.41#ibcon#first serial, iclass 12, count 2 2006.196.08:06:30.41#ibcon#enter sib2, iclass 12, count 2 2006.196.08:06:30.41#ibcon#flushed, iclass 12, count 2 2006.196.08:06:30.41#ibcon#about to write, iclass 12, count 2 2006.196.08:06:30.41#ibcon#wrote, iclass 12, count 2 2006.196.08:06:30.41#ibcon#about to read 3, iclass 12, count 2 2006.196.08:06:30.43#ibcon#read 3, iclass 12, count 2 2006.196.08:06:30.43#ibcon#about to read 4, iclass 12, count 2 2006.196.08:06:30.43#ibcon#read 4, iclass 12, count 2 2006.196.08:06:30.43#ibcon#about to read 5, iclass 12, count 2 2006.196.08:06:30.43#ibcon#read 5, iclass 12, count 2 2006.196.08:06:30.43#ibcon#about to read 6, iclass 12, count 2 2006.196.08:06:30.43#ibcon#read 6, iclass 12, count 2 2006.196.08:06:30.43#ibcon#end of sib2, iclass 12, count 2 2006.196.08:06:30.43#ibcon#*mode == 0, iclass 12, count 2 2006.196.08:06:30.43#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.196.08:06:30.43#ibcon#[25=AT08-07\r\n] 2006.196.08:06:30.43#ibcon#*before write, iclass 12, count 2 2006.196.08:06:30.43#ibcon#enter sib2, iclass 12, count 2 2006.196.08:06:30.43#ibcon#flushed, iclass 12, count 2 2006.196.08:06:30.43#ibcon#about to write, iclass 12, count 2 2006.196.08:06:30.43#ibcon#wrote, iclass 12, count 2 2006.196.08:06:30.43#ibcon#about to read 3, iclass 12, count 2 2006.196.08:06:30.46#ibcon#read 3, iclass 12, count 2 2006.196.08:06:30.46#ibcon#about to read 4, iclass 12, count 2 2006.196.08:06:30.46#ibcon#read 4, iclass 12, count 2 2006.196.08:06:30.46#ibcon#about to read 5, iclass 12, count 2 2006.196.08:06:30.46#ibcon#read 5, iclass 12, count 2 2006.196.08:06:30.46#ibcon#about to read 6, iclass 12, count 2 2006.196.08:06:30.46#ibcon#read 6, iclass 12, count 2 2006.196.08:06:30.46#ibcon#end of sib2, iclass 12, count 2 2006.196.08:06:30.46#ibcon#*after write, iclass 12, count 2 2006.196.08:06:30.46#ibcon#*before return 0, iclass 12, count 2 2006.196.08:06:30.46#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.196.08:06:30.46#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.196.08:06:30.46#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.196.08:06:30.46#ibcon#ireg 7 cls_cnt 0 2006.196.08:06:30.46#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.196.08:06:30.58#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.196.08:06:30.58#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.196.08:06:30.58#ibcon#enter wrdev, iclass 12, count 0 2006.196.08:06:30.58#ibcon#first serial, iclass 12, count 0 2006.196.08:06:30.58#ibcon#enter sib2, iclass 12, count 0 2006.196.08:06:30.58#ibcon#flushed, iclass 12, count 0 2006.196.08:06:30.58#ibcon#about to write, iclass 12, count 0 2006.196.08:06:30.58#ibcon#wrote, iclass 12, count 0 2006.196.08:06:30.58#ibcon#about to read 3, iclass 12, count 0 2006.196.08:06:30.60#ibcon#read 3, iclass 12, count 0 2006.196.08:06:30.60#ibcon#about to read 4, iclass 12, count 0 2006.196.08:06:30.60#ibcon#read 4, iclass 12, count 0 2006.196.08:06:30.60#ibcon#about to read 5, iclass 12, count 0 2006.196.08:06:30.60#ibcon#read 5, iclass 12, count 0 2006.196.08:06:30.60#ibcon#about to read 6, iclass 12, count 0 2006.196.08:06:30.60#ibcon#read 6, iclass 12, count 0 2006.196.08:06:30.60#ibcon#end of sib2, iclass 12, count 0 2006.196.08:06:30.60#ibcon#*mode == 0, iclass 12, count 0 2006.196.08:06:30.60#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.196.08:06:30.60#ibcon#[25=USB\r\n] 2006.196.08:06:30.60#ibcon#*before write, iclass 12, count 0 2006.196.08:06:30.60#ibcon#enter sib2, iclass 12, count 0 2006.196.08:06:30.60#ibcon#flushed, iclass 12, count 0 2006.196.08:06:30.60#ibcon#about to write, iclass 12, count 0 2006.196.08:06:30.60#ibcon#wrote, iclass 12, count 0 2006.196.08:06:30.60#ibcon#about to read 3, iclass 12, count 0 2006.196.08:06:30.63#ibcon#read 3, iclass 12, count 0 2006.196.08:06:30.63#ibcon#about to read 4, iclass 12, count 0 2006.196.08:06:30.63#ibcon#read 4, iclass 12, count 0 2006.196.08:06:30.63#ibcon#about to read 5, iclass 12, count 0 2006.196.08:06:30.63#ibcon#read 5, iclass 12, count 0 2006.196.08:06:30.63#ibcon#about to read 6, iclass 12, count 0 2006.196.08:06:30.63#ibcon#read 6, iclass 12, count 0 2006.196.08:06:30.63#ibcon#end of sib2, iclass 12, count 0 2006.196.08:06:30.63#ibcon#*after write, iclass 12, count 0 2006.196.08:06:30.63#ibcon#*before return 0, iclass 12, count 0 2006.196.08:06:30.63#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.196.08:06:30.63#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.196.08:06:30.63#ibcon#about to clear, iclass 12 cls_cnt 0 2006.196.08:06:30.63#ibcon#cleared, iclass 12 cls_cnt 0 2006.196.08:06:30.63$vc4f8/vblo=1,632.99 2006.196.08:06:30.63#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.196.08:06:30.63#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.196.08:06:30.63#ibcon#ireg 17 cls_cnt 0 2006.196.08:06:30.63#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.196.08:06:30.63#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.196.08:06:30.63#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.196.08:06:30.63#ibcon#enter wrdev, iclass 14, count 0 2006.196.08:06:30.63#ibcon#first serial, iclass 14, count 0 2006.196.08:06:30.63#ibcon#enter sib2, iclass 14, count 0 2006.196.08:06:30.63#ibcon#flushed, iclass 14, count 0 2006.196.08:06:30.63#ibcon#about to write, iclass 14, count 0 2006.196.08:06:30.63#ibcon#wrote, iclass 14, count 0 2006.196.08:06:30.63#ibcon#about to read 3, iclass 14, count 0 2006.196.08:06:30.65#ibcon#read 3, iclass 14, count 0 2006.196.08:06:30.65#ibcon#about to read 4, iclass 14, count 0 2006.196.08:06:30.65#ibcon#read 4, iclass 14, count 0 2006.196.08:06:30.65#ibcon#about to read 5, iclass 14, count 0 2006.196.08:06:30.65#ibcon#read 5, iclass 14, count 0 2006.196.08:06:30.65#ibcon#about to read 6, iclass 14, count 0 2006.196.08:06:30.65#ibcon#read 6, iclass 14, count 0 2006.196.08:06:30.65#ibcon#end of sib2, iclass 14, count 0 2006.196.08:06:30.65#ibcon#*mode == 0, iclass 14, count 0 2006.196.08:06:30.65#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.196.08:06:30.65#ibcon#[28=FRQ=01,632.99\r\n] 2006.196.08:06:30.65#ibcon#*before write, iclass 14, count 0 2006.196.08:06:30.65#ibcon#enter sib2, iclass 14, count 0 2006.196.08:06:30.65#ibcon#flushed, iclass 14, count 0 2006.196.08:06:30.65#ibcon#about to write, iclass 14, count 0 2006.196.08:06:30.65#ibcon#wrote, iclass 14, count 0 2006.196.08:06:30.65#ibcon#about to read 3, iclass 14, count 0 2006.196.08:06:30.69#ibcon#read 3, iclass 14, count 0 2006.196.08:06:30.69#ibcon#about to read 4, iclass 14, count 0 2006.196.08:06:30.69#ibcon#read 4, iclass 14, count 0 2006.196.08:06:30.69#ibcon#about to read 5, iclass 14, count 0 2006.196.08:06:30.69#ibcon#read 5, iclass 14, count 0 2006.196.08:06:30.69#ibcon#about to read 6, iclass 14, count 0 2006.196.08:06:30.69#ibcon#read 6, iclass 14, count 0 2006.196.08:06:30.69#ibcon#end of sib2, iclass 14, count 0 2006.196.08:06:30.69#ibcon#*after write, iclass 14, count 0 2006.196.08:06:30.69#ibcon#*before return 0, iclass 14, count 0 2006.196.08:06:30.69#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.196.08:06:30.69#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.196.08:06:30.69#ibcon#about to clear, iclass 14 cls_cnt 0 2006.196.08:06:30.69#ibcon#cleared, iclass 14 cls_cnt 0 2006.196.08:06:30.69$vc4f8/vb=1,4 2006.196.08:06:30.69#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.196.08:06:30.69#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.196.08:06:30.69#ibcon#ireg 11 cls_cnt 2 2006.196.08:06:30.69#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.196.08:06:30.69#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.196.08:06:30.69#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.196.08:06:30.69#ibcon#enter wrdev, iclass 16, count 2 2006.196.08:06:30.69#ibcon#first serial, iclass 16, count 2 2006.196.08:06:30.69#ibcon#enter sib2, iclass 16, count 2 2006.196.08:06:30.69#ibcon#flushed, iclass 16, count 2 2006.196.08:06:30.69#ibcon#about to write, iclass 16, count 2 2006.196.08:06:30.69#ibcon#wrote, iclass 16, count 2 2006.196.08:06:30.69#ibcon#about to read 3, iclass 16, count 2 2006.196.08:06:30.71#ibcon#read 3, iclass 16, count 2 2006.196.08:06:30.71#ibcon#about to read 4, iclass 16, count 2 2006.196.08:06:30.71#ibcon#read 4, iclass 16, count 2 2006.196.08:06:30.71#ibcon#about to read 5, iclass 16, count 2 2006.196.08:06:30.71#ibcon#read 5, iclass 16, count 2 2006.196.08:06:30.71#ibcon#about to read 6, iclass 16, count 2 2006.196.08:06:30.71#ibcon#read 6, iclass 16, count 2 2006.196.08:06:30.71#ibcon#end of sib2, iclass 16, count 2 2006.196.08:06:30.71#ibcon#*mode == 0, iclass 16, count 2 2006.196.08:06:30.71#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.196.08:06:30.71#ibcon#[27=AT01-04\r\n] 2006.196.08:06:30.71#ibcon#*before write, iclass 16, count 2 2006.196.08:06:30.71#ibcon#enter sib2, iclass 16, count 2 2006.196.08:06:30.71#ibcon#flushed, iclass 16, count 2 2006.196.08:06:30.71#ibcon#about to write, iclass 16, count 2 2006.196.08:06:30.71#ibcon#wrote, iclass 16, count 2 2006.196.08:06:30.71#ibcon#about to read 3, iclass 16, count 2 2006.196.08:06:30.74#ibcon#read 3, iclass 16, count 2 2006.196.08:06:30.74#ibcon#about to read 4, iclass 16, count 2 2006.196.08:06:30.74#ibcon#read 4, iclass 16, count 2 2006.196.08:06:30.74#ibcon#about to read 5, iclass 16, count 2 2006.196.08:06:30.74#ibcon#read 5, iclass 16, count 2 2006.196.08:06:30.74#ibcon#about to read 6, iclass 16, count 2 2006.196.08:06:30.74#ibcon#read 6, iclass 16, count 2 2006.196.08:06:30.74#ibcon#end of sib2, iclass 16, count 2 2006.196.08:06:30.74#ibcon#*after write, iclass 16, count 2 2006.196.08:06:30.74#ibcon#*before return 0, iclass 16, count 2 2006.196.08:06:30.74#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.196.08:06:30.74#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.196.08:06:30.74#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.196.08:06:30.74#ibcon#ireg 7 cls_cnt 0 2006.196.08:06:30.74#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.196.08:06:30.86#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.196.08:06:30.86#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.196.08:06:30.86#ibcon#enter wrdev, iclass 16, count 0 2006.196.08:06:30.86#ibcon#first serial, iclass 16, count 0 2006.196.08:06:30.86#ibcon#enter sib2, iclass 16, count 0 2006.196.08:06:30.86#ibcon#flushed, iclass 16, count 0 2006.196.08:06:30.86#ibcon#about to write, iclass 16, count 0 2006.196.08:06:30.86#ibcon#wrote, iclass 16, count 0 2006.196.08:06:30.86#ibcon#about to read 3, iclass 16, count 0 2006.196.08:06:30.88#ibcon#read 3, iclass 16, count 0 2006.196.08:06:30.88#ibcon#about to read 4, iclass 16, count 0 2006.196.08:06:30.88#ibcon#read 4, iclass 16, count 0 2006.196.08:06:30.88#ibcon#about to read 5, iclass 16, count 0 2006.196.08:06:30.88#ibcon#read 5, iclass 16, count 0 2006.196.08:06:30.88#ibcon#about to read 6, iclass 16, count 0 2006.196.08:06:30.88#ibcon#read 6, iclass 16, count 0 2006.196.08:06:30.88#ibcon#end of sib2, iclass 16, count 0 2006.196.08:06:30.88#ibcon#*mode == 0, iclass 16, count 0 2006.196.08:06:30.88#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.196.08:06:30.88#ibcon#[27=USB\r\n] 2006.196.08:06:30.88#ibcon#*before write, iclass 16, count 0 2006.196.08:06:30.88#ibcon#enter sib2, iclass 16, count 0 2006.196.08:06:30.88#ibcon#flushed, iclass 16, count 0 2006.196.08:06:30.88#ibcon#about to write, iclass 16, count 0 2006.196.08:06:30.88#ibcon#wrote, iclass 16, count 0 2006.196.08:06:30.88#ibcon#about to read 3, iclass 16, count 0 2006.196.08:06:30.91#ibcon#read 3, iclass 16, count 0 2006.196.08:06:30.91#ibcon#about to read 4, iclass 16, count 0 2006.196.08:06:30.91#ibcon#read 4, iclass 16, count 0 2006.196.08:06:30.91#ibcon#about to read 5, iclass 16, count 0 2006.196.08:06:30.91#ibcon#read 5, iclass 16, count 0 2006.196.08:06:30.91#ibcon#about to read 6, iclass 16, count 0 2006.196.08:06:30.91#ibcon#read 6, iclass 16, count 0 2006.196.08:06:30.91#ibcon#end of sib2, iclass 16, count 0 2006.196.08:06:30.91#ibcon#*after write, iclass 16, count 0 2006.196.08:06:30.91#ibcon#*before return 0, iclass 16, count 0 2006.196.08:06:30.91#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.196.08:06:30.91#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.196.08:06:30.91#ibcon#about to clear, iclass 16 cls_cnt 0 2006.196.08:06:30.91#ibcon#cleared, iclass 16 cls_cnt 0 2006.196.08:06:30.91$vc4f8/vblo=2,640.99 2006.196.08:06:30.91#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.196.08:06:30.91#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.196.08:06:30.91#ibcon#ireg 17 cls_cnt 0 2006.196.08:06:30.91#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.196.08:06:30.91#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.196.08:06:30.91#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.196.08:06:30.91#ibcon#enter wrdev, iclass 18, count 0 2006.196.08:06:30.91#ibcon#first serial, iclass 18, count 0 2006.196.08:06:30.91#ibcon#enter sib2, iclass 18, count 0 2006.196.08:06:30.91#ibcon#flushed, iclass 18, count 0 2006.196.08:06:30.91#ibcon#about to write, iclass 18, count 0 2006.196.08:06:30.91#ibcon#wrote, iclass 18, count 0 2006.196.08:06:30.91#ibcon#about to read 3, iclass 18, count 0 2006.196.08:06:30.93#ibcon#read 3, iclass 18, count 0 2006.196.08:06:30.93#ibcon#about to read 4, iclass 18, count 0 2006.196.08:06:30.93#ibcon#read 4, iclass 18, count 0 2006.196.08:06:30.93#ibcon#about to read 5, iclass 18, count 0 2006.196.08:06:30.93#ibcon#read 5, iclass 18, count 0 2006.196.08:06:30.93#ibcon#about to read 6, iclass 18, count 0 2006.196.08:06:30.93#ibcon#read 6, iclass 18, count 0 2006.196.08:06:30.93#ibcon#end of sib2, iclass 18, count 0 2006.196.08:06:30.93#ibcon#*mode == 0, iclass 18, count 0 2006.196.08:06:30.93#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.196.08:06:30.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.196.08:06:30.93#ibcon#*before write, iclass 18, count 0 2006.196.08:06:30.93#ibcon#enter sib2, iclass 18, count 0 2006.196.08:06:30.93#ibcon#flushed, iclass 18, count 0 2006.196.08:06:30.93#ibcon#about to write, iclass 18, count 0 2006.196.08:06:30.93#ibcon#wrote, iclass 18, count 0 2006.196.08:06:30.93#ibcon#about to read 3, iclass 18, count 0 2006.196.08:06:30.98#ibcon#read 3, iclass 18, count 0 2006.196.08:06:30.98#ibcon#about to read 4, iclass 18, count 0 2006.196.08:06:30.98#ibcon#read 4, iclass 18, count 0 2006.196.08:06:30.98#ibcon#about to read 5, iclass 18, count 0 2006.196.08:06:30.98#ibcon#read 5, iclass 18, count 0 2006.196.08:06:30.98#ibcon#about to read 6, iclass 18, count 0 2006.196.08:06:30.98#ibcon#read 6, iclass 18, count 0 2006.196.08:06:30.98#ibcon#end of sib2, iclass 18, count 0 2006.196.08:06:30.98#ibcon#*after write, iclass 18, count 0 2006.196.08:06:30.98#ibcon#*before return 0, iclass 18, count 0 2006.196.08:06:30.98#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.196.08:06:30.98#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.196.08:06:30.98#ibcon#about to clear, iclass 18 cls_cnt 0 2006.196.08:06:30.98#ibcon#cleared, iclass 18 cls_cnt 0 2006.196.08:06:30.98$vc4f8/vb=2,4 2006.196.08:06:30.98#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.196.08:06:30.98#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.196.08:06:30.98#ibcon#ireg 11 cls_cnt 2 2006.196.08:06:30.98#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.196.08:06:31.03#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.196.08:06:31.03#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.196.08:06:31.03#ibcon#enter wrdev, iclass 20, count 2 2006.196.08:06:31.03#ibcon#first serial, iclass 20, count 2 2006.196.08:06:31.03#ibcon#enter sib2, iclass 20, count 2 2006.196.08:06:31.03#ibcon#flushed, iclass 20, count 2 2006.196.08:06:31.03#ibcon#about to write, iclass 20, count 2 2006.196.08:06:31.03#ibcon#wrote, iclass 20, count 2 2006.196.08:06:31.03#ibcon#about to read 3, iclass 20, count 2 2006.196.08:06:31.05#ibcon#read 3, iclass 20, count 2 2006.196.08:06:31.05#ibcon#about to read 4, iclass 20, count 2 2006.196.08:06:31.05#ibcon#read 4, iclass 20, count 2 2006.196.08:06:31.05#ibcon#about to read 5, iclass 20, count 2 2006.196.08:06:31.05#ibcon#read 5, iclass 20, count 2 2006.196.08:06:31.05#ibcon#about to read 6, iclass 20, count 2 2006.196.08:06:31.05#ibcon#read 6, iclass 20, count 2 2006.196.08:06:31.05#ibcon#end of sib2, iclass 20, count 2 2006.196.08:06:31.05#ibcon#*mode == 0, iclass 20, count 2 2006.196.08:06:31.05#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.196.08:06:31.05#ibcon#[27=AT02-04\r\n] 2006.196.08:06:31.05#ibcon#*before write, iclass 20, count 2 2006.196.08:06:31.05#ibcon#enter sib2, iclass 20, count 2 2006.196.08:06:31.05#ibcon#flushed, iclass 20, count 2 2006.196.08:06:31.05#ibcon#about to write, iclass 20, count 2 2006.196.08:06:31.05#ibcon#wrote, iclass 20, count 2 2006.196.08:06:31.05#ibcon#about to read 3, iclass 20, count 2 2006.196.08:06:31.08#ibcon#read 3, iclass 20, count 2 2006.196.08:06:31.08#ibcon#about to read 4, iclass 20, count 2 2006.196.08:06:31.08#ibcon#read 4, iclass 20, count 2 2006.196.08:06:31.08#ibcon#about to read 5, iclass 20, count 2 2006.196.08:06:31.08#ibcon#read 5, iclass 20, count 2 2006.196.08:06:31.08#ibcon#about to read 6, iclass 20, count 2 2006.196.08:06:31.08#ibcon#read 6, iclass 20, count 2 2006.196.08:06:31.08#ibcon#end of sib2, iclass 20, count 2 2006.196.08:06:31.08#ibcon#*after write, iclass 20, count 2 2006.196.08:06:31.08#ibcon#*before return 0, iclass 20, count 2 2006.196.08:06:31.08#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.196.08:06:31.08#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.196.08:06:31.08#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.196.08:06:31.08#ibcon#ireg 7 cls_cnt 0 2006.196.08:06:31.08#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.196.08:06:31.20#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.196.08:06:31.20#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.196.08:06:31.20#ibcon#enter wrdev, iclass 20, count 0 2006.196.08:06:31.20#ibcon#first serial, iclass 20, count 0 2006.196.08:06:31.20#ibcon#enter sib2, iclass 20, count 0 2006.196.08:06:31.20#ibcon#flushed, iclass 20, count 0 2006.196.08:06:31.20#ibcon#about to write, iclass 20, count 0 2006.196.08:06:31.20#ibcon#wrote, iclass 20, count 0 2006.196.08:06:31.20#ibcon#about to read 3, iclass 20, count 0 2006.196.08:06:31.22#ibcon#read 3, iclass 20, count 0 2006.196.08:06:31.22#ibcon#about to read 4, iclass 20, count 0 2006.196.08:06:31.22#ibcon#read 4, iclass 20, count 0 2006.196.08:06:31.22#ibcon#about to read 5, iclass 20, count 0 2006.196.08:06:31.22#ibcon#read 5, iclass 20, count 0 2006.196.08:06:31.22#ibcon#about to read 6, iclass 20, count 0 2006.196.08:06:31.22#ibcon#read 6, iclass 20, count 0 2006.196.08:06:31.22#ibcon#end of sib2, iclass 20, count 0 2006.196.08:06:31.22#ibcon#*mode == 0, iclass 20, count 0 2006.196.08:06:31.22#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.196.08:06:31.22#ibcon#[27=USB\r\n] 2006.196.08:06:31.22#ibcon#*before write, iclass 20, count 0 2006.196.08:06:31.22#ibcon#enter sib2, iclass 20, count 0 2006.196.08:06:31.22#ibcon#flushed, iclass 20, count 0 2006.196.08:06:31.22#ibcon#about to write, iclass 20, count 0 2006.196.08:06:31.22#ibcon#wrote, iclass 20, count 0 2006.196.08:06:31.22#ibcon#about to read 3, iclass 20, count 0 2006.196.08:06:31.25#ibcon#read 3, iclass 20, count 0 2006.196.08:06:31.25#ibcon#about to read 4, iclass 20, count 0 2006.196.08:06:31.25#ibcon#read 4, iclass 20, count 0 2006.196.08:06:31.25#ibcon#about to read 5, iclass 20, count 0 2006.196.08:06:31.25#ibcon#read 5, iclass 20, count 0 2006.196.08:06:31.25#ibcon#about to read 6, iclass 20, count 0 2006.196.08:06:31.25#ibcon#read 6, iclass 20, count 0 2006.196.08:06:31.25#ibcon#end of sib2, iclass 20, count 0 2006.196.08:06:31.25#ibcon#*after write, iclass 20, count 0 2006.196.08:06:31.25#ibcon#*before return 0, iclass 20, count 0 2006.196.08:06:31.25#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.196.08:06:31.25#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.196.08:06:31.25#ibcon#about to clear, iclass 20 cls_cnt 0 2006.196.08:06:31.25#ibcon#cleared, iclass 20 cls_cnt 0 2006.196.08:06:31.25$vc4f8/vblo=3,656.99 2006.196.08:06:31.25#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.196.08:06:31.25#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.196.08:06:31.25#ibcon#ireg 17 cls_cnt 0 2006.196.08:06:31.25#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.196.08:06:31.25#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.196.08:06:31.25#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.196.08:06:31.25#ibcon#enter wrdev, iclass 22, count 0 2006.196.08:06:31.25#ibcon#first serial, iclass 22, count 0 2006.196.08:06:31.25#ibcon#enter sib2, iclass 22, count 0 2006.196.08:06:31.25#ibcon#flushed, iclass 22, count 0 2006.196.08:06:31.25#ibcon#about to write, iclass 22, count 0 2006.196.08:06:31.25#ibcon#wrote, iclass 22, count 0 2006.196.08:06:31.25#ibcon#about to read 3, iclass 22, count 0 2006.196.08:06:31.27#ibcon#read 3, iclass 22, count 0 2006.196.08:06:31.27#ibcon#about to read 4, iclass 22, count 0 2006.196.08:06:31.27#ibcon#read 4, iclass 22, count 0 2006.196.08:06:31.27#ibcon#about to read 5, iclass 22, count 0 2006.196.08:06:31.27#ibcon#read 5, iclass 22, count 0 2006.196.08:06:31.27#ibcon#about to read 6, iclass 22, count 0 2006.196.08:06:31.27#ibcon#read 6, iclass 22, count 0 2006.196.08:06:31.27#ibcon#end of sib2, iclass 22, count 0 2006.196.08:06:31.27#ibcon#*mode == 0, iclass 22, count 0 2006.196.08:06:31.27#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.196.08:06:31.27#ibcon#[28=FRQ=03,656.99\r\n] 2006.196.08:06:31.27#ibcon#*before write, iclass 22, count 0 2006.196.08:06:31.27#ibcon#enter sib2, iclass 22, count 0 2006.196.08:06:31.27#ibcon#flushed, iclass 22, count 0 2006.196.08:06:31.27#ibcon#about to write, iclass 22, count 0 2006.196.08:06:31.27#ibcon#wrote, iclass 22, count 0 2006.196.08:06:31.27#ibcon#about to read 3, iclass 22, count 0 2006.196.08:06:31.31#ibcon#read 3, iclass 22, count 0 2006.196.08:06:31.31#ibcon#about to read 4, iclass 22, count 0 2006.196.08:06:31.31#ibcon#read 4, iclass 22, count 0 2006.196.08:06:31.31#ibcon#about to read 5, iclass 22, count 0 2006.196.08:06:31.31#ibcon#read 5, iclass 22, count 0 2006.196.08:06:31.31#ibcon#about to read 6, iclass 22, count 0 2006.196.08:06:31.31#ibcon#read 6, iclass 22, count 0 2006.196.08:06:31.31#ibcon#end of sib2, iclass 22, count 0 2006.196.08:06:31.31#ibcon#*after write, iclass 22, count 0 2006.196.08:06:31.31#ibcon#*before return 0, iclass 22, count 0 2006.196.08:06:31.31#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.196.08:06:31.31#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.196.08:06:31.31#ibcon#about to clear, iclass 22 cls_cnt 0 2006.196.08:06:31.31#ibcon#cleared, iclass 22 cls_cnt 0 2006.196.08:06:31.31$vc4f8/vb=3,4 2006.196.08:06:31.31#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.196.08:06:31.31#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.196.08:06:31.31#ibcon#ireg 11 cls_cnt 2 2006.196.08:06:31.31#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.196.08:06:31.37#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.196.08:06:31.37#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.196.08:06:31.37#ibcon#enter wrdev, iclass 24, count 2 2006.196.08:06:31.37#ibcon#first serial, iclass 24, count 2 2006.196.08:06:31.37#ibcon#enter sib2, iclass 24, count 2 2006.196.08:06:31.37#ibcon#flushed, iclass 24, count 2 2006.196.08:06:31.37#ibcon#about to write, iclass 24, count 2 2006.196.08:06:31.37#ibcon#wrote, iclass 24, count 2 2006.196.08:06:31.37#ibcon#about to read 3, iclass 24, count 2 2006.196.08:06:31.39#ibcon#read 3, iclass 24, count 2 2006.196.08:06:31.39#ibcon#about to read 4, iclass 24, count 2 2006.196.08:06:31.39#ibcon#read 4, iclass 24, count 2 2006.196.08:06:31.39#ibcon#about to read 5, iclass 24, count 2 2006.196.08:06:31.39#ibcon#read 5, iclass 24, count 2 2006.196.08:06:31.39#ibcon#about to read 6, iclass 24, count 2 2006.196.08:06:31.39#ibcon#read 6, iclass 24, count 2 2006.196.08:06:31.39#ibcon#end of sib2, iclass 24, count 2 2006.196.08:06:31.39#ibcon#*mode == 0, iclass 24, count 2 2006.196.08:06:31.39#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.196.08:06:31.39#ibcon#[27=AT03-04\r\n] 2006.196.08:06:31.39#ibcon#*before write, iclass 24, count 2 2006.196.08:06:31.39#ibcon#enter sib2, iclass 24, count 2 2006.196.08:06:31.39#ibcon#flushed, iclass 24, count 2 2006.196.08:06:31.39#ibcon#about to write, iclass 24, count 2 2006.196.08:06:31.39#ibcon#wrote, iclass 24, count 2 2006.196.08:06:31.39#ibcon#about to read 3, iclass 24, count 2 2006.196.08:06:31.42#ibcon#read 3, iclass 24, count 2 2006.196.08:06:31.42#ibcon#about to read 4, iclass 24, count 2 2006.196.08:06:31.42#ibcon#read 4, iclass 24, count 2 2006.196.08:06:31.42#ibcon#about to read 5, iclass 24, count 2 2006.196.08:06:31.42#ibcon#read 5, iclass 24, count 2 2006.196.08:06:31.42#ibcon#about to read 6, iclass 24, count 2 2006.196.08:06:31.42#ibcon#read 6, iclass 24, count 2 2006.196.08:06:31.42#ibcon#end of sib2, iclass 24, count 2 2006.196.08:06:31.42#ibcon#*after write, iclass 24, count 2 2006.196.08:06:31.42#ibcon#*before return 0, iclass 24, count 2 2006.196.08:06:31.42#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.196.08:06:31.42#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.196.08:06:31.42#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.196.08:06:31.42#ibcon#ireg 7 cls_cnt 0 2006.196.08:06:31.42#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.196.08:06:31.54#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.196.08:06:31.54#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.196.08:06:31.54#ibcon#enter wrdev, iclass 24, count 0 2006.196.08:06:31.54#ibcon#first serial, iclass 24, count 0 2006.196.08:06:31.54#ibcon#enter sib2, iclass 24, count 0 2006.196.08:06:31.54#ibcon#flushed, iclass 24, count 0 2006.196.08:06:31.54#ibcon#about to write, iclass 24, count 0 2006.196.08:06:31.54#ibcon#wrote, iclass 24, count 0 2006.196.08:06:31.54#ibcon#about to read 3, iclass 24, count 0 2006.196.08:06:31.56#ibcon#read 3, iclass 24, count 0 2006.196.08:06:31.56#ibcon#about to read 4, iclass 24, count 0 2006.196.08:06:31.56#ibcon#read 4, iclass 24, count 0 2006.196.08:06:31.56#ibcon#about to read 5, iclass 24, count 0 2006.196.08:06:31.56#ibcon#read 5, iclass 24, count 0 2006.196.08:06:31.56#ibcon#about to read 6, iclass 24, count 0 2006.196.08:06:31.56#ibcon#read 6, iclass 24, count 0 2006.196.08:06:31.56#ibcon#end of sib2, iclass 24, count 0 2006.196.08:06:31.56#ibcon#*mode == 0, iclass 24, count 0 2006.196.08:06:31.56#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.196.08:06:31.56#ibcon#[27=USB\r\n] 2006.196.08:06:31.56#ibcon#*before write, iclass 24, count 0 2006.196.08:06:31.56#ibcon#enter sib2, iclass 24, count 0 2006.196.08:06:31.56#ibcon#flushed, iclass 24, count 0 2006.196.08:06:31.56#ibcon#about to write, iclass 24, count 0 2006.196.08:06:31.56#ibcon#wrote, iclass 24, count 0 2006.196.08:06:31.56#ibcon#about to read 3, iclass 24, count 0 2006.196.08:06:31.59#ibcon#read 3, iclass 24, count 0 2006.196.08:06:31.59#ibcon#about to read 4, iclass 24, count 0 2006.196.08:06:31.59#ibcon#read 4, iclass 24, count 0 2006.196.08:06:31.59#ibcon#about to read 5, iclass 24, count 0 2006.196.08:06:31.59#ibcon#read 5, iclass 24, count 0 2006.196.08:06:31.59#ibcon#about to read 6, iclass 24, count 0 2006.196.08:06:31.59#ibcon#read 6, iclass 24, count 0 2006.196.08:06:31.59#ibcon#end of sib2, iclass 24, count 0 2006.196.08:06:31.59#ibcon#*after write, iclass 24, count 0 2006.196.08:06:31.59#ibcon#*before return 0, iclass 24, count 0 2006.196.08:06:31.59#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.196.08:06:31.59#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.196.08:06:31.59#ibcon#about to clear, iclass 24 cls_cnt 0 2006.196.08:06:31.59#ibcon#cleared, iclass 24 cls_cnt 0 2006.196.08:06:31.59$vc4f8/vblo=4,712.99 2006.196.08:06:31.59#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.196.08:06:31.59#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.196.08:06:31.59#ibcon#ireg 17 cls_cnt 0 2006.196.08:06:31.59#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.196.08:06:31.59#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.196.08:06:31.59#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.196.08:06:31.59#ibcon#enter wrdev, iclass 26, count 0 2006.196.08:06:31.59#ibcon#first serial, iclass 26, count 0 2006.196.08:06:31.59#ibcon#enter sib2, iclass 26, count 0 2006.196.08:06:31.59#ibcon#flushed, iclass 26, count 0 2006.196.08:06:31.59#ibcon#about to write, iclass 26, count 0 2006.196.08:06:31.59#ibcon#wrote, iclass 26, count 0 2006.196.08:06:31.59#ibcon#about to read 3, iclass 26, count 0 2006.196.08:06:31.61#ibcon#read 3, iclass 26, count 0 2006.196.08:06:31.61#ibcon#about to read 4, iclass 26, count 0 2006.196.08:06:31.61#ibcon#read 4, iclass 26, count 0 2006.196.08:06:31.61#ibcon#about to read 5, iclass 26, count 0 2006.196.08:06:31.61#ibcon#read 5, iclass 26, count 0 2006.196.08:06:31.61#ibcon#about to read 6, iclass 26, count 0 2006.196.08:06:31.61#ibcon#read 6, iclass 26, count 0 2006.196.08:06:31.61#ibcon#end of sib2, iclass 26, count 0 2006.196.08:06:31.61#ibcon#*mode == 0, iclass 26, count 0 2006.196.08:06:31.61#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.196.08:06:31.61#ibcon#[28=FRQ=04,712.99\r\n] 2006.196.08:06:31.61#ibcon#*before write, iclass 26, count 0 2006.196.08:06:31.61#ibcon#enter sib2, iclass 26, count 0 2006.196.08:06:31.61#ibcon#flushed, iclass 26, count 0 2006.196.08:06:31.61#ibcon#about to write, iclass 26, count 0 2006.196.08:06:31.61#ibcon#wrote, iclass 26, count 0 2006.196.08:06:31.61#ibcon#about to read 3, iclass 26, count 0 2006.196.08:06:31.65#ibcon#read 3, iclass 26, count 0 2006.196.08:06:31.65#ibcon#about to read 4, iclass 26, count 0 2006.196.08:06:31.65#ibcon#read 4, iclass 26, count 0 2006.196.08:06:31.65#ibcon#about to read 5, iclass 26, count 0 2006.196.08:06:31.65#ibcon#read 5, iclass 26, count 0 2006.196.08:06:31.65#ibcon#about to read 6, iclass 26, count 0 2006.196.08:06:31.65#ibcon#read 6, iclass 26, count 0 2006.196.08:06:31.65#ibcon#end of sib2, iclass 26, count 0 2006.196.08:06:31.65#ibcon#*after write, iclass 26, count 0 2006.196.08:06:31.65#ibcon#*before return 0, iclass 26, count 0 2006.196.08:06:31.65#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.196.08:06:31.65#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.196.08:06:31.65#ibcon#about to clear, iclass 26 cls_cnt 0 2006.196.08:06:31.65#ibcon#cleared, iclass 26 cls_cnt 0 2006.196.08:06:31.65$vc4f8/vb=4,4 2006.196.08:06:31.65#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.196.08:06:31.65#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.196.08:06:31.65#ibcon#ireg 11 cls_cnt 2 2006.196.08:06:31.65#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.196.08:06:31.71#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.196.08:06:31.71#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.196.08:06:31.71#ibcon#enter wrdev, iclass 28, count 2 2006.196.08:06:31.71#ibcon#first serial, iclass 28, count 2 2006.196.08:06:31.71#ibcon#enter sib2, iclass 28, count 2 2006.196.08:06:31.71#ibcon#flushed, iclass 28, count 2 2006.196.08:06:31.71#ibcon#about to write, iclass 28, count 2 2006.196.08:06:31.71#ibcon#wrote, iclass 28, count 2 2006.196.08:06:31.71#ibcon#about to read 3, iclass 28, count 2 2006.196.08:06:31.73#ibcon#read 3, iclass 28, count 2 2006.196.08:06:31.73#ibcon#about to read 4, iclass 28, count 2 2006.196.08:06:31.73#ibcon#read 4, iclass 28, count 2 2006.196.08:06:31.73#ibcon#about to read 5, iclass 28, count 2 2006.196.08:06:31.73#ibcon#read 5, iclass 28, count 2 2006.196.08:06:31.73#ibcon#about to read 6, iclass 28, count 2 2006.196.08:06:31.73#ibcon#read 6, iclass 28, count 2 2006.196.08:06:31.73#ibcon#end of sib2, iclass 28, count 2 2006.196.08:06:31.73#ibcon#*mode == 0, iclass 28, count 2 2006.196.08:06:31.73#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.196.08:06:31.73#ibcon#[27=AT04-04\r\n] 2006.196.08:06:31.73#ibcon#*before write, iclass 28, count 2 2006.196.08:06:31.73#ibcon#enter sib2, iclass 28, count 2 2006.196.08:06:31.73#ibcon#flushed, iclass 28, count 2 2006.196.08:06:31.73#ibcon#about to write, iclass 28, count 2 2006.196.08:06:31.73#ibcon#wrote, iclass 28, count 2 2006.196.08:06:31.73#ibcon#about to read 3, iclass 28, count 2 2006.196.08:06:31.76#ibcon#read 3, iclass 28, count 2 2006.196.08:06:31.76#ibcon#about to read 4, iclass 28, count 2 2006.196.08:06:31.76#ibcon#read 4, iclass 28, count 2 2006.196.08:06:31.76#ibcon#about to read 5, iclass 28, count 2 2006.196.08:06:31.76#ibcon#read 5, iclass 28, count 2 2006.196.08:06:31.76#ibcon#about to read 6, iclass 28, count 2 2006.196.08:06:31.76#ibcon#read 6, iclass 28, count 2 2006.196.08:06:31.76#ibcon#end of sib2, iclass 28, count 2 2006.196.08:06:31.76#ibcon#*after write, iclass 28, count 2 2006.196.08:06:31.76#ibcon#*before return 0, iclass 28, count 2 2006.196.08:06:31.76#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.196.08:06:31.76#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.196.08:06:31.76#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.196.08:06:31.76#ibcon#ireg 7 cls_cnt 0 2006.196.08:06:31.76#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.196.08:06:31.88#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.196.08:06:31.88#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.196.08:06:31.88#ibcon#enter wrdev, iclass 28, count 0 2006.196.08:06:31.88#ibcon#first serial, iclass 28, count 0 2006.196.08:06:31.88#ibcon#enter sib2, iclass 28, count 0 2006.196.08:06:31.88#ibcon#flushed, iclass 28, count 0 2006.196.08:06:31.88#ibcon#about to write, iclass 28, count 0 2006.196.08:06:31.88#ibcon#wrote, iclass 28, count 0 2006.196.08:06:31.88#ibcon#about to read 3, iclass 28, count 0 2006.196.08:06:31.90#ibcon#read 3, iclass 28, count 0 2006.196.08:06:31.90#ibcon#about to read 4, iclass 28, count 0 2006.196.08:06:31.90#ibcon#read 4, iclass 28, count 0 2006.196.08:06:31.90#ibcon#about to read 5, iclass 28, count 0 2006.196.08:06:31.90#ibcon#read 5, iclass 28, count 0 2006.196.08:06:31.90#ibcon#about to read 6, iclass 28, count 0 2006.196.08:06:31.90#ibcon#read 6, iclass 28, count 0 2006.196.08:06:31.90#ibcon#end of sib2, iclass 28, count 0 2006.196.08:06:31.90#ibcon#*mode == 0, iclass 28, count 0 2006.196.08:06:31.90#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.196.08:06:31.90#ibcon#[27=USB\r\n] 2006.196.08:06:31.90#ibcon#*before write, iclass 28, count 0 2006.196.08:06:31.90#ibcon#enter sib2, iclass 28, count 0 2006.196.08:06:31.90#ibcon#flushed, iclass 28, count 0 2006.196.08:06:31.90#ibcon#about to write, iclass 28, count 0 2006.196.08:06:31.90#ibcon#wrote, iclass 28, count 0 2006.196.08:06:31.90#ibcon#about to read 3, iclass 28, count 0 2006.196.08:06:31.93#ibcon#read 3, iclass 28, count 0 2006.196.08:06:31.93#ibcon#about to read 4, iclass 28, count 0 2006.196.08:06:31.93#ibcon#read 4, iclass 28, count 0 2006.196.08:06:31.93#ibcon#about to read 5, iclass 28, count 0 2006.196.08:06:31.93#ibcon#read 5, iclass 28, count 0 2006.196.08:06:31.93#ibcon#about to read 6, iclass 28, count 0 2006.196.08:06:31.93#ibcon#read 6, iclass 28, count 0 2006.196.08:06:31.93#ibcon#end of sib2, iclass 28, count 0 2006.196.08:06:31.93#ibcon#*after write, iclass 28, count 0 2006.196.08:06:31.93#ibcon#*before return 0, iclass 28, count 0 2006.196.08:06:31.93#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.196.08:06:31.93#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.196.08:06:31.93#ibcon#about to clear, iclass 28 cls_cnt 0 2006.196.08:06:31.93#ibcon#cleared, iclass 28 cls_cnt 0 2006.196.08:06:31.93$vc4f8/vblo=5,744.99 2006.196.08:06:31.93#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.196.08:06:31.93#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.196.08:06:31.93#ibcon#ireg 17 cls_cnt 0 2006.196.08:06:31.93#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.196.08:06:31.93#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.196.08:06:31.93#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.196.08:06:31.93#ibcon#enter wrdev, iclass 30, count 0 2006.196.08:06:31.93#ibcon#first serial, iclass 30, count 0 2006.196.08:06:31.93#ibcon#enter sib2, iclass 30, count 0 2006.196.08:06:31.93#ibcon#flushed, iclass 30, count 0 2006.196.08:06:31.93#ibcon#about to write, iclass 30, count 0 2006.196.08:06:31.93#ibcon#wrote, iclass 30, count 0 2006.196.08:06:31.93#ibcon#about to read 3, iclass 30, count 0 2006.196.08:06:31.95#ibcon#read 3, iclass 30, count 0 2006.196.08:06:31.95#ibcon#about to read 4, iclass 30, count 0 2006.196.08:06:31.95#ibcon#read 4, iclass 30, count 0 2006.196.08:06:31.95#ibcon#about to read 5, iclass 30, count 0 2006.196.08:06:31.95#ibcon#read 5, iclass 30, count 0 2006.196.08:06:31.95#ibcon#about to read 6, iclass 30, count 0 2006.196.08:06:31.95#ibcon#read 6, iclass 30, count 0 2006.196.08:06:31.95#ibcon#end of sib2, iclass 30, count 0 2006.196.08:06:31.95#ibcon#*mode == 0, iclass 30, count 0 2006.196.08:06:31.95#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.196.08:06:31.95#ibcon#[28=FRQ=05,744.99\r\n] 2006.196.08:06:31.95#ibcon#*before write, iclass 30, count 0 2006.196.08:06:31.95#ibcon#enter sib2, iclass 30, count 0 2006.196.08:06:31.95#ibcon#flushed, iclass 30, count 0 2006.196.08:06:31.95#ibcon#about to write, iclass 30, count 0 2006.196.08:06:31.95#ibcon#wrote, iclass 30, count 0 2006.196.08:06:31.95#ibcon#about to read 3, iclass 30, count 0 2006.196.08:06:31.99#ibcon#read 3, iclass 30, count 0 2006.196.08:06:31.99#ibcon#about to read 4, iclass 30, count 0 2006.196.08:06:31.99#ibcon#read 4, iclass 30, count 0 2006.196.08:06:31.99#ibcon#about to read 5, iclass 30, count 0 2006.196.08:06:31.99#ibcon#read 5, iclass 30, count 0 2006.196.08:06:31.99#ibcon#about to read 6, iclass 30, count 0 2006.196.08:06:31.99#ibcon#read 6, iclass 30, count 0 2006.196.08:06:31.99#ibcon#end of sib2, iclass 30, count 0 2006.196.08:06:31.99#ibcon#*after write, iclass 30, count 0 2006.196.08:06:31.99#ibcon#*before return 0, iclass 30, count 0 2006.196.08:06:31.99#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.196.08:06:31.99#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.196.08:06:31.99#ibcon#about to clear, iclass 30 cls_cnt 0 2006.196.08:06:31.99#ibcon#cleared, iclass 30 cls_cnt 0 2006.196.08:06:31.99$vc4f8/vb=5,4 2006.196.08:06:31.99#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.196.08:06:31.99#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.196.08:06:31.99#ibcon#ireg 11 cls_cnt 2 2006.196.08:06:31.99#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.196.08:06:32.05#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.196.08:06:32.05#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.196.08:06:32.05#ibcon#enter wrdev, iclass 32, count 2 2006.196.08:06:32.05#ibcon#first serial, iclass 32, count 2 2006.196.08:06:32.05#ibcon#enter sib2, iclass 32, count 2 2006.196.08:06:32.05#ibcon#flushed, iclass 32, count 2 2006.196.08:06:32.05#ibcon#about to write, iclass 32, count 2 2006.196.08:06:32.05#ibcon#wrote, iclass 32, count 2 2006.196.08:06:32.05#ibcon#about to read 3, iclass 32, count 2 2006.196.08:06:32.07#ibcon#read 3, iclass 32, count 2 2006.196.08:06:32.07#ibcon#about to read 4, iclass 32, count 2 2006.196.08:06:32.07#ibcon#read 4, iclass 32, count 2 2006.196.08:06:32.07#ibcon#about to read 5, iclass 32, count 2 2006.196.08:06:32.07#ibcon#read 5, iclass 32, count 2 2006.196.08:06:32.07#ibcon#about to read 6, iclass 32, count 2 2006.196.08:06:32.07#ibcon#read 6, iclass 32, count 2 2006.196.08:06:32.07#ibcon#end of sib2, iclass 32, count 2 2006.196.08:06:32.07#ibcon#*mode == 0, iclass 32, count 2 2006.196.08:06:32.07#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.196.08:06:32.07#ibcon#[27=AT05-04\r\n] 2006.196.08:06:32.07#ibcon#*before write, iclass 32, count 2 2006.196.08:06:32.07#ibcon#enter sib2, iclass 32, count 2 2006.196.08:06:32.07#ibcon#flushed, iclass 32, count 2 2006.196.08:06:32.07#ibcon#about to write, iclass 32, count 2 2006.196.08:06:32.07#ibcon#wrote, iclass 32, count 2 2006.196.08:06:32.07#ibcon#about to read 3, iclass 32, count 2 2006.196.08:06:32.10#ibcon#read 3, iclass 32, count 2 2006.196.08:06:32.10#ibcon#about to read 4, iclass 32, count 2 2006.196.08:06:32.10#ibcon#read 4, iclass 32, count 2 2006.196.08:06:32.10#ibcon#about to read 5, iclass 32, count 2 2006.196.08:06:32.10#ibcon#read 5, iclass 32, count 2 2006.196.08:06:32.10#ibcon#about to read 6, iclass 32, count 2 2006.196.08:06:32.10#ibcon#read 6, iclass 32, count 2 2006.196.08:06:32.10#ibcon#end of sib2, iclass 32, count 2 2006.196.08:06:32.10#ibcon#*after write, iclass 32, count 2 2006.196.08:06:32.10#ibcon#*before return 0, iclass 32, count 2 2006.196.08:06:32.10#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.196.08:06:32.10#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.196.08:06:32.10#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.196.08:06:32.10#ibcon#ireg 7 cls_cnt 0 2006.196.08:06:32.10#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.196.08:06:32.22#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.196.08:06:32.22#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.196.08:06:32.22#ibcon#enter wrdev, iclass 32, count 0 2006.196.08:06:32.22#ibcon#first serial, iclass 32, count 0 2006.196.08:06:32.22#ibcon#enter sib2, iclass 32, count 0 2006.196.08:06:32.22#ibcon#flushed, iclass 32, count 0 2006.196.08:06:32.22#ibcon#about to write, iclass 32, count 0 2006.196.08:06:32.22#ibcon#wrote, iclass 32, count 0 2006.196.08:06:32.22#ibcon#about to read 3, iclass 32, count 0 2006.196.08:06:32.24#ibcon#read 3, iclass 32, count 0 2006.196.08:06:32.24#ibcon#about to read 4, iclass 32, count 0 2006.196.08:06:32.24#ibcon#read 4, iclass 32, count 0 2006.196.08:06:32.24#ibcon#about to read 5, iclass 32, count 0 2006.196.08:06:32.24#ibcon#read 5, iclass 32, count 0 2006.196.08:06:32.24#ibcon#about to read 6, iclass 32, count 0 2006.196.08:06:32.24#ibcon#read 6, iclass 32, count 0 2006.196.08:06:32.24#ibcon#end of sib2, iclass 32, count 0 2006.196.08:06:32.24#ibcon#*mode == 0, iclass 32, count 0 2006.196.08:06:32.24#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.196.08:06:32.24#ibcon#[27=USB\r\n] 2006.196.08:06:32.24#ibcon#*before write, iclass 32, count 0 2006.196.08:06:32.24#ibcon#enter sib2, iclass 32, count 0 2006.196.08:06:32.24#ibcon#flushed, iclass 32, count 0 2006.196.08:06:32.24#ibcon#about to write, iclass 32, count 0 2006.196.08:06:32.24#ibcon#wrote, iclass 32, count 0 2006.196.08:06:32.24#ibcon#about to read 3, iclass 32, count 0 2006.196.08:06:32.27#ibcon#read 3, iclass 32, count 0 2006.196.08:06:32.27#ibcon#about to read 4, iclass 32, count 0 2006.196.08:06:32.27#ibcon#read 4, iclass 32, count 0 2006.196.08:06:32.27#ibcon#about to read 5, iclass 32, count 0 2006.196.08:06:32.27#ibcon#read 5, iclass 32, count 0 2006.196.08:06:32.27#ibcon#about to read 6, iclass 32, count 0 2006.196.08:06:32.27#ibcon#read 6, iclass 32, count 0 2006.196.08:06:32.27#ibcon#end of sib2, iclass 32, count 0 2006.196.08:06:32.27#ibcon#*after write, iclass 32, count 0 2006.196.08:06:32.27#ibcon#*before return 0, iclass 32, count 0 2006.196.08:06:32.27#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.196.08:06:32.27#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.196.08:06:32.27#ibcon#about to clear, iclass 32 cls_cnt 0 2006.196.08:06:32.27#ibcon#cleared, iclass 32 cls_cnt 0 2006.196.08:06:32.27$vc4f8/vblo=6,752.99 2006.196.08:06:32.27#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.196.08:06:32.27#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.196.08:06:32.27#ibcon#ireg 17 cls_cnt 0 2006.196.08:06:32.27#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.196.08:06:32.27#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.196.08:06:32.27#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.196.08:06:32.27#ibcon#enter wrdev, iclass 34, count 0 2006.196.08:06:32.27#ibcon#first serial, iclass 34, count 0 2006.196.08:06:32.27#ibcon#enter sib2, iclass 34, count 0 2006.196.08:06:32.27#ibcon#flushed, iclass 34, count 0 2006.196.08:06:32.27#ibcon#about to write, iclass 34, count 0 2006.196.08:06:32.27#ibcon#wrote, iclass 34, count 0 2006.196.08:06:32.27#ibcon#about to read 3, iclass 34, count 0 2006.196.08:06:32.29#ibcon#read 3, iclass 34, count 0 2006.196.08:06:32.29#ibcon#about to read 4, iclass 34, count 0 2006.196.08:06:32.29#ibcon#read 4, iclass 34, count 0 2006.196.08:06:32.29#ibcon#about to read 5, iclass 34, count 0 2006.196.08:06:32.29#ibcon#read 5, iclass 34, count 0 2006.196.08:06:32.29#ibcon#about to read 6, iclass 34, count 0 2006.196.08:06:32.29#ibcon#read 6, iclass 34, count 0 2006.196.08:06:32.29#ibcon#end of sib2, iclass 34, count 0 2006.196.08:06:32.29#ibcon#*mode == 0, iclass 34, count 0 2006.196.08:06:32.29#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.196.08:06:32.29#ibcon#[28=FRQ=06,752.99\r\n] 2006.196.08:06:32.29#ibcon#*before write, iclass 34, count 0 2006.196.08:06:32.29#ibcon#enter sib2, iclass 34, count 0 2006.196.08:06:32.29#ibcon#flushed, iclass 34, count 0 2006.196.08:06:32.29#ibcon#about to write, iclass 34, count 0 2006.196.08:06:32.29#ibcon#wrote, iclass 34, count 0 2006.196.08:06:32.29#ibcon#about to read 3, iclass 34, count 0 2006.196.08:06:32.33#ibcon#read 3, iclass 34, count 0 2006.196.08:06:32.33#ibcon#about to read 4, iclass 34, count 0 2006.196.08:06:32.33#ibcon#read 4, iclass 34, count 0 2006.196.08:06:32.33#ibcon#about to read 5, iclass 34, count 0 2006.196.08:06:32.33#ibcon#read 5, iclass 34, count 0 2006.196.08:06:32.33#ibcon#about to read 6, iclass 34, count 0 2006.196.08:06:32.33#ibcon#read 6, iclass 34, count 0 2006.196.08:06:32.33#ibcon#end of sib2, iclass 34, count 0 2006.196.08:06:32.33#ibcon#*after write, iclass 34, count 0 2006.196.08:06:32.33#ibcon#*before return 0, iclass 34, count 0 2006.196.08:06:32.33#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.196.08:06:32.33#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.196.08:06:32.33#ibcon#about to clear, iclass 34 cls_cnt 0 2006.196.08:06:32.33#ibcon#cleared, iclass 34 cls_cnt 0 2006.196.08:06:32.33$vc4f8/vb=6,4 2006.196.08:06:32.33#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.196.08:06:32.33#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.196.08:06:32.33#ibcon#ireg 11 cls_cnt 2 2006.196.08:06:32.33#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.196.08:06:32.39#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.196.08:06:32.39#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.196.08:06:32.39#ibcon#enter wrdev, iclass 36, count 2 2006.196.08:06:32.39#ibcon#first serial, iclass 36, count 2 2006.196.08:06:32.39#ibcon#enter sib2, iclass 36, count 2 2006.196.08:06:32.39#ibcon#flushed, iclass 36, count 2 2006.196.08:06:32.39#ibcon#about to write, iclass 36, count 2 2006.196.08:06:32.39#ibcon#wrote, iclass 36, count 2 2006.196.08:06:32.39#ibcon#about to read 3, iclass 36, count 2 2006.196.08:06:32.41#ibcon#read 3, iclass 36, count 2 2006.196.08:06:32.41#ibcon#about to read 4, iclass 36, count 2 2006.196.08:06:32.41#ibcon#read 4, iclass 36, count 2 2006.196.08:06:32.41#ibcon#about to read 5, iclass 36, count 2 2006.196.08:06:32.41#ibcon#read 5, iclass 36, count 2 2006.196.08:06:32.41#ibcon#about to read 6, iclass 36, count 2 2006.196.08:06:32.41#ibcon#read 6, iclass 36, count 2 2006.196.08:06:32.41#ibcon#end of sib2, iclass 36, count 2 2006.196.08:06:32.41#ibcon#*mode == 0, iclass 36, count 2 2006.196.08:06:32.41#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.196.08:06:32.41#ibcon#[27=AT06-04\r\n] 2006.196.08:06:32.41#ibcon#*before write, iclass 36, count 2 2006.196.08:06:32.41#ibcon#enter sib2, iclass 36, count 2 2006.196.08:06:32.41#ibcon#flushed, iclass 36, count 2 2006.196.08:06:32.41#ibcon#about to write, iclass 36, count 2 2006.196.08:06:32.41#ibcon#wrote, iclass 36, count 2 2006.196.08:06:32.41#ibcon#about to read 3, iclass 36, count 2 2006.196.08:06:32.44#ibcon#read 3, iclass 36, count 2 2006.196.08:06:32.44#ibcon#about to read 4, iclass 36, count 2 2006.196.08:06:32.44#ibcon#read 4, iclass 36, count 2 2006.196.08:06:32.44#ibcon#about to read 5, iclass 36, count 2 2006.196.08:06:32.44#ibcon#read 5, iclass 36, count 2 2006.196.08:06:32.44#ibcon#about to read 6, iclass 36, count 2 2006.196.08:06:32.44#ibcon#read 6, iclass 36, count 2 2006.196.08:06:32.44#ibcon#end of sib2, iclass 36, count 2 2006.196.08:06:32.44#ibcon#*after write, iclass 36, count 2 2006.196.08:06:32.44#ibcon#*before return 0, iclass 36, count 2 2006.196.08:06:32.44#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.196.08:06:32.44#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.196.08:06:32.44#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.196.08:06:32.44#ibcon#ireg 7 cls_cnt 0 2006.196.08:06:32.44#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.196.08:06:32.56#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.196.08:06:32.56#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.196.08:06:32.56#ibcon#enter wrdev, iclass 36, count 0 2006.196.08:06:32.56#ibcon#first serial, iclass 36, count 0 2006.196.08:06:32.56#ibcon#enter sib2, iclass 36, count 0 2006.196.08:06:32.56#ibcon#flushed, iclass 36, count 0 2006.196.08:06:32.56#ibcon#about to write, iclass 36, count 0 2006.196.08:06:32.56#ibcon#wrote, iclass 36, count 0 2006.196.08:06:32.56#ibcon#about to read 3, iclass 36, count 0 2006.196.08:06:32.58#ibcon#read 3, iclass 36, count 0 2006.196.08:06:32.58#ibcon#about to read 4, iclass 36, count 0 2006.196.08:06:32.58#ibcon#read 4, iclass 36, count 0 2006.196.08:06:32.58#ibcon#about to read 5, iclass 36, count 0 2006.196.08:06:32.58#ibcon#read 5, iclass 36, count 0 2006.196.08:06:32.58#ibcon#about to read 6, iclass 36, count 0 2006.196.08:06:32.58#ibcon#read 6, iclass 36, count 0 2006.196.08:06:32.58#ibcon#end of sib2, iclass 36, count 0 2006.196.08:06:32.58#ibcon#*mode == 0, iclass 36, count 0 2006.196.08:06:32.58#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.196.08:06:32.58#ibcon#[27=USB\r\n] 2006.196.08:06:32.58#ibcon#*before write, iclass 36, count 0 2006.196.08:06:32.58#ibcon#enter sib2, iclass 36, count 0 2006.196.08:06:32.58#ibcon#flushed, iclass 36, count 0 2006.196.08:06:32.58#ibcon#about to write, iclass 36, count 0 2006.196.08:06:32.58#ibcon#wrote, iclass 36, count 0 2006.196.08:06:32.58#ibcon#about to read 3, iclass 36, count 0 2006.196.08:06:32.61#ibcon#read 3, iclass 36, count 0 2006.196.08:06:32.61#ibcon#about to read 4, iclass 36, count 0 2006.196.08:06:32.61#ibcon#read 4, iclass 36, count 0 2006.196.08:06:32.61#ibcon#about to read 5, iclass 36, count 0 2006.196.08:06:32.61#ibcon#read 5, iclass 36, count 0 2006.196.08:06:32.61#ibcon#about to read 6, iclass 36, count 0 2006.196.08:06:32.61#ibcon#read 6, iclass 36, count 0 2006.196.08:06:32.61#ibcon#end of sib2, iclass 36, count 0 2006.196.08:06:32.61#ibcon#*after write, iclass 36, count 0 2006.196.08:06:32.61#ibcon#*before return 0, iclass 36, count 0 2006.196.08:06:32.61#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.196.08:06:32.61#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.196.08:06:32.61#ibcon#about to clear, iclass 36 cls_cnt 0 2006.196.08:06:32.61#ibcon#cleared, iclass 36 cls_cnt 0 2006.196.08:06:32.61$vc4f8/vabw=wide 2006.196.08:06:32.61#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.196.08:06:32.61#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.196.08:06:32.61#ibcon#ireg 8 cls_cnt 0 2006.196.08:06:32.61#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.196.08:06:32.61#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.196.08:06:32.61#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.196.08:06:32.61#ibcon#enter wrdev, iclass 38, count 0 2006.196.08:06:32.61#ibcon#first serial, iclass 38, count 0 2006.196.08:06:32.61#ibcon#enter sib2, iclass 38, count 0 2006.196.08:06:32.61#ibcon#flushed, iclass 38, count 0 2006.196.08:06:32.61#ibcon#about to write, iclass 38, count 0 2006.196.08:06:32.61#ibcon#wrote, iclass 38, count 0 2006.196.08:06:32.61#ibcon#about to read 3, iclass 38, count 0 2006.196.08:06:32.63#ibcon#read 3, iclass 38, count 0 2006.196.08:06:32.63#ibcon#about to read 4, iclass 38, count 0 2006.196.08:06:32.63#ibcon#read 4, iclass 38, count 0 2006.196.08:06:32.63#ibcon#about to read 5, iclass 38, count 0 2006.196.08:06:32.63#ibcon#read 5, iclass 38, count 0 2006.196.08:06:32.63#ibcon#about to read 6, iclass 38, count 0 2006.196.08:06:32.63#ibcon#read 6, iclass 38, count 0 2006.196.08:06:32.63#ibcon#end of sib2, iclass 38, count 0 2006.196.08:06:32.63#ibcon#*mode == 0, iclass 38, count 0 2006.196.08:06:32.63#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.196.08:06:32.63#ibcon#[25=BW32\r\n] 2006.196.08:06:32.63#ibcon#*before write, iclass 38, count 0 2006.196.08:06:32.63#ibcon#enter sib2, iclass 38, count 0 2006.196.08:06:32.63#ibcon#flushed, iclass 38, count 0 2006.196.08:06:32.63#ibcon#about to write, iclass 38, count 0 2006.196.08:06:32.63#ibcon#wrote, iclass 38, count 0 2006.196.08:06:32.63#ibcon#about to read 3, iclass 38, count 0 2006.196.08:06:32.67#ibcon#read 3, iclass 38, count 0 2006.196.08:06:32.67#ibcon#about to read 4, iclass 38, count 0 2006.196.08:06:32.67#ibcon#read 4, iclass 38, count 0 2006.196.08:06:32.67#ibcon#about to read 5, iclass 38, count 0 2006.196.08:06:32.67#ibcon#read 5, iclass 38, count 0 2006.196.08:06:32.67#ibcon#about to read 6, iclass 38, count 0 2006.196.08:06:32.67#ibcon#read 6, iclass 38, count 0 2006.196.08:06:32.67#ibcon#end of sib2, iclass 38, count 0 2006.196.08:06:32.67#ibcon#*after write, iclass 38, count 0 2006.196.08:06:32.67#ibcon#*before return 0, iclass 38, count 0 2006.196.08:06:32.67#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.196.08:06:32.67#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.196.08:06:32.67#ibcon#about to clear, iclass 38 cls_cnt 0 2006.196.08:06:32.67#ibcon#cleared, iclass 38 cls_cnt 0 2006.196.08:06:32.67$vc4f8/vbbw=wide 2006.196.08:06:32.67#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.196.08:06:32.67#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.196.08:06:32.67#ibcon#ireg 8 cls_cnt 0 2006.196.08:06:32.67#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.196.08:06:32.73#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.196.08:06:32.73#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.196.08:06:32.73#ibcon#enter wrdev, iclass 40, count 0 2006.196.08:06:32.73#ibcon#first serial, iclass 40, count 0 2006.196.08:06:32.73#ibcon#enter sib2, iclass 40, count 0 2006.196.08:06:32.73#ibcon#flushed, iclass 40, count 0 2006.196.08:06:32.73#ibcon#about to write, iclass 40, count 0 2006.196.08:06:32.73#ibcon#wrote, iclass 40, count 0 2006.196.08:06:32.73#ibcon#about to read 3, iclass 40, count 0 2006.196.08:06:32.75#ibcon#read 3, iclass 40, count 0 2006.196.08:06:32.75#ibcon#about to read 4, iclass 40, count 0 2006.196.08:06:32.75#ibcon#read 4, iclass 40, count 0 2006.196.08:06:32.75#ibcon#about to read 5, iclass 40, count 0 2006.196.08:06:32.75#ibcon#read 5, iclass 40, count 0 2006.196.08:06:32.75#ibcon#about to read 6, iclass 40, count 0 2006.196.08:06:32.75#ibcon#read 6, iclass 40, count 0 2006.196.08:06:32.75#ibcon#end of sib2, iclass 40, count 0 2006.196.08:06:32.75#ibcon#*mode == 0, iclass 40, count 0 2006.196.08:06:32.75#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.196.08:06:32.75#ibcon#[27=BW32\r\n] 2006.196.08:06:32.75#ibcon#*before write, iclass 40, count 0 2006.196.08:06:32.75#ibcon#enter sib2, iclass 40, count 0 2006.196.08:06:32.75#ibcon#flushed, iclass 40, count 0 2006.196.08:06:32.75#ibcon#about to write, iclass 40, count 0 2006.196.08:06:32.75#ibcon#wrote, iclass 40, count 0 2006.196.08:06:32.75#ibcon#about to read 3, iclass 40, count 0 2006.196.08:06:32.78#ibcon#read 3, iclass 40, count 0 2006.196.08:06:32.78#ibcon#about to read 4, iclass 40, count 0 2006.196.08:06:32.78#ibcon#read 4, iclass 40, count 0 2006.196.08:06:32.78#ibcon#about to read 5, iclass 40, count 0 2006.196.08:06:32.78#ibcon#read 5, iclass 40, count 0 2006.196.08:06:32.78#ibcon#about to read 6, iclass 40, count 0 2006.196.08:06:32.78#ibcon#read 6, iclass 40, count 0 2006.196.08:06:32.78#ibcon#end of sib2, iclass 40, count 0 2006.196.08:06:32.78#ibcon#*after write, iclass 40, count 0 2006.196.08:06:32.78#ibcon#*before return 0, iclass 40, count 0 2006.196.08:06:32.78#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.196.08:06:32.78#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.196.08:06:32.78#ibcon#about to clear, iclass 40 cls_cnt 0 2006.196.08:06:32.78#ibcon#cleared, iclass 40 cls_cnt 0 2006.196.08:06:32.78$4f8m12a/ifd4f 2006.196.08:06:32.78$ifd4f/lo= 2006.196.08:06:32.78$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.196.08:06:32.78$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.196.08:06:32.78$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.196.08:06:32.78$ifd4f/patch= 2006.196.08:06:32.78$ifd4f/patch=lo1,a1,a2,a3,a4 2006.196.08:06:32.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.196.08:06:32.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.196.08:06:32.78$4f8m12a/"form=m,16.000,1:2 2006.196.08:06:32.78$4f8m12a/"tpicd 2006.196.08:06:32.78$4f8m12a/echo=off 2006.196.08:06:32.78$4f8m12a/xlog=off 2006.196.08:06:32.78:!2006.196.08:07:00 2006.196.08:06:42.13#trakl#Source acquired 2006.196.08:06:42.13#flagr#flagr/antenna,acquired 2006.196.08:07:00.00:preob 2006.196.08:07:01.13/onsource/TRACKING 2006.196.08:07:01.13:!2006.196.08:07:10 2006.196.08:07:10.00:data_valid=on 2006.196.08:07:10.00:midob 2006.196.08:07:10.13/onsource/TRACKING 2006.196.08:07:10.13/wx/29.34,1003.9,90 2006.196.08:07:10.22/cable/+6.3328E-03 2006.196.08:07:11.31/va/01,08,usb,yes,28,30 2006.196.08:07:11.31/va/02,07,usb,yes,28,30 2006.196.08:07:11.31/va/03,06,usb,yes,30,30 2006.196.08:07:11.31/va/04,07,usb,yes,29,31 2006.196.08:07:11.31/va/05,07,usb,yes,31,33 2006.196.08:07:11.31/va/06,06,usb,yes,30,30 2006.196.08:07:11.31/va/07,06,usb,yes,30,30 2006.196.08:07:11.31/va/08,07,usb,yes,29,28 2006.196.08:07:11.54/valo/01,532.99,yes,locked 2006.196.08:07:11.54/valo/02,572.99,yes,locked 2006.196.08:07:11.54/valo/03,672.99,yes,locked 2006.196.08:07:11.54/valo/04,832.99,yes,locked 2006.196.08:07:11.54/valo/05,652.99,yes,locked 2006.196.08:07:11.54/valo/06,772.99,yes,locked 2006.196.08:07:11.54/valo/07,832.99,yes,locked 2006.196.08:07:11.54/valo/08,852.99,yes,locked 2006.196.08:07:12.63/vb/01,04,usb,yes,28,27 2006.196.08:07:12.63/vb/02,04,usb,yes,30,31 2006.196.08:07:12.63/vb/03,04,usb,yes,26,30 2006.196.08:07:12.63/vb/04,04,usb,yes,27,27 2006.196.08:07:12.63/vb/05,04,usb,yes,26,30 2006.196.08:07:12.63/vb/06,04,usb,yes,27,29 2006.196.08:07:12.63/vb/07,04,usb,yes,29,29 2006.196.08:07:12.63/vb/08,04,usb,yes,26,30 2006.196.08:07:12.87/vblo/01,632.99,yes,locked 2006.196.08:07:12.87/vblo/02,640.99,yes,locked 2006.196.08:07:12.87/vblo/03,656.99,yes,locked 2006.196.08:07:12.87/vblo/04,712.99,yes,locked 2006.196.08:07:12.87/vblo/05,744.99,yes,locked 2006.196.08:07:12.87/vblo/06,752.99,yes,locked 2006.196.08:07:12.87/vblo/07,734.99,yes,locked 2006.196.08:07:12.87/vblo/08,744.99,yes,locked 2006.196.08:07:13.02/vabw/8 2006.196.08:07:13.17/vbbw/8 2006.196.08:07:13.26/xfe/off,on,15.0 2006.196.08:07:13.63/ifatt/23,28,28,28 2006.196.08:07:14.07/fmout-gps/S +3.37E-07 2006.196.08:07:14.11:!2006.196.08:08:10 2006.196.08:08:10.00:data_valid=off 2006.196.08:08:10.00:postob 2006.196.08:08:10.18/cable/+6.3381E-03 2006.196.08:08:10.18/wx/29.31,1003.9,91 2006.196.08:08:11.07/fmout-gps/S +3.38E-07 2006.196.08:08:11.07:scan_name=196-0809,k06196,160 2006.196.08:08:11.07:source=0808+019,081126.71,014652.2,2000.0,ccw 2006.196.08:08:11.14#flagr#flagr/antenna,new-source 2006.196.08:08:12.14:checkk5 2006.196.08:08:12.51/chk_autoobs//k5ts1/ autoobs is running! 2006.196.08:08:12.88/chk_autoobs//k5ts2/ autoobs is running! 2006.196.08:08:13.26/chk_autoobs//k5ts3/ autoobs is running! 2006.196.08:08:13.64/chk_autoobs//k5ts4/ autoobs is running! 2006.196.08:08:14.01/chk_obsdata//k5ts1/T1960807??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.08:08:14.38/chk_obsdata//k5ts2/T1960807??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.08:08:14.75/chk_obsdata//k5ts3/T1960807??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.08:08:15.12/chk_obsdata//k5ts4/T1960807??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.08:08:15.81/k5log//k5ts1_log_newline 2006.196.08:08:16.50/k5log//k5ts2_log_newline 2006.196.08:08:17.18/k5log//k5ts3_log_newline 2006.196.08:08:17.87/k5log//k5ts4_log_newline 2006.196.08:08:17.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.196.08:08:17.89:4f8m12a=2 2006.196.08:08:17.89$4f8m12a/echo=on 2006.196.08:08:17.89$4f8m12a/pcalon 2006.196.08:08:17.89$pcalon/"no phase cal control is implemented here 2006.196.08:08:17.89$4f8m12a/"tpicd=stop 2006.196.08:08:17.89$4f8m12a/vc4f8 2006.196.08:08:17.89$vc4f8/valo=1,532.99 2006.196.08:08:17.90#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.196.08:08:17.90#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.196.08:08:17.90#ibcon#ireg 17 cls_cnt 0 2006.196.08:08:17.90#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.196.08:08:17.90#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.196.08:08:17.90#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.196.08:08:17.90#ibcon#enter wrdev, iclass 15, count 0 2006.196.08:08:17.90#ibcon#first serial, iclass 15, count 0 2006.196.08:08:17.90#ibcon#enter sib2, iclass 15, count 0 2006.196.08:08:17.90#ibcon#flushed, iclass 15, count 0 2006.196.08:08:17.90#ibcon#about to write, iclass 15, count 0 2006.196.08:08:17.90#ibcon#wrote, iclass 15, count 0 2006.196.08:08:17.90#ibcon#about to read 3, iclass 15, count 0 2006.196.08:08:17.94#ibcon#read 3, iclass 15, count 0 2006.196.08:08:17.94#ibcon#about to read 4, iclass 15, count 0 2006.196.08:08:17.94#ibcon#read 4, iclass 15, count 0 2006.196.08:08:17.94#ibcon#about to read 5, iclass 15, count 0 2006.196.08:08:17.94#ibcon#read 5, iclass 15, count 0 2006.196.08:08:17.94#ibcon#about to read 6, iclass 15, count 0 2006.196.08:08:17.94#ibcon#read 6, iclass 15, count 0 2006.196.08:08:17.94#ibcon#end of sib2, iclass 15, count 0 2006.196.08:08:17.94#ibcon#*mode == 0, iclass 15, count 0 2006.196.08:08:17.94#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.196.08:08:17.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.196.08:08:17.94#ibcon#*before write, iclass 15, count 0 2006.196.08:08:17.94#ibcon#enter sib2, iclass 15, count 0 2006.196.08:08:17.94#ibcon#flushed, iclass 15, count 0 2006.196.08:08:17.94#ibcon#about to write, iclass 15, count 0 2006.196.08:08:17.94#ibcon#wrote, iclass 15, count 0 2006.196.08:08:17.94#ibcon#about to read 3, iclass 15, count 0 2006.196.08:08:17.99#ibcon#read 3, iclass 15, count 0 2006.196.08:08:17.99#ibcon#about to read 4, iclass 15, count 0 2006.196.08:08:17.99#ibcon#read 4, iclass 15, count 0 2006.196.08:08:17.99#ibcon#about to read 5, iclass 15, count 0 2006.196.08:08:17.99#ibcon#read 5, iclass 15, count 0 2006.196.08:08:17.99#ibcon#about to read 6, iclass 15, count 0 2006.196.08:08:17.99#ibcon#read 6, iclass 15, count 0 2006.196.08:08:17.99#ibcon#end of sib2, iclass 15, count 0 2006.196.08:08:17.99#ibcon#*after write, iclass 15, count 0 2006.196.08:08:17.99#ibcon#*before return 0, iclass 15, count 0 2006.196.08:08:17.99#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.196.08:08:17.99#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.196.08:08:17.99#ibcon#about to clear, iclass 15 cls_cnt 0 2006.196.08:08:17.99#ibcon#cleared, iclass 15 cls_cnt 0 2006.196.08:08:17.99$vc4f8/va=1,8 2006.196.08:08:17.99#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.196.08:08:17.99#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.196.08:08:17.99#ibcon#ireg 11 cls_cnt 2 2006.196.08:08:17.99#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.196.08:08:17.99#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.196.08:08:17.99#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.196.08:08:17.99#ibcon#enter wrdev, iclass 17, count 2 2006.196.08:08:17.99#ibcon#first serial, iclass 17, count 2 2006.196.08:08:17.99#ibcon#enter sib2, iclass 17, count 2 2006.196.08:08:17.99#ibcon#flushed, iclass 17, count 2 2006.196.08:08:17.99#ibcon#about to write, iclass 17, count 2 2006.196.08:08:17.99#ibcon#wrote, iclass 17, count 2 2006.196.08:08:17.99#ibcon#about to read 3, iclass 17, count 2 2006.196.08:08:18.01#ibcon#read 3, iclass 17, count 2 2006.196.08:08:18.01#ibcon#about to read 4, iclass 17, count 2 2006.196.08:08:18.01#ibcon#read 4, iclass 17, count 2 2006.196.08:08:18.01#ibcon#about to read 5, iclass 17, count 2 2006.196.08:08:18.01#ibcon#read 5, iclass 17, count 2 2006.196.08:08:18.01#ibcon#about to read 6, iclass 17, count 2 2006.196.08:08:18.01#ibcon#read 6, iclass 17, count 2 2006.196.08:08:18.01#ibcon#end of sib2, iclass 17, count 2 2006.196.08:08:18.01#ibcon#*mode == 0, iclass 17, count 2 2006.196.08:08:18.01#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.196.08:08:18.01#ibcon#[25=AT01-08\r\n] 2006.196.08:08:18.01#ibcon#*before write, iclass 17, count 2 2006.196.08:08:18.01#ibcon#enter sib2, iclass 17, count 2 2006.196.08:08:18.01#ibcon#flushed, iclass 17, count 2 2006.196.08:08:18.01#ibcon#about to write, iclass 17, count 2 2006.196.08:08:18.01#ibcon#wrote, iclass 17, count 2 2006.196.08:08:18.01#ibcon#about to read 3, iclass 17, count 2 2006.196.08:08:18.04#ibcon#read 3, iclass 17, count 2 2006.196.08:08:18.04#ibcon#about to read 4, iclass 17, count 2 2006.196.08:08:18.04#ibcon#read 4, iclass 17, count 2 2006.196.08:08:18.04#ibcon#about to read 5, iclass 17, count 2 2006.196.08:08:18.04#ibcon#read 5, iclass 17, count 2 2006.196.08:08:18.04#ibcon#about to read 6, iclass 17, count 2 2006.196.08:08:18.04#ibcon#read 6, iclass 17, count 2 2006.196.08:08:18.04#ibcon#end of sib2, iclass 17, count 2 2006.196.08:08:18.04#ibcon#*after write, iclass 17, count 2 2006.196.08:08:18.04#ibcon#*before return 0, iclass 17, count 2 2006.196.08:08:18.04#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.196.08:08:18.04#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.196.08:08:18.04#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.196.08:08:18.04#ibcon#ireg 7 cls_cnt 0 2006.196.08:08:18.04#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.196.08:08:18.16#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.196.08:08:18.16#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.196.08:08:18.16#ibcon#enter wrdev, iclass 17, count 0 2006.196.08:08:18.16#ibcon#first serial, iclass 17, count 0 2006.196.08:08:18.16#ibcon#enter sib2, iclass 17, count 0 2006.196.08:08:18.16#ibcon#flushed, iclass 17, count 0 2006.196.08:08:18.16#ibcon#about to write, iclass 17, count 0 2006.196.08:08:18.16#ibcon#wrote, iclass 17, count 0 2006.196.08:08:18.16#ibcon#about to read 3, iclass 17, count 0 2006.196.08:08:18.18#ibcon#read 3, iclass 17, count 0 2006.196.08:08:18.18#ibcon#about to read 4, iclass 17, count 0 2006.196.08:08:18.18#ibcon#read 4, iclass 17, count 0 2006.196.08:08:18.18#ibcon#about to read 5, iclass 17, count 0 2006.196.08:08:18.18#ibcon#read 5, iclass 17, count 0 2006.196.08:08:18.18#ibcon#about to read 6, iclass 17, count 0 2006.196.08:08:18.18#ibcon#read 6, iclass 17, count 0 2006.196.08:08:18.18#ibcon#end of sib2, iclass 17, count 0 2006.196.08:08:18.18#ibcon#*mode == 0, iclass 17, count 0 2006.196.08:08:18.18#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.196.08:08:18.18#ibcon#[25=USB\r\n] 2006.196.08:08:18.18#ibcon#*before write, iclass 17, count 0 2006.196.08:08:18.18#ibcon#enter sib2, iclass 17, count 0 2006.196.08:08:18.18#ibcon#flushed, iclass 17, count 0 2006.196.08:08:18.18#ibcon#about to write, iclass 17, count 0 2006.196.08:08:18.18#ibcon#wrote, iclass 17, count 0 2006.196.08:08:18.18#ibcon#about to read 3, iclass 17, count 0 2006.196.08:08:18.21#ibcon#read 3, iclass 17, count 0 2006.196.08:08:18.21#ibcon#about to read 4, iclass 17, count 0 2006.196.08:08:18.21#ibcon#read 4, iclass 17, count 0 2006.196.08:08:18.21#ibcon#about to read 5, iclass 17, count 0 2006.196.08:08:18.21#ibcon#read 5, iclass 17, count 0 2006.196.08:08:18.21#ibcon#about to read 6, iclass 17, count 0 2006.196.08:08:18.21#ibcon#read 6, iclass 17, count 0 2006.196.08:08:18.21#ibcon#end of sib2, iclass 17, count 0 2006.196.08:08:18.21#ibcon#*after write, iclass 17, count 0 2006.196.08:08:18.21#ibcon#*before return 0, iclass 17, count 0 2006.196.08:08:18.21#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.196.08:08:18.21#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.196.08:08:18.21#ibcon#about to clear, iclass 17 cls_cnt 0 2006.196.08:08:18.21#ibcon#cleared, iclass 17 cls_cnt 0 2006.196.08:08:18.21$vc4f8/valo=2,572.99 2006.196.08:08:18.21#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.196.08:08:18.21#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.196.08:08:18.21#ibcon#ireg 17 cls_cnt 0 2006.196.08:08:18.21#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.196.08:08:18.21#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.196.08:08:18.21#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.196.08:08:18.21#ibcon#enter wrdev, iclass 19, count 0 2006.196.08:08:18.21#ibcon#first serial, iclass 19, count 0 2006.196.08:08:18.21#ibcon#enter sib2, iclass 19, count 0 2006.196.08:08:18.21#ibcon#flushed, iclass 19, count 0 2006.196.08:08:18.21#ibcon#about to write, iclass 19, count 0 2006.196.08:08:18.21#ibcon#wrote, iclass 19, count 0 2006.196.08:08:18.21#ibcon#about to read 3, iclass 19, count 0 2006.196.08:08:18.23#ibcon#read 3, iclass 19, count 0 2006.196.08:08:18.23#ibcon#about to read 4, iclass 19, count 0 2006.196.08:08:18.23#ibcon#read 4, iclass 19, count 0 2006.196.08:08:18.23#ibcon#about to read 5, iclass 19, count 0 2006.196.08:08:18.23#ibcon#read 5, iclass 19, count 0 2006.196.08:08:18.23#ibcon#about to read 6, iclass 19, count 0 2006.196.08:08:18.23#ibcon#read 6, iclass 19, count 0 2006.196.08:08:18.23#ibcon#end of sib2, iclass 19, count 0 2006.196.08:08:18.23#ibcon#*mode == 0, iclass 19, count 0 2006.196.08:08:18.23#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.196.08:08:18.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.196.08:08:18.23#ibcon#*before write, iclass 19, count 0 2006.196.08:08:18.23#ibcon#enter sib2, iclass 19, count 0 2006.196.08:08:18.23#ibcon#flushed, iclass 19, count 0 2006.196.08:08:18.23#ibcon#about to write, iclass 19, count 0 2006.196.08:08:18.23#ibcon#wrote, iclass 19, count 0 2006.196.08:08:18.23#ibcon#about to read 3, iclass 19, count 0 2006.196.08:08:18.28#ibcon#read 3, iclass 19, count 0 2006.196.08:08:18.28#ibcon#about to read 4, iclass 19, count 0 2006.196.08:08:18.28#ibcon#read 4, iclass 19, count 0 2006.196.08:08:18.28#ibcon#about to read 5, iclass 19, count 0 2006.196.08:08:18.28#ibcon#read 5, iclass 19, count 0 2006.196.08:08:18.28#ibcon#about to read 6, iclass 19, count 0 2006.196.08:08:18.28#ibcon#read 6, iclass 19, count 0 2006.196.08:08:18.28#ibcon#end of sib2, iclass 19, count 0 2006.196.08:08:18.28#ibcon#*after write, iclass 19, count 0 2006.196.08:08:18.28#ibcon#*before return 0, iclass 19, count 0 2006.196.08:08:18.28#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.196.08:08:18.28#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.196.08:08:18.28#ibcon#about to clear, iclass 19 cls_cnt 0 2006.196.08:08:18.28#ibcon#cleared, iclass 19 cls_cnt 0 2006.196.08:08:18.28$vc4f8/va=2,7 2006.196.08:08:18.28#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.196.08:08:18.28#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.196.08:08:18.28#ibcon#ireg 11 cls_cnt 2 2006.196.08:08:18.28#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.196.08:08:18.33#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.196.08:08:18.33#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.196.08:08:18.33#ibcon#enter wrdev, iclass 21, count 2 2006.196.08:08:18.33#ibcon#first serial, iclass 21, count 2 2006.196.08:08:18.33#ibcon#enter sib2, iclass 21, count 2 2006.196.08:08:18.33#ibcon#flushed, iclass 21, count 2 2006.196.08:08:18.33#ibcon#about to write, iclass 21, count 2 2006.196.08:08:18.33#ibcon#wrote, iclass 21, count 2 2006.196.08:08:18.33#ibcon#about to read 3, iclass 21, count 2 2006.196.08:08:18.35#ibcon#read 3, iclass 21, count 2 2006.196.08:08:18.35#ibcon#about to read 4, iclass 21, count 2 2006.196.08:08:18.35#ibcon#read 4, iclass 21, count 2 2006.196.08:08:18.35#ibcon#about to read 5, iclass 21, count 2 2006.196.08:08:18.35#ibcon#read 5, iclass 21, count 2 2006.196.08:08:18.35#ibcon#about to read 6, iclass 21, count 2 2006.196.08:08:18.35#ibcon#read 6, iclass 21, count 2 2006.196.08:08:18.35#ibcon#end of sib2, iclass 21, count 2 2006.196.08:08:18.35#ibcon#*mode == 0, iclass 21, count 2 2006.196.08:08:18.35#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.196.08:08:18.35#ibcon#[25=AT02-07\r\n] 2006.196.08:08:18.35#ibcon#*before write, iclass 21, count 2 2006.196.08:08:18.35#ibcon#enter sib2, iclass 21, count 2 2006.196.08:08:18.35#ibcon#flushed, iclass 21, count 2 2006.196.08:08:18.35#ibcon#about to write, iclass 21, count 2 2006.196.08:08:18.35#ibcon#wrote, iclass 21, count 2 2006.196.08:08:18.35#ibcon#about to read 3, iclass 21, count 2 2006.196.08:08:18.38#ibcon#read 3, iclass 21, count 2 2006.196.08:08:18.38#ibcon#about to read 4, iclass 21, count 2 2006.196.08:08:18.38#ibcon#read 4, iclass 21, count 2 2006.196.08:08:18.38#ibcon#about to read 5, iclass 21, count 2 2006.196.08:08:18.38#ibcon#read 5, iclass 21, count 2 2006.196.08:08:18.38#ibcon#about to read 6, iclass 21, count 2 2006.196.08:08:18.38#ibcon#read 6, iclass 21, count 2 2006.196.08:08:18.38#ibcon#end of sib2, iclass 21, count 2 2006.196.08:08:18.38#ibcon#*after write, iclass 21, count 2 2006.196.08:08:18.38#ibcon#*before return 0, iclass 21, count 2 2006.196.08:08:18.38#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.196.08:08:18.38#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.196.08:08:18.38#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.196.08:08:18.38#ibcon#ireg 7 cls_cnt 0 2006.196.08:08:18.38#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.196.08:08:18.50#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.196.08:08:18.50#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.196.08:08:18.50#ibcon#enter wrdev, iclass 21, count 0 2006.196.08:08:18.50#ibcon#first serial, iclass 21, count 0 2006.196.08:08:18.50#ibcon#enter sib2, iclass 21, count 0 2006.196.08:08:18.50#ibcon#flushed, iclass 21, count 0 2006.196.08:08:18.50#ibcon#about to write, iclass 21, count 0 2006.196.08:08:18.50#ibcon#wrote, iclass 21, count 0 2006.196.08:08:18.50#ibcon#about to read 3, iclass 21, count 0 2006.196.08:08:18.52#ibcon#read 3, iclass 21, count 0 2006.196.08:08:18.52#ibcon#about to read 4, iclass 21, count 0 2006.196.08:08:18.52#ibcon#read 4, iclass 21, count 0 2006.196.08:08:18.52#ibcon#about to read 5, iclass 21, count 0 2006.196.08:08:18.52#ibcon#read 5, iclass 21, count 0 2006.196.08:08:18.52#ibcon#about to read 6, iclass 21, count 0 2006.196.08:08:18.52#ibcon#read 6, iclass 21, count 0 2006.196.08:08:18.52#ibcon#end of sib2, iclass 21, count 0 2006.196.08:08:18.52#ibcon#*mode == 0, iclass 21, count 0 2006.196.08:08:18.52#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.196.08:08:18.52#ibcon#[25=USB\r\n] 2006.196.08:08:18.52#ibcon#*before write, iclass 21, count 0 2006.196.08:08:18.52#ibcon#enter sib2, iclass 21, count 0 2006.196.08:08:18.52#ibcon#flushed, iclass 21, count 0 2006.196.08:08:18.52#ibcon#about to write, iclass 21, count 0 2006.196.08:08:18.52#ibcon#wrote, iclass 21, count 0 2006.196.08:08:18.52#ibcon#about to read 3, iclass 21, count 0 2006.196.08:08:18.55#ibcon#read 3, iclass 21, count 0 2006.196.08:08:18.55#ibcon#about to read 4, iclass 21, count 0 2006.196.08:08:18.55#ibcon#read 4, iclass 21, count 0 2006.196.08:08:18.55#ibcon#about to read 5, iclass 21, count 0 2006.196.08:08:18.55#ibcon#read 5, iclass 21, count 0 2006.196.08:08:18.55#ibcon#about to read 6, iclass 21, count 0 2006.196.08:08:18.55#ibcon#read 6, iclass 21, count 0 2006.196.08:08:18.55#ibcon#end of sib2, iclass 21, count 0 2006.196.08:08:18.55#ibcon#*after write, iclass 21, count 0 2006.196.08:08:18.55#ibcon#*before return 0, iclass 21, count 0 2006.196.08:08:18.55#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.196.08:08:18.55#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.196.08:08:18.55#ibcon#about to clear, iclass 21 cls_cnt 0 2006.196.08:08:18.55#ibcon#cleared, iclass 21 cls_cnt 0 2006.196.08:08:18.55$vc4f8/valo=3,672.99 2006.196.08:08:18.55#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.196.08:08:18.55#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.196.08:08:18.55#ibcon#ireg 17 cls_cnt 0 2006.196.08:08:18.55#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.196.08:08:18.55#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.196.08:08:18.55#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.196.08:08:18.55#ibcon#enter wrdev, iclass 23, count 0 2006.196.08:08:18.55#ibcon#first serial, iclass 23, count 0 2006.196.08:08:18.55#ibcon#enter sib2, iclass 23, count 0 2006.196.08:08:18.55#ibcon#flushed, iclass 23, count 0 2006.196.08:08:18.55#ibcon#about to write, iclass 23, count 0 2006.196.08:08:18.55#ibcon#wrote, iclass 23, count 0 2006.196.08:08:18.55#ibcon#about to read 3, iclass 23, count 0 2006.196.08:08:18.57#ibcon#read 3, iclass 23, count 0 2006.196.08:08:18.57#ibcon#about to read 4, iclass 23, count 0 2006.196.08:08:18.57#ibcon#read 4, iclass 23, count 0 2006.196.08:08:18.57#ibcon#about to read 5, iclass 23, count 0 2006.196.08:08:18.57#ibcon#read 5, iclass 23, count 0 2006.196.08:08:18.57#ibcon#about to read 6, iclass 23, count 0 2006.196.08:08:18.57#ibcon#read 6, iclass 23, count 0 2006.196.08:08:18.57#ibcon#end of sib2, iclass 23, count 0 2006.196.08:08:18.57#ibcon#*mode == 0, iclass 23, count 0 2006.196.08:08:18.57#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.196.08:08:18.57#ibcon#[26=FRQ=03,672.99\r\n] 2006.196.08:08:18.57#ibcon#*before write, iclass 23, count 0 2006.196.08:08:18.57#ibcon#enter sib2, iclass 23, count 0 2006.196.08:08:18.57#ibcon#flushed, iclass 23, count 0 2006.196.08:08:18.57#ibcon#about to write, iclass 23, count 0 2006.196.08:08:18.57#ibcon#wrote, iclass 23, count 0 2006.196.08:08:18.57#ibcon#about to read 3, iclass 23, count 0 2006.196.08:08:18.62#ibcon#read 3, iclass 23, count 0 2006.196.08:08:18.62#ibcon#about to read 4, iclass 23, count 0 2006.196.08:08:18.62#ibcon#read 4, iclass 23, count 0 2006.196.08:08:18.62#ibcon#about to read 5, iclass 23, count 0 2006.196.08:08:18.62#ibcon#read 5, iclass 23, count 0 2006.196.08:08:18.62#ibcon#about to read 6, iclass 23, count 0 2006.196.08:08:18.62#ibcon#read 6, iclass 23, count 0 2006.196.08:08:18.62#ibcon#end of sib2, iclass 23, count 0 2006.196.08:08:18.62#ibcon#*after write, iclass 23, count 0 2006.196.08:08:18.62#ibcon#*before return 0, iclass 23, count 0 2006.196.08:08:18.62#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.196.08:08:18.62#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.196.08:08:18.62#ibcon#about to clear, iclass 23 cls_cnt 0 2006.196.08:08:18.62#ibcon#cleared, iclass 23 cls_cnt 0 2006.196.08:08:18.62$vc4f8/va=3,6 2006.196.08:08:18.62#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.196.08:08:18.62#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.196.08:08:18.62#ibcon#ireg 11 cls_cnt 2 2006.196.08:08:18.62#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.196.08:08:18.67#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.196.08:08:18.67#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.196.08:08:18.67#ibcon#enter wrdev, iclass 25, count 2 2006.196.08:08:18.67#ibcon#first serial, iclass 25, count 2 2006.196.08:08:18.67#ibcon#enter sib2, iclass 25, count 2 2006.196.08:08:18.67#ibcon#flushed, iclass 25, count 2 2006.196.08:08:18.67#ibcon#about to write, iclass 25, count 2 2006.196.08:08:18.67#ibcon#wrote, iclass 25, count 2 2006.196.08:08:18.67#ibcon#about to read 3, iclass 25, count 2 2006.196.08:08:18.69#ibcon#read 3, iclass 25, count 2 2006.196.08:08:18.69#ibcon#about to read 4, iclass 25, count 2 2006.196.08:08:18.69#ibcon#read 4, iclass 25, count 2 2006.196.08:08:18.69#ibcon#about to read 5, iclass 25, count 2 2006.196.08:08:18.69#ibcon#read 5, iclass 25, count 2 2006.196.08:08:18.69#ibcon#about to read 6, iclass 25, count 2 2006.196.08:08:18.69#ibcon#read 6, iclass 25, count 2 2006.196.08:08:18.69#ibcon#end of sib2, iclass 25, count 2 2006.196.08:08:18.69#ibcon#*mode == 0, iclass 25, count 2 2006.196.08:08:18.69#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.196.08:08:18.69#ibcon#[25=AT03-06\r\n] 2006.196.08:08:18.69#ibcon#*before write, iclass 25, count 2 2006.196.08:08:18.69#ibcon#enter sib2, iclass 25, count 2 2006.196.08:08:18.69#ibcon#flushed, iclass 25, count 2 2006.196.08:08:18.69#ibcon#about to write, iclass 25, count 2 2006.196.08:08:18.69#ibcon#wrote, iclass 25, count 2 2006.196.08:08:18.69#ibcon#about to read 3, iclass 25, count 2 2006.196.08:08:18.72#ibcon#read 3, iclass 25, count 2 2006.196.08:08:18.72#ibcon#about to read 4, iclass 25, count 2 2006.196.08:08:18.72#ibcon#read 4, iclass 25, count 2 2006.196.08:08:18.72#ibcon#about to read 5, iclass 25, count 2 2006.196.08:08:18.72#ibcon#read 5, iclass 25, count 2 2006.196.08:08:18.72#ibcon#about to read 6, iclass 25, count 2 2006.196.08:08:18.72#ibcon#read 6, iclass 25, count 2 2006.196.08:08:18.72#ibcon#end of sib2, iclass 25, count 2 2006.196.08:08:18.72#ibcon#*after write, iclass 25, count 2 2006.196.08:08:18.72#ibcon#*before return 0, iclass 25, count 2 2006.196.08:08:18.72#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.196.08:08:18.72#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.196.08:08:18.72#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.196.08:08:18.72#ibcon#ireg 7 cls_cnt 0 2006.196.08:08:18.72#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.196.08:08:18.84#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.196.08:08:18.84#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.196.08:08:18.84#ibcon#enter wrdev, iclass 25, count 0 2006.196.08:08:18.84#ibcon#first serial, iclass 25, count 0 2006.196.08:08:18.84#ibcon#enter sib2, iclass 25, count 0 2006.196.08:08:18.84#ibcon#flushed, iclass 25, count 0 2006.196.08:08:18.84#ibcon#about to write, iclass 25, count 0 2006.196.08:08:18.84#ibcon#wrote, iclass 25, count 0 2006.196.08:08:18.84#ibcon#about to read 3, iclass 25, count 0 2006.196.08:08:18.86#ibcon#read 3, iclass 25, count 0 2006.196.08:08:18.86#ibcon#about to read 4, iclass 25, count 0 2006.196.08:08:18.86#ibcon#read 4, iclass 25, count 0 2006.196.08:08:18.86#ibcon#about to read 5, iclass 25, count 0 2006.196.08:08:18.86#ibcon#read 5, iclass 25, count 0 2006.196.08:08:18.86#ibcon#about to read 6, iclass 25, count 0 2006.196.08:08:18.86#ibcon#read 6, iclass 25, count 0 2006.196.08:08:18.86#ibcon#end of sib2, iclass 25, count 0 2006.196.08:08:18.86#ibcon#*mode == 0, iclass 25, count 0 2006.196.08:08:18.86#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.196.08:08:18.86#ibcon#[25=USB\r\n] 2006.196.08:08:18.86#ibcon#*before write, iclass 25, count 0 2006.196.08:08:18.86#ibcon#enter sib2, iclass 25, count 0 2006.196.08:08:18.86#ibcon#flushed, iclass 25, count 0 2006.196.08:08:18.86#ibcon#about to write, iclass 25, count 0 2006.196.08:08:18.86#ibcon#wrote, iclass 25, count 0 2006.196.08:08:18.86#ibcon#about to read 3, iclass 25, count 0 2006.196.08:08:18.89#ibcon#read 3, iclass 25, count 0 2006.196.08:08:18.89#ibcon#about to read 4, iclass 25, count 0 2006.196.08:08:18.89#ibcon#read 4, iclass 25, count 0 2006.196.08:08:18.89#ibcon#about to read 5, iclass 25, count 0 2006.196.08:08:18.89#ibcon#read 5, iclass 25, count 0 2006.196.08:08:18.89#ibcon#about to read 6, iclass 25, count 0 2006.196.08:08:18.89#ibcon#read 6, iclass 25, count 0 2006.196.08:08:18.89#ibcon#end of sib2, iclass 25, count 0 2006.196.08:08:18.89#ibcon#*after write, iclass 25, count 0 2006.196.08:08:18.89#ibcon#*before return 0, iclass 25, count 0 2006.196.08:08:18.89#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.196.08:08:18.89#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.196.08:08:18.89#ibcon#about to clear, iclass 25 cls_cnt 0 2006.196.08:08:18.89#ibcon#cleared, iclass 25 cls_cnt 0 2006.196.08:08:18.89$vc4f8/valo=4,832.99 2006.196.08:08:18.89#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.196.08:08:18.89#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.196.08:08:18.89#ibcon#ireg 17 cls_cnt 0 2006.196.08:08:18.89#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.196.08:08:18.89#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.196.08:08:18.89#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.196.08:08:18.89#ibcon#enter wrdev, iclass 27, count 0 2006.196.08:08:18.89#ibcon#first serial, iclass 27, count 0 2006.196.08:08:18.89#ibcon#enter sib2, iclass 27, count 0 2006.196.08:08:18.89#ibcon#flushed, iclass 27, count 0 2006.196.08:08:18.89#ibcon#about to write, iclass 27, count 0 2006.196.08:08:18.89#ibcon#wrote, iclass 27, count 0 2006.196.08:08:18.89#ibcon#about to read 3, iclass 27, count 0 2006.196.08:08:18.91#ibcon#read 3, iclass 27, count 0 2006.196.08:08:18.91#ibcon#about to read 4, iclass 27, count 0 2006.196.08:08:18.91#ibcon#read 4, iclass 27, count 0 2006.196.08:08:18.91#ibcon#about to read 5, iclass 27, count 0 2006.196.08:08:18.91#ibcon#read 5, iclass 27, count 0 2006.196.08:08:18.91#ibcon#about to read 6, iclass 27, count 0 2006.196.08:08:18.91#ibcon#read 6, iclass 27, count 0 2006.196.08:08:18.91#ibcon#end of sib2, iclass 27, count 0 2006.196.08:08:18.91#ibcon#*mode == 0, iclass 27, count 0 2006.196.08:08:18.91#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.196.08:08:18.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.196.08:08:18.91#ibcon#*before write, iclass 27, count 0 2006.196.08:08:18.91#ibcon#enter sib2, iclass 27, count 0 2006.196.08:08:18.91#ibcon#flushed, iclass 27, count 0 2006.196.08:08:18.91#ibcon#about to write, iclass 27, count 0 2006.196.08:08:18.91#ibcon#wrote, iclass 27, count 0 2006.196.08:08:18.91#ibcon#about to read 3, iclass 27, count 0 2006.196.08:08:18.96#ibcon#read 3, iclass 27, count 0 2006.196.08:08:18.96#ibcon#about to read 4, iclass 27, count 0 2006.196.08:08:18.96#ibcon#read 4, iclass 27, count 0 2006.196.08:08:18.96#ibcon#about to read 5, iclass 27, count 0 2006.196.08:08:18.96#ibcon#read 5, iclass 27, count 0 2006.196.08:08:18.96#ibcon#about to read 6, iclass 27, count 0 2006.196.08:08:18.96#ibcon#read 6, iclass 27, count 0 2006.196.08:08:18.96#ibcon#end of sib2, iclass 27, count 0 2006.196.08:08:18.96#ibcon#*after write, iclass 27, count 0 2006.196.08:08:18.96#ibcon#*before return 0, iclass 27, count 0 2006.196.08:08:18.96#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.196.08:08:18.96#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.196.08:08:18.96#ibcon#about to clear, iclass 27 cls_cnt 0 2006.196.08:08:18.96#ibcon#cleared, iclass 27 cls_cnt 0 2006.196.08:08:18.96$vc4f8/va=4,7 2006.196.08:08:18.96#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.196.08:08:18.96#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.196.08:08:18.96#ibcon#ireg 11 cls_cnt 2 2006.196.08:08:18.96#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.196.08:08:19.01#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.196.08:08:19.01#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.196.08:08:19.01#ibcon#enter wrdev, iclass 29, count 2 2006.196.08:08:19.01#ibcon#first serial, iclass 29, count 2 2006.196.08:08:19.01#ibcon#enter sib2, iclass 29, count 2 2006.196.08:08:19.01#ibcon#flushed, iclass 29, count 2 2006.196.08:08:19.01#ibcon#about to write, iclass 29, count 2 2006.196.08:08:19.01#ibcon#wrote, iclass 29, count 2 2006.196.08:08:19.01#ibcon#about to read 3, iclass 29, count 2 2006.196.08:08:19.03#ibcon#read 3, iclass 29, count 2 2006.196.08:08:19.03#ibcon#about to read 4, iclass 29, count 2 2006.196.08:08:19.03#ibcon#read 4, iclass 29, count 2 2006.196.08:08:19.03#ibcon#about to read 5, iclass 29, count 2 2006.196.08:08:19.03#ibcon#read 5, iclass 29, count 2 2006.196.08:08:19.03#ibcon#about to read 6, iclass 29, count 2 2006.196.08:08:19.03#ibcon#read 6, iclass 29, count 2 2006.196.08:08:19.03#ibcon#end of sib2, iclass 29, count 2 2006.196.08:08:19.03#ibcon#*mode == 0, iclass 29, count 2 2006.196.08:08:19.03#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.196.08:08:19.03#ibcon#[25=AT04-07\r\n] 2006.196.08:08:19.03#ibcon#*before write, iclass 29, count 2 2006.196.08:08:19.03#ibcon#enter sib2, iclass 29, count 2 2006.196.08:08:19.03#ibcon#flushed, iclass 29, count 2 2006.196.08:08:19.03#ibcon#about to write, iclass 29, count 2 2006.196.08:08:19.03#ibcon#wrote, iclass 29, count 2 2006.196.08:08:19.03#ibcon#about to read 3, iclass 29, count 2 2006.196.08:08:19.06#ibcon#read 3, iclass 29, count 2 2006.196.08:08:19.06#ibcon#about to read 4, iclass 29, count 2 2006.196.08:08:19.06#ibcon#read 4, iclass 29, count 2 2006.196.08:08:19.06#ibcon#about to read 5, iclass 29, count 2 2006.196.08:08:19.06#ibcon#read 5, iclass 29, count 2 2006.196.08:08:19.06#ibcon#about to read 6, iclass 29, count 2 2006.196.08:08:19.06#ibcon#read 6, iclass 29, count 2 2006.196.08:08:19.06#ibcon#end of sib2, iclass 29, count 2 2006.196.08:08:19.06#ibcon#*after write, iclass 29, count 2 2006.196.08:08:19.06#ibcon#*before return 0, iclass 29, count 2 2006.196.08:08:19.06#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.196.08:08:19.06#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.196.08:08:19.06#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.196.08:08:19.06#ibcon#ireg 7 cls_cnt 0 2006.196.08:08:19.06#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.196.08:08:19.18#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.196.08:08:19.18#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.196.08:08:19.18#ibcon#enter wrdev, iclass 29, count 0 2006.196.08:08:19.18#ibcon#first serial, iclass 29, count 0 2006.196.08:08:19.18#ibcon#enter sib2, iclass 29, count 0 2006.196.08:08:19.18#ibcon#flushed, iclass 29, count 0 2006.196.08:08:19.18#ibcon#about to write, iclass 29, count 0 2006.196.08:08:19.18#ibcon#wrote, iclass 29, count 0 2006.196.08:08:19.18#ibcon#about to read 3, iclass 29, count 0 2006.196.08:08:19.20#ibcon#read 3, iclass 29, count 0 2006.196.08:08:19.20#ibcon#about to read 4, iclass 29, count 0 2006.196.08:08:19.20#ibcon#read 4, iclass 29, count 0 2006.196.08:08:19.20#ibcon#about to read 5, iclass 29, count 0 2006.196.08:08:19.20#ibcon#read 5, iclass 29, count 0 2006.196.08:08:19.20#ibcon#about to read 6, iclass 29, count 0 2006.196.08:08:19.20#ibcon#read 6, iclass 29, count 0 2006.196.08:08:19.20#ibcon#end of sib2, iclass 29, count 0 2006.196.08:08:19.20#ibcon#*mode == 0, iclass 29, count 0 2006.196.08:08:19.20#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.196.08:08:19.20#ibcon#[25=USB\r\n] 2006.196.08:08:19.20#ibcon#*before write, iclass 29, count 0 2006.196.08:08:19.20#ibcon#enter sib2, iclass 29, count 0 2006.196.08:08:19.20#ibcon#flushed, iclass 29, count 0 2006.196.08:08:19.20#ibcon#about to write, iclass 29, count 0 2006.196.08:08:19.20#ibcon#wrote, iclass 29, count 0 2006.196.08:08:19.20#ibcon#about to read 3, iclass 29, count 0 2006.196.08:08:19.23#ibcon#read 3, iclass 29, count 0 2006.196.08:08:19.23#ibcon#about to read 4, iclass 29, count 0 2006.196.08:08:19.23#ibcon#read 4, iclass 29, count 0 2006.196.08:08:19.23#ibcon#about to read 5, iclass 29, count 0 2006.196.08:08:19.23#ibcon#read 5, iclass 29, count 0 2006.196.08:08:19.23#ibcon#about to read 6, iclass 29, count 0 2006.196.08:08:19.23#ibcon#read 6, iclass 29, count 0 2006.196.08:08:19.23#ibcon#end of sib2, iclass 29, count 0 2006.196.08:08:19.23#ibcon#*after write, iclass 29, count 0 2006.196.08:08:19.23#ibcon#*before return 0, iclass 29, count 0 2006.196.08:08:19.23#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.196.08:08:19.23#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.196.08:08:19.23#ibcon#about to clear, iclass 29 cls_cnt 0 2006.196.08:08:19.23#ibcon#cleared, iclass 29 cls_cnt 0 2006.196.08:08:19.23$vc4f8/valo=5,652.99 2006.196.08:08:19.23#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.196.08:08:19.23#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.196.08:08:19.23#ibcon#ireg 17 cls_cnt 0 2006.196.08:08:19.23#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.196.08:08:19.23#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.196.08:08:19.23#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.196.08:08:19.23#ibcon#enter wrdev, iclass 31, count 0 2006.196.08:08:19.23#ibcon#first serial, iclass 31, count 0 2006.196.08:08:19.23#ibcon#enter sib2, iclass 31, count 0 2006.196.08:08:19.23#ibcon#flushed, iclass 31, count 0 2006.196.08:08:19.23#ibcon#about to write, iclass 31, count 0 2006.196.08:08:19.23#ibcon#wrote, iclass 31, count 0 2006.196.08:08:19.23#ibcon#about to read 3, iclass 31, count 0 2006.196.08:08:19.25#ibcon#read 3, iclass 31, count 0 2006.196.08:08:19.25#ibcon#about to read 4, iclass 31, count 0 2006.196.08:08:19.25#ibcon#read 4, iclass 31, count 0 2006.196.08:08:19.25#ibcon#about to read 5, iclass 31, count 0 2006.196.08:08:19.25#ibcon#read 5, iclass 31, count 0 2006.196.08:08:19.25#ibcon#about to read 6, iclass 31, count 0 2006.196.08:08:19.25#ibcon#read 6, iclass 31, count 0 2006.196.08:08:19.25#ibcon#end of sib2, iclass 31, count 0 2006.196.08:08:19.25#ibcon#*mode == 0, iclass 31, count 0 2006.196.08:08:19.25#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.196.08:08:19.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.196.08:08:19.25#ibcon#*before write, iclass 31, count 0 2006.196.08:08:19.25#ibcon#enter sib2, iclass 31, count 0 2006.196.08:08:19.25#ibcon#flushed, iclass 31, count 0 2006.196.08:08:19.25#ibcon#about to write, iclass 31, count 0 2006.196.08:08:19.25#ibcon#wrote, iclass 31, count 0 2006.196.08:08:19.25#ibcon#about to read 3, iclass 31, count 0 2006.196.08:08:19.29#ibcon#read 3, iclass 31, count 0 2006.196.08:08:19.29#ibcon#about to read 4, iclass 31, count 0 2006.196.08:08:19.29#ibcon#read 4, iclass 31, count 0 2006.196.08:08:19.29#ibcon#about to read 5, iclass 31, count 0 2006.196.08:08:19.29#ibcon#read 5, iclass 31, count 0 2006.196.08:08:19.29#ibcon#about to read 6, iclass 31, count 0 2006.196.08:08:19.29#ibcon#read 6, iclass 31, count 0 2006.196.08:08:19.29#ibcon#end of sib2, iclass 31, count 0 2006.196.08:08:19.29#ibcon#*after write, iclass 31, count 0 2006.196.08:08:19.29#ibcon#*before return 0, iclass 31, count 0 2006.196.08:08:19.29#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.196.08:08:19.29#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.196.08:08:19.29#ibcon#about to clear, iclass 31 cls_cnt 0 2006.196.08:08:19.29#ibcon#cleared, iclass 31 cls_cnt 0 2006.196.08:08:19.29$vc4f8/va=5,7 2006.196.08:08:19.29#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.196.08:08:19.29#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.196.08:08:19.29#ibcon#ireg 11 cls_cnt 2 2006.196.08:08:19.29#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.196.08:08:19.35#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.196.08:08:19.35#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.196.08:08:19.35#ibcon#enter wrdev, iclass 33, count 2 2006.196.08:08:19.35#ibcon#first serial, iclass 33, count 2 2006.196.08:08:19.35#ibcon#enter sib2, iclass 33, count 2 2006.196.08:08:19.35#ibcon#flushed, iclass 33, count 2 2006.196.08:08:19.35#ibcon#about to write, iclass 33, count 2 2006.196.08:08:19.35#ibcon#wrote, iclass 33, count 2 2006.196.08:08:19.35#ibcon#about to read 3, iclass 33, count 2 2006.196.08:08:19.37#ibcon#read 3, iclass 33, count 2 2006.196.08:08:19.37#ibcon#about to read 4, iclass 33, count 2 2006.196.08:08:19.37#ibcon#read 4, iclass 33, count 2 2006.196.08:08:19.37#ibcon#about to read 5, iclass 33, count 2 2006.196.08:08:19.37#ibcon#read 5, iclass 33, count 2 2006.196.08:08:19.37#ibcon#about to read 6, iclass 33, count 2 2006.196.08:08:19.37#ibcon#read 6, iclass 33, count 2 2006.196.08:08:19.37#ibcon#end of sib2, iclass 33, count 2 2006.196.08:08:19.37#ibcon#*mode == 0, iclass 33, count 2 2006.196.08:08:19.37#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.196.08:08:19.37#ibcon#[25=AT05-07\r\n] 2006.196.08:08:19.37#ibcon#*before write, iclass 33, count 2 2006.196.08:08:19.37#ibcon#enter sib2, iclass 33, count 2 2006.196.08:08:19.37#ibcon#flushed, iclass 33, count 2 2006.196.08:08:19.37#ibcon#about to write, iclass 33, count 2 2006.196.08:08:19.37#ibcon#wrote, iclass 33, count 2 2006.196.08:08:19.37#ibcon#about to read 3, iclass 33, count 2 2006.196.08:08:19.40#ibcon#read 3, iclass 33, count 2 2006.196.08:08:19.40#ibcon#about to read 4, iclass 33, count 2 2006.196.08:08:19.40#ibcon#read 4, iclass 33, count 2 2006.196.08:08:19.40#ibcon#about to read 5, iclass 33, count 2 2006.196.08:08:19.40#ibcon#read 5, iclass 33, count 2 2006.196.08:08:19.40#ibcon#about to read 6, iclass 33, count 2 2006.196.08:08:19.40#ibcon#read 6, iclass 33, count 2 2006.196.08:08:19.40#ibcon#end of sib2, iclass 33, count 2 2006.196.08:08:19.40#ibcon#*after write, iclass 33, count 2 2006.196.08:08:19.40#ibcon#*before return 0, iclass 33, count 2 2006.196.08:08:19.40#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.196.08:08:19.40#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.196.08:08:19.40#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.196.08:08:19.40#ibcon#ireg 7 cls_cnt 0 2006.196.08:08:19.40#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.196.08:08:19.52#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.196.08:08:19.52#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.196.08:08:19.52#ibcon#enter wrdev, iclass 33, count 0 2006.196.08:08:19.52#ibcon#first serial, iclass 33, count 0 2006.196.08:08:19.52#ibcon#enter sib2, iclass 33, count 0 2006.196.08:08:19.52#ibcon#flushed, iclass 33, count 0 2006.196.08:08:19.52#ibcon#about to write, iclass 33, count 0 2006.196.08:08:19.52#ibcon#wrote, iclass 33, count 0 2006.196.08:08:19.52#ibcon#about to read 3, iclass 33, count 0 2006.196.08:08:19.54#ibcon#read 3, iclass 33, count 0 2006.196.08:08:19.54#ibcon#about to read 4, iclass 33, count 0 2006.196.08:08:19.54#ibcon#read 4, iclass 33, count 0 2006.196.08:08:19.54#ibcon#about to read 5, iclass 33, count 0 2006.196.08:08:19.54#ibcon#read 5, iclass 33, count 0 2006.196.08:08:19.54#ibcon#about to read 6, iclass 33, count 0 2006.196.08:08:19.54#ibcon#read 6, iclass 33, count 0 2006.196.08:08:19.54#ibcon#end of sib2, iclass 33, count 0 2006.196.08:08:19.54#ibcon#*mode == 0, iclass 33, count 0 2006.196.08:08:19.54#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.196.08:08:19.54#ibcon#[25=USB\r\n] 2006.196.08:08:19.54#ibcon#*before write, iclass 33, count 0 2006.196.08:08:19.54#ibcon#enter sib2, iclass 33, count 0 2006.196.08:08:19.54#ibcon#flushed, iclass 33, count 0 2006.196.08:08:19.54#ibcon#about to write, iclass 33, count 0 2006.196.08:08:19.54#ibcon#wrote, iclass 33, count 0 2006.196.08:08:19.54#ibcon#about to read 3, iclass 33, count 0 2006.196.08:08:19.57#ibcon#read 3, iclass 33, count 0 2006.196.08:08:19.57#ibcon#about to read 4, iclass 33, count 0 2006.196.08:08:19.57#ibcon#read 4, iclass 33, count 0 2006.196.08:08:19.57#ibcon#about to read 5, iclass 33, count 0 2006.196.08:08:19.57#ibcon#read 5, iclass 33, count 0 2006.196.08:08:19.57#ibcon#about to read 6, iclass 33, count 0 2006.196.08:08:19.57#ibcon#read 6, iclass 33, count 0 2006.196.08:08:19.57#ibcon#end of sib2, iclass 33, count 0 2006.196.08:08:19.57#ibcon#*after write, iclass 33, count 0 2006.196.08:08:19.57#ibcon#*before return 0, iclass 33, count 0 2006.196.08:08:19.57#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.196.08:08:19.57#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.196.08:08:19.57#ibcon#about to clear, iclass 33 cls_cnt 0 2006.196.08:08:19.57#ibcon#cleared, iclass 33 cls_cnt 0 2006.196.08:08:19.57$vc4f8/valo=6,772.99 2006.196.08:08:19.57#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.196.08:08:19.57#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.196.08:08:19.57#ibcon#ireg 17 cls_cnt 0 2006.196.08:08:19.57#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.196.08:08:19.57#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.196.08:08:19.57#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.196.08:08:19.57#ibcon#enter wrdev, iclass 35, count 0 2006.196.08:08:19.57#ibcon#first serial, iclass 35, count 0 2006.196.08:08:19.57#ibcon#enter sib2, iclass 35, count 0 2006.196.08:08:19.57#ibcon#flushed, iclass 35, count 0 2006.196.08:08:19.57#ibcon#about to write, iclass 35, count 0 2006.196.08:08:19.57#ibcon#wrote, iclass 35, count 0 2006.196.08:08:19.57#ibcon#about to read 3, iclass 35, count 0 2006.196.08:08:19.59#ibcon#read 3, iclass 35, count 0 2006.196.08:08:19.59#ibcon#about to read 4, iclass 35, count 0 2006.196.08:08:19.59#ibcon#read 4, iclass 35, count 0 2006.196.08:08:19.59#ibcon#about to read 5, iclass 35, count 0 2006.196.08:08:19.59#ibcon#read 5, iclass 35, count 0 2006.196.08:08:19.59#ibcon#about to read 6, iclass 35, count 0 2006.196.08:08:19.59#ibcon#read 6, iclass 35, count 0 2006.196.08:08:19.59#ibcon#end of sib2, iclass 35, count 0 2006.196.08:08:19.59#ibcon#*mode == 0, iclass 35, count 0 2006.196.08:08:19.59#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.196.08:08:19.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.196.08:08:19.59#ibcon#*before write, iclass 35, count 0 2006.196.08:08:19.59#ibcon#enter sib2, iclass 35, count 0 2006.196.08:08:19.59#ibcon#flushed, iclass 35, count 0 2006.196.08:08:19.59#ibcon#about to write, iclass 35, count 0 2006.196.08:08:19.59#ibcon#wrote, iclass 35, count 0 2006.196.08:08:19.59#ibcon#about to read 3, iclass 35, count 0 2006.196.08:08:19.64#ibcon#read 3, iclass 35, count 0 2006.196.08:08:19.64#ibcon#about to read 4, iclass 35, count 0 2006.196.08:08:19.64#ibcon#read 4, iclass 35, count 0 2006.196.08:08:19.64#ibcon#about to read 5, iclass 35, count 0 2006.196.08:08:19.64#ibcon#read 5, iclass 35, count 0 2006.196.08:08:19.64#ibcon#about to read 6, iclass 35, count 0 2006.196.08:08:19.64#ibcon#read 6, iclass 35, count 0 2006.196.08:08:19.64#ibcon#end of sib2, iclass 35, count 0 2006.196.08:08:19.64#ibcon#*after write, iclass 35, count 0 2006.196.08:08:19.64#ibcon#*before return 0, iclass 35, count 0 2006.196.08:08:19.64#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.196.08:08:19.64#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.196.08:08:19.64#ibcon#about to clear, iclass 35 cls_cnt 0 2006.196.08:08:19.64#ibcon#cleared, iclass 35 cls_cnt 0 2006.196.08:08:19.64$vc4f8/va=6,6 2006.196.08:08:19.64#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.196.08:08:19.64#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.196.08:08:19.64#ibcon#ireg 11 cls_cnt 2 2006.196.08:08:19.64#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.196.08:08:19.69#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.196.08:08:19.69#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.196.08:08:19.69#ibcon#enter wrdev, iclass 37, count 2 2006.196.08:08:19.69#ibcon#first serial, iclass 37, count 2 2006.196.08:08:19.69#ibcon#enter sib2, iclass 37, count 2 2006.196.08:08:19.69#ibcon#flushed, iclass 37, count 2 2006.196.08:08:19.69#ibcon#about to write, iclass 37, count 2 2006.196.08:08:19.69#ibcon#wrote, iclass 37, count 2 2006.196.08:08:19.69#ibcon#about to read 3, iclass 37, count 2 2006.196.08:08:19.71#ibcon#read 3, iclass 37, count 2 2006.196.08:08:19.71#ibcon#about to read 4, iclass 37, count 2 2006.196.08:08:19.71#ibcon#read 4, iclass 37, count 2 2006.196.08:08:19.71#ibcon#about to read 5, iclass 37, count 2 2006.196.08:08:19.71#ibcon#read 5, iclass 37, count 2 2006.196.08:08:19.71#ibcon#about to read 6, iclass 37, count 2 2006.196.08:08:19.71#ibcon#read 6, iclass 37, count 2 2006.196.08:08:19.71#ibcon#end of sib2, iclass 37, count 2 2006.196.08:08:19.71#ibcon#*mode == 0, iclass 37, count 2 2006.196.08:08:19.71#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.196.08:08:19.71#ibcon#[25=AT06-06\r\n] 2006.196.08:08:19.71#ibcon#*before write, iclass 37, count 2 2006.196.08:08:19.71#ibcon#enter sib2, iclass 37, count 2 2006.196.08:08:19.71#ibcon#flushed, iclass 37, count 2 2006.196.08:08:19.71#ibcon#about to write, iclass 37, count 2 2006.196.08:08:19.71#ibcon#wrote, iclass 37, count 2 2006.196.08:08:19.71#ibcon#about to read 3, iclass 37, count 2 2006.196.08:08:19.74#ibcon#read 3, iclass 37, count 2 2006.196.08:08:19.74#ibcon#about to read 4, iclass 37, count 2 2006.196.08:08:19.74#ibcon#read 4, iclass 37, count 2 2006.196.08:08:19.74#ibcon#about to read 5, iclass 37, count 2 2006.196.08:08:19.74#ibcon#read 5, iclass 37, count 2 2006.196.08:08:19.74#ibcon#about to read 6, iclass 37, count 2 2006.196.08:08:19.74#ibcon#read 6, iclass 37, count 2 2006.196.08:08:19.74#ibcon#end of sib2, iclass 37, count 2 2006.196.08:08:19.74#ibcon#*after write, iclass 37, count 2 2006.196.08:08:19.74#ibcon#*before return 0, iclass 37, count 2 2006.196.08:08:19.74#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.196.08:08:19.74#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.196.08:08:19.74#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.196.08:08:19.74#ibcon#ireg 7 cls_cnt 0 2006.196.08:08:19.74#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.196.08:08:19.86#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.196.08:08:19.86#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.196.08:08:19.86#ibcon#enter wrdev, iclass 37, count 0 2006.196.08:08:19.86#ibcon#first serial, iclass 37, count 0 2006.196.08:08:19.86#ibcon#enter sib2, iclass 37, count 0 2006.196.08:08:19.86#ibcon#flushed, iclass 37, count 0 2006.196.08:08:19.86#ibcon#about to write, iclass 37, count 0 2006.196.08:08:19.86#ibcon#wrote, iclass 37, count 0 2006.196.08:08:19.86#ibcon#about to read 3, iclass 37, count 0 2006.196.08:08:19.88#ibcon#read 3, iclass 37, count 0 2006.196.08:08:19.88#ibcon#about to read 4, iclass 37, count 0 2006.196.08:08:19.88#ibcon#read 4, iclass 37, count 0 2006.196.08:08:19.88#ibcon#about to read 5, iclass 37, count 0 2006.196.08:08:19.88#ibcon#read 5, iclass 37, count 0 2006.196.08:08:19.88#ibcon#about to read 6, iclass 37, count 0 2006.196.08:08:19.88#ibcon#read 6, iclass 37, count 0 2006.196.08:08:19.88#ibcon#end of sib2, iclass 37, count 0 2006.196.08:08:19.88#ibcon#*mode == 0, iclass 37, count 0 2006.196.08:08:19.88#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.196.08:08:19.88#ibcon#[25=USB\r\n] 2006.196.08:08:19.88#ibcon#*before write, iclass 37, count 0 2006.196.08:08:19.88#ibcon#enter sib2, iclass 37, count 0 2006.196.08:08:19.88#ibcon#flushed, iclass 37, count 0 2006.196.08:08:19.88#ibcon#about to write, iclass 37, count 0 2006.196.08:08:19.88#ibcon#wrote, iclass 37, count 0 2006.196.08:08:19.88#ibcon#about to read 3, iclass 37, count 0 2006.196.08:08:19.91#ibcon#read 3, iclass 37, count 0 2006.196.08:08:19.91#ibcon#about to read 4, iclass 37, count 0 2006.196.08:08:19.91#ibcon#read 4, iclass 37, count 0 2006.196.08:08:19.91#ibcon#about to read 5, iclass 37, count 0 2006.196.08:08:19.91#ibcon#read 5, iclass 37, count 0 2006.196.08:08:19.91#ibcon#about to read 6, iclass 37, count 0 2006.196.08:08:19.91#ibcon#read 6, iclass 37, count 0 2006.196.08:08:19.91#ibcon#end of sib2, iclass 37, count 0 2006.196.08:08:19.91#ibcon#*after write, iclass 37, count 0 2006.196.08:08:19.91#ibcon#*before return 0, iclass 37, count 0 2006.196.08:08:19.91#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.196.08:08:19.91#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.196.08:08:19.91#ibcon#about to clear, iclass 37 cls_cnt 0 2006.196.08:08:19.91#ibcon#cleared, iclass 37 cls_cnt 0 2006.196.08:08:19.91$vc4f8/valo=7,832.99 2006.196.08:08:19.91#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.196.08:08:19.91#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.196.08:08:19.91#ibcon#ireg 17 cls_cnt 0 2006.196.08:08:19.91#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.196.08:08:19.91#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.196.08:08:19.91#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.196.08:08:19.91#ibcon#enter wrdev, iclass 39, count 0 2006.196.08:08:19.91#ibcon#first serial, iclass 39, count 0 2006.196.08:08:19.91#ibcon#enter sib2, iclass 39, count 0 2006.196.08:08:19.91#ibcon#flushed, iclass 39, count 0 2006.196.08:08:19.91#ibcon#about to write, iclass 39, count 0 2006.196.08:08:19.91#ibcon#wrote, iclass 39, count 0 2006.196.08:08:19.91#ibcon#about to read 3, iclass 39, count 0 2006.196.08:08:19.93#ibcon#read 3, iclass 39, count 0 2006.196.08:08:19.93#ibcon#about to read 4, iclass 39, count 0 2006.196.08:08:19.93#ibcon#read 4, iclass 39, count 0 2006.196.08:08:19.93#ibcon#about to read 5, iclass 39, count 0 2006.196.08:08:19.93#ibcon#read 5, iclass 39, count 0 2006.196.08:08:19.93#ibcon#about to read 6, iclass 39, count 0 2006.196.08:08:19.93#ibcon#read 6, iclass 39, count 0 2006.196.08:08:19.93#ibcon#end of sib2, iclass 39, count 0 2006.196.08:08:19.93#ibcon#*mode == 0, iclass 39, count 0 2006.196.08:08:19.93#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.196.08:08:19.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.196.08:08:19.93#ibcon#*before write, iclass 39, count 0 2006.196.08:08:19.93#ibcon#enter sib2, iclass 39, count 0 2006.196.08:08:19.93#ibcon#flushed, iclass 39, count 0 2006.196.08:08:19.93#ibcon#about to write, iclass 39, count 0 2006.196.08:08:19.93#ibcon#wrote, iclass 39, count 0 2006.196.08:08:19.93#ibcon#about to read 3, iclass 39, count 0 2006.196.08:08:19.97#ibcon#read 3, iclass 39, count 0 2006.196.08:08:19.97#ibcon#about to read 4, iclass 39, count 0 2006.196.08:08:19.97#ibcon#read 4, iclass 39, count 0 2006.196.08:08:19.97#ibcon#about to read 5, iclass 39, count 0 2006.196.08:08:19.97#ibcon#read 5, iclass 39, count 0 2006.196.08:08:19.97#ibcon#about to read 6, iclass 39, count 0 2006.196.08:08:19.97#ibcon#read 6, iclass 39, count 0 2006.196.08:08:19.97#ibcon#end of sib2, iclass 39, count 0 2006.196.08:08:19.97#ibcon#*after write, iclass 39, count 0 2006.196.08:08:19.97#ibcon#*before return 0, iclass 39, count 0 2006.196.08:08:19.97#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.196.08:08:19.97#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.196.08:08:19.97#ibcon#about to clear, iclass 39 cls_cnt 0 2006.196.08:08:19.97#ibcon#cleared, iclass 39 cls_cnt 0 2006.196.08:08:19.97$vc4f8/va=7,6 2006.196.08:08:19.97#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.196.08:08:19.97#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.196.08:08:19.97#ibcon#ireg 11 cls_cnt 2 2006.196.08:08:19.97#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.196.08:08:20.03#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.196.08:08:20.03#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.196.08:08:20.03#ibcon#enter wrdev, iclass 3, count 2 2006.196.08:08:20.03#ibcon#first serial, iclass 3, count 2 2006.196.08:08:20.03#ibcon#enter sib2, iclass 3, count 2 2006.196.08:08:20.03#ibcon#flushed, iclass 3, count 2 2006.196.08:08:20.03#ibcon#about to write, iclass 3, count 2 2006.196.08:08:20.03#ibcon#wrote, iclass 3, count 2 2006.196.08:08:20.03#ibcon#about to read 3, iclass 3, count 2 2006.196.08:08:20.05#ibcon#read 3, iclass 3, count 2 2006.196.08:08:20.05#ibcon#about to read 4, iclass 3, count 2 2006.196.08:08:20.05#ibcon#read 4, iclass 3, count 2 2006.196.08:08:20.05#ibcon#about to read 5, iclass 3, count 2 2006.196.08:08:20.05#ibcon#read 5, iclass 3, count 2 2006.196.08:08:20.05#ibcon#about to read 6, iclass 3, count 2 2006.196.08:08:20.05#ibcon#read 6, iclass 3, count 2 2006.196.08:08:20.05#ibcon#end of sib2, iclass 3, count 2 2006.196.08:08:20.05#ibcon#*mode == 0, iclass 3, count 2 2006.196.08:08:20.05#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.196.08:08:20.05#ibcon#[25=AT07-06\r\n] 2006.196.08:08:20.05#ibcon#*before write, iclass 3, count 2 2006.196.08:08:20.05#ibcon#enter sib2, iclass 3, count 2 2006.196.08:08:20.05#ibcon#flushed, iclass 3, count 2 2006.196.08:08:20.05#ibcon#about to write, iclass 3, count 2 2006.196.08:08:20.05#ibcon#wrote, iclass 3, count 2 2006.196.08:08:20.05#ibcon#about to read 3, iclass 3, count 2 2006.196.08:08:20.08#ibcon#read 3, iclass 3, count 2 2006.196.08:08:20.08#ibcon#about to read 4, iclass 3, count 2 2006.196.08:08:20.08#ibcon#read 4, iclass 3, count 2 2006.196.08:08:20.08#ibcon#about to read 5, iclass 3, count 2 2006.196.08:08:20.08#ibcon#read 5, iclass 3, count 2 2006.196.08:08:20.08#ibcon#about to read 6, iclass 3, count 2 2006.196.08:08:20.08#ibcon#read 6, iclass 3, count 2 2006.196.08:08:20.08#ibcon#end of sib2, iclass 3, count 2 2006.196.08:08:20.08#ibcon#*after write, iclass 3, count 2 2006.196.08:08:20.08#ibcon#*before return 0, iclass 3, count 2 2006.196.08:08:20.08#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.196.08:08:20.08#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.196.08:08:20.08#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.196.08:08:20.08#ibcon#ireg 7 cls_cnt 0 2006.196.08:08:20.08#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.196.08:08:20.20#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.196.08:08:20.20#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.196.08:08:20.20#ibcon#enter wrdev, iclass 3, count 0 2006.196.08:08:20.20#ibcon#first serial, iclass 3, count 0 2006.196.08:08:20.20#ibcon#enter sib2, iclass 3, count 0 2006.196.08:08:20.20#ibcon#flushed, iclass 3, count 0 2006.196.08:08:20.20#ibcon#about to write, iclass 3, count 0 2006.196.08:08:20.20#ibcon#wrote, iclass 3, count 0 2006.196.08:08:20.20#ibcon#about to read 3, iclass 3, count 0 2006.196.08:08:20.22#ibcon#read 3, iclass 3, count 0 2006.196.08:08:20.22#ibcon#about to read 4, iclass 3, count 0 2006.196.08:08:20.22#ibcon#read 4, iclass 3, count 0 2006.196.08:08:20.22#ibcon#about to read 5, iclass 3, count 0 2006.196.08:08:20.22#ibcon#read 5, iclass 3, count 0 2006.196.08:08:20.22#ibcon#about to read 6, iclass 3, count 0 2006.196.08:08:20.22#ibcon#read 6, iclass 3, count 0 2006.196.08:08:20.22#ibcon#end of sib2, iclass 3, count 0 2006.196.08:08:20.22#ibcon#*mode == 0, iclass 3, count 0 2006.196.08:08:20.22#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.196.08:08:20.22#ibcon#[25=USB\r\n] 2006.196.08:08:20.22#ibcon#*before write, iclass 3, count 0 2006.196.08:08:20.22#ibcon#enter sib2, iclass 3, count 0 2006.196.08:08:20.22#ibcon#flushed, iclass 3, count 0 2006.196.08:08:20.22#ibcon#about to write, iclass 3, count 0 2006.196.08:08:20.22#ibcon#wrote, iclass 3, count 0 2006.196.08:08:20.22#ibcon#about to read 3, iclass 3, count 0 2006.196.08:08:20.25#ibcon#read 3, iclass 3, count 0 2006.196.08:08:20.25#ibcon#about to read 4, iclass 3, count 0 2006.196.08:08:20.25#ibcon#read 4, iclass 3, count 0 2006.196.08:08:20.25#ibcon#about to read 5, iclass 3, count 0 2006.196.08:08:20.25#ibcon#read 5, iclass 3, count 0 2006.196.08:08:20.25#ibcon#about to read 6, iclass 3, count 0 2006.196.08:08:20.25#ibcon#read 6, iclass 3, count 0 2006.196.08:08:20.25#ibcon#end of sib2, iclass 3, count 0 2006.196.08:08:20.25#ibcon#*after write, iclass 3, count 0 2006.196.08:08:20.25#ibcon#*before return 0, iclass 3, count 0 2006.196.08:08:20.25#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.196.08:08:20.25#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.196.08:08:20.25#ibcon#about to clear, iclass 3 cls_cnt 0 2006.196.08:08:20.25#ibcon#cleared, iclass 3 cls_cnt 0 2006.196.08:08:20.25$vc4f8/valo=8,852.99 2006.196.08:08:20.25#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.196.08:08:20.25#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.196.08:08:20.25#ibcon#ireg 17 cls_cnt 0 2006.196.08:08:20.25#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.196.08:08:20.25#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.196.08:08:20.25#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.196.08:08:20.25#ibcon#enter wrdev, iclass 5, count 0 2006.196.08:08:20.25#ibcon#first serial, iclass 5, count 0 2006.196.08:08:20.25#ibcon#enter sib2, iclass 5, count 0 2006.196.08:08:20.25#ibcon#flushed, iclass 5, count 0 2006.196.08:08:20.25#ibcon#about to write, iclass 5, count 0 2006.196.08:08:20.25#ibcon#wrote, iclass 5, count 0 2006.196.08:08:20.25#ibcon#about to read 3, iclass 5, count 0 2006.196.08:08:20.27#ibcon#read 3, iclass 5, count 0 2006.196.08:08:20.27#ibcon#about to read 4, iclass 5, count 0 2006.196.08:08:20.27#ibcon#read 4, iclass 5, count 0 2006.196.08:08:20.27#ibcon#about to read 5, iclass 5, count 0 2006.196.08:08:20.27#ibcon#read 5, iclass 5, count 0 2006.196.08:08:20.27#ibcon#about to read 6, iclass 5, count 0 2006.196.08:08:20.27#ibcon#read 6, iclass 5, count 0 2006.196.08:08:20.27#ibcon#end of sib2, iclass 5, count 0 2006.196.08:08:20.27#ibcon#*mode == 0, iclass 5, count 0 2006.196.08:08:20.27#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.196.08:08:20.27#ibcon#[26=FRQ=08,852.99\r\n] 2006.196.08:08:20.27#ibcon#*before write, iclass 5, count 0 2006.196.08:08:20.27#ibcon#enter sib2, iclass 5, count 0 2006.196.08:08:20.27#ibcon#flushed, iclass 5, count 0 2006.196.08:08:20.27#ibcon#about to write, iclass 5, count 0 2006.196.08:08:20.27#ibcon#wrote, iclass 5, count 0 2006.196.08:08:20.27#ibcon#about to read 3, iclass 5, count 0 2006.196.08:08:20.31#ibcon#read 3, iclass 5, count 0 2006.196.08:08:20.31#ibcon#about to read 4, iclass 5, count 0 2006.196.08:08:20.31#ibcon#read 4, iclass 5, count 0 2006.196.08:08:20.31#ibcon#about to read 5, iclass 5, count 0 2006.196.08:08:20.31#ibcon#read 5, iclass 5, count 0 2006.196.08:08:20.31#ibcon#about to read 6, iclass 5, count 0 2006.196.08:08:20.31#ibcon#read 6, iclass 5, count 0 2006.196.08:08:20.31#ibcon#end of sib2, iclass 5, count 0 2006.196.08:08:20.31#ibcon#*after write, iclass 5, count 0 2006.196.08:08:20.31#ibcon#*before return 0, iclass 5, count 0 2006.196.08:08:20.31#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.196.08:08:20.31#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.196.08:08:20.31#ibcon#about to clear, iclass 5 cls_cnt 0 2006.196.08:08:20.31#ibcon#cleared, iclass 5 cls_cnt 0 2006.196.08:08:20.31$vc4f8/va=8,7 2006.196.08:08:20.31#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.196.08:08:20.31#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.196.08:08:20.31#ibcon#ireg 11 cls_cnt 2 2006.196.08:08:20.31#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.196.08:08:20.37#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.196.08:08:20.37#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.196.08:08:20.37#ibcon#enter wrdev, iclass 7, count 2 2006.196.08:08:20.37#ibcon#first serial, iclass 7, count 2 2006.196.08:08:20.37#ibcon#enter sib2, iclass 7, count 2 2006.196.08:08:20.37#ibcon#flushed, iclass 7, count 2 2006.196.08:08:20.37#ibcon#about to write, iclass 7, count 2 2006.196.08:08:20.37#ibcon#wrote, iclass 7, count 2 2006.196.08:08:20.37#ibcon#about to read 3, iclass 7, count 2 2006.196.08:08:20.39#ibcon#read 3, iclass 7, count 2 2006.196.08:08:20.39#ibcon#about to read 4, iclass 7, count 2 2006.196.08:08:20.39#ibcon#read 4, iclass 7, count 2 2006.196.08:08:20.39#ibcon#about to read 5, iclass 7, count 2 2006.196.08:08:20.39#ibcon#read 5, iclass 7, count 2 2006.196.08:08:20.39#ibcon#about to read 6, iclass 7, count 2 2006.196.08:08:20.39#ibcon#read 6, iclass 7, count 2 2006.196.08:08:20.39#ibcon#end of sib2, iclass 7, count 2 2006.196.08:08:20.39#ibcon#*mode == 0, iclass 7, count 2 2006.196.08:08:20.39#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.196.08:08:20.39#ibcon#[25=AT08-07\r\n] 2006.196.08:08:20.39#ibcon#*before write, iclass 7, count 2 2006.196.08:08:20.39#ibcon#enter sib2, iclass 7, count 2 2006.196.08:08:20.39#ibcon#flushed, iclass 7, count 2 2006.196.08:08:20.39#ibcon#about to write, iclass 7, count 2 2006.196.08:08:20.39#ibcon#wrote, iclass 7, count 2 2006.196.08:08:20.39#ibcon#about to read 3, iclass 7, count 2 2006.196.08:08:20.42#ibcon#read 3, iclass 7, count 2 2006.196.08:08:20.42#ibcon#about to read 4, iclass 7, count 2 2006.196.08:08:20.42#ibcon#read 4, iclass 7, count 2 2006.196.08:08:20.42#ibcon#about to read 5, iclass 7, count 2 2006.196.08:08:20.42#ibcon#read 5, iclass 7, count 2 2006.196.08:08:20.42#ibcon#about to read 6, iclass 7, count 2 2006.196.08:08:20.42#ibcon#read 6, iclass 7, count 2 2006.196.08:08:20.42#ibcon#end of sib2, iclass 7, count 2 2006.196.08:08:20.42#ibcon#*after write, iclass 7, count 2 2006.196.08:08:20.42#ibcon#*before return 0, iclass 7, count 2 2006.196.08:08:20.42#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.196.08:08:20.42#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.196.08:08:20.42#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.196.08:08:20.42#ibcon#ireg 7 cls_cnt 0 2006.196.08:08:20.42#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.196.08:08:20.54#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.196.08:08:20.54#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.196.08:08:20.54#ibcon#enter wrdev, iclass 7, count 0 2006.196.08:08:20.54#ibcon#first serial, iclass 7, count 0 2006.196.08:08:20.54#ibcon#enter sib2, iclass 7, count 0 2006.196.08:08:20.54#ibcon#flushed, iclass 7, count 0 2006.196.08:08:20.54#ibcon#about to write, iclass 7, count 0 2006.196.08:08:20.54#ibcon#wrote, iclass 7, count 0 2006.196.08:08:20.54#ibcon#about to read 3, iclass 7, count 0 2006.196.08:08:20.56#ibcon#read 3, iclass 7, count 0 2006.196.08:08:20.56#ibcon#about to read 4, iclass 7, count 0 2006.196.08:08:20.56#ibcon#read 4, iclass 7, count 0 2006.196.08:08:20.56#ibcon#about to read 5, iclass 7, count 0 2006.196.08:08:20.56#ibcon#read 5, iclass 7, count 0 2006.196.08:08:20.56#ibcon#about to read 6, iclass 7, count 0 2006.196.08:08:20.56#ibcon#read 6, iclass 7, count 0 2006.196.08:08:20.56#ibcon#end of sib2, iclass 7, count 0 2006.196.08:08:20.56#ibcon#*mode == 0, iclass 7, count 0 2006.196.08:08:20.56#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.196.08:08:20.56#ibcon#[25=USB\r\n] 2006.196.08:08:20.56#ibcon#*before write, iclass 7, count 0 2006.196.08:08:20.56#ibcon#enter sib2, iclass 7, count 0 2006.196.08:08:20.56#ibcon#flushed, iclass 7, count 0 2006.196.08:08:20.56#ibcon#about to write, iclass 7, count 0 2006.196.08:08:20.56#ibcon#wrote, iclass 7, count 0 2006.196.08:08:20.56#ibcon#about to read 3, iclass 7, count 0 2006.196.08:08:20.59#ibcon#read 3, iclass 7, count 0 2006.196.08:08:20.59#ibcon#about to read 4, iclass 7, count 0 2006.196.08:08:20.59#ibcon#read 4, iclass 7, count 0 2006.196.08:08:20.59#ibcon#about to read 5, iclass 7, count 0 2006.196.08:08:20.59#ibcon#read 5, iclass 7, count 0 2006.196.08:08:20.59#ibcon#about to read 6, iclass 7, count 0 2006.196.08:08:20.59#ibcon#read 6, iclass 7, count 0 2006.196.08:08:20.59#ibcon#end of sib2, iclass 7, count 0 2006.196.08:08:20.59#ibcon#*after write, iclass 7, count 0 2006.196.08:08:20.59#ibcon#*before return 0, iclass 7, count 0 2006.196.08:08:20.59#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.196.08:08:20.59#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.196.08:08:20.59#ibcon#about to clear, iclass 7 cls_cnt 0 2006.196.08:08:20.59#ibcon#cleared, iclass 7 cls_cnt 0 2006.196.08:08:20.59$vc4f8/vblo=1,632.99 2006.196.08:08:20.59#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.196.08:08:20.59#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.196.08:08:20.59#ibcon#ireg 17 cls_cnt 0 2006.196.08:08:20.59#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.196.08:08:20.59#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.196.08:08:20.59#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.196.08:08:20.59#ibcon#enter wrdev, iclass 11, count 0 2006.196.08:08:20.59#ibcon#first serial, iclass 11, count 0 2006.196.08:08:20.59#ibcon#enter sib2, iclass 11, count 0 2006.196.08:08:20.59#ibcon#flushed, iclass 11, count 0 2006.196.08:08:20.59#ibcon#about to write, iclass 11, count 0 2006.196.08:08:20.59#ibcon#wrote, iclass 11, count 0 2006.196.08:08:20.59#ibcon#about to read 3, iclass 11, count 0 2006.196.08:08:20.61#ibcon#read 3, iclass 11, count 0 2006.196.08:08:20.61#ibcon#about to read 4, iclass 11, count 0 2006.196.08:08:20.61#ibcon#read 4, iclass 11, count 0 2006.196.08:08:20.61#ibcon#about to read 5, iclass 11, count 0 2006.196.08:08:20.61#ibcon#read 5, iclass 11, count 0 2006.196.08:08:20.61#ibcon#about to read 6, iclass 11, count 0 2006.196.08:08:20.61#ibcon#read 6, iclass 11, count 0 2006.196.08:08:20.61#ibcon#end of sib2, iclass 11, count 0 2006.196.08:08:20.61#ibcon#*mode == 0, iclass 11, count 0 2006.196.08:08:20.61#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.196.08:08:20.61#ibcon#[28=FRQ=01,632.99\r\n] 2006.196.08:08:20.61#ibcon#*before write, iclass 11, count 0 2006.196.08:08:20.61#ibcon#enter sib2, iclass 11, count 0 2006.196.08:08:20.61#ibcon#flushed, iclass 11, count 0 2006.196.08:08:20.61#ibcon#about to write, iclass 11, count 0 2006.196.08:08:20.61#ibcon#wrote, iclass 11, count 0 2006.196.08:08:20.61#ibcon#about to read 3, iclass 11, count 0 2006.196.08:08:20.65#ibcon#read 3, iclass 11, count 0 2006.196.08:08:20.65#ibcon#about to read 4, iclass 11, count 0 2006.196.08:08:20.65#ibcon#read 4, iclass 11, count 0 2006.196.08:08:20.65#ibcon#about to read 5, iclass 11, count 0 2006.196.08:08:20.65#ibcon#read 5, iclass 11, count 0 2006.196.08:08:20.65#ibcon#about to read 6, iclass 11, count 0 2006.196.08:08:20.65#ibcon#read 6, iclass 11, count 0 2006.196.08:08:20.65#ibcon#end of sib2, iclass 11, count 0 2006.196.08:08:20.65#ibcon#*after write, iclass 11, count 0 2006.196.08:08:20.65#ibcon#*before return 0, iclass 11, count 0 2006.196.08:08:20.65#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.196.08:08:20.65#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.196.08:08:20.65#ibcon#about to clear, iclass 11 cls_cnt 0 2006.196.08:08:20.65#ibcon#cleared, iclass 11 cls_cnt 0 2006.196.08:08:20.65$vc4f8/vb=1,4 2006.196.08:08:20.65#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.196.08:08:20.65#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.196.08:08:20.65#ibcon#ireg 11 cls_cnt 2 2006.196.08:08:20.65#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.196.08:08:20.65#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.196.08:08:20.65#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.196.08:08:20.65#ibcon#enter wrdev, iclass 13, count 2 2006.196.08:08:20.65#ibcon#first serial, iclass 13, count 2 2006.196.08:08:20.65#ibcon#enter sib2, iclass 13, count 2 2006.196.08:08:20.65#ibcon#flushed, iclass 13, count 2 2006.196.08:08:20.65#ibcon#about to write, iclass 13, count 2 2006.196.08:08:20.65#ibcon#wrote, iclass 13, count 2 2006.196.08:08:20.65#ibcon#about to read 3, iclass 13, count 2 2006.196.08:08:20.67#ibcon#read 3, iclass 13, count 2 2006.196.08:08:20.67#ibcon#about to read 4, iclass 13, count 2 2006.196.08:08:20.67#ibcon#read 4, iclass 13, count 2 2006.196.08:08:20.67#ibcon#about to read 5, iclass 13, count 2 2006.196.08:08:20.67#ibcon#read 5, iclass 13, count 2 2006.196.08:08:20.67#ibcon#about to read 6, iclass 13, count 2 2006.196.08:08:20.67#ibcon#read 6, iclass 13, count 2 2006.196.08:08:20.67#ibcon#end of sib2, iclass 13, count 2 2006.196.08:08:20.67#ibcon#*mode == 0, iclass 13, count 2 2006.196.08:08:20.67#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.196.08:08:20.67#ibcon#[27=AT01-04\r\n] 2006.196.08:08:20.67#ibcon#*before write, iclass 13, count 2 2006.196.08:08:20.67#ibcon#enter sib2, iclass 13, count 2 2006.196.08:08:20.67#ibcon#flushed, iclass 13, count 2 2006.196.08:08:20.67#ibcon#about to write, iclass 13, count 2 2006.196.08:08:20.67#ibcon#wrote, iclass 13, count 2 2006.196.08:08:20.67#ibcon#about to read 3, iclass 13, count 2 2006.196.08:08:20.70#ibcon#read 3, iclass 13, count 2 2006.196.08:08:20.70#ibcon#about to read 4, iclass 13, count 2 2006.196.08:08:20.70#ibcon#read 4, iclass 13, count 2 2006.196.08:08:20.70#ibcon#about to read 5, iclass 13, count 2 2006.196.08:08:20.70#ibcon#read 5, iclass 13, count 2 2006.196.08:08:20.70#ibcon#about to read 6, iclass 13, count 2 2006.196.08:08:20.70#ibcon#read 6, iclass 13, count 2 2006.196.08:08:20.70#ibcon#end of sib2, iclass 13, count 2 2006.196.08:08:20.70#ibcon#*after write, iclass 13, count 2 2006.196.08:08:20.70#ibcon#*before return 0, iclass 13, count 2 2006.196.08:08:20.70#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.196.08:08:20.70#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.196.08:08:20.70#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.196.08:08:20.70#ibcon#ireg 7 cls_cnt 0 2006.196.08:08:20.70#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.196.08:08:20.82#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.196.08:08:20.82#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.196.08:08:20.82#ibcon#enter wrdev, iclass 13, count 0 2006.196.08:08:20.82#ibcon#first serial, iclass 13, count 0 2006.196.08:08:20.82#ibcon#enter sib2, iclass 13, count 0 2006.196.08:08:20.82#ibcon#flushed, iclass 13, count 0 2006.196.08:08:20.82#ibcon#about to write, iclass 13, count 0 2006.196.08:08:20.82#ibcon#wrote, iclass 13, count 0 2006.196.08:08:20.82#ibcon#about to read 3, iclass 13, count 0 2006.196.08:08:20.84#ibcon#read 3, iclass 13, count 0 2006.196.08:08:20.84#ibcon#about to read 4, iclass 13, count 0 2006.196.08:08:20.84#ibcon#read 4, iclass 13, count 0 2006.196.08:08:20.84#ibcon#about to read 5, iclass 13, count 0 2006.196.08:08:20.84#ibcon#read 5, iclass 13, count 0 2006.196.08:08:20.84#ibcon#about to read 6, iclass 13, count 0 2006.196.08:08:20.84#ibcon#read 6, iclass 13, count 0 2006.196.08:08:20.84#ibcon#end of sib2, iclass 13, count 0 2006.196.08:08:20.84#ibcon#*mode == 0, iclass 13, count 0 2006.196.08:08:20.84#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.196.08:08:20.84#ibcon#[27=USB\r\n] 2006.196.08:08:20.84#ibcon#*before write, iclass 13, count 0 2006.196.08:08:20.84#ibcon#enter sib2, iclass 13, count 0 2006.196.08:08:20.84#ibcon#flushed, iclass 13, count 0 2006.196.08:08:20.84#ibcon#about to write, iclass 13, count 0 2006.196.08:08:20.84#ibcon#wrote, iclass 13, count 0 2006.196.08:08:20.84#ibcon#about to read 3, iclass 13, count 0 2006.196.08:08:20.87#ibcon#read 3, iclass 13, count 0 2006.196.08:08:20.87#ibcon#about to read 4, iclass 13, count 0 2006.196.08:08:20.87#ibcon#read 4, iclass 13, count 0 2006.196.08:08:20.87#ibcon#about to read 5, iclass 13, count 0 2006.196.08:08:20.87#ibcon#read 5, iclass 13, count 0 2006.196.08:08:20.87#ibcon#about to read 6, iclass 13, count 0 2006.196.08:08:20.87#ibcon#read 6, iclass 13, count 0 2006.196.08:08:20.87#ibcon#end of sib2, iclass 13, count 0 2006.196.08:08:20.87#ibcon#*after write, iclass 13, count 0 2006.196.08:08:20.87#ibcon#*before return 0, iclass 13, count 0 2006.196.08:08:20.87#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.196.08:08:20.87#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.196.08:08:20.87#ibcon#about to clear, iclass 13 cls_cnt 0 2006.196.08:08:20.87#ibcon#cleared, iclass 13 cls_cnt 0 2006.196.08:08:20.87$vc4f8/vblo=2,640.99 2006.196.08:08:20.87#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.196.08:08:20.87#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.196.08:08:20.87#ibcon#ireg 17 cls_cnt 0 2006.196.08:08:20.87#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.196.08:08:20.87#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.196.08:08:20.87#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.196.08:08:20.87#ibcon#enter wrdev, iclass 15, count 0 2006.196.08:08:20.87#ibcon#first serial, iclass 15, count 0 2006.196.08:08:20.87#ibcon#enter sib2, iclass 15, count 0 2006.196.08:08:20.87#ibcon#flushed, iclass 15, count 0 2006.196.08:08:20.87#ibcon#about to write, iclass 15, count 0 2006.196.08:08:20.87#ibcon#wrote, iclass 15, count 0 2006.196.08:08:20.87#ibcon#about to read 3, iclass 15, count 0 2006.196.08:08:20.89#ibcon#read 3, iclass 15, count 0 2006.196.08:08:20.89#ibcon#about to read 4, iclass 15, count 0 2006.196.08:08:20.89#ibcon#read 4, iclass 15, count 0 2006.196.08:08:20.89#ibcon#about to read 5, iclass 15, count 0 2006.196.08:08:20.89#ibcon#read 5, iclass 15, count 0 2006.196.08:08:20.89#ibcon#about to read 6, iclass 15, count 0 2006.196.08:08:20.89#ibcon#read 6, iclass 15, count 0 2006.196.08:08:20.89#ibcon#end of sib2, iclass 15, count 0 2006.196.08:08:20.89#ibcon#*mode == 0, iclass 15, count 0 2006.196.08:08:20.89#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.196.08:08:20.89#ibcon#[28=FRQ=02,640.99\r\n] 2006.196.08:08:20.89#ibcon#*before write, iclass 15, count 0 2006.196.08:08:20.89#ibcon#enter sib2, iclass 15, count 0 2006.196.08:08:20.89#ibcon#flushed, iclass 15, count 0 2006.196.08:08:20.89#ibcon#about to write, iclass 15, count 0 2006.196.08:08:20.89#ibcon#wrote, iclass 15, count 0 2006.196.08:08:20.89#ibcon#about to read 3, iclass 15, count 0 2006.196.08:08:20.93#ibcon#read 3, iclass 15, count 0 2006.196.08:08:20.93#ibcon#about to read 4, iclass 15, count 0 2006.196.08:08:20.93#ibcon#read 4, iclass 15, count 0 2006.196.08:08:20.93#ibcon#about to read 5, iclass 15, count 0 2006.196.08:08:20.93#ibcon#read 5, iclass 15, count 0 2006.196.08:08:20.93#ibcon#about to read 6, iclass 15, count 0 2006.196.08:08:20.93#ibcon#read 6, iclass 15, count 0 2006.196.08:08:20.93#ibcon#end of sib2, iclass 15, count 0 2006.196.08:08:20.93#ibcon#*after write, iclass 15, count 0 2006.196.08:08:20.93#ibcon#*before return 0, iclass 15, count 0 2006.196.08:08:20.93#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.196.08:08:20.93#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.196.08:08:20.93#ibcon#about to clear, iclass 15 cls_cnt 0 2006.196.08:08:20.93#ibcon#cleared, iclass 15 cls_cnt 0 2006.196.08:08:20.93$vc4f8/vb=2,4 2006.196.08:08:20.93#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.196.08:08:20.93#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.196.08:08:20.93#ibcon#ireg 11 cls_cnt 2 2006.196.08:08:20.93#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.196.08:08:20.99#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.196.08:08:20.99#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.196.08:08:20.99#ibcon#enter wrdev, iclass 17, count 2 2006.196.08:08:20.99#ibcon#first serial, iclass 17, count 2 2006.196.08:08:20.99#ibcon#enter sib2, iclass 17, count 2 2006.196.08:08:20.99#ibcon#flushed, iclass 17, count 2 2006.196.08:08:20.99#ibcon#about to write, iclass 17, count 2 2006.196.08:08:20.99#ibcon#wrote, iclass 17, count 2 2006.196.08:08:20.99#ibcon#about to read 3, iclass 17, count 2 2006.196.08:08:21.01#ibcon#read 3, iclass 17, count 2 2006.196.08:08:21.01#ibcon#about to read 4, iclass 17, count 2 2006.196.08:08:21.01#ibcon#read 4, iclass 17, count 2 2006.196.08:08:21.01#ibcon#about to read 5, iclass 17, count 2 2006.196.08:08:21.01#ibcon#read 5, iclass 17, count 2 2006.196.08:08:21.01#ibcon#about to read 6, iclass 17, count 2 2006.196.08:08:21.01#ibcon#read 6, iclass 17, count 2 2006.196.08:08:21.01#ibcon#end of sib2, iclass 17, count 2 2006.196.08:08:21.01#ibcon#*mode == 0, iclass 17, count 2 2006.196.08:08:21.01#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.196.08:08:21.01#ibcon#[27=AT02-04\r\n] 2006.196.08:08:21.01#ibcon#*before write, iclass 17, count 2 2006.196.08:08:21.01#ibcon#enter sib2, iclass 17, count 2 2006.196.08:08:21.01#ibcon#flushed, iclass 17, count 2 2006.196.08:08:21.01#ibcon#about to write, iclass 17, count 2 2006.196.08:08:21.01#ibcon#wrote, iclass 17, count 2 2006.196.08:08:21.01#ibcon#about to read 3, iclass 17, count 2 2006.196.08:08:21.04#ibcon#read 3, iclass 17, count 2 2006.196.08:08:21.04#ibcon#about to read 4, iclass 17, count 2 2006.196.08:08:21.04#ibcon#read 4, iclass 17, count 2 2006.196.08:08:21.04#ibcon#about to read 5, iclass 17, count 2 2006.196.08:08:21.04#ibcon#read 5, iclass 17, count 2 2006.196.08:08:21.04#ibcon#about to read 6, iclass 17, count 2 2006.196.08:08:21.04#ibcon#read 6, iclass 17, count 2 2006.196.08:08:21.04#ibcon#end of sib2, iclass 17, count 2 2006.196.08:08:21.04#ibcon#*after write, iclass 17, count 2 2006.196.08:08:21.04#ibcon#*before return 0, iclass 17, count 2 2006.196.08:08:21.04#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.196.08:08:21.04#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.196.08:08:21.04#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.196.08:08:21.04#ibcon#ireg 7 cls_cnt 0 2006.196.08:08:21.04#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.196.08:08:21.16#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.196.08:08:21.16#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.196.08:08:21.16#ibcon#enter wrdev, iclass 17, count 0 2006.196.08:08:21.16#ibcon#first serial, iclass 17, count 0 2006.196.08:08:21.16#ibcon#enter sib2, iclass 17, count 0 2006.196.08:08:21.16#ibcon#flushed, iclass 17, count 0 2006.196.08:08:21.16#ibcon#about to write, iclass 17, count 0 2006.196.08:08:21.16#ibcon#wrote, iclass 17, count 0 2006.196.08:08:21.16#ibcon#about to read 3, iclass 17, count 0 2006.196.08:08:21.18#ibcon#read 3, iclass 17, count 0 2006.196.08:08:21.18#ibcon#about to read 4, iclass 17, count 0 2006.196.08:08:21.18#ibcon#read 4, iclass 17, count 0 2006.196.08:08:21.18#ibcon#about to read 5, iclass 17, count 0 2006.196.08:08:21.18#ibcon#read 5, iclass 17, count 0 2006.196.08:08:21.18#ibcon#about to read 6, iclass 17, count 0 2006.196.08:08:21.18#ibcon#read 6, iclass 17, count 0 2006.196.08:08:21.18#ibcon#end of sib2, iclass 17, count 0 2006.196.08:08:21.18#ibcon#*mode == 0, iclass 17, count 0 2006.196.08:08:21.18#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.196.08:08:21.18#ibcon#[27=USB\r\n] 2006.196.08:08:21.18#ibcon#*before write, iclass 17, count 0 2006.196.08:08:21.18#ibcon#enter sib2, iclass 17, count 0 2006.196.08:08:21.18#ibcon#flushed, iclass 17, count 0 2006.196.08:08:21.18#ibcon#about to write, iclass 17, count 0 2006.196.08:08:21.18#ibcon#wrote, iclass 17, count 0 2006.196.08:08:21.18#ibcon#about to read 3, iclass 17, count 0 2006.196.08:08:21.21#ibcon#read 3, iclass 17, count 0 2006.196.08:08:21.21#ibcon#about to read 4, iclass 17, count 0 2006.196.08:08:21.21#ibcon#read 4, iclass 17, count 0 2006.196.08:08:21.21#ibcon#about to read 5, iclass 17, count 0 2006.196.08:08:21.21#ibcon#read 5, iclass 17, count 0 2006.196.08:08:21.21#ibcon#about to read 6, iclass 17, count 0 2006.196.08:08:21.21#ibcon#read 6, iclass 17, count 0 2006.196.08:08:21.21#ibcon#end of sib2, iclass 17, count 0 2006.196.08:08:21.21#ibcon#*after write, iclass 17, count 0 2006.196.08:08:21.21#ibcon#*before return 0, iclass 17, count 0 2006.196.08:08:21.21#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.196.08:08:21.21#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.196.08:08:21.21#ibcon#about to clear, iclass 17 cls_cnt 0 2006.196.08:08:21.21#ibcon#cleared, iclass 17 cls_cnt 0 2006.196.08:08:21.21$vc4f8/vblo=3,656.99 2006.196.08:08:21.21#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.196.08:08:21.21#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.196.08:08:21.21#ibcon#ireg 17 cls_cnt 0 2006.196.08:08:21.21#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.196.08:08:21.21#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.196.08:08:21.21#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.196.08:08:21.21#ibcon#enter wrdev, iclass 19, count 0 2006.196.08:08:21.21#ibcon#first serial, iclass 19, count 0 2006.196.08:08:21.21#ibcon#enter sib2, iclass 19, count 0 2006.196.08:08:21.21#ibcon#flushed, iclass 19, count 0 2006.196.08:08:21.21#ibcon#about to write, iclass 19, count 0 2006.196.08:08:21.21#ibcon#wrote, iclass 19, count 0 2006.196.08:08:21.21#ibcon#about to read 3, iclass 19, count 0 2006.196.08:08:21.23#ibcon#read 3, iclass 19, count 0 2006.196.08:08:21.23#ibcon#about to read 4, iclass 19, count 0 2006.196.08:08:21.23#ibcon#read 4, iclass 19, count 0 2006.196.08:08:21.23#ibcon#about to read 5, iclass 19, count 0 2006.196.08:08:21.23#ibcon#read 5, iclass 19, count 0 2006.196.08:08:21.23#ibcon#about to read 6, iclass 19, count 0 2006.196.08:08:21.23#ibcon#read 6, iclass 19, count 0 2006.196.08:08:21.23#ibcon#end of sib2, iclass 19, count 0 2006.196.08:08:21.23#ibcon#*mode == 0, iclass 19, count 0 2006.196.08:08:21.23#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.196.08:08:21.23#ibcon#[28=FRQ=03,656.99\r\n] 2006.196.08:08:21.23#ibcon#*before write, iclass 19, count 0 2006.196.08:08:21.23#ibcon#enter sib2, iclass 19, count 0 2006.196.08:08:21.23#ibcon#flushed, iclass 19, count 0 2006.196.08:08:21.23#ibcon#about to write, iclass 19, count 0 2006.196.08:08:21.23#ibcon#wrote, iclass 19, count 0 2006.196.08:08:21.23#ibcon#about to read 3, iclass 19, count 0 2006.196.08:08:21.27#ibcon#read 3, iclass 19, count 0 2006.196.08:08:21.27#ibcon#about to read 4, iclass 19, count 0 2006.196.08:08:21.27#ibcon#read 4, iclass 19, count 0 2006.196.08:08:21.27#ibcon#about to read 5, iclass 19, count 0 2006.196.08:08:21.27#ibcon#read 5, iclass 19, count 0 2006.196.08:08:21.27#ibcon#about to read 6, iclass 19, count 0 2006.196.08:08:21.27#ibcon#read 6, iclass 19, count 0 2006.196.08:08:21.27#ibcon#end of sib2, iclass 19, count 0 2006.196.08:08:21.27#ibcon#*after write, iclass 19, count 0 2006.196.08:08:21.27#ibcon#*before return 0, iclass 19, count 0 2006.196.08:08:21.27#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.196.08:08:21.27#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.196.08:08:21.27#ibcon#about to clear, iclass 19 cls_cnt 0 2006.196.08:08:21.27#ibcon#cleared, iclass 19 cls_cnt 0 2006.196.08:08:21.27$vc4f8/vb=3,4 2006.196.08:08:21.27#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.196.08:08:21.27#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.196.08:08:21.27#ibcon#ireg 11 cls_cnt 2 2006.196.08:08:21.27#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.196.08:08:21.33#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.196.08:08:21.33#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.196.08:08:21.33#ibcon#enter wrdev, iclass 21, count 2 2006.196.08:08:21.33#ibcon#first serial, iclass 21, count 2 2006.196.08:08:21.33#ibcon#enter sib2, iclass 21, count 2 2006.196.08:08:21.33#ibcon#flushed, iclass 21, count 2 2006.196.08:08:21.33#ibcon#about to write, iclass 21, count 2 2006.196.08:08:21.33#ibcon#wrote, iclass 21, count 2 2006.196.08:08:21.33#ibcon#about to read 3, iclass 21, count 2 2006.196.08:08:21.35#ibcon#read 3, iclass 21, count 2 2006.196.08:08:21.35#ibcon#about to read 4, iclass 21, count 2 2006.196.08:08:21.35#ibcon#read 4, iclass 21, count 2 2006.196.08:08:21.35#ibcon#about to read 5, iclass 21, count 2 2006.196.08:08:21.35#ibcon#read 5, iclass 21, count 2 2006.196.08:08:21.35#ibcon#about to read 6, iclass 21, count 2 2006.196.08:08:21.35#ibcon#read 6, iclass 21, count 2 2006.196.08:08:21.35#ibcon#end of sib2, iclass 21, count 2 2006.196.08:08:21.35#ibcon#*mode == 0, iclass 21, count 2 2006.196.08:08:21.35#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.196.08:08:21.35#ibcon#[27=AT03-04\r\n] 2006.196.08:08:21.35#ibcon#*before write, iclass 21, count 2 2006.196.08:08:21.35#ibcon#enter sib2, iclass 21, count 2 2006.196.08:08:21.35#ibcon#flushed, iclass 21, count 2 2006.196.08:08:21.35#ibcon#about to write, iclass 21, count 2 2006.196.08:08:21.35#ibcon#wrote, iclass 21, count 2 2006.196.08:08:21.35#ibcon#about to read 3, iclass 21, count 2 2006.196.08:08:21.38#ibcon#read 3, iclass 21, count 2 2006.196.08:08:21.38#ibcon#about to read 4, iclass 21, count 2 2006.196.08:08:21.38#ibcon#read 4, iclass 21, count 2 2006.196.08:08:21.38#ibcon#about to read 5, iclass 21, count 2 2006.196.08:08:21.38#ibcon#read 5, iclass 21, count 2 2006.196.08:08:21.38#ibcon#about to read 6, iclass 21, count 2 2006.196.08:08:21.38#ibcon#read 6, iclass 21, count 2 2006.196.08:08:21.38#ibcon#end of sib2, iclass 21, count 2 2006.196.08:08:21.38#ibcon#*after write, iclass 21, count 2 2006.196.08:08:21.38#ibcon#*before return 0, iclass 21, count 2 2006.196.08:08:21.38#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.196.08:08:21.38#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.196.08:08:21.38#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.196.08:08:21.38#ibcon#ireg 7 cls_cnt 0 2006.196.08:08:21.38#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.196.08:08:21.50#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.196.08:08:21.50#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.196.08:08:21.50#ibcon#enter wrdev, iclass 21, count 0 2006.196.08:08:21.50#ibcon#first serial, iclass 21, count 0 2006.196.08:08:21.50#ibcon#enter sib2, iclass 21, count 0 2006.196.08:08:21.50#ibcon#flushed, iclass 21, count 0 2006.196.08:08:21.50#ibcon#about to write, iclass 21, count 0 2006.196.08:08:21.50#ibcon#wrote, iclass 21, count 0 2006.196.08:08:21.50#ibcon#about to read 3, iclass 21, count 0 2006.196.08:08:21.52#ibcon#read 3, iclass 21, count 0 2006.196.08:08:21.52#ibcon#about to read 4, iclass 21, count 0 2006.196.08:08:21.52#ibcon#read 4, iclass 21, count 0 2006.196.08:08:21.52#ibcon#about to read 5, iclass 21, count 0 2006.196.08:08:21.52#ibcon#read 5, iclass 21, count 0 2006.196.08:08:21.52#ibcon#about to read 6, iclass 21, count 0 2006.196.08:08:21.52#ibcon#read 6, iclass 21, count 0 2006.196.08:08:21.52#ibcon#end of sib2, iclass 21, count 0 2006.196.08:08:21.52#ibcon#*mode == 0, iclass 21, count 0 2006.196.08:08:21.52#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.196.08:08:21.52#ibcon#[27=USB\r\n] 2006.196.08:08:21.52#ibcon#*before write, iclass 21, count 0 2006.196.08:08:21.52#ibcon#enter sib2, iclass 21, count 0 2006.196.08:08:21.52#ibcon#flushed, iclass 21, count 0 2006.196.08:08:21.52#ibcon#about to write, iclass 21, count 0 2006.196.08:08:21.52#ibcon#wrote, iclass 21, count 0 2006.196.08:08:21.52#ibcon#about to read 3, iclass 21, count 0 2006.196.08:08:21.55#ibcon#read 3, iclass 21, count 0 2006.196.08:08:21.55#ibcon#about to read 4, iclass 21, count 0 2006.196.08:08:21.55#ibcon#read 4, iclass 21, count 0 2006.196.08:08:21.55#ibcon#about to read 5, iclass 21, count 0 2006.196.08:08:21.55#ibcon#read 5, iclass 21, count 0 2006.196.08:08:21.55#ibcon#about to read 6, iclass 21, count 0 2006.196.08:08:21.55#ibcon#read 6, iclass 21, count 0 2006.196.08:08:21.55#ibcon#end of sib2, iclass 21, count 0 2006.196.08:08:21.55#ibcon#*after write, iclass 21, count 0 2006.196.08:08:21.55#ibcon#*before return 0, iclass 21, count 0 2006.196.08:08:21.55#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.196.08:08:21.55#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.196.08:08:21.55#ibcon#about to clear, iclass 21 cls_cnt 0 2006.196.08:08:21.55#ibcon#cleared, iclass 21 cls_cnt 0 2006.196.08:08:21.55$vc4f8/vblo=4,712.99 2006.196.08:08:21.55#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.196.08:08:21.55#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.196.08:08:21.55#ibcon#ireg 17 cls_cnt 0 2006.196.08:08:21.55#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.196.08:08:21.55#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.196.08:08:21.55#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.196.08:08:21.55#ibcon#enter wrdev, iclass 23, count 0 2006.196.08:08:21.55#ibcon#first serial, iclass 23, count 0 2006.196.08:08:21.55#ibcon#enter sib2, iclass 23, count 0 2006.196.08:08:21.55#ibcon#flushed, iclass 23, count 0 2006.196.08:08:21.55#ibcon#about to write, iclass 23, count 0 2006.196.08:08:21.55#ibcon#wrote, iclass 23, count 0 2006.196.08:08:21.55#ibcon#about to read 3, iclass 23, count 0 2006.196.08:08:21.57#ibcon#read 3, iclass 23, count 0 2006.196.08:08:21.57#ibcon#about to read 4, iclass 23, count 0 2006.196.08:08:21.57#ibcon#read 4, iclass 23, count 0 2006.196.08:08:21.57#ibcon#about to read 5, iclass 23, count 0 2006.196.08:08:21.57#ibcon#read 5, iclass 23, count 0 2006.196.08:08:21.57#ibcon#about to read 6, iclass 23, count 0 2006.196.08:08:21.57#ibcon#read 6, iclass 23, count 0 2006.196.08:08:21.57#ibcon#end of sib2, iclass 23, count 0 2006.196.08:08:21.57#ibcon#*mode == 0, iclass 23, count 0 2006.196.08:08:21.57#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.196.08:08:21.57#ibcon#[28=FRQ=04,712.99\r\n] 2006.196.08:08:21.57#ibcon#*before write, iclass 23, count 0 2006.196.08:08:21.57#ibcon#enter sib2, iclass 23, count 0 2006.196.08:08:21.57#ibcon#flushed, iclass 23, count 0 2006.196.08:08:21.57#ibcon#about to write, iclass 23, count 0 2006.196.08:08:21.57#ibcon#wrote, iclass 23, count 0 2006.196.08:08:21.57#ibcon#about to read 3, iclass 23, count 0 2006.196.08:08:21.61#ibcon#read 3, iclass 23, count 0 2006.196.08:08:21.61#ibcon#about to read 4, iclass 23, count 0 2006.196.08:08:21.61#ibcon#read 4, iclass 23, count 0 2006.196.08:08:21.61#ibcon#about to read 5, iclass 23, count 0 2006.196.08:08:21.61#ibcon#read 5, iclass 23, count 0 2006.196.08:08:21.61#ibcon#about to read 6, iclass 23, count 0 2006.196.08:08:21.61#ibcon#read 6, iclass 23, count 0 2006.196.08:08:21.61#ibcon#end of sib2, iclass 23, count 0 2006.196.08:08:21.61#ibcon#*after write, iclass 23, count 0 2006.196.08:08:21.61#ibcon#*before return 0, iclass 23, count 0 2006.196.08:08:21.61#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.196.08:08:21.61#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.196.08:08:21.61#ibcon#about to clear, iclass 23 cls_cnt 0 2006.196.08:08:21.61#ibcon#cleared, iclass 23 cls_cnt 0 2006.196.08:08:21.61$vc4f8/vb=4,4 2006.196.08:08:21.61#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.196.08:08:21.61#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.196.08:08:21.61#ibcon#ireg 11 cls_cnt 2 2006.196.08:08:21.61#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.196.08:08:21.67#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.196.08:08:21.67#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.196.08:08:21.67#ibcon#enter wrdev, iclass 25, count 2 2006.196.08:08:21.67#ibcon#first serial, iclass 25, count 2 2006.196.08:08:21.67#ibcon#enter sib2, iclass 25, count 2 2006.196.08:08:21.67#ibcon#flushed, iclass 25, count 2 2006.196.08:08:21.67#ibcon#about to write, iclass 25, count 2 2006.196.08:08:21.67#ibcon#wrote, iclass 25, count 2 2006.196.08:08:21.67#ibcon#about to read 3, iclass 25, count 2 2006.196.08:08:21.69#ibcon#read 3, iclass 25, count 2 2006.196.08:08:21.69#ibcon#about to read 4, iclass 25, count 2 2006.196.08:08:21.69#ibcon#read 4, iclass 25, count 2 2006.196.08:08:21.69#ibcon#about to read 5, iclass 25, count 2 2006.196.08:08:21.69#ibcon#read 5, iclass 25, count 2 2006.196.08:08:21.69#ibcon#about to read 6, iclass 25, count 2 2006.196.08:08:21.69#ibcon#read 6, iclass 25, count 2 2006.196.08:08:21.69#ibcon#end of sib2, iclass 25, count 2 2006.196.08:08:21.69#ibcon#*mode == 0, iclass 25, count 2 2006.196.08:08:21.69#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.196.08:08:21.69#ibcon#[27=AT04-04\r\n] 2006.196.08:08:21.69#ibcon#*before write, iclass 25, count 2 2006.196.08:08:21.69#ibcon#enter sib2, iclass 25, count 2 2006.196.08:08:21.69#ibcon#flushed, iclass 25, count 2 2006.196.08:08:21.69#ibcon#about to write, iclass 25, count 2 2006.196.08:08:21.69#ibcon#wrote, iclass 25, count 2 2006.196.08:08:21.69#ibcon#about to read 3, iclass 25, count 2 2006.196.08:08:21.72#ibcon#read 3, iclass 25, count 2 2006.196.08:08:21.72#ibcon#about to read 4, iclass 25, count 2 2006.196.08:08:21.72#ibcon#read 4, iclass 25, count 2 2006.196.08:08:21.72#ibcon#about to read 5, iclass 25, count 2 2006.196.08:08:21.72#ibcon#read 5, iclass 25, count 2 2006.196.08:08:21.72#ibcon#about to read 6, iclass 25, count 2 2006.196.08:08:21.72#ibcon#read 6, iclass 25, count 2 2006.196.08:08:21.72#ibcon#end of sib2, iclass 25, count 2 2006.196.08:08:21.72#ibcon#*after write, iclass 25, count 2 2006.196.08:08:21.72#ibcon#*before return 0, iclass 25, count 2 2006.196.08:08:21.72#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.196.08:08:21.72#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.196.08:08:21.72#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.196.08:08:21.72#ibcon#ireg 7 cls_cnt 0 2006.196.08:08:21.72#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.196.08:08:21.84#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.196.08:08:21.84#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.196.08:08:21.84#ibcon#enter wrdev, iclass 25, count 0 2006.196.08:08:21.84#ibcon#first serial, iclass 25, count 0 2006.196.08:08:21.84#ibcon#enter sib2, iclass 25, count 0 2006.196.08:08:21.84#ibcon#flushed, iclass 25, count 0 2006.196.08:08:21.84#ibcon#about to write, iclass 25, count 0 2006.196.08:08:21.84#ibcon#wrote, iclass 25, count 0 2006.196.08:08:21.84#ibcon#about to read 3, iclass 25, count 0 2006.196.08:08:21.86#ibcon#read 3, iclass 25, count 0 2006.196.08:08:21.86#ibcon#about to read 4, iclass 25, count 0 2006.196.08:08:21.86#ibcon#read 4, iclass 25, count 0 2006.196.08:08:21.86#ibcon#about to read 5, iclass 25, count 0 2006.196.08:08:21.86#ibcon#read 5, iclass 25, count 0 2006.196.08:08:21.86#ibcon#about to read 6, iclass 25, count 0 2006.196.08:08:21.86#ibcon#read 6, iclass 25, count 0 2006.196.08:08:21.86#ibcon#end of sib2, iclass 25, count 0 2006.196.08:08:21.86#ibcon#*mode == 0, iclass 25, count 0 2006.196.08:08:21.86#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.196.08:08:21.86#ibcon#[27=USB\r\n] 2006.196.08:08:21.86#ibcon#*before write, iclass 25, count 0 2006.196.08:08:21.86#ibcon#enter sib2, iclass 25, count 0 2006.196.08:08:21.86#ibcon#flushed, iclass 25, count 0 2006.196.08:08:21.86#ibcon#about to write, iclass 25, count 0 2006.196.08:08:21.86#ibcon#wrote, iclass 25, count 0 2006.196.08:08:21.86#ibcon#about to read 3, iclass 25, count 0 2006.196.08:08:21.89#ibcon#read 3, iclass 25, count 0 2006.196.08:08:21.89#ibcon#about to read 4, iclass 25, count 0 2006.196.08:08:21.89#ibcon#read 4, iclass 25, count 0 2006.196.08:08:21.89#ibcon#about to read 5, iclass 25, count 0 2006.196.08:08:21.89#ibcon#read 5, iclass 25, count 0 2006.196.08:08:21.89#ibcon#about to read 6, iclass 25, count 0 2006.196.08:08:21.89#ibcon#read 6, iclass 25, count 0 2006.196.08:08:21.89#ibcon#end of sib2, iclass 25, count 0 2006.196.08:08:21.89#ibcon#*after write, iclass 25, count 0 2006.196.08:08:21.89#ibcon#*before return 0, iclass 25, count 0 2006.196.08:08:21.89#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.196.08:08:21.89#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.196.08:08:21.89#ibcon#about to clear, iclass 25 cls_cnt 0 2006.196.08:08:21.89#ibcon#cleared, iclass 25 cls_cnt 0 2006.196.08:08:21.89$vc4f8/vblo=5,744.99 2006.196.08:08:21.89#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.196.08:08:21.89#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.196.08:08:21.89#ibcon#ireg 17 cls_cnt 0 2006.196.08:08:21.89#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.196.08:08:21.89#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.196.08:08:21.89#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.196.08:08:21.89#ibcon#enter wrdev, iclass 27, count 0 2006.196.08:08:21.89#ibcon#first serial, iclass 27, count 0 2006.196.08:08:21.89#ibcon#enter sib2, iclass 27, count 0 2006.196.08:08:21.89#ibcon#flushed, iclass 27, count 0 2006.196.08:08:21.89#ibcon#about to write, iclass 27, count 0 2006.196.08:08:21.89#ibcon#wrote, iclass 27, count 0 2006.196.08:08:21.89#ibcon#about to read 3, iclass 27, count 0 2006.196.08:08:21.91#ibcon#read 3, iclass 27, count 0 2006.196.08:08:21.91#ibcon#about to read 4, iclass 27, count 0 2006.196.08:08:21.91#ibcon#read 4, iclass 27, count 0 2006.196.08:08:21.91#ibcon#about to read 5, iclass 27, count 0 2006.196.08:08:21.91#ibcon#read 5, iclass 27, count 0 2006.196.08:08:21.91#ibcon#about to read 6, iclass 27, count 0 2006.196.08:08:21.91#ibcon#read 6, iclass 27, count 0 2006.196.08:08:21.91#ibcon#end of sib2, iclass 27, count 0 2006.196.08:08:21.91#ibcon#*mode == 0, iclass 27, count 0 2006.196.08:08:21.91#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.196.08:08:21.91#ibcon#[28=FRQ=05,744.99\r\n] 2006.196.08:08:21.91#ibcon#*before write, iclass 27, count 0 2006.196.08:08:21.91#ibcon#enter sib2, iclass 27, count 0 2006.196.08:08:21.91#ibcon#flushed, iclass 27, count 0 2006.196.08:08:21.91#ibcon#about to write, iclass 27, count 0 2006.196.08:08:21.91#ibcon#wrote, iclass 27, count 0 2006.196.08:08:21.91#ibcon#about to read 3, iclass 27, count 0 2006.196.08:08:21.96#ibcon#read 3, iclass 27, count 0 2006.196.08:08:21.96#ibcon#about to read 4, iclass 27, count 0 2006.196.08:08:21.96#ibcon#read 4, iclass 27, count 0 2006.196.08:08:21.96#ibcon#about to read 5, iclass 27, count 0 2006.196.08:08:21.96#ibcon#read 5, iclass 27, count 0 2006.196.08:08:21.96#ibcon#about to read 6, iclass 27, count 0 2006.196.08:08:21.96#ibcon#read 6, iclass 27, count 0 2006.196.08:08:21.96#ibcon#end of sib2, iclass 27, count 0 2006.196.08:08:21.96#ibcon#*after write, iclass 27, count 0 2006.196.08:08:21.96#ibcon#*before return 0, iclass 27, count 0 2006.196.08:08:21.96#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.196.08:08:21.96#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.196.08:08:21.96#ibcon#about to clear, iclass 27 cls_cnt 0 2006.196.08:08:21.96#ibcon#cleared, iclass 27 cls_cnt 0 2006.196.08:08:21.96$vc4f8/vb=5,4 2006.196.08:08:21.96#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.196.08:08:21.96#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.196.08:08:21.96#ibcon#ireg 11 cls_cnt 2 2006.196.08:08:21.96#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.196.08:08:22.01#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.196.08:08:22.01#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.196.08:08:22.01#ibcon#enter wrdev, iclass 29, count 2 2006.196.08:08:22.01#ibcon#first serial, iclass 29, count 2 2006.196.08:08:22.01#ibcon#enter sib2, iclass 29, count 2 2006.196.08:08:22.01#ibcon#flushed, iclass 29, count 2 2006.196.08:08:22.01#ibcon#about to write, iclass 29, count 2 2006.196.08:08:22.01#ibcon#wrote, iclass 29, count 2 2006.196.08:08:22.01#ibcon#about to read 3, iclass 29, count 2 2006.196.08:08:22.03#ibcon#read 3, iclass 29, count 2 2006.196.08:08:22.03#ibcon#about to read 4, iclass 29, count 2 2006.196.08:08:22.03#ibcon#read 4, iclass 29, count 2 2006.196.08:08:22.03#ibcon#about to read 5, iclass 29, count 2 2006.196.08:08:22.03#ibcon#read 5, iclass 29, count 2 2006.196.08:08:22.03#ibcon#about to read 6, iclass 29, count 2 2006.196.08:08:22.03#ibcon#read 6, iclass 29, count 2 2006.196.08:08:22.03#ibcon#end of sib2, iclass 29, count 2 2006.196.08:08:22.03#ibcon#*mode == 0, iclass 29, count 2 2006.196.08:08:22.03#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.196.08:08:22.03#ibcon#[27=AT05-04\r\n] 2006.196.08:08:22.03#ibcon#*before write, iclass 29, count 2 2006.196.08:08:22.03#ibcon#enter sib2, iclass 29, count 2 2006.196.08:08:22.03#ibcon#flushed, iclass 29, count 2 2006.196.08:08:22.03#ibcon#about to write, iclass 29, count 2 2006.196.08:08:22.03#ibcon#wrote, iclass 29, count 2 2006.196.08:08:22.03#ibcon#about to read 3, iclass 29, count 2 2006.196.08:08:22.06#ibcon#read 3, iclass 29, count 2 2006.196.08:08:22.06#ibcon#about to read 4, iclass 29, count 2 2006.196.08:08:22.06#ibcon#read 4, iclass 29, count 2 2006.196.08:08:22.06#ibcon#about to read 5, iclass 29, count 2 2006.196.08:08:22.06#ibcon#read 5, iclass 29, count 2 2006.196.08:08:22.06#ibcon#about to read 6, iclass 29, count 2 2006.196.08:08:22.06#ibcon#read 6, iclass 29, count 2 2006.196.08:08:22.06#ibcon#end of sib2, iclass 29, count 2 2006.196.08:08:22.06#ibcon#*after write, iclass 29, count 2 2006.196.08:08:22.06#ibcon#*before return 0, iclass 29, count 2 2006.196.08:08:22.06#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.196.08:08:22.06#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.196.08:08:22.06#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.196.08:08:22.06#ibcon#ireg 7 cls_cnt 0 2006.196.08:08:22.06#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.196.08:08:22.18#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.196.08:08:22.18#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.196.08:08:22.18#ibcon#enter wrdev, iclass 29, count 0 2006.196.08:08:22.18#ibcon#first serial, iclass 29, count 0 2006.196.08:08:22.18#ibcon#enter sib2, iclass 29, count 0 2006.196.08:08:22.18#ibcon#flushed, iclass 29, count 0 2006.196.08:08:22.18#ibcon#about to write, iclass 29, count 0 2006.196.08:08:22.18#ibcon#wrote, iclass 29, count 0 2006.196.08:08:22.18#ibcon#about to read 3, iclass 29, count 0 2006.196.08:08:22.20#ibcon#read 3, iclass 29, count 0 2006.196.08:08:22.20#ibcon#about to read 4, iclass 29, count 0 2006.196.08:08:22.20#ibcon#read 4, iclass 29, count 0 2006.196.08:08:22.20#ibcon#about to read 5, iclass 29, count 0 2006.196.08:08:22.20#ibcon#read 5, iclass 29, count 0 2006.196.08:08:22.20#ibcon#about to read 6, iclass 29, count 0 2006.196.08:08:22.20#ibcon#read 6, iclass 29, count 0 2006.196.08:08:22.20#ibcon#end of sib2, iclass 29, count 0 2006.196.08:08:22.20#ibcon#*mode == 0, iclass 29, count 0 2006.196.08:08:22.20#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.196.08:08:22.20#ibcon#[27=USB\r\n] 2006.196.08:08:22.20#ibcon#*before write, iclass 29, count 0 2006.196.08:08:22.20#ibcon#enter sib2, iclass 29, count 0 2006.196.08:08:22.20#ibcon#flushed, iclass 29, count 0 2006.196.08:08:22.20#ibcon#about to write, iclass 29, count 0 2006.196.08:08:22.20#ibcon#wrote, iclass 29, count 0 2006.196.08:08:22.20#ibcon#about to read 3, iclass 29, count 0 2006.196.08:08:22.23#ibcon#read 3, iclass 29, count 0 2006.196.08:08:22.23#ibcon#about to read 4, iclass 29, count 0 2006.196.08:08:22.23#ibcon#read 4, iclass 29, count 0 2006.196.08:08:22.23#ibcon#about to read 5, iclass 29, count 0 2006.196.08:08:22.23#ibcon#read 5, iclass 29, count 0 2006.196.08:08:22.23#ibcon#about to read 6, iclass 29, count 0 2006.196.08:08:22.23#ibcon#read 6, iclass 29, count 0 2006.196.08:08:22.23#ibcon#end of sib2, iclass 29, count 0 2006.196.08:08:22.23#ibcon#*after write, iclass 29, count 0 2006.196.08:08:22.23#ibcon#*before return 0, iclass 29, count 0 2006.196.08:08:22.23#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.196.08:08:22.23#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.196.08:08:22.23#ibcon#about to clear, iclass 29 cls_cnt 0 2006.196.08:08:22.23#ibcon#cleared, iclass 29 cls_cnt 0 2006.196.08:08:22.23$vc4f8/vblo=6,752.99 2006.196.08:08:22.23#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.196.08:08:22.23#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.196.08:08:22.23#ibcon#ireg 17 cls_cnt 0 2006.196.08:08:22.23#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.196.08:08:22.23#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.196.08:08:22.23#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.196.08:08:22.23#ibcon#enter wrdev, iclass 31, count 0 2006.196.08:08:22.23#ibcon#first serial, iclass 31, count 0 2006.196.08:08:22.23#ibcon#enter sib2, iclass 31, count 0 2006.196.08:08:22.23#ibcon#flushed, iclass 31, count 0 2006.196.08:08:22.23#ibcon#about to write, iclass 31, count 0 2006.196.08:08:22.23#ibcon#wrote, iclass 31, count 0 2006.196.08:08:22.23#ibcon#about to read 3, iclass 31, count 0 2006.196.08:08:22.25#ibcon#read 3, iclass 31, count 0 2006.196.08:08:22.25#ibcon#about to read 4, iclass 31, count 0 2006.196.08:08:22.25#ibcon#read 4, iclass 31, count 0 2006.196.08:08:22.25#ibcon#about to read 5, iclass 31, count 0 2006.196.08:08:22.25#ibcon#read 5, iclass 31, count 0 2006.196.08:08:22.25#ibcon#about to read 6, iclass 31, count 0 2006.196.08:08:22.25#ibcon#read 6, iclass 31, count 0 2006.196.08:08:22.25#ibcon#end of sib2, iclass 31, count 0 2006.196.08:08:22.25#ibcon#*mode == 0, iclass 31, count 0 2006.196.08:08:22.25#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.196.08:08:22.25#ibcon#[28=FRQ=06,752.99\r\n] 2006.196.08:08:22.25#ibcon#*before write, iclass 31, count 0 2006.196.08:08:22.25#ibcon#enter sib2, iclass 31, count 0 2006.196.08:08:22.25#ibcon#flushed, iclass 31, count 0 2006.196.08:08:22.25#ibcon#about to write, iclass 31, count 0 2006.196.08:08:22.25#ibcon#wrote, iclass 31, count 0 2006.196.08:08:22.25#ibcon#about to read 3, iclass 31, count 0 2006.196.08:08:22.29#ibcon#read 3, iclass 31, count 0 2006.196.08:08:22.29#ibcon#about to read 4, iclass 31, count 0 2006.196.08:08:22.29#ibcon#read 4, iclass 31, count 0 2006.196.08:08:22.29#ibcon#about to read 5, iclass 31, count 0 2006.196.08:08:22.29#ibcon#read 5, iclass 31, count 0 2006.196.08:08:22.29#ibcon#about to read 6, iclass 31, count 0 2006.196.08:08:22.29#ibcon#read 6, iclass 31, count 0 2006.196.08:08:22.29#ibcon#end of sib2, iclass 31, count 0 2006.196.08:08:22.29#ibcon#*after write, iclass 31, count 0 2006.196.08:08:22.29#ibcon#*before return 0, iclass 31, count 0 2006.196.08:08:22.29#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.196.08:08:22.29#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.196.08:08:22.29#ibcon#about to clear, iclass 31 cls_cnt 0 2006.196.08:08:22.29#ibcon#cleared, iclass 31 cls_cnt 0 2006.196.08:08:22.29$vc4f8/vb=6,4 2006.196.08:08:22.29#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.196.08:08:22.29#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.196.08:08:22.29#ibcon#ireg 11 cls_cnt 2 2006.196.08:08:22.29#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.196.08:08:22.35#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.196.08:08:22.35#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.196.08:08:22.35#ibcon#enter wrdev, iclass 33, count 2 2006.196.08:08:22.35#ibcon#first serial, iclass 33, count 2 2006.196.08:08:22.35#ibcon#enter sib2, iclass 33, count 2 2006.196.08:08:22.35#ibcon#flushed, iclass 33, count 2 2006.196.08:08:22.35#ibcon#about to write, iclass 33, count 2 2006.196.08:08:22.35#ibcon#wrote, iclass 33, count 2 2006.196.08:08:22.35#ibcon#about to read 3, iclass 33, count 2 2006.196.08:08:22.37#ibcon#read 3, iclass 33, count 2 2006.196.08:08:22.37#ibcon#about to read 4, iclass 33, count 2 2006.196.08:08:22.37#ibcon#read 4, iclass 33, count 2 2006.196.08:08:22.37#ibcon#about to read 5, iclass 33, count 2 2006.196.08:08:22.37#ibcon#read 5, iclass 33, count 2 2006.196.08:08:22.37#ibcon#about to read 6, iclass 33, count 2 2006.196.08:08:22.37#ibcon#read 6, iclass 33, count 2 2006.196.08:08:22.37#ibcon#end of sib2, iclass 33, count 2 2006.196.08:08:22.37#ibcon#*mode == 0, iclass 33, count 2 2006.196.08:08:22.37#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.196.08:08:22.37#ibcon#[27=AT06-04\r\n] 2006.196.08:08:22.37#ibcon#*before write, iclass 33, count 2 2006.196.08:08:22.37#ibcon#enter sib2, iclass 33, count 2 2006.196.08:08:22.37#ibcon#flushed, iclass 33, count 2 2006.196.08:08:22.37#ibcon#about to write, iclass 33, count 2 2006.196.08:08:22.37#ibcon#wrote, iclass 33, count 2 2006.196.08:08:22.37#ibcon#about to read 3, iclass 33, count 2 2006.196.08:08:22.40#ibcon#read 3, iclass 33, count 2 2006.196.08:08:22.40#ibcon#about to read 4, iclass 33, count 2 2006.196.08:08:22.40#ibcon#read 4, iclass 33, count 2 2006.196.08:08:22.40#ibcon#about to read 5, iclass 33, count 2 2006.196.08:08:22.40#ibcon#read 5, iclass 33, count 2 2006.196.08:08:22.40#ibcon#about to read 6, iclass 33, count 2 2006.196.08:08:22.40#ibcon#read 6, iclass 33, count 2 2006.196.08:08:22.40#ibcon#end of sib2, iclass 33, count 2 2006.196.08:08:22.40#ibcon#*after write, iclass 33, count 2 2006.196.08:08:22.40#ibcon#*before return 0, iclass 33, count 2 2006.196.08:08:22.40#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.196.08:08:22.40#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.196.08:08:22.40#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.196.08:08:22.40#ibcon#ireg 7 cls_cnt 0 2006.196.08:08:22.40#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.196.08:08:22.52#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.196.08:08:22.52#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.196.08:08:22.52#ibcon#enter wrdev, iclass 33, count 0 2006.196.08:08:22.52#ibcon#first serial, iclass 33, count 0 2006.196.08:08:22.52#ibcon#enter sib2, iclass 33, count 0 2006.196.08:08:22.52#ibcon#flushed, iclass 33, count 0 2006.196.08:08:22.52#ibcon#about to write, iclass 33, count 0 2006.196.08:08:22.52#ibcon#wrote, iclass 33, count 0 2006.196.08:08:22.52#ibcon#about to read 3, iclass 33, count 0 2006.196.08:08:22.54#ibcon#read 3, iclass 33, count 0 2006.196.08:08:22.54#ibcon#about to read 4, iclass 33, count 0 2006.196.08:08:22.54#ibcon#read 4, iclass 33, count 0 2006.196.08:08:22.54#ibcon#about to read 5, iclass 33, count 0 2006.196.08:08:22.54#ibcon#read 5, iclass 33, count 0 2006.196.08:08:22.54#ibcon#about to read 6, iclass 33, count 0 2006.196.08:08:22.54#ibcon#read 6, iclass 33, count 0 2006.196.08:08:22.54#ibcon#end of sib2, iclass 33, count 0 2006.196.08:08:22.54#ibcon#*mode == 0, iclass 33, count 0 2006.196.08:08:22.54#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.196.08:08:22.54#ibcon#[27=USB\r\n] 2006.196.08:08:22.54#ibcon#*before write, iclass 33, count 0 2006.196.08:08:22.54#ibcon#enter sib2, iclass 33, count 0 2006.196.08:08:22.54#ibcon#flushed, iclass 33, count 0 2006.196.08:08:22.54#ibcon#about to write, iclass 33, count 0 2006.196.08:08:22.54#ibcon#wrote, iclass 33, count 0 2006.196.08:08:22.54#ibcon#about to read 3, iclass 33, count 0 2006.196.08:08:22.57#ibcon#read 3, iclass 33, count 0 2006.196.08:08:22.57#ibcon#about to read 4, iclass 33, count 0 2006.196.08:08:22.57#ibcon#read 4, iclass 33, count 0 2006.196.08:08:22.57#ibcon#about to read 5, iclass 33, count 0 2006.196.08:08:22.57#ibcon#read 5, iclass 33, count 0 2006.196.08:08:22.57#ibcon#about to read 6, iclass 33, count 0 2006.196.08:08:22.57#ibcon#read 6, iclass 33, count 0 2006.196.08:08:22.57#ibcon#end of sib2, iclass 33, count 0 2006.196.08:08:22.57#ibcon#*after write, iclass 33, count 0 2006.196.08:08:22.57#ibcon#*before return 0, iclass 33, count 0 2006.196.08:08:22.57#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.196.08:08:22.57#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.196.08:08:22.57#ibcon#about to clear, iclass 33 cls_cnt 0 2006.196.08:08:22.57#ibcon#cleared, iclass 33 cls_cnt 0 2006.196.08:08:22.57$vc4f8/vabw=wide 2006.196.08:08:22.57#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.196.08:08:22.57#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.196.08:08:22.57#ibcon#ireg 8 cls_cnt 0 2006.196.08:08:22.57#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.196.08:08:22.57#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.196.08:08:22.57#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.196.08:08:22.57#ibcon#enter wrdev, iclass 35, count 0 2006.196.08:08:22.57#ibcon#first serial, iclass 35, count 0 2006.196.08:08:22.57#ibcon#enter sib2, iclass 35, count 0 2006.196.08:08:22.57#ibcon#flushed, iclass 35, count 0 2006.196.08:08:22.57#ibcon#about to write, iclass 35, count 0 2006.196.08:08:22.57#ibcon#wrote, iclass 35, count 0 2006.196.08:08:22.57#ibcon#about to read 3, iclass 35, count 0 2006.196.08:08:22.59#ibcon#read 3, iclass 35, count 0 2006.196.08:08:22.59#ibcon#about to read 4, iclass 35, count 0 2006.196.08:08:22.59#ibcon#read 4, iclass 35, count 0 2006.196.08:08:22.59#ibcon#about to read 5, iclass 35, count 0 2006.196.08:08:22.59#ibcon#read 5, iclass 35, count 0 2006.196.08:08:22.59#ibcon#about to read 6, iclass 35, count 0 2006.196.08:08:22.59#ibcon#read 6, iclass 35, count 0 2006.196.08:08:22.59#ibcon#end of sib2, iclass 35, count 0 2006.196.08:08:22.59#ibcon#*mode == 0, iclass 35, count 0 2006.196.08:08:22.59#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.196.08:08:22.59#ibcon#[25=BW32\r\n] 2006.196.08:08:22.59#ibcon#*before write, iclass 35, count 0 2006.196.08:08:22.59#ibcon#enter sib2, iclass 35, count 0 2006.196.08:08:22.59#ibcon#flushed, iclass 35, count 0 2006.196.08:08:22.59#ibcon#about to write, iclass 35, count 0 2006.196.08:08:22.59#ibcon#wrote, iclass 35, count 0 2006.196.08:08:22.59#ibcon#about to read 3, iclass 35, count 0 2006.196.08:08:22.62#ibcon#read 3, iclass 35, count 0 2006.196.08:08:22.62#ibcon#about to read 4, iclass 35, count 0 2006.196.08:08:22.62#ibcon#read 4, iclass 35, count 0 2006.196.08:08:22.62#ibcon#about to read 5, iclass 35, count 0 2006.196.08:08:22.62#ibcon#read 5, iclass 35, count 0 2006.196.08:08:22.62#ibcon#about to read 6, iclass 35, count 0 2006.196.08:08:22.62#ibcon#read 6, iclass 35, count 0 2006.196.08:08:22.62#ibcon#end of sib2, iclass 35, count 0 2006.196.08:08:22.62#ibcon#*after write, iclass 35, count 0 2006.196.08:08:22.62#ibcon#*before return 0, iclass 35, count 0 2006.196.08:08:22.62#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.196.08:08:22.62#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.196.08:08:22.62#ibcon#about to clear, iclass 35 cls_cnt 0 2006.196.08:08:22.62#ibcon#cleared, iclass 35 cls_cnt 0 2006.196.08:08:22.62$vc4f8/vbbw=wide 2006.196.08:08:22.62#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.196.08:08:22.62#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.196.08:08:22.62#ibcon#ireg 8 cls_cnt 0 2006.196.08:08:22.62#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.196.08:08:22.69#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.196.08:08:22.69#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.196.08:08:22.69#ibcon#enter wrdev, iclass 37, count 0 2006.196.08:08:22.69#ibcon#first serial, iclass 37, count 0 2006.196.08:08:22.69#ibcon#enter sib2, iclass 37, count 0 2006.196.08:08:22.69#ibcon#flushed, iclass 37, count 0 2006.196.08:08:22.69#ibcon#about to write, iclass 37, count 0 2006.196.08:08:22.69#ibcon#wrote, iclass 37, count 0 2006.196.08:08:22.69#ibcon#about to read 3, iclass 37, count 0 2006.196.08:08:22.71#ibcon#read 3, iclass 37, count 0 2006.196.08:08:22.71#ibcon#about to read 4, iclass 37, count 0 2006.196.08:08:22.71#ibcon#read 4, iclass 37, count 0 2006.196.08:08:22.71#ibcon#about to read 5, iclass 37, count 0 2006.196.08:08:22.71#ibcon#read 5, iclass 37, count 0 2006.196.08:08:22.71#ibcon#about to read 6, iclass 37, count 0 2006.196.08:08:22.71#ibcon#read 6, iclass 37, count 0 2006.196.08:08:22.71#ibcon#end of sib2, iclass 37, count 0 2006.196.08:08:22.71#ibcon#*mode == 0, iclass 37, count 0 2006.196.08:08:22.71#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.196.08:08:22.71#ibcon#[27=BW32\r\n] 2006.196.08:08:22.71#ibcon#*before write, iclass 37, count 0 2006.196.08:08:22.71#ibcon#enter sib2, iclass 37, count 0 2006.196.08:08:22.71#ibcon#flushed, iclass 37, count 0 2006.196.08:08:22.71#ibcon#about to write, iclass 37, count 0 2006.196.08:08:22.71#ibcon#wrote, iclass 37, count 0 2006.196.08:08:22.71#ibcon#about to read 3, iclass 37, count 0 2006.196.08:08:22.74#ibcon#read 3, iclass 37, count 0 2006.196.08:08:22.74#ibcon#about to read 4, iclass 37, count 0 2006.196.08:08:22.74#ibcon#read 4, iclass 37, count 0 2006.196.08:08:22.74#ibcon#about to read 5, iclass 37, count 0 2006.196.08:08:22.74#ibcon#read 5, iclass 37, count 0 2006.196.08:08:22.74#ibcon#about to read 6, iclass 37, count 0 2006.196.08:08:22.74#ibcon#read 6, iclass 37, count 0 2006.196.08:08:22.74#ibcon#end of sib2, iclass 37, count 0 2006.196.08:08:22.74#ibcon#*after write, iclass 37, count 0 2006.196.08:08:22.74#ibcon#*before return 0, iclass 37, count 0 2006.196.08:08:22.74#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.196.08:08:22.74#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.196.08:08:22.74#ibcon#about to clear, iclass 37 cls_cnt 0 2006.196.08:08:22.74#ibcon#cleared, iclass 37 cls_cnt 0 2006.196.08:08:22.74$4f8m12a/ifd4f 2006.196.08:08:22.74$ifd4f/lo= 2006.196.08:08:22.74$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.196.08:08:22.74$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.196.08:08:22.74$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.196.08:08:22.74$ifd4f/patch= 2006.196.08:08:22.74$ifd4f/patch=lo1,a1,a2,a3,a4 2006.196.08:08:22.74$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.196.08:08:22.74$ifd4f/patch=lo3,a5,a6,a7,a8 2006.196.08:08:22.74$4f8m12a/"form=m,16.000,1:2 2006.196.08:08:22.74$4f8m12a/"tpicd 2006.196.08:08:22.74$4f8m12a/echo=off 2006.196.08:08:22.74$4f8m12a/xlog=off 2006.196.08:08:22.74:!2006.196.08:09:10 2006.196.08:08:52.14#trakl#Source acquired 2006.196.08:08:53.14#flagr#flagr/antenna,acquired 2006.196.08:09:10.00:preob 2006.196.08:09:10.14/onsource/TRACKING 2006.196.08:09:10.14:!2006.196.08:09:20 2006.196.08:09:20.00:data_valid=on 2006.196.08:09:20.00:midob 2006.196.08:09:20.14/onsource/TRACKING 2006.196.08:09:20.14/wx/29.29,1003.9,91 2006.196.08:09:20.23/cable/+6.3371E-03 2006.196.08:09:21.32/va/01,08,usb,yes,32,34 2006.196.08:09:21.32/va/02,07,usb,yes,32,34 2006.196.08:09:21.32/va/03,06,usb,yes,34,34 2006.196.08:09:21.32/va/04,07,usb,yes,33,36 2006.196.08:09:21.32/va/05,07,usb,yes,36,38 2006.196.08:09:21.32/va/06,06,usb,yes,35,35 2006.196.08:09:21.32/va/07,06,usb,yes,35,35 2006.196.08:09:21.32/va/08,07,usb,yes,33,33 2006.196.08:09:21.55/valo/01,532.99,yes,locked 2006.196.08:09:21.55/valo/02,572.99,yes,locked 2006.196.08:09:21.55/valo/03,672.99,yes,locked 2006.196.08:09:21.55/valo/04,832.99,yes,locked 2006.196.08:09:21.55/valo/05,652.99,yes,locked 2006.196.08:09:21.55/valo/06,772.99,yes,locked 2006.196.08:09:21.55/valo/07,832.99,yes,locked 2006.196.08:09:21.55/valo/08,852.99,yes,locked 2006.196.08:09:22.64/vb/01,04,usb,yes,28,26 2006.196.08:09:22.64/vb/02,04,usb,yes,29,31 2006.196.08:09:22.64/vb/03,04,usb,yes,26,29 2006.196.08:09:22.64/vb/04,04,usb,yes,27,27 2006.196.08:09:22.64/vb/05,04,usb,yes,25,29 2006.196.08:09:22.64/vb/06,04,usb,yes,26,29 2006.196.08:09:22.64/vb/07,04,usb,yes,28,28 2006.196.08:09:22.64/vb/08,04,usb,yes,26,29 2006.196.08:09:22.88/vblo/01,632.99,yes,locked 2006.196.08:09:22.88/vblo/02,640.99,yes,locked 2006.196.08:09:22.88/vblo/03,656.99,yes,locked 2006.196.08:09:22.88/vblo/04,712.99,yes,locked 2006.196.08:09:22.88/vblo/05,744.99,yes,locked 2006.196.08:09:22.88/vblo/06,752.99,yes,locked 2006.196.08:09:22.88/vblo/07,734.99,yes,locked 2006.196.08:09:22.88/vblo/08,744.99,yes,locked 2006.196.08:09:23.03/vabw/8 2006.196.08:09:23.18/vbbw/8 2006.196.08:09:23.28/xfe/off,on,15.2 2006.196.08:09:23.66/ifatt/23,28,28,28 2006.196.08:09:24.07/fmout-gps/S +3.37E-07 2006.196.08:09:24.11:!2006.196.08:12:00 2006.196.08:12:00.00:data_valid=off 2006.196.08:12:00.00:postob 2006.196.08:12:00.18/cable/+6.3352E-03 2006.196.08:12:00.18/wx/29.22,1003.9,92 2006.196.08:12:01.07/fmout-gps/S +3.36E-07 2006.196.08:12:01.07:scan_name=196-0813,k06196,70 2006.196.08:12:01.07:source=1053+815,105811.54,811432.7,2000.0,neutral 2006.196.08:12:02.14#flagr#flagr/antenna,new-source 2006.196.08:12:02.14:checkk5 2006.196.08:12:02.51/chk_autoobs//k5ts1/ autoobs is running! 2006.196.08:12:02.93/chk_autoobs//k5ts2/ autoobs is running! 2006.196.08:12:03.32/chk_autoobs//k5ts3/ autoobs is running! 2006.196.08:12:03.70/chk_autoobs//k5ts4/ autoobs is running! 2006.196.08:12:04.06/chk_obsdata//k5ts1/T1960809??a.dat file size is correct (nominal:1280MB, actual:1272MB). 2006.196.08:12:04.44/chk_obsdata//k5ts2/T1960809??b.dat file size is correct (nominal:1280MB, actual:1272MB). 2006.196.08:12:04.81/chk_obsdata//k5ts3/T1960809??c.dat file size is correct (nominal:1280MB, actual:1272MB). 2006.196.08:12:05.18/chk_obsdata//k5ts4/T1960809??d.dat file size is correct (nominal:1280MB, actual:1272MB). 2006.196.08:12:05.87/k5log//k5ts1_log_newline 2006.196.08:12:06.57/k5log//k5ts2_log_newline 2006.196.08:12:07.25/k5log//k5ts3_log_newline 2006.196.08:12:07.94/k5log//k5ts4_log_newline 2006.196.08:12:07.96/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.196.08:12:07.96:4f8m12a=2 2006.196.08:12:07.96$4f8m12a/echo=on 2006.196.08:12:07.97$4f8m12a/pcalon 2006.196.08:12:07.97$pcalon/"no phase cal control is implemented here 2006.196.08:12:07.97$4f8m12a/"tpicd=stop 2006.196.08:12:07.97$4f8m12a/vc4f8 2006.196.08:12:07.97$vc4f8/valo=1,532.99 2006.196.08:12:07.97#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.196.08:12:07.97#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.196.08:12:07.97#ibcon#ireg 17 cls_cnt 0 2006.196.08:12:07.97#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.196.08:12:07.97#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.196.08:12:07.97#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.196.08:12:07.97#ibcon#enter wrdev, iclass 20, count 0 2006.196.08:12:07.97#ibcon#first serial, iclass 20, count 0 2006.196.08:12:07.97#ibcon#enter sib2, iclass 20, count 0 2006.196.08:12:07.97#ibcon#flushed, iclass 20, count 0 2006.196.08:12:07.97#ibcon#about to write, iclass 20, count 0 2006.196.08:12:07.97#ibcon#wrote, iclass 20, count 0 2006.196.08:12:07.97#ibcon#about to read 3, iclass 20, count 0 2006.196.08:12:08.01#ibcon#read 3, iclass 20, count 0 2006.196.08:12:08.01#ibcon#about to read 4, iclass 20, count 0 2006.196.08:12:08.01#ibcon#read 4, iclass 20, count 0 2006.196.08:12:08.01#ibcon#about to read 5, iclass 20, count 0 2006.196.08:12:08.01#ibcon#read 5, iclass 20, count 0 2006.196.08:12:08.01#ibcon#about to read 6, iclass 20, count 0 2006.196.08:12:08.01#ibcon#read 6, iclass 20, count 0 2006.196.08:12:08.01#ibcon#end of sib2, iclass 20, count 0 2006.196.08:12:08.01#ibcon#*mode == 0, iclass 20, count 0 2006.196.08:12:08.01#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.196.08:12:08.01#ibcon#[26=FRQ=01,532.99\r\n] 2006.196.08:12:08.01#ibcon#*before write, iclass 20, count 0 2006.196.08:12:08.01#ibcon#enter sib2, iclass 20, count 0 2006.196.08:12:08.01#ibcon#flushed, iclass 20, count 0 2006.196.08:12:08.01#ibcon#about to write, iclass 20, count 0 2006.196.08:12:08.01#ibcon#wrote, iclass 20, count 0 2006.196.08:12:08.01#ibcon#about to read 3, iclass 20, count 0 2006.196.08:12:08.06#ibcon#read 3, iclass 20, count 0 2006.196.08:12:08.06#ibcon#about to read 4, iclass 20, count 0 2006.196.08:12:08.06#ibcon#read 4, iclass 20, count 0 2006.196.08:12:08.06#ibcon#about to read 5, iclass 20, count 0 2006.196.08:12:08.06#ibcon#read 5, iclass 20, count 0 2006.196.08:12:08.06#ibcon#about to read 6, iclass 20, count 0 2006.196.08:12:08.06#ibcon#read 6, iclass 20, count 0 2006.196.08:12:08.06#ibcon#end of sib2, iclass 20, count 0 2006.196.08:12:08.06#ibcon#*after write, iclass 20, count 0 2006.196.08:12:08.06#ibcon#*before return 0, iclass 20, count 0 2006.196.08:12:08.06#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.196.08:12:08.06#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.196.08:12:08.06#ibcon#about to clear, iclass 20 cls_cnt 0 2006.196.08:12:08.06#ibcon#cleared, iclass 20 cls_cnt 0 2006.196.08:12:08.06$vc4f8/va=1,8 2006.196.08:12:08.06#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.196.08:12:08.06#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.196.08:12:08.06#ibcon#ireg 11 cls_cnt 2 2006.196.08:12:08.06#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.196.08:12:08.06#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.196.08:12:08.06#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.196.08:12:08.06#ibcon#enter wrdev, iclass 22, count 2 2006.196.08:12:08.06#ibcon#first serial, iclass 22, count 2 2006.196.08:12:08.06#ibcon#enter sib2, iclass 22, count 2 2006.196.08:12:08.06#ibcon#flushed, iclass 22, count 2 2006.196.08:12:08.06#ibcon#about to write, iclass 22, count 2 2006.196.08:12:08.06#ibcon#wrote, iclass 22, count 2 2006.196.08:12:08.06#ibcon#about to read 3, iclass 22, count 2 2006.196.08:12:08.08#ibcon#read 3, iclass 22, count 2 2006.196.08:12:08.08#ibcon#about to read 4, iclass 22, count 2 2006.196.08:12:08.08#ibcon#read 4, iclass 22, count 2 2006.196.08:12:08.08#ibcon#about to read 5, iclass 22, count 2 2006.196.08:12:08.08#ibcon#read 5, iclass 22, count 2 2006.196.08:12:08.08#ibcon#about to read 6, iclass 22, count 2 2006.196.08:12:08.08#ibcon#read 6, iclass 22, count 2 2006.196.08:12:08.08#ibcon#end of sib2, iclass 22, count 2 2006.196.08:12:08.08#ibcon#*mode == 0, iclass 22, count 2 2006.196.08:12:08.08#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.196.08:12:08.08#ibcon#[25=AT01-08\r\n] 2006.196.08:12:08.08#ibcon#*before write, iclass 22, count 2 2006.196.08:12:08.08#ibcon#enter sib2, iclass 22, count 2 2006.196.08:12:08.08#ibcon#flushed, iclass 22, count 2 2006.196.08:12:08.08#ibcon#about to write, iclass 22, count 2 2006.196.08:12:08.08#ibcon#wrote, iclass 22, count 2 2006.196.08:12:08.08#ibcon#about to read 3, iclass 22, count 2 2006.196.08:12:08.11#ibcon#read 3, iclass 22, count 2 2006.196.08:12:08.11#ibcon#about to read 4, iclass 22, count 2 2006.196.08:12:08.11#ibcon#read 4, iclass 22, count 2 2006.196.08:12:08.11#ibcon#about to read 5, iclass 22, count 2 2006.196.08:12:08.11#ibcon#read 5, iclass 22, count 2 2006.196.08:12:08.11#ibcon#about to read 6, iclass 22, count 2 2006.196.08:12:08.11#ibcon#read 6, iclass 22, count 2 2006.196.08:12:08.11#ibcon#end of sib2, iclass 22, count 2 2006.196.08:12:08.11#ibcon#*after write, iclass 22, count 2 2006.196.08:12:08.11#ibcon#*before return 0, iclass 22, count 2 2006.196.08:12:08.11#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.196.08:12:08.11#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.196.08:12:08.11#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.196.08:12:08.11#ibcon#ireg 7 cls_cnt 0 2006.196.08:12:08.11#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.196.08:12:08.23#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.196.08:12:08.23#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.196.08:12:08.23#ibcon#enter wrdev, iclass 22, count 0 2006.196.08:12:08.23#ibcon#first serial, iclass 22, count 0 2006.196.08:12:08.23#ibcon#enter sib2, iclass 22, count 0 2006.196.08:12:08.23#ibcon#flushed, iclass 22, count 0 2006.196.08:12:08.23#ibcon#about to write, iclass 22, count 0 2006.196.08:12:08.23#ibcon#wrote, iclass 22, count 0 2006.196.08:12:08.23#ibcon#about to read 3, iclass 22, count 0 2006.196.08:12:08.25#ibcon#read 3, iclass 22, count 0 2006.196.08:12:08.25#ibcon#about to read 4, iclass 22, count 0 2006.196.08:12:08.25#ibcon#read 4, iclass 22, count 0 2006.196.08:12:08.25#ibcon#about to read 5, iclass 22, count 0 2006.196.08:12:08.25#ibcon#read 5, iclass 22, count 0 2006.196.08:12:08.25#ibcon#about to read 6, iclass 22, count 0 2006.196.08:12:08.25#ibcon#read 6, iclass 22, count 0 2006.196.08:12:08.25#ibcon#end of sib2, iclass 22, count 0 2006.196.08:12:08.25#ibcon#*mode == 0, iclass 22, count 0 2006.196.08:12:08.25#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.196.08:12:08.25#ibcon#[25=USB\r\n] 2006.196.08:12:08.25#ibcon#*before write, iclass 22, count 0 2006.196.08:12:08.25#ibcon#enter sib2, iclass 22, count 0 2006.196.08:12:08.25#ibcon#flushed, iclass 22, count 0 2006.196.08:12:08.25#ibcon#about to write, iclass 22, count 0 2006.196.08:12:08.25#ibcon#wrote, iclass 22, count 0 2006.196.08:12:08.25#ibcon#about to read 3, iclass 22, count 0 2006.196.08:12:08.28#ibcon#read 3, iclass 22, count 0 2006.196.08:12:08.28#ibcon#about to read 4, iclass 22, count 0 2006.196.08:12:08.28#ibcon#read 4, iclass 22, count 0 2006.196.08:12:08.28#ibcon#about to read 5, iclass 22, count 0 2006.196.08:12:08.28#ibcon#read 5, iclass 22, count 0 2006.196.08:12:08.28#ibcon#about to read 6, iclass 22, count 0 2006.196.08:12:08.28#ibcon#read 6, iclass 22, count 0 2006.196.08:12:08.28#ibcon#end of sib2, iclass 22, count 0 2006.196.08:12:08.28#ibcon#*after write, iclass 22, count 0 2006.196.08:12:08.28#ibcon#*before return 0, iclass 22, count 0 2006.196.08:12:08.28#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.196.08:12:08.28#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.196.08:12:08.28#ibcon#about to clear, iclass 22 cls_cnt 0 2006.196.08:12:08.28#ibcon#cleared, iclass 22 cls_cnt 0 2006.196.08:12:08.28$vc4f8/valo=2,572.99 2006.196.08:12:08.28#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.196.08:12:08.28#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.196.08:12:08.28#ibcon#ireg 17 cls_cnt 0 2006.196.08:12:08.28#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.196.08:12:08.28#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.196.08:12:08.28#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.196.08:12:08.28#ibcon#enter wrdev, iclass 24, count 0 2006.196.08:12:08.28#ibcon#first serial, iclass 24, count 0 2006.196.08:12:08.28#ibcon#enter sib2, iclass 24, count 0 2006.196.08:12:08.28#ibcon#flushed, iclass 24, count 0 2006.196.08:12:08.28#ibcon#about to write, iclass 24, count 0 2006.196.08:12:08.28#ibcon#wrote, iclass 24, count 0 2006.196.08:12:08.28#ibcon#about to read 3, iclass 24, count 0 2006.196.08:12:08.30#ibcon#read 3, iclass 24, count 0 2006.196.08:12:08.30#ibcon#about to read 4, iclass 24, count 0 2006.196.08:12:08.30#ibcon#read 4, iclass 24, count 0 2006.196.08:12:08.30#ibcon#about to read 5, iclass 24, count 0 2006.196.08:12:08.30#ibcon#read 5, iclass 24, count 0 2006.196.08:12:08.30#ibcon#about to read 6, iclass 24, count 0 2006.196.08:12:08.30#ibcon#read 6, iclass 24, count 0 2006.196.08:12:08.30#ibcon#end of sib2, iclass 24, count 0 2006.196.08:12:08.30#ibcon#*mode == 0, iclass 24, count 0 2006.196.08:12:08.30#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.196.08:12:08.30#ibcon#[26=FRQ=02,572.99\r\n] 2006.196.08:12:08.30#ibcon#*before write, iclass 24, count 0 2006.196.08:12:08.30#ibcon#enter sib2, iclass 24, count 0 2006.196.08:12:08.30#ibcon#flushed, iclass 24, count 0 2006.196.08:12:08.30#ibcon#about to write, iclass 24, count 0 2006.196.08:12:08.30#ibcon#wrote, iclass 24, count 0 2006.196.08:12:08.30#ibcon#about to read 3, iclass 24, count 0 2006.196.08:12:08.35#ibcon#read 3, iclass 24, count 0 2006.196.08:12:08.35#ibcon#about to read 4, iclass 24, count 0 2006.196.08:12:08.35#ibcon#read 4, iclass 24, count 0 2006.196.08:12:08.35#ibcon#about to read 5, iclass 24, count 0 2006.196.08:12:08.35#ibcon#read 5, iclass 24, count 0 2006.196.08:12:08.35#ibcon#about to read 6, iclass 24, count 0 2006.196.08:12:08.35#ibcon#read 6, iclass 24, count 0 2006.196.08:12:08.35#ibcon#end of sib2, iclass 24, count 0 2006.196.08:12:08.35#ibcon#*after write, iclass 24, count 0 2006.196.08:12:08.35#ibcon#*before return 0, iclass 24, count 0 2006.196.08:12:08.35#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.196.08:12:08.35#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.196.08:12:08.35#ibcon#about to clear, iclass 24 cls_cnt 0 2006.196.08:12:08.35#ibcon#cleared, iclass 24 cls_cnt 0 2006.196.08:12:08.35$vc4f8/va=2,7 2006.196.08:12:08.35#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.196.08:12:08.35#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.196.08:12:08.35#ibcon#ireg 11 cls_cnt 2 2006.196.08:12:08.35#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.196.08:12:08.40#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.196.08:12:08.40#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.196.08:12:08.40#ibcon#enter wrdev, iclass 26, count 2 2006.196.08:12:08.40#ibcon#first serial, iclass 26, count 2 2006.196.08:12:08.40#ibcon#enter sib2, iclass 26, count 2 2006.196.08:12:08.40#ibcon#flushed, iclass 26, count 2 2006.196.08:12:08.40#ibcon#about to write, iclass 26, count 2 2006.196.08:12:08.40#ibcon#wrote, iclass 26, count 2 2006.196.08:12:08.40#ibcon#about to read 3, iclass 26, count 2 2006.196.08:12:08.42#ibcon#read 3, iclass 26, count 2 2006.196.08:12:08.42#ibcon#about to read 4, iclass 26, count 2 2006.196.08:12:08.42#ibcon#read 4, iclass 26, count 2 2006.196.08:12:08.42#ibcon#about to read 5, iclass 26, count 2 2006.196.08:12:08.42#ibcon#read 5, iclass 26, count 2 2006.196.08:12:08.42#ibcon#about to read 6, iclass 26, count 2 2006.196.08:12:08.42#ibcon#read 6, iclass 26, count 2 2006.196.08:12:08.42#ibcon#end of sib2, iclass 26, count 2 2006.196.08:12:08.42#ibcon#*mode == 0, iclass 26, count 2 2006.196.08:12:08.42#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.196.08:12:08.42#ibcon#[25=AT02-07\r\n] 2006.196.08:12:08.42#ibcon#*before write, iclass 26, count 2 2006.196.08:12:08.42#ibcon#enter sib2, iclass 26, count 2 2006.196.08:12:08.42#ibcon#flushed, iclass 26, count 2 2006.196.08:12:08.42#ibcon#about to write, iclass 26, count 2 2006.196.08:12:08.42#ibcon#wrote, iclass 26, count 2 2006.196.08:12:08.42#ibcon#about to read 3, iclass 26, count 2 2006.196.08:12:08.45#ibcon#read 3, iclass 26, count 2 2006.196.08:12:08.45#ibcon#about to read 4, iclass 26, count 2 2006.196.08:12:08.45#ibcon#read 4, iclass 26, count 2 2006.196.08:12:08.45#ibcon#about to read 5, iclass 26, count 2 2006.196.08:12:08.45#ibcon#read 5, iclass 26, count 2 2006.196.08:12:08.45#ibcon#about to read 6, iclass 26, count 2 2006.196.08:12:08.45#ibcon#read 6, iclass 26, count 2 2006.196.08:12:08.45#ibcon#end of sib2, iclass 26, count 2 2006.196.08:12:08.45#ibcon#*after write, iclass 26, count 2 2006.196.08:12:08.45#ibcon#*before return 0, iclass 26, count 2 2006.196.08:12:08.45#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.196.08:12:08.45#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.196.08:12:08.45#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.196.08:12:08.45#ibcon#ireg 7 cls_cnt 0 2006.196.08:12:08.45#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.196.08:12:08.57#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.196.08:12:08.57#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.196.08:12:08.57#ibcon#enter wrdev, iclass 26, count 0 2006.196.08:12:08.57#ibcon#first serial, iclass 26, count 0 2006.196.08:12:08.57#ibcon#enter sib2, iclass 26, count 0 2006.196.08:12:08.57#ibcon#flushed, iclass 26, count 0 2006.196.08:12:08.57#ibcon#about to write, iclass 26, count 0 2006.196.08:12:08.57#ibcon#wrote, iclass 26, count 0 2006.196.08:12:08.57#ibcon#about to read 3, iclass 26, count 0 2006.196.08:12:08.59#ibcon#read 3, iclass 26, count 0 2006.196.08:12:08.59#ibcon#about to read 4, iclass 26, count 0 2006.196.08:12:08.59#ibcon#read 4, iclass 26, count 0 2006.196.08:12:08.59#ibcon#about to read 5, iclass 26, count 0 2006.196.08:12:08.59#ibcon#read 5, iclass 26, count 0 2006.196.08:12:08.59#ibcon#about to read 6, iclass 26, count 0 2006.196.08:12:08.59#ibcon#read 6, iclass 26, count 0 2006.196.08:12:08.59#ibcon#end of sib2, iclass 26, count 0 2006.196.08:12:08.59#ibcon#*mode == 0, iclass 26, count 0 2006.196.08:12:08.59#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.196.08:12:08.59#ibcon#[25=USB\r\n] 2006.196.08:12:08.59#ibcon#*before write, iclass 26, count 0 2006.196.08:12:08.59#ibcon#enter sib2, iclass 26, count 0 2006.196.08:12:08.59#ibcon#flushed, iclass 26, count 0 2006.196.08:12:08.59#ibcon#about to write, iclass 26, count 0 2006.196.08:12:08.59#ibcon#wrote, iclass 26, count 0 2006.196.08:12:08.59#ibcon#about to read 3, iclass 26, count 0 2006.196.08:12:08.62#ibcon#read 3, iclass 26, count 0 2006.196.08:12:08.62#ibcon#about to read 4, iclass 26, count 0 2006.196.08:12:08.62#ibcon#read 4, iclass 26, count 0 2006.196.08:12:08.62#ibcon#about to read 5, iclass 26, count 0 2006.196.08:12:08.62#ibcon#read 5, iclass 26, count 0 2006.196.08:12:08.62#ibcon#about to read 6, iclass 26, count 0 2006.196.08:12:08.62#ibcon#read 6, iclass 26, count 0 2006.196.08:12:08.62#ibcon#end of sib2, iclass 26, count 0 2006.196.08:12:08.62#ibcon#*after write, iclass 26, count 0 2006.196.08:12:08.62#ibcon#*before return 0, iclass 26, count 0 2006.196.08:12:08.62#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.196.08:12:08.62#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.196.08:12:08.62#ibcon#about to clear, iclass 26 cls_cnt 0 2006.196.08:12:08.62#ibcon#cleared, iclass 26 cls_cnt 0 2006.196.08:12:08.62$vc4f8/valo=3,672.99 2006.196.08:12:08.62#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.196.08:12:08.62#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.196.08:12:08.62#ibcon#ireg 17 cls_cnt 0 2006.196.08:12:08.62#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.196.08:12:08.62#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.196.08:12:08.62#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.196.08:12:08.62#ibcon#enter wrdev, iclass 28, count 0 2006.196.08:12:08.62#ibcon#first serial, iclass 28, count 0 2006.196.08:12:08.62#ibcon#enter sib2, iclass 28, count 0 2006.196.08:12:08.62#ibcon#flushed, iclass 28, count 0 2006.196.08:12:08.62#ibcon#about to write, iclass 28, count 0 2006.196.08:12:08.62#ibcon#wrote, iclass 28, count 0 2006.196.08:12:08.62#ibcon#about to read 3, iclass 28, count 0 2006.196.08:12:08.64#ibcon#read 3, iclass 28, count 0 2006.196.08:12:08.64#ibcon#about to read 4, iclass 28, count 0 2006.196.08:12:08.64#ibcon#read 4, iclass 28, count 0 2006.196.08:12:08.64#ibcon#about to read 5, iclass 28, count 0 2006.196.08:12:08.64#ibcon#read 5, iclass 28, count 0 2006.196.08:12:08.64#ibcon#about to read 6, iclass 28, count 0 2006.196.08:12:08.64#ibcon#read 6, iclass 28, count 0 2006.196.08:12:08.64#ibcon#end of sib2, iclass 28, count 0 2006.196.08:12:08.64#ibcon#*mode == 0, iclass 28, count 0 2006.196.08:12:08.64#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.196.08:12:08.64#ibcon#[26=FRQ=03,672.99\r\n] 2006.196.08:12:08.64#ibcon#*before write, iclass 28, count 0 2006.196.08:12:08.64#ibcon#enter sib2, iclass 28, count 0 2006.196.08:12:08.64#ibcon#flushed, iclass 28, count 0 2006.196.08:12:08.64#ibcon#about to write, iclass 28, count 0 2006.196.08:12:08.64#ibcon#wrote, iclass 28, count 0 2006.196.08:12:08.64#ibcon#about to read 3, iclass 28, count 0 2006.196.08:12:08.69#ibcon#read 3, iclass 28, count 0 2006.196.08:12:08.69#ibcon#about to read 4, iclass 28, count 0 2006.196.08:12:08.69#ibcon#read 4, iclass 28, count 0 2006.196.08:12:08.69#ibcon#about to read 5, iclass 28, count 0 2006.196.08:12:08.69#ibcon#read 5, iclass 28, count 0 2006.196.08:12:08.69#ibcon#about to read 6, iclass 28, count 0 2006.196.08:12:08.69#ibcon#read 6, iclass 28, count 0 2006.196.08:12:08.69#ibcon#end of sib2, iclass 28, count 0 2006.196.08:12:08.69#ibcon#*after write, iclass 28, count 0 2006.196.08:12:08.69#ibcon#*before return 0, iclass 28, count 0 2006.196.08:12:08.69#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.196.08:12:08.69#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.196.08:12:08.69#ibcon#about to clear, iclass 28 cls_cnt 0 2006.196.08:12:08.69#ibcon#cleared, iclass 28 cls_cnt 0 2006.196.08:12:08.69$vc4f8/va=3,6 2006.196.08:12:08.69#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.196.08:12:08.69#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.196.08:12:08.69#ibcon#ireg 11 cls_cnt 2 2006.196.08:12:08.69#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.196.08:12:08.74#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.196.08:12:08.74#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.196.08:12:08.74#ibcon#enter wrdev, iclass 30, count 2 2006.196.08:12:08.74#ibcon#first serial, iclass 30, count 2 2006.196.08:12:08.74#ibcon#enter sib2, iclass 30, count 2 2006.196.08:12:08.74#ibcon#flushed, iclass 30, count 2 2006.196.08:12:08.74#ibcon#about to write, iclass 30, count 2 2006.196.08:12:08.74#ibcon#wrote, iclass 30, count 2 2006.196.08:12:08.74#ibcon#about to read 3, iclass 30, count 2 2006.196.08:12:08.76#ibcon#read 3, iclass 30, count 2 2006.196.08:12:08.76#ibcon#about to read 4, iclass 30, count 2 2006.196.08:12:08.76#ibcon#read 4, iclass 30, count 2 2006.196.08:12:08.76#ibcon#about to read 5, iclass 30, count 2 2006.196.08:12:08.76#ibcon#read 5, iclass 30, count 2 2006.196.08:12:08.76#ibcon#about to read 6, iclass 30, count 2 2006.196.08:12:08.76#ibcon#read 6, iclass 30, count 2 2006.196.08:12:08.76#ibcon#end of sib2, iclass 30, count 2 2006.196.08:12:08.76#ibcon#*mode == 0, iclass 30, count 2 2006.196.08:12:08.76#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.196.08:12:08.76#ibcon#[25=AT03-06\r\n] 2006.196.08:12:08.76#ibcon#*before write, iclass 30, count 2 2006.196.08:12:08.76#ibcon#enter sib2, iclass 30, count 2 2006.196.08:12:08.76#ibcon#flushed, iclass 30, count 2 2006.196.08:12:08.76#ibcon#about to write, iclass 30, count 2 2006.196.08:12:08.76#ibcon#wrote, iclass 30, count 2 2006.196.08:12:08.76#ibcon#about to read 3, iclass 30, count 2 2006.196.08:12:08.79#ibcon#read 3, iclass 30, count 2 2006.196.08:12:08.79#ibcon#about to read 4, iclass 30, count 2 2006.196.08:12:08.79#ibcon#read 4, iclass 30, count 2 2006.196.08:12:08.79#ibcon#about to read 5, iclass 30, count 2 2006.196.08:12:08.79#ibcon#read 5, iclass 30, count 2 2006.196.08:12:08.79#ibcon#about to read 6, iclass 30, count 2 2006.196.08:12:08.79#ibcon#read 6, iclass 30, count 2 2006.196.08:12:08.79#ibcon#end of sib2, iclass 30, count 2 2006.196.08:12:08.79#ibcon#*after write, iclass 30, count 2 2006.196.08:12:08.79#ibcon#*before return 0, iclass 30, count 2 2006.196.08:12:08.79#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.196.08:12:08.79#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.196.08:12:08.79#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.196.08:12:08.79#ibcon#ireg 7 cls_cnt 0 2006.196.08:12:08.79#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.196.08:12:08.91#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.196.08:12:08.91#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.196.08:12:08.91#ibcon#enter wrdev, iclass 30, count 0 2006.196.08:12:08.91#ibcon#first serial, iclass 30, count 0 2006.196.08:12:08.91#ibcon#enter sib2, iclass 30, count 0 2006.196.08:12:08.91#ibcon#flushed, iclass 30, count 0 2006.196.08:12:08.91#ibcon#about to write, iclass 30, count 0 2006.196.08:12:08.91#ibcon#wrote, iclass 30, count 0 2006.196.08:12:08.91#ibcon#about to read 3, iclass 30, count 0 2006.196.08:12:08.93#ibcon#read 3, iclass 30, count 0 2006.196.08:12:08.93#ibcon#about to read 4, iclass 30, count 0 2006.196.08:12:08.93#ibcon#read 4, iclass 30, count 0 2006.196.08:12:08.93#ibcon#about to read 5, iclass 30, count 0 2006.196.08:12:08.93#ibcon#read 5, iclass 30, count 0 2006.196.08:12:08.93#ibcon#about to read 6, iclass 30, count 0 2006.196.08:12:08.93#ibcon#read 6, iclass 30, count 0 2006.196.08:12:08.93#ibcon#end of sib2, iclass 30, count 0 2006.196.08:12:08.93#ibcon#*mode == 0, iclass 30, count 0 2006.196.08:12:08.93#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.196.08:12:08.93#ibcon#[25=USB\r\n] 2006.196.08:12:08.93#ibcon#*before write, iclass 30, count 0 2006.196.08:12:08.93#ibcon#enter sib2, iclass 30, count 0 2006.196.08:12:08.93#ibcon#flushed, iclass 30, count 0 2006.196.08:12:08.93#ibcon#about to write, iclass 30, count 0 2006.196.08:12:08.93#ibcon#wrote, iclass 30, count 0 2006.196.08:12:08.93#ibcon#about to read 3, iclass 30, count 0 2006.196.08:12:08.96#ibcon#read 3, iclass 30, count 0 2006.196.08:12:08.96#ibcon#about to read 4, iclass 30, count 0 2006.196.08:12:08.96#ibcon#read 4, iclass 30, count 0 2006.196.08:12:08.96#ibcon#about to read 5, iclass 30, count 0 2006.196.08:12:08.96#ibcon#read 5, iclass 30, count 0 2006.196.08:12:08.96#ibcon#about to read 6, iclass 30, count 0 2006.196.08:12:08.96#ibcon#read 6, iclass 30, count 0 2006.196.08:12:08.96#ibcon#end of sib2, iclass 30, count 0 2006.196.08:12:08.96#ibcon#*after write, iclass 30, count 0 2006.196.08:12:08.96#ibcon#*before return 0, iclass 30, count 0 2006.196.08:12:08.96#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.196.08:12:08.96#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.196.08:12:08.96#ibcon#about to clear, iclass 30 cls_cnt 0 2006.196.08:12:08.96#ibcon#cleared, iclass 30 cls_cnt 0 2006.196.08:12:08.96$vc4f8/valo=4,832.99 2006.196.08:12:08.96#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.196.08:12:08.96#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.196.08:12:08.96#ibcon#ireg 17 cls_cnt 0 2006.196.08:12:08.96#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.196.08:12:08.96#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.196.08:12:08.96#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.196.08:12:08.96#ibcon#enter wrdev, iclass 32, count 0 2006.196.08:12:08.96#ibcon#first serial, iclass 32, count 0 2006.196.08:12:08.96#ibcon#enter sib2, iclass 32, count 0 2006.196.08:12:08.96#ibcon#flushed, iclass 32, count 0 2006.196.08:12:08.96#ibcon#about to write, iclass 32, count 0 2006.196.08:12:08.96#ibcon#wrote, iclass 32, count 0 2006.196.08:12:08.96#ibcon#about to read 3, iclass 32, count 0 2006.196.08:12:08.98#ibcon#read 3, iclass 32, count 0 2006.196.08:12:08.98#ibcon#about to read 4, iclass 32, count 0 2006.196.08:12:08.98#ibcon#read 4, iclass 32, count 0 2006.196.08:12:08.98#ibcon#about to read 5, iclass 32, count 0 2006.196.08:12:08.98#ibcon#read 5, iclass 32, count 0 2006.196.08:12:08.98#ibcon#about to read 6, iclass 32, count 0 2006.196.08:12:08.98#ibcon#read 6, iclass 32, count 0 2006.196.08:12:08.98#ibcon#end of sib2, iclass 32, count 0 2006.196.08:12:08.98#ibcon#*mode == 0, iclass 32, count 0 2006.196.08:12:08.98#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.196.08:12:08.98#ibcon#[26=FRQ=04,832.99\r\n] 2006.196.08:12:08.98#ibcon#*before write, iclass 32, count 0 2006.196.08:12:08.98#ibcon#enter sib2, iclass 32, count 0 2006.196.08:12:08.98#ibcon#flushed, iclass 32, count 0 2006.196.08:12:08.98#ibcon#about to write, iclass 32, count 0 2006.196.08:12:08.98#ibcon#wrote, iclass 32, count 0 2006.196.08:12:08.98#ibcon#about to read 3, iclass 32, count 0 2006.196.08:12:09.02#ibcon#read 3, iclass 32, count 0 2006.196.08:12:09.02#ibcon#about to read 4, iclass 32, count 0 2006.196.08:12:09.02#ibcon#read 4, iclass 32, count 0 2006.196.08:12:09.02#ibcon#about to read 5, iclass 32, count 0 2006.196.08:12:09.02#ibcon#read 5, iclass 32, count 0 2006.196.08:12:09.02#ibcon#about to read 6, iclass 32, count 0 2006.196.08:12:09.02#ibcon#read 6, iclass 32, count 0 2006.196.08:12:09.02#ibcon#end of sib2, iclass 32, count 0 2006.196.08:12:09.02#ibcon#*after write, iclass 32, count 0 2006.196.08:12:09.02#ibcon#*before return 0, iclass 32, count 0 2006.196.08:12:09.02#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.196.08:12:09.02#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.196.08:12:09.02#ibcon#about to clear, iclass 32 cls_cnt 0 2006.196.08:12:09.02#ibcon#cleared, iclass 32 cls_cnt 0 2006.196.08:12:09.02$vc4f8/va=4,7 2006.196.08:12:09.02#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.196.08:12:09.02#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.196.08:12:09.02#ibcon#ireg 11 cls_cnt 2 2006.196.08:12:09.02#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.196.08:12:09.08#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.196.08:12:09.08#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.196.08:12:09.08#ibcon#enter wrdev, iclass 34, count 2 2006.196.08:12:09.08#ibcon#first serial, iclass 34, count 2 2006.196.08:12:09.08#ibcon#enter sib2, iclass 34, count 2 2006.196.08:12:09.08#ibcon#flushed, iclass 34, count 2 2006.196.08:12:09.08#ibcon#about to write, iclass 34, count 2 2006.196.08:12:09.08#ibcon#wrote, iclass 34, count 2 2006.196.08:12:09.08#ibcon#about to read 3, iclass 34, count 2 2006.196.08:12:09.10#ibcon#read 3, iclass 34, count 2 2006.196.08:12:09.10#ibcon#about to read 4, iclass 34, count 2 2006.196.08:12:09.10#ibcon#read 4, iclass 34, count 2 2006.196.08:12:09.10#ibcon#about to read 5, iclass 34, count 2 2006.196.08:12:09.10#ibcon#read 5, iclass 34, count 2 2006.196.08:12:09.10#ibcon#about to read 6, iclass 34, count 2 2006.196.08:12:09.10#ibcon#read 6, iclass 34, count 2 2006.196.08:12:09.10#ibcon#end of sib2, iclass 34, count 2 2006.196.08:12:09.10#ibcon#*mode == 0, iclass 34, count 2 2006.196.08:12:09.10#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.196.08:12:09.10#ibcon#[25=AT04-07\r\n] 2006.196.08:12:09.10#ibcon#*before write, iclass 34, count 2 2006.196.08:12:09.10#ibcon#enter sib2, iclass 34, count 2 2006.196.08:12:09.10#ibcon#flushed, iclass 34, count 2 2006.196.08:12:09.10#ibcon#about to write, iclass 34, count 2 2006.196.08:12:09.10#ibcon#wrote, iclass 34, count 2 2006.196.08:12:09.10#ibcon#about to read 3, iclass 34, count 2 2006.196.08:12:09.13#ibcon#read 3, iclass 34, count 2 2006.196.08:12:09.13#ibcon#about to read 4, iclass 34, count 2 2006.196.08:12:09.13#ibcon#read 4, iclass 34, count 2 2006.196.08:12:09.13#ibcon#about to read 5, iclass 34, count 2 2006.196.08:12:09.13#ibcon#read 5, iclass 34, count 2 2006.196.08:12:09.13#ibcon#about to read 6, iclass 34, count 2 2006.196.08:12:09.13#ibcon#read 6, iclass 34, count 2 2006.196.08:12:09.13#ibcon#end of sib2, iclass 34, count 2 2006.196.08:12:09.13#ibcon#*after write, iclass 34, count 2 2006.196.08:12:09.13#ibcon#*before return 0, iclass 34, count 2 2006.196.08:12:09.13#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.196.08:12:09.13#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.196.08:12:09.13#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.196.08:12:09.13#ibcon#ireg 7 cls_cnt 0 2006.196.08:12:09.13#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.196.08:12:09.25#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.196.08:12:09.25#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.196.08:12:09.25#ibcon#enter wrdev, iclass 34, count 0 2006.196.08:12:09.25#ibcon#first serial, iclass 34, count 0 2006.196.08:12:09.25#ibcon#enter sib2, iclass 34, count 0 2006.196.08:12:09.25#ibcon#flushed, iclass 34, count 0 2006.196.08:12:09.25#ibcon#about to write, iclass 34, count 0 2006.196.08:12:09.25#ibcon#wrote, iclass 34, count 0 2006.196.08:12:09.25#ibcon#about to read 3, iclass 34, count 0 2006.196.08:12:09.27#ibcon#read 3, iclass 34, count 0 2006.196.08:12:09.27#ibcon#about to read 4, iclass 34, count 0 2006.196.08:12:09.27#ibcon#read 4, iclass 34, count 0 2006.196.08:12:09.27#ibcon#about to read 5, iclass 34, count 0 2006.196.08:12:09.27#ibcon#read 5, iclass 34, count 0 2006.196.08:12:09.27#ibcon#about to read 6, iclass 34, count 0 2006.196.08:12:09.27#ibcon#read 6, iclass 34, count 0 2006.196.08:12:09.27#ibcon#end of sib2, iclass 34, count 0 2006.196.08:12:09.27#ibcon#*mode == 0, iclass 34, count 0 2006.196.08:12:09.27#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.196.08:12:09.27#ibcon#[25=USB\r\n] 2006.196.08:12:09.27#ibcon#*before write, iclass 34, count 0 2006.196.08:12:09.27#ibcon#enter sib2, iclass 34, count 0 2006.196.08:12:09.27#ibcon#flushed, iclass 34, count 0 2006.196.08:12:09.27#ibcon#about to write, iclass 34, count 0 2006.196.08:12:09.27#ibcon#wrote, iclass 34, count 0 2006.196.08:12:09.27#ibcon#about to read 3, iclass 34, count 0 2006.196.08:12:09.30#ibcon#read 3, iclass 34, count 0 2006.196.08:12:09.30#ibcon#about to read 4, iclass 34, count 0 2006.196.08:12:09.30#ibcon#read 4, iclass 34, count 0 2006.196.08:12:09.30#ibcon#about to read 5, iclass 34, count 0 2006.196.08:12:09.30#ibcon#read 5, iclass 34, count 0 2006.196.08:12:09.30#ibcon#about to read 6, iclass 34, count 0 2006.196.08:12:09.30#ibcon#read 6, iclass 34, count 0 2006.196.08:12:09.30#ibcon#end of sib2, iclass 34, count 0 2006.196.08:12:09.30#ibcon#*after write, iclass 34, count 0 2006.196.08:12:09.30#ibcon#*before return 0, iclass 34, count 0 2006.196.08:12:09.30#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.196.08:12:09.30#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.196.08:12:09.30#ibcon#about to clear, iclass 34 cls_cnt 0 2006.196.08:12:09.30#ibcon#cleared, iclass 34 cls_cnt 0 2006.196.08:12:09.30$vc4f8/valo=5,652.99 2006.196.08:12:09.30#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.196.08:12:09.30#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.196.08:12:09.30#ibcon#ireg 17 cls_cnt 0 2006.196.08:12:09.30#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.196.08:12:09.30#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.196.08:12:09.30#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.196.08:12:09.30#ibcon#enter wrdev, iclass 36, count 0 2006.196.08:12:09.30#ibcon#first serial, iclass 36, count 0 2006.196.08:12:09.30#ibcon#enter sib2, iclass 36, count 0 2006.196.08:12:09.30#ibcon#flushed, iclass 36, count 0 2006.196.08:12:09.30#ibcon#about to write, iclass 36, count 0 2006.196.08:12:09.30#ibcon#wrote, iclass 36, count 0 2006.196.08:12:09.30#ibcon#about to read 3, iclass 36, count 0 2006.196.08:12:09.32#ibcon#read 3, iclass 36, count 0 2006.196.08:12:09.32#ibcon#about to read 4, iclass 36, count 0 2006.196.08:12:09.32#ibcon#read 4, iclass 36, count 0 2006.196.08:12:09.32#ibcon#about to read 5, iclass 36, count 0 2006.196.08:12:09.32#ibcon#read 5, iclass 36, count 0 2006.196.08:12:09.32#ibcon#about to read 6, iclass 36, count 0 2006.196.08:12:09.32#ibcon#read 6, iclass 36, count 0 2006.196.08:12:09.32#ibcon#end of sib2, iclass 36, count 0 2006.196.08:12:09.32#ibcon#*mode == 0, iclass 36, count 0 2006.196.08:12:09.32#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.196.08:12:09.32#ibcon#[26=FRQ=05,652.99\r\n] 2006.196.08:12:09.32#ibcon#*before write, iclass 36, count 0 2006.196.08:12:09.32#ibcon#enter sib2, iclass 36, count 0 2006.196.08:12:09.32#ibcon#flushed, iclass 36, count 0 2006.196.08:12:09.32#ibcon#about to write, iclass 36, count 0 2006.196.08:12:09.32#ibcon#wrote, iclass 36, count 0 2006.196.08:12:09.32#ibcon#about to read 3, iclass 36, count 0 2006.196.08:12:09.36#ibcon#read 3, iclass 36, count 0 2006.196.08:12:09.36#ibcon#about to read 4, iclass 36, count 0 2006.196.08:12:09.36#ibcon#read 4, iclass 36, count 0 2006.196.08:12:09.36#ibcon#about to read 5, iclass 36, count 0 2006.196.08:12:09.36#ibcon#read 5, iclass 36, count 0 2006.196.08:12:09.36#ibcon#about to read 6, iclass 36, count 0 2006.196.08:12:09.36#ibcon#read 6, iclass 36, count 0 2006.196.08:12:09.36#ibcon#end of sib2, iclass 36, count 0 2006.196.08:12:09.36#ibcon#*after write, iclass 36, count 0 2006.196.08:12:09.36#ibcon#*before return 0, iclass 36, count 0 2006.196.08:12:09.36#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.196.08:12:09.36#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.196.08:12:09.36#ibcon#about to clear, iclass 36 cls_cnt 0 2006.196.08:12:09.36#ibcon#cleared, iclass 36 cls_cnt 0 2006.196.08:12:09.36$vc4f8/va=5,7 2006.196.08:12:09.36#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.196.08:12:09.36#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.196.08:12:09.36#ibcon#ireg 11 cls_cnt 2 2006.196.08:12:09.36#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.196.08:12:09.42#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.196.08:12:09.42#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.196.08:12:09.42#ibcon#enter wrdev, iclass 38, count 2 2006.196.08:12:09.42#ibcon#first serial, iclass 38, count 2 2006.196.08:12:09.42#ibcon#enter sib2, iclass 38, count 2 2006.196.08:12:09.42#ibcon#flushed, iclass 38, count 2 2006.196.08:12:09.42#ibcon#about to write, iclass 38, count 2 2006.196.08:12:09.42#ibcon#wrote, iclass 38, count 2 2006.196.08:12:09.42#ibcon#about to read 3, iclass 38, count 2 2006.196.08:12:09.44#ibcon#read 3, iclass 38, count 2 2006.196.08:12:09.44#ibcon#about to read 4, iclass 38, count 2 2006.196.08:12:09.44#ibcon#read 4, iclass 38, count 2 2006.196.08:12:09.44#ibcon#about to read 5, iclass 38, count 2 2006.196.08:12:09.44#ibcon#read 5, iclass 38, count 2 2006.196.08:12:09.44#ibcon#about to read 6, iclass 38, count 2 2006.196.08:12:09.44#ibcon#read 6, iclass 38, count 2 2006.196.08:12:09.44#ibcon#end of sib2, iclass 38, count 2 2006.196.08:12:09.44#ibcon#*mode == 0, iclass 38, count 2 2006.196.08:12:09.44#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.196.08:12:09.44#ibcon#[25=AT05-07\r\n] 2006.196.08:12:09.44#ibcon#*before write, iclass 38, count 2 2006.196.08:12:09.44#ibcon#enter sib2, iclass 38, count 2 2006.196.08:12:09.44#ibcon#flushed, iclass 38, count 2 2006.196.08:12:09.44#ibcon#about to write, iclass 38, count 2 2006.196.08:12:09.44#ibcon#wrote, iclass 38, count 2 2006.196.08:12:09.44#ibcon#about to read 3, iclass 38, count 2 2006.196.08:12:09.47#ibcon#read 3, iclass 38, count 2 2006.196.08:12:09.47#ibcon#about to read 4, iclass 38, count 2 2006.196.08:12:09.47#ibcon#read 4, iclass 38, count 2 2006.196.08:12:09.47#ibcon#about to read 5, iclass 38, count 2 2006.196.08:12:09.47#ibcon#read 5, iclass 38, count 2 2006.196.08:12:09.47#ibcon#about to read 6, iclass 38, count 2 2006.196.08:12:09.47#ibcon#read 6, iclass 38, count 2 2006.196.08:12:09.47#ibcon#end of sib2, iclass 38, count 2 2006.196.08:12:09.47#ibcon#*after write, iclass 38, count 2 2006.196.08:12:09.47#ibcon#*before return 0, iclass 38, count 2 2006.196.08:12:09.47#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.196.08:12:09.47#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.196.08:12:09.47#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.196.08:12:09.47#ibcon#ireg 7 cls_cnt 0 2006.196.08:12:09.47#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.196.08:12:09.59#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.196.08:12:09.59#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.196.08:12:09.59#ibcon#enter wrdev, iclass 38, count 0 2006.196.08:12:09.59#ibcon#first serial, iclass 38, count 0 2006.196.08:12:09.59#ibcon#enter sib2, iclass 38, count 0 2006.196.08:12:09.59#ibcon#flushed, iclass 38, count 0 2006.196.08:12:09.59#ibcon#about to write, iclass 38, count 0 2006.196.08:12:09.59#ibcon#wrote, iclass 38, count 0 2006.196.08:12:09.59#ibcon#about to read 3, iclass 38, count 0 2006.196.08:12:09.61#ibcon#read 3, iclass 38, count 0 2006.196.08:12:09.61#ibcon#about to read 4, iclass 38, count 0 2006.196.08:12:09.61#ibcon#read 4, iclass 38, count 0 2006.196.08:12:09.61#ibcon#about to read 5, iclass 38, count 0 2006.196.08:12:09.61#ibcon#read 5, iclass 38, count 0 2006.196.08:12:09.61#ibcon#about to read 6, iclass 38, count 0 2006.196.08:12:09.61#ibcon#read 6, iclass 38, count 0 2006.196.08:12:09.61#ibcon#end of sib2, iclass 38, count 0 2006.196.08:12:09.61#ibcon#*mode == 0, iclass 38, count 0 2006.196.08:12:09.61#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.196.08:12:09.61#ibcon#[25=USB\r\n] 2006.196.08:12:09.61#ibcon#*before write, iclass 38, count 0 2006.196.08:12:09.61#ibcon#enter sib2, iclass 38, count 0 2006.196.08:12:09.61#ibcon#flushed, iclass 38, count 0 2006.196.08:12:09.61#ibcon#about to write, iclass 38, count 0 2006.196.08:12:09.61#ibcon#wrote, iclass 38, count 0 2006.196.08:12:09.61#ibcon#about to read 3, iclass 38, count 0 2006.196.08:12:09.64#ibcon#read 3, iclass 38, count 0 2006.196.08:12:09.64#ibcon#about to read 4, iclass 38, count 0 2006.196.08:12:09.64#ibcon#read 4, iclass 38, count 0 2006.196.08:12:09.64#ibcon#about to read 5, iclass 38, count 0 2006.196.08:12:09.64#ibcon#read 5, iclass 38, count 0 2006.196.08:12:09.64#ibcon#about to read 6, iclass 38, count 0 2006.196.08:12:09.64#ibcon#read 6, iclass 38, count 0 2006.196.08:12:09.64#ibcon#end of sib2, iclass 38, count 0 2006.196.08:12:09.64#ibcon#*after write, iclass 38, count 0 2006.196.08:12:09.64#ibcon#*before return 0, iclass 38, count 0 2006.196.08:12:09.64#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.196.08:12:09.64#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.196.08:12:09.64#ibcon#about to clear, iclass 38 cls_cnt 0 2006.196.08:12:09.64#ibcon#cleared, iclass 38 cls_cnt 0 2006.196.08:12:09.64$vc4f8/valo=6,772.99 2006.196.08:12:09.64#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.196.08:12:09.64#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.196.08:12:09.64#ibcon#ireg 17 cls_cnt 0 2006.196.08:12:09.64#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.196.08:12:09.64#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.196.08:12:09.64#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.196.08:12:09.64#ibcon#enter wrdev, iclass 40, count 0 2006.196.08:12:09.64#ibcon#first serial, iclass 40, count 0 2006.196.08:12:09.64#ibcon#enter sib2, iclass 40, count 0 2006.196.08:12:09.64#ibcon#flushed, iclass 40, count 0 2006.196.08:12:09.64#ibcon#about to write, iclass 40, count 0 2006.196.08:12:09.64#ibcon#wrote, iclass 40, count 0 2006.196.08:12:09.64#ibcon#about to read 3, iclass 40, count 0 2006.196.08:12:09.66#ibcon#read 3, iclass 40, count 0 2006.196.08:12:09.66#ibcon#about to read 4, iclass 40, count 0 2006.196.08:12:09.66#ibcon#read 4, iclass 40, count 0 2006.196.08:12:09.66#ibcon#about to read 5, iclass 40, count 0 2006.196.08:12:09.66#ibcon#read 5, iclass 40, count 0 2006.196.08:12:09.66#ibcon#about to read 6, iclass 40, count 0 2006.196.08:12:09.66#ibcon#read 6, iclass 40, count 0 2006.196.08:12:09.66#ibcon#end of sib2, iclass 40, count 0 2006.196.08:12:09.66#ibcon#*mode == 0, iclass 40, count 0 2006.196.08:12:09.66#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.196.08:12:09.66#ibcon#[26=FRQ=06,772.99\r\n] 2006.196.08:12:09.66#ibcon#*before write, iclass 40, count 0 2006.196.08:12:09.66#ibcon#enter sib2, iclass 40, count 0 2006.196.08:12:09.66#ibcon#flushed, iclass 40, count 0 2006.196.08:12:09.66#ibcon#about to write, iclass 40, count 0 2006.196.08:12:09.66#ibcon#wrote, iclass 40, count 0 2006.196.08:12:09.66#ibcon#about to read 3, iclass 40, count 0 2006.196.08:12:09.71#ibcon#read 3, iclass 40, count 0 2006.196.08:12:09.71#ibcon#about to read 4, iclass 40, count 0 2006.196.08:12:09.71#ibcon#read 4, iclass 40, count 0 2006.196.08:12:09.71#ibcon#about to read 5, iclass 40, count 0 2006.196.08:12:09.71#ibcon#read 5, iclass 40, count 0 2006.196.08:12:09.71#ibcon#about to read 6, iclass 40, count 0 2006.196.08:12:09.71#ibcon#read 6, iclass 40, count 0 2006.196.08:12:09.71#ibcon#end of sib2, iclass 40, count 0 2006.196.08:12:09.71#ibcon#*after write, iclass 40, count 0 2006.196.08:12:09.71#ibcon#*before return 0, iclass 40, count 0 2006.196.08:12:09.71#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.196.08:12:09.71#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.196.08:12:09.71#ibcon#about to clear, iclass 40 cls_cnt 0 2006.196.08:12:09.71#ibcon#cleared, iclass 40 cls_cnt 0 2006.196.08:12:09.71$vc4f8/va=6,6 2006.196.08:12:09.71#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.196.08:12:09.71#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.196.08:12:09.71#ibcon#ireg 11 cls_cnt 2 2006.196.08:12:09.71#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.196.08:12:09.76#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.196.08:12:09.76#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.196.08:12:09.76#ibcon#enter wrdev, iclass 4, count 2 2006.196.08:12:09.76#ibcon#first serial, iclass 4, count 2 2006.196.08:12:09.76#ibcon#enter sib2, iclass 4, count 2 2006.196.08:12:09.76#ibcon#flushed, iclass 4, count 2 2006.196.08:12:09.76#ibcon#about to write, iclass 4, count 2 2006.196.08:12:09.76#ibcon#wrote, iclass 4, count 2 2006.196.08:12:09.76#ibcon#about to read 3, iclass 4, count 2 2006.196.08:12:09.78#ibcon#read 3, iclass 4, count 2 2006.196.08:12:09.78#ibcon#about to read 4, iclass 4, count 2 2006.196.08:12:09.78#ibcon#read 4, iclass 4, count 2 2006.196.08:12:09.78#ibcon#about to read 5, iclass 4, count 2 2006.196.08:12:09.78#ibcon#read 5, iclass 4, count 2 2006.196.08:12:09.78#ibcon#about to read 6, iclass 4, count 2 2006.196.08:12:09.78#ibcon#read 6, iclass 4, count 2 2006.196.08:12:09.78#ibcon#end of sib2, iclass 4, count 2 2006.196.08:12:09.78#ibcon#*mode == 0, iclass 4, count 2 2006.196.08:12:09.78#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.196.08:12:09.78#ibcon#[25=AT06-06\r\n] 2006.196.08:12:09.78#ibcon#*before write, iclass 4, count 2 2006.196.08:12:09.78#ibcon#enter sib2, iclass 4, count 2 2006.196.08:12:09.78#ibcon#flushed, iclass 4, count 2 2006.196.08:12:09.78#ibcon#about to write, iclass 4, count 2 2006.196.08:12:09.78#ibcon#wrote, iclass 4, count 2 2006.196.08:12:09.78#ibcon#about to read 3, iclass 4, count 2 2006.196.08:12:09.81#ibcon#read 3, iclass 4, count 2 2006.196.08:12:09.81#ibcon#about to read 4, iclass 4, count 2 2006.196.08:12:09.81#ibcon#read 4, iclass 4, count 2 2006.196.08:12:09.81#ibcon#about to read 5, iclass 4, count 2 2006.196.08:12:09.81#ibcon#read 5, iclass 4, count 2 2006.196.08:12:09.81#ibcon#about to read 6, iclass 4, count 2 2006.196.08:12:09.81#ibcon#read 6, iclass 4, count 2 2006.196.08:12:09.81#ibcon#end of sib2, iclass 4, count 2 2006.196.08:12:09.81#ibcon#*after write, iclass 4, count 2 2006.196.08:12:09.81#ibcon#*before return 0, iclass 4, count 2 2006.196.08:12:09.81#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.196.08:12:09.81#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.196.08:12:09.81#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.196.08:12:09.81#ibcon#ireg 7 cls_cnt 0 2006.196.08:12:09.81#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.196.08:12:09.93#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.196.08:12:09.93#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.196.08:12:09.93#ibcon#enter wrdev, iclass 4, count 0 2006.196.08:12:09.93#ibcon#first serial, iclass 4, count 0 2006.196.08:12:09.93#ibcon#enter sib2, iclass 4, count 0 2006.196.08:12:09.93#ibcon#flushed, iclass 4, count 0 2006.196.08:12:09.93#ibcon#about to write, iclass 4, count 0 2006.196.08:12:09.93#ibcon#wrote, iclass 4, count 0 2006.196.08:12:09.93#ibcon#about to read 3, iclass 4, count 0 2006.196.08:12:09.95#ibcon#read 3, iclass 4, count 0 2006.196.08:12:09.95#ibcon#about to read 4, iclass 4, count 0 2006.196.08:12:09.95#ibcon#read 4, iclass 4, count 0 2006.196.08:12:09.95#ibcon#about to read 5, iclass 4, count 0 2006.196.08:12:09.95#ibcon#read 5, iclass 4, count 0 2006.196.08:12:09.95#ibcon#about to read 6, iclass 4, count 0 2006.196.08:12:09.95#ibcon#read 6, iclass 4, count 0 2006.196.08:12:09.95#ibcon#end of sib2, iclass 4, count 0 2006.196.08:12:09.95#ibcon#*mode == 0, iclass 4, count 0 2006.196.08:12:09.95#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.196.08:12:09.95#ibcon#[25=USB\r\n] 2006.196.08:12:09.95#ibcon#*before write, iclass 4, count 0 2006.196.08:12:09.95#ibcon#enter sib2, iclass 4, count 0 2006.196.08:12:09.95#ibcon#flushed, iclass 4, count 0 2006.196.08:12:09.95#ibcon#about to write, iclass 4, count 0 2006.196.08:12:09.95#ibcon#wrote, iclass 4, count 0 2006.196.08:12:09.95#ibcon#about to read 3, iclass 4, count 0 2006.196.08:12:09.98#ibcon#read 3, iclass 4, count 0 2006.196.08:12:09.98#ibcon#about to read 4, iclass 4, count 0 2006.196.08:12:09.98#ibcon#read 4, iclass 4, count 0 2006.196.08:12:09.98#ibcon#about to read 5, iclass 4, count 0 2006.196.08:12:09.98#ibcon#read 5, iclass 4, count 0 2006.196.08:12:09.98#ibcon#about to read 6, iclass 4, count 0 2006.196.08:12:09.98#ibcon#read 6, iclass 4, count 0 2006.196.08:12:09.98#ibcon#end of sib2, iclass 4, count 0 2006.196.08:12:09.98#ibcon#*after write, iclass 4, count 0 2006.196.08:12:09.98#ibcon#*before return 0, iclass 4, count 0 2006.196.08:12:09.98#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.196.08:12:09.98#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.196.08:12:09.98#ibcon#about to clear, iclass 4 cls_cnt 0 2006.196.08:12:09.98#ibcon#cleared, iclass 4 cls_cnt 0 2006.196.08:12:09.98$vc4f8/valo=7,832.99 2006.196.08:12:09.98#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.196.08:12:09.98#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.196.08:12:09.98#ibcon#ireg 17 cls_cnt 0 2006.196.08:12:09.98#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.196.08:12:09.98#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.196.08:12:09.98#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.196.08:12:09.98#ibcon#enter wrdev, iclass 6, count 0 2006.196.08:12:09.98#ibcon#first serial, iclass 6, count 0 2006.196.08:12:09.98#ibcon#enter sib2, iclass 6, count 0 2006.196.08:12:09.98#ibcon#flushed, iclass 6, count 0 2006.196.08:12:09.98#ibcon#about to write, iclass 6, count 0 2006.196.08:12:09.98#ibcon#wrote, iclass 6, count 0 2006.196.08:12:09.98#ibcon#about to read 3, iclass 6, count 0 2006.196.08:12:10.00#ibcon#read 3, iclass 6, count 0 2006.196.08:12:10.00#ibcon#about to read 4, iclass 6, count 0 2006.196.08:12:10.00#ibcon#read 4, iclass 6, count 0 2006.196.08:12:10.00#ibcon#about to read 5, iclass 6, count 0 2006.196.08:12:10.00#ibcon#read 5, iclass 6, count 0 2006.196.08:12:10.00#ibcon#about to read 6, iclass 6, count 0 2006.196.08:12:10.00#ibcon#read 6, iclass 6, count 0 2006.196.08:12:10.00#ibcon#end of sib2, iclass 6, count 0 2006.196.08:12:10.00#ibcon#*mode == 0, iclass 6, count 0 2006.196.08:12:10.00#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.196.08:12:10.00#ibcon#[26=FRQ=07,832.99\r\n] 2006.196.08:12:10.00#ibcon#*before write, iclass 6, count 0 2006.196.08:12:10.00#ibcon#enter sib2, iclass 6, count 0 2006.196.08:12:10.00#ibcon#flushed, iclass 6, count 0 2006.196.08:12:10.00#ibcon#about to write, iclass 6, count 0 2006.196.08:12:10.00#ibcon#wrote, iclass 6, count 0 2006.196.08:12:10.00#ibcon#about to read 3, iclass 6, count 0 2006.196.08:12:10.04#ibcon#read 3, iclass 6, count 0 2006.196.08:12:10.04#ibcon#about to read 4, iclass 6, count 0 2006.196.08:12:10.04#ibcon#read 4, iclass 6, count 0 2006.196.08:12:10.04#ibcon#about to read 5, iclass 6, count 0 2006.196.08:12:10.04#ibcon#read 5, iclass 6, count 0 2006.196.08:12:10.04#ibcon#about to read 6, iclass 6, count 0 2006.196.08:12:10.04#ibcon#read 6, iclass 6, count 0 2006.196.08:12:10.04#ibcon#end of sib2, iclass 6, count 0 2006.196.08:12:10.04#ibcon#*after write, iclass 6, count 0 2006.196.08:12:10.04#ibcon#*before return 0, iclass 6, count 0 2006.196.08:12:10.04#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.196.08:12:10.04#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.196.08:12:10.04#ibcon#about to clear, iclass 6 cls_cnt 0 2006.196.08:12:10.04#ibcon#cleared, iclass 6 cls_cnt 0 2006.196.08:12:10.04$vc4f8/va=7,6 2006.196.08:12:10.04#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.196.08:12:10.04#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.196.08:12:10.04#ibcon#ireg 11 cls_cnt 2 2006.196.08:12:10.04#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.196.08:12:10.10#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.196.08:12:10.10#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.196.08:12:10.10#ibcon#enter wrdev, iclass 10, count 2 2006.196.08:12:10.10#ibcon#first serial, iclass 10, count 2 2006.196.08:12:10.10#ibcon#enter sib2, iclass 10, count 2 2006.196.08:12:10.10#ibcon#flushed, iclass 10, count 2 2006.196.08:12:10.10#ibcon#about to write, iclass 10, count 2 2006.196.08:12:10.10#ibcon#wrote, iclass 10, count 2 2006.196.08:12:10.10#ibcon#about to read 3, iclass 10, count 2 2006.196.08:12:10.12#ibcon#read 3, iclass 10, count 2 2006.196.08:12:10.12#ibcon#about to read 4, iclass 10, count 2 2006.196.08:12:10.12#ibcon#read 4, iclass 10, count 2 2006.196.08:12:10.12#ibcon#about to read 5, iclass 10, count 2 2006.196.08:12:10.12#ibcon#read 5, iclass 10, count 2 2006.196.08:12:10.12#ibcon#about to read 6, iclass 10, count 2 2006.196.08:12:10.12#ibcon#read 6, iclass 10, count 2 2006.196.08:12:10.12#ibcon#end of sib2, iclass 10, count 2 2006.196.08:12:10.12#ibcon#*mode == 0, iclass 10, count 2 2006.196.08:12:10.12#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.196.08:12:10.12#ibcon#[25=AT07-06\r\n] 2006.196.08:12:10.12#ibcon#*before write, iclass 10, count 2 2006.196.08:12:10.12#ibcon#enter sib2, iclass 10, count 2 2006.196.08:12:10.12#ibcon#flushed, iclass 10, count 2 2006.196.08:12:10.12#ibcon#about to write, iclass 10, count 2 2006.196.08:12:10.12#ibcon#wrote, iclass 10, count 2 2006.196.08:12:10.12#ibcon#about to read 3, iclass 10, count 2 2006.196.08:12:10.15#ibcon#read 3, iclass 10, count 2 2006.196.08:12:10.15#ibcon#about to read 4, iclass 10, count 2 2006.196.08:12:10.15#ibcon#read 4, iclass 10, count 2 2006.196.08:12:10.15#ibcon#about to read 5, iclass 10, count 2 2006.196.08:12:10.15#ibcon#read 5, iclass 10, count 2 2006.196.08:12:10.15#ibcon#about to read 6, iclass 10, count 2 2006.196.08:12:10.15#ibcon#read 6, iclass 10, count 2 2006.196.08:12:10.15#ibcon#end of sib2, iclass 10, count 2 2006.196.08:12:10.15#ibcon#*after write, iclass 10, count 2 2006.196.08:12:10.15#ibcon#*before return 0, iclass 10, count 2 2006.196.08:12:10.15#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.196.08:12:10.15#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.196.08:12:10.15#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.196.08:12:10.15#ibcon#ireg 7 cls_cnt 0 2006.196.08:12:10.15#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.196.08:12:10.27#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.196.08:12:10.27#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.196.08:12:10.27#ibcon#enter wrdev, iclass 10, count 0 2006.196.08:12:10.27#ibcon#first serial, iclass 10, count 0 2006.196.08:12:10.27#ibcon#enter sib2, iclass 10, count 0 2006.196.08:12:10.27#ibcon#flushed, iclass 10, count 0 2006.196.08:12:10.27#ibcon#about to write, iclass 10, count 0 2006.196.08:12:10.27#ibcon#wrote, iclass 10, count 0 2006.196.08:12:10.27#ibcon#about to read 3, iclass 10, count 0 2006.196.08:12:10.29#ibcon#read 3, iclass 10, count 0 2006.196.08:12:10.29#ibcon#about to read 4, iclass 10, count 0 2006.196.08:12:10.29#ibcon#read 4, iclass 10, count 0 2006.196.08:12:10.29#ibcon#about to read 5, iclass 10, count 0 2006.196.08:12:10.29#ibcon#read 5, iclass 10, count 0 2006.196.08:12:10.29#ibcon#about to read 6, iclass 10, count 0 2006.196.08:12:10.29#ibcon#read 6, iclass 10, count 0 2006.196.08:12:10.29#ibcon#end of sib2, iclass 10, count 0 2006.196.08:12:10.29#ibcon#*mode == 0, iclass 10, count 0 2006.196.08:12:10.29#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.196.08:12:10.29#ibcon#[25=USB\r\n] 2006.196.08:12:10.29#ibcon#*before write, iclass 10, count 0 2006.196.08:12:10.29#ibcon#enter sib2, iclass 10, count 0 2006.196.08:12:10.29#ibcon#flushed, iclass 10, count 0 2006.196.08:12:10.29#ibcon#about to write, iclass 10, count 0 2006.196.08:12:10.29#ibcon#wrote, iclass 10, count 0 2006.196.08:12:10.29#ibcon#about to read 3, iclass 10, count 0 2006.196.08:12:10.32#ibcon#read 3, iclass 10, count 0 2006.196.08:12:10.32#ibcon#about to read 4, iclass 10, count 0 2006.196.08:12:10.32#ibcon#read 4, iclass 10, count 0 2006.196.08:12:10.32#ibcon#about to read 5, iclass 10, count 0 2006.196.08:12:10.32#ibcon#read 5, iclass 10, count 0 2006.196.08:12:10.32#ibcon#about to read 6, iclass 10, count 0 2006.196.08:12:10.32#ibcon#read 6, iclass 10, count 0 2006.196.08:12:10.32#ibcon#end of sib2, iclass 10, count 0 2006.196.08:12:10.32#ibcon#*after write, iclass 10, count 0 2006.196.08:12:10.32#ibcon#*before return 0, iclass 10, count 0 2006.196.08:12:10.32#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.196.08:12:10.32#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.196.08:12:10.32#ibcon#about to clear, iclass 10 cls_cnt 0 2006.196.08:12:10.32#ibcon#cleared, iclass 10 cls_cnt 0 2006.196.08:12:10.32$vc4f8/valo=8,852.99 2006.196.08:12:10.32#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.196.08:12:10.32#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.196.08:12:10.32#ibcon#ireg 17 cls_cnt 0 2006.196.08:12:10.32#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.196.08:12:10.32#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.196.08:12:10.32#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.196.08:12:10.32#ibcon#enter wrdev, iclass 12, count 0 2006.196.08:12:10.32#ibcon#first serial, iclass 12, count 0 2006.196.08:12:10.32#ibcon#enter sib2, iclass 12, count 0 2006.196.08:12:10.32#ibcon#flushed, iclass 12, count 0 2006.196.08:12:10.32#ibcon#about to write, iclass 12, count 0 2006.196.08:12:10.32#ibcon#wrote, iclass 12, count 0 2006.196.08:12:10.32#ibcon#about to read 3, iclass 12, count 0 2006.196.08:12:10.34#ibcon#read 3, iclass 12, count 0 2006.196.08:12:10.34#ibcon#about to read 4, iclass 12, count 0 2006.196.08:12:10.34#ibcon#read 4, iclass 12, count 0 2006.196.08:12:10.34#ibcon#about to read 5, iclass 12, count 0 2006.196.08:12:10.34#ibcon#read 5, iclass 12, count 0 2006.196.08:12:10.34#ibcon#about to read 6, iclass 12, count 0 2006.196.08:12:10.34#ibcon#read 6, iclass 12, count 0 2006.196.08:12:10.34#ibcon#end of sib2, iclass 12, count 0 2006.196.08:12:10.34#ibcon#*mode == 0, iclass 12, count 0 2006.196.08:12:10.34#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.196.08:12:10.34#ibcon#[26=FRQ=08,852.99\r\n] 2006.196.08:12:10.34#ibcon#*before write, iclass 12, count 0 2006.196.08:12:10.34#ibcon#enter sib2, iclass 12, count 0 2006.196.08:12:10.34#ibcon#flushed, iclass 12, count 0 2006.196.08:12:10.34#ibcon#about to write, iclass 12, count 0 2006.196.08:12:10.34#ibcon#wrote, iclass 12, count 0 2006.196.08:12:10.34#ibcon#about to read 3, iclass 12, count 0 2006.196.08:12:10.39#ibcon#read 3, iclass 12, count 0 2006.196.08:12:10.39#ibcon#about to read 4, iclass 12, count 0 2006.196.08:12:10.39#ibcon#read 4, iclass 12, count 0 2006.196.08:12:10.39#ibcon#about to read 5, iclass 12, count 0 2006.196.08:12:10.39#ibcon#read 5, iclass 12, count 0 2006.196.08:12:10.39#ibcon#about to read 6, iclass 12, count 0 2006.196.08:12:10.39#ibcon#read 6, iclass 12, count 0 2006.196.08:12:10.39#ibcon#end of sib2, iclass 12, count 0 2006.196.08:12:10.39#ibcon#*after write, iclass 12, count 0 2006.196.08:12:10.39#ibcon#*before return 0, iclass 12, count 0 2006.196.08:12:10.39#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.196.08:12:10.39#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.196.08:12:10.39#ibcon#about to clear, iclass 12 cls_cnt 0 2006.196.08:12:10.39#ibcon#cleared, iclass 12 cls_cnt 0 2006.196.08:12:10.39$vc4f8/va=8,7 2006.196.08:12:10.39#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.196.08:12:10.39#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.196.08:12:10.39#ibcon#ireg 11 cls_cnt 2 2006.196.08:12:10.39#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.196.08:12:10.44#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.196.08:12:10.44#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.196.08:12:10.44#ibcon#enter wrdev, iclass 14, count 2 2006.196.08:12:10.44#ibcon#first serial, iclass 14, count 2 2006.196.08:12:10.44#ibcon#enter sib2, iclass 14, count 2 2006.196.08:12:10.44#ibcon#flushed, iclass 14, count 2 2006.196.08:12:10.44#ibcon#about to write, iclass 14, count 2 2006.196.08:12:10.44#ibcon#wrote, iclass 14, count 2 2006.196.08:12:10.44#ibcon#about to read 3, iclass 14, count 2 2006.196.08:12:10.46#ibcon#read 3, iclass 14, count 2 2006.196.08:12:10.46#ibcon#about to read 4, iclass 14, count 2 2006.196.08:12:10.46#ibcon#read 4, iclass 14, count 2 2006.196.08:12:10.46#ibcon#about to read 5, iclass 14, count 2 2006.196.08:12:10.46#ibcon#read 5, iclass 14, count 2 2006.196.08:12:10.46#ibcon#about to read 6, iclass 14, count 2 2006.196.08:12:10.46#ibcon#read 6, iclass 14, count 2 2006.196.08:12:10.46#ibcon#end of sib2, iclass 14, count 2 2006.196.08:12:10.46#ibcon#*mode == 0, iclass 14, count 2 2006.196.08:12:10.46#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.196.08:12:10.46#ibcon#[25=AT08-07\r\n] 2006.196.08:12:10.46#ibcon#*before write, iclass 14, count 2 2006.196.08:12:10.46#ibcon#enter sib2, iclass 14, count 2 2006.196.08:12:10.46#ibcon#flushed, iclass 14, count 2 2006.196.08:12:10.46#ibcon#about to write, iclass 14, count 2 2006.196.08:12:10.46#ibcon#wrote, iclass 14, count 2 2006.196.08:12:10.46#ibcon#about to read 3, iclass 14, count 2 2006.196.08:12:10.49#ibcon#read 3, iclass 14, count 2 2006.196.08:12:10.49#ibcon#about to read 4, iclass 14, count 2 2006.196.08:12:10.49#ibcon#read 4, iclass 14, count 2 2006.196.08:12:10.49#ibcon#about to read 5, iclass 14, count 2 2006.196.08:12:10.49#ibcon#read 5, iclass 14, count 2 2006.196.08:12:10.49#ibcon#about to read 6, iclass 14, count 2 2006.196.08:12:10.49#ibcon#read 6, iclass 14, count 2 2006.196.08:12:10.49#ibcon#end of sib2, iclass 14, count 2 2006.196.08:12:10.49#ibcon#*after write, iclass 14, count 2 2006.196.08:12:10.49#ibcon#*before return 0, iclass 14, count 2 2006.196.08:12:10.49#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.196.08:12:10.49#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.196.08:12:10.49#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.196.08:12:10.49#ibcon#ireg 7 cls_cnt 0 2006.196.08:12:10.49#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.196.08:12:10.61#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.196.08:12:10.61#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.196.08:12:10.61#ibcon#enter wrdev, iclass 14, count 0 2006.196.08:12:10.61#ibcon#first serial, iclass 14, count 0 2006.196.08:12:10.61#ibcon#enter sib2, iclass 14, count 0 2006.196.08:12:10.61#ibcon#flushed, iclass 14, count 0 2006.196.08:12:10.61#ibcon#about to write, iclass 14, count 0 2006.196.08:12:10.61#ibcon#wrote, iclass 14, count 0 2006.196.08:12:10.61#ibcon#about to read 3, iclass 14, count 0 2006.196.08:12:10.63#ibcon#read 3, iclass 14, count 0 2006.196.08:12:10.63#ibcon#about to read 4, iclass 14, count 0 2006.196.08:12:10.63#ibcon#read 4, iclass 14, count 0 2006.196.08:12:10.63#ibcon#about to read 5, iclass 14, count 0 2006.196.08:12:10.63#ibcon#read 5, iclass 14, count 0 2006.196.08:12:10.63#ibcon#about to read 6, iclass 14, count 0 2006.196.08:12:10.63#ibcon#read 6, iclass 14, count 0 2006.196.08:12:10.63#ibcon#end of sib2, iclass 14, count 0 2006.196.08:12:10.63#ibcon#*mode == 0, iclass 14, count 0 2006.196.08:12:10.63#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.196.08:12:10.63#ibcon#[25=USB\r\n] 2006.196.08:12:10.63#ibcon#*before write, iclass 14, count 0 2006.196.08:12:10.63#ibcon#enter sib2, iclass 14, count 0 2006.196.08:12:10.63#ibcon#flushed, iclass 14, count 0 2006.196.08:12:10.63#ibcon#about to write, iclass 14, count 0 2006.196.08:12:10.63#ibcon#wrote, iclass 14, count 0 2006.196.08:12:10.63#ibcon#about to read 3, iclass 14, count 0 2006.196.08:12:10.66#abcon#<5=/04 3.8 6.8 29.20 921003.9\r\n> 2006.196.08:12:10.66#ibcon#read 3, iclass 14, count 0 2006.196.08:12:10.66#ibcon#about to read 4, iclass 14, count 0 2006.196.08:12:10.66#ibcon#read 4, iclass 14, count 0 2006.196.08:12:10.66#ibcon#about to read 5, iclass 14, count 0 2006.196.08:12:10.66#ibcon#read 5, iclass 14, count 0 2006.196.08:12:10.66#ibcon#about to read 6, iclass 14, count 0 2006.196.08:12:10.66#ibcon#read 6, iclass 14, count 0 2006.196.08:12:10.66#ibcon#end of sib2, iclass 14, count 0 2006.196.08:12:10.66#ibcon#*after write, iclass 14, count 0 2006.196.08:12:10.66#ibcon#*before return 0, iclass 14, count 0 2006.196.08:12:10.66#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.196.08:12:10.66#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.196.08:12:10.66#ibcon#about to clear, iclass 14 cls_cnt 0 2006.196.08:12:10.66#ibcon#cleared, iclass 14 cls_cnt 0 2006.196.08:12:10.66$vc4f8/vblo=1,632.99 2006.196.08:12:10.66#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.196.08:12:10.66#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.196.08:12:10.66#ibcon#ireg 17 cls_cnt 0 2006.196.08:12:10.66#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.196.08:12:10.66#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.196.08:12:10.66#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.196.08:12:10.66#ibcon#enter wrdev, iclass 19, count 0 2006.196.08:12:10.66#ibcon#first serial, iclass 19, count 0 2006.196.08:12:10.66#ibcon#enter sib2, iclass 19, count 0 2006.196.08:12:10.66#ibcon#flushed, iclass 19, count 0 2006.196.08:12:10.66#ibcon#about to write, iclass 19, count 0 2006.196.08:12:10.66#ibcon#wrote, iclass 19, count 0 2006.196.08:12:10.66#ibcon#about to read 3, iclass 19, count 0 2006.196.08:12:10.68#abcon#{5=INTERFACE CLEAR} 2006.196.08:12:10.68#ibcon#read 3, iclass 19, count 0 2006.196.08:12:10.68#ibcon#about to read 4, iclass 19, count 0 2006.196.08:12:10.68#ibcon#read 4, iclass 19, count 0 2006.196.08:12:10.68#ibcon#about to read 5, iclass 19, count 0 2006.196.08:12:10.68#ibcon#read 5, iclass 19, count 0 2006.196.08:12:10.68#ibcon#about to read 6, iclass 19, count 0 2006.196.08:12:10.68#ibcon#read 6, iclass 19, count 0 2006.196.08:12:10.68#ibcon#end of sib2, iclass 19, count 0 2006.196.08:12:10.68#ibcon#*mode == 0, iclass 19, count 0 2006.196.08:12:10.68#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.196.08:12:10.68#ibcon#[28=FRQ=01,632.99\r\n] 2006.196.08:12:10.68#ibcon#*before write, iclass 19, count 0 2006.196.08:12:10.68#ibcon#enter sib2, iclass 19, count 0 2006.196.08:12:10.68#ibcon#flushed, iclass 19, count 0 2006.196.08:12:10.68#ibcon#about to write, iclass 19, count 0 2006.196.08:12:10.68#ibcon#wrote, iclass 19, count 0 2006.196.08:12:10.68#ibcon#about to read 3, iclass 19, count 0 2006.196.08:12:10.72#ibcon#read 3, iclass 19, count 0 2006.196.08:12:10.72#ibcon#about to read 4, iclass 19, count 0 2006.196.08:12:10.72#ibcon#read 4, iclass 19, count 0 2006.196.08:12:10.72#ibcon#about to read 5, iclass 19, count 0 2006.196.08:12:10.72#ibcon#read 5, iclass 19, count 0 2006.196.08:12:10.72#ibcon#about to read 6, iclass 19, count 0 2006.196.08:12:10.72#ibcon#read 6, iclass 19, count 0 2006.196.08:12:10.72#ibcon#end of sib2, iclass 19, count 0 2006.196.08:12:10.72#ibcon#*after write, iclass 19, count 0 2006.196.08:12:10.72#ibcon#*before return 0, iclass 19, count 0 2006.196.08:12:10.72#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.196.08:12:10.72#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.196.08:12:10.72#ibcon#about to clear, iclass 19 cls_cnt 0 2006.196.08:12:10.72#ibcon#cleared, iclass 19 cls_cnt 0 2006.196.08:12:10.72$vc4f8/vb=1,4 2006.196.08:12:10.72#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.196.08:12:10.72#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.196.08:12:10.72#ibcon#ireg 11 cls_cnt 2 2006.196.08:12:10.72#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.196.08:12:10.72#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.196.08:12:10.72#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.196.08:12:10.72#ibcon#enter wrdev, iclass 21, count 2 2006.196.08:12:10.72#ibcon#first serial, iclass 21, count 2 2006.196.08:12:10.72#ibcon#enter sib2, iclass 21, count 2 2006.196.08:12:10.72#ibcon#flushed, iclass 21, count 2 2006.196.08:12:10.72#ibcon#about to write, iclass 21, count 2 2006.196.08:12:10.72#ibcon#wrote, iclass 21, count 2 2006.196.08:12:10.72#ibcon#about to read 3, iclass 21, count 2 2006.196.08:12:10.74#ibcon#read 3, iclass 21, count 2 2006.196.08:12:10.74#ibcon#about to read 4, iclass 21, count 2 2006.196.08:12:10.74#ibcon#read 4, iclass 21, count 2 2006.196.08:12:10.74#ibcon#about to read 5, iclass 21, count 2 2006.196.08:12:10.74#ibcon#read 5, iclass 21, count 2 2006.196.08:12:10.74#ibcon#about to read 6, iclass 21, count 2 2006.196.08:12:10.74#ibcon#read 6, iclass 21, count 2 2006.196.08:12:10.74#ibcon#end of sib2, iclass 21, count 2 2006.196.08:12:10.74#ibcon#*mode == 0, iclass 21, count 2 2006.196.08:12:10.74#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.196.08:12:10.74#ibcon#[27=AT01-04\r\n] 2006.196.08:12:10.74#ibcon#*before write, iclass 21, count 2 2006.196.08:12:10.74#ibcon#enter sib2, iclass 21, count 2 2006.196.08:12:10.74#ibcon#flushed, iclass 21, count 2 2006.196.08:12:10.74#ibcon#about to write, iclass 21, count 2 2006.196.08:12:10.74#ibcon#wrote, iclass 21, count 2 2006.196.08:12:10.74#ibcon#about to read 3, iclass 21, count 2 2006.196.08:12:10.74#abcon#[5=S1D000X0/0*\r\n] 2006.196.08:12:10.77#ibcon#read 3, iclass 21, count 2 2006.196.08:12:10.77#ibcon#about to read 4, iclass 21, count 2 2006.196.08:12:10.77#ibcon#read 4, iclass 21, count 2 2006.196.08:12:10.77#ibcon#about to read 5, iclass 21, count 2 2006.196.08:12:10.77#ibcon#read 5, iclass 21, count 2 2006.196.08:12:10.77#ibcon#about to read 6, iclass 21, count 2 2006.196.08:12:10.77#ibcon#read 6, iclass 21, count 2 2006.196.08:12:10.77#ibcon#end of sib2, iclass 21, count 2 2006.196.08:12:10.77#ibcon#*after write, iclass 21, count 2 2006.196.08:12:10.77#ibcon#*before return 0, iclass 21, count 2 2006.196.08:12:10.77#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.196.08:12:10.77#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.196.08:12:10.77#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.196.08:12:10.77#ibcon#ireg 7 cls_cnt 0 2006.196.08:12:10.77#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.196.08:12:10.89#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.196.08:12:10.89#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.196.08:12:10.89#ibcon#enter wrdev, iclass 21, count 0 2006.196.08:12:10.89#ibcon#first serial, iclass 21, count 0 2006.196.08:12:10.89#ibcon#enter sib2, iclass 21, count 0 2006.196.08:12:10.89#ibcon#flushed, iclass 21, count 0 2006.196.08:12:10.89#ibcon#about to write, iclass 21, count 0 2006.196.08:12:10.89#ibcon#wrote, iclass 21, count 0 2006.196.08:12:10.89#ibcon#about to read 3, iclass 21, count 0 2006.196.08:12:10.91#ibcon#read 3, iclass 21, count 0 2006.196.08:12:10.91#ibcon#about to read 4, iclass 21, count 0 2006.196.08:12:10.91#ibcon#read 4, iclass 21, count 0 2006.196.08:12:10.91#ibcon#about to read 5, iclass 21, count 0 2006.196.08:12:10.91#ibcon#read 5, iclass 21, count 0 2006.196.08:12:10.91#ibcon#about to read 6, iclass 21, count 0 2006.196.08:12:10.91#ibcon#read 6, iclass 21, count 0 2006.196.08:12:10.91#ibcon#end of sib2, iclass 21, count 0 2006.196.08:12:10.91#ibcon#*mode == 0, iclass 21, count 0 2006.196.08:12:10.91#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.196.08:12:10.91#ibcon#[27=USB\r\n] 2006.196.08:12:10.91#ibcon#*before write, iclass 21, count 0 2006.196.08:12:10.91#ibcon#enter sib2, iclass 21, count 0 2006.196.08:12:10.91#ibcon#flushed, iclass 21, count 0 2006.196.08:12:10.91#ibcon#about to write, iclass 21, count 0 2006.196.08:12:10.91#ibcon#wrote, iclass 21, count 0 2006.196.08:12:10.91#ibcon#about to read 3, iclass 21, count 0 2006.196.08:12:10.94#ibcon#read 3, iclass 21, count 0 2006.196.08:12:10.94#ibcon#about to read 4, iclass 21, count 0 2006.196.08:12:10.94#ibcon#read 4, iclass 21, count 0 2006.196.08:12:10.94#ibcon#about to read 5, iclass 21, count 0 2006.196.08:12:10.94#ibcon#read 5, iclass 21, count 0 2006.196.08:12:10.94#ibcon#about to read 6, iclass 21, count 0 2006.196.08:12:10.94#ibcon#read 6, iclass 21, count 0 2006.196.08:12:10.94#ibcon#end of sib2, iclass 21, count 0 2006.196.08:12:10.94#ibcon#*after write, iclass 21, count 0 2006.196.08:12:10.94#ibcon#*before return 0, iclass 21, count 0 2006.196.08:12:10.94#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.196.08:12:10.94#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.196.08:12:10.94#ibcon#about to clear, iclass 21 cls_cnt 0 2006.196.08:12:10.94#ibcon#cleared, iclass 21 cls_cnt 0 2006.196.08:12:10.94$vc4f8/vblo=2,640.99 2006.196.08:12:10.94#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.196.08:12:10.94#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.196.08:12:10.94#ibcon#ireg 17 cls_cnt 0 2006.196.08:12:10.94#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.196.08:12:10.94#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.196.08:12:10.94#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.196.08:12:10.94#ibcon#enter wrdev, iclass 24, count 0 2006.196.08:12:10.94#ibcon#first serial, iclass 24, count 0 2006.196.08:12:10.94#ibcon#enter sib2, iclass 24, count 0 2006.196.08:12:10.94#ibcon#flushed, iclass 24, count 0 2006.196.08:12:10.94#ibcon#about to write, iclass 24, count 0 2006.196.08:12:10.94#ibcon#wrote, iclass 24, count 0 2006.196.08:12:10.94#ibcon#about to read 3, iclass 24, count 0 2006.196.08:12:10.96#ibcon#read 3, iclass 24, count 0 2006.196.08:12:10.96#ibcon#about to read 4, iclass 24, count 0 2006.196.08:12:10.96#ibcon#read 4, iclass 24, count 0 2006.196.08:12:10.96#ibcon#about to read 5, iclass 24, count 0 2006.196.08:12:10.96#ibcon#read 5, iclass 24, count 0 2006.196.08:12:10.96#ibcon#about to read 6, iclass 24, count 0 2006.196.08:12:10.96#ibcon#read 6, iclass 24, count 0 2006.196.08:12:10.96#ibcon#end of sib2, iclass 24, count 0 2006.196.08:12:10.96#ibcon#*mode == 0, iclass 24, count 0 2006.196.08:12:10.96#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.196.08:12:10.96#ibcon#[28=FRQ=02,640.99\r\n] 2006.196.08:12:10.96#ibcon#*before write, iclass 24, count 0 2006.196.08:12:10.96#ibcon#enter sib2, iclass 24, count 0 2006.196.08:12:10.96#ibcon#flushed, iclass 24, count 0 2006.196.08:12:10.96#ibcon#about to write, iclass 24, count 0 2006.196.08:12:10.96#ibcon#wrote, iclass 24, count 0 2006.196.08:12:10.96#ibcon#about to read 3, iclass 24, count 0 2006.196.08:12:11.00#ibcon#read 3, iclass 24, count 0 2006.196.08:12:11.00#ibcon#about to read 4, iclass 24, count 0 2006.196.08:12:11.00#ibcon#read 4, iclass 24, count 0 2006.196.08:12:11.00#ibcon#about to read 5, iclass 24, count 0 2006.196.08:12:11.00#ibcon#read 5, iclass 24, count 0 2006.196.08:12:11.00#ibcon#about to read 6, iclass 24, count 0 2006.196.08:12:11.00#ibcon#read 6, iclass 24, count 0 2006.196.08:12:11.00#ibcon#end of sib2, iclass 24, count 0 2006.196.08:12:11.00#ibcon#*after write, iclass 24, count 0 2006.196.08:12:11.00#ibcon#*before return 0, iclass 24, count 0 2006.196.08:12:11.00#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.196.08:12:11.00#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.196.08:12:11.00#ibcon#about to clear, iclass 24 cls_cnt 0 2006.196.08:12:11.00#ibcon#cleared, iclass 24 cls_cnt 0 2006.196.08:12:11.00$vc4f8/vb=2,4 2006.196.08:12:11.00#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.196.08:12:11.00#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.196.08:12:11.00#ibcon#ireg 11 cls_cnt 2 2006.196.08:12:11.00#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.196.08:12:11.06#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.196.08:12:11.06#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.196.08:12:11.06#ibcon#enter wrdev, iclass 26, count 2 2006.196.08:12:11.06#ibcon#first serial, iclass 26, count 2 2006.196.08:12:11.06#ibcon#enter sib2, iclass 26, count 2 2006.196.08:12:11.06#ibcon#flushed, iclass 26, count 2 2006.196.08:12:11.06#ibcon#about to write, iclass 26, count 2 2006.196.08:12:11.06#ibcon#wrote, iclass 26, count 2 2006.196.08:12:11.06#ibcon#about to read 3, iclass 26, count 2 2006.196.08:12:11.08#ibcon#read 3, iclass 26, count 2 2006.196.08:12:11.08#ibcon#about to read 4, iclass 26, count 2 2006.196.08:12:11.08#ibcon#read 4, iclass 26, count 2 2006.196.08:12:11.08#ibcon#about to read 5, iclass 26, count 2 2006.196.08:12:11.08#ibcon#read 5, iclass 26, count 2 2006.196.08:12:11.08#ibcon#about to read 6, iclass 26, count 2 2006.196.08:12:11.08#ibcon#read 6, iclass 26, count 2 2006.196.08:12:11.08#ibcon#end of sib2, iclass 26, count 2 2006.196.08:12:11.08#ibcon#*mode == 0, iclass 26, count 2 2006.196.08:12:11.08#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.196.08:12:11.08#ibcon#[27=AT02-04\r\n] 2006.196.08:12:11.08#ibcon#*before write, iclass 26, count 2 2006.196.08:12:11.08#ibcon#enter sib2, iclass 26, count 2 2006.196.08:12:11.08#ibcon#flushed, iclass 26, count 2 2006.196.08:12:11.08#ibcon#about to write, iclass 26, count 2 2006.196.08:12:11.08#ibcon#wrote, iclass 26, count 2 2006.196.08:12:11.08#ibcon#about to read 3, iclass 26, count 2 2006.196.08:12:11.11#ibcon#read 3, iclass 26, count 2 2006.196.08:12:11.11#ibcon#about to read 4, iclass 26, count 2 2006.196.08:12:11.11#ibcon#read 4, iclass 26, count 2 2006.196.08:12:11.11#ibcon#about to read 5, iclass 26, count 2 2006.196.08:12:11.11#ibcon#read 5, iclass 26, count 2 2006.196.08:12:11.11#ibcon#about to read 6, iclass 26, count 2 2006.196.08:12:11.11#ibcon#read 6, iclass 26, count 2 2006.196.08:12:11.11#ibcon#end of sib2, iclass 26, count 2 2006.196.08:12:11.11#ibcon#*after write, iclass 26, count 2 2006.196.08:12:11.11#ibcon#*before return 0, iclass 26, count 2 2006.196.08:12:11.11#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.196.08:12:11.11#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.196.08:12:11.11#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.196.08:12:11.11#ibcon#ireg 7 cls_cnt 0 2006.196.08:12:11.11#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.196.08:12:11.23#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.196.08:12:11.23#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.196.08:12:11.23#ibcon#enter wrdev, iclass 26, count 0 2006.196.08:12:11.23#ibcon#first serial, iclass 26, count 0 2006.196.08:12:11.23#ibcon#enter sib2, iclass 26, count 0 2006.196.08:12:11.23#ibcon#flushed, iclass 26, count 0 2006.196.08:12:11.23#ibcon#about to write, iclass 26, count 0 2006.196.08:12:11.23#ibcon#wrote, iclass 26, count 0 2006.196.08:12:11.23#ibcon#about to read 3, iclass 26, count 0 2006.196.08:12:11.25#ibcon#read 3, iclass 26, count 0 2006.196.08:12:11.25#ibcon#about to read 4, iclass 26, count 0 2006.196.08:12:11.25#ibcon#read 4, iclass 26, count 0 2006.196.08:12:11.25#ibcon#about to read 5, iclass 26, count 0 2006.196.08:12:11.25#ibcon#read 5, iclass 26, count 0 2006.196.08:12:11.25#ibcon#about to read 6, iclass 26, count 0 2006.196.08:12:11.25#ibcon#read 6, iclass 26, count 0 2006.196.08:12:11.25#ibcon#end of sib2, iclass 26, count 0 2006.196.08:12:11.25#ibcon#*mode == 0, iclass 26, count 0 2006.196.08:12:11.25#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.196.08:12:11.25#ibcon#[27=USB\r\n] 2006.196.08:12:11.25#ibcon#*before write, iclass 26, count 0 2006.196.08:12:11.25#ibcon#enter sib2, iclass 26, count 0 2006.196.08:12:11.25#ibcon#flushed, iclass 26, count 0 2006.196.08:12:11.25#ibcon#about to write, iclass 26, count 0 2006.196.08:12:11.25#ibcon#wrote, iclass 26, count 0 2006.196.08:12:11.25#ibcon#about to read 3, iclass 26, count 0 2006.196.08:12:11.28#ibcon#read 3, iclass 26, count 0 2006.196.08:12:11.28#ibcon#about to read 4, iclass 26, count 0 2006.196.08:12:11.28#ibcon#read 4, iclass 26, count 0 2006.196.08:12:11.28#ibcon#about to read 5, iclass 26, count 0 2006.196.08:12:11.28#ibcon#read 5, iclass 26, count 0 2006.196.08:12:11.28#ibcon#about to read 6, iclass 26, count 0 2006.196.08:12:11.28#ibcon#read 6, iclass 26, count 0 2006.196.08:12:11.28#ibcon#end of sib2, iclass 26, count 0 2006.196.08:12:11.28#ibcon#*after write, iclass 26, count 0 2006.196.08:12:11.28#ibcon#*before return 0, iclass 26, count 0 2006.196.08:12:11.28#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.196.08:12:11.28#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.196.08:12:11.28#ibcon#about to clear, iclass 26 cls_cnt 0 2006.196.08:12:11.28#ibcon#cleared, iclass 26 cls_cnt 0 2006.196.08:12:11.28$vc4f8/vblo=3,656.99 2006.196.08:12:11.28#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.196.08:12:11.28#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.196.08:12:11.28#ibcon#ireg 17 cls_cnt 0 2006.196.08:12:11.28#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.196.08:12:11.28#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.196.08:12:11.28#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.196.08:12:11.28#ibcon#enter wrdev, iclass 28, count 0 2006.196.08:12:11.28#ibcon#first serial, iclass 28, count 0 2006.196.08:12:11.28#ibcon#enter sib2, iclass 28, count 0 2006.196.08:12:11.28#ibcon#flushed, iclass 28, count 0 2006.196.08:12:11.28#ibcon#about to write, iclass 28, count 0 2006.196.08:12:11.28#ibcon#wrote, iclass 28, count 0 2006.196.08:12:11.28#ibcon#about to read 3, iclass 28, count 0 2006.196.08:12:11.30#ibcon#read 3, iclass 28, count 0 2006.196.08:12:11.30#ibcon#about to read 4, iclass 28, count 0 2006.196.08:12:11.30#ibcon#read 4, iclass 28, count 0 2006.196.08:12:11.30#ibcon#about to read 5, iclass 28, count 0 2006.196.08:12:11.30#ibcon#read 5, iclass 28, count 0 2006.196.08:12:11.30#ibcon#about to read 6, iclass 28, count 0 2006.196.08:12:11.30#ibcon#read 6, iclass 28, count 0 2006.196.08:12:11.30#ibcon#end of sib2, iclass 28, count 0 2006.196.08:12:11.30#ibcon#*mode == 0, iclass 28, count 0 2006.196.08:12:11.30#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.196.08:12:11.30#ibcon#[28=FRQ=03,656.99\r\n] 2006.196.08:12:11.30#ibcon#*before write, iclass 28, count 0 2006.196.08:12:11.30#ibcon#enter sib2, iclass 28, count 0 2006.196.08:12:11.30#ibcon#flushed, iclass 28, count 0 2006.196.08:12:11.30#ibcon#about to write, iclass 28, count 0 2006.196.08:12:11.30#ibcon#wrote, iclass 28, count 0 2006.196.08:12:11.30#ibcon#about to read 3, iclass 28, count 0 2006.196.08:12:11.35#ibcon#read 3, iclass 28, count 0 2006.196.08:12:11.35#ibcon#about to read 4, iclass 28, count 0 2006.196.08:12:11.35#ibcon#read 4, iclass 28, count 0 2006.196.08:12:11.35#ibcon#about to read 5, iclass 28, count 0 2006.196.08:12:11.35#ibcon#read 5, iclass 28, count 0 2006.196.08:12:11.35#ibcon#about to read 6, iclass 28, count 0 2006.196.08:12:11.35#ibcon#read 6, iclass 28, count 0 2006.196.08:12:11.35#ibcon#end of sib2, iclass 28, count 0 2006.196.08:12:11.35#ibcon#*after write, iclass 28, count 0 2006.196.08:12:11.35#ibcon#*before return 0, iclass 28, count 0 2006.196.08:12:11.35#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.196.08:12:11.35#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.196.08:12:11.35#ibcon#about to clear, iclass 28 cls_cnt 0 2006.196.08:12:11.35#ibcon#cleared, iclass 28 cls_cnt 0 2006.196.08:12:11.35$vc4f8/vb=3,4 2006.196.08:12:11.35#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.196.08:12:11.35#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.196.08:12:11.35#ibcon#ireg 11 cls_cnt 2 2006.196.08:12:11.35#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.196.08:12:11.40#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.196.08:12:11.40#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.196.08:12:11.40#ibcon#enter wrdev, iclass 30, count 2 2006.196.08:12:11.40#ibcon#first serial, iclass 30, count 2 2006.196.08:12:11.40#ibcon#enter sib2, iclass 30, count 2 2006.196.08:12:11.40#ibcon#flushed, iclass 30, count 2 2006.196.08:12:11.40#ibcon#about to write, iclass 30, count 2 2006.196.08:12:11.40#ibcon#wrote, iclass 30, count 2 2006.196.08:12:11.40#ibcon#about to read 3, iclass 30, count 2 2006.196.08:12:11.42#ibcon#read 3, iclass 30, count 2 2006.196.08:12:11.42#ibcon#about to read 4, iclass 30, count 2 2006.196.08:12:11.42#ibcon#read 4, iclass 30, count 2 2006.196.08:12:11.42#ibcon#about to read 5, iclass 30, count 2 2006.196.08:12:11.42#ibcon#read 5, iclass 30, count 2 2006.196.08:12:11.42#ibcon#about to read 6, iclass 30, count 2 2006.196.08:12:11.42#ibcon#read 6, iclass 30, count 2 2006.196.08:12:11.42#ibcon#end of sib2, iclass 30, count 2 2006.196.08:12:11.42#ibcon#*mode == 0, iclass 30, count 2 2006.196.08:12:11.42#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.196.08:12:11.42#ibcon#[27=AT03-04\r\n] 2006.196.08:12:11.42#ibcon#*before write, iclass 30, count 2 2006.196.08:12:11.42#ibcon#enter sib2, iclass 30, count 2 2006.196.08:12:11.42#ibcon#flushed, iclass 30, count 2 2006.196.08:12:11.42#ibcon#about to write, iclass 30, count 2 2006.196.08:12:11.42#ibcon#wrote, iclass 30, count 2 2006.196.08:12:11.42#ibcon#about to read 3, iclass 30, count 2 2006.196.08:12:11.45#ibcon#read 3, iclass 30, count 2 2006.196.08:12:11.45#ibcon#about to read 4, iclass 30, count 2 2006.196.08:12:11.45#ibcon#read 4, iclass 30, count 2 2006.196.08:12:11.45#ibcon#about to read 5, iclass 30, count 2 2006.196.08:12:11.45#ibcon#read 5, iclass 30, count 2 2006.196.08:12:11.45#ibcon#about to read 6, iclass 30, count 2 2006.196.08:12:11.45#ibcon#read 6, iclass 30, count 2 2006.196.08:12:11.45#ibcon#end of sib2, iclass 30, count 2 2006.196.08:12:11.45#ibcon#*after write, iclass 30, count 2 2006.196.08:12:11.45#ibcon#*before return 0, iclass 30, count 2 2006.196.08:12:11.45#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.196.08:12:11.45#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.196.08:12:11.45#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.196.08:12:11.45#ibcon#ireg 7 cls_cnt 0 2006.196.08:12:11.45#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.196.08:12:11.57#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.196.08:12:11.57#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.196.08:12:11.57#ibcon#enter wrdev, iclass 30, count 0 2006.196.08:12:11.57#ibcon#first serial, iclass 30, count 0 2006.196.08:12:11.57#ibcon#enter sib2, iclass 30, count 0 2006.196.08:12:11.57#ibcon#flushed, iclass 30, count 0 2006.196.08:12:11.57#ibcon#about to write, iclass 30, count 0 2006.196.08:12:11.57#ibcon#wrote, iclass 30, count 0 2006.196.08:12:11.57#ibcon#about to read 3, iclass 30, count 0 2006.196.08:12:11.59#ibcon#read 3, iclass 30, count 0 2006.196.08:12:11.59#ibcon#about to read 4, iclass 30, count 0 2006.196.08:12:11.59#ibcon#read 4, iclass 30, count 0 2006.196.08:12:11.59#ibcon#about to read 5, iclass 30, count 0 2006.196.08:12:11.59#ibcon#read 5, iclass 30, count 0 2006.196.08:12:11.59#ibcon#about to read 6, iclass 30, count 0 2006.196.08:12:11.59#ibcon#read 6, iclass 30, count 0 2006.196.08:12:11.59#ibcon#end of sib2, iclass 30, count 0 2006.196.08:12:11.59#ibcon#*mode == 0, iclass 30, count 0 2006.196.08:12:11.59#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.196.08:12:11.59#ibcon#[27=USB\r\n] 2006.196.08:12:11.59#ibcon#*before write, iclass 30, count 0 2006.196.08:12:11.59#ibcon#enter sib2, iclass 30, count 0 2006.196.08:12:11.59#ibcon#flushed, iclass 30, count 0 2006.196.08:12:11.59#ibcon#about to write, iclass 30, count 0 2006.196.08:12:11.59#ibcon#wrote, iclass 30, count 0 2006.196.08:12:11.59#ibcon#about to read 3, iclass 30, count 0 2006.196.08:12:11.62#ibcon#read 3, iclass 30, count 0 2006.196.08:12:11.62#ibcon#about to read 4, iclass 30, count 0 2006.196.08:12:11.62#ibcon#read 4, iclass 30, count 0 2006.196.08:12:11.62#ibcon#about to read 5, iclass 30, count 0 2006.196.08:12:11.62#ibcon#read 5, iclass 30, count 0 2006.196.08:12:11.62#ibcon#about to read 6, iclass 30, count 0 2006.196.08:12:11.62#ibcon#read 6, iclass 30, count 0 2006.196.08:12:11.62#ibcon#end of sib2, iclass 30, count 0 2006.196.08:12:11.62#ibcon#*after write, iclass 30, count 0 2006.196.08:12:11.62#ibcon#*before return 0, iclass 30, count 0 2006.196.08:12:11.62#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.196.08:12:11.62#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.196.08:12:11.62#ibcon#about to clear, iclass 30 cls_cnt 0 2006.196.08:12:11.62#ibcon#cleared, iclass 30 cls_cnt 0 2006.196.08:12:11.62$vc4f8/vblo=4,712.99 2006.196.08:12:11.62#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.196.08:12:11.62#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.196.08:12:11.62#ibcon#ireg 17 cls_cnt 0 2006.196.08:12:11.62#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.196.08:12:11.62#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.196.08:12:11.62#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.196.08:12:11.62#ibcon#enter wrdev, iclass 32, count 0 2006.196.08:12:11.62#ibcon#first serial, iclass 32, count 0 2006.196.08:12:11.62#ibcon#enter sib2, iclass 32, count 0 2006.196.08:12:11.62#ibcon#flushed, iclass 32, count 0 2006.196.08:12:11.62#ibcon#about to write, iclass 32, count 0 2006.196.08:12:11.62#ibcon#wrote, iclass 32, count 0 2006.196.08:12:11.62#ibcon#about to read 3, iclass 32, count 0 2006.196.08:12:11.64#ibcon#read 3, iclass 32, count 0 2006.196.08:12:11.64#ibcon#about to read 4, iclass 32, count 0 2006.196.08:12:11.64#ibcon#read 4, iclass 32, count 0 2006.196.08:12:11.64#ibcon#about to read 5, iclass 32, count 0 2006.196.08:12:11.64#ibcon#read 5, iclass 32, count 0 2006.196.08:12:11.64#ibcon#about to read 6, iclass 32, count 0 2006.196.08:12:11.64#ibcon#read 6, iclass 32, count 0 2006.196.08:12:11.64#ibcon#end of sib2, iclass 32, count 0 2006.196.08:12:11.64#ibcon#*mode == 0, iclass 32, count 0 2006.196.08:12:11.64#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.196.08:12:11.64#ibcon#[28=FRQ=04,712.99\r\n] 2006.196.08:12:11.64#ibcon#*before write, iclass 32, count 0 2006.196.08:12:11.64#ibcon#enter sib2, iclass 32, count 0 2006.196.08:12:11.64#ibcon#flushed, iclass 32, count 0 2006.196.08:12:11.64#ibcon#about to write, iclass 32, count 0 2006.196.08:12:11.64#ibcon#wrote, iclass 32, count 0 2006.196.08:12:11.64#ibcon#about to read 3, iclass 32, count 0 2006.196.08:12:11.68#ibcon#read 3, iclass 32, count 0 2006.196.08:12:11.68#ibcon#about to read 4, iclass 32, count 0 2006.196.08:12:11.68#ibcon#read 4, iclass 32, count 0 2006.196.08:12:11.68#ibcon#about to read 5, iclass 32, count 0 2006.196.08:12:11.68#ibcon#read 5, iclass 32, count 0 2006.196.08:12:11.68#ibcon#about to read 6, iclass 32, count 0 2006.196.08:12:11.68#ibcon#read 6, iclass 32, count 0 2006.196.08:12:11.68#ibcon#end of sib2, iclass 32, count 0 2006.196.08:12:11.68#ibcon#*after write, iclass 32, count 0 2006.196.08:12:11.68#ibcon#*before return 0, iclass 32, count 0 2006.196.08:12:11.68#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.196.08:12:11.68#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.196.08:12:11.68#ibcon#about to clear, iclass 32 cls_cnt 0 2006.196.08:12:11.68#ibcon#cleared, iclass 32 cls_cnt 0 2006.196.08:12:11.68$vc4f8/vb=4,4 2006.196.08:12:11.68#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.196.08:12:11.68#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.196.08:12:11.68#ibcon#ireg 11 cls_cnt 2 2006.196.08:12:11.68#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.196.08:12:11.74#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.196.08:12:11.74#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.196.08:12:11.74#ibcon#enter wrdev, iclass 34, count 2 2006.196.08:12:11.74#ibcon#first serial, iclass 34, count 2 2006.196.08:12:11.74#ibcon#enter sib2, iclass 34, count 2 2006.196.08:12:11.74#ibcon#flushed, iclass 34, count 2 2006.196.08:12:11.74#ibcon#about to write, iclass 34, count 2 2006.196.08:12:11.74#ibcon#wrote, iclass 34, count 2 2006.196.08:12:11.74#ibcon#about to read 3, iclass 34, count 2 2006.196.08:12:11.76#ibcon#read 3, iclass 34, count 2 2006.196.08:12:11.76#ibcon#about to read 4, iclass 34, count 2 2006.196.08:12:11.76#ibcon#read 4, iclass 34, count 2 2006.196.08:12:11.76#ibcon#about to read 5, iclass 34, count 2 2006.196.08:12:11.76#ibcon#read 5, iclass 34, count 2 2006.196.08:12:11.76#ibcon#about to read 6, iclass 34, count 2 2006.196.08:12:11.76#ibcon#read 6, iclass 34, count 2 2006.196.08:12:11.76#ibcon#end of sib2, iclass 34, count 2 2006.196.08:12:11.76#ibcon#*mode == 0, iclass 34, count 2 2006.196.08:12:11.76#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.196.08:12:11.76#ibcon#[27=AT04-04\r\n] 2006.196.08:12:11.76#ibcon#*before write, iclass 34, count 2 2006.196.08:12:11.76#ibcon#enter sib2, iclass 34, count 2 2006.196.08:12:11.76#ibcon#flushed, iclass 34, count 2 2006.196.08:12:11.76#ibcon#about to write, iclass 34, count 2 2006.196.08:12:11.76#ibcon#wrote, iclass 34, count 2 2006.196.08:12:11.76#ibcon#about to read 3, iclass 34, count 2 2006.196.08:12:11.79#ibcon#read 3, iclass 34, count 2 2006.196.08:12:11.79#ibcon#about to read 4, iclass 34, count 2 2006.196.08:12:11.79#ibcon#read 4, iclass 34, count 2 2006.196.08:12:11.79#ibcon#about to read 5, iclass 34, count 2 2006.196.08:12:11.79#ibcon#read 5, iclass 34, count 2 2006.196.08:12:11.79#ibcon#about to read 6, iclass 34, count 2 2006.196.08:12:11.79#ibcon#read 6, iclass 34, count 2 2006.196.08:12:11.79#ibcon#end of sib2, iclass 34, count 2 2006.196.08:12:11.79#ibcon#*after write, iclass 34, count 2 2006.196.08:12:11.79#ibcon#*before return 0, iclass 34, count 2 2006.196.08:12:11.79#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.196.08:12:11.79#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.196.08:12:11.79#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.196.08:12:11.79#ibcon#ireg 7 cls_cnt 0 2006.196.08:12:11.79#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.196.08:12:11.91#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.196.08:12:11.91#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.196.08:12:11.91#ibcon#enter wrdev, iclass 34, count 0 2006.196.08:12:11.91#ibcon#first serial, iclass 34, count 0 2006.196.08:12:11.91#ibcon#enter sib2, iclass 34, count 0 2006.196.08:12:11.91#ibcon#flushed, iclass 34, count 0 2006.196.08:12:11.91#ibcon#about to write, iclass 34, count 0 2006.196.08:12:11.91#ibcon#wrote, iclass 34, count 0 2006.196.08:12:11.91#ibcon#about to read 3, iclass 34, count 0 2006.196.08:12:11.93#ibcon#read 3, iclass 34, count 0 2006.196.08:12:11.93#ibcon#about to read 4, iclass 34, count 0 2006.196.08:12:11.93#ibcon#read 4, iclass 34, count 0 2006.196.08:12:11.93#ibcon#about to read 5, iclass 34, count 0 2006.196.08:12:11.93#ibcon#read 5, iclass 34, count 0 2006.196.08:12:11.93#ibcon#about to read 6, iclass 34, count 0 2006.196.08:12:11.93#ibcon#read 6, iclass 34, count 0 2006.196.08:12:11.93#ibcon#end of sib2, iclass 34, count 0 2006.196.08:12:11.93#ibcon#*mode == 0, iclass 34, count 0 2006.196.08:12:11.93#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.196.08:12:11.93#ibcon#[27=USB\r\n] 2006.196.08:12:11.93#ibcon#*before write, iclass 34, count 0 2006.196.08:12:11.93#ibcon#enter sib2, iclass 34, count 0 2006.196.08:12:11.93#ibcon#flushed, iclass 34, count 0 2006.196.08:12:11.93#ibcon#about to write, iclass 34, count 0 2006.196.08:12:11.93#ibcon#wrote, iclass 34, count 0 2006.196.08:12:11.93#ibcon#about to read 3, iclass 34, count 0 2006.196.08:12:11.96#ibcon#read 3, iclass 34, count 0 2006.196.08:12:11.96#ibcon#about to read 4, iclass 34, count 0 2006.196.08:12:11.96#ibcon#read 4, iclass 34, count 0 2006.196.08:12:11.96#ibcon#about to read 5, iclass 34, count 0 2006.196.08:12:11.96#ibcon#read 5, iclass 34, count 0 2006.196.08:12:11.96#ibcon#about to read 6, iclass 34, count 0 2006.196.08:12:11.96#ibcon#read 6, iclass 34, count 0 2006.196.08:12:11.96#ibcon#end of sib2, iclass 34, count 0 2006.196.08:12:11.96#ibcon#*after write, iclass 34, count 0 2006.196.08:12:11.96#ibcon#*before return 0, iclass 34, count 0 2006.196.08:12:11.96#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.196.08:12:11.96#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.196.08:12:11.96#ibcon#about to clear, iclass 34 cls_cnt 0 2006.196.08:12:11.96#ibcon#cleared, iclass 34 cls_cnt 0 2006.196.08:12:11.96$vc4f8/vblo=5,744.99 2006.196.08:12:11.96#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.196.08:12:11.96#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.196.08:12:11.96#ibcon#ireg 17 cls_cnt 0 2006.196.08:12:11.96#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.196.08:12:11.96#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.196.08:12:11.96#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.196.08:12:11.96#ibcon#enter wrdev, iclass 36, count 0 2006.196.08:12:11.96#ibcon#first serial, iclass 36, count 0 2006.196.08:12:11.96#ibcon#enter sib2, iclass 36, count 0 2006.196.08:12:11.96#ibcon#flushed, iclass 36, count 0 2006.196.08:12:11.96#ibcon#about to write, iclass 36, count 0 2006.196.08:12:11.96#ibcon#wrote, iclass 36, count 0 2006.196.08:12:11.96#ibcon#about to read 3, iclass 36, count 0 2006.196.08:12:11.98#ibcon#read 3, iclass 36, count 0 2006.196.08:12:11.98#ibcon#about to read 4, iclass 36, count 0 2006.196.08:12:11.98#ibcon#read 4, iclass 36, count 0 2006.196.08:12:11.98#ibcon#about to read 5, iclass 36, count 0 2006.196.08:12:11.98#ibcon#read 5, iclass 36, count 0 2006.196.08:12:11.98#ibcon#about to read 6, iclass 36, count 0 2006.196.08:12:11.98#ibcon#read 6, iclass 36, count 0 2006.196.08:12:11.98#ibcon#end of sib2, iclass 36, count 0 2006.196.08:12:11.98#ibcon#*mode == 0, iclass 36, count 0 2006.196.08:12:11.98#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.196.08:12:11.98#ibcon#[28=FRQ=05,744.99\r\n] 2006.196.08:12:11.98#ibcon#*before write, iclass 36, count 0 2006.196.08:12:11.98#ibcon#enter sib2, iclass 36, count 0 2006.196.08:12:11.98#ibcon#flushed, iclass 36, count 0 2006.196.08:12:11.98#ibcon#about to write, iclass 36, count 0 2006.196.08:12:11.98#ibcon#wrote, iclass 36, count 0 2006.196.08:12:11.98#ibcon#about to read 3, iclass 36, count 0 2006.196.08:12:12.03#ibcon#read 3, iclass 36, count 0 2006.196.08:12:12.03#ibcon#about to read 4, iclass 36, count 0 2006.196.08:12:12.03#ibcon#read 4, iclass 36, count 0 2006.196.08:12:12.03#ibcon#about to read 5, iclass 36, count 0 2006.196.08:12:12.03#ibcon#read 5, iclass 36, count 0 2006.196.08:12:12.03#ibcon#about to read 6, iclass 36, count 0 2006.196.08:12:12.03#ibcon#read 6, iclass 36, count 0 2006.196.08:12:12.03#ibcon#end of sib2, iclass 36, count 0 2006.196.08:12:12.03#ibcon#*after write, iclass 36, count 0 2006.196.08:12:12.03#ibcon#*before return 0, iclass 36, count 0 2006.196.08:12:12.03#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.196.08:12:12.03#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.196.08:12:12.03#ibcon#about to clear, iclass 36 cls_cnt 0 2006.196.08:12:12.03#ibcon#cleared, iclass 36 cls_cnt 0 2006.196.08:12:12.03$vc4f8/vb=5,4 2006.196.08:12:12.03#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.196.08:12:12.03#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.196.08:12:12.03#ibcon#ireg 11 cls_cnt 2 2006.196.08:12:12.03#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.196.08:12:12.08#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.196.08:12:12.08#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.196.08:12:12.08#ibcon#enter wrdev, iclass 38, count 2 2006.196.08:12:12.08#ibcon#first serial, iclass 38, count 2 2006.196.08:12:12.08#ibcon#enter sib2, iclass 38, count 2 2006.196.08:12:12.08#ibcon#flushed, iclass 38, count 2 2006.196.08:12:12.08#ibcon#about to write, iclass 38, count 2 2006.196.08:12:12.08#ibcon#wrote, iclass 38, count 2 2006.196.08:12:12.08#ibcon#about to read 3, iclass 38, count 2 2006.196.08:12:12.10#ibcon#read 3, iclass 38, count 2 2006.196.08:12:12.10#ibcon#about to read 4, iclass 38, count 2 2006.196.08:12:12.10#ibcon#read 4, iclass 38, count 2 2006.196.08:12:12.10#ibcon#about to read 5, iclass 38, count 2 2006.196.08:12:12.10#ibcon#read 5, iclass 38, count 2 2006.196.08:12:12.10#ibcon#about to read 6, iclass 38, count 2 2006.196.08:12:12.10#ibcon#read 6, iclass 38, count 2 2006.196.08:12:12.10#ibcon#end of sib2, iclass 38, count 2 2006.196.08:12:12.10#ibcon#*mode == 0, iclass 38, count 2 2006.196.08:12:12.10#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.196.08:12:12.10#ibcon#[27=AT05-04\r\n] 2006.196.08:12:12.10#ibcon#*before write, iclass 38, count 2 2006.196.08:12:12.10#ibcon#enter sib2, iclass 38, count 2 2006.196.08:12:12.10#ibcon#flushed, iclass 38, count 2 2006.196.08:12:12.10#ibcon#about to write, iclass 38, count 2 2006.196.08:12:12.10#ibcon#wrote, iclass 38, count 2 2006.196.08:12:12.10#ibcon#about to read 3, iclass 38, count 2 2006.196.08:12:12.13#ibcon#read 3, iclass 38, count 2 2006.196.08:12:12.13#ibcon#about to read 4, iclass 38, count 2 2006.196.08:12:12.13#ibcon#read 4, iclass 38, count 2 2006.196.08:12:12.13#ibcon#about to read 5, iclass 38, count 2 2006.196.08:12:12.13#ibcon#read 5, iclass 38, count 2 2006.196.08:12:12.13#ibcon#about to read 6, iclass 38, count 2 2006.196.08:12:12.13#ibcon#read 6, iclass 38, count 2 2006.196.08:12:12.13#ibcon#end of sib2, iclass 38, count 2 2006.196.08:12:12.13#ibcon#*after write, iclass 38, count 2 2006.196.08:12:12.13#ibcon#*before return 0, iclass 38, count 2 2006.196.08:12:12.13#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.196.08:12:12.13#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.196.08:12:12.13#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.196.08:12:12.13#ibcon#ireg 7 cls_cnt 0 2006.196.08:12:12.13#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.196.08:12:12.25#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.196.08:12:12.25#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.196.08:12:12.25#ibcon#enter wrdev, iclass 38, count 0 2006.196.08:12:12.25#ibcon#first serial, iclass 38, count 0 2006.196.08:12:12.25#ibcon#enter sib2, iclass 38, count 0 2006.196.08:12:12.25#ibcon#flushed, iclass 38, count 0 2006.196.08:12:12.25#ibcon#about to write, iclass 38, count 0 2006.196.08:12:12.25#ibcon#wrote, iclass 38, count 0 2006.196.08:12:12.25#ibcon#about to read 3, iclass 38, count 0 2006.196.08:12:12.27#ibcon#read 3, iclass 38, count 0 2006.196.08:12:12.27#ibcon#about to read 4, iclass 38, count 0 2006.196.08:12:12.27#ibcon#read 4, iclass 38, count 0 2006.196.08:12:12.27#ibcon#about to read 5, iclass 38, count 0 2006.196.08:12:12.27#ibcon#read 5, iclass 38, count 0 2006.196.08:12:12.27#ibcon#about to read 6, iclass 38, count 0 2006.196.08:12:12.27#ibcon#read 6, iclass 38, count 0 2006.196.08:12:12.27#ibcon#end of sib2, iclass 38, count 0 2006.196.08:12:12.27#ibcon#*mode == 0, iclass 38, count 0 2006.196.08:12:12.27#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.196.08:12:12.27#ibcon#[27=USB\r\n] 2006.196.08:12:12.27#ibcon#*before write, iclass 38, count 0 2006.196.08:12:12.27#ibcon#enter sib2, iclass 38, count 0 2006.196.08:12:12.27#ibcon#flushed, iclass 38, count 0 2006.196.08:12:12.27#ibcon#about to write, iclass 38, count 0 2006.196.08:12:12.27#ibcon#wrote, iclass 38, count 0 2006.196.08:12:12.27#ibcon#about to read 3, iclass 38, count 0 2006.196.08:12:12.30#ibcon#read 3, iclass 38, count 0 2006.196.08:12:12.30#ibcon#about to read 4, iclass 38, count 0 2006.196.08:12:12.30#ibcon#read 4, iclass 38, count 0 2006.196.08:12:12.30#ibcon#about to read 5, iclass 38, count 0 2006.196.08:12:12.30#ibcon#read 5, iclass 38, count 0 2006.196.08:12:12.30#ibcon#about to read 6, iclass 38, count 0 2006.196.08:12:12.30#ibcon#read 6, iclass 38, count 0 2006.196.08:12:12.30#ibcon#end of sib2, iclass 38, count 0 2006.196.08:12:12.30#ibcon#*after write, iclass 38, count 0 2006.196.08:12:12.30#ibcon#*before return 0, iclass 38, count 0 2006.196.08:12:12.30#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.196.08:12:12.30#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.196.08:12:12.30#ibcon#about to clear, iclass 38 cls_cnt 0 2006.196.08:12:12.30#ibcon#cleared, iclass 38 cls_cnt 0 2006.196.08:12:12.30$vc4f8/vblo=6,752.99 2006.196.08:12:12.30#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.196.08:12:12.30#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.196.08:12:12.30#ibcon#ireg 17 cls_cnt 0 2006.196.08:12:12.30#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.196.08:12:12.30#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.196.08:12:12.30#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.196.08:12:12.30#ibcon#enter wrdev, iclass 40, count 0 2006.196.08:12:12.30#ibcon#first serial, iclass 40, count 0 2006.196.08:12:12.30#ibcon#enter sib2, iclass 40, count 0 2006.196.08:12:12.30#ibcon#flushed, iclass 40, count 0 2006.196.08:12:12.30#ibcon#about to write, iclass 40, count 0 2006.196.08:12:12.30#ibcon#wrote, iclass 40, count 0 2006.196.08:12:12.30#ibcon#about to read 3, iclass 40, count 0 2006.196.08:12:12.32#ibcon#read 3, iclass 40, count 0 2006.196.08:12:12.32#ibcon#about to read 4, iclass 40, count 0 2006.196.08:12:12.32#ibcon#read 4, iclass 40, count 0 2006.196.08:12:12.32#ibcon#about to read 5, iclass 40, count 0 2006.196.08:12:12.32#ibcon#read 5, iclass 40, count 0 2006.196.08:12:12.32#ibcon#about to read 6, iclass 40, count 0 2006.196.08:12:12.32#ibcon#read 6, iclass 40, count 0 2006.196.08:12:12.32#ibcon#end of sib2, iclass 40, count 0 2006.196.08:12:12.32#ibcon#*mode == 0, iclass 40, count 0 2006.196.08:12:12.32#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.196.08:12:12.32#ibcon#[28=FRQ=06,752.99\r\n] 2006.196.08:12:12.32#ibcon#*before write, iclass 40, count 0 2006.196.08:12:12.32#ibcon#enter sib2, iclass 40, count 0 2006.196.08:12:12.32#ibcon#flushed, iclass 40, count 0 2006.196.08:12:12.32#ibcon#about to write, iclass 40, count 0 2006.196.08:12:12.32#ibcon#wrote, iclass 40, count 0 2006.196.08:12:12.32#ibcon#about to read 3, iclass 40, count 0 2006.196.08:12:12.36#ibcon#read 3, iclass 40, count 0 2006.196.08:12:12.36#ibcon#about to read 4, iclass 40, count 0 2006.196.08:12:12.36#ibcon#read 4, iclass 40, count 0 2006.196.08:12:12.36#ibcon#about to read 5, iclass 40, count 0 2006.196.08:12:12.36#ibcon#read 5, iclass 40, count 0 2006.196.08:12:12.36#ibcon#about to read 6, iclass 40, count 0 2006.196.08:12:12.36#ibcon#read 6, iclass 40, count 0 2006.196.08:12:12.36#ibcon#end of sib2, iclass 40, count 0 2006.196.08:12:12.36#ibcon#*after write, iclass 40, count 0 2006.196.08:12:12.36#ibcon#*before return 0, iclass 40, count 0 2006.196.08:12:12.36#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.196.08:12:12.36#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.196.08:12:12.36#ibcon#about to clear, iclass 40 cls_cnt 0 2006.196.08:12:12.36#ibcon#cleared, iclass 40 cls_cnt 0 2006.196.08:12:12.36$vc4f8/vb=6,4 2006.196.08:12:12.36#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.196.08:12:12.36#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.196.08:12:12.36#ibcon#ireg 11 cls_cnt 2 2006.196.08:12:12.36#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.196.08:12:12.42#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.196.08:12:12.42#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.196.08:12:12.42#ibcon#enter wrdev, iclass 4, count 2 2006.196.08:12:12.42#ibcon#first serial, iclass 4, count 2 2006.196.08:12:12.42#ibcon#enter sib2, iclass 4, count 2 2006.196.08:12:12.42#ibcon#flushed, iclass 4, count 2 2006.196.08:12:12.42#ibcon#about to write, iclass 4, count 2 2006.196.08:12:12.42#ibcon#wrote, iclass 4, count 2 2006.196.08:12:12.42#ibcon#about to read 3, iclass 4, count 2 2006.196.08:12:12.44#ibcon#read 3, iclass 4, count 2 2006.196.08:12:12.44#ibcon#about to read 4, iclass 4, count 2 2006.196.08:12:12.44#ibcon#read 4, iclass 4, count 2 2006.196.08:12:12.44#ibcon#about to read 5, iclass 4, count 2 2006.196.08:12:12.44#ibcon#read 5, iclass 4, count 2 2006.196.08:12:12.44#ibcon#about to read 6, iclass 4, count 2 2006.196.08:12:12.44#ibcon#read 6, iclass 4, count 2 2006.196.08:12:12.44#ibcon#end of sib2, iclass 4, count 2 2006.196.08:12:12.44#ibcon#*mode == 0, iclass 4, count 2 2006.196.08:12:12.44#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.196.08:12:12.44#ibcon#[27=AT06-04\r\n] 2006.196.08:12:12.44#ibcon#*before write, iclass 4, count 2 2006.196.08:12:12.44#ibcon#enter sib2, iclass 4, count 2 2006.196.08:12:12.44#ibcon#flushed, iclass 4, count 2 2006.196.08:12:12.44#ibcon#about to write, iclass 4, count 2 2006.196.08:12:12.44#ibcon#wrote, iclass 4, count 2 2006.196.08:12:12.44#ibcon#about to read 3, iclass 4, count 2 2006.196.08:12:12.47#ibcon#read 3, iclass 4, count 2 2006.196.08:12:12.47#ibcon#about to read 4, iclass 4, count 2 2006.196.08:12:12.47#ibcon#read 4, iclass 4, count 2 2006.196.08:12:12.47#ibcon#about to read 5, iclass 4, count 2 2006.196.08:12:12.47#ibcon#read 5, iclass 4, count 2 2006.196.08:12:12.47#ibcon#about to read 6, iclass 4, count 2 2006.196.08:12:12.47#ibcon#read 6, iclass 4, count 2 2006.196.08:12:12.47#ibcon#end of sib2, iclass 4, count 2 2006.196.08:12:12.47#ibcon#*after write, iclass 4, count 2 2006.196.08:12:12.47#ibcon#*before return 0, iclass 4, count 2 2006.196.08:12:12.47#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.196.08:12:12.47#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.196.08:12:12.47#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.196.08:12:12.47#ibcon#ireg 7 cls_cnt 0 2006.196.08:12:12.47#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.196.08:12:12.59#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.196.08:12:12.59#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.196.08:12:12.59#ibcon#enter wrdev, iclass 4, count 0 2006.196.08:12:12.59#ibcon#first serial, iclass 4, count 0 2006.196.08:12:12.59#ibcon#enter sib2, iclass 4, count 0 2006.196.08:12:12.59#ibcon#flushed, iclass 4, count 0 2006.196.08:12:12.59#ibcon#about to write, iclass 4, count 0 2006.196.08:12:12.59#ibcon#wrote, iclass 4, count 0 2006.196.08:12:12.59#ibcon#about to read 3, iclass 4, count 0 2006.196.08:12:12.61#ibcon#read 3, iclass 4, count 0 2006.196.08:12:12.61#ibcon#about to read 4, iclass 4, count 0 2006.196.08:12:12.61#ibcon#read 4, iclass 4, count 0 2006.196.08:12:12.61#ibcon#about to read 5, iclass 4, count 0 2006.196.08:12:12.61#ibcon#read 5, iclass 4, count 0 2006.196.08:12:12.61#ibcon#about to read 6, iclass 4, count 0 2006.196.08:12:12.61#ibcon#read 6, iclass 4, count 0 2006.196.08:12:12.61#ibcon#end of sib2, iclass 4, count 0 2006.196.08:12:12.61#ibcon#*mode == 0, iclass 4, count 0 2006.196.08:12:12.61#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.196.08:12:12.61#ibcon#[27=USB\r\n] 2006.196.08:12:12.61#ibcon#*before write, iclass 4, count 0 2006.196.08:12:12.61#ibcon#enter sib2, iclass 4, count 0 2006.196.08:12:12.61#ibcon#flushed, iclass 4, count 0 2006.196.08:12:12.61#ibcon#about to write, iclass 4, count 0 2006.196.08:12:12.61#ibcon#wrote, iclass 4, count 0 2006.196.08:12:12.61#ibcon#about to read 3, iclass 4, count 0 2006.196.08:12:12.64#ibcon#read 3, iclass 4, count 0 2006.196.08:12:12.64#ibcon#about to read 4, iclass 4, count 0 2006.196.08:12:12.64#ibcon#read 4, iclass 4, count 0 2006.196.08:12:12.64#ibcon#about to read 5, iclass 4, count 0 2006.196.08:12:12.64#ibcon#read 5, iclass 4, count 0 2006.196.08:12:12.64#ibcon#about to read 6, iclass 4, count 0 2006.196.08:12:12.64#ibcon#read 6, iclass 4, count 0 2006.196.08:12:12.64#ibcon#end of sib2, iclass 4, count 0 2006.196.08:12:12.64#ibcon#*after write, iclass 4, count 0 2006.196.08:12:12.64#ibcon#*before return 0, iclass 4, count 0 2006.196.08:12:12.64#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.196.08:12:12.64#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.196.08:12:12.64#ibcon#about to clear, iclass 4 cls_cnt 0 2006.196.08:12:12.64#ibcon#cleared, iclass 4 cls_cnt 0 2006.196.08:12:12.64$vc4f8/vabw=wide 2006.196.08:12:12.64#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.196.08:12:12.64#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.196.08:12:12.64#ibcon#ireg 8 cls_cnt 0 2006.196.08:12:12.64#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.196.08:12:12.64#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.196.08:12:12.64#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.196.08:12:12.64#ibcon#enter wrdev, iclass 6, count 0 2006.196.08:12:12.64#ibcon#first serial, iclass 6, count 0 2006.196.08:12:12.64#ibcon#enter sib2, iclass 6, count 0 2006.196.08:12:12.64#ibcon#flushed, iclass 6, count 0 2006.196.08:12:12.64#ibcon#about to write, iclass 6, count 0 2006.196.08:12:12.64#ibcon#wrote, iclass 6, count 0 2006.196.08:12:12.64#ibcon#about to read 3, iclass 6, count 0 2006.196.08:12:12.66#ibcon#read 3, iclass 6, count 0 2006.196.08:12:12.66#ibcon#about to read 4, iclass 6, count 0 2006.196.08:12:12.66#ibcon#read 4, iclass 6, count 0 2006.196.08:12:12.66#ibcon#about to read 5, iclass 6, count 0 2006.196.08:12:12.66#ibcon#read 5, iclass 6, count 0 2006.196.08:12:12.66#ibcon#about to read 6, iclass 6, count 0 2006.196.08:12:12.66#ibcon#read 6, iclass 6, count 0 2006.196.08:12:12.66#ibcon#end of sib2, iclass 6, count 0 2006.196.08:12:12.66#ibcon#*mode == 0, iclass 6, count 0 2006.196.08:12:12.66#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.196.08:12:12.66#ibcon#[25=BW32\r\n] 2006.196.08:12:12.66#ibcon#*before write, iclass 6, count 0 2006.196.08:12:12.66#ibcon#enter sib2, iclass 6, count 0 2006.196.08:12:12.66#ibcon#flushed, iclass 6, count 0 2006.196.08:12:12.66#ibcon#about to write, iclass 6, count 0 2006.196.08:12:12.66#ibcon#wrote, iclass 6, count 0 2006.196.08:12:12.66#ibcon#about to read 3, iclass 6, count 0 2006.196.08:12:12.70#ibcon#read 3, iclass 6, count 0 2006.196.08:12:12.70#ibcon#about to read 4, iclass 6, count 0 2006.196.08:12:12.70#ibcon#read 4, iclass 6, count 0 2006.196.08:12:12.70#ibcon#about to read 5, iclass 6, count 0 2006.196.08:12:12.70#ibcon#read 5, iclass 6, count 0 2006.196.08:12:12.70#ibcon#about to read 6, iclass 6, count 0 2006.196.08:12:12.70#ibcon#read 6, iclass 6, count 0 2006.196.08:12:12.70#ibcon#end of sib2, iclass 6, count 0 2006.196.08:12:12.70#ibcon#*after write, iclass 6, count 0 2006.196.08:12:12.70#ibcon#*before return 0, iclass 6, count 0 2006.196.08:12:12.70#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.196.08:12:12.70#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.196.08:12:12.70#ibcon#about to clear, iclass 6 cls_cnt 0 2006.196.08:12:12.70#ibcon#cleared, iclass 6 cls_cnt 0 2006.196.08:12:12.70$vc4f8/vbbw=wide 2006.196.08:12:12.70#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.196.08:12:12.70#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.196.08:12:12.70#ibcon#ireg 8 cls_cnt 0 2006.196.08:12:12.70#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.196.08:12:12.76#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.196.08:12:12.76#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.196.08:12:12.76#ibcon#enter wrdev, iclass 10, count 0 2006.196.08:12:12.76#ibcon#first serial, iclass 10, count 0 2006.196.08:12:12.76#ibcon#enter sib2, iclass 10, count 0 2006.196.08:12:12.76#ibcon#flushed, iclass 10, count 0 2006.196.08:12:12.76#ibcon#about to write, iclass 10, count 0 2006.196.08:12:12.76#ibcon#wrote, iclass 10, count 0 2006.196.08:12:12.76#ibcon#about to read 3, iclass 10, count 0 2006.196.08:12:12.78#ibcon#read 3, iclass 10, count 0 2006.196.08:12:12.78#ibcon#about to read 4, iclass 10, count 0 2006.196.08:12:12.78#ibcon#read 4, iclass 10, count 0 2006.196.08:12:12.78#ibcon#about to read 5, iclass 10, count 0 2006.196.08:12:12.78#ibcon#read 5, iclass 10, count 0 2006.196.08:12:12.78#ibcon#about to read 6, iclass 10, count 0 2006.196.08:12:12.78#ibcon#read 6, iclass 10, count 0 2006.196.08:12:12.78#ibcon#end of sib2, iclass 10, count 0 2006.196.08:12:12.78#ibcon#*mode == 0, iclass 10, count 0 2006.196.08:12:12.78#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.196.08:12:12.78#ibcon#[27=BW32\r\n] 2006.196.08:12:12.78#ibcon#*before write, iclass 10, count 0 2006.196.08:12:12.78#ibcon#enter sib2, iclass 10, count 0 2006.196.08:12:12.78#ibcon#flushed, iclass 10, count 0 2006.196.08:12:12.78#ibcon#about to write, iclass 10, count 0 2006.196.08:12:12.78#ibcon#wrote, iclass 10, count 0 2006.196.08:12:12.78#ibcon#about to read 3, iclass 10, count 0 2006.196.08:12:12.81#ibcon#read 3, iclass 10, count 0 2006.196.08:12:12.81#ibcon#about to read 4, iclass 10, count 0 2006.196.08:12:12.81#ibcon#read 4, iclass 10, count 0 2006.196.08:12:12.81#ibcon#about to read 5, iclass 10, count 0 2006.196.08:12:12.81#ibcon#read 5, iclass 10, count 0 2006.196.08:12:12.81#ibcon#about to read 6, iclass 10, count 0 2006.196.08:12:12.81#ibcon#read 6, iclass 10, count 0 2006.196.08:12:12.81#ibcon#end of sib2, iclass 10, count 0 2006.196.08:12:12.81#ibcon#*after write, iclass 10, count 0 2006.196.08:12:12.81#ibcon#*before return 0, iclass 10, count 0 2006.196.08:12:12.81#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.196.08:12:12.81#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.196.08:12:12.81#ibcon#about to clear, iclass 10 cls_cnt 0 2006.196.08:12:12.81#ibcon#cleared, iclass 10 cls_cnt 0 2006.196.08:12:12.81$4f8m12a/ifd4f 2006.196.08:12:12.81$ifd4f/lo= 2006.196.08:12:12.81$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.196.08:12:12.81$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.196.08:12:12.81$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.196.08:12:12.81$ifd4f/patch= 2006.196.08:12:12.81$ifd4f/patch=lo1,a1,a2,a3,a4 2006.196.08:12:12.81$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.196.08:12:12.81$ifd4f/patch=lo3,a5,a6,a7,a8 2006.196.08:12:12.81$4f8m12a/"form=m,16.000,1:2 2006.196.08:12:12.81$4f8m12a/"tpicd 2006.196.08:12:12.81$4f8m12a/echo=off 2006.196.08:12:12.81$4f8m12a/xlog=off 2006.196.08:12:12.81:!2006.196.08:13:00 2006.196.08:12:41.14#trakl#Source acquired 2006.196.08:12:42.14#flagr#flagr/antenna,acquired 2006.196.08:13:00.00:preob 2006.196.08:13:01.14/onsource/TRACKING 2006.196.08:13:01.14:!2006.196.08:13:10 2006.196.08:13:10.00:data_valid=on 2006.196.08:13:10.00:midob 2006.196.08:13:10.14/onsource/TRACKING 2006.196.08:13:10.14/wx/29.17,1003.9,92 2006.196.08:13:10.27/cable/+6.3379E-03 2006.196.08:13:11.36/va/01,08,usb,yes,29,30 2006.196.08:13:11.36/va/02,07,usb,yes,29,30 2006.196.08:13:11.36/va/03,06,usb,yes,30,31 2006.196.08:13:11.36/va/04,07,usb,yes,30,32 2006.196.08:13:11.36/va/05,07,usb,yes,32,33 2006.196.08:13:11.36/va/06,06,usb,yes,31,31 2006.196.08:13:11.36/va/07,06,usb,yes,31,31 2006.196.08:13:11.36/va/08,07,usb,yes,30,29 2006.196.08:13:11.59/valo/01,532.99,yes,locked 2006.196.08:13:11.59/valo/02,572.99,yes,locked 2006.196.08:13:11.59/valo/03,672.99,yes,locked 2006.196.08:13:11.59/valo/04,832.99,yes,locked 2006.196.08:13:11.59/valo/05,652.99,yes,locked 2006.196.08:13:11.59/valo/06,772.99,yes,locked 2006.196.08:13:11.59/valo/07,832.99,yes,locked 2006.196.08:13:11.59/valo/08,852.99,yes,locked 2006.196.08:13:12.68/vb/01,04,usb,yes,29,27 2006.196.08:13:12.68/vb/02,04,usb,yes,30,32 2006.196.08:13:12.68/vb/03,04,usb,yes,27,30 2006.196.08:13:12.68/vb/04,04,usb,yes,28,28 2006.196.08:13:12.68/vb/05,04,usb,yes,26,30 2006.196.08:13:12.68/vb/06,04,usb,yes,27,30 2006.196.08:13:12.68/vb/07,04,usb,yes,29,29 2006.196.08:13:12.68/vb/08,04,usb,yes,27,30 2006.196.08:13:12.91/vblo/01,632.99,yes,locked 2006.196.08:13:12.91/vblo/02,640.99,yes,locked 2006.196.08:13:12.91/vblo/03,656.99,yes,locked 2006.196.08:13:12.91/vblo/04,712.99,yes,locked 2006.196.08:13:12.91/vblo/05,744.99,yes,locked 2006.196.08:13:12.91/vblo/06,752.99,yes,locked 2006.196.08:13:12.91/vblo/07,734.99,yes,locked 2006.196.08:13:12.91/vblo/08,744.99,yes,locked 2006.196.08:13:13.06/vabw/8 2006.196.08:13:13.21/vbbw/8 2006.196.08:13:13.30/xfe/off,on,16.0 2006.196.08:13:13.69/ifatt/23,28,28,28 2006.196.08:13:14.08/fmout-gps/S +3.34E-07 2006.196.08:13:14.12:!2006.196.08:14:20 2006.196.08:14:20.00:data_valid=off 2006.196.08:14:20.00:postob 2006.196.08:14:20.16/cable/+6.3379E-03 2006.196.08:14:20.16/wx/29.14,1003.9,92 2006.196.08:14:21.07/fmout-gps/S +3.34E-07 2006.196.08:14:21.07:scan_name=196-0815,k06196,60 2006.196.08:14:21.07:source=0749+540,075301.38,535300.0,2000.0,ccw 2006.196.08:14:22.13#flagr#flagr/antenna,new-source 2006.196.08:14:22.13:checkk5 2006.196.08:14:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.196.08:14:22.89/chk_autoobs//k5ts2/ autoobs is running! 2006.196.08:14:23.26/chk_autoobs//k5ts3/ autoobs is running! 2006.196.08:14:23.64/chk_autoobs//k5ts4/ autoobs is running! 2006.196.08:14:24.00/chk_obsdata//k5ts1/T1960813??a.dat file size is correct (nominal:560MB, actual:560MB). 2006.196.08:14:24.37/chk_obsdata//k5ts2/T1960813??b.dat file size is correct (nominal:560MB, actual:560MB). 2006.196.08:14:24.75/chk_obsdata//k5ts3/T1960813??c.dat file size is correct (nominal:560MB, actual:560MB). 2006.196.08:14:25.11/chk_obsdata//k5ts4/T1960813??d.dat file size is correct (nominal:560MB, actual:560MB). 2006.196.08:14:25.80/k5log//k5ts1_log_newline 2006.196.08:14:26.50/k5log//k5ts2_log_newline 2006.196.08:14:27.18/k5log//k5ts3_log_newline 2006.196.08:14:27.87/k5log//k5ts4_log_newline 2006.196.08:14:27.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.196.08:14:27.90:4f8m12a=2 2006.196.08:14:27.90$4f8m12a/echo=on 2006.196.08:14:27.90$4f8m12a/pcalon 2006.196.08:14:27.90$pcalon/"no phase cal control is implemented here 2006.196.08:14:27.90$4f8m12a/"tpicd=stop 2006.196.08:14:27.90$4f8m12a/vc4f8 2006.196.08:14:27.90$vc4f8/valo=1,532.99 2006.196.08:14:27.90#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.196.08:14:27.90#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.196.08:14:27.90#ibcon#ireg 17 cls_cnt 0 2006.196.08:14:27.90#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.196.08:14:27.90#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.196.08:14:27.90#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.196.08:14:27.90#ibcon#enter wrdev, iclass 29, count 0 2006.196.08:14:27.90#ibcon#first serial, iclass 29, count 0 2006.196.08:14:27.90#ibcon#enter sib2, iclass 29, count 0 2006.196.08:14:27.90#ibcon#flushed, iclass 29, count 0 2006.196.08:14:27.90#ibcon#about to write, iclass 29, count 0 2006.196.08:14:27.90#ibcon#wrote, iclass 29, count 0 2006.196.08:14:27.90#ibcon#about to read 3, iclass 29, count 0 2006.196.08:14:27.94#ibcon#read 3, iclass 29, count 0 2006.196.08:14:27.94#ibcon#about to read 4, iclass 29, count 0 2006.196.08:14:27.94#ibcon#read 4, iclass 29, count 0 2006.196.08:14:27.94#ibcon#about to read 5, iclass 29, count 0 2006.196.08:14:27.94#ibcon#read 5, iclass 29, count 0 2006.196.08:14:27.94#ibcon#about to read 6, iclass 29, count 0 2006.196.08:14:27.94#ibcon#read 6, iclass 29, count 0 2006.196.08:14:27.94#ibcon#end of sib2, iclass 29, count 0 2006.196.08:14:27.94#ibcon#*mode == 0, iclass 29, count 0 2006.196.08:14:27.94#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.196.08:14:27.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.196.08:14:27.94#ibcon#*before write, iclass 29, count 0 2006.196.08:14:27.94#ibcon#enter sib2, iclass 29, count 0 2006.196.08:14:27.94#ibcon#flushed, iclass 29, count 0 2006.196.08:14:27.94#ibcon#about to write, iclass 29, count 0 2006.196.08:14:27.94#ibcon#wrote, iclass 29, count 0 2006.196.08:14:27.94#ibcon#about to read 3, iclass 29, count 0 2006.196.08:14:27.99#ibcon#read 3, iclass 29, count 0 2006.196.08:14:27.99#ibcon#about to read 4, iclass 29, count 0 2006.196.08:14:27.99#ibcon#read 4, iclass 29, count 0 2006.196.08:14:27.99#ibcon#about to read 5, iclass 29, count 0 2006.196.08:14:27.99#ibcon#read 5, iclass 29, count 0 2006.196.08:14:27.99#ibcon#about to read 6, iclass 29, count 0 2006.196.08:14:27.99#ibcon#read 6, iclass 29, count 0 2006.196.08:14:27.99#ibcon#end of sib2, iclass 29, count 0 2006.196.08:14:27.99#ibcon#*after write, iclass 29, count 0 2006.196.08:14:27.99#ibcon#*before return 0, iclass 29, count 0 2006.196.08:14:27.99#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.196.08:14:27.99#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.196.08:14:27.99#ibcon#about to clear, iclass 29 cls_cnt 0 2006.196.08:14:27.99#ibcon#cleared, iclass 29 cls_cnt 0 2006.196.08:14:27.99$vc4f8/va=1,8 2006.196.08:14:27.99#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.196.08:14:27.99#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.196.08:14:27.99#ibcon#ireg 11 cls_cnt 2 2006.196.08:14:27.99#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.196.08:14:27.99#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.196.08:14:27.99#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.196.08:14:27.99#ibcon#enter wrdev, iclass 31, count 2 2006.196.08:14:27.99#ibcon#first serial, iclass 31, count 2 2006.196.08:14:27.99#ibcon#enter sib2, iclass 31, count 2 2006.196.08:14:27.99#ibcon#flushed, iclass 31, count 2 2006.196.08:14:27.99#ibcon#about to write, iclass 31, count 2 2006.196.08:14:27.99#ibcon#wrote, iclass 31, count 2 2006.196.08:14:27.99#ibcon#about to read 3, iclass 31, count 2 2006.196.08:14:28.01#ibcon#read 3, iclass 31, count 2 2006.196.08:14:28.01#ibcon#about to read 4, iclass 31, count 2 2006.196.08:14:28.01#ibcon#read 4, iclass 31, count 2 2006.196.08:14:28.01#ibcon#about to read 5, iclass 31, count 2 2006.196.08:14:28.01#ibcon#read 5, iclass 31, count 2 2006.196.08:14:28.01#ibcon#about to read 6, iclass 31, count 2 2006.196.08:14:28.01#ibcon#read 6, iclass 31, count 2 2006.196.08:14:28.01#ibcon#end of sib2, iclass 31, count 2 2006.196.08:14:28.01#ibcon#*mode == 0, iclass 31, count 2 2006.196.08:14:28.01#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.196.08:14:28.01#ibcon#[25=AT01-08\r\n] 2006.196.08:14:28.01#ibcon#*before write, iclass 31, count 2 2006.196.08:14:28.01#ibcon#enter sib2, iclass 31, count 2 2006.196.08:14:28.01#ibcon#flushed, iclass 31, count 2 2006.196.08:14:28.01#ibcon#about to write, iclass 31, count 2 2006.196.08:14:28.01#ibcon#wrote, iclass 31, count 2 2006.196.08:14:28.01#ibcon#about to read 3, iclass 31, count 2 2006.196.08:14:28.04#ibcon#read 3, iclass 31, count 2 2006.196.08:14:28.04#ibcon#about to read 4, iclass 31, count 2 2006.196.08:14:28.04#ibcon#read 4, iclass 31, count 2 2006.196.08:14:28.04#ibcon#about to read 5, iclass 31, count 2 2006.196.08:14:28.04#ibcon#read 5, iclass 31, count 2 2006.196.08:14:28.04#ibcon#about to read 6, iclass 31, count 2 2006.196.08:14:28.04#ibcon#read 6, iclass 31, count 2 2006.196.08:14:28.04#ibcon#end of sib2, iclass 31, count 2 2006.196.08:14:28.04#ibcon#*after write, iclass 31, count 2 2006.196.08:14:28.04#ibcon#*before return 0, iclass 31, count 2 2006.196.08:14:28.04#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.196.08:14:28.04#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.196.08:14:28.04#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.196.08:14:28.04#ibcon#ireg 7 cls_cnt 0 2006.196.08:14:28.04#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.196.08:14:28.16#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.196.08:14:28.16#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.196.08:14:28.16#ibcon#enter wrdev, iclass 31, count 0 2006.196.08:14:28.16#ibcon#first serial, iclass 31, count 0 2006.196.08:14:28.16#ibcon#enter sib2, iclass 31, count 0 2006.196.08:14:28.16#ibcon#flushed, iclass 31, count 0 2006.196.08:14:28.16#ibcon#about to write, iclass 31, count 0 2006.196.08:14:28.16#ibcon#wrote, iclass 31, count 0 2006.196.08:14:28.16#ibcon#about to read 3, iclass 31, count 0 2006.196.08:14:28.18#ibcon#read 3, iclass 31, count 0 2006.196.08:14:28.18#ibcon#about to read 4, iclass 31, count 0 2006.196.08:14:28.18#ibcon#read 4, iclass 31, count 0 2006.196.08:14:28.18#ibcon#about to read 5, iclass 31, count 0 2006.196.08:14:28.18#ibcon#read 5, iclass 31, count 0 2006.196.08:14:28.18#ibcon#about to read 6, iclass 31, count 0 2006.196.08:14:28.18#ibcon#read 6, iclass 31, count 0 2006.196.08:14:28.18#ibcon#end of sib2, iclass 31, count 0 2006.196.08:14:28.18#ibcon#*mode == 0, iclass 31, count 0 2006.196.08:14:28.18#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.196.08:14:28.18#ibcon#[25=USB\r\n] 2006.196.08:14:28.18#ibcon#*before write, iclass 31, count 0 2006.196.08:14:28.18#ibcon#enter sib2, iclass 31, count 0 2006.196.08:14:28.18#ibcon#flushed, iclass 31, count 0 2006.196.08:14:28.18#ibcon#about to write, iclass 31, count 0 2006.196.08:14:28.18#ibcon#wrote, iclass 31, count 0 2006.196.08:14:28.18#ibcon#about to read 3, iclass 31, count 0 2006.196.08:14:28.21#ibcon#read 3, iclass 31, count 0 2006.196.08:14:28.21#ibcon#about to read 4, iclass 31, count 0 2006.196.08:14:28.21#ibcon#read 4, iclass 31, count 0 2006.196.08:14:28.21#ibcon#about to read 5, iclass 31, count 0 2006.196.08:14:28.21#ibcon#read 5, iclass 31, count 0 2006.196.08:14:28.21#ibcon#about to read 6, iclass 31, count 0 2006.196.08:14:28.21#ibcon#read 6, iclass 31, count 0 2006.196.08:14:28.21#ibcon#end of sib2, iclass 31, count 0 2006.196.08:14:28.21#ibcon#*after write, iclass 31, count 0 2006.196.08:14:28.21#ibcon#*before return 0, iclass 31, count 0 2006.196.08:14:28.21#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.196.08:14:28.21#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.196.08:14:28.21#ibcon#about to clear, iclass 31 cls_cnt 0 2006.196.08:14:28.21#ibcon#cleared, iclass 31 cls_cnt 0 2006.196.08:14:28.21$vc4f8/valo=2,572.99 2006.196.08:14:28.21#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.196.08:14:28.21#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.196.08:14:28.21#ibcon#ireg 17 cls_cnt 0 2006.196.08:14:28.21#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:14:28.21#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:14:28.21#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:14:28.21#ibcon#enter wrdev, iclass 33, count 0 2006.196.08:14:28.21#ibcon#first serial, iclass 33, count 0 2006.196.08:14:28.21#ibcon#enter sib2, iclass 33, count 0 2006.196.08:14:28.21#ibcon#flushed, iclass 33, count 0 2006.196.08:14:28.21#ibcon#about to write, iclass 33, count 0 2006.196.08:14:28.21#ibcon#wrote, iclass 33, count 0 2006.196.08:14:28.21#ibcon#about to read 3, iclass 33, count 0 2006.196.08:14:28.23#ibcon#read 3, iclass 33, count 0 2006.196.08:14:28.23#ibcon#about to read 4, iclass 33, count 0 2006.196.08:14:28.23#ibcon#read 4, iclass 33, count 0 2006.196.08:14:28.23#ibcon#about to read 5, iclass 33, count 0 2006.196.08:14:28.23#ibcon#read 5, iclass 33, count 0 2006.196.08:14:28.23#ibcon#about to read 6, iclass 33, count 0 2006.196.08:14:28.23#ibcon#read 6, iclass 33, count 0 2006.196.08:14:28.23#ibcon#end of sib2, iclass 33, count 0 2006.196.08:14:28.23#ibcon#*mode == 0, iclass 33, count 0 2006.196.08:14:28.23#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.196.08:14:28.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.196.08:14:28.23#ibcon#*before write, iclass 33, count 0 2006.196.08:14:28.23#ibcon#enter sib2, iclass 33, count 0 2006.196.08:14:28.23#ibcon#flushed, iclass 33, count 0 2006.196.08:14:28.23#ibcon#about to write, iclass 33, count 0 2006.196.08:14:28.23#ibcon#wrote, iclass 33, count 0 2006.196.08:14:28.23#ibcon#about to read 3, iclass 33, count 0 2006.196.08:14:28.27#ibcon#read 3, iclass 33, count 0 2006.196.08:14:28.27#ibcon#about to read 4, iclass 33, count 0 2006.196.08:14:28.27#ibcon#read 4, iclass 33, count 0 2006.196.08:14:28.27#ibcon#about to read 5, iclass 33, count 0 2006.196.08:14:28.27#ibcon#read 5, iclass 33, count 0 2006.196.08:14:28.27#ibcon#about to read 6, iclass 33, count 0 2006.196.08:14:28.27#ibcon#read 6, iclass 33, count 0 2006.196.08:14:28.27#ibcon#end of sib2, iclass 33, count 0 2006.196.08:14:28.27#ibcon#*after write, iclass 33, count 0 2006.196.08:14:28.27#ibcon#*before return 0, iclass 33, count 0 2006.196.08:14:28.27#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:14:28.27#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:14:28.27#ibcon#about to clear, iclass 33 cls_cnt 0 2006.196.08:14:28.27#ibcon#cleared, iclass 33 cls_cnt 0 2006.196.08:14:28.27$vc4f8/va=2,7 2006.196.08:14:28.27#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.196.08:14:28.27#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.196.08:14:28.27#ibcon#ireg 11 cls_cnt 2 2006.196.08:14:28.27#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.196.08:14:28.33#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.196.08:14:28.33#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.196.08:14:28.33#ibcon#enter wrdev, iclass 35, count 2 2006.196.08:14:28.33#ibcon#first serial, iclass 35, count 2 2006.196.08:14:28.33#ibcon#enter sib2, iclass 35, count 2 2006.196.08:14:28.33#ibcon#flushed, iclass 35, count 2 2006.196.08:14:28.33#ibcon#about to write, iclass 35, count 2 2006.196.08:14:28.33#ibcon#wrote, iclass 35, count 2 2006.196.08:14:28.33#ibcon#about to read 3, iclass 35, count 2 2006.196.08:14:28.35#ibcon#read 3, iclass 35, count 2 2006.196.08:14:28.35#ibcon#about to read 4, iclass 35, count 2 2006.196.08:14:28.35#ibcon#read 4, iclass 35, count 2 2006.196.08:14:28.35#ibcon#about to read 5, iclass 35, count 2 2006.196.08:14:28.35#ibcon#read 5, iclass 35, count 2 2006.196.08:14:28.35#ibcon#about to read 6, iclass 35, count 2 2006.196.08:14:28.35#ibcon#read 6, iclass 35, count 2 2006.196.08:14:28.35#ibcon#end of sib2, iclass 35, count 2 2006.196.08:14:28.35#ibcon#*mode == 0, iclass 35, count 2 2006.196.08:14:28.35#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.196.08:14:28.35#ibcon#[25=AT02-07\r\n] 2006.196.08:14:28.35#ibcon#*before write, iclass 35, count 2 2006.196.08:14:28.35#ibcon#enter sib2, iclass 35, count 2 2006.196.08:14:28.35#ibcon#flushed, iclass 35, count 2 2006.196.08:14:28.35#ibcon#about to write, iclass 35, count 2 2006.196.08:14:28.35#ibcon#wrote, iclass 35, count 2 2006.196.08:14:28.35#ibcon#about to read 3, iclass 35, count 2 2006.196.08:14:28.38#ibcon#read 3, iclass 35, count 2 2006.196.08:14:28.38#ibcon#about to read 4, iclass 35, count 2 2006.196.08:14:28.38#ibcon#read 4, iclass 35, count 2 2006.196.08:14:28.38#ibcon#about to read 5, iclass 35, count 2 2006.196.08:14:28.38#ibcon#read 5, iclass 35, count 2 2006.196.08:14:28.38#ibcon#about to read 6, iclass 35, count 2 2006.196.08:14:28.38#ibcon#read 6, iclass 35, count 2 2006.196.08:14:28.38#ibcon#end of sib2, iclass 35, count 2 2006.196.08:14:28.38#ibcon#*after write, iclass 35, count 2 2006.196.08:14:28.38#ibcon#*before return 0, iclass 35, count 2 2006.196.08:14:28.38#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.196.08:14:28.38#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.196.08:14:28.38#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.196.08:14:28.38#ibcon#ireg 7 cls_cnt 0 2006.196.08:14:28.38#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.196.08:14:28.50#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.196.08:14:28.50#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.196.08:14:28.50#ibcon#enter wrdev, iclass 35, count 0 2006.196.08:14:28.50#ibcon#first serial, iclass 35, count 0 2006.196.08:14:28.50#ibcon#enter sib2, iclass 35, count 0 2006.196.08:14:28.50#ibcon#flushed, iclass 35, count 0 2006.196.08:14:28.50#ibcon#about to write, iclass 35, count 0 2006.196.08:14:28.50#ibcon#wrote, iclass 35, count 0 2006.196.08:14:28.50#ibcon#about to read 3, iclass 35, count 0 2006.196.08:14:28.52#ibcon#read 3, iclass 35, count 0 2006.196.08:14:28.52#ibcon#about to read 4, iclass 35, count 0 2006.196.08:14:28.52#ibcon#read 4, iclass 35, count 0 2006.196.08:14:28.52#ibcon#about to read 5, iclass 35, count 0 2006.196.08:14:28.52#ibcon#read 5, iclass 35, count 0 2006.196.08:14:28.52#ibcon#about to read 6, iclass 35, count 0 2006.196.08:14:28.52#ibcon#read 6, iclass 35, count 0 2006.196.08:14:28.52#ibcon#end of sib2, iclass 35, count 0 2006.196.08:14:28.52#ibcon#*mode == 0, iclass 35, count 0 2006.196.08:14:28.52#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.196.08:14:28.52#ibcon#[25=USB\r\n] 2006.196.08:14:28.52#ibcon#*before write, iclass 35, count 0 2006.196.08:14:28.52#ibcon#enter sib2, iclass 35, count 0 2006.196.08:14:28.52#ibcon#flushed, iclass 35, count 0 2006.196.08:14:28.52#ibcon#about to write, iclass 35, count 0 2006.196.08:14:28.52#ibcon#wrote, iclass 35, count 0 2006.196.08:14:28.52#ibcon#about to read 3, iclass 35, count 0 2006.196.08:14:28.55#ibcon#read 3, iclass 35, count 0 2006.196.08:14:28.55#ibcon#about to read 4, iclass 35, count 0 2006.196.08:14:28.55#ibcon#read 4, iclass 35, count 0 2006.196.08:14:28.55#ibcon#about to read 5, iclass 35, count 0 2006.196.08:14:28.55#ibcon#read 5, iclass 35, count 0 2006.196.08:14:28.55#ibcon#about to read 6, iclass 35, count 0 2006.196.08:14:28.55#ibcon#read 6, iclass 35, count 0 2006.196.08:14:28.55#ibcon#end of sib2, iclass 35, count 0 2006.196.08:14:28.55#ibcon#*after write, iclass 35, count 0 2006.196.08:14:28.55#ibcon#*before return 0, iclass 35, count 0 2006.196.08:14:28.55#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.196.08:14:28.55#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.196.08:14:28.55#ibcon#about to clear, iclass 35 cls_cnt 0 2006.196.08:14:28.55#ibcon#cleared, iclass 35 cls_cnt 0 2006.196.08:14:28.55$vc4f8/valo=3,672.99 2006.196.08:14:28.55#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.196.08:14:28.55#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.196.08:14:28.55#ibcon#ireg 17 cls_cnt 0 2006.196.08:14:28.55#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.196.08:14:28.55#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.196.08:14:28.55#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.196.08:14:28.55#ibcon#enter wrdev, iclass 37, count 0 2006.196.08:14:28.55#ibcon#first serial, iclass 37, count 0 2006.196.08:14:28.55#ibcon#enter sib2, iclass 37, count 0 2006.196.08:14:28.55#ibcon#flushed, iclass 37, count 0 2006.196.08:14:28.55#ibcon#about to write, iclass 37, count 0 2006.196.08:14:28.55#ibcon#wrote, iclass 37, count 0 2006.196.08:14:28.55#ibcon#about to read 3, iclass 37, count 0 2006.196.08:14:28.57#ibcon#read 3, iclass 37, count 0 2006.196.08:14:28.57#ibcon#about to read 4, iclass 37, count 0 2006.196.08:14:28.57#ibcon#read 4, iclass 37, count 0 2006.196.08:14:28.57#ibcon#about to read 5, iclass 37, count 0 2006.196.08:14:28.57#ibcon#read 5, iclass 37, count 0 2006.196.08:14:28.57#ibcon#about to read 6, iclass 37, count 0 2006.196.08:14:28.57#ibcon#read 6, iclass 37, count 0 2006.196.08:14:28.57#ibcon#end of sib2, iclass 37, count 0 2006.196.08:14:28.57#ibcon#*mode == 0, iclass 37, count 0 2006.196.08:14:28.57#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.196.08:14:28.57#ibcon#[26=FRQ=03,672.99\r\n] 2006.196.08:14:28.57#ibcon#*before write, iclass 37, count 0 2006.196.08:14:28.57#ibcon#enter sib2, iclass 37, count 0 2006.196.08:14:28.57#ibcon#flushed, iclass 37, count 0 2006.196.08:14:28.57#ibcon#about to write, iclass 37, count 0 2006.196.08:14:28.57#ibcon#wrote, iclass 37, count 0 2006.196.08:14:28.57#ibcon#about to read 3, iclass 37, count 0 2006.196.08:14:28.61#ibcon#read 3, iclass 37, count 0 2006.196.08:14:28.61#ibcon#about to read 4, iclass 37, count 0 2006.196.08:14:28.61#ibcon#read 4, iclass 37, count 0 2006.196.08:14:28.61#ibcon#about to read 5, iclass 37, count 0 2006.196.08:14:28.61#ibcon#read 5, iclass 37, count 0 2006.196.08:14:28.61#ibcon#about to read 6, iclass 37, count 0 2006.196.08:14:28.61#ibcon#read 6, iclass 37, count 0 2006.196.08:14:28.61#ibcon#end of sib2, iclass 37, count 0 2006.196.08:14:28.61#ibcon#*after write, iclass 37, count 0 2006.196.08:14:28.61#ibcon#*before return 0, iclass 37, count 0 2006.196.08:14:28.61#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.196.08:14:28.61#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.196.08:14:28.61#ibcon#about to clear, iclass 37 cls_cnt 0 2006.196.08:14:28.61#ibcon#cleared, iclass 37 cls_cnt 0 2006.196.08:14:28.61$vc4f8/va=3,6 2006.196.08:14:28.61#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.196.08:14:28.61#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.196.08:14:28.61#ibcon#ireg 11 cls_cnt 2 2006.196.08:14:28.61#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.196.08:14:28.67#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.196.08:14:28.67#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.196.08:14:28.67#ibcon#enter wrdev, iclass 39, count 2 2006.196.08:14:28.67#ibcon#first serial, iclass 39, count 2 2006.196.08:14:28.67#ibcon#enter sib2, iclass 39, count 2 2006.196.08:14:28.67#ibcon#flushed, iclass 39, count 2 2006.196.08:14:28.67#ibcon#about to write, iclass 39, count 2 2006.196.08:14:28.67#ibcon#wrote, iclass 39, count 2 2006.196.08:14:28.67#ibcon#about to read 3, iclass 39, count 2 2006.196.08:14:28.69#ibcon#read 3, iclass 39, count 2 2006.196.08:14:28.69#ibcon#about to read 4, iclass 39, count 2 2006.196.08:14:28.69#ibcon#read 4, iclass 39, count 2 2006.196.08:14:28.69#ibcon#about to read 5, iclass 39, count 2 2006.196.08:14:28.69#ibcon#read 5, iclass 39, count 2 2006.196.08:14:28.69#ibcon#about to read 6, iclass 39, count 2 2006.196.08:14:28.69#ibcon#read 6, iclass 39, count 2 2006.196.08:14:28.69#ibcon#end of sib2, iclass 39, count 2 2006.196.08:14:28.69#ibcon#*mode == 0, iclass 39, count 2 2006.196.08:14:28.69#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.196.08:14:28.69#ibcon#[25=AT03-06\r\n] 2006.196.08:14:28.69#ibcon#*before write, iclass 39, count 2 2006.196.08:14:28.69#ibcon#enter sib2, iclass 39, count 2 2006.196.08:14:28.69#ibcon#flushed, iclass 39, count 2 2006.196.08:14:28.69#ibcon#about to write, iclass 39, count 2 2006.196.08:14:28.69#ibcon#wrote, iclass 39, count 2 2006.196.08:14:28.69#ibcon#about to read 3, iclass 39, count 2 2006.196.08:14:28.73#ibcon#read 3, iclass 39, count 2 2006.196.08:14:28.73#ibcon#about to read 4, iclass 39, count 2 2006.196.08:14:28.73#ibcon#read 4, iclass 39, count 2 2006.196.08:14:28.73#ibcon#about to read 5, iclass 39, count 2 2006.196.08:14:28.73#ibcon#read 5, iclass 39, count 2 2006.196.08:14:28.73#ibcon#about to read 6, iclass 39, count 2 2006.196.08:14:28.73#ibcon#read 6, iclass 39, count 2 2006.196.08:14:28.73#ibcon#end of sib2, iclass 39, count 2 2006.196.08:14:28.73#ibcon#*after write, iclass 39, count 2 2006.196.08:14:28.73#ibcon#*before return 0, iclass 39, count 2 2006.196.08:14:28.73#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.196.08:14:28.73#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.196.08:14:28.73#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.196.08:14:28.73#ibcon#ireg 7 cls_cnt 0 2006.196.08:14:28.73#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.196.08:14:28.85#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.196.08:14:28.85#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.196.08:14:28.85#ibcon#enter wrdev, iclass 39, count 0 2006.196.08:14:28.85#ibcon#first serial, iclass 39, count 0 2006.196.08:14:28.85#ibcon#enter sib2, iclass 39, count 0 2006.196.08:14:28.85#ibcon#flushed, iclass 39, count 0 2006.196.08:14:28.85#ibcon#about to write, iclass 39, count 0 2006.196.08:14:28.85#ibcon#wrote, iclass 39, count 0 2006.196.08:14:28.85#ibcon#about to read 3, iclass 39, count 0 2006.196.08:14:28.87#ibcon#read 3, iclass 39, count 0 2006.196.08:14:28.87#ibcon#about to read 4, iclass 39, count 0 2006.196.08:14:28.87#ibcon#read 4, iclass 39, count 0 2006.196.08:14:28.87#ibcon#about to read 5, iclass 39, count 0 2006.196.08:14:28.87#ibcon#read 5, iclass 39, count 0 2006.196.08:14:28.87#ibcon#about to read 6, iclass 39, count 0 2006.196.08:14:28.87#ibcon#read 6, iclass 39, count 0 2006.196.08:14:28.87#ibcon#end of sib2, iclass 39, count 0 2006.196.08:14:28.87#ibcon#*mode == 0, iclass 39, count 0 2006.196.08:14:28.87#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.196.08:14:28.87#ibcon#[25=USB\r\n] 2006.196.08:14:28.87#ibcon#*before write, iclass 39, count 0 2006.196.08:14:28.87#ibcon#enter sib2, iclass 39, count 0 2006.196.08:14:28.87#ibcon#flushed, iclass 39, count 0 2006.196.08:14:28.87#ibcon#about to write, iclass 39, count 0 2006.196.08:14:28.87#ibcon#wrote, iclass 39, count 0 2006.196.08:14:28.87#ibcon#about to read 3, iclass 39, count 0 2006.196.08:14:28.90#ibcon#read 3, iclass 39, count 0 2006.196.08:14:28.90#ibcon#about to read 4, iclass 39, count 0 2006.196.08:14:28.90#ibcon#read 4, iclass 39, count 0 2006.196.08:14:28.90#ibcon#about to read 5, iclass 39, count 0 2006.196.08:14:28.90#ibcon#read 5, iclass 39, count 0 2006.196.08:14:28.90#ibcon#about to read 6, iclass 39, count 0 2006.196.08:14:28.90#ibcon#read 6, iclass 39, count 0 2006.196.08:14:28.90#ibcon#end of sib2, iclass 39, count 0 2006.196.08:14:28.90#ibcon#*after write, iclass 39, count 0 2006.196.08:14:28.90#ibcon#*before return 0, iclass 39, count 0 2006.196.08:14:28.90#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.196.08:14:28.90#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.196.08:14:28.90#ibcon#about to clear, iclass 39 cls_cnt 0 2006.196.08:14:28.90#ibcon#cleared, iclass 39 cls_cnt 0 2006.196.08:14:28.90$vc4f8/valo=4,832.99 2006.196.08:14:28.90#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.196.08:14:28.90#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.196.08:14:28.90#ibcon#ireg 17 cls_cnt 0 2006.196.08:14:28.90#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.196.08:14:28.90#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.196.08:14:28.90#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.196.08:14:28.90#ibcon#enter wrdev, iclass 3, count 0 2006.196.08:14:28.90#ibcon#first serial, iclass 3, count 0 2006.196.08:14:28.90#ibcon#enter sib2, iclass 3, count 0 2006.196.08:14:28.90#ibcon#flushed, iclass 3, count 0 2006.196.08:14:28.90#ibcon#about to write, iclass 3, count 0 2006.196.08:14:28.90#ibcon#wrote, iclass 3, count 0 2006.196.08:14:28.90#ibcon#about to read 3, iclass 3, count 0 2006.196.08:14:28.92#ibcon#read 3, iclass 3, count 0 2006.196.08:14:28.92#ibcon#about to read 4, iclass 3, count 0 2006.196.08:14:28.92#ibcon#read 4, iclass 3, count 0 2006.196.08:14:28.92#ibcon#about to read 5, iclass 3, count 0 2006.196.08:14:28.92#ibcon#read 5, iclass 3, count 0 2006.196.08:14:28.92#ibcon#about to read 6, iclass 3, count 0 2006.196.08:14:28.92#ibcon#read 6, iclass 3, count 0 2006.196.08:14:28.92#ibcon#end of sib2, iclass 3, count 0 2006.196.08:14:28.92#ibcon#*mode == 0, iclass 3, count 0 2006.196.08:14:28.92#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.196.08:14:28.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.196.08:14:28.92#ibcon#*before write, iclass 3, count 0 2006.196.08:14:28.92#ibcon#enter sib2, iclass 3, count 0 2006.196.08:14:28.92#ibcon#flushed, iclass 3, count 0 2006.196.08:14:28.92#ibcon#about to write, iclass 3, count 0 2006.196.08:14:28.92#ibcon#wrote, iclass 3, count 0 2006.196.08:14:28.92#ibcon#about to read 3, iclass 3, count 0 2006.196.08:14:28.96#ibcon#read 3, iclass 3, count 0 2006.196.08:14:28.96#ibcon#about to read 4, iclass 3, count 0 2006.196.08:14:28.96#ibcon#read 4, iclass 3, count 0 2006.196.08:14:28.96#ibcon#about to read 5, iclass 3, count 0 2006.196.08:14:28.96#ibcon#read 5, iclass 3, count 0 2006.196.08:14:28.96#ibcon#about to read 6, iclass 3, count 0 2006.196.08:14:28.96#ibcon#read 6, iclass 3, count 0 2006.196.08:14:28.96#ibcon#end of sib2, iclass 3, count 0 2006.196.08:14:28.96#ibcon#*after write, iclass 3, count 0 2006.196.08:14:28.96#ibcon#*before return 0, iclass 3, count 0 2006.196.08:14:28.96#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.196.08:14:28.96#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.196.08:14:28.96#ibcon#about to clear, iclass 3 cls_cnt 0 2006.196.08:14:28.96#ibcon#cleared, iclass 3 cls_cnt 0 2006.196.08:14:28.96$vc4f8/va=4,7 2006.196.08:14:28.96#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.196.08:14:28.96#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.196.08:14:28.96#ibcon#ireg 11 cls_cnt 2 2006.196.08:14:28.96#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.196.08:14:29.02#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.196.08:14:29.02#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.196.08:14:29.02#ibcon#enter wrdev, iclass 5, count 2 2006.196.08:14:29.02#ibcon#first serial, iclass 5, count 2 2006.196.08:14:29.02#ibcon#enter sib2, iclass 5, count 2 2006.196.08:14:29.02#ibcon#flushed, iclass 5, count 2 2006.196.08:14:29.02#ibcon#about to write, iclass 5, count 2 2006.196.08:14:29.02#ibcon#wrote, iclass 5, count 2 2006.196.08:14:29.02#ibcon#about to read 3, iclass 5, count 2 2006.196.08:14:29.04#ibcon#read 3, iclass 5, count 2 2006.196.08:14:29.04#ibcon#about to read 4, iclass 5, count 2 2006.196.08:14:29.04#ibcon#read 4, iclass 5, count 2 2006.196.08:14:29.04#ibcon#about to read 5, iclass 5, count 2 2006.196.08:14:29.04#ibcon#read 5, iclass 5, count 2 2006.196.08:14:29.04#ibcon#about to read 6, iclass 5, count 2 2006.196.08:14:29.04#ibcon#read 6, iclass 5, count 2 2006.196.08:14:29.04#ibcon#end of sib2, iclass 5, count 2 2006.196.08:14:29.04#ibcon#*mode == 0, iclass 5, count 2 2006.196.08:14:29.04#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.196.08:14:29.04#ibcon#[25=AT04-07\r\n] 2006.196.08:14:29.04#ibcon#*before write, iclass 5, count 2 2006.196.08:14:29.04#ibcon#enter sib2, iclass 5, count 2 2006.196.08:14:29.04#ibcon#flushed, iclass 5, count 2 2006.196.08:14:29.04#ibcon#about to write, iclass 5, count 2 2006.196.08:14:29.04#ibcon#wrote, iclass 5, count 2 2006.196.08:14:29.04#ibcon#about to read 3, iclass 5, count 2 2006.196.08:14:29.07#ibcon#read 3, iclass 5, count 2 2006.196.08:14:29.07#ibcon#about to read 4, iclass 5, count 2 2006.196.08:14:29.07#ibcon#read 4, iclass 5, count 2 2006.196.08:14:29.07#ibcon#about to read 5, iclass 5, count 2 2006.196.08:14:29.07#ibcon#read 5, iclass 5, count 2 2006.196.08:14:29.07#ibcon#about to read 6, iclass 5, count 2 2006.196.08:14:29.07#ibcon#read 6, iclass 5, count 2 2006.196.08:14:29.07#ibcon#end of sib2, iclass 5, count 2 2006.196.08:14:29.07#ibcon#*after write, iclass 5, count 2 2006.196.08:14:29.07#ibcon#*before return 0, iclass 5, count 2 2006.196.08:14:29.07#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.196.08:14:29.07#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.196.08:14:29.07#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.196.08:14:29.07#ibcon#ireg 7 cls_cnt 0 2006.196.08:14:29.07#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.196.08:14:29.19#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.196.08:14:29.19#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.196.08:14:29.19#ibcon#enter wrdev, iclass 5, count 0 2006.196.08:14:29.19#ibcon#first serial, iclass 5, count 0 2006.196.08:14:29.19#ibcon#enter sib2, iclass 5, count 0 2006.196.08:14:29.19#ibcon#flushed, iclass 5, count 0 2006.196.08:14:29.19#ibcon#about to write, iclass 5, count 0 2006.196.08:14:29.19#ibcon#wrote, iclass 5, count 0 2006.196.08:14:29.19#ibcon#about to read 3, iclass 5, count 0 2006.196.08:14:29.21#ibcon#read 3, iclass 5, count 0 2006.196.08:14:29.21#ibcon#about to read 4, iclass 5, count 0 2006.196.08:14:29.21#ibcon#read 4, iclass 5, count 0 2006.196.08:14:29.21#ibcon#about to read 5, iclass 5, count 0 2006.196.08:14:29.21#ibcon#read 5, iclass 5, count 0 2006.196.08:14:29.21#ibcon#about to read 6, iclass 5, count 0 2006.196.08:14:29.21#ibcon#read 6, iclass 5, count 0 2006.196.08:14:29.21#ibcon#end of sib2, iclass 5, count 0 2006.196.08:14:29.21#ibcon#*mode == 0, iclass 5, count 0 2006.196.08:14:29.21#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.196.08:14:29.21#ibcon#[25=USB\r\n] 2006.196.08:14:29.21#ibcon#*before write, iclass 5, count 0 2006.196.08:14:29.21#ibcon#enter sib2, iclass 5, count 0 2006.196.08:14:29.21#ibcon#flushed, iclass 5, count 0 2006.196.08:14:29.21#ibcon#about to write, iclass 5, count 0 2006.196.08:14:29.21#ibcon#wrote, iclass 5, count 0 2006.196.08:14:29.21#ibcon#about to read 3, iclass 5, count 0 2006.196.08:14:29.24#ibcon#read 3, iclass 5, count 0 2006.196.08:14:29.24#ibcon#about to read 4, iclass 5, count 0 2006.196.08:14:29.24#ibcon#read 4, iclass 5, count 0 2006.196.08:14:29.24#ibcon#about to read 5, iclass 5, count 0 2006.196.08:14:29.24#ibcon#read 5, iclass 5, count 0 2006.196.08:14:29.24#ibcon#about to read 6, iclass 5, count 0 2006.196.08:14:29.24#ibcon#read 6, iclass 5, count 0 2006.196.08:14:29.24#ibcon#end of sib2, iclass 5, count 0 2006.196.08:14:29.24#ibcon#*after write, iclass 5, count 0 2006.196.08:14:29.24#ibcon#*before return 0, iclass 5, count 0 2006.196.08:14:29.24#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.196.08:14:29.24#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.196.08:14:29.24#ibcon#about to clear, iclass 5 cls_cnt 0 2006.196.08:14:29.24#ibcon#cleared, iclass 5 cls_cnt 0 2006.196.08:14:29.24$vc4f8/valo=5,652.99 2006.196.08:14:29.24#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.196.08:14:29.24#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.196.08:14:29.24#ibcon#ireg 17 cls_cnt 0 2006.196.08:14:29.24#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.196.08:14:29.24#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.196.08:14:29.24#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.196.08:14:29.24#ibcon#enter wrdev, iclass 7, count 0 2006.196.08:14:29.24#ibcon#first serial, iclass 7, count 0 2006.196.08:14:29.24#ibcon#enter sib2, iclass 7, count 0 2006.196.08:14:29.24#ibcon#flushed, iclass 7, count 0 2006.196.08:14:29.24#ibcon#about to write, iclass 7, count 0 2006.196.08:14:29.24#ibcon#wrote, iclass 7, count 0 2006.196.08:14:29.24#ibcon#about to read 3, iclass 7, count 0 2006.196.08:14:29.26#ibcon#read 3, iclass 7, count 0 2006.196.08:14:29.26#ibcon#about to read 4, iclass 7, count 0 2006.196.08:14:29.26#ibcon#read 4, iclass 7, count 0 2006.196.08:14:29.26#ibcon#about to read 5, iclass 7, count 0 2006.196.08:14:29.26#ibcon#read 5, iclass 7, count 0 2006.196.08:14:29.26#ibcon#about to read 6, iclass 7, count 0 2006.196.08:14:29.26#ibcon#read 6, iclass 7, count 0 2006.196.08:14:29.26#ibcon#end of sib2, iclass 7, count 0 2006.196.08:14:29.26#ibcon#*mode == 0, iclass 7, count 0 2006.196.08:14:29.26#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.196.08:14:29.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.196.08:14:29.26#ibcon#*before write, iclass 7, count 0 2006.196.08:14:29.26#ibcon#enter sib2, iclass 7, count 0 2006.196.08:14:29.26#ibcon#flushed, iclass 7, count 0 2006.196.08:14:29.26#ibcon#about to write, iclass 7, count 0 2006.196.08:14:29.26#ibcon#wrote, iclass 7, count 0 2006.196.08:14:29.26#ibcon#about to read 3, iclass 7, count 0 2006.196.08:14:29.30#ibcon#read 3, iclass 7, count 0 2006.196.08:14:29.30#ibcon#about to read 4, iclass 7, count 0 2006.196.08:14:29.30#ibcon#read 4, iclass 7, count 0 2006.196.08:14:29.30#ibcon#about to read 5, iclass 7, count 0 2006.196.08:14:29.30#ibcon#read 5, iclass 7, count 0 2006.196.08:14:29.30#ibcon#about to read 6, iclass 7, count 0 2006.196.08:14:29.30#ibcon#read 6, iclass 7, count 0 2006.196.08:14:29.30#ibcon#end of sib2, iclass 7, count 0 2006.196.08:14:29.30#ibcon#*after write, iclass 7, count 0 2006.196.08:14:29.30#ibcon#*before return 0, iclass 7, count 0 2006.196.08:14:29.30#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.196.08:14:29.30#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.196.08:14:29.30#ibcon#about to clear, iclass 7 cls_cnt 0 2006.196.08:14:29.30#ibcon#cleared, iclass 7 cls_cnt 0 2006.196.08:14:29.30$vc4f8/va=5,7 2006.196.08:14:29.30#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.196.08:14:29.30#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.196.08:14:29.30#ibcon#ireg 11 cls_cnt 2 2006.196.08:14:29.30#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.196.08:14:29.36#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.196.08:14:29.36#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.196.08:14:29.36#ibcon#enter wrdev, iclass 11, count 2 2006.196.08:14:29.36#ibcon#first serial, iclass 11, count 2 2006.196.08:14:29.36#ibcon#enter sib2, iclass 11, count 2 2006.196.08:14:29.36#ibcon#flushed, iclass 11, count 2 2006.196.08:14:29.36#ibcon#about to write, iclass 11, count 2 2006.196.08:14:29.36#ibcon#wrote, iclass 11, count 2 2006.196.08:14:29.36#ibcon#about to read 3, iclass 11, count 2 2006.196.08:14:29.38#ibcon#read 3, iclass 11, count 2 2006.196.08:14:29.38#ibcon#about to read 4, iclass 11, count 2 2006.196.08:14:29.38#ibcon#read 4, iclass 11, count 2 2006.196.08:14:29.38#ibcon#about to read 5, iclass 11, count 2 2006.196.08:14:29.38#ibcon#read 5, iclass 11, count 2 2006.196.08:14:29.38#ibcon#about to read 6, iclass 11, count 2 2006.196.08:14:29.38#ibcon#read 6, iclass 11, count 2 2006.196.08:14:29.38#ibcon#end of sib2, iclass 11, count 2 2006.196.08:14:29.38#ibcon#*mode == 0, iclass 11, count 2 2006.196.08:14:29.38#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.196.08:14:29.38#ibcon#[25=AT05-07\r\n] 2006.196.08:14:29.38#ibcon#*before write, iclass 11, count 2 2006.196.08:14:29.38#ibcon#enter sib2, iclass 11, count 2 2006.196.08:14:29.38#ibcon#flushed, iclass 11, count 2 2006.196.08:14:29.38#ibcon#about to write, iclass 11, count 2 2006.196.08:14:29.38#ibcon#wrote, iclass 11, count 2 2006.196.08:14:29.38#ibcon#about to read 3, iclass 11, count 2 2006.196.08:14:29.41#ibcon#read 3, iclass 11, count 2 2006.196.08:14:29.41#ibcon#about to read 4, iclass 11, count 2 2006.196.08:14:29.41#ibcon#read 4, iclass 11, count 2 2006.196.08:14:29.41#ibcon#about to read 5, iclass 11, count 2 2006.196.08:14:29.41#ibcon#read 5, iclass 11, count 2 2006.196.08:14:29.41#ibcon#about to read 6, iclass 11, count 2 2006.196.08:14:29.41#ibcon#read 6, iclass 11, count 2 2006.196.08:14:29.41#ibcon#end of sib2, iclass 11, count 2 2006.196.08:14:29.41#ibcon#*after write, iclass 11, count 2 2006.196.08:14:29.41#ibcon#*before return 0, iclass 11, count 2 2006.196.08:14:29.41#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.196.08:14:29.41#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.196.08:14:29.41#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.196.08:14:29.41#ibcon#ireg 7 cls_cnt 0 2006.196.08:14:29.41#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.196.08:14:29.53#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.196.08:14:29.53#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.196.08:14:29.53#ibcon#enter wrdev, iclass 11, count 0 2006.196.08:14:29.53#ibcon#first serial, iclass 11, count 0 2006.196.08:14:29.53#ibcon#enter sib2, iclass 11, count 0 2006.196.08:14:29.53#ibcon#flushed, iclass 11, count 0 2006.196.08:14:29.53#ibcon#about to write, iclass 11, count 0 2006.196.08:14:29.53#ibcon#wrote, iclass 11, count 0 2006.196.08:14:29.53#ibcon#about to read 3, iclass 11, count 0 2006.196.08:14:29.55#ibcon#read 3, iclass 11, count 0 2006.196.08:14:29.55#ibcon#about to read 4, iclass 11, count 0 2006.196.08:14:29.55#ibcon#read 4, iclass 11, count 0 2006.196.08:14:29.55#ibcon#about to read 5, iclass 11, count 0 2006.196.08:14:29.55#ibcon#read 5, iclass 11, count 0 2006.196.08:14:29.55#ibcon#about to read 6, iclass 11, count 0 2006.196.08:14:29.55#ibcon#read 6, iclass 11, count 0 2006.196.08:14:29.55#ibcon#end of sib2, iclass 11, count 0 2006.196.08:14:29.55#ibcon#*mode == 0, iclass 11, count 0 2006.196.08:14:29.55#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.196.08:14:29.55#ibcon#[25=USB\r\n] 2006.196.08:14:29.55#ibcon#*before write, iclass 11, count 0 2006.196.08:14:29.55#ibcon#enter sib2, iclass 11, count 0 2006.196.08:14:29.55#ibcon#flushed, iclass 11, count 0 2006.196.08:14:29.55#ibcon#about to write, iclass 11, count 0 2006.196.08:14:29.55#ibcon#wrote, iclass 11, count 0 2006.196.08:14:29.55#ibcon#about to read 3, iclass 11, count 0 2006.196.08:14:29.58#ibcon#read 3, iclass 11, count 0 2006.196.08:14:29.58#ibcon#about to read 4, iclass 11, count 0 2006.196.08:14:29.58#ibcon#read 4, iclass 11, count 0 2006.196.08:14:29.58#ibcon#about to read 5, iclass 11, count 0 2006.196.08:14:29.58#ibcon#read 5, iclass 11, count 0 2006.196.08:14:29.58#ibcon#about to read 6, iclass 11, count 0 2006.196.08:14:29.58#ibcon#read 6, iclass 11, count 0 2006.196.08:14:29.58#ibcon#end of sib2, iclass 11, count 0 2006.196.08:14:29.58#ibcon#*after write, iclass 11, count 0 2006.196.08:14:29.58#ibcon#*before return 0, iclass 11, count 0 2006.196.08:14:29.58#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.196.08:14:29.58#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.196.08:14:29.58#ibcon#about to clear, iclass 11 cls_cnt 0 2006.196.08:14:29.58#ibcon#cleared, iclass 11 cls_cnt 0 2006.196.08:14:29.58$vc4f8/valo=6,772.99 2006.196.08:14:29.58#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.196.08:14:29.58#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.196.08:14:29.58#ibcon#ireg 17 cls_cnt 0 2006.196.08:14:29.58#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.196.08:14:29.58#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.196.08:14:29.58#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.196.08:14:29.58#ibcon#enter wrdev, iclass 13, count 0 2006.196.08:14:29.58#ibcon#first serial, iclass 13, count 0 2006.196.08:14:29.58#ibcon#enter sib2, iclass 13, count 0 2006.196.08:14:29.58#ibcon#flushed, iclass 13, count 0 2006.196.08:14:29.58#ibcon#about to write, iclass 13, count 0 2006.196.08:14:29.58#ibcon#wrote, iclass 13, count 0 2006.196.08:14:29.58#ibcon#about to read 3, iclass 13, count 0 2006.196.08:14:29.60#ibcon#read 3, iclass 13, count 0 2006.196.08:14:29.60#ibcon#about to read 4, iclass 13, count 0 2006.196.08:14:29.60#ibcon#read 4, iclass 13, count 0 2006.196.08:14:29.60#ibcon#about to read 5, iclass 13, count 0 2006.196.08:14:29.60#ibcon#read 5, iclass 13, count 0 2006.196.08:14:29.60#ibcon#about to read 6, iclass 13, count 0 2006.196.08:14:29.60#ibcon#read 6, iclass 13, count 0 2006.196.08:14:29.60#ibcon#end of sib2, iclass 13, count 0 2006.196.08:14:29.60#ibcon#*mode == 0, iclass 13, count 0 2006.196.08:14:29.60#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.196.08:14:29.60#ibcon#[26=FRQ=06,772.99\r\n] 2006.196.08:14:29.60#ibcon#*before write, iclass 13, count 0 2006.196.08:14:29.60#ibcon#enter sib2, iclass 13, count 0 2006.196.08:14:29.60#ibcon#flushed, iclass 13, count 0 2006.196.08:14:29.60#ibcon#about to write, iclass 13, count 0 2006.196.08:14:29.60#ibcon#wrote, iclass 13, count 0 2006.196.08:14:29.60#ibcon#about to read 3, iclass 13, count 0 2006.196.08:14:29.64#ibcon#read 3, iclass 13, count 0 2006.196.08:14:29.64#ibcon#about to read 4, iclass 13, count 0 2006.196.08:14:29.64#ibcon#read 4, iclass 13, count 0 2006.196.08:14:29.64#ibcon#about to read 5, iclass 13, count 0 2006.196.08:14:29.64#ibcon#read 5, iclass 13, count 0 2006.196.08:14:29.64#ibcon#about to read 6, iclass 13, count 0 2006.196.08:14:29.64#ibcon#read 6, iclass 13, count 0 2006.196.08:14:29.64#ibcon#end of sib2, iclass 13, count 0 2006.196.08:14:29.64#ibcon#*after write, iclass 13, count 0 2006.196.08:14:29.64#ibcon#*before return 0, iclass 13, count 0 2006.196.08:14:29.64#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.196.08:14:29.64#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.196.08:14:29.64#ibcon#about to clear, iclass 13 cls_cnt 0 2006.196.08:14:29.64#ibcon#cleared, iclass 13 cls_cnt 0 2006.196.08:14:29.64$vc4f8/va=6,6 2006.196.08:14:29.64#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.196.08:14:29.64#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.196.08:14:29.64#ibcon#ireg 11 cls_cnt 2 2006.196.08:14:29.64#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.196.08:14:29.70#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.196.08:14:29.70#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.196.08:14:29.70#ibcon#enter wrdev, iclass 15, count 2 2006.196.08:14:29.70#ibcon#first serial, iclass 15, count 2 2006.196.08:14:29.70#ibcon#enter sib2, iclass 15, count 2 2006.196.08:14:29.70#ibcon#flushed, iclass 15, count 2 2006.196.08:14:29.70#ibcon#about to write, iclass 15, count 2 2006.196.08:14:29.70#ibcon#wrote, iclass 15, count 2 2006.196.08:14:29.70#ibcon#about to read 3, iclass 15, count 2 2006.196.08:14:29.72#ibcon#read 3, iclass 15, count 2 2006.196.08:14:29.72#ibcon#about to read 4, iclass 15, count 2 2006.196.08:14:29.72#ibcon#read 4, iclass 15, count 2 2006.196.08:14:29.72#ibcon#about to read 5, iclass 15, count 2 2006.196.08:14:29.72#ibcon#read 5, iclass 15, count 2 2006.196.08:14:29.72#ibcon#about to read 6, iclass 15, count 2 2006.196.08:14:29.72#ibcon#read 6, iclass 15, count 2 2006.196.08:14:29.72#ibcon#end of sib2, iclass 15, count 2 2006.196.08:14:29.72#ibcon#*mode == 0, iclass 15, count 2 2006.196.08:14:29.72#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.196.08:14:29.72#ibcon#[25=AT06-06\r\n] 2006.196.08:14:29.72#ibcon#*before write, iclass 15, count 2 2006.196.08:14:29.72#ibcon#enter sib2, iclass 15, count 2 2006.196.08:14:29.72#ibcon#flushed, iclass 15, count 2 2006.196.08:14:29.72#ibcon#about to write, iclass 15, count 2 2006.196.08:14:29.72#ibcon#wrote, iclass 15, count 2 2006.196.08:14:29.72#ibcon#about to read 3, iclass 15, count 2 2006.196.08:14:29.75#ibcon#read 3, iclass 15, count 2 2006.196.08:14:29.75#ibcon#about to read 4, iclass 15, count 2 2006.196.08:14:29.75#ibcon#read 4, iclass 15, count 2 2006.196.08:14:29.75#ibcon#about to read 5, iclass 15, count 2 2006.196.08:14:29.75#ibcon#read 5, iclass 15, count 2 2006.196.08:14:29.75#ibcon#about to read 6, iclass 15, count 2 2006.196.08:14:29.75#ibcon#read 6, iclass 15, count 2 2006.196.08:14:29.75#ibcon#end of sib2, iclass 15, count 2 2006.196.08:14:29.75#ibcon#*after write, iclass 15, count 2 2006.196.08:14:29.75#ibcon#*before return 0, iclass 15, count 2 2006.196.08:14:29.75#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.196.08:14:29.75#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.196.08:14:29.75#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.196.08:14:29.75#ibcon#ireg 7 cls_cnt 0 2006.196.08:14:29.75#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.196.08:14:29.87#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.196.08:14:29.87#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.196.08:14:29.87#ibcon#enter wrdev, iclass 15, count 0 2006.196.08:14:29.87#ibcon#first serial, iclass 15, count 0 2006.196.08:14:29.87#ibcon#enter sib2, iclass 15, count 0 2006.196.08:14:29.87#ibcon#flushed, iclass 15, count 0 2006.196.08:14:29.87#ibcon#about to write, iclass 15, count 0 2006.196.08:14:29.87#ibcon#wrote, iclass 15, count 0 2006.196.08:14:29.87#ibcon#about to read 3, iclass 15, count 0 2006.196.08:14:29.89#ibcon#read 3, iclass 15, count 0 2006.196.08:14:29.89#ibcon#about to read 4, iclass 15, count 0 2006.196.08:14:29.89#ibcon#read 4, iclass 15, count 0 2006.196.08:14:29.89#ibcon#about to read 5, iclass 15, count 0 2006.196.08:14:29.89#ibcon#read 5, iclass 15, count 0 2006.196.08:14:29.89#ibcon#about to read 6, iclass 15, count 0 2006.196.08:14:29.89#ibcon#read 6, iclass 15, count 0 2006.196.08:14:29.89#ibcon#end of sib2, iclass 15, count 0 2006.196.08:14:29.89#ibcon#*mode == 0, iclass 15, count 0 2006.196.08:14:29.89#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.196.08:14:29.89#ibcon#[25=USB\r\n] 2006.196.08:14:29.89#ibcon#*before write, iclass 15, count 0 2006.196.08:14:29.89#ibcon#enter sib2, iclass 15, count 0 2006.196.08:14:29.89#ibcon#flushed, iclass 15, count 0 2006.196.08:14:29.89#ibcon#about to write, iclass 15, count 0 2006.196.08:14:29.89#ibcon#wrote, iclass 15, count 0 2006.196.08:14:29.89#ibcon#about to read 3, iclass 15, count 0 2006.196.08:14:29.92#ibcon#read 3, iclass 15, count 0 2006.196.08:14:29.92#ibcon#about to read 4, iclass 15, count 0 2006.196.08:14:29.92#ibcon#read 4, iclass 15, count 0 2006.196.08:14:29.92#ibcon#about to read 5, iclass 15, count 0 2006.196.08:14:29.92#ibcon#read 5, iclass 15, count 0 2006.196.08:14:29.92#ibcon#about to read 6, iclass 15, count 0 2006.196.08:14:29.92#ibcon#read 6, iclass 15, count 0 2006.196.08:14:29.92#ibcon#end of sib2, iclass 15, count 0 2006.196.08:14:29.92#ibcon#*after write, iclass 15, count 0 2006.196.08:14:29.92#ibcon#*before return 0, iclass 15, count 0 2006.196.08:14:29.92#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.196.08:14:29.92#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.196.08:14:29.92#ibcon#about to clear, iclass 15 cls_cnt 0 2006.196.08:14:29.92#ibcon#cleared, iclass 15 cls_cnt 0 2006.196.08:14:29.92$vc4f8/valo=7,832.99 2006.196.08:14:29.92#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.196.08:14:29.92#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.196.08:14:29.92#ibcon#ireg 17 cls_cnt 0 2006.196.08:14:29.92#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.196.08:14:29.92#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.196.08:14:29.92#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.196.08:14:29.92#ibcon#enter wrdev, iclass 17, count 0 2006.196.08:14:29.92#ibcon#first serial, iclass 17, count 0 2006.196.08:14:29.92#ibcon#enter sib2, iclass 17, count 0 2006.196.08:14:29.92#ibcon#flushed, iclass 17, count 0 2006.196.08:14:29.92#ibcon#about to write, iclass 17, count 0 2006.196.08:14:29.92#ibcon#wrote, iclass 17, count 0 2006.196.08:14:29.92#ibcon#about to read 3, iclass 17, count 0 2006.196.08:14:29.94#ibcon#read 3, iclass 17, count 0 2006.196.08:14:29.94#ibcon#about to read 4, iclass 17, count 0 2006.196.08:14:29.94#ibcon#read 4, iclass 17, count 0 2006.196.08:14:29.94#ibcon#about to read 5, iclass 17, count 0 2006.196.08:14:29.94#ibcon#read 5, iclass 17, count 0 2006.196.08:14:29.94#ibcon#about to read 6, iclass 17, count 0 2006.196.08:14:29.94#ibcon#read 6, iclass 17, count 0 2006.196.08:14:29.94#ibcon#end of sib2, iclass 17, count 0 2006.196.08:14:29.94#ibcon#*mode == 0, iclass 17, count 0 2006.196.08:14:29.94#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.196.08:14:29.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.196.08:14:29.94#ibcon#*before write, iclass 17, count 0 2006.196.08:14:29.94#ibcon#enter sib2, iclass 17, count 0 2006.196.08:14:29.94#ibcon#flushed, iclass 17, count 0 2006.196.08:14:29.94#ibcon#about to write, iclass 17, count 0 2006.196.08:14:29.94#ibcon#wrote, iclass 17, count 0 2006.196.08:14:29.94#ibcon#about to read 3, iclass 17, count 0 2006.196.08:14:29.98#ibcon#read 3, iclass 17, count 0 2006.196.08:14:29.98#ibcon#about to read 4, iclass 17, count 0 2006.196.08:14:29.98#ibcon#read 4, iclass 17, count 0 2006.196.08:14:29.98#ibcon#about to read 5, iclass 17, count 0 2006.196.08:14:29.98#ibcon#read 5, iclass 17, count 0 2006.196.08:14:29.98#ibcon#about to read 6, iclass 17, count 0 2006.196.08:14:29.98#ibcon#read 6, iclass 17, count 0 2006.196.08:14:29.98#ibcon#end of sib2, iclass 17, count 0 2006.196.08:14:29.98#ibcon#*after write, iclass 17, count 0 2006.196.08:14:29.98#ibcon#*before return 0, iclass 17, count 0 2006.196.08:14:29.98#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.196.08:14:29.98#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.196.08:14:29.98#ibcon#about to clear, iclass 17 cls_cnt 0 2006.196.08:14:29.98#ibcon#cleared, iclass 17 cls_cnt 0 2006.196.08:14:29.98$vc4f8/va=7,6 2006.196.08:14:29.98#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.196.08:14:29.98#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.196.08:14:29.98#ibcon#ireg 11 cls_cnt 2 2006.196.08:14:29.98#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.196.08:14:30.04#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.196.08:14:30.04#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.196.08:14:30.04#ibcon#enter wrdev, iclass 19, count 2 2006.196.08:14:30.04#ibcon#first serial, iclass 19, count 2 2006.196.08:14:30.04#ibcon#enter sib2, iclass 19, count 2 2006.196.08:14:30.04#ibcon#flushed, iclass 19, count 2 2006.196.08:14:30.04#ibcon#about to write, iclass 19, count 2 2006.196.08:14:30.04#ibcon#wrote, iclass 19, count 2 2006.196.08:14:30.04#ibcon#about to read 3, iclass 19, count 2 2006.196.08:14:30.06#ibcon#read 3, iclass 19, count 2 2006.196.08:14:30.06#ibcon#about to read 4, iclass 19, count 2 2006.196.08:14:30.06#ibcon#read 4, iclass 19, count 2 2006.196.08:14:30.06#ibcon#about to read 5, iclass 19, count 2 2006.196.08:14:30.06#ibcon#read 5, iclass 19, count 2 2006.196.08:14:30.06#ibcon#about to read 6, iclass 19, count 2 2006.196.08:14:30.06#ibcon#read 6, iclass 19, count 2 2006.196.08:14:30.06#ibcon#end of sib2, iclass 19, count 2 2006.196.08:14:30.06#ibcon#*mode == 0, iclass 19, count 2 2006.196.08:14:30.06#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.196.08:14:30.06#ibcon#[25=AT07-06\r\n] 2006.196.08:14:30.06#ibcon#*before write, iclass 19, count 2 2006.196.08:14:30.06#ibcon#enter sib2, iclass 19, count 2 2006.196.08:14:30.06#ibcon#flushed, iclass 19, count 2 2006.196.08:14:30.06#ibcon#about to write, iclass 19, count 2 2006.196.08:14:30.06#ibcon#wrote, iclass 19, count 2 2006.196.08:14:30.06#ibcon#about to read 3, iclass 19, count 2 2006.196.08:14:30.09#ibcon#read 3, iclass 19, count 2 2006.196.08:14:30.09#ibcon#about to read 4, iclass 19, count 2 2006.196.08:14:30.09#ibcon#read 4, iclass 19, count 2 2006.196.08:14:30.09#ibcon#about to read 5, iclass 19, count 2 2006.196.08:14:30.09#ibcon#read 5, iclass 19, count 2 2006.196.08:14:30.09#ibcon#about to read 6, iclass 19, count 2 2006.196.08:14:30.09#ibcon#read 6, iclass 19, count 2 2006.196.08:14:30.09#ibcon#end of sib2, iclass 19, count 2 2006.196.08:14:30.09#ibcon#*after write, iclass 19, count 2 2006.196.08:14:30.09#ibcon#*before return 0, iclass 19, count 2 2006.196.08:14:30.09#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.196.08:14:30.09#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.196.08:14:30.09#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.196.08:14:30.09#ibcon#ireg 7 cls_cnt 0 2006.196.08:14:30.09#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.196.08:14:30.21#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.196.08:14:30.21#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.196.08:14:30.21#ibcon#enter wrdev, iclass 19, count 0 2006.196.08:14:30.21#ibcon#first serial, iclass 19, count 0 2006.196.08:14:30.21#ibcon#enter sib2, iclass 19, count 0 2006.196.08:14:30.21#ibcon#flushed, iclass 19, count 0 2006.196.08:14:30.21#ibcon#about to write, iclass 19, count 0 2006.196.08:14:30.21#ibcon#wrote, iclass 19, count 0 2006.196.08:14:30.21#ibcon#about to read 3, iclass 19, count 0 2006.196.08:14:30.23#ibcon#read 3, iclass 19, count 0 2006.196.08:14:30.23#ibcon#about to read 4, iclass 19, count 0 2006.196.08:14:30.23#ibcon#read 4, iclass 19, count 0 2006.196.08:14:30.23#ibcon#about to read 5, iclass 19, count 0 2006.196.08:14:30.23#ibcon#read 5, iclass 19, count 0 2006.196.08:14:30.23#ibcon#about to read 6, iclass 19, count 0 2006.196.08:14:30.23#ibcon#read 6, iclass 19, count 0 2006.196.08:14:30.23#ibcon#end of sib2, iclass 19, count 0 2006.196.08:14:30.23#ibcon#*mode == 0, iclass 19, count 0 2006.196.08:14:30.23#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.196.08:14:30.23#ibcon#[25=USB\r\n] 2006.196.08:14:30.23#ibcon#*before write, iclass 19, count 0 2006.196.08:14:30.23#ibcon#enter sib2, iclass 19, count 0 2006.196.08:14:30.23#ibcon#flushed, iclass 19, count 0 2006.196.08:14:30.23#ibcon#about to write, iclass 19, count 0 2006.196.08:14:30.23#ibcon#wrote, iclass 19, count 0 2006.196.08:14:30.23#ibcon#about to read 3, iclass 19, count 0 2006.196.08:14:30.26#ibcon#read 3, iclass 19, count 0 2006.196.08:14:30.26#ibcon#about to read 4, iclass 19, count 0 2006.196.08:14:30.26#ibcon#read 4, iclass 19, count 0 2006.196.08:14:30.26#ibcon#about to read 5, iclass 19, count 0 2006.196.08:14:30.26#ibcon#read 5, iclass 19, count 0 2006.196.08:14:30.26#ibcon#about to read 6, iclass 19, count 0 2006.196.08:14:30.26#ibcon#read 6, iclass 19, count 0 2006.196.08:14:30.26#ibcon#end of sib2, iclass 19, count 0 2006.196.08:14:30.26#ibcon#*after write, iclass 19, count 0 2006.196.08:14:30.26#ibcon#*before return 0, iclass 19, count 0 2006.196.08:14:30.26#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.196.08:14:30.26#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.196.08:14:30.26#ibcon#about to clear, iclass 19 cls_cnt 0 2006.196.08:14:30.26#ibcon#cleared, iclass 19 cls_cnt 0 2006.196.08:14:30.26$vc4f8/valo=8,852.99 2006.196.08:14:30.26#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.196.08:14:30.26#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.196.08:14:30.26#ibcon#ireg 17 cls_cnt 0 2006.196.08:14:30.26#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.196.08:14:30.26#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.196.08:14:30.26#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.196.08:14:30.26#ibcon#enter wrdev, iclass 21, count 0 2006.196.08:14:30.26#ibcon#first serial, iclass 21, count 0 2006.196.08:14:30.26#ibcon#enter sib2, iclass 21, count 0 2006.196.08:14:30.26#ibcon#flushed, iclass 21, count 0 2006.196.08:14:30.26#ibcon#about to write, iclass 21, count 0 2006.196.08:14:30.26#ibcon#wrote, iclass 21, count 0 2006.196.08:14:30.26#ibcon#about to read 3, iclass 21, count 0 2006.196.08:14:30.28#ibcon#read 3, iclass 21, count 0 2006.196.08:14:30.28#ibcon#about to read 4, iclass 21, count 0 2006.196.08:14:30.28#ibcon#read 4, iclass 21, count 0 2006.196.08:14:30.28#ibcon#about to read 5, iclass 21, count 0 2006.196.08:14:30.28#ibcon#read 5, iclass 21, count 0 2006.196.08:14:30.28#ibcon#about to read 6, iclass 21, count 0 2006.196.08:14:30.28#ibcon#read 6, iclass 21, count 0 2006.196.08:14:30.28#ibcon#end of sib2, iclass 21, count 0 2006.196.08:14:30.28#ibcon#*mode == 0, iclass 21, count 0 2006.196.08:14:30.28#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.196.08:14:30.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.196.08:14:30.28#ibcon#*before write, iclass 21, count 0 2006.196.08:14:30.28#ibcon#enter sib2, iclass 21, count 0 2006.196.08:14:30.28#ibcon#flushed, iclass 21, count 0 2006.196.08:14:30.28#ibcon#about to write, iclass 21, count 0 2006.196.08:14:30.28#ibcon#wrote, iclass 21, count 0 2006.196.08:14:30.28#ibcon#about to read 3, iclass 21, count 0 2006.196.08:14:30.32#ibcon#read 3, iclass 21, count 0 2006.196.08:14:30.32#ibcon#about to read 4, iclass 21, count 0 2006.196.08:14:30.32#ibcon#read 4, iclass 21, count 0 2006.196.08:14:30.32#ibcon#about to read 5, iclass 21, count 0 2006.196.08:14:30.32#ibcon#read 5, iclass 21, count 0 2006.196.08:14:30.32#ibcon#about to read 6, iclass 21, count 0 2006.196.08:14:30.32#ibcon#read 6, iclass 21, count 0 2006.196.08:14:30.32#ibcon#end of sib2, iclass 21, count 0 2006.196.08:14:30.32#ibcon#*after write, iclass 21, count 0 2006.196.08:14:30.32#ibcon#*before return 0, iclass 21, count 0 2006.196.08:14:30.32#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.196.08:14:30.32#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.196.08:14:30.32#ibcon#about to clear, iclass 21 cls_cnt 0 2006.196.08:14:30.32#ibcon#cleared, iclass 21 cls_cnt 0 2006.196.08:14:30.32$vc4f8/va=8,7 2006.196.08:14:30.32#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.196.08:14:30.32#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.196.08:14:30.32#ibcon#ireg 11 cls_cnt 2 2006.196.08:14:30.32#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.196.08:14:30.38#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.196.08:14:30.38#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.196.08:14:30.38#ibcon#enter wrdev, iclass 23, count 2 2006.196.08:14:30.38#ibcon#first serial, iclass 23, count 2 2006.196.08:14:30.38#ibcon#enter sib2, iclass 23, count 2 2006.196.08:14:30.38#ibcon#flushed, iclass 23, count 2 2006.196.08:14:30.38#ibcon#about to write, iclass 23, count 2 2006.196.08:14:30.38#ibcon#wrote, iclass 23, count 2 2006.196.08:14:30.38#ibcon#about to read 3, iclass 23, count 2 2006.196.08:14:30.40#ibcon#read 3, iclass 23, count 2 2006.196.08:14:30.40#ibcon#about to read 4, iclass 23, count 2 2006.196.08:14:30.40#ibcon#read 4, iclass 23, count 2 2006.196.08:14:30.40#ibcon#about to read 5, iclass 23, count 2 2006.196.08:14:30.40#ibcon#read 5, iclass 23, count 2 2006.196.08:14:30.40#ibcon#about to read 6, iclass 23, count 2 2006.196.08:14:30.40#ibcon#read 6, iclass 23, count 2 2006.196.08:14:30.40#ibcon#end of sib2, iclass 23, count 2 2006.196.08:14:30.40#ibcon#*mode == 0, iclass 23, count 2 2006.196.08:14:30.40#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.196.08:14:30.40#ibcon#[25=AT08-07\r\n] 2006.196.08:14:30.40#ibcon#*before write, iclass 23, count 2 2006.196.08:14:30.40#ibcon#enter sib2, iclass 23, count 2 2006.196.08:14:30.40#ibcon#flushed, iclass 23, count 2 2006.196.08:14:30.40#ibcon#about to write, iclass 23, count 2 2006.196.08:14:30.40#ibcon#wrote, iclass 23, count 2 2006.196.08:14:30.40#ibcon#about to read 3, iclass 23, count 2 2006.196.08:14:30.43#ibcon#read 3, iclass 23, count 2 2006.196.08:14:30.43#ibcon#about to read 4, iclass 23, count 2 2006.196.08:14:30.43#ibcon#read 4, iclass 23, count 2 2006.196.08:14:30.43#ibcon#about to read 5, iclass 23, count 2 2006.196.08:14:30.43#ibcon#read 5, iclass 23, count 2 2006.196.08:14:30.43#ibcon#about to read 6, iclass 23, count 2 2006.196.08:14:30.43#ibcon#read 6, iclass 23, count 2 2006.196.08:14:30.43#ibcon#end of sib2, iclass 23, count 2 2006.196.08:14:30.43#ibcon#*after write, iclass 23, count 2 2006.196.08:14:30.43#ibcon#*before return 0, iclass 23, count 2 2006.196.08:14:30.43#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.196.08:14:30.43#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.196.08:14:30.43#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.196.08:14:30.43#ibcon#ireg 7 cls_cnt 0 2006.196.08:14:30.43#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.196.08:14:30.55#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.196.08:14:30.55#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.196.08:14:30.55#ibcon#enter wrdev, iclass 23, count 0 2006.196.08:14:30.55#ibcon#first serial, iclass 23, count 0 2006.196.08:14:30.55#ibcon#enter sib2, iclass 23, count 0 2006.196.08:14:30.55#ibcon#flushed, iclass 23, count 0 2006.196.08:14:30.55#ibcon#about to write, iclass 23, count 0 2006.196.08:14:30.55#ibcon#wrote, iclass 23, count 0 2006.196.08:14:30.55#ibcon#about to read 3, iclass 23, count 0 2006.196.08:14:30.57#ibcon#read 3, iclass 23, count 0 2006.196.08:14:30.57#ibcon#about to read 4, iclass 23, count 0 2006.196.08:14:30.57#ibcon#read 4, iclass 23, count 0 2006.196.08:14:30.57#ibcon#about to read 5, iclass 23, count 0 2006.196.08:14:30.57#ibcon#read 5, iclass 23, count 0 2006.196.08:14:30.57#ibcon#about to read 6, iclass 23, count 0 2006.196.08:14:30.57#ibcon#read 6, iclass 23, count 0 2006.196.08:14:30.57#ibcon#end of sib2, iclass 23, count 0 2006.196.08:14:30.57#ibcon#*mode == 0, iclass 23, count 0 2006.196.08:14:30.57#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.196.08:14:30.57#ibcon#[25=USB\r\n] 2006.196.08:14:30.57#ibcon#*before write, iclass 23, count 0 2006.196.08:14:30.57#ibcon#enter sib2, iclass 23, count 0 2006.196.08:14:30.57#ibcon#flushed, iclass 23, count 0 2006.196.08:14:30.57#ibcon#about to write, iclass 23, count 0 2006.196.08:14:30.57#ibcon#wrote, iclass 23, count 0 2006.196.08:14:30.57#ibcon#about to read 3, iclass 23, count 0 2006.196.08:14:30.60#ibcon#read 3, iclass 23, count 0 2006.196.08:14:30.60#ibcon#about to read 4, iclass 23, count 0 2006.196.08:14:30.60#ibcon#read 4, iclass 23, count 0 2006.196.08:14:30.60#ibcon#about to read 5, iclass 23, count 0 2006.196.08:14:30.60#ibcon#read 5, iclass 23, count 0 2006.196.08:14:30.60#ibcon#about to read 6, iclass 23, count 0 2006.196.08:14:30.60#ibcon#read 6, iclass 23, count 0 2006.196.08:14:30.60#ibcon#end of sib2, iclass 23, count 0 2006.196.08:14:30.60#ibcon#*after write, iclass 23, count 0 2006.196.08:14:30.60#ibcon#*before return 0, iclass 23, count 0 2006.196.08:14:30.60#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.196.08:14:30.60#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.196.08:14:30.60#ibcon#about to clear, iclass 23 cls_cnt 0 2006.196.08:14:30.60#ibcon#cleared, iclass 23 cls_cnt 0 2006.196.08:14:30.60$vc4f8/vblo=1,632.99 2006.196.08:14:30.60#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.196.08:14:30.60#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.196.08:14:30.60#ibcon#ireg 17 cls_cnt 0 2006.196.08:14:30.60#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.196.08:14:30.60#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.196.08:14:30.60#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.196.08:14:30.60#ibcon#enter wrdev, iclass 25, count 0 2006.196.08:14:30.60#ibcon#first serial, iclass 25, count 0 2006.196.08:14:30.60#ibcon#enter sib2, iclass 25, count 0 2006.196.08:14:30.60#ibcon#flushed, iclass 25, count 0 2006.196.08:14:30.60#ibcon#about to write, iclass 25, count 0 2006.196.08:14:30.60#ibcon#wrote, iclass 25, count 0 2006.196.08:14:30.60#ibcon#about to read 3, iclass 25, count 0 2006.196.08:14:30.62#ibcon#read 3, iclass 25, count 0 2006.196.08:14:30.62#ibcon#about to read 4, iclass 25, count 0 2006.196.08:14:30.62#ibcon#read 4, iclass 25, count 0 2006.196.08:14:30.62#ibcon#about to read 5, iclass 25, count 0 2006.196.08:14:30.62#ibcon#read 5, iclass 25, count 0 2006.196.08:14:30.62#ibcon#about to read 6, iclass 25, count 0 2006.196.08:14:30.62#ibcon#read 6, iclass 25, count 0 2006.196.08:14:30.62#ibcon#end of sib2, iclass 25, count 0 2006.196.08:14:30.62#ibcon#*mode == 0, iclass 25, count 0 2006.196.08:14:30.62#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.196.08:14:30.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.196.08:14:30.62#ibcon#*before write, iclass 25, count 0 2006.196.08:14:30.62#ibcon#enter sib2, iclass 25, count 0 2006.196.08:14:30.62#ibcon#flushed, iclass 25, count 0 2006.196.08:14:30.62#ibcon#about to write, iclass 25, count 0 2006.196.08:14:30.62#ibcon#wrote, iclass 25, count 0 2006.196.08:14:30.62#ibcon#about to read 3, iclass 25, count 0 2006.196.08:14:30.66#ibcon#read 3, iclass 25, count 0 2006.196.08:14:30.66#ibcon#about to read 4, iclass 25, count 0 2006.196.08:14:30.66#ibcon#read 4, iclass 25, count 0 2006.196.08:14:30.66#ibcon#about to read 5, iclass 25, count 0 2006.196.08:14:30.66#ibcon#read 5, iclass 25, count 0 2006.196.08:14:30.66#ibcon#about to read 6, iclass 25, count 0 2006.196.08:14:30.66#ibcon#read 6, iclass 25, count 0 2006.196.08:14:30.66#ibcon#end of sib2, iclass 25, count 0 2006.196.08:14:30.66#ibcon#*after write, iclass 25, count 0 2006.196.08:14:30.66#ibcon#*before return 0, iclass 25, count 0 2006.196.08:14:30.66#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.196.08:14:30.66#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.196.08:14:30.66#ibcon#about to clear, iclass 25 cls_cnt 0 2006.196.08:14:30.66#ibcon#cleared, iclass 25 cls_cnt 0 2006.196.08:14:30.66$vc4f8/vb=1,4 2006.196.08:14:30.66#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.196.08:14:30.66#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.196.08:14:30.66#ibcon#ireg 11 cls_cnt 2 2006.196.08:14:30.66#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.196.08:14:30.66#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.196.08:14:30.66#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.196.08:14:30.66#ibcon#enter wrdev, iclass 27, count 2 2006.196.08:14:30.66#ibcon#first serial, iclass 27, count 2 2006.196.08:14:30.66#ibcon#enter sib2, iclass 27, count 2 2006.196.08:14:30.66#ibcon#flushed, iclass 27, count 2 2006.196.08:14:30.66#ibcon#about to write, iclass 27, count 2 2006.196.08:14:30.66#ibcon#wrote, iclass 27, count 2 2006.196.08:14:30.66#ibcon#about to read 3, iclass 27, count 2 2006.196.08:14:30.68#ibcon#read 3, iclass 27, count 2 2006.196.08:14:30.68#ibcon#about to read 4, iclass 27, count 2 2006.196.08:14:30.68#ibcon#read 4, iclass 27, count 2 2006.196.08:14:30.68#ibcon#about to read 5, iclass 27, count 2 2006.196.08:14:30.68#ibcon#read 5, iclass 27, count 2 2006.196.08:14:30.68#ibcon#about to read 6, iclass 27, count 2 2006.196.08:14:30.68#ibcon#read 6, iclass 27, count 2 2006.196.08:14:30.68#ibcon#end of sib2, iclass 27, count 2 2006.196.08:14:30.68#ibcon#*mode == 0, iclass 27, count 2 2006.196.08:14:30.68#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.196.08:14:30.68#ibcon#[27=AT01-04\r\n] 2006.196.08:14:30.68#ibcon#*before write, iclass 27, count 2 2006.196.08:14:30.68#ibcon#enter sib2, iclass 27, count 2 2006.196.08:14:30.68#ibcon#flushed, iclass 27, count 2 2006.196.08:14:30.68#ibcon#about to write, iclass 27, count 2 2006.196.08:14:30.68#ibcon#wrote, iclass 27, count 2 2006.196.08:14:30.68#ibcon#about to read 3, iclass 27, count 2 2006.196.08:14:30.71#ibcon#read 3, iclass 27, count 2 2006.196.08:14:30.71#ibcon#about to read 4, iclass 27, count 2 2006.196.08:14:30.71#ibcon#read 4, iclass 27, count 2 2006.196.08:14:30.71#ibcon#about to read 5, iclass 27, count 2 2006.196.08:14:30.71#ibcon#read 5, iclass 27, count 2 2006.196.08:14:30.71#ibcon#about to read 6, iclass 27, count 2 2006.196.08:14:30.71#ibcon#read 6, iclass 27, count 2 2006.196.08:14:30.71#ibcon#end of sib2, iclass 27, count 2 2006.196.08:14:30.71#ibcon#*after write, iclass 27, count 2 2006.196.08:14:30.71#ibcon#*before return 0, iclass 27, count 2 2006.196.08:14:30.71#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.196.08:14:30.71#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.196.08:14:30.71#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.196.08:14:30.71#ibcon#ireg 7 cls_cnt 0 2006.196.08:14:30.71#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.196.08:14:30.83#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.196.08:14:30.83#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.196.08:14:30.83#ibcon#enter wrdev, iclass 27, count 0 2006.196.08:14:30.83#ibcon#first serial, iclass 27, count 0 2006.196.08:14:30.83#ibcon#enter sib2, iclass 27, count 0 2006.196.08:14:30.83#ibcon#flushed, iclass 27, count 0 2006.196.08:14:30.83#ibcon#about to write, iclass 27, count 0 2006.196.08:14:30.83#ibcon#wrote, iclass 27, count 0 2006.196.08:14:30.83#ibcon#about to read 3, iclass 27, count 0 2006.196.08:14:30.85#ibcon#read 3, iclass 27, count 0 2006.196.08:14:30.85#ibcon#about to read 4, iclass 27, count 0 2006.196.08:14:30.85#ibcon#read 4, iclass 27, count 0 2006.196.08:14:30.85#ibcon#about to read 5, iclass 27, count 0 2006.196.08:14:30.85#ibcon#read 5, iclass 27, count 0 2006.196.08:14:30.85#ibcon#about to read 6, iclass 27, count 0 2006.196.08:14:30.85#ibcon#read 6, iclass 27, count 0 2006.196.08:14:30.85#ibcon#end of sib2, iclass 27, count 0 2006.196.08:14:30.85#ibcon#*mode == 0, iclass 27, count 0 2006.196.08:14:30.85#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.196.08:14:30.85#ibcon#[27=USB\r\n] 2006.196.08:14:30.85#ibcon#*before write, iclass 27, count 0 2006.196.08:14:30.85#ibcon#enter sib2, iclass 27, count 0 2006.196.08:14:30.85#ibcon#flushed, iclass 27, count 0 2006.196.08:14:30.85#ibcon#about to write, iclass 27, count 0 2006.196.08:14:30.85#ibcon#wrote, iclass 27, count 0 2006.196.08:14:30.85#ibcon#about to read 3, iclass 27, count 0 2006.196.08:14:30.88#ibcon#read 3, iclass 27, count 0 2006.196.08:14:30.88#ibcon#about to read 4, iclass 27, count 0 2006.196.08:14:30.88#ibcon#read 4, iclass 27, count 0 2006.196.08:14:30.88#ibcon#about to read 5, iclass 27, count 0 2006.196.08:14:30.88#ibcon#read 5, iclass 27, count 0 2006.196.08:14:30.88#ibcon#about to read 6, iclass 27, count 0 2006.196.08:14:30.88#ibcon#read 6, iclass 27, count 0 2006.196.08:14:30.88#ibcon#end of sib2, iclass 27, count 0 2006.196.08:14:30.88#ibcon#*after write, iclass 27, count 0 2006.196.08:14:30.88#ibcon#*before return 0, iclass 27, count 0 2006.196.08:14:30.88#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.196.08:14:30.88#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.196.08:14:30.88#ibcon#about to clear, iclass 27 cls_cnt 0 2006.196.08:14:30.88#ibcon#cleared, iclass 27 cls_cnt 0 2006.196.08:14:30.88$vc4f8/vblo=2,640.99 2006.196.08:14:30.88#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.196.08:14:30.88#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.196.08:14:30.88#ibcon#ireg 17 cls_cnt 0 2006.196.08:14:30.88#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.196.08:14:30.88#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.196.08:14:30.88#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.196.08:14:30.88#ibcon#enter wrdev, iclass 29, count 0 2006.196.08:14:30.88#ibcon#first serial, iclass 29, count 0 2006.196.08:14:30.88#ibcon#enter sib2, iclass 29, count 0 2006.196.08:14:30.88#ibcon#flushed, iclass 29, count 0 2006.196.08:14:30.88#ibcon#about to write, iclass 29, count 0 2006.196.08:14:30.88#ibcon#wrote, iclass 29, count 0 2006.196.08:14:30.88#ibcon#about to read 3, iclass 29, count 0 2006.196.08:14:30.90#ibcon#read 3, iclass 29, count 0 2006.196.08:14:30.90#ibcon#about to read 4, iclass 29, count 0 2006.196.08:14:30.90#ibcon#read 4, iclass 29, count 0 2006.196.08:14:30.90#ibcon#about to read 5, iclass 29, count 0 2006.196.08:14:30.90#ibcon#read 5, iclass 29, count 0 2006.196.08:14:30.90#ibcon#about to read 6, iclass 29, count 0 2006.196.08:14:30.90#ibcon#read 6, iclass 29, count 0 2006.196.08:14:30.90#ibcon#end of sib2, iclass 29, count 0 2006.196.08:14:30.90#ibcon#*mode == 0, iclass 29, count 0 2006.196.08:14:30.90#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.196.08:14:30.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.196.08:14:30.90#ibcon#*before write, iclass 29, count 0 2006.196.08:14:30.90#ibcon#enter sib2, iclass 29, count 0 2006.196.08:14:30.90#ibcon#flushed, iclass 29, count 0 2006.196.08:14:30.90#ibcon#about to write, iclass 29, count 0 2006.196.08:14:30.90#ibcon#wrote, iclass 29, count 0 2006.196.08:14:30.90#ibcon#about to read 3, iclass 29, count 0 2006.196.08:14:30.94#ibcon#read 3, iclass 29, count 0 2006.196.08:14:30.94#ibcon#about to read 4, iclass 29, count 0 2006.196.08:14:30.94#ibcon#read 4, iclass 29, count 0 2006.196.08:14:30.94#ibcon#about to read 5, iclass 29, count 0 2006.196.08:14:30.94#ibcon#read 5, iclass 29, count 0 2006.196.08:14:30.94#ibcon#about to read 6, iclass 29, count 0 2006.196.08:14:30.94#ibcon#read 6, iclass 29, count 0 2006.196.08:14:30.94#ibcon#end of sib2, iclass 29, count 0 2006.196.08:14:30.94#ibcon#*after write, iclass 29, count 0 2006.196.08:14:30.94#ibcon#*before return 0, iclass 29, count 0 2006.196.08:14:30.94#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.196.08:14:30.94#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.196.08:14:30.94#ibcon#about to clear, iclass 29 cls_cnt 0 2006.196.08:14:30.94#ibcon#cleared, iclass 29 cls_cnt 0 2006.196.08:14:30.94$vc4f8/vb=2,4 2006.196.08:14:30.94#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.196.08:14:30.94#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.196.08:14:30.94#ibcon#ireg 11 cls_cnt 2 2006.196.08:14:30.94#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.196.08:14:31.00#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.196.08:14:31.00#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.196.08:14:31.00#ibcon#enter wrdev, iclass 31, count 2 2006.196.08:14:31.00#ibcon#first serial, iclass 31, count 2 2006.196.08:14:31.00#ibcon#enter sib2, iclass 31, count 2 2006.196.08:14:31.00#ibcon#flushed, iclass 31, count 2 2006.196.08:14:31.00#ibcon#about to write, iclass 31, count 2 2006.196.08:14:31.00#ibcon#wrote, iclass 31, count 2 2006.196.08:14:31.00#ibcon#about to read 3, iclass 31, count 2 2006.196.08:14:31.02#ibcon#read 3, iclass 31, count 2 2006.196.08:14:31.02#ibcon#about to read 4, iclass 31, count 2 2006.196.08:14:31.02#ibcon#read 4, iclass 31, count 2 2006.196.08:14:31.02#ibcon#about to read 5, iclass 31, count 2 2006.196.08:14:31.02#ibcon#read 5, iclass 31, count 2 2006.196.08:14:31.02#ibcon#about to read 6, iclass 31, count 2 2006.196.08:14:31.02#ibcon#read 6, iclass 31, count 2 2006.196.08:14:31.02#ibcon#end of sib2, iclass 31, count 2 2006.196.08:14:31.02#ibcon#*mode == 0, iclass 31, count 2 2006.196.08:14:31.02#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.196.08:14:31.02#ibcon#[27=AT02-04\r\n] 2006.196.08:14:31.02#ibcon#*before write, iclass 31, count 2 2006.196.08:14:31.02#ibcon#enter sib2, iclass 31, count 2 2006.196.08:14:31.02#ibcon#flushed, iclass 31, count 2 2006.196.08:14:31.02#ibcon#about to write, iclass 31, count 2 2006.196.08:14:31.02#ibcon#wrote, iclass 31, count 2 2006.196.08:14:31.02#ibcon#about to read 3, iclass 31, count 2 2006.196.08:14:31.05#ibcon#read 3, iclass 31, count 2 2006.196.08:14:31.05#ibcon#about to read 4, iclass 31, count 2 2006.196.08:14:31.05#ibcon#read 4, iclass 31, count 2 2006.196.08:14:31.05#ibcon#about to read 5, iclass 31, count 2 2006.196.08:14:31.05#ibcon#read 5, iclass 31, count 2 2006.196.08:14:31.05#ibcon#about to read 6, iclass 31, count 2 2006.196.08:14:31.05#ibcon#read 6, iclass 31, count 2 2006.196.08:14:31.05#ibcon#end of sib2, iclass 31, count 2 2006.196.08:14:31.05#ibcon#*after write, iclass 31, count 2 2006.196.08:14:31.05#ibcon#*before return 0, iclass 31, count 2 2006.196.08:14:31.05#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.196.08:14:31.05#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.196.08:14:31.05#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.196.08:14:31.05#ibcon#ireg 7 cls_cnt 0 2006.196.08:14:31.05#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.196.08:14:31.17#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.196.08:14:31.17#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.196.08:14:31.17#ibcon#enter wrdev, iclass 31, count 0 2006.196.08:14:31.17#ibcon#first serial, iclass 31, count 0 2006.196.08:14:31.17#ibcon#enter sib2, iclass 31, count 0 2006.196.08:14:31.17#ibcon#flushed, iclass 31, count 0 2006.196.08:14:31.17#ibcon#about to write, iclass 31, count 0 2006.196.08:14:31.17#ibcon#wrote, iclass 31, count 0 2006.196.08:14:31.17#ibcon#about to read 3, iclass 31, count 0 2006.196.08:14:31.19#ibcon#read 3, iclass 31, count 0 2006.196.08:14:31.19#ibcon#about to read 4, iclass 31, count 0 2006.196.08:14:31.19#ibcon#read 4, iclass 31, count 0 2006.196.08:14:31.19#ibcon#about to read 5, iclass 31, count 0 2006.196.08:14:31.19#ibcon#read 5, iclass 31, count 0 2006.196.08:14:31.19#ibcon#about to read 6, iclass 31, count 0 2006.196.08:14:31.19#ibcon#read 6, iclass 31, count 0 2006.196.08:14:31.19#ibcon#end of sib2, iclass 31, count 0 2006.196.08:14:31.19#ibcon#*mode == 0, iclass 31, count 0 2006.196.08:14:31.19#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.196.08:14:31.19#ibcon#[27=USB\r\n] 2006.196.08:14:31.19#ibcon#*before write, iclass 31, count 0 2006.196.08:14:31.19#ibcon#enter sib2, iclass 31, count 0 2006.196.08:14:31.19#ibcon#flushed, iclass 31, count 0 2006.196.08:14:31.19#ibcon#about to write, iclass 31, count 0 2006.196.08:14:31.19#ibcon#wrote, iclass 31, count 0 2006.196.08:14:31.19#ibcon#about to read 3, iclass 31, count 0 2006.196.08:14:31.22#ibcon#read 3, iclass 31, count 0 2006.196.08:14:31.22#ibcon#about to read 4, iclass 31, count 0 2006.196.08:14:31.22#ibcon#read 4, iclass 31, count 0 2006.196.08:14:31.22#ibcon#about to read 5, iclass 31, count 0 2006.196.08:14:31.22#ibcon#read 5, iclass 31, count 0 2006.196.08:14:31.22#ibcon#about to read 6, iclass 31, count 0 2006.196.08:14:31.22#ibcon#read 6, iclass 31, count 0 2006.196.08:14:31.22#ibcon#end of sib2, iclass 31, count 0 2006.196.08:14:31.22#ibcon#*after write, iclass 31, count 0 2006.196.08:14:31.22#ibcon#*before return 0, iclass 31, count 0 2006.196.08:14:31.22#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.196.08:14:31.22#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.196.08:14:31.22#ibcon#about to clear, iclass 31 cls_cnt 0 2006.196.08:14:31.22#ibcon#cleared, iclass 31 cls_cnt 0 2006.196.08:14:31.22$vc4f8/vblo=3,656.99 2006.196.08:14:31.22#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.196.08:14:31.22#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.196.08:14:31.22#ibcon#ireg 17 cls_cnt 0 2006.196.08:14:31.22#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:14:31.22#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:14:31.22#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:14:31.22#ibcon#enter wrdev, iclass 33, count 0 2006.196.08:14:31.22#ibcon#first serial, iclass 33, count 0 2006.196.08:14:31.22#ibcon#enter sib2, iclass 33, count 0 2006.196.08:14:31.22#ibcon#flushed, iclass 33, count 0 2006.196.08:14:31.22#ibcon#about to write, iclass 33, count 0 2006.196.08:14:31.22#ibcon#wrote, iclass 33, count 0 2006.196.08:14:31.22#ibcon#about to read 3, iclass 33, count 0 2006.196.08:14:31.24#ibcon#read 3, iclass 33, count 0 2006.196.08:14:31.24#ibcon#about to read 4, iclass 33, count 0 2006.196.08:14:31.24#ibcon#read 4, iclass 33, count 0 2006.196.08:14:31.24#ibcon#about to read 5, iclass 33, count 0 2006.196.08:14:31.24#ibcon#read 5, iclass 33, count 0 2006.196.08:14:31.24#ibcon#about to read 6, iclass 33, count 0 2006.196.08:14:31.24#ibcon#read 6, iclass 33, count 0 2006.196.08:14:31.24#ibcon#end of sib2, iclass 33, count 0 2006.196.08:14:31.24#ibcon#*mode == 0, iclass 33, count 0 2006.196.08:14:31.24#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.196.08:14:31.24#ibcon#[28=FRQ=03,656.99\r\n] 2006.196.08:14:31.24#ibcon#*before write, iclass 33, count 0 2006.196.08:14:31.24#ibcon#enter sib2, iclass 33, count 0 2006.196.08:14:31.24#ibcon#flushed, iclass 33, count 0 2006.196.08:14:31.24#ibcon#about to write, iclass 33, count 0 2006.196.08:14:31.24#ibcon#wrote, iclass 33, count 0 2006.196.08:14:31.24#ibcon#about to read 3, iclass 33, count 0 2006.196.08:14:31.28#ibcon#read 3, iclass 33, count 0 2006.196.08:14:31.28#ibcon#about to read 4, iclass 33, count 0 2006.196.08:14:31.28#ibcon#read 4, iclass 33, count 0 2006.196.08:14:31.28#ibcon#about to read 5, iclass 33, count 0 2006.196.08:14:31.28#ibcon#read 5, iclass 33, count 0 2006.196.08:14:31.28#ibcon#about to read 6, iclass 33, count 0 2006.196.08:14:31.28#ibcon#read 6, iclass 33, count 0 2006.196.08:14:31.28#ibcon#end of sib2, iclass 33, count 0 2006.196.08:14:31.28#ibcon#*after write, iclass 33, count 0 2006.196.08:14:31.28#ibcon#*before return 0, iclass 33, count 0 2006.196.08:14:31.28#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:14:31.28#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:14:31.28#ibcon#about to clear, iclass 33 cls_cnt 0 2006.196.08:14:31.28#ibcon#cleared, iclass 33 cls_cnt 0 2006.196.08:14:31.28$vc4f8/vb=3,4 2006.196.08:14:31.28#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.196.08:14:31.28#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.196.08:14:31.28#ibcon#ireg 11 cls_cnt 2 2006.196.08:14:31.28#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.196.08:14:31.34#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.196.08:14:31.34#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.196.08:14:31.34#ibcon#enter wrdev, iclass 35, count 2 2006.196.08:14:31.34#ibcon#first serial, iclass 35, count 2 2006.196.08:14:31.34#ibcon#enter sib2, iclass 35, count 2 2006.196.08:14:31.34#ibcon#flushed, iclass 35, count 2 2006.196.08:14:31.34#ibcon#about to write, iclass 35, count 2 2006.196.08:14:31.34#ibcon#wrote, iclass 35, count 2 2006.196.08:14:31.34#ibcon#about to read 3, iclass 35, count 2 2006.196.08:14:31.36#ibcon#read 3, iclass 35, count 2 2006.196.08:14:31.36#ibcon#about to read 4, iclass 35, count 2 2006.196.08:14:31.36#ibcon#read 4, iclass 35, count 2 2006.196.08:14:31.36#ibcon#about to read 5, iclass 35, count 2 2006.196.08:14:31.36#ibcon#read 5, iclass 35, count 2 2006.196.08:14:31.36#ibcon#about to read 6, iclass 35, count 2 2006.196.08:14:31.36#ibcon#read 6, iclass 35, count 2 2006.196.08:14:31.36#ibcon#end of sib2, iclass 35, count 2 2006.196.08:14:31.36#ibcon#*mode == 0, iclass 35, count 2 2006.196.08:14:31.36#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.196.08:14:31.36#ibcon#[27=AT03-04\r\n] 2006.196.08:14:31.36#ibcon#*before write, iclass 35, count 2 2006.196.08:14:31.36#ibcon#enter sib2, iclass 35, count 2 2006.196.08:14:31.36#ibcon#flushed, iclass 35, count 2 2006.196.08:14:31.36#ibcon#about to write, iclass 35, count 2 2006.196.08:14:31.36#ibcon#wrote, iclass 35, count 2 2006.196.08:14:31.36#ibcon#about to read 3, iclass 35, count 2 2006.196.08:14:31.39#ibcon#read 3, iclass 35, count 2 2006.196.08:14:31.39#ibcon#about to read 4, iclass 35, count 2 2006.196.08:14:31.39#ibcon#read 4, iclass 35, count 2 2006.196.08:14:31.39#ibcon#about to read 5, iclass 35, count 2 2006.196.08:14:31.39#ibcon#read 5, iclass 35, count 2 2006.196.08:14:31.39#ibcon#about to read 6, iclass 35, count 2 2006.196.08:14:31.39#ibcon#read 6, iclass 35, count 2 2006.196.08:14:31.39#ibcon#end of sib2, iclass 35, count 2 2006.196.08:14:31.39#ibcon#*after write, iclass 35, count 2 2006.196.08:14:31.39#ibcon#*before return 0, iclass 35, count 2 2006.196.08:14:31.39#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.196.08:14:31.39#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.196.08:14:31.39#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.196.08:14:31.39#ibcon#ireg 7 cls_cnt 0 2006.196.08:14:31.39#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.196.08:14:31.51#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.196.08:14:31.51#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.196.08:14:31.51#ibcon#enter wrdev, iclass 35, count 0 2006.196.08:14:31.51#ibcon#first serial, iclass 35, count 0 2006.196.08:14:31.51#ibcon#enter sib2, iclass 35, count 0 2006.196.08:14:31.51#ibcon#flushed, iclass 35, count 0 2006.196.08:14:31.51#ibcon#about to write, iclass 35, count 0 2006.196.08:14:31.51#ibcon#wrote, iclass 35, count 0 2006.196.08:14:31.51#ibcon#about to read 3, iclass 35, count 0 2006.196.08:14:31.53#ibcon#read 3, iclass 35, count 0 2006.196.08:14:31.53#ibcon#about to read 4, iclass 35, count 0 2006.196.08:14:31.53#ibcon#read 4, iclass 35, count 0 2006.196.08:14:31.53#ibcon#about to read 5, iclass 35, count 0 2006.196.08:14:31.53#ibcon#read 5, iclass 35, count 0 2006.196.08:14:31.53#ibcon#about to read 6, iclass 35, count 0 2006.196.08:14:31.53#ibcon#read 6, iclass 35, count 0 2006.196.08:14:31.53#ibcon#end of sib2, iclass 35, count 0 2006.196.08:14:31.53#ibcon#*mode == 0, iclass 35, count 0 2006.196.08:14:31.53#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.196.08:14:31.53#ibcon#[27=USB\r\n] 2006.196.08:14:31.53#ibcon#*before write, iclass 35, count 0 2006.196.08:14:31.53#ibcon#enter sib2, iclass 35, count 0 2006.196.08:14:31.53#ibcon#flushed, iclass 35, count 0 2006.196.08:14:31.53#ibcon#about to write, iclass 35, count 0 2006.196.08:14:31.53#ibcon#wrote, iclass 35, count 0 2006.196.08:14:31.53#ibcon#about to read 3, iclass 35, count 0 2006.196.08:14:31.56#ibcon#read 3, iclass 35, count 0 2006.196.08:14:31.56#ibcon#about to read 4, iclass 35, count 0 2006.196.08:14:31.56#ibcon#read 4, iclass 35, count 0 2006.196.08:14:31.56#ibcon#about to read 5, iclass 35, count 0 2006.196.08:14:31.56#ibcon#read 5, iclass 35, count 0 2006.196.08:14:31.56#ibcon#about to read 6, iclass 35, count 0 2006.196.08:14:31.56#ibcon#read 6, iclass 35, count 0 2006.196.08:14:31.56#ibcon#end of sib2, iclass 35, count 0 2006.196.08:14:31.56#ibcon#*after write, iclass 35, count 0 2006.196.08:14:31.56#ibcon#*before return 0, iclass 35, count 0 2006.196.08:14:31.56#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.196.08:14:31.56#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.196.08:14:31.56#ibcon#about to clear, iclass 35 cls_cnt 0 2006.196.08:14:31.56#ibcon#cleared, iclass 35 cls_cnt 0 2006.196.08:14:31.56$vc4f8/vblo=4,712.99 2006.196.08:14:31.56#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.196.08:14:31.56#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.196.08:14:31.56#ibcon#ireg 17 cls_cnt 0 2006.196.08:14:31.56#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.196.08:14:31.56#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.196.08:14:31.56#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.196.08:14:31.56#ibcon#enter wrdev, iclass 37, count 0 2006.196.08:14:31.56#ibcon#first serial, iclass 37, count 0 2006.196.08:14:31.56#ibcon#enter sib2, iclass 37, count 0 2006.196.08:14:31.56#ibcon#flushed, iclass 37, count 0 2006.196.08:14:31.56#ibcon#about to write, iclass 37, count 0 2006.196.08:14:31.56#ibcon#wrote, iclass 37, count 0 2006.196.08:14:31.56#ibcon#about to read 3, iclass 37, count 0 2006.196.08:14:31.58#ibcon#read 3, iclass 37, count 0 2006.196.08:14:31.58#ibcon#about to read 4, iclass 37, count 0 2006.196.08:14:31.58#ibcon#read 4, iclass 37, count 0 2006.196.08:14:31.58#ibcon#about to read 5, iclass 37, count 0 2006.196.08:14:31.58#ibcon#read 5, iclass 37, count 0 2006.196.08:14:31.58#ibcon#about to read 6, iclass 37, count 0 2006.196.08:14:31.58#ibcon#read 6, iclass 37, count 0 2006.196.08:14:31.58#ibcon#end of sib2, iclass 37, count 0 2006.196.08:14:31.58#ibcon#*mode == 0, iclass 37, count 0 2006.196.08:14:31.58#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.196.08:14:31.58#ibcon#[28=FRQ=04,712.99\r\n] 2006.196.08:14:31.58#ibcon#*before write, iclass 37, count 0 2006.196.08:14:31.58#ibcon#enter sib2, iclass 37, count 0 2006.196.08:14:31.58#ibcon#flushed, iclass 37, count 0 2006.196.08:14:31.58#ibcon#about to write, iclass 37, count 0 2006.196.08:14:31.58#ibcon#wrote, iclass 37, count 0 2006.196.08:14:31.58#ibcon#about to read 3, iclass 37, count 0 2006.196.08:14:31.62#ibcon#read 3, iclass 37, count 0 2006.196.08:14:31.62#ibcon#about to read 4, iclass 37, count 0 2006.196.08:14:31.62#ibcon#read 4, iclass 37, count 0 2006.196.08:14:31.62#ibcon#about to read 5, iclass 37, count 0 2006.196.08:14:31.62#ibcon#read 5, iclass 37, count 0 2006.196.08:14:31.62#ibcon#about to read 6, iclass 37, count 0 2006.196.08:14:31.62#ibcon#read 6, iclass 37, count 0 2006.196.08:14:31.62#ibcon#end of sib2, iclass 37, count 0 2006.196.08:14:31.62#ibcon#*after write, iclass 37, count 0 2006.196.08:14:31.62#ibcon#*before return 0, iclass 37, count 0 2006.196.08:14:31.62#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.196.08:14:31.62#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.196.08:14:31.62#ibcon#about to clear, iclass 37 cls_cnt 0 2006.196.08:14:31.62#ibcon#cleared, iclass 37 cls_cnt 0 2006.196.08:14:31.62$vc4f8/vb=4,4 2006.196.08:14:31.62#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.196.08:14:31.62#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.196.08:14:31.62#ibcon#ireg 11 cls_cnt 2 2006.196.08:14:31.62#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.196.08:14:31.68#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.196.08:14:31.68#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.196.08:14:31.68#ibcon#enter wrdev, iclass 39, count 2 2006.196.08:14:31.68#ibcon#first serial, iclass 39, count 2 2006.196.08:14:31.68#ibcon#enter sib2, iclass 39, count 2 2006.196.08:14:31.68#ibcon#flushed, iclass 39, count 2 2006.196.08:14:31.68#ibcon#about to write, iclass 39, count 2 2006.196.08:14:31.68#ibcon#wrote, iclass 39, count 2 2006.196.08:14:31.68#ibcon#about to read 3, iclass 39, count 2 2006.196.08:14:31.70#ibcon#read 3, iclass 39, count 2 2006.196.08:14:31.70#ibcon#about to read 4, iclass 39, count 2 2006.196.08:14:31.70#ibcon#read 4, iclass 39, count 2 2006.196.08:14:31.70#ibcon#about to read 5, iclass 39, count 2 2006.196.08:14:31.70#ibcon#read 5, iclass 39, count 2 2006.196.08:14:31.70#ibcon#about to read 6, iclass 39, count 2 2006.196.08:14:31.70#ibcon#read 6, iclass 39, count 2 2006.196.08:14:31.70#ibcon#end of sib2, iclass 39, count 2 2006.196.08:14:31.70#ibcon#*mode == 0, iclass 39, count 2 2006.196.08:14:31.70#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.196.08:14:31.70#ibcon#[27=AT04-04\r\n] 2006.196.08:14:31.70#ibcon#*before write, iclass 39, count 2 2006.196.08:14:31.70#ibcon#enter sib2, iclass 39, count 2 2006.196.08:14:31.70#ibcon#flushed, iclass 39, count 2 2006.196.08:14:31.70#ibcon#about to write, iclass 39, count 2 2006.196.08:14:31.70#ibcon#wrote, iclass 39, count 2 2006.196.08:14:31.70#ibcon#about to read 3, iclass 39, count 2 2006.196.08:14:31.73#ibcon#read 3, iclass 39, count 2 2006.196.08:14:31.73#ibcon#about to read 4, iclass 39, count 2 2006.196.08:14:31.73#ibcon#read 4, iclass 39, count 2 2006.196.08:14:31.73#ibcon#about to read 5, iclass 39, count 2 2006.196.08:14:31.73#ibcon#read 5, iclass 39, count 2 2006.196.08:14:31.73#ibcon#about to read 6, iclass 39, count 2 2006.196.08:14:31.73#ibcon#read 6, iclass 39, count 2 2006.196.08:14:31.73#ibcon#end of sib2, iclass 39, count 2 2006.196.08:14:31.73#ibcon#*after write, iclass 39, count 2 2006.196.08:14:31.73#ibcon#*before return 0, iclass 39, count 2 2006.196.08:14:31.73#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.196.08:14:31.73#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.196.08:14:31.73#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.196.08:14:31.73#ibcon#ireg 7 cls_cnt 0 2006.196.08:14:31.73#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.196.08:14:31.85#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.196.08:14:31.85#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.196.08:14:31.85#ibcon#enter wrdev, iclass 39, count 0 2006.196.08:14:31.85#ibcon#first serial, iclass 39, count 0 2006.196.08:14:31.85#ibcon#enter sib2, iclass 39, count 0 2006.196.08:14:31.85#ibcon#flushed, iclass 39, count 0 2006.196.08:14:31.85#ibcon#about to write, iclass 39, count 0 2006.196.08:14:31.85#ibcon#wrote, iclass 39, count 0 2006.196.08:14:31.85#ibcon#about to read 3, iclass 39, count 0 2006.196.08:14:31.87#ibcon#read 3, iclass 39, count 0 2006.196.08:14:31.87#ibcon#about to read 4, iclass 39, count 0 2006.196.08:14:31.87#ibcon#read 4, iclass 39, count 0 2006.196.08:14:31.87#ibcon#about to read 5, iclass 39, count 0 2006.196.08:14:31.87#ibcon#read 5, iclass 39, count 0 2006.196.08:14:31.87#ibcon#about to read 6, iclass 39, count 0 2006.196.08:14:31.87#ibcon#read 6, iclass 39, count 0 2006.196.08:14:31.87#ibcon#end of sib2, iclass 39, count 0 2006.196.08:14:31.87#ibcon#*mode == 0, iclass 39, count 0 2006.196.08:14:31.87#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.196.08:14:31.87#ibcon#[27=USB\r\n] 2006.196.08:14:31.87#ibcon#*before write, iclass 39, count 0 2006.196.08:14:31.87#ibcon#enter sib2, iclass 39, count 0 2006.196.08:14:31.87#ibcon#flushed, iclass 39, count 0 2006.196.08:14:31.87#ibcon#about to write, iclass 39, count 0 2006.196.08:14:31.87#ibcon#wrote, iclass 39, count 0 2006.196.08:14:31.87#ibcon#about to read 3, iclass 39, count 0 2006.196.08:14:31.90#ibcon#read 3, iclass 39, count 0 2006.196.08:14:31.90#ibcon#about to read 4, iclass 39, count 0 2006.196.08:14:31.90#ibcon#read 4, iclass 39, count 0 2006.196.08:14:31.90#ibcon#about to read 5, iclass 39, count 0 2006.196.08:14:31.90#ibcon#read 5, iclass 39, count 0 2006.196.08:14:31.90#ibcon#about to read 6, iclass 39, count 0 2006.196.08:14:31.90#ibcon#read 6, iclass 39, count 0 2006.196.08:14:31.90#ibcon#end of sib2, iclass 39, count 0 2006.196.08:14:31.90#ibcon#*after write, iclass 39, count 0 2006.196.08:14:31.90#ibcon#*before return 0, iclass 39, count 0 2006.196.08:14:31.90#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.196.08:14:31.90#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.196.08:14:31.90#ibcon#about to clear, iclass 39 cls_cnt 0 2006.196.08:14:31.90#ibcon#cleared, iclass 39 cls_cnt 0 2006.196.08:14:31.90$vc4f8/vblo=5,744.99 2006.196.08:14:31.90#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.196.08:14:31.90#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.196.08:14:31.90#ibcon#ireg 17 cls_cnt 0 2006.196.08:14:31.90#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.196.08:14:31.90#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.196.08:14:31.90#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.196.08:14:31.90#ibcon#enter wrdev, iclass 3, count 0 2006.196.08:14:31.90#ibcon#first serial, iclass 3, count 0 2006.196.08:14:31.90#ibcon#enter sib2, iclass 3, count 0 2006.196.08:14:31.90#ibcon#flushed, iclass 3, count 0 2006.196.08:14:31.90#ibcon#about to write, iclass 3, count 0 2006.196.08:14:31.90#ibcon#wrote, iclass 3, count 0 2006.196.08:14:31.90#ibcon#about to read 3, iclass 3, count 0 2006.196.08:14:31.92#ibcon#read 3, iclass 3, count 0 2006.196.08:14:31.92#ibcon#about to read 4, iclass 3, count 0 2006.196.08:14:31.92#ibcon#read 4, iclass 3, count 0 2006.196.08:14:31.92#ibcon#about to read 5, iclass 3, count 0 2006.196.08:14:31.92#ibcon#read 5, iclass 3, count 0 2006.196.08:14:31.92#ibcon#about to read 6, iclass 3, count 0 2006.196.08:14:31.92#ibcon#read 6, iclass 3, count 0 2006.196.08:14:31.92#ibcon#end of sib2, iclass 3, count 0 2006.196.08:14:31.92#ibcon#*mode == 0, iclass 3, count 0 2006.196.08:14:31.92#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.196.08:14:31.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.196.08:14:31.92#ibcon#*before write, iclass 3, count 0 2006.196.08:14:31.92#ibcon#enter sib2, iclass 3, count 0 2006.196.08:14:31.92#ibcon#flushed, iclass 3, count 0 2006.196.08:14:31.92#ibcon#about to write, iclass 3, count 0 2006.196.08:14:31.92#ibcon#wrote, iclass 3, count 0 2006.196.08:14:31.92#ibcon#about to read 3, iclass 3, count 0 2006.196.08:14:31.96#ibcon#read 3, iclass 3, count 0 2006.196.08:14:31.96#ibcon#about to read 4, iclass 3, count 0 2006.196.08:14:31.96#ibcon#read 4, iclass 3, count 0 2006.196.08:14:31.96#ibcon#about to read 5, iclass 3, count 0 2006.196.08:14:31.96#ibcon#read 5, iclass 3, count 0 2006.196.08:14:31.96#ibcon#about to read 6, iclass 3, count 0 2006.196.08:14:31.96#ibcon#read 6, iclass 3, count 0 2006.196.08:14:31.96#ibcon#end of sib2, iclass 3, count 0 2006.196.08:14:31.96#ibcon#*after write, iclass 3, count 0 2006.196.08:14:31.96#ibcon#*before return 0, iclass 3, count 0 2006.196.08:14:31.96#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.196.08:14:31.96#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.196.08:14:31.96#ibcon#about to clear, iclass 3 cls_cnt 0 2006.196.08:14:31.96#ibcon#cleared, iclass 3 cls_cnt 0 2006.196.08:14:31.96$vc4f8/vb=5,4 2006.196.08:14:31.96#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.196.08:14:31.96#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.196.08:14:31.96#ibcon#ireg 11 cls_cnt 2 2006.196.08:14:31.96#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.196.08:14:32.02#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.196.08:14:32.02#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.196.08:14:32.02#ibcon#enter wrdev, iclass 5, count 2 2006.196.08:14:32.02#ibcon#first serial, iclass 5, count 2 2006.196.08:14:32.02#ibcon#enter sib2, iclass 5, count 2 2006.196.08:14:32.02#ibcon#flushed, iclass 5, count 2 2006.196.08:14:32.02#ibcon#about to write, iclass 5, count 2 2006.196.08:14:32.02#ibcon#wrote, iclass 5, count 2 2006.196.08:14:32.02#ibcon#about to read 3, iclass 5, count 2 2006.196.08:14:32.04#ibcon#read 3, iclass 5, count 2 2006.196.08:14:32.04#ibcon#about to read 4, iclass 5, count 2 2006.196.08:14:32.04#ibcon#read 4, iclass 5, count 2 2006.196.08:14:32.04#ibcon#about to read 5, iclass 5, count 2 2006.196.08:14:32.04#ibcon#read 5, iclass 5, count 2 2006.196.08:14:32.04#ibcon#about to read 6, iclass 5, count 2 2006.196.08:14:32.04#ibcon#read 6, iclass 5, count 2 2006.196.08:14:32.04#ibcon#end of sib2, iclass 5, count 2 2006.196.08:14:32.04#ibcon#*mode == 0, iclass 5, count 2 2006.196.08:14:32.04#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.196.08:14:32.04#ibcon#[27=AT05-04\r\n] 2006.196.08:14:32.04#ibcon#*before write, iclass 5, count 2 2006.196.08:14:32.04#ibcon#enter sib2, iclass 5, count 2 2006.196.08:14:32.04#ibcon#flushed, iclass 5, count 2 2006.196.08:14:32.04#ibcon#about to write, iclass 5, count 2 2006.196.08:14:32.04#ibcon#wrote, iclass 5, count 2 2006.196.08:14:32.04#ibcon#about to read 3, iclass 5, count 2 2006.196.08:14:32.07#ibcon#read 3, iclass 5, count 2 2006.196.08:14:32.07#ibcon#about to read 4, iclass 5, count 2 2006.196.08:14:32.07#ibcon#read 4, iclass 5, count 2 2006.196.08:14:32.07#ibcon#about to read 5, iclass 5, count 2 2006.196.08:14:32.07#ibcon#read 5, iclass 5, count 2 2006.196.08:14:32.07#ibcon#about to read 6, iclass 5, count 2 2006.196.08:14:32.07#ibcon#read 6, iclass 5, count 2 2006.196.08:14:32.07#ibcon#end of sib2, iclass 5, count 2 2006.196.08:14:32.07#ibcon#*after write, iclass 5, count 2 2006.196.08:14:32.07#ibcon#*before return 0, iclass 5, count 2 2006.196.08:14:32.07#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.196.08:14:32.07#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.196.08:14:32.07#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.196.08:14:32.07#ibcon#ireg 7 cls_cnt 0 2006.196.08:14:32.07#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.196.08:14:32.19#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.196.08:14:32.19#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.196.08:14:32.19#ibcon#enter wrdev, iclass 5, count 0 2006.196.08:14:32.19#ibcon#first serial, iclass 5, count 0 2006.196.08:14:32.19#ibcon#enter sib2, iclass 5, count 0 2006.196.08:14:32.19#ibcon#flushed, iclass 5, count 0 2006.196.08:14:32.19#ibcon#about to write, iclass 5, count 0 2006.196.08:14:32.19#ibcon#wrote, iclass 5, count 0 2006.196.08:14:32.19#ibcon#about to read 3, iclass 5, count 0 2006.196.08:14:32.22#ibcon#read 3, iclass 5, count 0 2006.196.08:14:32.22#ibcon#about to read 4, iclass 5, count 0 2006.196.08:14:32.22#ibcon#read 4, iclass 5, count 0 2006.196.08:14:32.22#ibcon#about to read 5, iclass 5, count 0 2006.196.08:14:32.22#ibcon#read 5, iclass 5, count 0 2006.196.08:14:32.22#ibcon#about to read 6, iclass 5, count 0 2006.196.08:14:32.22#ibcon#read 6, iclass 5, count 0 2006.196.08:14:32.22#ibcon#end of sib2, iclass 5, count 0 2006.196.08:14:32.22#ibcon#*mode == 0, iclass 5, count 0 2006.196.08:14:32.22#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.196.08:14:32.22#ibcon#[27=USB\r\n] 2006.196.08:14:32.22#ibcon#*before write, iclass 5, count 0 2006.196.08:14:32.22#ibcon#enter sib2, iclass 5, count 0 2006.196.08:14:32.22#ibcon#flushed, iclass 5, count 0 2006.196.08:14:32.22#ibcon#about to write, iclass 5, count 0 2006.196.08:14:32.22#ibcon#wrote, iclass 5, count 0 2006.196.08:14:32.22#ibcon#about to read 3, iclass 5, count 0 2006.196.08:14:32.25#ibcon#read 3, iclass 5, count 0 2006.196.08:14:32.25#ibcon#about to read 4, iclass 5, count 0 2006.196.08:14:32.25#ibcon#read 4, iclass 5, count 0 2006.196.08:14:32.25#ibcon#about to read 5, iclass 5, count 0 2006.196.08:14:32.25#ibcon#read 5, iclass 5, count 0 2006.196.08:14:32.25#ibcon#about to read 6, iclass 5, count 0 2006.196.08:14:32.25#ibcon#read 6, iclass 5, count 0 2006.196.08:14:32.25#ibcon#end of sib2, iclass 5, count 0 2006.196.08:14:32.25#ibcon#*after write, iclass 5, count 0 2006.196.08:14:32.25#ibcon#*before return 0, iclass 5, count 0 2006.196.08:14:32.25#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.196.08:14:32.25#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.196.08:14:32.25#ibcon#about to clear, iclass 5 cls_cnt 0 2006.196.08:14:32.25#ibcon#cleared, iclass 5 cls_cnt 0 2006.196.08:14:32.25$vc4f8/vblo=6,752.99 2006.196.08:14:32.25#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.196.08:14:32.25#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.196.08:14:32.25#ibcon#ireg 17 cls_cnt 0 2006.196.08:14:32.25#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.196.08:14:32.25#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.196.08:14:32.25#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.196.08:14:32.25#ibcon#enter wrdev, iclass 7, count 0 2006.196.08:14:32.25#ibcon#first serial, iclass 7, count 0 2006.196.08:14:32.25#ibcon#enter sib2, iclass 7, count 0 2006.196.08:14:32.25#ibcon#flushed, iclass 7, count 0 2006.196.08:14:32.25#ibcon#about to write, iclass 7, count 0 2006.196.08:14:32.25#ibcon#wrote, iclass 7, count 0 2006.196.08:14:32.25#ibcon#about to read 3, iclass 7, count 0 2006.196.08:14:32.27#ibcon#read 3, iclass 7, count 0 2006.196.08:14:32.27#ibcon#about to read 4, iclass 7, count 0 2006.196.08:14:32.27#ibcon#read 4, iclass 7, count 0 2006.196.08:14:32.27#ibcon#about to read 5, iclass 7, count 0 2006.196.08:14:32.27#ibcon#read 5, iclass 7, count 0 2006.196.08:14:32.27#ibcon#about to read 6, iclass 7, count 0 2006.196.08:14:32.27#ibcon#read 6, iclass 7, count 0 2006.196.08:14:32.27#ibcon#end of sib2, iclass 7, count 0 2006.196.08:14:32.27#ibcon#*mode == 0, iclass 7, count 0 2006.196.08:14:32.27#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.196.08:14:32.27#ibcon#[28=FRQ=06,752.99\r\n] 2006.196.08:14:32.27#ibcon#*before write, iclass 7, count 0 2006.196.08:14:32.27#ibcon#enter sib2, iclass 7, count 0 2006.196.08:14:32.27#ibcon#flushed, iclass 7, count 0 2006.196.08:14:32.27#ibcon#about to write, iclass 7, count 0 2006.196.08:14:32.27#ibcon#wrote, iclass 7, count 0 2006.196.08:14:32.27#ibcon#about to read 3, iclass 7, count 0 2006.196.08:14:32.31#ibcon#read 3, iclass 7, count 0 2006.196.08:14:32.31#ibcon#about to read 4, iclass 7, count 0 2006.196.08:14:32.31#ibcon#read 4, iclass 7, count 0 2006.196.08:14:32.31#ibcon#about to read 5, iclass 7, count 0 2006.196.08:14:32.31#ibcon#read 5, iclass 7, count 0 2006.196.08:14:32.31#ibcon#about to read 6, iclass 7, count 0 2006.196.08:14:32.31#ibcon#read 6, iclass 7, count 0 2006.196.08:14:32.31#ibcon#end of sib2, iclass 7, count 0 2006.196.08:14:32.31#ibcon#*after write, iclass 7, count 0 2006.196.08:14:32.31#ibcon#*before return 0, iclass 7, count 0 2006.196.08:14:32.31#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.196.08:14:32.31#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.196.08:14:32.31#ibcon#about to clear, iclass 7 cls_cnt 0 2006.196.08:14:32.31#ibcon#cleared, iclass 7 cls_cnt 0 2006.196.08:14:32.31$vc4f8/vb=6,4 2006.196.08:14:32.31#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.196.08:14:32.31#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.196.08:14:32.31#ibcon#ireg 11 cls_cnt 2 2006.196.08:14:32.31#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.196.08:14:32.37#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.196.08:14:32.37#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.196.08:14:32.37#ibcon#enter wrdev, iclass 11, count 2 2006.196.08:14:32.37#ibcon#first serial, iclass 11, count 2 2006.196.08:14:32.37#ibcon#enter sib2, iclass 11, count 2 2006.196.08:14:32.37#ibcon#flushed, iclass 11, count 2 2006.196.08:14:32.37#ibcon#about to write, iclass 11, count 2 2006.196.08:14:32.37#ibcon#wrote, iclass 11, count 2 2006.196.08:14:32.37#ibcon#about to read 3, iclass 11, count 2 2006.196.08:14:32.39#ibcon#read 3, iclass 11, count 2 2006.196.08:14:32.39#ibcon#about to read 4, iclass 11, count 2 2006.196.08:14:32.39#ibcon#read 4, iclass 11, count 2 2006.196.08:14:32.39#ibcon#about to read 5, iclass 11, count 2 2006.196.08:14:32.39#ibcon#read 5, iclass 11, count 2 2006.196.08:14:32.39#ibcon#about to read 6, iclass 11, count 2 2006.196.08:14:32.39#ibcon#read 6, iclass 11, count 2 2006.196.08:14:32.39#ibcon#end of sib2, iclass 11, count 2 2006.196.08:14:32.39#ibcon#*mode == 0, iclass 11, count 2 2006.196.08:14:32.39#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.196.08:14:32.39#ibcon#[27=AT06-04\r\n] 2006.196.08:14:32.39#ibcon#*before write, iclass 11, count 2 2006.196.08:14:32.39#ibcon#enter sib2, iclass 11, count 2 2006.196.08:14:32.39#ibcon#flushed, iclass 11, count 2 2006.196.08:14:32.39#ibcon#about to write, iclass 11, count 2 2006.196.08:14:32.39#ibcon#wrote, iclass 11, count 2 2006.196.08:14:32.39#ibcon#about to read 3, iclass 11, count 2 2006.196.08:14:32.42#ibcon#read 3, iclass 11, count 2 2006.196.08:14:32.42#ibcon#about to read 4, iclass 11, count 2 2006.196.08:14:32.42#ibcon#read 4, iclass 11, count 2 2006.196.08:14:32.42#ibcon#about to read 5, iclass 11, count 2 2006.196.08:14:32.42#ibcon#read 5, iclass 11, count 2 2006.196.08:14:32.42#ibcon#about to read 6, iclass 11, count 2 2006.196.08:14:32.42#ibcon#read 6, iclass 11, count 2 2006.196.08:14:32.42#ibcon#end of sib2, iclass 11, count 2 2006.196.08:14:32.42#ibcon#*after write, iclass 11, count 2 2006.196.08:14:32.42#ibcon#*before return 0, iclass 11, count 2 2006.196.08:14:32.42#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.196.08:14:32.42#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.196.08:14:32.42#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.196.08:14:32.42#ibcon#ireg 7 cls_cnt 0 2006.196.08:14:32.42#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.196.08:14:32.54#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.196.08:14:32.54#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.196.08:14:32.54#ibcon#enter wrdev, iclass 11, count 0 2006.196.08:14:32.54#ibcon#first serial, iclass 11, count 0 2006.196.08:14:32.54#ibcon#enter sib2, iclass 11, count 0 2006.196.08:14:32.54#ibcon#flushed, iclass 11, count 0 2006.196.08:14:32.54#ibcon#about to write, iclass 11, count 0 2006.196.08:14:32.54#ibcon#wrote, iclass 11, count 0 2006.196.08:14:32.54#ibcon#about to read 3, iclass 11, count 0 2006.196.08:14:32.56#ibcon#read 3, iclass 11, count 0 2006.196.08:14:32.56#ibcon#about to read 4, iclass 11, count 0 2006.196.08:14:32.56#ibcon#read 4, iclass 11, count 0 2006.196.08:14:32.56#ibcon#about to read 5, iclass 11, count 0 2006.196.08:14:32.56#ibcon#read 5, iclass 11, count 0 2006.196.08:14:32.56#ibcon#about to read 6, iclass 11, count 0 2006.196.08:14:32.56#ibcon#read 6, iclass 11, count 0 2006.196.08:14:32.56#ibcon#end of sib2, iclass 11, count 0 2006.196.08:14:32.56#ibcon#*mode == 0, iclass 11, count 0 2006.196.08:14:32.56#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.196.08:14:32.56#ibcon#[27=USB\r\n] 2006.196.08:14:32.56#ibcon#*before write, iclass 11, count 0 2006.196.08:14:32.56#ibcon#enter sib2, iclass 11, count 0 2006.196.08:14:32.56#ibcon#flushed, iclass 11, count 0 2006.196.08:14:32.56#ibcon#about to write, iclass 11, count 0 2006.196.08:14:32.56#ibcon#wrote, iclass 11, count 0 2006.196.08:14:32.56#ibcon#about to read 3, iclass 11, count 0 2006.196.08:14:32.59#ibcon#read 3, iclass 11, count 0 2006.196.08:14:32.59#ibcon#about to read 4, iclass 11, count 0 2006.196.08:14:32.59#ibcon#read 4, iclass 11, count 0 2006.196.08:14:32.59#ibcon#about to read 5, iclass 11, count 0 2006.196.08:14:32.59#ibcon#read 5, iclass 11, count 0 2006.196.08:14:32.59#ibcon#about to read 6, iclass 11, count 0 2006.196.08:14:32.59#ibcon#read 6, iclass 11, count 0 2006.196.08:14:32.59#ibcon#end of sib2, iclass 11, count 0 2006.196.08:14:32.59#ibcon#*after write, iclass 11, count 0 2006.196.08:14:32.59#ibcon#*before return 0, iclass 11, count 0 2006.196.08:14:32.59#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.196.08:14:32.59#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.196.08:14:32.59#ibcon#about to clear, iclass 11 cls_cnt 0 2006.196.08:14:32.59#ibcon#cleared, iclass 11 cls_cnt 0 2006.196.08:14:32.59$vc4f8/vabw=wide 2006.196.08:14:32.59#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.196.08:14:32.59#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.196.08:14:32.59#ibcon#ireg 8 cls_cnt 0 2006.196.08:14:32.59#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.196.08:14:32.59#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.196.08:14:32.59#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.196.08:14:32.59#ibcon#enter wrdev, iclass 13, count 0 2006.196.08:14:32.59#ibcon#first serial, iclass 13, count 0 2006.196.08:14:32.59#ibcon#enter sib2, iclass 13, count 0 2006.196.08:14:32.59#ibcon#flushed, iclass 13, count 0 2006.196.08:14:32.59#ibcon#about to write, iclass 13, count 0 2006.196.08:14:32.59#ibcon#wrote, iclass 13, count 0 2006.196.08:14:32.59#ibcon#about to read 3, iclass 13, count 0 2006.196.08:14:32.61#ibcon#read 3, iclass 13, count 0 2006.196.08:14:32.61#ibcon#about to read 4, iclass 13, count 0 2006.196.08:14:32.61#ibcon#read 4, iclass 13, count 0 2006.196.08:14:32.61#ibcon#about to read 5, iclass 13, count 0 2006.196.08:14:32.61#ibcon#read 5, iclass 13, count 0 2006.196.08:14:32.61#ibcon#about to read 6, iclass 13, count 0 2006.196.08:14:32.61#ibcon#read 6, iclass 13, count 0 2006.196.08:14:32.61#ibcon#end of sib2, iclass 13, count 0 2006.196.08:14:32.61#ibcon#*mode == 0, iclass 13, count 0 2006.196.08:14:32.61#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.196.08:14:32.61#ibcon#[25=BW32\r\n] 2006.196.08:14:32.61#ibcon#*before write, iclass 13, count 0 2006.196.08:14:32.61#ibcon#enter sib2, iclass 13, count 0 2006.196.08:14:32.61#ibcon#flushed, iclass 13, count 0 2006.196.08:14:32.61#ibcon#about to write, iclass 13, count 0 2006.196.08:14:32.61#ibcon#wrote, iclass 13, count 0 2006.196.08:14:32.61#ibcon#about to read 3, iclass 13, count 0 2006.196.08:14:32.64#ibcon#read 3, iclass 13, count 0 2006.196.08:14:32.64#ibcon#about to read 4, iclass 13, count 0 2006.196.08:14:32.64#ibcon#read 4, iclass 13, count 0 2006.196.08:14:32.64#ibcon#about to read 5, iclass 13, count 0 2006.196.08:14:32.64#ibcon#read 5, iclass 13, count 0 2006.196.08:14:32.64#ibcon#about to read 6, iclass 13, count 0 2006.196.08:14:32.64#ibcon#read 6, iclass 13, count 0 2006.196.08:14:32.64#ibcon#end of sib2, iclass 13, count 0 2006.196.08:14:32.64#ibcon#*after write, iclass 13, count 0 2006.196.08:14:32.64#ibcon#*before return 0, iclass 13, count 0 2006.196.08:14:32.64#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.196.08:14:32.64#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.196.08:14:32.64#ibcon#about to clear, iclass 13 cls_cnt 0 2006.196.08:14:32.64#ibcon#cleared, iclass 13 cls_cnt 0 2006.196.08:14:32.64$vc4f8/vbbw=wide 2006.196.08:14:32.64#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.196.08:14:32.64#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.196.08:14:32.64#ibcon#ireg 8 cls_cnt 0 2006.196.08:14:32.64#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.196.08:14:32.71#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.196.08:14:32.71#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.196.08:14:32.71#ibcon#enter wrdev, iclass 15, count 0 2006.196.08:14:32.71#ibcon#first serial, iclass 15, count 0 2006.196.08:14:32.71#ibcon#enter sib2, iclass 15, count 0 2006.196.08:14:32.71#ibcon#flushed, iclass 15, count 0 2006.196.08:14:32.71#ibcon#about to write, iclass 15, count 0 2006.196.08:14:32.71#ibcon#wrote, iclass 15, count 0 2006.196.08:14:32.71#ibcon#about to read 3, iclass 15, count 0 2006.196.08:14:32.73#ibcon#read 3, iclass 15, count 0 2006.196.08:14:32.73#ibcon#about to read 4, iclass 15, count 0 2006.196.08:14:32.73#ibcon#read 4, iclass 15, count 0 2006.196.08:14:32.73#ibcon#about to read 5, iclass 15, count 0 2006.196.08:14:32.73#ibcon#read 5, iclass 15, count 0 2006.196.08:14:32.73#ibcon#about to read 6, iclass 15, count 0 2006.196.08:14:32.73#ibcon#read 6, iclass 15, count 0 2006.196.08:14:32.73#ibcon#end of sib2, iclass 15, count 0 2006.196.08:14:32.73#ibcon#*mode == 0, iclass 15, count 0 2006.196.08:14:32.73#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.196.08:14:32.73#ibcon#[27=BW32\r\n] 2006.196.08:14:32.73#ibcon#*before write, iclass 15, count 0 2006.196.08:14:32.73#ibcon#enter sib2, iclass 15, count 0 2006.196.08:14:32.73#ibcon#flushed, iclass 15, count 0 2006.196.08:14:32.73#ibcon#about to write, iclass 15, count 0 2006.196.08:14:32.73#ibcon#wrote, iclass 15, count 0 2006.196.08:14:32.73#ibcon#about to read 3, iclass 15, count 0 2006.196.08:14:32.76#ibcon#read 3, iclass 15, count 0 2006.196.08:14:32.76#ibcon#about to read 4, iclass 15, count 0 2006.196.08:14:32.76#ibcon#read 4, iclass 15, count 0 2006.196.08:14:32.76#ibcon#about to read 5, iclass 15, count 0 2006.196.08:14:32.76#ibcon#read 5, iclass 15, count 0 2006.196.08:14:32.76#ibcon#about to read 6, iclass 15, count 0 2006.196.08:14:32.76#ibcon#read 6, iclass 15, count 0 2006.196.08:14:32.76#ibcon#end of sib2, iclass 15, count 0 2006.196.08:14:32.76#ibcon#*after write, iclass 15, count 0 2006.196.08:14:32.76#ibcon#*before return 0, iclass 15, count 0 2006.196.08:14:32.76#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.196.08:14:32.76#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.196.08:14:32.76#ibcon#about to clear, iclass 15 cls_cnt 0 2006.196.08:14:32.76#ibcon#cleared, iclass 15 cls_cnt 0 2006.196.08:14:32.76$4f8m12a/ifd4f 2006.196.08:14:32.76$ifd4f/lo= 2006.196.08:14:32.76$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.196.08:14:32.76$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.196.08:14:32.76$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.196.08:14:32.76$ifd4f/patch= 2006.196.08:14:32.76$ifd4f/patch=lo1,a1,a2,a3,a4 2006.196.08:14:32.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.196.08:14:32.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.196.08:14:32.76$4f8m12a/"form=m,16.000,1:2 2006.196.08:14:32.76$4f8m12a/"tpicd 2006.196.08:14:32.76$4f8m12a/echo=off 2006.196.08:14:32.76$4f8m12a/xlog=off 2006.196.08:14:32.76:!2006.196.08:15:00 2006.196.08:14:44.13#trakl#Source acquired 2006.196.08:14:44.13#flagr#flagr/antenna,acquired 2006.196.08:15:00.00:preob 2006.196.08:15:00.13/onsource/TRACKING 2006.196.08:15:00.13:!2006.196.08:15:10 2006.196.08:15:10.00:data_valid=on 2006.196.08:15:10.00:midob 2006.196.08:15:11.13/onsource/TRACKING 2006.196.08:15:11.13/wx/29.11,1003.9,89 2006.196.08:15:11.22/cable/+6.3380E-03 2006.196.08:15:12.31/va/01,08,usb,yes,29,31 2006.196.08:15:12.31/va/02,07,usb,yes,29,31 2006.196.08:15:12.31/va/03,06,usb,yes,31,31 2006.196.08:15:12.31/va/04,07,usb,yes,30,33 2006.196.08:15:12.31/va/05,07,usb,yes,33,35 2006.196.08:15:12.31/va/06,06,usb,yes,32,32 2006.196.08:15:12.31/va/07,06,usb,yes,32,32 2006.196.08:15:12.31/va/08,07,usb,yes,30,30 2006.196.08:15:12.54/valo/01,532.99,yes,locked 2006.196.08:15:12.54/valo/02,572.99,yes,locked 2006.196.08:15:12.54/valo/03,672.99,yes,locked 2006.196.08:15:12.54/valo/04,832.99,yes,locked 2006.196.08:15:12.54/valo/05,652.99,yes,locked 2006.196.08:15:12.54/valo/06,772.99,yes,locked 2006.196.08:15:12.54/valo/07,832.99,yes,locked 2006.196.08:15:12.54/valo/08,852.99,yes,locked 2006.196.08:15:13.63/vb/01,04,usb,yes,29,28 2006.196.08:15:13.63/vb/02,04,usb,yes,31,32 2006.196.08:15:13.63/vb/03,04,usb,yes,27,31 2006.196.08:15:13.63/vb/04,04,usb,yes,28,28 2006.196.08:15:13.63/vb/05,04,usb,yes,26,30 2006.196.08:15:13.63/vb/06,04,usb,yes,27,30 2006.196.08:15:13.63/vb/07,04,usb,yes,29,29 2006.196.08:15:13.63/vb/08,04,usb,yes,27,30 2006.196.08:15:13.87/vblo/01,632.99,yes,locked 2006.196.08:15:13.87/vblo/02,640.99,yes,locked 2006.196.08:15:13.87/vblo/03,656.99,yes,locked 2006.196.08:15:13.87/vblo/04,712.99,yes,locked 2006.196.08:15:13.87/vblo/05,744.99,yes,locked 2006.196.08:15:13.87/vblo/06,752.99,yes,locked 2006.196.08:15:13.87/vblo/07,734.99,yes,locked 2006.196.08:15:13.87/vblo/08,744.99,yes,locked 2006.196.08:15:14.02/vabw/8 2006.196.08:15:14.17/vbbw/8 2006.196.08:15:14.26/xfe/off,on,16.2 2006.196.08:15:14.64/ifatt/23,28,28,28 2006.196.08:15:15.07/fmout-gps/S +3.34E-07 2006.196.08:15:15.11:!2006.196.08:16:10 2006.196.08:16:10.00:data_valid=off 2006.196.08:16:10.00:postob 2006.196.08:16:10.09/cable/+6.3369E-03 2006.196.08:16:10.09/wx/29.08,1004.0,92 2006.196.08:16:11.06/fmout-gps/S +3.33E-07 2006.196.08:16:11.06:scan_name=196-0817,k06196,60 2006.196.08:16:11.06:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.196.08:16:11.13#flagr#flagr/antenna,new-source 2006.196.08:16:12.13:checkk5 2006.196.08:16:12.50/chk_autoobs//k5ts1/ autoobs is running! 2006.196.08:16:12.88/chk_autoobs//k5ts2/ autoobs is running! 2006.196.08:16:13.26/chk_autoobs//k5ts3/ autoobs is running! 2006.196.08:16:13.63/chk_autoobs//k5ts4/ autoobs is running! 2006.196.08:16:13.99/chk_obsdata//k5ts1/T1960815??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.08:16:14.36/chk_obsdata//k5ts2/T1960815??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.08:16:14.74/chk_obsdata//k5ts3/T1960815??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.08:16:15.11/chk_obsdata//k5ts4/T1960815??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.08:16:15.80/k5log//k5ts1_log_newline 2006.196.08:16:16.48/k5log//k5ts2_log_newline 2006.196.08:16:17.18/k5log//k5ts3_log_newline 2006.196.08:16:17.86/k5log//k5ts4_log_newline 2006.196.08:16:17.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.196.08:16:17.89:4f8m12a=2 2006.196.08:16:17.89$4f8m12a/echo=on 2006.196.08:16:17.89$4f8m12a/pcalon 2006.196.08:16:17.89$pcalon/"no phase cal control is implemented here 2006.196.08:16:17.89$4f8m12a/"tpicd=stop 2006.196.08:16:17.89$4f8m12a/vc4f8 2006.196.08:16:17.89$vc4f8/valo=1,532.99 2006.196.08:16:17.89#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.196.08:16:17.89#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.196.08:16:17.89#ibcon#ireg 17 cls_cnt 0 2006.196.08:16:17.89#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.196.08:16:17.89#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.196.08:16:17.89#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.196.08:16:17.89#ibcon#enter wrdev, iclass 26, count 0 2006.196.08:16:17.89#ibcon#first serial, iclass 26, count 0 2006.196.08:16:17.89#ibcon#enter sib2, iclass 26, count 0 2006.196.08:16:17.89#ibcon#flushed, iclass 26, count 0 2006.196.08:16:17.89#ibcon#about to write, iclass 26, count 0 2006.196.08:16:17.89#ibcon#wrote, iclass 26, count 0 2006.196.08:16:17.89#ibcon#about to read 3, iclass 26, count 0 2006.196.08:16:17.93#ibcon#read 3, iclass 26, count 0 2006.196.08:16:17.93#ibcon#about to read 4, iclass 26, count 0 2006.196.08:16:17.93#ibcon#read 4, iclass 26, count 0 2006.196.08:16:17.93#ibcon#about to read 5, iclass 26, count 0 2006.196.08:16:17.93#ibcon#read 5, iclass 26, count 0 2006.196.08:16:17.93#ibcon#about to read 6, iclass 26, count 0 2006.196.08:16:17.93#ibcon#read 6, iclass 26, count 0 2006.196.08:16:17.93#ibcon#end of sib2, iclass 26, count 0 2006.196.08:16:17.93#ibcon#*mode == 0, iclass 26, count 0 2006.196.08:16:17.93#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.196.08:16:17.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.196.08:16:17.93#ibcon#*before write, iclass 26, count 0 2006.196.08:16:17.93#ibcon#enter sib2, iclass 26, count 0 2006.196.08:16:17.93#ibcon#flushed, iclass 26, count 0 2006.196.08:16:17.93#ibcon#about to write, iclass 26, count 0 2006.196.08:16:17.93#ibcon#wrote, iclass 26, count 0 2006.196.08:16:17.93#ibcon#about to read 3, iclass 26, count 0 2006.196.08:16:17.98#ibcon#read 3, iclass 26, count 0 2006.196.08:16:17.98#ibcon#about to read 4, iclass 26, count 0 2006.196.08:16:17.98#ibcon#read 4, iclass 26, count 0 2006.196.08:16:17.98#ibcon#about to read 5, iclass 26, count 0 2006.196.08:16:17.98#ibcon#read 5, iclass 26, count 0 2006.196.08:16:17.98#ibcon#about to read 6, iclass 26, count 0 2006.196.08:16:17.98#ibcon#read 6, iclass 26, count 0 2006.196.08:16:17.98#ibcon#end of sib2, iclass 26, count 0 2006.196.08:16:17.98#ibcon#*after write, iclass 26, count 0 2006.196.08:16:17.98#ibcon#*before return 0, iclass 26, count 0 2006.196.08:16:17.98#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.196.08:16:17.98#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.196.08:16:17.98#ibcon#about to clear, iclass 26 cls_cnt 0 2006.196.08:16:17.98#ibcon#cleared, iclass 26 cls_cnt 0 2006.196.08:16:17.98$vc4f8/va=1,8 2006.196.08:16:17.98#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.196.08:16:17.98#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.196.08:16:17.98#ibcon#ireg 11 cls_cnt 2 2006.196.08:16:17.98#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.196.08:16:17.98#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.196.08:16:17.98#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.196.08:16:17.98#ibcon#enter wrdev, iclass 28, count 2 2006.196.08:16:17.98#ibcon#first serial, iclass 28, count 2 2006.196.08:16:17.98#ibcon#enter sib2, iclass 28, count 2 2006.196.08:16:17.98#ibcon#flushed, iclass 28, count 2 2006.196.08:16:17.98#ibcon#about to write, iclass 28, count 2 2006.196.08:16:17.98#ibcon#wrote, iclass 28, count 2 2006.196.08:16:17.98#ibcon#about to read 3, iclass 28, count 2 2006.196.08:16:18.00#ibcon#read 3, iclass 28, count 2 2006.196.08:16:18.00#ibcon#about to read 4, iclass 28, count 2 2006.196.08:16:18.00#ibcon#read 4, iclass 28, count 2 2006.196.08:16:18.00#ibcon#about to read 5, iclass 28, count 2 2006.196.08:16:18.00#ibcon#read 5, iclass 28, count 2 2006.196.08:16:18.00#ibcon#about to read 6, iclass 28, count 2 2006.196.08:16:18.00#ibcon#read 6, iclass 28, count 2 2006.196.08:16:18.00#ibcon#end of sib2, iclass 28, count 2 2006.196.08:16:18.00#ibcon#*mode == 0, iclass 28, count 2 2006.196.08:16:18.00#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.196.08:16:18.00#ibcon#[25=AT01-08\r\n] 2006.196.08:16:18.00#ibcon#*before write, iclass 28, count 2 2006.196.08:16:18.00#ibcon#enter sib2, iclass 28, count 2 2006.196.08:16:18.00#ibcon#flushed, iclass 28, count 2 2006.196.08:16:18.00#ibcon#about to write, iclass 28, count 2 2006.196.08:16:18.00#ibcon#wrote, iclass 28, count 2 2006.196.08:16:18.00#ibcon#about to read 3, iclass 28, count 2 2006.196.08:16:18.03#ibcon#read 3, iclass 28, count 2 2006.196.08:16:18.03#ibcon#about to read 4, iclass 28, count 2 2006.196.08:16:18.03#ibcon#read 4, iclass 28, count 2 2006.196.08:16:18.03#ibcon#about to read 5, iclass 28, count 2 2006.196.08:16:18.03#ibcon#read 5, iclass 28, count 2 2006.196.08:16:18.03#ibcon#about to read 6, iclass 28, count 2 2006.196.08:16:18.03#ibcon#read 6, iclass 28, count 2 2006.196.08:16:18.03#ibcon#end of sib2, iclass 28, count 2 2006.196.08:16:18.03#ibcon#*after write, iclass 28, count 2 2006.196.08:16:18.03#ibcon#*before return 0, iclass 28, count 2 2006.196.08:16:18.03#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.196.08:16:18.03#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.196.08:16:18.03#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.196.08:16:18.03#ibcon#ireg 7 cls_cnt 0 2006.196.08:16:18.03#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.196.08:16:18.15#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.196.08:16:18.15#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.196.08:16:18.15#ibcon#enter wrdev, iclass 28, count 0 2006.196.08:16:18.15#ibcon#first serial, iclass 28, count 0 2006.196.08:16:18.15#ibcon#enter sib2, iclass 28, count 0 2006.196.08:16:18.15#ibcon#flushed, iclass 28, count 0 2006.196.08:16:18.15#ibcon#about to write, iclass 28, count 0 2006.196.08:16:18.15#ibcon#wrote, iclass 28, count 0 2006.196.08:16:18.15#ibcon#about to read 3, iclass 28, count 0 2006.196.08:16:18.17#ibcon#read 3, iclass 28, count 0 2006.196.08:16:18.17#ibcon#about to read 4, iclass 28, count 0 2006.196.08:16:18.17#ibcon#read 4, iclass 28, count 0 2006.196.08:16:18.17#ibcon#about to read 5, iclass 28, count 0 2006.196.08:16:18.17#ibcon#read 5, iclass 28, count 0 2006.196.08:16:18.17#ibcon#about to read 6, iclass 28, count 0 2006.196.08:16:18.17#ibcon#read 6, iclass 28, count 0 2006.196.08:16:18.17#ibcon#end of sib2, iclass 28, count 0 2006.196.08:16:18.17#ibcon#*mode == 0, iclass 28, count 0 2006.196.08:16:18.17#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.196.08:16:18.17#ibcon#[25=USB\r\n] 2006.196.08:16:18.17#ibcon#*before write, iclass 28, count 0 2006.196.08:16:18.17#ibcon#enter sib2, iclass 28, count 0 2006.196.08:16:18.17#ibcon#flushed, iclass 28, count 0 2006.196.08:16:18.17#ibcon#about to write, iclass 28, count 0 2006.196.08:16:18.17#ibcon#wrote, iclass 28, count 0 2006.196.08:16:18.17#ibcon#about to read 3, iclass 28, count 0 2006.196.08:16:18.20#ibcon#read 3, iclass 28, count 0 2006.196.08:16:18.20#ibcon#about to read 4, iclass 28, count 0 2006.196.08:16:18.20#ibcon#read 4, iclass 28, count 0 2006.196.08:16:18.20#ibcon#about to read 5, iclass 28, count 0 2006.196.08:16:18.20#ibcon#read 5, iclass 28, count 0 2006.196.08:16:18.20#ibcon#about to read 6, iclass 28, count 0 2006.196.08:16:18.20#ibcon#read 6, iclass 28, count 0 2006.196.08:16:18.20#ibcon#end of sib2, iclass 28, count 0 2006.196.08:16:18.20#ibcon#*after write, iclass 28, count 0 2006.196.08:16:18.20#ibcon#*before return 0, iclass 28, count 0 2006.196.08:16:18.20#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.196.08:16:18.20#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.196.08:16:18.20#ibcon#about to clear, iclass 28 cls_cnt 0 2006.196.08:16:18.20#ibcon#cleared, iclass 28 cls_cnt 0 2006.196.08:16:18.20$vc4f8/valo=2,572.99 2006.196.08:16:18.20#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.196.08:16:18.20#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.196.08:16:18.20#ibcon#ireg 17 cls_cnt 0 2006.196.08:16:18.20#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.196.08:16:18.20#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.196.08:16:18.20#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.196.08:16:18.20#ibcon#enter wrdev, iclass 30, count 0 2006.196.08:16:18.20#ibcon#first serial, iclass 30, count 0 2006.196.08:16:18.20#ibcon#enter sib2, iclass 30, count 0 2006.196.08:16:18.20#ibcon#flushed, iclass 30, count 0 2006.196.08:16:18.20#ibcon#about to write, iclass 30, count 0 2006.196.08:16:18.20#ibcon#wrote, iclass 30, count 0 2006.196.08:16:18.20#ibcon#about to read 3, iclass 30, count 0 2006.196.08:16:18.22#ibcon#read 3, iclass 30, count 0 2006.196.08:16:18.22#ibcon#about to read 4, iclass 30, count 0 2006.196.08:16:18.22#ibcon#read 4, iclass 30, count 0 2006.196.08:16:18.22#ibcon#about to read 5, iclass 30, count 0 2006.196.08:16:18.22#ibcon#read 5, iclass 30, count 0 2006.196.08:16:18.22#ibcon#about to read 6, iclass 30, count 0 2006.196.08:16:18.22#ibcon#read 6, iclass 30, count 0 2006.196.08:16:18.22#ibcon#end of sib2, iclass 30, count 0 2006.196.08:16:18.22#ibcon#*mode == 0, iclass 30, count 0 2006.196.08:16:18.22#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.196.08:16:18.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.196.08:16:18.22#ibcon#*before write, iclass 30, count 0 2006.196.08:16:18.22#ibcon#enter sib2, iclass 30, count 0 2006.196.08:16:18.22#ibcon#flushed, iclass 30, count 0 2006.196.08:16:18.22#ibcon#about to write, iclass 30, count 0 2006.196.08:16:18.22#ibcon#wrote, iclass 30, count 0 2006.196.08:16:18.22#ibcon#about to read 3, iclass 30, count 0 2006.196.08:16:18.26#ibcon#read 3, iclass 30, count 0 2006.196.08:16:18.26#ibcon#about to read 4, iclass 30, count 0 2006.196.08:16:18.26#ibcon#read 4, iclass 30, count 0 2006.196.08:16:18.26#ibcon#about to read 5, iclass 30, count 0 2006.196.08:16:18.26#ibcon#read 5, iclass 30, count 0 2006.196.08:16:18.26#ibcon#about to read 6, iclass 30, count 0 2006.196.08:16:18.26#ibcon#read 6, iclass 30, count 0 2006.196.08:16:18.26#ibcon#end of sib2, iclass 30, count 0 2006.196.08:16:18.26#ibcon#*after write, iclass 30, count 0 2006.196.08:16:18.26#ibcon#*before return 0, iclass 30, count 0 2006.196.08:16:18.26#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.196.08:16:18.26#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.196.08:16:18.26#ibcon#about to clear, iclass 30 cls_cnt 0 2006.196.08:16:18.26#ibcon#cleared, iclass 30 cls_cnt 0 2006.196.08:16:18.26$vc4f8/va=2,7 2006.196.08:16:18.26#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.196.08:16:18.26#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.196.08:16:18.26#ibcon#ireg 11 cls_cnt 2 2006.196.08:16:18.26#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.196.08:16:18.32#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.196.08:16:18.32#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.196.08:16:18.32#ibcon#enter wrdev, iclass 32, count 2 2006.196.08:16:18.32#ibcon#first serial, iclass 32, count 2 2006.196.08:16:18.32#ibcon#enter sib2, iclass 32, count 2 2006.196.08:16:18.32#ibcon#flushed, iclass 32, count 2 2006.196.08:16:18.32#ibcon#about to write, iclass 32, count 2 2006.196.08:16:18.32#ibcon#wrote, iclass 32, count 2 2006.196.08:16:18.32#ibcon#about to read 3, iclass 32, count 2 2006.196.08:16:18.34#ibcon#read 3, iclass 32, count 2 2006.196.08:16:18.34#ibcon#about to read 4, iclass 32, count 2 2006.196.08:16:18.34#ibcon#read 4, iclass 32, count 2 2006.196.08:16:18.34#ibcon#about to read 5, iclass 32, count 2 2006.196.08:16:18.34#ibcon#read 5, iclass 32, count 2 2006.196.08:16:18.34#ibcon#about to read 6, iclass 32, count 2 2006.196.08:16:18.34#ibcon#read 6, iclass 32, count 2 2006.196.08:16:18.34#ibcon#end of sib2, iclass 32, count 2 2006.196.08:16:18.34#ibcon#*mode == 0, iclass 32, count 2 2006.196.08:16:18.34#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.196.08:16:18.34#ibcon#[25=AT02-07\r\n] 2006.196.08:16:18.34#ibcon#*before write, iclass 32, count 2 2006.196.08:16:18.34#ibcon#enter sib2, iclass 32, count 2 2006.196.08:16:18.34#ibcon#flushed, iclass 32, count 2 2006.196.08:16:18.34#ibcon#about to write, iclass 32, count 2 2006.196.08:16:18.34#ibcon#wrote, iclass 32, count 2 2006.196.08:16:18.34#ibcon#about to read 3, iclass 32, count 2 2006.196.08:16:18.37#ibcon#read 3, iclass 32, count 2 2006.196.08:16:18.37#ibcon#about to read 4, iclass 32, count 2 2006.196.08:16:18.37#ibcon#read 4, iclass 32, count 2 2006.196.08:16:18.37#ibcon#about to read 5, iclass 32, count 2 2006.196.08:16:18.37#ibcon#read 5, iclass 32, count 2 2006.196.08:16:18.37#ibcon#about to read 6, iclass 32, count 2 2006.196.08:16:18.37#ibcon#read 6, iclass 32, count 2 2006.196.08:16:18.37#ibcon#end of sib2, iclass 32, count 2 2006.196.08:16:18.37#ibcon#*after write, iclass 32, count 2 2006.196.08:16:18.37#ibcon#*before return 0, iclass 32, count 2 2006.196.08:16:18.37#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.196.08:16:18.37#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.196.08:16:18.37#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.196.08:16:18.37#ibcon#ireg 7 cls_cnt 0 2006.196.08:16:18.37#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.196.08:16:18.49#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.196.08:16:18.49#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.196.08:16:18.49#ibcon#enter wrdev, iclass 32, count 0 2006.196.08:16:18.49#ibcon#first serial, iclass 32, count 0 2006.196.08:16:18.49#ibcon#enter sib2, iclass 32, count 0 2006.196.08:16:18.49#ibcon#flushed, iclass 32, count 0 2006.196.08:16:18.49#ibcon#about to write, iclass 32, count 0 2006.196.08:16:18.49#ibcon#wrote, iclass 32, count 0 2006.196.08:16:18.49#ibcon#about to read 3, iclass 32, count 0 2006.196.08:16:18.51#ibcon#read 3, iclass 32, count 0 2006.196.08:16:18.51#ibcon#about to read 4, iclass 32, count 0 2006.196.08:16:18.51#ibcon#read 4, iclass 32, count 0 2006.196.08:16:18.51#ibcon#about to read 5, iclass 32, count 0 2006.196.08:16:18.51#ibcon#read 5, iclass 32, count 0 2006.196.08:16:18.51#ibcon#about to read 6, iclass 32, count 0 2006.196.08:16:18.51#ibcon#read 6, iclass 32, count 0 2006.196.08:16:18.51#ibcon#end of sib2, iclass 32, count 0 2006.196.08:16:18.51#ibcon#*mode == 0, iclass 32, count 0 2006.196.08:16:18.51#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.196.08:16:18.51#ibcon#[25=USB\r\n] 2006.196.08:16:18.51#ibcon#*before write, iclass 32, count 0 2006.196.08:16:18.51#ibcon#enter sib2, iclass 32, count 0 2006.196.08:16:18.51#ibcon#flushed, iclass 32, count 0 2006.196.08:16:18.51#ibcon#about to write, iclass 32, count 0 2006.196.08:16:18.51#ibcon#wrote, iclass 32, count 0 2006.196.08:16:18.51#ibcon#about to read 3, iclass 32, count 0 2006.196.08:16:18.54#ibcon#read 3, iclass 32, count 0 2006.196.08:16:18.54#ibcon#about to read 4, iclass 32, count 0 2006.196.08:16:18.54#ibcon#read 4, iclass 32, count 0 2006.196.08:16:18.54#ibcon#about to read 5, iclass 32, count 0 2006.196.08:16:18.54#ibcon#read 5, iclass 32, count 0 2006.196.08:16:18.54#ibcon#about to read 6, iclass 32, count 0 2006.196.08:16:18.54#ibcon#read 6, iclass 32, count 0 2006.196.08:16:18.54#ibcon#end of sib2, iclass 32, count 0 2006.196.08:16:18.54#ibcon#*after write, iclass 32, count 0 2006.196.08:16:18.54#ibcon#*before return 0, iclass 32, count 0 2006.196.08:16:18.54#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.196.08:16:18.54#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.196.08:16:18.54#ibcon#about to clear, iclass 32 cls_cnt 0 2006.196.08:16:18.54#ibcon#cleared, iclass 32 cls_cnt 0 2006.196.08:16:18.54$vc4f8/valo=3,672.99 2006.196.08:16:18.54#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.196.08:16:18.54#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.196.08:16:18.54#ibcon#ireg 17 cls_cnt 0 2006.196.08:16:18.54#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.196.08:16:18.54#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.196.08:16:18.54#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.196.08:16:18.54#ibcon#enter wrdev, iclass 34, count 0 2006.196.08:16:18.54#ibcon#first serial, iclass 34, count 0 2006.196.08:16:18.54#ibcon#enter sib2, iclass 34, count 0 2006.196.08:16:18.54#ibcon#flushed, iclass 34, count 0 2006.196.08:16:18.54#ibcon#about to write, iclass 34, count 0 2006.196.08:16:18.54#ibcon#wrote, iclass 34, count 0 2006.196.08:16:18.54#ibcon#about to read 3, iclass 34, count 0 2006.196.08:16:18.56#ibcon#read 3, iclass 34, count 0 2006.196.08:16:18.56#ibcon#about to read 4, iclass 34, count 0 2006.196.08:16:18.56#ibcon#read 4, iclass 34, count 0 2006.196.08:16:18.56#ibcon#about to read 5, iclass 34, count 0 2006.196.08:16:18.56#ibcon#read 5, iclass 34, count 0 2006.196.08:16:18.56#ibcon#about to read 6, iclass 34, count 0 2006.196.08:16:18.56#ibcon#read 6, iclass 34, count 0 2006.196.08:16:18.56#ibcon#end of sib2, iclass 34, count 0 2006.196.08:16:18.56#ibcon#*mode == 0, iclass 34, count 0 2006.196.08:16:18.56#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.196.08:16:18.56#ibcon#[26=FRQ=03,672.99\r\n] 2006.196.08:16:18.56#ibcon#*before write, iclass 34, count 0 2006.196.08:16:18.56#ibcon#enter sib2, iclass 34, count 0 2006.196.08:16:18.56#ibcon#flushed, iclass 34, count 0 2006.196.08:16:18.56#ibcon#about to write, iclass 34, count 0 2006.196.08:16:18.56#ibcon#wrote, iclass 34, count 0 2006.196.08:16:18.56#ibcon#about to read 3, iclass 34, count 0 2006.196.08:16:18.60#ibcon#read 3, iclass 34, count 0 2006.196.08:16:18.60#ibcon#about to read 4, iclass 34, count 0 2006.196.08:16:18.60#ibcon#read 4, iclass 34, count 0 2006.196.08:16:18.60#ibcon#about to read 5, iclass 34, count 0 2006.196.08:16:18.60#ibcon#read 5, iclass 34, count 0 2006.196.08:16:18.60#ibcon#about to read 6, iclass 34, count 0 2006.196.08:16:18.60#ibcon#read 6, iclass 34, count 0 2006.196.08:16:18.60#ibcon#end of sib2, iclass 34, count 0 2006.196.08:16:18.60#ibcon#*after write, iclass 34, count 0 2006.196.08:16:18.60#ibcon#*before return 0, iclass 34, count 0 2006.196.08:16:18.60#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.196.08:16:18.60#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.196.08:16:18.60#ibcon#about to clear, iclass 34 cls_cnt 0 2006.196.08:16:18.60#ibcon#cleared, iclass 34 cls_cnt 0 2006.196.08:16:18.60$vc4f8/va=3,6 2006.196.08:16:18.60#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.196.08:16:18.60#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.196.08:16:18.60#ibcon#ireg 11 cls_cnt 2 2006.196.08:16:18.60#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.196.08:16:18.66#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.196.08:16:18.66#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.196.08:16:18.66#ibcon#enter wrdev, iclass 36, count 2 2006.196.08:16:18.66#ibcon#first serial, iclass 36, count 2 2006.196.08:16:18.66#ibcon#enter sib2, iclass 36, count 2 2006.196.08:16:18.66#ibcon#flushed, iclass 36, count 2 2006.196.08:16:18.66#ibcon#about to write, iclass 36, count 2 2006.196.08:16:18.66#ibcon#wrote, iclass 36, count 2 2006.196.08:16:18.66#ibcon#about to read 3, iclass 36, count 2 2006.196.08:16:18.68#ibcon#read 3, iclass 36, count 2 2006.196.08:16:18.68#ibcon#about to read 4, iclass 36, count 2 2006.196.08:16:18.68#ibcon#read 4, iclass 36, count 2 2006.196.08:16:18.68#ibcon#about to read 5, iclass 36, count 2 2006.196.08:16:18.68#ibcon#read 5, iclass 36, count 2 2006.196.08:16:18.68#ibcon#about to read 6, iclass 36, count 2 2006.196.08:16:18.68#ibcon#read 6, iclass 36, count 2 2006.196.08:16:18.68#ibcon#end of sib2, iclass 36, count 2 2006.196.08:16:18.68#ibcon#*mode == 0, iclass 36, count 2 2006.196.08:16:18.68#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.196.08:16:18.68#ibcon#[25=AT03-06\r\n] 2006.196.08:16:18.68#ibcon#*before write, iclass 36, count 2 2006.196.08:16:18.68#ibcon#enter sib2, iclass 36, count 2 2006.196.08:16:18.68#ibcon#flushed, iclass 36, count 2 2006.196.08:16:18.68#ibcon#about to write, iclass 36, count 2 2006.196.08:16:18.68#ibcon#wrote, iclass 36, count 2 2006.196.08:16:18.68#ibcon#about to read 3, iclass 36, count 2 2006.196.08:16:18.72#ibcon#read 3, iclass 36, count 2 2006.196.08:16:18.72#ibcon#about to read 4, iclass 36, count 2 2006.196.08:16:18.72#ibcon#read 4, iclass 36, count 2 2006.196.08:16:18.72#ibcon#about to read 5, iclass 36, count 2 2006.196.08:16:18.72#ibcon#read 5, iclass 36, count 2 2006.196.08:16:18.72#ibcon#about to read 6, iclass 36, count 2 2006.196.08:16:18.72#ibcon#read 6, iclass 36, count 2 2006.196.08:16:18.72#ibcon#end of sib2, iclass 36, count 2 2006.196.08:16:18.72#ibcon#*after write, iclass 36, count 2 2006.196.08:16:18.72#ibcon#*before return 0, iclass 36, count 2 2006.196.08:16:18.72#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.196.08:16:18.72#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.196.08:16:18.72#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.196.08:16:18.72#ibcon#ireg 7 cls_cnt 0 2006.196.08:16:18.72#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.196.08:16:18.84#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.196.08:16:18.84#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.196.08:16:18.84#ibcon#enter wrdev, iclass 36, count 0 2006.196.08:16:18.84#ibcon#first serial, iclass 36, count 0 2006.196.08:16:18.84#ibcon#enter sib2, iclass 36, count 0 2006.196.08:16:18.84#ibcon#flushed, iclass 36, count 0 2006.196.08:16:18.84#ibcon#about to write, iclass 36, count 0 2006.196.08:16:18.84#ibcon#wrote, iclass 36, count 0 2006.196.08:16:18.84#ibcon#about to read 3, iclass 36, count 0 2006.196.08:16:18.86#ibcon#read 3, iclass 36, count 0 2006.196.08:16:18.86#ibcon#about to read 4, iclass 36, count 0 2006.196.08:16:18.86#ibcon#read 4, iclass 36, count 0 2006.196.08:16:18.86#ibcon#about to read 5, iclass 36, count 0 2006.196.08:16:18.86#ibcon#read 5, iclass 36, count 0 2006.196.08:16:18.86#ibcon#about to read 6, iclass 36, count 0 2006.196.08:16:18.86#ibcon#read 6, iclass 36, count 0 2006.196.08:16:18.86#ibcon#end of sib2, iclass 36, count 0 2006.196.08:16:18.86#ibcon#*mode == 0, iclass 36, count 0 2006.196.08:16:18.86#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.196.08:16:18.86#ibcon#[25=USB\r\n] 2006.196.08:16:18.86#ibcon#*before write, iclass 36, count 0 2006.196.08:16:18.86#ibcon#enter sib2, iclass 36, count 0 2006.196.08:16:18.86#ibcon#flushed, iclass 36, count 0 2006.196.08:16:18.86#ibcon#about to write, iclass 36, count 0 2006.196.08:16:18.86#ibcon#wrote, iclass 36, count 0 2006.196.08:16:18.86#ibcon#about to read 3, iclass 36, count 0 2006.196.08:16:18.89#ibcon#read 3, iclass 36, count 0 2006.196.08:16:18.89#ibcon#about to read 4, iclass 36, count 0 2006.196.08:16:18.89#ibcon#read 4, iclass 36, count 0 2006.196.08:16:18.89#ibcon#about to read 5, iclass 36, count 0 2006.196.08:16:18.89#ibcon#read 5, iclass 36, count 0 2006.196.08:16:18.89#ibcon#about to read 6, iclass 36, count 0 2006.196.08:16:18.89#ibcon#read 6, iclass 36, count 0 2006.196.08:16:18.89#ibcon#end of sib2, iclass 36, count 0 2006.196.08:16:18.89#ibcon#*after write, iclass 36, count 0 2006.196.08:16:18.89#ibcon#*before return 0, iclass 36, count 0 2006.196.08:16:18.89#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.196.08:16:18.89#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.196.08:16:18.89#ibcon#about to clear, iclass 36 cls_cnt 0 2006.196.08:16:18.89#ibcon#cleared, iclass 36 cls_cnt 0 2006.196.08:16:18.89$vc4f8/valo=4,832.99 2006.196.08:16:18.89#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.196.08:16:18.89#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.196.08:16:18.89#ibcon#ireg 17 cls_cnt 0 2006.196.08:16:18.89#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.196.08:16:18.89#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.196.08:16:18.89#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.196.08:16:18.89#ibcon#enter wrdev, iclass 38, count 0 2006.196.08:16:18.89#ibcon#first serial, iclass 38, count 0 2006.196.08:16:18.89#ibcon#enter sib2, iclass 38, count 0 2006.196.08:16:18.89#ibcon#flushed, iclass 38, count 0 2006.196.08:16:18.89#ibcon#about to write, iclass 38, count 0 2006.196.08:16:18.89#ibcon#wrote, iclass 38, count 0 2006.196.08:16:18.89#ibcon#about to read 3, iclass 38, count 0 2006.196.08:16:18.91#ibcon#read 3, iclass 38, count 0 2006.196.08:16:18.91#ibcon#about to read 4, iclass 38, count 0 2006.196.08:16:18.91#ibcon#read 4, iclass 38, count 0 2006.196.08:16:18.91#ibcon#about to read 5, iclass 38, count 0 2006.196.08:16:18.91#ibcon#read 5, iclass 38, count 0 2006.196.08:16:18.91#ibcon#about to read 6, iclass 38, count 0 2006.196.08:16:18.91#ibcon#read 6, iclass 38, count 0 2006.196.08:16:18.91#ibcon#end of sib2, iclass 38, count 0 2006.196.08:16:18.91#ibcon#*mode == 0, iclass 38, count 0 2006.196.08:16:18.91#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.196.08:16:18.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.196.08:16:18.91#ibcon#*before write, iclass 38, count 0 2006.196.08:16:18.91#ibcon#enter sib2, iclass 38, count 0 2006.196.08:16:18.91#ibcon#flushed, iclass 38, count 0 2006.196.08:16:18.91#ibcon#about to write, iclass 38, count 0 2006.196.08:16:18.91#ibcon#wrote, iclass 38, count 0 2006.196.08:16:18.91#ibcon#about to read 3, iclass 38, count 0 2006.196.08:16:18.95#ibcon#read 3, iclass 38, count 0 2006.196.08:16:18.95#ibcon#about to read 4, iclass 38, count 0 2006.196.08:16:18.95#ibcon#read 4, iclass 38, count 0 2006.196.08:16:18.95#ibcon#about to read 5, iclass 38, count 0 2006.196.08:16:18.95#ibcon#read 5, iclass 38, count 0 2006.196.08:16:18.95#ibcon#about to read 6, iclass 38, count 0 2006.196.08:16:18.95#ibcon#read 6, iclass 38, count 0 2006.196.08:16:18.95#ibcon#end of sib2, iclass 38, count 0 2006.196.08:16:18.95#ibcon#*after write, iclass 38, count 0 2006.196.08:16:18.95#ibcon#*before return 0, iclass 38, count 0 2006.196.08:16:18.95#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.196.08:16:18.95#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.196.08:16:18.95#ibcon#about to clear, iclass 38 cls_cnt 0 2006.196.08:16:18.95#ibcon#cleared, iclass 38 cls_cnt 0 2006.196.08:16:18.95$vc4f8/va=4,7 2006.196.08:16:18.95#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.196.08:16:18.95#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.196.08:16:18.95#ibcon#ireg 11 cls_cnt 2 2006.196.08:16:18.95#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.196.08:16:19.01#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.196.08:16:19.01#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.196.08:16:19.01#ibcon#enter wrdev, iclass 40, count 2 2006.196.08:16:19.01#ibcon#first serial, iclass 40, count 2 2006.196.08:16:19.01#ibcon#enter sib2, iclass 40, count 2 2006.196.08:16:19.01#ibcon#flushed, iclass 40, count 2 2006.196.08:16:19.01#ibcon#about to write, iclass 40, count 2 2006.196.08:16:19.01#ibcon#wrote, iclass 40, count 2 2006.196.08:16:19.01#ibcon#about to read 3, iclass 40, count 2 2006.196.08:16:19.03#ibcon#read 3, iclass 40, count 2 2006.196.08:16:19.03#ibcon#about to read 4, iclass 40, count 2 2006.196.08:16:19.03#ibcon#read 4, iclass 40, count 2 2006.196.08:16:19.03#ibcon#about to read 5, iclass 40, count 2 2006.196.08:16:19.03#ibcon#read 5, iclass 40, count 2 2006.196.08:16:19.03#ibcon#about to read 6, iclass 40, count 2 2006.196.08:16:19.03#ibcon#read 6, iclass 40, count 2 2006.196.08:16:19.03#ibcon#end of sib2, iclass 40, count 2 2006.196.08:16:19.03#ibcon#*mode == 0, iclass 40, count 2 2006.196.08:16:19.03#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.196.08:16:19.03#ibcon#[25=AT04-07\r\n] 2006.196.08:16:19.03#ibcon#*before write, iclass 40, count 2 2006.196.08:16:19.03#ibcon#enter sib2, iclass 40, count 2 2006.196.08:16:19.03#ibcon#flushed, iclass 40, count 2 2006.196.08:16:19.03#ibcon#about to write, iclass 40, count 2 2006.196.08:16:19.03#ibcon#wrote, iclass 40, count 2 2006.196.08:16:19.03#ibcon#about to read 3, iclass 40, count 2 2006.196.08:16:19.06#ibcon#read 3, iclass 40, count 2 2006.196.08:16:19.06#ibcon#about to read 4, iclass 40, count 2 2006.196.08:16:19.06#ibcon#read 4, iclass 40, count 2 2006.196.08:16:19.06#ibcon#about to read 5, iclass 40, count 2 2006.196.08:16:19.06#ibcon#read 5, iclass 40, count 2 2006.196.08:16:19.06#ibcon#about to read 6, iclass 40, count 2 2006.196.08:16:19.06#ibcon#read 6, iclass 40, count 2 2006.196.08:16:19.06#ibcon#end of sib2, iclass 40, count 2 2006.196.08:16:19.06#ibcon#*after write, iclass 40, count 2 2006.196.08:16:19.06#ibcon#*before return 0, iclass 40, count 2 2006.196.08:16:19.06#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.196.08:16:19.06#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.196.08:16:19.06#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.196.08:16:19.06#ibcon#ireg 7 cls_cnt 0 2006.196.08:16:19.06#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.196.08:16:19.18#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.196.08:16:19.18#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.196.08:16:19.18#ibcon#enter wrdev, iclass 40, count 0 2006.196.08:16:19.18#ibcon#first serial, iclass 40, count 0 2006.196.08:16:19.18#ibcon#enter sib2, iclass 40, count 0 2006.196.08:16:19.18#ibcon#flushed, iclass 40, count 0 2006.196.08:16:19.18#ibcon#about to write, iclass 40, count 0 2006.196.08:16:19.18#ibcon#wrote, iclass 40, count 0 2006.196.08:16:19.18#ibcon#about to read 3, iclass 40, count 0 2006.196.08:16:19.20#ibcon#read 3, iclass 40, count 0 2006.196.08:16:19.20#ibcon#about to read 4, iclass 40, count 0 2006.196.08:16:19.20#ibcon#read 4, iclass 40, count 0 2006.196.08:16:19.20#ibcon#about to read 5, iclass 40, count 0 2006.196.08:16:19.20#ibcon#read 5, iclass 40, count 0 2006.196.08:16:19.20#ibcon#about to read 6, iclass 40, count 0 2006.196.08:16:19.20#ibcon#read 6, iclass 40, count 0 2006.196.08:16:19.20#ibcon#end of sib2, iclass 40, count 0 2006.196.08:16:19.20#ibcon#*mode == 0, iclass 40, count 0 2006.196.08:16:19.20#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.196.08:16:19.20#ibcon#[25=USB\r\n] 2006.196.08:16:19.20#ibcon#*before write, iclass 40, count 0 2006.196.08:16:19.20#ibcon#enter sib2, iclass 40, count 0 2006.196.08:16:19.20#ibcon#flushed, iclass 40, count 0 2006.196.08:16:19.20#ibcon#about to write, iclass 40, count 0 2006.196.08:16:19.20#ibcon#wrote, iclass 40, count 0 2006.196.08:16:19.20#ibcon#about to read 3, iclass 40, count 0 2006.196.08:16:19.23#ibcon#read 3, iclass 40, count 0 2006.196.08:16:19.23#ibcon#about to read 4, iclass 40, count 0 2006.196.08:16:19.23#ibcon#read 4, iclass 40, count 0 2006.196.08:16:19.23#ibcon#about to read 5, iclass 40, count 0 2006.196.08:16:19.23#ibcon#read 5, iclass 40, count 0 2006.196.08:16:19.23#ibcon#about to read 6, iclass 40, count 0 2006.196.08:16:19.23#ibcon#read 6, iclass 40, count 0 2006.196.08:16:19.23#ibcon#end of sib2, iclass 40, count 0 2006.196.08:16:19.23#ibcon#*after write, iclass 40, count 0 2006.196.08:16:19.23#ibcon#*before return 0, iclass 40, count 0 2006.196.08:16:19.23#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.196.08:16:19.23#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.196.08:16:19.23#ibcon#about to clear, iclass 40 cls_cnt 0 2006.196.08:16:19.23#ibcon#cleared, iclass 40 cls_cnt 0 2006.196.08:16:19.23$vc4f8/valo=5,652.99 2006.196.08:16:19.23#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.196.08:16:19.23#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.196.08:16:19.23#ibcon#ireg 17 cls_cnt 0 2006.196.08:16:19.23#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.196.08:16:19.23#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.196.08:16:19.23#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.196.08:16:19.23#ibcon#enter wrdev, iclass 4, count 0 2006.196.08:16:19.23#ibcon#first serial, iclass 4, count 0 2006.196.08:16:19.23#ibcon#enter sib2, iclass 4, count 0 2006.196.08:16:19.23#ibcon#flushed, iclass 4, count 0 2006.196.08:16:19.23#ibcon#about to write, iclass 4, count 0 2006.196.08:16:19.23#ibcon#wrote, iclass 4, count 0 2006.196.08:16:19.23#ibcon#about to read 3, iclass 4, count 0 2006.196.08:16:19.25#ibcon#read 3, iclass 4, count 0 2006.196.08:16:19.25#ibcon#about to read 4, iclass 4, count 0 2006.196.08:16:19.25#ibcon#read 4, iclass 4, count 0 2006.196.08:16:19.25#ibcon#about to read 5, iclass 4, count 0 2006.196.08:16:19.25#ibcon#read 5, iclass 4, count 0 2006.196.08:16:19.25#ibcon#about to read 6, iclass 4, count 0 2006.196.08:16:19.25#ibcon#read 6, iclass 4, count 0 2006.196.08:16:19.25#ibcon#end of sib2, iclass 4, count 0 2006.196.08:16:19.25#ibcon#*mode == 0, iclass 4, count 0 2006.196.08:16:19.25#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.196.08:16:19.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.196.08:16:19.25#ibcon#*before write, iclass 4, count 0 2006.196.08:16:19.25#ibcon#enter sib2, iclass 4, count 0 2006.196.08:16:19.25#ibcon#flushed, iclass 4, count 0 2006.196.08:16:19.25#ibcon#about to write, iclass 4, count 0 2006.196.08:16:19.25#ibcon#wrote, iclass 4, count 0 2006.196.08:16:19.25#ibcon#about to read 3, iclass 4, count 0 2006.196.08:16:19.29#ibcon#read 3, iclass 4, count 0 2006.196.08:16:19.29#ibcon#about to read 4, iclass 4, count 0 2006.196.08:16:19.29#ibcon#read 4, iclass 4, count 0 2006.196.08:16:19.29#ibcon#about to read 5, iclass 4, count 0 2006.196.08:16:19.29#ibcon#read 5, iclass 4, count 0 2006.196.08:16:19.29#ibcon#about to read 6, iclass 4, count 0 2006.196.08:16:19.29#ibcon#read 6, iclass 4, count 0 2006.196.08:16:19.29#ibcon#end of sib2, iclass 4, count 0 2006.196.08:16:19.29#ibcon#*after write, iclass 4, count 0 2006.196.08:16:19.29#ibcon#*before return 0, iclass 4, count 0 2006.196.08:16:19.29#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.196.08:16:19.29#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.196.08:16:19.29#ibcon#about to clear, iclass 4 cls_cnt 0 2006.196.08:16:19.29#ibcon#cleared, iclass 4 cls_cnt 0 2006.196.08:16:19.29$vc4f8/va=5,7 2006.196.08:16:19.29#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.196.08:16:19.29#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.196.08:16:19.29#ibcon#ireg 11 cls_cnt 2 2006.196.08:16:19.29#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.196.08:16:19.35#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.196.08:16:19.35#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.196.08:16:19.35#ibcon#enter wrdev, iclass 6, count 2 2006.196.08:16:19.35#ibcon#first serial, iclass 6, count 2 2006.196.08:16:19.35#ibcon#enter sib2, iclass 6, count 2 2006.196.08:16:19.35#ibcon#flushed, iclass 6, count 2 2006.196.08:16:19.35#ibcon#about to write, iclass 6, count 2 2006.196.08:16:19.35#ibcon#wrote, iclass 6, count 2 2006.196.08:16:19.35#ibcon#about to read 3, iclass 6, count 2 2006.196.08:16:19.37#ibcon#read 3, iclass 6, count 2 2006.196.08:16:19.37#ibcon#about to read 4, iclass 6, count 2 2006.196.08:16:19.37#ibcon#read 4, iclass 6, count 2 2006.196.08:16:19.37#ibcon#about to read 5, iclass 6, count 2 2006.196.08:16:19.37#ibcon#read 5, iclass 6, count 2 2006.196.08:16:19.37#ibcon#about to read 6, iclass 6, count 2 2006.196.08:16:19.37#ibcon#read 6, iclass 6, count 2 2006.196.08:16:19.37#ibcon#end of sib2, iclass 6, count 2 2006.196.08:16:19.37#ibcon#*mode == 0, iclass 6, count 2 2006.196.08:16:19.37#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.196.08:16:19.37#ibcon#[25=AT05-07\r\n] 2006.196.08:16:19.37#ibcon#*before write, iclass 6, count 2 2006.196.08:16:19.37#ibcon#enter sib2, iclass 6, count 2 2006.196.08:16:19.37#ibcon#flushed, iclass 6, count 2 2006.196.08:16:19.37#ibcon#about to write, iclass 6, count 2 2006.196.08:16:19.37#ibcon#wrote, iclass 6, count 2 2006.196.08:16:19.37#ibcon#about to read 3, iclass 6, count 2 2006.196.08:16:19.40#ibcon#read 3, iclass 6, count 2 2006.196.08:16:19.40#ibcon#about to read 4, iclass 6, count 2 2006.196.08:16:19.40#ibcon#read 4, iclass 6, count 2 2006.196.08:16:19.40#ibcon#about to read 5, iclass 6, count 2 2006.196.08:16:19.40#ibcon#read 5, iclass 6, count 2 2006.196.08:16:19.40#ibcon#about to read 6, iclass 6, count 2 2006.196.08:16:19.40#ibcon#read 6, iclass 6, count 2 2006.196.08:16:19.40#ibcon#end of sib2, iclass 6, count 2 2006.196.08:16:19.40#ibcon#*after write, iclass 6, count 2 2006.196.08:16:19.40#ibcon#*before return 0, iclass 6, count 2 2006.196.08:16:19.40#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.196.08:16:19.40#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.196.08:16:19.40#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.196.08:16:19.40#ibcon#ireg 7 cls_cnt 0 2006.196.08:16:19.40#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.196.08:16:19.52#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.196.08:16:19.52#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.196.08:16:19.52#ibcon#enter wrdev, iclass 6, count 0 2006.196.08:16:19.52#ibcon#first serial, iclass 6, count 0 2006.196.08:16:19.52#ibcon#enter sib2, iclass 6, count 0 2006.196.08:16:19.52#ibcon#flushed, iclass 6, count 0 2006.196.08:16:19.52#ibcon#about to write, iclass 6, count 0 2006.196.08:16:19.52#ibcon#wrote, iclass 6, count 0 2006.196.08:16:19.52#ibcon#about to read 3, iclass 6, count 0 2006.196.08:16:19.54#ibcon#read 3, iclass 6, count 0 2006.196.08:16:19.54#ibcon#about to read 4, iclass 6, count 0 2006.196.08:16:19.54#ibcon#read 4, iclass 6, count 0 2006.196.08:16:19.54#ibcon#about to read 5, iclass 6, count 0 2006.196.08:16:19.54#ibcon#read 5, iclass 6, count 0 2006.196.08:16:19.54#ibcon#about to read 6, iclass 6, count 0 2006.196.08:16:19.54#ibcon#read 6, iclass 6, count 0 2006.196.08:16:19.54#ibcon#end of sib2, iclass 6, count 0 2006.196.08:16:19.54#ibcon#*mode == 0, iclass 6, count 0 2006.196.08:16:19.54#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.196.08:16:19.54#ibcon#[25=USB\r\n] 2006.196.08:16:19.54#ibcon#*before write, iclass 6, count 0 2006.196.08:16:19.54#ibcon#enter sib2, iclass 6, count 0 2006.196.08:16:19.54#ibcon#flushed, iclass 6, count 0 2006.196.08:16:19.54#ibcon#about to write, iclass 6, count 0 2006.196.08:16:19.54#ibcon#wrote, iclass 6, count 0 2006.196.08:16:19.54#ibcon#about to read 3, iclass 6, count 0 2006.196.08:16:19.57#ibcon#read 3, iclass 6, count 0 2006.196.08:16:19.57#ibcon#about to read 4, iclass 6, count 0 2006.196.08:16:19.57#ibcon#read 4, iclass 6, count 0 2006.196.08:16:19.57#ibcon#about to read 5, iclass 6, count 0 2006.196.08:16:19.57#ibcon#read 5, iclass 6, count 0 2006.196.08:16:19.57#ibcon#about to read 6, iclass 6, count 0 2006.196.08:16:19.57#ibcon#read 6, iclass 6, count 0 2006.196.08:16:19.57#ibcon#end of sib2, iclass 6, count 0 2006.196.08:16:19.57#ibcon#*after write, iclass 6, count 0 2006.196.08:16:19.57#ibcon#*before return 0, iclass 6, count 0 2006.196.08:16:19.57#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.196.08:16:19.57#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.196.08:16:19.57#ibcon#about to clear, iclass 6 cls_cnt 0 2006.196.08:16:19.57#ibcon#cleared, iclass 6 cls_cnt 0 2006.196.08:16:19.57$vc4f8/valo=6,772.99 2006.196.08:16:19.57#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.196.08:16:19.57#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.196.08:16:19.57#ibcon#ireg 17 cls_cnt 0 2006.196.08:16:19.57#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.196.08:16:19.57#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.196.08:16:19.57#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.196.08:16:19.57#ibcon#enter wrdev, iclass 10, count 0 2006.196.08:16:19.57#ibcon#first serial, iclass 10, count 0 2006.196.08:16:19.57#ibcon#enter sib2, iclass 10, count 0 2006.196.08:16:19.57#ibcon#flushed, iclass 10, count 0 2006.196.08:16:19.57#ibcon#about to write, iclass 10, count 0 2006.196.08:16:19.57#ibcon#wrote, iclass 10, count 0 2006.196.08:16:19.57#ibcon#about to read 3, iclass 10, count 0 2006.196.08:16:19.59#ibcon#read 3, iclass 10, count 0 2006.196.08:16:19.59#ibcon#about to read 4, iclass 10, count 0 2006.196.08:16:19.59#ibcon#read 4, iclass 10, count 0 2006.196.08:16:19.59#ibcon#about to read 5, iclass 10, count 0 2006.196.08:16:19.59#ibcon#read 5, iclass 10, count 0 2006.196.08:16:19.59#ibcon#about to read 6, iclass 10, count 0 2006.196.08:16:19.59#ibcon#read 6, iclass 10, count 0 2006.196.08:16:19.59#ibcon#end of sib2, iclass 10, count 0 2006.196.08:16:19.59#ibcon#*mode == 0, iclass 10, count 0 2006.196.08:16:19.59#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.196.08:16:19.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.196.08:16:19.59#ibcon#*before write, iclass 10, count 0 2006.196.08:16:19.59#ibcon#enter sib2, iclass 10, count 0 2006.196.08:16:19.59#ibcon#flushed, iclass 10, count 0 2006.196.08:16:19.59#ibcon#about to write, iclass 10, count 0 2006.196.08:16:19.59#ibcon#wrote, iclass 10, count 0 2006.196.08:16:19.59#ibcon#about to read 3, iclass 10, count 0 2006.196.08:16:19.64#ibcon#read 3, iclass 10, count 0 2006.196.08:16:19.64#ibcon#about to read 4, iclass 10, count 0 2006.196.08:16:19.64#ibcon#read 4, iclass 10, count 0 2006.196.08:16:19.64#ibcon#about to read 5, iclass 10, count 0 2006.196.08:16:19.64#ibcon#read 5, iclass 10, count 0 2006.196.08:16:19.64#ibcon#about to read 6, iclass 10, count 0 2006.196.08:16:19.64#ibcon#read 6, iclass 10, count 0 2006.196.08:16:19.64#ibcon#end of sib2, iclass 10, count 0 2006.196.08:16:19.64#ibcon#*after write, iclass 10, count 0 2006.196.08:16:19.64#ibcon#*before return 0, iclass 10, count 0 2006.196.08:16:19.64#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.196.08:16:19.64#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.196.08:16:19.64#ibcon#about to clear, iclass 10 cls_cnt 0 2006.196.08:16:19.64#ibcon#cleared, iclass 10 cls_cnt 0 2006.196.08:16:19.64$vc4f8/va=6,6 2006.196.08:16:19.64#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.196.08:16:19.64#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.196.08:16:19.64#ibcon#ireg 11 cls_cnt 2 2006.196.08:16:19.64#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.196.08:16:19.69#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.196.08:16:19.69#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.196.08:16:19.69#ibcon#enter wrdev, iclass 12, count 2 2006.196.08:16:19.69#ibcon#first serial, iclass 12, count 2 2006.196.08:16:19.69#ibcon#enter sib2, iclass 12, count 2 2006.196.08:16:19.69#ibcon#flushed, iclass 12, count 2 2006.196.08:16:19.69#ibcon#about to write, iclass 12, count 2 2006.196.08:16:19.69#ibcon#wrote, iclass 12, count 2 2006.196.08:16:19.69#ibcon#about to read 3, iclass 12, count 2 2006.196.08:16:19.71#ibcon#read 3, iclass 12, count 2 2006.196.08:16:19.71#ibcon#about to read 4, iclass 12, count 2 2006.196.08:16:19.71#ibcon#read 4, iclass 12, count 2 2006.196.08:16:19.71#ibcon#about to read 5, iclass 12, count 2 2006.196.08:16:19.71#ibcon#read 5, iclass 12, count 2 2006.196.08:16:19.71#ibcon#about to read 6, iclass 12, count 2 2006.196.08:16:19.71#ibcon#read 6, iclass 12, count 2 2006.196.08:16:19.71#ibcon#end of sib2, iclass 12, count 2 2006.196.08:16:19.71#ibcon#*mode == 0, iclass 12, count 2 2006.196.08:16:19.71#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.196.08:16:19.71#ibcon#[25=AT06-06\r\n] 2006.196.08:16:19.71#ibcon#*before write, iclass 12, count 2 2006.196.08:16:19.71#ibcon#enter sib2, iclass 12, count 2 2006.196.08:16:19.71#ibcon#flushed, iclass 12, count 2 2006.196.08:16:19.71#ibcon#about to write, iclass 12, count 2 2006.196.08:16:19.71#ibcon#wrote, iclass 12, count 2 2006.196.08:16:19.71#ibcon#about to read 3, iclass 12, count 2 2006.196.08:16:19.74#ibcon#read 3, iclass 12, count 2 2006.196.08:16:19.74#ibcon#about to read 4, iclass 12, count 2 2006.196.08:16:19.74#ibcon#read 4, iclass 12, count 2 2006.196.08:16:19.74#ibcon#about to read 5, iclass 12, count 2 2006.196.08:16:19.74#ibcon#read 5, iclass 12, count 2 2006.196.08:16:19.74#ibcon#about to read 6, iclass 12, count 2 2006.196.08:16:19.74#ibcon#read 6, iclass 12, count 2 2006.196.08:16:19.74#ibcon#end of sib2, iclass 12, count 2 2006.196.08:16:19.74#ibcon#*after write, iclass 12, count 2 2006.196.08:16:19.74#ibcon#*before return 0, iclass 12, count 2 2006.196.08:16:19.74#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.196.08:16:19.74#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.196.08:16:19.74#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.196.08:16:19.74#ibcon#ireg 7 cls_cnt 0 2006.196.08:16:19.74#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.196.08:16:19.86#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.196.08:16:19.86#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.196.08:16:19.86#ibcon#enter wrdev, iclass 12, count 0 2006.196.08:16:19.86#ibcon#first serial, iclass 12, count 0 2006.196.08:16:19.86#ibcon#enter sib2, iclass 12, count 0 2006.196.08:16:19.86#ibcon#flushed, iclass 12, count 0 2006.196.08:16:19.86#ibcon#about to write, iclass 12, count 0 2006.196.08:16:19.86#ibcon#wrote, iclass 12, count 0 2006.196.08:16:19.86#ibcon#about to read 3, iclass 12, count 0 2006.196.08:16:19.88#ibcon#read 3, iclass 12, count 0 2006.196.08:16:19.88#ibcon#about to read 4, iclass 12, count 0 2006.196.08:16:19.88#ibcon#read 4, iclass 12, count 0 2006.196.08:16:19.88#ibcon#about to read 5, iclass 12, count 0 2006.196.08:16:19.88#ibcon#read 5, iclass 12, count 0 2006.196.08:16:19.88#ibcon#about to read 6, iclass 12, count 0 2006.196.08:16:19.88#ibcon#read 6, iclass 12, count 0 2006.196.08:16:19.88#ibcon#end of sib2, iclass 12, count 0 2006.196.08:16:19.88#ibcon#*mode == 0, iclass 12, count 0 2006.196.08:16:19.88#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.196.08:16:19.88#ibcon#[25=USB\r\n] 2006.196.08:16:19.88#ibcon#*before write, iclass 12, count 0 2006.196.08:16:19.88#ibcon#enter sib2, iclass 12, count 0 2006.196.08:16:19.88#ibcon#flushed, iclass 12, count 0 2006.196.08:16:19.88#ibcon#about to write, iclass 12, count 0 2006.196.08:16:19.88#ibcon#wrote, iclass 12, count 0 2006.196.08:16:19.88#ibcon#about to read 3, iclass 12, count 0 2006.196.08:16:19.91#ibcon#read 3, iclass 12, count 0 2006.196.08:16:19.91#ibcon#about to read 4, iclass 12, count 0 2006.196.08:16:19.91#ibcon#read 4, iclass 12, count 0 2006.196.08:16:19.91#ibcon#about to read 5, iclass 12, count 0 2006.196.08:16:19.91#ibcon#read 5, iclass 12, count 0 2006.196.08:16:19.91#ibcon#about to read 6, iclass 12, count 0 2006.196.08:16:19.91#ibcon#read 6, iclass 12, count 0 2006.196.08:16:19.91#ibcon#end of sib2, iclass 12, count 0 2006.196.08:16:19.91#ibcon#*after write, iclass 12, count 0 2006.196.08:16:19.91#ibcon#*before return 0, iclass 12, count 0 2006.196.08:16:19.91#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.196.08:16:19.91#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.196.08:16:19.91#ibcon#about to clear, iclass 12 cls_cnt 0 2006.196.08:16:19.91#ibcon#cleared, iclass 12 cls_cnt 0 2006.196.08:16:19.91$vc4f8/valo=7,832.99 2006.196.08:16:19.91#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.196.08:16:19.91#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.196.08:16:19.91#ibcon#ireg 17 cls_cnt 0 2006.196.08:16:19.91#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.196.08:16:19.91#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.196.08:16:19.91#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.196.08:16:19.91#ibcon#enter wrdev, iclass 14, count 0 2006.196.08:16:19.91#ibcon#first serial, iclass 14, count 0 2006.196.08:16:19.91#ibcon#enter sib2, iclass 14, count 0 2006.196.08:16:19.91#ibcon#flushed, iclass 14, count 0 2006.196.08:16:19.91#ibcon#about to write, iclass 14, count 0 2006.196.08:16:19.91#ibcon#wrote, iclass 14, count 0 2006.196.08:16:19.91#ibcon#about to read 3, iclass 14, count 0 2006.196.08:16:19.93#ibcon#read 3, iclass 14, count 0 2006.196.08:16:19.93#ibcon#about to read 4, iclass 14, count 0 2006.196.08:16:19.93#ibcon#read 4, iclass 14, count 0 2006.196.08:16:19.93#ibcon#about to read 5, iclass 14, count 0 2006.196.08:16:19.93#ibcon#read 5, iclass 14, count 0 2006.196.08:16:19.93#ibcon#about to read 6, iclass 14, count 0 2006.196.08:16:19.93#ibcon#read 6, iclass 14, count 0 2006.196.08:16:19.93#ibcon#end of sib2, iclass 14, count 0 2006.196.08:16:19.93#ibcon#*mode == 0, iclass 14, count 0 2006.196.08:16:19.93#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.196.08:16:19.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.196.08:16:19.93#ibcon#*before write, iclass 14, count 0 2006.196.08:16:19.93#ibcon#enter sib2, iclass 14, count 0 2006.196.08:16:19.93#ibcon#flushed, iclass 14, count 0 2006.196.08:16:19.93#ibcon#about to write, iclass 14, count 0 2006.196.08:16:19.93#ibcon#wrote, iclass 14, count 0 2006.196.08:16:19.93#ibcon#about to read 3, iclass 14, count 0 2006.196.08:16:19.97#ibcon#read 3, iclass 14, count 0 2006.196.08:16:19.97#ibcon#about to read 4, iclass 14, count 0 2006.196.08:16:19.97#ibcon#read 4, iclass 14, count 0 2006.196.08:16:19.97#ibcon#about to read 5, iclass 14, count 0 2006.196.08:16:19.97#ibcon#read 5, iclass 14, count 0 2006.196.08:16:19.97#ibcon#about to read 6, iclass 14, count 0 2006.196.08:16:19.97#ibcon#read 6, iclass 14, count 0 2006.196.08:16:19.97#ibcon#end of sib2, iclass 14, count 0 2006.196.08:16:19.97#ibcon#*after write, iclass 14, count 0 2006.196.08:16:19.97#ibcon#*before return 0, iclass 14, count 0 2006.196.08:16:19.97#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.196.08:16:19.97#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.196.08:16:19.97#ibcon#about to clear, iclass 14 cls_cnt 0 2006.196.08:16:19.97#ibcon#cleared, iclass 14 cls_cnt 0 2006.196.08:16:19.97$vc4f8/va=7,6 2006.196.08:16:19.97#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.196.08:16:19.97#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.196.08:16:19.97#ibcon#ireg 11 cls_cnt 2 2006.196.08:16:19.97#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.196.08:16:20.03#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.196.08:16:20.03#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.196.08:16:20.03#ibcon#enter wrdev, iclass 16, count 2 2006.196.08:16:20.03#ibcon#first serial, iclass 16, count 2 2006.196.08:16:20.03#ibcon#enter sib2, iclass 16, count 2 2006.196.08:16:20.03#ibcon#flushed, iclass 16, count 2 2006.196.08:16:20.03#ibcon#about to write, iclass 16, count 2 2006.196.08:16:20.03#ibcon#wrote, iclass 16, count 2 2006.196.08:16:20.03#ibcon#about to read 3, iclass 16, count 2 2006.196.08:16:20.05#ibcon#read 3, iclass 16, count 2 2006.196.08:16:20.05#ibcon#about to read 4, iclass 16, count 2 2006.196.08:16:20.05#ibcon#read 4, iclass 16, count 2 2006.196.08:16:20.05#ibcon#about to read 5, iclass 16, count 2 2006.196.08:16:20.05#ibcon#read 5, iclass 16, count 2 2006.196.08:16:20.05#ibcon#about to read 6, iclass 16, count 2 2006.196.08:16:20.05#ibcon#read 6, iclass 16, count 2 2006.196.08:16:20.05#ibcon#end of sib2, iclass 16, count 2 2006.196.08:16:20.05#ibcon#*mode == 0, iclass 16, count 2 2006.196.08:16:20.05#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.196.08:16:20.05#ibcon#[25=AT07-06\r\n] 2006.196.08:16:20.05#ibcon#*before write, iclass 16, count 2 2006.196.08:16:20.05#ibcon#enter sib2, iclass 16, count 2 2006.196.08:16:20.05#ibcon#flushed, iclass 16, count 2 2006.196.08:16:20.05#ibcon#about to write, iclass 16, count 2 2006.196.08:16:20.05#ibcon#wrote, iclass 16, count 2 2006.196.08:16:20.05#ibcon#about to read 3, iclass 16, count 2 2006.196.08:16:20.08#ibcon#read 3, iclass 16, count 2 2006.196.08:16:20.08#ibcon#about to read 4, iclass 16, count 2 2006.196.08:16:20.08#ibcon#read 4, iclass 16, count 2 2006.196.08:16:20.08#ibcon#about to read 5, iclass 16, count 2 2006.196.08:16:20.08#ibcon#read 5, iclass 16, count 2 2006.196.08:16:20.08#ibcon#about to read 6, iclass 16, count 2 2006.196.08:16:20.08#ibcon#read 6, iclass 16, count 2 2006.196.08:16:20.08#ibcon#end of sib2, iclass 16, count 2 2006.196.08:16:20.08#ibcon#*after write, iclass 16, count 2 2006.196.08:16:20.08#ibcon#*before return 0, iclass 16, count 2 2006.196.08:16:20.08#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.196.08:16:20.08#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.196.08:16:20.08#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.196.08:16:20.08#ibcon#ireg 7 cls_cnt 0 2006.196.08:16:20.08#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.196.08:16:20.20#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.196.08:16:20.20#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.196.08:16:20.20#ibcon#enter wrdev, iclass 16, count 0 2006.196.08:16:20.20#ibcon#first serial, iclass 16, count 0 2006.196.08:16:20.20#ibcon#enter sib2, iclass 16, count 0 2006.196.08:16:20.20#ibcon#flushed, iclass 16, count 0 2006.196.08:16:20.20#ibcon#about to write, iclass 16, count 0 2006.196.08:16:20.20#ibcon#wrote, iclass 16, count 0 2006.196.08:16:20.20#ibcon#about to read 3, iclass 16, count 0 2006.196.08:16:20.22#ibcon#read 3, iclass 16, count 0 2006.196.08:16:20.22#ibcon#about to read 4, iclass 16, count 0 2006.196.08:16:20.22#ibcon#read 4, iclass 16, count 0 2006.196.08:16:20.22#ibcon#about to read 5, iclass 16, count 0 2006.196.08:16:20.22#ibcon#read 5, iclass 16, count 0 2006.196.08:16:20.22#ibcon#about to read 6, iclass 16, count 0 2006.196.08:16:20.22#ibcon#read 6, iclass 16, count 0 2006.196.08:16:20.22#ibcon#end of sib2, iclass 16, count 0 2006.196.08:16:20.22#ibcon#*mode == 0, iclass 16, count 0 2006.196.08:16:20.22#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.196.08:16:20.22#ibcon#[25=USB\r\n] 2006.196.08:16:20.22#ibcon#*before write, iclass 16, count 0 2006.196.08:16:20.22#ibcon#enter sib2, iclass 16, count 0 2006.196.08:16:20.22#ibcon#flushed, iclass 16, count 0 2006.196.08:16:20.22#ibcon#about to write, iclass 16, count 0 2006.196.08:16:20.22#ibcon#wrote, iclass 16, count 0 2006.196.08:16:20.22#ibcon#about to read 3, iclass 16, count 0 2006.196.08:16:20.25#ibcon#read 3, iclass 16, count 0 2006.196.08:16:20.25#ibcon#about to read 4, iclass 16, count 0 2006.196.08:16:20.25#ibcon#read 4, iclass 16, count 0 2006.196.08:16:20.25#ibcon#about to read 5, iclass 16, count 0 2006.196.08:16:20.25#ibcon#read 5, iclass 16, count 0 2006.196.08:16:20.25#ibcon#about to read 6, iclass 16, count 0 2006.196.08:16:20.25#ibcon#read 6, iclass 16, count 0 2006.196.08:16:20.25#ibcon#end of sib2, iclass 16, count 0 2006.196.08:16:20.25#ibcon#*after write, iclass 16, count 0 2006.196.08:16:20.25#ibcon#*before return 0, iclass 16, count 0 2006.196.08:16:20.25#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.196.08:16:20.25#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.196.08:16:20.25#ibcon#about to clear, iclass 16 cls_cnt 0 2006.196.08:16:20.25#ibcon#cleared, iclass 16 cls_cnt 0 2006.196.08:16:20.25$vc4f8/valo=8,852.99 2006.196.08:16:20.25#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.196.08:16:20.25#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.196.08:16:20.25#ibcon#ireg 17 cls_cnt 0 2006.196.08:16:20.25#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.196.08:16:20.25#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.196.08:16:20.25#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.196.08:16:20.25#ibcon#enter wrdev, iclass 18, count 0 2006.196.08:16:20.25#ibcon#first serial, iclass 18, count 0 2006.196.08:16:20.25#ibcon#enter sib2, iclass 18, count 0 2006.196.08:16:20.25#ibcon#flushed, iclass 18, count 0 2006.196.08:16:20.25#ibcon#about to write, iclass 18, count 0 2006.196.08:16:20.25#ibcon#wrote, iclass 18, count 0 2006.196.08:16:20.25#ibcon#about to read 3, iclass 18, count 0 2006.196.08:16:20.27#ibcon#read 3, iclass 18, count 0 2006.196.08:16:20.27#ibcon#about to read 4, iclass 18, count 0 2006.196.08:16:20.27#ibcon#read 4, iclass 18, count 0 2006.196.08:16:20.27#ibcon#about to read 5, iclass 18, count 0 2006.196.08:16:20.27#ibcon#read 5, iclass 18, count 0 2006.196.08:16:20.27#ibcon#about to read 6, iclass 18, count 0 2006.196.08:16:20.27#ibcon#read 6, iclass 18, count 0 2006.196.08:16:20.27#ibcon#end of sib2, iclass 18, count 0 2006.196.08:16:20.27#ibcon#*mode == 0, iclass 18, count 0 2006.196.08:16:20.27#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.196.08:16:20.27#ibcon#[26=FRQ=08,852.99\r\n] 2006.196.08:16:20.27#ibcon#*before write, iclass 18, count 0 2006.196.08:16:20.27#ibcon#enter sib2, iclass 18, count 0 2006.196.08:16:20.27#ibcon#flushed, iclass 18, count 0 2006.196.08:16:20.27#ibcon#about to write, iclass 18, count 0 2006.196.08:16:20.27#ibcon#wrote, iclass 18, count 0 2006.196.08:16:20.27#ibcon#about to read 3, iclass 18, count 0 2006.196.08:16:20.31#ibcon#read 3, iclass 18, count 0 2006.196.08:16:20.31#ibcon#about to read 4, iclass 18, count 0 2006.196.08:16:20.31#ibcon#read 4, iclass 18, count 0 2006.196.08:16:20.31#ibcon#about to read 5, iclass 18, count 0 2006.196.08:16:20.31#ibcon#read 5, iclass 18, count 0 2006.196.08:16:20.31#ibcon#about to read 6, iclass 18, count 0 2006.196.08:16:20.31#ibcon#read 6, iclass 18, count 0 2006.196.08:16:20.31#ibcon#end of sib2, iclass 18, count 0 2006.196.08:16:20.31#ibcon#*after write, iclass 18, count 0 2006.196.08:16:20.31#ibcon#*before return 0, iclass 18, count 0 2006.196.08:16:20.31#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.196.08:16:20.31#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.196.08:16:20.31#ibcon#about to clear, iclass 18 cls_cnt 0 2006.196.08:16:20.31#ibcon#cleared, iclass 18 cls_cnt 0 2006.196.08:16:20.31$vc4f8/va=8,7 2006.196.08:16:20.31#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.196.08:16:20.31#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.196.08:16:20.31#ibcon#ireg 11 cls_cnt 2 2006.196.08:16:20.31#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.196.08:16:20.37#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.196.08:16:20.37#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.196.08:16:20.37#ibcon#enter wrdev, iclass 20, count 2 2006.196.08:16:20.37#ibcon#first serial, iclass 20, count 2 2006.196.08:16:20.37#ibcon#enter sib2, iclass 20, count 2 2006.196.08:16:20.37#ibcon#flushed, iclass 20, count 2 2006.196.08:16:20.37#ibcon#about to write, iclass 20, count 2 2006.196.08:16:20.37#ibcon#wrote, iclass 20, count 2 2006.196.08:16:20.37#ibcon#about to read 3, iclass 20, count 2 2006.196.08:16:20.39#ibcon#read 3, iclass 20, count 2 2006.196.08:16:20.39#ibcon#about to read 4, iclass 20, count 2 2006.196.08:16:20.39#ibcon#read 4, iclass 20, count 2 2006.196.08:16:20.39#ibcon#about to read 5, iclass 20, count 2 2006.196.08:16:20.39#ibcon#read 5, iclass 20, count 2 2006.196.08:16:20.39#ibcon#about to read 6, iclass 20, count 2 2006.196.08:16:20.39#ibcon#read 6, iclass 20, count 2 2006.196.08:16:20.39#ibcon#end of sib2, iclass 20, count 2 2006.196.08:16:20.39#ibcon#*mode == 0, iclass 20, count 2 2006.196.08:16:20.39#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.196.08:16:20.39#ibcon#[25=AT08-07\r\n] 2006.196.08:16:20.39#ibcon#*before write, iclass 20, count 2 2006.196.08:16:20.39#ibcon#enter sib2, iclass 20, count 2 2006.196.08:16:20.39#ibcon#flushed, iclass 20, count 2 2006.196.08:16:20.39#ibcon#about to write, iclass 20, count 2 2006.196.08:16:20.39#ibcon#wrote, iclass 20, count 2 2006.196.08:16:20.39#ibcon#about to read 3, iclass 20, count 2 2006.196.08:16:20.42#ibcon#read 3, iclass 20, count 2 2006.196.08:16:20.42#ibcon#about to read 4, iclass 20, count 2 2006.196.08:16:20.42#ibcon#read 4, iclass 20, count 2 2006.196.08:16:20.42#ibcon#about to read 5, iclass 20, count 2 2006.196.08:16:20.42#ibcon#read 5, iclass 20, count 2 2006.196.08:16:20.42#ibcon#about to read 6, iclass 20, count 2 2006.196.08:16:20.42#ibcon#read 6, iclass 20, count 2 2006.196.08:16:20.42#ibcon#end of sib2, iclass 20, count 2 2006.196.08:16:20.42#ibcon#*after write, iclass 20, count 2 2006.196.08:16:20.42#ibcon#*before return 0, iclass 20, count 2 2006.196.08:16:20.42#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.196.08:16:20.42#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.196.08:16:20.42#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.196.08:16:20.42#ibcon#ireg 7 cls_cnt 0 2006.196.08:16:20.42#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.196.08:16:20.54#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.196.08:16:20.54#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.196.08:16:20.54#ibcon#enter wrdev, iclass 20, count 0 2006.196.08:16:20.54#ibcon#first serial, iclass 20, count 0 2006.196.08:16:20.54#ibcon#enter sib2, iclass 20, count 0 2006.196.08:16:20.54#ibcon#flushed, iclass 20, count 0 2006.196.08:16:20.54#ibcon#about to write, iclass 20, count 0 2006.196.08:16:20.54#ibcon#wrote, iclass 20, count 0 2006.196.08:16:20.54#ibcon#about to read 3, iclass 20, count 0 2006.196.08:16:20.56#ibcon#read 3, iclass 20, count 0 2006.196.08:16:20.56#ibcon#about to read 4, iclass 20, count 0 2006.196.08:16:20.56#ibcon#read 4, iclass 20, count 0 2006.196.08:16:20.56#ibcon#about to read 5, iclass 20, count 0 2006.196.08:16:20.56#ibcon#read 5, iclass 20, count 0 2006.196.08:16:20.56#ibcon#about to read 6, iclass 20, count 0 2006.196.08:16:20.56#ibcon#read 6, iclass 20, count 0 2006.196.08:16:20.56#ibcon#end of sib2, iclass 20, count 0 2006.196.08:16:20.56#ibcon#*mode == 0, iclass 20, count 0 2006.196.08:16:20.56#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.196.08:16:20.56#ibcon#[25=USB\r\n] 2006.196.08:16:20.56#ibcon#*before write, iclass 20, count 0 2006.196.08:16:20.56#ibcon#enter sib2, iclass 20, count 0 2006.196.08:16:20.56#ibcon#flushed, iclass 20, count 0 2006.196.08:16:20.56#ibcon#about to write, iclass 20, count 0 2006.196.08:16:20.56#ibcon#wrote, iclass 20, count 0 2006.196.08:16:20.56#ibcon#about to read 3, iclass 20, count 0 2006.196.08:16:20.59#ibcon#read 3, iclass 20, count 0 2006.196.08:16:20.59#ibcon#about to read 4, iclass 20, count 0 2006.196.08:16:20.59#ibcon#read 4, iclass 20, count 0 2006.196.08:16:20.59#ibcon#about to read 5, iclass 20, count 0 2006.196.08:16:20.59#ibcon#read 5, iclass 20, count 0 2006.196.08:16:20.59#ibcon#about to read 6, iclass 20, count 0 2006.196.08:16:20.59#ibcon#read 6, iclass 20, count 0 2006.196.08:16:20.59#ibcon#end of sib2, iclass 20, count 0 2006.196.08:16:20.59#ibcon#*after write, iclass 20, count 0 2006.196.08:16:20.59#ibcon#*before return 0, iclass 20, count 0 2006.196.08:16:20.59#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.196.08:16:20.59#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.196.08:16:20.59#ibcon#about to clear, iclass 20 cls_cnt 0 2006.196.08:16:20.59#ibcon#cleared, iclass 20 cls_cnt 0 2006.196.08:16:20.59$vc4f8/vblo=1,632.99 2006.196.08:16:20.59#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.196.08:16:20.59#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.196.08:16:20.59#ibcon#ireg 17 cls_cnt 0 2006.196.08:16:20.59#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.196.08:16:20.59#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.196.08:16:20.59#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.196.08:16:20.59#ibcon#enter wrdev, iclass 22, count 0 2006.196.08:16:20.59#ibcon#first serial, iclass 22, count 0 2006.196.08:16:20.59#ibcon#enter sib2, iclass 22, count 0 2006.196.08:16:20.59#ibcon#flushed, iclass 22, count 0 2006.196.08:16:20.59#ibcon#about to write, iclass 22, count 0 2006.196.08:16:20.59#ibcon#wrote, iclass 22, count 0 2006.196.08:16:20.59#ibcon#about to read 3, iclass 22, count 0 2006.196.08:16:20.61#ibcon#read 3, iclass 22, count 0 2006.196.08:16:20.61#ibcon#about to read 4, iclass 22, count 0 2006.196.08:16:20.61#ibcon#read 4, iclass 22, count 0 2006.196.08:16:20.61#ibcon#about to read 5, iclass 22, count 0 2006.196.08:16:20.61#ibcon#read 5, iclass 22, count 0 2006.196.08:16:20.61#ibcon#about to read 6, iclass 22, count 0 2006.196.08:16:20.61#ibcon#read 6, iclass 22, count 0 2006.196.08:16:20.61#ibcon#end of sib2, iclass 22, count 0 2006.196.08:16:20.61#ibcon#*mode == 0, iclass 22, count 0 2006.196.08:16:20.61#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.196.08:16:20.61#ibcon#[28=FRQ=01,632.99\r\n] 2006.196.08:16:20.61#ibcon#*before write, iclass 22, count 0 2006.196.08:16:20.61#ibcon#enter sib2, iclass 22, count 0 2006.196.08:16:20.61#ibcon#flushed, iclass 22, count 0 2006.196.08:16:20.61#ibcon#about to write, iclass 22, count 0 2006.196.08:16:20.61#ibcon#wrote, iclass 22, count 0 2006.196.08:16:20.61#ibcon#about to read 3, iclass 22, count 0 2006.196.08:16:20.66#ibcon#read 3, iclass 22, count 0 2006.196.08:16:20.66#ibcon#about to read 4, iclass 22, count 0 2006.196.08:16:20.66#ibcon#read 4, iclass 22, count 0 2006.196.08:16:20.66#ibcon#about to read 5, iclass 22, count 0 2006.196.08:16:20.66#ibcon#read 5, iclass 22, count 0 2006.196.08:16:20.66#ibcon#about to read 6, iclass 22, count 0 2006.196.08:16:20.66#ibcon#read 6, iclass 22, count 0 2006.196.08:16:20.66#ibcon#end of sib2, iclass 22, count 0 2006.196.08:16:20.66#ibcon#*after write, iclass 22, count 0 2006.196.08:16:20.66#ibcon#*before return 0, iclass 22, count 0 2006.196.08:16:20.66#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.196.08:16:20.66#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.196.08:16:20.66#ibcon#about to clear, iclass 22 cls_cnt 0 2006.196.08:16:20.66#ibcon#cleared, iclass 22 cls_cnt 0 2006.196.08:16:20.66$vc4f8/vb=1,4 2006.196.08:16:20.66#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.196.08:16:20.66#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.196.08:16:20.66#ibcon#ireg 11 cls_cnt 2 2006.196.08:16:20.66#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.196.08:16:20.66#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.196.08:16:20.66#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.196.08:16:20.66#ibcon#enter wrdev, iclass 24, count 2 2006.196.08:16:20.66#ibcon#first serial, iclass 24, count 2 2006.196.08:16:20.66#ibcon#enter sib2, iclass 24, count 2 2006.196.08:16:20.66#ibcon#flushed, iclass 24, count 2 2006.196.08:16:20.66#ibcon#about to write, iclass 24, count 2 2006.196.08:16:20.66#ibcon#wrote, iclass 24, count 2 2006.196.08:16:20.66#ibcon#about to read 3, iclass 24, count 2 2006.196.08:16:20.68#ibcon#read 3, iclass 24, count 2 2006.196.08:16:20.68#ibcon#about to read 4, iclass 24, count 2 2006.196.08:16:20.68#ibcon#read 4, iclass 24, count 2 2006.196.08:16:20.68#ibcon#about to read 5, iclass 24, count 2 2006.196.08:16:20.68#ibcon#read 5, iclass 24, count 2 2006.196.08:16:20.68#ibcon#about to read 6, iclass 24, count 2 2006.196.08:16:20.68#ibcon#read 6, iclass 24, count 2 2006.196.08:16:20.68#ibcon#end of sib2, iclass 24, count 2 2006.196.08:16:20.68#ibcon#*mode == 0, iclass 24, count 2 2006.196.08:16:20.68#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.196.08:16:20.68#ibcon#[27=AT01-04\r\n] 2006.196.08:16:20.68#ibcon#*before write, iclass 24, count 2 2006.196.08:16:20.68#ibcon#enter sib2, iclass 24, count 2 2006.196.08:16:20.68#ibcon#flushed, iclass 24, count 2 2006.196.08:16:20.68#ibcon#about to write, iclass 24, count 2 2006.196.08:16:20.68#ibcon#wrote, iclass 24, count 2 2006.196.08:16:20.68#ibcon#about to read 3, iclass 24, count 2 2006.196.08:16:20.71#ibcon#read 3, iclass 24, count 2 2006.196.08:16:20.71#ibcon#about to read 4, iclass 24, count 2 2006.196.08:16:20.71#ibcon#read 4, iclass 24, count 2 2006.196.08:16:20.71#ibcon#about to read 5, iclass 24, count 2 2006.196.08:16:20.71#ibcon#read 5, iclass 24, count 2 2006.196.08:16:20.71#ibcon#about to read 6, iclass 24, count 2 2006.196.08:16:20.71#ibcon#read 6, iclass 24, count 2 2006.196.08:16:20.71#ibcon#end of sib2, iclass 24, count 2 2006.196.08:16:20.71#ibcon#*after write, iclass 24, count 2 2006.196.08:16:20.71#ibcon#*before return 0, iclass 24, count 2 2006.196.08:16:20.71#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.196.08:16:20.71#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.196.08:16:20.71#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.196.08:16:20.71#ibcon#ireg 7 cls_cnt 0 2006.196.08:16:20.71#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.196.08:16:20.83#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.196.08:16:20.83#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.196.08:16:20.83#ibcon#enter wrdev, iclass 24, count 0 2006.196.08:16:20.83#ibcon#first serial, iclass 24, count 0 2006.196.08:16:20.83#ibcon#enter sib2, iclass 24, count 0 2006.196.08:16:20.83#ibcon#flushed, iclass 24, count 0 2006.196.08:16:20.83#ibcon#about to write, iclass 24, count 0 2006.196.08:16:20.83#ibcon#wrote, iclass 24, count 0 2006.196.08:16:20.83#ibcon#about to read 3, iclass 24, count 0 2006.196.08:16:20.85#ibcon#read 3, iclass 24, count 0 2006.196.08:16:20.85#ibcon#about to read 4, iclass 24, count 0 2006.196.08:16:20.85#ibcon#read 4, iclass 24, count 0 2006.196.08:16:20.85#ibcon#about to read 5, iclass 24, count 0 2006.196.08:16:20.85#ibcon#read 5, iclass 24, count 0 2006.196.08:16:20.85#ibcon#about to read 6, iclass 24, count 0 2006.196.08:16:20.85#ibcon#read 6, iclass 24, count 0 2006.196.08:16:20.85#ibcon#end of sib2, iclass 24, count 0 2006.196.08:16:20.85#ibcon#*mode == 0, iclass 24, count 0 2006.196.08:16:20.85#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.196.08:16:20.85#ibcon#[27=USB\r\n] 2006.196.08:16:20.85#ibcon#*before write, iclass 24, count 0 2006.196.08:16:20.85#ibcon#enter sib2, iclass 24, count 0 2006.196.08:16:20.85#ibcon#flushed, iclass 24, count 0 2006.196.08:16:20.85#ibcon#about to write, iclass 24, count 0 2006.196.08:16:20.85#ibcon#wrote, iclass 24, count 0 2006.196.08:16:20.85#ibcon#about to read 3, iclass 24, count 0 2006.196.08:16:20.88#ibcon#read 3, iclass 24, count 0 2006.196.08:16:20.88#ibcon#about to read 4, iclass 24, count 0 2006.196.08:16:20.88#ibcon#read 4, iclass 24, count 0 2006.196.08:16:20.88#ibcon#about to read 5, iclass 24, count 0 2006.196.08:16:20.88#ibcon#read 5, iclass 24, count 0 2006.196.08:16:20.88#ibcon#about to read 6, iclass 24, count 0 2006.196.08:16:20.88#ibcon#read 6, iclass 24, count 0 2006.196.08:16:20.88#ibcon#end of sib2, iclass 24, count 0 2006.196.08:16:20.88#ibcon#*after write, iclass 24, count 0 2006.196.08:16:20.88#ibcon#*before return 0, iclass 24, count 0 2006.196.08:16:20.88#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.196.08:16:20.88#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.196.08:16:20.88#ibcon#about to clear, iclass 24 cls_cnt 0 2006.196.08:16:20.88#ibcon#cleared, iclass 24 cls_cnt 0 2006.196.08:16:20.88$vc4f8/vblo=2,640.99 2006.196.08:16:20.88#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.196.08:16:20.88#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.196.08:16:20.88#ibcon#ireg 17 cls_cnt 0 2006.196.08:16:20.88#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.196.08:16:20.88#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.196.08:16:20.88#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.196.08:16:20.88#ibcon#enter wrdev, iclass 26, count 0 2006.196.08:16:20.88#ibcon#first serial, iclass 26, count 0 2006.196.08:16:20.88#ibcon#enter sib2, iclass 26, count 0 2006.196.08:16:20.88#ibcon#flushed, iclass 26, count 0 2006.196.08:16:20.88#ibcon#about to write, iclass 26, count 0 2006.196.08:16:20.88#ibcon#wrote, iclass 26, count 0 2006.196.08:16:20.88#ibcon#about to read 3, iclass 26, count 0 2006.196.08:16:20.90#ibcon#read 3, iclass 26, count 0 2006.196.08:16:20.90#ibcon#about to read 4, iclass 26, count 0 2006.196.08:16:20.90#ibcon#read 4, iclass 26, count 0 2006.196.08:16:20.90#ibcon#about to read 5, iclass 26, count 0 2006.196.08:16:20.90#ibcon#read 5, iclass 26, count 0 2006.196.08:16:20.90#ibcon#about to read 6, iclass 26, count 0 2006.196.08:16:20.90#ibcon#read 6, iclass 26, count 0 2006.196.08:16:20.90#ibcon#end of sib2, iclass 26, count 0 2006.196.08:16:20.90#ibcon#*mode == 0, iclass 26, count 0 2006.196.08:16:20.90#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.196.08:16:20.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.196.08:16:20.90#ibcon#*before write, iclass 26, count 0 2006.196.08:16:20.90#ibcon#enter sib2, iclass 26, count 0 2006.196.08:16:20.90#ibcon#flushed, iclass 26, count 0 2006.196.08:16:20.90#ibcon#about to write, iclass 26, count 0 2006.196.08:16:20.90#ibcon#wrote, iclass 26, count 0 2006.196.08:16:20.90#ibcon#about to read 3, iclass 26, count 0 2006.196.08:16:20.94#ibcon#read 3, iclass 26, count 0 2006.196.08:16:20.94#ibcon#about to read 4, iclass 26, count 0 2006.196.08:16:20.94#ibcon#read 4, iclass 26, count 0 2006.196.08:16:20.94#ibcon#about to read 5, iclass 26, count 0 2006.196.08:16:20.94#ibcon#read 5, iclass 26, count 0 2006.196.08:16:20.94#ibcon#about to read 6, iclass 26, count 0 2006.196.08:16:20.94#ibcon#read 6, iclass 26, count 0 2006.196.08:16:20.94#ibcon#end of sib2, iclass 26, count 0 2006.196.08:16:20.94#ibcon#*after write, iclass 26, count 0 2006.196.08:16:20.94#ibcon#*before return 0, iclass 26, count 0 2006.196.08:16:20.94#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.196.08:16:20.94#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.196.08:16:20.94#ibcon#about to clear, iclass 26 cls_cnt 0 2006.196.08:16:20.94#ibcon#cleared, iclass 26 cls_cnt 0 2006.196.08:16:20.94$vc4f8/vb=2,4 2006.196.08:16:20.94#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.196.08:16:20.94#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.196.08:16:20.94#ibcon#ireg 11 cls_cnt 2 2006.196.08:16:20.94#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.196.08:16:21.00#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.196.08:16:21.00#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.196.08:16:21.00#ibcon#enter wrdev, iclass 28, count 2 2006.196.08:16:21.00#ibcon#first serial, iclass 28, count 2 2006.196.08:16:21.00#ibcon#enter sib2, iclass 28, count 2 2006.196.08:16:21.00#ibcon#flushed, iclass 28, count 2 2006.196.08:16:21.00#ibcon#about to write, iclass 28, count 2 2006.196.08:16:21.00#ibcon#wrote, iclass 28, count 2 2006.196.08:16:21.00#ibcon#about to read 3, iclass 28, count 2 2006.196.08:16:21.02#ibcon#read 3, iclass 28, count 2 2006.196.08:16:21.02#ibcon#about to read 4, iclass 28, count 2 2006.196.08:16:21.02#ibcon#read 4, iclass 28, count 2 2006.196.08:16:21.02#ibcon#about to read 5, iclass 28, count 2 2006.196.08:16:21.02#ibcon#read 5, iclass 28, count 2 2006.196.08:16:21.02#ibcon#about to read 6, iclass 28, count 2 2006.196.08:16:21.02#ibcon#read 6, iclass 28, count 2 2006.196.08:16:21.02#ibcon#end of sib2, iclass 28, count 2 2006.196.08:16:21.02#ibcon#*mode == 0, iclass 28, count 2 2006.196.08:16:21.02#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.196.08:16:21.02#ibcon#[27=AT02-04\r\n] 2006.196.08:16:21.02#ibcon#*before write, iclass 28, count 2 2006.196.08:16:21.02#ibcon#enter sib2, iclass 28, count 2 2006.196.08:16:21.02#ibcon#flushed, iclass 28, count 2 2006.196.08:16:21.02#ibcon#about to write, iclass 28, count 2 2006.196.08:16:21.02#ibcon#wrote, iclass 28, count 2 2006.196.08:16:21.02#ibcon#about to read 3, iclass 28, count 2 2006.196.08:16:21.05#ibcon#read 3, iclass 28, count 2 2006.196.08:16:21.05#ibcon#about to read 4, iclass 28, count 2 2006.196.08:16:21.05#ibcon#read 4, iclass 28, count 2 2006.196.08:16:21.05#ibcon#about to read 5, iclass 28, count 2 2006.196.08:16:21.05#ibcon#read 5, iclass 28, count 2 2006.196.08:16:21.05#ibcon#about to read 6, iclass 28, count 2 2006.196.08:16:21.05#ibcon#read 6, iclass 28, count 2 2006.196.08:16:21.05#ibcon#end of sib2, iclass 28, count 2 2006.196.08:16:21.05#ibcon#*after write, iclass 28, count 2 2006.196.08:16:21.05#ibcon#*before return 0, iclass 28, count 2 2006.196.08:16:21.05#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.196.08:16:21.05#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.196.08:16:21.05#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.196.08:16:21.05#ibcon#ireg 7 cls_cnt 0 2006.196.08:16:21.05#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.196.08:16:21.17#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.196.08:16:21.17#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.196.08:16:21.17#ibcon#enter wrdev, iclass 28, count 0 2006.196.08:16:21.17#ibcon#first serial, iclass 28, count 0 2006.196.08:16:21.17#ibcon#enter sib2, iclass 28, count 0 2006.196.08:16:21.17#ibcon#flushed, iclass 28, count 0 2006.196.08:16:21.17#ibcon#about to write, iclass 28, count 0 2006.196.08:16:21.17#ibcon#wrote, iclass 28, count 0 2006.196.08:16:21.17#ibcon#about to read 3, iclass 28, count 0 2006.196.08:16:21.19#ibcon#read 3, iclass 28, count 0 2006.196.08:16:21.19#ibcon#about to read 4, iclass 28, count 0 2006.196.08:16:21.19#ibcon#read 4, iclass 28, count 0 2006.196.08:16:21.19#ibcon#about to read 5, iclass 28, count 0 2006.196.08:16:21.19#ibcon#read 5, iclass 28, count 0 2006.196.08:16:21.19#ibcon#about to read 6, iclass 28, count 0 2006.196.08:16:21.19#ibcon#read 6, iclass 28, count 0 2006.196.08:16:21.19#ibcon#end of sib2, iclass 28, count 0 2006.196.08:16:21.19#ibcon#*mode == 0, iclass 28, count 0 2006.196.08:16:21.19#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.196.08:16:21.19#ibcon#[27=USB\r\n] 2006.196.08:16:21.19#ibcon#*before write, iclass 28, count 0 2006.196.08:16:21.19#ibcon#enter sib2, iclass 28, count 0 2006.196.08:16:21.19#ibcon#flushed, iclass 28, count 0 2006.196.08:16:21.19#ibcon#about to write, iclass 28, count 0 2006.196.08:16:21.19#ibcon#wrote, iclass 28, count 0 2006.196.08:16:21.19#ibcon#about to read 3, iclass 28, count 0 2006.196.08:16:21.22#ibcon#read 3, iclass 28, count 0 2006.196.08:16:21.22#ibcon#about to read 4, iclass 28, count 0 2006.196.08:16:21.22#ibcon#read 4, iclass 28, count 0 2006.196.08:16:21.22#ibcon#about to read 5, iclass 28, count 0 2006.196.08:16:21.22#ibcon#read 5, iclass 28, count 0 2006.196.08:16:21.22#ibcon#about to read 6, iclass 28, count 0 2006.196.08:16:21.22#ibcon#read 6, iclass 28, count 0 2006.196.08:16:21.22#ibcon#end of sib2, iclass 28, count 0 2006.196.08:16:21.22#ibcon#*after write, iclass 28, count 0 2006.196.08:16:21.22#ibcon#*before return 0, iclass 28, count 0 2006.196.08:16:21.22#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.196.08:16:21.22#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.196.08:16:21.22#ibcon#about to clear, iclass 28 cls_cnt 0 2006.196.08:16:21.22#ibcon#cleared, iclass 28 cls_cnt 0 2006.196.08:16:21.22$vc4f8/vblo=3,656.99 2006.196.08:16:21.22#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.196.08:16:21.22#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.196.08:16:21.22#ibcon#ireg 17 cls_cnt 0 2006.196.08:16:21.22#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.196.08:16:21.22#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.196.08:16:21.22#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.196.08:16:21.22#ibcon#enter wrdev, iclass 30, count 0 2006.196.08:16:21.22#ibcon#first serial, iclass 30, count 0 2006.196.08:16:21.22#ibcon#enter sib2, iclass 30, count 0 2006.196.08:16:21.22#ibcon#flushed, iclass 30, count 0 2006.196.08:16:21.22#ibcon#about to write, iclass 30, count 0 2006.196.08:16:21.22#ibcon#wrote, iclass 30, count 0 2006.196.08:16:21.22#ibcon#about to read 3, iclass 30, count 0 2006.196.08:16:21.24#ibcon#read 3, iclass 30, count 0 2006.196.08:16:21.24#ibcon#about to read 4, iclass 30, count 0 2006.196.08:16:21.24#ibcon#read 4, iclass 30, count 0 2006.196.08:16:21.24#ibcon#about to read 5, iclass 30, count 0 2006.196.08:16:21.24#ibcon#read 5, iclass 30, count 0 2006.196.08:16:21.24#ibcon#about to read 6, iclass 30, count 0 2006.196.08:16:21.24#ibcon#read 6, iclass 30, count 0 2006.196.08:16:21.24#ibcon#end of sib2, iclass 30, count 0 2006.196.08:16:21.24#ibcon#*mode == 0, iclass 30, count 0 2006.196.08:16:21.24#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.196.08:16:21.24#ibcon#[28=FRQ=03,656.99\r\n] 2006.196.08:16:21.24#ibcon#*before write, iclass 30, count 0 2006.196.08:16:21.24#ibcon#enter sib2, iclass 30, count 0 2006.196.08:16:21.24#ibcon#flushed, iclass 30, count 0 2006.196.08:16:21.24#ibcon#about to write, iclass 30, count 0 2006.196.08:16:21.24#ibcon#wrote, iclass 30, count 0 2006.196.08:16:21.24#ibcon#about to read 3, iclass 30, count 0 2006.196.08:16:21.28#ibcon#read 3, iclass 30, count 0 2006.196.08:16:21.28#ibcon#about to read 4, iclass 30, count 0 2006.196.08:16:21.28#ibcon#read 4, iclass 30, count 0 2006.196.08:16:21.28#ibcon#about to read 5, iclass 30, count 0 2006.196.08:16:21.28#ibcon#read 5, iclass 30, count 0 2006.196.08:16:21.28#ibcon#about to read 6, iclass 30, count 0 2006.196.08:16:21.28#ibcon#read 6, iclass 30, count 0 2006.196.08:16:21.28#ibcon#end of sib2, iclass 30, count 0 2006.196.08:16:21.28#ibcon#*after write, iclass 30, count 0 2006.196.08:16:21.28#ibcon#*before return 0, iclass 30, count 0 2006.196.08:16:21.28#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.196.08:16:21.28#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.196.08:16:21.28#ibcon#about to clear, iclass 30 cls_cnt 0 2006.196.08:16:21.28#ibcon#cleared, iclass 30 cls_cnt 0 2006.196.08:16:21.28$vc4f8/vb=3,4 2006.196.08:16:21.28#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.196.08:16:21.28#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.196.08:16:21.28#ibcon#ireg 11 cls_cnt 2 2006.196.08:16:21.28#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.196.08:16:21.34#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.196.08:16:21.34#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.196.08:16:21.34#ibcon#enter wrdev, iclass 32, count 2 2006.196.08:16:21.34#ibcon#first serial, iclass 32, count 2 2006.196.08:16:21.34#ibcon#enter sib2, iclass 32, count 2 2006.196.08:16:21.34#ibcon#flushed, iclass 32, count 2 2006.196.08:16:21.34#ibcon#about to write, iclass 32, count 2 2006.196.08:16:21.34#ibcon#wrote, iclass 32, count 2 2006.196.08:16:21.34#ibcon#about to read 3, iclass 32, count 2 2006.196.08:16:21.36#ibcon#read 3, iclass 32, count 2 2006.196.08:16:21.36#ibcon#about to read 4, iclass 32, count 2 2006.196.08:16:21.36#ibcon#read 4, iclass 32, count 2 2006.196.08:16:21.36#ibcon#about to read 5, iclass 32, count 2 2006.196.08:16:21.36#ibcon#read 5, iclass 32, count 2 2006.196.08:16:21.36#ibcon#about to read 6, iclass 32, count 2 2006.196.08:16:21.36#ibcon#read 6, iclass 32, count 2 2006.196.08:16:21.36#ibcon#end of sib2, iclass 32, count 2 2006.196.08:16:21.36#ibcon#*mode == 0, iclass 32, count 2 2006.196.08:16:21.36#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.196.08:16:21.36#ibcon#[27=AT03-04\r\n] 2006.196.08:16:21.36#ibcon#*before write, iclass 32, count 2 2006.196.08:16:21.36#ibcon#enter sib2, iclass 32, count 2 2006.196.08:16:21.36#ibcon#flushed, iclass 32, count 2 2006.196.08:16:21.36#ibcon#about to write, iclass 32, count 2 2006.196.08:16:21.36#ibcon#wrote, iclass 32, count 2 2006.196.08:16:21.36#ibcon#about to read 3, iclass 32, count 2 2006.196.08:16:21.39#ibcon#read 3, iclass 32, count 2 2006.196.08:16:21.39#ibcon#about to read 4, iclass 32, count 2 2006.196.08:16:21.39#ibcon#read 4, iclass 32, count 2 2006.196.08:16:21.39#ibcon#about to read 5, iclass 32, count 2 2006.196.08:16:21.39#ibcon#read 5, iclass 32, count 2 2006.196.08:16:21.39#ibcon#about to read 6, iclass 32, count 2 2006.196.08:16:21.39#ibcon#read 6, iclass 32, count 2 2006.196.08:16:21.39#ibcon#end of sib2, iclass 32, count 2 2006.196.08:16:21.39#ibcon#*after write, iclass 32, count 2 2006.196.08:16:21.39#ibcon#*before return 0, iclass 32, count 2 2006.196.08:16:21.39#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.196.08:16:21.39#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.196.08:16:21.39#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.196.08:16:21.39#ibcon#ireg 7 cls_cnt 0 2006.196.08:16:21.39#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.196.08:16:21.51#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.196.08:16:21.51#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.196.08:16:21.51#ibcon#enter wrdev, iclass 32, count 0 2006.196.08:16:21.51#ibcon#first serial, iclass 32, count 0 2006.196.08:16:21.51#ibcon#enter sib2, iclass 32, count 0 2006.196.08:16:21.51#ibcon#flushed, iclass 32, count 0 2006.196.08:16:21.51#ibcon#about to write, iclass 32, count 0 2006.196.08:16:21.51#ibcon#wrote, iclass 32, count 0 2006.196.08:16:21.51#ibcon#about to read 3, iclass 32, count 0 2006.196.08:16:21.53#ibcon#read 3, iclass 32, count 0 2006.196.08:16:21.53#ibcon#about to read 4, iclass 32, count 0 2006.196.08:16:21.53#ibcon#read 4, iclass 32, count 0 2006.196.08:16:21.53#ibcon#about to read 5, iclass 32, count 0 2006.196.08:16:21.53#ibcon#read 5, iclass 32, count 0 2006.196.08:16:21.53#ibcon#about to read 6, iclass 32, count 0 2006.196.08:16:21.53#ibcon#read 6, iclass 32, count 0 2006.196.08:16:21.53#ibcon#end of sib2, iclass 32, count 0 2006.196.08:16:21.53#ibcon#*mode == 0, iclass 32, count 0 2006.196.08:16:21.53#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.196.08:16:21.53#ibcon#[27=USB\r\n] 2006.196.08:16:21.53#ibcon#*before write, iclass 32, count 0 2006.196.08:16:21.53#ibcon#enter sib2, iclass 32, count 0 2006.196.08:16:21.53#ibcon#flushed, iclass 32, count 0 2006.196.08:16:21.53#ibcon#about to write, iclass 32, count 0 2006.196.08:16:21.53#ibcon#wrote, iclass 32, count 0 2006.196.08:16:21.53#ibcon#about to read 3, iclass 32, count 0 2006.196.08:16:21.56#ibcon#read 3, iclass 32, count 0 2006.196.08:16:21.56#ibcon#about to read 4, iclass 32, count 0 2006.196.08:16:21.56#ibcon#read 4, iclass 32, count 0 2006.196.08:16:21.56#ibcon#about to read 5, iclass 32, count 0 2006.196.08:16:21.56#ibcon#read 5, iclass 32, count 0 2006.196.08:16:21.56#ibcon#about to read 6, iclass 32, count 0 2006.196.08:16:21.56#ibcon#read 6, iclass 32, count 0 2006.196.08:16:21.56#ibcon#end of sib2, iclass 32, count 0 2006.196.08:16:21.56#ibcon#*after write, iclass 32, count 0 2006.196.08:16:21.56#ibcon#*before return 0, iclass 32, count 0 2006.196.08:16:21.56#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.196.08:16:21.56#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.196.08:16:21.56#ibcon#about to clear, iclass 32 cls_cnt 0 2006.196.08:16:21.56#ibcon#cleared, iclass 32 cls_cnt 0 2006.196.08:16:21.56$vc4f8/vblo=4,712.99 2006.196.08:16:21.56#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.196.08:16:21.56#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.196.08:16:21.56#ibcon#ireg 17 cls_cnt 0 2006.196.08:16:21.56#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.196.08:16:21.56#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.196.08:16:21.56#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.196.08:16:21.56#ibcon#enter wrdev, iclass 34, count 0 2006.196.08:16:21.56#ibcon#first serial, iclass 34, count 0 2006.196.08:16:21.56#ibcon#enter sib2, iclass 34, count 0 2006.196.08:16:21.56#ibcon#flushed, iclass 34, count 0 2006.196.08:16:21.56#ibcon#about to write, iclass 34, count 0 2006.196.08:16:21.56#ibcon#wrote, iclass 34, count 0 2006.196.08:16:21.56#ibcon#about to read 3, iclass 34, count 0 2006.196.08:16:21.58#ibcon#read 3, iclass 34, count 0 2006.196.08:16:21.58#ibcon#about to read 4, iclass 34, count 0 2006.196.08:16:21.58#ibcon#read 4, iclass 34, count 0 2006.196.08:16:21.58#ibcon#about to read 5, iclass 34, count 0 2006.196.08:16:21.58#ibcon#read 5, iclass 34, count 0 2006.196.08:16:21.58#ibcon#about to read 6, iclass 34, count 0 2006.196.08:16:21.58#ibcon#read 6, iclass 34, count 0 2006.196.08:16:21.58#ibcon#end of sib2, iclass 34, count 0 2006.196.08:16:21.58#ibcon#*mode == 0, iclass 34, count 0 2006.196.08:16:21.58#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.196.08:16:21.58#ibcon#[28=FRQ=04,712.99\r\n] 2006.196.08:16:21.58#ibcon#*before write, iclass 34, count 0 2006.196.08:16:21.58#ibcon#enter sib2, iclass 34, count 0 2006.196.08:16:21.58#ibcon#flushed, iclass 34, count 0 2006.196.08:16:21.58#ibcon#about to write, iclass 34, count 0 2006.196.08:16:21.58#ibcon#wrote, iclass 34, count 0 2006.196.08:16:21.58#ibcon#about to read 3, iclass 34, count 0 2006.196.08:16:21.62#ibcon#read 3, iclass 34, count 0 2006.196.08:16:21.62#ibcon#about to read 4, iclass 34, count 0 2006.196.08:16:21.62#ibcon#read 4, iclass 34, count 0 2006.196.08:16:21.62#ibcon#about to read 5, iclass 34, count 0 2006.196.08:16:21.62#ibcon#read 5, iclass 34, count 0 2006.196.08:16:21.62#ibcon#about to read 6, iclass 34, count 0 2006.196.08:16:21.62#ibcon#read 6, iclass 34, count 0 2006.196.08:16:21.62#ibcon#end of sib2, iclass 34, count 0 2006.196.08:16:21.62#ibcon#*after write, iclass 34, count 0 2006.196.08:16:21.62#ibcon#*before return 0, iclass 34, count 0 2006.196.08:16:21.62#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.196.08:16:21.62#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.196.08:16:21.62#ibcon#about to clear, iclass 34 cls_cnt 0 2006.196.08:16:21.62#ibcon#cleared, iclass 34 cls_cnt 0 2006.196.08:16:21.62$vc4f8/vb=4,4 2006.196.08:16:21.62#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.196.08:16:21.62#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.196.08:16:21.62#ibcon#ireg 11 cls_cnt 2 2006.196.08:16:21.62#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.196.08:16:21.68#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.196.08:16:21.68#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.196.08:16:21.68#ibcon#enter wrdev, iclass 36, count 2 2006.196.08:16:21.68#ibcon#first serial, iclass 36, count 2 2006.196.08:16:21.68#ibcon#enter sib2, iclass 36, count 2 2006.196.08:16:21.68#ibcon#flushed, iclass 36, count 2 2006.196.08:16:21.68#ibcon#about to write, iclass 36, count 2 2006.196.08:16:21.68#ibcon#wrote, iclass 36, count 2 2006.196.08:16:21.68#ibcon#about to read 3, iclass 36, count 2 2006.196.08:16:21.70#ibcon#read 3, iclass 36, count 2 2006.196.08:16:21.70#ibcon#about to read 4, iclass 36, count 2 2006.196.08:16:21.70#ibcon#read 4, iclass 36, count 2 2006.196.08:16:21.70#ibcon#about to read 5, iclass 36, count 2 2006.196.08:16:21.70#ibcon#read 5, iclass 36, count 2 2006.196.08:16:21.70#ibcon#about to read 6, iclass 36, count 2 2006.196.08:16:21.70#ibcon#read 6, iclass 36, count 2 2006.196.08:16:21.70#ibcon#end of sib2, iclass 36, count 2 2006.196.08:16:21.70#ibcon#*mode == 0, iclass 36, count 2 2006.196.08:16:21.70#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.196.08:16:21.70#ibcon#[27=AT04-04\r\n] 2006.196.08:16:21.70#ibcon#*before write, iclass 36, count 2 2006.196.08:16:21.70#ibcon#enter sib2, iclass 36, count 2 2006.196.08:16:21.70#ibcon#flushed, iclass 36, count 2 2006.196.08:16:21.70#ibcon#about to write, iclass 36, count 2 2006.196.08:16:21.70#ibcon#wrote, iclass 36, count 2 2006.196.08:16:21.70#ibcon#about to read 3, iclass 36, count 2 2006.196.08:16:21.73#ibcon#read 3, iclass 36, count 2 2006.196.08:16:21.73#ibcon#about to read 4, iclass 36, count 2 2006.196.08:16:21.73#ibcon#read 4, iclass 36, count 2 2006.196.08:16:21.73#ibcon#about to read 5, iclass 36, count 2 2006.196.08:16:21.73#ibcon#read 5, iclass 36, count 2 2006.196.08:16:21.73#ibcon#about to read 6, iclass 36, count 2 2006.196.08:16:21.73#ibcon#read 6, iclass 36, count 2 2006.196.08:16:21.73#ibcon#end of sib2, iclass 36, count 2 2006.196.08:16:21.73#ibcon#*after write, iclass 36, count 2 2006.196.08:16:21.73#ibcon#*before return 0, iclass 36, count 2 2006.196.08:16:21.73#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.196.08:16:21.73#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.196.08:16:21.73#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.196.08:16:21.73#ibcon#ireg 7 cls_cnt 0 2006.196.08:16:21.73#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.196.08:16:21.85#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.196.08:16:21.85#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.196.08:16:21.85#ibcon#enter wrdev, iclass 36, count 0 2006.196.08:16:21.85#ibcon#first serial, iclass 36, count 0 2006.196.08:16:21.85#ibcon#enter sib2, iclass 36, count 0 2006.196.08:16:21.85#ibcon#flushed, iclass 36, count 0 2006.196.08:16:21.85#ibcon#about to write, iclass 36, count 0 2006.196.08:16:21.85#ibcon#wrote, iclass 36, count 0 2006.196.08:16:21.85#ibcon#about to read 3, iclass 36, count 0 2006.196.08:16:21.87#ibcon#read 3, iclass 36, count 0 2006.196.08:16:21.87#ibcon#about to read 4, iclass 36, count 0 2006.196.08:16:21.87#ibcon#read 4, iclass 36, count 0 2006.196.08:16:21.87#ibcon#about to read 5, iclass 36, count 0 2006.196.08:16:21.87#ibcon#read 5, iclass 36, count 0 2006.196.08:16:21.87#ibcon#about to read 6, iclass 36, count 0 2006.196.08:16:21.87#ibcon#read 6, iclass 36, count 0 2006.196.08:16:21.87#ibcon#end of sib2, iclass 36, count 0 2006.196.08:16:21.87#ibcon#*mode == 0, iclass 36, count 0 2006.196.08:16:21.87#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.196.08:16:21.87#ibcon#[27=USB\r\n] 2006.196.08:16:21.87#ibcon#*before write, iclass 36, count 0 2006.196.08:16:21.87#ibcon#enter sib2, iclass 36, count 0 2006.196.08:16:21.87#ibcon#flushed, iclass 36, count 0 2006.196.08:16:21.87#ibcon#about to write, iclass 36, count 0 2006.196.08:16:21.87#ibcon#wrote, iclass 36, count 0 2006.196.08:16:21.87#ibcon#about to read 3, iclass 36, count 0 2006.196.08:16:21.90#ibcon#read 3, iclass 36, count 0 2006.196.08:16:21.90#ibcon#about to read 4, iclass 36, count 0 2006.196.08:16:21.90#ibcon#read 4, iclass 36, count 0 2006.196.08:16:21.90#ibcon#about to read 5, iclass 36, count 0 2006.196.08:16:21.90#ibcon#read 5, iclass 36, count 0 2006.196.08:16:21.90#ibcon#about to read 6, iclass 36, count 0 2006.196.08:16:21.90#ibcon#read 6, iclass 36, count 0 2006.196.08:16:21.90#ibcon#end of sib2, iclass 36, count 0 2006.196.08:16:21.90#ibcon#*after write, iclass 36, count 0 2006.196.08:16:21.90#ibcon#*before return 0, iclass 36, count 0 2006.196.08:16:21.90#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.196.08:16:21.90#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.196.08:16:21.90#ibcon#about to clear, iclass 36 cls_cnt 0 2006.196.08:16:21.90#ibcon#cleared, iclass 36 cls_cnt 0 2006.196.08:16:21.90$vc4f8/vblo=5,744.99 2006.196.08:16:21.90#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.196.08:16:21.90#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.196.08:16:21.90#ibcon#ireg 17 cls_cnt 0 2006.196.08:16:21.90#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.196.08:16:21.90#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.196.08:16:21.90#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.196.08:16:21.90#ibcon#enter wrdev, iclass 38, count 0 2006.196.08:16:21.90#ibcon#first serial, iclass 38, count 0 2006.196.08:16:21.90#ibcon#enter sib2, iclass 38, count 0 2006.196.08:16:21.90#ibcon#flushed, iclass 38, count 0 2006.196.08:16:21.90#ibcon#about to write, iclass 38, count 0 2006.196.08:16:21.90#ibcon#wrote, iclass 38, count 0 2006.196.08:16:21.90#ibcon#about to read 3, iclass 38, count 0 2006.196.08:16:21.92#ibcon#read 3, iclass 38, count 0 2006.196.08:16:21.92#ibcon#about to read 4, iclass 38, count 0 2006.196.08:16:21.92#ibcon#read 4, iclass 38, count 0 2006.196.08:16:21.92#ibcon#about to read 5, iclass 38, count 0 2006.196.08:16:21.92#ibcon#read 5, iclass 38, count 0 2006.196.08:16:21.92#ibcon#about to read 6, iclass 38, count 0 2006.196.08:16:21.92#ibcon#read 6, iclass 38, count 0 2006.196.08:16:21.92#ibcon#end of sib2, iclass 38, count 0 2006.196.08:16:21.92#ibcon#*mode == 0, iclass 38, count 0 2006.196.08:16:21.92#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.196.08:16:21.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.196.08:16:21.92#ibcon#*before write, iclass 38, count 0 2006.196.08:16:21.92#ibcon#enter sib2, iclass 38, count 0 2006.196.08:16:21.92#ibcon#flushed, iclass 38, count 0 2006.196.08:16:21.92#ibcon#about to write, iclass 38, count 0 2006.196.08:16:21.92#ibcon#wrote, iclass 38, count 0 2006.196.08:16:21.92#ibcon#about to read 3, iclass 38, count 0 2006.196.08:16:21.96#ibcon#read 3, iclass 38, count 0 2006.196.08:16:21.96#ibcon#about to read 4, iclass 38, count 0 2006.196.08:16:21.96#ibcon#read 4, iclass 38, count 0 2006.196.08:16:21.96#ibcon#about to read 5, iclass 38, count 0 2006.196.08:16:21.96#ibcon#read 5, iclass 38, count 0 2006.196.08:16:21.96#ibcon#about to read 6, iclass 38, count 0 2006.196.08:16:21.96#ibcon#read 6, iclass 38, count 0 2006.196.08:16:21.96#ibcon#end of sib2, iclass 38, count 0 2006.196.08:16:21.96#ibcon#*after write, iclass 38, count 0 2006.196.08:16:21.96#ibcon#*before return 0, iclass 38, count 0 2006.196.08:16:21.96#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.196.08:16:21.96#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.196.08:16:21.96#ibcon#about to clear, iclass 38 cls_cnt 0 2006.196.08:16:21.96#ibcon#cleared, iclass 38 cls_cnt 0 2006.196.08:16:21.96$vc4f8/vb=5,4 2006.196.08:16:21.96#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.196.08:16:21.96#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.196.08:16:21.96#ibcon#ireg 11 cls_cnt 2 2006.196.08:16:21.96#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.196.08:16:22.02#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.196.08:16:22.02#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.196.08:16:22.02#ibcon#enter wrdev, iclass 40, count 2 2006.196.08:16:22.02#ibcon#first serial, iclass 40, count 2 2006.196.08:16:22.02#ibcon#enter sib2, iclass 40, count 2 2006.196.08:16:22.02#ibcon#flushed, iclass 40, count 2 2006.196.08:16:22.02#ibcon#about to write, iclass 40, count 2 2006.196.08:16:22.02#ibcon#wrote, iclass 40, count 2 2006.196.08:16:22.02#ibcon#about to read 3, iclass 40, count 2 2006.196.08:16:22.04#ibcon#read 3, iclass 40, count 2 2006.196.08:16:22.04#ibcon#about to read 4, iclass 40, count 2 2006.196.08:16:22.04#ibcon#read 4, iclass 40, count 2 2006.196.08:16:22.04#ibcon#about to read 5, iclass 40, count 2 2006.196.08:16:22.04#ibcon#read 5, iclass 40, count 2 2006.196.08:16:22.04#ibcon#about to read 6, iclass 40, count 2 2006.196.08:16:22.04#ibcon#read 6, iclass 40, count 2 2006.196.08:16:22.04#ibcon#end of sib2, iclass 40, count 2 2006.196.08:16:22.04#ibcon#*mode == 0, iclass 40, count 2 2006.196.08:16:22.04#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.196.08:16:22.04#ibcon#[27=AT05-04\r\n] 2006.196.08:16:22.04#ibcon#*before write, iclass 40, count 2 2006.196.08:16:22.04#ibcon#enter sib2, iclass 40, count 2 2006.196.08:16:22.04#ibcon#flushed, iclass 40, count 2 2006.196.08:16:22.04#ibcon#about to write, iclass 40, count 2 2006.196.08:16:22.04#ibcon#wrote, iclass 40, count 2 2006.196.08:16:22.04#ibcon#about to read 3, iclass 40, count 2 2006.196.08:16:22.07#ibcon#read 3, iclass 40, count 2 2006.196.08:16:22.07#ibcon#about to read 4, iclass 40, count 2 2006.196.08:16:22.07#ibcon#read 4, iclass 40, count 2 2006.196.08:16:22.07#ibcon#about to read 5, iclass 40, count 2 2006.196.08:16:22.07#ibcon#read 5, iclass 40, count 2 2006.196.08:16:22.07#ibcon#about to read 6, iclass 40, count 2 2006.196.08:16:22.07#ibcon#read 6, iclass 40, count 2 2006.196.08:16:22.07#ibcon#end of sib2, iclass 40, count 2 2006.196.08:16:22.07#ibcon#*after write, iclass 40, count 2 2006.196.08:16:22.07#ibcon#*before return 0, iclass 40, count 2 2006.196.08:16:22.07#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.196.08:16:22.07#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.196.08:16:22.07#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.196.08:16:22.07#ibcon#ireg 7 cls_cnt 0 2006.196.08:16:22.07#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.196.08:16:22.19#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.196.08:16:22.19#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.196.08:16:22.19#ibcon#enter wrdev, iclass 40, count 0 2006.196.08:16:22.19#ibcon#first serial, iclass 40, count 0 2006.196.08:16:22.19#ibcon#enter sib2, iclass 40, count 0 2006.196.08:16:22.19#ibcon#flushed, iclass 40, count 0 2006.196.08:16:22.19#ibcon#about to write, iclass 40, count 0 2006.196.08:16:22.19#ibcon#wrote, iclass 40, count 0 2006.196.08:16:22.19#ibcon#about to read 3, iclass 40, count 0 2006.196.08:16:22.21#ibcon#read 3, iclass 40, count 0 2006.196.08:16:22.21#ibcon#about to read 4, iclass 40, count 0 2006.196.08:16:22.21#ibcon#read 4, iclass 40, count 0 2006.196.08:16:22.21#ibcon#about to read 5, iclass 40, count 0 2006.196.08:16:22.21#ibcon#read 5, iclass 40, count 0 2006.196.08:16:22.21#ibcon#about to read 6, iclass 40, count 0 2006.196.08:16:22.21#ibcon#read 6, iclass 40, count 0 2006.196.08:16:22.21#ibcon#end of sib2, iclass 40, count 0 2006.196.08:16:22.21#ibcon#*mode == 0, iclass 40, count 0 2006.196.08:16:22.21#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.196.08:16:22.21#ibcon#[27=USB\r\n] 2006.196.08:16:22.21#ibcon#*before write, iclass 40, count 0 2006.196.08:16:22.21#ibcon#enter sib2, iclass 40, count 0 2006.196.08:16:22.21#ibcon#flushed, iclass 40, count 0 2006.196.08:16:22.21#ibcon#about to write, iclass 40, count 0 2006.196.08:16:22.21#ibcon#wrote, iclass 40, count 0 2006.196.08:16:22.21#ibcon#about to read 3, iclass 40, count 0 2006.196.08:16:22.24#ibcon#read 3, iclass 40, count 0 2006.196.08:16:22.24#ibcon#about to read 4, iclass 40, count 0 2006.196.08:16:22.24#ibcon#read 4, iclass 40, count 0 2006.196.08:16:22.24#ibcon#about to read 5, iclass 40, count 0 2006.196.08:16:22.24#ibcon#read 5, iclass 40, count 0 2006.196.08:16:22.24#ibcon#about to read 6, iclass 40, count 0 2006.196.08:16:22.24#ibcon#read 6, iclass 40, count 0 2006.196.08:16:22.24#ibcon#end of sib2, iclass 40, count 0 2006.196.08:16:22.24#ibcon#*after write, iclass 40, count 0 2006.196.08:16:22.24#ibcon#*before return 0, iclass 40, count 0 2006.196.08:16:22.24#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.196.08:16:22.24#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.196.08:16:22.24#ibcon#about to clear, iclass 40 cls_cnt 0 2006.196.08:16:22.24#ibcon#cleared, iclass 40 cls_cnt 0 2006.196.08:16:22.24$vc4f8/vblo=6,752.99 2006.196.08:16:22.24#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.196.08:16:22.24#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.196.08:16:22.24#ibcon#ireg 17 cls_cnt 0 2006.196.08:16:22.24#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.196.08:16:22.24#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.196.08:16:22.24#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.196.08:16:22.24#ibcon#enter wrdev, iclass 4, count 0 2006.196.08:16:22.24#ibcon#first serial, iclass 4, count 0 2006.196.08:16:22.24#ibcon#enter sib2, iclass 4, count 0 2006.196.08:16:22.24#ibcon#flushed, iclass 4, count 0 2006.196.08:16:22.24#ibcon#about to write, iclass 4, count 0 2006.196.08:16:22.24#ibcon#wrote, iclass 4, count 0 2006.196.08:16:22.24#ibcon#about to read 3, iclass 4, count 0 2006.196.08:16:22.26#ibcon#read 3, iclass 4, count 0 2006.196.08:16:22.26#ibcon#about to read 4, iclass 4, count 0 2006.196.08:16:22.26#ibcon#read 4, iclass 4, count 0 2006.196.08:16:22.26#ibcon#about to read 5, iclass 4, count 0 2006.196.08:16:22.26#ibcon#read 5, iclass 4, count 0 2006.196.08:16:22.26#ibcon#about to read 6, iclass 4, count 0 2006.196.08:16:22.26#ibcon#read 6, iclass 4, count 0 2006.196.08:16:22.26#ibcon#end of sib2, iclass 4, count 0 2006.196.08:16:22.26#ibcon#*mode == 0, iclass 4, count 0 2006.196.08:16:22.26#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.196.08:16:22.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.196.08:16:22.26#ibcon#*before write, iclass 4, count 0 2006.196.08:16:22.26#ibcon#enter sib2, iclass 4, count 0 2006.196.08:16:22.26#ibcon#flushed, iclass 4, count 0 2006.196.08:16:22.26#ibcon#about to write, iclass 4, count 0 2006.196.08:16:22.26#ibcon#wrote, iclass 4, count 0 2006.196.08:16:22.26#ibcon#about to read 3, iclass 4, count 0 2006.196.08:16:22.30#ibcon#read 3, iclass 4, count 0 2006.196.08:16:22.30#ibcon#about to read 4, iclass 4, count 0 2006.196.08:16:22.30#ibcon#read 4, iclass 4, count 0 2006.196.08:16:22.30#ibcon#about to read 5, iclass 4, count 0 2006.196.08:16:22.30#ibcon#read 5, iclass 4, count 0 2006.196.08:16:22.30#ibcon#about to read 6, iclass 4, count 0 2006.196.08:16:22.30#ibcon#read 6, iclass 4, count 0 2006.196.08:16:22.30#ibcon#end of sib2, iclass 4, count 0 2006.196.08:16:22.30#ibcon#*after write, iclass 4, count 0 2006.196.08:16:22.30#ibcon#*before return 0, iclass 4, count 0 2006.196.08:16:22.30#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.196.08:16:22.30#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.196.08:16:22.30#ibcon#about to clear, iclass 4 cls_cnt 0 2006.196.08:16:22.30#ibcon#cleared, iclass 4 cls_cnt 0 2006.196.08:16:22.30$vc4f8/vb=6,4 2006.196.08:16:22.30#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.196.08:16:22.30#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.196.08:16:22.30#ibcon#ireg 11 cls_cnt 2 2006.196.08:16:22.30#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.196.08:16:22.36#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.196.08:16:22.36#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.196.08:16:22.36#ibcon#enter wrdev, iclass 6, count 2 2006.196.08:16:22.36#ibcon#first serial, iclass 6, count 2 2006.196.08:16:22.36#ibcon#enter sib2, iclass 6, count 2 2006.196.08:16:22.36#ibcon#flushed, iclass 6, count 2 2006.196.08:16:22.36#ibcon#about to write, iclass 6, count 2 2006.196.08:16:22.36#ibcon#wrote, iclass 6, count 2 2006.196.08:16:22.36#ibcon#about to read 3, iclass 6, count 2 2006.196.08:16:22.38#ibcon#read 3, iclass 6, count 2 2006.196.08:16:22.38#ibcon#about to read 4, iclass 6, count 2 2006.196.08:16:22.38#ibcon#read 4, iclass 6, count 2 2006.196.08:16:22.38#ibcon#about to read 5, iclass 6, count 2 2006.196.08:16:22.38#ibcon#read 5, iclass 6, count 2 2006.196.08:16:22.38#ibcon#about to read 6, iclass 6, count 2 2006.196.08:16:22.38#ibcon#read 6, iclass 6, count 2 2006.196.08:16:22.38#ibcon#end of sib2, iclass 6, count 2 2006.196.08:16:22.38#ibcon#*mode == 0, iclass 6, count 2 2006.196.08:16:22.38#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.196.08:16:22.38#ibcon#[27=AT06-04\r\n] 2006.196.08:16:22.38#ibcon#*before write, iclass 6, count 2 2006.196.08:16:22.38#ibcon#enter sib2, iclass 6, count 2 2006.196.08:16:22.38#ibcon#flushed, iclass 6, count 2 2006.196.08:16:22.38#ibcon#about to write, iclass 6, count 2 2006.196.08:16:22.38#ibcon#wrote, iclass 6, count 2 2006.196.08:16:22.38#ibcon#about to read 3, iclass 6, count 2 2006.196.08:16:22.41#ibcon#read 3, iclass 6, count 2 2006.196.08:16:22.41#ibcon#about to read 4, iclass 6, count 2 2006.196.08:16:22.41#ibcon#read 4, iclass 6, count 2 2006.196.08:16:22.41#ibcon#about to read 5, iclass 6, count 2 2006.196.08:16:22.41#ibcon#read 5, iclass 6, count 2 2006.196.08:16:22.41#ibcon#about to read 6, iclass 6, count 2 2006.196.08:16:22.41#ibcon#read 6, iclass 6, count 2 2006.196.08:16:22.41#ibcon#end of sib2, iclass 6, count 2 2006.196.08:16:22.41#ibcon#*after write, iclass 6, count 2 2006.196.08:16:22.41#ibcon#*before return 0, iclass 6, count 2 2006.196.08:16:22.41#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.196.08:16:22.41#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.196.08:16:22.41#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.196.08:16:22.41#ibcon#ireg 7 cls_cnt 0 2006.196.08:16:22.41#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.196.08:16:22.53#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.196.08:16:22.53#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.196.08:16:22.53#ibcon#enter wrdev, iclass 6, count 0 2006.196.08:16:22.53#ibcon#first serial, iclass 6, count 0 2006.196.08:16:22.53#ibcon#enter sib2, iclass 6, count 0 2006.196.08:16:22.53#ibcon#flushed, iclass 6, count 0 2006.196.08:16:22.53#ibcon#about to write, iclass 6, count 0 2006.196.08:16:22.53#ibcon#wrote, iclass 6, count 0 2006.196.08:16:22.53#ibcon#about to read 3, iclass 6, count 0 2006.196.08:16:22.55#ibcon#read 3, iclass 6, count 0 2006.196.08:16:22.55#ibcon#about to read 4, iclass 6, count 0 2006.196.08:16:22.55#ibcon#read 4, iclass 6, count 0 2006.196.08:16:22.55#ibcon#about to read 5, iclass 6, count 0 2006.196.08:16:22.55#ibcon#read 5, iclass 6, count 0 2006.196.08:16:22.55#ibcon#about to read 6, iclass 6, count 0 2006.196.08:16:22.55#ibcon#read 6, iclass 6, count 0 2006.196.08:16:22.55#ibcon#end of sib2, iclass 6, count 0 2006.196.08:16:22.55#ibcon#*mode == 0, iclass 6, count 0 2006.196.08:16:22.55#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.196.08:16:22.55#ibcon#[27=USB\r\n] 2006.196.08:16:22.55#ibcon#*before write, iclass 6, count 0 2006.196.08:16:22.55#ibcon#enter sib2, iclass 6, count 0 2006.196.08:16:22.55#ibcon#flushed, iclass 6, count 0 2006.196.08:16:22.55#ibcon#about to write, iclass 6, count 0 2006.196.08:16:22.55#ibcon#wrote, iclass 6, count 0 2006.196.08:16:22.55#ibcon#about to read 3, iclass 6, count 0 2006.196.08:16:22.58#ibcon#read 3, iclass 6, count 0 2006.196.08:16:22.58#ibcon#about to read 4, iclass 6, count 0 2006.196.08:16:22.58#ibcon#read 4, iclass 6, count 0 2006.196.08:16:22.58#ibcon#about to read 5, iclass 6, count 0 2006.196.08:16:22.58#ibcon#read 5, iclass 6, count 0 2006.196.08:16:22.58#ibcon#about to read 6, iclass 6, count 0 2006.196.08:16:22.58#ibcon#read 6, iclass 6, count 0 2006.196.08:16:22.58#ibcon#end of sib2, iclass 6, count 0 2006.196.08:16:22.58#ibcon#*after write, iclass 6, count 0 2006.196.08:16:22.58#ibcon#*before return 0, iclass 6, count 0 2006.196.08:16:22.58#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.196.08:16:22.58#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.196.08:16:22.58#ibcon#about to clear, iclass 6 cls_cnt 0 2006.196.08:16:22.58#ibcon#cleared, iclass 6 cls_cnt 0 2006.196.08:16:22.58$vc4f8/vabw=wide 2006.196.08:16:22.58#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.196.08:16:22.58#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.196.08:16:22.58#ibcon#ireg 8 cls_cnt 0 2006.196.08:16:22.58#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.196.08:16:22.58#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.196.08:16:22.58#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.196.08:16:22.58#ibcon#enter wrdev, iclass 10, count 0 2006.196.08:16:22.58#ibcon#first serial, iclass 10, count 0 2006.196.08:16:22.58#ibcon#enter sib2, iclass 10, count 0 2006.196.08:16:22.58#ibcon#flushed, iclass 10, count 0 2006.196.08:16:22.58#ibcon#about to write, iclass 10, count 0 2006.196.08:16:22.58#ibcon#wrote, iclass 10, count 0 2006.196.08:16:22.58#ibcon#about to read 3, iclass 10, count 0 2006.196.08:16:22.60#ibcon#read 3, iclass 10, count 0 2006.196.08:16:22.60#ibcon#about to read 4, iclass 10, count 0 2006.196.08:16:22.60#ibcon#read 4, iclass 10, count 0 2006.196.08:16:22.60#ibcon#about to read 5, iclass 10, count 0 2006.196.08:16:22.60#ibcon#read 5, iclass 10, count 0 2006.196.08:16:22.60#ibcon#about to read 6, iclass 10, count 0 2006.196.08:16:22.60#ibcon#read 6, iclass 10, count 0 2006.196.08:16:22.60#ibcon#end of sib2, iclass 10, count 0 2006.196.08:16:22.60#ibcon#*mode == 0, iclass 10, count 0 2006.196.08:16:22.60#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.196.08:16:22.60#ibcon#[25=BW32\r\n] 2006.196.08:16:22.60#ibcon#*before write, iclass 10, count 0 2006.196.08:16:22.60#ibcon#enter sib2, iclass 10, count 0 2006.196.08:16:22.60#ibcon#flushed, iclass 10, count 0 2006.196.08:16:22.60#ibcon#about to write, iclass 10, count 0 2006.196.08:16:22.60#ibcon#wrote, iclass 10, count 0 2006.196.08:16:22.60#ibcon#about to read 3, iclass 10, count 0 2006.196.08:16:22.63#ibcon#read 3, iclass 10, count 0 2006.196.08:16:22.63#ibcon#about to read 4, iclass 10, count 0 2006.196.08:16:22.63#ibcon#read 4, iclass 10, count 0 2006.196.08:16:22.63#ibcon#about to read 5, iclass 10, count 0 2006.196.08:16:22.63#ibcon#read 5, iclass 10, count 0 2006.196.08:16:22.63#ibcon#about to read 6, iclass 10, count 0 2006.196.08:16:22.63#ibcon#read 6, iclass 10, count 0 2006.196.08:16:22.63#ibcon#end of sib2, iclass 10, count 0 2006.196.08:16:22.63#ibcon#*after write, iclass 10, count 0 2006.196.08:16:22.63#ibcon#*before return 0, iclass 10, count 0 2006.196.08:16:22.63#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.196.08:16:22.63#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.196.08:16:22.63#ibcon#about to clear, iclass 10 cls_cnt 0 2006.196.08:16:22.63#ibcon#cleared, iclass 10 cls_cnt 0 2006.196.08:16:22.63$vc4f8/vbbw=wide 2006.196.08:16:22.63#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.196.08:16:22.63#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.196.08:16:22.63#ibcon#ireg 8 cls_cnt 0 2006.196.08:16:22.63#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.196.08:16:22.70#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.196.08:16:22.70#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.196.08:16:22.70#ibcon#enter wrdev, iclass 12, count 0 2006.196.08:16:22.70#ibcon#first serial, iclass 12, count 0 2006.196.08:16:22.70#ibcon#enter sib2, iclass 12, count 0 2006.196.08:16:22.70#ibcon#flushed, iclass 12, count 0 2006.196.08:16:22.70#ibcon#about to write, iclass 12, count 0 2006.196.08:16:22.70#ibcon#wrote, iclass 12, count 0 2006.196.08:16:22.70#ibcon#about to read 3, iclass 12, count 0 2006.196.08:16:22.72#ibcon#read 3, iclass 12, count 0 2006.196.08:16:22.72#ibcon#about to read 4, iclass 12, count 0 2006.196.08:16:22.72#ibcon#read 4, iclass 12, count 0 2006.196.08:16:22.72#ibcon#about to read 5, iclass 12, count 0 2006.196.08:16:22.72#ibcon#read 5, iclass 12, count 0 2006.196.08:16:22.72#ibcon#about to read 6, iclass 12, count 0 2006.196.08:16:22.72#ibcon#read 6, iclass 12, count 0 2006.196.08:16:22.72#ibcon#end of sib2, iclass 12, count 0 2006.196.08:16:22.72#ibcon#*mode == 0, iclass 12, count 0 2006.196.08:16:22.72#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.196.08:16:22.72#ibcon#[27=BW32\r\n] 2006.196.08:16:22.72#ibcon#*before write, iclass 12, count 0 2006.196.08:16:22.72#ibcon#enter sib2, iclass 12, count 0 2006.196.08:16:22.72#ibcon#flushed, iclass 12, count 0 2006.196.08:16:22.72#ibcon#about to write, iclass 12, count 0 2006.196.08:16:22.72#ibcon#wrote, iclass 12, count 0 2006.196.08:16:22.72#ibcon#about to read 3, iclass 12, count 0 2006.196.08:16:22.75#ibcon#read 3, iclass 12, count 0 2006.196.08:16:22.75#ibcon#about to read 4, iclass 12, count 0 2006.196.08:16:22.75#ibcon#read 4, iclass 12, count 0 2006.196.08:16:22.75#ibcon#about to read 5, iclass 12, count 0 2006.196.08:16:22.75#ibcon#read 5, iclass 12, count 0 2006.196.08:16:22.75#ibcon#about to read 6, iclass 12, count 0 2006.196.08:16:22.75#ibcon#read 6, iclass 12, count 0 2006.196.08:16:22.75#ibcon#end of sib2, iclass 12, count 0 2006.196.08:16:22.75#ibcon#*after write, iclass 12, count 0 2006.196.08:16:22.75#ibcon#*before return 0, iclass 12, count 0 2006.196.08:16:22.75#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.196.08:16:22.75#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.196.08:16:22.75#ibcon#about to clear, iclass 12 cls_cnt 0 2006.196.08:16:22.75#ibcon#cleared, iclass 12 cls_cnt 0 2006.196.08:16:22.75$4f8m12a/ifd4f 2006.196.08:16:22.75$ifd4f/lo= 2006.196.08:16:22.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.196.08:16:22.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.196.08:16:22.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.196.08:16:22.75$ifd4f/patch= 2006.196.08:16:22.75$ifd4f/patch=lo1,a1,a2,a3,a4 2006.196.08:16:22.75$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.196.08:16:22.75$ifd4f/patch=lo3,a5,a6,a7,a8 2006.196.08:16:22.75$4f8m12a/"form=m,16.000,1:2 2006.196.08:16:22.75$4f8m12a/"tpicd 2006.196.08:16:22.75$4f8m12a/echo=off 2006.196.08:16:22.75$4f8m12a/xlog=off 2006.196.08:16:22.75:!2006.196.08:16:50 2006.196.08:16:32.14#trakl#Source acquired 2006.196.08:16:32.14#flagr#flagr/antenna,acquired 2006.196.08:16:50.00:preob 2006.196.08:16:51.14/onsource/TRACKING 2006.196.08:16:51.14:!2006.196.08:17:00 2006.196.08:17:00.00:data_valid=on 2006.196.08:17:00.00:midob 2006.196.08:17:00.14/onsource/TRACKING 2006.196.08:17:00.14/wx/29.04,1004.0,74 2006.196.08:17:00.27/cable/+6.3366E-03 2006.196.08:17:01.36/va/01,08,usb,yes,47,50 2006.196.08:17:01.36/va/02,07,usb,yes,48,50 2006.196.08:17:01.36/va/03,06,usb,yes,51,51 2006.196.08:17:01.36/va/04,07,usb,yes,49,53 2006.196.08:17:01.36/va/05,07,usb,yes,53,56 2006.196.08:17:01.36/va/06,06,usb,yes,52,52 2006.196.08:17:01.36/va/07,06,usb,yes,53,53 2006.196.08:17:01.36/va/08,07,usb,yes,50,50 2006.196.08:17:01.59/valo/01,532.99,yes,locked 2006.196.08:17:01.59/valo/02,572.99,yes,locked 2006.196.08:17:01.59/valo/03,672.99,yes,locked 2006.196.08:17:01.59/valo/04,832.99,yes,locked 2006.196.08:17:01.59/valo/05,652.99,yes,locked 2006.196.08:17:01.59/valo/06,772.99,yes,locked 2006.196.08:17:01.59/valo/07,832.99,yes,locked 2006.196.08:17:01.59/valo/08,852.99,yes,locked 2006.196.08:17:02.68/vb/01,04,usb,yes,40,38 2006.196.08:17:02.68/vb/02,04,usb,yes,42,44 2006.196.08:17:02.68/vb/03,04,usb,yes,38,43 2006.196.08:17:02.68/vb/04,04,usb,yes,39,39 2006.196.08:17:02.68/vb/05,04,usb,yes,37,42 2006.196.08:17:02.68/vb/06,04,usb,yes,38,42 2006.196.08:17:02.68/vb/07,04,usb,yes,41,41 2006.196.08:17:02.68/vb/08,04,usb,yes,37,42 2006.196.08:17:02.91/vblo/01,632.99,yes,locked 2006.196.08:17:02.91/vblo/02,640.99,yes,locked 2006.196.08:17:02.91/vblo/03,656.99,yes,locked 2006.196.08:17:02.91/vblo/04,712.99,yes,locked 2006.196.08:17:02.91/vblo/05,744.99,yes,locked 2006.196.08:17:02.91/vblo/06,752.99,yes,locked 2006.196.08:17:02.91/vblo/07,734.99,yes,locked 2006.196.08:17:02.91/vblo/08,744.99,yes,locked 2006.196.08:17:03.06/vabw/8 2006.196.08:17:03.21/vbbw/8 2006.196.08:17:03.30/xfe/off,on,15.2 2006.196.08:17:03.67/ifatt/23,28,28,28 2006.196.08:17:04.06/fmout-gps/S +3.33E-07 2006.196.08:17:04.12:!2006.196.08:18:00 2006.196.08:17:29.07?ERROR st -97 Trouble decoding pressure data 2006.196.08:17:29.07#wxget#05 4.2 6.8 29.03 931004.0 2006.196.08:18:00.00:data_valid=off 2006.196.08:18:00.00:postob 2006.196.08:18:00.22/cable/+6.3389E-03 2006.196.08:18:00.22/wx/29.01,1004.0,93 2006.196.08:18:01.06/fmout-gps/S +3.32E-07 2006.196.08:18:01.06:scan_name=196-0818,k06196,60 2006.196.08:18:01.06:source=oj287,085448.87,200630.6,2000.0,ccw 2006.196.08:18:01.14#flagr#flagr/antenna,new-source 2006.196.08:18:02.14:checkk5 2006.196.08:18:02.51/chk_autoobs//k5ts1/ autoobs is running! 2006.196.08:18:02.89/chk_autoobs//k5ts2/ autoobs is running! 2006.196.08:18:03.27/chk_autoobs//k5ts3/ autoobs is running! 2006.196.08:18:03.64/chk_autoobs//k5ts4/ autoobs is running! 2006.196.08:18:04.01/chk_obsdata//k5ts1/T1960817??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.08:18:04.39/chk_obsdata//k5ts2/T1960817??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.08:18:04.76/chk_obsdata//k5ts3/T1960817??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.08:18:05.13/chk_obsdata//k5ts4/T1960817??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.08:18:05.82/k5log//k5ts1_log_newline 2006.196.08:18:06.51/k5log//k5ts2_log_newline 2006.196.08:18:07.20/k5log//k5ts3_log_newline 2006.196.08:18:07.88/k5log//k5ts4_log_newline 2006.196.08:18:07.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.196.08:18:07.91:4f8m12a=2 2006.196.08:18:07.91$4f8m12a/echo=on 2006.196.08:18:07.91$4f8m12a/pcalon 2006.196.08:18:07.91$pcalon/"no phase cal control is implemented here 2006.196.08:18:07.91$4f8m12a/"tpicd=stop 2006.196.08:18:07.91$4f8m12a/vc4f8 2006.196.08:18:07.91$vc4f8/valo=1,532.99 2006.196.08:18:07.91#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.196.08:18:07.91#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.196.08:18:07.91#ibcon#ireg 17 cls_cnt 0 2006.196.08:18:07.91#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.196.08:18:07.91#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.196.08:18:07.91#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.196.08:18:07.91#ibcon#enter wrdev, iclass 12, count 0 2006.196.08:18:07.91#ibcon#first serial, iclass 12, count 0 2006.196.08:18:07.91#ibcon#enter sib2, iclass 12, count 0 2006.196.08:18:07.91#ibcon#flushed, iclass 12, count 0 2006.196.08:18:07.91#ibcon#about to write, iclass 12, count 0 2006.196.08:18:07.91#ibcon#wrote, iclass 12, count 0 2006.196.08:18:07.91#ibcon#about to read 3, iclass 12, count 0 2006.196.08:18:07.93#ibcon#read 3, iclass 12, count 0 2006.196.08:18:07.93#ibcon#about to read 4, iclass 12, count 0 2006.196.08:18:07.93#ibcon#read 4, iclass 12, count 0 2006.196.08:18:07.93#ibcon#about to read 5, iclass 12, count 0 2006.196.08:18:07.93#ibcon#read 5, iclass 12, count 0 2006.196.08:18:07.93#ibcon#about to read 6, iclass 12, count 0 2006.196.08:18:07.93#ibcon#read 6, iclass 12, count 0 2006.196.08:18:07.93#ibcon#end of sib2, iclass 12, count 0 2006.196.08:18:07.93#ibcon#*mode == 0, iclass 12, count 0 2006.196.08:18:07.93#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.196.08:18:07.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.196.08:18:07.93#ibcon#*before write, iclass 12, count 0 2006.196.08:18:07.93#ibcon#enter sib2, iclass 12, count 0 2006.196.08:18:07.93#ibcon#flushed, iclass 12, count 0 2006.196.08:18:07.93#ibcon#about to write, iclass 12, count 0 2006.196.08:18:07.93#ibcon#wrote, iclass 12, count 0 2006.196.08:18:07.93#ibcon#about to read 3, iclass 12, count 0 2006.196.08:18:07.98#ibcon#read 3, iclass 12, count 0 2006.196.08:18:07.98#ibcon#about to read 4, iclass 12, count 0 2006.196.08:18:07.98#ibcon#read 4, iclass 12, count 0 2006.196.08:18:07.98#ibcon#about to read 5, iclass 12, count 0 2006.196.08:18:07.98#ibcon#read 5, iclass 12, count 0 2006.196.08:18:07.98#ibcon#about to read 6, iclass 12, count 0 2006.196.08:18:07.98#ibcon#read 6, iclass 12, count 0 2006.196.08:18:07.98#ibcon#end of sib2, iclass 12, count 0 2006.196.08:18:07.98#ibcon#*after write, iclass 12, count 0 2006.196.08:18:07.98#ibcon#*before return 0, iclass 12, count 0 2006.196.08:18:07.98#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.196.08:18:07.98#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.196.08:18:07.98#ibcon#about to clear, iclass 12 cls_cnt 0 2006.196.08:18:07.98#ibcon#cleared, iclass 12 cls_cnt 0 2006.196.08:18:07.98$vc4f8/va=1,8 2006.196.08:18:07.98#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.196.08:18:07.98#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.196.08:18:07.98#ibcon#ireg 11 cls_cnt 2 2006.196.08:18:07.98#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.196.08:18:07.98#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.196.08:18:07.98#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.196.08:18:07.98#ibcon#enter wrdev, iclass 14, count 2 2006.196.08:18:07.98#ibcon#first serial, iclass 14, count 2 2006.196.08:18:07.98#ibcon#enter sib2, iclass 14, count 2 2006.196.08:18:07.98#ibcon#flushed, iclass 14, count 2 2006.196.08:18:07.98#ibcon#about to write, iclass 14, count 2 2006.196.08:18:07.98#ibcon#wrote, iclass 14, count 2 2006.196.08:18:07.98#ibcon#about to read 3, iclass 14, count 2 2006.196.08:18:08.00#ibcon#read 3, iclass 14, count 2 2006.196.08:18:08.00#ibcon#about to read 4, iclass 14, count 2 2006.196.08:18:08.00#ibcon#read 4, iclass 14, count 2 2006.196.08:18:08.00#ibcon#about to read 5, iclass 14, count 2 2006.196.08:18:08.00#ibcon#read 5, iclass 14, count 2 2006.196.08:18:08.00#ibcon#about to read 6, iclass 14, count 2 2006.196.08:18:08.00#ibcon#read 6, iclass 14, count 2 2006.196.08:18:08.00#ibcon#end of sib2, iclass 14, count 2 2006.196.08:18:08.00#ibcon#*mode == 0, iclass 14, count 2 2006.196.08:18:08.00#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.196.08:18:08.00#ibcon#[25=AT01-08\r\n] 2006.196.08:18:08.00#ibcon#*before write, iclass 14, count 2 2006.196.08:18:08.00#ibcon#enter sib2, iclass 14, count 2 2006.196.08:18:08.00#ibcon#flushed, iclass 14, count 2 2006.196.08:18:08.00#ibcon#about to write, iclass 14, count 2 2006.196.08:18:08.00#ibcon#wrote, iclass 14, count 2 2006.196.08:18:08.00#ibcon#about to read 3, iclass 14, count 2 2006.196.08:18:08.03#ibcon#read 3, iclass 14, count 2 2006.196.08:18:08.03#ibcon#about to read 4, iclass 14, count 2 2006.196.08:18:08.03#ibcon#read 4, iclass 14, count 2 2006.196.08:18:08.03#ibcon#about to read 5, iclass 14, count 2 2006.196.08:18:08.03#ibcon#read 5, iclass 14, count 2 2006.196.08:18:08.03#ibcon#about to read 6, iclass 14, count 2 2006.196.08:18:08.03#ibcon#read 6, iclass 14, count 2 2006.196.08:18:08.03#ibcon#end of sib2, iclass 14, count 2 2006.196.08:18:08.03#ibcon#*after write, iclass 14, count 2 2006.196.08:18:08.03#ibcon#*before return 0, iclass 14, count 2 2006.196.08:18:08.03#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.196.08:18:08.03#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.196.08:18:08.03#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.196.08:18:08.03#ibcon#ireg 7 cls_cnt 0 2006.196.08:18:08.03#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.196.08:18:08.15#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.196.08:18:08.15#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.196.08:18:08.15#ibcon#enter wrdev, iclass 14, count 0 2006.196.08:18:08.15#ibcon#first serial, iclass 14, count 0 2006.196.08:18:08.15#ibcon#enter sib2, iclass 14, count 0 2006.196.08:18:08.15#ibcon#flushed, iclass 14, count 0 2006.196.08:18:08.15#ibcon#about to write, iclass 14, count 0 2006.196.08:18:08.15#ibcon#wrote, iclass 14, count 0 2006.196.08:18:08.15#ibcon#about to read 3, iclass 14, count 0 2006.196.08:18:08.17#ibcon#read 3, iclass 14, count 0 2006.196.08:18:08.17#ibcon#about to read 4, iclass 14, count 0 2006.196.08:18:08.17#ibcon#read 4, iclass 14, count 0 2006.196.08:18:08.17#ibcon#about to read 5, iclass 14, count 0 2006.196.08:18:08.17#ibcon#read 5, iclass 14, count 0 2006.196.08:18:08.17#ibcon#about to read 6, iclass 14, count 0 2006.196.08:18:08.17#ibcon#read 6, iclass 14, count 0 2006.196.08:18:08.17#ibcon#end of sib2, iclass 14, count 0 2006.196.08:18:08.17#ibcon#*mode == 0, iclass 14, count 0 2006.196.08:18:08.17#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.196.08:18:08.17#ibcon#[25=USB\r\n] 2006.196.08:18:08.17#ibcon#*before write, iclass 14, count 0 2006.196.08:18:08.17#ibcon#enter sib2, iclass 14, count 0 2006.196.08:18:08.17#ibcon#flushed, iclass 14, count 0 2006.196.08:18:08.17#ibcon#about to write, iclass 14, count 0 2006.196.08:18:08.17#ibcon#wrote, iclass 14, count 0 2006.196.08:18:08.17#ibcon#about to read 3, iclass 14, count 0 2006.196.08:18:08.20#ibcon#read 3, iclass 14, count 0 2006.196.08:18:08.20#ibcon#about to read 4, iclass 14, count 0 2006.196.08:18:08.20#ibcon#read 4, iclass 14, count 0 2006.196.08:18:08.20#ibcon#about to read 5, iclass 14, count 0 2006.196.08:18:08.20#ibcon#read 5, iclass 14, count 0 2006.196.08:18:08.20#ibcon#about to read 6, iclass 14, count 0 2006.196.08:18:08.20#ibcon#read 6, iclass 14, count 0 2006.196.08:18:08.20#ibcon#end of sib2, iclass 14, count 0 2006.196.08:18:08.20#ibcon#*after write, iclass 14, count 0 2006.196.08:18:08.20#ibcon#*before return 0, iclass 14, count 0 2006.196.08:18:08.20#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.196.08:18:08.20#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.196.08:18:08.20#ibcon#about to clear, iclass 14 cls_cnt 0 2006.196.08:18:08.20#ibcon#cleared, iclass 14 cls_cnt 0 2006.196.08:18:08.20$vc4f8/valo=2,572.99 2006.196.08:18:08.20#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.196.08:18:08.20#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.196.08:18:08.20#ibcon#ireg 17 cls_cnt 0 2006.196.08:18:08.20#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.196.08:18:08.20#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.196.08:18:08.20#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.196.08:18:08.20#ibcon#enter wrdev, iclass 16, count 0 2006.196.08:18:08.20#ibcon#first serial, iclass 16, count 0 2006.196.08:18:08.20#ibcon#enter sib2, iclass 16, count 0 2006.196.08:18:08.20#ibcon#flushed, iclass 16, count 0 2006.196.08:18:08.20#ibcon#about to write, iclass 16, count 0 2006.196.08:18:08.20#ibcon#wrote, iclass 16, count 0 2006.196.08:18:08.20#ibcon#about to read 3, iclass 16, count 0 2006.196.08:18:08.22#ibcon#read 3, iclass 16, count 0 2006.196.08:18:08.22#ibcon#about to read 4, iclass 16, count 0 2006.196.08:18:08.22#ibcon#read 4, iclass 16, count 0 2006.196.08:18:08.22#ibcon#about to read 5, iclass 16, count 0 2006.196.08:18:08.22#ibcon#read 5, iclass 16, count 0 2006.196.08:18:08.22#ibcon#about to read 6, iclass 16, count 0 2006.196.08:18:08.22#ibcon#read 6, iclass 16, count 0 2006.196.08:18:08.22#ibcon#end of sib2, iclass 16, count 0 2006.196.08:18:08.22#ibcon#*mode == 0, iclass 16, count 0 2006.196.08:18:08.22#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.196.08:18:08.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.196.08:18:08.22#ibcon#*before write, iclass 16, count 0 2006.196.08:18:08.22#ibcon#enter sib2, iclass 16, count 0 2006.196.08:18:08.22#ibcon#flushed, iclass 16, count 0 2006.196.08:18:08.22#ibcon#about to write, iclass 16, count 0 2006.196.08:18:08.22#ibcon#wrote, iclass 16, count 0 2006.196.08:18:08.22#ibcon#about to read 3, iclass 16, count 0 2006.196.08:18:08.27#ibcon#read 3, iclass 16, count 0 2006.196.08:18:08.27#ibcon#about to read 4, iclass 16, count 0 2006.196.08:18:08.27#ibcon#read 4, iclass 16, count 0 2006.196.08:18:08.27#ibcon#about to read 5, iclass 16, count 0 2006.196.08:18:08.27#ibcon#read 5, iclass 16, count 0 2006.196.08:18:08.27#ibcon#about to read 6, iclass 16, count 0 2006.196.08:18:08.27#ibcon#read 6, iclass 16, count 0 2006.196.08:18:08.27#ibcon#end of sib2, iclass 16, count 0 2006.196.08:18:08.27#ibcon#*after write, iclass 16, count 0 2006.196.08:18:08.27#ibcon#*before return 0, iclass 16, count 0 2006.196.08:18:08.27#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.196.08:18:08.27#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.196.08:18:08.27#ibcon#about to clear, iclass 16 cls_cnt 0 2006.196.08:18:08.27#ibcon#cleared, iclass 16 cls_cnt 0 2006.196.08:18:08.27$vc4f8/va=2,7 2006.196.08:18:08.27#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.196.08:18:08.27#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.196.08:18:08.27#ibcon#ireg 11 cls_cnt 2 2006.196.08:18:08.27#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.196.08:18:08.32#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.196.08:18:08.32#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.196.08:18:08.32#ibcon#enter wrdev, iclass 18, count 2 2006.196.08:18:08.32#ibcon#first serial, iclass 18, count 2 2006.196.08:18:08.32#ibcon#enter sib2, iclass 18, count 2 2006.196.08:18:08.32#ibcon#flushed, iclass 18, count 2 2006.196.08:18:08.32#ibcon#about to write, iclass 18, count 2 2006.196.08:18:08.32#ibcon#wrote, iclass 18, count 2 2006.196.08:18:08.32#ibcon#about to read 3, iclass 18, count 2 2006.196.08:18:08.34#ibcon#read 3, iclass 18, count 2 2006.196.08:18:08.34#ibcon#about to read 4, iclass 18, count 2 2006.196.08:18:08.34#ibcon#read 4, iclass 18, count 2 2006.196.08:18:08.34#ibcon#about to read 5, iclass 18, count 2 2006.196.08:18:08.34#ibcon#read 5, iclass 18, count 2 2006.196.08:18:08.34#ibcon#about to read 6, iclass 18, count 2 2006.196.08:18:08.34#ibcon#read 6, iclass 18, count 2 2006.196.08:18:08.34#ibcon#end of sib2, iclass 18, count 2 2006.196.08:18:08.34#ibcon#*mode == 0, iclass 18, count 2 2006.196.08:18:08.34#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.196.08:18:08.34#ibcon#[25=AT02-07\r\n] 2006.196.08:18:08.34#ibcon#*before write, iclass 18, count 2 2006.196.08:18:08.34#ibcon#enter sib2, iclass 18, count 2 2006.196.08:18:08.34#ibcon#flushed, iclass 18, count 2 2006.196.08:18:08.34#ibcon#about to write, iclass 18, count 2 2006.196.08:18:08.34#ibcon#wrote, iclass 18, count 2 2006.196.08:18:08.34#ibcon#about to read 3, iclass 18, count 2 2006.196.08:18:08.37#ibcon#read 3, iclass 18, count 2 2006.196.08:18:08.37#ibcon#about to read 4, iclass 18, count 2 2006.196.08:18:08.37#ibcon#read 4, iclass 18, count 2 2006.196.08:18:08.37#ibcon#about to read 5, iclass 18, count 2 2006.196.08:18:08.37#ibcon#read 5, iclass 18, count 2 2006.196.08:18:08.37#ibcon#about to read 6, iclass 18, count 2 2006.196.08:18:08.37#ibcon#read 6, iclass 18, count 2 2006.196.08:18:08.37#ibcon#end of sib2, iclass 18, count 2 2006.196.08:18:08.37#ibcon#*after write, iclass 18, count 2 2006.196.08:18:08.37#ibcon#*before return 0, iclass 18, count 2 2006.196.08:18:08.37#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.196.08:18:08.37#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.196.08:18:08.37#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.196.08:18:08.37#ibcon#ireg 7 cls_cnt 0 2006.196.08:18:08.37#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.196.08:18:08.49#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.196.08:18:08.49#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.196.08:18:08.49#ibcon#enter wrdev, iclass 18, count 0 2006.196.08:18:08.49#ibcon#first serial, iclass 18, count 0 2006.196.08:18:08.49#ibcon#enter sib2, iclass 18, count 0 2006.196.08:18:08.49#ibcon#flushed, iclass 18, count 0 2006.196.08:18:08.49#ibcon#about to write, iclass 18, count 0 2006.196.08:18:08.49#ibcon#wrote, iclass 18, count 0 2006.196.08:18:08.49#ibcon#about to read 3, iclass 18, count 0 2006.196.08:18:08.51#ibcon#read 3, iclass 18, count 0 2006.196.08:18:08.51#ibcon#about to read 4, iclass 18, count 0 2006.196.08:18:08.51#ibcon#read 4, iclass 18, count 0 2006.196.08:18:08.51#ibcon#about to read 5, iclass 18, count 0 2006.196.08:18:08.51#ibcon#read 5, iclass 18, count 0 2006.196.08:18:08.51#ibcon#about to read 6, iclass 18, count 0 2006.196.08:18:08.51#ibcon#read 6, iclass 18, count 0 2006.196.08:18:08.51#ibcon#end of sib2, iclass 18, count 0 2006.196.08:18:08.51#ibcon#*mode == 0, iclass 18, count 0 2006.196.08:18:08.51#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.196.08:18:08.51#ibcon#[25=USB\r\n] 2006.196.08:18:08.51#ibcon#*before write, iclass 18, count 0 2006.196.08:18:08.51#ibcon#enter sib2, iclass 18, count 0 2006.196.08:18:08.51#ibcon#flushed, iclass 18, count 0 2006.196.08:18:08.51#ibcon#about to write, iclass 18, count 0 2006.196.08:18:08.51#ibcon#wrote, iclass 18, count 0 2006.196.08:18:08.51#ibcon#about to read 3, iclass 18, count 0 2006.196.08:18:08.54#ibcon#read 3, iclass 18, count 0 2006.196.08:18:08.54#ibcon#about to read 4, iclass 18, count 0 2006.196.08:18:08.54#ibcon#read 4, iclass 18, count 0 2006.196.08:18:08.54#ibcon#about to read 5, iclass 18, count 0 2006.196.08:18:08.54#ibcon#read 5, iclass 18, count 0 2006.196.08:18:08.54#ibcon#about to read 6, iclass 18, count 0 2006.196.08:18:08.54#ibcon#read 6, iclass 18, count 0 2006.196.08:18:08.54#ibcon#end of sib2, iclass 18, count 0 2006.196.08:18:08.54#ibcon#*after write, iclass 18, count 0 2006.196.08:18:08.54#ibcon#*before return 0, iclass 18, count 0 2006.196.08:18:08.54#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.196.08:18:08.54#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.196.08:18:08.54#ibcon#about to clear, iclass 18 cls_cnt 0 2006.196.08:18:08.54#ibcon#cleared, iclass 18 cls_cnt 0 2006.196.08:18:08.54$vc4f8/valo=3,672.99 2006.196.08:18:08.54#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.196.08:18:08.54#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.196.08:18:08.54#ibcon#ireg 17 cls_cnt 0 2006.196.08:18:08.54#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.196.08:18:08.54#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.196.08:18:08.54#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.196.08:18:08.54#ibcon#enter wrdev, iclass 20, count 0 2006.196.08:18:08.54#ibcon#first serial, iclass 20, count 0 2006.196.08:18:08.54#ibcon#enter sib2, iclass 20, count 0 2006.196.08:18:08.54#ibcon#flushed, iclass 20, count 0 2006.196.08:18:08.54#ibcon#about to write, iclass 20, count 0 2006.196.08:18:08.54#ibcon#wrote, iclass 20, count 0 2006.196.08:18:08.54#ibcon#about to read 3, iclass 20, count 0 2006.196.08:18:08.56#ibcon#read 3, iclass 20, count 0 2006.196.08:18:08.56#ibcon#about to read 4, iclass 20, count 0 2006.196.08:18:08.56#ibcon#read 4, iclass 20, count 0 2006.196.08:18:08.56#ibcon#about to read 5, iclass 20, count 0 2006.196.08:18:08.56#ibcon#read 5, iclass 20, count 0 2006.196.08:18:08.56#ibcon#about to read 6, iclass 20, count 0 2006.196.08:18:08.56#ibcon#read 6, iclass 20, count 0 2006.196.08:18:08.56#ibcon#end of sib2, iclass 20, count 0 2006.196.08:18:08.56#ibcon#*mode == 0, iclass 20, count 0 2006.196.08:18:08.56#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.196.08:18:08.56#ibcon#[26=FRQ=03,672.99\r\n] 2006.196.08:18:08.56#ibcon#*before write, iclass 20, count 0 2006.196.08:18:08.56#ibcon#enter sib2, iclass 20, count 0 2006.196.08:18:08.56#ibcon#flushed, iclass 20, count 0 2006.196.08:18:08.56#ibcon#about to write, iclass 20, count 0 2006.196.08:18:08.56#ibcon#wrote, iclass 20, count 0 2006.196.08:18:08.56#ibcon#about to read 3, iclass 20, count 0 2006.196.08:18:08.60#ibcon#read 3, iclass 20, count 0 2006.196.08:18:08.60#ibcon#about to read 4, iclass 20, count 0 2006.196.08:18:08.60#ibcon#read 4, iclass 20, count 0 2006.196.08:18:08.60#ibcon#about to read 5, iclass 20, count 0 2006.196.08:18:08.60#ibcon#read 5, iclass 20, count 0 2006.196.08:18:08.60#ibcon#about to read 6, iclass 20, count 0 2006.196.08:18:08.60#ibcon#read 6, iclass 20, count 0 2006.196.08:18:08.60#ibcon#end of sib2, iclass 20, count 0 2006.196.08:18:08.60#ibcon#*after write, iclass 20, count 0 2006.196.08:18:08.60#ibcon#*before return 0, iclass 20, count 0 2006.196.08:18:08.60#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.196.08:18:08.60#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.196.08:18:08.60#ibcon#about to clear, iclass 20 cls_cnt 0 2006.196.08:18:08.60#ibcon#cleared, iclass 20 cls_cnt 0 2006.196.08:18:08.60$vc4f8/va=3,6 2006.196.08:18:08.60#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.196.08:18:08.60#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.196.08:18:08.60#ibcon#ireg 11 cls_cnt 2 2006.196.08:18:08.60#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.196.08:18:08.66#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.196.08:18:08.66#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.196.08:18:08.66#ibcon#enter wrdev, iclass 22, count 2 2006.196.08:18:08.66#ibcon#first serial, iclass 22, count 2 2006.196.08:18:08.66#ibcon#enter sib2, iclass 22, count 2 2006.196.08:18:08.66#ibcon#flushed, iclass 22, count 2 2006.196.08:18:08.66#ibcon#about to write, iclass 22, count 2 2006.196.08:18:08.66#ibcon#wrote, iclass 22, count 2 2006.196.08:18:08.66#ibcon#about to read 3, iclass 22, count 2 2006.196.08:18:08.68#ibcon#read 3, iclass 22, count 2 2006.196.08:18:08.68#ibcon#about to read 4, iclass 22, count 2 2006.196.08:18:08.68#ibcon#read 4, iclass 22, count 2 2006.196.08:18:08.68#ibcon#about to read 5, iclass 22, count 2 2006.196.08:18:08.68#ibcon#read 5, iclass 22, count 2 2006.196.08:18:08.68#ibcon#about to read 6, iclass 22, count 2 2006.196.08:18:08.68#ibcon#read 6, iclass 22, count 2 2006.196.08:18:08.68#ibcon#end of sib2, iclass 22, count 2 2006.196.08:18:08.68#ibcon#*mode == 0, iclass 22, count 2 2006.196.08:18:08.68#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.196.08:18:08.68#ibcon#[25=AT03-06\r\n] 2006.196.08:18:08.68#ibcon#*before write, iclass 22, count 2 2006.196.08:18:08.68#ibcon#enter sib2, iclass 22, count 2 2006.196.08:18:08.68#ibcon#flushed, iclass 22, count 2 2006.196.08:18:08.68#ibcon#about to write, iclass 22, count 2 2006.196.08:18:08.68#ibcon#wrote, iclass 22, count 2 2006.196.08:18:08.68#ibcon#about to read 3, iclass 22, count 2 2006.196.08:18:08.71#ibcon#read 3, iclass 22, count 2 2006.196.08:18:08.71#ibcon#about to read 4, iclass 22, count 2 2006.196.08:18:08.71#ibcon#read 4, iclass 22, count 2 2006.196.08:18:08.71#ibcon#about to read 5, iclass 22, count 2 2006.196.08:18:08.71#ibcon#read 5, iclass 22, count 2 2006.196.08:18:08.71#ibcon#about to read 6, iclass 22, count 2 2006.196.08:18:08.71#ibcon#read 6, iclass 22, count 2 2006.196.08:18:08.71#ibcon#end of sib2, iclass 22, count 2 2006.196.08:18:08.71#ibcon#*after write, iclass 22, count 2 2006.196.08:18:08.71#ibcon#*before return 0, iclass 22, count 2 2006.196.08:18:08.71#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.196.08:18:08.71#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.196.08:18:08.71#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.196.08:18:08.71#ibcon#ireg 7 cls_cnt 0 2006.196.08:18:08.71#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.196.08:18:08.83#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.196.08:18:08.83#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.196.08:18:08.83#ibcon#enter wrdev, iclass 22, count 0 2006.196.08:18:08.83#ibcon#first serial, iclass 22, count 0 2006.196.08:18:08.83#ibcon#enter sib2, iclass 22, count 0 2006.196.08:18:08.83#ibcon#flushed, iclass 22, count 0 2006.196.08:18:08.83#ibcon#about to write, iclass 22, count 0 2006.196.08:18:08.83#ibcon#wrote, iclass 22, count 0 2006.196.08:18:08.83#ibcon#about to read 3, iclass 22, count 0 2006.196.08:18:08.85#ibcon#read 3, iclass 22, count 0 2006.196.08:18:08.85#ibcon#about to read 4, iclass 22, count 0 2006.196.08:18:08.85#ibcon#read 4, iclass 22, count 0 2006.196.08:18:08.85#ibcon#about to read 5, iclass 22, count 0 2006.196.08:18:08.85#ibcon#read 5, iclass 22, count 0 2006.196.08:18:08.85#ibcon#about to read 6, iclass 22, count 0 2006.196.08:18:08.85#ibcon#read 6, iclass 22, count 0 2006.196.08:18:08.85#ibcon#end of sib2, iclass 22, count 0 2006.196.08:18:08.85#ibcon#*mode == 0, iclass 22, count 0 2006.196.08:18:08.85#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.196.08:18:08.85#ibcon#[25=USB\r\n] 2006.196.08:18:08.85#ibcon#*before write, iclass 22, count 0 2006.196.08:18:08.85#ibcon#enter sib2, iclass 22, count 0 2006.196.08:18:08.85#ibcon#flushed, iclass 22, count 0 2006.196.08:18:08.85#ibcon#about to write, iclass 22, count 0 2006.196.08:18:08.85#ibcon#wrote, iclass 22, count 0 2006.196.08:18:08.85#ibcon#about to read 3, iclass 22, count 0 2006.196.08:18:08.88#ibcon#read 3, iclass 22, count 0 2006.196.08:18:08.88#ibcon#about to read 4, iclass 22, count 0 2006.196.08:18:08.88#ibcon#read 4, iclass 22, count 0 2006.196.08:18:08.88#ibcon#about to read 5, iclass 22, count 0 2006.196.08:18:08.88#ibcon#read 5, iclass 22, count 0 2006.196.08:18:08.88#ibcon#about to read 6, iclass 22, count 0 2006.196.08:18:08.88#ibcon#read 6, iclass 22, count 0 2006.196.08:18:08.88#ibcon#end of sib2, iclass 22, count 0 2006.196.08:18:08.88#ibcon#*after write, iclass 22, count 0 2006.196.08:18:08.88#ibcon#*before return 0, iclass 22, count 0 2006.196.08:18:08.88#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.196.08:18:08.88#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.196.08:18:08.88#ibcon#about to clear, iclass 22 cls_cnt 0 2006.196.08:18:08.88#ibcon#cleared, iclass 22 cls_cnt 0 2006.196.08:18:08.88$vc4f8/valo=4,832.99 2006.196.08:18:08.88#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.196.08:18:08.88#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.196.08:18:08.88#ibcon#ireg 17 cls_cnt 0 2006.196.08:18:08.88#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.196.08:18:08.88#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.196.08:18:08.88#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.196.08:18:08.88#ibcon#enter wrdev, iclass 24, count 0 2006.196.08:18:08.88#ibcon#first serial, iclass 24, count 0 2006.196.08:18:08.88#ibcon#enter sib2, iclass 24, count 0 2006.196.08:18:08.88#ibcon#flushed, iclass 24, count 0 2006.196.08:18:08.88#ibcon#about to write, iclass 24, count 0 2006.196.08:18:08.88#ibcon#wrote, iclass 24, count 0 2006.196.08:18:08.88#ibcon#about to read 3, iclass 24, count 0 2006.196.08:18:08.90#ibcon#read 3, iclass 24, count 0 2006.196.08:18:08.90#ibcon#about to read 4, iclass 24, count 0 2006.196.08:18:08.90#ibcon#read 4, iclass 24, count 0 2006.196.08:18:08.90#ibcon#about to read 5, iclass 24, count 0 2006.196.08:18:08.90#ibcon#read 5, iclass 24, count 0 2006.196.08:18:08.90#ibcon#about to read 6, iclass 24, count 0 2006.196.08:18:08.90#ibcon#read 6, iclass 24, count 0 2006.196.08:18:08.90#ibcon#end of sib2, iclass 24, count 0 2006.196.08:18:08.90#ibcon#*mode == 0, iclass 24, count 0 2006.196.08:18:08.90#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.196.08:18:08.90#ibcon#[26=FRQ=04,832.99\r\n] 2006.196.08:18:08.90#ibcon#*before write, iclass 24, count 0 2006.196.08:18:08.90#ibcon#enter sib2, iclass 24, count 0 2006.196.08:18:08.90#ibcon#flushed, iclass 24, count 0 2006.196.08:18:08.90#ibcon#about to write, iclass 24, count 0 2006.196.08:18:08.90#ibcon#wrote, iclass 24, count 0 2006.196.08:18:08.90#ibcon#about to read 3, iclass 24, count 0 2006.196.08:18:08.94#ibcon#read 3, iclass 24, count 0 2006.196.08:18:08.94#ibcon#about to read 4, iclass 24, count 0 2006.196.08:18:08.94#ibcon#read 4, iclass 24, count 0 2006.196.08:18:08.94#ibcon#about to read 5, iclass 24, count 0 2006.196.08:18:08.94#ibcon#read 5, iclass 24, count 0 2006.196.08:18:08.94#ibcon#about to read 6, iclass 24, count 0 2006.196.08:18:08.94#ibcon#read 6, iclass 24, count 0 2006.196.08:18:08.94#ibcon#end of sib2, iclass 24, count 0 2006.196.08:18:08.94#ibcon#*after write, iclass 24, count 0 2006.196.08:18:08.94#ibcon#*before return 0, iclass 24, count 0 2006.196.08:18:08.94#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.196.08:18:08.94#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.196.08:18:08.94#ibcon#about to clear, iclass 24 cls_cnt 0 2006.196.08:18:08.94#ibcon#cleared, iclass 24 cls_cnt 0 2006.196.08:18:08.94$vc4f8/va=4,7 2006.196.08:18:08.94#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.196.08:18:08.94#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.196.08:18:08.94#ibcon#ireg 11 cls_cnt 2 2006.196.08:18:08.94#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.196.08:18:09.00#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.196.08:18:09.00#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.196.08:18:09.00#ibcon#enter wrdev, iclass 26, count 2 2006.196.08:18:09.00#ibcon#first serial, iclass 26, count 2 2006.196.08:18:09.00#ibcon#enter sib2, iclass 26, count 2 2006.196.08:18:09.00#ibcon#flushed, iclass 26, count 2 2006.196.08:18:09.00#ibcon#about to write, iclass 26, count 2 2006.196.08:18:09.00#ibcon#wrote, iclass 26, count 2 2006.196.08:18:09.00#ibcon#about to read 3, iclass 26, count 2 2006.196.08:18:09.02#ibcon#read 3, iclass 26, count 2 2006.196.08:18:09.02#ibcon#about to read 4, iclass 26, count 2 2006.196.08:18:09.02#ibcon#read 4, iclass 26, count 2 2006.196.08:18:09.02#ibcon#about to read 5, iclass 26, count 2 2006.196.08:18:09.02#ibcon#read 5, iclass 26, count 2 2006.196.08:18:09.02#ibcon#about to read 6, iclass 26, count 2 2006.196.08:18:09.02#ibcon#read 6, iclass 26, count 2 2006.196.08:18:09.02#ibcon#end of sib2, iclass 26, count 2 2006.196.08:18:09.02#ibcon#*mode == 0, iclass 26, count 2 2006.196.08:18:09.02#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.196.08:18:09.02#ibcon#[25=AT04-07\r\n] 2006.196.08:18:09.02#ibcon#*before write, iclass 26, count 2 2006.196.08:18:09.02#ibcon#enter sib2, iclass 26, count 2 2006.196.08:18:09.02#ibcon#flushed, iclass 26, count 2 2006.196.08:18:09.02#ibcon#about to write, iclass 26, count 2 2006.196.08:18:09.02#ibcon#wrote, iclass 26, count 2 2006.196.08:18:09.02#ibcon#about to read 3, iclass 26, count 2 2006.196.08:18:09.05#ibcon#read 3, iclass 26, count 2 2006.196.08:18:09.05#ibcon#about to read 4, iclass 26, count 2 2006.196.08:18:09.05#ibcon#read 4, iclass 26, count 2 2006.196.08:18:09.05#ibcon#about to read 5, iclass 26, count 2 2006.196.08:18:09.05#ibcon#read 5, iclass 26, count 2 2006.196.08:18:09.05#ibcon#about to read 6, iclass 26, count 2 2006.196.08:18:09.05#ibcon#read 6, iclass 26, count 2 2006.196.08:18:09.05#ibcon#end of sib2, iclass 26, count 2 2006.196.08:18:09.05#ibcon#*after write, iclass 26, count 2 2006.196.08:18:09.05#ibcon#*before return 0, iclass 26, count 2 2006.196.08:18:09.05#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.196.08:18:09.05#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.196.08:18:09.05#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.196.08:18:09.05#ibcon#ireg 7 cls_cnt 0 2006.196.08:18:09.05#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.196.08:18:09.17#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.196.08:18:09.17#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.196.08:18:09.17#ibcon#enter wrdev, iclass 26, count 0 2006.196.08:18:09.17#ibcon#first serial, iclass 26, count 0 2006.196.08:18:09.17#ibcon#enter sib2, iclass 26, count 0 2006.196.08:18:09.17#ibcon#flushed, iclass 26, count 0 2006.196.08:18:09.17#ibcon#about to write, iclass 26, count 0 2006.196.08:18:09.17#ibcon#wrote, iclass 26, count 0 2006.196.08:18:09.17#ibcon#about to read 3, iclass 26, count 0 2006.196.08:18:09.19#ibcon#read 3, iclass 26, count 0 2006.196.08:18:09.19#ibcon#about to read 4, iclass 26, count 0 2006.196.08:18:09.19#ibcon#read 4, iclass 26, count 0 2006.196.08:18:09.19#ibcon#about to read 5, iclass 26, count 0 2006.196.08:18:09.19#ibcon#read 5, iclass 26, count 0 2006.196.08:18:09.19#ibcon#about to read 6, iclass 26, count 0 2006.196.08:18:09.19#ibcon#read 6, iclass 26, count 0 2006.196.08:18:09.19#ibcon#end of sib2, iclass 26, count 0 2006.196.08:18:09.19#ibcon#*mode == 0, iclass 26, count 0 2006.196.08:18:09.19#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.196.08:18:09.19#ibcon#[25=USB\r\n] 2006.196.08:18:09.19#ibcon#*before write, iclass 26, count 0 2006.196.08:18:09.19#ibcon#enter sib2, iclass 26, count 0 2006.196.08:18:09.19#ibcon#flushed, iclass 26, count 0 2006.196.08:18:09.19#ibcon#about to write, iclass 26, count 0 2006.196.08:18:09.19#ibcon#wrote, iclass 26, count 0 2006.196.08:18:09.19#ibcon#about to read 3, iclass 26, count 0 2006.196.08:18:09.22#ibcon#read 3, iclass 26, count 0 2006.196.08:18:09.22#ibcon#about to read 4, iclass 26, count 0 2006.196.08:18:09.22#ibcon#read 4, iclass 26, count 0 2006.196.08:18:09.22#ibcon#about to read 5, iclass 26, count 0 2006.196.08:18:09.22#ibcon#read 5, iclass 26, count 0 2006.196.08:18:09.22#ibcon#about to read 6, iclass 26, count 0 2006.196.08:18:09.22#ibcon#read 6, iclass 26, count 0 2006.196.08:18:09.22#ibcon#end of sib2, iclass 26, count 0 2006.196.08:18:09.22#ibcon#*after write, iclass 26, count 0 2006.196.08:18:09.22#ibcon#*before return 0, iclass 26, count 0 2006.196.08:18:09.22#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.196.08:18:09.22#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.196.08:18:09.22#ibcon#about to clear, iclass 26 cls_cnt 0 2006.196.08:18:09.22#ibcon#cleared, iclass 26 cls_cnt 0 2006.196.08:18:09.22$vc4f8/valo=5,652.99 2006.196.08:18:09.22#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.196.08:18:09.22#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.196.08:18:09.22#ibcon#ireg 17 cls_cnt 0 2006.196.08:18:09.22#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.196.08:18:09.22#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.196.08:18:09.22#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.196.08:18:09.22#ibcon#enter wrdev, iclass 28, count 0 2006.196.08:18:09.22#ibcon#first serial, iclass 28, count 0 2006.196.08:18:09.22#ibcon#enter sib2, iclass 28, count 0 2006.196.08:18:09.22#ibcon#flushed, iclass 28, count 0 2006.196.08:18:09.22#ibcon#about to write, iclass 28, count 0 2006.196.08:18:09.22#ibcon#wrote, iclass 28, count 0 2006.196.08:18:09.22#ibcon#about to read 3, iclass 28, count 0 2006.196.08:18:09.24#ibcon#read 3, iclass 28, count 0 2006.196.08:18:09.24#ibcon#about to read 4, iclass 28, count 0 2006.196.08:18:09.24#ibcon#read 4, iclass 28, count 0 2006.196.08:18:09.24#ibcon#about to read 5, iclass 28, count 0 2006.196.08:18:09.24#ibcon#read 5, iclass 28, count 0 2006.196.08:18:09.24#ibcon#about to read 6, iclass 28, count 0 2006.196.08:18:09.24#ibcon#read 6, iclass 28, count 0 2006.196.08:18:09.24#ibcon#end of sib2, iclass 28, count 0 2006.196.08:18:09.24#ibcon#*mode == 0, iclass 28, count 0 2006.196.08:18:09.24#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.196.08:18:09.24#ibcon#[26=FRQ=05,652.99\r\n] 2006.196.08:18:09.24#ibcon#*before write, iclass 28, count 0 2006.196.08:18:09.24#ibcon#enter sib2, iclass 28, count 0 2006.196.08:18:09.24#ibcon#flushed, iclass 28, count 0 2006.196.08:18:09.24#ibcon#about to write, iclass 28, count 0 2006.196.08:18:09.24#ibcon#wrote, iclass 28, count 0 2006.196.08:18:09.24#ibcon#about to read 3, iclass 28, count 0 2006.196.08:18:09.28#ibcon#read 3, iclass 28, count 0 2006.196.08:18:09.28#ibcon#about to read 4, iclass 28, count 0 2006.196.08:18:09.28#ibcon#read 4, iclass 28, count 0 2006.196.08:18:09.28#ibcon#about to read 5, iclass 28, count 0 2006.196.08:18:09.28#ibcon#read 5, iclass 28, count 0 2006.196.08:18:09.28#ibcon#about to read 6, iclass 28, count 0 2006.196.08:18:09.28#ibcon#read 6, iclass 28, count 0 2006.196.08:18:09.28#ibcon#end of sib2, iclass 28, count 0 2006.196.08:18:09.28#ibcon#*after write, iclass 28, count 0 2006.196.08:18:09.28#ibcon#*before return 0, iclass 28, count 0 2006.196.08:18:09.28#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.196.08:18:09.28#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.196.08:18:09.28#ibcon#about to clear, iclass 28 cls_cnt 0 2006.196.08:18:09.28#ibcon#cleared, iclass 28 cls_cnt 0 2006.196.08:18:09.28$vc4f8/va=5,7 2006.196.08:18:09.28#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.196.08:18:09.28#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.196.08:18:09.28#ibcon#ireg 11 cls_cnt 2 2006.196.08:18:09.28#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.196.08:18:09.34#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.196.08:18:09.34#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.196.08:18:09.34#ibcon#enter wrdev, iclass 30, count 2 2006.196.08:18:09.34#ibcon#first serial, iclass 30, count 2 2006.196.08:18:09.34#ibcon#enter sib2, iclass 30, count 2 2006.196.08:18:09.34#ibcon#flushed, iclass 30, count 2 2006.196.08:18:09.34#ibcon#about to write, iclass 30, count 2 2006.196.08:18:09.34#ibcon#wrote, iclass 30, count 2 2006.196.08:18:09.34#ibcon#about to read 3, iclass 30, count 2 2006.196.08:18:09.36#ibcon#read 3, iclass 30, count 2 2006.196.08:18:09.36#ibcon#about to read 4, iclass 30, count 2 2006.196.08:18:09.36#ibcon#read 4, iclass 30, count 2 2006.196.08:18:09.36#ibcon#about to read 5, iclass 30, count 2 2006.196.08:18:09.36#ibcon#read 5, iclass 30, count 2 2006.196.08:18:09.36#ibcon#about to read 6, iclass 30, count 2 2006.196.08:18:09.36#ibcon#read 6, iclass 30, count 2 2006.196.08:18:09.36#ibcon#end of sib2, iclass 30, count 2 2006.196.08:18:09.36#ibcon#*mode == 0, iclass 30, count 2 2006.196.08:18:09.36#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.196.08:18:09.36#ibcon#[25=AT05-07\r\n] 2006.196.08:18:09.36#ibcon#*before write, iclass 30, count 2 2006.196.08:18:09.36#ibcon#enter sib2, iclass 30, count 2 2006.196.08:18:09.36#ibcon#flushed, iclass 30, count 2 2006.196.08:18:09.36#ibcon#about to write, iclass 30, count 2 2006.196.08:18:09.36#ibcon#wrote, iclass 30, count 2 2006.196.08:18:09.36#ibcon#about to read 3, iclass 30, count 2 2006.196.08:18:09.39#ibcon#read 3, iclass 30, count 2 2006.196.08:18:09.39#ibcon#about to read 4, iclass 30, count 2 2006.196.08:18:09.39#ibcon#read 4, iclass 30, count 2 2006.196.08:18:09.39#ibcon#about to read 5, iclass 30, count 2 2006.196.08:18:09.39#ibcon#read 5, iclass 30, count 2 2006.196.08:18:09.39#ibcon#about to read 6, iclass 30, count 2 2006.196.08:18:09.39#ibcon#read 6, iclass 30, count 2 2006.196.08:18:09.39#ibcon#end of sib2, iclass 30, count 2 2006.196.08:18:09.39#ibcon#*after write, iclass 30, count 2 2006.196.08:18:09.39#ibcon#*before return 0, iclass 30, count 2 2006.196.08:18:09.39#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.196.08:18:09.39#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.196.08:18:09.39#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.196.08:18:09.39#ibcon#ireg 7 cls_cnt 0 2006.196.08:18:09.39#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.196.08:18:09.51#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.196.08:18:09.51#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.196.08:18:09.51#ibcon#enter wrdev, iclass 30, count 0 2006.196.08:18:09.51#ibcon#first serial, iclass 30, count 0 2006.196.08:18:09.51#ibcon#enter sib2, iclass 30, count 0 2006.196.08:18:09.51#ibcon#flushed, iclass 30, count 0 2006.196.08:18:09.51#ibcon#about to write, iclass 30, count 0 2006.196.08:18:09.51#ibcon#wrote, iclass 30, count 0 2006.196.08:18:09.51#ibcon#about to read 3, iclass 30, count 0 2006.196.08:18:09.53#ibcon#read 3, iclass 30, count 0 2006.196.08:18:09.53#ibcon#about to read 4, iclass 30, count 0 2006.196.08:18:09.53#ibcon#read 4, iclass 30, count 0 2006.196.08:18:09.53#ibcon#about to read 5, iclass 30, count 0 2006.196.08:18:09.53#ibcon#read 5, iclass 30, count 0 2006.196.08:18:09.53#ibcon#about to read 6, iclass 30, count 0 2006.196.08:18:09.53#ibcon#read 6, iclass 30, count 0 2006.196.08:18:09.53#ibcon#end of sib2, iclass 30, count 0 2006.196.08:18:09.53#ibcon#*mode == 0, iclass 30, count 0 2006.196.08:18:09.53#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.196.08:18:09.53#ibcon#[25=USB\r\n] 2006.196.08:18:09.53#ibcon#*before write, iclass 30, count 0 2006.196.08:18:09.53#ibcon#enter sib2, iclass 30, count 0 2006.196.08:18:09.53#ibcon#flushed, iclass 30, count 0 2006.196.08:18:09.53#ibcon#about to write, iclass 30, count 0 2006.196.08:18:09.53#ibcon#wrote, iclass 30, count 0 2006.196.08:18:09.53#ibcon#about to read 3, iclass 30, count 0 2006.196.08:18:09.56#ibcon#read 3, iclass 30, count 0 2006.196.08:18:09.56#ibcon#about to read 4, iclass 30, count 0 2006.196.08:18:09.56#ibcon#read 4, iclass 30, count 0 2006.196.08:18:09.56#ibcon#about to read 5, iclass 30, count 0 2006.196.08:18:09.56#ibcon#read 5, iclass 30, count 0 2006.196.08:18:09.56#ibcon#about to read 6, iclass 30, count 0 2006.196.08:18:09.56#ibcon#read 6, iclass 30, count 0 2006.196.08:18:09.56#ibcon#end of sib2, iclass 30, count 0 2006.196.08:18:09.56#ibcon#*after write, iclass 30, count 0 2006.196.08:18:09.56#ibcon#*before return 0, iclass 30, count 0 2006.196.08:18:09.56#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.196.08:18:09.56#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.196.08:18:09.56#ibcon#about to clear, iclass 30 cls_cnt 0 2006.196.08:18:09.56#ibcon#cleared, iclass 30 cls_cnt 0 2006.196.08:18:09.56$vc4f8/valo=6,772.99 2006.196.08:18:09.56#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.196.08:18:09.56#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.196.08:18:09.56#ibcon#ireg 17 cls_cnt 0 2006.196.08:18:09.56#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:18:09.56#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:18:09.56#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:18:09.56#ibcon#enter wrdev, iclass 33, count 0 2006.196.08:18:09.56#ibcon#first serial, iclass 33, count 0 2006.196.08:18:09.56#ibcon#enter sib2, iclass 33, count 0 2006.196.08:18:09.56#ibcon#flushed, iclass 33, count 0 2006.196.08:18:09.56#ibcon#about to write, iclass 33, count 0 2006.196.08:18:09.56#ibcon#wrote, iclass 33, count 0 2006.196.08:18:09.56#ibcon#about to read 3, iclass 33, count 0 2006.196.08:18:09.58#ibcon#read 3, iclass 33, count 0 2006.196.08:18:09.58#ibcon#about to read 4, iclass 33, count 0 2006.196.08:18:09.58#ibcon#read 4, iclass 33, count 0 2006.196.08:18:09.58#ibcon#about to read 5, iclass 33, count 0 2006.196.08:18:09.58#ibcon#read 5, iclass 33, count 0 2006.196.08:18:09.58#ibcon#about to read 6, iclass 33, count 0 2006.196.08:18:09.58#ibcon#read 6, iclass 33, count 0 2006.196.08:18:09.58#ibcon#end of sib2, iclass 33, count 0 2006.196.08:18:09.58#ibcon#*mode == 0, iclass 33, count 0 2006.196.08:18:09.58#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.196.08:18:09.58#ibcon#[26=FRQ=06,772.99\r\n] 2006.196.08:18:09.58#ibcon#*before write, iclass 33, count 0 2006.196.08:18:09.58#ibcon#enter sib2, iclass 33, count 0 2006.196.08:18:09.58#ibcon#flushed, iclass 33, count 0 2006.196.08:18:09.58#ibcon#about to write, iclass 33, count 0 2006.196.08:18:09.58#ibcon#wrote, iclass 33, count 0 2006.196.08:18:09.58#ibcon#about to read 3, iclass 33, count 0 2006.196.08:18:09.59#abcon#<5=/05 4.3 6.8 29.00 931004.1\r\n> 2006.196.08:18:09.61#abcon#{5=INTERFACE CLEAR} 2006.196.08:18:09.62#ibcon#read 3, iclass 33, count 0 2006.196.08:18:09.62#ibcon#about to read 4, iclass 33, count 0 2006.196.08:18:09.62#ibcon#read 4, iclass 33, count 0 2006.196.08:18:09.62#ibcon#about to read 5, iclass 33, count 0 2006.196.08:18:09.62#ibcon#read 5, iclass 33, count 0 2006.196.08:18:09.62#ibcon#about to read 6, iclass 33, count 0 2006.196.08:18:09.62#ibcon#read 6, iclass 33, count 0 2006.196.08:18:09.62#ibcon#end of sib2, iclass 33, count 0 2006.196.08:18:09.62#ibcon#*after write, iclass 33, count 0 2006.196.08:18:09.62#ibcon#*before return 0, iclass 33, count 0 2006.196.08:18:09.62#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:18:09.62#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:18:09.62#ibcon#about to clear, iclass 33 cls_cnt 0 2006.196.08:18:09.62#ibcon#cleared, iclass 33 cls_cnt 0 2006.196.08:18:09.62$vc4f8/va=6,6 2006.196.08:18:09.62#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.196.08:18:09.62#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.196.08:18:09.62#ibcon#ireg 11 cls_cnt 2 2006.196.08:18:09.62#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.196.08:18:09.67#abcon#[5=S1D000X0/0*\r\n] 2006.196.08:18:09.68#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.196.08:18:09.68#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.196.08:18:09.68#ibcon#enter wrdev, iclass 37, count 2 2006.196.08:18:09.68#ibcon#first serial, iclass 37, count 2 2006.196.08:18:09.68#ibcon#enter sib2, iclass 37, count 2 2006.196.08:18:09.68#ibcon#flushed, iclass 37, count 2 2006.196.08:18:09.68#ibcon#about to write, iclass 37, count 2 2006.196.08:18:09.68#ibcon#wrote, iclass 37, count 2 2006.196.08:18:09.68#ibcon#about to read 3, iclass 37, count 2 2006.196.08:18:09.70#ibcon#read 3, iclass 37, count 2 2006.196.08:18:09.70#ibcon#about to read 4, iclass 37, count 2 2006.196.08:18:09.70#ibcon#read 4, iclass 37, count 2 2006.196.08:18:09.70#ibcon#about to read 5, iclass 37, count 2 2006.196.08:18:09.70#ibcon#read 5, iclass 37, count 2 2006.196.08:18:09.70#ibcon#about to read 6, iclass 37, count 2 2006.196.08:18:09.70#ibcon#read 6, iclass 37, count 2 2006.196.08:18:09.70#ibcon#end of sib2, iclass 37, count 2 2006.196.08:18:09.70#ibcon#*mode == 0, iclass 37, count 2 2006.196.08:18:09.70#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.196.08:18:09.70#ibcon#[25=AT06-06\r\n] 2006.196.08:18:09.70#ibcon#*before write, iclass 37, count 2 2006.196.08:18:09.70#ibcon#enter sib2, iclass 37, count 2 2006.196.08:18:09.70#ibcon#flushed, iclass 37, count 2 2006.196.08:18:09.70#ibcon#about to write, iclass 37, count 2 2006.196.08:18:09.70#ibcon#wrote, iclass 37, count 2 2006.196.08:18:09.70#ibcon#about to read 3, iclass 37, count 2 2006.196.08:18:09.73#ibcon#read 3, iclass 37, count 2 2006.196.08:18:09.73#ibcon#about to read 4, iclass 37, count 2 2006.196.08:18:09.73#ibcon#read 4, iclass 37, count 2 2006.196.08:18:09.73#ibcon#about to read 5, iclass 37, count 2 2006.196.08:18:09.73#ibcon#read 5, iclass 37, count 2 2006.196.08:18:09.73#ibcon#about to read 6, iclass 37, count 2 2006.196.08:18:09.73#ibcon#read 6, iclass 37, count 2 2006.196.08:18:09.73#ibcon#end of sib2, iclass 37, count 2 2006.196.08:18:09.73#ibcon#*after write, iclass 37, count 2 2006.196.08:18:09.73#ibcon#*before return 0, iclass 37, count 2 2006.196.08:18:09.73#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.196.08:18:09.73#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.196.08:18:09.73#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.196.08:18:09.73#ibcon#ireg 7 cls_cnt 0 2006.196.08:18:09.73#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.196.08:18:09.85#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.196.08:18:09.85#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.196.08:18:09.85#ibcon#enter wrdev, iclass 37, count 0 2006.196.08:18:09.85#ibcon#first serial, iclass 37, count 0 2006.196.08:18:09.85#ibcon#enter sib2, iclass 37, count 0 2006.196.08:18:09.85#ibcon#flushed, iclass 37, count 0 2006.196.08:18:09.85#ibcon#about to write, iclass 37, count 0 2006.196.08:18:09.85#ibcon#wrote, iclass 37, count 0 2006.196.08:18:09.85#ibcon#about to read 3, iclass 37, count 0 2006.196.08:18:09.87#ibcon#read 3, iclass 37, count 0 2006.196.08:18:09.87#ibcon#about to read 4, iclass 37, count 0 2006.196.08:18:09.87#ibcon#read 4, iclass 37, count 0 2006.196.08:18:09.87#ibcon#about to read 5, iclass 37, count 0 2006.196.08:18:09.87#ibcon#read 5, iclass 37, count 0 2006.196.08:18:09.87#ibcon#about to read 6, iclass 37, count 0 2006.196.08:18:09.87#ibcon#read 6, iclass 37, count 0 2006.196.08:18:09.87#ibcon#end of sib2, iclass 37, count 0 2006.196.08:18:09.87#ibcon#*mode == 0, iclass 37, count 0 2006.196.08:18:09.87#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.196.08:18:09.87#ibcon#[25=USB\r\n] 2006.196.08:18:09.87#ibcon#*before write, iclass 37, count 0 2006.196.08:18:09.87#ibcon#enter sib2, iclass 37, count 0 2006.196.08:18:09.87#ibcon#flushed, iclass 37, count 0 2006.196.08:18:09.87#ibcon#about to write, iclass 37, count 0 2006.196.08:18:09.87#ibcon#wrote, iclass 37, count 0 2006.196.08:18:09.87#ibcon#about to read 3, iclass 37, count 0 2006.196.08:18:09.90#ibcon#read 3, iclass 37, count 0 2006.196.08:18:09.90#ibcon#about to read 4, iclass 37, count 0 2006.196.08:18:09.90#ibcon#read 4, iclass 37, count 0 2006.196.08:18:09.90#ibcon#about to read 5, iclass 37, count 0 2006.196.08:18:09.90#ibcon#read 5, iclass 37, count 0 2006.196.08:18:09.90#ibcon#about to read 6, iclass 37, count 0 2006.196.08:18:09.90#ibcon#read 6, iclass 37, count 0 2006.196.08:18:09.90#ibcon#end of sib2, iclass 37, count 0 2006.196.08:18:09.90#ibcon#*after write, iclass 37, count 0 2006.196.08:18:09.90#ibcon#*before return 0, iclass 37, count 0 2006.196.08:18:09.90#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.196.08:18:09.90#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.196.08:18:09.90#ibcon#about to clear, iclass 37 cls_cnt 0 2006.196.08:18:09.90#ibcon#cleared, iclass 37 cls_cnt 0 2006.196.08:18:09.90$vc4f8/valo=7,832.99 2006.196.08:18:09.90#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.196.08:18:09.90#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.196.08:18:09.90#ibcon#ireg 17 cls_cnt 0 2006.196.08:18:09.90#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.196.08:18:09.90#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.196.08:18:09.90#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.196.08:18:09.90#ibcon#enter wrdev, iclass 40, count 0 2006.196.08:18:09.90#ibcon#first serial, iclass 40, count 0 2006.196.08:18:09.90#ibcon#enter sib2, iclass 40, count 0 2006.196.08:18:09.90#ibcon#flushed, iclass 40, count 0 2006.196.08:18:09.90#ibcon#about to write, iclass 40, count 0 2006.196.08:18:09.90#ibcon#wrote, iclass 40, count 0 2006.196.08:18:09.90#ibcon#about to read 3, iclass 40, count 0 2006.196.08:18:09.92#ibcon#read 3, iclass 40, count 0 2006.196.08:18:09.92#ibcon#about to read 4, iclass 40, count 0 2006.196.08:18:09.92#ibcon#read 4, iclass 40, count 0 2006.196.08:18:09.92#ibcon#about to read 5, iclass 40, count 0 2006.196.08:18:09.92#ibcon#read 5, iclass 40, count 0 2006.196.08:18:09.92#ibcon#about to read 6, iclass 40, count 0 2006.196.08:18:09.92#ibcon#read 6, iclass 40, count 0 2006.196.08:18:09.92#ibcon#end of sib2, iclass 40, count 0 2006.196.08:18:09.92#ibcon#*mode == 0, iclass 40, count 0 2006.196.08:18:09.92#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.196.08:18:09.92#ibcon#[26=FRQ=07,832.99\r\n] 2006.196.08:18:09.92#ibcon#*before write, iclass 40, count 0 2006.196.08:18:09.92#ibcon#enter sib2, iclass 40, count 0 2006.196.08:18:09.92#ibcon#flushed, iclass 40, count 0 2006.196.08:18:09.92#ibcon#about to write, iclass 40, count 0 2006.196.08:18:09.92#ibcon#wrote, iclass 40, count 0 2006.196.08:18:09.92#ibcon#about to read 3, iclass 40, count 0 2006.196.08:18:09.96#ibcon#read 3, iclass 40, count 0 2006.196.08:18:09.96#ibcon#about to read 4, iclass 40, count 0 2006.196.08:18:09.96#ibcon#read 4, iclass 40, count 0 2006.196.08:18:09.96#ibcon#about to read 5, iclass 40, count 0 2006.196.08:18:09.96#ibcon#read 5, iclass 40, count 0 2006.196.08:18:09.96#ibcon#about to read 6, iclass 40, count 0 2006.196.08:18:09.96#ibcon#read 6, iclass 40, count 0 2006.196.08:18:09.96#ibcon#end of sib2, iclass 40, count 0 2006.196.08:18:09.96#ibcon#*after write, iclass 40, count 0 2006.196.08:18:09.96#ibcon#*before return 0, iclass 40, count 0 2006.196.08:18:09.96#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.196.08:18:09.96#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.196.08:18:09.96#ibcon#about to clear, iclass 40 cls_cnt 0 2006.196.08:18:09.96#ibcon#cleared, iclass 40 cls_cnt 0 2006.196.08:18:09.96$vc4f8/va=7,6 2006.196.08:18:09.96#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.196.08:18:09.96#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.196.08:18:09.96#ibcon#ireg 11 cls_cnt 2 2006.196.08:18:09.96#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.196.08:18:10.02#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.196.08:18:10.02#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.196.08:18:10.02#ibcon#enter wrdev, iclass 4, count 2 2006.196.08:18:10.02#ibcon#first serial, iclass 4, count 2 2006.196.08:18:10.02#ibcon#enter sib2, iclass 4, count 2 2006.196.08:18:10.02#ibcon#flushed, iclass 4, count 2 2006.196.08:18:10.02#ibcon#about to write, iclass 4, count 2 2006.196.08:18:10.02#ibcon#wrote, iclass 4, count 2 2006.196.08:18:10.02#ibcon#about to read 3, iclass 4, count 2 2006.196.08:18:10.04#ibcon#read 3, iclass 4, count 2 2006.196.08:18:10.04#ibcon#about to read 4, iclass 4, count 2 2006.196.08:18:10.04#ibcon#read 4, iclass 4, count 2 2006.196.08:18:10.04#ibcon#about to read 5, iclass 4, count 2 2006.196.08:18:10.04#ibcon#read 5, iclass 4, count 2 2006.196.08:18:10.04#ibcon#about to read 6, iclass 4, count 2 2006.196.08:18:10.04#ibcon#read 6, iclass 4, count 2 2006.196.08:18:10.04#ibcon#end of sib2, iclass 4, count 2 2006.196.08:18:10.04#ibcon#*mode == 0, iclass 4, count 2 2006.196.08:18:10.04#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.196.08:18:10.04#ibcon#[25=AT07-06\r\n] 2006.196.08:18:10.04#ibcon#*before write, iclass 4, count 2 2006.196.08:18:10.04#ibcon#enter sib2, iclass 4, count 2 2006.196.08:18:10.04#ibcon#flushed, iclass 4, count 2 2006.196.08:18:10.04#ibcon#about to write, iclass 4, count 2 2006.196.08:18:10.04#ibcon#wrote, iclass 4, count 2 2006.196.08:18:10.04#ibcon#about to read 3, iclass 4, count 2 2006.196.08:18:10.07#ibcon#read 3, iclass 4, count 2 2006.196.08:18:10.07#ibcon#about to read 4, iclass 4, count 2 2006.196.08:18:10.07#ibcon#read 4, iclass 4, count 2 2006.196.08:18:10.07#ibcon#about to read 5, iclass 4, count 2 2006.196.08:18:10.07#ibcon#read 5, iclass 4, count 2 2006.196.08:18:10.07#ibcon#about to read 6, iclass 4, count 2 2006.196.08:18:10.07#ibcon#read 6, iclass 4, count 2 2006.196.08:18:10.07#ibcon#end of sib2, iclass 4, count 2 2006.196.08:18:10.07#ibcon#*after write, iclass 4, count 2 2006.196.08:18:10.07#ibcon#*before return 0, iclass 4, count 2 2006.196.08:18:10.07#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.196.08:18:10.07#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.196.08:18:10.07#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.196.08:18:10.07#ibcon#ireg 7 cls_cnt 0 2006.196.08:18:10.07#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.196.08:18:10.19#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.196.08:18:10.19#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.196.08:18:10.19#ibcon#enter wrdev, iclass 4, count 0 2006.196.08:18:10.19#ibcon#first serial, iclass 4, count 0 2006.196.08:18:10.19#ibcon#enter sib2, iclass 4, count 0 2006.196.08:18:10.19#ibcon#flushed, iclass 4, count 0 2006.196.08:18:10.19#ibcon#about to write, iclass 4, count 0 2006.196.08:18:10.19#ibcon#wrote, iclass 4, count 0 2006.196.08:18:10.19#ibcon#about to read 3, iclass 4, count 0 2006.196.08:18:10.21#ibcon#read 3, iclass 4, count 0 2006.196.08:18:10.21#ibcon#about to read 4, iclass 4, count 0 2006.196.08:18:10.21#ibcon#read 4, iclass 4, count 0 2006.196.08:18:10.21#ibcon#about to read 5, iclass 4, count 0 2006.196.08:18:10.21#ibcon#read 5, iclass 4, count 0 2006.196.08:18:10.21#ibcon#about to read 6, iclass 4, count 0 2006.196.08:18:10.21#ibcon#read 6, iclass 4, count 0 2006.196.08:18:10.21#ibcon#end of sib2, iclass 4, count 0 2006.196.08:18:10.21#ibcon#*mode == 0, iclass 4, count 0 2006.196.08:18:10.21#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.196.08:18:10.21#ibcon#[25=USB\r\n] 2006.196.08:18:10.21#ibcon#*before write, iclass 4, count 0 2006.196.08:18:10.21#ibcon#enter sib2, iclass 4, count 0 2006.196.08:18:10.21#ibcon#flushed, iclass 4, count 0 2006.196.08:18:10.21#ibcon#about to write, iclass 4, count 0 2006.196.08:18:10.21#ibcon#wrote, iclass 4, count 0 2006.196.08:18:10.21#ibcon#about to read 3, iclass 4, count 0 2006.196.08:18:10.24#ibcon#read 3, iclass 4, count 0 2006.196.08:18:10.24#ibcon#about to read 4, iclass 4, count 0 2006.196.08:18:10.24#ibcon#read 4, iclass 4, count 0 2006.196.08:18:10.24#ibcon#about to read 5, iclass 4, count 0 2006.196.08:18:10.24#ibcon#read 5, iclass 4, count 0 2006.196.08:18:10.24#ibcon#about to read 6, iclass 4, count 0 2006.196.08:18:10.24#ibcon#read 6, iclass 4, count 0 2006.196.08:18:10.24#ibcon#end of sib2, iclass 4, count 0 2006.196.08:18:10.24#ibcon#*after write, iclass 4, count 0 2006.196.08:18:10.24#ibcon#*before return 0, iclass 4, count 0 2006.196.08:18:10.24#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.196.08:18:10.24#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.196.08:18:10.24#ibcon#about to clear, iclass 4 cls_cnt 0 2006.196.08:18:10.24#ibcon#cleared, iclass 4 cls_cnt 0 2006.196.08:18:10.24$vc4f8/valo=8,852.99 2006.196.08:18:10.24#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.196.08:18:10.24#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.196.08:18:10.24#ibcon#ireg 17 cls_cnt 0 2006.196.08:18:10.24#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.196.08:18:10.24#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.196.08:18:10.24#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.196.08:18:10.24#ibcon#enter wrdev, iclass 6, count 0 2006.196.08:18:10.24#ibcon#first serial, iclass 6, count 0 2006.196.08:18:10.24#ibcon#enter sib2, iclass 6, count 0 2006.196.08:18:10.24#ibcon#flushed, iclass 6, count 0 2006.196.08:18:10.24#ibcon#about to write, iclass 6, count 0 2006.196.08:18:10.24#ibcon#wrote, iclass 6, count 0 2006.196.08:18:10.24#ibcon#about to read 3, iclass 6, count 0 2006.196.08:18:10.26#ibcon#read 3, iclass 6, count 0 2006.196.08:18:10.26#ibcon#about to read 4, iclass 6, count 0 2006.196.08:18:10.26#ibcon#read 4, iclass 6, count 0 2006.196.08:18:10.26#ibcon#about to read 5, iclass 6, count 0 2006.196.08:18:10.26#ibcon#read 5, iclass 6, count 0 2006.196.08:18:10.26#ibcon#about to read 6, iclass 6, count 0 2006.196.08:18:10.26#ibcon#read 6, iclass 6, count 0 2006.196.08:18:10.26#ibcon#end of sib2, iclass 6, count 0 2006.196.08:18:10.26#ibcon#*mode == 0, iclass 6, count 0 2006.196.08:18:10.26#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.196.08:18:10.26#ibcon#[26=FRQ=08,852.99\r\n] 2006.196.08:18:10.26#ibcon#*before write, iclass 6, count 0 2006.196.08:18:10.26#ibcon#enter sib2, iclass 6, count 0 2006.196.08:18:10.26#ibcon#flushed, iclass 6, count 0 2006.196.08:18:10.26#ibcon#about to write, iclass 6, count 0 2006.196.08:18:10.26#ibcon#wrote, iclass 6, count 0 2006.196.08:18:10.26#ibcon#about to read 3, iclass 6, count 0 2006.196.08:18:10.30#ibcon#read 3, iclass 6, count 0 2006.196.08:18:10.30#ibcon#about to read 4, iclass 6, count 0 2006.196.08:18:10.30#ibcon#read 4, iclass 6, count 0 2006.196.08:18:10.30#ibcon#about to read 5, iclass 6, count 0 2006.196.08:18:10.30#ibcon#read 5, iclass 6, count 0 2006.196.08:18:10.30#ibcon#about to read 6, iclass 6, count 0 2006.196.08:18:10.30#ibcon#read 6, iclass 6, count 0 2006.196.08:18:10.30#ibcon#end of sib2, iclass 6, count 0 2006.196.08:18:10.30#ibcon#*after write, iclass 6, count 0 2006.196.08:18:10.30#ibcon#*before return 0, iclass 6, count 0 2006.196.08:18:10.30#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.196.08:18:10.30#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.196.08:18:10.30#ibcon#about to clear, iclass 6 cls_cnt 0 2006.196.08:18:10.30#ibcon#cleared, iclass 6 cls_cnt 0 2006.196.08:18:10.30$vc4f8/va=8,7 2006.196.08:18:10.30#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.196.08:18:10.30#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.196.08:18:10.30#ibcon#ireg 11 cls_cnt 2 2006.196.08:18:10.30#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.196.08:18:10.36#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.196.08:18:10.36#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.196.08:18:10.36#ibcon#enter wrdev, iclass 10, count 2 2006.196.08:18:10.36#ibcon#first serial, iclass 10, count 2 2006.196.08:18:10.36#ibcon#enter sib2, iclass 10, count 2 2006.196.08:18:10.36#ibcon#flushed, iclass 10, count 2 2006.196.08:18:10.36#ibcon#about to write, iclass 10, count 2 2006.196.08:18:10.36#ibcon#wrote, iclass 10, count 2 2006.196.08:18:10.36#ibcon#about to read 3, iclass 10, count 2 2006.196.08:18:10.38#ibcon#read 3, iclass 10, count 2 2006.196.08:18:10.38#ibcon#about to read 4, iclass 10, count 2 2006.196.08:18:10.38#ibcon#read 4, iclass 10, count 2 2006.196.08:18:10.38#ibcon#about to read 5, iclass 10, count 2 2006.196.08:18:10.38#ibcon#read 5, iclass 10, count 2 2006.196.08:18:10.38#ibcon#about to read 6, iclass 10, count 2 2006.196.08:18:10.38#ibcon#read 6, iclass 10, count 2 2006.196.08:18:10.38#ibcon#end of sib2, iclass 10, count 2 2006.196.08:18:10.38#ibcon#*mode == 0, iclass 10, count 2 2006.196.08:18:10.38#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.196.08:18:10.38#ibcon#[25=AT08-07\r\n] 2006.196.08:18:10.38#ibcon#*before write, iclass 10, count 2 2006.196.08:18:10.38#ibcon#enter sib2, iclass 10, count 2 2006.196.08:18:10.38#ibcon#flushed, iclass 10, count 2 2006.196.08:18:10.38#ibcon#about to write, iclass 10, count 2 2006.196.08:18:10.38#ibcon#wrote, iclass 10, count 2 2006.196.08:18:10.38#ibcon#about to read 3, iclass 10, count 2 2006.196.08:18:10.41#ibcon#read 3, iclass 10, count 2 2006.196.08:18:10.41#ibcon#about to read 4, iclass 10, count 2 2006.196.08:18:10.41#ibcon#read 4, iclass 10, count 2 2006.196.08:18:10.41#ibcon#about to read 5, iclass 10, count 2 2006.196.08:18:10.41#ibcon#read 5, iclass 10, count 2 2006.196.08:18:10.41#ibcon#about to read 6, iclass 10, count 2 2006.196.08:18:10.41#ibcon#read 6, iclass 10, count 2 2006.196.08:18:10.41#ibcon#end of sib2, iclass 10, count 2 2006.196.08:18:10.41#ibcon#*after write, iclass 10, count 2 2006.196.08:18:10.41#ibcon#*before return 0, iclass 10, count 2 2006.196.08:18:10.41#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.196.08:18:10.41#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.196.08:18:10.41#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.196.08:18:10.41#ibcon#ireg 7 cls_cnt 0 2006.196.08:18:10.41#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.196.08:18:10.53#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.196.08:18:10.53#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.196.08:18:10.53#ibcon#enter wrdev, iclass 10, count 0 2006.196.08:18:10.53#ibcon#first serial, iclass 10, count 0 2006.196.08:18:10.53#ibcon#enter sib2, iclass 10, count 0 2006.196.08:18:10.53#ibcon#flushed, iclass 10, count 0 2006.196.08:18:10.53#ibcon#about to write, iclass 10, count 0 2006.196.08:18:10.53#ibcon#wrote, iclass 10, count 0 2006.196.08:18:10.53#ibcon#about to read 3, iclass 10, count 0 2006.196.08:18:10.55#ibcon#read 3, iclass 10, count 0 2006.196.08:18:10.55#ibcon#about to read 4, iclass 10, count 0 2006.196.08:18:10.55#ibcon#read 4, iclass 10, count 0 2006.196.08:18:10.55#ibcon#about to read 5, iclass 10, count 0 2006.196.08:18:10.55#ibcon#read 5, iclass 10, count 0 2006.196.08:18:10.55#ibcon#about to read 6, iclass 10, count 0 2006.196.08:18:10.55#ibcon#read 6, iclass 10, count 0 2006.196.08:18:10.55#ibcon#end of sib2, iclass 10, count 0 2006.196.08:18:10.55#ibcon#*mode == 0, iclass 10, count 0 2006.196.08:18:10.55#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.196.08:18:10.55#ibcon#[25=USB\r\n] 2006.196.08:18:10.55#ibcon#*before write, iclass 10, count 0 2006.196.08:18:10.55#ibcon#enter sib2, iclass 10, count 0 2006.196.08:18:10.55#ibcon#flushed, iclass 10, count 0 2006.196.08:18:10.55#ibcon#about to write, iclass 10, count 0 2006.196.08:18:10.55#ibcon#wrote, iclass 10, count 0 2006.196.08:18:10.55#ibcon#about to read 3, iclass 10, count 0 2006.196.08:18:10.58#ibcon#read 3, iclass 10, count 0 2006.196.08:18:10.58#ibcon#about to read 4, iclass 10, count 0 2006.196.08:18:10.58#ibcon#read 4, iclass 10, count 0 2006.196.08:18:10.58#ibcon#about to read 5, iclass 10, count 0 2006.196.08:18:10.58#ibcon#read 5, iclass 10, count 0 2006.196.08:18:10.58#ibcon#about to read 6, iclass 10, count 0 2006.196.08:18:10.58#ibcon#read 6, iclass 10, count 0 2006.196.08:18:10.58#ibcon#end of sib2, iclass 10, count 0 2006.196.08:18:10.58#ibcon#*after write, iclass 10, count 0 2006.196.08:18:10.58#ibcon#*before return 0, iclass 10, count 0 2006.196.08:18:10.58#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.196.08:18:10.58#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.196.08:18:10.58#ibcon#about to clear, iclass 10 cls_cnt 0 2006.196.08:18:10.58#ibcon#cleared, iclass 10 cls_cnt 0 2006.196.08:18:10.58$vc4f8/vblo=1,632.99 2006.196.08:18:10.58#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.196.08:18:10.58#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.196.08:18:10.58#ibcon#ireg 17 cls_cnt 0 2006.196.08:18:10.58#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.196.08:18:10.58#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.196.08:18:10.58#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.196.08:18:10.58#ibcon#enter wrdev, iclass 12, count 0 2006.196.08:18:10.58#ibcon#first serial, iclass 12, count 0 2006.196.08:18:10.58#ibcon#enter sib2, iclass 12, count 0 2006.196.08:18:10.58#ibcon#flushed, iclass 12, count 0 2006.196.08:18:10.58#ibcon#about to write, iclass 12, count 0 2006.196.08:18:10.58#ibcon#wrote, iclass 12, count 0 2006.196.08:18:10.58#ibcon#about to read 3, iclass 12, count 0 2006.196.08:18:10.60#ibcon#read 3, iclass 12, count 0 2006.196.08:18:10.60#ibcon#about to read 4, iclass 12, count 0 2006.196.08:18:10.60#ibcon#read 4, iclass 12, count 0 2006.196.08:18:10.60#ibcon#about to read 5, iclass 12, count 0 2006.196.08:18:10.60#ibcon#read 5, iclass 12, count 0 2006.196.08:18:10.60#ibcon#about to read 6, iclass 12, count 0 2006.196.08:18:10.60#ibcon#read 6, iclass 12, count 0 2006.196.08:18:10.60#ibcon#end of sib2, iclass 12, count 0 2006.196.08:18:10.60#ibcon#*mode == 0, iclass 12, count 0 2006.196.08:18:10.60#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.196.08:18:10.60#ibcon#[28=FRQ=01,632.99\r\n] 2006.196.08:18:10.60#ibcon#*before write, iclass 12, count 0 2006.196.08:18:10.60#ibcon#enter sib2, iclass 12, count 0 2006.196.08:18:10.60#ibcon#flushed, iclass 12, count 0 2006.196.08:18:10.60#ibcon#about to write, iclass 12, count 0 2006.196.08:18:10.60#ibcon#wrote, iclass 12, count 0 2006.196.08:18:10.60#ibcon#about to read 3, iclass 12, count 0 2006.196.08:18:10.64#ibcon#read 3, iclass 12, count 0 2006.196.08:18:10.64#ibcon#about to read 4, iclass 12, count 0 2006.196.08:18:10.64#ibcon#read 4, iclass 12, count 0 2006.196.08:18:10.64#ibcon#about to read 5, iclass 12, count 0 2006.196.08:18:10.64#ibcon#read 5, iclass 12, count 0 2006.196.08:18:10.64#ibcon#about to read 6, iclass 12, count 0 2006.196.08:18:10.64#ibcon#read 6, iclass 12, count 0 2006.196.08:18:10.64#ibcon#end of sib2, iclass 12, count 0 2006.196.08:18:10.64#ibcon#*after write, iclass 12, count 0 2006.196.08:18:10.64#ibcon#*before return 0, iclass 12, count 0 2006.196.08:18:10.64#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.196.08:18:10.64#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.196.08:18:10.64#ibcon#about to clear, iclass 12 cls_cnt 0 2006.196.08:18:10.64#ibcon#cleared, iclass 12 cls_cnt 0 2006.196.08:18:10.64$vc4f8/vb=1,4 2006.196.08:18:10.64#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.196.08:18:10.64#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.196.08:18:10.64#ibcon#ireg 11 cls_cnt 2 2006.196.08:18:10.64#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.196.08:18:10.64#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.196.08:18:10.64#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.196.08:18:10.64#ibcon#enter wrdev, iclass 14, count 2 2006.196.08:18:10.64#ibcon#first serial, iclass 14, count 2 2006.196.08:18:10.64#ibcon#enter sib2, iclass 14, count 2 2006.196.08:18:10.64#ibcon#flushed, iclass 14, count 2 2006.196.08:18:10.64#ibcon#about to write, iclass 14, count 2 2006.196.08:18:10.64#ibcon#wrote, iclass 14, count 2 2006.196.08:18:10.64#ibcon#about to read 3, iclass 14, count 2 2006.196.08:18:10.66#ibcon#read 3, iclass 14, count 2 2006.196.08:18:10.66#ibcon#about to read 4, iclass 14, count 2 2006.196.08:18:10.66#ibcon#read 4, iclass 14, count 2 2006.196.08:18:10.66#ibcon#about to read 5, iclass 14, count 2 2006.196.08:18:10.66#ibcon#read 5, iclass 14, count 2 2006.196.08:18:10.66#ibcon#about to read 6, iclass 14, count 2 2006.196.08:18:10.66#ibcon#read 6, iclass 14, count 2 2006.196.08:18:10.66#ibcon#end of sib2, iclass 14, count 2 2006.196.08:18:10.66#ibcon#*mode == 0, iclass 14, count 2 2006.196.08:18:10.66#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.196.08:18:10.66#ibcon#[27=AT01-04\r\n] 2006.196.08:18:10.66#ibcon#*before write, iclass 14, count 2 2006.196.08:18:10.66#ibcon#enter sib2, iclass 14, count 2 2006.196.08:18:10.66#ibcon#flushed, iclass 14, count 2 2006.196.08:18:10.66#ibcon#about to write, iclass 14, count 2 2006.196.08:18:10.66#ibcon#wrote, iclass 14, count 2 2006.196.08:18:10.66#ibcon#about to read 3, iclass 14, count 2 2006.196.08:18:10.69#ibcon#read 3, iclass 14, count 2 2006.196.08:18:10.69#ibcon#about to read 4, iclass 14, count 2 2006.196.08:18:10.69#ibcon#read 4, iclass 14, count 2 2006.196.08:18:10.69#ibcon#about to read 5, iclass 14, count 2 2006.196.08:18:10.69#ibcon#read 5, iclass 14, count 2 2006.196.08:18:10.69#ibcon#about to read 6, iclass 14, count 2 2006.196.08:18:10.69#ibcon#read 6, iclass 14, count 2 2006.196.08:18:10.69#ibcon#end of sib2, iclass 14, count 2 2006.196.08:18:10.69#ibcon#*after write, iclass 14, count 2 2006.196.08:18:10.69#ibcon#*before return 0, iclass 14, count 2 2006.196.08:18:10.69#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.196.08:18:10.69#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.196.08:18:10.69#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.196.08:18:10.69#ibcon#ireg 7 cls_cnt 0 2006.196.08:18:10.69#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.196.08:18:10.81#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.196.08:18:10.81#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.196.08:18:10.81#ibcon#enter wrdev, iclass 14, count 0 2006.196.08:18:10.81#ibcon#first serial, iclass 14, count 0 2006.196.08:18:10.81#ibcon#enter sib2, iclass 14, count 0 2006.196.08:18:10.81#ibcon#flushed, iclass 14, count 0 2006.196.08:18:10.81#ibcon#about to write, iclass 14, count 0 2006.196.08:18:10.81#ibcon#wrote, iclass 14, count 0 2006.196.08:18:10.81#ibcon#about to read 3, iclass 14, count 0 2006.196.08:18:10.83#ibcon#read 3, iclass 14, count 0 2006.196.08:18:10.83#ibcon#about to read 4, iclass 14, count 0 2006.196.08:18:10.83#ibcon#read 4, iclass 14, count 0 2006.196.08:18:10.83#ibcon#about to read 5, iclass 14, count 0 2006.196.08:18:10.83#ibcon#read 5, iclass 14, count 0 2006.196.08:18:10.83#ibcon#about to read 6, iclass 14, count 0 2006.196.08:18:10.83#ibcon#read 6, iclass 14, count 0 2006.196.08:18:10.83#ibcon#end of sib2, iclass 14, count 0 2006.196.08:18:10.83#ibcon#*mode == 0, iclass 14, count 0 2006.196.08:18:10.83#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.196.08:18:10.83#ibcon#[27=USB\r\n] 2006.196.08:18:10.83#ibcon#*before write, iclass 14, count 0 2006.196.08:18:10.83#ibcon#enter sib2, iclass 14, count 0 2006.196.08:18:10.83#ibcon#flushed, iclass 14, count 0 2006.196.08:18:10.83#ibcon#about to write, iclass 14, count 0 2006.196.08:18:10.83#ibcon#wrote, iclass 14, count 0 2006.196.08:18:10.83#ibcon#about to read 3, iclass 14, count 0 2006.196.08:18:10.86#ibcon#read 3, iclass 14, count 0 2006.196.08:18:10.86#ibcon#about to read 4, iclass 14, count 0 2006.196.08:18:10.86#ibcon#read 4, iclass 14, count 0 2006.196.08:18:10.86#ibcon#about to read 5, iclass 14, count 0 2006.196.08:18:10.86#ibcon#read 5, iclass 14, count 0 2006.196.08:18:10.86#ibcon#about to read 6, iclass 14, count 0 2006.196.08:18:10.86#ibcon#read 6, iclass 14, count 0 2006.196.08:18:10.86#ibcon#end of sib2, iclass 14, count 0 2006.196.08:18:10.86#ibcon#*after write, iclass 14, count 0 2006.196.08:18:10.86#ibcon#*before return 0, iclass 14, count 0 2006.196.08:18:10.86#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.196.08:18:10.86#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.196.08:18:10.86#ibcon#about to clear, iclass 14 cls_cnt 0 2006.196.08:18:10.86#ibcon#cleared, iclass 14 cls_cnt 0 2006.196.08:18:10.86$vc4f8/vblo=2,640.99 2006.196.08:18:10.86#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.196.08:18:10.86#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.196.08:18:10.86#ibcon#ireg 17 cls_cnt 0 2006.196.08:18:10.86#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.196.08:18:10.86#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.196.08:18:10.86#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.196.08:18:10.86#ibcon#enter wrdev, iclass 16, count 0 2006.196.08:18:10.86#ibcon#first serial, iclass 16, count 0 2006.196.08:18:10.86#ibcon#enter sib2, iclass 16, count 0 2006.196.08:18:10.86#ibcon#flushed, iclass 16, count 0 2006.196.08:18:10.86#ibcon#about to write, iclass 16, count 0 2006.196.08:18:10.86#ibcon#wrote, iclass 16, count 0 2006.196.08:18:10.86#ibcon#about to read 3, iclass 16, count 0 2006.196.08:18:10.88#ibcon#read 3, iclass 16, count 0 2006.196.08:18:10.88#ibcon#about to read 4, iclass 16, count 0 2006.196.08:18:10.88#ibcon#read 4, iclass 16, count 0 2006.196.08:18:10.88#ibcon#about to read 5, iclass 16, count 0 2006.196.08:18:10.88#ibcon#read 5, iclass 16, count 0 2006.196.08:18:10.88#ibcon#about to read 6, iclass 16, count 0 2006.196.08:18:10.88#ibcon#read 6, iclass 16, count 0 2006.196.08:18:10.88#ibcon#end of sib2, iclass 16, count 0 2006.196.08:18:10.88#ibcon#*mode == 0, iclass 16, count 0 2006.196.08:18:10.88#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.196.08:18:10.88#ibcon#[28=FRQ=02,640.99\r\n] 2006.196.08:18:10.88#ibcon#*before write, iclass 16, count 0 2006.196.08:18:10.88#ibcon#enter sib2, iclass 16, count 0 2006.196.08:18:10.88#ibcon#flushed, iclass 16, count 0 2006.196.08:18:10.88#ibcon#about to write, iclass 16, count 0 2006.196.08:18:10.88#ibcon#wrote, iclass 16, count 0 2006.196.08:18:10.88#ibcon#about to read 3, iclass 16, count 0 2006.196.08:18:10.92#ibcon#read 3, iclass 16, count 0 2006.196.08:18:10.92#ibcon#about to read 4, iclass 16, count 0 2006.196.08:18:10.92#ibcon#read 4, iclass 16, count 0 2006.196.08:18:10.92#ibcon#about to read 5, iclass 16, count 0 2006.196.08:18:10.92#ibcon#read 5, iclass 16, count 0 2006.196.08:18:10.92#ibcon#about to read 6, iclass 16, count 0 2006.196.08:18:10.92#ibcon#read 6, iclass 16, count 0 2006.196.08:18:10.92#ibcon#end of sib2, iclass 16, count 0 2006.196.08:18:10.92#ibcon#*after write, iclass 16, count 0 2006.196.08:18:10.92#ibcon#*before return 0, iclass 16, count 0 2006.196.08:18:10.92#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.196.08:18:10.92#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.196.08:18:10.92#ibcon#about to clear, iclass 16 cls_cnt 0 2006.196.08:18:10.92#ibcon#cleared, iclass 16 cls_cnt 0 2006.196.08:18:10.92$vc4f8/vb=2,4 2006.196.08:18:10.92#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.196.08:18:10.92#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.196.08:18:10.92#ibcon#ireg 11 cls_cnt 2 2006.196.08:18:10.92#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.196.08:18:10.98#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.196.08:18:10.98#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.196.08:18:10.98#ibcon#enter wrdev, iclass 18, count 2 2006.196.08:18:10.98#ibcon#first serial, iclass 18, count 2 2006.196.08:18:10.98#ibcon#enter sib2, iclass 18, count 2 2006.196.08:18:10.98#ibcon#flushed, iclass 18, count 2 2006.196.08:18:10.98#ibcon#about to write, iclass 18, count 2 2006.196.08:18:10.98#ibcon#wrote, iclass 18, count 2 2006.196.08:18:10.98#ibcon#about to read 3, iclass 18, count 2 2006.196.08:18:11.00#ibcon#read 3, iclass 18, count 2 2006.196.08:18:11.00#ibcon#about to read 4, iclass 18, count 2 2006.196.08:18:11.00#ibcon#read 4, iclass 18, count 2 2006.196.08:18:11.00#ibcon#about to read 5, iclass 18, count 2 2006.196.08:18:11.00#ibcon#read 5, iclass 18, count 2 2006.196.08:18:11.00#ibcon#about to read 6, iclass 18, count 2 2006.196.08:18:11.00#ibcon#read 6, iclass 18, count 2 2006.196.08:18:11.00#ibcon#end of sib2, iclass 18, count 2 2006.196.08:18:11.00#ibcon#*mode == 0, iclass 18, count 2 2006.196.08:18:11.00#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.196.08:18:11.00#ibcon#[27=AT02-04\r\n] 2006.196.08:18:11.00#ibcon#*before write, iclass 18, count 2 2006.196.08:18:11.00#ibcon#enter sib2, iclass 18, count 2 2006.196.08:18:11.00#ibcon#flushed, iclass 18, count 2 2006.196.08:18:11.00#ibcon#about to write, iclass 18, count 2 2006.196.08:18:11.00#ibcon#wrote, iclass 18, count 2 2006.196.08:18:11.00#ibcon#about to read 3, iclass 18, count 2 2006.196.08:18:11.03#ibcon#read 3, iclass 18, count 2 2006.196.08:18:11.03#ibcon#about to read 4, iclass 18, count 2 2006.196.08:18:11.03#ibcon#read 4, iclass 18, count 2 2006.196.08:18:11.03#ibcon#about to read 5, iclass 18, count 2 2006.196.08:18:11.03#ibcon#read 5, iclass 18, count 2 2006.196.08:18:11.03#ibcon#about to read 6, iclass 18, count 2 2006.196.08:18:11.03#ibcon#read 6, iclass 18, count 2 2006.196.08:18:11.03#ibcon#end of sib2, iclass 18, count 2 2006.196.08:18:11.03#ibcon#*after write, iclass 18, count 2 2006.196.08:18:11.03#ibcon#*before return 0, iclass 18, count 2 2006.196.08:18:11.03#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.196.08:18:11.03#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.196.08:18:11.03#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.196.08:18:11.03#ibcon#ireg 7 cls_cnt 0 2006.196.08:18:11.03#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.196.08:18:11.15#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.196.08:18:11.15#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.196.08:18:11.15#ibcon#enter wrdev, iclass 18, count 0 2006.196.08:18:11.15#ibcon#first serial, iclass 18, count 0 2006.196.08:18:11.15#ibcon#enter sib2, iclass 18, count 0 2006.196.08:18:11.15#ibcon#flushed, iclass 18, count 0 2006.196.08:18:11.15#ibcon#about to write, iclass 18, count 0 2006.196.08:18:11.15#ibcon#wrote, iclass 18, count 0 2006.196.08:18:11.15#ibcon#about to read 3, iclass 18, count 0 2006.196.08:18:11.17#ibcon#read 3, iclass 18, count 0 2006.196.08:18:11.17#ibcon#about to read 4, iclass 18, count 0 2006.196.08:18:11.17#ibcon#read 4, iclass 18, count 0 2006.196.08:18:11.17#ibcon#about to read 5, iclass 18, count 0 2006.196.08:18:11.17#ibcon#read 5, iclass 18, count 0 2006.196.08:18:11.17#ibcon#about to read 6, iclass 18, count 0 2006.196.08:18:11.17#ibcon#read 6, iclass 18, count 0 2006.196.08:18:11.17#ibcon#end of sib2, iclass 18, count 0 2006.196.08:18:11.17#ibcon#*mode == 0, iclass 18, count 0 2006.196.08:18:11.17#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.196.08:18:11.17#ibcon#[27=USB\r\n] 2006.196.08:18:11.17#ibcon#*before write, iclass 18, count 0 2006.196.08:18:11.17#ibcon#enter sib2, iclass 18, count 0 2006.196.08:18:11.17#ibcon#flushed, iclass 18, count 0 2006.196.08:18:11.17#ibcon#about to write, iclass 18, count 0 2006.196.08:18:11.17#ibcon#wrote, iclass 18, count 0 2006.196.08:18:11.17#ibcon#about to read 3, iclass 18, count 0 2006.196.08:18:11.20#ibcon#read 3, iclass 18, count 0 2006.196.08:18:11.20#ibcon#about to read 4, iclass 18, count 0 2006.196.08:18:11.20#ibcon#read 4, iclass 18, count 0 2006.196.08:18:11.20#ibcon#about to read 5, iclass 18, count 0 2006.196.08:18:11.20#ibcon#read 5, iclass 18, count 0 2006.196.08:18:11.20#ibcon#about to read 6, iclass 18, count 0 2006.196.08:18:11.20#ibcon#read 6, iclass 18, count 0 2006.196.08:18:11.20#ibcon#end of sib2, iclass 18, count 0 2006.196.08:18:11.20#ibcon#*after write, iclass 18, count 0 2006.196.08:18:11.20#ibcon#*before return 0, iclass 18, count 0 2006.196.08:18:11.20#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.196.08:18:11.20#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.196.08:18:11.20#ibcon#about to clear, iclass 18 cls_cnt 0 2006.196.08:18:11.20#ibcon#cleared, iclass 18 cls_cnt 0 2006.196.08:18:11.20$vc4f8/vblo=3,656.99 2006.196.08:18:11.20#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.196.08:18:11.20#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.196.08:18:11.20#ibcon#ireg 17 cls_cnt 0 2006.196.08:18:11.20#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.196.08:18:11.20#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.196.08:18:11.20#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.196.08:18:11.20#ibcon#enter wrdev, iclass 20, count 0 2006.196.08:18:11.20#ibcon#first serial, iclass 20, count 0 2006.196.08:18:11.20#ibcon#enter sib2, iclass 20, count 0 2006.196.08:18:11.20#ibcon#flushed, iclass 20, count 0 2006.196.08:18:11.20#ibcon#about to write, iclass 20, count 0 2006.196.08:18:11.20#ibcon#wrote, iclass 20, count 0 2006.196.08:18:11.20#ibcon#about to read 3, iclass 20, count 0 2006.196.08:18:11.22#ibcon#read 3, iclass 20, count 0 2006.196.08:18:11.22#ibcon#about to read 4, iclass 20, count 0 2006.196.08:18:11.22#ibcon#read 4, iclass 20, count 0 2006.196.08:18:11.22#ibcon#about to read 5, iclass 20, count 0 2006.196.08:18:11.22#ibcon#read 5, iclass 20, count 0 2006.196.08:18:11.22#ibcon#about to read 6, iclass 20, count 0 2006.196.08:18:11.22#ibcon#read 6, iclass 20, count 0 2006.196.08:18:11.22#ibcon#end of sib2, iclass 20, count 0 2006.196.08:18:11.22#ibcon#*mode == 0, iclass 20, count 0 2006.196.08:18:11.22#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.196.08:18:11.22#ibcon#[28=FRQ=03,656.99\r\n] 2006.196.08:18:11.22#ibcon#*before write, iclass 20, count 0 2006.196.08:18:11.22#ibcon#enter sib2, iclass 20, count 0 2006.196.08:18:11.22#ibcon#flushed, iclass 20, count 0 2006.196.08:18:11.22#ibcon#about to write, iclass 20, count 0 2006.196.08:18:11.22#ibcon#wrote, iclass 20, count 0 2006.196.08:18:11.22#ibcon#about to read 3, iclass 20, count 0 2006.196.08:18:11.26#ibcon#read 3, iclass 20, count 0 2006.196.08:18:11.26#ibcon#about to read 4, iclass 20, count 0 2006.196.08:18:11.26#ibcon#read 4, iclass 20, count 0 2006.196.08:18:11.26#ibcon#about to read 5, iclass 20, count 0 2006.196.08:18:11.26#ibcon#read 5, iclass 20, count 0 2006.196.08:18:11.26#ibcon#about to read 6, iclass 20, count 0 2006.196.08:18:11.26#ibcon#read 6, iclass 20, count 0 2006.196.08:18:11.26#ibcon#end of sib2, iclass 20, count 0 2006.196.08:18:11.26#ibcon#*after write, iclass 20, count 0 2006.196.08:18:11.26#ibcon#*before return 0, iclass 20, count 0 2006.196.08:18:11.26#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.196.08:18:11.26#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.196.08:18:11.26#ibcon#about to clear, iclass 20 cls_cnt 0 2006.196.08:18:11.26#ibcon#cleared, iclass 20 cls_cnt 0 2006.196.08:18:11.26$vc4f8/vb=3,4 2006.196.08:18:11.26#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.196.08:18:11.26#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.196.08:18:11.26#ibcon#ireg 11 cls_cnt 2 2006.196.08:18:11.26#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.196.08:18:11.32#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.196.08:18:11.32#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.196.08:18:11.32#ibcon#enter wrdev, iclass 22, count 2 2006.196.08:18:11.32#ibcon#first serial, iclass 22, count 2 2006.196.08:18:11.32#ibcon#enter sib2, iclass 22, count 2 2006.196.08:18:11.32#ibcon#flushed, iclass 22, count 2 2006.196.08:18:11.32#ibcon#about to write, iclass 22, count 2 2006.196.08:18:11.32#ibcon#wrote, iclass 22, count 2 2006.196.08:18:11.32#ibcon#about to read 3, iclass 22, count 2 2006.196.08:18:11.34#ibcon#read 3, iclass 22, count 2 2006.196.08:18:11.34#ibcon#about to read 4, iclass 22, count 2 2006.196.08:18:11.34#ibcon#read 4, iclass 22, count 2 2006.196.08:18:11.34#ibcon#about to read 5, iclass 22, count 2 2006.196.08:18:11.34#ibcon#read 5, iclass 22, count 2 2006.196.08:18:11.34#ibcon#about to read 6, iclass 22, count 2 2006.196.08:18:11.34#ibcon#read 6, iclass 22, count 2 2006.196.08:18:11.34#ibcon#end of sib2, iclass 22, count 2 2006.196.08:18:11.34#ibcon#*mode == 0, iclass 22, count 2 2006.196.08:18:11.34#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.196.08:18:11.34#ibcon#[27=AT03-04\r\n] 2006.196.08:18:11.34#ibcon#*before write, iclass 22, count 2 2006.196.08:18:11.34#ibcon#enter sib2, iclass 22, count 2 2006.196.08:18:11.34#ibcon#flushed, iclass 22, count 2 2006.196.08:18:11.34#ibcon#about to write, iclass 22, count 2 2006.196.08:18:11.34#ibcon#wrote, iclass 22, count 2 2006.196.08:18:11.34#ibcon#about to read 3, iclass 22, count 2 2006.196.08:18:11.37#ibcon#read 3, iclass 22, count 2 2006.196.08:18:11.37#ibcon#about to read 4, iclass 22, count 2 2006.196.08:18:11.37#ibcon#read 4, iclass 22, count 2 2006.196.08:18:11.37#ibcon#about to read 5, iclass 22, count 2 2006.196.08:18:11.37#ibcon#read 5, iclass 22, count 2 2006.196.08:18:11.37#ibcon#about to read 6, iclass 22, count 2 2006.196.08:18:11.37#ibcon#read 6, iclass 22, count 2 2006.196.08:18:11.37#ibcon#end of sib2, iclass 22, count 2 2006.196.08:18:11.37#ibcon#*after write, iclass 22, count 2 2006.196.08:18:11.37#ibcon#*before return 0, iclass 22, count 2 2006.196.08:18:11.37#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.196.08:18:11.37#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.196.08:18:11.37#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.196.08:18:11.37#ibcon#ireg 7 cls_cnt 0 2006.196.08:18:11.37#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.196.08:18:11.49#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.196.08:18:11.49#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.196.08:18:11.49#ibcon#enter wrdev, iclass 22, count 0 2006.196.08:18:11.49#ibcon#first serial, iclass 22, count 0 2006.196.08:18:11.49#ibcon#enter sib2, iclass 22, count 0 2006.196.08:18:11.49#ibcon#flushed, iclass 22, count 0 2006.196.08:18:11.49#ibcon#about to write, iclass 22, count 0 2006.196.08:18:11.49#ibcon#wrote, iclass 22, count 0 2006.196.08:18:11.49#ibcon#about to read 3, iclass 22, count 0 2006.196.08:18:11.51#ibcon#read 3, iclass 22, count 0 2006.196.08:18:11.51#ibcon#about to read 4, iclass 22, count 0 2006.196.08:18:11.51#ibcon#read 4, iclass 22, count 0 2006.196.08:18:11.51#ibcon#about to read 5, iclass 22, count 0 2006.196.08:18:11.51#ibcon#read 5, iclass 22, count 0 2006.196.08:18:11.51#ibcon#about to read 6, iclass 22, count 0 2006.196.08:18:11.51#ibcon#read 6, iclass 22, count 0 2006.196.08:18:11.51#ibcon#end of sib2, iclass 22, count 0 2006.196.08:18:11.51#ibcon#*mode == 0, iclass 22, count 0 2006.196.08:18:11.51#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.196.08:18:11.51#ibcon#[27=USB\r\n] 2006.196.08:18:11.51#ibcon#*before write, iclass 22, count 0 2006.196.08:18:11.51#ibcon#enter sib2, iclass 22, count 0 2006.196.08:18:11.51#ibcon#flushed, iclass 22, count 0 2006.196.08:18:11.51#ibcon#about to write, iclass 22, count 0 2006.196.08:18:11.51#ibcon#wrote, iclass 22, count 0 2006.196.08:18:11.51#ibcon#about to read 3, iclass 22, count 0 2006.196.08:18:11.54#ibcon#read 3, iclass 22, count 0 2006.196.08:18:11.54#ibcon#about to read 4, iclass 22, count 0 2006.196.08:18:11.54#ibcon#read 4, iclass 22, count 0 2006.196.08:18:11.54#ibcon#about to read 5, iclass 22, count 0 2006.196.08:18:11.54#ibcon#read 5, iclass 22, count 0 2006.196.08:18:11.54#ibcon#about to read 6, iclass 22, count 0 2006.196.08:18:11.54#ibcon#read 6, iclass 22, count 0 2006.196.08:18:11.54#ibcon#end of sib2, iclass 22, count 0 2006.196.08:18:11.54#ibcon#*after write, iclass 22, count 0 2006.196.08:18:11.54#ibcon#*before return 0, iclass 22, count 0 2006.196.08:18:11.54#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.196.08:18:11.54#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.196.08:18:11.54#ibcon#about to clear, iclass 22 cls_cnt 0 2006.196.08:18:11.54#ibcon#cleared, iclass 22 cls_cnt 0 2006.196.08:18:11.54$vc4f8/vblo=4,712.99 2006.196.08:18:11.54#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.196.08:18:11.54#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.196.08:18:11.54#ibcon#ireg 17 cls_cnt 0 2006.196.08:18:11.54#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.196.08:18:11.54#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.196.08:18:11.54#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.196.08:18:11.54#ibcon#enter wrdev, iclass 24, count 0 2006.196.08:18:11.54#ibcon#first serial, iclass 24, count 0 2006.196.08:18:11.54#ibcon#enter sib2, iclass 24, count 0 2006.196.08:18:11.54#ibcon#flushed, iclass 24, count 0 2006.196.08:18:11.54#ibcon#about to write, iclass 24, count 0 2006.196.08:18:11.54#ibcon#wrote, iclass 24, count 0 2006.196.08:18:11.54#ibcon#about to read 3, iclass 24, count 0 2006.196.08:18:11.56#ibcon#read 3, iclass 24, count 0 2006.196.08:18:11.56#ibcon#about to read 4, iclass 24, count 0 2006.196.08:18:11.56#ibcon#read 4, iclass 24, count 0 2006.196.08:18:11.56#ibcon#about to read 5, iclass 24, count 0 2006.196.08:18:11.56#ibcon#read 5, iclass 24, count 0 2006.196.08:18:11.56#ibcon#about to read 6, iclass 24, count 0 2006.196.08:18:11.56#ibcon#read 6, iclass 24, count 0 2006.196.08:18:11.56#ibcon#end of sib2, iclass 24, count 0 2006.196.08:18:11.56#ibcon#*mode == 0, iclass 24, count 0 2006.196.08:18:11.56#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.196.08:18:11.56#ibcon#[28=FRQ=04,712.99\r\n] 2006.196.08:18:11.56#ibcon#*before write, iclass 24, count 0 2006.196.08:18:11.56#ibcon#enter sib2, iclass 24, count 0 2006.196.08:18:11.56#ibcon#flushed, iclass 24, count 0 2006.196.08:18:11.56#ibcon#about to write, iclass 24, count 0 2006.196.08:18:11.56#ibcon#wrote, iclass 24, count 0 2006.196.08:18:11.56#ibcon#about to read 3, iclass 24, count 0 2006.196.08:18:11.60#ibcon#read 3, iclass 24, count 0 2006.196.08:18:11.60#ibcon#about to read 4, iclass 24, count 0 2006.196.08:18:11.60#ibcon#read 4, iclass 24, count 0 2006.196.08:18:11.60#ibcon#about to read 5, iclass 24, count 0 2006.196.08:18:11.60#ibcon#read 5, iclass 24, count 0 2006.196.08:18:11.60#ibcon#about to read 6, iclass 24, count 0 2006.196.08:18:11.60#ibcon#read 6, iclass 24, count 0 2006.196.08:18:11.60#ibcon#end of sib2, iclass 24, count 0 2006.196.08:18:11.60#ibcon#*after write, iclass 24, count 0 2006.196.08:18:11.60#ibcon#*before return 0, iclass 24, count 0 2006.196.08:18:11.60#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.196.08:18:11.60#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.196.08:18:11.60#ibcon#about to clear, iclass 24 cls_cnt 0 2006.196.08:18:11.60#ibcon#cleared, iclass 24 cls_cnt 0 2006.196.08:18:11.60$vc4f8/vb=4,4 2006.196.08:18:11.60#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.196.08:18:11.60#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.196.08:18:11.60#ibcon#ireg 11 cls_cnt 2 2006.196.08:18:11.60#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.196.08:18:11.66#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.196.08:18:11.66#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.196.08:18:11.66#ibcon#enter wrdev, iclass 26, count 2 2006.196.08:18:11.66#ibcon#first serial, iclass 26, count 2 2006.196.08:18:11.66#ibcon#enter sib2, iclass 26, count 2 2006.196.08:18:11.66#ibcon#flushed, iclass 26, count 2 2006.196.08:18:11.66#ibcon#about to write, iclass 26, count 2 2006.196.08:18:11.66#ibcon#wrote, iclass 26, count 2 2006.196.08:18:11.66#ibcon#about to read 3, iclass 26, count 2 2006.196.08:18:11.68#ibcon#read 3, iclass 26, count 2 2006.196.08:18:11.68#ibcon#about to read 4, iclass 26, count 2 2006.196.08:18:11.68#ibcon#read 4, iclass 26, count 2 2006.196.08:18:11.68#ibcon#about to read 5, iclass 26, count 2 2006.196.08:18:11.68#ibcon#read 5, iclass 26, count 2 2006.196.08:18:11.68#ibcon#about to read 6, iclass 26, count 2 2006.196.08:18:11.68#ibcon#read 6, iclass 26, count 2 2006.196.08:18:11.68#ibcon#end of sib2, iclass 26, count 2 2006.196.08:18:11.68#ibcon#*mode == 0, iclass 26, count 2 2006.196.08:18:11.68#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.196.08:18:11.68#ibcon#[27=AT04-04\r\n] 2006.196.08:18:11.68#ibcon#*before write, iclass 26, count 2 2006.196.08:18:11.68#ibcon#enter sib2, iclass 26, count 2 2006.196.08:18:11.68#ibcon#flushed, iclass 26, count 2 2006.196.08:18:11.68#ibcon#about to write, iclass 26, count 2 2006.196.08:18:11.68#ibcon#wrote, iclass 26, count 2 2006.196.08:18:11.68#ibcon#about to read 3, iclass 26, count 2 2006.196.08:18:11.71#ibcon#read 3, iclass 26, count 2 2006.196.08:18:11.71#ibcon#about to read 4, iclass 26, count 2 2006.196.08:18:11.71#ibcon#read 4, iclass 26, count 2 2006.196.08:18:11.71#ibcon#about to read 5, iclass 26, count 2 2006.196.08:18:11.71#ibcon#read 5, iclass 26, count 2 2006.196.08:18:11.71#ibcon#about to read 6, iclass 26, count 2 2006.196.08:18:11.71#ibcon#read 6, iclass 26, count 2 2006.196.08:18:11.71#ibcon#end of sib2, iclass 26, count 2 2006.196.08:18:11.71#ibcon#*after write, iclass 26, count 2 2006.196.08:18:11.71#ibcon#*before return 0, iclass 26, count 2 2006.196.08:18:11.71#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.196.08:18:11.71#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.196.08:18:11.71#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.196.08:18:11.71#ibcon#ireg 7 cls_cnt 0 2006.196.08:18:11.71#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.196.08:18:11.83#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.196.08:18:11.83#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.196.08:18:11.83#ibcon#enter wrdev, iclass 26, count 0 2006.196.08:18:11.83#ibcon#first serial, iclass 26, count 0 2006.196.08:18:11.83#ibcon#enter sib2, iclass 26, count 0 2006.196.08:18:11.83#ibcon#flushed, iclass 26, count 0 2006.196.08:18:11.83#ibcon#about to write, iclass 26, count 0 2006.196.08:18:11.83#ibcon#wrote, iclass 26, count 0 2006.196.08:18:11.83#ibcon#about to read 3, iclass 26, count 0 2006.196.08:18:11.85#ibcon#read 3, iclass 26, count 0 2006.196.08:18:11.85#ibcon#about to read 4, iclass 26, count 0 2006.196.08:18:11.85#ibcon#read 4, iclass 26, count 0 2006.196.08:18:11.85#ibcon#about to read 5, iclass 26, count 0 2006.196.08:18:11.85#ibcon#read 5, iclass 26, count 0 2006.196.08:18:11.85#ibcon#about to read 6, iclass 26, count 0 2006.196.08:18:11.85#ibcon#read 6, iclass 26, count 0 2006.196.08:18:11.85#ibcon#end of sib2, iclass 26, count 0 2006.196.08:18:11.85#ibcon#*mode == 0, iclass 26, count 0 2006.196.08:18:11.85#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.196.08:18:11.85#ibcon#[27=USB\r\n] 2006.196.08:18:11.85#ibcon#*before write, iclass 26, count 0 2006.196.08:18:11.85#ibcon#enter sib2, iclass 26, count 0 2006.196.08:18:11.85#ibcon#flushed, iclass 26, count 0 2006.196.08:18:11.85#ibcon#about to write, iclass 26, count 0 2006.196.08:18:11.85#ibcon#wrote, iclass 26, count 0 2006.196.08:18:11.85#ibcon#about to read 3, iclass 26, count 0 2006.196.08:18:11.88#ibcon#read 3, iclass 26, count 0 2006.196.08:18:11.88#ibcon#about to read 4, iclass 26, count 0 2006.196.08:18:11.88#ibcon#read 4, iclass 26, count 0 2006.196.08:18:11.88#ibcon#about to read 5, iclass 26, count 0 2006.196.08:18:11.88#ibcon#read 5, iclass 26, count 0 2006.196.08:18:11.88#ibcon#about to read 6, iclass 26, count 0 2006.196.08:18:11.88#ibcon#read 6, iclass 26, count 0 2006.196.08:18:11.88#ibcon#end of sib2, iclass 26, count 0 2006.196.08:18:11.88#ibcon#*after write, iclass 26, count 0 2006.196.08:18:11.88#ibcon#*before return 0, iclass 26, count 0 2006.196.08:18:11.88#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.196.08:18:11.88#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.196.08:18:11.88#ibcon#about to clear, iclass 26 cls_cnt 0 2006.196.08:18:11.88#ibcon#cleared, iclass 26 cls_cnt 0 2006.196.08:18:11.88$vc4f8/vblo=5,744.99 2006.196.08:18:11.88#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.196.08:18:11.88#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.196.08:18:11.88#ibcon#ireg 17 cls_cnt 0 2006.196.08:18:11.88#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.196.08:18:11.88#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.196.08:18:11.88#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.196.08:18:11.88#ibcon#enter wrdev, iclass 28, count 0 2006.196.08:18:11.88#ibcon#first serial, iclass 28, count 0 2006.196.08:18:11.88#ibcon#enter sib2, iclass 28, count 0 2006.196.08:18:11.88#ibcon#flushed, iclass 28, count 0 2006.196.08:18:11.88#ibcon#about to write, iclass 28, count 0 2006.196.08:18:11.88#ibcon#wrote, iclass 28, count 0 2006.196.08:18:11.88#ibcon#about to read 3, iclass 28, count 0 2006.196.08:18:11.90#ibcon#read 3, iclass 28, count 0 2006.196.08:18:11.90#ibcon#about to read 4, iclass 28, count 0 2006.196.08:18:11.90#ibcon#read 4, iclass 28, count 0 2006.196.08:18:11.90#ibcon#about to read 5, iclass 28, count 0 2006.196.08:18:11.90#ibcon#read 5, iclass 28, count 0 2006.196.08:18:11.90#ibcon#about to read 6, iclass 28, count 0 2006.196.08:18:11.90#ibcon#read 6, iclass 28, count 0 2006.196.08:18:11.90#ibcon#end of sib2, iclass 28, count 0 2006.196.08:18:11.90#ibcon#*mode == 0, iclass 28, count 0 2006.196.08:18:11.90#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.196.08:18:11.90#ibcon#[28=FRQ=05,744.99\r\n] 2006.196.08:18:11.90#ibcon#*before write, iclass 28, count 0 2006.196.08:18:11.90#ibcon#enter sib2, iclass 28, count 0 2006.196.08:18:11.90#ibcon#flushed, iclass 28, count 0 2006.196.08:18:11.90#ibcon#about to write, iclass 28, count 0 2006.196.08:18:11.90#ibcon#wrote, iclass 28, count 0 2006.196.08:18:11.90#ibcon#about to read 3, iclass 28, count 0 2006.196.08:18:11.94#ibcon#read 3, iclass 28, count 0 2006.196.08:18:11.94#ibcon#about to read 4, iclass 28, count 0 2006.196.08:18:11.94#ibcon#read 4, iclass 28, count 0 2006.196.08:18:11.94#ibcon#about to read 5, iclass 28, count 0 2006.196.08:18:11.94#ibcon#read 5, iclass 28, count 0 2006.196.08:18:11.94#ibcon#about to read 6, iclass 28, count 0 2006.196.08:18:11.94#ibcon#read 6, iclass 28, count 0 2006.196.08:18:11.94#ibcon#end of sib2, iclass 28, count 0 2006.196.08:18:11.94#ibcon#*after write, iclass 28, count 0 2006.196.08:18:11.94#ibcon#*before return 0, iclass 28, count 0 2006.196.08:18:11.94#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.196.08:18:11.94#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.196.08:18:11.94#ibcon#about to clear, iclass 28 cls_cnt 0 2006.196.08:18:11.94#ibcon#cleared, iclass 28 cls_cnt 0 2006.196.08:18:11.94$vc4f8/vb=5,4 2006.196.08:18:11.94#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.196.08:18:11.94#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.196.08:18:11.94#ibcon#ireg 11 cls_cnt 2 2006.196.08:18:11.94#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.196.08:18:12.00#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.196.08:18:12.00#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.196.08:18:12.00#ibcon#enter wrdev, iclass 30, count 2 2006.196.08:18:12.00#ibcon#first serial, iclass 30, count 2 2006.196.08:18:12.00#ibcon#enter sib2, iclass 30, count 2 2006.196.08:18:12.00#ibcon#flushed, iclass 30, count 2 2006.196.08:18:12.00#ibcon#about to write, iclass 30, count 2 2006.196.08:18:12.00#ibcon#wrote, iclass 30, count 2 2006.196.08:18:12.00#ibcon#about to read 3, iclass 30, count 2 2006.196.08:18:12.02#ibcon#read 3, iclass 30, count 2 2006.196.08:18:12.02#ibcon#about to read 4, iclass 30, count 2 2006.196.08:18:12.02#ibcon#read 4, iclass 30, count 2 2006.196.08:18:12.02#ibcon#about to read 5, iclass 30, count 2 2006.196.08:18:12.02#ibcon#read 5, iclass 30, count 2 2006.196.08:18:12.02#ibcon#about to read 6, iclass 30, count 2 2006.196.08:18:12.02#ibcon#read 6, iclass 30, count 2 2006.196.08:18:12.02#ibcon#end of sib2, iclass 30, count 2 2006.196.08:18:12.02#ibcon#*mode == 0, iclass 30, count 2 2006.196.08:18:12.02#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.196.08:18:12.02#ibcon#[27=AT05-04\r\n] 2006.196.08:18:12.02#ibcon#*before write, iclass 30, count 2 2006.196.08:18:12.02#ibcon#enter sib2, iclass 30, count 2 2006.196.08:18:12.02#ibcon#flushed, iclass 30, count 2 2006.196.08:18:12.02#ibcon#about to write, iclass 30, count 2 2006.196.08:18:12.02#ibcon#wrote, iclass 30, count 2 2006.196.08:18:12.02#ibcon#about to read 3, iclass 30, count 2 2006.196.08:18:12.05#ibcon#read 3, iclass 30, count 2 2006.196.08:18:12.05#ibcon#about to read 4, iclass 30, count 2 2006.196.08:18:12.05#ibcon#read 4, iclass 30, count 2 2006.196.08:18:12.05#ibcon#about to read 5, iclass 30, count 2 2006.196.08:18:12.05#ibcon#read 5, iclass 30, count 2 2006.196.08:18:12.05#ibcon#about to read 6, iclass 30, count 2 2006.196.08:18:12.05#ibcon#read 6, iclass 30, count 2 2006.196.08:18:12.05#ibcon#end of sib2, iclass 30, count 2 2006.196.08:18:12.05#ibcon#*after write, iclass 30, count 2 2006.196.08:18:12.05#ibcon#*before return 0, iclass 30, count 2 2006.196.08:18:12.05#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.196.08:18:12.05#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.196.08:18:12.05#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.196.08:18:12.05#ibcon#ireg 7 cls_cnt 0 2006.196.08:18:12.05#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.196.08:18:12.17#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.196.08:18:12.17#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.196.08:18:12.17#ibcon#enter wrdev, iclass 30, count 0 2006.196.08:18:12.17#ibcon#first serial, iclass 30, count 0 2006.196.08:18:12.17#ibcon#enter sib2, iclass 30, count 0 2006.196.08:18:12.17#ibcon#flushed, iclass 30, count 0 2006.196.08:18:12.17#ibcon#about to write, iclass 30, count 0 2006.196.08:18:12.17#ibcon#wrote, iclass 30, count 0 2006.196.08:18:12.17#ibcon#about to read 3, iclass 30, count 0 2006.196.08:18:12.20#ibcon#read 3, iclass 30, count 0 2006.196.08:18:12.20#ibcon#about to read 4, iclass 30, count 0 2006.196.08:18:12.20#ibcon#read 4, iclass 30, count 0 2006.196.08:18:12.20#ibcon#about to read 5, iclass 30, count 0 2006.196.08:18:12.20#ibcon#read 5, iclass 30, count 0 2006.196.08:18:12.20#ibcon#about to read 6, iclass 30, count 0 2006.196.08:18:12.20#ibcon#read 6, iclass 30, count 0 2006.196.08:18:12.20#ibcon#end of sib2, iclass 30, count 0 2006.196.08:18:12.20#ibcon#*mode == 0, iclass 30, count 0 2006.196.08:18:12.20#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.196.08:18:12.20#ibcon#[27=USB\r\n] 2006.196.08:18:12.20#ibcon#*before write, iclass 30, count 0 2006.196.08:18:12.20#ibcon#enter sib2, iclass 30, count 0 2006.196.08:18:12.20#ibcon#flushed, iclass 30, count 0 2006.196.08:18:12.20#ibcon#about to write, iclass 30, count 0 2006.196.08:18:12.20#ibcon#wrote, iclass 30, count 0 2006.196.08:18:12.20#ibcon#about to read 3, iclass 30, count 0 2006.196.08:18:12.23#ibcon#read 3, iclass 30, count 0 2006.196.08:18:12.23#ibcon#about to read 4, iclass 30, count 0 2006.196.08:18:12.23#ibcon#read 4, iclass 30, count 0 2006.196.08:18:12.23#ibcon#about to read 5, iclass 30, count 0 2006.196.08:18:12.23#ibcon#read 5, iclass 30, count 0 2006.196.08:18:12.23#ibcon#about to read 6, iclass 30, count 0 2006.196.08:18:12.23#ibcon#read 6, iclass 30, count 0 2006.196.08:18:12.23#ibcon#end of sib2, iclass 30, count 0 2006.196.08:18:12.23#ibcon#*after write, iclass 30, count 0 2006.196.08:18:12.23#ibcon#*before return 0, iclass 30, count 0 2006.196.08:18:12.23#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.196.08:18:12.23#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.196.08:18:12.23#ibcon#about to clear, iclass 30 cls_cnt 0 2006.196.08:18:12.23#ibcon#cleared, iclass 30 cls_cnt 0 2006.196.08:18:12.23$vc4f8/vblo=6,752.99 2006.196.08:18:12.23#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.196.08:18:12.23#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.196.08:18:12.23#ibcon#ireg 17 cls_cnt 0 2006.196.08:18:12.23#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.196.08:18:12.23#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.196.08:18:12.23#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.196.08:18:12.23#ibcon#enter wrdev, iclass 32, count 0 2006.196.08:18:12.23#ibcon#first serial, iclass 32, count 0 2006.196.08:18:12.23#ibcon#enter sib2, iclass 32, count 0 2006.196.08:18:12.23#ibcon#flushed, iclass 32, count 0 2006.196.08:18:12.23#ibcon#about to write, iclass 32, count 0 2006.196.08:18:12.23#ibcon#wrote, iclass 32, count 0 2006.196.08:18:12.23#ibcon#about to read 3, iclass 32, count 0 2006.196.08:18:12.25#ibcon#read 3, iclass 32, count 0 2006.196.08:18:12.25#ibcon#about to read 4, iclass 32, count 0 2006.196.08:18:12.25#ibcon#read 4, iclass 32, count 0 2006.196.08:18:12.25#ibcon#about to read 5, iclass 32, count 0 2006.196.08:18:12.25#ibcon#read 5, iclass 32, count 0 2006.196.08:18:12.25#ibcon#about to read 6, iclass 32, count 0 2006.196.08:18:12.25#ibcon#read 6, iclass 32, count 0 2006.196.08:18:12.25#ibcon#end of sib2, iclass 32, count 0 2006.196.08:18:12.25#ibcon#*mode == 0, iclass 32, count 0 2006.196.08:18:12.25#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.196.08:18:12.25#ibcon#[28=FRQ=06,752.99\r\n] 2006.196.08:18:12.25#ibcon#*before write, iclass 32, count 0 2006.196.08:18:12.25#ibcon#enter sib2, iclass 32, count 0 2006.196.08:18:12.25#ibcon#flushed, iclass 32, count 0 2006.196.08:18:12.25#ibcon#about to write, iclass 32, count 0 2006.196.08:18:12.25#ibcon#wrote, iclass 32, count 0 2006.196.08:18:12.25#ibcon#about to read 3, iclass 32, count 0 2006.196.08:18:12.29#ibcon#read 3, iclass 32, count 0 2006.196.08:18:12.29#ibcon#about to read 4, iclass 32, count 0 2006.196.08:18:12.29#ibcon#read 4, iclass 32, count 0 2006.196.08:18:12.29#ibcon#about to read 5, iclass 32, count 0 2006.196.08:18:12.29#ibcon#read 5, iclass 32, count 0 2006.196.08:18:12.29#ibcon#about to read 6, iclass 32, count 0 2006.196.08:18:12.29#ibcon#read 6, iclass 32, count 0 2006.196.08:18:12.29#ibcon#end of sib2, iclass 32, count 0 2006.196.08:18:12.29#ibcon#*after write, iclass 32, count 0 2006.196.08:18:12.29#ibcon#*before return 0, iclass 32, count 0 2006.196.08:18:12.29#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.196.08:18:12.29#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.196.08:18:12.29#ibcon#about to clear, iclass 32 cls_cnt 0 2006.196.08:18:12.29#ibcon#cleared, iclass 32 cls_cnt 0 2006.196.08:18:12.29$vc4f8/vb=6,4 2006.196.08:18:12.29#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.196.08:18:12.29#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.196.08:18:12.29#ibcon#ireg 11 cls_cnt 2 2006.196.08:18:12.29#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.196.08:18:12.35#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.196.08:18:12.35#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.196.08:18:12.35#ibcon#enter wrdev, iclass 34, count 2 2006.196.08:18:12.35#ibcon#first serial, iclass 34, count 2 2006.196.08:18:12.35#ibcon#enter sib2, iclass 34, count 2 2006.196.08:18:12.35#ibcon#flushed, iclass 34, count 2 2006.196.08:18:12.35#ibcon#about to write, iclass 34, count 2 2006.196.08:18:12.35#ibcon#wrote, iclass 34, count 2 2006.196.08:18:12.35#ibcon#about to read 3, iclass 34, count 2 2006.196.08:18:12.37#ibcon#read 3, iclass 34, count 2 2006.196.08:18:12.37#ibcon#about to read 4, iclass 34, count 2 2006.196.08:18:12.37#ibcon#read 4, iclass 34, count 2 2006.196.08:18:12.37#ibcon#about to read 5, iclass 34, count 2 2006.196.08:18:12.37#ibcon#read 5, iclass 34, count 2 2006.196.08:18:12.37#ibcon#about to read 6, iclass 34, count 2 2006.196.08:18:12.37#ibcon#read 6, iclass 34, count 2 2006.196.08:18:12.37#ibcon#end of sib2, iclass 34, count 2 2006.196.08:18:12.37#ibcon#*mode == 0, iclass 34, count 2 2006.196.08:18:12.37#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.196.08:18:12.37#ibcon#[27=AT06-04\r\n] 2006.196.08:18:12.37#ibcon#*before write, iclass 34, count 2 2006.196.08:18:12.37#ibcon#enter sib2, iclass 34, count 2 2006.196.08:18:12.37#ibcon#flushed, iclass 34, count 2 2006.196.08:18:12.37#ibcon#about to write, iclass 34, count 2 2006.196.08:18:12.37#ibcon#wrote, iclass 34, count 2 2006.196.08:18:12.37#ibcon#about to read 3, iclass 34, count 2 2006.196.08:18:12.40#ibcon#read 3, iclass 34, count 2 2006.196.08:18:12.40#ibcon#about to read 4, iclass 34, count 2 2006.196.08:18:12.40#ibcon#read 4, iclass 34, count 2 2006.196.08:18:12.40#ibcon#about to read 5, iclass 34, count 2 2006.196.08:18:12.40#ibcon#read 5, iclass 34, count 2 2006.196.08:18:12.40#ibcon#about to read 6, iclass 34, count 2 2006.196.08:18:12.40#ibcon#read 6, iclass 34, count 2 2006.196.08:18:12.40#ibcon#end of sib2, iclass 34, count 2 2006.196.08:18:12.40#ibcon#*after write, iclass 34, count 2 2006.196.08:18:12.40#ibcon#*before return 0, iclass 34, count 2 2006.196.08:18:12.40#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.196.08:18:12.40#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.196.08:18:12.40#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.196.08:18:12.40#ibcon#ireg 7 cls_cnt 0 2006.196.08:18:12.40#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.196.08:18:12.52#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.196.08:18:12.52#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.196.08:18:12.52#ibcon#enter wrdev, iclass 34, count 0 2006.196.08:18:12.52#ibcon#first serial, iclass 34, count 0 2006.196.08:18:12.52#ibcon#enter sib2, iclass 34, count 0 2006.196.08:18:12.52#ibcon#flushed, iclass 34, count 0 2006.196.08:18:12.52#ibcon#about to write, iclass 34, count 0 2006.196.08:18:12.52#ibcon#wrote, iclass 34, count 0 2006.196.08:18:12.52#ibcon#about to read 3, iclass 34, count 0 2006.196.08:18:12.54#ibcon#read 3, iclass 34, count 0 2006.196.08:18:12.54#ibcon#about to read 4, iclass 34, count 0 2006.196.08:18:12.54#ibcon#read 4, iclass 34, count 0 2006.196.08:18:12.54#ibcon#about to read 5, iclass 34, count 0 2006.196.08:18:12.54#ibcon#read 5, iclass 34, count 0 2006.196.08:18:12.54#ibcon#about to read 6, iclass 34, count 0 2006.196.08:18:12.54#ibcon#read 6, iclass 34, count 0 2006.196.08:18:12.54#ibcon#end of sib2, iclass 34, count 0 2006.196.08:18:12.54#ibcon#*mode == 0, iclass 34, count 0 2006.196.08:18:12.54#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.196.08:18:12.54#ibcon#[27=USB\r\n] 2006.196.08:18:12.54#ibcon#*before write, iclass 34, count 0 2006.196.08:18:12.54#ibcon#enter sib2, iclass 34, count 0 2006.196.08:18:12.54#ibcon#flushed, iclass 34, count 0 2006.196.08:18:12.54#ibcon#about to write, iclass 34, count 0 2006.196.08:18:12.54#ibcon#wrote, iclass 34, count 0 2006.196.08:18:12.54#ibcon#about to read 3, iclass 34, count 0 2006.196.08:18:12.57#ibcon#read 3, iclass 34, count 0 2006.196.08:18:12.57#ibcon#about to read 4, iclass 34, count 0 2006.196.08:18:12.57#ibcon#read 4, iclass 34, count 0 2006.196.08:18:12.57#ibcon#about to read 5, iclass 34, count 0 2006.196.08:18:12.57#ibcon#read 5, iclass 34, count 0 2006.196.08:18:12.57#ibcon#about to read 6, iclass 34, count 0 2006.196.08:18:12.57#ibcon#read 6, iclass 34, count 0 2006.196.08:18:12.57#ibcon#end of sib2, iclass 34, count 0 2006.196.08:18:12.57#ibcon#*after write, iclass 34, count 0 2006.196.08:18:12.57#ibcon#*before return 0, iclass 34, count 0 2006.196.08:18:12.57#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.196.08:18:12.57#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.196.08:18:12.57#ibcon#about to clear, iclass 34 cls_cnt 0 2006.196.08:18:12.57#ibcon#cleared, iclass 34 cls_cnt 0 2006.196.08:18:12.57$vc4f8/vabw=wide 2006.196.08:18:12.57#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.196.08:18:12.57#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.196.08:18:12.57#ibcon#ireg 8 cls_cnt 0 2006.196.08:18:12.57#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.196.08:18:12.57#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.196.08:18:12.57#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.196.08:18:12.57#ibcon#enter wrdev, iclass 36, count 0 2006.196.08:18:12.57#ibcon#first serial, iclass 36, count 0 2006.196.08:18:12.57#ibcon#enter sib2, iclass 36, count 0 2006.196.08:18:12.57#ibcon#flushed, iclass 36, count 0 2006.196.08:18:12.57#ibcon#about to write, iclass 36, count 0 2006.196.08:18:12.57#ibcon#wrote, iclass 36, count 0 2006.196.08:18:12.57#ibcon#about to read 3, iclass 36, count 0 2006.196.08:18:12.59#ibcon#read 3, iclass 36, count 0 2006.196.08:18:12.59#ibcon#about to read 4, iclass 36, count 0 2006.196.08:18:12.59#ibcon#read 4, iclass 36, count 0 2006.196.08:18:12.59#ibcon#about to read 5, iclass 36, count 0 2006.196.08:18:12.59#ibcon#read 5, iclass 36, count 0 2006.196.08:18:12.59#ibcon#about to read 6, iclass 36, count 0 2006.196.08:18:12.59#ibcon#read 6, iclass 36, count 0 2006.196.08:18:12.59#ibcon#end of sib2, iclass 36, count 0 2006.196.08:18:12.59#ibcon#*mode == 0, iclass 36, count 0 2006.196.08:18:12.59#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.196.08:18:12.59#ibcon#[25=BW32\r\n] 2006.196.08:18:12.59#ibcon#*before write, iclass 36, count 0 2006.196.08:18:12.59#ibcon#enter sib2, iclass 36, count 0 2006.196.08:18:12.59#ibcon#flushed, iclass 36, count 0 2006.196.08:18:12.59#ibcon#about to write, iclass 36, count 0 2006.196.08:18:12.59#ibcon#wrote, iclass 36, count 0 2006.196.08:18:12.59#ibcon#about to read 3, iclass 36, count 0 2006.196.08:18:12.62#ibcon#read 3, iclass 36, count 0 2006.196.08:18:12.62#ibcon#about to read 4, iclass 36, count 0 2006.196.08:18:12.62#ibcon#read 4, iclass 36, count 0 2006.196.08:18:12.62#ibcon#about to read 5, iclass 36, count 0 2006.196.08:18:12.62#ibcon#read 5, iclass 36, count 0 2006.196.08:18:12.62#ibcon#about to read 6, iclass 36, count 0 2006.196.08:18:12.62#ibcon#read 6, iclass 36, count 0 2006.196.08:18:12.62#ibcon#end of sib2, iclass 36, count 0 2006.196.08:18:12.62#ibcon#*after write, iclass 36, count 0 2006.196.08:18:12.62#ibcon#*before return 0, iclass 36, count 0 2006.196.08:18:12.62#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.196.08:18:12.62#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.196.08:18:12.62#ibcon#about to clear, iclass 36 cls_cnt 0 2006.196.08:18:12.62#ibcon#cleared, iclass 36 cls_cnt 0 2006.196.08:18:12.62$vc4f8/vbbw=wide 2006.196.08:18:12.62#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.196.08:18:12.62#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.196.08:18:12.62#ibcon#ireg 8 cls_cnt 0 2006.196.08:18:12.62#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.196.08:18:12.69#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.196.08:18:12.69#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.196.08:18:12.69#ibcon#enter wrdev, iclass 38, count 0 2006.196.08:18:12.69#ibcon#first serial, iclass 38, count 0 2006.196.08:18:12.69#ibcon#enter sib2, iclass 38, count 0 2006.196.08:18:12.69#ibcon#flushed, iclass 38, count 0 2006.196.08:18:12.69#ibcon#about to write, iclass 38, count 0 2006.196.08:18:12.69#ibcon#wrote, iclass 38, count 0 2006.196.08:18:12.69#ibcon#about to read 3, iclass 38, count 0 2006.196.08:18:12.71#ibcon#read 3, iclass 38, count 0 2006.196.08:18:12.71#ibcon#about to read 4, iclass 38, count 0 2006.196.08:18:12.71#ibcon#read 4, iclass 38, count 0 2006.196.08:18:12.71#ibcon#about to read 5, iclass 38, count 0 2006.196.08:18:12.71#ibcon#read 5, iclass 38, count 0 2006.196.08:18:12.71#ibcon#about to read 6, iclass 38, count 0 2006.196.08:18:12.71#ibcon#read 6, iclass 38, count 0 2006.196.08:18:12.71#ibcon#end of sib2, iclass 38, count 0 2006.196.08:18:12.71#ibcon#*mode == 0, iclass 38, count 0 2006.196.08:18:12.71#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.196.08:18:12.71#ibcon#[27=BW32\r\n] 2006.196.08:18:12.71#ibcon#*before write, iclass 38, count 0 2006.196.08:18:12.71#ibcon#enter sib2, iclass 38, count 0 2006.196.08:18:12.71#ibcon#flushed, iclass 38, count 0 2006.196.08:18:12.71#ibcon#about to write, iclass 38, count 0 2006.196.08:18:12.71#ibcon#wrote, iclass 38, count 0 2006.196.08:18:12.71#ibcon#about to read 3, iclass 38, count 0 2006.196.08:18:12.74#ibcon#read 3, iclass 38, count 0 2006.196.08:18:12.74#ibcon#about to read 4, iclass 38, count 0 2006.196.08:18:12.74#ibcon#read 4, iclass 38, count 0 2006.196.08:18:12.74#ibcon#about to read 5, iclass 38, count 0 2006.196.08:18:12.74#ibcon#read 5, iclass 38, count 0 2006.196.08:18:12.74#ibcon#about to read 6, iclass 38, count 0 2006.196.08:18:12.74#ibcon#read 6, iclass 38, count 0 2006.196.08:18:12.74#ibcon#end of sib2, iclass 38, count 0 2006.196.08:18:12.74#ibcon#*after write, iclass 38, count 0 2006.196.08:18:12.74#ibcon#*before return 0, iclass 38, count 0 2006.196.08:18:12.74#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.196.08:18:12.74#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.196.08:18:12.74#ibcon#about to clear, iclass 38 cls_cnt 0 2006.196.08:18:12.74#ibcon#cleared, iclass 38 cls_cnt 0 2006.196.08:18:12.74$4f8m12a/ifd4f 2006.196.08:18:12.74$ifd4f/lo= 2006.196.08:18:12.74$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.196.08:18:12.74$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.196.08:18:12.74$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.196.08:18:12.74$ifd4f/patch= 2006.196.08:18:12.74$ifd4f/patch=lo1,a1,a2,a3,a4 2006.196.08:18:12.74$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.196.08:18:12.74$ifd4f/patch=lo3,a5,a6,a7,a8 2006.196.08:18:12.74$4f8m12a/"form=m,16.000,1:2 2006.196.08:18:12.74$4f8m12a/"tpicd 2006.196.08:18:12.74$4f8m12a/echo=off 2006.196.08:18:12.74$4f8m12a/xlog=off 2006.196.08:18:12.74:!2006.196.08:18:40 2006.196.08:18:25.14#trakl#Source acquired 2006.196.08:18:25.14#flagr#flagr/antenna,acquired 2006.196.08:18:40.00:preob 2006.196.08:18:41.14/onsource/TRACKING 2006.196.08:18:41.14:!2006.196.08:18:50 2006.196.08:18:50.00:data_valid=on 2006.196.08:18:50.00:midob 2006.196.08:18:50.14/onsource/TRACKING 2006.196.08:18:50.14/wx/28.99,1004.0,93 2006.196.08:18:50.26/cable/+6.3394E-03 2006.196.08:18:51.35/va/01,08,usb,yes,29,31 2006.196.08:18:51.35/va/02,07,usb,yes,30,31 2006.196.08:18:51.35/va/03,06,usb,yes,31,31 2006.196.08:18:51.35/va/04,07,usb,yes,31,33 2006.196.08:18:51.35/va/05,07,usb,yes,33,35 2006.196.08:18:51.35/va/06,06,usb,yes,32,32 2006.196.08:18:51.35/va/07,06,usb,yes,32,32 2006.196.08:18:51.35/va/08,07,usb,yes,31,30 2006.196.08:18:51.58/valo/01,532.99,yes,locked 2006.196.08:18:51.58/valo/02,572.99,yes,locked 2006.196.08:18:51.58/valo/03,672.99,yes,locked 2006.196.08:18:51.58/valo/04,832.99,yes,locked 2006.196.08:18:51.58/valo/05,652.99,yes,locked 2006.196.08:18:51.58/valo/06,772.99,yes,locked 2006.196.08:18:51.58/valo/07,832.99,yes,locked 2006.196.08:18:51.58/valo/08,852.99,yes,locked 2006.196.08:18:52.67/vb/01,04,usb,yes,29,28 2006.196.08:18:52.67/vb/02,04,usb,yes,31,32 2006.196.08:18:52.67/vb/03,04,usb,yes,27,31 2006.196.08:18:52.67/vb/04,04,usb,yes,28,28 2006.196.08:18:52.67/vb/05,04,usb,yes,27,30 2006.196.08:18:52.67/vb/06,04,usb,yes,27,30 2006.196.08:18:52.67/vb/07,04,usb,yes,30,29 2006.196.08:18:52.67/vb/08,04,usb,yes,27,30 2006.196.08:18:52.91/vblo/01,632.99,yes,locked 2006.196.08:18:52.91/vblo/02,640.99,yes,locked 2006.196.08:18:52.91/vblo/03,656.99,yes,locked 2006.196.08:18:52.91/vblo/04,712.99,yes,locked 2006.196.08:18:52.91/vblo/05,744.99,yes,locked 2006.196.08:18:52.91/vblo/06,752.99,yes,locked 2006.196.08:18:52.91/vblo/07,734.99,yes,locked 2006.196.08:18:52.91/vblo/08,744.99,yes,locked 2006.196.08:18:53.06/vabw/8 2006.196.08:18:53.21/vbbw/8 2006.196.08:18:53.30/xfe/off,on,15.0 2006.196.08:18:53.69/ifatt/23,28,28,28 2006.196.08:18:54.06/fmout-gps/S +3.31E-07 2006.196.08:18:54.13:!2006.196.08:19:50 2006.196.08:19:50.00:data_valid=off 2006.196.08:19:50.00:postob 2006.196.08:19:50.10/cable/+6.3390E-03 2006.196.08:19:50.10/wx/28.95,1004.1,93 2006.196.08:19:51.06/fmout-gps/S +3.33E-07 2006.196.08:19:51.06:scan_name=196-0820,k06196,60 2006.196.08:19:51.06:source=0823+033,082550.34,030924.5,2000.0,ccw 2006.196.08:19:51.14#flagr#flagr/antenna,new-source 2006.196.08:19:52.14:checkk5 2006.196.08:19:52.51/chk_autoobs//k5ts1/ autoobs is running! 2006.196.08:19:52.88/chk_autoobs//k5ts2/ autoobs is running! 2006.196.08:19:53.26/chk_autoobs//k5ts3/ autoobs is running! 2006.196.08:19:53.66/chk_autoobs//k5ts4/ autoobs is running! 2006.196.08:19:54.03/chk_obsdata//k5ts1/T1960818??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.196.08:19:54.40/chk_obsdata//k5ts2/T1960818??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.196.08:19:54.76/chk_obsdata//k5ts3/T1960818??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.196.08:19:55.13/chk_obsdata//k5ts4/T1960818??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.196.08:19:55.82/k5log//k5ts1_log_newline 2006.196.08:19:56.51/k5log//k5ts2_log_newline 2006.196.08:19:57.21/k5log//k5ts3_log_newline 2006.196.08:19:57.89/k5log//k5ts4_log_newline 2006.196.08:19:57.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.196.08:19:57.92:4f8m12a=2 2006.196.08:19:57.92$4f8m12a/echo=on 2006.196.08:19:57.92$4f8m12a/pcalon 2006.196.08:19:57.92$pcalon/"no phase cal control is implemented here 2006.196.08:19:57.92$4f8m12a/"tpicd=stop 2006.196.08:19:57.92$4f8m12a/vc4f8 2006.196.08:19:57.92$vc4f8/valo=1,532.99 2006.196.08:19:57.92#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.196.08:19:57.92#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.196.08:19:57.92#ibcon#ireg 17 cls_cnt 0 2006.196.08:19:57.92#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.196.08:19:57.92#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.196.08:19:57.92#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.196.08:19:57.92#ibcon#enter wrdev, iclass 7, count 0 2006.196.08:19:57.92#ibcon#first serial, iclass 7, count 0 2006.196.08:19:57.92#ibcon#enter sib2, iclass 7, count 0 2006.196.08:19:57.92#ibcon#flushed, iclass 7, count 0 2006.196.08:19:57.92#ibcon#about to write, iclass 7, count 0 2006.196.08:19:57.92#ibcon#wrote, iclass 7, count 0 2006.196.08:19:57.92#ibcon#about to read 3, iclass 7, count 0 2006.196.08:19:57.96#ibcon#read 3, iclass 7, count 0 2006.196.08:19:57.96#ibcon#about to read 4, iclass 7, count 0 2006.196.08:19:57.96#ibcon#read 4, iclass 7, count 0 2006.196.08:19:57.96#ibcon#about to read 5, iclass 7, count 0 2006.196.08:19:57.96#ibcon#read 5, iclass 7, count 0 2006.196.08:19:57.96#ibcon#about to read 6, iclass 7, count 0 2006.196.08:19:57.96#ibcon#read 6, iclass 7, count 0 2006.196.08:19:57.96#ibcon#end of sib2, iclass 7, count 0 2006.196.08:19:57.96#ibcon#*mode == 0, iclass 7, count 0 2006.196.08:19:57.96#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.196.08:19:57.96#ibcon#[26=FRQ=01,532.99\r\n] 2006.196.08:19:57.96#ibcon#*before write, iclass 7, count 0 2006.196.08:19:57.96#ibcon#enter sib2, iclass 7, count 0 2006.196.08:19:57.96#ibcon#flushed, iclass 7, count 0 2006.196.08:19:57.96#ibcon#about to write, iclass 7, count 0 2006.196.08:19:57.96#ibcon#wrote, iclass 7, count 0 2006.196.08:19:57.96#ibcon#about to read 3, iclass 7, count 0 2006.196.08:19:58.01#ibcon#read 3, iclass 7, count 0 2006.196.08:19:58.01#ibcon#about to read 4, iclass 7, count 0 2006.196.08:19:58.01#ibcon#read 4, iclass 7, count 0 2006.196.08:19:58.01#ibcon#about to read 5, iclass 7, count 0 2006.196.08:19:58.01#ibcon#read 5, iclass 7, count 0 2006.196.08:19:58.01#ibcon#about to read 6, iclass 7, count 0 2006.196.08:19:58.01#ibcon#read 6, iclass 7, count 0 2006.196.08:19:58.01#ibcon#end of sib2, iclass 7, count 0 2006.196.08:19:58.01#ibcon#*after write, iclass 7, count 0 2006.196.08:19:58.01#ibcon#*before return 0, iclass 7, count 0 2006.196.08:19:58.01#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.196.08:19:58.01#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.196.08:19:58.01#ibcon#about to clear, iclass 7 cls_cnt 0 2006.196.08:19:58.01#ibcon#cleared, iclass 7 cls_cnt 0 2006.196.08:19:58.01$vc4f8/va=1,8 2006.196.08:19:58.01#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.196.08:19:58.01#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.196.08:19:58.01#ibcon#ireg 11 cls_cnt 2 2006.196.08:19:58.01#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.196.08:19:58.01#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.196.08:19:58.01#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.196.08:19:58.01#ibcon#enter wrdev, iclass 11, count 2 2006.196.08:19:58.01#ibcon#first serial, iclass 11, count 2 2006.196.08:19:58.01#ibcon#enter sib2, iclass 11, count 2 2006.196.08:19:58.01#ibcon#flushed, iclass 11, count 2 2006.196.08:19:58.01#ibcon#about to write, iclass 11, count 2 2006.196.08:19:58.01#ibcon#wrote, iclass 11, count 2 2006.196.08:19:58.01#ibcon#about to read 3, iclass 11, count 2 2006.196.08:19:58.03#ibcon#read 3, iclass 11, count 2 2006.196.08:19:58.03#ibcon#about to read 4, iclass 11, count 2 2006.196.08:19:58.03#ibcon#read 4, iclass 11, count 2 2006.196.08:19:58.03#ibcon#about to read 5, iclass 11, count 2 2006.196.08:19:58.03#ibcon#read 5, iclass 11, count 2 2006.196.08:19:58.03#ibcon#about to read 6, iclass 11, count 2 2006.196.08:19:58.03#ibcon#read 6, iclass 11, count 2 2006.196.08:19:58.03#ibcon#end of sib2, iclass 11, count 2 2006.196.08:19:58.03#ibcon#*mode == 0, iclass 11, count 2 2006.196.08:19:58.03#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.196.08:19:58.03#ibcon#[25=AT01-08\r\n] 2006.196.08:19:58.03#ibcon#*before write, iclass 11, count 2 2006.196.08:19:58.03#ibcon#enter sib2, iclass 11, count 2 2006.196.08:19:58.03#ibcon#flushed, iclass 11, count 2 2006.196.08:19:58.03#ibcon#about to write, iclass 11, count 2 2006.196.08:19:58.03#ibcon#wrote, iclass 11, count 2 2006.196.08:19:58.03#ibcon#about to read 3, iclass 11, count 2 2006.196.08:19:58.06#ibcon#read 3, iclass 11, count 2 2006.196.08:19:58.06#ibcon#about to read 4, iclass 11, count 2 2006.196.08:19:58.06#ibcon#read 4, iclass 11, count 2 2006.196.08:19:58.06#ibcon#about to read 5, iclass 11, count 2 2006.196.08:19:58.06#ibcon#read 5, iclass 11, count 2 2006.196.08:19:58.06#ibcon#about to read 6, iclass 11, count 2 2006.196.08:19:58.06#ibcon#read 6, iclass 11, count 2 2006.196.08:19:58.06#ibcon#end of sib2, iclass 11, count 2 2006.196.08:19:58.06#ibcon#*after write, iclass 11, count 2 2006.196.08:19:58.06#ibcon#*before return 0, iclass 11, count 2 2006.196.08:19:58.06#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.196.08:19:58.06#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.196.08:19:58.06#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.196.08:19:58.06#ibcon#ireg 7 cls_cnt 0 2006.196.08:19:58.06#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.196.08:19:58.18#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.196.08:19:58.18#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.196.08:19:58.18#ibcon#enter wrdev, iclass 11, count 0 2006.196.08:19:58.18#ibcon#first serial, iclass 11, count 0 2006.196.08:19:58.18#ibcon#enter sib2, iclass 11, count 0 2006.196.08:19:58.18#ibcon#flushed, iclass 11, count 0 2006.196.08:19:58.18#ibcon#about to write, iclass 11, count 0 2006.196.08:19:58.18#ibcon#wrote, iclass 11, count 0 2006.196.08:19:58.18#ibcon#about to read 3, iclass 11, count 0 2006.196.08:19:58.20#ibcon#read 3, iclass 11, count 0 2006.196.08:19:58.20#ibcon#about to read 4, iclass 11, count 0 2006.196.08:19:58.20#ibcon#read 4, iclass 11, count 0 2006.196.08:19:58.20#ibcon#about to read 5, iclass 11, count 0 2006.196.08:19:58.20#ibcon#read 5, iclass 11, count 0 2006.196.08:19:58.20#ibcon#about to read 6, iclass 11, count 0 2006.196.08:19:58.20#ibcon#read 6, iclass 11, count 0 2006.196.08:19:58.20#ibcon#end of sib2, iclass 11, count 0 2006.196.08:19:58.20#ibcon#*mode == 0, iclass 11, count 0 2006.196.08:19:58.20#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.196.08:19:58.20#ibcon#[25=USB\r\n] 2006.196.08:19:58.20#ibcon#*before write, iclass 11, count 0 2006.196.08:19:58.20#ibcon#enter sib2, iclass 11, count 0 2006.196.08:19:58.20#ibcon#flushed, iclass 11, count 0 2006.196.08:19:58.20#ibcon#about to write, iclass 11, count 0 2006.196.08:19:58.20#ibcon#wrote, iclass 11, count 0 2006.196.08:19:58.20#ibcon#about to read 3, iclass 11, count 0 2006.196.08:19:58.23#ibcon#read 3, iclass 11, count 0 2006.196.08:19:58.23#ibcon#about to read 4, iclass 11, count 0 2006.196.08:19:58.23#ibcon#read 4, iclass 11, count 0 2006.196.08:19:58.23#ibcon#about to read 5, iclass 11, count 0 2006.196.08:19:58.23#ibcon#read 5, iclass 11, count 0 2006.196.08:19:58.23#ibcon#about to read 6, iclass 11, count 0 2006.196.08:19:58.23#ibcon#read 6, iclass 11, count 0 2006.196.08:19:58.23#ibcon#end of sib2, iclass 11, count 0 2006.196.08:19:58.23#ibcon#*after write, iclass 11, count 0 2006.196.08:19:58.23#ibcon#*before return 0, iclass 11, count 0 2006.196.08:19:58.23#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.196.08:19:58.23#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.196.08:19:58.23#ibcon#about to clear, iclass 11 cls_cnt 0 2006.196.08:19:58.23#ibcon#cleared, iclass 11 cls_cnt 0 2006.196.08:19:58.23$vc4f8/valo=2,572.99 2006.196.08:19:58.23#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.196.08:19:58.23#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.196.08:19:58.23#ibcon#ireg 17 cls_cnt 0 2006.196.08:19:58.23#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.196.08:19:58.23#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.196.08:19:58.23#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.196.08:19:58.23#ibcon#enter wrdev, iclass 13, count 0 2006.196.08:19:58.23#ibcon#first serial, iclass 13, count 0 2006.196.08:19:58.23#ibcon#enter sib2, iclass 13, count 0 2006.196.08:19:58.23#ibcon#flushed, iclass 13, count 0 2006.196.08:19:58.23#ibcon#about to write, iclass 13, count 0 2006.196.08:19:58.23#ibcon#wrote, iclass 13, count 0 2006.196.08:19:58.23#ibcon#about to read 3, iclass 13, count 0 2006.196.08:19:58.25#ibcon#read 3, iclass 13, count 0 2006.196.08:19:58.25#ibcon#about to read 4, iclass 13, count 0 2006.196.08:19:58.25#ibcon#read 4, iclass 13, count 0 2006.196.08:19:58.25#ibcon#about to read 5, iclass 13, count 0 2006.196.08:19:58.25#ibcon#read 5, iclass 13, count 0 2006.196.08:19:58.25#ibcon#about to read 6, iclass 13, count 0 2006.196.08:19:58.25#ibcon#read 6, iclass 13, count 0 2006.196.08:19:58.25#ibcon#end of sib2, iclass 13, count 0 2006.196.08:19:58.25#ibcon#*mode == 0, iclass 13, count 0 2006.196.08:19:58.25#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.196.08:19:58.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.196.08:19:58.25#ibcon#*before write, iclass 13, count 0 2006.196.08:19:58.25#ibcon#enter sib2, iclass 13, count 0 2006.196.08:19:58.25#ibcon#flushed, iclass 13, count 0 2006.196.08:19:58.25#ibcon#about to write, iclass 13, count 0 2006.196.08:19:58.25#ibcon#wrote, iclass 13, count 0 2006.196.08:19:58.25#ibcon#about to read 3, iclass 13, count 0 2006.196.08:19:58.29#ibcon#read 3, iclass 13, count 0 2006.196.08:19:58.29#ibcon#about to read 4, iclass 13, count 0 2006.196.08:19:58.29#ibcon#read 4, iclass 13, count 0 2006.196.08:19:58.29#ibcon#about to read 5, iclass 13, count 0 2006.196.08:19:58.29#ibcon#read 5, iclass 13, count 0 2006.196.08:19:58.29#ibcon#about to read 6, iclass 13, count 0 2006.196.08:19:58.29#ibcon#read 6, iclass 13, count 0 2006.196.08:19:58.29#ibcon#end of sib2, iclass 13, count 0 2006.196.08:19:58.29#ibcon#*after write, iclass 13, count 0 2006.196.08:19:58.29#ibcon#*before return 0, iclass 13, count 0 2006.196.08:19:58.29#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.196.08:19:58.29#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.196.08:19:58.29#ibcon#about to clear, iclass 13 cls_cnt 0 2006.196.08:19:58.29#ibcon#cleared, iclass 13 cls_cnt 0 2006.196.08:19:58.29$vc4f8/va=2,7 2006.196.08:19:58.29#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.196.08:19:58.29#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.196.08:19:58.29#ibcon#ireg 11 cls_cnt 2 2006.196.08:19:58.29#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.196.08:19:58.35#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.196.08:19:58.35#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.196.08:19:58.35#ibcon#enter wrdev, iclass 15, count 2 2006.196.08:19:58.35#ibcon#first serial, iclass 15, count 2 2006.196.08:19:58.35#ibcon#enter sib2, iclass 15, count 2 2006.196.08:19:58.35#ibcon#flushed, iclass 15, count 2 2006.196.08:19:58.35#ibcon#about to write, iclass 15, count 2 2006.196.08:19:58.35#ibcon#wrote, iclass 15, count 2 2006.196.08:19:58.35#ibcon#about to read 3, iclass 15, count 2 2006.196.08:19:58.37#ibcon#read 3, iclass 15, count 2 2006.196.08:19:58.37#ibcon#about to read 4, iclass 15, count 2 2006.196.08:19:58.37#ibcon#read 4, iclass 15, count 2 2006.196.08:19:58.37#ibcon#about to read 5, iclass 15, count 2 2006.196.08:19:58.37#ibcon#read 5, iclass 15, count 2 2006.196.08:19:58.37#ibcon#about to read 6, iclass 15, count 2 2006.196.08:19:58.37#ibcon#read 6, iclass 15, count 2 2006.196.08:19:58.37#ibcon#end of sib2, iclass 15, count 2 2006.196.08:19:58.37#ibcon#*mode == 0, iclass 15, count 2 2006.196.08:19:58.37#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.196.08:19:58.37#ibcon#[25=AT02-07\r\n] 2006.196.08:19:58.37#ibcon#*before write, iclass 15, count 2 2006.196.08:19:58.37#ibcon#enter sib2, iclass 15, count 2 2006.196.08:19:58.37#ibcon#flushed, iclass 15, count 2 2006.196.08:19:58.37#ibcon#about to write, iclass 15, count 2 2006.196.08:19:58.37#ibcon#wrote, iclass 15, count 2 2006.196.08:19:58.37#ibcon#about to read 3, iclass 15, count 2 2006.196.08:19:58.40#ibcon#read 3, iclass 15, count 2 2006.196.08:19:58.40#ibcon#about to read 4, iclass 15, count 2 2006.196.08:19:58.40#ibcon#read 4, iclass 15, count 2 2006.196.08:19:58.40#ibcon#about to read 5, iclass 15, count 2 2006.196.08:19:58.40#ibcon#read 5, iclass 15, count 2 2006.196.08:19:58.40#ibcon#about to read 6, iclass 15, count 2 2006.196.08:19:58.40#ibcon#read 6, iclass 15, count 2 2006.196.08:19:58.40#ibcon#end of sib2, iclass 15, count 2 2006.196.08:19:58.40#ibcon#*after write, iclass 15, count 2 2006.196.08:19:58.40#ibcon#*before return 0, iclass 15, count 2 2006.196.08:19:58.40#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.196.08:19:58.40#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.196.08:19:58.40#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.196.08:19:58.40#ibcon#ireg 7 cls_cnt 0 2006.196.08:19:58.40#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.196.08:19:58.52#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.196.08:19:58.52#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.196.08:19:58.52#ibcon#enter wrdev, iclass 15, count 0 2006.196.08:19:58.52#ibcon#first serial, iclass 15, count 0 2006.196.08:19:58.52#ibcon#enter sib2, iclass 15, count 0 2006.196.08:19:58.52#ibcon#flushed, iclass 15, count 0 2006.196.08:19:58.52#ibcon#about to write, iclass 15, count 0 2006.196.08:19:58.52#ibcon#wrote, iclass 15, count 0 2006.196.08:19:58.52#ibcon#about to read 3, iclass 15, count 0 2006.196.08:19:58.54#ibcon#read 3, iclass 15, count 0 2006.196.08:19:58.54#ibcon#about to read 4, iclass 15, count 0 2006.196.08:19:58.54#ibcon#read 4, iclass 15, count 0 2006.196.08:19:58.54#ibcon#about to read 5, iclass 15, count 0 2006.196.08:19:58.54#ibcon#read 5, iclass 15, count 0 2006.196.08:19:58.54#ibcon#about to read 6, iclass 15, count 0 2006.196.08:19:58.54#ibcon#read 6, iclass 15, count 0 2006.196.08:19:58.54#ibcon#end of sib2, iclass 15, count 0 2006.196.08:19:58.54#ibcon#*mode == 0, iclass 15, count 0 2006.196.08:19:58.54#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.196.08:19:58.54#ibcon#[25=USB\r\n] 2006.196.08:19:58.54#ibcon#*before write, iclass 15, count 0 2006.196.08:19:58.54#ibcon#enter sib2, iclass 15, count 0 2006.196.08:19:58.54#ibcon#flushed, iclass 15, count 0 2006.196.08:19:58.54#ibcon#about to write, iclass 15, count 0 2006.196.08:19:58.54#ibcon#wrote, iclass 15, count 0 2006.196.08:19:58.54#ibcon#about to read 3, iclass 15, count 0 2006.196.08:19:58.57#ibcon#read 3, iclass 15, count 0 2006.196.08:19:58.57#ibcon#about to read 4, iclass 15, count 0 2006.196.08:19:58.57#ibcon#read 4, iclass 15, count 0 2006.196.08:19:58.57#ibcon#about to read 5, iclass 15, count 0 2006.196.08:19:58.57#ibcon#read 5, iclass 15, count 0 2006.196.08:19:58.57#ibcon#about to read 6, iclass 15, count 0 2006.196.08:19:58.57#ibcon#read 6, iclass 15, count 0 2006.196.08:19:58.57#ibcon#end of sib2, iclass 15, count 0 2006.196.08:19:58.57#ibcon#*after write, iclass 15, count 0 2006.196.08:19:58.57#ibcon#*before return 0, iclass 15, count 0 2006.196.08:19:58.57#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.196.08:19:58.57#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.196.08:19:58.57#ibcon#about to clear, iclass 15 cls_cnt 0 2006.196.08:19:58.57#ibcon#cleared, iclass 15 cls_cnt 0 2006.196.08:19:58.57$vc4f8/valo=3,672.99 2006.196.08:19:58.57#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.196.08:19:58.57#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.196.08:19:58.57#ibcon#ireg 17 cls_cnt 0 2006.196.08:19:58.57#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.196.08:19:58.57#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.196.08:19:58.57#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.196.08:19:58.57#ibcon#enter wrdev, iclass 17, count 0 2006.196.08:19:58.57#ibcon#first serial, iclass 17, count 0 2006.196.08:19:58.57#ibcon#enter sib2, iclass 17, count 0 2006.196.08:19:58.57#ibcon#flushed, iclass 17, count 0 2006.196.08:19:58.57#ibcon#about to write, iclass 17, count 0 2006.196.08:19:58.57#ibcon#wrote, iclass 17, count 0 2006.196.08:19:58.57#ibcon#about to read 3, iclass 17, count 0 2006.196.08:19:58.59#ibcon#read 3, iclass 17, count 0 2006.196.08:19:58.59#ibcon#about to read 4, iclass 17, count 0 2006.196.08:19:58.59#ibcon#read 4, iclass 17, count 0 2006.196.08:19:58.59#ibcon#about to read 5, iclass 17, count 0 2006.196.08:19:58.59#ibcon#read 5, iclass 17, count 0 2006.196.08:19:58.59#ibcon#about to read 6, iclass 17, count 0 2006.196.08:19:58.59#ibcon#read 6, iclass 17, count 0 2006.196.08:19:58.59#ibcon#end of sib2, iclass 17, count 0 2006.196.08:19:58.59#ibcon#*mode == 0, iclass 17, count 0 2006.196.08:19:58.59#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.196.08:19:58.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.196.08:19:58.59#ibcon#*before write, iclass 17, count 0 2006.196.08:19:58.59#ibcon#enter sib2, iclass 17, count 0 2006.196.08:19:58.59#ibcon#flushed, iclass 17, count 0 2006.196.08:19:58.59#ibcon#about to write, iclass 17, count 0 2006.196.08:19:58.59#ibcon#wrote, iclass 17, count 0 2006.196.08:19:58.59#ibcon#about to read 3, iclass 17, count 0 2006.196.08:19:58.63#ibcon#read 3, iclass 17, count 0 2006.196.08:19:58.63#ibcon#about to read 4, iclass 17, count 0 2006.196.08:19:58.63#ibcon#read 4, iclass 17, count 0 2006.196.08:19:58.63#ibcon#about to read 5, iclass 17, count 0 2006.196.08:19:58.63#ibcon#read 5, iclass 17, count 0 2006.196.08:19:58.63#ibcon#about to read 6, iclass 17, count 0 2006.196.08:19:58.63#ibcon#read 6, iclass 17, count 0 2006.196.08:19:58.63#ibcon#end of sib2, iclass 17, count 0 2006.196.08:19:58.63#ibcon#*after write, iclass 17, count 0 2006.196.08:19:58.63#ibcon#*before return 0, iclass 17, count 0 2006.196.08:19:58.63#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.196.08:19:58.63#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.196.08:19:58.63#ibcon#about to clear, iclass 17 cls_cnt 0 2006.196.08:19:58.63#ibcon#cleared, iclass 17 cls_cnt 0 2006.196.08:19:58.63$vc4f8/va=3,6 2006.196.08:19:58.63#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.196.08:19:58.63#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.196.08:19:58.63#ibcon#ireg 11 cls_cnt 2 2006.196.08:19:58.63#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.196.08:19:58.69#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.196.08:19:58.69#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.196.08:19:58.69#ibcon#enter wrdev, iclass 19, count 2 2006.196.08:19:58.69#ibcon#first serial, iclass 19, count 2 2006.196.08:19:58.69#ibcon#enter sib2, iclass 19, count 2 2006.196.08:19:58.69#ibcon#flushed, iclass 19, count 2 2006.196.08:19:58.69#ibcon#about to write, iclass 19, count 2 2006.196.08:19:58.69#ibcon#wrote, iclass 19, count 2 2006.196.08:19:58.69#ibcon#about to read 3, iclass 19, count 2 2006.196.08:19:58.71#ibcon#read 3, iclass 19, count 2 2006.196.08:19:58.71#ibcon#about to read 4, iclass 19, count 2 2006.196.08:19:58.71#ibcon#read 4, iclass 19, count 2 2006.196.08:19:58.71#ibcon#about to read 5, iclass 19, count 2 2006.196.08:19:58.71#ibcon#read 5, iclass 19, count 2 2006.196.08:19:58.71#ibcon#about to read 6, iclass 19, count 2 2006.196.08:19:58.71#ibcon#read 6, iclass 19, count 2 2006.196.08:19:58.71#ibcon#end of sib2, iclass 19, count 2 2006.196.08:19:58.71#ibcon#*mode == 0, iclass 19, count 2 2006.196.08:19:58.71#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.196.08:19:58.71#ibcon#[25=AT03-06\r\n] 2006.196.08:19:58.71#ibcon#*before write, iclass 19, count 2 2006.196.08:19:58.71#ibcon#enter sib2, iclass 19, count 2 2006.196.08:19:58.71#ibcon#flushed, iclass 19, count 2 2006.196.08:19:58.71#ibcon#about to write, iclass 19, count 2 2006.196.08:19:58.71#ibcon#wrote, iclass 19, count 2 2006.196.08:19:58.71#ibcon#about to read 3, iclass 19, count 2 2006.196.08:19:58.74#ibcon#read 3, iclass 19, count 2 2006.196.08:19:58.74#ibcon#about to read 4, iclass 19, count 2 2006.196.08:19:58.74#ibcon#read 4, iclass 19, count 2 2006.196.08:19:58.74#ibcon#about to read 5, iclass 19, count 2 2006.196.08:19:58.74#ibcon#read 5, iclass 19, count 2 2006.196.08:19:58.74#ibcon#about to read 6, iclass 19, count 2 2006.196.08:19:58.74#ibcon#read 6, iclass 19, count 2 2006.196.08:19:58.74#ibcon#end of sib2, iclass 19, count 2 2006.196.08:19:58.74#ibcon#*after write, iclass 19, count 2 2006.196.08:19:58.74#ibcon#*before return 0, iclass 19, count 2 2006.196.08:19:58.74#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.196.08:19:58.74#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.196.08:19:58.74#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.196.08:19:58.74#ibcon#ireg 7 cls_cnt 0 2006.196.08:19:58.74#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.196.08:19:58.86#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.196.08:19:58.86#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.196.08:19:58.86#ibcon#enter wrdev, iclass 19, count 0 2006.196.08:19:58.86#ibcon#first serial, iclass 19, count 0 2006.196.08:19:58.86#ibcon#enter sib2, iclass 19, count 0 2006.196.08:19:58.86#ibcon#flushed, iclass 19, count 0 2006.196.08:19:58.86#ibcon#about to write, iclass 19, count 0 2006.196.08:19:58.86#ibcon#wrote, iclass 19, count 0 2006.196.08:19:58.86#ibcon#about to read 3, iclass 19, count 0 2006.196.08:19:58.88#ibcon#read 3, iclass 19, count 0 2006.196.08:19:58.88#ibcon#about to read 4, iclass 19, count 0 2006.196.08:19:58.88#ibcon#read 4, iclass 19, count 0 2006.196.08:19:58.88#ibcon#about to read 5, iclass 19, count 0 2006.196.08:19:58.88#ibcon#read 5, iclass 19, count 0 2006.196.08:19:58.88#ibcon#about to read 6, iclass 19, count 0 2006.196.08:19:58.88#ibcon#read 6, iclass 19, count 0 2006.196.08:19:58.88#ibcon#end of sib2, iclass 19, count 0 2006.196.08:19:58.88#ibcon#*mode == 0, iclass 19, count 0 2006.196.08:19:58.88#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.196.08:19:58.88#ibcon#[25=USB\r\n] 2006.196.08:19:58.88#ibcon#*before write, iclass 19, count 0 2006.196.08:19:58.88#ibcon#enter sib2, iclass 19, count 0 2006.196.08:19:58.88#ibcon#flushed, iclass 19, count 0 2006.196.08:19:58.88#ibcon#about to write, iclass 19, count 0 2006.196.08:19:58.88#ibcon#wrote, iclass 19, count 0 2006.196.08:19:58.88#ibcon#about to read 3, iclass 19, count 0 2006.196.08:19:58.91#ibcon#read 3, iclass 19, count 0 2006.196.08:19:58.91#ibcon#about to read 4, iclass 19, count 0 2006.196.08:19:58.91#ibcon#read 4, iclass 19, count 0 2006.196.08:19:58.91#ibcon#about to read 5, iclass 19, count 0 2006.196.08:19:58.91#ibcon#read 5, iclass 19, count 0 2006.196.08:19:58.91#ibcon#about to read 6, iclass 19, count 0 2006.196.08:19:58.91#ibcon#read 6, iclass 19, count 0 2006.196.08:19:58.91#ibcon#end of sib2, iclass 19, count 0 2006.196.08:19:58.91#ibcon#*after write, iclass 19, count 0 2006.196.08:19:58.91#ibcon#*before return 0, iclass 19, count 0 2006.196.08:19:58.91#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.196.08:19:58.91#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.196.08:19:58.91#ibcon#about to clear, iclass 19 cls_cnt 0 2006.196.08:19:58.91#ibcon#cleared, iclass 19 cls_cnt 0 2006.196.08:19:58.91$vc4f8/valo=4,832.99 2006.196.08:19:58.91#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.196.08:19:58.91#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.196.08:19:58.91#ibcon#ireg 17 cls_cnt 0 2006.196.08:19:58.91#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.196.08:19:58.91#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.196.08:19:58.91#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.196.08:19:58.91#ibcon#enter wrdev, iclass 21, count 0 2006.196.08:19:58.91#ibcon#first serial, iclass 21, count 0 2006.196.08:19:58.91#ibcon#enter sib2, iclass 21, count 0 2006.196.08:19:58.91#ibcon#flushed, iclass 21, count 0 2006.196.08:19:58.91#ibcon#about to write, iclass 21, count 0 2006.196.08:19:58.91#ibcon#wrote, iclass 21, count 0 2006.196.08:19:58.91#ibcon#about to read 3, iclass 21, count 0 2006.196.08:19:58.93#ibcon#read 3, iclass 21, count 0 2006.196.08:19:58.93#ibcon#about to read 4, iclass 21, count 0 2006.196.08:19:58.93#ibcon#read 4, iclass 21, count 0 2006.196.08:19:58.93#ibcon#about to read 5, iclass 21, count 0 2006.196.08:19:58.93#ibcon#read 5, iclass 21, count 0 2006.196.08:19:58.93#ibcon#about to read 6, iclass 21, count 0 2006.196.08:19:58.93#ibcon#read 6, iclass 21, count 0 2006.196.08:19:58.93#ibcon#end of sib2, iclass 21, count 0 2006.196.08:19:58.93#ibcon#*mode == 0, iclass 21, count 0 2006.196.08:19:58.93#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.196.08:19:58.93#ibcon#[26=FRQ=04,832.99\r\n] 2006.196.08:19:58.93#ibcon#*before write, iclass 21, count 0 2006.196.08:19:58.93#ibcon#enter sib2, iclass 21, count 0 2006.196.08:19:58.93#ibcon#flushed, iclass 21, count 0 2006.196.08:19:58.93#ibcon#about to write, iclass 21, count 0 2006.196.08:19:58.93#ibcon#wrote, iclass 21, count 0 2006.196.08:19:58.93#ibcon#about to read 3, iclass 21, count 0 2006.196.08:19:58.97#ibcon#read 3, iclass 21, count 0 2006.196.08:19:58.97#ibcon#about to read 4, iclass 21, count 0 2006.196.08:19:58.97#ibcon#read 4, iclass 21, count 0 2006.196.08:19:58.97#ibcon#about to read 5, iclass 21, count 0 2006.196.08:19:58.97#ibcon#read 5, iclass 21, count 0 2006.196.08:19:58.97#ibcon#about to read 6, iclass 21, count 0 2006.196.08:19:58.97#ibcon#read 6, iclass 21, count 0 2006.196.08:19:58.97#ibcon#end of sib2, iclass 21, count 0 2006.196.08:19:58.97#ibcon#*after write, iclass 21, count 0 2006.196.08:19:58.97#ibcon#*before return 0, iclass 21, count 0 2006.196.08:19:58.97#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.196.08:19:58.97#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.196.08:19:58.97#ibcon#about to clear, iclass 21 cls_cnt 0 2006.196.08:19:58.97#ibcon#cleared, iclass 21 cls_cnt 0 2006.196.08:19:58.97$vc4f8/va=4,7 2006.196.08:19:58.97#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.196.08:19:58.97#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.196.08:19:58.97#ibcon#ireg 11 cls_cnt 2 2006.196.08:19:58.97#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.196.08:19:59.03#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.196.08:19:59.03#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.196.08:19:59.03#ibcon#enter wrdev, iclass 23, count 2 2006.196.08:19:59.03#ibcon#first serial, iclass 23, count 2 2006.196.08:19:59.03#ibcon#enter sib2, iclass 23, count 2 2006.196.08:19:59.03#ibcon#flushed, iclass 23, count 2 2006.196.08:19:59.03#ibcon#about to write, iclass 23, count 2 2006.196.08:19:59.03#ibcon#wrote, iclass 23, count 2 2006.196.08:19:59.03#ibcon#about to read 3, iclass 23, count 2 2006.196.08:19:59.05#ibcon#read 3, iclass 23, count 2 2006.196.08:19:59.05#ibcon#about to read 4, iclass 23, count 2 2006.196.08:19:59.05#ibcon#read 4, iclass 23, count 2 2006.196.08:19:59.05#ibcon#about to read 5, iclass 23, count 2 2006.196.08:19:59.05#ibcon#read 5, iclass 23, count 2 2006.196.08:19:59.05#ibcon#about to read 6, iclass 23, count 2 2006.196.08:19:59.05#ibcon#read 6, iclass 23, count 2 2006.196.08:19:59.05#ibcon#end of sib2, iclass 23, count 2 2006.196.08:19:59.05#ibcon#*mode == 0, iclass 23, count 2 2006.196.08:19:59.05#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.196.08:19:59.05#ibcon#[25=AT04-07\r\n] 2006.196.08:19:59.05#ibcon#*before write, iclass 23, count 2 2006.196.08:19:59.05#ibcon#enter sib2, iclass 23, count 2 2006.196.08:19:59.05#ibcon#flushed, iclass 23, count 2 2006.196.08:19:59.05#ibcon#about to write, iclass 23, count 2 2006.196.08:19:59.05#ibcon#wrote, iclass 23, count 2 2006.196.08:19:59.05#ibcon#about to read 3, iclass 23, count 2 2006.196.08:19:59.08#ibcon#read 3, iclass 23, count 2 2006.196.08:19:59.08#ibcon#about to read 4, iclass 23, count 2 2006.196.08:19:59.08#ibcon#read 4, iclass 23, count 2 2006.196.08:19:59.08#ibcon#about to read 5, iclass 23, count 2 2006.196.08:19:59.08#ibcon#read 5, iclass 23, count 2 2006.196.08:19:59.08#ibcon#about to read 6, iclass 23, count 2 2006.196.08:19:59.08#ibcon#read 6, iclass 23, count 2 2006.196.08:19:59.08#ibcon#end of sib2, iclass 23, count 2 2006.196.08:19:59.08#ibcon#*after write, iclass 23, count 2 2006.196.08:19:59.08#ibcon#*before return 0, iclass 23, count 2 2006.196.08:19:59.08#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.196.08:19:59.08#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.196.08:19:59.08#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.196.08:19:59.08#ibcon#ireg 7 cls_cnt 0 2006.196.08:19:59.08#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.196.08:19:59.20#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.196.08:19:59.20#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.196.08:19:59.20#ibcon#enter wrdev, iclass 23, count 0 2006.196.08:19:59.20#ibcon#first serial, iclass 23, count 0 2006.196.08:19:59.20#ibcon#enter sib2, iclass 23, count 0 2006.196.08:19:59.20#ibcon#flushed, iclass 23, count 0 2006.196.08:19:59.20#ibcon#about to write, iclass 23, count 0 2006.196.08:19:59.20#ibcon#wrote, iclass 23, count 0 2006.196.08:19:59.20#ibcon#about to read 3, iclass 23, count 0 2006.196.08:19:59.22#ibcon#read 3, iclass 23, count 0 2006.196.08:19:59.22#ibcon#about to read 4, iclass 23, count 0 2006.196.08:19:59.22#ibcon#read 4, iclass 23, count 0 2006.196.08:19:59.22#ibcon#about to read 5, iclass 23, count 0 2006.196.08:19:59.22#ibcon#read 5, iclass 23, count 0 2006.196.08:19:59.22#ibcon#about to read 6, iclass 23, count 0 2006.196.08:19:59.22#ibcon#read 6, iclass 23, count 0 2006.196.08:19:59.22#ibcon#end of sib2, iclass 23, count 0 2006.196.08:19:59.22#ibcon#*mode == 0, iclass 23, count 0 2006.196.08:19:59.22#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.196.08:19:59.22#ibcon#[25=USB\r\n] 2006.196.08:19:59.22#ibcon#*before write, iclass 23, count 0 2006.196.08:19:59.22#ibcon#enter sib2, iclass 23, count 0 2006.196.08:19:59.22#ibcon#flushed, iclass 23, count 0 2006.196.08:19:59.22#ibcon#about to write, iclass 23, count 0 2006.196.08:19:59.22#ibcon#wrote, iclass 23, count 0 2006.196.08:19:59.22#ibcon#about to read 3, iclass 23, count 0 2006.196.08:19:59.25#ibcon#read 3, iclass 23, count 0 2006.196.08:19:59.25#ibcon#about to read 4, iclass 23, count 0 2006.196.08:19:59.25#ibcon#read 4, iclass 23, count 0 2006.196.08:19:59.25#ibcon#about to read 5, iclass 23, count 0 2006.196.08:19:59.25#ibcon#read 5, iclass 23, count 0 2006.196.08:19:59.25#ibcon#about to read 6, iclass 23, count 0 2006.196.08:19:59.25#ibcon#read 6, iclass 23, count 0 2006.196.08:19:59.25#ibcon#end of sib2, iclass 23, count 0 2006.196.08:19:59.25#ibcon#*after write, iclass 23, count 0 2006.196.08:19:59.25#ibcon#*before return 0, iclass 23, count 0 2006.196.08:19:59.25#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.196.08:19:59.25#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.196.08:19:59.25#ibcon#about to clear, iclass 23 cls_cnt 0 2006.196.08:19:59.25#ibcon#cleared, iclass 23 cls_cnt 0 2006.196.08:19:59.25$vc4f8/valo=5,652.99 2006.196.08:19:59.25#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.196.08:19:59.25#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.196.08:19:59.25#ibcon#ireg 17 cls_cnt 0 2006.196.08:19:59.25#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.196.08:19:59.25#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.196.08:19:59.25#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.196.08:19:59.25#ibcon#enter wrdev, iclass 25, count 0 2006.196.08:19:59.25#ibcon#first serial, iclass 25, count 0 2006.196.08:19:59.25#ibcon#enter sib2, iclass 25, count 0 2006.196.08:19:59.25#ibcon#flushed, iclass 25, count 0 2006.196.08:19:59.25#ibcon#about to write, iclass 25, count 0 2006.196.08:19:59.25#ibcon#wrote, iclass 25, count 0 2006.196.08:19:59.25#ibcon#about to read 3, iclass 25, count 0 2006.196.08:19:59.27#ibcon#read 3, iclass 25, count 0 2006.196.08:19:59.27#ibcon#about to read 4, iclass 25, count 0 2006.196.08:19:59.27#ibcon#read 4, iclass 25, count 0 2006.196.08:19:59.27#ibcon#about to read 5, iclass 25, count 0 2006.196.08:19:59.27#ibcon#read 5, iclass 25, count 0 2006.196.08:19:59.27#ibcon#about to read 6, iclass 25, count 0 2006.196.08:19:59.27#ibcon#read 6, iclass 25, count 0 2006.196.08:19:59.27#ibcon#end of sib2, iclass 25, count 0 2006.196.08:19:59.27#ibcon#*mode == 0, iclass 25, count 0 2006.196.08:19:59.27#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.196.08:19:59.27#ibcon#[26=FRQ=05,652.99\r\n] 2006.196.08:19:59.27#ibcon#*before write, iclass 25, count 0 2006.196.08:19:59.27#ibcon#enter sib2, iclass 25, count 0 2006.196.08:19:59.27#ibcon#flushed, iclass 25, count 0 2006.196.08:19:59.27#ibcon#about to write, iclass 25, count 0 2006.196.08:19:59.27#ibcon#wrote, iclass 25, count 0 2006.196.08:19:59.27#ibcon#about to read 3, iclass 25, count 0 2006.196.08:19:59.31#ibcon#read 3, iclass 25, count 0 2006.196.08:19:59.31#ibcon#about to read 4, iclass 25, count 0 2006.196.08:19:59.31#ibcon#read 4, iclass 25, count 0 2006.196.08:19:59.31#ibcon#about to read 5, iclass 25, count 0 2006.196.08:19:59.31#ibcon#read 5, iclass 25, count 0 2006.196.08:19:59.31#ibcon#about to read 6, iclass 25, count 0 2006.196.08:19:59.31#ibcon#read 6, iclass 25, count 0 2006.196.08:19:59.31#ibcon#end of sib2, iclass 25, count 0 2006.196.08:19:59.31#ibcon#*after write, iclass 25, count 0 2006.196.08:19:59.31#ibcon#*before return 0, iclass 25, count 0 2006.196.08:19:59.31#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.196.08:19:59.31#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.196.08:19:59.31#ibcon#about to clear, iclass 25 cls_cnt 0 2006.196.08:19:59.31#ibcon#cleared, iclass 25 cls_cnt 0 2006.196.08:19:59.31$vc4f8/va=5,7 2006.196.08:19:59.31#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.196.08:19:59.31#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.196.08:19:59.31#ibcon#ireg 11 cls_cnt 2 2006.196.08:19:59.31#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.196.08:19:59.37#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.196.08:19:59.37#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.196.08:19:59.37#ibcon#enter wrdev, iclass 27, count 2 2006.196.08:19:59.37#ibcon#first serial, iclass 27, count 2 2006.196.08:19:59.37#ibcon#enter sib2, iclass 27, count 2 2006.196.08:19:59.37#ibcon#flushed, iclass 27, count 2 2006.196.08:19:59.37#ibcon#about to write, iclass 27, count 2 2006.196.08:19:59.37#ibcon#wrote, iclass 27, count 2 2006.196.08:19:59.37#ibcon#about to read 3, iclass 27, count 2 2006.196.08:19:59.39#ibcon#read 3, iclass 27, count 2 2006.196.08:19:59.39#ibcon#about to read 4, iclass 27, count 2 2006.196.08:19:59.39#ibcon#read 4, iclass 27, count 2 2006.196.08:19:59.39#ibcon#about to read 5, iclass 27, count 2 2006.196.08:19:59.39#ibcon#read 5, iclass 27, count 2 2006.196.08:19:59.39#ibcon#about to read 6, iclass 27, count 2 2006.196.08:19:59.39#ibcon#read 6, iclass 27, count 2 2006.196.08:19:59.39#ibcon#end of sib2, iclass 27, count 2 2006.196.08:19:59.39#ibcon#*mode == 0, iclass 27, count 2 2006.196.08:19:59.39#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.196.08:19:59.39#ibcon#[25=AT05-07\r\n] 2006.196.08:19:59.39#ibcon#*before write, iclass 27, count 2 2006.196.08:19:59.39#ibcon#enter sib2, iclass 27, count 2 2006.196.08:19:59.39#ibcon#flushed, iclass 27, count 2 2006.196.08:19:59.39#ibcon#about to write, iclass 27, count 2 2006.196.08:19:59.39#ibcon#wrote, iclass 27, count 2 2006.196.08:19:59.39#ibcon#about to read 3, iclass 27, count 2 2006.196.08:19:59.42#ibcon#read 3, iclass 27, count 2 2006.196.08:19:59.42#ibcon#about to read 4, iclass 27, count 2 2006.196.08:19:59.42#ibcon#read 4, iclass 27, count 2 2006.196.08:19:59.42#ibcon#about to read 5, iclass 27, count 2 2006.196.08:19:59.42#ibcon#read 5, iclass 27, count 2 2006.196.08:19:59.42#ibcon#about to read 6, iclass 27, count 2 2006.196.08:19:59.42#ibcon#read 6, iclass 27, count 2 2006.196.08:19:59.42#ibcon#end of sib2, iclass 27, count 2 2006.196.08:19:59.42#ibcon#*after write, iclass 27, count 2 2006.196.08:19:59.42#ibcon#*before return 0, iclass 27, count 2 2006.196.08:19:59.42#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.196.08:19:59.42#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.196.08:19:59.42#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.196.08:19:59.42#ibcon#ireg 7 cls_cnt 0 2006.196.08:19:59.42#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.196.08:19:59.54#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.196.08:19:59.54#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.196.08:19:59.54#ibcon#enter wrdev, iclass 27, count 0 2006.196.08:19:59.54#ibcon#first serial, iclass 27, count 0 2006.196.08:19:59.54#ibcon#enter sib2, iclass 27, count 0 2006.196.08:19:59.54#ibcon#flushed, iclass 27, count 0 2006.196.08:19:59.54#ibcon#about to write, iclass 27, count 0 2006.196.08:19:59.54#ibcon#wrote, iclass 27, count 0 2006.196.08:19:59.54#ibcon#about to read 3, iclass 27, count 0 2006.196.08:19:59.56#ibcon#read 3, iclass 27, count 0 2006.196.08:19:59.56#ibcon#about to read 4, iclass 27, count 0 2006.196.08:19:59.56#ibcon#read 4, iclass 27, count 0 2006.196.08:19:59.56#ibcon#about to read 5, iclass 27, count 0 2006.196.08:19:59.56#ibcon#read 5, iclass 27, count 0 2006.196.08:19:59.56#ibcon#about to read 6, iclass 27, count 0 2006.196.08:19:59.56#ibcon#read 6, iclass 27, count 0 2006.196.08:19:59.56#ibcon#end of sib2, iclass 27, count 0 2006.196.08:19:59.56#ibcon#*mode == 0, iclass 27, count 0 2006.196.08:19:59.56#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.196.08:19:59.56#ibcon#[25=USB\r\n] 2006.196.08:19:59.56#ibcon#*before write, iclass 27, count 0 2006.196.08:19:59.56#ibcon#enter sib2, iclass 27, count 0 2006.196.08:19:59.56#ibcon#flushed, iclass 27, count 0 2006.196.08:19:59.56#ibcon#about to write, iclass 27, count 0 2006.196.08:19:59.56#ibcon#wrote, iclass 27, count 0 2006.196.08:19:59.56#ibcon#about to read 3, iclass 27, count 0 2006.196.08:19:59.59#ibcon#read 3, iclass 27, count 0 2006.196.08:19:59.59#ibcon#about to read 4, iclass 27, count 0 2006.196.08:19:59.59#ibcon#read 4, iclass 27, count 0 2006.196.08:19:59.59#ibcon#about to read 5, iclass 27, count 0 2006.196.08:19:59.59#ibcon#read 5, iclass 27, count 0 2006.196.08:19:59.59#ibcon#about to read 6, iclass 27, count 0 2006.196.08:19:59.59#ibcon#read 6, iclass 27, count 0 2006.196.08:19:59.59#ibcon#end of sib2, iclass 27, count 0 2006.196.08:19:59.59#ibcon#*after write, iclass 27, count 0 2006.196.08:19:59.59#ibcon#*before return 0, iclass 27, count 0 2006.196.08:19:59.59#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.196.08:19:59.59#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.196.08:19:59.59#ibcon#about to clear, iclass 27 cls_cnt 0 2006.196.08:19:59.59#ibcon#cleared, iclass 27 cls_cnt 0 2006.196.08:19:59.59$vc4f8/valo=6,772.99 2006.196.08:19:59.59#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.196.08:19:59.59#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.196.08:19:59.59#ibcon#ireg 17 cls_cnt 0 2006.196.08:19:59.59#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.196.08:19:59.59#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.196.08:19:59.59#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.196.08:19:59.59#ibcon#enter wrdev, iclass 29, count 0 2006.196.08:19:59.59#ibcon#first serial, iclass 29, count 0 2006.196.08:19:59.59#ibcon#enter sib2, iclass 29, count 0 2006.196.08:19:59.59#ibcon#flushed, iclass 29, count 0 2006.196.08:19:59.59#ibcon#about to write, iclass 29, count 0 2006.196.08:19:59.59#ibcon#wrote, iclass 29, count 0 2006.196.08:19:59.59#ibcon#about to read 3, iclass 29, count 0 2006.196.08:19:59.61#ibcon#read 3, iclass 29, count 0 2006.196.08:19:59.61#ibcon#about to read 4, iclass 29, count 0 2006.196.08:19:59.61#ibcon#read 4, iclass 29, count 0 2006.196.08:19:59.61#ibcon#about to read 5, iclass 29, count 0 2006.196.08:19:59.61#ibcon#read 5, iclass 29, count 0 2006.196.08:19:59.61#ibcon#about to read 6, iclass 29, count 0 2006.196.08:19:59.61#ibcon#read 6, iclass 29, count 0 2006.196.08:19:59.61#ibcon#end of sib2, iclass 29, count 0 2006.196.08:19:59.61#ibcon#*mode == 0, iclass 29, count 0 2006.196.08:19:59.61#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.196.08:19:59.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.196.08:19:59.61#ibcon#*before write, iclass 29, count 0 2006.196.08:19:59.61#ibcon#enter sib2, iclass 29, count 0 2006.196.08:19:59.61#ibcon#flushed, iclass 29, count 0 2006.196.08:19:59.61#ibcon#about to write, iclass 29, count 0 2006.196.08:19:59.61#ibcon#wrote, iclass 29, count 0 2006.196.08:19:59.61#ibcon#about to read 3, iclass 29, count 0 2006.196.08:19:59.66#ibcon#read 3, iclass 29, count 0 2006.196.08:19:59.66#ibcon#about to read 4, iclass 29, count 0 2006.196.08:19:59.66#ibcon#read 4, iclass 29, count 0 2006.196.08:19:59.66#ibcon#about to read 5, iclass 29, count 0 2006.196.08:19:59.66#ibcon#read 5, iclass 29, count 0 2006.196.08:19:59.66#ibcon#about to read 6, iclass 29, count 0 2006.196.08:19:59.66#ibcon#read 6, iclass 29, count 0 2006.196.08:19:59.66#ibcon#end of sib2, iclass 29, count 0 2006.196.08:19:59.66#ibcon#*after write, iclass 29, count 0 2006.196.08:19:59.66#ibcon#*before return 0, iclass 29, count 0 2006.196.08:19:59.66#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.196.08:19:59.66#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.196.08:19:59.66#ibcon#about to clear, iclass 29 cls_cnt 0 2006.196.08:19:59.66#ibcon#cleared, iclass 29 cls_cnt 0 2006.196.08:19:59.66$vc4f8/va=6,6 2006.196.08:19:59.66#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.196.08:19:59.66#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.196.08:19:59.66#ibcon#ireg 11 cls_cnt 2 2006.196.08:19:59.66#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.196.08:19:59.71#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.196.08:19:59.71#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.196.08:19:59.71#ibcon#enter wrdev, iclass 31, count 2 2006.196.08:19:59.71#ibcon#first serial, iclass 31, count 2 2006.196.08:19:59.71#ibcon#enter sib2, iclass 31, count 2 2006.196.08:19:59.71#ibcon#flushed, iclass 31, count 2 2006.196.08:19:59.71#ibcon#about to write, iclass 31, count 2 2006.196.08:19:59.71#ibcon#wrote, iclass 31, count 2 2006.196.08:19:59.71#ibcon#about to read 3, iclass 31, count 2 2006.196.08:19:59.73#ibcon#read 3, iclass 31, count 2 2006.196.08:19:59.73#ibcon#about to read 4, iclass 31, count 2 2006.196.08:19:59.73#ibcon#read 4, iclass 31, count 2 2006.196.08:19:59.73#ibcon#about to read 5, iclass 31, count 2 2006.196.08:19:59.73#ibcon#read 5, iclass 31, count 2 2006.196.08:19:59.73#ibcon#about to read 6, iclass 31, count 2 2006.196.08:19:59.73#ibcon#read 6, iclass 31, count 2 2006.196.08:19:59.73#ibcon#end of sib2, iclass 31, count 2 2006.196.08:19:59.73#ibcon#*mode == 0, iclass 31, count 2 2006.196.08:19:59.73#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.196.08:19:59.73#ibcon#[25=AT06-06\r\n] 2006.196.08:19:59.73#ibcon#*before write, iclass 31, count 2 2006.196.08:19:59.73#ibcon#enter sib2, iclass 31, count 2 2006.196.08:19:59.73#ibcon#flushed, iclass 31, count 2 2006.196.08:19:59.73#ibcon#about to write, iclass 31, count 2 2006.196.08:19:59.73#ibcon#wrote, iclass 31, count 2 2006.196.08:19:59.73#ibcon#about to read 3, iclass 31, count 2 2006.196.08:19:59.76#ibcon#read 3, iclass 31, count 2 2006.196.08:19:59.76#ibcon#about to read 4, iclass 31, count 2 2006.196.08:19:59.76#ibcon#read 4, iclass 31, count 2 2006.196.08:19:59.76#ibcon#about to read 5, iclass 31, count 2 2006.196.08:19:59.76#ibcon#read 5, iclass 31, count 2 2006.196.08:19:59.76#ibcon#about to read 6, iclass 31, count 2 2006.196.08:19:59.76#ibcon#read 6, iclass 31, count 2 2006.196.08:19:59.76#ibcon#end of sib2, iclass 31, count 2 2006.196.08:19:59.76#ibcon#*after write, iclass 31, count 2 2006.196.08:19:59.76#ibcon#*before return 0, iclass 31, count 2 2006.196.08:19:59.76#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.196.08:19:59.76#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.196.08:19:59.76#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.196.08:19:59.76#ibcon#ireg 7 cls_cnt 0 2006.196.08:19:59.76#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.196.08:19:59.88#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.196.08:19:59.88#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.196.08:19:59.88#ibcon#enter wrdev, iclass 31, count 0 2006.196.08:19:59.88#ibcon#first serial, iclass 31, count 0 2006.196.08:19:59.88#ibcon#enter sib2, iclass 31, count 0 2006.196.08:19:59.88#ibcon#flushed, iclass 31, count 0 2006.196.08:19:59.88#ibcon#about to write, iclass 31, count 0 2006.196.08:19:59.88#ibcon#wrote, iclass 31, count 0 2006.196.08:19:59.88#ibcon#about to read 3, iclass 31, count 0 2006.196.08:19:59.90#ibcon#read 3, iclass 31, count 0 2006.196.08:19:59.90#ibcon#about to read 4, iclass 31, count 0 2006.196.08:19:59.90#ibcon#read 4, iclass 31, count 0 2006.196.08:19:59.90#ibcon#about to read 5, iclass 31, count 0 2006.196.08:19:59.90#ibcon#read 5, iclass 31, count 0 2006.196.08:19:59.90#ibcon#about to read 6, iclass 31, count 0 2006.196.08:19:59.90#ibcon#read 6, iclass 31, count 0 2006.196.08:19:59.90#ibcon#end of sib2, iclass 31, count 0 2006.196.08:19:59.90#ibcon#*mode == 0, iclass 31, count 0 2006.196.08:19:59.90#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.196.08:19:59.90#ibcon#[25=USB\r\n] 2006.196.08:19:59.90#ibcon#*before write, iclass 31, count 0 2006.196.08:19:59.90#ibcon#enter sib2, iclass 31, count 0 2006.196.08:19:59.90#ibcon#flushed, iclass 31, count 0 2006.196.08:19:59.90#ibcon#about to write, iclass 31, count 0 2006.196.08:19:59.90#ibcon#wrote, iclass 31, count 0 2006.196.08:19:59.90#ibcon#about to read 3, iclass 31, count 0 2006.196.08:19:59.93#ibcon#read 3, iclass 31, count 0 2006.196.08:19:59.93#ibcon#about to read 4, iclass 31, count 0 2006.196.08:19:59.93#ibcon#read 4, iclass 31, count 0 2006.196.08:19:59.93#ibcon#about to read 5, iclass 31, count 0 2006.196.08:19:59.93#ibcon#read 5, iclass 31, count 0 2006.196.08:19:59.93#ibcon#about to read 6, iclass 31, count 0 2006.196.08:19:59.93#ibcon#read 6, iclass 31, count 0 2006.196.08:19:59.93#ibcon#end of sib2, iclass 31, count 0 2006.196.08:19:59.93#ibcon#*after write, iclass 31, count 0 2006.196.08:19:59.93#ibcon#*before return 0, iclass 31, count 0 2006.196.08:19:59.93#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.196.08:19:59.93#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.196.08:19:59.93#ibcon#about to clear, iclass 31 cls_cnt 0 2006.196.08:19:59.93#ibcon#cleared, iclass 31 cls_cnt 0 2006.196.08:19:59.93$vc4f8/valo=7,832.99 2006.196.08:19:59.93#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.196.08:19:59.93#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.196.08:19:59.93#ibcon#ireg 17 cls_cnt 0 2006.196.08:19:59.93#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:19:59.93#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:19:59.93#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:19:59.93#ibcon#enter wrdev, iclass 33, count 0 2006.196.08:19:59.93#ibcon#first serial, iclass 33, count 0 2006.196.08:19:59.93#ibcon#enter sib2, iclass 33, count 0 2006.196.08:19:59.93#ibcon#flushed, iclass 33, count 0 2006.196.08:19:59.93#ibcon#about to write, iclass 33, count 0 2006.196.08:19:59.93#ibcon#wrote, iclass 33, count 0 2006.196.08:19:59.93#ibcon#about to read 3, iclass 33, count 0 2006.196.08:19:59.95#ibcon#read 3, iclass 33, count 0 2006.196.08:19:59.95#ibcon#about to read 4, iclass 33, count 0 2006.196.08:19:59.95#ibcon#read 4, iclass 33, count 0 2006.196.08:19:59.95#ibcon#about to read 5, iclass 33, count 0 2006.196.08:19:59.95#ibcon#read 5, iclass 33, count 0 2006.196.08:19:59.95#ibcon#about to read 6, iclass 33, count 0 2006.196.08:19:59.95#ibcon#read 6, iclass 33, count 0 2006.196.08:19:59.95#ibcon#end of sib2, iclass 33, count 0 2006.196.08:19:59.95#ibcon#*mode == 0, iclass 33, count 0 2006.196.08:19:59.95#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.196.08:19:59.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.196.08:19:59.95#ibcon#*before write, iclass 33, count 0 2006.196.08:19:59.95#ibcon#enter sib2, iclass 33, count 0 2006.196.08:19:59.95#ibcon#flushed, iclass 33, count 0 2006.196.08:19:59.95#ibcon#about to write, iclass 33, count 0 2006.196.08:19:59.95#ibcon#wrote, iclass 33, count 0 2006.196.08:19:59.95#ibcon#about to read 3, iclass 33, count 0 2006.196.08:19:59.99#ibcon#read 3, iclass 33, count 0 2006.196.08:19:59.99#ibcon#about to read 4, iclass 33, count 0 2006.196.08:19:59.99#ibcon#read 4, iclass 33, count 0 2006.196.08:19:59.99#ibcon#about to read 5, iclass 33, count 0 2006.196.08:19:59.99#ibcon#read 5, iclass 33, count 0 2006.196.08:19:59.99#ibcon#about to read 6, iclass 33, count 0 2006.196.08:19:59.99#ibcon#read 6, iclass 33, count 0 2006.196.08:19:59.99#ibcon#end of sib2, iclass 33, count 0 2006.196.08:19:59.99#ibcon#*after write, iclass 33, count 0 2006.196.08:19:59.99#ibcon#*before return 0, iclass 33, count 0 2006.196.08:19:59.99#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:19:59.99#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:19:59.99#ibcon#about to clear, iclass 33 cls_cnt 0 2006.196.08:19:59.99#ibcon#cleared, iclass 33 cls_cnt 0 2006.196.08:19:59.99$vc4f8/va=7,6 2006.196.08:19:59.99#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.196.08:19:59.99#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.196.08:19:59.99#ibcon#ireg 11 cls_cnt 2 2006.196.08:19:59.99#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.196.08:20:00.05#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.196.08:20:00.05#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.196.08:20:00.05#ibcon#enter wrdev, iclass 35, count 2 2006.196.08:20:00.05#ibcon#first serial, iclass 35, count 2 2006.196.08:20:00.05#ibcon#enter sib2, iclass 35, count 2 2006.196.08:20:00.05#ibcon#flushed, iclass 35, count 2 2006.196.08:20:00.05#ibcon#about to write, iclass 35, count 2 2006.196.08:20:00.05#ibcon#wrote, iclass 35, count 2 2006.196.08:20:00.05#ibcon#about to read 3, iclass 35, count 2 2006.196.08:20:00.07#ibcon#read 3, iclass 35, count 2 2006.196.08:20:00.07#ibcon#about to read 4, iclass 35, count 2 2006.196.08:20:00.07#ibcon#read 4, iclass 35, count 2 2006.196.08:20:00.07#ibcon#about to read 5, iclass 35, count 2 2006.196.08:20:00.07#ibcon#read 5, iclass 35, count 2 2006.196.08:20:00.07#ibcon#about to read 6, iclass 35, count 2 2006.196.08:20:00.07#ibcon#read 6, iclass 35, count 2 2006.196.08:20:00.07#ibcon#end of sib2, iclass 35, count 2 2006.196.08:20:00.07#ibcon#*mode == 0, iclass 35, count 2 2006.196.08:20:00.07#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.196.08:20:00.07#ibcon#[25=AT07-06\r\n] 2006.196.08:20:00.07#ibcon#*before write, iclass 35, count 2 2006.196.08:20:00.07#ibcon#enter sib2, iclass 35, count 2 2006.196.08:20:00.07#ibcon#flushed, iclass 35, count 2 2006.196.08:20:00.07#ibcon#about to write, iclass 35, count 2 2006.196.08:20:00.07#ibcon#wrote, iclass 35, count 2 2006.196.08:20:00.07#ibcon#about to read 3, iclass 35, count 2 2006.196.08:20:00.10#ibcon#read 3, iclass 35, count 2 2006.196.08:20:00.10#ibcon#about to read 4, iclass 35, count 2 2006.196.08:20:00.10#ibcon#read 4, iclass 35, count 2 2006.196.08:20:00.10#ibcon#about to read 5, iclass 35, count 2 2006.196.08:20:00.10#ibcon#read 5, iclass 35, count 2 2006.196.08:20:00.10#ibcon#about to read 6, iclass 35, count 2 2006.196.08:20:00.10#ibcon#read 6, iclass 35, count 2 2006.196.08:20:00.10#ibcon#end of sib2, iclass 35, count 2 2006.196.08:20:00.10#ibcon#*after write, iclass 35, count 2 2006.196.08:20:00.10#ibcon#*before return 0, iclass 35, count 2 2006.196.08:20:00.10#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.196.08:20:00.10#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.196.08:20:00.10#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.196.08:20:00.10#ibcon#ireg 7 cls_cnt 0 2006.196.08:20:00.10#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.196.08:20:00.22#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.196.08:20:00.22#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.196.08:20:00.22#ibcon#enter wrdev, iclass 35, count 0 2006.196.08:20:00.22#ibcon#first serial, iclass 35, count 0 2006.196.08:20:00.22#ibcon#enter sib2, iclass 35, count 0 2006.196.08:20:00.22#ibcon#flushed, iclass 35, count 0 2006.196.08:20:00.22#ibcon#about to write, iclass 35, count 0 2006.196.08:20:00.22#ibcon#wrote, iclass 35, count 0 2006.196.08:20:00.22#ibcon#about to read 3, iclass 35, count 0 2006.196.08:20:00.24#ibcon#read 3, iclass 35, count 0 2006.196.08:20:00.24#ibcon#about to read 4, iclass 35, count 0 2006.196.08:20:00.24#ibcon#read 4, iclass 35, count 0 2006.196.08:20:00.24#ibcon#about to read 5, iclass 35, count 0 2006.196.08:20:00.24#ibcon#read 5, iclass 35, count 0 2006.196.08:20:00.24#ibcon#about to read 6, iclass 35, count 0 2006.196.08:20:00.24#ibcon#read 6, iclass 35, count 0 2006.196.08:20:00.24#ibcon#end of sib2, iclass 35, count 0 2006.196.08:20:00.24#ibcon#*mode == 0, iclass 35, count 0 2006.196.08:20:00.24#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.196.08:20:00.24#ibcon#[25=USB\r\n] 2006.196.08:20:00.24#ibcon#*before write, iclass 35, count 0 2006.196.08:20:00.24#ibcon#enter sib2, iclass 35, count 0 2006.196.08:20:00.24#ibcon#flushed, iclass 35, count 0 2006.196.08:20:00.24#ibcon#about to write, iclass 35, count 0 2006.196.08:20:00.24#ibcon#wrote, iclass 35, count 0 2006.196.08:20:00.24#ibcon#about to read 3, iclass 35, count 0 2006.196.08:20:00.27#ibcon#read 3, iclass 35, count 0 2006.196.08:20:00.27#ibcon#about to read 4, iclass 35, count 0 2006.196.08:20:00.27#ibcon#read 4, iclass 35, count 0 2006.196.08:20:00.27#ibcon#about to read 5, iclass 35, count 0 2006.196.08:20:00.27#ibcon#read 5, iclass 35, count 0 2006.196.08:20:00.27#ibcon#about to read 6, iclass 35, count 0 2006.196.08:20:00.27#ibcon#read 6, iclass 35, count 0 2006.196.08:20:00.27#ibcon#end of sib2, iclass 35, count 0 2006.196.08:20:00.27#ibcon#*after write, iclass 35, count 0 2006.196.08:20:00.27#ibcon#*before return 0, iclass 35, count 0 2006.196.08:20:00.27#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.196.08:20:00.27#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.196.08:20:00.27#ibcon#about to clear, iclass 35 cls_cnt 0 2006.196.08:20:00.27#ibcon#cleared, iclass 35 cls_cnt 0 2006.196.08:20:00.27$vc4f8/valo=8,852.99 2006.196.08:20:00.27#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.196.08:20:00.27#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.196.08:20:00.27#ibcon#ireg 17 cls_cnt 0 2006.196.08:20:00.27#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.196.08:20:00.27#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.196.08:20:00.27#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.196.08:20:00.27#ibcon#enter wrdev, iclass 37, count 0 2006.196.08:20:00.27#ibcon#first serial, iclass 37, count 0 2006.196.08:20:00.27#ibcon#enter sib2, iclass 37, count 0 2006.196.08:20:00.27#ibcon#flushed, iclass 37, count 0 2006.196.08:20:00.27#ibcon#about to write, iclass 37, count 0 2006.196.08:20:00.27#ibcon#wrote, iclass 37, count 0 2006.196.08:20:00.27#ibcon#about to read 3, iclass 37, count 0 2006.196.08:20:00.29#ibcon#read 3, iclass 37, count 0 2006.196.08:20:00.29#ibcon#about to read 4, iclass 37, count 0 2006.196.08:20:00.29#ibcon#read 4, iclass 37, count 0 2006.196.08:20:00.29#ibcon#about to read 5, iclass 37, count 0 2006.196.08:20:00.29#ibcon#read 5, iclass 37, count 0 2006.196.08:20:00.29#ibcon#about to read 6, iclass 37, count 0 2006.196.08:20:00.29#ibcon#read 6, iclass 37, count 0 2006.196.08:20:00.29#ibcon#end of sib2, iclass 37, count 0 2006.196.08:20:00.29#ibcon#*mode == 0, iclass 37, count 0 2006.196.08:20:00.29#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.196.08:20:00.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.196.08:20:00.29#ibcon#*before write, iclass 37, count 0 2006.196.08:20:00.29#ibcon#enter sib2, iclass 37, count 0 2006.196.08:20:00.29#ibcon#flushed, iclass 37, count 0 2006.196.08:20:00.29#ibcon#about to write, iclass 37, count 0 2006.196.08:20:00.29#ibcon#wrote, iclass 37, count 0 2006.196.08:20:00.29#ibcon#about to read 3, iclass 37, count 0 2006.196.08:20:00.33#ibcon#read 3, iclass 37, count 0 2006.196.08:20:00.33#ibcon#about to read 4, iclass 37, count 0 2006.196.08:20:00.33#ibcon#read 4, iclass 37, count 0 2006.196.08:20:00.33#ibcon#about to read 5, iclass 37, count 0 2006.196.08:20:00.33#ibcon#read 5, iclass 37, count 0 2006.196.08:20:00.33#ibcon#about to read 6, iclass 37, count 0 2006.196.08:20:00.33#ibcon#read 6, iclass 37, count 0 2006.196.08:20:00.33#ibcon#end of sib2, iclass 37, count 0 2006.196.08:20:00.33#ibcon#*after write, iclass 37, count 0 2006.196.08:20:00.33#ibcon#*before return 0, iclass 37, count 0 2006.196.08:20:00.33#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.196.08:20:00.33#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.196.08:20:00.33#ibcon#about to clear, iclass 37 cls_cnt 0 2006.196.08:20:00.33#ibcon#cleared, iclass 37 cls_cnt 0 2006.196.08:20:00.33$vc4f8/va=8,7 2006.196.08:20:00.33#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.196.08:20:00.33#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.196.08:20:00.33#ibcon#ireg 11 cls_cnt 2 2006.196.08:20:00.33#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.196.08:20:00.39#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.196.08:20:00.39#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.196.08:20:00.39#ibcon#enter wrdev, iclass 39, count 2 2006.196.08:20:00.39#ibcon#first serial, iclass 39, count 2 2006.196.08:20:00.39#ibcon#enter sib2, iclass 39, count 2 2006.196.08:20:00.39#ibcon#flushed, iclass 39, count 2 2006.196.08:20:00.39#ibcon#about to write, iclass 39, count 2 2006.196.08:20:00.39#ibcon#wrote, iclass 39, count 2 2006.196.08:20:00.39#ibcon#about to read 3, iclass 39, count 2 2006.196.08:20:00.41#ibcon#read 3, iclass 39, count 2 2006.196.08:20:00.41#ibcon#about to read 4, iclass 39, count 2 2006.196.08:20:00.41#ibcon#read 4, iclass 39, count 2 2006.196.08:20:00.41#ibcon#about to read 5, iclass 39, count 2 2006.196.08:20:00.41#ibcon#read 5, iclass 39, count 2 2006.196.08:20:00.41#ibcon#about to read 6, iclass 39, count 2 2006.196.08:20:00.41#ibcon#read 6, iclass 39, count 2 2006.196.08:20:00.41#ibcon#end of sib2, iclass 39, count 2 2006.196.08:20:00.41#ibcon#*mode == 0, iclass 39, count 2 2006.196.08:20:00.41#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.196.08:20:00.41#ibcon#[25=AT08-07\r\n] 2006.196.08:20:00.41#ibcon#*before write, iclass 39, count 2 2006.196.08:20:00.41#ibcon#enter sib2, iclass 39, count 2 2006.196.08:20:00.41#ibcon#flushed, iclass 39, count 2 2006.196.08:20:00.41#ibcon#about to write, iclass 39, count 2 2006.196.08:20:00.41#ibcon#wrote, iclass 39, count 2 2006.196.08:20:00.41#ibcon#about to read 3, iclass 39, count 2 2006.196.08:20:00.44#ibcon#read 3, iclass 39, count 2 2006.196.08:20:00.44#ibcon#about to read 4, iclass 39, count 2 2006.196.08:20:00.44#ibcon#read 4, iclass 39, count 2 2006.196.08:20:00.44#ibcon#about to read 5, iclass 39, count 2 2006.196.08:20:00.44#ibcon#read 5, iclass 39, count 2 2006.196.08:20:00.44#ibcon#about to read 6, iclass 39, count 2 2006.196.08:20:00.44#ibcon#read 6, iclass 39, count 2 2006.196.08:20:00.44#ibcon#end of sib2, iclass 39, count 2 2006.196.08:20:00.44#ibcon#*after write, iclass 39, count 2 2006.196.08:20:00.44#ibcon#*before return 0, iclass 39, count 2 2006.196.08:20:00.44#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.196.08:20:00.44#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.196.08:20:00.44#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.196.08:20:00.44#ibcon#ireg 7 cls_cnt 0 2006.196.08:20:00.44#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.196.08:20:00.56#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.196.08:20:00.56#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.196.08:20:00.56#ibcon#enter wrdev, iclass 39, count 0 2006.196.08:20:00.56#ibcon#first serial, iclass 39, count 0 2006.196.08:20:00.56#ibcon#enter sib2, iclass 39, count 0 2006.196.08:20:00.56#ibcon#flushed, iclass 39, count 0 2006.196.08:20:00.56#ibcon#about to write, iclass 39, count 0 2006.196.08:20:00.56#ibcon#wrote, iclass 39, count 0 2006.196.08:20:00.56#ibcon#about to read 3, iclass 39, count 0 2006.196.08:20:00.58#ibcon#read 3, iclass 39, count 0 2006.196.08:20:00.58#ibcon#about to read 4, iclass 39, count 0 2006.196.08:20:00.58#ibcon#read 4, iclass 39, count 0 2006.196.08:20:00.58#ibcon#about to read 5, iclass 39, count 0 2006.196.08:20:00.58#ibcon#read 5, iclass 39, count 0 2006.196.08:20:00.58#ibcon#about to read 6, iclass 39, count 0 2006.196.08:20:00.58#ibcon#read 6, iclass 39, count 0 2006.196.08:20:00.58#ibcon#end of sib2, iclass 39, count 0 2006.196.08:20:00.58#ibcon#*mode == 0, iclass 39, count 0 2006.196.08:20:00.58#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.196.08:20:00.58#ibcon#[25=USB\r\n] 2006.196.08:20:00.58#ibcon#*before write, iclass 39, count 0 2006.196.08:20:00.58#ibcon#enter sib2, iclass 39, count 0 2006.196.08:20:00.58#ibcon#flushed, iclass 39, count 0 2006.196.08:20:00.58#ibcon#about to write, iclass 39, count 0 2006.196.08:20:00.58#ibcon#wrote, iclass 39, count 0 2006.196.08:20:00.58#ibcon#about to read 3, iclass 39, count 0 2006.196.08:20:00.61#ibcon#read 3, iclass 39, count 0 2006.196.08:20:00.61#ibcon#about to read 4, iclass 39, count 0 2006.196.08:20:00.61#ibcon#read 4, iclass 39, count 0 2006.196.08:20:00.61#ibcon#about to read 5, iclass 39, count 0 2006.196.08:20:00.61#ibcon#read 5, iclass 39, count 0 2006.196.08:20:00.61#ibcon#about to read 6, iclass 39, count 0 2006.196.08:20:00.61#ibcon#read 6, iclass 39, count 0 2006.196.08:20:00.61#ibcon#end of sib2, iclass 39, count 0 2006.196.08:20:00.61#ibcon#*after write, iclass 39, count 0 2006.196.08:20:00.61#ibcon#*before return 0, iclass 39, count 0 2006.196.08:20:00.61#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.196.08:20:00.61#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.196.08:20:00.61#ibcon#about to clear, iclass 39 cls_cnt 0 2006.196.08:20:00.61#ibcon#cleared, iclass 39 cls_cnt 0 2006.196.08:20:00.61$vc4f8/vblo=1,632.99 2006.196.08:20:00.61#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.196.08:20:00.61#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.196.08:20:00.61#ibcon#ireg 17 cls_cnt 0 2006.196.08:20:00.61#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.196.08:20:00.61#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.196.08:20:00.61#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.196.08:20:00.61#ibcon#enter wrdev, iclass 3, count 0 2006.196.08:20:00.61#ibcon#first serial, iclass 3, count 0 2006.196.08:20:00.61#ibcon#enter sib2, iclass 3, count 0 2006.196.08:20:00.61#ibcon#flushed, iclass 3, count 0 2006.196.08:20:00.61#ibcon#about to write, iclass 3, count 0 2006.196.08:20:00.61#ibcon#wrote, iclass 3, count 0 2006.196.08:20:00.61#ibcon#about to read 3, iclass 3, count 0 2006.196.08:20:00.63#ibcon#read 3, iclass 3, count 0 2006.196.08:20:00.63#ibcon#about to read 4, iclass 3, count 0 2006.196.08:20:00.63#ibcon#read 4, iclass 3, count 0 2006.196.08:20:00.63#ibcon#about to read 5, iclass 3, count 0 2006.196.08:20:00.63#ibcon#read 5, iclass 3, count 0 2006.196.08:20:00.63#ibcon#about to read 6, iclass 3, count 0 2006.196.08:20:00.63#ibcon#read 6, iclass 3, count 0 2006.196.08:20:00.63#ibcon#end of sib2, iclass 3, count 0 2006.196.08:20:00.63#ibcon#*mode == 0, iclass 3, count 0 2006.196.08:20:00.63#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.196.08:20:00.63#ibcon#[28=FRQ=01,632.99\r\n] 2006.196.08:20:00.63#ibcon#*before write, iclass 3, count 0 2006.196.08:20:00.63#ibcon#enter sib2, iclass 3, count 0 2006.196.08:20:00.63#ibcon#flushed, iclass 3, count 0 2006.196.08:20:00.63#ibcon#about to write, iclass 3, count 0 2006.196.08:20:00.63#ibcon#wrote, iclass 3, count 0 2006.196.08:20:00.63#ibcon#about to read 3, iclass 3, count 0 2006.196.08:20:00.67#ibcon#read 3, iclass 3, count 0 2006.196.08:20:00.67#ibcon#about to read 4, iclass 3, count 0 2006.196.08:20:00.67#ibcon#read 4, iclass 3, count 0 2006.196.08:20:00.67#ibcon#about to read 5, iclass 3, count 0 2006.196.08:20:00.67#ibcon#read 5, iclass 3, count 0 2006.196.08:20:00.67#ibcon#about to read 6, iclass 3, count 0 2006.196.08:20:00.67#ibcon#read 6, iclass 3, count 0 2006.196.08:20:00.67#ibcon#end of sib2, iclass 3, count 0 2006.196.08:20:00.67#ibcon#*after write, iclass 3, count 0 2006.196.08:20:00.67#ibcon#*before return 0, iclass 3, count 0 2006.196.08:20:00.67#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.196.08:20:00.67#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.196.08:20:00.67#ibcon#about to clear, iclass 3 cls_cnt 0 2006.196.08:20:00.67#ibcon#cleared, iclass 3 cls_cnt 0 2006.196.08:20:00.67$vc4f8/vb=1,4 2006.196.08:20:00.67#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.196.08:20:00.67#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.196.08:20:00.67#ibcon#ireg 11 cls_cnt 2 2006.196.08:20:00.67#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.196.08:20:00.67#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.196.08:20:00.67#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.196.08:20:00.67#ibcon#enter wrdev, iclass 5, count 2 2006.196.08:20:00.67#ibcon#first serial, iclass 5, count 2 2006.196.08:20:00.67#ibcon#enter sib2, iclass 5, count 2 2006.196.08:20:00.67#ibcon#flushed, iclass 5, count 2 2006.196.08:20:00.67#ibcon#about to write, iclass 5, count 2 2006.196.08:20:00.67#ibcon#wrote, iclass 5, count 2 2006.196.08:20:00.67#ibcon#about to read 3, iclass 5, count 2 2006.196.08:20:00.69#ibcon#read 3, iclass 5, count 2 2006.196.08:20:00.69#ibcon#about to read 4, iclass 5, count 2 2006.196.08:20:00.69#ibcon#read 4, iclass 5, count 2 2006.196.08:20:00.69#ibcon#about to read 5, iclass 5, count 2 2006.196.08:20:00.69#ibcon#read 5, iclass 5, count 2 2006.196.08:20:00.69#ibcon#about to read 6, iclass 5, count 2 2006.196.08:20:00.69#ibcon#read 6, iclass 5, count 2 2006.196.08:20:00.69#ibcon#end of sib2, iclass 5, count 2 2006.196.08:20:00.69#ibcon#*mode == 0, iclass 5, count 2 2006.196.08:20:00.69#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.196.08:20:00.69#ibcon#[27=AT01-04\r\n] 2006.196.08:20:00.69#ibcon#*before write, iclass 5, count 2 2006.196.08:20:00.69#ibcon#enter sib2, iclass 5, count 2 2006.196.08:20:00.69#ibcon#flushed, iclass 5, count 2 2006.196.08:20:00.69#ibcon#about to write, iclass 5, count 2 2006.196.08:20:00.69#ibcon#wrote, iclass 5, count 2 2006.196.08:20:00.69#ibcon#about to read 3, iclass 5, count 2 2006.196.08:20:00.72#ibcon#read 3, iclass 5, count 2 2006.196.08:20:00.72#ibcon#about to read 4, iclass 5, count 2 2006.196.08:20:00.72#ibcon#read 4, iclass 5, count 2 2006.196.08:20:00.72#ibcon#about to read 5, iclass 5, count 2 2006.196.08:20:00.72#ibcon#read 5, iclass 5, count 2 2006.196.08:20:00.72#ibcon#about to read 6, iclass 5, count 2 2006.196.08:20:00.72#ibcon#read 6, iclass 5, count 2 2006.196.08:20:00.72#ibcon#end of sib2, iclass 5, count 2 2006.196.08:20:00.72#ibcon#*after write, iclass 5, count 2 2006.196.08:20:00.72#ibcon#*before return 0, iclass 5, count 2 2006.196.08:20:00.72#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.196.08:20:00.72#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.196.08:20:00.72#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.196.08:20:00.72#ibcon#ireg 7 cls_cnt 0 2006.196.08:20:00.72#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.196.08:20:00.84#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.196.08:20:00.84#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.196.08:20:00.84#ibcon#enter wrdev, iclass 5, count 0 2006.196.08:20:00.84#ibcon#first serial, iclass 5, count 0 2006.196.08:20:00.84#ibcon#enter sib2, iclass 5, count 0 2006.196.08:20:00.84#ibcon#flushed, iclass 5, count 0 2006.196.08:20:00.84#ibcon#about to write, iclass 5, count 0 2006.196.08:20:00.84#ibcon#wrote, iclass 5, count 0 2006.196.08:20:00.84#ibcon#about to read 3, iclass 5, count 0 2006.196.08:20:00.86#ibcon#read 3, iclass 5, count 0 2006.196.08:20:00.86#ibcon#about to read 4, iclass 5, count 0 2006.196.08:20:00.86#ibcon#read 4, iclass 5, count 0 2006.196.08:20:00.86#ibcon#about to read 5, iclass 5, count 0 2006.196.08:20:00.86#ibcon#read 5, iclass 5, count 0 2006.196.08:20:00.86#ibcon#about to read 6, iclass 5, count 0 2006.196.08:20:00.86#ibcon#read 6, iclass 5, count 0 2006.196.08:20:00.86#ibcon#end of sib2, iclass 5, count 0 2006.196.08:20:00.86#ibcon#*mode == 0, iclass 5, count 0 2006.196.08:20:00.86#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.196.08:20:00.86#ibcon#[27=USB\r\n] 2006.196.08:20:00.86#ibcon#*before write, iclass 5, count 0 2006.196.08:20:00.86#ibcon#enter sib2, iclass 5, count 0 2006.196.08:20:00.86#ibcon#flushed, iclass 5, count 0 2006.196.08:20:00.86#ibcon#about to write, iclass 5, count 0 2006.196.08:20:00.86#ibcon#wrote, iclass 5, count 0 2006.196.08:20:00.86#ibcon#about to read 3, iclass 5, count 0 2006.196.08:20:00.89#ibcon#read 3, iclass 5, count 0 2006.196.08:20:00.89#ibcon#about to read 4, iclass 5, count 0 2006.196.08:20:00.89#ibcon#read 4, iclass 5, count 0 2006.196.08:20:00.89#ibcon#about to read 5, iclass 5, count 0 2006.196.08:20:00.89#ibcon#read 5, iclass 5, count 0 2006.196.08:20:00.89#ibcon#about to read 6, iclass 5, count 0 2006.196.08:20:00.89#ibcon#read 6, iclass 5, count 0 2006.196.08:20:00.89#ibcon#end of sib2, iclass 5, count 0 2006.196.08:20:00.89#ibcon#*after write, iclass 5, count 0 2006.196.08:20:00.89#ibcon#*before return 0, iclass 5, count 0 2006.196.08:20:00.89#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.196.08:20:00.89#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.196.08:20:00.89#ibcon#about to clear, iclass 5 cls_cnt 0 2006.196.08:20:00.89#ibcon#cleared, iclass 5 cls_cnt 0 2006.196.08:20:00.89$vc4f8/vblo=2,640.99 2006.196.08:20:00.89#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.196.08:20:00.89#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.196.08:20:00.89#ibcon#ireg 17 cls_cnt 0 2006.196.08:20:00.89#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.196.08:20:00.89#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.196.08:20:00.89#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.196.08:20:00.89#ibcon#enter wrdev, iclass 7, count 0 2006.196.08:20:00.89#ibcon#first serial, iclass 7, count 0 2006.196.08:20:00.89#ibcon#enter sib2, iclass 7, count 0 2006.196.08:20:00.89#ibcon#flushed, iclass 7, count 0 2006.196.08:20:00.89#ibcon#about to write, iclass 7, count 0 2006.196.08:20:00.89#ibcon#wrote, iclass 7, count 0 2006.196.08:20:00.89#ibcon#about to read 3, iclass 7, count 0 2006.196.08:20:00.91#ibcon#read 3, iclass 7, count 0 2006.196.08:20:00.91#ibcon#about to read 4, iclass 7, count 0 2006.196.08:20:00.91#ibcon#read 4, iclass 7, count 0 2006.196.08:20:00.91#ibcon#about to read 5, iclass 7, count 0 2006.196.08:20:00.91#ibcon#read 5, iclass 7, count 0 2006.196.08:20:00.91#ibcon#about to read 6, iclass 7, count 0 2006.196.08:20:00.91#ibcon#read 6, iclass 7, count 0 2006.196.08:20:00.91#ibcon#end of sib2, iclass 7, count 0 2006.196.08:20:00.91#ibcon#*mode == 0, iclass 7, count 0 2006.196.08:20:00.91#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.196.08:20:00.91#ibcon#[28=FRQ=02,640.99\r\n] 2006.196.08:20:00.91#ibcon#*before write, iclass 7, count 0 2006.196.08:20:00.91#ibcon#enter sib2, iclass 7, count 0 2006.196.08:20:00.91#ibcon#flushed, iclass 7, count 0 2006.196.08:20:00.91#ibcon#about to write, iclass 7, count 0 2006.196.08:20:00.91#ibcon#wrote, iclass 7, count 0 2006.196.08:20:00.91#ibcon#about to read 3, iclass 7, count 0 2006.196.08:20:00.95#ibcon#read 3, iclass 7, count 0 2006.196.08:20:00.95#ibcon#about to read 4, iclass 7, count 0 2006.196.08:20:00.95#ibcon#read 4, iclass 7, count 0 2006.196.08:20:00.95#ibcon#about to read 5, iclass 7, count 0 2006.196.08:20:00.95#ibcon#read 5, iclass 7, count 0 2006.196.08:20:00.95#ibcon#about to read 6, iclass 7, count 0 2006.196.08:20:00.95#ibcon#read 6, iclass 7, count 0 2006.196.08:20:00.95#ibcon#end of sib2, iclass 7, count 0 2006.196.08:20:00.95#ibcon#*after write, iclass 7, count 0 2006.196.08:20:00.95#ibcon#*before return 0, iclass 7, count 0 2006.196.08:20:00.95#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.196.08:20:00.95#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.196.08:20:00.95#ibcon#about to clear, iclass 7 cls_cnt 0 2006.196.08:20:00.95#ibcon#cleared, iclass 7 cls_cnt 0 2006.196.08:20:00.95$vc4f8/vb=2,4 2006.196.08:20:00.95#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.196.08:20:00.95#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.196.08:20:00.95#ibcon#ireg 11 cls_cnt 2 2006.196.08:20:00.95#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.196.08:20:01.01#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.196.08:20:01.01#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.196.08:20:01.01#ibcon#enter wrdev, iclass 11, count 2 2006.196.08:20:01.01#ibcon#first serial, iclass 11, count 2 2006.196.08:20:01.01#ibcon#enter sib2, iclass 11, count 2 2006.196.08:20:01.01#ibcon#flushed, iclass 11, count 2 2006.196.08:20:01.01#ibcon#about to write, iclass 11, count 2 2006.196.08:20:01.01#ibcon#wrote, iclass 11, count 2 2006.196.08:20:01.01#ibcon#about to read 3, iclass 11, count 2 2006.196.08:20:01.03#ibcon#read 3, iclass 11, count 2 2006.196.08:20:01.03#ibcon#about to read 4, iclass 11, count 2 2006.196.08:20:01.03#ibcon#read 4, iclass 11, count 2 2006.196.08:20:01.03#ibcon#about to read 5, iclass 11, count 2 2006.196.08:20:01.03#ibcon#read 5, iclass 11, count 2 2006.196.08:20:01.03#ibcon#about to read 6, iclass 11, count 2 2006.196.08:20:01.03#ibcon#read 6, iclass 11, count 2 2006.196.08:20:01.03#ibcon#end of sib2, iclass 11, count 2 2006.196.08:20:01.03#ibcon#*mode == 0, iclass 11, count 2 2006.196.08:20:01.03#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.196.08:20:01.03#ibcon#[27=AT02-04\r\n] 2006.196.08:20:01.03#ibcon#*before write, iclass 11, count 2 2006.196.08:20:01.03#ibcon#enter sib2, iclass 11, count 2 2006.196.08:20:01.03#ibcon#flushed, iclass 11, count 2 2006.196.08:20:01.03#ibcon#about to write, iclass 11, count 2 2006.196.08:20:01.03#ibcon#wrote, iclass 11, count 2 2006.196.08:20:01.03#ibcon#about to read 3, iclass 11, count 2 2006.196.08:20:01.06#ibcon#read 3, iclass 11, count 2 2006.196.08:20:01.06#ibcon#about to read 4, iclass 11, count 2 2006.196.08:20:01.06#ibcon#read 4, iclass 11, count 2 2006.196.08:20:01.06#ibcon#about to read 5, iclass 11, count 2 2006.196.08:20:01.06#ibcon#read 5, iclass 11, count 2 2006.196.08:20:01.06#ibcon#about to read 6, iclass 11, count 2 2006.196.08:20:01.06#ibcon#read 6, iclass 11, count 2 2006.196.08:20:01.06#ibcon#end of sib2, iclass 11, count 2 2006.196.08:20:01.06#ibcon#*after write, iclass 11, count 2 2006.196.08:20:01.06#ibcon#*before return 0, iclass 11, count 2 2006.196.08:20:01.06#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.196.08:20:01.06#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.196.08:20:01.06#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.196.08:20:01.06#ibcon#ireg 7 cls_cnt 0 2006.196.08:20:01.06#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.196.08:20:01.18#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.196.08:20:01.18#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.196.08:20:01.18#ibcon#enter wrdev, iclass 11, count 0 2006.196.08:20:01.18#ibcon#first serial, iclass 11, count 0 2006.196.08:20:01.18#ibcon#enter sib2, iclass 11, count 0 2006.196.08:20:01.18#ibcon#flushed, iclass 11, count 0 2006.196.08:20:01.18#ibcon#about to write, iclass 11, count 0 2006.196.08:20:01.18#ibcon#wrote, iclass 11, count 0 2006.196.08:20:01.18#ibcon#about to read 3, iclass 11, count 0 2006.196.08:20:01.21#ibcon#read 3, iclass 11, count 0 2006.196.08:20:01.21#ibcon#about to read 4, iclass 11, count 0 2006.196.08:20:01.21#ibcon#read 4, iclass 11, count 0 2006.196.08:20:01.21#ibcon#about to read 5, iclass 11, count 0 2006.196.08:20:01.21#ibcon#read 5, iclass 11, count 0 2006.196.08:20:01.21#ibcon#about to read 6, iclass 11, count 0 2006.196.08:20:01.21#ibcon#read 6, iclass 11, count 0 2006.196.08:20:01.21#ibcon#end of sib2, iclass 11, count 0 2006.196.08:20:01.21#ibcon#*mode == 0, iclass 11, count 0 2006.196.08:20:01.21#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.196.08:20:01.21#ibcon#[27=USB\r\n] 2006.196.08:20:01.21#ibcon#*before write, iclass 11, count 0 2006.196.08:20:01.21#ibcon#enter sib2, iclass 11, count 0 2006.196.08:20:01.21#ibcon#flushed, iclass 11, count 0 2006.196.08:20:01.21#ibcon#about to write, iclass 11, count 0 2006.196.08:20:01.21#ibcon#wrote, iclass 11, count 0 2006.196.08:20:01.21#ibcon#about to read 3, iclass 11, count 0 2006.196.08:20:01.24#ibcon#read 3, iclass 11, count 0 2006.196.08:20:01.24#ibcon#about to read 4, iclass 11, count 0 2006.196.08:20:01.24#ibcon#read 4, iclass 11, count 0 2006.196.08:20:01.24#ibcon#about to read 5, iclass 11, count 0 2006.196.08:20:01.24#ibcon#read 5, iclass 11, count 0 2006.196.08:20:01.24#ibcon#about to read 6, iclass 11, count 0 2006.196.08:20:01.24#ibcon#read 6, iclass 11, count 0 2006.196.08:20:01.24#ibcon#end of sib2, iclass 11, count 0 2006.196.08:20:01.24#ibcon#*after write, iclass 11, count 0 2006.196.08:20:01.24#ibcon#*before return 0, iclass 11, count 0 2006.196.08:20:01.24#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.196.08:20:01.24#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.196.08:20:01.24#ibcon#about to clear, iclass 11 cls_cnt 0 2006.196.08:20:01.24#ibcon#cleared, iclass 11 cls_cnt 0 2006.196.08:20:01.24$vc4f8/vblo=3,656.99 2006.196.08:20:01.24#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.196.08:20:01.24#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.196.08:20:01.24#ibcon#ireg 17 cls_cnt 0 2006.196.08:20:01.24#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.196.08:20:01.24#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.196.08:20:01.24#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.196.08:20:01.24#ibcon#enter wrdev, iclass 13, count 0 2006.196.08:20:01.24#ibcon#first serial, iclass 13, count 0 2006.196.08:20:01.24#ibcon#enter sib2, iclass 13, count 0 2006.196.08:20:01.24#ibcon#flushed, iclass 13, count 0 2006.196.08:20:01.24#ibcon#about to write, iclass 13, count 0 2006.196.08:20:01.24#ibcon#wrote, iclass 13, count 0 2006.196.08:20:01.24#ibcon#about to read 3, iclass 13, count 0 2006.196.08:20:01.26#ibcon#read 3, iclass 13, count 0 2006.196.08:20:01.26#ibcon#about to read 4, iclass 13, count 0 2006.196.08:20:01.26#ibcon#read 4, iclass 13, count 0 2006.196.08:20:01.26#ibcon#about to read 5, iclass 13, count 0 2006.196.08:20:01.26#ibcon#read 5, iclass 13, count 0 2006.196.08:20:01.26#ibcon#about to read 6, iclass 13, count 0 2006.196.08:20:01.26#ibcon#read 6, iclass 13, count 0 2006.196.08:20:01.26#ibcon#end of sib2, iclass 13, count 0 2006.196.08:20:01.26#ibcon#*mode == 0, iclass 13, count 0 2006.196.08:20:01.26#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.196.08:20:01.26#ibcon#[28=FRQ=03,656.99\r\n] 2006.196.08:20:01.26#ibcon#*before write, iclass 13, count 0 2006.196.08:20:01.26#ibcon#enter sib2, iclass 13, count 0 2006.196.08:20:01.26#ibcon#flushed, iclass 13, count 0 2006.196.08:20:01.26#ibcon#about to write, iclass 13, count 0 2006.196.08:20:01.26#ibcon#wrote, iclass 13, count 0 2006.196.08:20:01.26#ibcon#about to read 3, iclass 13, count 0 2006.196.08:20:01.30#ibcon#read 3, iclass 13, count 0 2006.196.08:20:01.30#ibcon#about to read 4, iclass 13, count 0 2006.196.08:20:01.30#ibcon#read 4, iclass 13, count 0 2006.196.08:20:01.30#ibcon#about to read 5, iclass 13, count 0 2006.196.08:20:01.30#ibcon#read 5, iclass 13, count 0 2006.196.08:20:01.30#ibcon#about to read 6, iclass 13, count 0 2006.196.08:20:01.30#ibcon#read 6, iclass 13, count 0 2006.196.08:20:01.30#ibcon#end of sib2, iclass 13, count 0 2006.196.08:20:01.30#ibcon#*after write, iclass 13, count 0 2006.196.08:20:01.30#ibcon#*before return 0, iclass 13, count 0 2006.196.08:20:01.30#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.196.08:20:01.30#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.196.08:20:01.30#ibcon#about to clear, iclass 13 cls_cnt 0 2006.196.08:20:01.30#ibcon#cleared, iclass 13 cls_cnt 0 2006.196.08:20:01.30$vc4f8/vb=3,4 2006.196.08:20:01.30#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.196.08:20:01.30#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.196.08:20:01.30#ibcon#ireg 11 cls_cnt 2 2006.196.08:20:01.30#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.196.08:20:01.36#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.196.08:20:01.36#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.196.08:20:01.36#ibcon#enter wrdev, iclass 15, count 2 2006.196.08:20:01.36#ibcon#first serial, iclass 15, count 2 2006.196.08:20:01.36#ibcon#enter sib2, iclass 15, count 2 2006.196.08:20:01.36#ibcon#flushed, iclass 15, count 2 2006.196.08:20:01.36#ibcon#about to write, iclass 15, count 2 2006.196.08:20:01.36#ibcon#wrote, iclass 15, count 2 2006.196.08:20:01.36#ibcon#about to read 3, iclass 15, count 2 2006.196.08:20:01.38#ibcon#read 3, iclass 15, count 2 2006.196.08:20:01.38#ibcon#about to read 4, iclass 15, count 2 2006.196.08:20:01.38#ibcon#read 4, iclass 15, count 2 2006.196.08:20:01.38#ibcon#about to read 5, iclass 15, count 2 2006.196.08:20:01.38#ibcon#read 5, iclass 15, count 2 2006.196.08:20:01.38#ibcon#about to read 6, iclass 15, count 2 2006.196.08:20:01.38#ibcon#read 6, iclass 15, count 2 2006.196.08:20:01.38#ibcon#end of sib2, iclass 15, count 2 2006.196.08:20:01.38#ibcon#*mode == 0, iclass 15, count 2 2006.196.08:20:01.38#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.196.08:20:01.38#ibcon#[27=AT03-04\r\n] 2006.196.08:20:01.38#ibcon#*before write, iclass 15, count 2 2006.196.08:20:01.38#ibcon#enter sib2, iclass 15, count 2 2006.196.08:20:01.38#ibcon#flushed, iclass 15, count 2 2006.196.08:20:01.38#ibcon#about to write, iclass 15, count 2 2006.196.08:20:01.38#ibcon#wrote, iclass 15, count 2 2006.196.08:20:01.38#ibcon#about to read 3, iclass 15, count 2 2006.196.08:20:01.41#ibcon#read 3, iclass 15, count 2 2006.196.08:20:01.41#ibcon#about to read 4, iclass 15, count 2 2006.196.08:20:01.41#ibcon#read 4, iclass 15, count 2 2006.196.08:20:01.41#ibcon#about to read 5, iclass 15, count 2 2006.196.08:20:01.41#ibcon#read 5, iclass 15, count 2 2006.196.08:20:01.41#ibcon#about to read 6, iclass 15, count 2 2006.196.08:20:01.41#ibcon#read 6, iclass 15, count 2 2006.196.08:20:01.41#ibcon#end of sib2, iclass 15, count 2 2006.196.08:20:01.41#ibcon#*after write, iclass 15, count 2 2006.196.08:20:01.41#ibcon#*before return 0, iclass 15, count 2 2006.196.08:20:01.41#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.196.08:20:01.41#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.196.08:20:01.41#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.196.08:20:01.41#ibcon#ireg 7 cls_cnt 0 2006.196.08:20:01.41#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.196.08:20:01.46#abcon#<5=/05 4.1 6.4 28.94 931004.0\r\n> 2006.196.08:20:01.48#abcon#{5=INTERFACE CLEAR} 2006.196.08:20:01.53#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.196.08:20:01.53#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.196.08:20:01.53#ibcon#enter wrdev, iclass 15, count 0 2006.196.08:20:01.53#ibcon#first serial, iclass 15, count 0 2006.196.08:20:01.53#ibcon#enter sib2, iclass 15, count 0 2006.196.08:20:01.53#ibcon#flushed, iclass 15, count 0 2006.196.08:20:01.53#ibcon#about to write, iclass 15, count 0 2006.196.08:20:01.53#ibcon#wrote, iclass 15, count 0 2006.196.08:20:01.53#ibcon#about to read 3, iclass 15, count 0 2006.196.08:20:01.54#abcon#[5=S1D000X0/0*\r\n] 2006.196.08:20:01.55#ibcon#read 3, iclass 15, count 0 2006.196.08:20:01.55#ibcon#about to read 4, iclass 15, count 0 2006.196.08:20:01.55#ibcon#read 4, iclass 15, count 0 2006.196.08:20:01.55#ibcon#about to read 5, iclass 15, count 0 2006.196.08:20:01.55#ibcon#read 5, iclass 15, count 0 2006.196.08:20:01.55#ibcon#about to read 6, iclass 15, count 0 2006.196.08:20:01.55#ibcon#read 6, iclass 15, count 0 2006.196.08:20:01.55#ibcon#end of sib2, iclass 15, count 0 2006.196.08:20:01.55#ibcon#*mode == 0, iclass 15, count 0 2006.196.08:20:01.55#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.196.08:20:01.55#ibcon#[27=USB\r\n] 2006.196.08:20:01.55#ibcon#*before write, iclass 15, count 0 2006.196.08:20:01.55#ibcon#enter sib2, iclass 15, count 0 2006.196.08:20:01.55#ibcon#flushed, iclass 15, count 0 2006.196.08:20:01.55#ibcon#about to write, iclass 15, count 0 2006.196.08:20:01.55#ibcon#wrote, iclass 15, count 0 2006.196.08:20:01.55#ibcon#about to read 3, iclass 15, count 0 2006.196.08:20:01.58#ibcon#read 3, iclass 15, count 0 2006.196.08:20:01.58#ibcon#about to read 4, iclass 15, count 0 2006.196.08:20:01.58#ibcon#read 4, iclass 15, count 0 2006.196.08:20:01.58#ibcon#about to read 5, iclass 15, count 0 2006.196.08:20:01.58#ibcon#read 5, iclass 15, count 0 2006.196.08:20:01.58#ibcon#about to read 6, iclass 15, count 0 2006.196.08:20:01.58#ibcon#read 6, iclass 15, count 0 2006.196.08:20:01.58#ibcon#end of sib2, iclass 15, count 0 2006.196.08:20:01.58#ibcon#*after write, iclass 15, count 0 2006.196.08:20:01.58#ibcon#*before return 0, iclass 15, count 0 2006.196.08:20:01.58#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.196.08:20:01.58#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.196.08:20:01.58#ibcon#about to clear, iclass 15 cls_cnt 0 2006.196.08:20:01.58#ibcon#cleared, iclass 15 cls_cnt 0 2006.196.08:20:01.58$vc4f8/vblo=4,712.99 2006.196.08:20:01.58#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.196.08:20:01.58#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.196.08:20:01.58#ibcon#ireg 17 cls_cnt 0 2006.196.08:20:01.58#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.196.08:20:01.58#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.196.08:20:01.58#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.196.08:20:01.58#ibcon#enter wrdev, iclass 21, count 0 2006.196.08:20:01.58#ibcon#first serial, iclass 21, count 0 2006.196.08:20:01.58#ibcon#enter sib2, iclass 21, count 0 2006.196.08:20:01.58#ibcon#flushed, iclass 21, count 0 2006.196.08:20:01.58#ibcon#about to write, iclass 21, count 0 2006.196.08:20:01.58#ibcon#wrote, iclass 21, count 0 2006.196.08:20:01.58#ibcon#about to read 3, iclass 21, count 0 2006.196.08:20:01.60#ibcon#read 3, iclass 21, count 0 2006.196.08:20:01.60#ibcon#about to read 4, iclass 21, count 0 2006.196.08:20:01.60#ibcon#read 4, iclass 21, count 0 2006.196.08:20:01.60#ibcon#about to read 5, iclass 21, count 0 2006.196.08:20:01.60#ibcon#read 5, iclass 21, count 0 2006.196.08:20:01.60#ibcon#about to read 6, iclass 21, count 0 2006.196.08:20:01.60#ibcon#read 6, iclass 21, count 0 2006.196.08:20:01.60#ibcon#end of sib2, iclass 21, count 0 2006.196.08:20:01.60#ibcon#*mode == 0, iclass 21, count 0 2006.196.08:20:01.60#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.196.08:20:01.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.196.08:20:01.60#ibcon#*before write, iclass 21, count 0 2006.196.08:20:01.60#ibcon#enter sib2, iclass 21, count 0 2006.196.08:20:01.60#ibcon#flushed, iclass 21, count 0 2006.196.08:20:01.60#ibcon#about to write, iclass 21, count 0 2006.196.08:20:01.60#ibcon#wrote, iclass 21, count 0 2006.196.08:20:01.60#ibcon#about to read 3, iclass 21, count 0 2006.196.08:20:01.64#ibcon#read 3, iclass 21, count 0 2006.196.08:20:01.64#ibcon#about to read 4, iclass 21, count 0 2006.196.08:20:01.64#ibcon#read 4, iclass 21, count 0 2006.196.08:20:01.64#ibcon#about to read 5, iclass 21, count 0 2006.196.08:20:01.64#ibcon#read 5, iclass 21, count 0 2006.196.08:20:01.64#ibcon#about to read 6, iclass 21, count 0 2006.196.08:20:01.64#ibcon#read 6, iclass 21, count 0 2006.196.08:20:01.64#ibcon#end of sib2, iclass 21, count 0 2006.196.08:20:01.64#ibcon#*after write, iclass 21, count 0 2006.196.08:20:01.64#ibcon#*before return 0, iclass 21, count 0 2006.196.08:20:01.64#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.196.08:20:01.64#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.196.08:20:01.64#ibcon#about to clear, iclass 21 cls_cnt 0 2006.196.08:20:01.64#ibcon#cleared, iclass 21 cls_cnt 0 2006.196.08:20:01.64$vc4f8/vb=4,4 2006.196.08:20:01.64#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.196.08:20:01.64#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.196.08:20:01.64#ibcon#ireg 11 cls_cnt 2 2006.196.08:20:01.64#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.196.08:20:01.70#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.196.08:20:01.70#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.196.08:20:01.70#ibcon#enter wrdev, iclass 23, count 2 2006.196.08:20:01.70#ibcon#first serial, iclass 23, count 2 2006.196.08:20:01.70#ibcon#enter sib2, iclass 23, count 2 2006.196.08:20:01.70#ibcon#flushed, iclass 23, count 2 2006.196.08:20:01.70#ibcon#about to write, iclass 23, count 2 2006.196.08:20:01.70#ibcon#wrote, iclass 23, count 2 2006.196.08:20:01.70#ibcon#about to read 3, iclass 23, count 2 2006.196.08:20:01.72#ibcon#read 3, iclass 23, count 2 2006.196.08:20:01.72#ibcon#about to read 4, iclass 23, count 2 2006.196.08:20:01.72#ibcon#read 4, iclass 23, count 2 2006.196.08:20:01.72#ibcon#about to read 5, iclass 23, count 2 2006.196.08:20:01.72#ibcon#read 5, iclass 23, count 2 2006.196.08:20:01.72#ibcon#about to read 6, iclass 23, count 2 2006.196.08:20:01.72#ibcon#read 6, iclass 23, count 2 2006.196.08:20:01.72#ibcon#end of sib2, iclass 23, count 2 2006.196.08:20:01.72#ibcon#*mode == 0, iclass 23, count 2 2006.196.08:20:01.72#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.196.08:20:01.72#ibcon#[27=AT04-04\r\n] 2006.196.08:20:01.72#ibcon#*before write, iclass 23, count 2 2006.196.08:20:01.72#ibcon#enter sib2, iclass 23, count 2 2006.196.08:20:01.72#ibcon#flushed, iclass 23, count 2 2006.196.08:20:01.72#ibcon#about to write, iclass 23, count 2 2006.196.08:20:01.72#ibcon#wrote, iclass 23, count 2 2006.196.08:20:01.72#ibcon#about to read 3, iclass 23, count 2 2006.196.08:20:01.75#ibcon#read 3, iclass 23, count 2 2006.196.08:20:01.75#ibcon#about to read 4, iclass 23, count 2 2006.196.08:20:01.75#ibcon#read 4, iclass 23, count 2 2006.196.08:20:01.75#ibcon#about to read 5, iclass 23, count 2 2006.196.08:20:01.75#ibcon#read 5, iclass 23, count 2 2006.196.08:20:01.75#ibcon#about to read 6, iclass 23, count 2 2006.196.08:20:01.75#ibcon#read 6, iclass 23, count 2 2006.196.08:20:01.75#ibcon#end of sib2, iclass 23, count 2 2006.196.08:20:01.75#ibcon#*after write, iclass 23, count 2 2006.196.08:20:01.75#ibcon#*before return 0, iclass 23, count 2 2006.196.08:20:01.75#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.196.08:20:01.75#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.196.08:20:01.75#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.196.08:20:01.75#ibcon#ireg 7 cls_cnt 0 2006.196.08:20:01.75#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.196.08:20:01.87#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.196.08:20:01.87#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.196.08:20:01.87#ibcon#enter wrdev, iclass 23, count 0 2006.196.08:20:01.87#ibcon#first serial, iclass 23, count 0 2006.196.08:20:01.87#ibcon#enter sib2, iclass 23, count 0 2006.196.08:20:01.87#ibcon#flushed, iclass 23, count 0 2006.196.08:20:01.87#ibcon#about to write, iclass 23, count 0 2006.196.08:20:01.87#ibcon#wrote, iclass 23, count 0 2006.196.08:20:01.87#ibcon#about to read 3, iclass 23, count 0 2006.196.08:20:01.89#ibcon#read 3, iclass 23, count 0 2006.196.08:20:01.89#ibcon#about to read 4, iclass 23, count 0 2006.196.08:20:01.89#ibcon#read 4, iclass 23, count 0 2006.196.08:20:01.89#ibcon#about to read 5, iclass 23, count 0 2006.196.08:20:01.89#ibcon#read 5, iclass 23, count 0 2006.196.08:20:01.89#ibcon#about to read 6, iclass 23, count 0 2006.196.08:20:01.89#ibcon#read 6, iclass 23, count 0 2006.196.08:20:01.89#ibcon#end of sib2, iclass 23, count 0 2006.196.08:20:01.89#ibcon#*mode == 0, iclass 23, count 0 2006.196.08:20:01.89#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.196.08:20:01.89#ibcon#[27=USB\r\n] 2006.196.08:20:01.89#ibcon#*before write, iclass 23, count 0 2006.196.08:20:01.89#ibcon#enter sib2, iclass 23, count 0 2006.196.08:20:01.89#ibcon#flushed, iclass 23, count 0 2006.196.08:20:01.89#ibcon#about to write, iclass 23, count 0 2006.196.08:20:01.89#ibcon#wrote, iclass 23, count 0 2006.196.08:20:01.89#ibcon#about to read 3, iclass 23, count 0 2006.196.08:20:01.92#ibcon#read 3, iclass 23, count 0 2006.196.08:20:01.92#ibcon#about to read 4, iclass 23, count 0 2006.196.08:20:01.92#ibcon#read 4, iclass 23, count 0 2006.196.08:20:01.92#ibcon#about to read 5, iclass 23, count 0 2006.196.08:20:01.92#ibcon#read 5, iclass 23, count 0 2006.196.08:20:01.92#ibcon#about to read 6, iclass 23, count 0 2006.196.08:20:01.92#ibcon#read 6, iclass 23, count 0 2006.196.08:20:01.92#ibcon#end of sib2, iclass 23, count 0 2006.196.08:20:01.92#ibcon#*after write, iclass 23, count 0 2006.196.08:20:01.92#ibcon#*before return 0, iclass 23, count 0 2006.196.08:20:01.92#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.196.08:20:01.92#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.196.08:20:01.92#ibcon#about to clear, iclass 23 cls_cnt 0 2006.196.08:20:01.92#ibcon#cleared, iclass 23 cls_cnt 0 2006.196.08:20:01.92$vc4f8/vblo=5,744.99 2006.196.08:20:01.92#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.196.08:20:01.92#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.196.08:20:01.92#ibcon#ireg 17 cls_cnt 0 2006.196.08:20:01.92#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.196.08:20:01.92#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.196.08:20:01.92#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.196.08:20:01.92#ibcon#enter wrdev, iclass 25, count 0 2006.196.08:20:01.92#ibcon#first serial, iclass 25, count 0 2006.196.08:20:01.92#ibcon#enter sib2, iclass 25, count 0 2006.196.08:20:01.92#ibcon#flushed, iclass 25, count 0 2006.196.08:20:01.92#ibcon#about to write, iclass 25, count 0 2006.196.08:20:01.92#ibcon#wrote, iclass 25, count 0 2006.196.08:20:01.92#ibcon#about to read 3, iclass 25, count 0 2006.196.08:20:01.94#ibcon#read 3, iclass 25, count 0 2006.196.08:20:01.94#ibcon#about to read 4, iclass 25, count 0 2006.196.08:20:01.94#ibcon#read 4, iclass 25, count 0 2006.196.08:20:01.94#ibcon#about to read 5, iclass 25, count 0 2006.196.08:20:01.94#ibcon#read 5, iclass 25, count 0 2006.196.08:20:01.94#ibcon#about to read 6, iclass 25, count 0 2006.196.08:20:01.94#ibcon#read 6, iclass 25, count 0 2006.196.08:20:01.94#ibcon#end of sib2, iclass 25, count 0 2006.196.08:20:01.94#ibcon#*mode == 0, iclass 25, count 0 2006.196.08:20:01.94#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.196.08:20:01.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.196.08:20:01.94#ibcon#*before write, iclass 25, count 0 2006.196.08:20:01.94#ibcon#enter sib2, iclass 25, count 0 2006.196.08:20:01.94#ibcon#flushed, iclass 25, count 0 2006.196.08:20:01.94#ibcon#about to write, iclass 25, count 0 2006.196.08:20:01.94#ibcon#wrote, iclass 25, count 0 2006.196.08:20:01.94#ibcon#about to read 3, iclass 25, count 0 2006.196.08:20:01.98#ibcon#read 3, iclass 25, count 0 2006.196.08:20:01.98#ibcon#about to read 4, iclass 25, count 0 2006.196.08:20:01.98#ibcon#read 4, iclass 25, count 0 2006.196.08:20:01.98#ibcon#about to read 5, iclass 25, count 0 2006.196.08:20:01.98#ibcon#read 5, iclass 25, count 0 2006.196.08:20:01.98#ibcon#about to read 6, iclass 25, count 0 2006.196.08:20:01.98#ibcon#read 6, iclass 25, count 0 2006.196.08:20:01.98#ibcon#end of sib2, iclass 25, count 0 2006.196.08:20:01.98#ibcon#*after write, iclass 25, count 0 2006.196.08:20:01.98#ibcon#*before return 0, iclass 25, count 0 2006.196.08:20:01.98#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.196.08:20:01.98#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.196.08:20:01.98#ibcon#about to clear, iclass 25 cls_cnt 0 2006.196.08:20:01.98#ibcon#cleared, iclass 25 cls_cnt 0 2006.196.08:20:01.98$vc4f8/vb=5,4 2006.196.08:20:01.98#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.196.08:20:01.98#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.196.08:20:01.98#ibcon#ireg 11 cls_cnt 2 2006.196.08:20:01.98#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.196.08:20:02.04#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.196.08:20:02.04#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.196.08:20:02.04#ibcon#enter wrdev, iclass 27, count 2 2006.196.08:20:02.04#ibcon#first serial, iclass 27, count 2 2006.196.08:20:02.04#ibcon#enter sib2, iclass 27, count 2 2006.196.08:20:02.04#ibcon#flushed, iclass 27, count 2 2006.196.08:20:02.04#ibcon#about to write, iclass 27, count 2 2006.196.08:20:02.04#ibcon#wrote, iclass 27, count 2 2006.196.08:20:02.04#ibcon#about to read 3, iclass 27, count 2 2006.196.08:20:02.06#ibcon#read 3, iclass 27, count 2 2006.196.08:20:02.06#ibcon#about to read 4, iclass 27, count 2 2006.196.08:20:02.06#ibcon#read 4, iclass 27, count 2 2006.196.08:20:02.06#ibcon#about to read 5, iclass 27, count 2 2006.196.08:20:02.06#ibcon#read 5, iclass 27, count 2 2006.196.08:20:02.06#ibcon#about to read 6, iclass 27, count 2 2006.196.08:20:02.06#ibcon#read 6, iclass 27, count 2 2006.196.08:20:02.06#ibcon#end of sib2, iclass 27, count 2 2006.196.08:20:02.06#ibcon#*mode == 0, iclass 27, count 2 2006.196.08:20:02.06#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.196.08:20:02.06#ibcon#[27=AT05-04\r\n] 2006.196.08:20:02.06#ibcon#*before write, iclass 27, count 2 2006.196.08:20:02.06#ibcon#enter sib2, iclass 27, count 2 2006.196.08:20:02.06#ibcon#flushed, iclass 27, count 2 2006.196.08:20:02.06#ibcon#about to write, iclass 27, count 2 2006.196.08:20:02.06#ibcon#wrote, iclass 27, count 2 2006.196.08:20:02.06#ibcon#about to read 3, iclass 27, count 2 2006.196.08:20:02.09#ibcon#read 3, iclass 27, count 2 2006.196.08:20:02.09#ibcon#about to read 4, iclass 27, count 2 2006.196.08:20:02.09#ibcon#read 4, iclass 27, count 2 2006.196.08:20:02.09#ibcon#about to read 5, iclass 27, count 2 2006.196.08:20:02.09#ibcon#read 5, iclass 27, count 2 2006.196.08:20:02.09#ibcon#about to read 6, iclass 27, count 2 2006.196.08:20:02.09#ibcon#read 6, iclass 27, count 2 2006.196.08:20:02.09#ibcon#end of sib2, iclass 27, count 2 2006.196.08:20:02.09#ibcon#*after write, iclass 27, count 2 2006.196.08:20:02.09#ibcon#*before return 0, iclass 27, count 2 2006.196.08:20:02.09#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.196.08:20:02.09#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.196.08:20:02.09#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.196.08:20:02.09#ibcon#ireg 7 cls_cnt 0 2006.196.08:20:02.09#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.196.08:20:02.21#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.196.08:20:02.21#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.196.08:20:02.21#ibcon#enter wrdev, iclass 27, count 0 2006.196.08:20:02.21#ibcon#first serial, iclass 27, count 0 2006.196.08:20:02.21#ibcon#enter sib2, iclass 27, count 0 2006.196.08:20:02.21#ibcon#flushed, iclass 27, count 0 2006.196.08:20:02.21#ibcon#about to write, iclass 27, count 0 2006.196.08:20:02.21#ibcon#wrote, iclass 27, count 0 2006.196.08:20:02.21#ibcon#about to read 3, iclass 27, count 0 2006.196.08:20:02.23#ibcon#read 3, iclass 27, count 0 2006.196.08:20:02.23#ibcon#about to read 4, iclass 27, count 0 2006.196.08:20:02.23#ibcon#read 4, iclass 27, count 0 2006.196.08:20:02.23#ibcon#about to read 5, iclass 27, count 0 2006.196.08:20:02.23#ibcon#read 5, iclass 27, count 0 2006.196.08:20:02.23#ibcon#about to read 6, iclass 27, count 0 2006.196.08:20:02.23#ibcon#read 6, iclass 27, count 0 2006.196.08:20:02.23#ibcon#end of sib2, iclass 27, count 0 2006.196.08:20:02.23#ibcon#*mode == 0, iclass 27, count 0 2006.196.08:20:02.23#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.196.08:20:02.23#ibcon#[27=USB\r\n] 2006.196.08:20:02.23#ibcon#*before write, iclass 27, count 0 2006.196.08:20:02.23#ibcon#enter sib2, iclass 27, count 0 2006.196.08:20:02.23#ibcon#flushed, iclass 27, count 0 2006.196.08:20:02.23#ibcon#about to write, iclass 27, count 0 2006.196.08:20:02.23#ibcon#wrote, iclass 27, count 0 2006.196.08:20:02.23#ibcon#about to read 3, iclass 27, count 0 2006.196.08:20:02.26#ibcon#read 3, iclass 27, count 0 2006.196.08:20:02.26#ibcon#about to read 4, iclass 27, count 0 2006.196.08:20:02.26#ibcon#read 4, iclass 27, count 0 2006.196.08:20:02.26#ibcon#about to read 5, iclass 27, count 0 2006.196.08:20:02.26#ibcon#read 5, iclass 27, count 0 2006.196.08:20:02.26#ibcon#about to read 6, iclass 27, count 0 2006.196.08:20:02.26#ibcon#read 6, iclass 27, count 0 2006.196.08:20:02.26#ibcon#end of sib2, iclass 27, count 0 2006.196.08:20:02.26#ibcon#*after write, iclass 27, count 0 2006.196.08:20:02.26#ibcon#*before return 0, iclass 27, count 0 2006.196.08:20:02.26#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.196.08:20:02.26#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.196.08:20:02.26#ibcon#about to clear, iclass 27 cls_cnt 0 2006.196.08:20:02.26#ibcon#cleared, iclass 27 cls_cnt 0 2006.196.08:20:02.26$vc4f8/vblo=6,752.99 2006.196.08:20:02.26#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.196.08:20:02.26#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.196.08:20:02.26#ibcon#ireg 17 cls_cnt 0 2006.196.08:20:02.26#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.196.08:20:02.26#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.196.08:20:02.26#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.196.08:20:02.26#ibcon#enter wrdev, iclass 29, count 0 2006.196.08:20:02.26#ibcon#first serial, iclass 29, count 0 2006.196.08:20:02.26#ibcon#enter sib2, iclass 29, count 0 2006.196.08:20:02.26#ibcon#flushed, iclass 29, count 0 2006.196.08:20:02.26#ibcon#about to write, iclass 29, count 0 2006.196.08:20:02.26#ibcon#wrote, iclass 29, count 0 2006.196.08:20:02.26#ibcon#about to read 3, iclass 29, count 0 2006.196.08:20:02.28#ibcon#read 3, iclass 29, count 0 2006.196.08:20:02.28#ibcon#about to read 4, iclass 29, count 0 2006.196.08:20:02.28#ibcon#read 4, iclass 29, count 0 2006.196.08:20:02.28#ibcon#about to read 5, iclass 29, count 0 2006.196.08:20:02.28#ibcon#read 5, iclass 29, count 0 2006.196.08:20:02.28#ibcon#about to read 6, iclass 29, count 0 2006.196.08:20:02.28#ibcon#read 6, iclass 29, count 0 2006.196.08:20:02.28#ibcon#end of sib2, iclass 29, count 0 2006.196.08:20:02.28#ibcon#*mode == 0, iclass 29, count 0 2006.196.08:20:02.28#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.196.08:20:02.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.196.08:20:02.28#ibcon#*before write, iclass 29, count 0 2006.196.08:20:02.28#ibcon#enter sib2, iclass 29, count 0 2006.196.08:20:02.28#ibcon#flushed, iclass 29, count 0 2006.196.08:20:02.28#ibcon#about to write, iclass 29, count 0 2006.196.08:20:02.28#ibcon#wrote, iclass 29, count 0 2006.196.08:20:02.28#ibcon#about to read 3, iclass 29, count 0 2006.196.08:20:02.32#ibcon#read 3, iclass 29, count 0 2006.196.08:20:02.32#ibcon#about to read 4, iclass 29, count 0 2006.196.08:20:02.32#ibcon#read 4, iclass 29, count 0 2006.196.08:20:02.32#ibcon#about to read 5, iclass 29, count 0 2006.196.08:20:02.32#ibcon#read 5, iclass 29, count 0 2006.196.08:20:02.32#ibcon#about to read 6, iclass 29, count 0 2006.196.08:20:02.32#ibcon#read 6, iclass 29, count 0 2006.196.08:20:02.32#ibcon#end of sib2, iclass 29, count 0 2006.196.08:20:02.32#ibcon#*after write, iclass 29, count 0 2006.196.08:20:02.32#ibcon#*before return 0, iclass 29, count 0 2006.196.08:20:02.32#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.196.08:20:02.32#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.196.08:20:02.32#ibcon#about to clear, iclass 29 cls_cnt 0 2006.196.08:20:02.32#ibcon#cleared, iclass 29 cls_cnt 0 2006.196.08:20:02.32$vc4f8/vb=6,4 2006.196.08:20:02.32#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.196.08:20:02.32#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.196.08:20:02.32#ibcon#ireg 11 cls_cnt 2 2006.196.08:20:02.32#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.196.08:20:02.38#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.196.08:20:02.38#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.196.08:20:02.38#ibcon#enter wrdev, iclass 31, count 2 2006.196.08:20:02.38#ibcon#first serial, iclass 31, count 2 2006.196.08:20:02.38#ibcon#enter sib2, iclass 31, count 2 2006.196.08:20:02.38#ibcon#flushed, iclass 31, count 2 2006.196.08:20:02.38#ibcon#about to write, iclass 31, count 2 2006.196.08:20:02.38#ibcon#wrote, iclass 31, count 2 2006.196.08:20:02.38#ibcon#about to read 3, iclass 31, count 2 2006.196.08:20:02.40#ibcon#read 3, iclass 31, count 2 2006.196.08:20:02.40#ibcon#about to read 4, iclass 31, count 2 2006.196.08:20:02.40#ibcon#read 4, iclass 31, count 2 2006.196.08:20:02.40#ibcon#about to read 5, iclass 31, count 2 2006.196.08:20:02.40#ibcon#read 5, iclass 31, count 2 2006.196.08:20:02.40#ibcon#about to read 6, iclass 31, count 2 2006.196.08:20:02.40#ibcon#read 6, iclass 31, count 2 2006.196.08:20:02.40#ibcon#end of sib2, iclass 31, count 2 2006.196.08:20:02.40#ibcon#*mode == 0, iclass 31, count 2 2006.196.08:20:02.40#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.196.08:20:02.40#ibcon#[27=AT06-04\r\n] 2006.196.08:20:02.40#ibcon#*before write, iclass 31, count 2 2006.196.08:20:02.40#ibcon#enter sib2, iclass 31, count 2 2006.196.08:20:02.40#ibcon#flushed, iclass 31, count 2 2006.196.08:20:02.40#ibcon#about to write, iclass 31, count 2 2006.196.08:20:02.40#ibcon#wrote, iclass 31, count 2 2006.196.08:20:02.40#ibcon#about to read 3, iclass 31, count 2 2006.196.08:20:02.43#ibcon#read 3, iclass 31, count 2 2006.196.08:20:02.43#ibcon#about to read 4, iclass 31, count 2 2006.196.08:20:02.43#ibcon#read 4, iclass 31, count 2 2006.196.08:20:02.43#ibcon#about to read 5, iclass 31, count 2 2006.196.08:20:02.43#ibcon#read 5, iclass 31, count 2 2006.196.08:20:02.43#ibcon#about to read 6, iclass 31, count 2 2006.196.08:20:02.43#ibcon#read 6, iclass 31, count 2 2006.196.08:20:02.43#ibcon#end of sib2, iclass 31, count 2 2006.196.08:20:02.43#ibcon#*after write, iclass 31, count 2 2006.196.08:20:02.43#ibcon#*before return 0, iclass 31, count 2 2006.196.08:20:02.43#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.196.08:20:02.43#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.196.08:20:02.43#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.196.08:20:02.43#ibcon#ireg 7 cls_cnt 0 2006.196.08:20:02.43#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.196.08:20:02.55#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.196.08:20:02.55#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.196.08:20:02.55#ibcon#enter wrdev, iclass 31, count 0 2006.196.08:20:02.55#ibcon#first serial, iclass 31, count 0 2006.196.08:20:02.55#ibcon#enter sib2, iclass 31, count 0 2006.196.08:20:02.55#ibcon#flushed, iclass 31, count 0 2006.196.08:20:02.55#ibcon#about to write, iclass 31, count 0 2006.196.08:20:02.55#ibcon#wrote, iclass 31, count 0 2006.196.08:20:02.55#ibcon#about to read 3, iclass 31, count 0 2006.196.08:20:02.57#ibcon#read 3, iclass 31, count 0 2006.196.08:20:02.57#ibcon#about to read 4, iclass 31, count 0 2006.196.08:20:02.57#ibcon#read 4, iclass 31, count 0 2006.196.08:20:02.57#ibcon#about to read 5, iclass 31, count 0 2006.196.08:20:02.57#ibcon#read 5, iclass 31, count 0 2006.196.08:20:02.57#ibcon#about to read 6, iclass 31, count 0 2006.196.08:20:02.57#ibcon#read 6, iclass 31, count 0 2006.196.08:20:02.57#ibcon#end of sib2, iclass 31, count 0 2006.196.08:20:02.57#ibcon#*mode == 0, iclass 31, count 0 2006.196.08:20:02.57#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.196.08:20:02.57#ibcon#[27=USB\r\n] 2006.196.08:20:02.57#ibcon#*before write, iclass 31, count 0 2006.196.08:20:02.57#ibcon#enter sib2, iclass 31, count 0 2006.196.08:20:02.57#ibcon#flushed, iclass 31, count 0 2006.196.08:20:02.57#ibcon#about to write, iclass 31, count 0 2006.196.08:20:02.57#ibcon#wrote, iclass 31, count 0 2006.196.08:20:02.57#ibcon#about to read 3, iclass 31, count 0 2006.196.08:20:02.60#ibcon#read 3, iclass 31, count 0 2006.196.08:20:02.60#ibcon#about to read 4, iclass 31, count 0 2006.196.08:20:02.60#ibcon#read 4, iclass 31, count 0 2006.196.08:20:02.60#ibcon#about to read 5, iclass 31, count 0 2006.196.08:20:02.60#ibcon#read 5, iclass 31, count 0 2006.196.08:20:02.60#ibcon#about to read 6, iclass 31, count 0 2006.196.08:20:02.60#ibcon#read 6, iclass 31, count 0 2006.196.08:20:02.60#ibcon#end of sib2, iclass 31, count 0 2006.196.08:20:02.60#ibcon#*after write, iclass 31, count 0 2006.196.08:20:02.60#ibcon#*before return 0, iclass 31, count 0 2006.196.08:20:02.60#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.196.08:20:02.60#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.196.08:20:02.60#ibcon#about to clear, iclass 31 cls_cnt 0 2006.196.08:20:02.60#ibcon#cleared, iclass 31 cls_cnt 0 2006.196.08:20:02.60$vc4f8/vabw=wide 2006.196.08:20:02.60#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.196.08:20:02.60#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.196.08:20:02.60#ibcon#ireg 8 cls_cnt 0 2006.196.08:20:02.60#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:20:02.60#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:20:02.60#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:20:02.60#ibcon#enter wrdev, iclass 33, count 0 2006.196.08:20:02.60#ibcon#first serial, iclass 33, count 0 2006.196.08:20:02.60#ibcon#enter sib2, iclass 33, count 0 2006.196.08:20:02.60#ibcon#flushed, iclass 33, count 0 2006.196.08:20:02.60#ibcon#about to write, iclass 33, count 0 2006.196.08:20:02.60#ibcon#wrote, iclass 33, count 0 2006.196.08:20:02.60#ibcon#about to read 3, iclass 33, count 0 2006.196.08:20:02.62#ibcon#read 3, iclass 33, count 0 2006.196.08:20:02.62#ibcon#about to read 4, iclass 33, count 0 2006.196.08:20:02.62#ibcon#read 4, iclass 33, count 0 2006.196.08:20:02.62#ibcon#about to read 5, iclass 33, count 0 2006.196.08:20:02.62#ibcon#read 5, iclass 33, count 0 2006.196.08:20:02.62#ibcon#about to read 6, iclass 33, count 0 2006.196.08:20:02.62#ibcon#read 6, iclass 33, count 0 2006.196.08:20:02.62#ibcon#end of sib2, iclass 33, count 0 2006.196.08:20:02.62#ibcon#*mode == 0, iclass 33, count 0 2006.196.08:20:02.62#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.196.08:20:02.62#ibcon#[25=BW32\r\n] 2006.196.08:20:02.62#ibcon#*before write, iclass 33, count 0 2006.196.08:20:02.62#ibcon#enter sib2, iclass 33, count 0 2006.196.08:20:02.62#ibcon#flushed, iclass 33, count 0 2006.196.08:20:02.62#ibcon#about to write, iclass 33, count 0 2006.196.08:20:02.62#ibcon#wrote, iclass 33, count 0 2006.196.08:20:02.62#ibcon#about to read 3, iclass 33, count 0 2006.196.08:20:02.65#ibcon#read 3, iclass 33, count 0 2006.196.08:20:02.65#ibcon#about to read 4, iclass 33, count 0 2006.196.08:20:02.65#ibcon#read 4, iclass 33, count 0 2006.196.08:20:02.65#ibcon#about to read 5, iclass 33, count 0 2006.196.08:20:02.65#ibcon#read 5, iclass 33, count 0 2006.196.08:20:02.65#ibcon#about to read 6, iclass 33, count 0 2006.196.08:20:02.65#ibcon#read 6, iclass 33, count 0 2006.196.08:20:02.65#ibcon#end of sib2, iclass 33, count 0 2006.196.08:20:02.65#ibcon#*after write, iclass 33, count 0 2006.196.08:20:02.65#ibcon#*before return 0, iclass 33, count 0 2006.196.08:20:02.65#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:20:02.65#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:20:02.65#ibcon#about to clear, iclass 33 cls_cnt 0 2006.196.08:20:02.65#ibcon#cleared, iclass 33 cls_cnt 0 2006.196.08:20:02.65$vc4f8/vbbw=wide 2006.196.08:20:02.65#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.196.08:20:02.65#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.196.08:20:02.65#ibcon#ireg 8 cls_cnt 0 2006.196.08:20:02.65#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.196.08:20:02.72#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.196.08:20:02.72#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.196.08:20:02.72#ibcon#enter wrdev, iclass 35, count 0 2006.196.08:20:02.72#ibcon#first serial, iclass 35, count 0 2006.196.08:20:02.72#ibcon#enter sib2, iclass 35, count 0 2006.196.08:20:02.72#ibcon#flushed, iclass 35, count 0 2006.196.08:20:02.72#ibcon#about to write, iclass 35, count 0 2006.196.08:20:02.72#ibcon#wrote, iclass 35, count 0 2006.196.08:20:02.72#ibcon#about to read 3, iclass 35, count 0 2006.196.08:20:02.74#ibcon#read 3, iclass 35, count 0 2006.196.08:20:02.74#ibcon#about to read 4, iclass 35, count 0 2006.196.08:20:02.74#ibcon#read 4, iclass 35, count 0 2006.196.08:20:02.74#ibcon#about to read 5, iclass 35, count 0 2006.196.08:20:02.74#ibcon#read 5, iclass 35, count 0 2006.196.08:20:02.74#ibcon#about to read 6, iclass 35, count 0 2006.196.08:20:02.74#ibcon#read 6, iclass 35, count 0 2006.196.08:20:02.74#ibcon#end of sib2, iclass 35, count 0 2006.196.08:20:02.74#ibcon#*mode == 0, iclass 35, count 0 2006.196.08:20:02.74#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.196.08:20:02.74#ibcon#[27=BW32\r\n] 2006.196.08:20:02.74#ibcon#*before write, iclass 35, count 0 2006.196.08:20:02.74#ibcon#enter sib2, iclass 35, count 0 2006.196.08:20:02.74#ibcon#flushed, iclass 35, count 0 2006.196.08:20:02.74#ibcon#about to write, iclass 35, count 0 2006.196.08:20:02.74#ibcon#wrote, iclass 35, count 0 2006.196.08:20:02.74#ibcon#about to read 3, iclass 35, count 0 2006.196.08:20:02.77#ibcon#read 3, iclass 35, count 0 2006.196.08:20:02.77#ibcon#about to read 4, iclass 35, count 0 2006.196.08:20:02.77#ibcon#read 4, iclass 35, count 0 2006.196.08:20:02.77#ibcon#about to read 5, iclass 35, count 0 2006.196.08:20:02.77#ibcon#read 5, iclass 35, count 0 2006.196.08:20:02.77#ibcon#about to read 6, iclass 35, count 0 2006.196.08:20:02.77#ibcon#read 6, iclass 35, count 0 2006.196.08:20:02.77#ibcon#end of sib2, iclass 35, count 0 2006.196.08:20:02.77#ibcon#*after write, iclass 35, count 0 2006.196.08:20:02.77#ibcon#*before return 0, iclass 35, count 0 2006.196.08:20:02.77#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.196.08:20:02.77#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.196.08:20:02.77#ibcon#about to clear, iclass 35 cls_cnt 0 2006.196.08:20:02.77#ibcon#cleared, iclass 35 cls_cnt 0 2006.196.08:20:02.77$4f8m12a/ifd4f 2006.196.08:20:02.77$ifd4f/lo= 2006.196.08:20:02.77$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.196.08:20:02.77$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.196.08:20:02.77$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.196.08:20:02.77$ifd4f/patch= 2006.196.08:20:02.77$ifd4f/patch=lo1,a1,a2,a3,a4 2006.196.08:20:02.77$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.196.08:20:02.77$ifd4f/patch=lo3,a5,a6,a7,a8 2006.196.08:20:02.77$4f8m12a/"form=m,16.000,1:2 2006.196.08:20:02.77$4f8m12a/"tpicd 2006.196.08:20:02.77$4f8m12a/echo=off 2006.196.08:20:02.77$4f8m12a/xlog=off 2006.196.08:20:02.77:!2006.196.08:20:30 2006.196.08:20:10.14#trakl#Source acquired 2006.196.08:20:12.14#flagr#flagr/antenna,acquired 2006.196.08:20:30.00:preob 2006.196.08:20:31.14/onsource/TRACKING 2006.196.08:20:31.14:!2006.196.08:20:40 2006.196.08:20:40.00:data_valid=on 2006.196.08:20:40.00:midob 2006.196.08:20:40.14/onsource/TRACKING 2006.196.08:20:40.14/wx/28.93,1004.0,93 2006.196.08:20:40.29/cable/+6.3402E-03 2006.196.08:20:41.38/va/01,08,usb,yes,32,34 2006.196.08:20:41.38/va/02,07,usb,yes,32,34 2006.196.08:20:41.38/va/03,06,usb,yes,34,34 2006.196.08:20:41.38/va/04,07,usb,yes,33,35 2006.196.08:20:41.38/va/05,07,usb,yes,36,38 2006.196.08:20:41.38/va/06,06,usb,yes,35,34 2006.196.08:20:41.38/va/07,06,usb,yes,35,35 2006.196.08:20:41.38/va/08,07,usb,yes,33,33 2006.196.08:20:41.61/valo/01,532.99,yes,locked 2006.196.08:20:41.61/valo/02,572.99,yes,locked 2006.196.08:20:41.61/valo/03,672.99,yes,locked 2006.196.08:20:41.61/valo/04,832.99,yes,locked 2006.196.08:20:41.61/valo/05,652.99,yes,locked 2006.196.08:20:41.61/valo/06,772.99,yes,locked 2006.196.08:20:41.61/valo/07,832.99,yes,locked 2006.196.08:20:41.61/valo/08,852.99,yes,locked 2006.196.08:20:42.70/vb/01,04,usb,yes,27,28 2006.196.08:20:42.70/vb/02,04,usb,yes,29,33 2006.196.08:20:42.70/vb/03,04,usb,yes,26,29 2006.196.08:20:42.70/vb/04,04,usb,yes,26,26 2006.196.08:20:42.70/vb/05,04,usb,yes,25,29 2006.196.08:20:42.70/vb/06,04,usb,yes,26,29 2006.196.08:20:42.70/vb/07,04,usb,yes,28,28 2006.196.08:20:42.70/vb/08,04,usb,yes,26,29 2006.196.08:20:42.93/vblo/01,632.99,yes,locked 2006.196.08:20:42.93/vblo/02,640.99,yes,locked 2006.196.08:20:42.93/vblo/03,656.99,yes,locked 2006.196.08:20:42.93/vblo/04,712.99,yes,locked 2006.196.08:20:42.93/vblo/05,744.99,yes,locked 2006.196.08:20:42.93/vblo/06,752.99,yes,locked 2006.196.08:20:42.93/vblo/07,734.99,yes,locked 2006.196.08:20:42.93/vblo/08,744.99,yes,locked 2006.196.08:20:43.08/vabw/8 2006.196.08:20:43.23/vbbw/8 2006.196.08:20:43.32/xfe/off,on,15.0 2006.196.08:20:43.69/ifatt/23,28,28,28 2006.196.08:20:44.06/fmout-gps/S +3.33E-07 2006.196.08:20:44.13:!2006.196.08:21:40 2006.196.08:21:40.00:data_valid=off 2006.196.08:21:40.00:postob 2006.196.08:21:40.13/cable/+6.3383E-03 2006.196.08:21:40.13/wx/28.90,1004.1,94 2006.196.08:21:41.06/fmout-gps/S +3.33E-07 2006.196.08:21:41.06:scan_name=196-0822,k06196,60 2006.196.08:21:41.06:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.196.08:21:41.14#flagr#flagr/antenna,new-source 2006.196.08:21:42.14:checkk5 2006.196.08:21:42.52/chk_autoobs//k5ts1/ autoobs is running! 2006.196.08:21:42.89/chk_autoobs//k5ts2/ autoobs is running! 2006.196.08:21:43.27/chk_autoobs//k5ts3/ autoobs is running! 2006.196.08:21:43.64/chk_autoobs//k5ts4/ autoobs is running! 2006.196.08:21:44.01/chk_obsdata//k5ts1/T1960820??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.08:21:44.38/chk_obsdata//k5ts2/T1960820??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.08:21:44.75/chk_obsdata//k5ts3/T1960820??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.08:21:45.12/chk_obsdata//k5ts4/T1960820??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.08:21:45.81/k5log//k5ts1_log_newline 2006.196.08:21:46.51/k5log//k5ts2_log_newline 2006.196.08:21:47.21/k5log//k5ts3_log_newline 2006.196.08:21:47.91/k5log//k5ts4_log_newline 2006.196.08:21:47.94/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.196.08:21:47.94:4f8m12a=3 2006.196.08:21:47.94$4f8m12a/echo=on 2006.196.08:21:47.94$4f8m12a/pcalon 2006.196.08:21:47.94$pcalon/"no phase cal control is implemented here 2006.196.08:21:47.94$4f8m12a/"tpicd=stop 2006.196.08:21:47.94$4f8m12a/vc4f8 2006.196.08:21:47.94$vc4f8/valo=1,532.99 2006.196.08:21:47.94#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.196.08:21:47.94#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.196.08:21:47.94#ibcon#ireg 17 cls_cnt 0 2006.196.08:21:47.94#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.196.08:21:47.94#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.196.08:21:47.94#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.196.08:21:47.94#ibcon#enter wrdev, iclass 4, count 0 2006.196.08:21:47.94#ibcon#first serial, iclass 4, count 0 2006.196.08:21:47.94#ibcon#enter sib2, iclass 4, count 0 2006.196.08:21:47.94#ibcon#flushed, iclass 4, count 0 2006.196.08:21:47.94#ibcon#about to write, iclass 4, count 0 2006.196.08:21:47.94#ibcon#wrote, iclass 4, count 0 2006.196.08:21:47.94#ibcon#about to read 3, iclass 4, count 0 2006.196.08:21:47.98#ibcon#read 3, iclass 4, count 0 2006.196.08:21:47.98#ibcon#about to read 4, iclass 4, count 0 2006.196.08:21:47.98#ibcon#read 4, iclass 4, count 0 2006.196.08:21:47.98#ibcon#about to read 5, iclass 4, count 0 2006.196.08:21:47.98#ibcon#read 5, iclass 4, count 0 2006.196.08:21:47.98#ibcon#about to read 6, iclass 4, count 0 2006.196.08:21:47.98#ibcon#read 6, iclass 4, count 0 2006.196.08:21:47.98#ibcon#end of sib2, iclass 4, count 0 2006.196.08:21:47.98#ibcon#*mode == 0, iclass 4, count 0 2006.196.08:21:47.98#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.196.08:21:47.98#ibcon#[26=FRQ=01,532.99\r\n] 2006.196.08:21:47.98#ibcon#*before write, iclass 4, count 0 2006.196.08:21:47.98#ibcon#enter sib2, iclass 4, count 0 2006.196.08:21:47.98#ibcon#flushed, iclass 4, count 0 2006.196.08:21:47.98#ibcon#about to write, iclass 4, count 0 2006.196.08:21:47.98#ibcon#wrote, iclass 4, count 0 2006.196.08:21:47.98#ibcon#about to read 3, iclass 4, count 0 2006.196.08:21:48.03#ibcon#read 3, iclass 4, count 0 2006.196.08:21:48.03#ibcon#about to read 4, iclass 4, count 0 2006.196.08:21:48.03#ibcon#read 4, iclass 4, count 0 2006.196.08:21:48.03#ibcon#about to read 5, iclass 4, count 0 2006.196.08:21:48.03#ibcon#read 5, iclass 4, count 0 2006.196.08:21:48.03#ibcon#about to read 6, iclass 4, count 0 2006.196.08:21:48.03#ibcon#read 6, iclass 4, count 0 2006.196.08:21:48.03#ibcon#end of sib2, iclass 4, count 0 2006.196.08:21:48.03#ibcon#*after write, iclass 4, count 0 2006.196.08:21:48.03#ibcon#*before return 0, iclass 4, count 0 2006.196.08:21:48.03#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.196.08:21:48.03#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.196.08:21:48.03#ibcon#about to clear, iclass 4 cls_cnt 0 2006.196.08:21:48.03#ibcon#cleared, iclass 4 cls_cnt 0 2006.196.08:21:48.03$vc4f8/va=1,8 2006.196.08:21:48.03#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.196.08:21:48.03#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.196.08:21:48.03#ibcon#ireg 11 cls_cnt 2 2006.196.08:21:48.03#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.196.08:21:48.03#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.196.08:21:48.03#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.196.08:21:48.03#ibcon#enter wrdev, iclass 6, count 2 2006.196.08:21:48.03#ibcon#first serial, iclass 6, count 2 2006.196.08:21:48.03#ibcon#enter sib2, iclass 6, count 2 2006.196.08:21:48.03#ibcon#flushed, iclass 6, count 2 2006.196.08:21:48.03#ibcon#about to write, iclass 6, count 2 2006.196.08:21:48.03#ibcon#wrote, iclass 6, count 2 2006.196.08:21:48.03#ibcon#about to read 3, iclass 6, count 2 2006.196.08:21:48.05#ibcon#read 3, iclass 6, count 2 2006.196.08:21:48.05#ibcon#about to read 4, iclass 6, count 2 2006.196.08:21:48.05#ibcon#read 4, iclass 6, count 2 2006.196.08:21:48.05#ibcon#about to read 5, iclass 6, count 2 2006.196.08:21:48.05#ibcon#read 5, iclass 6, count 2 2006.196.08:21:48.05#ibcon#about to read 6, iclass 6, count 2 2006.196.08:21:48.05#ibcon#read 6, iclass 6, count 2 2006.196.08:21:48.05#ibcon#end of sib2, iclass 6, count 2 2006.196.08:21:48.05#ibcon#*mode == 0, iclass 6, count 2 2006.196.08:21:48.05#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.196.08:21:48.05#ibcon#[25=AT01-08\r\n] 2006.196.08:21:48.05#ibcon#*before write, iclass 6, count 2 2006.196.08:21:48.05#ibcon#enter sib2, iclass 6, count 2 2006.196.08:21:48.05#ibcon#flushed, iclass 6, count 2 2006.196.08:21:48.05#ibcon#about to write, iclass 6, count 2 2006.196.08:21:48.05#ibcon#wrote, iclass 6, count 2 2006.196.08:21:48.05#ibcon#about to read 3, iclass 6, count 2 2006.196.08:21:48.08#ibcon#read 3, iclass 6, count 2 2006.196.08:21:48.08#ibcon#about to read 4, iclass 6, count 2 2006.196.08:21:48.08#ibcon#read 4, iclass 6, count 2 2006.196.08:21:48.08#ibcon#about to read 5, iclass 6, count 2 2006.196.08:21:48.08#ibcon#read 5, iclass 6, count 2 2006.196.08:21:48.08#ibcon#about to read 6, iclass 6, count 2 2006.196.08:21:48.08#ibcon#read 6, iclass 6, count 2 2006.196.08:21:48.08#ibcon#end of sib2, iclass 6, count 2 2006.196.08:21:48.08#ibcon#*after write, iclass 6, count 2 2006.196.08:21:48.08#ibcon#*before return 0, iclass 6, count 2 2006.196.08:21:48.08#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.196.08:21:48.08#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.196.08:21:48.08#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.196.08:21:48.08#ibcon#ireg 7 cls_cnt 0 2006.196.08:21:48.08#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.196.08:21:48.20#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.196.08:21:48.20#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.196.08:21:48.20#ibcon#enter wrdev, iclass 6, count 0 2006.196.08:21:48.20#ibcon#first serial, iclass 6, count 0 2006.196.08:21:48.20#ibcon#enter sib2, iclass 6, count 0 2006.196.08:21:48.20#ibcon#flushed, iclass 6, count 0 2006.196.08:21:48.20#ibcon#about to write, iclass 6, count 0 2006.196.08:21:48.20#ibcon#wrote, iclass 6, count 0 2006.196.08:21:48.20#ibcon#about to read 3, iclass 6, count 0 2006.196.08:21:48.22#ibcon#read 3, iclass 6, count 0 2006.196.08:21:48.22#ibcon#about to read 4, iclass 6, count 0 2006.196.08:21:48.22#ibcon#read 4, iclass 6, count 0 2006.196.08:21:48.22#ibcon#about to read 5, iclass 6, count 0 2006.196.08:21:48.22#ibcon#read 5, iclass 6, count 0 2006.196.08:21:48.22#ibcon#about to read 6, iclass 6, count 0 2006.196.08:21:48.22#ibcon#read 6, iclass 6, count 0 2006.196.08:21:48.22#ibcon#end of sib2, iclass 6, count 0 2006.196.08:21:48.22#ibcon#*mode == 0, iclass 6, count 0 2006.196.08:21:48.22#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.196.08:21:48.22#ibcon#[25=USB\r\n] 2006.196.08:21:48.22#ibcon#*before write, iclass 6, count 0 2006.196.08:21:48.22#ibcon#enter sib2, iclass 6, count 0 2006.196.08:21:48.22#ibcon#flushed, iclass 6, count 0 2006.196.08:21:48.22#ibcon#about to write, iclass 6, count 0 2006.196.08:21:48.22#ibcon#wrote, iclass 6, count 0 2006.196.08:21:48.22#ibcon#about to read 3, iclass 6, count 0 2006.196.08:21:48.25#ibcon#read 3, iclass 6, count 0 2006.196.08:21:48.25#ibcon#about to read 4, iclass 6, count 0 2006.196.08:21:48.25#ibcon#read 4, iclass 6, count 0 2006.196.08:21:48.25#ibcon#about to read 5, iclass 6, count 0 2006.196.08:21:48.25#ibcon#read 5, iclass 6, count 0 2006.196.08:21:48.25#ibcon#about to read 6, iclass 6, count 0 2006.196.08:21:48.25#ibcon#read 6, iclass 6, count 0 2006.196.08:21:48.25#ibcon#end of sib2, iclass 6, count 0 2006.196.08:21:48.25#ibcon#*after write, iclass 6, count 0 2006.196.08:21:48.25#ibcon#*before return 0, iclass 6, count 0 2006.196.08:21:48.25#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.196.08:21:48.25#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.196.08:21:48.25#ibcon#about to clear, iclass 6 cls_cnt 0 2006.196.08:21:48.25#ibcon#cleared, iclass 6 cls_cnt 0 2006.196.08:21:48.25$vc4f8/valo=2,572.99 2006.196.08:21:48.25#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.196.08:21:48.25#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.196.08:21:48.25#ibcon#ireg 17 cls_cnt 0 2006.196.08:21:48.25#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.196.08:21:48.25#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.196.08:21:48.25#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.196.08:21:48.25#ibcon#enter wrdev, iclass 10, count 0 2006.196.08:21:48.25#ibcon#first serial, iclass 10, count 0 2006.196.08:21:48.25#ibcon#enter sib2, iclass 10, count 0 2006.196.08:21:48.25#ibcon#flushed, iclass 10, count 0 2006.196.08:21:48.25#ibcon#about to write, iclass 10, count 0 2006.196.08:21:48.25#ibcon#wrote, iclass 10, count 0 2006.196.08:21:48.25#ibcon#about to read 3, iclass 10, count 0 2006.196.08:21:48.27#ibcon#read 3, iclass 10, count 0 2006.196.08:21:48.27#ibcon#about to read 4, iclass 10, count 0 2006.196.08:21:48.27#ibcon#read 4, iclass 10, count 0 2006.196.08:21:48.27#ibcon#about to read 5, iclass 10, count 0 2006.196.08:21:48.27#ibcon#read 5, iclass 10, count 0 2006.196.08:21:48.27#ibcon#about to read 6, iclass 10, count 0 2006.196.08:21:48.27#ibcon#read 6, iclass 10, count 0 2006.196.08:21:48.27#ibcon#end of sib2, iclass 10, count 0 2006.196.08:21:48.27#ibcon#*mode == 0, iclass 10, count 0 2006.196.08:21:48.27#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.196.08:21:48.27#ibcon#[26=FRQ=02,572.99\r\n] 2006.196.08:21:48.27#ibcon#*before write, iclass 10, count 0 2006.196.08:21:48.27#ibcon#enter sib2, iclass 10, count 0 2006.196.08:21:48.27#ibcon#flushed, iclass 10, count 0 2006.196.08:21:48.27#ibcon#about to write, iclass 10, count 0 2006.196.08:21:48.27#ibcon#wrote, iclass 10, count 0 2006.196.08:21:48.27#ibcon#about to read 3, iclass 10, count 0 2006.196.08:21:48.31#ibcon#read 3, iclass 10, count 0 2006.196.08:21:48.31#ibcon#about to read 4, iclass 10, count 0 2006.196.08:21:48.31#ibcon#read 4, iclass 10, count 0 2006.196.08:21:48.31#ibcon#about to read 5, iclass 10, count 0 2006.196.08:21:48.31#ibcon#read 5, iclass 10, count 0 2006.196.08:21:48.31#ibcon#about to read 6, iclass 10, count 0 2006.196.08:21:48.31#ibcon#read 6, iclass 10, count 0 2006.196.08:21:48.31#ibcon#end of sib2, iclass 10, count 0 2006.196.08:21:48.31#ibcon#*after write, iclass 10, count 0 2006.196.08:21:48.31#ibcon#*before return 0, iclass 10, count 0 2006.196.08:21:48.31#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.196.08:21:48.31#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.196.08:21:48.31#ibcon#about to clear, iclass 10 cls_cnt 0 2006.196.08:21:48.31#ibcon#cleared, iclass 10 cls_cnt 0 2006.196.08:21:48.31$vc4f8/va=2,7 2006.196.08:21:48.31#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.196.08:21:48.31#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.196.08:21:48.31#ibcon#ireg 11 cls_cnt 2 2006.196.08:21:48.31#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.196.08:21:48.37#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.196.08:21:48.37#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.196.08:21:48.37#ibcon#enter wrdev, iclass 12, count 2 2006.196.08:21:48.37#ibcon#first serial, iclass 12, count 2 2006.196.08:21:48.37#ibcon#enter sib2, iclass 12, count 2 2006.196.08:21:48.37#ibcon#flushed, iclass 12, count 2 2006.196.08:21:48.37#ibcon#about to write, iclass 12, count 2 2006.196.08:21:48.37#ibcon#wrote, iclass 12, count 2 2006.196.08:21:48.37#ibcon#about to read 3, iclass 12, count 2 2006.196.08:21:48.39#ibcon#read 3, iclass 12, count 2 2006.196.08:21:48.39#ibcon#about to read 4, iclass 12, count 2 2006.196.08:21:48.39#ibcon#read 4, iclass 12, count 2 2006.196.08:21:48.39#ibcon#about to read 5, iclass 12, count 2 2006.196.08:21:48.39#ibcon#read 5, iclass 12, count 2 2006.196.08:21:48.39#ibcon#about to read 6, iclass 12, count 2 2006.196.08:21:48.39#ibcon#read 6, iclass 12, count 2 2006.196.08:21:48.39#ibcon#end of sib2, iclass 12, count 2 2006.196.08:21:48.39#ibcon#*mode == 0, iclass 12, count 2 2006.196.08:21:48.39#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.196.08:21:48.39#ibcon#[25=AT02-07\r\n] 2006.196.08:21:48.39#ibcon#*before write, iclass 12, count 2 2006.196.08:21:48.39#ibcon#enter sib2, iclass 12, count 2 2006.196.08:21:48.39#ibcon#flushed, iclass 12, count 2 2006.196.08:21:48.39#ibcon#about to write, iclass 12, count 2 2006.196.08:21:48.39#ibcon#wrote, iclass 12, count 2 2006.196.08:21:48.39#ibcon#about to read 3, iclass 12, count 2 2006.196.08:21:48.42#ibcon#read 3, iclass 12, count 2 2006.196.08:21:48.42#ibcon#about to read 4, iclass 12, count 2 2006.196.08:21:48.42#ibcon#read 4, iclass 12, count 2 2006.196.08:21:48.42#ibcon#about to read 5, iclass 12, count 2 2006.196.08:21:48.42#ibcon#read 5, iclass 12, count 2 2006.196.08:21:48.42#ibcon#about to read 6, iclass 12, count 2 2006.196.08:21:48.42#ibcon#read 6, iclass 12, count 2 2006.196.08:21:48.42#ibcon#end of sib2, iclass 12, count 2 2006.196.08:21:48.42#ibcon#*after write, iclass 12, count 2 2006.196.08:21:48.42#ibcon#*before return 0, iclass 12, count 2 2006.196.08:21:48.42#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.196.08:21:48.42#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.196.08:21:48.42#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.196.08:21:48.42#ibcon#ireg 7 cls_cnt 0 2006.196.08:21:48.42#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.196.08:21:48.54#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.196.08:21:48.54#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.196.08:21:48.54#ibcon#enter wrdev, iclass 12, count 0 2006.196.08:21:48.54#ibcon#first serial, iclass 12, count 0 2006.196.08:21:48.54#ibcon#enter sib2, iclass 12, count 0 2006.196.08:21:48.54#ibcon#flushed, iclass 12, count 0 2006.196.08:21:48.54#ibcon#about to write, iclass 12, count 0 2006.196.08:21:48.54#ibcon#wrote, iclass 12, count 0 2006.196.08:21:48.54#ibcon#about to read 3, iclass 12, count 0 2006.196.08:21:48.56#ibcon#read 3, iclass 12, count 0 2006.196.08:21:48.56#ibcon#about to read 4, iclass 12, count 0 2006.196.08:21:48.56#ibcon#read 4, iclass 12, count 0 2006.196.08:21:48.56#ibcon#about to read 5, iclass 12, count 0 2006.196.08:21:48.56#ibcon#read 5, iclass 12, count 0 2006.196.08:21:48.56#ibcon#about to read 6, iclass 12, count 0 2006.196.08:21:48.56#ibcon#read 6, iclass 12, count 0 2006.196.08:21:48.56#ibcon#end of sib2, iclass 12, count 0 2006.196.08:21:48.56#ibcon#*mode == 0, iclass 12, count 0 2006.196.08:21:48.56#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.196.08:21:48.56#ibcon#[25=USB\r\n] 2006.196.08:21:48.56#ibcon#*before write, iclass 12, count 0 2006.196.08:21:48.56#ibcon#enter sib2, iclass 12, count 0 2006.196.08:21:48.56#ibcon#flushed, iclass 12, count 0 2006.196.08:21:48.56#ibcon#about to write, iclass 12, count 0 2006.196.08:21:48.56#ibcon#wrote, iclass 12, count 0 2006.196.08:21:48.56#ibcon#about to read 3, iclass 12, count 0 2006.196.08:21:48.59#ibcon#read 3, iclass 12, count 0 2006.196.08:21:48.59#ibcon#about to read 4, iclass 12, count 0 2006.196.08:21:48.59#ibcon#read 4, iclass 12, count 0 2006.196.08:21:48.59#ibcon#about to read 5, iclass 12, count 0 2006.196.08:21:48.59#ibcon#read 5, iclass 12, count 0 2006.196.08:21:48.59#ibcon#about to read 6, iclass 12, count 0 2006.196.08:21:48.59#ibcon#read 6, iclass 12, count 0 2006.196.08:21:48.59#ibcon#end of sib2, iclass 12, count 0 2006.196.08:21:48.59#ibcon#*after write, iclass 12, count 0 2006.196.08:21:48.59#ibcon#*before return 0, iclass 12, count 0 2006.196.08:21:48.59#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.196.08:21:48.59#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.196.08:21:48.59#ibcon#about to clear, iclass 12 cls_cnt 0 2006.196.08:21:48.59#ibcon#cleared, iclass 12 cls_cnt 0 2006.196.08:21:48.59$vc4f8/valo=3,672.99 2006.196.08:21:48.59#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.196.08:21:48.59#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.196.08:21:48.59#ibcon#ireg 17 cls_cnt 0 2006.196.08:21:48.59#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.196.08:21:48.59#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.196.08:21:48.59#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.196.08:21:48.59#ibcon#enter wrdev, iclass 14, count 0 2006.196.08:21:48.59#ibcon#first serial, iclass 14, count 0 2006.196.08:21:48.59#ibcon#enter sib2, iclass 14, count 0 2006.196.08:21:48.59#ibcon#flushed, iclass 14, count 0 2006.196.08:21:48.59#ibcon#about to write, iclass 14, count 0 2006.196.08:21:48.59#ibcon#wrote, iclass 14, count 0 2006.196.08:21:48.59#ibcon#about to read 3, iclass 14, count 0 2006.196.08:21:48.61#ibcon#read 3, iclass 14, count 0 2006.196.08:21:48.61#ibcon#about to read 4, iclass 14, count 0 2006.196.08:21:48.61#ibcon#read 4, iclass 14, count 0 2006.196.08:21:48.61#ibcon#about to read 5, iclass 14, count 0 2006.196.08:21:48.61#ibcon#read 5, iclass 14, count 0 2006.196.08:21:48.61#ibcon#about to read 6, iclass 14, count 0 2006.196.08:21:48.61#ibcon#read 6, iclass 14, count 0 2006.196.08:21:48.61#ibcon#end of sib2, iclass 14, count 0 2006.196.08:21:48.61#ibcon#*mode == 0, iclass 14, count 0 2006.196.08:21:48.61#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.196.08:21:48.61#ibcon#[26=FRQ=03,672.99\r\n] 2006.196.08:21:48.61#ibcon#*before write, iclass 14, count 0 2006.196.08:21:48.61#ibcon#enter sib2, iclass 14, count 0 2006.196.08:21:48.61#ibcon#flushed, iclass 14, count 0 2006.196.08:21:48.61#ibcon#about to write, iclass 14, count 0 2006.196.08:21:48.61#ibcon#wrote, iclass 14, count 0 2006.196.08:21:48.61#ibcon#about to read 3, iclass 14, count 0 2006.196.08:21:48.65#ibcon#read 3, iclass 14, count 0 2006.196.08:21:48.65#ibcon#about to read 4, iclass 14, count 0 2006.196.08:21:48.65#ibcon#read 4, iclass 14, count 0 2006.196.08:21:48.65#ibcon#about to read 5, iclass 14, count 0 2006.196.08:21:48.65#ibcon#read 5, iclass 14, count 0 2006.196.08:21:48.65#ibcon#about to read 6, iclass 14, count 0 2006.196.08:21:48.65#ibcon#read 6, iclass 14, count 0 2006.196.08:21:48.65#ibcon#end of sib2, iclass 14, count 0 2006.196.08:21:48.65#ibcon#*after write, iclass 14, count 0 2006.196.08:21:48.65#ibcon#*before return 0, iclass 14, count 0 2006.196.08:21:48.65#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.196.08:21:48.65#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.196.08:21:48.65#ibcon#about to clear, iclass 14 cls_cnt 0 2006.196.08:21:48.65#ibcon#cleared, iclass 14 cls_cnt 0 2006.196.08:21:48.65$vc4f8/va=3,6 2006.196.08:21:48.65#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.196.08:21:48.65#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.196.08:21:48.65#ibcon#ireg 11 cls_cnt 2 2006.196.08:21:48.65#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.196.08:21:48.71#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.196.08:21:48.71#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.196.08:21:48.71#ibcon#enter wrdev, iclass 16, count 2 2006.196.08:21:48.71#ibcon#first serial, iclass 16, count 2 2006.196.08:21:48.71#ibcon#enter sib2, iclass 16, count 2 2006.196.08:21:48.71#ibcon#flushed, iclass 16, count 2 2006.196.08:21:48.71#ibcon#about to write, iclass 16, count 2 2006.196.08:21:48.71#ibcon#wrote, iclass 16, count 2 2006.196.08:21:48.71#ibcon#about to read 3, iclass 16, count 2 2006.196.08:21:48.73#ibcon#read 3, iclass 16, count 2 2006.196.08:21:48.73#ibcon#about to read 4, iclass 16, count 2 2006.196.08:21:48.73#ibcon#read 4, iclass 16, count 2 2006.196.08:21:48.73#ibcon#about to read 5, iclass 16, count 2 2006.196.08:21:48.73#ibcon#read 5, iclass 16, count 2 2006.196.08:21:48.73#ibcon#about to read 6, iclass 16, count 2 2006.196.08:21:48.73#ibcon#read 6, iclass 16, count 2 2006.196.08:21:48.73#ibcon#end of sib2, iclass 16, count 2 2006.196.08:21:48.73#ibcon#*mode == 0, iclass 16, count 2 2006.196.08:21:48.73#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.196.08:21:48.73#ibcon#[25=AT03-06\r\n] 2006.196.08:21:48.73#ibcon#*before write, iclass 16, count 2 2006.196.08:21:48.73#ibcon#enter sib2, iclass 16, count 2 2006.196.08:21:48.73#ibcon#flushed, iclass 16, count 2 2006.196.08:21:48.73#ibcon#about to write, iclass 16, count 2 2006.196.08:21:48.73#ibcon#wrote, iclass 16, count 2 2006.196.08:21:48.73#ibcon#about to read 3, iclass 16, count 2 2006.196.08:21:48.76#ibcon#read 3, iclass 16, count 2 2006.196.08:21:48.76#ibcon#about to read 4, iclass 16, count 2 2006.196.08:21:48.76#ibcon#read 4, iclass 16, count 2 2006.196.08:21:48.76#ibcon#about to read 5, iclass 16, count 2 2006.196.08:21:48.76#ibcon#read 5, iclass 16, count 2 2006.196.08:21:48.76#ibcon#about to read 6, iclass 16, count 2 2006.196.08:21:48.76#ibcon#read 6, iclass 16, count 2 2006.196.08:21:48.76#ibcon#end of sib2, iclass 16, count 2 2006.196.08:21:48.76#ibcon#*after write, iclass 16, count 2 2006.196.08:21:48.76#ibcon#*before return 0, iclass 16, count 2 2006.196.08:21:48.76#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.196.08:21:48.76#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.196.08:21:48.76#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.196.08:21:48.76#ibcon#ireg 7 cls_cnt 0 2006.196.08:21:48.76#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.196.08:21:48.88#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.196.08:21:48.88#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.196.08:21:48.88#ibcon#enter wrdev, iclass 16, count 0 2006.196.08:21:48.88#ibcon#first serial, iclass 16, count 0 2006.196.08:21:48.88#ibcon#enter sib2, iclass 16, count 0 2006.196.08:21:48.88#ibcon#flushed, iclass 16, count 0 2006.196.08:21:48.88#ibcon#about to write, iclass 16, count 0 2006.196.08:21:48.88#ibcon#wrote, iclass 16, count 0 2006.196.08:21:48.88#ibcon#about to read 3, iclass 16, count 0 2006.196.08:21:48.90#ibcon#read 3, iclass 16, count 0 2006.196.08:21:48.90#ibcon#about to read 4, iclass 16, count 0 2006.196.08:21:48.90#ibcon#read 4, iclass 16, count 0 2006.196.08:21:48.90#ibcon#about to read 5, iclass 16, count 0 2006.196.08:21:48.90#ibcon#read 5, iclass 16, count 0 2006.196.08:21:48.90#ibcon#about to read 6, iclass 16, count 0 2006.196.08:21:48.90#ibcon#read 6, iclass 16, count 0 2006.196.08:21:48.90#ibcon#end of sib2, iclass 16, count 0 2006.196.08:21:48.90#ibcon#*mode == 0, iclass 16, count 0 2006.196.08:21:48.90#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.196.08:21:48.90#ibcon#[25=USB\r\n] 2006.196.08:21:48.90#ibcon#*before write, iclass 16, count 0 2006.196.08:21:48.90#ibcon#enter sib2, iclass 16, count 0 2006.196.08:21:48.90#ibcon#flushed, iclass 16, count 0 2006.196.08:21:48.90#ibcon#about to write, iclass 16, count 0 2006.196.08:21:48.90#ibcon#wrote, iclass 16, count 0 2006.196.08:21:48.90#ibcon#about to read 3, iclass 16, count 0 2006.196.08:21:48.93#ibcon#read 3, iclass 16, count 0 2006.196.08:21:48.93#ibcon#about to read 4, iclass 16, count 0 2006.196.08:21:48.93#ibcon#read 4, iclass 16, count 0 2006.196.08:21:48.93#ibcon#about to read 5, iclass 16, count 0 2006.196.08:21:48.93#ibcon#read 5, iclass 16, count 0 2006.196.08:21:48.93#ibcon#about to read 6, iclass 16, count 0 2006.196.08:21:48.93#ibcon#read 6, iclass 16, count 0 2006.196.08:21:48.93#ibcon#end of sib2, iclass 16, count 0 2006.196.08:21:48.93#ibcon#*after write, iclass 16, count 0 2006.196.08:21:48.93#ibcon#*before return 0, iclass 16, count 0 2006.196.08:21:48.93#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.196.08:21:48.93#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.196.08:21:48.93#ibcon#about to clear, iclass 16 cls_cnt 0 2006.196.08:21:48.93#ibcon#cleared, iclass 16 cls_cnt 0 2006.196.08:21:48.93$vc4f8/valo=4,832.99 2006.196.08:21:48.93#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.196.08:21:48.93#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.196.08:21:48.93#ibcon#ireg 17 cls_cnt 0 2006.196.08:21:48.93#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.196.08:21:48.93#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.196.08:21:48.93#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.196.08:21:48.93#ibcon#enter wrdev, iclass 18, count 0 2006.196.08:21:48.93#ibcon#first serial, iclass 18, count 0 2006.196.08:21:48.93#ibcon#enter sib2, iclass 18, count 0 2006.196.08:21:48.93#ibcon#flushed, iclass 18, count 0 2006.196.08:21:48.93#ibcon#about to write, iclass 18, count 0 2006.196.08:21:48.93#ibcon#wrote, iclass 18, count 0 2006.196.08:21:48.93#ibcon#about to read 3, iclass 18, count 0 2006.196.08:21:48.95#ibcon#read 3, iclass 18, count 0 2006.196.08:21:48.95#ibcon#about to read 4, iclass 18, count 0 2006.196.08:21:48.95#ibcon#read 4, iclass 18, count 0 2006.196.08:21:48.95#ibcon#about to read 5, iclass 18, count 0 2006.196.08:21:48.95#ibcon#read 5, iclass 18, count 0 2006.196.08:21:48.95#ibcon#about to read 6, iclass 18, count 0 2006.196.08:21:48.95#ibcon#read 6, iclass 18, count 0 2006.196.08:21:48.95#ibcon#end of sib2, iclass 18, count 0 2006.196.08:21:48.95#ibcon#*mode == 0, iclass 18, count 0 2006.196.08:21:48.95#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.196.08:21:48.95#ibcon#[26=FRQ=04,832.99\r\n] 2006.196.08:21:48.95#ibcon#*before write, iclass 18, count 0 2006.196.08:21:48.95#ibcon#enter sib2, iclass 18, count 0 2006.196.08:21:48.95#ibcon#flushed, iclass 18, count 0 2006.196.08:21:48.95#ibcon#about to write, iclass 18, count 0 2006.196.08:21:48.95#ibcon#wrote, iclass 18, count 0 2006.196.08:21:48.95#ibcon#about to read 3, iclass 18, count 0 2006.196.08:21:48.99#ibcon#read 3, iclass 18, count 0 2006.196.08:21:48.99#ibcon#about to read 4, iclass 18, count 0 2006.196.08:21:48.99#ibcon#read 4, iclass 18, count 0 2006.196.08:21:48.99#ibcon#about to read 5, iclass 18, count 0 2006.196.08:21:48.99#ibcon#read 5, iclass 18, count 0 2006.196.08:21:48.99#ibcon#about to read 6, iclass 18, count 0 2006.196.08:21:48.99#ibcon#read 6, iclass 18, count 0 2006.196.08:21:48.99#ibcon#end of sib2, iclass 18, count 0 2006.196.08:21:48.99#ibcon#*after write, iclass 18, count 0 2006.196.08:21:48.99#ibcon#*before return 0, iclass 18, count 0 2006.196.08:21:48.99#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.196.08:21:48.99#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.196.08:21:48.99#ibcon#about to clear, iclass 18 cls_cnt 0 2006.196.08:21:48.99#ibcon#cleared, iclass 18 cls_cnt 0 2006.196.08:21:48.99$vc4f8/va=4,7 2006.196.08:21:48.99#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.196.08:21:48.99#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.196.08:21:48.99#ibcon#ireg 11 cls_cnt 2 2006.196.08:21:48.99#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.196.08:21:49.05#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.196.08:21:49.05#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.196.08:21:49.05#ibcon#enter wrdev, iclass 20, count 2 2006.196.08:21:49.05#ibcon#first serial, iclass 20, count 2 2006.196.08:21:49.05#ibcon#enter sib2, iclass 20, count 2 2006.196.08:21:49.05#ibcon#flushed, iclass 20, count 2 2006.196.08:21:49.05#ibcon#about to write, iclass 20, count 2 2006.196.08:21:49.05#ibcon#wrote, iclass 20, count 2 2006.196.08:21:49.05#ibcon#about to read 3, iclass 20, count 2 2006.196.08:21:49.07#ibcon#read 3, iclass 20, count 2 2006.196.08:21:49.07#ibcon#about to read 4, iclass 20, count 2 2006.196.08:21:49.07#ibcon#read 4, iclass 20, count 2 2006.196.08:21:49.07#ibcon#about to read 5, iclass 20, count 2 2006.196.08:21:49.07#ibcon#read 5, iclass 20, count 2 2006.196.08:21:49.07#ibcon#about to read 6, iclass 20, count 2 2006.196.08:21:49.07#ibcon#read 6, iclass 20, count 2 2006.196.08:21:49.07#ibcon#end of sib2, iclass 20, count 2 2006.196.08:21:49.07#ibcon#*mode == 0, iclass 20, count 2 2006.196.08:21:49.07#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.196.08:21:49.07#ibcon#[25=AT04-07\r\n] 2006.196.08:21:49.07#ibcon#*before write, iclass 20, count 2 2006.196.08:21:49.07#ibcon#enter sib2, iclass 20, count 2 2006.196.08:21:49.07#ibcon#flushed, iclass 20, count 2 2006.196.08:21:49.07#ibcon#about to write, iclass 20, count 2 2006.196.08:21:49.07#ibcon#wrote, iclass 20, count 2 2006.196.08:21:49.07#ibcon#about to read 3, iclass 20, count 2 2006.196.08:21:49.10#ibcon#read 3, iclass 20, count 2 2006.196.08:21:49.10#ibcon#about to read 4, iclass 20, count 2 2006.196.08:21:49.10#ibcon#read 4, iclass 20, count 2 2006.196.08:21:49.10#ibcon#about to read 5, iclass 20, count 2 2006.196.08:21:49.10#ibcon#read 5, iclass 20, count 2 2006.196.08:21:49.10#ibcon#about to read 6, iclass 20, count 2 2006.196.08:21:49.10#ibcon#read 6, iclass 20, count 2 2006.196.08:21:49.10#ibcon#end of sib2, iclass 20, count 2 2006.196.08:21:49.10#ibcon#*after write, iclass 20, count 2 2006.196.08:21:49.10#ibcon#*before return 0, iclass 20, count 2 2006.196.08:21:49.10#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.196.08:21:49.10#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.196.08:21:49.10#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.196.08:21:49.10#ibcon#ireg 7 cls_cnt 0 2006.196.08:21:49.10#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.196.08:21:49.22#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.196.08:21:49.22#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.196.08:21:49.22#ibcon#enter wrdev, iclass 20, count 0 2006.196.08:21:49.22#ibcon#first serial, iclass 20, count 0 2006.196.08:21:49.22#ibcon#enter sib2, iclass 20, count 0 2006.196.08:21:49.22#ibcon#flushed, iclass 20, count 0 2006.196.08:21:49.22#ibcon#about to write, iclass 20, count 0 2006.196.08:21:49.22#ibcon#wrote, iclass 20, count 0 2006.196.08:21:49.22#ibcon#about to read 3, iclass 20, count 0 2006.196.08:21:49.24#ibcon#read 3, iclass 20, count 0 2006.196.08:21:49.24#ibcon#about to read 4, iclass 20, count 0 2006.196.08:21:49.24#ibcon#read 4, iclass 20, count 0 2006.196.08:21:49.24#ibcon#about to read 5, iclass 20, count 0 2006.196.08:21:49.24#ibcon#read 5, iclass 20, count 0 2006.196.08:21:49.24#ibcon#about to read 6, iclass 20, count 0 2006.196.08:21:49.24#ibcon#read 6, iclass 20, count 0 2006.196.08:21:49.24#ibcon#end of sib2, iclass 20, count 0 2006.196.08:21:49.24#ibcon#*mode == 0, iclass 20, count 0 2006.196.08:21:49.24#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.196.08:21:49.24#ibcon#[25=USB\r\n] 2006.196.08:21:49.24#ibcon#*before write, iclass 20, count 0 2006.196.08:21:49.24#ibcon#enter sib2, iclass 20, count 0 2006.196.08:21:49.24#ibcon#flushed, iclass 20, count 0 2006.196.08:21:49.24#ibcon#about to write, iclass 20, count 0 2006.196.08:21:49.24#ibcon#wrote, iclass 20, count 0 2006.196.08:21:49.24#ibcon#about to read 3, iclass 20, count 0 2006.196.08:21:49.27#ibcon#read 3, iclass 20, count 0 2006.196.08:21:49.27#ibcon#about to read 4, iclass 20, count 0 2006.196.08:21:49.27#ibcon#read 4, iclass 20, count 0 2006.196.08:21:49.27#ibcon#about to read 5, iclass 20, count 0 2006.196.08:21:49.27#ibcon#read 5, iclass 20, count 0 2006.196.08:21:49.27#ibcon#about to read 6, iclass 20, count 0 2006.196.08:21:49.27#ibcon#read 6, iclass 20, count 0 2006.196.08:21:49.27#ibcon#end of sib2, iclass 20, count 0 2006.196.08:21:49.27#ibcon#*after write, iclass 20, count 0 2006.196.08:21:49.27#ibcon#*before return 0, iclass 20, count 0 2006.196.08:21:49.27#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.196.08:21:49.27#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.196.08:21:49.27#ibcon#about to clear, iclass 20 cls_cnt 0 2006.196.08:21:49.27#ibcon#cleared, iclass 20 cls_cnt 0 2006.196.08:21:49.27$vc4f8/valo=5,652.99 2006.196.08:21:49.27#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.196.08:21:49.27#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.196.08:21:49.27#ibcon#ireg 17 cls_cnt 0 2006.196.08:21:49.27#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.196.08:21:49.27#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.196.08:21:49.27#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.196.08:21:49.27#ibcon#enter wrdev, iclass 22, count 0 2006.196.08:21:49.27#ibcon#first serial, iclass 22, count 0 2006.196.08:21:49.27#ibcon#enter sib2, iclass 22, count 0 2006.196.08:21:49.27#ibcon#flushed, iclass 22, count 0 2006.196.08:21:49.27#ibcon#about to write, iclass 22, count 0 2006.196.08:21:49.27#ibcon#wrote, iclass 22, count 0 2006.196.08:21:49.27#ibcon#about to read 3, iclass 22, count 0 2006.196.08:21:49.29#ibcon#read 3, iclass 22, count 0 2006.196.08:21:49.29#ibcon#about to read 4, iclass 22, count 0 2006.196.08:21:49.29#ibcon#read 4, iclass 22, count 0 2006.196.08:21:49.29#ibcon#about to read 5, iclass 22, count 0 2006.196.08:21:49.29#ibcon#read 5, iclass 22, count 0 2006.196.08:21:49.29#ibcon#about to read 6, iclass 22, count 0 2006.196.08:21:49.29#ibcon#read 6, iclass 22, count 0 2006.196.08:21:49.29#ibcon#end of sib2, iclass 22, count 0 2006.196.08:21:49.29#ibcon#*mode == 0, iclass 22, count 0 2006.196.08:21:49.29#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.196.08:21:49.29#ibcon#[26=FRQ=05,652.99\r\n] 2006.196.08:21:49.29#ibcon#*before write, iclass 22, count 0 2006.196.08:21:49.29#ibcon#enter sib2, iclass 22, count 0 2006.196.08:21:49.29#ibcon#flushed, iclass 22, count 0 2006.196.08:21:49.29#ibcon#about to write, iclass 22, count 0 2006.196.08:21:49.29#ibcon#wrote, iclass 22, count 0 2006.196.08:21:49.29#ibcon#about to read 3, iclass 22, count 0 2006.196.08:21:49.33#ibcon#read 3, iclass 22, count 0 2006.196.08:21:49.33#ibcon#about to read 4, iclass 22, count 0 2006.196.08:21:49.33#ibcon#read 4, iclass 22, count 0 2006.196.08:21:49.33#ibcon#about to read 5, iclass 22, count 0 2006.196.08:21:49.33#ibcon#read 5, iclass 22, count 0 2006.196.08:21:49.33#ibcon#about to read 6, iclass 22, count 0 2006.196.08:21:49.33#ibcon#read 6, iclass 22, count 0 2006.196.08:21:49.33#ibcon#end of sib2, iclass 22, count 0 2006.196.08:21:49.33#ibcon#*after write, iclass 22, count 0 2006.196.08:21:49.33#ibcon#*before return 0, iclass 22, count 0 2006.196.08:21:49.33#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.196.08:21:49.33#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.196.08:21:49.33#ibcon#about to clear, iclass 22 cls_cnt 0 2006.196.08:21:49.33#ibcon#cleared, iclass 22 cls_cnt 0 2006.196.08:21:49.33$vc4f8/va=5,7 2006.196.08:21:49.33#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.196.08:21:49.33#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.196.08:21:49.33#ibcon#ireg 11 cls_cnt 2 2006.196.08:21:49.33#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.196.08:21:49.39#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.196.08:21:49.39#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.196.08:21:49.39#ibcon#enter wrdev, iclass 24, count 2 2006.196.08:21:49.39#ibcon#first serial, iclass 24, count 2 2006.196.08:21:49.39#ibcon#enter sib2, iclass 24, count 2 2006.196.08:21:49.39#ibcon#flushed, iclass 24, count 2 2006.196.08:21:49.39#ibcon#about to write, iclass 24, count 2 2006.196.08:21:49.39#ibcon#wrote, iclass 24, count 2 2006.196.08:21:49.39#ibcon#about to read 3, iclass 24, count 2 2006.196.08:21:49.41#ibcon#read 3, iclass 24, count 2 2006.196.08:21:49.41#ibcon#about to read 4, iclass 24, count 2 2006.196.08:21:49.41#ibcon#read 4, iclass 24, count 2 2006.196.08:21:49.41#ibcon#about to read 5, iclass 24, count 2 2006.196.08:21:49.41#ibcon#read 5, iclass 24, count 2 2006.196.08:21:49.41#ibcon#about to read 6, iclass 24, count 2 2006.196.08:21:49.41#ibcon#read 6, iclass 24, count 2 2006.196.08:21:49.41#ibcon#end of sib2, iclass 24, count 2 2006.196.08:21:49.41#ibcon#*mode == 0, iclass 24, count 2 2006.196.08:21:49.41#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.196.08:21:49.41#ibcon#[25=AT05-07\r\n] 2006.196.08:21:49.41#ibcon#*before write, iclass 24, count 2 2006.196.08:21:49.41#ibcon#enter sib2, iclass 24, count 2 2006.196.08:21:49.41#ibcon#flushed, iclass 24, count 2 2006.196.08:21:49.41#ibcon#about to write, iclass 24, count 2 2006.196.08:21:49.41#ibcon#wrote, iclass 24, count 2 2006.196.08:21:49.41#ibcon#about to read 3, iclass 24, count 2 2006.196.08:21:49.44#ibcon#read 3, iclass 24, count 2 2006.196.08:21:49.44#ibcon#about to read 4, iclass 24, count 2 2006.196.08:21:49.44#ibcon#read 4, iclass 24, count 2 2006.196.08:21:49.44#ibcon#about to read 5, iclass 24, count 2 2006.196.08:21:49.44#ibcon#read 5, iclass 24, count 2 2006.196.08:21:49.44#ibcon#about to read 6, iclass 24, count 2 2006.196.08:21:49.44#ibcon#read 6, iclass 24, count 2 2006.196.08:21:49.44#ibcon#end of sib2, iclass 24, count 2 2006.196.08:21:49.44#ibcon#*after write, iclass 24, count 2 2006.196.08:21:49.44#ibcon#*before return 0, iclass 24, count 2 2006.196.08:21:49.44#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.196.08:21:49.44#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.196.08:21:49.44#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.196.08:21:49.44#ibcon#ireg 7 cls_cnt 0 2006.196.08:21:49.44#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.196.08:21:49.56#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.196.08:21:49.56#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.196.08:21:49.56#ibcon#enter wrdev, iclass 24, count 0 2006.196.08:21:49.56#ibcon#first serial, iclass 24, count 0 2006.196.08:21:49.56#ibcon#enter sib2, iclass 24, count 0 2006.196.08:21:49.56#ibcon#flushed, iclass 24, count 0 2006.196.08:21:49.56#ibcon#about to write, iclass 24, count 0 2006.196.08:21:49.56#ibcon#wrote, iclass 24, count 0 2006.196.08:21:49.56#ibcon#about to read 3, iclass 24, count 0 2006.196.08:21:49.58#ibcon#read 3, iclass 24, count 0 2006.196.08:21:49.58#ibcon#about to read 4, iclass 24, count 0 2006.196.08:21:49.58#ibcon#read 4, iclass 24, count 0 2006.196.08:21:49.58#ibcon#about to read 5, iclass 24, count 0 2006.196.08:21:49.58#ibcon#read 5, iclass 24, count 0 2006.196.08:21:49.58#ibcon#about to read 6, iclass 24, count 0 2006.196.08:21:49.58#ibcon#read 6, iclass 24, count 0 2006.196.08:21:49.58#ibcon#end of sib2, iclass 24, count 0 2006.196.08:21:49.58#ibcon#*mode == 0, iclass 24, count 0 2006.196.08:21:49.58#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.196.08:21:49.58#ibcon#[25=USB\r\n] 2006.196.08:21:49.58#ibcon#*before write, iclass 24, count 0 2006.196.08:21:49.58#ibcon#enter sib2, iclass 24, count 0 2006.196.08:21:49.58#ibcon#flushed, iclass 24, count 0 2006.196.08:21:49.58#ibcon#about to write, iclass 24, count 0 2006.196.08:21:49.58#ibcon#wrote, iclass 24, count 0 2006.196.08:21:49.58#ibcon#about to read 3, iclass 24, count 0 2006.196.08:21:49.61#ibcon#read 3, iclass 24, count 0 2006.196.08:21:49.61#ibcon#about to read 4, iclass 24, count 0 2006.196.08:21:49.61#ibcon#read 4, iclass 24, count 0 2006.196.08:21:49.61#ibcon#about to read 5, iclass 24, count 0 2006.196.08:21:49.61#ibcon#read 5, iclass 24, count 0 2006.196.08:21:49.61#ibcon#about to read 6, iclass 24, count 0 2006.196.08:21:49.61#ibcon#read 6, iclass 24, count 0 2006.196.08:21:49.61#ibcon#end of sib2, iclass 24, count 0 2006.196.08:21:49.61#ibcon#*after write, iclass 24, count 0 2006.196.08:21:49.61#ibcon#*before return 0, iclass 24, count 0 2006.196.08:21:49.61#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.196.08:21:49.61#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.196.08:21:49.61#ibcon#about to clear, iclass 24 cls_cnt 0 2006.196.08:21:49.61#ibcon#cleared, iclass 24 cls_cnt 0 2006.196.08:21:49.61$vc4f8/valo=6,772.99 2006.196.08:21:49.61#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.196.08:21:49.61#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.196.08:21:49.61#ibcon#ireg 17 cls_cnt 0 2006.196.08:21:49.61#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.196.08:21:49.61#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.196.08:21:49.61#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.196.08:21:49.61#ibcon#enter wrdev, iclass 26, count 0 2006.196.08:21:49.61#ibcon#first serial, iclass 26, count 0 2006.196.08:21:49.61#ibcon#enter sib2, iclass 26, count 0 2006.196.08:21:49.61#ibcon#flushed, iclass 26, count 0 2006.196.08:21:49.61#ibcon#about to write, iclass 26, count 0 2006.196.08:21:49.61#ibcon#wrote, iclass 26, count 0 2006.196.08:21:49.61#ibcon#about to read 3, iclass 26, count 0 2006.196.08:21:49.63#ibcon#read 3, iclass 26, count 0 2006.196.08:21:49.63#ibcon#about to read 4, iclass 26, count 0 2006.196.08:21:49.63#ibcon#read 4, iclass 26, count 0 2006.196.08:21:49.63#ibcon#about to read 5, iclass 26, count 0 2006.196.08:21:49.63#ibcon#read 5, iclass 26, count 0 2006.196.08:21:49.63#ibcon#about to read 6, iclass 26, count 0 2006.196.08:21:49.63#ibcon#read 6, iclass 26, count 0 2006.196.08:21:49.63#ibcon#end of sib2, iclass 26, count 0 2006.196.08:21:49.63#ibcon#*mode == 0, iclass 26, count 0 2006.196.08:21:49.63#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.196.08:21:49.63#ibcon#[26=FRQ=06,772.99\r\n] 2006.196.08:21:49.63#ibcon#*before write, iclass 26, count 0 2006.196.08:21:49.63#ibcon#enter sib2, iclass 26, count 0 2006.196.08:21:49.63#ibcon#flushed, iclass 26, count 0 2006.196.08:21:49.63#ibcon#about to write, iclass 26, count 0 2006.196.08:21:49.63#ibcon#wrote, iclass 26, count 0 2006.196.08:21:49.63#ibcon#about to read 3, iclass 26, count 0 2006.196.08:21:49.67#ibcon#read 3, iclass 26, count 0 2006.196.08:21:49.67#ibcon#about to read 4, iclass 26, count 0 2006.196.08:21:49.67#ibcon#read 4, iclass 26, count 0 2006.196.08:21:49.67#ibcon#about to read 5, iclass 26, count 0 2006.196.08:21:49.67#ibcon#read 5, iclass 26, count 0 2006.196.08:21:49.67#ibcon#about to read 6, iclass 26, count 0 2006.196.08:21:49.67#ibcon#read 6, iclass 26, count 0 2006.196.08:21:49.67#ibcon#end of sib2, iclass 26, count 0 2006.196.08:21:49.67#ibcon#*after write, iclass 26, count 0 2006.196.08:21:49.67#ibcon#*before return 0, iclass 26, count 0 2006.196.08:21:49.67#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.196.08:21:49.67#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.196.08:21:49.67#ibcon#about to clear, iclass 26 cls_cnt 0 2006.196.08:21:49.67#ibcon#cleared, iclass 26 cls_cnt 0 2006.196.08:21:49.67$vc4f8/va=6,6 2006.196.08:21:49.67#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.196.08:21:49.67#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.196.08:21:49.67#ibcon#ireg 11 cls_cnt 2 2006.196.08:21:49.67#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.196.08:21:49.73#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.196.08:21:49.73#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.196.08:21:49.73#ibcon#enter wrdev, iclass 28, count 2 2006.196.08:21:49.73#ibcon#first serial, iclass 28, count 2 2006.196.08:21:49.73#ibcon#enter sib2, iclass 28, count 2 2006.196.08:21:49.73#ibcon#flushed, iclass 28, count 2 2006.196.08:21:49.73#ibcon#about to write, iclass 28, count 2 2006.196.08:21:49.73#ibcon#wrote, iclass 28, count 2 2006.196.08:21:49.73#ibcon#about to read 3, iclass 28, count 2 2006.196.08:21:49.75#ibcon#read 3, iclass 28, count 2 2006.196.08:21:49.75#ibcon#about to read 4, iclass 28, count 2 2006.196.08:21:49.75#ibcon#read 4, iclass 28, count 2 2006.196.08:21:49.75#ibcon#about to read 5, iclass 28, count 2 2006.196.08:21:49.75#ibcon#read 5, iclass 28, count 2 2006.196.08:21:49.75#ibcon#about to read 6, iclass 28, count 2 2006.196.08:21:49.75#ibcon#read 6, iclass 28, count 2 2006.196.08:21:49.75#ibcon#end of sib2, iclass 28, count 2 2006.196.08:21:49.75#ibcon#*mode == 0, iclass 28, count 2 2006.196.08:21:49.75#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.196.08:21:49.75#ibcon#[25=AT06-06\r\n] 2006.196.08:21:49.75#ibcon#*before write, iclass 28, count 2 2006.196.08:21:49.75#ibcon#enter sib2, iclass 28, count 2 2006.196.08:21:49.75#ibcon#flushed, iclass 28, count 2 2006.196.08:21:49.75#ibcon#about to write, iclass 28, count 2 2006.196.08:21:49.75#ibcon#wrote, iclass 28, count 2 2006.196.08:21:49.75#ibcon#about to read 3, iclass 28, count 2 2006.196.08:21:49.78#ibcon#read 3, iclass 28, count 2 2006.196.08:21:49.78#ibcon#about to read 4, iclass 28, count 2 2006.196.08:21:49.78#ibcon#read 4, iclass 28, count 2 2006.196.08:21:49.78#ibcon#about to read 5, iclass 28, count 2 2006.196.08:21:49.78#ibcon#read 5, iclass 28, count 2 2006.196.08:21:49.78#ibcon#about to read 6, iclass 28, count 2 2006.196.08:21:49.78#ibcon#read 6, iclass 28, count 2 2006.196.08:21:49.78#ibcon#end of sib2, iclass 28, count 2 2006.196.08:21:49.78#ibcon#*after write, iclass 28, count 2 2006.196.08:21:49.78#ibcon#*before return 0, iclass 28, count 2 2006.196.08:21:49.78#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.196.08:21:49.78#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.196.08:21:49.78#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.196.08:21:49.78#ibcon#ireg 7 cls_cnt 0 2006.196.08:21:49.78#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.196.08:21:49.90#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.196.08:21:49.90#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.196.08:21:49.90#ibcon#enter wrdev, iclass 28, count 0 2006.196.08:21:49.90#ibcon#first serial, iclass 28, count 0 2006.196.08:21:49.90#ibcon#enter sib2, iclass 28, count 0 2006.196.08:21:49.90#ibcon#flushed, iclass 28, count 0 2006.196.08:21:49.90#ibcon#about to write, iclass 28, count 0 2006.196.08:21:49.90#ibcon#wrote, iclass 28, count 0 2006.196.08:21:49.90#ibcon#about to read 3, iclass 28, count 0 2006.196.08:21:49.92#ibcon#read 3, iclass 28, count 0 2006.196.08:21:49.92#ibcon#about to read 4, iclass 28, count 0 2006.196.08:21:49.92#ibcon#read 4, iclass 28, count 0 2006.196.08:21:49.92#ibcon#about to read 5, iclass 28, count 0 2006.196.08:21:49.92#ibcon#read 5, iclass 28, count 0 2006.196.08:21:49.92#ibcon#about to read 6, iclass 28, count 0 2006.196.08:21:49.92#ibcon#read 6, iclass 28, count 0 2006.196.08:21:49.92#ibcon#end of sib2, iclass 28, count 0 2006.196.08:21:49.92#ibcon#*mode == 0, iclass 28, count 0 2006.196.08:21:49.92#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.196.08:21:49.92#ibcon#[25=USB\r\n] 2006.196.08:21:49.92#ibcon#*before write, iclass 28, count 0 2006.196.08:21:49.92#ibcon#enter sib2, iclass 28, count 0 2006.196.08:21:49.92#ibcon#flushed, iclass 28, count 0 2006.196.08:21:49.92#ibcon#about to write, iclass 28, count 0 2006.196.08:21:49.92#ibcon#wrote, iclass 28, count 0 2006.196.08:21:49.92#ibcon#about to read 3, iclass 28, count 0 2006.196.08:21:49.95#ibcon#read 3, iclass 28, count 0 2006.196.08:21:49.95#ibcon#about to read 4, iclass 28, count 0 2006.196.08:21:49.95#ibcon#read 4, iclass 28, count 0 2006.196.08:21:49.95#ibcon#about to read 5, iclass 28, count 0 2006.196.08:21:49.95#ibcon#read 5, iclass 28, count 0 2006.196.08:21:49.95#ibcon#about to read 6, iclass 28, count 0 2006.196.08:21:49.95#ibcon#read 6, iclass 28, count 0 2006.196.08:21:49.95#ibcon#end of sib2, iclass 28, count 0 2006.196.08:21:49.95#ibcon#*after write, iclass 28, count 0 2006.196.08:21:49.95#ibcon#*before return 0, iclass 28, count 0 2006.196.08:21:49.95#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.196.08:21:49.95#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.196.08:21:49.95#ibcon#about to clear, iclass 28 cls_cnt 0 2006.196.08:21:49.95#ibcon#cleared, iclass 28 cls_cnt 0 2006.196.08:21:49.95$vc4f8/valo=7,832.99 2006.196.08:21:49.95#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.196.08:21:49.95#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.196.08:21:49.95#ibcon#ireg 17 cls_cnt 0 2006.196.08:21:49.95#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.196.08:21:49.95#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.196.08:21:49.95#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.196.08:21:49.95#ibcon#enter wrdev, iclass 30, count 0 2006.196.08:21:49.95#ibcon#first serial, iclass 30, count 0 2006.196.08:21:49.95#ibcon#enter sib2, iclass 30, count 0 2006.196.08:21:49.95#ibcon#flushed, iclass 30, count 0 2006.196.08:21:49.95#ibcon#about to write, iclass 30, count 0 2006.196.08:21:49.95#ibcon#wrote, iclass 30, count 0 2006.196.08:21:49.95#ibcon#about to read 3, iclass 30, count 0 2006.196.08:21:49.97#ibcon#read 3, iclass 30, count 0 2006.196.08:21:49.97#ibcon#about to read 4, iclass 30, count 0 2006.196.08:21:49.97#ibcon#read 4, iclass 30, count 0 2006.196.08:21:49.97#ibcon#about to read 5, iclass 30, count 0 2006.196.08:21:49.97#ibcon#read 5, iclass 30, count 0 2006.196.08:21:49.97#ibcon#about to read 6, iclass 30, count 0 2006.196.08:21:49.97#ibcon#read 6, iclass 30, count 0 2006.196.08:21:49.97#ibcon#end of sib2, iclass 30, count 0 2006.196.08:21:49.97#ibcon#*mode == 0, iclass 30, count 0 2006.196.08:21:49.97#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.196.08:21:49.97#ibcon#[26=FRQ=07,832.99\r\n] 2006.196.08:21:49.97#ibcon#*before write, iclass 30, count 0 2006.196.08:21:49.97#ibcon#enter sib2, iclass 30, count 0 2006.196.08:21:49.97#ibcon#flushed, iclass 30, count 0 2006.196.08:21:49.97#ibcon#about to write, iclass 30, count 0 2006.196.08:21:49.97#ibcon#wrote, iclass 30, count 0 2006.196.08:21:49.97#ibcon#about to read 3, iclass 30, count 0 2006.196.08:21:50.01#ibcon#read 3, iclass 30, count 0 2006.196.08:21:50.01#ibcon#about to read 4, iclass 30, count 0 2006.196.08:21:50.01#ibcon#read 4, iclass 30, count 0 2006.196.08:21:50.01#ibcon#about to read 5, iclass 30, count 0 2006.196.08:21:50.01#ibcon#read 5, iclass 30, count 0 2006.196.08:21:50.01#ibcon#about to read 6, iclass 30, count 0 2006.196.08:21:50.01#ibcon#read 6, iclass 30, count 0 2006.196.08:21:50.01#ibcon#end of sib2, iclass 30, count 0 2006.196.08:21:50.01#ibcon#*after write, iclass 30, count 0 2006.196.08:21:50.01#ibcon#*before return 0, iclass 30, count 0 2006.196.08:21:50.01#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.196.08:21:50.01#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.196.08:21:50.01#ibcon#about to clear, iclass 30 cls_cnt 0 2006.196.08:21:50.01#ibcon#cleared, iclass 30 cls_cnt 0 2006.196.08:21:50.01$vc4f8/va=7,6 2006.196.08:21:50.01#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.196.08:21:50.01#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.196.08:21:50.01#ibcon#ireg 11 cls_cnt 2 2006.196.08:21:50.01#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.196.08:21:50.07#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.196.08:21:50.07#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.196.08:21:50.07#ibcon#enter wrdev, iclass 32, count 2 2006.196.08:21:50.07#ibcon#first serial, iclass 32, count 2 2006.196.08:21:50.07#ibcon#enter sib2, iclass 32, count 2 2006.196.08:21:50.07#ibcon#flushed, iclass 32, count 2 2006.196.08:21:50.07#ibcon#about to write, iclass 32, count 2 2006.196.08:21:50.07#ibcon#wrote, iclass 32, count 2 2006.196.08:21:50.07#ibcon#about to read 3, iclass 32, count 2 2006.196.08:21:50.09#ibcon#read 3, iclass 32, count 2 2006.196.08:21:50.09#ibcon#about to read 4, iclass 32, count 2 2006.196.08:21:50.09#ibcon#read 4, iclass 32, count 2 2006.196.08:21:50.09#ibcon#about to read 5, iclass 32, count 2 2006.196.08:21:50.09#ibcon#read 5, iclass 32, count 2 2006.196.08:21:50.09#ibcon#about to read 6, iclass 32, count 2 2006.196.08:21:50.09#ibcon#read 6, iclass 32, count 2 2006.196.08:21:50.09#ibcon#end of sib2, iclass 32, count 2 2006.196.08:21:50.09#ibcon#*mode == 0, iclass 32, count 2 2006.196.08:21:50.09#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.196.08:21:50.09#ibcon#[25=AT07-06\r\n] 2006.196.08:21:50.09#ibcon#*before write, iclass 32, count 2 2006.196.08:21:50.09#ibcon#enter sib2, iclass 32, count 2 2006.196.08:21:50.09#ibcon#flushed, iclass 32, count 2 2006.196.08:21:50.09#ibcon#about to write, iclass 32, count 2 2006.196.08:21:50.09#ibcon#wrote, iclass 32, count 2 2006.196.08:21:50.09#ibcon#about to read 3, iclass 32, count 2 2006.196.08:21:50.12#ibcon#read 3, iclass 32, count 2 2006.196.08:21:50.12#ibcon#about to read 4, iclass 32, count 2 2006.196.08:21:50.12#ibcon#read 4, iclass 32, count 2 2006.196.08:21:50.12#ibcon#about to read 5, iclass 32, count 2 2006.196.08:21:50.12#ibcon#read 5, iclass 32, count 2 2006.196.08:21:50.12#ibcon#about to read 6, iclass 32, count 2 2006.196.08:21:50.12#ibcon#read 6, iclass 32, count 2 2006.196.08:21:50.12#ibcon#end of sib2, iclass 32, count 2 2006.196.08:21:50.12#ibcon#*after write, iclass 32, count 2 2006.196.08:21:50.12#ibcon#*before return 0, iclass 32, count 2 2006.196.08:21:50.12#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.196.08:21:50.12#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.196.08:21:50.12#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.196.08:21:50.12#ibcon#ireg 7 cls_cnt 0 2006.196.08:21:50.12#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.196.08:21:50.24#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.196.08:21:50.24#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.196.08:21:50.24#ibcon#enter wrdev, iclass 32, count 0 2006.196.08:21:50.24#ibcon#first serial, iclass 32, count 0 2006.196.08:21:50.24#ibcon#enter sib2, iclass 32, count 0 2006.196.08:21:50.24#ibcon#flushed, iclass 32, count 0 2006.196.08:21:50.24#ibcon#about to write, iclass 32, count 0 2006.196.08:21:50.24#ibcon#wrote, iclass 32, count 0 2006.196.08:21:50.24#ibcon#about to read 3, iclass 32, count 0 2006.196.08:21:50.26#ibcon#read 3, iclass 32, count 0 2006.196.08:21:50.26#ibcon#about to read 4, iclass 32, count 0 2006.196.08:21:50.26#ibcon#read 4, iclass 32, count 0 2006.196.08:21:50.26#ibcon#about to read 5, iclass 32, count 0 2006.196.08:21:50.26#ibcon#read 5, iclass 32, count 0 2006.196.08:21:50.26#ibcon#about to read 6, iclass 32, count 0 2006.196.08:21:50.26#ibcon#read 6, iclass 32, count 0 2006.196.08:21:50.26#ibcon#end of sib2, iclass 32, count 0 2006.196.08:21:50.26#ibcon#*mode == 0, iclass 32, count 0 2006.196.08:21:50.26#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.196.08:21:50.26#ibcon#[25=USB\r\n] 2006.196.08:21:50.26#ibcon#*before write, iclass 32, count 0 2006.196.08:21:50.26#ibcon#enter sib2, iclass 32, count 0 2006.196.08:21:50.26#ibcon#flushed, iclass 32, count 0 2006.196.08:21:50.26#ibcon#about to write, iclass 32, count 0 2006.196.08:21:50.26#ibcon#wrote, iclass 32, count 0 2006.196.08:21:50.26#ibcon#about to read 3, iclass 32, count 0 2006.196.08:21:50.29#ibcon#read 3, iclass 32, count 0 2006.196.08:21:50.29#ibcon#about to read 4, iclass 32, count 0 2006.196.08:21:50.29#ibcon#read 4, iclass 32, count 0 2006.196.08:21:50.29#ibcon#about to read 5, iclass 32, count 0 2006.196.08:21:50.29#ibcon#read 5, iclass 32, count 0 2006.196.08:21:50.29#ibcon#about to read 6, iclass 32, count 0 2006.196.08:21:50.29#ibcon#read 6, iclass 32, count 0 2006.196.08:21:50.29#ibcon#end of sib2, iclass 32, count 0 2006.196.08:21:50.29#ibcon#*after write, iclass 32, count 0 2006.196.08:21:50.29#ibcon#*before return 0, iclass 32, count 0 2006.196.08:21:50.29#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.196.08:21:50.29#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.196.08:21:50.29#ibcon#about to clear, iclass 32 cls_cnt 0 2006.196.08:21:50.29#ibcon#cleared, iclass 32 cls_cnt 0 2006.196.08:21:50.29$vc4f8/valo=8,852.99 2006.196.08:21:50.29#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.196.08:21:50.29#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.196.08:21:50.29#ibcon#ireg 17 cls_cnt 0 2006.196.08:21:50.29#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.196.08:21:50.29#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.196.08:21:50.29#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.196.08:21:50.29#ibcon#enter wrdev, iclass 34, count 0 2006.196.08:21:50.29#ibcon#first serial, iclass 34, count 0 2006.196.08:21:50.29#ibcon#enter sib2, iclass 34, count 0 2006.196.08:21:50.29#ibcon#flushed, iclass 34, count 0 2006.196.08:21:50.29#ibcon#about to write, iclass 34, count 0 2006.196.08:21:50.29#ibcon#wrote, iclass 34, count 0 2006.196.08:21:50.29#ibcon#about to read 3, iclass 34, count 0 2006.196.08:21:50.31#ibcon#read 3, iclass 34, count 0 2006.196.08:21:50.31#ibcon#about to read 4, iclass 34, count 0 2006.196.08:21:50.31#ibcon#read 4, iclass 34, count 0 2006.196.08:21:50.31#ibcon#about to read 5, iclass 34, count 0 2006.196.08:21:50.31#ibcon#read 5, iclass 34, count 0 2006.196.08:21:50.31#ibcon#about to read 6, iclass 34, count 0 2006.196.08:21:50.31#ibcon#read 6, iclass 34, count 0 2006.196.08:21:50.31#ibcon#end of sib2, iclass 34, count 0 2006.196.08:21:50.31#ibcon#*mode == 0, iclass 34, count 0 2006.196.08:21:50.31#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.196.08:21:50.31#ibcon#[26=FRQ=08,852.99\r\n] 2006.196.08:21:50.31#ibcon#*before write, iclass 34, count 0 2006.196.08:21:50.31#ibcon#enter sib2, iclass 34, count 0 2006.196.08:21:50.31#ibcon#flushed, iclass 34, count 0 2006.196.08:21:50.31#ibcon#about to write, iclass 34, count 0 2006.196.08:21:50.31#ibcon#wrote, iclass 34, count 0 2006.196.08:21:50.31#ibcon#about to read 3, iclass 34, count 0 2006.196.08:21:50.35#ibcon#read 3, iclass 34, count 0 2006.196.08:21:50.35#ibcon#about to read 4, iclass 34, count 0 2006.196.08:21:50.35#ibcon#read 4, iclass 34, count 0 2006.196.08:21:50.35#ibcon#about to read 5, iclass 34, count 0 2006.196.08:21:50.35#ibcon#read 5, iclass 34, count 0 2006.196.08:21:50.35#ibcon#about to read 6, iclass 34, count 0 2006.196.08:21:50.35#ibcon#read 6, iclass 34, count 0 2006.196.08:21:50.35#ibcon#end of sib2, iclass 34, count 0 2006.196.08:21:50.35#ibcon#*after write, iclass 34, count 0 2006.196.08:21:50.35#ibcon#*before return 0, iclass 34, count 0 2006.196.08:21:50.35#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.196.08:21:50.35#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.196.08:21:50.35#ibcon#about to clear, iclass 34 cls_cnt 0 2006.196.08:21:50.35#ibcon#cleared, iclass 34 cls_cnt 0 2006.196.08:21:50.35$vc4f8/va=8,7 2006.196.08:21:50.35#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.196.08:21:50.35#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.196.08:21:50.35#ibcon#ireg 11 cls_cnt 2 2006.196.08:21:50.35#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.196.08:21:50.41#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.196.08:21:50.41#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.196.08:21:50.41#ibcon#enter wrdev, iclass 36, count 2 2006.196.08:21:50.41#ibcon#first serial, iclass 36, count 2 2006.196.08:21:50.41#ibcon#enter sib2, iclass 36, count 2 2006.196.08:21:50.41#ibcon#flushed, iclass 36, count 2 2006.196.08:21:50.41#ibcon#about to write, iclass 36, count 2 2006.196.08:21:50.41#ibcon#wrote, iclass 36, count 2 2006.196.08:21:50.41#ibcon#about to read 3, iclass 36, count 2 2006.196.08:21:50.43#ibcon#read 3, iclass 36, count 2 2006.196.08:21:50.43#ibcon#about to read 4, iclass 36, count 2 2006.196.08:21:50.43#ibcon#read 4, iclass 36, count 2 2006.196.08:21:50.43#ibcon#about to read 5, iclass 36, count 2 2006.196.08:21:50.43#ibcon#read 5, iclass 36, count 2 2006.196.08:21:50.43#ibcon#about to read 6, iclass 36, count 2 2006.196.08:21:50.43#ibcon#read 6, iclass 36, count 2 2006.196.08:21:50.43#ibcon#end of sib2, iclass 36, count 2 2006.196.08:21:50.43#ibcon#*mode == 0, iclass 36, count 2 2006.196.08:21:50.43#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.196.08:21:50.43#ibcon#[25=AT08-07\r\n] 2006.196.08:21:50.43#ibcon#*before write, iclass 36, count 2 2006.196.08:21:50.43#ibcon#enter sib2, iclass 36, count 2 2006.196.08:21:50.43#ibcon#flushed, iclass 36, count 2 2006.196.08:21:50.43#ibcon#about to write, iclass 36, count 2 2006.196.08:21:50.43#ibcon#wrote, iclass 36, count 2 2006.196.08:21:50.43#ibcon#about to read 3, iclass 36, count 2 2006.196.08:21:50.46#ibcon#read 3, iclass 36, count 2 2006.196.08:21:50.46#ibcon#about to read 4, iclass 36, count 2 2006.196.08:21:50.46#ibcon#read 4, iclass 36, count 2 2006.196.08:21:50.46#ibcon#about to read 5, iclass 36, count 2 2006.196.08:21:50.46#ibcon#read 5, iclass 36, count 2 2006.196.08:21:50.46#ibcon#about to read 6, iclass 36, count 2 2006.196.08:21:50.46#ibcon#read 6, iclass 36, count 2 2006.196.08:21:50.46#ibcon#end of sib2, iclass 36, count 2 2006.196.08:21:50.46#ibcon#*after write, iclass 36, count 2 2006.196.08:21:50.46#ibcon#*before return 0, iclass 36, count 2 2006.196.08:21:50.46#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.196.08:21:50.46#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.196.08:21:50.46#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.196.08:21:50.46#ibcon#ireg 7 cls_cnt 0 2006.196.08:21:50.46#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.196.08:21:50.58#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.196.08:21:50.58#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.196.08:21:50.58#ibcon#enter wrdev, iclass 36, count 0 2006.196.08:21:50.58#ibcon#first serial, iclass 36, count 0 2006.196.08:21:50.58#ibcon#enter sib2, iclass 36, count 0 2006.196.08:21:50.58#ibcon#flushed, iclass 36, count 0 2006.196.08:21:50.58#ibcon#about to write, iclass 36, count 0 2006.196.08:21:50.58#ibcon#wrote, iclass 36, count 0 2006.196.08:21:50.58#ibcon#about to read 3, iclass 36, count 0 2006.196.08:21:50.60#ibcon#read 3, iclass 36, count 0 2006.196.08:21:50.60#ibcon#about to read 4, iclass 36, count 0 2006.196.08:21:50.60#ibcon#read 4, iclass 36, count 0 2006.196.08:21:50.60#ibcon#about to read 5, iclass 36, count 0 2006.196.08:21:50.60#ibcon#read 5, iclass 36, count 0 2006.196.08:21:50.60#ibcon#about to read 6, iclass 36, count 0 2006.196.08:21:50.60#ibcon#read 6, iclass 36, count 0 2006.196.08:21:50.60#ibcon#end of sib2, iclass 36, count 0 2006.196.08:21:50.60#ibcon#*mode == 0, iclass 36, count 0 2006.196.08:21:50.60#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.196.08:21:50.60#ibcon#[25=USB\r\n] 2006.196.08:21:50.60#ibcon#*before write, iclass 36, count 0 2006.196.08:21:50.60#ibcon#enter sib2, iclass 36, count 0 2006.196.08:21:50.60#ibcon#flushed, iclass 36, count 0 2006.196.08:21:50.60#ibcon#about to write, iclass 36, count 0 2006.196.08:21:50.60#ibcon#wrote, iclass 36, count 0 2006.196.08:21:50.60#ibcon#about to read 3, iclass 36, count 0 2006.196.08:21:50.63#ibcon#read 3, iclass 36, count 0 2006.196.08:21:50.63#ibcon#about to read 4, iclass 36, count 0 2006.196.08:21:50.63#ibcon#read 4, iclass 36, count 0 2006.196.08:21:50.63#ibcon#about to read 5, iclass 36, count 0 2006.196.08:21:50.63#ibcon#read 5, iclass 36, count 0 2006.196.08:21:50.63#ibcon#about to read 6, iclass 36, count 0 2006.196.08:21:50.63#ibcon#read 6, iclass 36, count 0 2006.196.08:21:50.63#ibcon#end of sib2, iclass 36, count 0 2006.196.08:21:50.63#ibcon#*after write, iclass 36, count 0 2006.196.08:21:50.63#ibcon#*before return 0, iclass 36, count 0 2006.196.08:21:50.63#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.196.08:21:50.63#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.196.08:21:50.63#ibcon#about to clear, iclass 36 cls_cnt 0 2006.196.08:21:50.63#ibcon#cleared, iclass 36 cls_cnt 0 2006.196.08:21:50.63$vc4f8/vblo=1,632.99 2006.196.08:21:50.63#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.196.08:21:50.63#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.196.08:21:50.63#ibcon#ireg 17 cls_cnt 0 2006.196.08:21:50.63#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.196.08:21:50.63#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.196.08:21:50.63#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.196.08:21:50.63#ibcon#enter wrdev, iclass 38, count 0 2006.196.08:21:50.63#ibcon#first serial, iclass 38, count 0 2006.196.08:21:50.63#ibcon#enter sib2, iclass 38, count 0 2006.196.08:21:50.63#ibcon#flushed, iclass 38, count 0 2006.196.08:21:50.63#ibcon#about to write, iclass 38, count 0 2006.196.08:21:50.63#ibcon#wrote, iclass 38, count 0 2006.196.08:21:50.63#ibcon#about to read 3, iclass 38, count 0 2006.196.08:21:50.65#ibcon#read 3, iclass 38, count 0 2006.196.08:21:50.65#ibcon#about to read 4, iclass 38, count 0 2006.196.08:21:50.65#ibcon#read 4, iclass 38, count 0 2006.196.08:21:50.65#ibcon#about to read 5, iclass 38, count 0 2006.196.08:21:50.65#ibcon#read 5, iclass 38, count 0 2006.196.08:21:50.65#ibcon#about to read 6, iclass 38, count 0 2006.196.08:21:50.65#ibcon#read 6, iclass 38, count 0 2006.196.08:21:50.65#ibcon#end of sib2, iclass 38, count 0 2006.196.08:21:50.65#ibcon#*mode == 0, iclass 38, count 0 2006.196.08:21:50.65#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.196.08:21:50.65#ibcon#[28=FRQ=01,632.99\r\n] 2006.196.08:21:50.65#ibcon#*before write, iclass 38, count 0 2006.196.08:21:50.65#ibcon#enter sib2, iclass 38, count 0 2006.196.08:21:50.65#ibcon#flushed, iclass 38, count 0 2006.196.08:21:50.65#ibcon#about to write, iclass 38, count 0 2006.196.08:21:50.65#ibcon#wrote, iclass 38, count 0 2006.196.08:21:50.65#ibcon#about to read 3, iclass 38, count 0 2006.196.08:21:50.69#ibcon#read 3, iclass 38, count 0 2006.196.08:21:50.69#ibcon#about to read 4, iclass 38, count 0 2006.196.08:21:50.69#ibcon#read 4, iclass 38, count 0 2006.196.08:21:50.69#ibcon#about to read 5, iclass 38, count 0 2006.196.08:21:50.69#ibcon#read 5, iclass 38, count 0 2006.196.08:21:50.69#ibcon#about to read 6, iclass 38, count 0 2006.196.08:21:50.69#ibcon#read 6, iclass 38, count 0 2006.196.08:21:50.69#ibcon#end of sib2, iclass 38, count 0 2006.196.08:21:50.69#ibcon#*after write, iclass 38, count 0 2006.196.08:21:50.69#ibcon#*before return 0, iclass 38, count 0 2006.196.08:21:50.69#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.196.08:21:50.69#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.196.08:21:50.69#ibcon#about to clear, iclass 38 cls_cnt 0 2006.196.08:21:50.69#ibcon#cleared, iclass 38 cls_cnt 0 2006.196.08:21:50.69$vc4f8/vb=1,4 2006.196.08:21:50.69#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.196.08:21:50.69#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.196.08:21:50.69#ibcon#ireg 11 cls_cnt 2 2006.196.08:21:50.69#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.196.08:21:50.69#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.196.08:21:50.69#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.196.08:21:50.69#ibcon#enter wrdev, iclass 40, count 2 2006.196.08:21:50.69#ibcon#first serial, iclass 40, count 2 2006.196.08:21:50.69#ibcon#enter sib2, iclass 40, count 2 2006.196.08:21:50.69#ibcon#flushed, iclass 40, count 2 2006.196.08:21:50.69#ibcon#about to write, iclass 40, count 2 2006.196.08:21:50.69#ibcon#wrote, iclass 40, count 2 2006.196.08:21:50.69#ibcon#about to read 3, iclass 40, count 2 2006.196.08:21:50.71#ibcon#read 3, iclass 40, count 2 2006.196.08:21:50.71#ibcon#about to read 4, iclass 40, count 2 2006.196.08:21:50.71#ibcon#read 4, iclass 40, count 2 2006.196.08:21:50.71#ibcon#about to read 5, iclass 40, count 2 2006.196.08:21:50.71#ibcon#read 5, iclass 40, count 2 2006.196.08:21:50.71#ibcon#about to read 6, iclass 40, count 2 2006.196.08:21:50.71#ibcon#read 6, iclass 40, count 2 2006.196.08:21:50.71#ibcon#end of sib2, iclass 40, count 2 2006.196.08:21:50.71#ibcon#*mode == 0, iclass 40, count 2 2006.196.08:21:50.71#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.196.08:21:50.71#ibcon#[27=AT01-04\r\n] 2006.196.08:21:50.71#ibcon#*before write, iclass 40, count 2 2006.196.08:21:50.71#ibcon#enter sib2, iclass 40, count 2 2006.196.08:21:50.71#ibcon#flushed, iclass 40, count 2 2006.196.08:21:50.71#ibcon#about to write, iclass 40, count 2 2006.196.08:21:50.71#ibcon#wrote, iclass 40, count 2 2006.196.08:21:50.71#ibcon#about to read 3, iclass 40, count 2 2006.196.08:21:50.74#ibcon#read 3, iclass 40, count 2 2006.196.08:21:50.74#ibcon#about to read 4, iclass 40, count 2 2006.196.08:21:50.74#ibcon#read 4, iclass 40, count 2 2006.196.08:21:50.74#ibcon#about to read 5, iclass 40, count 2 2006.196.08:21:50.74#ibcon#read 5, iclass 40, count 2 2006.196.08:21:50.74#ibcon#about to read 6, iclass 40, count 2 2006.196.08:21:50.74#ibcon#read 6, iclass 40, count 2 2006.196.08:21:50.74#ibcon#end of sib2, iclass 40, count 2 2006.196.08:21:50.74#ibcon#*after write, iclass 40, count 2 2006.196.08:21:50.74#ibcon#*before return 0, iclass 40, count 2 2006.196.08:21:50.74#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.196.08:21:50.74#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.196.08:21:50.74#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.196.08:21:50.74#ibcon#ireg 7 cls_cnt 0 2006.196.08:21:50.74#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.196.08:21:50.86#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.196.08:21:50.86#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.196.08:21:50.86#ibcon#enter wrdev, iclass 40, count 0 2006.196.08:21:50.86#ibcon#first serial, iclass 40, count 0 2006.196.08:21:50.86#ibcon#enter sib2, iclass 40, count 0 2006.196.08:21:50.86#ibcon#flushed, iclass 40, count 0 2006.196.08:21:50.86#ibcon#about to write, iclass 40, count 0 2006.196.08:21:50.86#ibcon#wrote, iclass 40, count 0 2006.196.08:21:50.86#ibcon#about to read 3, iclass 40, count 0 2006.196.08:21:50.88#ibcon#read 3, iclass 40, count 0 2006.196.08:21:50.88#ibcon#about to read 4, iclass 40, count 0 2006.196.08:21:50.88#ibcon#read 4, iclass 40, count 0 2006.196.08:21:50.88#ibcon#about to read 5, iclass 40, count 0 2006.196.08:21:50.88#ibcon#read 5, iclass 40, count 0 2006.196.08:21:50.88#ibcon#about to read 6, iclass 40, count 0 2006.196.08:21:50.88#ibcon#read 6, iclass 40, count 0 2006.196.08:21:50.88#ibcon#end of sib2, iclass 40, count 0 2006.196.08:21:50.88#ibcon#*mode == 0, iclass 40, count 0 2006.196.08:21:50.88#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.196.08:21:50.88#ibcon#[27=USB\r\n] 2006.196.08:21:50.88#ibcon#*before write, iclass 40, count 0 2006.196.08:21:50.88#ibcon#enter sib2, iclass 40, count 0 2006.196.08:21:50.88#ibcon#flushed, iclass 40, count 0 2006.196.08:21:50.88#ibcon#about to write, iclass 40, count 0 2006.196.08:21:50.88#ibcon#wrote, iclass 40, count 0 2006.196.08:21:50.88#ibcon#about to read 3, iclass 40, count 0 2006.196.08:21:50.91#ibcon#read 3, iclass 40, count 0 2006.196.08:21:50.91#ibcon#about to read 4, iclass 40, count 0 2006.196.08:21:50.91#ibcon#read 4, iclass 40, count 0 2006.196.08:21:50.91#ibcon#about to read 5, iclass 40, count 0 2006.196.08:21:50.91#ibcon#read 5, iclass 40, count 0 2006.196.08:21:50.91#ibcon#about to read 6, iclass 40, count 0 2006.196.08:21:50.91#ibcon#read 6, iclass 40, count 0 2006.196.08:21:50.91#ibcon#end of sib2, iclass 40, count 0 2006.196.08:21:50.91#ibcon#*after write, iclass 40, count 0 2006.196.08:21:50.91#ibcon#*before return 0, iclass 40, count 0 2006.196.08:21:50.91#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.196.08:21:50.91#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.196.08:21:50.91#ibcon#about to clear, iclass 40 cls_cnt 0 2006.196.08:21:50.91#ibcon#cleared, iclass 40 cls_cnt 0 2006.196.08:21:50.91$vc4f8/vblo=2,640.99 2006.196.08:21:50.91#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.196.08:21:50.91#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.196.08:21:50.91#ibcon#ireg 17 cls_cnt 0 2006.196.08:21:50.91#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.196.08:21:50.91#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.196.08:21:50.91#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.196.08:21:50.91#ibcon#enter wrdev, iclass 4, count 0 2006.196.08:21:50.91#ibcon#first serial, iclass 4, count 0 2006.196.08:21:50.91#ibcon#enter sib2, iclass 4, count 0 2006.196.08:21:50.91#ibcon#flushed, iclass 4, count 0 2006.196.08:21:50.91#ibcon#about to write, iclass 4, count 0 2006.196.08:21:50.91#ibcon#wrote, iclass 4, count 0 2006.196.08:21:50.91#ibcon#about to read 3, iclass 4, count 0 2006.196.08:21:50.93#ibcon#read 3, iclass 4, count 0 2006.196.08:21:50.93#ibcon#about to read 4, iclass 4, count 0 2006.196.08:21:50.93#ibcon#read 4, iclass 4, count 0 2006.196.08:21:50.93#ibcon#about to read 5, iclass 4, count 0 2006.196.08:21:50.93#ibcon#read 5, iclass 4, count 0 2006.196.08:21:50.93#ibcon#about to read 6, iclass 4, count 0 2006.196.08:21:50.93#ibcon#read 6, iclass 4, count 0 2006.196.08:21:50.93#ibcon#end of sib2, iclass 4, count 0 2006.196.08:21:50.93#ibcon#*mode == 0, iclass 4, count 0 2006.196.08:21:50.93#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.196.08:21:50.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.196.08:21:50.93#ibcon#*before write, iclass 4, count 0 2006.196.08:21:50.93#ibcon#enter sib2, iclass 4, count 0 2006.196.08:21:50.93#ibcon#flushed, iclass 4, count 0 2006.196.08:21:50.93#ibcon#about to write, iclass 4, count 0 2006.196.08:21:50.93#ibcon#wrote, iclass 4, count 0 2006.196.08:21:50.93#ibcon#about to read 3, iclass 4, count 0 2006.196.08:21:50.97#ibcon#read 3, iclass 4, count 0 2006.196.08:21:50.97#ibcon#about to read 4, iclass 4, count 0 2006.196.08:21:50.97#ibcon#read 4, iclass 4, count 0 2006.196.08:21:50.97#ibcon#about to read 5, iclass 4, count 0 2006.196.08:21:50.97#ibcon#read 5, iclass 4, count 0 2006.196.08:21:50.97#ibcon#about to read 6, iclass 4, count 0 2006.196.08:21:50.97#ibcon#read 6, iclass 4, count 0 2006.196.08:21:50.97#ibcon#end of sib2, iclass 4, count 0 2006.196.08:21:50.97#ibcon#*after write, iclass 4, count 0 2006.196.08:21:50.97#ibcon#*before return 0, iclass 4, count 0 2006.196.08:21:50.97#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.196.08:21:50.97#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.196.08:21:50.97#ibcon#about to clear, iclass 4 cls_cnt 0 2006.196.08:21:50.97#ibcon#cleared, iclass 4 cls_cnt 0 2006.196.08:21:50.97$vc4f8/vb=2,4 2006.196.08:21:50.97#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.196.08:21:50.97#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.196.08:21:50.97#ibcon#ireg 11 cls_cnt 2 2006.196.08:21:50.97#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.196.08:21:51.03#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.196.08:21:51.03#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.196.08:21:51.03#ibcon#enter wrdev, iclass 6, count 2 2006.196.08:21:51.03#ibcon#first serial, iclass 6, count 2 2006.196.08:21:51.03#ibcon#enter sib2, iclass 6, count 2 2006.196.08:21:51.03#ibcon#flushed, iclass 6, count 2 2006.196.08:21:51.03#ibcon#about to write, iclass 6, count 2 2006.196.08:21:51.03#ibcon#wrote, iclass 6, count 2 2006.196.08:21:51.03#ibcon#about to read 3, iclass 6, count 2 2006.196.08:21:51.05#ibcon#read 3, iclass 6, count 2 2006.196.08:21:51.05#ibcon#about to read 4, iclass 6, count 2 2006.196.08:21:51.05#ibcon#read 4, iclass 6, count 2 2006.196.08:21:51.05#ibcon#about to read 5, iclass 6, count 2 2006.196.08:21:51.05#ibcon#read 5, iclass 6, count 2 2006.196.08:21:51.05#ibcon#about to read 6, iclass 6, count 2 2006.196.08:21:51.05#ibcon#read 6, iclass 6, count 2 2006.196.08:21:51.05#ibcon#end of sib2, iclass 6, count 2 2006.196.08:21:51.05#ibcon#*mode == 0, iclass 6, count 2 2006.196.08:21:51.05#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.196.08:21:51.05#ibcon#[27=AT02-04\r\n] 2006.196.08:21:51.05#ibcon#*before write, iclass 6, count 2 2006.196.08:21:51.05#ibcon#enter sib2, iclass 6, count 2 2006.196.08:21:51.05#ibcon#flushed, iclass 6, count 2 2006.196.08:21:51.05#ibcon#about to write, iclass 6, count 2 2006.196.08:21:51.05#ibcon#wrote, iclass 6, count 2 2006.196.08:21:51.05#ibcon#about to read 3, iclass 6, count 2 2006.196.08:21:51.08#ibcon#read 3, iclass 6, count 2 2006.196.08:21:51.08#ibcon#about to read 4, iclass 6, count 2 2006.196.08:21:51.08#ibcon#read 4, iclass 6, count 2 2006.196.08:21:51.08#ibcon#about to read 5, iclass 6, count 2 2006.196.08:21:51.08#ibcon#read 5, iclass 6, count 2 2006.196.08:21:51.08#ibcon#about to read 6, iclass 6, count 2 2006.196.08:21:51.08#ibcon#read 6, iclass 6, count 2 2006.196.08:21:51.08#ibcon#end of sib2, iclass 6, count 2 2006.196.08:21:51.08#ibcon#*after write, iclass 6, count 2 2006.196.08:21:51.08#ibcon#*before return 0, iclass 6, count 2 2006.196.08:21:51.08#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.196.08:21:51.08#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.196.08:21:51.08#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.196.08:21:51.08#ibcon#ireg 7 cls_cnt 0 2006.196.08:21:51.08#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.196.08:21:51.20#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.196.08:21:51.20#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.196.08:21:51.20#ibcon#enter wrdev, iclass 6, count 0 2006.196.08:21:51.20#ibcon#first serial, iclass 6, count 0 2006.196.08:21:51.20#ibcon#enter sib2, iclass 6, count 0 2006.196.08:21:51.20#ibcon#flushed, iclass 6, count 0 2006.196.08:21:51.20#ibcon#about to write, iclass 6, count 0 2006.196.08:21:51.20#ibcon#wrote, iclass 6, count 0 2006.196.08:21:51.20#ibcon#about to read 3, iclass 6, count 0 2006.196.08:21:51.23#ibcon#read 3, iclass 6, count 0 2006.196.08:21:51.23#ibcon#about to read 4, iclass 6, count 0 2006.196.08:21:51.23#ibcon#read 4, iclass 6, count 0 2006.196.08:21:51.23#ibcon#about to read 5, iclass 6, count 0 2006.196.08:21:51.23#ibcon#read 5, iclass 6, count 0 2006.196.08:21:51.23#ibcon#about to read 6, iclass 6, count 0 2006.196.08:21:51.23#ibcon#read 6, iclass 6, count 0 2006.196.08:21:51.23#ibcon#end of sib2, iclass 6, count 0 2006.196.08:21:51.23#ibcon#*mode == 0, iclass 6, count 0 2006.196.08:21:51.23#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.196.08:21:51.23#ibcon#[27=USB\r\n] 2006.196.08:21:51.23#ibcon#*before write, iclass 6, count 0 2006.196.08:21:51.23#ibcon#enter sib2, iclass 6, count 0 2006.196.08:21:51.23#ibcon#flushed, iclass 6, count 0 2006.196.08:21:51.23#ibcon#about to write, iclass 6, count 0 2006.196.08:21:51.23#ibcon#wrote, iclass 6, count 0 2006.196.08:21:51.23#ibcon#about to read 3, iclass 6, count 0 2006.196.08:21:51.26#ibcon#read 3, iclass 6, count 0 2006.196.08:21:51.26#ibcon#about to read 4, iclass 6, count 0 2006.196.08:21:51.26#ibcon#read 4, iclass 6, count 0 2006.196.08:21:51.26#ibcon#about to read 5, iclass 6, count 0 2006.196.08:21:51.26#ibcon#read 5, iclass 6, count 0 2006.196.08:21:51.26#ibcon#about to read 6, iclass 6, count 0 2006.196.08:21:51.26#ibcon#read 6, iclass 6, count 0 2006.196.08:21:51.26#ibcon#end of sib2, iclass 6, count 0 2006.196.08:21:51.26#ibcon#*after write, iclass 6, count 0 2006.196.08:21:51.26#ibcon#*before return 0, iclass 6, count 0 2006.196.08:21:51.26#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.196.08:21:51.26#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.196.08:21:51.26#ibcon#about to clear, iclass 6 cls_cnt 0 2006.196.08:21:51.26#ibcon#cleared, iclass 6 cls_cnt 0 2006.196.08:21:51.26$vc4f8/vblo=3,656.99 2006.196.08:21:51.26#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.196.08:21:51.26#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.196.08:21:51.26#ibcon#ireg 17 cls_cnt 0 2006.196.08:21:51.26#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.196.08:21:51.26#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.196.08:21:51.26#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.196.08:21:51.26#ibcon#enter wrdev, iclass 10, count 0 2006.196.08:21:51.26#ibcon#first serial, iclass 10, count 0 2006.196.08:21:51.26#ibcon#enter sib2, iclass 10, count 0 2006.196.08:21:51.26#ibcon#flushed, iclass 10, count 0 2006.196.08:21:51.26#ibcon#about to write, iclass 10, count 0 2006.196.08:21:51.26#ibcon#wrote, iclass 10, count 0 2006.196.08:21:51.26#ibcon#about to read 3, iclass 10, count 0 2006.196.08:21:51.28#ibcon#read 3, iclass 10, count 0 2006.196.08:21:51.28#ibcon#about to read 4, iclass 10, count 0 2006.196.08:21:51.28#ibcon#read 4, iclass 10, count 0 2006.196.08:21:51.28#ibcon#about to read 5, iclass 10, count 0 2006.196.08:21:51.28#ibcon#read 5, iclass 10, count 0 2006.196.08:21:51.28#ibcon#about to read 6, iclass 10, count 0 2006.196.08:21:51.28#ibcon#read 6, iclass 10, count 0 2006.196.08:21:51.28#ibcon#end of sib2, iclass 10, count 0 2006.196.08:21:51.28#ibcon#*mode == 0, iclass 10, count 0 2006.196.08:21:51.28#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.196.08:21:51.28#ibcon#[28=FRQ=03,656.99\r\n] 2006.196.08:21:51.28#ibcon#*before write, iclass 10, count 0 2006.196.08:21:51.28#ibcon#enter sib2, iclass 10, count 0 2006.196.08:21:51.28#ibcon#flushed, iclass 10, count 0 2006.196.08:21:51.28#ibcon#about to write, iclass 10, count 0 2006.196.08:21:51.28#ibcon#wrote, iclass 10, count 0 2006.196.08:21:51.28#ibcon#about to read 3, iclass 10, count 0 2006.196.08:21:51.32#ibcon#read 3, iclass 10, count 0 2006.196.08:21:51.32#ibcon#about to read 4, iclass 10, count 0 2006.196.08:21:51.32#ibcon#read 4, iclass 10, count 0 2006.196.08:21:51.32#ibcon#about to read 5, iclass 10, count 0 2006.196.08:21:51.32#ibcon#read 5, iclass 10, count 0 2006.196.08:21:51.32#ibcon#about to read 6, iclass 10, count 0 2006.196.08:21:51.32#ibcon#read 6, iclass 10, count 0 2006.196.08:21:51.32#ibcon#end of sib2, iclass 10, count 0 2006.196.08:21:51.32#ibcon#*after write, iclass 10, count 0 2006.196.08:21:51.32#ibcon#*before return 0, iclass 10, count 0 2006.196.08:21:51.32#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.196.08:21:51.32#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.196.08:21:51.32#ibcon#about to clear, iclass 10 cls_cnt 0 2006.196.08:21:51.32#ibcon#cleared, iclass 10 cls_cnt 0 2006.196.08:21:51.32$vc4f8/vb=3,4 2006.196.08:21:51.32#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.196.08:21:51.32#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.196.08:21:51.32#ibcon#ireg 11 cls_cnt 2 2006.196.08:21:51.32#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.196.08:21:51.38#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.196.08:21:51.38#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.196.08:21:51.38#ibcon#enter wrdev, iclass 12, count 2 2006.196.08:21:51.38#ibcon#first serial, iclass 12, count 2 2006.196.08:21:51.38#ibcon#enter sib2, iclass 12, count 2 2006.196.08:21:51.38#ibcon#flushed, iclass 12, count 2 2006.196.08:21:51.38#ibcon#about to write, iclass 12, count 2 2006.196.08:21:51.38#ibcon#wrote, iclass 12, count 2 2006.196.08:21:51.38#ibcon#about to read 3, iclass 12, count 2 2006.196.08:21:51.40#ibcon#read 3, iclass 12, count 2 2006.196.08:21:51.40#ibcon#about to read 4, iclass 12, count 2 2006.196.08:21:51.40#ibcon#read 4, iclass 12, count 2 2006.196.08:21:51.40#ibcon#about to read 5, iclass 12, count 2 2006.196.08:21:51.40#ibcon#read 5, iclass 12, count 2 2006.196.08:21:51.40#ibcon#about to read 6, iclass 12, count 2 2006.196.08:21:51.40#ibcon#read 6, iclass 12, count 2 2006.196.08:21:51.40#ibcon#end of sib2, iclass 12, count 2 2006.196.08:21:51.40#ibcon#*mode == 0, iclass 12, count 2 2006.196.08:21:51.40#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.196.08:21:51.40#ibcon#[27=AT03-04\r\n] 2006.196.08:21:51.40#ibcon#*before write, iclass 12, count 2 2006.196.08:21:51.40#ibcon#enter sib2, iclass 12, count 2 2006.196.08:21:51.40#ibcon#flushed, iclass 12, count 2 2006.196.08:21:51.40#ibcon#about to write, iclass 12, count 2 2006.196.08:21:51.40#ibcon#wrote, iclass 12, count 2 2006.196.08:21:51.40#ibcon#about to read 3, iclass 12, count 2 2006.196.08:21:51.43#ibcon#read 3, iclass 12, count 2 2006.196.08:21:51.43#ibcon#about to read 4, iclass 12, count 2 2006.196.08:21:51.43#ibcon#read 4, iclass 12, count 2 2006.196.08:21:51.43#ibcon#about to read 5, iclass 12, count 2 2006.196.08:21:51.43#ibcon#read 5, iclass 12, count 2 2006.196.08:21:51.43#ibcon#about to read 6, iclass 12, count 2 2006.196.08:21:51.43#ibcon#read 6, iclass 12, count 2 2006.196.08:21:51.43#ibcon#end of sib2, iclass 12, count 2 2006.196.08:21:51.43#ibcon#*after write, iclass 12, count 2 2006.196.08:21:51.43#ibcon#*before return 0, iclass 12, count 2 2006.196.08:21:51.43#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.196.08:21:51.43#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.196.08:21:51.43#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.196.08:21:51.43#ibcon#ireg 7 cls_cnt 0 2006.196.08:21:51.43#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.196.08:21:51.55#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.196.08:21:51.55#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.196.08:21:51.55#ibcon#enter wrdev, iclass 12, count 0 2006.196.08:21:51.55#ibcon#first serial, iclass 12, count 0 2006.196.08:21:51.55#ibcon#enter sib2, iclass 12, count 0 2006.196.08:21:51.55#ibcon#flushed, iclass 12, count 0 2006.196.08:21:51.55#ibcon#about to write, iclass 12, count 0 2006.196.08:21:51.55#ibcon#wrote, iclass 12, count 0 2006.196.08:21:51.55#ibcon#about to read 3, iclass 12, count 0 2006.196.08:21:51.57#ibcon#read 3, iclass 12, count 0 2006.196.08:21:51.57#ibcon#about to read 4, iclass 12, count 0 2006.196.08:21:51.57#ibcon#read 4, iclass 12, count 0 2006.196.08:21:51.57#ibcon#about to read 5, iclass 12, count 0 2006.196.08:21:51.57#ibcon#read 5, iclass 12, count 0 2006.196.08:21:51.57#ibcon#about to read 6, iclass 12, count 0 2006.196.08:21:51.57#ibcon#read 6, iclass 12, count 0 2006.196.08:21:51.57#ibcon#end of sib2, iclass 12, count 0 2006.196.08:21:51.57#ibcon#*mode == 0, iclass 12, count 0 2006.196.08:21:51.57#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.196.08:21:51.57#ibcon#[27=USB\r\n] 2006.196.08:21:51.57#ibcon#*before write, iclass 12, count 0 2006.196.08:21:51.57#ibcon#enter sib2, iclass 12, count 0 2006.196.08:21:51.57#ibcon#flushed, iclass 12, count 0 2006.196.08:21:51.57#ibcon#about to write, iclass 12, count 0 2006.196.08:21:51.57#ibcon#wrote, iclass 12, count 0 2006.196.08:21:51.57#ibcon#about to read 3, iclass 12, count 0 2006.196.08:21:51.60#ibcon#read 3, iclass 12, count 0 2006.196.08:21:51.60#ibcon#about to read 4, iclass 12, count 0 2006.196.08:21:51.60#ibcon#read 4, iclass 12, count 0 2006.196.08:21:51.60#ibcon#about to read 5, iclass 12, count 0 2006.196.08:21:51.60#ibcon#read 5, iclass 12, count 0 2006.196.08:21:51.60#ibcon#about to read 6, iclass 12, count 0 2006.196.08:21:51.60#ibcon#read 6, iclass 12, count 0 2006.196.08:21:51.60#ibcon#end of sib2, iclass 12, count 0 2006.196.08:21:51.60#ibcon#*after write, iclass 12, count 0 2006.196.08:21:51.60#ibcon#*before return 0, iclass 12, count 0 2006.196.08:21:51.60#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.196.08:21:51.60#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.196.08:21:51.60#ibcon#about to clear, iclass 12 cls_cnt 0 2006.196.08:21:51.60#ibcon#cleared, iclass 12 cls_cnt 0 2006.196.08:21:51.60$vc4f8/vblo=4,712.99 2006.196.08:21:51.60#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.196.08:21:51.60#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.196.08:21:51.60#ibcon#ireg 17 cls_cnt 0 2006.196.08:21:51.60#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.196.08:21:51.60#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.196.08:21:51.60#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.196.08:21:51.60#ibcon#enter wrdev, iclass 14, count 0 2006.196.08:21:51.60#ibcon#first serial, iclass 14, count 0 2006.196.08:21:51.60#ibcon#enter sib2, iclass 14, count 0 2006.196.08:21:51.60#ibcon#flushed, iclass 14, count 0 2006.196.08:21:51.60#ibcon#about to write, iclass 14, count 0 2006.196.08:21:51.60#ibcon#wrote, iclass 14, count 0 2006.196.08:21:51.60#ibcon#about to read 3, iclass 14, count 0 2006.196.08:21:51.62#ibcon#read 3, iclass 14, count 0 2006.196.08:21:51.62#ibcon#about to read 4, iclass 14, count 0 2006.196.08:21:51.62#ibcon#read 4, iclass 14, count 0 2006.196.08:21:51.62#ibcon#about to read 5, iclass 14, count 0 2006.196.08:21:51.62#ibcon#read 5, iclass 14, count 0 2006.196.08:21:51.62#ibcon#about to read 6, iclass 14, count 0 2006.196.08:21:51.62#ibcon#read 6, iclass 14, count 0 2006.196.08:21:51.62#ibcon#end of sib2, iclass 14, count 0 2006.196.08:21:51.62#ibcon#*mode == 0, iclass 14, count 0 2006.196.08:21:51.62#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.196.08:21:51.62#ibcon#[28=FRQ=04,712.99\r\n] 2006.196.08:21:51.62#ibcon#*before write, iclass 14, count 0 2006.196.08:21:51.62#ibcon#enter sib2, iclass 14, count 0 2006.196.08:21:51.62#ibcon#flushed, iclass 14, count 0 2006.196.08:21:51.62#ibcon#about to write, iclass 14, count 0 2006.196.08:21:51.62#ibcon#wrote, iclass 14, count 0 2006.196.08:21:51.62#ibcon#about to read 3, iclass 14, count 0 2006.196.08:21:51.66#ibcon#read 3, iclass 14, count 0 2006.196.08:21:51.66#ibcon#about to read 4, iclass 14, count 0 2006.196.08:21:51.66#ibcon#read 4, iclass 14, count 0 2006.196.08:21:51.66#ibcon#about to read 5, iclass 14, count 0 2006.196.08:21:51.66#ibcon#read 5, iclass 14, count 0 2006.196.08:21:51.66#ibcon#about to read 6, iclass 14, count 0 2006.196.08:21:51.66#ibcon#read 6, iclass 14, count 0 2006.196.08:21:51.66#ibcon#end of sib2, iclass 14, count 0 2006.196.08:21:51.66#ibcon#*after write, iclass 14, count 0 2006.196.08:21:51.66#ibcon#*before return 0, iclass 14, count 0 2006.196.08:21:51.66#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.196.08:21:51.66#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.196.08:21:51.66#ibcon#about to clear, iclass 14 cls_cnt 0 2006.196.08:21:51.66#ibcon#cleared, iclass 14 cls_cnt 0 2006.196.08:21:51.66$vc4f8/vb=4,4 2006.196.08:21:51.66#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.196.08:21:51.66#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.196.08:21:51.66#ibcon#ireg 11 cls_cnt 2 2006.196.08:21:51.66#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.196.08:21:51.72#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.196.08:21:51.72#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.196.08:21:51.72#ibcon#enter wrdev, iclass 16, count 2 2006.196.08:21:51.72#ibcon#first serial, iclass 16, count 2 2006.196.08:21:51.72#ibcon#enter sib2, iclass 16, count 2 2006.196.08:21:51.72#ibcon#flushed, iclass 16, count 2 2006.196.08:21:51.72#ibcon#about to write, iclass 16, count 2 2006.196.08:21:51.72#ibcon#wrote, iclass 16, count 2 2006.196.08:21:51.72#ibcon#about to read 3, iclass 16, count 2 2006.196.08:21:51.74#ibcon#read 3, iclass 16, count 2 2006.196.08:21:51.74#ibcon#about to read 4, iclass 16, count 2 2006.196.08:21:51.74#ibcon#read 4, iclass 16, count 2 2006.196.08:21:51.74#ibcon#about to read 5, iclass 16, count 2 2006.196.08:21:51.74#ibcon#read 5, iclass 16, count 2 2006.196.08:21:51.74#ibcon#about to read 6, iclass 16, count 2 2006.196.08:21:51.74#ibcon#read 6, iclass 16, count 2 2006.196.08:21:51.74#ibcon#end of sib2, iclass 16, count 2 2006.196.08:21:51.74#ibcon#*mode == 0, iclass 16, count 2 2006.196.08:21:51.74#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.196.08:21:51.74#ibcon#[27=AT04-04\r\n] 2006.196.08:21:51.74#ibcon#*before write, iclass 16, count 2 2006.196.08:21:51.74#ibcon#enter sib2, iclass 16, count 2 2006.196.08:21:51.74#ibcon#flushed, iclass 16, count 2 2006.196.08:21:51.74#ibcon#about to write, iclass 16, count 2 2006.196.08:21:51.74#ibcon#wrote, iclass 16, count 2 2006.196.08:21:51.74#ibcon#about to read 3, iclass 16, count 2 2006.196.08:21:51.77#ibcon#read 3, iclass 16, count 2 2006.196.08:21:51.77#ibcon#about to read 4, iclass 16, count 2 2006.196.08:21:51.77#ibcon#read 4, iclass 16, count 2 2006.196.08:21:51.77#ibcon#about to read 5, iclass 16, count 2 2006.196.08:21:51.77#ibcon#read 5, iclass 16, count 2 2006.196.08:21:51.77#ibcon#about to read 6, iclass 16, count 2 2006.196.08:21:51.77#ibcon#read 6, iclass 16, count 2 2006.196.08:21:51.77#ibcon#end of sib2, iclass 16, count 2 2006.196.08:21:51.77#ibcon#*after write, iclass 16, count 2 2006.196.08:21:51.77#ibcon#*before return 0, iclass 16, count 2 2006.196.08:21:51.77#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.196.08:21:51.77#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.196.08:21:51.77#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.196.08:21:51.77#ibcon#ireg 7 cls_cnt 0 2006.196.08:21:51.77#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.196.08:21:51.89#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.196.08:21:51.89#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.196.08:21:51.89#ibcon#enter wrdev, iclass 16, count 0 2006.196.08:21:51.89#ibcon#first serial, iclass 16, count 0 2006.196.08:21:51.89#ibcon#enter sib2, iclass 16, count 0 2006.196.08:21:51.89#ibcon#flushed, iclass 16, count 0 2006.196.08:21:51.89#ibcon#about to write, iclass 16, count 0 2006.196.08:21:51.89#ibcon#wrote, iclass 16, count 0 2006.196.08:21:51.89#ibcon#about to read 3, iclass 16, count 0 2006.196.08:21:51.91#ibcon#read 3, iclass 16, count 0 2006.196.08:21:51.91#ibcon#about to read 4, iclass 16, count 0 2006.196.08:21:51.91#ibcon#read 4, iclass 16, count 0 2006.196.08:21:51.91#ibcon#about to read 5, iclass 16, count 0 2006.196.08:21:51.91#ibcon#read 5, iclass 16, count 0 2006.196.08:21:51.91#ibcon#about to read 6, iclass 16, count 0 2006.196.08:21:51.91#ibcon#read 6, iclass 16, count 0 2006.196.08:21:51.91#ibcon#end of sib2, iclass 16, count 0 2006.196.08:21:51.91#ibcon#*mode == 0, iclass 16, count 0 2006.196.08:21:51.91#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.196.08:21:51.91#ibcon#[27=USB\r\n] 2006.196.08:21:51.91#ibcon#*before write, iclass 16, count 0 2006.196.08:21:51.91#ibcon#enter sib2, iclass 16, count 0 2006.196.08:21:51.91#ibcon#flushed, iclass 16, count 0 2006.196.08:21:51.91#ibcon#about to write, iclass 16, count 0 2006.196.08:21:51.91#ibcon#wrote, iclass 16, count 0 2006.196.08:21:51.91#ibcon#about to read 3, iclass 16, count 0 2006.196.08:21:51.94#ibcon#read 3, iclass 16, count 0 2006.196.08:21:51.94#ibcon#about to read 4, iclass 16, count 0 2006.196.08:21:51.94#ibcon#read 4, iclass 16, count 0 2006.196.08:21:51.94#ibcon#about to read 5, iclass 16, count 0 2006.196.08:21:51.94#ibcon#read 5, iclass 16, count 0 2006.196.08:21:51.94#ibcon#about to read 6, iclass 16, count 0 2006.196.08:21:51.94#ibcon#read 6, iclass 16, count 0 2006.196.08:21:51.94#ibcon#end of sib2, iclass 16, count 0 2006.196.08:21:51.94#ibcon#*after write, iclass 16, count 0 2006.196.08:21:51.94#ibcon#*before return 0, iclass 16, count 0 2006.196.08:21:51.94#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.196.08:21:51.94#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.196.08:21:51.94#ibcon#about to clear, iclass 16 cls_cnt 0 2006.196.08:21:51.94#ibcon#cleared, iclass 16 cls_cnt 0 2006.196.08:21:51.94$vc4f8/vblo=5,744.99 2006.196.08:21:51.94#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.196.08:21:51.94#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.196.08:21:51.94#ibcon#ireg 17 cls_cnt 0 2006.196.08:21:51.94#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.196.08:21:51.94#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.196.08:21:51.94#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.196.08:21:51.94#ibcon#enter wrdev, iclass 18, count 0 2006.196.08:21:51.94#ibcon#first serial, iclass 18, count 0 2006.196.08:21:51.94#ibcon#enter sib2, iclass 18, count 0 2006.196.08:21:51.94#ibcon#flushed, iclass 18, count 0 2006.196.08:21:51.94#ibcon#about to write, iclass 18, count 0 2006.196.08:21:51.94#ibcon#wrote, iclass 18, count 0 2006.196.08:21:51.94#ibcon#about to read 3, iclass 18, count 0 2006.196.08:21:51.96#ibcon#read 3, iclass 18, count 0 2006.196.08:21:51.96#ibcon#about to read 4, iclass 18, count 0 2006.196.08:21:51.96#ibcon#read 4, iclass 18, count 0 2006.196.08:21:51.96#ibcon#about to read 5, iclass 18, count 0 2006.196.08:21:51.96#ibcon#read 5, iclass 18, count 0 2006.196.08:21:51.96#ibcon#about to read 6, iclass 18, count 0 2006.196.08:21:51.96#ibcon#read 6, iclass 18, count 0 2006.196.08:21:51.96#ibcon#end of sib2, iclass 18, count 0 2006.196.08:21:51.96#ibcon#*mode == 0, iclass 18, count 0 2006.196.08:21:51.96#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.196.08:21:51.96#ibcon#[28=FRQ=05,744.99\r\n] 2006.196.08:21:51.96#ibcon#*before write, iclass 18, count 0 2006.196.08:21:51.96#ibcon#enter sib2, iclass 18, count 0 2006.196.08:21:51.96#ibcon#flushed, iclass 18, count 0 2006.196.08:21:51.96#ibcon#about to write, iclass 18, count 0 2006.196.08:21:51.96#ibcon#wrote, iclass 18, count 0 2006.196.08:21:51.96#ibcon#about to read 3, iclass 18, count 0 2006.196.08:21:52.00#ibcon#read 3, iclass 18, count 0 2006.196.08:21:52.00#ibcon#about to read 4, iclass 18, count 0 2006.196.08:21:52.00#ibcon#read 4, iclass 18, count 0 2006.196.08:21:52.00#ibcon#about to read 5, iclass 18, count 0 2006.196.08:21:52.00#ibcon#read 5, iclass 18, count 0 2006.196.08:21:52.00#ibcon#about to read 6, iclass 18, count 0 2006.196.08:21:52.00#ibcon#read 6, iclass 18, count 0 2006.196.08:21:52.00#ibcon#end of sib2, iclass 18, count 0 2006.196.08:21:52.00#ibcon#*after write, iclass 18, count 0 2006.196.08:21:52.00#ibcon#*before return 0, iclass 18, count 0 2006.196.08:21:52.00#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.196.08:21:52.00#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.196.08:21:52.00#ibcon#about to clear, iclass 18 cls_cnt 0 2006.196.08:21:52.00#ibcon#cleared, iclass 18 cls_cnt 0 2006.196.08:21:52.00$vc4f8/vb=5,4 2006.196.08:21:52.00#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.196.08:21:52.00#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.196.08:21:52.00#ibcon#ireg 11 cls_cnt 2 2006.196.08:21:52.00#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.196.08:21:52.06#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.196.08:21:52.06#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.196.08:21:52.06#ibcon#enter wrdev, iclass 20, count 2 2006.196.08:21:52.06#ibcon#first serial, iclass 20, count 2 2006.196.08:21:52.06#ibcon#enter sib2, iclass 20, count 2 2006.196.08:21:52.06#ibcon#flushed, iclass 20, count 2 2006.196.08:21:52.06#ibcon#about to write, iclass 20, count 2 2006.196.08:21:52.06#ibcon#wrote, iclass 20, count 2 2006.196.08:21:52.06#ibcon#about to read 3, iclass 20, count 2 2006.196.08:21:52.08#ibcon#read 3, iclass 20, count 2 2006.196.08:21:52.08#ibcon#about to read 4, iclass 20, count 2 2006.196.08:21:52.08#ibcon#read 4, iclass 20, count 2 2006.196.08:21:52.08#ibcon#about to read 5, iclass 20, count 2 2006.196.08:21:52.08#ibcon#read 5, iclass 20, count 2 2006.196.08:21:52.08#ibcon#about to read 6, iclass 20, count 2 2006.196.08:21:52.08#ibcon#read 6, iclass 20, count 2 2006.196.08:21:52.08#ibcon#end of sib2, iclass 20, count 2 2006.196.08:21:52.08#ibcon#*mode == 0, iclass 20, count 2 2006.196.08:21:52.08#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.196.08:21:52.08#ibcon#[27=AT05-04\r\n] 2006.196.08:21:52.08#ibcon#*before write, iclass 20, count 2 2006.196.08:21:52.08#ibcon#enter sib2, iclass 20, count 2 2006.196.08:21:52.08#ibcon#flushed, iclass 20, count 2 2006.196.08:21:52.08#ibcon#about to write, iclass 20, count 2 2006.196.08:21:52.08#ibcon#wrote, iclass 20, count 2 2006.196.08:21:52.08#ibcon#about to read 3, iclass 20, count 2 2006.196.08:21:52.11#ibcon#read 3, iclass 20, count 2 2006.196.08:21:52.11#ibcon#about to read 4, iclass 20, count 2 2006.196.08:21:52.11#ibcon#read 4, iclass 20, count 2 2006.196.08:21:52.11#ibcon#about to read 5, iclass 20, count 2 2006.196.08:21:52.11#ibcon#read 5, iclass 20, count 2 2006.196.08:21:52.11#ibcon#about to read 6, iclass 20, count 2 2006.196.08:21:52.11#ibcon#read 6, iclass 20, count 2 2006.196.08:21:52.11#ibcon#end of sib2, iclass 20, count 2 2006.196.08:21:52.11#ibcon#*after write, iclass 20, count 2 2006.196.08:21:52.11#ibcon#*before return 0, iclass 20, count 2 2006.196.08:21:52.11#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.196.08:21:52.11#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.196.08:21:52.11#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.196.08:21:52.11#ibcon#ireg 7 cls_cnt 0 2006.196.08:21:52.11#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.196.08:21:52.23#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.196.08:21:52.23#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.196.08:21:52.23#ibcon#enter wrdev, iclass 20, count 0 2006.196.08:21:52.23#ibcon#first serial, iclass 20, count 0 2006.196.08:21:52.23#ibcon#enter sib2, iclass 20, count 0 2006.196.08:21:52.23#ibcon#flushed, iclass 20, count 0 2006.196.08:21:52.23#ibcon#about to write, iclass 20, count 0 2006.196.08:21:52.23#ibcon#wrote, iclass 20, count 0 2006.196.08:21:52.23#ibcon#about to read 3, iclass 20, count 0 2006.196.08:21:52.25#ibcon#read 3, iclass 20, count 0 2006.196.08:21:52.25#ibcon#about to read 4, iclass 20, count 0 2006.196.08:21:52.25#ibcon#read 4, iclass 20, count 0 2006.196.08:21:52.25#ibcon#about to read 5, iclass 20, count 0 2006.196.08:21:52.25#ibcon#read 5, iclass 20, count 0 2006.196.08:21:52.25#ibcon#about to read 6, iclass 20, count 0 2006.196.08:21:52.25#ibcon#read 6, iclass 20, count 0 2006.196.08:21:52.25#ibcon#end of sib2, iclass 20, count 0 2006.196.08:21:52.25#ibcon#*mode == 0, iclass 20, count 0 2006.196.08:21:52.25#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.196.08:21:52.25#ibcon#[27=USB\r\n] 2006.196.08:21:52.25#ibcon#*before write, iclass 20, count 0 2006.196.08:21:52.25#ibcon#enter sib2, iclass 20, count 0 2006.196.08:21:52.25#ibcon#flushed, iclass 20, count 0 2006.196.08:21:52.25#ibcon#about to write, iclass 20, count 0 2006.196.08:21:52.25#ibcon#wrote, iclass 20, count 0 2006.196.08:21:52.25#ibcon#about to read 3, iclass 20, count 0 2006.196.08:21:52.28#ibcon#read 3, iclass 20, count 0 2006.196.08:21:52.28#ibcon#about to read 4, iclass 20, count 0 2006.196.08:21:52.28#ibcon#read 4, iclass 20, count 0 2006.196.08:21:52.28#ibcon#about to read 5, iclass 20, count 0 2006.196.08:21:52.28#ibcon#read 5, iclass 20, count 0 2006.196.08:21:52.28#ibcon#about to read 6, iclass 20, count 0 2006.196.08:21:52.28#ibcon#read 6, iclass 20, count 0 2006.196.08:21:52.28#ibcon#end of sib2, iclass 20, count 0 2006.196.08:21:52.28#ibcon#*after write, iclass 20, count 0 2006.196.08:21:52.28#ibcon#*before return 0, iclass 20, count 0 2006.196.08:21:52.28#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.196.08:21:52.28#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.196.08:21:52.28#ibcon#about to clear, iclass 20 cls_cnt 0 2006.196.08:21:52.28#ibcon#cleared, iclass 20 cls_cnt 0 2006.196.08:21:52.28$vc4f8/vblo=6,752.99 2006.196.08:21:52.28#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.196.08:21:52.28#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.196.08:21:52.28#ibcon#ireg 17 cls_cnt 0 2006.196.08:21:52.28#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.196.08:21:52.28#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.196.08:21:52.28#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.196.08:21:52.28#ibcon#enter wrdev, iclass 22, count 0 2006.196.08:21:52.28#ibcon#first serial, iclass 22, count 0 2006.196.08:21:52.28#ibcon#enter sib2, iclass 22, count 0 2006.196.08:21:52.28#ibcon#flushed, iclass 22, count 0 2006.196.08:21:52.28#ibcon#about to write, iclass 22, count 0 2006.196.08:21:52.28#ibcon#wrote, iclass 22, count 0 2006.196.08:21:52.28#ibcon#about to read 3, iclass 22, count 0 2006.196.08:21:52.30#ibcon#read 3, iclass 22, count 0 2006.196.08:21:52.30#ibcon#about to read 4, iclass 22, count 0 2006.196.08:21:52.30#ibcon#read 4, iclass 22, count 0 2006.196.08:21:52.30#ibcon#about to read 5, iclass 22, count 0 2006.196.08:21:52.30#ibcon#read 5, iclass 22, count 0 2006.196.08:21:52.30#ibcon#about to read 6, iclass 22, count 0 2006.196.08:21:52.30#ibcon#read 6, iclass 22, count 0 2006.196.08:21:52.30#ibcon#end of sib2, iclass 22, count 0 2006.196.08:21:52.30#ibcon#*mode == 0, iclass 22, count 0 2006.196.08:21:52.30#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.196.08:21:52.30#ibcon#[28=FRQ=06,752.99\r\n] 2006.196.08:21:52.30#ibcon#*before write, iclass 22, count 0 2006.196.08:21:52.30#ibcon#enter sib2, iclass 22, count 0 2006.196.08:21:52.30#ibcon#flushed, iclass 22, count 0 2006.196.08:21:52.30#ibcon#about to write, iclass 22, count 0 2006.196.08:21:52.30#ibcon#wrote, iclass 22, count 0 2006.196.08:21:52.30#ibcon#about to read 3, iclass 22, count 0 2006.196.08:21:52.34#ibcon#read 3, iclass 22, count 0 2006.196.08:21:52.34#ibcon#about to read 4, iclass 22, count 0 2006.196.08:21:52.34#ibcon#read 4, iclass 22, count 0 2006.196.08:21:52.34#ibcon#about to read 5, iclass 22, count 0 2006.196.08:21:52.34#ibcon#read 5, iclass 22, count 0 2006.196.08:21:52.34#ibcon#about to read 6, iclass 22, count 0 2006.196.08:21:52.34#ibcon#read 6, iclass 22, count 0 2006.196.08:21:52.34#ibcon#end of sib2, iclass 22, count 0 2006.196.08:21:52.34#ibcon#*after write, iclass 22, count 0 2006.196.08:21:52.34#ibcon#*before return 0, iclass 22, count 0 2006.196.08:21:52.34#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.196.08:21:52.34#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.196.08:21:52.34#ibcon#about to clear, iclass 22 cls_cnt 0 2006.196.08:21:52.34#ibcon#cleared, iclass 22 cls_cnt 0 2006.196.08:21:52.34$vc4f8/vb=6,4 2006.196.08:21:52.34#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.196.08:21:52.34#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.196.08:21:52.34#ibcon#ireg 11 cls_cnt 2 2006.196.08:21:52.34#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.196.08:21:52.40#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.196.08:21:52.40#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.196.08:21:52.40#ibcon#enter wrdev, iclass 24, count 2 2006.196.08:21:52.40#ibcon#first serial, iclass 24, count 2 2006.196.08:21:52.40#ibcon#enter sib2, iclass 24, count 2 2006.196.08:21:52.40#ibcon#flushed, iclass 24, count 2 2006.196.08:21:52.40#ibcon#about to write, iclass 24, count 2 2006.196.08:21:52.40#ibcon#wrote, iclass 24, count 2 2006.196.08:21:52.40#ibcon#about to read 3, iclass 24, count 2 2006.196.08:21:52.42#ibcon#read 3, iclass 24, count 2 2006.196.08:21:52.42#ibcon#about to read 4, iclass 24, count 2 2006.196.08:21:52.42#ibcon#read 4, iclass 24, count 2 2006.196.08:21:52.42#ibcon#about to read 5, iclass 24, count 2 2006.196.08:21:52.42#ibcon#read 5, iclass 24, count 2 2006.196.08:21:52.42#ibcon#about to read 6, iclass 24, count 2 2006.196.08:21:52.42#ibcon#read 6, iclass 24, count 2 2006.196.08:21:52.42#ibcon#end of sib2, iclass 24, count 2 2006.196.08:21:52.42#ibcon#*mode == 0, iclass 24, count 2 2006.196.08:21:52.42#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.196.08:21:52.42#ibcon#[27=AT06-04\r\n] 2006.196.08:21:52.42#ibcon#*before write, iclass 24, count 2 2006.196.08:21:52.42#ibcon#enter sib2, iclass 24, count 2 2006.196.08:21:52.42#ibcon#flushed, iclass 24, count 2 2006.196.08:21:52.42#ibcon#about to write, iclass 24, count 2 2006.196.08:21:52.42#ibcon#wrote, iclass 24, count 2 2006.196.08:21:52.42#ibcon#about to read 3, iclass 24, count 2 2006.196.08:21:52.45#ibcon#read 3, iclass 24, count 2 2006.196.08:21:52.45#ibcon#about to read 4, iclass 24, count 2 2006.196.08:21:52.45#ibcon#read 4, iclass 24, count 2 2006.196.08:21:52.45#ibcon#about to read 5, iclass 24, count 2 2006.196.08:21:52.45#ibcon#read 5, iclass 24, count 2 2006.196.08:21:52.45#ibcon#about to read 6, iclass 24, count 2 2006.196.08:21:52.45#ibcon#read 6, iclass 24, count 2 2006.196.08:21:52.45#ibcon#end of sib2, iclass 24, count 2 2006.196.08:21:52.45#ibcon#*after write, iclass 24, count 2 2006.196.08:21:52.45#ibcon#*before return 0, iclass 24, count 2 2006.196.08:21:52.45#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.196.08:21:52.45#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.196.08:21:52.45#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.196.08:21:52.45#ibcon#ireg 7 cls_cnt 0 2006.196.08:21:52.45#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.196.08:21:52.57#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.196.08:21:52.57#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.196.08:21:52.57#ibcon#enter wrdev, iclass 24, count 0 2006.196.08:21:52.57#ibcon#first serial, iclass 24, count 0 2006.196.08:21:52.57#ibcon#enter sib2, iclass 24, count 0 2006.196.08:21:52.57#ibcon#flushed, iclass 24, count 0 2006.196.08:21:52.57#ibcon#about to write, iclass 24, count 0 2006.196.08:21:52.57#ibcon#wrote, iclass 24, count 0 2006.196.08:21:52.57#ibcon#about to read 3, iclass 24, count 0 2006.196.08:21:52.59#ibcon#read 3, iclass 24, count 0 2006.196.08:21:52.59#ibcon#about to read 4, iclass 24, count 0 2006.196.08:21:52.59#ibcon#read 4, iclass 24, count 0 2006.196.08:21:52.59#ibcon#about to read 5, iclass 24, count 0 2006.196.08:21:52.59#ibcon#read 5, iclass 24, count 0 2006.196.08:21:52.59#ibcon#about to read 6, iclass 24, count 0 2006.196.08:21:52.59#ibcon#read 6, iclass 24, count 0 2006.196.08:21:52.59#ibcon#end of sib2, iclass 24, count 0 2006.196.08:21:52.59#ibcon#*mode == 0, iclass 24, count 0 2006.196.08:21:52.59#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.196.08:21:52.59#ibcon#[27=USB\r\n] 2006.196.08:21:52.59#ibcon#*before write, iclass 24, count 0 2006.196.08:21:52.59#ibcon#enter sib2, iclass 24, count 0 2006.196.08:21:52.59#ibcon#flushed, iclass 24, count 0 2006.196.08:21:52.59#ibcon#about to write, iclass 24, count 0 2006.196.08:21:52.59#ibcon#wrote, iclass 24, count 0 2006.196.08:21:52.59#ibcon#about to read 3, iclass 24, count 0 2006.196.08:21:52.62#ibcon#read 3, iclass 24, count 0 2006.196.08:21:52.62#ibcon#about to read 4, iclass 24, count 0 2006.196.08:21:52.62#ibcon#read 4, iclass 24, count 0 2006.196.08:21:52.62#ibcon#about to read 5, iclass 24, count 0 2006.196.08:21:52.62#ibcon#read 5, iclass 24, count 0 2006.196.08:21:52.62#ibcon#about to read 6, iclass 24, count 0 2006.196.08:21:52.62#ibcon#read 6, iclass 24, count 0 2006.196.08:21:52.62#ibcon#end of sib2, iclass 24, count 0 2006.196.08:21:52.62#ibcon#*after write, iclass 24, count 0 2006.196.08:21:52.62#ibcon#*before return 0, iclass 24, count 0 2006.196.08:21:52.62#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.196.08:21:52.62#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.196.08:21:52.62#ibcon#about to clear, iclass 24 cls_cnt 0 2006.196.08:21:52.62#ibcon#cleared, iclass 24 cls_cnt 0 2006.196.08:21:52.62$vc4f8/vabw=wide 2006.196.08:21:52.62#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.196.08:21:52.62#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.196.08:21:52.62#ibcon#ireg 8 cls_cnt 0 2006.196.08:21:52.62#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.196.08:21:52.62#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.196.08:21:52.62#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.196.08:21:52.62#ibcon#enter wrdev, iclass 26, count 0 2006.196.08:21:52.62#ibcon#first serial, iclass 26, count 0 2006.196.08:21:52.62#ibcon#enter sib2, iclass 26, count 0 2006.196.08:21:52.62#ibcon#flushed, iclass 26, count 0 2006.196.08:21:52.62#ibcon#about to write, iclass 26, count 0 2006.196.08:21:52.62#ibcon#wrote, iclass 26, count 0 2006.196.08:21:52.62#ibcon#about to read 3, iclass 26, count 0 2006.196.08:21:52.64#ibcon#read 3, iclass 26, count 0 2006.196.08:21:52.64#ibcon#about to read 4, iclass 26, count 0 2006.196.08:21:52.64#ibcon#read 4, iclass 26, count 0 2006.196.08:21:52.64#ibcon#about to read 5, iclass 26, count 0 2006.196.08:21:52.64#ibcon#read 5, iclass 26, count 0 2006.196.08:21:52.64#ibcon#about to read 6, iclass 26, count 0 2006.196.08:21:52.64#ibcon#read 6, iclass 26, count 0 2006.196.08:21:52.64#ibcon#end of sib2, iclass 26, count 0 2006.196.08:21:52.64#ibcon#*mode == 0, iclass 26, count 0 2006.196.08:21:52.64#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.196.08:21:52.64#ibcon#[25=BW32\r\n] 2006.196.08:21:52.64#ibcon#*before write, iclass 26, count 0 2006.196.08:21:52.64#ibcon#enter sib2, iclass 26, count 0 2006.196.08:21:52.64#ibcon#flushed, iclass 26, count 0 2006.196.08:21:52.64#ibcon#about to write, iclass 26, count 0 2006.196.08:21:52.64#ibcon#wrote, iclass 26, count 0 2006.196.08:21:52.64#ibcon#about to read 3, iclass 26, count 0 2006.196.08:21:52.67#ibcon#read 3, iclass 26, count 0 2006.196.08:21:52.67#ibcon#about to read 4, iclass 26, count 0 2006.196.08:21:52.67#ibcon#read 4, iclass 26, count 0 2006.196.08:21:52.67#ibcon#about to read 5, iclass 26, count 0 2006.196.08:21:52.67#ibcon#read 5, iclass 26, count 0 2006.196.08:21:52.67#ibcon#about to read 6, iclass 26, count 0 2006.196.08:21:52.67#ibcon#read 6, iclass 26, count 0 2006.196.08:21:52.67#ibcon#end of sib2, iclass 26, count 0 2006.196.08:21:52.67#ibcon#*after write, iclass 26, count 0 2006.196.08:21:52.67#ibcon#*before return 0, iclass 26, count 0 2006.196.08:21:52.67#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.196.08:21:52.67#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.196.08:21:52.67#ibcon#about to clear, iclass 26 cls_cnt 0 2006.196.08:21:52.67#ibcon#cleared, iclass 26 cls_cnt 0 2006.196.08:21:52.67$vc4f8/vbbw=wide 2006.196.08:21:52.67#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.196.08:21:52.67#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.196.08:21:52.67#ibcon#ireg 8 cls_cnt 0 2006.196.08:21:52.67#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.196.08:21:52.74#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.196.08:21:52.74#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.196.08:21:52.74#ibcon#enter wrdev, iclass 28, count 0 2006.196.08:21:52.74#ibcon#first serial, iclass 28, count 0 2006.196.08:21:52.74#ibcon#enter sib2, iclass 28, count 0 2006.196.08:21:52.74#ibcon#flushed, iclass 28, count 0 2006.196.08:21:52.74#ibcon#about to write, iclass 28, count 0 2006.196.08:21:52.74#ibcon#wrote, iclass 28, count 0 2006.196.08:21:52.74#ibcon#about to read 3, iclass 28, count 0 2006.196.08:21:52.76#ibcon#read 3, iclass 28, count 0 2006.196.08:21:52.76#ibcon#about to read 4, iclass 28, count 0 2006.196.08:21:52.76#ibcon#read 4, iclass 28, count 0 2006.196.08:21:52.76#ibcon#about to read 5, iclass 28, count 0 2006.196.08:21:52.76#ibcon#read 5, iclass 28, count 0 2006.196.08:21:52.76#ibcon#about to read 6, iclass 28, count 0 2006.196.08:21:52.76#ibcon#read 6, iclass 28, count 0 2006.196.08:21:52.76#ibcon#end of sib2, iclass 28, count 0 2006.196.08:21:52.76#ibcon#*mode == 0, iclass 28, count 0 2006.196.08:21:52.76#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.196.08:21:52.76#ibcon#[27=BW32\r\n] 2006.196.08:21:52.76#ibcon#*before write, iclass 28, count 0 2006.196.08:21:52.76#ibcon#enter sib2, iclass 28, count 0 2006.196.08:21:52.76#ibcon#flushed, iclass 28, count 0 2006.196.08:21:52.76#ibcon#about to write, iclass 28, count 0 2006.196.08:21:52.76#ibcon#wrote, iclass 28, count 0 2006.196.08:21:52.76#ibcon#about to read 3, iclass 28, count 0 2006.196.08:21:52.79#ibcon#read 3, iclass 28, count 0 2006.196.08:21:52.79#ibcon#about to read 4, iclass 28, count 0 2006.196.08:21:52.79#ibcon#read 4, iclass 28, count 0 2006.196.08:21:52.79#ibcon#about to read 5, iclass 28, count 0 2006.196.08:21:52.79#ibcon#read 5, iclass 28, count 0 2006.196.08:21:52.79#ibcon#about to read 6, iclass 28, count 0 2006.196.08:21:52.79#ibcon#read 6, iclass 28, count 0 2006.196.08:21:52.79#ibcon#end of sib2, iclass 28, count 0 2006.196.08:21:52.79#ibcon#*after write, iclass 28, count 0 2006.196.08:21:52.79#ibcon#*before return 0, iclass 28, count 0 2006.196.08:21:52.79#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.196.08:21:52.79#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.196.08:21:52.79#ibcon#about to clear, iclass 28 cls_cnt 0 2006.196.08:21:52.79#ibcon#cleared, iclass 28 cls_cnt 0 2006.196.08:21:52.79$4f8m12a/ifd4f 2006.196.08:21:52.79$ifd4f/lo= 2006.196.08:21:52.79$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.196.08:21:52.79$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.196.08:21:52.79$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.196.08:21:52.79$ifd4f/patch= 2006.196.08:21:52.79$ifd4f/patch=lo1,a1,a2,a3,a4 2006.196.08:21:52.79$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.196.08:21:52.79$ifd4f/patch=lo3,a5,a6,a7,a8 2006.196.08:21:52.79$4f8m12a/"form=m,16.000,1:2 2006.196.08:21:52.79$4f8m12a/"tpicd 2006.196.08:21:52.79$4f8m12a/echo=off 2006.196.08:21:52.79$4f8m12a/xlog=off 2006.196.08:21:52.79:!2006.196.08:22:40 2006.196.08:22:02.14#trakl#Source acquired 2006.196.08:22:02.14#flagr#flagr/antenna,acquired 2006.196.08:22:40.00:preob 2006.196.08:22:40.14/onsource/TRACKING 2006.196.08:22:40.14:!2006.196.08:22:50 2006.196.08:22:50.00:data_valid=on 2006.196.08:22:50.00:midob 2006.196.08:22:50.14/onsource/TRACKING 2006.196.08:22:50.14/wx/28.88,1004.1,93 2006.196.08:22:50.26/cable/+6.3384E-03 2006.196.08:22:51.35/va/01,08,usb,yes,29,31 2006.196.08:22:51.35/va/02,07,usb,yes,30,31 2006.196.08:22:51.35/va/03,06,usb,yes,31,31 2006.196.08:22:51.35/va/04,07,usb,yes,30,33 2006.196.08:22:51.35/va/05,07,usb,yes,33,35 2006.196.08:22:51.35/va/06,06,usb,yes,32,32 2006.196.08:22:51.35/va/07,06,usb,yes,32,32 2006.196.08:22:51.35/va/08,07,usb,yes,31,30 2006.196.08:22:51.58/valo/01,532.99,yes,locked 2006.196.08:22:51.58/valo/02,572.99,yes,locked 2006.196.08:22:51.58/valo/03,672.99,yes,locked 2006.196.08:22:51.58/valo/04,832.99,yes,locked 2006.196.08:22:51.58/valo/05,652.99,yes,locked 2006.196.08:22:51.58/valo/06,772.99,yes,locked 2006.196.08:22:51.58/valo/07,832.99,yes,locked 2006.196.08:22:51.58/valo/08,852.99,yes,locked 2006.196.08:22:52.67/vb/01,04,usb,yes,29,27 2006.196.08:22:52.67/vb/02,04,usb,yes,30,32 2006.196.08:22:52.67/vb/03,04,usb,yes,27,31 2006.196.08:22:52.67/vb/04,04,usb,yes,28,28 2006.196.08:22:52.67/vb/05,04,usb,yes,26,30 2006.196.08:22:52.67/vb/06,04,usb,yes,27,30 2006.196.08:22:52.67/vb/07,04,usb,yes,29,29 2006.196.08:22:52.67/vb/08,04,usb,yes,27,30 2006.196.08:22:52.91/vblo/01,632.99,yes,locked 2006.196.08:22:52.91/vblo/02,640.99,yes,locked 2006.196.08:22:52.91/vblo/03,656.99,yes,locked 2006.196.08:22:52.91/vblo/04,712.99,yes,locked 2006.196.08:22:52.91/vblo/05,744.99,yes,locked 2006.196.08:22:52.91/vblo/06,752.99,yes,locked 2006.196.08:22:52.91/vblo/07,734.99,yes,locked 2006.196.08:22:52.91/vblo/08,744.99,yes,locked 2006.196.08:22:53.06/vabw/8 2006.196.08:22:53.21/vbbw/8 2006.196.08:22:53.32/xfe/off,on,14.7 2006.196.08:22:53.70/ifatt/23,28,28,28 2006.196.08:22:54.06/fmout-gps/S +3.33E-07 2006.196.08:22:54.13:!2006.196.08:23:50 2006.196.08:23:50.00:data_valid=off 2006.196.08:23:50.00:postob 2006.196.08:23:50.15/cable/+6.3393E-03 2006.196.08:23:50.15/wx/28.86,1004.1,93 2006.196.08:23:51.06/fmout-gps/S +3.34E-07 2006.196.08:23:51.06:scan_name=196-0826,k06196,60 2006.196.08:23:51.06:source=0804+499,080839.67,495036.5,2000.0,ccw 2006.196.08:23:51.13#flagr#flagr/antenna,new-source 2006.196.08:23:52.13:checkk5 2006.196.08:23:52.50/chk_autoobs//k5ts1/ autoobs is running! 2006.196.08:23:52.88/chk_autoobs//k5ts2/ autoobs is running! 2006.196.08:23:53.26/chk_autoobs//k5ts3/ autoobs is running! 2006.196.08:23:53.63/chk_autoobs//k5ts4/ autoobs is running! 2006.196.08:23:54.00/chk_obsdata//k5ts1/T1960822??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.08:23:54.37/chk_obsdata//k5ts2/T1960822??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.08:23:54.73/chk_obsdata//k5ts3/T1960822??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.08:23:55.10/chk_obsdata//k5ts4/T1960822??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.08:23:55.79/k5log//k5ts1_log_newline 2006.196.08:23:56.49/k5log//k5ts2_log_newline 2006.196.08:23:57.20/k5log//k5ts3_log_newline 2006.196.08:23:57.89/k5log//k5ts4_log_newline 2006.196.08:23:57.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.196.08:23:57.91:4f8m12a=3 2006.196.08:23:57.91$4f8m12a/echo=on 2006.196.08:23:57.91$4f8m12a/pcalon 2006.196.08:23:57.91$pcalon/"no phase cal control is implemented here 2006.196.08:23:57.91$4f8m12a/"tpicd=stop 2006.196.08:23:57.91$4f8m12a/vc4f8 2006.196.08:23:57.91$vc4f8/valo=1,532.99 2006.196.08:23:57.92#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.196.08:23:57.92#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.196.08:23:57.92#ibcon#ireg 17 cls_cnt 0 2006.196.08:23:57.92#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.196.08:23:57.92#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.196.08:23:57.92#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.196.08:23:57.92#ibcon#enter wrdev, iclass 11, count 0 2006.196.08:23:57.92#ibcon#first serial, iclass 11, count 0 2006.196.08:23:57.92#ibcon#enter sib2, iclass 11, count 0 2006.196.08:23:57.92#ibcon#flushed, iclass 11, count 0 2006.196.08:23:57.92#ibcon#about to write, iclass 11, count 0 2006.196.08:23:57.92#ibcon#wrote, iclass 11, count 0 2006.196.08:23:57.92#ibcon#about to read 3, iclass 11, count 0 2006.196.08:23:57.96#ibcon#read 3, iclass 11, count 0 2006.196.08:23:57.96#ibcon#about to read 4, iclass 11, count 0 2006.196.08:23:57.96#ibcon#read 4, iclass 11, count 0 2006.196.08:23:57.96#ibcon#about to read 5, iclass 11, count 0 2006.196.08:23:57.96#ibcon#read 5, iclass 11, count 0 2006.196.08:23:57.96#ibcon#about to read 6, iclass 11, count 0 2006.196.08:23:57.96#ibcon#read 6, iclass 11, count 0 2006.196.08:23:57.96#ibcon#end of sib2, iclass 11, count 0 2006.196.08:23:57.96#ibcon#*mode == 0, iclass 11, count 0 2006.196.08:23:57.96#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.196.08:23:57.96#ibcon#[26=FRQ=01,532.99\r\n] 2006.196.08:23:57.96#ibcon#*before write, iclass 11, count 0 2006.196.08:23:57.96#ibcon#enter sib2, iclass 11, count 0 2006.196.08:23:57.96#ibcon#flushed, iclass 11, count 0 2006.196.08:23:57.96#ibcon#about to write, iclass 11, count 0 2006.196.08:23:57.96#ibcon#wrote, iclass 11, count 0 2006.196.08:23:57.96#ibcon#about to read 3, iclass 11, count 0 2006.196.08:23:58.01#ibcon#read 3, iclass 11, count 0 2006.196.08:23:58.01#ibcon#about to read 4, iclass 11, count 0 2006.196.08:23:58.01#ibcon#read 4, iclass 11, count 0 2006.196.08:23:58.01#ibcon#about to read 5, iclass 11, count 0 2006.196.08:23:58.01#ibcon#read 5, iclass 11, count 0 2006.196.08:23:58.01#ibcon#about to read 6, iclass 11, count 0 2006.196.08:23:58.01#ibcon#read 6, iclass 11, count 0 2006.196.08:23:58.01#ibcon#end of sib2, iclass 11, count 0 2006.196.08:23:58.01#ibcon#*after write, iclass 11, count 0 2006.196.08:23:58.01#ibcon#*before return 0, iclass 11, count 0 2006.196.08:23:58.01#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.196.08:23:58.01#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.196.08:23:58.01#ibcon#about to clear, iclass 11 cls_cnt 0 2006.196.08:23:58.01#ibcon#cleared, iclass 11 cls_cnt 0 2006.196.08:23:58.01$vc4f8/va=1,8 2006.196.08:23:58.01#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.196.08:23:58.01#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.196.08:23:58.01#ibcon#ireg 11 cls_cnt 2 2006.196.08:23:58.01#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.196.08:23:58.01#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.196.08:23:58.01#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.196.08:23:58.01#ibcon#enter wrdev, iclass 13, count 2 2006.196.08:23:58.01#ibcon#first serial, iclass 13, count 2 2006.196.08:23:58.01#ibcon#enter sib2, iclass 13, count 2 2006.196.08:23:58.01#ibcon#flushed, iclass 13, count 2 2006.196.08:23:58.01#ibcon#about to write, iclass 13, count 2 2006.196.08:23:58.01#ibcon#wrote, iclass 13, count 2 2006.196.08:23:58.01#ibcon#about to read 3, iclass 13, count 2 2006.196.08:23:58.03#ibcon#read 3, iclass 13, count 2 2006.196.08:23:58.03#ibcon#about to read 4, iclass 13, count 2 2006.196.08:23:58.03#ibcon#read 4, iclass 13, count 2 2006.196.08:23:58.03#ibcon#about to read 5, iclass 13, count 2 2006.196.08:23:58.03#ibcon#read 5, iclass 13, count 2 2006.196.08:23:58.03#ibcon#about to read 6, iclass 13, count 2 2006.196.08:23:58.03#ibcon#read 6, iclass 13, count 2 2006.196.08:23:58.03#ibcon#end of sib2, iclass 13, count 2 2006.196.08:23:58.03#ibcon#*mode == 0, iclass 13, count 2 2006.196.08:23:58.03#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.196.08:23:58.03#ibcon#[25=AT01-08\r\n] 2006.196.08:23:58.03#ibcon#*before write, iclass 13, count 2 2006.196.08:23:58.03#ibcon#enter sib2, iclass 13, count 2 2006.196.08:23:58.03#ibcon#flushed, iclass 13, count 2 2006.196.08:23:58.03#ibcon#about to write, iclass 13, count 2 2006.196.08:23:58.03#ibcon#wrote, iclass 13, count 2 2006.196.08:23:58.03#ibcon#about to read 3, iclass 13, count 2 2006.196.08:23:58.06#ibcon#read 3, iclass 13, count 2 2006.196.08:23:58.06#ibcon#about to read 4, iclass 13, count 2 2006.196.08:23:58.06#ibcon#read 4, iclass 13, count 2 2006.196.08:23:58.06#ibcon#about to read 5, iclass 13, count 2 2006.196.08:23:58.06#ibcon#read 5, iclass 13, count 2 2006.196.08:23:58.06#ibcon#about to read 6, iclass 13, count 2 2006.196.08:23:58.06#ibcon#read 6, iclass 13, count 2 2006.196.08:23:58.06#ibcon#end of sib2, iclass 13, count 2 2006.196.08:23:58.06#ibcon#*after write, iclass 13, count 2 2006.196.08:23:58.06#ibcon#*before return 0, iclass 13, count 2 2006.196.08:23:58.06#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.196.08:23:58.06#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.196.08:23:58.06#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.196.08:23:58.06#ibcon#ireg 7 cls_cnt 0 2006.196.08:23:58.06#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.196.08:23:58.18#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.196.08:23:58.18#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.196.08:23:58.18#ibcon#enter wrdev, iclass 13, count 0 2006.196.08:23:58.18#ibcon#first serial, iclass 13, count 0 2006.196.08:23:58.18#ibcon#enter sib2, iclass 13, count 0 2006.196.08:23:58.18#ibcon#flushed, iclass 13, count 0 2006.196.08:23:58.18#ibcon#about to write, iclass 13, count 0 2006.196.08:23:58.18#ibcon#wrote, iclass 13, count 0 2006.196.08:23:58.18#ibcon#about to read 3, iclass 13, count 0 2006.196.08:23:58.20#ibcon#read 3, iclass 13, count 0 2006.196.08:23:58.20#ibcon#about to read 4, iclass 13, count 0 2006.196.08:23:58.20#ibcon#read 4, iclass 13, count 0 2006.196.08:23:58.20#ibcon#about to read 5, iclass 13, count 0 2006.196.08:23:58.20#ibcon#read 5, iclass 13, count 0 2006.196.08:23:58.20#ibcon#about to read 6, iclass 13, count 0 2006.196.08:23:58.20#ibcon#read 6, iclass 13, count 0 2006.196.08:23:58.20#ibcon#end of sib2, iclass 13, count 0 2006.196.08:23:58.20#ibcon#*mode == 0, iclass 13, count 0 2006.196.08:23:58.20#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.196.08:23:58.20#ibcon#[25=USB\r\n] 2006.196.08:23:58.20#ibcon#*before write, iclass 13, count 0 2006.196.08:23:58.20#ibcon#enter sib2, iclass 13, count 0 2006.196.08:23:58.20#ibcon#flushed, iclass 13, count 0 2006.196.08:23:58.20#ibcon#about to write, iclass 13, count 0 2006.196.08:23:58.20#ibcon#wrote, iclass 13, count 0 2006.196.08:23:58.20#ibcon#about to read 3, iclass 13, count 0 2006.196.08:23:58.23#ibcon#read 3, iclass 13, count 0 2006.196.08:23:58.23#ibcon#about to read 4, iclass 13, count 0 2006.196.08:23:58.23#ibcon#read 4, iclass 13, count 0 2006.196.08:23:58.23#ibcon#about to read 5, iclass 13, count 0 2006.196.08:23:58.23#ibcon#read 5, iclass 13, count 0 2006.196.08:23:58.23#ibcon#about to read 6, iclass 13, count 0 2006.196.08:23:58.23#ibcon#read 6, iclass 13, count 0 2006.196.08:23:58.23#ibcon#end of sib2, iclass 13, count 0 2006.196.08:23:58.23#ibcon#*after write, iclass 13, count 0 2006.196.08:23:58.23#ibcon#*before return 0, iclass 13, count 0 2006.196.08:23:58.23#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.196.08:23:58.23#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.196.08:23:58.23#ibcon#about to clear, iclass 13 cls_cnt 0 2006.196.08:23:58.23#ibcon#cleared, iclass 13 cls_cnt 0 2006.196.08:23:58.23$vc4f8/valo=2,572.99 2006.196.08:23:58.23#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.196.08:23:58.23#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.196.08:23:58.23#ibcon#ireg 17 cls_cnt 0 2006.196.08:23:58.23#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.196.08:23:58.23#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.196.08:23:58.23#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.196.08:23:58.23#ibcon#enter wrdev, iclass 15, count 0 2006.196.08:23:58.23#ibcon#first serial, iclass 15, count 0 2006.196.08:23:58.23#ibcon#enter sib2, iclass 15, count 0 2006.196.08:23:58.23#ibcon#flushed, iclass 15, count 0 2006.196.08:23:58.23#ibcon#about to write, iclass 15, count 0 2006.196.08:23:58.23#ibcon#wrote, iclass 15, count 0 2006.196.08:23:58.23#ibcon#about to read 3, iclass 15, count 0 2006.196.08:23:58.25#ibcon#read 3, iclass 15, count 0 2006.196.08:23:58.25#ibcon#about to read 4, iclass 15, count 0 2006.196.08:23:58.25#ibcon#read 4, iclass 15, count 0 2006.196.08:23:58.25#ibcon#about to read 5, iclass 15, count 0 2006.196.08:23:58.25#ibcon#read 5, iclass 15, count 0 2006.196.08:23:58.25#ibcon#about to read 6, iclass 15, count 0 2006.196.08:23:58.25#ibcon#read 6, iclass 15, count 0 2006.196.08:23:58.25#ibcon#end of sib2, iclass 15, count 0 2006.196.08:23:58.25#ibcon#*mode == 0, iclass 15, count 0 2006.196.08:23:58.25#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.196.08:23:58.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.196.08:23:58.25#ibcon#*before write, iclass 15, count 0 2006.196.08:23:58.25#ibcon#enter sib2, iclass 15, count 0 2006.196.08:23:58.25#ibcon#flushed, iclass 15, count 0 2006.196.08:23:58.25#ibcon#about to write, iclass 15, count 0 2006.196.08:23:58.25#ibcon#wrote, iclass 15, count 0 2006.196.08:23:58.25#ibcon#about to read 3, iclass 15, count 0 2006.196.08:23:58.29#ibcon#read 3, iclass 15, count 0 2006.196.08:23:58.29#ibcon#about to read 4, iclass 15, count 0 2006.196.08:23:58.29#ibcon#read 4, iclass 15, count 0 2006.196.08:23:58.29#ibcon#about to read 5, iclass 15, count 0 2006.196.08:23:58.29#ibcon#read 5, iclass 15, count 0 2006.196.08:23:58.29#ibcon#about to read 6, iclass 15, count 0 2006.196.08:23:58.29#ibcon#read 6, iclass 15, count 0 2006.196.08:23:58.29#ibcon#end of sib2, iclass 15, count 0 2006.196.08:23:58.29#ibcon#*after write, iclass 15, count 0 2006.196.08:23:58.29#ibcon#*before return 0, iclass 15, count 0 2006.196.08:23:58.29#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.196.08:23:58.29#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.196.08:23:58.29#ibcon#about to clear, iclass 15 cls_cnt 0 2006.196.08:23:58.29#ibcon#cleared, iclass 15 cls_cnt 0 2006.196.08:23:58.29$vc4f8/va=2,7 2006.196.08:23:58.29#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.196.08:23:58.29#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.196.08:23:58.29#ibcon#ireg 11 cls_cnt 2 2006.196.08:23:58.29#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.196.08:23:58.35#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.196.08:23:58.35#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.196.08:23:58.35#ibcon#enter wrdev, iclass 17, count 2 2006.196.08:23:58.35#ibcon#first serial, iclass 17, count 2 2006.196.08:23:58.35#ibcon#enter sib2, iclass 17, count 2 2006.196.08:23:58.35#ibcon#flushed, iclass 17, count 2 2006.196.08:23:58.35#ibcon#about to write, iclass 17, count 2 2006.196.08:23:58.35#ibcon#wrote, iclass 17, count 2 2006.196.08:23:58.35#ibcon#about to read 3, iclass 17, count 2 2006.196.08:23:58.37#ibcon#read 3, iclass 17, count 2 2006.196.08:23:58.37#ibcon#about to read 4, iclass 17, count 2 2006.196.08:23:58.37#ibcon#read 4, iclass 17, count 2 2006.196.08:23:58.37#ibcon#about to read 5, iclass 17, count 2 2006.196.08:23:58.37#ibcon#read 5, iclass 17, count 2 2006.196.08:23:58.37#ibcon#about to read 6, iclass 17, count 2 2006.196.08:23:58.37#ibcon#read 6, iclass 17, count 2 2006.196.08:23:58.37#ibcon#end of sib2, iclass 17, count 2 2006.196.08:23:58.37#ibcon#*mode == 0, iclass 17, count 2 2006.196.08:23:58.37#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.196.08:23:58.37#ibcon#[25=AT02-07\r\n] 2006.196.08:23:58.37#ibcon#*before write, iclass 17, count 2 2006.196.08:23:58.37#ibcon#enter sib2, iclass 17, count 2 2006.196.08:23:58.37#ibcon#flushed, iclass 17, count 2 2006.196.08:23:58.37#ibcon#about to write, iclass 17, count 2 2006.196.08:23:58.37#ibcon#wrote, iclass 17, count 2 2006.196.08:23:58.37#ibcon#about to read 3, iclass 17, count 2 2006.196.08:23:58.40#ibcon#read 3, iclass 17, count 2 2006.196.08:23:58.40#ibcon#about to read 4, iclass 17, count 2 2006.196.08:23:58.40#ibcon#read 4, iclass 17, count 2 2006.196.08:23:58.40#ibcon#about to read 5, iclass 17, count 2 2006.196.08:23:58.40#ibcon#read 5, iclass 17, count 2 2006.196.08:23:58.40#ibcon#about to read 6, iclass 17, count 2 2006.196.08:23:58.40#ibcon#read 6, iclass 17, count 2 2006.196.08:23:58.40#ibcon#end of sib2, iclass 17, count 2 2006.196.08:23:58.40#ibcon#*after write, iclass 17, count 2 2006.196.08:23:58.40#ibcon#*before return 0, iclass 17, count 2 2006.196.08:23:58.40#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.196.08:23:58.40#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.196.08:23:58.40#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.196.08:23:58.40#ibcon#ireg 7 cls_cnt 0 2006.196.08:23:58.40#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.196.08:23:58.52#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.196.08:23:58.52#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.196.08:23:58.52#ibcon#enter wrdev, iclass 17, count 0 2006.196.08:23:58.52#ibcon#first serial, iclass 17, count 0 2006.196.08:23:58.52#ibcon#enter sib2, iclass 17, count 0 2006.196.08:23:58.52#ibcon#flushed, iclass 17, count 0 2006.196.08:23:58.52#ibcon#about to write, iclass 17, count 0 2006.196.08:23:58.52#ibcon#wrote, iclass 17, count 0 2006.196.08:23:58.52#ibcon#about to read 3, iclass 17, count 0 2006.196.08:23:58.54#ibcon#read 3, iclass 17, count 0 2006.196.08:23:58.54#ibcon#about to read 4, iclass 17, count 0 2006.196.08:23:58.54#ibcon#read 4, iclass 17, count 0 2006.196.08:23:58.54#ibcon#about to read 5, iclass 17, count 0 2006.196.08:23:58.54#ibcon#read 5, iclass 17, count 0 2006.196.08:23:58.54#ibcon#about to read 6, iclass 17, count 0 2006.196.08:23:58.54#ibcon#read 6, iclass 17, count 0 2006.196.08:23:58.54#ibcon#end of sib2, iclass 17, count 0 2006.196.08:23:58.54#ibcon#*mode == 0, iclass 17, count 0 2006.196.08:23:58.54#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.196.08:23:58.54#ibcon#[25=USB\r\n] 2006.196.08:23:58.54#ibcon#*before write, iclass 17, count 0 2006.196.08:23:58.54#ibcon#enter sib2, iclass 17, count 0 2006.196.08:23:58.54#ibcon#flushed, iclass 17, count 0 2006.196.08:23:58.54#ibcon#about to write, iclass 17, count 0 2006.196.08:23:58.54#ibcon#wrote, iclass 17, count 0 2006.196.08:23:58.54#ibcon#about to read 3, iclass 17, count 0 2006.196.08:23:58.57#ibcon#read 3, iclass 17, count 0 2006.196.08:23:58.57#ibcon#about to read 4, iclass 17, count 0 2006.196.08:23:58.57#ibcon#read 4, iclass 17, count 0 2006.196.08:23:58.57#ibcon#about to read 5, iclass 17, count 0 2006.196.08:23:58.57#ibcon#read 5, iclass 17, count 0 2006.196.08:23:58.57#ibcon#about to read 6, iclass 17, count 0 2006.196.08:23:58.57#ibcon#read 6, iclass 17, count 0 2006.196.08:23:58.57#ibcon#end of sib2, iclass 17, count 0 2006.196.08:23:58.57#ibcon#*after write, iclass 17, count 0 2006.196.08:23:58.57#ibcon#*before return 0, iclass 17, count 0 2006.196.08:23:58.57#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.196.08:23:58.57#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.196.08:23:58.57#ibcon#about to clear, iclass 17 cls_cnt 0 2006.196.08:23:58.57#ibcon#cleared, iclass 17 cls_cnt 0 2006.196.08:23:58.57$vc4f8/valo=3,672.99 2006.196.08:23:58.57#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.196.08:23:58.57#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.196.08:23:58.57#ibcon#ireg 17 cls_cnt 0 2006.196.08:23:58.57#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.196.08:23:58.57#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.196.08:23:58.57#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.196.08:23:58.57#ibcon#enter wrdev, iclass 19, count 0 2006.196.08:23:58.57#ibcon#first serial, iclass 19, count 0 2006.196.08:23:58.57#ibcon#enter sib2, iclass 19, count 0 2006.196.08:23:58.57#ibcon#flushed, iclass 19, count 0 2006.196.08:23:58.57#ibcon#about to write, iclass 19, count 0 2006.196.08:23:58.57#ibcon#wrote, iclass 19, count 0 2006.196.08:23:58.57#ibcon#about to read 3, iclass 19, count 0 2006.196.08:23:58.59#ibcon#read 3, iclass 19, count 0 2006.196.08:23:58.59#ibcon#about to read 4, iclass 19, count 0 2006.196.08:23:58.59#ibcon#read 4, iclass 19, count 0 2006.196.08:23:58.59#ibcon#about to read 5, iclass 19, count 0 2006.196.08:23:58.59#ibcon#read 5, iclass 19, count 0 2006.196.08:23:58.59#ibcon#about to read 6, iclass 19, count 0 2006.196.08:23:58.59#ibcon#read 6, iclass 19, count 0 2006.196.08:23:58.59#ibcon#end of sib2, iclass 19, count 0 2006.196.08:23:58.59#ibcon#*mode == 0, iclass 19, count 0 2006.196.08:23:58.59#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.196.08:23:58.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.196.08:23:58.59#ibcon#*before write, iclass 19, count 0 2006.196.08:23:58.59#ibcon#enter sib2, iclass 19, count 0 2006.196.08:23:58.59#ibcon#flushed, iclass 19, count 0 2006.196.08:23:58.59#ibcon#about to write, iclass 19, count 0 2006.196.08:23:58.59#ibcon#wrote, iclass 19, count 0 2006.196.08:23:58.59#ibcon#about to read 3, iclass 19, count 0 2006.196.08:23:58.63#ibcon#read 3, iclass 19, count 0 2006.196.08:23:58.63#ibcon#about to read 4, iclass 19, count 0 2006.196.08:23:58.63#ibcon#read 4, iclass 19, count 0 2006.196.08:23:58.63#ibcon#about to read 5, iclass 19, count 0 2006.196.08:23:58.63#ibcon#read 5, iclass 19, count 0 2006.196.08:23:58.63#ibcon#about to read 6, iclass 19, count 0 2006.196.08:23:58.63#ibcon#read 6, iclass 19, count 0 2006.196.08:23:58.63#ibcon#end of sib2, iclass 19, count 0 2006.196.08:23:58.63#ibcon#*after write, iclass 19, count 0 2006.196.08:23:58.63#ibcon#*before return 0, iclass 19, count 0 2006.196.08:23:58.63#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.196.08:23:58.63#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.196.08:23:58.63#ibcon#about to clear, iclass 19 cls_cnt 0 2006.196.08:23:58.63#ibcon#cleared, iclass 19 cls_cnt 0 2006.196.08:23:58.63$vc4f8/va=3,6 2006.196.08:23:58.63#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.196.08:23:58.63#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.196.08:23:58.63#ibcon#ireg 11 cls_cnt 2 2006.196.08:23:58.63#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.196.08:23:58.69#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.196.08:23:58.69#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.196.08:23:58.69#ibcon#enter wrdev, iclass 21, count 2 2006.196.08:23:58.69#ibcon#first serial, iclass 21, count 2 2006.196.08:23:58.69#ibcon#enter sib2, iclass 21, count 2 2006.196.08:23:58.69#ibcon#flushed, iclass 21, count 2 2006.196.08:23:58.69#ibcon#about to write, iclass 21, count 2 2006.196.08:23:58.69#ibcon#wrote, iclass 21, count 2 2006.196.08:23:58.69#ibcon#about to read 3, iclass 21, count 2 2006.196.08:23:58.71#ibcon#read 3, iclass 21, count 2 2006.196.08:23:58.71#ibcon#about to read 4, iclass 21, count 2 2006.196.08:23:58.71#ibcon#read 4, iclass 21, count 2 2006.196.08:23:58.71#ibcon#about to read 5, iclass 21, count 2 2006.196.08:23:58.71#ibcon#read 5, iclass 21, count 2 2006.196.08:23:58.71#ibcon#about to read 6, iclass 21, count 2 2006.196.08:23:58.71#ibcon#read 6, iclass 21, count 2 2006.196.08:23:58.71#ibcon#end of sib2, iclass 21, count 2 2006.196.08:23:58.71#ibcon#*mode == 0, iclass 21, count 2 2006.196.08:23:58.71#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.196.08:23:58.71#ibcon#[25=AT03-06\r\n] 2006.196.08:23:58.71#ibcon#*before write, iclass 21, count 2 2006.196.08:23:58.71#ibcon#enter sib2, iclass 21, count 2 2006.196.08:23:58.71#ibcon#flushed, iclass 21, count 2 2006.196.08:23:58.71#ibcon#about to write, iclass 21, count 2 2006.196.08:23:58.71#ibcon#wrote, iclass 21, count 2 2006.196.08:23:58.71#ibcon#about to read 3, iclass 21, count 2 2006.196.08:23:58.75#ibcon#read 3, iclass 21, count 2 2006.196.08:23:58.75#ibcon#about to read 4, iclass 21, count 2 2006.196.08:23:58.75#ibcon#read 4, iclass 21, count 2 2006.196.08:23:58.75#ibcon#about to read 5, iclass 21, count 2 2006.196.08:23:58.75#ibcon#read 5, iclass 21, count 2 2006.196.08:23:58.75#ibcon#about to read 6, iclass 21, count 2 2006.196.08:23:58.75#ibcon#read 6, iclass 21, count 2 2006.196.08:23:58.75#ibcon#end of sib2, iclass 21, count 2 2006.196.08:23:58.75#ibcon#*after write, iclass 21, count 2 2006.196.08:23:58.75#ibcon#*before return 0, iclass 21, count 2 2006.196.08:23:58.75#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.196.08:23:58.75#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.196.08:23:58.75#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.196.08:23:58.75#ibcon#ireg 7 cls_cnt 0 2006.196.08:23:58.75#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.196.08:23:58.87#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.196.08:23:58.87#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.196.08:23:58.87#ibcon#enter wrdev, iclass 21, count 0 2006.196.08:23:58.87#ibcon#first serial, iclass 21, count 0 2006.196.08:23:58.87#ibcon#enter sib2, iclass 21, count 0 2006.196.08:23:58.87#ibcon#flushed, iclass 21, count 0 2006.196.08:23:58.87#ibcon#about to write, iclass 21, count 0 2006.196.08:23:58.87#ibcon#wrote, iclass 21, count 0 2006.196.08:23:58.87#ibcon#about to read 3, iclass 21, count 0 2006.196.08:23:58.89#ibcon#read 3, iclass 21, count 0 2006.196.08:23:58.89#ibcon#about to read 4, iclass 21, count 0 2006.196.08:23:58.89#ibcon#read 4, iclass 21, count 0 2006.196.08:23:58.89#ibcon#about to read 5, iclass 21, count 0 2006.196.08:23:58.89#ibcon#read 5, iclass 21, count 0 2006.196.08:23:58.89#ibcon#about to read 6, iclass 21, count 0 2006.196.08:23:58.89#ibcon#read 6, iclass 21, count 0 2006.196.08:23:58.89#ibcon#end of sib2, iclass 21, count 0 2006.196.08:23:58.89#ibcon#*mode == 0, iclass 21, count 0 2006.196.08:23:58.89#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.196.08:23:58.89#ibcon#[25=USB\r\n] 2006.196.08:23:58.89#ibcon#*before write, iclass 21, count 0 2006.196.08:23:58.89#ibcon#enter sib2, iclass 21, count 0 2006.196.08:23:58.89#ibcon#flushed, iclass 21, count 0 2006.196.08:23:58.89#ibcon#about to write, iclass 21, count 0 2006.196.08:23:58.89#ibcon#wrote, iclass 21, count 0 2006.196.08:23:58.89#ibcon#about to read 3, iclass 21, count 0 2006.196.08:23:58.92#ibcon#read 3, iclass 21, count 0 2006.196.08:23:58.92#ibcon#about to read 4, iclass 21, count 0 2006.196.08:23:58.92#ibcon#read 4, iclass 21, count 0 2006.196.08:23:58.92#ibcon#about to read 5, iclass 21, count 0 2006.196.08:23:58.92#ibcon#read 5, iclass 21, count 0 2006.196.08:23:58.92#ibcon#about to read 6, iclass 21, count 0 2006.196.08:23:58.92#ibcon#read 6, iclass 21, count 0 2006.196.08:23:58.92#ibcon#end of sib2, iclass 21, count 0 2006.196.08:23:58.92#ibcon#*after write, iclass 21, count 0 2006.196.08:23:58.92#ibcon#*before return 0, iclass 21, count 0 2006.196.08:23:58.92#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.196.08:23:58.92#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.196.08:23:58.92#ibcon#about to clear, iclass 21 cls_cnt 0 2006.196.08:23:58.92#ibcon#cleared, iclass 21 cls_cnt 0 2006.196.08:23:58.92$vc4f8/valo=4,832.99 2006.196.08:23:58.92#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.196.08:23:58.92#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.196.08:23:58.92#ibcon#ireg 17 cls_cnt 0 2006.196.08:23:58.92#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.196.08:23:58.92#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.196.08:23:58.92#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.196.08:23:58.92#ibcon#enter wrdev, iclass 23, count 0 2006.196.08:23:58.92#ibcon#first serial, iclass 23, count 0 2006.196.08:23:58.92#ibcon#enter sib2, iclass 23, count 0 2006.196.08:23:58.92#ibcon#flushed, iclass 23, count 0 2006.196.08:23:58.92#ibcon#about to write, iclass 23, count 0 2006.196.08:23:58.92#ibcon#wrote, iclass 23, count 0 2006.196.08:23:58.92#ibcon#about to read 3, iclass 23, count 0 2006.196.08:23:58.94#ibcon#read 3, iclass 23, count 0 2006.196.08:23:58.94#ibcon#about to read 4, iclass 23, count 0 2006.196.08:23:58.94#ibcon#read 4, iclass 23, count 0 2006.196.08:23:58.94#ibcon#about to read 5, iclass 23, count 0 2006.196.08:23:58.94#ibcon#read 5, iclass 23, count 0 2006.196.08:23:58.94#ibcon#about to read 6, iclass 23, count 0 2006.196.08:23:58.94#ibcon#read 6, iclass 23, count 0 2006.196.08:23:58.94#ibcon#end of sib2, iclass 23, count 0 2006.196.08:23:58.94#ibcon#*mode == 0, iclass 23, count 0 2006.196.08:23:58.94#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.196.08:23:58.94#ibcon#[26=FRQ=04,832.99\r\n] 2006.196.08:23:58.94#ibcon#*before write, iclass 23, count 0 2006.196.08:23:58.94#ibcon#enter sib2, iclass 23, count 0 2006.196.08:23:58.94#ibcon#flushed, iclass 23, count 0 2006.196.08:23:58.94#ibcon#about to write, iclass 23, count 0 2006.196.08:23:58.94#ibcon#wrote, iclass 23, count 0 2006.196.08:23:58.94#ibcon#about to read 3, iclass 23, count 0 2006.196.08:23:58.98#ibcon#read 3, iclass 23, count 0 2006.196.08:23:58.98#ibcon#about to read 4, iclass 23, count 0 2006.196.08:23:58.98#ibcon#read 4, iclass 23, count 0 2006.196.08:23:58.98#ibcon#about to read 5, iclass 23, count 0 2006.196.08:23:58.98#ibcon#read 5, iclass 23, count 0 2006.196.08:23:58.98#ibcon#about to read 6, iclass 23, count 0 2006.196.08:23:58.98#ibcon#read 6, iclass 23, count 0 2006.196.08:23:58.98#ibcon#end of sib2, iclass 23, count 0 2006.196.08:23:58.98#ibcon#*after write, iclass 23, count 0 2006.196.08:23:58.98#ibcon#*before return 0, iclass 23, count 0 2006.196.08:23:58.98#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.196.08:23:58.98#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.196.08:23:58.98#ibcon#about to clear, iclass 23 cls_cnt 0 2006.196.08:23:58.98#ibcon#cleared, iclass 23 cls_cnt 0 2006.196.08:23:58.98$vc4f8/va=4,7 2006.196.08:23:58.98#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.196.08:23:58.98#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.196.08:23:58.98#ibcon#ireg 11 cls_cnt 2 2006.196.08:23:58.98#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.196.08:23:59.04#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.196.08:23:59.04#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.196.08:23:59.04#ibcon#enter wrdev, iclass 25, count 2 2006.196.08:23:59.04#ibcon#first serial, iclass 25, count 2 2006.196.08:23:59.04#ibcon#enter sib2, iclass 25, count 2 2006.196.08:23:59.04#ibcon#flushed, iclass 25, count 2 2006.196.08:23:59.04#ibcon#about to write, iclass 25, count 2 2006.196.08:23:59.04#ibcon#wrote, iclass 25, count 2 2006.196.08:23:59.04#ibcon#about to read 3, iclass 25, count 2 2006.196.08:23:59.06#ibcon#read 3, iclass 25, count 2 2006.196.08:23:59.06#ibcon#about to read 4, iclass 25, count 2 2006.196.08:23:59.06#ibcon#read 4, iclass 25, count 2 2006.196.08:23:59.06#ibcon#about to read 5, iclass 25, count 2 2006.196.08:23:59.06#ibcon#read 5, iclass 25, count 2 2006.196.08:23:59.06#ibcon#about to read 6, iclass 25, count 2 2006.196.08:23:59.06#ibcon#read 6, iclass 25, count 2 2006.196.08:23:59.06#ibcon#end of sib2, iclass 25, count 2 2006.196.08:23:59.06#ibcon#*mode == 0, iclass 25, count 2 2006.196.08:23:59.06#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.196.08:23:59.06#ibcon#[25=AT04-07\r\n] 2006.196.08:23:59.06#ibcon#*before write, iclass 25, count 2 2006.196.08:23:59.06#ibcon#enter sib2, iclass 25, count 2 2006.196.08:23:59.06#ibcon#flushed, iclass 25, count 2 2006.196.08:23:59.06#ibcon#about to write, iclass 25, count 2 2006.196.08:23:59.06#ibcon#wrote, iclass 25, count 2 2006.196.08:23:59.06#ibcon#about to read 3, iclass 25, count 2 2006.196.08:23:59.09#ibcon#read 3, iclass 25, count 2 2006.196.08:23:59.09#ibcon#about to read 4, iclass 25, count 2 2006.196.08:23:59.09#ibcon#read 4, iclass 25, count 2 2006.196.08:23:59.09#ibcon#about to read 5, iclass 25, count 2 2006.196.08:23:59.09#ibcon#read 5, iclass 25, count 2 2006.196.08:23:59.09#ibcon#about to read 6, iclass 25, count 2 2006.196.08:23:59.09#ibcon#read 6, iclass 25, count 2 2006.196.08:23:59.09#ibcon#end of sib2, iclass 25, count 2 2006.196.08:23:59.09#ibcon#*after write, iclass 25, count 2 2006.196.08:23:59.09#ibcon#*before return 0, iclass 25, count 2 2006.196.08:23:59.09#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.196.08:23:59.09#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.196.08:23:59.09#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.196.08:23:59.09#ibcon#ireg 7 cls_cnt 0 2006.196.08:23:59.09#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.196.08:23:59.21#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.196.08:23:59.21#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.196.08:23:59.21#ibcon#enter wrdev, iclass 25, count 0 2006.196.08:23:59.21#ibcon#first serial, iclass 25, count 0 2006.196.08:23:59.21#ibcon#enter sib2, iclass 25, count 0 2006.196.08:23:59.21#ibcon#flushed, iclass 25, count 0 2006.196.08:23:59.21#ibcon#about to write, iclass 25, count 0 2006.196.08:23:59.21#ibcon#wrote, iclass 25, count 0 2006.196.08:23:59.21#ibcon#about to read 3, iclass 25, count 0 2006.196.08:23:59.23#ibcon#read 3, iclass 25, count 0 2006.196.08:23:59.23#ibcon#about to read 4, iclass 25, count 0 2006.196.08:23:59.23#ibcon#read 4, iclass 25, count 0 2006.196.08:23:59.23#ibcon#about to read 5, iclass 25, count 0 2006.196.08:23:59.23#ibcon#read 5, iclass 25, count 0 2006.196.08:23:59.23#ibcon#about to read 6, iclass 25, count 0 2006.196.08:23:59.23#ibcon#read 6, iclass 25, count 0 2006.196.08:23:59.23#ibcon#end of sib2, iclass 25, count 0 2006.196.08:23:59.23#ibcon#*mode == 0, iclass 25, count 0 2006.196.08:23:59.23#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.196.08:23:59.23#ibcon#[25=USB\r\n] 2006.196.08:23:59.23#ibcon#*before write, iclass 25, count 0 2006.196.08:23:59.23#ibcon#enter sib2, iclass 25, count 0 2006.196.08:23:59.23#ibcon#flushed, iclass 25, count 0 2006.196.08:23:59.23#ibcon#about to write, iclass 25, count 0 2006.196.08:23:59.23#ibcon#wrote, iclass 25, count 0 2006.196.08:23:59.23#ibcon#about to read 3, iclass 25, count 0 2006.196.08:23:59.26#ibcon#read 3, iclass 25, count 0 2006.196.08:23:59.26#ibcon#about to read 4, iclass 25, count 0 2006.196.08:23:59.26#ibcon#read 4, iclass 25, count 0 2006.196.08:23:59.26#ibcon#about to read 5, iclass 25, count 0 2006.196.08:23:59.26#ibcon#read 5, iclass 25, count 0 2006.196.08:23:59.26#ibcon#about to read 6, iclass 25, count 0 2006.196.08:23:59.26#ibcon#read 6, iclass 25, count 0 2006.196.08:23:59.26#ibcon#end of sib2, iclass 25, count 0 2006.196.08:23:59.26#ibcon#*after write, iclass 25, count 0 2006.196.08:23:59.26#ibcon#*before return 0, iclass 25, count 0 2006.196.08:23:59.26#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.196.08:23:59.26#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.196.08:23:59.26#ibcon#about to clear, iclass 25 cls_cnt 0 2006.196.08:23:59.26#ibcon#cleared, iclass 25 cls_cnt 0 2006.196.08:23:59.26$vc4f8/valo=5,652.99 2006.196.08:23:59.26#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.196.08:23:59.26#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.196.08:23:59.26#ibcon#ireg 17 cls_cnt 0 2006.196.08:23:59.26#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.196.08:23:59.26#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.196.08:23:59.26#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.196.08:23:59.26#ibcon#enter wrdev, iclass 27, count 0 2006.196.08:23:59.26#ibcon#first serial, iclass 27, count 0 2006.196.08:23:59.26#ibcon#enter sib2, iclass 27, count 0 2006.196.08:23:59.26#ibcon#flushed, iclass 27, count 0 2006.196.08:23:59.26#ibcon#about to write, iclass 27, count 0 2006.196.08:23:59.26#ibcon#wrote, iclass 27, count 0 2006.196.08:23:59.26#ibcon#about to read 3, iclass 27, count 0 2006.196.08:23:59.28#ibcon#read 3, iclass 27, count 0 2006.196.08:23:59.28#ibcon#about to read 4, iclass 27, count 0 2006.196.08:23:59.28#ibcon#read 4, iclass 27, count 0 2006.196.08:23:59.28#ibcon#about to read 5, iclass 27, count 0 2006.196.08:23:59.28#ibcon#read 5, iclass 27, count 0 2006.196.08:23:59.28#ibcon#about to read 6, iclass 27, count 0 2006.196.08:23:59.28#ibcon#read 6, iclass 27, count 0 2006.196.08:23:59.28#ibcon#end of sib2, iclass 27, count 0 2006.196.08:23:59.28#ibcon#*mode == 0, iclass 27, count 0 2006.196.08:23:59.28#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.196.08:23:59.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.196.08:23:59.28#ibcon#*before write, iclass 27, count 0 2006.196.08:23:59.28#ibcon#enter sib2, iclass 27, count 0 2006.196.08:23:59.28#ibcon#flushed, iclass 27, count 0 2006.196.08:23:59.28#ibcon#about to write, iclass 27, count 0 2006.196.08:23:59.28#ibcon#wrote, iclass 27, count 0 2006.196.08:23:59.28#ibcon#about to read 3, iclass 27, count 0 2006.196.08:23:59.32#ibcon#read 3, iclass 27, count 0 2006.196.08:23:59.32#ibcon#about to read 4, iclass 27, count 0 2006.196.08:23:59.32#ibcon#read 4, iclass 27, count 0 2006.196.08:23:59.32#ibcon#about to read 5, iclass 27, count 0 2006.196.08:23:59.32#ibcon#read 5, iclass 27, count 0 2006.196.08:23:59.32#ibcon#about to read 6, iclass 27, count 0 2006.196.08:23:59.32#ibcon#read 6, iclass 27, count 0 2006.196.08:23:59.32#ibcon#end of sib2, iclass 27, count 0 2006.196.08:23:59.32#ibcon#*after write, iclass 27, count 0 2006.196.08:23:59.32#ibcon#*before return 0, iclass 27, count 0 2006.196.08:23:59.32#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.196.08:23:59.32#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.196.08:23:59.32#ibcon#about to clear, iclass 27 cls_cnt 0 2006.196.08:23:59.32#ibcon#cleared, iclass 27 cls_cnt 0 2006.196.08:23:59.32$vc4f8/va=5,7 2006.196.08:23:59.32#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.196.08:23:59.32#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.196.08:23:59.32#ibcon#ireg 11 cls_cnt 2 2006.196.08:23:59.32#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.196.08:23:59.38#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.196.08:23:59.38#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.196.08:23:59.38#ibcon#enter wrdev, iclass 29, count 2 2006.196.08:23:59.38#ibcon#first serial, iclass 29, count 2 2006.196.08:23:59.38#ibcon#enter sib2, iclass 29, count 2 2006.196.08:23:59.38#ibcon#flushed, iclass 29, count 2 2006.196.08:23:59.38#ibcon#about to write, iclass 29, count 2 2006.196.08:23:59.38#ibcon#wrote, iclass 29, count 2 2006.196.08:23:59.38#ibcon#about to read 3, iclass 29, count 2 2006.196.08:23:59.40#ibcon#read 3, iclass 29, count 2 2006.196.08:23:59.40#ibcon#about to read 4, iclass 29, count 2 2006.196.08:23:59.40#ibcon#read 4, iclass 29, count 2 2006.196.08:23:59.40#ibcon#about to read 5, iclass 29, count 2 2006.196.08:23:59.40#ibcon#read 5, iclass 29, count 2 2006.196.08:23:59.40#ibcon#about to read 6, iclass 29, count 2 2006.196.08:23:59.40#ibcon#read 6, iclass 29, count 2 2006.196.08:23:59.40#ibcon#end of sib2, iclass 29, count 2 2006.196.08:23:59.40#ibcon#*mode == 0, iclass 29, count 2 2006.196.08:23:59.40#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.196.08:23:59.40#ibcon#[25=AT05-07\r\n] 2006.196.08:23:59.40#ibcon#*before write, iclass 29, count 2 2006.196.08:23:59.40#ibcon#enter sib2, iclass 29, count 2 2006.196.08:23:59.40#ibcon#flushed, iclass 29, count 2 2006.196.08:23:59.40#ibcon#about to write, iclass 29, count 2 2006.196.08:23:59.40#ibcon#wrote, iclass 29, count 2 2006.196.08:23:59.40#ibcon#about to read 3, iclass 29, count 2 2006.196.08:23:59.43#ibcon#read 3, iclass 29, count 2 2006.196.08:23:59.43#ibcon#about to read 4, iclass 29, count 2 2006.196.08:23:59.43#ibcon#read 4, iclass 29, count 2 2006.196.08:23:59.43#ibcon#about to read 5, iclass 29, count 2 2006.196.08:23:59.43#ibcon#read 5, iclass 29, count 2 2006.196.08:23:59.43#ibcon#about to read 6, iclass 29, count 2 2006.196.08:23:59.43#ibcon#read 6, iclass 29, count 2 2006.196.08:23:59.43#ibcon#end of sib2, iclass 29, count 2 2006.196.08:23:59.43#ibcon#*after write, iclass 29, count 2 2006.196.08:23:59.43#ibcon#*before return 0, iclass 29, count 2 2006.196.08:23:59.43#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.196.08:23:59.43#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.196.08:23:59.43#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.196.08:23:59.43#ibcon#ireg 7 cls_cnt 0 2006.196.08:23:59.43#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.196.08:23:59.55#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.196.08:23:59.55#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.196.08:23:59.55#ibcon#enter wrdev, iclass 29, count 0 2006.196.08:23:59.55#ibcon#first serial, iclass 29, count 0 2006.196.08:23:59.55#ibcon#enter sib2, iclass 29, count 0 2006.196.08:23:59.55#ibcon#flushed, iclass 29, count 0 2006.196.08:23:59.55#ibcon#about to write, iclass 29, count 0 2006.196.08:23:59.55#ibcon#wrote, iclass 29, count 0 2006.196.08:23:59.55#ibcon#about to read 3, iclass 29, count 0 2006.196.08:23:59.57#ibcon#read 3, iclass 29, count 0 2006.196.08:23:59.57#ibcon#about to read 4, iclass 29, count 0 2006.196.08:23:59.57#ibcon#read 4, iclass 29, count 0 2006.196.08:23:59.57#ibcon#about to read 5, iclass 29, count 0 2006.196.08:23:59.57#ibcon#read 5, iclass 29, count 0 2006.196.08:23:59.57#ibcon#about to read 6, iclass 29, count 0 2006.196.08:23:59.57#ibcon#read 6, iclass 29, count 0 2006.196.08:23:59.57#ibcon#end of sib2, iclass 29, count 0 2006.196.08:23:59.57#ibcon#*mode == 0, iclass 29, count 0 2006.196.08:23:59.57#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.196.08:23:59.57#ibcon#[25=USB\r\n] 2006.196.08:23:59.57#ibcon#*before write, iclass 29, count 0 2006.196.08:23:59.57#ibcon#enter sib2, iclass 29, count 0 2006.196.08:23:59.57#ibcon#flushed, iclass 29, count 0 2006.196.08:23:59.57#ibcon#about to write, iclass 29, count 0 2006.196.08:23:59.57#ibcon#wrote, iclass 29, count 0 2006.196.08:23:59.57#ibcon#about to read 3, iclass 29, count 0 2006.196.08:23:59.60#ibcon#read 3, iclass 29, count 0 2006.196.08:23:59.60#ibcon#about to read 4, iclass 29, count 0 2006.196.08:23:59.60#ibcon#read 4, iclass 29, count 0 2006.196.08:23:59.60#ibcon#about to read 5, iclass 29, count 0 2006.196.08:23:59.60#ibcon#read 5, iclass 29, count 0 2006.196.08:23:59.60#ibcon#about to read 6, iclass 29, count 0 2006.196.08:23:59.60#ibcon#read 6, iclass 29, count 0 2006.196.08:23:59.60#ibcon#end of sib2, iclass 29, count 0 2006.196.08:23:59.60#ibcon#*after write, iclass 29, count 0 2006.196.08:23:59.60#ibcon#*before return 0, iclass 29, count 0 2006.196.08:23:59.60#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.196.08:23:59.60#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.196.08:23:59.60#ibcon#about to clear, iclass 29 cls_cnt 0 2006.196.08:23:59.60#ibcon#cleared, iclass 29 cls_cnt 0 2006.196.08:23:59.60$vc4f8/valo=6,772.99 2006.196.08:23:59.60#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.196.08:23:59.60#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.196.08:23:59.60#ibcon#ireg 17 cls_cnt 0 2006.196.08:23:59.60#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.196.08:23:59.60#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.196.08:23:59.60#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.196.08:23:59.60#ibcon#enter wrdev, iclass 31, count 0 2006.196.08:23:59.60#ibcon#first serial, iclass 31, count 0 2006.196.08:23:59.60#ibcon#enter sib2, iclass 31, count 0 2006.196.08:23:59.60#ibcon#flushed, iclass 31, count 0 2006.196.08:23:59.60#ibcon#about to write, iclass 31, count 0 2006.196.08:23:59.60#ibcon#wrote, iclass 31, count 0 2006.196.08:23:59.60#ibcon#about to read 3, iclass 31, count 0 2006.196.08:23:59.62#ibcon#read 3, iclass 31, count 0 2006.196.08:23:59.62#ibcon#about to read 4, iclass 31, count 0 2006.196.08:23:59.62#ibcon#read 4, iclass 31, count 0 2006.196.08:23:59.62#ibcon#about to read 5, iclass 31, count 0 2006.196.08:23:59.62#ibcon#read 5, iclass 31, count 0 2006.196.08:23:59.62#ibcon#about to read 6, iclass 31, count 0 2006.196.08:23:59.62#ibcon#read 6, iclass 31, count 0 2006.196.08:23:59.62#ibcon#end of sib2, iclass 31, count 0 2006.196.08:23:59.62#ibcon#*mode == 0, iclass 31, count 0 2006.196.08:23:59.62#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.196.08:23:59.62#ibcon#[26=FRQ=06,772.99\r\n] 2006.196.08:23:59.62#ibcon#*before write, iclass 31, count 0 2006.196.08:23:59.62#ibcon#enter sib2, iclass 31, count 0 2006.196.08:23:59.62#ibcon#flushed, iclass 31, count 0 2006.196.08:23:59.62#ibcon#about to write, iclass 31, count 0 2006.196.08:23:59.62#ibcon#wrote, iclass 31, count 0 2006.196.08:23:59.62#ibcon#about to read 3, iclass 31, count 0 2006.196.08:23:59.67#ibcon#read 3, iclass 31, count 0 2006.196.08:23:59.67#ibcon#about to read 4, iclass 31, count 0 2006.196.08:23:59.67#ibcon#read 4, iclass 31, count 0 2006.196.08:23:59.67#ibcon#about to read 5, iclass 31, count 0 2006.196.08:23:59.67#ibcon#read 5, iclass 31, count 0 2006.196.08:23:59.67#ibcon#about to read 6, iclass 31, count 0 2006.196.08:23:59.67#ibcon#read 6, iclass 31, count 0 2006.196.08:23:59.67#ibcon#end of sib2, iclass 31, count 0 2006.196.08:23:59.67#ibcon#*after write, iclass 31, count 0 2006.196.08:23:59.67#ibcon#*before return 0, iclass 31, count 0 2006.196.08:23:59.67#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.196.08:23:59.67#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.196.08:23:59.67#ibcon#about to clear, iclass 31 cls_cnt 0 2006.196.08:23:59.67#ibcon#cleared, iclass 31 cls_cnt 0 2006.196.08:23:59.67$vc4f8/va=6,6 2006.196.08:23:59.67#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.196.08:23:59.67#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.196.08:23:59.67#ibcon#ireg 11 cls_cnt 2 2006.196.08:23:59.67#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.196.08:23:59.72#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.196.08:23:59.72#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.196.08:23:59.72#ibcon#enter wrdev, iclass 33, count 2 2006.196.08:23:59.72#ibcon#first serial, iclass 33, count 2 2006.196.08:23:59.72#ibcon#enter sib2, iclass 33, count 2 2006.196.08:23:59.72#ibcon#flushed, iclass 33, count 2 2006.196.08:23:59.72#ibcon#about to write, iclass 33, count 2 2006.196.08:23:59.72#ibcon#wrote, iclass 33, count 2 2006.196.08:23:59.72#ibcon#about to read 3, iclass 33, count 2 2006.196.08:23:59.74#ibcon#read 3, iclass 33, count 2 2006.196.08:23:59.74#ibcon#about to read 4, iclass 33, count 2 2006.196.08:23:59.74#ibcon#read 4, iclass 33, count 2 2006.196.08:23:59.74#ibcon#about to read 5, iclass 33, count 2 2006.196.08:23:59.74#ibcon#read 5, iclass 33, count 2 2006.196.08:23:59.74#ibcon#about to read 6, iclass 33, count 2 2006.196.08:23:59.74#ibcon#read 6, iclass 33, count 2 2006.196.08:23:59.74#ibcon#end of sib2, iclass 33, count 2 2006.196.08:23:59.74#ibcon#*mode == 0, iclass 33, count 2 2006.196.08:23:59.74#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.196.08:23:59.74#ibcon#[25=AT06-06\r\n] 2006.196.08:23:59.74#ibcon#*before write, iclass 33, count 2 2006.196.08:23:59.74#ibcon#enter sib2, iclass 33, count 2 2006.196.08:23:59.74#ibcon#flushed, iclass 33, count 2 2006.196.08:23:59.74#ibcon#about to write, iclass 33, count 2 2006.196.08:23:59.74#ibcon#wrote, iclass 33, count 2 2006.196.08:23:59.74#ibcon#about to read 3, iclass 33, count 2 2006.196.08:23:59.77#ibcon#read 3, iclass 33, count 2 2006.196.08:23:59.77#ibcon#about to read 4, iclass 33, count 2 2006.196.08:23:59.77#ibcon#read 4, iclass 33, count 2 2006.196.08:23:59.77#ibcon#about to read 5, iclass 33, count 2 2006.196.08:23:59.77#ibcon#read 5, iclass 33, count 2 2006.196.08:23:59.77#ibcon#about to read 6, iclass 33, count 2 2006.196.08:23:59.77#ibcon#read 6, iclass 33, count 2 2006.196.08:23:59.77#ibcon#end of sib2, iclass 33, count 2 2006.196.08:23:59.77#ibcon#*after write, iclass 33, count 2 2006.196.08:23:59.77#ibcon#*before return 0, iclass 33, count 2 2006.196.08:23:59.77#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.196.08:23:59.77#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.196.08:23:59.77#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.196.08:23:59.77#ibcon#ireg 7 cls_cnt 0 2006.196.08:23:59.77#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.196.08:23:59.89#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.196.08:23:59.89#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.196.08:23:59.89#ibcon#enter wrdev, iclass 33, count 0 2006.196.08:23:59.89#ibcon#first serial, iclass 33, count 0 2006.196.08:23:59.89#ibcon#enter sib2, iclass 33, count 0 2006.196.08:23:59.89#ibcon#flushed, iclass 33, count 0 2006.196.08:23:59.89#ibcon#about to write, iclass 33, count 0 2006.196.08:23:59.89#ibcon#wrote, iclass 33, count 0 2006.196.08:23:59.89#ibcon#about to read 3, iclass 33, count 0 2006.196.08:23:59.91#ibcon#read 3, iclass 33, count 0 2006.196.08:23:59.91#ibcon#about to read 4, iclass 33, count 0 2006.196.08:23:59.91#ibcon#read 4, iclass 33, count 0 2006.196.08:23:59.91#ibcon#about to read 5, iclass 33, count 0 2006.196.08:23:59.91#ibcon#read 5, iclass 33, count 0 2006.196.08:23:59.91#ibcon#about to read 6, iclass 33, count 0 2006.196.08:23:59.91#ibcon#read 6, iclass 33, count 0 2006.196.08:23:59.91#ibcon#end of sib2, iclass 33, count 0 2006.196.08:23:59.91#ibcon#*mode == 0, iclass 33, count 0 2006.196.08:23:59.91#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.196.08:23:59.91#ibcon#[25=USB\r\n] 2006.196.08:23:59.91#ibcon#*before write, iclass 33, count 0 2006.196.08:23:59.91#ibcon#enter sib2, iclass 33, count 0 2006.196.08:23:59.91#ibcon#flushed, iclass 33, count 0 2006.196.08:23:59.91#ibcon#about to write, iclass 33, count 0 2006.196.08:23:59.91#ibcon#wrote, iclass 33, count 0 2006.196.08:23:59.91#ibcon#about to read 3, iclass 33, count 0 2006.196.08:23:59.94#ibcon#read 3, iclass 33, count 0 2006.196.08:23:59.94#ibcon#about to read 4, iclass 33, count 0 2006.196.08:23:59.94#ibcon#read 4, iclass 33, count 0 2006.196.08:23:59.94#ibcon#about to read 5, iclass 33, count 0 2006.196.08:23:59.94#ibcon#read 5, iclass 33, count 0 2006.196.08:23:59.94#ibcon#about to read 6, iclass 33, count 0 2006.196.08:23:59.94#ibcon#read 6, iclass 33, count 0 2006.196.08:23:59.94#ibcon#end of sib2, iclass 33, count 0 2006.196.08:23:59.94#ibcon#*after write, iclass 33, count 0 2006.196.08:23:59.94#ibcon#*before return 0, iclass 33, count 0 2006.196.08:23:59.94#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.196.08:23:59.94#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.196.08:23:59.94#ibcon#about to clear, iclass 33 cls_cnt 0 2006.196.08:23:59.94#ibcon#cleared, iclass 33 cls_cnt 0 2006.196.08:23:59.94$vc4f8/valo=7,832.99 2006.196.08:23:59.94#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.196.08:23:59.94#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.196.08:23:59.94#ibcon#ireg 17 cls_cnt 0 2006.196.08:23:59.94#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.196.08:23:59.94#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.196.08:23:59.94#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.196.08:23:59.94#ibcon#enter wrdev, iclass 35, count 0 2006.196.08:23:59.94#ibcon#first serial, iclass 35, count 0 2006.196.08:23:59.94#ibcon#enter sib2, iclass 35, count 0 2006.196.08:23:59.94#ibcon#flushed, iclass 35, count 0 2006.196.08:23:59.94#ibcon#about to write, iclass 35, count 0 2006.196.08:23:59.94#ibcon#wrote, iclass 35, count 0 2006.196.08:23:59.94#ibcon#about to read 3, iclass 35, count 0 2006.196.08:23:59.96#ibcon#read 3, iclass 35, count 0 2006.196.08:23:59.96#ibcon#about to read 4, iclass 35, count 0 2006.196.08:23:59.96#ibcon#read 4, iclass 35, count 0 2006.196.08:23:59.96#ibcon#about to read 5, iclass 35, count 0 2006.196.08:23:59.96#ibcon#read 5, iclass 35, count 0 2006.196.08:23:59.96#ibcon#about to read 6, iclass 35, count 0 2006.196.08:23:59.96#ibcon#read 6, iclass 35, count 0 2006.196.08:23:59.96#ibcon#end of sib2, iclass 35, count 0 2006.196.08:23:59.96#ibcon#*mode == 0, iclass 35, count 0 2006.196.08:23:59.96#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.196.08:23:59.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.196.08:23:59.96#ibcon#*before write, iclass 35, count 0 2006.196.08:23:59.96#ibcon#enter sib2, iclass 35, count 0 2006.196.08:23:59.96#ibcon#flushed, iclass 35, count 0 2006.196.08:23:59.96#ibcon#about to write, iclass 35, count 0 2006.196.08:23:59.96#ibcon#wrote, iclass 35, count 0 2006.196.08:23:59.96#ibcon#about to read 3, iclass 35, count 0 2006.196.08:24:00.00#ibcon#read 3, iclass 35, count 0 2006.196.08:24:00.00#ibcon#about to read 4, iclass 35, count 0 2006.196.08:24:00.00#ibcon#read 4, iclass 35, count 0 2006.196.08:24:00.00#ibcon#about to read 5, iclass 35, count 0 2006.196.08:24:00.00#ibcon#read 5, iclass 35, count 0 2006.196.08:24:00.00#ibcon#about to read 6, iclass 35, count 0 2006.196.08:24:00.00#ibcon#read 6, iclass 35, count 0 2006.196.08:24:00.00#ibcon#end of sib2, iclass 35, count 0 2006.196.08:24:00.00#ibcon#*after write, iclass 35, count 0 2006.196.08:24:00.00#ibcon#*before return 0, iclass 35, count 0 2006.196.08:24:00.00#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.196.08:24:00.00#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.196.08:24:00.00#ibcon#about to clear, iclass 35 cls_cnt 0 2006.196.08:24:00.00#ibcon#cleared, iclass 35 cls_cnt 0 2006.196.08:24:00.00$vc4f8/va=7,6 2006.196.08:24:00.00#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.196.08:24:00.00#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.196.08:24:00.00#ibcon#ireg 11 cls_cnt 2 2006.196.08:24:00.00#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.196.08:24:00.06#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.196.08:24:00.06#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.196.08:24:00.06#ibcon#enter wrdev, iclass 37, count 2 2006.196.08:24:00.06#ibcon#first serial, iclass 37, count 2 2006.196.08:24:00.06#ibcon#enter sib2, iclass 37, count 2 2006.196.08:24:00.06#ibcon#flushed, iclass 37, count 2 2006.196.08:24:00.06#ibcon#about to write, iclass 37, count 2 2006.196.08:24:00.06#ibcon#wrote, iclass 37, count 2 2006.196.08:24:00.06#ibcon#about to read 3, iclass 37, count 2 2006.196.08:24:00.08#ibcon#read 3, iclass 37, count 2 2006.196.08:24:00.08#ibcon#about to read 4, iclass 37, count 2 2006.196.08:24:00.08#ibcon#read 4, iclass 37, count 2 2006.196.08:24:00.08#ibcon#about to read 5, iclass 37, count 2 2006.196.08:24:00.08#ibcon#read 5, iclass 37, count 2 2006.196.08:24:00.08#ibcon#about to read 6, iclass 37, count 2 2006.196.08:24:00.08#ibcon#read 6, iclass 37, count 2 2006.196.08:24:00.08#ibcon#end of sib2, iclass 37, count 2 2006.196.08:24:00.08#ibcon#*mode == 0, iclass 37, count 2 2006.196.08:24:00.08#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.196.08:24:00.08#ibcon#[25=AT07-06\r\n] 2006.196.08:24:00.08#ibcon#*before write, iclass 37, count 2 2006.196.08:24:00.08#ibcon#enter sib2, iclass 37, count 2 2006.196.08:24:00.08#ibcon#flushed, iclass 37, count 2 2006.196.08:24:00.08#ibcon#about to write, iclass 37, count 2 2006.196.08:24:00.08#ibcon#wrote, iclass 37, count 2 2006.196.08:24:00.08#ibcon#about to read 3, iclass 37, count 2 2006.196.08:24:00.11#ibcon#read 3, iclass 37, count 2 2006.196.08:24:00.11#ibcon#about to read 4, iclass 37, count 2 2006.196.08:24:00.11#ibcon#read 4, iclass 37, count 2 2006.196.08:24:00.11#ibcon#about to read 5, iclass 37, count 2 2006.196.08:24:00.11#ibcon#read 5, iclass 37, count 2 2006.196.08:24:00.11#ibcon#about to read 6, iclass 37, count 2 2006.196.08:24:00.11#ibcon#read 6, iclass 37, count 2 2006.196.08:24:00.11#ibcon#end of sib2, iclass 37, count 2 2006.196.08:24:00.11#ibcon#*after write, iclass 37, count 2 2006.196.08:24:00.11#ibcon#*before return 0, iclass 37, count 2 2006.196.08:24:00.11#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.196.08:24:00.11#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.196.08:24:00.11#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.196.08:24:00.11#ibcon#ireg 7 cls_cnt 0 2006.196.08:24:00.11#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.196.08:24:00.23#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.196.08:24:00.23#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.196.08:24:00.23#ibcon#enter wrdev, iclass 37, count 0 2006.196.08:24:00.23#ibcon#first serial, iclass 37, count 0 2006.196.08:24:00.23#ibcon#enter sib2, iclass 37, count 0 2006.196.08:24:00.23#ibcon#flushed, iclass 37, count 0 2006.196.08:24:00.23#ibcon#about to write, iclass 37, count 0 2006.196.08:24:00.23#ibcon#wrote, iclass 37, count 0 2006.196.08:24:00.23#ibcon#about to read 3, iclass 37, count 0 2006.196.08:24:00.25#ibcon#read 3, iclass 37, count 0 2006.196.08:24:00.25#ibcon#about to read 4, iclass 37, count 0 2006.196.08:24:00.25#ibcon#read 4, iclass 37, count 0 2006.196.08:24:00.25#ibcon#about to read 5, iclass 37, count 0 2006.196.08:24:00.25#ibcon#read 5, iclass 37, count 0 2006.196.08:24:00.25#ibcon#about to read 6, iclass 37, count 0 2006.196.08:24:00.25#ibcon#read 6, iclass 37, count 0 2006.196.08:24:00.25#ibcon#end of sib2, iclass 37, count 0 2006.196.08:24:00.25#ibcon#*mode == 0, iclass 37, count 0 2006.196.08:24:00.25#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.196.08:24:00.25#ibcon#[25=USB\r\n] 2006.196.08:24:00.25#ibcon#*before write, iclass 37, count 0 2006.196.08:24:00.25#ibcon#enter sib2, iclass 37, count 0 2006.196.08:24:00.25#ibcon#flushed, iclass 37, count 0 2006.196.08:24:00.25#ibcon#about to write, iclass 37, count 0 2006.196.08:24:00.25#ibcon#wrote, iclass 37, count 0 2006.196.08:24:00.25#ibcon#about to read 3, iclass 37, count 0 2006.196.08:24:00.28#ibcon#read 3, iclass 37, count 0 2006.196.08:24:00.28#ibcon#about to read 4, iclass 37, count 0 2006.196.08:24:00.28#ibcon#read 4, iclass 37, count 0 2006.196.08:24:00.28#ibcon#about to read 5, iclass 37, count 0 2006.196.08:24:00.28#ibcon#read 5, iclass 37, count 0 2006.196.08:24:00.28#ibcon#about to read 6, iclass 37, count 0 2006.196.08:24:00.28#ibcon#read 6, iclass 37, count 0 2006.196.08:24:00.28#ibcon#end of sib2, iclass 37, count 0 2006.196.08:24:00.28#ibcon#*after write, iclass 37, count 0 2006.196.08:24:00.28#ibcon#*before return 0, iclass 37, count 0 2006.196.08:24:00.28#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.196.08:24:00.28#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.196.08:24:00.28#ibcon#about to clear, iclass 37 cls_cnt 0 2006.196.08:24:00.28#ibcon#cleared, iclass 37 cls_cnt 0 2006.196.08:24:00.28$vc4f8/valo=8,852.99 2006.196.08:24:00.28#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.196.08:24:00.28#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.196.08:24:00.28#ibcon#ireg 17 cls_cnt 0 2006.196.08:24:00.28#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.196.08:24:00.28#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.196.08:24:00.28#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.196.08:24:00.28#ibcon#enter wrdev, iclass 39, count 0 2006.196.08:24:00.28#ibcon#first serial, iclass 39, count 0 2006.196.08:24:00.28#ibcon#enter sib2, iclass 39, count 0 2006.196.08:24:00.28#ibcon#flushed, iclass 39, count 0 2006.196.08:24:00.28#ibcon#about to write, iclass 39, count 0 2006.196.08:24:00.28#ibcon#wrote, iclass 39, count 0 2006.196.08:24:00.28#ibcon#about to read 3, iclass 39, count 0 2006.196.08:24:00.30#ibcon#read 3, iclass 39, count 0 2006.196.08:24:00.30#ibcon#about to read 4, iclass 39, count 0 2006.196.08:24:00.30#ibcon#read 4, iclass 39, count 0 2006.196.08:24:00.30#ibcon#about to read 5, iclass 39, count 0 2006.196.08:24:00.30#ibcon#read 5, iclass 39, count 0 2006.196.08:24:00.30#ibcon#about to read 6, iclass 39, count 0 2006.196.08:24:00.30#ibcon#read 6, iclass 39, count 0 2006.196.08:24:00.30#ibcon#end of sib2, iclass 39, count 0 2006.196.08:24:00.30#ibcon#*mode == 0, iclass 39, count 0 2006.196.08:24:00.30#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.196.08:24:00.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.196.08:24:00.30#ibcon#*before write, iclass 39, count 0 2006.196.08:24:00.30#ibcon#enter sib2, iclass 39, count 0 2006.196.08:24:00.30#ibcon#flushed, iclass 39, count 0 2006.196.08:24:00.30#ibcon#about to write, iclass 39, count 0 2006.196.08:24:00.30#ibcon#wrote, iclass 39, count 0 2006.196.08:24:00.30#ibcon#about to read 3, iclass 39, count 0 2006.196.08:24:00.34#ibcon#read 3, iclass 39, count 0 2006.196.08:24:00.34#ibcon#about to read 4, iclass 39, count 0 2006.196.08:24:00.34#ibcon#read 4, iclass 39, count 0 2006.196.08:24:00.34#ibcon#about to read 5, iclass 39, count 0 2006.196.08:24:00.34#ibcon#read 5, iclass 39, count 0 2006.196.08:24:00.34#ibcon#about to read 6, iclass 39, count 0 2006.196.08:24:00.34#ibcon#read 6, iclass 39, count 0 2006.196.08:24:00.34#ibcon#end of sib2, iclass 39, count 0 2006.196.08:24:00.34#ibcon#*after write, iclass 39, count 0 2006.196.08:24:00.34#ibcon#*before return 0, iclass 39, count 0 2006.196.08:24:00.34#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.196.08:24:00.34#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.196.08:24:00.34#ibcon#about to clear, iclass 39 cls_cnt 0 2006.196.08:24:00.34#ibcon#cleared, iclass 39 cls_cnt 0 2006.196.08:24:00.34$vc4f8/va=8,7 2006.196.08:24:00.34#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.196.08:24:00.34#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.196.08:24:00.34#ibcon#ireg 11 cls_cnt 2 2006.196.08:24:00.34#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.196.08:24:00.40#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.196.08:24:00.40#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.196.08:24:00.40#ibcon#enter wrdev, iclass 3, count 2 2006.196.08:24:00.40#ibcon#first serial, iclass 3, count 2 2006.196.08:24:00.40#ibcon#enter sib2, iclass 3, count 2 2006.196.08:24:00.40#ibcon#flushed, iclass 3, count 2 2006.196.08:24:00.40#ibcon#about to write, iclass 3, count 2 2006.196.08:24:00.40#ibcon#wrote, iclass 3, count 2 2006.196.08:24:00.40#ibcon#about to read 3, iclass 3, count 2 2006.196.08:24:00.42#ibcon#read 3, iclass 3, count 2 2006.196.08:24:00.42#ibcon#about to read 4, iclass 3, count 2 2006.196.08:24:00.42#ibcon#read 4, iclass 3, count 2 2006.196.08:24:00.42#ibcon#about to read 5, iclass 3, count 2 2006.196.08:24:00.42#ibcon#read 5, iclass 3, count 2 2006.196.08:24:00.42#ibcon#about to read 6, iclass 3, count 2 2006.196.08:24:00.42#ibcon#read 6, iclass 3, count 2 2006.196.08:24:00.42#ibcon#end of sib2, iclass 3, count 2 2006.196.08:24:00.42#ibcon#*mode == 0, iclass 3, count 2 2006.196.08:24:00.42#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.196.08:24:00.42#ibcon#[25=AT08-07\r\n] 2006.196.08:24:00.42#ibcon#*before write, iclass 3, count 2 2006.196.08:24:00.42#ibcon#enter sib2, iclass 3, count 2 2006.196.08:24:00.42#ibcon#flushed, iclass 3, count 2 2006.196.08:24:00.42#ibcon#about to write, iclass 3, count 2 2006.196.08:24:00.42#ibcon#wrote, iclass 3, count 2 2006.196.08:24:00.42#ibcon#about to read 3, iclass 3, count 2 2006.196.08:24:00.45#ibcon#read 3, iclass 3, count 2 2006.196.08:24:00.45#ibcon#about to read 4, iclass 3, count 2 2006.196.08:24:00.45#ibcon#read 4, iclass 3, count 2 2006.196.08:24:00.45#ibcon#about to read 5, iclass 3, count 2 2006.196.08:24:00.45#ibcon#read 5, iclass 3, count 2 2006.196.08:24:00.45#ibcon#about to read 6, iclass 3, count 2 2006.196.08:24:00.45#ibcon#read 6, iclass 3, count 2 2006.196.08:24:00.45#ibcon#end of sib2, iclass 3, count 2 2006.196.08:24:00.45#ibcon#*after write, iclass 3, count 2 2006.196.08:24:00.45#ibcon#*before return 0, iclass 3, count 2 2006.196.08:24:00.45#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.196.08:24:00.45#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.196.08:24:00.45#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.196.08:24:00.45#ibcon#ireg 7 cls_cnt 0 2006.196.08:24:00.45#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.196.08:24:00.57#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.196.08:24:00.57#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.196.08:24:00.57#ibcon#enter wrdev, iclass 3, count 0 2006.196.08:24:00.57#ibcon#first serial, iclass 3, count 0 2006.196.08:24:00.57#ibcon#enter sib2, iclass 3, count 0 2006.196.08:24:00.57#ibcon#flushed, iclass 3, count 0 2006.196.08:24:00.57#ibcon#about to write, iclass 3, count 0 2006.196.08:24:00.57#ibcon#wrote, iclass 3, count 0 2006.196.08:24:00.57#ibcon#about to read 3, iclass 3, count 0 2006.196.08:24:00.59#ibcon#read 3, iclass 3, count 0 2006.196.08:24:00.59#ibcon#about to read 4, iclass 3, count 0 2006.196.08:24:00.59#ibcon#read 4, iclass 3, count 0 2006.196.08:24:00.59#ibcon#about to read 5, iclass 3, count 0 2006.196.08:24:00.59#ibcon#read 5, iclass 3, count 0 2006.196.08:24:00.59#ibcon#about to read 6, iclass 3, count 0 2006.196.08:24:00.59#ibcon#read 6, iclass 3, count 0 2006.196.08:24:00.59#ibcon#end of sib2, iclass 3, count 0 2006.196.08:24:00.59#ibcon#*mode == 0, iclass 3, count 0 2006.196.08:24:00.59#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.196.08:24:00.59#ibcon#[25=USB\r\n] 2006.196.08:24:00.59#ibcon#*before write, iclass 3, count 0 2006.196.08:24:00.59#ibcon#enter sib2, iclass 3, count 0 2006.196.08:24:00.59#ibcon#flushed, iclass 3, count 0 2006.196.08:24:00.59#ibcon#about to write, iclass 3, count 0 2006.196.08:24:00.59#ibcon#wrote, iclass 3, count 0 2006.196.08:24:00.59#ibcon#about to read 3, iclass 3, count 0 2006.196.08:24:00.62#ibcon#read 3, iclass 3, count 0 2006.196.08:24:00.62#ibcon#about to read 4, iclass 3, count 0 2006.196.08:24:00.62#ibcon#read 4, iclass 3, count 0 2006.196.08:24:00.62#ibcon#about to read 5, iclass 3, count 0 2006.196.08:24:00.62#ibcon#read 5, iclass 3, count 0 2006.196.08:24:00.62#ibcon#about to read 6, iclass 3, count 0 2006.196.08:24:00.62#ibcon#read 6, iclass 3, count 0 2006.196.08:24:00.62#ibcon#end of sib2, iclass 3, count 0 2006.196.08:24:00.62#ibcon#*after write, iclass 3, count 0 2006.196.08:24:00.62#ibcon#*before return 0, iclass 3, count 0 2006.196.08:24:00.62#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.196.08:24:00.62#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.196.08:24:00.62#ibcon#about to clear, iclass 3 cls_cnt 0 2006.196.08:24:00.62#ibcon#cleared, iclass 3 cls_cnt 0 2006.196.08:24:00.62$vc4f8/vblo=1,632.99 2006.196.08:24:00.62#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.196.08:24:00.62#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.196.08:24:00.62#ibcon#ireg 17 cls_cnt 0 2006.196.08:24:00.62#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.196.08:24:00.62#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.196.08:24:00.62#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.196.08:24:00.62#ibcon#enter wrdev, iclass 5, count 0 2006.196.08:24:00.62#ibcon#first serial, iclass 5, count 0 2006.196.08:24:00.62#ibcon#enter sib2, iclass 5, count 0 2006.196.08:24:00.62#ibcon#flushed, iclass 5, count 0 2006.196.08:24:00.62#ibcon#about to write, iclass 5, count 0 2006.196.08:24:00.62#ibcon#wrote, iclass 5, count 0 2006.196.08:24:00.62#ibcon#about to read 3, iclass 5, count 0 2006.196.08:24:00.64#ibcon#read 3, iclass 5, count 0 2006.196.08:24:00.64#ibcon#about to read 4, iclass 5, count 0 2006.196.08:24:00.64#ibcon#read 4, iclass 5, count 0 2006.196.08:24:00.64#ibcon#about to read 5, iclass 5, count 0 2006.196.08:24:00.64#ibcon#read 5, iclass 5, count 0 2006.196.08:24:00.64#ibcon#about to read 6, iclass 5, count 0 2006.196.08:24:00.64#ibcon#read 6, iclass 5, count 0 2006.196.08:24:00.64#ibcon#end of sib2, iclass 5, count 0 2006.196.08:24:00.64#ibcon#*mode == 0, iclass 5, count 0 2006.196.08:24:00.64#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.196.08:24:00.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.196.08:24:00.64#ibcon#*before write, iclass 5, count 0 2006.196.08:24:00.64#ibcon#enter sib2, iclass 5, count 0 2006.196.08:24:00.64#ibcon#flushed, iclass 5, count 0 2006.196.08:24:00.64#ibcon#about to write, iclass 5, count 0 2006.196.08:24:00.64#ibcon#wrote, iclass 5, count 0 2006.196.08:24:00.64#ibcon#about to read 3, iclass 5, count 0 2006.196.08:24:00.69#ibcon#read 3, iclass 5, count 0 2006.196.08:24:00.69#ibcon#about to read 4, iclass 5, count 0 2006.196.08:24:00.69#ibcon#read 4, iclass 5, count 0 2006.196.08:24:00.69#ibcon#about to read 5, iclass 5, count 0 2006.196.08:24:00.69#ibcon#read 5, iclass 5, count 0 2006.196.08:24:00.69#ibcon#about to read 6, iclass 5, count 0 2006.196.08:24:00.69#ibcon#read 6, iclass 5, count 0 2006.196.08:24:00.69#ibcon#end of sib2, iclass 5, count 0 2006.196.08:24:00.69#ibcon#*after write, iclass 5, count 0 2006.196.08:24:00.69#ibcon#*before return 0, iclass 5, count 0 2006.196.08:24:00.69#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.196.08:24:00.69#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.196.08:24:00.69#ibcon#about to clear, iclass 5 cls_cnt 0 2006.196.08:24:00.69#ibcon#cleared, iclass 5 cls_cnt 0 2006.196.08:24:00.69$vc4f8/vb=1,4 2006.196.08:24:00.69#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.196.08:24:00.69#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.196.08:24:00.69#ibcon#ireg 11 cls_cnt 2 2006.196.08:24:00.69#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.196.08:24:00.69#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.196.08:24:00.69#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.196.08:24:00.69#ibcon#enter wrdev, iclass 7, count 2 2006.196.08:24:00.69#ibcon#first serial, iclass 7, count 2 2006.196.08:24:00.69#ibcon#enter sib2, iclass 7, count 2 2006.196.08:24:00.69#ibcon#flushed, iclass 7, count 2 2006.196.08:24:00.69#ibcon#about to write, iclass 7, count 2 2006.196.08:24:00.69#ibcon#wrote, iclass 7, count 2 2006.196.08:24:00.69#ibcon#about to read 3, iclass 7, count 2 2006.196.08:24:00.71#ibcon#read 3, iclass 7, count 2 2006.196.08:24:00.71#ibcon#about to read 4, iclass 7, count 2 2006.196.08:24:00.71#ibcon#read 4, iclass 7, count 2 2006.196.08:24:00.71#ibcon#about to read 5, iclass 7, count 2 2006.196.08:24:00.71#ibcon#read 5, iclass 7, count 2 2006.196.08:24:00.71#ibcon#about to read 6, iclass 7, count 2 2006.196.08:24:00.71#ibcon#read 6, iclass 7, count 2 2006.196.08:24:00.71#ibcon#end of sib2, iclass 7, count 2 2006.196.08:24:00.71#ibcon#*mode == 0, iclass 7, count 2 2006.196.08:24:00.71#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.196.08:24:00.71#ibcon#[27=AT01-04\r\n] 2006.196.08:24:00.71#ibcon#*before write, iclass 7, count 2 2006.196.08:24:00.71#ibcon#enter sib2, iclass 7, count 2 2006.196.08:24:00.71#ibcon#flushed, iclass 7, count 2 2006.196.08:24:00.71#ibcon#about to write, iclass 7, count 2 2006.196.08:24:00.71#ibcon#wrote, iclass 7, count 2 2006.196.08:24:00.71#ibcon#about to read 3, iclass 7, count 2 2006.196.08:24:00.74#ibcon#read 3, iclass 7, count 2 2006.196.08:24:00.74#ibcon#about to read 4, iclass 7, count 2 2006.196.08:24:00.74#ibcon#read 4, iclass 7, count 2 2006.196.08:24:00.74#ibcon#about to read 5, iclass 7, count 2 2006.196.08:24:00.74#ibcon#read 5, iclass 7, count 2 2006.196.08:24:00.74#ibcon#about to read 6, iclass 7, count 2 2006.196.08:24:00.74#ibcon#read 6, iclass 7, count 2 2006.196.08:24:00.74#ibcon#end of sib2, iclass 7, count 2 2006.196.08:24:00.74#ibcon#*after write, iclass 7, count 2 2006.196.08:24:00.74#ibcon#*before return 0, iclass 7, count 2 2006.196.08:24:00.74#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.196.08:24:00.74#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.196.08:24:00.74#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.196.08:24:00.74#ibcon#ireg 7 cls_cnt 0 2006.196.08:24:00.74#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.196.08:24:00.86#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.196.08:24:00.86#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.196.08:24:00.86#ibcon#enter wrdev, iclass 7, count 0 2006.196.08:24:00.86#ibcon#first serial, iclass 7, count 0 2006.196.08:24:00.86#ibcon#enter sib2, iclass 7, count 0 2006.196.08:24:00.86#ibcon#flushed, iclass 7, count 0 2006.196.08:24:00.86#ibcon#about to write, iclass 7, count 0 2006.196.08:24:00.86#ibcon#wrote, iclass 7, count 0 2006.196.08:24:00.86#ibcon#about to read 3, iclass 7, count 0 2006.196.08:24:00.88#ibcon#read 3, iclass 7, count 0 2006.196.08:24:00.88#ibcon#about to read 4, iclass 7, count 0 2006.196.08:24:00.88#ibcon#read 4, iclass 7, count 0 2006.196.08:24:00.88#ibcon#about to read 5, iclass 7, count 0 2006.196.08:24:00.88#ibcon#read 5, iclass 7, count 0 2006.196.08:24:00.88#ibcon#about to read 6, iclass 7, count 0 2006.196.08:24:00.88#ibcon#read 6, iclass 7, count 0 2006.196.08:24:00.88#ibcon#end of sib2, iclass 7, count 0 2006.196.08:24:00.88#ibcon#*mode == 0, iclass 7, count 0 2006.196.08:24:00.88#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.196.08:24:00.88#ibcon#[27=USB\r\n] 2006.196.08:24:00.88#ibcon#*before write, iclass 7, count 0 2006.196.08:24:00.88#ibcon#enter sib2, iclass 7, count 0 2006.196.08:24:00.88#ibcon#flushed, iclass 7, count 0 2006.196.08:24:00.88#ibcon#about to write, iclass 7, count 0 2006.196.08:24:00.88#ibcon#wrote, iclass 7, count 0 2006.196.08:24:00.88#ibcon#about to read 3, iclass 7, count 0 2006.196.08:24:00.91#ibcon#read 3, iclass 7, count 0 2006.196.08:24:00.91#ibcon#about to read 4, iclass 7, count 0 2006.196.08:24:00.91#ibcon#read 4, iclass 7, count 0 2006.196.08:24:00.91#ibcon#about to read 5, iclass 7, count 0 2006.196.08:24:00.91#ibcon#read 5, iclass 7, count 0 2006.196.08:24:00.91#ibcon#about to read 6, iclass 7, count 0 2006.196.08:24:00.91#ibcon#read 6, iclass 7, count 0 2006.196.08:24:00.91#ibcon#end of sib2, iclass 7, count 0 2006.196.08:24:00.91#ibcon#*after write, iclass 7, count 0 2006.196.08:24:00.91#ibcon#*before return 0, iclass 7, count 0 2006.196.08:24:00.91#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.196.08:24:00.91#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.196.08:24:00.91#ibcon#about to clear, iclass 7 cls_cnt 0 2006.196.08:24:00.91#ibcon#cleared, iclass 7 cls_cnt 0 2006.196.08:24:00.91$vc4f8/vblo=2,640.99 2006.196.08:24:00.91#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.196.08:24:00.91#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.196.08:24:00.91#ibcon#ireg 17 cls_cnt 0 2006.196.08:24:00.91#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.196.08:24:00.91#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.196.08:24:00.91#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.196.08:24:00.91#ibcon#enter wrdev, iclass 11, count 0 2006.196.08:24:00.91#ibcon#first serial, iclass 11, count 0 2006.196.08:24:00.91#ibcon#enter sib2, iclass 11, count 0 2006.196.08:24:00.91#ibcon#flushed, iclass 11, count 0 2006.196.08:24:00.91#ibcon#about to write, iclass 11, count 0 2006.196.08:24:00.91#ibcon#wrote, iclass 11, count 0 2006.196.08:24:00.91#ibcon#about to read 3, iclass 11, count 0 2006.196.08:24:00.93#ibcon#read 3, iclass 11, count 0 2006.196.08:24:00.93#ibcon#about to read 4, iclass 11, count 0 2006.196.08:24:00.93#ibcon#read 4, iclass 11, count 0 2006.196.08:24:00.93#ibcon#about to read 5, iclass 11, count 0 2006.196.08:24:00.93#ibcon#read 5, iclass 11, count 0 2006.196.08:24:00.93#ibcon#about to read 6, iclass 11, count 0 2006.196.08:24:00.93#ibcon#read 6, iclass 11, count 0 2006.196.08:24:00.93#ibcon#end of sib2, iclass 11, count 0 2006.196.08:24:00.93#ibcon#*mode == 0, iclass 11, count 0 2006.196.08:24:00.93#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.196.08:24:00.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.196.08:24:00.93#ibcon#*before write, iclass 11, count 0 2006.196.08:24:00.93#ibcon#enter sib2, iclass 11, count 0 2006.196.08:24:00.93#ibcon#flushed, iclass 11, count 0 2006.196.08:24:00.93#ibcon#about to write, iclass 11, count 0 2006.196.08:24:00.93#ibcon#wrote, iclass 11, count 0 2006.196.08:24:00.93#ibcon#about to read 3, iclass 11, count 0 2006.196.08:24:00.97#ibcon#read 3, iclass 11, count 0 2006.196.08:24:00.97#ibcon#about to read 4, iclass 11, count 0 2006.196.08:24:00.97#ibcon#read 4, iclass 11, count 0 2006.196.08:24:00.97#ibcon#about to read 5, iclass 11, count 0 2006.196.08:24:00.97#ibcon#read 5, iclass 11, count 0 2006.196.08:24:00.97#ibcon#about to read 6, iclass 11, count 0 2006.196.08:24:00.97#ibcon#read 6, iclass 11, count 0 2006.196.08:24:00.97#ibcon#end of sib2, iclass 11, count 0 2006.196.08:24:00.97#ibcon#*after write, iclass 11, count 0 2006.196.08:24:00.97#ibcon#*before return 0, iclass 11, count 0 2006.196.08:24:00.97#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.196.08:24:00.97#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.196.08:24:00.97#ibcon#about to clear, iclass 11 cls_cnt 0 2006.196.08:24:00.97#ibcon#cleared, iclass 11 cls_cnt 0 2006.196.08:24:00.97$vc4f8/vb=2,4 2006.196.08:24:00.97#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.196.08:24:00.97#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.196.08:24:00.97#ibcon#ireg 11 cls_cnt 2 2006.196.08:24:00.97#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.196.08:24:01.03#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.196.08:24:01.03#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.196.08:24:01.03#ibcon#enter wrdev, iclass 13, count 2 2006.196.08:24:01.03#ibcon#first serial, iclass 13, count 2 2006.196.08:24:01.03#ibcon#enter sib2, iclass 13, count 2 2006.196.08:24:01.03#ibcon#flushed, iclass 13, count 2 2006.196.08:24:01.03#ibcon#about to write, iclass 13, count 2 2006.196.08:24:01.03#ibcon#wrote, iclass 13, count 2 2006.196.08:24:01.03#ibcon#about to read 3, iclass 13, count 2 2006.196.08:24:01.05#ibcon#read 3, iclass 13, count 2 2006.196.08:24:01.05#ibcon#about to read 4, iclass 13, count 2 2006.196.08:24:01.05#ibcon#read 4, iclass 13, count 2 2006.196.08:24:01.05#ibcon#about to read 5, iclass 13, count 2 2006.196.08:24:01.05#ibcon#read 5, iclass 13, count 2 2006.196.08:24:01.05#ibcon#about to read 6, iclass 13, count 2 2006.196.08:24:01.05#ibcon#read 6, iclass 13, count 2 2006.196.08:24:01.05#ibcon#end of sib2, iclass 13, count 2 2006.196.08:24:01.05#ibcon#*mode == 0, iclass 13, count 2 2006.196.08:24:01.05#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.196.08:24:01.05#ibcon#[27=AT02-04\r\n] 2006.196.08:24:01.05#ibcon#*before write, iclass 13, count 2 2006.196.08:24:01.05#ibcon#enter sib2, iclass 13, count 2 2006.196.08:24:01.05#ibcon#flushed, iclass 13, count 2 2006.196.08:24:01.05#ibcon#about to write, iclass 13, count 2 2006.196.08:24:01.05#ibcon#wrote, iclass 13, count 2 2006.196.08:24:01.05#ibcon#about to read 3, iclass 13, count 2 2006.196.08:24:01.08#ibcon#read 3, iclass 13, count 2 2006.196.08:24:01.08#ibcon#about to read 4, iclass 13, count 2 2006.196.08:24:01.08#ibcon#read 4, iclass 13, count 2 2006.196.08:24:01.08#ibcon#about to read 5, iclass 13, count 2 2006.196.08:24:01.08#ibcon#read 5, iclass 13, count 2 2006.196.08:24:01.08#ibcon#about to read 6, iclass 13, count 2 2006.196.08:24:01.08#ibcon#read 6, iclass 13, count 2 2006.196.08:24:01.08#ibcon#end of sib2, iclass 13, count 2 2006.196.08:24:01.08#ibcon#*after write, iclass 13, count 2 2006.196.08:24:01.08#ibcon#*before return 0, iclass 13, count 2 2006.196.08:24:01.08#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.196.08:24:01.08#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.196.08:24:01.08#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.196.08:24:01.08#ibcon#ireg 7 cls_cnt 0 2006.196.08:24:01.08#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.196.08:24:01.20#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.196.08:24:01.20#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.196.08:24:01.20#ibcon#enter wrdev, iclass 13, count 0 2006.196.08:24:01.20#ibcon#first serial, iclass 13, count 0 2006.196.08:24:01.20#ibcon#enter sib2, iclass 13, count 0 2006.196.08:24:01.20#ibcon#flushed, iclass 13, count 0 2006.196.08:24:01.20#ibcon#about to write, iclass 13, count 0 2006.196.08:24:01.20#ibcon#wrote, iclass 13, count 0 2006.196.08:24:01.20#ibcon#about to read 3, iclass 13, count 0 2006.196.08:24:01.22#ibcon#read 3, iclass 13, count 0 2006.196.08:24:01.22#ibcon#about to read 4, iclass 13, count 0 2006.196.08:24:01.22#ibcon#read 4, iclass 13, count 0 2006.196.08:24:01.22#ibcon#about to read 5, iclass 13, count 0 2006.196.08:24:01.22#ibcon#read 5, iclass 13, count 0 2006.196.08:24:01.22#ibcon#about to read 6, iclass 13, count 0 2006.196.08:24:01.22#ibcon#read 6, iclass 13, count 0 2006.196.08:24:01.22#ibcon#end of sib2, iclass 13, count 0 2006.196.08:24:01.22#ibcon#*mode == 0, iclass 13, count 0 2006.196.08:24:01.22#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.196.08:24:01.22#ibcon#[27=USB\r\n] 2006.196.08:24:01.22#ibcon#*before write, iclass 13, count 0 2006.196.08:24:01.22#ibcon#enter sib2, iclass 13, count 0 2006.196.08:24:01.22#ibcon#flushed, iclass 13, count 0 2006.196.08:24:01.22#ibcon#about to write, iclass 13, count 0 2006.196.08:24:01.22#ibcon#wrote, iclass 13, count 0 2006.196.08:24:01.22#ibcon#about to read 3, iclass 13, count 0 2006.196.08:24:01.25#ibcon#read 3, iclass 13, count 0 2006.196.08:24:01.25#ibcon#about to read 4, iclass 13, count 0 2006.196.08:24:01.25#ibcon#read 4, iclass 13, count 0 2006.196.08:24:01.25#ibcon#about to read 5, iclass 13, count 0 2006.196.08:24:01.25#ibcon#read 5, iclass 13, count 0 2006.196.08:24:01.25#ibcon#about to read 6, iclass 13, count 0 2006.196.08:24:01.25#ibcon#read 6, iclass 13, count 0 2006.196.08:24:01.25#ibcon#end of sib2, iclass 13, count 0 2006.196.08:24:01.25#ibcon#*after write, iclass 13, count 0 2006.196.08:24:01.25#ibcon#*before return 0, iclass 13, count 0 2006.196.08:24:01.25#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.196.08:24:01.25#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.196.08:24:01.25#ibcon#about to clear, iclass 13 cls_cnt 0 2006.196.08:24:01.25#ibcon#cleared, iclass 13 cls_cnt 0 2006.196.08:24:01.25$vc4f8/vblo=3,656.99 2006.196.08:24:01.25#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.196.08:24:01.25#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.196.08:24:01.25#ibcon#ireg 17 cls_cnt 0 2006.196.08:24:01.25#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.196.08:24:01.25#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.196.08:24:01.25#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.196.08:24:01.25#ibcon#enter wrdev, iclass 15, count 0 2006.196.08:24:01.25#ibcon#first serial, iclass 15, count 0 2006.196.08:24:01.25#ibcon#enter sib2, iclass 15, count 0 2006.196.08:24:01.25#ibcon#flushed, iclass 15, count 0 2006.196.08:24:01.25#ibcon#about to write, iclass 15, count 0 2006.196.08:24:01.25#ibcon#wrote, iclass 15, count 0 2006.196.08:24:01.25#ibcon#about to read 3, iclass 15, count 0 2006.196.08:24:01.27#ibcon#read 3, iclass 15, count 0 2006.196.08:24:01.27#ibcon#about to read 4, iclass 15, count 0 2006.196.08:24:01.27#ibcon#read 4, iclass 15, count 0 2006.196.08:24:01.27#ibcon#about to read 5, iclass 15, count 0 2006.196.08:24:01.27#ibcon#read 5, iclass 15, count 0 2006.196.08:24:01.27#ibcon#about to read 6, iclass 15, count 0 2006.196.08:24:01.27#ibcon#read 6, iclass 15, count 0 2006.196.08:24:01.27#ibcon#end of sib2, iclass 15, count 0 2006.196.08:24:01.27#ibcon#*mode == 0, iclass 15, count 0 2006.196.08:24:01.27#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.196.08:24:01.27#ibcon#[28=FRQ=03,656.99\r\n] 2006.196.08:24:01.27#ibcon#*before write, iclass 15, count 0 2006.196.08:24:01.27#ibcon#enter sib2, iclass 15, count 0 2006.196.08:24:01.27#ibcon#flushed, iclass 15, count 0 2006.196.08:24:01.27#ibcon#about to write, iclass 15, count 0 2006.196.08:24:01.27#ibcon#wrote, iclass 15, count 0 2006.196.08:24:01.27#ibcon#about to read 3, iclass 15, count 0 2006.196.08:24:01.31#ibcon#read 3, iclass 15, count 0 2006.196.08:24:01.31#ibcon#about to read 4, iclass 15, count 0 2006.196.08:24:01.31#ibcon#read 4, iclass 15, count 0 2006.196.08:24:01.31#ibcon#about to read 5, iclass 15, count 0 2006.196.08:24:01.31#ibcon#read 5, iclass 15, count 0 2006.196.08:24:01.31#ibcon#about to read 6, iclass 15, count 0 2006.196.08:24:01.31#ibcon#read 6, iclass 15, count 0 2006.196.08:24:01.31#ibcon#end of sib2, iclass 15, count 0 2006.196.08:24:01.31#ibcon#*after write, iclass 15, count 0 2006.196.08:24:01.31#ibcon#*before return 0, iclass 15, count 0 2006.196.08:24:01.31#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.196.08:24:01.31#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.196.08:24:01.31#ibcon#about to clear, iclass 15 cls_cnt 0 2006.196.08:24:01.31#ibcon#cleared, iclass 15 cls_cnt 0 2006.196.08:24:01.31$vc4f8/vb=3,4 2006.196.08:24:01.31#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.196.08:24:01.31#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.196.08:24:01.31#ibcon#ireg 11 cls_cnt 2 2006.196.08:24:01.31#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.196.08:24:01.37#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.196.08:24:01.37#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.196.08:24:01.37#ibcon#enter wrdev, iclass 17, count 2 2006.196.08:24:01.37#ibcon#first serial, iclass 17, count 2 2006.196.08:24:01.37#ibcon#enter sib2, iclass 17, count 2 2006.196.08:24:01.37#ibcon#flushed, iclass 17, count 2 2006.196.08:24:01.37#ibcon#about to write, iclass 17, count 2 2006.196.08:24:01.37#ibcon#wrote, iclass 17, count 2 2006.196.08:24:01.37#ibcon#about to read 3, iclass 17, count 2 2006.196.08:24:01.39#ibcon#read 3, iclass 17, count 2 2006.196.08:24:01.39#ibcon#about to read 4, iclass 17, count 2 2006.196.08:24:01.39#ibcon#read 4, iclass 17, count 2 2006.196.08:24:01.39#ibcon#about to read 5, iclass 17, count 2 2006.196.08:24:01.39#ibcon#read 5, iclass 17, count 2 2006.196.08:24:01.39#ibcon#about to read 6, iclass 17, count 2 2006.196.08:24:01.39#ibcon#read 6, iclass 17, count 2 2006.196.08:24:01.39#ibcon#end of sib2, iclass 17, count 2 2006.196.08:24:01.39#ibcon#*mode == 0, iclass 17, count 2 2006.196.08:24:01.39#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.196.08:24:01.39#ibcon#[27=AT03-04\r\n] 2006.196.08:24:01.39#ibcon#*before write, iclass 17, count 2 2006.196.08:24:01.39#ibcon#enter sib2, iclass 17, count 2 2006.196.08:24:01.39#ibcon#flushed, iclass 17, count 2 2006.196.08:24:01.39#ibcon#about to write, iclass 17, count 2 2006.196.08:24:01.39#ibcon#wrote, iclass 17, count 2 2006.196.08:24:01.39#ibcon#about to read 3, iclass 17, count 2 2006.196.08:24:01.42#ibcon#read 3, iclass 17, count 2 2006.196.08:24:01.42#ibcon#about to read 4, iclass 17, count 2 2006.196.08:24:01.42#ibcon#read 4, iclass 17, count 2 2006.196.08:24:01.42#ibcon#about to read 5, iclass 17, count 2 2006.196.08:24:01.42#ibcon#read 5, iclass 17, count 2 2006.196.08:24:01.42#ibcon#about to read 6, iclass 17, count 2 2006.196.08:24:01.42#ibcon#read 6, iclass 17, count 2 2006.196.08:24:01.42#ibcon#end of sib2, iclass 17, count 2 2006.196.08:24:01.42#ibcon#*after write, iclass 17, count 2 2006.196.08:24:01.42#ibcon#*before return 0, iclass 17, count 2 2006.196.08:24:01.42#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.196.08:24:01.42#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.196.08:24:01.42#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.196.08:24:01.42#ibcon#ireg 7 cls_cnt 0 2006.196.08:24:01.42#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.196.08:24:01.54#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.196.08:24:01.54#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.196.08:24:01.54#ibcon#enter wrdev, iclass 17, count 0 2006.196.08:24:01.54#ibcon#first serial, iclass 17, count 0 2006.196.08:24:01.54#ibcon#enter sib2, iclass 17, count 0 2006.196.08:24:01.54#ibcon#flushed, iclass 17, count 0 2006.196.08:24:01.54#ibcon#about to write, iclass 17, count 0 2006.196.08:24:01.54#ibcon#wrote, iclass 17, count 0 2006.196.08:24:01.54#ibcon#about to read 3, iclass 17, count 0 2006.196.08:24:01.56#ibcon#read 3, iclass 17, count 0 2006.196.08:24:01.56#ibcon#about to read 4, iclass 17, count 0 2006.196.08:24:01.56#ibcon#read 4, iclass 17, count 0 2006.196.08:24:01.56#ibcon#about to read 5, iclass 17, count 0 2006.196.08:24:01.56#ibcon#read 5, iclass 17, count 0 2006.196.08:24:01.56#ibcon#about to read 6, iclass 17, count 0 2006.196.08:24:01.56#ibcon#read 6, iclass 17, count 0 2006.196.08:24:01.56#ibcon#end of sib2, iclass 17, count 0 2006.196.08:24:01.56#ibcon#*mode == 0, iclass 17, count 0 2006.196.08:24:01.56#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.196.08:24:01.56#ibcon#[27=USB\r\n] 2006.196.08:24:01.56#ibcon#*before write, iclass 17, count 0 2006.196.08:24:01.56#ibcon#enter sib2, iclass 17, count 0 2006.196.08:24:01.56#ibcon#flushed, iclass 17, count 0 2006.196.08:24:01.56#ibcon#about to write, iclass 17, count 0 2006.196.08:24:01.56#ibcon#wrote, iclass 17, count 0 2006.196.08:24:01.56#ibcon#about to read 3, iclass 17, count 0 2006.196.08:24:01.59#ibcon#read 3, iclass 17, count 0 2006.196.08:24:01.59#ibcon#about to read 4, iclass 17, count 0 2006.196.08:24:01.59#ibcon#read 4, iclass 17, count 0 2006.196.08:24:01.59#ibcon#about to read 5, iclass 17, count 0 2006.196.08:24:01.59#ibcon#read 5, iclass 17, count 0 2006.196.08:24:01.59#ibcon#about to read 6, iclass 17, count 0 2006.196.08:24:01.59#ibcon#read 6, iclass 17, count 0 2006.196.08:24:01.59#ibcon#end of sib2, iclass 17, count 0 2006.196.08:24:01.59#ibcon#*after write, iclass 17, count 0 2006.196.08:24:01.59#ibcon#*before return 0, iclass 17, count 0 2006.196.08:24:01.59#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.196.08:24:01.59#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.196.08:24:01.59#ibcon#about to clear, iclass 17 cls_cnt 0 2006.196.08:24:01.59#ibcon#cleared, iclass 17 cls_cnt 0 2006.196.08:24:01.59$vc4f8/vblo=4,712.99 2006.196.08:24:01.59#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.196.08:24:01.59#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.196.08:24:01.59#ibcon#ireg 17 cls_cnt 0 2006.196.08:24:01.59#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.196.08:24:01.59#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.196.08:24:01.59#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.196.08:24:01.59#ibcon#enter wrdev, iclass 19, count 0 2006.196.08:24:01.59#ibcon#first serial, iclass 19, count 0 2006.196.08:24:01.59#ibcon#enter sib2, iclass 19, count 0 2006.196.08:24:01.59#ibcon#flushed, iclass 19, count 0 2006.196.08:24:01.59#ibcon#about to write, iclass 19, count 0 2006.196.08:24:01.59#ibcon#wrote, iclass 19, count 0 2006.196.08:24:01.59#ibcon#about to read 3, iclass 19, count 0 2006.196.08:24:01.61#ibcon#read 3, iclass 19, count 0 2006.196.08:24:01.61#ibcon#about to read 4, iclass 19, count 0 2006.196.08:24:01.61#ibcon#read 4, iclass 19, count 0 2006.196.08:24:01.61#ibcon#about to read 5, iclass 19, count 0 2006.196.08:24:01.61#ibcon#read 5, iclass 19, count 0 2006.196.08:24:01.61#ibcon#about to read 6, iclass 19, count 0 2006.196.08:24:01.61#ibcon#read 6, iclass 19, count 0 2006.196.08:24:01.61#ibcon#end of sib2, iclass 19, count 0 2006.196.08:24:01.61#ibcon#*mode == 0, iclass 19, count 0 2006.196.08:24:01.61#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.196.08:24:01.61#ibcon#[28=FRQ=04,712.99\r\n] 2006.196.08:24:01.61#ibcon#*before write, iclass 19, count 0 2006.196.08:24:01.61#ibcon#enter sib2, iclass 19, count 0 2006.196.08:24:01.61#ibcon#flushed, iclass 19, count 0 2006.196.08:24:01.61#ibcon#about to write, iclass 19, count 0 2006.196.08:24:01.61#ibcon#wrote, iclass 19, count 0 2006.196.08:24:01.61#ibcon#about to read 3, iclass 19, count 0 2006.196.08:24:01.65#ibcon#read 3, iclass 19, count 0 2006.196.08:24:01.65#ibcon#about to read 4, iclass 19, count 0 2006.196.08:24:01.65#ibcon#read 4, iclass 19, count 0 2006.196.08:24:01.65#ibcon#about to read 5, iclass 19, count 0 2006.196.08:24:01.65#ibcon#read 5, iclass 19, count 0 2006.196.08:24:01.65#ibcon#about to read 6, iclass 19, count 0 2006.196.08:24:01.65#ibcon#read 6, iclass 19, count 0 2006.196.08:24:01.65#ibcon#end of sib2, iclass 19, count 0 2006.196.08:24:01.65#ibcon#*after write, iclass 19, count 0 2006.196.08:24:01.65#ibcon#*before return 0, iclass 19, count 0 2006.196.08:24:01.65#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.196.08:24:01.65#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.196.08:24:01.65#ibcon#about to clear, iclass 19 cls_cnt 0 2006.196.08:24:01.65#ibcon#cleared, iclass 19 cls_cnt 0 2006.196.08:24:01.65$vc4f8/vb=4,4 2006.196.08:24:01.65#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.196.08:24:01.65#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.196.08:24:01.65#ibcon#ireg 11 cls_cnt 2 2006.196.08:24:01.65#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.196.08:24:01.71#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.196.08:24:01.71#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.196.08:24:01.71#ibcon#enter wrdev, iclass 21, count 2 2006.196.08:24:01.71#ibcon#first serial, iclass 21, count 2 2006.196.08:24:01.71#ibcon#enter sib2, iclass 21, count 2 2006.196.08:24:01.71#ibcon#flushed, iclass 21, count 2 2006.196.08:24:01.71#ibcon#about to write, iclass 21, count 2 2006.196.08:24:01.71#ibcon#wrote, iclass 21, count 2 2006.196.08:24:01.71#ibcon#about to read 3, iclass 21, count 2 2006.196.08:24:01.73#ibcon#read 3, iclass 21, count 2 2006.196.08:24:01.73#ibcon#about to read 4, iclass 21, count 2 2006.196.08:24:01.73#ibcon#read 4, iclass 21, count 2 2006.196.08:24:01.73#ibcon#about to read 5, iclass 21, count 2 2006.196.08:24:01.73#ibcon#read 5, iclass 21, count 2 2006.196.08:24:01.73#ibcon#about to read 6, iclass 21, count 2 2006.196.08:24:01.73#ibcon#read 6, iclass 21, count 2 2006.196.08:24:01.73#ibcon#end of sib2, iclass 21, count 2 2006.196.08:24:01.73#ibcon#*mode == 0, iclass 21, count 2 2006.196.08:24:01.73#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.196.08:24:01.73#ibcon#[27=AT04-04\r\n] 2006.196.08:24:01.73#ibcon#*before write, iclass 21, count 2 2006.196.08:24:01.73#ibcon#enter sib2, iclass 21, count 2 2006.196.08:24:01.73#ibcon#flushed, iclass 21, count 2 2006.196.08:24:01.73#ibcon#about to write, iclass 21, count 2 2006.196.08:24:01.73#ibcon#wrote, iclass 21, count 2 2006.196.08:24:01.73#ibcon#about to read 3, iclass 21, count 2 2006.196.08:24:01.76#ibcon#read 3, iclass 21, count 2 2006.196.08:24:01.76#ibcon#about to read 4, iclass 21, count 2 2006.196.08:24:01.76#ibcon#read 4, iclass 21, count 2 2006.196.08:24:01.76#ibcon#about to read 5, iclass 21, count 2 2006.196.08:24:01.76#ibcon#read 5, iclass 21, count 2 2006.196.08:24:01.76#ibcon#about to read 6, iclass 21, count 2 2006.196.08:24:01.76#ibcon#read 6, iclass 21, count 2 2006.196.08:24:01.76#ibcon#end of sib2, iclass 21, count 2 2006.196.08:24:01.76#ibcon#*after write, iclass 21, count 2 2006.196.08:24:01.76#ibcon#*before return 0, iclass 21, count 2 2006.196.08:24:01.76#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.196.08:24:01.76#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.196.08:24:01.76#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.196.08:24:01.76#ibcon#ireg 7 cls_cnt 0 2006.196.08:24:01.76#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.196.08:24:01.88#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.196.08:24:01.88#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.196.08:24:01.88#ibcon#enter wrdev, iclass 21, count 0 2006.196.08:24:01.88#ibcon#first serial, iclass 21, count 0 2006.196.08:24:01.88#ibcon#enter sib2, iclass 21, count 0 2006.196.08:24:01.88#ibcon#flushed, iclass 21, count 0 2006.196.08:24:01.88#ibcon#about to write, iclass 21, count 0 2006.196.08:24:01.88#ibcon#wrote, iclass 21, count 0 2006.196.08:24:01.88#ibcon#about to read 3, iclass 21, count 0 2006.196.08:24:01.90#ibcon#read 3, iclass 21, count 0 2006.196.08:24:01.90#ibcon#about to read 4, iclass 21, count 0 2006.196.08:24:01.90#ibcon#read 4, iclass 21, count 0 2006.196.08:24:01.90#ibcon#about to read 5, iclass 21, count 0 2006.196.08:24:01.90#ibcon#read 5, iclass 21, count 0 2006.196.08:24:01.90#ibcon#about to read 6, iclass 21, count 0 2006.196.08:24:01.90#ibcon#read 6, iclass 21, count 0 2006.196.08:24:01.90#ibcon#end of sib2, iclass 21, count 0 2006.196.08:24:01.90#ibcon#*mode == 0, iclass 21, count 0 2006.196.08:24:01.90#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.196.08:24:01.90#ibcon#[27=USB\r\n] 2006.196.08:24:01.90#ibcon#*before write, iclass 21, count 0 2006.196.08:24:01.90#ibcon#enter sib2, iclass 21, count 0 2006.196.08:24:01.90#ibcon#flushed, iclass 21, count 0 2006.196.08:24:01.90#ibcon#about to write, iclass 21, count 0 2006.196.08:24:01.90#ibcon#wrote, iclass 21, count 0 2006.196.08:24:01.90#ibcon#about to read 3, iclass 21, count 0 2006.196.08:24:01.93#ibcon#read 3, iclass 21, count 0 2006.196.08:24:01.93#ibcon#about to read 4, iclass 21, count 0 2006.196.08:24:01.93#ibcon#read 4, iclass 21, count 0 2006.196.08:24:01.93#ibcon#about to read 5, iclass 21, count 0 2006.196.08:24:01.93#ibcon#read 5, iclass 21, count 0 2006.196.08:24:01.93#ibcon#about to read 6, iclass 21, count 0 2006.196.08:24:01.93#ibcon#read 6, iclass 21, count 0 2006.196.08:24:01.93#ibcon#end of sib2, iclass 21, count 0 2006.196.08:24:01.93#ibcon#*after write, iclass 21, count 0 2006.196.08:24:01.93#ibcon#*before return 0, iclass 21, count 0 2006.196.08:24:01.93#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.196.08:24:01.93#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.196.08:24:01.93#ibcon#about to clear, iclass 21 cls_cnt 0 2006.196.08:24:01.93#ibcon#cleared, iclass 21 cls_cnt 0 2006.196.08:24:01.93$vc4f8/vblo=5,744.99 2006.196.08:24:01.93#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.196.08:24:01.93#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.196.08:24:01.93#ibcon#ireg 17 cls_cnt 0 2006.196.08:24:01.93#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.196.08:24:01.93#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.196.08:24:01.93#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.196.08:24:01.93#ibcon#enter wrdev, iclass 23, count 0 2006.196.08:24:01.93#ibcon#first serial, iclass 23, count 0 2006.196.08:24:01.93#ibcon#enter sib2, iclass 23, count 0 2006.196.08:24:01.93#ibcon#flushed, iclass 23, count 0 2006.196.08:24:01.93#ibcon#about to write, iclass 23, count 0 2006.196.08:24:01.93#ibcon#wrote, iclass 23, count 0 2006.196.08:24:01.93#ibcon#about to read 3, iclass 23, count 0 2006.196.08:24:01.95#ibcon#read 3, iclass 23, count 0 2006.196.08:24:01.95#ibcon#about to read 4, iclass 23, count 0 2006.196.08:24:01.95#ibcon#read 4, iclass 23, count 0 2006.196.08:24:01.95#ibcon#about to read 5, iclass 23, count 0 2006.196.08:24:01.95#ibcon#read 5, iclass 23, count 0 2006.196.08:24:01.95#ibcon#about to read 6, iclass 23, count 0 2006.196.08:24:01.95#ibcon#read 6, iclass 23, count 0 2006.196.08:24:01.95#ibcon#end of sib2, iclass 23, count 0 2006.196.08:24:01.95#ibcon#*mode == 0, iclass 23, count 0 2006.196.08:24:01.95#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.196.08:24:01.95#ibcon#[28=FRQ=05,744.99\r\n] 2006.196.08:24:01.95#ibcon#*before write, iclass 23, count 0 2006.196.08:24:01.95#ibcon#enter sib2, iclass 23, count 0 2006.196.08:24:01.95#ibcon#flushed, iclass 23, count 0 2006.196.08:24:01.95#ibcon#about to write, iclass 23, count 0 2006.196.08:24:01.95#ibcon#wrote, iclass 23, count 0 2006.196.08:24:01.95#ibcon#about to read 3, iclass 23, count 0 2006.196.08:24:01.99#ibcon#read 3, iclass 23, count 0 2006.196.08:24:01.99#ibcon#about to read 4, iclass 23, count 0 2006.196.08:24:01.99#ibcon#read 4, iclass 23, count 0 2006.196.08:24:01.99#ibcon#about to read 5, iclass 23, count 0 2006.196.08:24:01.99#ibcon#read 5, iclass 23, count 0 2006.196.08:24:01.99#ibcon#about to read 6, iclass 23, count 0 2006.196.08:24:01.99#ibcon#read 6, iclass 23, count 0 2006.196.08:24:01.99#ibcon#end of sib2, iclass 23, count 0 2006.196.08:24:01.99#ibcon#*after write, iclass 23, count 0 2006.196.08:24:01.99#ibcon#*before return 0, iclass 23, count 0 2006.196.08:24:01.99#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.196.08:24:01.99#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.196.08:24:01.99#ibcon#about to clear, iclass 23 cls_cnt 0 2006.196.08:24:01.99#ibcon#cleared, iclass 23 cls_cnt 0 2006.196.08:24:01.99$vc4f8/vb=5,4 2006.196.08:24:01.99#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.196.08:24:01.99#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.196.08:24:01.99#ibcon#ireg 11 cls_cnt 2 2006.196.08:24:01.99#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.196.08:24:02.05#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.196.08:24:02.05#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.196.08:24:02.05#ibcon#enter wrdev, iclass 25, count 2 2006.196.08:24:02.05#ibcon#first serial, iclass 25, count 2 2006.196.08:24:02.05#ibcon#enter sib2, iclass 25, count 2 2006.196.08:24:02.05#ibcon#flushed, iclass 25, count 2 2006.196.08:24:02.05#ibcon#about to write, iclass 25, count 2 2006.196.08:24:02.05#ibcon#wrote, iclass 25, count 2 2006.196.08:24:02.05#ibcon#about to read 3, iclass 25, count 2 2006.196.08:24:02.07#ibcon#read 3, iclass 25, count 2 2006.196.08:24:02.07#ibcon#about to read 4, iclass 25, count 2 2006.196.08:24:02.07#ibcon#read 4, iclass 25, count 2 2006.196.08:24:02.07#ibcon#about to read 5, iclass 25, count 2 2006.196.08:24:02.07#ibcon#read 5, iclass 25, count 2 2006.196.08:24:02.07#ibcon#about to read 6, iclass 25, count 2 2006.196.08:24:02.07#ibcon#read 6, iclass 25, count 2 2006.196.08:24:02.07#ibcon#end of sib2, iclass 25, count 2 2006.196.08:24:02.07#ibcon#*mode == 0, iclass 25, count 2 2006.196.08:24:02.07#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.196.08:24:02.07#ibcon#[27=AT05-04\r\n] 2006.196.08:24:02.07#ibcon#*before write, iclass 25, count 2 2006.196.08:24:02.07#ibcon#enter sib2, iclass 25, count 2 2006.196.08:24:02.07#ibcon#flushed, iclass 25, count 2 2006.196.08:24:02.07#ibcon#about to write, iclass 25, count 2 2006.196.08:24:02.07#ibcon#wrote, iclass 25, count 2 2006.196.08:24:02.07#ibcon#about to read 3, iclass 25, count 2 2006.196.08:24:02.10#ibcon#read 3, iclass 25, count 2 2006.196.08:24:02.10#ibcon#about to read 4, iclass 25, count 2 2006.196.08:24:02.10#ibcon#read 4, iclass 25, count 2 2006.196.08:24:02.10#ibcon#about to read 5, iclass 25, count 2 2006.196.08:24:02.10#ibcon#read 5, iclass 25, count 2 2006.196.08:24:02.10#ibcon#about to read 6, iclass 25, count 2 2006.196.08:24:02.10#ibcon#read 6, iclass 25, count 2 2006.196.08:24:02.10#ibcon#end of sib2, iclass 25, count 2 2006.196.08:24:02.10#ibcon#*after write, iclass 25, count 2 2006.196.08:24:02.10#ibcon#*before return 0, iclass 25, count 2 2006.196.08:24:02.10#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.196.08:24:02.10#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.196.08:24:02.10#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.196.08:24:02.10#ibcon#ireg 7 cls_cnt 0 2006.196.08:24:02.10#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.196.08:24:02.22#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.196.08:24:02.22#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.196.08:24:02.22#ibcon#enter wrdev, iclass 25, count 0 2006.196.08:24:02.22#ibcon#first serial, iclass 25, count 0 2006.196.08:24:02.22#ibcon#enter sib2, iclass 25, count 0 2006.196.08:24:02.22#ibcon#flushed, iclass 25, count 0 2006.196.08:24:02.22#ibcon#about to write, iclass 25, count 0 2006.196.08:24:02.22#ibcon#wrote, iclass 25, count 0 2006.196.08:24:02.22#ibcon#about to read 3, iclass 25, count 0 2006.196.08:24:02.24#ibcon#read 3, iclass 25, count 0 2006.196.08:24:02.24#ibcon#about to read 4, iclass 25, count 0 2006.196.08:24:02.24#ibcon#read 4, iclass 25, count 0 2006.196.08:24:02.24#ibcon#about to read 5, iclass 25, count 0 2006.196.08:24:02.24#ibcon#read 5, iclass 25, count 0 2006.196.08:24:02.24#ibcon#about to read 6, iclass 25, count 0 2006.196.08:24:02.24#ibcon#read 6, iclass 25, count 0 2006.196.08:24:02.24#ibcon#end of sib2, iclass 25, count 0 2006.196.08:24:02.24#ibcon#*mode == 0, iclass 25, count 0 2006.196.08:24:02.24#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.196.08:24:02.24#ibcon#[27=USB\r\n] 2006.196.08:24:02.24#ibcon#*before write, iclass 25, count 0 2006.196.08:24:02.24#ibcon#enter sib2, iclass 25, count 0 2006.196.08:24:02.24#ibcon#flushed, iclass 25, count 0 2006.196.08:24:02.24#ibcon#about to write, iclass 25, count 0 2006.196.08:24:02.24#ibcon#wrote, iclass 25, count 0 2006.196.08:24:02.24#ibcon#about to read 3, iclass 25, count 0 2006.196.08:24:02.27#ibcon#read 3, iclass 25, count 0 2006.196.08:24:02.27#ibcon#about to read 4, iclass 25, count 0 2006.196.08:24:02.27#ibcon#read 4, iclass 25, count 0 2006.196.08:24:02.27#ibcon#about to read 5, iclass 25, count 0 2006.196.08:24:02.27#ibcon#read 5, iclass 25, count 0 2006.196.08:24:02.27#ibcon#about to read 6, iclass 25, count 0 2006.196.08:24:02.27#ibcon#read 6, iclass 25, count 0 2006.196.08:24:02.27#ibcon#end of sib2, iclass 25, count 0 2006.196.08:24:02.27#ibcon#*after write, iclass 25, count 0 2006.196.08:24:02.27#ibcon#*before return 0, iclass 25, count 0 2006.196.08:24:02.27#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.196.08:24:02.27#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.196.08:24:02.27#ibcon#about to clear, iclass 25 cls_cnt 0 2006.196.08:24:02.27#ibcon#cleared, iclass 25 cls_cnt 0 2006.196.08:24:02.27$vc4f8/vblo=6,752.99 2006.196.08:24:02.27#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.196.08:24:02.27#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.196.08:24:02.27#ibcon#ireg 17 cls_cnt 0 2006.196.08:24:02.27#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.196.08:24:02.27#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.196.08:24:02.27#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.196.08:24:02.27#ibcon#enter wrdev, iclass 27, count 0 2006.196.08:24:02.27#ibcon#first serial, iclass 27, count 0 2006.196.08:24:02.27#ibcon#enter sib2, iclass 27, count 0 2006.196.08:24:02.27#ibcon#flushed, iclass 27, count 0 2006.196.08:24:02.27#ibcon#about to write, iclass 27, count 0 2006.196.08:24:02.27#ibcon#wrote, iclass 27, count 0 2006.196.08:24:02.27#ibcon#about to read 3, iclass 27, count 0 2006.196.08:24:02.29#ibcon#read 3, iclass 27, count 0 2006.196.08:24:02.29#ibcon#about to read 4, iclass 27, count 0 2006.196.08:24:02.29#ibcon#read 4, iclass 27, count 0 2006.196.08:24:02.29#ibcon#about to read 5, iclass 27, count 0 2006.196.08:24:02.29#ibcon#read 5, iclass 27, count 0 2006.196.08:24:02.29#ibcon#about to read 6, iclass 27, count 0 2006.196.08:24:02.29#ibcon#read 6, iclass 27, count 0 2006.196.08:24:02.29#ibcon#end of sib2, iclass 27, count 0 2006.196.08:24:02.29#ibcon#*mode == 0, iclass 27, count 0 2006.196.08:24:02.29#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.196.08:24:02.29#ibcon#[28=FRQ=06,752.99\r\n] 2006.196.08:24:02.29#ibcon#*before write, iclass 27, count 0 2006.196.08:24:02.29#ibcon#enter sib2, iclass 27, count 0 2006.196.08:24:02.29#ibcon#flushed, iclass 27, count 0 2006.196.08:24:02.29#ibcon#about to write, iclass 27, count 0 2006.196.08:24:02.29#ibcon#wrote, iclass 27, count 0 2006.196.08:24:02.29#ibcon#about to read 3, iclass 27, count 0 2006.196.08:24:02.34#ibcon#read 3, iclass 27, count 0 2006.196.08:24:02.34#ibcon#about to read 4, iclass 27, count 0 2006.196.08:24:02.34#ibcon#read 4, iclass 27, count 0 2006.196.08:24:02.34#ibcon#about to read 5, iclass 27, count 0 2006.196.08:24:02.34#ibcon#read 5, iclass 27, count 0 2006.196.08:24:02.34#ibcon#about to read 6, iclass 27, count 0 2006.196.08:24:02.34#ibcon#read 6, iclass 27, count 0 2006.196.08:24:02.34#ibcon#end of sib2, iclass 27, count 0 2006.196.08:24:02.34#ibcon#*after write, iclass 27, count 0 2006.196.08:24:02.34#ibcon#*before return 0, iclass 27, count 0 2006.196.08:24:02.34#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.196.08:24:02.34#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.196.08:24:02.34#ibcon#about to clear, iclass 27 cls_cnt 0 2006.196.08:24:02.34#ibcon#cleared, iclass 27 cls_cnt 0 2006.196.08:24:02.34$vc4f8/vb=6,4 2006.196.08:24:02.34#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.196.08:24:02.34#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.196.08:24:02.34#ibcon#ireg 11 cls_cnt 2 2006.196.08:24:02.34#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.196.08:24:02.39#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.196.08:24:02.39#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.196.08:24:02.39#ibcon#enter wrdev, iclass 29, count 2 2006.196.08:24:02.39#ibcon#first serial, iclass 29, count 2 2006.196.08:24:02.39#ibcon#enter sib2, iclass 29, count 2 2006.196.08:24:02.39#ibcon#flushed, iclass 29, count 2 2006.196.08:24:02.39#ibcon#about to write, iclass 29, count 2 2006.196.08:24:02.39#ibcon#wrote, iclass 29, count 2 2006.196.08:24:02.39#ibcon#about to read 3, iclass 29, count 2 2006.196.08:24:02.41#ibcon#read 3, iclass 29, count 2 2006.196.08:24:02.41#ibcon#about to read 4, iclass 29, count 2 2006.196.08:24:02.41#ibcon#read 4, iclass 29, count 2 2006.196.08:24:02.41#ibcon#about to read 5, iclass 29, count 2 2006.196.08:24:02.41#ibcon#read 5, iclass 29, count 2 2006.196.08:24:02.41#ibcon#about to read 6, iclass 29, count 2 2006.196.08:24:02.41#ibcon#read 6, iclass 29, count 2 2006.196.08:24:02.41#ibcon#end of sib2, iclass 29, count 2 2006.196.08:24:02.41#ibcon#*mode == 0, iclass 29, count 2 2006.196.08:24:02.41#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.196.08:24:02.41#ibcon#[27=AT06-04\r\n] 2006.196.08:24:02.41#ibcon#*before write, iclass 29, count 2 2006.196.08:24:02.41#ibcon#enter sib2, iclass 29, count 2 2006.196.08:24:02.41#ibcon#flushed, iclass 29, count 2 2006.196.08:24:02.41#ibcon#about to write, iclass 29, count 2 2006.196.08:24:02.41#ibcon#wrote, iclass 29, count 2 2006.196.08:24:02.41#ibcon#about to read 3, iclass 29, count 2 2006.196.08:24:02.44#ibcon#read 3, iclass 29, count 2 2006.196.08:24:02.44#ibcon#about to read 4, iclass 29, count 2 2006.196.08:24:02.44#ibcon#read 4, iclass 29, count 2 2006.196.08:24:02.44#ibcon#about to read 5, iclass 29, count 2 2006.196.08:24:02.44#ibcon#read 5, iclass 29, count 2 2006.196.08:24:02.44#ibcon#about to read 6, iclass 29, count 2 2006.196.08:24:02.44#ibcon#read 6, iclass 29, count 2 2006.196.08:24:02.44#ibcon#end of sib2, iclass 29, count 2 2006.196.08:24:02.44#ibcon#*after write, iclass 29, count 2 2006.196.08:24:02.44#ibcon#*before return 0, iclass 29, count 2 2006.196.08:24:02.44#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.196.08:24:02.44#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.196.08:24:02.44#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.196.08:24:02.44#ibcon#ireg 7 cls_cnt 0 2006.196.08:24:02.44#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.196.08:24:02.56#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.196.08:24:02.56#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.196.08:24:02.56#ibcon#enter wrdev, iclass 29, count 0 2006.196.08:24:02.56#ibcon#first serial, iclass 29, count 0 2006.196.08:24:02.56#ibcon#enter sib2, iclass 29, count 0 2006.196.08:24:02.56#ibcon#flushed, iclass 29, count 0 2006.196.08:24:02.56#ibcon#about to write, iclass 29, count 0 2006.196.08:24:02.56#ibcon#wrote, iclass 29, count 0 2006.196.08:24:02.56#ibcon#about to read 3, iclass 29, count 0 2006.196.08:24:02.58#ibcon#read 3, iclass 29, count 0 2006.196.08:24:02.58#ibcon#about to read 4, iclass 29, count 0 2006.196.08:24:02.58#ibcon#read 4, iclass 29, count 0 2006.196.08:24:02.58#ibcon#about to read 5, iclass 29, count 0 2006.196.08:24:02.58#ibcon#read 5, iclass 29, count 0 2006.196.08:24:02.58#ibcon#about to read 6, iclass 29, count 0 2006.196.08:24:02.58#ibcon#read 6, iclass 29, count 0 2006.196.08:24:02.58#ibcon#end of sib2, iclass 29, count 0 2006.196.08:24:02.58#ibcon#*mode == 0, iclass 29, count 0 2006.196.08:24:02.58#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.196.08:24:02.58#ibcon#[27=USB\r\n] 2006.196.08:24:02.58#ibcon#*before write, iclass 29, count 0 2006.196.08:24:02.58#ibcon#enter sib2, iclass 29, count 0 2006.196.08:24:02.58#ibcon#flushed, iclass 29, count 0 2006.196.08:24:02.58#ibcon#about to write, iclass 29, count 0 2006.196.08:24:02.58#ibcon#wrote, iclass 29, count 0 2006.196.08:24:02.58#ibcon#about to read 3, iclass 29, count 0 2006.196.08:24:02.61#ibcon#read 3, iclass 29, count 0 2006.196.08:24:02.61#ibcon#about to read 4, iclass 29, count 0 2006.196.08:24:02.61#ibcon#read 4, iclass 29, count 0 2006.196.08:24:02.61#ibcon#about to read 5, iclass 29, count 0 2006.196.08:24:02.61#ibcon#read 5, iclass 29, count 0 2006.196.08:24:02.61#ibcon#about to read 6, iclass 29, count 0 2006.196.08:24:02.61#ibcon#read 6, iclass 29, count 0 2006.196.08:24:02.61#ibcon#end of sib2, iclass 29, count 0 2006.196.08:24:02.61#ibcon#*after write, iclass 29, count 0 2006.196.08:24:02.61#ibcon#*before return 0, iclass 29, count 0 2006.196.08:24:02.61#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.196.08:24:02.61#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.196.08:24:02.61#ibcon#about to clear, iclass 29 cls_cnt 0 2006.196.08:24:02.61#ibcon#cleared, iclass 29 cls_cnt 0 2006.196.08:24:02.61$vc4f8/vabw=wide 2006.196.08:24:02.61#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.196.08:24:02.61#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.196.08:24:02.61#ibcon#ireg 8 cls_cnt 0 2006.196.08:24:02.61#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.196.08:24:02.61#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.196.08:24:02.61#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.196.08:24:02.61#ibcon#enter wrdev, iclass 31, count 0 2006.196.08:24:02.61#ibcon#first serial, iclass 31, count 0 2006.196.08:24:02.61#ibcon#enter sib2, iclass 31, count 0 2006.196.08:24:02.61#ibcon#flushed, iclass 31, count 0 2006.196.08:24:02.61#ibcon#about to write, iclass 31, count 0 2006.196.08:24:02.61#ibcon#wrote, iclass 31, count 0 2006.196.08:24:02.61#ibcon#about to read 3, iclass 31, count 0 2006.196.08:24:02.63#ibcon#read 3, iclass 31, count 0 2006.196.08:24:02.63#ibcon#about to read 4, iclass 31, count 0 2006.196.08:24:02.63#ibcon#read 4, iclass 31, count 0 2006.196.08:24:02.63#ibcon#about to read 5, iclass 31, count 0 2006.196.08:24:02.63#ibcon#read 5, iclass 31, count 0 2006.196.08:24:02.63#ibcon#about to read 6, iclass 31, count 0 2006.196.08:24:02.63#ibcon#read 6, iclass 31, count 0 2006.196.08:24:02.63#ibcon#end of sib2, iclass 31, count 0 2006.196.08:24:02.63#ibcon#*mode == 0, iclass 31, count 0 2006.196.08:24:02.63#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.196.08:24:02.63#ibcon#[25=BW32\r\n] 2006.196.08:24:02.63#ibcon#*before write, iclass 31, count 0 2006.196.08:24:02.63#ibcon#enter sib2, iclass 31, count 0 2006.196.08:24:02.63#ibcon#flushed, iclass 31, count 0 2006.196.08:24:02.63#ibcon#about to write, iclass 31, count 0 2006.196.08:24:02.63#ibcon#wrote, iclass 31, count 0 2006.196.08:24:02.63#ibcon#about to read 3, iclass 31, count 0 2006.196.08:24:02.66#ibcon#read 3, iclass 31, count 0 2006.196.08:24:02.66#ibcon#about to read 4, iclass 31, count 0 2006.196.08:24:02.66#ibcon#read 4, iclass 31, count 0 2006.196.08:24:02.66#ibcon#about to read 5, iclass 31, count 0 2006.196.08:24:02.66#ibcon#read 5, iclass 31, count 0 2006.196.08:24:02.66#ibcon#about to read 6, iclass 31, count 0 2006.196.08:24:02.66#ibcon#read 6, iclass 31, count 0 2006.196.08:24:02.66#ibcon#end of sib2, iclass 31, count 0 2006.196.08:24:02.66#ibcon#*after write, iclass 31, count 0 2006.196.08:24:02.66#ibcon#*before return 0, iclass 31, count 0 2006.196.08:24:02.66#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.196.08:24:02.66#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.196.08:24:02.66#ibcon#about to clear, iclass 31 cls_cnt 0 2006.196.08:24:02.66#ibcon#cleared, iclass 31 cls_cnt 0 2006.196.08:24:02.66$vc4f8/vbbw=wide 2006.196.08:24:02.66#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.196.08:24:02.66#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.196.08:24:02.66#ibcon#ireg 8 cls_cnt 0 2006.196.08:24:02.66#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:24:02.73#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:24:02.73#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:24:02.73#ibcon#enter wrdev, iclass 33, count 0 2006.196.08:24:02.73#ibcon#first serial, iclass 33, count 0 2006.196.08:24:02.73#ibcon#enter sib2, iclass 33, count 0 2006.196.08:24:02.73#ibcon#flushed, iclass 33, count 0 2006.196.08:24:02.73#ibcon#about to write, iclass 33, count 0 2006.196.08:24:02.73#ibcon#wrote, iclass 33, count 0 2006.196.08:24:02.73#ibcon#about to read 3, iclass 33, count 0 2006.196.08:24:02.75#ibcon#read 3, iclass 33, count 0 2006.196.08:24:02.75#ibcon#about to read 4, iclass 33, count 0 2006.196.08:24:02.75#ibcon#read 4, iclass 33, count 0 2006.196.08:24:02.75#ibcon#about to read 5, iclass 33, count 0 2006.196.08:24:02.75#ibcon#read 5, iclass 33, count 0 2006.196.08:24:02.75#ibcon#about to read 6, iclass 33, count 0 2006.196.08:24:02.75#ibcon#read 6, iclass 33, count 0 2006.196.08:24:02.75#ibcon#end of sib2, iclass 33, count 0 2006.196.08:24:02.75#ibcon#*mode == 0, iclass 33, count 0 2006.196.08:24:02.75#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.196.08:24:02.75#ibcon#[27=BW32\r\n] 2006.196.08:24:02.75#ibcon#*before write, iclass 33, count 0 2006.196.08:24:02.75#ibcon#enter sib2, iclass 33, count 0 2006.196.08:24:02.75#ibcon#flushed, iclass 33, count 0 2006.196.08:24:02.75#ibcon#about to write, iclass 33, count 0 2006.196.08:24:02.75#ibcon#wrote, iclass 33, count 0 2006.196.08:24:02.75#ibcon#about to read 3, iclass 33, count 0 2006.196.08:24:02.78#ibcon#read 3, iclass 33, count 0 2006.196.08:24:02.78#ibcon#about to read 4, iclass 33, count 0 2006.196.08:24:02.78#ibcon#read 4, iclass 33, count 0 2006.196.08:24:02.78#ibcon#about to read 5, iclass 33, count 0 2006.196.08:24:02.78#ibcon#read 5, iclass 33, count 0 2006.196.08:24:02.78#ibcon#about to read 6, iclass 33, count 0 2006.196.08:24:02.78#ibcon#read 6, iclass 33, count 0 2006.196.08:24:02.78#ibcon#end of sib2, iclass 33, count 0 2006.196.08:24:02.78#ibcon#*after write, iclass 33, count 0 2006.196.08:24:02.78#ibcon#*before return 0, iclass 33, count 0 2006.196.08:24:02.78#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:24:02.78#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:24:02.78#ibcon#about to clear, iclass 33 cls_cnt 0 2006.196.08:24:02.78#ibcon#cleared, iclass 33 cls_cnt 0 2006.196.08:24:02.78$4f8m12a/ifd4f 2006.196.08:24:02.78$ifd4f/lo= 2006.196.08:24:02.78$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.196.08:24:02.78$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.196.08:24:02.78$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.196.08:24:02.78$ifd4f/patch= 2006.196.08:24:02.78$ifd4f/patch=lo1,a1,a2,a3,a4 2006.196.08:24:02.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.196.08:24:02.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.196.08:24:02.78$4f8m12a/"form=m,16.000,1:2 2006.196.08:24:02.78$4f8m12a/"tpicd 2006.196.08:24:02.78$4f8m12a/echo=off 2006.196.08:24:02.78$4f8m12a/xlog=off 2006.196.08:24:02.78:!2006.196.08:26:10 2006.196.08:24:07.13#trakl#Source acquired 2006.196.08:24:09.13#flagr#flagr/antenna,acquired 2006.196.08:26:10.00:preob 2006.196.08:26:10.14/onsource/TRACKING 2006.196.08:26:10.14:!2006.196.08:26:20 2006.196.08:26:20.00:data_valid=on 2006.196.08:26:20.00:midob 2006.196.08:26:21.14/onsource/TRACKING 2006.196.08:26:21.14/wx/28.80,1004.2,93 2006.196.08:26:21.26/cable/+6.3383E-03 2006.196.08:26:22.35/va/01,08,usb,yes,29,31 2006.196.08:26:22.35/va/02,07,usb,yes,30,31 2006.196.08:26:22.35/va/03,06,usb,yes,31,31 2006.196.08:26:22.35/va/04,07,usb,yes,30,33 2006.196.08:26:22.35/va/05,07,usb,yes,33,35 2006.196.08:26:22.35/va/06,06,usb,yes,32,32 2006.196.08:26:22.35/va/07,06,usb,yes,33,32 2006.196.08:26:22.35/va/08,07,usb,yes,31,30 2006.196.08:26:22.58/valo/01,532.99,yes,locked 2006.196.08:26:22.58/valo/02,572.99,yes,locked 2006.196.08:26:22.58/valo/03,672.99,yes,locked 2006.196.08:26:22.58/valo/04,832.99,yes,locked 2006.196.08:26:22.58/valo/05,652.99,yes,locked 2006.196.08:26:22.58/valo/06,772.99,yes,locked 2006.196.08:26:22.58/valo/07,832.99,yes,locked 2006.196.08:26:22.58/valo/08,852.99,yes,locked 2006.196.08:26:23.67/vb/01,04,usb,yes,29,27 2006.196.08:26:23.67/vb/02,04,usb,yes,30,32 2006.196.08:26:23.67/vb/03,04,usb,yes,27,31 2006.196.08:26:23.67/vb/04,04,usb,yes,28,28 2006.196.08:26:23.67/vb/05,04,usb,yes,26,30 2006.196.08:26:23.67/vb/06,04,usb,yes,27,30 2006.196.08:26:23.67/vb/07,04,usb,yes,29,29 2006.196.08:26:23.67/vb/08,04,usb,yes,27,30 2006.196.08:26:23.91/vblo/01,632.99,yes,locked 2006.196.08:26:23.91/vblo/02,640.99,yes,locked 2006.196.08:26:23.91/vblo/03,656.99,yes,locked 2006.196.08:26:23.91/vblo/04,712.99,yes,locked 2006.196.08:26:23.91/vblo/05,744.99,yes,locked 2006.196.08:26:23.91/vblo/06,752.99,yes,locked 2006.196.08:26:23.91/vblo/07,734.99,yes,locked 2006.196.08:26:23.91/vblo/08,744.99,yes,locked 2006.196.08:26:24.06/vabw/8 2006.196.08:26:24.21/vbbw/8 2006.196.08:26:24.30/xfe/off,on,15.0 2006.196.08:26:24.69/ifatt/23,28,28,28 2006.196.08:26:25.07/fmout-gps/S +3.33E-07 2006.196.08:26:25.14:!2006.196.08:27:20 2006.196.08:27:20.00:data_valid=off 2006.196.08:27:20.00:postob 2006.196.08:27:20.08/cable/+6.3389E-03 2006.196.08:27:20.08/wx/28.78,1004.3,93 2006.196.08:27:21.07/fmout-gps/S +3.33E-07 2006.196.08:27:21.07:scan_name=196-0828,k06196,60 2006.196.08:27:21.07:source=3c418,203837.03,511912.7,2000.0,cw 2006.196.08:27:21.14#flagr#flagr/antenna,new-source 2006.196.08:27:22.14:checkk5 2006.196.08:27:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.196.08:27:22.89/chk_autoobs//k5ts2/ autoobs is running! 2006.196.08:27:23.27/chk_autoobs//k5ts3/ autoobs is running! 2006.196.08:27:23.64/chk_autoobs//k5ts4/ autoobs is running! 2006.196.08:27:24.02/chk_obsdata//k5ts1/T1960826??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.08:27:24.40/chk_obsdata//k5ts2/T1960826??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.08:27:24.77/chk_obsdata//k5ts3/T1960826??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.08:27:25.14/chk_obsdata//k5ts4/T1960826??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.08:27:25.82/k5log//k5ts1_log_newline 2006.196.08:27:26.52/k5log//k5ts2_log_newline 2006.196.08:27:27.21/k5log//k5ts3_log_newline 2006.196.08:27:27.90/k5log//k5ts4_log_newline 2006.196.08:27:27.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.196.08:27:27.92:4f8m12a=3 2006.196.08:27:27.92$4f8m12a/echo=on 2006.196.08:27:27.92$4f8m12a/pcalon 2006.196.08:27:27.92$pcalon/"no phase cal control is implemented here 2006.196.08:27:27.92$4f8m12a/"tpicd=stop 2006.196.08:27:27.92$4f8m12a/vc4f8 2006.196.08:27:27.92$vc4f8/valo=1,532.99 2006.196.08:27:27.93#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.196.08:27:27.93#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.196.08:27:27.93#ibcon#ireg 17 cls_cnt 0 2006.196.08:27:27.93#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.196.08:27:27.93#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.196.08:27:27.93#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.196.08:27:27.93#ibcon#enter wrdev, iclass 6, count 0 2006.196.08:27:27.93#ibcon#first serial, iclass 6, count 0 2006.196.08:27:27.93#ibcon#enter sib2, iclass 6, count 0 2006.196.08:27:27.93#ibcon#flushed, iclass 6, count 0 2006.196.08:27:27.93#ibcon#about to write, iclass 6, count 0 2006.196.08:27:27.93#ibcon#wrote, iclass 6, count 0 2006.196.08:27:27.93#ibcon#about to read 3, iclass 6, count 0 2006.196.08:27:27.97#ibcon#read 3, iclass 6, count 0 2006.196.08:27:27.97#ibcon#about to read 4, iclass 6, count 0 2006.196.08:27:27.97#ibcon#read 4, iclass 6, count 0 2006.196.08:27:27.97#ibcon#about to read 5, iclass 6, count 0 2006.196.08:27:27.97#ibcon#read 5, iclass 6, count 0 2006.196.08:27:27.97#ibcon#about to read 6, iclass 6, count 0 2006.196.08:27:27.97#ibcon#read 6, iclass 6, count 0 2006.196.08:27:27.97#ibcon#end of sib2, iclass 6, count 0 2006.196.08:27:27.97#ibcon#*mode == 0, iclass 6, count 0 2006.196.08:27:27.97#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.196.08:27:27.97#ibcon#[26=FRQ=01,532.99\r\n] 2006.196.08:27:27.97#ibcon#*before write, iclass 6, count 0 2006.196.08:27:27.97#ibcon#enter sib2, iclass 6, count 0 2006.196.08:27:27.97#ibcon#flushed, iclass 6, count 0 2006.196.08:27:27.97#ibcon#about to write, iclass 6, count 0 2006.196.08:27:27.97#ibcon#wrote, iclass 6, count 0 2006.196.08:27:27.97#ibcon#about to read 3, iclass 6, count 0 2006.196.08:27:28.02#ibcon#read 3, iclass 6, count 0 2006.196.08:27:28.02#ibcon#about to read 4, iclass 6, count 0 2006.196.08:27:28.02#ibcon#read 4, iclass 6, count 0 2006.196.08:27:28.02#ibcon#about to read 5, iclass 6, count 0 2006.196.08:27:28.02#ibcon#read 5, iclass 6, count 0 2006.196.08:27:28.02#ibcon#about to read 6, iclass 6, count 0 2006.196.08:27:28.02#ibcon#read 6, iclass 6, count 0 2006.196.08:27:28.02#ibcon#end of sib2, iclass 6, count 0 2006.196.08:27:28.02#ibcon#*after write, iclass 6, count 0 2006.196.08:27:28.02#ibcon#*before return 0, iclass 6, count 0 2006.196.08:27:28.02#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.196.08:27:28.02#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.196.08:27:28.02#ibcon#about to clear, iclass 6 cls_cnt 0 2006.196.08:27:28.02#ibcon#cleared, iclass 6 cls_cnt 0 2006.196.08:27:28.02$vc4f8/va=1,8 2006.196.08:27:28.02#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.196.08:27:28.02#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.196.08:27:28.02#ibcon#ireg 11 cls_cnt 2 2006.196.08:27:28.02#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.196.08:27:28.02#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.196.08:27:28.02#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.196.08:27:28.02#ibcon#enter wrdev, iclass 10, count 2 2006.196.08:27:28.02#ibcon#first serial, iclass 10, count 2 2006.196.08:27:28.02#ibcon#enter sib2, iclass 10, count 2 2006.196.08:27:28.02#ibcon#flushed, iclass 10, count 2 2006.196.08:27:28.02#ibcon#about to write, iclass 10, count 2 2006.196.08:27:28.02#ibcon#wrote, iclass 10, count 2 2006.196.08:27:28.02#ibcon#about to read 3, iclass 10, count 2 2006.196.08:27:28.04#ibcon#read 3, iclass 10, count 2 2006.196.08:27:28.04#ibcon#about to read 4, iclass 10, count 2 2006.196.08:27:28.04#ibcon#read 4, iclass 10, count 2 2006.196.08:27:28.04#ibcon#about to read 5, iclass 10, count 2 2006.196.08:27:28.04#ibcon#read 5, iclass 10, count 2 2006.196.08:27:28.04#ibcon#about to read 6, iclass 10, count 2 2006.196.08:27:28.04#ibcon#read 6, iclass 10, count 2 2006.196.08:27:28.04#ibcon#end of sib2, iclass 10, count 2 2006.196.08:27:28.04#ibcon#*mode == 0, iclass 10, count 2 2006.196.08:27:28.04#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.196.08:27:28.04#ibcon#[25=AT01-08\r\n] 2006.196.08:27:28.04#ibcon#*before write, iclass 10, count 2 2006.196.08:27:28.04#ibcon#enter sib2, iclass 10, count 2 2006.196.08:27:28.04#ibcon#flushed, iclass 10, count 2 2006.196.08:27:28.04#ibcon#about to write, iclass 10, count 2 2006.196.08:27:28.04#ibcon#wrote, iclass 10, count 2 2006.196.08:27:28.04#ibcon#about to read 3, iclass 10, count 2 2006.196.08:27:28.08#ibcon#read 3, iclass 10, count 2 2006.196.08:27:28.08#ibcon#about to read 4, iclass 10, count 2 2006.196.08:27:28.08#ibcon#read 4, iclass 10, count 2 2006.196.08:27:28.08#ibcon#about to read 5, iclass 10, count 2 2006.196.08:27:28.08#ibcon#read 5, iclass 10, count 2 2006.196.08:27:28.08#ibcon#about to read 6, iclass 10, count 2 2006.196.08:27:28.08#ibcon#read 6, iclass 10, count 2 2006.196.08:27:28.08#ibcon#end of sib2, iclass 10, count 2 2006.196.08:27:28.08#ibcon#*after write, iclass 10, count 2 2006.196.08:27:28.08#ibcon#*before return 0, iclass 10, count 2 2006.196.08:27:28.08#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.196.08:27:28.08#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.196.08:27:28.08#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.196.08:27:28.08#ibcon#ireg 7 cls_cnt 0 2006.196.08:27:28.08#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.196.08:27:28.20#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.196.08:27:28.20#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.196.08:27:28.20#ibcon#enter wrdev, iclass 10, count 0 2006.196.08:27:28.20#ibcon#first serial, iclass 10, count 0 2006.196.08:27:28.20#ibcon#enter sib2, iclass 10, count 0 2006.196.08:27:28.20#ibcon#flushed, iclass 10, count 0 2006.196.08:27:28.20#ibcon#about to write, iclass 10, count 0 2006.196.08:27:28.20#ibcon#wrote, iclass 10, count 0 2006.196.08:27:28.20#ibcon#about to read 3, iclass 10, count 0 2006.196.08:27:28.23#ibcon#read 3, iclass 10, count 0 2006.196.08:27:28.23#ibcon#about to read 4, iclass 10, count 0 2006.196.08:27:28.23#ibcon#read 4, iclass 10, count 0 2006.196.08:27:28.23#ibcon#about to read 5, iclass 10, count 0 2006.196.08:27:28.23#ibcon#read 5, iclass 10, count 0 2006.196.08:27:28.23#ibcon#about to read 6, iclass 10, count 0 2006.196.08:27:28.23#ibcon#read 6, iclass 10, count 0 2006.196.08:27:28.23#ibcon#end of sib2, iclass 10, count 0 2006.196.08:27:28.23#ibcon#*mode == 0, iclass 10, count 0 2006.196.08:27:28.23#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.196.08:27:28.23#ibcon#[25=USB\r\n] 2006.196.08:27:28.23#ibcon#*before write, iclass 10, count 0 2006.196.08:27:28.23#ibcon#enter sib2, iclass 10, count 0 2006.196.08:27:28.23#ibcon#flushed, iclass 10, count 0 2006.196.08:27:28.23#ibcon#about to write, iclass 10, count 0 2006.196.08:27:28.23#ibcon#wrote, iclass 10, count 0 2006.196.08:27:28.23#ibcon#about to read 3, iclass 10, count 0 2006.196.08:27:28.26#ibcon#read 3, iclass 10, count 0 2006.196.08:27:28.26#ibcon#about to read 4, iclass 10, count 0 2006.196.08:27:28.26#ibcon#read 4, iclass 10, count 0 2006.196.08:27:28.26#ibcon#about to read 5, iclass 10, count 0 2006.196.08:27:28.26#ibcon#read 5, iclass 10, count 0 2006.196.08:27:28.26#ibcon#about to read 6, iclass 10, count 0 2006.196.08:27:28.26#ibcon#read 6, iclass 10, count 0 2006.196.08:27:28.26#ibcon#end of sib2, iclass 10, count 0 2006.196.08:27:28.26#ibcon#*after write, iclass 10, count 0 2006.196.08:27:28.26#ibcon#*before return 0, iclass 10, count 0 2006.196.08:27:28.26#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.196.08:27:28.26#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.196.08:27:28.26#ibcon#about to clear, iclass 10 cls_cnt 0 2006.196.08:27:28.26#ibcon#cleared, iclass 10 cls_cnt 0 2006.196.08:27:28.26$vc4f8/valo=2,572.99 2006.196.08:27:28.26#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.196.08:27:28.26#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.196.08:27:28.26#ibcon#ireg 17 cls_cnt 0 2006.196.08:27:28.26#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.196.08:27:28.26#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.196.08:27:28.26#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.196.08:27:28.26#ibcon#enter wrdev, iclass 12, count 0 2006.196.08:27:28.26#ibcon#first serial, iclass 12, count 0 2006.196.08:27:28.26#ibcon#enter sib2, iclass 12, count 0 2006.196.08:27:28.26#ibcon#flushed, iclass 12, count 0 2006.196.08:27:28.26#ibcon#about to write, iclass 12, count 0 2006.196.08:27:28.26#ibcon#wrote, iclass 12, count 0 2006.196.08:27:28.26#ibcon#about to read 3, iclass 12, count 0 2006.196.08:27:28.28#ibcon#read 3, iclass 12, count 0 2006.196.08:27:28.28#ibcon#about to read 4, iclass 12, count 0 2006.196.08:27:28.28#ibcon#read 4, iclass 12, count 0 2006.196.08:27:28.28#ibcon#about to read 5, iclass 12, count 0 2006.196.08:27:28.28#ibcon#read 5, iclass 12, count 0 2006.196.08:27:28.28#ibcon#about to read 6, iclass 12, count 0 2006.196.08:27:28.28#ibcon#read 6, iclass 12, count 0 2006.196.08:27:28.28#ibcon#end of sib2, iclass 12, count 0 2006.196.08:27:28.28#ibcon#*mode == 0, iclass 12, count 0 2006.196.08:27:28.28#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.196.08:27:28.28#ibcon#[26=FRQ=02,572.99\r\n] 2006.196.08:27:28.28#ibcon#*before write, iclass 12, count 0 2006.196.08:27:28.28#ibcon#enter sib2, iclass 12, count 0 2006.196.08:27:28.28#ibcon#flushed, iclass 12, count 0 2006.196.08:27:28.28#ibcon#about to write, iclass 12, count 0 2006.196.08:27:28.28#ibcon#wrote, iclass 12, count 0 2006.196.08:27:28.28#ibcon#about to read 3, iclass 12, count 0 2006.196.08:27:28.32#ibcon#read 3, iclass 12, count 0 2006.196.08:27:28.32#ibcon#about to read 4, iclass 12, count 0 2006.196.08:27:28.32#ibcon#read 4, iclass 12, count 0 2006.196.08:27:28.32#ibcon#about to read 5, iclass 12, count 0 2006.196.08:27:28.32#ibcon#read 5, iclass 12, count 0 2006.196.08:27:28.32#ibcon#about to read 6, iclass 12, count 0 2006.196.08:27:28.32#ibcon#read 6, iclass 12, count 0 2006.196.08:27:28.32#ibcon#end of sib2, iclass 12, count 0 2006.196.08:27:28.32#ibcon#*after write, iclass 12, count 0 2006.196.08:27:28.32#ibcon#*before return 0, iclass 12, count 0 2006.196.08:27:28.32#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.196.08:27:28.32#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.196.08:27:28.32#ibcon#about to clear, iclass 12 cls_cnt 0 2006.196.08:27:28.32#ibcon#cleared, iclass 12 cls_cnt 0 2006.196.08:27:28.32$vc4f8/va=2,7 2006.196.08:27:28.32#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.196.08:27:28.32#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.196.08:27:28.32#ibcon#ireg 11 cls_cnt 2 2006.196.08:27:28.32#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.196.08:27:28.38#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.196.08:27:28.38#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.196.08:27:28.38#ibcon#enter wrdev, iclass 14, count 2 2006.196.08:27:28.38#ibcon#first serial, iclass 14, count 2 2006.196.08:27:28.38#ibcon#enter sib2, iclass 14, count 2 2006.196.08:27:28.38#ibcon#flushed, iclass 14, count 2 2006.196.08:27:28.38#ibcon#about to write, iclass 14, count 2 2006.196.08:27:28.38#ibcon#wrote, iclass 14, count 2 2006.196.08:27:28.38#ibcon#about to read 3, iclass 14, count 2 2006.196.08:27:28.40#ibcon#read 3, iclass 14, count 2 2006.196.08:27:28.40#ibcon#about to read 4, iclass 14, count 2 2006.196.08:27:28.40#ibcon#read 4, iclass 14, count 2 2006.196.08:27:28.40#ibcon#about to read 5, iclass 14, count 2 2006.196.08:27:28.40#ibcon#read 5, iclass 14, count 2 2006.196.08:27:28.40#ibcon#about to read 6, iclass 14, count 2 2006.196.08:27:28.40#ibcon#read 6, iclass 14, count 2 2006.196.08:27:28.40#ibcon#end of sib2, iclass 14, count 2 2006.196.08:27:28.40#ibcon#*mode == 0, iclass 14, count 2 2006.196.08:27:28.40#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.196.08:27:28.40#ibcon#[25=AT02-07\r\n] 2006.196.08:27:28.40#ibcon#*before write, iclass 14, count 2 2006.196.08:27:28.40#ibcon#enter sib2, iclass 14, count 2 2006.196.08:27:28.40#ibcon#flushed, iclass 14, count 2 2006.196.08:27:28.40#ibcon#about to write, iclass 14, count 2 2006.196.08:27:28.40#ibcon#wrote, iclass 14, count 2 2006.196.08:27:28.40#ibcon#about to read 3, iclass 14, count 2 2006.196.08:27:28.43#ibcon#read 3, iclass 14, count 2 2006.196.08:27:28.43#ibcon#about to read 4, iclass 14, count 2 2006.196.08:27:28.43#ibcon#read 4, iclass 14, count 2 2006.196.08:27:28.43#ibcon#about to read 5, iclass 14, count 2 2006.196.08:27:28.43#ibcon#read 5, iclass 14, count 2 2006.196.08:27:28.43#ibcon#about to read 6, iclass 14, count 2 2006.196.08:27:28.43#ibcon#read 6, iclass 14, count 2 2006.196.08:27:28.43#ibcon#end of sib2, iclass 14, count 2 2006.196.08:27:28.43#ibcon#*after write, iclass 14, count 2 2006.196.08:27:28.43#ibcon#*before return 0, iclass 14, count 2 2006.196.08:27:28.43#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.196.08:27:28.43#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.196.08:27:28.43#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.196.08:27:28.43#ibcon#ireg 7 cls_cnt 0 2006.196.08:27:28.43#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.196.08:27:28.55#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.196.08:27:28.55#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.196.08:27:28.55#ibcon#enter wrdev, iclass 14, count 0 2006.196.08:27:28.55#ibcon#first serial, iclass 14, count 0 2006.196.08:27:28.55#ibcon#enter sib2, iclass 14, count 0 2006.196.08:27:28.55#ibcon#flushed, iclass 14, count 0 2006.196.08:27:28.55#ibcon#about to write, iclass 14, count 0 2006.196.08:27:28.55#ibcon#wrote, iclass 14, count 0 2006.196.08:27:28.55#ibcon#about to read 3, iclass 14, count 0 2006.196.08:27:28.57#ibcon#read 3, iclass 14, count 0 2006.196.08:27:28.57#ibcon#about to read 4, iclass 14, count 0 2006.196.08:27:28.57#ibcon#read 4, iclass 14, count 0 2006.196.08:27:28.57#ibcon#about to read 5, iclass 14, count 0 2006.196.08:27:28.57#ibcon#read 5, iclass 14, count 0 2006.196.08:27:28.57#ibcon#about to read 6, iclass 14, count 0 2006.196.08:27:28.57#ibcon#read 6, iclass 14, count 0 2006.196.08:27:28.57#ibcon#end of sib2, iclass 14, count 0 2006.196.08:27:28.57#ibcon#*mode == 0, iclass 14, count 0 2006.196.08:27:28.57#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.196.08:27:28.57#ibcon#[25=USB\r\n] 2006.196.08:27:28.57#ibcon#*before write, iclass 14, count 0 2006.196.08:27:28.57#ibcon#enter sib2, iclass 14, count 0 2006.196.08:27:28.57#ibcon#flushed, iclass 14, count 0 2006.196.08:27:28.57#ibcon#about to write, iclass 14, count 0 2006.196.08:27:28.57#ibcon#wrote, iclass 14, count 0 2006.196.08:27:28.57#ibcon#about to read 3, iclass 14, count 0 2006.196.08:27:28.60#ibcon#read 3, iclass 14, count 0 2006.196.08:27:28.60#ibcon#about to read 4, iclass 14, count 0 2006.196.08:27:28.60#ibcon#read 4, iclass 14, count 0 2006.196.08:27:28.60#ibcon#about to read 5, iclass 14, count 0 2006.196.08:27:28.60#ibcon#read 5, iclass 14, count 0 2006.196.08:27:28.60#ibcon#about to read 6, iclass 14, count 0 2006.196.08:27:28.60#ibcon#read 6, iclass 14, count 0 2006.196.08:27:28.60#ibcon#end of sib2, iclass 14, count 0 2006.196.08:27:28.60#ibcon#*after write, iclass 14, count 0 2006.196.08:27:28.60#ibcon#*before return 0, iclass 14, count 0 2006.196.08:27:28.60#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.196.08:27:28.60#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.196.08:27:28.60#ibcon#about to clear, iclass 14 cls_cnt 0 2006.196.08:27:28.60#ibcon#cleared, iclass 14 cls_cnt 0 2006.196.08:27:28.60$vc4f8/valo=3,672.99 2006.196.08:27:28.60#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.196.08:27:28.60#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.196.08:27:28.60#ibcon#ireg 17 cls_cnt 0 2006.196.08:27:28.60#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.196.08:27:28.60#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.196.08:27:28.60#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.196.08:27:28.60#ibcon#enter wrdev, iclass 16, count 0 2006.196.08:27:28.60#ibcon#first serial, iclass 16, count 0 2006.196.08:27:28.60#ibcon#enter sib2, iclass 16, count 0 2006.196.08:27:28.60#ibcon#flushed, iclass 16, count 0 2006.196.08:27:28.60#ibcon#about to write, iclass 16, count 0 2006.196.08:27:28.60#ibcon#wrote, iclass 16, count 0 2006.196.08:27:28.60#ibcon#about to read 3, iclass 16, count 0 2006.196.08:27:28.62#ibcon#read 3, iclass 16, count 0 2006.196.08:27:28.62#ibcon#about to read 4, iclass 16, count 0 2006.196.08:27:28.62#ibcon#read 4, iclass 16, count 0 2006.196.08:27:28.62#ibcon#about to read 5, iclass 16, count 0 2006.196.08:27:28.62#ibcon#read 5, iclass 16, count 0 2006.196.08:27:28.62#ibcon#about to read 6, iclass 16, count 0 2006.196.08:27:28.62#ibcon#read 6, iclass 16, count 0 2006.196.08:27:28.62#ibcon#end of sib2, iclass 16, count 0 2006.196.08:27:28.62#ibcon#*mode == 0, iclass 16, count 0 2006.196.08:27:28.62#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.196.08:27:28.62#ibcon#[26=FRQ=03,672.99\r\n] 2006.196.08:27:28.62#ibcon#*before write, iclass 16, count 0 2006.196.08:27:28.62#ibcon#enter sib2, iclass 16, count 0 2006.196.08:27:28.62#ibcon#flushed, iclass 16, count 0 2006.196.08:27:28.62#ibcon#about to write, iclass 16, count 0 2006.196.08:27:28.62#ibcon#wrote, iclass 16, count 0 2006.196.08:27:28.62#ibcon#about to read 3, iclass 16, count 0 2006.196.08:27:28.67#ibcon#read 3, iclass 16, count 0 2006.196.08:27:28.67#ibcon#about to read 4, iclass 16, count 0 2006.196.08:27:28.67#ibcon#read 4, iclass 16, count 0 2006.196.08:27:28.67#ibcon#about to read 5, iclass 16, count 0 2006.196.08:27:28.67#ibcon#read 5, iclass 16, count 0 2006.196.08:27:28.67#ibcon#about to read 6, iclass 16, count 0 2006.196.08:27:28.67#ibcon#read 6, iclass 16, count 0 2006.196.08:27:28.67#ibcon#end of sib2, iclass 16, count 0 2006.196.08:27:28.67#ibcon#*after write, iclass 16, count 0 2006.196.08:27:28.67#ibcon#*before return 0, iclass 16, count 0 2006.196.08:27:28.67#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.196.08:27:28.67#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.196.08:27:28.67#ibcon#about to clear, iclass 16 cls_cnt 0 2006.196.08:27:28.67#ibcon#cleared, iclass 16 cls_cnt 0 2006.196.08:27:28.67$vc4f8/va=3,6 2006.196.08:27:28.67#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.196.08:27:28.67#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.196.08:27:28.67#ibcon#ireg 11 cls_cnt 2 2006.196.08:27:28.67#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.196.08:27:28.72#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.196.08:27:28.72#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.196.08:27:28.72#ibcon#enter wrdev, iclass 18, count 2 2006.196.08:27:28.72#ibcon#first serial, iclass 18, count 2 2006.196.08:27:28.72#ibcon#enter sib2, iclass 18, count 2 2006.196.08:27:28.72#ibcon#flushed, iclass 18, count 2 2006.196.08:27:28.72#ibcon#about to write, iclass 18, count 2 2006.196.08:27:28.72#ibcon#wrote, iclass 18, count 2 2006.196.08:27:28.72#ibcon#about to read 3, iclass 18, count 2 2006.196.08:27:28.74#ibcon#read 3, iclass 18, count 2 2006.196.08:27:28.74#ibcon#about to read 4, iclass 18, count 2 2006.196.08:27:28.74#ibcon#read 4, iclass 18, count 2 2006.196.08:27:28.74#ibcon#about to read 5, iclass 18, count 2 2006.196.08:27:28.74#ibcon#read 5, iclass 18, count 2 2006.196.08:27:28.74#ibcon#about to read 6, iclass 18, count 2 2006.196.08:27:28.74#ibcon#read 6, iclass 18, count 2 2006.196.08:27:28.74#ibcon#end of sib2, iclass 18, count 2 2006.196.08:27:28.74#ibcon#*mode == 0, iclass 18, count 2 2006.196.08:27:28.74#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.196.08:27:28.74#ibcon#[25=AT03-06\r\n] 2006.196.08:27:28.74#ibcon#*before write, iclass 18, count 2 2006.196.08:27:28.74#ibcon#enter sib2, iclass 18, count 2 2006.196.08:27:28.74#ibcon#flushed, iclass 18, count 2 2006.196.08:27:28.74#ibcon#about to write, iclass 18, count 2 2006.196.08:27:28.74#ibcon#wrote, iclass 18, count 2 2006.196.08:27:28.74#ibcon#about to read 3, iclass 18, count 2 2006.196.08:27:28.77#ibcon#read 3, iclass 18, count 2 2006.196.08:27:28.77#ibcon#about to read 4, iclass 18, count 2 2006.196.08:27:28.77#ibcon#read 4, iclass 18, count 2 2006.196.08:27:28.77#ibcon#about to read 5, iclass 18, count 2 2006.196.08:27:28.77#ibcon#read 5, iclass 18, count 2 2006.196.08:27:28.77#ibcon#about to read 6, iclass 18, count 2 2006.196.08:27:28.77#ibcon#read 6, iclass 18, count 2 2006.196.08:27:28.77#ibcon#end of sib2, iclass 18, count 2 2006.196.08:27:28.77#ibcon#*after write, iclass 18, count 2 2006.196.08:27:28.77#ibcon#*before return 0, iclass 18, count 2 2006.196.08:27:28.77#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.196.08:27:28.77#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.196.08:27:28.77#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.196.08:27:28.77#ibcon#ireg 7 cls_cnt 0 2006.196.08:27:28.77#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.196.08:27:28.89#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.196.08:27:28.89#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.196.08:27:28.89#ibcon#enter wrdev, iclass 18, count 0 2006.196.08:27:28.89#ibcon#first serial, iclass 18, count 0 2006.196.08:27:28.89#ibcon#enter sib2, iclass 18, count 0 2006.196.08:27:28.89#ibcon#flushed, iclass 18, count 0 2006.196.08:27:28.89#ibcon#about to write, iclass 18, count 0 2006.196.08:27:28.89#ibcon#wrote, iclass 18, count 0 2006.196.08:27:28.89#ibcon#about to read 3, iclass 18, count 0 2006.196.08:27:28.91#ibcon#read 3, iclass 18, count 0 2006.196.08:27:28.91#ibcon#about to read 4, iclass 18, count 0 2006.196.08:27:28.91#ibcon#read 4, iclass 18, count 0 2006.196.08:27:28.91#ibcon#about to read 5, iclass 18, count 0 2006.196.08:27:28.91#ibcon#read 5, iclass 18, count 0 2006.196.08:27:28.91#ibcon#about to read 6, iclass 18, count 0 2006.196.08:27:28.91#ibcon#read 6, iclass 18, count 0 2006.196.08:27:28.91#ibcon#end of sib2, iclass 18, count 0 2006.196.08:27:28.91#ibcon#*mode == 0, iclass 18, count 0 2006.196.08:27:28.91#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.196.08:27:28.91#ibcon#[25=USB\r\n] 2006.196.08:27:28.91#ibcon#*before write, iclass 18, count 0 2006.196.08:27:28.91#ibcon#enter sib2, iclass 18, count 0 2006.196.08:27:28.91#ibcon#flushed, iclass 18, count 0 2006.196.08:27:28.91#ibcon#about to write, iclass 18, count 0 2006.196.08:27:28.91#ibcon#wrote, iclass 18, count 0 2006.196.08:27:28.91#ibcon#about to read 3, iclass 18, count 0 2006.196.08:27:28.94#ibcon#read 3, iclass 18, count 0 2006.196.08:27:28.94#ibcon#about to read 4, iclass 18, count 0 2006.196.08:27:28.94#ibcon#read 4, iclass 18, count 0 2006.196.08:27:28.94#ibcon#about to read 5, iclass 18, count 0 2006.196.08:27:28.94#ibcon#read 5, iclass 18, count 0 2006.196.08:27:28.94#ibcon#about to read 6, iclass 18, count 0 2006.196.08:27:28.94#ibcon#read 6, iclass 18, count 0 2006.196.08:27:28.94#ibcon#end of sib2, iclass 18, count 0 2006.196.08:27:28.94#ibcon#*after write, iclass 18, count 0 2006.196.08:27:28.94#ibcon#*before return 0, iclass 18, count 0 2006.196.08:27:28.94#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.196.08:27:28.94#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.196.08:27:28.94#ibcon#about to clear, iclass 18 cls_cnt 0 2006.196.08:27:28.94#ibcon#cleared, iclass 18 cls_cnt 0 2006.196.08:27:28.94$vc4f8/valo=4,832.99 2006.196.08:27:28.94#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.196.08:27:28.94#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.196.08:27:28.94#ibcon#ireg 17 cls_cnt 0 2006.196.08:27:28.94#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.196.08:27:28.94#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.196.08:27:28.94#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.196.08:27:28.94#ibcon#enter wrdev, iclass 20, count 0 2006.196.08:27:28.94#ibcon#first serial, iclass 20, count 0 2006.196.08:27:28.94#ibcon#enter sib2, iclass 20, count 0 2006.196.08:27:28.94#ibcon#flushed, iclass 20, count 0 2006.196.08:27:28.94#ibcon#about to write, iclass 20, count 0 2006.196.08:27:28.94#ibcon#wrote, iclass 20, count 0 2006.196.08:27:28.94#ibcon#about to read 3, iclass 20, count 0 2006.196.08:27:28.96#ibcon#read 3, iclass 20, count 0 2006.196.08:27:28.96#ibcon#about to read 4, iclass 20, count 0 2006.196.08:27:28.96#ibcon#read 4, iclass 20, count 0 2006.196.08:27:28.96#ibcon#about to read 5, iclass 20, count 0 2006.196.08:27:28.96#ibcon#read 5, iclass 20, count 0 2006.196.08:27:28.96#ibcon#about to read 6, iclass 20, count 0 2006.196.08:27:28.96#ibcon#read 6, iclass 20, count 0 2006.196.08:27:28.96#ibcon#end of sib2, iclass 20, count 0 2006.196.08:27:28.96#ibcon#*mode == 0, iclass 20, count 0 2006.196.08:27:28.96#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.196.08:27:28.96#ibcon#[26=FRQ=04,832.99\r\n] 2006.196.08:27:28.96#ibcon#*before write, iclass 20, count 0 2006.196.08:27:28.96#ibcon#enter sib2, iclass 20, count 0 2006.196.08:27:28.96#ibcon#flushed, iclass 20, count 0 2006.196.08:27:28.96#ibcon#about to write, iclass 20, count 0 2006.196.08:27:28.96#ibcon#wrote, iclass 20, count 0 2006.196.08:27:28.96#ibcon#about to read 3, iclass 20, count 0 2006.196.08:27:29.00#ibcon#read 3, iclass 20, count 0 2006.196.08:27:29.00#ibcon#about to read 4, iclass 20, count 0 2006.196.08:27:29.00#ibcon#read 4, iclass 20, count 0 2006.196.08:27:29.00#ibcon#about to read 5, iclass 20, count 0 2006.196.08:27:29.00#ibcon#read 5, iclass 20, count 0 2006.196.08:27:29.00#ibcon#about to read 6, iclass 20, count 0 2006.196.08:27:29.00#ibcon#read 6, iclass 20, count 0 2006.196.08:27:29.00#ibcon#end of sib2, iclass 20, count 0 2006.196.08:27:29.00#ibcon#*after write, iclass 20, count 0 2006.196.08:27:29.00#ibcon#*before return 0, iclass 20, count 0 2006.196.08:27:29.00#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.196.08:27:29.00#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.196.08:27:29.00#ibcon#about to clear, iclass 20 cls_cnt 0 2006.196.08:27:29.00#ibcon#cleared, iclass 20 cls_cnt 0 2006.196.08:27:29.00$vc4f8/va=4,7 2006.196.08:27:29.00#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.196.08:27:29.00#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.196.08:27:29.00#ibcon#ireg 11 cls_cnt 2 2006.196.08:27:29.00#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.196.08:27:29.06#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.196.08:27:29.06#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.196.08:27:29.06#ibcon#enter wrdev, iclass 22, count 2 2006.196.08:27:29.06#ibcon#first serial, iclass 22, count 2 2006.196.08:27:29.06#ibcon#enter sib2, iclass 22, count 2 2006.196.08:27:29.06#ibcon#flushed, iclass 22, count 2 2006.196.08:27:29.06#ibcon#about to write, iclass 22, count 2 2006.196.08:27:29.06#ibcon#wrote, iclass 22, count 2 2006.196.08:27:29.06#ibcon#about to read 3, iclass 22, count 2 2006.196.08:27:29.08#ibcon#read 3, iclass 22, count 2 2006.196.08:27:29.08#ibcon#about to read 4, iclass 22, count 2 2006.196.08:27:29.08#ibcon#read 4, iclass 22, count 2 2006.196.08:27:29.08#ibcon#about to read 5, iclass 22, count 2 2006.196.08:27:29.08#ibcon#read 5, iclass 22, count 2 2006.196.08:27:29.08#ibcon#about to read 6, iclass 22, count 2 2006.196.08:27:29.08#ibcon#read 6, iclass 22, count 2 2006.196.08:27:29.08#ibcon#end of sib2, iclass 22, count 2 2006.196.08:27:29.08#ibcon#*mode == 0, iclass 22, count 2 2006.196.08:27:29.08#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.196.08:27:29.08#ibcon#[25=AT04-07\r\n] 2006.196.08:27:29.08#ibcon#*before write, iclass 22, count 2 2006.196.08:27:29.08#ibcon#enter sib2, iclass 22, count 2 2006.196.08:27:29.08#ibcon#flushed, iclass 22, count 2 2006.196.08:27:29.08#ibcon#about to write, iclass 22, count 2 2006.196.08:27:29.08#ibcon#wrote, iclass 22, count 2 2006.196.08:27:29.08#ibcon#about to read 3, iclass 22, count 2 2006.196.08:27:29.11#abcon#<5=/05 3.2 6.2 28.78 931004.3\r\n> 2006.196.08:27:29.11#ibcon#read 3, iclass 22, count 2 2006.196.08:27:29.11#ibcon#about to read 4, iclass 22, count 2 2006.196.08:27:29.11#ibcon#read 4, iclass 22, count 2 2006.196.08:27:29.11#ibcon#about to read 5, iclass 22, count 2 2006.196.08:27:29.11#ibcon#read 5, iclass 22, count 2 2006.196.08:27:29.11#ibcon#about to read 6, iclass 22, count 2 2006.196.08:27:29.11#ibcon#read 6, iclass 22, count 2 2006.196.08:27:29.11#ibcon#end of sib2, iclass 22, count 2 2006.196.08:27:29.11#ibcon#*after write, iclass 22, count 2 2006.196.08:27:29.11#ibcon#*before return 0, iclass 22, count 2 2006.196.08:27:29.11#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.196.08:27:29.11#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.196.08:27:29.11#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.196.08:27:29.11#ibcon#ireg 7 cls_cnt 0 2006.196.08:27:29.11#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.196.08:27:29.13#abcon#{5=INTERFACE CLEAR} 2006.196.08:27:29.19#abcon#[5=S1D000X0/0*\r\n] 2006.196.08:27:29.23#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.196.08:27:29.23#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.196.08:27:29.23#ibcon#enter wrdev, iclass 22, count 0 2006.196.08:27:29.23#ibcon#first serial, iclass 22, count 0 2006.196.08:27:29.23#ibcon#enter sib2, iclass 22, count 0 2006.196.08:27:29.23#ibcon#flushed, iclass 22, count 0 2006.196.08:27:29.23#ibcon#about to write, iclass 22, count 0 2006.196.08:27:29.23#ibcon#wrote, iclass 22, count 0 2006.196.08:27:29.23#ibcon#about to read 3, iclass 22, count 0 2006.196.08:27:29.25#ibcon#read 3, iclass 22, count 0 2006.196.08:27:29.25#ibcon#about to read 4, iclass 22, count 0 2006.196.08:27:29.25#ibcon#read 4, iclass 22, count 0 2006.196.08:27:29.25#ibcon#about to read 5, iclass 22, count 0 2006.196.08:27:29.25#ibcon#read 5, iclass 22, count 0 2006.196.08:27:29.25#ibcon#about to read 6, iclass 22, count 0 2006.196.08:27:29.25#ibcon#read 6, iclass 22, count 0 2006.196.08:27:29.25#ibcon#end of sib2, iclass 22, count 0 2006.196.08:27:29.25#ibcon#*mode == 0, iclass 22, count 0 2006.196.08:27:29.25#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.196.08:27:29.25#ibcon#[25=USB\r\n] 2006.196.08:27:29.25#ibcon#*before write, iclass 22, count 0 2006.196.08:27:29.25#ibcon#enter sib2, iclass 22, count 0 2006.196.08:27:29.25#ibcon#flushed, iclass 22, count 0 2006.196.08:27:29.25#ibcon#about to write, iclass 22, count 0 2006.196.08:27:29.25#ibcon#wrote, iclass 22, count 0 2006.196.08:27:29.25#ibcon#about to read 3, iclass 22, count 0 2006.196.08:27:29.28#ibcon#read 3, iclass 22, count 0 2006.196.08:27:29.28#ibcon#about to read 4, iclass 22, count 0 2006.196.08:27:29.28#ibcon#read 4, iclass 22, count 0 2006.196.08:27:29.28#ibcon#about to read 5, iclass 22, count 0 2006.196.08:27:29.28#ibcon#read 5, iclass 22, count 0 2006.196.08:27:29.28#ibcon#about to read 6, iclass 22, count 0 2006.196.08:27:29.28#ibcon#read 6, iclass 22, count 0 2006.196.08:27:29.28#ibcon#end of sib2, iclass 22, count 0 2006.196.08:27:29.28#ibcon#*after write, iclass 22, count 0 2006.196.08:27:29.28#ibcon#*before return 0, iclass 22, count 0 2006.196.08:27:29.28#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.196.08:27:29.28#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.196.08:27:29.28#ibcon#about to clear, iclass 22 cls_cnt 0 2006.196.08:27:29.28#ibcon#cleared, iclass 22 cls_cnt 0 2006.196.08:27:29.28$vc4f8/valo=5,652.99 2006.196.08:27:29.28#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.196.08:27:29.28#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.196.08:27:29.28#ibcon#ireg 17 cls_cnt 0 2006.196.08:27:29.28#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.196.08:27:29.28#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.196.08:27:29.28#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.196.08:27:29.28#ibcon#enter wrdev, iclass 28, count 0 2006.196.08:27:29.28#ibcon#first serial, iclass 28, count 0 2006.196.08:27:29.28#ibcon#enter sib2, iclass 28, count 0 2006.196.08:27:29.28#ibcon#flushed, iclass 28, count 0 2006.196.08:27:29.28#ibcon#about to write, iclass 28, count 0 2006.196.08:27:29.28#ibcon#wrote, iclass 28, count 0 2006.196.08:27:29.28#ibcon#about to read 3, iclass 28, count 0 2006.196.08:27:29.30#ibcon#read 3, iclass 28, count 0 2006.196.08:27:29.30#ibcon#about to read 4, iclass 28, count 0 2006.196.08:27:29.30#ibcon#read 4, iclass 28, count 0 2006.196.08:27:29.30#ibcon#about to read 5, iclass 28, count 0 2006.196.08:27:29.30#ibcon#read 5, iclass 28, count 0 2006.196.08:27:29.30#ibcon#about to read 6, iclass 28, count 0 2006.196.08:27:29.30#ibcon#read 6, iclass 28, count 0 2006.196.08:27:29.30#ibcon#end of sib2, iclass 28, count 0 2006.196.08:27:29.30#ibcon#*mode == 0, iclass 28, count 0 2006.196.08:27:29.30#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.196.08:27:29.30#ibcon#[26=FRQ=05,652.99\r\n] 2006.196.08:27:29.30#ibcon#*before write, iclass 28, count 0 2006.196.08:27:29.30#ibcon#enter sib2, iclass 28, count 0 2006.196.08:27:29.30#ibcon#flushed, iclass 28, count 0 2006.196.08:27:29.30#ibcon#about to write, iclass 28, count 0 2006.196.08:27:29.30#ibcon#wrote, iclass 28, count 0 2006.196.08:27:29.30#ibcon#about to read 3, iclass 28, count 0 2006.196.08:27:29.34#ibcon#read 3, iclass 28, count 0 2006.196.08:27:29.34#ibcon#about to read 4, iclass 28, count 0 2006.196.08:27:29.34#ibcon#read 4, iclass 28, count 0 2006.196.08:27:29.34#ibcon#about to read 5, iclass 28, count 0 2006.196.08:27:29.34#ibcon#read 5, iclass 28, count 0 2006.196.08:27:29.34#ibcon#about to read 6, iclass 28, count 0 2006.196.08:27:29.34#ibcon#read 6, iclass 28, count 0 2006.196.08:27:29.34#ibcon#end of sib2, iclass 28, count 0 2006.196.08:27:29.34#ibcon#*after write, iclass 28, count 0 2006.196.08:27:29.34#ibcon#*before return 0, iclass 28, count 0 2006.196.08:27:29.34#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.196.08:27:29.34#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.196.08:27:29.34#ibcon#about to clear, iclass 28 cls_cnt 0 2006.196.08:27:29.34#ibcon#cleared, iclass 28 cls_cnt 0 2006.196.08:27:29.34$vc4f8/va=5,7 2006.196.08:27:29.34#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.196.08:27:29.34#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.196.08:27:29.34#ibcon#ireg 11 cls_cnt 2 2006.196.08:27:29.34#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.196.08:27:29.40#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.196.08:27:29.40#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.196.08:27:29.40#ibcon#enter wrdev, iclass 30, count 2 2006.196.08:27:29.40#ibcon#first serial, iclass 30, count 2 2006.196.08:27:29.40#ibcon#enter sib2, iclass 30, count 2 2006.196.08:27:29.40#ibcon#flushed, iclass 30, count 2 2006.196.08:27:29.40#ibcon#about to write, iclass 30, count 2 2006.196.08:27:29.40#ibcon#wrote, iclass 30, count 2 2006.196.08:27:29.40#ibcon#about to read 3, iclass 30, count 2 2006.196.08:27:29.42#ibcon#read 3, iclass 30, count 2 2006.196.08:27:29.42#ibcon#about to read 4, iclass 30, count 2 2006.196.08:27:29.42#ibcon#read 4, iclass 30, count 2 2006.196.08:27:29.42#ibcon#about to read 5, iclass 30, count 2 2006.196.08:27:29.42#ibcon#read 5, iclass 30, count 2 2006.196.08:27:29.42#ibcon#about to read 6, iclass 30, count 2 2006.196.08:27:29.42#ibcon#read 6, iclass 30, count 2 2006.196.08:27:29.42#ibcon#end of sib2, iclass 30, count 2 2006.196.08:27:29.42#ibcon#*mode == 0, iclass 30, count 2 2006.196.08:27:29.42#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.196.08:27:29.42#ibcon#[25=AT05-07\r\n] 2006.196.08:27:29.42#ibcon#*before write, iclass 30, count 2 2006.196.08:27:29.42#ibcon#enter sib2, iclass 30, count 2 2006.196.08:27:29.42#ibcon#flushed, iclass 30, count 2 2006.196.08:27:29.42#ibcon#about to write, iclass 30, count 2 2006.196.08:27:29.42#ibcon#wrote, iclass 30, count 2 2006.196.08:27:29.42#ibcon#about to read 3, iclass 30, count 2 2006.196.08:27:29.45#ibcon#read 3, iclass 30, count 2 2006.196.08:27:29.45#ibcon#about to read 4, iclass 30, count 2 2006.196.08:27:29.45#ibcon#read 4, iclass 30, count 2 2006.196.08:27:29.45#ibcon#about to read 5, iclass 30, count 2 2006.196.08:27:29.45#ibcon#read 5, iclass 30, count 2 2006.196.08:27:29.45#ibcon#about to read 6, iclass 30, count 2 2006.196.08:27:29.45#ibcon#read 6, iclass 30, count 2 2006.196.08:27:29.45#ibcon#end of sib2, iclass 30, count 2 2006.196.08:27:29.45#ibcon#*after write, iclass 30, count 2 2006.196.08:27:29.45#ibcon#*before return 0, iclass 30, count 2 2006.196.08:27:29.45#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.196.08:27:29.45#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.196.08:27:29.45#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.196.08:27:29.45#ibcon#ireg 7 cls_cnt 0 2006.196.08:27:29.45#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.196.08:27:29.57#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.196.08:27:29.57#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.196.08:27:29.57#ibcon#enter wrdev, iclass 30, count 0 2006.196.08:27:29.57#ibcon#first serial, iclass 30, count 0 2006.196.08:27:29.57#ibcon#enter sib2, iclass 30, count 0 2006.196.08:27:29.57#ibcon#flushed, iclass 30, count 0 2006.196.08:27:29.57#ibcon#about to write, iclass 30, count 0 2006.196.08:27:29.57#ibcon#wrote, iclass 30, count 0 2006.196.08:27:29.57#ibcon#about to read 3, iclass 30, count 0 2006.196.08:27:29.59#ibcon#read 3, iclass 30, count 0 2006.196.08:27:29.59#ibcon#about to read 4, iclass 30, count 0 2006.196.08:27:29.59#ibcon#read 4, iclass 30, count 0 2006.196.08:27:29.59#ibcon#about to read 5, iclass 30, count 0 2006.196.08:27:29.59#ibcon#read 5, iclass 30, count 0 2006.196.08:27:29.59#ibcon#about to read 6, iclass 30, count 0 2006.196.08:27:29.59#ibcon#read 6, iclass 30, count 0 2006.196.08:27:29.59#ibcon#end of sib2, iclass 30, count 0 2006.196.08:27:29.59#ibcon#*mode == 0, iclass 30, count 0 2006.196.08:27:29.59#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.196.08:27:29.59#ibcon#[25=USB\r\n] 2006.196.08:27:29.59#ibcon#*before write, iclass 30, count 0 2006.196.08:27:29.59#ibcon#enter sib2, iclass 30, count 0 2006.196.08:27:29.59#ibcon#flushed, iclass 30, count 0 2006.196.08:27:29.59#ibcon#about to write, iclass 30, count 0 2006.196.08:27:29.59#ibcon#wrote, iclass 30, count 0 2006.196.08:27:29.59#ibcon#about to read 3, iclass 30, count 0 2006.196.08:27:29.62#ibcon#read 3, iclass 30, count 0 2006.196.08:27:29.62#ibcon#about to read 4, iclass 30, count 0 2006.196.08:27:29.62#ibcon#read 4, iclass 30, count 0 2006.196.08:27:29.62#ibcon#about to read 5, iclass 30, count 0 2006.196.08:27:29.62#ibcon#read 5, iclass 30, count 0 2006.196.08:27:29.62#ibcon#about to read 6, iclass 30, count 0 2006.196.08:27:29.62#ibcon#read 6, iclass 30, count 0 2006.196.08:27:29.62#ibcon#end of sib2, iclass 30, count 0 2006.196.08:27:29.62#ibcon#*after write, iclass 30, count 0 2006.196.08:27:29.62#ibcon#*before return 0, iclass 30, count 0 2006.196.08:27:29.62#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.196.08:27:29.62#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.196.08:27:29.62#ibcon#about to clear, iclass 30 cls_cnt 0 2006.196.08:27:29.62#ibcon#cleared, iclass 30 cls_cnt 0 2006.196.08:27:29.62$vc4f8/valo=6,772.99 2006.196.08:27:29.62#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.196.08:27:29.62#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.196.08:27:29.62#ibcon#ireg 17 cls_cnt 0 2006.196.08:27:29.62#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.196.08:27:29.62#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.196.08:27:29.62#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.196.08:27:29.62#ibcon#enter wrdev, iclass 32, count 0 2006.196.08:27:29.62#ibcon#first serial, iclass 32, count 0 2006.196.08:27:29.62#ibcon#enter sib2, iclass 32, count 0 2006.196.08:27:29.62#ibcon#flushed, iclass 32, count 0 2006.196.08:27:29.62#ibcon#about to write, iclass 32, count 0 2006.196.08:27:29.62#ibcon#wrote, iclass 32, count 0 2006.196.08:27:29.62#ibcon#about to read 3, iclass 32, count 0 2006.196.08:27:29.64#ibcon#read 3, iclass 32, count 0 2006.196.08:27:29.64#ibcon#about to read 4, iclass 32, count 0 2006.196.08:27:29.64#ibcon#read 4, iclass 32, count 0 2006.196.08:27:29.64#ibcon#about to read 5, iclass 32, count 0 2006.196.08:27:29.64#ibcon#read 5, iclass 32, count 0 2006.196.08:27:29.64#ibcon#about to read 6, iclass 32, count 0 2006.196.08:27:29.64#ibcon#read 6, iclass 32, count 0 2006.196.08:27:29.64#ibcon#end of sib2, iclass 32, count 0 2006.196.08:27:29.64#ibcon#*mode == 0, iclass 32, count 0 2006.196.08:27:29.64#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.196.08:27:29.64#ibcon#[26=FRQ=06,772.99\r\n] 2006.196.08:27:29.64#ibcon#*before write, iclass 32, count 0 2006.196.08:27:29.64#ibcon#enter sib2, iclass 32, count 0 2006.196.08:27:29.64#ibcon#flushed, iclass 32, count 0 2006.196.08:27:29.64#ibcon#about to write, iclass 32, count 0 2006.196.08:27:29.64#ibcon#wrote, iclass 32, count 0 2006.196.08:27:29.64#ibcon#about to read 3, iclass 32, count 0 2006.196.08:27:29.69#ibcon#read 3, iclass 32, count 0 2006.196.08:27:29.69#ibcon#about to read 4, iclass 32, count 0 2006.196.08:27:29.69#ibcon#read 4, iclass 32, count 0 2006.196.08:27:29.69#ibcon#about to read 5, iclass 32, count 0 2006.196.08:27:29.69#ibcon#read 5, iclass 32, count 0 2006.196.08:27:29.69#ibcon#about to read 6, iclass 32, count 0 2006.196.08:27:29.69#ibcon#read 6, iclass 32, count 0 2006.196.08:27:29.69#ibcon#end of sib2, iclass 32, count 0 2006.196.08:27:29.69#ibcon#*after write, iclass 32, count 0 2006.196.08:27:29.69#ibcon#*before return 0, iclass 32, count 0 2006.196.08:27:29.69#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.196.08:27:29.69#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.196.08:27:29.69#ibcon#about to clear, iclass 32 cls_cnt 0 2006.196.08:27:29.69#ibcon#cleared, iclass 32 cls_cnt 0 2006.196.08:27:29.69$vc4f8/va=6,6 2006.196.08:27:29.69#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.196.08:27:29.69#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.196.08:27:29.69#ibcon#ireg 11 cls_cnt 2 2006.196.08:27:29.69#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.196.08:27:29.74#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.196.08:27:29.74#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.196.08:27:29.74#ibcon#enter wrdev, iclass 34, count 2 2006.196.08:27:29.74#ibcon#first serial, iclass 34, count 2 2006.196.08:27:29.74#ibcon#enter sib2, iclass 34, count 2 2006.196.08:27:29.74#ibcon#flushed, iclass 34, count 2 2006.196.08:27:29.74#ibcon#about to write, iclass 34, count 2 2006.196.08:27:29.74#ibcon#wrote, iclass 34, count 2 2006.196.08:27:29.74#ibcon#about to read 3, iclass 34, count 2 2006.196.08:27:29.76#ibcon#read 3, iclass 34, count 2 2006.196.08:27:29.76#ibcon#about to read 4, iclass 34, count 2 2006.196.08:27:29.76#ibcon#read 4, iclass 34, count 2 2006.196.08:27:29.76#ibcon#about to read 5, iclass 34, count 2 2006.196.08:27:29.76#ibcon#read 5, iclass 34, count 2 2006.196.08:27:29.76#ibcon#about to read 6, iclass 34, count 2 2006.196.08:27:29.76#ibcon#read 6, iclass 34, count 2 2006.196.08:27:29.76#ibcon#end of sib2, iclass 34, count 2 2006.196.08:27:29.76#ibcon#*mode == 0, iclass 34, count 2 2006.196.08:27:29.76#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.196.08:27:29.76#ibcon#[25=AT06-06\r\n] 2006.196.08:27:29.76#ibcon#*before write, iclass 34, count 2 2006.196.08:27:29.76#ibcon#enter sib2, iclass 34, count 2 2006.196.08:27:29.76#ibcon#flushed, iclass 34, count 2 2006.196.08:27:29.76#ibcon#about to write, iclass 34, count 2 2006.196.08:27:29.76#ibcon#wrote, iclass 34, count 2 2006.196.08:27:29.76#ibcon#about to read 3, iclass 34, count 2 2006.196.08:27:29.79#ibcon#read 3, iclass 34, count 2 2006.196.08:27:29.79#ibcon#about to read 4, iclass 34, count 2 2006.196.08:27:29.79#ibcon#read 4, iclass 34, count 2 2006.196.08:27:29.79#ibcon#about to read 5, iclass 34, count 2 2006.196.08:27:29.79#ibcon#read 5, iclass 34, count 2 2006.196.08:27:29.79#ibcon#about to read 6, iclass 34, count 2 2006.196.08:27:29.79#ibcon#read 6, iclass 34, count 2 2006.196.08:27:29.79#ibcon#end of sib2, iclass 34, count 2 2006.196.08:27:29.79#ibcon#*after write, iclass 34, count 2 2006.196.08:27:29.79#ibcon#*before return 0, iclass 34, count 2 2006.196.08:27:29.79#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.196.08:27:29.79#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.196.08:27:29.79#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.196.08:27:29.79#ibcon#ireg 7 cls_cnt 0 2006.196.08:27:29.79#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.196.08:27:29.91#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.196.08:27:29.91#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.196.08:27:29.91#ibcon#enter wrdev, iclass 34, count 0 2006.196.08:27:29.91#ibcon#first serial, iclass 34, count 0 2006.196.08:27:29.91#ibcon#enter sib2, iclass 34, count 0 2006.196.08:27:29.91#ibcon#flushed, iclass 34, count 0 2006.196.08:27:29.91#ibcon#about to write, iclass 34, count 0 2006.196.08:27:29.91#ibcon#wrote, iclass 34, count 0 2006.196.08:27:29.91#ibcon#about to read 3, iclass 34, count 0 2006.196.08:27:29.93#ibcon#read 3, iclass 34, count 0 2006.196.08:27:29.93#ibcon#about to read 4, iclass 34, count 0 2006.196.08:27:29.93#ibcon#read 4, iclass 34, count 0 2006.196.08:27:29.93#ibcon#about to read 5, iclass 34, count 0 2006.196.08:27:29.93#ibcon#read 5, iclass 34, count 0 2006.196.08:27:29.93#ibcon#about to read 6, iclass 34, count 0 2006.196.08:27:29.93#ibcon#read 6, iclass 34, count 0 2006.196.08:27:29.93#ibcon#end of sib2, iclass 34, count 0 2006.196.08:27:29.93#ibcon#*mode == 0, iclass 34, count 0 2006.196.08:27:29.93#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.196.08:27:29.93#ibcon#[25=USB\r\n] 2006.196.08:27:29.93#ibcon#*before write, iclass 34, count 0 2006.196.08:27:29.93#ibcon#enter sib2, iclass 34, count 0 2006.196.08:27:29.93#ibcon#flushed, iclass 34, count 0 2006.196.08:27:29.93#ibcon#about to write, iclass 34, count 0 2006.196.08:27:29.93#ibcon#wrote, iclass 34, count 0 2006.196.08:27:29.93#ibcon#about to read 3, iclass 34, count 0 2006.196.08:27:29.96#ibcon#read 3, iclass 34, count 0 2006.196.08:27:29.96#ibcon#about to read 4, iclass 34, count 0 2006.196.08:27:29.96#ibcon#read 4, iclass 34, count 0 2006.196.08:27:29.96#ibcon#about to read 5, iclass 34, count 0 2006.196.08:27:29.96#ibcon#read 5, iclass 34, count 0 2006.196.08:27:29.96#ibcon#about to read 6, iclass 34, count 0 2006.196.08:27:29.96#ibcon#read 6, iclass 34, count 0 2006.196.08:27:29.96#ibcon#end of sib2, iclass 34, count 0 2006.196.08:27:29.96#ibcon#*after write, iclass 34, count 0 2006.196.08:27:29.96#ibcon#*before return 0, iclass 34, count 0 2006.196.08:27:29.96#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.196.08:27:29.96#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.196.08:27:29.96#ibcon#about to clear, iclass 34 cls_cnt 0 2006.196.08:27:29.96#ibcon#cleared, iclass 34 cls_cnt 0 2006.196.08:27:29.96$vc4f8/valo=7,832.99 2006.196.08:27:29.96#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.196.08:27:29.96#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.196.08:27:29.96#ibcon#ireg 17 cls_cnt 0 2006.196.08:27:29.96#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.196.08:27:29.96#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.196.08:27:29.96#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.196.08:27:29.96#ibcon#enter wrdev, iclass 36, count 0 2006.196.08:27:29.96#ibcon#first serial, iclass 36, count 0 2006.196.08:27:29.96#ibcon#enter sib2, iclass 36, count 0 2006.196.08:27:29.96#ibcon#flushed, iclass 36, count 0 2006.196.08:27:29.96#ibcon#about to write, iclass 36, count 0 2006.196.08:27:29.96#ibcon#wrote, iclass 36, count 0 2006.196.08:27:29.96#ibcon#about to read 3, iclass 36, count 0 2006.196.08:27:29.98#ibcon#read 3, iclass 36, count 0 2006.196.08:27:29.98#ibcon#about to read 4, iclass 36, count 0 2006.196.08:27:29.98#ibcon#read 4, iclass 36, count 0 2006.196.08:27:29.98#ibcon#about to read 5, iclass 36, count 0 2006.196.08:27:29.98#ibcon#read 5, iclass 36, count 0 2006.196.08:27:29.98#ibcon#about to read 6, iclass 36, count 0 2006.196.08:27:29.98#ibcon#read 6, iclass 36, count 0 2006.196.08:27:29.98#ibcon#end of sib2, iclass 36, count 0 2006.196.08:27:29.98#ibcon#*mode == 0, iclass 36, count 0 2006.196.08:27:29.98#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.196.08:27:29.98#ibcon#[26=FRQ=07,832.99\r\n] 2006.196.08:27:29.98#ibcon#*before write, iclass 36, count 0 2006.196.08:27:29.98#ibcon#enter sib2, iclass 36, count 0 2006.196.08:27:29.98#ibcon#flushed, iclass 36, count 0 2006.196.08:27:29.98#ibcon#about to write, iclass 36, count 0 2006.196.08:27:29.98#ibcon#wrote, iclass 36, count 0 2006.196.08:27:29.98#ibcon#about to read 3, iclass 36, count 0 2006.196.08:27:30.02#ibcon#read 3, iclass 36, count 0 2006.196.08:27:30.02#ibcon#about to read 4, iclass 36, count 0 2006.196.08:27:30.02#ibcon#read 4, iclass 36, count 0 2006.196.08:27:30.02#ibcon#about to read 5, iclass 36, count 0 2006.196.08:27:30.02#ibcon#read 5, iclass 36, count 0 2006.196.08:27:30.02#ibcon#about to read 6, iclass 36, count 0 2006.196.08:27:30.02#ibcon#read 6, iclass 36, count 0 2006.196.08:27:30.02#ibcon#end of sib2, iclass 36, count 0 2006.196.08:27:30.02#ibcon#*after write, iclass 36, count 0 2006.196.08:27:30.02#ibcon#*before return 0, iclass 36, count 0 2006.196.08:27:30.02#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.196.08:27:30.02#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.196.08:27:30.02#ibcon#about to clear, iclass 36 cls_cnt 0 2006.196.08:27:30.02#ibcon#cleared, iclass 36 cls_cnt 0 2006.196.08:27:30.02$vc4f8/va=7,6 2006.196.08:27:30.02#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.196.08:27:30.02#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.196.08:27:30.02#ibcon#ireg 11 cls_cnt 2 2006.196.08:27:30.02#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.196.08:27:30.08#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.196.08:27:30.08#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.196.08:27:30.08#ibcon#enter wrdev, iclass 38, count 2 2006.196.08:27:30.08#ibcon#first serial, iclass 38, count 2 2006.196.08:27:30.08#ibcon#enter sib2, iclass 38, count 2 2006.196.08:27:30.08#ibcon#flushed, iclass 38, count 2 2006.196.08:27:30.08#ibcon#about to write, iclass 38, count 2 2006.196.08:27:30.08#ibcon#wrote, iclass 38, count 2 2006.196.08:27:30.08#ibcon#about to read 3, iclass 38, count 2 2006.196.08:27:30.10#ibcon#read 3, iclass 38, count 2 2006.196.08:27:30.10#ibcon#about to read 4, iclass 38, count 2 2006.196.08:27:30.10#ibcon#read 4, iclass 38, count 2 2006.196.08:27:30.10#ibcon#about to read 5, iclass 38, count 2 2006.196.08:27:30.10#ibcon#read 5, iclass 38, count 2 2006.196.08:27:30.10#ibcon#about to read 6, iclass 38, count 2 2006.196.08:27:30.10#ibcon#read 6, iclass 38, count 2 2006.196.08:27:30.10#ibcon#end of sib2, iclass 38, count 2 2006.196.08:27:30.10#ibcon#*mode == 0, iclass 38, count 2 2006.196.08:27:30.10#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.196.08:27:30.10#ibcon#[25=AT07-06\r\n] 2006.196.08:27:30.10#ibcon#*before write, iclass 38, count 2 2006.196.08:27:30.10#ibcon#enter sib2, iclass 38, count 2 2006.196.08:27:30.10#ibcon#flushed, iclass 38, count 2 2006.196.08:27:30.10#ibcon#about to write, iclass 38, count 2 2006.196.08:27:30.10#ibcon#wrote, iclass 38, count 2 2006.196.08:27:30.10#ibcon#about to read 3, iclass 38, count 2 2006.196.08:27:30.13#ibcon#read 3, iclass 38, count 2 2006.196.08:27:30.13#ibcon#about to read 4, iclass 38, count 2 2006.196.08:27:30.13#ibcon#read 4, iclass 38, count 2 2006.196.08:27:30.13#ibcon#about to read 5, iclass 38, count 2 2006.196.08:27:30.13#ibcon#read 5, iclass 38, count 2 2006.196.08:27:30.13#ibcon#about to read 6, iclass 38, count 2 2006.196.08:27:30.13#ibcon#read 6, iclass 38, count 2 2006.196.08:27:30.13#ibcon#end of sib2, iclass 38, count 2 2006.196.08:27:30.13#ibcon#*after write, iclass 38, count 2 2006.196.08:27:30.13#ibcon#*before return 0, iclass 38, count 2 2006.196.08:27:30.13#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.196.08:27:30.13#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.196.08:27:30.13#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.196.08:27:30.13#ibcon#ireg 7 cls_cnt 0 2006.196.08:27:30.13#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.196.08:27:30.25#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.196.08:27:30.25#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.196.08:27:30.25#ibcon#enter wrdev, iclass 38, count 0 2006.196.08:27:30.25#ibcon#first serial, iclass 38, count 0 2006.196.08:27:30.25#ibcon#enter sib2, iclass 38, count 0 2006.196.08:27:30.25#ibcon#flushed, iclass 38, count 0 2006.196.08:27:30.25#ibcon#about to write, iclass 38, count 0 2006.196.08:27:30.25#ibcon#wrote, iclass 38, count 0 2006.196.08:27:30.25#ibcon#about to read 3, iclass 38, count 0 2006.196.08:27:30.27#ibcon#read 3, iclass 38, count 0 2006.196.08:27:30.27#ibcon#about to read 4, iclass 38, count 0 2006.196.08:27:30.27#ibcon#read 4, iclass 38, count 0 2006.196.08:27:30.27#ibcon#about to read 5, iclass 38, count 0 2006.196.08:27:30.27#ibcon#read 5, iclass 38, count 0 2006.196.08:27:30.27#ibcon#about to read 6, iclass 38, count 0 2006.196.08:27:30.27#ibcon#read 6, iclass 38, count 0 2006.196.08:27:30.27#ibcon#end of sib2, iclass 38, count 0 2006.196.08:27:30.27#ibcon#*mode == 0, iclass 38, count 0 2006.196.08:27:30.27#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.196.08:27:30.27#ibcon#[25=USB\r\n] 2006.196.08:27:30.27#ibcon#*before write, iclass 38, count 0 2006.196.08:27:30.27#ibcon#enter sib2, iclass 38, count 0 2006.196.08:27:30.27#ibcon#flushed, iclass 38, count 0 2006.196.08:27:30.27#ibcon#about to write, iclass 38, count 0 2006.196.08:27:30.27#ibcon#wrote, iclass 38, count 0 2006.196.08:27:30.27#ibcon#about to read 3, iclass 38, count 0 2006.196.08:27:30.30#ibcon#read 3, iclass 38, count 0 2006.196.08:27:30.30#ibcon#about to read 4, iclass 38, count 0 2006.196.08:27:30.30#ibcon#read 4, iclass 38, count 0 2006.196.08:27:30.30#ibcon#about to read 5, iclass 38, count 0 2006.196.08:27:30.30#ibcon#read 5, iclass 38, count 0 2006.196.08:27:30.30#ibcon#about to read 6, iclass 38, count 0 2006.196.08:27:30.30#ibcon#read 6, iclass 38, count 0 2006.196.08:27:30.30#ibcon#end of sib2, iclass 38, count 0 2006.196.08:27:30.30#ibcon#*after write, iclass 38, count 0 2006.196.08:27:30.30#ibcon#*before return 0, iclass 38, count 0 2006.196.08:27:30.30#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.196.08:27:30.30#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.196.08:27:30.30#ibcon#about to clear, iclass 38 cls_cnt 0 2006.196.08:27:30.30#ibcon#cleared, iclass 38 cls_cnt 0 2006.196.08:27:30.30$vc4f8/valo=8,852.99 2006.196.08:27:30.30#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.196.08:27:30.30#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.196.08:27:30.30#ibcon#ireg 17 cls_cnt 0 2006.196.08:27:30.30#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.196.08:27:30.30#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.196.08:27:30.30#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.196.08:27:30.30#ibcon#enter wrdev, iclass 40, count 0 2006.196.08:27:30.30#ibcon#first serial, iclass 40, count 0 2006.196.08:27:30.30#ibcon#enter sib2, iclass 40, count 0 2006.196.08:27:30.30#ibcon#flushed, iclass 40, count 0 2006.196.08:27:30.30#ibcon#about to write, iclass 40, count 0 2006.196.08:27:30.30#ibcon#wrote, iclass 40, count 0 2006.196.08:27:30.30#ibcon#about to read 3, iclass 40, count 0 2006.196.08:27:30.32#ibcon#read 3, iclass 40, count 0 2006.196.08:27:30.32#ibcon#about to read 4, iclass 40, count 0 2006.196.08:27:30.32#ibcon#read 4, iclass 40, count 0 2006.196.08:27:30.32#ibcon#about to read 5, iclass 40, count 0 2006.196.08:27:30.32#ibcon#read 5, iclass 40, count 0 2006.196.08:27:30.32#ibcon#about to read 6, iclass 40, count 0 2006.196.08:27:30.32#ibcon#read 6, iclass 40, count 0 2006.196.08:27:30.32#ibcon#end of sib2, iclass 40, count 0 2006.196.08:27:30.32#ibcon#*mode == 0, iclass 40, count 0 2006.196.08:27:30.32#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.196.08:27:30.32#ibcon#[26=FRQ=08,852.99\r\n] 2006.196.08:27:30.32#ibcon#*before write, iclass 40, count 0 2006.196.08:27:30.32#ibcon#enter sib2, iclass 40, count 0 2006.196.08:27:30.32#ibcon#flushed, iclass 40, count 0 2006.196.08:27:30.32#ibcon#about to write, iclass 40, count 0 2006.196.08:27:30.32#ibcon#wrote, iclass 40, count 0 2006.196.08:27:30.32#ibcon#about to read 3, iclass 40, count 0 2006.196.08:27:30.36#ibcon#read 3, iclass 40, count 0 2006.196.08:27:30.36#ibcon#about to read 4, iclass 40, count 0 2006.196.08:27:30.36#ibcon#read 4, iclass 40, count 0 2006.196.08:27:30.36#ibcon#about to read 5, iclass 40, count 0 2006.196.08:27:30.36#ibcon#read 5, iclass 40, count 0 2006.196.08:27:30.36#ibcon#about to read 6, iclass 40, count 0 2006.196.08:27:30.36#ibcon#read 6, iclass 40, count 0 2006.196.08:27:30.36#ibcon#end of sib2, iclass 40, count 0 2006.196.08:27:30.36#ibcon#*after write, iclass 40, count 0 2006.196.08:27:30.36#ibcon#*before return 0, iclass 40, count 0 2006.196.08:27:30.36#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.196.08:27:30.36#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.196.08:27:30.36#ibcon#about to clear, iclass 40 cls_cnt 0 2006.196.08:27:30.36#ibcon#cleared, iclass 40 cls_cnt 0 2006.196.08:27:30.36$vc4f8/va=8,7 2006.196.08:27:30.36#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.196.08:27:30.36#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.196.08:27:30.36#ibcon#ireg 11 cls_cnt 2 2006.196.08:27:30.36#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.196.08:27:30.42#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.196.08:27:30.42#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.196.08:27:30.42#ibcon#enter wrdev, iclass 4, count 2 2006.196.08:27:30.42#ibcon#first serial, iclass 4, count 2 2006.196.08:27:30.42#ibcon#enter sib2, iclass 4, count 2 2006.196.08:27:30.42#ibcon#flushed, iclass 4, count 2 2006.196.08:27:30.42#ibcon#about to write, iclass 4, count 2 2006.196.08:27:30.42#ibcon#wrote, iclass 4, count 2 2006.196.08:27:30.42#ibcon#about to read 3, iclass 4, count 2 2006.196.08:27:30.44#ibcon#read 3, iclass 4, count 2 2006.196.08:27:30.44#ibcon#about to read 4, iclass 4, count 2 2006.196.08:27:30.44#ibcon#read 4, iclass 4, count 2 2006.196.08:27:30.44#ibcon#about to read 5, iclass 4, count 2 2006.196.08:27:30.44#ibcon#read 5, iclass 4, count 2 2006.196.08:27:30.44#ibcon#about to read 6, iclass 4, count 2 2006.196.08:27:30.44#ibcon#read 6, iclass 4, count 2 2006.196.08:27:30.44#ibcon#end of sib2, iclass 4, count 2 2006.196.08:27:30.44#ibcon#*mode == 0, iclass 4, count 2 2006.196.08:27:30.44#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.196.08:27:30.44#ibcon#[25=AT08-07\r\n] 2006.196.08:27:30.44#ibcon#*before write, iclass 4, count 2 2006.196.08:27:30.44#ibcon#enter sib2, iclass 4, count 2 2006.196.08:27:30.44#ibcon#flushed, iclass 4, count 2 2006.196.08:27:30.44#ibcon#about to write, iclass 4, count 2 2006.196.08:27:30.44#ibcon#wrote, iclass 4, count 2 2006.196.08:27:30.44#ibcon#about to read 3, iclass 4, count 2 2006.196.08:27:30.47#ibcon#read 3, iclass 4, count 2 2006.196.08:27:30.47#ibcon#about to read 4, iclass 4, count 2 2006.196.08:27:30.47#ibcon#read 4, iclass 4, count 2 2006.196.08:27:30.47#ibcon#about to read 5, iclass 4, count 2 2006.196.08:27:30.47#ibcon#read 5, iclass 4, count 2 2006.196.08:27:30.47#ibcon#about to read 6, iclass 4, count 2 2006.196.08:27:30.47#ibcon#read 6, iclass 4, count 2 2006.196.08:27:30.47#ibcon#end of sib2, iclass 4, count 2 2006.196.08:27:30.47#ibcon#*after write, iclass 4, count 2 2006.196.08:27:30.47#ibcon#*before return 0, iclass 4, count 2 2006.196.08:27:30.47#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.196.08:27:30.47#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.196.08:27:30.47#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.196.08:27:30.47#ibcon#ireg 7 cls_cnt 0 2006.196.08:27:30.47#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.196.08:27:30.59#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.196.08:27:30.59#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.196.08:27:30.59#ibcon#enter wrdev, iclass 4, count 0 2006.196.08:27:30.59#ibcon#first serial, iclass 4, count 0 2006.196.08:27:30.59#ibcon#enter sib2, iclass 4, count 0 2006.196.08:27:30.59#ibcon#flushed, iclass 4, count 0 2006.196.08:27:30.59#ibcon#about to write, iclass 4, count 0 2006.196.08:27:30.59#ibcon#wrote, iclass 4, count 0 2006.196.08:27:30.59#ibcon#about to read 3, iclass 4, count 0 2006.196.08:27:30.61#ibcon#read 3, iclass 4, count 0 2006.196.08:27:30.61#ibcon#about to read 4, iclass 4, count 0 2006.196.08:27:30.61#ibcon#read 4, iclass 4, count 0 2006.196.08:27:30.61#ibcon#about to read 5, iclass 4, count 0 2006.196.08:27:30.61#ibcon#read 5, iclass 4, count 0 2006.196.08:27:30.61#ibcon#about to read 6, iclass 4, count 0 2006.196.08:27:30.61#ibcon#read 6, iclass 4, count 0 2006.196.08:27:30.61#ibcon#end of sib2, iclass 4, count 0 2006.196.08:27:30.61#ibcon#*mode == 0, iclass 4, count 0 2006.196.08:27:30.61#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.196.08:27:30.61#ibcon#[25=USB\r\n] 2006.196.08:27:30.61#ibcon#*before write, iclass 4, count 0 2006.196.08:27:30.61#ibcon#enter sib2, iclass 4, count 0 2006.196.08:27:30.61#ibcon#flushed, iclass 4, count 0 2006.196.08:27:30.61#ibcon#about to write, iclass 4, count 0 2006.196.08:27:30.61#ibcon#wrote, iclass 4, count 0 2006.196.08:27:30.61#ibcon#about to read 3, iclass 4, count 0 2006.196.08:27:30.64#ibcon#read 3, iclass 4, count 0 2006.196.08:27:30.64#ibcon#about to read 4, iclass 4, count 0 2006.196.08:27:30.64#ibcon#read 4, iclass 4, count 0 2006.196.08:27:30.64#ibcon#about to read 5, iclass 4, count 0 2006.196.08:27:30.64#ibcon#read 5, iclass 4, count 0 2006.196.08:27:30.64#ibcon#about to read 6, iclass 4, count 0 2006.196.08:27:30.64#ibcon#read 6, iclass 4, count 0 2006.196.08:27:30.64#ibcon#end of sib2, iclass 4, count 0 2006.196.08:27:30.64#ibcon#*after write, iclass 4, count 0 2006.196.08:27:30.64#ibcon#*before return 0, iclass 4, count 0 2006.196.08:27:30.64#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.196.08:27:30.64#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.196.08:27:30.64#ibcon#about to clear, iclass 4 cls_cnt 0 2006.196.08:27:30.64#ibcon#cleared, iclass 4 cls_cnt 0 2006.196.08:27:30.64$vc4f8/vblo=1,632.99 2006.196.08:27:30.64#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.196.08:27:30.64#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.196.08:27:30.64#ibcon#ireg 17 cls_cnt 0 2006.196.08:27:30.64#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.196.08:27:30.64#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.196.08:27:30.64#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.196.08:27:30.64#ibcon#enter wrdev, iclass 6, count 0 2006.196.08:27:30.64#ibcon#first serial, iclass 6, count 0 2006.196.08:27:30.64#ibcon#enter sib2, iclass 6, count 0 2006.196.08:27:30.64#ibcon#flushed, iclass 6, count 0 2006.196.08:27:30.64#ibcon#about to write, iclass 6, count 0 2006.196.08:27:30.64#ibcon#wrote, iclass 6, count 0 2006.196.08:27:30.64#ibcon#about to read 3, iclass 6, count 0 2006.196.08:27:30.66#ibcon#read 3, iclass 6, count 0 2006.196.08:27:30.66#ibcon#about to read 4, iclass 6, count 0 2006.196.08:27:30.66#ibcon#read 4, iclass 6, count 0 2006.196.08:27:30.66#ibcon#about to read 5, iclass 6, count 0 2006.196.08:27:30.66#ibcon#read 5, iclass 6, count 0 2006.196.08:27:30.66#ibcon#about to read 6, iclass 6, count 0 2006.196.08:27:30.66#ibcon#read 6, iclass 6, count 0 2006.196.08:27:30.66#ibcon#end of sib2, iclass 6, count 0 2006.196.08:27:30.66#ibcon#*mode == 0, iclass 6, count 0 2006.196.08:27:30.66#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.196.08:27:30.66#ibcon#[28=FRQ=01,632.99\r\n] 2006.196.08:27:30.66#ibcon#*before write, iclass 6, count 0 2006.196.08:27:30.66#ibcon#enter sib2, iclass 6, count 0 2006.196.08:27:30.66#ibcon#flushed, iclass 6, count 0 2006.196.08:27:30.66#ibcon#about to write, iclass 6, count 0 2006.196.08:27:30.66#ibcon#wrote, iclass 6, count 0 2006.196.08:27:30.66#ibcon#about to read 3, iclass 6, count 0 2006.196.08:27:30.70#ibcon#read 3, iclass 6, count 0 2006.196.08:27:30.70#ibcon#about to read 4, iclass 6, count 0 2006.196.08:27:30.70#ibcon#read 4, iclass 6, count 0 2006.196.08:27:30.70#ibcon#about to read 5, iclass 6, count 0 2006.196.08:27:30.70#ibcon#read 5, iclass 6, count 0 2006.196.08:27:30.70#ibcon#about to read 6, iclass 6, count 0 2006.196.08:27:30.70#ibcon#read 6, iclass 6, count 0 2006.196.08:27:30.70#ibcon#end of sib2, iclass 6, count 0 2006.196.08:27:30.70#ibcon#*after write, iclass 6, count 0 2006.196.08:27:30.70#ibcon#*before return 0, iclass 6, count 0 2006.196.08:27:30.70#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.196.08:27:30.70#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.196.08:27:30.70#ibcon#about to clear, iclass 6 cls_cnt 0 2006.196.08:27:30.70#ibcon#cleared, iclass 6 cls_cnt 0 2006.196.08:27:30.70$vc4f8/vb=1,4 2006.196.08:27:30.70#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.196.08:27:30.70#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.196.08:27:30.70#ibcon#ireg 11 cls_cnt 2 2006.196.08:27:30.70#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.196.08:27:30.70#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.196.08:27:30.70#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.196.08:27:30.70#ibcon#enter wrdev, iclass 10, count 2 2006.196.08:27:30.70#ibcon#first serial, iclass 10, count 2 2006.196.08:27:30.70#ibcon#enter sib2, iclass 10, count 2 2006.196.08:27:30.70#ibcon#flushed, iclass 10, count 2 2006.196.08:27:30.70#ibcon#about to write, iclass 10, count 2 2006.196.08:27:30.70#ibcon#wrote, iclass 10, count 2 2006.196.08:27:30.70#ibcon#about to read 3, iclass 10, count 2 2006.196.08:27:30.72#ibcon#read 3, iclass 10, count 2 2006.196.08:27:30.72#ibcon#about to read 4, iclass 10, count 2 2006.196.08:27:30.72#ibcon#read 4, iclass 10, count 2 2006.196.08:27:30.72#ibcon#about to read 5, iclass 10, count 2 2006.196.08:27:30.72#ibcon#read 5, iclass 10, count 2 2006.196.08:27:30.72#ibcon#about to read 6, iclass 10, count 2 2006.196.08:27:30.72#ibcon#read 6, iclass 10, count 2 2006.196.08:27:30.72#ibcon#end of sib2, iclass 10, count 2 2006.196.08:27:30.72#ibcon#*mode == 0, iclass 10, count 2 2006.196.08:27:30.72#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.196.08:27:30.72#ibcon#[27=AT01-04\r\n] 2006.196.08:27:30.72#ibcon#*before write, iclass 10, count 2 2006.196.08:27:30.72#ibcon#enter sib2, iclass 10, count 2 2006.196.08:27:30.72#ibcon#flushed, iclass 10, count 2 2006.196.08:27:30.72#ibcon#about to write, iclass 10, count 2 2006.196.08:27:30.72#ibcon#wrote, iclass 10, count 2 2006.196.08:27:30.72#ibcon#about to read 3, iclass 10, count 2 2006.196.08:27:30.75#ibcon#read 3, iclass 10, count 2 2006.196.08:27:30.75#ibcon#about to read 4, iclass 10, count 2 2006.196.08:27:30.75#ibcon#read 4, iclass 10, count 2 2006.196.08:27:30.75#ibcon#about to read 5, iclass 10, count 2 2006.196.08:27:30.75#ibcon#read 5, iclass 10, count 2 2006.196.08:27:30.75#ibcon#about to read 6, iclass 10, count 2 2006.196.08:27:30.75#ibcon#read 6, iclass 10, count 2 2006.196.08:27:30.75#ibcon#end of sib2, iclass 10, count 2 2006.196.08:27:30.75#ibcon#*after write, iclass 10, count 2 2006.196.08:27:30.75#ibcon#*before return 0, iclass 10, count 2 2006.196.08:27:30.75#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.196.08:27:30.75#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.196.08:27:30.75#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.196.08:27:30.75#ibcon#ireg 7 cls_cnt 0 2006.196.08:27:30.75#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.196.08:27:30.87#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.196.08:27:30.87#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.196.08:27:30.87#ibcon#enter wrdev, iclass 10, count 0 2006.196.08:27:30.87#ibcon#first serial, iclass 10, count 0 2006.196.08:27:30.87#ibcon#enter sib2, iclass 10, count 0 2006.196.08:27:30.87#ibcon#flushed, iclass 10, count 0 2006.196.08:27:30.87#ibcon#about to write, iclass 10, count 0 2006.196.08:27:30.87#ibcon#wrote, iclass 10, count 0 2006.196.08:27:30.87#ibcon#about to read 3, iclass 10, count 0 2006.196.08:27:30.89#ibcon#read 3, iclass 10, count 0 2006.196.08:27:30.89#ibcon#about to read 4, iclass 10, count 0 2006.196.08:27:30.89#ibcon#read 4, iclass 10, count 0 2006.196.08:27:30.89#ibcon#about to read 5, iclass 10, count 0 2006.196.08:27:30.89#ibcon#read 5, iclass 10, count 0 2006.196.08:27:30.89#ibcon#about to read 6, iclass 10, count 0 2006.196.08:27:30.89#ibcon#read 6, iclass 10, count 0 2006.196.08:27:30.89#ibcon#end of sib2, iclass 10, count 0 2006.196.08:27:30.89#ibcon#*mode == 0, iclass 10, count 0 2006.196.08:27:30.89#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.196.08:27:30.89#ibcon#[27=USB\r\n] 2006.196.08:27:30.89#ibcon#*before write, iclass 10, count 0 2006.196.08:27:30.89#ibcon#enter sib2, iclass 10, count 0 2006.196.08:27:30.89#ibcon#flushed, iclass 10, count 0 2006.196.08:27:30.89#ibcon#about to write, iclass 10, count 0 2006.196.08:27:30.89#ibcon#wrote, iclass 10, count 0 2006.196.08:27:30.89#ibcon#about to read 3, iclass 10, count 0 2006.196.08:27:30.92#ibcon#read 3, iclass 10, count 0 2006.196.08:27:30.92#ibcon#about to read 4, iclass 10, count 0 2006.196.08:27:30.92#ibcon#read 4, iclass 10, count 0 2006.196.08:27:30.92#ibcon#about to read 5, iclass 10, count 0 2006.196.08:27:30.92#ibcon#read 5, iclass 10, count 0 2006.196.08:27:30.92#ibcon#about to read 6, iclass 10, count 0 2006.196.08:27:30.92#ibcon#read 6, iclass 10, count 0 2006.196.08:27:30.92#ibcon#end of sib2, iclass 10, count 0 2006.196.08:27:30.92#ibcon#*after write, iclass 10, count 0 2006.196.08:27:30.92#ibcon#*before return 0, iclass 10, count 0 2006.196.08:27:30.92#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.196.08:27:30.92#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.196.08:27:30.92#ibcon#about to clear, iclass 10 cls_cnt 0 2006.196.08:27:30.92#ibcon#cleared, iclass 10 cls_cnt 0 2006.196.08:27:30.92$vc4f8/vblo=2,640.99 2006.196.08:27:30.92#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.196.08:27:30.92#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.196.08:27:30.92#ibcon#ireg 17 cls_cnt 0 2006.196.08:27:30.92#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.196.08:27:30.92#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.196.08:27:30.92#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.196.08:27:30.92#ibcon#enter wrdev, iclass 12, count 0 2006.196.08:27:30.92#ibcon#first serial, iclass 12, count 0 2006.196.08:27:30.92#ibcon#enter sib2, iclass 12, count 0 2006.196.08:27:30.92#ibcon#flushed, iclass 12, count 0 2006.196.08:27:30.92#ibcon#about to write, iclass 12, count 0 2006.196.08:27:30.92#ibcon#wrote, iclass 12, count 0 2006.196.08:27:30.92#ibcon#about to read 3, iclass 12, count 0 2006.196.08:27:30.94#ibcon#read 3, iclass 12, count 0 2006.196.08:27:30.94#ibcon#about to read 4, iclass 12, count 0 2006.196.08:27:30.94#ibcon#read 4, iclass 12, count 0 2006.196.08:27:30.94#ibcon#about to read 5, iclass 12, count 0 2006.196.08:27:30.94#ibcon#read 5, iclass 12, count 0 2006.196.08:27:30.94#ibcon#about to read 6, iclass 12, count 0 2006.196.08:27:30.94#ibcon#read 6, iclass 12, count 0 2006.196.08:27:30.94#ibcon#end of sib2, iclass 12, count 0 2006.196.08:27:30.94#ibcon#*mode == 0, iclass 12, count 0 2006.196.08:27:30.94#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.196.08:27:30.94#ibcon#[28=FRQ=02,640.99\r\n] 2006.196.08:27:30.94#ibcon#*before write, iclass 12, count 0 2006.196.08:27:30.94#ibcon#enter sib2, iclass 12, count 0 2006.196.08:27:30.94#ibcon#flushed, iclass 12, count 0 2006.196.08:27:30.94#ibcon#about to write, iclass 12, count 0 2006.196.08:27:30.94#ibcon#wrote, iclass 12, count 0 2006.196.08:27:30.94#ibcon#about to read 3, iclass 12, count 0 2006.196.08:27:30.98#ibcon#read 3, iclass 12, count 0 2006.196.08:27:30.98#ibcon#about to read 4, iclass 12, count 0 2006.196.08:27:30.98#ibcon#read 4, iclass 12, count 0 2006.196.08:27:30.98#ibcon#about to read 5, iclass 12, count 0 2006.196.08:27:30.98#ibcon#read 5, iclass 12, count 0 2006.196.08:27:30.98#ibcon#about to read 6, iclass 12, count 0 2006.196.08:27:30.98#ibcon#read 6, iclass 12, count 0 2006.196.08:27:30.98#ibcon#end of sib2, iclass 12, count 0 2006.196.08:27:30.98#ibcon#*after write, iclass 12, count 0 2006.196.08:27:30.98#ibcon#*before return 0, iclass 12, count 0 2006.196.08:27:30.98#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.196.08:27:30.98#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.196.08:27:30.98#ibcon#about to clear, iclass 12 cls_cnt 0 2006.196.08:27:30.98#ibcon#cleared, iclass 12 cls_cnt 0 2006.196.08:27:30.98$vc4f8/vb=2,4 2006.196.08:27:30.98#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.196.08:27:30.98#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.196.08:27:30.98#ibcon#ireg 11 cls_cnt 2 2006.196.08:27:30.98#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.196.08:27:31.04#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.196.08:27:31.04#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.196.08:27:31.04#ibcon#enter wrdev, iclass 14, count 2 2006.196.08:27:31.04#ibcon#first serial, iclass 14, count 2 2006.196.08:27:31.04#ibcon#enter sib2, iclass 14, count 2 2006.196.08:27:31.04#ibcon#flushed, iclass 14, count 2 2006.196.08:27:31.04#ibcon#about to write, iclass 14, count 2 2006.196.08:27:31.04#ibcon#wrote, iclass 14, count 2 2006.196.08:27:31.04#ibcon#about to read 3, iclass 14, count 2 2006.196.08:27:31.06#ibcon#read 3, iclass 14, count 2 2006.196.08:27:31.06#ibcon#about to read 4, iclass 14, count 2 2006.196.08:27:31.06#ibcon#read 4, iclass 14, count 2 2006.196.08:27:31.06#ibcon#about to read 5, iclass 14, count 2 2006.196.08:27:31.06#ibcon#read 5, iclass 14, count 2 2006.196.08:27:31.06#ibcon#about to read 6, iclass 14, count 2 2006.196.08:27:31.06#ibcon#read 6, iclass 14, count 2 2006.196.08:27:31.06#ibcon#end of sib2, iclass 14, count 2 2006.196.08:27:31.06#ibcon#*mode == 0, iclass 14, count 2 2006.196.08:27:31.06#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.196.08:27:31.06#ibcon#[27=AT02-04\r\n] 2006.196.08:27:31.06#ibcon#*before write, iclass 14, count 2 2006.196.08:27:31.06#ibcon#enter sib2, iclass 14, count 2 2006.196.08:27:31.06#ibcon#flushed, iclass 14, count 2 2006.196.08:27:31.06#ibcon#about to write, iclass 14, count 2 2006.196.08:27:31.06#ibcon#wrote, iclass 14, count 2 2006.196.08:27:31.06#ibcon#about to read 3, iclass 14, count 2 2006.196.08:27:31.09#ibcon#read 3, iclass 14, count 2 2006.196.08:27:31.09#ibcon#about to read 4, iclass 14, count 2 2006.196.08:27:31.09#ibcon#read 4, iclass 14, count 2 2006.196.08:27:31.09#ibcon#about to read 5, iclass 14, count 2 2006.196.08:27:31.09#ibcon#read 5, iclass 14, count 2 2006.196.08:27:31.09#ibcon#about to read 6, iclass 14, count 2 2006.196.08:27:31.09#ibcon#read 6, iclass 14, count 2 2006.196.08:27:31.09#ibcon#end of sib2, iclass 14, count 2 2006.196.08:27:31.09#ibcon#*after write, iclass 14, count 2 2006.196.08:27:31.09#ibcon#*before return 0, iclass 14, count 2 2006.196.08:27:31.09#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.196.08:27:31.09#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.196.08:27:31.09#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.196.08:27:31.09#ibcon#ireg 7 cls_cnt 0 2006.196.08:27:31.09#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.196.08:27:31.21#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.196.08:27:31.21#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.196.08:27:31.21#ibcon#enter wrdev, iclass 14, count 0 2006.196.08:27:31.21#ibcon#first serial, iclass 14, count 0 2006.196.08:27:31.21#ibcon#enter sib2, iclass 14, count 0 2006.196.08:27:31.21#ibcon#flushed, iclass 14, count 0 2006.196.08:27:31.21#ibcon#about to write, iclass 14, count 0 2006.196.08:27:31.21#ibcon#wrote, iclass 14, count 0 2006.196.08:27:31.21#ibcon#about to read 3, iclass 14, count 0 2006.196.08:27:31.24#ibcon#read 3, iclass 14, count 0 2006.196.08:27:31.24#ibcon#about to read 4, iclass 14, count 0 2006.196.08:27:31.24#ibcon#read 4, iclass 14, count 0 2006.196.08:27:31.24#ibcon#about to read 5, iclass 14, count 0 2006.196.08:27:31.24#ibcon#read 5, iclass 14, count 0 2006.196.08:27:31.24#ibcon#about to read 6, iclass 14, count 0 2006.196.08:27:31.24#ibcon#read 6, iclass 14, count 0 2006.196.08:27:31.24#ibcon#end of sib2, iclass 14, count 0 2006.196.08:27:31.24#ibcon#*mode == 0, iclass 14, count 0 2006.196.08:27:31.24#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.196.08:27:31.24#ibcon#[27=USB\r\n] 2006.196.08:27:31.24#ibcon#*before write, iclass 14, count 0 2006.196.08:27:31.24#ibcon#enter sib2, iclass 14, count 0 2006.196.08:27:31.24#ibcon#flushed, iclass 14, count 0 2006.196.08:27:31.24#ibcon#about to write, iclass 14, count 0 2006.196.08:27:31.24#ibcon#wrote, iclass 14, count 0 2006.196.08:27:31.24#ibcon#about to read 3, iclass 14, count 0 2006.196.08:27:31.27#ibcon#read 3, iclass 14, count 0 2006.196.08:27:31.27#ibcon#about to read 4, iclass 14, count 0 2006.196.08:27:31.27#ibcon#read 4, iclass 14, count 0 2006.196.08:27:31.27#ibcon#about to read 5, iclass 14, count 0 2006.196.08:27:31.27#ibcon#read 5, iclass 14, count 0 2006.196.08:27:31.27#ibcon#about to read 6, iclass 14, count 0 2006.196.08:27:31.27#ibcon#read 6, iclass 14, count 0 2006.196.08:27:31.27#ibcon#end of sib2, iclass 14, count 0 2006.196.08:27:31.27#ibcon#*after write, iclass 14, count 0 2006.196.08:27:31.27#ibcon#*before return 0, iclass 14, count 0 2006.196.08:27:31.27#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.196.08:27:31.27#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.196.08:27:31.27#ibcon#about to clear, iclass 14 cls_cnt 0 2006.196.08:27:31.27#ibcon#cleared, iclass 14 cls_cnt 0 2006.196.08:27:31.27$vc4f8/vblo=3,656.99 2006.196.08:27:31.27#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.196.08:27:31.27#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.196.08:27:31.27#ibcon#ireg 17 cls_cnt 0 2006.196.08:27:31.27#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.196.08:27:31.27#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.196.08:27:31.27#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.196.08:27:31.27#ibcon#enter wrdev, iclass 16, count 0 2006.196.08:27:31.27#ibcon#first serial, iclass 16, count 0 2006.196.08:27:31.27#ibcon#enter sib2, iclass 16, count 0 2006.196.08:27:31.27#ibcon#flushed, iclass 16, count 0 2006.196.08:27:31.27#ibcon#about to write, iclass 16, count 0 2006.196.08:27:31.27#ibcon#wrote, iclass 16, count 0 2006.196.08:27:31.27#ibcon#about to read 3, iclass 16, count 0 2006.196.08:27:31.29#ibcon#read 3, iclass 16, count 0 2006.196.08:27:31.29#ibcon#about to read 4, iclass 16, count 0 2006.196.08:27:31.29#ibcon#read 4, iclass 16, count 0 2006.196.08:27:31.29#ibcon#about to read 5, iclass 16, count 0 2006.196.08:27:31.29#ibcon#read 5, iclass 16, count 0 2006.196.08:27:31.29#ibcon#about to read 6, iclass 16, count 0 2006.196.08:27:31.29#ibcon#read 6, iclass 16, count 0 2006.196.08:27:31.29#ibcon#end of sib2, iclass 16, count 0 2006.196.08:27:31.29#ibcon#*mode == 0, iclass 16, count 0 2006.196.08:27:31.29#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.196.08:27:31.29#ibcon#[28=FRQ=03,656.99\r\n] 2006.196.08:27:31.29#ibcon#*before write, iclass 16, count 0 2006.196.08:27:31.29#ibcon#enter sib2, iclass 16, count 0 2006.196.08:27:31.29#ibcon#flushed, iclass 16, count 0 2006.196.08:27:31.29#ibcon#about to write, iclass 16, count 0 2006.196.08:27:31.29#ibcon#wrote, iclass 16, count 0 2006.196.08:27:31.29#ibcon#about to read 3, iclass 16, count 0 2006.196.08:27:31.33#ibcon#read 3, iclass 16, count 0 2006.196.08:27:31.33#ibcon#about to read 4, iclass 16, count 0 2006.196.08:27:31.33#ibcon#read 4, iclass 16, count 0 2006.196.08:27:31.33#ibcon#about to read 5, iclass 16, count 0 2006.196.08:27:31.33#ibcon#read 5, iclass 16, count 0 2006.196.08:27:31.33#ibcon#about to read 6, iclass 16, count 0 2006.196.08:27:31.33#ibcon#read 6, iclass 16, count 0 2006.196.08:27:31.33#ibcon#end of sib2, iclass 16, count 0 2006.196.08:27:31.33#ibcon#*after write, iclass 16, count 0 2006.196.08:27:31.33#ibcon#*before return 0, iclass 16, count 0 2006.196.08:27:31.33#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.196.08:27:31.33#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.196.08:27:31.33#ibcon#about to clear, iclass 16 cls_cnt 0 2006.196.08:27:31.33#ibcon#cleared, iclass 16 cls_cnt 0 2006.196.08:27:31.33$vc4f8/vb=3,4 2006.196.08:27:31.33#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.196.08:27:31.33#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.196.08:27:31.33#ibcon#ireg 11 cls_cnt 2 2006.196.08:27:31.33#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.196.08:27:31.39#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.196.08:27:31.39#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.196.08:27:31.39#ibcon#enter wrdev, iclass 18, count 2 2006.196.08:27:31.39#ibcon#first serial, iclass 18, count 2 2006.196.08:27:31.39#ibcon#enter sib2, iclass 18, count 2 2006.196.08:27:31.39#ibcon#flushed, iclass 18, count 2 2006.196.08:27:31.39#ibcon#about to write, iclass 18, count 2 2006.196.08:27:31.39#ibcon#wrote, iclass 18, count 2 2006.196.08:27:31.39#ibcon#about to read 3, iclass 18, count 2 2006.196.08:27:31.41#ibcon#read 3, iclass 18, count 2 2006.196.08:27:31.41#ibcon#about to read 4, iclass 18, count 2 2006.196.08:27:31.41#ibcon#read 4, iclass 18, count 2 2006.196.08:27:31.41#ibcon#about to read 5, iclass 18, count 2 2006.196.08:27:31.41#ibcon#read 5, iclass 18, count 2 2006.196.08:27:31.41#ibcon#about to read 6, iclass 18, count 2 2006.196.08:27:31.41#ibcon#read 6, iclass 18, count 2 2006.196.08:27:31.41#ibcon#end of sib2, iclass 18, count 2 2006.196.08:27:31.41#ibcon#*mode == 0, iclass 18, count 2 2006.196.08:27:31.41#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.196.08:27:31.41#ibcon#[27=AT03-04\r\n] 2006.196.08:27:31.41#ibcon#*before write, iclass 18, count 2 2006.196.08:27:31.41#ibcon#enter sib2, iclass 18, count 2 2006.196.08:27:31.41#ibcon#flushed, iclass 18, count 2 2006.196.08:27:31.41#ibcon#about to write, iclass 18, count 2 2006.196.08:27:31.41#ibcon#wrote, iclass 18, count 2 2006.196.08:27:31.41#ibcon#about to read 3, iclass 18, count 2 2006.196.08:27:31.44#ibcon#read 3, iclass 18, count 2 2006.196.08:27:31.44#ibcon#about to read 4, iclass 18, count 2 2006.196.08:27:31.44#ibcon#read 4, iclass 18, count 2 2006.196.08:27:31.44#ibcon#about to read 5, iclass 18, count 2 2006.196.08:27:31.44#ibcon#read 5, iclass 18, count 2 2006.196.08:27:31.44#ibcon#about to read 6, iclass 18, count 2 2006.196.08:27:31.44#ibcon#read 6, iclass 18, count 2 2006.196.08:27:31.44#ibcon#end of sib2, iclass 18, count 2 2006.196.08:27:31.44#ibcon#*after write, iclass 18, count 2 2006.196.08:27:31.44#ibcon#*before return 0, iclass 18, count 2 2006.196.08:27:31.44#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.196.08:27:31.44#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.196.08:27:31.44#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.196.08:27:31.44#ibcon#ireg 7 cls_cnt 0 2006.196.08:27:31.44#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.196.08:27:31.56#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.196.08:27:31.56#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.196.08:27:31.56#ibcon#enter wrdev, iclass 18, count 0 2006.196.08:27:31.56#ibcon#first serial, iclass 18, count 0 2006.196.08:27:31.56#ibcon#enter sib2, iclass 18, count 0 2006.196.08:27:31.56#ibcon#flushed, iclass 18, count 0 2006.196.08:27:31.56#ibcon#about to write, iclass 18, count 0 2006.196.08:27:31.56#ibcon#wrote, iclass 18, count 0 2006.196.08:27:31.56#ibcon#about to read 3, iclass 18, count 0 2006.196.08:27:31.58#ibcon#read 3, iclass 18, count 0 2006.196.08:27:31.58#ibcon#about to read 4, iclass 18, count 0 2006.196.08:27:31.58#ibcon#read 4, iclass 18, count 0 2006.196.08:27:31.58#ibcon#about to read 5, iclass 18, count 0 2006.196.08:27:31.58#ibcon#read 5, iclass 18, count 0 2006.196.08:27:31.58#ibcon#about to read 6, iclass 18, count 0 2006.196.08:27:31.58#ibcon#read 6, iclass 18, count 0 2006.196.08:27:31.58#ibcon#end of sib2, iclass 18, count 0 2006.196.08:27:31.58#ibcon#*mode == 0, iclass 18, count 0 2006.196.08:27:31.58#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.196.08:27:31.58#ibcon#[27=USB\r\n] 2006.196.08:27:31.58#ibcon#*before write, iclass 18, count 0 2006.196.08:27:31.58#ibcon#enter sib2, iclass 18, count 0 2006.196.08:27:31.58#ibcon#flushed, iclass 18, count 0 2006.196.08:27:31.58#ibcon#about to write, iclass 18, count 0 2006.196.08:27:31.58#ibcon#wrote, iclass 18, count 0 2006.196.08:27:31.58#ibcon#about to read 3, iclass 18, count 0 2006.196.08:27:31.61#ibcon#read 3, iclass 18, count 0 2006.196.08:27:31.61#ibcon#about to read 4, iclass 18, count 0 2006.196.08:27:31.61#ibcon#read 4, iclass 18, count 0 2006.196.08:27:31.61#ibcon#about to read 5, iclass 18, count 0 2006.196.08:27:31.61#ibcon#read 5, iclass 18, count 0 2006.196.08:27:31.61#ibcon#about to read 6, iclass 18, count 0 2006.196.08:27:31.61#ibcon#read 6, iclass 18, count 0 2006.196.08:27:31.61#ibcon#end of sib2, iclass 18, count 0 2006.196.08:27:31.61#ibcon#*after write, iclass 18, count 0 2006.196.08:27:31.61#ibcon#*before return 0, iclass 18, count 0 2006.196.08:27:31.61#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.196.08:27:31.61#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.196.08:27:31.61#ibcon#about to clear, iclass 18 cls_cnt 0 2006.196.08:27:31.61#ibcon#cleared, iclass 18 cls_cnt 0 2006.196.08:27:31.61$vc4f8/vblo=4,712.99 2006.196.08:27:31.61#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.196.08:27:31.61#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.196.08:27:31.61#ibcon#ireg 17 cls_cnt 0 2006.196.08:27:31.61#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.196.08:27:31.61#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.196.08:27:31.61#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.196.08:27:31.61#ibcon#enter wrdev, iclass 20, count 0 2006.196.08:27:31.61#ibcon#first serial, iclass 20, count 0 2006.196.08:27:31.61#ibcon#enter sib2, iclass 20, count 0 2006.196.08:27:31.61#ibcon#flushed, iclass 20, count 0 2006.196.08:27:31.61#ibcon#about to write, iclass 20, count 0 2006.196.08:27:31.61#ibcon#wrote, iclass 20, count 0 2006.196.08:27:31.61#ibcon#about to read 3, iclass 20, count 0 2006.196.08:27:31.63#ibcon#read 3, iclass 20, count 0 2006.196.08:27:31.63#ibcon#about to read 4, iclass 20, count 0 2006.196.08:27:31.63#ibcon#read 4, iclass 20, count 0 2006.196.08:27:31.63#ibcon#about to read 5, iclass 20, count 0 2006.196.08:27:31.63#ibcon#read 5, iclass 20, count 0 2006.196.08:27:31.63#ibcon#about to read 6, iclass 20, count 0 2006.196.08:27:31.63#ibcon#read 6, iclass 20, count 0 2006.196.08:27:31.63#ibcon#end of sib2, iclass 20, count 0 2006.196.08:27:31.63#ibcon#*mode == 0, iclass 20, count 0 2006.196.08:27:31.63#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.196.08:27:31.63#ibcon#[28=FRQ=04,712.99\r\n] 2006.196.08:27:31.63#ibcon#*before write, iclass 20, count 0 2006.196.08:27:31.63#ibcon#enter sib2, iclass 20, count 0 2006.196.08:27:31.63#ibcon#flushed, iclass 20, count 0 2006.196.08:27:31.63#ibcon#about to write, iclass 20, count 0 2006.196.08:27:31.63#ibcon#wrote, iclass 20, count 0 2006.196.08:27:31.63#ibcon#about to read 3, iclass 20, count 0 2006.196.08:27:31.67#ibcon#read 3, iclass 20, count 0 2006.196.08:27:31.67#ibcon#about to read 4, iclass 20, count 0 2006.196.08:27:31.67#ibcon#read 4, iclass 20, count 0 2006.196.08:27:31.67#ibcon#about to read 5, iclass 20, count 0 2006.196.08:27:31.67#ibcon#read 5, iclass 20, count 0 2006.196.08:27:31.67#ibcon#about to read 6, iclass 20, count 0 2006.196.08:27:31.67#ibcon#read 6, iclass 20, count 0 2006.196.08:27:31.67#ibcon#end of sib2, iclass 20, count 0 2006.196.08:27:31.67#ibcon#*after write, iclass 20, count 0 2006.196.08:27:31.67#ibcon#*before return 0, iclass 20, count 0 2006.196.08:27:31.67#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.196.08:27:31.67#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.196.08:27:31.67#ibcon#about to clear, iclass 20 cls_cnt 0 2006.196.08:27:31.67#ibcon#cleared, iclass 20 cls_cnt 0 2006.196.08:27:31.67$vc4f8/vb=4,4 2006.196.08:27:31.67#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.196.08:27:31.67#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.196.08:27:31.67#ibcon#ireg 11 cls_cnt 2 2006.196.08:27:31.67#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.196.08:27:31.73#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.196.08:27:31.73#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.196.08:27:31.73#ibcon#enter wrdev, iclass 22, count 2 2006.196.08:27:31.73#ibcon#first serial, iclass 22, count 2 2006.196.08:27:31.73#ibcon#enter sib2, iclass 22, count 2 2006.196.08:27:31.73#ibcon#flushed, iclass 22, count 2 2006.196.08:27:31.73#ibcon#about to write, iclass 22, count 2 2006.196.08:27:31.73#ibcon#wrote, iclass 22, count 2 2006.196.08:27:31.73#ibcon#about to read 3, iclass 22, count 2 2006.196.08:27:31.75#ibcon#read 3, iclass 22, count 2 2006.196.08:27:31.75#ibcon#about to read 4, iclass 22, count 2 2006.196.08:27:31.75#ibcon#read 4, iclass 22, count 2 2006.196.08:27:31.75#ibcon#about to read 5, iclass 22, count 2 2006.196.08:27:31.75#ibcon#read 5, iclass 22, count 2 2006.196.08:27:31.75#ibcon#about to read 6, iclass 22, count 2 2006.196.08:27:31.75#ibcon#read 6, iclass 22, count 2 2006.196.08:27:31.75#ibcon#end of sib2, iclass 22, count 2 2006.196.08:27:31.75#ibcon#*mode == 0, iclass 22, count 2 2006.196.08:27:31.75#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.196.08:27:31.75#ibcon#[27=AT04-04\r\n] 2006.196.08:27:31.75#ibcon#*before write, iclass 22, count 2 2006.196.08:27:31.75#ibcon#enter sib2, iclass 22, count 2 2006.196.08:27:31.75#ibcon#flushed, iclass 22, count 2 2006.196.08:27:31.75#ibcon#about to write, iclass 22, count 2 2006.196.08:27:31.75#ibcon#wrote, iclass 22, count 2 2006.196.08:27:31.75#ibcon#about to read 3, iclass 22, count 2 2006.196.08:27:31.78#ibcon#read 3, iclass 22, count 2 2006.196.08:27:31.78#ibcon#about to read 4, iclass 22, count 2 2006.196.08:27:31.78#ibcon#read 4, iclass 22, count 2 2006.196.08:27:31.78#ibcon#about to read 5, iclass 22, count 2 2006.196.08:27:31.78#ibcon#read 5, iclass 22, count 2 2006.196.08:27:31.78#ibcon#about to read 6, iclass 22, count 2 2006.196.08:27:31.78#ibcon#read 6, iclass 22, count 2 2006.196.08:27:31.78#ibcon#end of sib2, iclass 22, count 2 2006.196.08:27:31.78#ibcon#*after write, iclass 22, count 2 2006.196.08:27:31.78#ibcon#*before return 0, iclass 22, count 2 2006.196.08:27:31.78#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.196.08:27:31.78#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.196.08:27:31.78#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.196.08:27:31.78#ibcon#ireg 7 cls_cnt 0 2006.196.08:27:31.78#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.196.08:27:31.90#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.196.08:27:31.90#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.196.08:27:31.90#ibcon#enter wrdev, iclass 22, count 0 2006.196.08:27:31.90#ibcon#first serial, iclass 22, count 0 2006.196.08:27:31.90#ibcon#enter sib2, iclass 22, count 0 2006.196.08:27:31.90#ibcon#flushed, iclass 22, count 0 2006.196.08:27:31.90#ibcon#about to write, iclass 22, count 0 2006.196.08:27:31.90#ibcon#wrote, iclass 22, count 0 2006.196.08:27:31.90#ibcon#about to read 3, iclass 22, count 0 2006.196.08:27:31.92#ibcon#read 3, iclass 22, count 0 2006.196.08:27:31.92#ibcon#about to read 4, iclass 22, count 0 2006.196.08:27:31.92#ibcon#read 4, iclass 22, count 0 2006.196.08:27:31.92#ibcon#about to read 5, iclass 22, count 0 2006.196.08:27:31.92#ibcon#read 5, iclass 22, count 0 2006.196.08:27:31.92#ibcon#about to read 6, iclass 22, count 0 2006.196.08:27:31.92#ibcon#read 6, iclass 22, count 0 2006.196.08:27:31.92#ibcon#end of sib2, iclass 22, count 0 2006.196.08:27:31.92#ibcon#*mode == 0, iclass 22, count 0 2006.196.08:27:31.92#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.196.08:27:31.92#ibcon#[27=USB\r\n] 2006.196.08:27:31.92#ibcon#*before write, iclass 22, count 0 2006.196.08:27:31.92#ibcon#enter sib2, iclass 22, count 0 2006.196.08:27:31.92#ibcon#flushed, iclass 22, count 0 2006.196.08:27:31.92#ibcon#about to write, iclass 22, count 0 2006.196.08:27:31.92#ibcon#wrote, iclass 22, count 0 2006.196.08:27:31.92#ibcon#about to read 3, iclass 22, count 0 2006.196.08:27:31.95#ibcon#read 3, iclass 22, count 0 2006.196.08:27:31.95#ibcon#about to read 4, iclass 22, count 0 2006.196.08:27:31.95#ibcon#read 4, iclass 22, count 0 2006.196.08:27:31.95#ibcon#about to read 5, iclass 22, count 0 2006.196.08:27:31.95#ibcon#read 5, iclass 22, count 0 2006.196.08:27:31.95#ibcon#about to read 6, iclass 22, count 0 2006.196.08:27:31.95#ibcon#read 6, iclass 22, count 0 2006.196.08:27:31.95#ibcon#end of sib2, iclass 22, count 0 2006.196.08:27:31.95#ibcon#*after write, iclass 22, count 0 2006.196.08:27:31.95#ibcon#*before return 0, iclass 22, count 0 2006.196.08:27:31.95#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.196.08:27:31.95#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.196.08:27:31.95#ibcon#about to clear, iclass 22 cls_cnt 0 2006.196.08:27:31.95#ibcon#cleared, iclass 22 cls_cnt 0 2006.196.08:27:31.95$vc4f8/vblo=5,744.99 2006.196.08:27:31.95#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.196.08:27:31.95#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.196.08:27:31.95#ibcon#ireg 17 cls_cnt 0 2006.196.08:27:31.95#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.196.08:27:31.95#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.196.08:27:31.95#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.196.08:27:31.95#ibcon#enter wrdev, iclass 24, count 0 2006.196.08:27:31.95#ibcon#first serial, iclass 24, count 0 2006.196.08:27:31.95#ibcon#enter sib2, iclass 24, count 0 2006.196.08:27:31.95#ibcon#flushed, iclass 24, count 0 2006.196.08:27:31.95#ibcon#about to write, iclass 24, count 0 2006.196.08:27:31.95#ibcon#wrote, iclass 24, count 0 2006.196.08:27:31.95#ibcon#about to read 3, iclass 24, count 0 2006.196.08:27:31.97#ibcon#read 3, iclass 24, count 0 2006.196.08:27:31.97#ibcon#about to read 4, iclass 24, count 0 2006.196.08:27:31.97#ibcon#read 4, iclass 24, count 0 2006.196.08:27:31.97#ibcon#about to read 5, iclass 24, count 0 2006.196.08:27:31.97#ibcon#read 5, iclass 24, count 0 2006.196.08:27:31.97#ibcon#about to read 6, iclass 24, count 0 2006.196.08:27:31.97#ibcon#read 6, iclass 24, count 0 2006.196.08:27:31.97#ibcon#end of sib2, iclass 24, count 0 2006.196.08:27:31.97#ibcon#*mode == 0, iclass 24, count 0 2006.196.08:27:31.97#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.196.08:27:31.97#ibcon#[28=FRQ=05,744.99\r\n] 2006.196.08:27:31.97#ibcon#*before write, iclass 24, count 0 2006.196.08:27:31.97#ibcon#enter sib2, iclass 24, count 0 2006.196.08:27:31.97#ibcon#flushed, iclass 24, count 0 2006.196.08:27:31.97#ibcon#about to write, iclass 24, count 0 2006.196.08:27:31.97#ibcon#wrote, iclass 24, count 0 2006.196.08:27:31.97#ibcon#about to read 3, iclass 24, count 0 2006.196.08:27:32.01#ibcon#read 3, iclass 24, count 0 2006.196.08:27:32.01#ibcon#about to read 4, iclass 24, count 0 2006.196.08:27:32.01#ibcon#read 4, iclass 24, count 0 2006.196.08:27:32.01#ibcon#about to read 5, iclass 24, count 0 2006.196.08:27:32.01#ibcon#read 5, iclass 24, count 0 2006.196.08:27:32.01#ibcon#about to read 6, iclass 24, count 0 2006.196.08:27:32.01#ibcon#read 6, iclass 24, count 0 2006.196.08:27:32.01#ibcon#end of sib2, iclass 24, count 0 2006.196.08:27:32.01#ibcon#*after write, iclass 24, count 0 2006.196.08:27:32.01#ibcon#*before return 0, iclass 24, count 0 2006.196.08:27:32.01#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.196.08:27:32.01#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.196.08:27:32.01#ibcon#about to clear, iclass 24 cls_cnt 0 2006.196.08:27:32.01#ibcon#cleared, iclass 24 cls_cnt 0 2006.196.08:27:32.01$vc4f8/vb=5,4 2006.196.08:27:32.01#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.196.08:27:32.01#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.196.08:27:32.01#ibcon#ireg 11 cls_cnt 2 2006.196.08:27:32.01#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.196.08:27:32.07#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.196.08:27:32.07#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.196.08:27:32.07#ibcon#enter wrdev, iclass 26, count 2 2006.196.08:27:32.07#ibcon#first serial, iclass 26, count 2 2006.196.08:27:32.07#ibcon#enter sib2, iclass 26, count 2 2006.196.08:27:32.07#ibcon#flushed, iclass 26, count 2 2006.196.08:27:32.07#ibcon#about to write, iclass 26, count 2 2006.196.08:27:32.07#ibcon#wrote, iclass 26, count 2 2006.196.08:27:32.07#ibcon#about to read 3, iclass 26, count 2 2006.196.08:27:32.09#ibcon#read 3, iclass 26, count 2 2006.196.08:27:32.09#ibcon#about to read 4, iclass 26, count 2 2006.196.08:27:32.09#ibcon#read 4, iclass 26, count 2 2006.196.08:27:32.09#ibcon#about to read 5, iclass 26, count 2 2006.196.08:27:32.09#ibcon#read 5, iclass 26, count 2 2006.196.08:27:32.09#ibcon#about to read 6, iclass 26, count 2 2006.196.08:27:32.09#ibcon#read 6, iclass 26, count 2 2006.196.08:27:32.09#ibcon#end of sib2, iclass 26, count 2 2006.196.08:27:32.09#ibcon#*mode == 0, iclass 26, count 2 2006.196.08:27:32.09#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.196.08:27:32.09#ibcon#[27=AT05-04\r\n] 2006.196.08:27:32.09#ibcon#*before write, iclass 26, count 2 2006.196.08:27:32.09#ibcon#enter sib2, iclass 26, count 2 2006.196.08:27:32.09#ibcon#flushed, iclass 26, count 2 2006.196.08:27:32.09#ibcon#about to write, iclass 26, count 2 2006.196.08:27:32.09#ibcon#wrote, iclass 26, count 2 2006.196.08:27:32.09#ibcon#about to read 3, iclass 26, count 2 2006.196.08:27:32.12#ibcon#read 3, iclass 26, count 2 2006.196.08:27:32.12#ibcon#about to read 4, iclass 26, count 2 2006.196.08:27:32.12#ibcon#read 4, iclass 26, count 2 2006.196.08:27:32.12#ibcon#about to read 5, iclass 26, count 2 2006.196.08:27:32.12#ibcon#read 5, iclass 26, count 2 2006.196.08:27:32.12#ibcon#about to read 6, iclass 26, count 2 2006.196.08:27:32.12#ibcon#read 6, iclass 26, count 2 2006.196.08:27:32.12#ibcon#end of sib2, iclass 26, count 2 2006.196.08:27:32.12#ibcon#*after write, iclass 26, count 2 2006.196.08:27:32.12#ibcon#*before return 0, iclass 26, count 2 2006.196.08:27:32.12#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.196.08:27:32.12#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.196.08:27:32.12#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.196.08:27:32.12#ibcon#ireg 7 cls_cnt 0 2006.196.08:27:32.12#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.196.08:27:32.24#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.196.08:27:32.24#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.196.08:27:32.24#ibcon#enter wrdev, iclass 26, count 0 2006.196.08:27:32.24#ibcon#first serial, iclass 26, count 0 2006.196.08:27:32.24#ibcon#enter sib2, iclass 26, count 0 2006.196.08:27:32.24#ibcon#flushed, iclass 26, count 0 2006.196.08:27:32.24#ibcon#about to write, iclass 26, count 0 2006.196.08:27:32.24#ibcon#wrote, iclass 26, count 0 2006.196.08:27:32.24#ibcon#about to read 3, iclass 26, count 0 2006.196.08:27:32.26#ibcon#read 3, iclass 26, count 0 2006.196.08:27:32.26#ibcon#about to read 4, iclass 26, count 0 2006.196.08:27:32.26#ibcon#read 4, iclass 26, count 0 2006.196.08:27:32.26#ibcon#about to read 5, iclass 26, count 0 2006.196.08:27:32.26#ibcon#read 5, iclass 26, count 0 2006.196.08:27:32.26#ibcon#about to read 6, iclass 26, count 0 2006.196.08:27:32.26#ibcon#read 6, iclass 26, count 0 2006.196.08:27:32.26#ibcon#end of sib2, iclass 26, count 0 2006.196.08:27:32.26#ibcon#*mode == 0, iclass 26, count 0 2006.196.08:27:32.26#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.196.08:27:32.26#ibcon#[27=USB\r\n] 2006.196.08:27:32.26#ibcon#*before write, iclass 26, count 0 2006.196.08:27:32.26#ibcon#enter sib2, iclass 26, count 0 2006.196.08:27:32.26#ibcon#flushed, iclass 26, count 0 2006.196.08:27:32.26#ibcon#about to write, iclass 26, count 0 2006.196.08:27:32.26#ibcon#wrote, iclass 26, count 0 2006.196.08:27:32.26#ibcon#about to read 3, iclass 26, count 0 2006.196.08:27:32.29#ibcon#read 3, iclass 26, count 0 2006.196.08:27:32.29#ibcon#about to read 4, iclass 26, count 0 2006.196.08:27:32.29#ibcon#read 4, iclass 26, count 0 2006.196.08:27:32.29#ibcon#about to read 5, iclass 26, count 0 2006.196.08:27:32.29#ibcon#read 5, iclass 26, count 0 2006.196.08:27:32.29#ibcon#about to read 6, iclass 26, count 0 2006.196.08:27:32.29#ibcon#read 6, iclass 26, count 0 2006.196.08:27:32.29#ibcon#end of sib2, iclass 26, count 0 2006.196.08:27:32.29#ibcon#*after write, iclass 26, count 0 2006.196.08:27:32.29#ibcon#*before return 0, iclass 26, count 0 2006.196.08:27:32.29#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.196.08:27:32.29#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.196.08:27:32.29#ibcon#about to clear, iclass 26 cls_cnt 0 2006.196.08:27:32.29#ibcon#cleared, iclass 26 cls_cnt 0 2006.196.08:27:32.29$vc4f8/vblo=6,752.99 2006.196.08:27:32.29#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.196.08:27:32.29#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.196.08:27:32.29#ibcon#ireg 17 cls_cnt 0 2006.196.08:27:32.29#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.196.08:27:32.29#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.196.08:27:32.29#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.196.08:27:32.29#ibcon#enter wrdev, iclass 28, count 0 2006.196.08:27:32.29#ibcon#first serial, iclass 28, count 0 2006.196.08:27:32.29#ibcon#enter sib2, iclass 28, count 0 2006.196.08:27:32.29#ibcon#flushed, iclass 28, count 0 2006.196.08:27:32.29#ibcon#about to write, iclass 28, count 0 2006.196.08:27:32.29#ibcon#wrote, iclass 28, count 0 2006.196.08:27:32.29#ibcon#about to read 3, iclass 28, count 0 2006.196.08:27:32.31#ibcon#read 3, iclass 28, count 0 2006.196.08:27:32.31#ibcon#about to read 4, iclass 28, count 0 2006.196.08:27:32.31#ibcon#read 4, iclass 28, count 0 2006.196.08:27:32.31#ibcon#about to read 5, iclass 28, count 0 2006.196.08:27:32.31#ibcon#read 5, iclass 28, count 0 2006.196.08:27:32.31#ibcon#about to read 6, iclass 28, count 0 2006.196.08:27:32.31#ibcon#read 6, iclass 28, count 0 2006.196.08:27:32.31#ibcon#end of sib2, iclass 28, count 0 2006.196.08:27:32.31#ibcon#*mode == 0, iclass 28, count 0 2006.196.08:27:32.31#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.196.08:27:32.31#ibcon#[28=FRQ=06,752.99\r\n] 2006.196.08:27:32.31#ibcon#*before write, iclass 28, count 0 2006.196.08:27:32.31#ibcon#enter sib2, iclass 28, count 0 2006.196.08:27:32.31#ibcon#flushed, iclass 28, count 0 2006.196.08:27:32.31#ibcon#about to write, iclass 28, count 0 2006.196.08:27:32.31#ibcon#wrote, iclass 28, count 0 2006.196.08:27:32.31#ibcon#about to read 3, iclass 28, count 0 2006.196.08:27:32.35#ibcon#read 3, iclass 28, count 0 2006.196.08:27:32.35#ibcon#about to read 4, iclass 28, count 0 2006.196.08:27:32.35#ibcon#read 4, iclass 28, count 0 2006.196.08:27:32.35#ibcon#about to read 5, iclass 28, count 0 2006.196.08:27:32.35#ibcon#read 5, iclass 28, count 0 2006.196.08:27:32.35#ibcon#about to read 6, iclass 28, count 0 2006.196.08:27:32.35#ibcon#read 6, iclass 28, count 0 2006.196.08:27:32.35#ibcon#end of sib2, iclass 28, count 0 2006.196.08:27:32.35#ibcon#*after write, iclass 28, count 0 2006.196.08:27:32.35#ibcon#*before return 0, iclass 28, count 0 2006.196.08:27:32.35#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.196.08:27:32.35#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.196.08:27:32.35#ibcon#about to clear, iclass 28 cls_cnt 0 2006.196.08:27:32.35#ibcon#cleared, iclass 28 cls_cnt 0 2006.196.08:27:32.35$vc4f8/vb=6,4 2006.196.08:27:32.35#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.196.08:27:32.35#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.196.08:27:32.35#ibcon#ireg 11 cls_cnt 2 2006.196.08:27:32.35#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.196.08:27:32.41#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.196.08:27:32.41#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.196.08:27:32.41#ibcon#enter wrdev, iclass 30, count 2 2006.196.08:27:32.41#ibcon#first serial, iclass 30, count 2 2006.196.08:27:32.41#ibcon#enter sib2, iclass 30, count 2 2006.196.08:27:32.41#ibcon#flushed, iclass 30, count 2 2006.196.08:27:32.41#ibcon#about to write, iclass 30, count 2 2006.196.08:27:32.41#ibcon#wrote, iclass 30, count 2 2006.196.08:27:32.41#ibcon#about to read 3, iclass 30, count 2 2006.196.08:27:32.43#ibcon#read 3, iclass 30, count 2 2006.196.08:27:32.43#ibcon#about to read 4, iclass 30, count 2 2006.196.08:27:32.43#ibcon#read 4, iclass 30, count 2 2006.196.08:27:32.43#ibcon#about to read 5, iclass 30, count 2 2006.196.08:27:32.43#ibcon#read 5, iclass 30, count 2 2006.196.08:27:32.43#ibcon#about to read 6, iclass 30, count 2 2006.196.08:27:32.43#ibcon#read 6, iclass 30, count 2 2006.196.08:27:32.43#ibcon#end of sib2, iclass 30, count 2 2006.196.08:27:32.43#ibcon#*mode == 0, iclass 30, count 2 2006.196.08:27:32.43#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.196.08:27:32.43#ibcon#[27=AT06-04\r\n] 2006.196.08:27:32.43#ibcon#*before write, iclass 30, count 2 2006.196.08:27:32.43#ibcon#enter sib2, iclass 30, count 2 2006.196.08:27:32.43#ibcon#flushed, iclass 30, count 2 2006.196.08:27:32.43#ibcon#about to write, iclass 30, count 2 2006.196.08:27:32.43#ibcon#wrote, iclass 30, count 2 2006.196.08:27:32.43#ibcon#about to read 3, iclass 30, count 2 2006.196.08:27:32.46#ibcon#read 3, iclass 30, count 2 2006.196.08:27:32.46#ibcon#about to read 4, iclass 30, count 2 2006.196.08:27:32.46#ibcon#read 4, iclass 30, count 2 2006.196.08:27:32.46#ibcon#about to read 5, iclass 30, count 2 2006.196.08:27:32.46#ibcon#read 5, iclass 30, count 2 2006.196.08:27:32.46#ibcon#about to read 6, iclass 30, count 2 2006.196.08:27:32.46#ibcon#read 6, iclass 30, count 2 2006.196.08:27:32.46#ibcon#end of sib2, iclass 30, count 2 2006.196.08:27:32.46#ibcon#*after write, iclass 30, count 2 2006.196.08:27:32.46#ibcon#*before return 0, iclass 30, count 2 2006.196.08:27:32.46#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.196.08:27:32.46#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.196.08:27:32.46#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.196.08:27:32.46#ibcon#ireg 7 cls_cnt 0 2006.196.08:27:32.46#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.196.08:27:32.58#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.196.08:27:32.58#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.196.08:27:32.58#ibcon#enter wrdev, iclass 30, count 0 2006.196.08:27:32.58#ibcon#first serial, iclass 30, count 0 2006.196.08:27:32.58#ibcon#enter sib2, iclass 30, count 0 2006.196.08:27:32.58#ibcon#flushed, iclass 30, count 0 2006.196.08:27:32.58#ibcon#about to write, iclass 30, count 0 2006.196.08:27:32.58#ibcon#wrote, iclass 30, count 0 2006.196.08:27:32.58#ibcon#about to read 3, iclass 30, count 0 2006.196.08:27:32.60#ibcon#read 3, iclass 30, count 0 2006.196.08:27:32.60#ibcon#about to read 4, iclass 30, count 0 2006.196.08:27:32.60#ibcon#read 4, iclass 30, count 0 2006.196.08:27:32.60#ibcon#about to read 5, iclass 30, count 0 2006.196.08:27:32.60#ibcon#read 5, iclass 30, count 0 2006.196.08:27:32.60#ibcon#about to read 6, iclass 30, count 0 2006.196.08:27:32.60#ibcon#read 6, iclass 30, count 0 2006.196.08:27:32.60#ibcon#end of sib2, iclass 30, count 0 2006.196.08:27:32.60#ibcon#*mode == 0, iclass 30, count 0 2006.196.08:27:32.60#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.196.08:27:32.60#ibcon#[27=USB\r\n] 2006.196.08:27:32.60#ibcon#*before write, iclass 30, count 0 2006.196.08:27:32.60#ibcon#enter sib2, iclass 30, count 0 2006.196.08:27:32.60#ibcon#flushed, iclass 30, count 0 2006.196.08:27:32.60#ibcon#about to write, iclass 30, count 0 2006.196.08:27:32.60#ibcon#wrote, iclass 30, count 0 2006.196.08:27:32.60#ibcon#about to read 3, iclass 30, count 0 2006.196.08:27:32.63#ibcon#read 3, iclass 30, count 0 2006.196.08:27:32.63#ibcon#about to read 4, iclass 30, count 0 2006.196.08:27:32.63#ibcon#read 4, iclass 30, count 0 2006.196.08:27:32.63#ibcon#about to read 5, iclass 30, count 0 2006.196.08:27:32.63#ibcon#read 5, iclass 30, count 0 2006.196.08:27:32.63#ibcon#about to read 6, iclass 30, count 0 2006.196.08:27:32.63#ibcon#read 6, iclass 30, count 0 2006.196.08:27:32.63#ibcon#end of sib2, iclass 30, count 0 2006.196.08:27:32.63#ibcon#*after write, iclass 30, count 0 2006.196.08:27:32.63#ibcon#*before return 0, iclass 30, count 0 2006.196.08:27:32.63#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.196.08:27:32.63#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.196.08:27:32.63#ibcon#about to clear, iclass 30 cls_cnt 0 2006.196.08:27:32.63#ibcon#cleared, iclass 30 cls_cnt 0 2006.196.08:27:32.63$vc4f8/vabw=wide 2006.196.08:27:32.63#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.196.08:27:32.63#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.196.08:27:32.63#ibcon#ireg 8 cls_cnt 0 2006.196.08:27:32.63#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.196.08:27:32.63#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.196.08:27:32.63#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.196.08:27:32.63#ibcon#enter wrdev, iclass 32, count 0 2006.196.08:27:32.63#ibcon#first serial, iclass 32, count 0 2006.196.08:27:32.63#ibcon#enter sib2, iclass 32, count 0 2006.196.08:27:32.63#ibcon#flushed, iclass 32, count 0 2006.196.08:27:32.63#ibcon#about to write, iclass 32, count 0 2006.196.08:27:32.63#ibcon#wrote, iclass 32, count 0 2006.196.08:27:32.63#ibcon#about to read 3, iclass 32, count 0 2006.196.08:27:32.65#ibcon#read 3, iclass 32, count 0 2006.196.08:27:32.65#ibcon#about to read 4, iclass 32, count 0 2006.196.08:27:32.65#ibcon#read 4, iclass 32, count 0 2006.196.08:27:32.65#ibcon#about to read 5, iclass 32, count 0 2006.196.08:27:32.65#ibcon#read 5, iclass 32, count 0 2006.196.08:27:32.65#ibcon#about to read 6, iclass 32, count 0 2006.196.08:27:32.65#ibcon#read 6, iclass 32, count 0 2006.196.08:27:32.65#ibcon#end of sib2, iclass 32, count 0 2006.196.08:27:32.65#ibcon#*mode == 0, iclass 32, count 0 2006.196.08:27:32.65#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.196.08:27:32.65#ibcon#[25=BW32\r\n] 2006.196.08:27:32.65#ibcon#*before write, iclass 32, count 0 2006.196.08:27:32.65#ibcon#enter sib2, iclass 32, count 0 2006.196.08:27:32.65#ibcon#flushed, iclass 32, count 0 2006.196.08:27:32.65#ibcon#about to write, iclass 32, count 0 2006.196.08:27:32.65#ibcon#wrote, iclass 32, count 0 2006.196.08:27:32.65#ibcon#about to read 3, iclass 32, count 0 2006.196.08:27:32.68#ibcon#read 3, iclass 32, count 0 2006.196.08:27:32.68#ibcon#about to read 4, iclass 32, count 0 2006.196.08:27:32.68#ibcon#read 4, iclass 32, count 0 2006.196.08:27:32.68#ibcon#about to read 5, iclass 32, count 0 2006.196.08:27:32.68#ibcon#read 5, iclass 32, count 0 2006.196.08:27:32.68#ibcon#about to read 6, iclass 32, count 0 2006.196.08:27:32.68#ibcon#read 6, iclass 32, count 0 2006.196.08:27:32.68#ibcon#end of sib2, iclass 32, count 0 2006.196.08:27:32.68#ibcon#*after write, iclass 32, count 0 2006.196.08:27:32.68#ibcon#*before return 0, iclass 32, count 0 2006.196.08:27:32.68#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.196.08:27:32.68#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.196.08:27:32.68#ibcon#about to clear, iclass 32 cls_cnt 0 2006.196.08:27:32.68#ibcon#cleared, iclass 32 cls_cnt 0 2006.196.08:27:32.68$vc4f8/vbbw=wide 2006.196.08:27:32.68#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.196.08:27:32.68#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.196.08:27:32.68#ibcon#ireg 8 cls_cnt 0 2006.196.08:27:32.68#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.196.08:27:32.75#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.196.08:27:32.75#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.196.08:27:32.75#ibcon#enter wrdev, iclass 34, count 0 2006.196.08:27:32.75#ibcon#first serial, iclass 34, count 0 2006.196.08:27:32.75#ibcon#enter sib2, iclass 34, count 0 2006.196.08:27:32.75#ibcon#flushed, iclass 34, count 0 2006.196.08:27:32.75#ibcon#about to write, iclass 34, count 0 2006.196.08:27:32.75#ibcon#wrote, iclass 34, count 0 2006.196.08:27:32.75#ibcon#about to read 3, iclass 34, count 0 2006.196.08:27:32.77#ibcon#read 3, iclass 34, count 0 2006.196.08:27:32.77#ibcon#about to read 4, iclass 34, count 0 2006.196.08:27:32.77#ibcon#read 4, iclass 34, count 0 2006.196.08:27:32.77#ibcon#about to read 5, iclass 34, count 0 2006.196.08:27:32.77#ibcon#read 5, iclass 34, count 0 2006.196.08:27:32.77#ibcon#about to read 6, iclass 34, count 0 2006.196.08:27:32.77#ibcon#read 6, iclass 34, count 0 2006.196.08:27:32.77#ibcon#end of sib2, iclass 34, count 0 2006.196.08:27:32.77#ibcon#*mode == 0, iclass 34, count 0 2006.196.08:27:32.77#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.196.08:27:32.77#ibcon#[27=BW32\r\n] 2006.196.08:27:32.77#ibcon#*before write, iclass 34, count 0 2006.196.08:27:32.77#ibcon#enter sib2, iclass 34, count 0 2006.196.08:27:32.77#ibcon#flushed, iclass 34, count 0 2006.196.08:27:32.77#ibcon#about to write, iclass 34, count 0 2006.196.08:27:32.77#ibcon#wrote, iclass 34, count 0 2006.196.08:27:32.77#ibcon#about to read 3, iclass 34, count 0 2006.196.08:27:32.80#ibcon#read 3, iclass 34, count 0 2006.196.08:27:32.80#ibcon#about to read 4, iclass 34, count 0 2006.196.08:27:32.80#ibcon#read 4, iclass 34, count 0 2006.196.08:27:32.80#ibcon#about to read 5, iclass 34, count 0 2006.196.08:27:32.80#ibcon#read 5, iclass 34, count 0 2006.196.08:27:32.80#ibcon#about to read 6, iclass 34, count 0 2006.196.08:27:32.80#ibcon#read 6, iclass 34, count 0 2006.196.08:27:32.80#ibcon#end of sib2, iclass 34, count 0 2006.196.08:27:32.80#ibcon#*after write, iclass 34, count 0 2006.196.08:27:32.80#ibcon#*before return 0, iclass 34, count 0 2006.196.08:27:32.80#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.196.08:27:32.80#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.196.08:27:32.80#ibcon#about to clear, iclass 34 cls_cnt 0 2006.196.08:27:32.80#ibcon#cleared, iclass 34 cls_cnt 0 2006.196.08:27:32.80$4f8m12a/ifd4f 2006.196.08:27:32.80$ifd4f/lo= 2006.196.08:27:32.80$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.196.08:27:32.80$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.196.08:27:32.80$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.196.08:27:32.80$ifd4f/patch= 2006.196.08:27:32.80$ifd4f/patch=lo1,a1,a2,a3,a4 2006.196.08:27:32.80$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.196.08:27:32.80$ifd4f/patch=lo3,a5,a6,a7,a8 2006.196.08:27:32.80$4f8m12a/"form=m,16.000,1:2 2006.196.08:27:32.80$4f8m12a/"tpicd 2006.196.08:27:32.80$4f8m12a/echo=off 2006.196.08:27:32.80$4f8m12a/xlog=off 2006.196.08:27:32.80:!2006.196.08:28:20 2006.196.08:28:01.14#trakl#Source acquired 2006.196.08:28:03.14#flagr#flagr/antenna,acquired 2006.196.08:28:20.00:preob 2006.196.08:28:20.14/onsource/TRACKING 2006.196.08:28:20.14:!2006.196.08:28:30 2006.196.08:28:30.00:data_valid=on 2006.196.08:28:30.00:midob 2006.196.08:28:30.14/onsource/TRACKING 2006.196.08:28:30.14/wx/28.76,1004.2,93 2006.196.08:28:30.19/cable/+6.3376E-03 2006.196.08:28:31.28/va/01,08,usb,yes,32,34 2006.196.08:28:31.28/va/02,07,usb,yes,32,34 2006.196.08:28:31.28/va/03,06,usb,yes,34,34 2006.196.08:28:31.28/va/04,07,usb,yes,33,35 2006.196.08:28:31.28/va/05,07,usb,yes,36,38 2006.196.08:28:31.28/va/06,06,usb,yes,35,35 2006.196.08:28:31.28/va/07,06,usb,yes,36,36 2006.196.08:28:31.28/va/08,07,usb,yes,34,33 2006.196.08:28:31.51/valo/01,532.99,yes,locked 2006.196.08:28:31.51/valo/02,572.99,yes,locked 2006.196.08:28:31.51/valo/03,672.99,yes,locked 2006.196.08:28:31.51/valo/04,832.99,yes,locked 2006.196.08:28:31.51/valo/05,652.99,yes,locked 2006.196.08:28:31.51/valo/06,772.99,yes,locked 2006.196.08:28:31.51/valo/07,832.99,yes,locked 2006.196.08:28:31.51/valo/08,852.99,yes,locked 2006.196.08:28:32.60/vb/01,04,usb,yes,30,29 2006.196.08:28:32.60/vb/02,04,usb,yes,32,33 2006.196.08:28:32.60/vb/03,04,usb,yes,28,32 2006.196.08:28:32.60/vb/04,04,usb,yes,29,30 2006.196.08:28:32.60/vb/05,04,usb,yes,28,32 2006.196.08:28:32.60/vb/06,04,usb,yes,29,32 2006.196.08:28:32.60/vb/07,04,usb,yes,31,31 2006.196.08:28:32.60/vb/08,04,usb,yes,28,32 2006.196.08:28:32.83/vblo/01,632.99,yes,locked 2006.196.08:28:32.83/vblo/02,640.99,yes,locked 2006.196.08:28:32.83/vblo/03,656.99,yes,locked 2006.196.08:28:32.83/vblo/04,712.99,yes,locked 2006.196.08:28:32.83/vblo/05,744.99,yes,locked 2006.196.08:28:32.83/vblo/06,752.99,yes,locked 2006.196.08:28:32.83/vblo/07,734.99,yes,locked 2006.196.08:28:32.83/vblo/08,744.99,yes,locked 2006.196.08:28:32.98/vabw/8 2006.196.08:28:33.13/vbbw/8 2006.196.08:28:33.22/xfe/off,on,15.2 2006.196.08:28:33.59/ifatt/23,28,28,28 2006.196.08:28:34.07/fmout-gps/S +3.34E-07 2006.196.08:28:34.11:!2006.196.08:29:30 2006.196.08:29:30.00:data_valid=off 2006.196.08:29:30.00:postob 2006.196.08:29:30.14/cable/+6.3379E-03 2006.196.08:29:30.14/wx/28.74,1004.2,92 2006.196.08:29:31.07/fmout-gps/S +3.34E-07 2006.196.08:29:31.07:scan_name=196-0830,k06196,60 2006.196.08:29:31.07:source=1803+784,180045.68,782804.0,2000.0,cw 2006.196.08:29:31.14#flagr#flagr/antenna,new-source 2006.196.08:29:32.14:checkk5 2006.196.08:29:32.51/chk_autoobs//k5ts1/ autoobs is running! 2006.196.08:29:32.91/chk_autoobs//k5ts2/ autoobs is running! 2006.196.08:29:33.28/chk_autoobs//k5ts3/ autoobs is running! 2006.196.08:29:33.65/chk_autoobs//k5ts4/ autoobs is running! 2006.196.08:29:34.02/chk_obsdata//k5ts1/T1960828??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.08:29:34.39/chk_obsdata//k5ts2/T1960828??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.08:29:34.76/chk_obsdata//k5ts3/T1960828??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.08:29:35.15/chk_obsdata//k5ts4/T1960828??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.08:29:35.84/k5log//k5ts1_log_newline 2006.196.08:29:36.53/k5log//k5ts2_log_newline 2006.196.08:29:37.22/k5log//k5ts3_log_newline 2006.196.08:29:37.91/k5log//k5ts4_log_newline 2006.196.08:29:37.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.196.08:29:37.93:4f8m12a=3 2006.196.08:29:37.93$4f8m12a/echo=on 2006.196.08:29:37.93$4f8m12a/pcalon 2006.196.08:29:37.93$pcalon/"no phase cal control is implemented here 2006.196.08:29:37.93$4f8m12a/"tpicd=stop 2006.196.08:29:37.93$4f8m12a/vc4f8 2006.196.08:29:37.93$vc4f8/valo=1,532.99 2006.196.08:29:37.94#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.196.08:29:37.94#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.196.08:29:37.94#ibcon#ireg 17 cls_cnt 0 2006.196.08:29:37.94#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.196.08:29:37.94#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.196.08:29:37.94#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.196.08:29:37.94#ibcon#enter wrdev, iclass 13, count 0 2006.196.08:29:37.94#ibcon#first serial, iclass 13, count 0 2006.196.08:29:37.94#ibcon#enter sib2, iclass 13, count 0 2006.196.08:29:37.94#ibcon#flushed, iclass 13, count 0 2006.196.08:29:37.94#ibcon#about to write, iclass 13, count 0 2006.196.08:29:37.94#ibcon#wrote, iclass 13, count 0 2006.196.08:29:37.94#ibcon#about to read 3, iclass 13, count 0 2006.196.08:29:37.98#ibcon#read 3, iclass 13, count 0 2006.196.08:29:37.98#ibcon#about to read 4, iclass 13, count 0 2006.196.08:29:37.98#ibcon#read 4, iclass 13, count 0 2006.196.08:29:37.98#ibcon#about to read 5, iclass 13, count 0 2006.196.08:29:37.98#ibcon#read 5, iclass 13, count 0 2006.196.08:29:37.98#ibcon#about to read 6, iclass 13, count 0 2006.196.08:29:37.98#ibcon#read 6, iclass 13, count 0 2006.196.08:29:37.98#ibcon#end of sib2, iclass 13, count 0 2006.196.08:29:37.98#ibcon#*mode == 0, iclass 13, count 0 2006.196.08:29:37.98#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.196.08:29:37.98#ibcon#[26=FRQ=01,532.99\r\n] 2006.196.08:29:37.98#ibcon#*before write, iclass 13, count 0 2006.196.08:29:37.98#ibcon#enter sib2, iclass 13, count 0 2006.196.08:29:37.98#ibcon#flushed, iclass 13, count 0 2006.196.08:29:37.98#ibcon#about to write, iclass 13, count 0 2006.196.08:29:37.98#ibcon#wrote, iclass 13, count 0 2006.196.08:29:37.98#ibcon#about to read 3, iclass 13, count 0 2006.196.08:29:38.03#ibcon#read 3, iclass 13, count 0 2006.196.08:29:38.03#ibcon#about to read 4, iclass 13, count 0 2006.196.08:29:38.03#ibcon#read 4, iclass 13, count 0 2006.196.08:29:38.03#ibcon#about to read 5, iclass 13, count 0 2006.196.08:29:38.03#ibcon#read 5, iclass 13, count 0 2006.196.08:29:38.03#ibcon#about to read 6, iclass 13, count 0 2006.196.08:29:38.03#ibcon#read 6, iclass 13, count 0 2006.196.08:29:38.03#ibcon#end of sib2, iclass 13, count 0 2006.196.08:29:38.03#ibcon#*after write, iclass 13, count 0 2006.196.08:29:38.03#ibcon#*before return 0, iclass 13, count 0 2006.196.08:29:38.03#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.196.08:29:38.03#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.196.08:29:38.03#ibcon#about to clear, iclass 13 cls_cnt 0 2006.196.08:29:38.03#ibcon#cleared, iclass 13 cls_cnt 0 2006.196.08:29:38.03$vc4f8/va=1,8 2006.196.08:29:38.03#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.196.08:29:38.03#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.196.08:29:38.03#ibcon#ireg 11 cls_cnt 2 2006.196.08:29:38.03#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.196.08:29:38.03#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.196.08:29:38.03#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.196.08:29:38.03#ibcon#enter wrdev, iclass 15, count 2 2006.196.08:29:38.03#ibcon#first serial, iclass 15, count 2 2006.196.08:29:38.03#ibcon#enter sib2, iclass 15, count 2 2006.196.08:29:38.03#ibcon#flushed, iclass 15, count 2 2006.196.08:29:38.03#ibcon#about to write, iclass 15, count 2 2006.196.08:29:38.03#ibcon#wrote, iclass 15, count 2 2006.196.08:29:38.03#ibcon#about to read 3, iclass 15, count 2 2006.196.08:29:38.05#ibcon#read 3, iclass 15, count 2 2006.196.08:29:38.05#ibcon#about to read 4, iclass 15, count 2 2006.196.08:29:38.05#ibcon#read 4, iclass 15, count 2 2006.196.08:29:38.05#ibcon#about to read 5, iclass 15, count 2 2006.196.08:29:38.05#ibcon#read 5, iclass 15, count 2 2006.196.08:29:38.05#ibcon#about to read 6, iclass 15, count 2 2006.196.08:29:38.05#ibcon#read 6, iclass 15, count 2 2006.196.08:29:38.05#ibcon#end of sib2, iclass 15, count 2 2006.196.08:29:38.05#ibcon#*mode == 0, iclass 15, count 2 2006.196.08:29:38.05#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.196.08:29:38.05#ibcon#[25=AT01-08\r\n] 2006.196.08:29:38.05#ibcon#*before write, iclass 15, count 2 2006.196.08:29:38.05#ibcon#enter sib2, iclass 15, count 2 2006.196.08:29:38.05#ibcon#flushed, iclass 15, count 2 2006.196.08:29:38.05#ibcon#about to write, iclass 15, count 2 2006.196.08:29:38.05#ibcon#wrote, iclass 15, count 2 2006.196.08:29:38.05#ibcon#about to read 3, iclass 15, count 2 2006.196.08:29:38.08#ibcon#read 3, iclass 15, count 2 2006.196.08:29:38.08#ibcon#about to read 4, iclass 15, count 2 2006.196.08:29:38.08#ibcon#read 4, iclass 15, count 2 2006.196.08:29:38.08#ibcon#about to read 5, iclass 15, count 2 2006.196.08:29:38.08#ibcon#read 5, iclass 15, count 2 2006.196.08:29:38.08#ibcon#about to read 6, iclass 15, count 2 2006.196.08:29:38.08#ibcon#read 6, iclass 15, count 2 2006.196.08:29:38.08#ibcon#end of sib2, iclass 15, count 2 2006.196.08:29:38.08#ibcon#*after write, iclass 15, count 2 2006.196.08:29:38.08#ibcon#*before return 0, iclass 15, count 2 2006.196.08:29:38.08#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.196.08:29:38.08#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.196.08:29:38.08#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.196.08:29:38.08#ibcon#ireg 7 cls_cnt 0 2006.196.08:29:38.08#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.196.08:29:38.20#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.196.08:29:38.20#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.196.08:29:38.20#ibcon#enter wrdev, iclass 15, count 0 2006.196.08:29:38.20#ibcon#first serial, iclass 15, count 0 2006.196.08:29:38.20#ibcon#enter sib2, iclass 15, count 0 2006.196.08:29:38.20#ibcon#flushed, iclass 15, count 0 2006.196.08:29:38.20#ibcon#about to write, iclass 15, count 0 2006.196.08:29:38.20#ibcon#wrote, iclass 15, count 0 2006.196.08:29:38.20#ibcon#about to read 3, iclass 15, count 0 2006.196.08:29:38.22#ibcon#read 3, iclass 15, count 0 2006.196.08:29:38.22#ibcon#about to read 4, iclass 15, count 0 2006.196.08:29:38.22#ibcon#read 4, iclass 15, count 0 2006.196.08:29:38.22#ibcon#about to read 5, iclass 15, count 0 2006.196.08:29:38.22#ibcon#read 5, iclass 15, count 0 2006.196.08:29:38.22#ibcon#about to read 6, iclass 15, count 0 2006.196.08:29:38.22#ibcon#read 6, iclass 15, count 0 2006.196.08:29:38.22#ibcon#end of sib2, iclass 15, count 0 2006.196.08:29:38.22#ibcon#*mode == 0, iclass 15, count 0 2006.196.08:29:38.22#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.196.08:29:38.22#ibcon#[25=USB\r\n] 2006.196.08:29:38.22#ibcon#*before write, iclass 15, count 0 2006.196.08:29:38.22#ibcon#enter sib2, iclass 15, count 0 2006.196.08:29:38.22#ibcon#flushed, iclass 15, count 0 2006.196.08:29:38.22#ibcon#about to write, iclass 15, count 0 2006.196.08:29:38.22#ibcon#wrote, iclass 15, count 0 2006.196.08:29:38.22#ibcon#about to read 3, iclass 15, count 0 2006.196.08:29:38.25#ibcon#read 3, iclass 15, count 0 2006.196.08:29:38.25#ibcon#about to read 4, iclass 15, count 0 2006.196.08:29:38.25#ibcon#read 4, iclass 15, count 0 2006.196.08:29:38.25#ibcon#about to read 5, iclass 15, count 0 2006.196.08:29:38.25#ibcon#read 5, iclass 15, count 0 2006.196.08:29:38.25#ibcon#about to read 6, iclass 15, count 0 2006.196.08:29:38.25#ibcon#read 6, iclass 15, count 0 2006.196.08:29:38.25#ibcon#end of sib2, iclass 15, count 0 2006.196.08:29:38.25#ibcon#*after write, iclass 15, count 0 2006.196.08:29:38.25#ibcon#*before return 0, iclass 15, count 0 2006.196.08:29:38.25#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.196.08:29:38.25#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.196.08:29:38.25#ibcon#about to clear, iclass 15 cls_cnt 0 2006.196.08:29:38.25#ibcon#cleared, iclass 15 cls_cnt 0 2006.196.08:29:38.25$vc4f8/valo=2,572.99 2006.196.08:29:38.25#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.196.08:29:38.25#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.196.08:29:38.25#ibcon#ireg 17 cls_cnt 0 2006.196.08:29:38.25#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.196.08:29:38.25#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.196.08:29:38.25#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.196.08:29:38.25#ibcon#enter wrdev, iclass 17, count 0 2006.196.08:29:38.25#ibcon#first serial, iclass 17, count 0 2006.196.08:29:38.25#ibcon#enter sib2, iclass 17, count 0 2006.196.08:29:38.25#ibcon#flushed, iclass 17, count 0 2006.196.08:29:38.25#ibcon#about to write, iclass 17, count 0 2006.196.08:29:38.25#ibcon#wrote, iclass 17, count 0 2006.196.08:29:38.25#ibcon#about to read 3, iclass 17, count 0 2006.196.08:29:38.27#ibcon#read 3, iclass 17, count 0 2006.196.08:29:38.27#ibcon#about to read 4, iclass 17, count 0 2006.196.08:29:38.27#ibcon#read 4, iclass 17, count 0 2006.196.08:29:38.27#ibcon#about to read 5, iclass 17, count 0 2006.196.08:29:38.27#ibcon#read 5, iclass 17, count 0 2006.196.08:29:38.27#ibcon#about to read 6, iclass 17, count 0 2006.196.08:29:38.27#ibcon#read 6, iclass 17, count 0 2006.196.08:29:38.27#ibcon#end of sib2, iclass 17, count 0 2006.196.08:29:38.27#ibcon#*mode == 0, iclass 17, count 0 2006.196.08:29:38.27#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.196.08:29:38.27#ibcon#[26=FRQ=02,572.99\r\n] 2006.196.08:29:38.27#ibcon#*before write, iclass 17, count 0 2006.196.08:29:38.27#ibcon#enter sib2, iclass 17, count 0 2006.196.08:29:38.27#ibcon#flushed, iclass 17, count 0 2006.196.08:29:38.27#ibcon#about to write, iclass 17, count 0 2006.196.08:29:38.27#ibcon#wrote, iclass 17, count 0 2006.196.08:29:38.27#ibcon#about to read 3, iclass 17, count 0 2006.196.08:29:38.31#ibcon#read 3, iclass 17, count 0 2006.196.08:29:38.31#ibcon#about to read 4, iclass 17, count 0 2006.196.08:29:38.31#ibcon#read 4, iclass 17, count 0 2006.196.08:29:38.31#ibcon#about to read 5, iclass 17, count 0 2006.196.08:29:38.31#ibcon#read 5, iclass 17, count 0 2006.196.08:29:38.31#ibcon#about to read 6, iclass 17, count 0 2006.196.08:29:38.31#ibcon#read 6, iclass 17, count 0 2006.196.08:29:38.31#ibcon#end of sib2, iclass 17, count 0 2006.196.08:29:38.31#ibcon#*after write, iclass 17, count 0 2006.196.08:29:38.31#ibcon#*before return 0, iclass 17, count 0 2006.196.08:29:38.31#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.196.08:29:38.31#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.196.08:29:38.31#ibcon#about to clear, iclass 17 cls_cnt 0 2006.196.08:29:38.31#ibcon#cleared, iclass 17 cls_cnt 0 2006.196.08:29:38.31$vc4f8/va=2,7 2006.196.08:29:38.31#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.196.08:29:38.31#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.196.08:29:38.31#ibcon#ireg 11 cls_cnt 2 2006.196.08:29:38.31#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.196.08:29:38.37#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.196.08:29:38.37#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.196.08:29:38.37#ibcon#enter wrdev, iclass 19, count 2 2006.196.08:29:38.37#ibcon#first serial, iclass 19, count 2 2006.196.08:29:38.37#ibcon#enter sib2, iclass 19, count 2 2006.196.08:29:38.37#ibcon#flushed, iclass 19, count 2 2006.196.08:29:38.37#ibcon#about to write, iclass 19, count 2 2006.196.08:29:38.37#ibcon#wrote, iclass 19, count 2 2006.196.08:29:38.37#ibcon#about to read 3, iclass 19, count 2 2006.196.08:29:38.39#ibcon#read 3, iclass 19, count 2 2006.196.08:29:38.39#ibcon#about to read 4, iclass 19, count 2 2006.196.08:29:38.39#ibcon#read 4, iclass 19, count 2 2006.196.08:29:38.39#ibcon#about to read 5, iclass 19, count 2 2006.196.08:29:38.39#ibcon#read 5, iclass 19, count 2 2006.196.08:29:38.39#ibcon#about to read 6, iclass 19, count 2 2006.196.08:29:38.39#ibcon#read 6, iclass 19, count 2 2006.196.08:29:38.39#ibcon#end of sib2, iclass 19, count 2 2006.196.08:29:38.39#ibcon#*mode == 0, iclass 19, count 2 2006.196.08:29:38.39#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.196.08:29:38.39#ibcon#[25=AT02-07\r\n] 2006.196.08:29:38.39#ibcon#*before write, iclass 19, count 2 2006.196.08:29:38.39#ibcon#enter sib2, iclass 19, count 2 2006.196.08:29:38.39#ibcon#flushed, iclass 19, count 2 2006.196.08:29:38.39#ibcon#about to write, iclass 19, count 2 2006.196.08:29:38.39#ibcon#wrote, iclass 19, count 2 2006.196.08:29:38.39#ibcon#about to read 3, iclass 19, count 2 2006.196.08:29:38.42#ibcon#read 3, iclass 19, count 2 2006.196.08:29:38.42#ibcon#about to read 4, iclass 19, count 2 2006.196.08:29:38.42#ibcon#read 4, iclass 19, count 2 2006.196.08:29:38.42#ibcon#about to read 5, iclass 19, count 2 2006.196.08:29:38.42#ibcon#read 5, iclass 19, count 2 2006.196.08:29:38.42#ibcon#about to read 6, iclass 19, count 2 2006.196.08:29:38.42#ibcon#read 6, iclass 19, count 2 2006.196.08:29:38.42#ibcon#end of sib2, iclass 19, count 2 2006.196.08:29:38.42#ibcon#*after write, iclass 19, count 2 2006.196.08:29:38.42#ibcon#*before return 0, iclass 19, count 2 2006.196.08:29:38.42#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.196.08:29:38.42#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.196.08:29:38.42#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.196.08:29:38.42#ibcon#ireg 7 cls_cnt 0 2006.196.08:29:38.42#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.196.08:29:38.54#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.196.08:29:38.54#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.196.08:29:38.54#ibcon#enter wrdev, iclass 19, count 0 2006.196.08:29:38.54#ibcon#first serial, iclass 19, count 0 2006.196.08:29:38.54#ibcon#enter sib2, iclass 19, count 0 2006.196.08:29:38.54#ibcon#flushed, iclass 19, count 0 2006.196.08:29:38.54#ibcon#about to write, iclass 19, count 0 2006.196.08:29:38.54#ibcon#wrote, iclass 19, count 0 2006.196.08:29:38.54#ibcon#about to read 3, iclass 19, count 0 2006.196.08:29:38.56#ibcon#read 3, iclass 19, count 0 2006.196.08:29:38.56#ibcon#about to read 4, iclass 19, count 0 2006.196.08:29:38.56#ibcon#read 4, iclass 19, count 0 2006.196.08:29:38.56#ibcon#about to read 5, iclass 19, count 0 2006.196.08:29:38.56#ibcon#read 5, iclass 19, count 0 2006.196.08:29:38.56#ibcon#about to read 6, iclass 19, count 0 2006.196.08:29:38.56#ibcon#read 6, iclass 19, count 0 2006.196.08:29:38.56#ibcon#end of sib2, iclass 19, count 0 2006.196.08:29:38.56#ibcon#*mode == 0, iclass 19, count 0 2006.196.08:29:38.56#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.196.08:29:38.56#ibcon#[25=USB\r\n] 2006.196.08:29:38.56#ibcon#*before write, iclass 19, count 0 2006.196.08:29:38.56#ibcon#enter sib2, iclass 19, count 0 2006.196.08:29:38.56#ibcon#flushed, iclass 19, count 0 2006.196.08:29:38.56#ibcon#about to write, iclass 19, count 0 2006.196.08:29:38.56#ibcon#wrote, iclass 19, count 0 2006.196.08:29:38.56#ibcon#about to read 3, iclass 19, count 0 2006.196.08:29:38.59#ibcon#read 3, iclass 19, count 0 2006.196.08:29:38.59#ibcon#about to read 4, iclass 19, count 0 2006.196.08:29:38.59#ibcon#read 4, iclass 19, count 0 2006.196.08:29:38.59#ibcon#about to read 5, iclass 19, count 0 2006.196.08:29:38.59#ibcon#read 5, iclass 19, count 0 2006.196.08:29:38.59#ibcon#about to read 6, iclass 19, count 0 2006.196.08:29:38.59#ibcon#read 6, iclass 19, count 0 2006.196.08:29:38.59#ibcon#end of sib2, iclass 19, count 0 2006.196.08:29:38.59#ibcon#*after write, iclass 19, count 0 2006.196.08:29:38.59#ibcon#*before return 0, iclass 19, count 0 2006.196.08:29:38.59#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.196.08:29:38.59#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.196.08:29:38.59#ibcon#about to clear, iclass 19 cls_cnt 0 2006.196.08:29:38.59#ibcon#cleared, iclass 19 cls_cnt 0 2006.196.08:29:38.59$vc4f8/valo=3,672.99 2006.196.08:29:38.59#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.196.08:29:38.59#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.196.08:29:38.59#ibcon#ireg 17 cls_cnt 0 2006.196.08:29:38.59#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.196.08:29:38.59#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.196.08:29:38.59#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.196.08:29:38.59#ibcon#enter wrdev, iclass 21, count 0 2006.196.08:29:38.59#ibcon#first serial, iclass 21, count 0 2006.196.08:29:38.59#ibcon#enter sib2, iclass 21, count 0 2006.196.08:29:38.59#ibcon#flushed, iclass 21, count 0 2006.196.08:29:38.59#ibcon#about to write, iclass 21, count 0 2006.196.08:29:38.59#ibcon#wrote, iclass 21, count 0 2006.196.08:29:38.59#ibcon#about to read 3, iclass 21, count 0 2006.196.08:29:38.61#ibcon#read 3, iclass 21, count 0 2006.196.08:29:38.61#ibcon#about to read 4, iclass 21, count 0 2006.196.08:29:38.61#ibcon#read 4, iclass 21, count 0 2006.196.08:29:38.61#ibcon#about to read 5, iclass 21, count 0 2006.196.08:29:38.61#ibcon#read 5, iclass 21, count 0 2006.196.08:29:38.61#ibcon#about to read 6, iclass 21, count 0 2006.196.08:29:38.61#ibcon#read 6, iclass 21, count 0 2006.196.08:29:38.61#ibcon#end of sib2, iclass 21, count 0 2006.196.08:29:38.61#ibcon#*mode == 0, iclass 21, count 0 2006.196.08:29:38.61#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.196.08:29:38.61#ibcon#[26=FRQ=03,672.99\r\n] 2006.196.08:29:38.61#ibcon#*before write, iclass 21, count 0 2006.196.08:29:38.61#ibcon#enter sib2, iclass 21, count 0 2006.196.08:29:38.61#ibcon#flushed, iclass 21, count 0 2006.196.08:29:38.61#ibcon#about to write, iclass 21, count 0 2006.196.08:29:38.61#ibcon#wrote, iclass 21, count 0 2006.196.08:29:38.61#ibcon#about to read 3, iclass 21, count 0 2006.196.08:29:38.66#ibcon#read 3, iclass 21, count 0 2006.196.08:29:38.66#ibcon#about to read 4, iclass 21, count 0 2006.196.08:29:38.66#ibcon#read 4, iclass 21, count 0 2006.196.08:29:38.66#ibcon#about to read 5, iclass 21, count 0 2006.196.08:29:38.66#ibcon#read 5, iclass 21, count 0 2006.196.08:29:38.66#ibcon#about to read 6, iclass 21, count 0 2006.196.08:29:38.66#ibcon#read 6, iclass 21, count 0 2006.196.08:29:38.66#ibcon#end of sib2, iclass 21, count 0 2006.196.08:29:38.66#ibcon#*after write, iclass 21, count 0 2006.196.08:29:38.66#ibcon#*before return 0, iclass 21, count 0 2006.196.08:29:38.66#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.196.08:29:38.66#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.196.08:29:38.66#ibcon#about to clear, iclass 21 cls_cnt 0 2006.196.08:29:38.66#ibcon#cleared, iclass 21 cls_cnt 0 2006.196.08:29:38.66$vc4f8/va=3,6 2006.196.08:29:38.66#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.196.08:29:38.66#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.196.08:29:38.66#ibcon#ireg 11 cls_cnt 2 2006.196.08:29:38.66#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.196.08:29:38.71#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.196.08:29:38.71#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.196.08:29:38.71#ibcon#enter wrdev, iclass 23, count 2 2006.196.08:29:38.71#ibcon#first serial, iclass 23, count 2 2006.196.08:29:38.71#ibcon#enter sib2, iclass 23, count 2 2006.196.08:29:38.71#ibcon#flushed, iclass 23, count 2 2006.196.08:29:38.71#ibcon#about to write, iclass 23, count 2 2006.196.08:29:38.71#ibcon#wrote, iclass 23, count 2 2006.196.08:29:38.71#ibcon#about to read 3, iclass 23, count 2 2006.196.08:29:38.73#ibcon#read 3, iclass 23, count 2 2006.196.08:29:38.73#ibcon#about to read 4, iclass 23, count 2 2006.196.08:29:38.73#ibcon#read 4, iclass 23, count 2 2006.196.08:29:38.73#ibcon#about to read 5, iclass 23, count 2 2006.196.08:29:38.73#ibcon#read 5, iclass 23, count 2 2006.196.08:29:38.73#ibcon#about to read 6, iclass 23, count 2 2006.196.08:29:38.73#ibcon#read 6, iclass 23, count 2 2006.196.08:29:38.73#ibcon#end of sib2, iclass 23, count 2 2006.196.08:29:38.73#ibcon#*mode == 0, iclass 23, count 2 2006.196.08:29:38.73#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.196.08:29:38.73#ibcon#[25=AT03-06\r\n] 2006.196.08:29:38.73#ibcon#*before write, iclass 23, count 2 2006.196.08:29:38.73#ibcon#enter sib2, iclass 23, count 2 2006.196.08:29:38.73#ibcon#flushed, iclass 23, count 2 2006.196.08:29:38.73#ibcon#about to write, iclass 23, count 2 2006.196.08:29:38.73#ibcon#wrote, iclass 23, count 2 2006.196.08:29:38.73#ibcon#about to read 3, iclass 23, count 2 2006.196.08:29:38.76#ibcon#read 3, iclass 23, count 2 2006.196.08:29:38.76#ibcon#about to read 4, iclass 23, count 2 2006.196.08:29:38.76#ibcon#read 4, iclass 23, count 2 2006.196.08:29:38.76#ibcon#about to read 5, iclass 23, count 2 2006.196.08:29:38.76#ibcon#read 5, iclass 23, count 2 2006.196.08:29:38.76#ibcon#about to read 6, iclass 23, count 2 2006.196.08:29:38.76#ibcon#read 6, iclass 23, count 2 2006.196.08:29:38.76#ibcon#end of sib2, iclass 23, count 2 2006.196.08:29:38.76#ibcon#*after write, iclass 23, count 2 2006.196.08:29:38.76#ibcon#*before return 0, iclass 23, count 2 2006.196.08:29:38.76#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.196.08:29:38.76#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.196.08:29:38.76#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.196.08:29:38.76#ibcon#ireg 7 cls_cnt 0 2006.196.08:29:38.76#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.196.08:29:38.88#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.196.08:29:38.88#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.196.08:29:38.88#ibcon#enter wrdev, iclass 23, count 0 2006.196.08:29:38.88#ibcon#first serial, iclass 23, count 0 2006.196.08:29:38.88#ibcon#enter sib2, iclass 23, count 0 2006.196.08:29:38.88#ibcon#flushed, iclass 23, count 0 2006.196.08:29:38.88#ibcon#about to write, iclass 23, count 0 2006.196.08:29:38.88#ibcon#wrote, iclass 23, count 0 2006.196.08:29:38.88#ibcon#about to read 3, iclass 23, count 0 2006.196.08:29:38.90#ibcon#read 3, iclass 23, count 0 2006.196.08:29:38.90#ibcon#about to read 4, iclass 23, count 0 2006.196.08:29:38.90#ibcon#read 4, iclass 23, count 0 2006.196.08:29:38.90#ibcon#about to read 5, iclass 23, count 0 2006.196.08:29:38.90#ibcon#read 5, iclass 23, count 0 2006.196.08:29:38.90#ibcon#about to read 6, iclass 23, count 0 2006.196.08:29:38.90#ibcon#read 6, iclass 23, count 0 2006.196.08:29:38.90#ibcon#end of sib2, iclass 23, count 0 2006.196.08:29:38.90#ibcon#*mode == 0, iclass 23, count 0 2006.196.08:29:38.90#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.196.08:29:38.90#ibcon#[25=USB\r\n] 2006.196.08:29:38.90#ibcon#*before write, iclass 23, count 0 2006.196.08:29:38.90#ibcon#enter sib2, iclass 23, count 0 2006.196.08:29:38.90#ibcon#flushed, iclass 23, count 0 2006.196.08:29:38.90#ibcon#about to write, iclass 23, count 0 2006.196.08:29:38.90#ibcon#wrote, iclass 23, count 0 2006.196.08:29:38.90#ibcon#about to read 3, iclass 23, count 0 2006.196.08:29:38.93#ibcon#read 3, iclass 23, count 0 2006.196.08:29:38.93#ibcon#about to read 4, iclass 23, count 0 2006.196.08:29:38.93#ibcon#read 4, iclass 23, count 0 2006.196.08:29:38.93#ibcon#about to read 5, iclass 23, count 0 2006.196.08:29:38.93#ibcon#read 5, iclass 23, count 0 2006.196.08:29:38.93#ibcon#about to read 6, iclass 23, count 0 2006.196.08:29:38.93#ibcon#read 6, iclass 23, count 0 2006.196.08:29:38.93#ibcon#end of sib2, iclass 23, count 0 2006.196.08:29:38.93#ibcon#*after write, iclass 23, count 0 2006.196.08:29:38.93#ibcon#*before return 0, iclass 23, count 0 2006.196.08:29:38.93#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.196.08:29:38.93#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.196.08:29:38.93#ibcon#about to clear, iclass 23 cls_cnt 0 2006.196.08:29:38.93#ibcon#cleared, iclass 23 cls_cnt 0 2006.196.08:29:38.93$vc4f8/valo=4,832.99 2006.196.08:29:38.93#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.196.08:29:38.93#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.196.08:29:38.93#ibcon#ireg 17 cls_cnt 0 2006.196.08:29:38.93#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.196.08:29:38.93#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.196.08:29:38.93#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.196.08:29:38.93#ibcon#enter wrdev, iclass 25, count 0 2006.196.08:29:38.93#ibcon#first serial, iclass 25, count 0 2006.196.08:29:38.93#ibcon#enter sib2, iclass 25, count 0 2006.196.08:29:38.93#ibcon#flushed, iclass 25, count 0 2006.196.08:29:38.93#ibcon#about to write, iclass 25, count 0 2006.196.08:29:38.93#ibcon#wrote, iclass 25, count 0 2006.196.08:29:38.93#ibcon#about to read 3, iclass 25, count 0 2006.196.08:29:38.95#ibcon#read 3, iclass 25, count 0 2006.196.08:29:38.95#ibcon#about to read 4, iclass 25, count 0 2006.196.08:29:38.95#ibcon#read 4, iclass 25, count 0 2006.196.08:29:38.95#ibcon#about to read 5, iclass 25, count 0 2006.196.08:29:38.95#ibcon#read 5, iclass 25, count 0 2006.196.08:29:38.95#ibcon#about to read 6, iclass 25, count 0 2006.196.08:29:38.95#ibcon#read 6, iclass 25, count 0 2006.196.08:29:38.95#ibcon#end of sib2, iclass 25, count 0 2006.196.08:29:38.95#ibcon#*mode == 0, iclass 25, count 0 2006.196.08:29:38.95#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.196.08:29:38.95#ibcon#[26=FRQ=04,832.99\r\n] 2006.196.08:29:38.95#ibcon#*before write, iclass 25, count 0 2006.196.08:29:38.95#ibcon#enter sib2, iclass 25, count 0 2006.196.08:29:38.95#ibcon#flushed, iclass 25, count 0 2006.196.08:29:38.95#ibcon#about to write, iclass 25, count 0 2006.196.08:29:38.95#ibcon#wrote, iclass 25, count 0 2006.196.08:29:38.95#ibcon#about to read 3, iclass 25, count 0 2006.196.08:29:38.99#ibcon#read 3, iclass 25, count 0 2006.196.08:29:38.99#ibcon#about to read 4, iclass 25, count 0 2006.196.08:29:38.99#ibcon#read 4, iclass 25, count 0 2006.196.08:29:38.99#ibcon#about to read 5, iclass 25, count 0 2006.196.08:29:38.99#ibcon#read 5, iclass 25, count 0 2006.196.08:29:38.99#ibcon#about to read 6, iclass 25, count 0 2006.196.08:29:38.99#ibcon#read 6, iclass 25, count 0 2006.196.08:29:38.99#ibcon#end of sib2, iclass 25, count 0 2006.196.08:29:38.99#ibcon#*after write, iclass 25, count 0 2006.196.08:29:38.99#ibcon#*before return 0, iclass 25, count 0 2006.196.08:29:38.99#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.196.08:29:38.99#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.196.08:29:38.99#ibcon#about to clear, iclass 25 cls_cnt 0 2006.196.08:29:38.99#ibcon#cleared, iclass 25 cls_cnt 0 2006.196.08:29:38.99$vc4f8/va=4,7 2006.196.08:29:38.99#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.196.08:29:38.99#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.196.08:29:38.99#ibcon#ireg 11 cls_cnt 2 2006.196.08:29:38.99#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.196.08:29:39.05#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.196.08:29:39.05#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.196.08:29:39.05#ibcon#enter wrdev, iclass 27, count 2 2006.196.08:29:39.05#ibcon#first serial, iclass 27, count 2 2006.196.08:29:39.05#ibcon#enter sib2, iclass 27, count 2 2006.196.08:29:39.05#ibcon#flushed, iclass 27, count 2 2006.196.08:29:39.05#ibcon#about to write, iclass 27, count 2 2006.196.08:29:39.05#ibcon#wrote, iclass 27, count 2 2006.196.08:29:39.05#ibcon#about to read 3, iclass 27, count 2 2006.196.08:29:39.07#ibcon#read 3, iclass 27, count 2 2006.196.08:29:39.07#ibcon#about to read 4, iclass 27, count 2 2006.196.08:29:39.07#ibcon#read 4, iclass 27, count 2 2006.196.08:29:39.07#ibcon#about to read 5, iclass 27, count 2 2006.196.08:29:39.07#ibcon#read 5, iclass 27, count 2 2006.196.08:29:39.07#ibcon#about to read 6, iclass 27, count 2 2006.196.08:29:39.07#ibcon#read 6, iclass 27, count 2 2006.196.08:29:39.07#ibcon#end of sib2, iclass 27, count 2 2006.196.08:29:39.07#ibcon#*mode == 0, iclass 27, count 2 2006.196.08:29:39.07#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.196.08:29:39.07#ibcon#[25=AT04-07\r\n] 2006.196.08:29:39.07#ibcon#*before write, iclass 27, count 2 2006.196.08:29:39.07#ibcon#enter sib2, iclass 27, count 2 2006.196.08:29:39.07#ibcon#flushed, iclass 27, count 2 2006.196.08:29:39.07#ibcon#about to write, iclass 27, count 2 2006.196.08:29:39.07#ibcon#wrote, iclass 27, count 2 2006.196.08:29:39.07#ibcon#about to read 3, iclass 27, count 2 2006.196.08:29:39.10#ibcon#read 3, iclass 27, count 2 2006.196.08:29:39.10#ibcon#about to read 4, iclass 27, count 2 2006.196.08:29:39.10#ibcon#read 4, iclass 27, count 2 2006.196.08:29:39.10#ibcon#about to read 5, iclass 27, count 2 2006.196.08:29:39.10#ibcon#read 5, iclass 27, count 2 2006.196.08:29:39.10#ibcon#about to read 6, iclass 27, count 2 2006.196.08:29:39.10#ibcon#read 6, iclass 27, count 2 2006.196.08:29:39.10#ibcon#end of sib2, iclass 27, count 2 2006.196.08:29:39.10#ibcon#*after write, iclass 27, count 2 2006.196.08:29:39.10#ibcon#*before return 0, iclass 27, count 2 2006.196.08:29:39.10#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.196.08:29:39.10#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.196.08:29:39.10#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.196.08:29:39.10#ibcon#ireg 7 cls_cnt 0 2006.196.08:29:39.10#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.196.08:29:39.22#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.196.08:29:39.22#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.196.08:29:39.22#ibcon#enter wrdev, iclass 27, count 0 2006.196.08:29:39.22#ibcon#first serial, iclass 27, count 0 2006.196.08:29:39.22#ibcon#enter sib2, iclass 27, count 0 2006.196.08:29:39.22#ibcon#flushed, iclass 27, count 0 2006.196.08:29:39.22#ibcon#about to write, iclass 27, count 0 2006.196.08:29:39.22#ibcon#wrote, iclass 27, count 0 2006.196.08:29:39.22#ibcon#about to read 3, iclass 27, count 0 2006.196.08:29:39.24#ibcon#read 3, iclass 27, count 0 2006.196.08:29:39.24#ibcon#about to read 4, iclass 27, count 0 2006.196.08:29:39.24#ibcon#read 4, iclass 27, count 0 2006.196.08:29:39.24#ibcon#about to read 5, iclass 27, count 0 2006.196.08:29:39.24#ibcon#read 5, iclass 27, count 0 2006.196.08:29:39.24#ibcon#about to read 6, iclass 27, count 0 2006.196.08:29:39.24#ibcon#read 6, iclass 27, count 0 2006.196.08:29:39.24#ibcon#end of sib2, iclass 27, count 0 2006.196.08:29:39.24#ibcon#*mode == 0, iclass 27, count 0 2006.196.08:29:39.24#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.196.08:29:39.24#ibcon#[25=USB\r\n] 2006.196.08:29:39.24#ibcon#*before write, iclass 27, count 0 2006.196.08:29:39.24#ibcon#enter sib2, iclass 27, count 0 2006.196.08:29:39.24#ibcon#flushed, iclass 27, count 0 2006.196.08:29:39.24#ibcon#about to write, iclass 27, count 0 2006.196.08:29:39.24#ibcon#wrote, iclass 27, count 0 2006.196.08:29:39.24#ibcon#about to read 3, iclass 27, count 0 2006.196.08:29:39.27#ibcon#read 3, iclass 27, count 0 2006.196.08:29:39.27#ibcon#about to read 4, iclass 27, count 0 2006.196.08:29:39.27#ibcon#read 4, iclass 27, count 0 2006.196.08:29:39.27#ibcon#about to read 5, iclass 27, count 0 2006.196.08:29:39.27#ibcon#read 5, iclass 27, count 0 2006.196.08:29:39.27#ibcon#about to read 6, iclass 27, count 0 2006.196.08:29:39.27#ibcon#read 6, iclass 27, count 0 2006.196.08:29:39.27#ibcon#end of sib2, iclass 27, count 0 2006.196.08:29:39.27#ibcon#*after write, iclass 27, count 0 2006.196.08:29:39.27#ibcon#*before return 0, iclass 27, count 0 2006.196.08:29:39.27#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.196.08:29:39.27#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.196.08:29:39.27#ibcon#about to clear, iclass 27 cls_cnt 0 2006.196.08:29:39.27#ibcon#cleared, iclass 27 cls_cnt 0 2006.196.08:29:39.27$vc4f8/valo=5,652.99 2006.196.08:29:39.27#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.196.08:29:39.27#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.196.08:29:39.27#ibcon#ireg 17 cls_cnt 0 2006.196.08:29:39.27#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.196.08:29:39.27#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.196.08:29:39.27#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.196.08:29:39.27#ibcon#enter wrdev, iclass 29, count 0 2006.196.08:29:39.27#ibcon#first serial, iclass 29, count 0 2006.196.08:29:39.27#ibcon#enter sib2, iclass 29, count 0 2006.196.08:29:39.27#ibcon#flushed, iclass 29, count 0 2006.196.08:29:39.27#ibcon#about to write, iclass 29, count 0 2006.196.08:29:39.27#ibcon#wrote, iclass 29, count 0 2006.196.08:29:39.27#ibcon#about to read 3, iclass 29, count 0 2006.196.08:29:39.29#ibcon#read 3, iclass 29, count 0 2006.196.08:29:39.29#ibcon#about to read 4, iclass 29, count 0 2006.196.08:29:39.29#ibcon#read 4, iclass 29, count 0 2006.196.08:29:39.29#ibcon#about to read 5, iclass 29, count 0 2006.196.08:29:39.29#ibcon#read 5, iclass 29, count 0 2006.196.08:29:39.29#ibcon#about to read 6, iclass 29, count 0 2006.196.08:29:39.29#ibcon#read 6, iclass 29, count 0 2006.196.08:29:39.29#ibcon#end of sib2, iclass 29, count 0 2006.196.08:29:39.29#ibcon#*mode == 0, iclass 29, count 0 2006.196.08:29:39.29#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.196.08:29:39.29#ibcon#[26=FRQ=05,652.99\r\n] 2006.196.08:29:39.29#ibcon#*before write, iclass 29, count 0 2006.196.08:29:39.29#ibcon#enter sib2, iclass 29, count 0 2006.196.08:29:39.29#ibcon#flushed, iclass 29, count 0 2006.196.08:29:39.29#ibcon#about to write, iclass 29, count 0 2006.196.08:29:39.29#ibcon#wrote, iclass 29, count 0 2006.196.08:29:39.29#ibcon#about to read 3, iclass 29, count 0 2006.196.08:29:39.33#ibcon#read 3, iclass 29, count 0 2006.196.08:29:39.33#ibcon#about to read 4, iclass 29, count 0 2006.196.08:29:39.33#ibcon#read 4, iclass 29, count 0 2006.196.08:29:39.33#ibcon#about to read 5, iclass 29, count 0 2006.196.08:29:39.33#ibcon#read 5, iclass 29, count 0 2006.196.08:29:39.33#ibcon#about to read 6, iclass 29, count 0 2006.196.08:29:39.33#ibcon#read 6, iclass 29, count 0 2006.196.08:29:39.33#ibcon#end of sib2, iclass 29, count 0 2006.196.08:29:39.33#ibcon#*after write, iclass 29, count 0 2006.196.08:29:39.33#ibcon#*before return 0, iclass 29, count 0 2006.196.08:29:39.33#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.196.08:29:39.33#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.196.08:29:39.33#ibcon#about to clear, iclass 29 cls_cnt 0 2006.196.08:29:39.33#ibcon#cleared, iclass 29 cls_cnt 0 2006.196.08:29:39.33$vc4f8/va=5,7 2006.196.08:29:39.33#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.196.08:29:39.33#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.196.08:29:39.33#ibcon#ireg 11 cls_cnt 2 2006.196.08:29:39.33#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.196.08:29:39.39#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.196.08:29:39.39#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.196.08:29:39.39#ibcon#enter wrdev, iclass 31, count 2 2006.196.08:29:39.39#ibcon#first serial, iclass 31, count 2 2006.196.08:29:39.39#ibcon#enter sib2, iclass 31, count 2 2006.196.08:29:39.39#ibcon#flushed, iclass 31, count 2 2006.196.08:29:39.39#ibcon#about to write, iclass 31, count 2 2006.196.08:29:39.39#ibcon#wrote, iclass 31, count 2 2006.196.08:29:39.39#ibcon#about to read 3, iclass 31, count 2 2006.196.08:29:39.41#ibcon#read 3, iclass 31, count 2 2006.196.08:29:39.41#ibcon#about to read 4, iclass 31, count 2 2006.196.08:29:39.41#ibcon#read 4, iclass 31, count 2 2006.196.08:29:39.41#ibcon#about to read 5, iclass 31, count 2 2006.196.08:29:39.41#ibcon#read 5, iclass 31, count 2 2006.196.08:29:39.41#ibcon#about to read 6, iclass 31, count 2 2006.196.08:29:39.41#ibcon#read 6, iclass 31, count 2 2006.196.08:29:39.41#ibcon#end of sib2, iclass 31, count 2 2006.196.08:29:39.41#ibcon#*mode == 0, iclass 31, count 2 2006.196.08:29:39.41#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.196.08:29:39.41#ibcon#[25=AT05-07\r\n] 2006.196.08:29:39.41#ibcon#*before write, iclass 31, count 2 2006.196.08:29:39.41#ibcon#enter sib2, iclass 31, count 2 2006.196.08:29:39.41#ibcon#flushed, iclass 31, count 2 2006.196.08:29:39.41#ibcon#about to write, iclass 31, count 2 2006.196.08:29:39.41#ibcon#wrote, iclass 31, count 2 2006.196.08:29:39.41#ibcon#about to read 3, iclass 31, count 2 2006.196.08:29:39.44#ibcon#read 3, iclass 31, count 2 2006.196.08:29:39.44#ibcon#about to read 4, iclass 31, count 2 2006.196.08:29:39.44#ibcon#read 4, iclass 31, count 2 2006.196.08:29:39.44#ibcon#about to read 5, iclass 31, count 2 2006.196.08:29:39.44#ibcon#read 5, iclass 31, count 2 2006.196.08:29:39.44#ibcon#about to read 6, iclass 31, count 2 2006.196.08:29:39.44#ibcon#read 6, iclass 31, count 2 2006.196.08:29:39.44#ibcon#end of sib2, iclass 31, count 2 2006.196.08:29:39.44#ibcon#*after write, iclass 31, count 2 2006.196.08:29:39.44#ibcon#*before return 0, iclass 31, count 2 2006.196.08:29:39.44#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.196.08:29:39.44#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.196.08:29:39.44#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.196.08:29:39.44#ibcon#ireg 7 cls_cnt 0 2006.196.08:29:39.44#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.196.08:29:39.56#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.196.08:29:39.56#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.196.08:29:39.56#ibcon#enter wrdev, iclass 31, count 0 2006.196.08:29:39.56#ibcon#first serial, iclass 31, count 0 2006.196.08:29:39.56#ibcon#enter sib2, iclass 31, count 0 2006.196.08:29:39.56#ibcon#flushed, iclass 31, count 0 2006.196.08:29:39.56#ibcon#about to write, iclass 31, count 0 2006.196.08:29:39.56#ibcon#wrote, iclass 31, count 0 2006.196.08:29:39.56#ibcon#about to read 3, iclass 31, count 0 2006.196.08:29:39.58#ibcon#read 3, iclass 31, count 0 2006.196.08:29:39.58#ibcon#about to read 4, iclass 31, count 0 2006.196.08:29:39.58#ibcon#read 4, iclass 31, count 0 2006.196.08:29:39.58#ibcon#about to read 5, iclass 31, count 0 2006.196.08:29:39.58#ibcon#read 5, iclass 31, count 0 2006.196.08:29:39.58#ibcon#about to read 6, iclass 31, count 0 2006.196.08:29:39.58#ibcon#read 6, iclass 31, count 0 2006.196.08:29:39.58#ibcon#end of sib2, iclass 31, count 0 2006.196.08:29:39.58#ibcon#*mode == 0, iclass 31, count 0 2006.196.08:29:39.58#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.196.08:29:39.58#ibcon#[25=USB\r\n] 2006.196.08:29:39.58#ibcon#*before write, iclass 31, count 0 2006.196.08:29:39.58#ibcon#enter sib2, iclass 31, count 0 2006.196.08:29:39.58#ibcon#flushed, iclass 31, count 0 2006.196.08:29:39.58#ibcon#about to write, iclass 31, count 0 2006.196.08:29:39.58#ibcon#wrote, iclass 31, count 0 2006.196.08:29:39.58#ibcon#about to read 3, iclass 31, count 0 2006.196.08:29:39.61#ibcon#read 3, iclass 31, count 0 2006.196.08:29:39.61#ibcon#about to read 4, iclass 31, count 0 2006.196.08:29:39.61#ibcon#read 4, iclass 31, count 0 2006.196.08:29:39.61#ibcon#about to read 5, iclass 31, count 0 2006.196.08:29:39.61#ibcon#read 5, iclass 31, count 0 2006.196.08:29:39.61#ibcon#about to read 6, iclass 31, count 0 2006.196.08:29:39.61#ibcon#read 6, iclass 31, count 0 2006.196.08:29:39.61#ibcon#end of sib2, iclass 31, count 0 2006.196.08:29:39.61#ibcon#*after write, iclass 31, count 0 2006.196.08:29:39.61#ibcon#*before return 0, iclass 31, count 0 2006.196.08:29:39.61#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.196.08:29:39.61#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.196.08:29:39.61#ibcon#about to clear, iclass 31 cls_cnt 0 2006.196.08:29:39.61#ibcon#cleared, iclass 31 cls_cnt 0 2006.196.08:29:39.61$vc4f8/valo=6,772.99 2006.196.08:29:39.61#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.196.08:29:39.61#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.196.08:29:39.61#ibcon#ireg 17 cls_cnt 0 2006.196.08:29:39.61#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:29:39.61#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:29:39.61#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:29:39.61#ibcon#enter wrdev, iclass 33, count 0 2006.196.08:29:39.61#ibcon#first serial, iclass 33, count 0 2006.196.08:29:39.61#ibcon#enter sib2, iclass 33, count 0 2006.196.08:29:39.61#ibcon#flushed, iclass 33, count 0 2006.196.08:29:39.61#ibcon#about to write, iclass 33, count 0 2006.196.08:29:39.61#ibcon#wrote, iclass 33, count 0 2006.196.08:29:39.61#ibcon#about to read 3, iclass 33, count 0 2006.196.08:29:39.63#ibcon#read 3, iclass 33, count 0 2006.196.08:29:39.63#ibcon#about to read 4, iclass 33, count 0 2006.196.08:29:39.63#ibcon#read 4, iclass 33, count 0 2006.196.08:29:39.63#ibcon#about to read 5, iclass 33, count 0 2006.196.08:29:39.63#ibcon#read 5, iclass 33, count 0 2006.196.08:29:39.63#ibcon#about to read 6, iclass 33, count 0 2006.196.08:29:39.63#ibcon#read 6, iclass 33, count 0 2006.196.08:29:39.63#ibcon#end of sib2, iclass 33, count 0 2006.196.08:29:39.63#ibcon#*mode == 0, iclass 33, count 0 2006.196.08:29:39.63#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.196.08:29:39.63#ibcon#[26=FRQ=06,772.99\r\n] 2006.196.08:29:39.63#ibcon#*before write, iclass 33, count 0 2006.196.08:29:39.63#ibcon#enter sib2, iclass 33, count 0 2006.196.08:29:39.63#ibcon#flushed, iclass 33, count 0 2006.196.08:29:39.63#ibcon#about to write, iclass 33, count 0 2006.196.08:29:39.63#ibcon#wrote, iclass 33, count 0 2006.196.08:29:39.63#ibcon#about to read 3, iclass 33, count 0 2006.196.08:29:39.67#ibcon#read 3, iclass 33, count 0 2006.196.08:29:39.67#ibcon#about to read 4, iclass 33, count 0 2006.196.08:29:39.67#ibcon#read 4, iclass 33, count 0 2006.196.08:29:39.67#ibcon#about to read 5, iclass 33, count 0 2006.196.08:29:39.67#ibcon#read 5, iclass 33, count 0 2006.196.08:29:39.67#ibcon#about to read 6, iclass 33, count 0 2006.196.08:29:39.67#ibcon#read 6, iclass 33, count 0 2006.196.08:29:39.67#ibcon#end of sib2, iclass 33, count 0 2006.196.08:29:39.67#ibcon#*after write, iclass 33, count 0 2006.196.08:29:39.67#ibcon#*before return 0, iclass 33, count 0 2006.196.08:29:39.67#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:29:39.67#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:29:39.67#ibcon#about to clear, iclass 33 cls_cnt 0 2006.196.08:29:39.67#ibcon#cleared, iclass 33 cls_cnt 0 2006.196.08:29:39.67$vc4f8/va=6,6 2006.196.08:29:39.67#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.196.08:29:39.67#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.196.08:29:39.67#ibcon#ireg 11 cls_cnt 2 2006.196.08:29:39.67#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.196.08:29:39.73#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.196.08:29:39.73#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.196.08:29:39.73#ibcon#enter wrdev, iclass 35, count 2 2006.196.08:29:39.73#ibcon#first serial, iclass 35, count 2 2006.196.08:29:39.73#ibcon#enter sib2, iclass 35, count 2 2006.196.08:29:39.73#ibcon#flushed, iclass 35, count 2 2006.196.08:29:39.73#ibcon#about to write, iclass 35, count 2 2006.196.08:29:39.73#ibcon#wrote, iclass 35, count 2 2006.196.08:29:39.73#ibcon#about to read 3, iclass 35, count 2 2006.196.08:29:39.75#ibcon#read 3, iclass 35, count 2 2006.196.08:29:39.75#ibcon#about to read 4, iclass 35, count 2 2006.196.08:29:39.75#ibcon#read 4, iclass 35, count 2 2006.196.08:29:39.75#ibcon#about to read 5, iclass 35, count 2 2006.196.08:29:39.75#ibcon#read 5, iclass 35, count 2 2006.196.08:29:39.75#ibcon#about to read 6, iclass 35, count 2 2006.196.08:29:39.75#ibcon#read 6, iclass 35, count 2 2006.196.08:29:39.75#ibcon#end of sib2, iclass 35, count 2 2006.196.08:29:39.75#ibcon#*mode == 0, iclass 35, count 2 2006.196.08:29:39.75#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.196.08:29:39.75#ibcon#[25=AT06-06\r\n] 2006.196.08:29:39.75#ibcon#*before write, iclass 35, count 2 2006.196.08:29:39.75#ibcon#enter sib2, iclass 35, count 2 2006.196.08:29:39.75#ibcon#flushed, iclass 35, count 2 2006.196.08:29:39.75#ibcon#about to write, iclass 35, count 2 2006.196.08:29:39.75#ibcon#wrote, iclass 35, count 2 2006.196.08:29:39.75#ibcon#about to read 3, iclass 35, count 2 2006.196.08:29:39.78#ibcon#read 3, iclass 35, count 2 2006.196.08:29:39.78#ibcon#about to read 4, iclass 35, count 2 2006.196.08:29:39.78#ibcon#read 4, iclass 35, count 2 2006.196.08:29:39.78#ibcon#about to read 5, iclass 35, count 2 2006.196.08:29:39.78#ibcon#read 5, iclass 35, count 2 2006.196.08:29:39.78#ibcon#about to read 6, iclass 35, count 2 2006.196.08:29:39.78#ibcon#read 6, iclass 35, count 2 2006.196.08:29:39.78#ibcon#end of sib2, iclass 35, count 2 2006.196.08:29:39.78#ibcon#*after write, iclass 35, count 2 2006.196.08:29:39.78#ibcon#*before return 0, iclass 35, count 2 2006.196.08:29:39.78#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.196.08:29:39.78#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.196.08:29:39.78#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.196.08:29:39.78#ibcon#ireg 7 cls_cnt 0 2006.196.08:29:39.78#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.196.08:29:39.90#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.196.08:29:39.90#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.196.08:29:39.90#ibcon#enter wrdev, iclass 35, count 0 2006.196.08:29:39.90#ibcon#first serial, iclass 35, count 0 2006.196.08:29:39.90#ibcon#enter sib2, iclass 35, count 0 2006.196.08:29:39.90#ibcon#flushed, iclass 35, count 0 2006.196.08:29:39.90#ibcon#about to write, iclass 35, count 0 2006.196.08:29:39.90#ibcon#wrote, iclass 35, count 0 2006.196.08:29:39.90#ibcon#about to read 3, iclass 35, count 0 2006.196.08:29:39.92#ibcon#read 3, iclass 35, count 0 2006.196.08:29:39.92#ibcon#about to read 4, iclass 35, count 0 2006.196.08:29:39.92#ibcon#read 4, iclass 35, count 0 2006.196.08:29:39.92#ibcon#about to read 5, iclass 35, count 0 2006.196.08:29:39.92#ibcon#read 5, iclass 35, count 0 2006.196.08:29:39.92#ibcon#about to read 6, iclass 35, count 0 2006.196.08:29:39.92#ibcon#read 6, iclass 35, count 0 2006.196.08:29:39.92#ibcon#end of sib2, iclass 35, count 0 2006.196.08:29:39.92#ibcon#*mode == 0, iclass 35, count 0 2006.196.08:29:39.92#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.196.08:29:39.92#ibcon#[25=USB\r\n] 2006.196.08:29:39.92#ibcon#*before write, iclass 35, count 0 2006.196.08:29:39.92#ibcon#enter sib2, iclass 35, count 0 2006.196.08:29:39.92#ibcon#flushed, iclass 35, count 0 2006.196.08:29:39.92#ibcon#about to write, iclass 35, count 0 2006.196.08:29:39.92#ibcon#wrote, iclass 35, count 0 2006.196.08:29:39.92#ibcon#about to read 3, iclass 35, count 0 2006.196.08:29:39.95#ibcon#read 3, iclass 35, count 0 2006.196.08:29:39.95#ibcon#about to read 4, iclass 35, count 0 2006.196.08:29:39.95#ibcon#read 4, iclass 35, count 0 2006.196.08:29:39.95#ibcon#about to read 5, iclass 35, count 0 2006.196.08:29:39.95#ibcon#read 5, iclass 35, count 0 2006.196.08:29:39.95#ibcon#about to read 6, iclass 35, count 0 2006.196.08:29:39.95#ibcon#read 6, iclass 35, count 0 2006.196.08:29:39.95#ibcon#end of sib2, iclass 35, count 0 2006.196.08:29:39.95#ibcon#*after write, iclass 35, count 0 2006.196.08:29:39.95#ibcon#*before return 0, iclass 35, count 0 2006.196.08:29:39.95#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.196.08:29:39.95#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.196.08:29:39.95#ibcon#about to clear, iclass 35 cls_cnt 0 2006.196.08:29:39.95#ibcon#cleared, iclass 35 cls_cnt 0 2006.196.08:29:39.95$vc4f8/valo=7,832.99 2006.196.08:29:39.95#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.196.08:29:39.95#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.196.08:29:39.95#ibcon#ireg 17 cls_cnt 0 2006.196.08:29:39.95#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.196.08:29:39.95#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.196.08:29:39.95#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.196.08:29:39.95#ibcon#enter wrdev, iclass 37, count 0 2006.196.08:29:39.95#ibcon#first serial, iclass 37, count 0 2006.196.08:29:39.95#ibcon#enter sib2, iclass 37, count 0 2006.196.08:29:39.95#ibcon#flushed, iclass 37, count 0 2006.196.08:29:39.95#ibcon#about to write, iclass 37, count 0 2006.196.08:29:39.95#ibcon#wrote, iclass 37, count 0 2006.196.08:29:39.95#ibcon#about to read 3, iclass 37, count 0 2006.196.08:29:39.97#ibcon#read 3, iclass 37, count 0 2006.196.08:29:39.97#ibcon#about to read 4, iclass 37, count 0 2006.196.08:29:39.97#ibcon#read 4, iclass 37, count 0 2006.196.08:29:39.97#ibcon#about to read 5, iclass 37, count 0 2006.196.08:29:39.97#ibcon#read 5, iclass 37, count 0 2006.196.08:29:39.97#ibcon#about to read 6, iclass 37, count 0 2006.196.08:29:39.97#ibcon#read 6, iclass 37, count 0 2006.196.08:29:39.97#ibcon#end of sib2, iclass 37, count 0 2006.196.08:29:39.97#ibcon#*mode == 0, iclass 37, count 0 2006.196.08:29:39.97#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.196.08:29:39.97#ibcon#[26=FRQ=07,832.99\r\n] 2006.196.08:29:39.97#ibcon#*before write, iclass 37, count 0 2006.196.08:29:39.97#ibcon#enter sib2, iclass 37, count 0 2006.196.08:29:39.97#ibcon#flushed, iclass 37, count 0 2006.196.08:29:39.97#ibcon#about to write, iclass 37, count 0 2006.196.08:29:39.97#ibcon#wrote, iclass 37, count 0 2006.196.08:29:39.97#ibcon#about to read 3, iclass 37, count 0 2006.196.08:29:40.01#ibcon#read 3, iclass 37, count 0 2006.196.08:29:40.01#ibcon#about to read 4, iclass 37, count 0 2006.196.08:29:40.01#ibcon#read 4, iclass 37, count 0 2006.196.08:29:40.01#ibcon#about to read 5, iclass 37, count 0 2006.196.08:29:40.01#ibcon#read 5, iclass 37, count 0 2006.196.08:29:40.01#ibcon#about to read 6, iclass 37, count 0 2006.196.08:29:40.01#ibcon#read 6, iclass 37, count 0 2006.196.08:29:40.01#ibcon#end of sib2, iclass 37, count 0 2006.196.08:29:40.01#ibcon#*after write, iclass 37, count 0 2006.196.08:29:40.01#ibcon#*before return 0, iclass 37, count 0 2006.196.08:29:40.01#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.196.08:29:40.01#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.196.08:29:40.01#ibcon#about to clear, iclass 37 cls_cnt 0 2006.196.08:29:40.01#ibcon#cleared, iclass 37 cls_cnt 0 2006.196.08:29:40.01$vc4f8/va=7,6 2006.196.08:29:40.01#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.196.08:29:40.01#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.196.08:29:40.01#ibcon#ireg 11 cls_cnt 2 2006.196.08:29:40.01#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.196.08:29:40.07#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.196.08:29:40.07#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.196.08:29:40.07#ibcon#enter wrdev, iclass 39, count 2 2006.196.08:29:40.07#ibcon#first serial, iclass 39, count 2 2006.196.08:29:40.07#ibcon#enter sib2, iclass 39, count 2 2006.196.08:29:40.07#ibcon#flushed, iclass 39, count 2 2006.196.08:29:40.07#ibcon#about to write, iclass 39, count 2 2006.196.08:29:40.07#ibcon#wrote, iclass 39, count 2 2006.196.08:29:40.07#ibcon#about to read 3, iclass 39, count 2 2006.196.08:29:40.09#ibcon#read 3, iclass 39, count 2 2006.196.08:29:40.09#ibcon#about to read 4, iclass 39, count 2 2006.196.08:29:40.09#ibcon#read 4, iclass 39, count 2 2006.196.08:29:40.09#ibcon#about to read 5, iclass 39, count 2 2006.196.08:29:40.09#ibcon#read 5, iclass 39, count 2 2006.196.08:29:40.09#ibcon#about to read 6, iclass 39, count 2 2006.196.08:29:40.09#ibcon#read 6, iclass 39, count 2 2006.196.08:29:40.09#ibcon#end of sib2, iclass 39, count 2 2006.196.08:29:40.09#ibcon#*mode == 0, iclass 39, count 2 2006.196.08:29:40.09#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.196.08:29:40.09#ibcon#[25=AT07-06\r\n] 2006.196.08:29:40.09#ibcon#*before write, iclass 39, count 2 2006.196.08:29:40.09#ibcon#enter sib2, iclass 39, count 2 2006.196.08:29:40.09#ibcon#flushed, iclass 39, count 2 2006.196.08:29:40.09#ibcon#about to write, iclass 39, count 2 2006.196.08:29:40.09#ibcon#wrote, iclass 39, count 2 2006.196.08:29:40.09#ibcon#about to read 3, iclass 39, count 2 2006.196.08:29:40.12#ibcon#read 3, iclass 39, count 2 2006.196.08:29:40.12#ibcon#about to read 4, iclass 39, count 2 2006.196.08:29:40.12#ibcon#read 4, iclass 39, count 2 2006.196.08:29:40.12#ibcon#about to read 5, iclass 39, count 2 2006.196.08:29:40.12#ibcon#read 5, iclass 39, count 2 2006.196.08:29:40.12#ibcon#about to read 6, iclass 39, count 2 2006.196.08:29:40.12#ibcon#read 6, iclass 39, count 2 2006.196.08:29:40.12#ibcon#end of sib2, iclass 39, count 2 2006.196.08:29:40.12#ibcon#*after write, iclass 39, count 2 2006.196.08:29:40.12#ibcon#*before return 0, iclass 39, count 2 2006.196.08:29:40.12#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.196.08:29:40.12#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.196.08:29:40.12#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.196.08:29:40.12#ibcon#ireg 7 cls_cnt 0 2006.196.08:29:40.12#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.196.08:29:40.24#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.196.08:29:40.24#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.196.08:29:40.24#ibcon#enter wrdev, iclass 39, count 0 2006.196.08:29:40.24#ibcon#first serial, iclass 39, count 0 2006.196.08:29:40.24#ibcon#enter sib2, iclass 39, count 0 2006.196.08:29:40.24#ibcon#flushed, iclass 39, count 0 2006.196.08:29:40.24#ibcon#about to write, iclass 39, count 0 2006.196.08:29:40.24#ibcon#wrote, iclass 39, count 0 2006.196.08:29:40.24#ibcon#about to read 3, iclass 39, count 0 2006.196.08:29:40.26#ibcon#read 3, iclass 39, count 0 2006.196.08:29:40.26#ibcon#about to read 4, iclass 39, count 0 2006.196.08:29:40.26#ibcon#read 4, iclass 39, count 0 2006.196.08:29:40.26#ibcon#about to read 5, iclass 39, count 0 2006.196.08:29:40.26#ibcon#read 5, iclass 39, count 0 2006.196.08:29:40.26#ibcon#about to read 6, iclass 39, count 0 2006.196.08:29:40.26#ibcon#read 6, iclass 39, count 0 2006.196.08:29:40.26#ibcon#end of sib2, iclass 39, count 0 2006.196.08:29:40.26#ibcon#*mode == 0, iclass 39, count 0 2006.196.08:29:40.26#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.196.08:29:40.26#ibcon#[25=USB\r\n] 2006.196.08:29:40.26#ibcon#*before write, iclass 39, count 0 2006.196.08:29:40.26#ibcon#enter sib2, iclass 39, count 0 2006.196.08:29:40.26#ibcon#flushed, iclass 39, count 0 2006.196.08:29:40.26#ibcon#about to write, iclass 39, count 0 2006.196.08:29:40.26#ibcon#wrote, iclass 39, count 0 2006.196.08:29:40.26#ibcon#about to read 3, iclass 39, count 0 2006.196.08:29:40.29#ibcon#read 3, iclass 39, count 0 2006.196.08:29:40.29#ibcon#about to read 4, iclass 39, count 0 2006.196.08:29:40.29#ibcon#read 4, iclass 39, count 0 2006.196.08:29:40.29#ibcon#about to read 5, iclass 39, count 0 2006.196.08:29:40.29#ibcon#read 5, iclass 39, count 0 2006.196.08:29:40.29#ibcon#about to read 6, iclass 39, count 0 2006.196.08:29:40.29#ibcon#read 6, iclass 39, count 0 2006.196.08:29:40.29#ibcon#end of sib2, iclass 39, count 0 2006.196.08:29:40.29#ibcon#*after write, iclass 39, count 0 2006.196.08:29:40.29#ibcon#*before return 0, iclass 39, count 0 2006.196.08:29:40.29#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.196.08:29:40.29#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.196.08:29:40.29#ibcon#about to clear, iclass 39 cls_cnt 0 2006.196.08:29:40.29#ibcon#cleared, iclass 39 cls_cnt 0 2006.196.08:29:40.29$vc4f8/valo=8,852.99 2006.196.08:29:40.29#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.196.08:29:40.29#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.196.08:29:40.29#ibcon#ireg 17 cls_cnt 0 2006.196.08:29:40.29#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.196.08:29:40.29#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.196.08:29:40.29#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.196.08:29:40.29#ibcon#enter wrdev, iclass 3, count 0 2006.196.08:29:40.29#ibcon#first serial, iclass 3, count 0 2006.196.08:29:40.29#ibcon#enter sib2, iclass 3, count 0 2006.196.08:29:40.29#ibcon#flushed, iclass 3, count 0 2006.196.08:29:40.29#ibcon#about to write, iclass 3, count 0 2006.196.08:29:40.29#ibcon#wrote, iclass 3, count 0 2006.196.08:29:40.29#ibcon#about to read 3, iclass 3, count 0 2006.196.08:29:40.31#ibcon#read 3, iclass 3, count 0 2006.196.08:29:40.31#ibcon#about to read 4, iclass 3, count 0 2006.196.08:29:40.31#ibcon#read 4, iclass 3, count 0 2006.196.08:29:40.31#ibcon#about to read 5, iclass 3, count 0 2006.196.08:29:40.31#ibcon#read 5, iclass 3, count 0 2006.196.08:29:40.31#ibcon#about to read 6, iclass 3, count 0 2006.196.08:29:40.31#ibcon#read 6, iclass 3, count 0 2006.196.08:29:40.31#ibcon#end of sib2, iclass 3, count 0 2006.196.08:29:40.31#ibcon#*mode == 0, iclass 3, count 0 2006.196.08:29:40.31#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.196.08:29:40.31#ibcon#[26=FRQ=08,852.99\r\n] 2006.196.08:29:40.31#ibcon#*before write, iclass 3, count 0 2006.196.08:29:40.31#ibcon#enter sib2, iclass 3, count 0 2006.196.08:29:40.31#ibcon#flushed, iclass 3, count 0 2006.196.08:29:40.31#ibcon#about to write, iclass 3, count 0 2006.196.08:29:40.31#ibcon#wrote, iclass 3, count 0 2006.196.08:29:40.31#ibcon#about to read 3, iclass 3, count 0 2006.196.08:29:40.35#ibcon#read 3, iclass 3, count 0 2006.196.08:29:40.35#ibcon#about to read 4, iclass 3, count 0 2006.196.08:29:40.35#ibcon#read 4, iclass 3, count 0 2006.196.08:29:40.35#ibcon#about to read 5, iclass 3, count 0 2006.196.08:29:40.35#ibcon#read 5, iclass 3, count 0 2006.196.08:29:40.35#ibcon#about to read 6, iclass 3, count 0 2006.196.08:29:40.35#ibcon#read 6, iclass 3, count 0 2006.196.08:29:40.35#ibcon#end of sib2, iclass 3, count 0 2006.196.08:29:40.35#ibcon#*after write, iclass 3, count 0 2006.196.08:29:40.35#ibcon#*before return 0, iclass 3, count 0 2006.196.08:29:40.35#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.196.08:29:40.35#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.196.08:29:40.35#ibcon#about to clear, iclass 3 cls_cnt 0 2006.196.08:29:40.35#ibcon#cleared, iclass 3 cls_cnt 0 2006.196.08:29:40.35$vc4f8/va=8,7 2006.196.08:29:40.35#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.196.08:29:40.35#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.196.08:29:40.35#ibcon#ireg 11 cls_cnt 2 2006.196.08:29:40.35#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.196.08:29:40.41#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.196.08:29:40.41#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.196.08:29:40.41#ibcon#enter wrdev, iclass 5, count 2 2006.196.08:29:40.41#ibcon#first serial, iclass 5, count 2 2006.196.08:29:40.41#ibcon#enter sib2, iclass 5, count 2 2006.196.08:29:40.41#ibcon#flushed, iclass 5, count 2 2006.196.08:29:40.41#ibcon#about to write, iclass 5, count 2 2006.196.08:29:40.41#ibcon#wrote, iclass 5, count 2 2006.196.08:29:40.41#ibcon#about to read 3, iclass 5, count 2 2006.196.08:29:40.43#ibcon#read 3, iclass 5, count 2 2006.196.08:29:40.43#ibcon#about to read 4, iclass 5, count 2 2006.196.08:29:40.43#ibcon#read 4, iclass 5, count 2 2006.196.08:29:40.43#ibcon#about to read 5, iclass 5, count 2 2006.196.08:29:40.43#ibcon#read 5, iclass 5, count 2 2006.196.08:29:40.43#ibcon#about to read 6, iclass 5, count 2 2006.196.08:29:40.43#ibcon#read 6, iclass 5, count 2 2006.196.08:29:40.43#ibcon#end of sib2, iclass 5, count 2 2006.196.08:29:40.43#ibcon#*mode == 0, iclass 5, count 2 2006.196.08:29:40.43#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.196.08:29:40.43#ibcon#[25=AT08-07\r\n] 2006.196.08:29:40.43#ibcon#*before write, iclass 5, count 2 2006.196.08:29:40.43#ibcon#enter sib2, iclass 5, count 2 2006.196.08:29:40.43#ibcon#flushed, iclass 5, count 2 2006.196.08:29:40.43#ibcon#about to write, iclass 5, count 2 2006.196.08:29:40.43#ibcon#wrote, iclass 5, count 2 2006.196.08:29:40.43#ibcon#about to read 3, iclass 5, count 2 2006.196.08:29:40.46#ibcon#read 3, iclass 5, count 2 2006.196.08:29:40.46#ibcon#about to read 4, iclass 5, count 2 2006.196.08:29:40.46#ibcon#read 4, iclass 5, count 2 2006.196.08:29:40.46#ibcon#about to read 5, iclass 5, count 2 2006.196.08:29:40.46#ibcon#read 5, iclass 5, count 2 2006.196.08:29:40.46#ibcon#about to read 6, iclass 5, count 2 2006.196.08:29:40.46#ibcon#read 6, iclass 5, count 2 2006.196.08:29:40.46#ibcon#end of sib2, iclass 5, count 2 2006.196.08:29:40.46#ibcon#*after write, iclass 5, count 2 2006.196.08:29:40.46#ibcon#*before return 0, iclass 5, count 2 2006.196.08:29:40.46#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.196.08:29:40.46#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.196.08:29:40.46#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.196.08:29:40.46#ibcon#ireg 7 cls_cnt 0 2006.196.08:29:40.46#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.196.08:29:40.58#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.196.08:29:40.58#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.196.08:29:40.58#ibcon#enter wrdev, iclass 5, count 0 2006.196.08:29:40.58#ibcon#first serial, iclass 5, count 0 2006.196.08:29:40.58#ibcon#enter sib2, iclass 5, count 0 2006.196.08:29:40.58#ibcon#flushed, iclass 5, count 0 2006.196.08:29:40.58#ibcon#about to write, iclass 5, count 0 2006.196.08:29:40.58#ibcon#wrote, iclass 5, count 0 2006.196.08:29:40.58#ibcon#about to read 3, iclass 5, count 0 2006.196.08:29:40.60#ibcon#read 3, iclass 5, count 0 2006.196.08:29:40.60#ibcon#about to read 4, iclass 5, count 0 2006.196.08:29:40.60#ibcon#read 4, iclass 5, count 0 2006.196.08:29:40.60#ibcon#about to read 5, iclass 5, count 0 2006.196.08:29:40.60#ibcon#read 5, iclass 5, count 0 2006.196.08:29:40.60#ibcon#about to read 6, iclass 5, count 0 2006.196.08:29:40.60#ibcon#read 6, iclass 5, count 0 2006.196.08:29:40.60#ibcon#end of sib2, iclass 5, count 0 2006.196.08:29:40.60#ibcon#*mode == 0, iclass 5, count 0 2006.196.08:29:40.60#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.196.08:29:40.60#ibcon#[25=USB\r\n] 2006.196.08:29:40.60#ibcon#*before write, iclass 5, count 0 2006.196.08:29:40.60#ibcon#enter sib2, iclass 5, count 0 2006.196.08:29:40.60#ibcon#flushed, iclass 5, count 0 2006.196.08:29:40.60#ibcon#about to write, iclass 5, count 0 2006.196.08:29:40.60#ibcon#wrote, iclass 5, count 0 2006.196.08:29:40.60#ibcon#about to read 3, iclass 5, count 0 2006.196.08:29:40.63#ibcon#read 3, iclass 5, count 0 2006.196.08:29:40.63#ibcon#about to read 4, iclass 5, count 0 2006.196.08:29:40.63#ibcon#read 4, iclass 5, count 0 2006.196.08:29:40.63#ibcon#about to read 5, iclass 5, count 0 2006.196.08:29:40.63#ibcon#read 5, iclass 5, count 0 2006.196.08:29:40.63#ibcon#about to read 6, iclass 5, count 0 2006.196.08:29:40.63#ibcon#read 6, iclass 5, count 0 2006.196.08:29:40.63#ibcon#end of sib2, iclass 5, count 0 2006.196.08:29:40.63#ibcon#*after write, iclass 5, count 0 2006.196.08:29:40.63#ibcon#*before return 0, iclass 5, count 0 2006.196.08:29:40.63#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.196.08:29:40.63#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.196.08:29:40.63#ibcon#about to clear, iclass 5 cls_cnt 0 2006.196.08:29:40.63#ibcon#cleared, iclass 5 cls_cnt 0 2006.196.08:29:40.63$vc4f8/vblo=1,632.99 2006.196.08:29:40.63#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.196.08:29:40.63#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.196.08:29:40.63#ibcon#ireg 17 cls_cnt 0 2006.196.08:29:40.63#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.196.08:29:40.63#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.196.08:29:40.63#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.196.08:29:40.63#ibcon#enter wrdev, iclass 7, count 0 2006.196.08:29:40.63#ibcon#first serial, iclass 7, count 0 2006.196.08:29:40.63#ibcon#enter sib2, iclass 7, count 0 2006.196.08:29:40.63#ibcon#flushed, iclass 7, count 0 2006.196.08:29:40.63#ibcon#about to write, iclass 7, count 0 2006.196.08:29:40.63#ibcon#wrote, iclass 7, count 0 2006.196.08:29:40.63#ibcon#about to read 3, iclass 7, count 0 2006.196.08:29:40.65#ibcon#read 3, iclass 7, count 0 2006.196.08:29:40.65#ibcon#about to read 4, iclass 7, count 0 2006.196.08:29:40.65#ibcon#read 4, iclass 7, count 0 2006.196.08:29:40.65#ibcon#about to read 5, iclass 7, count 0 2006.196.08:29:40.65#ibcon#read 5, iclass 7, count 0 2006.196.08:29:40.65#ibcon#about to read 6, iclass 7, count 0 2006.196.08:29:40.65#ibcon#read 6, iclass 7, count 0 2006.196.08:29:40.65#ibcon#end of sib2, iclass 7, count 0 2006.196.08:29:40.65#ibcon#*mode == 0, iclass 7, count 0 2006.196.08:29:40.65#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.196.08:29:40.65#ibcon#[28=FRQ=01,632.99\r\n] 2006.196.08:29:40.65#ibcon#*before write, iclass 7, count 0 2006.196.08:29:40.65#ibcon#enter sib2, iclass 7, count 0 2006.196.08:29:40.65#ibcon#flushed, iclass 7, count 0 2006.196.08:29:40.65#ibcon#about to write, iclass 7, count 0 2006.196.08:29:40.65#ibcon#wrote, iclass 7, count 0 2006.196.08:29:40.65#ibcon#about to read 3, iclass 7, count 0 2006.196.08:29:40.69#ibcon#read 3, iclass 7, count 0 2006.196.08:29:40.69#ibcon#about to read 4, iclass 7, count 0 2006.196.08:29:40.69#ibcon#read 4, iclass 7, count 0 2006.196.08:29:40.69#ibcon#about to read 5, iclass 7, count 0 2006.196.08:29:40.69#ibcon#read 5, iclass 7, count 0 2006.196.08:29:40.69#ibcon#about to read 6, iclass 7, count 0 2006.196.08:29:40.69#ibcon#read 6, iclass 7, count 0 2006.196.08:29:40.69#ibcon#end of sib2, iclass 7, count 0 2006.196.08:29:40.69#ibcon#*after write, iclass 7, count 0 2006.196.08:29:40.69#ibcon#*before return 0, iclass 7, count 0 2006.196.08:29:40.69#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.196.08:29:40.69#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.196.08:29:40.69#ibcon#about to clear, iclass 7 cls_cnt 0 2006.196.08:29:40.69#ibcon#cleared, iclass 7 cls_cnt 0 2006.196.08:29:40.69$vc4f8/vb=1,4 2006.196.08:29:40.69#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.196.08:29:40.69#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.196.08:29:40.69#ibcon#ireg 11 cls_cnt 2 2006.196.08:29:40.69#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.196.08:29:40.69#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.196.08:29:40.69#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.196.08:29:40.69#ibcon#enter wrdev, iclass 11, count 2 2006.196.08:29:40.69#ibcon#first serial, iclass 11, count 2 2006.196.08:29:40.69#ibcon#enter sib2, iclass 11, count 2 2006.196.08:29:40.69#ibcon#flushed, iclass 11, count 2 2006.196.08:29:40.69#ibcon#about to write, iclass 11, count 2 2006.196.08:29:40.69#ibcon#wrote, iclass 11, count 2 2006.196.08:29:40.69#ibcon#about to read 3, iclass 11, count 2 2006.196.08:29:40.71#ibcon#read 3, iclass 11, count 2 2006.196.08:29:40.71#ibcon#about to read 4, iclass 11, count 2 2006.196.08:29:40.71#ibcon#read 4, iclass 11, count 2 2006.196.08:29:40.71#ibcon#about to read 5, iclass 11, count 2 2006.196.08:29:40.71#ibcon#read 5, iclass 11, count 2 2006.196.08:29:40.71#ibcon#about to read 6, iclass 11, count 2 2006.196.08:29:40.71#ibcon#read 6, iclass 11, count 2 2006.196.08:29:40.71#ibcon#end of sib2, iclass 11, count 2 2006.196.08:29:40.71#ibcon#*mode == 0, iclass 11, count 2 2006.196.08:29:40.71#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.196.08:29:40.71#ibcon#[27=AT01-04\r\n] 2006.196.08:29:40.71#ibcon#*before write, iclass 11, count 2 2006.196.08:29:40.71#ibcon#enter sib2, iclass 11, count 2 2006.196.08:29:40.71#ibcon#flushed, iclass 11, count 2 2006.196.08:29:40.71#ibcon#about to write, iclass 11, count 2 2006.196.08:29:40.71#ibcon#wrote, iclass 11, count 2 2006.196.08:29:40.71#ibcon#about to read 3, iclass 11, count 2 2006.196.08:29:40.74#ibcon#read 3, iclass 11, count 2 2006.196.08:29:40.74#ibcon#about to read 4, iclass 11, count 2 2006.196.08:29:40.74#ibcon#read 4, iclass 11, count 2 2006.196.08:29:40.74#ibcon#about to read 5, iclass 11, count 2 2006.196.08:29:40.74#ibcon#read 5, iclass 11, count 2 2006.196.08:29:40.74#ibcon#about to read 6, iclass 11, count 2 2006.196.08:29:40.74#ibcon#read 6, iclass 11, count 2 2006.196.08:29:40.74#ibcon#end of sib2, iclass 11, count 2 2006.196.08:29:40.74#ibcon#*after write, iclass 11, count 2 2006.196.08:29:40.74#ibcon#*before return 0, iclass 11, count 2 2006.196.08:29:40.74#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.196.08:29:40.74#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.196.08:29:40.74#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.196.08:29:40.74#ibcon#ireg 7 cls_cnt 0 2006.196.08:29:40.74#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.196.08:29:40.86#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.196.08:29:40.86#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.196.08:29:40.86#ibcon#enter wrdev, iclass 11, count 0 2006.196.08:29:40.86#ibcon#first serial, iclass 11, count 0 2006.196.08:29:40.86#ibcon#enter sib2, iclass 11, count 0 2006.196.08:29:40.86#ibcon#flushed, iclass 11, count 0 2006.196.08:29:40.86#ibcon#about to write, iclass 11, count 0 2006.196.08:29:40.86#ibcon#wrote, iclass 11, count 0 2006.196.08:29:40.86#ibcon#about to read 3, iclass 11, count 0 2006.196.08:29:40.88#ibcon#read 3, iclass 11, count 0 2006.196.08:29:40.88#ibcon#about to read 4, iclass 11, count 0 2006.196.08:29:40.88#ibcon#read 4, iclass 11, count 0 2006.196.08:29:40.88#ibcon#about to read 5, iclass 11, count 0 2006.196.08:29:40.88#ibcon#read 5, iclass 11, count 0 2006.196.08:29:40.88#ibcon#about to read 6, iclass 11, count 0 2006.196.08:29:40.88#ibcon#read 6, iclass 11, count 0 2006.196.08:29:40.88#ibcon#end of sib2, iclass 11, count 0 2006.196.08:29:40.88#ibcon#*mode == 0, iclass 11, count 0 2006.196.08:29:40.88#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.196.08:29:40.88#ibcon#[27=USB\r\n] 2006.196.08:29:40.88#ibcon#*before write, iclass 11, count 0 2006.196.08:29:40.88#ibcon#enter sib2, iclass 11, count 0 2006.196.08:29:40.88#ibcon#flushed, iclass 11, count 0 2006.196.08:29:40.88#ibcon#about to write, iclass 11, count 0 2006.196.08:29:40.88#ibcon#wrote, iclass 11, count 0 2006.196.08:29:40.88#ibcon#about to read 3, iclass 11, count 0 2006.196.08:29:40.91#ibcon#read 3, iclass 11, count 0 2006.196.08:29:40.91#ibcon#about to read 4, iclass 11, count 0 2006.196.08:29:40.91#ibcon#read 4, iclass 11, count 0 2006.196.08:29:40.91#ibcon#about to read 5, iclass 11, count 0 2006.196.08:29:40.91#ibcon#read 5, iclass 11, count 0 2006.196.08:29:40.91#ibcon#about to read 6, iclass 11, count 0 2006.196.08:29:40.91#ibcon#read 6, iclass 11, count 0 2006.196.08:29:40.91#ibcon#end of sib2, iclass 11, count 0 2006.196.08:29:40.91#ibcon#*after write, iclass 11, count 0 2006.196.08:29:40.91#ibcon#*before return 0, iclass 11, count 0 2006.196.08:29:40.91#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.196.08:29:40.91#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.196.08:29:40.91#ibcon#about to clear, iclass 11 cls_cnt 0 2006.196.08:29:40.91#ibcon#cleared, iclass 11 cls_cnt 0 2006.196.08:29:40.91$vc4f8/vblo=2,640.99 2006.196.08:29:40.91#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.196.08:29:40.91#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.196.08:29:40.91#ibcon#ireg 17 cls_cnt 0 2006.196.08:29:40.91#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.196.08:29:40.91#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.196.08:29:40.91#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.196.08:29:40.91#ibcon#enter wrdev, iclass 13, count 0 2006.196.08:29:40.91#ibcon#first serial, iclass 13, count 0 2006.196.08:29:40.91#ibcon#enter sib2, iclass 13, count 0 2006.196.08:29:40.91#ibcon#flushed, iclass 13, count 0 2006.196.08:29:40.91#ibcon#about to write, iclass 13, count 0 2006.196.08:29:40.91#ibcon#wrote, iclass 13, count 0 2006.196.08:29:40.91#ibcon#about to read 3, iclass 13, count 0 2006.196.08:29:40.93#ibcon#read 3, iclass 13, count 0 2006.196.08:29:40.93#ibcon#about to read 4, iclass 13, count 0 2006.196.08:29:40.93#ibcon#read 4, iclass 13, count 0 2006.196.08:29:40.93#ibcon#about to read 5, iclass 13, count 0 2006.196.08:29:40.93#ibcon#read 5, iclass 13, count 0 2006.196.08:29:40.93#ibcon#about to read 6, iclass 13, count 0 2006.196.08:29:40.93#ibcon#read 6, iclass 13, count 0 2006.196.08:29:40.93#ibcon#end of sib2, iclass 13, count 0 2006.196.08:29:40.93#ibcon#*mode == 0, iclass 13, count 0 2006.196.08:29:40.93#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.196.08:29:40.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.196.08:29:40.93#ibcon#*before write, iclass 13, count 0 2006.196.08:29:40.93#ibcon#enter sib2, iclass 13, count 0 2006.196.08:29:40.93#ibcon#flushed, iclass 13, count 0 2006.196.08:29:40.93#ibcon#about to write, iclass 13, count 0 2006.196.08:29:40.93#ibcon#wrote, iclass 13, count 0 2006.196.08:29:40.93#ibcon#about to read 3, iclass 13, count 0 2006.196.08:29:40.97#ibcon#read 3, iclass 13, count 0 2006.196.08:29:40.97#ibcon#about to read 4, iclass 13, count 0 2006.196.08:29:40.97#ibcon#read 4, iclass 13, count 0 2006.196.08:29:40.97#ibcon#about to read 5, iclass 13, count 0 2006.196.08:29:40.97#ibcon#read 5, iclass 13, count 0 2006.196.08:29:40.97#ibcon#about to read 6, iclass 13, count 0 2006.196.08:29:40.97#ibcon#read 6, iclass 13, count 0 2006.196.08:29:40.97#ibcon#end of sib2, iclass 13, count 0 2006.196.08:29:40.97#ibcon#*after write, iclass 13, count 0 2006.196.08:29:40.97#ibcon#*before return 0, iclass 13, count 0 2006.196.08:29:40.97#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.196.08:29:40.97#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.196.08:29:40.97#ibcon#about to clear, iclass 13 cls_cnt 0 2006.196.08:29:40.97#ibcon#cleared, iclass 13 cls_cnt 0 2006.196.08:29:40.97$vc4f8/vb=2,4 2006.196.08:29:40.97#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.196.08:29:40.97#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.196.08:29:40.97#ibcon#ireg 11 cls_cnt 2 2006.196.08:29:40.97#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.196.08:29:41.03#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.196.08:29:41.03#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.196.08:29:41.03#ibcon#enter wrdev, iclass 15, count 2 2006.196.08:29:41.03#ibcon#first serial, iclass 15, count 2 2006.196.08:29:41.03#ibcon#enter sib2, iclass 15, count 2 2006.196.08:29:41.03#ibcon#flushed, iclass 15, count 2 2006.196.08:29:41.03#ibcon#about to write, iclass 15, count 2 2006.196.08:29:41.03#ibcon#wrote, iclass 15, count 2 2006.196.08:29:41.03#ibcon#about to read 3, iclass 15, count 2 2006.196.08:29:41.05#ibcon#read 3, iclass 15, count 2 2006.196.08:29:41.05#ibcon#about to read 4, iclass 15, count 2 2006.196.08:29:41.05#ibcon#read 4, iclass 15, count 2 2006.196.08:29:41.05#ibcon#about to read 5, iclass 15, count 2 2006.196.08:29:41.05#ibcon#read 5, iclass 15, count 2 2006.196.08:29:41.05#ibcon#about to read 6, iclass 15, count 2 2006.196.08:29:41.05#ibcon#read 6, iclass 15, count 2 2006.196.08:29:41.05#ibcon#end of sib2, iclass 15, count 2 2006.196.08:29:41.05#ibcon#*mode == 0, iclass 15, count 2 2006.196.08:29:41.05#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.196.08:29:41.05#ibcon#[27=AT02-04\r\n] 2006.196.08:29:41.05#ibcon#*before write, iclass 15, count 2 2006.196.08:29:41.05#ibcon#enter sib2, iclass 15, count 2 2006.196.08:29:41.05#ibcon#flushed, iclass 15, count 2 2006.196.08:29:41.05#ibcon#about to write, iclass 15, count 2 2006.196.08:29:41.05#ibcon#wrote, iclass 15, count 2 2006.196.08:29:41.05#ibcon#about to read 3, iclass 15, count 2 2006.196.08:29:41.08#ibcon#read 3, iclass 15, count 2 2006.196.08:29:41.08#ibcon#about to read 4, iclass 15, count 2 2006.196.08:29:41.08#ibcon#read 4, iclass 15, count 2 2006.196.08:29:41.08#ibcon#about to read 5, iclass 15, count 2 2006.196.08:29:41.08#ibcon#read 5, iclass 15, count 2 2006.196.08:29:41.08#ibcon#about to read 6, iclass 15, count 2 2006.196.08:29:41.08#ibcon#read 6, iclass 15, count 2 2006.196.08:29:41.08#ibcon#end of sib2, iclass 15, count 2 2006.196.08:29:41.08#ibcon#*after write, iclass 15, count 2 2006.196.08:29:41.08#ibcon#*before return 0, iclass 15, count 2 2006.196.08:29:41.08#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.196.08:29:41.08#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.196.08:29:41.08#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.196.08:29:41.08#ibcon#ireg 7 cls_cnt 0 2006.196.08:29:41.08#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.196.08:29:41.20#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.196.08:29:41.20#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.196.08:29:41.20#ibcon#enter wrdev, iclass 15, count 0 2006.196.08:29:41.20#ibcon#first serial, iclass 15, count 0 2006.196.08:29:41.20#ibcon#enter sib2, iclass 15, count 0 2006.196.08:29:41.20#ibcon#flushed, iclass 15, count 0 2006.196.08:29:41.20#ibcon#about to write, iclass 15, count 0 2006.196.08:29:41.20#ibcon#wrote, iclass 15, count 0 2006.196.08:29:41.20#ibcon#about to read 3, iclass 15, count 0 2006.196.08:29:41.23#ibcon#read 3, iclass 15, count 0 2006.196.08:29:41.23#ibcon#about to read 4, iclass 15, count 0 2006.196.08:29:41.23#ibcon#read 4, iclass 15, count 0 2006.196.08:29:41.23#ibcon#about to read 5, iclass 15, count 0 2006.196.08:29:41.23#ibcon#read 5, iclass 15, count 0 2006.196.08:29:41.23#ibcon#about to read 6, iclass 15, count 0 2006.196.08:29:41.23#ibcon#read 6, iclass 15, count 0 2006.196.08:29:41.23#ibcon#end of sib2, iclass 15, count 0 2006.196.08:29:41.23#ibcon#*mode == 0, iclass 15, count 0 2006.196.08:29:41.23#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.196.08:29:41.23#ibcon#[27=USB\r\n] 2006.196.08:29:41.23#ibcon#*before write, iclass 15, count 0 2006.196.08:29:41.23#ibcon#enter sib2, iclass 15, count 0 2006.196.08:29:41.23#ibcon#flushed, iclass 15, count 0 2006.196.08:29:41.23#ibcon#about to write, iclass 15, count 0 2006.196.08:29:41.23#ibcon#wrote, iclass 15, count 0 2006.196.08:29:41.23#ibcon#about to read 3, iclass 15, count 0 2006.196.08:29:41.26#ibcon#read 3, iclass 15, count 0 2006.196.08:29:41.26#ibcon#about to read 4, iclass 15, count 0 2006.196.08:29:41.26#ibcon#read 4, iclass 15, count 0 2006.196.08:29:41.26#ibcon#about to read 5, iclass 15, count 0 2006.196.08:29:41.26#ibcon#read 5, iclass 15, count 0 2006.196.08:29:41.26#ibcon#about to read 6, iclass 15, count 0 2006.196.08:29:41.26#ibcon#read 6, iclass 15, count 0 2006.196.08:29:41.26#ibcon#end of sib2, iclass 15, count 0 2006.196.08:29:41.26#ibcon#*after write, iclass 15, count 0 2006.196.08:29:41.26#ibcon#*before return 0, iclass 15, count 0 2006.196.08:29:41.26#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.196.08:29:41.26#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.196.08:29:41.26#ibcon#about to clear, iclass 15 cls_cnt 0 2006.196.08:29:41.26#ibcon#cleared, iclass 15 cls_cnt 0 2006.196.08:29:41.26$vc4f8/vblo=3,656.99 2006.196.08:29:41.26#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.196.08:29:41.26#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.196.08:29:41.26#ibcon#ireg 17 cls_cnt 0 2006.196.08:29:41.26#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.196.08:29:41.26#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.196.08:29:41.26#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.196.08:29:41.26#ibcon#enter wrdev, iclass 17, count 0 2006.196.08:29:41.26#ibcon#first serial, iclass 17, count 0 2006.196.08:29:41.26#ibcon#enter sib2, iclass 17, count 0 2006.196.08:29:41.26#ibcon#flushed, iclass 17, count 0 2006.196.08:29:41.26#ibcon#about to write, iclass 17, count 0 2006.196.08:29:41.26#ibcon#wrote, iclass 17, count 0 2006.196.08:29:41.26#ibcon#about to read 3, iclass 17, count 0 2006.196.08:29:41.28#ibcon#read 3, iclass 17, count 0 2006.196.08:29:41.28#ibcon#about to read 4, iclass 17, count 0 2006.196.08:29:41.28#ibcon#read 4, iclass 17, count 0 2006.196.08:29:41.28#ibcon#about to read 5, iclass 17, count 0 2006.196.08:29:41.28#ibcon#read 5, iclass 17, count 0 2006.196.08:29:41.28#ibcon#about to read 6, iclass 17, count 0 2006.196.08:29:41.28#ibcon#read 6, iclass 17, count 0 2006.196.08:29:41.28#ibcon#end of sib2, iclass 17, count 0 2006.196.08:29:41.28#ibcon#*mode == 0, iclass 17, count 0 2006.196.08:29:41.28#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.196.08:29:41.28#ibcon#[28=FRQ=03,656.99\r\n] 2006.196.08:29:41.28#ibcon#*before write, iclass 17, count 0 2006.196.08:29:41.28#ibcon#enter sib2, iclass 17, count 0 2006.196.08:29:41.28#ibcon#flushed, iclass 17, count 0 2006.196.08:29:41.28#ibcon#about to write, iclass 17, count 0 2006.196.08:29:41.28#ibcon#wrote, iclass 17, count 0 2006.196.08:29:41.28#ibcon#about to read 3, iclass 17, count 0 2006.196.08:29:41.32#abcon#<5=/05 2.9 4.4 28.74 931004.2\r\n> 2006.196.08:29:41.32#ibcon#read 3, iclass 17, count 0 2006.196.08:29:41.32#ibcon#about to read 4, iclass 17, count 0 2006.196.08:29:41.32#ibcon#read 4, iclass 17, count 0 2006.196.08:29:41.32#ibcon#about to read 5, iclass 17, count 0 2006.196.08:29:41.32#ibcon#read 5, iclass 17, count 0 2006.196.08:29:41.32#ibcon#about to read 6, iclass 17, count 0 2006.196.08:29:41.32#ibcon#read 6, iclass 17, count 0 2006.196.08:29:41.32#ibcon#end of sib2, iclass 17, count 0 2006.196.08:29:41.32#ibcon#*after write, iclass 17, count 0 2006.196.08:29:41.32#ibcon#*before return 0, iclass 17, count 0 2006.196.08:29:41.32#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.196.08:29:41.32#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.196.08:29:41.32#ibcon#about to clear, iclass 17 cls_cnt 0 2006.196.08:29:41.32#ibcon#cleared, iclass 17 cls_cnt 0 2006.196.08:29:41.32$vc4f8/vb=3,4 2006.196.08:29:41.32#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.196.08:29:41.32#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.196.08:29:41.32#ibcon#ireg 11 cls_cnt 2 2006.196.08:29:41.32#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.196.08:29:41.34#abcon#{5=INTERFACE CLEAR} 2006.196.08:29:41.38#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.196.08:29:41.38#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.196.08:29:41.38#ibcon#enter wrdev, iclass 22, count 2 2006.196.08:29:41.38#ibcon#first serial, iclass 22, count 2 2006.196.08:29:41.38#ibcon#enter sib2, iclass 22, count 2 2006.196.08:29:41.38#ibcon#flushed, iclass 22, count 2 2006.196.08:29:41.38#ibcon#about to write, iclass 22, count 2 2006.196.08:29:41.38#ibcon#wrote, iclass 22, count 2 2006.196.08:29:41.38#ibcon#about to read 3, iclass 22, count 2 2006.196.08:29:41.40#ibcon#read 3, iclass 22, count 2 2006.196.08:29:41.40#ibcon#about to read 4, iclass 22, count 2 2006.196.08:29:41.40#ibcon#read 4, iclass 22, count 2 2006.196.08:29:41.40#ibcon#about to read 5, iclass 22, count 2 2006.196.08:29:41.40#ibcon#read 5, iclass 22, count 2 2006.196.08:29:41.40#ibcon#about to read 6, iclass 22, count 2 2006.196.08:29:41.40#ibcon#read 6, iclass 22, count 2 2006.196.08:29:41.40#ibcon#end of sib2, iclass 22, count 2 2006.196.08:29:41.40#ibcon#*mode == 0, iclass 22, count 2 2006.196.08:29:41.40#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.196.08:29:41.40#ibcon#[27=AT03-04\r\n] 2006.196.08:29:41.40#ibcon#*before write, iclass 22, count 2 2006.196.08:29:41.40#ibcon#enter sib2, iclass 22, count 2 2006.196.08:29:41.40#ibcon#flushed, iclass 22, count 2 2006.196.08:29:41.40#ibcon#about to write, iclass 22, count 2 2006.196.08:29:41.40#ibcon#wrote, iclass 22, count 2 2006.196.08:29:41.40#ibcon#about to read 3, iclass 22, count 2 2006.196.08:29:41.40#abcon#[5=S1D000X0/0*\r\n] 2006.196.08:29:41.43#ibcon#read 3, iclass 22, count 2 2006.196.08:29:41.43#ibcon#about to read 4, iclass 22, count 2 2006.196.08:29:41.43#ibcon#read 4, iclass 22, count 2 2006.196.08:29:41.43#ibcon#about to read 5, iclass 22, count 2 2006.196.08:29:41.43#ibcon#read 5, iclass 22, count 2 2006.196.08:29:41.43#ibcon#about to read 6, iclass 22, count 2 2006.196.08:29:41.43#ibcon#read 6, iclass 22, count 2 2006.196.08:29:41.43#ibcon#end of sib2, iclass 22, count 2 2006.196.08:29:41.43#ibcon#*after write, iclass 22, count 2 2006.196.08:29:41.43#ibcon#*before return 0, iclass 22, count 2 2006.196.08:29:41.43#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.196.08:29:41.43#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.196.08:29:41.43#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.196.08:29:41.43#ibcon#ireg 7 cls_cnt 0 2006.196.08:29:41.43#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.196.08:29:41.55#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.196.08:29:41.55#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.196.08:29:41.55#ibcon#enter wrdev, iclass 22, count 0 2006.196.08:29:41.55#ibcon#first serial, iclass 22, count 0 2006.196.08:29:41.55#ibcon#enter sib2, iclass 22, count 0 2006.196.08:29:41.55#ibcon#flushed, iclass 22, count 0 2006.196.08:29:41.55#ibcon#about to write, iclass 22, count 0 2006.196.08:29:41.55#ibcon#wrote, iclass 22, count 0 2006.196.08:29:41.55#ibcon#about to read 3, iclass 22, count 0 2006.196.08:29:41.57#ibcon#read 3, iclass 22, count 0 2006.196.08:29:41.57#ibcon#about to read 4, iclass 22, count 0 2006.196.08:29:41.57#ibcon#read 4, iclass 22, count 0 2006.196.08:29:41.57#ibcon#about to read 5, iclass 22, count 0 2006.196.08:29:41.57#ibcon#read 5, iclass 22, count 0 2006.196.08:29:41.57#ibcon#about to read 6, iclass 22, count 0 2006.196.08:29:41.57#ibcon#read 6, iclass 22, count 0 2006.196.08:29:41.57#ibcon#end of sib2, iclass 22, count 0 2006.196.08:29:41.57#ibcon#*mode == 0, iclass 22, count 0 2006.196.08:29:41.57#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.196.08:29:41.57#ibcon#[27=USB\r\n] 2006.196.08:29:41.57#ibcon#*before write, iclass 22, count 0 2006.196.08:29:41.57#ibcon#enter sib2, iclass 22, count 0 2006.196.08:29:41.57#ibcon#flushed, iclass 22, count 0 2006.196.08:29:41.57#ibcon#about to write, iclass 22, count 0 2006.196.08:29:41.57#ibcon#wrote, iclass 22, count 0 2006.196.08:29:41.57#ibcon#about to read 3, iclass 22, count 0 2006.196.08:29:41.60#ibcon#read 3, iclass 22, count 0 2006.196.08:29:41.60#ibcon#about to read 4, iclass 22, count 0 2006.196.08:29:41.60#ibcon#read 4, iclass 22, count 0 2006.196.08:29:41.60#ibcon#about to read 5, iclass 22, count 0 2006.196.08:29:41.60#ibcon#read 5, iclass 22, count 0 2006.196.08:29:41.60#ibcon#about to read 6, iclass 22, count 0 2006.196.08:29:41.60#ibcon#read 6, iclass 22, count 0 2006.196.08:29:41.60#ibcon#end of sib2, iclass 22, count 0 2006.196.08:29:41.60#ibcon#*after write, iclass 22, count 0 2006.196.08:29:41.60#ibcon#*before return 0, iclass 22, count 0 2006.196.08:29:41.60#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.196.08:29:41.60#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.196.08:29:41.60#ibcon#about to clear, iclass 22 cls_cnt 0 2006.196.08:29:41.60#ibcon#cleared, iclass 22 cls_cnt 0 2006.196.08:29:41.60$vc4f8/vblo=4,712.99 2006.196.08:29:41.60#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.196.08:29:41.60#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.196.08:29:41.60#ibcon#ireg 17 cls_cnt 0 2006.196.08:29:41.60#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.196.08:29:41.60#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.196.08:29:41.60#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.196.08:29:41.60#ibcon#enter wrdev, iclass 25, count 0 2006.196.08:29:41.60#ibcon#first serial, iclass 25, count 0 2006.196.08:29:41.60#ibcon#enter sib2, iclass 25, count 0 2006.196.08:29:41.60#ibcon#flushed, iclass 25, count 0 2006.196.08:29:41.60#ibcon#about to write, iclass 25, count 0 2006.196.08:29:41.60#ibcon#wrote, iclass 25, count 0 2006.196.08:29:41.60#ibcon#about to read 3, iclass 25, count 0 2006.196.08:29:41.62#ibcon#read 3, iclass 25, count 0 2006.196.08:29:41.62#ibcon#about to read 4, iclass 25, count 0 2006.196.08:29:41.62#ibcon#read 4, iclass 25, count 0 2006.196.08:29:41.62#ibcon#about to read 5, iclass 25, count 0 2006.196.08:29:41.62#ibcon#read 5, iclass 25, count 0 2006.196.08:29:41.62#ibcon#about to read 6, iclass 25, count 0 2006.196.08:29:41.62#ibcon#read 6, iclass 25, count 0 2006.196.08:29:41.62#ibcon#end of sib2, iclass 25, count 0 2006.196.08:29:41.62#ibcon#*mode == 0, iclass 25, count 0 2006.196.08:29:41.62#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.196.08:29:41.62#ibcon#[28=FRQ=04,712.99\r\n] 2006.196.08:29:41.62#ibcon#*before write, iclass 25, count 0 2006.196.08:29:41.62#ibcon#enter sib2, iclass 25, count 0 2006.196.08:29:41.62#ibcon#flushed, iclass 25, count 0 2006.196.08:29:41.62#ibcon#about to write, iclass 25, count 0 2006.196.08:29:41.62#ibcon#wrote, iclass 25, count 0 2006.196.08:29:41.62#ibcon#about to read 3, iclass 25, count 0 2006.196.08:29:41.66#ibcon#read 3, iclass 25, count 0 2006.196.08:29:41.66#ibcon#about to read 4, iclass 25, count 0 2006.196.08:29:41.66#ibcon#read 4, iclass 25, count 0 2006.196.08:29:41.66#ibcon#about to read 5, iclass 25, count 0 2006.196.08:29:41.66#ibcon#read 5, iclass 25, count 0 2006.196.08:29:41.66#ibcon#about to read 6, iclass 25, count 0 2006.196.08:29:41.66#ibcon#read 6, iclass 25, count 0 2006.196.08:29:41.66#ibcon#end of sib2, iclass 25, count 0 2006.196.08:29:41.66#ibcon#*after write, iclass 25, count 0 2006.196.08:29:41.66#ibcon#*before return 0, iclass 25, count 0 2006.196.08:29:41.66#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.196.08:29:41.66#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.196.08:29:41.66#ibcon#about to clear, iclass 25 cls_cnt 0 2006.196.08:29:41.66#ibcon#cleared, iclass 25 cls_cnt 0 2006.196.08:29:41.66$vc4f8/vb=4,4 2006.196.08:29:41.66#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.196.08:29:41.66#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.196.08:29:41.66#ibcon#ireg 11 cls_cnt 2 2006.196.08:29:41.66#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.196.08:29:41.72#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.196.08:29:41.72#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.196.08:29:41.72#ibcon#enter wrdev, iclass 27, count 2 2006.196.08:29:41.72#ibcon#first serial, iclass 27, count 2 2006.196.08:29:41.72#ibcon#enter sib2, iclass 27, count 2 2006.196.08:29:41.72#ibcon#flushed, iclass 27, count 2 2006.196.08:29:41.72#ibcon#about to write, iclass 27, count 2 2006.196.08:29:41.72#ibcon#wrote, iclass 27, count 2 2006.196.08:29:41.72#ibcon#about to read 3, iclass 27, count 2 2006.196.08:29:41.74#ibcon#read 3, iclass 27, count 2 2006.196.08:29:41.74#ibcon#about to read 4, iclass 27, count 2 2006.196.08:29:41.74#ibcon#read 4, iclass 27, count 2 2006.196.08:29:41.74#ibcon#about to read 5, iclass 27, count 2 2006.196.08:29:41.74#ibcon#read 5, iclass 27, count 2 2006.196.08:29:41.74#ibcon#about to read 6, iclass 27, count 2 2006.196.08:29:41.74#ibcon#read 6, iclass 27, count 2 2006.196.08:29:41.74#ibcon#end of sib2, iclass 27, count 2 2006.196.08:29:41.74#ibcon#*mode == 0, iclass 27, count 2 2006.196.08:29:41.74#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.196.08:29:41.74#ibcon#[27=AT04-04\r\n] 2006.196.08:29:41.74#ibcon#*before write, iclass 27, count 2 2006.196.08:29:41.74#ibcon#enter sib2, iclass 27, count 2 2006.196.08:29:41.74#ibcon#flushed, iclass 27, count 2 2006.196.08:29:41.74#ibcon#about to write, iclass 27, count 2 2006.196.08:29:41.74#ibcon#wrote, iclass 27, count 2 2006.196.08:29:41.74#ibcon#about to read 3, iclass 27, count 2 2006.196.08:29:41.77#ibcon#read 3, iclass 27, count 2 2006.196.08:29:41.77#ibcon#about to read 4, iclass 27, count 2 2006.196.08:29:41.77#ibcon#read 4, iclass 27, count 2 2006.196.08:29:41.77#ibcon#about to read 5, iclass 27, count 2 2006.196.08:29:41.77#ibcon#read 5, iclass 27, count 2 2006.196.08:29:41.77#ibcon#about to read 6, iclass 27, count 2 2006.196.08:29:41.77#ibcon#read 6, iclass 27, count 2 2006.196.08:29:41.77#ibcon#end of sib2, iclass 27, count 2 2006.196.08:29:41.77#ibcon#*after write, iclass 27, count 2 2006.196.08:29:41.77#ibcon#*before return 0, iclass 27, count 2 2006.196.08:29:41.77#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.196.08:29:41.77#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.196.08:29:41.77#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.196.08:29:41.77#ibcon#ireg 7 cls_cnt 0 2006.196.08:29:41.77#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.196.08:29:41.89#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.196.08:29:41.89#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.196.08:29:41.89#ibcon#enter wrdev, iclass 27, count 0 2006.196.08:29:41.89#ibcon#first serial, iclass 27, count 0 2006.196.08:29:41.89#ibcon#enter sib2, iclass 27, count 0 2006.196.08:29:41.89#ibcon#flushed, iclass 27, count 0 2006.196.08:29:41.89#ibcon#about to write, iclass 27, count 0 2006.196.08:29:41.89#ibcon#wrote, iclass 27, count 0 2006.196.08:29:41.89#ibcon#about to read 3, iclass 27, count 0 2006.196.08:29:41.91#ibcon#read 3, iclass 27, count 0 2006.196.08:29:41.91#ibcon#about to read 4, iclass 27, count 0 2006.196.08:29:41.91#ibcon#read 4, iclass 27, count 0 2006.196.08:29:41.91#ibcon#about to read 5, iclass 27, count 0 2006.196.08:29:41.91#ibcon#read 5, iclass 27, count 0 2006.196.08:29:41.91#ibcon#about to read 6, iclass 27, count 0 2006.196.08:29:41.91#ibcon#read 6, iclass 27, count 0 2006.196.08:29:41.91#ibcon#end of sib2, iclass 27, count 0 2006.196.08:29:41.91#ibcon#*mode == 0, iclass 27, count 0 2006.196.08:29:41.91#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.196.08:29:41.91#ibcon#[27=USB\r\n] 2006.196.08:29:41.91#ibcon#*before write, iclass 27, count 0 2006.196.08:29:41.91#ibcon#enter sib2, iclass 27, count 0 2006.196.08:29:41.91#ibcon#flushed, iclass 27, count 0 2006.196.08:29:41.91#ibcon#about to write, iclass 27, count 0 2006.196.08:29:41.91#ibcon#wrote, iclass 27, count 0 2006.196.08:29:41.91#ibcon#about to read 3, iclass 27, count 0 2006.196.08:29:41.94#ibcon#read 3, iclass 27, count 0 2006.196.08:29:41.94#ibcon#about to read 4, iclass 27, count 0 2006.196.08:29:41.94#ibcon#read 4, iclass 27, count 0 2006.196.08:29:41.94#ibcon#about to read 5, iclass 27, count 0 2006.196.08:29:41.94#ibcon#read 5, iclass 27, count 0 2006.196.08:29:41.94#ibcon#about to read 6, iclass 27, count 0 2006.196.08:29:41.94#ibcon#read 6, iclass 27, count 0 2006.196.08:29:41.94#ibcon#end of sib2, iclass 27, count 0 2006.196.08:29:41.94#ibcon#*after write, iclass 27, count 0 2006.196.08:29:41.94#ibcon#*before return 0, iclass 27, count 0 2006.196.08:29:41.94#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.196.08:29:41.94#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.196.08:29:41.94#ibcon#about to clear, iclass 27 cls_cnt 0 2006.196.08:29:41.94#ibcon#cleared, iclass 27 cls_cnt 0 2006.196.08:29:41.94$vc4f8/vblo=5,744.99 2006.196.08:29:41.94#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.196.08:29:41.94#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.196.08:29:41.94#ibcon#ireg 17 cls_cnt 0 2006.196.08:29:41.94#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.196.08:29:41.94#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.196.08:29:41.94#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.196.08:29:41.94#ibcon#enter wrdev, iclass 29, count 0 2006.196.08:29:41.94#ibcon#first serial, iclass 29, count 0 2006.196.08:29:41.94#ibcon#enter sib2, iclass 29, count 0 2006.196.08:29:41.94#ibcon#flushed, iclass 29, count 0 2006.196.08:29:41.94#ibcon#about to write, iclass 29, count 0 2006.196.08:29:41.94#ibcon#wrote, iclass 29, count 0 2006.196.08:29:41.94#ibcon#about to read 3, iclass 29, count 0 2006.196.08:29:41.96#ibcon#read 3, iclass 29, count 0 2006.196.08:29:41.96#ibcon#about to read 4, iclass 29, count 0 2006.196.08:29:41.96#ibcon#read 4, iclass 29, count 0 2006.196.08:29:41.96#ibcon#about to read 5, iclass 29, count 0 2006.196.08:29:41.96#ibcon#read 5, iclass 29, count 0 2006.196.08:29:41.96#ibcon#about to read 6, iclass 29, count 0 2006.196.08:29:41.96#ibcon#read 6, iclass 29, count 0 2006.196.08:29:41.96#ibcon#end of sib2, iclass 29, count 0 2006.196.08:29:41.96#ibcon#*mode == 0, iclass 29, count 0 2006.196.08:29:41.96#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.196.08:29:41.96#ibcon#[28=FRQ=05,744.99\r\n] 2006.196.08:29:41.96#ibcon#*before write, iclass 29, count 0 2006.196.08:29:41.96#ibcon#enter sib2, iclass 29, count 0 2006.196.08:29:41.96#ibcon#flushed, iclass 29, count 0 2006.196.08:29:41.96#ibcon#about to write, iclass 29, count 0 2006.196.08:29:41.96#ibcon#wrote, iclass 29, count 0 2006.196.08:29:41.96#ibcon#about to read 3, iclass 29, count 0 2006.196.08:29:42.00#ibcon#read 3, iclass 29, count 0 2006.196.08:29:42.00#ibcon#about to read 4, iclass 29, count 0 2006.196.08:29:42.00#ibcon#read 4, iclass 29, count 0 2006.196.08:29:42.00#ibcon#about to read 5, iclass 29, count 0 2006.196.08:29:42.00#ibcon#read 5, iclass 29, count 0 2006.196.08:29:42.00#ibcon#about to read 6, iclass 29, count 0 2006.196.08:29:42.00#ibcon#read 6, iclass 29, count 0 2006.196.08:29:42.00#ibcon#end of sib2, iclass 29, count 0 2006.196.08:29:42.00#ibcon#*after write, iclass 29, count 0 2006.196.08:29:42.00#ibcon#*before return 0, iclass 29, count 0 2006.196.08:29:42.00#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.196.08:29:42.00#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.196.08:29:42.00#ibcon#about to clear, iclass 29 cls_cnt 0 2006.196.08:29:42.00#ibcon#cleared, iclass 29 cls_cnt 0 2006.196.08:29:42.00$vc4f8/vb=5,4 2006.196.08:29:42.00#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.196.08:29:42.00#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.196.08:29:42.00#ibcon#ireg 11 cls_cnt 2 2006.196.08:29:42.00#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.196.08:29:42.06#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.196.08:29:42.06#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.196.08:29:42.06#ibcon#enter wrdev, iclass 31, count 2 2006.196.08:29:42.06#ibcon#first serial, iclass 31, count 2 2006.196.08:29:42.06#ibcon#enter sib2, iclass 31, count 2 2006.196.08:29:42.06#ibcon#flushed, iclass 31, count 2 2006.196.08:29:42.06#ibcon#about to write, iclass 31, count 2 2006.196.08:29:42.06#ibcon#wrote, iclass 31, count 2 2006.196.08:29:42.06#ibcon#about to read 3, iclass 31, count 2 2006.196.08:29:42.08#ibcon#read 3, iclass 31, count 2 2006.196.08:29:42.08#ibcon#about to read 4, iclass 31, count 2 2006.196.08:29:42.08#ibcon#read 4, iclass 31, count 2 2006.196.08:29:42.08#ibcon#about to read 5, iclass 31, count 2 2006.196.08:29:42.08#ibcon#read 5, iclass 31, count 2 2006.196.08:29:42.08#ibcon#about to read 6, iclass 31, count 2 2006.196.08:29:42.08#ibcon#read 6, iclass 31, count 2 2006.196.08:29:42.08#ibcon#end of sib2, iclass 31, count 2 2006.196.08:29:42.08#ibcon#*mode == 0, iclass 31, count 2 2006.196.08:29:42.08#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.196.08:29:42.08#ibcon#[27=AT05-04\r\n] 2006.196.08:29:42.08#ibcon#*before write, iclass 31, count 2 2006.196.08:29:42.08#ibcon#enter sib2, iclass 31, count 2 2006.196.08:29:42.08#ibcon#flushed, iclass 31, count 2 2006.196.08:29:42.08#ibcon#about to write, iclass 31, count 2 2006.196.08:29:42.08#ibcon#wrote, iclass 31, count 2 2006.196.08:29:42.08#ibcon#about to read 3, iclass 31, count 2 2006.196.08:29:42.11#ibcon#read 3, iclass 31, count 2 2006.196.08:29:42.11#ibcon#about to read 4, iclass 31, count 2 2006.196.08:29:42.11#ibcon#read 4, iclass 31, count 2 2006.196.08:29:42.11#ibcon#about to read 5, iclass 31, count 2 2006.196.08:29:42.11#ibcon#read 5, iclass 31, count 2 2006.196.08:29:42.11#ibcon#about to read 6, iclass 31, count 2 2006.196.08:29:42.11#ibcon#read 6, iclass 31, count 2 2006.196.08:29:42.11#ibcon#end of sib2, iclass 31, count 2 2006.196.08:29:42.11#ibcon#*after write, iclass 31, count 2 2006.196.08:29:42.11#ibcon#*before return 0, iclass 31, count 2 2006.196.08:29:42.11#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.196.08:29:42.11#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.196.08:29:42.11#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.196.08:29:42.11#ibcon#ireg 7 cls_cnt 0 2006.196.08:29:42.11#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.196.08:29:42.23#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.196.08:29:42.23#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.196.08:29:42.23#ibcon#enter wrdev, iclass 31, count 0 2006.196.08:29:42.23#ibcon#first serial, iclass 31, count 0 2006.196.08:29:42.23#ibcon#enter sib2, iclass 31, count 0 2006.196.08:29:42.23#ibcon#flushed, iclass 31, count 0 2006.196.08:29:42.23#ibcon#about to write, iclass 31, count 0 2006.196.08:29:42.23#ibcon#wrote, iclass 31, count 0 2006.196.08:29:42.23#ibcon#about to read 3, iclass 31, count 0 2006.196.08:29:42.25#ibcon#read 3, iclass 31, count 0 2006.196.08:29:42.25#ibcon#about to read 4, iclass 31, count 0 2006.196.08:29:42.25#ibcon#read 4, iclass 31, count 0 2006.196.08:29:42.25#ibcon#about to read 5, iclass 31, count 0 2006.196.08:29:42.25#ibcon#read 5, iclass 31, count 0 2006.196.08:29:42.25#ibcon#about to read 6, iclass 31, count 0 2006.196.08:29:42.25#ibcon#read 6, iclass 31, count 0 2006.196.08:29:42.25#ibcon#end of sib2, iclass 31, count 0 2006.196.08:29:42.25#ibcon#*mode == 0, iclass 31, count 0 2006.196.08:29:42.25#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.196.08:29:42.25#ibcon#[27=USB\r\n] 2006.196.08:29:42.25#ibcon#*before write, iclass 31, count 0 2006.196.08:29:42.25#ibcon#enter sib2, iclass 31, count 0 2006.196.08:29:42.25#ibcon#flushed, iclass 31, count 0 2006.196.08:29:42.25#ibcon#about to write, iclass 31, count 0 2006.196.08:29:42.25#ibcon#wrote, iclass 31, count 0 2006.196.08:29:42.25#ibcon#about to read 3, iclass 31, count 0 2006.196.08:29:42.28#ibcon#read 3, iclass 31, count 0 2006.196.08:29:42.28#ibcon#about to read 4, iclass 31, count 0 2006.196.08:29:42.28#ibcon#read 4, iclass 31, count 0 2006.196.08:29:42.28#ibcon#about to read 5, iclass 31, count 0 2006.196.08:29:42.28#ibcon#read 5, iclass 31, count 0 2006.196.08:29:42.28#ibcon#about to read 6, iclass 31, count 0 2006.196.08:29:42.28#ibcon#read 6, iclass 31, count 0 2006.196.08:29:42.28#ibcon#end of sib2, iclass 31, count 0 2006.196.08:29:42.28#ibcon#*after write, iclass 31, count 0 2006.196.08:29:42.28#ibcon#*before return 0, iclass 31, count 0 2006.196.08:29:42.28#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.196.08:29:42.28#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.196.08:29:42.28#ibcon#about to clear, iclass 31 cls_cnt 0 2006.196.08:29:42.28#ibcon#cleared, iclass 31 cls_cnt 0 2006.196.08:29:42.28$vc4f8/vblo=6,752.99 2006.196.08:29:42.28#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.196.08:29:42.28#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.196.08:29:42.28#ibcon#ireg 17 cls_cnt 0 2006.196.08:29:42.28#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:29:42.28#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:29:42.28#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:29:42.28#ibcon#enter wrdev, iclass 33, count 0 2006.196.08:29:42.28#ibcon#first serial, iclass 33, count 0 2006.196.08:29:42.28#ibcon#enter sib2, iclass 33, count 0 2006.196.08:29:42.28#ibcon#flushed, iclass 33, count 0 2006.196.08:29:42.28#ibcon#about to write, iclass 33, count 0 2006.196.08:29:42.28#ibcon#wrote, iclass 33, count 0 2006.196.08:29:42.28#ibcon#about to read 3, iclass 33, count 0 2006.196.08:29:42.30#ibcon#read 3, iclass 33, count 0 2006.196.08:29:42.30#ibcon#about to read 4, iclass 33, count 0 2006.196.08:29:42.30#ibcon#read 4, iclass 33, count 0 2006.196.08:29:42.30#ibcon#about to read 5, iclass 33, count 0 2006.196.08:29:42.30#ibcon#read 5, iclass 33, count 0 2006.196.08:29:42.30#ibcon#about to read 6, iclass 33, count 0 2006.196.08:29:42.30#ibcon#read 6, iclass 33, count 0 2006.196.08:29:42.30#ibcon#end of sib2, iclass 33, count 0 2006.196.08:29:42.30#ibcon#*mode == 0, iclass 33, count 0 2006.196.08:29:42.30#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.196.08:29:42.30#ibcon#[28=FRQ=06,752.99\r\n] 2006.196.08:29:42.30#ibcon#*before write, iclass 33, count 0 2006.196.08:29:42.30#ibcon#enter sib2, iclass 33, count 0 2006.196.08:29:42.30#ibcon#flushed, iclass 33, count 0 2006.196.08:29:42.30#ibcon#about to write, iclass 33, count 0 2006.196.08:29:42.30#ibcon#wrote, iclass 33, count 0 2006.196.08:29:42.30#ibcon#about to read 3, iclass 33, count 0 2006.196.08:29:42.34#ibcon#read 3, iclass 33, count 0 2006.196.08:29:42.34#ibcon#about to read 4, iclass 33, count 0 2006.196.08:29:42.34#ibcon#read 4, iclass 33, count 0 2006.196.08:29:42.34#ibcon#about to read 5, iclass 33, count 0 2006.196.08:29:42.34#ibcon#read 5, iclass 33, count 0 2006.196.08:29:42.34#ibcon#about to read 6, iclass 33, count 0 2006.196.08:29:42.34#ibcon#read 6, iclass 33, count 0 2006.196.08:29:42.34#ibcon#end of sib2, iclass 33, count 0 2006.196.08:29:42.34#ibcon#*after write, iclass 33, count 0 2006.196.08:29:42.34#ibcon#*before return 0, iclass 33, count 0 2006.196.08:29:42.34#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:29:42.34#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.196.08:29:42.34#ibcon#about to clear, iclass 33 cls_cnt 0 2006.196.08:29:42.34#ibcon#cleared, iclass 33 cls_cnt 0 2006.196.08:29:42.34$vc4f8/vb=6,4 2006.196.08:29:42.34#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.196.08:29:42.34#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.196.08:29:42.34#ibcon#ireg 11 cls_cnt 2 2006.196.08:29:42.34#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.196.08:29:42.40#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.196.08:29:42.40#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.196.08:29:42.40#ibcon#enter wrdev, iclass 35, count 2 2006.196.08:29:42.40#ibcon#first serial, iclass 35, count 2 2006.196.08:29:42.40#ibcon#enter sib2, iclass 35, count 2 2006.196.08:29:42.40#ibcon#flushed, iclass 35, count 2 2006.196.08:29:42.40#ibcon#about to write, iclass 35, count 2 2006.196.08:29:42.40#ibcon#wrote, iclass 35, count 2 2006.196.08:29:42.40#ibcon#about to read 3, iclass 35, count 2 2006.196.08:29:42.42#ibcon#read 3, iclass 35, count 2 2006.196.08:29:42.42#ibcon#about to read 4, iclass 35, count 2 2006.196.08:29:42.42#ibcon#read 4, iclass 35, count 2 2006.196.08:29:42.42#ibcon#about to read 5, iclass 35, count 2 2006.196.08:29:42.42#ibcon#read 5, iclass 35, count 2 2006.196.08:29:42.42#ibcon#about to read 6, iclass 35, count 2 2006.196.08:29:42.42#ibcon#read 6, iclass 35, count 2 2006.196.08:29:42.42#ibcon#end of sib2, iclass 35, count 2 2006.196.08:29:42.42#ibcon#*mode == 0, iclass 35, count 2 2006.196.08:29:42.42#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.196.08:29:42.42#ibcon#[27=AT06-04\r\n] 2006.196.08:29:42.42#ibcon#*before write, iclass 35, count 2 2006.196.08:29:42.42#ibcon#enter sib2, iclass 35, count 2 2006.196.08:29:42.42#ibcon#flushed, iclass 35, count 2 2006.196.08:29:42.42#ibcon#about to write, iclass 35, count 2 2006.196.08:29:42.42#ibcon#wrote, iclass 35, count 2 2006.196.08:29:42.42#ibcon#about to read 3, iclass 35, count 2 2006.196.08:29:42.45#ibcon#read 3, iclass 35, count 2 2006.196.08:29:42.45#ibcon#about to read 4, iclass 35, count 2 2006.196.08:29:42.45#ibcon#read 4, iclass 35, count 2 2006.196.08:29:42.45#ibcon#about to read 5, iclass 35, count 2 2006.196.08:29:42.45#ibcon#read 5, iclass 35, count 2 2006.196.08:29:42.45#ibcon#about to read 6, iclass 35, count 2 2006.196.08:29:42.45#ibcon#read 6, iclass 35, count 2 2006.196.08:29:42.45#ibcon#end of sib2, iclass 35, count 2 2006.196.08:29:42.45#ibcon#*after write, iclass 35, count 2 2006.196.08:29:42.45#ibcon#*before return 0, iclass 35, count 2 2006.196.08:29:42.45#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.196.08:29:42.45#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.196.08:29:42.45#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.196.08:29:42.45#ibcon#ireg 7 cls_cnt 0 2006.196.08:29:42.45#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.196.08:29:42.57#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.196.08:29:42.57#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.196.08:29:42.57#ibcon#enter wrdev, iclass 35, count 0 2006.196.08:29:42.57#ibcon#first serial, iclass 35, count 0 2006.196.08:29:42.57#ibcon#enter sib2, iclass 35, count 0 2006.196.08:29:42.57#ibcon#flushed, iclass 35, count 0 2006.196.08:29:42.57#ibcon#about to write, iclass 35, count 0 2006.196.08:29:42.57#ibcon#wrote, iclass 35, count 0 2006.196.08:29:42.57#ibcon#about to read 3, iclass 35, count 0 2006.196.08:29:42.59#ibcon#read 3, iclass 35, count 0 2006.196.08:29:42.59#ibcon#about to read 4, iclass 35, count 0 2006.196.08:29:42.59#ibcon#read 4, iclass 35, count 0 2006.196.08:29:42.59#ibcon#about to read 5, iclass 35, count 0 2006.196.08:29:42.59#ibcon#read 5, iclass 35, count 0 2006.196.08:29:42.59#ibcon#about to read 6, iclass 35, count 0 2006.196.08:29:42.59#ibcon#read 6, iclass 35, count 0 2006.196.08:29:42.59#ibcon#end of sib2, iclass 35, count 0 2006.196.08:29:42.59#ibcon#*mode == 0, iclass 35, count 0 2006.196.08:29:42.59#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.196.08:29:42.59#ibcon#[27=USB\r\n] 2006.196.08:29:42.59#ibcon#*before write, iclass 35, count 0 2006.196.08:29:42.59#ibcon#enter sib2, iclass 35, count 0 2006.196.08:29:42.59#ibcon#flushed, iclass 35, count 0 2006.196.08:29:42.59#ibcon#about to write, iclass 35, count 0 2006.196.08:29:42.59#ibcon#wrote, iclass 35, count 0 2006.196.08:29:42.59#ibcon#about to read 3, iclass 35, count 0 2006.196.08:29:42.62#ibcon#read 3, iclass 35, count 0 2006.196.08:29:42.62#ibcon#about to read 4, iclass 35, count 0 2006.196.08:29:42.62#ibcon#read 4, iclass 35, count 0 2006.196.08:29:42.62#ibcon#about to read 5, iclass 35, count 0 2006.196.08:29:42.62#ibcon#read 5, iclass 35, count 0 2006.196.08:29:42.62#ibcon#about to read 6, iclass 35, count 0 2006.196.08:29:42.62#ibcon#read 6, iclass 35, count 0 2006.196.08:29:42.62#ibcon#end of sib2, iclass 35, count 0 2006.196.08:29:42.62#ibcon#*after write, iclass 35, count 0 2006.196.08:29:42.62#ibcon#*before return 0, iclass 35, count 0 2006.196.08:29:42.62#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.196.08:29:42.62#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.196.08:29:42.62#ibcon#about to clear, iclass 35 cls_cnt 0 2006.196.08:29:42.62#ibcon#cleared, iclass 35 cls_cnt 0 2006.196.08:29:42.62$vc4f8/vabw=wide 2006.196.08:29:42.62#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.196.08:29:42.62#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.196.08:29:42.62#ibcon#ireg 8 cls_cnt 0 2006.196.08:29:42.62#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.196.08:29:42.62#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.196.08:29:42.62#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.196.08:29:42.62#ibcon#enter wrdev, iclass 37, count 0 2006.196.08:29:42.62#ibcon#first serial, iclass 37, count 0 2006.196.08:29:42.62#ibcon#enter sib2, iclass 37, count 0 2006.196.08:29:42.62#ibcon#flushed, iclass 37, count 0 2006.196.08:29:42.62#ibcon#about to write, iclass 37, count 0 2006.196.08:29:42.62#ibcon#wrote, iclass 37, count 0 2006.196.08:29:42.62#ibcon#about to read 3, iclass 37, count 0 2006.196.08:29:42.64#ibcon#read 3, iclass 37, count 0 2006.196.08:29:42.64#ibcon#about to read 4, iclass 37, count 0 2006.196.08:29:42.64#ibcon#read 4, iclass 37, count 0 2006.196.08:29:42.64#ibcon#about to read 5, iclass 37, count 0 2006.196.08:29:42.64#ibcon#read 5, iclass 37, count 0 2006.196.08:29:42.64#ibcon#about to read 6, iclass 37, count 0 2006.196.08:29:42.64#ibcon#read 6, iclass 37, count 0 2006.196.08:29:42.64#ibcon#end of sib2, iclass 37, count 0 2006.196.08:29:42.64#ibcon#*mode == 0, iclass 37, count 0 2006.196.08:29:42.64#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.196.08:29:42.64#ibcon#[25=BW32\r\n] 2006.196.08:29:42.64#ibcon#*before write, iclass 37, count 0 2006.196.08:29:42.64#ibcon#enter sib2, iclass 37, count 0 2006.196.08:29:42.64#ibcon#flushed, iclass 37, count 0 2006.196.08:29:42.64#ibcon#about to write, iclass 37, count 0 2006.196.08:29:42.64#ibcon#wrote, iclass 37, count 0 2006.196.08:29:42.64#ibcon#about to read 3, iclass 37, count 0 2006.196.08:29:42.67#ibcon#read 3, iclass 37, count 0 2006.196.08:29:42.67#ibcon#about to read 4, iclass 37, count 0 2006.196.08:29:42.67#ibcon#read 4, iclass 37, count 0 2006.196.08:29:42.67#ibcon#about to read 5, iclass 37, count 0 2006.196.08:29:42.67#ibcon#read 5, iclass 37, count 0 2006.196.08:29:42.67#ibcon#about to read 6, iclass 37, count 0 2006.196.08:29:42.67#ibcon#read 6, iclass 37, count 0 2006.196.08:29:42.67#ibcon#end of sib2, iclass 37, count 0 2006.196.08:29:42.67#ibcon#*after write, iclass 37, count 0 2006.196.08:29:42.67#ibcon#*before return 0, iclass 37, count 0 2006.196.08:29:42.67#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.196.08:29:42.67#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.196.08:29:42.67#ibcon#about to clear, iclass 37 cls_cnt 0 2006.196.08:29:42.67#ibcon#cleared, iclass 37 cls_cnt 0 2006.196.08:29:42.67$vc4f8/vbbw=wide 2006.196.08:29:42.67#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.196.08:29:42.67#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.196.08:29:42.67#ibcon#ireg 8 cls_cnt 0 2006.196.08:29:42.67#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.196.08:29:42.74#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.196.08:29:42.74#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.196.08:29:42.74#ibcon#enter wrdev, iclass 39, count 0 2006.196.08:29:42.74#ibcon#first serial, iclass 39, count 0 2006.196.08:29:42.74#ibcon#enter sib2, iclass 39, count 0 2006.196.08:29:42.74#ibcon#flushed, iclass 39, count 0 2006.196.08:29:42.74#ibcon#about to write, iclass 39, count 0 2006.196.08:29:42.74#ibcon#wrote, iclass 39, count 0 2006.196.08:29:42.74#ibcon#about to read 3, iclass 39, count 0 2006.196.08:29:42.76#ibcon#read 3, iclass 39, count 0 2006.196.08:29:42.76#ibcon#about to read 4, iclass 39, count 0 2006.196.08:29:42.76#ibcon#read 4, iclass 39, count 0 2006.196.08:29:42.76#ibcon#about to read 5, iclass 39, count 0 2006.196.08:29:42.76#ibcon#read 5, iclass 39, count 0 2006.196.08:29:42.76#ibcon#about to read 6, iclass 39, count 0 2006.196.08:29:42.76#ibcon#read 6, iclass 39, count 0 2006.196.08:29:42.76#ibcon#end of sib2, iclass 39, count 0 2006.196.08:29:42.76#ibcon#*mode == 0, iclass 39, count 0 2006.196.08:29:42.76#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.196.08:29:42.76#ibcon#[27=BW32\r\n] 2006.196.08:29:42.76#ibcon#*before write, iclass 39, count 0 2006.196.08:29:42.76#ibcon#enter sib2, iclass 39, count 0 2006.196.08:29:42.76#ibcon#flushed, iclass 39, count 0 2006.196.08:29:42.76#ibcon#about to write, iclass 39, count 0 2006.196.08:29:42.76#ibcon#wrote, iclass 39, count 0 2006.196.08:29:42.76#ibcon#about to read 3, iclass 39, count 0 2006.196.08:29:42.79#ibcon#read 3, iclass 39, count 0 2006.196.08:29:42.79#ibcon#about to read 4, iclass 39, count 0 2006.196.08:29:42.79#ibcon#read 4, iclass 39, count 0 2006.196.08:29:42.79#ibcon#about to read 5, iclass 39, count 0 2006.196.08:29:42.79#ibcon#read 5, iclass 39, count 0 2006.196.08:29:42.79#ibcon#about to read 6, iclass 39, count 0 2006.196.08:29:42.79#ibcon#read 6, iclass 39, count 0 2006.196.08:29:42.79#ibcon#end of sib2, iclass 39, count 0 2006.196.08:29:42.79#ibcon#*after write, iclass 39, count 0 2006.196.08:29:42.79#ibcon#*before return 0, iclass 39, count 0 2006.196.08:29:42.79#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.196.08:29:42.79#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.196.08:29:42.79#ibcon#about to clear, iclass 39 cls_cnt 0 2006.196.08:29:42.79#ibcon#cleared, iclass 39 cls_cnt 0 2006.196.08:29:42.79$4f8m12a/ifd4f 2006.196.08:29:42.79$ifd4f/lo= 2006.196.08:29:42.79$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.196.08:29:42.79$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.196.08:29:42.79$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.196.08:29:42.79$ifd4f/patch= 2006.196.08:29:42.79$ifd4f/patch=lo1,a1,a2,a3,a4 2006.196.08:29:42.79$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.196.08:29:42.79$ifd4f/patch=lo3,a5,a6,a7,a8 2006.196.08:29:42.79$4f8m12a/"form=m,16.000,1:2 2006.196.08:29:42.79$4f8m12a/"tpicd 2006.196.08:29:42.79$4f8m12a/echo=off 2006.196.08:29:42.79$4f8m12a/xlog=off 2006.196.08:29:42.79:!2006.196.08:30:10 2006.196.08:29:50.14#trakl#Source acquired 2006.196.08:29:52.14#flagr#flagr/antenna,acquired 2006.196.08:30:10.00:preob 2006.196.08:30:11.14/onsource/TRACKING 2006.196.08:30:11.14:!2006.196.08:30:20 2006.196.08:30:20.00:data_valid=on 2006.196.08:30:20.00:midob 2006.196.08:30:20.14/onsource/TRACKING 2006.196.08:30:20.14/wx/28.73,1004.3,93 2006.196.08:30:20.30/cable/+6.3391E-03 2006.196.08:30:21.39/va/01,08,usb,yes,29,31 2006.196.08:30:21.39/va/02,07,usb,yes,29,31 2006.196.08:30:21.39/va/03,06,usb,yes,31,31 2006.196.08:30:21.39/va/04,07,usb,yes,30,32 2006.196.08:30:21.39/va/05,07,usb,yes,32,34 2006.196.08:30:21.39/va/06,06,usb,yes,32,31 2006.196.08:30:21.39/va/07,06,usb,yes,32,32 2006.196.08:30:21.39/va/08,07,usb,yes,30,30 2006.196.08:30:21.62/valo/01,532.99,yes,locked 2006.196.08:30:21.62/valo/02,572.99,yes,locked 2006.196.08:30:21.62/valo/03,672.99,yes,locked 2006.196.08:30:21.62/valo/04,832.99,yes,locked 2006.196.08:30:21.62/valo/05,652.99,yes,locked 2006.196.08:30:21.62/valo/06,772.99,yes,locked 2006.196.08:30:21.62/valo/07,832.99,yes,locked 2006.196.08:30:21.62/valo/08,852.99,yes,locked 2006.196.08:30:22.71/vb/01,04,usb,yes,28,27 2006.196.08:30:22.71/vb/02,04,usb,yes,30,31 2006.196.08:30:22.71/vb/03,04,usb,yes,27,30 2006.196.08:30:22.71/vb/04,04,usb,yes,27,27 2006.196.08:30:22.71/vb/05,04,usb,yes,26,30 2006.196.08:30:22.71/vb/06,04,usb,yes,27,30 2006.196.08:30:22.71/vb/07,04,usb,yes,29,29 2006.196.08:30:22.71/vb/08,04,usb,yes,27,30 2006.196.08:30:22.95/vblo/01,632.99,yes,locked 2006.196.08:30:22.95/vblo/02,640.99,yes,locked 2006.196.08:30:22.95/vblo/03,656.99,yes,locked 2006.196.08:30:22.95/vblo/04,712.99,yes,locked 2006.196.08:30:22.95/vblo/05,744.99,yes,locked 2006.196.08:30:22.95/vblo/06,752.99,yes,locked 2006.196.08:30:22.95/vblo/07,734.99,yes,locked 2006.196.08:30:22.95/vblo/08,744.99,yes,locked 2006.196.08:30:23.10/vabw/8 2006.196.08:30:23.25/vbbw/8 2006.196.08:30:23.34/xfe/off,on,14.7 2006.196.08:30:23.74/ifatt/23,28,28,28 2006.196.08:30:24.07/fmout-gps/S +3.35E-07 2006.196.08:30:24.14:!2006.196.08:31:20 2006.196.08:31:20.00:data_valid=off 2006.196.08:31:20.00:postob 2006.196.08:31:20.22/cable/+6.3391E-03 2006.196.08:31:20.22/wx/28.72,1004.3,93 2006.196.08:31:21.07/fmout-gps/S +3.36E-07 2006.196.08:31:21.07:scan_name=196-0832,k06196,60 2006.196.08:31:21.07:source=3c371,180650.68,694928.1,2000.0,cw 2006.196.08:31:21.13#flagr#flagr/antenna,new-source 2006.196.08:31:22.13:checkk5 2006.196.08:31:22.50/chk_autoobs//k5ts1/ autoobs is running! 2006.196.08:31:22.87/chk_autoobs//k5ts2/ autoobs is running! 2006.196.08:31:23.24/chk_autoobs//k5ts3/ autoobs is running! 2006.196.08:31:23.61/chk_autoobs//k5ts4/ autoobs is running! 2006.196.08:31:23.97/chk_obsdata//k5ts1/T1960830??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.196.08:31:24.34/chk_obsdata//k5ts2/T1960830??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.196.08:31:24.71/chk_obsdata//k5ts3/T1960830??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.196.08:31:25.08/chk_obsdata//k5ts4/T1960830??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.196.08:31:25.77/k5log//k5ts1_log_newline 2006.196.08:31:26.47/k5log//k5ts2_log_newline 2006.196.08:31:27.16/k5log//k5ts3_log_newline 2006.196.08:31:27.85/k5log//k5ts4_log_newline 2006.196.08:31:27.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.196.08:31:27.87:4f8m12a=3 2006.196.08:31:27.87$4f8m12a/echo=on 2006.196.08:31:27.87$4f8m12a/pcalon 2006.196.08:31:27.87$pcalon/"no phase cal control is implemented here 2006.196.08:31:27.87$4f8m12a/"tpicd=stop 2006.196.08:31:27.87$4f8m12a/vc4f8 2006.196.08:31:27.87$vc4f8/valo=1,532.99 2006.196.08:31:27.88#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.196.08:31:27.88#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.196.08:31:27.88#ibcon#ireg 17 cls_cnt 0 2006.196.08:31:27.88#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.196.08:31:27.88#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.196.08:31:27.88#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.196.08:31:27.88#ibcon#enter wrdev, iclass 10, count 0 2006.196.08:31:27.88#ibcon#first serial, iclass 10, count 0 2006.196.08:31:27.88#ibcon#enter sib2, iclass 10, count 0 2006.196.08:31:27.88#ibcon#flushed, iclass 10, count 0 2006.196.08:31:27.88#ibcon#about to write, iclass 10, count 0 2006.196.08:31:27.88#ibcon#wrote, iclass 10, count 0 2006.196.08:31:27.88#ibcon#about to read 3, iclass 10, count 0 2006.196.08:31:27.92#ibcon#read 3, iclass 10, count 0 2006.196.08:31:27.92#ibcon#about to read 4, iclass 10, count 0 2006.196.08:31:27.92#ibcon#read 4, iclass 10, count 0 2006.196.08:31:27.92#ibcon#about to read 5, iclass 10, count 0 2006.196.08:31:27.92#ibcon#read 5, iclass 10, count 0 2006.196.08:31:27.92#ibcon#about to read 6, iclass 10, count 0 2006.196.08:31:27.92#ibcon#read 6, iclass 10, count 0 2006.196.08:31:27.92#ibcon#end of sib2, iclass 10, count 0 2006.196.08:31:27.92#ibcon#*mode == 0, iclass 10, count 0 2006.196.08:31:27.92#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.196.08:31:27.92#ibcon#[26=FRQ=01,532.99\r\n] 2006.196.08:31:27.92#ibcon#*before write, iclass 10, count 0 2006.196.08:31:27.92#ibcon#enter sib2, iclass 10, count 0 2006.196.08:31:27.92#ibcon#flushed, iclass 10, count 0 2006.196.08:31:27.92#ibcon#about to write, iclass 10, count 0 2006.196.08:31:27.92#ibcon#wrote, iclass 10, count 0 2006.196.08:31:27.92#ibcon#about to read 3, iclass 10, count 0 2006.196.08:31:27.97#ibcon#read 3, iclass 10, count 0 2006.196.08:31:27.97#ibcon#about to read 4, iclass 10, count 0 2006.196.08:31:27.97#ibcon#read 4, iclass 10, count 0 2006.196.08:31:27.97#ibcon#about to read 5, iclass 10, count 0 2006.196.08:31:27.97#ibcon#read 5, iclass 10, count 0 2006.196.08:31:27.97#ibcon#about to read 6, iclass 10, count 0 2006.196.08:31:27.97#ibcon#read 6, iclass 10, count 0 2006.196.08:31:27.97#ibcon#end of sib2, iclass 10, count 0 2006.196.08:31:27.97#ibcon#*after write, iclass 10, count 0 2006.196.08:31:27.97#ibcon#*before return 0, iclass 10, count 0 2006.196.08:31:27.97#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.196.08:31:27.97#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.196.08:31:27.97#ibcon#about to clear, iclass 10 cls_cnt 0 2006.196.08:31:27.97#ibcon#cleared, iclass 10 cls_cnt 0 2006.196.08:31:27.97$vc4f8/va=1,8 2006.196.08:31:27.97#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.196.08:31:27.97#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.196.08:31:27.97#ibcon#ireg 11 cls_cnt 2 2006.196.08:31:27.97#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.196.08:31:27.97#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.196.08:31:27.97#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.196.08:31:27.97#ibcon#enter wrdev, iclass 12, count 2 2006.196.08:31:27.97#ibcon#first serial, iclass 12, count 2 2006.196.08:31:27.97#ibcon#enter sib2, iclass 12, count 2 2006.196.08:31:27.97#ibcon#flushed, iclass 12, count 2 2006.196.08:31:27.97#ibcon#about to write, iclass 12, count 2 2006.196.08:31:27.97#ibcon#wrote, iclass 12, count 2 2006.196.08:31:27.97#ibcon#about to read 3, iclass 12, count 2 2006.196.08:31:27.99#ibcon#read 3, iclass 12, count 2 2006.196.08:31:27.99#ibcon#about to read 4, iclass 12, count 2 2006.196.08:31:27.99#ibcon#read 4, iclass 12, count 2 2006.196.08:31:27.99#ibcon#about to read 5, iclass 12, count 2 2006.196.08:31:27.99#ibcon#read 5, iclass 12, count 2 2006.196.08:31:27.99#ibcon#about to read 6, iclass 12, count 2 2006.196.08:31:27.99#ibcon#read 6, iclass 12, count 2 2006.196.08:31:27.99#ibcon#end of sib2, iclass 12, count 2 2006.196.08:31:27.99#ibcon#*mode == 0, iclass 12, count 2 2006.196.08:31:27.99#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.196.08:31:27.99#ibcon#[25=AT01-08\r\n] 2006.196.08:31:27.99#ibcon#*before write, iclass 12, count 2 2006.196.08:31:27.99#ibcon#enter sib2, iclass 12, count 2 2006.196.08:31:27.99#ibcon#flushed, iclass 12, count 2 2006.196.08:31:27.99#ibcon#about to write, iclass 12, count 2 2006.196.08:31:27.99#ibcon#wrote, iclass 12, count 2 2006.196.08:31:27.99#ibcon#about to read 3, iclass 12, count 2 2006.196.08:31:28.02#ibcon#read 3, iclass 12, count 2 2006.196.08:31:28.02#ibcon#about to read 4, iclass 12, count 2 2006.196.08:31:28.02#ibcon#read 4, iclass 12, count 2 2006.196.08:31:28.02#ibcon#about to read 5, iclass 12, count 2 2006.196.08:31:28.02#ibcon#read 5, iclass 12, count 2 2006.196.08:31:28.02#ibcon#about to read 6, iclass 12, count 2 2006.196.08:31:28.02#ibcon#read 6, iclass 12, count 2 2006.196.08:31:28.02#ibcon#end of sib2, iclass 12, count 2 2006.196.08:31:28.02#ibcon#*after write, iclass 12, count 2 2006.196.08:31:28.02#ibcon#*before return 0, iclass 12, count 2 2006.196.08:31:28.02#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.196.08:31:28.02#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.196.08:31:28.02#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.196.08:31:28.02#ibcon#ireg 7 cls_cnt 0 2006.196.08:31:28.02#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.196.08:31:28.14#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.196.08:31:28.14#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.196.08:31:28.14#ibcon#enter wrdev, iclass 12, count 0 2006.196.08:31:28.14#ibcon#first serial, iclass 12, count 0 2006.196.08:31:28.14#ibcon#enter sib2, iclass 12, count 0 2006.196.08:31:28.14#ibcon#flushed, iclass 12, count 0 2006.196.08:31:28.14#ibcon#about to write, iclass 12, count 0 2006.196.08:31:28.14#ibcon#wrote, iclass 12, count 0 2006.196.08:31:28.14#ibcon#about to read 3, iclass 12, count 0 2006.196.08:31:28.16#ibcon#read 3, iclass 12, count 0 2006.196.08:31:28.16#ibcon#about to read 4, iclass 12, count 0 2006.196.08:31:28.16#ibcon#read 4, iclass 12, count 0 2006.196.08:31:28.16#ibcon#about to read 5, iclass 12, count 0 2006.196.08:31:28.16#ibcon#read 5, iclass 12, count 0 2006.196.08:31:28.16#ibcon#about to read 6, iclass 12, count 0 2006.196.08:31:28.16#ibcon#read 6, iclass 12, count 0 2006.196.08:31:28.16#ibcon#end of sib2, iclass 12, count 0 2006.196.08:31:28.16#ibcon#*mode == 0, iclass 12, count 0 2006.196.08:31:28.16#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.196.08:31:28.16#ibcon#[25=USB\r\n] 2006.196.08:31:28.16#ibcon#*before write, iclass 12, count 0 2006.196.08:31:28.16#ibcon#enter sib2, iclass 12, count 0 2006.196.08:31:28.16#ibcon#flushed, iclass 12, count 0 2006.196.08:31:28.16#ibcon#about to write, iclass 12, count 0 2006.196.08:31:28.16#ibcon#wrote, iclass 12, count 0 2006.196.08:31:28.16#ibcon#about to read 3, iclass 12, count 0 2006.196.08:31:28.19#ibcon#read 3, iclass 12, count 0 2006.196.08:31:28.19#ibcon#about to read 4, iclass 12, count 0 2006.196.08:31:28.19#ibcon#read 4, iclass 12, count 0 2006.196.08:31:28.19#ibcon#about to read 5, iclass 12, count 0 2006.196.08:31:28.19#ibcon#read 5, iclass 12, count 0 2006.196.08:31:28.19#ibcon#about to read 6, iclass 12, count 0 2006.196.08:31:28.19#ibcon#read 6, iclass 12, count 0 2006.196.08:31:28.19#ibcon#end of sib2, iclass 12, count 0 2006.196.08:31:28.19#ibcon#*after write, iclass 12, count 0 2006.196.08:31:28.19#ibcon#*before return 0, iclass 12, count 0 2006.196.08:31:28.19#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.196.08:31:28.19#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.196.08:31:28.19#ibcon#about to clear, iclass 12 cls_cnt 0 2006.196.08:31:28.19#ibcon#cleared, iclass 12 cls_cnt 0 2006.196.08:31:28.19$vc4f8/valo=2,572.99 2006.196.08:31:28.19#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.196.08:31:28.19#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.196.08:31:28.19#ibcon#ireg 17 cls_cnt 0 2006.196.08:31:28.19#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.196.08:31:28.19#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.196.08:31:28.19#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.196.08:31:28.19#ibcon#enter wrdev, iclass 14, count 0 2006.196.08:31:28.19#ibcon#first serial, iclass 14, count 0 2006.196.08:31:28.19#ibcon#enter sib2, iclass 14, count 0 2006.196.08:31:28.19#ibcon#flushed, iclass 14, count 0 2006.196.08:31:28.19#ibcon#about to write, iclass 14, count 0 2006.196.08:31:28.19#ibcon#wrote, iclass 14, count 0 2006.196.08:31:28.19#ibcon#about to read 3, iclass 14, count 0 2006.196.08:31:28.21#ibcon#read 3, iclass 14, count 0 2006.196.08:31:28.21#ibcon#about to read 4, iclass 14, count 0 2006.196.08:31:28.21#ibcon#read 4, iclass 14, count 0 2006.196.08:31:28.21#ibcon#about to read 5, iclass 14, count 0 2006.196.08:31:28.21#ibcon#read 5, iclass 14, count 0 2006.196.08:31:28.21#ibcon#about to read 6, iclass 14, count 0 2006.196.08:31:28.21#ibcon#read 6, iclass 14, count 0 2006.196.08:31:28.21#ibcon#end of sib2, iclass 14, count 0 2006.196.08:31:28.21#ibcon#*mode == 0, iclass 14, count 0 2006.196.08:31:28.21#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.196.08:31:28.21#ibcon#[26=FRQ=02,572.99\r\n] 2006.196.08:31:28.21#ibcon#*before write, iclass 14, count 0 2006.196.08:31:28.21#ibcon#enter sib2, iclass 14, count 0 2006.196.08:31:28.21#ibcon#flushed, iclass 14, count 0 2006.196.08:31:28.21#ibcon#about to write, iclass 14, count 0 2006.196.08:31:28.21#ibcon#wrote, iclass 14, count 0 2006.196.08:31:28.21#ibcon#about to read 3, iclass 14, count 0 2006.196.08:31:28.26#ibcon#read 3, iclass 14, count 0 2006.196.08:31:28.26#ibcon#about to read 4, iclass 14, count 0 2006.196.08:31:28.26#ibcon#read 4, iclass 14, count 0 2006.196.08:31:28.26#ibcon#about to read 5, iclass 14, count 0 2006.196.08:31:28.26#ibcon#read 5, iclass 14, count 0 2006.196.08:31:28.26#ibcon#about to read 6, iclass 14, count 0 2006.196.08:31:28.26#ibcon#read 6, iclass 14, count 0 2006.196.08:31:28.26#ibcon#end of sib2, iclass 14, count 0 2006.196.08:31:28.26#ibcon#*after write, iclass 14, count 0 2006.196.08:31:28.26#ibcon#*before return 0, iclass 14, count 0 2006.196.08:31:28.26#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.196.08:31:28.26#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.196.08:31:28.26#ibcon#about to clear, iclass 14 cls_cnt 0 2006.196.08:31:28.26#ibcon#cleared, iclass 14 cls_cnt 0 2006.196.08:31:28.26$vc4f8/va=2,7 2006.196.08:31:28.26#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.196.08:31:28.26#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.196.08:31:28.26#ibcon#ireg 11 cls_cnt 2 2006.196.08:31:28.26#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.196.08:31:28.31#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.196.08:31:28.31#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.196.08:31:28.31#ibcon#enter wrdev, iclass 16, count 2 2006.196.08:31:28.31#ibcon#first serial, iclass 16, count 2 2006.196.08:31:28.31#ibcon#enter sib2, iclass 16, count 2 2006.196.08:31:28.31#ibcon#flushed, iclass 16, count 2 2006.196.08:31:28.31#ibcon#about to write, iclass 16, count 2 2006.196.08:31:28.31#ibcon#wrote, iclass 16, count 2 2006.196.08:31:28.31#ibcon#about to read 3, iclass 16, count 2 2006.196.08:31:28.33#ibcon#read 3, iclass 16, count 2 2006.196.08:31:28.33#ibcon#about to read 4, iclass 16, count 2 2006.196.08:31:28.33#ibcon#read 4, iclass 16, count 2 2006.196.08:31:28.33#ibcon#about to read 5, iclass 16, count 2 2006.196.08:31:28.33#ibcon#read 5, iclass 16, count 2 2006.196.08:31:28.33#ibcon#about to read 6, iclass 16, count 2 2006.196.08:31:28.33#ibcon#read 6, iclass 16, count 2 2006.196.08:31:28.33#ibcon#end of sib2, iclass 16, count 2 2006.196.08:31:28.33#ibcon#*mode == 0, iclass 16, count 2 2006.196.08:31:28.33#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.196.08:31:28.33#ibcon#[25=AT02-07\r\n] 2006.196.08:31:28.33#ibcon#*before write, iclass 16, count 2 2006.196.08:31:28.33#ibcon#enter sib2, iclass 16, count 2 2006.196.08:31:28.33#ibcon#flushed, iclass 16, count 2 2006.196.08:31:28.33#ibcon#about to write, iclass 16, count 2 2006.196.08:31:28.33#ibcon#wrote, iclass 16, count 2 2006.196.08:31:28.33#ibcon#about to read 3, iclass 16, count 2 2006.196.08:31:28.36#ibcon#read 3, iclass 16, count 2 2006.196.08:31:28.36#ibcon#about to read 4, iclass 16, count 2 2006.196.08:31:28.36#ibcon#read 4, iclass 16, count 2 2006.196.08:31:28.36#ibcon#about to read 5, iclass 16, count 2 2006.196.08:31:28.36#ibcon#read 5, iclass 16, count 2 2006.196.08:31:28.36#ibcon#about to read 6, iclass 16, count 2 2006.196.08:31:28.36#ibcon#read 6, iclass 16, count 2 2006.196.08:31:28.36#ibcon#end of sib2, iclass 16, count 2 2006.196.08:31:28.36#ibcon#*after write, iclass 16, count 2 2006.196.08:31:28.36#ibcon#*before return 0, iclass 16, count 2 2006.196.08:31:28.36#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.196.08:31:28.36#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.196.08:31:28.36#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.196.08:31:28.36#ibcon#ireg 7 cls_cnt 0 2006.196.08:31:28.36#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.196.08:31:28.48#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.196.08:31:28.48#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.196.08:31:28.48#ibcon#enter wrdev, iclass 16, count 0 2006.196.08:31:28.48#ibcon#first serial, iclass 16, count 0 2006.196.08:31:28.48#ibcon#enter sib2, iclass 16, count 0 2006.196.08:31:28.48#ibcon#flushed, iclass 16, count 0 2006.196.08:31:28.48#ibcon#about to write, iclass 16, count 0 2006.196.08:31:28.48#ibcon#wrote, iclass 16, count 0 2006.196.08:31:28.48#ibcon#about to read 3, iclass 16, count 0 2006.196.08:31:28.50#ibcon#read 3, iclass 16, count 0 2006.196.08:31:28.50#ibcon#about to read 4, iclass 16, count 0 2006.196.08:31:28.50#ibcon#read 4, iclass 16, count 0 2006.196.08:31:28.50#ibcon#about to read 5, iclass 16, count 0 2006.196.08:31:28.50#ibcon#read 5, iclass 16, count 0 2006.196.08:31:28.50#ibcon#about to read 6, iclass 16, count 0 2006.196.08:31:28.50#ibcon#read 6, iclass 16, count 0 2006.196.08:31:28.50#ibcon#end of sib2, iclass 16, count 0 2006.196.08:31:28.50#ibcon#*mode == 0, iclass 16, count 0 2006.196.08:31:28.50#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.196.08:31:28.50#ibcon#[25=USB\r\n] 2006.196.08:31:28.50#ibcon#*before write, iclass 16, count 0 2006.196.08:31:28.50#ibcon#enter sib2, iclass 16, count 0 2006.196.08:31:28.50#ibcon#flushed, iclass 16, count 0 2006.196.08:31:28.50#ibcon#about to write, iclass 16, count 0 2006.196.08:31:28.50#ibcon#wrote, iclass 16, count 0 2006.196.08:31:28.50#ibcon#about to read 3, iclass 16, count 0 2006.196.08:31:28.53#ibcon#read 3, iclass 16, count 0 2006.196.08:31:28.53#ibcon#about to read 4, iclass 16, count 0 2006.196.08:31:28.53#ibcon#read 4, iclass 16, count 0 2006.196.08:31:28.53#ibcon#about to read 5, iclass 16, count 0 2006.196.08:31:28.53#ibcon#read 5, iclass 16, count 0 2006.196.08:31:28.53#ibcon#about to read 6, iclass 16, count 0 2006.196.08:31:28.53#ibcon#read 6, iclass 16, count 0 2006.196.08:31:28.53#ibcon#end of sib2, iclass 16, count 0 2006.196.08:31:28.53#ibcon#*after write, iclass 16, count 0 2006.196.08:31:28.53#ibcon#*before return 0, iclass 16, count 0 2006.196.08:31:28.53#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.196.08:31:28.53#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.196.08:31:28.53#ibcon#about to clear, iclass 16 cls_cnt 0 2006.196.08:31:28.53#ibcon#cleared, iclass 16 cls_cnt 0 2006.196.08:31:28.53$vc4f8/valo=3,672.99 2006.196.08:31:28.53#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.196.08:31:28.53#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.196.08:31:28.53#ibcon#ireg 17 cls_cnt 0 2006.196.08:31:28.53#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.196.08:31:28.53#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.196.08:31:28.53#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.196.08:31:28.53#ibcon#enter wrdev, iclass 18, count 0 2006.196.08:31:28.53#ibcon#first serial, iclass 18, count 0 2006.196.08:31:28.53#ibcon#enter sib2, iclass 18, count 0 2006.196.08:31:28.53#ibcon#flushed, iclass 18, count 0 2006.196.08:31:28.53#ibcon#about to write, iclass 18, count 0 2006.196.08:31:28.53#ibcon#wrote, iclass 18, count 0 2006.196.08:31:28.53#ibcon#about to read 3, iclass 18, count 0 2006.196.08:31:28.55#ibcon#read 3, iclass 18, count 0 2006.196.08:31:28.55#ibcon#about to read 4, iclass 18, count 0 2006.196.08:31:28.55#ibcon#read 4, iclass 18, count 0 2006.196.08:31:28.55#ibcon#about to read 5, iclass 18, count 0 2006.196.08:31:28.55#ibcon#read 5, iclass 18, count 0 2006.196.08:31:28.55#ibcon#about to read 6, iclass 18, count 0 2006.196.08:31:28.55#ibcon#read 6, iclass 18, count 0 2006.196.08:31:28.55#ibcon#end of sib2, iclass 18, count 0 2006.196.08:31:28.55#ibcon#*mode == 0, iclass 18, count 0 2006.196.08:31:28.55#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.196.08:31:28.55#ibcon#[26=FRQ=03,672.99\r\n] 2006.196.08:31:28.55#ibcon#*before write, iclass 18, count 0 2006.196.08:31:28.55#ibcon#enter sib2, iclass 18, count 0 2006.196.08:31:28.55#ibcon#flushed, iclass 18, count 0 2006.196.08:31:28.55#ibcon#about to write, iclass 18, count 0 2006.196.08:31:28.55#ibcon#wrote, iclass 18, count 0 2006.196.08:31:28.55#ibcon#about to read 3, iclass 18, count 0 2006.196.08:31:28.60#ibcon#read 3, iclass 18, count 0 2006.196.08:31:28.60#ibcon#about to read 4, iclass 18, count 0 2006.196.08:31:28.60#ibcon#read 4, iclass 18, count 0 2006.196.08:31:28.60#ibcon#about to read 5, iclass 18, count 0 2006.196.08:31:28.60#ibcon#read 5, iclass 18, count 0 2006.196.08:31:28.60#ibcon#about to read 6, iclass 18, count 0 2006.196.08:31:28.60#ibcon#read 6, iclass 18, count 0 2006.196.08:31:28.60#ibcon#end of sib2, iclass 18, count 0 2006.196.08:31:28.60#ibcon#*after write, iclass 18, count 0 2006.196.08:31:28.60#ibcon#*before return 0, iclass 18, count 0 2006.196.08:31:28.60#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.196.08:31:28.60#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.196.08:31:28.60#ibcon#about to clear, iclass 18 cls_cnt 0 2006.196.08:31:28.60#ibcon#cleared, iclass 18 cls_cnt 0 2006.196.08:31:28.60$vc4f8/va=3,6 2006.196.08:31:28.60#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.196.08:31:28.60#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.196.08:31:28.60#ibcon#ireg 11 cls_cnt 2 2006.196.08:31:28.60#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.196.08:31:28.65#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.196.08:31:28.65#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.196.08:31:28.65#ibcon#enter wrdev, iclass 20, count 2 2006.196.08:31:28.65#ibcon#first serial, iclass 20, count 2 2006.196.08:31:28.65#ibcon#enter sib2, iclass 20, count 2 2006.196.08:31:28.65#ibcon#flushed, iclass 20, count 2 2006.196.08:31:28.65#ibcon#about to write, iclass 20, count 2 2006.196.08:31:28.65#ibcon#wrote, iclass 20, count 2 2006.196.08:31:28.65#ibcon#about to read 3, iclass 20, count 2 2006.196.08:31:28.67#ibcon#read 3, iclass 20, count 2 2006.196.08:31:28.67#ibcon#about to read 4, iclass 20, count 2 2006.196.08:31:28.67#ibcon#read 4, iclass 20, count 2 2006.196.08:31:28.67#ibcon#about to read 5, iclass 20, count 2 2006.196.08:31:28.67#ibcon#read 5, iclass 20, count 2 2006.196.08:31:28.67#ibcon#about to read 6, iclass 20, count 2 2006.196.08:31:28.67#ibcon#read 6, iclass 20, count 2 2006.196.08:31:28.67#ibcon#end of sib2, iclass 20, count 2 2006.196.08:31:28.67#ibcon#*mode == 0, iclass 20, count 2 2006.196.08:31:28.67#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.196.08:31:28.67#ibcon#[25=AT03-06\r\n] 2006.196.08:31:28.67#ibcon#*before write, iclass 20, count 2 2006.196.08:31:28.67#ibcon#enter sib2, iclass 20, count 2 2006.196.08:31:28.67#ibcon#flushed, iclass 20, count 2 2006.196.08:31:28.67#ibcon#about to write, iclass 20, count 2 2006.196.08:31:28.67#ibcon#wrote, iclass 20, count 2 2006.196.08:31:28.67#ibcon#about to read 3, iclass 20, count 2 2006.196.08:31:28.70#ibcon#read 3, iclass 20, count 2 2006.196.08:31:28.70#ibcon#about to read 4, iclass 20, count 2 2006.196.08:31:28.70#ibcon#read 4, iclass 20, count 2 2006.196.08:31:28.70#ibcon#about to read 5, iclass 20, count 2 2006.196.08:31:28.70#ibcon#read 5, iclass 20, count 2 2006.196.08:31:28.70#ibcon#about to read 6, iclass 20, count 2 2006.196.08:31:28.70#ibcon#read 6, iclass 20, count 2 2006.196.08:31:28.70#ibcon#end of sib2, iclass 20, count 2 2006.196.08:31:28.70#ibcon#*after write, iclass 20, count 2 2006.196.08:31:28.70#ibcon#*before return 0, iclass 20, count 2 2006.196.08:31:28.70#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.196.08:31:28.70#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.196.08:31:28.70#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.196.08:31:28.70#ibcon#ireg 7 cls_cnt 0 2006.196.08:31:28.70#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.196.08:31:28.82#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.196.08:31:28.82#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.196.08:31:28.82#ibcon#enter wrdev, iclass 20, count 0 2006.196.08:31:28.82#ibcon#first serial, iclass 20, count 0 2006.196.08:31:28.82#ibcon#enter sib2, iclass 20, count 0 2006.196.08:31:28.82#ibcon#flushed, iclass 20, count 0 2006.196.08:31:28.82#ibcon#about to write, iclass 20, count 0 2006.196.08:31:28.82#ibcon#wrote, iclass 20, count 0 2006.196.08:31:28.82#ibcon#about to read 3, iclass 20, count 0 2006.196.08:31:28.84#ibcon#read 3, iclass 20, count 0 2006.196.08:31:28.84#ibcon#about to read 4, iclass 20, count 0 2006.196.08:31:28.84#ibcon#read 4, iclass 20, count 0 2006.196.08:31:28.84#ibcon#about to read 5, iclass 20, count 0 2006.196.08:31:28.84#ibcon#read 5, iclass 20, count 0 2006.196.08:31:28.84#ibcon#about to read 6, iclass 20, count 0 2006.196.08:31:28.84#ibcon#read 6, iclass 20, count 0 2006.196.08:31:28.84#ibcon#end of sib2, iclass 20, count 0 2006.196.08:31:28.84#ibcon#*mode == 0, iclass 20, count 0 2006.196.08:31:28.84#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.196.08:31:28.84#ibcon#[25=USB\r\n] 2006.196.08:31:28.84#ibcon#*before write, iclass 20, count 0 2006.196.08:31:28.84#ibcon#enter sib2, iclass 20, count 0 2006.196.08:31:28.84#ibcon#flushed, iclass 20, count 0 2006.196.08:31:28.84#ibcon#about to write, iclass 20, count 0 2006.196.08:31:28.84#ibcon#wrote, iclass 20, count 0 2006.196.08:31:28.84#ibcon#about to read 3, iclass 20, count 0 2006.196.08:31:28.87#ibcon#read 3, iclass 20, count 0 2006.196.08:31:28.87#ibcon#about to read 4, iclass 20, count 0 2006.196.08:31:28.87#ibcon#read 4, iclass 20, count 0 2006.196.08:31:28.87#ibcon#about to read 5, iclass 20, count 0 2006.196.08:31:28.87#ibcon#read 5, iclass 20, count 0 2006.196.08:31:28.87#ibcon#about to read 6, iclass 20, count 0 2006.196.08:31:28.87#ibcon#read 6, iclass 20, count 0 2006.196.08:31:28.87#ibcon#end of sib2, iclass 20, count 0 2006.196.08:31:28.87#ibcon#*after write, iclass 20, count 0 2006.196.08:31:28.87#ibcon#*before return 0, iclass 20, count 0 2006.196.08:31:28.87#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.196.08:31:28.87#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.196.08:31:28.87#ibcon#about to clear, iclass 20 cls_cnt 0 2006.196.08:31:28.87#ibcon#cleared, iclass 20 cls_cnt 0 2006.196.08:31:28.87$vc4f8/valo=4,832.99 2006.196.08:31:28.87#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.196.08:31:28.87#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.196.08:31:28.87#ibcon#ireg 17 cls_cnt 0 2006.196.08:31:28.87#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.196.08:31:28.87#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.196.08:31:28.87#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.196.08:31:28.87#ibcon#enter wrdev, iclass 22, count 0 2006.196.08:31:28.87#ibcon#first serial, iclass 22, count 0 2006.196.08:31:28.87#ibcon#enter sib2, iclass 22, count 0 2006.196.08:31:28.87#ibcon#flushed, iclass 22, count 0 2006.196.08:31:28.87#ibcon#about to write, iclass 22, count 0 2006.196.08:31:28.87#ibcon#wrote, iclass 22, count 0 2006.196.08:31:28.87#ibcon#about to read 3, iclass 22, count 0 2006.196.08:31:28.89#ibcon#read 3, iclass 22, count 0 2006.196.08:31:28.89#ibcon#about to read 4, iclass 22, count 0 2006.196.08:31:28.89#ibcon#read 4, iclass 22, count 0 2006.196.08:31:28.89#ibcon#about to read 5, iclass 22, count 0 2006.196.08:31:28.89#ibcon#read 5, iclass 22, count 0 2006.196.08:31:28.89#ibcon#about to read 6, iclass 22, count 0 2006.196.08:31:28.89#ibcon#read 6, iclass 22, count 0 2006.196.08:31:28.89#ibcon#end of sib2, iclass 22, count 0 2006.196.08:31:28.89#ibcon#*mode == 0, iclass 22, count 0 2006.196.08:31:28.89#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.196.08:31:28.89#ibcon#[26=FRQ=04,832.99\r\n] 2006.196.08:31:28.89#ibcon#*before write, iclass 22, count 0 2006.196.08:31:28.89#ibcon#enter sib2, iclass 22, count 0 2006.196.08:31:28.89#ibcon#flushed, iclass 22, count 0 2006.196.08:31:28.89#ibcon#about to write, iclass 22, count 0 2006.196.08:31:28.89#ibcon#wrote, iclass 22, count 0 2006.196.08:31:28.89#ibcon#about to read 3, iclass 22, count 0 2006.196.08:31:28.93#ibcon#read 3, iclass 22, count 0 2006.196.08:31:28.93#ibcon#about to read 4, iclass 22, count 0 2006.196.08:31:28.93#ibcon#read 4, iclass 22, count 0 2006.196.08:31:28.93#ibcon#about to read 5, iclass 22, count 0 2006.196.08:31:28.93#ibcon#read 5, iclass 22, count 0 2006.196.08:31:28.93#ibcon#about to read 6, iclass 22, count 0 2006.196.08:31:28.93#ibcon#read 6, iclass 22, count 0 2006.196.08:31:28.93#ibcon#end of sib2, iclass 22, count 0 2006.196.08:31:28.93#ibcon#*after write, iclass 22, count 0 2006.196.08:31:28.93#ibcon#*before return 0, iclass 22, count 0 2006.196.08:31:28.93#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.196.08:31:28.93#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.196.08:31:28.93#ibcon#about to clear, iclass 22 cls_cnt 0 2006.196.08:31:28.93#ibcon#cleared, iclass 22 cls_cnt 0 2006.196.08:31:28.93$vc4f8/va=4,7 2006.196.08:31:28.93#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.196.08:31:28.93#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.196.08:31:28.93#ibcon#ireg 11 cls_cnt 2 2006.196.08:31:28.93#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.196.08:31:28.99#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.196.08:31:28.99#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.196.08:31:28.99#ibcon#enter wrdev, iclass 24, count 2 2006.196.08:31:28.99#ibcon#first serial, iclass 24, count 2 2006.196.08:31:28.99#ibcon#enter sib2, iclass 24, count 2 2006.196.08:31:28.99#ibcon#flushed, iclass 24, count 2 2006.196.08:31:28.99#ibcon#about to write, iclass 24, count 2 2006.196.08:31:28.99#ibcon#wrote, iclass 24, count 2 2006.196.08:31:28.99#ibcon#about to read 3, iclass 24, count 2 2006.196.08:31:29.01#ibcon#read 3, iclass 24, count 2 2006.196.08:31:29.01#ibcon#about to read 4, iclass 24, count 2 2006.196.08:31:29.01#ibcon#read 4, iclass 24, count 2 2006.196.08:31:29.01#ibcon#about to read 5, iclass 24, count 2 2006.196.08:31:29.01#ibcon#read 5, iclass 24, count 2 2006.196.08:31:29.01#ibcon#about to read 6, iclass 24, count 2 2006.196.08:31:29.01#ibcon#read 6, iclass 24, count 2 2006.196.08:31:29.01#ibcon#end of sib2, iclass 24, count 2 2006.196.08:31:29.01#ibcon#*mode == 0, iclass 24, count 2 2006.196.08:31:29.01#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.196.08:31:29.01#ibcon#[25=AT04-07\r\n] 2006.196.08:31:29.01#ibcon#*before write, iclass 24, count 2 2006.196.08:31:29.01#ibcon#enter sib2, iclass 24, count 2 2006.196.08:31:29.01#ibcon#flushed, iclass 24, count 2 2006.196.08:31:29.01#ibcon#about to write, iclass 24, count 2 2006.196.08:31:29.01#ibcon#wrote, iclass 24, count 2 2006.196.08:31:29.01#ibcon#about to read 3, iclass 24, count 2 2006.196.08:31:29.04#ibcon#read 3, iclass 24, count 2 2006.196.08:31:29.04#ibcon#about to read 4, iclass 24, count 2 2006.196.08:31:29.04#ibcon#read 4, iclass 24, count 2 2006.196.08:31:29.04#ibcon#about to read 5, iclass 24, count 2 2006.196.08:31:29.04#ibcon#read 5, iclass 24, count 2 2006.196.08:31:29.04#ibcon#about to read 6, iclass 24, count 2 2006.196.08:31:29.04#ibcon#read 6, iclass 24, count 2 2006.196.08:31:29.04#ibcon#end of sib2, iclass 24, count 2 2006.196.08:31:29.04#ibcon#*after write, iclass 24, count 2 2006.196.08:31:29.04#ibcon#*before return 0, iclass 24, count 2 2006.196.08:31:29.04#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.196.08:31:29.04#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.196.08:31:29.04#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.196.08:31:29.04#ibcon#ireg 7 cls_cnt 0 2006.196.08:31:29.04#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.196.08:31:29.16#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.196.08:31:29.16#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.196.08:31:29.16#ibcon#enter wrdev, iclass 24, count 0 2006.196.08:31:29.16#ibcon#first serial, iclass 24, count 0 2006.196.08:31:29.16#ibcon#enter sib2, iclass 24, count 0 2006.196.08:31:29.16#ibcon#flushed, iclass 24, count 0 2006.196.08:31:29.16#ibcon#about to write, iclass 24, count 0 2006.196.08:31:29.16#ibcon#wrote, iclass 24, count 0 2006.196.08:31:29.16#ibcon#about to read 3, iclass 24, count 0 2006.196.08:31:29.18#ibcon#read 3, iclass 24, count 0 2006.196.08:31:29.18#ibcon#about to read 4, iclass 24, count 0 2006.196.08:31:29.18#ibcon#read 4, iclass 24, count 0 2006.196.08:31:29.18#ibcon#about to read 5, iclass 24, count 0 2006.196.08:31:29.18#ibcon#read 5, iclass 24, count 0 2006.196.08:31:29.18#ibcon#about to read 6, iclass 24, count 0 2006.196.08:31:29.18#ibcon#read 6, iclass 24, count 0 2006.196.08:31:29.18#ibcon#end of sib2, iclass 24, count 0 2006.196.08:31:29.18#ibcon#*mode == 0, iclass 24, count 0 2006.196.08:31:29.18#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.196.08:31:29.18#ibcon#[25=USB\r\n] 2006.196.08:31:29.18#ibcon#*before write, iclass 24, count 0 2006.196.08:31:29.18#ibcon#enter sib2, iclass 24, count 0 2006.196.08:31:29.18#ibcon#flushed, iclass 24, count 0 2006.196.08:31:29.18#ibcon#about to write, iclass 24, count 0 2006.196.08:31:29.18#ibcon#wrote, iclass 24, count 0 2006.196.08:31:29.18#ibcon#about to read 3, iclass 24, count 0 2006.196.08:31:29.21#ibcon#read 3, iclass 24, count 0 2006.196.08:31:29.21#ibcon#about to read 4, iclass 24, count 0 2006.196.08:31:29.21#ibcon#read 4, iclass 24, count 0 2006.196.08:31:29.21#ibcon#about to read 5, iclass 24, count 0 2006.196.08:31:29.21#ibcon#read 5, iclass 24, count 0 2006.196.08:31:29.21#ibcon#about to read 6, iclass 24, count 0 2006.196.08:31:29.21#ibcon#read 6, iclass 24, count 0 2006.196.08:31:29.21#ibcon#end of sib2, iclass 24, count 0 2006.196.08:31:29.21#ibcon#*after write, iclass 24, count 0 2006.196.08:31:29.21#ibcon#*before return 0, iclass 24, count 0 2006.196.08:31:29.21#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.196.08:31:29.21#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.196.08:31:29.21#ibcon#about to clear, iclass 24 cls_cnt 0 2006.196.08:31:29.21#ibcon#cleared, iclass 24 cls_cnt 0 2006.196.08:31:29.21$vc4f8/valo=5,652.99 2006.196.08:31:29.21#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.196.08:31:29.21#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.196.08:31:29.21#ibcon#ireg 17 cls_cnt 0 2006.196.08:31:29.21#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.196.08:31:29.21#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.196.08:31:29.21#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.196.08:31:29.21#ibcon#enter wrdev, iclass 26, count 0 2006.196.08:31:29.21#ibcon#first serial, iclass 26, count 0 2006.196.08:31:29.21#ibcon#enter sib2, iclass 26, count 0 2006.196.08:31:29.21#ibcon#flushed, iclass 26, count 0 2006.196.08:31:29.21#ibcon#about to write, iclass 26, count 0 2006.196.08:31:29.21#ibcon#wrote, iclass 26, count 0 2006.196.08:31:29.21#ibcon#about to read 3, iclass 26, count 0 2006.196.08:31:29.23#ibcon#read 3, iclass 26, count 0 2006.196.08:31:29.23#ibcon#about to read 4, iclass 26, count 0 2006.196.08:31:29.23#ibcon#read 4, iclass 26, count 0 2006.196.08:31:29.23#ibcon#about to read 5, iclass 26, count 0 2006.196.08:31:29.23#ibcon#read 5, iclass 26, count 0 2006.196.08:31:29.23#ibcon#about to read 6, iclass 26, count 0 2006.196.08:31:29.23#ibcon#read 6, iclass 26, count 0 2006.196.08:31:29.23#ibcon#end of sib2, iclass 26, count 0 2006.196.08:31:29.23#ibcon#*mode == 0, iclass 26, count 0 2006.196.08:31:29.23#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.196.08:31:29.23#ibcon#[26=FRQ=05,652.99\r\n] 2006.196.08:31:29.23#ibcon#*before write, iclass 26, count 0 2006.196.08:31:29.23#ibcon#enter sib2, iclass 26, count 0 2006.196.08:31:29.23#ibcon#flushed, iclass 26, count 0 2006.196.08:31:29.23#ibcon#about to write, iclass 26, count 0 2006.196.08:31:29.23#ibcon#wrote, iclass 26, count 0 2006.196.08:31:29.23#ibcon#about to read 3, iclass 26, count 0 2006.196.08:31:29.27#ibcon#read 3, iclass 26, count 0 2006.196.08:31:29.27#ibcon#about to read 4, iclass 26, count 0 2006.196.08:31:29.27#ibcon#read 4, iclass 26, count 0 2006.196.08:31:29.27#ibcon#about to read 5, iclass 26, count 0 2006.196.08:31:29.27#ibcon#read 5, iclass 26, count 0 2006.196.08:31:29.27#ibcon#about to read 6, iclass 26, count 0 2006.196.08:31:29.27#ibcon#read 6, iclass 26, count 0 2006.196.08:31:29.27#ibcon#end of sib2, iclass 26, count 0 2006.196.08:31:29.27#ibcon#*after write, iclass 26, count 0 2006.196.08:31:29.27#ibcon#*before return 0, iclass 26, count 0 2006.196.08:31:29.27#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.196.08:31:29.27#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.196.08:31:29.27#ibcon#about to clear, iclass 26 cls_cnt 0 2006.196.08:31:29.27#ibcon#cleared, iclass 26 cls_cnt 0 2006.196.08:31:29.27$vc4f8/va=5,7 2006.196.08:31:29.27#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.196.08:31:29.27#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.196.08:31:29.27#ibcon#ireg 11 cls_cnt 2 2006.196.08:31:29.27#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.196.08:31:29.33#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.196.08:31:29.33#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.196.08:31:29.33#ibcon#enter wrdev, iclass 28, count 2 2006.196.08:31:29.33#ibcon#first serial, iclass 28, count 2 2006.196.08:31:29.33#ibcon#enter sib2, iclass 28, count 2 2006.196.08:31:29.33#ibcon#flushed, iclass 28, count 2 2006.196.08:31:29.33#ibcon#about to write, iclass 28, count 2 2006.196.08:31:29.33#ibcon#wrote, iclass 28, count 2 2006.196.08:31:29.33#ibcon#about to read 3, iclass 28, count 2 2006.196.08:31:29.35#ibcon#read 3, iclass 28, count 2 2006.196.08:31:29.35#ibcon#about to read 4, iclass 28, count 2 2006.196.08:31:29.35#ibcon#read 4, iclass 28, count 2 2006.196.08:31:29.35#ibcon#about to read 5, iclass 28, count 2 2006.196.08:31:29.35#ibcon#read 5, iclass 28, count 2 2006.196.08:31:29.35#ibcon#about to read 6, iclass 28, count 2 2006.196.08:31:29.35#ibcon#read 6, iclass 28, count 2 2006.196.08:31:29.35#ibcon#end of sib2, iclass 28, count 2 2006.196.08:31:29.35#ibcon#*mode == 0, iclass 28, count 2 2006.196.08:31:29.35#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.196.08:31:29.35#ibcon#[25=AT05-07\r\n] 2006.196.08:31:29.35#ibcon#*before write, iclass 28, count 2 2006.196.08:31:29.35#ibcon#enter sib2, iclass 28, count 2 2006.196.08:31:29.35#ibcon#flushed, iclass 28, count 2 2006.196.08:31:29.35#ibcon#about to write, iclass 28, count 2 2006.196.08:31:29.35#ibcon#wrote, iclass 28, count 2 2006.196.08:31:29.35#ibcon#about to read 3, iclass 28, count 2 2006.196.08:31:29.38#ibcon#read 3, iclass 28, count 2 2006.196.08:31:29.38#ibcon#about to read 4, iclass 28, count 2 2006.196.08:31:29.38#ibcon#read 4, iclass 28, count 2 2006.196.08:31:29.38#ibcon#about to read 5, iclass 28, count 2 2006.196.08:31:29.38#ibcon#read 5, iclass 28, count 2 2006.196.08:31:29.38#ibcon#about to read 6, iclass 28, count 2 2006.196.08:31:29.38#ibcon#read 6, iclass 28, count 2 2006.196.08:31:29.38#ibcon#end of sib2, iclass 28, count 2 2006.196.08:31:29.38#ibcon#*after write, iclass 28, count 2 2006.196.08:31:29.38#ibcon#*before return 0, iclass 28, count 2 2006.196.08:31:29.38#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.196.08:31:29.38#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.196.08:31:29.38#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.196.08:31:29.38#ibcon#ireg 7 cls_cnt 0 2006.196.08:31:29.38#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.196.08:31:29.50#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.196.08:31:29.50#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.196.08:31:29.50#ibcon#enter wrdev, iclass 28, count 0 2006.196.08:31:29.50#ibcon#first serial, iclass 28, count 0 2006.196.08:31:29.50#ibcon#enter sib2, iclass 28, count 0 2006.196.08:31:29.50#ibcon#flushed, iclass 28, count 0 2006.196.08:31:29.50#ibcon#about to write, iclass 28, count 0 2006.196.08:31:29.50#ibcon#wrote, iclass 28, count 0 2006.196.08:31:29.50#ibcon#about to read 3, iclass 28, count 0 2006.196.08:31:29.52#ibcon#read 3, iclass 28, count 0 2006.196.08:31:29.52#ibcon#about to read 4, iclass 28, count 0 2006.196.08:31:29.52#ibcon#read 4, iclass 28, count 0 2006.196.08:31:29.52#ibcon#about to read 5, iclass 28, count 0 2006.196.08:31:29.52#ibcon#read 5, iclass 28, count 0 2006.196.08:31:29.52#ibcon#about to read 6, iclass 28, count 0 2006.196.08:31:29.52#ibcon#read 6, iclass 28, count 0 2006.196.08:31:29.52#ibcon#end of sib2, iclass 28, count 0 2006.196.08:31:29.52#ibcon#*mode == 0, iclass 28, count 0 2006.196.08:31:29.52#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.196.08:31:29.52#ibcon#[25=USB\r\n] 2006.196.08:31:29.52#ibcon#*before write, iclass 28, count 0 2006.196.08:31:29.52#ibcon#enter sib2, iclass 28, count 0 2006.196.08:31:29.52#ibcon#flushed, iclass 28, count 0 2006.196.08:31:29.52#ibcon#about to write, iclass 28, count 0 2006.196.08:31:29.52#ibcon#wrote, iclass 28, count 0 2006.196.08:31:29.52#ibcon#about to read 3, iclass 28, count 0 2006.196.08:31:29.55#ibcon#read 3, iclass 28, count 0 2006.196.08:31:29.55#ibcon#about to read 4, iclass 28, count 0 2006.196.08:31:29.55#ibcon#read 4, iclass 28, count 0 2006.196.08:31:29.55#ibcon#about to read 5, iclass 28, count 0 2006.196.08:31:29.55#ibcon#read 5, iclass 28, count 0 2006.196.08:31:29.55#ibcon#about to read 6, iclass 28, count 0 2006.196.08:31:29.55#ibcon#read 6, iclass 28, count 0 2006.196.08:31:29.55#ibcon#end of sib2, iclass 28, count 0 2006.196.08:31:29.55#ibcon#*after write, iclass 28, count 0 2006.196.08:31:29.55#ibcon#*before return 0, iclass 28, count 0 2006.196.08:31:29.55#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.196.08:31:29.55#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.196.08:31:29.55#ibcon#about to clear, iclass 28 cls_cnt 0 2006.196.08:31:29.55#ibcon#cleared, iclass 28 cls_cnt 0 2006.196.08:31:29.55$vc4f8/valo=6,772.99 2006.196.08:31:29.55#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.196.08:31:29.55#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.196.08:31:29.55#ibcon#ireg 17 cls_cnt 0 2006.196.08:31:29.55#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.196.08:31:29.55#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.196.08:31:29.55#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.196.08:31:29.55#ibcon#enter wrdev, iclass 30, count 0 2006.196.08:31:29.55#ibcon#first serial, iclass 30, count 0 2006.196.08:31:29.55#ibcon#enter sib2, iclass 30, count 0 2006.196.08:31:29.55#ibcon#flushed, iclass 30, count 0 2006.196.08:31:29.55#ibcon#about to write, iclass 30, count 0 2006.196.08:31:29.55#ibcon#wrote, iclass 30, count 0 2006.196.08:31:29.55#ibcon#about to read 3, iclass 30, count 0 2006.196.08:31:29.57#ibcon#read 3, iclass 30, count 0 2006.196.08:31:29.57#ibcon#about to read 4, iclass 30, count 0 2006.196.08:31:29.57#ibcon#read 4, iclass 30, count 0 2006.196.08:31:29.57#ibcon#about to read 5, iclass 30, count 0 2006.196.08:31:29.57#ibcon#read 5, iclass 30, count 0 2006.196.08:31:29.57#ibcon#about to read 6, iclass 30, count 0 2006.196.08:31:29.57#ibcon#read 6, iclass 30, count 0 2006.196.08:31:29.57#ibcon#end of sib2, iclass 30, count 0 2006.196.08:31:29.57#ibcon#*mode == 0, iclass 30, count 0 2006.196.08:31:29.57#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.196.08:31:29.57#ibcon#[26=FRQ=06,772.99\r\n] 2006.196.08:31:29.57#ibcon#*before write, iclass 30, count 0 2006.196.08:31:29.57#ibcon#enter sib2, iclass 30, count 0 2006.196.08:31:29.57#ibcon#flushed, iclass 30, count 0 2006.196.08:31:29.57#ibcon#about to write, iclass 30, count 0 2006.196.08:31:29.57#ibcon#wrote, iclass 30, count 0 2006.196.08:31:29.57#ibcon#about to read 3, iclass 30, count 0 2006.196.08:31:29.62#ibcon#read 3, iclass 30, count 0 2006.196.08:31:29.62#ibcon#about to read 4, iclass 30, count 0 2006.196.08:31:29.62#ibcon#read 4, iclass 30, count 0 2006.196.08:31:29.62#ibcon#about to read 5, iclass 30, count 0 2006.196.08:31:29.62#ibcon#read 5, iclass 30, count 0 2006.196.08:31:29.62#ibcon#about to read 6, iclass 30, count 0 2006.196.08:31:29.62#ibcon#read 6, iclass 30, count 0 2006.196.08:31:29.62#ibcon#end of sib2, iclass 30, count 0 2006.196.08:31:29.62#ibcon#*after write, iclass 30, count 0 2006.196.08:31:29.62#ibcon#*before return 0, iclass 30, count 0 2006.196.08:31:29.62#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.196.08:31:29.62#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.196.08:31:29.62#ibcon#about to clear, iclass 30 cls_cnt 0 2006.196.08:31:29.62#ibcon#cleared, iclass 30 cls_cnt 0 2006.196.08:31:29.62$vc4f8/va=6,6 2006.196.08:31:29.62#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.196.08:31:29.62#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.196.08:31:29.62#ibcon#ireg 11 cls_cnt 2 2006.196.08:31:29.62#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.196.08:31:29.67#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.196.08:31:29.67#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.196.08:31:29.67#ibcon#enter wrdev, iclass 32, count 2 2006.196.08:31:29.67#ibcon#first serial, iclass 32, count 2 2006.196.08:31:29.67#ibcon#enter sib2, iclass 32, count 2 2006.196.08:31:29.67#ibcon#flushed, iclass 32, count 2 2006.196.08:31:29.67#ibcon#about to write, iclass 32, count 2 2006.196.08:31:29.67#ibcon#wrote, iclass 32, count 2 2006.196.08:31:29.67#ibcon#about to read 3, iclass 32, count 2 2006.196.08:31:29.69#ibcon#read 3, iclass 32, count 2 2006.196.08:31:29.69#ibcon#about to read 4, iclass 32, count 2 2006.196.08:31:29.69#ibcon#read 4, iclass 32, count 2 2006.196.08:31:29.69#ibcon#about to read 5, iclass 32, count 2 2006.196.08:31:29.69#ibcon#read 5, iclass 32, count 2 2006.196.08:31:29.69#ibcon#about to read 6, iclass 32, count 2 2006.196.08:31:29.69#ibcon#read 6, iclass 32, count 2 2006.196.08:31:29.69#ibcon#end of sib2, iclass 32, count 2 2006.196.08:31:29.69#ibcon#*mode == 0, iclass 32, count 2 2006.196.08:31:29.69#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.196.08:31:29.69#ibcon#[25=AT06-06\r\n] 2006.196.08:31:29.69#ibcon#*before write, iclass 32, count 2 2006.196.08:31:29.69#ibcon#enter sib2, iclass 32, count 2 2006.196.08:31:29.69#ibcon#flushed, iclass 32, count 2 2006.196.08:31:29.69#ibcon#about to write, iclass 32, count 2 2006.196.08:31:29.69#ibcon#wrote, iclass 32, count 2 2006.196.08:31:29.69#ibcon#about to read 3, iclass 32, count 2 2006.196.08:31:29.72#ibcon#read 3, iclass 32, count 2 2006.196.08:31:29.72#ibcon#about to read 4, iclass 32, count 2 2006.196.08:31:29.72#ibcon#read 4, iclass 32, count 2 2006.196.08:31:29.72#ibcon#about to read 5, iclass 32, count 2 2006.196.08:31:29.72#ibcon#read 5, iclass 32, count 2 2006.196.08:31:29.72#ibcon#about to read 6, iclass 32, count 2 2006.196.08:31:29.72#ibcon#read 6, iclass 32, count 2 2006.196.08:31:29.72#ibcon#end of sib2, iclass 32, count 2 2006.196.08:31:29.72#ibcon#*after write, iclass 32, count 2 2006.196.08:31:29.72#ibcon#*before return 0, iclass 32, count 2 2006.196.08:31:29.72#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.196.08:31:29.72#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.196.08:31:29.72#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.196.08:31:29.72#ibcon#ireg 7 cls_cnt 0 2006.196.08:31:29.72#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.196.08:31:29.84#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.196.08:31:29.84#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.196.08:31:29.84#ibcon#enter wrdev, iclass 32, count 0 2006.196.08:31:29.84#ibcon#first serial, iclass 32, count 0 2006.196.08:31:29.84#ibcon#enter sib2, iclass 32, count 0 2006.196.08:31:29.84#ibcon#flushed, iclass 32, count 0 2006.196.08:31:29.84#ibcon#about to write, iclass 32, count 0 2006.196.08:31:29.84#ibcon#wrote, iclass 32, count 0 2006.196.08:31:29.84#ibcon#about to read 3, iclass 32, count 0 2006.196.08:31:29.86#ibcon#read 3, iclass 32, count 0 2006.196.08:31:29.86#ibcon#about to read 4, iclass 32, count 0 2006.196.08:31:29.86#ibcon#read 4, iclass 32, count 0 2006.196.08:31:29.86#ibcon#about to read 5, iclass 32, count 0 2006.196.08:31:29.86#ibcon#read 5, iclass 32, count 0 2006.196.08:31:29.86#ibcon#about to read 6, iclass 32, count 0 2006.196.08:31:29.86#ibcon#read 6, iclass 32, count 0 2006.196.08:31:29.86#ibcon#end of sib2, iclass 32, count 0 2006.196.08:31:29.86#ibcon#*mode == 0, iclass 32, count 0 2006.196.08:31:29.86#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.196.08:31:29.86#ibcon#[25=USB\r\n] 2006.196.08:31:29.86#ibcon#*before write, iclass 32, count 0 2006.196.08:31:29.86#ibcon#enter sib2, iclass 32, count 0 2006.196.08:31:29.86#ibcon#flushed, iclass 32, count 0 2006.196.08:31:29.86#ibcon#about to write, iclass 32, count 0 2006.196.08:31:29.86#ibcon#wrote, iclass 32, count 0 2006.196.08:31:29.86#ibcon#about to read 3, iclass 32, count 0 2006.196.08:31:29.89#ibcon#read 3, iclass 32, count 0 2006.196.08:31:29.89#ibcon#about to read 4, iclass 32, count 0 2006.196.08:31:29.89#ibcon#read 4, iclass 32, count 0 2006.196.08:31:29.89#ibcon#about to read 5, iclass 32, count 0 2006.196.08:31:29.89#ibcon#read 5, iclass 32, count 0 2006.196.08:31:29.89#ibcon#about to read 6, iclass 32, count 0 2006.196.08:31:29.89#ibcon#read 6, iclass 32, count 0 2006.196.08:31:29.89#ibcon#end of sib2, iclass 32, count 0 2006.196.08:31:29.89#ibcon#*after write, iclass 32, count 0 2006.196.08:31:29.89#ibcon#*before return 0, iclass 32, count 0 2006.196.08:31:29.89#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.196.08:31:29.89#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.196.08:31:29.89#ibcon#about to clear, iclass 32 cls_cnt 0 2006.196.08:31:29.89#ibcon#cleared, iclass 32 cls_cnt 0 2006.196.08:31:29.89$vc4f8/valo=7,832.99 2006.196.08:31:29.89#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.196.08:31:29.89#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.196.08:31:29.89#ibcon#ireg 17 cls_cnt 0 2006.196.08:31:29.89#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.196.08:31:29.89#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.196.08:31:29.89#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.196.08:31:29.89#ibcon#enter wrdev, iclass 34, count 0 2006.196.08:31:29.89#ibcon#first serial, iclass 34, count 0 2006.196.08:31:29.89#ibcon#enter sib2, iclass 34, count 0 2006.196.08:31:29.89#ibcon#flushed, iclass 34, count 0 2006.196.08:31:29.89#ibcon#about to write, iclass 34, count 0 2006.196.08:31:29.89#ibcon#wrote, iclass 34, count 0 2006.196.08:31:29.89#ibcon#about to read 3, iclass 34, count 0 2006.196.08:31:29.91#ibcon#read 3, iclass 34, count 0 2006.196.08:31:29.91#ibcon#about to read 4, iclass 34, count 0 2006.196.08:31:29.91#ibcon#read 4, iclass 34, count 0 2006.196.08:31:29.91#ibcon#about to read 5, iclass 34, count 0 2006.196.08:31:29.91#ibcon#read 5, iclass 34, count 0 2006.196.08:31:29.91#ibcon#about to read 6, iclass 34, count 0 2006.196.08:31:29.91#ibcon#read 6, iclass 34, count 0 2006.196.08:31:29.91#ibcon#end of sib2, iclass 34, count 0 2006.196.08:31:29.91#ibcon#*mode == 0, iclass 34, count 0 2006.196.08:31:29.91#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.196.08:31:29.91#ibcon#[26=FRQ=07,832.99\r\n] 2006.196.08:31:29.91#ibcon#*before write, iclass 34, count 0 2006.196.08:31:29.91#ibcon#enter sib2, iclass 34, count 0 2006.196.08:31:29.91#ibcon#flushed, iclass 34, count 0 2006.196.08:31:29.91#ibcon#about to write, iclass 34, count 0 2006.196.08:31:29.91#ibcon#wrote, iclass 34, count 0 2006.196.08:31:29.91#ibcon#about to read 3, iclass 34, count 0 2006.196.08:31:29.95#ibcon#read 3, iclass 34, count 0 2006.196.08:31:29.95#ibcon#about to read 4, iclass 34, count 0 2006.196.08:31:29.95#ibcon#read 4, iclass 34, count 0 2006.196.08:31:29.95#ibcon#about to read 5, iclass 34, count 0 2006.196.08:31:29.95#ibcon#read 5, iclass 34, count 0 2006.196.08:31:29.95#ibcon#about to read 6, iclass 34, count 0 2006.196.08:31:29.95#ibcon#read 6, iclass 34, count 0 2006.196.08:31:29.95#ibcon#end of sib2, iclass 34, count 0 2006.196.08:31:29.95#ibcon#*after write, iclass 34, count 0 2006.196.08:31:29.95#ibcon#*before return 0, iclass 34, count 0 2006.196.08:31:29.95#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.196.08:31:29.95#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.196.08:31:29.95#ibcon#about to clear, iclass 34 cls_cnt 0 2006.196.08:31:29.95#ibcon#cleared, iclass 34 cls_cnt 0 2006.196.08:31:29.95$vc4f8/va=7,6 2006.196.08:31:29.95#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.196.08:31:29.95#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.196.08:31:29.95#ibcon#ireg 11 cls_cnt 2 2006.196.08:31:29.95#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.196.08:31:30.01#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.196.08:31:30.01#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.196.08:31:30.01#ibcon#enter wrdev, iclass 36, count 2 2006.196.08:31:30.01#ibcon#first serial, iclass 36, count 2 2006.196.08:31:30.01#ibcon#enter sib2, iclass 36, count 2 2006.196.08:31:30.01#ibcon#flushed, iclass 36, count 2 2006.196.08:31:30.01#ibcon#about to write, iclass 36, count 2 2006.196.08:31:30.01#ibcon#wrote, iclass 36, count 2 2006.196.08:31:30.01#ibcon#about to read 3, iclass 36, count 2 2006.196.08:31:30.03#ibcon#read 3, iclass 36, count 2 2006.196.08:31:30.03#ibcon#about to read 4, iclass 36, count 2 2006.196.08:31:30.03#ibcon#read 4, iclass 36, count 2 2006.196.08:31:30.03#ibcon#about to read 5, iclass 36, count 2 2006.196.08:31:30.03#ibcon#read 5, iclass 36, count 2 2006.196.08:31:30.03#ibcon#about to read 6, iclass 36, count 2 2006.196.08:31:30.03#ibcon#read 6, iclass 36, count 2 2006.196.08:31:30.03#ibcon#end of sib2, iclass 36, count 2 2006.196.08:31:30.03#ibcon#*mode == 0, iclass 36, count 2 2006.196.08:31:30.03#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.196.08:31:30.03#ibcon#[25=AT07-06\r\n] 2006.196.08:31:30.03#ibcon#*before write, iclass 36, count 2 2006.196.08:31:30.03#ibcon#enter sib2, iclass 36, count 2 2006.196.08:31:30.03#ibcon#flushed, iclass 36, count 2 2006.196.08:31:30.03#ibcon#about to write, iclass 36, count 2 2006.196.08:31:30.03#ibcon#wrote, iclass 36, count 2 2006.196.08:31:30.03#ibcon#about to read 3, iclass 36, count 2 2006.196.08:31:30.06#ibcon#read 3, iclass 36, count 2 2006.196.08:31:30.06#ibcon#about to read 4, iclass 36, count 2 2006.196.08:31:30.06#ibcon#read 4, iclass 36, count 2 2006.196.08:31:30.06#ibcon#about to read 5, iclass 36, count 2 2006.196.08:31:30.06#ibcon#read 5, iclass 36, count 2 2006.196.08:31:30.06#ibcon#about to read 6, iclass 36, count 2 2006.196.08:31:30.06#ibcon#read 6, iclass 36, count 2 2006.196.08:31:30.06#ibcon#end of sib2, iclass 36, count 2 2006.196.08:31:30.06#ibcon#*after write, iclass 36, count 2 2006.196.08:31:30.06#ibcon#*before return 0, iclass 36, count 2 2006.196.08:31:30.06#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.196.08:31:30.06#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.196.08:31:30.06#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.196.08:31:30.06#ibcon#ireg 7 cls_cnt 0 2006.196.08:31:30.06#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.196.08:31:30.18#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.196.08:31:30.18#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.196.08:31:30.18#ibcon#enter wrdev, iclass 36, count 0 2006.196.08:31:30.18#ibcon#first serial, iclass 36, count 0 2006.196.08:31:30.18#ibcon#enter sib2, iclass 36, count 0 2006.196.08:31:30.18#ibcon#flushed, iclass 36, count 0 2006.196.08:31:30.18#ibcon#about to write, iclass 36, count 0 2006.196.08:31:30.18#ibcon#wrote, iclass 36, count 0 2006.196.08:31:30.18#ibcon#about to read 3, iclass 36, count 0 2006.196.08:31:30.21#ibcon#read 3, iclass 36, count 0 2006.196.08:31:30.21#ibcon#about to read 4, iclass 36, count 0 2006.196.08:31:30.21#ibcon#read 4, iclass 36, count 0 2006.196.08:31:30.21#ibcon#about to read 5, iclass 36, count 0 2006.196.08:31:30.21#ibcon#read 5, iclass 36, count 0 2006.196.08:31:30.21#ibcon#about to read 6, iclass 36, count 0 2006.196.08:31:30.21#ibcon#read 6, iclass 36, count 0 2006.196.08:31:30.21#ibcon#end of sib2, iclass 36, count 0 2006.196.08:31:30.21#ibcon#*mode == 0, iclass 36, count 0 2006.196.08:31:30.21#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.196.08:31:30.21#ibcon#[25=USB\r\n] 2006.196.08:31:30.21#ibcon#*before write, iclass 36, count 0 2006.196.08:31:30.21#ibcon#enter sib2, iclass 36, count 0 2006.196.08:31:30.21#ibcon#flushed, iclass 36, count 0 2006.196.08:31:30.21#ibcon#about to write, iclass 36, count 0 2006.196.08:31:30.21#ibcon#wrote, iclass 36, count 0 2006.196.08:31:30.21#ibcon#about to read 3, iclass 36, count 0 2006.196.08:31:30.24#ibcon#read 3, iclass 36, count 0 2006.196.08:31:30.24#ibcon#about to read 4, iclass 36, count 0 2006.196.08:31:30.24#ibcon#read 4, iclass 36, count 0 2006.196.08:31:30.24#ibcon#about to read 5, iclass 36, count 0 2006.196.08:31:30.24#ibcon#read 5, iclass 36, count 0 2006.196.08:31:30.24#ibcon#about to read 6, iclass 36, count 0 2006.196.08:31:30.24#ibcon#read 6, iclass 36, count 0 2006.196.08:31:30.24#ibcon#end of sib2, iclass 36, count 0 2006.196.08:31:30.24#ibcon#*after write, iclass 36, count 0 2006.196.08:31:30.24#ibcon#*before return 0, iclass 36, count 0 2006.196.08:31:30.24#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.196.08:31:30.24#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.196.08:31:30.24#ibcon#about to clear, iclass 36 cls_cnt 0 2006.196.08:31:30.24#ibcon#cleared, iclass 36 cls_cnt 0 2006.196.08:31:30.24$vc4f8/valo=8,852.99 2006.196.08:31:30.24#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.196.08:31:30.24#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.196.08:31:30.24#ibcon#ireg 17 cls_cnt 0 2006.196.08:31:30.24#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.196.08:31:30.24#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.196.08:31:30.24#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.196.08:31:30.24#ibcon#enter wrdev, iclass 38, count 0 2006.196.08:31:30.24#ibcon#first serial, iclass 38, count 0 2006.196.08:31:30.24#ibcon#enter sib2, iclass 38, count 0 2006.196.08:31:30.24#ibcon#flushed, iclass 38, count 0 2006.196.08:31:30.24#ibcon#about to write, iclass 38, count 0 2006.196.08:31:30.24#ibcon#wrote, iclass 38, count 0 2006.196.08:31:30.24#ibcon#about to read 3, iclass 38, count 0 2006.196.08:31:30.26#ibcon#read 3, iclass 38, count 0 2006.196.08:31:30.26#ibcon#about to read 4, iclass 38, count 0 2006.196.08:31:30.26#ibcon#read 4, iclass 38, count 0 2006.196.08:31:30.26#ibcon#about to read 5, iclass 38, count 0 2006.196.08:31:30.26#ibcon#read 5, iclass 38, count 0 2006.196.08:31:30.26#ibcon#about to read 6, iclass 38, count 0 2006.196.08:31:30.26#ibcon#read 6, iclass 38, count 0 2006.196.08:31:30.26#ibcon#end of sib2, iclass 38, count 0 2006.196.08:31:30.26#ibcon#*mode == 0, iclass 38, count 0 2006.196.08:31:30.26#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.196.08:31:30.26#ibcon#[26=FRQ=08,852.99\r\n] 2006.196.08:31:30.26#ibcon#*before write, iclass 38, count 0 2006.196.08:31:30.26#ibcon#enter sib2, iclass 38, count 0 2006.196.08:31:30.26#ibcon#flushed, iclass 38, count 0 2006.196.08:31:30.26#ibcon#about to write, iclass 38, count 0 2006.196.08:31:30.26#ibcon#wrote, iclass 38, count 0 2006.196.08:31:30.26#ibcon#about to read 3, iclass 38, count 0 2006.196.08:31:30.30#ibcon#read 3, iclass 38, count 0 2006.196.08:31:30.30#ibcon#about to read 4, iclass 38, count 0 2006.196.08:31:30.30#ibcon#read 4, iclass 38, count 0 2006.196.08:31:30.30#ibcon#about to read 5, iclass 38, count 0 2006.196.08:31:30.30#ibcon#read 5, iclass 38, count 0 2006.196.08:31:30.30#ibcon#about to read 6, iclass 38, count 0 2006.196.08:31:30.30#ibcon#read 6, iclass 38, count 0 2006.196.08:31:30.30#ibcon#end of sib2, iclass 38, count 0 2006.196.08:31:30.30#ibcon#*after write, iclass 38, count 0 2006.196.08:31:30.30#ibcon#*before return 0, iclass 38, count 0 2006.196.08:31:30.30#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.196.08:31:30.30#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.196.08:31:30.30#ibcon#about to clear, iclass 38 cls_cnt 0 2006.196.08:31:30.30#ibcon#cleared, iclass 38 cls_cnt 0 2006.196.08:31:30.30$vc4f8/va=8,7 2006.196.08:31:30.30#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.196.08:31:30.30#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.196.08:31:30.30#ibcon#ireg 11 cls_cnt 2 2006.196.08:31:30.30#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.196.08:31:30.36#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.196.08:31:30.36#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.196.08:31:30.36#ibcon#enter wrdev, iclass 40, count 2 2006.196.08:31:30.36#ibcon#first serial, iclass 40, count 2 2006.196.08:31:30.36#ibcon#enter sib2, iclass 40, count 2 2006.196.08:31:30.36#ibcon#flushed, iclass 40, count 2 2006.196.08:31:30.36#ibcon#about to write, iclass 40, count 2 2006.196.08:31:30.36#ibcon#wrote, iclass 40, count 2 2006.196.08:31:30.36#ibcon#about to read 3, iclass 40, count 2 2006.196.08:31:30.38#ibcon#read 3, iclass 40, count 2 2006.196.08:31:30.38#ibcon#about to read 4, iclass 40, count 2 2006.196.08:31:30.38#ibcon#read 4, iclass 40, count 2 2006.196.08:31:30.38#ibcon#about to read 5, iclass 40, count 2 2006.196.08:31:30.38#ibcon#read 5, iclass 40, count 2 2006.196.08:31:30.38#ibcon#about to read 6, iclass 40, count 2 2006.196.08:31:30.38#ibcon#read 6, iclass 40, count 2 2006.196.08:31:30.38#ibcon#end of sib2, iclass 40, count 2 2006.196.08:31:30.38#ibcon#*mode == 0, iclass 40, count 2 2006.196.08:31:30.38#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.196.08:31:30.38#ibcon#[25=AT08-07\r\n] 2006.196.08:31:30.38#ibcon#*before write, iclass 40, count 2 2006.196.08:31:30.38#ibcon#enter sib2, iclass 40, count 2 2006.196.08:31:30.38#ibcon#flushed, iclass 40, count 2 2006.196.08:31:30.38#ibcon#about to write, iclass 40, count 2 2006.196.08:31:30.38#ibcon#wrote, iclass 40, count 2 2006.196.08:31:30.38#ibcon#about to read 3, iclass 40, count 2 2006.196.08:31:30.41#ibcon#read 3, iclass 40, count 2 2006.196.08:31:30.41#ibcon#about to read 4, iclass 40, count 2 2006.196.08:31:30.41#ibcon#read 4, iclass 40, count 2 2006.196.08:31:30.41#ibcon#about to read 5, iclass 40, count 2 2006.196.08:31:30.41#ibcon#read 5, iclass 40, count 2 2006.196.08:31:30.41#ibcon#about to read 6, iclass 40, count 2 2006.196.08:31:30.41#ibcon#read 6, iclass 40, count 2 2006.196.08:31:30.41#ibcon#end of sib2, iclass 40, count 2 2006.196.08:31:30.41#ibcon#*after write, iclass 40, count 2 2006.196.08:31:30.41#ibcon#*before return 0, iclass 40, count 2 2006.196.08:31:30.41#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.196.08:31:30.41#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.196.08:31:30.41#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.196.08:31:30.41#ibcon#ireg 7 cls_cnt 0 2006.196.08:31:30.41#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.196.08:31:30.53#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.196.08:31:30.53#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.196.08:31:30.53#ibcon#enter wrdev, iclass 40, count 0 2006.196.08:31:30.53#ibcon#first serial, iclass 40, count 0 2006.196.08:31:30.53#ibcon#enter sib2, iclass 40, count 0 2006.196.08:31:30.53#ibcon#flushed, iclass 40, count 0 2006.196.08:31:30.53#ibcon#about to write, iclass 40, count 0 2006.196.08:31:30.53#ibcon#wrote, iclass 40, count 0 2006.196.08:31:30.53#ibcon#about to read 3, iclass 40, count 0 2006.196.08:31:30.55#ibcon#read 3, iclass 40, count 0 2006.196.08:31:30.55#ibcon#about to read 4, iclass 40, count 0 2006.196.08:31:30.55#ibcon#read 4, iclass 40, count 0 2006.196.08:31:30.55#ibcon#about to read 5, iclass 40, count 0 2006.196.08:31:30.55#ibcon#read 5, iclass 40, count 0 2006.196.08:31:30.55#ibcon#about to read 6, iclass 40, count 0 2006.196.08:31:30.55#ibcon#read 6, iclass 40, count 0 2006.196.08:31:30.55#ibcon#end of sib2, iclass 40, count 0 2006.196.08:31:30.55#ibcon#*mode == 0, iclass 40, count 0 2006.196.08:31:30.55#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.196.08:31:30.55#ibcon#[25=USB\r\n] 2006.196.08:31:30.55#ibcon#*before write, iclass 40, count 0 2006.196.08:31:30.55#ibcon#enter sib2, iclass 40, count 0 2006.196.08:31:30.55#ibcon#flushed, iclass 40, count 0 2006.196.08:31:30.55#ibcon#about to write, iclass 40, count 0 2006.196.08:31:30.55#ibcon#wrote, iclass 40, count 0 2006.196.08:31:30.55#ibcon#about to read 3, iclass 40, count 0 2006.196.08:31:30.58#ibcon#read 3, iclass 40, count 0 2006.196.08:31:30.58#ibcon#about to read 4, iclass 40, count 0 2006.196.08:31:30.58#ibcon#read 4, iclass 40, count 0 2006.196.08:31:30.58#ibcon#about to read 5, iclass 40, count 0 2006.196.08:31:30.58#ibcon#read 5, iclass 40, count 0 2006.196.08:31:30.58#ibcon#about to read 6, iclass 40, count 0 2006.196.08:31:30.58#ibcon#read 6, iclass 40, count 0 2006.196.08:31:30.58#ibcon#end of sib2, iclass 40, count 0 2006.196.08:31:30.58#ibcon#*after write, iclass 40, count 0 2006.196.08:31:30.58#ibcon#*before return 0, iclass 40, count 0 2006.196.08:31:30.58#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.196.08:31:30.58#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.196.08:31:30.58#ibcon#about to clear, iclass 40 cls_cnt 0 2006.196.08:31:30.58#ibcon#cleared, iclass 40 cls_cnt 0 2006.196.08:31:30.58$vc4f8/vblo=1,632.99 2006.196.08:31:30.58#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.196.08:31:30.58#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.196.08:31:30.58#ibcon#ireg 17 cls_cnt 0 2006.196.08:31:30.58#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.196.08:31:30.58#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.196.08:31:30.58#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.196.08:31:30.58#ibcon#enter wrdev, iclass 4, count 0 2006.196.08:31:30.58#ibcon#first serial, iclass 4, count 0 2006.196.08:31:30.58#ibcon#enter sib2, iclass 4, count 0 2006.196.08:31:30.58#ibcon#flushed, iclass 4, count 0 2006.196.08:31:30.58#ibcon#about to write, iclass 4, count 0 2006.196.08:31:30.58#ibcon#wrote, iclass 4, count 0 2006.196.08:31:30.58#ibcon#about to read 3, iclass 4, count 0 2006.196.08:31:30.60#ibcon#read 3, iclass 4, count 0 2006.196.08:31:30.60#ibcon#about to read 4, iclass 4, count 0 2006.196.08:31:30.60#ibcon#read 4, iclass 4, count 0 2006.196.08:31:30.60#ibcon#about to read 5, iclass 4, count 0 2006.196.08:31:30.60#ibcon#read 5, iclass 4, count 0 2006.196.08:31:30.60#ibcon#about to read 6, iclass 4, count 0 2006.196.08:31:30.60#ibcon#read 6, iclass 4, count 0 2006.196.08:31:30.60#ibcon#end of sib2, iclass 4, count 0 2006.196.08:31:30.60#ibcon#*mode == 0, iclass 4, count 0 2006.196.08:31:30.60#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.196.08:31:30.60#ibcon#[28=FRQ=01,632.99\r\n] 2006.196.08:31:30.60#ibcon#*before write, iclass 4, count 0 2006.196.08:31:30.60#ibcon#enter sib2, iclass 4, count 0 2006.196.08:31:30.60#ibcon#flushed, iclass 4, count 0 2006.196.08:31:30.60#ibcon#about to write, iclass 4, count 0 2006.196.08:31:30.60#ibcon#wrote, iclass 4, count 0 2006.196.08:31:30.60#ibcon#about to read 3, iclass 4, count 0 2006.196.08:31:30.64#ibcon#read 3, iclass 4, count 0 2006.196.08:31:30.64#ibcon#about to read 4, iclass 4, count 0 2006.196.08:31:30.64#ibcon#read 4, iclass 4, count 0 2006.196.08:31:30.64#ibcon#about to read 5, iclass 4, count 0 2006.196.08:31:30.64#ibcon#read 5, iclass 4, count 0 2006.196.08:31:30.64#ibcon#about to read 6, iclass 4, count 0 2006.196.08:31:30.64#ibcon#read 6, iclass 4, count 0 2006.196.08:31:30.64#ibcon#end of sib2, iclass 4, count 0 2006.196.08:31:30.64#ibcon#*after write, iclass 4, count 0 2006.196.08:31:30.64#ibcon#*before return 0, iclass 4, count 0 2006.196.08:31:30.64#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.196.08:31:30.64#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.196.08:31:30.64#ibcon#about to clear, iclass 4 cls_cnt 0 2006.196.08:31:30.64#ibcon#cleared, iclass 4 cls_cnt 0 2006.196.08:31:30.64$vc4f8/vb=1,4 2006.196.08:31:30.64#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.196.08:31:30.64#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.196.08:31:30.64#ibcon#ireg 11 cls_cnt 2 2006.196.08:31:30.64#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.196.08:31:30.64#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.196.08:31:30.64#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.196.08:31:30.64#ibcon#enter wrdev, iclass 6, count 2 2006.196.08:31:30.64#ibcon#first serial, iclass 6, count 2 2006.196.08:31:30.64#ibcon#enter sib2, iclass 6, count 2 2006.196.08:31:30.64#ibcon#flushed, iclass 6, count 2 2006.196.08:31:30.64#ibcon#about to write, iclass 6, count 2 2006.196.08:31:30.64#ibcon#wrote, iclass 6, count 2 2006.196.08:31:30.64#ibcon#about to read 3, iclass 6, count 2 2006.196.08:31:30.66#ibcon#read 3, iclass 6, count 2 2006.196.08:31:30.66#ibcon#about to read 4, iclass 6, count 2 2006.196.08:31:30.66#ibcon#read 4, iclass 6, count 2 2006.196.08:31:30.66#ibcon#about to read 5, iclass 6, count 2 2006.196.08:31:30.66#ibcon#read 5, iclass 6, count 2 2006.196.08:31:30.66#ibcon#about to read 6, iclass 6, count 2 2006.196.08:31:30.66#ibcon#read 6, iclass 6, count 2 2006.196.08:31:30.66#ibcon#end of sib2, iclass 6, count 2 2006.196.08:31:30.66#ibcon#*mode == 0, iclass 6, count 2 2006.196.08:31:30.66#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.196.08:31:30.66#ibcon#[27=AT01-04\r\n] 2006.196.08:31:30.66#ibcon#*before write, iclass 6, count 2 2006.196.08:31:30.66#ibcon#enter sib2, iclass 6, count 2 2006.196.08:31:30.66#ibcon#flushed, iclass 6, count 2 2006.196.08:31:30.66#ibcon#about to write, iclass 6, count 2 2006.196.08:31:30.66#ibcon#wrote, iclass 6, count 2 2006.196.08:31:30.66#ibcon#about to read 3, iclass 6, count 2 2006.196.08:31:30.69#ibcon#read 3, iclass 6, count 2 2006.196.08:31:30.69#ibcon#about to read 4, iclass 6, count 2 2006.196.08:31:30.69#ibcon#read 4, iclass 6, count 2 2006.196.08:31:30.69#ibcon#about to read 5, iclass 6, count 2 2006.196.08:31:30.69#ibcon#read 5, iclass 6, count 2 2006.196.08:31:30.69#ibcon#about to read 6, iclass 6, count 2 2006.196.08:31:30.69#ibcon#read 6, iclass 6, count 2 2006.196.08:31:30.69#ibcon#end of sib2, iclass 6, count 2 2006.196.08:31:30.69#ibcon#*after write, iclass 6, count 2 2006.196.08:31:30.69#ibcon#*before return 0, iclass 6, count 2 2006.196.08:31:30.69#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.196.08:31:30.69#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.196.08:31:30.69#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.196.08:31:30.69#ibcon#ireg 7 cls_cnt 0 2006.196.08:31:30.69#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.196.08:31:30.81#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.196.08:31:30.81#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.196.08:31:30.81#ibcon#enter wrdev, iclass 6, count 0 2006.196.08:31:30.81#ibcon#first serial, iclass 6, count 0 2006.196.08:31:30.81#ibcon#enter sib2, iclass 6, count 0 2006.196.08:31:30.81#ibcon#flushed, iclass 6, count 0 2006.196.08:31:30.81#ibcon#about to write, iclass 6, count 0 2006.196.08:31:30.81#ibcon#wrote, iclass 6, count 0 2006.196.08:31:30.81#ibcon#about to read 3, iclass 6, count 0 2006.196.08:31:30.83#ibcon#read 3, iclass 6, count 0 2006.196.08:31:30.83#ibcon#about to read 4, iclass 6, count 0 2006.196.08:31:30.83#ibcon#read 4, iclass 6, count 0 2006.196.08:31:30.83#ibcon#about to read 5, iclass 6, count 0 2006.196.08:31:30.83#ibcon#read 5, iclass 6, count 0 2006.196.08:31:30.83#ibcon#about to read 6, iclass 6, count 0 2006.196.08:31:30.83#ibcon#read 6, iclass 6, count 0 2006.196.08:31:30.83#ibcon#end of sib2, iclass 6, count 0 2006.196.08:31:30.83#ibcon#*mode == 0, iclass 6, count 0 2006.196.08:31:30.83#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.196.08:31:30.83#ibcon#[27=USB\r\n] 2006.196.08:31:30.83#ibcon#*before write, iclass 6, count 0 2006.196.08:31:30.83#ibcon#enter sib2, iclass 6, count 0 2006.196.08:31:30.83#ibcon#flushed, iclass 6, count 0 2006.196.08:31:30.83#ibcon#about to write, iclass 6, count 0 2006.196.08:31:30.83#ibcon#wrote, iclass 6, count 0 2006.196.08:31:30.83#ibcon#about to read 3, iclass 6, count 0 2006.196.08:31:30.86#ibcon#read 3, iclass 6, count 0 2006.196.08:31:30.86#ibcon#about to read 4, iclass 6, count 0 2006.196.08:31:30.86#ibcon#read 4, iclass 6, count 0 2006.196.08:31:30.86#ibcon#about to read 5, iclass 6, count 0 2006.196.08:31:30.86#ibcon#read 5, iclass 6, count 0 2006.196.08:31:30.86#ibcon#about to read 6, iclass 6, count 0 2006.196.08:31:30.86#ibcon#read 6, iclass 6, count 0 2006.196.08:31:30.86#ibcon#end of sib2, iclass 6, count 0 2006.196.08:31:30.86#ibcon#*after write, iclass 6, count 0 2006.196.08:31:30.86#ibcon#*before return 0, iclass 6, count 0 2006.196.08:31:30.86#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.196.08:31:30.86#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.196.08:31:30.86#ibcon#about to clear, iclass 6 cls_cnt 0 2006.196.08:31:30.86#ibcon#cleared, iclass 6 cls_cnt 0 2006.196.08:31:30.86$vc4f8/vblo=2,640.99 2006.196.08:31:30.86#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.196.08:31:30.86#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.196.08:31:30.86#ibcon#ireg 17 cls_cnt 0 2006.196.08:31:30.86#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.196.08:31:30.86#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.196.08:31:30.86#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.196.08:31:30.86#ibcon#enter wrdev, iclass 10, count 0 2006.196.08:31:30.86#ibcon#first serial, iclass 10, count 0 2006.196.08:31:30.86#ibcon#enter sib2, iclass 10, count 0 2006.196.08:31:30.86#ibcon#flushed, iclass 10, count 0 2006.196.08:31:30.86#ibcon#about to write, iclass 10, count 0 2006.196.08:31:30.86#ibcon#wrote, iclass 10, count 0 2006.196.08:31:30.86#ibcon#about to read 3, iclass 10, count 0 2006.196.08:31:30.88#ibcon#read 3, iclass 10, count 0 2006.196.08:31:30.88#ibcon#about to read 4, iclass 10, count 0 2006.196.08:31:30.88#ibcon#read 4, iclass 10, count 0 2006.196.08:31:30.88#ibcon#about to read 5, iclass 10, count 0 2006.196.08:31:30.88#ibcon#read 5, iclass 10, count 0 2006.196.08:31:30.88#ibcon#about to read 6, iclass 10, count 0 2006.196.08:31:30.88#ibcon#read 6, iclass 10, count 0 2006.196.08:31:30.88#ibcon#end of sib2, iclass 10, count 0 2006.196.08:31:30.88#ibcon#*mode == 0, iclass 10, count 0 2006.196.08:31:30.88#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.196.08:31:30.88#ibcon#[28=FRQ=02,640.99\r\n] 2006.196.08:31:30.88#ibcon#*before write, iclass 10, count 0 2006.196.08:31:30.88#ibcon#enter sib2, iclass 10, count 0 2006.196.08:31:30.88#ibcon#flushed, iclass 10, count 0 2006.196.08:31:30.88#ibcon#about to write, iclass 10, count 0 2006.196.08:31:30.88#ibcon#wrote, iclass 10, count 0 2006.196.08:31:30.88#ibcon#about to read 3, iclass 10, count 0 2006.196.08:31:30.92#ibcon#read 3, iclass 10, count 0 2006.196.08:31:30.92#ibcon#about to read 4, iclass 10, count 0 2006.196.08:31:30.92#ibcon#read 4, iclass 10, count 0 2006.196.08:31:30.92#ibcon#about to read 5, iclass 10, count 0 2006.196.08:31:30.92#ibcon#read 5, iclass 10, count 0 2006.196.08:31:30.92#ibcon#about to read 6, iclass 10, count 0 2006.196.08:31:30.92#ibcon#read 6, iclass 10, count 0 2006.196.08:31:30.92#ibcon#end of sib2, iclass 10, count 0 2006.196.08:31:30.92#ibcon#*after write, iclass 10, count 0 2006.196.08:31:30.92#ibcon#*before return 0, iclass 10, count 0 2006.196.08:31:30.92#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.196.08:31:30.92#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.196.08:31:30.92#ibcon#about to clear, iclass 10 cls_cnt 0 2006.196.08:31:30.92#ibcon#cleared, iclass 10 cls_cnt 0 2006.196.08:31:30.92$vc4f8/vb=2,4 2006.196.08:31:30.92#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.196.08:31:30.92#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.196.08:31:30.92#ibcon#ireg 11 cls_cnt 2 2006.196.08:31:30.92#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.196.08:31:30.98#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.196.08:31:30.98#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.196.08:31:30.98#ibcon#enter wrdev, iclass 12, count 2 2006.196.08:31:30.98#ibcon#first serial, iclass 12, count 2 2006.196.08:31:30.98#ibcon#enter sib2, iclass 12, count 2 2006.196.08:31:30.98#ibcon#flushed, iclass 12, count 2 2006.196.08:31:30.98#ibcon#about to write, iclass 12, count 2 2006.196.08:31:30.98#ibcon#wrote, iclass 12, count 2 2006.196.08:31:30.98#ibcon#about to read 3, iclass 12, count 2 2006.196.08:31:31.00#ibcon#read 3, iclass 12, count 2 2006.196.08:31:31.00#ibcon#about to read 4, iclass 12, count 2 2006.196.08:31:31.00#ibcon#read 4, iclass 12, count 2 2006.196.08:31:31.00#ibcon#about to read 5, iclass 12, count 2 2006.196.08:31:31.00#ibcon#read 5, iclass 12, count 2 2006.196.08:31:31.00#ibcon#about to read 6, iclass 12, count 2 2006.196.08:31:31.00#ibcon#read 6, iclass 12, count 2 2006.196.08:31:31.00#ibcon#end of sib2, iclass 12, count 2 2006.196.08:31:31.00#ibcon#*mode == 0, iclass 12, count 2 2006.196.08:31:31.00#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.196.08:31:31.00#ibcon#[27=AT02-04\r\n] 2006.196.08:31:31.00#ibcon#*before write, iclass 12, count 2 2006.196.08:31:31.00#ibcon#enter sib2, iclass 12, count 2 2006.196.08:31:31.00#ibcon#flushed, iclass 12, count 2 2006.196.08:31:31.00#ibcon#about to write, iclass 12, count 2 2006.196.08:31:31.00#ibcon#wrote, iclass 12, count 2 2006.196.08:31:31.00#ibcon#about to read 3, iclass 12, count 2 2006.196.08:31:31.03#ibcon#read 3, iclass 12, count 2 2006.196.08:31:31.03#ibcon#about to read 4, iclass 12, count 2 2006.196.08:31:31.03#ibcon#read 4, iclass 12, count 2 2006.196.08:31:31.03#ibcon#about to read 5, iclass 12, count 2 2006.196.08:31:31.03#ibcon#read 5, iclass 12, count 2 2006.196.08:31:31.03#ibcon#about to read 6, iclass 12, count 2 2006.196.08:31:31.03#ibcon#read 6, iclass 12, count 2 2006.196.08:31:31.03#ibcon#end of sib2, iclass 12, count 2 2006.196.08:31:31.03#ibcon#*after write, iclass 12, count 2 2006.196.08:31:31.03#ibcon#*before return 0, iclass 12, count 2 2006.196.08:31:31.03#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.196.08:31:31.03#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.196.08:31:31.03#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.196.08:31:31.03#ibcon#ireg 7 cls_cnt 0 2006.196.08:31:31.03#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.196.08:31:31.15#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.196.08:31:31.15#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.196.08:31:31.15#ibcon#enter wrdev, iclass 12, count 0 2006.196.08:31:31.15#ibcon#first serial, iclass 12, count 0 2006.196.08:31:31.15#ibcon#enter sib2, iclass 12, count 0 2006.196.08:31:31.15#ibcon#flushed, iclass 12, count 0 2006.196.08:31:31.15#ibcon#about to write, iclass 12, count 0 2006.196.08:31:31.15#ibcon#wrote, iclass 12, count 0 2006.196.08:31:31.15#ibcon#about to read 3, iclass 12, count 0 2006.196.08:31:31.17#ibcon#read 3, iclass 12, count 0 2006.196.08:31:31.17#ibcon#about to read 4, iclass 12, count 0 2006.196.08:31:31.17#ibcon#read 4, iclass 12, count 0 2006.196.08:31:31.17#ibcon#about to read 5, iclass 12, count 0 2006.196.08:31:31.17#ibcon#read 5, iclass 12, count 0 2006.196.08:31:31.17#ibcon#about to read 6, iclass 12, count 0 2006.196.08:31:31.17#ibcon#read 6, iclass 12, count 0 2006.196.08:31:31.17#ibcon#end of sib2, iclass 12, count 0 2006.196.08:31:31.17#ibcon#*mode == 0, iclass 12, count 0 2006.196.08:31:31.17#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.196.08:31:31.17#ibcon#[27=USB\r\n] 2006.196.08:31:31.17#ibcon#*before write, iclass 12, count 0 2006.196.08:31:31.17#ibcon#enter sib2, iclass 12, count 0 2006.196.08:31:31.17#ibcon#flushed, iclass 12, count 0 2006.196.08:31:31.17#ibcon#about to write, iclass 12, count 0 2006.196.08:31:31.17#ibcon#wrote, iclass 12, count 0 2006.196.08:31:31.17#ibcon#about to read 3, iclass 12, count 0 2006.196.08:31:31.20#ibcon#read 3, iclass 12, count 0 2006.196.08:31:31.20#ibcon#about to read 4, iclass 12, count 0 2006.196.08:31:31.20#ibcon#read 4, iclass 12, count 0 2006.196.08:31:31.20#ibcon#about to read 5, iclass 12, count 0 2006.196.08:31:31.20#ibcon#read 5, iclass 12, count 0 2006.196.08:31:31.20#ibcon#about to read 6, iclass 12, count 0 2006.196.08:31:31.20#ibcon#read 6, iclass 12, count 0 2006.196.08:31:31.20#ibcon#end of sib2, iclass 12, count 0 2006.196.08:31:31.20#ibcon#*after write, iclass 12, count 0 2006.196.08:31:31.20#ibcon#*before return 0, iclass 12, count 0 2006.196.08:31:31.20#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.196.08:31:31.20#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.196.08:31:31.20#ibcon#about to clear, iclass 12 cls_cnt 0 2006.196.08:31:31.20#ibcon#cleared, iclass 12 cls_cnt 0 2006.196.08:31:31.20$vc4f8/vblo=3,656.99 2006.196.08:31:31.20#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.196.08:31:31.20#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.196.08:31:31.20#ibcon#ireg 17 cls_cnt 0 2006.196.08:31:31.20#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.196.08:31:31.20#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.196.08:31:31.20#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.196.08:31:31.20#ibcon#enter wrdev, iclass 14, count 0 2006.196.08:31:31.20#ibcon#first serial, iclass 14, count 0 2006.196.08:31:31.20#ibcon#enter sib2, iclass 14, count 0 2006.196.08:31:31.20#ibcon#flushed, iclass 14, count 0 2006.196.08:31:31.20#ibcon#about to write, iclass 14, count 0 2006.196.08:31:31.20#ibcon#wrote, iclass 14, count 0 2006.196.08:31:31.20#ibcon#about to read 3, iclass 14, count 0 2006.196.08:31:31.22#ibcon#read 3, iclass 14, count 0 2006.196.08:31:31.22#ibcon#about to read 4, iclass 14, count 0 2006.196.08:31:31.22#ibcon#read 4, iclass 14, count 0 2006.196.08:31:31.22#ibcon#about to read 5, iclass 14, count 0 2006.196.08:31:31.22#ibcon#read 5, iclass 14, count 0 2006.196.08:31:31.22#ibcon#about to read 6, iclass 14, count 0 2006.196.08:31:31.22#ibcon#read 6, iclass 14, count 0 2006.196.08:31:31.22#ibcon#end of sib2, iclass 14, count 0 2006.196.08:31:31.22#ibcon#*mode == 0, iclass 14, count 0 2006.196.08:31:31.22#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.196.08:31:31.22#ibcon#[28=FRQ=03,656.99\r\n] 2006.196.08:31:31.22#ibcon#*before write, iclass 14, count 0 2006.196.08:31:31.22#ibcon#enter sib2, iclass 14, count 0 2006.196.08:31:31.22#ibcon#flushed, iclass 14, count 0 2006.196.08:31:31.22#ibcon#about to write, iclass 14, count 0 2006.196.08:31:31.22#ibcon#wrote, iclass 14, count 0 2006.196.08:31:31.22#ibcon#about to read 3, iclass 14, count 0 2006.196.08:31:31.26#ibcon#read 3, iclass 14, count 0 2006.196.08:31:31.26#ibcon#about to read 4, iclass 14, count 0 2006.196.08:31:31.26#ibcon#read 4, iclass 14, count 0 2006.196.08:31:31.26#ibcon#about to read 5, iclass 14, count 0 2006.196.08:31:31.26#ibcon#read 5, iclass 14, count 0 2006.196.08:31:31.26#ibcon#about to read 6, iclass 14, count 0 2006.196.08:31:31.26#ibcon#read 6, iclass 14, count 0 2006.196.08:31:31.26#ibcon#end of sib2, iclass 14, count 0 2006.196.08:31:31.26#ibcon#*after write, iclass 14, count 0 2006.196.08:31:31.26#ibcon#*before return 0, iclass 14, count 0 2006.196.08:31:31.26#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.196.08:31:31.26#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.196.08:31:31.26#ibcon#about to clear, iclass 14 cls_cnt 0 2006.196.08:31:31.26#ibcon#cleared, iclass 14 cls_cnt 0 2006.196.08:31:31.26$vc4f8/vb=3,4 2006.196.08:31:31.26#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.196.08:31:31.26#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.196.08:31:31.26#ibcon#ireg 11 cls_cnt 2 2006.196.08:31:31.26#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.196.08:31:31.32#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.196.08:31:31.32#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.196.08:31:31.32#ibcon#enter wrdev, iclass 16, count 2 2006.196.08:31:31.32#ibcon#first serial, iclass 16, count 2 2006.196.08:31:31.32#ibcon#enter sib2, iclass 16, count 2 2006.196.08:31:31.32#ibcon#flushed, iclass 16, count 2 2006.196.08:31:31.32#ibcon#about to write, iclass 16, count 2 2006.196.08:31:31.32#ibcon#wrote, iclass 16, count 2 2006.196.08:31:31.32#ibcon#about to read 3, iclass 16, count 2 2006.196.08:31:31.34#ibcon#read 3, iclass 16, count 2 2006.196.08:31:31.34#ibcon#about to read 4, iclass 16, count 2 2006.196.08:31:31.34#ibcon#read 4, iclass 16, count 2 2006.196.08:31:31.34#ibcon#about to read 5, iclass 16, count 2 2006.196.08:31:31.34#ibcon#read 5, iclass 16, count 2 2006.196.08:31:31.34#ibcon#about to read 6, iclass 16, count 2 2006.196.08:31:31.34#ibcon#read 6, iclass 16, count 2 2006.196.08:31:31.34#ibcon#end of sib2, iclass 16, count 2 2006.196.08:31:31.34#ibcon#*mode == 0, iclass 16, count 2 2006.196.08:31:31.34#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.196.08:31:31.34#ibcon#[27=AT03-04\r\n] 2006.196.08:31:31.34#ibcon#*before write, iclass 16, count 2 2006.196.08:31:31.34#ibcon#enter sib2, iclass 16, count 2 2006.196.08:31:31.34#ibcon#flushed, iclass 16, count 2 2006.196.08:31:31.34#ibcon#about to write, iclass 16, count 2 2006.196.08:31:31.34#ibcon#wrote, iclass 16, count 2 2006.196.08:31:31.34#ibcon#about to read 3, iclass 16, count 2 2006.196.08:31:31.37#ibcon#read 3, iclass 16, count 2 2006.196.08:31:31.37#ibcon#about to read 4, iclass 16, count 2 2006.196.08:31:31.37#ibcon#read 4, iclass 16, count 2 2006.196.08:31:31.37#ibcon#about to read 5, iclass 16, count 2 2006.196.08:31:31.37#ibcon#read 5, iclass 16, count 2 2006.196.08:31:31.37#ibcon#about to read 6, iclass 16, count 2 2006.196.08:31:31.37#ibcon#read 6, iclass 16, count 2 2006.196.08:31:31.37#ibcon#end of sib2, iclass 16, count 2 2006.196.08:31:31.37#ibcon#*after write, iclass 16, count 2 2006.196.08:31:31.37#ibcon#*before return 0, iclass 16, count 2 2006.196.08:31:31.37#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.196.08:31:31.37#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.196.08:31:31.37#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.196.08:31:31.37#ibcon#ireg 7 cls_cnt 0 2006.196.08:31:31.37#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.196.08:31:31.49#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.196.08:31:31.49#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.196.08:31:31.49#ibcon#enter wrdev, iclass 16, count 0 2006.196.08:31:31.49#ibcon#first serial, iclass 16, count 0 2006.196.08:31:31.49#ibcon#enter sib2, iclass 16, count 0 2006.196.08:31:31.49#ibcon#flushed, iclass 16, count 0 2006.196.08:31:31.49#ibcon#about to write, iclass 16, count 0 2006.196.08:31:31.49#ibcon#wrote, iclass 16, count 0 2006.196.08:31:31.49#ibcon#about to read 3, iclass 16, count 0 2006.196.08:31:31.51#ibcon#read 3, iclass 16, count 0 2006.196.08:31:31.51#ibcon#about to read 4, iclass 16, count 0 2006.196.08:31:31.51#ibcon#read 4, iclass 16, count 0 2006.196.08:31:31.51#ibcon#about to read 5, iclass 16, count 0 2006.196.08:31:31.51#ibcon#read 5, iclass 16, count 0 2006.196.08:31:31.51#ibcon#about to read 6, iclass 16, count 0 2006.196.08:31:31.51#ibcon#read 6, iclass 16, count 0 2006.196.08:31:31.51#ibcon#end of sib2, iclass 16, count 0 2006.196.08:31:31.51#ibcon#*mode == 0, iclass 16, count 0 2006.196.08:31:31.51#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.196.08:31:31.51#ibcon#[27=USB\r\n] 2006.196.08:31:31.51#ibcon#*before write, iclass 16, count 0 2006.196.08:31:31.51#ibcon#enter sib2, iclass 16, count 0 2006.196.08:31:31.51#ibcon#flushed, iclass 16, count 0 2006.196.08:31:31.51#ibcon#about to write, iclass 16, count 0 2006.196.08:31:31.51#ibcon#wrote, iclass 16, count 0 2006.196.08:31:31.51#ibcon#about to read 3, iclass 16, count 0 2006.196.08:31:31.54#ibcon#read 3, iclass 16, count 0 2006.196.08:31:31.54#ibcon#about to read 4, iclass 16, count 0 2006.196.08:31:31.54#ibcon#read 4, iclass 16, count 0 2006.196.08:31:31.54#ibcon#about to read 5, iclass 16, count 0 2006.196.08:31:31.54#ibcon#read 5, iclass 16, count 0 2006.196.08:31:31.54#ibcon#about to read 6, iclass 16, count 0 2006.196.08:31:31.54#ibcon#read 6, iclass 16, count 0 2006.196.08:31:31.54#ibcon#end of sib2, iclass 16, count 0 2006.196.08:31:31.54#ibcon#*after write, iclass 16, count 0 2006.196.08:31:31.54#ibcon#*before return 0, iclass 16, count 0 2006.196.08:31:31.54#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.196.08:31:31.54#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.196.08:31:31.54#ibcon#about to clear, iclass 16 cls_cnt 0 2006.196.08:31:31.54#ibcon#cleared, iclass 16 cls_cnt 0 2006.196.08:31:31.54$vc4f8/vblo=4,712.99 2006.196.08:31:31.54#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.196.08:31:31.54#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.196.08:31:31.54#ibcon#ireg 17 cls_cnt 0 2006.196.08:31:31.54#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.196.08:31:31.54#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.196.08:31:31.54#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.196.08:31:31.54#ibcon#enter wrdev, iclass 18, count 0 2006.196.08:31:31.54#ibcon#first serial, iclass 18, count 0 2006.196.08:31:31.54#ibcon#enter sib2, iclass 18, count 0 2006.196.08:31:31.54#ibcon#flushed, iclass 18, count 0 2006.196.08:31:31.54#ibcon#about to write, iclass 18, count 0 2006.196.08:31:31.54#ibcon#wrote, iclass 18, count 0 2006.196.08:31:31.54#ibcon#about to read 3, iclass 18, count 0 2006.196.08:31:31.56#ibcon#read 3, iclass 18, count 0 2006.196.08:31:31.56#ibcon#about to read 4, iclass 18, count 0 2006.196.08:31:31.56#ibcon#read 4, iclass 18, count 0 2006.196.08:31:31.56#ibcon#about to read 5, iclass 18, count 0 2006.196.08:31:31.56#ibcon#read 5, iclass 18, count 0 2006.196.08:31:31.56#ibcon#about to read 6, iclass 18, count 0 2006.196.08:31:31.56#ibcon#read 6, iclass 18, count 0 2006.196.08:31:31.56#ibcon#end of sib2, iclass 18, count 0 2006.196.08:31:31.56#ibcon#*mode == 0, iclass 18, count 0 2006.196.08:31:31.56#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.196.08:31:31.56#ibcon#[28=FRQ=04,712.99\r\n] 2006.196.08:31:31.56#ibcon#*before write, iclass 18, count 0 2006.196.08:31:31.56#ibcon#enter sib2, iclass 18, count 0 2006.196.08:31:31.56#ibcon#flushed, iclass 18, count 0 2006.196.08:31:31.56#ibcon#about to write, iclass 18, count 0 2006.196.08:31:31.56#ibcon#wrote, iclass 18, count 0 2006.196.08:31:31.56#ibcon#about to read 3, iclass 18, count 0 2006.196.08:31:31.60#ibcon#read 3, iclass 18, count 0 2006.196.08:31:31.60#ibcon#about to read 4, iclass 18, count 0 2006.196.08:31:31.60#ibcon#read 4, iclass 18, count 0 2006.196.08:31:31.60#ibcon#about to read 5, iclass 18, count 0 2006.196.08:31:31.60#ibcon#read 5, iclass 18, count 0 2006.196.08:31:31.60#ibcon#about to read 6, iclass 18, count 0 2006.196.08:31:31.60#ibcon#read 6, iclass 18, count 0 2006.196.08:31:31.60#ibcon#end of sib2, iclass 18, count 0 2006.196.08:31:31.60#ibcon#*after write, iclass 18, count 0 2006.196.08:31:31.60#ibcon#*before return 0, iclass 18, count 0 2006.196.08:31:31.60#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.196.08:31:31.60#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.196.08:31:31.60#ibcon#about to clear, iclass 18 cls_cnt 0 2006.196.08:31:31.60#ibcon#cleared, iclass 18 cls_cnt 0 2006.196.08:31:31.60$vc4f8/vb=4,4 2006.196.08:31:31.60#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.196.08:31:31.60#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.196.08:31:31.60#ibcon#ireg 11 cls_cnt 2 2006.196.08:31:31.60#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.196.08:31:31.66#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.196.08:31:31.66#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.196.08:31:31.66#ibcon#enter wrdev, iclass 20, count 2 2006.196.08:31:31.66#ibcon#first serial, iclass 20, count 2 2006.196.08:31:31.66#ibcon#enter sib2, iclass 20, count 2 2006.196.08:31:31.66#ibcon#flushed, iclass 20, count 2 2006.196.08:31:31.66#ibcon#about to write, iclass 20, count 2 2006.196.08:31:31.66#ibcon#wrote, iclass 20, count 2 2006.196.08:31:31.66#ibcon#about to read 3, iclass 20, count 2 2006.196.08:31:31.68#ibcon#read 3, iclass 20, count 2 2006.196.08:31:31.68#ibcon#about to read 4, iclass 20, count 2 2006.196.08:31:31.68#ibcon#read 4, iclass 20, count 2 2006.196.08:31:31.68#ibcon#about to read 5, iclass 20, count 2 2006.196.08:31:31.68#ibcon#read 5, iclass 20, count 2 2006.196.08:31:31.68#ibcon#about to read 6, iclass 20, count 2 2006.196.08:31:31.68#ibcon#read 6, iclass 20, count 2 2006.196.08:31:31.68#ibcon#end of sib2, iclass 20, count 2 2006.196.08:31:31.68#ibcon#*mode == 0, iclass 20, count 2 2006.196.08:31:31.68#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.196.08:31:31.68#ibcon#[27=AT04-04\r\n] 2006.196.08:31:31.68#ibcon#*before write, iclass 20, count 2 2006.196.08:31:31.68#ibcon#enter sib2, iclass 20, count 2 2006.196.08:31:31.68#ibcon#flushed, iclass 20, count 2 2006.196.08:31:31.68#ibcon#about to write, iclass 20, count 2 2006.196.08:31:31.68#ibcon#wrote, iclass 20, count 2 2006.196.08:31:31.68#ibcon#about to read 3, iclass 20, count 2 2006.196.08:31:31.71#ibcon#read 3, iclass 20, count 2 2006.196.08:31:31.71#ibcon#about to read 4, iclass 20, count 2 2006.196.08:31:31.71#ibcon#read 4, iclass 20, count 2 2006.196.08:31:31.71#ibcon#about to read 5, iclass 20, count 2 2006.196.08:31:31.71#ibcon#read 5, iclass 20, count 2 2006.196.08:31:31.71#ibcon#about to read 6, iclass 20, count 2 2006.196.08:31:31.71#ibcon#read 6, iclass 20, count 2 2006.196.08:31:31.71#ibcon#end of sib2, iclass 20, count 2 2006.196.08:31:31.71#ibcon#*after write, iclass 20, count 2 2006.196.08:31:31.71#ibcon#*before return 0, iclass 20, count 2 2006.196.08:31:31.71#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.196.08:31:31.71#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.196.08:31:31.71#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.196.08:31:31.71#ibcon#ireg 7 cls_cnt 0 2006.196.08:31:31.71#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.196.08:31:31.83#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.196.08:31:31.83#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.196.08:31:31.83#ibcon#enter wrdev, iclass 20, count 0 2006.196.08:31:31.83#ibcon#first serial, iclass 20, count 0 2006.196.08:31:31.83#ibcon#enter sib2, iclass 20, count 0 2006.196.08:31:31.83#ibcon#flushed, iclass 20, count 0 2006.196.08:31:31.83#ibcon#about to write, iclass 20, count 0 2006.196.08:31:31.83#ibcon#wrote, iclass 20, count 0 2006.196.08:31:31.83#ibcon#about to read 3, iclass 20, count 0 2006.196.08:31:31.85#ibcon#read 3, iclass 20, count 0 2006.196.08:31:31.85#ibcon#about to read 4, iclass 20, count 0 2006.196.08:31:31.85#ibcon#read 4, iclass 20, count 0 2006.196.08:31:31.85#ibcon#about to read 5, iclass 20, count 0 2006.196.08:31:31.85#ibcon#read 5, iclass 20, count 0 2006.196.08:31:31.85#ibcon#about to read 6, iclass 20, count 0 2006.196.08:31:31.85#ibcon#read 6, iclass 20, count 0 2006.196.08:31:31.85#ibcon#end of sib2, iclass 20, count 0 2006.196.08:31:31.85#ibcon#*mode == 0, iclass 20, count 0 2006.196.08:31:31.85#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.196.08:31:31.85#ibcon#[27=USB\r\n] 2006.196.08:31:31.85#ibcon#*before write, iclass 20, count 0 2006.196.08:31:31.85#ibcon#enter sib2, iclass 20, count 0 2006.196.08:31:31.85#ibcon#flushed, iclass 20, count 0 2006.196.08:31:31.85#ibcon#about to write, iclass 20, count 0 2006.196.08:31:31.85#ibcon#wrote, iclass 20, count 0 2006.196.08:31:31.85#ibcon#about to read 3, iclass 20, count 0 2006.196.08:31:31.88#ibcon#read 3, iclass 20, count 0 2006.196.08:31:31.88#ibcon#about to read 4, iclass 20, count 0 2006.196.08:31:31.88#ibcon#read 4, iclass 20, count 0 2006.196.08:31:31.88#ibcon#about to read 5, iclass 20, count 0 2006.196.08:31:31.88#ibcon#read 5, iclass 20, count 0 2006.196.08:31:31.88#ibcon#about to read 6, iclass 20, count 0 2006.196.08:31:31.88#ibcon#read 6, iclass 20, count 0 2006.196.08:31:31.88#ibcon#end of sib2, iclass 20, count 0 2006.196.08:31:31.88#ibcon#*after write, iclass 20, count 0 2006.196.08:31:31.88#ibcon#*before return 0, iclass 20, count 0 2006.196.08:31:31.88#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.196.08:31:31.88#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.196.08:31:31.88#ibcon#about to clear, iclass 20 cls_cnt 0 2006.196.08:31:31.88#ibcon#cleared, iclass 20 cls_cnt 0 2006.196.08:31:31.88$vc4f8/vblo=5,744.99 2006.196.08:31:31.88#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.196.08:31:31.88#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.196.08:31:31.88#ibcon#ireg 17 cls_cnt 0 2006.196.08:31:31.88#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.196.08:31:31.88#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.196.08:31:31.88#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.196.08:31:31.88#ibcon#enter wrdev, iclass 22, count 0 2006.196.08:31:31.88#ibcon#first serial, iclass 22, count 0 2006.196.08:31:31.88#ibcon#enter sib2, iclass 22, count 0 2006.196.08:31:31.88#ibcon#flushed, iclass 22, count 0 2006.196.08:31:31.88#ibcon#about to write, iclass 22, count 0 2006.196.08:31:31.88#ibcon#wrote, iclass 22, count 0 2006.196.08:31:31.88#ibcon#about to read 3, iclass 22, count 0 2006.196.08:31:31.90#ibcon#read 3, iclass 22, count 0 2006.196.08:31:31.90#ibcon#about to read 4, iclass 22, count 0 2006.196.08:31:31.90#ibcon#read 4, iclass 22, count 0 2006.196.08:31:31.90#ibcon#about to read 5, iclass 22, count 0 2006.196.08:31:31.90#ibcon#read 5, iclass 22, count 0 2006.196.08:31:31.90#ibcon#about to read 6, iclass 22, count 0 2006.196.08:31:31.90#ibcon#read 6, iclass 22, count 0 2006.196.08:31:31.90#ibcon#end of sib2, iclass 22, count 0 2006.196.08:31:31.90#ibcon#*mode == 0, iclass 22, count 0 2006.196.08:31:31.90#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.196.08:31:31.90#ibcon#[28=FRQ=05,744.99\r\n] 2006.196.08:31:31.90#ibcon#*before write, iclass 22, count 0 2006.196.08:31:31.90#ibcon#enter sib2, iclass 22, count 0 2006.196.08:31:31.90#ibcon#flushed, iclass 22, count 0 2006.196.08:31:31.90#ibcon#about to write, iclass 22, count 0 2006.196.08:31:31.90#ibcon#wrote, iclass 22, count 0 2006.196.08:31:31.90#ibcon#about to read 3, iclass 22, count 0 2006.196.08:31:31.94#ibcon#read 3, iclass 22, count 0 2006.196.08:31:31.94#ibcon#about to read 4, iclass 22, count 0 2006.196.08:31:31.94#ibcon#read 4, iclass 22, count 0 2006.196.08:31:31.94#ibcon#about to read 5, iclass 22, count 0 2006.196.08:31:31.94#ibcon#read 5, iclass 22, count 0 2006.196.08:31:31.94#ibcon#about to read 6, iclass 22, count 0 2006.196.08:31:31.94#ibcon#read 6, iclass 22, count 0 2006.196.08:31:31.94#ibcon#end of sib2, iclass 22, count 0 2006.196.08:31:31.94#ibcon#*after write, iclass 22, count 0 2006.196.08:31:31.94#ibcon#*before return 0, iclass 22, count 0 2006.196.08:31:31.94#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.196.08:31:31.94#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.196.08:31:31.94#ibcon#about to clear, iclass 22 cls_cnt 0 2006.196.08:31:31.94#ibcon#cleared, iclass 22 cls_cnt 0 2006.196.08:31:31.94$vc4f8/vb=5,4 2006.196.08:31:31.94#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.196.08:31:31.94#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.196.08:31:31.94#ibcon#ireg 11 cls_cnt 2 2006.196.08:31:31.94#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.196.08:31:32.00#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.196.08:31:32.00#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.196.08:31:32.00#ibcon#enter wrdev, iclass 24, count 2 2006.196.08:31:32.00#ibcon#first serial, iclass 24, count 2 2006.196.08:31:32.00#ibcon#enter sib2, iclass 24, count 2 2006.196.08:31:32.00#ibcon#flushed, iclass 24, count 2 2006.196.08:31:32.00#ibcon#about to write, iclass 24, count 2 2006.196.08:31:32.00#ibcon#wrote, iclass 24, count 2 2006.196.08:31:32.00#ibcon#about to read 3, iclass 24, count 2 2006.196.08:31:32.02#ibcon#read 3, iclass 24, count 2 2006.196.08:31:32.02#ibcon#about to read 4, iclass 24, count 2 2006.196.08:31:32.02#ibcon#read 4, iclass 24, count 2 2006.196.08:31:32.02#ibcon#about to read 5, iclass 24, count 2 2006.196.08:31:32.02#ibcon#read 5, iclass 24, count 2 2006.196.08:31:32.02#ibcon#about to read 6, iclass 24, count 2 2006.196.08:31:32.02#ibcon#read 6, iclass 24, count 2 2006.196.08:31:32.02#ibcon#end of sib2, iclass 24, count 2 2006.196.08:31:32.02#ibcon#*mode == 0, iclass 24, count 2 2006.196.08:31:32.02#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.196.08:31:32.02#ibcon#[27=AT05-04\r\n] 2006.196.08:31:32.02#ibcon#*before write, iclass 24, count 2 2006.196.08:31:32.02#ibcon#enter sib2, iclass 24, count 2 2006.196.08:31:32.02#ibcon#flushed, iclass 24, count 2 2006.196.08:31:32.02#ibcon#about to write, iclass 24, count 2 2006.196.08:31:32.02#ibcon#wrote, iclass 24, count 2 2006.196.08:31:32.02#ibcon#about to read 3, iclass 24, count 2 2006.196.08:31:32.05#ibcon#read 3, iclass 24, count 2 2006.196.08:31:32.05#ibcon#about to read 4, iclass 24, count 2 2006.196.08:31:32.05#ibcon#read 4, iclass 24, count 2 2006.196.08:31:32.05#ibcon#about to read 5, iclass 24, count 2 2006.196.08:31:32.05#ibcon#read 5, iclass 24, count 2 2006.196.08:31:32.05#ibcon#about to read 6, iclass 24, count 2 2006.196.08:31:32.05#ibcon#read 6, iclass 24, count 2 2006.196.08:31:32.05#ibcon#end of sib2, iclass 24, count 2 2006.196.08:31:32.05#ibcon#*after write, iclass 24, count 2 2006.196.08:31:32.05#ibcon#*before return 0, iclass 24, count 2 2006.196.08:31:32.05#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.196.08:31:32.05#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.196.08:31:32.05#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.196.08:31:32.05#ibcon#ireg 7 cls_cnt 0 2006.196.08:31:32.05#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.196.08:31:32.17#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.196.08:31:32.17#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.196.08:31:32.17#ibcon#enter wrdev, iclass 24, count 0 2006.196.08:31:32.17#ibcon#first serial, iclass 24, count 0 2006.196.08:31:32.17#ibcon#enter sib2, iclass 24, count 0 2006.196.08:31:32.17#ibcon#flushed, iclass 24, count 0 2006.196.08:31:32.17#ibcon#about to write, iclass 24, count 0 2006.196.08:31:32.17#ibcon#wrote, iclass 24, count 0 2006.196.08:31:32.17#ibcon#about to read 3, iclass 24, count 0 2006.196.08:31:32.19#ibcon#read 3, iclass 24, count 0 2006.196.08:31:32.19#ibcon#about to read 4, iclass 24, count 0 2006.196.08:31:32.19#ibcon#read 4, iclass 24, count 0 2006.196.08:31:32.19#ibcon#about to read 5, iclass 24, count 0 2006.196.08:31:32.19#ibcon#read 5, iclass 24, count 0 2006.196.08:31:32.19#ibcon#about to read 6, iclass 24, count 0 2006.196.08:31:32.19#ibcon#read 6, iclass 24, count 0 2006.196.08:31:32.19#ibcon#end of sib2, iclass 24, count 0 2006.196.08:31:32.19#ibcon#*mode == 0, iclass 24, count 0 2006.196.08:31:32.19#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.196.08:31:32.19#ibcon#[27=USB\r\n] 2006.196.08:31:32.19#ibcon#*before write, iclass 24, count 0 2006.196.08:31:32.19#ibcon#enter sib2, iclass 24, count 0 2006.196.08:31:32.19#ibcon#flushed, iclass 24, count 0 2006.196.08:31:32.19#ibcon#about to write, iclass 24, count 0 2006.196.08:31:32.19#ibcon#wrote, iclass 24, count 0 2006.196.08:31:32.19#ibcon#about to read 3, iclass 24, count 0 2006.196.08:31:32.22#ibcon#read 3, iclass 24, count 0 2006.196.08:31:32.22#ibcon#about to read 4, iclass 24, count 0 2006.196.08:31:32.22#ibcon#read 4, iclass 24, count 0 2006.196.08:31:32.22#ibcon#about to read 5, iclass 24, count 0 2006.196.08:31:32.22#ibcon#read 5, iclass 24, count 0 2006.196.08:31:32.22#ibcon#about to read 6, iclass 24, count 0 2006.196.08:31:32.22#ibcon#read 6, iclass 24, count 0 2006.196.08:31:32.22#ibcon#end of sib2, iclass 24, count 0 2006.196.08:31:32.22#ibcon#*after write, iclass 24, count 0 2006.196.08:31:32.22#ibcon#*before return 0, iclass 24, count 0 2006.196.08:31:32.22#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.196.08:31:32.22#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.196.08:31:32.22#ibcon#about to clear, iclass 24 cls_cnt 0 2006.196.08:31:32.22#ibcon#cleared, iclass 24 cls_cnt 0 2006.196.08:31:32.22$vc4f8/vblo=6,752.99 2006.196.08:31:32.22#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.196.08:31:32.22#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.196.08:31:32.22#ibcon#ireg 17 cls_cnt 0 2006.196.08:31:32.22#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.196.08:31:32.22#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.196.08:31:32.22#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.196.08:31:32.22#ibcon#enter wrdev, iclass 26, count 0 2006.196.08:31:32.22#ibcon#first serial, iclass 26, count 0 2006.196.08:31:32.22#ibcon#enter sib2, iclass 26, count 0 2006.196.08:31:32.22#ibcon#flushed, iclass 26, count 0 2006.196.08:31:32.22#ibcon#about to write, iclass 26, count 0 2006.196.08:31:32.22#ibcon#wrote, iclass 26, count 0 2006.196.08:31:32.22#ibcon#about to read 3, iclass 26, count 0 2006.196.08:31:32.24#ibcon#read 3, iclass 26, count 0 2006.196.08:31:32.24#ibcon#about to read 4, iclass 26, count 0 2006.196.08:31:32.24#ibcon#read 4, iclass 26, count 0 2006.196.08:31:32.24#ibcon#about to read 5, iclass 26, count 0 2006.196.08:31:32.24#ibcon#read 5, iclass 26, count 0 2006.196.08:31:32.24#ibcon#about to read 6, iclass 26, count 0 2006.196.08:31:32.24#ibcon#read 6, iclass 26, count 0 2006.196.08:31:32.24#ibcon#end of sib2, iclass 26, count 0 2006.196.08:31:32.24#ibcon#*mode == 0, iclass 26, count 0 2006.196.08:31:32.24#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.196.08:31:32.24#ibcon#[28=FRQ=06,752.99\r\n] 2006.196.08:31:32.24#ibcon#*before write, iclass 26, count 0 2006.196.08:31:32.24#ibcon#enter sib2, iclass 26, count 0 2006.196.08:31:32.24#ibcon#flushed, iclass 26, count 0 2006.196.08:31:32.24#ibcon#about to write, iclass 26, count 0 2006.196.08:31:32.24#ibcon#wrote, iclass 26, count 0 2006.196.08:31:32.24#ibcon#about to read 3, iclass 26, count 0 2006.196.08:31:32.28#ibcon#read 3, iclass 26, count 0 2006.196.08:31:32.28#ibcon#about to read 4, iclass 26, count 0 2006.196.08:31:32.28#ibcon#read 4, iclass 26, count 0 2006.196.08:31:32.28#ibcon#about to read 5, iclass 26, count 0 2006.196.08:31:32.28#ibcon#read 5, iclass 26, count 0 2006.196.08:31:32.28#ibcon#about to read 6, iclass 26, count 0 2006.196.08:31:32.28#ibcon#read 6, iclass 26, count 0 2006.196.08:31:32.28#ibcon#end of sib2, iclass 26, count 0 2006.196.08:31:32.28#ibcon#*after write, iclass 26, count 0 2006.196.08:31:32.28#ibcon#*before return 0, iclass 26, count 0 2006.196.08:31:32.28#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.196.08:31:32.28#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.196.08:31:32.28#ibcon#about to clear, iclass 26 cls_cnt 0 2006.196.08:31:32.28#ibcon#cleared, iclass 26 cls_cnt 0 2006.196.08:31:32.28$vc4f8/vb=6,4 2006.196.08:31:32.28#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.196.08:31:32.28#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.196.08:31:32.28#ibcon#ireg 11 cls_cnt 2 2006.196.08:31:32.28#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.196.08:31:32.34#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.196.08:31:32.34#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.196.08:31:32.34#ibcon#enter wrdev, iclass 28, count 2 2006.196.08:31:32.34#ibcon#first serial, iclass 28, count 2 2006.196.08:31:32.34#ibcon#enter sib2, iclass 28, count 2 2006.196.08:31:32.34#ibcon#flushed, iclass 28, count 2 2006.196.08:31:32.34#ibcon#about to write, iclass 28, count 2 2006.196.08:31:32.34#ibcon#wrote, iclass 28, count 2 2006.196.08:31:32.34#ibcon#about to read 3, iclass 28, count 2 2006.196.08:31:32.36#ibcon#read 3, iclass 28, count 2 2006.196.08:31:32.36#ibcon#about to read 4, iclass 28, count 2 2006.196.08:31:32.36#ibcon#read 4, iclass 28, count 2 2006.196.08:31:32.36#ibcon#about to read 5, iclass 28, count 2 2006.196.08:31:32.36#ibcon#read 5, iclass 28, count 2 2006.196.08:31:32.36#ibcon#about to read 6, iclass 28, count 2 2006.196.08:31:32.36#ibcon#read 6, iclass 28, count 2 2006.196.08:31:32.36#ibcon#end of sib2, iclass 28, count 2 2006.196.08:31:32.36#ibcon#*mode == 0, iclass 28, count 2 2006.196.08:31:32.36#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.196.08:31:32.36#ibcon#[27=AT06-04\r\n] 2006.196.08:31:32.36#ibcon#*before write, iclass 28, count 2 2006.196.08:31:32.36#ibcon#enter sib2, iclass 28, count 2 2006.196.08:31:32.36#ibcon#flushed, iclass 28, count 2 2006.196.08:31:32.36#ibcon#about to write, iclass 28, count 2 2006.196.08:31:32.36#ibcon#wrote, iclass 28, count 2 2006.196.08:31:32.36#ibcon#about to read 3, iclass 28, count 2 2006.196.08:31:32.39#ibcon#read 3, iclass 28, count 2 2006.196.08:31:32.39#ibcon#about to read 4, iclass 28, count 2 2006.196.08:31:32.39#ibcon#read 4, iclass 28, count 2 2006.196.08:31:32.39#ibcon#about to read 5, iclass 28, count 2 2006.196.08:31:32.39#ibcon#read 5, iclass 28, count 2 2006.196.08:31:32.39#ibcon#about to read 6, iclass 28, count 2 2006.196.08:31:32.39#ibcon#read 6, iclass 28, count 2 2006.196.08:31:32.39#ibcon#end of sib2, iclass 28, count 2 2006.196.08:31:32.39#ibcon#*after write, iclass 28, count 2 2006.196.08:31:32.39#ibcon#*before return 0, iclass 28, count 2 2006.196.08:31:32.39#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.196.08:31:32.39#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.196.08:31:32.39#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.196.08:31:32.39#ibcon#ireg 7 cls_cnt 0 2006.196.08:31:32.39#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.196.08:31:32.51#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.196.08:31:32.51#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.196.08:31:32.51#ibcon#enter wrdev, iclass 28, count 0 2006.196.08:31:32.51#ibcon#first serial, iclass 28, count 0 2006.196.08:31:32.51#ibcon#enter sib2, iclass 28, count 0 2006.196.08:31:32.51#ibcon#flushed, iclass 28, count 0 2006.196.08:31:32.51#ibcon#about to write, iclass 28, count 0 2006.196.08:31:32.51#ibcon#wrote, iclass 28, count 0 2006.196.08:31:32.51#ibcon#about to read 3, iclass 28, count 0 2006.196.08:31:32.53#ibcon#read 3, iclass 28, count 0 2006.196.08:31:32.53#ibcon#about to read 4, iclass 28, count 0 2006.196.08:31:32.53#ibcon#read 4, iclass 28, count 0 2006.196.08:31:32.53#ibcon#about to read 5, iclass 28, count 0 2006.196.08:31:32.53#ibcon#read 5, iclass 28, count 0 2006.196.08:31:32.53#ibcon#about to read 6, iclass 28, count 0 2006.196.08:31:32.53#ibcon#read 6, iclass 28, count 0 2006.196.08:31:32.53#ibcon#end of sib2, iclass 28, count 0 2006.196.08:31:32.53#ibcon#*mode == 0, iclass 28, count 0 2006.196.08:31:32.53#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.196.08:31:32.53#ibcon#[27=USB\r\n] 2006.196.08:31:32.53#ibcon#*before write, iclass 28, count 0 2006.196.08:31:32.53#ibcon#enter sib2, iclass 28, count 0 2006.196.08:31:32.53#ibcon#flushed, iclass 28, count 0 2006.196.08:31:32.53#ibcon#about to write, iclass 28, count 0 2006.196.08:31:32.53#ibcon#wrote, iclass 28, count 0 2006.196.08:31:32.53#ibcon#about to read 3, iclass 28, count 0 2006.196.08:31:32.56#ibcon#read 3, iclass 28, count 0 2006.196.08:31:32.56#ibcon#about to read 4, iclass 28, count 0 2006.196.08:31:32.56#ibcon#read 4, iclass 28, count 0 2006.196.08:31:32.56#ibcon#about to read 5, iclass 28, count 0 2006.196.08:31:32.56#ibcon#read 5, iclass 28, count 0 2006.196.08:31:32.56#ibcon#about to read 6, iclass 28, count 0 2006.196.08:31:32.56#ibcon#read 6, iclass 28, count 0 2006.196.08:31:32.56#ibcon#end of sib2, iclass 28, count 0 2006.196.08:31:32.56#ibcon#*after write, iclass 28, count 0 2006.196.08:31:32.56#ibcon#*before return 0, iclass 28, count 0 2006.196.08:31:32.56#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.196.08:31:32.56#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.196.08:31:32.56#ibcon#about to clear, iclass 28 cls_cnt 0 2006.196.08:31:32.56#ibcon#cleared, iclass 28 cls_cnt 0 2006.196.08:31:32.56$vc4f8/vabw=wide 2006.196.08:31:32.56#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.196.08:31:32.56#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.196.08:31:32.56#ibcon#ireg 8 cls_cnt 0 2006.196.08:31:32.56#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.196.08:31:32.56#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.196.08:31:32.56#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.196.08:31:32.56#ibcon#enter wrdev, iclass 30, count 0 2006.196.08:31:32.56#ibcon#first serial, iclass 30, count 0 2006.196.08:31:32.56#ibcon#enter sib2, iclass 30, count 0 2006.196.08:31:32.56#ibcon#flushed, iclass 30, count 0 2006.196.08:31:32.56#ibcon#about to write, iclass 30, count 0 2006.196.08:31:32.56#ibcon#wrote, iclass 30, count 0 2006.196.08:31:32.56#ibcon#about to read 3, iclass 30, count 0 2006.196.08:31:32.58#ibcon#read 3, iclass 30, count 0 2006.196.08:31:32.58#ibcon#about to read 4, iclass 30, count 0 2006.196.08:31:32.58#ibcon#read 4, iclass 30, count 0 2006.196.08:31:32.58#ibcon#about to read 5, iclass 30, count 0 2006.196.08:31:32.58#ibcon#read 5, iclass 30, count 0 2006.196.08:31:32.58#ibcon#about to read 6, iclass 30, count 0 2006.196.08:31:32.58#ibcon#read 6, iclass 30, count 0 2006.196.08:31:32.58#ibcon#end of sib2, iclass 30, count 0 2006.196.08:31:32.58#ibcon#*mode == 0, iclass 30, count 0 2006.196.08:31:32.58#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.196.08:31:32.58#ibcon#[25=BW32\r\n] 2006.196.08:31:32.58#ibcon#*before write, iclass 30, count 0 2006.196.08:31:32.58#ibcon#enter sib2, iclass 30, count 0 2006.196.08:31:32.58#ibcon#flushed, iclass 30, count 0 2006.196.08:31:32.58#ibcon#about to write, iclass 30, count 0 2006.196.08:31:32.58#ibcon#wrote, iclass 30, count 0 2006.196.08:31:32.58#ibcon#about to read 3, iclass 30, count 0 2006.196.08:31:32.61#ibcon#read 3, iclass 30, count 0 2006.196.08:31:32.61#ibcon#about to read 4, iclass 30, count 0 2006.196.08:31:32.61#ibcon#read 4, iclass 30, count 0 2006.196.08:31:32.61#ibcon#about to read 5, iclass 30, count 0 2006.196.08:31:32.61#ibcon#read 5, iclass 30, count 0 2006.196.08:31:32.61#ibcon#about to read 6, iclass 30, count 0 2006.196.08:31:32.61#ibcon#read 6, iclass 30, count 0 2006.196.08:31:32.61#ibcon#end of sib2, iclass 30, count 0 2006.196.08:31:32.61#ibcon#*after write, iclass 30, count 0 2006.196.08:31:32.61#ibcon#*before return 0, iclass 30, count 0 2006.196.08:31:32.61#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.196.08:31:32.61#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.196.08:31:32.61#ibcon#about to clear, iclass 30 cls_cnt 0 2006.196.08:31:32.61#ibcon#cleared, iclass 30 cls_cnt 0 2006.196.08:31:32.61$vc4f8/vbbw=wide 2006.196.08:31:32.61#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.196.08:31:32.61#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.196.08:31:32.61#ibcon#ireg 8 cls_cnt 0 2006.196.08:31:32.61#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.196.08:31:32.68#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.196.08:31:32.68#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.196.08:31:32.68#ibcon#enter wrdev, iclass 32, count 0 2006.196.08:31:32.68#ibcon#first serial, iclass 32, count 0 2006.196.08:31:32.68#ibcon#enter sib2, iclass 32, count 0 2006.196.08:31:32.68#ibcon#flushed, iclass 32, count 0 2006.196.08:31:32.68#ibcon#about to write, iclass 32, count 0 2006.196.08:31:32.68#ibcon#wrote, iclass 32, count 0 2006.196.08:31:32.68#ibcon#about to read 3, iclass 32, count 0 2006.196.08:31:32.70#ibcon#read 3, iclass 32, count 0 2006.196.08:31:32.70#ibcon#about to read 4, iclass 32, count 0 2006.196.08:31:32.70#ibcon#read 4, iclass 32, count 0 2006.196.08:31:32.70#ibcon#about to read 5, iclass 32, count 0 2006.196.08:31:32.70#ibcon#read 5, iclass 32, count 0 2006.196.08:31:32.70#ibcon#about to read 6, iclass 32, count 0 2006.196.08:31:32.70#ibcon#read 6, iclass 32, count 0 2006.196.08:31:32.70#ibcon#end of sib2, iclass 32, count 0 2006.196.08:31:32.70#ibcon#*mode == 0, iclass 32, count 0 2006.196.08:31:32.70#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.196.08:31:32.70#ibcon#[27=BW32\r\n] 2006.196.08:31:32.70#ibcon#*before write, iclass 32, count 0 2006.196.08:31:32.70#ibcon#enter sib2, iclass 32, count 0 2006.196.08:31:32.70#ibcon#flushed, iclass 32, count 0 2006.196.08:31:32.70#ibcon#about to write, iclass 32, count 0 2006.196.08:31:32.70#ibcon#wrote, iclass 32, count 0 2006.196.08:31:32.70#ibcon#about to read 3, iclass 32, count 0 2006.196.08:31:32.73#ibcon#read 3, iclass 32, count 0 2006.196.08:31:32.73#ibcon#about to read 4, iclass 32, count 0 2006.196.08:31:32.73#ibcon#read 4, iclass 32, count 0 2006.196.08:31:32.73#ibcon#about to read 5, iclass 32, count 0 2006.196.08:31:32.73#ibcon#read 5, iclass 32, count 0 2006.196.08:31:32.73#ibcon#about to read 6, iclass 32, count 0 2006.196.08:31:32.73#ibcon#read 6, iclass 32, count 0 2006.196.08:31:32.73#ibcon#end of sib2, iclass 32, count 0 2006.196.08:31:32.73#ibcon#*after write, iclass 32, count 0 2006.196.08:31:32.73#ibcon#*before return 0, iclass 32, count 0 2006.196.08:31:32.73#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.196.08:31:32.73#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.196.08:31:32.73#ibcon#about to clear, iclass 32 cls_cnt 0 2006.196.08:31:32.73#ibcon#cleared, iclass 32 cls_cnt 0 2006.196.08:31:32.73$4f8m12a/ifd4f 2006.196.08:31:32.73$ifd4f/lo= 2006.196.08:31:32.73$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.196.08:31:32.73$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.196.08:31:32.73$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.196.08:31:32.73$ifd4f/patch= 2006.196.08:31:32.73$ifd4f/patch=lo1,a1,a2,a3,a4 2006.196.08:31:32.73$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.196.08:31:32.73$ifd4f/patch=lo3,a5,a6,a7,a8 2006.196.08:31:32.73$4f8m12a/"form=m,16.000,1:2 2006.196.08:31:32.73$4f8m12a/"tpicd 2006.196.08:31:32.73$4f8m12a/echo=off 2006.196.08:31:32.73$4f8m12a/xlog=off 2006.196.08:31:32.73:!2006.196.08:32:00 2006.196.08:31:35.13#trakl#Source acquired 2006.196.08:31:36.13#flagr#flagr/antenna,acquired 2006.196.08:32:00.00:preob 2006.196.08:32:01.13/onsource/TRACKING 2006.196.08:32:01.13:!2006.196.08:32:10 2006.196.08:32:10.00:data_valid=on 2006.196.08:32:10.00:midob 2006.196.08:32:10.13/onsource/TRACKING 2006.196.08:32:10.13/wx/28.70,1004.3,93 2006.196.08:32:10.26/cable/+6.3401E-03 2006.196.08:32:11.35/va/01,08,usb,yes,29,31 2006.196.08:32:11.35/va/02,07,usb,yes,29,30 2006.196.08:32:11.35/va/03,06,usb,yes,31,31 2006.196.08:32:11.35/va/04,07,usb,yes,30,32 2006.196.08:32:11.35/va/05,07,usb,yes,33,34 2006.196.08:32:11.35/va/06,06,usb,yes,32,31 2006.196.08:32:11.35/va/07,06,usb,yes,32,32 2006.196.08:32:11.35/va/08,07,usb,yes,30,30 2006.196.08:32:11.58/valo/01,532.99,yes,locked 2006.196.08:32:11.58/valo/02,572.99,yes,locked 2006.196.08:32:11.58/valo/03,672.99,yes,locked 2006.196.08:32:11.58/valo/04,832.99,yes,locked 2006.196.08:32:11.58/valo/05,652.99,yes,locked 2006.196.08:32:11.58/valo/06,772.99,yes,locked 2006.196.08:32:11.58/valo/07,832.99,yes,locked 2006.196.08:32:11.58/valo/08,852.99,yes,locked 2006.196.08:32:12.67/vb/01,04,usb,yes,29,27 2006.196.08:32:12.67/vb/02,04,usb,yes,30,32 2006.196.08:32:12.67/vb/03,04,usb,yes,27,31 2006.196.08:32:12.67/vb/04,04,usb,yes,28,28 2006.196.08:32:12.67/vb/05,04,usb,yes,26,30 2006.196.08:32:12.67/vb/06,04,usb,yes,27,30 2006.196.08:32:12.67/vb/07,04,usb,yes,29,29 2006.196.08:32:12.67/vb/08,04,usb,yes,27,30 2006.196.08:32:12.90/vblo/01,632.99,yes,locked 2006.196.08:32:12.90/vblo/02,640.99,yes,locked 2006.196.08:32:12.90/vblo/03,656.99,yes,locked 2006.196.08:32:12.90/vblo/04,712.99,yes,locked 2006.196.08:32:12.90/vblo/05,744.99,yes,locked 2006.196.08:32:12.90/vblo/06,752.99,yes,locked 2006.196.08:32:12.90/vblo/07,734.99,yes,locked 2006.196.08:32:12.90/vblo/08,744.99,yes,locked 2006.196.08:32:13.05/vabw/8 2006.196.08:32:13.20/vbbw/8 2006.196.08:32:13.33/xfe/off,on,15.5 2006.196.08:32:13.71/ifatt/23,28,28,28 2006.196.08:32:14.07/fmout-gps/S +3.36E-07 2006.196.08:32:14.11:!2006.196.08:33:10 2006.196.08:33:10.00:data_valid=off 2006.196.08:33:10.00:postob 2006.196.08:33:10.11/cable/+6.3386E-03 2006.196.08:33:10.11/wx/28.68,1004.3,93 2006.196.08:33:11.07/fmout-gps/S +3.37E-07 2006.196.08:33:11.07:checkk5last 2006.196.08:33:11.07&checkk5last/chk_obsdata=1 2006.196.08:33:11.08&checkk5last/chk_obsdata=2 2006.196.08:33:11.08&checkk5last/chk_obsdata=3 2006.196.08:33:11.08&checkk5last/chk_obsdata=4 2006.196.08:33:11.09&checkk5last/k5log=1 2006.196.08:33:11.09&checkk5last/k5log=2 2006.196.08:33:11.09&checkk5last/k5log=3 2006.196.08:33:11.09&checkk5last/k5log=4 2006.196.08:33:11.10&checkk5last/obsinfo 2006.196.08:33:11.48/chk_obsdata//k5ts1/T1960832??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.08:33:11.86/chk_obsdata//k5ts2/T1960832??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.08:33:12.22/chk_obsdata//k5ts3/T1960832??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.08:33:12.59/chk_obsdata//k5ts4/T1960832??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.196.08:33:13.29/k5log//k5ts1_log_newline 2006.196.08:33:13.98/k5log//k5ts2_log_newline 2006.196.08:33:14.67/k5log//k5ts3_log_newline 2006.196.08:33:15.36/k5log//k5ts4_log_newline 2006.196.08:33:15.38/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.196.08:33:15.38:"sched_end 2006.196.08:33:15.38:source=idle 2006.196.08:33:16.14:stow 2006.196.08:33:16.14&stow/source=idle 2006.196.08:33:16.14&stow/"this is stow command. 2006.196.08:33:16.14&stow/antenna=m3 2006.196.08:33:16.14#flagr#flagr/antenna,new-source 2006.196.08:33:19.01:!+10m 2006.196.08:43:19.02:standby 2006.196.08:43:20.01:sy=cp /usr2/log/k06196ts.log /usr2/log_backup/ 2006.196.08:43:20.09:log=k06197ts